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<h4>UNIVERSITY PARTNERS</h4><p class="text-left">Many Universities and Research Centers are designing complex new hardware using High-Level Synthesis. Below are some research partners and the various designs that they have created in part by leveraging libraries from <a href="https://hlslibs.org/">HLSLIBS.org</a>.
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<h4>FlexASR (Harvard)</h4><p class="text-left"><a href="https://github.com/harvard-acc/FlexASR">FlexASR Github</a><br><br>
Paper: <a href="https://ieeexplore.ieee.org/document/9366062">A 25mm2 SoC for IoT Devices with 18ms Noise-Robust Speech-to-Text Latency via Bayesian Speech Denoising and Attention-Based Sequence-to-Sequence DNN Speech Recognition in 16nm FinFET</a><br><br>
CHIPKIT Talk: <a href="https://www.youtube.com/watch?v=MNy9BWyuPwE">Closing the Algorithm/Hardware Design and Verification Loop with Speed via HLS</a><br><br>
International Solid-State Circuits Conference Slides: <a href="https://scholar.harvard.edu/files/ttambe/files/tambe_isscc_2021_presentation.pdf">A 25mm2 SoC for IoT Devices with 18ms Noise-Robust
Speech-to-Text Latency via Bayesian Speech
Denoising and Attention-Based Sequence-to-Sequence
DNN Speech Recognition in 16nm FinFET
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<h4>EdgeBert (Harvard)</h4><p class="text-left"><a href="https://github.com/harvard-acc/EdgeBERT">EdgeBERT Github</a><br><br>
MICRO 2021 Paper: <a href="https://scholar.harvard.edu/files/ttambe/files/edgebert_nlp_micro_2021.pdf">EdgeBERT: Sentence-Level Energy Optimizations for Latency-Aware Multi-Task NLP Inference</a>
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<h4>DNN Accelerator (Stanford)</h4><p class="text-left"><a href="https://code.stanford.edu/kprabhu7/dnn-accelerator">DNN Accelerator Code Files</a><br><br>
2021 Symposium on VLSI Circuits Paper: <a href="https://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=9492347&tag=1">CHIMERA: A 0.92 TOPS, 2.2 TOPS/W Edge AI Accelerator with
2 MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference </a><br><br>
Webinar: <a href="https://event.on24.com/wcc/r/3340763/3F85299E7314D4B30F0E926A4E8E13C4?partnerref=HLSLibs">Stanford University: Edge ML Accelerator SoC Design Using Catapult HLS</a>
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<h4>DUTH (cache-coherent NoC)</h4><p class="text-left"><a href="https://github.com/ic-lab-duth/NoCpad">NoC Github</a>
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