From 30c7648e3a7dd860128fa2b1dd6f9824e3cfb702 Mon Sep 17 00:00:00 2001 From: ixgbe <1113177880@qq.com> Date: Fri, 5 Dec 2025 15:44:03 +0800 Subject: [PATCH 1/3] ggml-cpu: add ggml_thread_cpu_relax with Zihintpause support Signed-off-by: Wang Yang --- ggml/src/ggml-cpu/ggml-cpu.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/ggml/src/ggml-cpu/ggml-cpu.c b/ggml/src/ggml-cpu/ggml-cpu.c index 8507557267a..b468b115a18 100644 --- a/ggml/src/ggml-cpu/ggml-cpu.c +++ b/ggml/src/ggml-cpu/ggml-cpu.c @@ -490,6 +490,15 @@ static inline void ggml_thread_cpu_relax(void) { static inline void ggml_thread_cpu_relax(void) { _mm_pause(); } +#elif defined(__riscv) +static inline void ggml_thread_cpu_relax(void) { + #ifdef __riscv_zihintpause + __asm__ __volatile__ ("pause"); + #else + /* Encoding of the pause instruction */ + __asm__ __volatile__ (".4byte 0x100000F"); + #endif +} #else static inline void ggml_thread_cpu_relax(void) {;} #endif From 9c741a7aaa427bcdd0b1f10e6145ffd732eee123 Mon Sep 17 00:00:00 2001 From: ixgbe <1113177880@qq.com> Date: Mon, 8 Dec 2025 10:35:21 +0800 Subject: [PATCH 2/3] cmake: enable RISC-V zihintpause extension for Spacemit builds --- .github/workflows/build-linux-cross.yml | 1 + docs/build-riscv64-spacemit.md | 1 + ggml/CMakeLists.txt | 1 + ggml/src/ggml-cpu/CMakeLists.txt | 3 +++ 4 files changed, 6 insertions(+) diff --git a/.github/workflows/build-linux-cross.yml b/.github/workflows/build-linux-cross.yml index 36201281f00..c2c6ea12ae4 100644 --- a/.github/workflows/build-linux-cross.yml +++ b/.github/workflows/build-linux-cross.yml @@ -291,6 +291,7 @@ jobs: -DGGML_RVV=ON \ -DGGML_RV_ZFH=ON \ -DGGML_RV_ZICBOP=ON \ + -DGGML_RV_ZIHINTPAUSE=ON \ -DRISCV64_SPACEMIT_IME_SPEC=RISCV64_SPACEMIT_IME1 \ -DCMAKE_TOOLCHAIN_FILE=${PWD}/cmake/riscv64-spacemit-linux-gnu-gcc.cmake diff --git a/docs/build-riscv64-spacemit.md b/docs/build-riscv64-spacemit.md index eaa65325465..79bd4de63af 100644 --- a/docs/build-riscv64-spacemit.md +++ b/docs/build-riscv64-spacemit.md @@ -19,6 +19,7 @@ cmake -B build \ -DGGML_RVV=ON \ -DGGML_RV_ZFH=ON \ -DGGML_RV_ZICBOP=ON \ + -DGGML_RV_ZIHINTPAUSE=ON \ -DRISCV64_SPACEMIT_IME_SPEC=RISCV64_SPACEMIT_IME1 \ -DCMAKE_TOOLCHAIN_FILE=${PWD}/cmake/riscv64-spacemit-linux-gnu-gcc.cmake \ -DCMAKE_INSTALL_PREFIX=build/installed diff --git a/ggml/CMakeLists.txt b/ggml/CMakeLists.txt index 0ccd901921d..4e7c44d2aa4 100644 --- a/ggml/CMakeLists.txt +++ b/ggml/CMakeLists.txt @@ -168,6 +168,7 @@ option(GGML_RVV "ggml: enable rvv" ON) option(GGML_RV_ZFH "ggml: enable riscv zfh" ON) option(GGML_RV_ZVFH "ggml: enable riscv zvfh" ON) option(GGML_RV_ZICBOP "ggml: enable riscv zicbop" ON) +option(GGML_RV_ZIHINTPAUSE "ggml: enable riscv zihintpause " ON) option(GGML_XTHEADVECTOR "ggml: enable xtheadvector" OFF) option(GGML_VXE "ggml: enable vxe" ${GGML_NATIVE}) diff --git a/ggml/src/ggml-cpu/CMakeLists.txt b/ggml/src/ggml-cpu/CMakeLists.txt index 7e53a57b7b0..fc31089f3e2 100644 --- a/ggml/src/ggml-cpu/CMakeLists.txt +++ b/ggml/src/ggml-cpu/CMakeLists.txt @@ -469,6 +469,9 @@ function(ggml_add_cpu_backend_variant_impl tag_name) if (GGML_RV_ZICBOP) string(APPEND MARCH_STR "_zicbop") endif() + if (GGML_RV_ZIHINTPAUSE) + string(APPEND MARCH_STR "_zihintpause") + endif() list(APPEND ARCH_FLAGS "-march=${MARCH_STR}" -mabi=lp64d) else() # Begin with the lowest baseline From 5b83384aadfa519f93e133f733c4f2ebeb23bb48 Mon Sep 17 00:00:00 2001 From: ixgbe <1113177880@qq.com> Date: Mon, 8 Dec 2025 10:40:55 +0800 Subject: [PATCH 3/3] readme : add ZIHINTPAUSE support for RISC-V --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index 2e44ae7d0c7..b52996135b9 100644 --- a/README.md +++ b/README.md @@ -61,7 +61,7 @@ range of hardware - locally and in the cloud. - Plain C/C++ implementation without any dependencies - Apple silicon is a first-class citizen - optimized via ARM NEON, Accelerate and Metal frameworks - AVX, AVX2, AVX512 and AMX support for x86 architectures -- RVV, ZVFH, ZFH and ZICBOP support for RISC-V architectures +- RVV, ZVFH, ZFH, ZICBOP and ZIHINTPAUSE support for RISC-V architectures - 1.5-bit, 2-bit, 3-bit, 4-bit, 5-bit, 6-bit, and 8-bit integer quantization for faster inference and reduced memory use - Custom CUDA kernels for running LLMs on NVIDIA GPUs (support for AMD GPUs via HIP and Moore Threads GPUs via MUSA) - Vulkan and SYCL backend support