@@ -165,9 +165,6 @@ extern bool riscv_epilogue_uses (unsigned int);
165165extern bool riscv_can_use_return_insn (void );
166166extern rtx riscv_function_value (const_tree, const_tree, enum machine_mode);
167167extern bool riscv_store_data_bypass_p (rtx_insn *, rtx_insn *);
168- extern bool arcv_mpy_1c_bypass_p (rtx_insn *, rtx_insn *);
169- extern bool arcv_mpy_2c_bypass_p (rtx_insn *, rtx_insn *);
170- extern bool arcv_mpy_10c_bypass_p (rtx_insn *, rtx_insn *);
171168extern rtx riscv_gen_gpr_save_insn (struct riscv_frame_info *);
172169extern bool riscv_gpr_save_operation_p (rtx);
173170extern void riscv_reinit (void );
@@ -224,6 +221,24 @@ extern bool riscv_expand_block_compare (rtx, rtx, rtx, rtx);
224221extern bool riscv_expand_block_move (rtx, rtx, rtx);
225222extern bool riscv_expand_block_clear (rtx, rtx);
226223
224+ #ifndef GCC_RISCV_ARCV_H
225+ #define GCC_RISCV_ARCV_H
226+
227+ /* Routines implemented in arcv.cc. */
228+ extern bool arcv_mpy_1c_bypass_p (rtx_insn *, rtx_insn *);
229+ extern bool arcv_mpy_2c_bypass_p (rtx_insn *, rtx_insn *);
230+ extern bool arcv_mpy_10c_bypass_p (rtx_insn *, rtx_insn *);
231+ extern bool arcv_can_issue_more_p (int , int );
232+ extern int arcv_sched_variable_issue (rtx_insn *, int );
233+ extern bool arcv_macro_fusion_pair_p (rtx_insn *, rtx_insn *);
234+ extern void arcv_sched_init (void );
235+ extern int arcv_sched_reorder2 (rtx_insn **, int *);
236+ extern int arcv_sched_adjust_priority (rtx_insn *, int );
237+ extern int arcv_sched_adjust_cost (rtx_insn *, int , int );
238+ extern void arcv_sched_fusion_priority (rtx_insn *, int , int *, int *);
239+
240+ #endif /* GCC_RISCV_ARCV_H */
241+
227242/* Information about one CPU we know about. */
228243struct riscv_cpu_info {
229244 /* This CPU's canonical name. */
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