replace spdlog::trace with SPDLOG_TRACE that can be disabled at compile time

Author: fogInSingularity

flags/CMakeLists.txt

@@ -68,3 +68,7 @@ target_link_options(sim-flags
         >
 )
 
+target_compile_definitions(sim-flags INTERFACE
+    $<$<CONFIG:Release>:SPDLOG_ACTIVE_LEVEL=SPDLOG_LEVEL_INFO>
+    $<$<CONFIG:Debug>:SPDLOG_ACTIVE_LEVEL=SPDLOG_LEVEL_TRACE>
+)

src/helpers/include/helpers/trace_calls.hpp

@@ -7,7 +7,7 @@
 
 namespace hlp {
 
-inline void trace_call(std::source_location loc = std::source_location::current()) {
+inline void trace_call([[maybe_unused]] std::source_location loc = std::source_location::current()) {
 #if !defined(NDEBUG)
     // spdlog::debug("Function call: {}, {}:{}", loc.function_name(), loc.file_name(), loc.line());
     spdlog::debug("Function call: {}", loc.function_name());

src/isa/include/isa/rv_insn.hpp

@@ -37,7 +37,7 @@ class RvInsn {
         constexpr uint32_t kRdShift = 7;
         constexpr uint32_t kRdMask  = 0x1Fu;
         auto rd = (raw_insn_ >> kRdShift) & kRdMask;
-        spdlog::trace("Rd(): rd = {}", rd);
+        SPDLOG_TRACE("Rd(): rd = {}", rd);
         return rd;
     }
 
@@ -51,7 +51,7 @@ class RvInsn {
         constexpr uint32_t kRs1Shift = 15;
         constexpr uint32_t kRs1Mask  = 0x1Fu;
         auto rs1 = (raw_insn_ >> kRs1Shift) & kRs1Mask;
-        spdlog::trace("Rs1(): rs1 = {}", rs1);
+        SPDLOG_TRACE("Rs1(): rs1 = {}", rs1);
         return rs1;
     }
 
@@ -78,7 +78,7 @@ class RvInsn {
         constexpr unsigned kImmBits  = 12;
         uint32_t imm = raw_insn_ >> kImmShift;
         auto sext = SignExtend(imm, kImmBits);
-        spdlog::trace("i immid: {}", sext);
+        SPDLOG_TRACE("i immid: {}", sext);
         return sext;
     }
 
@@ -139,7 +139,7 @@ class RvInsn {
         );
 
         auto sext = SignExtend(imm, kImmBits);
-        spdlog::trace("j immid: {}", sext);
+        SPDLOG_TRACE("j immid: {}", sext);
         return sext;
     }
 };} // namespace isa

src/isa/source/ext_i_cb.cpp

@@ -18,9 +18,7 @@ namespace {
 
 constexpr uint32_t ArithmRightShift(uint32_t x, unsigned shift) {
     constexpr unsigned num_bits = sizeof(x) * CHAR_BIT;
-    constexpr uint32_t one = uint32_t{1};
     constexpr unsigned sign_bit = num_bits - 1;
-    constexpr uint32_t sign_bit_mask = one << sign_bit;
     constexpr uint32_t all_ones = std::numeric_limits<uint32_t>::max();
     constexpr uint32_t zero = uint32_t{0};
 

src/sim/include/sim/rv_sim.hpp

@@ -63,7 +63,7 @@ class RVSim {
     void SetXReg(size_t index, isa::Register value) {
         assert(index < isa::kNumXRegisters);
 
-        spdlog::trace("set x reg: index {}, value {}", index, value);
+        SPDLOG_TRACE("set x reg: index {}, value {}", index, value);
 
         if (index == hlp::FromEnum(isa::XRegAlias::zero)) { return; }
 
@@ -88,7 +88,7 @@ class RVSim {
 
     void SetFReg(size_t index, isa::FRegister value) {
         assert(index < isa::kNumFRegisters);
-        spdlog::trace("set f reg: index {}, value {:#x}", index, value.v);
+        SPDLOG_TRACE("set f reg: index {}, value {:#x}", index, value.v);
 
         fregs_[index] = value;
     }
@@ -97,12 +97,12 @@ class RVSim {
         assert(index < isa::kNumFRegisters);
 
         auto fval = fregs_[index];
-        spdlog::trace("get f reg: index {}, value {:#x}", index, fval.v);
+        SPDLOG_TRACE("get f reg: index {}, value {:#x}", index, fval.v);
         return fval;
     }
 
     void SetCSR(size_t index, isa::Register value) {
-        spdlog::debug("set csr called: index {}, value {}", index, value);
+        SPDLOG_TRACE("set csr called: index {}, value {}", index, value);
 
         switch (hlp::ToEnum<isa::CSR>(index)) {
             case isa::CSR::fflags:
@@ -125,7 +125,7 @@ class RVSim {
     }
 
     isa::Register GetCSR(size_t index) {
-        spdlog::debug("get csr called: index {}", index);
+        SPDLOG_TRACE("get csr called: index {}", index);
 
         switch (hlp::ToEnum<isa::CSR>(index)) {
             case isa::CSR::fflags:
@@ -165,9 +165,9 @@ class RVSim {
     }
 
     void Trace() {
-        spdlog::trace("trace sim:");
+        SPDLOG_TRACE("trace sim:");
         for (size_t i = 0; i < isa::kNumXRegisters; i++) {
-            spdlog::trace("Reg {}: {}", i, xregs_[i]);
+            SPDLOG_TRACE("Reg {}: {}", i, xregs_[i]);
         }
     }
 };

src/sim/source/decode.cpp

@@ -25,6 +25,7 @@ constexpr DecodeTable InsnDecodeTable {{
 #undef MNEMONIC
 }};
 
+// FIXME fix decode
 isa::InsnMnemonic Decode(isa::UndecodedInsn insn) {
     for (auto& entry: InsnDecodeTable) {
         if ((insn & entry.mask) == entry.match) {

src/sim/source/memory.cpp

@@ -18,7 +18,7 @@ bool IsAddrInSegment(isa::Address addr, const MemorySegm& segm);
 } // namespace
 
 uint32_t Memory::LoadU32(isa::Address addr) {
-    spdlog::trace("Memory u32 read: addr {}", addr);
+    SPDLOG_TRACE("Memory u32 read: addr {}", addr);
 
     for (const auto& segm: memory_) {
         if (!IsAddrInSegment(addr, segm)) { continue; }

src/sim/source/rv_sim.cpp

@@ -18,10 +18,10 @@ int RVSim::Execute() {
         // Trace();
 
         isa::UndecodedInsn undecoded_insn = memory_.Fetch(ip_);
-        spdlog::trace("undecoded insn: {:#04x}", undecoded_insn);
+        SPDLOG_TRACE("undecoded insn: {:#04x}", undecoded_insn);
 
         isa::InsnMnemonic mnem = Decode(undecoded_insn);
-        spdlog::trace("Mnemonic: {}", isa::MnemonicToStr(mnem));
+        SPDLOG_TRACE("Mnemonic: {}", isa::MnemonicToStr(mnem));
         if (mnem == isa::InsnMnemonic::kInvalid) {
             throw hlp::TraceableException{"Unkown instuction encountered"};
         }

tests/compute_heavy_test/api.s

@@ -0,0 +1,27 @@
+.global read
+.global write
+.global exit
+.global _start
+
+.section .text
+
+read:
+    li a7, 63
+    ecall
+    ret
+
+write:
+    li a7, 64
+    ecall
+    ret
+
+exit:
+    li a7, 93
+    ecall
+
+_start:
+    # passing argc, argv[]
+    lw a0, 0(sp)
+    addi a1, sp, 4 # 8 for 64-bit mode
+    call main
+    j exit

tests/compute_heavy_test/build.sh

@@ -1,20 +1,20 @@
 #!/bin/bash
 
 riscv64-unknown-elf-gcc \
-    -march=rv32im \
-    -mabi=ilp32 \
+    -march=rv32imf_zbb \
+    -mabi=ilp32f \
     -nostdlib \
     -ffreestanding \
     $1 -o $1.s -S -O2
 
 riscv64-unknown-elf-as \
-    -march=rv32im \
-    -mabi=ilp32 \
+    -march=rv32imf_zbb \
+    -mabi=ilp32f \
     -o $1.o $1.s
 
 riscv64-unknown-elf-as \
-    -march=rv32im \
-    -mabi=ilp32 \
+    -march=rv32imf_zbb \
+    -mabi=ilp32f \
     -o api.o api.s
 
 riscv64-unknown-elf-ld \