Makefile

export CLOCK_PERIOD = 15.0

VCS = vcs +prof-kdb -sverilog -debug_access+all+reverse +incdir+lib/ \
	  -Mdir=build/csrc +define+CLOCK_PERIOD=$(CLOCK_PERIOD)

RUN_VERDI = -gui=verdi -verdi_opts "-ultra"

SYNTH_SCRIPT = 470synth.tcl

STD_CELLS = /afs/umich.edu/class/eecs470/lib/verilog/lec25dscc25.v

vpath %.verdi $(shell find build -type d)
vpath %.sv $(shell find rtl test -type d)
vpath %_test.sv $(shell find test -type d)
vpath %.vg $(shell find syn -type d)

# Temporarily remove some sources from compilation bc syntax errors
#SOURCES = $(shell find rtl/ lib/ -name *.sv -o -name *.svh)
SOURCES = $(shell find lib/ -name *.sv -o -name *.svh) \
		  rtl/neuron_IF_one_adder.sv \
		  rtl/layer_IF_one_adder.sv \
		  rtl/fiNN_IF_one_adder.sv \
		  rtl/output_digit.sv


LIB = $(shell find lib/ -name *.sv -o -name *.svh)

# Behavioral Simulation 
# Usage: make example.out
%.out: %.simv
	cd build; \
	./$*.simv | tee $*.out

%.simv: %_test.sv %.sv
	mkdir -p build; \
	$(VCS) $< $(SOURCES) $(LIB) -o build/$*.simv

# Verdi
# Usage: make example.verdi
%.verdi: %.simv
	./build/$*.simv $(RUN_VERDI)

# Synthesis
# Usage: make example.syn
%.syn: %.sv
	cd syn && \
	MODULE=$* SOURCES="$(SOURCES)" \
	dc_shell-t -f $(SYNTH_SCRIPT) | tee $*_syn.out

# Module level sim on synthesized netlist
%.syn.test: %.syn.simv
	cd build; \
	./$*.syn.simv | tee $*.syn.out

# Simv from synthesized netlist (make sure to run module.synth first)
%.syn.simv: %_test.sv %.vg | build
	$(VCS) $^ $(STD_CELLS) \
		-o build/$@

clean: clean_sim clean_syn clean_verdi
	rm -rf *.daidir
	rm -f verdi_config_file

clean_verdi:
	rm -rf novas* ucli.key verdiLog inter.fsdb

clean_sim:
	rm -rf build

clean_syn:
	cd syn && rm -rf *.vg *_svsim.sv *.res *.rep *.ddc *.chk *.syn *.out \
		*.db *.svf *.mr *.pvl command.log *.rpt *.v *.sdc *.sdf *output* alib-52\
		cksum_dir