Right now the GEM_AMC.SLOW_CONTROL.SCA.CTRL.TTC_HARD_RESET_EN defaults to 0x1 for FW versions 3.X.Y.
Whenever a TTC hard reset is sent by CMS in P5 this is causing an SCA reset which results in lost firmware on the OH. Can this above register be defaulted to 0x0?
Right now the
GEM_AMC.SLOW_CONTROL.SCA.CTRL.TTC_HARD_RESET_ENdefaults to0x1for FW versions3.X.Y.Whenever a TTC hard reset is sent by CMS in P5 this is causing an SCA reset which results in lost firmware on the OH. Can this above register be defaulted to
0x0?