Add C5 support (#541)

* feat: Add C5 support

* docs: Add changelog

Author: SergioGasquez

CHANGELOG.md

@@ -8,6 +8,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 ## [Unreleased]
 
 ### Added
+- Add ESP32-C5 support (#541)
 
 ### Fixed
 

README.md

@@ -190,7 +190,7 @@ Options:
           With this option, espup will skip GCC installation (it will be handled by esp-idf-sys), hence you won't be able to build no_std applications.
 
   -t, --targets <TARGETS>
-          Comma or space separated list of targets [esp32,esp32c2,esp32c3,esp32c6,esp32h2,esp32s2,esp32s3,esp32p4,all]
+          Comma or space separated list of targets [esp32,esp32c2,esp32c3,esp32c5,esp32c6,esp32h2,esp32s2,esp32s3,esp32p4,all]
 
           [default: all]
 
@@ -260,7 +260,7 @@ Options:
           With this option, espup will skip GCC installation (it will be handled by esp-idf-sys), hence you won't be able to build no_std applications.
 
   -t, --targets <TARGETS>
-          Comma or space separated list of targets [esp32,esp32c2,esp32c3,esp32c6,esp32h2,esp32s2,esp32s3,all]
+          Comma or space separated list of targets [esp32,esp32c2,esp32c3,esp32c5,esp32c6,esp32h2,esp32s2,esp32s3,all]
 
           [default: all]
 

src/cli.rs

@@ -51,7 +51,7 @@ pub struct InstallOpts {
     /// With this option, espup will skip GCC installation (it will be handled by esp-idf-sys), hence you won't be able to build no_std applications.
     #[arg(short = 's', long)]
     pub std: bool,
-    /// Comma or space separated list of targets [esp32,esp32c2,esp32c3,esp32c6,esp32h2,esp32s2,esp32s3,esp32p4,all].
+    /// Comma or space separated list of targets [esp32,esp32c2,esp32c3,esp32c5,esp32c6,esp32h2,esp32s2,esp32s3,esp32p4,all].
     #[arg(short = 't', long, default_value = "all", value_parser = parse_targets)]
     pub targets: HashSet<Target>,
     /// Xtensa Rust toolchain version.

src/targets.rs

@@ -16,6 +16,8 @@ pub enum Target {
     /// RISC-V based single core
     ESP32C3,
     /// RISC-V based single core
+    ESP32C5,
+    /// RISC-V based single core
     ESP32C6,
     /// RISC-V based single core
     ESP32H2,
@@ -88,6 +90,7 @@ mod tests {
             Target::ESP32,
             Target::ESP32C2,
             Target::ESP32C3,
+            Target::ESP32C5,
             Target::ESP32C6,
             Target::ESP32H2,
             Target::ESP32S2,