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Fixes to top level includes for MISRA warnings
What's Wrong: * Lagging compliance issues * Missing documentation on several namespaces and files. How Was it Fixed (if not obvious): * Abide by compliance. What side effects does this have (could be none): * None Which builds did you run to make sure they build? [X] arm-none-eabi-gcc Cortex M4 [X] arm-none-eabi-gcc Cortex M7 [ ] (Apple) Native Clang [ ] (Apple) Homebrew GCC [X] (Apple) Homebrew LLVM How Do We Know and Can Show It's Fixed: * Doxygen generation * Unit Tests pass * Builds pass Which Unittest Series did you Check? [ ] (Apple) Native Clang [ ] (Apple) Homebrew GCC [X] (Apple) Homebrew LLVM Did this affect any on-target builds? If so which were tested? [ ] STM32F407VE board [ ] STM32H753ZI board
1 parent 8a90d44 commit 7e72cde

24 files changed

Lines changed: 288 additions & 182 deletions

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CMakePresets.json

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"name": "distcc",
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"hidden": true,
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"displayName": "Distributed Building Configuration",
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"description": "Configuration for distributed building using distcc",
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"description": "Configuration for distributed building using distcc-bare-metal-builder which has arm-none-eabi-gcc-13.x",
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"cacheVariables": {
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"CMAKE_C_COMPILER_LAUNCHER": "distcc",
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"CMAKE_CXX_COMPILER_LAUNCHER": "distcc"
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"DISTCC_VERBOSE": "0",
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"DISTCC_FALLBACK": "1",
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"DISTCC_SKIP_LOCAL_RETRY": "0",
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"DISTCC_DIR": "/tmp/distcc"
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"DISTCC_DIR": "/tmp/distcc",
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"PATH": "/Applications/ArmGNUToolchain/13.2.rel1/arm-none-eabi/bin:$penv{PATH}"
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}
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},
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{
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"hidden": false,
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"inherits": "on-host",
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"displayName": "Native Clang Toolchain",
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"description": "Uses the default clang in your path",
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"description": "Uses the default clang in your path (Apple Clang potentially)",
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"toolchainFile": "${sourceDir}/build-support/lib/cmake/native-clang.cmake"
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},
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{
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"name": "native-llvm",
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"hidden": false,
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"inherits": "on-host",
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"displayName": "Native LLVM Toolchain",
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"displayName": "Native LLVM Toolchain (Homebrew LLVM potentially)",
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"toolchainFile": "${sourceDir}/build-support/lib/cmake/native-llvm.cmake"
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}
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],
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{
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"name": "build-cortex-m4-gcc-arm-none-eabi",
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"inherits": "build-common",
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"targets": [
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"all",
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"docs"
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],
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"targets": "all",
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"configurePreset": "cortex-m4-gcc-arm-none-eabi"
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},
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{
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"name": "build-cortex-m7-gcc-arm-none-eabi",
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"inherits": "build-common",
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"targets": [
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"all",
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"docs"
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],
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"targets": "all",
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"configurePreset": "cortex-m7-gcc-arm-none-eabi"
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},
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{

documentation/Doxyfile

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WARN_FORMAT = "$file:$line: $text"
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WARN_LINE_FORMAT = at line $line of file $file
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WARN_LOGFILE =
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INPUT = README.md modules/ documentation/
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INPUT = README.md modules/ documentation/ include/ configurations/full/
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INPUT_ENCODING = UTF-8
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INPUT_FILE_ENCODING =
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FILE_PATTERNS = *.c *.cc *.cxx *.cxxm *.cpp *.cppm *.ccm *.c++ *.c++m *.java *.ii *.ixx *.ipp *.i++ *.inl *.idl *.ddl *.odl *.h *.hh *.hxx *.hpp *.h++ *.l *.cs *.d *.php *.php4 *.php5 *.phtml *.inc *.m *.markdown *.md *.mm *.dox *.py *.pyw *.f90 *.f95 *.f03 *.f08 *.f18 *.f *.for *.vhd *.vhdl *.ucf *.qsf *.ice
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RECURSIVE = YES
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EXCLUDE = vocabulary.txt cortex-m-registers.txt thumb2-mnemonics.txt commit.txt
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EXCLUDE_SYMLINKS = NO
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EXCLUDE_PATTERNS = */.git/* */.svn/* */.hg/* */CMakeFiles/* */_CPack_Packages/* DartConfiguration.tcl CMakeLists.txt CMakeCache.txt modules/*/demo/* modules/*/test/*
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EXCLUDE_PATTERNS = */.git/* */.svn/* */.hg/* */CMakeFiles/* */_CPack_Packages/* DartConfiguration.tcl CMakeLists.txt CMakeCache.txt modules/*/demo/* modules/*/test*/*
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EXCLUDE_SYMBOLS =
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EXAMPLE_PATH = modules/*/demo/*
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EXAMPLE_PATTERNS = *

documentation/cortex-m-modes.md

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# Processor Modes
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There are several "dimensions" to the Mode discussion.
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Cortex-M uses three independent axes of "modes" that often get conflated:
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* Privilege - Determines access in the MPU to protected regions of memory and to specific (co)processor instructions.
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* Stack - Stores data and frames on one of two stacks Main (stored in `MSP`) and Process (stored in `PSP`)
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* Execution - Code can be executed in either Handler (via any handler) or Thread (normal)
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* Privilege: access permissions for MPU regions and privileged system instructions.
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* Stack: which stack pointer is active for exception entry/return.
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* Execution: Thread mode (normal code) vs Handler mode (exceptions/interrupts).
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In this mix several concepts together with some disjointed parlance but the core notion is that when you are in the elevated Mode you'll be executing a `handler` which will be `privileged`, with it's context on `main` stack.
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These axes combine to define what is possible at any time.
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When you are in the non-elevated mode, you'll be in some `Thread` of execution, which will be `non-privileged` with it's context on the `process` stack.
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| Execution | Privilege | Stack pointer | What is possible |
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| --- | --- | --- | --- |
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| Thread | Privileged or Unprivileged | PSP or MSP (configurable) | Normal code; unprivileged thread cannot access protected regions or privileged instructions. |
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| Handler | Always Privileged | MSP (fixed) | Exception/ISR code with full privileged access. |
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When you call an `svc #IMM` in `Thread` mode, the processor will save it's state on the `Process` Stack and then swap to the `Main` stack and run a `handler` in `privileged` mode.
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Key rules:
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* Handler mode is always privileged and always uses the Main stack.
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* Thread mode can be privileged or unprivileged and can use either stack pointer.
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* Unprivileged thread code cannot switch to privileged; it must request service via exceptions.
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Typical flow:
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* Thread mode executes application code, often unprivileged on the Process stack.
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* An exception (IRQ, fault, or `svc #imm`) causes hardware to push the Thread context to the current stack, switch to the Main stack, and enter Handler mode as privileged.
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* Returning from the exception restores the prior Thread mode privilege and stack selection.
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Reset vector:
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* On reset, the core loads the initial MSP from the vector table at address 0x00000000 and then loads the Reset handler address from 0x00000004.
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* The Reset handler runs in Handler mode, privileged, using the Main stack.
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* Reset can be triggered by power-on reset, external reset pin, watchdog reset, software system reset (e.g., `SCB->AIRCR`), or brown-out conditions (device dependent).

documentation/stmf407ve_memory_map.md

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# STM32F407VE Memory Map
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(Generated w/ Copilot, so if there are issues, please file a bug report!)
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## Overview
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The STM32F407VE microcontroller features multiple memory regions optimized for different purposes. This document details the complete memory layout as defined by the linker scripts.

documentation/supervisor.md

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### How could/should it be used?
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* `IMM` - This could be the enumerated value of the "command" or some other indicator of calling convention.
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* The Registers are 32 bit values, but can be any 32 bit value (pointer, float, uint32_t, etc)
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* Returned values should not be pointers or references back to supervisor memory (which will be protected). Access to protected memory will fault.
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* Returned values should be system codes (if they can fit in a single uint32_t)
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* The Registers are 32 bit values, but can be any 32 bit value (pointer, float, uint32_t, etc) and should use `cortex::word` type.
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* Returned values should not be pointers or references back to supervisor memory (which will be protected). Access to protected memory from unprivileged code will fault.
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* Returned values should be system codes (if they can fit in a single `cortex::word`)
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### Usecases
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All `IMM` are just enumeration of commands. Parameters are ad-hoc. Returns are simple Status codes.
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`auto ret = foo(x, y, z, w);` becomes `auto ret = supervisor<FOO>(x, y, z, w);`, internally a switch cases handles `case FOO:` which knows to how reinterpret `arg0-arg3`. Things are added manually.
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`auto ret = foo(x, y, z, w);` becomes `auto ret = supervisor<FOO>(x, y, z, w);`, internally a switch cases handles `case FOO:` which knows to how reinterpret `arg0-arg3`. Things are added manually to the enumeration of `IMM` values.
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#### Pros
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#### Cons
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* Poor object oriented abstraction, hard to mock.
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* Lots of duplicated code.
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* Lots of duplicated, boilerplate code.
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### Option 2
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* Some repeated code over each different interface type
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* Some repeated boilerplate code over each different interface type
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### Option 3
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embedded-superloop.code-workspace

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"testMate.cpp.test.parallelExecutionOfExecutableLimit": 2,
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"cSpell.words": [
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"distcc"
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]
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],
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"cmake.configureOnOpen": false
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}
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}

include/compiler.hpp

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#define COMPILER_HPP_
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/// @file
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/// Contains compiler specific attributes and macros. These should be the only MACROS in the system due to how the attributes are different on
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/// @brief Contains compiler specific attributes and macros. These should be the only MACROS in the system due to how the attributes are different on
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/// different compilers.
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#if defined(__GNUC__) or defined(__clang__)
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/// @brief Defines a compiler-specific attribute
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#define ATTRIBUTE(x) __attribute__(x)
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#endif
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/// @def LINKER_SECTION
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/// @brief Places a variable or function in a specific linker section
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/// @def NAKED
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/// @brief Marks a function as naked, meaning it has no prologue/epilogue
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/// @def USED
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/// @brief Marks a variable or function as used, preventing the compiler from optimizing it away
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/// @def ALWAYS_INLINE
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/// @brief Marks a function as always inline, preventing the compiler from generating a separate function call
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/// @def ISR
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/// @brief Marks a function as an interrupt service routine. This applies several attributes to ensure the functions are used and do not have a
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/// prologue/epilogue.
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#if defined(UNITTEST)
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// Unit Testing on GCC/Clang typically will not need or want the on-target attributes defined as
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// they interfere with the normal operation of the unit tests.
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#define LINKER_SECTION(x)
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#define NAKED
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#define USED __attribute__((used))
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#define ALWAYS_INLINE
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#define ISR
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#elif (defined(__GNUC__) or defined(__clang__)) and defined(__arm__)
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// On GCC/Clang for ARM, define the attributes for the target
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#define LINKER_SECTION(x) ATTRIBUTE((used, section(x)))
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#define NAKED ATTRIBUTE((used, naked))
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#define USED ATTRIBUTE((used))
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#define PRIz "zu"
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#endif
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// clang-format off
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inline size_t operator""_Z( unsigned long long int value) {
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return size_t(value);
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/// @brief User-defined literal for size_t
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inline size_t operator""_Z(unsigned long long int value) {
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return static_cast<size_t>(value);
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}
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// clang-format on
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/// On 32 bit system the precision type that is passed around on the stack is a float, on 64 bit systems it is a double.
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#if defined(__SIZEOF_POINTER__) && __SIZEOF_POINTER__ == 8
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/// On 64 bit system the precision type that is passed around on the stack is a double.
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using precision = double;
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#else
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#else // 32 bit systems
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/// On 32 bit system the precision type that is passed around on the stack is a float.
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using precision = float;
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#endif
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/// A concept that requires the type to implement all the comparison operators
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template <typename TYPE>
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concept Comparible = requires(std::remove_reference_t<TYPE> const& t, std::remove_reference_t<TYPE> const& u) {
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concept Comparable = requires(std::remove_reference_t<TYPE> const& t, std::remove_reference_t<TYPE> const& u) {
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{ t < u } -> std::convertible_to<bool>;
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{ t <= u } -> std::convertible_to<bool>;
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{ t > u } -> std::convertible_to<bool>;

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