From 4f8fa1b0fcce93cbef3fd69df7d4cc65fdd62bd8 Mon Sep 17 00:00:00 2001
From: Daniel Kroening <dkr@amazon.com>
Date: Mon, 1 Dec 2025 19:06:30 -0800
Subject: [PATCH] SystemVerilog: test for time data type

---
 regression/verilog/data-types/time1.desc |  7 +++++++
 regression/verilog/data-types/time1.sv   | 12 ++++++++++++
 2 files changed, 19 insertions(+)
 create mode 100644 regression/verilog/data-types/time1.desc
 create mode 100644 regression/verilog/data-types/time1.sv

diff --git a/regression/verilog/data-types/time1.desc b/regression/verilog/data-types/time1.desc
new file mode 100644
index 000000000..18c3eae6b
--- /dev/null
+++ b/regression/verilog/data-types/time1.desc
@@ -0,0 +1,7 @@
+CORE
+time1.sv
+--bound -
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
diff --git a/regression/verilog/data-types/time1.sv b/regression/verilog/data-types/time1.sv
new file mode 100644
index 000000000..76116eeeb
--- /dev/null
+++ b/regression/verilog/data-types/time1.sv
@@ -0,0 +1,12 @@
+module main;
+
+  initial begin : some_block
+    time some_time;
+    some_time = 1;
+    assert(some_time == 1);
+    some_time++;
+    assert(some_time == 2);
+    assert($bits(some_time) == 64);
+  end
+
+endmodule