From 21ea5a4c43fbbf6fbc5a0c9a03adbdddc393633d Mon Sep 17 00:00:00 2001
From: Daniel Kroening <dkr@amazon.com>
Date: Thu, 20 Nov 2025 14:52:07 -0800
Subject: [PATCH] Verilog: KNOWNBUG test for typed parameter ports

---
 regression/verilog/modules/parameter_ports5.desc |  7 +++++++
 regression/verilog/modules/parameter_ports5.sv   | 12 ++++++++++++
 2 files changed, 19 insertions(+)
 create mode 100644 regression/verilog/modules/parameter_ports5.desc
 create mode 100644 regression/verilog/modules/parameter_ports5.sv

diff --git a/regression/verilog/modules/parameter_ports5.desc b/regression/verilog/modules/parameter_ports5.desc
new file mode 100644
index 000000000..645cd370c
--- /dev/null
+++ b/regression/verilog/modules/parameter_ports5.desc
@@ -0,0 +1,7 @@
+KNOWNBUG
+parameter_ports5.v
+
+^EXIT=0$
+^SIGNAL=0$
+--
+The type of the parameter is ignored.
diff --git a/regression/verilog/modules/parameter_ports5.sv b/regression/verilog/modules/parameter_ports5.sv
new file mode 100644
index 000000000..10b23ab48
--- /dev/null
+++ b/regression/verilog/modules/parameter_ports5.sv
@@ -0,0 +1,12 @@
+module sub #(parameter byte P = 0);
+
+  initial assert($bits(P) == 8);
+  initial assert(P == 2);
+
+endmodule
+
+module main;
+
+  sub #('h102) submodule();
+
+endmodule // main