From 31653d80bbf3129472053e2488fac056ed1b45ae Mon Sep 17 00:00:00 2001
From: Daniel Kroening <dkr@amazon.com>
Date: Mon, 17 Nov 2025 12:59:53 -0800
Subject: [PATCH] KNOWNBUG test for parameter without default value

SystemVerilog 1800-2017 allows module parameter ports without default value.
---
 .../verilog/modules/parameter_without_default1.desc   |  9 +++++++++
 .../verilog/modules/parameter_without_default1.sv     | 11 +++++++++++
 2 files changed, 20 insertions(+)
 create mode 100644 regression/verilog/modules/parameter_without_default1.desc
 create mode 100644 regression/verilog/modules/parameter_without_default1.sv

diff --git a/regression/verilog/modules/parameter_without_default1.desc b/regression/verilog/modules/parameter_without_default1.desc
new file mode 100644
index 000000000..b638875f0
--- /dev/null
+++ b/regression/verilog/modules/parameter_without_default1.desc
@@ -0,0 +1,9 @@
+KNOWNBUG
+parameter_without_default1.sv
+
+^EXIT=2$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
+This does not parse.
diff --git a/regression/verilog/modules/parameter_without_default1.sv b/regression/verilog/modules/parameter_without_default1.sv
new file mode 100644
index 000000000..aa5f4dade
--- /dev/null
+++ b/regression/verilog/modules/parameter_without_default1.sv
@@ -0,0 +1,11 @@
+// P has no default value; allowed by 1800-2017 6.20.1
+module my_module #(P);
+
+endmodule
+
+module main;
+
+  // error: didn't give value for P
+  my_module m1();
+
+endmodule