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lines changed Original file line number Diff line number Diff line change 1+ CORE
2+ followed-by4.sv
3+ --bound 3
4+ ^\[main\.p1\] always \(main\.x == 0 #-# 1\): REFUTED$
5+ ^\[main\.p2\] \(1 or \(##2 1\)\) #-# main\.x == 2: PROVED up to bound 3$
6+ ^\[main\.p3\] \(1 or \(##2 1\)\) #-# main\.x == 0: PROVED up to bound 3$
7+ ^EXIT=10$
8+ ^SIGNAL=0$
9+ --
10+ ^warning: ignoring
11+ --
Original file line number Diff line number Diff line change 1+ module main (input clk);
2+
3+ reg [31 : 0 ] x;
4+
5+ initial x= 0 ;
6+
7+ // 0, 1, ...
8+ always @ (posedge clk)
9+ x<= x+ 1 ;
10+
11+ // fails in the 2nd timeframe since the LHS doesn't match
12+ p1 : assert property (x== 0 # - # 1 );
13+
14+ // the RHS only needs to hold from _any one_ of the LHS matches,
15+ // not all
16+ initial p2 : assert property ((1 or ## 2 1 ) # - # x== 2 );
17+ initial p3 : assert property ((1 or ## 2 1 ) # - # x== 0 );
18+
19+ endmodule
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