Merge pull request #1334 from diffblue/integer_literals2

Verilog: tests for unsigned integer literals

Author: tautschnig

regression/verilog/expressions/integer_literals2.desc

@@ -0,0 +1,7 @@
+CORE
+integer_literals2.sv
+
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring

regression/verilog/expressions/integer_literals2.sv

@@ -0,0 +1,20 @@
+module main;
+
+  // 1800-2017 5.7.1
+
+  // "If the size of the unsigned number is smaller than the size specified
+  // for the literal constant, the unsigned number shall be padded to the
+  // left with zeros."
+  initial assert (4'b1 === 4'b0001);
+
+  // "If the leftmost bit in the unsigned number is an x or a z, then
+  // an x or a z shall be used to pad to the left, respectively."
+  initial assert (4'bz1 === 4'bzzz1);
+  initial assert (4'bx1 === 4'bxxx1);
+
+  // "If the size of the unsigned number is larger than the size specified
+  // for the literal constant, the unsigned number shall be truncated from
+  // the left."
+  initial assert (4'b1111_1111 === 4'b1111);
+
+endmodule