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tautschnigtautschnig
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Merge pull request #1459 from diffblue/use_verilog_identifier
Use `verilog_identifier_exprt`
2 parents 14b0489 + 591b7fd commit 8a0ed88

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5 files changed

+48
-41
lines changed

5 files changed

+48
-41
lines changed

‎src/verilog/parser.y‎

Lines changed: 6 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -112,7 +112,7 @@ inline static void init(YYSTYPE &expr, const irep_idt &id)
112112

113113
/*******************************************************************\
114114
115-
Function: new_symbol
115+
Function: new_identifier
116116
117117
Inputs:
118118
@@ -123,9 +123,9 @@ Function: new_symbol
123123
124124
\*******************************************************************/
125125

126-
inline static void new_symbol(YYSTYPE &dest, YYSTYPE &src)
126+
inline static void new_identifier(YYSTYPE &dest, YYSTYPE &src)
127127
{
128-
init(dest, ID_symbol);
128+
init(dest, ID_verilog_identifier);
129129
const auto base_name = stack_expr(src).id();
130130
stack_expr(dest).set(ID_identifier, base_name);
131131
stack_expr(dest).set(ID_base_name, base_name);
@@ -3719,7 +3719,7 @@ function_statement: statement
37193719
;
37203720

37213721
system_task_name: TOK_SYSIDENT
3722-
{ new_symbol($$, $1); stack_expr($$).id(ID_verilog_identifier); }
3722+
{ new_identifier($$, $1); }
37233723
;
37243724

37253725
// System Verilog standard 1800-2017
@@ -4648,12 +4648,12 @@ attr_name: identifier
46484648
// in a higher scope.
46494649
any_identifier:
46504650
TOK_TYPE_IDENTIFIER
4651-
{ new_symbol($$, $1); }
4651+
{ new_identifier($$, $1); }
46524652
| non_type_identifier
46534653
;
46544654

46554655
non_type_identifier: TOK_NON_TYPE_IDENTIFIER
4656-
{ new_symbol($$, $1); }
4656+
{ new_identifier($$, $1); }
46574657
;
46584658

46594659
block_identifier: TOK_NON_TYPE_IDENTIFIER;
@@ -4769,7 +4769,6 @@ hierarchical_identifier:
47694769
| hierarchical_identifier '.' identifier
47704770
{ init($$, ID_hierarchical_identifier);
47714771
stack_expr($$).reserve_operands(2);
4772-
stack_expr($3).id(ID_verilog_identifier);
47734772
mto($$, $1);
47744773
mto($$, $3);
47754774
}

‎src/verilog/verilog_generate.cpp‎

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -170,13 +170,14 @@ void verilog_typecheckt::elaborate_generate_assign(
170170
const verilog_generate_assignt &statement,
171171
module_itemst &dest)
172172
{
173-
if(statement.lhs().id() != ID_symbol)
173+
if(statement.lhs().id() != ID_verilog_identifier)
174174
{
175175
throw errort().with_location(statement.lhs().source_location())
176176
<< "expected symbol on left hand side of assignment";
177177
}
178178

179-
const irep_idt &identifier = to_symbol_expr(statement.lhs()).get_identifier();
179+
const irep_idt &identifier =
180+
to_verilog_identifier_expr(statement.lhs()).base_name();
180181

181182
genvarst::iterator it=genvars.find(identifier);
182183

‎src/verilog/verilog_typecheck.cpp‎

Lines changed: 13 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -60,11 +60,12 @@ void verilog_typecheckt::typecheck_port_connection(
6060
{
6161
// IEEE 1800 2017 6.10 allows implicit declarations of nets when
6262
// used in a port connection.
63-
if(op.id() == ID_symbol)
63+
if(op.id() == ID_verilog_identifier)
6464
{
6565
// The type of the implicit net is _not_ the type of the port,
6666
// but an "implicit scalar net of default net type".
67-
op = convert_symbol(to_symbol_expr(op), bool_typet{});
67+
op = convert_verilog_identifier(
68+
to_verilog_identifier_expr(op), bool_typet{});
6869
}
6970
else
7071
{
@@ -233,11 +234,12 @@ void verilog_typecheckt::typecheck_builtin_port_connections(
233234
{
234235
// IEEE 1800 2017 6.10 allows implicit declarations of nets when
235236
// used in a port connection.
236-
if(connection.id() == ID_symbol)
237+
if(connection.id() == ID_verilog_identifier)
237238
{
238239
// The type of the implicit net is _not_ the type of the port,
239240
// but an "implicit scalar net of default net type".
240-
connection = convert_symbol(to_symbol_expr(connection), bool_typet{});
241+
connection = convert_verilog_identifier(
242+
to_verilog_identifier_expr(connection), bool_typet{});
241243
}
242244
else
243245
{
@@ -845,8 +847,9 @@ void verilog_typecheckt::convert_continuous_assign(
845847
// from the RHS, and hence, we convert that first.
846848
convert_expr(rhs);
847849

848-
if(lhs.id() == ID_symbol)
849-
lhs = convert_symbol(to_symbol_expr(lhs), rhs.type());
850+
if(lhs.id() == ID_verilog_identifier)
851+
lhs =
852+
convert_verilog_identifier(to_verilog_identifier_expr(lhs), rhs.type());
850853
else
851854
convert_expr(lhs);
852855

@@ -877,7 +880,8 @@ void verilog_typecheckt::convert_function_call_or_task_enable(
877880
}
878881
else
879882
{
880-
irep_idt base_name = to_symbol_expr(statement.function()).get_identifier();
883+
irep_idt base_name =
884+
to_verilog_identifier_expr(statement.function()).base_name();
881885

882886
// look it up
883887
const irep_idt full_identifier =
@@ -914,8 +918,8 @@ void verilog_typecheckt::convert_function_call_or_task_enable(
914918
assignment_conversion(arguments[i], parameter_types[i].type());
915919
}
916920

917-
statement.function().type() = symbol->type;
918-
statement.function().set(ID_identifier, symbol->name);
921+
statement.function() =
922+
symbol->symbol_expr().with_source_location(statement.function());
919923
}
920924
}
921925

‎src/verilog/verilog_typecheck_expr.cpp‎

Lines changed: 22 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -629,24 +629,24 @@ exprt verilog_typecheck_exprt::convert_expr_function_call(
629629
if(expr.is_system_function_call())
630630
return convert_system_function(expr);
631631

632-
if(expr.function().id()!=ID_symbol)
632+
if(expr.function().id() != ID_verilog_identifier)
633633
{
634634
throw errort().with_location(expr.source_location())
635-
<< "expected symbol as function argument";
635+
<< "expected identifier as function";
636636
}
637637

638-
symbol_exprt &f_op=to_symbol_expr(expr.function());
638+
exprt &f_op = expr.function();
639639

640-
const irep_idt &identifier = f_op.get_identifier();
640+
const irep_idt &base_name = to_verilog_identifier_expr(f_op).base_name();
641641

642-
std::string full_identifier=
643-
id2string(module_identifier)+"."+id2string(identifier);
642+
std::string full_identifier =
643+
id2string(module_identifier) + "." + id2string(base_name);
644644

645645
const symbolt *symbol;
646646
if(ns.lookup(full_identifier, symbol))
647647
{
648648
throw errort().with_location(f_op.source_location())
649-
<< "unknown function `" << identifier << "'";
649+
<< "unknown function `" << base_name << "'";
650650
}
651651

652652
if(symbol->type.id()!=ID_code)
@@ -656,9 +656,8 @@ exprt verilog_typecheck_exprt::convert_expr_function_call(
656656
}
657657

658658
const code_typet &code_type=to_code_type(symbol->type);
659-
660-
f_op.type()=code_type;
661-
f_op.set(ID_identifier, full_identifier);
659+
660+
f_op = symbol->symbol_expr().with_source_location(f_op);
662661
expr.type()=code_type.return_type();
663662

664663
if(code_type.return_type().id()==ID_empty)
@@ -1220,9 +1219,10 @@ exprt verilog_typecheck_exprt::convert_nullary_expr(nullary_exprt expr)
12201219
{
12211220
return convert_constant(to_constant_expr(std::move(expr)));
12221221
}
1223-
else if(expr.id()==ID_symbol)
1222+
else if(expr.id() == ID_verilog_identifier)
12241223
{
1225-
return convert_symbol(to_symbol_expr(std::move(expr)), {});
1224+
return convert_verilog_identifier(
1225+
to_verilog_identifier_expr(std::move(expr)), {});
12261226
}
12271227
else if(expr.id()==ID_verilog_star_event)
12281228
{
@@ -1270,9 +1270,10 @@ Function: verilog_typecheck_exprt::resolve
12701270
12711271
\*******************************************************************/
12721272

1273-
const symbolt *verilog_typecheck_exprt::resolve(const symbol_exprt &expr)
1273+
const symbolt *
1274+
verilog_typecheck_exprt::resolve(const verilog_identifier_exprt &expr)
12741275
{
1275-
const irep_idt &base_name = expr.get_identifier();
1276+
const irep_idt &base_name = expr.base_name();
12761277

12771278
// in a task or function? Try local ones first
12781279
if(function_or_task_name!="")
@@ -1322,12 +1323,12 @@ Function: verilog_typecheck_exprt::convert_symbol
13221323
13231324
\*******************************************************************/
13241325

1325-
exprt verilog_typecheck_exprt::convert_symbol(
1326-
symbol_exprt expr,
1326+
exprt verilog_typecheck_exprt::convert_verilog_identifier(
1327+
verilog_identifier_exprt expr,
13271328
const std::optional<typet> &implicit_net_type)
13281329
{
13291330
auto symbol = resolve(expr);
1330-
auto base_name = expr.get_identifier();
1331+
auto base_name = expr.base_name();
13311332

13321333
if(symbol != nullptr)
13331334
{
@@ -2959,12 +2960,13 @@ exprt verilog_typecheck_exprt::convert_binary_expr(binary_exprt expr)
29592960
auto location = expr.source_location();
29602961
auto &package_scope = to_verilog_package_scope_expr(expr);
29612962

2962-
if(package_scope.identifier().id() != ID_symbol)
2963+
if(package_scope.identifier().id() != ID_verilog_identifier)
29632964
throw errort().with_location(location)
2964-
<< expr.id() << " expects symbol on the rhs";
2965+
<< expr.id() << " expects verilog_identifier on the rhs";
29652966

29662967
auto package_base = package_scope.package_base_name();
2967-
auto rhs_base = package_scope.identifier().get(ID_base_name);
2968+
auto rhs_base =
2969+
to_verilog_identifier_expr(package_scope.identifier()).base_name();
29682970

29692971
// stitch together
29702972
irep_idt full_identifier =

‎src/verilog/verilog_typecheck_expr.h‎

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -174,9 +174,10 @@ class verilog_typecheck_exprt:public verilog_typecheck_baset
174174
protected:
175175
[[nodiscard]] exprt convert_expr_rec(exprt expr);
176176
[[nodiscard]] exprt convert_constant(constant_exprt);
177-
[[nodiscard]] const symbolt *resolve(const symbol_exprt &);
178-
[[nodiscard]] exprt
179-
convert_symbol(symbol_exprt, const std::optional<typet> &implicit_net_type);
177+
[[nodiscard]] const symbolt *resolve(const verilog_identifier_exprt &);
178+
[[nodiscard]] exprt convert_verilog_identifier(
179+
verilog_identifier_exprt,
180+
const std::optional<typet> &implicit_net_type);
180181
[[nodiscard]] exprt
181182
convert_hierarchical_identifier(class hierarchical_identifier_exprt);
182183
[[nodiscard]] exprt convert_nullary_expr(nullary_exprt);

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