Merge pull request #1370 from diffblue/always_comb2-aig

KNOWNBUG test for Verilog->AIG conversion

Author: kroening

regression/verilog/synthesis/always_comb2.aig.desc

@@ -0,0 +1,12 @@
+KNOWNBUG
+always_comb2.sv
+--aig
+^\[main\.p0\] always main\.data == 0 -> main\.decoded == 1: PROVED .*$
+^\[main\.p1\] always main\.data == 1 -> main\.decoded == 2: PROVED .*$
+^\[main\.p2\] always main\.data == 2 -> main\.decoded == 4: PROVED .*$
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
+This segfaults.