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Verilog: extract code for $typename, $left, $right into separate file
This extracts the implementations of $typename, $left, $right into a separate file.
1 parent 5c83c53 commit 4994375

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4 files changed

+185
-78
lines changed

4 files changed

+185
-78
lines changed

‎src/verilog/Makefile‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2,6 +2,7 @@ SRC = aval_bval_encoding.cpp \
22
convert_literals.cpp \
33
expr2verilog.cpp \
44
sva_expr.cpp \
5+
typename.cpp \
56
verilog_bits.cpp \
67
verilog_elaborate.cpp \
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verilog_elaborate_type.cpp \

‎src/verilog/typename.cpp‎

Lines changed: 156 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,156 @@
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/*******************************************************************\
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Module: $typename
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Author: Daniel Kroening, dkr@amazon.com
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\*******************************************************************/
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#include "typename.h"
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#include <util/arith_tools.h>
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#include "verilog_bits.h"
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// unpacked array: left bound
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// packed array: index of most significant element
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// 0 otherwise
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mp_integer left(const typet &type)
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{
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if(
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type.id() == ID_unsignedbv || type.id() == ID_signedbv ||
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type.id() == ID_verilog_unsignedbv || type.id() == ID_verilog_signedbv ||
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type.id() == ID_bool)
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{
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auto offset = type.get_int(ID_C_offset);
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if(type.get_bool(ID_C_increasing))
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return offset;
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else
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return offset + verilog_bits(type) - 1;
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}
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else if(type.id() == ID_array)
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{
33+
auto offset = numeric_cast_v<mp_integer>(
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to_constant_expr(static_cast<const exprt &>(type.find(ID_offset))));
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if(type.get_bool(ID_C_increasing))
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return offset;
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else
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{
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return offset +
40+
numeric_cast_v<mp_integer>(
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to_constant_expr(to_array_type(type).size())) -
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1;
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}
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}
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else
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return 0;
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}
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// unpacked array: right bound
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// packed array: index of least significant element
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// 0 otherwise
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mp_integer right(const typet &type)
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{
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if(
55+
type.id() == ID_unsignedbv || type.id() == ID_signedbv ||
56+
type.id() == ID_verilog_unsignedbv || type.id() == ID_verilog_signedbv ||
57+
type.id() == ID_bool)
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{
59+
auto offset = type.get_int(ID_C_offset);
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if(type.get_bool(ID_C_increasing))
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return offset + verilog_bits(type) - 1;
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else
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return offset;
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}
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else if(type.id() == ID_array)
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{
67+
auto offset = numeric_cast_v<mp_integer>(
68+
to_constant_expr(static_cast<const exprt &>(type.find(ID_offset))));
69+
if(type.get_bool(ID_C_increasing))
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{
71+
return offset +
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numeric_cast_v<mp_integer>(
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to_constant_expr(to_array_type(type).size())) -
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1;
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}
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else
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return offset;
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}
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else
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return 0;
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}
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std::string verilog_typename(const typet &type)
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{
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const auto verilog_type = type.get(ID_C_verilog_type);
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auto left = [](const typet &type)
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{ return integer2string(verilog_left(type)); };
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auto right = [](const typet &type)
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{ return integer2string(verilog_right(type)); };
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if(type.id() == ID_unsignedbv)
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{
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if(verilog_type == ID_verilog_byte)
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return "byte unsigned";
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else if(verilog_type == ID_verilog_int)
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return "int unsigned";
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else if(verilog_type == ID_verilog_longint)
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return "longint unsigned";
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else if(verilog_type == ID_verilog_shortint)
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return "shortint unsigned";
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else
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return "bit[" + left(type) + ":" + right(type) + "]";
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}
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else if(type.id() == ID_verilog_unsignedbv)
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{
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return "logic[" + left(type) + ":" + right(type) + "]";
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}
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else if(type.id() == ID_bool)
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{
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return "bit";
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}
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else if(type.id() == ID_signedbv)
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{
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if(verilog_type == ID_verilog_byte)
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return "byte";
117+
else if(verilog_type == ID_verilog_int)
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return "int";
119+
else if(verilog_type == ID_verilog_longint)
120+
return "longint";
121+
else if(verilog_type == ID_verilog_shortint)
122+
return "shortint";
123+
else
124+
return "bit signed[" + left(type) + ":" + right(type) + "]";
125+
}
126+
else if(type.id() == ID_verilog_signedbv)
127+
{
128+
return "logic signed[" + left(type) + ":" + right(type) + "]";
129+
}
130+
else if(type.id() == ID_verilog_realtime)
131+
{
132+
return "realtime";
133+
}
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else if(type.id() == ID_verilog_real)
135+
{
136+
return "real";
137+
}
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else if(type.id() == ID_verilog_shortreal)
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{
140+
return "shortreal";
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}
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else if(type.id() == ID_verilog_chandle)
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{
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return "chandle";
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}
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else if(type.id() == ID_verilog_event)
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{
148+
return "event";
149+
}
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else if(type.id() == ID_verilog_string)
151+
{
152+
return "string";
153+
}
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else
155+
return "?";
156+
}

‎src/verilog/typename.h‎

Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,25 @@
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/*******************************************************************\
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Module: $typename
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Author: Daniel Kroening, dkr@amazon.com
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\*******************************************************************/
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#ifndef CPROVER_VERILOG_TYPENAME_H
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#define CPROVER_VERILOG_TYPENAME_H
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#include <util/mp_arith.h>
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class typet;
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/// Verilog's $left
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mp_integer verilog_left(const typet &);
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/// Verilog's $right
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mp_integer verilog_right(const typet &);
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/// Verilog's $typename
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std::string verilog_typename(const typet &);
24+
25+
#endif

‎src/verilog/verilog_typecheck_expr.cpp‎

Lines changed: 3 additions & 78 deletions
Original file line numberDiff line numberDiff line change
@@ -23,6 +23,7 @@ Author: Daniel Kroening, kroening@kroening.com
2323
#include "aval_bval_encoding.h"
2424
#include "convert_literals.h"
2525
#include "expr2verilog.h"
26+
#include "typename.h"
2627
#include "verilog_bits.h"
2728
#include "verilog_expr.h"
2829
#include "verilog_lowering.h"
@@ -950,84 +951,8 @@ Function: verilog_typecheck_exprt::typename_string
950951

951952
exprt verilog_typecheck_exprt::typename_string(const exprt &expr)
952953
{
953-
auto &type = expr.type();
954-
955-
auto left = this->left(expr);
956-
auto right = this->right(expr);
957-
958-
const auto verilog_type = type.get(ID_C_verilog_type);
959-
960-
std::string s;
961-
962-
if(type.id() == ID_unsignedbv)
963-
{
964-
if(verilog_type == ID_verilog_byte)
965-
s = "byte unsigned";
966-
else if(verilog_type == ID_verilog_int)
967-
s = "int unsigned";
968-
else if(verilog_type == ID_verilog_longint)
969-
s = "longint unsigned";
970-
else if(verilog_type == ID_verilog_shortint)
971-
s = "shortint unsigned";
972-
else
973-
s = "bit[" + to_string(left) + ":" + to_string(right) + "]";
974-
}
975-
else if(type.id() == ID_verilog_unsignedbv)
976-
{
977-
s = "logic[" + to_string(left) + ":" + to_string(right) + "]";
978-
}
979-
else if(type.id() == ID_bool)
980-
{
981-
s = "bit";
982-
}
983-
else if(type.id() == ID_signedbv)
984-
{
985-
if(verilog_type == ID_verilog_byte)
986-
s = "byte";
987-
else if(verilog_type == ID_verilog_int)
988-
s = "int";
989-
else if(verilog_type == ID_verilog_longint)
990-
s = "longint";
991-
else if(verilog_type == ID_verilog_shortint)
992-
s = "shortint";
993-
else
994-
s = "bit signed[" + to_string(left) + ":" + to_string(right) + "]";
995-
}
996-
else if(type.id() == ID_verilog_signedbv)
997-
{
998-
s = "logic signed[" + to_string(left) + ":" + to_string(right) + "]";
999-
}
1000-
else if(type.id() == ID_verilog_realtime)
1001-
{
1002-
s = "realtime";
1003-
}
1004-
else if(type.id() == ID_verilog_real)
1005-
{
1006-
s = "real";
1007-
}
1008-
else if(type.id() == ID_verilog_shortreal)
1009-
{
1010-
s = "shortreal";
1011-
}
1012-
else if(type.id() == ID_verilog_chandle)
1013-
{
1014-
s = "chandle";
1015-
}
1016-
else if(type.id() == ID_verilog_event)
1017-
{
1018-
s = "event";
1019-
}
1020-
else if(type.id() == ID_verilog_string)
1021-
{
1022-
s = "string";
1023-
}
1024-
else
1025-
s = "?";
1026-
1027-
auto result = convert_string_literal(s);
1028-
result.add_source_location() = expr.source_location();
1029-
1030-
return std::move(result);
954+
auto s = verilog_typename(expr.type());
955+
return convert_string_literal(s).with_source_location(expr);
1031956
}
1032957

1033958
/*******************************************************************\

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