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2 parents 195103b + b6634d8 commit 3313643Copy full SHA for 3313643
regression/ebmc-spot/sva-buechi/disable_iff1.bdd.desc
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-KNOWNBUG
+CORE
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../../verilog/SVA/disable_iff1.sv
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--buechi --module main --bdd --numbered-trace
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^\[main\.p0\] always \(disable iff \(main.counter == 0\) main\.counter != 0\): PROVED$
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