From fee8f911a94cf3a5081ff138d0f2939e0b927d2b Mon Sep 17 00:00:00 2001 From: Brandon Chuang Date: Fri, 6 Oct 2023 16:06:48 +0800 Subject: [PATCH] [Edgecore] Add as4500-52p DTS CPU: Marvell 98DX3530 with integrated CPU MAC: Marvell 98DX3530 PHY: Marvell 88E1780 x 4 (1G port 16~32) Marvell 88E2780 x 2 (Migi-G port 33-48) DRAM: 8GB(MAC) DDR4 SDRAM AirFlow: Front To Back Function port: 1 x USB port 1 x RJ45 Mgmt port 1 x RJ45 Console port Ethernet Port: 48 x 1G Uplink port: 4xSFP+ PoE: Microsemi PD69208M x 12 + PD69210 x 2 The DTS is for the PR: https://github.com/dentproject/dentOS/pull/285 Signed-off-by: Brandon Chuang --- .../boot/dts/marvell/accton-as4500-52p.dts | 39 ++ .../boot/dts/marvell/accton-as4500-52p.dtsi | 395 ++++++++++++++++++ 2 files changed, 434 insertions(+) create mode 100644 arch/arm64/boot/dts/marvell/accton-as4500-52p.dts create mode 100644 arch/arm64/boot/dts/marvell/accton-as4500-52p.dtsi diff --git a/arch/arm64/boot/dts/marvell/accton-as4500-52p.dts b/arch/arm64/boot/dts/marvell/accton-as4500-52p.dts new file mode 100644 index 0000000000000..0c02ca06f18d9 --- /dev/null +++ b/arch/arm64/boot/dts/marvell/accton-as4500-52p.dts @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree For Accton as4500-52p. + * + * Copyright (C) 2021 Marvell + * + */ + +#include "accton-as4500-52p.dtsi" + +/ { + model = "Marvell AC5X RD board"; +}; + +&mdio { + status = "disabled"; + pinctrl-names = "default"; + phy0: ethernet-phy@0 { + reg = <0x0>; + }; +}; + +ð0 { + status = "disabled"; + phy-mode = "sgmii"; + phy = <&phy0>; +}; + +&usb0 { + status= "okay"; +}; + +&usb1 { + compatible = "chipidea,usb2"; + phys = <&usb1phy>; + phy-names = "usb-phy"; + dr_mode = "host"; +}; + diff --git a/arch/arm64/boot/dts/marvell/accton-as4500-52p.dtsi b/arch/arm64/boot/dts/marvell/accton-as4500-52p.dtsi new file mode 100644 index 0000000000000..728845e6727c7 --- /dev/null +++ b/arch/arm64/boot/dts/marvell/accton-as4500-52p.dtsi @@ -0,0 +1,395 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Device Tree For Accton as4500-52p. + * + * Copyright (C) 2021 Marvell + * + */ + +/dts-v1/; + +#include +#include +/*#include */ + +/ { + model = "Marvell AC5x board"; + compatible = "marvell,armada3700"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + prestera_rsvd: buffer@0x200000000 { + /* to be used as a shared pool of DMA buffers for a set of devices */ + compatible = "shared-dma-pool"; + /* No one other than devices registered for that mem, may use this area */ + no-map; + + /* Base addr (first 2 cells) requires alignment, we choose start of memory */ + reg = <0x2 0x0 0x0 0x400000>; + }; + }; + + mvDma { + compatible = "marvell,mv_dma"; + memory-region = <&prestera_rsvd>; + status = "okay"; + }; + + aliases { + serial0 = &uart0; + spiflash0 = &spiflash0; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + //clock-frequency = <10020>; + //clock-frequency = <110400>; + //clock-frequency = <110020>; + clock-frequency = <25000000>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = ; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + dma-ranges; + + internal-regs@7f000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + /* 16M internal register @ 0x7f00_0000 */ + ranges = <0x0 0x0 0x7f000000 0x1000000>; + dma-coherent; + + uart0: serial@12000 { + compatible = "snps,dw-apb-uart"; + reg = <0x12000 0x100>; + reg-shift = <2>; + interrupts = ; + reg-io-width = <1>; + clock-frequency = <328000000>; + status = "okay"; + }; + + mdio: mdio@20000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "marvell,orion-mdio"; + reg = <0x22004 0x4>; + clocks = <&core_clock>; + phy0: ethernet-phy@0 { + reg = < 0 0 >; + }; + }; + + i2c0: i2c@11000{ + compatible = "marvell,mv78230-i2c"; + reg = <0x11000 0x20>; + + clocks = <&core_clock>; + clock-names = "core"; + interrupts = ; + clock-frequency=<100000>; + status="okay"; + }; + + i2c1: i2c@11100{ + compatible = "marvell,mv78230-i2c"; + reg = <0x11100 0x20>; + + clocks = <&core_clock>; + clock-names = "core"; + interrupts = ; + clock-frequency=<100000>; + status="okay"; + }; + + gpio0: gpio@18100 { + compatible = "marvell,ac5-gpio"; + #gpio-cells = <2>; + gpio-controller; + reg = <0x18100 0x200>; + // gpio-ranges = <&pinctrl0 0 0 46>; + ngpios = <46>; + }; + }; + + mmc_dma: mmc-dma-peripherals@80500000 { + compatible = "simple-bus"; + #address-cells = <0x2>; + #size-cells = <0x2>; + ranges; + dma-coherent; + + sdhci0: sdhci@805c0000 { + compatible = "marvell,ac5-sdhci", "marvell,armada-ap806-sdhci"; + reg = <0x0 0x805c0000 0x0 0x300>; + reg-names = "ctrl", "decoder"; + interrupts = ; + clocks = <&core_clock>; + clock-names = "core"; + status = "okay"; + bus-width = <8>; + /*marvell,xenon-phy-slow-mode;*/ + non-removable; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + }; + }; + + /* Dedicated section for devices behind 32bit controllers so we + can configure specific DMA mapping for them */ + 32bit-dma-peripherals@7f000000 { + compatible = "simple-bus"; + #address-cells = <0x2>; + #size-cells = <0x2>; + ranges = <0x0 0x0 0x0 0x7f000000 0x0 0x1000000>; + /* Host phy ram starts at 0x200M */ + dma-ranges = <0x0 0x0 0x2 0x0 0x1 0x0>; + dma-coherent; + + eth0: ethernet@20000 { + compatible = "marvell,armada-ac5-neta"; + reg = <0x0 0x20000 0x0 0x4000>; + interrupts = ; + clocks = <&core_clock>; + status = "disabled"; + phy-mode = "sgmii"; + }; + + eth1: ethernet@24000 { + compatible = "marvell,armada-ac5-neta"; + reg = <0x0 0x24000 0x0 0x4000>; + interrupts = ; + clocks = <&core_clock>; + status = "disabled"; + phy-mode = "sgmii"; + fixed-link { + speed = <100>; + full-duplex; + }; + }; + + /* A dummy entry used for chipidea phy init */ + usb1phy: usbphy { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; + + /* USB0 is a host USB */ + usb0: usb@80000 { + compatible = "marvell,orion-ehci"; + reg = <0x0 0x80000 0x0 0x500>; + interrupts = ; + status = "okay"; + }; + + /* USB1 is a peripheral USB */ + usb1: usb@A0000 { + reg = <0x0 0xA0000 0x0 0x500>; + interrupts = ; + status = "okay"; + }; + }; + + pcie0: pcie@800a0000 { + compatible = "marvell,ac5-pcie", "snps,dw-pcie"; + reg = <0 0x800a0000 0 0x20000> , <0 0x3fff0000 0 0x10000>; + reg-names = "ctrl", "config"; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + dma-coherent; + bus-range = <0 0xff>; + /* ranges for the PCI memory and I/O regions */ + ranges = <0x82000000 0 0x30000000 0 0x30000000 0 0xfff0000>; + + interrupt-map-mask = <0 0 0 1>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; + + interrupts = ; + + num-lanes = <1>; + status = "disabled"; + + clocks = <&core_clock>; + }; + + core_clock: core_clock@0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + }; + + axi_clock: axi_clock@0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <325000000>; + }; + + spi_clock: spi_clock@0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + }; + + spi@805a0000 { + compatible = "marvell,armada-3700-spi"; + reg = <0x0 0x805a0000 0x0 0x50>; + #address-cells = <0x1>; + #size-cells = <0x0>; + clocks = <&spi_clock>; + interrupts = ; + num-cs = <1>; + status = "okay"; + + spiflash0: spi-flash@0 { + compatible = "spi-nor"; + spi-max-frequency = <50000000>; + spi-tx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */ + spi-rx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */ + reg = <0>; + + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "u-boot"; + reg = <0x0 0x400000>; + }; + + parition@1 { + label = "u-boot_env"; + reg = <0x400000 0x10000>; + }; + + parition@2 { + label = "oem"; + reg = <0x410000 0xf0000>; + }; + + parition@3 { + label = "reserve"; + reg = <0x500000 0x1b00000>; + }; + }; + }; + + spi@805a8000 { + compatible = "marvell,armada-3700-spi"; + reg = <0x0 0x805a8000 0x0 0x50>; + #address-cells = <0x1>; + #size-cells = <0x0>; + clocks = <&spi_clock>; + interrupts = ; + num-cs = <1>; + status = "disabled"; + }; + + nand: nand@805b00 { + compatible = "marvell,ac5-nand-controller"; + reg = <0x0 0x805b0000 0x0 0x00000054 + 0x0 0x840F8204 0x0 0x00000004 + 0x0 0x80013010 0x0 0x00000020>; + #address-cells = <0x1>; + #size-cells = <0x0>; + interrupts = ; + clocks = <&core_clock>; + /*marvell,system-controller = <0x15>*/ + status = "disabled"; + + nand@0 { + reg = <0x0>; + label = "main-storage"; + nand-rb = <0>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <12>; + nand-ecc-step-size = <512>; + }; + }; + + prestera { + compatible = "marvell,armada-ac5-switch"; + interrupts = ; + status = "okay"; + }; + + }; + + gic: interrupt-controller@80600000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + /*#redistributor-regions = <1>;*/ + redistributor-stride = <0x0 0x20000>; /* 128kB stride */ + reg = <0x0 0x80600000 0x0 0x10000>, /* GICD */ + <0x0 0x80660000 0x0 0x40000>; /* GICR */ + interrupts = ; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + core1 { + cpu = <&CPU1>; + }; + }; + }; + + CPU0:cpu@0 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + CPU1:cpu@1 { + device_type = "cpu"; + compatible = "arm,armv8"; + reg = <0x0 0x100>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + }; + + L2_0: l2-cache0 { + compatible = "cache"; + }; + }; + + memory@00000000 { + device_type = "memory"; + reg = <0x2 0x00000000 0x1 0x00000000>; + // linux,usable-memory = <0x2 0x00000000 0x0 0x80000000>; + }; +};