floating point -Fused Multiply-Add bug

[ting831015]

i have some bug in my verilog ,i can't fix it ,could you heip me fix it,please ? it's about floating point-Fused Multiply-Add

module FMA (a, b, c,P);
input [31:0] a, b, c;
output [31:0] d;
output [31:0] P;
wire sa, sb, sc,sp,sd;
wire [7:0] ea, eb, ec,ed;
wire [22:0] ma, mb, mc,md;

assign sa = a[31];
assign sb = b[31];
assign sc = c[31];
assign ea = a[30:23];
assign eb = b[30:23];
assign ec = c[30:23];
assign ma = a[22:0];
assign mb = b[22:0];
assign mc = c[22:0];
wire[75:0]ctmp,ptmp;
wire[45:0]mp;
wire[7:0]ep;
wire[7:0]ge,le,fe;
wire[6:0]ss;
wire[75:0]gm,lm,alm,dtmp;
wire[23:0]nm;
wire ovf;
wire [26:0]rnd;

assign ep=ea+eb-8'd127;
assign sp=sa^sb;
assign ctmp=(sc)?{26'b0,~{1'b1,mc}+1,25'b0}:{26'b0, {1'b1, mc}, 25'b0};
assign mp = ma*mb;
assign P={sp,ep,mp};

assign ptmp=(sp)?{26'b0,~{1'b1,mp}+1,2'b0}:{26'b0, {1'b1,mp} ,2'b0};
wire pgtc=(ep>=ec);

assign {ge,gm}=pgtc?{ep,ptmp}:{ec,ctmp};
assign {le,lm}=pgtc?{ec,ctmp}:{ep,ptmp};
assign fe=ge-le;
assign alm=lm>>>fe;

wire[75:0]sm=gm+alm;
assign sd=sm[75];
assign dtmp=sd?~sm+1:sm;
assign nm=dtmp[50:27];
assign rnd=dtmp[26:0];
LOD #(76, 7) ff1 (.din(dtmp), .zero_cnt(ss));
assign {dtmp[75:51],nm,rnd}=dtmp<<ss;
assign{ovf,ed}=ge-ss+8'd27;

assign md= nm + rnd;
assign d={sd,ed,md};

endmodule
define TRUE 1'b1 define FALSE 1'b0
module LOD #(
parameter WIDTH = 76,
parameter y = 7);
(
input [WIDTH-1:0] din,
output reg [y-1:0] zero_cnt);

integer i;
reg continue;
always @(*) begin
    i=75;
    continue = `TRUE;
    while ((i>=0) && continue) begin
        zero_cnt = din[i] ? 7'd75 - i : 7'd0;
        continue = din[i] ? `FALSE : `TRUE;
       i=i-1; // problematic ?
    end

end
endmodule