I have a set of SystemVerilog files in a folder named verilog.
For example, I have the file verilog/dff.sv. Within that file is a module declared as module dff (#parameter SIZE = 1). I would expect this to pass the linter, as the filename and the module name are identical. However, when I run svlint, I get a failure for module_identifier_matches_filename
I have a set of SystemVerilog files in a folder named
verilog.For example, I have the file
verilog/dff.sv. Within that file is a module declared asmodule dff (#parameter SIZE = 1). I would expect this to pass the linter, as the filename and the module name are identical. However, when I runsvlint, I get a failure formodule_identifier_matches_filename