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dpll: add phase-adjust-gran pin attribute
JIRA: https://issues.redhat.com/browse/RHEL-126529 Upstream commit(s): commit 30176bf Author: Ivan Vecera <ivecera@redhat.com> Date: Wed Oct 29 16:32:06 2025 +0100 dpll: add phase-adjust-gran pin attribute Phase-adjust values are currently limited by a min-max range. Some hardware requires, for certain pin types, that values be multiples of a specific granularity, as in the zl3073x driver. Add a `phase-adjust-gran` pin attribute and an appropriate field in dpll_pin_properties. If set by the driver, use its value to validate user-provided phase-adjust values. Reviewed-by: Michal Schmidt <mschmidt@redhat.com> Reviewed-by: Petr Oros <poros@redhat.com> Tested-by: Prathosh Satish <Prathosh.Satish@microchip.com> Signed-off-by: Ivan Vecera <ivecera@redhat.com> Reviewed-by: Jiri Pirko <jiri@nvidia.com> Reviewed-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com> Link: https://patch.msgid.link/20251029153207.178448-2-ivecera@redhat.com Signed-off-by: Jakub Kicinski <kuba@kernel.org> Signed-off-by: Petr Oros <poros@redhat.com>
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‎Documentation/driver-api/dpll.rst‎

Lines changed: 20 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -198,26 +198,28 @@ be requested with the same attribute with ``DPLL_CMD_DEVICE_SET`` command.
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================================== ======================================
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Device may also provide ability to adjust a signal phase on a pin.
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If pin phase adjustment is supported, minimal and maximal values that pin
202-
handle shall be provide to the user on ``DPLL_CMD_PIN_GET`` respond
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with ``DPLL_A_PIN_PHASE_ADJUST_MIN`` and ``DPLL_A_PIN_PHASE_ADJUST_MAX``
201+
If pin phase adjustment is supported, minimal and maximal values and
202+
granularity that pin handle shall be provided to the user on
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``DPLL_CMD_PIN_GET`` respond with ``DPLL_A_PIN_PHASE_ADJUST_MIN``,
204+
``DPLL_A_PIN_PHASE_ADJUST_MAX`` and ``DPLL_A_PIN_PHASE_ADJUST_GRAN``
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attributes. Configured phase adjust value is provided with
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``DPLL_A_PIN_PHASE_ADJUST`` attribute of a pin, and value change can be
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requested with the same attribute with ``DPLL_CMD_PIN_SET`` command.
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208-
=============================== ======================================
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``DPLL_A_PIN_ID`` configured pin id
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``DPLL_A_PIN_PHASE_ADJUST_MIN`` attr minimum value of phase adjustment
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``DPLL_A_PIN_PHASE_ADJUST_MAX`` attr maximum value of phase adjustment
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``DPLL_A_PIN_PHASE_ADJUST`` attr configured value of phase
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adjustment on parent dpll device
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``DPLL_A_PIN_PARENT_DEVICE`` nested attribute for requesting
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configuration on given parent dpll
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device
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``DPLL_A_PIN_PARENT_ID`` parent dpll device id
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``DPLL_A_PIN_PHASE_OFFSET`` attr measured phase difference
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between a pin and parent dpll device
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=============================== ======================================
209+
================================ ==========================================
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``DPLL_A_PIN_ID`` configured pin id
211+
``DPLL_A_PIN_PHASE_ADJUST_GRAN`` attr granularity of phase adjustment value
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``DPLL_A_PIN_PHASE_ADJUST_MIN`` attr minimum value of phase adjustment
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``DPLL_A_PIN_PHASE_ADJUST_MAX`` attr maximum value of phase adjustment
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``DPLL_A_PIN_PHASE_ADJUST`` attr configured value of phase
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adjustment on parent dpll device
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``DPLL_A_PIN_PARENT_DEVICE`` nested attribute for requesting
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configuration on given parent dpll
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device
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``DPLL_A_PIN_PARENT_ID`` parent dpll device id
220+
``DPLL_A_PIN_PHASE_OFFSET`` attr measured phase difference
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between a pin and parent dpll device
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================================ ==========================================
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All phase related values are provided in pico seconds, which represents
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time difference between signals phase. The negative value means that
@@ -384,6 +386,8 @@ according to attribute purpose.
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frequencies
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``DPLL_A_PIN_ANY_FREQUENCY_MIN`` attr minimum value of frequency
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``DPLL_A_PIN_ANY_FREQUENCY_MAX`` attr maximum value of frequency
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``DPLL_A_PIN_PHASE_ADJUST_GRAN`` attr granularity of phase
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adjustment value
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``DPLL_A_PIN_PHASE_ADJUST_MIN`` attr minimum value of phase
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adjustment
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``DPLL_A_PIN_PHASE_ADJUST_MAX`` attr maximum value of phase

‎Documentation/netlink/specs/dpll.yaml‎

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -440,6 +440,12 @@ attribute-sets:
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doc: |
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Capable pin provides list of pins that can be bound to create a
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reference-sync pin pair.
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-
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name: phase-adjust-gran
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type: u32
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doc: |
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Granularity of phase adjustment, in picoseconds. The value of
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phase adjustment must be a multiple of this granularity.
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-
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name: pin-parent-device
@@ -616,6 +622,7 @@ operations:
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- capabilities
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- parent-device
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- parent-pin
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- phase-adjust-gran
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- phase-adjust-min
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- phase-adjust-max
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- phase-adjust

‎drivers/dpll/dpll_netlink.c‎

Lines changed: 11 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -637,6 +637,10 @@ dpll_cmd_pin_get_one(struct sk_buff *msg, struct dpll_pin *pin,
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ret = dpll_msg_add_pin_freq(msg, pin, ref, extack);
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if (ret)
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return ret;
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if (prop->phase_gran &&
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nla_put_u32(msg, DPLL_A_PIN_PHASE_ADJUST_GRAN,
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prop->phase_gran))
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return -EMSGSIZE;
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if (nla_put_s32(msg, DPLL_A_PIN_PHASE_ADJUST_MIN,
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prop->phase_range.min))
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return -EMSGSIZE;
@@ -1261,7 +1265,13 @@ dpll_pin_phase_adj_set(struct dpll_pin *pin, struct nlattr *phase_adj_attr,
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if (phase_adj > pin->prop.phase_range.max ||
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phase_adj < pin->prop.phase_range.min) {
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NL_SET_ERR_MSG_ATTR(extack, phase_adj_attr,
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"phase adjust value not supported");
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"phase adjust value of out range");
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return -EINVAL;
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}
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if (pin->prop.phase_gran && phase_adj % (s32)pin->prop.phase_gran) {
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NL_SET_ERR_MSG_ATTR_FMT(extack, phase_adj_attr,
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"phase adjust value not multiple of %u",
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pin->prop.phase_gran);
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return -EINVAL;
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}
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‎include/linux/dpll.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -193,6 +193,7 @@ struct dpll_pin_properties {
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u32 freq_supported_num;
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struct dpll_pin_frequency *freq_supported;
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struct dpll_pin_phase_adjust_range phase_range;
196+
u32 phase_gran;
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};
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#if IS_ENABLED(CONFIG_DPLL)

‎include/uapi/linux/dpll.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -251,6 +251,7 @@ enum dpll_a_pin {
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DPLL_A_PIN_ESYNC_FREQUENCY_SUPPORTED,
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DPLL_A_PIN_ESYNC_PULSE,
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DPLL_A_PIN_REFERENCE_SYNC,
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DPLL_A_PIN_PHASE_ADJUST_GRAN,
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__DPLL_A_PIN_MAX,
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DPLL_A_PIN_MAX = (__DPLL_A_PIN_MAX - 1)

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