Skip to content

Commit b9f9fbc

Browse files
stanleychuysgregkh
authored andcommitted
i3c: master: svc: Prevent incomplete IBI transaction
[ Upstream commit 3a36273 ] If no free IBI slot is available, svc_i3c_master_handle_ibi returns immediately. This causes the STOP condition to be missed because the EmitStop request is sent when the transfer is not complete. To resolve this, svc_i3c_master_handle_ibi must wait for the transfer to complete before returning. Fixes: dd3c528 ("i3c: master: svc: Add Silvaco I3C master driver") Signed-off-by: Stanley Chu <yschu@nuvoton.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://patch.msgid.link/20251027034715.708243-1-yschu@nuvoton.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Signed-off-by: Sasha Levin <sashal@kernel.org>
1 parent d3bacdd commit b9f9fbc

File tree

1 file changed

+14
-8
lines changed

1 file changed

+14
-8
lines changed

drivers/i3c/master/svc-i3c-master.c

Lines changed: 14 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -366,21 +366,27 @@ static int svc_i3c_master_handle_ibi(struct svc_i3c_master *master,
366366
int ret, val;
367367
u8 *buf;
368368

369-
slot = i3c_generic_ibi_get_free_slot(data->ibi_pool);
370-
if (!slot)
371-
return -ENOSPC;
372-
373-
slot->len = 0;
374-
buf = slot->data;
375-
369+
/*
370+
* Wait for transfer to complete before returning. Otherwise, the EmitStop
371+
* request might be sent when the transfer is not complete.
372+
*/
376373
ret = readl_relaxed_poll_timeout(master->regs + SVC_I3C_MSTATUS, val,
377374
SVC_I3C_MSTATUS_COMPLETE(val), 0, 1000);
378375
if (ret) {
379376
dev_err(master->dev, "Timeout when polling for COMPLETE\n");
380-
i3c_generic_ibi_recycle_slot(data->ibi_pool, slot);
381377
return ret;
382378
}
383379

380+
slot = i3c_generic_ibi_get_free_slot(data->ibi_pool);
381+
if (!slot) {
382+
dev_dbg(master->dev, "No free ibi slot, drop the data\n");
383+
writel(SVC_I3C_MDATACTRL_FLUSHRB, master->regs + SVC_I3C_MDATACTRL);
384+
return -ENOSPC;
385+
}
386+
387+
slot->len = 0;
388+
buf = slot->data;
389+
384390
while (SVC_I3C_MSTATUS_RXPEND(readl(master->regs + SVC_I3C_MSTATUS)) &&
385391
slot->len < SVC_I3C_FIFO_SIZE) {
386392
mdatactrl = readl(master->regs + SVC_I3C_MDATACTRL);

0 commit comments

Comments
 (0)