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dpll: add reference-sync netlink attribute
JIRA: https://issues.redhat.com/browse/RHEL-126529 Upstream commit(s): commit 7f15ee3 Author: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com> Date: Thu Jun 26 15:52:17 2025 +0200 dpll: add reference-sync netlink attribute Add new netlink attribute to allow user space configuration of reference sync pin pairs, where both pins are used to provide one clock signal consisting of both: base frequency and sync signal. Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com> Reviewed-by: Milena Olech <milena.olech@intel.com> Reviewed-by: Jiri Pirko <jiri@nvidia.com> Signed-off-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com> Link: https://patch.msgid.link/20250626135219.1769350-2-arkadiusz.kubalewski@intel.com Signed-off-by: Jakub Kicinski <kuba@kernel.org> Signed-off-by: Petr Oros <poros@redhat.com>
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‎Documentation/driver-api/dpll.rst‎

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@@ -253,6 +253,31 @@ the pin.
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``DPLL_A_PIN_ESYNC_PULSE`` pulse type of Embedded SYNC
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========================================= =================================
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Reference SYNC
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==============
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The device may support the Reference SYNC feature, which allows the combination
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of two inputs into a input pair. In this configuration, clock signals
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from both inputs are used to synchronize the DPLL device. The higher frequency
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signal is utilized for the loop bandwidth of the DPLL, while the lower frequency
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signal is used to syntonize the output signal of the DPLL device. This feature
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enables the provision of a high-quality loop bandwidth signal from an external
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source.
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A capable input provides a list of inputs that can be bound with to create
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Reference SYNC. To control this feature, the user must request a desired
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state for a target pin: use ``DPLL_PIN_STATE_CONNECTED`` to enable or
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``DPLL_PIN_STATE_DISCONNECTED`` to disable the feature. An input pin can be
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bound to only one other pin at any given time.
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============================== ==========================================
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``DPLL_A_PIN_REFERENCE_SYNC`` nested attribute for providing info or
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requesting configuration of the Reference
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SYNC feature
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``DPLL_A_PIN_ID`` target pin id for Reference SYNC feature
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``DPLL_A_PIN_STATE`` state of Reference SYNC connection
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============================== ==========================================
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Configuration commands group
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============================
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‎Documentation/netlink/specs/dpll.yaml‎

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@@ -428,6 +428,15 @@ attribute-sets:
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doc: |
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A ratio of high to low state of a SYNC signal pulse embedded
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into base clock frequency. Value is in percents.
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-
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name: reference-sync
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type: nest
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multi-attr: true
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nested-attributes: reference-sync
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doc: |
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Capable pin provides list of pins that can be bound to create a
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reference-sync pin pair.
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-
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name: pin-parent-device
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subset-of: pin
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name: frequency-min
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-
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name: frequency-max
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-
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name: reference-sync
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subset-of: pin
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attributes:
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-
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name: id
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-
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name: state
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operations:
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enum-name: dpll_cmd
@@ -598,6 +615,7 @@ operations:
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- esync-frequency
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- esync-frequency-supported
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- esync-pulse
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- reference-sync
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dump:
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request:
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- parent-pin
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- phase-adjust
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- esync-frequency
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- reference-sync
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-
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name: pin-create-ntf
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doc: Notification about pin appearing

‎drivers/dpll/dpll_nl.c‎

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@@ -24,6 +24,11 @@ const struct nla_policy dpll_pin_parent_pin_nl_policy[DPLL_A_PIN_STATE + 1] = {
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[DPLL_A_PIN_STATE] = NLA_POLICY_RANGE(NLA_U32, 1, 3),
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};
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const struct nla_policy dpll_reference_sync_nl_policy[DPLL_A_PIN_STATE + 1] = {
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[DPLL_A_PIN_ID] = { .type = NLA_U32, },
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[DPLL_A_PIN_STATE] = NLA_POLICY_RANGE(NLA_U32, 1, 3),
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};
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/* DPLL_CMD_DEVICE_ID_GET - do */
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static const struct nla_policy dpll_device_id_get_nl_policy[DPLL_A_TYPE + 1] = {
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[DPLL_A_MODULE_NAME] = { .type = NLA_NUL_STRING, },
@@ -63,7 +68,7 @@ static const struct nla_policy dpll_pin_get_dump_nl_policy[DPLL_A_PIN_ID + 1] =
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};
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/* DPLL_CMD_PIN_SET - do */
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static const struct nla_policy dpll_pin_set_nl_policy[DPLL_A_PIN_ESYNC_FREQUENCY + 1] = {
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static const struct nla_policy dpll_pin_set_nl_policy[DPLL_A_PIN_REFERENCE_SYNC + 1] = {
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[DPLL_A_PIN_ID] = { .type = NLA_U32, },
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[DPLL_A_PIN_FREQUENCY] = { .type = NLA_U64, },
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[DPLL_A_PIN_DIRECTION] = NLA_POLICY_RANGE(NLA_U32, 1, 2),
@@ -73,6 +78,7 @@ static const struct nla_policy dpll_pin_set_nl_policy[DPLL_A_PIN_ESYNC_FREQUENCY
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[DPLL_A_PIN_PARENT_PIN] = NLA_POLICY_NESTED(dpll_pin_parent_pin_nl_policy),
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[DPLL_A_PIN_PHASE_ADJUST] = { .type = NLA_S32, },
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[DPLL_A_PIN_ESYNC_FREQUENCY] = { .type = NLA_U64, },
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[DPLL_A_PIN_REFERENCE_SYNC] = NLA_POLICY_NESTED(dpll_reference_sync_nl_policy),
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};
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/* Ops table for dpll */
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.doit = dpll_nl_pin_set_doit,
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.post_doit = dpll_pin_post_doit,
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.policy = dpll_pin_set_nl_policy,
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.maxattr = DPLL_A_PIN_ESYNC_FREQUENCY,
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.maxattr = DPLL_A_PIN_REFERENCE_SYNC,
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.flags = GENL_ADMIN_PERM | GENL_CMD_CAP_DO,
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},
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};

‎drivers/dpll/dpll_nl.h‎

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/* Common nested types */
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extern const struct nla_policy dpll_pin_parent_device_nl_policy[DPLL_A_PIN_PHASE_OFFSET + 1];
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extern const struct nla_policy dpll_pin_parent_pin_nl_policy[DPLL_A_PIN_STATE + 1];
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extern const struct nla_policy dpll_reference_sync_nl_policy[DPLL_A_PIN_STATE + 1];
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int dpll_lock_doit(const struct genl_split_ops *ops, struct sk_buff *skb,
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struct genl_info *info);

‎include/uapi/linux/dpll.h‎

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@@ -249,6 +249,7 @@ enum dpll_a_pin {
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DPLL_A_PIN_ESYNC_FREQUENCY,
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DPLL_A_PIN_ESYNC_FREQUENCY_SUPPORTED,
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DPLL_A_PIN_ESYNC_PULSE,
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DPLL_A_PIN_REFERENCE_SYNC,
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__DPLL_A_PIN_MAX,
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DPLL_A_PIN_MAX = (__DPLL_A_PIN_MAX - 1)

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