From cc39f87783d7ce65d375f7d4a4ab8c13503f7b68 Mon Sep 17 00:00:00 2001 From: ALVAROPING1 Date: Sat, 7 Mar 2026 13:59:25 +0100 Subject: [PATCH 01/85] tests(arch): simplify definition of common execution tests --- .../unit/arch/mips/mips_example_002.test.mts | 39 +--- .../unit/arch/mips/mips_example_003.test.mts | 45 ++--- .../unit/arch/mips/mips_example_004.test.mts | 43 ++--- .../unit/arch/mips/mips_example_005.test.mts | 37 +--- .../unit/arch/mips/mips_example_006.test.mts | 39 +--- .../unit/arch/mips/mips_example_007.test.mts | 39 +--- .../unit/arch/mips/mips_example_008.test.mts | 37 +--- .../unit/arch/mips/mips_example_011.test.mts | 40 +--- .../unit/arch/mips/mips_example_012.test.mts | 39 +--- tests/unit/arch/riscv/example_001.test.mts | 62 ++---- tests/unit/arch/riscv/example_002.test.mts | 111 +++++------ tests/unit/arch/riscv/example_003.test.mts | 78 +++----- tests/unit/arch/riscv/example_004.test.mts | 180 ++++++++---------- tests/unit/arch/riscv/example_005.test.mts | 54 ++---- tests/unit/arch/riscv/example_006.test.mts | 58 ++---- tests/unit/arch/riscv/example_007.test.mts | 37 +--- tests/unit/arch/riscv/example_008.test.mts | 76 +++----- tests/unit/arch/riscv/example_011.test.mts | 56 ++---- tests/unit/arch/riscv/example_012.test.mts | 55 ++---- tests/unit/arch/riscv/example_013.test.mts | 40 ++-- .../arch/riscv/floating_point_demo.test.mts | 12 +- tests/unit/arch/simulator-test-utils.mts | 25 +++ 22 files changed, 415 insertions(+), 787 deletions(-) diff --git a/tests/unit/arch/mips/mips_example_002.test.mts b/tests/unit/arch/mips/mips_example_002.test.mts index eaa100dea..ae1d29b32 100644 --- a/tests/unit/arch/mips/mips_example_002.test.mts +++ b/tests/unit/arch/mips/mips_example_002.test.mts @@ -1,44 +1,27 @@ -import { assertEquals } from "https://deno.land/std/assert/mod.ts"; -import { - setupSimulator, - executeN, - cleanupSimulator, - assertSimulatorState, -} from "../simulator-test-utils.mts"; - -Deno.test("MIPS Basic Arithmetic Operations", async () => { - const testAssembly = ` +import { assertExecution } from "../simulator-test-utils.mts"; +const testAssembly = ` # # Creator (https://creatorsim.github.io/creator/) # .text main: - + li $t0, 10 li $t1, 13 li $t2, 45 li $t3, 33 - + add $t4, $t0, $t1 # 10+13 sub $t5, $t2, $t3 # 45-33 mul $t6, $t3, $t3 # 33*33 div $t7, $t6, $t1 # $t6/13 +`; - `; - - const MIPS_ARCH_PATH = "../../../architecture/MIPS32.yml"; - - // Setup simulator with MIPS architecture - await setupSimulator(testAssembly, MIPS_ARCH_PATH); - - // Execute the program - const result = executeN(1000); - assertEquals(result.error, false, "Execution should not error"); - - // Assert all expected state using the wrapper function - assertSimulatorState({ +Deno.test( + "MIPS Basic Arithmetic Operations", + assertExecution("MIPS32.yml", testAssembly, { registers: { r8: 0xan, // t0 = 10 r9: 0xdn, // t1 = 13 @@ -51,7 +34,5 @@ main: }, display: "", // Display buffer should be empty keyboard: "", // Keyboard buffer should be empty - }); - - cleanupSimulator(); -}); + }), +); diff --git a/tests/unit/arch/mips/mips_example_003.test.mts b/tests/unit/arch/mips/mips_example_003.test.mts index b63d0c45d..0ee22eba5 100644 --- a/tests/unit/arch/mips/mips_example_003.test.mts +++ b/tests/unit/arch/mips/mips_example_003.test.mts @@ -1,14 +1,6 @@ -import { assertEquals } from "https://deno.land/std/assert/mod.ts"; -import { - setupSimulator, - executeN, - cleanupSimulator, - assertSimulatorState, -} from "../simulator-test-utils.mts"; - -Deno.test("MIPS Data Types and Memory Operations", async () => { - const testAssembly = ` +import { assertExecution } from "../simulator-test-utils.mts"; +const testAssembly = ` # # Creator (https://creatorsim.github.io/creator/) # @@ -27,37 +19,28 @@ Deno.test("MIPS Data Types and Memory Operations", async () => { .text main: - + la $t0, w1 #w1 address -> $t0 la $t1, b1 #b1 address -> $t1 la $t2, h1 #h1 address -> $t2 - + lw $t3, 0($t0) #Memory[$t0] -> $t3 lw $t4, w1 #Memory[w1] -> $t4 - + lb $t5, 0($t1) #Memory[$t1] -> $t5 lb $t6, b1 #Memory[b1] -> $t6 - + lh $t7, 0($t2) #Memory[$t2] -> $t7 lh $t8, h1 #Memory[h1] -> $t8 - + sw $t3, w2 #$t3 -> Memory[w2] sb $t5, b2 #$t5 -> Memory[b2] sh $t7, h2 #$t7 -> Memory[h2] +`; - `; - - const MIPS_ARCH_PATH = "../../../architecture/MIPS32.yml"; - - // Setup simulator with MIPS architecture - await setupSimulator(testAssembly, MIPS_ARCH_PATH); - - // Execute the program - const result = executeN(1000); - assertEquals(result.error, false, "Execution should not error"); - - // Assert all expected state using the wrapper function - assertSimulatorState({ +Deno.test( + "MIPS Data Types and Memory Operations", + assertExecution("MIPS32.yml", testAssembly, { registers: { r1: 0x20000en, // at r8: 0x200000n, // t0 @@ -77,7 +60,5 @@ main: }, display: "", // Display buffer should be empty keyboard: "", // Keyboard buffer should be empty - }); - - cleanupSimulator(); -}); + }), +); diff --git a/tests/unit/arch/mips/mips_example_004.test.mts b/tests/unit/arch/mips/mips_example_004.test.mts index 799293147..2d29e4c21 100644 --- a/tests/unit/arch/mips/mips_example_004.test.mts +++ b/tests/unit/arch/mips/mips_example_004.test.mts @@ -1,31 +1,24 @@ -import { assertEquals } from "https://deno.land/std/assert/mod.ts"; -import { - setupSimulator, - executeN, - cleanupSimulator, - assertSimulatorState, -} from "../simulator-test-utils.mts"; +import { assertExecution } from "../simulator-test-utils.mts"; -Deno.test("MIPS Floating Point Operations", async () => { - const testAssembly = ` +const testAssembly = ` # # Creator (https://creatorsim.github.io/creator/) # - + .data a: .double 34.544 b: .double 11.443 c: .double 665.4 - + d: .space 24 - + .text main: la $t0, a la $t1, b la $t2, c la $t3, d - + l.d $f0, 0($t0) l.d $f2, 0($t1) l.d $f10, 0($t2) @@ -41,20 +34,12 @@ main: li $v0, 10 syscall +`; - `; - - const MIPS_ARCH_PATH = "../../../architecture/MIPS32.yml"; - - // Setup simulator with MIPS architecture - await setupSimulator(testAssembly, MIPS_ARCH_PATH); - - // Execute the program - const result = executeN(1000); - assertEquals(result.error, false, "Execution should not error"); - // TODO: finish the conditions below - // Assert all expected state using the wrapper function - assertSimulatorState({ +Deno.test( + "MIPS Floating Point Operations", + assertExecution("MIPS32.yml", testAssembly, { + // TODO: finish the conditions below registers: { r1: 0x200018n, // at r2: 0xan, // v0 @@ -65,7 +50,5 @@ main: }, display: "", // Display buffer should be empty keyboard: "", // Keyboard buffer should be empty - }); - - cleanupSimulator(); -}); + }), +); diff --git a/tests/unit/arch/mips/mips_example_005.test.mts b/tests/unit/arch/mips/mips_example_005.test.mts index 698ee5827..19c0fea79 100644 --- a/tests/unit/arch/mips/mips_example_005.test.mts +++ b/tests/unit/arch/mips/mips_example_005.test.mts @@ -1,14 +1,6 @@ -import { assertEquals } from "https://deno.land/std/assert/mod.ts"; -import { - setupSimulator, - executeN, - cleanupSimulator, - assertSimulatorState, -} from "../simulator-test-utils.mts"; - -Deno.test("MIPS Loop and Print Sum", async () => { - const testAssembly = ` +import { assertExecution } from "../simulator-test-utils.mts"; +const testAssembly = ` # # Creator (https://creatorsim.github.io/creator/) # @@ -27,22 +19,11 @@ Deno.test("MIPS Loop and Print Sum", async () => { end_while: li $v0, 1 syscall #print_int +`; - - - `; - - const MIPS_ARCH_PATH = "../../../architecture/MIPS32.yml"; - - // Setup simulator with MIPS architecture - await setupSimulator(testAssembly, MIPS_ARCH_PATH); - - // Execute the program - const result = executeN(1000); - assertEquals(result.error, false, "Execution should not error"); - - // Assert all expected state using the wrapper function - assertSimulatorState({ +Deno.test( + "MIPS Loop and Print Sum", + assertExecution("MIPS32.yml", testAssembly, { registers: { r2: 0x1n, // v0 r4: 0x2dn, // a0 = 45 @@ -51,7 +32,5 @@ Deno.test("MIPS Loop and Print Sum", async () => { }, display: "45", // Should display '45' keyboard: "", // Keyboard buffer should be empty - }); - - cleanupSimulator(); -}); + }), +); diff --git a/tests/unit/arch/mips/mips_example_006.test.mts b/tests/unit/arch/mips/mips_example_006.test.mts index eb988f863..e06aa3b57 100644 --- a/tests/unit/arch/mips/mips_example_006.test.mts +++ b/tests/unit/arch/mips/mips_example_006.test.mts @@ -1,14 +1,6 @@ -import { assertEquals } from "https://deno.land/std/assert/mod.ts"; -import { - setupSimulator, - executeN, - cleanupSimulator, - assertSimulatorState, -} from "../simulator-test-utils.mts"; - -Deno.test("MIPS Branching Instructions", async () => { - const testAssembly = ` +import { assertExecution } from "../simulator-test-utils.mts"; +const testAssembly = ` # # Creator (https://creatorsim.github.io/creator/) # @@ -18,8 +10,8 @@ Deno.test("MIPS Branching Instructions", async () => { li $t0, 4 li $t1, 2 ble $t0, 5, jump1 - - jump2: + + jump2: li $t3, 34 li $v0, 10 syscall @@ -28,20 +20,11 @@ Deno.test("MIPS Branching Instructions", async () => { li $t9, 11 li $t8, 555 b jump2 +`; - `; - - const MIPS_ARCH_PATH = "../../../architecture/MIPS32.yml"; - - // Setup simulator with MIPS architecture - await setupSimulator(testAssembly, MIPS_ARCH_PATH); - - // Execute the program - const result = executeN(1000); - assertEquals(result.error, false, "Execution should not error"); - - // Assert all expected state using the wrapper function - assertSimulatorState({ +Deno.test( + "MIPS Branching Instructions", + assertExecution("MIPS32.yml", testAssembly, { registers: { r1: 0x1n, // at r2: 0xan, // v0 @@ -53,7 +36,5 @@ Deno.test("MIPS Branching Instructions", async () => { }, display: "", // Display buffer should be empty keyboard: "", // Keyboard buffer should be empty - }); - - cleanupSimulator(); -}); + }), +); diff --git a/tests/unit/arch/mips/mips_example_007.test.mts b/tests/unit/arch/mips/mips_example_007.test.mts index 25215688c..e8e872c71 100644 --- a/tests/unit/arch/mips/mips_example_007.test.mts +++ b/tests/unit/arch/mips/mips_example_007.test.mts @@ -1,14 +1,6 @@ -import { assertEquals } from "https://deno.land/std/assert/mod.ts"; -import { - setupSimulator, - executeN, - cleanupSimulator, - assertSimulatorState, -} from "../simulator-test-utils.mts"; - -Deno.test("MIPS Array Sum Loop", async () => { - const testAssembly = ` +import { assertExecution } from "../simulator-test-utils.mts"; +const testAssembly = ` # # Creator (https://creatorsim.github.io/creator/) # @@ -41,25 +33,14 @@ loop1: beq $t1, $t2, end1 #if($t1 == $t2) --> jump to fin1 b loop1 # loop end -end1: +end1: li $v0, 10 syscall +`; - - - `; - - const MIPS_ARCH_PATH = "../../../architecture/MIPS32.yml"; - - // Setup simulator with MIPS architecture - await setupSimulator(testAssembly, MIPS_ARCH_PATH); - - // Execute the program - const result = executeN(1000); - assertEquals(result.error, false, "Execution should not error"); - - // Assert all expected state using the wrapper function - assertSimulatorState({ +Deno.test( + "MIPS Array Sum Loop", + assertExecution("MIPS32.yml", testAssembly, { registers: { PC: 0x44n, r1: 0x200000n, // at @@ -74,7 +55,5 @@ end1: }, display: "", // Display buffer should be empty keyboard: "", // Keyboard buffer should be empty - }); - - cleanupSimulator(); -}); + }), +); diff --git a/tests/unit/arch/mips/mips_example_008.test.mts b/tests/unit/arch/mips/mips_example_008.test.mts index 1f172c007..e688cd312 100644 --- a/tests/unit/arch/mips/mips_example_008.test.mts +++ b/tests/unit/arch/mips/mips_example_008.test.mts @@ -1,14 +1,6 @@ -import { assertEquals } from "https://deno.land/std/assert/mod.ts"; -import { - setupSimulator, - executeN, - cleanupSimulator, - assertSimulatorState, -} from "../simulator-test-utils.mts"; - -Deno.test("MIPS Matrix Copy with Floats", async () => { - const testAssembly = ` +import { assertExecution } from "../simulator-test-utils.mts"; +const testAssembly = ` # # Creator (https://creatorsim.github.io/creator/) # @@ -33,7 +25,7 @@ main: li $t3, 4 move $t4, $zero move $t5, $zero - + loop1: beq $t2, $t4, end1 loop2: beq $t3, $t5, end2 l.s $f0, 0($t0) @@ -47,20 +39,11 @@ end2: addi $t4, $t4, 1 b loop1 end1: li $v0, 10 syscall +`; - `; - - const MIPS_ARCH_PATH = "../../../architecture/MIPS32.yml"; - - // Setup simulator with MIPS architecture - await setupSimulator(testAssembly, MIPS_ARCH_PATH); - - // Execute the program - const result = executeN(1000); - assertEquals(result.error, false, "Execution should not error"); - - // Assert all expected state using the wrapper function - assertSimulatorState({ +Deno.test( + "MIPS Matrix Copy with Floats", + assertExecution("MIPS32.yml", testAssembly, { registers: { r1: 0x200040n, // at r2: 0xan, // v0 @@ -117,7 +100,5 @@ end1: li $v0, 10 }, display: "", // Display buffer should be empty keyboard: "", // Keyboard buffer should be empty - }); - - cleanupSimulator(); -}); + }), +); diff --git a/tests/unit/arch/mips/mips_example_011.test.mts b/tests/unit/arch/mips/mips_example_011.test.mts index 379ef3f58..3e488fd2a 100644 --- a/tests/unit/arch/mips/mips_example_011.test.mts +++ b/tests/unit/arch/mips/mips_example_011.test.mts @@ -1,14 +1,6 @@ -import { assertEquals } from "https://deno.land/std/assert/mod.ts"; -import { - setupSimulator, - executeN, - cleanupSimulator, - assertSimulatorState, -} from "../simulator-test-utils.mts"; - -Deno.test("MIPS Function Calls", async () => { - const testAssembly = ` +import { assertExecution } from "../simulator-test-utils.mts"; +const testAssembly = ` # # Creator (https://creatorsim.github.io/creator/) # @@ -28,32 +20,22 @@ main: syscall li $v0, 10 syscall - + sum: add $t1, $a0, $a1 add $t2, $a2, $a2 move $v0, $t1 move $v1, $t2 - jr $ra + jr $ra sub: sub $v0, $a0, $a1 jr $ra - - - `; +`; - const MIPS_ARCH_PATH = "../../../architecture/MIPS32.yml"; - - // Setup simulator with MIPS architecture - await setupSimulator(testAssembly, MIPS_ARCH_PATH); - - // Execute the program - const result = executeN(1000); - assertEquals(result.error, false, "Execution should not error"); - - // Assert all expected state using the wrapper function - assertSimulatorState({ +Deno.test( + "MIPS Function Calls", + assertExecution("MIPS32.yml", testAssembly, { registers: { PC: 0x38n, r1: 0xffffffb3n, // at @@ -68,7 +50,5 @@ sub: }, display: "-144", // Should display '-144' keyboard: "", // Keyboard buffer should be empty - }); - - cleanupSimulator(); -}); + }), +); diff --git a/tests/unit/arch/mips/mips_example_012.test.mts b/tests/unit/arch/mips/mips_example_012.test.mts index 0fd08c544..702559876 100644 --- a/tests/unit/arch/mips/mips_example_012.test.mts +++ b/tests/unit/arch/mips/mips_example_012.test.mts @@ -1,14 +1,6 @@ -import { assertEquals } from "https://deno.land/std/assert/mod.ts"; -import { - setupSimulator, - executeN, - cleanupSimulator, - assertSimulatorState, -} from "../simulator-test-utils.mts"; - -Deno.test("MIPS Recursive Factorial", async () => { - const testAssembly = ` +import { assertExecution } from "../simulator-test-utils.mts"; +const testAssembly = ` # # ARCOS.INF.UC3M.ES # BY-NC-SA (https://creativecommons.org/licenses/by-nc-sa/4.0/deed.es) @@ -17,7 +9,7 @@ Deno.test("MIPS Recursive Factorial", async () => { .text - main: + main: # v1 = factorial(5) li $a0, 5 jal factorial @@ -42,7 +34,7 @@ factorial: # if ($a < 2): # return 1 bge $a0, 2, b_else - li $v0, 1 + li $v0, 1 b b_efs # else: # return $a0 * factorial($a0 - 1) @@ -59,20 +51,11 @@ factorial: # return $v0 jr $ra +`; - `; - - const MIPS_ARCH_PATH = "../../../architecture/MIPS32.yml"; - - // Setup simulator with MIPS architecture - await setupSimulator(testAssembly, MIPS_ARCH_PATH); - - // Execute the program - const result = executeN(1000); - assertEquals(result.error, false, "Execution should not error"); - - // Assert all expected state using the wrapper function - assertSimulatorState({ +Deno.test( + "MIPS Recursive Factorial", + assertExecution("MIPS32.yml", testAssembly, { registers: { PC: 0x1cn, r1: 0x1n, // at @@ -83,7 +66,5 @@ factorial: }, display: "120", // Should display '120' keyboard: "", // Keyboard buffer should be empty - }); - - cleanupSimulator(); -}); + }), +); diff --git a/tests/unit/arch/riscv/example_001.test.mts b/tests/unit/arch/riscv/example_001.test.mts index 4cafdc26f..38196a9da 100644 --- a/tests/unit/arch/riscv/example_001.test.mts +++ b/tests/unit/arch/riscv/example_001.test.mts @@ -1,36 +1,26 @@ -import { assertEquals } from "https://deno.land/std/assert/mod.ts"; -import { - setupSimulator, - executeN, - cleanupSimulator, - assertSimulatorState, -} from "../simulator-test-utils.mts"; - -Deno.test( - "Architecture-agnostic testing - RISC-V Basic Data Types and Print Operations", - async () => { - const testAssembly = ` +import { assertExecution } from "../simulator-test-utils.mts"; +const testAssembly = ` # # Creator (https://creatorsim.github.io/creator/) # .data - + byte: .byte 12 - + .align 1 half: .half 34 - + .text main: - - # print byte value + + # print byte value la a0, byte lb a0, 0(a0) li a7, 1 ecall - + # print half value la a0, half lh a0, 0(a0) @@ -40,31 +30,15 @@ Deno.test( # exit program li a7, 10 ecall +`; - `; - - const RISCV_ARCH_PATH = "../../../architecture/RISCV/RV32IMFD.yml"; - - // Setup simulator with RISC-V architecture - await setupSimulator(testAssembly, RISCV_ARCH_PATH); - - // Execute the program - const result = executeN(1000); - assertEquals( - result.error, - false, - `Execution should not error. ${result.output}`, - ); - - // Assert all expected state using the wrapper function - assertSimulatorState({ - registers: { - a0: 0x22n, // a0 should contain 34 (0x22) - }, - display: "1234", // Should show '1234' (12 followed by 34) - keyboard: "", // Keyboard buffer should be empty - }); - - cleanupSimulator(); - }, +Deno.test( + "Architecture-agnostic testing - RISC-V Basic Data Types and Print Operations", + assertExecution("RISCV/RV32IMFD.yml", testAssembly, { + registers: { + a0: 0x22n, // a0 should contain 34 (0x22) + }, + display: "1234", // Should show '1234' (12 followed by 34) + keyboard: "", // Keyboard buffer should be empty + }), ); diff --git a/tests/unit/arch/riscv/example_002.test.mts b/tests/unit/arch/riscv/example_002.test.mts index 1c30b9995..a3ab71f8b 100644 --- a/tests/unit/arch/riscv/example_002.test.mts +++ b/tests/unit/arch/riscv/example_002.test.mts @@ -1,16 +1,6 @@ -import { assertEquals } from "https://deno.land/std/assert/mod.ts"; -import { - setupSimulator, - executeN, - cleanupSimulator, - assertSimulatorState, -} from "../simulator-test-utils.mts"; +import { assertExecution } from "../simulator-test-utils.mts"; -Deno.test( - "Architecture-agnostic testing - RISC-V Store Hello World without Data Segment", - - async () => { - const testAssembly = ` +const testAssembly = ` # # Creator (https://creatorsim.github.io/creator/) # Example: Store "hello world" byte by byte without data segment @@ -18,102 +8,91 @@ Deno.test( .text main: - # Use a base memory address + # Use a base memory address li t1, 0x200000 - + # Store "hello world" byte by byte # 'h' = 104 li t0, 104 sb t0, 0(t1) - - # 'e' = 101 + + # 'e' = 101 li t0, 101 sb t0, 1(t1) - + # 'l' = 108 li t0, 108 sb t0, 2(t1) - + # 'l' = 108 li t0, 108 sb t0, 3(t1) - + # 'o' = 111 li t0, 111 sb t0, 4(t1) - + # ' ' = 32 (space) li t0, 32 sb t0, 5(t1) - + # 'w' = 119 li t0, 119 sb t0, 6(t1) - + # 'o' = 111 li t0, 111 sb t0, 7(t1) - + # 'r' = 114 li t0, 114 sb t0, 8(t1) - + # 'l' = 108 li t0, 108 sb t0, 9(t1) - + # 'd' = 100 li t0, 100 sb t0, 10(t1) - + # null terminator = 0 li t0, 0 sb t0, 11(t1) - + # Print the string (system call 4 - print string) mv a0, t1 # address of string li a7, 4 # system call for print string ecall - + # exit program li a7, 10 ecall - `; - - const RISCV_ARCH_PATH = "../../../architecture/RISCV/RV32IMFD.yml"; - - // Setup simulator with RISC-V architecture - await setupSimulator(testAssembly, RISCV_ARCH_PATH); - - // Execute the program - const result = executeN(1000); - assertEquals(result.error, false, "Execution should not error"); - - // Assert all expected state using the wrapper function - assertSimulatorState({ - registers: { - x5: 0x0n, // t0 - last value stored - x6: 0x200000n, // t1 - base address - x10: 0x200000n, // a0 - string address - }, - memory: { - "0x200000": 0x68n, // 'h' = 104 - "0x200001": 0x65n, // 'e' = 101 - "0x200002": 0x6cn, // 'l' = 108 - "0x200003": 0x6cn, // 'l' = 108 - "0x200004": 0x6fn, // 'o' = 111 - "0x200005": 0x20n, // ' ' = 32 (space) - "0x200006": 0x77n, // 'w' = 119 - "0x200007": 0x6fn, // 'o' = 111 - "0x200008": 0x72n, // 'r' = 114 - "0x200009": 0x6cn, // 'l' = 108 - "0x20000a": 0x64n, // 'd' = 100 - "0x20000b": 0x0n, // null terminator - }, - display: "hello world", - keyboard: "", - }); - - cleanupSimulator(); - }, +`; + +Deno.test( + "Architecture-agnostic testing - RISC-V Store Hello World without Data Segment", + assertExecution("RISCV/RV32IMFD.yml", testAssembly, { + registers: { + x5: 0x0n, // t0 - last value stored + x6: 0x200000n, // t1 - base address + x10: 0x200000n, // a0 - string address + }, + memory: { + "0x200000": 0x68n, // 'h' = 104 + "0x200001": 0x65n, // 'e' = 101 + "0x200002": 0x6cn, // 'l' = 108 + "0x200003": 0x6cn, // 'l' = 108 + "0x200004": 0x6fn, // 'o' = 111 + "0x200005": 0x20n, // ' ' = 32 (space) + "0x200006": 0x77n, // 'w' = 119 + "0x200007": 0x6fn, // 'o' = 111 + "0x200008": 0x72n, // 'r' = 114 + "0x200009": 0x6cn, // 'l' = 108 + "0x20000a": 0x64n, // 'd' = 100 + "0x20000b": 0x0n, // null terminator + }, + display: "hello world", + keyboard: "", + }), ); diff --git a/tests/unit/arch/riscv/example_003.test.mts b/tests/unit/arch/riscv/example_003.test.mts index 6c8003c53..5d8c4e50b 100644 --- a/tests/unit/arch/riscv/example_003.test.mts +++ b/tests/unit/arch/riscv/example_003.test.mts @@ -1,16 +1,6 @@ -import { assertEquals } from "https://deno.land/std/assert/mod.ts"; -import { - setupSimulator, - executeN, - cleanupSimulator, - assertSimulatorState, -} from "../simulator-test-utils.mts"; - -Deno.test( - "Architecture-agnostic testing - RISC-V Load and Store Operations", - async () => { - const testAssembly = ` +import { assertExecution } from "../simulator-test-utils.mts"; +const testAssembly = ` # # Creator (https://creatorsim.github.io/creator/) # @@ -29,13 +19,13 @@ Deno.test( .text main: - + la t0, w1 # w1 address -> t0 lw t3, 0(t0) # Memory[t0] -> t3 la t1, b1 # b1 address -> t1 lb t4, 0(t1) # Memory[t1] -> t4 - + la t2, h1 # h1 address -> t2 lh t5, 0 (t2) # Memory[t2] -> t5 @@ -47,44 +37,32 @@ main: la t0, h2 # h2 address -> t0 sh t5, 0(t0) # t5 -> Memory[h2] - + # exit program li a7, 10 ecall +`; - `; - - const RISCV_ARCH_PATH = "../../../architecture/RISCV/RV32IMFD.yml"; - - // Setup simulator with RISC-V architecture - await setupSimulator(testAssembly, RISCV_ARCH_PATH); - - // Execute the program - const result = executeN(1000); - assertEquals(result.error, false, "Execution should not error"); - - // Assert all expected state using the wrapper function - assertSimulatorState({ - registers: { - x5: 0x20000en, // t0 - h2 address - x6: 0x200004n, // t1 - b1 address - x7: 0x200006n, // t2 - h1 address - x28: 0xen, // t3 - loaded w1 value - x29: 0x78n, // t4 - loaded b1 value (120) - x30: 0x16n, // t5 - loaded h1 value - }, - memory: { - "0x200003": 0xen, // w1 = 14 - "0x200004": 0x78n, // b1 = 120 - "0x200007": 0x16n, // h1 = 22 - "0x20000b": 0xen, // w2 = copied from w1 - "0x20000c": 0x78n, // b2 = copied from b1 - "0x20000f": 0x16n, // h2 = copied from h1 - }, - display: "", - keyboard: "", - }); - - cleanupSimulator(); - }, +Deno.test( + "Architecture-agnostic testing - RISC-V Load and Store Operations", + assertExecution("RISCV/RV32IMFD.yml", testAssembly, { + registers: { + x5: 0x20000en, // t0 - h2 address + x6: 0x200004n, // t1 - b1 address + x7: 0x200006n, // t2 - h1 address + x28: 0xen, // t3 - loaded w1 value + x29: 0x78n, // t4 - loaded b1 value (120) + x30: 0x16n, // t5 - loaded h1 value + }, + memory: { + "0x200003": 0xen, // w1 = 14 + "0x200004": 0x78n, // b1 = 120 + "0x200007": 0x16n, // h1 = 22 + "0x20000b": 0xen, // w2 = copied from w1 + "0x20000c": 0x78n, // b2 = copied from b1 + "0x20000f": 0x16n, // h2 = copied from h1 + }, + display: "", + keyboard: "", + }), ); diff --git a/tests/unit/arch/riscv/example_004.test.mts b/tests/unit/arch/riscv/example_004.test.mts index e3cab9647..fe2bf33ce 100644 --- a/tests/unit/arch/riscv/example_004.test.mts +++ b/tests/unit/arch/riscv/example_004.test.mts @@ -1,43 +1,32 @@ -import { assertEquals } from "https://deno.land/std/assert/mod.ts"; -import { - setupSimulator, - executeN, - cleanupSimulator, - assertSimulatorState, -} from "../simulator-test-utils.mts"; -// This test has been verified with SPIKE -Deno.test( - "Architecture-agnostic testing - RISC-V Double Precision Floating Point Operations", - // eslint-disable-next-line max-lines-per-function - async () => { - const testAssembly = ` +import { assertExecution } from "../simulator-test-utils.mts"; +const testAssembly = ` # # Creator (https://creatorsim.github.io/creator/) # - + .data a: .double 34.544 b: .double 11.443 c: .double 665.4 - + d: .zero 24 - + .text main: - + la x5, a la x6, b la x7, c la x8, d - + fld f0, 0(x5) fld f2, 0(x6) fld f10, 0(x7) fadd.d f0, f0, f0 fsub.d f4, f10, f0 fdiv.d f12, f10, f2 - + fsd f0, 0(x8) addi x8, x8, 8 fsd f4, 0(x8) @@ -47,87 +36,76 @@ main: # exit program li a7, 10 ecall +`; - `; - - const RISCV_ARCH_PATH = "../../../architecture/RISCV/RV32IMFD.yml"; - - // Setup simulator with RISC-V architecture - await setupSimulator(testAssembly, RISCV_ARCH_PATH); - - // Execute the program - const result = executeN(1000); - assertEquals(result.error, false, "Execution should not error"); - - // Assert all expected state using the wrapper function - assertSimulatorState({ - registers: { - x5: 0x200000n, // should contain 0x200000 - x6: 0x200008n, // should contain 0x200008 - x7: 0x200010n, // should contain 0x200010 - x8: 0x200028n, // should contain 0x200028 - f0: 0x405145a1cac08312n, // should contain 0x405145A1CAC08312 - f2: 0x4026e2d0e5604189n, // should contain 0x4026E2D0E5604189 - f4: 0x4082a27ef9db22d1n, // should contain 0x4082A27EF9DB22D1 - f10: 0x4084cb3333333333n, // should contain 0x4084CB3333333333 - f12: 0x404d13154689c3e9n, // should contain 0x404D13154689C3E9 - }, - memory: { - // Original double values in memory - "0x200000": 0x40n, - "0x200001": 0x41n, - "0x200002": 0x45n, - "0x200003": 0xa1n, - "0x200004": 0xcan, - "0x200005": 0xc0n, - "0x200006": 0x83n, - "0x200007": 0x12n, // a: 34.544 - "0x200008": 0x40n, - "0x200009": 0x26n, - "0x20000a": 0xe2n, - "0x20000b": 0xd0n, - "0x20000c": 0xe5n, - "0x20000d": 0x60n, - "0x20000e": 0x41n, - "0x20000f": 0x89n, // b: 11.443 - "0x200010": 0x40n, - "0x200011": 0x84n, - "0x200012": 0xcbn, - "0x200013": 0x33n, - "0x200014": 0x33n, - "0x200015": 0x33n, - "0x200016": 0x33n, - "0x200017": 0x33n, // c: 665.4 - // Results stored by the program - "0x200018": 0x40n, - "0x200019": 0x51n, - "0x20001a": 0x45n, - "0x20001b": 0xa1n, - "0x20001c": 0xcan, - "0x20001d": 0xc0n, - "0x20001e": 0x83n, - "0x20001f": 0x12n, // f0: fadd.d result - "0x200020": 0x40n, - "0x200021": 0x82n, - "0x200022": 0xa2n, - "0x200023": 0x7en, - "0x200024": 0xf9n, - "0x200025": 0xdbn, - "0x200026": 0x22n, - "0x200027": 0xd1n, // f4: fsub.d result - "0x200028": 0x40n, - "0x200029": 0x4dn, - "0x20002a": 0x13n, - "0x20002b": 0x15n, - "0x20002c": 0x46n, - "0x20002d": 0x89n, - "0x20002e": 0xc3n, - "0x20002f": 0xe9n, // f12: fdiv.d result - }, - display: "", // Display buffer should be empty - keyboard: "", // Keyboard buffer should be empty - }); - - cleanupSimulator(); - }, +// This test has been verified with SPIKE +Deno.test( + "Architecture-agnostic testing - RISC-V Double Precision Floating Point Operations", + assertExecution("RISCV/RV32IMFD.yml", testAssembly, { + registers: { + x5: 0x200000n, + x6: 0x200008n, + x7: 0x200010n, + x8: 0x200028n, + f0: 0x405145a1cac08312n, + f2: 0x4026e2d0e5604189n, + f4: 0x4082a27ef9db22d1n, + f10: 0x4084cb3333333333n, + f12: 0x404d13154689c3e9n, + }, + memory: { + // Original double values in memory + "0x200000": 0x40n, + "0x200001": 0x41n, + "0x200002": 0x45n, + "0x200003": 0xa1n, + "0x200004": 0xcan, + "0x200005": 0xc0n, + "0x200006": 0x83n, + "0x200007": 0x12n, // a: 34.544 + "0x200008": 0x40n, + "0x200009": 0x26n, + "0x20000a": 0xe2n, + "0x20000b": 0xd0n, + "0x20000c": 0xe5n, + "0x20000d": 0x60n, + "0x20000e": 0x41n, + "0x20000f": 0x89n, // b: 11.443 + "0x200010": 0x40n, + "0x200011": 0x84n, + "0x200012": 0xcbn, + "0x200013": 0x33n, + "0x200014": 0x33n, + "0x200015": 0x33n, + "0x200016": 0x33n, + "0x200017": 0x33n, // c: 665.4 + // Results stored by the program + "0x200018": 0x40n, + "0x200019": 0x51n, + "0x20001a": 0x45n, + "0x20001b": 0xa1n, + "0x20001c": 0xcan, + "0x20001d": 0xc0n, + "0x20001e": 0x83n, + "0x20001f": 0x12n, // f0: fadd.d result + "0x200020": 0x40n, + "0x200021": 0x82n, + "0x200022": 0xa2n, + "0x200023": 0x7en, + "0x200024": 0xf9n, + "0x200025": 0xdbn, + "0x200026": 0x22n, + "0x200027": 0xd1n, // f4: fsub.d result + "0x200028": 0x40n, + "0x200029": 0x4dn, + "0x20002a": 0x13n, + "0x20002b": 0x15n, + "0x20002c": 0x46n, + "0x20002d": 0x89n, + "0x20002e": 0xc3n, + "0x20002f": 0xe9n, // f12: fdiv.d result + }, + display: "", // Display buffer should be empty + keyboard: "", // Keyboard buffer should be empty + }), ); diff --git a/tests/unit/arch/riscv/example_005.test.mts b/tests/unit/arch/riscv/example_005.test.mts index 959c3b7ff..03aeb701d 100644 --- a/tests/unit/arch/riscv/example_005.test.mts +++ b/tests/unit/arch/riscv/example_005.test.mts @@ -1,16 +1,6 @@ -import { assertEquals } from "https://deno.land/std/assert/mod.ts"; -import { - setupSimulator, - executeN, - cleanupSimulator, - assertSimulatorState, -} from "../simulator-test-utils.mts"; - -Deno.test( - "Architecture-agnostic testing - RISC-V Sum of First 10 Numbers", - async () => { - const testAssembly = ` +import { assertExecution } from "../simulator-test-utils.mts"; +const testAssembly = ` # # Creator (https://creatorsim.github.io/creator/) # @@ -20,12 +10,12 @@ Deno.test( max: .byte 10 .text - main: + main: la t0, max lb t0, 0 (t0) li t1, 0 li a0, 0 - + while: bge t1, t0, end_while add a0, a0, t1 addi t1, t1, 1 @@ -37,29 +27,17 @@ Deno.test( # exit program li a7, 10 ecall +`; - `; - - const RISCV_ARCH_PATH = "../../../architecture/RISCV/RV32IMFD.yml"; - - // Setup simulator with RISC-V architecture - await setupSimulator(testAssembly, RISCV_ARCH_PATH); - - // Execute the program - const result = executeN(1000); - assertEquals(result.error, false, "Execution should not error"); - - // Assert all expected state using the wrapper function - assertSimulatorState({ - registers: { - x5: 0xan, // t0 should contain 0xa (10) - x6: 0xan, // t1 should contain 0xa (10 - loop counter after completion) - x10: 0x2dn, // a0 should contain 0x2d (45 - sum of 0+1+2+...+9) - }, - display: "45", // Display should show '45' - keyboard: "", // Keyboard buffer should be empty - }); - - cleanupSimulator(); - }, +Deno.test( + "Architecture-agnostic testing - RISC-V Sum of First 10 Numbers", + assertExecution("RISCV/RV32IMFD.yml", testAssembly, { + registers: { + x5: 0xan, // t0 should contain 0xa (10) + x6: 0xan, // t1 should contain 0xa (10 - loop counter after completion) + x10: 0x2dn, // a0 should contain 0x2d (45 - sum of 0+1+2+...+9) + }, + display: "45", // Display should show '45' + keyboard: "", // Keyboard buffer should be empty + }), ); diff --git a/tests/unit/arch/riscv/example_006.test.mts b/tests/unit/arch/riscv/example_006.test.mts index 6b6d93d9f..a83ea0a76 100644 --- a/tests/unit/arch/riscv/example_006.test.mts +++ b/tests/unit/arch/riscv/example_006.test.mts @@ -1,16 +1,6 @@ -import { assertEquals } from "https://deno.land/std/assert/mod.ts"; -import { - setupSimulator, - executeN, - cleanupSimulator, - assertSimulatorState, -} from "../simulator-test-utils.mts"; - -Deno.test( - "Architecture-agnostic testing - RISC-V Branch and Jump Operations", - async () => { - const testAssembly = ` +import { assertExecution } from "../simulator-test-utils.mts"; +const testAssembly = ` # # Creator (https://creatorsim.github.io/creator/) # @@ -22,8 +12,8 @@ Deno.test( li t1, 2 li t3, 5 bge t3, t0, jump1 - - jump2: + + jump2: li t3, 34 li a7, 10 ecall @@ -36,32 +26,20 @@ Deno.test( # exit program li a7, 10 ecall - `; - const RISCV_ARCH_PATH = "../../../architecture/RISCV/RV32IMFD.yml"; - - // Setup simulator with RISC-V architecture - await setupSimulator(testAssembly, RISCV_ARCH_PATH); - - // Execute the program - const result = executeN(1000); - assertEquals(result.error, false, "Execution should not error"); - - // Assert all expected state using the wrapper function - assertSimulatorState({ - registers: { - x5: 0x4n, // t0 should contain 0x4 - x6: 0x2n, // t1 should contain 0x2 - x17: 0xan, // a7 should contain 0xa (syscall 10 - exit) - x28: 0x22n, // t3 should contain 0x22 (34 in decimal) - x29: 0xbn, // t4 should contain 0xb (11 in decimal) - x30: 0x22bn, // t5 should contain 0x22b (555 in decimal) - }, - display: "", // Display buffer should be empty - keyboard: "", // Keyboard buffer should be empty - }); - - cleanupSimulator(); - }, +Deno.test( + "Architecture-agnostic testing - RISC-V Branch and Jump Operations", + assertExecution("RISCV/RV32IMFD.yml", testAssembly, { + registers: { + x5: 0x4n, // t0 should contain 0x4 + x6: 0x2n, // t1 should contain 0x2 + x17: 0xan, // a7 should contain 0xa (syscall 10 - exit) + x28: 0x22n, // t3 should contain 0x22 (34 in decimal) + x29: 0xbn, // t4 should contain 0xb (11 in decimal) + x30: 0x22bn, // t5 should contain 0x22b (555 in decimal) + }, + display: "", // Display buffer should be empty + keyboard: "", // Keyboard buffer should be empty + }), ); diff --git a/tests/unit/arch/riscv/example_007.test.mts b/tests/unit/arch/riscv/example_007.test.mts index e3be55599..e38dd8f02 100644 --- a/tests/unit/arch/riscv/example_007.test.mts +++ b/tests/unit/arch/riscv/example_007.test.mts @@ -1,14 +1,6 @@ -import { assertEquals } from "https://deno.land/std/assert/mod.ts"; -import { - setupSimulator, - executeN, - cleanupSimulator, - assertSimulatorState, -} from "../simulator-test-utils.mts"; - -Deno.test("Architecture-agnostic testing - RISC-V Array Sum Loop", async () => { - const testAssembly = ` +import { assertExecution } from "../simulator-test-utils.mts"; +const testAssembly = ` # # Creator (https://creatorsim.github.io/creator/) # @@ -42,24 +34,15 @@ loop1: beq t1, t2, end1 # if(t1 == t2) --> jump to fin1 beq x0, x0, loop1 # loop end -end1: +end1: # exit program li a7, 10 ecall +`; - `; - - const RISCV_ARCH_PATH = "../../../architecture/RISCV/RV32IMFD.yml"; - - // Setup simulator with RISC-V architecture - await setupSimulator(testAssembly, RISCV_ARCH_PATH); - - // Execute the program - const result = executeN(1000); - assertEquals(result.error, false, "Execution should not error"); - - // Assert all expected state using the wrapper function - assertSimulatorState({ +Deno.test( + "Architecture-agnostic testing - RISC-V Array Sum Loop", + assertExecution("RISCV/RV32IMFD.yml", testAssembly, { registers: { x5: 0xfn, // t0 should contain 0xf (15 - sum of 1+2+3+4+5) x6: 0x5n, // t1 should contain 0x5 (loop counter after completion) @@ -71,7 +54,5 @@ end1: }, display: "", // Display buffer should be empty keyboard: "", // Keyboard buffer should be empty - }); - - cleanupSimulator(); -}); + }), +); diff --git a/tests/unit/arch/riscv/example_008.test.mts b/tests/unit/arch/riscv/example_008.test.mts index 2f497014f..2d56fbf31 100644 --- a/tests/unit/arch/riscv/example_008.test.mts +++ b/tests/unit/arch/riscv/example_008.test.mts @@ -1,17 +1,6 @@ -import { assertEquals } from "https://deno.land/std/assert/mod.ts"; -import { - setupSimulator, - executeN, - cleanupSimulator, - assertSimulatorState, -} from "../simulator-test-utils.mts"; - -Deno.test( - "Architecture-agnostic testing - RISC-V Matrix Copy with Floating Point", - - async () => { - const testAssembly = ` +import { assertExecution } from "../simulator-test-utils.mts"; +const testAssembly = ` # # Creator (https://creatorsim.github.io/creator/) # @@ -37,7 +26,7 @@ main: li t3, 4 add t4, zero, zero add t5, zero, zero - + loop1: beq t2, t4, end1 loop2: beq t3, t5, end2 flw f0, 0(t0) @@ -49,43 +38,32 @@ loop2: beq t3, t5, end2 end2: addi t4, t4, 1 add t5, zero, zero beq x0, x0, loop1 -end1: +end1: # exit program li a7, 10 ecall +`; - - `; - const RISCV_ARCH_PATH = "../../../architecture/RISCV/RV32IMFD.yml"; - // Setup simulator with RISC-V architecture - await setupSimulator(testAssembly, RISCV_ARCH_PATH); - - // Execute the program - const result = executeN(1000); - assertEquals(result.error, false, "Execution should not error"); - - // Assert all expected state using the wrapper function - assertSimulatorState({ - registers: { - x5: 0x200040n, - x6: 0x200080n, - x7: 0x4n, - x28: 0x4n, - x29: 0x4n, - f0: 0xffffffff33441124n, - }, - memory: { - "0x20007f": 0x24n, - "0x20007e": 0x11n, - "0x20007d": 0x44n, - "0x20007c": 0x33n, - "0x200040": 0x34n, - "0x200044": 0x34n, - "0x200048": 0x34n, - "0x20004c": 0x34n, - }, - }); - - cleanupSimulator(); - }, +Deno.test( + "Architecture-agnostic testing - RISC-V Matrix Copy with Floating Point", + assertExecution("RISCV/RV32IMFD.yml", testAssembly, { + registers: { + x5: 0x200040n, + x6: 0x200080n, + x7: 0x4n, + x28: 0x4n, + x29: 0x4n, + f0: 0xffffffff33441124n, + }, + memory: { + "0x20007f": 0x24n, + "0x20007e": 0x11n, + "0x20007d": 0x44n, + "0x20007c": 0x33n, + "0x200040": 0x34n, + "0x200044": 0x34n, + "0x200048": 0x34n, + "0x20004c": 0x34n, + }, + }), ); diff --git a/tests/unit/arch/riscv/example_011.test.mts b/tests/unit/arch/riscv/example_011.test.mts index 0689f843f..05d817460 100644 --- a/tests/unit/arch/riscv/example_011.test.mts +++ b/tests/unit/arch/riscv/example_011.test.mts @@ -1,16 +1,6 @@ -import { assertEquals } from "https://deno.land/std/assert/mod.ts"; -import { - setupSimulator, - executeN, - cleanupSimulator, - assertSimulatorState, -} from "../simulator-test-utils.mts"; - -Deno.test( - "Architecture-agnostic testing - RISC-V Function Calls and Stack Operations", - async () => { - const testAssembly = ` +import { assertExecution } from "../simulator-test-utils.mts"; +const testAssembly = ` # # Creator (https://creatorsim.github.io/creator/) # @@ -40,36 +30,24 @@ sum: add t2, a2, a2 add a0, t1, zero add a1, t2, zero - jr ra + jr ra sub: sub a0, a0, a1 jr ra +`; - `; - - const RISCV_ARCH_PATH = "../../../architecture/RISCV/RV32IMFD.yml"; - - // Setup simulator with RISC-V architecture - await setupSimulator(testAssembly, RISCV_ARCH_PATH); - - // Execute the program - const result = executeN(1000); - assertEquals(result.error, false, "Execution should not error"); - - // Assert all expected state using the wrapper function - assertSimulatorState({ - registers: { - x6: 0xffffffcan, // t1 should contain 0xffffffca (-54 in 2's complement) - x7: 0x5an, // t2 should contain 0x5a (90 in decimal) - x10: 0xffffff70n, // a0 should contain 0xffffff70 (-144 in 2's complement) - x11: 0x5an, // a1 should contain 0x5a (90 in decimal) - x12: 0x2dn, // a2 should contain 0x2d (45 in decimal) - }, - display: "-144", // Display should show '-144' - keyboard: "", // Keyboard buffer should be empty - }); - - cleanupSimulator(); - }, +Deno.test( + "Architecture-agnostic testing - RISC-V Function Calls and Stack Operations", + assertExecution("RISCV/RV32IMFD.yml", testAssembly, { + registers: { + x6: 0xffffffcan, // t1 should contain 0xffffffca (-54 in 2's complement) + x7: 0x5an, // t2 should contain 0x5a (90 in decimal) + x10: 0xffffff70n, // a0 should contain 0xffffff70 (-144 in 2's complement) + x11: 0x5an, // a1 should contain 0x5a (90 in decimal) + x12: 0x2dn, // a2 should contain 0x2d (45 in decimal) + }, + display: "-144", // Display should show '-144' + keyboard: "", // Keyboard buffer should be empty + }), ); diff --git a/tests/unit/arch/riscv/example_012.test.mts b/tests/unit/arch/riscv/example_012.test.mts index 05ba77ebc..d706f4565 100644 --- a/tests/unit/arch/riscv/example_012.test.mts +++ b/tests/unit/arch/riscv/example_012.test.mts @@ -1,17 +1,6 @@ -import { assertEquals } from "https://deno.land/std/assert/mod.ts"; -import { - setupSimulator, - executeN, - cleanupSimulator, - assertSimulatorState, -} from "../simulator-test-utils.mts"; - -Deno.test( - "Architecture-agnostic testing - RISC-V Recursive Factorial Function", - - async () => { - const testAssembly = ` +import { assertExecution } from "../simulator-test-utils.mts"; +const testAssembly = ` # # ARCOS.INF.UC3M.ES # BY-NC-SA (https://creativecommons.org/licenses/by-nc-sa/4.0/deed.es) @@ -20,7 +9,7 @@ Deno.test( .text - main: + main: addi sp, sp, -4 sw ra, 0(sp) @@ -51,7 +40,7 @@ factorial: # return 1 li x5, 2 bge a0, t0, b_else - li a0, 1 + li a0, 1 beq x0, x0, b_efs # else: # return a0 * factorial(a0 - 1) @@ -68,29 +57,17 @@ factorial: # return t0 jr ra +`; - `; - - const RISCV_ARCH_PATH = "../../../architecture/RISCV/RV32IMFD.yml"; - - // Setup simulator with RISC-V architecture - await setupSimulator(testAssembly, RISCV_ARCH_PATH); - - // Execute the program - const result = executeN(1000); - assertEquals(result.error, false, "Execution should not error"); - - // Assert all expected state using the wrapper function - assertSimulatorState({ - registers: { - x5: 0x2n, // t0 should contain 0x2 (comparison value) - x6: 0x5n, // t1 should contain 0x5 (last factorial parameter) - x10: 0x78n, // a0 should contain 0x78 (120 - factorial of 5) - }, - display: "120", // Display should show '120' (5! = 120) - keyboard: "", // Keyboard buffer should be empty - }); - - cleanupSimulator(); - }, +Deno.test( + "Architecture-agnostic testing - RISC-V Recursive Factorial Function", + assertExecution("RISCV/RV32IMFD.yml", testAssembly, { + registers: { + x5: 0x2n, // t0 should contain 0x2 (comparison value) + x6: 0x5n, // t1 should contain 0x5 (last factorial parameter) + x10: 0x78n, // a0 should contain 0x78 (120 - factorial of 5) + }, + display: "120", // Display should show '120' (5! = 120) + keyboard: "", // Keyboard buffer should be empty + }), ); diff --git a/tests/unit/arch/riscv/example_013.test.mts b/tests/unit/arch/riscv/example_013.test.mts index 800807de9..97f35b69e 100644 --- a/tests/unit/arch/riscv/example_013.test.mts +++ b/tests/unit/arch/riscv/example_013.test.mts @@ -7,11 +7,7 @@ import { } from "../simulator-test-utils.mts"; import * as creator from "@/core/core.mjs"; -Deno.test( - "Architecture-agnostic testing - RISC-V Nested Function Calls with Stack", - // eslint-disable-next-line max-lines-per-function - async () => { - const testAssembly = ` +const testAssembly = ` # # Creator (https://creatorsim.github.io/creator/) # @@ -30,13 +26,13 @@ main: li a0, 23 li a1, -77 li a2, 45 - + # Call the first level function (starts the nested calls) jal ra, level1 - + # Store result mv s0, a0 - + # Print result li a7, 1 ecall @@ -59,16 +55,16 @@ level1: sw s0, 8(sp) sw a0, 4(sp) # Save argument a0 sw a1, 0(sp) # Save argument a1 - + # Save arguments in saved registers mv s0, a0 - + # Call level2 jal ra, level2 - + # Add original a0 to result add a0, a0, s0 - + # Restore registers and return lw a1, 0(sp) lw s0, 8(sp) @@ -83,14 +79,14 @@ level2: sw ra, 8(sp) sw a1, 4(sp) sw a2, 0(sp) - + # Call level3 jal ra, level3 - + # Add original a2 to result lw t0, 0(sp) add a0, a0, t0 - + # Restore and return lw a1, 4(sp) lw ra, 8(sp) @@ -103,14 +99,14 @@ level3: addi sp, sp, -8 sw ra, 4(sp) sw a1, 0(sp) - + # First call the original sum function jal ra, sum - + # Then call sub with result from sum lw a1, 0(sp) jal ra, sub - + # Restore and return lw ra, 4(sp) addi sp, sp, 8 @@ -122,14 +118,16 @@ sum: add t2, a2, a2 add a0, t1, zero add a1, t2, zero - jr ra + jr ra sub: sub a0, a0, a1 jr ra +`; - `; - +Deno.test( + "Architecture-agnostic testing - RISC-V Nested Function Calls with Stack", + async () => { const RISCV_ARCH_PATH = "../../../architecture/RISCV/RV32IMFD.yml"; // Setup simulator with RISC-V architecture diff --git a/tests/unit/arch/riscv/floating_point_demo.test.mts b/tests/unit/arch/riscv/floating_point_demo.test.mts index 19306a1b3..a26e88474 100644 --- a/tests/unit/arch/riscv/floating_point_demo.test.mts +++ b/tests/unit/arch/riscv/floating_point_demo.test.mts @@ -12,27 +12,27 @@ const FLOATING_POINT_DEMO_ASSEMBLY = ` pi: .float 3.14159265 e: .float 2.71828183 radius: .float 5.0 - + .text main: # Load floating point constants la t0, pi flw f0, 0(t0) # f0 = pi - + la t0, e flw f1, 0(t0) # f1 = e - + la t0, radius flw f2, 0(t0) # f2 = radius (5.0) - + # Mathematical operations fadd.s f3, f0, f1 # f3 = pi + e fmul.s f4, f0, f1 # f4 = pi * e - + # Circle area calculation: area = pi * radius^2 fmul.s f5, f2, f2 # f5 = radius^2 fmul.s f6, f0, f5 # f6 = pi * radius^2 - + # exit program li a7, 10 ecall diff --git a/tests/unit/arch/simulator-test-utils.mts b/tests/unit/arch/simulator-test-utils.mts index d05ed3891..d80726f54 100644 --- a/tests/unit/arch/simulator-test-utils.mts +++ b/tests/unit/arch/simulator-test-utils.mts @@ -384,3 +384,28 @@ export function assertSimulatorState( ); } } + +/** + * Verifies the execution of an assembly code + * @param arch - Architecture file to use + * @param code - Assembly code to execute + * @param expected - Object containing expected values for registers, memory, display, and keyboard + */ +export function assertExecution( + arch: string, + code: string, + expected: ExpectedState, +): () => Promise { + return async () => { + const ARCH_PATH = "../../../architecture/" + arch; + await setupSimulator(code, ARCH_PATH); + const result = executeN(1000); + assertEquals( + result.error, + false, + `Execution should not error. ${result.output}`, + ); + assertSimulatorState(expected) + cleanupSimulator(); + } +} From 9d4b204c6beedf5bf43b0b266296ae5e019e3234 Mon Sep 17 00:00:00 2001 From: ALVAROPING1 Date: Sat, 7 Mar 2026 14:23:47 +0100 Subject: [PATCH 02/85] tests(arch): add execution entry point test --- .../unit/arch/riscv/entry_point_demo.test.mts | 41 +++++++++++++++++++ 1 file changed, 41 insertions(+) create mode 100644 tests/unit/arch/riscv/entry_point_demo.test.mts diff --git a/tests/unit/arch/riscv/entry_point_demo.test.mts b/tests/unit/arch/riscv/entry_point_demo.test.mts new file mode 100644 index 000000000..b437645a1 --- /dev/null +++ b/tests/unit/arch/riscv/entry_point_demo.test.mts @@ -0,0 +1,41 @@ +import { assertExecution } from "../simulator-test-utils.mts"; + +const testAssembly = ` +# +# Creator (https://creatorsim.github.io/creator/) +# +.text + foo: + # Not executed + addi t0, x0, 1 + addi t1, x0, 2 + addi t2, x0, 3 + addi t3, x0, 4 + addi t4, x0, 5 + main: + # Start of the program + addi t0, t0, 5 + addi t1, t1, 5 + addi t2, t2, 5 + addi t3, t3, 5 + addi t4, t4, 5 + + # exit program + li a7, 10 + ecall +`; + +Deno.test( + "Architecture-agnostic testing - RISC-V Execution entry point", + assertExecution("RISCV/RV32IMFD.yml", testAssembly, { + registers: { + t0: 5n, + t1: 5n, + t2: 5n, + t3: 5n, + t4: 5n, + }, + display: "", + keyboard: "", + }), +); From 9ddf6cb7541b5974c62ad692f1c5059b5cd4ac10 Mon Sep 17 00:00:00 2001 From: ALVAROPING1 Date: Sun, 8 Mar 2026 14:51:16 +0100 Subject: [PATCH 03/85] fix: fix remaining usages of single label elements --- src/cli/commands/instructions.mts | 8 ++--- src/cli/commands/memory.mts | 6 ++-- src/cli/types.mts | 2 +- src/core/assembler/assembler.d.ts | 2 +- .../creatorAssembler/creatorAssemblerBase.mjs | 9 ++---- src/core/assembler/rasm/deno/rasm.mjs | 2 +- src/core/assembler/rasm/web/rasm.mjs | 2 +- .../assembler/sjasmplus/deno/sjasmplus.mjs | 2 +- src/core/capi/memory.mts | 4 +-- src/core/memory/Memory.mts | 29 ++++++++++--------- src/rpc/server.mts | 26 ++++++++--------- src/web/components/assembly/SaveLibrary.vue | 18 +++++++----- src/web/components/simulator/HexViewer.vue | 4 +-- .../components/simulator/TableExecution.vue | 2 +- 14 files changed, 58 insertions(+), 58 deletions(-) diff --git a/src/cli/commands/instructions.mts b/src/cli/commands/instructions.mts index 7ba9e72ad..1df840f8e 100644 --- a/src/cli/commands/instructions.mts +++ b/src/cli/commands/instructions.mts @@ -50,7 +50,7 @@ function displayInstruction( hideLibrary = false, ): void { const address = instr.Address.padEnd(8); - const label = (instr.Label || "").padEnd(11); + const label = instr.Label.join(",").padEnd(11); let loaded = (instr.loaded || "").padEnd(23); const loadedIsBinary = /^[01]+$/.test(loaded); const rightColumn = instr.user || ""; @@ -117,7 +117,7 @@ export function findInstructionByAddressOrLabel( address = userInput.toLowerCase(); } else { const labelMatch = instructions.find( - instr => instr.Label === userInput, + instr => instr.Label.includes(userInput), ); if (labelMatch) { @@ -159,7 +159,7 @@ export function toggleBreakpoint(index: number): void { console.log( `Breakpoint ${status} at ${instr!.Address}${ - instr!.Label ? ` (${instr!.Label})` : "" + instr!.Label.length > 0 ? ` (${instr!.Label.join(",")})` : "" }: ${instr!.loaded}`, ); } @@ -179,7 +179,7 @@ function listBreakpoints(): void { for (const bp of breakpoints) { console.log( - ` ${bp.Address}${bp.Label ? ` (${bp.Label})` : ""}: ${bp.loaded}`, + ` ${bp.Address}${bp.Label.length > 0 ? ` (${bp.Label.join(",")})` : ""}: ${bp.loaded}`, ); } } diff --git a/src/cli/commands/memory.mts b/src/cli/commands/memory.mts index 48d4d1a88..25f218727 100644 --- a/src/cli/commands/memory.mts +++ b/src/cli/commands/memory.mts @@ -68,7 +68,7 @@ function displayMemory(address: number, count: number): void { const formattedAddr = `0x${currentAddr.toString(16).padStart(8, "0")}`; const hintsInRange: Array<{ - hint: { tag: string; type: string; sizeInBits?: number }; + hint: { tag: string[]; type: string; sizeInBits?: number }; offset: number; }> = []; for (let j = 0; j < wordSize; j++) { @@ -95,8 +95,8 @@ function displayMemory(address: number, count: number): void { const colors = getHintColors(); for (let k = 0; k < hintsInRange.length; k++) { - const { hint, offset } = hintsInRange[k]; - const tag = hint.tag || ""; + const { hint, offset } = hintsInRange[k]!; + const tag = hint.tag.join(","); const type = hint.type || ""; const shortHint = type && tag ? `${tag}:${type}` : type || tag; const sizeInfo = hint.sizeInBits diff --git a/src/cli/types.mts b/src/cli/types.mts index cbe69b2f8..37b0a1b15 100644 --- a/src/cli/types.mts +++ b/src/cli/types.mts @@ -61,7 +61,7 @@ export interface ReturnType { */ export interface Instruction { Address: string; - Label: string | null; + Label: string[]; loaded: string; user: string; Break: boolean | null; diff --git a/src/core/assembler/assembler.d.ts b/src/core/assembler/assembler.d.ts index eebd4e3d6..94c0ccb85 100644 --- a/src/core/assembler/assembler.d.ts +++ b/src/core/assembler/assembler.d.ts @@ -1,7 +1,7 @@ type Instruction = { Address: string; Break: boolean | null; - Label: string; + Label: string[]; binary: string; hide: boolean; loaded: string; diff --git a/src/core/assembler/creatorAssembler/creatorAssemblerBase.mjs b/src/core/assembler/creatorAssembler/creatorAssemblerBase.mjs index 479a06e3a..1a185f813 100644 --- a/src/core/assembler/creatorAssembler/creatorAssemblerBase.mjs +++ b/src/core/assembler/creatorAssembler/creatorAssemblerBase.mjs @@ -548,12 +548,9 @@ export function assembleCreatorLibrary(code, wasmModules) { // Mark global labels on library instructions for (const instruction of libraryInstructions) { - if (instruction.Label !== "") { - if (label_table[instruction.Label].global === true) { - instruction.globl = true; - } else { - instruction.Label = ""; - } + instruction.Label = instruction.Label.filter(label => label_table[label].global); + if (instruction.Label.length > 0) { + instruction.globl = true; } } diff --git a/src/core/assembler/rasm/deno/rasm.mjs b/src/core/assembler/rasm/deno/rasm.mjs index 8f6699093..e41e7a926 100644 --- a/src/core/assembler/rasm/deno/rasm.mjs +++ b/src/core/assembler/rasm/deno/rasm.mjs @@ -126,7 +126,7 @@ export function rasmAssemble(code) { // Add hints to memory based on the parsed labels for (const [name, addr] of Object.entries(parsedSymbols)) { - main_memory.addHint(addr, name); + main_memory.addHint(addr, [name]); } // Set the tag instructions for the parsed symbols diff --git a/src/core/assembler/rasm/web/rasm.mjs b/src/core/assembler/rasm/web/rasm.mjs index f1190bb74..04fd01ba8 100644 --- a/src/core/assembler/rasm/web/rasm.mjs +++ b/src/core/assembler/rasm/web/rasm.mjs @@ -205,7 +205,7 @@ export async function rasmAssemble(code) { // Add hints to memory based on the parsed labels for (const [name, addr] of Object.entries(parsedSymbols)) { - main_memory.addHint(addr, name); + main_memory.addHint(addr, [name]); } // Set the tag instructions for the parsed symbols diff --git a/src/core/assembler/sjasmplus/deno/sjasmplus.mjs b/src/core/assembler/sjasmplus/deno/sjasmplus.mjs index 430bdd2c4..66ad4d0da 100644 --- a/src/core/assembler/sjasmplus/deno/sjasmplus.mjs +++ b/src/core/assembler/sjasmplus/deno/sjasmplus.mjs @@ -84,7 +84,7 @@ export function sjasmplusAssemble(code) { // Now add hints to memory based on the parsed symbols (its a dictionary) for (const [name, addr] of Object.entries(parsedSymbols)) { - main_memory.addHint(addr, name); + main_memory.addHint(addr, [name]); } // Clean up temp files diff --git a/src/core/capi/memory.mts b/src/core/capi/memory.mts index ef5ef4b38..5bb05d884 100644 --- a/src/core/capi/memory.mts +++ b/src/core/capi/memory.mts @@ -226,7 +226,7 @@ export const MEM = { if (hint) { try { const sizeInBits = bytes * BYTESIZE; - memory.addHint(BigInt(address), "", hint, sizeInBits); + memory.addHint(BigInt(address), [], hint, sizeInBits); } catch (e) { raise( "Failed to add hint for address '0x" + @@ -341,7 +341,7 @@ export const MEM = { : devices.get(deviceID)!.memory; try { - memory.addHint(address, "", hint, sizeInBits); + memory.addHint(address, [], hint, sizeInBits); return true; } catch (e) { raise( diff --git a/src/core/memory/Memory.mts b/src/core/memory/Memory.mts index d690075cc..7e92bde06 100644 --- a/src/core/memory/Memory.mts +++ b/src/core/memory/Memory.mts @@ -663,7 +663,7 @@ export class Memory { * const memory = new Memory({ sizeInBytes: 1000000 }); * memory.write(100n, 123); * memory.write(50000n, 456); - * memory.addHint(100n, "int32", 32); + * memory.addHint(100n, [], "int32", 32); * * const snapshot = memory.dump(); // Only contains 2 entries, not 1M, plus hints * memory.restore(snapshot); @@ -720,7 +720,7 @@ export class Memory { * @example Restoring memory state * ```typescript * const memory = new Memory({ sizeInBytes: 100000, bitsPerByte: 8 }); - * memory.addHint(0x100n, "int32", 32); + * memory.addHint(0x100n, [], "int32", 32); * const snapshot = memory.dump(); * // ... modify memory ... * memory.restore(snapshot); // Back to original state with hints @@ -1332,9 +1332,10 @@ export class Memory { * @example Adding hints * ```typescript * const memory = new Memory({ sizeInBytes: 1024 }); - * memory.addHint(0x100n, "", "double", 64); // No tag, just type - * memory.addHint(0x200n, "myVar", "int32", 32); - * memory.addHint(0x300n, "myString", "string"); // No size specified + * memory.addHint(0x100n, [], "double", 64); // No tag, just type + * memory.addHint(0x200n, ["myVar"], "int32", 32); + * memory.addHint(0x300n, ["myString"], "string"); // No size specified + * memory.addHint(0x400n, ["foo", "bar"], "int32", 32); // Multiple tags * ``` */ addHint( @@ -1370,7 +1371,7 @@ export class Memory { * @example Removing hints * ```typescript * const memory = new Memory({ sizeInBytes: 1024 }); - * memory.addHint(0x100n, "double", 64); + * memory.addHint(0x100n, [], "double", 64); * const removed = memory.removeHint(0x100n); // true * const notFound = memory.removeHint(0x200n); // false * ``` @@ -1388,7 +1389,7 @@ export class Memory { * @example Getting hints * ```typescript * const memory = new Memory({ sizeInBytes: 1024 }); - * memory.addHint(0x100n, "double", 64); + * memory.addHint(0x100n, [], "double", 64); * * const hint = memory.getHint(0x100n); * if (hint) { @@ -1411,8 +1412,8 @@ export class Memory { * @example Getting all hints * ```typescript * const memory = new Memory({ sizeInBytes: 1024 }); - * memory.addHint(0x200n, "int32", 32); - * memory.addHint(0x100n, "double", 64); + * memory.addHint(0x200n, [], "int32", 32); + * memory.addHint(0x100n, [], "double", 64); * * const hints = memory.getAllHints(); * for (const hint of hints) { @@ -1439,8 +1440,8 @@ export class Memory { * @example Clearing hints * ```typescript * const memory = new Memory({ sizeInBytes: 1024 }); - * memory.addHint(0x100n, "double", 64); - * memory.addHint(0x200n, "int32", 32); + * memory.addHint(0x100n, [], "double", 64); + * memory.addHint(0x200n, [], "int32", 32); * * console.log(memory.getAllHints().length); // 2 * memory.clearHints(); @@ -1478,9 +1479,9 @@ export class Memory { * @example Getting hints in range * ```typescript * const memory = new Memory({ sizeInBytes: 1024 }); - * memory.addHint(0x100n, "double", 64); - * memory.addHint(0x200n, "int32", 32); - * memory.addHint(0x300n, "string"); + * memory.addHint(0x100n, [], "double", 64); + * memory.addHint(0x200n, [], "int32", 32); + * memory.addHint(0x300n, [], "string"); * * const hintsInRange = memory.getHintsInRange(0x150n, 0x250n); * console.log(hintsInRange.length); // 1 (only the int32 at 0x200) diff --git a/src/rpc/server.mts b/src/rpc/server.mts index ae73d9ea5..848a619c2 100644 --- a/src/rpc/server.mts +++ b/src/rpc/server.mts @@ -84,7 +84,7 @@ interface EmulatorState { }; instructions: Array<{ address: string; - label?: string; + label: string[]; asm: string; machineCode: string; }>; @@ -597,13 +597,13 @@ class CreatorRpcServer { baseAddress: bigint, wordSize: number, ): Array<{ - tag: string; + tag: string[]; type: string; offset: number; sizeInBits?: number; }> { const hints: Array<{ - tag: string; + tag: string[]; type: string; offset: number; sizeInBits?: number; @@ -730,7 +730,7 @@ class CreatorRpcServer { // Get instruction list with better debugging info const instructionList = instructions.map((instr, index) => ({ address: instr.Address, - label: instr.Label || "", + label: instr.Label, asm: instr.loaded || instr.user || "", machineCode: instr.binary || instr.loaded || "", instructionIndex: index, @@ -767,7 +767,7 @@ class CreatorRpcServer { currentInstruction?: { index: number; address: string; - label?: string; + label: string[]; asm: string; machineCode: string; isBreakpoint?: boolean; @@ -775,7 +775,7 @@ class CreatorRpcServer { nextInstruction?: { index: number; address: string; - label?: string; + label: string[]; asm: string; machineCode: string; }; @@ -824,7 +824,7 @@ class CreatorRpcServer { currentInstruction = { index: i, address: instr.Address, - label: instr.Label || undefined, + label: instr.Label, asm: instr.loaded || instr.user || "", machineCode: instr.binary || instr.loaded || "", isBreakpoint: instr.Break === true, @@ -836,7 +836,7 @@ class CreatorRpcServer { nextInstruction = { index: i + 1, address: nextInstr.Address, - label: nextInstr.Label || undefined, + label: nextInstr.Label, asm: nextInstr.loaded || nextInstr.user || "", machineCode: nextInstr.binary || nextInstr.loaded || "", @@ -877,7 +877,7 @@ class CreatorRpcServer { }): Promise<{ index: number; address: string; - label?: string; + label: string[]; asm: string; machineCode: string; visible: boolean; @@ -918,7 +918,7 @@ class CreatorRpcServer { return { index, address: instruction.Address, - label: instruction.Label || undefined, + label: instruction.Label, asm: instruction.loaded || instruction.user || "", machineCode: instruction.binary || instruction.loaded || "", visible: instruction.visible !== false, @@ -980,7 +980,7 @@ class CreatorRpcServer { instruction: { index, address: instruction.Address, - label: instruction.Label || undefined, + label: instruction.Label, asm: instruction.loaded || instruction.user || "", machineCode: instruction.binary || instruction.loaded || "", isBreakpoint: instruction.Break === true, @@ -1001,7 +1001,7 @@ class CreatorRpcServer { Array<{ index: number; address: string; - label?: string; + label?: string[]; asm: string; machineCode: string; visible: boolean; @@ -1024,7 +1024,7 @@ class CreatorRpcServer { return instructions.map((instr, index) => ({ index, address: instr.Address, - label: instr.Label || undefined, + label: instr.Label, asm: instr.loaded || instr.user || "", user: instr.user || "", loaded: instr.loaded || "", diff --git a/src/web/components/assembly/SaveLibrary.vue b/src/web/components/assembly/SaveLibrary.vue index a564efd44..2441418c5 100644 --- a/src/web/components/assembly/SaveLibrary.vue +++ b/src/web/components/assembly/SaveLibrary.vue @@ -91,10 +91,11 @@ export default defineComponent({ } // Check for main symbol (not allowed in libraries) + const main = architecture.config.main_function; for (const instruction of libraryInstructions) { - if (instruction.Label === "main") { + if (instruction.Label.includes(main)) { show_notification( - 'You cannot use the "main" label in a library', + `You cannot use the "${main}" label in a library`, "danger", ); return false; @@ -114,16 +115,17 @@ export default defineComponent({ // Add symbol if instruction has a global label if ( - instruction.Label && - instruction.Label !== "" && + instruction.Label.length > 0 && instruction.globl === true ) { const addr = parseInt(instruction.Address, 16); - symbols.push({ - name: instruction.Label, - addr, - }); + for (const label of instruction.Label) { + symbols.push({ + name: label, + addr, + }); + } } } diff --git a/src/web/components/simulator/HexViewer.vue b/src/web/components/simulator/HexViewer.vue index 47f18c2d0..ec280ce99 100644 --- a/src/web/components/simulator/HexViewer.vue +++ b/src/web/components/simulator/HexViewer.vue @@ -536,7 +536,7 @@ export default defineComponent({ // Add hint for this instruction hints.push({ address: addr.toString(), - tag: instruction.loaded || instruction.user, + tag: [instruction.loaded || instruction.user], type: "instruction", sizeInBits: instructionSizeInBits, }); @@ -603,7 +603,7 @@ export default defineComponent({ for (let i = 0; i < sizeInBytes; i++) { this.hintMap.set(address + i, { - tag: typeof hint.tag === "string" ? hint.tag : hint.tag.join(", "), + tag: hint.tag.join(", "), type: hint.type, sizeInBits: hint.sizeInBits, colorIndex: hintColorIndex, diff --git a/src/web/components/simulator/TableExecution.vue b/src/web/components/simulator/TableExecution.vue index 771ea9394..9ccd8863a 100644 --- a/src/web/components/simulator/TableExecution.vue +++ b/src/web/components/simulator/TableExecution.vue @@ -211,7 +211,7 @@ export default {   {{ row.item.Address }} Date: Sun, 8 Mar 2026 14:52:31 +0100 Subject: [PATCH 04/85] refactor(memory): refactor duplicate get written addresses code --- src/core/memory/Memory.mts | 41 +++++++++++++++++++------------------- 1 file changed, 20 insertions(+), 21 deletions(-) diff --git a/src/core/memory/Memory.mts b/src/core/memory/Memory.mts index 7e92bde06..3e8511d4a 100644 --- a/src/core/memory/Memory.mts +++ b/src/core/memory/Memory.mts @@ -627,13 +627,29 @@ export class Memory { } /** - * Returns the addresses that have been written + * Returns an array of all addresses that have been written to. + * + * @returns Array of written addresses (number), sorted in ascending order. + * + * @example + * ```typescript + * const memory = new Memory({ sizeInBytes: 100 }); + * memory.write(5n, 123); + * memory.write(10n, 255); + * const written = memory.getWrittenAddresses(); // [5, 10] + * ``` + */ + getWrittenAddresses(): number[] { + // Sort addresses to ensure consistent output + return Array.from(this.writtenAddresses).sort((a, b) => a - b); + } + + /** + * Returns the addresses that have been written to, along with their value */ getWritten(): Array<{ addr: number; value: number }> { return ( - Array.from(this.writtenAddresses) - // Sort addresses to ensure consistent output - .sort((a, b) => a - b) + this.getWrittenAddresses() .map((addr, _i, _arr) => ({ addr, value: this.read(BigInt(addr)), @@ -1452,23 +1468,6 @@ export class Memory { this.hints.clear(); } - /** - * Returns an array of all addresses that have been written to. - * - * @returns Array of written addresses (number), sorted in ascending order. - * - * @example - * ```typescript - * const memory = new Memory({ sizeInBytes: 100 }); - * memory.write(5n, 123); - * memory.write(10n, 255); - * const written = memory.getWrittenAddresses(); // [5, 10] - * ``` - */ - getWrittenAddresses(): number[] { - return Array.from(this.writtenAddresses).sort((a, b) => a - b); - } - /** * Gets hints within a specified address range. * From 9becfb71c622ce74cd181e08819d8f5ce4c159fe Mon Sep 17 00:00:00 2001 From: ALVAROPING1 Date: Sun, 8 Mar 2026 14:53:19 +0100 Subject: [PATCH 05/85] chore: add non-null assertions where TS can't see array index is in bounds --- src/cli/commands/instructions.mts | 2 +- src/cli/commands/memory.mts | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/cli/commands/instructions.mts b/src/cli/commands/instructions.mts index 1df840f8e..62eac4b77 100644 --- a/src/cli/commands/instructions.mts +++ b/src/cli/commands/instructions.mts @@ -100,7 +100,7 @@ export function handleInstructionsCommand(limit?: number): void { : instructions.length; for (let i = 0; i < count; i++) { - displayInstruction(instructions[i], currentPC); + displayInstruction(instructions[i]!, currentPC); } } diff --git a/src/cli/commands/memory.mts b/src/cli/commands/memory.mts index 25f218727..9f92fb711 100644 --- a/src/cli/commands/memory.mts +++ b/src/cli/commands/memory.mts @@ -36,7 +36,7 @@ function applyHintHighlighting( const colors = getHintColors(); for (let k = hintsInRange.length - 1; k >= 0; k--) { - const { hint, offset } = hintsInRange[k]; + const { hint, offset } = hintsInRange[k]!; if (!hint.sizeInBits) continue; const sizeInBytes = Math.ceil(hint.sizeInBits / 8); From a93649c1ad2cb934e5b1be07011f4db488cb07eb Mon Sep 17 00:00:00 2001 From: EUtrilla2002 <100451242@alumnos.uc3m.es> Date: Fri, 13 Mar 2026 10:42:18 +0100 Subject: [PATCH 06/85] Added function in interrupts --- src/core/capi/arduino_functions.mts | 4 ++-- src/core/events.mts | 2 ++ src/web/components/simulator/ArduinoTerminal.vue | 7 +++++++ 3 files changed, 11 insertions(+), 2 deletions(-) diff --git a/src/core/capi/arduino_functions.mts b/src/core/capi/arduino_functions.mts index f2663dc30..ca0e904b6 100644 --- a/src/core/capi/arduino_functions.mts +++ b/src/core/capi/arduino_functions.mts @@ -796,10 +796,10 @@ export function cr_digitalPinToInterrupt() { }); } export function cr_interrupts() { - //TODO + coreEvents.emit("arduino-interrupts-enabled", true); } export function cr_nointerrupts() { - // TODO + coreEvents.emit("arduino-interrupts-enabled", false); } export function cr_isDigit() { var ret1 = crex_findReg("a0"); diff --git a/src/core/events.mts b/src/core/events.mts index 3b44da169..6b8d4ba78 100644 --- a/src/core/events.mts +++ b/src/core/events.mts @@ -137,6 +137,8 @@ export type CoreEvents = { "arduino-find-vector-slot": ArduinoFindSlotEvent; /** Emitted when the simulator requests to get the pin assigned to an interrupt vector slot */ "arduino-get-pin-from-slot": ArduinoGetPinFromSlotEvent; + /** Emitted when interrupts are enabled/disabled */ + "arduino-interrupts-enabled": boolean; }; /** * Emitted when the simulator sends text to the Arduino Terminal diff --git a/src/web/components/simulator/ArduinoTerminal.vue b/src/web/components/simulator/ArduinoTerminal.vue index 1fb4d9179..cba81efe3 100644 --- a/src/web/components/simulator/ArduinoTerminal.vue +++ b/src/web/components/simulator/ArduinoTerminal.vue @@ -154,6 +154,7 @@ import { } from "../../../core/register/registerOperations.mjs"; import { crex_findReg } from "../../../core/register/registerLookup.mjs"; + export default { setup() { return { @@ -180,6 +181,7 @@ export default { isResizing: false, chipStyles: {}, interrupt: {}, + isInterruptsEnabled: true, }; }, @@ -239,6 +241,7 @@ export default { }); coreEvents.on("arduino-pin-interrupt", pinName => { + if (!this.isInterruptsEnabled) return; this.interrupt[pinName.pin] = true; esp32vect.value[pinName.position] = [ BigInt(pinName.pin.replace(/\D/g, "")), @@ -247,8 +250,12 @@ export default { ]; }); coreEvents.on("arduino-pin-detach-interrupt", pinName => { + if (!this.isInterruptsEnabled) return; delete this.interrupt[pinName.pin]; }); + coreEvents.on("arduino-interrupts-enabled", enabled => { + this.isInterruptsEnabled = enabled; + }); }, beforeUnmount() { From 87e0ea30bc99c46f182243eb4aded5284d56fd8c Mon Sep 17 00:00:00 2001 From: EUtrilla2002 <100451242@alumnos.uc3m.es> Date: Mon, 16 Mar 2026 10:23:02 +0100 Subject: [PATCH 07/85] Flush original function(does not erase terminal) --- src/core/capi/arduino_functions.mts | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/core/capi/arduino_functions.mts b/src/core/capi/arduino_functions.mts index ca0e904b6..f62388391 100644 --- a/src/core/capi/arduino_functions.mts +++ b/src/core/capi/arduino_functions.mts @@ -1301,11 +1301,9 @@ export function cr_serial_flush() { }); if (serial_begin != 0 && initArduino != 0) { status.keyboard = ""; - status.display = ""; const root = (document as any).app; if (root) { root.keyboard = ""; - root.display = ""; root.enter = null; } } From d6f521058adf2ec152fe7010792fc004765281b2 Mon Sep 17 00:00:00 2001 From: EUtrilla2002 <100451242@alumnos.uc3m.es> Date: Mon, 16 Mar 2026 10:59:47 +0100 Subject: [PATCH 08/85] Erased flush example (does not work as it should) --- examples/RISCV-32-arduino/list.json | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) diff --git a/examples/RISCV-32-arduino/list.json b/examples/RISCV-32-arduino/list.json index e93c09329..242052ac5 100644 --- a/examples/RISCV-32-arduino/list.json +++ b/examples/RISCV-32-arduino/list.json @@ -74,30 +74,24 @@ { "name": "Example 11", "id": "e11", - "url": "examples/RISCV-32-arduino/example11.s", - "description": "Serial Flush example" + "url": "examples/RISCV-32-arduino/example12.s", + "description": "Serial readBytes example" }, { "name": "Example 12", "id": "e12", - "url": "examples/RISCV-32-arduino/example12.s", - "description": "Serial parseInt example" + "url": "examples/RISCV-32-arduino/example14.s", + "description": "Serial readBytes example" }, { "name": "Example 13", "id": "e13", - "url": "examples/RISCV-32-arduino/example13.s", - "description": "Serial readBytes example" - }, - { - "name": "Example 14", - "id": "e14", "url": "examples/RISCV-32-arduino/example14.s", "description": "Serial readBytesUntil example" }, { - "name": "Example 15", - "id": "e15", + "name": "Example 14", + "id": "e14", "url": "examples/RISCV-32-arduino/example15.s", "description": "High level interrupts example" } From 32630f730ab7ce1722818f7aff19a65a4decba56 Mon Sep 17 00:00:00 2001 From: EUtrilla2002 <100451242@alumnos.uc3m.es> Date: Mon, 16 Mar 2026 11:04:47 +0100 Subject: [PATCH 09/85] fixed readBytes examples --- examples/RISCV-32-arduino/example13.s | 2 +- examples/RISCV-32-arduino/example14.s | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/examples/RISCV-32-arduino/example13.s b/examples/RISCV-32-arduino/example13.s index 763be1eae..bb3910e8c 100644 --- a/examples/RISCV-32-arduino/example13.s +++ b/examples/RISCV-32-arduino/example13.s @@ -4,7 +4,7 @@ space: .zero 100 .text setup: - li a0, 11520 + li a0, 115200 addi sp, sp, -4 sw ra, 0(sp) jal ra, serial_begin diff --git a/examples/RISCV-32-arduino/example14.s b/examples/RISCV-32-arduino/example14.s index af9de2c9e..1de9d30b2 100644 --- a/examples/RISCV-32-arduino/example14.s +++ b/examples/RISCV-32-arduino/example14.s @@ -6,7 +6,7 @@ .text setup: - li a0, 11520 + li a0, 115200 addi sp, sp, -4 sw ra, 0(sp) jal ra, serial_begin From e35bae074006719ac865410ff0eb3e0684677b9d Mon Sep 17 00:00:00 2001 From: EUtrilla2002 <100451242@alumnos.uc3m.es> Date: Mon, 16 Mar 2026 13:32:53 +0100 Subject: [PATCH 10/85] Fixed examples --- examples/RISCV-32-arduino/example10.s | 28 +++---- examples/RISCV-32-arduino/example11.s | 73 +++++++++++++----- examples/RISCV-32-arduino/example12.s | 79 ++++++++----------- examples/RISCV-32-arduino/example13.s | 31 +++++--- examples/RISCV-32-arduino/example14.s | 107 +++++++++++++++++++------- examples/RISCV-32-arduino/example15.s | 96 ----------------------- examples/RISCV-32-arduino/list.json | 10 +-- src/core/executor/IO.mjs | 10 ++- 8 files changed, 207 insertions(+), 227 deletions(-) delete mode 100644 examples/RISCV-32-arduino/example15.s diff --git a/examples/RISCV-32-arduino/example10.s b/examples/RISCV-32-arduino/example10.s index 0719e901d..e51c50043 100644 --- a/examples/RISCV-32-arduino/example10.s +++ b/examples/RISCV-32-arduino/example10.s @@ -18,16 +18,16 @@ not_found: lw ra, 0(sp) addi sp, sp, 4 - #li a0, 10000 - #addi sp, sp, -4 - #sw ra, 0(sp) - #jal ra, delay - #lw ra, 0(sp) - #addi sp, sp, 4 + li a0, 10000 + addi sp, sp, -4 + sw ra, 0(sp) + jal ra, delay + lw ra, 0(sp) + addi sp, sp, 4 jal ra, loop -founded: +found_text: la a0, found addi sp, sp, -4 sw ra, 0(sp) @@ -35,12 +35,12 @@ founded: lw ra, 0(sp) addi sp, sp, 4 - #li a0, 10000 - #addi sp, sp, -4 - #sw ra, 0(sp) - #jal ra, delay - #lw ra, 0(sp) - #addi sp, sp, 4 + li a0, 10000 + addi sp, sp, -4 + sw ra, 0(sp) + jal ra, delay + lw ra, 0(sp) + addi sp, sp, 4 jal ra, loop @@ -75,7 +75,7 @@ loop: addi sp, sp, 4 beqz a0, not_found - jal ra, founded + jal ra, found_text diff --git a/examples/RISCV-32-arduino/example11.s b/examples/RISCV-32-arduino/example11.s index 47ee83428..0e16ee683 100644 --- a/examples/RISCV-32-arduino/example11.s +++ b/examples/RISCV-32-arduino/example11.s @@ -1,24 +1,55 @@ -# Creatino Example: Starting Monitor Print + +#Creatino example: parseInt .data - msg: .string "Hello! Serial here" + msg: .string "Enter a integer number:\n" + sol: .string "You entered %d" + lookahead: .string "SKIP_NONE" - msg2: .string "Come soon!!" .text - main: - # ESP-IDF needs to initiate Arduino component first - jal ra, initArduino - # Baud rate depends on the board you are using. Maybe the same values don't fit everywhere - li a0, 115200 - jal ra, serial_begin - la a0, msg - jal ra, serial_printf - - #Now, we will wait all the data is transmitted - jal ra, serial_flush - - #Print again!! - la a0, msg2 - jal ra, serial_printf - - - jr ra \ No newline at end of file + +number: + mv a1, a0 + la a0, sol + addi sp, sp, -4 + sw ra, 0(sp) + jal ra, serial_printf + lw ra, 0(sp) + addi sp, sp, 4 + jal ra, loop + +setup: + li a0, 115200 + addi sp, sp, -4 + sw ra, 0(sp) + jal ra, serial_begin + lw ra, 0(sp) + addi sp, sp, 4 + + jr ra + +loop: + la a0, msg + addi sp, sp, -4 + sw ra, 0(sp) + jal ra, serial_printf + lw ra, 0(sp) + addi sp, sp, 4 + + la a0, lookahead + addi sp, sp, -4 + sw ra, 0(sp) + jal ra, serial_parseInt + lw ra, 0(sp) + addi sp, sp, 4 + bnez a0, number + jal ra, loop + + +main: + jal ra, initArduino + addi sp, sp, -4 + sw ra, 0(sp) + jal ra, setup + lw ra, 0(sp) + addi sp, sp, 4 + j loop \ No newline at end of file diff --git a/examples/RISCV-32-arduino/example12.s b/examples/RISCV-32-arduino/example12.s index cc7e0a446..bb3910e8c 100644 --- a/examples/RISCV-32-arduino/example12.s +++ b/examples/RISCV-32-arduino/example12.s @@ -1,55 +1,40 @@ - -#Creatino example: parse +#Template for Arduino proyects .data - msg: .string "Enter a integer number:\n" - sol: .string "You entered %d" - lookahead: .string "SKIP_NONE" +space: .zero 100 .text - -number: - mv a1, a0 - la a0, sol - addi sp, sp, -4 - sw ra, 0(sp) - jal ra, serial_printf - lw ra, 0(sp) - addi sp, sp, 4 - jal ra, loop - setup: - li a0, 115200 - addi sp, sp, -4 - sw ra, 0(sp) - jal ra, serial_begin - lw ra, 0(sp) - addi sp, sp, 4 - + li a0, 115200 + addi sp, sp, -4 + sw ra, 0(sp) + jal ra, serial_begin + lw ra, 0(sp) + addi sp, sp, 4 jr ra - -loop: - la a0, msg - addi sp, sp, -4 - sw ra, 0(sp) - jal ra, serial_printf - lw ra, 0(sp) - addi sp, sp, 4 - - la a0, lookahead - addi sp, sp, -4 - sw ra, 0(sp) - jal ra, serial_parseInt - lw ra, 0(sp) - addi sp, sp, 4 - bnez a0, number - jal ra, loop - - +loop: + + addi sp, sp, -4 + sw ra, 0(sp) + la a0, space + li a1, 5 + jal ra, serial_readBytes + lw ra, 0(sp) + addi sp, sp, 4 + + + addi sp, sp, -4 + sw ra, 0(sp) + la a0, space + jal ra, serial_printf + lw ra, 0(sp) + addi sp, sp, 4 + + j loop main: - jal ra, initArduino - addi sp, sp, -4 - sw ra, 0(sp) + addi sp, sp, -16 + sw ra, 12(sp) + jal ra, initArduino jal ra, setup - lw ra, 0(sp) - addi sp, sp, 4 + lw ra, 12(sp) + addi sp, sp, 16 j loop \ No newline at end of file diff --git a/examples/RISCV-32-arduino/example13.s b/examples/RISCV-32-arduino/example13.s index bb3910e8c..1de9d30b2 100644 --- a/examples/RISCV-32-arduino/example13.s +++ b/examples/RISCV-32-arduino/example13.s @@ -1,6 +1,8 @@ -#Template for Arduino proyects +# Creatino example:readBytes .data -space: .zero 100 + space: .zero 100 #Buffer to place the string + print: .string "%s\n" + char: .byte 65 #A .text setup: @@ -13,22 +15,27 @@ setup: jr ra loop: + # read int + la a0, char + lb a0, 0(a0) + la a1, space + la a2, 5 # number of letters it will have + addi sp, sp, -4 - sw ra, 0(sp) - la a0, space - li a1, 5 - jal ra, serial_readBytes - lw ra, 0(sp) + sw ra, 0(sp) + jal ra, serial_readBytesUntil + lw ra, 0(sp) addi sp, sp, 4 - - addi sp, sp, -4 - sw ra, 0(sp) + # print: la a0, space + addi sp, sp, -4 + sw ra, 0(sp) jal ra, serial_printf - lw ra, 0(sp) - addi sp, sp, 4 + lw ra, 0(sp) + addi sp, sp, 4 + # return j loop main: addi sp, sp, -16 diff --git a/examples/RISCV-32-arduino/example14.s b/examples/RISCV-32-arduino/example14.s index 1de9d30b2..96972db52 100644 --- a/examples/RISCV-32-arduino/example14.s +++ b/examples/RISCV-32-arduino/example14.s @@ -1,47 +1,96 @@ -# Creatino example:readBytes +# Creatino example: GPIO Interrupts .data - space: .zero 100 #Buffer to place the string - print: .string "%s\n" - char: .byte 65 #A - + ledPin: .byte 4 + interruptpin: .byte 6 + state: .byte 0 #LOW + change: .byte 0x04 .text -setup: - li a0, 115200 +blink: + la t1, ledPin + lb a0, 0(t1) + li a1, 1 addi sp, sp, -4 - sw ra, 0(sp) - jal ra, serial_begin - lw ra, 0(sp) + sw ra,0(sp) + jal ra, digitalWrite# digitalWrite(ledPin, state) + lw ra,0(sp) addi sp, sp, 4 jr ra + + loop: + la t1, ledPin + lb a0, 0(t1) + li a1,0 + addi sp, sp, -4 + sw ra,0(sp) + jal ra, digitalWrite# digitalWrite(ledPin, state) + lw ra,0(sp) + addi sp, sp, 4 + + li a0, 100 + addi sp, sp, -4 + sw ra,0(sp) + jal ra, delay # delay(1000) + lw ra,0(sp) + addi sp, sp, 4 + j loop - # read int - la a0, char - lb a0, 0(a0) - la a1, space - la a2, 5 # number of letters it will have +setup: + #Start pins + la t1, ledPin + lb a0, 0(t1) + li a1, 0x03 #OUTPUT + addi sp, sp, -4 + sw ra,0(sp) + jal ra, pinMode #pinMode(ledPin, OUTPUT); + lw ra,0(sp) + addi sp, sp, 4 + la t1, interruptpin + lb a0, 0(t1) + li a1, 0x05 #INPUT_PULLUP + addi sp, sp, -4 + sw ra,0(sp) + jal ra, pinMode# pinMode(ledPin, INPUT_PULLUP); + lw ra,0(sp) + addi sp, sp, 4 + + la t1, interruptpin + lb a0, 0(t1) + addi sp, sp, -4 + sw ra,0(sp) + jal ra, digitalPinToInterrupt #digitalPinToInterrupt(interruptpin); + lw ra,0(sp) + addi sp, sp, 4 + + la a1, blink + la t1, change + lb a2, 0(t1) + + addi sp, sp, -4 + sw ra,0(sp) + jal ra, attachInterrupt #attachInterrupt(digitalPinToInterrupt(interruptPin), blink, CHANGE); + lw ra,0(sp) + addi sp, sp, 4 + jr ra + +main: + # Llamar a cr_initArduino() addi sp, sp, -4 sw ra, 0(sp) - jal ra, serial_readBytesUntil + jal ra, initArduino lw ra, 0(sp) addi sp, sp, 4 - # print: - la a0, space + # Llamar a setup() addi sp, sp, -4 sw ra, 0(sp) - jal ra, serial_printf + jal ra, setup lw ra, 0(sp) - addi sp, sp, 4 + addi sp, sp, 4 - # return + # Bucle infinito j loop -main: - addi sp, sp, -16 - sw ra, 12(sp) - jal ra, initArduino - jal ra, setup - lw ra, 12(sp) - addi sp, sp, 16 - j loop \ No newline at end of file + + + \ No newline at end of file diff --git a/examples/RISCV-32-arduino/example15.s b/examples/RISCV-32-arduino/example15.s deleted file mode 100644 index 96972db52..000000000 --- a/examples/RISCV-32-arduino/example15.s +++ /dev/null @@ -1,96 +0,0 @@ -# Creatino example: GPIO Interrupts -.data - ledPin: .byte 4 - interruptpin: .byte 6 - state: .byte 0 #LOW - change: .byte 0x04 -.text -blink: - la t1, ledPin - lb a0, 0(t1) - li a1, 1 - addi sp, sp, -4 - sw ra,0(sp) - jal ra, digitalWrite# digitalWrite(ledPin, state) - lw ra,0(sp) - addi sp, sp, 4 - jr ra - - -loop: - la t1, ledPin - lb a0, 0(t1) - li a1,0 - addi sp, sp, -4 - sw ra,0(sp) - jal ra, digitalWrite# digitalWrite(ledPin, state) - lw ra,0(sp) - addi sp, sp, 4 - - li a0, 100 - addi sp, sp, -4 - sw ra,0(sp) - jal ra, delay # delay(1000) - lw ra,0(sp) - addi sp, sp, 4 - j loop - -setup: - #Start pins - la t1, ledPin - lb a0, 0(t1) - li a1, 0x03 #OUTPUT - addi sp, sp, -4 - sw ra,0(sp) - jal ra, pinMode #pinMode(ledPin, OUTPUT); - lw ra,0(sp) - addi sp, sp, 4 - la t1, interruptpin - lb a0, 0(t1) - li a1, 0x05 #INPUT_PULLUP - addi sp, sp, -4 - sw ra,0(sp) - jal ra, pinMode# pinMode(ledPin, INPUT_PULLUP); - lw ra,0(sp) - addi sp, sp, 4 - - la t1, interruptpin - lb a0, 0(t1) - addi sp, sp, -4 - sw ra,0(sp) - jal ra, digitalPinToInterrupt #digitalPinToInterrupt(interruptpin); - lw ra,0(sp) - addi sp, sp, 4 - - la a1, blink - - la t1, change - lb a2, 0(t1) - - addi sp, sp, -4 - sw ra,0(sp) - jal ra, attachInterrupt #attachInterrupt(digitalPinToInterrupt(interruptPin), blink, CHANGE); - lw ra,0(sp) - addi sp, sp, 4 - jr ra - -main: - # Llamar a cr_initArduino() - addi sp, sp, -4 - sw ra, 0(sp) - jal ra, initArduino - lw ra, 0(sp) - addi sp, sp, 4 - - # Llamar a setup() - addi sp, sp, -4 - sw ra, 0(sp) - jal ra, setup - lw ra, 0(sp) - addi sp, sp, 4 - - # Bucle infinito - j loop - - - \ No newline at end of file diff --git a/examples/RISCV-32-arduino/list.json b/examples/RISCV-32-arduino/list.json index 242052ac5..640a1f39b 100644 --- a/examples/RISCV-32-arduino/list.json +++ b/examples/RISCV-32-arduino/list.json @@ -74,25 +74,25 @@ { "name": "Example 11", "id": "e11", - "url": "examples/RISCV-32-arduino/example12.s", - "description": "Serial readBytes example" + "url": "examples/RISCV-32-arduino/example11.s", + "description": "Serial parseInt example" }, { "name": "Example 12", "id": "e12", - "url": "examples/RISCV-32-arduino/example14.s", + "url": "examples/RISCV-32-arduino/example12.s", "description": "Serial readBytes example" }, { "name": "Example 13", "id": "e13", - "url": "examples/RISCV-32-arduino/example14.s", + "url": "examples/RISCV-32-arduino/example13.s", "description": "Serial readBytesUntil example" }, { "name": "Example 14", "id": "e14", - "url": "examples/RISCV-32-arduino/example15.s", + "url": "examples/RISCV-32-arduino/example14.s", "description": "High level interrupts example" } diff --git a/src/core/executor/IO.mjs b/src/core/executor/IO.mjs index 1f545e932..2572f6fe3 100644 --- a/src/core/executor/IO.mjs +++ b/src/core/executor/IO.mjs @@ -623,6 +623,9 @@ export function keyboard_read_find(fn_post_read, fn_post_params,fn_post_length,f ); } length = readRegister(ret2.indexComp, ret2.indexElem); + if (length <= 0) { + length = Infinity; // No length limit + } } @@ -666,19 +669,20 @@ export function keyboard_read_find(fn_post_read, fn_post_params,fn_post_length,f if (typeof Deno !== "undefined") { let keystroke = rawPrompt(); - if (until && typeof until === "string") { + if (until && typeof until === "string" && until !== "" ) { const idx = keystroke.indexOf(until); if (idx !== -1) { keystroke = keystroke.substring(0, idx); } } - - if (keystroke.includes(target) && keystroke.length <= (length || keystroke.length) && !keystroke.includes(until)) { + if (keystroke.includes(target) && keystroke.length <= length) { writeRegister(1n, ret1.indexComp, ret1.indexElem); } else { writeRegister(0n, ret1.indexComp, ret1.indexElem); } + + status.run_program = 0; return packExecute( false, From 808c94d02704156662c4c7cf03c7db3b9cba5acd Mon Sep 17 00:00:00 2001 From: ALVAROPING1 Date: Mon, 16 Mar 2026 13:43:49 +0100 Subject: [PATCH 11/85] fix(mips): allow reading doubles from `FP\d+` registers --- src/core/capi/arch/mips.mjs | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/core/capi/arch/mips.mjs b/src/core/capi/arch/mips.mjs index e7a62b532..8a62c5692 100644 --- a/src/core/capi/arch/mips.mjs +++ b/src/core/capi/arch/mips.mjs @@ -39,13 +39,14 @@ export const ARCH = { /** * Reads a double precision floating point value from a register pair. - * @param {string} regName - The base register name (must be even, e.g., "f0") + * @param {string} regName - The base register name (must be even, e.g., "f0" or "FP0") * @returns {number} The JavaScript number representation of the double */ readDouble(regName) { this.validateEvenRegister(regName); - const regNumber = parseInt(regName.substring(1), 10); + const offset = regName.substring(0, 2) === "FP"? 2 : 1; + const regNumber = parseInt(regName.substring(offset), 10); const highReg = regName; const lowRegName = "f" + (regNumber + 1); From 64cdd42d887dcdaa5694f267cc19f7ccc17c0eef Mon Sep 17 00:00:00 2001 From: ALVAROPING1 Date: Mon, 16 Mar 2026 13:45:12 +0100 Subject: [PATCH 12/85] fix(stackTracker): properly reset stack frames This avoids creating a new stack frame each time the first instruction of main is executed --- src/core/executor/executor.mjs | 10 ---------- src/core/memory/StackTracker.mts | 1 + 2 files changed, 1 insertion(+), 10 deletions(-) diff --git a/src/core/executor/executor.mjs b/src/core/executor/executor.mjs index 987fbabeb..3d8963411 100644 --- a/src/core/executor/executor.mjs +++ b/src/core/executor/executor.mjs @@ -367,16 +367,6 @@ function executeInstructionCycle() { logger.debug("Execution Index:" + status.execution_index); logger.debug("PC Register: " + getPC()); - // Special check for stack visualization purposes - if ( - status.execution_index === - instructions.findIndex( - i => parseInt(i.Address, 16) === get_entrypoint(), - ) - ) { - stackTracker.newFrame(tag_instructions[getPC()]?.tag || ""); - } - // Check for conditions that would stop execution const inLoopCheckResult = performExecutionChecks(); if (inLoopCheckResult !== null) { diff --git a/src/core/memory/StackTracker.mts b/src/core/memory/StackTracker.mts index cc462fa56..54664d2da 100644 --- a/src/core/memory/StackTracker.mts +++ b/src/core/memory/StackTracker.mts @@ -71,6 +71,7 @@ export class StackTracker { public reset() { this.frames.length = 0; this.hints.clear(); + this.newFrame("main"); } /** From 88e74bd7278c02b55ad4b43e51174b5711986321 Mon Sep 17 00:00:00 2001 From: ALVAROPING1 Date: Mon, 16 Mar 2026 13:46:17 +0100 Subject: [PATCH 13/85] fix(capi.stack): fix `.endFrame()` popping multiple stack frames --- src/core/capi/stack.mts | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/core/capi/stack.mts b/src/core/capi/stack.mts index 4a98abf41..c8a8cc7d3 100644 --- a/src/core/capi/stack.mts +++ b/src/core/capi/stack.mts @@ -47,8 +47,7 @@ export const STACK = { } }, endFrame() { - // stack tracker: pop both frames - stackTracker.popFrame(); + // stack tracker: pop frame stackTracker.popFrame(); // sentinel From f98606835897c81d176df8bada3c55ae2fa67c64 Mon Sep 17 00:00:00 2001 From: ALVAROPING1 Date: Mon, 16 Mar 2026 13:47:49 +0100 Subject: [PATCH 14/85] refactor(core): remove redundant bigint conversion when reading PC --- src/core/core.mjs | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/core/core.mjs b/src/core/core.mjs index b22d072c3..2c94cd499 100644 --- a/src/core/core.mjs +++ b/src/core/core.mjs @@ -682,11 +682,10 @@ export function getRegisterInfo(regName) { } export function getPC() { - const pc_address = readRegister( + return readRegister( PC_REG_INDEX.indexComp, PC_REG_INDEX.indexElem, ); - return BigInt(pc_address); } export function getSP() { From 357d32d03a5e3ba3de6834d5d410f35866c89086 Mon Sep 17 00:00:00 2001 From: EUtrilla2002 <100451242@alumnos.uc3m.es> Date: Mon, 16 Mar 2026 13:49:36 +0100 Subject: [PATCH 15/85] Fixed find --- src/core/executor/IO.mjs | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/core/executor/IO.mjs b/src/core/executor/IO.mjs index 2572f6fe3..daa1832ad 100644 --- a/src/core/executor/IO.mjs +++ b/src/core/executor/IO.mjs @@ -710,7 +710,13 @@ export function keyboard_read_find(fn_post_read, fn_post_params,fn_post_length,f // Find logic // console.log("keystroke:", `"${keystroke}"`, keystroke.length); // console.log("until:", `"${until}"`, until.length); - if (keystroke.includes(target) && keystroke.length <= (length || keystroke.length) && !keystroke.includes(until)) { + if (until && typeof until === "string" && until !== "" ) { + const idx = keystroke.indexOf(until); + if (idx !== -1) { + keystroke = keystroke.substring(0, idx); + } + } + if (keystroke.includes(target) && keystroke.length <= length) { writeRegister(1n, ret1.indexComp, ret1.indexElem); } else { writeRegister(0n, ret1.indexComp, ret1.indexElem); From afb9f712022cfdf220226ec539ace8c52060f4a9 Mon Sep 17 00:00:00 2001 From: ALVAROPING1 Date: Mon, 16 Mar 2026 13:54:40 +0100 Subject: [PATCH 16/85] fix(architecture): allow `jr ra` on the `main` function to exit the program --- architecture/MIPS32.yml | 6 ++++-- architecture/RISCV/RV32IMFD.yml | 10 ++++++---- architecture/RISCV/RV64IMFD.yml | 6 ++++-- architecture/RISCV/SRV32.yml | 8 +++++--- architecture/RISCV/SRV64.yml | 8 +++++--- 5 files changed, 24 insertions(+), 14 deletions(-) diff --git a/architecture/MIPS32.yml b/architecture/MIPS32.yml index d61d0743b..28be3ea44 100644 --- a/architecture/MIPS32.yml +++ b/architecture/MIPS32.yml @@ -2279,8 +2279,10 @@ instructions: stopbit: 0 value: "001000" definition: |- - registers.PC = registers[rs]; - CAPI.STACK.endFrame(); + const pc = registers[rs] + registers.PC = pc; + if (BigInt.asIntN(32, pc) === -1n) CAPI.SYSCALL.exit(); + else CAPI.STACK.endFrame(); - name: lb template: Custom type: Memory access diff --git a/architecture/RISCV/RV32IMFD.yml b/architecture/RISCV/RV32IMFD.yml index a9434c2f8..16f1050b5 100644 --- a/architecture/RISCV/RV32IMFD.yml +++ b/architecture/RISCV/RV32IMFD.yml @@ -166,8 +166,8 @@ components: - x1 - ra nbits: 32 - value: 0xFFFFFF00 - default_value: 0xFFFFFF00 + value: 0xFFFFFFFF + default_value: 0xFFFFFFFF encoding: 1 properties: - read @@ -1601,8 +1601,10 @@ instructions: value: "000" definition: | registers[rd] = registers.pc + 4n; - registers.pc = (registers[rs1] + imm) & ~1n; - CAPI.STACK.endFrame(); + const pc = registers[rs1] + imm; + registers.pc = pc & ~1n; + if (BigInt.asIntN(32, pc) === -1n) CAPI.SYSCALL.exit(); + else CAPI.STACK.endFrame(); help: Jump to address and place return address in rd. - name: lb diff --git a/architecture/RISCV/RV64IMFD.yml b/architecture/RISCV/RV64IMFD.yml index 6492c5a1b..5604d4265 100644 --- a/architecture/RISCV/RV64IMFD.yml +++ b/architecture/RISCV/RV64IMFD.yml @@ -1619,8 +1619,10 @@ instructions: value: "000" definition: | registers[rd] = registers.pc + 4n; - registers.pc = (registers[rs1] + imm) & ~1n; - CAPI.STACK.endFrame(); + const pc = registers[rs1] + imm; + registers.pc = pc & ~1n; + if (BigInt.asIntN(64, pc) === -1n) CAPI.SYSCALL.exit(); + else CAPI.STACK.endFrame(); help: Jump to address and place return address in rd. - name: lb diff --git a/architecture/RISCV/SRV32.yml b/architecture/RISCV/SRV32.yml index acb3049ed..4857310d4 100644 --- a/architecture/RISCV/SRV32.yml +++ b/architecture/RISCV/SRV32.yml @@ -2160,9 +2160,11 @@ instructions: - field: funct3 value: "000" definition: | - registers[rd] = registers["PC"] + 4n; - registers["PC"] = (registers[rs1] + imm) & ~1n; - CAPI.CHECK_STACK.end(); CAPI.DRAW_STACK.end(registers["PC"]); + registers[rd] = registers.pc + 4n; + const pc = registers[rs1] + imm; + registers.pc = pc & ~1n; + if (BigInt.asIntN(32, pc) === -1n) CAPI.SYSCALL.exit(); + else CAPI.STACK.endFrame(); help: Jump to address and place return address in rd. - name: lb extension: I diff --git a/architecture/RISCV/SRV64.yml b/architecture/RISCV/SRV64.yml index ee506592c..e3d6e6cba 100644 --- a/architecture/RISCV/SRV64.yml +++ b/architecture/RISCV/SRV64.yml @@ -2171,9 +2171,11 @@ instructions: - field: funct3 value: "000" definition: | - registers[rd] = registers["PC"] + 4n; - registers["PC"] = (registers[rs1] + imm) & ~1n; - CAPI.CHECK_STACK.end(); CAPI.DRAW_STACK.end(registers["PC"]); + registers[rd] = registers.pc + 4n; + const pc = registers[rs1] + imm; + registers.pc = pc & ~1n; + if (BigInt.asIntN(64, pc) === -1n) CAPI.SYSCALL.exit(); + else CAPI.STACK.endFrame(); help: Jump to address and place return address in rd. - name: lb extension: I From 37746c3161337735f8acc62a52b4d001bec1d65c Mon Sep 17 00:00:00 2001 From: ALVAROPING1 Date: Mon, 16 Mar 2026 13:55:27 +0100 Subject: [PATCH 17/85] fix(MIPS): fix incorrect numerical int register names --- architecture/MIPS32.yml | 64 +++++++++---------- .../unit/arch/mips/mips_example_002.test.mts | 16 ++--- .../unit/arch/mips/mips_example_003.test.mts | 20 +++--- .../unit/arch/mips/mips_example_004.test.mts | 12 ++-- .../unit/arch/mips/mips_example_005.test.mts | 8 +-- .../unit/arch/mips/mips_example_006.test.mts | 14 ++-- .../unit/arch/mips/mips_example_007.test.mts | 18 +++--- .../unit/arch/mips/mips_example_008.test.mts | 14 ++-- .../unit/arch/mips/mips_example_011.test.mts | 18 +++--- .../unit/arch/mips/mips_example_012.test.mts | 10 +-- 10 files changed, 97 insertions(+), 97 deletions(-) diff --git a/architecture/MIPS32.yml b/architecture/MIPS32.yml index 28be3ea44..863a8625a 100644 --- a/architecture/MIPS32.yml +++ b/architecture/MIPS32.yml @@ -132,7 +132,7 @@ components: double_precision: false elements: - name: - - r0 + - "0" - zero nbits: 32 value: 0 @@ -141,7 +141,7 @@ components: properties: - read - name: - - r1 + - "1" - at nbits: 32 value: 0 @@ -151,7 +151,7 @@ components: - read - write - name: - - r2 + - "2" - v0 nbits: 32 value: 0 @@ -161,7 +161,7 @@ components: - read - write - name: - - r3 + - "3" - v1 nbits: 32 value: 0 @@ -171,7 +171,7 @@ components: - read - write - name: - - r4 + - "4" - a0 nbits: 32 value: 0 @@ -181,7 +181,7 @@ components: - read - write - name: - - r5 + - "5" - a1 nbits: 32 value: 0 @@ -191,7 +191,7 @@ components: - read - write - name: - - r6 + - "6" - a2 nbits: 32 value: 0 @@ -201,7 +201,7 @@ components: - read - write - name: - - r7 + - "7" - a3 nbits: 32 value: 0 @@ -211,7 +211,7 @@ components: - read - write - name: - - r8 + - "8" - t0 nbits: 32 value: 0 @@ -221,7 +221,7 @@ components: - read - write - name: - - r9 + - "9" - t1 nbits: 32 value: 0 @@ -231,7 +231,7 @@ components: - read - write - name: - - r10 + - "10" - t2 nbits: 32 value: 0 @@ -241,7 +241,7 @@ components: - read - write - name: - - r11 + - "11" - t3 nbits: 32 value: 0 @@ -251,7 +251,7 @@ components: - read - write - name: - - r12 + - "12" - t4 nbits: 32 value: 0 @@ -261,7 +261,7 @@ components: - read - write - name: - - r13 + - "13" - t5 nbits: 32 value: 0 @@ -271,7 +271,7 @@ components: - read - write - name: - - r14 + - "14" - t6 nbits: 32 value: 0 @@ -281,7 +281,7 @@ components: - read - write - name: - - r15 + - "15" - t7 nbits: 32 value: 0 @@ -291,7 +291,7 @@ components: - read - write - name: - - r16 + - "16" - s0 nbits: 32 value: 0 @@ -302,7 +302,7 @@ components: - write - saved - name: - - r17 + - "17" - s1 nbits: 32 value: 0 @@ -313,7 +313,7 @@ components: - write - saved - name: - - r18 + - "18" - s2 nbits: 32 value: 0 @@ -324,7 +324,7 @@ components: - write - saved - name: - - r19 + - "19" - s3 nbits: 32 value: 0 @@ -335,7 +335,7 @@ components: - write - saved - name: - - r20 + - "20" - s4 nbits: 32 value: 0 @@ -346,7 +346,7 @@ components: - write - saved - name: - - r21 + - "21" - s5 nbits: 32 value: 0 @@ -357,7 +357,7 @@ components: - write - saved - name: - - r22 + - "22" - s6 nbits: 32 value: 0 @@ -368,7 +368,7 @@ components: - write - saved - name: - - r23 + - "23" - s7 nbits: 32 value: 0 @@ -379,7 +379,7 @@ components: - write - saved - name: - - r24 + - "24" - t8 nbits: 32 value: 0 @@ -389,7 +389,7 @@ components: - read - write - name: - - r25 + - "25" - t9 nbits: 32 value: 0 @@ -399,7 +399,7 @@ components: - read - write - name: - - r26 + - "26" - k0 nbits: 32 value: 0 @@ -409,7 +409,7 @@ components: - read - write - name: - - r27 + - "27" - k1 nbits: 32 value: 0 @@ -419,7 +419,7 @@ components: - read - write - name: - - r28 + - "28" - gp nbits: 32 value: 0 @@ -430,7 +430,7 @@ components: - write - global_pointer - name: - - r29 + - "29" - sp nbits: 32 value: 268435452 @@ -441,7 +441,7 @@ components: - write - stack_pointer - name: - - r30 + - "30" - fp nbits: 32 value: 0 @@ -452,7 +452,7 @@ components: - write - frame_pointer - name: - - r31 + - "31" - ra nbits: 32 value: 4294967295 diff --git a/tests/unit/arch/mips/mips_example_002.test.mts b/tests/unit/arch/mips/mips_example_002.test.mts index ae1d29b32..59632a9c2 100644 --- a/tests/unit/arch/mips/mips_example_002.test.mts +++ b/tests/unit/arch/mips/mips_example_002.test.mts @@ -23,14 +23,14 @@ Deno.test( "MIPS Basic Arithmetic Operations", assertExecution("MIPS32.yml", testAssembly, { registers: { - r8: 0xan, // t0 = 10 - r9: 0xdn, // t1 = 13 - r10: 0x2dn, // t2 = 45 - r11: 0x21n, // t3 = 33 - r12: 0x17n, // t4 = 23 - r13: 0xcn, // t5 = 12 - r14: 0x441n, // t6 = 1089 - r15: 0x53n, // t7 = 83 + "8": 0xan, // t0 = 10 + "9": 0xdn, // t1 = 13 + "10": 0x2dn, // t2 = 45 + "11": 0x21n, // t3 = 33 + "12": 0x17n, // t4 = 23 + "13": 0xcn, // t5 = 12 + "14": 0x441n, // t6 = 1089 + "15": 0x53n, // t7 = 83 }, display: "", // Display buffer should be empty keyboard: "", // Keyboard buffer should be empty diff --git a/tests/unit/arch/mips/mips_example_003.test.mts b/tests/unit/arch/mips/mips_example_003.test.mts index 0ee22eba5..7a0fdc02f 100644 --- a/tests/unit/arch/mips/mips_example_003.test.mts +++ b/tests/unit/arch/mips/mips_example_003.test.mts @@ -42,16 +42,16 @@ Deno.test( "MIPS Data Types and Memory Operations", assertExecution("MIPS32.yml", testAssembly, { registers: { - r1: 0x20000en, // at - r8: 0x200000n, // t0 - r9: 0x200004n, // t1 - r10: 0x200006n, // t2 - r11: 0xen, // t3 - r12: 0xen, // t4 - r13: 0x78n, // t5 - r14: 0x78n, // t6 - r15: 0x16n, // t7 - r24: 0x16n, // t8 + "1": 0x20000en, // at + "8": 0x200000n, // t0 + "9": 0x200004n, // t1 + "10": 0x200006n, // t2 + "11": 0xen, // t3 + "12": 0xen, // t4 + "13": 0x78n, // t5 + "14": 0x78n, // t6 + "15": 0x16n, // t7 + "24": 0x16n, // t8 }, memory: { "0x20000f": 0x16n, diff --git a/tests/unit/arch/mips/mips_example_004.test.mts b/tests/unit/arch/mips/mips_example_004.test.mts index 2d29e4c21..aeac318a1 100644 --- a/tests/unit/arch/mips/mips_example_004.test.mts +++ b/tests/unit/arch/mips/mips_example_004.test.mts @@ -41,12 +41,12 @@ Deno.test( assertExecution("MIPS32.yml", testAssembly, { // TODO: finish the conditions below registers: { - r1: 0x200018n, // at - r2: 0xan, // v0 - r8: 0x200000n, // t0 - r9: 0x200008n, // t1 - r10: 0x200010n, // t2 - r11: 0x200028n, // t3 + "1": 0x200018n, // at + "2": 0xan, // v0 + "8": 0x200000n, // t0 + "9": 0x200008n, // t1 + "10": 0x200010n, // t2 + "11": 0x200028n, // t3 }, display: "", // Display buffer should be empty keyboard: "", // Keyboard buffer should be empty diff --git a/tests/unit/arch/mips/mips_example_005.test.mts b/tests/unit/arch/mips/mips_example_005.test.mts index 19c0fea79..a57a96587 100644 --- a/tests/unit/arch/mips/mips_example_005.test.mts +++ b/tests/unit/arch/mips/mips_example_005.test.mts @@ -25,10 +25,10 @@ Deno.test( "MIPS Loop and Print Sum", assertExecution("MIPS32.yml", testAssembly, { registers: { - r2: 0x1n, // v0 - r4: 0x2dn, // a0 = 45 - r8: 0xan, // t0 = 10 - r9: 0xan, // t1 = 10 + "2": 0x1n, // v0 + "4": 0x2dn, // a0 = 45 + "8": 0xan, // t0 = 10 + "9": 0xan, // t1 = 10 }, display: "45", // Should display '45' keyboard: "", // Keyboard buffer should be empty diff --git a/tests/unit/arch/mips/mips_example_006.test.mts b/tests/unit/arch/mips/mips_example_006.test.mts index e06aa3b57..3ae682947 100644 --- a/tests/unit/arch/mips/mips_example_006.test.mts +++ b/tests/unit/arch/mips/mips_example_006.test.mts @@ -26,13 +26,13 @@ Deno.test( "MIPS Branching Instructions", assertExecution("MIPS32.yml", testAssembly, { registers: { - r1: 0x1n, // at - r2: 0xan, // v0 - r8: 0x4n, // t0 - r9: 0x2n, // t1 - r11: 0x22n, // t3 - r24: 0x22bn, // t8 - r25: 0xbn, // t9 + "1": 0x1n, // at + "2": 0xan, // v0 + "8": 0x4n, // t0 + "9": 0x2n, // t1 + "11": 0x22n, // t3 + "24": 0x22bn, // t8 + "25": 0xbn, // t9 }, display: "", // Display buffer should be empty keyboard: "", // Keyboard buffer should be empty diff --git a/tests/unit/arch/mips/mips_example_007.test.mts b/tests/unit/arch/mips/mips_example_007.test.mts index e8e872c71..3c3af6981 100644 --- a/tests/unit/arch/mips/mips_example_007.test.mts +++ b/tests/unit/arch/mips/mips_example_007.test.mts @@ -43,15 +43,15 @@ Deno.test( assertExecution("MIPS32.yml", testAssembly, { registers: { PC: 0x44n, - r1: 0x200000n, // at - r2: 0xan, // v0 - r9: 0x5n, // t1 - r10: 0x5n, // t2 - r11: 0x1n, // t3 - r12: 0x4n, // t4 - r13: 0x200014n, // t5 - r14: 0x5n, // t6 - r15: 0xfn, // t7 + "1": 0x200000n, // at + "2": 0xan, // v0 + "9": 0x5n, // t1 + "10": 0x5n, // t2 + "11": 0x1n, // t3 + "12": 0x4n, // t4 + "13": 0x200014n, // t5 + "14": 0x5n, // t6 + "15": 0xfn, // t7 }, display: "", // Display buffer should be empty keyboard: "", // Keyboard buffer should be empty diff --git a/tests/unit/arch/mips/mips_example_008.test.mts b/tests/unit/arch/mips/mips_example_008.test.mts index e688cd312..8f06781a8 100644 --- a/tests/unit/arch/mips/mips_example_008.test.mts +++ b/tests/unit/arch/mips/mips_example_008.test.mts @@ -45,13 +45,13 @@ Deno.test( "MIPS Matrix Copy with Floats", assertExecution("MIPS32.yml", testAssembly, { registers: { - r1: 0x200040n, // at - r2: 0xan, // v0 - r8: 0x200040n, // t0 - r9: 0x200080n, // t1 - r10: 0x4n, // t2 - r11: 0x4n, // t3 - r12: 0x4n, // t4 + "1": 0x200040n, // at + "2": 0xan, // v0 + "8": 0x200040n, // t0 + "9": 0x200080n, // t1 + "10": 0x4n, // t2 + "11": 0x4n, // t3 + "12": 0x4n, // t4 }, memory: { "0x20007f": 0x24n, diff --git a/tests/unit/arch/mips/mips_example_011.test.mts b/tests/unit/arch/mips/mips_example_011.test.mts index 3e488fd2a..64beb4195 100644 --- a/tests/unit/arch/mips/mips_example_011.test.mts +++ b/tests/unit/arch/mips/mips_example_011.test.mts @@ -38,15 +38,15 @@ Deno.test( assertExecution("MIPS32.yml", testAssembly, { registers: { PC: 0x38n, - r1: 0xffffffb3n, // at - r2: 0xan, // v0 - r3: 0x5an, // v1 - r4: 0xffffff70n, // a0 - r5: 0x5an, // a1 - r6: 0x2dn, // a2 - r9: 0xffffffcan, // t1 - r10: 0x5an, // t2 - r31: 0x24n, // ra + "1": 0xffffffb3n, // at + "2": 0xan, // v0 + "3": 0x5an, // v1 + "4": 0xffffff70n, // a0 + "5": 0x5an, // a1 + "6": 0x2dn, // a2 + "9": 0xffffffcan, // t1 + "10": 0x5an, // t2 + "31": 0x24n, // ra }, display: "-144", // Should display '-144' keyboard: "", // Keyboard buffer should be empty diff --git a/tests/unit/arch/mips/mips_example_012.test.mts b/tests/unit/arch/mips/mips_example_012.test.mts index 702559876..973a01705 100644 --- a/tests/unit/arch/mips/mips_example_012.test.mts +++ b/tests/unit/arch/mips/mips_example_012.test.mts @@ -58,11 +58,11 @@ Deno.test( assertExecution("MIPS32.yml", testAssembly, { registers: { PC: 0x1cn, - r1: 0x1n, // at - r2: 0xan, // v0 - r4: 0x78n, // a0 - r9: 0x5n, // t1 - r31: 0x8n, // ra + "1": 0x1n, // at + "2": 0xan, // v0 + "4": 0x78n, // a0 + "9": 0x5n, // t1 + "31": 0x8n, // ra }, display: "120", // Should display '120' keyboard: "", // Keyboard buffer should be empty From 7a3965738c9a34998945e36bb0dd2c0a41e20636 Mon Sep 17 00:00:00 2001 From: ALVAROPING1 Date: Mon, 16 Mar 2026 13:56:11 +0100 Subject: [PATCH 18/85] fix(MIPS): add missing `FP\d+` float register aliases --- architecture/MIPS32.yml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/architecture/MIPS32.yml b/architecture/MIPS32.yml index 863a8625a..51dc9055b 100644 --- a/architecture/MIPS32.yml +++ b/architecture/MIPS32.yml @@ -467,6 +467,7 @@ components: elements: - name: - f0 + - FP0 nbits: 32 value: 0 default_value: 0 @@ -485,6 +486,7 @@ components: - write - name: - f2 + - FP2 nbits: 32 value: 0 default_value: 0 @@ -503,6 +505,7 @@ components: - write - name: - f4 + - FP4 nbits: 32 value: 0 default_value: 0 @@ -521,6 +524,7 @@ components: - write - name: - f6 + - FP6 nbits: 32 value: 0 default_value: 0 @@ -539,6 +543,7 @@ components: - write - name: - f8 + - FP8 nbits: 32 value: 0 default_value: 0 @@ -557,6 +562,7 @@ components: - write - name: - f10 + - FP10 nbits: 32 value: 0 default_value: 0 @@ -575,6 +581,7 @@ components: - write - name: - f12 + - FP12 nbits: 32 value: 0 default_value: 0 @@ -593,6 +600,7 @@ components: - write - name: - f14 + - FP14 nbits: 32 value: 0 default_value: 0 @@ -611,6 +619,7 @@ components: - write - name: - f16 + - FP16 nbits: 32 value: 0 default_value: 0 @@ -629,6 +638,7 @@ components: - write - name: - f18 + - FP18 nbits: 32 value: 0 default_value: 0 @@ -647,6 +657,7 @@ components: - write - name: - f20 + - FP20 nbits: 32 value: 0 default_value: 0 @@ -665,6 +676,7 @@ components: - write - name: - f22 + - FP22 nbits: 32 value: 0 default_value: 0 @@ -683,6 +695,7 @@ components: - write - name: - f24 + - FP24 nbits: 32 value: 0 default_value: 0 @@ -701,6 +714,7 @@ components: - write - name: - f26 + - FP26 nbits: 32 value: 0 default_value: 0 @@ -719,6 +733,7 @@ components: - write - name: - f28 + - FP28 nbits: 32 value: 0 default_value: 0 @@ -737,6 +752,7 @@ components: - write - name: - f30 + - FP30 nbits: 32 value: 0 default_value: 0 From b240da29aa543853a776f9161bd44f4d70ca9702 Mon Sep 17 00:00:00 2001 From: ALVAROPING1 Date: Mon, 16 Mar 2026 13:58:29 +0100 Subject: [PATCH 19/85] fix(IO): fix kbd_read_char returning incorrect value --- src/core/executor/IO.mjs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/core/executor/IO.mjs b/src/core/executor/IO.mjs index daa1832ad..953d38273 100644 --- a/src/core/executor/IO.mjs +++ b/src/core/executor/IO.mjs @@ -58,7 +58,7 @@ export function kbd_read_char(keystroke, params) { } writeRegister(BigInt(value), params.indexComp, params.indexElem); - return value; + return keystroke[0] || ""; } export function kbd_read_int(keystroke, params) { From de92c761f5d5da79107701990506790f01a1814f Mon Sep 17 00:00:00 2001 From: ALVAROPING1 Date: Mon, 16 Mar 2026 14:00:36 +0100 Subject: [PATCH 20/85] fix(IO): fix kbd_read_double erroring out on the CLI --- src/core/executor/IO.mjs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/core/executor/IO.mjs b/src/core/executor/IO.mjs index 953d38273..2ae7eb7b8 100644 --- a/src/core/executor/IO.mjs +++ b/src/core/executor/IO.mjs @@ -125,7 +125,7 @@ export function kbd_read_double(keystroke, params) { const value = parseFloat(keystroke, 10); // validate input - if (typeof document.app !== "undefined" && isNaN(value)) { + if (typeof document !== "undefined" && document.app && isNaN(value)) { show_notification( `Invalid input: '${keystroke}' is not a double`, "danger", From 9516080adde1a82089d35929dfe2ecce82b0c598 Mon Sep 17 00:00:00 2001 From: ALVAROPING1 Date: Mon, 16 Mar 2026 14:09:43 +0100 Subject: [PATCH 21/85] fix(RISCV): fix many incorrect instruction definitions --- architecture/RISCV/RV32IMFD.yml | 120 +++++++----------------- architecture/RISCV/RV64IMFD.yml | 101 +++++++------------- architecture/RISCV/SRV32.yml | 157 ++++++++++++-------------------- architecture/RISCV/SRV64.yml | 140 ++++++++++++---------------- 4 files changed, 179 insertions(+), 339 deletions(-) diff --git a/architecture/RISCV/RV32IMFD.yml b/architecture/RISCV/RV32IMFD.yml index 16f1050b5..34656289f 100644 --- a/architecture/RISCV/RV32IMFD.yml +++ b/architecture/RISCV/RV32IMFD.yml @@ -1733,7 +1733,7 @@ instructions: - field: funct7 value: "0100000" definition: | - if (shamt > 0) registers[rd] = CAPI.FP.int2uint(registers[rs1] >> shamt); + if (shamt > 0) registers[rd] = CAPI.FP.int2uint(CAPI.FP.uint2int(registers[rs1]) >> shamt); help: Performs arithmetic right shift on the value in register rs1 by the shift amount held in the lower 5 bits of the immediate. - name: srli @@ -2108,11 +2108,9 @@ instructions: - field: funct3 value: "101" definition: | - if (registers[rs2] != 0) { - registers[rd] = BigInt.asIntN( - 32, - (BigInt.asUintN(32, BigInt(registers[rs1])) / BigInt.asUintN(32, BigInt(registers[rs2]))) - ); + const div = registers[rs2] + if (div != 0) { + registers[rd] = CAPI.FP.int2uint(registers[rs1] / div); } else CAPI.VALIDATION.raise('Division by zero not allowed'); help: Perform an XLEN-bit by XLEN-bit unsigned integer division of rs1 by @@ -2142,12 +2140,8 @@ instructions: - field: funct3 value: "001" definition: | - registers[rd] = BigInt.asIntN( - 32, - BigInt.asIntN( - 64, - BigInt.asIntN(32, BigInt(registers[rs1])) * BigInt.asIntN(32, BigInt(registers[rs2])), - ) >> 32n, + registers[rd] = CAPI.FP.int2uint( + (CAPI.FP.uint2int(registers[rs1]) * CAPI.FP.uint2int(registers[rs2])) >> 32n, ); help: Performs an XLEN-bit by XLEN-bit multiplication of signed rs1 by signed rs2 and places the lower XLEN bits in the destination register. @@ -2162,12 +2156,8 @@ instructions: - field: funct3 value: "010" definition: | - registers[rd] = BigInt.asIntN( - 32, - BigInt.asIntN( - 64, - BigInt.asIntN(32, BigInt(registers[rs1])) * BigInt.asUintN(32, BigInt(registers[rs2])), - ) >> 32n, + registers[rd] = CAPI.FP.int2uint( + (CAPI.FP.uint2int(registers[rs1]) * registers[rs2]) >> 32n, ); help: Performs an XLEN-bit by XLEN-bit multiplication of signed rs1 by unsigned rs2 and places the upper XLEN bits in the destination register. @@ -2182,12 +2172,8 @@ instructions: - field: funct3 value: "011" definition: | - registers[rd] = BigInt.asIntN( - 32, - BigInt.asUintN( - 64, - BigInt.asUintN(32, BigInt(registers[rs1])) * BigInt.asUintN(32, BigInt(registers[rs2])), - ) >> 32n, + registers[rd] = CAPI.FP.int2uint( + (registers[rs1] * registers[rs2]) >> 32n, ); help: Performs an XLEN-bit by XLEN-bit multiplication of unsigned rs1 by unsigned rs2 and places the upper XLEN bits in the destination register. @@ -2321,9 +2307,9 @@ instructions: optional: true order: 3 postoperation: | - registers[rd] = CAPI.ARCH.toBigInt(registers[rd],'NaNBfloat32_64'); + registers[rd] = CAPI.ARCH.toBigInt(result,'NaNBfloat32_64'); definition: | - registers[rd] = CAPI.FP.uint2int(registers[rs1]) + const result = CAPI.FP.uint2int(registers[rs1]) help: Converts a 32-bit signed integer, in integer register rs1 into a floating-point number in floating-point register rd. - name: fcvt.s.wu @@ -2439,17 +2425,11 @@ instructions: - field: rd type: INT-Reg preoperation: | - let result, rs1Number, rs2Number, type_rs1, type_rs2; + let rs1Number, rs2Number, type_rs1, type_rs2; [rs1Number, type_rs1] = CAPI.ARCH.toJSNumberD(registers[rs1]); [rs2Number, type_rs2] = CAPI.ARCH.toJSNumberD(registers[rs2]); - postoperation: | - if (CAPI.FP.isNaN(result)) { - registers[rd] = CAPI.ARCH.toBigInt(result, "NaN32"); - } else { - registers[rd] = CAPI.ARCH.toBigInt(result, "NaNBfloat32_64"); - } definition: | - result = (rs1Number === rs2Number) ? 1 : 0; + registers[rd] = (rs1Number === rs2Number)? 1n : 0n; help: Performs a quiet equal comparison between floating-point registers rs1 and rs2 and record the Boolean result in integer register rd. Only signaling NaN inputs cause an Invalid Operation exception. The result is @@ -2467,17 +2447,11 @@ instructions: - field: rd type: INT-Reg preoperation: | - let result, rs1Number, rs2Number, type_rs1, type_rs2; + let rs1Number, rs2Number, type_rs1, type_rs2; [rs1Number, type_rs1] = CAPI.ARCH.toJSNumberD(registers[rs1]); [rs2Number, type_rs2] = CAPI.ARCH.toJSNumberD(registers[rs2]); - postoperation: | - if (CAPI.FP.isNaN(result)) { - registers[rd] = CAPI.ARCH.toBigInt(result, "NaN32"); - } else { - registers[rd] = CAPI.ARCH.toBigInt(result, "NaNBfloat32_64"); - } definition: | - result = (rs1Number <= rs2Number) ? 1 : 0; + registers[rd] = (rs1Number <= rs2Number)? 1n : 0n; help: Performs a quiet less or equal comparison between floating-point registers rs1 and rs2 and record the Boolean result in integer register rd. Only signaling NaN inputs cause an Invalid Operation exception. The @@ -2495,17 +2469,11 @@ instructions: - field: rd type: INT-Reg preoperation: | - let result, rs1Number, rs2Number, type_rs1, type_rs2; + let rs1Number, rs2Number, type_rs1, type_rs2; [rs1Number, type_rs1] = CAPI.ARCH.toJSNumberD(registers[rs1]); [rs2Number, type_rs2] = CAPI.ARCH.toJSNumberD(registers[rs2]); - postoperation: | - if (CAPI.FP.isNaN(result)) { - registers[rd] = CAPI.ARCH.toBigInt(result, "NaN32"); - } else { - registers[rd] = CAPI.ARCH.toBigInt(result, "NaNBfloat32_64"); - } definition: | - result = (rs1Number < rs2Number) ? 1 : 0; + registers[rd] = (rs1Number < rs2Number)? 1n : 0n; help: Performs a quiet less comparison between floating-point registers rs1 and rs2 and record the Boolean result in integer register rd. Only signaling NaN inputs cause an Invalid Operation exception. The result is @@ -2724,9 +2692,8 @@ instructions: optional: true order: 3 preoperation: | - let result, rs1Number, rs2Number, type_rs1, type_rs2; + let result, rs1Number, type_rs1; [rs1Number, type_rs1] = CAPI.ARCH.toJSNumberD(registers[rs1]); - [rs2Number, type_rs2] = CAPI.ARCH.toJSNumberD(registers[rs2]); postoperation: | if (CAPI.FP.isNaN(result)) { registers[rd] = CAPI.ARCH.toBigInt(result, "NaN32"); @@ -2738,7 +2705,7 @@ instructions: result = Math.sqrt(rs1Number); } else { CAPI.VALIDATION.raise( - 'Square root of a negative number is not allowed.' + "Square root of a negative number is not allowed." ); } help: Perform single-precision square root. @@ -2785,7 +2752,7 @@ instructions: let result, rs1Number, rs2Number, rs3Number, type_rs1, type_rs2, type_rs3; [rs1Number, type_rs1] = CAPI.ARCH.toJSNumberD(registers[rs1]); [rs2Number, type_rs2] = CAPI.ARCH.toJSNumberD(registers[rs2]); - [rs3Number, type_rs3] = CAPI.ARCH.toJSNumberD(rs3); + [rs3Number, type_rs3] = CAPI.ARCH.toJSNumberD(registers[rs3]); postoperation: | if (CAPI.FP.isNaN(result)) { registers[rd] = CAPI.ARCH.toBigInt(result, "NaN32"); @@ -2812,7 +2779,7 @@ instructions: let result, rs1Number, rs2Number, rs3Number, type_rs1, type_rs2, type_rs3; [rs1Number, type_rs1] = CAPI.ARCH.toJSNumberD(registers[rs1]); [rs2Number, type_rs2] = CAPI.ARCH.toJSNumberD(registers[rs2]); - [rs3Number, type_rs3] = CAPI.ARCH.toJSNumberD(rs3); + [rs3Number, type_rs3] = CAPI.ARCH.toJSNumberD(registers[rs3]); postoperation: | if (CAPI.FP.isNaN(result)) { registers[rd] = CAPI.ARCH.toBigInt(result, "NaN32"); @@ -2839,7 +2806,7 @@ instructions: let result, rs1Number, rs2Number, rs3Number, type_rs1, type_rs2, type_rs3; [rs1Number, type_rs1] = CAPI.ARCH.toJSNumberD(registers[rs1]); [rs2Number, type_rs2] = CAPI.ARCH.toJSNumberD(registers[rs2]); - [rs3Number, type_rs3] = CAPI.ARCH.toJSNumberD(rs3); + [rs3Number, type_rs3] = CAPI.ARCH.toJSNumberD(registers[rs3]); postoperation: | if (CAPI.FP.isNaN(result)) { registers[rd] = CAPI.ARCH.toBigInt(result, "NaN32"); @@ -2866,7 +2833,7 @@ instructions: let result, rs1Number, rs2Number, rs3Number, type_rs1, type_rs2, type_rs3; [rs1Number, type_rs1] = CAPI.ARCH.toJSNumberD(registers[rs1]); [rs2Number, type_rs2] = CAPI.ARCH.toJSNumberD(registers[rs2]); - [rs3Number, type_rs3] = CAPI.ARCH.toJSNumberD(rs3); + [rs3Number, type_rs3] = CAPI.ARCH.toJSNumberD(registers[rs3]); postoperation: | if (CAPI.FP.isNaN(result)) { registers[rd] = CAPI.ARCH.toBigInt(result, "NaN32"); @@ -3033,8 +3000,8 @@ instructions: - field: rs1 type: INT-Reg preoperation: | - let result, rs1Number, type_rs1; - [rs1Number, type_rs1] = CAPI.ARCH.toJSNumberD(registers[rs1]); + let result, rs1Number; + rs1Number = registers[rs1]; postoperation: | registers[rd] = CAPI.ARCH.toBigInt(result, 'float64'); definition: | @@ -3207,17 +3174,11 @@ instructions: - field: rd type: INT-Reg preoperation: | - let result, rs1Number, rs2Number, type_rs1, type_rs2; + let rs1Number, rs2Number, type_rs1, type_rs2; [rs1Number, type_rs1] = CAPI.ARCH.toJSNumberD(registers[rs1]); [rs2Number, type_rs2] = CAPI.ARCH.toJSNumberD(registers[rs2]); - postoperation: | - if (CAPI.FP.isNaN(result)) { - registers[rd] = CAPI.ARCH.toBigInt(result, "NaN64"); - } else { - registers[rd] = CAPI.ARCH.toBigInt(result, "float64"); - } definition: | - registers[rd] = (rs1Number == rs2Number) ? 1 : 0; + registers[rd] = (rs1Number === rs2Number)? 1n : 0n; help: Performs a quiet equal comparison between double-precision floating-point registers rs1 and rs2 and record the Boolean result in integer register rd. Only signaling NaN inputs cause an Invalid @@ -3238,14 +3199,8 @@ instructions: let rs1Number, rs2Number, type_rs1, type_rs2; [rs1Number, type_rs1] = CAPI.ARCH.toJSNumberD(registers[rs1]); [rs2Number, type_rs2] = CAPI.ARCH.toJSNumberD(registers[rs2]); - postoperation: | - if (CAPI.FP.isNaN(result)) { - registers[rd] = CAPI.ARCH.toBigInt(result, "NaN64"); - } else { - registers[rd] = CAPI.ARCH.toBigInt(result, "float64"); - } definition: | - registers[rd] = (rs1Number <= rs2Number) ? 1 : 0; + registers[rd] = (rs1Number <= rs2Number)? 1n : 0n; help: Performs a quiet less or equal comparison between double-precision floating-point registers rs1 and rs2 and record the Boolean result in integer register rd. Only signaling NaN inputs cause an Invalid @@ -3266,14 +3221,8 @@ instructions: let rs1Number, rs2Number, type_rs1, type_rs2; [rs1Number, type_rs1] = CAPI.ARCH.toJSNumberD(registers[rs1]); [rs2Number, type_rs2] = CAPI.ARCH.toJSNumberD(registers[rs2]); - postoperation: | - if (CAPI.FP.isNaN(result)) { - registers[rd] = CAPI.ARCH.toBigInt(result, "NaN64"); - } else { - registers[rd] = CAPI.ARCH.toBigInt(result, "float64"); - } definition: | - registers[rd] = (rs1Number < rs2Number) ? 1 : 0; + registers[rd] = (rs1Number < rs2Number) ? 1n : 0n; help: Performs a quiet less comparison between double-precision floating-point registers rs1 and rs2 and record the Boolean result in integer register rd. Only signaling NaN inputs cause an Invalid @@ -3394,7 +3343,7 @@ instructions: registers[rd] = CAPI.ARCH.toBigInt(result, "float64"); } definition: | - registers[rd] = (rs2Number > 0) ? -Math.abs(rs1Number) : +Math.abs(rs1Number); + result = (rs2Number > 0) ? -Math.abs(rs1Number) : +Math.abs(rs1Number); help: Produce a result that takes all bits except the sign bit from rs1. The result's sign bit is opposite of rs2's sign bit. @@ -3420,7 +3369,7 @@ instructions: definition: | let a = rs1Number < 0; let b = rs2Number < 0; - registers[rd] = a ^ b ? -Math.abs(rs1Number) : Math.abs(rs1Number); + result = a ^ b ? -Math.abs(rs1Number) : Math.abs(rs1Number); help: Produce a result that takes all bits except the sign bit from rs1. The result's sign bit is XOR of sign bit of rs1 and rs2. @@ -3441,9 +3390,8 @@ instructions: optional: true order: 3 preoperation: | - let result, rs1Number, rs2Number, type_rs1, type_rs2; + let result, rs1Number, type_rs1; [rs1Number, type_rs1] = CAPI.ARCH.toJSNumberD(registers[rs1]); - [rs2Number, type_rs2] = CAPI.ARCH.toJSNumberD(registers[rs2]); postoperation: | if (CAPI.FP.isNaN(result)) { registers[rd] = CAPI.ARCH.toBigInt(result, "NaN64"); @@ -3452,7 +3400,7 @@ instructions: } definition: | if (rs1Number >= 0) { - registers[rd] = Math.sqrt(rs1Number); + result = Math.sqrt(rs1Number); } else { CAPI.VALIDATION.raise( "Square root of a negative number is not allowed." diff --git a/architecture/RISCV/RV64IMFD.yml b/architecture/RISCV/RV64IMFD.yml index 5604d4265..a3de7308c 100644 --- a/architecture/RISCV/RV64IMFD.yml +++ b/architecture/RISCV/RV64IMFD.yml @@ -1830,7 +1830,7 @@ instructions: - field: funct7 value: "0000000" definition: | - if (shamt > 0) rd = (rs1 >> shamt); + if (shamt > 0) registers[rd] = CAPI.FP.int2uint(registers[rs1] >> shamt); help: Performs logical right shift on the value in register rs1 by the shift amount held in the lower 5 bits of the immediate. - name: srliw @@ -1846,7 +1846,7 @@ instructions: definition: | if (shamt > 0) { const temp = - ((BigInt(registers[rs1]) & 0xffffffffn) >> BigInt(shamt)) & 0xffffffffn; + ((registers[rs1] & 0xffffffffn) >> shamt) & 0xffffffffn; registers[rd] = temp & 0x80000000n ? temp | 0xffffffff00000000n : temp; registers[rd] = CAPI.FP.int2uint(registers[rd]); } @@ -2098,8 +2098,8 @@ instructions: - field: funct3 value: "000" definition: | - const temp = (BigInt(rs1) + BigInt(rs2)) & 0xFFFFFFFFn; - rd = temp & 0x80000000n ? temp | 0xFFFFFFFF00000000n : temp; + const temp = (registers[rs1] + registers[rs2]) & 0xFFFFFFFFn; + registers[rd] = temp & 0x80000000n ? temp | 0xFFFFFFFF00000000n : temp; help: Subtract the 32-bit of registers rs1 and 32-bit of register rs2 and stores the result in rd. Arithmetic overflow is ignored and the low 32-bits of the result is sign-extended to 64-bits and written to the @@ -2293,10 +2293,11 @@ instructions: - field: funct3 value: "101" definition: | - if (registers[rs2] != 0) { + const div = registers[rs2] + if (div != 0) { registers[rd] = BigInt.asIntN( 32, - (BigInt.asUintN(32, BigInt(registers[rs1])) / BigInt.asUintN(32, BigInt(registers[rs2]))) + (BigInt.asUintN(32, registers[rs1]) / BigInt.asUintN(32, div)) ); } else CAPI.VALIDATION.raise('Division by zero not allowed'); @@ -2327,7 +2328,7 @@ instructions: - field: funct3 value: "001" definition: | - registers[rd] = BigInt.asIntN( + registers[rd] = BigInt.asUintN( 32, BigInt.asIntN( 64, @@ -2503,9 +2504,9 @@ instructions: optional: true order: 3 postoperation: | - registers[rd] = CAPI.ARCH.toBigInt(registers[rd],'NaNBfloat32_64'); + registers[rd] = CAPI.ARCH.toBigInt(result,'NaNBfloat32_64'); definition: | - registers[rd] = CAPI.FP.uint2int(registers[rs1]) + result = CAPI.FP.uint2int(registers[rs1]) help: Converts a 32-bit signed integer, in integer register rs1 into a floating-point number in floating-point register rd. - name: fcvt.s.wu @@ -2621,17 +2622,11 @@ instructions: - field: rd type: INT-Reg preoperation: | - let result, rs1Number, rs2Number, type_rs1, type_rs2; + let rs1Number, rs2Number, type_rs1, type_rs2; [rs1Number, type_rs1] = CAPI.ARCH.toJSNumberD(registers[rs1]); [rs2Number, type_rs2] = CAPI.ARCH.toJSNumberD(registers[rs2]); - postoperation: | - if (CAPI.FP.isNaN(result)) { - registers[rd] = CAPI.ARCH.toBigInt(result, "NaN32"); - } else { - registers[rd] = CAPI.ARCH.toBigInt(result, "NaNBfloat32_64"); - } definition: | - result = (rs1Number === rs2Number) ? 1 : 0; + registers[rd] = (rs1Number === rs2Number)? 1n : 0n; help: Performs a quiet equal comparison between floating-point registers rs1 and rs2 and record the Boolean result in integer register rd. Only signaling NaN inputs cause an Invalid Operation exception. The result is @@ -2649,17 +2644,11 @@ instructions: - field: rd type: INT-Reg preoperation: | - let result, rs1Number, rs2Number, type_rs1, type_rs2; + let rs1Number, rs2Number, type_rs1, type_rs2; [rs1Number, type_rs1] = CAPI.ARCH.toJSNumberD(registers[rs1]); [rs2Number, type_rs2] = CAPI.ARCH.toJSNumberD(registers[rs2]); - postoperation: | - if (CAPI.FP.isNaN(result)) { - registers[rd] = CAPI.ARCH.toBigInt(result, "NaN32"); - } else { - registers[rd] = CAPI.ARCH.toBigInt(result, "NaNBfloat32_64"); - } definition: | - result = (rs1Number <= rs2Number) ? 1 : 0; + registers[rd] = (rs1Number <= rs2Number)? 1n : 0n; help: Performs a quiet equal comparison between floating-point registers rs1 and rs2 and record the Boolean result in integer register rd. Only signaling NaN inputs cause an Invalid Operation exception. The result is @@ -2677,17 +2666,11 @@ instructions: - field: rd type: INT-Reg preoperation: | - let result, rs1Number, rs2Number, type_rs1, type_rs2; + let rs1Number, rs2Number, type_rs1, type_rs2; [rs1Number, type_rs1] = CAPI.ARCH.toJSNumberD(registers[rs1]); [rs2Number, type_rs2] = CAPI.ARCH.toJSNumberD(registers[rs2]); - postoperation: | - if (CAPI.FP.isNaN(result)) { - registers[rd] = CAPI.ARCH.toBigInt(result, "NaN32"); - } else { - registers[rd] = CAPI.ARCH.toBigInt(result, "NaNBfloat32_64"); - } definition: | - result = (rs1Number < rs2Number) ? 1 : 0; + registers[rd] = (rs1Number < rs2Number)? 1n : 0n; help: Performs a quiet less or equal comparison between floating-point registers rs1 and rs2 and record the Boolean result in integer register rd. Only signaling NaN inputs cause an Invalid Operation exception. The @@ -2906,9 +2889,8 @@ instructions: optional: true order: 3 preoperation: | - let result, rs1Number, rs2Number, type_rs1, type_rs2; + let result, rs1Number, type_rs1; [rs1Number, type_rs1] = CAPI.ARCH.toJSNumberD(registers[rs1]); - [rs2Number, type_rs2] = CAPI.ARCH.toJSNumberD(registers[rs2]); postoperation: | if (CAPI.FP.isNaN(result)) { registers[rd] = CAPI.ARCH.toBigInt(result, "NaN32"); @@ -2920,7 +2902,7 @@ instructions: result = Math.sqrt(rs1Number); } else { CAPI.VALIDATION.raise( - 'Square root of a negative number is not allowed.' + "Square root of a negative number is not allowed." ); } help: Perform single-precision square root. @@ -2967,7 +2949,7 @@ instructions: let result, rs1Number, rs2Number, rs3Number, type_rs1, type_rs2, type_rs3; [rs1Number, type_rs1] = CAPI.ARCH.toJSNumberD(registers[rs1]); [rs2Number, type_rs2] = CAPI.ARCH.toJSNumberD(registers[rs2]); - [rs3Number, type_rs3] = CAPI.ARCH.toJSNumberD(rs3); + [rs3Number, type_rs3] = CAPI.ARCH.toJSNumberD(registers[rs3]); postoperation: | if (CAPI.FP.isNaN(result)) { registers[rd] = CAPI.ARCH.toBigInt(result, "NaN32"); @@ -2994,7 +2976,7 @@ instructions: let result, rs1Number, rs2Number, rs3Number, type_rs1, type_rs2, type_rs3; [rs1Number, type_rs1] = CAPI.ARCH.toJSNumberD(registers[rs1]); [rs2Number, type_rs2] = CAPI.ARCH.toJSNumberD(registers[rs2]); - [rs3Number, type_rs3] = CAPI.ARCH.toJSNumberD(rs3); + [rs3Number, type_rs3] = CAPI.ARCH.toJSNumberD(registers[rs3]); postoperation: | if (CAPI.FP.isNaN(result)) { registers[rd] = CAPI.ARCH.toBigInt(result, "NaN32"); @@ -3021,7 +3003,7 @@ instructions: let result, rs1Number, rs2Number, rs3Number, type_rs1, type_rs2, type_rs3; [rs1Number, type_rs1] = CAPI.ARCH.toJSNumberD(registers[rs1]); [rs2Number, type_rs2] = CAPI.ARCH.toJSNumberD(registers[rs2]); - [rs3Number, type_rs3] = CAPI.ARCH.toJSNumberD(rs3); + [rs3Number, type_rs3] = CAPI.ARCH.toJSNumberD(registers[rs3]); postoperation: | if (CAPI.FP.isNaN(result)) { registers[rd] = CAPI.ARCH.toBigInt(result, "NaN32"); @@ -3048,7 +3030,7 @@ instructions: let result, rs1Number, rs2Number, rs3Number, type_rs1, type_rs2, type_rs3; [rs1Number, type_rs1] = CAPI.ARCH.toJSNumberD(registers[rs1]); [rs2Number, type_rs2] = CAPI.ARCH.toJSNumberD(registers[rs2]); - [rs3Number, type_rs3] = CAPI.ARCH.toJSNumberD(rs3); + [rs3Number, type_rs3] = CAPI.ARCH.toJSNumberD(registers[rs3]); postoperation: | if (CAPI.FP.isNaN(result)) { registers[rd] = CAPI.ARCH.toBigInt(result, "NaN32"); @@ -3213,8 +3195,8 @@ instructions: - field: rs1 type: INT-Reg preoperation: | - let result, rs1Number, type_rs1; - [rs1Number, type_rs1] = CAPI.ARCH.toJSNumberD(registers[rs1]); + let result, rs1Number; + rs1Number = registers[rs1]; postoperation: | registers[rd] = CAPI.ARCH.toBigInt(result, 'float64'); definition: | @@ -3387,17 +3369,11 @@ instructions: - field: rd type: INT-Reg preoperation: | - let result, rs1Number, rs2Number, type_rs1, type_rs2; + let rs1Number, rs2Number, type_rs1, type_rs2; [rs1Number, type_rs1] = CAPI.ARCH.toJSNumberD(registers[rs1]); [rs2Number, type_rs2] = CAPI.ARCH.toJSNumberD(registers[rs2]); - postoperation: | - if (CAPI.FP.isNaN(result)) { - registers[rd] = CAPI.ARCH.toBigInt(result, "NaN64"); - } else { - registers[rd] = CAPI.ARCH.toBigInt(result, "float64"); - } definition: | - registers[rd] = (rs1Number == rs2Number) ? 1 : 0; + registers[rd] = (rs1Number === rs2Number)? 1n : 0n; help: Performs a quiet equal comparison between double-precision floating-point registers rs1 and rs2 and record the Boolean result in integer register rd. Only signaling NaN inputs cause an Invalid @@ -3418,14 +3394,8 @@ instructions: let rs1Number, rs2Number, type_rs1, type_rs2; [rs1Number, type_rs1] = CAPI.ARCH.toJSNumberD(registers[rs1]); [rs2Number, type_rs2] = CAPI.ARCH.toJSNumberD(registers[rs2]); - postoperation: | - if (CAPI.FP.isNaN(result)) { - registers[rd] = CAPI.ARCH.toBigInt(result, "NaN64"); - } else { - registers[rd] = CAPI.ARCH.toBigInt(result, "float64"); - } definition: | - registers[rd] = (rs1Number <= rs2Number) ? 1 : 0; + registers[rd] = (rs1Number <= rs2Number)? 1n : 0n; help: Performs a quiet less or equal comparison between double-precision floating-point registers rs1 and rs2 and record the Boolean result in integer register rd. Only signaling NaN inputs cause an Invalid @@ -3446,14 +3416,8 @@ instructions: let rs1Number, rs2Number, type_rs1, type_rs2; [rs1Number, type_rs1] = CAPI.ARCH.toJSNumberD(registers[rs1]); [rs2Number, type_rs2] = CAPI.ARCH.toJSNumberD(registers[rs2]); - postoperation: | - if (CAPI.FP.isNaN(result)) { - registers[rd] = CAPI.ARCH.toBigInt(result, "NaN64"); - } else { - registers[rd] = CAPI.ARCH.toBigInt(result, "float64"); - } definition: | - registers[rd] = (rs1Number < rs2Number) ? 1 : 0; + registers[rd] = (rs1Number < rs2Number)? 1n : 0n; help: Performs a quiet less comparison between double-precision floating-point registers rs1 and rs2 and record the Boolean result in integer register rd. Only signaling NaN inputs cause an Invalid @@ -3574,7 +3538,7 @@ instructions: registers[rd] = CAPI.ARCH.toBigInt(result, "float64"); } definition: | - registers[rd] = (rs2Number > 0) ? -Math.abs(rs1Number) : +Math.abs(rs1Number); + result = (rs2Number > 0) ? -Math.abs(rs1Number) : +Math.abs(rs1Number); help: Produce a result that takes all bits except the sign bit from rs1. The result's sign bit is opposite of rs2's sign bit. @@ -3600,7 +3564,7 @@ instructions: definition: | let a = rs1Number < 0; let b = rs2Number < 0; - registers[rd] = a ^ b ? -Math.abs(rs1Number) : Math.abs(rs1Number); + result = a ^ b ? -Math.abs(rs1Number) : Math.abs(rs1Number); help: Produce a result that takes all bits except the sign bit from rs1. The result's sign bit is XOR of sign bit of rs1 and rs2. @@ -3621,9 +3585,8 @@ instructions: optional: true order: 3 preoperation: | - let result, rs1Number, rs2Number, type_rs1, type_rs2; + let result, rs1Number, type_rs1; [rs1Number, type_rs1] = CAPI.ARCH.toJSNumberD(registers[rs1]); - [rs2Number, type_rs2] = CAPI.ARCH.toJSNumberD(registers[rs2]); postoperation: | if (CAPI.FP.isNaN(result)) { registers[rd] = CAPI.ARCH.toBigInt(result, "NaN64"); @@ -3632,7 +3595,7 @@ instructions: } definition: | if (rs1Number >= 0) { - registers[rd] = Math.sqrt(rs1Number); + result = Math.sqrt(rs1Number); } else { CAPI.VALIDATION.raise( "Square root of a negative number is not allowed." diff --git a/architecture/RISCV/SRV32.yml b/architecture/RISCV/SRV32.yml index 4857310d4..39758f959 100644 --- a/architecture/RISCV/SRV32.yml +++ b/architecture/RISCV/SRV32.yml @@ -2284,7 +2284,7 @@ instructions: - field: funct3 value: "010" definition: | - registers[rd] = (CAPI.FP.uint2int(registers[rs1]) < CAPI.FP.uint2int(imm)) ? 1 : 0; + registers[rd] = (CAPI.FP.uint2int(registers[rs1]) < CAPI.FP.uint2int(imm)) ? 1n : 0n; help: Place the value 1 in register rd if register rs1 is less than the signextended immediate when both are treated as signed numbers, else 0 is written to rd. - name: sltiu @@ -2297,7 +2297,7 @@ instructions: - field: funct3 value: "011" definition: | - registers[rd] = (CAPI.FP.int2uint(registers[rs1]) < CAPI.FP.int2uint(imm)) ? 1: 0; + registers[rd] = (CAPI.FP.int2uint(registers[rs1]) < CAPI.FP.int2uint(imm)) ? 1n: 0n; help: Place the value 1 in register rd if register rs1 is less than the immediate when both are treated as unsigned numbers, else 0 is written to rd. - name: srai extension: I @@ -2421,7 +2421,7 @@ instructions: - field: funct3 value: "010" definition: | - registers[rd] = (CAPI.FP.uint2int(registers[rs1]) < CAPI.FP.uint2int(registers[rs2])) ? 1 : 0; + registers[rd] = (CAPI.FP.uint2int(registers[rs1]) < CAPI.FP.uint2int(registers[rs2])) ? 1n : 0n; help: Place the value 1 in register rd if register rs1 is less than register rs2 when both are treated as signed numbers, else 0 is written to rd. - name: sltu @@ -2676,13 +2676,11 @@ instructions: - field: funct3 value: "101" definition: | - if (registers[rs2] != 0) { - registers[rd] = BigInt.asIntN( - 32, - (BigInt.asUintN(32, BigInt(registers[rs1])) / BigInt.asUintN(32, BigInt(registers[rs2]))) - ); + const div = registers[rs2] + if (div != 0) { + registers[rd] = CAPI.FP.int2uint(registers[rs1] / div); } - else CAPI.VALIDATION.raise('Division by registers[zero] not allowed'); + else CAPI.VALIDATION.raise('Division by zero not allowed'); help: Perform an XLEN-bit by XLEN-bit unsigned integer division of rs1 by rs2, rounding towards zero. - name: mul extension: M @@ -2709,12 +2707,8 @@ instructions: - field: funct3 value: "001" definition: | - registers[rd] = BigInt.asIntN( - 32, - BigInt.asIntN( - 64, - BigInt.asIntN(32, BigInt(registers[rs1])) * BigInt.asIntN(32, BigInt(registers[rs2])), - ) >> 32n, + registers[rd] = CAPI.FP.int2uint( + (CAPI.FP.uint2int(registers[rs1]) * CAPI.FP.uint2int(registers[rs2])) >> 32n, ); help: Performs an XLEN-bit by XLEN-bit multiplication of signed rs1 by signed rs2 and places the lower XLEN bits in the destination register. - name: mulhsu @@ -2728,12 +2722,8 @@ instructions: - field: funct3 value: "010" definition: | - registers[rd] = BigInt.asIntN( - 32, - BigInt.asIntN( - 64, - BigInt.asIntN(32, BigInt(registers[rs1])) * BigInt.asUintN(32, BigInt(registers[rs2])), - ) >> 32n, + registers[rd] = CAPI.FP.int2uint( + (CAPI.FP.uint2int(registers[rs1]) * registers[rs2]) >> 32n, ); help: Performs an XLEN-bit by XLEN-bit multiplication of signed rs1 by unsigned rs2 and places the upper XLEN bits in the destination register. - name: mulhu @@ -2747,12 +2737,8 @@ instructions: - field: funct3 value: "011" definition: | - registers[rd] = BigInt.asIntN( - 32, - BigInt.asUintN( - 64, - BigInt.asUintN(32, BigInt(registers[rs1])) * BigInt.asUintN(32, BigInt(registers[rs2])), - ) >> 32n, + registers[rd] = CAPI.FP.int2uint( + (registers[rs1] * registers[rs2]) >> 32n, ); help: Performs an XLEN-bit by XLEN-bit multiplication of unsigned rs1 by unsigned rs2 and places the upper XLEN bits in the destination register. - name: rem @@ -2884,9 +2870,9 @@ instructions: optional: true order: 3 postoperation: | - registers[rd] = CAPI.ARCH.toBigInt(registers[rd],'NaNBfloat32_64'); + registers[rd] = CAPI.ARCH.toBigInt(result,'NaNBfloat32_64'); definition: | - registers[rd] = CAPI.FP.uint2int(registers[rs1]) + result = CAPI.FP.uint2int(registers[rs1]) help: Converts a 32-bit signed integer, in integer register rs1 into a floating-point number in floating-point register rd. - name: fcvt.s.wu @@ -3008,18 +2994,11 @@ instructions: - field: rd type: INT-Reg preoperation: | - let result, rs1Number, rs2Number, type_rs1, type_rs2; + let rs1Number, rs2Number, type_rs1, type_rs2; [rs1Number, type_rs1] = CAPI.ARCH.toJSNumberD(registers[rs1]); [rs2Number, type_rs2] = CAPI.ARCH.toJSNumberD(registers[rs2]); - postoperation: | - if (isNaN(result)) { - registers[rd] = CAPI.ARCH.toBigInt(result, "NaN32"); - } else { - registers[rd] = CAPI.ARCH.toBigInt(result, "NaNBfloat32_64"); - } - definition: | - result = (rs1Number === rs2Number) ? 1 : 0; + registers[rd] = (rs1Number === rs2Number)? 1n : 0n; help: Performs a quiet equal comparison between floating-point registers rs1 and rs2 and record the Boolean result in integer register rd. Only signaling NaN inputs cause an Invalid Operation exception. The result is 0 if either operand is NaN. - name: fle.s @@ -3035,18 +3014,11 @@ instructions: - field: rd type: INT-Reg preoperation: | - let result, rs1Number, rs2Number, type_rs1, type_rs2; + let rs1Number, rs2Number, type_rs1, type_rs2; [rs1Number, type_rs1] = CAPI.ARCH.toJSNumberD(registers[rs1]); [rs2Number, type_rs2] = CAPI.ARCH.toJSNumberD(registers[rs2]); - postoperation: | - if (isNaN(result)) { - registers[rd] = CAPI.ARCH.toBigInt(result, "NaN32"); - } else { - registers[rd] = CAPI.ARCH.toBigInt(result, "NaNBfloat32_64"); - } - definition: | - result = (rs1Number <= rs2Number) ? 1 : 0; + registers[rd] = (rs1Number <= rs2Number)? 1n : 0n; help: Performs a quiet less or equal comparison between floating-point registers rs1 and rs2 and record the Boolean result in integer register rd. Only signaling NaN inputs cause an Invalid Operation exception. The result is 0 if either operand is NaN. - name: flt.s @@ -3062,18 +3034,11 @@ instructions: - field: rd type: INT-Reg preoperation: | - let result, rs1Number, rs2Number, type_rs1, type_rs2; + let rs1Number, rs2Number, type_rs1, type_rs2; [rs1Number, type_rs1] = CAPI.ARCH.toJSNumberD(registers[rs1]); [rs2Number, type_rs2] = CAPI.ARCH.toJSNumberD(registers[rs2]); - postoperation: | - if (isNaN(result)) { - registers[rd] = CAPI.ARCH.toBigInt(result, "NaN32"); - } else { - registers[rd] = CAPI.ARCH.toBigInt(result, "NaNBfloat32_64"); - } - definition: | - result = (rs1Number < rs2Number) ? 1 : 0; + registers[rd] = (rs1Number < rs2Number)? 1n : 0n; help: Performs a quiet less comparison between floating-point registers rs1 and rs2 and record the Boolean result in integer register rd. Only signaling NaN inputs cause an Invalid Operation exception. The result is 0 if either operand is NaN. - name: fmax.s @@ -3295,9 +3260,8 @@ instructions: optional: true order: 3 preoperation: | - let result, rs1Number, rs2Number, type_rs1, type_rs2; + let result, rs1Number, type_rs1; [rs1Number, type_rs1] = CAPI.ARCH.toJSNumberD(registers[rs1]); - [rs2Number, type_rs2] = CAPI.ARCH.toJSNumberD(registers[rs2]); postoperation: | if (isNaN(result)) { registers[rd] = CAPI.ARCH.toBigInt(result, "NaN32"); @@ -3310,7 +3274,7 @@ instructions: result = Math.sqrt(rs1Number); } else { CAPI.VALIDATION.raise( - 'Square root of a negative number is not allowed.' + "Square root of a negative number is not allowed." ); } help: Perform single-precision square root. @@ -3359,7 +3323,7 @@ instructions: let result, rs1Number, rs2Number, rs3Number, type_rs1, type_rs2, type_rs3; [rs1Number, type_rs1] = CAPI.ARCH.toJSNumberD(registers[rs1]); [rs2Number, type_rs2] = CAPI.ARCH.toJSNumberD(registers[rs2]); - [rs3Number, type_rs3] = CAPI.ARCH.toJSNumberD(rs3); + [rs3Number, type_rs3] = CAPI.ARCH.toJSNumberD(registers[rs3]); postoperation: | if (isNaN(result)) { registers[rd] = CAPI.ARCH.toBigInt(result, "NaN32"); @@ -3388,7 +3352,7 @@ instructions: let result, rs1Number, rs2Number, rs3Number, type_rs1, type_rs2, type_rs3; [rs1Number, type_rs1] = CAPI.ARCH.toJSNumberD(registers[rs1]); [rs2Number, type_rs2] = CAPI.ARCH.toJSNumberD(registers[rs2]); - [rs3Number, type_rs3] = CAPI.ARCH.toJSNumberD(rs3); + [rs3Number, type_rs3] = CAPI.ARCH.toJSNumberD(registers[rs3]); postoperation: | if (isNaN(result)) { registers[rd] = CAPI.ARCH.toBigInt(result, "NaN32"); @@ -3417,7 +3381,7 @@ instructions: let result, rs1Number, rs2Number, rs3Number, type_rs1, type_rs2, type_rs3; [rs1Number, type_rs1] = CAPI.ARCH.toJSNumberD(registers[rs1]); [rs2Number, type_rs2] = CAPI.ARCH.toJSNumberD(registers[rs2]); - [rs3Number, type_rs3] = CAPI.ARCH.toJSNumberD(rs3); + [rs3Number, type_rs3] = CAPI.ARCH.toJSNumberD(registers[rs3]); postoperation: | if (isNaN(result)) { registers[rd] = CAPI.ARCH.toBigInt(result, "NaN32"); @@ -3446,7 +3410,7 @@ instructions: let result, rs1Number, rs2Number, rs3Number, type_rs1, type_rs2, type_rs3; [rs1Number, type_rs1] = CAPI.ARCH.toJSNumberD(registers[rs1]); [rs2Number, type_rs2] = CAPI.ARCH.toJSNumberD(registers[rs2]); - [rs3Number, type_rs3] = CAPI.ARCH.toJSNumberD(rs3); + [rs3Number, type_rs3] = CAPI.ARCH.toJSNumberD(registers[rs3]); postoperation: | if (isNaN(result)) { registers[rd] = CAPI.ARCH.toBigInt(result, "NaN32"); @@ -3606,8 +3570,8 @@ instructions: - field: rs1 type: INT-Reg preoperation: | - let result, rs1Number, type_rs1; - [rs1Number, type_rs1] = CAPI.ARCH.toJSNumberD(registers[rs1]); + let result, rs1Number; + rs1Number = registers[rs1]; postoperation: | registers[rd] = CAPI.ARCH.toBigInt(result, 'float64'); definition: | @@ -3680,7 +3644,7 @@ instructions: result = rs1Number; // TODO: This doesn't seem right, check the RISC-V manual help: Converts double floating-point register in rs1 into a floating-point number in floating-point register rd. - - name: fcvt.w.d + - name: fcvt.w.d extension: D template: R-Conversion fields: @@ -3714,7 +3678,7 @@ instructions: result = CAPI.FP.int2uint(parseInt(rs1Number)); help: Converts a double-precision floating-point number in floating-point register rs1 to a signed 32-bit integer, in integer register rd. - - name: fcvt.wu.d + - name: fcvt.wu.d extension: D template: R-Conversion fields: @@ -3748,7 +3712,7 @@ instructions: result = CAPI.FP.int2uint(parseInt(rs1Number)); help: Converts a double-precision floating-point number in floating-point register rs1 to a unsigned 32-bit integer, in integer register rd. - - name: fdiv.d + - name: fdiv.d extension: D template: R-Double fields: @@ -3775,7 +3739,7 @@ instructions: definition: | result = rs1Number / rs2Number; help: Perform double-precision floating-point division. - - name: feq.d + - name: feq.d extension: D template: R-Double fields: @@ -3788,16 +3752,14 @@ instructions: - field: rd type: INT-Reg preoperation: | - let result, rs1Number, rs2Number, type_rs1, type_rs2; + let rs1Number, rs2Number, type_rs1, type_rs2; [rs1Number, type_rs1] = CAPI.ARCH.toJSNumberD(registers[rs1]); [rs2Number, type_rs2] = CAPI.ARCH.toJSNumberD(registers[rs2]); - postoperation: | - definition: | - registers[rd] = (rs1Number == rs2Number) ? 1 : 0; + registers[rd] = (rs1Number === rs2Number)? 1n : 0n; help: Performs a quiet equal comparison between double-precision floating-point registers rs1 and rs2 and record the Boolean result in integer register rd. Only signaling NaN inputs cause an Invalid Operation exception. The result is 0 if either operand is NaN. - - name: fle.d + - name: fle.d extension: D template: R-Double fields: @@ -3813,13 +3775,11 @@ instructions: let rs1Number, rs2Number, type_rs1, type_rs2; [rs1Number, type_rs1] = CAPI.ARCH.toJSNumberD(registers[rs1]); [rs2Number, type_rs2] = CAPI.ARCH.toJSNumberD(registers[rs2]); - postoperation: | - definition: | - registers[rd] = (rs1Number <= rs2Number) ? 1 : 0; + registers[rd] = (rs1Number <= rs2Number)? 1n : 0n; help: Performs a quiet less or equal comparison between double-precision floating-point registers rs1 and rs2 and record the Boolean result in integer register rd. Only signaling NaN inputs cause an Invalid Operation exception. The result is 0 if either operand is NaN. - - name: flt.d + - name: flt.d extension: D template: R-Double fields: @@ -3835,13 +3795,11 @@ instructions: let rs1Number, rs2Number, type_rs1, type_rs2; [rs1Number, type_rs1] = CAPI.ARCH.toJSNumberD(registers[rs1]); [rs2Number, type_rs2] = CAPI.ARCH.toJSNumberD(registers[rs2]); - postoperation: | - definition: | - registers[rd] = (rs1Number < rs2Number) ? 1 : 0; + registers[rd] = (rs1Number < rs2Number)? 1n : 0n; help: Performs a quiet less comparison between double-precision floating-point registers rs1 and rs2 and record the Boolean result in integer register rd. Only signaling NaN inputs cause an Invalid Operation exception. The result is 0 if either operand is NaN. - - name: fmax.d + - name: fmax.d extension: D template: R-Double fields: @@ -3866,7 +3824,7 @@ instructions: result = Math.max(rs1Number, rs2Number); help: Write the larger of double precision data in rs1 and rs2 to rd. - - name: fmin.d + - name: fmin.d extension: D template: R-Double fields: @@ -3891,7 +3849,7 @@ instructions: result = Math.min(rs1Number, rs2Number); help: Write the smaller of double precision data in rs1 and rs2 to rd. - - name: fmul.d + - name: fmul.d extension: D template: R-Double fields: @@ -3919,7 +3877,7 @@ instructions: result = rs1Number * rs2Number; help: Perform double-precision floating-point addition. - - name: fsgnj.d + - name: fsgnj.d extension: D template: R-Double fields: @@ -3943,7 +3901,7 @@ instructions: definition: | registers[rd] = (rs2Number > 0) ? Math.abs(rs1Number) : -Math.abs(rs1Number); help: Perform double-precision floating-point multiplication. - - name: fsgnjn.d + - name: fsgnjn.d extension: D template: R-Double fields: @@ -3965,10 +3923,10 @@ instructions: } definition: | - registers[rd] = (rs2Number > 0) ? -Math.abs(rs1Number) : +Math.abs(rs1Number); + result = (rs2Number > 0) ? -Math.abs(rs1Number) : +Math.abs(rs1Number); help: Produce a result that takes all bits except the sign bit from rs1. The result's sign bit is opposite of rs2's sign bit. - - name: fsgnjx.d + - name: fsgnjx.d extension: D template: R-Double fields: @@ -3992,9 +3950,9 @@ instructions: definition: | let a = rs1Number < 0; let b = rs2Number < 0; - registers[rd] = a ^ b ? -Math.abs(rs1Number) : Math.abs(rs1Number); + result = a ^ b ? -Math.abs(rs1Number) : Math.abs(rs1Number); help: Produce a result that takes all bits except the sign bit from rs1. The result's sign bit is XOR of sign bit of rs1 and rs2. - - name: fsqrt.d + - name: fsqrt.d extension: D template: R-Double fields: @@ -4012,9 +3970,8 @@ instructions: optional: true order: 3 preoperation: | - let result, rs1Number, rs2Number, type_rs1, type_rs2; + let result, rs1Number, type_rs1; [rs1Number, type_rs1] = CAPI.ARCH.toJSNumberD(registers[rs1]); - [rs2Number, type_rs2] = CAPI.ARCH.toJSNumberD(registers[rs2]); postoperation: | if (isNaN(result)) { registers[rd] = CAPI.ARCH.toBigInt(result, "NaN64"); @@ -4024,14 +3981,14 @@ instructions: definition: | if (rs1Number >= 0) { - registers[rd] = Math.sqrt(rs1Number); + result = Math.sqrt(rs1Number); } else { CAPI.VALIDATION.raise( "Square root of a negative number is not allowed." ); } help: Perform double-precision square root. - - name: fsub.d + - name: fsub.d extension: D template: R-Double fields: @@ -4059,7 +4016,7 @@ instructions: result = rs1Number - rs2Number; help: Perform double-precision floating-point addition. - - name: fmadd.d + - name: fmadd.d extension: D template: R4-Double fields: @@ -4089,7 +4046,7 @@ instructions: result = rs1Number * rs2Number + rs3Number; help: Perform double-precision fused multiply addition. - - name: fmsub.d + - name: fmsub.d extension: D template: R4-Double fields: @@ -4119,7 +4076,7 @@ instructions: result = rs1Number * rs2Number - rs3Number; help: Perform double-precision fused multiply subtraction. - - name: fnmadd.d + - name: fnmadd.d extension: D template: R4-Double fields: @@ -4149,7 +4106,7 @@ instructions: result = -rs1Number * rs2Number - rs3Number; help: Perform negated double-precision fused multiply addition. - - name: fnmsub.d + - name: fnmsub.d extension: D template: R4-Double fields: @@ -4179,7 +4136,7 @@ instructions: result = -rs1Number * rs2Number + rs3Number; help: Perform negated double-precision fused multiply subtraction. - - name: fsd + - name: fsd extension: D template: S fields: @@ -4197,7 +4154,7 @@ instructions: CAPI.MEM.addHint(registers[rs1] + imm, "float64", 64); help: Store a double-precision value from the floating-point registers to memory. Zifencei: - - name: fence.i + - name: fence.i extension: D template: Custom type: Syscall diff --git a/architecture/RISCV/SRV64.yml b/architecture/RISCV/SRV64.yml index e3d6e6cba..e6d6813a7 100644 --- a/architecture/RISCV/SRV64.yml +++ b/architecture/RISCV/SRV64.yml @@ -2282,7 +2282,7 @@ instructions: - field: funct3 value: "010" definition: | - registers[rd] = (CAPI.FP.uint2int(registers[rs1]) < CAPI.FP.uint2int(imm)) ? 1 : 0; + registers[rd] = (CAPI.FP.uint2int(registers[rs1]) < CAPI.FP.uint2int(imm)) ? 1n : 0n; help: Place the value 1 in register rd if register rs1 is less than the signextended immediate when both are treated as signed numbers, else 0 is written to rd. - name: sltiu @@ -2295,7 +2295,7 @@ instructions: - field: funct3 value: "011" definition: | - registers[rd] = (CAPI.FP.int2uint(registers[rs1]) < CAPI.FP.int2uint(imm)) ? 1: 0; + registers[rd] = (CAPI.FP.int2uint(registers[rs1]) < CAPI.FP.int2uint(imm)) ? 1n: 0n; help: Place the value 1 in register rd if register rs1 is less than the immediate when both are treated as unsigned numbers, else 0 is written to rd. - name: srai extension: I @@ -2309,7 +2309,7 @@ instructions: - field: funct7 value: "0100000" definition: | - if (shamt > 0) registers[rd] = CAPI.FP.int2uint(registers[rs1] >> shamt); + if (shamt > 0) registers[rd] = (BigInt.asIntN(64, registers[rs1]) >> shamt); help: Performs arithmetic right shift on the value in register rs1 by the shift amount held in the lower 5 bits of the immediate. - name: srli @@ -2419,7 +2419,7 @@ instructions: - field: funct3 value: "010" definition: | - registers[rd] = (CAPI.FP.uint2int(registers[rs1]) < CAPI.FP.uint2int(registers[rs2])) ? 1 : 0; + registers[rd] = (CAPI.FP.uint2int(registers[rs1]) < CAPI.FP.uint2int(registers[rs2])) ? 1n : 0n; help: Place the value 1 in register rd if register rs1 is less than register rs2 when both are treated as signed numbers, else 0 is written to rd. - name: sltu @@ -2655,13 +2655,14 @@ instructions: - field: funct3 value: "101" definition: | - if (registers[rs2] != 0) { + const div = registers[rs2] + if (div != 0) { registers[rd] = BigInt.asIntN( 32, - (BigInt.asUintN(32, BigInt(registers[rs1])) / BigInt.asUintN(32, BigInt(registers[rs2]))) + (BigInt.asUintN(32, registers[rs1]) / BigInt.asUintN(32, div)) ); } - else CAPI.VALIDATION.raise('Division by registers[zero] not allowed'); + else CAPI.VALIDATION.raise('Division by zero not allowed'); help: Perform an XLEN-bit by XLEN-bit unsigned integer division of rs1 by rs2, rounding towards zero. - name: mul extension: M @@ -2688,11 +2689,11 @@ instructions: - field: funct3 value: "001" definition: | - registers[rd] = BigInt.asIntN( + registers[rd] = BigInt.asUintN( 32, BigInt.asIntN( 64, - BigInt.asIntN(32, BigInt(registers[rs1])) * BigInt.asIntN(32, BigInt(registers[rs2])), + BigInt.asIntN(32, registers[rs1]) * BigInt.asIntN(32, registers[rs2]), ) >> 32n, ); help: Performs an XLEN-bit by XLEN-bit multiplication of signed rs1 by signed rs2 and places the lower XLEN bits in the destination register. @@ -2711,7 +2712,7 @@ instructions: 32, BigInt.asIntN( 64, - BigInt.asIntN(32, BigInt(registers[rs1])) * BigInt.asUintN(32, BigInt(registers[rs2])), + BigInt.asIntN(32, registers[rs1]) * BigInt.asUintN(32, registers[rs2]), ) >> 32n, ); help: Performs an XLEN-bit by XLEN-bit multiplication of signed rs1 by unsigned rs2 and places the upper XLEN bits in the destination register. @@ -2730,7 +2731,7 @@ instructions: 32, BigInt.asUintN( 64, - BigInt.asUintN(32, BigInt(registers[rs1])) * BigInt.asUintN(32, BigInt(registers[rs2])), + BigInt.asUintN(32, registers[rs1]) * BigInt.asUintN(32, registers[rs2]), ) >> 32n, ); help: Performs an XLEN-bit by XLEN-bit multiplication of unsigned rs1 by unsigned rs2 and places the upper XLEN bits in the destination register. @@ -2863,9 +2864,9 @@ instructions: optional: true order: 3 postoperation: | - registers[rd] = CAPI.ARCH.toBigInt(registers[rd],'NaNBfloat32_64'); + registers[rd] = CAPI.ARCH.toBigInt(result,'NaNBfloat32_64'); definition: | - registers[rd] = CAPI.FP.uint2int(registers[rs1]) + result = CAPI.FP.uint2int(registers[rs1]) help: Converts a 32-bit signed integer, in integer register rs1 into a floating-point number in floating-point register rd. - name: fcvt.s.wu @@ -2987,18 +2988,11 @@ instructions: - field: rd type: INT-Reg preoperation: | - let result, rs1Number, rs2Number, type_rs1, type_rs2; + let rs1Number, rs2Number, type_rs1, type_rs2; [rs1Number, type_rs1] = CAPI.ARCH.toJSNumberD(registers[rs1]); [rs2Number, type_rs2] = CAPI.ARCH.toJSNumberD(registers[rs2]); - postoperation: | - if (isNaN(result)) { - registers[rd] = CAPI.ARCH.toBigInt(result, "NaN32"); - } else { - registers[rd] = CAPI.ARCH.toBigInt(result, "NaNBfloat32_64"); - } - definition: | - result = (rs1Number === rs2Number) ? 1 : 0; + registers[rd] = (rs1Number === rs2Number)? 1n : 0n; help: Performs a quiet equal comparison between floating-point registers rs1 and rs2 and record the Boolean result in integer register rd. Only signaling NaN inputs cause an Invalid Operation exception. The result is 0 if either operand is NaN. - name: fle.s @@ -3014,18 +3008,11 @@ instructions: - field: rd type: INT-Reg preoperation: | - let result, rs1Number, rs2Number, type_rs1, type_rs2; + let rs1Number, rs2Number, type_rs1, type_rs2; [rs1Number, type_rs1] = CAPI.ARCH.toJSNumberD(registers[rs1]); [rs2Number, type_rs2] = CAPI.ARCH.toJSNumberD(registers[rs2]); - postoperation: | - if (isNaN(result)) { - registers[rd] = CAPI.ARCH.toBigInt(result, "NaN32"); - } else { - registers[rd] = CAPI.ARCH.toBigInt(result, "NaNBfloat32_64"); - } - definition: | - result = (rs1Number <= rs2Number) ? 1 : 0; + registers[rd] = (rs1Number <= rs2Number)? 1n : 0n; help: Performs a quiet less or equal comparison between floating-point registers rs1 and rs2 and record the Boolean result in integer register rd. Only signaling NaN inputs cause an Invalid Operation exception. The result is 0 if either operand is NaN. - name: flt.s @@ -3041,18 +3028,11 @@ instructions: - field: rd type: INT-Reg preoperation: | - let result, rs1Number, rs2Number, type_rs1, type_rs2; + let rs1Number, rs2Number, type_rs1, type_rs2; [rs1Number, type_rs1] = CAPI.ARCH.toJSNumberD(registers[rs1]); [rs2Number, type_rs2] = CAPI.ARCH.toJSNumberD(registers[rs2]); - postoperation: | - if (isNaN(result)) { - registers[rd] = CAPI.ARCH.toBigInt(result, "NaN32"); - } else { - registers[rd] = CAPI.ARCH.toBigInt(result, "NaNBfloat32_64"); - } - definition: | - result = (rs1Number < rs2Number) ? 1 : 0; + registers[rd] = (rs1Number < rs2Number)? 1n : 0n; help: Performs a quiet less comparison between floating-point registers rs1 and rs2 and record the Boolean result in integer register rd. Only signaling NaN inputs cause an Invalid Operation exception. The result is 0 if either operand is NaN. - name: fmax.s @@ -3274,9 +3254,8 @@ instructions: optional: true order: 3 preoperation: | - let result, rs1Number, rs2Number, type_rs1, type_rs2; + let result, rs1Number, type_rs1; [rs1Number, type_rs1] = CAPI.ARCH.toJSNumberD(registers[rs1]); - [rs2Number, type_rs2] = CAPI.ARCH.toJSNumberD(registers[rs2]); postoperation: | if (isNaN(result)) { registers[rd] = CAPI.ARCH.toBigInt(result, "NaN32"); @@ -3289,7 +3268,7 @@ instructions: result = Math.sqrt(rs1Number); } else { CAPI.VALIDATION.raise( - 'Square root of a negative number is not allowed.' + "Square root of a negative number is not allowed." ); } help: Perform single-precision square root. @@ -3338,7 +3317,7 @@ instructions: let result, rs1Number, rs2Number, rs3Number, type_rs1, type_rs2, type_rs3; [rs1Number, type_rs1] = CAPI.ARCH.toJSNumberD(registers[rs1]); [rs2Number, type_rs2] = CAPI.ARCH.toJSNumberD(registers[rs2]); - [rs3Number, type_rs3] = CAPI.ARCH.toJSNumberD(rs3); + [rs3Number, type_rs3] = CAPI.ARCH.toJSNumberD(registers[rs3]); postoperation: | if (isNaN(result)) { registers[rd] = CAPI.ARCH.toBigInt(result, "NaN32"); @@ -3367,7 +3346,7 @@ instructions: let result, rs1Number, rs2Number, rs3Number, type_rs1, type_rs2, type_rs3; [rs1Number, type_rs1] = CAPI.ARCH.toJSNumberD(registers[rs1]); [rs2Number, type_rs2] = CAPI.ARCH.toJSNumberD(registers[rs2]); - [rs3Number, type_rs3] = CAPI.ARCH.toJSNumberD(rs3); + [rs3Number, type_rs3] = CAPI.ARCH.toJSNumberD(registers[rs3]); postoperation: | if (isNaN(result)) { registers[rd] = CAPI.ARCH.toBigInt(result, "NaN32"); @@ -3396,7 +3375,7 @@ instructions: let result, rs1Number, rs2Number, rs3Number, type_rs1, type_rs2, type_rs3; [rs1Number, type_rs1] = CAPI.ARCH.toJSNumberD(registers[rs1]); [rs2Number, type_rs2] = CAPI.ARCH.toJSNumberD(registers[rs2]); - [rs3Number, type_rs3] = CAPI.ARCH.toJSNumberD(rs3); + [rs3Number, type_rs3] = CAPI.ARCH.toJSNumberD(registers[rs3]); postoperation: | if (isNaN(result)) { registers[rd] = CAPI.ARCH.toBigInt(result, "NaN32"); @@ -3425,7 +3404,7 @@ instructions: let result, rs1Number, rs2Number, rs3Number, type_rs1, type_rs2, type_rs3; [rs1Number, type_rs1] = CAPI.ARCH.toJSNumberD(registers[rs1]); [rs2Number, type_rs2] = CAPI.ARCH.toJSNumberD(registers[rs2]); - [rs3Number, type_rs3] = CAPI.ARCH.toJSNumberD(rs3); + [rs3Number, type_rs3] = CAPI.ARCH.toJSNumberD(registers[rs3]); postoperation: | if (isNaN(result)) { registers[rd] = CAPI.ARCH.toBigInt(result, "NaN32"); @@ -3585,8 +3564,8 @@ instructions: - field: rs1 type: INT-Reg preoperation: | - let result, rs1Number, type_rs1; - [rs1Number, type_rs1] = CAPI.ARCH.toJSNumberD(registers[rs1]); + let result, rs1Number; + rs1Number = registers[rs1]; postoperation: | registers[rd] = CAPI.ARCH.toBigInt(result, 'float64'); definition: | @@ -3659,7 +3638,7 @@ instructions: result = rs1Number; // TODO: This doesn't seem right, check the RISC-V manual help: Converts double floating-point register in rs1 into a floating-point number in floating-point register rd. - - name: fcvt.w.d + - name: fcvt.w.d extension: D template: R-Conversion fields: @@ -3693,7 +3672,7 @@ instructions: result = CAPI.FP.int2uint(parseInt(rs1Number)); help: Converts a double-precision floating-point number in floating-point register rs1 to a signed 32-bit integer, in integer register rd. - - name: fcvt.wu.d + - name: fcvt.wu.d extension: D template: R-Conversion fields: @@ -3727,7 +3706,7 @@ instructions: result = CAPI.FP.int2uint(parseInt(rs1Number)); help: Converts a double-precision floating-point number in floating-point register rs1 to a unsigned 32-bit integer, in integer register rd. - - name: fdiv.d + - name: fdiv.d extension: D template: R-Double fields: @@ -3754,7 +3733,7 @@ instructions: definition: | result = rs1Number / rs2Number; help: Perform double-precision floating-point division. - - name: feq.d + - name: feq.d extension: D template: R-Double fields: @@ -3767,16 +3746,14 @@ instructions: - field: rd type: INT-Reg preoperation: | - let result, rs1Number, rs2Number, type_rs1, type_rs2; + let rs1Number, rs2Number, type_rs1, type_rs2; [rs1Number, type_rs1] = CAPI.ARCH.toJSNumberD(registers[rs1]); [rs2Number, type_rs2] = CAPI.ARCH.toJSNumberD(registers[rs2]); - postoperation: | - definition: | - registers[rd] = (rs1Number == rs2Number) ? 1 : 0; + registers[rd] = (rs1Number == rs2Number)? 1n : 0n; help: Performs a quiet equal comparison between double-precision floating-point registers rs1 and rs2 and record the Boolean result in integer register rd. Only signaling NaN inputs cause an Invalid Operation exception. The result is 0 if either operand is NaN. - - name: fle.d + - name: fle.d extension: D template: R-Double fields: @@ -3792,13 +3769,11 @@ instructions: let rs1Number, rs2Number, type_rs1, type_rs2; [rs1Number, type_rs1] = CAPI.ARCH.toJSNumberD(registers[rs1]); [rs2Number, type_rs2] = CAPI.ARCH.toJSNumberD(registers[rs2]); - postoperation: | - definition: | - registers[rd] = (rs1Number <= rs2Number) ? 1 : 0; + registers[rd] = (rs1Number <= rs2Number) ? 1n : 0n; help: Performs a quiet less or equal comparison between double-precision floating-point registers rs1 and rs2 and record the Boolean result in integer register rd. Only signaling NaN inputs cause an Invalid Operation exception. The result is 0 if either operand is NaN. - - name: flt.d + - name: flt.d extension: D template: R-Double fields: @@ -3814,13 +3789,11 @@ instructions: let rs1Number, rs2Number, type_rs1, type_rs2; [rs1Number, type_rs1] = CAPI.ARCH.toJSNumberD(registers[rs1]); [rs2Number, type_rs2] = CAPI.ARCH.toJSNumberD(registers[rs2]); - postoperation: | - definition: | - registers[rd] = (rs1Number < rs2Number) ? 1 : 0; + registers[rd] = (rs1Number < rs2Number)? 1n : 0n; help: Performs a quiet less comparison between double-precision floating-point registers rs1 and rs2 and record the Boolean result in integer register rd. Only signaling NaN inputs cause an Invalid Operation exception. The result is 0 if either operand is NaN. - - name: fmax.d + - name: fmax.d extension: D template: R-Double fields: @@ -3845,7 +3818,7 @@ instructions: result = Math.max(rs1Number, rs2Number); help: Write the larger of double precision data in rs1 and rs2 to rd. - - name: fmin.d + - name: fmin.d extension: D template: R-Double fields: @@ -3870,7 +3843,7 @@ instructions: result = Math.min(rs1Number, rs2Number); help: Write the smaller of double precision data in rs1 and rs2 to rd. - - name: fmul.d + - name: fmul.d extension: D template: R-Double fields: @@ -3898,7 +3871,7 @@ instructions: result = rs1Number * rs2Number; help: Perform double-precision floating-point addition. - - name: fsgnj.d + - name: fsgnj.d extension: D template: R-Double fields: @@ -3922,7 +3895,7 @@ instructions: definition: | registers[rd] = (rs2Number > 0) ? Math.abs(rs1Number) : -Math.abs(rs1Number); help: Perform double-precision floating-point multiplication. - - name: fsgnjn.d + - name: fsgnjn.d extension: D template: R-Double fields: @@ -3944,10 +3917,10 @@ instructions: } definition: | - registers[rd] = (rs2Number > 0) ? -Math.abs(rs1Number) : +Math.abs(rs1Number); + result = (rs2Number > 0) ? -Math.abs(rs1Number) : +Math.abs(rs1Number); help: Produce a result that takes all bits except the sign bit from rs1. The result's sign bit is opposite of rs2's sign bit. - - name: fsgnjx.d + - name: fsgnjx.d extension: D template: R-Double fields: @@ -3971,9 +3944,9 @@ instructions: definition: | let a = rs1Number < 0; let b = rs2Number < 0; - registers[rd] = a ^ b ? -Math.abs(rs1Number) : Math.abs(rs1Number); + result = a ^ b ? -Math.abs(rs1Number) : Math.abs(rs1Number); help: Produce a result that takes all bits except the sign bit from rs1. The result's sign bit is XOR of sign bit of rs1 and rs2. - - name: fsqrt.d + - name: fsqrt.d extension: D template: R-Double fields: @@ -3991,9 +3964,8 @@ instructions: optional: true order: 3 preoperation: | - let result, rs1Number, rs2Number, type_rs1, type_rs2; + let result, rs1Number, type_rs1; [rs1Number, type_rs1] = CAPI.ARCH.toJSNumberD(registers[rs1]); - [rs2Number, type_rs2] = CAPI.ARCH.toJSNumberD(registers[rs2]); postoperation: | if (isNaN(result)) { registers[rd] = CAPI.ARCH.toBigInt(result, "NaN64"); @@ -4003,14 +3975,14 @@ instructions: definition: | if (rs1Number >= 0) { - registers[rd] = Math.sqrt(rs1Number); + result = Math.sqrt(rs1Number); } else { CAPI.VALIDATION.raise( "Square root of a negative number is not allowed." ); } help: Perform double-precision square root. - - name: fsub.d + - name: fsub.d extension: D template: R-Double fields: @@ -4038,7 +4010,7 @@ instructions: result = rs1Number - rs2Number; help: Perform double-precision floating-point addition. - - name: fmadd.d + - name: fmadd.d extension: D template: R4-Double fields: @@ -4068,7 +4040,7 @@ instructions: result = rs1Number * rs2Number + rs3Number; help: Perform double-precision fused multiply addition. - - name: fmsub.d + - name: fmsub.d extension: D template: R4-Double fields: @@ -4098,7 +4070,7 @@ instructions: result = rs1Number * rs2Number - rs3Number; help: Perform double-precision fused multiply subtraction. - - name: fnmadd.d + - name: fnmadd.d extension: D template: R4-Double fields: @@ -4128,7 +4100,7 @@ instructions: result = -rs1Number * rs2Number - rs3Number; help: Perform negated double-precision fused multiply addition. - - name: fnmsub.d + - name: fnmsub.d extension: D template: R4-Double fields: @@ -4158,7 +4130,7 @@ instructions: result = -rs1Number * rs2Number + rs3Number; help: Perform negated double-precision fused multiply subtraction. - - name: fsd + - name: fsd extension: D template: S fields: @@ -4176,7 +4148,7 @@ instructions: CAPI.MEM.addHint(registers[rs1] + imm, "float64", 64); help: Store a double-precision value from the floating-point registers to memory. Zifencei: - - name: fence.i + - name: fence.i extension: D template: Custom type: Syscall From 7656b99847c67d337060282eda4e66c5d0590d60 Mon Sep 17 00:00:00 2001 From: ALVAROPING1 Date: Mon, 16 Mar 2026 14:11:49 +0100 Subject: [PATCH 22/85] fix(RISCV): fix ecall handler not popping the stack frame --- architecture/RISCV/RV32IMFD.yml | 1 + architecture/RISCV/RV64IMFD.yml | 1 + 2 files changed, 2 insertions(+) diff --git a/architecture/RISCV/RV32IMFD.yml b/architecture/RISCV/RV32IMFD.yml index 34656289f..dc6ea9c8d 100644 --- a/architecture/RISCV/RV32IMFD.yml +++ b/architecture/RISCV/RV32IMFD.yml @@ -4033,6 +4033,7 @@ interrupts: break; } CAPI.INTERRUPTS.clearHighlight(); + CAPI.STACK.endFrame(); custom: | CAPI.INTERRUPTS.globalDisable(); diff --git a/architecture/RISCV/RV64IMFD.yml b/architecture/RISCV/RV64IMFD.yml index a3de7308c..a87bb6f19 100644 --- a/architecture/RISCV/RV64IMFD.yml +++ b/architecture/RISCV/RV64IMFD.yml @@ -4222,6 +4222,7 @@ interrupts: break; } CAPI.INTERRUPTS.clearHighlight(); + CAPI.STACK.endFrame(); custom: | CAPI.INTERRUPTS.globalDisable(); From 4d95f60c754ae6ee7041faa3f1fde61185672c7c Mon Sep 17 00:00:00 2001 From: ALVAROPING1 Date: Mon, 16 Mar 2026 15:16:10 +0100 Subject: [PATCH 23/85] fix(MIPS): fix many incorrect instruction definitions --- architecture/MIPS32.yml | 154 ++++++++++++++++++++++++---------------- 1 file changed, 94 insertions(+), 60 deletions(-) diff --git a/architecture/MIPS32.yml b/architecture/MIPS32.yml index 51dc9055b..fe560f84e 100644 --- a/architecture/MIPS32.yml +++ b/architecture/MIPS32.yml @@ -1035,13 +1035,36 @@ instructions: fields: - field: function value: "000101" + - field: fmt + type: cop + value: "00000" - field: ft order: null value: "00000" preoperation: | - let fsValue = CAPI.FS.uint2float32(registers[fs]); + let fsValue = CAPI.FP.uint2float32(registers[fs]); postoperation: | - fd = CAPI.FS.float322uint(result); + registers[fd] = CAPI.FP.float322uint(result); + definition: | + let result = Math.abs(fsValue); + - name: abs.d + type: Arithmetic floating point + template: FPU_R + nwords: 1 + clk_cycles: 1 + fields: + - field: function + value: "000101" + - field: fmt + type: cop + value: "00001" + - field: ft + order: null + value: "00000" + preoperation: | + let fsValue = CAPI.ARCH.readDouble(fs); + postoperation: | + CAPI.ARCH.writeDouble(result, fd) definition: | let result = Math.abs(fsValue); @@ -1074,10 +1097,10 @@ instructions: value: "00000" type: cop preoperation: | - fsValue = CAPI.FS.uint2float32(registers[fs]); - ftValue = CAPI.FS.uint2float32(registers[ft]); + fsValue = CAPI.FP.uint2float32(registers[fs]); + ftValue = CAPI.FP.uint2float32(registers[ft]); postoperation: | - registers[fd] = CAPI.FS.float322uint(result); + registers[fd] = CAPI.FP.float322uint(result); definition: | let result = fsValue + ftValue; @@ -1167,7 +1190,7 @@ instructions: - field: opcode value: "001100" definition: | - registers[rt] = registers[rs] & (imm & 0xFFFF); + registers[rt] = registers[rs] & (imm & 0xFFFFn); - name: bc template: Custom @@ -1337,8 +1360,10 @@ instructions: - field: imm type: offset_bytes definition: | + const pc = registers.PC + registers.ra = pc if (CAPI.FP.uint2int(registers[rs]) >= 0) { - registers.PC = registers.PC - 4n + imm; + registers.PC = pc - 4n + imm; CAPI.STACK.beginFrame(registers[rs]); } @@ -1691,7 +1716,9 @@ instructions: startbit: 5 stopbit: 0 value: "100001" - definition: registers[fd] = registers[fs]; + definition: | + let val = CAPI.FP.uint2float32(registers[fs]); + CAPI.ARCH.writeDouble(val, fd); - name: cvt.d.w template: Custom type: Arithmetic floating point @@ -1712,7 +1739,7 @@ instructions: stopbit: 21 value: "00001" - field: fs - type: SFP-Reg + type: INT-Reg startbit: 15 stopbit: 11 order: 2 @@ -1730,7 +1757,7 @@ instructions: startbit: 5 stopbit: 0 value: "100001" - definition: registers[fd] = registers[fs]; + definition: CAPI.ARCH.writeDouble(Number(CAPI.FP.uint2int(registers[fs])), fd); - name: cvt.s.d template: Custom type: Arithmetic floating point @@ -1770,8 +1797,8 @@ instructions: stopbit: 0 value: "100000" definition: | - let val = CAPI.FS.uint2float32(registers[fs]); - CAPI.ARCH.writeDouble(val, fd); + let val = CAPI.ARCH.readDouble(fs); + registers[fd] = CAPI.FP.float322uint(val, fd); - name: cvt.s.w template: Custom type: Arithmetic floating point @@ -1792,7 +1819,7 @@ instructions: stopbit: 21 value: "00010" - field: fs - type: SFP-Reg + type: INT-Reg startbit: 15 stopbit: 11 order: 2 @@ -1810,7 +1837,7 @@ instructions: startbit: 5 stopbit: 0 value: "100000" - definition: registers[fd] = parseFloat(float2int_v2(registers[fs])); + definition: registers[fd] = CAPI.FP.float322uint(Number(CAPI.FP.uint2int(registers[fs]))); - name: cvt.w.d template: Custom type: Arithmetic floating point @@ -1838,7 +1865,7 @@ instructions: prefix: $ suffix: "," - field: fd - type: SFP-Reg + type: INT-Reg startbit: 10 stopbit: 6 order: 1 @@ -1851,7 +1878,7 @@ instructions: value: "100100" definition: | let val = CAPI.ARCH.readDouble(fs); - CAPI.REG.write(BigInt(Math.trunc(val)), fd); + CAPI.REG.write(CAPI.FP.int2uint(BigInt(Math.trunc(val))), fd); - name: cvt.w.s template: Custom type: Arithmetic floating point @@ -1879,7 +1906,7 @@ instructions: prefix: $ suffix: "," - field: fd - type: SFP-Reg + type: INT-Reg startbit: 10 stopbit: 6 order: 1 @@ -1890,7 +1917,9 @@ instructions: startbit: 5 stopbit: 0 value: "100100" - definition: registers[fd] = parseInt(registers[fs]); + definition: | + let val = CAPI.FP.uint2float32(registers[fs]); + CAPI.REG.write(CAPI.FP.int2uint(BigInt(Math.trunc(val))), fd); - name: div template: Custom type: Arithmetic integer @@ -2093,10 +2122,10 @@ instructions: stopbit: 0 value: "000011" preoperation: | - fsValue = CAPI.FS.uint2float32(fs); - ftValue = CAPI.FS.uint2float32(ft); + fsValue = CAPI.FP.uint2float32(registers[fs]); + ftValue = CAPI.FP.uint2float32(registers[ft]); postoperation: | - fd = CAPI.FS.float322uint(result); + registers[fd] = CAPI.FP.float322uint(result); definition: |- let result; if (ftValue != 0) @@ -2148,7 +2177,7 @@ instructions: value: "011011" definition: |- if (registers[rt] != 0) - { registers[rd] = Math.floor(CAPI.FP.int2uint(registers[rs]) / CAPI.FP.int2uint(registers[rt])); } + { registers[rd] = CAPI.FP.int2uint(registers[rs]) / CAPI.FP.int2uint(registers[rt]); } else { CAPI.VALIDATION.raise('Division by zero not allowed'); } - name: divu template: Custom @@ -2184,9 +2213,9 @@ instructions: value: "011011" definition: |- if (registers[rt] != 0) - { registers.LO = Math.floor(CAPI.FP.int2uint(registers[rs]) / CAPI.FP.int2uint(registers[rt])); - registers.HI = CAPI.FP.int2uint(registers[rs]) % CAPI.FP.int2uint(registers[rt]); } - else { CAPI.VALIDATION.raise('Division by zero not allowed'); } + { registers.LO = CAPI.FP.int2uint(registers[rs]) / CAPI.FP.int2uint(registers[rt]); + registers.HI = CAPI.FP.int2uint(registers[rs]) % CAPI.FP.int2uint(registers[rt]); } + else { CAPI.VALIDATION.raise('Division by zero not allowed'); } - name: j template: Custom type: Unconditional bifurcation @@ -2839,9 +2868,9 @@ instructions: stopbit: 0 value: "000110" preoperation: | - fsValue = CAPI.FS.uint2float32(fs); + fsValue = CAPI.FP.uint2float32(fs); postoperation: | - registers[fd] = CAPI.FS.float322uint(result); + registers[fd] = CAPI.FP.float322uint(result); definition: let result = fsValue; - name: mtc1 template: Custom @@ -2875,7 +2904,7 @@ instructions: stopbit: 11 order: 2 prefix: $ - definition: registers[fs] = CAPI.FP.uint2float32(registers[rt]); + definition: registers[fs] = registers[rt]; - name: mthi template: Custom type: Transfer between registers @@ -3064,10 +3093,10 @@ instructions: stopbit: 0 value: "000010" preoperation: | - fsValue = CAPI.FS.uint2float32(fs); - ftValue = CAPI.FS.uint2float32(ft); + fsValue = CAPI.FP.uint2float32(registers[fs]); + ftValue = CAPI.FP.uint2float32(registers[ft]); postoperation: | - registers[fd] = CAPI.FS.float322uint(result); + registers[fd] = CAPI.FP.float322uint(result); definition: | let result = fsValue * ftValue; - name: mult @@ -3104,8 +3133,8 @@ instructions: value: "011000" definition: |- let result = CAPI.FP.uint2int(registers[rs]) * CAPI.FP.uint2int(registers[rt]); - registers.HI = Math.floor(result / Math.pow (2, 32)); - registers.LO = result % Math.pow(2, 32); + registers.HI = CAPI.FP.int2uint(result >> 32n); + registers.LO = CAPI.FP.int2uint(result & 0xFFFFFFFFn); - name: multu template: Custom type: Arithmetic integer @@ -3140,10 +3169,8 @@ instructions: value: "011001" definition: |- let result = CAPI.FP.int2uint(registers[rs]) * CAPI.FP.int2uint(registers[rt]); - registers.HI = Math.floor(result / Math.pow(2, 32)); - registers.HI = registers.HI >>> 0; // TODO: This is broken with bigints. - registers.LO = result % Math.pow(2, 32); - registers.LO = registers.LO >>> 0; + registers.HI = CAPI.FP.int2uint(result >> 32n); + registers.LO = CAPI.FP.int2uint(result & 0xFFFFFFFFn); - name: nop template: Custom type: Logic @@ -3322,7 +3349,7 @@ instructions: stopbit: 0 value: "000010" definition: | - registers[rd] = CAPI.FP.int2uint((registers[rt] >>> sa) | (registers[rt] << (32 - sa))); // TODO: This is broken with bigints. + registers[rd] = CAPI.FP.int2uint((CAPI.FP.int2uint(registers[rt]) >> sa) | (registers[rt] << (32n - sa))); - name: rsqrt.d template: Custom type: Arithmetic floating point @@ -3409,9 +3436,9 @@ instructions: stopbit: 0 value: "010110" preoperation: | - fsValue = CAPI.FS.uint2float32(fs); + fsValue = CAPI.FP.uint2float32(registers[fs]); postoperation: | - fd = CAPI.FS.float322uint(fd); + registers[fd] = CAPI.FP.float322uint(result); definition: |- let result; if (fsValue >= 0) { @@ -3495,8 +3522,8 @@ instructions: if (CAPI.VALIDATION.isMisaligned(registers[base] + off, 'd')) { CAPI.VALIDATION.raise('The memory must be aligned'); } - CAPI.MEM.write(registers[base] + off, 4, BigInt(parts[0]), ft); - CAPI.MEM.write(registers[base] + off + 4n, 4, BigInt(parts[1])); + CAPI.MEM.write(registers[base] + off, 4, BigInt(parts[1]), ft); + CAPI.MEM.write(registers[base] + off + 4n, 4, BigInt(parts[0])); - name: sh template: Custom type: Memory access @@ -3570,7 +3597,7 @@ instructions: startbit: 5 stopbit: 0 value: "111111" - definition: rd = CAPI.FP.int2uint(registers[rt] << sa); + definition: registers[rd] = CAPI.FP.int2uint(registers[rt] << sa); - name: slt template: Custom type: Logic @@ -3805,9 +3832,9 @@ instructions: stopbit: 0 value: "000100" preoperation: | - fsValue = CAPI.FS.uint2float32(fs); + fsValue = CAPI.FP.uint2float32(registers[fs]); postoperation: | - registers[fd] = CAPI.FS.float322uint(result); + registers[fd] = CAPI.FP.float322uint(result); definition: |- let result; if (fsValue >= 0) { @@ -3854,7 +3881,7 @@ instructions: stopbit: 0 value: "000011" definition: | - registers[rd] = CAPI.FP.int2uint(registers[rt] >> sa); + registers[rd] = CAPI.FP.int2uint(CAPI.FP.uint2int(registers[rt]) >> sa); - name: srl template: Custom type: Arithmetic integer @@ -3899,7 +3926,7 @@ instructions: stopbit: 0 value: "000010" definition: | - registers[rd] = registers[rt] >>> sa; // TODO:broken with bigints. + registers[rd] = CAPI.FP.int2uint(registers[rt]) >> sa; - name: sub template: Custom type: Arithmetic integer @@ -4037,10 +4064,10 @@ instructions: stopbit: 0 value: "000001" preoperation: | - fsValue = CAPI.FS.uint2float32(fs); - ftValue = CAPI.FS.uint2float32(ft); + fsValue = CAPI.FP.uint2float32(registers[fs]); + ftValue = CAPI.FP.uint2float32(registers[ft]); postoperation: | - registers[fd] = CAPI.FS.float322uint(result); + registers[fd] = CAPI.FP.float322uint(result); definition: let result = fsValue - ftValue; - name: subu template: Custom @@ -4174,6 +4201,7 @@ instructions: value: "001100" definition: |- let FP0 = CAPI.ARCH.readDouble('f0'); + let f12 = CAPI.FP.uint2float32(registers.f12); let FP12 = CAPI.ARCH.readDouble('f12'); switch(registers["v0"]) { case 1n: @@ -4192,10 +4220,10 @@ instructions: CAPI.SYSCALL.read('v0', 'int32'); break; case 6n: - CAPI.SYSCALL.read(f0, 'float'); + CAPI.SYSCALL.read('f0', 'float'); break; case 7n: - CAPI.SYSCALL.read(FP0, 'double'); + CAPI.SYSCALL.read('FP0', 'double'); break; case 8n: CAPI.SYSCALL.read('a0', 'string', 'a1'); @@ -4999,18 +5027,24 @@ pseudoinstructions: - field: val type: imm-signed definition: |- - no_ret_op{tmp0=Field.2.(63,32).double; - tmp_low0=tmp0&0x0000FFFF; - tmp_hi0=tmp0>>>16; - tmp1=Field.2.(31,0).double; - tmp_low1=tmp1&0x0000FFFF; - tmp_hi1=tmp1>>>16}; + no_ret_op{ + tmp0=Field.2.(63,32).double; + tmp_low0=tmp0&0x0000FFFF; + tmp_hi0=tmp0>>>16; + tmp1=Field.2.(31,0).double; + tmp_low1=tmp1&0x0000FFFF; + tmp_hi1=tmp1>>>16; + tmp_reg=reg_name{1}; + regNumber=parseInt(tmp_reg.substring(2), 10); + reg0="f" + regNumber; + reg1="f" + (regNumber + 1); + }; lui $at, op{tmp_hi1}; ori $at, $at, op{tmp_low1}; - mtc1 $at, $aliasDouble(rd;1); + mtc1 $at, $op{reg1}; lui $at, op{tmp_hi0}; ori $at, $at, op{tmp_low0}; - mtc1 $at, $aliasDouble(rd;0); + mtc1 $at, $op{reg0}; - name: li.s help: "" properties: [] From f26bae4e72fc3c6fa75d2bfd708b7f59d952a073 Mon Sep 17 00:00:00 2001 From: ALVAROPING1 Date: Mon, 16 Mar 2026 15:17:05 +0100 Subject: [PATCH 24/85] tests(IO): allow tests to override IO keyboard input for non-interactive execution --- src/core/executor/IO.mjs | 42 ++++++++++++++++++++++++++-------------- 1 file changed, 27 insertions(+), 15 deletions(-) diff --git a/src/core/executor/IO.mjs b/src/core/executor/IO.mjs index 2ae7eb7b8..b314bd499 100644 --- a/src/core/executor/IO.mjs +++ b/src/core/executor/IO.mjs @@ -33,6 +33,13 @@ import { coreEvents, CoreEventTypes } from "../events.mts"; import { crex_findReg } from "../register/registerLookup.mjs"; import { Memory } from "../memory/Memory.mts"; +/** Keyboard data override. Intended exclusively for running interactive tests */ +export const testKeyboard = { + enable: false, + /** @type {string[]} */ + data: [], +} + export function display_print(info) { if (typeof document !== "undefined" && document.app) { document.app.$data.display += info; @@ -54,7 +61,7 @@ export function kbd_read_char(keystroke, params) { sailexec._send_char_to_C(value); document.app.$data.execution_mode_run = document.app.$data.last_execution_mode_run; - document.app.$data.last_execution_mode_run = -1; + document.app.$data.last_execution_mode_run = -1; } writeRegister(BigInt(value), params.indexComp, params.indexElem); @@ -84,7 +91,7 @@ export function kbd_read_int(keystroke, params) { sailexec._send_int_to_C(value); document.app.$data.execution_mode_run = document.app.$data.last_execution_mode_run; - document.app.$data.last_execution_mode_run = -1; + document.app.$data.last_execution_mode_run = -1; } value = BigInt(value); @@ -109,14 +116,14 @@ export function kbd_read_float(keystroke, params) { document.app.$data.execution_mode_run = document.app.$data.last_execution_mode_run; - document.app.$data.last_execution_mode_run = -1; + document.app.$data.last_execution_mode_run = -1; } const buffer = new ArrayBuffer(4); const view = new DataView(buffer); view.setFloat32(0,value, false); const bits = view.getUint32(0, false); - writeRegister(BigInt(("0x" + bits.toString(16).padStart(8, "0"))), params.indexComp, params.indexElem); + writeRegister(BigInt(bits), params.indexComp, params.indexElem); return value; } @@ -137,7 +144,7 @@ export function kbd_read_double(keystroke, params) { sailexec._send_double_to_C(value); document.app.$data.execution_mode_run = document.app.$data.last_execution_mode_run; - document.app.$data.last_execution_mode_run = -1; + document.app.$data.last_execution_mode_run = -1; } writeRegister(value, params.indexComp, params.indexElem, "DFP-Reg"); @@ -170,7 +177,7 @@ export function kbd_read_string(keystroke, params) { } document.app.$data.execution_mode_run = document.app.$data.last_execution_mode_run; - document.app.$data.last_execution_mode_run = -1; + document.app.$data.last_execution_mode_run = -1; } return keystroke; } @@ -192,6 +199,11 @@ function checkEnter(buf) { * @returns {string} - The user input without extra space or newline */ function rawPrompt() { + if (testKeyboard.enable) { + const data = testKeyboard.data.shift() || "" + process.stdout.write(data); // Echo the character + return data + } // Build input character by character until we hit Enter const chunks = []; const decoder = new TextDecoder(); @@ -247,7 +259,7 @@ export function keyboard_parseInt(fn_post_read, fn_post_params) { const addr = readRegister(ret1.indexComp, ret1.indexElem); // Get the memory instance const memory = main_memory; - + // Validate address is within memory bounds if (addr >= BigInt(memory.getSize())) { throw packExecute( @@ -278,10 +290,10 @@ export function keyboard_parseInt(fn_post_read, fn_post_params) { var regex = new RegExp("^\\s*(-?\\d+)"); } - - // Deno / CLI mode + + // Deno / CLI mode if (typeof Deno !== "undefined") { let keystroke = rawPrompt(); var match = regex.exec(keystroke); @@ -385,7 +397,7 @@ export function keyboard_read(fn_post_read, fn_post_params) { if (typeof Deno !== "undefined") { const keystroke = rawPrompt(); const value = fn_post_read(keystroke, fn_post_params); - status.keyboard = status.keyboard + " " + value; + status.keyboard += " " + value; status.run_program = 0; // Reset run_program status return null; @@ -485,9 +497,9 @@ export function keyboard_read_until(fn_post_read, fn_post_params, fn_post_until) if (idx !== -1) { keystroke = keystroke.slice(0, idx); } - + } - // console.log("Extracted keystroke until 'until':", `"${keystroke}"`); + // console.log("Extracted keystroke until 'until':", `"${keystroke}"`); const value = fn_post_read(keystroke, fn_post_params); status.keyboard = status.keyboard + " " + value; status.run_program = 0; // Reset run_program status @@ -590,7 +602,7 @@ export function keyboard_read_find(fn_post_read, fn_post_params,fn_post_length,f const addr = readRegister(ret1.indexComp, ret1.indexElem); // Get the memory instance const memory = main_memory; - + // Validate address is within memory bounds if (addr >= BigInt(memory.getSize())) { throw packExecute( @@ -662,10 +674,10 @@ export function keyboard_read_find(fn_post_read, fn_post_params,fn_post_length,f memoryAddr++; } - // console.log("Until string: ", until); + // console.log("Until string: ", until); } - // Deno / CLI mode + // Deno / CLI mode if (typeof Deno !== "undefined") { let keystroke = rawPrompt(); From 5ac6598624df8781ff6440468a904c0bd640abb4 Mon Sep 17 00:00:00 2001 From: ALVAROPING1 Date: Mon, 16 Mar 2026 15:45:18 +0100 Subject: [PATCH 25/85] tests: add architecture snapshot tests --- tests/arch/arch_utils.mts | 102 +++++++++++++++++++++++ tests/arch/mips/correct.test.mts | 24 ++++++ tests/arch/mips/instructions.test.mts | 5 ++ tests/arch/mips/sentinel.test.mts | 3 + tests/arch/riscv/correct.test.mts | 24 ++++++ tests/arch/riscv/instructions.test.mts | 3 + tests/arch/riscv/sentinel.test.mts | 3 + tests/unit/arch/simulator-test-utils.mts | 55 ++++++++---- 8 files changed, 204 insertions(+), 15 deletions(-) create mode 100644 tests/arch/arch_utils.mts create mode 100644 tests/arch/mips/correct.test.mts create mode 100644 tests/arch/mips/instructions.test.mts create mode 100644 tests/arch/mips/sentinel.test.mts create mode 100644 tests/arch/riscv/correct.test.mts create mode 100644 tests/arch/riscv/instructions.test.mts create mode 100644 tests/arch/riscv/sentinel.test.mts diff --git a/tests/arch/arch_utils.mts b/tests/arch/arch_utils.mts new file mode 100644 index 000000000..67e2464be --- /dev/null +++ b/tests/arch/arch_utils.mts @@ -0,0 +1,102 @@ +import { assertSnapshot } from "jsr:@std/testing/snapshot"; +import * as path from "jsr:@std/path"; +import fs from "node:fs"; +import { + executeStep, + loadArchitecture, + compileAssembly, +} from "../unit/arch/simulator-test-utils.mts"; +import { testKeyboard } from "../../src/core/executor/IO.mjs"; +import * as creator from "../../src/core/core.mjs"; +import { coreEvents } from "../../src/core/events.mts"; +import { logger } from "../../src/core/utils/creator_logger.mjs"; + +export const ARCH = { + riscv: "RISCV/RV32IMFD.yml", + riscv64: "RISCV/RV64IMFD.yml", + mips: "MIPS32.yml", + simple8: "simple8.yml", +}; + +const PREFIX = path.fromFileUrl(import.meta.url + "/../../../"); + +/** + * Executes a group of execution snapshot tests + * @param archPath - Path to the YAML architecture configuration file, from the architectures folder + * @param dir - Path to the directory with the assembly files + * @param keyboard - Map of test file name to its corresponding keyboard input. Unspecified files + * use an empty input + * @param expect_error - Set of test file names that are expected to throw errors during execution + */ +export function snapshot_tests( + archPath: string, + dir: string, + keyboard: Map = new Map(), + expect_error: Set = new Set(), +): void { + logger.disable(); + const ARCH_PATH = "architecture/" + archPath; + loadArchitecture(ARCH_PATH); + const DIR = `${PREFIX}tests/arch/${dir}`; + testKeyboard.enable = true; + for (const file of fs.globSync("*.s", { cwd: DIR })) { + Deno.test(`${dir}/${file}`, async t => { + const errors = expect_error.has(file); + // Record passing convention errors + const sentinel_errors: { function: string; msg: string }[] = []; + coreEvents.on("sentinel-error", e => + sentinel_errors.push({ + function: e.functionName, + msg: e.message, + }), + ); + + // Compile code + const path = `${DIR}/${file}`; + const testAssembly = fs.readFileSync(path, "utf8"); + await compileAssembly(testAssembly); + + // Setup keyboard input if specified + testKeyboard.data = keyboard.get(file) || []; + + // Execute code + let result = { output: "", error: false }; + const instruction_errors: {i: number, error: string}[] = []; + for (let i = 0; i < 1000; i++) { + try { + result = executeStep(); + if (result.error || creator.status.execution_index === -2) + break; + } catch (e) { + if (errors) + instruction_errors.push({i, error: (e as Error).message}); + else throw e; + } + } + + // Save state + const memory = creator.main_memory + .getWritten() + .map(d => [d.addr, d.value]) + .filter(x => x[1] !== 0); + + const registers = creator.REGISTERS.flatMap(r => r.elements) + .filter(r => r.value !== r.default_value) + .map(r => [r.name.join(","), "0x" + r.value.toString(16)]); + + const state = { + error: result.error === false ? false : result.output, + memory: Object.fromEntries(memory), + registers: Object.fromEntries(registers), + display: creator.status.display, + keyboard: creator.status.keyboard, + sentinel_errors, + ...(errors ? { instruction_errors } : {}), + }; + + await assertSnapshot(t, state, { + path: `${PREFIX}/tests/arch/__snapshots__/${dir}/${file}.snap`, + }); + }); + } +} diff --git a/tests/arch/mips/correct.test.mts b/tests/arch/mips/correct.test.mts new file mode 100644 index 000000000..dab94b20c --- /dev/null +++ b/tests/arch/mips/correct.test.mts @@ -0,0 +1,24 @@ +import { ARCH, snapshot_tests } from "../arch_utils.mts"; + +const long_str = + "This is a very long string with many characters and a lot of data. :) 123\n"; + +snapshot_tests( + ARCH.mips, + "mips/correct/examples", + new Map([ + ["test_mips_example_009.s", ["123\n", "456\n"]], + ["test_mips_example_010.s", [long_str.length + "\n", long_str]], + ]), +); +snapshot_tests( + ARCH.mips, + "mips/correct/syscalls", + new Map([ + ["test_mips_syscall_005.s", ["1234567\n"]], + ["test_mips_syscall_006.s", ["1.234567\n"]], + ["test_mips_syscall_007.s", ["1.234567890123456\n"]], + ["test_mips_syscall_008.s", ["This is a long string\n"]], + ["test_mips_syscall_012.s", ["a\n"]], + ]), +); diff --git a/tests/arch/mips/instructions.test.mts b/tests/arch/mips/instructions.test.mts new file mode 100644 index 000000000..fcf5b9933 --- /dev/null +++ b/tests/arch/mips/instructions.test.mts @@ -0,0 +1,5 @@ +import { ARCH, snapshot_tests } from "../arch_utils.mts" + +snapshot_tests(ARCH.mips, "mips/instructions", undefined, new Set([ + "test_mips_instruction_058.s", "test_mips_instruction_064.s" +])); diff --git a/tests/arch/mips/sentinel.test.mts b/tests/arch/mips/sentinel.test.mts new file mode 100644 index 000000000..542729330 --- /dev/null +++ b/tests/arch/mips/sentinel.test.mts @@ -0,0 +1,3 @@ +import { ARCH, snapshot_tests } from "../arch_utils.mts" + +snapshot_tests(ARCH.mips, "mips/sentinel"); diff --git a/tests/arch/riscv/correct.test.mts b/tests/arch/riscv/correct.test.mts new file mode 100644 index 000000000..d9d47b778 --- /dev/null +++ b/tests/arch/riscv/correct.test.mts @@ -0,0 +1,24 @@ +import { ARCH, snapshot_tests } from "../arch_utils.mts"; + +const long_str = + "This is a very long string with many characters and a lot of data. :) 123\n"; + +snapshot_tests( + ARCH.riscv, + "riscv/correct/examples", + new Map([ + ["test_riscv_example_009.s", ["123\n", "456\n"]], + ["test_riscv_example_010.s", [long_str.length + "\n", long_str]], + ]), +); +snapshot_tests( + ARCH.riscv, + "riscv/correct/syscalls", + new Map([ + ["test_riscv_syscall_005.s", ["1234567\n"]], + ["test_riscv_syscall_006.s", ["1.234567\n"]], + ["test_riscv_syscall_007.s", ["1.234567890123456\n"]], + ["test_riscv_syscall_008.s", ["This is a long string\n"]], + ["test_riscv_syscall_012.s", ["a\n"]], + ]), +); diff --git a/tests/arch/riscv/instructions.test.mts b/tests/arch/riscv/instructions.test.mts new file mode 100644 index 000000000..b8af0fe04 --- /dev/null +++ b/tests/arch/riscv/instructions.test.mts @@ -0,0 +1,3 @@ +import { ARCH, snapshot_tests } from "../arch_utils.mts" + +snapshot_tests(ARCH.riscv, "riscv/instructions"); diff --git a/tests/arch/riscv/sentinel.test.mts b/tests/arch/riscv/sentinel.test.mts new file mode 100644 index 000000000..3e145cc39 --- /dev/null +++ b/tests/arch/riscv/sentinel.test.mts @@ -0,0 +1,3 @@ +import { ARCH, snapshot_tests } from "../arch_utils.mts" + +snapshot_tests(ARCH.riscv, "riscv/sentinel"); diff --git a/tests/unit/arch/simulator-test-utils.mts b/tests/unit/arch/simulator-test-utils.mts index d80726f54..1dd960c0d 100644 --- a/tests/unit/arch/simulator-test-utils.mts +++ b/tests/unit/arch/simulator-test-utils.mts @@ -98,24 +98,13 @@ export function getByteAtAddress(address: bigint): bigint { } /** - * Setup function to initialize simulator state with architecture from YAML file - * @param testAssembly - Assembly code to compile and load + * Load an architecture from YAML file into the simulator * @param yamlPath - Path to the YAML architecture configuration file - * @returns Setup results including architecture and compilation status + * @returns Architecture loading result */ -export async function setupSimulator( - testAssembly: string, - yamlPath: string, - assembler: string = "default", -): Promise<{ - archResult: ArchResult; - compileResult: CompileResult; -}> { - logger.disable(); - +export function loadArchitecture(yamlPath: string|URL): ArchResult { // Load architecture configuration from file synchronously - const archPath = new URL(yamlPath, import.meta.url); - const architectureConfigContent = fs.readFileSync(archPath, "utf8"); + const architectureConfigContent = fs.readFileSync(yamlPath, "utf8"); // yaml.load returns unknown; narrow its type and validate at runtime const archObject = yaml.load(architectureConfigContent) as | { config?: { plugin?: string } } @@ -145,6 +134,19 @@ export async function setupSimulator( `Failed to load architecture from ${yamlPath}: ${archResult.token}`, ); } + return archResult; +} + +/** + * Setup function to initialize simulator state with architecture from YAML file + * @param testAssembly - Assembly code to compile and load + * @param assembler - Name of the assembler to use + * @returns Setup results including architecture and compilation status + */ +export async function compileAssembly( + testAssembly: string, + assembler: string = "default", +): Promise { const compilerKey = assembler || "default"; if (!isValidCompilerKey(compilerKey)) { @@ -153,6 +155,8 @@ export async function setupSimulator( ); } + creator.reset(); + const compilerFunction = compiler_map[compilerKey]; // Compile assembly code const compileResult = (await creator.assembly_compile( @@ -165,6 +169,27 @@ export async function setupSimulator( creator.reset(); + return compileResult; +} + +/** + * Setup function to initialize simulator state with architecture from YAML file + * @param testAssembly - Assembly code to compile and load + * @param yamlPath - Path to the YAML architecture configuration file + * @returns Setup results including architecture and compilation status + */ +export async function setupSimulator( + testAssembly: string, + yamlPath: string, + assembler: string = "default", +): Promise<{ + archResult: ArchResult; + compileResult: CompileResult; +}> { + logger.disable(); + const archPath = new URL(yamlPath, import.meta.url); + const archResult = loadArchitecture(archPath) + const compileResult = await compileAssembly(testAssembly, assembler) return { archResult, compileResult }; } From 5ac8da46f1786316c0848cc52168909b8b233c82 Mon Sep 17 00:00:00 2001 From: ALVAROPING1 Date: Mon, 16 Mar 2026 15:50:19 +0100 Subject: [PATCH 26/85] tests: initial migration of old snapshot tests results --- .../examples/test_mips_example_001.out | 5 +++ .../examples/test_mips_example_013.out | 41 +++++++++++++++++++ .../syscalls/test_mips_syscall_001.out | 2 +- .../compiler/test_mips_error_compiler_001.out | 18 +++++--- .../compiler/test_mips_error_compiler_002.out | 12 +++--- .../compiler/test_mips_error_compiler_003.out | 32 +++++++++++++-- .../compiler/test_mips_error_compiler_004.out | 14 ++++--- .../compiler/test_mips_error_compiler_005.out | 15 ++++--- .../compiler/test_mips_error_compiler_006.out | 25 ++++++++--- .../compiler/test_mips_error_compiler_007.out | 14 ++++--- .../compiler/test_mips_error_compiler_008.out | 14 ++++--- .../compiler/test_mips_error_compiler_009.out | 24 +++++++++-- .../compiler/test_mips_error_compiler_014.out | 12 +++--- .../compiler/test_mips_error_compiler_015.out | 13 +++--- .../compiler/test_mips_error_compiler_016.out | 15 ++++--- .../compiler/test_mips_error_compiler_017.out | 15 ++++--- .../compiler/test_mips_error_compiler_018.out | 15 ++++--- .../compiler/test_mips_error_compiler_019.out | 15 ++++--- .../compiler/test_mips_error_compiler_021.out | 13 +++--- .../compiler/test_mips_error_compiler_022.out | 13 +++--- .../compiler/test_mips_error_compiler_023.out | 14 ++++--- .../compiler/test_mips_error_compiler_030.out | 11 +++-- .../executor/test_mips_error_executor_009.out | 2 +- .../test_mips_instruction_022.out | 2 +- .../test_mips_instruction_023.out | 2 +- .../test_mips_instruction_027.out | 2 +- .../test_mips_instruction_028.out | 2 +- .../test_mips_instruction_033.out | 12 +++--- .../test_mips_instruction_037.out | 12 +++--- .../test_mips_instruction_066.out | 13 +++--- .../test_mips_instruction_067.out | 13 +++--- .../mips/sentinel/test_mips_sentinels_018.out | 10 +---- .../examples/test_riscv_example_001.out | 5 +++ .../examples/test_riscv_example_013.out | 41 +++++++++++++++++++ .../test_riscv_error_compiler_001.out | 18 +++++--- .../test_riscv_error_compiler_002.out | 12 +++--- .../test_riscv_error_compiler_003.out | 24 +++++++++-- .../test_riscv_error_compiler_004.out | 14 ++++--- .../test_riscv_error_compiler_005.out | 15 ++++--- .../test_riscv_error_compiler_006.out | 25 ++++++++--- .../test_riscv_error_compiler_007.out | 14 ++++--- .../test_riscv_error_compiler_008.out | 20 ++++++--- .../test_riscv_error_compiler_009.out | 24 +++++++++-- .../test_riscv_error_compiler_014.out | 12 +++--- .../test_riscv_error_compiler_015.out | 13 +++--- .../test_riscv_error_compiler_016.out | 15 ++++--- .../test_riscv_error_compiler_017.out | 15 ++++--- .../test_riscv_error_compiler_018.out | 15 ++++--- .../test_riscv_error_compiler_019.out | 15 ++++--- .../test_riscv_error_compiler_021.out | 13 +++--- .../test_riscv_error_compiler_022.out | 13 +++--- .../test_riscv_error_compiler_023.out | 14 ++++--- .../test_riscv_error_compiler_030.out | 11 +++-- .../test_riscv_instruction_004.out | 2 +- .../test_riscv_instruction_013.out | 3 ++ .../test_riscv_instruction_022.out | 2 +- .../test_riscv_instruction_035.out | 2 +- .../test_riscv_instruction_036.out | 2 +- .../test_riscv_instruction_037.out | 2 +- .../test_riscv_instruction_039.out | 2 +- .../test_riscv_instruction_040.out | 2 +- .../test_riscv_instruction_043.out | 2 +- .../test_riscv_instruction_045.out | 2 +- .../test_riscv_instruction_046.out | 2 +- .../test_riscv_instruction_047.out | 2 +- .../test_riscv_instruction_048.out | 2 +- .../test_riscv_instruction_049.out | 2 +- .../test_riscv_instruction_050.out | 2 +- .../test_riscv_instruction_051.out | 2 +- 69 files changed, 551 insertions(+), 252 deletions(-) create mode 100644 tests/arch/mips/correct/examples/test_mips_example_001.out create mode 100644 tests/arch/mips/correct/examples/test_mips_example_013.out create mode 100644 tests/arch/riscv/correct/examples/test_riscv_example_001.out create mode 100644 tests/arch/riscv/correct/examples/test_riscv_example_013.out create mode 100644 tests/arch/riscv/instructions/test_riscv_instruction_013.out diff --git a/tests/arch/mips/correct/examples/test_mips_example_001.out b/tests/arch/mips/correct/examples/test_mips_example_001.out new file mode 100644 index 000000000..b48eb7374 --- /dev/null +++ b/tests/arch/mips/correct/examples/test_mips_example_001.out @@ -0,0 +1,5 @@ + +12 +34 +cr[PC]:0xffffffff; ir[1,at]:0x200002; ir[2,v0]:0x1; ir[4,a0]:0x22; keyboard[0x0]:''; display[0x0]:'1234'; + diff --git a/tests/arch/mips/correct/examples/test_mips_example_013.out b/tests/arch/mips/correct/examples/test_mips_example_013.out new file mode 100644 index 000000000..97dfc5ec5 --- /dev/null +++ b/tests/arch/mips/correct/examples/test_mips_example_013.out @@ -0,0 +1,41 @@ + +83 +116 +114 +105 +110 +103 +32 +105 +110 +32 +85 +84 +70 +45 +56 +58 +32 +-30 +-120 +-128 +32 +-30 +-120 +-85 +32 +-30 +-120 +-121 +32 +-30 +-120 +-120 +32 +-16 +-97 +-96 +-84 +0 +cr[PC]:0x20; ir[1,at]:0x200000; ir[2,v0]:0x1; ir[8,t0]:0x200026; keyboard[0x0]:''; display[0x0]:'83116114105110103321051103285847045565832-30-120-12832-30-120-8532-30-120-12132-30-120-12032-16-97-96-840'; + diff --git a/tests/arch/mips/correct/syscalls/test_mips_syscall_001.out b/tests/arch/mips/correct/syscalls/test_mips_syscall_001.out index 1192ad0e9..601697ff4 100644 --- a/tests/arch/mips/correct/syscalls/test_mips_syscall_001.out +++ b/tests/arch/mips/correct/syscalls/test_mips_syscall_001.out @@ -6,5 +6,5 @@ -5678 1 1416128883 -cr[PC]:0x74; ir[1,at]:0x200008; ir[2,v0]:0x1; ir[4,a0]:0x54686973; ir[8,t0]:0x4; ir[9,t1]:0x200000; keyboard[0x0]:''; display[0x0]:'6673120134-567811416128883'; +cr[PC]:0x6c; ir[1,at]:0x200008; ir[2,v0]:0x1; ir[4,a0]:0x54686973; ir[8,t0]:0x4; ir[9,t1]:0x200000; keyboard[0x0]:''; display[0x0]:'6673120134-567811416128883'; diff --git a/tests/arch/mips/error/compiler/test_mips_error_compiler_001.out b/tests/arch/mips/error/compiler/test_mips_error_compiler_001.out index d8f77e300..5c7476c32 100644 --- a/tests/arch/mips/error/compiler/test_mips_error_compiler_001.out +++ b/tests/arch/mips/error/compiler/test_mips_error_compiler_001.out @@ -1,10 +1,18 @@ -Error at line 9 (A): -Repeated tag: A - - 8 a: .byte -1 -->9 A: .half 23 +[E12] Error: Label `A` is already defined + ╭─[ assembly:9:4 ] + │ + 7 │ A: .word -1 + │ ─┬ + │ ╰── Note: Label also defined here + │ + 9 │ A: .half 23 + │ ─┬ + │ ╰── Duplicate label + │ + │ Help: Consider renaming either of the labels +───╯ Not executed keyboard[0x0]:''; display[0x0]:''; diff --git a/tests/arch/mips/error/compiler/test_mips_error_compiler_002.out b/tests/arch/mips/error/compiler/test_mips_error_compiler_002.out index 18b3b2fc0..10ce10d62 100644 --- a/tests/arch/mips/error/compiler/test_mips_error_compiler_002.out +++ b/tests/arch/mips/error/compiler/test_mips_error_compiler_002.out @@ -1,10 +1,12 @@ -Error at line 12 (suma): -Instruction 'suma' not found - - 11 main: -->12 suma $t0, $t1, $t2 +[E02] Error: Instruction `suma` isn't defined + ╭─[ assembly:12:4 ] + │ + 12 │ suma $t0, $t1, $t2 + │ ──┬─ + │ ╰─── Unknown instruction +────╯ Not executed keyboard[0x0]:''; display[0x0]:''; diff --git a/tests/arch/mips/error/compiler/test_mips_error_compiler_003.out b/tests/arch/mips/error/compiler/test_mips_error_compiler_003.out index cbf7e3143..d2bf39ee3 100644 --- a/tests/arch/mips/error/compiler/test_mips_error_compiler_003.out +++ b/tests/arch/mips/error/compiler/test_mips_error_compiler_003.out @@ -1,10 +1,34 @@ -Error at line 12 (add $reg3 $reg2 $reg1): -Incorrect instruction syntax for 'add $reg3 $reg2 $reg1' +[E09] Error: Incorrect instruction syntax + ╭─[ assembly:12:8 ] + │ + 12 │ add 25, $t1, 12 + │ ─────┬───── + │ ╰─────── Incorrect syntax + │ + │ Note: Allowed formats: + │ add $reg3,$reg2,$reg1 + │ add $rs,$rt,inm +────╯ - 11 main: -->12 add 25, $t1, 12 +The syntax `add $reg3,$reg2,$reg1` failed with the following reason: +Error: found `integer (25)` but expected `$` + ╭─[ assembly:12:8 ] + │ + 12 │ add 25, $t1, 12 + │ ─┬ + │ ╰── Unexpected input +────╯ + +The syntax `add $rs,$rt,inm` failed with the following reason: +Error: found `integer (25)` but expected `$` + ╭─[ assembly:12:8 ] + │ + 12 │ add 25, $t1, 12 + │ ─┬ + │ ╰── Unexpected input +────╯ Not executed keyboard[0x0]:''; display[0x0]:''; diff --git a/tests/arch/mips/error/compiler/test_mips_error_compiler_004.out b/tests/arch/mips/error/compiler/test_mips_error_compiler_004.out index 639433294..682367df3 100644 --- a/tests/arch/mips/error/compiler/test_mips_error_compiler_004.out +++ b/tests/arch/mips/error/compiler/test_mips_error_compiler_004.out @@ -1,10 +1,14 @@ -Error at line 12 (s50): -Register 's50' not found - - 11 main: -->12 add $t0, $t1, $s50 +[E05] Error: Register `s50` isn't defined in file type `Integer` + ╭─[ assembly:12:19 ] + │ + 12 │ add $t0, $t1, $s50 + │ ─┬─ + │ ╰─── Unknown register + │ + │ Help: Did you mean `s0` or `s5`? +────╯ Not executed keyboard[0x0]:''; display[0x0]:''; diff --git a/tests/arch/mips/error/compiler/test_mips_error_compiler_005.out b/tests/arch/mips/error/compiler/test_mips_error_compiler_005.out index 8a51b1caa..5c0fd2a61 100644 --- a/tests/arch/mips/error/compiler/test_mips_error_compiler_005.out +++ b/tests/arch/mips/error/compiler/test_mips_error_compiler_005.out @@ -1,11 +1,14 @@ -Error at line 7 (0x123): -Number '0x123' is too big - - 6 .data -->7 a: .byte 0x123 - 8 +[E23] Error: Value `291` is outside of the valid range of the field + ╭─[ assembly:7:19 ] + │ + 7 │ a: .byte 0x123 + │ ──┬── + │ ╰──── This expression has value `291` + │ + │ Note: Allowed range is [-128, 255] +───╯ Not executed keyboard[0x0]:''; display[0x0]:''; diff --git a/tests/arch/mips/error/compiler/test_mips_error_compiler_006.out b/tests/arch/mips/error/compiler/test_mips_error_compiler_006.out index 8a51b1caa..a77e8dcd5 100644 --- a/tests/arch/mips/error/compiler/test_mips_error_compiler_006.out +++ b/tests/arch/mips/error/compiler/test_mips_error_compiler_006.out @@ -1,11 +1,26 @@ -Error at line 7 (0x123): -Number '0x123' is too big +[E09] Error: Incorrect instruction syntax + ╭─[ assembly:11:7 ] + │ + 11 │ li $t0, 0xhello + │ ──────┬───── + │ ╰─────── Incorrect syntax + │ + │ Note: Allowed formats: + │ li $rd,val +────╯ - 6 .data -->7 a: .byte 0x123 - 8 +The syntax `li $rd,val` failed with the following reason: +Error: found `identifier (xhello)` but expected `\n`, `binary operator`, or `end of input` + ╭─[ assembly:11:13 ] + │ + 11 │ li $t0, 0xhello + │ ┬───┬── + │ ╰──────── While parsing this `expression` + │ │ + │ ╰──── Unexpected input +────╯ Not executed keyboard[0x0]:''; display[0x0]:''; diff --git a/tests/arch/mips/error/compiler/test_mips_error_compiler_007.out b/tests/arch/mips/error/compiler/test_mips_error_compiler_007.out index d181ef242..c966e8c00 100644 --- a/tests/arch/mips/error/compiler/test_mips_error_compiler_007.out +++ b/tests/arch/mips/error/compiler/test_mips_error_compiler_007.out @@ -1,10 +1,14 @@ -Error at line 11 (mains): -Tag 'mains' is not valid - - 10 li $t0, 10 -->11 j mains +[E03] Error: Label `mains` isn't defined + ╭─[ assembly:11:7 ] + │ + 11 │ j mains + │ ──┬── + │ ╰──── Unknown label + │ + │ Help: Did you mean `main`? +────╯ Not executed keyboard[0x0]:''; display[0x0]:''; diff --git a/tests/arch/mips/error/compiler/test_mips_error_compiler_008.out b/tests/arch/mips/error/compiler/test_mips_error_compiler_008.out index 1a1fa1532..eb758f055 100644 --- a/tests/arch/mips/error/compiler/test_mips_error_compiler_008.out +++ b/tests/arch/mips/error/compiler/test_mips_error_compiler_008.out @@ -1,10 +1,14 @@ -Error at line 8: -Please check instruction syntax, inmediate ranges, register name, etc. - - 7 main: -->8 j 0x12345678 +[E23] Error: Value `305419896` is outside of the valid range of the field + ╭─[ assembly:8:6 ] + │ + 8 │ j 0x12345678 + │ ─────┬──── + │ ╰────── This expression has value `305419896` + │ + │ Note: Allowed range is [-33554432, 33554431] +───╯ Not executed keyboard[0x0]:''; display[0x0]:''; diff --git a/tests/arch/mips/error/compiler/test_mips_error_compiler_009.out b/tests/arch/mips/error/compiler/test_mips_error_compiler_009.out index b902b990c..dc58ec9fa 100644 --- a/tests/arch/mips/error/compiler/test_mips_error_compiler_009.out +++ b/tests/arch/mips/error/compiler/test_mips_error_compiler_009.out @@ -1,10 +1,26 @@ -Error at line 8 (0xhello): -Immediate number '0xhello' is not valid +[E09] Error: Incorrect instruction syntax + ╭─[ assembly:8:6 ] + │ + 8 │ j 0xhello + │ ───┬─── + │ ╰───── Incorrect syntax + │ + │ Note: Allowed formats: + │ j addr +───╯ - 7 main: -->8 j 0xhello +The syntax `j addr` failed with the following reason: +Error: found `identifier (xhello)` but expected `\n`, `binary operator`, or `end of input` + ╭─[ assembly:8:7 ] + │ + 8 │ j 0xhello + │ ┬───┬── + │ ╰──────── While parsing this `expression` + │ │ + │ ╰──── Unexpected input +───╯ Not executed keyboard[0x0]:''; display[0x0]:''; diff --git a/tests/arch/mips/error/compiler/test_mips_error_compiler_014.out b/tests/arch/mips/error/compiler/test_mips_error_compiler_014.out index a4744db4d..81e4462e8 100644 --- a/tests/arch/mips/error/compiler/test_mips_error_compiler_014.out +++ b/tests/arch/mips/error/compiler/test_mips_error_compiler_014.out @@ -1,10 +1,12 @@ -Error at line 8 (.directive): -Invalid directive: .directive - - 7 .align 2 -->8 example: .directive 221 +[E01] Error: Directive `.directive` isn't defined + ╭─[ assembly:8:14 ] + │ + 8 │ example: .directive 221 + │ ─────┬──── + │ ╰────── Unknown directive +───╯ Not executed keyboard[0x0]:''; display[0x0]:''; diff --git a/tests/arch/mips/error/compiler/test_mips_error_compiler_015.out b/tests/arch/mips/error/compiler/test_mips_error_compiler_015.out index 691cbf761..0c8632ae4 100644 --- a/tests/arch/mips/error/compiler/test_mips_error_compiler_015.out +++ b/tests/arch/mips/error/compiler/test_mips_error_compiler_015.out @@ -1,11 +1,12 @@ -Error at line 8 (hello): -Invalid value 'hello' as number. - - 7 .align 2 -->8 example: .word hello - 9 +[E03] Error: Label `hello` isn't defined + ╭─[ assembly:8:22 ] + │ + 8 │ example: .word hello + │ ──┬── + │ ╰──── Unknown label +───╯ Not executed keyboard[0x0]:''; display[0x0]:''; diff --git a/tests/arch/mips/error/compiler/test_mips_error_compiler_016.out b/tests/arch/mips/error/compiler/test_mips_error_compiler_016.out index 16bbdbcf2..ea7274441 100644 --- a/tests/arch/mips/error/compiler/test_mips_error_compiler_016.out +++ b/tests/arch/mips/error/compiler/test_mips_error_compiler_016.out @@ -1,11 +1,14 @@ -Error at line 8: -The string of characters must start with " - - 7 .align 2 -->8 example: .ascii hello world" - 9 +Error: Unterminated string literal + ╭─[ assembly:8:32 ] + │ + 8 │ example: .ascii hello world" + │ ───┬─┬ + │ ╰──── While parsing this `identifier` + │ │ + │ ╰── Caused by this +───╯ Not executed keyboard[0x0]:''; display[0x0]:''; diff --git a/tests/arch/mips/error/compiler/test_mips_error_compiler_017.out b/tests/arch/mips/error/compiler/test_mips_error_compiler_017.out index 252b00265..543ea4f4a 100644 --- a/tests/arch/mips/error/compiler/test_mips_error_compiler_017.out +++ b/tests/arch/mips/error/compiler/test_mips_error_compiler_017.out @@ -1,11 +1,14 @@ -Error at line 8: -The string of characters must end with " - - 7 .align 2 -->8 example: .ascii "hello world - 9 +Error: Unterminated string literal + ╭─[ assembly:8:33 ] + │ + 8 │ example: .ascii "hello world + │ ──────┬─────┬ + │ ╰──────── While parsing this `string` + │ │ + │ ╰── Caused by this +───╯ Not executed keyboard[0x0]:''; display[0x0]:''; diff --git a/tests/arch/mips/error/compiler/test_mips_error_compiler_018.out b/tests/arch/mips/error/compiler/test_mips_error_compiler_018.out index 89c84b0f2..da5e6eec9 100644 --- a/tests/arch/mips/error/compiler/test_mips_error_compiler_018.out +++ b/tests/arch/mips/error/compiler/test_mips_error_compiler_018.out @@ -1,11 +1,14 @@ -Error at line 7 (0x12345): -Number '0x12345' is too big - - 6 .data -->7 example: .half 0x12345 - 8 +[E23] Error: Value `74565` is outside of the valid range of the field + ╭─[ assembly:7:20 ] + │ + 7 │ example: .half 0x12345 + │ ───┬─── + │ ╰───── This expression has value `74565` + │ + │ Note: Allowed range is [-32768, 65535] +───╯ Not executed keyboard[0x0]:''; display[0x0]:''; diff --git a/tests/arch/mips/error/compiler/test_mips_error_compiler_019.out b/tests/arch/mips/error/compiler/test_mips_error_compiler_019.out index d1dc21973..61d170cee 100644 --- a/tests/arch/mips/error/compiler/test_mips_error_compiler_019.out +++ b/tests/arch/mips/error/compiler/test_mips_error_compiler_019.out @@ -1,11 +1,14 @@ -Error at line 7 (0x): -Number '0x' is empty - - 6 .data -->7 .byte 0x - 8 +Error: found `identifier (x)` but expected `,`, `\n`, `binary operator`, or `end of input` + ╭─[ assembly:7:12 ] + │ + 7 │ .byte 0x + │ ┬┬ + │ ╰─── While parsing this `expression` + │ │ + │ ╰── Unexpected input +───╯ Not executed keyboard[0x0]:''; display[0x0]:''; diff --git a/tests/arch/mips/error/compiler/test_mips_error_compiler_021.out b/tests/arch/mips/error/compiler/test_mips_error_compiler_021.out index 35a2ef06c..0fae5b507 100644 --- a/tests/arch/mips/error/compiler/test_mips_error_compiler_021.out +++ b/tests/arch/mips/error/compiler/test_mips_error_compiler_021.out @@ -1,11 +1,12 @@ -Error at line 9: -The data must be aligned - - 8 example: .byte 23 -->9 example2: .half 2 - 10 string: .asciiz "hello" +[E17] Error: Data at address `0x200001` isn't aligned to size `2` nor word size `4` + ╭─[ assembly:9:21 ] + │ + 9 │ example2: .half 2 + │ ┬ + │ ╰── This value isn't aligned +───╯ Not executed keyboard[0x0]:''; display[0x0]:''; diff --git a/tests/arch/mips/error/compiler/test_mips_error_compiler_022.out b/tests/arch/mips/error/compiler/test_mips_error_compiler_022.out index 780eee03b..f4c45383c 100644 --- a/tests/arch/mips/error/compiler/test_mips_error_compiler_022.out +++ b/tests/arch/mips/error/compiler/test_mips_error_compiler_022.out @@ -1,11 +1,12 @@ -Error at line 7 (-10): -The space directive value should be positive and greater than zero - - 6 .data -->7 .space -10 - 8 +[E22] Error: Negative values aren't allowed here + ╭─[ assembly:7:12 ] + │ + 7 │ .space -10 + │ ─┬─ + │ ╰─── This expression has value `-10` +───╯ Not executed keyboard[0x0]:''; display[0x0]:''; diff --git a/tests/arch/mips/error/compiler/test_mips_error_compiler_023.out b/tests/arch/mips/error/compiler/test_mips_error_compiler_023.out index a99e652c7..deb0a1708 100644 --- a/tests/arch/mips/error/compiler/test_mips_error_compiler_023.out +++ b/tests/arch/mips/error/compiler/test_mips_error_compiler_023.out @@ -1,10 +1,14 @@ -Error at line 10: -Empty directive - - 9 example2: .half -->10 +[E10] Error: Incorrect amount of arguments, expected at least `1` but found `0` + ╭─[ assembly:9:20 ] + │ + 9 │ example2: .half + │ │ + │ ╰─ This directive has `0` arguments + │ + │ Help: Consider adding the missing `1` argument +───╯ Not executed keyboard[0x0]:''; display[0x0]:''; diff --git a/tests/arch/mips/error/compiler/test_mips_error_compiler_030.out b/tests/arch/mips/error/compiler/test_mips_error_compiler_030.out index e7ae53a33..a02fc0290 100644 --- a/tests/arch/mips/error/compiler/test_mips_error_compiler_030.out +++ b/tests/arch/mips/error/compiler/test_mips_error_compiler_030.out @@ -1,9 +1,12 @@ -Error at line 1 (Please enter the assembly code before compiling): -Please enter the assembly code before compiling - -->1 +[E13] Error: Main label `main` not found + ╭─[ assembly:8:15 ] + │ + 8 │ li $t0, 10 + │ │ + │ ╰─ Consider adding a label called `main` to an instruction +───╯ Not executed keyboard[0x0]:''; display[0x0]:''; diff --git a/tests/arch/mips/error/executor/test_mips_error_executor_009.out b/tests/arch/mips/error/executor/test_mips_error_executor_009.out index 8be2fd58a..4250e5e73 100644 --- a/tests/arch/mips/error/executor/test_mips_error_executor_009.out +++ b/tests/arch/mips/error/executor/test_mips_error_executor_009.out @@ -1,6 +1,6 @@ Error found. - The register 0 | zero is not writeable + The register 0 | zero cannot be written cr[PC]:0x4; keyboard[0x0]:''; display[0x0]:''; diff --git a/tests/arch/mips/instructions/test_mips_instruction_022.out b/tests/arch/mips/instructions/test_mips_instruction_022.out index f99b8375d..688c96a0a 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_022.out +++ b/tests/arch/mips/instructions/test_mips_instruction_022.out @@ -1,3 +1,3 @@ -cr[PC]:0x20; ir[1,at]:0xffffdaf2; ir[8,t0]:0xaad4; ir[9,t1]:0x11d7; ir[10,t2]:0xffffdaf2; ir[11,t3]:0x2ab5; ir[12,t4]:0x7000011d; ir[13,t5]:0xb5e5ffff; keyboard[0x0]:''; display[0x0]:''; +cr[PC]:0x28; ir[1,at]:0xffffdaf2; ir[8,t0]:0xaad4; ir[9,t1]:0x11d7; ir[10,t2]:0xffffdaf2; ir[11,t3]:0x2ab5; ir[12,t4]:0x7000011d; ir[13,t5]:0xb5e5ffff; keyboard[0x0]:''; display[0x0]:''; diff --git a/tests/arch/mips/instructions/test_mips_instruction_023.out b/tests/arch/mips/instructions/test_mips_instruction_023.out index 17e3993e1..206f0d6eb 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_023.out +++ b/tests/arch/mips/instructions/test_mips_instruction_023.out @@ -1,3 +1,3 @@ -cr[PC]:0x20; ir[1,at]:0xffffdaf2; ir[8,t0]:0xaad4; ir[9,t1]:0x11d7; ir[10,t2]:0xffffdaf2; ir[11,t3]:0x2ab50; ir[12,t4]:0x11d70; ir[13,t5]:0xed790000; keyboard[0x0]:''; display[0x0]:''; +cr[PC]:0x28; ir[1,at]:0xffffdaf2; ir[8,t0]:0xaad4; ir[9,t1]:0x11d7; ir[10,t2]:0xffffdaf2; ir[11,t3]:0x2ab50; ir[12,t4]:0x11d70; ir[13,t5]:0xed790000; keyboard[0x0]:''; display[0x0]:''; diff --git a/tests/arch/mips/instructions/test_mips_instruction_027.out b/tests/arch/mips/instructions/test_mips_instruction_027.out index 82a1d683e..103850674 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_027.out +++ b/tests/arch/mips/instructions/test_mips_instruction_027.out @@ -1,3 +1,3 @@ -cr[PC]:0x20; ir[1,at]:0xffffdaf2; ir[8,t0]:0xaad4; ir[9,t1]:0x11d7; ir[10,t2]:0xffffdaf2; ir[11,t3]:0x2ab5; ir[12,t4]:0x11d; ir[13,t5]:0x1ffff; keyboard[0x0]:''; display[0x0]:''; +cr[PC]:0x28; ir[1,at]:0xffffdaf2; ir[8,t0]:0xaad4; ir[9,t1]:0x11d7; ir[10,t2]:0xffffdaf2; ir[11,t3]:0x2ab5; ir[12,t4]:0x11d; ir[13,t5]:0x1ffff; keyboard[0x0]:''; display[0x0]:''; diff --git a/tests/arch/mips/instructions/test_mips_instruction_028.out b/tests/arch/mips/instructions/test_mips_instruction_028.out index 4a38129f0..96e538869 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_028.out +++ b/tests/arch/mips/instructions/test_mips_instruction_028.out @@ -1,3 +1,3 @@ -cr[PC]:0x20; ir[1,at]:0xffffdaf2; ir[8,t0]:0xaad4; ir[9,t1]:0x11d7; ir[10,t2]:0xffffdaf2; ir[11,t3]:0x2ab5; ir[12,t4]:0x11d; ir[13,t5]:0xffffffff; keyboard[0x0]:''; display[0x0]:''; +cr[PC]:0x28; ir[1,at]:0xffffdaf2; ir[8,t0]:0xaad4; ir[9,t1]:0x11d7; ir[10,t2]:0xffffdaf2; ir[11,t3]:0x2ab5; ir[12,t4]:0x11d; ir[13,t5]:0xffffffff; keyboard[0x0]:''; display[0x0]:''; diff --git a/tests/arch/mips/instructions/test_mips_instruction_033.out b/tests/arch/mips/instructions/test_mips_instruction_033.out index 18e6769ae..c870908e4 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_033.out +++ b/tests/arch/mips/instructions/test_mips_instruction_033.out @@ -1,10 +1,12 @@ -Error at line 16 (Please enter the assembly code before compiling): -Please enter the assembly code before compiling - - 15 # srli x10, x7, 15 -->16 +[E13] Error: Main label `main` not found + ╭─[ assembly:1:1 ] + │ + 1 │ + │ │ + │ ╰─ Consider adding a label called `main` to an instruction +───╯ Not executed keyboard[0x0]:''; display[0x0]:''; diff --git a/tests/arch/mips/instructions/test_mips_instruction_037.out b/tests/arch/mips/instructions/test_mips_instruction_037.out index ba5eddb6d..c870908e4 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_037.out +++ b/tests/arch/mips/instructions/test_mips_instruction_037.out @@ -1,10 +1,12 @@ -Error at line 19 (Please enter the assembly code before compiling): -Please enter the assembly code before compiling - - 18 # mulhu x12, x8, x5 -->19 +[E13] Error: Main label `main` not found + ╭─[ assembly:1:1 ] + │ + 1 │ + │ │ + │ ╰─ Consider adding a label called `main` to an instruction +───╯ Not executed keyboard[0x0]:''; display[0x0]:''; diff --git a/tests/arch/mips/instructions/test_mips_instruction_066.out b/tests/arch/mips/instructions/test_mips_instruction_066.out index a7f2fc49f..aa4e53991 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_066.out +++ b/tests/arch/mips/instructions/test_mips_instruction_066.out @@ -1,11 +1,12 @@ -Error at line 15 (t0): -Register 't0' not found - - 14 -->15 cvt.w.d $t0, $FP0 - 16 cvt.w.d $t1, $FP2 +[E05] Error: Register `t0` isn't defined in file type `DoubleFloatingPoint` + ╭─[ assembly:15:14 ] + │ + 15 │ cvt.w.d $t0, $FP0 + │ ─┬ + │ ╰── Unknown register +────╯ Not executed keyboard[0x0]:''; display[0x0]:''; diff --git a/tests/arch/mips/instructions/test_mips_instruction_067.out b/tests/arch/mips/instructions/test_mips_instruction_067.out index 9bfd1f418..6b18c9b6f 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_067.out +++ b/tests/arch/mips/instructions/test_mips_instruction_067.out @@ -1,11 +1,12 @@ -Error at line 17 (t0): -Register 't0' not found - - 16 -->17 cvt.d.w $FP0, $t0 - 18 cvt.d.w $FP2, $t1 +[E05] Error: Register `t0` isn't defined in file type `DoubleFloatingPoint` + ╭─[ assembly:17:20 ] + │ + 17 │ cvt.d.w $FP0, $t0 + │ ─┬ + │ ╰── Unknown register +────╯ Not executed keyboard[0x0]:''; display[0x0]:''; diff --git a/tests/arch/mips/sentinel/test_mips_sentinels_018.out b/tests/arch/mips/sentinel/test_mips_sentinels_018.out index 5142e9336..d4255a064 100644 --- a/tests/arch/mips/sentinel/test_mips_sentinels_018.out +++ b/tests/arch/mips/sentinel/test_mips_sentinels_018.out @@ -1,11 +1,3 @@ - -Error at line 29 (addi $reg2 $reg1 val): -Incorrect instruction syntax for 'addi $reg2 $reg1 val' - - 28 undefined -->29 undefined - -Not executed -keyboard[0x0]:''; display[0x0]:''; +cr[PC]:0x10; ir[2,v0]:0xa; ir[29,sp]:0x9; ir[31,ra]:0x8; keyboard[0x0]:''; display[0x0]:''; diff --git a/tests/arch/riscv/correct/examples/test_riscv_example_001.out b/tests/arch/riscv/correct/examples/test_riscv_example_001.out new file mode 100644 index 000000000..b813595e7 --- /dev/null +++ b/tests/arch/riscv/correct/examples/test_riscv_example_001.out @@ -0,0 +1,5 @@ + +12 +34 +cr[PC]:0xfffffffe; ir[x10,a0]:0x22; ir[x17,a7]:0x1; keyboard[0x0]:''; display[0x0]:'1234'; + diff --git a/tests/arch/riscv/correct/examples/test_riscv_example_013.out b/tests/arch/riscv/correct/examples/test_riscv_example_013.out new file mode 100644 index 000000000..fa87a5452 --- /dev/null +++ b/tests/arch/riscv/correct/examples/test_riscv_example_013.out @@ -0,0 +1,41 @@ + +83 +116 +114 +105 +110 +103 +32 +105 +110 +32 +85 +84 +70 +45 +56 +58 +32 +-30 +-120 +-128 +32 +-30 +-120 +-85 +32 +-30 +-120 +-121 +32 +-30 +-120 +-120 +32 +-16 +-97 +-96 +-84 +0 +cr[PC]:0x1c; ir[x5,t0]:0x200026; ir[x17,a7]:0x1; keyboard[0x0]:''; display[0x0]:'83116114105110103321051103285847045565832-30-120-12832-30-120-8532-30-120-12132-30-120-12032-16-97-96-840'; + diff --git a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_001.out b/tests/arch/riscv/error/compiler/test_riscv_error_compiler_001.out index 8155de365..5131c282f 100644 --- a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_001.out +++ b/tests/arch/riscv/error/compiler/test_riscv_error_compiler_001.out @@ -1,10 +1,18 @@ -Error at line 9 (A): -Repeated tag: A - - 8 a: .byte -1 -->9 A: .half 23 +[E12] Error: Label `A` is already defined + ╭─[ assembly:9:2 ] + │ + 7 │ A: .word -1 + │ ─┬ + │ ╰─────── Note: Label also defined here + │ + 9 │ A: .half 23 + │ ─┬ + │ ╰───── Duplicate label + │ + │ Help: Consider renaming either of the labels +───╯ Not executed keyboard[0x0]:''; display[0x0]:''; diff --git a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_002.out b/tests/arch/riscv/error/compiler/test_riscv_error_compiler_002.out index 3c2aa4610..fad0e52c0 100644 --- a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_002.out +++ b/tests/arch/riscv/error/compiler/test_riscv_error_compiler_002.out @@ -1,10 +1,12 @@ -Error at line 12 (suma): -Instruction 'suma' not found - - 11 main: -->12 suma t0, t1, t2 +[E02] Error: Instruction `suma` isn't defined + ╭─[ assembly:12:2 ] + │ + 12 │ suma t0, t1, t2 + │ ──┬─ + │ ╰─── Unknown instruction +────╯ Not executed keyboard[0x0]:''; display[0x0]:''; diff --git a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_003.out b/tests/arch/riscv/error/compiler/test_riscv_error_compiler_003.out index 5a0b754b2..c14b5930e 100644 --- a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_003.out +++ b/tests/arch/riscv/error/compiler/test_riscv_error_compiler_003.out @@ -1,10 +1,26 @@ -Error at line 12 (add rd rs1 rs2): -Incorrect instruction syntax for 'add rd rs1 rs2' +[E09] Error: Incorrect instruction syntax + ╭─[ assembly:12:8 ] + │ + 12 │ add t0, t1 + │ ───┬── + │ ╰──── Incorrect syntax + │ + │ Note: Allowed formats: + │ add rd,rs1,rs2 +────╯ - 11 main: -->12 add t0, t1 +The syntax `add rd,rs1,rs2` failed with the following reason: +Error: found `end of input` but expected `,`, `\n`, or `binary operator` + ╭─[ assembly:12:14 ] + │ + 12 │ add t0, t1 + │ ─┬│ + │ ╰── While parsing this `expression` + │ │ + │ ╰─ Unexpected input +────╯ Not executed keyboard[0x0]:''; display[0x0]:''; diff --git a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_004.out b/tests/arch/riscv/error/compiler/test_riscv_error_compiler_004.out index 9b2d1dc38..b942b63b9 100644 --- a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_004.out +++ b/tests/arch/riscv/error/compiler/test_riscv_error_compiler_004.out @@ -1,10 +1,14 @@ -Error at line 12 (s50): -Register 's50' not found - - 11 main: -->12 add t0, t1, s50 +[E05] Error: Register `s50` isn't defined in file type `Integer` + ╭─[ assembly:12:14 ] + │ + 12 │ add t0, t1, s50 + │ ─┬─ + │ ╰─── Unknown register + │ + │ Help: Did you mean `s0`, `s10`, or `s5`? +────╯ Not executed keyboard[0x0]:''; display[0x0]:''; diff --git a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_005.out b/tests/arch/riscv/error/compiler/test_riscv_error_compiler_005.out index 8a51b1caa..5c0fd2a61 100644 --- a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_005.out +++ b/tests/arch/riscv/error/compiler/test_riscv_error_compiler_005.out @@ -1,11 +1,14 @@ -Error at line 7 (0x123): -Number '0x123' is too big - - 6 .data -->7 a: .byte 0x123 - 8 +[E23] Error: Value `291` is outside of the valid range of the field + ╭─[ assembly:7:19 ] + │ + 7 │ a: .byte 0x123 + │ ──┬── + │ ╰──── This expression has value `291` + │ + │ Note: Allowed range is [-128, 255] +───╯ Not executed keyboard[0x0]:''; display[0x0]:''; diff --git a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_006.out b/tests/arch/riscv/error/compiler/test_riscv_error_compiler_006.out index 8a51b1caa..38fa6dacb 100644 --- a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_006.out +++ b/tests/arch/riscv/error/compiler/test_riscv_error_compiler_006.out @@ -1,11 +1,26 @@ -Error at line 7 (0x123): -Number '0x123' is too big +[E09] Error: Incorrect instruction syntax + ╭─[ assembly:11:7 ] + │ + 11 │ li t0, 0xhello + │ ─────┬───── + │ ╰─────── Incorrect syntax + │ + │ Note: Allowed formats: + │ li rd,val +────╯ - 6 .data -->7 a: .byte 0x123 - 8 +The syntax `li rd,val` failed with the following reason: +Error: found `identifier (xhello)` but expected `\n`, `binary operator`, or `end of input` + ╭─[ assembly:11:12 ] + │ + 11 │ li t0, 0xhello + │ ┬───┬── + │ ╰──────── While parsing this `expression` + │ │ + │ ╰──── Unexpected input +────╯ Not executed keyboard[0x0]:''; display[0x0]:''; diff --git a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_007.out b/tests/arch/riscv/error/compiler/test_riscv_error_compiler_007.out index 77e040699..c966e8c00 100644 --- a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_007.out +++ b/tests/arch/riscv/error/compiler/test_riscv_error_compiler_007.out @@ -1,10 +1,14 @@ -Error at line 11 (mains): -Tag 'mains' is not valid - - 10 li t0, 10 -->11 j mains +[E03] Error: Label `mains` isn't defined + ╭─[ assembly:11:7 ] + │ + 11 │ j mains + │ ──┬── + │ ╰──── Unknown label + │ + │ Help: Did you mean `main`? +────╯ Not executed keyboard[0x0]:''; display[0x0]:''; diff --git a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_008.out b/tests/arch/riscv/error/compiler/test_riscv_error_compiler_008.out index 1a1fa1532..a310e0504 100644 --- a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_008.out +++ b/tests/arch/riscv/error/compiler/test_riscv_error_compiler_008.out @@ -1,10 +1,20 @@ -Error at line 8: -Please check instruction syntax, inmediate ranges, register name, etc. - - 7 main: -->8 j 0x12345678 +[E23] Error: Value `305419896` is outside of the valid range of the field + ╭─[ :1:17 ] + │ + 1 │ beq zero, zero, off; + │ ─┬─ + │ ╰─── This expression has value `305419896` + │ + ├─[ assembly:8:4 ] + │ + 8 │ j 0x12345678 + │ ──────┬───── + │ ╰─────── Generated by this pseudoinstruction + │ + │ Note: Allowed range is [-4096, 4095] +───╯ Not executed keyboard[0x0]:''; display[0x0]:''; diff --git a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_009.out b/tests/arch/riscv/error/compiler/test_riscv_error_compiler_009.out index 338606755..e000c91dc 100644 --- a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_009.out +++ b/tests/arch/riscv/error/compiler/test_riscv_error_compiler_009.out @@ -1,10 +1,26 @@ -Error at line 8: -Please check instruction syntax, inmediate ranges, register name, etc. +[E09] Error: Incorrect instruction syntax + ╭─[ assembly:8:6 ] + │ + 8 │ j 0xhello + │ ───┬─── + │ ╰───── Incorrect syntax + │ + │ Note: Allowed formats: + │ j off +───╯ - 7 main: -->8 j 0xhello +The syntax `j off` failed with the following reason: +Error: found `identifier (xhello)` but expected `\n`, `binary operator`, or `end of input` + ╭─[ assembly:8:7 ] + │ + 8 │ j 0xhello + │ ┬───┬── + │ ╰──────── While parsing this `expression` + │ │ + │ ╰──── Unexpected input +───╯ Not executed keyboard[0x0]:''; display[0x0]:''; diff --git a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_014.out b/tests/arch/riscv/error/compiler/test_riscv_error_compiler_014.out index a4744db4d..81e4462e8 100644 --- a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_014.out +++ b/tests/arch/riscv/error/compiler/test_riscv_error_compiler_014.out @@ -1,10 +1,12 @@ -Error at line 8 (.directive): -Invalid directive: .directive - - 7 .align 2 -->8 example: .directive 221 +[E01] Error: Directive `.directive` isn't defined + ╭─[ assembly:8:14 ] + │ + 8 │ example: .directive 221 + │ ─────┬──── + │ ╰────── Unknown directive +───╯ Not executed keyboard[0x0]:''; display[0x0]:''; diff --git a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_015.out b/tests/arch/riscv/error/compiler/test_riscv_error_compiler_015.out index 691cbf761..0c8632ae4 100644 --- a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_015.out +++ b/tests/arch/riscv/error/compiler/test_riscv_error_compiler_015.out @@ -1,11 +1,12 @@ -Error at line 8 (hello): -Invalid value 'hello' as number. - - 7 .align 2 -->8 example: .word hello - 9 +[E03] Error: Label `hello` isn't defined + ╭─[ assembly:8:22 ] + │ + 8 │ example: .word hello + │ ──┬── + │ ╰──── Unknown label +───╯ Not executed keyboard[0x0]:''; display[0x0]:''; diff --git a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_016.out b/tests/arch/riscv/error/compiler/test_riscv_error_compiler_016.out index d56d429ca..daa5fb858 100644 --- a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_016.out +++ b/tests/arch/riscv/error/compiler/test_riscv_error_compiler_016.out @@ -1,11 +1,14 @@ -Error at line 8: -The string of characters must start with " - - 7 .align 2 -->8 example: .string hello world" - 9 +Error: Unterminated string literal + ╭─[ assembly:8:33 ] + │ + 8 │ example: .string hello world" + │ ───┬─┬ + │ ╰──── While parsing this `identifier` + │ │ + │ ╰── Caused by this +───╯ Not executed keyboard[0x0]:''; display[0x0]:''; diff --git a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_017.out b/tests/arch/riscv/error/compiler/test_riscv_error_compiler_017.out index 81a724a14..ade735b68 100644 --- a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_017.out +++ b/tests/arch/riscv/error/compiler/test_riscv_error_compiler_017.out @@ -1,11 +1,14 @@ -Error at line 8: -The string of characters must end with " - - 7 .align 2 -->8 example: .string "hello world - 9 +Error: Unterminated string literal + ╭─[ assembly:8:34 ] + │ + 8 │ example: .string "hello world + │ ──────┬─────┬ + │ ╰──────── While parsing this `string` + │ │ + │ ╰── Caused by this +───╯ Not executed keyboard[0x0]:''; display[0x0]:''; diff --git a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_018.out b/tests/arch/riscv/error/compiler/test_riscv_error_compiler_018.out index 89c84b0f2..da5e6eec9 100644 --- a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_018.out +++ b/tests/arch/riscv/error/compiler/test_riscv_error_compiler_018.out @@ -1,11 +1,14 @@ -Error at line 7 (0x12345): -Number '0x12345' is too big - - 6 .data -->7 example: .half 0x12345 - 8 +[E23] Error: Value `74565` is outside of the valid range of the field + ╭─[ assembly:7:20 ] + │ + 7 │ example: .half 0x12345 + │ ───┬─── + │ ╰───── This expression has value `74565` + │ + │ Note: Allowed range is [-32768, 65535] +───╯ Not executed keyboard[0x0]:''; display[0x0]:''; diff --git a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_019.out b/tests/arch/riscv/error/compiler/test_riscv_error_compiler_019.out index d1dc21973..61d170cee 100644 --- a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_019.out +++ b/tests/arch/riscv/error/compiler/test_riscv_error_compiler_019.out @@ -1,11 +1,14 @@ -Error at line 7 (0x): -Number '0x' is empty - - 6 .data -->7 .byte 0x - 8 +Error: found `identifier (x)` but expected `,`, `\n`, `binary operator`, or `end of input` + ╭─[ assembly:7:12 ] + │ + 7 │ .byte 0x + │ ┬┬ + │ ╰─── While parsing this `expression` + │ │ + │ ╰── Unexpected input +───╯ Not executed keyboard[0x0]:''; display[0x0]:''; diff --git a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_021.out b/tests/arch/riscv/error/compiler/test_riscv_error_compiler_021.out index 90b6f30f3..0fae5b507 100644 --- a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_021.out +++ b/tests/arch/riscv/error/compiler/test_riscv_error_compiler_021.out @@ -1,11 +1,12 @@ -Error at line 9: -The data must be aligned - - 8 example: .byte 23 -->9 example2: .half 2 - 10 string: .string "hello" +[E17] Error: Data at address `0x200001` isn't aligned to size `2` nor word size `4` + ╭─[ assembly:9:21 ] + │ + 9 │ example2: .half 2 + │ ┬ + │ ╰── This value isn't aligned +───╯ Not executed keyboard[0x0]:''; display[0x0]:''; diff --git a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_022.out b/tests/arch/riscv/error/compiler/test_riscv_error_compiler_022.out index df7b1e2b4..e9a31f9c7 100644 --- a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_022.out +++ b/tests/arch/riscv/error/compiler/test_riscv_error_compiler_022.out @@ -1,11 +1,12 @@ -Error at line 7 (-10): -The space directive value should be positive and greater than zero - - 6 .data -->7 .zero -10 - 8 +[E22] Error: Negative values aren't allowed here + ╭─[ assembly:7:11 ] + │ + 7 │ .zero -10 + │ ─┬─ + │ ╰─── This expression has value `-10` +───╯ Not executed keyboard[0x0]:''; display[0x0]:''; diff --git a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_023.out b/tests/arch/riscv/error/compiler/test_riscv_error_compiler_023.out index a99e652c7..deb0a1708 100644 --- a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_023.out +++ b/tests/arch/riscv/error/compiler/test_riscv_error_compiler_023.out @@ -1,10 +1,14 @@ -Error at line 10: -Empty directive - - 9 example2: .half -->10 +[E10] Error: Incorrect amount of arguments, expected at least `1` but found `0` + ╭─[ assembly:9:20 ] + │ + 9 │ example2: .half + │ │ + │ ╰─ This directive has `0` arguments + │ + │ Help: Consider adding the missing `1` argument +───╯ Not executed keyboard[0x0]:''; display[0x0]:''; diff --git a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_030.out b/tests/arch/riscv/error/compiler/test_riscv_error_compiler_030.out index e7ae53a33..660623da0 100644 --- a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_030.out +++ b/tests/arch/riscv/error/compiler/test_riscv_error_compiler_030.out @@ -1,9 +1,12 @@ -Error at line 1 (Please enter the assembly code before compiling): -Please enter the assembly code before compiling - -->1 +[E13] Error: Main label `main` not found + ╭─[ assembly:8:14 ] + │ + 8 │ li t0, 10 + │ │ + │ ╰─ Consider adding a label called `main` to an instruction +───╯ Not executed keyboard[0x0]:''; display[0x0]:''; diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_004.out b/tests/arch/riscv/instructions/test_riscv_instruction_004.out index 3804ee956..d36f27819 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_004.out +++ b/tests/arch/riscv/instructions/test_riscv_instruction_004.out @@ -1,3 +1,3 @@ -cr[PC]:0x14; ir[x5,t0]:0x23000; ir[x6,t1]:0x56db000; ir[x7,t2]:0x34000; ir[x8,fp,s0]:0xff002000; ir[x9,s1]:0x2000; keyboard[0x0]:''; display[0x0]:''; +cr[PC]:0x14; ir[x5,t0]:0x23000; ir[x6,t1]:0x56db000; ir[x7,t2]:0x34000; ir[x8,fp,s0]:0x7f002000; ir[x9,s1]:0x2000; keyboard[0x0]:''; display[0x0]:''; diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_013.out b/tests/arch/riscv/instructions/test_riscv_instruction_013.out new file mode 100644 index 000000000..5d7a09fa8 --- /dev/null +++ b/tests/arch/riscv/instructions/test_riscv_instruction_013.out @@ -0,0 +1,3 @@ + +cr[PC]:0x48; ir[x5,t0]:0x200000; ir[x6,t1]:0x200004; ir[x7,t2]:0x200006; ir[x8,fp,s0]:0xe; ir[x10,a0]:0x7f; ir[x12,a2]:0x7fff; ir[x14,a4]:0x20000e; memory[0x20000f]:0xff; memory[0x20000e]:0x7f; memory[0x20000c]:0x7f; memory[0x20000b]:0x0e; keyboard[0x0]:''; display[0x0]:''; + diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_022.out b/tests/arch/riscv/instructions/test_riscv_instruction_022.out index 4061495a9..f08cdef68 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_022.out +++ b/tests/arch/riscv/instructions/test_riscv_instruction_022.out @@ -1,3 +1,3 @@ -cr[PC]:0x24; ir[x5,t0]:0xaad4; ir[x6,t1]:0x11d7; ir[x7,t2]:0xffffdaf2; ir[x8,fp,s0]:0x2ab5; ir[x9,s1]:0x11d; ir[x10,a0]:0x1ffff; keyboard[0x0]:''; display[0x0]:''; +cr[PC]:0x24; ir[x5,t0]:0xaad4; ir[x6,t1]:0x11d7; ir[x7,t2]:0xffffdaf2; ir[x8,fp,s0]:0x2ab5; ir[x9,s1]:0x11d; ir[x10,a0]:0xffffffff; keyboard[0x0]:''; display[0x0]:''; diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_035.out b/tests/arch/riscv/instructions/test_riscv_instruction_035.out index f44fa7a68..11914d179 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_035.out +++ b/tests/arch/riscv/instructions/test_riscv_instruction_035.out @@ -1,3 +1,3 @@ -cr[PC]:0x20; ir[x5,t0]:0xa; ir[x6,t1]:0xd; ir[x7,t2]:0x2d; ir[x8,fp,s0]:0xfffffffe; ir[x11,a1]:0xffffffff; ir[x12,a2]:0xffffffff; keyboard[0x0]:''; display[0x0]:''; +cr[PC]:0x20; ir[x5,t0]:0xa; ir[x6,t1]:0xd; ir[x7,t2]:0x2d; ir[x8,fp,s0]:0xfffffffe; ir[x9,s1]:0x82; ir[x10,a0]:0x249; ir[x11,a1]:0xffffffa6; ir[x12,a2]:0xffffffec; keyboard[0x0]:''; display[0x0]:''; diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_036.out b/tests/arch/riscv/instructions/test_riscv_instruction_036.out index ea927e21c..11914d179 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_036.out +++ b/tests/arch/riscv/instructions/test_riscv_instruction_036.out @@ -1,3 +1,3 @@ -cr[PC]:0x20; ir[x5,t0]:0xa; ir[x6,t1]:0xd; ir[x7,t2]:0x2d; ir[x8,fp,s0]:0xfffffffe; ir[x11,a1]:0x2c; ir[x12,a2]:0xffffffff; keyboard[0x0]:''; display[0x0]:''; +cr[PC]:0x20; ir[x5,t0]:0xa; ir[x6,t1]:0xd; ir[x7,t2]:0x2d; ir[x8,fp,s0]:0xfffffffe; ir[x9,s1]:0x82; ir[x10,a0]:0x249; ir[x11,a1]:0xffffffa6; ir[x12,a2]:0xffffffec; keyboard[0x0]:''; display[0x0]:''; diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_037.out b/tests/arch/riscv/instructions/test_riscv_instruction_037.out index 28c4473a5..11914d179 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_037.out +++ b/tests/arch/riscv/instructions/test_riscv_instruction_037.out @@ -1,3 +1,3 @@ -cr[PC]:0x20; ir[x5,t0]:0xa; ir[x6,t1]:0xd; ir[x7,t2]:0x2d; ir[x8,fp,s0]:0xfffffffe; ir[x11,a1]:0x2c; ir[x12,a2]:0x9; keyboard[0x0]:''; display[0x0]:''; +cr[PC]:0x20; ir[x5,t0]:0xa; ir[x6,t1]:0xd; ir[x7,t2]:0x2d; ir[x8,fp,s0]:0xfffffffe; ir[x9,s1]:0x82; ir[x10,a0]:0x249; ir[x11,a1]:0xffffffa6; ir[x12,a2]:0xffffffec; keyboard[0x0]:''; display[0x0]:''; diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_039.out b/tests/arch/riscv/instructions/test_riscv_instruction_039.out index f7fe5caf1..8308a6c53 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_039.out +++ b/tests/arch/riscv/instructions/test_riscv_instruction_039.out @@ -1,3 +1,3 @@ -cr[PC]:0x24; ir[x5,t0]:0x10; ir[x6,t1]:0x100; ir[x7,t2]:0xffffe000; ir[x8,fp,s0]:0x18; ir[x9,s1]:0xffffe00; ir[x10,a0]:0x10; ir[x11,a1]:0xaaaa955; keyboard[0x0]:''; display[0x0]:''; +cr[PC]:0x24; ir[x5,t0]:0x10; ir[x6,t1]:0x100; ir[x7,t2]:0xffffe000; ir[x8,fp,s0]:0x18; ir[x9,s1]:0xffffe00; ir[x10,a0]:0x10; ir[x11,a1]:0xaaaa955; ir[x12,a2]:0x5; keyboard[0x0]:''; display[0x0]:''; diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_040.out b/tests/arch/riscv/instructions/test_riscv_instruction_040.out index 2faa31cb3..a6c4184e4 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_040.out +++ b/tests/arch/riscv/instructions/test_riscv_instruction_040.out @@ -1,3 +1,3 @@ -cr[pc]:0x24; ir[x5,t0]:0x10; ir[x6,t1]:0x100; ir[x7,t2]:0xffffe000; ir[x8,fp,s0]:0x18; ir[x11,a1]:0x8; ir[x12,a2]:0x18; keyboard[0x0]:''; display[0x0]:''; +cr[PC]:0x24; ir[x5,t0]:0x10; ir[x6,t1]:0x100; ir[x7,t2]:0xffffe000; ir[x8,fp,s0]:0x18; ir[x11,a1]:0x8; ir[x12,a2]:0x18; keyboard[0x0]:''; display[0x0]:''; diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_043.out b/tests/arch/riscv/instructions/test_riscv_instruction_043.out index b1e9bb09b..d540a9815 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_043.out +++ b/tests/arch/riscv/instructions/test_riscv_instruction_043.out @@ -1,3 +1,3 @@ -cr[pc]:0x24; ir[x5,t0]:0xb; ir[x6,t1]:0x22b; ir[x7,t2]:0x5; ir[x8,fp,s0]:0x21f; ir[x17,a7]:0xa; ir[x28,t3]:0x22; keyboard[0x0]:''; display[0x0]:''; +cr[PC]:0x24; ir[x5,t0]:0xb; ir[x6,t1]:0x22b; ir[x7,t2]:0x5; ir[x8,fp,s0]:0x21f; ir[x17,a7]:0xa; ir[x28,t3]:0x22; keyboard[0x0]:''; display[0x0]:''; diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_045.out b/tests/arch/riscv/instructions/test_riscv_instruction_045.out index 5f5ed833a..4b5977236 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_045.out +++ b/tests/arch/riscv/instructions/test_riscv_instruction_045.out @@ -1,3 +1,3 @@ -cr[pc]:0x24; ir[x5,t0]:0xb; ir[x6,t1]:0xfffffdd5; ir[x7,t2]:0x5; ir[x8,fp,s0]:0xfffffde1; ir[x17,a7]:0xa; ir[x28,t3]:0x22; keyboard[0x0]:''; display[0x0]:''; +cr[PC]:0x24; ir[x5,t0]:0xb; ir[x6,t1]:0xfffffdd5; ir[x7,t2]:0x5; ir[x8,fp,s0]:0xfffffde1; ir[x17,a7]:0xa; ir[x28,t3]:0x22; keyboard[0x0]:''; display[0x0]:''; diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_046.out b/tests/arch/riscv/instructions/test_riscv_instruction_046.out index 3764481ae..5c8366988 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_046.out +++ b/tests/arch/riscv/instructions/test_riscv_instruction_046.out @@ -1,3 +1,3 @@ -cr[pc]:0x24; ir[x5,t0]:0x22346; ir[x6,t1]:0x11d7; ir[x7,t2]:0xffffdaf2; ir[x8,fp,s0]:0xfffddcb9; ir[x9,s1]:0xffffee28; ir[x10,a0]:0x250d; keyboard[0x0]:''; display[0x0]:''; +cr[PC]:0x24; ir[x5,t0]:0x22346; ir[x6,t1]:0x11d7; ir[x7,t2]:0xffffdaf2; ir[x8,fp,s0]:0xfffddcb9; ir[x9,s1]:0xffffee28; ir[x10,a0]:0x250d; keyboard[0x0]:''; display[0x0]:''; diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_047.out b/tests/arch/riscv/instructions/test_riscv_instruction_047.out index a33577387..e899ec914 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_047.out +++ b/tests/arch/riscv/instructions/test_riscv_instruction_047.out @@ -1,3 +1,3 @@ -cr[pc]:0x24; ir[x5,t0]:0x22346; ir[x6,t1]:0x11d7; ir[x7,t2]:0xffffdaf2; ir[x8,fp,s0]:0xfffddcba; ir[x9,s1]:0xffffee29; ir[x10,a0]:0x250e; keyboard[0x0]:''; display[0x0]:''; +cr[PC]:0x24; ir[x5,t0]:0x22346; ir[x6,t1]:0x11d7; ir[x7,t2]:0xffffdaf2; ir[x8,fp,s0]:0xfffddcba; ir[x9,s1]:0xffffee29; ir[x10,a0]:0x250e; keyboard[0x0]:''; display[0x0]:''; diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_048.out b/tests/arch/riscv/instructions/test_riscv_instruction_048.out index fb4cb4600..79919eac7 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_048.out +++ b/tests/arch/riscv/instructions/test_riscv_instruction_048.out @@ -1,3 +1,3 @@ -cr[pc]:0x18; ir[x4,tp]:0x1; ir[x6,t1]:0xffffffff; ir[x9,s1]:0x1; keyboard[0x0]:''; display[0x0]:''; +cr[PC]:0x18; ir[x4,tp]:0x1; ir[x6,t1]:0xffffffff; ir[x9,s1]:0x1; keyboard[0x0]:''; display[0x0]:''; diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_049.out b/tests/arch/riscv/instructions/test_riscv_instruction_049.out index 3e9ef139c..468629a21 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_049.out +++ b/tests/arch/riscv/instructions/test_riscv_instruction_049.out @@ -1,3 +1,3 @@ -cr[pc]:0x18; ir[x4,tp]:0x1; ir[x6,t1]:0xffffffff; ir[x8,fp,s0]:0x1; ir[x10,a0]:0x1; keyboard[0x0]:''; display[0x0]:''; +cr[PC]:0x18; ir[x4,tp]:0x1; ir[x6,t1]:0xffffffff; ir[x8,fp,s0]:0x1; ir[x10,a0]:0x1; keyboard[0x0]:''; display[0x0]:''; diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_050.out b/tests/arch/riscv/instructions/test_riscv_instruction_050.out index 6a6e64bc5..3fe384ae6 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_050.out +++ b/tests/arch/riscv/instructions/test_riscv_instruction_050.out @@ -1,3 +1,3 @@ -cr[pc]:0x18; ir[x4,tp]:0x1; ir[x6,t1]:0xffffffff; ir[x8,fp,s0]:0x1; keyboard[0x0]:''; display[0x0]:''; +cr[PC]:0x18; ir[x4,tp]:0x1; ir[x6,t1]:0xffffffff; ir[x8,fp,s0]:0x1; keyboard[0x0]:''; display[0x0]:''; diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_051.out b/tests/arch/riscv/instructions/test_riscv_instruction_051.out index e4b537b15..e2fa0a4f7 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_051.out +++ b/tests/arch/riscv/instructions/test_riscv_instruction_051.out @@ -1,3 +1,3 @@ -cr[pc]:0x18; ir[x4,tp]:0x1; ir[x6,t1]:0xffffffff; ir[x10,a0]:0x1; keyboard[0x0]:''; display[0x0]:''; +cr[PC]:0x18; ir[x4,tp]:0x1; ir[x6,t1]:0xffffffff; ir[x10,a0]:0x1; keyboard[0x0]:''; display[0x0]:''; From c5e26e1530606d726f79112ec15dc91bc97d7ef5 Mon Sep 17 00:00:00 2001 From: ALVAROPING1 Date: Mon, 16 Mar 2026 15:50:45 +0100 Subject: [PATCH 27/85] tests: migration of old snapshot tests --- deno.lock | 35 +++ .../examples/test_mips_example_001.s.snap | 106 +++++++++ .../examples/test_mips_example_002.s.snap | 54 +++++ .../examples/test_mips_example_003.s.snap | 113 +++++++++ .../examples/test_mips_example_004.s.snap | 145 ++++++++++++ .../examples/test_mips_example_005.s.snap | 56 +++++ .../examples/test_mips_example_006.s.snap | 58 +++++ .../examples/test_mips_example_007.s.snap | 78 ++++++ .../examples/test_mips_example_008.s.snap | 171 ++++++++++++++ .../examples/test_mips_example_009.s.snap | 169 +++++++++++++ .../examples/test_mips_example_010.s.snap | 221 +++++++++++++++++ .../examples/test_mips_example_011.s.snap | 85 +++++++ .../examples/test_mips_example_012.s.snap | 119 ++++++++++ .../examples/test_mips_example_013.s.snap | 79 +++++++ .../syscalls/test_mips_syscall_001.s.snap | 114 +++++++++ .../syscalls/test_mips_syscall_002.s.snap | 59 +++++ .../syscalls/test_mips_syscall_003.s.snap | 89 +++++++ .../syscalls/test_mips_syscall_004.s.snap | 87 +++++++ .../syscalls/test_mips_syscall_005.s.snap | 23 ++ .../syscalls/test_mips_syscall_006.s.snap | 24 ++ .../syscalls/test_mips_syscall_008.s.snap | 43 ++++ .../syscalls/test_mips_syscall_010.s.snap | 27 +++ .../syscalls/test_mips_syscall_011.s.snap | 27 +++ .../syscalls/test_mips_syscall_012.s.snap | 23 ++ .../test_mips_instruction_001.s.snap | 56 +++++ .../test_mips_instruction_002.s.snap | 36 +++ .../test_mips_instruction_003.s.snap | 66 ++++++ .../test_mips_instruction_004.s.snap | 40 ++++ .../test_mips_instruction_005.s.snap | 68 ++++++ .../test_mips_instruction_006.s.snap | 73 ++++++ .../test_mips_instruction_007.s.snap | 71 ++++++ .../test_mips_instruction_008.s.snap | 72 ++++++ .../test_mips_instruction_009.s.snap | 80 +++++++ .../test_mips_instruction_010.s.snap | 80 +++++++ .../test_mips_instruction_011.s.snap | 81 +++++++ .../test_mips_instruction_012.s.snap | 80 +++++++ .../test_mips_instruction_013.s.snap | 125 ++++++++++ .../test_mips_instruction_014.s.snap | 71 ++++++ .../test_mips_instruction_015.s.snap | 70 ++++++ .../test_mips_instruction_016.s.snap | 70 ++++++ .../test_mips_instruction_017.s.snap | 62 +++++ .../test_mips_instruction_018.s.snap | 62 +++++ .../test_mips_instruction_019.s.snap | 62 +++++ .../test_mips_instruction_020.s.snap | 55 +++++ .../test_mips_instruction_021.s.snap | 55 +++++ .../test_mips_instruction_022.s.snap | 58 +++++ .../test_mips_instruction_023.s.snap | 58 +++++ .../test_mips_instruction_024.s.snap | 55 +++++ .../test_mips_instruction_025.s.snap | 55 +++++ .../test_mips_instruction_026.s.snap | 77 ++++++ .../test_mips_instruction_027.s.snap | 58 +++++ .../test_mips_instruction_028.s.snap | 58 +++++ .../test_mips_instruction_029.s.snap | 77 ++++++ .../test_mips_instruction_030.s.snap | 77 ++++++ .../test_mips_instruction_031.s.snap | 122 ++++++++++ .../test_mips_instruction_032.s.snap | 71 ++++++ .../test_mips_instruction_034.s.snap | 63 +++++ .../test_mips_instruction_035.s.snap | 78 ++++++ .../test_mips_instruction_036.s.snap | 71 ++++++ .../test_mips_instruction_037.s.snap | 71 ++++++ .../test_mips_instruction_038.s.snap | 61 +++++ .../test_mips_instruction_039.s.snap | 61 +++++ .../test_mips_instruction_040.s.snap | 65 +++++ .../test_mips_instruction_041.s.snap | 60 +++++ .../test_mips_instruction_042.s.snap | 75 ++++++ .../test_mips_instruction_043.s.snap | 89 +++++++ .../test_mips_instruction_044.s.snap | 74 ++++++ .../test_mips_instruction_045.s.snap | 102 ++++++++ .../test_mips_instruction_046.s.snap | 62 +++++ .../test_mips_instruction_047.s.snap | 47 ++++ .../test_mips_instruction_048.s.snap | 60 +++++ .../test_mips_instruction_049.s.snap | 55 +++++ .../test_mips_instruction_050.s.snap | 66 ++++++ .../test_mips_instruction_051.s.snap | 52 ++++ .../test_mips_instruction_052.s.snap | 44 ++++ .../test_mips_instruction_053.s.snap | 45 ++++ .../test_mips_instruction_054.s.snap | 43 ++++ .../test_mips_instruction_055.s.snap | 52 ++++ .../test_mips_instruction_056.s.snap | 71 ++++++ .../test_mips_instruction_057.s.snap | 65 +++++ .../test_mips_instruction_058.s.snap | 140 +++++++++++ .../test_mips_instruction_059.s.snap | 133 +++++++++++ .../test_mips_instruction_060.s.snap | 135 +++++++++++ .../test_mips_instruction_061.s.snap | 132 +++++++++++ .../test_mips_instruction_062.s.snap | 130 ++++++++++ .../test_mips_instruction_063.s.snap | 132 +++++++++++ .../test_mips_instruction_064.s.snap | 141 +++++++++++ .../test_mips_instruction_065.s.snap | 112 +++++++++ .../test_mips_instruction_066.s.snap | 95 ++++++++ .../test_mips_instruction_067.s.snap | 109 +++++++++ .../sentinel/test_mips_sentinels_001.s.snap | 60 +++++ .../sentinel/test_mips_sentinels_002.s.snap | 60 +++++ .../sentinel/test_mips_sentinels_003.s.snap | 60 +++++ .../sentinel/test_mips_sentinels_004.s.snap | 60 +++++ .../sentinel/test_mips_sentinels_005.s.snap | 33 +++ .../sentinel/test_mips_sentinels_006.s.snap | 33 +++ .../sentinel/test_mips_sentinels_007.s.snap | 33 +++ .../sentinel/test_mips_sentinels_008.s.snap | 33 +++ .../sentinel/test_mips_sentinels_009.s.snap | 32 +++ .../sentinel/test_mips_sentinels_010.s.snap | 67 ++++++ .../sentinel/test_mips_sentinels_011.s.snap | 67 ++++++ .../sentinel/test_mips_sentinels_012.s.snap | 67 ++++++ .../sentinel/test_mips_sentinels_013.s.snap | 67 ++++++ .../sentinel/test_mips_sentinels_014.s.snap | 67 ++++++ .../sentinel/test_mips_sentinels_015.s.snap | 67 ++++++ .../sentinel/test_mips_sentinels_016.s.snap | 67 ++++++ .../sentinel/test_mips_sentinels_017.s.snap | 67 ++++++ .../sentinel/test_mips_sentinels_018.s.snap | 39 +++ .../sentinel/test_mips_sentinels_019.s.snap | 64 +++++ .../sentinel/test_mips_sentinels_020.s.snap | 64 +++++ .../sentinel/test_mips_sentinels_021.s.snap | 64 +++++ .../sentinel/test_mips_sentinels_022.s.snap | 64 +++++ .../sentinel/test_mips_sentinels_023.s.snap | 64 +++++ .../sentinel/test_mips_sentinels_024.s.snap | 64 +++++ .../sentinel/test_mips_sentinels_025.s.snap | 64 +++++ .../sentinel/test_mips_sentinels_026.s.snap | 64 +++++ .../sentinel/test_mips_sentinels_027.s.snap | 64 +++++ .../sentinel/test_mips_sentinels_028.s.snap | 64 +++++ .../sentinel/test_mips_sentinels_029.s.snap | 59 +++++ .../sentinel/test_mips_sentinels_030.s.snap | 60 +++++ .../sentinel/test_mips_sentinels_031.s.snap | 49 ++++ .../sentinel/test_mips_sentinels_032.s.snap | 53 +++++ .../sentinel/test_mips_sentinels_033.s.snap | 56 +++++ .../sentinel/test_mips_sentinels_034.s.snap | 55 +++++ .../sentinel/test_mips_sentinels_035.s.snap | 55 +++++ .../examples/test_riscv_example_001.s.snap | 124 ++++++++++ .../examples/test_riscv_example_002.s.snap | 61 +++++ .../examples/test_riscv_example_003.s.snap | 92 ++++++++ .../examples/test_riscv_example_004.s.snap | 133 +++++++++++ .../examples/test_riscv_example_005.s.snap | 52 ++++ .../examples/test_riscv_example_006.s.snap | 54 +++++ .../examples/test_riscv_example_007.s.snap | 74 ++++++ .../examples/test_riscv_example_008.s.snap | 167 +++++++++++++ .../examples/test_riscv_example_009.s.snap | 177 ++++++++++++++ .../examples/test_riscv_example_010.s.snap | 223 ++++++++++++++++++ .../examples/test_riscv_example_011.s.snap | 83 +++++++ .../examples/test_riscv_example_012.s.snap | 129 ++++++++++ .../examples/test_riscv_example_013.s.snap | 78 ++++++ .../examples/test_riscv_example_014.s.snap | 221 +++++++++++++++++ .../examples/test_riscv_example_015.s.snap | 126 ++++++++++ .../examples/test_riscv_tutorial_001.s.snap | 71 ++++++ .../syscalls/test_riscv_syscall_001.s.snap | 117 +++++++++ .../syscalls/test_riscv_syscall_002.s.snap | 52 ++++ .../syscalls/test_riscv_syscall_003.s.snap | 52 ++++ .../syscalls/test_riscv_syscall_004.s.snap | 81 +++++++ .../syscalls/test_riscv_syscall_005.s.snap | 24 ++ .../syscalls/test_riscv_syscall_006.s.snap | 24 ++ .../syscalls/test_riscv_syscall_008.s.snap | 41 ++++ .../syscalls/test_riscv_syscall_010.s.snap | 27 +++ .../syscalls/test_riscv_syscall_011.s.snap | 28 +++ .../syscalls/test_riscv_syscall_012.s.snap | 24 ++ .../test_riscv_instruction_001.s.snap | 49 ++++ .../test_riscv_instruction_002.s.snap | 36 +++ .../test_riscv_instruction_003.s.snap | 55 +++++ .../test_riscv_instruction_004.s.snap | 38 +++ .../test_riscv_instruction_005.s.snap | 58 +++++ .../test_riscv_instruction_006.s.snap | 61 +++++ .../test_riscv_instruction_007.s.snap | 66 ++++++ .../test_riscv_instruction_008.s.snap | 62 +++++ .../test_riscv_instruction_009.s.snap | 67 ++++++ .../test_riscv_instruction_010.s.snap | 66 ++++++ .../test_riscv_instruction_011.s.snap | 67 ++++++ .../test_riscv_instruction_012.s.snap | 66 ++++++ .../test_riscv_instruction_013.s.snap | 91 +++++++ .../test_riscv_instruction_014.s.snap | 67 ++++++ .../test_riscv_instruction_015.s.snap | 62 +++++ .../test_riscv_instruction_016.s.snap | 62 +++++ .../test_riscv_instruction_017.s.snap | 57 +++++ .../test_riscv_instruction_018.s.snap | 57 +++++ .../test_riscv_instruction_019.s.snap | 57 +++++ .../test_riscv_instruction_020.s.snap | 53 +++++ .../test_riscv_instruction_021.s.snap | 53 +++++ .../test_riscv_instruction_022.s.snap | 56 +++++ .../test_riscv_instruction_023.s.snap | 66 ++++++ .../test_riscv_instruction_024.s.snap | 57 +++++ .../test_riscv_instruction_025.s.snap | 57 +++++ .../test_riscv_instruction_026.s.snap | 71 ++++++ .../test_riscv_instruction_027.s.snap | 66 ++++++ .../test_riscv_instruction_028.s.snap | 68 ++++++ .../test_riscv_instruction_029.s.snap | 71 ++++++ .../test_riscv_instruction_030.s.snap | 71 ++++++ .../test_riscv_instruction_031.s.snap | 116 +++++++++ .../test_riscv_instruction_032.s.snap | 53 +++++ .../test_riscv_instruction_033.s.snap | 53 +++++ .../test_riscv_instruction_034.s.snap | 56 +++++ .../test_riscv_instruction_035.s.snap | 54 +++++ .../test_riscv_instruction_036.s.snap | 54 +++++ .../test_riscv_instruction_037.s.snap | 54 +++++ .../test_riscv_instruction_038.s.snap | 58 +++++ .../test_riscv_instruction_039.s.snap | 58 +++++ .../test_riscv_instruction_040.s.snap | 57 +++++ .../test_riscv_instruction_041.s.snap | 57 +++++ .../test_riscv_instruction_042.s.snap | 62 +++++ .../test_riscv_instruction_043.s.snap | 62 +++++ .../test_riscv_instruction_044.s.snap | 62 +++++ .../test_riscv_instruction_045.s.snap | 62 +++++ .../test_riscv_instruction_046.s.snap | 57 +++++ .../test_riscv_instruction_047.s.snap | 57 +++++ .../test_riscv_instruction_048.s.snap | 39 +++ .../test_riscv_instruction_049.s.snap | 40 ++++ .../test_riscv_instruction_050.s.snap | 39 +++ .../test_riscv_instruction_051.s.snap | 39 +++ .../test_riscv_instruction_052.s.snap | 152 ++++++++++++ .../test_riscv_instruction_053.s.snap | 155 ++++++++++++ .../test_riscv_instruction_054.s.snap | 154 ++++++++++++ .../test_riscv_instruction_055.s.snap | 154 ++++++++++++ .../test_riscv_instruction_056.s.snap | 155 ++++++++++++ .../test_riscv_instruction_057.s.snap | 155 ++++++++++++ .../test_riscv_instruction_058.s.snap | 131 ++++++++++ .../test_riscv_instruction_059.s.snap | 131 ++++++++++ .../test_riscv_instruction_060.s.snap | 131 ++++++++++ .../test_riscv_instruction_061.s.snap | 134 +++++++++++ .../test_riscv_instruction_062.s.snap | 134 +++++++++++ .../test_riscv_instruction_063.s.snap | 154 ++++++++++++ .../test_riscv_instruction_064.s.snap | 156 ++++++++++++ .../test_riscv_instruction_065.s.snap | 153 ++++++++++++ .../sentinel/test_riscv_sentinels_001.s.snap | 56 +++++ .../sentinel/test_riscv_sentinels_002.s.snap | 56 +++++ .../sentinel/test_riscv_sentinels_003.s.snap | 56 +++++ .../sentinel/test_riscv_sentinels_004.s.snap | 56 +++++ .../sentinel/test_riscv_sentinels_005.s.snap | 56 +++++ .../sentinel/test_riscv_sentinels_006.s.snap | 56 +++++ .../sentinel/test_riscv_sentinels_007.s.snap | 56 +++++ .../sentinel/test_riscv_sentinels_008.s.snap | 55 +++++ .../sentinel/test_riscv_sentinels_009.s.snap | 60 +++++ .../sentinel/test_riscv_sentinels_010.s.snap | 60 +++++ .../sentinel/test_riscv_sentinels_011.s.snap | 60 +++++ .../sentinel/test_riscv_sentinels_012.s.snap | 60 +++++ .../sentinel/test_riscv_sentinels_013.s.snap | 60 +++++ .../sentinel/test_riscv_sentinels_014.s.snap | 60 +++++ .../sentinel/test_riscv_sentinels_015.s.snap | 60 +++++ .../sentinel/test_riscv_sentinels_016.s.snap | 57 +++++ .../sentinel/test_riscv_sentinels_017.s.snap | 63 +++++ .../sentinel/test_riscv_sentinels_018.s.snap | 63 +++++ .../sentinel/test_riscv_sentinels_019.s.snap | 63 +++++ .../sentinel/test_riscv_sentinels_020.s.snap | 63 +++++ .../sentinel/test_riscv_sentinels_021.s.snap | 63 +++++ .../sentinel/test_riscv_sentinels_022.s.snap | 63 +++++ .../sentinel/test_riscv_sentinels_023.s.snap | 63 +++++ .../sentinel/test_riscv_sentinels_024.s.snap | 63 +++++ .../sentinel/test_riscv_sentinels_025.s.snap | 63 +++++ .../sentinel/test_riscv_sentinels_026.s.snap | 63 +++++ .../sentinel/test_riscv_sentinels_027.s.snap | 63 +++++ .../sentinel/test_riscv_sentinels_028.s.snap | 33 +++ .../sentinel/test_riscv_sentinels_029.s.snap | 37 +++ .../sentinel/test_riscv_sentinels_030.s.snap | 33 +++ .../sentinel/test_riscv_sentinels_031.s.snap | 33 +++ .../sentinel/test_riscv_sentinels_032.s.snap | 47 ++++ .../sentinel/test_riscv_sentinels_033.s.snap | 50 ++++ .../sentinel/test_riscv_sentinels_034.s.snap | 53 +++++ .../sentinel/test_riscv_sentinels_035.s.snap | 53 +++++ .../sentinel/test_riscv_sentinels_036.s.snap | 54 +++++ .../sentinel/test_riscv_sentinels_037.s.snap | 120 ++++++++++ .../examples/test_mips_example_001.out | 5 - .../correct/examples/test_mips_example_001.s | 40 +++- .../examples/test_mips_example_002.out | 3 - .../correct/examples/test_mips_example_002.s | 1 + .../examples/test_mips_example_003.out | 3 - .../correct/examples/test_mips_example_003.s | 8 +- .../examples/test_mips_example_004.out | 3 - .../correct/examples/test_mips_example_004.s | 12 +- .../examples/test_mips_example_005.out | 4 - .../correct/examples/test_mips_example_005.s | 24 +- .../examples/test_mips_example_006.out | 3 - .../examples/test_mips_example_007.out | 3 - .../correct/examples/test_mips_example_007.s | 2 +- .../examples/test_mips_example_008.out | 3 - .../examples/test_mips_example_011.out | 4 - .../examples/test_mips_example_012.out | 4 - .../correct/examples/test_mips_example_012.s | 2 +- .../examples/test_mips_example_013.out | 41 ---- .../correct/examples/test_mips_example_013.s | 16 ++ .../syscalls/test_mips_syscall_001.out | 10 - .../correct/syscalls/test_mips_syscall_001.s | 10 +- .../syscalls/test_mips_syscall_002.out | 6 - .../correct/syscalls/test_mips_syscall_002.s | 3 +- .../syscalls/test_mips_syscall_003.out | 6 - .../correct/syscalls/test_mips_syscall_003.s | 3 +- .../syscalls/test_mips_syscall_004.out | 8 - .../correct/syscalls/test_mips_syscall_004.s | 1 + .../correct/syscalls/test_mips_syscall_005.s | 3 +- .../correct/syscalls/test_mips_syscall_006.s | 1 + .../correct/syscalls/test_mips_syscall_007.s | 2 +- .../correct/syscalls/test_mips_syscall_008.s | 3 +- .../correct/syscalls/test_mips_syscall_009.s | 5 +- .../syscalls/test_mips_syscall_010.out | 3 - .../correct/syscalls/test_mips_syscall_010.s | 1 + .../syscalls/test_mips_syscall_011.out | 4 - .../correct/syscalls/test_mips_syscall_011.s | 1 + .../correct/syscalls/test_mips_syscall_012.s | 7 +- .../test_mips_instruction_001.out | 3 - .../instructions/test_mips_instruction_001.s | 4 +- .../test_mips_instruction_002.out | 3 - .../instructions/test_mips_instruction_002.s | 2 + .../test_mips_instruction_003.out | 3 - .../instructions/test_mips_instruction_003.s | 4 +- .../test_mips_instruction_004.out | 3 - .../instructions/test_mips_instruction_004.s | 4 +- .../test_mips_instruction_005.out | 3 - .../instructions/test_mips_instruction_005.s | 4 +- .../test_mips_instruction_006.out | 3 - .../instructions/test_mips_instruction_006.s | 4 +- .../test_mips_instruction_007.out | 3 - .../instructions/test_mips_instruction_007.s | 1 - .../test_mips_instruction_008.out | 12 - .../instructions/test_mips_instruction_008.s | 22 +- .../test_mips_instruction_009.out | 3 - .../test_mips_instruction_010.out | 3 - .../test_mips_instruction_011.out | 3 - .../test_mips_instruction_012.out | 3 - .../test_mips_instruction_013.out | 3 - .../instructions/test_mips_instruction_013.s | 2 + .../test_mips_instruction_014.out | 3 - .../instructions/test_mips_instruction_014.s | 2 + .../test_mips_instruction_015.out | 3 - .../instructions/test_mips_instruction_015.s | 2 + .../test_mips_instruction_016.out | 3 - .../instructions/test_mips_instruction_016.s | 2 + .../test_mips_instruction_017.out | 3 - .../instructions/test_mips_instruction_017.s | 1 + .../test_mips_instruction_018.out | 3 - .../instructions/test_mips_instruction_018.s | 2 + .../test_mips_instruction_019.out | 3 - .../instructions/test_mips_instruction_019.s | 3 +- .../test_mips_instruction_020.out | 3 - .../instructions/test_mips_instruction_020.s | 2 + .../test_mips_instruction_021.out | 3 - .../instructions/test_mips_instruction_021.s | 2 + .../test_mips_instruction_022.out | 3 - .../instructions/test_mips_instruction_022.s | 2 + .../test_mips_instruction_023.out | 3 - .../instructions/test_mips_instruction_023.s | 2 + .../test_mips_instruction_024.out | 3 - .../instructions/test_mips_instruction_024.s | 3 +- .../test_mips_instruction_025.out | 3 - .../instructions/test_mips_instruction_025.s | 2 + .../test_mips_instruction_026.out | 3 - .../instructions/test_mips_instruction_026.s | 3 +- .../test_mips_instruction_027.out | 3 - .../instructions/test_mips_instruction_027.s | 2 + .../test_mips_instruction_028.out | 3 - .../instructions/test_mips_instruction_028.s | 2 + .../test_mips_instruction_029.out | 3 - .../instructions/test_mips_instruction_029.s | 3 +- .../test_mips_instruction_030.out | 3 - .../instructions/test_mips_instruction_030.s | 2 + .../test_mips_instruction_031.out | 3 - .../instructions/test_mips_instruction_031.s | 2 +- .../test_mips_instruction_032.out | 3 - .../instructions/test_mips_instruction_032.s | 8 + .../test_mips_instruction_033.out | 13 - .../instructions/test_mips_instruction_033.s | 15 -- .../test_mips_instruction_034.out | 3 - .../instructions/test_mips_instruction_034.s | 2 + .../test_mips_instruction_035.out | 3 - .../instructions/test_mips_instruction_035.s | 4 +- .../test_mips_instruction_036.out | 3 - .../instructions/test_mips_instruction_036.s | 4 +- .../test_mips_instruction_037.out | 13 - .../instructions/test_mips_instruction_037.s | 28 ++- .../test_mips_instruction_038.out | 3 - .../instructions/test_mips_instruction_038.s | 2 + .../test_mips_instruction_039.out | 3 - .../instructions/test_mips_instruction_039.s | 2 + .../test_mips_instruction_040.out | 3 - .../instructions/test_mips_instruction_040.s | 2 + .../test_mips_instruction_041.out | 3 - .../instructions/test_mips_instruction_041.s | 2 + .../test_mips_instruction_042.out | 3 - .../test_mips_instruction_043.out | 3 - .../test_mips_instruction_044.out | 3 - .../test_mips_instruction_045.out | 3 - .../test_mips_instruction_046.out | 3 - .../instructions/test_mips_instruction_046.s | 5 +- .../test_mips_instruction_047.out | 3 - .../instructions/test_mips_instruction_047.s | 2 + .../test_mips_instruction_048.out | 3 - .../instructions/test_mips_instruction_048.s | 2 + .../test_mips_instruction_049.out | 3 - .../instructions/test_mips_instruction_049.s | 2 + .../test_mips_instruction_050.out | 3 - .../instructions/test_mips_instruction_050.s | 2 + .../test_mips_instruction_051.out | 3 - .../instructions/test_mips_instruction_051.s | 2 - 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tests/arch/riscv/sentinel/test_riscv_sentinels_037.s create mode 100644 tests/arch/riscv64/load_test.s diff --git a/deno.lock b/deno.lock index 36ad7990d..0ea81da64 100644 --- a/deno.lock +++ b/deno.lock @@ -1,6 +1,12 @@ { "version": "5", "specifiers": { + "jsr:@std/assert@^1.0.17": "1.0.19", + "jsr:@std/fs@^1.0.22": "1.0.23", + "jsr:@std/internal@^1.0.12": "1.0.12", + "jsr:@std/path@*": "1.1.4", + "jsr:@std/path@^1.1.4": "1.1.4", + "jsr:@std/testing@*": "1.0.17", "npm:@codemirror/lang-yaml@^6.1.2": "6.1.2", "npm:@codemirror/language@^6.11.3": "6.12.1", "npm:@codemirror/legacy-modes@^6.5.1": "6.5.2", @@ -69,6 +75,35 @@ "npm:xterm@^5.3.0": "5.3.0", "npm:yargs@18": "18.0.0" }, + "jsr": { + "@std/assert@1.0.19": { + "integrity": "eaada96ee120cb980bc47e040f82814d786fe8162ecc53c91d8df60b8755991e" + }, + "@std/fs@1.0.23": { + "integrity": "3ecbae4ce4fee03b180fa710caff36bb5adb66631c46a6460aaad49515565a37", + "dependencies": [ + "jsr:@std/path@^1.1.4" + ] + }, + "@std/internal@1.0.12": { + "integrity": "972a634fd5bc34b242024402972cd5143eac68d8dffaca5eaa4dba30ce17b027" + }, + "@std/path@1.1.4": { + "integrity": "1d2d43f39efb1b42f0b1882a25486647cb851481862dc7313390b2bb044314b5", + "dependencies": [ + "jsr:@std/internal" + ] + }, + "@std/testing@1.0.17": { + "integrity": "87bdc2700fa98249d48a17cd72413352d3d3680dcfbdb64947fd0982d6bbf681", + "dependencies": [ + "jsr:@std/assert", + "jsr:@std/fs", + "jsr:@std/internal", + "jsr:@std/path@^1.1.4" + ] + } + }, "npm": { "@aesoper/normal-utils@0.1.5": { "integrity": "sha512-LFF/6y6h5mfwhnJaWqqxuC8zzDaHCG62kMRkd8xhDtq62TQj9dM17A9DhE87W7DhiARJsHLgcina/9P4eNCN1w==" diff --git a/tests/arch/__snapshots__/mips/correct/examples/test_mips_example_001.s.snap b/tests/arch/__snapshots__/mips/correct/examples/test_mips_example_001.s.snap new file mode 100644 index 000000000..ef55d71b2 --- /dev/null +++ b/tests/arch/__snapshots__/mips/correct/examples/test_mips_example_001.s.snap @@ -0,0 +1,106 @@ +export const snapshot = {}; + +snapshot[`mips/correct/examples/test_mips_example_001.s 1`] = ` +{ + display: "1234", + error: false, + keyboard: "", + memory: { + "0": 60, + "1": 1, + "10": 32, + "11": 32, + "12": 128, + "13": 132, + "16": 32, + "17": 2, + "19": 1, + "2097152": 12, + "2097155": 34, + "2097156": 255, + "2097157": 255, + "2097158": 233, + "2097159": 210, + "2097160": 67, + "2097161": 228, + "2097162": 41, + "2097163": 55, + "2097164": 64, + "2097165": 195, + "2097166": 6, + "2097167": 171, + "2097168": 133, + "2097169": 30, + "2097170": 184, + "2097171": 82, + "2097172": 84, + "2097173": 104, + "2097174": 105, + "2097175": 115, + "2097176": 32, + "2097177": 105, + "2097178": 115, + "2097179": 32, + "2097180": 97, + "2097181": 32, + "2097182": 115, + "2097183": 116, + "2097184": 114, + "2097185": 105, + "2097186": 110, + "2097187": 103, + "2097189": 84, + "2097190": 104, + "2097191": 105, + "2097192": 115, + "2097193": 32, + "2097194": 105, + "2097195": 115, + "2097196": 32, + "2097197": 97, + "2097198": 110, + "2097199": 111, + "2097200": 116, + "2097201": 104, + "2097202": 101, + "2097203": 114, + "2097204": 32, + "2097205": 115, + "2097206": 116, + "2097207": 114, + "2097208": 105, + "2097209": 110, + "2097210": 103, + "23": 12, + "24": 60, + "25": 1, + "27": 32, + "28": 52, + "29": 33, + "3": 32, + "31": 2, + "33": 32, + "34": 32, + "35": 32, + "36": 132, + "37": 132, + "4": 52, + "40": 32, + "41": 2, + "43": 1, + "47": 12, + "48": 3, + "49": 224, + "5": 33, + "51": 8, + "9": 32, + }, + registers: { + "1,at": "0x200002", + "2,v0": "0x1", + "4,a0": "0x22", + PC: "0xffffffff", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/correct/examples/test_mips_example_002.s.snap b/tests/arch/__snapshots__/mips/correct/examples/test_mips_example_002.s.snap new file mode 100644 index 000000000..ba6eca87e --- /dev/null +++ b/tests/arch/__snapshots__/mips/correct/examples/test_mips_example_002.s.snap @@ -0,0 +1,54 @@ +export const snapshot = {}; + +snapshot[`mips/correct/examples/test_mips_example_002.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 8, + "11": 45, + "12": 32, + "13": 11, + "15": 33, + "16": 1, + "17": 40, + "18": 96, + "19": 32, + "20": 1, + "21": 170, + "22": 88, + "23": 34, + "24": 113, + "25": 203, + "26": 88, + "27": 2, + "28": 1, + "29": 201, + "3": 10, + "30": 120, + "31": 154, + "32": 3, + "33": 224, + "35": 8, + "4": 32, + "5": 9, + "7": 13, + "8": 32, + "9": 10, + }, + registers: { + "10,t2": "0x2d", + "11,t3": "0x21", + "12,t4": "0x17", + "13,t5": "0xc", + "14,t6": "0x441", + "15,t7": "0x53", + "8,t0": "0xa", + "9,t1": "0xd", + PC: "0xffffffff", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/correct/examples/test_mips_example_003.s.snap b/tests/arch/__snapshots__/mips/correct/examples/test_mips_example_003.s.snap new file mode 100644 index 000000000..0a85e28b9 --- /dev/null +++ b/tests/arch/__snapshots__/mips/correct/examples/test_mips_example_003.s.snap @@ -0,0 +1,113 @@ +export const snapshot = {}; + +snapshot[`mips/correct/examples/test_mips_example_003.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 60, + "1": 1, + "10": 64, + "100": 52, + "101": 33, + "103": 12, + "104": 160, + "105": 45, + "108": 60, + "109": 1, + "11": 32, + "111": 32, + "112": 52, + "113": 33, + "115": 14, + "116": 164, + "117": 47, + "12": 60, + "120": 3, + "121": 224, + "123": 8, + "13": 1, + "15": 32, + "16": 52, + "17": 33, + "19": 4, + "2097155": 14, + "2097156": 120, + "2097159": 22, + "2097163": 14, + "2097164": 120, + "2097167": 22, + "21": 32, + "22": 72, + "23": 32, + "24": 60, + "25": 1, + "27": 32, + "28": 52, + "29": 33, + "3": 32, + "31": 6, + "33": 32, + "34": 80, + "35": 32, + "36": 141, + "37": 11, + "4": 52, + "40": 60, + "41": 1, + "43": 32, + "44": 52, + "45": 33, + "48": 140, + "49": 44, + "5": 33, + "52": 129, + "53": 45, + "56": 60, + "57": 1, + "59": 32, + "60": 52, + "61": 33, + "63": 4, + "64": 128, + "65": 46, + "68": 133, + "69": 79, + "72": 60, + "73": 1, + "75": 32, + "76": 52, + "77": 33, + "79": 6, + "80": 132, + "81": 56, + "84": 60, + "85": 1, + "87": 32, + "88": 52, + "89": 33, + "9": 32, + "91": 8, + "92": 172, + "93": 43, + "96": 60, + "97": 1, + "99": 32, + }, + registers: { + "1,at": "0x20000e", + "10,t2": "0x200006", + "11,t3": "0xe", + "12,t4": "0xe", + "13,t5": "0x78", + "14,t6": "0x78", + "15,t7": "0x16", + "24,t8": "0x16", + "8,t0": "0x200000", + "9,t1": "0x200004", + PC: "0xffffffff", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/correct/examples/test_mips_example_004.s.snap b/tests/arch/__snapshots__/mips/correct/examples/test_mips_example_004.s.snap new file mode 100644 index 000000000..ee838237c --- /dev/null +++ b/tests/arch/__snapshots__/mips/correct/examples/test_mips_example_004.s.snap @@ -0,0 +1,145 @@ +export const snapshot = {}; + +snapshot[`mips/correct/examples/test_mips_example_004.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 60, + "1": 1, + "10": 64, + "11": 32, + "12": 60, + "13": 1, + "15": 32, + "16": 52, + "17": 33, + "19": 8, + "2097152": 64, + "2097153": 65, + "2097154": 69, + "2097155": 161, + "2097156": 202, + "2097157": 192, + "2097158": 131, + "2097159": 18, + "2097160": 64, + "2097161": 38, + "2097162": 226, + "2097163": 208, + "2097164": 229, + "2097165": 96, + "2097166": 65, + "2097167": 137, + "2097168": 64, + "2097169": 132, + "2097170": 203, + "2097171": 51, + "2097172": 51, + "2097173": 51, + "2097174": 51, + "2097175": 51, + "2097176": 64, + "2097177": 81, + "2097178": 69, + "2097179": 161, + "2097180": 202, + "2097181": 192, + "2097182": 131, + "2097183": 18, + "2097184": 64, + "2097185": 130, + "2097186": 162, + "2097187": 126, + "2097188": 249, + "2097189": 219, + "2097190": 34, + "2097191": 209, + "2097192": 64, + "2097193": 77, + "2097194": 19, + "2097195": 21, + "2097196": 70, + "2097197": 137, + "2097198": 195, + "2097199": 233, + "21": 32, + "22": 72, + "23": 32, + "24": 60, + "25": 1, + "27": 32, + "28": 52, + "29": 33, + "3": 32, + "31": 16, + "33": 32, + "34": 80, + "35": 32, + "36": 60, + "37": 1, + "39": 32, + "4": 52, + "40": 52, + "41": 33, + "43": 24, + "45": 32, + "46": 88, + "47": 32, + "48": 213, + "5": 33, + "52": 213, + "53": 34, + "56": 213, + "57": 74, + "60": 68, + "61": 32, + "64": 68, + "65": 32, + "66": 81, + "67": 1, + "68": 68, + "69": 34, + "70": 83, + "71": 3, + "72": 245, + "73": 96, + "76": 33, + "77": 107, + "79": 8, + "80": 245, + "81": 100, + "84": 33, + "85": 107, + "87": 8, + "88": 245, + "89": 108, + "9": 32, + "92": 32, + "93": 2, + "95": 10, + "99": 12, + }, + registers: { + "1,at": "0x200018", + "10,t2": "0x200010", + "11,t3": "0x200028", + "2,v0": "0xa", + "8,t0": "0x200000", + "9,t1": "0x200008", + "f0,FP0": "0x405145a1", + "f10,FP10": "0x4084cb33", + "f12,FP12": "0x404d1315", + "f2,FP2": "0x4026e2d0", + "f4,FP4": "0x4082a27e", + PC: "0x64", + f11: "0x33333333", + f13: "0x4689c3e9", + f1: "0xcac08312", + f3: "0xe5604189", + f5: "0xf9db22d1", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/correct/examples/test_mips_example_005.s.snap b/tests/arch/__snapshots__/mips/correct/examples/test_mips_example_005.s.snap new file mode 100644 index 000000000..4f41b6af9 --- /dev/null +++ b/tests/arch/__snapshots__/mips/correct/examples/test_mips_example_005.s.snap @@ -0,0 +1,56 @@ +export const snapshot = {}; + +snapshot[`mips/correct/examples/test_mips_example_005.s 1`] = ` +{ + display: "45", + error: false, + keyboard: "", + memory: { + "0": 60, + "1": 1, + "12": 32, + "13": 9, + "16": 32, + "17": 4, + "20": 1, + "2097152": 10, + "21": 40, + "22": 8, + "23": 42, + "24": 16, + "25": 1, + "27": 16, + "28": 1, + "29": 36, + "3": 32, + "30": 32, + "31": 32, + "32": 33, + "33": 41, + "35": 1, + "36": 4, + "37": 1, + "38": 255, + "39": 240, + "4": 52, + "40": 32, + "41": 2, + "43": 1, + "47": 12, + "48": 3, + "49": 224, + "5": 33, + "51": 8, + "8": 128, + "9": 40, + }, + registers: { + "2,v0": "0x1", + "4,a0": "0x2d", + "8,t0": "0xa", + "9,t1": "0xa", + PC: "0xffffffff", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/correct/examples/test_mips_example_006.s.snap b/tests/arch/__snapshots__/mips/correct/examples/test_mips_example_006.s.snap new file mode 100644 index 000000000..e5b07a381 --- /dev/null +++ b/tests/arch/__snapshots__/mips/correct/examples/test_mips_example_006.s.snap @@ -0,0 +1,58 @@ +export const snapshot = {}; + +snapshot[`mips/correct/examples/test_mips_example_006.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 8, + "11": 5, + "12": 32, + "13": 33, + "15": 1, + "16": 41, + "17": 1, + "19": 5, + "20": 20, + "21": 1, + "23": 16, + "24": 32, + "25": 11, + "27": 34, + "28": 32, + "29": 2, + "3": 4, + "31": 10, + "35": 12, + "36": 32, + "37": 25, + "39": 11, + "4": 32, + "40": 32, + "41": 24, + "42": 2, + "43": 43, + "44": 4, + "45": 1, + "46": 255, + "47": 236, + "5": 9, + "7": 2, + "8": 32, + "9": 1, + }, + registers: { + "1,at": "0x1", + "11,t3": "0x22", + "2,v0": "0xa", + "24,t8": "0x22b", + "25,t9": "0xb", + "8,t0": "0x4", + "9,t1": "0x2", + PC: "0x24", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/correct/examples/test_mips_example_007.s.snap b/tests/arch/__snapshots__/mips/correct/examples/test_mips_example_007.s.snap new file mode 100644 index 000000000..7a394b823 --- /dev/null +++ b/tests/arch/__snapshots__/mips/correct/examples/test_mips_example_007.s.snap @@ -0,0 +1,78 @@ +export const snapshot = {}; + +snapshot[`mips/correct/examples/test_mips_example_007.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 11, + "11": 32, + "12": 52, + "13": 33, + "17": 32, + "18": 104, + "19": 32, + "20": 32, + "2097155": 1, + "2097159": 2, + "2097163": 3, + "2097167": 4, + "2097171": 5, + "21": 15, + "24": 32, + "25": 9, + "28": 32, + "29": 10, + "3": 1, + "31": 5, + "32": 17, + "33": 73, + "35": 28, + "36": 113, + "37": 201, + "38": 96, + "39": 2, + "4": 32, + "40": 141, + "41": 174, + "44": 1, + "45": 207, + "46": 120, + "47": 32, + "48": 1, + "49": 105, + "5": 12, + "50": 72, + "51": 32, + "52": 33, + "53": 173, + "55": 4, + "56": 4, + "57": 1, + "58": 255, + "59": 232, + "60": 32, + "61": 2, + "63": 10, + "67": 12, + "7": 4, + "8": 60, + "9": 1, + }, + registers: { + "1,at": "0x200000", + "10,t2": "0x5", + "11,t3": "0x1", + "12,t4": "0x4", + "13,t5": "0x200014", + "14,t6": "0x5", + "15,t7": "0xf", + "2,v0": "0xa", + "9,t1": "0x5", + PC: "0x44", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/correct/examples/test_mips_example_008.s.snap b/tests/arch/__snapshots__/mips/correct/examples/test_mips_example_008.s.snap new file mode 100644 index 000000000..f161c277d --- /dev/null +++ b/tests/arch/__snapshots__/mips/correct/examples/test_mips_example_008.s.snap @@ -0,0 +1,171 @@ +export const snapshot = {}; + +snapshot[`mips/correct/examples/test_mips_example_008.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 60, + "1": 1, + "10": 64, + "11": 32, + "12": 60, + "13": 1, + "15": 32, + "16": 52, + "17": 33, + "19": 64, + "2097152": 52, + "2097156": 52, + "2097160": 52, + "2097164": 52, + "2097168": 35, + "2097169": 69, + "2097173": 67, + "2097174": 34, + "2097175": 16, + "2097176": 119, + "2097177": 81, + "2097178": 33, + "2097179": 32, + "2097180": 20, + "2097181": 20, + "2097182": 20, + "2097183": 20, + "2097186": 2, + "2097187": 20, + "2097188": 68, + "2097189": 85, + "2097190": 17, + "2097191": 34, + "2097192": 170, + "2097193": 191, + "2097194": 240, + "2097195": 18, + "2097196": 119, + "2097197": 208, + "2097202": 255, + "2097203": 35, + "2097204": 18, + "2097205": 52, + "2097206": 86, + "2097207": 120, + "2097208": 135, + "2097209": 101, + "2097210": 67, + "2097211": 33, + "2097212": 51, + "2097213": 68, + "2097214": 17, + "2097215": 36, + "2097216": 52, + "2097220": 52, + "2097224": 52, + "2097228": 52, + "2097232": 35, + "2097233": 69, + "2097237": 67, + "2097238": 34, + "2097239": 16, + "2097240": 119, + "2097241": 81, + "2097242": 33, + "2097243": 32, + "2097244": 20, + "2097245": 20, + "2097246": 20, + "2097247": 20, + "2097250": 2, + "2097251": 20, + "2097252": 68, + "2097253": 85, + "2097254": 17, + "2097255": 34, + "2097256": 170, + "2097257": 191, + "2097258": 240, + "2097259": 18, + "2097260": 119, + "2097261": 208, + "2097266": 255, + "2097267": 35, + "2097268": 18, + "2097269": 52, + "2097270": 86, + "2097271": 120, + "2097272": 135, + "2097273": 101, + "2097274": 67, + "2097275": 33, + "2097276": 51, + "2097277": 68, + "2097278": 17, + "2097279": 36, + "21": 32, + "22": 72, + "23": 32, + "24": 32, + "25": 10, + "27": 4, + "28": 32, + "29": 11, + "3": 32, + "31": 4, + "34": 96, + "35": 32, + "38": 104, + "39": 32, + "4": 52, + "40": 17, + "41": 138, + "43": 44, + "44": 17, + "45": 171, + "47": 28, + "48": 197, + "5": 33, + "52": 229, + "53": 32, + "56": 33, + "57": 8, + "59": 4, + "60": 33, + "61": 41, + "63": 4, + "64": 33, + "65": 173, + "67": 1, + "68": 4, + "69": 1, + "70": 255, + "71": 232, + "72": 33, + "73": 140, + "75": 1, + "78": 104, + "79": 32, + "80": 4, + "81": 1, + "82": 255, + "83": 216, + "84": 32, + "85": 2, + "87": 10, + "9": 32, + "91": 12, + }, + registers: { + "1,at": "0x200040", + "10,t2": "0x4", + "11,t3": "0x4", + "12,t4": "0x4", + "2,v0": "0xa", + "8,t0": "0x200040", + "9,t1": "0x200080", + "f0,FP0": "0x33441124", + PC: "0x5c", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/correct/examples/test_mips_example_009.s.snap b/tests/arch/__snapshots__/mips/correct/examples/test_mips_example_009.s.snap new file mode 100644 index 000000000..6460ae63b --- /dev/null +++ b/tests/arch/__snapshots__/mips/correct/examples/test_mips_example_009.s.snap @@ -0,0 +1,169 @@ +export const snapshot = {}; + +snapshot[`mips/correct/examples/test_mips_example_009.s 1`] = ` +{ + display: "Please, insert the first number.Please, insert the second number.The result is: 579", + error: false, + keyboard: " 123 456", + memory: { + "0": 60, + "1": 1, + "10": 32, + "100": 32, + "101": 2, + "103": 10, + "107": 12, + "11": 32, + "12": 32, + "13": 2, + "15": 4, + "19": 12, + "20": 32, + "2097152": 80, + "2097153": 108, + "2097154": 101, + "2097155": 97, + "2097156": 115, + "2097157": 101, + "2097158": 44, + "2097159": 32, + "2097160": 105, + "2097161": 110, + "2097162": 115, + "2097163": 101, + "2097164": 114, + "2097165": 116, + "2097166": 32, + "2097167": 116, + "2097168": 104, + "2097169": 101, + "2097170": 32, + "2097171": 102, + "2097172": 105, + "2097173": 114, + "2097174": 115, + "2097175": 116, + "2097176": 32, + "2097177": 110, + "2097178": 117, + "2097179": 109, + "2097180": 98, + "2097181": 101, + "2097182": 114, + "2097183": 46, + "2097185": 80, + "2097186": 108, + "2097187": 101, + "2097188": 97, + "2097189": 115, + "2097190": 101, + "2097191": 44, + "2097192": 32, + "2097193": 105, + "2097194": 110, + "2097195": 115, + "2097196": 101, + "2097197": 114, + "2097198": 116, + "2097199": 32, + "2097200": 116, + "2097201": 104, + "2097202": 101, + "2097203": 32, + "2097204": 115, + "2097205": 101, + "2097206": 99, + "2097207": 111, + "2097208": 110, + "2097209": 100, + "2097210": 32, + "2097211": 110, + "2097212": 117, + "2097213": 109, + "2097214": 98, + "2097215": 101, + "2097216": 114, + "2097217": 46, + "2097219": 84, + "2097220": 104, + "2097221": 101, + "2097222": 32, + "2097223": 114, + "2097224": 101, + "2097225": 115, + "2097226": 117, + "2097227": 108, + "2097228": 116, + "2097229": 32, + "2097230": 105, + "2097231": 115, + "2097232": 58, + "2097233": 32, + "21": 2, + "23": 5, + "27": 12, + "29": 64, + "3": 32, + "30": 64, + "31": 32, + "32": 60, + "33": 1, + "35": 32, + "36": 52, + "37": 33, + "39": 33, + "4": 52, + "41": 32, + "42": 32, + "43": 32, + "44": 32, + "45": 2, + "47": 4, + "5": 33, + "51": 12, + "52": 32, + "53": 2, + "55": 5, + "59": 12, + "61": 64, + "62": 72, + "63": 32, + "64": 1, + "65": 40, + "66": 80, + "67": 32, + "68": 60, + "69": 1, + "71": 32, + "72": 52, + "73": 33, + "75": 67, + "77": 32, + "78": 32, + "79": 32, + "80": 32, + "81": 2, + "83": 4, + "87": 12, + "88": 1, + "89": 64, + "9": 32, + "90": 32, + "91": 32, + "92": 32, + "93": 2, + "95": 1, + "99": 12, + }, + registers: { + "1,at": "0x200043", + "10,t2": "0x243", + "2,v0": "0xa", + "4,a0": "0x243", + "8,t0": "0x7b", + "9,t1": "0x1c8", + PC: "0x6c", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/correct/examples/test_mips_example_010.s.snap b/tests/arch/__snapshots__/mips/correct/examples/test_mips_example_010.s.snap new file mode 100644 index 000000000..ebe2c0e70 --- /dev/null +++ b/tests/arch/__snapshots__/mips/correct/examples/test_mips_example_010.s.snap @@ -0,0 +1,221 @@ +export const snapshot = {}; + +snapshot[`mips/correct/examples/test_mips_example_010.s 1`] = ` +{ + display: "Insert the string length (no more than 100 characters) Insert the string This is a very long string with many characters and a lot of data. :) 123 +", + error: false, + keyboard: " 74 This is a very long string with many characters and a lot of data. :) 123 +", + memory: { + "0": 60, + "1": 1, + "10": 32, + "11": 32, + "12": 32, + "13": 2, + "15": 4, + "19": 12, + "20": 32, + "2097152": 73, + "2097153": 110, + "2097154": 115, + "2097155": 101, + "2097156": 114, + "2097157": 116, + "2097158": 32, + "2097159": 116, + "2097160": 104, + "2097161": 101, + "2097162": 32, + "2097163": 115, + "2097164": 116, + "2097165": 114, + "2097166": 105, + "2097167": 110, + "2097168": 103, + "2097169": 32, + "2097170": 108, + "2097171": 101, + "2097172": 110, + "2097173": 103, + "2097174": 116, + "2097175": 104, + "2097176": 32, + "2097177": 40, + "2097178": 110, + "2097179": 111, + "2097180": 32, + "2097181": 109, + "2097182": 111, + "2097183": 114, + "2097184": 101, + "2097185": 32, + "2097186": 116, + "2097187": 104, + "2097188": 97, + "2097189": 110, + "2097190": 32, + "2097191": 49, + "2097192": 48, + "2097193": 48, + "2097194": 32, + "2097195": 99, + "2097196": 104, + "2097197": 97, + "2097198": 114, + "2097199": 97, + "2097200": 99, + "2097201": 116, + "2097202": 101, + "2097203": 114, + "2097204": 115, + "2097205": 41, + "2097206": 32, + "2097208": 73, + "2097209": 110, + "2097210": 115, + "2097211": 101, + "2097212": 114, + "2097213": 116, + "2097214": 32, + "2097215": 116, + "2097216": 104, + "2097217": 101, + "2097218": 32, + "2097219": 115, + "2097220": 116, + "2097221": 114, + "2097222": 105, + "2097223": 110, + "2097224": 103, + "2097225": 32, + "2097227": 84, + "2097228": 104, + "2097229": 105, + "2097230": 115, + "2097231": 32, + "2097232": 105, + "2097233": 115, + "2097234": 32, + "2097235": 97, + "2097236": 32, + "2097237": 118, + "2097238": 101, + "2097239": 114, + "2097240": 121, + "2097241": 32, + "2097242": 108, + "2097243": 111, + "2097244": 110, + "2097245": 103, + "2097246": 32, + "2097247": 115, + "2097248": 116, + "2097249": 114, + "2097250": 105, + "2097251": 110, + "2097252": 103, + "2097253": 32, + "2097254": 119, + "2097255": 105, + "2097256": 116, + "2097257": 104, + "2097258": 32, + "2097259": 109, + "2097260": 97, + "2097261": 110, + "2097262": 121, + "2097263": 32, + "2097264": 99, + "2097265": 104, + "2097266": 97, + "2097267": 114, + "2097268": 97, + "2097269": 99, + "2097270": 116, + "2097271": 101, + "2097272": 114, + "2097273": 115, + "2097274": 32, + "2097275": 97, + "2097276": 110, + "2097277": 100, + "2097278": 32, + "2097279": 97, + "2097280": 32, + "2097281": 108, + "2097282": 111, + "2097283": 116, + "2097284": 32, + "2097285": 111, + "2097286": 102, + "2097287": 32, + "2097288": 100, + "2097289": 97, + "2097290": 116, + "2097291": 97, + "2097292": 46, + "2097293": 32, + "2097294": 58, + "2097295": 41, + "2097296": 32, + "2097297": 49, + "2097298": 50, + "2097299": 51, + "2097300": 10, + "21": 2, + "23": 5, + "27": 12, + "29": 64, + "3": 32, + "30": 64, + "31": 32, + "32": 60, + "33": 1, + "35": 32, + "36": 52, + "37": 33, + "39": 56, + "4": 52, + "41": 32, + "42": 32, + "43": 32, + "44": 32, + "45": 2, + "47": 4, + "5": 33, + "51": 12, + "52": 60, + "53": 1, + "55": 32, + "56": 52, + "57": 33, + "59": 75, + "61": 32, + "62": 32, + "63": 32, + "64": 1, + "66": 40, + "67": 32, + "68": 32, + "69": 2, + "71": 8, + "75": 12, + "76": 32, + "77": 2, + "79": 4, + "83": 12, + "9": 32, + }, + registers: { + "1,at": "0x20004b", + "2,v0": "0x4", + "4,a0": "0x20004b", + "5,a1": "0x4a", + "8,t0": "0x4a", + PC: "0xfa0", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/correct/examples/test_mips_example_011.s.snap b/tests/arch/__snapshots__/mips/correct/examples/test_mips_example_011.s.snap new file mode 100644 index 000000000..aa1fe0e7b --- /dev/null +++ b/tests/arch/__snapshots__/mips/correct/examples/test_mips_example_011.s.snap @@ -0,0 +1,85 @@ +export const snapshot = {}; + +snapshot[`mips/correct/examples/test_mips_example_011.s 1`] = ` +{ + display: "-144", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 4, + "10": 255, + "11": 179, + "13": 32, + "14": 40, + "15": 32, + "16": 32, + "17": 6, + "19": 45, + "20": 12, + "23": 56, + "25": 64, + "26": 32, + "27": 32, + "29": 96, + "3": 23, + "30": 40, + "31": 32, + "32": 12, + "35": 76, + "37": 64, + "38": 32, + "39": 32, + "4": 60, + "40": 32, + "41": 2, + "43": 1, + "47": 12, + "48": 32, + "49": 2, + "5": 1, + "51": 10, + "55": 12, + "57": 164, + "58": 72, + "59": 32, + "6": 255, + "61": 198, + "62": 80, + "63": 32, + "64": 1, + "65": 32, + "66": 16, + "67": 32, + "68": 1, + "69": 64, + "7": 255, + "70": 24, + "71": 32, + "72": 3, + "73": 224, + "75": 8, + "77": 68, + "78": 40, + "79": 34, + "8": 52, + "80": 3, + "81": 224, + "83": 8, + "9": 33, + }, + registers: { + "1,at": "0xffffffb3", + "10,t2": "0x5a", + "2,v0": "0xa", + "3,v1": "0x5a", + "31,ra": "0x24", + "4,a0": "0xffffff70", + "5,a1": "0x5a", + "6,a2": "0x2d", + "9,t1": "0xffffffca", + PC: "0x38", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/correct/examples/test_mips_example_012.s.snap b/tests/arch/__snapshots__/mips/correct/examples/test_mips_example_012.s.snap new file mode 100644 index 000000000..d75d13a91 --- /dev/null +++ b/tests/arch/__snapshots__/mips/correct/examples/test_mips_example_012.s.snap @@ -0,0 +1,119 @@ +export const snapshot = {}; + +snapshot[`mips/correct/examples/test_mips_example_012.s 1`] = ` +{ + display: "120", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 4, + "10": 32, + "11": 32, + "12": 32, + "13": 2, + "15": 1, + "19": 12, + "20": 32, + "21": 2, + "23": 10, + "268435396": 15, + "268435397": 255, + "268435398": 255, + "268435399": 208, + "268435403": 76, + "268435407": 2, + "268435408": 15, + "268435409": 255, + "268435410": 255, + "268435411": 220, + "268435415": 76, + "268435419": 3, + "268435420": 15, + "268435421": 255, + "268435422": 255, + "268435423": 232, + "268435427": 76, + "268435431": 4, + "268435432": 15, + "268435433": 255, + "268435434": 255, + "268435435": 244, + "268435439": 76, + "268435443": 5, + "268435451": 8, + "27": 12, + "28": 32, + "29": 1, + "3": 5, + "31": 12, + "32": 3, + "33": 161, + "34": 232, + "35": 35, + "36": 175, + "37": 191, + "39": 8, + "4": 12, + "40": 175, + "41": 190, + "43": 4, + "44": 39, + "45": 190, + "47": 4, + "48": 40, + "49": 129, + "51": 2, + "52": 16, + "53": 1, + "55": 12, + "56": 32, + "57": 2, + "59": 1, + "60": 4, + "61": 1, + "63": 24, + "64": 175, + "65": 196, + "66": 255, + "67": 252, + "68": 32, + "69": 132, + "7": 28, + "70": 255, + "71": 255, + "72": 12, + "75": 28, + "76": 143, + "77": 201, + "78": 255, + "79": 252, + "80": 112, + "81": 66, + "82": 72, + "83": 2, + "84": 143, + "85": 191, + "87": 8, + "88": 143, + "89": 190, + "9": 64, + "91": 4, + "92": 39, + "93": 189, + "95": 12, + "96": 3, + "97": 224, + "99": 8, + }, + registers: { + "1,at": "0x1", + "2,v0": "0xa", + "31,ra": "0x8", + "4,a0": "0x78", + "9,t1": "0x5", + PC: "0x1c", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/correct/examples/test_mips_example_013.s.snap b/tests/arch/__snapshots__/mips/correct/examples/test_mips_example_013.s.snap new file mode 100644 index 000000000..e1ad6b48b --- /dev/null +++ b/tests/arch/__snapshots__/mips/correct/examples/test_mips_example_013.s.snap @@ -0,0 +1,79 @@ +export const snapshot = {}; + +snapshot[`mips/correct/examples/test_mips_example_013.s 1`] = ` +{ + display: "83116114105110103321051103285847045565832226136128322261361713222613613532226136136322401591601720", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 2, + "13": 32, + "14": 64, + "15": 32, + "16": 129, + "17": 4, + "2097152": 83, + "2097153": 116, + "2097154": 114, + "2097155": 105, + "2097156": 110, + "2097157": 103, + "2097158": 32, + "2097159": 105, + "2097160": 110, + "2097161": 32, + "2097162": 85, + "2097163": 84, + "2097164": 70, + "2097165": 45, + "2097166": 56, + "2097167": 58, + "2097168": 32, + "2097169": 226, + "2097170": 136, + "2097171": 128, + "2097172": 32, + "2097173": 226, + "2097174": 136, + "2097175": 171, + "2097176": 32, + "2097177": 226, + "2097178": 136, + "2097179": 135, + "2097180": 32, + "2097181": 226, + "2097182": 136, + "2097183": 136, + "2097184": 32, + "2097185": 240, + "2097186": 159, + "2097187": 160, + "2097188": 172, + "23": 12, + "24": 33, + "25": 8, + "27": 1, + "28": 20, + "29": 4, + "3": 1, + "30": 255, + "31": 244, + "32": 3, + "33": 224, + "35": 8, + "4": 60, + "5": 1, + "7": 32, + "8": 52, + "9": 33, + }, + registers: { + "1,at": "0x200000", + "2,v0": "0x1", + "8,t0": "0x200026", + PC: "0xffffffff", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/correct/syscalls/test_mips_syscall_001.s.snap b/tests/arch/__snapshots__/mips/correct/syscalls/test_mips_syscall_001.s.snap new file mode 100644 index 000000000..9d4d8ed5a --- /dev/null +++ b/tests/arch/__snapshots__/mips/correct/syscalls/test_mips_syscall_001.s.snap @@ -0,0 +1,114 @@ +export const snapshot = {}; + +snapshot[`mips/correct/syscalls/test_mips_syscall_001.s 1`] = ` +{ + display: "6673120134-567811416128883", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 2, + "100": 140, + "101": 36, + "107": 12, + "108": 3, + "109": 224, + "11": 12, + "111": 8, + "12": 60, + "13": 1, + "15": 32, + "16": 52, + "17": 33, + "20": 128, + "2097152": 120, + "2097153": 1, + "2097155": 34, + "2097156": 255, + "2097157": 255, + "2097158": 233, + "2097159": 210, + "2097160": 84, + "2097161": 104, + "2097162": 105, + "2097163": 115, + "2097164": 32, + "2097165": 105, + "2097166": 115, + "2097167": 32, + "2097168": 97, + "2097169": 110, + "2097170": 111, + "2097171": 116, + "2097172": 104, + "2097173": 101, + "2097174": 114, + "2097175": 32, + "2097176": 115, + "2097177": 116, + "2097178": 114, + "2097179": 105, + "2097180": 110, + "2097181": 103, + "21": 36, + "27": 12, + "28": 32, + "29": 8, + "3": 1, + "31": 4, + "32": 60, + "33": 1, + "35": 32, + "36": 52, + "37": 33, + "4": 32, + "41": 32, + "42": 72, + "43": 32, + "44": 129, + "45": 36, + "47": 1, + "5": 4, + "51": 12, + "52": 60, + "53": 1, + "55": 32, + "56": 52, + "57": 33, + "59": 2, + "6": 26, + "60": 132, + "61": 36, + "67": 12, + "68": 60, + "69": 1, + "7": 17, + "71": 32, + "72": 52, + "73": 33, + "75": 4, + "76": 140, + "77": 36, + "83": 12, + "84": 32, + "85": 4, + "87": 1, + "91": 12, + "92": 60, + "93": 1, + "95": 32, + "96": 52, + "97": 33, + "99": 8, + }, + registers: { + "1,at": "0x200008", + "2,v0": "0x1", + "4,a0": "0x54686973", + "8,t0": "0x4", + "9,t1": "0x200000", + PC: "0xffffffff", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/correct/syscalls/test_mips_syscall_002.s.snap b/tests/arch/__snapshots__/mips/correct/syscalls/test_mips_syscall_002.s.snap new file mode 100644 index 000000000..132e5d0ec --- /dev/null +++ b/tests/arch/__snapshots__/mips/correct/syscalls/test_mips_syscall_002.s.snap @@ -0,0 +1,59 @@ +export const snapshot = {}; + +snapshot[`mips/correct/syscalls/test_mips_syscall_002.s 1`] = ` +{ + display: "6673-86.97399902343751.100000023841858", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 2, + "10": 136, + "12": 68, + "13": 129, + "14": 96, + "19": 12, + "20": 60, + "21": 1, + "22": 194, + "23": 173, + "24": 52, + "25": 33, + "26": 242, + "27": 176, + "28": 68, + "29": 129, + "3": 2, + "30": 96, + "35": 12, + "36": 60, + "37": 1, + "38": 63, + "39": 140, + "4": 60, + "40": 52, + "41": 33, + "42": 204, + "43": 205, + "44": 68, + "45": 129, + "46": 96, + "5": 1, + "51": 12, + "52": 3, + "53": 224, + "55": 8, + "6": 69, + "7": 208, + "8": 52, + "9": 33, + }, + registers: { + "1,at": "0x3f8ccccd", + "2,v0": "0x2", + "f12,FP12": "0x3f8ccccd", + PC: "0xffffffff", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/correct/syscalls/test_mips_syscall_003.s.snap b/tests/arch/__snapshots__/mips/correct/syscalls/test_mips_syscall_003.s.snap new file mode 100644 index 000000000..d58147cdc --- /dev/null +++ b/tests/arch/__snapshots__/mips/correct/syscalls/test_mips_syscall_003.s.snap @@ -0,0 +1,89 @@ +export const snapshot = {}; + +snapshot[`mips/correct/syscalls/test_mips_syscall_003.s 1`] = ` +{ + display: "6673-86.9741.1", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 2, + "12": 68, + "13": 129, + "14": 104, + "16": 60, + "17": 1, + "18": 64, + "19": 186, + "20": 52, + "21": 33, + "22": 17, + "24": 68, + "25": 129, + "26": 96, + "3": 3, + "31": 12, + "32": 60, + "33": 1, + "34": 4, + "35": 24, + "36": 52, + "37": 33, + "38": 147, + "39": 117, + "4": 60, + "40": 68, + "41": 129, + "42": 104, + "44": 60, + "45": 1, + "46": 192, + "47": 85, + "48": 52, + "49": 33, + "5": 1, + "50": 190, + "51": 86, + "52": 68, + "53": 129, + "54": 96, + "59": 12, + "60": 60, + "61": 1, + "62": 153, + "63": 153, + "64": 52, + "65": 33, + "66": 153, + "67": 154, + "68": 68, + "69": 129, + "70": 104, + "72": 60, + "73": 1, + "74": 63, + "75": 241, + "76": 52, + "77": 33, + "78": 153, + "79": 153, + "8": 52, + "80": 68, + "81": 129, + "82": 96, + "87": 12, + "88": 3, + "89": 224, + "9": 33, + "91": 8, + }, + registers: { + "1,at": "0x3ff19999", + "2,v0": "0x3", + "f12,FP12": "0x3ff19999", + PC: "0xffffffff", + f13: "0x9999999a", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/correct/syscalls/test_mips_syscall_004.s.snap b/tests/arch/__snapshots__/mips/correct/syscalls/test_mips_syscall_004.s.snap new file mode 100644 index 000000000..4264ac178 --- /dev/null +++ b/tests/arch/__snapshots__/mips/correct/syscalls/test_mips_syscall_004.s.snap @@ -0,0 +1,87 @@ +export const snapshot = {}; + +snapshot[`mips/correct/syscalls/test_mips_syscall_004.s 1`] = ` +{ + display: "First StringSecond Stringaa +", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 2, + "13": 32, + "14": 32, + "15": 32, + "19": 12, + "20": 60, + "2097152": 70, + "2097153": 105, + "2097154": 114, + "2097155": 115, + "2097156": 116, + "2097157": 32, + "2097158": 83, + "2097159": 116, + "2097160": 114, + "2097161": 105, + "2097162": 110, + "2097163": 103, + "2097165": 83, + "2097166": 101, + "2097167": 99, + "2097168": 111, + "2097169": 110, + "2097170": 100, + "2097171": 32, + "2097172": 83, + "2097173": 116, + "2097174": 114, + "2097175": 105, + "2097176": 110, + "2097177": 103, + "2097178": 97, + "21": 1, + "23": 32, + "24": 52, + "25": 33, + "27": 13, + "29": 32, + "3": 4, + "30": 32, + "31": 32, + "35": 12, + "36": 60, + "37": 1, + "39": 32, + "4": 60, + "40": 52, + "41": 33, + "43": 26, + "45": 32, + "46": 32, + "47": 32, + "5": 1, + "51": 12, + "52": 32, + "53": 4, + "55": 10, + "56": 32, + "57": 2, + "59": 11, + "63": 12, + "64": 3, + "65": 224, + "67": 8, + "7": 32, + "8": 52, + "9": 33, + }, + registers: { + "1,at": "0x20001a", + "2,v0": "0xb", + "4,a0": "0xa", + PC: "0xffffffff", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/correct/syscalls/test_mips_syscall_005.s.snap b/tests/arch/__snapshots__/mips/correct/syscalls/test_mips_syscall_005.s.snap new file mode 100644 index 000000000..41ba70e46 --- /dev/null +++ b/tests/arch/__snapshots__/mips/correct/syscalls/test_mips_syscall_005.s.snap @@ -0,0 +1,23 @@ +export const snapshot = {}; + +snapshot[`mips/correct/syscalls/test_mips_syscall_005.s 1`] = ` +{ + display: "", + error: false, + keyboard: " 1234567", + memory: { + "0": 32, + "1": 2, + "11": 8, + "3": 5, + "7": 12, + "8": 3, + "9": 224, + }, + registers: { + "2,v0": "0x12d687", + PC: "0xffffffff", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/correct/syscalls/test_mips_syscall_006.s.snap b/tests/arch/__snapshots__/mips/correct/syscalls/test_mips_syscall_006.s.snap new file mode 100644 index 000000000..4ace707da --- /dev/null +++ b/tests/arch/__snapshots__/mips/correct/syscalls/test_mips_syscall_006.s.snap @@ -0,0 +1,24 @@ +export const snapshot = {}; + +snapshot[`mips/correct/syscalls/test_mips_syscall_006.s 1`] = ` +{ + display: "", + error: false, + keyboard: " 1.234567", + memory: { + "0": 32, + "1": 2, + "11": 8, + "3": 6, + "7": 12, + "8": 3, + "9": 224, + }, + registers: { + "2,v0": "0x6", + "f0,FP0": "0x3f9e064b", + PC: "0xffffffff", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/correct/syscalls/test_mips_syscall_008.s.snap b/tests/arch/__snapshots__/mips/correct/syscalls/test_mips_syscall_008.s.snap new file mode 100644 index 000000000..a181eae7b --- /dev/null +++ b/tests/arch/__snapshots__/mips/correct/syscalls/test_mips_syscall_008.s.snap @@ -0,0 +1,43 @@ +export const snapshot = {}; + +snapshot[`mips/correct/syscalls/test_mips_syscall_008.s 1`] = ` +{ + display: "", + error: false, + keyboard: " This is a long string +", + memory: { + "0": 32, + "1": 2, + "13": 32, + "14": 32, + "15": 32, + "16": 32, + "17": 5, + "19": 5, + "2097152": 84, + "2097153": 104, + "2097154": 105, + "2097155": 115, + "2097156": 32, + "23": 12, + "24": 3, + "25": 224, + "27": 8, + "3": 8, + "4": 60, + "5": 1, + "7": 32, + "8": 52, + "9": 33, + }, + registers: { + "1,at": "0x200000", + "2,v0": "0x8", + "4,a0": "0x200000", + "5,a1": "0x5", + PC: "0xffffffff", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/correct/syscalls/test_mips_syscall_010.s.snap b/tests/arch/__snapshots__/mips/correct/syscalls/test_mips_syscall_010.s.snap new file mode 100644 index 000000000..6837374a0 --- /dev/null +++ b/tests/arch/__snapshots__/mips/correct/syscalls/test_mips_syscall_010.s.snap @@ -0,0 +1,27 @@ +export const snapshot = {}; + +snapshot[`mips/correct/syscalls/test_mips_syscall_010.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 2, + "10": 1, + "11": 197, + "12": 3, + "13": 224, + "15": 8, + "3": 10, + "7": 12, + "8": 32, + "9": 8, + }, + registers: { + "2,v0": "0xa", + PC: "0x8", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/correct/syscalls/test_mips_syscall_011.s.snap b/tests/arch/__snapshots__/mips/correct/syscalls/test_mips_syscall_011.s.snap new file mode 100644 index 000000000..ba6c0b63a --- /dev/null +++ b/tests/arch/__snapshots__/mips/correct/syscalls/test_mips_syscall_011.s.snap @@ -0,0 +1,27 @@ +export const snapshot = {}; + +snapshot[`mips/correct/syscalls/test_mips_syscall_011.s 1`] = ` +{ + display: "c", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 2, + "11": 12, + "12": 3, + "13": 224, + "15": 8, + "3": 11, + "4": 32, + "5": 4, + "7": 99, + }, + registers: { + "2,v0": "0xb", + "4,a0": "0x63", + PC: "0xffffffff", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/correct/syscalls/test_mips_syscall_012.s.snap b/tests/arch/__snapshots__/mips/correct/syscalls/test_mips_syscall_012.s.snap new file mode 100644 index 000000000..4c6defe87 --- /dev/null +++ b/tests/arch/__snapshots__/mips/correct/syscalls/test_mips_syscall_012.s.snap @@ -0,0 +1,23 @@ +export const snapshot = {}; + +snapshot[`mips/correct/syscalls/test_mips_syscall_012.s 1`] = ` +{ + display: "", + error: false, + keyboard: " a", + memory: { + "0": 32, + "1": 2, + "11": 8, + "3": 12, + "7": 12, + "8": 3, + "9": 224, + }, + registers: { + "2,v0": "0x61", + PC: "0xffffffff", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_001.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_001.s.snap new file mode 100644 index 000000000..ce753f488 --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_001.s.snap @@ -0,0 +1,56 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_001.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 8, + "10": 255, + "11": 226, + "13": 32, + "14": 72, + "15": 32, + "16": 32, + "17": 10, + "20": 32, + "21": 11, + "23": 18, + "24": 1, + "25": 40, + "26": 96, + "27": 32, + "28": 1, + "29": 73, + "3": 10, + "30": 104, + "31": 32, + "32": 1, + "33": 106, + "34": 112, + "35": 32, + "36": 3, + "37": 224, + "39": 8, + "4": 60, + "5": 1, + "6": 255, + "7": 255, + "8": 52, + "9": 33, + }, + registers: { + "1,at": "0xffffffe2", + "11,t3": "0x12", + "12,t4": "0xffffffec", + "13,t5": "0xffffffe2", + "14,t6": "0x12", + "8,t0": "0xa", + "9,t1": "0xffffffe2", + PC: "0xffffffff", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_002.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_002.s.snap new file mode 100644 index 000000000..dba5cd9b9 --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_002.s.snap @@ -0,0 +1,36 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_002.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 8, + "10": 1, + "11": 155, + "12": 33, + "13": 75, + "15": 12, + "16": 3, + "17": 224, + "19": 8, + "3": 10, + "4": 33, + "5": 9, + "6": 255, + "7": 226, + "8": 33, + "9": 42, + }, + registers: { + "10,t2": "0x187", + "11,t3": "0x193", + "8,t0": "0xa", + "9,t1": "0xffffffec", + PC: "0xffffffff", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_003.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_003.s.snap new file mode 100644 index 000000000..8ddb7c836 --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_003.s.snap @@ -0,0 +1,66 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_003.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 8, + "10": 252, + "11": 87, + "13": 32, + "14": 72, + "15": 32, + "16": 32, + "17": 10, + "19": 12, + "2": 2, + "20": 60, + "21": 1, + "23": 18, + "24": 52, + "25": 33, + "26": 53, + "27": 21, + "29": 32, + "3": 35, + "30": 88, + "31": 32, + "32": 1, + "33": 136, + "34": 72, + "35": 34, + "36": 1, + "37": 170, + "38": 96, + "39": 34, + "4": 60, + "40": 1, + "41": 203, + "42": 104, + "43": 34, + "44": 3, + "45": 224, + "47": 8, + "5": 1, + "6": 255, + "7": 255, + "8": 52, + "9": 33, + }, + registers: { + "1,at": "0x123515", + "10,t2": "0xc", + "11,t3": "0x123515", + "12,t4": "0x5cc", + "13,t5": "0xfffffa40", + "14,t6": "0x123ad5", + "8,t0": "0x223", + "9,t1": "0xfffffc57", + PC: "0xffffffff", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_004.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_004.s.snap new file mode 100644 index 000000000..27cc3fc15 --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_004.s.snap @@ -0,0 +1,40 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_004.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 60, + "1": 8, + "11": 52, + "12": 60, + "13": 24, + "14": 15, + "15": 240, + "16": 60, + "17": 25, + "19": 2, + "20": 3, + "21": 224, + "23": 8, + "3": 35, + "4": 60, + "5": 14, + "6": 86, + "7": 219, + "8": 60, + "9": 15, + }, + registers: { + "14,t6": "0x56db0000", + "15,t7": "0x340000", + "24,t8": "0xff00000", + "25,t9": "0x20000", + "8,t0": "0x230000", + PC: "0xffffffff", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_005.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_005.s.snap new file mode 100644 index 000000000..906e28f0d --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_005.s.snap @@ -0,0 +1,68 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_005.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 13, + "10": 252, + "11": 87, + "13": 32, + "14": 112, + "15": 32, + "16": 32, + "17": 15, + "19": 12, + "2": 2, + "20": 60, + "21": 1, + "23": 18, + "24": 52, + "25": 33, + "26": 53, + "27": 21, + "29": 32, + "3": 35, + "30": 192, + "31": 32, + "32": 12, + "35": 48, + "36": 3, + "37": 45, + "38": 112, + "39": 34, + "4": 60, + "40": 2, + "41": 47, + "42": 200, + "43": 34, + "44": 2, + "45": 88, + "46": 136, + "47": 34, + "48": 32, + "49": 2, + "5": 1, + "51": 10, + "55": 12, + "6": 255, + "7": 255, + "8": 52, + "9": 33, + }, + registers: { + "1,at": "0x123515", + "13,t5": "0x223", + "14,t6": "0xfffffc57", + "15,t7": "0xc", + "2,v0": "0xa", + "24,t8": "0x123515", + "31,ra": "0x24", + PC: "0x38", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_006.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_006.s.snap new file mode 100644 index 000000000..5eb7c08ff --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_006.s.snap @@ -0,0 +1,73 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_006.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 8, + "10": 252, + "11": 87, + "13": 32, + "14": 72, + "15": 32, + "16": 32, + "17": 10, + "19": 12, + "2": 2, + "20": 60, + "21": 1, + "23": 18, + "24": 52, + "25": 33, + "26": 53, + "27": 21, + "29": 32, + "3": 35, + "30": 88, + "31": 32, + "32": 32, + "33": 24, + "35": 52, + "36": 3, + "38": 96, + "39": 9, + "4": 60, + "40": 1, + "41": 169, + "42": 80, + "43": 34, + "44": 1, + "45": 202, + "46": 88, + "47": 34, + "48": 1, + "49": 235, + "5": 1, + "50": 96, + "51": 34, + "52": 32, + "53": 2, + "55": 10, + "59": 12, + "6": 255, + "7": 255, + "8": 52, + "9": 33, + }, + registers: { + "1,at": "0x123515", + "10,t2": "0xc", + "11,t3": "0x123515", + "12,t4": "0x28", + "2,v0": "0xa", + "24,t8": "0x34", + "8,t0": "0x223", + "9,t1": "0xfffffc57", + PC: "0x3c", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_007.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_007.s.snap new file mode 100644 index 000000000..6f46b2f72 --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_007.s.snap @@ -0,0 +1,71 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_007.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 60, + "1": 1, + "10": 64, + "11": 32, + "12": 32, + "13": 9, + "15": 2, + "16": 32, + "17": 10, + "19": 5, + "20": 60, + "21": 1, + "23": 4, + "24": 52, + "25": 33, + "26": 69, + "27": 98, + "29": 32, + "3": 4, + "30": 88, + "31": 32, + "32": 17, + "33": 104, + "35": 16, + "36": 32, + "37": 14, + "39": 34, + "4": 52, + "40": 32, + "41": 2, + "43": 10, + "47": 12, + "48": 32, + "49": 12, + "5": 33, + "51": 11, + "52": 32, + "53": 13, + "54": 2, + "55": 43, + "56": 17, + "57": 8, + "58": 255, + "59": 236, + "6": 69, + "7": 98, + "9": 32, + }, + registers: { + "1,at": "0x44562", + "10,t2": "0x5", + "11,t3": "0x44562", + "12,t4": "0xb", + "13,t5": "0x22b", + "14,t6": "0x22", + "2,v0": "0xa", + "8,t0": "0x44562", + "9,t1": "0x2", + PC: "0x30", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_008.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_008.s.snap new file mode 100644 index 000000000..8658cac21 --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_008.s.snap @@ -0,0 +1,72 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_008.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 60, + "1": 1, + "10": 64, + "11": 32, + "12": 32, + "13": 9, + "15": 2, + "16": 32, + "17": 10, + "19": 5, + "20": 60, + "21": 1, + "23": 4, + "24": 52, + "25": 33, + "26": 69, + "27": 98, + "29": 32, + "3": 4, + "30": 88, + "31": 32, + "32": 21, + "33": 10, + "35": 16, + "36": 32, + "37": 14, + "39": 34, + "4": 52, + "40": 32, + "41": 2, + "43": 10, + "47": 12, + "48": 32, + "49": 12, + "5": 33, + "50": 7, + "51": 84, + "52": 32, + "53": 13, + "54": 2, + "55": 43, + "56": 21, + "57": 72, + "58": 255, + "59": 236, + "6": 69, + "7": 98, + "9": 32, + }, + registers: { + "1,at": "0x44562", + "10,t2": "0x5", + "11,t3": "0x44562", + "12,t4": "0x754", + "13,t5": "0x22b", + "14,t6": "0x22", + "2,v0": "0xa", + "8,t0": "0x44562", + "9,t1": "0x2", + PC: "0x30", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_009.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_009.s.snap new file mode 100644 index 000000000..1d0ade045 --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_009.s.snap @@ -0,0 +1,80 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_009.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 8, + "11": 5, + "12": 60, + "13": 1, + "15": 4, + "16": 52, + "17": 33, + "18": 69, + "19": 98, + "2": 1, + "21": 32, + "22": 88, + "23": 32, + "24": 1, + "25": 10, + "26": 8, + "27": 42, + "28": 20, + "29": 1, + "3": 105, + "31": 24, + "32": 1, + "33": 40, + "34": 8, + "35": 42, + "36": 20, + "37": 1, + "39": 16, + "4": 32, + "40": 32, + "41": 14, + "43": 34, + "44": 32, + "45": 2, + "47": 10, + "5": 9, + "51": 12, + "52": 32, + "53": 12, + "55": 11, + "56": 32, + "57": 13, + "58": 2, + "59": 43, + "60": 1, + "61": 141, + "62": 8, + "63": 42, + "64": 20, + "65": 1, + "66": 255, + "67": 232, + "7": 2, + "8": 32, + "9": 10, + }, + registers: { + "1,at": "0x1", + "10,t2": "0x5", + "11,t3": "0x44562", + "12,t4": "0xb", + "13,t5": "0x22b", + "14,t6": "0x22", + "2,v0": "0xa", + "8,t0": "0x169", + "9,t1": "0x2", + PC: "0x34", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_010.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_010.s.snap new file mode 100644 index 000000000..32ea81a2b --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_010.s.snap @@ -0,0 +1,80 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_010.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 8, + "11": 5, + "12": 60, + "13": 1, + "15": 4, + "16": 52, + "17": 33, + "18": 69, + "19": 98, + "2": 1, + "21": 32, + "22": 88, + "23": 32, + "24": 1, + "25": 11, + "26": 8, + "27": 42, + "28": 16, + "29": 1, + "3": 105, + "31": 24, + "32": 1, + "33": 104, + "34": 8, + "35": 42, + "36": 16, + "37": 1, + "39": 16, + "4": 32, + "40": 32, + "41": 14, + "43": 34, + "44": 32, + "45": 2, + "47": 10, + "5": 9, + "51": 12, + "52": 32, + "53": 12, + "54": 7, + "55": 84, + "56": 32, + "57": 13, + "58": 2, + "59": 43, + "60": 1, + "61": 141, + "62": 8, + "63": 42, + "64": 16, + "65": 1, + "66": 255, + "67": 232, + "7": 2, + "8": 32, + "9": 10, + }, + registers: { + "10,t2": "0x5", + "11,t3": "0x44562", + "12,t4": "0x754", + "13,t5": "0x22b", + "14,t6": "0x22", + "2,v0": "0xa", + "8,t0": "0x169", + "9,t1": "0x2", + PC: "0x34", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_011.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_011.s.snap new file mode 100644 index 000000000..84df901c2 --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_011.s.snap @@ -0,0 +1,81 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_011.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 8, + "11": 5, + "12": 60, + "13": 1, + "15": 4, + "16": 52, + "17": 33, + "18": 69, + "19": 98, + "2": 1, + "21": 32, + "22": 88, + "23": 32, + "24": 1, + "25": 10, + "26": 8, + "27": 43, + "28": 20, + "29": 1, + "3": 105, + "31": 24, + "32": 1, + "33": 40, + "34": 8, + "35": 43, + "36": 20, + "37": 1, + "39": 16, + "4": 32, + "40": 32, + "41": 14, + "43": 34, + "44": 32, + "45": 2, + "47": 10, + "5": 9, + "51": 12, + "52": 32, + "53": 12, + "54": 7, + "55": 84, + "56": 32, + "57": 13, + "58": 2, + "59": 43, + "60": 1, + "61": 172, + "62": 8, + "63": 43, + "64": 20, + "65": 1, + "66": 255, + "67": 232, + "7": 2, + "8": 32, + "9": 10, + }, + registers: { + "1,at": "0x1", + "10,t2": "0x5", + "11,t3": "0x44562", + "12,t4": "0x754", + "13,t5": "0x22b", + "14,t6": "0x22", + "2,v0": "0xa", + "8,t0": "0x169", + "9,t1": "0x2", + PC: "0x34", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_012.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_012.s.snap new file mode 100644 index 000000000..5e91a5ec5 --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_012.s.snap @@ -0,0 +1,80 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_012.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 8, + "11": 5, + "12": 60, + "13": 1, + "15": 4, + "16": 52, + "17": 33, + "18": 69, + "19": 98, + "2": 1, + "21": 32, + "22": 88, + "23": 32, + "24": 1, + "25": 11, + "26": 8, + "27": 43, + "28": 16, + "29": 1, + "3": 105, + "31": 24, + "32": 1, + "33": 106, + "34": 8, + "35": 43, + "36": 16, + "37": 1, + "39": 16, + "4": 32, + "40": 32, + "41": 14, + "43": 34, + "44": 32, + "45": 2, + "47": 10, + "5": 9, + "51": 12, + "52": 32, + "53": 12, + "54": 7, + "55": 84, + "56": 32, + "57": 13, + "58": 2, + "59": 43, + "60": 1, + "61": 141, + "62": 8, + "63": 43, + "64": 16, + "65": 1, + "66": 255, + "67": 232, + "7": 2, + "8": 32, + "9": 10, + }, + registers: { + "10,t2": "0x5", + "11,t3": "0x44562", + "12,t4": "0x754", + "13,t5": "0x22b", + "14,t6": "0x22", + "2,v0": "0xa", + "8,t0": "0x169", + "9,t1": "0x2", + PC: "0x34", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_013.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_013.s.snap new file mode 100644 index 000000000..c2afafd66 --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_013.s.snap @@ -0,0 +1,125 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_013.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 60, + "1": 1, + "10": 64, + "100": 60, + "101": 1, + "103": 32, + "104": 52, + "105": 33, + "107": 12, + "109": 32, + "11": 32, + "110": 200, + "111": 32, + "112": 163, + "113": 45, + "116": 60, + "117": 1, + "119": 32, + "12": 60, + "120": 52, + "121": 33, + "123": 14, + "125": 32, + "126": 200, + "127": 32, + "128": 167, + "129": 47, + "13": 1, + "132": 3, + "133": 224, + "135": 8, + "15": 32, + "16": 52, + "17": 33, + "19": 4, + "2097155": 14, + "2097156": 127, + "2097158": 127, + "2097159": 255, + "2097163": 14, + "2097164": 127, + "2097166": 127, + "2097167": 255, + "21": 32, + "22": 72, + "23": 32, + "24": 60, + "25": 1, + "27": 32, + "28": 52, + "29": 33, + "3": 32, + "31": 6, + "33": 32, + "34": 80, + "35": 32, + "36": 141, + "37": 11, + "4": 52, + "40": 60, + "41": 1, + "43": 32, + "44": 52, + "45": 33, + "48": 140, + "49": 44, + "5": 33, + "52": 129, + "53": 45, + "56": 60, + "57": 1, + "59": 32, + "60": 52, + "61": 33, + "63": 4, + "64": 144, + "65": 46, + "68": 133, + "69": 79, + "72": 60, + "73": 1, + "75": 32, + "76": 52, + "77": 33, + "79": 6, + "80": 148, + "81": 56, + "84": 60, + "85": 1, + "87": 32, + "88": 52, + "89": 33, + "9": 32, + "91": 8, + "93": 32, + "94": 200, + "95": 32, + "96": 175, + "97": 43, + }, + registers: { + "1,at": "0x20000e", + "10,t2": "0x200006", + "11,t3": "0xe", + "12,t4": "0xe", + "13,t5": "0x7f", + "14,t6": "0x7f", + "15,t7": "0x7fff", + "24,t8": "0x7fff", + "25,t9": "0x20000e", + "8,t0": "0x200000", + "9,t1": "0x200004", + PC: "0xffffffff", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_014.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_014.s.snap new file mode 100644 index 000000000..ad613abdf --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_014.s.snap @@ -0,0 +1,71 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_014.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 60, + "1": 1, + "10": 64, + "11": 32, + "12": 60, + "13": 1, + "15": 32, + "16": 52, + "17": 33, + "19": 2, + "2097152": 127, + "2097154": 255, + "2097155": 255, + "21": 32, + "22": 72, + "23": 32, + "24": 145, + "25": 10, + "28": 149, + "29": 43, + "3": 32, + "32": 60, + "33": 1, + "35": 32, + "36": 52, + "37": 33, + "39": 4, + "4": 52, + "41": 32, + "42": 96, + "43": 32, + "44": 161, + "45": 141, + "48": 60, + "49": 1, + "5": 33, + "51": 32, + "52": 52, + "53": 33, + "55": 6, + "57": 32, + "58": 112, + "59": 32, + "60": 165, + "61": 207, + "64": 3, + "65": 224, + "67": 8, + "9": 32, + }, + registers: { + "1,at": "0x200006", + "10,t2": "0x7f", + "11,t3": "0xffff", + "12,t4": "0x200004", + "14,t6": "0x200006", + "8,t0": "0x200000", + "9,t1": "0x200002", + PC: "0xffffffff", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_015.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_015.s.snap new file mode 100644 index 000000000..850ca19f5 --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_015.s.snap @@ -0,0 +1,70 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_015.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 8, + "10": 252, + "13": 32, + "14": 104, + "15": 32, + "16": 41, + "17": 9, + "18": 2, + "19": 239, + "2": 2, + "20": 41, + "21": 10, + "22": 2, + "23": 240, + "24": 41, + "25": 11, + "26": 2, + "27": 241, + "28": 41, + "29": 12, + "3": 240, + "30": 2, + "31": 242, + "32": 41, + "33": 174, + "34": 251, + "35": 255, + "36": 41, + "37": 175, + "38": 252, + "4": 60, + "40": 41, + "41": 184, + "42": 252, + "43": 1, + "44": 41, + "45": 185, + "46": 252, + "47": 2, + "48": 3, + "49": 224, + "5": 1, + "51": 8, + "6": 255, + "7": 255, + "8": 52, + "9": 33, + }, + registers: { + "1,at": "0xfffffc00", + "11,t3": "0x1", + "12,t4": "0x1", + "13,t5": "0xfffffc00", + "24,t8": "0x1", + "25,t9": "0x1", + "8,t0": "0x2f0", + PC: "0xffffffff", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_016.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_016.s.snap new file mode 100644 index 000000000..925eca3aa --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_016.s.snap @@ -0,0 +1,70 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_016.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 8, + "10": 252, + "13": 32, + "14": 104, + "15": 32, + "16": 45, + "17": 9, + "18": 2, + "19": 239, + "2": 2, + "20": 45, + "21": 10, + "22": 2, + "23": 240, + "24": 45, + "25": 11, + "26": 2, + "27": 241, + "28": 45, + "29": 12, + "3": 240, + "30": 2, + "31": 242, + "32": 45, + "33": 174, + "34": 251, + "35": 255, + "36": 45, + "37": 175, + "38": 252, + "4": 60, + "40": 45, + "41": 184, + "42": 252, + "43": 1, + "44": 45, + "45": 185, + "46": 252, + "47": 2, + "48": 3, + "49": 224, + "5": 1, + "51": 8, + "6": 255, + "7": 255, + "8": 52, + "9": 33, + }, + registers: { + "1,at": "0xfffffc00", + "11,t3": "0x1", + "12,t4": "0x1", + "13,t5": "0xfffffc00", + "24,t8": "0x1", + "25,t9": "0x1", + "8,t0": "0x2f0", + PC: "0xffffffff", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_017.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_017.s.snap new file mode 100644 index 000000000..bde27f869 --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_017.s.snap @@ -0,0 +1,62 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_017.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 60, + "1": 1, + "10": 64, + "11": 32, + "12": 32, + "13": 9, + "14": 17, + "15": 215, + "16": 60, + "17": 1, + "18": 255, + "19": 255, + "20": 52, + "21": 33, + "22": 218, + "23": 242, + "25": 32, + "26": 80, + "27": 32, + "28": 57, + "29": 104, + "3": 2, + "30": 4, + "31": 85, + "32": 57, + "33": 137, + "34": 2, + "35": 34, + "36": 57, + "37": 170, + "38": 15, + "39": 255, + "4": 52, + "40": 3, + "41": 224, + "43": 8, + "5": 33, + "6": 35, + "7": 70, + "9": 32, + }, + registers: { + "1,at": "0xffffdaf2", + "10,t2": "0xffffdaf2", + "11,t3": "0x22713", + "12,t4": "0x13f5", + "13,t5": "0xffffd50d", + "8,t0": "0x22346", + "9,t1": "0x11d7", + PC: "0xffffffff", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_018.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_018.s.snap new file mode 100644 index 000000000..de1b4a071 --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_018.s.snap @@ -0,0 +1,62 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_018.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 60, + "1": 1, + "10": 64, + "11": 32, + "12": 32, + "13": 9, + "14": 17, + "15": 215, + "16": 60, + "17": 1, + "18": 255, + "19": 255, + "20": 52, + "21": 33, + "22": 218, + "23": 242, + "25": 32, + "26": 80, + "27": 32, + "28": 53, + "29": 104, + "3": 2, + "30": 4, + "31": 85, + "32": 53, + "33": 137, + "34": 2, + "35": 34, + "36": 53, + "37": 170, + "38": 15, + "39": 255, + "4": 52, + "40": 3, + "41": 224, + "43": 8, + "5": 33, + "6": 35, + "7": 70, + "9": 32, + }, + registers: { + "1,at": "0xffffdaf2", + "10,t2": "0xffffdaf2", + "11,t3": "0x22757", + "12,t4": "0x13f7", + "13,t5": "0xffffdfff", + "8,t0": "0x22346", + "9,t1": "0x11d7", + PC: "0xffffffff", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_019.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_019.s.snap new file mode 100644 index 000000000..3a78f89f0 --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_019.s.snap @@ -0,0 +1,62 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_019.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 60, + "1": 1, + "10": 64, + "11": 32, + "12": 32, + "13": 9, + "14": 17, + "15": 215, + "16": 60, + "17": 1, + "18": 255, + "19": 255, + "20": 52, + "21": 33, + "22": 218, + "23": 242, + "25": 32, + "26": 80, + "27": 32, + "28": 49, + "29": 11, + "3": 2, + "30": 4, + "31": 85, + "32": 49, + "33": 44, + "34": 2, + "35": 34, + "36": 49, + "37": 77, + "38": 15, + "39": 255, + "4": 52, + "40": 3, + "41": 224, + "43": 8, + "5": 33, + "6": 35, + "7": 70, + "9": 32, + }, + registers: { + "1,at": "0xffffdaf2", + "10,t2": "0xffffdaf2", + "11,t3": "0x44", + "12,t4": "0x2", + "13,t5": "0xaf2", + "8,t0": "0x22346", + "9,t1": "0x11d7", + PC: "0xffffffff", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_020.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_020.s.snap new file mode 100644 index 000000000..2dc28abe2 --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_020.s.snap @@ -0,0 +1,55 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_020.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 8, + "10": 255, + "11": 255, + "12": 52, + "13": 33, + "14": 224, + "17": 32, + "18": 80, + "19": 32, + "20": 32, + "21": 11, + "23": 24, + "24": 1, + "25": 72, + "27": 26, + "28": 1, + "29": 40, + "3": 16, + "31": 26, + "32": 1, + "33": 75, + "35": 26, + "36": 1, + "37": 106, + "39": 26, + "4": 32, + "40": 3, + "41": 224, + "43": 8, + "5": 9, + "6": 1, + "8": 60, + "9": 1, + }, + registers: { + "1,at": "0xffffe000", + "10,t2": "0xffffe000", + "11,t3": "0x18", + "8,t0": "0x10", + "9,t1": "0x100", + HI: "0x18", + PC: "0xffffffff", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_021.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_021.s.snap new file mode 100644 index 000000000..2190af87d --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_021.s.snap @@ -0,0 +1,55 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_021.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 8, + "10": 255, + "11": 255, + "12": 52, + "13": 33, + "14": 224, + "17": 32, + "18": 80, + "19": 32, + "20": 32, + "21": 11, + "23": 24, + "24": 1, + "25": 72, + "27": 27, + "28": 1, + "29": 40, + "3": 16, + "31": 27, + "32": 1, + "33": 75, + "35": 27, + "36": 1, + "37": 106, + "39": 27, + "4": 32, + "40": 3, + "41": 224, + "43": 8, + "5": 9, + "6": 1, + "8": 60, + "9": 1, + }, + registers: { + "1,at": "0xffffe000", + "10,t2": "0xffffe000", + "11,t3": "0x18", + "8,t0": "0x10", + "9,t1": "0x100", + HI: "0x18", + PC: "0xffffffff", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_022.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_022.s.snap new file mode 100644 index 000000000..c8c481e4e --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_022.s.snap @@ -0,0 +1,58 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_022.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 60, + "1": 1, + "10": 64, + "11": 32, + "12": 32, + "13": 9, + "14": 17, + "15": 215, + "16": 60, + "17": 1, + "18": 255, + "19": 255, + "20": 52, + "21": 33, + "22": 218, + "23": 242, + "25": 32, + "26": 80, + "27": 32, + "29": 40, + "30": 88, + "31": 130, + "33": 41, + "34": 97, + "35": 2, + "37": 42, + "38": 107, + "39": 194, + "4": 52, + "40": 3, + "41": 224, + "43": 8, + "5": 33, + "6": 170, + "7": 212, + "9": 32, + }, + registers: { + "1,at": "0xffffdaf2", + "10,t2": "0xffffdaf2", + "11,t3": "0x2ab5", + "12,t4": "0x7000011d", + "13,t5": "0xb5e5ffff", + "8,t0": "0xaad4", + "9,t1": "0x11d7", + PC: "0xffffffff", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_023.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_023.s.snap new file mode 100644 index 000000000..85876f8bf --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_023.s.snap @@ -0,0 +1,58 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_023.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 60, + "1": 1, + "10": 64, + "11": 32, + "12": 32, + "13": 9, + "14": 17, + "15": 215, + "16": 60, + "17": 1, + "18": 255, + "19": 255, + "20": 52, + "21": 33, + "22": 218, + "23": 242, + "25": 32, + "26": 80, + "27": 32, + "29": 8, + "30": 88, + "31": 191, + "33": 9, + "34": 97, + "35": 63, + "37": 10, + "38": 107, + "39": 255, + "4": 52, + "40": 3, + "41": 224, + "43": 8, + "5": 33, + "6": 170, + "7": 212, + "9": 32, + }, + registers: { + "1,at": "0xffffdaf2", + "10,t2": "0xffffdaf2", + "11,t3": "0x2ab50", + "12,t4": "0x11d70", + "13,t5": "0xed790000", + "8,t0": "0xaad4", + "9,t1": "0x11d7", + PC: "0xffffffff", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_024.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_024.s.snap new file mode 100644 index 000000000..ca1acc358 --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_024.s.snap @@ -0,0 +1,55 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_024.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 8, + "10": 32, + "11": 1, + "12": 32, + "13": 11, + "14": 32, + "15": 2, + "16": 1, + "17": 40, + "18": 96, + "19": 42, + "2": 31, + "20": 1, + "21": 41, + "22": 104, + "23": 42, + "24": 1, + "25": 42, + "26": 112, + "27": 42, + "28": 1, + "29": 43, + "3": 255, + "30": 120, + "31": 42, + "32": 3, + "33": 224, + "35": 8, + "4": 32, + "5": 9, + "6": 32, + "8": 32, + "9": 10, + }, + registers: { + "10,t2": "0x2001", + "11,t3": "0x2002", + "14,t6": "0x1", + "15,t7": "0x1", + "8,t0": "0x1fff", + "9,t1": "0x2000", + PC: "0xffffffff", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_025.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_025.s.snap new file mode 100644 index 000000000..15ffb81c0 --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_025.s.snap @@ -0,0 +1,55 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_025.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 8, + "10": 32, + "11": 1, + "12": 32, + "13": 11, + "14": 32, + "15": 2, + "16": 1, + "17": 40, + "18": 96, + "19": 43, + "2": 31, + "20": 1, + "21": 41, + "22": 104, + "23": 43, + "24": 1, + "25": 42, + "26": 112, + "27": 43, + "28": 1, + "29": 43, + "3": 255, + "30": 120, + "31": 43, + "32": 3, + "33": 224, + "35": 8, + "4": 32, + "5": 9, + "6": 32, + "8": 32, + "9": 10, + }, + registers: { + "10,t2": "0x2001", + "11,t3": "0x2002", + "14,t6": "0x1", + "15,t7": "0x1", + "8,t0": "0x1fff", + "9,t1": "0x2000", + PC: "0xffffffff", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_026.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_026.s.snap new file mode 100644 index 000000000..1a616168a --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_026.s.snap @@ -0,0 +1,77 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_026.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 60, + "1": 1, + "10": 64, + "11": 32, + "12": 32, + "13": 9, + "14": 17, + "15": 215, + "16": 60, + "17": 1, + "18": 255, + "19": 255, + "20": 52, + "21": 33, + "22": 218, + "23": 242, + "25": 32, + "26": 80, + "27": 32, + "28": 32, + "29": 11, + "3": 2, + "30": 4, + "31": 85, + "32": 32, + "33": 12, + "34": 2, + "35": 34, + "36": 32, + "37": 13, + "38": 15, + "39": 255, + "4": 52, + "40": 1, + "41": 200, + "42": 88, + "43": 38, + "44": 1, + "45": 233, + "46": 96, + "47": 38, + "48": 3, + "49": 10, + "5": 33, + "50": 104, + "51": 38, + "52": 3, + "53": 224, + "55": 8, + "6": 35, + "7": 70, + "9": 32, + }, + registers: { + "1,at": "0xffffdaf2", + "10,t2": "0xffffdaf2", + "11,t3": "0x455", + "12,t4": "0x222", + "13,t5": "0xfff", + "14,t6": "0x22713", + "15,t7": "0x13f5", + "24,t8": "0xffffd50d", + "8,t0": "0x22346", + "9,t1": "0x11d7", + PC: "0xffffffff", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_027.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_027.s.snap new file mode 100644 index 000000000..82f6dfb1e --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_027.s.snap @@ -0,0 +1,58 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_027.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 60, + "1": 1, + "10": 64, + "11": 32, + "12": 32, + "13": 9, + "14": 17, + "15": 215, + "16": 60, + "17": 1, + "18": 255, + "19": 255, + "20": 52, + "21": 33, + "22": 218, + "23": 242, + "25": 32, + "26": 80, + "27": 32, + "29": 8, + "30": 88, + "31": 130, + "33": 9, + "34": 97, + "35": 2, + "37": 10, + "38": 107, + "39": 194, + "4": 52, + "40": 3, + "41": 224, + "43": 8, + "5": 33, + "6": 170, + "7": 212, + "9": 32, + }, + registers: { + "1,at": "0xffffdaf2", + "10,t2": "0xffffdaf2", + "11,t3": "0x2ab5", + "12,t4": "0x11d", + "13,t5": "0x1ffff", + "8,t0": "0xaad4", + "9,t1": "0x11d7", + PC: "0xffffffff", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_028.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_028.s.snap new file mode 100644 index 000000000..5089860e6 --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_028.s.snap @@ -0,0 +1,58 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_028.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 60, + "1": 1, + "10": 64, + "11": 32, + "12": 32, + "13": 9, + "14": 17, + "15": 215, + "16": 60, + "17": 1, + "18": 255, + "19": 255, + "20": 52, + "21": 33, + "22": 218, + "23": 242, + "25": 32, + "26": 80, + "27": 32, + "29": 8, + "30": 88, + "31": 131, + "33": 9, + "34": 97, + "35": 3, + "37": 10, + "38": 107, + "39": 195, + "4": 52, + "40": 3, + "41": 224, + "43": 8, + "5": 33, + "6": 170, + "7": 212, + "9": 32, + }, + registers: { + "1,at": "0xffffdaf2", + "10,t2": "0xffffdaf2", + "11,t3": "0x2ab5", + "12,t4": "0x11d", + "13,t5": "0xffffffff", + "8,t0": "0xaad4", + "9,t1": "0x11d7", + PC: "0xffffffff", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_029.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_029.s.snap new file mode 100644 index 000000000..cc0bc1ae8 --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_029.s.snap @@ -0,0 +1,77 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_029.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 60, + "1": 1, + "10": 64, + "11": 32, + "12": 32, + "13": 9, + "14": 17, + "15": 215, + "16": 60, + "17": 1, + "18": 255, + "19": 255, + "20": 52, + "21": 33, + "22": 218, + "23": 242, + "25": 32, + "26": 80, + "27": 32, + "28": 32, + "29": 11, + "3": 2, + "30": 4, + "31": 85, + "32": 32, + "33": 12, + "34": 2, + "35": 34, + "36": 32, + "37": 13, + "38": 15, + "39": 255, + "4": 52, + "40": 1, + "41": 200, + "42": 88, + "43": 37, + "44": 1, + "45": 233, + "46": 96, + "47": 37, + "48": 3, + "49": 10, + "5": 33, + "50": 104, + "51": 37, + "52": 3, + "53": 224, + "55": 8, + "6": 35, + "7": 70, + "9": 32, + }, + registers: { + "1,at": "0xffffdaf2", + "10,t2": "0xffffdaf2", + "11,t3": "0x455", + "12,t4": "0x222", + "13,t5": "0xfff", + "14,t6": "0x22757", + "15,t7": "0x13f7", + "24,t8": "0xffffdfff", + "8,t0": "0x22346", + "9,t1": "0x11d7", + PC: "0xffffffff", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_030.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_030.s.snap new file mode 100644 index 000000000..154fbfc68 --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_030.s.snap @@ -0,0 +1,77 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_030.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 60, + "1": 1, + "10": 64, + "11": 32, + "12": 32, + "13": 9, + "14": 17, + "15": 215, + "16": 60, + "17": 1, + "18": 255, + "19": 255, + "20": 52, + "21": 33, + "22": 218, + "23": 242, + "25": 32, + "26": 80, + "27": 32, + "28": 32, + "29": 11, + "3": 2, + "30": 4, + "31": 85, + "32": 32, + "33": 12, + "34": 2, + "35": 34, + "36": 32, + "37": 13, + "38": 15, + "39": 255, + "4": 52, + "40": 1, + "41": 104, + "42": 112, + "43": 36, + "44": 1, + "45": 137, + "46": 120, + "47": 36, + "48": 1, + "49": 170, + "5": 33, + "50": 192, + "51": 36, + "52": 3, + "53": 224, + "55": 8, + "6": 35, + "7": 70, + "9": 32, + }, + registers: { + "1,at": "0xffffdaf2", + "10,t2": "0xffffdaf2", + "11,t3": "0x455", + "12,t4": "0x222", + "13,t5": "0xfff", + "14,t6": "0x44", + "15,t7": "0x2", + "24,t8": "0xaf2", + "8,t0": "0x22346", + "9,t1": "0x11d7", + PC: "0xffffffff", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_031.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_031.s.snap new file mode 100644 index 000000000..a4b82bd9d --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_031.s.snap @@ -0,0 +1,122 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_031.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 60, + "1": 1, + "10": 64, + "11": 32, + "12": 60, + "13": 1, + "15": 32, + "16": 52, + "17": 33, + "19": 8, + "2097152": 64, + "2097153": 65, + "2097154": 69, + "2097155": 161, + "2097156": 202, + "2097157": 192, + "2097158": 131, + "2097159": 18, + "2097160": 64, + "2097161": 38, + "2097162": 226, + "2097163": 208, + "2097164": 229, + "2097165": 96, + "2097166": 65, + "2097167": 137, + "2097172": 7, + "2097173": 84, + "2097174": 79, + "2097175": 251, + "2097176": 64, + "2097177": 65, + "2097178": 69, + "2097179": 161, + "2097180": 202, + "2097181": 192, + "2097182": 131, + "2097183": 18, + "2097184": 64, + "2097185": 38, + "2097186": 226, + "2097187": 208, + "2097188": 229, + "2097189": 96, + "2097190": 65, + "2097191": 137, + "2097196": 7, + "2097197": 84, + "2097198": 79, + "2097199": 251, + "21": 32, + "22": 72, + "23": 32, + "24": 60, + "25": 1, + "27": 32, + "28": 52, + "29": 33, + "3": 32, + "31": 16, + "33": 32, + "34": 80, + "35": 32, + "36": 60, + "37": 1, + "39": 32, + "4": 52, + "40": 52, + "41": 33, + "43": 24, + "45": 32, + "46": 88, + "47": 32, + "48": 213, + "5": 33, + "52": 213, + "53": 34, + "56": 213, + "57": 68, + "60": 245, + "61": 96, + "64": 33, + "65": 107, + "67": 8, + "68": 245, + "69": 98, + "72": 33, + "73": 107, + "75": 8, + "76": 245, + "77": 100, + "80": 32, + "81": 2, + "83": 10, + "87": 12, + "9": 32, + }, + registers: { + "1,at": "0x200018", + "10,t2": "0x200010", + "11,t3": "0x200028", + "2,v0": "0xa", + "8,t0": "0x200000", + "9,t1": "0x200008", + "f0,FP0": "0x404145a1", + "f2,FP2": "0x4026e2d0", + PC: "0x58", + f1: "0xcac08312", + f3: "0xe5604189", + f5: "0x7544ffb", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_032.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_032.s.snap new file mode 100644 index 000000000..1a48cccd9 --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_032.s.snap @@ -0,0 +1,71 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_032.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 8, + "11": 45, + "12": 60, + "13": 1, + "14": 255, + "15": 255, + "16": 52, + "17": 33, + "18": 255, + "19": 254, + "21": 32, + "22": 88, + "23": 32, + "24": 1, + "25": 40, + "27": 24, + "3": 10, + "30": 128, + "31": 16, + "34": 136, + "35": 18, + "36": 1, + "37": 73, + "39": 24, + "4": 32, + "42": 144, + "43": 16, + "46": 152, + "47": 18, + "48": 1, + "49": 106, + "5": 9, + "51": 24, + "54": 160, + "55": 16, + "58": 168, + "59": 18, + "60": 1, + "61": 139, + "63": 24, + "64": 3, + "65": 224, + "67": 8, + "7": 13, + "8": 32, + "9": 10, + }, + registers: { + "1,at": "0xfffffffe", + "10,t2": "0x2d", + "11,t3": "0xfffffffe", + "17,s1": "0x82", + "19,s3": "0x249", + "20,s4": "0xffffffff", + "21,s5": "0xffffffa6", + "8,t0": "0xa", + "9,t1": "0xd", + PC: "0xffffffff", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_034.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_034.s.snap new file mode 100644 index 000000000..c6580c8f9 --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_034.s.snap @@ -0,0 +1,63 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_034.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 8, + "11": 45, + "12": 60, + "13": 1, + "14": 255, + "15": 255, + "16": 52, + "17": 33, + "18": 255, + "19": 254, + "21": 32, + "22": 88, + "23": 32, + "24": 113, + "25": 136, + "26": 72, + "27": 2, + "28": 113, + "29": 169, + "3": 10, + "30": 80, + "31": 2, + "32": 113, + "33": 202, + "34": 88, + "35": 2, + "36": 113, + "37": 235, + "38": 96, + "39": 2, + "4": 32, + "40": 3, + "41": 224, + "43": 8, + "5": 9, + "7": 13, + "8": 32, + "9": 10, + }, + registers: { + "1,at": "0xfffffffe", + "10,t2": "0x2d", + "11,t3": "0xfffffffe", + "12,t4": "0x82", + "13,t5": "0x249", + "14,t6": "0xffffffa6", + "15,t7": "0xfffffefc", + "8,t0": "0xa", + "9,t1": "0xd", + PC: "0xffffffff", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_035.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_035.s.snap new file mode 100644 index 000000000..5c3617f1d --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_035.s.snap @@ -0,0 +1,78 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_035.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 60, + "1": 1, + "10": 64, + "11": 32, + "12": 32, + "13": 9, + "15": 222, + "16": 60, + "17": 1, + "19": 250, + "2": 1, + "20": 52, + "21": 33, + "22": 187, + "23": 83, + "25": 32, + "26": 80, + "27": 32, + "28": 60, + "29": 1, + "3": 101, + "30": 254, + "31": 154, + "32": 52, + "33": 33, + "34": 17, + "35": 61, + "37": 32, + "38": 88, + "39": 32, + "4": 52, + "40": 1, + "41": 40, + "42": 96, + "43": 33, + "44": 1, + "45": 73, + "46": 104, + "47": 33, + "48": 1, + "49": 106, + "5": 33, + "50": 112, + "51": 33, + "52": 1, + "53": 11, + "54": 120, + "55": 33, + "56": 3, + "57": 224, + "59": 8, + "6": 238, + "7": 184, + "9": 32, + }, + registers: { + "1,at": "0xfe9a113d", + "10,t2": "0xfabb53", + "11,t3": "0xfe9a113d", + "12,t4": "0x165ef96", + "13,t5": "0xfabc31", + "14,t6": "0xff94cc90", + "15,t7": "0xfffffff5", + "8,t0": "0x165eeb8", + "9,t1": "0xde", + PC: "0xffffffff", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_036.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_036.s.snap new file mode 100644 index 000000000..e84c30f5b --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_036.s.snap @@ -0,0 +1,71 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_036.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 8, + "10": 1, + "11": 35, + "12": 60, + "13": 1, + "14": 255, + "15": 255, + "16": 52, + "17": 33, + "18": 169, + "19": 18, + "2": 37, + "21": 32, + "22": 88, + "23": 32, + "24": 37, + "25": 12, + "26": 179, + "27": 56, + "28": 37, + "29": 45, + "3": 184, + "30": 21, + "31": 235, + "32": 37, + "33": 78, + "34": 1, + "35": 36, + "36": 60, + "37": 1, + "39": 3, + "4": 32, + "40": 52, + "41": 33, + "42": 113, + "43": 131, + "45": 43, + "46": 120, + "47": 33, + "48": 3, + "49": 224, + "5": 9, + "51": 8, + "7": 222, + "8": 32, + "9": 10, + }, + registers: { + "1,at": "0x37183", + "10,t2": "0x123", + "11,t3": "0xffffa912", + "12,t4": "0xffffd8f0", + "13,t5": "0x16c9", + "14,t6": "0x247", + "15,t7": "0x31a95", + "8,t0": "0x25b8", + "9,t1": "0xde", + PC: "0xffffffff", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_037.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_037.s.snap new file mode 100644 index 000000000..18128e117 --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_037.s.snap @@ -0,0 +1,71 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_037.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 8, + "11": 45, + "12": 60, + "13": 1, + "14": 255, + "15": 255, + "16": 52, + "17": 33, + "18": 255, + "19": 254, + "21": 32, + "22": 88, + "23": 32, + "24": 1, + "25": 40, + "27": 25, + "3": 10, + "30": 128, + "31": 16, + "34": 136, + "35": 18, + "36": 1, + "37": 73, + "39": 25, + "4": 32, + "42": 144, + "43": 16, + "46": 152, + "47": 18, + "48": 1, + "49": 106, + "5": 9, + "51": 25, + "54": 160, + "55": 16, + "58": 168, + "59": 18, + "60": 1, + "61": 139, + "63": 25, + "64": 3, + "65": 224, + "67": 8, + "7": 13, + "8": 32, + "9": 10, + }, + registers: { + "1,at": "0xfffffffe", + "10,t2": "0x2d", + "11,t3": "0xfffffffe", + "17,s1": "0x82", + "19,s3": "0x249", + "20,s4": "0x2c", + "21,s5": "0xffffffa6", + "8,t0": "0xa", + "9,t1": "0xd", + PC: "0xffffffff", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_038.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_038.s.snap new file mode 100644 index 000000000..a8a07d867 --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_038.s.snap @@ -0,0 +1,61 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_038.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 8, + "10": 255, + "11": 255, + "12": 52, + "13": 33, + "14": 224, + "17": 32, + "18": 80, + "19": 32, + "20": 32, + "21": 11, + "23": 24, + "24": 1, + "25": 72, + "26": 96, + "27": 154, + "28": 1, + "29": 40, + "3": 16, + "30": 104, + "31": 154, + "32": 1, + "33": 75, + "34": 112, + "35": 154, + "36": 1, + "37": 106, + "38": 120, + "39": 154, + "4": 32, + "40": 3, + "41": 224, + "43": 8, + "5": 9, + "6": 1, + "8": 60, + "9": 1, + }, + registers: { + "1,at": "0xffffe000", + "10,t2": "0xffffe000", + "11,t3": "0x18", + "12,t4": "0xfffffe00", + "13,t5": "0x10", + "14,t6": "0xfffffeab", + "8,t0": "0x10", + "9,t1": "0x100", + PC: "0xffffffff", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_039.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_039.s.snap new file mode 100644 index 000000000..07bdc3394 --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_039.s.snap @@ -0,0 +1,61 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_039.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 8, + "10": 255, + "11": 255, + "12": 52, + "13": 33, + "14": 224, + "17": 32, + "18": 80, + "19": 32, + "20": 32, + "21": 11, + "23": 24, + "24": 1, + "25": 72, + "26": 96, + "27": 155, + "28": 1, + "29": 40, + "3": 16, + "30": 104, + "31": 155, + "32": 1, + "33": 75, + "34": 112, + "35": 155, + "36": 1, + "37": 106, + "38": 120, + "39": 155, + "4": 32, + "40": 3, + "41": 224, + "43": 8, + "5": 9, + "6": 1, + "8": 60, + "9": 1, + }, + registers: { + "1,at": "0xffffe000", + "10,t2": "0xffffe000", + "11,t3": "0x18", + "12,t4": "0xffffe00", + "13,t5": "0x10", + "14,t6": "0xaaaa955", + "8,t0": "0x10", + "9,t1": "0x100", + PC: "0xffffffff", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_040.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_040.s.snap new file mode 100644 index 000000000..037fbaad8 --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_040.s.snap @@ -0,0 +1,65 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_040.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 8, + "10": 255, + "11": 255, + "12": 52, + "13": 33, + "14": 224, + "17": 32, + "18": 80, + "19": 32, + "20": 32, + "21": 11, + "23": 24, + "24": 1, + "25": 72, + "27": 26, + "3": 16, + "30": 96, + "31": 16, + "32": 1, + "33": 40, + "35": 26, + "38": 104, + "39": 16, + "4": 32, + "40": 1, + "41": 75, + "43": 26, + "46": 112, + "47": 16, + "48": 1, + "49": 106, + "5": 9, + "51": 26, + "54": 120, + "55": 16, + "56": 3, + "57": 224, + "59": 8, + "6": 1, + "8": 60, + "9": 1, + }, + registers: { + "1,at": "0xffffe000", + "10,t2": "0xffffe000", + "11,t3": "0x18", + "14,t6": "0xfffffff8", + "15,t7": "0x18", + "8,t0": "0x10", + "9,t1": "0x100", + HI: "0x18", + PC: "0xffffffff", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_041.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_041.s.snap new file mode 100644 index 000000000..5003b1dd2 --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_041.s.snap @@ -0,0 +1,60 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_041.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 8, + "10": 255, + "11": 255, + "12": 52, + "13": 33, + "14": 224, + "17": 32, + "18": 80, + "19": 32, + "20": 32, + "21": 11, + "23": 24, + "24": 1, + "25": 72, + "26": 96, + "27": 219, + "28": 1, + "29": 40, + "3": 16, + "30": 104, + "31": 219, + "32": 1, + "33": 75, + "34": 112, + "35": 219, + "36": 1, + "37": 106, + "38": 120, + "39": 219, + "4": 32, + "40": 3, + "41": 224, + "43": 8, + "5": 9, + "6": 1, + "8": 60, + "9": 1, + }, + registers: { + "1,at": "0xffffe000", + "10,t2": "0xffffe000", + "11,t3": "0x18", + "14,t6": "0x8", + "15,t7": "0x18", + "8,t0": "0x10", + "9,t1": "0x100", + PC: "0xffffffff", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_042.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_042.s.snap new file mode 100644 index 000000000..543a522b7 --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_042.s.snap @@ -0,0 +1,75 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_042.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 8, + "11": 5, + "12": 32, + "13": 11, + "14": 2, + "15": 31, + "16": 1, + "17": 9, + "18": 8, + "19": 42, + "2": 3, + "20": 20, + "21": 1, + "23": 24, + "24": 1, + "25": 104, + "26": 8, + "27": 42, + "28": 20, + "29": 1, + "3": 114, + "31": 16, + "32": 32, + "33": 14, + "35": 34, + "36": 32, + "37": 2, + "39": 10, + "4": 32, + "43": 12, + "44": 32, + "45": 12, + "47": 11, + "48": 32, + "49": 13, + "5": 9, + "50": 2, + "51": 43, + "52": 1, + "53": 141, + "54": 8, + "55": 42, + "56": 20, + "57": 1, + "58": 255, + "59": 232, + "6": 3, + "7": 113, + "8": 32, + "9": 10, + }, + registers: { + "1,at": "0x1", + "10,t2": "0x5", + "11,t3": "0x21f", + "12,t4": "0xb", + "13,t5": "0x22b", + "14,t6": "0x22", + "2,v0": "0xa", + "8,t0": "0x372", + "9,t1": "0x371", + PC: "0x2c", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_043.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_043.s.snap new file mode 100644 index 000000000..f20aee26f --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_043.s.snap @@ -0,0 +1,89 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_043.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 60, + "1": 1, + "10": 64, + "11": 32, + "12": 60, + "13": 1, + "14": 255, + "15": 255, + "16": 52, + "17": 33, + "18": 252, + "19": 143, + "2": 255, + "21": 32, + "22": 72, + "23": 32, + "24": 32, + "25": 10, + "27": 5, + "28": 32, + "29": 11, + "3": 255, + "30": 2, + "31": 31, + "32": 1, + "33": 40, + "34": 8, + "35": 43, + "36": 20, + "37": 1, + "39": 24, + "4": 52, + "40": 1, + "41": 75, + "42": 8, + "43": 43, + "44": 20, + "45": 1, + "47": 16, + "48": 32, + "49": 14, + "5": 33, + "51": 34, + "52": 32, + "53": 2, + "55": 10, + "59": 12, + "6": 252, + "60": 32, + "61": 12, + "63": 11, + "64": 32, + "65": 13, + "66": 2, + "67": 43, + "68": 1, + "69": 141, + "7": 142, + "70": 8, + "71": 43, + "72": 20, + "73": 1, + "74": 255, + "75": 232, + "9": 32, + }, + registers: { + "1,at": "0x1", + "10,t2": "0x5", + "11,t3": "0x21f", + "12,t4": "0xb", + "13,t5": "0x22b", + "14,t6": "0x22", + "2,v0": "0xa", + "8,t0": "0xfffffc8e", + "9,t1": "0xfffffc8f", + PC: "0x3c", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_044.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_044.s.snap new file mode 100644 index 000000000..ac7db661b --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_044.s.snap @@ -0,0 +1,74 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_044.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 8, + "11": 5, + "12": 32, + "13": 11, + "14": 2, + "15": 31, + "16": 1, + "17": 40, + "18": 8, + "19": 42, + "2": 3, + "20": 16, + "21": 1, + "23": 24, + "24": 1, + "25": 106, + "26": 8, + "27": 42, + "28": 16, + "29": 1, + "3": 114, + "31": 16, + "32": 32, + "33": 14, + "35": 34, + "36": 32, + "37": 2, + "39": 10, + "4": 32, + "43": 12, + "44": 32, + "45": 12, + "47": 11, + "48": 32, + "49": 13, + "5": 9, + "50": 2, + "51": 43, + "52": 1, + "53": 172, + "54": 8, + "55": 42, + "56": 16, + "57": 1, + "58": 255, + "59": 232, + "6": 3, + "7": 113, + "8": 32, + "9": 10, + }, + registers: { + "10,t2": "0x5", + "11,t3": "0x21f", + "12,t4": "0xb", + "13,t5": "0x22b", + "14,t6": "0x22", + "2,v0": "0xa", + "8,t0": "0x372", + "9,t1": "0x371", + PC: "0x2c", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_045.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_045.s.snap new file mode 100644 index 000000000..d9a0adfac --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_045.s.snap @@ -0,0 +1,102 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_045.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 60, + "1": 1, + "10": 64, + "11": 32, + "12": 60, + "13": 1, + "14": 255, + "15": 255, + "16": 52, + "17": 33, + "18": 252, + "19": 143, + "2": 255, + "21": 32, + "22": 72, + "23": 32, + "24": 32, + "25": 10, + "27": 5, + "28": 60, + "29": 1, + "3": 255, + "30": 255, + "31": 255, + "32": 52, + "33": 33, + "34": 253, + "35": 225, + "37": 32, + "38": 88, + "39": 32, + "4": 52, + "40": 1, + "41": 9, + "42": 8, + "43": 43, + "44": 16, + "45": 1, + "47": 24, + "48": 1, + "49": 105, + "5": 33, + "50": 8, + "51": 43, + "52": 16, + "53": 1, + "55": 16, + "56": 32, + "57": 14, + "59": 34, + "6": 252, + "60": 32, + "61": 2, + "63": 10, + "67": 12, + "68": 32, + "69": 12, + "7": 142, + "71": 11, + "72": 60, + "73": 1, + "74": 255, + "75": 255, + "76": 52, + "77": 33, + "78": 253, + "79": 213, + "81": 32, + "82": 104, + "83": 32, + "84": 1, + "85": 141, + "86": 8, + "87": 43, + "88": 16, + "89": 1, + "9": 32, + "90": 255, + "91": 224, + }, + registers: { + "10,t2": "0x5", + "11,t3": "0xfffffde1", + "12,t4": "0xb", + "13,t5": "0xfffffdd5", + "14,t6": "0x22", + "2,v0": "0xa", + "8,t0": "0xfffffc8e", + "9,t1": "0xfffffc8f", + PC: "0x44", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_046.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_046.s.snap new file mode 100644 index 000000000..fae6e06ed --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_046.s.snap @@ -0,0 +1,62 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_046.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 60, + "1": 1, + "10": 64, + "11": 32, + "12": 32, + "13": 9, + "14": 17, + "15": 215, + "16": 60, + "17": 1, + "18": 255, + "19": 255, + "20": 52, + "21": 33, + "22": 218, + "23": 242, + "25": 32, + "26": 80, + "27": 32, + "28": 1, + "29": 9, + "3": 2, + "30": 88, + "31": 47, + "32": 1, + "33": 42, + "34": 96, + "35": 47, + "36": 1, + "37": 72, + "38": 104, + "39": 47, + "4": 52, + "40": 3, + "41": 224, + "43": 8, + "5": 33, + "6": 35, + "7": 70, + "9": 32, + }, + registers: { + "1,at": "0xffffdaf2", + "10,t2": "0xffffdaf2", + "11,t3": "0xfffdcc28", + "12,t4": "0x2408", + "13,t5": "0x409", + "8,t0": "0x22346", + "9,t1": "0x11d7", + PC: "0xffffffff", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_047.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_047.s.snap new file mode 100644 index 000000000..e1c21c7ff --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_047.s.snap @@ -0,0 +1,47 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_047.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 60, + "1": 1, + "10": 64, + "11": 32, + "12": 32, + "13": 9, + "14": 17, + "15": 215, + "20": 60, + "21": 1, + "22": 255, + "23": 255, + "24": 52, + "25": 33, + "26": 218, + "27": 242, + "29": 32, + "3": 2, + "30": 80, + "31": 32, + "32": 3, + "33": 224, + "35": 8, + "4": 52, + "5": 33, + "6": 35, + "7": 70, + "9": 32, + }, + registers: { + "1,at": "0xffffdaf2", + "10,t2": "0xffffdaf2", + "8,t0": "0x22346", + "9,t1": "0x11d7", + PC: "0xffffffff", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_048.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_048.s.snap new file mode 100644 index 000000000..824d6a417 --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_048.s.snap @@ -0,0 +1,60 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_048.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 8, + "10": 66, + "11": 53, + "13": 32, + "14": 72, + "15": 32, + "16": 60, + "17": 1, + "18": 255, + "19": 255, + "20": 52, + "21": 33, + "22": 255, + "23": 255, + "25": 32, + "26": 80, + "27": 32, + "28": 1, + "3": 1, + "30": 88, + "31": 32, + "32": 1, + "33": 32, + "34": 96, + "35": 32, + "36": 1, + "37": 64, + "38": 104, + "39": 32, + "4": 60, + "40": 3, + "41": 224, + "43": 8, + "5": 1, + "7": 35, + "8": 52, + "9": 33, + }, + registers: { + "1,at": "0xffffffff", + "10,t2": "0xffffffff", + "11,t3": "0x1", + "12,t4": "0x234235", + "13,t5": "0xffffffff", + "8,t0": "0x1", + "9,t1": "0x234235", + PC: "0xffffffff", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_049.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_049.s.snap new file mode 100644 index 000000000..ba3d394c1 --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_049.s.snap @@ -0,0 +1,55 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_049.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 60, + "1": 1, + "10": 64, + "11": 32, + "12": 60, + "13": 1, + "14": 255, + "15": 248, + "16": 52, + "17": 33, + "18": 224, + "19": 202, + "21": 32, + "22": 72, + "23": 32, + "24": 1, + "27": 17, + "28": 1, + "29": 32, + "3": 35, + "31": 19, + "34": 88, + "35": 16, + "38": 96, + "39": 18, + "4": 52, + "40": 3, + "41": 224, + "43": 8, + "5": 33, + "6": 69, + "7": 102, + "9": 32, + }, + registers: { + "1,at": "0xfff8e0ca", + "11,t3": "0x234566", + "12,t4": "0xfff8e0ca", + "8,t0": "0x234566", + "9,t1": "0xfff8e0ca", + HI: "0x234566", + LO: "0xfff8e0ca", + PC: "0xffffffff", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_050.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_050.s.snap new file mode 100644 index 000000000..cefbdbc6a --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_050.s.snap @@ -0,0 +1,66 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_050.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 8, + "10": 252, + "11": 87, + "13": 32, + "14": 72, + "15": 32, + "16": 32, + "17": 10, + "19": 12, + "2": 2, + "20": 60, + "21": 1, + "23": 18, + "24": 52, + "25": 33, + "26": 53, + "27": 21, + "29": 32, + "3": 35, + "30": 88, + "31": 32, + "32": 1, + "33": 9, + "34": 96, + "35": 35, + "36": 1, + "37": 76, + "38": 104, + "39": 35, + "4": 60, + "40": 1, + "41": 109, + "42": 112, + "43": 35, + "44": 3, + "45": 224, + "47": 8, + "5": 1, + "6": 255, + "7": 255, + "8": 52, + "9": 33, + }, + registers: { + "1,at": "0x123515", + "10,t2": "0xc", + "11,t3": "0x123515", + "12,t4": "0x5cc", + "13,t5": "0xfffffa40", + "14,t6": "0x123ad5", + "8,t0": "0x223", + "9,t1": "0xfffffc57", + PC: "0xffffffff", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_051.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_051.s.snap new file mode 100644 index 000000000..1087c338e --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_051.s.snap @@ -0,0 +1,52 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_051.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 8, + "10": 255, + "11": 255, + "12": 52, + "13": 33, + "14": 255, + "15": 255, + "17": 32, + "18": 80, + "19": 32, + "20": 16, + "21": 9, + "23": 16, + "24": 32, + "25": 14, + "27": 34, + "28": 32, + "29": 2, + "3": 1, + "31": 10, + "35": 12, + "36": 32, + "37": 12, + "4": 32, + "40": 16, + "41": 12, + "42": 255, + "43": 240, + "5": 9, + "8": 60, + "9": 1, + }, + registers: { + "1,at": "0xffffffff", + "10,t2": "0xffffffff", + "14,t6": "0x22", + "2,v0": "0xa", + "8,t0": "0x1", + PC: "0x24", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_052.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_052.s.snap new file mode 100644 index 000000000..3e48bb1cb --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_052.s.snap @@ -0,0 +1,44 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_052.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 8, + "11": 20, + "12": 5, + "13": 1, + "15": 16, + "16": 32, + "17": 14, + "19": 34, + "20": 32, + "21": 2, + "23": 10, + "27": 12, + "28": 32, + "29": 12, + "3": 1, + "31": 2, + "32": 5, + "33": 129, + "34": 255, + "35": 240, + "4": 32, + "5": 9, + "8": 5, + "9": 33, + }, + registers: { + "12,t4": "0x2", + "14,t6": "0x22", + "2,v0": "0xa", + "8,t0": "0x1", + PC: "0x1c", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_053.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_053.s.snap new file mode 100644 index 000000000..62966623a --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_053.s.snap @@ -0,0 +1,45 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_053.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 8, + "11": 20, + "12": 5, + "13": 17, + "15": 16, + "16": 32, + "17": 14, + "19": 34, + "20": 32, + "21": 2, + "23": 10, + "27": 12, + "28": 32, + "29": 12, + "3": 1, + "31": 2, + "32": 5, + "33": 145, + "34": 255, + "35": 240, + "4": 32, + "5": 9, + "8": 5, + "9": 49, + }, + registers: { + "12,t4": "0x2", + "14,t6": "0x22", + "2,v0": "0xa", + "31,ra": "0x24", + "8,t0": "0x1", + PC: "0x1c", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_054.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_054.s.snap new file mode 100644 index 000000000..4f5d8f033 --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_054.s.snap @@ -0,0 +1,43 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_054.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 8, + "11": 20, + "12": 29, + "15": 16, + "16": 32, + "17": 14, + "19": 34, + "20": 32, + "21": 2, + "23": 10, + "27": 12, + "28": 32, + "29": 12, + "3": 1, + "31": 2, + "32": 29, + "33": 128, + "34": 255, + "35": 240, + "4": 32, + "5": 9, + "8": 29, + "9": 32, + }, + registers: { + "12,t4": "0x2", + "14,t6": "0x22", + "2,v0": "0xa", + "8,t0": "0x1", + PC: "0x1c", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_055.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_055.s.snap new file mode 100644 index 000000000..4d9144f27 --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_055.s.snap @@ -0,0 +1,52 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_055.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 8, + "10": 255, + "11": 255, + "13": 32, + "14": 72, + "15": 32, + "16": 25, + "19": 20, + "20": 25, + "21": 32, + "23": 16, + "24": 32, + "25": 14, + "27": 34, + "28": 32, + "29": 2, + "3": 1, + "31": 10, + "35": 12, + "36": 32, + "37": 12, + "4": 60, + "40": 25, + "41": 128, + "42": 255, + "43": 240, + "5": 1, + "6": 255, + "7": 255, + "8": 52, + "9": 33, + }, + registers: { + "1,at": "0xffffffff", + "14,t6": "0x22", + "2,v0": "0xa", + "8,t0": "0x1", + "9,t1": "0xffffffff", + PC: "0x24", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_056.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_056.s.snap new file mode 100644 index 000000000..2c0eec16a --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_056.s.snap @@ -0,0 +1,71 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_056.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 8, + "10": 2, + "11": 31, + "12": 1, + "13": 9, + "14": 8, + "15": 42, + "16": 20, + "17": 1, + "19": 24, + "2": 3, + "20": 1, + "21": 73, + "22": 8, + "23": 42, + "24": 20, + "25": 1, + "27": 16, + "28": 32, + "29": 14, + "3": 114, + "31": 34, + "32": 32, + "33": 2, + "35": 10, + "39": 12, + "4": 32, + "40": 32, + "41": 12, + "43": 11, + "44": 32, + "45": 13, + "46": 2, + "47": 43, + "48": 1, + "49": 141, + "5": 9, + "50": 8, + "51": 42, + "52": 20, + "53": 1, + "54": 255, + "55": 232, + "6": 3, + "7": 113, + "8": 32, + "9": 10, + }, + registers: { + "1,at": "0x1", + "10,t2": "0x21f", + "12,t4": "0xb", + "13,t5": "0x22b", + "14,t6": "0x22", + "2,v0": "0xa", + "8,t0": "0x372", + "9,t1": "0x371", + PC: "0x28", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_057.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_057.s.snap new file mode 100644 index 000000000..4784adc3c --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_057.s.snap @@ -0,0 +1,65 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_057.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 8, + "10": 255, + "11": 255, + "12": 52, + "13": 33, + "14": 255, + "15": 255, + "17": 32, + "18": 80, + "19": 32, + "20": 20, + "21": 8, + "23": 16, + "24": 32, + "25": 14, + "27": 34, + "28": 32, + "29": 2, + "3": 1, + "31": 10, + "35": 12, + "36": 60, + "37": 1, + "39": 3, + "4": 32, + "40": 52, + "41": 33, + "42": 151, + "43": 99, + "45": 32, + "46": 96, + "47": 32, + "48": 32, + "49": 13, + "5": 9, + "51": 170, + "52": 20, + "53": 12, + "54": 255, + "55": 228, + "8": 60, + "9": 1, + }, + registers: { + "1,at": "0x39763", + "10,t2": "0xffffffff", + "12,t4": "0x39763", + "13,t5": "0xaa", + "14,t6": "0x22", + "2,v0": "0xa", + "8,t0": "0x1", + PC: "0x24", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_058.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_058.s.snap new file mode 100644 index 000000000..94a60725e --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_058.s.snap @@ -0,0 +1,140 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_058.s 1`] = ` +{ + display: "", + error: false, + instruction_errors: [ + { + error: "Square root of a negative number is not allowed.", + i: 28, + }, + { + error: "Square root of a negative number is not allowed.", + i: 31, + }, + ], + keyboard: "", + memory: { + "0": 60, + "1": 1, + "10": 8, + "100": 52, + "101": 33, + "104": 68, + "105": 129, + "106": 64, + "108": 68, + "109": 32, + "110": 2, + "111": 132, + "112": 68, + "113": 32, + "114": 19, + "115": 4, + "116": 68, + "117": 32, + "118": 35, + "119": 132, + "12": 60, + "120": 68, + "122": 52, + "123": 4, + "124": 68, + "126": 60, + "127": 68, + "128": 68, + "13": 1, + "130": 68, + "131": 132, + "132": 32, + "133": 2, + "135": 10, + "139": 12, + "14": 64, + "15": 112, + "16": 52, + "17": 33, + "20": 68, + "21": 129, + "24": 60, + "25": 1, + "28": 52, + "29": 33, + "32": 68, + "33": 129, + "34": 24, + "36": 60, + "37": 1, + "38": 192, + "39": 171, + "4": 52, + "40": 52, + "41": 33, + "42": 50, + "44": 68, + "45": 129, + "46": 16, + "48": 60, + "49": 1, + "5": 33, + "52": 52, + "53": 33, + "56": 68, + "57": 129, + "58": 40, + "60": 60, + "61": 1, + "62": 64, + "63": 181, + "64": 52, + "65": 33, + "66": 100, + "68": 68, + "69": 129, + "70": 32, + "72": 60, + "73": 1, + "74": 70, + "75": 25, + "76": 52, + "77": 33, + "78": 36, + "8": 68, + "80": 68, + "81": 129, + "82": 48, + "84": 60, + "85": 1, + "86": 198, + "87": 1, + "88": 52, + "89": 33, + "9": 129, + "90": 100, + "92": 68, + "93": 129, + "94": 56, + "96": 60, + "97": 1, + "98": 70, + "99": 16, + }, + registers: { + "1,at": "0x46100000", + "2,v0": "0xa", + "f0,FP0": "0x40700000", + "f10,FP10": "0x40300000", + "f14,FP14": "0x40528000", + "f16,FP16": "0x42c60000", + "f18,FP18": "0x42c00000", + "f2,FP2": "0xc0ab3200", + "f4,FP4": "0x40b56400", + "f6,FP6": "0x46192400", + "f8,FP8": "0x46100000", + PC: "0x8c", + f7: "0xc6016400", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_059.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_059.s.snap new file mode 100644 index 000000000..4e98bab36 --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_059.s.snap @@ -0,0 +1,133 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_059.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 60, + "1": 1, + "10": 8, + "100": 52, + "101": 33, + "104": 68, + "105": 129, + "106": 64, + "108": 68, + "109": 32, + "110": 2, + "111": 128, + "112": 68, + "113": 34, + "114": 19, + "116": 68, + "117": 36, + "118": 35, + "119": 128, + "12": 60, + "120": 68, + "121": 6, + "122": 52, + "124": 68, + "125": 7, + "126": 60, + "127": 64, + "128": 68, + "129": 8, + "13": 1, + "130": 68, + "131": 128, + "132": 32, + "133": 2, + "135": 10, + "139": 12, + "14": 64, + "15": 112, + "16": 52, + "17": 33, + "20": 68, + "21": 129, + "24": 60, + "25": 1, + "28": 52, + "29": 33, + "32": 68, + "33": 129, + "34": 24, + "36": 60, + "37": 1, + "38": 64, + "39": 171, + "4": 52, + "40": 52, + "41": 33, + "42": 50, + "44": 68, + "45": 129, + "46": 16, + "48": 60, + "49": 1, + "5": 33, + "52": 52, + "53": 33, + "56": 68, + "57": 129, + "58": 40, + "60": 60, + "61": 1, + "62": 64, + "63": 181, + "64": 52, + "65": 33, + "66": 100, + "68": 68, + "69": 129, + "70": 32, + "72": 60, + "73": 1, + "74": 70, + "75": 25, + "76": 52, + "77": 33, + "78": 36, + "8": 68, + "80": 68, + "81": 129, + "82": 48, + "84": 60, + "85": 1, + "86": 70, + "87": 1, + "88": 52, + "89": 33, + "9": 129, + "90": 100, + "92": 68, + "93": 129, + "94": 56, + "96": 60, + "97": 1, + "98": 70, + "99": 16, + }, + registers: { + "1,at": "0x46100000", + "2,v0": "0xa", + "f0,FP0": "0x40700000", + "f10,FP10": "0x40800000", + "f12,FP12": "0x40bb3200", + "f14,FP14": "0x40c56400", + "f16,FP16": "0x46992400", + "f18,FP18": "0x46900000", + "f2,FP2": "0x40ab3200", + "f4,FP4": "0x40b56400", + "f6,FP6": "0x46192400", + "f8,FP8": "0x46100000", + PC: "0x8c", + f17: "0x46816400", + f7: "0x46016400", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_060.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_060.s.snap new file mode 100644 index 000000000..c4dcee483 --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_060.s.snap @@ -0,0 +1,135 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_060.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 60, + "1": 1, + "10": 8, + "100": 52, + "101": 33, + "104": 68, + "105": 129, + "106": 64, + "108": 68, + "109": 34, + "110": 2, + "111": 129, + "112": 68, + "113": 36, + "114": 19, + "115": 1, + "116": 68, + "117": 32, + "118": 35, + "119": 129, + "12": 60, + "120": 68, + "121": 7, + "122": 52, + "123": 1, + "124": 68, + "125": 8, + "126": 60, + "127": 65, + "128": 68, + "129": 6, + "13": 1, + "130": 68, + "131": 129, + "132": 32, + "133": 2, + "135": 10, + "139": 12, + "14": 64, + "15": 112, + "16": 52, + "17": 33, + "20": 68, + "21": 129, + "24": 60, + "25": 1, + "28": 52, + "29": 33, + "32": 68, + "33": 129, + "34": 24, + "36": 60, + "37": 1, + "38": 64, + "39": 171, + "4": 52, + "40": 52, + "41": 33, + "42": 50, + "44": 68, + "45": 129, + "46": 16, + "48": 60, + "49": 1, + "5": 33, + "52": 52, + "53": 33, + "56": 68, + "57": 129, + "58": 40, + "60": 60, + "61": 1, + "62": 64, + "63": 181, + "64": 52, + "65": 33, + "66": 100, + "68": 68, + "69": 129, + "70": 32, + "72": 60, + "73": 1, + "74": 70, + "75": 25, + "76": 52, + "77": 33, + "78": 36, + "8": 68, + "80": 68, + "81": 129, + "82": 48, + "84": 60, + "85": 1, + "86": 70, + "87": 1, + "88": 52, + "89": 33, + "9": 129, + "90": 100, + "92": 68, + "93": 129, + "94": 56, + "96": 60, + "97": 1, + "98": 70, + "99": 16, + }, + registers: { + "1,at": "0x46100000", + "2,v0": "0xa", + "f0,FP0": "0x40700000", + "f10,FP10": "0xc0a93200", + "f12,FP12": "0xc09f2c00", + "f14,FP14": "0x40b46400", + "f16,FP16": "0x44be0000", + "f18,FP18": "0xc4124000", + "f2,FP2": "0x40ab3200", + "f4,FP4": "0x40b56400", + "f6,FP6": "0x46192400", + "f8,FP8": "0x46100000", + PC: "0x8c", + f17: "0xc469c000", + f7: "0x46016400", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_061.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_061.s.snap new file mode 100644 index 000000000..6bd73b644 --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_061.s.snap @@ -0,0 +1,132 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_061.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 60, + "1": 1, + "10": 8, + "100": 52, + "101": 33, + "104": 68, + "105": 129, + "106": 64, + "108": 68, + "109": 32, + "110": 2, + "111": 133, + "112": 68, + "113": 32, + "114": 19, + "115": 5, + "116": 68, + "117": 32, + "118": 35, + "119": 133, + "12": 60, + "120": 68, + "122": 52, + "123": 5, + "124": 68, + "126": 60, + "127": 69, + "128": 68, + "13": 1, + "130": 68, + "131": 133, + "132": 32, + "133": 2, + "135": 10, + "139": 12, + "14": 64, + "15": 112, + "16": 52, + "17": 33, + "20": 68, + "21": 129, + "24": 60, + "25": 1, + "28": 52, + "29": 33, + "32": 68, + "33": 129, + "34": 24, + "36": 60, + "37": 1, + "38": 192, + "39": 171, + "4": 52, + "40": 52, + "41": 33, + "42": 50, + "44": 68, + "45": 129, + "46": 16, + "48": 60, + "49": 1, + "5": 33, + "52": 52, + "53": 33, + "56": 68, + "57": 129, + "58": 40, + "60": 60, + "61": 1, + "62": 64, + "63": 181, + "64": 52, + "65": 33, + "66": 100, + "68": 68, + "69": 129, + "70": 32, + "72": 60, + "73": 1, + "74": 198, + "75": 25, + "76": 52, + "77": 33, + "78": 36, + "8": 68, + "80": 68, + "81": 129, + "82": 48, + "84": 60, + "85": 1, + "86": 70, + "87": 1, + "88": 52, + "89": 33, + "9": 129, + "90": 100, + "92": 68, + "93": 129, + "94": 56, + "96": 60, + "97": 1, + "98": 198, + "99": 16, + }, + registers: { + "1,at": "0xc6100000", + "2,v0": "0xa", + "f0,FP0": "0x40700000", + "f10,FP10": "0x40700000", + "f12,FP12": "0x40ab3200", + "f14,FP14": "0x40b56400", + "f16,FP16": "0x46192400", + "f18,FP18": "0x46100000", + "f2,FP2": "0xc0ab3200", + "f4,FP4": "0x40b56400", + "f6,FP6": "0xc6192400", + "f8,FP8": "0xc6100000", + PC: "0x8c", + f17: "0x46016400", + f7: "0x46016400", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_062.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_062.s.snap new file mode 100644 index 000000000..ddd888b59 --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_062.s.snap @@ -0,0 +1,130 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_062.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 60, + "1": 1, + "10": 8, + "100": 52, + "101": 33, + "104": 68, + "105": 129, + "106": 64, + "108": 68, + "109": 34, + "110": 2, + "111": 130, + "112": 68, + "113": 36, + "114": 19, + "115": 2, + "116": 68, + "117": 32, + "118": 35, + "119": 130, + "12": 60, + "120": 68, + "121": 7, + "122": 52, + "123": 2, + "124": 68, + "125": 8, + "126": 60, + "127": 66, + "128": 68, + "129": 6, + "13": 1, + "130": 68, + "131": 130, + "132": 32, + "133": 2, + "135": 10, + "139": 12, + "14": 64, + "15": 112, + "16": 52, + "17": 33, + "20": 68, + "21": 129, + "24": 60, + "25": 1, + "28": 52, + "29": 33, + "32": 68, + "33": 129, + "34": 24, + "36": 60, + "37": 1, + "38": 192, + "39": 176, + "4": 52, + "40": 52, + "41": 33, + "44": 68, + "45": 129, + "46": 16, + "48": 60, + "49": 1, + "5": 33, + "52": 52, + "53": 33, + "56": 68, + "57": 129, + "58": 40, + "60": 60, + "61": 1, + "62": 64, + "63": 8, + "64": 52, + "65": 33, + "68": 68, + "69": 129, + "70": 32, + "72": 60, + "73": 1, + "74": 195, + "75": 150, + "76": 52, + "77": 33, + "8": 68, + "80": 68, + "81": 129, + "82": 48, + "84": 60, + "85": 1, + "86": 64, + "87": 160, + "88": 52, + "89": 33, + "9": 129, + "92": 68, + "93": 129, + "94": 56, + "96": 60, + "97": 1, + "98": 196, + }, + registers: { + "1,at": "0xc4000000", + "2,v0": "0xa", + "f0,FP0": "0x40700000", + "f10,FP10": "0xc1300000", + "f12,FP12": "0xc0c80000", + "f14,FP14": "0x40880000", + "f16,FP16": "0xc4bb8000", + "f18,FP18": "0x48160000", + "f2,FP2": "0xc0b00000", + "f4,FP4": "0x40080000", + "f6,FP6": "0xc3960000", + "f8,FP8": "0xc4000000", + PC: "0x8c", + f17: "0xc5200000", + f7: "0x40a00000", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_063.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_063.s.snap new file mode 100644 index 000000000..490c1be1c --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_063.s.snap @@ -0,0 +1,132 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_063.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 60, + "1": 1, + "10": 8, + "100": 52, + "101": 33, + "104": 68, + "105": 129, + "106": 64, + "108": 68, + "109": 34, + "110": 2, + "111": 131, + "112": 68, + "113": 36, + "114": 19, + "115": 3, + "116": 68, + "117": 36, + "118": 3, + "119": 131, + "12": 60, + "120": 68, + "121": 7, + "122": 52, + "123": 3, + "124": 68, + "125": 8, + "126": 60, + "127": 67, + "128": 68, + "129": 6, + "13": 1, + "130": 68, + "131": 131, + "132": 32, + "133": 2, + "135": 10, + "139": 12, + "14": 64, + "15": 112, + "16": 52, + "17": 33, + "20": 68, + "21": 129, + "24": 60, + "25": 1, + "28": 52, + "29": 33, + "32": 68, + "33": 129, + "34": 24, + "36": 60, + "37": 1, + "38": 192, + "39": 176, + "4": 52, + "40": 52, + "41": 33, + "44": 68, + "45": 129, + "46": 16, + "48": 60, + "49": 1, + "5": 33, + "52": 52, + "53": 33, + "56": 68, + "57": 129, + "58": 40, + "60": 60, + "61": 1, + "62": 64, + "63": 8, + "64": 52, + "65": 33, + "68": 68, + "69": 129, + "70": 32, + "72": 60, + "73": 1, + "74": 195, + "75": 150, + "76": 52, + "77": 33, + "8": 68, + "80": 68, + "81": 129, + "82": 48, + "84": 60, + "85": 1, + "86": 64, + "87": 160, + "88": 52, + "89": 33, + "9": 129, + "92": 68, + "93": 129, + "94": 56, + "96": 60, + "97": 1, + "98": 196, + }, + registers: { + "1,at": "0xc4000000", + "2,v0": "0xa", + "f0,FP0": "0x40700000", + "f10,FP10": "0xbfb00000", + "f12,FP12": "0xc0955555", + "f14,FP14": "0x40555555", + "f16,FP16": "0xc2700000", + "f18,FP18": "0x3fda740e", + "f2,FP2": "0xc0b00000", + "f4,FP4": "0x40080000", + "f6,FP6": "0xc3960000", + "f8,FP8": "0xc4000000", + PC: "0x8c", + f13: "0x55555555", + f15: "0x55555555", + f17: "0xbc200000", + f7: "0x40a00000", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_064.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_064.s.snap new file mode 100644 index 000000000..4598a17c2 --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_064.s.snap @@ -0,0 +1,141 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_064.s 1`] = ` +{ + display: "", + error: false, + instruction_errors: [ + { + error: "Square root of a negative number is not allowed.", + i: 28, + }, + { + error: "Square root of a negative number is not allowed.", + i: 31, + }, + ], + keyboard: "", + memory: { + "0": 60, + "1": 1, + "10": 8, + "100": 52, + "101": 33, + "104": 68, + "105": 129, + "106": 64, + "108": 68, + "109": 32, + "110": 2, + "111": 150, + "112": 68, + "113": 32, + "114": 19, + "115": 22, + "116": 68, + "117": 32, + "118": 35, + "119": 150, + "12": 60, + "120": 68, + "122": 52, + "123": 22, + "124": 68, + "126": 60, + "127": 86, + "128": 68, + "13": 1, + "130": 68, + "131": 150, + "132": 32, + "133": 2, + "135": 10, + "139": 12, + "14": 64, + "15": 112, + "16": 52, + "17": 33, + "20": 68, + "21": 129, + "24": 60, + "25": 1, + "28": 52, + "29": 33, + "32": 68, + "33": 129, + "34": 24, + "36": 60, + "37": 1, + "38": 192, + "39": 171, + "4": 52, + "40": 52, + "41": 33, + "42": 50, + "44": 68, + "45": 129, + "46": 16, + "48": 60, + "49": 1, + "5": 33, + "52": 52, + "53": 33, + "56": 68, + "57": 129, + "58": 40, + "60": 60, + "61": 1, + "62": 64, + "63": 181, + "64": 52, + "65": 33, + "66": 100, + "68": 68, + "69": 129, + "70": 32, + "72": 60, + "73": 1, + "74": 70, + "75": 25, + "76": 52, + "77": 33, + "78": 36, + "8": 68, + "80": 68, + "81": 129, + "82": 48, + "84": 60, + "85": 1, + "86": 198, + "87": 1, + "88": 52, + "89": 33, + "9": 129, + "90": 100, + "92": 68, + "93": 129, + "94": 56, + "96": 60, + "97": 1, + "98": 70, + "99": 16, + }, + registers: { + "1,at": "0x46100000", + "2,v0": "0xa", + "f0,FP0": "0x40700000", + "f10,FP10": "0x3fb00000", + "f14,FP14": "0x3f8bacf9", + "f16,FP16": "0x3c257eb5", + "f18,FP18": "0x3c2aaaab", + "f2,FP2": "0xc0ab3200", + "f4,FP4": "0x40b56400", + "f6,FP6": "0x46192400", + "f8,FP8": "0x46100000", + PC: "0x8c", + f15: "0x14c1bad0", + f7: "0xc6016400", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_065.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_065.s.snap new file mode 100644 index 000000000..ff2f42b32 --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_065.s.snap @@ -0,0 +1,112 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_065.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 60, + "1": 1, + "10": 8, + "100": 52, + "101": 33, + "104": 68, + "105": 129, + "106": 64, + "108": 68, + "110": 50, + "111": 161, + "112": 68, + "113": 32, + "114": 96, + "115": 160, + "116": 32, + "117": 2, + "119": 10, + "12": 60, + "123": 12, + "13": 1, + "14": 64, + "15": 112, + "16": 52, + "17": 33, + "20": 68, + "21": 129, + "24": 60, + "25": 1, + "28": 52, + "29": 33, + "32": 68, + "33": 129, + "34": 24, + "36": 60, + "37": 1, + "38": 192, + "39": 171, + "4": 52, + "40": 52, + "41": 33, + "42": 50, + "44": 68, + "45": 129, + "46": 16, + "48": 60, + "49": 1, + "5": 33, + "52": 52, + "53": 33, + "56": 68, + "57": 129, + "58": 40, + "60": 60, + "61": 1, + "62": 64, + "63": 181, + "64": 52, + "65": 33, + "66": 100, + "68": 68, + "69": 129, + "70": 32, + "72": 60, + "73": 1, + "74": 70, + "75": 25, + "76": 52, + "77": 33, + "78": 36, + "8": 68, + "80": 68, + "81": 129, + "82": 48, + "84": 60, + "85": 1, + "86": 198, + "87": 1, + "88": 52, + "89": 33, + "9": 129, + "90": 100, + "92": 68, + "93": 129, + "94": 56, + "96": 60, + "97": 1, + "98": 70, + "99": 16, + }, + registers: { + "1,at": "0x46100000", + "2,v0": "0xa", + "f0,FP0": "0x40700000", + "f10,FP10": "0x40c32480", + "f4,FP4": "0x40b56400", + "f6,FP6": "0x46192400", + "f8,FP8": "0x46100000", + PC: "0x7c", + f7: "0xc6016400", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_066.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_066.s.snap new file mode 100644 index 000000000..bf9b48bcd --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_066.s.snap @@ -0,0 +1,95 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_066.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 60, + "1": 1, + "10": 8, + "12": 60, + "13": 1, + "14": 64, + "15": 112, + "16": 52, + "17": 33, + "20": 68, + "21": 129, + "24": 60, + "25": 1, + "28": 52, + "29": 33, + "32": 68, + "33": 129, + "34": 24, + "36": 60, + "37": 1, + "38": 192, + "39": 171, + "4": 52, + "40": 52, + "41": 33, + "42": 50, + "44": 68, + "45": 129, + "46": 16, + "48": 60, + "49": 1, + "5": 33, + "50": 70, + "51": 25, + "52": 52, + "53": 33, + "54": 36, + "56": 68, + "57": 129, + "58": 48, + "60": 60, + "61": 1, + "62": 198, + "63": 1, + "64": 52, + "65": 33, + "66": 100, + "68": 68, + "69": 129, + "70": 56, + "72": 68, + "73": 32, + "74": 2, + "75": 36, + "76": 68, + "77": 32, + "78": 18, + "79": 100, + "8": 68, + "80": 68, + "82": 50, + "83": 164, + "84": 68, + "86": 58, + "87": 228, + "88": 32, + "89": 2, + "9": 129, + "91": 10, + "95": 12, + }, + registers: { + "1,at": "0xc6016400", + "10,t2": "0x2649", + "11,t3": "0xffffdfa7", + "2,v0": "0xa", + "8,t0": "0x100", + "9,t1": "0xfffff267", + "f0,FP0": "0x40700000", + "f2,FP2": "0xc0ab3200", + "f6,FP6": "0x46192400", + PC: "0x60", + f7: "0xc6016400", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_067.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_067.s.snap new file mode 100644 index 000000000..c2558cb60 --- /dev/null +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_067.s.snap @@ -0,0 +1,109 @@ +export const snapshot = {}; + +snapshot[`mips/instructions/test_mips_instruction_067.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 60, + "1": 1, + "10": 64, + "11": 32, + "12": 60, + "13": 1, + "14": 255, + "15": 220, + "16": 52, + "17": 33, + "18": 53, + "19": 154, + "21": 32, + "22": 72, + "23": 32, + "24": 60, + "25": 1, + "26": 2, + "27": 52, + "28": 52, + "29": 33, + "3": 1, + "30": 103, + "31": 255, + "33": 32, + "34": 80, + "35": 32, + "36": 60, + "37": 1, + "38": 255, + "39": 169, + "4": 52, + "40": 52, + "41": 33, + "42": 175, + "43": 159, + "45": 32, + "46": 88, + "47": 32, + "48": 32, + "49": 12, + "5": 33, + "50": 30, + "51": 219, + "52": 32, + "53": 13, + "54": 22, + "55": 46, + "56": 68, + "57": 32, + "58": 64, + "59": 33, + "6": 226, + "60": 68, + "61": 32, + "62": 72, + "63": 161, + "64": 68, + "65": 32, + "66": 81, + "67": 33, + "68": 68, + "69": 64, + "7": 174, + "70": 89, + "71": 160, + "72": 68, + "73": 64, + "74": 97, + "75": 224, + "76": 68, + "77": 64, + "78": 106, + "79": 32, + "80": 32, + "81": 2, + "83": 10, + "87": 12, + "9": 32, + }, + registers: { + "1,at": "0xffa9af9f", + "10,t2": "0x23467ff", + "11,t3": "0xffa9af9f", + "12,t4": "0x1edb", + "13,t5": "0x162e", + "2,v0": "0xa", + "8,t0": "0x1e2ae", + "9,t1": "0xffdc359a", + "f0,FP0": "0x40fe2ae0", + "f2,FP2": "0xc141e533", + "f4,FP4": "0x4181a33f", + "f6,FP6": "0xcaaca0c2", + "f8,FP8": "0x45b17000", + PC: "0x58", + f5: "0xf8000000", + f7: "0x45f6d800", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_001.s.snap b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_001.s.snap new file mode 100644 index 000000000..61e91bc93 --- /dev/null +++ b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_001.s.snap @@ -0,0 +1,60 @@ +export const snapshot = {}; + +snapshot[`mips/sentinel/test_mips_sentinels_001.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 4, + "11": 10, + "15": 12, + "16": 32, + "17": 1, + "19": 12, + "20": 3, + "21": 161, + "22": 232, + "23": 35, + "24": 175, + "25": 191, + "268435451": 8, + "27": 8, + "28": 175, + "29": 190, + "3": 5, + "31": 4, + "32": 39, + "33": 190, + "35": 4, + "36": 32, + "37": 4, + "39": 2, + "4": 12, + "40": 143, + "41": 191, + "43": 8, + "44": 143, + "45": 190, + "47": 4, + "48": 39, + "49": 189, + "51": 12, + "52": 3, + "53": 224, + "55": 8, + "7": 16, + "8": 32, + "9": 2, + }, + registers: { + "1,at": "0xc", + "2,v0": "0xa", + "31,ra": "0x8", + "4,a0": "0x2", + PC: "0x10", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_002.s.snap b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_002.s.snap new file mode 100644 index 000000000..9e9ca32aa --- /dev/null +++ b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_002.s.snap @@ -0,0 +1,60 @@ +export const snapshot = {}; + +snapshot[`mips/sentinel/test_mips_sentinels_002.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 5, + "11": 10, + "15": 12, + "16": 32, + "17": 1, + "19": 12, + "20": 3, + "21": 161, + "22": 232, + "23": 35, + "24": 175, + "25": 191, + "268435451": 8, + "27": 8, + "28": 175, + "29": 190, + "3": 5, + "31": 4, + "32": 39, + "33": 190, + "35": 4, + "36": 32, + "37": 5, + "39": 2, + "4": 12, + "40": 143, + "41": 191, + "43": 8, + "44": 143, + "45": 190, + "47": 4, + "48": 39, + "49": 189, + "51": 12, + "52": 3, + "53": 224, + "55": 8, + "7": 16, + "8": 32, + "9": 2, + }, + registers: { + "1,at": "0xc", + "2,v0": "0xa", + "31,ra": "0x8", + "5,a1": "0x2", + PC: "0x10", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_003.s.snap b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_003.s.snap new file mode 100644 index 000000000..b87ce2183 --- /dev/null +++ b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_003.s.snap @@ -0,0 +1,60 @@ +export const snapshot = {}; + +snapshot[`mips/sentinel/test_mips_sentinels_003.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 6, + "11": 10, + "15": 12, + "16": 32, + "17": 1, + "19": 12, + "20": 3, + "21": 161, + "22": 232, + "23": 35, + "24": 175, + "25": 191, + "268435451": 8, + "27": 8, + "28": 175, + "29": 190, + "3": 5, + "31": 4, + "32": 39, + "33": 190, + "35": 4, + "36": 32, + "37": 6, + "39": 2, + "4": 12, + "40": 143, + "41": 191, + "43": 8, + "44": 143, + "45": 190, + "47": 4, + "48": 39, + "49": 189, + "51": 12, + "52": 3, + "53": 224, + "55": 8, + "7": 16, + "8": 32, + "9": 2, + }, + registers: { + "1,at": "0xc", + "2,v0": "0xa", + "31,ra": "0x8", + "6,a2": "0x2", + PC: "0x10", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_004.s.snap b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_004.s.snap new file mode 100644 index 000000000..105920296 --- /dev/null +++ b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_004.s.snap @@ -0,0 +1,60 @@ +export const snapshot = {}; + +snapshot[`mips/sentinel/test_mips_sentinels_004.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 7, + "11": 10, + "15": 12, + "16": 32, + "17": 1, + "19": 12, + "20": 3, + "21": 161, + "22": 232, + "23": 35, + "24": 175, + "25": 191, + "268435451": 8, + "27": 8, + "28": 175, + "29": 190, + "3": 5, + "31": 4, + "32": 39, + "33": 190, + "35": 4, + "36": 32, + "37": 7, + "39": 2, + "4": 12, + "40": 143, + "41": 191, + "43": 8, + "44": 143, + "45": 190, + "47": 4, + "48": 39, + "49": 189, + "51": 12, + "52": 3, + "53": 224, + "55": 8, + "7": 16, + "8": 32, + "9": 2, + }, + registers: { + "1,at": "0xc", + "2,v0": "0xa", + "31,ra": "0x8", + "7,a3": "0x2", + PC: "0x10", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_005.s.snap b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_005.s.snap new file mode 100644 index 000000000..fbd1ca9a2 --- /dev/null +++ b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_005.s.snap @@ -0,0 +1,33 @@ +export const snapshot = {}; + +snapshot[`mips/sentinel/test_mips_sentinels_005.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 30, + "11": 10, + "15": 12, + "16": 32, + "17": 30, + "19": 5, + "20": 3, + "21": 224, + "23": 8, + "3": 5, + "4": 12, + "7": 16, + "8": 32, + "9": 2, + }, + registers: { + "2,v0": "0xa", + "30,fp": "0x5", + "31,ra": "0x8", + PC: "0x10", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_006.s.snap b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_006.s.snap new file mode 100644 index 000000000..be7427858 --- /dev/null +++ b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_006.s.snap @@ -0,0 +1,33 @@ +export const snapshot = {}; + +snapshot[`mips/sentinel/test_mips_sentinels_006.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 28, + "11": 10, + "15": 12, + "16": 32, + "17": 28, + "19": 5, + "20": 3, + "21": 224, + "23": 8, + "3": 5, + "4": 12, + "7": 16, + "8": 32, + "9": 2, + }, + registers: { + "2,v0": "0xa", + "28,gp": "0x5", + "31,ra": "0x8", + PC: "0x10", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_007.s.snap b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_007.s.snap new file mode 100644 index 000000000..3020f8f0b --- /dev/null +++ b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_007.s.snap @@ -0,0 +1,33 @@ +export const snapshot = {}; + +snapshot[`mips/sentinel/test_mips_sentinels_007.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 26, + "11": 10, + "15": 12, + "16": 32, + "17": 26, + "19": 5, + "20": 3, + "21": 224, + "23": 8, + "3": 5, + "4": 12, + "7": 16, + "8": 32, + "9": 2, + }, + registers: { + "2,v0": "0xa", + "26,k0": "0x5", + "31,ra": "0x8", + PC: "0x10", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_008.s.snap b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_008.s.snap new file mode 100644 index 000000000..82d869b69 --- /dev/null +++ b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_008.s.snap @@ -0,0 +1,33 @@ +export const snapshot = {}; + +snapshot[`mips/sentinel/test_mips_sentinels_008.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 27, + "11": 10, + "15": 12, + "16": 32, + "17": 27, + "19": 5, + "20": 3, + "21": 224, + "23": 8, + "3": 5, + "4": 12, + "7": 16, + "8": 32, + "9": 2, + }, + registers: { + "2,v0": "0xa", + "27,k1": "0x5", + "31,ra": "0x8", + PC: "0x10", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_009.s.snap b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_009.s.snap new file mode 100644 index 000000000..48acc183a --- /dev/null +++ b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_009.s.snap @@ -0,0 +1,32 @@ +export const snapshot = {}; + +snapshot[`mips/sentinel/test_mips_sentinels_009.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 31, + "11": 10, + "15": 12, + "16": 32, + "17": 31, + "18": 16, + "19": 138, + "20": 3, + "21": 224, + "23": 8, + "3": 5, + "4": 12, + "7": 16, + "8": 32, + "9": 2, + }, + registers: { + "31,ra": "0x108a", + PC: "0x201a", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_010.s.snap b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_010.s.snap new file mode 100644 index 000000000..4e7546130 --- /dev/null +++ b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_010.s.snap @@ -0,0 +1,67 @@ +export const snapshot = {}; + +snapshot[`mips/sentinel/test_mips_sentinels_010.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 16, + "11": 10, + "15": 12, + "16": 32, + "17": 1, + "19": 12, + "20": 3, + "21": 161, + "22": 232, + "23": 35, + "24": 175, + "25": 191, + "268435451": 8, + "27": 8, + "28": 175, + "29": 190, + "3": 5, + "31": 4, + "32": 39, + "33": 190, + "35": 4, + "36": 32, + "37": 16, + "39": 2, + "4": 12, + "40": 143, + "41": 191, + "43": 8, + "44": 143, + "45": 190, + "47": 4, + "48": 39, + "49": 189, + "51": 12, + "52": 3, + "53": 224, + "55": 8, + "7": 16, + "8": 32, + "9": 2, + }, + registers: { + "1,at": "0xc", + "16,s0": "0x2", + "2,v0": "0xa", + "31,ra": "0x8", + PC: "0x10", + }, + sentinel_errors: [ + { + function: "test", + msg: "Calling convention violations in test: + - Register 16,s0 was used but never saved to memory + - Register 16,s0 value changed but not properly restored", + }, + ], +} +`; diff --git a/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_011.s.snap b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_011.s.snap new file mode 100644 index 000000000..8a042d16f --- /dev/null +++ b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_011.s.snap @@ -0,0 +1,67 @@ +export const snapshot = {}; + +snapshot[`mips/sentinel/test_mips_sentinels_011.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 17, + "11": 10, + "15": 12, + "16": 32, + "17": 1, + "19": 12, + "20": 3, + "21": 161, + "22": 232, + "23": 35, + "24": 175, + "25": 191, + "268435451": 8, + "27": 8, + "28": 175, + "29": 190, + "3": 5, + "31": 4, + "32": 39, + "33": 190, + "35": 4, + "36": 32, + "37": 17, + "39": 2, + "4": 12, + "40": 143, + "41": 191, + "43": 8, + "44": 143, + "45": 190, + "47": 4, + "48": 39, + "49": 189, + "51": 12, + "52": 3, + "53": 224, + "55": 8, + "7": 16, + "8": 32, + "9": 2, + }, + registers: { + "1,at": "0xc", + "17,s1": "0x2", + "2,v0": "0xa", + "31,ra": "0x8", + PC: "0x10", + }, + sentinel_errors: [ + { + function: "test", + msg: "Calling convention violations in test: + - Register 17,s1 was used but never saved to memory + - Register 17,s1 value changed but not properly restored", + }, + ], +} +`; diff --git a/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_012.s.snap b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_012.s.snap new file mode 100644 index 000000000..6a8c3a649 --- /dev/null +++ b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_012.s.snap @@ -0,0 +1,67 @@ +export const snapshot = {}; + +snapshot[`mips/sentinel/test_mips_sentinels_012.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 18, + "11": 10, + "15": 12, + "16": 32, + "17": 1, + "19": 12, + "20": 3, + "21": 161, + "22": 232, + "23": 35, + "24": 175, + "25": 191, + "268435451": 8, + "27": 8, + "28": 175, + "29": 190, + "3": 5, + "31": 4, + "32": 39, + "33": 190, + "35": 4, + "36": 32, + "37": 18, + "39": 2, + "4": 12, + "40": 143, + "41": 191, + "43": 8, + "44": 143, + "45": 190, + "47": 4, + "48": 39, + "49": 189, + "51": 12, + "52": 3, + "53": 224, + "55": 8, + "7": 16, + "8": 32, + "9": 2, + }, + registers: { + "1,at": "0xc", + "18,s2": "0x2", + "2,v0": "0xa", + "31,ra": "0x8", + PC: "0x10", + }, + sentinel_errors: [ + { + function: "test", + msg: "Calling convention violations in test: + - Register 18,s2 was used but never saved to memory + - Register 18,s2 value changed but not properly restored", + }, + ], +} +`; diff --git a/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_013.s.snap b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_013.s.snap new file mode 100644 index 000000000..ca9f05292 --- /dev/null +++ b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_013.s.snap @@ -0,0 +1,67 @@ +export const snapshot = {}; + +snapshot[`mips/sentinel/test_mips_sentinels_013.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 19, + "11": 10, + "15": 12, + "16": 32, + "17": 1, + "19": 12, + "20": 3, + "21": 161, + "22": 232, + "23": 35, + "24": 175, + "25": 191, + "268435451": 8, + "27": 8, + "28": 175, + "29": 190, + "3": 5, + "31": 4, + "32": 39, + "33": 190, + "35": 4, + "36": 32, + "37": 19, + "39": 2, + "4": 12, + "40": 143, + "41": 191, + "43": 8, + "44": 143, + "45": 190, + "47": 4, + "48": 39, + "49": 189, + "51": 12, + "52": 3, + "53": 224, + "55": 8, + "7": 16, + "8": 32, + "9": 2, + }, + registers: { + "1,at": "0xc", + "19,s3": "0x2", + "2,v0": "0xa", + "31,ra": "0x8", + PC: "0x10", + }, + sentinel_errors: [ + { + function: "test", + msg: "Calling convention violations in test: + - Register 19,s3 was used but never saved to memory + - Register 19,s3 value changed but not properly restored", + }, + ], +} +`; diff --git a/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_014.s.snap b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_014.s.snap new file mode 100644 index 000000000..ebab8f212 --- /dev/null +++ b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_014.s.snap @@ -0,0 +1,67 @@ +export const snapshot = {}; + +snapshot[`mips/sentinel/test_mips_sentinels_014.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 20, + "11": 10, + "15": 12, + "16": 32, + "17": 1, + "19": 12, + "20": 3, + "21": 161, + "22": 232, + "23": 35, + "24": 175, + "25": 191, + "268435451": 8, + "27": 8, + "28": 175, + "29": 190, + "3": 5, + "31": 4, + "32": 39, + "33": 190, + "35": 4, + "36": 32, + "37": 20, + "39": 2, + "4": 12, + "40": 143, + "41": 191, + "43": 8, + "44": 143, + "45": 190, + "47": 4, + "48": 39, + "49": 189, + "51": 12, + "52": 3, + "53": 224, + "55": 8, + "7": 16, + "8": 32, + "9": 2, + }, + registers: { + "1,at": "0xc", + "2,v0": "0xa", + "20,s4": "0x2", + "31,ra": "0x8", + PC: "0x10", + }, + sentinel_errors: [ + { + function: "test", + msg: "Calling convention violations in test: + - Register 20,s4 was used but never saved to memory + - Register 20,s4 value changed but not properly restored", + }, + ], +} +`; diff --git a/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_015.s.snap b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_015.s.snap new file mode 100644 index 000000000..7afae490d --- /dev/null +++ b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_015.s.snap @@ -0,0 +1,67 @@ +export const snapshot = {}; + +snapshot[`mips/sentinel/test_mips_sentinels_015.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 21, + "11": 10, + "15": 12, + "16": 32, + "17": 1, + "19": 12, + "20": 3, + "21": 161, + "22": 232, + "23": 35, + "24": 175, + "25": 191, + "268435451": 8, + "27": 8, + "28": 175, + "29": 190, + "3": 5, + "31": 4, + "32": 39, + "33": 190, + "35": 4, + "36": 32, + "37": 21, + "39": 2, + "4": 12, + "40": 143, + "41": 191, + "43": 8, + "44": 143, + "45": 190, + "47": 4, + "48": 39, + "49": 189, + "51": 12, + "52": 3, + "53": 224, + "55": 8, + "7": 16, + "8": 32, + "9": 2, + }, + registers: { + "1,at": "0xc", + "2,v0": "0xa", + "21,s5": "0x2", + "31,ra": "0x8", + PC: "0x10", + }, + sentinel_errors: [ + { + function: "test", + msg: "Calling convention violations in test: + - Register 21,s5 was used but never saved to memory + - Register 21,s5 value changed but not properly restored", + }, + ], +} +`; diff --git a/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_016.s.snap b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_016.s.snap new file mode 100644 index 000000000..5a0bf5d4c --- /dev/null +++ b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_016.s.snap @@ -0,0 +1,67 @@ +export const snapshot = {}; + +snapshot[`mips/sentinel/test_mips_sentinels_016.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 22, + "11": 10, + "15": 12, + "16": 32, + "17": 1, + "19": 12, + "20": 3, + "21": 161, + "22": 232, + "23": 35, + "24": 175, + "25": 191, + "268435451": 8, + "27": 8, + "28": 175, + "29": 190, + "3": 5, + "31": 4, + "32": 39, + "33": 190, + "35": 4, + "36": 32, + "37": 22, + "39": 2, + "4": 12, + "40": 143, + "41": 191, + "43": 8, + "44": 143, + "45": 190, + "47": 4, + "48": 39, + "49": 189, + "51": 12, + "52": 3, + "53": 224, + "55": 8, + "7": 16, + "8": 32, + "9": 2, + }, + registers: { + "1,at": "0xc", + "2,v0": "0xa", + "22,s6": "0x2", + "31,ra": "0x8", + PC: "0x10", + }, + sentinel_errors: [ + { + function: "test", + msg: "Calling convention violations in test: + - Register 22,s6 was used but never saved to memory + - Register 22,s6 value changed but not properly restored", + }, + ], +} +`; diff --git a/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_017.s.snap b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_017.s.snap new file mode 100644 index 000000000..f68e2030d --- /dev/null +++ b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_017.s.snap @@ -0,0 +1,67 @@ +export const snapshot = {}; + +snapshot[`mips/sentinel/test_mips_sentinels_017.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 23, + "11": 10, + "15": 12, + "16": 32, + "17": 1, + "19": 12, + "20": 3, + "21": 161, + "22": 232, + "23": 35, + "24": 175, + "25": 191, + "268435451": 8, + "27": 8, + "28": 175, + "29": 190, + "3": 5, + "31": 4, + "32": 39, + "33": 190, + "35": 4, + "36": 32, + "37": 23, + "39": 2, + "4": 12, + "40": 143, + "41": 191, + "43": 8, + "44": 143, + "45": 190, + "47": 4, + "48": 39, + "49": 189, + "51": 12, + "52": 3, + "53": 224, + "55": 8, + "7": 16, + "8": 32, + "9": 2, + }, + registers: { + "1,at": "0xc", + "2,v0": "0xa", + "23,s7": "0x2", + "31,ra": "0x8", + PC: "0x10", + }, + sentinel_errors: [ + { + function: "test", + msg: "Calling convention violations in test: + - Register 23,s7 was used but never saved to memory + - Register 23,s7 value changed but not properly restored", + }, + ], +} +`; diff --git a/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_018.s.snap b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_018.s.snap new file mode 100644 index 000000000..27c5a83da --- /dev/null +++ b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_018.s.snap @@ -0,0 +1,39 @@ +export const snapshot = {}; + +snapshot[`mips/sentinel/test_mips_sentinels_018.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 29, + "11": 10, + "15": 12, + "16": 35, + "17": 189, + "19": 4, + "20": 3, + "21": 224, + "23": 8, + "3": 5, + "4": 12, + "7": 16, + "8": 32, + "9": 2, + }, + registers: { + "2,v0": "0xa", + "29,sp": "0x9", + "31,ra": "0x8", + PC: "0x10", + }, + sentinel_errors: [ + { + function: "test", + msg: "Calling convention violations in test: + - Stack pointer not restored: entered at 0x5, exited at 0x9", + }, + ], +} +`; diff --git a/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_019.s.snap b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_019.s.snap new file mode 100644 index 000000000..5cc2a97be --- /dev/null +++ b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_019.s.snap @@ -0,0 +1,64 @@ +export const snapshot = {}; + +snapshot[`mips/sentinel/test_mips_sentinels_019.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 8, + "11": 20, + "12": 32, + "13": 2, + "15": 10, + "19": 12, + "20": 32, + "21": 1, + "23": 12, + "24": 3, + "25": 161, + "26": 232, + "268435451": 12, + "27": 35, + "28": 175, + "29": 191, + "3": 1, + "31": 8, + "32": 175, + "33": 190, + "35": 4, + "36": 39, + "37": 190, + "39": 4, + "4": 32, + "40": 32, + "41": 8, + "43": 2, + "44": 143, + "45": 191, + "47": 8, + "48": 143, + "49": 190, + "5": 4, + "51": 4, + "52": 39, + "53": 189, + "55": 12, + "56": 3, + "57": 224, + "59": 8, + "7": 5, + "8": 12, + }, + registers: { + "1,at": "0xc", + "2,v0": "0xa", + "31,ra": "0xc", + "4,a0": "0x5", + "8,t0": "0x2", + PC: "0x14", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_020.s.snap b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_020.s.snap new file mode 100644 index 000000000..37c630c32 --- /dev/null +++ b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_020.s.snap @@ -0,0 +1,64 @@ +export const snapshot = {}; + +snapshot[`mips/sentinel/test_mips_sentinels_020.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 9, + "11": 20, + "12": 32, + "13": 2, + "15": 10, + "19": 12, + "20": 32, + "21": 1, + "23": 12, + "24": 3, + "25": 161, + "26": 232, + "268435451": 12, + "27": 35, + "28": 175, + "29": 191, + "3": 1, + "31": 8, + "32": 175, + "33": 190, + "35": 4, + "36": 39, + "37": 190, + "39": 4, + "4": 32, + "40": 32, + "41": 9, + "43": 2, + "44": 143, + "45": 191, + "47": 8, + "48": 143, + "49": 190, + "5": 4, + "51": 4, + "52": 39, + "53": 189, + "55": 12, + "56": 3, + "57": 224, + "59": 8, + "7": 5, + "8": 12, + }, + registers: { + "1,at": "0xc", + "2,v0": "0xa", + "31,ra": "0xc", + "4,a0": "0x5", + "9,t1": "0x2", + PC: "0x14", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_021.s.snap b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_021.s.snap new file mode 100644 index 000000000..09f8476b4 --- /dev/null +++ b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_021.s.snap @@ -0,0 +1,64 @@ +export const snapshot = {}; + +snapshot[`mips/sentinel/test_mips_sentinels_021.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 10, + "11": 20, + "12": 32, + "13": 2, + "15": 10, + "19": 12, + "20": 32, + "21": 1, + "23": 12, + "24": 3, + "25": 161, + "26": 232, + "268435451": 12, + "27": 35, + "28": 175, + "29": 191, + "3": 1, + "31": 8, + "32": 175, + "33": 190, + "35": 4, + "36": 39, + "37": 190, + "39": 4, + "4": 32, + "40": 32, + "41": 10, + "43": 2, + "44": 143, + "45": 191, + "47": 8, + "48": 143, + "49": 190, + "5": 4, + "51": 4, + "52": 39, + "53": 189, + "55": 12, + "56": 3, + "57": 224, + "59": 8, + "7": 5, + "8": 12, + }, + registers: { + "1,at": "0xc", + "10,t2": "0x2", + "2,v0": "0xa", + "31,ra": "0xc", + "4,a0": "0x5", + PC: "0x14", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_022.s.snap b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_022.s.snap new file mode 100644 index 000000000..45b69ce9e --- /dev/null +++ b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_022.s.snap @@ -0,0 +1,64 @@ +export const snapshot = {}; + +snapshot[`mips/sentinel/test_mips_sentinels_022.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 11, + "11": 20, + "12": 32, + "13": 2, + "15": 10, + "19": 12, + "20": 32, + "21": 1, + "23": 12, + "24": 3, + "25": 161, + "26": 232, + "268435451": 12, + "27": 35, + "28": 175, + "29": 191, + "3": 1, + "31": 8, + "32": 175, + "33": 190, + "35": 4, + "36": 39, + "37": 190, + "39": 4, + "4": 32, + "40": 32, + "41": 11, + "43": 2, + "44": 143, + "45": 191, + "47": 8, + "48": 143, + "49": 190, + "5": 4, + "51": 4, + "52": 39, + "53": 189, + "55": 12, + "56": 3, + "57": 224, + "59": 8, + "7": 5, + "8": 12, + }, + registers: { + "1,at": "0xc", + "11,t3": "0x2", + "2,v0": "0xa", + "31,ra": "0xc", + "4,a0": "0x5", + PC: "0x14", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_023.s.snap b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_023.s.snap new file mode 100644 index 000000000..090bcda82 --- /dev/null +++ b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_023.s.snap @@ -0,0 +1,64 @@ +export const snapshot = {}; + +snapshot[`mips/sentinel/test_mips_sentinels_023.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 12, + "11": 20, + "12": 32, + "13": 2, + "15": 10, + "19": 12, + "20": 32, + "21": 1, + "23": 12, + "24": 3, + "25": 161, + "26": 232, + "268435451": 12, + "27": 35, + "28": 175, + "29": 191, + "3": 1, + "31": 8, + "32": 175, + "33": 190, + "35": 4, + "36": 39, + "37": 190, + "39": 4, + "4": 32, + "40": 32, + "41": 12, + "43": 2, + "44": 143, + "45": 191, + "47": 8, + "48": 143, + "49": 190, + "5": 4, + "51": 4, + "52": 39, + "53": 189, + "55": 12, + "56": 3, + "57": 224, + "59": 8, + "7": 5, + "8": 12, + }, + registers: { + "1,at": "0xc", + "12,t4": "0x2", + "2,v0": "0xa", + "31,ra": "0xc", + "4,a0": "0x5", + PC: "0x14", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_024.s.snap b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_024.s.snap new file mode 100644 index 000000000..2f9d42493 --- /dev/null +++ b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_024.s.snap @@ -0,0 +1,64 @@ +export const snapshot = {}; + +snapshot[`mips/sentinel/test_mips_sentinels_024.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 13, + "11": 20, + "12": 32, + "13": 2, + "15": 10, + "19": 12, + "20": 32, + "21": 1, + "23": 12, + "24": 3, + "25": 161, + "26": 232, + "268435451": 12, + "27": 35, + "28": 175, + "29": 191, + "3": 1, + "31": 8, + "32": 175, + "33": 190, + "35": 4, + "36": 39, + "37": 190, + "39": 4, + "4": 32, + "40": 32, + "41": 13, + "43": 2, + "44": 143, + "45": 191, + "47": 8, + "48": 143, + "49": 190, + "5": 4, + "51": 4, + "52": 39, + "53": 189, + "55": 12, + "56": 3, + "57": 224, + "59": 8, + "7": 5, + "8": 12, + }, + registers: { + "1,at": "0xc", + "13,t5": "0x2", + "2,v0": "0xa", + "31,ra": "0xc", + "4,a0": "0x5", + PC: "0x14", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_025.s.snap b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_025.s.snap new file mode 100644 index 000000000..6aea5b61f --- /dev/null +++ b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_025.s.snap @@ -0,0 +1,64 @@ +export const snapshot = {}; + +snapshot[`mips/sentinel/test_mips_sentinels_025.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 14, + "11": 20, + "12": 32, + "13": 2, + "15": 10, + "19": 12, + "20": 32, + "21": 1, + "23": 12, + "24": 3, + "25": 161, + "26": 232, + "268435451": 12, + "27": 35, + "28": 175, + "29": 191, + "3": 1, + "31": 8, + "32": 175, + "33": 190, + "35": 4, + "36": 39, + "37": 190, + "39": 4, + "4": 32, + "40": 32, + "41": 14, + "43": 2, + "44": 143, + "45": 191, + "47": 8, + "48": 143, + "49": 190, + "5": 4, + "51": 4, + "52": 39, + "53": 189, + "55": 12, + "56": 3, + "57": 224, + "59": 8, + "7": 5, + "8": 12, + }, + registers: { + "1,at": "0xc", + "14,t6": "0x2", + "2,v0": "0xa", + "31,ra": "0xc", + "4,a0": "0x5", + PC: "0x14", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_026.s.snap b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_026.s.snap new file mode 100644 index 000000000..bd81fa898 --- /dev/null +++ b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_026.s.snap @@ -0,0 +1,64 @@ +export const snapshot = {}; + +snapshot[`mips/sentinel/test_mips_sentinels_026.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 15, + "11": 20, + "12": 32, + "13": 2, + "15": 10, + "19": 12, + "20": 32, + "21": 1, + "23": 12, + "24": 3, + "25": 161, + "26": 232, + "268435451": 12, + "27": 35, + "28": 175, + "29": 191, + "3": 1, + "31": 8, + "32": 175, + "33": 190, + "35": 4, + "36": 39, + "37": 190, + "39": 4, + "4": 32, + "40": 32, + "41": 15, + "43": 2, + "44": 143, + "45": 191, + "47": 8, + "48": 143, + "49": 190, + "5": 4, + "51": 4, + "52": 39, + "53": 189, + "55": 12, + "56": 3, + "57": 224, + "59": 8, + "7": 5, + "8": 12, + }, + registers: { + "1,at": "0xc", + "15,t7": "0x2", + "2,v0": "0xa", + "31,ra": "0xc", + "4,a0": "0x5", + PC: "0x14", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_027.s.snap b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_027.s.snap new file mode 100644 index 000000000..77e2679b1 --- /dev/null +++ b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_027.s.snap @@ -0,0 +1,64 @@ +export const snapshot = {}; + +snapshot[`mips/sentinel/test_mips_sentinels_027.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 24, + "11": 20, + "12": 32, + "13": 2, + "15": 10, + "19": 12, + "20": 32, + "21": 1, + "23": 12, + "24": 3, + "25": 161, + "26": 232, + "268435451": 12, + "27": 35, + "28": 175, + "29": 191, + "3": 1, + "31": 8, + "32": 175, + "33": 190, + "35": 4, + "36": 39, + "37": 190, + "39": 4, + "4": 32, + "40": 32, + "41": 24, + "43": 2, + "44": 143, + "45": 191, + "47": 8, + "48": 143, + "49": 190, + "5": 4, + "51": 4, + "52": 39, + "53": 189, + "55": 12, + "56": 3, + "57": 224, + "59": 8, + "7": 5, + "8": 12, + }, + registers: { + "1,at": "0xc", + "2,v0": "0xa", + "24,t8": "0x2", + "31,ra": "0xc", + "4,a0": "0x5", + PC: "0x14", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_028.s.snap b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_028.s.snap new file mode 100644 index 000000000..01c45e942 --- /dev/null +++ b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_028.s.snap @@ -0,0 +1,64 @@ +export const snapshot = {}; + +snapshot[`mips/sentinel/test_mips_sentinels_028.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 25, + "11": 20, + "12": 32, + "13": 2, + "15": 10, + "19": 12, + "20": 32, + "21": 1, + "23": 12, + "24": 3, + "25": 161, + "26": 232, + "268435451": 12, + "27": 35, + "28": 175, + "29": 191, + "3": 1, + "31": 8, + "32": 175, + "33": 190, + "35": 4, + "36": 39, + "37": 190, + "39": 4, + "4": 32, + "40": 32, + "41": 25, + "43": 2, + "44": 143, + "45": 191, + "47": 8, + "48": 143, + "49": 190, + "5": 4, + "51": 4, + "52": 39, + "53": 189, + "55": 12, + "56": 3, + "57": 224, + "59": 8, + "7": 5, + "8": 12, + }, + registers: { + "1,at": "0xc", + "2,v0": "0xa", + "25,t9": "0x2", + "31,ra": "0xc", + "4,a0": "0x5", + PC: "0x14", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_029.s.snap b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_029.s.snap new file mode 100644 index 000000000..56f652ae1 --- /dev/null +++ b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_029.s.snap @@ -0,0 +1,59 @@ +export const snapshot = {}; + +snapshot[`mips/sentinel/test_mips_sentinels_029.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 2, + "11": 10, + "15": 12, + "16": 32, + "17": 1, + "19": 12, + "20": 3, + "21": 161, + "22": 232, + "23": 35, + "24": 175, + "25": 191, + "268435451": 8, + "27": 8, + "28": 175, + "29": 190, + "3": 5, + "31": 4, + "32": 39, + "33": 190, + "35": 4, + "36": 32, + "37": 2, + "39": 2, + "4": 12, + "40": 143, + "41": 191, + "43": 8, + "44": 143, + "45": 190, + "47": 4, + "48": 39, + "49": 189, + "51": 12, + "52": 3, + "53": 224, + "55": 8, + "7": 16, + "8": 32, + "9": 2, + }, + registers: { + "1,at": "0xc", + "2,v0": "0xa", + "31,ra": "0x8", + PC: "0x10", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_030.s.snap b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_030.s.snap new file mode 100644 index 000000000..4bf706229 --- /dev/null +++ b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_030.s.snap @@ -0,0 +1,60 @@ +export const snapshot = {}; + +snapshot[`mips/sentinel/test_mips_sentinels_030.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 3, + "11": 10, + "15": 12, + "16": 32, + "17": 1, + "19": 12, + "20": 3, + "21": 161, + "22": 232, + "23": 35, + "24": 175, + "25": 191, + "268435451": 8, + "27": 8, + "28": 175, + "29": 190, + "3": 5, + "31": 4, + "32": 39, + "33": 190, + "35": 4, + "36": 32, + "37": 3, + "39": 2, + "4": 12, + "40": 143, + "41": 191, + "43": 8, + "44": 143, + "45": 190, + "47": 4, + "48": 39, + "49": 189, + "51": 12, + "52": 3, + "53": 224, + "55": 8, + "7": 16, + "8": 32, + "9": 2, + }, + registers: { + "1,at": "0xc", + "2,v0": "0xa", + "3,v1": "0x2", + "31,ra": "0x8", + PC: "0x10", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_031.s.snap b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_031.s.snap new file mode 100644 index 000000000..79eb6925b --- /dev/null +++ b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_031.s.snap @@ -0,0 +1,49 @@ +export const snapshot = {}; + +snapshot[`mips/sentinel/test_mips_sentinels_031.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 16, + "11": 10, + "15": 12, + "16": 32, + "17": 1, + "19": 8, + "20": 3, + "21": 161, + "22": 232, + "23": 35, + "24": 175, + "25": 176, + "268435447": 2, + "28": 32, + "29": 16, + "3": 2, + "31": 2, + "32": 143, + "33": 176, + "36": 39, + "37": 189, + "39": 8, + "4": 12, + "40": 3, + "41": 224, + "43": 8, + "7": 16, + "8": 32, + "9": 2, + }, + registers: { + "1,at": "0x8", + "16,s0": "0x2", + "2,v0": "0xa", + "31,ra": "0x8", + PC: "0x10", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_032.s.snap b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_032.s.snap new file mode 100644 index 000000000..8564afcd1 --- /dev/null +++ b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_032.s.snap @@ -0,0 +1,53 @@ +export const snapshot = {}; + +snapshot[`mips/sentinel/test_mips_sentinels_032.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 16, + "11": 10, + "15": 12, + "16": 32, + "17": 1, + "19": 4, + "20": 3, + "21": 161, + "22": 232, + "23": 35, + "24": 175, + "25": 176, + "268435451": 5, + "28": 32, + "29": 16, + "3": 5, + "31": 5, + "32": 39, + "33": 189, + "35": 4, + "36": 3, + "37": 224, + "39": 8, + "4": 12, + "7": 16, + "8": 32, + "9": 2, + }, + registers: { + "1,at": "0x4", + "16,s0": "0x5", + "2,v0": "0xa", + "31,ra": "0x8", + PC: "0x10", + }, + sentinel_errors: [ + { + function: "test", + msg: "Calling convention violations in test: + - Register 16,s0 was saved but never restored", + }, + ], +} +`; diff --git a/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_033.s.snap b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_033.s.snap new file mode 100644 index 000000000..3f434801d --- /dev/null +++ b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_033.s.snap @@ -0,0 +1,56 @@ +export const snapshot = {}; + +snapshot[`mips/sentinel/test_mips_sentinels_033.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 16, + "11": 10, + "15": 12, + "16": 32, + "17": 1, + "19": 8, + "20": 3, + "21": 161, + "22": 232, + "23": 35, + "24": 175, + "25": 176, + "268435447": 2, + "28": 32, + "29": 16, + "3": 2, + "31": 2, + "32": 143, + "33": 176, + "35": 4, + "36": 39, + "37": 189, + "39": 8, + "4": 12, + "40": 3, + "41": 224, + "43": 8, + "7": 16, + "8": 32, + "9": 2, + }, + registers: { + "1,at": "0x8", + "2,v0": "0xa", + "31,ra": "0x8", + PC: "0x10", + }, + sentinel_errors: [ + { + function: "test", + msg: "Calling convention violations in test: + - Register 16,s0 saved at 0xffffff4 but restored from 0xffffff8 + - Register 16,s0 value changed but not properly restored", + }, + ], +} +`; diff --git a/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_034.s.snap b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_034.s.snap new file mode 100644 index 000000000..44782e1fa --- /dev/null +++ b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_034.s.snap @@ -0,0 +1,55 @@ +export const snapshot = {}; + +snapshot[`mips/sentinel/test_mips_sentinels_034.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 16, + "11": 10, + "15": 12, + "16": 32, + "17": 1, + "19": 8, + "20": 3, + "21": 161, + "22": 232, + "23": 35, + "24": 175, + "25": 176, + "268435447": 2, + "28": 32, + "29": 16, + "3": 2, + "31": 2, + "32": 135, + "33": 176, + "36": 39, + "37": 189, + "39": 8, + "4": 12, + "40": 3, + "41": 224, + "43": 8, + "7": 16, + "8": 32, + "9": 2, + }, + registers: { + "1,at": "0x8", + "2,v0": "0xa", + "31,ra": "0x8", + PC: "0x10", + }, + sentinel_errors: [ + { + function: "test", + msg: "Calling convention violations in test: + - Register 16,s0 saved with 4 bytes but restored with 2 bytes + - Register 16,s0 value changed but not properly restored", + }, + ], +} +`; diff --git a/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_035.s.snap b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_035.s.snap new file mode 100644 index 000000000..bcd912727 --- /dev/null +++ b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_035.s.snap @@ -0,0 +1,55 @@ +export const snapshot = {}; + +snapshot[`mips/sentinel/test_mips_sentinels_035.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 32, + "1": 16, + "11": 10, + "15": 12, + "16": 32, + "17": 1, + "19": 8, + "20": 3, + "21": 161, + "22": 232, + "23": 35, + "24": 175, + "25": 176, + "28": 175, + "29": 168, + "3": 2, + "32": 32, + "33": 16, + "35": 2, + "36": 143, + "37": 176, + "4": 12, + "40": 39, + "41": 189, + "43": 8, + "44": 3, + "45": 224, + "47": 8, + "7": 16, + "8": 32, + "9": 2, + }, + registers: { + "1,at": "0x8", + "2,v0": "0xa", + "31,ra": "0x8", + PC: "0x10", + }, + sentinel_errors: [ + { + function: "test", + msg: "Calling convention violations in test: + - Register 16,s0 value changed but not properly restored", + }, + ], +} +`; diff --git a/tests/arch/__snapshots__/riscv/correct/examples/test_riscv_example_001.s.snap b/tests/arch/__snapshots__/riscv/correct/examples/test_riscv_example_001.s.snap new file mode 100644 index 000000000..bbbd78127 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/correct/examples/test_riscv_example_001.s.snap @@ -0,0 +1,124 @@ +export const snapshot = {}; + +snapshot[`riscv/correct/examples/test_riscv_example_001.s 1`] = ` +{ + display: "1234", + error: false, + keyboard: "", + memory: { + "1": 32, + "10": 5, + "11": 3, + "13": 16, + "14": 8, + "15": 147, + "19": 115, + "2": 5, + "2097152": 12, + "2097155": 34, + "2097156": 255, + "2097157": 255, + "2097158": 233, + "2097159": 210, + "2097160": 67, + "2097161": 228, + "2097162": 41, + "2097163": 55, + "2097164": 64, + "2097165": 195, + "2097166": 6, + "2097167": 171, + "2097168": 133, + "2097169": 30, + "2097170": 184, + "2097171": 82, + "2097172": 84, + "2097173": 104, + "2097174": 105, + "2097175": 115, + "2097176": 32, + "2097177": 105, + "2097178": 115, + "2097179": 32, + "2097180": 97, + "2097181": 32, + "2097182": 115, + "2097183": 116, + "2097184": 114, + "2097185": 105, + "2097186": 110, + "2097187": 103, + "2097189": 84, + "2097190": 104, + "2097191": 105, + "2097192": 115, + "2097193": 32, + "2097194": 105, + "2097195": 115, + "2097196": 32, + "2097197": 97, + "2097198": 110, + "2097199": 111, + "2097200": 116, + "2097201": 104, + "2097202": 101, + "2097203": 114, + "2097204": 32, + "2097205": 115, + "2097206": 116, + "2097207": 114, + "2097208": 105, + "2097209": 110, + "2097210": 103, + "21": 32, + "22": 5, + "23": 23, + "24": 254, + "25": 229, + "26": 5, + "27": 19, + "29": 5, + "3": 23, + "30": 21, + "31": 3, + "33": 16, + "34": 8, + "35": 147, + "39": 115, + "41": 32, + "42": 5, + "43": 23, + "44": 254, + "45": 69, + "46": 5, + "47": 19, + "49": 5, + "5": 5, + "50": 48, + "51": 7, + "53": 32, + "54": 5, + "55": 23, + "56": 253, + "57": 133, + "58": 5, + "59": 19, + "6": 5, + "61": 5, + "62": 48, + "63": 39, + "66": 128, + "67": 103, + "7": 19, + "9": 5, + }, + registers: { + "f0,ft0": "0x40c306ab851eb852", + "x10,a0": "0x20000c", + "x17,a7": "0x1", + mtime: "0x11", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/correct/examples/test_riscv_example_002.s.snap b/tests/arch/__snapshots__/riscv/correct/examples/test_riscv_example_002.s.snap new file mode 100644 index 000000000..5fd239c1c --- /dev/null +++ b/tests/arch/__snapshots__/riscv/correct/examples/test_riscv_example_002.s.snap @@ -0,0 +1,61 @@ +export const snapshot = {}; + +snapshot[`riscv/correct/examples/test_riscv_example_002.s 1`] = ` +{ + display: "4", + error: false, + keyboard: "", + memory: { + "1": 160, + "10": 3, + "11": 147, + "12": 2, + "13": 16, + "14": 14, + "15": 19, + "17": 98, + "18": 142, + "19": 179, + "2": 2, + "20": 65, + "21": 195, + "22": 142, + "23": 179, + "24": 3, + "25": 206, + "26": 14, + "27": 179, + "28": 2, + "29": 83, + "3": 147, + "30": 206, + "31": 179, + "33": 14, + "34": 133, + "35": 19, + "37": 16, + "38": 8, + "39": 147, + "43": 115, + "46": 128, + "47": 103, + "5": 208, + "6": 3, + "7": 19, + "8": 2, + "9": 208, + }, + registers: { + "x10,a0": "0x4", + "x17,a7": "0x1", + "x28,t3": "0x21", + "x29,t4": "0x4", + "x5,t0": "0xa", + "x6,t1": "0xd", + "x7,t2": "0x2d", + mtime: "0xc", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/correct/examples/test_riscv_example_003.s.snap b/tests/arch/__snapshots__/riscv/correct/examples/test_riscv_example_003.s.snap new file mode 100644 index 000000000..424e76c87 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/correct/examples/test_riscv_example_003.s.snap @@ -0,0 +1,92 @@ +export const snapshot = {}; + +snapshot[`riscv/correct/examples/test_riscv_example_003.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 32, + "10": 174, + "11": 3, + "13": 32, + "14": 3, + "15": 23, + "16": 255, + "17": 131, + "18": 3, + "19": 19, + "2": 2, + "2097155": 14, + "2097156": 120, + "2097159": 22, + "2097163": 14, + "2097164": 120, + "2097167": 22, + "21": 3, + "22": 14, + "23": 131, + "25": 32, + "26": 3, + "27": 151, + "28": 254, + "29": 227, + "3": 151, + "30": 131, + "31": 147, + "33": 3, + "34": 159, + "35": 3, + "37": 32, + "38": 2, + "39": 151, + "40": 254, + "41": 66, + "42": 130, + "43": 147, + "44": 1, + "45": 194, + "46": 160, + "47": 35, + "49": 32, + "5": 2, + "50": 2, + "51": 151, + "52": 253, + "53": 194, + "54": 130, + "55": 147, + "56": 1, + "57": 210, + "58": 128, + "59": 35, + "6": 130, + "61": 32, + "62": 2, + "63": 151, + "64": 253, + "65": 34, + "66": 130, + "67": 147, + "68": 1, + "69": 226, + "7": 147, + "70": 144, + "71": 35, + "74": 128, + "75": 103, + "9": 2, + }, + registers: { + "x28,t3": "0xe", + "x29,t4": "0x78", + "x30,t5": "0x16", + "x5,t0": "0x20000e", + "x6,t1": "0x200004", + "x7,t2": "0x200006", + mtime: "0x13", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/correct/examples/test_riscv_example_004.s.snap b/tests/arch/__snapshots__/riscv/correct/examples/test_riscv_example_004.s.snap new file mode 100644 index 000000000..c6b7e9d3d --- /dev/null +++ b/tests/arch/__snapshots__/riscv/correct/examples/test_riscv_example_004.s.snap @@ -0,0 +1,133 @@ +export const snapshot = {}; + +snapshot[`riscv/correct/examples/test_riscv_example_004.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 32, + "10": 3, + "11": 23, + "13": 3, + "14": 3, + "15": 19, + "17": 32, + "18": 3, + "19": 151, + "2": 2, + "2097152": 64, + "2097153": 65, + "2097154": 69, + "2097155": 161, + "2097156": 202, + "2097157": 192, + "2097158": 131, + "2097159": 18, + "2097160": 64, + "2097161": 38, + "2097162": 226, + "2097163": 208, + "2097164": 229, + "2097165": 96, + "2097166": 65, + "2097167": 137, + "2097168": 64, + "2097169": 132, + "2097170": 203, + "2097171": 51, + "2097172": 51, + "2097173": 51, + "2097174": 51, + "2097175": 51, + "2097176": 64, + "2097177": 81, + "2097178": 69, + "2097179": 161, + "2097180": 202, + "2097181": 192, + "2097182": 131, + "2097183": 18, + "2097184": 64, + "2097185": 130, + "2097186": 162, + "2097187": 126, + "2097188": 249, + "2097189": 219, + "2097190": 34, + "2097191": 209, + "2097192": 64, + "2097193": 77, + "2097194": 19, + "2097195": 21, + "2097196": 70, + "2097197": 137, + "2097198": 195, + "2097199": 233, + "21": 3, + "22": 131, + "23": 147, + "25": 32, + "26": 4, + "27": 23, + "29": 4, + "3": 151, + "30": 4, + "31": 19, + "33": 2, + "34": 176, + "35": 7, + "37": 3, + "38": 49, + "39": 7, + "41": 3, + "42": 181, + "43": 7, + "44": 2, + "47": 83, + "48": 10, + "49": 5, + "5": 2, + "50": 2, + "51": 83, + "52": 26, + "53": 37, + "54": 6, + "55": 83, + "57": 4, + "58": 48, + "59": 39, + "6": 130, + "61": 132, + "62": 4, + "63": 19, + "65": 68, + "66": 48, + "67": 39, + "69": 132, + "7": 147, + "70": 4, + "71": 19, + "73": 196, + "74": 48, + "75": 39, + "78": 128, + "79": 103, + "9": 32, + }, + registers: { + "f0,ft0": "0x405145a1cac08312", + "f10,fa0": "0x4084cb3333333333", + "f12,fa2": "0x404d13154689c3e9", + "f2,ft2": "0x4026e2d0e5604189", + "f4,ft4": "0x4082a27ef9db22d1", + "x5,t0": "0x200000", + "x6,t1": "0x200008", + "x7,t2": "0x200010", + "x8,fp,s0": "0x200028", + mtime: "0x14", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/correct/examples/test_riscv_example_005.s.snap b/tests/arch/__snapshots__/riscv/correct/examples/test_riscv_example_005.s.snap new file mode 100644 index 000000000..9087fc2cf --- /dev/null +++ b/tests/arch/__snapshots__/riscv/correct/examples/test_riscv_example_005.s.snap @@ -0,0 +1,52 @@ +export const snapshot = {}; + +snapshot[`riscv/correct/examples/test_riscv_example_005.s 1`] = ` +{ + display: "45", + error: false, + keyboard: "", + memory: { + "1": 32, + "10": 130, + "11": 131, + "14": 3, + "15": 19, + "18": 5, + "19": 19, + "2": 2, + "2097152": 10, + "21": 83, + "22": 88, + "23": 99, + "25": 101, + "26": 5, + "27": 51, + "29": 19, + "3": 151, + "30": 3, + "31": 19, + "32": 254, + "34": 10, + "35": 227, + "37": 16, + "38": 8, + "39": 147, + "43": 115, + "46": 128, + "47": 103, + "5": 2, + "6": 130, + "7": 147, + "9": 2, + }, + registers: { + "x10,a0": "0x2d", + "x17,a7": "0x1", + "x5,t0": "0xa", + "x6,t1": "0xa", + mtime: "0x31", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/correct/examples/test_riscv_example_006.s.snap b/tests/arch/__snapshots__/riscv/correct/examples/test_riscv_example_006.s.snap new file mode 100644 index 000000000..b2b9594e4 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/correct/examples/test_riscv_example_006.s.snap @@ -0,0 +1,54 @@ +export const snapshot = {}; + +snapshot[`riscv/correct/examples/test_riscv_example_006.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 64, + "10": 14, + "11": 19, + "13": 94, + "14": 88, + "15": 99, + "16": 2, + "17": 32, + "18": 14, + "19": 19, + "2": 2, + "21": 160, + "22": 8, + "23": 147, + "27": 115, + "29": 176, + "3": 147, + "30": 14, + "31": 147, + "32": 34, + "33": 176, + "34": 15, + "35": 19, + "36": 254, + "38": 6, + "39": 227, + "42": 128, + "43": 103, + "5": 32, + "6": 3, + "7": 19, + "9": 80, + }, + registers: { + "x17,a7": "0xa", + "x28,t3": "0x22", + "x29,t4": "0xb", + "x30,t5": "0x22b", + "x5,t0": "0x4", + "x6,t1": "0x2", + mtime: "0xa", + pc: "0x1c", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/correct/examples/test_riscv_example_007.s.snap b/tests/arch/__snapshots__/riscv/correct/examples/test_riscv_example_007.s.snap new file mode 100644 index 000000000..019a7bd29 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/correct/examples/test_riscv_example_007.s.snap @@ -0,0 +1,74 @@ +export const snapshot = {}; + +snapshot[`riscv/correct/examples/test_riscv_example_007.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 16, + "10": 15, + "11": 23, + "12": 255, + "13": 143, + "14": 15, + "15": 19, + "18": 2, + "19": 147, + "2": 14, + "2097155": 1, + "2097159": 2, + "2097163": 3, + "2097167": 4, + "2097171": 5, + "22": 3, + "23": 19, + "25": 80, + "26": 3, + "27": 147, + "29": 115, + "3": 19, + "30": 14, + "31": 99, + "32": 3, + "33": 211, + "34": 15, + "35": 179, + "37": 15, + "38": 47, + "39": 131, + "40": 1, + "41": 242, + "42": 130, + "43": 179, + "44": 1, + "45": 195, + "46": 3, + "47": 51, + "49": 79, + "5": 64, + "50": 15, + "51": 19, + "52": 254, + "54": 4, + "55": 227, + "58": 128, + "59": 103, + "6": 14, + "7": 147, + "9": 32, + }, + registers: { + "x28,t3": "0x1", + "x29,t4": "0x4", + "x30,t5": "0x200014", + "x31,t6": "0x5", + "x5,t0": "0xf", + "x6,t1": "0x5", + "x7,t2": "0x5", + mtime: "0x2c", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/correct/examples/test_riscv_example_008.s.snap b/tests/arch/__snapshots__/riscv/correct/examples/test_riscv_example_008.s.snap new file mode 100644 index 000000000..41e88affb --- /dev/null +++ b/tests/arch/__snapshots__/riscv/correct/examples/test_riscv_example_008.s.snap @@ -0,0 +1,167 @@ +export const snapshot = {}; + +snapshot[`riscv/correct/examples/test_riscv_example_008.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 32, + "10": 3, + "11": 55, + "12": 4, + "13": 3, + "14": 3, + "15": 19, + "17": 64, + "18": 3, + "19": 147, + "2": 2, + "2097152": 52, + "2097156": 52, + "2097160": 52, + "2097164": 52, + "2097168": 35, + "2097169": 69, + "2097173": 67, + "2097174": 34, + "2097175": 16, + "2097176": 119, + "2097177": 81, + "2097178": 33, + "2097179": 32, + "2097180": 20, + "2097181": 20, + "2097182": 20, + "2097183": 20, + "2097186": 2, + "2097187": 20, + "2097188": 68, + "2097189": 85, + "2097190": 17, + "2097191": 34, + "2097192": 170, + "2097193": 191, + "2097194": 240, + "2097195": 18, + "2097196": 119, + "2097197": 208, + "2097202": 255, + "2097203": 35, + "2097204": 18, + "2097205": 52, + "2097206": 86, + "2097207": 120, + "2097208": 135, + "2097209": 101, + "2097210": 67, + "2097211": 33, + "2097212": 51, + "2097213": 68, + "2097214": 17, + "2097215": 36, + "2097216": 52, + "2097220": 52, + "2097224": 52, + "2097228": 52, + "2097232": 35, + "2097233": 69, + "2097237": 67, + "2097238": 34, + "2097239": 16, + "2097240": 119, + "2097241": 81, + "2097242": 33, + "2097243": 32, + "2097244": 20, + "2097245": 20, + "2097246": 20, + "2097247": 20, + "2097250": 2, + "2097251": 20, + "2097252": 68, + "2097253": 85, + "2097254": 17, + "2097255": 34, + "2097256": 170, + "2097257": 191, + "2097258": 240, + "2097259": 18, + "2097260": 119, + "2097261": 208, + "2097266": 255, + "2097267": 35, + "2097268": 18, + "2097269": 52, + "2097270": 86, + "2097271": 120, + "2097272": 135, + "2097273": 101, + "2097274": 67, + "2097275": 33, + "2097276": 51, + "2097277": 68, + "2097278": 17, + "2097279": 36, + "21": 64, + "22": 14, + "23": 19, + "26": 14, + "27": 179, + "3": 151, + "30": 15, + "31": 51, + "32": 3, + "33": 211, + "34": 134, + "35": 99, + "36": 1, + "37": 238, + "38": 14, + "39": 99, + "41": 2, + "42": 160, + "43": 7, + "45": 3, + "46": 32, + "47": 39, + "49": 66, + "5": 2, + "50": 130, + "51": 147, + "53": 67, + "54": 3, + "55": 19, + "57": 31, + "58": 15, + "59": 19, + "6": 130, + "60": 254, + "62": 4, + "63": 227, + "65": 30, + "66": 142, + "67": 147, + "7": 147, + "70": 15, + "71": 51, + "72": 252, + "74": 12, + "75": 227, + "78": 128, + "79": 103, + "9": 32, + }, + registers: { + "f0,ft0": "0xffffffff33441124", + "x28,t3": "0x4", + "x29,t4": "0x4", + "x5,t0": "0x200040", + "x6,t1": "0x200080", + "x7,t2": "0x4", + mtime: "0x8e", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/correct/examples/test_riscv_example_009.s.snap b/tests/arch/__snapshots__/riscv/correct/examples/test_riscv_example_009.s.snap new file mode 100644 index 000000000..948839d47 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/correct/examples/test_riscv_example_009.s.snap @@ -0,0 +1,177 @@ +export const snapshot = {}; + +snapshot[`riscv/correct/examples/test_riscv_example_009.s 1`] = ` +{ + display: " +Please, insert the first number: +Please, insert the second number: +The result is: 579 +", + error: false, + keyboard: " 123 456", + memory: { + "1": 32, + "10": 8, + "103": 115, + "106": 128, + "107": 103, + "11": 147, + "15": 115, + "17": 80, + "18": 8, + "19": 147, + "2": 5, + "2097152": 10, + "2097153": 80, + "2097154": 108, + "2097155": 101, + "2097156": 97, + "2097157": 115, + "2097158": 101, + "2097159": 44, + "2097160": 32, + "2097161": 105, + "2097162": 110, + "2097163": 115, + "2097164": 101, + "2097165": 114, + "2097166": 116, + "2097167": 32, + "2097168": 116, + "2097169": 104, + "2097170": 101, + "2097171": 32, + "2097172": 102, + "2097173": 105, + "2097174": 114, + "2097175": 115, + "2097176": 116, + "2097177": 32, + "2097178": 110, + "2097179": 117, + "2097180": 109, + "2097181": 98, + "2097182": 101, + "2097183": 114, + "2097184": 58, + "2097185": 32, + "2097187": 10, + "2097188": 80, + "2097189": 108, + "2097190": 101, + "2097191": 97, + "2097192": 115, + "2097193": 101, + "2097194": 44, + "2097195": 32, + "2097196": 105, + "2097197": 110, + "2097198": 115, + "2097199": 101, + "2097200": 114, + "2097201": 116, + "2097202": 32, + "2097203": 116, + "2097204": 104, + "2097205": 101, + "2097206": 32, + "2097207": 115, + "2097208": 101, + "2097209": 99, + "2097210": 111, + "2097211": 110, + "2097212": 100, + "2097213": 32, + "2097214": 110, + "2097215": 117, + "2097216": 109, + "2097217": 98, + "2097218": 101, + "2097219": 114, + "2097220": 58, + "2097221": 32, + "2097223": 10, + "2097224": 84, + "2097225": 104, + "2097226": 101, + "2097227": 32, + "2097228": 114, + "2097229": 101, + "2097230": 115, + "2097231": 117, + "2097232": 108, + "2097233": 116, + "2097234": 32, + "2097235": 105, + "2097236": 115, + "2097237": 58, + "2097238": 32, + "2097240": 10, + "23": 115, + "25": 5, + "26": 2, + "27": 179, + "29": 32, + "3": 23, + "30": 5, + "31": 23, + "33": 117, + "34": 5, + "35": 19, + "37": 64, + "38": 8, + "39": 147, + "43": 115, + "45": 80, + "46": 8, + "47": 147, + "5": 5, + "51": 115, + "53": 5, + "54": 3, + "55": 51, + "57": 98, + "58": 131, + "59": 179, + "6": 5, + "61": 32, + "62": 5, + "63": 23, + "65": 181, + "66": 5, + "67": 19, + "69": 64, + "7": 19, + "70": 8, + "71": 147, + "75": 115, + "77": 3, + "78": 133, + "79": 51, + "81": 16, + "82": 8, + "83": 147, + "87": 115, + "89": 32, + "9": 64, + "90": 5, + "91": 23, + "93": 5, + "94": 5, + "95": 19, + "97": 64, + "98": 8, + "99": 147, + }, + registers: { + "x10,a0": "0x200058", + "x17,a7": "0x4", + "x5,t0": "0x7b", + "x6,t1": "0x1c8", + "x7,t2": "0x243", + mtime: "0x1b", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/correct/examples/test_riscv_example_010.s.snap b/tests/arch/__snapshots__/riscv/correct/examples/test_riscv_example_010.s.snap new file mode 100644 index 000000000..7734d0aa9 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/correct/examples/test_riscv_example_010.s.snap @@ -0,0 +1,223 @@ +export const snapshot = {}; + +snapshot[`riscv/correct/examples/test_riscv_example_010.s 1`] = ` +{ + display: "Insert the string length (no more than 100 characters) Insert the string This is a very long string with many characters and a lot of data. :) 123 +", + error: false, + keyboard: " 74 This is a very long string with many characters and a lot of data. :) 123 +", + memory: { + "1": 32, + "10": 8, + "11": 147, + "15": 115, + "17": 80, + "18": 8, + "19": 147, + "2": 5, + "2097152": 73, + "2097153": 110, + "2097154": 115, + "2097155": 101, + "2097156": 114, + "2097157": 116, + "2097158": 32, + "2097159": 116, + "2097160": 104, + "2097161": 101, + "2097162": 32, + "2097163": 115, + "2097164": 116, + "2097165": 114, + "2097166": 105, + "2097167": 110, + "2097168": 103, + "2097169": 32, + "2097170": 108, + "2097171": 101, + "2097172": 110, + "2097173": 103, + "2097174": 116, + "2097175": 104, + "2097176": 32, + "2097177": 40, + "2097178": 110, + "2097179": 111, + "2097180": 32, + "2097181": 109, + "2097182": 111, + "2097183": 114, + "2097184": 101, + "2097185": 32, + "2097186": 116, + "2097187": 104, + "2097188": 97, + "2097189": 110, + "2097190": 32, + "2097191": 49, + "2097192": 48, + "2097193": 48, + "2097194": 32, + "2097195": 99, + "2097196": 104, + "2097197": 97, + "2097198": 114, + "2097199": 97, + "2097200": 99, + "2097201": 116, + "2097202": 101, + "2097203": 114, + "2097204": 115, + "2097205": 41, + "2097206": 32, + "2097208": 73, + "2097209": 110, + "2097210": 115, + "2097211": 101, + "2097212": 114, + "2097213": 116, + "2097214": 32, + "2097215": 116, + "2097216": 104, + "2097217": 101, + "2097218": 32, + "2097219": 115, + "2097220": 116, + "2097221": 114, + "2097222": 105, + "2097223": 110, + "2097224": 103, + "2097225": 32, + "2097227": 84, + "2097228": 104, + "2097229": 105, + "2097230": 115, + "2097231": 32, + "2097232": 105, + "2097233": 115, + "2097234": 32, + "2097235": 97, + "2097236": 32, + "2097237": 118, + "2097238": 101, + "2097239": 114, + "2097240": 121, + "2097241": 32, + "2097242": 108, + "2097243": 111, + "2097244": 110, + "2097245": 103, + "2097246": 32, + "2097247": 115, + "2097248": 116, + "2097249": 114, + "2097250": 105, + "2097251": 110, + "2097252": 103, + "2097253": 32, + "2097254": 119, + "2097255": 105, + "2097256": 116, + "2097257": 104, + "2097258": 32, + "2097259": 109, + "2097260": 97, + "2097261": 110, + "2097262": 121, + "2097263": 32, + "2097264": 99, + "2097265": 104, + "2097266": 97, + "2097267": 114, + "2097268": 97, + "2097269": 99, + "2097270": 116, + "2097271": 101, + "2097272": 114, + "2097273": 115, + "2097274": 32, + "2097275": 97, + "2097276": 110, + "2097277": 100, + "2097278": 32, + "2097279": 97, + "2097280": 32, + "2097281": 108, + "2097282": 111, + "2097283": 116, + "2097284": 32, + "2097285": 111, + "2097286": 102, + "2097287": 32, + "2097288": 100, + "2097289": 97, + "2097290": 116, + "2097291": 97, + "2097292": 46, + "2097293": 32, + "2097294": 58, + "2097295": 41, + "2097296": 32, + "2097297": 49, + "2097298": 50, + "2097299": 51, + "2097300": 10, + "23": 115, + "25": 5, + "26": 2, + "27": 179, + "29": 32, + "3": 23, + "30": 5, + "31": 23, + "32": 1, + "33": 197, + "34": 5, + "35": 19, + "37": 64, + "38": 8, + "39": 147, + "43": 115, + "45": 32, + "46": 5, + "47": 23, + "48": 1, + "49": 245, + "5": 5, + "50": 5, + "51": 19, + "53": 2, + "54": 133, + "55": 179, + "57": 128, + "58": 8, + "59": 147, + "6": 5, + "63": 115, + "65": 32, + "66": 5, + "67": 23, + "69": 181, + "7": 19, + "70": 5, + "71": 19, + "73": 64, + "74": 8, + "75": 147, + "79": 115, + "82": 128, + "83": 103, + "9": 64, + }, + registers: { + "x10,a0": "0x20004b", + "x11,a1": "0x4a", + "x17,a7": "0x4", + "x5,t0": "0x4a", + mtime: "0x15", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/correct/examples/test_riscv_example_011.s.snap b/tests/arch/__snapshots__/riscv/correct/examples/test_riscv_example_011.s.snap new file mode 100644 index 000000000..58a4eaf89 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/correct/examples/test_riscv_example_011.s.snap @@ -0,0 +1,83 @@ +export const snapshot = {}; + +snapshot[`riscv/correct/examples/test_riscv_example_011.s 1`] = ` +{ + display: "-144", + error: false, + keyboard: "", + memory: { + "0": 255, + "1": 193, + "10": 5, + "11": 19, + "12": 251, + "13": 48, + "14": 5, + "15": 147, + "16": 2, + "17": 208, + "18": 6, + "19": 19, + "2": 1, + "20": 1, + "21": 192, + "23": 239, + "24": 2, + "25": 192, + "268435448": 255, + "268435449": 255, + "268435450": 255, + "268435451": 255, + "27": 239, + "29": 16, + "3": 19, + "30": 8, + "31": 147, + "35": 115, + "37": 1, + "38": 32, + "39": 131, + "41": 65, + "42": 1, + "43": 19, + "46": 128, + "47": 103, + "49": 181, + "5": 17, + "50": 3, + "51": 51, + "53": 198, + "54": 3, + "55": 179, + "57": 3, + "58": 5, + "59": 51, + "6": 32, + "61": 3, + "62": 133, + "63": 179, + "66": 128, + "67": 103, + "68": 64, + "69": 181, + "7": 35, + "70": 5, + "71": 51, + "74": 128, + "75": 103, + "8": 1, + "9": 112, + }, + registers: { + "x10,a0": "0xffffff70", + "x11,a1": "0x5a", + "x12,a2": "0x2d", + "x17,a7": "0x1", + "x6,t1": "0xffffffca", + "x7,t2": "0x5a", + mtime: "0x13", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/correct/examples/test_riscv_example_012.s.snap b/tests/arch/__snapshots__/riscv/correct/examples/test_riscv_example_012.s.snap new file mode 100644 index 000000000..08411b28d --- /dev/null +++ b/tests/arch/__snapshots__/riscv/correct/examples/test_riscv_example_012.s.snap @@ -0,0 +1,129 @@ +export const snapshot = {}; + +snapshot[`riscv/correct/examples/test_riscv_example_012.s 1`] = ` +{ + display: "120", + error: false, + keyboard: "", + memory: { + "0": 255, + "1": 193, + "10": 5, + "102": 128, + "103": 103, + "11": 19, + "12": 1, + "13": 128, + "15": 239, + "17": 16, + "18": 8, + "19": 147, + "2": 1, + "23": 115, + "25": 1, + "26": 32, + "268435392": 15, + "268435393": 255, + "268435394": 255, + "268435395": 204, + "268435399": 80, + "268435403": 2, + "268435404": 15, + "268435405": 255, + "268435406": 255, + "268435407": 216, + "268435411": 80, + "268435415": 3, + "268435416": 15, + "268435417": 255, + "268435418": 255, + "268435419": 228, + "268435423": 80, + "268435427": 4, + "268435428": 15, + "268435429": 255, + "268435430": 255, + "268435431": 240, + "268435435": 80, + "268435439": 5, + "268435447": 16, + "268435448": 255, + "268435449": 255, + "268435450": 255, + "268435451": 255, + "27": 131, + "29": 65, + "3": 19, + "30": 1, + "31": 19, + "34": 128, + "35": 103, + "36": 255, + "37": 65, + "38": 1, + "39": 19, + "41": 17, + "42": 36, + "43": 35, + "45": 129, + "46": 34, + "47": 35, + "49": 65, + "5": 17, + "50": 4, + "51": 19, + "53": 32, + "54": 2, + "55": 147, + "57": 85, + "58": 86, + "59": 99, + "6": 32, + "61": 16, + "62": 5, + "63": 19, + "66": 12, + "67": 99, + "68": 254, + "69": 164, + "7": 35, + "70": 46, + "71": 35, + "72": 255, + "73": 245, + "74": 5, + "75": 19, + "76": 253, + "77": 159, + "78": 240, + "79": 239, + "80": 255, + "81": 196, + "82": 35, + "83": 3, + "84": 2, + "85": 101, + "86": 5, + "87": 51, + "89": 129, + "9": 80, + "90": 32, + "91": 131, + "93": 65, + "94": 36, + "95": 3, + "97": 193, + "98": 1, + "99": 19, + }, + registers: { + "x10,a0": "0x78", + "x17,a7": "0x1", + "x5,t0": "0x2", + "x6,t1": "0x5", + mtime: "0x51", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/correct/examples/test_riscv_example_013.s.snap b/tests/arch/__snapshots__/riscv/correct/examples/test_riscv_example_013.s.snap new file mode 100644 index 000000000..312fa8936 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/correct/examples/test_riscv_example_013.s.snap @@ -0,0 +1,78 @@ +export const snapshot = {}; + +snapshot[`riscv/correct/examples/test_riscv_example_013.s 1`] = ` +{ + display: "83116114105110103321051103285847045565832226136128322261361713222613613532226136136322401591601720", + error: false, + keyboard: "", + memory: { + "1": 16, + "10": 130, + "11": 147, + "13": 2, + "14": 133, + "15": 3, + "19": 115, + "2": 8, + "2097152": 83, + "2097153": 116, + "2097154": 114, + "2097155": 105, + "2097156": 110, + "2097157": 103, + "2097158": 32, + "2097159": 105, + "2097160": 110, + "2097161": 32, + "2097162": 85, + "2097163": 84, + "2097164": 70, + "2097165": 45, + "2097166": 56, + "2097167": 58, + "2097168": 32, + "2097169": 226, + "2097170": 136, + "2097171": 128, + "2097172": 32, + "2097173": 226, + "2097174": 136, + "2097175": 171, + "2097176": 32, + "2097177": 226, + "2097178": 136, + "2097179": 135, + "2097180": 32, + "2097181": 226, + "2097182": 136, + "2097183": 136, + "2097184": 32, + "2097185": 240, + "2097186": 159, + "2097187": 160, + "2097188": 172, + "21": 18, + "22": 130, + "23": 147, + "24": 254, + "25": 5, + "26": 26, + "27": 227, + "3": 147, + "30": 128, + "31": 103, + "5": 32, + "6": 2, + "7": 151, + "8": 255, + "9": 194, + }, + registers: { + "x17,a7": "0x1", + "x5,t0": "0x200026", + mtime: "0x9c", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/correct/examples/test_riscv_example_014.s.snap b/tests/arch/__snapshots__/riscv/correct/examples/test_riscv_example_014.s.snap new file mode 100644 index 000000000..6c18595ad --- /dev/null +++ b/tests/arch/__snapshots__/riscv/correct/examples/test_riscv_example_014.s.snap @@ -0,0 +1,221 @@ +export const snapshot = {}; + +snapshot[`riscv/correct/examples/test_riscv_example_014.s 1`] = ` +{ + display: "91", + error: false, + keyboard: "", + memory: { + "0": 255, + "1": 1, + "10": 36, + "101": 133, + "102": 5, + "103": 51, + "105": 1, + "106": 37, + "107": 131, + "109": 129, + "11": 35, + "110": 36, + "111": 3, + "113": 193, + "114": 32, + "115": 131, + "116": 1, + "117": 1, + "118": 1, + "119": 19, + "122": 128, + "123": 103, + "124": 255, + "125": 65, + "126": 1, + "127": 19, + "129": 17, + "13": 145, + "130": 36, + "131": 35, + "133": 177, + "134": 34, + "135": 35, + "137": 193, + "138": 32, + "139": 35, + "14": 34, + "140": 1, + "141": 192, + "143": 239, + "145": 1, + "146": 34, + "147": 131, + "149": 85, + "15": 35, + "150": 5, + "151": 51, + "153": 65, + "154": 37, + "155": 131, + "157": 129, + "158": 32, + "159": 131, + "16": 1, + "161": 193, + "162": 1, + "163": 19, + "166": 128, + "167": 103, + "168": 255, + "169": 129, + "17": 33, + "170": 1, + "171": 19, + "173": 17, + "174": 34, + "175": 35, + "177": 177, + "178": 32, + "179": 35, + "18": 32, + "180": 1, + "181": 128, + "183": 239, + "185": 1, + "186": 37, + "187": 131, + "188": 2, + "189": 64, + "19": 35, + "191": 239, + "193": 65, + "194": 32, + "195": 131, + "197": 129, + "198": 1, + "199": 19, + "2": 1, + "20": 1, + "202": 128, + "203": 103, + "205": 181, + "206": 3, + "207": 51, + "209": 198, + "21": 112, + "210": 3, + "211": 179, + "213": 3, + "214": 5, + "215": 51, + "217": 3, + "218": 133, + "219": 179, + "22": 5, + "222": 128, + "223": 103, + "224": 64, + "225": 181, + "226": 5, + "227": 51, + "23": 19, + "230": 128, + "231": 103, + "24": 251, + "25": 48, + "26": 5, + "268435400": 255, + "268435401": 255, + "268435402": 255, + "268435403": 179, + "268435407": 144, + "268435411": 45, + "268435412": 255, + "268435413": 255, + "268435414": 255, + "268435415": 179, + "268435419": 100, + "268435420": 255, + "268435421": 255, + "268435422": 255, + "268435423": 179, + "268435427": 23, + "268435435": 36, + "268435448": 255, + "268435449": 255, + "268435450": 255, + "268435451": 255, + "27": 147, + "28": 2, + "29": 208, + "3": 19, + "30": 6, + "31": 19, + "32": 2, + "33": 128, + "35": 239, + "37": 5, + "38": 4, + "39": 19, + "41": 16, + "42": 8, + "43": 147, + "47": 115, + "49": 1, + "5": 17, + "50": 41, + "51": 3, + "53": 65, + "54": 36, + "55": 131, + "57": 129, + "58": 36, + "59": 3, + "6": 38, + "61": 193, + "62": 32, + "63": 131, + "64": 1, + "65": 1, + "66": 1, + "67": 19, + "7": 35, + "70": 128, + "71": 103, + "72": 255, + "73": 1, + "74": 1, + "75": 19, + "77": 17, + "78": 38, + "79": 35, + "81": 129, + "82": 36, + "83": 35, + "85": 161, + "86": 34, + "87": 35, + "89": 177, + "9": 129, + "90": 32, + "91": 35, + "93": 5, + "94": 4, + "95": 19, + "96": 1, + "97": 192, + "99": 239, + }, + registers: { + "x10,a0": "0x5b", + "x11,a1": "0xffffffb3", + "x12,a2": "0x2d", + "x17,a7": "0x1", + "x5,t0": "0x2d", + "x6,t1": "0xffffffca", + "x7,t2": "0x5a", + mtime: "0x3a", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/correct/examples/test_riscv_example_015.s.snap b/tests/arch/__snapshots__/riscv/correct/examples/test_riscv_example_015.s.snap new file mode 100644 index 000000000..8ffc81532 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/correct/examples/test_riscv_example_015.s.snap @@ -0,0 +1,126 @@ +export const snapshot = {}; + +snapshot[`riscv/correct/examples/test_riscv_example_015.s 1`] = ` +{ + display: "hello world", + error: false, + keyboard: "", + memory: { + "1": 32, + "10": 2, + "101": 83, + "102": 5, + "103": 163, + "105": 3, + "106": 5, + "107": 19, + "109": 64, + "11": 147, + "110": 8, + "111": 147, + "115": 115, + "117": 160, + "118": 8, + "119": 147, + "123": 115, + "13": 83, + "15": 35, + "16": 6, + "17": 80, + "18": 2, + "19": 147, + "2": 3, + "2097152": 104, + "2097153": 101, + "2097154": 108, + "2097155": 108, + "2097156": 111, + "2097157": 32, + "2097158": 119, + "2097159": 111, + "2097160": 114, + "2097161": 108, + "2097162": 100, + "21": 83, + "23": 163, + "24": 6, + "25": 192, + "26": 2, + "27": 147, + "29": 83, + "3": 55, + "30": 1, + "31": 35, + "32": 6, + "33": 192, + "34": 2, + "35": 147, + "37": 83, + "38": 1, + "39": 163, + "40": 6, + "41": 240, + "42": 2, + "43": 147, + "45": 83, + "46": 2, + "47": 35, + "48": 2, + "5": 3, + "50": 2, + "51": 147, + "53": 83, + "54": 2, + "55": 163, + "56": 7, + "57": 112, + "58": 2, + "59": 147, + "6": 3, + "61": 83, + "62": 3, + "63": 35, + "64": 6, + "65": 240, + "66": 2, + "67": 147, + "69": 83, + "7": 19, + "70": 3, + "71": 163, + "72": 7, + "73": 32, + "74": 2, + "75": 147, + "77": 83, + "78": 4, + "79": 35, + "8": 6, + "80": 6, + "81": 192, + "82": 2, + "83": 147, + "85": 83, + "86": 4, + "87": 163, + "88": 6, + "89": 64, + "9": 128, + "90": 2, + "91": 147, + "93": 83, + "94": 5, + "95": 35, + "98": 2, + "99": 147, + }, + registers: { + "x10,a0": "0x200000", + "x17,a7": "0xa", + "x6,t1": "0x200000", + mtime: "0x1f", + pc: "0x7c", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/correct/examples/test_riscv_tutorial_001.s.snap b/tests/arch/__snapshots__/riscv/correct/examples/test_riscv_tutorial_001.s.snap new file mode 100644 index 000000000..1cbc7b4e0 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/correct/examples/test_riscv_tutorial_001.s.snap @@ -0,0 +1,71 @@ +export const snapshot = {}; + +snapshot[`riscv/correct/examples/test_riscv_tutorial_001.s 1`] = ` +{ + display: "2097152This is a string", + error: false, + keyboard: "", + memory: { + "0": 18, + "1": 48, + "10": 5, + "11": 19, + "13": 5, + "14": 37, + "15": 131, + "17": 16, + "18": 8, + "19": 147, + "2": 3, + "2097152": 18, + "2097153": 52, + "2097154": 86, + "2097155": 120, + "2097156": 84, + "2097157": 104, + "2097158": 105, + "2097159": 115, + "2097160": 32, + "2097161": 105, + "2097162": 115, + "2097163": 32, + "2097164": 97, + "2097165": 32, + "2097166": 115, + "2097167": 116, + "2097168": 114, + "2097169": 105, + "2097170": 110, + "2097171": 103, + "23": 115, + "25": 32, + "26": 5, + "27": 23, + "28": 254, + "29": 197, + "3": 19, + "30": 5, + "31": 19, + "33": 64, + "34": 8, + "35": 147, + "39": 115, + "42": 128, + "43": 103, + "5": 32, + "6": 5, + "7": 23, + "8": 255, + "9": 197, + }, + registers: { + "x10,a0": "0x200004", + "x11,a1": "0x12345678", + "x17,a7": "0x4", + "x6,t1": "0x123", + mtime: "0xb", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/correct/syscalls/test_riscv_syscall_001.s.snap b/tests/arch/__snapshots__/riscv/correct/syscalls/test_riscv_syscall_001.s.snap new file mode 100644 index 000000000..7b15a7f13 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/correct/syscalls/test_riscv_syscall_001.s.snap @@ -0,0 +1,117 @@ +export const snapshot = {}; + +snapshot[`riscv/correct/syscalls/test_riscv_syscall_001.s 1`] = ` +{ + display: "667312034-56781316893491This is a string", + error: false, + keyboard: "", + memory: { + "1": 16, + "10": 5, + "102": 128, + "103": 103, + "11": 19, + "15": 115, + "17": 32, + "18": 3, + "19": 23, + "2": 8, + "20": 255, + "2097152": 120, + "2097153": 255, + "2097155": 34, + "2097156": 255, + "2097157": 255, + "2097158": 233, + "2097159": 210, + "2097160": 84, + "2097161": 104, + "2097162": 105, + "2097163": 115, + "2097164": 32, + "2097165": 105, + "2097166": 115, + "2097167": 32, + "2097168": 97, + "2097169": 32, + "2097170": 115, + "2097171": 116, + "2097172": 114, + "2097173": 105, + "2097174": 110, + "2097175": 103, + "2097180": 63, + "2097181": 140, + "2097182": 204, + "2097183": 205, + "21": 3, + "22": 3, + "23": 19, + "25": 3, + "26": 5, + "27": 3, + "3": 147, + "31": 115, + "33": 32, + "34": 3, + "35": 23, + "36": 254, + "37": 35, + "38": 3, + "39": 19, + "41": 3, + "42": 21, + "43": 3, + "47": 115, + "49": 32, + "50": 3, + "51": 23, + "52": 253, + "53": 67, + "54": 3, + "55": 19, + "57": 3, + "58": 37, + "59": 3, + "6": 37, + "63": 115, + "65": 32, + "66": 3, + "67": 23, + "68": 253, + "69": 195, + "7": 55, + "70": 3, + "71": 19, + "73": 3, + "74": 32, + "75": 7, + "76": 224, + "78": 5, + "79": 83, + "8": 161, + "83": 115, + "85": 64, + "86": 8, + "87": 147, + "89": 32, + "9": 21, + "90": 5, + "91": 23, + "92": 251, + "93": 5, + "94": 5, + "95": 19, + "99": 115, + }, + registers: { + "f0,ft0": "0xffffffff3f8ccccd", + "x10,a0": "0x200008", + "x17,a7": "0x4", + "x6,t1": "0x20001c", + mtime: "0x1a", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/correct/syscalls/test_riscv_syscall_002.s.snap b/tests/arch/__snapshots__/riscv/correct/syscalls/test_riscv_syscall_002.s.snap new file mode 100644 index 000000000..69ba4738c --- /dev/null +++ b/tests/arch/__snapshots__/riscv/correct/syscalls/test_riscv_syscall_002.s.snap @@ -0,0 +1,52 @@ +export const snapshot = {}; + +snapshot[`riscv/correct/syscalls/test_riscv_syscall_002.s 1`] = ` +{ + display: "6673-861", + error: false, + keyboard: "", + memory: { + "1": 32, + "10": 130, + "11": 147, + "12": 208, + "13": 2, + "14": 133, + "15": 83, + "19": 115, + "2": 8, + "20": 250, + "21": 160, + "22": 2, + "23": 147, + "24": 208, + "25": 2, + "26": 133, + "27": 83, + "3": 147, + "31": 115, + "33": 16, + "34": 2, + "35": 147, + "36": 208, + "37": 2, + "38": 133, + "39": 83, + "43": 115, + "46": 128, + "47": 103, + "6": 34, + "7": 183, + "8": 161, + "9": 18, + }, + registers: { + "f10,fa0": "0xffffffff3f800000", + "x17,a7": "0x2", + "x5,t0": "0x1", + mtime: "0xc", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/correct/syscalls/test_riscv_syscall_003.s.snap b/tests/arch/__snapshots__/riscv/correct/syscalls/test_riscv_syscall_003.s.snap new file mode 100644 index 000000000..d3220d1c7 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/correct/syscalls/test_riscv_syscall_003.s.snap @@ -0,0 +1,52 @@ +export const snapshot = {}; + +snapshot[`riscv/correct/syscalls/test_riscv_syscall_003.s 1`] = ` +{ + display: "6673-861", + error: false, + keyboard: "", + memory: { + "1": 48, + "10": 130, + "11": 147, + "12": 210, + "13": 2, + "14": 133, + "15": 83, + "19": 115, + "2": 8, + "20": 250, + "21": 160, + "22": 2, + "23": 147, + "24": 210, + "25": 2, + "26": 133, + "27": 83, + "3": 147, + "31": 115, + "33": 16, + "34": 2, + "35": 147, + "36": 210, + "37": 2, + "38": 133, + "39": 83, + "43": 115, + "46": 128, + "47": 103, + "6": 34, + "7": 183, + "8": 161, + "9": 18, + }, + registers: { + "f10,fa0": "0x3ff0000000000000", + "x17,a7": "0x3", + "x5,t0": "0x1", + mtime: "0xc", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/correct/syscalls/test_riscv_syscall_004.s.snap b/tests/arch/__snapshots__/riscv/correct/syscalls/test_riscv_syscall_004.s.snap new file mode 100644 index 000000000..2803b1ca4 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/correct/syscalls/test_riscv_syscall_004.s.snap @@ -0,0 +1,81 @@ +export const snapshot = {}; + +snapshot[`riscv/correct/syscalls/test_riscv_syscall_004.s 1`] = ` +{ + display: "First StringSecond Stringa +", + error: false, + keyboard: "", + memory: { + "1": 64, + "10": 5, + "11": 19, + "15": 115, + "17": 32, + "18": 5, + "19": 23, + "2": 8, + "20": 255, + "2097152": 70, + "2097153": 105, + "2097154": 114, + "2097155": 115, + "2097156": 116, + "2097157": 32, + "2097158": 83, + "2097159": 116, + "2097160": 114, + "2097161": 105, + "2097162": 110, + "2097163": 103, + "2097165": 83, + "2097166": 101, + "2097167": 99, + "2097168": 111, + "2097169": 110, + "2097170": 100, + "2097171": 32, + "2097172": 83, + "2097173": 116, + "2097174": 114, + "2097175": 105, + "2097176": 110, + "2097177": 103, + "2097179": 97, + "21": 213, + "22": 5, + "23": 19, + "27": 115, + "29": 32, + "3": 147, + "30": 5, + "31": 23, + "32": 255, + "33": 245, + "34": 5, + "35": 19, + "39": 115, + "41": 160, + "42": 5, + "43": 19, + "45": 176, + "46": 8, + "47": 147, + "5": 32, + "51": 115, + "54": 128, + "55": 103, + "6": 5, + "7": 23, + "8": 255, + "9": 197, + }, + registers: { + "x10,a0": "0xa", + "x17,a7": "0xb", + mtime: "0xe", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/correct/syscalls/test_riscv_syscall_005.s.snap b/tests/arch/__snapshots__/riscv/correct/syscalls/test_riscv_syscall_005.s.snap new file mode 100644 index 000000000..f0eecc9ea --- /dev/null +++ b/tests/arch/__snapshots__/riscv/correct/syscalls/test_riscv_syscall_005.s.snap @@ -0,0 +1,24 @@ +export const snapshot = {}; + +snapshot[`riscv/correct/syscalls/test_riscv_syscall_005.s 1`] = ` +{ + display: "", + error: false, + keyboard: " 1234567", + memory: { + "1": 80, + "10": 128, + "11": 103, + "2": 8, + "3": 147, + "7": 115, + }, + registers: { + "x10,a0": "0x12d687", + "x17,a7": "0x5", + mtime: "0x3", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/correct/syscalls/test_riscv_syscall_006.s.snap b/tests/arch/__snapshots__/riscv/correct/syscalls/test_riscv_syscall_006.s.snap new file mode 100644 index 000000000..0f0971512 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/correct/syscalls/test_riscv_syscall_006.s.snap @@ -0,0 +1,24 @@ +export const snapshot = {}; + +snapshot[`riscv/correct/syscalls/test_riscv_syscall_006.s 1`] = ` +{ + display: "", + error: false, + keyboard: " 1.234567", + memory: { + "1": 96, + "10": 128, + "11": 103, + "2": 8, + "3": 147, + "7": 115, + }, + registers: { + "f10,fa0": "0x3f9e064b", + "x17,a7": "0x6", + mtime: "0x3", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/correct/syscalls/test_riscv_syscall_008.s.snap b/tests/arch/__snapshots__/riscv/correct/syscalls/test_riscv_syscall_008.s.snap new file mode 100644 index 000000000..c3bb3aaba --- /dev/null +++ b/tests/arch/__snapshots__/riscv/correct/syscalls/test_riscv_syscall_008.s.snap @@ -0,0 +1,41 @@ +export const snapshot = {}; + +snapshot[`riscv/correct/syscalls/test_riscv_syscall_008.s 1`] = ` +{ + display: "", + error: false, + keyboard: " This is a long string +", + memory: { + "1": 128, + "10": 5, + "11": 19, + "13": 80, + "14": 5, + "15": 147, + "19": 115, + "2": 8, + "2097152": 84, + "2097153": 104, + "2097154": 105, + "2097155": 115, + "2097156": 32, + "22": 128, + "23": 103, + "3": 147, + "5": 32, + "6": 5, + "7": 23, + "8": 255, + "9": 197, + }, + registers: { + "x10,a0": "0x200000", + "x11,a1": "0x5", + "x17,a7": "0x8", + mtime: "0x6", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/correct/syscalls/test_riscv_syscall_010.s.snap b/tests/arch/__snapshots__/riscv/correct/syscalls/test_riscv_syscall_010.s.snap new file mode 100644 index 000000000..a0a109688 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/correct/syscalls/test_riscv_syscall_010.s.snap @@ -0,0 +1,27 @@ +export const snapshot = {}; + +snapshot[`riscv/correct/syscalls/test_riscv_syscall_010.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 160, + "10": 2, + "11": 147, + "14": 128, + "15": 103, + "2": 8, + "3": 147, + "7": 115, + "8": 28, + "9": 80, + }, + registers: { + "x17,a7": "0xa", + mtime: "0x2", + pc: "0x8", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/correct/syscalls/test_riscv_syscall_011.s.snap b/tests/arch/__snapshots__/riscv/correct/syscalls/test_riscv_syscall_011.s.snap new file mode 100644 index 000000000..6b8f0e75c --- /dev/null +++ b/tests/arch/__snapshots__/riscv/correct/syscalls/test_riscv_syscall_011.s.snap @@ -0,0 +1,28 @@ +export const snapshot = {}; + +snapshot[`riscv/correct/syscalls/test_riscv_syscall_011.s 1`] = ` +{ + display: "c", + error: false, + keyboard: "", + memory: { + "1": 176, + "11": 115, + "14": 128, + "15": 103, + "2": 8, + "3": 147, + "4": 6, + "5": 48, + "6": 5, + "7": 19, + }, + registers: { + "x10,a0": "0x63", + "x17,a7": "0xb", + mtime: "0x4", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/correct/syscalls/test_riscv_syscall_012.s.snap b/tests/arch/__snapshots__/riscv/correct/syscalls/test_riscv_syscall_012.s.snap new file mode 100644 index 000000000..80a8b24f4 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/correct/syscalls/test_riscv_syscall_012.s.snap @@ -0,0 +1,24 @@ +export const snapshot = {}; + +snapshot[`riscv/correct/syscalls/test_riscv_syscall_012.s 1`] = ` +{ + display: "", + error: false, + keyboard: " a", + memory: { + "1": 192, + "10": 128, + "11": 103, + "2": 8, + "3": 147, + "7": 115, + }, + registers: { + "x10,a0": "0x61", + "x17,a7": "0xc", + mtime: "0x3", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_001.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_001.s.snap new file mode 100644 index 000000000..39793573c --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_001.s.snap @@ -0,0 +1,49 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_001.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 160, + "10": 3, + "11": 147, + "12": 1, + "14": 4, + "15": 55, + "16": 255, + "17": 244, + "18": 4, + "19": 19, + "2": 2, + "21": 98, + "22": 132, + "23": 179, + "25": 147, + "26": 133, + "27": 51, + "29": 164, + "3": 147, + "30": 5, + "31": 179, + "34": 128, + "35": 103, + "4": 254, + "5": 32, + "6": 3, + "7": 19, + }, + registers: { + "x10,a0": "0xffffffec", + "x11,a1": "0xffffeb", + "x5,t0": "0xa", + "x6,t1": "0xffffffe2", + "x8,fp,s0": "0xffffff", + "x9,s1": "0xffffffec", + mtime: "0x9", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_002.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_002.s.snap new file mode 100644 index 000000000..20a7e772f --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_002.s.snap @@ -0,0 +1,36 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_002.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 160, + "10": 133, + "11": 19, + "13": 197, + "14": 5, + "15": 147, + "18": 128, + "19": 103, + "2": 2, + "3": 147, + "4": 254, + "5": 34, + "6": 132, + "7": 147, + "8": 25, + "9": 180, + }, + registers: { + "x10,a0": "0x187", + "x11,a1": "0x193", + "x5,t0": "0xa", + "x9,s1": "0xffffffec", + mtime: "0x5", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_003.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_003.s.snap new file mode 100644 index 000000000..aeecc28e9 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_003.s.snap @@ -0,0 +1,55 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_003.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 34, + "1": 48, + "10": 3, + "11": 147, + "13": 18, + "14": 52, + "15": 55, + "16": 81, + "17": 84, + "18": 4, + "19": 19, + "2": 2, + "20": 64, + "21": 98, + "22": 132, + "23": 179, + "24": 64, + "25": 147, + "26": 133, + "27": 51, + "28": 64, + "29": 164, + "3": 147, + "30": 5, + "31": 179, + "34": 128, + "35": 103, + "4": 197, + "5": 112, + "6": 3, + "7": 19, + "9": 192, + }, + registers: { + "x10,a0": "0xfffffa40", + "x11,a1": "0x123ad5", + "x5,t0": "0x223", + "x6,t1": "0xfffffc57", + "x7,t2": "0xc", + "x8,fp,s0": "0x123515", + "x9,s1": "0x5cc", + mtime: "0x9", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_004.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_004.s.snap new file mode 100644 index 000000000..8ba0a97d5 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_004.s.snap @@ -0,0 +1,38 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_004.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 2, + "10": 67, + "11": 183, + "12": 255, + "14": 36, + "15": 55, + "18": 36, + "19": 183, + "2": 50, + "22": 128, + "23": 103, + "3": 183, + "4": 5, + "5": 109, + "6": 179, + "7": 55, + "9": 3, + }, + registers: { + "x5,t0": "0x23000", + "x6,t1": "0x56db000", + "x7,t2": "0x34000", + "x8,fp,s0": "0xff002000", + "x9,s1": "0x2000", + mtime: "0x6", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_005.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_005.s.snap new file mode 100644 index 000000000..24bd3e43d --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_005.s.snap @@ -0,0 +1,58 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_005.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 34, + "1": 48, + "10": 3, + "11": 147, + "13": 18, + "14": 52, + "15": 55, + "16": 81, + "17": 84, + "18": 4, + "19": 19, + "2": 2, + "20": 1, + "23": 239, + "24": 64, + "25": 98, + "26": 132, + "27": 179, + "28": 64, + "29": 147, + "3": 147, + "30": 133, + "31": 51, + "32": 64, + "33": 164, + "34": 5, + "35": 179, + "37": 160, + "38": 8, + "39": 147, + "4": 197, + "43": 115, + "5": 112, + "6": 3, + "7": 19, + "9": 192, + }, + registers: { + "x1,ra": "0x18", + "x17,a7": "0xa", + "x5,t0": "0x223", + "x6,t1": "0xfffffc57", + "x7,t2": "0xc", + "x8,fp,s0": "0x123515", + mtime: "0x8", + pc: "0x2c", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_006.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_006.s.snap new file mode 100644 index 000000000..2aab05046 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_006.s.snap @@ -0,0 +1,61 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_006.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 34, + "1": 48, + "10": 3, + "11": 147, + "13": 18, + "14": 52, + "15": 55, + "16": 81, + "17": 84, + "18": 4, + "19": 19, + "2": 2, + "21": 64, + "23": 111, + "24": 2, + "25": 128, + "27": 231, + "28": 64, + "29": 98, + "3": 147, + "30": 132, + "31": 179, + "32": 64, + "33": 147, + "34": 133, + "35": 51, + "36": 64, + "37": 164, + "38": 5, + "39": 179, + "4": 197, + "41": 160, + "42": 8, + "43": 147, + "47": 115, + "5": 112, + "6": 3, + "7": 19, + "9": 192, + }, + registers: { + "x1,ra": "0x1c", + "x17,a7": "0xa", + "x5,t0": "0x223", + "x6,t1": "0xfffffc57", + "x7,t2": "0xc", + "x8,fp,s0": "0x123515", + mtime: "0x9", + pc: "0x30", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_007.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_007.s.snap new file mode 100644 index 000000000..3d1143eed --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_007.s.snap @@ -0,0 +1,66 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_007.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 4, + "10": 3, + "11": 19, + "13": 80, + "14": 3, + "15": 147, + "17": 4, + "18": 68, + "19": 55, + "2": 66, + "20": 86, + "21": 36, + "22": 4, + "23": 19, + "25": 83, + "26": 138, + "27": 99, + "29": 98, + "3": 183, + "30": 136, + "31": 99, + "32": 2, + "33": 32, + "34": 14, + "35": 19, + "37": 160, + "38": 8, + "39": 147, + "4": 86, + "43": 115, + "45": 176, + "46": 2, + "47": 147, + "48": 34, + "49": 176, + "5": 34, + "50": 3, + "51": 19, + "52": 254, + "54": 6, + "55": 227, + "6": 130, + "7": 147, + "9": 32, + }, + registers: { + "x17,a7": "0xa", + "x28,t3": "0x22", + "x5,t0": "0x44562", + "x6,t1": "0x2", + "x7,t2": "0x5", + "x8,fp,s0": "0x44562", + mtime: "0xb", + pc: "0x2c", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_008.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_008.s.snap new file mode 100644 index 000000000..61a54cef8 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_008.s.snap @@ -0,0 +1,62 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_008.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 22, + "1": 144, + "10": 3, + "11": 147, + "13": 4, + "14": 68, + "15": 55, + "16": 86, + "17": 36, + "18": 4, + "19": 19, + "2": 2, + "21": 114, + "22": 152, + "23": 99, + "24": 2, + "25": 32, + "26": 14, + "27": 19, + "29": 160, + "3": 147, + "30": 8, + "31": 147, + "35": 115, + "36": 117, + "37": 64, + "38": 2, + "39": 147, + "40": 34, + "41": 176, + "42": 3, + "43": 19, + "44": 254, + "45": 98, + "46": 150, + "47": 227, + "5": 32, + "6": 3, + "7": 19, + "9": 80, + }, + registers: { + "x17,a7": "0xa", + "x28,t3": "0x22", + "x5,t0": "0x754", + "x6,t1": "0x22b", + "x7,t2": "0x5", + "x8,fp,s0": "0x44562", + mtime: "0xc", + pc: "0x24", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_009.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_009.s.snap new file mode 100644 index 000000000..86fa6b008 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_009.s.snap @@ -0,0 +1,67 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_009.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 22, + "1": 144, + "10": 3, + "11": 147, + "13": 4, + "14": 68, + "15": 55, + "16": 86, + "17": 36, + "18": 4, + "19": 19, + "2": 2, + "21": 114, + "22": 202, + "23": 99, + "25": 83, + "26": 72, + "27": 99, + "28": 2, + "29": 32, + "3": 147, + "30": 14, + "31": 19, + "33": 160, + "34": 8, + "35": 147, + "39": 115, + "40": 117, + "41": 64, + "42": 4, + "43": 147, + "44": 34, + "45": 176, + "46": 5, + "47": 19, + "48": 254, + "49": 149, + "5": 32, + "50": 70, + "51": 227, + "6": 3, + "7": 19, + "9": 80, + }, + registers: { + "x10,a0": "0x22b", + "x17,a7": "0xa", + "x28,t3": "0x22", + "x5,t0": "0x169", + "x6,t1": "0x2", + "x7,t2": "0x5", + "x8,fp,s0": "0x44562", + "x9,s1": "0x754", + mtime: "0xd", + pc: "0x28", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_010.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_010.s.snap new file mode 100644 index 000000000..99f9ae882 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_010.s.snap @@ -0,0 +1,66 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_010.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 22, + "1": 144, + "10": 3, + "11": 147, + "13": 4, + "14": 68, + "15": 55, + "16": 86, + "17": 36, + "18": 4, + "19": 19, + "2": 2, + "21": 130, + "22": 218, + "23": 99, + "25": 84, + "26": 88, + "27": 99, + "28": 2, + "29": 32, + "3": 147, + "30": 14, + "31": 19, + "33": 160, + "34": 8, + "35": 147, + "39": 115, + "40": 117, + "41": 64, + "42": 2, + "43": 147, + "44": 34, + "45": 176, + "46": 15, + "47": 147, + "48": 254, + "49": 98, + "5": 32, + "50": 214, + "51": 227, + "6": 3, + "7": 19, + "9": 80, + }, + registers: { + "x17,a7": "0xa", + "x28,t3": "0x22", + "x31,t6": "0x22b", + "x5,t0": "0x754", + "x6,t1": "0x2", + "x7,t2": "0x5", + "x8,fp,s0": "0x44562", + mtime: "0xd", + pc: "0x28", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_011.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_011.s.snap new file mode 100644 index 000000000..e0c5bd98b --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_011.s.snap @@ -0,0 +1,67 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_011.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 22, + "1": 144, + "10": 3, + "11": 147, + "13": 4, + "14": 68, + "15": 55, + "16": 86, + "17": 36, + "18": 4, + "19": 19, + "2": 2, + "21": 114, + "22": 234, + "23": 99, + "25": 83, + "26": 104, + "27": 99, + "28": 2, + "29": 32, + "3": 147, + "30": 14, + "31": 19, + "33": 160, + "34": 8, + "35": 147, + "39": 115, + "40": 117, + "41": 64, + "42": 4, + "43": 147, + "44": 34, + "45": 176, + "46": 5, + "47": 19, + "48": 254, + "49": 149, + "5": 32, + "50": 102, + "51": 227, + "6": 3, + "7": 19, + "9": 80, + }, + registers: { + "x10,a0": "0x22b", + "x17,a7": "0xa", + "x28,t3": "0x22", + "x5,t0": "0x169", + "x6,t1": "0x2", + "x7,t2": "0x5", + "x8,fp,s0": "0x44562", + "x9,s1": "0x754", + mtime: "0xd", + pc: "0x28", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_012.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_012.s.snap new file mode 100644 index 000000000..aa0c49dab --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_012.s.snap @@ -0,0 +1,66 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_012.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 22, + "1": 144, + "10": 3, + "11": 147, + "13": 4, + "14": 68, + "15": 55, + "16": 86, + "17": 36, + "18": 4, + "19": 19, + "2": 2, + "21": 130, + "22": 250, + "23": 99, + "25": 84, + "26": 120, + "27": 99, + "28": 2, + "29": 32, + "3": 147, + "30": 14, + "31": 19, + "33": 160, + "34": 8, + "35": 147, + "39": 115, + "40": 117, + "41": 64, + "42": 2, + "43": 147, + "44": 34, + "45": 176, + "46": 15, + "47": 147, + "48": 254, + "49": 98, + "5": 32, + "50": 246, + "51": 227, + "6": 3, + "7": 19, + "9": 80, + }, + registers: { + "x17,a7": "0xa", + "x28,t3": "0x22", + "x31,t6": "0x22b", + "x5,t0": "0x754", + "x6,t1": "0x2", + "x7,t2": "0x5", + "x8,fp,s0": "0x44562", + mtime: "0xd", + pc: "0x28", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_013.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_013.s.snap new file mode 100644 index 000000000..28d1fef2f --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_013.s.snap @@ -0,0 +1,91 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_013.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 32, + "10": 3, + "11": 23, + "12": 255, + "13": 195, + "14": 3, + "15": 19, + "17": 32, + "18": 3, + "19": 151, + "2": 2, + "20": 255, + "2097155": 14, + "2097156": 127, + "2097158": 127, + "2097159": 255, + "2097163": 14, + "2097164": 127, + "2097166": 127, + "2097167": 255, + "21": 99, + "22": 131, + "23": 147, + "25": 2, + "26": 164, + "27": 3, + "29": 3, + "3": 151, + "30": 5, + "31": 3, + "33": 3, + "34": 150, + "35": 3, + "37": 32, + "38": 7, + "39": 23, + "40": 254, + "41": 71, + "42": 7, + "43": 19, + "45": 135, + "46": 32, + "47": 35, + "49": 32, + "5": 2, + "50": 7, + "51": 23, + "52": 253, + "53": 199, + "54": 7, + "55": 19, + "57": 167, + "59": 35, + "6": 130, + "61": 32, + "62": 7, + "63": 23, + "64": 253, + "65": 39, + "66": 7, + "67": 19, + "69": 199, + "7": 147, + "70": 16, + "71": 35, + "74": 128, + "75": 103, + "9": 32, + }, + registers: { + "x10,a0": "0x7f", + "x12,a2": "0x7fff", + "x14,a4": "0x20000e", + "x5,t0": "0x200000", + "x6,t1": "0x200004", + "x7,t2": "0x200006", + "x8,fp,s0": "0xe", + mtime: "0x13", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_014.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_014.s.snap new file mode 100644 index 000000000..a292e0e0c --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_014.s.snap @@ -0,0 +1,67 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_014.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 32, + "10": 3, + "11": 151, + "12": 255, + "13": 163, + "14": 131, + "15": 147, + "17": 3, + "18": 69, + "19": 3, + "2": 3, + "2097152": 127, + "2097154": 255, + "2097155": 255, + "2097156": 127, + "2097158": 255, + "2097159": 255, + "21": 3, + "22": 214, + "23": 3, + "25": 32, + "26": 7, + "27": 23, + "28": 254, + "29": 199, + "3": 23, + "30": 7, + "31": 19, + "33": 167, + "35": 35, + "37": 32, + "38": 7, + "39": 23, + "40": 254, + "41": 39, + "42": 7, + "43": 19, + "45": 199, + "46": 16, + "47": 35, + "5": 3, + "50": 128, + "51": 103, + "6": 3, + "7": 19, + "9": 32, + }, + registers: { + "x10,a0": "0x7f", + "x12,a2": "0xffff", + "x14,a4": "0x200006", + "x6,t1": "0x200000", + "x7,t2": "0x200002", + mtime: "0xd", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_015.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_015.s.snap new file mode 100644 index 000000000..add3f7ae4 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_015.s.snap @@ -0,0 +1,62 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_015.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 47, + "10": 163, + "11": 19, + "12": 47, + "13": 2, + "14": 163, + "15": 147, + "16": 47, + "17": 18, + "18": 164, + "19": 19, + "2": 2, + "20": 47, + "21": 34, + "22": 164, + "23": 147, + "24": 191, + "25": 245, + "26": 37, + "27": 147, + "28": 192, + "29": 5, + "3": 147, + "30": 38, + "31": 19, + "32": 192, + "33": 21, + "34": 38, + "35": 147, + "36": 192, + "37": 37, + "38": 39, + "39": 19, + "4": 192, + "42": 128, + "43": 103, + "6": 5, + "7": 19, + "8": 46, + "9": 242, + }, + registers: { + "x10,a0": "0xfffffc00", + "x13,a3": "0x1", + "x14,a4": "0x1", + "x5,t0": "0x2f0", + "x8,fp,s0": "0x1", + "x9,s1": "0x1", + mtime: "0xb", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_016.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_016.s.snap new file mode 100644 index 000000000..cf00a3cfa --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_016.s.snap @@ -0,0 +1,62 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_016.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 47, + "10": 179, + "11": 19, + "12": 47, + "13": 2, + "14": 179, + "15": 147, + "16": 47, + "17": 18, + "18": 180, + "19": 19, + "2": 2, + "20": 47, + "21": 34, + "22": 180, + "23": 147, + "24": 191, + "25": 245, + "26": 53, + "27": 147, + "28": 192, + "29": 5, + "3": 147, + "30": 54, + "31": 19, + "32": 192, + "33": 21, + "34": 54, + "35": 147, + "36": 192, + "37": 37, + "38": 55, + "39": 19, + "4": 192, + "42": 128, + "43": 103, + "6": 5, + "7": 19, + "8": 46, + "9": 242, + }, + registers: { + "x10,a0": "0xfffffc00", + "x13,a3": "0x1", + "x14,a4": "0x1", + "x5,t0": "0x2f0", + "x8,fp,s0": "0x1", + "x9,s1": "0x1", + mtime: "0xb", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_017.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_017.s.snap new file mode 100644 index 000000000..65e9a59a2 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_017.s.snap @@ -0,0 +1,57 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_017.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 2, + "10": 19, + "11": 55, + "12": 29, + "13": 115, + "14": 3, + "15": 19, + "16": 255, + "17": 255, + "18": 227, + "19": 183, + "2": 34, + "20": 175, + "21": 35, + "22": 131, + "23": 147, + "24": 69, + "25": 82, + "26": 196, + "27": 19, + "28": 34, + "29": 35, + "3": 183, + "30": 68, + "31": 147, + "32": 127, + "33": 243, + "34": 197, + "35": 19, + "38": 128, + "39": 103, + "4": 52, + "5": 98, + "6": 130, + "7": 147, + }, + registers: { + "x10,a0": "0xffffdd0d", + "x5,t0": "0x22346", + "x6,t1": "0x11d7", + "x7,t2": "0xffffdaf2", + "x8,fp,s0": "0x22713", + "x9,s1": "0x13f5", + mtime: "0xa", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_018.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_018.s.snap new file mode 100644 index 000000000..e23ae4b36 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_018.s.snap @@ -0,0 +1,57 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_018.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 2, + "10": 19, + "11": 55, + "12": 29, + "13": 115, + "14": 3, + "15": 19, + "16": 255, + "17": 255, + "18": 227, + "19": 183, + "2": 34, + "20": 175, + "21": 35, + "22": 131, + "23": 147, + "24": 69, + "25": 82, + "26": 228, + "27": 19, + "28": 34, + "29": 35, + "3": 183, + "30": 100, + "31": 147, + "32": 127, + "33": 243, + "34": 229, + "35": 19, + "38": 128, + "39": 103, + "4": 52, + "5": 98, + "6": 130, + "7": 147, + }, + registers: { + "x10,a0": "0xffffdfff", + "x5,t0": "0x22346", + "x6,t1": "0x11d7", + "x7,t2": "0xffffdaf2", + "x8,fp,s0": "0x22757", + "x9,s1": "0x13f7", + mtime: "0xa", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_019.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_019.s.snap new file mode 100644 index 000000000..4fa06300f --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_019.s.snap @@ -0,0 +1,57 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_019.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 2, + "10": 19, + "11": 55, + "12": 29, + "13": 115, + "14": 3, + "15": 19, + "16": 255, + "17": 255, + "18": 227, + "19": 183, + "2": 34, + "20": 175, + "21": 35, + "22": 131, + "23": 147, + "24": 69, + "25": 82, + "26": 244, + "27": 19, + "28": 34, + "29": 35, + "3": 183, + "30": 116, + "31": 147, + "32": 127, + "33": 243, + "34": 245, + "35": 19, + "38": 128, + "39": 103, + "4": 52, + "5": 98, + "6": 130, + "7": 147, + }, + registers: { + "x10,a0": "0x2f2", + "x5,t0": "0x22346", + "x6,t1": "0x11d7", + "x7,t2": "0xffffdaf2", + "x8,fp,s0": "0x44", + "x9,s1": "0x2", + mtime: "0xa", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_020.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_020.s.snap new file mode 100644 index 000000000..6095567a2 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_020.s.snap @@ -0,0 +1,53 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_020.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "10": 19, + "11": 55, + "12": 29, + "13": 115, + "14": 3, + "15": 19, + "16": 255, + "17": 255, + "18": 227, + "19": 183, + "2": 178, + "20": 175, + "21": 35, + "22": 131, + "23": 147, + "25": 34, + "26": 148, + "27": 19, + "29": 67, + "3": 183, + "30": 20, + "31": 147, + "33": 243, + "34": 149, + "35": 19, + "38": 128, + "39": 103, + "4": 173, + "5": 66, + "6": 130, + "7": 147, + }, + registers: { + "x10,a0": "0xed790000", + "x5,t0": "0xaad4", + "x6,t1": "0x11d7", + "x7,t2": "0xffffdaf2", + "x8,fp,s0": "0x2ab50", + "x9,s1": "0x11d70", + mtime: "0xa", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_021.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_021.s.snap new file mode 100644 index 000000000..adfb55eca --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_021.s.snap @@ -0,0 +1,53 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_021.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "10": 19, + "11": 55, + "12": 29, + "13": 115, + "14": 3, + "15": 19, + "16": 255, + "17": 255, + "18": 227, + "19": 183, + "2": 178, + "20": 175, + "21": 35, + "22": 131, + "23": 147, + "25": 34, + "26": 212, + "27": 19, + "29": 67, + "3": 183, + "30": 84, + "31": 147, + "33": 243, + "34": 213, + "35": 19, + "38": 128, + "39": 103, + "4": 173, + "5": 66, + "6": 130, + "7": 147, + }, + registers: { + "x10,a0": "0x1ffff", + "x5,t0": "0xaad4", + "x6,t1": "0x11d7", + "x7,t2": "0xffffdaf2", + "x8,fp,s0": "0x2ab5", + "x9,s1": "0x11d", + mtime: "0xa", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_022.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_022.s.snap new file mode 100644 index 000000000..0a90d95ec --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_022.s.snap @@ -0,0 +1,56 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_022.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "10": 19, + "11": 55, + "12": 29, + "13": 115, + "14": 3, + "15": 19, + "16": 255, + "17": 255, + "18": 227, + "19": 183, + "2": 178, + "20": 175, + "21": 35, + "22": 131, + "23": 147, + "24": 64, + "25": 34, + "26": 212, + "27": 19, + "28": 64, + "29": 67, + "3": 183, + "30": 84, + "31": 147, + "32": 64, + "33": 243, + "34": 213, + "35": 19, + "38": 128, + "39": 103, + "4": 173, + "5": 66, + "6": 130, + "7": 147, + }, + registers: { + "x10,a0": "0xffffffff", + "x5,t0": "0xaad4", + "x6,t1": "0x11d7", + "x7,t2": "0xffffdaf2", + "x8,fp,s0": "0x2ab5", + "x9,s1": "0x11d", + mtime: "0xa", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_023.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_023.s.snap new file mode 100644 index 000000000..ccafadb81 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_023.s.snap @@ -0,0 +1,66 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_023.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "10": 19, + "11": 55, + "12": 29, + "13": 115, + "14": 3, + "15": 19, + "16": 255, + "17": 255, + "18": 227, + "19": 183, + "2": 178, + "20": 175, + "21": 35, + "22": 131, + "23": 147, + "25": 32, + "26": 4, + "27": 19, + "29": 16, + "3": 183, + "30": 4, + "31": 147, + "32": 85, + "33": 64, + "34": 5, + "35": 19, + "37": 130, + "38": 149, + "39": 179, + "4": 173, + "41": 147, + "42": 22, + "43": 51, + "45": 163, + "46": 150, + "47": 179, + "5": 66, + "50": 128, + "51": 103, + "6": 130, + "7": 147, + }, + registers: { + "x10,a0": "0x554", + "x11,a1": "0x2ab50", + "x12,a2": "0x23ae", + "x13,a3": "0xaf200000", + "x5,t0": "0xaad4", + "x6,t1": "0x11d7", + "x7,t2": "0xffffdaf2", + "x8,fp,s0": "0x2", + "x9,s1": "0x1", + mtime: "0xd", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_024.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_024.s.snap new file mode 100644 index 000000000..e2bd2e2ff --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_024.s.snap @@ -0,0 +1,57 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_024.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "10": 34, + "11": 183, + "13": 2, + "14": 130, + "15": 147, + "18": 35, + "19": 55, + "2": 34, + "21": 19, + "22": 3, + "23": 19, + "26": 35, + "27": 183, + "29": 35, + "3": 55, + "30": 131, + "31": 147, + "33": 66, + "34": 164, + "35": 51, + "37": 82, + "38": 164, + "39": 179, + "4": 255, + "41": 98, + "42": 165, + "43": 51, + "45": 114, + "46": 165, + "47": 179, + "5": 242, + "50": 128, + "51": 103, + "6": 2, + "7": 19, + }, + registers: { + "x10,a0": "0x1", + "x11,a1": "0x1", + "x4,tp": "0x1fff", + "x5,t0": "0x2000", + "x6,t1": "0x2001", + "x7,t2": "0x2002", + mtime: "0xd", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_025.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_025.s.snap new file mode 100644 index 000000000..bd116296e --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_025.s.snap @@ -0,0 +1,57 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_025.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "10": 34, + "11": 183, + "13": 2, + "14": 130, + "15": 147, + "18": 35, + "19": 55, + "2": 34, + "21": 19, + "22": 3, + "23": 19, + "26": 35, + "27": 183, + "29": 35, + "3": 55, + "30": 131, + "31": 147, + "33": 66, + "34": 180, + "35": 51, + "37": 82, + "38": 180, + "39": 179, + "4": 255, + "41": 98, + "42": 181, + "43": 51, + "45": 114, + "46": 181, + "47": 179, + "5": 242, + "50": 128, + "51": 103, + "6": 2, + "7": 19, + }, + registers: { + "x10,a0": "0x1", + "x11,a1": "0x1", + "x4,tp": "0x1fff", + "x5,t0": "0x2000", + "x6,t1": "0x2001", + "x7,t2": "0x2002", + mtime: "0xd", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_026.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_026.s.snap new file mode 100644 index 000000000..4a1bef7ef --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_026.s.snap @@ -0,0 +1,71 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_026.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 2, + "10": 19, + "11": 55, + "12": 29, + "13": 115, + "14": 3, + "15": 19, + "16": 255, + "17": 255, + "18": 227, + "19": 183, + "2": 34, + "20": 175, + "21": 35, + "22": 131, + "23": 147, + "24": 69, + "25": 80, + "26": 4, + "27": 19, + "28": 34, + "29": 32, + "3": 183, + "30": 4, + "31": 147, + "34": 21, + "35": 55, + "36": 255, + "37": 245, + "38": 5, + "39": 19, + "4": 52, + "41": 130, + "42": 197, + "43": 179, + "45": 147, + "46": 70, + "47": 51, + "49": 163, + "5": 98, + "50": 198, + "51": 179, + "54": 128, + "55": 103, + "6": 130, + "7": 147, + }, + registers: { + "x10,a0": "0xfff", + "x11,a1": "0x22713", + "x12,a2": "0x13f5", + "x13,a3": "0xffffd50d", + "x5,t0": "0x22346", + "x6,t1": "0x11d7", + "x7,t2": "0xffffdaf2", + "x8,fp,s0": "0x455", + "x9,s1": "0x222", + mtime: "0xe", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_027.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_027.s.snap new file mode 100644 index 000000000..ec27725ac --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_027.s.snap @@ -0,0 +1,66 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_027.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "10": 19, + "11": 55, + "12": 29, + "13": 115, + "14": 3, + "15": 19, + "16": 255, + "17": 255, + "18": 227, + "19": 183, + "2": 178, + "20": 175, + "21": 35, + "22": 131, + "23": 147, + "25": 32, + "26": 4, + "27": 19, + "29": 16, + "3": 183, + "30": 4, + "31": 147, + "32": 85, + "33": 64, + "34": 5, + "35": 19, + "37": 130, + "38": 213, + "39": 179, + "4": 173, + "41": 147, + "42": 86, + "43": 51, + "45": 163, + "46": 214, + "47": 179, + "5": 66, + "50": 128, + "51": 103, + "6": 130, + "7": 147, + }, + registers: { + "x10,a0": "0x554", + "x11,a1": "0x2ab5", + "x12,a2": "0x8eb", + "x13,a3": "0xfff", + "x5,t0": "0xaad4", + "x6,t1": "0x11d7", + "x7,t2": "0xffffdaf2", + "x8,fp,s0": "0x2", + "x9,s1": "0x1", + mtime: "0xd", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_028.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_028.s.snap new file mode 100644 index 000000000..45d2129bf --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_028.s.snap @@ -0,0 +1,68 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_028.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "10": 19, + "11": 55, + "12": 29, + "13": 115, + "14": 3, + "15": 19, + "16": 255, + "17": 255, + "18": 227, + "19": 183, + "2": 178, + "20": 175, + "21": 35, + "22": 131, + "23": 147, + "25": 32, + "26": 4, + "27": 19, + "29": 16, + "3": 183, + "30": 4, + "31": 147, + "33": 48, + "34": 5, + "35": 19, + "36": 64, + "37": 130, + "38": 213, + "39": 179, + "4": 173, + "40": 64, + "41": 147, + "42": 86, + "43": 51, + "44": 64, + "45": 163, + "46": 214, + "47": 179, + "5": 66, + "50": 128, + "51": 103, + "6": 130, + "7": 147, + }, + registers: { + "x10,a0": "0x3", + "x11,a1": "0x2ab5", + "x12,a2": "0x8eb", + "x13,a3": "0xfffffb5e", + "x5,t0": "0xaad4", + "x6,t1": "0x11d7", + "x7,t2": "0xffffdaf2", + "x8,fp,s0": "0x2", + "x9,s1": "0x1", + mtime: "0xd", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_029.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_029.s.snap new file mode 100644 index 000000000..d7d993491 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_029.s.snap @@ -0,0 +1,71 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_029.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 2, + "10": 19, + "11": 55, + "12": 29, + "13": 115, + "14": 3, + "15": 19, + "16": 255, + "17": 255, + "18": 227, + "19": 183, + "2": 34, + "20": 175, + "21": 35, + "22": 131, + "23": 147, + "24": 69, + "25": 80, + "26": 4, + "27": 19, + "28": 34, + "29": 32, + "3": 183, + "30": 4, + "31": 147, + "34": 21, + "35": 55, + "36": 255, + "37": 245, + "38": 5, + "39": 19, + "4": 52, + "41": 130, + "42": 229, + "43": 179, + "45": 147, + "46": 102, + "47": 51, + "49": 163, + "5": 98, + "50": 230, + "51": 179, + "54": 128, + "55": 103, + "6": 130, + "7": 147, + }, + registers: { + "x10,a0": "0xfff", + "x11,a1": "0x22757", + "x12,a2": "0x13f7", + "x13,a3": "0xffffdfff", + "x5,t0": "0x22346", + "x6,t1": "0x11d7", + "x7,t2": "0xffffdaf2", + "x8,fp,s0": "0x455", + "x9,s1": "0x222", + mtime: "0xe", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_030.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_030.s.snap new file mode 100644 index 000000000..55fad3bec --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_030.s.snap @@ -0,0 +1,71 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_030.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 2, + "10": 19, + "11": 55, + "12": 29, + "13": 115, + "14": 3, + "15": 19, + "16": 255, + "17": 255, + "18": 227, + "19": 183, + "2": 34, + "20": 175, + "21": 35, + "22": 131, + "23": 147, + "24": 69, + "25": 80, + "26": 4, + "27": 19, + "28": 34, + "29": 32, + "3": 183, + "30": 4, + "31": 147, + "34": 21, + "35": 55, + "36": 255, + "37": 245, + "38": 5, + "39": 19, + "4": 52, + "41": 130, + "42": 245, + "43": 179, + "45": 147, + "46": 118, + "47": 51, + "49": 163, + "5": 98, + "50": 246, + "51": 179, + "54": 128, + "55": 103, + "6": 130, + "7": 147, + }, + registers: { + "x10,a0": "0xfff", + "x11,a1": "0x44", + "x12,a2": "0x2", + "x13,a3": "0xaf2", + "x5,t0": "0x22346", + "x6,t1": "0x11d7", + "x7,t2": "0xffffdaf2", + "x8,fp,s0": "0x455", + "x9,s1": "0x222", + mtime: "0xe", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_031.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_031.s.snap new file mode 100644 index 000000000..dba766795 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_031.s.snap @@ -0,0 +1,116 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_031.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 32, + "10": 3, + "11": 23, + "13": 3, + "14": 3, + "15": 19, + "17": 32, + "18": 3, + "19": 151, + "2": 2, + "2097152": 64, + "2097153": 65, + "2097154": 69, + "2097155": 161, + "2097156": 202, + "2097157": 192, + "2097158": 131, + "2097159": 18, + "2097160": 64, + "2097161": 38, + "2097162": 226, + "2097163": 208, + "2097164": 229, + "2097165": 96, + "2097166": 65, + "2097167": 137, + "2097172": 7, + "2097173": 84, + "2097174": 79, + "2097175": 251, + "2097176": 64, + "2097177": 65, + "2097178": 69, + "2097179": 161, + "2097180": 202, + "2097181": 192, + "2097182": 131, + "2097183": 18, + "2097184": 64, + "2097185": 38, + "2097186": 226, + "2097187": 208, + "2097188": 229, + "2097189": 96, + "2097190": 65, + "2097191": 137, + "2097196": 7, + "2097197": 84, + "2097198": 79, + "2097199": 251, + "21": 3, + "22": 131, + "23": 147, + "25": 32, + "26": 4, + "27": 23, + "29": 4, + "3": 151, + "30": 4, + "31": 19, + "33": 2, + "34": 176, + "35": 7, + "37": 3, + "38": 49, + "39": 7, + "41": 3, + "42": 181, + "43": 7, + "45": 4, + "46": 48, + "47": 39, + "49": 132, + "5": 2, + "50": 4, + "51": 19, + "53": 36, + "54": 48, + "55": 39, + "57": 132, + "58": 4, + "59": 19, + "6": 130, + "61": 164, + "62": 48, + "63": 39, + "65": 160, + "66": 8, + "67": 147, + "7": 147, + "71": 115, + "9": 32, + }, + registers: { + "f0,ft0": "0x404145a1cac08312", + "f10,fa0": "0x7544ffb", + "f2,ft2": "0x4026e2d0e5604189", + "x17,a7": "0xa", + "x5,t0": "0x200000", + "x6,t1": "0x200008", + "x7,t2": "0x200010", + "x8,fp,s0": "0x200028", + mtime: "0x12", + pc: "0x48", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_032.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_032.s.snap new file mode 100644 index 000000000..23aba0e5b --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_032.s.snap @@ -0,0 +1,53 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_032.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "10": 19, + "11": 55, + "12": 29, + "13": 115, + "14": 3, + "15": 19, + "16": 255, + "17": 255, + "18": 227, + "19": 183, + "2": 178, + "20": 175, + "21": 35, + "22": 131, + "23": 147, + "25": 34, + "26": 149, + "27": 147, + "29": 19, + "3": 183, + "30": 22, + "31": 19, + "33": 243, + "34": 150, + "35": 147, + "38": 128, + "39": 103, + "4": 173, + "5": 66, + "6": 130, + "7": 147, + }, + registers: { + "x11,a1": "0x2ab50", + "x12,a2": "0x23ae", + "x13,a3": "0xed790000", + "x5,t0": "0xaad4", + "x6,t1": "0x11d7", + "x7,t2": "0xffffdaf2", + mtime: "0xa", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_033.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_033.s.snap new file mode 100644 index 000000000..688d06ca0 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_033.s.snap @@ -0,0 +1,53 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_033.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "10": 19, + "11": 55, + "12": 29, + "13": 115, + "14": 3, + "15": 19, + "16": 255, + "17": 255, + "18": 227, + "19": 183, + "2": 178, + "20": 175, + "21": 35, + "22": 131, + "23": 147, + "25": 34, + "26": 212, + "27": 19, + "29": 19, + "3": 183, + "30": 84, + "31": 147, + "33": 243, + "34": 213, + "35": 19, + "38": 128, + "39": 103, + "4": 173, + "5": 66, + "6": 130, + "7": 147, + }, + registers: { + "x10,a0": "0x1ffff", + "x5,t0": "0xaad4", + "x6,t1": "0x11d7", + "x7,t2": "0xffffdaf2", + "x8,fp,s0": "0x2ab5", + "x9,s1": "0x8eb", + mtime: "0xa", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_034.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_034.s.snap new file mode 100644 index 000000000..83baa6417 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_034.s.snap @@ -0,0 +1,56 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_034.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 160, + "10": 3, + "11": 147, + "12": 255, + "13": 224, + "14": 4, + "15": 19, + "16": 2, + "17": 98, + "18": 132, + "19": 179, + "2": 2, + "20": 2, + "21": 115, + "22": 5, + "23": 51, + "24": 2, + "25": 131, + "26": 133, + "27": 179, + "28": 2, + "29": 84, + "3": 147, + "30": 6, + "31": 51, + "34": 128, + "35": 103, + "5": 208, + "6": 3, + "7": 19, + "8": 2, + "9": 208, + }, + registers: { + "x10,a0": "0x249", + "x11,a1": "0xffffffa6", + "x12,a2": "0xffffffec", + "x5,t0": "0xa", + "x6,t1": "0xd", + "x7,t2": "0x2d", + "x8,fp,s0": "0xfffffffe", + "x9,s1": "0x82", + mtime: "0x9", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_035.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_035.s.snap new file mode 100644 index 000000000..4faf8225b --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_035.s.snap @@ -0,0 +1,54 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_035.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 160, + "10": 3, + "11": 147, + "12": 255, + "13": 224, + "14": 4, + "15": 19, + "16": 2, + "17": 98, + "18": 148, + "19": 179, + "2": 2, + "20": 2, + "21": 115, + "22": 21, + "23": 51, + "24": 2, + "25": 131, + "26": 149, + "27": 179, + "28": 2, + "29": 84, + "3": 147, + "30": 22, + "31": 51, + "34": 128, + "35": 103, + "5": 208, + "6": 3, + "7": 19, + "8": 2, + "9": 208, + }, + registers: { + "x11,a1": "0xffffffff", + "x12,a2": "0xffffffff", + "x5,t0": "0xa", + "x6,t1": "0xd", + "x7,t2": "0x2d", + "x8,fp,s0": "0xfffffffe", + mtime: "0x9", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_036.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_036.s.snap new file mode 100644 index 000000000..ac1e3d4ce --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_036.s.snap @@ -0,0 +1,54 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_036.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 160, + "10": 3, + "11": 147, + "12": 255, + "13": 224, + "14": 4, + "15": 19, + "16": 2, + "17": 98, + "18": 164, + "19": 179, + "2": 2, + "20": 2, + "21": 115, + "22": 37, + "23": 51, + "24": 2, + "25": 131, + "26": 165, + "27": 179, + "28": 2, + "29": 84, + "3": 147, + "30": 38, + "31": 51, + "34": 128, + "35": 103, + "5": 208, + "6": 3, + "7": 19, + "8": 2, + "9": 208, + }, + registers: { + "x11,a1": "0x2c", + "x12,a2": "0xffffffff", + "x5,t0": "0xa", + "x6,t1": "0xd", + "x7,t2": "0x2d", + "x8,fp,s0": "0xfffffffe", + mtime: "0x9", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_037.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_037.s.snap new file mode 100644 index 000000000..79e284d2e --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_037.s.snap @@ -0,0 +1,54 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_037.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 160, + "10": 3, + "11": 147, + "12": 255, + "13": 224, + "14": 4, + "15": 19, + "16": 2, + "17": 98, + "18": 180, + "19": 179, + "2": 2, + "20": 2, + "21": 115, + "22": 53, + "23": 51, + "24": 2, + "25": 131, + "26": 181, + "27": 179, + "28": 2, + "29": 84, + "3": 147, + "30": 54, + "31": 51, + "34": 128, + "35": 103, + "5": 208, + "6": 3, + "7": 19, + "8": 2, + "9": 208, + }, + registers: { + "x11,a1": "0x2c", + "x12,a2": "0x9", + "x5,t0": "0xa", + "x6,t1": "0xd", + "x7,t2": "0x2d", + "x8,fp,s0": "0xfffffffe", + mtime: "0x9", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_038.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_038.s.snap new file mode 100644 index 000000000..3fcbef7b8 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_038.s.snap @@ -0,0 +1,58 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_038.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 1, + "10": 227, + "11": 183, + "13": 3, + "14": 131, + "15": 147, + "16": 1, + "17": 128, + "18": 4, + "19": 19, + "2": 2, + "20": 2, + "21": 83, + "22": 196, + "23": 179, + "24": 2, + "25": 83, + "26": 69, + "27": 51, + "28": 2, + "29": 131, + "3": 147, + "30": 197, + "31": 179, + "32": 2, + "33": 116, + "34": 70, + "35": 51, + "38": 128, + "39": 103, + "4": 16, + "6": 3, + "7": 19, + "8": 255, + "9": 255, + }, + registers: { + "x10,a0": "0x10", + "x11,a1": "0xfffffeab", + "x5,t0": "0x10", + "x6,t1": "0x100", + "x7,t2": "0xffffe000", + "x8,fp,s0": "0x18", + "x9,s1": "0xfffffe00", + mtime: "0xa", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_039.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_039.s.snap new file mode 100644 index 000000000..5147f4ac6 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_039.s.snap @@ -0,0 +1,58 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_039.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 1, + "10": 227, + "11": 183, + "13": 3, + "14": 131, + "15": 147, + "16": 1, + "17": 128, + "18": 4, + "19": 19, + "2": 2, + "20": 2, + "21": 83, + "22": 212, + "23": 179, + "24": 2, + "25": 83, + "26": 85, + "27": 51, + "28": 2, + "29": 131, + "3": 147, + "30": 213, + "31": 179, + "32": 2, + "33": 116, + "34": 86, + "35": 51, + "38": 128, + "39": 103, + "4": 16, + "6": 3, + "7": 19, + "8": 255, + "9": 255, + }, + registers: { + "x10,a0": "0x10", + "x11,a1": "0xaaaa955", + "x5,t0": "0x10", + "x6,t1": "0x100", + "x7,t2": "0xffffe000", + "x8,fp,s0": "0x18", + "x9,s1": "0xffffe00", + mtime: "0xa", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_040.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_040.s.snap new file mode 100644 index 000000000..919fb9151 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_040.s.snap @@ -0,0 +1,57 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_040.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 1, + "10": 227, + "11": 183, + "13": 3, + "14": 131, + "15": 147, + "16": 1, + "17": 128, + "18": 4, + "19": 19, + "2": 2, + "20": 2, + "21": 83, + "22": 228, + "23": 179, + "24": 2, + "25": 83, + "26": 101, + "27": 51, + "28": 2, + "29": 131, + "3": 147, + "30": 229, + "31": 179, + "32": 2, + "33": 116, + "34": 102, + "35": 51, + "38": 128, + "39": 103, + "4": 16, + "6": 3, + "7": 19, + "8": 255, + "9": 255, + }, + registers: { + "x11,a1": "0x8", + "x12,a2": "0x18", + "x5,t0": "0x10", + "x6,t1": "0x100", + "x7,t2": "0xffffe000", + "x8,fp,s0": "0x18", + mtime: "0xa", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_041.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_041.s.snap new file mode 100644 index 000000000..e740b32b2 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_041.s.snap @@ -0,0 +1,57 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_041.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 1, + "10": 227, + "11": 183, + "13": 3, + "14": 131, + "15": 147, + "16": 1, + "17": 128, + "18": 4, + "19": 19, + "2": 2, + "20": 2, + "21": 83, + "22": 244, + "23": 179, + "24": 2, + "25": 83, + "26": 117, + "27": 51, + "28": 2, + "29": 131, + "3": 147, + "30": 245, + "31": 179, + "32": 2, + "33": 116, + "34": 118, + "35": 51, + "38": 128, + "39": 103, + "4": 16, + "6": 3, + "7": 19, + "8": 255, + "9": 255, + }, + registers: { + "x11,a1": "0x8", + "x12,a2": "0x18", + "x5,t0": "0x10", + "x6,t1": "0x100", + "x7,t2": "0xffffe000", + "x8,fp,s0": "0x18", + mtime: "0xa", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_042.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_042.s.snap new file mode 100644 index 000000000..26f51e141 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_042.s.snap @@ -0,0 +1,62 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_042.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 55, + "1": 32, + "10": 3, + "11": 147, + "12": 33, + "13": 240, + "14": 4, + "15": 19, + "17": 98, + "18": 202, + "19": 99, + "2": 2, + "21": 84, + "22": 72, + "23": 99, + "24": 2, + "25": 32, + "26": 14, + "27": 19, + "29": 160, + "3": 147, + "30": 8, + "31": 147, + "35": 115, + "37": 176, + "38": 2, + "39": 147, + "4": 55, + "40": 34, + "41": 176, + "42": 3, + "43": 19, + "44": 254, + "45": 98, + "46": 198, + "47": 227, + "5": 16, + "6": 3, + "7": 19, + "9": 80, + }, + registers: { + "x17,a7": "0xa", + "x28,t3": "0x22", + "x5,t0": "0xb", + "x6,t1": "0x22b", + "x7,t2": "0x5", + "x8,fp,s0": "0x21f", + mtime: "0xc", + pc: "0x24", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_043.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_043.s.snap new file mode 100644 index 000000000..883965a92 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_043.s.snap @@ -0,0 +1,62 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_043.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 200, + "1": 224, + "10": 3, + "11": 147, + "12": 33, + "13": 240, + "14": 4, + "15": 19, + "17": 83, + "18": 106, + "19": 99, + "2": 2, + "21": 131, + "22": 232, + "23": 99, + "24": 2, + "25": 32, + "26": 14, + "27": 19, + "29": 160, + "3": 147, + "30": 8, + "31": 147, + "35": 115, + "37": 176, + "38": 2, + "39": 147, + "4": 200, + "40": 34, + "41": 176, + "42": 3, + "43": 19, + "44": 254, + "45": 98, + "46": 230, + "47": 227, + "5": 240, + "6": 3, + "7": 19, + "9": 80, + }, + registers: { + "x17,a7": "0xa", + "x28,t3": "0x22", + "x5,t0": "0xb", + "x6,t1": "0x22b", + "x7,t2": "0x5", + "x8,fp,s0": "0x21f", + mtime: "0xc", + pc: "0x24", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_044.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_044.s.snap new file mode 100644 index 000000000..b85443449 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_044.s.snap @@ -0,0 +1,62 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_044.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 55, + "1": 32, + "10": 3, + "11": 147, + "12": 33, + "13": 240, + "14": 4, + "15": 19, + "17": 83, + "18": 90, + "19": 99, + "2": 2, + "21": 116, + "22": 88, + "23": 99, + "24": 2, + "25": 32, + "26": 14, + "27": 19, + "29": 160, + "3": 147, + "30": 8, + "31": 147, + "35": 115, + "37": 176, + "38": 2, + "39": 147, + "4": 55, + "40": 34, + "41": 176, + "42": 3, + "43": 19, + "44": 254, + "45": 83, + "46": 86, + "47": 227, + "5": 16, + "6": 3, + "7": 19, + "9": 80, + }, + registers: { + "x17,a7": "0xa", + "x28,t3": "0x22", + "x5,t0": "0xb", + "x6,t1": "0x22b", + "x7,t2": "0x5", + "x8,fp,s0": "0x21f", + mtime: "0xc", + pc: "0x24", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_045.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_045.s.snap new file mode 100644 index 000000000..c468a7b0c --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_045.s.snap @@ -0,0 +1,62 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_045.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 200, + "1": 224, + "10": 3, + "11": 147, + "12": 222, + "13": 16, + "14": 4, + "15": 19, + "17": 98, + "18": 218, + "19": 99, + "2": 2, + "21": 100, + "22": 88, + "23": 99, + "24": 2, + "25": 32, + "26": 14, + "27": 19, + "29": 160, + "3": 147, + "30": 8, + "31": 147, + "35": 115, + "37": 176, + "38": 2, + "39": 147, + "4": 200, + "40": 221, + "41": 80, + "42": 3, + "43": 19, + "44": 254, + "45": 98, + "46": 214, + "47": 227, + "5": 240, + "6": 3, + "7": 19, + "9": 80, + }, + registers: { + "x17,a7": "0xa", + "x28,t3": "0x22", + "x5,t0": "0xb", + "x6,t1": "0xfffffdd5", + "x7,t2": "0x5", + "x8,fp,s0": "0xfffffde1", + mtime: "0xc", + pc: "0x24", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_046.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_046.s.snap new file mode 100644 index 000000000..4c33f942b --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_046.s.snap @@ -0,0 +1,57 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_046.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 2, + "10": 19, + "11": 55, + "12": 29, + "13": 115, + "14": 3, + "15": 19, + "16": 255, + "17": 255, + "18": 227, + "19": 183, + "2": 34, + "20": 175, + "21": 35, + "22": 131, + "23": 147, + "24": 255, + "25": 242, + "26": 196, + "27": 19, + "28": 255, + "29": 243, + "3": 183, + "30": 68, + "31": 147, + "32": 255, + "33": 243, + "34": 197, + "35": 19, + "38": 128, + "39": 103, + "4": 52, + "5": 98, + "6": 130, + "7": 147, + }, + registers: { + "x10,a0": "0x250d", + "x5,t0": "0x22346", + "x6,t1": "0x11d7", + "x7,t2": "0xffffdaf2", + "x8,fp,s0": "0xfffddcb9", + "x9,s1": "0xffffee28", + mtime: "0xa", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_047.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_047.s.snap new file mode 100644 index 000000000..c89e60c59 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_047.s.snap @@ -0,0 +1,57 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_047.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 2, + "10": 19, + "11": 55, + "12": 29, + "13": 115, + "14": 3, + "15": 19, + "16": 255, + "17": 255, + "18": 227, + "19": 183, + "2": 34, + "20": 175, + "21": 35, + "22": 131, + "23": 147, + "24": 64, + "25": 80, + "26": 4, + "27": 51, + "28": 64, + "29": 96, + "3": 183, + "30": 4, + "31": 179, + "32": 64, + "33": 112, + "34": 5, + "35": 51, + "38": 128, + "39": 103, + "4": 52, + "5": 98, + "6": 130, + "7": 147, + }, + registers: { + "x10,a0": "0x250e", + "x5,t0": "0x22346", + "x6,t1": "0x11d7", + "x7,t2": "0xffffdaf2", + "x8,fp,s0": "0xfffddcba", + "x9,s1": "0xffffee29", + mtime: "0xa", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_048.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_048.s.snap new file mode 100644 index 000000000..ea0c52a58 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_048.s.snap @@ -0,0 +1,39 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_048.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 16, + "10": 3, + "11": 19, + "13": 18, + "14": 52, + "15": 19, + "17": 18, + "18": 180, + "19": 147, + "2": 2, + "21": 19, + "22": 53, + "23": 19, + "26": 128, + "27": 103, + "3": 19, + "6": 2, + "7": 147, + "8": 255, + "9": 240, + }, + registers: { + "x4,tp": "0x1", + "x6,t1": "0xffffffff", + "x9,s1": "0x1", + mtime: "0x7", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_049.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_049.s.snap new file mode 100644 index 000000000..9df3e6760 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_049.s.snap @@ -0,0 +1,40 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_049.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 16, + "10": 3, + "11": 19, + "13": 64, + "14": 52, + "15": 51, + "17": 80, + "18": 52, + "19": 179, + "2": 2, + "21": 96, + "22": 53, + "23": 51, + "26": 128, + "27": 103, + "3": 19, + "6": 2, + "7": 147, + "8": 255, + "9": 240, + }, + registers: { + "x10,a0": "0x1", + "x4,tp": "0x1", + "x6,t1": "0xffffffff", + "x8,fp,s0": "0x1", + mtime: "0x7", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_050.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_050.s.snap new file mode 100644 index 000000000..70bc8cb53 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_050.s.snap @@ -0,0 +1,39 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_050.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 16, + "10": 3, + "11": 19, + "13": 64, + "14": 36, + "15": 51, + "17": 80, + "18": 36, + "19": 179, + "2": 2, + "21": 96, + "22": 37, + "23": 51, + "26": 128, + "27": 103, + "3": 19, + "6": 2, + "7": 147, + "8": 255, + "9": 240, + }, + registers: { + "x4,tp": "0x1", + "x6,t1": "0xffffffff", + "x8,fp,s0": "0x1", + mtime: "0x7", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_051.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_051.s.snap new file mode 100644 index 000000000..a18d804e1 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_051.s.snap @@ -0,0 +1,39 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_051.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 16, + "10": 3, + "11": 19, + "13": 2, + "14": 36, + "15": 51, + "17": 2, + "18": 164, + "19": 179, + "2": 2, + "21": 3, + "22": 37, + "23": 51, + "26": 128, + "27": 103, + "3": 19, + "6": 2, + "7": 147, + "8": 255, + "9": 240, + }, + registers: { + "x10,a0": "0x1", + "x4,tp": "0x1", + "x6,t1": "0xffffffff", + mtime: "0x7", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_052.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_052.s.snap new file mode 100644 index 000000000..473f0ded1 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_052.s.snap @@ -0,0 +1,152 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_052.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 32, + "10": 3, + "103": 115, + "11": 23, + "13": 3, + "14": 3, + "15": 19, + "17": 32, + "18": 3, + "19": 151, + "2": 2, + "2097152": 64, + "2097153": 131, + "2097154": 84, + "2097155": 250, + "2097156": 109, + "2097157": 239, + "2097158": 199, + "2097159": 164, + "2097160": 64, + "2097161": 140, + "2097162": 18, + "2097163": 192, + "2097164": 131, + "2097165": 18, + "2097166": 110, + "2097167": 152, + "2097168": 64, + "2097169": 195, + "2097170": 92, + "2097171": 198, + "2097172": 102, + "2097173": 102, + "2097174": 102, + "2097175": 102, + "2097176": 66, + "2097177": 247, + "2097178": 62, + "2097179": 155, + "2097180": 67, + "2097181": 228, + "2097182": 44, + "2097183": 8, + "2097184": 197, + "2097185": 236, + "2097186": 20, + "2097187": 102, + "21": 3, + "22": 131, + "23": 147, + "25": 32, + "26": 4, + "27": 23, + "29": 4, + "3": 151, + "30": 4, + "31": 19, + "33": 32, + "34": 4, + "35": 151, + "36": 255, + "37": 196, + "38": 132, + "39": 147, + "41": 32, + "42": 5, + "43": 23, + "44": 255, + "45": 133, + "46": 5, + "47": 19, + "49": 2, + "5": 2, + "50": 176, + "51": 7, + "53": 3, + "54": 49, + "55": 7, + "57": 3, + "58": 178, + "59": 7, + "6": 130, + "60": 2, + "62": 3, + "63": 83, + "64": 2, + "65": 33, + "66": 4, + "67": 83, + "68": 2, + "69": 66, + "7": 147, + "70": 5, + "71": 83, + "73": 4, + "74": 38, + "75": 7, + "77": 4, + "78": 167, + "79": 7, + "81": 5, + "82": 40, + "83": 7, + "85": 230, + "86": 9, + "87": 83, + "88": 1, + "89": 7, + "9": 32, + "90": 10, + "91": 83, + "93": 200, + "94": 11, + "95": 83, + "97": 160, + "98": 8, + "99": 147, + }, + registers: { + "f0,ft0": "0x408354fa6defc7a4", + "f10,fa0": "0x40d35cc666666666", + "f12,fa2": "0xffffffff42f73e9b", + "f14,fa4": "0xffffffff43e42c08", + "f16,fa6": "0xffffffffc5ec1466", + "f18,fs2": "0xffffffff4410fdd7", + "f2,ft2": "0x408c12c083126e98", + "f20,fs4": "0xffffffffc5ddd1a6", + "f22,fs6": "0xffffffffc5e8376c", + "f4,ft4": "0x40c35cc666666666", + "f6,ft6": "0x409354fa6defc7a4", + "f8,fs0": "0x409c12c083126e98", + "x10,a0": "0x200020", + "x17,a7": "0xa", + "x5,t0": "0x200000", + "x6,t1": "0x200008", + "x7,t2": "0x200010", + "x8,fp,s0": "0x200018", + "x9,s1": "0x20001c", + mtime: "0x1a", + pc: "0x68", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_053.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_053.s.snap new file mode 100644 index 000000000..8273c7b7a --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_053.s.snap @@ -0,0 +1,155 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_053.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 32, + "10": 3, + "103": 115, + "11": 23, + "13": 3, + "14": 3, + "15": 19, + "17": 32, + "18": 3, + "19": 151, + "2": 2, + "2097152": 64, + "2097153": 131, + "2097154": 84, + "2097155": 250, + "2097156": 109, + "2097157": 239, + "2097158": 199, + "2097159": 164, + "2097160": 64, + "2097161": 140, + "2097162": 18, + "2097163": 192, + "2097164": 131, + "2097165": 18, + "2097166": 110, + "2097167": 152, + "2097168": 64, + "2097169": 195, + "2097170": 92, + "2097171": 198, + "2097172": 102, + "2097173": 102, + "2097174": 102, + "2097175": 102, + "2097176": 66, + "2097177": 247, + "2097178": 62, + "2097179": 155, + "2097180": 67, + "2097181": 228, + "2097182": 44, + "2097183": 8, + "2097184": 197, + "2097185": 236, + "2097186": 20, + "2097187": 102, + "21": 3, + "22": 131, + "23": 147, + "25": 32, + "26": 4, + "27": 23, + "29": 4, + "3": 151, + "30": 4, + "31": 19, + "33": 32, + "34": 4, + "35": 151, + "36": 255, + "37": 196, + "38": 132, + "39": 147, + "41": 32, + "42": 5, + "43": 23, + "44": 255, + "45": 133, + "46": 5, + "47": 19, + "49": 2, + "5": 2, + "50": 176, + "51": 7, + "53": 3, + "54": 49, + "55": 7, + "57": 3, + "58": 178, + "59": 7, + "6": 130, + "60": 10, + "61": 32, + "62": 3, + "63": 83, + "64": 10, + "65": 65, + "66": 4, + "67": 83, + "68": 10, + "69": 2, + "7": 147, + "70": 5, + "71": 83, + "73": 4, + "74": 38, + "75": 7, + "77": 4, + "78": 167, + "79": 7, + "81": 5, + "82": 40, + "83": 7, + "84": 8, + "85": 230, + "86": 9, + "87": 83, + "88": 9, + "89": 7, + "9": 32, + "90": 10, + "91": 83, + "92": 8, + "93": 200, + "94": 11, + "95": 83, + "97": 160, + "98": 8, + "99": 147, + }, + registers: { + "f0,ft0": "0x408354fa6defc7a4", + "f10,fa0": "0x40c22776bf8769ec", + "f12,fa2": "0xffffffff42f73e9b", + "f14,fa4": "0xffffffff43e42c08", + "f16,fa6": "0xffffffffc5ec1466", + "f18,fs2": "0xffffffffc3a65c61", + "f2,ft2": "0x408c12c083126e98", + "f20,fs4": "0xffffffff45fa5726", + "f22,fs6": "0xffffffffc5eff160", + "f4,ft4": "0x40c35cc666666666", + "f6,ft6": "0xc0717b8c2a454de8", + "f8,fs0": "0xc0c19b9a5e353f7c", + "x10,a0": "0x200020", + "x17,a7": "0xa", + "x5,t0": "0x200000", + "x6,t1": "0x200008", + "x7,t2": "0x200010", + "x8,fp,s0": "0x200018", + "x9,s1": "0x20001c", + mtime: "0x1a", + pc: "0x68", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_054.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_054.s.snap new file mode 100644 index 000000000..87c4d0346 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_054.s.snap @@ -0,0 +1,154 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_054.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 32, + "10": 3, + "103": 115, + "11": 23, + "13": 3, + "14": 3, + "15": 19, + "17": 32, + "18": 3, + "19": 151, + "2": 2, + "2097152": 64, + "2097153": 131, + "2097154": 84, + "2097155": 250, + "2097156": 109, + "2097157": 239, + "2097158": 199, + "2097159": 164, + "2097160": 64, + "2097161": 140, + "2097162": 18, + "2097163": 192, + "2097164": 131, + "2097165": 18, + "2097166": 110, + "2097167": 152, + "2097168": 64, + "2097169": 195, + "2097170": 92, + "2097171": 198, + "2097172": 102, + "2097173": 102, + "2097174": 102, + "2097175": 102, + "2097176": 66, + "2097177": 247, + "2097178": 62, + "2097179": 155, + "2097180": 67, + "2097181": 228, + "2097182": 44, + "2097183": 8, + "2097184": 197, + "2097185": 236, + "2097186": 20, + "2097187": 102, + "21": 3, + "22": 131, + "23": 147, + "25": 32, + "26": 4, + "27": 23, + "29": 4, + "3": 151, + "30": 4, + "31": 19, + "33": 32, + "34": 4, + "35": 151, + "36": 255, + "37": 196, + "38": 132, + "39": 147, + "41": 32, + "42": 5, + "43": 23, + "44": 255, + "45": 133, + "46": 5, + "47": 19, + "49": 2, + "5": 2, + "50": 176, + "51": 7, + "53": 3, + "54": 49, + "55": 7, + "57": 3, + "58": 178, + "59": 7, + "6": 130, + "60": 18, + "62": 3, + "63": 83, + "64": 18, + "65": 33, + "66": 4, + "67": 83, + "68": 18, + "69": 66, + "7": 147, + "70": 5, + "71": 83, + "73": 4, + "74": 38, + "75": 7, + "77": 4, + "78": 167, + "79": 7, + "81": 5, + "82": 40, + "83": 7, + "84": 16, + "85": 230, + "86": 9, + "87": 83, + "88": 17, + "89": 7, + "9": 32, + "90": 10, + "91": 83, + "92": 16, + "93": 200, + "94": 11, + "95": 83, + "97": 160, + "98": 8, + "99": 147, + }, + registers: { + "f0,ft0": "0x408354fa6defc7a4", + "f10,fa0": "0x41976e712668f5c2", + "f12,fa2": "0xffffffff42f73e9b", + "f14,fa4": "0xffffffff43e42c08", + "f16,fa6": "0xffffffffc5ec1466", + "f18,fs2": "0xffffffff475c5e49", + "f2,ft2": "0x408c12c083126e98", + "f20,fs4": "0xffffffffca526ac6", + "f22,fs6": "0xffffffffc964016a", + "f4,ft4": "0x40c35cc666666666", + "f6,ft6": "0x41175b9619eb7e4e", + "f8,fs0": "0x4128a0dbe279dd3c", + "x10,a0": "0x200020", + "x17,a7": "0xa", + "x5,t0": "0x200000", + "x6,t1": "0x200008", + "x7,t2": "0x200010", + "x8,fp,s0": "0x200018", + "x9,s1": "0x20001c", + mtime: "0x1a", + pc: "0x68", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_055.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_055.s.snap new file mode 100644 index 000000000..ab316c6e0 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_055.s.snap @@ -0,0 +1,154 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_055.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 32, + "10": 3, + "103": 115, + "11": 23, + "13": 3, + "14": 3, + "15": 19, + "17": 32, + "18": 3, + "19": 151, + "2": 2, + "2097152": 64, + "2097153": 131, + "2097154": 84, + "2097155": 250, + "2097156": 109, + "2097157": 239, + "2097158": 199, + "2097159": 164, + "2097160": 64, + "2097161": 140, + "2097162": 18, + "2097163": 192, + "2097164": 131, + "2097165": 18, + "2097166": 110, + "2097167": 152, + "2097168": 64, + "2097169": 195, + "2097170": 92, + "2097171": 198, + "2097172": 102, + "2097173": 102, + "2097174": 102, + "2097175": 102, + "2097176": 66, + "2097177": 247, + "2097178": 62, + "2097179": 155, + "2097180": 67, + "2097181": 228, + "2097182": 44, + "2097183": 8, + "2097184": 197, + "2097185": 236, + "2097186": 20, + "2097187": 102, + "21": 3, + "22": 131, + "23": 147, + "25": 32, + "26": 4, + "27": 23, + "29": 4, + "3": 151, + "30": 4, + "31": 19, + "33": 32, + "34": 4, + "35": 151, + "36": 255, + "37": 196, + "38": 132, + "39": 147, + "41": 32, + "42": 5, + "43": 23, + "44": 255, + "45": 133, + "46": 5, + "47": 19, + "49": 2, + "5": 2, + "50": 176, + "51": 7, + "53": 3, + "54": 49, + "55": 7, + "57": 3, + "58": 178, + "59": 7, + "6": 130, + "60": 26, + "62": 3, + "63": 83, + "64": 26, + "65": 33, + "66": 4, + "67": 83, + "68": 26, + "69": 66, + "7": 147, + "70": 5, + "71": 83, + "73": 4, + "74": 38, + "75": 7, + "77": 4, + "78": 167, + "79": 7, + "81": 5, + "82": 40, + "83": 7, + "84": 24, + "85": 230, + "86": 9, + "87": 83, + "88": 25, + "89": 7, + "9": 32, + "90": 10, + "91": 83, + "92": 24, + "93": 200, + "94": 11, + "95": 83, + "97": 160, + "98": 8, + "99": 147, + }, + registers: { + "f0,ft0": "0x408354fa6defc7a4", + "f10,fa0": "0x3ff0000000000000", + "f12,fa2": "0xffffffff42f73e9b", + "f14,fa4": "0xffffffff43e42c08", + "f16,fa6": "0xffffffffc5ec1466", + "f18,fs2": "0xffffffff3e8ab307", + "f2,ft2": "0x408c12c083126e98", + "f20,fs4": "0xffffffffbd776cd1", + "f22,fs6": "0xffffffffc2747094", + "f4,ft4": "0x40c35cc666666666", + "f6,ft6": "0x3ff0000000000000", + "f8,fs0": "0x3ff0000000000000", + "x10,a0": "0x200020", + "x17,a7": "0xa", + "x5,t0": "0x200000", + "x6,t1": "0x200008", + "x7,t2": "0x200010", + "x8,fp,s0": "0x200018", + "x9,s1": "0x20001c", + mtime: "0x1a", + pc: "0x68", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_056.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_056.s.snap new file mode 100644 index 000000000..6cf69cd3b --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_056.s.snap @@ -0,0 +1,155 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_056.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 32, + "10": 3, + "103": 115, + "11": 23, + "13": 3, + "14": 3, + "15": 19, + "17": 32, + "18": 3, + "19": 151, + "2": 2, + "2097152": 64, + "2097153": 131, + "2097154": 84, + "2097155": 250, + "2097156": 109, + "2097157": 239, + "2097158": 199, + "2097159": 164, + "2097160": 64, + "2097161": 140, + "2097162": 18, + "2097163": 192, + "2097164": 131, + "2097165": 18, + "2097166": 110, + "2097167": 152, + "2097168": 64, + "2097169": 195, + "2097170": 92, + "2097171": 198, + "2097172": 102, + "2097173": 102, + "2097174": 102, + "2097175": 102, + "2097176": 66, + "2097177": 247, + "2097178": 62, + "2097179": 155, + "2097180": 67, + "2097181": 228, + "2097182": 44, + "2097183": 8, + "2097184": 197, + "2097185": 236, + "2097186": 20, + "2097187": 102, + "21": 3, + "22": 131, + "23": 147, + "25": 32, + "26": 4, + "27": 23, + "29": 4, + "3": 151, + "30": 4, + "31": 19, + "33": 32, + "34": 4, + "35": 151, + "36": 255, + "37": 196, + "38": 132, + "39": 147, + "41": 32, + "42": 5, + "43": 23, + "44": 255, + "45": 133, + "46": 5, + "47": 19, + "49": 2, + "5": 2, + "50": 176, + "51": 7, + "53": 3, + "54": 49, + "55": 7, + "57": 3, + "58": 178, + "59": 7, + "6": 130, + "60": 42, + "61": 32, + "62": 3, + "63": 83, + "64": 42, + "65": 65, + "66": 4, + "67": 83, + "68": 42, + "69": 2, + "7": 147, + "70": 5, + "71": 83, + "73": 4, + "74": 38, + "75": 7, + "77": 4, + "78": 167, + "79": 7, + "81": 5, + "82": 40, + "83": 7, + "84": 40, + "85": 230, + "86": 9, + "87": 83, + "88": 41, + "89": 7, + "9": 32, + "90": 10, + "91": 83, + "92": 40, + "93": 200, + "94": 11, + "95": 83, + "97": 160, + "98": 8, + "99": 147, + }, + registers: { + "f0,ft0": "0x408354fa6defc7a4", + "f10,fa0": "0x408354fa6defc7a4", + "f12,fa2": "0xffffffff42f73e9b", + "f14,fa4": "0xffffffff43e42c08", + "f16,fa6": "0xffffffffc5ec1466", + "f18,fs2": "0xffffffff42f73e9b", + "f2,ft2": "0x408c12c083126e98", + "f20,fs4": "0xffffffffc5ec1466", + "f22,fs6": "0xffffffffc5ec1466", + "f4,ft4": "0x40c35cc666666666", + "f6,ft6": "0x408354fa6defc7a4", + "f8,fs0": "0x408c12c083126e98", + "x10,a0": "0x200020", + "x17,a7": "0xa", + "x5,t0": "0x200000", + "x6,t1": "0x200008", + "x7,t2": "0x200010", + "x8,fp,s0": "0x200018", + "x9,s1": "0x20001c", + mtime: "0x1a", + pc: "0x68", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_057.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_057.s.snap new file mode 100644 index 000000000..0c98667bd --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_057.s.snap @@ -0,0 +1,155 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_057.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 32, + "10": 3, + "103": 115, + "11": 23, + "13": 3, + "14": 3, + "15": 19, + "17": 32, + "18": 3, + "19": 151, + "2": 2, + "2097152": 64, + "2097153": 131, + "2097154": 84, + "2097155": 250, + "2097156": 109, + "2097157": 239, + "2097158": 199, + "2097159": 164, + "2097160": 64, + "2097161": 140, + "2097162": 18, + "2097163": 192, + "2097164": 131, + "2097165": 18, + "2097166": 110, + "2097167": 152, + "2097168": 64, + "2097169": 195, + "2097170": 92, + "2097171": 198, + "2097172": 102, + "2097173": 102, + "2097174": 102, + "2097175": 102, + "2097176": 66, + "2097177": 247, + "2097178": 62, + "2097179": 155, + "2097180": 67, + "2097181": 228, + "2097182": 44, + "2097183": 8, + "2097184": 197, + "2097185": 236, + "2097186": 20, + "2097187": 102, + "21": 3, + "22": 131, + "23": 147, + "25": 32, + "26": 4, + "27": 23, + "29": 4, + "3": 151, + "30": 4, + "31": 19, + "33": 32, + "34": 4, + "35": 151, + "36": 255, + "37": 196, + "38": 132, + "39": 147, + "41": 32, + "42": 5, + "43": 23, + "44": 255, + "45": 133, + "46": 5, + "47": 19, + "49": 2, + "5": 2, + "50": 176, + "51": 7, + "53": 3, + "54": 49, + "55": 7, + "57": 3, + "58": 178, + "59": 7, + "6": 130, + "60": 42, + "61": 32, + "62": 19, + "63": 83, + "64": 42, + "65": 65, + "66": 20, + "67": 83, + "68": 42, + "69": 2, + "7": 147, + "70": 21, + "71": 83, + "73": 4, + "74": 38, + "75": 7, + "77": 4, + "78": 167, + "79": 7, + "81": 5, + "82": 40, + "83": 7, + "84": 40, + "85": 230, + "86": 25, + "87": 83, + "88": 41, + "89": 7, + "9": 32, + "90": 26, + "91": 83, + "92": 40, + "93": 200, + "94": 27, + "95": 83, + "97": 160, + "98": 8, + "99": 147, + }, + registers: { + "f0,ft0": "0x408354fa6defc7a4", + "f10,fa0": "0x40c35cc666666666", + "f12,fa2": "0xffffffff42f73e9b", + "f14,fa4": "0xffffffff43e42c08", + "f16,fa6": "0xffffffffc5ec1466", + "f18,fs2": "0xffffffff43e42c08", + "f2,ft2": "0x408c12c083126e98", + "f20,fs4": "0xffffffff43e42c08", + "f22,fs6": "0xffffffff42f73e9b", + "f4,ft4": "0x40c35cc666666666", + "f6,ft6": "0x408c12c083126e98", + "f8,fs0": "0x40c35cc666666666", + "x10,a0": "0x200020", + "x17,a7": "0xa", + "x5,t0": "0x200000", + "x6,t1": "0x200008", + "x7,t2": "0x200010", + "x8,fp,s0": "0x200018", + "x9,s1": "0x20001c", + mtime: "0x1a", + pc: "0x68", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_058.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_058.s.snap new file mode 100644 index 000000000..cb99e278d --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_058.s.snap @@ -0,0 +1,131 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_058.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 32, + "10": 3, + "103": 115, + "11": 23, + "13": 3, + "14": 3, + "15": 19, + "17": 32, + "18": 3, + "19": 151, + "2": 2, + "2097152": 64, + "2097153": 112, + "2097160": 64, + "2097161": 171, + "2097162": 50, + "2097168": 64, + "2097169": 181, + "2097170": 100, + "2097176": 70, + "2097177": 25, + "2097178": 36, + "2097180": 70, + "2097181": 1, + "2097182": 100, + "2097184": 70, + "2097185": 16, + "21": 3, + "22": 131, + "23": 147, + "25": 32, + "26": 4, + "27": 23, + "29": 4, + "3": 151, + "30": 4, + "31": 19, + "33": 32, + "34": 4, + "35": 151, + "36": 255, + "37": 196, + "38": 132, + "39": 147, + "41": 32, + "42": 5, + "43": 23, + "44": 255, + "45": 133, + "46": 5, + "47": 19, + "49": 2, + "5": 2, + "50": 176, + "51": 7, + "53": 3, + "54": 49, + "55": 7, + "57": 3, + "58": 178, + "59": 7, + "6": 130, + "60": 90, + "62": 3, + "63": 83, + "64": 90, + "65": 1, + "66": 4, + "67": 83, + "68": 90, + "69": 2, + "7": 147, + "70": 5, + "71": 83, + "73": 4, + "74": 38, + "75": 7, + "77": 4, + "78": 167, + "79": 7, + "81": 5, + "82": 40, + "83": 7, + "84": 88, + "85": 6, + "86": 3, + "87": 83, + "88": 88, + "89": 7, + "9": 32, + "90": 4, + "91": 83, + "92": 88, + "93": 8, + "94": 5, + "95": 83, + "97": 160, + "98": 8, + "99": 147, + }, + registers: { + "f0,ft0": "0x4070000000000000", + "f10,fa0": "0xffffffff42c00000", + "f12,fa2": "0xffffffff46192400", + "f14,fa4": "0xffffffff46016400", + "f16,fa6": "0xffffffff46100000", + "f2,ft2": "0x40ab320000000000", + "f4,ft4": "0x40b5640000000000", + "f6,ft6": "0xffffffff42c60000", + "f8,fs0": "0xffffffff42b60000", + "x10,a0": "0x200020", + "x17,a7": "0xa", + "x5,t0": "0x200000", + "x6,t1": "0x200008", + "x7,t2": "0x200010", + "x8,fp,s0": "0x200018", + "x9,s1": "0x20001c", + mtime: "0x1a", + pc: "0x68", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_059.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_059.s.snap new file mode 100644 index 000000000..96406e977 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_059.s.snap @@ -0,0 +1,131 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_059.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 32, + "10": 3, + "103": 115, + "11": 23, + "13": 3, + "14": 3, + "15": 19, + "17": 32, + "18": 3, + "19": 151, + "2": 2, + "2097152": 64, + "2097153": 112, + "2097160": 64, + "2097161": 171, + "2097162": 50, + "2097168": 64, + "2097169": 181, + "2097170": 100, + "2097176": 70, + "2097177": 25, + "2097178": 36, + "2097180": 70, + "2097181": 1, + "2097182": 100, + "2097184": 70, + "2097185": 16, + "21": 3, + "22": 131, + "23": 147, + "25": 32, + "26": 4, + "27": 23, + "29": 4, + "3": 151, + "30": 4, + "31": 19, + "33": 32, + "34": 4, + "35": 151, + "36": 255, + "37": 196, + "38": 132, + "39": 147, + "41": 32, + "42": 5, + "43": 23, + "44": 255, + "45": 133, + "46": 5, + "47": 19, + "49": 2, + "5": 2, + "50": 176, + "51": 7, + "53": 3, + "54": 49, + "55": 7, + "57": 3, + "58": 178, + "59": 7, + "6": 130, + "60": 2, + "62": 3, + "63": 67, + "64": 18, + "65": 33, + "66": 4, + "67": 67, + "68": 34, + "69": 66, + "7": 147, + "70": 5, + "71": 67, + "73": 4, + "74": 38, + "75": 7, + "77": 4, + "78": 167, + "79": 7, + "81": 5, + "82": 40, + "83": 7, + "84": 96, + "85": 198, + "86": 3, + "87": 67, + "88": 112, + "89": 231, + "9": 32, + "90": 4, + "91": 67, + "92": 129, + "93": 8, + "94": 5, + "95": 67, + "97": 160, + "98": 8, + "99": 147, + }, + registers: { + "f0,ft0": "0x4070000000000000", + "f10,fa0": "0xffffffff4ca20480", + "f12,fa2": "0xffffffff46192400", + "f14,fa4": "0xffffffff46016400", + "f16,fa6": "0xffffffff46100000", + "f2,ft2": "0x40ab320000000000", + "f4,ft4": "0x40b5640000000000", + "f6,ft6": "0xffffffff4cb73ce3", + "f8,fs0": "0xffffffff4c82cfe9", + "x10,a0": "0x200020", + "x17,a7": "0xa", + "x5,t0": "0x200000", + "x6,t1": "0x200008", + "x7,t2": "0x200010", + "x8,fp,s0": "0x200018", + "x9,s1": "0x20001c", + mtime: "0x1a", + pc: "0x68", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_060.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_060.s.snap new file mode 100644 index 000000000..ac1b19a83 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_060.s.snap @@ -0,0 +1,131 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_060.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 32, + "10": 3, + "103": 115, + "11": 23, + "13": 3, + "14": 3, + "15": 19, + "17": 32, + "18": 3, + "19": 151, + "2": 2, + "2097152": 64, + "2097153": 112, + "2097160": 64, + "2097161": 171, + "2097162": 50, + "2097168": 64, + "2097169": 181, + "2097170": 100, + "2097176": 70, + "2097177": 25, + "2097178": 36, + "2097180": 70, + "2097181": 1, + "2097182": 100, + "2097184": 70, + "2097185": 16, + "21": 3, + "22": 131, + "23": 147, + "25": 32, + "26": 4, + "27": 23, + "29": 4, + "3": 151, + "30": 4, + "31": 19, + "33": 32, + "34": 4, + "35": 151, + "36": 255, + "37": 196, + "38": 132, + "39": 147, + "41": 32, + "42": 5, + "43": 23, + "44": 255, + "45": 133, + "46": 5, + "47": 19, + "49": 2, + "5": 2, + "50": 176, + "51": 7, + "53": 3, + "54": 49, + "55": 7, + "57": 3, + "58": 178, + "59": 7, + "6": 130, + "60": 2, + "62": 3, + "63": 71, + "64": 18, + "65": 33, + "66": 4, + "67": 71, + "68": 34, + "69": 66, + "7": 147, + "70": 5, + "71": 71, + "73": 4, + "74": 38, + "75": 7, + "77": 4, + "78": 167, + "79": 7, + "81": 5, + "82": 40, + "83": 7, + "84": 96, + "85": 198, + "86": 3, + "87": 71, + "88": 112, + "89": 231, + "9": 32, + "90": 4, + "91": 71, + "92": 129, + "93": 8, + "94": 5, + "95": 71, + "97": 160, + "98": 8, + "99": 147, + }, + registers: { + "f0,ft0": "0x4070000000000000", + "f10,fa0": "0xffffffff4ca1fb80", + "f12,fa2": "0xffffffff46192400", + "f14,fa4": "0xffffffff46016400", + "f16,fa6": "0xffffffff46100000", + "f2,ft2": "0x40ab320000000000", + "f4,ft4": "0x40b5640000000000", + "f6,ft6": "0xffffffff4cb73351", + "f8,fs0": "0xffffffff4c82c7d3", + "x10,a0": "0x200020", + "x17,a7": "0xa", + "x5,t0": "0x200000", + "x6,t1": "0x200008", + "x7,t2": "0x200010", + "x8,fp,s0": "0x200018", + "x9,s1": "0x20001c", + mtime: "0x1a", + pc: "0x68", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_061.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_061.s.snap new file mode 100644 index 000000000..82fff505f --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_061.s.snap @@ -0,0 +1,134 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_061.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 32, + "10": 3, + "103": 115, + "11": 23, + "13": 3, + "14": 3, + "15": 19, + "17": 32, + "18": 3, + "19": 151, + "2": 2, + "2097152": 64, + "2097153": 112, + "2097160": 192, + "2097161": 171, + "2097162": 50, + "2097168": 64, + "2097169": 181, + "2097170": 100, + "2097176": 198, + "2097177": 25, + "2097178": 36, + "2097180": 70, + "2097181": 1, + "2097182": 100, + "2097184": 198, + "2097185": 16, + "21": 3, + "22": 131, + "23": 147, + "25": 32, + "26": 4, + "27": 23, + "29": 4, + "3": 151, + "30": 4, + "31": 19, + "33": 32, + "34": 4, + "35": 151, + "36": 255, + "37": 196, + "38": 132, + "39": 147, + "41": 32, + "42": 5, + "43": 23, + "44": 255, + "45": 133, + "46": 5, + "47": 19, + "49": 2, + "5": 2, + "50": 176, + "51": 7, + "53": 3, + "54": 49, + "55": 7, + "57": 3, + "58": 178, + "59": 7, + "6": 130, + "60": 34, + "62": 35, + "63": 83, + "64": 34, + "65": 33, + "66": 36, + "67": 83, + "68": 34, + "69": 66, + "7": 147, + "70": 37, + "71": 83, + "73": 4, + "74": 38, + "75": 7, + "77": 4, + "78": 167, + "79": 7, + "81": 5, + "82": 40, + "83": 7, + "84": 32, + "85": 198, + "86": 41, + "87": 83, + "88": 32, + "89": 231, + "9": 32, + "90": 42, + "91": 83, + "92": 33, + "93": 8, + "94": 43, + "95": 83, + "97": 160, + "98": 8, + "99": 147, + }, + registers: { + "f0,ft0": "0x4070000000000000", + "f10,fa0": "0x40b5640000000000", + "f12,fa2": "0xffffffffc6192400", + "f14,fa4": "0xffffffff46016400", + "f16,fa6": "0xffffffffc6100000", + "f18,fs2": "0xffffffff46192400", + "f2,ft2": "0xc0ab320000000000", + "f20,fs4": "0xffffffff46016400", + "f22,fs6": "0xffffffff46100000", + "f4,ft4": "0x40b5640000000000", + "f6,ft6": "0x4070000000000000", + "f8,fs0": "0x40ab320000000000", + "x10,a0": "0x200020", + "x17,a7": "0xa", + "x5,t0": "0x200000", + "x6,t1": "0x200008", + "x7,t2": "0x200010", + "x8,fp,s0": "0x200018", + "x9,s1": "0x20001c", + mtime: "0x1a", + pc: "0x68", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_062.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_062.s.snap new file mode 100644 index 000000000..6b01239b0 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_062.s.snap @@ -0,0 +1,134 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_062.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 32, + "10": 3, + "103": 115, + "11": 23, + "13": 3, + "14": 3, + "15": 19, + "17": 32, + "18": 3, + "19": 151, + "2": 2, + "2097152": 64, + "2097153": 112, + "2097160": 192, + "2097161": 171, + "2097162": 50, + "2097168": 64, + "2097169": 181, + "2097170": 100, + "2097176": 198, + "2097177": 25, + "2097178": 36, + "2097180": 70, + "2097181": 1, + "2097182": 100, + "2097184": 198, + "2097185": 16, + "21": 3, + "22": 131, + "23": 147, + "25": 32, + "26": 4, + "27": 23, + "29": 4, + "3": 151, + "30": 4, + "31": 19, + "33": 32, + "34": 4, + "35": 151, + "36": 255, + "37": 196, + "38": 132, + "39": 147, + "41": 32, + "42": 5, + "43": 23, + "44": 255, + "45": 133, + "46": 5, + "47": 19, + "49": 2, + "5": 2, + "50": 176, + "51": 7, + "53": 3, + "54": 49, + "55": 7, + "57": 3, + "58": 178, + "59": 7, + "6": 130, + "60": 34, + "62": 19, + "63": 83, + "64": 34, + "65": 33, + "66": 20, + "67": 83, + "68": 34, + "69": 66, + "7": 147, + "70": 21, + "71": 83, + "73": 4, + "74": 38, + "75": 7, + "77": 4, + "78": 167, + "79": 7, + "81": 5, + "82": 40, + "83": 7, + "84": 32, + "85": 198, + "86": 25, + "87": 83, + "88": 32, + "89": 231, + "9": 32, + "90": 26, + "91": 83, + "92": 33, + "93": 8, + "94": 27, + "95": 83, + "97": 160, + "98": 8, + "99": 147, + }, + registers: { + "f0,ft0": "0x4070000000000000", + "f10,fa0": "0xc0b5640000000000", + "f12,fa2": "0xffffffffc6192400", + "f14,fa4": "0xffffffff46016400", + "f16,fa6": "0xffffffffc6100000", + "f18,fs2": "0xffffffff46192400", + "f2,ft2": "0xc0ab320000000000", + "f20,fs4": "0xffffffffc6016400", + "f22,fs6": "0xffffffff46100000", + "f4,ft4": "0x40b5640000000000", + "f6,ft6": "0xc070000000000000", + "f8,fs0": "0x40ab320000000000", + "x10,a0": "0x200020", + "x17,a7": "0xa", + "x5,t0": "0x200000", + "x6,t1": "0x200008", + "x7,t2": "0x200010", + "x8,fp,s0": "0x200018", + "x9,s1": "0x20001c", + mtime: "0x1a", + pc: "0x68", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_063.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_063.s.snap new file mode 100644 index 000000000..269980e0d --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_063.s.snap @@ -0,0 +1,154 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_063.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 32, + "10": 3, + "100": 160, + "101": 231, + "102": 41, + "103": 83, + "104": 160, + "105": 230, + "106": 41, + "107": 211, + "108": 160, + "109": 199, + "11": 23, + "110": 42, + "111": 83, + "112": 161, + "113": 6, + "114": 42, + "115": 211, + "116": 161, + "117": 8, + "118": 43, + "119": 83, + "121": 160, + "122": 8, + "123": 147, + "127": 115, + "13": 3, + "14": 3, + "15": 19, + "17": 32, + "18": 3, + "19": 151, + "2": 2, + "2097152": 64, + "2097153": 112, + "2097160": 64, + "2097161": 171, + "2097162": 50, + "2097168": 127, + "2097169": 248, + "2097176": 70, + "2097177": 25, + "2097178": 36, + "2097180": 70, + "2097181": 36, + "2097182": 26, + "2097184": 127, + "2097185": 248, + "21": 3, + "22": 131, + "23": 147, + "25": 32, + "26": 4, + "27": 23, + "29": 4, + "3": 151, + "30": 4, + "31": 19, + "33": 32, + "34": 4, + "35": 151, + "36": 255, + "37": 196, + "38": 132, + "39": 147, + "41": 32, + "42": 5, + "43": 23, + "44": 255, + "45": 133, + "46": 5, + "47": 19, + "49": 2, + "5": 2, + "50": 176, + "51": 7, + "53": 3, + "54": 49, + "55": 7, + "57": 3, + "58": 178, + "59": 7, + "6": 130, + "60": 162, + "62": 37, + "63": 211, + "64": 162, + "65": 33, + "66": 38, + "67": 83, + "68": 162, + "69": 32, + "7": 147, + "70": 38, + "71": 211, + "72": 162, + "73": 1, + "74": 39, + "75": 83, + "76": 162, + "77": 64, + "78": 39, + "79": 211, + "80": 162, + "81": 66, + "82": 40, + "83": 83, + "85": 4, + "86": 38, + "87": 7, + "89": 4, + "9": 32, + "90": 167, + "91": 7, + "93": 5, + "94": 40, + "95": 7, + "96": 160, + "97": 198, + "98": 40, + "99": 211, + }, + registers: { + "f0,ft0": "0x4070000000000000", + "f12,fa2": "0xffffffff46192400", + "f14,fa4": "0xffffffff46241a00", + "f16,fa6": "0xffffffff7ff80000", + "f2,ft2": "0x40ab320000000000", + "f4,ft4": "0x7ff8000000000000", + "x10,a0": "0x200020", + "x11,a1": "0x1", + "x12,a2": "0x1", + "x17,a7": "0xa", + "x18,s2": "0x1", + "x5,t0": "0x200000", + "x6,t1": "0x200008", + "x7,t2": "0x200010", + "x8,fp,s0": "0x200018", + "x9,s1": "0x20001c", + mtime: "0x20", + pc: "0x80", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_064.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_064.s.snap new file mode 100644 index 000000000..f8458d62e --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_064.s.snap @@ -0,0 +1,156 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_064.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 32, + "10": 3, + "100": 160, + "101": 231, + "102": 9, + "103": 83, + "104": 160, + "105": 230, + "106": 9, + "107": 211, + "108": 160, + "109": 199, + "11": 23, + "110": 10, + "111": 83, + "112": 161, + "113": 6, + "114": 10, + "115": 211, + "116": 161, + "117": 8, + "118": 11, + "119": 83, + "121": 160, + "122": 8, + "123": 147, + "127": 115, + "13": 3, + "14": 3, + "15": 19, + "17": 32, + "18": 3, + "19": 151, + "2": 2, + "2097152": 64, + "2097153": 112, + "2097160": 64, + "2097161": 171, + "2097162": 50, + "2097168": 127, + "2097169": 248, + "2097176": 70, + "2097177": 25, + "2097178": 36, + "2097180": 70, + "2097181": 36, + "2097182": 26, + "2097184": 127, + "2097185": 248, + "21": 3, + "22": 131, + "23": 147, + "25": 32, + "26": 4, + "27": 23, + "29": 4, + "3": 151, + "30": 4, + "31": 19, + "33": 32, + "34": 4, + "35": 151, + "36": 255, + "37": 196, + "38": 132, + "39": 147, + "41": 32, + "42": 5, + "43": 23, + "44": 255, + "45": 133, + "46": 5, + "47": 19, + "49": 2, + "5": 2, + "50": 176, + "51": 7, + "53": 3, + "54": 49, + "55": 7, + "57": 3, + "58": 178, + "59": 7, + "6": 130, + "60": 162, + "62": 5, + "63": 211, + "64": 162, + "65": 33, + "66": 6, + "67": 83, + "68": 162, + "69": 32, + "7": 147, + "70": 6, + "71": 211, + "72": 162, + "73": 1, + "74": 7, + "75": 83, + "76": 162, + "77": 64, + "78": 7, + "79": 211, + "80": 162, + "81": 66, + "82": 8, + "83": 83, + "85": 4, + "86": 38, + "87": 7, + "89": 4, + "9": 32, + "90": 167, + "91": 7, + "93": 5, + "94": 40, + "95": 7, + "96": 160, + "97": 198, + "98": 8, + "99": 211, + }, + registers: { + "f0,ft0": "0x4070000000000000", + "f12,fa2": "0xffffffff46192400", + "f14,fa4": "0xffffffff46241a00", + "f16,fa6": "0xffffffff7ff80000", + "f2,ft2": "0x40ab320000000000", + "f4,ft4": "0x7ff8000000000000", + "x10,a0": "0x200020", + "x11,a1": "0x1", + "x12,a2": "0x1", + "x13,a3": "0x1", + "x17,a7": "0xa", + "x18,s2": "0x1", + "x19,s3": "0x1", + "x5,t0": "0x200000", + "x6,t1": "0x200008", + "x7,t2": "0x200010", + "x8,fp,s0": "0x200018", + "x9,s1": "0x20001c", + mtime: "0x20", + pc: "0x80", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_065.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_065.s.snap new file mode 100644 index 000000000..35580d2e7 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_065.s.snap @@ -0,0 +1,153 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_065.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 32, + "10": 3, + "100": 160, + "101": 231, + "102": 25, + "103": 83, + "104": 160, + "105": 230, + "106": 25, + "107": 211, + "108": 160, + "109": 199, + "11": 23, + "110": 26, + "111": 83, + "112": 161, + "113": 6, + "114": 26, + "115": 211, + "116": 161, + "117": 8, + "118": 27, + "119": 83, + "121": 160, + "122": 8, + "123": 147, + "127": 115, + "13": 3, + "14": 3, + "15": 19, + "17": 32, + "18": 3, + "19": 151, + "2": 2, + "2097152": 64, + "2097153": 112, + "2097160": 64, + "2097161": 171, + "2097162": 50, + "2097168": 127, + "2097169": 248, + "2097176": 70, + "2097177": 25, + "2097178": 36, + "2097180": 70, + "2097181": 36, + "2097182": 26, + "2097184": 127, + "2097185": 248, + "21": 3, + "22": 131, + "23": 147, + "25": 32, + "26": 4, + "27": 23, + "29": 4, + "3": 151, + "30": 4, + "31": 19, + "33": 32, + "34": 4, + "35": 151, + "36": 255, + "37": 196, + "38": 132, + "39": 147, + "41": 32, + "42": 5, + "43": 23, + "44": 255, + "45": 133, + "46": 5, + "47": 19, + "49": 2, + "5": 2, + "50": 176, + "51": 7, + "53": 3, + "54": 49, + "55": 7, + "57": 3, + "58": 178, + "59": 7, + "6": 130, + "60": 162, + "62": 21, + "63": 211, + "64": 162, + "65": 33, + "66": 22, + "67": 83, + "68": 162, + "69": 32, + "7": 147, + "70": 22, + "71": 211, + "72": 162, + "73": 1, + "74": 23, + "75": 83, + "76": 162, + "77": 64, + "78": 23, + "79": 211, + "80": 162, + "81": 66, + "82": 24, + "83": 83, + "85": 4, + "86": 38, + "87": 7, + "89": 4, + "9": 32, + "90": 167, + "91": 7, + "93": 5, + "94": 40, + "95": 7, + "96": 160, + "97": 198, + "98": 24, + "99": 211, + }, + registers: { + "f0,ft0": "0x4070000000000000", + "f12,fa2": "0xffffffff46192400", + "f14,fa4": "0xffffffff46241a00", + "f16,fa6": "0xffffffff7ff80000", + "f2,ft2": "0x40ab320000000000", + "f4,ft4": "0x7ff8000000000000", + "x10,a0": "0x200020", + "x13,a3": "0x1", + "x17,a7": "0xa", + "x19,s3": "0x1", + "x5,t0": "0x200000", + "x6,t1": "0x200008", + "x7,t2": "0x200010", + "x8,fp,s0": "0x200018", + "x9,s1": "0x20001c", + mtime: "0x20", + pc: "0x80", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_001.s.snap b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_001.s.snap new file mode 100644 index 000000000..a51178411 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_001.s.snap @@ -0,0 +1,56 @@ +export const snapshot = {}; + +snapshot[`riscv/sentinel/test_riscv_sentinels_001.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 80, + "10": 8, + "11": 147, + "15": 115, + "16": 255, + "17": 65, + "18": 1, + "19": 19, + "2": 5, + "21": 17, + "22": 36, + "23": 35, + "25": 129, + "26": 34, + "268435451": 8, + "27": 35, + "29": 65, + "3": 19, + "30": 4, + "31": 19, + "33": 32, + "34": 5, + "35": 19, + "37": 129, + "38": 32, + "39": 131, + "41": 65, + "42": 36, + "43": 3, + "45": 193, + "46": 1, + "47": 19, + "5": 192, + "50": 128, + "51": 103, + "7": 239, + "9": 160, + }, + registers: { + "x1,ra": "0x8", + "x10,a0": "0x2", + "x17,a7": "0xa", + mtime: "0xd", + pc: "0x10", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_002.s.snap b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_002.s.snap new file mode 100644 index 000000000..de8915b87 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_002.s.snap @@ -0,0 +1,56 @@ +export const snapshot = {}; + +snapshot[`riscv/sentinel/test_riscv_sentinels_002.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 80, + "10": 8, + "11": 147, + "15": 115, + "16": 255, + "17": 65, + "18": 1, + "19": 19, + "2": 5, + "21": 17, + "22": 36, + "23": 35, + "25": 129, + "26": 34, + "268435451": 8, + "27": 35, + "29": 65, + "3": 147, + "30": 4, + "31": 19, + "33": 32, + "34": 5, + "35": 147, + "37": 129, + "38": 32, + "39": 131, + "41": 65, + "42": 36, + "43": 3, + "45": 193, + "46": 1, + "47": 19, + "5": 192, + "50": 128, + "51": 103, + "7": 239, + "9": 160, + }, + registers: { + "x1,ra": "0x8", + "x11,a1": "0x2", + "x17,a7": "0xa", + mtime: "0xd", + pc: "0x10", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_003.s.snap b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_003.s.snap new file mode 100644 index 000000000..a5abb1645 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_003.s.snap @@ -0,0 +1,56 @@ +export const snapshot = {}; + +snapshot[`riscv/sentinel/test_riscv_sentinels_003.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 80, + "10": 8, + "11": 147, + "15": 115, + "16": 255, + "17": 65, + "18": 1, + "19": 19, + "2": 6, + "21": 17, + "22": 36, + "23": 35, + "25": 129, + "26": 34, + "268435451": 8, + "27": 35, + "29": 65, + "3": 19, + "30": 4, + "31": 19, + "33": 32, + "34": 6, + "35": 19, + "37": 129, + "38": 32, + "39": 131, + "41": 65, + "42": 36, + "43": 3, + "45": 193, + "46": 1, + "47": 19, + "5": 192, + "50": 128, + "51": 103, + "7": 239, + "9": 160, + }, + registers: { + "x1,ra": "0x8", + "x12,a2": "0x2", + "x17,a7": "0xa", + mtime: "0xd", + pc: "0x10", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_004.s.snap b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_004.s.snap new file mode 100644 index 000000000..61979074d --- /dev/null +++ b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_004.s.snap @@ -0,0 +1,56 @@ +export const snapshot = {}; + +snapshot[`riscv/sentinel/test_riscv_sentinels_004.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 80, + "10": 8, + "11": 147, + "15": 115, + "16": 255, + "17": 65, + "18": 1, + "19": 19, + "2": 6, + "21": 17, + "22": 36, + "23": 35, + "25": 129, + "26": 34, + "268435451": 8, + "27": 35, + "29": 65, + "3": 147, + "30": 4, + "31": 19, + "33": 32, + "34": 6, + "35": 147, + "37": 129, + "38": 32, + "39": 131, + "41": 65, + "42": 36, + "43": 3, + "45": 193, + "46": 1, + "47": 19, + "5": 192, + "50": 128, + "51": 103, + "7": 239, + "9": 160, + }, + registers: { + "x1,ra": "0x8", + "x13,a3": "0x2", + "x17,a7": "0xa", + mtime: "0xd", + pc: "0x10", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_005.s.snap b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_005.s.snap new file mode 100644 index 000000000..1e2e93131 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_005.s.snap @@ -0,0 +1,56 @@ +export const snapshot = {}; + +snapshot[`riscv/sentinel/test_riscv_sentinels_005.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 80, + "10": 8, + "11": 147, + "15": 115, + "16": 255, + "17": 65, + "18": 1, + "19": 19, + "2": 7, + "21": 17, + "22": 36, + "23": 35, + "25": 129, + "26": 34, + "268435451": 8, + "27": 35, + "29": 65, + "3": 19, + "30": 4, + "31": 19, + "33": 32, + "34": 7, + "35": 19, + "37": 129, + "38": 32, + "39": 131, + "41": 65, + "42": 36, + "43": 3, + "45": 193, + "46": 1, + "47": 19, + "5": 192, + "50": 128, + "51": 103, + "7": 239, + "9": 160, + }, + registers: { + "x1,ra": "0x8", + "x14,a4": "0x2", + "x17,a7": "0xa", + mtime: "0xd", + pc: "0x10", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_006.s.snap b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_006.s.snap new file mode 100644 index 000000000..ce30724f6 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_006.s.snap @@ -0,0 +1,56 @@ +export const snapshot = {}; + +snapshot[`riscv/sentinel/test_riscv_sentinels_006.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 80, + "10": 8, + "11": 147, + "15": 115, + "16": 255, + "17": 65, + "18": 1, + "19": 19, + "2": 7, + "21": 17, + "22": 36, + "23": 35, + "25": 129, + "26": 34, + "268435451": 8, + "27": 35, + "29": 65, + "3": 147, + "30": 4, + "31": 19, + "33": 32, + "34": 7, + "35": 147, + "37": 129, + "38": 32, + "39": 131, + "41": 65, + "42": 36, + "43": 3, + "45": 193, + "46": 1, + "47": 19, + "5": 192, + "50": 128, + "51": 103, + "7": 239, + "9": 160, + }, + registers: { + "x1,ra": "0x8", + "x15,a5": "0x2", + "x17,a7": "0xa", + mtime: "0xd", + pc: "0x10", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_007.s.snap b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_007.s.snap new file mode 100644 index 000000000..83c508aae --- /dev/null +++ b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_007.s.snap @@ -0,0 +1,56 @@ +export const snapshot = {}; + +snapshot[`riscv/sentinel/test_riscv_sentinels_007.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 80, + "10": 8, + "11": 147, + "15": 115, + "16": 255, + "17": 65, + "18": 1, + "19": 19, + "2": 8, + "21": 17, + "22": 36, + "23": 35, + "25": 129, + "26": 34, + "268435451": 8, + "27": 35, + "29": 65, + "3": 19, + "30": 4, + "31": 19, + "33": 32, + "34": 8, + "35": 19, + "37": 129, + "38": 32, + "39": 131, + "41": 65, + "42": 36, + "43": 3, + "45": 193, + "46": 1, + "47": 19, + "5": 192, + "50": 128, + "51": 103, + "7": 239, + "9": 160, + }, + registers: { + "x1,ra": "0x8", + "x16,a6": "0x2", + "x17,a7": "0xa", + mtime: "0xd", + pc: "0x10", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_008.s.snap b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_008.s.snap new file mode 100644 index 000000000..223e7e346 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_008.s.snap @@ -0,0 +1,55 @@ +export const snapshot = {}; + +snapshot[`riscv/sentinel/test_riscv_sentinels_008.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 80, + "10": 8, + "11": 147, + "15": 115, + "16": 255, + "17": 65, + "18": 1, + "19": 19, + "2": 8, + "21": 17, + "22": 36, + "23": 35, + "25": 129, + "26": 34, + "268435451": 8, + "27": 35, + "29": 65, + "3": 147, + "30": 4, + "31": 19, + "33": 32, + "34": 8, + "35": 147, + "37": 129, + "38": 32, + "39": 131, + "41": 65, + "42": 36, + "43": 3, + "45": 193, + "46": 1, + "47": 19, + "5": 192, + "50": 128, + "51": 103, + "7": 239, + "9": 160, + }, + registers: { + "x1,ra": "0x8", + "x17,a7": "0xa", + mtime: "0xd", + pc: "0x10", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_009.s.snap b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_009.s.snap new file mode 100644 index 000000000..502cbdb59 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_009.s.snap @@ -0,0 +1,60 @@ +export const snapshot = {}; + +snapshot[`riscv/sentinel/test_riscv_sentinels_009.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 16, + "11": 239, + "13": 160, + "14": 8, + "15": 147, + "19": 115, + "2": 2, + "20": 255, + "21": 65, + "22": 1, + "23": 19, + "25": 17, + "26": 36, + "268435451": 12, + "27": 35, + "29": 129, + "3": 147, + "30": 34, + "31": 35, + "33": 65, + "34": 4, + "35": 19, + "37": 32, + "38": 2, + "39": 147, + "41": 129, + "42": 32, + "43": 131, + "45": 65, + "46": 36, + "47": 3, + "49": 193, + "5": 80, + "50": 1, + "51": 19, + "54": 128, + "55": 103, + "6": 5, + "7": 19, + "9": 192, + }, + registers: { + "x1,ra": "0xc", + "x10,a0": "0x5", + "x17,a7": "0xa", + "x5,t0": "0x2", + mtime: "0xe", + pc: "0x14", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_010.s.snap b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_010.s.snap new file mode 100644 index 000000000..2806b4ce4 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_010.s.snap @@ -0,0 +1,60 @@ +export const snapshot = {}; + +snapshot[`riscv/sentinel/test_riscv_sentinels_010.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 16, + "11": 239, + "13": 160, + "14": 8, + "15": 147, + "19": 115, + "2": 3, + "20": 255, + "21": 65, + "22": 1, + "23": 19, + "25": 17, + "26": 36, + "268435451": 12, + "27": 35, + "29": 129, + "3": 19, + "30": 34, + "31": 35, + "33": 65, + "34": 4, + "35": 19, + "37": 32, + "38": 3, + "39": 19, + "41": 129, + "42": 32, + "43": 131, + "45": 65, + "46": 36, + "47": 3, + "49": 193, + "5": 80, + "50": 1, + "51": 19, + "54": 128, + "55": 103, + "6": 5, + "7": 19, + "9": 192, + }, + registers: { + "x1,ra": "0xc", + "x10,a0": "0x5", + "x17,a7": "0xa", + "x6,t1": "0x2", + mtime: "0xe", + pc: "0x14", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_011.s.snap b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_011.s.snap new file mode 100644 index 000000000..3ac9b2736 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_011.s.snap @@ -0,0 +1,60 @@ +export const snapshot = {}; + +snapshot[`riscv/sentinel/test_riscv_sentinels_011.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 16, + "11": 239, + "13": 160, + "14": 8, + "15": 147, + "19": 115, + "2": 3, + "20": 255, + "21": 65, + "22": 1, + "23": 19, + "25": 17, + "26": 36, + "268435451": 12, + "27": 35, + "29": 129, + "3": 147, + "30": 34, + "31": 35, + "33": 65, + "34": 4, + "35": 19, + "37": 32, + "38": 3, + "39": 147, + "41": 129, + "42": 32, + "43": 131, + "45": 65, + "46": 36, + "47": 3, + "49": 193, + "5": 80, + "50": 1, + "51": 19, + "54": 128, + "55": 103, + "6": 5, + "7": 19, + "9": 192, + }, + registers: { + "x1,ra": "0xc", + "x10,a0": "0x5", + "x17,a7": "0xa", + "x7,t2": "0x2", + mtime: "0xe", + pc: "0x14", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_012.s.snap b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_012.s.snap new file mode 100644 index 000000000..88cbfc8bc --- /dev/null +++ b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_012.s.snap @@ -0,0 +1,60 @@ +export const snapshot = {}; + +snapshot[`riscv/sentinel/test_riscv_sentinels_012.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 16, + "11": 239, + "13": 160, + "14": 8, + "15": 147, + "19": 115, + "2": 14, + "20": 255, + "21": 65, + "22": 1, + "23": 19, + "25": 17, + "26": 36, + "268435451": 12, + "27": 35, + "29": 129, + "3": 19, + "30": 34, + "31": 35, + "33": 65, + "34": 4, + "35": 19, + "37": 32, + "38": 14, + "39": 19, + "41": 129, + "42": 32, + "43": 131, + "45": 65, + "46": 36, + "47": 3, + "49": 193, + "5": 80, + "50": 1, + "51": 19, + "54": 128, + "55": 103, + "6": 5, + "7": 19, + "9": 192, + }, + registers: { + "x1,ra": "0xc", + "x10,a0": "0x5", + "x17,a7": "0xa", + "x28,t3": "0x2", + mtime: "0xe", + pc: "0x14", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_013.s.snap b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_013.s.snap new file mode 100644 index 000000000..25c25a0b6 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_013.s.snap @@ -0,0 +1,60 @@ +export const snapshot = {}; + +snapshot[`riscv/sentinel/test_riscv_sentinels_013.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 16, + "11": 239, + "13": 160, + "14": 8, + "15": 147, + "19": 115, + "2": 14, + "20": 255, + "21": 65, + "22": 1, + "23": 19, + "25": 17, + "26": 36, + "268435451": 12, + "27": 35, + "29": 129, + "3": 147, + "30": 34, + "31": 35, + "33": 65, + "34": 4, + "35": 19, + "37": 32, + "38": 14, + "39": 147, + "41": 129, + "42": 32, + "43": 131, + "45": 65, + "46": 36, + "47": 3, + "49": 193, + "5": 80, + "50": 1, + "51": 19, + "54": 128, + "55": 103, + "6": 5, + "7": 19, + "9": 192, + }, + registers: { + "x1,ra": "0xc", + "x10,a0": "0x5", + "x17,a7": "0xa", + "x29,t4": "0x2", + mtime: "0xe", + pc: "0x14", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_014.s.snap b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_014.s.snap new file mode 100644 index 000000000..11c71c924 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_014.s.snap @@ -0,0 +1,60 @@ +export const snapshot = {}; + +snapshot[`riscv/sentinel/test_riscv_sentinels_014.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 16, + "11": 239, + "13": 160, + "14": 8, + "15": 147, + "19": 115, + "2": 15, + "20": 255, + "21": 65, + "22": 1, + "23": 19, + "25": 17, + "26": 36, + "268435451": 12, + "27": 35, + "29": 129, + "3": 19, + "30": 34, + "31": 35, + "33": 65, + "34": 4, + "35": 19, + "37": 32, + "38": 15, + "39": 19, + "41": 129, + "42": 32, + "43": 131, + "45": 65, + "46": 36, + "47": 3, + "49": 193, + "5": 80, + "50": 1, + "51": 19, + "54": 128, + "55": 103, + "6": 5, + "7": 19, + "9": 192, + }, + registers: { + "x1,ra": "0xc", + "x10,a0": "0x5", + "x17,a7": "0xa", + "x30,t5": "0x2", + mtime: "0xe", + pc: "0x14", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_015.s.snap b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_015.s.snap new file mode 100644 index 000000000..14c8b1c0d --- /dev/null +++ b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_015.s.snap @@ -0,0 +1,60 @@ +export const snapshot = {}; + +snapshot[`riscv/sentinel/test_riscv_sentinels_015.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 16, + "11": 239, + "13": 160, + "14": 8, + "15": 147, + "19": 115, + "2": 15, + "20": 255, + "21": 65, + "22": 1, + "23": 19, + "25": 17, + "26": 36, + "268435451": 12, + "27": 35, + "29": 129, + "3": 147, + "30": 34, + "31": 35, + "33": 65, + "34": 4, + "35": 19, + "37": 32, + "38": 15, + "39": 147, + "41": 129, + "42": 32, + "43": 131, + "45": 65, + "46": 36, + "47": 3, + "49": 193, + "5": 80, + "50": 1, + "51": 19, + "54": 128, + "55": 103, + "6": 5, + "7": 19, + "9": 192, + }, + registers: { + "x1,ra": "0xc", + "x10,a0": "0x5", + "x17,a7": "0xa", + "x31,t6": "0x2", + mtime: "0xe", + pc: "0x14", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_016.s.snap b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_016.s.snap new file mode 100644 index 000000000..7446e0332 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_016.s.snap @@ -0,0 +1,57 @@ +export const snapshot = {}; + +snapshot[`riscv/sentinel/test_riscv_sentinels_016.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 80, + "10": 8, + "11": 147, + "15": 115, + "16": 255, + "17": 65, + "18": 1, + "19": 19, + "2": 4, + "21": 17, + "22": 36, + "23": 35, + "25": 129, + "26": 34, + "268435447": 5, + "268435451": 8, + "27": 35, + "29": 65, + "3": 19, + "30": 4, + "31": 19, + "33": 32, + "34": 4, + "35": 19, + "37": 129, + "38": 32, + "39": 131, + "41": 65, + "42": 36, + "43": 3, + "45": 193, + "46": 1, + "47": 19, + "5": 192, + "50": 128, + "51": 103, + "7": 239, + "9": 160, + }, + registers: { + "x1,ra": "0x8", + "x17,a7": "0xa", + "x8,fp,s0": "0x5", + mtime: "0xd", + pc: "0x10", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_017.s.snap b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_017.s.snap new file mode 100644 index 000000000..56b94e6e1 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_017.s.snap @@ -0,0 +1,63 @@ +export const snapshot = {}; + +snapshot[`riscv/sentinel/test_riscv_sentinels_017.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 80, + "10": 8, + "11": 147, + "15": 115, + "16": 255, + "17": 65, + "18": 1, + "19": 19, + "2": 4, + "21": 17, + "22": 36, + "23": 35, + "25": 129, + "26": 34, + "268435451": 8, + "27": 35, + "29": 65, + "3": 147, + "30": 4, + "31": 19, + "33": 32, + "34": 4, + "35": 147, + "37": 129, + "38": 32, + "39": 131, + "41": 65, + "42": 36, + "43": 3, + "45": 193, + "46": 1, + "47": 19, + "5": 192, + "50": 128, + "51": 103, + "7": 239, + "9": 160, + }, + registers: { + "x1,ra": "0x8", + "x17,a7": "0xa", + "x9,s1": "0x2", + mtime: "0xd", + pc: "0x10", + }, + sentinel_errors: [ + { + function: "test", + msg: "Calling convention violations in test: + - Register x9,s1 was used but never saved to memory + - Register x9,s1 value changed but not properly restored", + }, + ], +} +`; diff --git a/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_018.s.snap b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_018.s.snap new file mode 100644 index 000000000..a751d2d17 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_018.s.snap @@ -0,0 +1,63 @@ +export const snapshot = {}; + +snapshot[`riscv/sentinel/test_riscv_sentinels_018.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 80, + "10": 8, + "11": 147, + "15": 115, + "16": 255, + "17": 65, + "18": 1, + "19": 19, + "2": 9, + "21": 17, + "22": 36, + "23": 35, + "25": 129, + "26": 34, + "268435451": 8, + "27": 35, + "29": 65, + "3": 19, + "30": 4, + "31": 19, + "33": 32, + "34": 9, + "35": 19, + "37": 129, + "38": 32, + "39": 131, + "41": 65, + "42": 36, + "43": 3, + "45": 193, + "46": 1, + "47": 19, + "5": 192, + "50": 128, + "51": 103, + "7": 239, + "9": 160, + }, + registers: { + "x1,ra": "0x8", + "x17,a7": "0xa", + "x18,s2": "0x2", + mtime: "0xd", + pc: "0x10", + }, + sentinel_errors: [ + { + function: "test", + msg: "Calling convention violations in test: + - Register x18,s2 was used but never saved to memory + - Register x18,s2 value changed but not properly restored", + }, + ], +} +`; diff --git a/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_019.s.snap b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_019.s.snap new file mode 100644 index 000000000..160371a48 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_019.s.snap @@ -0,0 +1,63 @@ +export const snapshot = {}; + +snapshot[`riscv/sentinel/test_riscv_sentinels_019.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 80, + "10": 8, + "11": 147, + "15": 115, + "16": 255, + "17": 65, + "18": 1, + "19": 19, + "2": 9, + "21": 17, + "22": 36, + "23": 35, + "25": 129, + "26": 34, + "268435451": 8, + "27": 35, + "29": 65, + "3": 147, + "30": 4, + "31": 19, + "33": 32, + "34": 9, + "35": 147, + "37": 129, + "38": 32, + "39": 131, + "41": 65, + "42": 36, + "43": 3, + "45": 193, + "46": 1, + "47": 19, + "5": 192, + "50": 128, + "51": 103, + "7": 239, + "9": 160, + }, + registers: { + "x1,ra": "0x8", + "x17,a7": "0xa", + "x19,s3": "0x2", + mtime: "0xd", + pc: "0x10", + }, + sentinel_errors: [ + { + function: "test", + msg: "Calling convention violations in test: + - Register x19,s3 was used but never saved to memory + - Register x19,s3 value changed but not properly restored", + }, + ], +} +`; diff --git a/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_020.s.snap b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_020.s.snap new file mode 100644 index 000000000..be3f0ccac --- /dev/null +++ b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_020.s.snap @@ -0,0 +1,63 @@ +export const snapshot = {}; + +snapshot[`riscv/sentinel/test_riscv_sentinels_020.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 80, + "10": 8, + "11": 147, + "15": 115, + "16": 255, + "17": 65, + "18": 1, + "19": 19, + "2": 10, + "21": 17, + "22": 36, + "23": 35, + "25": 129, + "26": 34, + "268435451": 8, + "27": 35, + "29": 65, + "3": 19, + "30": 4, + "31": 19, + "33": 32, + "34": 10, + "35": 19, + "37": 129, + "38": 32, + "39": 131, + "41": 65, + "42": 36, + "43": 3, + "45": 193, + "46": 1, + "47": 19, + "5": 192, + "50": 128, + "51": 103, + "7": 239, + "9": 160, + }, + registers: { + "x1,ra": "0x8", + "x17,a7": "0xa", + "x20,s4": "0x2", + mtime: "0xd", + pc: "0x10", + }, + sentinel_errors: [ + { + function: "test", + msg: "Calling convention violations in test: + - Register x20,s4 was used but never saved to memory + - Register x20,s4 value changed but not properly restored", + }, + ], +} +`; diff --git a/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_021.s.snap b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_021.s.snap new file mode 100644 index 000000000..fd1213c7d --- /dev/null +++ b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_021.s.snap @@ -0,0 +1,63 @@ +export const snapshot = {}; + +snapshot[`riscv/sentinel/test_riscv_sentinels_021.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 80, + "10": 8, + "11": 147, + "15": 115, + "16": 255, + "17": 65, + "18": 1, + "19": 19, + "2": 10, + "21": 17, + "22": 36, + "23": 35, + "25": 129, + "26": 34, + "268435451": 8, + "27": 35, + "29": 65, + "3": 147, + "30": 4, + "31": 19, + "33": 32, + "34": 10, + "35": 147, + "37": 129, + "38": 32, + "39": 131, + "41": 65, + "42": 36, + "43": 3, + "45": 193, + "46": 1, + "47": 19, + "5": 192, + "50": 128, + "51": 103, + "7": 239, + "9": 160, + }, + registers: { + "x1,ra": "0x8", + "x17,a7": "0xa", + "x21,s5": "0x2", + mtime: "0xd", + pc: "0x10", + }, + sentinel_errors: [ + { + function: "test", + msg: "Calling convention violations in test: + - Register x21,s5 was used but never saved to memory + - Register x21,s5 value changed but not properly restored", + }, + ], +} +`; diff --git a/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_022.s.snap b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_022.s.snap new file mode 100644 index 000000000..3b4cd43a1 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_022.s.snap @@ -0,0 +1,63 @@ +export const snapshot = {}; + +snapshot[`riscv/sentinel/test_riscv_sentinels_022.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 80, + "10": 8, + "11": 147, + "15": 115, + "16": 255, + "17": 65, + "18": 1, + "19": 19, + "2": 11, + "21": 17, + "22": 36, + "23": 35, + "25": 129, + "26": 34, + "268435451": 8, + "27": 35, + "29": 65, + "3": 19, + "30": 4, + "31": 19, + "33": 32, + "34": 11, + "35": 19, + "37": 129, + "38": 32, + "39": 131, + "41": 65, + "42": 36, + "43": 3, + "45": 193, + "46": 1, + "47": 19, + "5": 192, + "50": 128, + "51": 103, + "7": 239, + "9": 160, + }, + registers: { + "x1,ra": "0x8", + "x17,a7": "0xa", + "x22,s6": "0x2", + mtime: "0xd", + pc: "0x10", + }, + sentinel_errors: [ + { + function: "test", + msg: "Calling convention violations in test: + - Register x22,s6 was used but never saved to memory + - Register x22,s6 value changed but not properly restored", + }, + ], +} +`; diff --git a/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_023.s.snap b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_023.s.snap new file mode 100644 index 000000000..6d1bf8296 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_023.s.snap @@ -0,0 +1,63 @@ +export const snapshot = {}; + +snapshot[`riscv/sentinel/test_riscv_sentinels_023.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 80, + "10": 8, + "11": 147, + "15": 115, + "16": 255, + "17": 65, + "18": 1, + "19": 19, + "2": 11, + "21": 17, + "22": 36, + "23": 35, + "25": 129, + "26": 34, + "268435451": 8, + "27": 35, + "29": 65, + "3": 147, + "30": 4, + "31": 19, + "33": 32, + "34": 11, + "35": 147, + "37": 129, + "38": 32, + "39": 131, + "41": 65, + "42": 36, + "43": 3, + "45": 193, + "46": 1, + "47": 19, + "5": 192, + "50": 128, + "51": 103, + "7": 239, + "9": 160, + }, + registers: { + "x1,ra": "0x8", + "x17,a7": "0xa", + "x23,s7": "0x2", + mtime: "0xd", + pc: "0x10", + }, + sentinel_errors: [ + { + function: "test", + msg: "Calling convention violations in test: + - Register x23,s7 was used but never saved to memory + - Register x23,s7 value changed but not properly restored", + }, + ], +} +`; diff --git a/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_024.s.snap b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_024.s.snap new file mode 100644 index 000000000..0603d2c62 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_024.s.snap @@ -0,0 +1,63 @@ +export const snapshot = {}; + +snapshot[`riscv/sentinel/test_riscv_sentinels_024.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 80, + "10": 8, + "11": 147, + "15": 115, + "16": 255, + "17": 65, + "18": 1, + "19": 19, + "2": 12, + "21": 17, + "22": 36, + "23": 35, + "25": 129, + "26": 34, + "268435451": 8, + "27": 35, + "29": 65, + "3": 19, + "30": 4, + "31": 19, + "33": 32, + "34": 12, + "35": 19, + "37": 129, + "38": 32, + "39": 131, + "41": 65, + "42": 36, + "43": 3, + "45": 193, + "46": 1, + "47": 19, + "5": 192, + "50": 128, + "51": 103, + "7": 239, + "9": 160, + }, + registers: { + "x1,ra": "0x8", + "x17,a7": "0xa", + "x24,s8": "0x2", + mtime: "0xd", + pc: "0x10", + }, + sentinel_errors: [ + { + function: "test", + msg: "Calling convention violations in test: + - Register x24,s8 was used but never saved to memory + - Register x24,s8 value changed but not properly restored", + }, + ], +} +`; diff --git a/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_025.s.snap b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_025.s.snap new file mode 100644 index 000000000..fd1a35565 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_025.s.snap @@ -0,0 +1,63 @@ +export const snapshot = {}; + +snapshot[`riscv/sentinel/test_riscv_sentinels_025.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 80, + "10": 8, + "11": 147, + "15": 115, + "16": 255, + "17": 65, + "18": 1, + "19": 19, + "2": 12, + "21": 17, + "22": 36, + "23": 35, + "25": 129, + "26": 34, + "268435451": 8, + "27": 35, + "29": 65, + "3": 147, + "30": 4, + "31": 19, + "33": 32, + "34": 12, + "35": 147, + "37": 129, + "38": 32, + "39": 131, + "41": 65, + "42": 36, + "43": 3, + "45": 193, + "46": 1, + "47": 19, + "5": 192, + "50": 128, + "51": 103, + "7": 239, + "9": 160, + }, + registers: { + "x1,ra": "0x8", + "x17,a7": "0xa", + "x25,s9": "0x2", + mtime: "0xd", + pc: "0x10", + }, + sentinel_errors: [ + { + function: "test", + msg: "Calling convention violations in test: + - Register x25,s9 was used but never saved to memory + - Register x25,s9 value changed but not properly restored", + }, + ], +} +`; diff --git a/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_026.s.snap b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_026.s.snap new file mode 100644 index 000000000..93fb738b8 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_026.s.snap @@ -0,0 +1,63 @@ +export const snapshot = {}; + +snapshot[`riscv/sentinel/test_riscv_sentinels_026.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 80, + "10": 8, + "11": 147, + "15": 115, + "16": 255, + "17": 65, + "18": 1, + "19": 19, + "2": 13, + "21": 17, + "22": 36, + "23": 35, + "25": 129, + "26": 34, + "268435451": 8, + "27": 35, + "29": 65, + "3": 19, + "30": 4, + "31": 19, + "33": 32, + "34": 13, + "35": 19, + "37": 129, + "38": 32, + "39": 131, + "41": 65, + "42": 36, + "43": 3, + "45": 193, + "46": 1, + "47": 19, + "5": 192, + "50": 128, + "51": 103, + "7": 239, + "9": 160, + }, + registers: { + "x1,ra": "0x8", + "x17,a7": "0xa", + "x26,s10": "0x2", + mtime: "0xd", + pc: "0x10", + }, + sentinel_errors: [ + { + function: "test", + msg: "Calling convention violations in test: + - Register x26,s10 was used but never saved to memory + - Register x26,s10 value changed but not properly restored", + }, + ], +} +`; diff --git a/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_027.s.snap b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_027.s.snap new file mode 100644 index 000000000..8e0dce267 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_027.s.snap @@ -0,0 +1,63 @@ +export const snapshot = {}; + +snapshot[`riscv/sentinel/test_riscv_sentinels_027.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 80, + "10": 8, + "11": 147, + "15": 115, + "16": 255, + "17": 65, + "18": 1, + "19": 19, + "2": 13, + "21": 17, + "22": 36, + "23": 35, + "25": 129, + "26": 34, + "268435451": 8, + "27": 35, + "29": 65, + "3": 147, + "30": 4, + "31": 19, + "33": 32, + "34": 13, + "35": 147, + "37": 129, + "38": 32, + "39": 131, + "41": 65, + "42": 36, + "43": 3, + "45": 193, + "46": 1, + "47": 19, + "5": 192, + "50": 128, + "51": 103, + "7": 239, + "9": 160, + }, + registers: { + "x1,ra": "0x8", + "x17,a7": "0xa", + "x27,s11": "0x2", + mtime: "0xd", + pc: "0x10", + }, + sentinel_errors: [ + { + function: "test", + msg: "Calling convention violations in test: + - Register x27,s11 was used but never saved to memory + - Register x27,s11 value changed but not properly restored", + }, + ], +} +`; diff --git a/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_028.s.snap b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_028.s.snap new file mode 100644 index 000000000..c1f6c2cee --- /dev/null +++ b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_028.s.snap @@ -0,0 +1,33 @@ +export const snapshot = {}; + +snapshot[`riscv/sentinel/test_riscv_sentinels_028.s 1`] = ` +{ + display: "", + error: "Error decoding instruction: Illegal Instruction: 0x00000000", + keyboard: "", + memory: { + "1": 80, + "10": 8, + "11": 147, + "15": 115, + "18": 16, + "19": 183, + "20": 8, + "21": 160, + "22": 128, + "23": 147, + "26": 128, + "27": 103, + "3": 147, + "5": 192, + "7": 239, + "9": 160, + }, + registers: { + "x1,ra": "0x108a", + mtime: "0x5", + pc: "0x108a", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_029.s.snap b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_029.s.snap new file mode 100644 index 000000000..0e6984b32 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_029.s.snap @@ -0,0 +1,37 @@ +export const snapshot = {}; + +snapshot[`riscv/sentinel/test_riscv_sentinels_029.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 192, + "11": 115, + "12": 255, + "13": 193, + "14": 1, + "15": 19, + "18": 128, + "19": 103, + "3": 239, + "5": 160, + "6": 8, + "7": 147, + }, + registers: { + "x1,ra": "0x4", + "x17,a7": "0xa", + "x2,sp": "0xffffff8", + mtime: "0x5", + pc: "0xc", + }, + sentinel_errors: [ + { + function: "test", + msg: "Calling convention violations in test: + - Stack pointer not restored: entered at 0xffffffc, exited at 0xffffff8", + }, + ], +} +`; diff --git a/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_030.s.snap b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_030.s.snap new file mode 100644 index 000000000..e287dd757 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_030.s.snap @@ -0,0 +1,33 @@ +export const snapshot = {}; + +snapshot[`riscv/sentinel/test_riscv_sentinels_030.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 80, + "10": 8, + "11": 147, + "15": 115, + "17": 80, + "18": 1, + "19": 147, + "2": 1, + "22": 128, + "23": 103, + "3": 147, + "5": 192, + "7": 239, + "9": 160, + }, + registers: { + "x1,ra": "0x8", + "x17,a7": "0xa", + "x3,gp": "0x5", + mtime: "0x6", + pc: "0x10", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_031.s.snap b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_031.s.snap new file mode 100644 index 000000000..f4aeb993e --- /dev/null +++ b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_031.s.snap @@ -0,0 +1,33 @@ +export const snapshot = {}; + +snapshot[`riscv/sentinel/test_riscv_sentinels_031.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 80, + "10": 8, + "11": 147, + "15": 115, + "17": 80, + "18": 2, + "19": 19, + "2": 2, + "22": 128, + "23": 103, + "3": 19, + "5": 192, + "7": 239, + "9": 160, + }, + registers: { + "x1,ra": "0x8", + "x17,a7": "0xa", + "x4,tp": "0x5", + mtime: "0x6", + pc: "0x10", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_032.s.snap b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_032.s.snap new file mode 100644 index 000000000..d6692847f --- /dev/null +++ b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_032.s.snap @@ -0,0 +1,47 @@ +export const snapshot = {}; + +snapshot[`riscv/sentinel/test_riscv_sentinels_032.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 32, + "10": 8, + "11": 147, + "15": 115, + "16": 255, + "17": 129, + "18": 1, + "19": 19, + "2": 4, + "21": 145, + "22": 32, + "23": 35, + "25": 32, + "26": 4, + "268435447": 2, + "27": 147, + "29": 1, + "3": 147, + "30": 36, + "31": 131, + "33": 129, + "34": 1, + "35": 19, + "38": 128, + "39": 103, + "5": 192, + "7": 239, + "9": 160, + }, + registers: { + "x1,ra": "0x8", + "x17,a7": "0xa", + "x9,s1": "0x2", + mtime: "0xa", + pc: "0x10", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_033.s.snap b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_033.s.snap new file mode 100644 index 000000000..d06a910d9 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_033.s.snap @@ -0,0 +1,50 @@ +export const snapshot = {}; + +snapshot[`riscv/sentinel/test_riscv_sentinels_033.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 80, + "10": 8, + "11": 147, + "15": 115, + "16": 255, + "17": 193, + "18": 1, + "19": 19, + "2": 4, + "21": 145, + "22": 32, + "23": 35, + "25": 80, + "26": 4, + "268435451": 5, + "27": 147, + "29": 65, + "3": 147, + "30": 1, + "31": 19, + "34": 128, + "35": 103, + "5": 192, + "7": 239, + "9": 160, + }, + registers: { + "x1,ra": "0x8", + "x17,a7": "0xa", + "x9,s1": "0x5", + mtime: "0x9", + pc: "0x10", + }, + sentinel_errors: [ + { + function: "test", + msg: "Calling convention violations in test: + - Register x9,s1 was saved but never restored", + }, + ], +} +`; diff --git a/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_034.s.snap b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_034.s.snap new file mode 100644 index 000000000..1633d70d9 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_034.s.snap @@ -0,0 +1,53 @@ +export const snapshot = {}; + +snapshot[`riscv/sentinel/test_riscv_sentinels_034.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 32, + "10": 8, + "11": 147, + "15": 115, + "16": 255, + "17": 129, + "18": 1, + "19": 19, + "2": 4, + "21": 145, + "22": 32, + "23": 35, + "25": 32, + "26": 4, + "268435447": 2, + "27": 147, + "29": 65, + "3": 147, + "30": 36, + "31": 131, + "33": 129, + "34": 1, + "35": 19, + "38": 128, + "39": 103, + "5": 192, + "7": 239, + "9": 160, + }, + registers: { + "x1,ra": "0x8", + "x17,a7": "0xa", + mtime: "0xa", + pc: "0x10", + }, + sentinel_errors: [ + { + function: "test", + msg: "Calling convention violations in test: + - Register x9,s1 saved at 0xffffff4 but restored from 0xffffff8 + - Register x9,s1 value changed but not properly restored", + }, + ], +} +`; diff --git a/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_035.s.snap b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_035.s.snap new file mode 100644 index 000000000..b7d7f189e --- /dev/null +++ b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_035.s.snap @@ -0,0 +1,53 @@ +export const snapshot = {}; + +snapshot[`riscv/sentinel/test_riscv_sentinels_035.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 32, + "10": 8, + "11": 147, + "15": 115, + "16": 255, + "17": 129, + "18": 1, + "19": 19, + "2": 4, + "21": 145, + "22": 32, + "23": 35, + "25": 32, + "26": 4, + "268435447": 2, + "27": 147, + "29": 1, + "3": 147, + "30": 20, + "31": 131, + "33": 129, + "34": 1, + "35": 19, + "38": 128, + "39": 103, + "5": 192, + "7": 239, + "9": 160, + }, + registers: { + "x1,ra": "0x8", + "x17,a7": "0xa", + mtime: "0xa", + pc: "0x10", + }, + sentinel_errors: [ + { + function: "test", + msg: "Calling convention violations in test: + - Register x9,s1 saved with 4 bytes but restored with 2 bytes + - Register x9,s1 value changed but not properly restored", + }, + ], +} +`; diff --git a/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_036.s.snap b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_036.s.snap new file mode 100644 index 000000000..082ae9517 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_036.s.snap @@ -0,0 +1,54 @@ +export const snapshot = {}; + +snapshot[`riscv/sentinel/test_riscv_sentinels_036.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 32, + "10": 8, + "11": 147, + "15": 115, + "16": 255, + "17": 129, + "18": 1, + "19": 19, + "2": 4, + "21": 145, + "22": 32, + "23": 35, + "25": 81, + "26": 32, + "27": 35, + "29": 32, + "3": 147, + "30": 4, + "31": 147, + "33": 1, + "34": 36, + "35": 131, + "37": 129, + "38": 1, + "39": 19, + "42": 128, + "43": 103, + "5": 192, + "7": 239, + "9": 160, + }, + registers: { + "x1,ra": "0x8", + "x17,a7": "0xa", + mtime: "0xb", + pc: "0x10", + }, + sentinel_errors: [ + { + function: "test", + msg: "Calling convention violations in test: + - Register x9,s1 value changed but not properly restored", + }, + ], +} +`; diff --git a/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_037.s.snap b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_037.s.snap new file mode 100644 index 000000000..485d2b9c2 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/sentinel/test_riscv_sentinels_037.s.snap @@ -0,0 +1,120 @@ +export const snapshot = {}; + +snapshot[`riscv/sentinel/test_riscv_sentinels_037.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 6, + "1": 64, + "10": 9, + "11": 147, + "12": 2, + "13": 160, + "14": 10, + "15": 19, + "16": 5, + "17": 64, + "18": 10, + "19": 147, + "2": 4, + "20": 1, + "21": 64, + "23": 239, + "24": 1, + "25": 36, + "26": 130, + "268435451": 24, + "27": 179, + "28": 1, + "29": 73, + "3": 147, + "30": 131, + "31": 51, + "33": 160, + "34": 8, + "35": 147, + "39": 115, + "4": 12, + "40": 255, + "41": 65, + "42": 1, + "43": 19, + "45": 17, + "46": 36, + "47": 35, + "49": 129, + "5": 128, + "50": 34, + "51": 35, + "53": 65, + "54": 4, + "55": 19, + "56": 62, + "57": 112, + "58": 4, + "59": 147, + "6": 9, + "60": 55, + "61": 128, + "62": 9, + "63": 19, + "64": 48, + "65": 144, + "66": 9, + "67": 147, + "68": 1, + "69": 90, + "7": 19, + "70": 4, + "71": 179, + "72": 34, + "73": 176, + "74": 4, + "75": 147, + "76": 27, + "77": 192, + "78": 9, + "79": 19, + "8": 18, + "81": 129, + "82": 32, + "83": 131, + "85": 65, + "86": 36, + "87": 3, + "89": 193, + "9": 192, + "90": 1, + "91": 19, + "94": 128, + "95": 103, + }, + registers: { + "x1,ra": "0x18", + "x17,a7": "0xa", + "x18,s2": "0x1bc", + "x19,s3": "0x309", + "x20,s4": "0x2a", + "x21,s5": "0x54", + "x5,t0": "0x3e7", + "x6,t1": "0x333", + "x9,s1": "0x22b", + mtime: "0x18", + pc: "0x28", + }, + sentinel_errors: [ + { + function: "bad_function", + msg: "Calling convention violations in bad_function: + - Register x9,s1 was used but never saved to memory + - Register x9,s1 value changed but not properly restored + - Register x18,s2 was used but never saved to memory + - Register x18,s2 value changed but not properly restored + - Register x19,s3 was used but never saved to memory + - Register x19,s3 value changed but not properly restored", + }, + ], +} +`; diff --git a/tests/arch/mips/correct/examples/test_mips_example_001.out b/tests/arch/mips/correct/examples/test_mips_example_001.out deleted file mode 100644 index b48eb7374..000000000 --- a/tests/arch/mips/correct/examples/test_mips_example_001.out +++ /dev/null @@ -1,5 +0,0 @@ - -12 -34 -cr[PC]:0xffffffff; ir[1,at]:0x200002; ir[2,v0]:0x1; ir[4,a0]:0x22; keyboard[0x0]:''; display[0x0]:'1234'; - diff --git a/tests/arch/mips/correct/examples/test_mips_example_001.s b/tests/arch/mips/correct/examples/test_mips_example_001.s index 7961619d5..c44649b70 100644 --- a/tests/arch/mips/correct/examples/test_mips_example_001.s +++ b/tests/arch/mips/correct/examples/test_mips_example_001.s @@ -3,17 +3,35 @@ # Creator (https://creatorsim.github.io/creator/) # - .data +.data - byte: .byte 12 + byte: .byte 12 - .align 1 - half: .half 34 + .align 1 + half: .half 34 - .align 2 - word: .word -5678 - float: .float 456.322 - double: .double 9741.34 - stringZ: .asciiz "This is a string" - string: .ascii "This is another string" - space: .space 32 + .align 2 + word: .word -5678 + float: .float 456.322 + double: .double 9741.34 + stringZ: .asciiz "This is a string" + string: .ascii "This is another string" + space: .space 32 + +.text + main: + + # print byte value +first:la $a0, byte + lb $a0, 0($a0) + li $v0, 1 + syscall + + # print half value + la $a0, half + lh $a0, 0($a0) + li $v0, 1 + syscall + + #return + jr $ra diff --git a/tests/arch/mips/correct/examples/test_mips_example_002.out b/tests/arch/mips/correct/examples/test_mips_example_002.out deleted file mode 100644 index 4329ef305..000000000 --- a/tests/arch/mips/correct/examples/test_mips_example_002.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x20; ir[8,t0]:0xa; ir[9,t1]:0xd; ir[10,t2]:0x2d; ir[11,t3]:0x21; ir[12,t4]:0x17; ir[13,t5]:0xc; ir[14,t6]:0x441; ir[15,t7]:0x53; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/correct/examples/test_mips_example_002.s b/tests/arch/mips/correct/examples/test_mips_example_002.s index d4b38f55b..968178cff 100644 --- a/tests/arch/mips/correct/examples/test_mips_example_002.s +++ b/tests/arch/mips/correct/examples/test_mips_example_002.s @@ -15,3 +15,4 @@ main: sub $t5, $t2, $t3 # 45-33 mul $t6, $t3, $t3 # 33*33 div $t7, $t6, $t1 # $t6/13 + jr $ra diff --git a/tests/arch/mips/correct/examples/test_mips_example_003.out b/tests/arch/mips/correct/examples/test_mips_example_003.out deleted file mode 100644 index 043764100..000000000 --- a/tests/arch/mips/correct/examples/test_mips_example_003.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x78; ir[1,at]:0x20000e; ir[8,t0]:0x200000; ir[9,t1]:0x200004; ir[10,t2]:0x200006; ir[11,t3]:0xe; ir[12,t4]:0xe; ir[13,t5]:0x78; ir[14,t6]:0x78; ir[15,t7]:0x16; ir[24,t8]:0x16; memory[0x20000f]:0x16; memory[0x20000c]:0x78; memory[0x20000b]:0x0e; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/correct/examples/test_mips_example_003.s b/tests/arch/mips/correct/examples/test_mips_example_003.s index d1686ba04..c16a5f7d1 100644 --- a/tests/arch/mips/correct/examples/test_mips_example_003.s +++ b/tests/arch/mips/correct/examples/test_mips_example_003.s @@ -22,16 +22,16 @@ main: la $t1, b1 #b1 address -> $t1 la $t2, h1 #h1 address -> $t2 - lw $t3, ($t0) #Memory[$t0] -> $t3 + lw $t3, 0($t0) #Memory[$t0] -> $t3 lw $t4, w1 #Memory[w1] -> $t4 - lb $t5, ($t1) #Memory[$t1] -> $t5 + lb $t5, 0($t1) #Memory[$t1] -> $t5 lb $t6, b1 #Memory[b1] -> $t6 - lh $t7, ($t2) #Memory[$t2] -> $t7 + lh $t7, 0($t2) #Memory[$t2] -> $t7 lh $t8, h1 #Memory[h1] -> $t8 sw $t3, w2 #$t3 -> Memory[w2] sb $t5, b2 #$t5 -> Memory[b2] sh $t7, h2 #$t7 -> Memory[h2] - \ No newline at end of file + jr $ra diff --git a/tests/arch/mips/correct/examples/test_mips_example_004.out b/tests/arch/mips/correct/examples/test_mips_example_004.out deleted file mode 100644 index 5afd90f0b..000000000 --- a/tests/arch/mips/correct/examples/test_mips_example_004.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x64; ir[1,at]:0x200018; ir[2,v0]:0xa; ir[8,t0]:0x200000; ir[9,t1]:0x200008; ir[10,t2]:0x200010; ir[11,t3]:0x200028; sfpr[f0]:0x405145A1; sfpr[f1]:0xCAC08312; sfpr[f2]:0x4026E2D0; sfpr[f3]:0xE5604189; sfpr[f4]:0x4082A27E; sfpr[f5]:0xF9DB22D1; sfpr[f10]:0x4084CB33; sfpr[f11]:0x33333333; sfpr[f12]:0x404D1315; sfpr[f13]:0x4689C3E9; dfpr[FP0]:0x405145A1CAC08312; dfpr[FP2]:0x4026E2D0E5604189; dfpr[FP4]:0x4082A27EF9DB22D1; dfpr[FP10]:0x4084CB3333333333; dfpr[FP12]:0x404D13154689C3E9; memory[0x20002f]:0xE9; memory[0x20002e]:0xC3; memory[0x20002d]:0x89; memory[0x20002c]:0x46; memory[0x20002b]:0x15; memory[0x20002a]:0x13; memory[0x200029]:0x4D; memory[0x200028]:0x40; memory[0x200027]:0xD1; memory[0x200026]:0x22; memory[0x200025]:0xDB; memory[0x200024]:0xF9; memory[0x200023]:0x7E; memory[0x200022]:0xA2; memory[0x200021]:0x82; memory[0x200020]:0x40; memory[0x20001f]:0x12; memory[0x20001e]:0x83; memory[0x20001d]:0xC0; memory[0x20001c]:0xCA; memory[0x20001b]:0xA1; memory[0x20001a]:0x45; memory[0x200019]:0x51; memory[0x200018]:0x40; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/correct/examples/test_mips_example_004.s b/tests/arch/mips/correct/examples/test_mips_example_004.s index 981c7ca0a..b281964dc 100644 --- a/tests/arch/mips/correct/examples/test_mips_example_004.s +++ b/tests/arch/mips/correct/examples/test_mips_example_004.s @@ -17,18 +17,18 @@ main: la $t2, c la $t3, d - l.d $FP0, ($t0) - l.d $FP2, ($t1) - l.d $FP10, ($t2) + l.d $FP0, 0($t0) + l.d $FP2, 0($t1) + l.d $FP10, 0($t2) add.d $FP0, $FP0, $FP0 sub.d $FP4, $FP10, $FP0 div.d $FP12, $FP10, $FP2 - s.d $FP0, ($t3) + s.d $FP0, 0($t3) addi $t3, $t3, 8 - s.d $FP4, ($t3) + s.d $FP4, 0($t3) addi $t3, $t3, 8 - s.d $FP12, ($t3) + s.d $FP12, 0($t3) li $v0, 10 syscall diff --git a/tests/arch/mips/correct/examples/test_mips_example_005.out b/tests/arch/mips/correct/examples/test_mips_example_005.out deleted file mode 100644 index 85592e9a9..000000000 --- a/tests/arch/mips/correct/examples/test_mips_example_005.out +++ /dev/null @@ -1,4 +0,0 @@ - -45 -cr[PC]:0x30; ir[2,v0]:0x1; ir[4,a0]:0x2d; ir[8,t0]:0xa; ir[9,t1]:0xa; keyboard[0x0]:''; display[0x0]:'45'; - diff --git a/tests/arch/mips/correct/examples/test_mips_example_005.s b/tests/arch/mips/correct/examples/test_mips_example_005.s index 6954d93fa..4eb68e0a3 100644 --- a/tests/arch/mips/correct/examples/test_mips_example_005.s +++ b/tests/arch/mips/correct/examples/test_mips_example_005.s @@ -5,18 +5,18 @@ # Sum of the first 10 numbers from 0 to 9 .data - max: .byte 10 + max: .byte 10 .text - main: lb $t0, max - li $t1, 0 - li $a0, 0 - while: bge $t1, $t0, end_while - add $a0, $a0, $t1 - add $t1, $t1, 1 - b while + main: lb $t0, max + li $t1, 0 + li $a0, 0 + while: bge $t1, $t0, end_while + add $a0, $a0, $t1 + add $t1, $t1, 1 + b while - end_while: li $v0, 1 - syscall #print_int + end_while: li $v0, 1 + syscall #print_int + + jr $ra - - \ No newline at end of file diff --git a/tests/arch/mips/correct/examples/test_mips_example_006.out b/tests/arch/mips/correct/examples/test_mips_example_006.out deleted file mode 100644 index 86145f1b7..000000000 --- a/tests/arch/mips/correct/examples/test_mips_example_006.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x24; ir[1,at]:0x1; ir[2,v0]:0xa; ir[8,t0]:0x4; ir[9,t1]:0x2; ir[11,t3]:0x22; ir[24,t8]:0x22b; ir[25,t9]:0xb; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/correct/examples/test_mips_example_007.out b/tests/arch/mips/correct/examples/test_mips_example_007.out deleted file mode 100644 index 831227000..000000000 --- a/tests/arch/mips/correct/examples/test_mips_example_007.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x44; ir[1,at]:0x200000; ir[2,v0]:0xa; ir[9,t1]:0x5; ir[10,t2]:0x5; ir[11,t3]:0x1; ir[12,t4]:0x4; ir[13,t5]:0x200014; ir[14,t6]:0x5; ir[15,t7]:0xf; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/correct/examples/test_mips_example_007.s b/tests/arch/mips/correct/examples/test_mips_example_007.s index a50a482d9..1d475e3d3 100644 --- a/tests/arch/mips/correct/examples/test_mips_example_007.s +++ b/tests/arch/mips/correct/examples/test_mips_example_007.s @@ -22,7 +22,7 @@ loop1: beq $t1, $t2, end1 #if($t1 == $t2) --> jump to fin1 # loop body mul $t6, $t1, $t4 # $t1 * $t4 -> $t6 - lw $t6, ($t5) # Memory[$t5] -> $t6 + lw $t6, 0($t5) # Memory[$t5] -> $t6 add $t7, $t7, $t6 # $t6 + $t7 -> $t7 # loop next... diff --git a/tests/arch/mips/correct/examples/test_mips_example_008.out b/tests/arch/mips/correct/examples/test_mips_example_008.out deleted file mode 100644 index 32452f644..000000000 --- a/tests/arch/mips/correct/examples/test_mips_example_008.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x5c; ir[1,at]:0x200040; ir[2,v0]:0xa; ir[8,t0]:0x200040; ir[9,t1]:0x200080; ir[10,t2]:0x4; ir[11,t3]:0x4; ir[12,t4]:0x4; sfpr[f0]:0x33441124; dfpr[FP0]:0x3344112400000000; memory[0x20007f]:0x24; memory[0x20007e]:0x11; memory[0x20007d]:0x44; memory[0x20007c]:0x33; memory[0x20007b]:0x21; memory[0x20007a]:0x43; memory[0x200079]:0x65; memory[0x200078]:0x87; memory[0x200077]:0x78; memory[0x200076]:0x56; memory[0x200075]:0x34; memory[0x200074]:0x12; memory[0x200073]:0x23; memory[0x200072]:0xff; memory[0x20006d]:0xd0; memory[0x20006c]:0x77; memory[0x20006b]:0x12; memory[0x20006a]:0xf0; memory[0x200069]:0xbf; memory[0x200068]:0xaa; memory[0x200067]:0x22; memory[0x200066]:0x11; memory[0x200065]:0x55; memory[0x200064]:0x44; memory[0x200063]:0x14; memory[0x200062]:0x02; memory[0x20005f]:0x14; memory[0x20005e]:0x14; memory[0x20005d]:0x14; memory[0x20005c]:0x14; memory[0x20005b]:0x20; memory[0x20005a]:0x21; memory[0x200059]:0x51; memory[0x200058]:0x77; memory[0x200057]:0x10; memory[0x200056]:0x22; memory[0x200055]:0x43; memory[0x200051]:0x45; memory[0x200050]:0x23; memory[0x20004c]:0x34; memory[0x200048]:0x34; memory[0x200044]:0x34; memory[0x200040]:0x34; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/correct/examples/test_mips_example_011.out b/tests/arch/mips/correct/examples/test_mips_example_011.out deleted file mode 100644 index 25e4c6e16..000000000 --- a/tests/arch/mips/correct/examples/test_mips_example_011.out +++ /dev/null @@ -1,4 +0,0 @@ - --144 -cr[PC]:0x38; ir[1,at]:0xffffffb3; ir[2,v0]:0xa; ir[3,v1]:0x5a; ir[4,a0]:0xffffff70; ir[5,a1]:0x5a; ir[6,a2]:0x2d; ir[9,t1]:0xffffffca; ir[10,t2]:0x5a; ir[31,ra]:0x24; keyboard[0x0]:''; display[0x0]:'-144'; - diff --git a/tests/arch/mips/correct/examples/test_mips_example_012.out b/tests/arch/mips/correct/examples/test_mips_example_012.out deleted file mode 100644 index 8a933c1f1..000000000 --- a/tests/arch/mips/correct/examples/test_mips_example_012.out +++ /dev/null @@ -1,4 +0,0 @@ - -120 -cr[PC]:0x1c; ir[1,at]:0x1; ir[2,v0]:0xa; ir[4,a0]:0x78; ir[9,t1]:0x5; ir[31,ra]:0x8; keyboard[0x0]:''; display[0x0]:'120'; - diff --git a/tests/arch/mips/correct/examples/test_mips_example_012.s b/tests/arch/mips/correct/examples/test_mips_example_012.s index d29c63883..de82be4e1 100644 --- a/tests/arch/mips/correct/examples/test_mips_example_012.s +++ b/tests/arch/mips/correct/examples/test_mips_example_012.s @@ -31,7 +31,7 @@ factorial: # if ($a < 2): # return 1 - bge $a0 2, b_else + bge $a0, 2, b_else li $v0, 1 b b_efs # else: diff --git a/tests/arch/mips/correct/examples/test_mips_example_013.out b/tests/arch/mips/correct/examples/test_mips_example_013.out deleted file mode 100644 index 97dfc5ec5..000000000 --- a/tests/arch/mips/correct/examples/test_mips_example_013.out +++ /dev/null @@ -1,41 +0,0 @@ - -83 -116 -114 -105 -110 -103 -32 -105 -110 -32 -85 -84 -70 -45 -56 -58 -32 --30 --120 --128 -32 --30 --120 --85 -32 --30 --120 --121 -32 --30 --120 --120 -32 --16 --97 --96 --84 -0 -cr[PC]:0x20; ir[1,at]:0x200000; ir[2,v0]:0x1; ir[8,t0]:0x200026; keyboard[0x0]:''; display[0x0]:'83116114105110103321051103285847045565832-30-120-12832-30-120-8532-30-120-12132-30-120-12032-16-97-96-840'; - diff --git a/tests/arch/mips/correct/examples/test_mips_example_013.s b/tests/arch/mips/correct/examples/test_mips_example_013.s new file mode 100644 index 000000000..074a0c3c3 --- /dev/null +++ b/tests/arch/mips/correct/examples/test_mips_example_013.s @@ -0,0 +1,16 @@ + +# +# Creator (https://creatorsim.github.io/creator/) +# + +.data + utf8: .asciiz "String in UTF-8: ∀ ∫ ∇ ∈ 🠬" + +.text +main: li $v0, 1 + la $t0, utf8 +loop: lb $a0, 0($t0) + syscall + addi $t0, $t0, 1 + bne $a0, $zero, loop + jr $ra diff --git a/tests/arch/mips/correct/syscalls/test_mips_syscall_001.out b/tests/arch/mips/correct/syscalls/test_mips_syscall_001.out deleted file mode 100644 index 601697ff4..000000000 --- a/tests/arch/mips/correct/syscalls/test_mips_syscall_001.out +++ /dev/null @@ -1,10 +0,0 @@ - -6673 -120 -1 -34 --5678 -1 -1416128883 -cr[PC]:0x6c; ir[1,at]:0x200008; ir[2,v0]:0x1; ir[4,a0]:0x54686973; ir[8,t0]:0x4; ir[9,t1]:0x200000; keyboard[0x0]:''; display[0x0]:'6673120134-567811416128883'; - diff --git a/tests/arch/mips/correct/syscalls/test_mips_syscall_001.s b/tests/arch/mips/correct/syscalls/test_mips_syscall_001.s index 6b17047be..cea51ca33 100644 --- a/tests/arch/mips/correct/syscalls/test_mips_syscall_001.s +++ b/tests/arch/mips/correct/syscalls/test_mips_syscall_001.s @@ -6,7 +6,7 @@ .align 2 - byte: .byte 120,257 + byte: .byte 120,1 half: .half 34 word: .word -5678 string: .ascii "This is another string" @@ -36,10 +36,12 @@ main: lw $a0, word syscall - # print float - li $a0, 1.1 + # print int + li $a0, 1 syscall # string string lw $a0, string - syscall \ No newline at end of file + syscall + + jr $ra diff --git a/tests/arch/mips/correct/syscalls/test_mips_syscall_002.out b/tests/arch/mips/correct/syscalls/test_mips_syscall_002.out deleted file mode 100644 index 396e1786f..000000000 --- a/tests/arch/mips/correct/syscalls/test_mips_syscall_002.out +++ /dev/null @@ -1,6 +0,0 @@ - -6673 --86.9739990234375 -1.100000023841858 -cr[PC]:0x34; ir[1,at]:0x3f8ccccd; ir[2,v0]:0x2; sfpr[f12]:0x3F8CCCCD; dfpr[FP12]:0x3F8CCCCD00000000; keyboard[0x0]:''; display[0x0]:'6673-86.97399902343751.100000023841858'; - diff --git a/tests/arch/mips/correct/syscalls/test_mips_syscall_002.s b/tests/arch/mips/correct/syscalls/test_mips_syscall_002.s index 2b6d4d4cb..3cadd0042 100644 --- a/tests/arch/mips/correct/syscalls/test_mips_syscall_002.s +++ b/tests/arch/mips/correct/syscalls/test_mips_syscall_002.s @@ -15,4 +15,5 @@ main: li.s $f12, 1.1 syscall - \ No newline at end of file + + jr $ra diff --git a/tests/arch/mips/correct/syscalls/test_mips_syscall_003.out b/tests/arch/mips/correct/syscalls/test_mips_syscall_003.out deleted file mode 100644 index 668c40ee9..000000000 --- a/tests/arch/mips/correct/syscalls/test_mips_syscall_003.out +++ /dev/null @@ -1,6 +0,0 @@ - -6673 --86.974 -1.1 -cr[PC]:0x58; ir[1,at]:0x3ff19999; ir[2,v0]:0x3; sfpr[f12]:0x3FF19999; sfpr[f13]:0x9999999A; dfpr[FP12]:0x3FF199999999999A; keyboard[0x0]:''; display[0x0]:'6673-86.9741.1'; - diff --git a/tests/arch/mips/correct/syscalls/test_mips_syscall_003.s b/tests/arch/mips/correct/syscalls/test_mips_syscall_003.s index aba6d1d2b..350992844 100644 --- a/tests/arch/mips/correct/syscalls/test_mips_syscall_003.s +++ b/tests/arch/mips/correct/syscalls/test_mips_syscall_003.s @@ -15,4 +15,5 @@ main: li.d $FP12, 1.1 syscall - \ No newline at end of file + + jr $ra diff --git a/tests/arch/mips/correct/syscalls/test_mips_syscall_004.out b/tests/arch/mips/correct/syscalls/test_mips_syscall_004.out deleted file mode 100644 index 448ffe1e3..000000000 --- a/tests/arch/mips/correct/syscalls/test_mips_syscall_004.out +++ /dev/null @@ -1,8 +0,0 @@ - -First String -Second Stringa -a - - -cr[PC]:0x40; ir[1,at]:0x20001a; ir[2,v0]:0xb; ir[4,a0]:0xa; keyboard[0x0]:''; display[0x0]:'First%20StringSecond%20Stringaa%0A'; - diff --git a/tests/arch/mips/correct/syscalls/test_mips_syscall_004.s b/tests/arch/mips/correct/syscalls/test_mips_syscall_004.s index de034a1ac..ea6263858 100644 --- a/tests/arch/mips/correct/syscalls/test_mips_syscall_004.s +++ b/tests/arch/mips/correct/syscalls/test_mips_syscall_004.s @@ -26,3 +26,4 @@ main: li $v0, 11 syscall + jr $ra diff --git a/tests/arch/mips/correct/syscalls/test_mips_syscall_005.s b/tests/arch/mips/correct/syscalls/test_mips_syscall_005.s index 668534068..852bf8182 100644 --- a/tests/arch/mips/correct/syscalls/test_mips_syscall_005.s +++ b/tests/arch/mips/correct/syscalls/test_mips_syscall_005.s @@ -6,4 +6,5 @@ .text main: li $v0, 5 - syscall \ No newline at end of file + syscall + jr $ra diff --git a/tests/arch/mips/correct/syscalls/test_mips_syscall_006.s b/tests/arch/mips/correct/syscalls/test_mips_syscall_006.s index ab013f90f..c81330dcd 100644 --- a/tests/arch/mips/correct/syscalls/test_mips_syscall_006.s +++ b/tests/arch/mips/correct/syscalls/test_mips_syscall_006.s @@ -7,3 +7,4 @@ main: li $v0, 6 syscall + jr $ra diff --git a/tests/arch/mips/correct/syscalls/test_mips_syscall_007.s b/tests/arch/mips/correct/syscalls/test_mips_syscall_007.s index 88a7ae8a5..fa8a7fd0f 100644 --- a/tests/arch/mips/correct/syscalls/test_mips_syscall_007.s +++ b/tests/arch/mips/correct/syscalls/test_mips_syscall_007.s @@ -7,4 +7,4 @@ main: li $v0, 7 syscall - \ No newline at end of file + jr $ra diff --git a/tests/arch/mips/correct/syscalls/test_mips_syscall_008.s b/tests/arch/mips/correct/syscalls/test_mips_syscall_008.s index c36f690b4..3faed0190 100644 --- a/tests/arch/mips/correct/syscalls/test_mips_syscall_008.s +++ b/tests/arch/mips/correct/syscalls/test_mips_syscall_008.s @@ -14,4 +14,5 @@ li $v0, 8 la $a0, buffer li $a1, 5 - syscall \ No newline at end of file + syscall + jr $ra diff --git a/tests/arch/mips/correct/syscalls/test_mips_syscall_009.s b/tests/arch/mips/correct/syscalls/test_mips_syscall_009.s index 38676b338..92e84411b 100644 --- a/tests/arch/mips/correct/syscalls/test_mips_syscall_009.s +++ b/tests/arch/mips/correct/syscalls/test_mips_syscall_009.s @@ -12,5 +12,6 @@ li $a0, 8 syscall - sw $t0, ($v0) - sw $t1, 4($v0) \ No newline at end of file + sw $t0, 0($v0) + sw $t1, 4($v0) + jr $ra diff --git a/tests/arch/mips/correct/syscalls/test_mips_syscall_010.out b/tests/arch/mips/correct/syscalls/test_mips_syscall_010.out deleted file mode 100644 index 413fc0e89..000000000 --- a/tests/arch/mips/correct/syscalls/test_mips_syscall_010.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x8; ir[2,v0]:0xa; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/correct/syscalls/test_mips_syscall_010.s b/tests/arch/mips/correct/syscalls/test_mips_syscall_010.s index c5b86634f..f2662a383 100644 --- a/tests/arch/mips/correct/syscalls/test_mips_syscall_010.s +++ b/tests/arch/mips/correct/syscalls/test_mips_syscall_010.s @@ -8,3 +8,4 @@ li $v0, 10 syscall li $t0, 453 + jr $ra diff --git a/tests/arch/mips/correct/syscalls/test_mips_syscall_011.out b/tests/arch/mips/correct/syscalls/test_mips_syscall_011.out deleted file mode 100644 index 78634f9ba..000000000 --- a/tests/arch/mips/correct/syscalls/test_mips_syscall_011.out +++ /dev/null @@ -1,4 +0,0 @@ - -c -cr[PC]:0xc; ir[2,v0]:0xb; ir[4,a0]:0x63; keyboard[0x0]:''; display[0x0]:'c'; - diff --git a/tests/arch/mips/correct/syscalls/test_mips_syscall_011.s b/tests/arch/mips/correct/syscalls/test_mips_syscall_011.s index 34f522d9c..231dd5e92 100644 --- a/tests/arch/mips/correct/syscalls/test_mips_syscall_011.s +++ b/tests/arch/mips/correct/syscalls/test_mips_syscall_011.s @@ -8,3 +8,4 @@ li $v0, 11 li $a0, 'c' syscall + jr $ra diff --git a/tests/arch/mips/correct/syscalls/test_mips_syscall_012.s b/tests/arch/mips/correct/syscalls/test_mips_syscall_012.s index b58a811e1..dca4c5a81 100644 --- a/tests/arch/mips/correct/syscalls/test_mips_syscall_012.s +++ b/tests/arch/mips/correct/syscalls/test_mips_syscall_012.s @@ -3,7 +3,8 @@ # Creator (https://creatorsim.github.io/creator/) # -.text - main: +.text + main: li $v0, 12 - syscall \ No newline at end of file + syscall + jr $ra diff --git a/tests/arch/mips/instructions/test_mips_instruction_001.out b/tests/arch/mips/instructions/test_mips_instruction_001.out deleted file mode 100644 index 900b4d789..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_001.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x24; ir[1,at]:0xffffffe2; ir[8,t0]:0xa; ir[9,t1]:0xffffffe2; ir[11,t3]:0x12; ir[12,t4]:0xffffffec; ir[13,t5]:0xffffffe2; ir[14,t6]:0x12; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_001.s b/tests/arch/mips/instructions/test_mips_instruction_001.s index d87d151cd..1a78a7d75 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_001.s +++ b/tests/arch/mips/instructions/test_mips_instruction_001.s @@ -13,4 +13,6 @@ main: add $t4, $t0, $t1 add $t5, $t1, $t2 - add $t6, $t2, $t3 \ No newline at end of file + add $t6, $t2, $t3 + + jr $ra diff --git a/tests/arch/mips/instructions/test_mips_instruction_002.out b/tests/arch/mips/instructions/test_mips_instruction_002.out deleted file mode 100644 index db1062c53..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_002.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x10; ir[8,t0]:0xa; ir[9,t1]:0xffffffec; ir[10,t2]:0x187; ir[11,t3]:0x193; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_002.s b/tests/arch/mips/instructions/test_mips_instruction_002.s index 2b6b6ab14..b86067357 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_002.s +++ b/tests/arch/mips/instructions/test_mips_instruction_002.s @@ -9,3 +9,5 @@ main: addi $t1, $t0, -30 # 10 - 30 addi $t2, $t1, 411 # x9 + 411 addi $t3, $t2, 12 # x10 - 12 + + jr $ra diff --git a/tests/arch/mips/instructions/test_mips_instruction_003.out b/tests/arch/mips/instructions/test_mips_instruction_003.out deleted file mode 100644 index bacd4ab5c..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_003.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x2c; ir[1,at]:0x123515; ir[8,t0]:0x223; ir[9,t1]:0xfffffc57; ir[10,t2]:0xc; ir[11,t3]:0x123515; ir[12,t4]:0x5cc; ir[13,t5]:0xfffffa40; ir[14,t6]:0x123ad5; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_003.s b/tests/arch/mips/instructions/test_mips_instruction_003.s index 8be9b6661..ec09e2523 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_003.s +++ b/tests/arch/mips/instructions/test_mips_instruction_003.s @@ -13,4 +13,6 @@ main: sub $t4, $t0, $t1 sub $t5, $t2, $t4 - sub $t6, $t3, $t5 \ No newline at end of file + sub $t6, $t3, $t5 + + jr $ra diff --git a/tests/arch/mips/instructions/test_mips_instruction_004.out b/tests/arch/mips/instructions/test_mips_instruction_004.out deleted file mode 100644 index 57115dae6..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_004.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x14; ir[8,t0]:0x230000; ir[14,t6]:0x56db0000; ir[15,t7]:0x340000; ir[24,t8]:0xff00000; ir[25,t9]:0x20000; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_004.s b/tests/arch/mips/instructions/test_mips_instruction_004.s index 638557b1b..5de59e58b 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_004.s +++ b/tests/arch/mips/instructions/test_mips_instruction_004.s @@ -10,4 +10,6 @@ main: lui $t6, 22235 lui $t7, 0x34 lui $t8, 0xFF0 - lui $t9, 2 \ No newline at end of file + lui $t9, 2 + + jr $ra diff --git a/tests/arch/mips/instructions/test_mips_instruction_005.out b/tests/arch/mips/instructions/test_mips_instruction_005.out deleted file mode 100644 index 20e66e4df..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_005.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x38; ir[1,at]:0x123515; ir[4,a0]:0xa; ir[13,t5]:0x223; ir[14,t6]:0xfffffc57; ir[15,t7]:0xc; ir[24,t8]:0x123515; ir[31,ra]:0x24; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_005.s b/tests/arch/mips/instructions/test_mips_instruction_005.s index a1a50a895..db66cdc7c 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_005.s +++ b/tests/arch/mips/instructions/test_mips_instruction_005.s @@ -18,5 +18,5 @@ main: sub $s2, $t8, $s1 end: - li $a0, 10 - syscall \ No newline at end of file + li $v0, 10 + syscall diff --git a/tests/arch/mips/instructions/test_mips_instruction_006.out b/tests/arch/mips/instructions/test_mips_instruction_006.out deleted file mode 100644 index 46acb6292..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_006.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x3c; ir[1,at]:0x123515; ir[4,a0]:0xa; ir[8,t0]:0x223; ir[9,t1]:0xfffffc57; ir[10,t2]:0xc; ir[11,t3]:0x123515; ir[12,t4]:0x28; ir[24,t8]:0x34; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_006.s b/tests/arch/mips/instructions/test_mips_instruction_006.s index d71724420..872dca943 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_006.s +++ b/tests/arch/mips/instructions/test_mips_instruction_006.s @@ -19,5 +19,5 @@ main: sub $t7, $t3, $t4 end: - li $a0, 10 - syscall \ No newline at end of file + li $v0, 10 + syscall diff --git a/tests/arch/mips/instructions/test_mips_instruction_007.out b/tests/arch/mips/instructions/test_mips_instruction_007.out deleted file mode 100644 index 68d7ecac0..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_007.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x34; ir[1,at]:0x44562; ir[2,v0]:0xa; ir[8,t0]:0x44562; ir[9,t1]:0x2; ir[10,t2]:0x5; ir[11,t3]:0x44562; ir[12,t4]:0xb; ir[13,t5]:0x22b; ir[14,t6]:0x22; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_007.s b/tests/arch/mips/instructions/test_mips_instruction_007.s index f7669e2c0..d63d8f503 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_007.s +++ b/tests/arch/mips/instructions/test_mips_instruction_007.s @@ -9,7 +9,6 @@ li $t1, 2 li $t2, 5 li $t3, 0x44562 - beq $t2, $t0, jump1 beq $t0, $t3, jump1 jump2: diff --git a/tests/arch/mips/instructions/test_mips_instruction_008.out b/tests/arch/mips/instructions/test_mips_instruction_008.out deleted file mode 100644 index 0528e6b1e..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_008.out +++ /dev/null @@ -1,12 +0,0 @@ - - -Error at line 8 (li $rd val): -Incorrect instruction syntax for 'li $rd val' - - 7 main: -->8 li x5, 361 - 9 li x6, 2 - -Not executed -keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_008.s b/tests/arch/mips/instructions/test_mips_instruction_008.s index 4166e27fd..303d953e3 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_008.s +++ b/tests/arch/mips/instructions/test_mips_instruction_008.s @@ -5,18 +5,18 @@ .text main: - li x5, 361 - li x6, 2 - li x7, 5 - li x8, 0x44562 - bne x5, x7, jump1 + li $t0, 0x44562 + li $t1, 2 + li $t2, 5 + li $t3, 0x44562 + bne $t2, $t0, jump1 jump2: - li t3, 34 - li a7, 10 - ecall + li $t6, 34 + li $v0, 10 + syscall jump1: - li x5, 0x754 - li x6, 555 - bne x5, x6, jump2 + li $t4, 0x754 + li $t5, 555 + bne $t0, $t2, jump2 diff --git a/tests/arch/mips/instructions/test_mips_instruction_009.out b/tests/arch/mips/instructions/test_mips_instruction_009.out deleted file mode 100644 index cbaa6cb41..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_009.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x34; ir[1,at]:0x1; ir[2,v0]:0xa; ir[8,t0]:0x169; ir[9,t1]:0x2; ir[10,t2]:0x5; ir[11,t3]:0x44562; ir[12,t4]:0xb; ir[13,t5]:0x22b; ir[14,t6]:0x22; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_010.out b/tests/arch/mips/instructions/test_mips_instruction_010.out deleted file mode 100644 index d969fee5e..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_010.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x34; ir[2,v0]:0xa; ir[8,t0]:0x169; ir[9,t1]:0x2; ir[10,t2]:0x5; ir[11,t3]:0x44562; ir[12,t4]:0x754; ir[13,t5]:0x22b; ir[14,t6]:0x22; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_011.out b/tests/arch/mips/instructions/test_mips_instruction_011.out deleted file mode 100644 index 6b9821a08..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_011.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x34; ir[1,at]:0x1; ir[2,v0]:0xa; ir[8,t0]:0x169; ir[9,t1]:0x2; ir[10,t2]:0x5; ir[11,t3]:0x44562; ir[12,t4]:0x754; ir[13,t5]:0x22b; ir[14,t6]:0x22; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_012.out b/tests/arch/mips/instructions/test_mips_instruction_012.out deleted file mode 100644 index d969fee5e..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_012.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x34; ir[2,v0]:0xa; ir[8,t0]:0x169; ir[9,t1]:0x2; ir[10,t2]:0x5; ir[11,t3]:0x44562; ir[12,t4]:0x754; ir[13,t5]:0x22b; ir[14,t6]:0x22; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_013.out b/tests/arch/mips/instructions/test_mips_instruction_013.out deleted file mode 100644 index ca3e7acd1..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_013.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x84; ir[1,at]:0x20000e; ir[8,t0]:0x200000; ir[9,t1]:0x200004; ir[10,t2]:0x200006; ir[11,t3]:0xe; ir[12,t4]:0xe; ir[13,t5]:0x7f; ir[14,t6]:0x7f; ir[15,t7]:0x7fff; ir[24,t8]:0x7fff; ir[25,t9]:0x20000e; memory[0x20000f]:0xff; memory[0x20000e]:0x7f; memory[0x20000c]:0x7f; memory[0x20000b]:0x0e; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_013.s b/tests/arch/mips/instructions/test_mips_instruction_013.s index 1a671a08a..db2d72275 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_013.s +++ b/tests/arch/mips/instructions/test_mips_instruction_013.s @@ -39,3 +39,5 @@ main: la $t9, h2 sh $t7, 0($t9) + + jr $ra diff --git a/tests/arch/mips/instructions/test_mips_instruction_014.out b/tests/arch/mips/instructions/test_mips_instruction_014.out deleted file mode 100644 index 6b1659aaf..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_014.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x40; ir[1,at]:0x200006; ir[8,t0]:0x200000; ir[9,t1]:0x200002; ir[10,t2]:0x7f; ir[11,t3]:0xffff; ir[12,t4]:0x200004; ir[14,t6]:0x200006; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_014.s b/tests/arch/mips/instructions/test_mips_instruction_014.s index 8b2c9dbbf..d2b77184c 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_014.s +++ b/tests/arch/mips/instructions/test_mips_instruction_014.s @@ -26,3 +26,5 @@ main: la $t6, h2 sh $t7, 0($t6) + + jr $ra diff --git a/tests/arch/mips/instructions/test_mips_instruction_015.out b/tests/arch/mips/instructions/test_mips_instruction_015.out deleted file mode 100644 index 59829a8d8..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_015.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x30; ir[1,at]:0xfffffc00; ir[8,t0]:0x2f0; ir[11,t3]:0x1; ir[12,t4]:0x1; ir[13,t5]:0xfffffc00; ir[24,t8]:0x1; ir[25,t9]:0x1; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_015.s b/tests/arch/mips/instructions/test_mips_instruction_015.s index c9c855656..06cf9cea7 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_015.s +++ b/tests/arch/mips/instructions/test_mips_instruction_015.s @@ -17,3 +17,5 @@ main: slti $t7, $t5, -1024 slti $t8, $t5, -1023 slti $t9, $t5, -1022 + + jr $ra diff --git a/tests/arch/mips/instructions/test_mips_instruction_016.out b/tests/arch/mips/instructions/test_mips_instruction_016.out deleted file mode 100644 index 59829a8d8..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_016.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x30; ir[1,at]:0xfffffc00; ir[8,t0]:0x2f0; ir[11,t3]:0x1; ir[12,t4]:0x1; ir[13,t5]:0xfffffc00; ir[24,t8]:0x1; ir[25,t9]:0x1; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_016.s b/tests/arch/mips/instructions/test_mips_instruction_016.s index 18931a363..8797f2a56 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_016.s +++ b/tests/arch/mips/instructions/test_mips_instruction_016.s @@ -17,3 +17,5 @@ main: sltiu $t7, $t5, -1024 sltiu $t8, $t5, -1023 sltiu $t9, $t5, -1022 + + jr $ra diff --git a/tests/arch/mips/instructions/test_mips_instruction_017.out b/tests/arch/mips/instructions/test_mips_instruction_017.out deleted file mode 100644 index 8f3ec36ae..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_017.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x28; ir[1,at]:0xffffdaf2; ir[8,t0]:0x22346; ir[9,t1]:0x11d7; ir[10,t2]:0xffffdaf2; ir[11,t3]:0x22713; ir[12,t4]:0x13f5; ir[13,t5]:0xffffd50d; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_017.s b/tests/arch/mips/instructions/test_mips_instruction_017.s index c558df997..0f16a6129 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_017.s +++ b/tests/arch/mips/instructions/test_mips_instruction_017.s @@ -14,3 +14,4 @@ main: xori $t4, $t1, 0x222 xori $t5, $t2, 0xFFF + jr $ra diff --git a/tests/arch/mips/instructions/test_mips_instruction_018.out b/tests/arch/mips/instructions/test_mips_instruction_018.out deleted file mode 100644 index e4fa60c7e..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_018.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x28; ir[1,at]:0xffffdaf2; ir[8,t0]:0x22346; ir[9,t1]:0x11d7; ir[10,t2]:0xffffdaf2; ir[11,t3]:0x22757; ir[12,t4]:0x13f7; ir[13,t5]:0xffffdfff; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_018.s b/tests/arch/mips/instructions/test_mips_instruction_018.s index 187350c05..d9100a7b6 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_018.s +++ b/tests/arch/mips/instructions/test_mips_instruction_018.s @@ -13,3 +13,5 @@ main: ori $t3, $t0, 0x455 ori $t4, $t1, 0x222 ori $t5, $t2, 0xFFF + + jr $ra diff --git a/tests/arch/mips/instructions/test_mips_instruction_019.out b/tests/arch/mips/instructions/test_mips_instruction_019.out deleted file mode 100644 index 7b376001e..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_019.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x28; ir[1,at]:0xffffdaf2; ir[8,t0]:0x22346; ir[9,t1]:0x11d7; ir[10,t2]:0xffffdaf2; ir[11,t3]:0x44; ir[12,t4]:0x2; ir[13,t5]:0xaf2; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_019.s b/tests/arch/mips/instructions/test_mips_instruction_019.s index 6c48b4a04..2303680d0 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_019.s +++ b/tests/arch/mips/instructions/test_mips_instruction_019.s @@ -13,4 +13,5 @@ main: andi $t3, $t0, 0x455 andi $t4, $t1, 0x222 andi $t5, $t2, 0xFFF - + + jr $ra diff --git a/tests/arch/mips/instructions/test_mips_instruction_020.out b/tests/arch/mips/instructions/test_mips_instruction_020.out deleted file mode 100644 index dad0761ad..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_020.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x28; cr[HI]:0x18; ir[1,at]:0xffffe000; ir[8,t0]:0x10; ir[9,t1]:0x100; ir[10,t2]:0xffffe000; ir[11,t3]:0x18; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_020.s b/tests/arch/mips/instructions/test_mips_instruction_020.s index 614f46890..f3072dd69 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_020.s +++ b/tests/arch/mips/instructions/test_mips_instruction_020.s @@ -15,3 +15,5 @@ main: div $t1, $t0 div $t2, $t3 div $t3, $t2 + + jr $ra diff --git a/tests/arch/mips/instructions/test_mips_instruction_021.out b/tests/arch/mips/instructions/test_mips_instruction_021.out deleted file mode 100644 index dad0761ad..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_021.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x28; cr[HI]:0x18; ir[1,at]:0xffffe000; ir[8,t0]:0x10; ir[9,t1]:0x100; ir[10,t2]:0xffffe000; ir[11,t3]:0x18; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_021.s b/tests/arch/mips/instructions/test_mips_instruction_021.s index a23893e7b..66663f35e 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_021.s +++ b/tests/arch/mips/instructions/test_mips_instruction_021.s @@ -15,3 +15,5 @@ main: divu $t1, $t0 divu $t2, $t3 divu $t3, $t2 + + jr $ra diff --git a/tests/arch/mips/instructions/test_mips_instruction_022.out b/tests/arch/mips/instructions/test_mips_instruction_022.out deleted file mode 100644 index 688c96a0a..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_022.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x28; ir[1,at]:0xffffdaf2; ir[8,t0]:0xaad4; ir[9,t1]:0x11d7; ir[10,t2]:0xffffdaf2; ir[11,t3]:0x2ab5; ir[12,t4]:0x7000011d; ir[13,t5]:0xb5e5ffff; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_022.s b/tests/arch/mips/instructions/test_mips_instruction_022.s index ce58bf55f..6891c41de 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_022.s +++ b/tests/arch/mips/instructions/test_mips_instruction_022.s @@ -13,3 +13,5 @@ main: rotr $t3, $t0, 2 rotr $t4, $t1, 4 rotr $t5, $t2, 15 + + jr $ra diff --git a/tests/arch/mips/instructions/test_mips_instruction_023.out b/tests/arch/mips/instructions/test_mips_instruction_023.out deleted file mode 100644 index 206f0d6eb..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_023.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x28; ir[1,at]:0xffffdaf2; ir[8,t0]:0xaad4; ir[9,t1]:0x11d7; ir[10,t2]:0xffffdaf2; ir[11,t3]:0x2ab50; ir[12,t4]:0x11d70; ir[13,t5]:0xed790000; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_023.s b/tests/arch/mips/instructions/test_mips_instruction_023.s index faf899208..901e7d0a8 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_023.s +++ b/tests/arch/mips/instructions/test_mips_instruction_023.s @@ -13,3 +13,5 @@ main: sll $t3, $t0, 2 sll $t4, $t1, 4 sll $t5, $t2, 15 + + jr $ra diff --git a/tests/arch/mips/instructions/test_mips_instruction_024.out b/tests/arch/mips/instructions/test_mips_instruction_024.out deleted file mode 100644 index 6fb5b5912..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_024.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x20; ir[8,t0]:0x1fff; ir[9,t1]:0x2000; ir[10,t2]:0x2001; ir[11,t3]:0x2002; ir[14,t6]:0x1; ir[15,t7]:0x1; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_024.s b/tests/arch/mips/instructions/test_mips_instruction_024.s index 61f93bcc6..bab810e37 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_024.s +++ b/tests/arch/mips/instructions/test_mips_instruction_024.s @@ -15,4 +15,5 @@ main: slt $t5, $t1, $t1 slt $t6, $t1, $t2 slt $t7, $t1, $t3 - + + jr $ra diff --git a/tests/arch/mips/instructions/test_mips_instruction_025.out b/tests/arch/mips/instructions/test_mips_instruction_025.out deleted file mode 100644 index 6fb5b5912..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_025.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x20; ir[8,t0]:0x1fff; ir[9,t1]:0x2000; ir[10,t2]:0x2001; ir[11,t3]:0x2002; ir[14,t6]:0x1; ir[15,t7]:0x1; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_025.s b/tests/arch/mips/instructions/test_mips_instruction_025.s index 108210861..8e95e7cac 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_025.s +++ b/tests/arch/mips/instructions/test_mips_instruction_025.s @@ -15,3 +15,5 @@ sltu $t4, $t1, $t0 sltu $t5, $t1, $t1 sltu $t6, $t1, $t2 sltu $t7, $t1, $t3 + +jr $ra diff --git a/tests/arch/mips/instructions/test_mips_instruction_026.out b/tests/arch/mips/instructions/test_mips_instruction_026.out deleted file mode 100644 index 66db93488..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_026.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x34; ir[1,at]:0xffffdaf2; ir[8,t0]:0x22346; ir[9,t1]:0x11d7; ir[10,t2]:0xffffdaf2; ir[11,t3]:0x455; ir[12,t4]:0x222; ir[13,t5]:0xfff; ir[14,t6]:0x22713; ir[15,t7]:0x13f5; ir[24,t8]:0xffffd50d; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_026.s b/tests/arch/mips/instructions/test_mips_instruction_026.s index 791c9e161..469709e5c 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_026.s +++ b/tests/arch/mips/instructions/test_mips_instruction_026.s @@ -17,4 +17,5 @@ main: xor $t6, $t0, $t3 xor $t7, $t1, $t4 xor $t8, $t2, $t5 - + + jr $ra diff --git a/tests/arch/mips/instructions/test_mips_instruction_027.out b/tests/arch/mips/instructions/test_mips_instruction_027.out deleted file mode 100644 index 103850674..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_027.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x28; ir[1,at]:0xffffdaf2; ir[8,t0]:0xaad4; ir[9,t1]:0x11d7; ir[10,t2]:0xffffdaf2; ir[11,t3]:0x2ab5; ir[12,t4]:0x11d; ir[13,t5]:0x1ffff; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_027.s b/tests/arch/mips/instructions/test_mips_instruction_027.s index af90b6329..1e65511ce 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_027.s +++ b/tests/arch/mips/instructions/test_mips_instruction_027.s @@ -13,3 +13,5 @@ main: srl $t3, $t0, 2 srl $t4, $t1, 4 srl $t5, $t2, 15 + + jr $ra diff --git a/tests/arch/mips/instructions/test_mips_instruction_028.out b/tests/arch/mips/instructions/test_mips_instruction_028.out deleted file mode 100644 index 96e538869..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_028.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x28; ir[1,at]:0xffffdaf2; ir[8,t0]:0xaad4; ir[9,t1]:0x11d7; ir[10,t2]:0xffffdaf2; ir[11,t3]:0x2ab5; ir[12,t4]:0x11d; ir[13,t5]:0xffffffff; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_028.s b/tests/arch/mips/instructions/test_mips_instruction_028.s index 6dbd5b035..57030738d 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_028.s +++ b/tests/arch/mips/instructions/test_mips_instruction_028.s @@ -13,3 +13,5 @@ main: sra $t3, $t0, 2 sra $t4, $t1, 4 sra $t5, $t2, 15 + + jr $ra diff --git a/tests/arch/mips/instructions/test_mips_instruction_029.out b/tests/arch/mips/instructions/test_mips_instruction_029.out deleted file mode 100644 index e5a99869f..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_029.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x34; ir[1,at]:0xffffdaf2; ir[8,t0]:0x22346; ir[9,t1]:0x11d7; ir[10,t2]:0xffffdaf2; ir[11,t3]:0x455; ir[12,t4]:0x222; ir[13,t5]:0xfff; ir[14,t6]:0x22757; ir[15,t7]:0x13f7; ir[24,t8]:0xffffdfff; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_029.s b/tests/arch/mips/instructions/test_mips_instruction_029.s index 7103732ef..902d0f24d 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_029.s +++ b/tests/arch/mips/instructions/test_mips_instruction_029.s @@ -17,4 +17,5 @@ main: or $t6, $t0, $t3 or $t7, $t1, $t4 or $t8, $t2, $t5 - + + jr $ra diff --git a/tests/arch/mips/instructions/test_mips_instruction_030.out b/tests/arch/mips/instructions/test_mips_instruction_030.out deleted file mode 100644 index 282f5d001..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_030.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x34; ir[1,at]:0xffffdaf2; ir[8,t0]:0x22346; ir[9,t1]:0x11d7; ir[10,t2]:0xffffdaf2; ir[11,t3]:0x455; ir[12,t4]:0x222; ir[13,t5]:0xfff; ir[14,t6]:0x44; ir[15,t7]:0x2; ir[24,t8]:0xaf2; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_030.s b/tests/arch/mips/instructions/test_mips_instruction_030.s index 1eff71284..e349a870f 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_030.s +++ b/tests/arch/mips/instructions/test_mips_instruction_030.s @@ -17,3 +17,5 @@ main: and $t6, $t0, $t3 and $t7, $t1, $t4 and $t8, $t2, $t5 + + jr $ra diff --git a/tests/arch/mips/instructions/test_mips_instruction_031.out b/tests/arch/mips/instructions/test_mips_instruction_031.out deleted file mode 100644 index 78a74dbe1..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_031.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x58; ir[1,at]:0x200018; ir[2,v0]:0xa; ir[8,t0]:0x200000; ir[9,t1]:0x200008; ir[10,t2]:0x200010; ir[11,t3]:0x200028; sfpr[f0]:0x404145A1; sfpr[f1]:0xCAC08312; sfpr[f2]:0x4026E2D0; sfpr[f3]:0xE5604189; sfpr[f5]:0x07544FFB; dfpr[FP0]:0x404145A1CAC08312; dfpr[FP2]:0x4026E2D0E5604189; dfpr[FP4]:0x0000000007544FFB; memory[0x20002f]:0xFB; memory[0x20002e]:0x4F; memory[0x20002d]:0x54; memory[0x20002c]:0x07; memory[0x200027]:0x89; memory[0x200026]:0x41; memory[0x200025]:0x60; memory[0x200024]:0xE5; memory[0x200023]:0xD0; memory[0x200022]:0xE2; memory[0x200021]:0x26; memory[0x200020]:0x40; memory[0x20001f]:0x12; memory[0x20001e]:0x83; memory[0x20001d]:0xC0; memory[0x20001c]:0xCA; memory[0x20001b]:0xA1; memory[0x20001a]:0x45; memory[0x200019]:0x41; memory[0x200018]:0x40; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_031.s b/tests/arch/mips/instructions/test_mips_instruction_031.s index e3711dbf8..2e7845123 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_031.s +++ b/tests/arch/mips/instructions/test_mips_instruction_031.s @@ -6,7 +6,7 @@ .data a: .double 34.544 b: .double 11.443 - c: .double 0x7544FFB + c: .doubleword 0x7544FFB d: .space 24 diff --git a/tests/arch/mips/instructions/test_mips_instruction_032.out b/tests/arch/mips/instructions/test_mips_instruction_032.out deleted file mode 100644 index 29b9f23e2..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_032.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x28; ir[1,at]:0xfffffffe; ir[8,t0]:0xa; ir[9,t1]:0xd; ir[10,t2]:0x2d; ir[11,t3]:0xfffffffe; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_032.s b/tests/arch/mips/instructions/test_mips_instruction_032.s index 5e8f65179..9942922c6 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_032.s +++ b/tests/arch/mips/instructions/test_mips_instruction_032.s @@ -12,6 +12,14 @@ main: li $t3, -2 mult $t0, $t1 + mfhi $s0 + mflo $s1 mult $t1, $t2 + mfhi $s2 + mflo $s3 mult $t2, $t3 + mfhi $s4 + mflo $s5 mult $t3, $t4 + + jr $ra diff --git a/tests/arch/mips/instructions/test_mips_instruction_033.out b/tests/arch/mips/instructions/test_mips_instruction_033.out deleted file mode 100644 index c870908e4..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_033.out +++ /dev/null @@ -1,13 +0,0 @@ - - -[E13] Error: Main label `main` not found - ╭─[ assembly:1:1 ] - │ - 1 │ - │ │ - │ ╰─ Consider adding a label called `main` to an instruction -───╯ - -Not executed -keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_033.s b/tests/arch/mips/instructions/test_mips_instruction_033.s deleted file mode 100644 index ada9fda11..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_033.s +++ /dev/null @@ -1,15 +0,0 @@ - -# -# Creator (https://creatorsim.github.io/creator/) -# - -#.text -#main: - -# li x5, 0xAAD4 -# li x6, 4567 -# li x7, -9486 - -# srli x8, x5, 2 -# srli x9, x6, 1 -# srli x10, x7, 15 diff --git a/tests/arch/mips/instructions/test_mips_instruction_034.out b/tests/arch/mips/instructions/test_mips_instruction_034.out deleted file mode 100644 index 3d1493dfd..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_034.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x28; ir[1,at]:0xfffffffe; ir[8,t0]:0xa; ir[9,t1]:0xd; ir[10,t2]:0x2d; ir[11,t3]:0xfffffffe; ir[12,t4]:0x82; ir[13,t5]:0x249; ir[14,t6]:0xffffffa6; ir[15,t7]:0xfffffefc; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_034.s b/tests/arch/mips/instructions/test_mips_instruction_034.s index 51ac2b04b..d5b1a9d77 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_034.s +++ b/tests/arch/mips/instructions/test_mips_instruction_034.s @@ -15,3 +15,5 @@ main: mul $t5, $t1, $t2 mul $t6, $t2, $t3 mul $t7, $t3, $t4 + + jr $ra diff --git a/tests/arch/mips/instructions/test_mips_instruction_035.out b/tests/arch/mips/instructions/test_mips_instruction_035.out deleted file mode 100644 index 89adf5106..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_035.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x38; ir[1,at]:0xfe9a113d; ir[8,t0]:0x165eeb8; ir[9,t1]:0xde; ir[10,t2]:0xfabb53; ir[11,t3]:0xfe9a113d; ir[12,t4]:0x165ef96; ir[13,t5]:0xfabc31; ir[14,t6]:0xff94cc90; ir[15,t7]:0xfffffff5; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_035.s b/tests/arch/mips/instructions/test_mips_instruction_035.s index 585021ab5..8b830b444 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_035.s +++ b/tests/arch/mips/instructions/test_mips_instruction_035.s @@ -13,4 +13,6 @@ main: addu $t4, $t0, $t1 addu $t5, $t1, $t2 addu $t6, $t2, $t3 - addu $t7, $t3, $t0 \ No newline at end of file + addu $t7, $t3, $t0 + + jr $ra diff --git a/tests/arch/mips/instructions/test_mips_instruction_036.out b/tests/arch/mips/instructions/test_mips_instruction_036.out deleted file mode 100644 index d3566d4b6..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_036.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x30; ir[1,at]:0x37183; ir[8,t0]:0x25b8; ir[9,t1]:0xde; ir[10,t2]:0x123; ir[11,t3]:0xffffa912; ir[12,t4]:0xffffd8f0; ir[13,t5]:0x16c9; ir[14,t6]:0x247; ir[15,t7]:0x31a95; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_036.s b/tests/arch/mips/instructions/test_mips_instruction_036.s index a6b52a812..679e8290b 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_036.s +++ b/tests/arch/mips/instructions/test_mips_instruction_036.s @@ -13,4 +13,6 @@ main: addiu $t4, $t0, -19656 addiu $t5, $t1, 5611 addiu $t6, $t2, 0x124 - addiu $t7, $t3, 225667 \ No newline at end of file + addiu $t7, $t3, 225667 + + jr $ra diff --git a/tests/arch/mips/instructions/test_mips_instruction_037.out b/tests/arch/mips/instructions/test_mips_instruction_037.out deleted file mode 100644 index c870908e4..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_037.out +++ /dev/null @@ -1,13 +0,0 @@ - - -[E13] Error: Main label `main` not found - ╭─[ assembly:1:1 ] - │ - 1 │ - │ │ - │ ╰─ Consider adding a label called `main` to an instruction -───╯ - -Not executed -keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_037.s b/tests/arch/mips/instructions/test_mips_instruction_037.s index 514137a05..42b9e0a54 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_037.s +++ b/tests/arch/mips/instructions/test_mips_instruction_037.s @@ -4,15 +4,23 @@ # -# .text -# main: +.text +main: -# li x5, 10 -# li x6, 13 -# li x7, 45 -# li x8, -2 + li $t0, 10 + li $t1, 13 + li $t2, 45 + li $t3, -2 -# mulhu x9, x5, x6 -# mulhu x10, x6, x7 -# mulhu x11, x7, x8 -# mulhu x12, x8, x5 + multu $t0, $t1 + mfhi $s0 + mflo $s1 + multu $t1, $t2 + mfhi $s2 + mflo $s3 + multu $t2, $t3 + mfhi $s4 + mflo $s5 + multu $t3, $t4 + + jr $ra diff --git a/tests/arch/mips/instructions/test_mips_instruction_038.out b/tests/arch/mips/instructions/test_mips_instruction_038.out deleted file mode 100644 index be16b5c16..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_038.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x28; ir[1,at]:0xffffe000; ir[8,t0]:0x10; ir[9,t1]:0x100; ir[10,t2]:0xffffe000; ir[11,t3]:0x18; ir[12,t4]:0xfffffe00; ir[13,t5]:0x10; ir[14,t6]:0xfffffeab; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_038.s b/tests/arch/mips/instructions/test_mips_instruction_038.s index dc9c8cc58..3169e8611 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_038.s +++ b/tests/arch/mips/instructions/test_mips_instruction_038.s @@ -15,3 +15,5 @@ main: div $t5, $t1, $t0 div $t6, $t2, $t3 div $t7, $t3, $t2 + + jr $ra diff --git a/tests/arch/mips/instructions/test_mips_instruction_039.out b/tests/arch/mips/instructions/test_mips_instruction_039.out deleted file mode 100644 index a35e0b6db..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_039.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x28; ir[1,at]:0xffffe000; ir[8,t0]:0x10; ir[9,t1]:0x100; ir[10,t2]:0xffffe000; ir[11,t3]:0x18; ir[12,t4]:0xffffe00; ir[13,t5]:0x10; ir[14,t6]:0xaaaa955; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_039.s b/tests/arch/mips/instructions/test_mips_instruction_039.s index d4e7ab5ea..842f86225 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_039.s +++ b/tests/arch/mips/instructions/test_mips_instruction_039.s @@ -15,3 +15,5 @@ main: divu $t5, $t1, $t0 divu $t6, $t2, $t3 divu $t7, $t3, $t2 + + jr $ra diff --git a/tests/arch/mips/instructions/test_mips_instruction_040.out b/tests/arch/mips/instructions/test_mips_instruction_040.out deleted file mode 100644 index f06e30407..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_040.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x38; cr[HI]:0x18; ir[1,at]:0xffffe000; ir[8,t0]:0x10; ir[9,t1]:0x100; ir[10,t2]:0xffffe000; ir[11,t3]:0x18; ir[14,t6]:0xfffffff8; ir[15,t7]:0x18; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_040.s b/tests/arch/mips/instructions/test_mips_instruction_040.s index 84ec0633a..d7ef0043e 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_040.s +++ b/tests/arch/mips/instructions/test_mips_instruction_040.s @@ -15,3 +15,5 @@ main: rem $t5, $t1, $t0 rem $t6, $t2, $t3 rem $t7, $t3, $t2 + + jr $ra diff --git a/tests/arch/mips/instructions/test_mips_instruction_041.out b/tests/arch/mips/instructions/test_mips_instruction_041.out deleted file mode 100644 index 843277c82..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_041.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x28; ir[1,at]:0xffffe000; ir[8,t0]:0x10; ir[9,t1]:0x100; ir[10,t2]:0xffffe000; ir[11,t3]:0x18; ir[14,t6]:0x8; ir[15,t7]:0x18; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_041.s b/tests/arch/mips/instructions/test_mips_instruction_041.s index e55c978bd..01653bac7 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_041.s +++ b/tests/arch/mips/instructions/test_mips_instruction_041.s @@ -15,3 +15,5 @@ main: modu $t5, $t1, $t0 modu $t6, $t2, $t3 modu $t7, $t3, $t2 + + jr $ra diff --git a/tests/arch/mips/instructions/test_mips_instruction_042.out b/tests/arch/mips/instructions/test_mips_instruction_042.out deleted file mode 100644 index dd2ef2a4d..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_042.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x2c; ir[1,at]:0x1; ir[2,v0]:0xa; ir[8,t0]:0x372; ir[9,t1]:0x371; ir[10,t2]:0x5; ir[11,t3]:0x21f; ir[12,t4]:0xb; ir[13,t5]:0x22b; ir[14,t6]:0x22; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_043.out b/tests/arch/mips/instructions/test_mips_instruction_043.out deleted file mode 100644 index 22cb038ed..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_043.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x3c; ir[1,at]:0x1; ir[2,v0]:0xa; ir[8,t0]:0xfffffc8e; ir[9,t1]:0xfffffc8f; ir[10,t2]:0x5; ir[11,t3]:0x21f; ir[12,t4]:0xb; ir[13,t5]:0x22b; ir[14,t6]:0x22; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_044.out b/tests/arch/mips/instructions/test_mips_instruction_044.out deleted file mode 100644 index a92e51337..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_044.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x2c; ir[2,v0]:0xa; ir[8,t0]:0x372; ir[9,t1]:0x371; ir[10,t2]:0x5; ir[11,t3]:0x21f; ir[12,t4]:0xb; ir[13,t5]:0x22b; ir[14,t6]:0x22; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_045.out b/tests/arch/mips/instructions/test_mips_instruction_045.out deleted file mode 100644 index b266a7736..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_045.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x44; ir[2,v0]:0xa; ir[8,t0]:0xfffffc8e; ir[9,t1]:0xfffffc8f; ir[10,t2]:0x5; ir[11,t3]:0xfffffde1; ir[12,t4]:0xb; ir[13,t5]:0xfffffdd5; ir[14,t6]:0x22; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_046.out b/tests/arch/mips/instructions/test_mips_instruction_046.out deleted file mode 100644 index 6a9a67d65..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_046.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x28; ir[1,at]:0xffffdaf2; ir[8,t0]:0x22346; ir[9,t1]:0x11d7; ir[10,t2]:0xffffdaf2; ir[11,t3]:0xfffdcc28; ir[12,t4]:0x2408; ir[13,t5]:0x409; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_046.s b/tests/arch/mips/instructions/test_mips_instruction_046.s index 0113ca325..f020ca3a9 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_046.s +++ b/tests/arch/mips/instructions/test_mips_instruction_046.s @@ -12,5 +12,6 @@ main: nor $t3, $t0, $t1 nor $t4, $t1, $t2 - nor $t5, $t2, $t0 - + nor $t5, $t2, $t0 + + jr $ra diff --git a/tests/arch/mips/instructions/test_mips_instruction_047.out b/tests/arch/mips/instructions/test_mips_instruction_047.out deleted file mode 100644 index 03210c2f7..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_047.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x20; ir[1,at]:0xffffdaf2; ir[8,t0]:0x22346; ir[9,t1]:0x11d7; ir[10,t2]:0xffffdaf2; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_047.s b/tests/arch/mips/instructions/test_mips_instruction_047.s index 2259bebe2..af3df45d2 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_047.s +++ b/tests/arch/mips/instructions/test_mips_instruction_047.s @@ -10,3 +10,5 @@ main: li $t1, 4567 nop li $t2, -9486 + + jr $ra diff --git a/tests/arch/mips/instructions/test_mips_instruction_048.out b/tests/arch/mips/instructions/test_mips_instruction_048.out deleted file mode 100644 index 3ec14dc7d..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_048.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x28; ir[1,at]:0xffffffff; ir[8,t0]:0x1; ir[9,t1]:0x234235; ir[10,t2]:0xffffffff; ir[11,t3]:0x1; ir[12,t4]:0x234235; ir[13,t5]:0xffffffff; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_048.s b/tests/arch/mips/instructions/test_mips_instruction_048.s index cdc87be7c..709205b4f 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_048.s +++ b/tests/arch/mips/instructions/test_mips_instruction_048.s @@ -13,3 +13,5 @@ main: move $t3, $t0 move $t4, $t1 move $t5, $t2 + + jr $ra diff --git a/tests/arch/mips/instructions/test_mips_instruction_049.out b/tests/arch/mips/instructions/test_mips_instruction_049.out deleted file mode 100644 index e59e3b9d2..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_049.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x28; cr[HI]:0x234566; cr[LO]:0xfff8e0ca; ir[1,at]:0xfff8e0ca; ir[8,t0]:0x234566; ir[9,t1]:0xfff8e0ca; ir[11,t3]:0x234566; ir[12,t4]:0xfff8e0ca; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_049.s b/tests/arch/mips/instructions/test_mips_instruction_049.s index 3459ab9a6..381e5f6d8 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_049.s +++ b/tests/arch/mips/instructions/test_mips_instruction_049.s @@ -14,3 +14,5 @@ main: mfhi $t3 mflo $t4 + + jr $ra diff --git a/tests/arch/mips/instructions/test_mips_instruction_050.out b/tests/arch/mips/instructions/test_mips_instruction_050.out deleted file mode 100644 index bacd4ab5c..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_050.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x2c; ir[1,at]:0x123515; ir[8,t0]:0x223; ir[9,t1]:0xfffffc57; ir[10,t2]:0xc; ir[11,t3]:0x123515; ir[12,t4]:0x5cc; ir[13,t5]:0xfffffa40; ir[14,t6]:0x123ad5; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_050.s b/tests/arch/mips/instructions/test_mips_instruction_050.s index 66b43ed49..03b97fa23 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_050.s +++ b/tests/arch/mips/instructions/test_mips_instruction_050.s @@ -14,3 +14,5 @@ main: subu $t4, $t0, $t1 subu $t5, $t2, $t4 subu $t6, $t3, $t5 + + jr $ra diff --git a/tests/arch/mips/instructions/test_mips_instruction_051.out b/tests/arch/mips/instructions/test_mips_instruction_051.out deleted file mode 100644 index 1336a995d..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_051.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x2c; ir[1,at]:0xffffffff; ir[2,v0]:0xa; ir[8,t0]:0x1; ir[10,t2]:0xffffffff; ir[14,t6]:0x22; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_051.s b/tests/arch/mips/instructions/test_mips_instruction_051.s index 7cc2e4ec8..061fd3373 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_051.s +++ b/tests/arch/mips/instructions/test_mips_instruction_051.s @@ -8,8 +8,6 @@ li $t0, 1 li $t1, 0 li $t2, -1 - beqz $t0, jump1 - beqz $t2, jump1 beqz $t1, jump1 jump2: diff --git a/tests/arch/mips/instructions/test_mips_instruction_052.out b/tests/arch/mips/instructions/test_mips_instruction_052.out deleted file mode 100644 index be4fabf45..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_052.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x1c; ir[2,v0]:0xa; ir[8,t0]:0x1; ir[12,t4]:0x2; ir[14,t6]:0x22; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_053.out b/tests/arch/mips/instructions/test_mips_instruction_053.out deleted file mode 100644 index 4c699ccf1..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_053.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x1c; ir[2,v0]:0xa; ir[8,t0]:0x1; ir[12,t4]:0x2; ir[14,t6]:0x22; ir[31,ra]:0x24; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_054.out b/tests/arch/mips/instructions/test_mips_instruction_054.out deleted file mode 100644 index be4fabf45..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_054.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x1c; ir[2,v0]:0xa; ir[8,t0]:0x1; ir[12,t4]:0x2; ir[14,t6]:0x22; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_055.out b/tests/arch/mips/instructions/test_mips_instruction_055.out deleted file mode 100644 index 9ab7de936..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_055.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x24; ir[1,at]:0xffffffff; ir[2,v0]:0xa; ir[8,t0]:0x1; ir[9,t1]:0xffffffff; ir[14,t6]:0x22; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_056.out b/tests/arch/mips/instructions/test_mips_instruction_056.out deleted file mode 100644 index ab3d78d7e..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_056.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x28; ir[1,at]:0x1; ir[2,v0]:0xa; ir[8,t0]:0x372; ir[9,t1]:0x371; ir[10,t2]:0x21f; ir[12,t4]:0xb; ir[13,t5]:0x22b; ir[14,t6]:0x22; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_057.out b/tests/arch/mips/instructions/test_mips_instruction_057.out deleted file mode 100644 index f8a21d08b..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_057.out +++ /dev/null @@ -1,12 +0,0 @@ - - -Error at line 11 (11): -Syntax error near line: 11 - - 10 li $t2, 0xAAB -->11 bnez $t0, $t2, jump1 - 12 bnez $t0, $t1, jump1 - -Not executed -keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_057.s b/tests/arch/mips/instructions/test_mips_instruction_057.s index 6a807ed58..8ecbe5dd5 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_057.s +++ b/tests/arch/mips/instructions/test_mips_instruction_057.s @@ -5,11 +5,10 @@ .text main: - li $t0, 0xAAB - li $t1, 0xBBA - li $t2, 0xAAB - bnez $t0, $t2, jump1 - bnez $t0, $t1, jump1 + li $t0, 1 + li $t1, 0 + li $t2, -1 + bnez $t0, jump1 jump2: li $t6, 34 @@ -19,4 +18,4 @@ jump1: li $t4, 235363 li $t5, 0xAA - bnez $t4, $t5, jump2 + bnez $t4, jump2 diff --git a/tests/arch/mips/instructions/test_mips_instruction_058.out b/tests/arch/mips/instructions/test_mips_instruction_058.out deleted file mode 100644 index cbf66af21..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_058.out +++ /dev/null @@ -1,5 +0,0 @@ - -Square root of a negative number is not allowed. -Square root of a negative number is not allowed. -cr[PC]:0x8c; ir[1,at]:0x46100000; ir[2,v0]:0xa; sfpr[f0]:0x40700000; sfpr[f2]:0xC0AB3200; sfpr[f4]:0x40B56400; sfpr[f6]:0x46192400; sfpr[f7]:0xC6016400; sfpr[f8]:0x46100000; sfpr[f10]:0x40300000; sfpr[f14]:0x40528000; sfpr[f16]:0x42C60000; sfpr[f18]:0x42C00000; dfpr[FP0]:0x4070000000000000; dfpr[FP2]:0xC0AB320000000000; dfpr[FP4]:0x40B5640000000000; dfpr[FP6]:0x46192400C6016400; dfpr[FP8]:0x4610000000000000; dfpr[FP10]:0x4030000000000000; dfpr[FP14]:0x4052800000000000; dfpr[FP16]:0x42C6000000000000; dfpr[FP18]:0x42C0000000000000; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_059.out b/tests/arch/mips/instructions/test_mips_instruction_059.out deleted file mode 100644 index 3f3b26876..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_059.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x8c; ir[1,at]:0x46100000; ir[2,v0]:0xa; sfpr[f0]:0x40700000; sfpr[f2]:0x40AB3200; sfpr[f4]:0x40B56400; sfpr[f6]:0x46192400; sfpr[f7]:0x46016400; sfpr[f8]:0x46100000; sfpr[f10]:0x40800000; sfpr[f12]:0x40BB3200; sfpr[f14]:0x40C56400; sfpr[f16]:0x46992400; sfpr[f17]:0x46816400; sfpr[f18]:0x46900000; dfpr[FP0]:0x4070000000000000; dfpr[FP2]:0x40AB320000000000; dfpr[FP4]:0x40B5640000000000; dfpr[FP6]:0x4619240046016400; dfpr[FP8]:0x4610000000000000; dfpr[FP10]:0x4080000000000000; dfpr[FP12]:0x40BB320000000000; dfpr[FP14]:0x40C5640000000000; dfpr[FP16]:0x4699240046816400; dfpr[FP18]:0x4690000000000000; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_060.out b/tests/arch/mips/instructions/test_mips_instruction_060.out deleted file mode 100644 index a0233e6a7..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_060.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x8c; ir[1,at]:0x46100000; ir[2,v0]:0xa; sfpr[f0]:0x40700000; sfpr[f2]:0x40AB3200; sfpr[f4]:0x40B56400; sfpr[f6]:0x46192400; sfpr[f7]:0x46016400; sfpr[f8]:0x46100000; sfpr[f10]:0xC0A93200; sfpr[f12]:0xC09F2C00; sfpr[f14]:0x40B46400; sfpr[f16]:0x44BE0000; sfpr[f17]:0xC469C000; sfpr[f18]:0xC4124000; dfpr[FP0]:0x4070000000000000; dfpr[FP2]:0x40AB320000000000; dfpr[FP4]:0x40B5640000000000; dfpr[FP6]:0x4619240046016400; dfpr[FP8]:0x4610000000000000; dfpr[FP10]:0xC0A9320000000000; dfpr[FP12]:0xC09F2C0000000000; dfpr[FP14]:0x40B4640000000000; dfpr[FP16]:0x44BE0000C469C000; dfpr[FP18]:0xC412400000000000; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_061.out b/tests/arch/mips/instructions/test_mips_instruction_061.out deleted file mode 100644 index ef763a1af..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_061.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x8c; ir[1,at]:0xc6100000; ir[2,v0]:0xa; sfpr[f0]:0x40700000; sfpr[f2]:0xC0AB3200; sfpr[f4]:0x40B56400; sfpr[f6]:0xC6192400; sfpr[f7]:0x46016400; sfpr[f8]:0xC6100000; sfpr[f10]:0x40700000; sfpr[f12]:0x40AB3200; sfpr[f14]:0x40B56400; sfpr[f16]:0x46192400; sfpr[f17]:0x46016400; sfpr[f18]:0x46100000; dfpr[FP0]:0x4070000000000000; dfpr[FP2]:0xC0AB320000000000; dfpr[FP4]:0x40B5640000000000; dfpr[FP6]:0xC619240046016400; dfpr[FP8]:0xC610000000000000; dfpr[FP10]:0x4070000000000000; dfpr[FP12]:0x40AB320000000000; dfpr[FP14]:0x40B5640000000000; dfpr[FP16]:0x4619240046016400; dfpr[FP18]:0x4610000000000000; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_062.out b/tests/arch/mips/instructions/test_mips_instruction_062.out deleted file mode 100644 index 1876723f8..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_062.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x8c; ir[1,at]:0xc4000000; ir[2,v0]:0xa; sfpr[f0]:0x40700000; sfpr[f2]:0xC0B00000; sfpr[f4]:0x40080000; sfpr[f6]:0xC3960000; sfpr[f7]:0x40A00000; sfpr[f8]:0xC4000000; sfpr[f10]:0xC1300000; sfpr[f12]:0xC0C80000; sfpr[f14]:0x40880000; sfpr[f16]:0xC4BB8000; sfpr[f17]:0xC5200000; sfpr[f18]:0x48160000; dfpr[FP0]:0x4070000000000000; dfpr[FP2]:0xC0B0000000000000; dfpr[FP4]:0x4008000000000000; dfpr[FP6]:0xC396000040A00000; dfpr[FP8]:0xC400000000000000; dfpr[FP10]:0xC130000000000000; dfpr[FP12]:0xC0C8000000000000; dfpr[FP14]:0x4088000000000000; dfpr[FP16]:0xC4BB8000C5200000; dfpr[FP18]:0x4816000000000000; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_063.out b/tests/arch/mips/instructions/test_mips_instruction_063.out deleted file mode 100644 index 2f61c3d3e..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_063.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x8c; ir[1,at]:0xc4000000; ir[2,v0]:0xa; sfpr[f0]:0x40700000; sfpr[f2]:0xC0B00000; sfpr[f4]:0x40080000; sfpr[f6]:0xC3960000; sfpr[f7]:0x40A00000; sfpr[f8]:0xC4000000; sfpr[f10]:0xBFB00000; sfpr[f12]:0xC0955555; sfpr[f13]:0x55555555; sfpr[f14]:0x40555555; sfpr[f15]:0x55555555; sfpr[f16]:0xC2700000; sfpr[f17]:0xBC200000; sfpr[f18]:0x3FDA740E; dfpr[FP0]:0x4070000000000000; dfpr[FP2]:0xC0B0000000000000; dfpr[FP4]:0x4008000000000000; dfpr[FP6]:0xC396000040A00000; dfpr[FP8]:0xC400000000000000; dfpr[FP10]:0xBFB0000000000000; dfpr[FP12]:0xC095555555555555; dfpr[FP14]:0x4055555555555555; dfpr[FP16]:0xC2700000BC200000; dfpr[FP18]:0x3FDA740E00000000; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_064.out b/tests/arch/mips/instructions/test_mips_instruction_064.out deleted file mode 100644 index 88b64bde0..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_064.out +++ /dev/null @@ -1,5 +0,0 @@ - -Square root of a negative number is not allowed. -Square root of a negative number is not allowed. -cr[PC]:0x8c; ir[1,at]:0x46100000; ir[2,v0]:0xa; sfpr[f0]:0x40700000; sfpr[f2]:0xC0AB3200; sfpr[f4]:0x40B56400; sfpr[f6]:0x46192400; sfpr[f7]:0xC6016400; sfpr[f8]:0x46100000; sfpr[f10]:0x3FB00000; sfpr[f14]:0x3F8BACF9; sfpr[f15]:0x14C1BAD0; sfpr[f16]:0x3C257EB5; sfpr[f18]:0x3C2AAAAB; dfpr[FP0]:0x4070000000000000; dfpr[FP2]:0xC0AB320000000000; dfpr[FP4]:0x40B5640000000000; dfpr[FP6]:0x46192400C6016400; dfpr[FP8]:0x4610000000000000; dfpr[FP10]:0x3FB0000000000000; dfpr[FP14]:0x3F8BACF914C1BAD0; dfpr[FP16]:0x3C257EB500000000; dfpr[FP18]:0x3C2AAAAB00000000; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_065.out b/tests/arch/mips/instructions/test_mips_instruction_065.out deleted file mode 100644 index f5851cade..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_065.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x7c; ir[1,at]:0x46100000; ir[2,v0]:0xa; sfpr[f0]:0x40700000; sfpr[f4]:0x40B56400; sfpr[f6]:0x46192400; sfpr[f7]:0xC6016400; sfpr[f8]:0x46100000; sfpr[f10]:0x40C32480; dfpr[FP0]:0x4070000000000000; dfpr[FP4]:0x40B5640000000000; dfpr[FP6]:0x46192400C6016400; dfpr[FP8]:0x4610000000000000; dfpr[FP10]:0x40C3248000000000; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_066.out b/tests/arch/mips/instructions/test_mips_instruction_066.out deleted file mode 100644 index aa4e53991..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_066.out +++ /dev/null @@ -1,13 +0,0 @@ - - -[E05] Error: Register `t0` isn't defined in file type `DoubleFloatingPoint` - ╭─[ assembly:15:14 ] - │ - 15 │ cvt.w.d $t0, $FP0 - │ ─┬ - │ ╰── Unknown register -────╯ - -Not executed -keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/instructions/test_mips_instruction_067.out b/tests/arch/mips/instructions/test_mips_instruction_067.out deleted file mode 100644 index 6b18c9b6f..000000000 --- a/tests/arch/mips/instructions/test_mips_instruction_067.out +++ /dev/null @@ -1,13 +0,0 @@ - - -[E05] Error: Register `t0` isn't defined in file type `DoubleFloatingPoint` - ╭─[ assembly:17:20 ] - │ - 17 │ cvt.d.w $FP0, $t0 - │ ─┬ - │ ╰── Unknown register -────╯ - -Not executed -keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/sentinel/test_mips_sentinels_001.out b/tests/arch/mips/sentinel/test_mips_sentinels_001.out deleted file mode 100644 index bb418b996..000000000 --- a/tests/arch/mips/sentinel/test_mips_sentinels_001.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x10; ir[1,at]:0xc; ir[2,v0]:0xa; ir[4,a0]:0x2; ir[31,ra]:0x8; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/sentinel/test_mips_sentinels_002.out b/tests/arch/mips/sentinel/test_mips_sentinels_002.out deleted file mode 100644 index f46867bca..000000000 --- a/tests/arch/mips/sentinel/test_mips_sentinels_002.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x10; ir[1,at]:0xc; ir[2,v0]:0xa; ir[5,a1]:0x2; ir[31,ra]:0x8; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/sentinel/test_mips_sentinels_003.out b/tests/arch/mips/sentinel/test_mips_sentinels_003.out deleted file mode 100644 index c14ee77a8..000000000 --- a/tests/arch/mips/sentinel/test_mips_sentinels_003.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x10; ir[1,at]:0xc; ir[2,v0]:0xa; ir[6,a2]:0x2; ir[31,ra]:0x8; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/sentinel/test_mips_sentinels_004.out b/tests/arch/mips/sentinel/test_mips_sentinels_004.out deleted file mode 100644 index 50539f39a..000000000 --- a/tests/arch/mips/sentinel/test_mips_sentinels_004.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x10; ir[1,at]:0xc; ir[2,v0]:0xa; ir[7,a3]:0x2; ir[31,ra]:0x8; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/sentinel/test_mips_sentinels_005.out b/tests/arch/mips/sentinel/test_mips_sentinels_005.out deleted file mode 100644 index a0f0cd1bc..000000000 --- a/tests/arch/mips/sentinel/test_mips_sentinels_005.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x10; ir[2,v0]:0xa; ir[30,fp]:0x5; ir[31,ra]:0x8; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/sentinel/test_mips_sentinels_006.out b/tests/arch/mips/sentinel/test_mips_sentinels_006.out deleted file mode 100644 index 3d1295729..000000000 --- a/tests/arch/mips/sentinel/test_mips_sentinels_006.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x10; ir[2,v0]:0xa; ir[28,gp]:0x5; ir[31,ra]:0x8; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/sentinel/test_mips_sentinels_007.out b/tests/arch/mips/sentinel/test_mips_sentinels_007.out deleted file mode 100644 index dd69094bb..000000000 --- a/tests/arch/mips/sentinel/test_mips_sentinels_007.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x10; ir[2,v0]:0xa; ir[26,k0]:0x5; ir[31,ra]:0x8; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/sentinel/test_mips_sentinels_008.out b/tests/arch/mips/sentinel/test_mips_sentinels_008.out deleted file mode 100644 index 4d9b823e3..000000000 --- a/tests/arch/mips/sentinel/test_mips_sentinels_008.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x10; ir[2,v0]:0xa; ir[27,k1]:0x5; ir[31,ra]:0x8; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/sentinel/test_mips_sentinels_009.out b/tests/arch/mips/sentinel/test_mips_sentinels_009.out deleted file mode 100644 index 879dd5bc9..000000000 --- a/tests/arch/mips/sentinel/test_mips_sentinels_009.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x108a; ir[31,ra]:0x108a; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/sentinel/test_mips_sentinels_010.out b/tests/arch/mips/sentinel/test_mips_sentinels_010.out deleted file mode 100644 index 18774653c..000000000 --- a/tests/arch/mips/sentinel/test_mips_sentinels_010.out +++ /dev/null @@ -1,4 +0,0 @@ - -DANGER: Possible failure in the parameter passing convention -cr[PC]:0x10; ir[1,at]:0xc; ir[2,v0]:0xa; ir[16,s0]:0x2; ir[31,ra]:0x8; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/sentinel/test_mips_sentinels_011.out b/tests/arch/mips/sentinel/test_mips_sentinels_011.out deleted file mode 100644 index b51ae811a..000000000 --- a/tests/arch/mips/sentinel/test_mips_sentinels_011.out +++ /dev/null @@ -1,4 +0,0 @@ - -DANGER: Possible failure in the parameter passing convention -cr[PC]:0x10; ir[1,at]:0xc; ir[2,v0]:0xa; ir[17,s1]:0x2; ir[31,ra]:0x8; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/sentinel/test_mips_sentinels_012.out b/tests/arch/mips/sentinel/test_mips_sentinels_012.out deleted file mode 100644 index 506c4585a..000000000 --- a/tests/arch/mips/sentinel/test_mips_sentinels_012.out +++ /dev/null @@ -1,4 +0,0 @@ - -DANGER: Possible failure in the parameter passing convention -cr[PC]:0x10; ir[1,at]:0xc; ir[2,v0]:0xa; ir[18,s2]:0x2; ir[31,ra]:0x8; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/sentinel/test_mips_sentinels_013.out b/tests/arch/mips/sentinel/test_mips_sentinels_013.out deleted file mode 100644 index 3b40f66be..000000000 --- a/tests/arch/mips/sentinel/test_mips_sentinels_013.out +++ /dev/null @@ -1,4 +0,0 @@ - -DANGER: Possible failure in the parameter passing convention -cr[PC]:0x10; ir[1,at]:0xc; ir[2,v0]:0xa; ir[19,s3]:0x2; ir[31,ra]:0x8; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/sentinel/test_mips_sentinels_014.out b/tests/arch/mips/sentinel/test_mips_sentinels_014.out deleted file mode 100644 index 69ae1d83e..000000000 --- a/tests/arch/mips/sentinel/test_mips_sentinels_014.out +++ /dev/null @@ -1,4 +0,0 @@ - -DANGER: Possible failure in the parameter passing convention -cr[PC]:0x10; ir[1,at]:0xc; ir[2,v0]:0xa; ir[20,s4]:0x2; ir[31,ra]:0x8; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/sentinel/test_mips_sentinels_015.out b/tests/arch/mips/sentinel/test_mips_sentinels_015.out deleted file mode 100644 index 21e24116b..000000000 --- a/tests/arch/mips/sentinel/test_mips_sentinels_015.out +++ /dev/null @@ -1,4 +0,0 @@ - -DANGER: Possible failure in the parameter passing convention -cr[PC]:0x10; ir[1,at]:0xc; ir[2,v0]:0xa; ir[21,s5]:0x2; ir[31,ra]:0x8; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/sentinel/test_mips_sentinels_015.s b/tests/arch/mips/sentinel/test_mips_sentinels_015.s index 8f58a2c70..3a645ca42 100644 --- a/tests/arch/mips/sentinel/test_mips_sentinels_015.s +++ b/tests/arch/mips/sentinel/test_mips_sentinels_015.s @@ -24,7 +24,7 @@ sw $fp, 4($sp) addu $fp, $sp, 4 - li $s5 2 + li $s5, 2 b_efs: lw $ra, 8($sp) lw $fp, 4($sp) diff --git a/tests/arch/mips/sentinel/test_mips_sentinels_016.out b/tests/arch/mips/sentinel/test_mips_sentinels_016.out deleted file mode 100644 index 04f024272..000000000 --- a/tests/arch/mips/sentinel/test_mips_sentinels_016.out +++ /dev/null @@ -1,4 +0,0 @@ - -DANGER: Possible failure in the parameter passing convention -cr[PC]:0x10; ir[1,at]:0xc; ir[2,v0]:0xa; ir[22,s6]:0x2; ir[31,ra]:0x8; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/sentinel/test_mips_sentinels_017.out b/tests/arch/mips/sentinel/test_mips_sentinels_017.out deleted file mode 100644 index 5ef9599fa..000000000 --- a/tests/arch/mips/sentinel/test_mips_sentinels_017.out +++ /dev/null @@ -1,4 +0,0 @@ - -DANGER: Possible failure in the parameter passing convention -cr[PC]:0x10; ir[1,at]:0xc; ir[2,v0]:0xa; ir[23,s7]:0x2; ir[31,ra]:0x8; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/sentinel/test_mips_sentinels_018.out b/tests/arch/mips/sentinel/test_mips_sentinels_018.out deleted file mode 100644 index d4255a064..000000000 --- a/tests/arch/mips/sentinel/test_mips_sentinels_018.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x10; ir[2,v0]:0xa; ir[29,sp]:0x9; ir[31,ra]:0x8; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/sentinel/test_mips_sentinels_018.s b/tests/arch/mips/sentinel/test_mips_sentinels_018.s index fd0689909..1e133a052 100644 --- a/tests/arch/mips/sentinel/test_mips_sentinels_018.s +++ b/tests/arch/mips/sentinel/test_mips_sentinels_018.s @@ -20,7 +20,7 @@ test: # crear "stack frame" para $ra, $fp y una variable local - addi $sp, 4 + addi $sp, $sp, 4 # return $v0 jr $ra diff --git a/tests/arch/mips/sentinel/test_mips_sentinels_019.out b/tests/arch/mips/sentinel/test_mips_sentinels_019.out deleted file mode 100644 index f4832849c..000000000 --- a/tests/arch/mips/sentinel/test_mips_sentinels_019.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x14; ir[1,at]:0xc; ir[2,v0]:0xa; ir[4,a0]:0x5; ir[8,t0]:0x2; ir[31,ra]:0xc; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/sentinel/test_mips_sentinels_020.out b/tests/arch/mips/sentinel/test_mips_sentinels_020.out deleted file mode 100644 index d09cc3282..000000000 --- a/tests/arch/mips/sentinel/test_mips_sentinels_020.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x14; ir[1,at]:0xc; ir[2,v0]:0xa; ir[4,a0]:0x5; ir[9,t1]:0x2; ir[31,ra]:0xc; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/sentinel/test_mips_sentinels_021.out b/tests/arch/mips/sentinel/test_mips_sentinels_021.out deleted file mode 100644 index 8ee1d8b05..000000000 --- a/tests/arch/mips/sentinel/test_mips_sentinels_021.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x14; ir[1,at]:0xc; ir[2,v0]:0xa; ir[4,a0]:0x5; ir[10,t2]:0x2; ir[31,ra]:0xc; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/sentinel/test_mips_sentinels_021.s b/tests/arch/mips/sentinel/test_mips_sentinels_021.s index 371362521..bda3fb15d 100644 --- a/tests/arch/mips/sentinel/test_mips_sentinels_021.s +++ b/tests/arch/mips/sentinel/test_mips_sentinels_021.s @@ -24,7 +24,7 @@ sw $fp, 4($sp) addu $fp, $sp, 4 - li $t2 2 + li $t2, 2 b_efs: lw $ra, 8($sp) lw $fp, 4($sp) diff --git a/tests/arch/mips/sentinel/test_mips_sentinels_022.out b/tests/arch/mips/sentinel/test_mips_sentinels_022.out deleted file mode 100644 index 6c9cac29a..000000000 --- a/tests/arch/mips/sentinel/test_mips_sentinels_022.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x14; ir[1,at]:0xc; ir[2,v0]:0xa; ir[4,a0]:0x5; ir[11,t3]:0x2; ir[31,ra]:0xc; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/sentinel/test_mips_sentinels_023.out b/tests/arch/mips/sentinel/test_mips_sentinels_023.out deleted file mode 100644 index 07c9e23dd..000000000 --- a/tests/arch/mips/sentinel/test_mips_sentinels_023.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x14; ir[1,at]:0xc; ir[2,v0]:0xa; ir[4,a0]:0x5; ir[12,t4]:0x2; ir[31,ra]:0xc; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/sentinel/test_mips_sentinels_024.out b/tests/arch/mips/sentinel/test_mips_sentinels_024.out deleted file mode 100644 index 9367e8993..000000000 --- a/tests/arch/mips/sentinel/test_mips_sentinels_024.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x14; ir[1,at]:0xc; ir[2,v0]:0xa; ir[4,a0]:0x5; ir[13,t5]:0x2; ir[31,ra]:0xc; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/sentinel/test_mips_sentinels_024.s b/tests/arch/mips/sentinel/test_mips_sentinels_024.s index 5bc180a83..514a5bff7 100644 --- a/tests/arch/mips/sentinel/test_mips_sentinels_024.s +++ b/tests/arch/mips/sentinel/test_mips_sentinels_024.s @@ -20,11 +20,11 @@ test: # crear "stack frame" para $ra, $fp y una variable local subu $sp, $sp, 12 - sw $ra 8($sp) - sw $fp 4($sp) + sw $ra, 8($sp) + sw $fp, 4($sp) addu $fp, $sp, 4 - li $t5 2 + li $t5, 2 b_efs: lw $ra, 8($sp) lw $fp, 4($sp) diff --git a/tests/arch/mips/sentinel/test_mips_sentinels_025.out b/tests/arch/mips/sentinel/test_mips_sentinels_025.out deleted file mode 100644 index 14fc5479d..000000000 --- a/tests/arch/mips/sentinel/test_mips_sentinels_025.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x14; ir[1,at]:0xc; ir[2,v0]:0xa; ir[4,a0]:0x5; ir[14,t6]:0x2; ir[31,ra]:0xc; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/sentinel/test_mips_sentinels_026.out b/tests/arch/mips/sentinel/test_mips_sentinels_026.out deleted file mode 100644 index f4b028484..000000000 --- a/tests/arch/mips/sentinel/test_mips_sentinels_026.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x14; ir[1,at]:0xc; ir[2,v0]:0xa; ir[4,a0]:0x5; ir[15,t7]:0x2; ir[31,ra]:0xc; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/sentinel/test_mips_sentinels_027.out b/tests/arch/mips/sentinel/test_mips_sentinels_027.out deleted file mode 100644 index 232c69474..000000000 --- a/tests/arch/mips/sentinel/test_mips_sentinels_027.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x14; ir[1,at]:0xc; ir[2,v0]:0xa; ir[4,a0]:0x5; ir[24,t8]:0x2; ir[31,ra]:0xc; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/sentinel/test_mips_sentinels_028.out b/tests/arch/mips/sentinel/test_mips_sentinels_028.out deleted file mode 100644 index 371ae21e2..000000000 --- a/tests/arch/mips/sentinel/test_mips_sentinels_028.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x14; ir[1,at]:0xc; ir[2,v0]:0xa; ir[4,a0]:0x5; ir[25,t9]:0x2; ir[31,ra]:0xc; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/sentinel/test_mips_sentinels_029.out b/tests/arch/mips/sentinel/test_mips_sentinels_029.out deleted file mode 100644 index 4d3db4da2..000000000 --- a/tests/arch/mips/sentinel/test_mips_sentinels_029.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x10; ir[1,at]:0xc; ir[2,v0]:0xa; ir[31,ra]:0x8; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/sentinel/test_mips_sentinels_030.out b/tests/arch/mips/sentinel/test_mips_sentinels_030.out deleted file mode 100644 index c8585a613..000000000 --- a/tests/arch/mips/sentinel/test_mips_sentinels_030.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x10; ir[1,at]:0xc; ir[2,v0]:0xa; ir[3,v1]:0x2; ir[31,ra]:0x8; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/sentinel/test_mips_sentinels_031.out b/tests/arch/mips/sentinel/test_mips_sentinels_031.out deleted file mode 100644 index 4ffae289d..000000000 --- a/tests/arch/mips/sentinel/test_mips_sentinels_031.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x10; ir[1,at]:0x8; ir[2,v0]:0xa; ir[16,s0]:0x2; ir[31,ra]:0x8; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/sentinel/test_mips_sentinels_031.s b/tests/arch/mips/sentinel/test_mips_sentinels_031.s index 3dbbf2ff2..edf1cd97d 100644 --- a/tests/arch/mips/sentinel/test_mips_sentinels_031.s +++ b/tests/arch/mips/sentinel/test_mips_sentinels_031.s @@ -20,11 +20,11 @@ test: # crear "stack frame" para $ra, $fp y una variable local subu $sp, $sp, 8 - sw $s0, ($sp) + sw $s0, 0($sp) li $s0, 2 - b_efs: lw $s0, ($sp) + b_efs: lw $s0, 0($sp) addu $sp, $sp, 8 diff --git a/tests/arch/mips/sentinel/test_mips_sentinels_032.out b/tests/arch/mips/sentinel/test_mips_sentinels_032.out deleted file mode 100644 index 513072789..000000000 --- a/tests/arch/mips/sentinel/test_mips_sentinels_032.out +++ /dev/null @@ -1,4 +0,0 @@ - -DANGER: Possible failure in the parameter passing convention -cr[PC]:0x10; ir[1,at]:0x4; ir[2,v0]:0xa; ir[16,s0]:0x5; ir[31,ra]:0x8; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/sentinel/test_mips_sentinels_032.s b/tests/arch/mips/sentinel/test_mips_sentinels_032.s index ed8cb2f3f..af0e8779e 100644 --- a/tests/arch/mips/sentinel/test_mips_sentinels_032.s +++ b/tests/arch/mips/sentinel/test_mips_sentinels_032.s @@ -20,7 +20,7 @@ test: # crear "stack frame" para $ra, $fp y una variable local subu $sp, $sp, 4 - sw $s0, ($sp) + sw $s0, 0($sp) li $s0, 5 diff --git a/tests/arch/mips/sentinel/test_mips_sentinels_033.out b/tests/arch/mips/sentinel/test_mips_sentinels_033.out deleted file mode 100644 index db4973b2b..000000000 --- a/tests/arch/mips/sentinel/test_mips_sentinels_033.out +++ /dev/null @@ -1,4 +0,0 @@ - -DANGER: Possible failure in the parameter passing convention -cr[PC]:0x10; ir[1,at]:0x8; ir[2,v0]:0xa; ir[31,ra]:0x8; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/sentinel/test_mips_sentinels_033.s b/tests/arch/mips/sentinel/test_mips_sentinels_033.s index 74c232e75..87391980c 100644 --- a/tests/arch/mips/sentinel/test_mips_sentinels_033.s +++ b/tests/arch/mips/sentinel/test_mips_sentinels_033.s @@ -19,8 +19,8 @@ test: # crear "stack frame" para $ra, $fp y una variable local - subu $sp, $sp 8 - sw $s0, ($sp) + subu $sp, $sp, 8 + sw $s0, 0($sp) li $s0, 2 diff --git a/tests/arch/mips/sentinel/test_mips_sentinels_034.out b/tests/arch/mips/sentinel/test_mips_sentinels_034.out deleted file mode 100644 index db4973b2b..000000000 --- a/tests/arch/mips/sentinel/test_mips_sentinels_034.out +++ /dev/null @@ -1,4 +0,0 @@ - -DANGER: Possible failure in the parameter passing convention -cr[PC]:0x10; ir[1,at]:0x8; ir[2,v0]:0xa; ir[31,ra]:0x8; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/sentinel/test_mips_sentinels_034.s b/tests/arch/mips/sentinel/test_mips_sentinels_034.s index 8d73bd065..a3cab173b 100644 --- a/tests/arch/mips/sentinel/test_mips_sentinels_034.s +++ b/tests/arch/mips/sentinel/test_mips_sentinels_034.s @@ -20,11 +20,11 @@ test: # crear "stack frame" para $ra, $fp y una variable local subu $sp, $sp, 8 - sw $s0, ($sp) + sw $s0, 0($sp) li $s0, 2 - b_efs: lh $s0, ($sp) + b_efs: lh $s0, 0($sp) addu $sp, $sp, 8 diff --git a/tests/arch/mips/sentinel/test_mips_sentinels_035.out b/tests/arch/mips/sentinel/test_mips_sentinels_035.out deleted file mode 100644 index db4973b2b..000000000 --- a/tests/arch/mips/sentinel/test_mips_sentinels_035.out +++ /dev/null @@ -1,4 +0,0 @@ - -DANGER: Possible failure in the parameter passing convention -cr[PC]:0x10; ir[1,at]:0x8; ir[2,v0]:0xa; ir[31,ra]:0x8; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/sentinel/test_mips_sentinels_035.s b/tests/arch/mips/sentinel/test_mips_sentinels_035.s index 932a9aa64..74cd18ec9 100644 --- a/tests/arch/mips/sentinel/test_mips_sentinels_035.s +++ b/tests/arch/mips/sentinel/test_mips_sentinels_035.s @@ -20,12 +20,12 @@ test: # crear "stack frame" para $ra, $fp y una variable local subu $sp, $sp, 8 - sw $s0, ($sp) - sw $t0, ($sp) + sw $s0, 0($sp) + sw $t0, 0($sp) li $s0, 2 - b_efs: lw $s0, ($sp) + b_efs: lw $s0, 0($sp) addu $sp, $sp, 8 diff --git a/tests/arch/riscv/correct/examples/test_riscv_example_001.out b/tests/arch/riscv/correct/examples/test_riscv_example_001.out deleted file mode 100644 index b813595e7..000000000 --- a/tests/arch/riscv/correct/examples/test_riscv_example_001.out +++ /dev/null @@ -1,5 +0,0 @@ - -12 -34 -cr[PC]:0xfffffffe; ir[x10,a0]:0x22; ir[x17,a7]:0x1; keyboard[0x0]:''; display[0x0]:'1234'; - diff --git a/tests/arch/riscv/correct/examples/test_riscv_example_002.out b/tests/arch/riscv/correct/examples/test_riscv_example_002.out deleted file mode 100644 index f585b2625..000000000 --- a/tests/arch/riscv/correct/examples/test_riscv_example_002.out +++ /dev/null @@ -1,4 +0,0 @@ - -4 -cr[PC]:0xfffffffe; ir[x5,t0]:0xa; ir[x6,t1]:0xd; ir[x7,t2]:0x2d; ir[x10,a0]:0x4; ir[x17,a7]:0x1; ir[x28,t3]:0x21; ir[x29,t4]:0x4; keyboard[0x0]:''; display[0x0]:'4'; - diff --git a/tests/arch/riscv/correct/examples/test_riscv_example_002.s b/tests/arch/riscv/correct/examples/test_riscv_example_002.s index f710bf04e..8f00158bd 100644 --- a/tests/arch/riscv/correct/examples/test_riscv_example_002.s +++ b/tests/arch/riscv/correct/examples/test_riscv_example_002.s @@ -1,68 +1,26 @@ + # # Creator (https://creatorsim.github.io/creator/) -# Example: Store "hello world" byte by byte without data segment # .text - main: - # Use a base memory address - li t1, 0x200000 - - # Store "hello world" byte by byte - # 'h' = 104 - li t0, 104 - sb t0, 0(t1) - - # 'e' = 101 - li t0, 101 - sb t0, 1(t1) - - # 'l' = 108 - li t0, 108 - sb t0, 2(t1) - - # 'l' = 108 - li t0, 108 - sb t0, 3(t1) - - # 'o' = 111 - li t0, 111 - sb t0, 4(t1) - - # ' ' = 32 (space) - li t0, 32 - sb t0, 5(t1) - - # 'w' = 119 - li t0, 119 - sb t0, 6(t1) - - # 'o' = 111 - li t0, 111 - sb t0, 7(t1) - - # 'r' = 114 - li t0, 114 - sb t0, 8(t1) - - # 'l' = 108 - li t0, 108 - sb t0, 9(t1) - - # 'd' = 100 - li t0, 100 - sb t0, 10(t1) - - # null terminator = 0 - li t0, 0 - sb t0, 11(t1) - - # Print the string (system call 4 - print string) - mv a0, t1 # address of string - li a7, 4 # system call for print string - ecall - - # Return - li a7, 10 - ecall +main: + + li t0, 10 + li t1, 13 + li t2, 45 + li t3, 33 + + add t4, t0, t1 # 10+13 + sub t4, t2, t3 # 45-33 + mul t4, t3, t3 # 33*33 + div t4, t2, t0 # 45/10 + + # print last t4 + mv a0, t4 + li a7, 1 + ecall + + # return + jr ra diff --git a/tests/arch/riscv/correct/examples/test_riscv_example_003.out b/tests/arch/riscv/correct/examples/test_riscv_example_003.out deleted file mode 100644 index 83847e45f..000000000 --- a/tests/arch/riscv/correct/examples/test_riscv_example_003.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0xfffffffe; ir[x5,t0]:0x20000e; ir[x6,t1]:0x200004; ir[x7,t2]:0x200006; ir[x28,t3]:0xe; ir[x29,t4]:0x78; ir[x30,t5]:0x16; memory[0x20000f]:0x16; memory[0x20000c]:0x78; memory[0x20000b]:0x0e; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/correct/examples/test_riscv_example_003.s b/tests/arch/riscv/correct/examples/test_riscv_example_003.s index 3b9c35088..5a372f2dc 100644 --- a/tests/arch/riscv/correct/examples/test_riscv_example_003.s +++ b/tests/arch/riscv/correct/examples/test_riscv_example_003.s @@ -6,7 +6,6 @@ .data w1: .word 14 b1: .byte 120 - b4: .byte 0x7F .align 1 h1: .half 22 diff --git a/tests/arch/riscv/correct/examples/test_riscv_example_004.out b/tests/arch/riscv/correct/examples/test_riscv_example_004.out deleted file mode 100644 index 4004704ae..000000000 --- a/tests/arch/riscv/correct/examples/test_riscv_example_004.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0xfffffffe; ir[x5,t0]:0x200000; ir[x6,t1]:0x200008; ir[x7,t2]:0x200010; ir[x8,fp,s0]:0x200028; fpr[f0,ft0]:0x405145A1CAC08312; fpr[f2,ft2]:0x4026E2D0E5604189; fpr[f4,ft4]:0x4082A27EF9DB22D1; fpr[f10,fa0]:0x4084CB3333333333; fpr[f12,fa2]:0x404D13154689C3E9; memory[0x20002f]:0xE9; memory[0x20002e]:0xC3; memory[0x20002d]:0x89; memory[0x20002c]:0x46; memory[0x20002b]:0x15; memory[0x20002a]:0x13; memory[0x200029]:0x4D; memory[0x200028]:0x40; memory[0x200027]:0xD1; memory[0x200026]:0x22; memory[0x200025]:0xDB; memory[0x200024]:0xF9; memory[0x200023]:0x7E; memory[0x200022]:0xA2; memory[0x200021]:0x82; memory[0x200020]:0x40; memory[0x20001f]:0x12; memory[0x20001e]:0x83; memory[0x20001d]:0xC0; memory[0x20001c]:0xCA; memory[0x20001b]:0xA1; memory[0x20001a]:0x45; memory[0x200019]:0x51; memory[0x200018]:0x40; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/correct/examples/test_riscv_example_005.out b/tests/arch/riscv/correct/examples/test_riscv_example_005.out deleted file mode 100644 index 16083806e..000000000 --- a/tests/arch/riscv/correct/examples/test_riscv_example_005.out +++ /dev/null @@ -1,4 +0,0 @@ - -45 -cr[PC]:0xfffffffe; ir[x5,t0]:0xa; ir[x6,t1]:0xa; ir[x10,a0]:0x2d; ir[x17,a7]:0x1; keyboard[0x0]:''; display[0x0]:'45'; - diff --git a/tests/arch/riscv/correct/examples/test_riscv_example_006.out b/tests/arch/riscv/correct/examples/test_riscv_example_006.out deleted file mode 100644 index 0d638f0c9..000000000 --- a/tests/arch/riscv/correct/examples/test_riscv_example_006.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x1c; ir[x5,t0]:0x4; ir[x6,t1]:0x2; ir[x17,a7]:0xa; ir[x28,t3]:0x22; ir[x29,t4]:0xb; ir[x30,t5]:0x22b; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/correct/examples/test_riscv_example_007.out b/tests/arch/riscv/correct/examples/test_riscv_example_007.out deleted file mode 100644 index 1bf2a3f44..000000000 --- a/tests/arch/riscv/correct/examples/test_riscv_example_007.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0xfffffffe; ir[x5,t0]:0xf; ir[x6,t1]:0x5; ir[x7,t2]:0x5; ir[x28,t3]:0x1; ir[x29,t4]:0x4; ir[x30,t5]:0x200014; ir[x31,t6]:0x5; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/correct/examples/test_riscv_example_008.out b/tests/arch/riscv/correct/examples/test_riscv_example_008.out deleted file mode 100644 index 2cca57405..000000000 --- a/tests/arch/riscv/correct/examples/test_riscv_example_008.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0xfffffffe; ir[x5,t0]:0x200040; ir[x6,t1]:0x200080; ir[x7,t2]:0x4; ir[x28,t3]:0x4; ir[x29,t4]:0x4; fpr[f0,ft0]:0xffffffff33441124; memory[0x20007f]:0x24; memory[0x20007e]:0x11; memory[0x20007d]:0x44; memory[0x20007c]:0x33; memory[0x20007b]:0x21; memory[0x20007a]:0x43; memory[0x200079]:0x65; memory[0x200078]:0x87; memory[0x200077]:0x78; memory[0x200076]:0x56; memory[0x200075]:0x34; memory[0x200074]:0x12; memory[0x200073]:0x23; memory[0x200072]:0xff; memory[0x20006d]:0xd0; memory[0x20006c]:0x77; memory[0x20006b]:0x12; memory[0x20006a]:0xf0; memory[0x200069]:0xbf; memory[0x200068]:0xaa; memory[0x200067]:0x22; memory[0x200066]:0x11; memory[0x200065]:0x55; memory[0x200064]:0x44; memory[0x200063]:0x14; memory[0x200062]:0x02; memory[0x20005f]:0x14; memory[0x20005e]:0x14; memory[0x20005d]:0x14; memory[0x20005c]:0x14; memory[0x20005b]:0x20; memory[0x20005a]:0x21; memory[0x200059]:0x51; memory[0x200058]:0x77; memory[0x200057]:0x10; memory[0x200056]:0x22; memory[0x200055]:0x43; memory[0x200051]:0x45; memory[0x200050]:0x23; memory[0x20004c]:0x34; memory[0x200048]:0x34; memory[0x200044]:0x34; memory[0x200040]:0x34; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/correct/examples/test_riscv_example_011.out b/tests/arch/riscv/correct/examples/test_riscv_example_011.out deleted file mode 100644 index 55200332a..000000000 --- a/tests/arch/riscv/correct/examples/test_riscv_example_011.out +++ /dev/null @@ -1,4 +0,0 @@ - --144 -cr[PC]:0xfffffffe; ir[x6,t1]:0xffffffca; ir[x7,t2]:0x5a; ir[x10,a0]:0xffffff70; ir[x11,a1]:0x5a; ir[x12,a2]:0x2d; ir[x17,a7]:0x1; keyboard[0x0]:''; display[0x0]:'-144'; - diff --git a/tests/arch/riscv/correct/examples/test_riscv_example_012.out b/tests/arch/riscv/correct/examples/test_riscv_example_012.out deleted file mode 100644 index 1a3ed56da..000000000 --- a/tests/arch/riscv/correct/examples/test_riscv_example_012.out +++ /dev/null @@ -1,4 +0,0 @@ - -120 -cr[PC]:0xfffffffe; ir[x5,t0]:0x2; ir[x6,t1]:0x5; ir[x10,a0]:0x78; ir[x17,a7]:0x1; keyboard[0x0]:''; display[0x0]:'120'; - diff --git a/tests/arch/riscv/correct/examples/test_riscv_example_013.out b/tests/arch/riscv/correct/examples/test_riscv_example_013.out deleted file mode 100644 index fa87a5452..000000000 --- a/tests/arch/riscv/correct/examples/test_riscv_example_013.out +++ /dev/null @@ -1,41 +0,0 @@ - -83 -116 -114 -105 -110 -103 -32 -105 -110 -32 -85 -84 -70 -45 -56 -58 -32 --30 --120 --128 -32 --30 --120 --85 -32 --30 --120 --121 -32 --30 --120 --120 -32 --16 --97 --96 --84 -0 -cr[PC]:0x1c; ir[x5,t0]:0x200026; ir[x17,a7]:0x1; keyboard[0x0]:''; display[0x0]:'83116114105110103321051103285847045565832-30-120-12832-30-120-8532-30-120-12132-30-120-12032-16-97-96-840'; - diff --git a/tests/arch/riscv/correct/examples/test_riscv_example_013.s b/tests/arch/riscv/correct/examples/test_riscv_example_013.s index c7912aa9b..07643a3c4 100644 --- a/tests/arch/riscv/correct/examples/test_riscv_example_013.s +++ b/tests/arch/riscv/correct/examples/test_riscv_example_013.s @@ -1,113 +1,16 @@ + # # Creator (https://creatorsim.github.io/creator/) # -.text - -main: - # Create stack frame - addi sp, sp, -16 # Allocate space for 4 words - sw ra, 12(sp) # Save return address - sw s0, 8(sp) # Save callee-saved registers - sw s1, 4(sp) - sw s2, 0(sp) - - # Initialize arguments - li a0, 23 - li a1, -77 - li a2, 45 - - # Call the first level function (starts the nested calls) - jal ra, level1 - - # Store result - mv s0, a0 - - # Print result - li a7, 1 - ecall - - # Restore registers and return - lw s2, 0(sp) - lw s1, 4(sp) - lw s0, 8(sp) - lw ra, 12(sp) - addi sp, sp, 16 - jr ra +.data + utf8: .string "String in UTF-8: ∀ ∫ ∇ ∈ 🠬" -# First level function - calls level2 -level1: - # Create stack frame - addi sp, sp, -16 - sw ra, 12(sp) - sw s0, 8(sp) - sw a0, 4(sp) # Save argument a0 - sw a1, 0(sp) # Save argument a1 - - # Save arguments in saved registers - mv s0, a0 - - # Call level2 - jal ra, level2 - - # Add original a0 to result - add a0, a0, s0 - - # Restore registers and return - lw a1, 0(sp) - lw s0, 8(sp) - lw ra, 12(sp) - addi sp, sp, 16 - jr ra - -# Second level function - calls level3 -level2: - # Create stack frame - addi sp, sp, -12 - sw ra, 8(sp) - sw a1, 4(sp) - sw a2, 0(sp) - - # Call level3 - jal ra, level3 - - # Add original a2 to result - lw t0, 0(sp) - add a0, a0, t0 - - # Restore and return - lw a1, 4(sp) - lw ra, 8(sp) - addi sp, sp, 12 - jr ra - -# Third level function - calls sum -level3: - # Create stack frame - addi sp, sp, -8 - sw ra, 4(sp) - sw a1, 0(sp) - - # First call the original sum function - jal ra, sum - - # Then call sub with result from sum - lw a1, 0(sp) - jal ra, sub - - # Restore and return - lw ra, 4(sp) - addi sp, sp, 8 - jr ra - -# Original functions from the example -sum: - add t1, a0, a1 - add t2, a2, a2 - add a0, t1, zero - add a1, t2, zero - jr ra - -sub: - sub a0, a0, a1 - jr ra +.text +main: li a7, 1 + la t0, utf8 +loop: lb a0, 0(t0) + ecall + addi t0, t0, 1 + bne a0, zero, loop + jr ra diff --git a/tests/arch/riscv/correct/examples/test_riscv_example_014.s b/tests/arch/riscv/correct/examples/test_riscv_example_014.s index be379ab67..c7912aa9b 100644 --- a/tests/arch/riscv/correct/examples/test_riscv_example_014.s +++ b/tests/arch/riscv/correct/examples/test_riscv_example_014.s @@ -1,97 +1,113 @@ # # Creator (https://creatorsim.github.io/creator/) -# Example: Various data types in data segment and memory operations # -.data -.align 4 +.text -# Different data types in data segment -byte_values: .byte 0x42, 0x73, 0xA5, 0xFF - .byte -128, 127, 0, 55 +main: + # Create stack frame + addi sp, sp, -16 # Allocate space for 4 words + sw ra, 12(sp) # Save return address + sw s0, 8(sp) # Save callee-saved registers + sw s1, 4(sp) + sw s2, 0(sp) -.align 2 -half_values: .half 0x1234, 0x5678, 0xABCD, 0xEF12 - .half -32768, 32767, 0, 12345 + # Initialize arguments + li a0, 23 + li a1, -77 + li a2, 45 + + # Call the first level function (starts the nested calls) + jal ra, level1 + + # Store result + mv s0, a0 + + # Print result + li a7, 1 + ecall -.align 4 -word_values: .word 0x12345678, 0x87654321, 0xDEADBEEF, 0xCAFEBABE - .word -2147483648, 2147483647, 0, 1000000 + # Restore registers and return + lw s2, 0(sp) + lw s1, 4(sp) + lw s0, 8(sp) + lw ra, 12(sp) + addi sp, sp, 16 + jr ra -.align 3 -double_values: .dword 0x123456789ABCDEF0, 0xFEDCBA9876543210 - .dword 0x0123456789ABCDEF, 0xAAAABBBBCCCCDDDD +# First level function - calls level2 +level1: + # Create stack frame + addi sp, sp, -16 + sw ra, 12(sp) + sw s0, 8(sp) + sw a0, 4(sp) # Save argument a0 + sw a1, 0(sp) # Save argument a1 + + # Save arguments in saved registers + mv s0, a0 + + # Call level2 + jal ra, level2 + + # Add original a0 to result + add a0, a0, s0 + + # Restore registers and return + lw a1, 0(sp) + lw s0, 8(sp) + lw ra, 12(sp) + addi sp, sp, 16 + jr ra -# String data -.align 1 -string_data: .string "Hello, RISC-V!" - .byte 0 # Null terminator +# Second level function - calls level3 +level2: + # Create stack frame + addi sp, sp, -12 + sw ra, 8(sp) + sw a1, 4(sp) + sw a2, 0(sp) + + # Call level3 + jal ra, level3 + + # Add original a2 to result + lw t0, 0(sp) + add a0, a0, t0 + + # Restore and return + lw a1, 4(sp) + lw ra, 8(sp) + addi sp, sp, 12 + jr ra -# Float data (stored as word) -.align 4 -float_data: .word 0x40490FDB # Pi as IEEE 754 float (3.14159...) - .word 0x402DF854 # e as IEEE 754 float (2.71828...) +# Third level function - calls sum +level3: + # Create stack frame + addi sp, sp, -8 + sw ra, 4(sp) + sw a1, 0(sp) + + # First call the original sum function + jal ra, sum + + # Then call sub with result from sum + lw a1, 0(sp) + jal ra, sub + + # Restore and return + lw ra, 4(sp) + addi sp, sp, 8 + jr ra -# Target memory locations for writing -.align 4 -target_area: .space 256 # Reserve 256 bytes for writing data +# Original functions from the example +sum: + add t1, a0, a1 + add t2, a2, a2 + add a0, t1, zero + add a1, t2, zero + jr ra -.text -main: - # Set up base addresses - la t0, byte_values - la t1, half_values - la t2, word_values - la t3, double_values - la t4, target_area - - # Copy and manipulate byte data - lb a0, 0(t0) # Load first byte (0x42) - sb a0, 0(t4) # Store to target area - lb a1, 3(t0) # Load fourth byte (0xFF) - sb a1, 1(t4) # Store to target area + 1 - - # Manipulate and store modified byte - addi a0, a0, 1 # Increment byte value - sb a0, 2(t4) # Store modified byte - - # Copy and manipulate half-word data - lh a0, 0(t1) # Load first half (0x1234) - sh a0, 4(t4) # Store to target area + 4 - lh a1, 6(t1) # Load fourth half (0xEF12) - sh a1, 6(t4) # Store to target area + 6 - - # Perform arithmetic on half-word and store - add a2, a0, a1 # Add two half-words - sh a2, 8(t4) # Store result - - # Copy and manipulate word data - lw a0, 0(t2) # Load first word (0x12345678) - sw a0, 12(t4) # Store to target area + 12 - lw a1, 12(t2) # Load fourth word (0xCAFEBABE) - sw a1, 16(t4) # Store to target area + 16 - - # Perform bitwise operations on words - xor a2, a0, a1 # XOR two words - sw a2, 20(t4) # Store XOR result - or a3, a0, a1 # OR two words - sw a3, 24(t4) # Store OR result - and a4, a0, a1 # AND two words - sw a4, 28(t4) # Store AND result - - # Copy double-word data (64-bit) - ld a0, 0(t3) # Load first double-word - sd a0, 32(t4) # Store to target area + 32 - ld a1, 8(t3) # Load second double-word - sd a1, 40(t4) # Store to target area + 40 - - # Create and store new data patterns - li a0, 0x55AA55AA # Create alternating bit pattern - sw a0, 48(t4) # Store pattern - - # Store sequential byte pattern - li a0, 0x01 # Start with 1 - li a1, 8 # Counter for 8 bytes - addi a2, t4, 52 # Start address for pattern - - jr ra \ No newline at end of file +sub: + sub a0, a0, a1 + jr ra diff --git a/tests/arch/riscv/correct/examples/test_riscv_example_015.s b/tests/arch/riscv/correct/examples/test_riscv_example_015.s new file mode 100644 index 000000000..f710bf04e --- /dev/null +++ b/tests/arch/riscv/correct/examples/test_riscv_example_015.s @@ -0,0 +1,68 @@ +# +# Creator (https://creatorsim.github.io/creator/) +# Example: Store "hello world" byte by byte without data segment +# + +.text + main: + # Use a base memory address + li t1, 0x200000 + + # Store "hello world" byte by byte + # 'h' = 104 + li t0, 104 + sb t0, 0(t1) + + # 'e' = 101 + li t0, 101 + sb t0, 1(t1) + + # 'l' = 108 + li t0, 108 + sb t0, 2(t1) + + # 'l' = 108 + li t0, 108 + sb t0, 3(t1) + + # 'o' = 111 + li t0, 111 + sb t0, 4(t1) + + # ' ' = 32 (space) + li t0, 32 + sb t0, 5(t1) + + # 'w' = 119 + li t0, 119 + sb t0, 6(t1) + + # 'o' = 111 + li t0, 111 + sb t0, 7(t1) + + # 'r' = 114 + li t0, 114 + sb t0, 8(t1) + + # 'l' = 108 + li t0, 108 + sb t0, 9(t1) + + # 'd' = 100 + li t0, 100 + sb t0, 10(t1) + + # null terminator = 0 + li t0, 0 + sb t0, 11(t1) + + # Print the string (system call 4 - print string) + mv a0, t1 # address of string + li a7, 4 # system call for print string + ecall + + # Return + li a7, 10 + ecall + diff --git a/tests/arch/riscv/correct/syscalls/test_riscv_syscall_001.out b/tests/arch/riscv/correct/syscalls/test_riscv_syscall_001.out deleted file mode 100644 index cddaf93dd..000000000 --- a/tests/arch/riscv/correct/syscalls/test_riscv_syscall_001.out +++ /dev/null @@ -1,9 +0,0 @@ - -6673 -120 -34 --5678 -1066192077 -this is a string -cr[PC]:0x64; ir[x6,t1]:0x20001c; ir[x10,a0]:0x200008; ir[x17,a7]:0x4; fpr[f0,ft0]:0xffffffff3F8CCCCD; keyboard[0x0]:''; display[0x0]:'667312034-56781066192077this%20is%20a%20string'; - diff --git a/tests/arch/riscv/correct/syscalls/test_riscv_syscall_002.out b/tests/arch/riscv/correct/syscalls/test_riscv_syscall_002.out deleted file mode 100644 index f5a0b4798..000000000 --- a/tests/arch/riscv/correct/syscalls/test_riscv_syscall_002.out +++ /dev/null @@ -1,6 +0,0 @@ - -6673 --86 -1 -cr[PC]:0x2c; ir[x5,t0]:0x1; ir[x17,a7]:0x2; fpr[f10,fa0]:0xffffffff3F800000; keyboard[0x0]:''; display[0x0]:'6673-861'; - diff --git a/tests/arch/riscv/correct/syscalls/test_riscv_syscall_003.out b/tests/arch/riscv/correct/syscalls/test_riscv_syscall_003.out deleted file mode 100644 index bf4dd79ce..000000000 --- a/tests/arch/riscv/correct/syscalls/test_riscv_syscall_003.out +++ /dev/null @@ -1,6 +0,0 @@ - -6673 --86 -1 -cr[PC]:0x2c; ir[x5,t0]:0x1; ir[x17,a7]:0x3; fpr[f10,fa0]:0x3FF0000000000000; keyboard[0x0]:''; display[0x0]:'6673-861'; - diff --git a/tests/arch/riscv/correct/syscalls/test_riscv_syscall_004.out b/tests/arch/riscv/correct/syscalls/test_riscv_syscall_004.out deleted file mode 100644 index d08cb5580..000000000 --- a/tests/arch/riscv/correct/syscalls/test_riscv_syscall_004.out +++ /dev/null @@ -1,8 +0,0 @@ - -First String -Second String -a - - -cr[PC]:0x34; ir[x10,a0]:0xa; ir[x17,a7]:0xb; keyboard[0x0]:''; display[0x0]:'First%20StringSecond%20Stringa%0A'; - diff --git a/tests/arch/riscv/correct/syscalls/test_riscv_syscall_005.s b/tests/arch/riscv/correct/syscalls/test_riscv_syscall_005.s index 05f1fb810..ac99a90fd 100644 --- a/tests/arch/riscv/correct/syscalls/test_riscv_syscall_005.s +++ b/tests/arch/riscv/correct/syscalls/test_riscv_syscall_005.s @@ -6,4 +6,5 @@ .text main: li a7, 5 - ecall \ No newline at end of file + ecall + jr ra \ No newline at end of file diff --git a/tests/arch/riscv/correct/syscalls/test_riscv_syscall_006.s b/tests/arch/riscv/correct/syscalls/test_riscv_syscall_006.s index b3ad184d5..f1770f2dd 100644 --- a/tests/arch/riscv/correct/syscalls/test_riscv_syscall_006.s +++ b/tests/arch/riscv/correct/syscalls/test_riscv_syscall_006.s @@ -7,3 +7,4 @@ main: li a7, 6 ecall + jr ra diff --git a/tests/arch/riscv/correct/syscalls/test_riscv_syscall_007.s b/tests/arch/riscv/correct/syscalls/test_riscv_syscall_007.s index 177ae9419..cb406937d 100644 --- a/tests/arch/riscv/correct/syscalls/test_riscv_syscall_007.s +++ b/tests/arch/riscv/correct/syscalls/test_riscv_syscall_007.s @@ -7,4 +7,4 @@ main: li a7, 7 ecall - \ No newline at end of file + jr ra \ No newline at end of file diff --git a/tests/arch/riscv/correct/syscalls/test_riscv_syscall_008.s b/tests/arch/riscv/correct/syscalls/test_riscv_syscall_008.s index e339d211c..28f0ce457 100644 --- a/tests/arch/riscv/correct/syscalls/test_riscv_syscall_008.s +++ b/tests/arch/riscv/correct/syscalls/test_riscv_syscall_008.s @@ -14,4 +14,5 @@ li a7, 8 la a0, buffer li a1, 5 - ecall \ No newline at end of file + ecall + jr ra \ No newline at end of file diff --git a/tests/arch/riscv/correct/syscalls/test_riscv_syscall_009.s b/tests/arch/riscv/correct/syscalls/test_riscv_syscall_009.s index 300d643e2..cfbb7e931 100644 --- a/tests/arch/riscv/correct/syscalls/test_riscv_syscall_009.s +++ b/tests/arch/riscv/correct/syscalls/test_riscv_syscall_009.s @@ -13,4 +13,5 @@ ecall sw t0, 0(a0) - sw t1, 4(a0) \ No newline at end of file + sw t1, 4(a0) + jr ra diff --git a/tests/arch/riscv/correct/syscalls/test_riscv_syscall_010.out b/tests/arch/riscv/correct/syscalls/test_riscv_syscall_010.out deleted file mode 100644 index ffed9be10..000000000 --- a/tests/arch/riscv/correct/syscalls/test_riscv_syscall_010.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x8; ir[x17,a7]:0xa; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/correct/syscalls/test_riscv_syscall_010.s b/tests/arch/riscv/correct/syscalls/test_riscv_syscall_010.s index 800efcdeb..5355c5c8c 100644 --- a/tests/arch/riscv/correct/syscalls/test_riscv_syscall_010.s +++ b/tests/arch/riscv/correct/syscalls/test_riscv_syscall_010.s @@ -8,3 +8,4 @@ li a7, 10 ecall li t0, 453 + jr ra diff --git a/tests/arch/riscv/correct/syscalls/test_riscv_syscall_011.out b/tests/arch/riscv/correct/syscalls/test_riscv_syscall_011.out deleted file mode 100644 index 2e7d093b0..000000000 --- a/tests/arch/riscv/correct/syscalls/test_riscv_syscall_011.out +++ /dev/null @@ -1,4 +0,0 @@ - -c -cr[PC]:0xc; ir[x10,a0]:0x63; ir[x17,a7]:0xb; keyboard[0x0]:''; display[0x0]:'c'; - diff --git a/tests/arch/riscv/correct/syscalls/test_riscv_syscall_011.s b/tests/arch/riscv/correct/syscalls/test_riscv_syscall_011.s index 61cb6278f..0b7064bf5 100644 --- a/tests/arch/riscv/correct/syscalls/test_riscv_syscall_011.s +++ b/tests/arch/riscv/correct/syscalls/test_riscv_syscall_011.s @@ -8,3 +8,4 @@ li a7, 11 li a0, 'c' ecall + jr ra diff --git a/tests/arch/riscv/correct/syscalls/test_riscv_syscall_012.s b/tests/arch/riscv/correct/syscalls/test_riscv_syscall_012.s index 7f3b95895..3a734cb42 100644 --- a/tests/arch/riscv/correct/syscalls/test_riscv_syscall_012.s +++ b/tests/arch/riscv/correct/syscalls/test_riscv_syscall_012.s @@ -7,3 +7,4 @@ main: li a7, 12 ecall + jr ra diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_001.out b/tests/arch/riscv/instructions/test_riscv_instruction_001.out deleted file mode 100644 index 9b6c2763c..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_001.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x20; ir[x5,t0]:0xa; ir[x6,t1]:0xffffffe2; ir[x8,fp,s0]:0xffffff; ir[x9,s1]:0xffffffec; ir[x10,a0]:0xffffffec; ir[x11,a1]:0xffffeb; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_001.s b/tests/arch/riscv/instructions/test_riscv_instruction_001.s index 6cc090db2..598092385 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_001.s +++ b/tests/arch/riscv/instructions/test_riscv_instruction_001.s @@ -13,7 +13,7 @@ main: add x9, x5, x6 # 10 - 30 add x10, x7, x9 # -20 + 0 - add x11, x8, x10 # -20 + 0xFFFFFF noo -> 0xFFFFFF - 20 + add x11, x8, x10 # -20 + 0xFFFFFF # end program jr ra diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_002.out b/tests/arch/riscv/instructions/test_riscv_instruction_002.out deleted file mode 100644 index 86264c0de..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_002.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x10; ir[x5,t0]:0xa; ir[x9,s1]:0xffffffec; ir[x10,a0]:0x187; ir[x11,a1]:0x193; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_002.s b/tests/arch/riscv/instructions/test_riscv_instruction_002.s index e6db252ef..d4fb18e85 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_002.s +++ b/tests/arch/riscv/instructions/test_riscv_instruction_002.s @@ -10,4 +10,6 @@ main: addi x9, x5, -30 # 10 - 30 addi x10, x9, 411 # x9 + 411 addi x11, x10, 12 # x10 - 12 - #addi x11, x10, 42568 # x10 - 42568 \ No newline at end of file + #addi x11, x10, 42568 # x10 - 42568 + + jr ra diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_003.out b/tests/arch/riscv/instructions/test_riscv_instruction_003.out deleted file mode 100644 index 00aa1c232..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_003.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x20; ir[x5,t0]:0x223; ir[x6,t1]:0xfffffc57; ir[x7,t2]:0xc; ir[x8,fp,s0]:0x123515; ir[x9,s1]:0x5cc; ir[x10,a0]:0xfffffa40; ir[x11,a1]:0x123ad5; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_003.s b/tests/arch/riscv/instructions/test_riscv_instruction_003.s index a0496bffd..219cd60ed 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_003.s +++ b/tests/arch/riscv/instructions/test_riscv_instruction_003.s @@ -13,4 +13,6 @@ main: sub x9, x5, x6 # 547 - (-937) sub x10, x7, x9 # 12 - 1484 - sub x11, x8, x10 # 0x123515 + 1472 \ No newline at end of file + sub x11, x8, x10 # 0x123515 + 1472 + + jr ra diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_004.out b/tests/arch/riscv/instructions/test_riscv_instruction_004.out deleted file mode 100644 index d36f27819..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_004.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x14; ir[x5,t0]:0x23000; ir[x6,t1]:0x56db000; ir[x7,t2]:0x34000; ir[x8,fp,s0]:0x7f002000; ir[x9,s1]:0x2000; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_004.s b/tests/arch/riscv/instructions/test_riscv_instruction_004.s index fba8eb31a..1d7a55472 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_004.s +++ b/tests/arch/riscv/instructions/test_riscv_instruction_004.s @@ -10,4 +10,6 @@ main: lui x6, 22235 lui x7, 0x34 lui x8, 0xFF002 - lui x9, 2 \ No newline at end of file + lui x9, 2 + + jr ra diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_005.out b/tests/arch/riscv/instructions/test_riscv_instruction_005.out deleted file mode 100644 index 1271c94c8..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_005.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x2c; ir[x1,ra]:0x18; ir[x5,t0]:0x223; ir[x6,t1]:0xfffffc57; ir[x7,t2]:0xc; ir[x8,fp,s0]:0x123515; ir[x17,a7]:0xa; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_006.out b/tests/arch/riscv/instructions/test_riscv_instruction_006.out deleted file mode 100644 index 1271c94c8..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_006.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x2c; ir[x1,ra]:0x18; ir[x5,t0]:0x223; ir[x6,t1]:0xfffffc57; ir[x7,t2]:0xc; ir[x8,fp,s0]:0x123515; ir[x17,a7]:0xa; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_006.s b/tests/arch/riscv/instructions/test_riscv_instruction_006.s index 37b337e98..2fed5e543 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_006.s +++ b/tests/arch/riscv/instructions/test_riscv_instruction_006.s @@ -11,7 +11,8 @@ main: li x7, 12 li x8, 0x123515 - jal x1, end + jal x0, mid +mid:jalr x1, 0x28(x0) sub x9, x5, x6 # 547 - (-937) sub x10, x7, x9 # 12 - 1484 @@ -19,4 +20,4 @@ main: end: li a7, 10 - ecall \ No newline at end of file + ecall diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_007.out b/tests/arch/riscv/instructions/test_riscv_instruction_007.out deleted file mode 100644 index af8d133ea..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_007.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x2c; ir[x5,t0]:0x44562; ir[x6,t1]:0x2; ir[x7,t2]:0x5; ir[x8,fp,s0]:0x44562; ir[x17,a7]:0xa; ir[x28,t3]:0x22; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_008.out b/tests/arch/riscv/instructions/test_riscv_instruction_008.out deleted file mode 100644 index 21d396ff4..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_008.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x24; ir[x5,t0]:0x754; ir[x6,t1]:0x22b; ir[x7,t2]:0x5; ir[x8,fp,s0]:0x44562; ir[x17,a7]:0xa; ir[x28,t3]:0x22; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_009.out b/tests/arch/riscv/instructions/test_riscv_instruction_009.out deleted file mode 100644 index d4bf66ee9..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_009.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x28; ir[x5,t0]:0x169; ir[x6,t1]:0x2; ir[x7,t2]:0x5; ir[x8,fp,s0]:0x44562; ir[x9,s1]:0x754; ir[x10,a0]:0x22b; ir[x17,a7]:0xa; ir[x28,t3]:0x22; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_010.out b/tests/arch/riscv/instructions/test_riscv_instruction_010.out deleted file mode 100644 index cd97af2a3..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_010.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x28; ir[x5,t0]:0x754; ir[x6,t1]:0x2; ir[x7,t2]:0x5; ir[x8,fp,s0]:0x44562; ir[x17,a7]:0xa; ir[x28,t3]:0x22; ir[x31,t6]:0x22b; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_011.out b/tests/arch/riscv/instructions/test_riscv_instruction_011.out deleted file mode 100644 index d4bf66ee9..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_011.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x28; ir[x5,t0]:0x169; ir[x6,t1]:0x2; ir[x7,t2]:0x5; ir[x8,fp,s0]:0x44562; ir[x9,s1]:0x754; ir[x10,a0]:0x22b; ir[x17,a7]:0xa; ir[x28,t3]:0x22; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_012.out b/tests/arch/riscv/instructions/test_riscv_instruction_012.out deleted file mode 100644 index cd97af2a3..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_012.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x28; ir[x5,t0]:0x754; ir[x6,t1]:0x2; ir[x7,t2]:0x5; ir[x8,fp,s0]:0x44562; ir[x17,a7]:0xa; ir[x28,t3]:0x22; ir[x31,t6]:0x22b; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_013.out b/tests/arch/riscv/instructions/test_riscv_instruction_013.out deleted file mode 100644 index 5d7a09fa8..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_013.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x48; ir[x5,t0]:0x200000; ir[x6,t1]:0x200004; ir[x7,t2]:0x200006; ir[x8,fp,s0]:0xe; ir[x10,a0]:0x7f; ir[x12,a2]:0x7fff; ir[x14,a4]:0x20000e; memory[0x20000f]:0xff; memory[0x20000e]:0x7f; memory[0x20000c]:0x7f; memory[0x20000b]:0x0e; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_013.s b/tests/arch/riscv/instructions/test_riscv_instruction_013.s new file mode 100644 index 000000000..3f01a3201 --- /dev/null +++ b/tests/arch/riscv/instructions/test_riscv_instruction_013.s @@ -0,0 +1,43 @@ + +# +# Creator (https://creatorsim.github.io/creator/) +# + +.data + w1: .word 14 + b1: .byte 127 + + .align 1 + h1: .half 32767 + w2: .zero 4 + b2: .zero 1 + + .align 1 + h2: .zero 2 + +.text +main: + + la x5, w1 # w1 address -> x5 + la x6, b1 # b1 address -> x6 + la x7, h1 # h1 address -> x7 + + lw x8, 0 (x5) # Memory[x5] -> x8 + #lw x9, w1 # Memory[w1] -> x9 + + lb x10, 0(x6) # Memory[x6] -> x10 + #lb x11, b1 # Memory[b1] -> x11 + + lh x12, 0 (x7) # Memory[x7] -> x12 + #lh x13, h1 # Memory[h1] -> x13 + + la x14, w2 # w2 address -> x14 + sw x8, 0(x14) # x8 -> Memory[w2] + + la x14, b2 # b2 address -> x14 + sb x10, 0(x14) # x10 -> Memory[b2] + + la x14, h2 # h2 address -> x14 + sh x12, 0(x14) # x12 -> Memory[h2] + + jr ra diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_014.out b/tests/arch/riscv/instructions/test_riscv_instruction_014.out deleted file mode 100644 index 7059f0735..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_014.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x30; ir[x6,t1]:0x200000; ir[x7,t2]:0x200002; ir[x10,a0]:0x7f; ir[x12,a2]:0xffff; ir[x14,a4]:0x200006; memory[0x200007]:0xff; memory[0x200006]:0xff; memory[0x200004]:0x7f; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_014.s b/tests/arch/riscv/instructions/test_riscv_instruction_014.s index 4226d8430..3ec4dc88b 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_014.s +++ b/tests/arch/riscv/instructions/test_riscv_instruction_014.s @@ -28,4 +28,4 @@ main: la x14, h2 # h2 address -> x14 sh x12, 0(x14) # x12 -> Memory[h2] - + jr ra diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_015.out b/tests/arch/riscv/instructions/test_riscv_instruction_015.out deleted file mode 100644 index 77770faba..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_015.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x28; ir[x5,t0]:0x2f0; ir[x8,fp,s0]:0x1; ir[x9,s1]:0x1; ir[x10,a0]:0xfffffc00; ir[x13,a3]:0x1; ir[x14,a4]:0x1; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_015.s b/tests/arch/riscv/instructions/test_riscv_instruction_015.s index 855a234f0..2d478dbf2 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_015.s +++ b/tests/arch/riscv/instructions/test_riscv_instruction_015.s @@ -17,3 +17,5 @@ main: slti x12, x10, -1024 slti x13, x10, -1023 slti x14, x10, -1022 + + jr ra diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_016.out b/tests/arch/riscv/instructions/test_riscv_instruction_016.out deleted file mode 100644 index 77770faba..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_016.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x28; ir[x5,t0]:0x2f0; ir[x8,fp,s0]:0x1; ir[x9,s1]:0x1; ir[x10,a0]:0xfffffc00; ir[x13,a3]:0x1; ir[x14,a4]:0x1; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_016.s b/tests/arch/riscv/instructions/test_riscv_instruction_016.s index 0281f6484..bfb5d0e11 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_016.s +++ b/tests/arch/riscv/instructions/test_riscv_instruction_016.s @@ -17,4 +17,5 @@ main: sltiu x12, x10, -1024 sltiu x13, x10, -1023 sltiu x14, x10, -1022 - \ No newline at end of file + + jr ra diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_017.out b/tests/arch/riscv/instructions/test_riscv_instruction_017.out deleted file mode 100644 index f66ba25a1..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_017.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x24; ir[x5,t0]:0x22346; ir[x6,t1]:0x11d7; ir[x7,t2]:0xffffdaf2; ir[x8,fp,s0]:0x22713; ir[x9,s1]:0x13f5; ir[x10,a0]:0xffffdd0d; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_017.s b/tests/arch/riscv/instructions/test_riscv_instruction_017.s index f60d28db0..163a93426 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_017.s +++ b/tests/arch/riscv/instructions/test_riscv_instruction_017.s @@ -13,4 +13,5 @@ main: xori x8, x5, 0x455 xori x9, x6, 0x222 xori x10, x7, 0x7FF - \ No newline at end of file + + jr ra diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_018.out b/tests/arch/riscv/instructions/test_riscv_instruction_018.out deleted file mode 100644 index 86396ba9b..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_018.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x24; ir[x5,t0]:0x22346; ir[x6,t1]:0x11d7; ir[x7,t2]:0xffffdaf2; ir[x8,fp,s0]:0x22757; ir[x9,s1]:0x13f7; ir[x10,a0]:0xffffdfff; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_018.s b/tests/arch/riscv/instructions/test_riscv_instruction_018.s index 3afe33af6..0d4b1b46b 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_018.s +++ b/tests/arch/riscv/instructions/test_riscv_instruction_018.s @@ -13,4 +13,5 @@ main: ori x8, x5, 0x455 ori x9, x6, 0x222 ori x10, x7, 0x7FF - \ No newline at end of file + + jr ra diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_019.out b/tests/arch/riscv/instructions/test_riscv_instruction_019.out deleted file mode 100644 index 542127014..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_019.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x24; ir[x5,t0]:0x22346; ir[x6,t1]:0x11d7; ir[x7,t2]:0xffffdaf2; ir[x8,fp,s0]:0x44; ir[x9,s1]:0x2; ir[x10,a0]:0x2f2; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_019.s b/tests/arch/riscv/instructions/test_riscv_instruction_019.s index 02ab3a5a5..d561e683e 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_019.s +++ b/tests/arch/riscv/instructions/test_riscv_instruction_019.s @@ -13,4 +13,5 @@ main: andi x8, x5, 0x455 andi x9, x6, 0x222 andi x10, x7, 0x7FF - \ No newline at end of file + + jr ra diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_020.out b/tests/arch/riscv/instructions/test_riscv_instruction_020.out deleted file mode 100644 index b77dbf3fb..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_020.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x24; ir[x5,t0]:0xaad4; ir[x6,t1]:0x11d7; ir[x7,t2]:0xffffdaf2; ir[x8,fp,s0]:0x2ab50; ir[x9,s1]:0x11d70; ir[x10,a0]:0xed790000; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_020.s b/tests/arch/riscv/instructions/test_riscv_instruction_020.s index e9402f6a9..32e0555b4 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_020.s +++ b/tests/arch/riscv/instructions/test_riscv_instruction_020.s @@ -13,5 +13,5 @@ main: slli x8, x5, 2 slli x9, x6, 4 slli x10, x7, 15 - - \ No newline at end of file + + jr ra diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_021.out b/tests/arch/riscv/instructions/test_riscv_instruction_021.out deleted file mode 100644 index 4061495a9..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_021.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x24; ir[x5,t0]:0xaad4; ir[x6,t1]:0x11d7; ir[x7,t2]:0xffffdaf2; ir[x8,fp,s0]:0x2ab5; ir[x9,s1]:0x11d; ir[x10,a0]:0x1ffff; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_021.s b/tests/arch/riscv/instructions/test_riscv_instruction_021.s index 8230216ef..06880a71a 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_021.s +++ b/tests/arch/riscv/instructions/test_riscv_instruction_021.s @@ -13,5 +13,5 @@ main: srli x8, x5, 2 srli x9, x6,4 srli x10, x7, 15 - - \ No newline at end of file + + jr ra diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_022.out b/tests/arch/riscv/instructions/test_riscv_instruction_022.out deleted file mode 100644 index f08cdef68..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_022.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x24; ir[x5,t0]:0xaad4; ir[x6,t1]:0x11d7; ir[x7,t2]:0xffffdaf2; ir[x8,fp,s0]:0x2ab5; ir[x9,s1]:0x11d; ir[x10,a0]:0xffffffff; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_022.s b/tests/arch/riscv/instructions/test_riscv_instruction_022.s index 334e2d526..980c04dbc 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_022.s +++ b/tests/arch/riscv/instructions/test_riscv_instruction_022.s @@ -13,5 +13,5 @@ main: srai x8, x5, 2 srai x9, x6, 4 srai x10, x7, 15 - - \ No newline at end of file + + jr ra diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_023.out b/tests/arch/riscv/instructions/test_riscv_instruction_023.out deleted file mode 100644 index 388f71930..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_023.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x30; ir[x5,t0]:0xaad4; ir[x6,t1]:0x11d7; ir[x7,t2]:0xffffdaf2; ir[x8,fp,s0]:0x2; ir[x9,s1]:0x1; ir[x10,a0]:0x554; ir[x11,a1]:0x2ab50; ir[x12,a2]:0x23ae; ir[x13,a3]:0xaf200000; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_023.s b/tests/arch/riscv/instructions/test_riscv_instruction_023.s index 0fcd4cba9..966b579d0 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_023.s +++ b/tests/arch/riscv/instructions/test_riscv_instruction_023.s @@ -17,5 +17,5 @@ main: sll x11, x5, x8 sll x12, x6, x9 sll x13, x7, x10 - - \ No newline at end of file + + jr ra diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_024.out b/tests/arch/riscv/instructions/test_riscv_instruction_024.out deleted file mode 100644 index 16aa3e8f5..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_024.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x30; ir[x4,tp]:0x1fff; ir[x5,t0]:0x2000; ir[x6,t1]:0x2001; ir[x7,t2]:0x2002; ir[x10,a0]:0x1; ir[x11,a1]:0x1; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_024.s b/tests/arch/riscv/instructions/test_riscv_instruction_024.s index ce6a1636a..bcaa66a29 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_024.s +++ b/tests/arch/riscv/instructions/test_riscv_instruction_024.s @@ -15,5 +15,5 @@ main: slt x9, x5, x5 slt x10, x5, x6 slt x11, x5, x7 - - \ No newline at end of file + + jr ra diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_025.out b/tests/arch/riscv/instructions/test_riscv_instruction_025.out deleted file mode 100644 index 16aa3e8f5..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_025.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x30; ir[x4,tp]:0x1fff; ir[x5,t0]:0x2000; ir[x6,t1]:0x2001; ir[x7,t2]:0x2002; ir[x10,a0]:0x1; ir[x11,a1]:0x1; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_025.s b/tests/arch/riscv/instructions/test_riscv_instruction_025.s index bb195955d..059c11d0b 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_025.s +++ b/tests/arch/riscv/instructions/test_riscv_instruction_025.s @@ -15,5 +15,5 @@ main: sltu x9, x5, x5 sltu x10, x5, x6 sltu x11, x5, x7 - - \ No newline at end of file + + jr ra diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_026.out b/tests/arch/riscv/instructions/test_riscv_instruction_026.out deleted file mode 100644 index 096e3c74a..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_026.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x34; ir[x5,t0]:0x22346; ir[x6,t1]:0x11d7; ir[x7,t2]:0xffffdaf2; ir[x8,fp,s0]:0x455; ir[x9,s1]:0x222; ir[x10,a0]:0xfff; ir[x11,a1]:0x22713; ir[x12,a2]:0x13f5; ir[x13,a3]:0xffffd50d; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_026.s b/tests/arch/riscv/instructions/test_riscv_instruction_026.s index a4a23438c..50ad86b15 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_026.s +++ b/tests/arch/riscv/instructions/test_riscv_instruction_026.s @@ -16,4 +16,5 @@ main: xor x11, x5, x8 xor x12, x6, x9 xor x13, x7, x10 - \ No newline at end of file + + jr ra diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_027.out b/tests/arch/riscv/instructions/test_riscv_instruction_027.out deleted file mode 100644 index 6f7aacc1f..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_027.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x30; ir[x5,t0]:0xaad4; ir[x6,t1]:0x11d7; ir[x7,t2]:0xffffdaf2; ir[x8,fp,s0]:0x2; ir[x9,s1]:0x1; ir[x10,a0]:0x554; ir[x11,a1]:0x2ab5; ir[x12,a2]:0x8eb; ir[x13,a3]:0xfff; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_027.s b/tests/arch/riscv/instructions/test_riscv_instruction_027.s index a4f9a6850..fa173b152 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_027.s +++ b/tests/arch/riscv/instructions/test_riscv_instruction_027.s @@ -17,5 +17,5 @@ main: srl x11, x5, x8 srl x12, x6, x9 srl x13, x7, x10 - - \ No newline at end of file + + jr ra diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_028.out b/tests/arch/riscv/instructions/test_riscv_instruction_028.out deleted file mode 100644 index 2e3bd4b04..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_028.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x30; ir[x5,t0]:0xaad4; ir[x6,t1]:0x11d7; ir[x7,t2]:0xffffdaf2; ir[x8,fp,s0]:0x2; ir[x9,s1]:0x1; ir[x10,a0]:0x3; ir[x11,a1]:0x2ab5; ir[x12,a2]:0x8eb; ir[x13,a3]:0xfffffb5e; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_028.s b/tests/arch/riscv/instructions/test_riscv_instruction_028.s index 6ee6c537d..fc827460c 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_028.s +++ b/tests/arch/riscv/instructions/test_riscv_instruction_028.s @@ -17,5 +17,5 @@ main: sra x11, x5, x8 sra x12, x6, x9 sra x13, x7, x10 - - \ No newline at end of file + + jr ra diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_029.out b/tests/arch/riscv/instructions/test_riscv_instruction_029.out deleted file mode 100644 index 24437a090..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_029.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x34; ir[x5,t0]:0x22346; ir[x6,t1]:0x11d7; ir[x7,t2]:0xffffdaf2; ir[x8,fp,s0]:0x455; ir[x9,s1]:0x222; ir[x10,a0]:0xfff; ir[x11,a1]:0x22757; ir[x12,a2]:0x13f7; ir[x13,a3]:0xffffdfff; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_029.s b/tests/arch/riscv/instructions/test_riscv_instruction_029.s index 0bb5ada10..75185d581 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_029.s +++ b/tests/arch/riscv/instructions/test_riscv_instruction_029.s @@ -17,4 +17,5 @@ main: or x11, x5, x8 or x12, x6, x9 or x13, x7, x10 - \ No newline at end of file + + jr ra diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_030.out b/tests/arch/riscv/instructions/test_riscv_instruction_030.out deleted file mode 100644 index 07949e23b..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_030.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x34; ir[x5,t0]:0x22346; ir[x6,t1]:0x11d7; ir[x7,t2]:0xffffdaf2; ir[x8,fp,s0]:0x455; ir[x9,s1]:0x222; ir[x10,a0]:0xfff; ir[x11,a1]:0x44; ir[x12,a2]:0x2; ir[x13,a3]:0xaf2; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_030.s b/tests/arch/riscv/instructions/test_riscv_instruction_030.s index af649328a..0a12873b1 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_030.s +++ b/tests/arch/riscv/instructions/test_riscv_instruction_030.s @@ -17,4 +17,5 @@ main: and x11, x5, x8 and x12, x6, x9 and x13, x7, x10 - \ No newline at end of file + + jr ra diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_031.out b/tests/arch/riscv/instructions/test_riscv_instruction_031.out deleted file mode 100644 index fa69ecb29..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_031.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x48; ir[x5,t0]:0x200000; ir[x6,t1]:0x200008; ir[x7,t2]:0x200010; ir[x8,fp,s0]:0x200028; ir[x17,a7]:0xa; fpr[f0,ft0]:0x404145A1CAC08312; fpr[f2,ft2]:0x4026E2D0E5604189; fpr[f10,fa0]:0x0000000007544FFB; memory[0x20002f]:0xFB; memory[0x20002e]:0x4F; memory[0x20002d]:0x54; memory[0x20002c]:0x07; memory[0x200027]:0x89; memory[0x200026]:0x41; memory[0x200025]:0x60; memory[0x200024]:0xE5; memory[0x200023]:0xD0; memory[0x200022]:0xE2; memory[0x200021]:0x26; memory[0x200020]:0x40; memory[0x20001f]:0x12; memory[0x20001e]:0x83; memory[0x20001d]:0xC0; memory[0x20001c]:0xCA; memory[0x20001b]:0xA1; memory[0x20001a]:0x45; memory[0x200019]:0x41; memory[0x200018]:0x40; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_032.out b/tests/arch/riscv/instructions/test_riscv_instruction_032.out deleted file mode 100644 index 3b389b284..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_032.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x24; ir[x5,t0]:0xaad4; ir[x6,t1]:0x11d7; ir[x7,t2]:0xffffdaf2; ir[x11,a1]:0x2ab50; ir[x12,a2]:0x23ae; ir[x13,a3]:0xed790000; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_032.s b/tests/arch/riscv/instructions/test_riscv_instruction_032.s index 3eb06ea4d..961877008 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_032.s +++ b/tests/arch/riscv/instructions/test_riscv_instruction_032.s @@ -13,5 +13,5 @@ main: slli x11, x5, 2 slli x12, x6, 1 slli x13, x7, 15 - - \ No newline at end of file + + jr ra diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_033.out b/tests/arch/riscv/instructions/test_riscv_instruction_033.out deleted file mode 100644 index 2457c5412..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_033.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x24; ir[x5,t0]:0xaad4; ir[x6,t1]:0x11d7; ir[x7,t2]:0xffffdaf2; ir[x8,fp,s0]:0x2ab5; ir[x9,s1]:0x8eb; ir[x10,a0]:0x1ffff; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_033.s b/tests/arch/riscv/instructions/test_riscv_instruction_033.s index b5ef81c57..f3d4b7a91 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_033.s +++ b/tests/arch/riscv/instructions/test_riscv_instruction_033.s @@ -13,5 +13,5 @@ main: srli x8, x5, 2 srli x9, x6, 1 srli x10, x7, 15 - - \ No newline at end of file + + jr ra diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_034.out b/tests/arch/riscv/instructions/test_riscv_instruction_034.out deleted file mode 100644 index 11914d179..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_034.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x20; ir[x5,t0]:0xa; ir[x6,t1]:0xd; ir[x7,t2]:0x2d; ir[x8,fp,s0]:0xfffffffe; ir[x9,s1]:0x82; ir[x10,a0]:0x249; ir[x11,a1]:0xffffffa6; ir[x12,a2]:0xffffffec; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_034.s b/tests/arch/riscv/instructions/test_riscv_instruction_034.s index 2febf9bb1..5f4dd8861 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_034.s +++ b/tests/arch/riscv/instructions/test_riscv_instruction_034.s @@ -14,4 +14,6 @@ main: mul x9, x5, x6 mul x10, x6, x7 mul x11, x7, x8 - mul x12, x8, x5 \ No newline at end of file + mul x12, x8, x5 + + jr ra diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_035.out b/tests/arch/riscv/instructions/test_riscv_instruction_035.out deleted file mode 100644 index 11914d179..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_035.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x20; ir[x5,t0]:0xa; ir[x6,t1]:0xd; ir[x7,t2]:0x2d; ir[x8,fp,s0]:0xfffffffe; ir[x9,s1]:0x82; ir[x10,a0]:0x249; ir[x11,a1]:0xffffffa6; ir[x12,a2]:0xffffffec; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_035.s b/tests/arch/riscv/instructions/test_riscv_instruction_035.s index 22d187c2e..ba7eadb3f 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_035.s +++ b/tests/arch/riscv/instructions/test_riscv_instruction_035.s @@ -14,4 +14,6 @@ main: mulh x9, x5, x6 mulh x10, x6, x7 mulh x11, x7, x8 - mulh x12, x8, x5 \ No newline at end of file + mulh x12, x8, x5 + + jr ra diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_036.out b/tests/arch/riscv/instructions/test_riscv_instruction_036.out deleted file mode 100644 index 11914d179..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_036.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x20; ir[x5,t0]:0xa; ir[x6,t1]:0xd; ir[x7,t2]:0x2d; ir[x8,fp,s0]:0xfffffffe; ir[x9,s1]:0x82; ir[x10,a0]:0x249; ir[x11,a1]:0xffffffa6; ir[x12,a2]:0xffffffec; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_036.s b/tests/arch/riscv/instructions/test_riscv_instruction_036.s index 21bd31725..8d8b115f9 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_036.s +++ b/tests/arch/riscv/instructions/test_riscv_instruction_036.s @@ -14,4 +14,6 @@ main: mulhsu x9, x5, x6 mulhsu x10, x6, x7 mulhsu x11, x7, x8 - mulhsu x12, x8, x5 \ No newline at end of file + mulhsu x12, x8, x5 + + jr ra diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_037.out b/tests/arch/riscv/instructions/test_riscv_instruction_037.out deleted file mode 100644 index 11914d179..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_037.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x20; ir[x5,t0]:0xa; ir[x6,t1]:0xd; ir[x7,t2]:0x2d; ir[x8,fp,s0]:0xfffffffe; ir[x9,s1]:0x82; ir[x10,a0]:0x249; ir[x11,a1]:0xffffffa6; ir[x12,a2]:0xffffffec; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_037.s b/tests/arch/riscv/instructions/test_riscv_instruction_037.s index d8aa6bcb8..f2e4855d8 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_037.s +++ b/tests/arch/riscv/instructions/test_riscv_instruction_037.s @@ -14,4 +14,6 @@ main: mulhu x9, x5, x6 mulhu x10, x6, x7 mulhu x11, x7, x8 - mulhu x12, x8, x5 \ No newline at end of file + mulhu x12, x8, x5 + + jr ra diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_038.out b/tests/arch/riscv/instructions/test_riscv_instruction_038.out deleted file mode 100644 index c4e091cd4..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_038.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x24; ir[x5,t0]:0x10; ir[x6,t1]:0x100; ir[x7,t2]:0xffffe000; ir[x8,fp,s0]:0x18; ir[x9,s1]:0xfffffe00; ir[x10,a0]:0x10; ir[x11,a1]:0xfffffeab; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_038.s b/tests/arch/riscv/instructions/test_riscv_instruction_038.s index 872c90619..c4dc3fa11 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_038.s +++ b/tests/arch/riscv/instructions/test_riscv_instruction_038.s @@ -14,4 +14,6 @@ main: div x9, x7, x5 div x10, x6, x5 div x11, x7, x8 - div x12, x8, x7 \ No newline at end of file + div x12, x8, x7 + + jr ra diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_039.out b/tests/arch/riscv/instructions/test_riscv_instruction_039.out deleted file mode 100644 index 8308a6c53..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_039.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x24; ir[x5,t0]:0x10; ir[x6,t1]:0x100; ir[x7,t2]:0xffffe000; ir[x8,fp,s0]:0x18; ir[x9,s1]:0xffffe00; ir[x10,a0]:0x10; ir[x11,a1]:0xaaaa955; ir[x12,a2]:0x5; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_039.s b/tests/arch/riscv/instructions/test_riscv_instruction_039.s index e3e35296c..73d502bcd 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_039.s +++ b/tests/arch/riscv/instructions/test_riscv_instruction_039.s @@ -14,4 +14,6 @@ main: divu x9, x7, x5 divu x10, x6, x5 divu x11, x7, x8 - divu x12, x8, x7 \ No newline at end of file + divu x12, x8, x7 + + jr ra diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_040.out b/tests/arch/riscv/instructions/test_riscv_instruction_040.out deleted file mode 100644 index a6c4184e4..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_040.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x24; ir[x5,t0]:0x10; ir[x6,t1]:0x100; ir[x7,t2]:0xffffe000; ir[x8,fp,s0]:0x18; ir[x11,a1]:0x8; ir[x12,a2]:0x18; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_040.s b/tests/arch/riscv/instructions/test_riscv_instruction_040.s index 1646350c8..ebc40381d 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_040.s +++ b/tests/arch/riscv/instructions/test_riscv_instruction_040.s @@ -14,4 +14,6 @@ main: rem x9, x7, x5 rem x10, x6, x5 rem x11, x7, x8 - rem x12, x8, x7 \ No newline at end of file + rem x12, x8, x7 + + jr ra diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_041.out b/tests/arch/riscv/instructions/test_riscv_instruction_041.out deleted file mode 100644 index a6c4184e4..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_041.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x24; ir[x5,t0]:0x10; ir[x6,t1]:0x100; ir[x7,t2]:0xffffe000; ir[x8,fp,s0]:0x18; ir[x11,a1]:0x8; ir[x12,a2]:0x18; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_041.s b/tests/arch/riscv/instructions/test_riscv_instruction_041.s index 8f0998d68..09ac24249 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_041.s +++ b/tests/arch/riscv/instructions/test_riscv_instruction_041.s @@ -14,4 +14,6 @@ main: remu x9, x7, x5 remu x10, x6, x5 remu x11, x7, x8 - remu x12, x8, x7 \ No newline at end of file + remu x12, x8, x7 + + jr ra diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_042.out b/tests/arch/riscv/instructions/test_riscv_instruction_042.out deleted file mode 100644 index d540a9815..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_042.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x24; ir[x5,t0]:0xb; ir[x6,t1]:0x22b; ir[x7,t2]:0x5; ir[x8,fp,s0]:0x21f; ir[x17,a7]:0xa; ir[x28,t3]:0x22; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_043.out b/tests/arch/riscv/instructions/test_riscv_instruction_043.out deleted file mode 100644 index d540a9815..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_043.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x24; ir[x5,t0]:0xb; ir[x6,t1]:0x22b; ir[x7,t2]:0x5; ir[x8,fp,s0]:0x21f; ir[x17,a7]:0xa; ir[x28,t3]:0x22; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_044.out b/tests/arch/riscv/instructions/test_riscv_instruction_044.out deleted file mode 100644 index d540a9815..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_044.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x24; ir[x5,t0]:0xb; ir[x6,t1]:0x22b; ir[x7,t2]:0x5; ir[x8,fp,s0]:0x21f; ir[x17,a7]:0xa; ir[x28,t3]:0x22; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_045.out b/tests/arch/riscv/instructions/test_riscv_instruction_045.out deleted file mode 100644 index 4b5977236..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_045.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x24; ir[x5,t0]:0xb; ir[x6,t1]:0xfffffdd5; ir[x7,t2]:0x5; ir[x8,fp,s0]:0xfffffde1; ir[x17,a7]:0xa; ir[x28,t3]:0x22; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_046.out b/tests/arch/riscv/instructions/test_riscv_instruction_046.out deleted file mode 100644 index 5c8366988..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_046.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x24; ir[x5,t0]:0x22346; ir[x6,t1]:0x11d7; ir[x7,t2]:0xffffdaf2; ir[x8,fp,s0]:0xfffddcb9; ir[x9,s1]:0xffffee28; ir[x10,a0]:0x250d; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_046.s b/tests/arch/riscv/instructions/test_riscv_instruction_046.s index 4d6501f09..df1b8b884 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_046.s +++ b/tests/arch/riscv/instructions/test_riscv_instruction_046.s @@ -13,4 +13,5 @@ main: not x8, x5 not x9, x6 not x10, x7 - \ No newline at end of file + + jr ra diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_047.out b/tests/arch/riscv/instructions/test_riscv_instruction_047.out deleted file mode 100644 index e899ec914..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_047.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x24; ir[x5,t0]:0x22346; ir[x6,t1]:0x11d7; ir[x7,t2]:0xffffdaf2; ir[x8,fp,s0]:0xfffddcba; ir[x9,s1]:0xffffee29; ir[x10,a0]:0x250e; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_047.s b/tests/arch/riscv/instructions/test_riscv_instruction_047.s index a2dafd5c6..1cdb1fb66 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_047.s +++ b/tests/arch/riscv/instructions/test_riscv_instruction_047.s @@ -13,4 +13,5 @@ main: neg x8, x5 neg x9, x6 neg x10, x7 - \ No newline at end of file + + jr ra diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_048.out b/tests/arch/riscv/instructions/test_riscv_instruction_048.out deleted file mode 100644 index 79919eac7..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_048.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x18; ir[x4,tp]:0x1; ir[x6,t1]:0xffffffff; ir[x9,s1]:0x1; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_048.s b/tests/arch/riscv/instructions/test_riscv_instruction_048.s index 9f2ef07ea..433c21075 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_048.s +++ b/tests/arch/riscv/instructions/test_riscv_instruction_048.s @@ -13,5 +13,5 @@ main: seqz x8, x4 seqz x9, x5 seqz x10, x6 - - \ No newline at end of file + + jr ra diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_049.out b/tests/arch/riscv/instructions/test_riscv_instruction_049.out deleted file mode 100644 index 468629a21..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_049.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x18; ir[x4,tp]:0x1; ir[x6,t1]:0xffffffff; ir[x8,fp,s0]:0x1; ir[x10,a0]:0x1; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_049.s b/tests/arch/riscv/instructions/test_riscv_instruction_049.s index 506fd2134..efac8dc73 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_049.s +++ b/tests/arch/riscv/instructions/test_riscv_instruction_049.s @@ -13,5 +13,5 @@ main: snez x8, x4 snez x9, x5 snez x10, x6 - - \ No newline at end of file + + jr ra diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_050.out b/tests/arch/riscv/instructions/test_riscv_instruction_050.out deleted file mode 100644 index 3fe384ae6..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_050.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x18; ir[x4,tp]:0x1; ir[x6,t1]:0xffffffff; ir[x8,fp,s0]:0x1; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_050.s b/tests/arch/riscv/instructions/test_riscv_instruction_050.s index 8a89e59bd..c6cbd74d1 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_050.s +++ b/tests/arch/riscv/instructions/test_riscv_instruction_050.s @@ -13,5 +13,5 @@ main: sgtz x8, x4 sgtz x9, x5 sgtz x10, x6 - - \ No newline at end of file + + jr ra diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_051.out b/tests/arch/riscv/instructions/test_riscv_instruction_051.out deleted file mode 100644 index e2fa0a4f7..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_051.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x18; ir[x4,tp]:0x1; ir[x6,t1]:0xffffffff; ir[x10,a0]:0x1; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_051.s b/tests/arch/riscv/instructions/test_riscv_instruction_051.s index 4f1efa007..4104e8ddb 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_051.s +++ b/tests/arch/riscv/instructions/test_riscv_instruction_051.s @@ -13,5 +13,5 @@ main: sltz x8, x4 sltz x9, x5 sltz x10, x6 - - \ No newline at end of file + + jr ra diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_052.out b/tests/arch/riscv/instructions/test_riscv_instruction_052.out deleted file mode 100644 index 2072776ab..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_052.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x68; ir[x5,t0]:0x200000; ir[x6,t1]:0x200008; ir[x7,t2]:0x200010; ir[x8,fp,s0]:0x200018; ir[x9,s1]:0x20001c; ir[x10,a0]:0x200020; ir[x17,a7]:0xa; fpr[f0,ft0]:0x408354FA6DEFC7A4; fpr[f2,ft2]:0x408C12C083126E98; fpr[f4,ft4]:0x40C35CC666666666; fpr[f6,ft6]:0x409354FA6DEFC7A4; fpr[f8,fs0]:0x409C12C083126E98; fpr[f10,fa0]:0x40D35CC666666666; fpr[f12,fa2]:0xffffffff42F73E9B; fpr[f14,fa4]:0xffffffff43E42C08; fpr[f16,fa6]:0xffffffffC5EC1466; fpr[f18,fs2]:0xffffffff4410FDD7; fpr[f20,fs4]:0xffffffffC5DDD1A6; fpr[f22,fs6]:0xffffffffC5E8376C; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_053.out b/tests/arch/riscv/instructions/test_riscv_instruction_053.out deleted file mode 100644 index 15fb6e89e..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_053.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x68; ir[x5,t0]:0x200000; ir[x6,t1]:0x200008; ir[x7,t2]:0x200010; ir[x8,fp,s0]:0x200018; ir[x9,s1]:0x20001c; ir[x10,a0]:0x200020; ir[x17,a7]:0xa; fpr[f0,ft0]:0x408354FA6DEFC7A4; fpr[f2,ft2]:0x408C12C083126E98; fpr[f4,ft4]:0x40C35CC666666666; fpr[f6,ft6]:0xC0717B8C2A454DE8; fpr[f8,fs0]:0xC0C19B9A5E353F7C; fpr[f10,fa0]:0x40C22776BF8769EC; fpr[f12,fa2]:0xffffffff42F73E9B; fpr[f14,fa4]:0xffffffff43E42C08; fpr[f16,fa6]:0xffffffffC5EC1466; fpr[f18,fs2]:0xffffffffC3A65C61; fpr[f20,fs4]:0xffffffff45FA5726; fpr[f22,fs6]:0xffffffffC5EFF160; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_054.out b/tests/arch/riscv/instructions/test_riscv_instruction_054.out deleted file mode 100644 index fe84e09e1..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_054.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x68; ir[x5,t0]:0x200000; ir[x6,t1]:0x200008; ir[x7,t2]:0x200010; ir[x8,fp,s0]:0x200018; ir[x9,s1]:0x20001c; ir[x10,a0]:0x200020; ir[x17,a7]:0xa; fpr[f0,ft0]:0x408354FA6DEFC7A4; fpr[f2,ft2]:0x408C12C083126E98; fpr[f4,ft4]:0x40C35CC666666666; fpr[f6,ft6]:0x41175B9619EB7E4E; fpr[f8,fs0]:0x4128A0DBE279DD3C; fpr[f10,fa0]:0x41976E712668F5C2; fpr[f12,fa2]:0xffffffff42F73E9B; fpr[f14,fa4]:0xffffffff43E42C08; fpr[f16,fa6]:0xffffffffC5EC1466; fpr[f18,fs2]:0xffffffff475C5E49; fpr[f20,fs4]:0xffffffffCA526AC6; fpr[f22,fs6]:0xffffffffC964016A; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_055.out b/tests/arch/riscv/instructions/test_riscv_instruction_055.out deleted file mode 100644 index 492f0cd5a..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_055.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x68; ir[x5,t0]:0x200000; ir[x6,t1]:0x200008; ir[x7,t2]:0x200010; ir[x8,fp,s0]:0x200018; ir[x9,s1]:0x20001c; ir[x10,a0]:0x200020; ir[x17,a7]:0xa; fpr[f0,ft0]:0x408354FA6DEFC7A4; fpr[f2,ft2]:0x408C12C083126E98; fpr[f4,ft4]:0x40C35CC666666666; fpr[f6,ft6]:0x3FF0000000000000; fpr[f8,fs0]:0x3FF0000000000000; fpr[f10,fa0]:0x3FF0000000000000; fpr[f12,fa2]:0xffffffff42F73E9B; fpr[f14,fa4]:0xffffffff43E42C08; fpr[f16,fa6]:0xffffffffC5EC1466; fpr[f18,fs2]:0xffffffff3E8AB307; fpr[f20,fs4]:0xffffffffBD776CD1; fpr[f22,fs6]:0xffffffffC2747094; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_056.out b/tests/arch/riscv/instructions/test_riscv_instruction_056.out deleted file mode 100644 index 3408223c1..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_056.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x68; ir[x5,t0]:0x200000; ir[x6,t1]:0x200008; ir[x7,t2]:0x200010; ir[x8,fp,s0]:0x200018; ir[x9,s1]:0x20001c; ir[x10,a0]:0x200020; ir[x17,a7]:0xa; fpr[f0,ft0]:0x408354FA6DEFC7A4; fpr[f2,ft2]:0x408C12C083126E98; fpr[f4,ft4]:0x40C35CC666666666; fpr[f6,ft6]:0x408354FA6DEFC7A4; fpr[f8,fs0]:0x408C12C083126E98; fpr[f10,fa0]:0x408354FA6DEFC7A4; fpr[f12,fa2]:0xffffffff42F73E9B; fpr[f14,fa4]:0xffffffff43E42C08; fpr[f16,fa6]:0xffffffffC5EC1466; fpr[f18,fs2]:0xffffffff42F73E9B; fpr[f20,fs4]:0xffffffffC5EC1466; fpr[f22,fs6]:0xffffffffC5EC1466; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_057.out b/tests/arch/riscv/instructions/test_riscv_instruction_057.out deleted file mode 100644 index 88886b8b8..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_057.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x68; ir[x5,t0]:0x200000; ir[x6,t1]:0x200008; ir[x7,t2]:0x200010; ir[x8,fp,s0]:0x200018; ir[x9,s1]:0x20001c; ir[x10,a0]:0x200020; ir[x17,a7]:0xa; fpr[f0,ft0]:0x408354FA6DEFC7A4; fpr[f2,ft2]:0x408C12C083126E98; fpr[f4,ft4]:0x40C35CC666666666; fpr[f6,ft6]:0x408C12C083126E98; fpr[f8,fs0]:0x40C35CC666666666; fpr[f10,fa0]:0x40C35CC666666666; fpr[f12,fa2]:0xffffffff42F73E9B; fpr[f14,fa4]:0xffffffff43E42C08; fpr[f16,fa6]:0xffffffffC5EC1466; fpr[f18,fs2]:0xffffffff43E42C08; fpr[f20,fs4]:0xffffffff43E42C08; fpr[f22,fs6]:0xffffffff42F73E9B; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_058.out b/tests/arch/riscv/instructions/test_riscv_instruction_058.out deleted file mode 100644 index 149d7c395..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_058.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x68; ir[x5,t0]:0x200000; ir[x6,t1]:0x200008; ir[x7,t2]:0x200010; ir[x8,fp,s0]:0x200018; ir[x9,s1]:0x20001c; ir[x10,a0]:0x200020; ir[x17,a7]:0xa; fpr[f0,ft0]:0x4070000000000000; fpr[f2,ft2]:0x40AB320000000000; fpr[f4,ft4]:0x40B5640000000000; fpr[f6,ft6]:0xffffffff42C60000; fpr[f8,fs0]:0xffffffff42B60000; fpr[f10,fa0]:0xffffffff42C00000; fpr[f12,fa2]:0xffffffff46192400; fpr[f14,fa4]:0xffffffff46016400; fpr[f16,fa6]:0xffffffff46100000; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_059.out b/tests/arch/riscv/instructions/test_riscv_instruction_059.out deleted file mode 100644 index d5d9b9daf..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_059.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x68; ir[x5,t0]:0x200000; ir[x6,t1]:0x200008; ir[x7,t2]:0x200010; ir[x8,fp,s0]:0x200018; ir[x9,s1]:0x20001c; ir[x10,a0]:0x200020; ir[x17,a7]:0xa; fpr[f0,ft0]:0x4070000000000000; fpr[f2,ft2]:0x40AB320000000000; fpr[f4,ft4]:0x40B5640000000000; fpr[f6,ft6]:0xffffffff4CB73CE3; fpr[f8,fs0]:0xffffffff4C82CFE9; fpr[f10,fa0]:0xffffffff4CA20480; fpr[f12,fa2]:0xffffffff46192400; fpr[f14,fa4]:0xffffffff46016400; fpr[f16,fa6]:0xffffffff46100000; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_060.out b/tests/arch/riscv/instructions/test_riscv_instruction_060.out deleted file mode 100644 index 061097777..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_060.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x68; ir[x5,t0]:0x200000; ir[x6,t1]:0x200008; ir[x7,t2]:0x200010; ir[x8,fp,s0]:0x200018; ir[x9,s1]:0x20001c; ir[x10,a0]:0x200020; ir[x17,a7]:0xa; fpr[f0,ft0]:0x4070000000000000; fpr[f2,ft2]:0x40AB320000000000; fpr[f4,ft4]:0x40B5640000000000; fpr[f6,ft6]:0xffffffff4CB73351; fpr[f8,fs0]:0xffffffff4C82C7D3; fpr[f10,fa0]:0xffffffff4CA1FB80; fpr[f12,fa2]:0xffffffff46192400; fpr[f14,fa4]:0xffffffff46016400; fpr[f16,fa6]:0xffffffff46100000; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_061.out b/tests/arch/riscv/instructions/test_riscv_instruction_061.out deleted file mode 100644 index 30306dda4..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_061.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x68; ir[x5,t0]:0x200000; ir[x6,t1]:0x200008; ir[x7,t2]:0x200010; ir[x8,fp,s0]:0x200018; ir[x9,s1]:0x20001c; ir[x10,a0]:0x200020; ir[x17,a7]:0xa; fpr[f0,ft0]:0x4070000000000000; fpr[f2,ft2]:0xC0AB320000000000; fpr[f4,ft4]:0x40B5640000000000; fpr[f6,ft6]:0x4070000000000000; fpr[f8,fs0]:0x40AB320000000000; fpr[f10,fa0]:0x40B5640000000000; fpr[f12,fa2]:0xffffffffC6192400; fpr[f14,fa4]:0xffffffff46016400; fpr[f16,fa6]:0xffffffffC6100000; fpr[f18,fs2]:0xffffffff46192400; fpr[f20,fs4]:0xffffffff46016400; fpr[f22,fs6]:0xffffffff46100000; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_062.out b/tests/arch/riscv/instructions/test_riscv_instruction_062.out deleted file mode 100644 index 074efd0ac..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_062.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x68; ir[x5,t0]:0x200000; ir[x6,t1]:0x200008; ir[x7,t2]:0x200010; ir[x8,fp,s0]:0x200018; ir[x9,s1]:0x20001c; ir[x10,a0]:0x200020; ir[x17,a7]:0xa; fpr[f0,ft0]:0x4070000000000000; fpr[f2,ft2]:0xC0AB320000000000; fpr[f4,ft4]:0x40B5640000000000; fpr[f6,ft6]:0xC070000000000000; fpr[f8,fs0]:0x40AB320000000000; fpr[f10,fa0]:0xC0B5640000000000; fpr[f12,fa2]:0xffffffffC6192400; fpr[f14,fa4]:0xffffffff46016400; fpr[f16,fa6]:0xffffffffC6100000; fpr[f18,fs2]:0xffffffff46192400; fpr[f20,fs4]:0xffffffffC6016400; fpr[f22,fs6]:0xffffffff46100000; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_063.out b/tests/arch/riscv/instructions/test_riscv_instruction_063.out deleted file mode 100644 index 24c2f0562..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_063.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x40; ir[x5,t0]:0x200000; ir[x6,t1]:0x200008; ir[x8,fp,s0]:0x200010; ir[x9,s1]:0x200014; ir[x11,a1]:0x1; ir[x17,a7]:0xa; fpr[f0,ft0]:0x4070000000000000; fpr[f2,ft2]:0x40AB320000000000; fpr[f12,fa2]:0xffffffff46192400; fpr[f14,fa4]:0xffffffff46192400; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_063.s b/tests/arch/riscv/instructions/test_riscv_instruction_063.s index c3b0ab67b..395757004 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_063.s +++ b/tests/arch/riscv/instructions/test_riscv_instruction_063.s @@ -6,26 +6,42 @@ .data a: .double 256.0 b: .double 3481.0 + c: .double NaN d: .float 9801.0 - e: .float 9801.0 + e: .float 10502.5 + f: .double NaN .text main: - la x5, a - la x6, b - la x8, d - la x9, e + la x5, a + la x6, b + la x7, c + la x8, d + la x9, e + la x10, f fld f0, 0(x5) fld f2, 0(x6) + fld f4, 0(x7) - feq.d x10, f0, f2 + feq.d x11, f0, f0 + feq.d x12, f2, f2 + feq.d x13, f0, f2 + feq.d x14, f2, f0 + feq.d x15, f0, f4 + feq.d x16, f4, f4 flw f12, 0(x8) flw f14, 0(x9) + flw f16, 0(x10) - feq.s x11, f12, f14 + feq.s x17, f12, f12 + feq.s x18, f14, f14 + feq.s x19, f12, f14 + feq.s x20, f14, f12 + feq.s x21, f12, f16 + feq.s x22, f16, f16 li a7, 10 ecall diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_064.out b/tests/arch/riscv/instructions/test_riscv_instruction_064.out deleted file mode 100644 index 96c1e52c8..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_064.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x40; ir[x5,t0]:0x200000; ir[x6,t1]:0x200008; ir[x8,fp,s0]:0x200010; ir[x9,s1]:0x200014; ir[x10,a0]:0x1; ir[x11,a1]:0x1; ir[x17,a7]:0xa; fpr[f0,ft0]:0x4070000000000000; fpr[f2,ft2]:0x40AB320000000000; fpr[f12,fa2]:0xffffffff46192400; fpr[f14,fa4]:0xffffffff46192400; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_064.s b/tests/arch/riscv/instructions/test_riscv_instruction_064.s index bc3634cf7..4edf15363 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_064.s +++ b/tests/arch/riscv/instructions/test_riscv_instruction_064.s @@ -6,26 +6,42 @@ .data a: .double 256.0 b: .double 3481.0 + c: .double NaN d: .float 9801.0 - e: .float 9801.0 + e: .float 10502.5 + f: .double NaN .text main: - la x5, a - la x6, b - la x8, d - la x9, e + la x5, a + la x6, b + la x7, c + la x8, d + la x9, e + la x10, f fld f0, 0(x5) fld f2, 0(x6) + fld f4, 0(x7) - fle.d x10, f0, f2 + fle.d x11, f0, f0 + fle.d x12, f2, f2 + fle.d x13, f0, f2 + fle.d x14, f2, f0 + fle.d x15, f0, f4 + fle.d x16, f4, f4 flw f12, 0(x8) flw f14, 0(x9) + flw f16, 0(x10) - fle.s x11, f12, f14 + fle.s x17, f12, f12 + fle.s x18, f14, f14 + fle.s x19, f12, f14 + fle.s x20, f14, f12 + fle.s x21, f12, f16 + fle.s x22, f16, f16 li a7, 10 ecall diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_065.out b/tests/arch/riscv/instructions/test_riscv_instruction_065.out deleted file mode 100644 index 626ebf364..000000000 --- a/tests/arch/riscv/instructions/test_riscv_instruction_065.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x40; ir[x5,t0]:0x200000; ir[x6,t1]:0x200008; ir[x8,fp,s0]:0x200010; ir[x9,s1]:0x200014; ir[x10,a0]:0x1; ir[x17,a7]:0xa; fpr[f0,ft0]:0x4070000000000000; fpr[f2,ft2]:0x40AB320000000000; fpr[f12,fa2]:0xffffffff46192400; fpr[f14,fa4]:0xffffffff46192400; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_065.s b/tests/arch/riscv/instructions/test_riscv_instruction_065.s index 43942b9b5..6f9a6b693 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_065.s +++ b/tests/arch/riscv/instructions/test_riscv_instruction_065.s @@ -6,26 +6,42 @@ .data a: .double 256.0 b: .double 3481.0 + c: .double NaN d: .float 9801.0 - e: .float 9801.0 + e: .float 10502.5 + f: .double NaN .text main: - la x5, a - la x6, b - la x8, d - la x9, e + la x5, a + la x6, b + la x7, c + la x8, d + la x9, e + la x10, f fld f0, 0(x5) fld f2, 0(x6) + fld f4, 0(x7) - flt.d x10, f0, f2 + flt.d x11, f0, f0 + flt.d x12, f2, f2 + flt.d x13, f0, f2 + flt.d x14, f2, f0 + flt.d x15, f0, f4 + flt.d x16, f4, f4 flw f12, 0(x8) flw f14, 0(x9) + flw f16, 0(x10) - flt.s x11, f12, f14 + flt.s x17, f12, f12 + flt.s x18, f14, f14 + flt.s x19, f12, f14 + flt.s x20, f14, f12 + flt.s x21, f12, f16 + flt.s x22, f16, f16 li a7, 10 ecall diff --git a/tests/arch/riscv/sentinel/test_riscv_sentinels_001.out b/tests/arch/riscv/sentinel/test_riscv_sentinels_001.out deleted file mode 100644 index ec02416fe..000000000 --- a/tests/arch/riscv/sentinel/test_riscv_sentinels_001.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x10; ir[x1,ra]:0x8; ir[x10,a0]:0x2; ir[x17,a7]:0xa; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/sentinel/test_riscv_sentinels_002.out b/tests/arch/riscv/sentinel/test_riscv_sentinels_002.out deleted file mode 100644 index f63ccfd64..000000000 --- a/tests/arch/riscv/sentinel/test_riscv_sentinels_002.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x10; ir[x1,ra]:0x8; ir[x11,a1]:0x2; ir[x17,a7]:0xa; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/sentinel/test_riscv_sentinels_003.out b/tests/arch/riscv/sentinel/test_riscv_sentinels_003.out deleted file mode 100644 index 1f2506910..000000000 --- a/tests/arch/riscv/sentinel/test_riscv_sentinels_003.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x10; ir[x1,ra]:0x8; ir[x12,a2]:0x2; ir[x17,a7]:0xa; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/sentinel/test_riscv_sentinels_004.out b/tests/arch/riscv/sentinel/test_riscv_sentinels_004.out deleted file mode 100644 index 2078e8118..000000000 --- a/tests/arch/riscv/sentinel/test_riscv_sentinels_004.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x10; ir[x1,ra]:0x8; ir[x13,a3]:0x2; ir[x17,a7]:0xa; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/sentinel/test_riscv_sentinels_005.out b/tests/arch/riscv/sentinel/test_riscv_sentinels_005.out deleted file mode 100644 index 661a7d162..000000000 --- a/tests/arch/riscv/sentinel/test_riscv_sentinels_005.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x10; ir[x1,ra]:0x8; ir[x14,a4]:0x2; ir[x17,a7]:0xa; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/sentinel/test_riscv_sentinels_006.out b/tests/arch/riscv/sentinel/test_riscv_sentinels_006.out deleted file mode 100644 index 459d42467..000000000 --- a/tests/arch/riscv/sentinel/test_riscv_sentinels_006.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x10; ir[x1,ra]:0x8; ir[x15,a5]:0x2; ir[x17,a7]:0xa; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/sentinel/test_riscv_sentinels_007.out b/tests/arch/riscv/sentinel/test_riscv_sentinels_007.out deleted file mode 100644 index 975dc033b..000000000 --- a/tests/arch/riscv/sentinel/test_riscv_sentinels_007.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x10; ir[x1,ra]:0x8; ir[x16,a6]:0x2; ir[x17,a7]:0xa; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/sentinel/test_riscv_sentinels_008.out b/tests/arch/riscv/sentinel/test_riscv_sentinels_008.out deleted file mode 100644 index d41f24c40..000000000 --- a/tests/arch/riscv/sentinel/test_riscv_sentinels_008.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x10; ir[x1,ra]:0x8; ir[x17,a7]:0xa; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/sentinel/test_riscv_sentinels_009.out b/tests/arch/riscv/sentinel/test_riscv_sentinels_009.out deleted file mode 100644 index b1f6ae203..000000000 --- a/tests/arch/riscv/sentinel/test_riscv_sentinels_009.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x14; ir[x1,ra]:0xc; ir[x5,t0]:0x2; ir[x10,a0]:0x5; ir[x17,a7]:0xa; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/sentinel/test_riscv_sentinels_010.out b/tests/arch/riscv/sentinel/test_riscv_sentinels_010.out deleted file mode 100644 index 0bacf9fc3..000000000 --- a/tests/arch/riscv/sentinel/test_riscv_sentinels_010.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x14; ir[x1,ra]:0xc; ir[x6,t1]:0x2; ir[x10,a0]:0x5; ir[x17,a7]:0xa; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/sentinel/test_riscv_sentinels_011.out b/tests/arch/riscv/sentinel/test_riscv_sentinels_011.out deleted file mode 100644 index dfb9e1353..000000000 --- a/tests/arch/riscv/sentinel/test_riscv_sentinels_011.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x14; ir[x1,ra]:0xc; ir[x7,t2]:0x2; ir[x10,a0]:0x5; ir[x17,a7]:0xa; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/sentinel/test_riscv_sentinels_012.out b/tests/arch/riscv/sentinel/test_riscv_sentinels_012.out deleted file mode 100644 index 7589a33bc..000000000 --- a/tests/arch/riscv/sentinel/test_riscv_sentinels_012.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x14; ir[x1,ra]:0xc; ir[x10,a0]:0x5; ir[x17,a7]:0xa; ir[x28,t3]:0x2; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/sentinel/test_riscv_sentinels_013.out b/tests/arch/riscv/sentinel/test_riscv_sentinels_013.out deleted file mode 100644 index ae29f2f30..000000000 --- a/tests/arch/riscv/sentinel/test_riscv_sentinels_013.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x14; ir[x1,ra]:0xc; ir[x10,a0]:0x5; ir[x17,a7]:0xa; ir[x29,t4]:0x2; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/sentinel/test_riscv_sentinels_014.out b/tests/arch/riscv/sentinel/test_riscv_sentinels_014.out deleted file mode 100644 index 95447ea10..000000000 --- a/tests/arch/riscv/sentinel/test_riscv_sentinels_014.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x14; ir[x1,ra]:0xc; ir[x10,a0]:0x5; ir[x17,a7]:0xa; ir[x30,t5]:0x2; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/sentinel/test_riscv_sentinels_015.out b/tests/arch/riscv/sentinel/test_riscv_sentinels_015.out deleted file mode 100644 index c376cd77f..000000000 --- a/tests/arch/riscv/sentinel/test_riscv_sentinels_015.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x14; ir[x1,ra]:0xc; ir[x10,a0]:0x5; ir[x17,a7]:0xa; ir[x31,t6]:0x2; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/sentinel/test_riscv_sentinels_016.out b/tests/arch/riscv/sentinel/test_riscv_sentinels_016.out deleted file mode 100644 index 4c91bfdcb..000000000 --- a/tests/arch/riscv/sentinel/test_riscv_sentinels_016.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x10; ir[x1,ra]:0x8; ir[x8,fp,s0]:0x5; ir[x17,a7]:0xa; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/sentinel/test_riscv_sentinels_017.out b/tests/arch/riscv/sentinel/test_riscv_sentinels_017.out deleted file mode 100644 index f57049ea3..000000000 --- a/tests/arch/riscv/sentinel/test_riscv_sentinels_017.out +++ /dev/null @@ -1,4 +0,0 @@ - -DANGER: Possible failure in the parameter passing convention -cr[PC]:0x10; ir[x1,ra]:0x8; ir[x9,s1]:0x2; ir[x17,a7]:0xa; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/sentinel/test_riscv_sentinels_017.s b/tests/arch/riscv/sentinel/test_riscv_sentinels_017.s index ed7294e8b..df5fbce1b 100644 --- a/tests/arch/riscv/sentinel/test_riscv_sentinels_017.s +++ b/tests/arch/riscv/sentinel/test_riscv_sentinels_017.s @@ -1,62 +1,34 @@ + # # ARCOS.INF.UC3M.ES # BY-NC-SA (https://creativecommons.org/licenses/by-nc-sa/4.0/deed.es) # -# BAD EXAMPLE: This code VIOLATES RISC-V parameter conventions -# DO NOT follow this pattern in real code! -# + .text main: - # Set up important values in saved registers - li s0, 100 # Important value that should be preserved - li s1, 200 # Another important value - li s2, 300 # Yet another important value - - # Pass parameters incorrectly - using saved registers instead of a0-a7 - li s3, 42 # WRONG: Should use a0 for first parameter - li s4, 84 # WRONG: Should use a1 for second parameter - - # Call function - caller expects s0-s4 to be unchanged after call - jal ra, bad_function - - # Try to use the values we set earlier - they will be corrupted! - add t0, s0, s1 # Expected: 100 + 200 = 300, but will be wrong - add t1, s2, s3 # Expected: 300 + 42 = 342, but will be wrong + li s1, 5 + jal ra, test + # exit li a7, 10 ecall - bad_function: - # WRONG: Create stack frame but don't save caller's saved registers + test: + # crear "stack frame" para ra, fp y una variable local addi sp, sp, -12 sw ra, 8(sp) sw fp, 4(sp) addi fp, sp, 4 - # VIOLATION 1: Destroy caller's saved registers without saving them - li s0, 999 # WRONG: Overwrites caller's s0 (was 100) - li s1, 888 # WRONG: Overwrites caller's s1 (was 200) - li s2, 777 # WRONG: Overwrites caller's s2 (was 300) - - # VIOLATION 2: Use saved registers for parameters instead of a0-a7 - # Should read parameters from a0, a1, etc. but using s3, s4 instead - add s0, s3, s4 # WRONG: Should use a0, a1 for parameters - - # VIOLATION 3: Don't set return value in a0 - # Function should return result in a0, but doesn't - - # VIOLATION 4: Use saved registers for local variables - li s1, 555 # WRONG: Should use temporary registers t0-t6 - li s2, 444 # WRONG: Should use temporary registers t0-t6 + li s1, 2 - b_efs: # WRONG: Restore stack but not the saved registers we corrupted - lw ra, 8(sp) + b_efs: lw ra, 8(sp) lw fp, 4(sp) addi sp, sp, 12 - # Return without setting a0 and with corrupted saved registers - jr ra + # return a7 + jr ra diff --git a/tests/arch/riscv/sentinel/test_riscv_sentinels_018.out b/tests/arch/riscv/sentinel/test_riscv_sentinels_018.out deleted file mode 100644 index a1e7af79f..000000000 --- a/tests/arch/riscv/sentinel/test_riscv_sentinels_018.out +++ /dev/null @@ -1,4 +0,0 @@ - -DANGER: Possible failure in the parameter passing convention -cr[PC]:0x10; ir[x1,ra]:0x8; ir[x17,a7]:0xa; ir[x18,s2]:0x2; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/sentinel/test_riscv_sentinels_019.out b/tests/arch/riscv/sentinel/test_riscv_sentinels_019.out deleted file mode 100644 index aabace55c..000000000 --- a/tests/arch/riscv/sentinel/test_riscv_sentinels_019.out +++ /dev/null @@ -1,4 +0,0 @@ - -DANGER: Possible failure in the parameter passing convention -cr[PC]:0x10; ir[x1,ra]:0x8; ir[x17,a7]:0xa; ir[x19,s3]:0x2; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/sentinel/test_riscv_sentinels_020.out b/tests/arch/riscv/sentinel/test_riscv_sentinels_020.out deleted file mode 100644 index 02498398f..000000000 --- a/tests/arch/riscv/sentinel/test_riscv_sentinels_020.out +++ /dev/null @@ -1,4 +0,0 @@ - -DANGER: Possible failure in the parameter passing convention -cr[PC]:0x10; ir[x1,ra]:0x8; ir[x17,a7]:0xa; ir[x20,s4]:0x2; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/sentinel/test_riscv_sentinels_021.out b/tests/arch/riscv/sentinel/test_riscv_sentinels_021.out deleted file mode 100644 index 1add8318d..000000000 --- a/tests/arch/riscv/sentinel/test_riscv_sentinels_021.out +++ /dev/null @@ -1,4 +0,0 @@ - -DANGER: Possible failure in the parameter passing convention -cr[PC]:0x10; ir[x1,ra]:0x8; ir[x17,a7]:0xa; ir[x21,s5]:0x2; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/sentinel/test_riscv_sentinels_022.out b/tests/arch/riscv/sentinel/test_riscv_sentinels_022.out deleted file mode 100644 index c7b7cf6a1..000000000 --- a/tests/arch/riscv/sentinel/test_riscv_sentinels_022.out +++ /dev/null @@ -1,4 +0,0 @@ - -DANGER: Possible failure in the parameter passing convention -cr[PC]:0x10; ir[x1,ra]:0x8; ir[x17,a7]:0xa; ir[x22,s6]:0x2; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/sentinel/test_riscv_sentinels_023.out b/tests/arch/riscv/sentinel/test_riscv_sentinels_023.out deleted file mode 100644 index faad03f5f..000000000 --- a/tests/arch/riscv/sentinel/test_riscv_sentinels_023.out +++ /dev/null @@ -1,4 +0,0 @@ - -DANGER: Possible failure in the parameter passing convention -cr[PC]:0x10; ir[x1,ra]:0x8; ir[x17,a7]:0xa; ir[x23,s7]:0x2; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/sentinel/test_riscv_sentinels_024.out b/tests/arch/riscv/sentinel/test_riscv_sentinels_024.out deleted file mode 100644 index 89404f49f..000000000 --- a/tests/arch/riscv/sentinel/test_riscv_sentinels_024.out +++ /dev/null @@ -1,4 +0,0 @@ - -DANGER: Possible failure in the parameter passing convention -cr[PC]:0x10; ir[x1,ra]:0x8; ir[x17,a7]:0xa; ir[x24,s8]:0x2; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/sentinel/test_riscv_sentinels_025.out b/tests/arch/riscv/sentinel/test_riscv_sentinels_025.out deleted file mode 100644 index 79a87be11..000000000 --- a/tests/arch/riscv/sentinel/test_riscv_sentinels_025.out +++ /dev/null @@ -1,4 +0,0 @@ - -DANGER: Possible failure in the parameter passing convention -cr[PC]:0x10; ir[x1,ra]:0x8; ir[x17,a7]:0xa; ir[x25,s9]:0x2; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/sentinel/test_riscv_sentinels_026.out b/tests/arch/riscv/sentinel/test_riscv_sentinels_026.out deleted file mode 100644 index d8033c781..000000000 --- a/tests/arch/riscv/sentinel/test_riscv_sentinels_026.out +++ /dev/null @@ -1,4 +0,0 @@ - -DANGER: Possible failure in the parameter passing convention -cr[PC]:0x10; ir[x1,ra]:0x8; ir[x17,a7]:0xa; ir[x26,s10]:0x2; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/sentinel/test_riscv_sentinels_027.out b/tests/arch/riscv/sentinel/test_riscv_sentinels_027.out deleted file mode 100644 index 543a02c79..000000000 --- a/tests/arch/riscv/sentinel/test_riscv_sentinels_027.out +++ /dev/null @@ -1,4 +0,0 @@ - -DANGER: Possible failure in the parameter passing convention -cr[PC]:0x10; ir[x1,ra]:0x8; ir[x17,a7]:0xa; ir[x27,s11]:0x2; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/sentinel/test_riscv_sentinels_028.out b/tests/arch/riscv/sentinel/test_riscv_sentinels_028.out deleted file mode 100644 index db9165564..000000000 --- a/tests/arch/riscv/sentinel/test_riscv_sentinels_028.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x108a; ir[x1,ra]:0x108a; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/sentinel/test_riscv_sentinels_029.out b/tests/arch/riscv/sentinel/test_riscv_sentinels_029.out deleted file mode 100644 index bb60acf12..000000000 --- a/tests/arch/riscv/sentinel/test_riscv_sentinels_029.out +++ /dev/null @@ -1,4 +0,0 @@ - -DANGER: Stack memory has not been released successfully -cr[PC]:0xc; ir[x1,ra]:0x4; ir[x2,sp]:0x10000000; ir[x17,a7]:0xa; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/sentinel/test_riscv_sentinels_029.s b/tests/arch/riscv/sentinel/test_riscv_sentinels_029.s index 3571d72ef..10622106f 100644 --- a/tests/arch/riscv/sentinel/test_riscv_sentinels_029.s +++ b/tests/arch/riscv/sentinel/test_riscv_sentinels_029.s @@ -19,7 +19,7 @@ test: # crear "stack frame" para ra, fp y una variable local - addi sp, sp, 4 + addi sp, sp, -4 # return a7 jr ra diff --git a/tests/arch/riscv/sentinel/test_riscv_sentinels_030.out b/tests/arch/riscv/sentinel/test_riscv_sentinels_030.out deleted file mode 100644 index d2239354a..000000000 --- a/tests/arch/riscv/sentinel/test_riscv_sentinels_030.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x10; ir[x1,ra]:0x8; ir[x3,gp]:0x5; ir[x17,a7]:0xa; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/sentinel/test_riscv_sentinels_031.out b/tests/arch/riscv/sentinel/test_riscv_sentinels_031.out deleted file mode 100644 index 60cc8943a..000000000 --- a/tests/arch/riscv/sentinel/test_riscv_sentinels_031.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x10; ir[x1,ra]:0x8; ir[x4,tp]:0x5; ir[x17,a7]:0xa; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/sentinel/test_riscv_sentinels_032.out b/tests/arch/riscv/sentinel/test_riscv_sentinels_032.out deleted file mode 100644 index a01e19525..000000000 --- a/tests/arch/riscv/sentinel/test_riscv_sentinels_032.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x10; ir[x1,ra]:0x8; ir[x9,s1]:0x2; ir[x17,a7]:0xa; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/sentinel/test_riscv_sentinels_033.out b/tests/arch/riscv/sentinel/test_riscv_sentinels_033.out deleted file mode 100644 index 9a879306b..000000000 --- a/tests/arch/riscv/sentinel/test_riscv_sentinels_033.out +++ /dev/null @@ -1,4 +0,0 @@ - -DANGER: Possible failure in the parameter passing convention -cr[PC]:0x10; ir[x1,ra]:0x8; ir[x9,s1]:0x5; ir[x17,a7]:0xa; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/sentinel/test_riscv_sentinels_034.out b/tests/arch/riscv/sentinel/test_riscv_sentinels_034.out deleted file mode 100644 index 06d1055ae..000000000 --- a/tests/arch/riscv/sentinel/test_riscv_sentinels_034.out +++ /dev/null @@ -1,4 +0,0 @@ - -DANGER: Possible failure in the parameter passing convention -cr[PC]:0x10; ir[x1,ra]:0x8; ir[x17,a7]:0xa; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/sentinel/test_riscv_sentinels_035.out b/tests/arch/riscv/sentinel/test_riscv_sentinels_035.out deleted file mode 100644 index 06d1055ae..000000000 --- a/tests/arch/riscv/sentinel/test_riscv_sentinels_035.out +++ /dev/null @@ -1,4 +0,0 @@ - -DANGER: Possible failure in the parameter passing convention -cr[PC]:0x10; ir[x1,ra]:0x8; ir[x17,a7]:0xa; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/sentinel/test_riscv_sentinels_036.out b/tests/arch/riscv/sentinel/test_riscv_sentinels_036.out deleted file mode 100644 index 06d1055ae..000000000 --- a/tests/arch/riscv/sentinel/test_riscv_sentinels_036.out +++ /dev/null @@ -1,4 +0,0 @@ - -DANGER: Possible failure in the parameter passing convention -cr[PC]:0x10; ir[x1,ra]:0x8; ir[x17,a7]:0xa; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/sentinel/test_riscv_sentinels_037.s b/tests/arch/riscv/sentinel/test_riscv_sentinels_037.s new file mode 100644 index 000000000..2005eb5a3 --- /dev/null +++ b/tests/arch/riscv/sentinel/test_riscv_sentinels_037.s @@ -0,0 +1,62 @@ +# +# ARCOS.INF.UC3M.ES +# BY-NC-SA (https://creativecommons.org/licenses/by-nc-sa/4.0/deed.es) +# +# BAD EXAMPLE: This code VIOLATES RISC-V parameter conventions +# DO NOT follow this pattern in real code! +# + +.text + + main: + # Set up important values in saved registers + li s1, 100 # Important value that should be preserved + li s2, 200 # Another important value + li s3, 300 # Yet another important value + + # Pass parameters incorrectly - using saved registers instead of a0-a7 + li s4, 42 # WRONG: Should use a0 for first parameter + li s5, 84 # WRONG: Should use a1 for second parameter + + # Call function - caller expects s0-s5 to be unchanged after call + jal ra, bad_function + + # Try to use the values we set earlier - they will be corrupted! + add t0, s1, s2 # Expected: 100 + 200 = 300, but will be wrong + add t1, s3, s4 # Expected: 300 + 42 = 342, but will be wrong + + # exit + li a7, 10 + ecall + + + bad_function: + # WRONG: Create stack frame but don't save caller's saved registers + addi sp, sp, -12 + sw ra, 8(sp) + sw fp, 4(sp) + addi fp, sp, 4 + + # VIOLATION 1: Destroy caller's saved registers without saving them + li s1, 999 # WRONG: Overwrites caller's s0 (was 100) + li s2, 888 # WRONG: Overwrites caller's s1 (was 200) + li s3, 777 # WRONG: Overwrites caller's s2 (was 300) + + # VIOLATION 2: Use saved registers for parameters instead of a0-a7 + # Should read parameters from a0, a1, etc. but using s3, s4 instead + add s1, s4, s5 # WRONG: Should use a0, a1 for parameters + + # VIOLATION 3: Don't set return value in a0 + # Function should return result in a0, but doesn't + + # VIOLATION 4: Use saved registers for local variables + li s1, 555 # WRONG: Should use temporary registers t0-t6 + li s2, 444 # WRONG: Should use temporary registers t0-t6 + + b_efs: # WRONG: Restore stack but not the saved registers we corrupted + lw ra, 8(sp) + lw fp, 4(sp) + addi sp, sp, 12 + + # Return without setting a0 and with corrupted saved registers + jr ra diff --git a/tests/arch/riscv64/add_test.s b/tests/arch/riscv64/add_test.s index 44b3d91a0..502a5187e 100644 --- a/tests/arch/riscv64/add_test.s +++ b/tests/arch/riscv64/add_test.s @@ -4,3 +4,4 @@ main: li t1, 0xffffffffffffffff li t2, 0xffffffffffffffff add t0, t1, t2 +jr ra diff --git a/tests/arch/riscv64/addiw_test.s b/tests/arch/riscv64/addiw_test.s index 315b215ed..b4605d7f1 100644 --- a/tests/arch/riscv64/addiw_test.s +++ b/tests/arch/riscv64/addiw_test.s @@ -26,4 +26,5 @@ main: # Test 6: Negative overflow lui s10, 0x80000 # s10 = 0x80000000 - addiw s11, s10, -1 # Expected s11 = 0x7FFFFFFF \ No newline at end of file + addiw s11, s10, -1 # Expected s11 = 0x7FFFFFFF + jr ra diff --git a/tests/arch/riscv64/addw_test.s b/tests/arch/riscv64/addw_test.s index 5fd955f2e..36ab362d1 100644 --- a/tests/arch/riscv64/addw_test.s +++ b/tests/arch/riscv64/addw_test.s @@ -21,3 +21,4 @@ main: # Test 4: Edge case - max 32-bit signed + 0x10000 lui s8, 0x7FFF0 # s8 = 0x0000000007FFF0000 addw s9, s8, s1 # Expected s9 = 0x0000000080000000 + jr ra diff --git a/tests/arch/riscv64/beq_test.s b/tests/arch/riscv64/beq_test.s index 784f1f1f6..c27e12989 100644 --- a/tests/arch/riscv64/beq_test.s +++ b/tests/arch/riscv64/beq_test.s @@ -7,7 +7,8 @@ main: addi x0, x0, 0 # NOP addi x0, x0, 0 # NOP slli x7, x7, 0 # Increment x7 + jr ra target: addi x5, x5, 0x321 # Increment x5 # Exit with status code 0 - li a0, 0 \ No newline at end of file + li a0, 0 diff --git a/tests/arch/riscv64/load_test.s b/tests/arch/riscv64/load_test.s new file mode 100644 index 000000000..be379ab67 --- /dev/null +++ b/tests/arch/riscv64/load_test.s @@ -0,0 +1,97 @@ +# +# Creator (https://creatorsim.github.io/creator/) +# Example: Various data types in data segment and memory operations +# + +.data +.align 4 + +# Different data types in data segment +byte_values: .byte 0x42, 0x73, 0xA5, 0xFF + .byte -128, 127, 0, 55 + +.align 2 +half_values: .half 0x1234, 0x5678, 0xABCD, 0xEF12 + .half -32768, 32767, 0, 12345 + +.align 4 +word_values: .word 0x12345678, 0x87654321, 0xDEADBEEF, 0xCAFEBABE + .word -2147483648, 2147483647, 0, 1000000 + +.align 3 +double_values: .dword 0x123456789ABCDEF0, 0xFEDCBA9876543210 + .dword 0x0123456789ABCDEF, 0xAAAABBBBCCCCDDDD + +# String data +.align 1 +string_data: .string "Hello, RISC-V!" + .byte 0 # Null terminator + +# Float data (stored as word) +.align 4 +float_data: .word 0x40490FDB # Pi as IEEE 754 float (3.14159...) + .word 0x402DF854 # e as IEEE 754 float (2.71828...) + +# Target memory locations for writing +.align 4 +target_area: .space 256 # Reserve 256 bytes for writing data + +.text +main: + # Set up base addresses + la t0, byte_values + la t1, half_values + la t2, word_values + la t3, double_values + la t4, target_area + + # Copy and manipulate byte data + lb a0, 0(t0) # Load first byte (0x42) + sb a0, 0(t4) # Store to target area + lb a1, 3(t0) # Load fourth byte (0xFF) + sb a1, 1(t4) # Store to target area + 1 + + # Manipulate and store modified byte + addi a0, a0, 1 # Increment byte value + sb a0, 2(t4) # Store modified byte + + # Copy and manipulate half-word data + lh a0, 0(t1) # Load first half (0x1234) + sh a0, 4(t4) # Store to target area + 4 + lh a1, 6(t1) # Load fourth half (0xEF12) + sh a1, 6(t4) # Store to target area + 6 + + # Perform arithmetic on half-word and store + add a2, a0, a1 # Add two half-words + sh a2, 8(t4) # Store result + + # Copy and manipulate word data + lw a0, 0(t2) # Load first word (0x12345678) + sw a0, 12(t4) # Store to target area + 12 + lw a1, 12(t2) # Load fourth word (0xCAFEBABE) + sw a1, 16(t4) # Store to target area + 16 + + # Perform bitwise operations on words + xor a2, a0, a1 # XOR two words + sw a2, 20(t4) # Store XOR result + or a3, a0, a1 # OR two words + sw a3, 24(t4) # Store OR result + and a4, a0, a1 # AND two words + sw a4, 28(t4) # Store AND result + + # Copy double-word data (64-bit) + ld a0, 0(t3) # Load first double-word + sd a0, 32(t4) # Store to target area + 32 + ld a1, 8(t3) # Load second double-word + sd a1, 40(t4) # Store to target area + 40 + + # Create and store new data patterns + li a0, 0x55AA55AA # Create alternating bit pattern + sw a0, 48(t4) # Store pattern + + # Store sequential byte pattern + li a0, 0x01 # Start with 1 + li a1, 8 # Counter for 8 bytes + addi a2, t4, 52 # Start address for pattern + + jr ra \ No newline at end of file diff --git a/tests/arch/riscv64/lui_test.s b/tests/arch/riscv64/lui_test.s index 0142f3d41..51c91404e 100644 --- a/tests/arch/riscv64/lui_test.s +++ b/tests/arch/riscv64/lui_test.s @@ -1,13 +1,14 @@ .text main: # Test 1: Small positive immediate value - lui x1, 0x1 # Expected x1 = 0x0000000000001000 + lui x10, 0x1 # Expected x1 = 0x0000000000001000 # Test 2: Large positive immediate value - lui x2, 0xFFFFF # Expected x2 = 0x00000FFFFF000 + lui x11, 0xFFFFF # Expected x2 = 0x00000FFFFF000 # Test 3: Negative immediate value - lui x3, 0x80000 # Expected x3 = 0xFFFFFFFF80000000 + lui x12, 0x80000 # Expected x3 = 0xFFFFFFFF80000000 # Test 4: Edge case (maximum 20-bit value) - lui x4, 0x7FFFF # Expected x4 = 0x0007FFFF00000 \ No newline at end of file + lui x13, 0x7FFFF # Expected x4 = 0x0007FFFF00000 + jr ra diff --git a/tests/arch/riscv64/memory_test.s b/tests/arch/riscv64/memory_test.s index 199d7be8c..391eff96d 100644 --- a/tests/arch/riscv64/memory_test.s +++ b/tests/arch/riscv64/memory_test.s @@ -43,4 +43,5 @@ lbu x5, 0(x4) # Now we try to save it la x4, z5 -sb x5, 3(x4) \ No newline at end of file +sb x5, 3(x4) +jr ra diff --git a/tests/arch/riscv64/slli_test.s b/tests/arch/riscv64/slli_test.s index 547379d4e..073efdfc3 100644 --- a/tests/arch/riscv64/slli_test.s +++ b/tests/arch/riscv64/slli_test.s @@ -12,8 +12,7 @@ main: slli s4, s3, 20 # Expected: 0x100000 # Test 3: Shift negative - lui s5, 0xFFFFF # Load -1 - addi s5, s5, 0xFFF # s5 = -1 + addi s5, zero, -1 # Load -1 slli s6, s5, 32 # Expected: 0xFFFFFFFF00000000 # Test 4: Maximum shift (63) @@ -23,4 +22,5 @@ main: # Test 5: Large value shift lui s9, 0x7FFFF # Load large positive - slli s10, s9, 1 # Expected: 0xFFFE0000 \ No newline at end of file + slli s10, s9, 1 # Expected: 0xFFFE0000 + jr ra diff --git a/tests/arch/riscv64/slliw_test.s b/tests/arch/riscv64/slliw_test.s index be73706ac..18315dc82 100644 --- a/tests/arch/riscv64/slliw_test.s +++ b/tests/arch/riscv64/slliw_test.s @@ -9,4 +9,5 @@ li s0, 0xFFFFFFFF slliw s1, s0, 1 # Shift right by 1 - should become positive -srliw s2, s1, 1 \ No newline at end of file +srliw s2, s1, 1 +jr ra diff --git a/tests/arch/riscv64/sllw_test.s b/tests/arch/riscv64/sllw_test.s index dcd30cb7e..c2fba0f91 100644 --- a/tests/arch/riscv64/sllw_test.s +++ b/tests/arch/riscv64/sllw_test.s @@ -4,4 +4,5 @@ main: li s3, -35 # Load same test value slli s4, s3, 1 srli s5, s4, 1 - srai s6, s4, 1 \ No newline at end of file + srai s6, s4, 1 + jr ra diff --git a/tests/arch/riscv64/subw_test.s b/tests/arch/riscv64/subw_test.s index 0256e3fac..daa368583 100644 --- a/tests/arch/riscv64/subw_test.s +++ b/tests/arch/riscv64/subw_test.s @@ -16,4 +16,5 @@ main: # Test 4: Edge case - max 32-bit value lui s11, 0x7FFF0 # s11 = 0x7FFF0000 - subw s7, s11, x0 # Expected s7 = 0x7FFF0000 \ No newline at end of file + subw s7, s11, x0 # Expected s7 = 0x7FFF0000 + jr ra diff --git a/tests/unit/arch/mips/mips_example_002.test.mts b/tests/unit/arch/mips/mips_example_002.test.mts index 59632a9c2..f88a8a982 100644 --- a/tests/unit/arch/mips/mips_example_002.test.mts +++ b/tests/unit/arch/mips/mips_example_002.test.mts @@ -17,6 +17,7 @@ main: sub $t5, $t2, $t3 # 45-33 mul $t6, $t3, $t3 # 33*33 div $t7, $t6, $t1 # $t6/13 + jr $ra `; Deno.test( diff --git a/tests/unit/arch/mips/mips_example_003.test.mts b/tests/unit/arch/mips/mips_example_003.test.mts index 7a0fdc02f..0991ab236 100644 --- a/tests/unit/arch/mips/mips_example_003.test.mts +++ b/tests/unit/arch/mips/mips_example_003.test.mts @@ -36,6 +36,7 @@ main: sw $t3, w2 #$t3 -> Memory[w2] sb $t5, b2 #$t5 -> Memory[b2] sh $t7, h2 #$t7 -> Memory[h2] + jr $ra `; Deno.test( diff --git a/tests/unit/arch/mips/mips_example_005.test.mts b/tests/unit/arch/mips/mips_example_005.test.mts index a57a96587..4905cc6ab 100644 --- a/tests/unit/arch/mips/mips_example_005.test.mts +++ b/tests/unit/arch/mips/mips_example_005.test.mts @@ -19,6 +19,7 @@ const testAssembly = ` end_while: li $v0, 1 syscall #print_int + jr $ra `; Deno.test( From b67aeea6dac0ed535532a766b4e19de91a9407f8 Mon Sep 17 00:00:00 2001 From: ALVAROPING1 Date: Mon, 16 Mar 2026 16:30:03 +0100 Subject: [PATCH 28/85] tests: use core event types enum instead of raw string --- tests/arch/arch_utils.mts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/arch/arch_utils.mts b/tests/arch/arch_utils.mts index 67e2464be..10200a4fc 100644 --- a/tests/arch/arch_utils.mts +++ b/tests/arch/arch_utils.mts @@ -8,7 +8,7 @@ import { } from "../unit/arch/simulator-test-utils.mts"; import { testKeyboard } from "../../src/core/executor/IO.mjs"; import * as creator from "../../src/core/core.mjs"; -import { coreEvents } from "../../src/core/events.mts"; +import { coreEvents, CoreEventTypes } from "../../src/core/events.mts"; import { logger } from "../../src/core/utils/creator_logger.mjs"; export const ARCH = { @@ -44,7 +44,7 @@ export function snapshot_tests( const errors = expect_error.has(file); // Record passing convention errors const sentinel_errors: { function: string; msg: string }[] = []; - coreEvents.on("sentinel-error", e => + coreEvents.on(CoreEventTypes.SENTINEL_ERROR, e => sentinel_errors.push({ function: e.functionName, msg: e.message, From 31ca1815afb2b8e3f085f6fb0da7888c6d8188fd Mon Sep 17 00:00:00 2001 From: ALVAROPING1 Date: Tue, 17 Mar 2026 11:58:50 +0100 Subject: [PATCH 29/85] fix(IO): fix floats/doubles being incorrectly written to registers --- src/core/capi/arch/riscv.mjs | 9 ++++++ src/core/executor/IO.mjs | 30 +++++++++++++++---- src/core/utils/float_bigint.mjs | 5 ---- .../syscalls/test_mips_syscall_007.s.snap | 25 ++++++++++++++++ .../syscalls/test_riscv_syscall_006.s.snap | 2 +- .../syscalls/test_riscv_syscall_007.s.snap | 24 +++++++++++++++ 6 files changed, 83 insertions(+), 12 deletions(-) create mode 100644 tests/arch/__snapshots__/mips/correct/syscalls/test_mips_syscall_007.s.snap create mode 100644 tests/arch/__snapshots__/riscv/correct/syscalls/test_riscv_syscall_007.s.snap diff --git a/src/core/capi/arch/riscv.mjs b/src/core/capi/arch/riscv.mjs index 27313cd2d..3b10f1114 100644 --- a/src/core/capi/arch/riscv.mjs +++ b/src/core/capi/arch/riscv.mjs @@ -227,4 +227,13 @@ export const ARCH = { NaNBoxed = BigInt(NaNBoxed); return NaNBoxed; }, + /** + * Writes a float32 to a register, using NaN boxing with float64 + * @param {number} value - The JavaScript number to write + * @param {string} regName - The base register name (must be even, e.g., "f0") + **/ + writeFloat(value, regName) { + const bits = this.toBigInt(value, "NaNBfloat32_64") + CAPI.REG.write(bits, regName) + } }; diff --git a/src/core/executor/IO.mjs b/src/core/executor/IO.mjs index b314bd499..3d6316ac7 100644 --- a/src/core/executor/IO.mjs +++ b/src/core/executor/IO.mjs @@ -119,11 +119,18 @@ export function kbd_read_float(keystroke, params) { document.app.$data.last_execution_mode_run = -1; } - const buffer = new ArrayBuffer(4); - const view = new DataView(buffer); - view.setFloat32(0,value, false); - const bits = view.getUint32(0, false); - writeRegister(BigInt(bits), params.indexComp, params.indexElem); + // If the current architecture has a write float specialization, use it. + // Otherwise, fallback to writing the bits directly + if (CAPI.ARCH.writeFloat !== undefined) { + const reg = architecture.components[params.indexComp].elements[params.indexElem] + CAPI.ARCH.writeFloat(value, reg.name[0]) + } else { + const buffer = new ArrayBuffer(4); + const view = new DataView(buffer); + view.setFloat32(0,value, false); + const bits = BigInt(view.getUint32(0, false)); + writeRegister(bits, params.indexComp, params.indexElem); + } return value; } @@ -146,7 +153,18 @@ export function kbd_read_double(keystroke, params) { document.app.$data.execution_mode_run = document.app.$data.last_execution_mode_run; document.app.$data.last_execution_mode_run = -1; } - writeRegister(value, params.indexComp, params.indexElem, "DFP-Reg"); + // If the current architecture has a write float specialization, use it. + // Otherwise, fallback to writing the bits directly + if (CAPI.ARCH.writeDouble !== undefined) { + const reg = architecture.components[params.indexComp].elements[params.indexElem] + CAPI.ARCH.writeDouble(value, reg.name[0]) + } else { + const buffer = new ArrayBuffer(8); + const view = new DataView(buffer); + view.setFloat64(0, value, false); + const bits = view.getBigUint64(0, false); + writeRegister(bits, params.indexComp, params.indexElem); + } return value; } diff --git a/src/core/utils/float_bigint.mjs b/src/core/utils/float_bigint.mjs index a4b022ead..08f523a04 100644 --- a/src/core/utils/float_bigint.mjs +++ b/src/core/utils/float_bigint.mjs @@ -47,11 +47,6 @@ export function bi_BigIntTofloat(big_int_value) { */ export function bi_BigIntTodouble(big_int_value) { const hex = big_int_value.toString(16).padStart(16, "0"); - // if the first 8 characters are 0, it's a 32-bit float, not a double - if (hex.substring(0, 8) === "00000000") { - return hex2float("0x" + hex.substring(8, 16)); - } - return hex2double("0x" + hex); } diff --git a/tests/arch/__snapshots__/mips/correct/syscalls/test_mips_syscall_007.s.snap b/tests/arch/__snapshots__/mips/correct/syscalls/test_mips_syscall_007.s.snap new file mode 100644 index 000000000..c1887bdcb --- /dev/null +++ b/tests/arch/__snapshots__/mips/correct/syscalls/test_mips_syscall_007.s.snap @@ -0,0 +1,25 @@ +export const snapshot = {}; + +snapshot[`mips/correct/syscalls/test_mips_syscall_007.s 1`] = ` +{ + display: "", + error: false, + keyboard: " 1.234567890123456", + memory: { + "0": 32, + "1": 2, + "11": 8, + "3": 7, + "7": 12, + "8": 3, + "9": 224, + }, + registers: { + "2,v0": "0x7", + "f0,FP0": "0x3ff3c0ca", + PC: "0xffffffff", + f1: "0x428c59f8", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/correct/syscalls/test_riscv_syscall_006.s.snap b/tests/arch/__snapshots__/riscv/correct/syscalls/test_riscv_syscall_006.s.snap index 0f0971512..c2b1fe9c1 100644 --- a/tests/arch/__snapshots__/riscv/correct/syscalls/test_riscv_syscall_006.s.snap +++ b/tests/arch/__snapshots__/riscv/correct/syscalls/test_riscv_syscall_006.s.snap @@ -14,7 +14,7 @@ snapshot[`riscv/correct/syscalls/test_riscv_syscall_006.s 1`] = ` "7": 115, }, registers: { - "f10,fa0": "0x3f9e064b", + "f10,fa0": "0xffffffff3f9e064b", "x17,a7": "0x6", mtime: "0x3", pc: "0xfffffffe", diff --git a/tests/arch/__snapshots__/riscv/correct/syscalls/test_riscv_syscall_007.s.snap b/tests/arch/__snapshots__/riscv/correct/syscalls/test_riscv_syscall_007.s.snap new file mode 100644 index 000000000..8b10963ab --- /dev/null +++ b/tests/arch/__snapshots__/riscv/correct/syscalls/test_riscv_syscall_007.s.snap @@ -0,0 +1,24 @@ +export const snapshot = {}; + +snapshot[`riscv/correct/syscalls/test_riscv_syscall_007.s 1`] = ` +{ + display: "", + error: false, + keyboard: " 1.234567890123456", + memory: { + "1": 112, + "10": 128, + "11": 103, + "2": 8, + "3": 147, + "7": 115, + }, + registers: { + "f10,fa0": "0x3ff3c0ca428c59f8", + "x17,a7": "0x7", + mtime: "0x3", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; From f2946484a53301380e6299194824db483f146582 Mon Sep 17 00:00:00 2001 From: ALVAROPING1 Date: Tue, 17 Mar 2026 14:43:33 +0100 Subject: [PATCH 30/85] fix(validation): add validation of memory accesses (alignment/segfaults) --- architecture/MIPS32.yml | 64 ++++++++++++++++-------- architecture/RISCV/RV32IMFD.yml | 61 +++++++++++++++-------- architecture/RISCV/RV64IMFD.yml | 86 +++++++++++++++++++++------------ architecture/RISCV/SRV32.yml | 78 +++++++++++++++++++----------- architecture/RISCV/SRV64.yml | 64 +++++++++++++++--------- src/core/capi/validation.mts | 12 ++++- 6 files changed, 243 insertions(+), 122 deletions(-) diff --git a/architecture/MIPS32.yml b/architecture/MIPS32.yml index fe560f84e..1f4ec4ed0 100644 --- a/architecture/MIPS32.yml +++ b/architecture/MIPS32.yml @@ -2363,7 +2363,7 @@ instructions: suffix: ) order: 3 definition: | - registers[reg1] = CAPI.MEM.read(registers[reg2]+val, 1, reg1); + registers[reg1] = CAPI.MEM.read(registers[reg2]+val, 1, reg1, false); - name: lbu template: Custom type: Memory access @@ -2399,7 +2399,7 @@ instructions: order: 2 space: false definition: | - registers[rt] = CAPI.MEM.read(registers[base]+off, 1, rt); + registers[rt] = CAPI.MEM.read(registers[base]+off, 1, rt, false); - name: ldc1 template: Custom type: Memory access @@ -2439,11 +2439,11 @@ instructions: postoperation: | CAPI.ARCH.writeDouble(doubleValue, ft); definition: | - if (CAPI.VALIDATION.isMisaligned(registers[base] + off, 'd')) { - CAPI.VALIDATION.raise('The memory must be aligned'); - } - let high = CAPI.MEM.read(registers[base] + off, 4); - let low = CAPI.MEM.read(registers[base] + off + 4n, 4, ft); + let addr = registers[base] + off; + if (CAPI.VALIDATION.isMisaligned(addr, 8)) + CAPI.VALIDATION.raise('The memory must be aligned'); + let high = CAPI.MEM.read(addr, 4, false); + let low = CAPI.MEM.read(addr + 4n, 4, ft, false); let doubleValue = CAPI.FP.uint2float64(Number(low), Number(high)); - name: lh template: Custom @@ -2480,7 +2480,10 @@ instructions: prefix: ($ suffix: ) definition: | - registers[reg1] = CAPI.MEM.read(registers[reg2]+val, 2, reg1); + let addr = registers[reg2] + val; + if (CAPI.VALIDATION.isMisaligned(addr, 2)) + CAPI.VALIDATION.raise('The memory must be aligned'); + registers[reg1] = CAPI.MEM.read(addr, 2, reg1, false); - name: lhu template: Custom type: Memory access @@ -2516,7 +2519,10 @@ instructions: order: 2 space: false definition: | - registers[rt] = CAPI.MEM.read(registers[base]+off, 2, rt); + let addr = registers[base] + off; + if (CAPI.VALIDATION.isMisaligned(addr, 2)) + CAPI.VALIDATION.raise('The memory must be aligned'); + registers[rt] = CAPI.MEM.read(addr, 2, rt, false); - name: lui template: Custom type: Other @@ -2580,7 +2586,10 @@ instructions: suffix: ) order: 3 definition: | - registers[reg1] = CAPI.MEM.read(registers[reg2]+val, 4, reg1); + let addr = registers[reg2] + val; + if (CAPI.VALIDATION.isMisaligned(addr, 4)) + CAPI.VALIDATION.raise('The memory must be aligned'); + registers[reg1] = CAPI.MEM.read(addr, 4, reg1, false); - name: lwc1 template: Custom type: Memory access @@ -2616,7 +2625,10 @@ instructions: order: 2 space: false definition: |- - registers[ft] = CAPI.MEM.read(registers[base]+off, 4, ft); + let addr = registers[base] + off; + if (CAPI.VALIDATION.isMisaligned(addr, 4)) + CAPI.VALIDATION.raise('The memory must be aligned'); + registers[ft] = CAPI.MEM.read(addr, 4, ft, false); - name: mfc1 template: Custom type: Transfer between registers @@ -3480,7 +3492,7 @@ instructions: stopbit: 0 order: 2 space: false - definition: "CAPI.MEM.write(registers[base]+off, 1, registers[rt], rt);" + definition: "CAPI.MEM.write(registers[base]+off, 1, registers[rt], rt, 'byte', false);" - name: sdc1 template: Custom type: Memory access @@ -3518,12 +3530,12 @@ instructions: preoperation: | let doubleValue = CAPI.ARCH.readDouble(ft); let parts = CAPI.FP.float642uint(doubleValue); + let value = (BigInt(parts[1]) << 32n) | BigInt(parts[0]) definition: | - if (CAPI.VALIDATION.isMisaligned(registers[base] + off, 'd')) { - CAPI.VALIDATION.raise('The memory must be aligned'); - } - CAPI.MEM.write(registers[base] + off, 4, BigInt(parts[1]), ft); - CAPI.MEM.write(registers[base] + off + 4n, 4, BigInt(parts[0])); + let addr = registers[base] + off; + if (CAPI.VALIDATION.isMisaligned(addr, 8)) + CAPI.VALIDATION.raise('The memory must be aligned'); + CAPI.MEM.write(addr, 8, value, ft, 'float64', false); - name: sh template: Custom type: Memory access @@ -3558,7 +3570,11 @@ instructions: stopbit: 0 order: 2 space: false - definition: "CAPI.MEM.write(registers[base]+off, 2, registers[rt], rt);" + definition: | + let addr = registers[base] + off; + if (CAPI.VALIDATION.isMisaligned(addr, 2)) + CAPI.VALIDATION.raise('The memory must be aligned'); + CAPI.MEM.write(addr, 2, registers[rt], rt, 'half', false); - name: sll template: Custom type: Arithmetic integer @@ -4144,7 +4160,11 @@ instructions: prefix: ($ suffix: ) order: 3 - definition: "CAPI.MEM.write(val+registers[reg2], 4, registers[reg1], reg1);" + definition: | + let addr = registers[reg2] + val; + if (CAPI.VALIDATION.isMisaligned(addr, 4)) + CAPI.VALIDATION.raise('The memory must be aligned'); + CAPI.MEM.write(addr, 4, registers[reg1], reg1, 'word', false); - name: swc1 template: Custom type: Memory access @@ -4179,7 +4199,11 @@ instructions: stopbit: 0 order: 2 space: false - definition: "CAPI.MEM.write(registers[base]+off, 4, registers[ft], ft);" + definition: | + let addr = registers[base] + off; + if (CAPI.VALIDATION.isMisaligned(addr, 4)) + CAPI.VALIDATION.raise('The memory must be aligned'); + CAPI.MEM.write(addr, 4, registers[ft], ft, 'float32', false); - name: syscall template: Custom type: Syscall diff --git a/architecture/RISCV/RV32IMFD.yml b/architecture/RISCV/RV32IMFD.yml index dc6ea9c8d..08cdfc14e 100644 --- a/architecture/RISCV/RV32IMFD.yml +++ b/architecture/RISCV/RV32IMFD.yml @@ -1616,7 +1616,7 @@ instructions: - field: funct3 value: "000" definition: | - registers[rd] = CAPI.MEM.read(imm + registers[rs1], 1, rd); + registers[rd] = CAPI.MEM.read(imm + registers[rs1], 1, rd, false); help: Loads a 8-bit value from memory and sign-extends this to XLEN bits before storing it in register rd. - name: lbu @@ -1629,8 +1629,8 @@ instructions: value: "100" definition: | let addr = CAPI.FP.int2uint(registers[rs1]) + imm; - registers[rd] = CAPI.MEM.read(addr, 1, rd); - registers[rd] = CAPI.FP.int2uint(registers[rd]); + let result = CAPI.MEM.read(addr, 1, rd, false); + registers[rd] = CAPI.FP.int2uint(result); help: Loads a 8-bit value from memory and zero-extends this to XLEN bits before storing it in register rd. - name: lh @@ -1642,7 +1642,10 @@ instructions: - field: funct3 value: "001" definition: | - registers[rd] = CAPI.MEM.read(imm + registers[rs1], 2, rd); + let addr = registers[rs1] + imm; + if (CAPI.VALIDATION.isMisaligned(addr, 2)) + CAPI.VALIDATION.raise('The memory must be aligned'); + registers[rd] = CAPI.MEM.read(addr, 2, rd, false); help: Loads a 16-bit value from memory and sign-extends this to XLEN bits before storing it in register rd. - name: lhu @@ -1654,9 +1657,11 @@ instructions: - field: funct3 value: "101" definition: | - let addr = CAPI.FP.int2uint(registers[rs1], 32) + imm; - registers[rd] = CAPI.MEM.read(addr, 2, rd); - registers[rd] = CAPI.FP.int2uint(registers[rd]); + let addr = registers[rs1] + imm; + if (CAPI.VALIDATION.isMisaligned(addr, 2)) + CAPI.VALIDATION.raise('The memory must be aligned'); + let result = CAPI.MEM.read(addr, 2, rd, false); + registers[rd] = CAPI.FP.int2uint(result); help: Loads a 16-bit value from memory and zero-extends this to XLEN bits before storing it in register rd. - name: lw @@ -1668,8 +1673,10 @@ instructions: - field: funct3 value: "010" definition: | - let addr = CAPI.FP.int2uint(registers[rs1], 32) + imm; - registers[rd] = CAPI.MEM.read(addr, 4, rd); + let addr = registers[rs1] + imm; + if (CAPI.VALIDATION.isMisaligned(addr, 4)) + CAPI.VALIDATION.raise('The memory must be aligned'); + registers[rd] = CAPI.MEM.read(addr, 4, rd, false); help: Loads a 32-bit value from memory and sign-extends this to XLEN bits before storing it in register rd. - name: ori @@ -1949,7 +1956,7 @@ instructions: - field: funct3 value: "000" definition: | - CAPI.MEM.write(registers[rs1] + imm, 1, BigInt.asUintN(8, registers[rs2]), rs2, 'byte'); + CAPI.MEM.write(registers[rs1] + imm, 1, BigInt.asUintN(8, registers[rs2]), rs2, 'byte', false); help: Store 8-bit, values from the low bits of register rs2 to memory. - name: sh @@ -1960,10 +1967,12 @@ instructions: - field: funct3 value: "001" definition: | - CAPI.MEM.write(imm + registers[rs1], 2, BigInt.asUintN(16, registers[rs2]), rs2, 'half'); + let addr = registers[rs1] + imm; + if (CAPI.VALIDATION.isMisaligned(addr, 2)) + CAPI.VALIDATION.raise('The memory must be aligned'); + CAPI.MEM.write(addr, 2, BigInt.asUintN(16, registers[rs2]), rs2, 'half', false); help: Store 16-bit, values from the low bits of register rs2 to memory. - # The check for the - name: sw template: S fields: @@ -1972,7 +1981,10 @@ instructions: - field: funct3 value: "010" definition: | - CAPI.MEM.write(imm + registers[rs1], 4, BigInt.asUintN(32, registers[rs2]), rs2, 'word'); + let addr = registers[rs1] + imm; + if (CAPI.VALIDATION.isMisaligned(addr, 4)) + CAPI.VALIDATION.raise('The memory must be aligned'); + CAPI.MEM.write(addr, 4, BigInt.asUintN(32, registers[rs2]), rs2, 'word', false); help: Store 32-bit, values from the low bits of register rs2 to memory. # U-type instructions @@ -2224,7 +2236,10 @@ instructions: - field: rd type: DFP-Reg definition: | - registers[rd] = CAPI.MEM.read(registers[rs1] + imm, 4, rd); + let addr = registers[rs1] + imm; + if (CAPI.VALIDATION.isMisaligned(addr, 4)) + CAPI.VALIDATION.raise('The memory must be aligned'); + registers[rd] = CAPI.MEM.read(addr, 4, rd, false); postoperation: | registers[rd] = CAPI.ARCH.NaNBox(registers[rd]); @@ -2855,7 +2870,10 @@ instructions: type: DFP-Reg definition: | let value = registers[rs2] & 0xFFFFFFFFn; - CAPI.MEM.write(registers[rs1] + imm, 4, value, rs2, 'float32'); + let addr = registers[rs1] + imm; + if (CAPI.VALIDATION.isMisaligned(addr, 4)) + CAPI.VALIDATION.raise('The memory must be aligned'); + CAPI.MEM.write(addr, 4, value, rs2, 'float32', false); help: Store a single-precision value from floating-point register rs2 to memory. D: @@ -2877,10 +2895,10 @@ instructions: - field: rd type: DFP-Reg definition: | - if (CAPI.VALIDATION.isMisaligned(registers[rs1] + imm, 'd')) { - CAPI.VALIDATION.raise('The memory must be aligned'); - } - registers[rd] = CAPI.MEM.read(registers[rs1] + imm, 8, rd); + let addr = registers[rs1] + imm; + if (CAPI.VALIDATION.isMisaligned(addr, 8)) + CAPI.VALIDATION.raise('The memory must be aligned'); + registers[rd] = CAPI.MEM.read(addr, 8, rd, false); help: Load a double-precision floating-point value from memory into floating-point register rd. - name: fadd.d @@ -3556,7 +3574,10 @@ instructions: - field: rs2 type: DFP-Reg definition: | - CAPI.MEM.write(registers[rs1] + imm, 8, registers[rs2], rs2, 'float64'); + let addr = registers[rs1] + imm; + if (CAPI.VALIDATION.isMisaligned(addr, 8)) + CAPI.VALIDATION.raise('The memory must be aligned'); + CAPI.MEM.write(addr, 8, registers[rs2], rs2, 'float64', false); help: Store a double-precision value from the floating-point registers to memory. diff --git a/architecture/RISCV/RV64IMFD.yml b/architecture/RISCV/RV64IMFD.yml index a87bb6f19..0a512a887 100644 --- a/architecture/RISCV/RV64IMFD.yml +++ b/architecture/RISCV/RV64IMFD.yml @@ -1634,7 +1634,7 @@ instructions: - field: funct3 value: "000" definition: | - registers[rd] = CAPI.MEM.read(imm + registers[rs1], 1, rd); + registers[rd] = CAPI.MEM.read(imm + registers[rs1], 1, rd, false); help: Loads a 8-bit value from memory and sign-extends this to XLEN bits before storing it in register rd. - name: lbu @@ -1647,8 +1647,8 @@ instructions: value: "100" definition: | let addr = CAPI.FP.int2uint(registers[rs1]) + imm; - registers[rd] = CAPI.MEM.read(addr, 1, rd); - registers[rd] = CAPI.FP.int2uint(registers[rd]); + let result = CAPI.MEM.read(addr, 1, rd, false); + registers[rd] = CAPI.FP.int2uint(result); help: Loads a 8-bit value from memory and zero-extends this to XLEN bits before storing it in register rd. - name: lh @@ -1660,7 +1660,10 @@ instructions: - field: funct3 value: "001" definition: | - registers[rd] = CAPI.MEM.read(imm + registers[rs1], 2, rd); + let addr = registers[rs1] + imm; + if (CAPI.VALIDATION.isMisaligned(addr, 2)) + CAPI.VALIDATION.raise('The memory must be aligned'); + registers[rd] = CAPI.MEM.read(addr, 2, rd, false); help: Loads a 16-bit value from memory and sign-extends this to XLEN bits before storing it in register rd. - name: lhu @@ -1672,9 +1675,11 @@ instructions: - field: funct3 value: "101" definition: | - let addr = CAPI.FP.int2uint(registers[rs1], 32) + imm; - registers[rd] = CAPI.MEM.read(addr, 2, rd); - registers[rd] = CAPI.FP.int2uint(registers[rd]); + let addr = registers[rs1] + imm; + if (CAPI.VALIDATION.isMisaligned(addr, 2)) + CAPI.VALIDATION.raise('The memory must be aligned'); + let result = CAPI.MEM.read(addr, 2, rd, false); + registers[rd] = CAPI.FP.int2uint(result); help: Loads a 16-bit value from memory and zero-extends this to XLEN bits before storing it in register rd. - name: lw @@ -1686,8 +1691,10 @@ instructions: - field: funct3 value: "010" definition: | - let addr = CAPI.FP.int2uint(registers[rs1], 32) + imm; - registers[rd] = CAPI.MEM.read(addr, 4, rd); + let addr = registers[rs1] + imm; + if (CAPI.VALIDATION.isMisaligned(addr, 4)) + CAPI.VALIDATION.raise('The memory must be aligned'); + registers[rd] = CAPI.MEM.read(addr, 4, rd, false); help: Loads a 32-bit value from memory and sign-extends this to XLEN bits before storing it in register rd. - name: lwu @@ -1699,9 +1706,11 @@ instructions: - field: funct3 value: "110" definition: | - var addr = CAPI.FP.int2uint(registers[rs1]) + imm; - registers[rd] = CAPI.MEM.read(addr, 4, rd); - registers[rd] = CAPI.FP.int2uint(registers[rd]); + let addr = registers[rs1] + imm; + if (CAPI.VALIDATION.isMisaligned(addr, 4)) + CAPI.VALIDATION.raise('The memory must be aligned'); + result = CAPI.MEM.read(addr, 4, rd, false); + registers[rd] = CAPI.FP.int2uint(result); help: Loads a 32-bit value from memory and zero-extends this to 64 bits before storing it in register rd. - name: ld @@ -1713,8 +1722,10 @@ instructions: - field: funct3 value: "011" definition: | - let addr = CAPI.FP.int2uint(registers[rs1]) + imm; - registers[rd] = CAPI.MEM.read(addr, 8, rd); + let addr = registers[rs1] + imm; + if (CAPI.VALIDATION.isMisaligned(addr, 8)) + CAPI.VALIDATION.raise('The memory must be aligned'); + registers[rd] = CAPI.MEM.read(addr, 8, rd, false); help: Loads a 64-bit value from memory into register rd for RV64I. - name: ori @@ -2134,7 +2145,7 @@ instructions: - field: funct3 value: "000" definition: | - CAPI.MEM.write(registers[rs1] + imm, 1, BigInt.asUintN(8, registers[rs2]), rs2, 'byte'); + CAPI.MEM.write(registers[rs1] + imm, 1, BigInt.asUintN(8, registers[rs2]), rs2, 'byte', false); help: Store 8-bit, values from the low bits of register rs2 to memory. - name: sh @@ -2145,7 +2156,10 @@ instructions: - field: funct3 value: "001" definition: | - CAPI.MEM.write(imm + registers[rs1], 2, BigInt.asUintN(16, registers[rs2]), rs2, 'half'); + let addr = registers[rs1] + imm; + if (CAPI.VALIDATION.isMisaligned(addr, 2)) + CAPI.VALIDATION.raise('The memory must be aligned'); + CAPI.MEM.write(addr, 2, BigInt.asUintN(16, registers[rs2]), rs2, 'half', false); help: Store 16-bit, values from the low bits of register rs2 to memory. # The check for the @@ -2157,7 +2171,10 @@ instructions: - field: funct3 value: "010" definition: | - CAPI.MEM.write(imm + registers[rs1], 4, BigInt.asUintN(32, registers[rs2]), rs2, 'word'); + let addr = registers[rs1] + imm; + if (CAPI.VALIDATION.isMisaligned(addr, 4)) + CAPI.VALIDATION.raise('The memory must be aligned'); + CAPI.MEM.write(addr, 4, BigInt.asUintN(32, registers[rs2]), rs2, 'word', false); help: Store 32-bit, values from the low bits of register rs2 to memory. - name: sd @@ -2168,12 +2185,16 @@ instructions: - field: funct3 value: "011" definition: | + let addr = registers[rs1] + imm; + if (CAPI.VALIDATION.isMisaligned(addr, 8)) + CAPI.VALIDATION.raise('The memory must be aligned'); CAPI.MEM.write( - imm + registers[rs1], + addr, 8, BigInt.asUintN(64, registers[rs2]), rs2, - "double", + "float64", + false, ); help: Loads a 64-bit value from memory into register rd for RV64I. @@ -2425,7 +2446,10 @@ instructions: - field: rd type: SFP-Reg definition: | - registers[rd] = CAPI.MEM.read(registers[rs1] + imm, 4, rd); + let addr = registers[rs1] + imm; + if (CAPI.VALIDATION.isMisaligned(addr, 4)) + CAPI.VALIDATION.raise('The memory must be aligned'); + registers[rd] = CAPI.MEM.read(addr, 4, rd, false); postoperation: | registers[rd] = CAPI.ARCH.NaNBox(registers[rd]); help: Load a single-precision floating-point value from memory into floating-point register rd. @@ -3052,7 +3076,10 @@ instructions: type: SFP-Reg definition: | let value = registers[rs2] & 0xFFFFFFFFn; - CAPI.MEM.write(registers[rs1] + imm, 4, value, rs2, 'float32'); + let addr = registers[rs1] + imm; + if (CAPI.VALIDATION.isMisaligned(addr, 4)) + CAPI.VALIDATION.raise('The memory must be aligned'); + CAPI.MEM.write(addr, 4, value, rs2, 'float32', false); help: Store a single-precision value from floating-point register rs2 to memory. D: @@ -3074,10 +3101,10 @@ instructions: - field: rd type: DFP-Reg definition: | - if (CAPI.VALIDATION.isMisaligned(registers[rs1] + imm, 'd')) { - CAPI.VALIDATION.raise('The memory must be aligned'); - } - registers[rd] = CAPI.MEM.read(registers[rs1] + imm, 8, rd); + let addr = registers[rs1] + imm; + if (CAPI.VALIDATION.isMisaligned(addr, 8)) + CAPI.VALIDATION.raise('The memory must be aligned'); + registers[rd] = CAPI.MEM.read(8, 8, rd, false); help: Load a double-precision floating-point value from memory into floating-point register rd. - name: fadd.d @@ -3751,11 +3778,10 @@ instructions: - field: rs2 type: DFP-Reg definition: | - let val = BigInt("0x" + CAPI.FP.split_double(registers[rs2], 0)); - CAPI.MEM.write(registers[rs1] + imm, 4, val, rs2); - val = BigInt("0x" + CAPI.FP.split_double(registers[rs2], 1)); - CAPI.MEM.write(registers[rs1] + imm + 4n, 4, val, rs2); - CAPI.MEM.addHint(registers[rs1] + imm, "float64", 64); + let addr = registers[rs1] + imm; + if (CAPI.VALIDATION.isMisaligned(addr, 8)) + CAPI.VALIDATION.raise('The memory must be aligned'); + CAPI.MEM.write(addr, 8, registers[rs2], rs2, 'float64', false); help: Store a double-precision value from the floating-point registers to memory. diff --git a/architecture/RISCV/SRV32.yml b/architecture/RISCV/SRV32.yml index 39758f959..9bf8ef08d 100644 --- a/architecture/RISCV/SRV32.yml +++ b/architecture/RISCV/SRV32.yml @@ -2176,7 +2176,7 @@ instructions: - field: funct3 value: "000" definition: | - registers[rd] = CAPI.MEM.read(imm + registers[rs1], 1, rd); + registers[rd] = CAPI.MEM.read(imm + registers[rs1], 1, rd, false); help: Loads a 8-bit value from memory and sign-extends this to XLEN bits before storing it in register rd. - name: lbu @@ -2190,8 +2190,8 @@ instructions: value: "100" definition: | let addr = CAPI.FP.int2uint(registers[rs1]) + imm; - registers[rd] = CAPI.MEM.read(addr, 1, rd); - registers[rd] = CAPI.FP.int2uint(registers[rd]); + let result = CAPI.MEM.read(addr, 1, rd, false); + registers[rd] = CAPI.FP.int2uint(result); help: Loads a 8-bit value from memory and zero-extends this to XLEN bits before storing it in register rd. - name: lh extension: I @@ -2203,7 +2203,10 @@ instructions: - field: funct3 value: "001" definition: | - registers[rd] = CAPI.MEM.read(imm + registers[rs1], 2, rd); + let addr = registers[rs1] + imm; + if (CAPI.VALIDATION.isMisaligned(addr, 2)) + CAPI.VALIDATION.raise('The memory must be aligned'); + registers[rd] = CAPI.MEM.read(addr, 2, rd, false); help: Loads a 16-bit value from memory and sign-extends this to XLEN bits before storing it in register rd. - name: lhu @@ -2216,9 +2219,11 @@ instructions: - field: funct3 value: "101" definition: | - let addr = CAPI.FP.int2uint(registers[rs1], 32) + imm; - registers[rd] = CAPI.MEM.read(addr, 2, rd); - registers[rd] = CAPI.FP.int2uint(registers[rd]); + let addr = registers[rs1] + imm; + if (CAPI.VALIDATION.isMisaligned(addr, 2)) + CAPI.VALIDATION.raise('The memory must be aligned'); + let result = CAPI.MEM.read(addr, 2, rd, false); + registers[rd] = CAPI.FP.int2uint(result); help: Loads a 16-bit value from memory and zero-extends this to XLEN bits before storing it in register rd. - name: lw extension: I @@ -2230,8 +2235,10 @@ instructions: - field: funct3 value: "010" definition: | - let addr = CAPI.FP.int2uint(registers[rs1], 32) + imm; - registers[rd] = CAPI.MEM.read(addr, 4, rd); + let addr = registers[rs1] + imm; + if (CAPI.VALIDATION.isMisaligned(addr, 4)) + CAPI.VALIDATION.raise('The memory must be aligned'); + registers[rd] = CAPI.MEM.read(addr, 4, rd, false); help: Loads a 32-bit value from memory and sign-extends this to XLEN bits before storing it in register rd. - name: ld extension: D @@ -2243,8 +2250,10 @@ instructions: - field: funct3 value: "011" definition: | - let addr = CAPI.FP.int2uint(registers[rs1]) + imm; - registers[rd] = CAPI.MEM.read(addr, 8, rd); + let addr = registers[rs1] + imm; + if (CAPI.VALIDATION.isMisaligned(addr, 8)) + CAPI.VALIDATION.raise('The memory must be aligned'); + registers[rd] = CAPI.MEM.read(addr, 8, rd, false); help: Loads a 64-bit value from memory into register rd for RV64I. - name: ori extension: I @@ -2503,7 +2512,7 @@ instructions: - field: funct3 value: "000" definition: | - CAPI.MEM.write(registers[rs1] + imm, 1, BigInt.asUintN(8, registers[rs2]), rs2, 'byte'); + CAPI.MEM.write(registers[rs1] + imm, 1, BigInt.asUintN(8, registers[rs2]), rs2, 'byte', false); help: Store 8-bit, values from the low bits of register rs2 to memory. - name: sh @@ -2515,7 +2524,10 @@ instructions: - field: funct3 value: "001" definition: | - CAPI.MEM.write(imm + registers[rs1], 2, BigInt.asUintN(16, registers[rs2]), rs2, 'half'); + let addr = registers[rs1] + imm; + if (CAPI.VALIDATION.isMisaligned(addr, 2)) + CAPI.VALIDATION.raise('The memory must be aligned'); + CAPI.MEM.write(addr, 2, BigInt.asUintN(16, registers[rs2]), rs2, 'half', false); help: Store 16-bit, values from the low bits of register rs2 to memory. - name: sw @@ -2527,7 +2539,10 @@ instructions: - field: funct3 value: "010" definition: | - CAPI.MEM.write(imm + registers[rs1], 4, BigInt.asUintN(32, registers[rs2]), rs2, 'word'); + let addr = registers[rs1] + imm; + if (CAPI.VALIDATION.isMisaligned(addr, 4)) + CAPI.VALIDATION.raise('The memory must be aligned'); + CAPI.MEM.write(addr, 4, BigInt.asUintN(32, registers[rs2]), rs2, 'word', false); help: Store 32-bit, values from the low bits of register rs2 to memory. @@ -2540,12 +2555,16 @@ instructions: - field: funct3 value: "011" definition: | + let addr = registers[rs1] + imm; + if (CAPI.VALIDATION.isMisaligned(addr, 8)) + CAPI.VALIDATION.raise('The memory must be aligned'); CAPI.MEM.write( - imm + registers[rs1], + addr, 8, BigInt.asUintN(64, registers[rs2]), rs2, - "double", + "float64", + false, ); help: Loads a 64-bit value from memory into register rd for RV64I. @@ -2782,7 +2801,10 @@ instructions: - field: rd type: DFP-Reg definition: | - registers[rd] = CAPI.MEM.read(registers[rs1] + imm, 4, rd); + let addr = registers[rs1] + imm; + if (CAPI.VALIDATION.isMisaligned(addr, 4)) + CAPI.VALIDATION.raise('The memory must be aligned'); + registers[rd] = CAPI.MEM.read(addr, 4, rd, false); postoperation: | registers[rd] = CAPI.ARCH.NaNBox(registers[rd]); @@ -3434,7 +3456,10 @@ instructions: type: DFP-Reg definition: | let value = registers[rs2] & 0xFFFFFFFFn; - CAPI.MEM.write(registers[rs1] + imm, 4, value, rs2, 'float32'); + let addr = registers[rs1] + imm; + if (CAPI.VALIDATION.isMisaligned(addr, 4)) + CAPI.VALIDATION.raise('The memory must be aligned'); + CAPI.MEM.write(addr, 4, value, rs2, 'float32', false); help: Store a single-precision value from floating-point register rs2 to memory. D: - name: fld @@ -3449,10 +3474,10 @@ instructions: - field: rd type: DFP-Reg definition: | - if (CAPI.VALIDATION.isMisaligned(registers[rs1] + imm, 'd')) { - CAPI.VALIDATION.raise('The memory must be aligned'); - } - registers[rd] = CAPI.MEM.read(registers[rs1] + imm, 8, rd); + let addr = registers[rs1] + imm; + if (CAPI.VALIDATION.isMisaligned(addr, 8)) + CAPI.VALIDATION.raise('The memory must be aligned'); + registers[rd] = CAPI.MEM.read(addr, 8, rd, false); help: Load a double-precision floating-point value from memory into floating-point register rd. - name: fadd.d extension: D @@ -4147,11 +4172,10 @@ instructions: - field: rs2 type: DFP-Reg definition: | - let val = BigInt("0x" + CAPI.FP.split_double(registers[rs2], 0)); - CAPI.MEM.write(registers[rs1] + imm, 4, val, rs2); - val = BigInt("0x" + CAPI.FP.split_double(registers[rs2], 1)); - CAPI.MEM.write(registers[rs1] + imm + 4n, 4, val, rs2); - CAPI.MEM.addHint(registers[rs1] + imm, "float64", 64); + let addr = registers[rs1] + imm; + if (CAPI.VALIDATION.isMisaligned(addr, 8)) + CAPI.VALIDATION.raise('The memory must be aligned'); + CAPI.MEM.write(addr, 8, registers[rs2], rs2, 'float64', false); help: Store a double-precision value from the floating-point registers to memory. Zifencei: - name: fence.i diff --git a/architecture/RISCV/SRV64.yml b/architecture/RISCV/SRV64.yml index e6d6813a7..49b890cbf 100644 --- a/architecture/RISCV/SRV64.yml +++ b/architecture/RISCV/SRV64.yml @@ -2187,7 +2187,7 @@ instructions: - field: funct3 value: "000" definition: | - registers[rd] = CAPI.MEM.read(imm + registers[rs1], 1, rd); + registers[rd] = CAPI.MEM.read(imm + registers[rs1], 1, rd, false); help: Loads a 8-bit value from memory and sign-extends this to XLEN bits before storing it in register rd. - name: lbu @@ -2201,8 +2201,8 @@ instructions: value: "100" definition: | let addr = CAPI.FP.int2uint(registers[rs1]) + imm; - registers[rd] = CAPI.MEM.read(addr, 1, rd); - registers[rd] = CAPI.FP.int2uint(registers[rd]); + let result = CAPI.MEM.read(addr, 1, rd, false); + registers[rd] = CAPI.FP.int2uint(result); help: Loads a 8-bit value from memory and zero-extends this to XLEN bits before storing it in register rd. - name: lh extension: I @@ -2214,7 +2214,10 @@ instructions: - field: funct3 value: "001" definition: | - registers[rd] = CAPI.MEM.read(imm + registers[rs1], 2, rd); + let addr = registers[rs1] + imm; + if (CAPI.VALIDATION.isMisaligned(addr, 2)) + CAPI.VALIDATION.raise('The memory must be aligned'); + registers[rd] = CAPI.MEM.read(addr, 2, rd, false); help: Loads a 16-bit value from memory and sign-extends this to XLEN bits before storing it in register rd. - name: lhu @@ -2227,9 +2230,11 @@ instructions: - field: funct3 value: "101" definition: | - let addr = CAPI.FP.int2uint(registers[rs1], 32) + imm; - registers[rd] = CAPI.MEM.read(addr, 2, rd); - registers[rd] = CAPI.FP.int2uint(registers[rd]); + let addr = registers[rs1] + imm; + if (CAPI.VALIDATION.isMisaligned(addr, 2)) + CAPI.VALIDATION.raise('The memory must be aligned'); + let result = CAPI.MEM.read(addr, 2, rd, false); + registers[rd] = CAPI.FP.int2uint(result); help: Loads a 16-bit value from memory and zero-extends this to XLEN bits before storing it in register rd. - name: lw extension: I @@ -2241,8 +2246,10 @@ instructions: - field: funct3 value: "010" definition: | - let addr = CAPI.FP.int2uint(registers[rs1], 32) + imm; - registers[rd] = CAPI.MEM.read(addr, 4, rd); + let addr = registers[rs1] + imm; + if (CAPI.VALIDATION.isMisaligned(addr, 4)) + CAPI.VALIDATION.raise('The memory must be aligned'); + registers[rd] = CAPI.MEM.read(addr, 4, rd, false); help: Loads a 32-bit value from memory and sign-extends this to XLEN bits before storing it in register rd. - name: ori extension: I @@ -2501,7 +2508,7 @@ instructions: - field: funct3 value: "000" definition: | - CAPI.MEM.write(registers[rs1] + imm, 1, BigInt.asUintN(8, registers[rs2]), rs2, 'byte'); + CAPI.MEM.write(registers[rs1] + imm, 1, BigInt.asUintN(8, registers[rs2]), rs2, 'byte', false); help: Store 8-bit, values from the low bits of register rs2 to memory. - name: sh @@ -2513,7 +2520,10 @@ instructions: - field: funct3 value: "001" definition: | - CAPI.MEM.write(imm + registers[rs1], 2, BigInt.asUintN(16, registers[rs2]), rs2, 'half'); + let addr = registers[rs1] + imm; + if (CAPI.VALIDATION.isMisaligned(addr, 2)) + CAPI.VALIDATION.raise('The memory must be aligned'); + CAPI.MEM.write(addr, 2, BigInt.asUintN(16, registers[rs2]), rs2, 'half', false); help: Store 16-bit, values from the low bits of register rs2 to memory. - name: sw @@ -2525,7 +2535,10 @@ instructions: - field: funct3 value: "010" definition: | - CAPI.MEM.write(imm + registers[rs1], 4, BigInt.asUintN(32, registers[rs2]), rs2, 'word'); + let addr = registers[rs1] + imm; + if (CAPI.VALIDATION.isMisaligned(addr, 4)) + CAPI.VALIDATION.raise('The memory must be aligned'); + CAPI.MEM.write(addr, 4, BigInt.asUintN(32, registers[rs2]), rs2, 'word', false); help: Store 32-bit, values from the low bits of register rs2 to memory. - name: auipc @@ -2776,7 +2789,10 @@ instructions: - field: rd type: DFP-Reg definition: | - registers[rd] = CAPI.MEM.read(registers[rs1] + imm, 4, rd); + let addr = registers[rs1] + imm; + if (CAPI.VALIDATION.isMisaligned(addr, 4)) + CAPI.VALIDATION.raise('The memory must be aligned'); + registers[rd] = CAPI.MEM.read(addr, 4, rd, false); postoperation: | registers[rd] = CAPI.ARCH.NaNBox(registers[rd]); @@ -3428,7 +3444,10 @@ instructions: type: DFP-Reg definition: | let value = registers[rs2] & 0xFFFFFFFFn; - CAPI.MEM.write(registers[rs1] + imm, 4, value, rs2, 'float32'); + let addr = registers[rs1] + imm; + if (CAPI.VALIDATION.isMisaligned(addr, 4)) + CAPI.VALIDATION.raise('The memory must be aligned'); + CAPI.MEM.write(addr, 4, value, rs2, 'float32', false); help: Store a single-precision value from floating-point register rs2 to memory. D: - name: fld @@ -3443,10 +3462,10 @@ instructions: - field: rd type: DFP-Reg definition: | - if (CAPI.VALIDATION.isMisaligned(registers[rs1] + imm, 'd')) { - CAPI.VALIDATION.raise('The memory must be aligned'); - } - registers[rd] = CAPI.MEM.read(registers[rs1] + imm, 8, rd); + let addr = registers[rs1] + imm; + if (CAPI.VALIDATION.isMisaligned(addr, 8)) + CAPI.VALIDATION.raise('The memory must be aligned'); + registers[rd] = CAPI.MEM.read(addr, 8, rd, false); help: Load a double-precision floating-point value from memory into floating-point register rd. - name: fadd.d extension: D @@ -4141,11 +4160,10 @@ instructions: - field: rs2 type: DFP-Reg definition: | - let val = BigInt("0x" + CAPI.FP.split_double(registers[rs2], 0)); - CAPI.MEM.write(registers[rs1] + imm, 4, val, rs2); - val = BigInt("0x" + CAPI.FP.split_double(registers[rs2], 1)); - CAPI.MEM.write(registers[rs1] + imm + 4n, 4, val, rs2); - CAPI.MEM.addHint(registers[rs1] + imm, "float64", 64); + let addr = registers[rs1] + imm; + if (CAPI.VALIDATION.isMisaligned(addr, 8)) + CAPI.VALIDATION.raise('The memory must be aligned'); + CAPI.MEM.write(addr, 8, registers[rs2], rs2, 'float64', false); help: Store a double-precision value from the floating-point registers to memory. Zifencei: - name: fence.i diff --git a/src/core/capi/validation.mts b/src/core/capi/validation.mts index dd4276e07..4fe2c40c5 100644 --- a/src/core/capi/validation.mts +++ b/src/core/capi/validation.mts @@ -18,6 +18,7 @@ */ import { capi_uint2int } from "./fp.mts"; +import { architecture } from "../core.mjs"; type Document = { app: { exception(msg: string): unknown } }; @@ -44,8 +45,15 @@ export function isOverflow(op1: bigint, op2: bigint, res_u: bigint) { ); } -export function isMisaligned(addr: bigint, type: string) { - return false; +/** + * Checks whether an address is misaligned + * @param addr - Base address to read/write + * @param size - Size of the element being read/written + **/ +export function isMisaligned(addr: bigint, size: bigint|number) { + const config = architecture.config; + const word_size_bytes = BigInt(config.word_size / config.byte_size); + return addr % word_size_bytes !== 0n && addr % BigInt(size) !== 0n; } // Object export for initCAPI spreading From a231b31e0cda0fe4de86c06668368a482fff8606 Mon Sep 17 00:00:00 2001 From: ALVAROPING1 Date: Tue, 17 Mar 2026 14:44:32 +0100 Subject: [PATCH 31/85] fix(executor): add proper validation of stack pointer address --- src/core/executor/executor.mjs | 40 ++++--------------- .../sentinel/test_mips_sentinels_018.s.snap | 10 +++-- .../mips/sentinel/test_mips_sentinels_018.s | 4 +- 3 files changed, 16 insertions(+), 38 deletions(-) diff --git a/src/core/executor/executor.mjs b/src/core/executor/executor.mjs index 3d8963411..577ca2f90 100644 --- a/src/core/executor/executor.mjs +++ b/src/core/executor/executor.mjs @@ -468,44 +468,20 @@ export function writeStackLimit(stackLimit) { // Get memory segments from the Memory object const segments = main_memory.getMemorySegments(); - // // Check if stack pointer would be placed in data segment - // if ( - // dataSegment && - // stackLimitBigInt <= dataSegment.end && - // stackLimitBigInt >= dataSegment.start - // ) { - // draw.danger.push(status.execution_index); - // throw packExecute( - // true, - // "Stack pointer cannot be placed in the data segment", - // "danger", - // null, - // ); - // } - - // // Check if stack pointer would be placed in text segment - // if ( - // textSegment && - // stackLimitBigInt <= textSegment.end && - // stackLimitBigInt >= textSegment.start - // ) { - // draw.danger.push(status.execution_index); - // throw packExecute( - // true, - // "Stack pointer cannot be placed in the text segment", - // "danger", - // null, - // ); - // } - // Get current stack pointer from memory segments const stackSegment = segments.get("stack"); - - // Check if stack pointer would be placed in stack segment + // Check if stack pointer would be above stack end if (stackSegment && stackLimitBigInt > stackSegment.end) { throw new Error("Stack pointer cannot be outside the stack segment"); } + // Check if stack pointer would be placed in text/data segments + for (const [name, value] of segments) { + if (name === "stack") continue; + if (value.start <= stackLimitBigInt && stackLimitBigInt <= value.end) + throw new Error(`Stack pointer cannot be placed in the ${name} segment`); + } + stackTracker.updateCurrentFrame(stackLimit); // Update the stack segment in the memory layout if it exists diff --git a/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_018.s.snap b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_018.s.snap index 27c5a83da..55e0c8f81 100644 --- a/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_018.s.snap +++ b/tests/arch/__snapshots__/mips/sentinel/test_mips_sentinels_018.s.snap @@ -7,12 +7,13 @@ snapshot[`mips/sentinel/test_mips_sentinels_018.s 1`] = ` keyboard: "", memory: { "0": 32, - "1": 29, + "1": 18, "11": 10, "15": 12, "16": 35, "17": 189, - "19": 4, + "18": 255, + "19": 252, "20": 3, "21": 224, "23": 8, @@ -23,8 +24,9 @@ snapshot[`mips/sentinel/test_mips_sentinels_018.s 1`] = ` "9": 2, }, registers: { + "18,s2": "0x5", "2,v0": "0xa", - "29,sp": "0x9", + "29,sp": "0xffffff8", "31,ra": "0x8", PC: "0x10", }, @@ -32,7 +34,7 @@ snapshot[`mips/sentinel/test_mips_sentinels_018.s 1`] = ` { function: "test", msg: "Calling convention violations in test: - - Stack pointer not restored: entered at 0x5, exited at 0x9", + - Stack pointer not restored: entered at 0xffffffc, exited at 0xffffff8", }, ], } diff --git a/tests/arch/mips/sentinel/test_mips_sentinels_018.s b/tests/arch/mips/sentinel/test_mips_sentinels_018.s index 1e133a052..5b0a0c82c 100644 --- a/tests/arch/mips/sentinel/test_mips_sentinels_018.s +++ b/tests/arch/mips/sentinel/test_mips_sentinels_018.s @@ -9,7 +9,7 @@ main: - li $sp, 5 + li $s2, 5 jal test # exit @@ -20,7 +20,7 @@ test: # crear "stack frame" para $ra, $fp y una variable local - addi $sp, $sp, 4 + addi $sp, $sp, -4 # return $v0 jr $ra From 0a9bf517e6dd257f6376481709927fe22d8fd9ea Mon Sep 17 00:00:00 2001 From: ALVAROPING1 Date: Tue, 17 Mar 2026 14:45:12 +0100 Subject: [PATCH 32/85] fix(registerOperations): fix object being thrown instead of a proper `Error` --- src/core/register/registerOperations.mjs | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/src/core/register/registerOperations.mjs b/src/core/register/registerOperations.mjs index f402fbe25..c32243d2f 100644 --- a/src/core/register/registerOperations.mjs +++ b/src/core/register/registerOperations.mjs @@ -119,12 +119,7 @@ export function writeRegister(value, indexComp, indexElem) { } draw.danger.push(status.execution_index); - throw packExecute( - true, - "The register " + elementName + " is not writeable", - "danger", - null, - ); + throw new Error(`The register ${elementName} is not writeable`); } element.value = value; From e3c0fd680d368c18ef0e53e9c789040dc2895cb8 Mon Sep 17 00:00:00 2001 From: ALVAROPING1 Date: Tue, 17 Mar 2026 14:46:03 +0100 Subject: [PATCH 33/85] tests: migration of old execution error tests --- .../test_mips_error_executor_002.s.snap | 37 +++++++++++++++++ .../test_mips_error_executor_003.s.snap | 27 ++++++++++++ .../test_mips_error_executor_004.s.snap | 34 +++++++++++++++ .../test_mips_error_executor_005.s.snap | 30 ++++++++++++++ .../test_mips_error_executor_006.s.snap | 30 ++++++++++++++ .../test_mips_error_executor_007.s.snap | 41 +++++++++++++++++++ .../test_mips_error_executor_008.s.snap | 41 +++++++++++++++++++ .../test_mips_error_executor_009.s.snap | 26 ++++++++++++ .../test_riscv_error_executor_002.s.snap | 29 +++++++++++++ .../test_riscv_error_executor_003.s.snap | 27 ++++++++++++ .../test_riscv_error_executor_004.s.snap | 35 ++++++++++++++++ .../test_riscv_error_executor_005.s.snap | 31 ++++++++++++++ .../test_riscv_error_executor_006.s.snap | 30 ++++++++++++++ .../test_riscv_error_executor_007.s.snap | 38 +++++++++++++++++ .../test_riscv_error_executor_008.s.snap | 38 +++++++++++++++++ .../test_riscv_error_executor_009.s.snap | 20 +++++++++ tests/arch/mips/error.test.mts | 12 ++++++ .../executor/test_mips_error_executor_001.out | 6 --- .../executor/test_mips_error_executor_002.out | 6 --- .../executor/test_mips_error_executor_002.s | 5 ++- .../executor/test_mips_error_executor_003.out | 6 --- .../executor/test_mips_error_executor_003.s | 1 + .../executor/test_mips_error_executor_004.out | 6 --- .../executor/test_mips_error_executor_004.s | 1 + .../executor/test_mips_error_executor_005.out | 7 ---- .../executor/test_mips_error_executor_005.s | 3 +- .../executor/test_mips_error_executor_006.out | 7 ---- .../executor/test_mips_error_executor_006.s | 3 +- .../executor/test_mips_error_executor_007.out | 7 ---- .../executor/test_mips_error_executor_007.s | 3 +- .../executor/test_mips_error_executor_008.out | 7 ---- .../executor/test_mips_error_executor_008.s | 3 +- .../executor/test_mips_error_executor_009.out | 6 --- .../executor/test_mips_error_executor_009.s | 3 +- tests/arch/riscv/error.test.mts | 11 +++++ .../executor/test_riscv_error_executor_002.s} | 3 ++ .../test_riscv_error_executor_003.out | 6 --- .../executor/test_riscv_error_executor_003.s | 1 + .../test_riscv_error_executor_004.out | 6 --- .../executor/test_riscv_error_executor_004.s | 1 + .../test_riscv_error_executor_005.out | 7 ---- .../executor/test_riscv_error_executor_005.s | 3 +- .../test_riscv_error_executor_006.out | 7 ---- .../executor/test_riscv_error_executor_006.s | 3 +- .../test_riscv_error_executor_007.out | 7 ---- .../executor/test_riscv_error_executor_007.s | 3 +- .../test_riscv_error_executor_008.out | 7 ---- .../executor/test_riscv_error_executor_008.s | 3 +- .../test_riscv_error_executor_009.out | 3 -- .../executor/test_riscv_error_executor_009.s | 3 +- 50 files changed, 567 insertions(+), 113 deletions(-) create mode 100644 tests/arch/__snapshots__/mips/error/executor/test_mips_error_executor_002.s.snap create mode 100644 tests/arch/__snapshots__/mips/error/executor/test_mips_error_executor_003.s.snap create mode 100644 tests/arch/__snapshots__/mips/error/executor/test_mips_error_executor_004.s.snap create mode 100644 tests/arch/__snapshots__/mips/error/executor/test_mips_error_executor_005.s.snap create mode 100644 tests/arch/__snapshots__/mips/error/executor/test_mips_error_executor_006.s.snap create mode 100644 tests/arch/__snapshots__/mips/error/executor/test_mips_error_executor_007.s.snap create mode 100644 tests/arch/__snapshots__/mips/error/executor/test_mips_error_executor_008.s.snap create mode 100644 tests/arch/__snapshots__/mips/error/executor/test_mips_error_executor_009.s.snap create mode 100644 tests/arch/__snapshots__/riscv/error/executor/test_riscv_error_executor_002.s.snap create mode 100644 tests/arch/__snapshots__/riscv/error/executor/test_riscv_error_executor_003.s.snap create mode 100644 tests/arch/__snapshots__/riscv/error/executor/test_riscv_error_executor_004.s.snap create mode 100644 tests/arch/__snapshots__/riscv/error/executor/test_riscv_error_executor_005.s.snap create mode 100644 tests/arch/__snapshots__/riscv/error/executor/test_riscv_error_executor_006.s.snap create mode 100644 tests/arch/__snapshots__/riscv/error/executor/test_riscv_error_executor_007.s.snap create mode 100644 tests/arch/__snapshots__/riscv/error/executor/test_riscv_error_executor_008.s.snap create mode 100644 tests/arch/__snapshots__/riscv/error/executor/test_riscv_error_executor_009.s.snap create mode 100644 tests/arch/mips/error.test.mts delete mode 100644 tests/arch/mips/error/executor/test_mips_error_executor_001.out delete mode 100644 tests/arch/mips/error/executor/test_mips_error_executor_002.out delete mode 100644 tests/arch/mips/error/executor/test_mips_error_executor_003.out delete mode 100644 tests/arch/mips/error/executor/test_mips_error_executor_004.out delete mode 100644 tests/arch/mips/error/executor/test_mips_error_executor_005.out delete mode 100644 tests/arch/mips/error/executor/test_mips_error_executor_006.out delete mode 100644 tests/arch/mips/error/executor/test_mips_error_executor_007.out delete mode 100644 tests/arch/mips/error/executor/test_mips_error_executor_008.out delete mode 100644 tests/arch/mips/error/executor/test_mips_error_executor_009.out create mode 100644 tests/arch/riscv/error.test.mts rename tests/arch/{mips/error/executor/test_mips_error_executor_001.s => riscv/error/executor/test_riscv_error_executor_002.s} (62%) delete mode 100644 tests/arch/riscv/error/executor/test_riscv_error_executor_003.out delete mode 100644 tests/arch/riscv/error/executor/test_riscv_error_executor_004.out delete mode 100644 tests/arch/riscv/error/executor/test_riscv_error_executor_005.out delete mode 100644 tests/arch/riscv/error/executor/test_riscv_error_executor_006.out delete mode 100644 tests/arch/riscv/error/executor/test_riscv_error_executor_007.out delete mode 100644 tests/arch/riscv/error/executor/test_riscv_error_executor_008.out delete mode 100644 tests/arch/riscv/error/executor/test_riscv_error_executor_009.out diff --git a/tests/arch/__snapshots__/mips/error/executor/test_mips_error_executor_002.s.snap b/tests/arch/__snapshots__/mips/error/executor/test_mips_error_executor_002.s.snap new file mode 100644 index 000000000..4b9a9294e --- /dev/null +++ b/tests/arch/__snapshots__/mips/error/executor/test_mips_error_executor_002.s.snap @@ -0,0 +1,37 @@ +export const snapshot = {}; + +snapshot[`mips/error/executor/test_mips_error_executor_002.s 1`] = ` +{ + display: "", + error: false, + instruction_errors: [ + { + error: "Stack pointer cannot be outside the stack segment", + i: 2, + }, + ], + keyboard: "", + memory: { + "0": 60, + "1": 1, + "10": 232, + "11": 32, + "12": 3, + "13": 224, + "15": 8, + "2": 255, + "3": 255, + "4": 52, + "5": 33, + "6": 255, + "7": 255, + "9": 32, + }, + registers: { + "1,at": "0xffffffff", + "29,sp": "0xffffffff", + PC: "0xffffffff", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/error/executor/test_mips_error_executor_003.s.snap b/tests/arch/__snapshots__/mips/error/executor/test_mips_error_executor_003.s.snap new file mode 100644 index 000000000..ce7c73b21 --- /dev/null +++ b/tests/arch/__snapshots__/mips/error/executor/test_mips_error_executor_003.s.snap @@ -0,0 +1,27 @@ +export const snapshot = {}; + +snapshot[`mips/error/executor/test_mips_error_executor_003.s 1`] = ` +{ + display: "", + error: false, + instruction_errors: [ + { + error: "Stack pointer cannot be placed in the text segment", + i: 0, + }, + ], + keyboard: "", + memory: { + "0": 32, + "1": 29, + "4": 3, + "5": 224, + "7": 8, + }, + registers: { + "29,sp": "0x0", + PC: "0xffffffff", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/error/executor/test_mips_error_executor_004.s.snap b/tests/arch/__snapshots__/mips/error/executor/test_mips_error_executor_004.s.snap new file mode 100644 index 000000000..488b0efca --- /dev/null +++ b/tests/arch/__snapshots__/mips/error/executor/test_mips_error_executor_004.s.snap @@ -0,0 +1,34 @@ +export const snapshot = {}; + +snapshot[`mips/error/executor/test_mips_error_executor_004.s 1`] = ` +{ + display: "", + error: false, + instruction_errors: [ + { + error: "Stack pointer cannot be placed in the data segment", + i: 2, + }, + ], + keyboard: "", + memory: { + "0": 60, + "1": 1, + "10": 232, + "11": 32, + "12": 3, + "13": 224, + "15": 8, + "3": 32, + "4": 52, + "5": 33, + "9": 32, + }, + registers: { + "1,at": "0x200000", + "29,sp": "0x200000", + PC: "0xffffffff", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/error/executor/test_mips_error_executor_005.s.snap b/tests/arch/__snapshots__/mips/error/executor/test_mips_error_executor_005.s.snap new file mode 100644 index 000000000..898273a85 --- /dev/null +++ b/tests/arch/__snapshots__/mips/error/executor/test_mips_error_executor_005.s.snap @@ -0,0 +1,30 @@ +export const snapshot = {}; + +snapshot[`mips/error/executor/test_mips_error_executor_005.s 1`] = ` +{ + display: "", + error: false, + instruction_errors: [ + { + error: "Segmentation fault. You tried to write in the text segment", + i: 1, + }, + ], + keyboard: "", + memory: { + "0": 32, + "1": 8, + "11": 8, + "3": 10, + "4": 172, + "5": 8, + "8": 3, + "9": 224, + }, + registers: { + "8,t0": "0xa", + PC: "0xffffffff", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/error/executor/test_mips_error_executor_006.s.snap b/tests/arch/__snapshots__/mips/error/executor/test_mips_error_executor_006.s.snap new file mode 100644 index 000000000..7839c58b4 --- /dev/null +++ b/tests/arch/__snapshots__/mips/error/executor/test_mips_error_executor_006.s.snap @@ -0,0 +1,30 @@ +export const snapshot = {}; + +snapshot[`mips/error/executor/test_mips_error_executor_006.s 1`] = ` +{ + display: "", + error: false, + instruction_errors: [ + { + error: "Segmentation fault. You tried to read in the text segment (00000000)", + i: 1, + }, + ], + keyboard: "", + memory: { + "0": 32, + "1": 8, + "11": 8, + "3": 10, + "4": 140, + "5": 8, + "8": 3, + "9": 224, + }, + registers: { + "8,t0": "0xa", + PC: "0xffffffff", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/error/executor/test_mips_error_executor_007.s.snap b/tests/arch/__snapshots__/mips/error/executor/test_mips_error_executor_007.s.snap new file mode 100644 index 000000000..30db9fc1a --- /dev/null +++ b/tests/arch/__snapshots__/mips/error/executor/test_mips_error_executor_007.s.snap @@ -0,0 +1,41 @@ +export const snapshot = {}; + +snapshot[`mips/error/executor/test_mips_error_executor_007.s 1`] = ` +{ + display: "", + error: false, + instruction_errors: [ + { + error: "The memory must be aligned", + i: 4, + }, + ], + keyboard: "", + memory: { + "0": 60, + "1": 1, + "10": 64, + "11": 32, + "12": 32, + "13": 9, + "15": 10, + "16": 173, + "17": 9, + "19": 1, + "20": 3, + "21": 224, + "23": 8, + "3": 32, + "4": 52, + "5": 33, + "9": 32, + }, + registers: { + "1,at": "0x200000", + "8,t0": "0x200000", + "9,t1": "0xa", + PC: "0xffffffff", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/error/executor/test_mips_error_executor_008.s.snap b/tests/arch/__snapshots__/mips/error/executor/test_mips_error_executor_008.s.snap new file mode 100644 index 000000000..516516598 --- /dev/null +++ b/tests/arch/__snapshots__/mips/error/executor/test_mips_error_executor_008.s.snap @@ -0,0 +1,41 @@ +export const snapshot = {}; + +snapshot[`mips/error/executor/test_mips_error_executor_008.s 1`] = ` +{ + display: "", + error: false, + instruction_errors: [ + { + error: "The memory must be aligned", + i: 4, + }, + ], + keyboard: "", + memory: { + "0": 60, + "1": 1, + "10": 64, + "11": 32, + "12": 32, + "13": 9, + "15": 10, + "16": 141, + "17": 9, + "19": 1, + "20": 3, + "21": 224, + "23": 8, + "3": 32, + "4": 52, + "5": 33, + "9": 32, + }, + registers: { + "1,at": "0x200000", + "8,t0": "0x200000", + "9,t1": "0xa", + PC: "0xffffffff", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/mips/error/executor/test_mips_error_executor_009.s.snap b/tests/arch/__snapshots__/mips/error/executor/test_mips_error_executor_009.s.snap new file mode 100644 index 000000000..a13c076be --- /dev/null +++ b/tests/arch/__snapshots__/mips/error/executor/test_mips_error_executor_009.s.snap @@ -0,0 +1,26 @@ +export const snapshot = {}; + +snapshot[`mips/error/executor/test_mips_error_executor_009.s 1`] = ` +{ + display: "", + error: false, + instruction_errors: [ + { + error: "The register 0 | zero is not writeable", + i: 0, + }, + ], + keyboard: "", + memory: { + "0": 32, + "3": 10, + "4": 3, + "5": 224, + "7": 8, + }, + registers: { + PC: "0xffffffff", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/error/executor/test_riscv_error_executor_002.s.snap b/tests/arch/__snapshots__/riscv/error/executor/test_riscv_error_executor_002.s.snap new file mode 100644 index 000000000..859bee583 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/error/executor/test_riscv_error_executor_002.s.snap @@ -0,0 +1,29 @@ +export const snapshot = {}; + +snapshot[`riscv/error/executor/test_riscv_error_executor_002.s 1`] = ` +{ + display: "", + error: false, + instruction_errors: [ + { + error: "Stack pointer cannot be outside the stack segment", + i: 0, + }, + ], + keyboard: "", + memory: { + "0": 255, + "1": 240, + "2": 1, + "3": 19, + "6": 128, + "7": 103, + }, + registers: { + "x2,sp": "0xffffffff", + mtime: "0x1", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/error/executor/test_riscv_error_executor_003.s.snap b/tests/arch/__snapshots__/riscv/error/executor/test_riscv_error_executor_003.s.snap new file mode 100644 index 000000000..dc6f2613a --- /dev/null +++ b/tests/arch/__snapshots__/riscv/error/executor/test_riscv_error_executor_003.s.snap @@ -0,0 +1,27 @@ +export const snapshot = {}; + +snapshot[`riscv/error/executor/test_riscv_error_executor_003.s 1`] = ` +{ + display: "", + error: false, + instruction_errors: [ + { + error: "Stack pointer cannot be placed in the text segment", + i: 0, + }, + ], + keyboard: "", + memory: { + "2": 1, + "3": 19, + "6": 128, + "7": 103, + }, + registers: { + "x2,sp": "0x0", + mtime: "0x1", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/error/executor/test_riscv_error_executor_004.s.snap b/tests/arch/__snapshots__/riscv/error/executor/test_riscv_error_executor_004.s.snap new file mode 100644 index 000000000..efbd927e5 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/error/executor/test_riscv_error_executor_004.s.snap @@ -0,0 +1,35 @@ +export const snapshot = {}; + +snapshot[`riscv/error/executor/test_riscv_error_executor_004.s 1`] = ` +{ + display: "", + error: false, + instruction_errors: [ + { + error: "Stack pointer cannot be placed in the data segment", + i: 2, + }, + ], + keyboard: "", + memory: { + "1": 32, + "10": 129, + "11": 19, + "14": 128, + "15": 103, + "2": 2, + "3": 183, + "5": 2, + "6": 130, + "7": 147, + "9": 2, + }, + registers: { + "x2,sp": "0x200000", + "x5,t0": "0x200000", + mtime: "0x3", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/error/executor/test_riscv_error_executor_005.s.snap b/tests/arch/__snapshots__/riscv/error/executor/test_riscv_error_executor_005.s.snap new file mode 100644 index 000000000..c9c825533 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/error/executor/test_riscv_error_executor_005.s.snap @@ -0,0 +1,31 @@ +export const snapshot = {}; + +snapshot[`riscv/error/executor/test_riscv_error_executor_005.s 1`] = ` +{ + display: "", + error: false, + instruction_errors: [ + { + error: "Segmentation fault. You tried to write in the text segment", + i: 1, + }, + ], + keyboard: "", + memory: { + "1": 160, + "10": 128, + "11": 103, + "2": 2, + "3": 147, + "5": 80, + "6": 32, + "7": 35, + }, + registers: { + "x5,t0": "0xa", + mtime: "0x2", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/error/executor/test_riscv_error_executor_006.s.snap b/tests/arch/__snapshots__/riscv/error/executor/test_riscv_error_executor_006.s.snap new file mode 100644 index 000000000..586ceb0c5 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/error/executor/test_riscv_error_executor_006.s.snap @@ -0,0 +1,30 @@ +export const snapshot = {}; + +snapshot[`riscv/error/executor/test_riscv_error_executor_006.s 1`] = ` +{ + display: "", + error: false, + instruction_errors: [ + { + error: "Segmentation fault. You tried to read in the text segment (00000000)", + i: 1, + }, + ], + keyboard: "", + memory: { + "1": 160, + "10": 128, + "11": 103, + "2": 2, + "3": 147, + "6": 34, + "7": 131, + }, + registers: { + "x5,t0": "0xa", + mtime: "0x2", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/error/executor/test_riscv_error_executor_007.s.snap b/tests/arch/__snapshots__/riscv/error/executor/test_riscv_error_executor_007.s.snap new file mode 100644 index 000000000..9ebb39bea --- /dev/null +++ b/tests/arch/__snapshots__/riscv/error/executor/test_riscv_error_executor_007.s.snap @@ -0,0 +1,38 @@ +export const snapshot = {}; + +snapshot[`riscv/error/executor/test_riscv_error_executor_007.s 1`] = ` +{ + display: "", + error: false, + instruction_errors: [ + { + error: "The memory must be aligned", + i: 3, + }, + ], + keyboard: "", + memory: { + "1": 32, + "10": 3, + "11": 19, + "13": 98, + "14": 160, + "15": 163, + "18": 128, + "19": 103, + "2": 2, + "3": 151, + "5": 2, + "6": 130, + "7": 147, + "9": 160, + }, + registers: { + "x5,t0": "0x200000", + "x6,t1": "0xa", + mtime: "0x4", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/error/executor/test_riscv_error_executor_008.s.snap b/tests/arch/__snapshots__/riscv/error/executor/test_riscv_error_executor_008.s.snap new file mode 100644 index 000000000..d5905944b --- /dev/null +++ b/tests/arch/__snapshots__/riscv/error/executor/test_riscv_error_executor_008.s.snap @@ -0,0 +1,38 @@ +export const snapshot = {}; + +snapshot[`riscv/error/executor/test_riscv_error_executor_008.s 1`] = ` +{ + display: "", + error: false, + instruction_errors: [ + { + error: "The memory must be aligned", + i: 3, + }, + ], + keyboard: "", + memory: { + "1": 32, + "10": 3, + "11": 19, + "13": 18, + "14": 163, + "15": 3, + "18": 128, + "19": 103, + "2": 2, + "3": 151, + "5": 2, + "6": 130, + "7": 147, + "9": 160, + }, + registers: { + "x5,t0": "0x200000", + "x6,t1": "0xa", + mtime: "0x4", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/error/executor/test_riscv_error_executor_009.s.snap b/tests/arch/__snapshots__/riscv/error/executor/test_riscv_error_executor_009.s.snap new file mode 100644 index 000000000..65c9cf25a --- /dev/null +++ b/tests/arch/__snapshots__/riscv/error/executor/test_riscv_error_executor_009.s.snap @@ -0,0 +1,20 @@ +export const snapshot = {}; + +snapshot[`riscv/error/executor/test_riscv_error_executor_009.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "1": 160, + "3": 19, + "6": 128, + "7": 103, + }, + registers: { + mtime: "0x2", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/mips/error.test.mts b/tests/arch/mips/error.test.mts new file mode 100644 index 000000000..2bd41e175 --- /dev/null +++ b/tests/arch/mips/error.test.mts @@ -0,0 +1,12 @@ +import { ARCH, snapshot_tests } from "../arch_utils.mts"; + +snapshot_tests(ARCH.mips, "mips/error/executor", undefined, new Set([ + "test_mips_error_executor_002.s", + "test_mips_error_executor_003.s", + "test_mips_error_executor_004.s", + "test_mips_error_executor_005.s", + "test_mips_error_executor_006.s", + "test_mips_error_executor_007.s", + "test_mips_error_executor_008.s", + "test_mips_error_executor_009.s", +])); diff --git a/tests/arch/mips/error/executor/test_mips_error_executor_001.out b/tests/arch/mips/error/executor/test_mips_error_executor_001.out deleted file mode 100644 index 5c4077cc1..000000000 --- a/tests/arch/mips/error/executor/test_mips_error_executor_001.out +++ /dev/null @@ -1,6 +0,0 @@ - - - Error found. - No instructions in memory -keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/error/executor/test_mips_error_executor_002.out b/tests/arch/mips/error/executor/test_mips_error_executor_002.out deleted file mode 100644 index 0719a3681..000000000 --- a/tests/arch/mips/error/executor/test_mips_error_executor_002.out +++ /dev/null @@ -1,6 +0,0 @@ - - - Error found. - Label "main" not found -keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/error/executor/test_mips_error_executor_002.s b/tests/arch/mips/error/executor/test_mips_error_executor_002.s index 6ad952bf9..98f743490 100644 --- a/tests/arch/mips/error/executor/test_mips_error_executor_002.s +++ b/tests/arch/mips/error/executor/test_mips_error_executor_002.s @@ -4,5 +4,6 @@ # .text -main_: - li $t0, 10 +main: + li $sp, 0xffffffff + jr $ra diff --git a/tests/arch/mips/error/executor/test_mips_error_executor_003.out b/tests/arch/mips/error/executor/test_mips_error_executor_003.out deleted file mode 100644 index 55840b182..000000000 --- a/tests/arch/mips/error/executor/test_mips_error_executor_003.out +++ /dev/null @@ -1,6 +0,0 @@ - - - Error found. - Stack pointer cannot be placed in the text segment -cr[PC]:0x4; ir[29,sp]:0x0; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/error/executor/test_mips_error_executor_003.s b/tests/arch/mips/error/executor/test_mips_error_executor_003.s index b481c85ad..f85c4419d 100644 --- a/tests/arch/mips/error/executor/test_mips_error_executor_003.s +++ b/tests/arch/mips/error/executor/test_mips_error_executor_003.s @@ -6,3 +6,4 @@ .text main: li $sp, 0 + jr $ra diff --git a/tests/arch/mips/error/executor/test_mips_error_executor_004.out b/tests/arch/mips/error/executor/test_mips_error_executor_004.out deleted file mode 100644 index 64d1a4355..000000000 --- a/tests/arch/mips/error/executor/test_mips_error_executor_004.out +++ /dev/null @@ -1,6 +0,0 @@ - - - Error found. - Stack pointer cannot be placed in the data segment -cr[PC]:0xc; ir[1,at]:0x200000; ir[29,sp]:0x200000; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/error/executor/test_mips_error_executor_004.s b/tests/arch/mips/error/executor/test_mips_error_executor_004.s index 63eea2c51..7d4666d73 100644 --- a/tests/arch/mips/error/executor/test_mips_error_executor_004.s +++ b/tests/arch/mips/error/executor/test_mips_error_executor_004.s @@ -6,3 +6,4 @@ .text main: li $sp, 0x00200000 + jr $ra diff --git a/tests/arch/mips/error/executor/test_mips_error_executor_005.out b/tests/arch/mips/error/executor/test_mips_error_executor_005.out deleted file mode 100644 index 6a1c963ae..000000000 --- a/tests/arch/mips/error/executor/test_mips_error_executor_005.out +++ /dev/null @@ -1,7 +0,0 @@ - -Segmentation fault. You tried to write in the text segment - - Error found. - The program has finished with errors -cr[PC]:0x8; ir[8,t0]:0xa; memory[0x3]:0x0a; memory[0x1]:0x00; memory[0x0]:0x00; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/error/executor/test_mips_error_executor_005.s b/tests/arch/mips/error/executor/test_mips_error_executor_005.s index 2b34bfa8e..4295fb47b 100644 --- a/tests/arch/mips/error/executor/test_mips_error_executor_005.s +++ b/tests/arch/mips/error/executor/test_mips_error_executor_005.s @@ -7,4 +7,5 @@ main: li $t0, 10 - sw $t0, 0 \ No newline at end of file + sw $t0, 0 + jr $ra diff --git a/tests/arch/mips/error/executor/test_mips_error_executor_006.out b/tests/arch/mips/error/executor/test_mips_error_executor_006.out deleted file mode 100644 index 04b86e53d..000000000 --- a/tests/arch/mips/error/executor/test_mips_error_executor_006.out +++ /dev/null @@ -1,7 +0,0 @@ - -Segmentation fault. You tried to read in the text segment - - Error found. - The program has finished with errors -cr[PC]:0x8; ir[8,t0]:0x2008000a; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/error/executor/test_mips_error_executor_006.s b/tests/arch/mips/error/executor/test_mips_error_executor_006.s index b71603663..f5ac66fb0 100644 --- a/tests/arch/mips/error/executor/test_mips_error_executor_006.s +++ b/tests/arch/mips/error/executor/test_mips_error_executor_006.s @@ -7,4 +7,5 @@ main: li $t0, 10 - lw $t0, 0 \ No newline at end of file + lw $t0, 0 + jr $ra diff --git a/tests/arch/mips/error/executor/test_mips_error_executor_007.out b/tests/arch/mips/error/executor/test_mips_error_executor_007.out deleted file mode 100644 index a2bde039a..000000000 --- a/tests/arch/mips/error/executor/test_mips_error_executor_007.out +++ /dev/null @@ -1,7 +0,0 @@ - -The memory must be align - - Error found. - The program has finished with errors -cr[PC]:0x14; ir[1,at]:0x200000; ir[8,t0]:0x200000; ir[9,t1]:0xa; memory[0x200004]:0x0a; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/error/executor/test_mips_error_executor_007.s b/tests/arch/mips/error/executor/test_mips_error_executor_007.s index d7dc6f383..ac6904039 100644 --- a/tests/arch/mips/error/executor/test_mips_error_executor_007.s +++ b/tests/arch/mips/error/executor/test_mips_error_executor_007.s @@ -11,4 +11,5 @@ main: la $t0, a li $t1, 10 - sw $t1, 1($t0) \ No newline at end of file + sw $t1, 1($t0) + jr $ra diff --git a/tests/arch/mips/error/executor/test_mips_error_executor_008.out b/tests/arch/mips/error/executor/test_mips_error_executor_008.out deleted file mode 100644 index 0fe23d1da..000000000 --- a/tests/arch/mips/error/executor/test_mips_error_executor_008.out +++ /dev/null @@ -1,7 +0,0 @@ - -The memory must be align - - Error found. - The program has finished with errors -cr[PC]:0x14; ir[1,at]:0x200000; ir[8,t0]:0x200000; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/error/executor/test_mips_error_executor_008.s b/tests/arch/mips/error/executor/test_mips_error_executor_008.s index aa287ad80..c16028e5f 100644 --- a/tests/arch/mips/error/executor/test_mips_error_executor_008.s +++ b/tests/arch/mips/error/executor/test_mips_error_executor_008.s @@ -11,4 +11,5 @@ main: la $t0, a li $t1, 10 - lw $t1, 1($t0) \ No newline at end of file + lw $t1, 1($t0) + jr $ra diff --git a/tests/arch/mips/error/executor/test_mips_error_executor_009.out b/tests/arch/mips/error/executor/test_mips_error_executor_009.out deleted file mode 100644 index 4250e5e73..000000000 --- a/tests/arch/mips/error/executor/test_mips_error_executor_009.out +++ /dev/null @@ -1,6 +0,0 @@ - - - Error found. - The register 0 | zero cannot be written -cr[PC]:0x4; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/error/executor/test_mips_error_executor_009.s b/tests/arch/mips/error/executor/test_mips_error_executor_009.s index f9fb1b439..3fece1246 100644 --- a/tests/arch/mips/error/executor/test_mips_error_executor_009.s +++ b/tests/arch/mips/error/executor/test_mips_error_executor_009.s @@ -6,4 +6,5 @@ .text main: - li $zero, 10 \ No newline at end of file + li $zero, 10 + jr $ra diff --git a/tests/arch/riscv/error.test.mts b/tests/arch/riscv/error.test.mts new file mode 100644 index 000000000..f460d6507 --- /dev/null +++ b/tests/arch/riscv/error.test.mts @@ -0,0 +1,11 @@ +import { ARCH, snapshot_tests } from "../arch_utils.mts"; + +snapshot_tests(ARCH.riscv, "riscv/error/executor", undefined, new Set([ + "test_riscv_error_executor_002.s", + "test_riscv_error_executor_003.s", + "test_riscv_error_executor_004.s", + "test_riscv_error_executor_005.s", + "test_riscv_error_executor_006.s", + "test_riscv_error_executor_007.s", + "test_riscv_error_executor_008.s", +])); diff --git a/tests/arch/mips/error/executor/test_mips_error_executor_001.s b/tests/arch/riscv/error/executor/test_riscv_error_executor_002.s similarity index 62% rename from tests/arch/mips/error/executor/test_mips_error_executor_001.s rename to tests/arch/riscv/error/executor/test_riscv_error_executor_002.s index fe029decf..3aa637410 100644 --- a/tests/arch/mips/error/executor/test_mips_error_executor_001.s +++ b/tests/arch/riscv/error/executor/test_riscv_error_executor_002.s @@ -4,3 +4,6 @@ # .text +main: + li sp, 0xffffffff + jr ra diff --git a/tests/arch/riscv/error/executor/test_riscv_error_executor_003.out b/tests/arch/riscv/error/executor/test_riscv_error_executor_003.out deleted file mode 100644 index 41f939f68..000000000 --- a/tests/arch/riscv/error/executor/test_riscv_error_executor_003.out +++ /dev/null @@ -1,6 +0,0 @@ - - - Error found. - Stack pointer cannot be placed in the text segment -cr[PC]:0x4; ir[x2,sp]:0x0; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/error/executor/test_riscv_error_executor_003.s b/tests/arch/riscv/error/executor/test_riscv_error_executor_003.s index d61e3decb..6e4c1c4c8 100644 --- a/tests/arch/riscv/error/executor/test_riscv_error_executor_003.s +++ b/tests/arch/riscv/error/executor/test_riscv_error_executor_003.s @@ -6,3 +6,4 @@ .text main: li sp, 0 + jr ra diff --git a/tests/arch/riscv/error/executor/test_riscv_error_executor_004.out b/tests/arch/riscv/error/executor/test_riscv_error_executor_004.out deleted file mode 100644 index fffc73ce7..000000000 --- a/tests/arch/riscv/error/executor/test_riscv_error_executor_004.out +++ /dev/null @@ -1,6 +0,0 @@ - - - Error found. - Stack pointer cannot be placed in the data segment -cr[PC]:0xc; ir[x2,sp]:0x200000; ir[x5,t0]:0x200000; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/error/executor/test_riscv_error_executor_004.s b/tests/arch/riscv/error/executor/test_riscv_error_executor_004.s index 57d3a7ae8..10506d2ba 100644 --- a/tests/arch/riscv/error/executor/test_riscv_error_executor_004.s +++ b/tests/arch/riscv/error/executor/test_riscv_error_executor_004.s @@ -7,3 +7,4 @@ main: li t0, 0x00200000 mv sp, t0 + jr ra diff --git a/tests/arch/riscv/error/executor/test_riscv_error_executor_005.out b/tests/arch/riscv/error/executor/test_riscv_error_executor_005.out deleted file mode 100644 index ebc756a9e..000000000 --- a/tests/arch/riscv/error/executor/test_riscv_error_executor_005.out +++ /dev/null @@ -1,7 +0,0 @@ - -Segmentation fault. You tried to write in the text segment - - Error found. - The program has finished with errors -cr[PC]:0x8; ir[x5,t0]:0xa; memory[0x3]:0x0a; memory[0x2]:0x00; memory[0x1]:0x00; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/error/executor/test_riscv_error_executor_005.s b/tests/arch/riscv/error/executor/test_riscv_error_executor_005.s index 6f81fdadc..acd9bceea 100644 --- a/tests/arch/riscv/error/executor/test_riscv_error_executor_005.s +++ b/tests/arch/riscv/error/executor/test_riscv_error_executor_005.s @@ -7,4 +7,5 @@ main: li t0, 10 - sw t0, 0(zero) \ No newline at end of file + sw t0, 0(zero) + jr ra diff --git a/tests/arch/riscv/error/executor/test_riscv_error_executor_006.out b/tests/arch/riscv/error/executor/test_riscv_error_executor_006.out deleted file mode 100644 index 641a1da44..000000000 --- a/tests/arch/riscv/error/executor/test_riscv_error_executor_006.out +++ /dev/null @@ -1,7 +0,0 @@ - -Segmentation fault. You tried to read in the text segment - - Error found. - The program has finished with errors -cr[PC]:0x8; ir[x5,t0]:0xa00293; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/error/executor/test_riscv_error_executor_006.s b/tests/arch/riscv/error/executor/test_riscv_error_executor_006.s index c72cd28e6..aaae79cb6 100644 --- a/tests/arch/riscv/error/executor/test_riscv_error_executor_006.s +++ b/tests/arch/riscv/error/executor/test_riscv_error_executor_006.s @@ -7,4 +7,5 @@ main: li t0, 10 - lw t0, 0(zero) \ No newline at end of file + lw t0, 0(zero) + jr ra diff --git a/tests/arch/riscv/error/executor/test_riscv_error_executor_007.out b/tests/arch/riscv/error/executor/test_riscv_error_executor_007.out deleted file mode 100644 index 15ec1b3b1..000000000 --- a/tests/arch/riscv/error/executor/test_riscv_error_executor_007.out +++ /dev/null @@ -1,7 +0,0 @@ - -The memory must be align - - Error found. - The program has finished with errors -cr[PC]:0x10; ir[x5,t0]:0x200000; ir[x6,t1]:0xa; memory[0x200004]:0x0a; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/error/executor/test_riscv_error_executor_007.s b/tests/arch/riscv/error/executor/test_riscv_error_executor_007.s index dd90edd83..c591ec62d 100644 --- a/tests/arch/riscv/error/executor/test_riscv_error_executor_007.s +++ b/tests/arch/riscv/error/executor/test_riscv_error_executor_007.s @@ -11,4 +11,5 @@ main: la t0, a li t1, 10 - sw t1, 1(t0) \ No newline at end of file + sw t1, 1(t0) + jr ra diff --git a/tests/arch/riscv/error/executor/test_riscv_error_executor_008.out b/tests/arch/riscv/error/executor/test_riscv_error_executor_008.out deleted file mode 100644 index 949224d25..000000000 --- a/tests/arch/riscv/error/executor/test_riscv_error_executor_008.out +++ /dev/null @@ -1,7 +0,0 @@ - -The memory must be align - - Error found. - The program has finished with errors -cr[PC]:0x10; ir[x5,t0]:0x200000; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/error/executor/test_riscv_error_executor_008.s b/tests/arch/riscv/error/executor/test_riscv_error_executor_008.s index 519330089..8535757fa 100644 --- a/tests/arch/riscv/error/executor/test_riscv_error_executor_008.s +++ b/tests/arch/riscv/error/executor/test_riscv_error_executor_008.s @@ -11,4 +11,5 @@ main: la t0, a li t1, 10 - lw t1, 1(t0) \ No newline at end of file + lw t1, 1(t0) + jr ra diff --git a/tests/arch/riscv/error/executor/test_riscv_error_executor_009.out b/tests/arch/riscv/error/executor/test_riscv_error_executor_009.out deleted file mode 100644 index e65d3b74b..000000000 --- a/tests/arch/riscv/error/executor/test_riscv_error_executor_009.out +++ /dev/null @@ -1,3 +0,0 @@ - -cr[PC]:0x4; keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/error/executor/test_riscv_error_executor_009.s b/tests/arch/riscv/error/executor/test_riscv_error_executor_009.s index 8e37924be..fdb3b3167 100644 --- a/tests/arch/riscv/error/executor/test_riscv_error_executor_009.s +++ b/tests/arch/riscv/error/executor/test_riscv_error_executor_009.s @@ -6,4 +6,5 @@ .text main: - li zero, 10 \ No newline at end of file + li zero, 10 + jr ra From 2c70662c72894af97322dc0af0a6901cf9bad634 Mon Sep 17 00:00:00 2001 From: ALVAROPING1 Date: Wed, 18 Mar 2026 11:21:04 +0100 Subject: [PATCH 34/85] tests: remove keyboard echo while running tests --- src/core/executor/IO.mjs | 1 - 1 file changed, 1 deletion(-) diff --git a/src/core/executor/IO.mjs b/src/core/executor/IO.mjs index 3d6316ac7..803c29142 100644 --- a/src/core/executor/IO.mjs +++ b/src/core/executor/IO.mjs @@ -219,7 +219,6 @@ function checkEnter(buf) { function rawPrompt() { if (testKeyboard.enable) { const data = testKeyboard.data.shift() || "" - process.stdout.write(data); // Echo the character return data } // Build input character by character until we hit Enter From 2d3b3c1800fcb9a178d7970edca5056936bae8cf Mon Sep 17 00:00:00 2001 From: ALVAROPING1 Date: Wed, 18 Mar 2026 12:10:45 +0100 Subject: [PATCH 35/85] tests: rename snapshot tests to execution tests --- tests/arch/arch_utils.mts | 9 ++++++--- tests/arch/mips/correct.test.mts | 6 +++--- tests/arch/mips/error.test.mts | 27 +++++++++++++++----------- tests/arch/mips/instructions.test.mts | 11 +++++++---- tests/arch/mips/sentinel.test.mts | 4 ++-- tests/arch/riscv/correct.test.mts | 6 +++--- tests/arch/riscv/error.test.mts | 25 ++++++++++++++---------- tests/arch/riscv/instructions.test.mts | 4 ++-- tests/arch/riscv/sentinel.test.mts | 4 ++-- 9 files changed, 56 insertions(+), 40 deletions(-) diff --git a/tests/arch/arch_utils.mts b/tests/arch/arch_utils.mts index 10200a4fc..55b019578 100644 --- a/tests/arch/arch_utils.mts +++ b/tests/arch/arch_utils.mts @@ -28,7 +28,7 @@ const PREFIX = path.fromFileUrl(import.meta.url + "/../../../"); * use an empty input * @param expect_error - Set of test file names that are expected to throw errors during execution */ -export function snapshot_tests( +export function execution_tests( archPath: string, dir: string, keyboard: Map = new Map(), @@ -61,7 +61,7 @@ export function snapshot_tests( // Execute code let result = { output: "", error: false }; - const instruction_errors: {i: number, error: string}[] = []; + const instruction_errors: { i: number; error: string }[] = []; for (let i = 0; i < 1000; i++) { try { result = executeStep(); @@ -69,7 +69,10 @@ export function snapshot_tests( break; } catch (e) { if (errors) - instruction_errors.push({i, error: (e as Error).message}); + instruction_errors.push({ + i, + error: (e as Error).message, + }); else throw e; } } diff --git a/tests/arch/mips/correct.test.mts b/tests/arch/mips/correct.test.mts index dab94b20c..718c3dfdf 100644 --- a/tests/arch/mips/correct.test.mts +++ b/tests/arch/mips/correct.test.mts @@ -1,9 +1,9 @@ -import { ARCH, snapshot_tests } from "../arch_utils.mts"; +import { ARCH, execution_tests } from "../arch_utils.mts"; const long_str = "This is a very long string with many characters and a lot of data. :) 123\n"; -snapshot_tests( +execution_tests( ARCH.mips, "mips/correct/examples", new Map([ @@ -11,7 +11,7 @@ snapshot_tests( ["test_mips_example_010.s", [long_str.length + "\n", long_str]], ]), ); -snapshot_tests( +execution_tests( ARCH.mips, "mips/correct/syscalls", new Map([ diff --git a/tests/arch/mips/error.test.mts b/tests/arch/mips/error.test.mts index 2bd41e175..cbd1a9b36 100644 --- a/tests/arch/mips/error.test.mts +++ b/tests/arch/mips/error.test.mts @@ -1,12 +1,17 @@ -import { ARCH, snapshot_tests } from "../arch_utils.mts"; +import { ARCH, execution_tests } from "../arch_utils.mts"; -snapshot_tests(ARCH.mips, "mips/error/executor", undefined, new Set([ - "test_mips_error_executor_002.s", - "test_mips_error_executor_003.s", - "test_mips_error_executor_004.s", - "test_mips_error_executor_005.s", - "test_mips_error_executor_006.s", - "test_mips_error_executor_007.s", - "test_mips_error_executor_008.s", - "test_mips_error_executor_009.s", -])); +execution_tests( + ARCH.mips, + "mips/error/executor", + undefined, + new Set([ + "test_mips_error_executor_002.s", + "test_mips_error_executor_003.s", + "test_mips_error_executor_004.s", + "test_mips_error_executor_005.s", + "test_mips_error_executor_006.s", + "test_mips_error_executor_007.s", + "test_mips_error_executor_008.s", + "test_mips_error_executor_009.s", + ]), +); diff --git a/tests/arch/mips/instructions.test.mts b/tests/arch/mips/instructions.test.mts index fcf5b9933..426b2d941 100644 --- a/tests/arch/mips/instructions.test.mts +++ b/tests/arch/mips/instructions.test.mts @@ -1,5 +1,8 @@ -import { ARCH, snapshot_tests } from "../arch_utils.mts" +import { ARCH, execution_tests } from "../arch_utils.mts"; -snapshot_tests(ARCH.mips, "mips/instructions", undefined, new Set([ - "test_mips_instruction_058.s", "test_mips_instruction_064.s" -])); +execution_tests( + ARCH.mips, + "mips/instructions", + undefined, + new Set(["test_mips_instruction_058.s", "test_mips_instruction_064.s"]), +); diff --git a/tests/arch/mips/sentinel.test.mts b/tests/arch/mips/sentinel.test.mts index 542729330..90e3c6cde 100644 --- a/tests/arch/mips/sentinel.test.mts +++ b/tests/arch/mips/sentinel.test.mts @@ -1,3 +1,3 @@ -import { ARCH, snapshot_tests } from "../arch_utils.mts" +import { ARCH, execution_tests } from "../arch_utils.mts"; -snapshot_tests(ARCH.mips, "mips/sentinel"); +execution_tests(ARCH.mips, "mips/sentinel"); diff --git a/tests/arch/riscv/correct.test.mts b/tests/arch/riscv/correct.test.mts index d9d47b778..b02890841 100644 --- a/tests/arch/riscv/correct.test.mts +++ b/tests/arch/riscv/correct.test.mts @@ -1,9 +1,9 @@ -import { ARCH, snapshot_tests } from "../arch_utils.mts"; +import { ARCH, execution_tests } from "../arch_utils.mts"; const long_str = "This is a very long string with many characters and a lot of data. :) 123\n"; -snapshot_tests( +execution_tests( ARCH.riscv, "riscv/correct/examples", new Map([ @@ -11,7 +11,7 @@ snapshot_tests( ["test_riscv_example_010.s", [long_str.length + "\n", long_str]], ]), ); -snapshot_tests( +execution_tests( ARCH.riscv, "riscv/correct/syscalls", new Map([ diff --git a/tests/arch/riscv/error.test.mts b/tests/arch/riscv/error.test.mts index f460d6507..e571e7b20 100644 --- a/tests/arch/riscv/error.test.mts +++ b/tests/arch/riscv/error.test.mts @@ -1,11 +1,16 @@ -import { ARCH, snapshot_tests } from "../arch_utils.mts"; +import { ARCH, execution_tests } from "../arch_utils.mts"; -snapshot_tests(ARCH.riscv, "riscv/error/executor", undefined, new Set([ - "test_riscv_error_executor_002.s", - "test_riscv_error_executor_003.s", - "test_riscv_error_executor_004.s", - "test_riscv_error_executor_005.s", - "test_riscv_error_executor_006.s", - "test_riscv_error_executor_007.s", - "test_riscv_error_executor_008.s", -])); +execution_tests( + ARCH.riscv, + "riscv/error/executor", + undefined, + new Set([ + "test_riscv_error_executor_002.s", + "test_riscv_error_executor_003.s", + "test_riscv_error_executor_004.s", + "test_riscv_error_executor_005.s", + "test_riscv_error_executor_006.s", + "test_riscv_error_executor_007.s", + "test_riscv_error_executor_008.s", + ]), +); diff --git a/tests/arch/riscv/instructions.test.mts b/tests/arch/riscv/instructions.test.mts index b8af0fe04..5239ed99d 100644 --- a/tests/arch/riscv/instructions.test.mts +++ b/tests/arch/riscv/instructions.test.mts @@ -1,3 +1,3 @@ -import { ARCH, snapshot_tests } from "../arch_utils.mts" +import { ARCH, execution_tests } from "../arch_utils.mts"; -snapshot_tests(ARCH.riscv, "riscv/instructions"); +execution_tests(ARCH.riscv, "riscv/instructions"); diff --git a/tests/arch/riscv/sentinel.test.mts b/tests/arch/riscv/sentinel.test.mts index 3e145cc39..c8d22d86f 100644 --- a/tests/arch/riscv/sentinel.test.mts +++ b/tests/arch/riscv/sentinel.test.mts @@ -1,3 +1,3 @@ -import { ARCH, snapshot_tests } from "../arch_utils.mts" +import { ARCH, execution_tests } from "../arch_utils.mts"; -snapshot_tests(ARCH.riscv, "riscv/sentinel"); +execution_tests(ARCH.riscv, "riscv/sentinel"); From b595cc6be5acdc52ff5d7e78c627e1dab197c021 Mon Sep 17 00:00:00 2001 From: ALVAROPING1 Date: Wed, 18 Mar 2026 15:36:41 +0100 Subject: [PATCH 36/85] fix(assembler): allow using different color format on different environments Allows the web version to keep using HTML formatting, while CLI can use ANSI escape sequences --- src/core/assembler/assembler.d.ts | 3 +++ src/core/assembler/assembler.mjs | 26 +++++++++++++------ .../creatorAssembler/creatorAssemblerBase.mjs | 26 +++++++++++-------- .../deno/creatorAssembler.mjs | 7 ++--- .../creatorAssembler/web/creatorAssembler.mjs | 2 +- src/core/core.mjs | 15 ++++++++--- tests/unit/arch/simulator-test-utils.mts | 1 + 7 files changed, 53 insertions(+), 27 deletions(-) diff --git a/src/core/assembler/assembler.d.ts b/src/core/assembler/assembler.d.ts index 94c0ccb85..f48b08041 100644 --- a/src/core/assembler/assembler.d.ts +++ b/src/core/assembler/assembler.d.ts @@ -16,3 +16,6 @@ export declare const instructions: Instruction[]; type InstructionTagMap = { [addr: number]: { tag: string; global: boolean } }; export declare let tag_instructions: InstructionTagMap; + +type CompilerFn = (code: string, library: boolean, ansi_color: boolean) + => Promise | object diff --git a/src/core/assembler/assembler.mjs b/src/core/assembler/assembler.mjs index b6021f5ff..c501c99eb 100644 --- a/src/core/assembler/assembler.mjs +++ b/src/core/assembler/assembler.mjs @@ -103,11 +103,20 @@ export function formatErrorWithColors(error) { return htmlMsg; } -export function getCleanErrorMessage(error) { +export function getCleanErrorMessage(error, ansi_color = true) { const errorMsg = String(error); - const parsed = ansicolor.parse(errorMsg); - const cleanMsg = parsed.spans.map(span => span.text).join(""); - return cleanMsg; + if (ansi_color) { + const parsed = ansicolor.parse(errorMsg); + return parsed.spans.map(span => span.text).join(""); + } else { + return errorMsg + .replace(/<.+?>/g, "") + .replace(/&/g, "&") + .replace(/</g, "<") + .replace(/>/g, ">") + .replace(/"/g, '"') + .replace(/'/g, "'"); + } } /** @@ -319,10 +328,11 @@ export function parseDebugSymbols(debugSymbols) { /** * Dispatcher for assembly compilers. * @param {string} code - * @param {any} library - * @param {string} compiler + * @param {boolean} library + * @param {import("./assembler.d.ts").CompilerFn} compiler + * @param {boolean} ansi_color */ -export function assembly_compiler(code, library, compiler) { +export function assembly_compiler(code, library, compiler, ansi_color = false) { // If no compiler is specified, error out if (!compiler) { raise("No compiler specified for assembly compilation"); @@ -333,5 +343,5 @@ export function assembly_compiler(code, library, compiler) { status.executedInstructions = 0; status.clkCycles = 0; - return compiler(code, library); + return compiler(code, library, ansi_color); } diff --git a/src/core/assembler/creatorAssembler/creatorAssemblerBase.mjs b/src/core/assembler/creatorAssembler/creatorAssemblerBase.mjs index 1a185f813..9ec7f0bd9 100644 --- a/src/core/assembler/creatorAssembler/creatorAssemblerBase.mjs +++ b/src/core/assembler/creatorAssembler/creatorAssemblerBase.mjs @@ -63,10 +63,11 @@ let libraryInstructions = []; /** * Handle compilation error * @param {String} error - Error message returned by the assembler + * @param {boolean} ansi_color - Whether errors are formatted with ANSI or HTML colors * @returns {Object} Structured error data */ -function handleError(error) { - const cleanErrorText = error.replace(/<.+?>/g, ""); +function handleError(error, ansi_color) { + const cleanErrorText = getCleanErrorMessage(error, ansi_color); const linterInfo = parseErrorForLinter(cleanErrorText); return { errorcode: "101", @@ -491,9 +492,10 @@ function writeInstructionsToMemory(instructions, library_instructions) { * Compile assembly code as a library * @param {string} code - Assembly code to compile * @param {WasmModules} wasmModules - Assembler's WASM modules + * @param {boolean} ansi_color - Whether to use ANSI or HTML colors (default: HTML) * @returns {Object} Compilation result */ -export function assembleCreatorLibrary(code, wasmModules) { +export function assembleCreatorLibrary(code, wasmModules, ansi_color) { /* Google Analytics */ creator_ga("compile", "compile.library"); @@ -516,7 +518,7 @@ export function assembleCreatorLibrary(code, wasmModules) { 0, // library_offset (not used for library compilation) "{}", // no library labels true, // library flag - Color.Html, + ansi_color? Color.Ansi : Color.Html, ); // Library compilation: only binary instructions @@ -543,7 +545,7 @@ export function assembleCreatorLibrary(code, wasmModules) { const data_mem = compiled.data; loadDataIntoMemory(data_mem, wasmModules); } catch (error) { - return handleError(error) + return handleError(error, ansi_color) } // Mark global labels on library instructions @@ -570,9 +572,10 @@ export function assembleCreatorLibrary(code, wasmModules) { * Compile assembly code as a normal program * @param {string} code - Assembly code to compile * @param {WasmModules} wasmModules - Assembler's WASM modules + * @param {boolean} ansi_color - Whether to use ANSI or HTML colors (default: HTML) * @returns {Object} Compilation result */ -export function assembleCreatorProgram(code, wasmModules) { +export function assembleCreatorProgram(code, wasmModules, ansi_color) { /* Google Analytics */ creator_ga("compile", "compile.assembly"); @@ -601,7 +604,7 @@ export function assembleCreatorProgram(code, wasmModules) { library_offset, labels_json, false, // not a library - Color.Html, + ansi_color? Color.Ansi : Color.Html, ); // Normal compilation: populate instructions for execution/display @@ -628,7 +631,7 @@ export function assembleCreatorProgram(code, wasmModules) { const data_mem = compiled.data; loadDataIntoMemory(data_mem, wasmModules); } catch (error) { - return handleError(error) + return handleError(error, ansi_color) } // Write library binary to memory if present @@ -663,12 +666,13 @@ export function assembleCreatorProgram(code, wasmModules) { * @param {string} code - Assembly code to compile * @param {boolean} library - Whether this is a library compilation * @param {WasmModules} wasmModules - Assembler's WASM modules + * @param {boolean} ansi_color - Whether to use ANSI or HTML colors (default: HTML) * @returns {Object} Compilation result */ -export function assembleCreatorBase(code, library, wasmModules) { +export function assembleCreatorBase(code, library, wasmModules, ansi_color = false) { if (library) { - return assembleCreatorLibrary(code, wasmModules); + return assembleCreatorLibrary(code, wasmModules, ansi_color); } else { - return assembleCreatorProgram(code, wasmModules); + return assembleCreatorProgram(code, wasmModules, ansi_color); } } diff --git a/src/core/assembler/creatorAssembler/deno/creatorAssembler.mjs b/src/core/assembler/creatorAssembler/deno/creatorAssembler.mjs index 62d02d05c..df9ab5991 100644 --- a/src/core/assembler/creatorAssembler/deno/creatorAssembler.mjs +++ b/src/core/assembler/creatorAssembler/deno/creatorAssembler.mjs @@ -22,13 +22,14 @@ import { assembleCreatorBase } from "../creatorAssemblerBase.mjs"; import * as wasmModules from "./wasm/creator_assembler.js"; /** - * Deno-specific assembly compiler that uses ANSI color configuration + * Deno-specific assembly compiler * WASM is automatically initialized in Deno version * @param {string} code - Assembly code to compile * @param {boolean} library - Whether this is a library compilation + * @param {boolean} ansi_color - Whether to use ANSI or HTML colors (default: ANSI) * @returns {Object} Compilation result */ -export function assembleCreator(code, library) { +export function assembleCreator(code, library, ansi_color = true) { // Call the common base implementation - return assembleCreatorBase(code, library, wasmModules); + return assembleCreatorBase(code, library, wasmModules, ansi_color); } diff --git a/src/core/assembler/creatorAssembler/web/creatorAssembler.mjs b/src/core/assembler/creatorAssembler/web/creatorAssembler.mjs index 0eee173ef..bd1dd1d19 100644 --- a/src/core/assembler/creatorAssembler/web/creatorAssembler.mjs +++ b/src/core/assembler/creatorAssembler/web/creatorAssembler.mjs @@ -32,5 +32,5 @@ export async function assembleCreator(code, library) { await wasm_web_init(); // Call the common base implementation - return assembleCreatorBase(code, library, wasmModules); + return assembleCreatorBase(code, library, wasmModules, false); } diff --git a/src/core/core.mjs b/src/core/core.mjs index 2c94cd499..0b8b06137 100644 --- a/src/core/core.mjs +++ b/src/core/core.mjs @@ -307,17 +307,24 @@ export async function load_CREATino() { // compilation -export async function assembly_compile(code, compiler) { +/** + * Compiles an assembly code with the chosen compiler + * @param {string} code + * @param {import("./assembler/assembler.d.ts").CompilerFn} compiler + * @param {boolean} ansi_color - Whether to format errors with ANSI escape sequences + * (`true`) or HTML tags (`false`) + **/ +export async function assembly_compile(code, compiler, ansi_color = false) { var ret; if (architecture.config.name.includes("SRV")){ if (Object.keys(loadedLibrary).length === 0) - ret = await assembly_compiler(code, false, compiler); + ret = await assembly_compiler(code, false, compiler, ansi_color); else - ret = await assembly_compiler(code, true, compiler); + ret = await assembly_compiler(code, true, compiler, ansi_color); } else{ - ret = await assembly_compiler(code, false, compiler); + ret = await assembly_compiler(code, false, compiler, ansi_color); } switch (ret.status) { diff --git a/tests/unit/arch/simulator-test-utils.mts b/tests/unit/arch/simulator-test-utils.mts index 1dd960c0d..8933c2b23 100644 --- a/tests/unit/arch/simulator-test-utils.mts +++ b/tests/unit/arch/simulator-test-utils.mts @@ -162,6 +162,7 @@ export async function compileAssembly( const compileResult = (await creator.assembly_compile( testAssembly, compilerFunction, + true, )) as CompileResult; if (compileResult.status !== "ok") { throw new Error(`Failed to compile assembly: ${compileResult.msg}`); From 0fc4637fa93ede2b490feb06bc65210c1bd31d27 Mon Sep 17 00:00:00 2001 From: ALVAROPING1 Date: Wed, 18 Mar 2026 15:38:02 +0100 Subject: [PATCH 37/85] fix(creator-assembler): fix incorrect display of syntax of pseudoinstructions in errors --- creator-assembler | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/creator-assembler b/creator-assembler index 567859473..0531a2707 160000 --- a/creator-assembler +++ b/creator-assembler @@ -1 +1 @@ -Subproject commit 5678594737724c2fcc8b2d25f324ecd6d4aa3599 +Subproject commit 0531a2707011af39e85d78ffd588d14c73861ffd From 1b7e6f7a109ef0dc3fba0bfe08441565b5f5c8b8 Mon Sep 17 00:00:00 2001 From: ALVAROPING1 Date: Wed, 18 Mar 2026 15:39:28 +0100 Subject: [PATCH 38/85] tests: migration of old compiler error tests --- .../test_mips_error_compiler_001.s.snap | 60 ++++++++++ .../test_mips_error_compiler_002.s.snap | 42 +++++++ .../test_mips_error_compiler_003.s.snap | 108 ++++++++++++++++++ .../test_mips_error_compiler_004.s.snap | 48 ++++++++ .../test_mips_error_compiler_005.s.snap | 48 ++++++++ .../test_mips_error_compiler_006.s.snap | 84 ++++++++++++++ .../test_mips_error_compiler_007.s.snap | 48 ++++++++ .../test_mips_error_compiler_008.s.snap | 48 ++++++++ .../test_mips_error_compiler_009.s.snap | 84 ++++++++++++++ .../test_mips_error_compiler_010.s.snap | 42 +++++++ .../test_mips_error_compiler_014.s.snap | 42 +++++++ .../test_mips_error_compiler_015.s.snap | 42 +++++++ .../test_mips_error_compiler_016.s.snap | 48 ++++++++ .../test_mips_error_compiler_017.s.snap | 48 ++++++++ .../test_mips_error_compiler_018.s.snap | 48 ++++++++ .../test_mips_error_compiler_019.s.snap | 48 ++++++++ .../test_mips_error_compiler_021.s.snap | 42 +++++++ .../test_mips_error_compiler_022.s.snap | 42 +++++++ .../test_mips_error_compiler_023.s.snap | 48 ++++++++ .../test_mips_error_compiler_030.s.snap | 42 +++++++ .../test_riscv_error_compiler_001.s.snap | 60 ++++++++++ .../test_riscv_error_compiler_002.s.snap | 42 +++++++ .../test_riscv_error_compiler_003.s.snap | 84 ++++++++++++++ .../test_riscv_error_compiler_004.s.snap | 48 ++++++++ .../test_riscv_error_compiler_005.s.snap | 48 ++++++++ .../test_riscv_error_compiler_006.s.snap | 84 ++++++++++++++ .../test_riscv_error_compiler_007.s.snap | 48 ++++++++ .../test_riscv_error_compiler_008.s.snap | 66 +++++++++++ .../test_riscv_error_compiler_009.s.snap | 84 ++++++++++++++ .../test_riscv_error_compiler_010.s.snap | 42 +++++++ .../test_riscv_error_compiler_014.s.snap | 42 +++++++ .../test_riscv_error_compiler_015.s.snap | 42 +++++++ .../test_riscv_error_compiler_016.s.snap | 48 ++++++++ .../test_riscv_error_compiler_017.s.snap | 48 ++++++++ .../test_riscv_error_compiler_018.s.snap | 48 ++++++++ .../test_riscv_error_compiler_019.s.snap | 48 ++++++++ .../test_riscv_error_compiler_021.s.snap | 42 +++++++ .../test_riscv_error_compiler_022.s.snap | 42 +++++++ .../test_riscv_error_compiler_023.s.snap | 48 ++++++++ .../test_riscv_error_compiler_030.s.snap | 42 +++++++ tests/arch/arch_utils.mts | 41 +++++++ tests/arch/mips/error.test.mts | 4 +- .../compiler/test_mips_error_compiler_001.out | 19 --- .../compiler/test_mips_error_compiler_002.out | 13 --- .../compiler/test_mips_error_compiler_003.out | 35 ------ .../compiler/test_mips_error_compiler_004.out | 15 --- .../compiler/test_mips_error_compiler_005.out | 15 --- .../compiler/test_mips_error_compiler_006.out | 27 ----- .../compiler/test_mips_error_compiler_007.out | 15 --- .../compiler/test_mips_error_compiler_008.out | 15 --- .../compiler/test_mips_error_compiler_009.out | 27 ----- .../compiler/test_mips_error_compiler_010.s | 4 +- .../compiler/test_mips_error_compiler_014.out | 13 --- .../compiler/test_mips_error_compiler_015.out | 13 --- .../compiler/test_mips_error_compiler_016.out | 15 --- .../compiler/test_mips_error_compiler_017.out | 15 --- .../compiler/test_mips_error_compiler_018.out | 15 --- .../compiler/test_mips_error_compiler_018.s | 3 +- .../compiler/test_mips_error_compiler_019.out | 15 --- .../compiler/test_mips_error_compiler_021.out | 13 --- .../compiler/test_mips_error_compiler_022.out | 13 --- .../compiler/test_mips_error_compiler_023.out | 15 --- .../compiler/test_mips_error_compiler_030.out | 13 --- .../compiler/test_mips_error_compiler_030.s | 8 ++ tests/arch/riscv/error.test.mts | 4 +- .../test_riscv_error_compiler_001.out | 19 --- .../test_riscv_error_compiler_002.out | 13 --- .../test_riscv_error_compiler_003.out | 27 ----- .../test_riscv_error_compiler_004.out | 15 --- .../test_riscv_error_compiler_005.out | 15 --- .../test_riscv_error_compiler_006.out | 27 ----- .../test_riscv_error_compiler_007.out | 15 --- .../test_riscv_error_compiler_008.out | 21 ---- .../test_riscv_error_compiler_009.out | 27 ----- .../compiler/test_riscv_error_compiler_010.s | 4 +- .../test_riscv_error_compiler_014.out | 13 --- .../test_riscv_error_compiler_015.out | 13 --- .../test_riscv_error_compiler_016.out | 15 --- .../test_riscv_error_compiler_017.out | 15 --- .../test_riscv_error_compiler_018.out | 15 --- .../test_riscv_error_compiler_019.out | 15 --- .../test_riscv_error_compiler_021.out | 13 --- .../test_riscv_error_compiler_022.out | 13 --- .../test_riscv_error_compiler_023.out | 15 --- .../test_riscv_error_compiler_030.out | 13 --- .../compiler/test_riscv_error_compiler_030.s | 8 ++ tests/unit/arch/simulator-test-utils.mts | 9 +- 87 files changed, 2191 insertions(+), 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delete mode 100644 tests/arch/riscv/error/compiler/test_riscv_error_compiler_019.out delete mode 100644 tests/arch/riscv/error/compiler/test_riscv_error_compiler_021.out delete mode 100644 tests/arch/riscv/error/compiler/test_riscv_error_compiler_022.out delete mode 100644 tests/arch/riscv/error/compiler/test_riscv_error_compiler_023.out delete mode 100644 tests/arch/riscv/error/compiler/test_riscv_error_compiler_030.out diff --git a/tests/arch/__snapshots__/mips/error/compiler/test_mips_error_compiler_001.s.snap b/tests/arch/__snapshots__/mips/error/compiler/test_mips_error_compiler_001.s.snap new file mode 100644 index 000000000..c5f09d8e6 --- /dev/null +++ b/tests/arch/__snapshots__/mips/error/compiler/test_mips_error_compiler_001.s.snap @@ -0,0 +1,60 @@ +export const snapshot = {}; + +snapshot[`mips/error/compiler/test_mips_error_compiler_001.s 1`] = ` +{ + column: 4, + errorText: "[E12] Error: Label A is already defined", + line: 9, +} +`; + +snapshot[`mips/error/compiler/test_mips_error_compiler_001.s 2`] = ` +"[E12] Error: Label A is already defined + ╭─[ assembly:9:4 ] + │ + 7 │ A: .word -1 + │ ─┬ + │ ╰── Note: Label also defined here + │ + 9 │ A: .half 23 + │ ─┬ + │ ╰── Duplicate label + │ + │ Help: Consider renaming either of the labels +───╯ +" +`; + +snapshot[`mips/error/compiler/test_mips_error_compiler_001.s 3`] = ` +"[E12] Error: Label A is already defined + ╭─[ assembly:9:4 ] + │ + 7 │ A: .word -1 + │ ─┬ + │ ╰── Note: Label also defined here + │ + 9 │ A: .half 23 + │ ─┬ + │ ╰── Duplicate label + │ + │ Help: Consider renaming either of the labels +───╯ +" +`; + +snapshot[`mips/error/compiler/test_mips_error_compiler_001.s 4`] = ` +"[E12] Error: Label A is already defined + ╭─[ assembly:9:4 ] + │ + 7 │    A:    .word -1 +  │ ─┬ +  │ ╰── Note: Label also defined here +  │ + 9 │    A:    .half 23 +  │ ─┬ +  │ ╰── Duplicate label +  │ +  │ Help: Consider renaming either of the labels +───╯ +" +`; diff --git a/tests/arch/__snapshots__/mips/error/compiler/test_mips_error_compiler_002.s.snap b/tests/arch/__snapshots__/mips/error/compiler/test_mips_error_compiler_002.s.snap new file mode 100644 index 000000000..c367c3661 --- /dev/null +++ b/tests/arch/__snapshots__/mips/error/compiler/test_mips_error_compiler_002.s.snap @@ -0,0 +1,42 @@ +export const snapshot = {}; + +snapshot[`mips/error/compiler/test_mips_error_compiler_002.s 1`] = ` +{ + column: 4, + errorText: "[E02] Error: Instruction suma isn't defined", + line: 12, +} +`; + +snapshot[`mips/error/compiler/test_mips_error_compiler_002.s 2`] = ` +"[E02] Error: Instruction suma isn't defined + ╭─[ assembly:12:4 ] + │ + 12 │ suma \$t0, \$t1, \$t2 + │ ──┬─ + │ ╰─── Unknown instruction +────╯ +" +`; + +snapshot[`mips/error/compiler/test_mips_error_compiler_002.s 3`] = ` +"[E02] Error: Instruction suma isn't defined + ╭─[ assembly:12:4 ] + │ + 12 │ suma \$t0, \$t1, \$t2 + │ ──┬─ + │ ╰─── Unknown instruction +────╯ +" +`; + +snapshot[`mips/error/compiler/test_mips_error_compiler_002.s 4`] = ` +"[E02] Error: Instruction suma isn't defined + ╭─[ assembly:12:4 ] + │ + 12 │    suma \$t0, \$t1, \$t2 +  │ ──┬─ +  │ ╰─── Unknown instruction +────╯ +" +`; diff --git a/tests/arch/__snapshots__/mips/error/compiler/test_mips_error_compiler_003.s.snap b/tests/arch/__snapshots__/mips/error/compiler/test_mips_error_compiler_003.s.snap new file mode 100644 index 000000000..56a5ac36a --- /dev/null +++ b/tests/arch/__snapshots__/mips/error/compiler/test_mips_error_compiler_003.s.snap @@ -0,0 +1,108 @@ +export const snapshot = {}; + +snapshot[`mips/error/compiler/test_mips_error_compiler_003.s 1`] = ` +{ + column: 8, + errorText: "[E09] Error: Incorrect instruction syntax", + line: 12, +} +`; + +snapshot[`mips/error/compiler/test_mips_error_compiler_003.s 2`] = ` +"[E09] Error: Incorrect instruction syntax + ╭─[ assembly:12:8 ] + │ + 12 │ add 25, \$t1, 12 + │ ─────┬───── + │ ╰─────── Incorrect syntax + │ + │ Note: Allowed formats: + │ opcode \$rd, \$rt, \$rs + │ opcode \$rs, \$rt, inm +────╯ + +The syntax opcode \$rd, \$rt, \$rs failed with the following reason: +Error: found integer (25) but expected \$ + ╭─[ assembly:12:8 ] + │ + 12 │ add 25, \$t1, 12 + │ ─┬ + │ ╰── Unexpected input +────╯ + +The syntax opcode \$rs, \$rt, inm failed with the following reason: +Error: found integer (25) but expected \$ + ╭─[ assembly:12:8 ] + │ + 12 │ add 25, \$t1, 12 + │ ─┬ + │ ╰── Unexpected input +────╯ +" +`; + +snapshot[`mips/error/compiler/test_mips_error_compiler_003.s 3`] = ` +"[E09] Error: Incorrect instruction syntax + ╭─[ assembly:12:8 ] + │ + 12 │ add 25, \$t1, 12 + │ ─────┬───── + │ ╰─────── Incorrect syntax + │ + │ Note: Allowed formats: + │ opcode \$rd, \$rt, \$rs + │ opcode \$rs, \$rt, inm +────╯ + +The syntax opcode \$rd, \$rt, \$rs failed with the following reason: +Error: found integer (25) but expected \$ + ╭─[ assembly:12:8 ] + │ + 12 │ add 25, \$t1, 12 + │ ─┬ + │ ╰── Unexpected input +────╯ + +The syntax opcode \$rs, \$rt, inm failed with the following reason: +Error: found integer (25) but expected \$ + ╭─[ assembly:12:8 ] + │ + 12 │ add 25, \$t1, 12 + │ ─┬ + │ ╰── Unexpected input +────╯ +" +`; + +snapshot[`mips/error/compiler/test_mips_error_compiler_003.s 4`] = ` +"[E09] Error: Incorrect instruction syntax + ╭─[ assembly:12:8 ] + │ + 12 │    add 25, \$t1, 12 +  │ ─────┬───── +  │ ╰─────── Incorrect syntax +  │ +  │ Note: Allowed formats: +  │ opcode \$rd, \$rt, \$rs +  │ opcode \$rs, \$rt, inm +────╯ + +The syntax opcode \$rd, \$rt, \$rs failed with the following reason: +Error: found integer (25) but expected \$ + ╭─[ assembly:12:8 ] + │ + 12 │    add 25, \$t1, 12 +  │ ─┬ +  │ ╰── Unexpected input +────╯ + +The syntax opcode \$rs, \$rt, inm failed with the following reason: +Error: found integer (25) but expected \$ + ╭─[ assembly:12:8 ] + │ + 12 │    add 25, \$t1, 12 +  │ ─┬ +  │ ╰── Unexpected input +────╯ +" +`; diff --git a/tests/arch/__snapshots__/mips/error/compiler/test_mips_error_compiler_004.s.snap b/tests/arch/__snapshots__/mips/error/compiler/test_mips_error_compiler_004.s.snap new file mode 100644 index 000000000..f9b2e9478 --- /dev/null +++ b/tests/arch/__snapshots__/mips/error/compiler/test_mips_error_compiler_004.s.snap @@ -0,0 +1,48 @@ +export const snapshot = {}; + +snapshot[`mips/error/compiler/test_mips_error_compiler_004.s 1`] = ` +{ + column: 19, + errorText: "[E05] Error: Register s50 isn't defined in file type Integer", + line: 12, +} +`; + +snapshot[`mips/error/compiler/test_mips_error_compiler_004.s 2`] = ` +"[E05] Error: Register s50 isn't defined in file type Integer + ╭─[ assembly:12:19 ] + │ + 12 │ add \$t0, \$t1, \$s50 + │ ─┬─ + │ ╰─── Unknown register + │ + │ Help: Did you mean s0 or s5? +────╯ +" +`; + +snapshot[`mips/error/compiler/test_mips_error_compiler_004.s 3`] = ` +"[E05] Error: Register s50 isn't defined in file type Integer + ╭─[ assembly:12:19 ] + │ + 12 │ add \$t0, \$t1, \$s50 + │ ─┬─ + │ ╰─── Unknown register + │ + │ Help: Did you mean s0 or s5? +────╯ +" +`; + +snapshot[`mips/error/compiler/test_mips_error_compiler_004.s 4`] = ` +"[E05] Error: Register s50 isn't defined in file type Integer + ╭─[ assembly:12:19 ] + │ + 12 │    add \$t0, \$t1, \$s50 +  │ ─┬─ +  │ ╰─── Unknown register +  │ +  │ Help: Did you mean s0 or s5? +────╯ +" +`; diff --git a/tests/arch/__snapshots__/mips/error/compiler/test_mips_error_compiler_005.s.snap b/tests/arch/__snapshots__/mips/error/compiler/test_mips_error_compiler_005.s.snap new file mode 100644 index 000000000..aa4f3f98f --- /dev/null +++ b/tests/arch/__snapshots__/mips/error/compiler/test_mips_error_compiler_005.s.snap @@ -0,0 +1,48 @@ +export const snapshot = {}; + +snapshot[`mips/error/compiler/test_mips_error_compiler_005.s 1`] = ` +{ + column: 19, + errorText: "[E23] Error: Value 291 is outside of the valid range of the field", + line: 7, +} +`; + +snapshot[`mips/error/compiler/test_mips_error_compiler_005.s 2`] = ` +"[E23] Error: Value 291 is outside of the valid range of the field + ╭─[ assembly:7:19 ] + │ + 7 │ a: .byte 0x123 + │ ──┬── + │ ╰──── This expression has value 291 + │ + │ Note: Allowed range is [-128, 255] +───╯ +" +`; + +snapshot[`mips/error/compiler/test_mips_error_compiler_005.s 3`] = ` +"[E23] Error: Value 291 is outside of the valid range of the field + ╭─[ assembly:7:19 ] + │ + 7 │ a: .byte 0x123 + │ ──┬── + │ ╰──── This expression has value 291 + │ + │ Note: Allowed range is [-128, 255] +───╯ +" +`; + +snapshot[`mips/error/compiler/test_mips_error_compiler_005.s 4`] = ` +"[E23] Error: Value 291 is outside of the valid range of the field + ╭─[ assembly:7:19 ] + │ + 7 │     a:      .byte 0x123 +  │ ──┬── +  │ ╰──── This expression has value 291 +  │ +  │ Note: Allowed range is [-128, 255] +───╯ +" +`; diff --git a/tests/arch/__snapshots__/mips/error/compiler/test_mips_error_compiler_006.s.snap b/tests/arch/__snapshots__/mips/error/compiler/test_mips_error_compiler_006.s.snap new file mode 100644 index 000000000..3dd5704d3 --- /dev/null +++ b/tests/arch/__snapshots__/mips/error/compiler/test_mips_error_compiler_006.s.snap @@ -0,0 +1,84 @@ +export const snapshot = {}; + +snapshot[`mips/error/compiler/test_mips_error_compiler_006.s 1`] = ` +{ + column: 7, + errorText: "[E09] Error: Incorrect instruction syntax", + line: 11, +} +`; + +snapshot[`mips/error/compiler/test_mips_error_compiler_006.s 2`] = ` +"[E09] Error: Incorrect instruction syntax + ╭─[ assembly:11:7 ] + │ + 11 │ li \$t0, 0xhello + │ ──────┬───── + │ ╰─────── Incorrect syntax + │ + │ Note: Allowed formats: + │ opcode \$rd, val +────╯ + +The syntax opcode \$rd, val failed with the following reason: +Error: found identifier (xhello) but expected binary operator or end of input + ╭─[ assembly:11:13 ] + │ + 11 │ li \$t0, 0xhello + │ ┬───┬── + │ ╰──────── While parsing this expression + │ │ + │ ╰──── Unexpected input +────╯ +" +`; + +snapshot[`mips/error/compiler/test_mips_error_compiler_006.s 3`] = ` +"[E09] Error: Incorrect instruction syntax + ╭─[ assembly:11:7 ] + │ + 11 │ li \$t0, 0xhello + │ ──────┬───── + │ ╰─────── Incorrect syntax + │ + │ Note: Allowed formats: + │ opcode \$rd, val +────╯ + +The syntax opcode \$rd, val failed with the following reason: +Error: found identifier (xhello) but expected binary operator or end of input + ╭─[ assembly:11:13 ] + │ + 11 │ li \$t0, 0xhello + │ ┬───┬── + │ ╰──────── While parsing this expression + │ │ + │ ╰──── Unexpected input +────╯ +" +`; + +snapshot[`mips/error/compiler/test_mips_error_compiler_006.s 4`] = ` +"[E09] Error: Incorrect instruction syntax + ╭─[ assembly:11:7 ] + │ + 11 │    li \$t0, 0xhello +  │ ──────┬───── +  │ ╰─────── Incorrect syntax +  │ +  │ Note: Allowed formats: +  │ opcode \$rd, val +────╯ + +The syntax opcode \$rd, val failed with the following reason: +Error: found identifier (xhello) but expected binary operator or end of input + ╭─[ assembly:11:13 ] + │ + 11 │    li \$t0, 0xhello +  │ ┬───┬── +  │ ╰──────── While parsing this expression +  │ │ +  │ ╰──── Unexpected input +────╯ +" +`; diff --git a/tests/arch/__snapshots__/mips/error/compiler/test_mips_error_compiler_007.s.snap b/tests/arch/__snapshots__/mips/error/compiler/test_mips_error_compiler_007.s.snap new file mode 100644 index 000000000..b1d9d4502 --- /dev/null +++ b/tests/arch/__snapshots__/mips/error/compiler/test_mips_error_compiler_007.s.snap @@ -0,0 +1,48 @@ +export const snapshot = {}; + +snapshot[`mips/error/compiler/test_mips_error_compiler_007.s 1`] = ` +{ + column: 7, + errorText: "[E03] Error: Label mains isn't defined", + line: 11, +} +`; + +snapshot[`mips/error/compiler/test_mips_error_compiler_007.s 2`] = ` +"[E03] Error: Label mains isn't defined + ╭─[ assembly:11:7 ] + │ + 11 │ j mains + │ ──┬── + │ ╰──── Unknown label + │ + │ Help: Did you mean main? +────╯ +" +`; + +snapshot[`mips/error/compiler/test_mips_error_compiler_007.s 3`] = ` +"[E03] Error: Label mains isn't defined + ╭─[ assembly:11:7 ] + │ + 11 │ j mains + │ ──┬── + │ ╰──── Unknown label + │ + │ Help: Did you mean main? +────╯ +" +`; + +snapshot[`mips/error/compiler/test_mips_error_compiler_007.s 4`] = ` +"[E03] Error: Label mains isn't defined + ╭─[ assembly:11:7 ] + │ + 11 │     j mains +  │ ──┬── +  │ ╰──── Unknown label +  │ +  │ Help: Did you mean main? +────╯ +" +`; diff --git a/tests/arch/__snapshots__/mips/error/compiler/test_mips_error_compiler_008.s.snap b/tests/arch/__snapshots__/mips/error/compiler/test_mips_error_compiler_008.s.snap new file mode 100644 index 000000000..f5c44bc87 --- /dev/null +++ b/tests/arch/__snapshots__/mips/error/compiler/test_mips_error_compiler_008.s.snap @@ -0,0 +1,48 @@ +export const snapshot = {}; + +snapshot[`mips/error/compiler/test_mips_error_compiler_008.s 1`] = ` +{ + column: 6, + errorText: "[E23] Error: Value 305419896 is outside of the valid range of the field", + line: 8, +} +`; + +snapshot[`mips/error/compiler/test_mips_error_compiler_008.s 2`] = ` +"[E23] Error: Value 305419896 is outside of the valid range of the field + ╭─[ assembly:8:6 ] + │ + 8 │ j 0x12345678 + │ ─────┬──── + │ ╰────── This expression has value 305419896 + │ + │ Note: Allowed range is [-33554432, 33554431] +───╯ +" +`; + +snapshot[`mips/error/compiler/test_mips_error_compiler_008.s 3`] = ` +"[E23] Error: Value 305419896 is outside of the valid range of the field + ╭─[ assembly:8:6 ] + │ + 8 │ j 0x12345678 + │ ─────┬──── + │ ╰────── This expression has value 305419896 + │ + │ Note: Allowed range is [-33554432, 33554431] +───╯ +" +`; + +snapshot[`mips/error/compiler/test_mips_error_compiler_008.s 4`] = ` +"[E23] Error: Value 305419896 is outside of the valid range of the field + ╭─[ assembly:8:6 ] + │ + 8 │    j 0x12345678 +  │ ─────┬──── +  │ ╰────── This expression has value 305419896 +  │ +  │ Note: Allowed range is [-33554432, 33554431] +───╯ +" +`; diff --git a/tests/arch/__snapshots__/mips/error/compiler/test_mips_error_compiler_009.s.snap b/tests/arch/__snapshots__/mips/error/compiler/test_mips_error_compiler_009.s.snap new file mode 100644 index 000000000..323daf058 --- /dev/null +++ b/tests/arch/__snapshots__/mips/error/compiler/test_mips_error_compiler_009.s.snap @@ -0,0 +1,84 @@ +export const snapshot = {}; + +snapshot[`mips/error/compiler/test_mips_error_compiler_009.s 1`] = ` +{ + column: 6, + errorText: "[E09] Error: Incorrect instruction syntax", + line: 8, +} +`; + +snapshot[`mips/error/compiler/test_mips_error_compiler_009.s 2`] = ` +"[E09] Error: Incorrect instruction syntax + ╭─[ assembly:8:6 ] + │ + 8 │ j 0xhello + │ ───┬─── + │ ╰───── Incorrect syntax + │ + │ Note: Allowed formats: + │ opcode addr +───╯ + +The syntax opcode addr failed with the following reason: +Error: found identifier (xhello) but expected binary operator or end of input + ╭─[ assembly:8:7 ] + │ + 8 │ j 0xhello + │ ┬───┬── + │ ╰──────── While parsing this expression + │ │ + │ ╰──── Unexpected input +───╯ +" +`; + +snapshot[`mips/error/compiler/test_mips_error_compiler_009.s 3`] = ` +"[E09] Error: Incorrect instruction syntax + ╭─[ assembly:8:6 ] + │ + 8 │ j 0xhello + │ ───┬─── + │ ╰───── Incorrect syntax + │ + │ Note: Allowed formats: + │ opcode addr +───╯ + +The syntax opcode addr failed with the following reason: +Error: found identifier (xhello) but expected binary operator or end of input + ╭─[ assembly:8:7 ] + │ + 8 │ j 0xhello + │ ┬───┬── + │ ╰──────── While parsing this expression + │ │ + │ ╰──── Unexpected input +───╯ +" +`; + +snapshot[`mips/error/compiler/test_mips_error_compiler_009.s 4`] = ` +"[E09] Error: Incorrect instruction syntax + ╭─[ assembly:8:6 ] + │ + 8 │    j 0xhello +  │ ───┬─── +  │ ╰───── Incorrect syntax +  │ +  │ Note: Allowed formats: +  │ opcode addr +───╯ + +The syntax opcode addr failed with the following reason: +Error: found identifier (xhello) but expected binary operator or end of input + ╭─[ assembly:8:7 ] + │ + 8 │    j 0xhello +  │ ┬───┬── +  │ ╰──────── While parsing this expression +  │ │ +  │ ╰──── Unexpected input +───╯ +" +`; diff --git a/tests/arch/__snapshots__/mips/error/compiler/test_mips_error_compiler_010.s.snap b/tests/arch/__snapshots__/mips/error/compiler/test_mips_error_compiler_010.s.snap new file mode 100644 index 000000000..7487173b4 --- /dev/null +++ b/tests/arch/__snapshots__/mips/error/compiler/test_mips_error_compiler_010.s.snap @@ -0,0 +1,42 @@ +export const snapshot = {}; + +snapshot[`mips/error/compiler/test_mips_error_compiler_010.s 1`] = ` +{ + column: 17, + errorText: "[E16] Error: Data memory segment is full", + line: 8, +} +`; + +snapshot[`mips/error/compiler/test_mips_error_compiler_010.s 2`] = ` +"[E16] Error: Data memory segment is full + ╭─[ assembly:8:17 ] + │ + 8 │ spa: .space 16 * 1024 * 1024 * 1024 + │ ───────────┬─────────── + │ ╰───────────── This element doesn't fit in the available space +───╯ +" +`; + +snapshot[`mips/error/compiler/test_mips_error_compiler_010.s 3`] = ` +"[E16] Error: Data memory segment is full + ╭─[ assembly:8:17 ] + │ + 8 │ spa: .space 16 * 1024 * 1024 * 1024 + │ ───────────┬─────────── + │ ╰───────────── This element doesn't fit in the available space +───╯ +" +`; + +snapshot[`mips/error/compiler/test_mips_error_compiler_010.s 4`] = ` +"[E16] Error: Data memory segment is full + ╭─[ assembly:8:17 ] + │ + 8 │     spa:    .space 16 * 1024 * 1024 * 1024 +  │ ───────────┬─────────── +  │ ╰───────────── This element doesn't fit in the available space +───╯ +" +`; diff --git a/tests/arch/__snapshots__/mips/error/compiler/test_mips_error_compiler_014.s.snap b/tests/arch/__snapshots__/mips/error/compiler/test_mips_error_compiler_014.s.snap new file mode 100644 index 000000000..55c049f65 --- /dev/null +++ b/tests/arch/__snapshots__/mips/error/compiler/test_mips_error_compiler_014.s.snap @@ -0,0 +1,42 @@ +export const snapshot = {}; + +snapshot[`mips/error/compiler/test_mips_error_compiler_014.s 1`] = ` +{ + column: 14, + errorText: "[E01] Error: Directive .directive isn't defined", + line: 8, +} +`; + +snapshot[`mips/error/compiler/test_mips_error_compiler_014.s 2`] = ` +"[E01] Error: Directive .directive isn't defined + ╭─[ assembly:8:14 ] + │ + 8 │ example: .directive 221 + │ ─────┬──── + │ ╰────── Unknown directive +───╯ +" +`; + +snapshot[`mips/error/compiler/test_mips_error_compiler_014.s 3`] = ` +"[E01] Error: Directive .directive isn't defined + ╭─[ assembly:8:14 ] + │ + 8 │ example: .directive 221 + │ ─────┬──── + │ ╰────── Unknown directive +───╯ +" +`; + +snapshot[`mips/error/compiler/test_mips_error_compiler_014.s 4`] = ` +"[E01] Error: Directive .directive isn't defined + ╭─[ assembly:8:14 ] + │ + 8 │     example:    .directive 221 +  │ ─────┬──── +  │ ╰────── Unknown directive +───╯ +" +`; diff --git a/tests/arch/__snapshots__/mips/error/compiler/test_mips_error_compiler_015.s.snap b/tests/arch/__snapshots__/mips/error/compiler/test_mips_error_compiler_015.s.snap new file mode 100644 index 000000000..3607075e8 --- /dev/null +++ b/tests/arch/__snapshots__/mips/error/compiler/test_mips_error_compiler_015.s.snap @@ -0,0 +1,42 @@ +export const snapshot = {}; + +snapshot[`mips/error/compiler/test_mips_error_compiler_015.s 1`] = ` +{ + column: 22, + errorText: "[E03] Error: Label hello isn't defined", + line: 8, +} +`; + +snapshot[`mips/error/compiler/test_mips_error_compiler_015.s 2`] = ` +"[E03] Error: Label hello isn't defined + ╭─[ assembly:8:22 ] + │ + 8 │ example: .word hello + │ ──┬── + │ ╰──── Unknown label +───╯ +" +`; + +snapshot[`mips/error/compiler/test_mips_error_compiler_015.s 3`] = ` +"[E03] Error: Label hello isn't defined + ╭─[ assembly:8:22 ] + │ + 8 │ example: .word hello + │ ──┬── + │ ╰──── Unknown label +───╯ +" +`; + +snapshot[`mips/error/compiler/test_mips_error_compiler_015.s 4`] = ` +"[E03] Error: Label hello isn't defined + ╭─[ assembly:8:22 ] + │ + 8 │     example:[38;5;249m   .word hello +  │ ──┬── +  │ ╰──── Unknown label +───╯ +" +`; diff --git a/tests/arch/__snapshots__/mips/error/compiler/test_mips_error_compiler_016.s.snap b/tests/arch/__snapshots__/mips/error/compiler/test_mips_error_compiler_016.s.snap new file mode 100644 index 000000000..9f9d44ae0 --- /dev/null +++ b/tests/arch/__snapshots__/mips/error/compiler/test_mips_error_compiler_016.s.snap @@ -0,0 +1,48 @@ +export const snapshot = {}; + +snapshot[`mips/error/compiler/test_mips_error_compiler_016.s 1`] = ` +{ + column: 32, + errorText: "Compilation error", + line: 8, +} +`; + +snapshot[`mips/error/compiler/test_mips_error_compiler_016.s 2`] = ` +'Error: Unterminated string literal + ╭─[ assembly:8:32 ] + │ + 8 │ example: .ascii hello world" + │ ───┬─┬ + │ ╰──── While parsing this identifier + │ │ + │ ╰── Caused by this +───╯ +' +`; + +snapshot[`mips/error/compiler/test_mips_error_compiler_016.s 3`] = ` +"Error: Unterminated string literal + ╭─[ assembly:8:32 ] + │ + 8 │ example: .ascii hello world" + │ ───┬─┬ + │ ╰──── While parsing this identifier + │ │ + │ ╰── Caused by this +───╯ +" +`; + +snapshot[`mips/error/compiler/test_mips_error_compiler_016.s 4`] = ` +'Error: Unterminated string literal + ╭─[ assembly:8:32 ] + │ + 8 │     example:    .ascii hello world" +  │ ───┬─┬ +  │ ╰──── While parsing this identifier +  │ │ +  │ ╰── Caused by this +───╯ +' +`; diff --git a/tests/arch/__snapshots__/mips/error/compiler/test_mips_error_compiler_017.s.snap b/tests/arch/__snapshots__/mips/error/compiler/test_mips_error_compiler_017.s.snap new file mode 100644 index 000000000..649ff19cd --- /dev/null +++ b/tests/arch/__snapshots__/mips/error/compiler/test_mips_error_compiler_017.s.snap @@ -0,0 +1,48 @@ +export const snapshot = {}; + +snapshot[`mips/error/compiler/test_mips_error_compiler_017.s 1`] = ` +{ + column: 33, + errorText: "Compilation error", + line: 8, +} +`; + +snapshot[`mips/error/compiler/test_mips_error_compiler_017.s 2`] = ` +'Error: Unterminated string literal + ╭─[ assembly:8:33 ] + │ + 8 │ example: .ascii "hello world + │ ──────┬─────┬ + │ ╰──────── While parsing this string + │ │ + │ ╰── Caused by this +───╯ +' +`; + +snapshot[`mips/error/compiler/test_mips_error_compiler_017.s 3`] = ` +"Error: Unterminated string literal + ╭─[ assembly:8:33 ] + │ + 8 │ example: .ascii "hello world + │ ──────┬─────┬ + │ ╰──────── While parsing this string + │ │ + │ ╰── Caused by this +───╯ +" +`; + +snapshot[`mips/error/compiler/test_mips_error_compiler_017.s 4`] = ` +'Error: Unterminated string literal + ╭─[ assembly:8:33 ] + │ + 8 │     example:    .ascii "hello world +  │ ──────┬─────┬ +  │ ╰──────── While parsing this string +  │ │ +  │ ╰── Caused by this +───╯ +' +`; diff --git a/tests/arch/__snapshots__/mips/error/compiler/test_mips_error_compiler_018.s.snap b/tests/arch/__snapshots__/mips/error/compiler/test_mips_error_compiler_018.s.snap new file mode 100644 index 000000000..139d3c109 --- /dev/null +++ b/tests/arch/__snapshots__/mips/error/compiler/test_mips_error_compiler_018.s.snap @@ -0,0 +1,48 @@ +export const snapshot = {}; + +snapshot[`mips/error/compiler/test_mips_error_compiler_018.s 1`] = ` +{ + column: 20, + errorText: "[E23] Error: Value 74565 is outside of the valid range of the field", + line: 7, +} +`; + +snapshot[`mips/error/compiler/test_mips_error_compiler_018.s 2`] = ` +"[E23] Error: Value 74565 is outside of the valid range of the field + ╭─[ assembly:7:20 ] + │ + 7 │ example: .half 0x12345 + │ ───┬─── + │ ╰───── This expression has value 74565 + │ + │ Note: Allowed range is [-32768, 65535] +───╯ +" +`; + +snapshot[`mips/error/compiler/test_mips_error_compiler_018.s 3`] = ` +"[E23] Error: Value 74565 is outside of the valid range of the field + ╭─[ assembly:7:20 ] + │ + 7 │ example: .half 0x12345 + │ ───┬─── + │ ╰───── This expression has value 74565 + │ + │ Note: Allowed range is [-32768, 65535] +───╯ +" +`; + +snapshot[`mips/error/compiler/test_mips_error_compiler_018.s 4`] = ` +"[E23] Error: Value 74565 is outside of the valid range of the field + ╭─[ assembly:7:20 ] + │ + 7 │   example:   .half 0x12345 +  │ ───┬─── +  │ ╰───── This expression has value 74565 +  │ +  │ Note: Allowed range is [-32768, 65535] +───╯ +" +`; diff --git a/tests/arch/__snapshots__/mips/error/compiler/test_mips_error_compiler_019.s.snap b/tests/arch/__snapshots__/mips/error/compiler/test_mips_error_compiler_019.s.snap new file mode 100644 index 000000000..136f4cce4 --- /dev/null +++ b/tests/arch/__snapshots__/mips/error/compiler/test_mips_error_compiler_019.s.snap @@ -0,0 +1,48 @@ +export const snapshot = {}; + +snapshot[`mips/error/compiler/test_mips_error_compiler_019.s 1`] = ` +{ + column: 12, + errorText: "Compilation error", + line: 7, +} +`; + +snapshot[`mips/error/compiler/test_mips_error_compiler_019.s 2`] = ` +"Error: found identifier (x) but expected ,, \\\\n, binary operator, or end of input + ╭─[ assembly:7:12 ] + │ + 7 │ .byte 0x + │ ┬┬ + │ ╰─── While parsing this expression + │ │ + │ ╰── Unexpected input +───╯ +" +`; + +snapshot[`mips/error/compiler/test_mips_error_compiler_019.s 3`] = ` +"Error: found identifier (x) but expected ,, \\\\n, binary operator, or end of input + ╭─[ assembly:7:12 ] + │ + 7 │ .byte 0x + │ ┬┬ + │ ╰─── While parsing this expression + │ │ + │ ╰── Unexpected input +───╯ +" +`; + +snapshot[`mips/error/compiler/test_mips_error_compiler_019.s 4`] = ` +"Error: found identifier (x) but expected ,, \\\\n, binary operator, or end of input + ╭─[ assembly:7:12 ] + │ + 7 │     .byte 0x +  │ ┬┬ +  │ ╰─── While parsing this expression +  │ │ +  │ ╰── Unexpected input +───╯ +" +`; diff --git a/tests/arch/__snapshots__/mips/error/compiler/test_mips_error_compiler_021.s.snap b/tests/arch/__snapshots__/mips/error/compiler/test_mips_error_compiler_021.s.snap new file mode 100644 index 000000000..a96c36841 --- /dev/null +++ b/tests/arch/__snapshots__/mips/error/compiler/test_mips_error_compiler_021.s.snap @@ -0,0 +1,42 @@ +export const snapshot = {}; + +snapshot[`mips/error/compiler/test_mips_error_compiler_021.s 1`] = ` +{ + column: 21, + errorText: "[E17] Error: Data at address 0x200001 isn't aligned to size 2 nor word size 4", + line: 9, +} +`; + +snapshot[`mips/error/compiler/test_mips_error_compiler_021.s 2`] = ` +"[E17] Error: Data at address 0x200001 isn't aligned to size 2 nor word size 4 + ╭─[ assembly:9:21 ] + │ + 9 │ example2: .half 2 + │ ┬ + │ ╰── This value isn't aligned +───╯ +" +`; + +snapshot[`mips/error/compiler/test_mips_error_compiler_021.s 3`] = ` +"[E17] Error: Data at address 0x200001 isn't aligned to size 2 nor word size 4 + ╭─[ assembly:9:21 ] + │ + 9 │ example2: .half 2 + │ ┬ + │ ╰── This value isn't aligned +───╯ +" +`; + +snapshot[`mips/error/compiler/test_mips_error_compiler_021.s 4`] = ` +"[E17] Error: Data at address 0x200001 isn't aligned to size 2 nor word size 4 + ╭─[ assembly:9:21 ] + │ + 9 │     example2:   .half 2 +  │ ┬ +  │ ╰── This value isn't aligned +───╯ +" +`; diff --git a/tests/arch/__snapshots__/mips/error/compiler/test_mips_error_compiler_022.s.snap b/tests/arch/__snapshots__/mips/error/compiler/test_mips_error_compiler_022.s.snap new file mode 100644 index 000000000..6b9f731eb --- /dev/null +++ b/tests/arch/__snapshots__/mips/error/compiler/test_mips_error_compiler_022.s.snap @@ -0,0 +1,42 @@ +export const snapshot = {}; + +snapshot[`mips/error/compiler/test_mips_error_compiler_022.s 1`] = ` +{ + column: 12, + errorText: "[E22] Error: Negative values aren't allowed here", + line: 7, +} +`; + +snapshot[`mips/error/compiler/test_mips_error_compiler_022.s 2`] = ` +"[E22] Error: Negative values aren't allowed here + ╭─[ assembly:7:12 ] + │ + 7 │ .space -10 + │ ─┬─ + │ ╰─── This expression has value -10 +───╯ +" +`; + +snapshot[`mips/error/compiler/test_mips_error_compiler_022.s 3`] = ` +"[E22] Error: Negative values aren't allowed here + ╭─[ assembly:7:12 ] + │ + 7 │ .space -10 + │ ─┬─ + │ ╰─── This expression has value -10 +───╯ +" +`; + +snapshot[`mips/error/compiler/test_mips_error_compiler_022.s 4`] = ` +"[E22] Error: Negative values aren't allowed here + ╭─[ assembly:7:12 ] + │ + 7 │     .space -10 +  │ ─┬─ +  │ ╰─── This expression has value -10 +───╯ +" +`; diff --git a/tests/arch/__snapshots__/mips/error/compiler/test_mips_error_compiler_023.s.snap b/tests/arch/__snapshots__/mips/error/compiler/test_mips_error_compiler_023.s.snap new file mode 100644 index 000000000..06a04eb48 --- /dev/null +++ b/tests/arch/__snapshots__/mips/error/compiler/test_mips_error_compiler_023.s.snap @@ -0,0 +1,48 @@ +export const snapshot = {}; + +snapshot[`mips/error/compiler/test_mips_error_compiler_023.s 1`] = ` +{ + column: 20, + errorText: "[E10] Error: Incorrect amount of arguments, expected at least 1 but found 0", + line: 9, +} +`; + +snapshot[`mips/error/compiler/test_mips_error_compiler_023.s 2`] = ` +"[E10] Error: Incorrect amount of arguments, expected at least 1 but found 0 + ╭─[ assembly:9:20 ] + │ + 9 │ example2: .half + │ │ + │ ╰─ This directive has 0 arguments + │ + │ Help: Consider adding the missing 1 argument +───╯ +" +`; + +snapshot[`mips/error/compiler/test_mips_error_compiler_023.s 3`] = ` +"[E10] Error: Incorrect amount of arguments, expected at least 1 but found 0 + ╭─[ assembly:9:20 ] + │ + 9 │ example2: .half + │ │ + │ ╰─ This directive has 0 arguments + │ + │ Help: Consider adding the missing 1 argument +───╯ +" +`; + +snapshot[`mips/error/compiler/test_mips_error_compiler_023.s 4`] = ` +"[E10] Error: Incorrect amount of arguments, expected at least 1 but found 0 + ╭─[ assembly:9:20 ] + │ + 9 │    example2:    .half +  │ │ +  │ ╰─ This directive has 0 arguments +  │ +  │ Help: Consider adding the missing 1 argument +───╯ +" +`; diff --git a/tests/arch/__snapshots__/mips/error/compiler/test_mips_error_compiler_030.s.snap b/tests/arch/__snapshots__/mips/error/compiler/test_mips_error_compiler_030.s.snap new file mode 100644 index 000000000..9a27e8733 --- /dev/null +++ b/tests/arch/__snapshots__/mips/error/compiler/test_mips_error_compiler_030.s.snap @@ -0,0 +1,42 @@ +export const snapshot = {}; + +snapshot[`mips/error/compiler/test_mips_error_compiler_030.s 1`] = ` +{ + column: 15, + errorText: "[E13] Error: Main label main not found", + line: 8, +} +`; + +snapshot[`mips/error/compiler/test_mips_error_compiler_030.s 2`] = ` +"[E13] Error: Main label main not found + ╭─[ assembly:8:15 ] + │ + 8 │ li \$t0, 10 + │ │ + │ ╰─ Consider adding a label called main to an instruction +───╯ +" +`; + +snapshot[`mips/error/compiler/test_mips_error_compiler_030.s 3`] = ` +"[E13] Error: Main label main not found + ╭─[ assembly:8:15 ] + │ + 8 │ li \$t0, 10 + │ │ + │ ╰─ Consider adding a label called main to an instruction +───╯ +" +`; + +snapshot[`mips/error/compiler/test_mips_error_compiler_030.s 4`] = ` +"[E13] Error: Main label main not found + ╭─[ assembly:8:15 ] + │ + 8 │     li \$t0, 10 +  │ │ +  │ ╰─ Consider adding a label called main to an instruction +───╯ +" +`; diff --git a/tests/arch/__snapshots__/riscv/error/compiler/test_riscv_error_compiler_001.s.snap b/tests/arch/__snapshots__/riscv/error/compiler/test_riscv_error_compiler_001.s.snap new file mode 100644 index 000000000..9aa54d348 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/error/compiler/test_riscv_error_compiler_001.s.snap @@ -0,0 +1,60 @@ +export const snapshot = {}; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_001.s 1`] = ` +{ + column: 2, + errorText: "[E12] Error: Label A is already defined", + line: 9, +} +`; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_001.s 2`] = ` +"[E12] Error: Label A is already defined + ╭─[ assembly:9:2 ] + │ + 7 │ A: .word -1 + │ ─┬ + │ ╰─────── Note: Label also defined here + │ + 9 │ A: .half 23 + │ ─┬ + │ ╰───── Duplicate label + │ + │ Help: Consider renaming either of the labels +───╯ +" +`; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_001.s 3`] = ` +"[E12] Error: Label A is already defined + ╭─[ assembly:9:2 ] + │ + 7 │ A: .word -1 + │ ─┬ + │ ╰─────── Note: Label also defined here + │ + 9 │ A: .half 23 + │ ─┬ + │ ╰───── Duplicate label + │ + │ Help: Consider renaming either of the labels +───╯ +" +`; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_001.s 4`] = ` +"[E12] Error: Label A is already defined + ╭─[ assembly:9:2 ] + │ + 7 │     A:       .word -1 +  │ ─┬ +  │ ╰─────── Note: Label also defined here +  │ + 9 │     A:     .half 23 +  │ ─┬ +  │ ╰───── Duplicate label +  │ +  │ Help: Consider renaming either of the labels +───╯ +" +`; diff --git a/tests/arch/__snapshots__/riscv/error/compiler/test_riscv_error_compiler_002.s.snap b/tests/arch/__snapshots__/riscv/error/compiler/test_riscv_error_compiler_002.s.snap new file mode 100644 index 000000000..8e0d31393 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/error/compiler/test_riscv_error_compiler_002.s.snap @@ -0,0 +1,42 @@ +export const snapshot = {}; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_002.s 1`] = ` +{ + column: 2, + errorText: "[E02] Error: Instruction suma isn't defined", + line: 12, +} +`; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_002.s 2`] = ` +"[E02] Error: Instruction suma isn't defined + ╭─[ assembly:12:2 ] + │ + 12 │ suma t0, t1, t2 + │ ──┬─ + │ ╰─── Unknown instruction +────╯ +" +`; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_002.s 3`] = ` +"[E02] Error: Instruction suma isn't defined + ╭─[ assembly:12:2 ] + │ + 12 │ suma t0, t1, t2 + │ ──┬─ + │ ╰─── Unknown instruction +────╯ +" +`; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_002.s 4`] = ` +"[E02] Error: Instruction suma isn't defined + ╭─[ assembly:12:2 ] + │ + 12 │     suma t0, t1, t2 +  │ ──┬─ +  │ ╰─── Unknown instruction +────╯ +" +`; diff --git a/tests/arch/__snapshots__/riscv/error/compiler/test_riscv_error_compiler_003.s.snap b/tests/arch/__snapshots__/riscv/error/compiler/test_riscv_error_compiler_003.s.snap new file mode 100644 index 000000000..96174480e --- /dev/null +++ b/tests/arch/__snapshots__/riscv/error/compiler/test_riscv_error_compiler_003.s.snap @@ -0,0 +1,84 @@ +export const snapshot = {}; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_003.s 1`] = ` +{ + column: 8, + errorText: "[E09] Error: Incorrect instruction syntax", + line: 12, +} +`; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_003.s 2`] = ` +"[E09] Error: Incorrect instruction syntax + ╭─[ assembly:12:8 ] + │ + 12 │ add t0, t1 + │ ───┬── + │ ╰──── Incorrect syntax + │ + │ Note: Allowed formats: + │ opcode rd, rs1, rs2 +────╯ + +The syntax opcode rd, rs1, rs2 failed with the following reason: +Error: found end of input but expected , or binary operator + ╭─[ assembly:12:14 ] + │ + 12 │ add t0, t1 + │ ─┬│ + │ ╰── While parsing this expression + │ │ + │ ╰─ Unexpected input +────╯ +" +`; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_003.s 3`] = ` +"[E09] Error: Incorrect instruction syntax + ╭─[ assembly:12:8 ] + │ + 12 │ add t0, t1 + │ ───┬── + │ ╰──── Incorrect syntax + │ + │ Note: Allowed formats: + │ opcode rd, rs1, rs2 +────╯ + +The syntax opcode rd, rs1, rs2 failed with the following reason: +Error: found end of input but expected , or binary operator + ╭─[ assembly:12:14 ] + │ + 12 │ add t0, t1 + │ ─┬│ + │ ╰── While parsing this expression + │ │ + │ ╰─ Unexpected input +────╯ +" +`; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_003.s 4`] = ` +"[E09] Error: Incorrect instruction syntax + ╭─[ assembly:12:8 ] + │ + 12 │    add t0, t1 +  │ ───┬── +  │ ╰──── Incorrect syntax +  │ +  │ Note: Allowed formats: +  │ opcode rd, rs1, rs2 +────╯ + +The syntax opcode rd, rs1, rs2 failed with the following reason: +Error: found end of input but expected , or binary operator + ╭─[ assembly:12:14 ] + │ + 12 │    add t0, t1 +  │ ─┬│ +  │ ╰── While parsing this expression +  │ │ +  │ ╰─ Unexpected input +────╯ +" +`; diff --git a/tests/arch/__snapshots__/riscv/error/compiler/test_riscv_error_compiler_004.s.snap b/tests/arch/__snapshots__/riscv/error/compiler/test_riscv_error_compiler_004.s.snap new file mode 100644 index 000000000..156e4eb2a --- /dev/null +++ b/tests/arch/__snapshots__/riscv/error/compiler/test_riscv_error_compiler_004.s.snap @@ -0,0 +1,48 @@ +export const snapshot = {}; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_004.s 1`] = ` +{ + column: 14, + errorText: "[E05] Error: Register s50 isn't defined in file type Integer", + line: 12, +} +`; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_004.s 2`] = ` +"[E05] Error: Register s50 isn't defined in file type Integer + ╭─[ assembly:12:14 ] + │ + 12 │ add t0, t1, s50 + │ ─┬─ + │ ╰─── Unknown register + │ + │ Help: Did you mean s0, s10, or s5? +────╯ +" +`; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_004.s 3`] = ` +"[E05] Error: Register s50 isn't defined in file type Integer + ╭─[ assembly:12:14 ] + │ + 12 │ add t0, t1, s50 + │ ─┬─ + │ ╰─── Unknown register + │ + │ Help: Did you mean s0, s10, or s5? +────╯ +" +`; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_004.s 4`] = ` +"[E05] Error: Register s50 isn't defined in file type Integer + ╭─[ assembly:12:14 ] + │ + 12 │     add t0, t1, s50 +  │ ─┬─ +  │ ╰─── Unknown register +  │ +  │ Help: Did you mean s0, s10, or s5? +────╯ +" +`; diff --git a/tests/arch/__snapshots__/riscv/error/compiler/test_riscv_error_compiler_005.s.snap b/tests/arch/__snapshots__/riscv/error/compiler/test_riscv_error_compiler_005.s.snap new file mode 100644 index 000000000..7a023e6f5 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/error/compiler/test_riscv_error_compiler_005.s.snap @@ -0,0 +1,48 @@ +export const snapshot = {}; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_005.s 1`] = ` +{ + column: 19, + errorText: "[E23] Error: Value 291 is outside of the valid range of the field", + line: 7, +} +`; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_005.s 2`] = ` +"[E23] Error: Value 291 is outside of the valid range of the field + ╭─[ assembly:7:19 ] + │ + 7 │ a: .byte 0x123 + │ ──┬── + │ ╰──── This expression has value 291 + │ + │ Note: Allowed range is [-128, 255] +───╯ +" +`; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_005.s 3`] = ` +"[E23] Error: Value 291 is outside of the valid range of the field + ╭─[ assembly:7:19 ] + │ + 7 │ a: .byte 0x123 + │ ──┬── + │ ╰──── This expression has value 291 + │ + │ Note: Allowed range is [-128, 255] +───╯ +" +`; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_005.s 4`] = ` +"[E23] Error: Value 291 is outside of the valid range of the field + ╭─[ assembly:7:19 ] + │ + 7 │     a:      .byte 0x123 +  │ ──┬── +  │ ╰──── This expression has value 291 +  │ +  │ Note: Allowed range is [-128, 255] +───╯ +" +`; diff --git a/tests/arch/__snapshots__/riscv/error/compiler/test_riscv_error_compiler_006.s.snap b/tests/arch/__snapshots__/riscv/error/compiler/test_riscv_error_compiler_006.s.snap new file mode 100644 index 000000000..93dce8464 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/error/compiler/test_riscv_error_compiler_006.s.snap @@ -0,0 +1,84 @@ +export const snapshot = {}; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_006.s 1`] = ` +{ + column: 7, + errorText: "[E09] Error: Incorrect instruction syntax", + line: 11, +} +`; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_006.s 2`] = ` +"[E09] Error: Incorrect instruction syntax + ╭─[ assembly:11:7 ] + │ + 11 │ li t0, 0xhello + │ ─────┬───── + │ ╰─────── Incorrect syntax + │ + │ Note: Allowed formats: + │ opcode rd, val +────╯ + +The syntax opcode rd, val failed with the following reason: +Error: found identifier (xhello) but expected binary operator or end of input + ╭─[ assembly:11:12 ] + │ + 11 │ li t0, 0xhello + │ ┬───┬── + │ ╰──────── While parsing this expression + │ │ + │ ╰──── Unexpected input +────╯ +" +`; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_006.s 3`] = ` +"[E09] Error: Incorrect instruction syntax + ╭─[ assembly:11:7 ] + │ + 11 │ li t0, 0xhello + │ ─────┬───── + │ ╰─────── Incorrect syntax + │ + │ Note: Allowed formats: + │ opcode rd, val +────╯ + +The syntax opcode rd, val failed with the following reason: +Error: found identifier (xhello) but expected binary operator or end of input + ╭─[ assembly:11:12 ] + │ + 11 │ li t0, 0xhello + │ ┬───┬── + │ ╰──────── While parsing this expression + │ │ + │ ╰──── Unexpected input +────╯ +" +`; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_006.s 4`] = ` +"[E09] Error: Incorrect instruction syntax + ╭─[ assembly:11:7 ] + │ + 11 │    li t0, 0xhello +  │ ─────┬───── +  │ ╰─────── Incorrect syntax +  │ +  │ Note: Allowed formats: +  │ opcode rd, val +────╯ + +The syntax opcode rd, val failed with the following reason: +Error: found identifier (xhello) but expected binary operator or end of input + ╭─[ assembly:11:12 ] + │ + 11 │    li t0, 0xhello +  │ ┬───┬── +  │ ╰──────── While parsing this expression +  │ │ +  │ ╰──── Unexpected input +────╯ +" +`; diff --git a/tests/arch/__snapshots__/riscv/error/compiler/test_riscv_error_compiler_007.s.snap b/tests/arch/__snapshots__/riscv/error/compiler/test_riscv_error_compiler_007.s.snap new file mode 100644 index 000000000..4e7d94e16 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/error/compiler/test_riscv_error_compiler_007.s.snap @@ -0,0 +1,48 @@ +export const snapshot = {}; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_007.s 1`] = ` +{ + column: 7, + errorText: "[E03] Error: Label mains isn't defined", + line: 11, +} +`; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_007.s 2`] = ` +"[E03] Error: Label mains isn't defined + ╭─[ assembly:11:7 ] + │ + 11 │ j mains + │ ──┬── + │ ╰──── Unknown label + │ + │ Help: Did you mean main? +────╯ +" +`; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_007.s 3`] = ` +"[E03] Error: Label mains isn't defined + ╭─[ assembly:11:7 ] + │ + 11 │ j mains + │ ──┬── + │ ╰──── Unknown label + │ + │ Help: Did you mean main? +────╯ +" +`; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_007.s 4`] = ` +"[E03] Error: Label mains isn't defined + ╭─[ assembly:11:7 ] + │ + 11 │     j mains +  │ ──┬── +  │ ╰──── Unknown label +  │ +  │ Help: Did you mean main? +────╯ +" +`; diff --git a/tests/arch/__snapshots__/riscv/error/compiler/test_riscv_error_compiler_008.s.snap b/tests/arch/__snapshots__/riscv/error/compiler/test_riscv_error_compiler_008.s.snap new file mode 100644 index 000000000..e64a0476b --- /dev/null +++ b/tests/arch/__snapshots__/riscv/error/compiler/test_riscv_error_compiler_008.s.snap @@ -0,0 +1,66 @@ +export const snapshot = {}; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_008.s 1`] = ` +{ + column: 4, + errorText: "[E23] Error: Value 305419896 is outside of the valid range of the field", + line: 8, +} +`; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_008.s 2`] = ` +"[E23] Error: Value 305419896 is outside of the valid range of the field + ╭─[ :1:17 ] + │ + 1 │ beq zero, zero, off; + │ ─┬─ + │ ╰─── This expression has value 305419896 + │ + ├─[ assembly:8:4 ] + │ + 8 │ j 0x12345678 + │ ──────┬───── + │ ╰─────── Generated by this pseudoinstruction + │ + │ Note: Allowed range is [-4096, 4095] +───╯ +" +`; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_008.s 3`] = ` +"[E23] Error: Value 305419896 is outside of the valid range of the field + ╭─[ <expansion 1>:1:17 ] + │ + 1 │ beq zero, zero, off; + │ ─┬─ + │ ╰─── This expression has value 305419896 + │ + ├─[ assembly:8:4 ] + │ + 8 │ j 0x12345678 + │ ──────┬───── + │ ╰─────── Generated by this pseudoinstruction + │ + │ Note: Allowed range is [-4096, 4095] +───╯ +" +`; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_008.s 4`] = ` +"[E23] Error: Value 305419896 is outside of the valid range of the field + ╭─[ :1:17 ] + │ + 1 │ beq zero, zero, off; +  │ ─┬─ +  │ ╰─── This expression has value 305419896 + │ + ├─[ assembly:8:4 ] + │ + 8 │    j 0x12345678 +  │ ──────┬───── +  │ ╰─────── Generated by this pseudoinstruction +  │ +  │ Note: Allowed range is [-4096, 4095] +───╯ +" +`; diff --git a/tests/arch/__snapshots__/riscv/error/compiler/test_riscv_error_compiler_009.s.snap b/tests/arch/__snapshots__/riscv/error/compiler/test_riscv_error_compiler_009.s.snap new file mode 100644 index 000000000..91590d5d8 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/error/compiler/test_riscv_error_compiler_009.s.snap @@ -0,0 +1,84 @@ +export const snapshot = {}; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_009.s 1`] = ` +{ + column: 6, + errorText: "[E09] Error: Incorrect instruction syntax", + line: 8, +} +`; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_009.s 2`] = ` +"[E09] Error: Incorrect instruction syntax + ╭─[ assembly:8:6 ] + │ + 8 │ j 0xhello + │ ───┬─── + │ ╰───── Incorrect syntax + │ + │ Note: Allowed formats: + │ opcode off +───╯ + +The syntax opcode off failed with the following reason: +Error: found identifier (xhello) but expected binary operator or end of input + ╭─[ assembly:8:7 ] + │ + 8 │ j 0xhello + │ ┬───┬── + │ ╰──────── While parsing this expression + │ │ + │ ╰──── Unexpected input +───╯ +" +`; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_009.s 3`] = ` +"[E09] Error: Incorrect instruction syntax + ╭─[ assembly:8:6 ] + │ + 8 │ j 0xhello + │ ───┬─── + │ ╰───── Incorrect syntax + │ + │ Note: Allowed formats: + │ opcode off +───╯ + +The syntax opcode off failed with the following reason: +Error: found identifier (xhello) but expected binary operator or end of input + ╭─[ assembly:8:7 ] + │ + 8 │ j 0xhello + │ ┬───┬── + │ ╰──────── While parsing this expression + │ │ + │ ╰──── Unexpected input +───╯ +" +`; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_009.s 4`] = ` +"[E09] Error: Incorrect instruction syntax + ╭─[ assembly:8:6 ] + │ + 8 │    j 0xhello +  │ ───┬─── +  │ ╰───── Incorrect syntax +  │ +  │ Note: Allowed formats: +  │ opcode off +───╯ + +The syntax opcode off failed with the following reason: +Error: found identifier (xhello) but expected binary operator or end of input + ╭─[ assembly:8:7 ] + │ + 8 │    j 0xhello +  │ ┬───┬── +  │ ╰──────── While parsing this expression +  │ │ +  │ ╰──── Unexpected input +───╯ +" +`; diff --git a/tests/arch/__snapshots__/riscv/error/compiler/test_riscv_error_compiler_010.s.snap b/tests/arch/__snapshots__/riscv/error/compiler/test_riscv_error_compiler_010.s.snap new file mode 100644 index 000000000..4b2e947f0 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/error/compiler/test_riscv_error_compiler_010.s.snap @@ -0,0 +1,42 @@ +export const snapshot = {}; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_010.s 1`] = ` +{ + column: 16, + errorText: "[E16] Error: Data memory segment is full", + line: 8, +} +`; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_010.s 2`] = ` +"[E16] Error: Data memory segment is full + ╭─[ assembly:8:16 ] + │ + 8 │ spa: .zero 16 * 1024 * 1024 * 1024 + │ ───────────┬─────────── + │ ╰───────────── This element doesn't fit in the available space +───╯ +" +`; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_010.s 3`] = ` +"[E16] Error: Data memory segment is full + ╭─[ assembly:8:16 ] + │ + 8 │ spa: .zero 16 * 1024 * 1024 * 1024 + │ ───────────┬─────────── + │ ╰───────────── This element doesn't fit in the available space +───╯ +" +`; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_010.s 4`] = ` +"[E16] Error: Data memory segment is full + ╭─[ assembly:8:16 ] + │ + 8 │     spa:    .zero  16 * 1024 * 1024 * 1024 +  │ ───────────┬─────────── +  │ ╰───────────── This element doesn't fit in the available space +───╯ +" +`; diff --git a/tests/arch/__snapshots__/riscv/error/compiler/test_riscv_error_compiler_014.s.snap b/tests/arch/__snapshots__/riscv/error/compiler/test_riscv_error_compiler_014.s.snap new file mode 100644 index 000000000..b9eb29ed3 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/error/compiler/test_riscv_error_compiler_014.s.snap @@ -0,0 +1,42 @@ +export const snapshot = {}; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_014.s 1`] = ` +{ + column: 14, + errorText: "[E01] Error: Directive .directive isn't defined", + line: 8, +} +`; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_014.s 2`] = ` +"[E01] Error: Directive .directive isn't defined + ╭─[ assembly:8:14 ] + │ + 8 │ example: .directive 221 + │ ─────┬──── + │ ╰────── Unknown directive +───╯ +" +`; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_014.s 3`] = ` +"[E01] Error: Directive .directive isn't defined + ╭─[ assembly:8:14 ] + │ + 8 │ example: .directive 221 + │ ─────┬──── + │ ╰────── Unknown directive +───╯ +" +`; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_014.s 4`] = ` +"[E01] Error: Directive .directive isn't defined + ╭─[ assembly:8:14 ] + │ + 8 │     example:    .directive 221 +  │ ─────┬──── +  │ ╰────── Unknown directive +───╯ +" +`; diff --git a/tests/arch/__snapshots__/riscv/error/compiler/test_riscv_error_compiler_015.s.snap b/tests/arch/__snapshots__/riscv/error/compiler/test_riscv_error_compiler_015.s.snap new file mode 100644 index 000000000..aa77ace0e --- /dev/null +++ b/tests/arch/__snapshots__/riscv/error/compiler/test_riscv_error_compiler_015.s.snap @@ -0,0 +1,42 @@ +export const snapshot = {}; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_015.s 1`] = ` +{ + column: 22, + errorText: "[E03] Error: Label hello isn't defined", + line: 8, +} +`; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_015.s 2`] = ` +"[E03] Error: Label hello isn't defined + ╭─[ assembly:8:22 ] + │ + 8 │ example: .word hello + │ ──┬── + │ ╰──── Unknown label +───╯ +" +`; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_015.s 3`] = ` +"[E03] Error: Label hello isn't defined + ╭─[ assembly:8:22 ] + │ + 8 │ example: .word hello + │ ──┬── + │ ╰──── Unknown label +───╯ +" +`; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_015.s 4`] = ` +"[E03] Error: Label hello isn't defined + ╭─[ assembly:8:22 ] + │ + 8 │     example:   .word hello +  │ ──┬── +  │ ╰──── Unknown label +───╯ +" +`; diff --git a/tests/arch/__snapshots__/riscv/error/compiler/test_riscv_error_compiler_016.s.snap b/tests/arch/__snapshots__/riscv/error/compiler/test_riscv_error_compiler_016.s.snap new file mode 100644 index 000000000..cffc1ed27 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/error/compiler/test_riscv_error_compiler_016.s.snap @@ -0,0 +1,48 @@ +export const snapshot = {}; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_016.s 1`] = ` +{ + column: 33, + errorText: "Compilation error", + line: 8, +} +`; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_016.s 2`] = ` +'Error: Unterminated string literal + ╭─[ assembly:8:33 ] + │ + 8 │ example: .string hello world" + │ ───┬─┬ + │ ╰──── While parsing this identifier + │ │ + │ ╰── Caused by this +───╯ +' +`; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_016.s 3`] = ` +"Error: Unterminated string literal + ╭─[ assembly:8:33 ] + │ + 8 │ example: .string hello world" + │ ───┬─┬ + │ ╰──── While parsing this identifier + │ │ + │ ╰── Caused by this +───╯ +" +`; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_016.s 4`] = ` +'Error: Unterminated string literal + ╭─[ assembly:8:33 ] + │ + 8 │     example:    .string hello world" +  │ ───┬─┬ +  │ ╰──── While parsing this identifier +  │ │ +  │ ╰── Caused by this +───╯ +' +`; diff --git a/tests/arch/__snapshots__/riscv/error/compiler/test_riscv_error_compiler_017.s.snap b/tests/arch/__snapshots__/riscv/error/compiler/test_riscv_error_compiler_017.s.snap new file mode 100644 index 000000000..c2fa2e1af --- /dev/null +++ b/tests/arch/__snapshots__/riscv/error/compiler/test_riscv_error_compiler_017.s.snap @@ -0,0 +1,48 @@ +export const snapshot = {}; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_017.s 1`] = ` +{ + column: 34, + errorText: "Compilation error", + line: 8, +} +`; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_017.s 2`] = ` +'Error: Unterminated string literal + ╭─[ assembly:8:34 ] + │ + 8 │ example: .string "hello world + │ ──────┬─────┬ + │ ╰──────── While parsing this string + │ │ + │ ╰── Caused by this +───╯ +' +`; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_017.s 3`] = ` +"Error: Unterminated string literal + ╭─[ assembly:8:34 ] + │ + 8 │ example: .string "hello world + │ ──────┬─────┬ + │ ╰──────── While parsing this string + │ │ + │ ╰── Caused by this +───╯ +" +`; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_017.s 4`] = ` +'Error: Unterminated string literal + ╭─[ assembly:8:34 ] + │ + 8 │     example:    .string "hello world +  │ ──────┬─────┬ +  │ ╰──────── While parsing this string +  │ │ +  │ ╰── Caused by this +───╯ +' +`; diff --git a/tests/arch/__snapshots__/riscv/error/compiler/test_riscv_error_compiler_018.s.snap b/tests/arch/__snapshots__/riscv/error/compiler/test_riscv_error_compiler_018.s.snap new file mode 100644 index 000000000..3476a5bd0 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/error/compiler/test_riscv_error_compiler_018.s.snap @@ -0,0 +1,48 @@ +export const snapshot = {}; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_018.s 1`] = ` +{ + column: 20, + errorText: "[E23] Error: Value 74565 is outside of the valid range of the field", + line: 7, +} +`; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_018.s 2`] = ` +"[E23] Error: Value 74565 is outside of the valid range of the field + ╭─[ assembly:7:20 ] + │ + 7 │ example: .half 0x12345 + │ ───┬─── + │ ╰───── This expression has value 74565 + │ + │ Note: Allowed range is [-32768, 65535] +───╯ +" +`; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_018.s 3`] = ` +"[E23] Error: Value 74565 is outside of the valid range of the field + ╭─[ assembly:7:20 ] + │ + 7 │ example: .half 0x12345 + │ ───┬─── + │ ╰───── This expression has value 74565 + │ + │ Note: Allowed range is [-32768, 65535] +───╯ +" +`; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_018.s 4`] = ` +"[E23] Error: Value 74565 is outside of the valid range of the field + ╭─[ assembly:7:20 ] + │ + 7 │   example:   .half 0x12345 +  │ ───┬─── +  │ ╰───── This expression has value 74565 +  │ +  │ Note: Allowed range is [-32768, 65535] +───╯ +" +`; diff --git a/tests/arch/__snapshots__/riscv/error/compiler/test_riscv_error_compiler_019.s.snap b/tests/arch/__snapshots__/riscv/error/compiler/test_riscv_error_compiler_019.s.snap new file mode 100644 index 000000000..ef6f4bcea --- /dev/null +++ b/tests/arch/__snapshots__/riscv/error/compiler/test_riscv_error_compiler_019.s.snap @@ -0,0 +1,48 @@ +export const snapshot = {}; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_019.s 1`] = ` +{ + column: 12, + errorText: "Compilation error", + line: 7, +} +`; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_019.s 2`] = ` +"Error: found identifier (x) but expected ,, \\\\n, binary operator, or end of input + ╭─[ assembly:7:12 ] + │ + 7 │ .byte 0x + │ ┬┬ + │ ╰─── While parsing this expression + │ │ + │ ╰── Unexpected input +───╯ +" +`; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_019.s 3`] = ` +"Error: found identifier (x) but expected ,, \\\\n, binary operator, or end of input + ╭─[ assembly:7:12 ] + │ + 7 │ .byte 0x + │ ┬┬ + │ ╰─── While parsing this expression + │ │ + │ ╰── Unexpected input +───╯ +" +`; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_019.s 4`] = ` +"Error: found identifier (x) but expected ,, \\\\n, binary operator, or end of input + ╭─[ assembly:7:12 ] + │ + 7 │     .byte 0x +  │ ┬┬ +  │ ╰─── While parsing this expression +  │ │ +  │ ╰── Unexpected input +───╯ +" +`; diff --git a/tests/arch/__snapshots__/riscv/error/compiler/test_riscv_error_compiler_021.s.snap b/tests/arch/__snapshots__/riscv/error/compiler/test_riscv_error_compiler_021.s.snap new file mode 100644 index 000000000..cfa77126f --- /dev/null +++ b/tests/arch/__snapshots__/riscv/error/compiler/test_riscv_error_compiler_021.s.snap @@ -0,0 +1,42 @@ +export const snapshot = {}; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_021.s 1`] = ` +{ + column: 21, + errorText: "[E17] Error: Data at address 0x200001 isn't aligned to size 2 nor word size 4", + line: 9, +} +`; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_021.s 2`] = ` +"[E17] Error: Data at address 0x200001 isn't aligned to size 2 nor word size 4 + ╭─[ assembly:9:21 ] + │ + 9 │ example2: .half 2 + │ ┬ + │ ╰── This value isn't aligned +───╯ +" +`; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_021.s 3`] = ` +"[E17] Error: Data at address 0x200001 isn't aligned to size 2 nor word size 4 + ╭─[ assembly:9:21 ] + │ + 9 │ example2: .half 2 + │ ┬ + │ ╰── This value isn't aligned +───╯ +" +`; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_021.s 4`] = ` +"[E17] Error: Data at address 0x200001 isn't aligned to size 2 nor word size 4 + ╭─[ assembly:9:21 ] + │ + 9 │     example2:   .half 2 +  │ ┬ +  │ ╰── This value isn't aligned +───╯ +" +`; diff --git a/tests/arch/__snapshots__/riscv/error/compiler/test_riscv_error_compiler_022.s.snap b/tests/arch/__snapshots__/riscv/error/compiler/test_riscv_error_compiler_022.s.snap new file mode 100644 index 000000000..a8fa01035 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/error/compiler/test_riscv_error_compiler_022.s.snap @@ -0,0 +1,42 @@ +export const snapshot = {}; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_022.s 1`] = ` +{ + column: 11, + errorText: "[E22] Error: Negative values aren't allowed here", + line: 7, +} +`; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_022.s 2`] = ` +"[E22] Error: Negative values aren't allowed here + ╭─[ assembly:7:11 ] + │ + 7 │ .zero -10 + │ ─┬─ + │ ╰─── This expression has value -10 +───╯ +" +`; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_022.s 3`] = ` +"[E22] Error: Negative values aren't allowed here + ╭─[ assembly:7:11 ] + │ + 7 │ .zero -10 + │ ─┬─ + │ ╰─── This expression has value -10 +───╯ +" +`; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_022.s 4`] = ` +"[E22] Error: Negative values aren't allowed here + ╭─[ assembly:7:11 ] + │ + 7 │     .zero -10 +  │ ─┬─ +  │ ╰─── This expression has value -10 +───╯ +" +`; diff --git a/tests/arch/__snapshots__/riscv/error/compiler/test_riscv_error_compiler_023.s.snap b/tests/arch/__snapshots__/riscv/error/compiler/test_riscv_error_compiler_023.s.snap new file mode 100644 index 000000000..5433e5684 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/error/compiler/test_riscv_error_compiler_023.s.snap @@ -0,0 +1,48 @@ +export const snapshot = {}; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_023.s 1`] = ` +{ + column: 20, + errorText: "[E10] Error: Incorrect amount of arguments, expected at least 1 but found 0", + line: 9, +} +`; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_023.s 2`] = ` +"[E10] Error: Incorrect amount of arguments, expected at least 1 but found 0 + ╭─[ assembly:9:20 ] + │ + 9 │ example2: .half + │ │ + │ ╰─ This directive has 0 arguments + │ + │ Help: Consider adding the missing 1 argument +───╯ +" +`; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_023.s 3`] = ` +"[E10] Error: Incorrect amount of arguments, expected at least 1 but found 0 + ╭─[ assembly:9:20 ] + │ + 9 │ example2: .half + │ │ + │ ╰─ This directive has 0 arguments + │ + │ Help: Consider adding the missing 1 argument +───╯ +" +`; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_023.s 4`] = ` +"[E10] Error: Incorrect amount of arguments, expected at least 1 but found 0 + ╭─[ assembly:9:20 ] + │ + 9 │    example2:    .half +  │ │ +  │ ╰─ This directive has 0 arguments +  │ +  │ Help: Consider adding the missing 1 argument +───╯ +" +`; diff --git a/tests/arch/__snapshots__/riscv/error/compiler/test_riscv_error_compiler_030.s.snap b/tests/arch/__snapshots__/riscv/error/compiler/test_riscv_error_compiler_030.s.snap new file mode 100644 index 000000000..ca1b94a2a --- /dev/null +++ b/tests/arch/__snapshots__/riscv/error/compiler/test_riscv_error_compiler_030.s.snap @@ -0,0 +1,42 @@ +export const snapshot = {}; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_030.s 1`] = ` +{ + column: 14, + errorText: "[E13] Error: Main label main not found", + line: 8, +} +`; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_030.s 2`] = ` +"[E13] Error: Main label main not found + ╭─[ assembly:8:14 ] + │ + 8 │ li t0, 10 + │ │ + │ ╰─ Consider adding a label called main to an instruction +───╯ +" +`; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_030.s 3`] = ` +"[E13] Error: Main label main not found + ╭─[ assembly:8:14 ] + │ + 8 │ li t0, 10 + │ │ + │ ╰─ Consider adding a label called main to an instruction +───╯ +" +`; + +snapshot[`riscv/error/compiler/test_riscv_error_compiler_030.s 4`] = ` +"[E13] Error: Main label main not found + ╭─[ assembly:8:14 ] + │ + 8 │     li t0, 10 +  │ │ +  │ ╰─ Consider adding a label called main to an instruction +───╯ +" +`; diff --git a/tests/arch/arch_utils.mts b/tests/arch/arch_utils.mts index 55b019578..94f8c1d27 100644 --- a/tests/arch/arch_utils.mts +++ b/tests/arch/arch_utils.mts @@ -1,15 +1,19 @@ import { assertSnapshot } from "jsr:@std/testing/snapshot"; +import { assertEquals } from "https://deno.land/std/assert/mod.ts"; import * as path from "jsr:@std/path"; import fs from "node:fs"; import { executeStep, loadArchitecture, compileAssembly, + CompileResult, } from "../unit/arch/simulator-test-utils.mts"; import { testKeyboard } from "../../src/core/executor/IO.mjs"; import * as creator from "../../src/core/core.mjs"; import { coreEvents, CoreEventTypes } from "../../src/core/events.mts"; import { logger } from "../../src/core/utils/creator_logger.mjs"; +import { assembleCreator } from "../../src/core/assembler/creatorAssembler/deno/creatorAssembler.mjs"; +import { getCleanErrorMessage } from "../../src/core/assembler/assembler.mjs"; export const ARCH = { riscv: "RISCV/RV32IMFD.yml", @@ -103,3 +107,40 @@ export function execution_tests( }); } } + +/** + * Executes a group of compiler error snapshot tests + * @param archPath - Path to the YAML architecture configuration file, from the architectures folder + * @param dir - Path to the directory with the assembly files + */ +export function compile_error_tests(archPath: string, dir: string): void { + logger.disable(); + const ARCH_PATH = "architecture/" + archPath; + loadArchitecture(ARCH_PATH); + const DIR = `${PREFIX}tests/arch/${dir}`; + for (const file of fs.globSync("*.s", { cwd: DIR })) { + Deno.test(`${dir}/${file}`, async t => { + // Compile code + const asm_path = `${DIR}/${file}`; + const path = `${PREFIX}/tests/arch/__snapshots__/${dir}/${file}.snap`; + const testAssembly = fs.readFileSync(asm_path, "utf8"); + const res_ansi = (await creator.assembly_compile( + testAssembly, + assembleCreator, + true, + )) as CompileResult; + const res_html = (await creator.assembly_compile( + testAssembly, + assembleCreator, + false, + )) as CompileResult; + const cleanMsg = getCleanErrorMessage(res_html.msg, false); + assertEquals(getCleanErrorMessage(res_ansi.msg, true), cleanMsg); + assertEquals(res_ansi.linter, res_html.linter); + await assertSnapshot(t, res_html.linter, { path }); + await assertSnapshot(t, cleanMsg, { path }); + await assertSnapshot(t, res_html.msg, { path }); + await assertSnapshot(t, res_ansi.msg, { path }); + }); + } +} diff --git a/tests/arch/mips/error.test.mts b/tests/arch/mips/error.test.mts index cbd1a9b36..54d2a2a7e 100644 --- a/tests/arch/mips/error.test.mts +++ b/tests/arch/mips/error.test.mts @@ -1,4 +1,4 @@ -import { ARCH, execution_tests } from "../arch_utils.mts"; +import { ARCH, execution_tests, compile_error_tests } from "../arch_utils.mts"; execution_tests( ARCH.mips, @@ -15,3 +15,5 @@ execution_tests( "test_mips_error_executor_009.s", ]), ); + +compile_error_tests(ARCH.mips, "mips/error/compiler") diff --git a/tests/arch/mips/error/compiler/test_mips_error_compiler_001.out b/tests/arch/mips/error/compiler/test_mips_error_compiler_001.out deleted file mode 100644 index 5c7476c32..000000000 --- a/tests/arch/mips/error/compiler/test_mips_error_compiler_001.out +++ /dev/null @@ -1,19 +0,0 @@ - - -[E12] Error: Label `A` is already defined - ╭─[ assembly:9:4 ] - │ - 7 │ A: .word -1 - │ ─┬ - │ ╰── Note: Label also defined here - │ - 9 │ A: .half 23 - │ ─┬ - │ ╰── Duplicate label - │ - │ Help: Consider renaming either of the labels -───╯ - -Not executed -keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/error/compiler/test_mips_error_compiler_002.out b/tests/arch/mips/error/compiler/test_mips_error_compiler_002.out deleted file mode 100644 index 10ce10d62..000000000 --- a/tests/arch/mips/error/compiler/test_mips_error_compiler_002.out +++ /dev/null @@ -1,13 +0,0 @@ - - -[E02] Error: Instruction `suma` isn't defined - ╭─[ assembly:12:4 ] - │ - 12 │ suma $t0, $t1, $t2 - │ ──┬─ - │ ╰─── Unknown instruction -────╯ - -Not executed -keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/error/compiler/test_mips_error_compiler_003.out b/tests/arch/mips/error/compiler/test_mips_error_compiler_003.out deleted file mode 100644 index d2bf39ee3..000000000 --- a/tests/arch/mips/error/compiler/test_mips_error_compiler_003.out +++ /dev/null @@ -1,35 +0,0 @@ - - -[E09] Error: Incorrect instruction syntax - ╭─[ assembly:12:8 ] - │ - 12 │ add 25, $t1, 12 - │ ─────┬───── - │ ╰─────── Incorrect syntax - │ - │ Note: Allowed formats: - │ add $reg3,$reg2,$reg1 - │ add $rs,$rt,inm -────╯ - -The syntax `add $reg3,$reg2,$reg1` failed with the following reason: -Error: found `integer (25)` but expected `$` - ╭─[ assembly:12:8 ] - │ - 12 │ add 25, $t1, 12 - │ ─┬ - │ ╰── Unexpected input -────╯ - -The syntax `add $rs,$rt,inm` failed with the following reason: -Error: found `integer (25)` but expected `$` - ╭─[ assembly:12:8 ] - │ - 12 │ add 25, $t1, 12 - │ ─┬ - │ ╰── Unexpected input -────╯ - -Not executed -keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/error/compiler/test_mips_error_compiler_004.out b/tests/arch/mips/error/compiler/test_mips_error_compiler_004.out deleted file mode 100644 index 682367df3..000000000 --- a/tests/arch/mips/error/compiler/test_mips_error_compiler_004.out +++ /dev/null @@ -1,15 +0,0 @@ - - -[E05] Error: Register `s50` isn't defined in file type `Integer` - ╭─[ assembly:12:19 ] - │ - 12 │ add $t0, $t1, $s50 - │ ─┬─ - │ ╰─── Unknown register - │ - │ Help: Did you mean `s0` or `s5`? -────╯ - -Not executed -keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/error/compiler/test_mips_error_compiler_005.out b/tests/arch/mips/error/compiler/test_mips_error_compiler_005.out deleted file mode 100644 index 5c0fd2a61..000000000 --- a/tests/arch/mips/error/compiler/test_mips_error_compiler_005.out +++ /dev/null @@ -1,15 +0,0 @@ - - -[E23] Error: Value `291` is outside of the valid range of the field - ╭─[ assembly:7:19 ] - │ - 7 │ a: .byte 0x123 - │ ──┬── - │ ╰──── This expression has value `291` - │ - │ Note: Allowed range is [-128, 255] -───╯ - -Not executed -keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/error/compiler/test_mips_error_compiler_006.out b/tests/arch/mips/error/compiler/test_mips_error_compiler_006.out deleted file mode 100644 index a77e8dcd5..000000000 --- a/tests/arch/mips/error/compiler/test_mips_error_compiler_006.out +++ /dev/null @@ -1,27 +0,0 @@ - - -[E09] Error: Incorrect instruction syntax - ╭─[ assembly:11:7 ] - │ - 11 │ li $t0, 0xhello - │ ──────┬───── - │ ╰─────── Incorrect syntax - │ - │ Note: Allowed formats: - │ li $rd,val -────╯ - -The syntax `li $rd,val` failed with the following reason: -Error: found `identifier (xhello)` but expected `\n`, `binary operator`, or `end of input` - ╭─[ assembly:11:13 ] - │ - 11 │ li $t0, 0xhello - │ ┬───┬── - │ ╰──────── While parsing this `expression` - │ │ - │ ╰──── Unexpected input -────╯ - -Not executed -keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/error/compiler/test_mips_error_compiler_007.out b/tests/arch/mips/error/compiler/test_mips_error_compiler_007.out deleted file mode 100644 index c966e8c00..000000000 --- a/tests/arch/mips/error/compiler/test_mips_error_compiler_007.out +++ /dev/null @@ -1,15 +0,0 @@ - - -[E03] Error: Label `mains` isn't defined - ╭─[ assembly:11:7 ] - │ - 11 │ j mains - │ ──┬── - │ ╰──── Unknown label - │ - │ Help: Did you mean `main`? -────╯ - -Not executed -keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/error/compiler/test_mips_error_compiler_008.out b/tests/arch/mips/error/compiler/test_mips_error_compiler_008.out deleted file mode 100644 index eb758f055..000000000 --- a/tests/arch/mips/error/compiler/test_mips_error_compiler_008.out +++ /dev/null @@ -1,15 +0,0 @@ - - -[E23] Error: Value `305419896` is outside of the valid range of the field - ╭─[ assembly:8:6 ] - │ - 8 │ j 0x12345678 - │ ─────┬──── - │ ╰────── This expression has value `305419896` - │ - │ Note: Allowed range is [-33554432, 33554431] -───╯ - -Not executed -keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/error/compiler/test_mips_error_compiler_009.out b/tests/arch/mips/error/compiler/test_mips_error_compiler_009.out deleted file mode 100644 index dc58ec9fa..000000000 --- a/tests/arch/mips/error/compiler/test_mips_error_compiler_009.out +++ /dev/null @@ -1,27 +0,0 @@ - - -[E09] Error: Incorrect instruction syntax - ╭─[ assembly:8:6 ] - │ - 8 │ j 0xhello - │ ───┬─── - │ ╰───── Incorrect syntax - │ - │ Note: Allowed formats: - │ j addr -───╯ - -The syntax `j addr` failed with the following reason: -Error: found `identifier (xhello)` but expected `\n`, `binary operator`, or `end of input` - ╭─[ assembly:8:7 ] - │ - 8 │ j 0xhello - │ ┬───┬── - │ ╰──────── While parsing this `expression` - │ │ - │ ╰──── Unexpected input -───╯ - -Not executed -keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/error/compiler/test_mips_error_compiler_010.s b/tests/arch/mips/error/compiler/test_mips_error_compiler_010.s index 94af4567c..975b26a38 100644 --- a/tests/arch/mips/error/compiler/test_mips_error_compiler_010.s +++ b/tests/arch/mips/error/compiler/test_mips_error_compiler_010.s @@ -5,8 +5,8 @@ .data .align 2 - spa: .space 52428800 + spa: .space 16 * 1024 * 1024 * 1024 .text main: - li $t0, 10 \ No newline at end of file + li $t0, 10 diff --git a/tests/arch/mips/error/compiler/test_mips_error_compiler_014.out b/tests/arch/mips/error/compiler/test_mips_error_compiler_014.out deleted file mode 100644 index 81e4462e8..000000000 --- a/tests/arch/mips/error/compiler/test_mips_error_compiler_014.out +++ /dev/null @@ -1,13 +0,0 @@ - - -[E01] Error: Directive `.directive` isn't defined - ╭─[ assembly:8:14 ] - │ - 8 │ example: .directive 221 - │ ─────┬──── - │ ╰────── Unknown directive -───╯ - -Not executed -keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/error/compiler/test_mips_error_compiler_015.out b/tests/arch/mips/error/compiler/test_mips_error_compiler_015.out deleted file mode 100644 index 0c8632ae4..000000000 --- a/tests/arch/mips/error/compiler/test_mips_error_compiler_015.out +++ /dev/null @@ -1,13 +0,0 @@ - - -[E03] Error: Label `hello` isn't defined - ╭─[ assembly:8:22 ] - │ - 8 │ example: .word hello - │ ──┬── - │ ╰──── Unknown label -───╯ - -Not executed -keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/error/compiler/test_mips_error_compiler_016.out b/tests/arch/mips/error/compiler/test_mips_error_compiler_016.out deleted file mode 100644 index ea7274441..000000000 --- a/tests/arch/mips/error/compiler/test_mips_error_compiler_016.out +++ /dev/null @@ -1,15 +0,0 @@ - - -Error: Unterminated string literal - ╭─[ assembly:8:32 ] - │ - 8 │ example: .ascii hello world" - │ ───┬─┬ - │ ╰──── While parsing this `identifier` - │ │ - │ ╰── Caused by this -───╯ - -Not executed -keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/error/compiler/test_mips_error_compiler_017.out b/tests/arch/mips/error/compiler/test_mips_error_compiler_017.out deleted file mode 100644 index 543ea4f4a..000000000 --- a/tests/arch/mips/error/compiler/test_mips_error_compiler_017.out +++ /dev/null @@ -1,15 +0,0 @@ - - -Error: Unterminated string literal - ╭─[ assembly:8:33 ] - │ - 8 │ example: .ascii "hello world - │ ──────┬─────┬ - │ ╰──────── While parsing this `string` - │ │ - │ ╰── Caused by this -───╯ - -Not executed -keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/error/compiler/test_mips_error_compiler_018.out b/tests/arch/mips/error/compiler/test_mips_error_compiler_018.out deleted file mode 100644 index da5e6eec9..000000000 --- a/tests/arch/mips/error/compiler/test_mips_error_compiler_018.out +++ /dev/null @@ -1,15 +0,0 @@ - - -[E23] Error: Value `74565` is outside of the valid range of the field - ╭─[ assembly:7:20 ] - │ - 7 │ example: .half 0x12345 - │ ───┬─── - │ ╰───── This expression has value `74565` - │ - │ Note: Allowed range is [-32768, 65535] -───╯ - -Not executed -keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/error/compiler/test_mips_error_compiler_018.s b/tests/arch/mips/error/compiler/test_mips_error_compiler_018.s index ee62c630c..8f6025dc4 100644 --- a/tests/arch/mips/error/compiler/test_mips_error_compiler_018.s +++ b/tests/arch/mips/error/compiler/test_mips_error_compiler_018.s @@ -5,4 +5,5 @@ .data example: .half 0x12345 - +.text +main: nop diff --git a/tests/arch/mips/error/compiler/test_mips_error_compiler_019.out b/tests/arch/mips/error/compiler/test_mips_error_compiler_019.out deleted file mode 100644 index 61d170cee..000000000 --- a/tests/arch/mips/error/compiler/test_mips_error_compiler_019.out +++ /dev/null @@ -1,15 +0,0 @@ - - -Error: found `identifier (x)` but expected `,`, `\n`, `binary operator`, or `end of input` - ╭─[ assembly:7:12 ] - │ - 7 │ .byte 0x - │ ┬┬ - │ ╰─── While parsing this `expression` - │ │ - │ ╰── Unexpected input -───╯ - -Not executed -keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/error/compiler/test_mips_error_compiler_021.out b/tests/arch/mips/error/compiler/test_mips_error_compiler_021.out deleted file mode 100644 index 0fae5b507..000000000 --- a/tests/arch/mips/error/compiler/test_mips_error_compiler_021.out +++ /dev/null @@ -1,13 +0,0 @@ - - -[E17] Error: Data at address `0x200001` isn't aligned to size `2` nor word size `4` - ╭─[ assembly:9:21 ] - │ - 9 │ example2: .half 2 - │ ┬ - │ ╰── This value isn't aligned -───╯ - -Not executed -keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/error/compiler/test_mips_error_compiler_022.out b/tests/arch/mips/error/compiler/test_mips_error_compiler_022.out deleted file mode 100644 index f4c45383c..000000000 --- a/tests/arch/mips/error/compiler/test_mips_error_compiler_022.out +++ /dev/null @@ -1,13 +0,0 @@ - - -[E22] Error: Negative values aren't allowed here - ╭─[ assembly:7:12 ] - │ - 7 │ .space -10 - │ ─┬─ - │ ╰─── This expression has value `-10` -───╯ - -Not executed -keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/error/compiler/test_mips_error_compiler_023.out b/tests/arch/mips/error/compiler/test_mips_error_compiler_023.out deleted file mode 100644 index deb0a1708..000000000 --- a/tests/arch/mips/error/compiler/test_mips_error_compiler_023.out +++ /dev/null @@ -1,15 +0,0 @@ - - -[E10] Error: Incorrect amount of arguments, expected at least `1` but found `0` - ╭─[ assembly:9:20 ] - │ - 9 │ example2: .half - │ │ - │ ╰─ This directive has `0` arguments - │ - │ Help: Consider adding the missing `1` argument -───╯ - -Not executed -keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/error/compiler/test_mips_error_compiler_030.out b/tests/arch/mips/error/compiler/test_mips_error_compiler_030.out deleted file mode 100644 index a02fc0290..000000000 --- a/tests/arch/mips/error/compiler/test_mips_error_compiler_030.out +++ /dev/null @@ -1,13 +0,0 @@ - - -[E13] Error: Main label `main` not found - ╭─[ assembly:8:15 ] - │ - 8 │ li $t0, 10 - │ │ - │ ╰─ Consider adding a label called `main` to an instruction -───╯ - -Not executed -keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/mips/error/compiler/test_mips_error_compiler_030.s b/tests/arch/mips/error/compiler/test_mips_error_compiler_030.s index e69de29bb..6ad952bf9 100644 --- a/tests/arch/mips/error/compiler/test_mips_error_compiler_030.s +++ b/tests/arch/mips/error/compiler/test_mips_error_compiler_030.s @@ -0,0 +1,8 @@ + +# +# Creator (https://creatorsim.github.io/creator/) +# + +.text +main_: + li $t0, 10 diff --git a/tests/arch/riscv/error.test.mts b/tests/arch/riscv/error.test.mts index e571e7b20..cfa60fb8b 100644 --- a/tests/arch/riscv/error.test.mts +++ b/tests/arch/riscv/error.test.mts @@ -1,4 +1,4 @@ -import { ARCH, execution_tests } from "../arch_utils.mts"; +import { ARCH, execution_tests, compile_error_tests } from "../arch_utils.mts"; execution_tests( ARCH.riscv, @@ -14,3 +14,5 @@ execution_tests( "test_riscv_error_executor_008.s", ]), ); + +compile_error_tests(ARCH.riscv, "riscv/error/compiler") diff --git a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_001.out b/tests/arch/riscv/error/compiler/test_riscv_error_compiler_001.out deleted file mode 100644 index 5131c282f..000000000 --- a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_001.out +++ /dev/null @@ -1,19 +0,0 @@ - - -[E12] Error: Label `A` is already defined - ╭─[ assembly:9:2 ] - │ - 7 │ A: .word -1 - │ ─┬ - │ ╰─────── Note: Label also defined here - │ - 9 │ A: .half 23 - │ ─┬ - │ ╰───── Duplicate label - │ - │ Help: Consider renaming either of the labels -───╯ - -Not executed -keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_002.out b/tests/arch/riscv/error/compiler/test_riscv_error_compiler_002.out deleted file mode 100644 index fad0e52c0..000000000 --- a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_002.out +++ /dev/null @@ -1,13 +0,0 @@ - - -[E02] Error: Instruction `suma` isn't defined - ╭─[ assembly:12:2 ] - │ - 12 │ suma t0, t1, t2 - │ ──┬─ - │ ╰─── Unknown instruction -────╯ - -Not executed -keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_003.out b/tests/arch/riscv/error/compiler/test_riscv_error_compiler_003.out deleted file mode 100644 index c14b5930e..000000000 --- a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_003.out +++ /dev/null @@ -1,27 +0,0 @@ - - -[E09] Error: Incorrect instruction syntax - ╭─[ assembly:12:8 ] - │ - 12 │ add t0, t1 - │ ───┬── - │ ╰──── Incorrect syntax - │ - │ Note: Allowed formats: - │ add rd,rs1,rs2 -────╯ - -The syntax `add rd,rs1,rs2` failed with the following reason: -Error: found `end of input` but expected `,`, `\n`, or `binary operator` - ╭─[ assembly:12:14 ] - │ - 12 │ add t0, t1 - │ ─┬│ - │ ╰── While parsing this `expression` - │ │ - │ ╰─ Unexpected input -────╯ - -Not executed -keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_004.out b/tests/arch/riscv/error/compiler/test_riscv_error_compiler_004.out deleted file mode 100644 index b942b63b9..000000000 --- a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_004.out +++ /dev/null @@ -1,15 +0,0 @@ - - -[E05] Error: Register `s50` isn't defined in file type `Integer` - ╭─[ assembly:12:14 ] - │ - 12 │ add t0, t1, s50 - │ ─┬─ - │ ╰─── Unknown register - │ - │ Help: Did you mean `s0`, `s10`, or `s5`? -────╯ - -Not executed -keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_005.out b/tests/arch/riscv/error/compiler/test_riscv_error_compiler_005.out deleted file mode 100644 index 5c0fd2a61..000000000 --- a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_005.out +++ /dev/null @@ -1,15 +0,0 @@ - - -[E23] Error: Value `291` is outside of the valid range of the field - ╭─[ assembly:7:19 ] - │ - 7 │ a: .byte 0x123 - │ ──┬── - │ ╰──── This expression has value `291` - │ - │ Note: Allowed range is [-128, 255] -───╯ - -Not executed -keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_006.out b/tests/arch/riscv/error/compiler/test_riscv_error_compiler_006.out deleted file mode 100644 index 38fa6dacb..000000000 --- a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_006.out +++ /dev/null @@ -1,27 +0,0 @@ - - -[E09] Error: Incorrect instruction syntax - ╭─[ assembly:11:7 ] - │ - 11 │ li t0, 0xhello - │ ─────┬───── - │ ╰─────── Incorrect syntax - │ - │ Note: Allowed formats: - │ li rd,val -────╯ - -The syntax `li rd,val` failed with the following reason: -Error: found `identifier (xhello)` but expected `\n`, `binary operator`, or `end of input` - ╭─[ assembly:11:12 ] - │ - 11 │ li t0, 0xhello - │ ┬───┬── - │ ╰──────── While parsing this `expression` - │ │ - │ ╰──── Unexpected input -────╯ - -Not executed -keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_007.out b/tests/arch/riscv/error/compiler/test_riscv_error_compiler_007.out deleted file mode 100644 index c966e8c00..000000000 --- a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_007.out +++ /dev/null @@ -1,15 +0,0 @@ - - -[E03] Error: Label `mains` isn't defined - ╭─[ assembly:11:7 ] - │ - 11 │ j mains - │ ──┬── - │ ╰──── Unknown label - │ - │ Help: Did you mean `main`? -────╯ - -Not executed -keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_008.out b/tests/arch/riscv/error/compiler/test_riscv_error_compiler_008.out deleted file mode 100644 index a310e0504..000000000 --- a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_008.out +++ /dev/null @@ -1,21 +0,0 @@ - - -[E23] Error: Value `305419896` is outside of the valid range of the field - ╭─[ :1:17 ] - │ - 1 │ beq zero, zero, off; - │ ─┬─ - │ ╰─── This expression has value `305419896` - │ - ├─[ assembly:8:4 ] - │ - 8 │ j 0x12345678 - │ ──────┬───── - │ ╰─────── Generated by this pseudoinstruction - │ - │ Note: Allowed range is [-4096, 4095] -───╯ - -Not executed -keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_009.out b/tests/arch/riscv/error/compiler/test_riscv_error_compiler_009.out deleted file mode 100644 index e000c91dc..000000000 --- a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_009.out +++ /dev/null @@ -1,27 +0,0 @@ - - -[E09] Error: Incorrect instruction syntax - ╭─[ assembly:8:6 ] - │ - 8 │ j 0xhello - │ ───┬─── - │ ╰───── Incorrect syntax - │ - │ Note: Allowed formats: - │ j off -───╯ - -The syntax `j off` failed with the following reason: -Error: found `identifier (xhello)` but expected `\n`, `binary operator`, or `end of input` - ╭─[ assembly:8:7 ] - │ - 8 │ j 0xhello - │ ┬───┬── - │ ╰──────── While parsing this `expression` - │ │ - │ ╰──── Unexpected input -───╯ - -Not executed -keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_010.s b/tests/arch/riscv/error/compiler/test_riscv_error_compiler_010.s index d7c8857d4..99317a3d8 100644 --- a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_010.s +++ b/tests/arch/riscv/error/compiler/test_riscv_error_compiler_010.s @@ -5,8 +5,8 @@ .data .align 2 - spa: .zero 52428800 + spa: .zero 16 * 1024 * 1024 * 1024 .text main: - li t0, 10 \ No newline at end of file + li t0, 10 diff --git a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_014.out b/tests/arch/riscv/error/compiler/test_riscv_error_compiler_014.out deleted file mode 100644 index 81e4462e8..000000000 --- a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_014.out +++ /dev/null @@ -1,13 +0,0 @@ - - -[E01] Error: Directive `.directive` isn't defined - ╭─[ assembly:8:14 ] - │ - 8 │ example: .directive 221 - │ ─────┬──── - │ ╰────── Unknown directive -───╯ - -Not executed -keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_015.out b/tests/arch/riscv/error/compiler/test_riscv_error_compiler_015.out deleted file mode 100644 index 0c8632ae4..000000000 --- a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_015.out +++ /dev/null @@ -1,13 +0,0 @@ - - -[E03] Error: Label `hello` isn't defined - ╭─[ assembly:8:22 ] - │ - 8 │ example: .word hello - │ ──┬── - │ ╰──── Unknown label -───╯ - -Not executed -keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_016.out b/tests/arch/riscv/error/compiler/test_riscv_error_compiler_016.out deleted file mode 100644 index daa5fb858..000000000 --- a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_016.out +++ /dev/null @@ -1,15 +0,0 @@ - - -Error: Unterminated string literal - ╭─[ assembly:8:33 ] - │ - 8 │ example: .string hello world" - │ ───┬─┬ - │ ╰──── While parsing this `identifier` - │ │ - │ ╰── Caused by this -───╯ - -Not executed -keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_017.out b/tests/arch/riscv/error/compiler/test_riscv_error_compiler_017.out deleted file mode 100644 index ade735b68..000000000 --- a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_017.out +++ /dev/null @@ -1,15 +0,0 @@ - - -Error: Unterminated string literal - ╭─[ assembly:8:34 ] - │ - 8 │ example: .string "hello world - │ ──────┬─────┬ - │ ╰──────── While parsing this `string` - │ │ - │ ╰── Caused by this -───╯ - -Not executed -keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_018.out b/tests/arch/riscv/error/compiler/test_riscv_error_compiler_018.out deleted file mode 100644 index da5e6eec9..000000000 --- a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_018.out +++ /dev/null @@ -1,15 +0,0 @@ - - -[E23] Error: Value `74565` is outside of the valid range of the field - ╭─[ assembly:7:20 ] - │ - 7 │ example: .half 0x12345 - │ ───┬─── - │ ╰───── This expression has value `74565` - │ - │ Note: Allowed range is [-32768, 65535] -───╯ - -Not executed -keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_019.out b/tests/arch/riscv/error/compiler/test_riscv_error_compiler_019.out deleted file mode 100644 index 61d170cee..000000000 --- a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_019.out +++ /dev/null @@ -1,15 +0,0 @@ - - -Error: found `identifier (x)` but expected `,`, `\n`, `binary operator`, or `end of input` - ╭─[ assembly:7:12 ] - │ - 7 │ .byte 0x - │ ┬┬ - │ ╰─── While parsing this `expression` - │ │ - │ ╰── Unexpected input -───╯ - -Not executed -keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_021.out b/tests/arch/riscv/error/compiler/test_riscv_error_compiler_021.out deleted file mode 100644 index 0fae5b507..000000000 --- a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_021.out +++ /dev/null @@ -1,13 +0,0 @@ - - -[E17] Error: Data at address `0x200001` isn't aligned to size `2` nor word size `4` - ╭─[ assembly:9:21 ] - │ - 9 │ example2: .half 2 - │ ┬ - │ ╰── This value isn't aligned -───╯ - -Not executed -keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_022.out b/tests/arch/riscv/error/compiler/test_riscv_error_compiler_022.out deleted file mode 100644 index e9a31f9c7..000000000 --- a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_022.out +++ /dev/null @@ -1,13 +0,0 @@ - - -[E22] Error: Negative values aren't allowed here - ╭─[ assembly:7:11 ] - │ - 7 │ .zero -10 - │ ─┬─ - │ ╰─── This expression has value `-10` -───╯ - -Not executed -keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_023.out b/tests/arch/riscv/error/compiler/test_riscv_error_compiler_023.out deleted file mode 100644 index deb0a1708..000000000 --- a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_023.out +++ /dev/null @@ -1,15 +0,0 @@ - - -[E10] Error: Incorrect amount of arguments, expected at least `1` but found `0` - ╭─[ assembly:9:20 ] - │ - 9 │ example2: .half - │ │ - │ ╰─ This directive has `0` arguments - │ - │ Help: Consider adding the missing `1` argument -───╯ - -Not executed -keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_030.out b/tests/arch/riscv/error/compiler/test_riscv_error_compiler_030.out deleted file mode 100644 index 660623da0..000000000 --- a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_030.out +++ /dev/null @@ -1,13 +0,0 @@ - - -[E13] Error: Main label `main` not found - ╭─[ assembly:8:14 ] - │ - 8 │ li t0, 10 - │ │ - │ ╰─ Consider adding a label called `main` to an instruction -───╯ - -Not executed -keyboard[0x0]:''; display[0x0]:''; - diff --git a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_030.s b/tests/arch/riscv/error/compiler/test_riscv_error_compiler_030.s index e69de29bb..4f8f3a5a4 100644 --- a/tests/arch/riscv/error/compiler/test_riscv_error_compiler_030.s +++ b/tests/arch/riscv/error/compiler/test_riscv_error_compiler_030.s @@ -0,0 +1,8 @@ + +# +# Creator (https://creatorsim.github.io/creator/) +# + +.text +main_: + li t0, 10 diff --git a/tests/unit/arch/simulator-test-utils.mts b/tests/unit/arch/simulator-test-utils.mts index 8933c2b23..651010265 100644 --- a/tests/unit/arch/simulator-test-utils.mts +++ b/tests/unit/arch/simulator-test-utils.mts @@ -24,6 +24,7 @@ export interface ArchResult { export interface CompileResult { status: string; msg?: string; + linter?: { errorText: string, line: number, column: number } } export interface ExecutionResult { @@ -147,17 +148,15 @@ export async function compileAssembly( testAssembly: string, assembler: string = "default", ): Promise { - const compilerKey = assembler || "default"; - - if (!isValidCompilerKey(compilerKey)) { + if (!isValidCompilerKey(assembler)) { throw new Error( - `Invalid assembler: ${compilerKey}. Valid options are: ${Object.keys(compiler_map).join(", ")}`, + `Invalid assembler: ${assembler}. Valid options are: ${Object.keys(compiler_map).join(", ")}`, ); } creator.reset(); - const compilerFunction = compiler_map[compilerKey]; + const compilerFunction = compiler_map[assembler]; // Compile assembly code const compileResult = (await creator.assembly_compile( testAssembly, From 9afb5923b44b519fad9c4d03ca962aa6412c3ab3 Mon Sep 17 00:00:00 2001 From: ALVAROPING1 Date: Wed, 18 Mar 2026 21:13:06 +0100 Subject: [PATCH 39/85] refactor(sentinel): remove unnecessary type conversions --- src/core/sentinel/sentinel.mjs | 81 +++++++--------------------------- 1 file changed, 15 insertions(+), 66 deletions(-) diff --git a/src/core/sentinel/sentinel.mjs b/src/core/sentinel/sentinel.mjs index 52eadac62..f5b3a012c 100644 --- a/src/core/sentinel/sentinel.mjs +++ b/src/core/sentinel/sentinel.mjs @@ -30,46 +30,6 @@ const EventType = { READ_REGISTER: "read_register", }; -// Helpers for safe BigInt conversions and comparisons -function toBigIntSafe(v) { - if (v === null || typeof v === "undefined") return null; - if (typeof v === "bigint") return v; - if (typeof v === "number") { - if (!Number.isInteger(v)) return null; - return BigInt(v); - } - // strings and other types that BigInt accepts - try { - return BigInt(v); - } catch (_e) { - return null; - } -} - -function bigintsEqual(a, b) { - const A = toBigIntSafe(a); - const B = toBigIntSafe(b); - if (A === null || B === null) return false; - return A === B; -} - -function valuesEqual(a, b) { - // Handle null/undefined - if (a === null || a === undefined || b === null || b === undefined) { - return a === b; - } - - // Try BigInt comparison first - const A = toBigIntSafe(a); - const B = toBigIntSafe(b); - if (A !== null && B !== null) { - return A === B; - } - - // Fallback to strict equality - return a === b; -} - /** * Represents a single event in the register lifecycle */ @@ -78,9 +38,8 @@ class RegisterEvent { this.type = type; this.regIndex = regIndex; this.elemIndex = elemIndex; - // Normalize address/size to BigInt when possible to avoid mixed-type comparisons - this.address = toBigIntSafe(address); - this.size = toBigIntSafe(size); + this.address = address; + this.size = size; this.timestamp = Date.now(); } @@ -214,9 +173,9 @@ class ConventionRules { } if (firstSave && lastRestore) { - if (!bigintsEqual(firstSave.address, lastRestore.address)) { - const saveAddr = toBigIntSafe(firstSave.address); - const restoreAddr = toBigIntSafe(lastRestore.address); + if (firstSave.address !== lastRestore.address) { + const saveAddr = firstSave.address; + const restoreAddr = lastRestore.address; const saveStr = saveAddr !== null ? `0x${saveAddr.toString(16)}` @@ -235,17 +194,13 @@ class ConventionRules { // Rule 3: Save and restore sizes must match if (firstSave && lastRestore) { - const s1 = toBigIntSafe(firstSave.size); - const s2 = toBigIntSafe(lastRestore.size); - if (s1 === null || s2 === null || s1 !== s2) { - const s1Str = - s1 !== null ? s1.toString() : String(firstSave.size); - const s2Str = - s2 !== null ? s2.toString() : String(lastRestore.size); + const s1 = firstSave.size; + const s2 = lastRestore.size; + if (s1 !== s2) { violations.push({ rule: "SIZE_MISMATCH", register: register.name, - message: `Register ${register.name} saved with ${s1Str} bytes but restored with ${s2Str} bytes`, + message: `Register ${register.name} saved with ${s1} bytes but restored with ${s2} bytes`, }); } } @@ -254,7 +209,7 @@ class ConventionRules { const currentValue = REGISTERS[regIndex].elements[elemIndex].value; const initialValue = frame.initialRegisterValues[regIndex]?.[elemIndex]; - const valueChanged = !valuesEqual(currentValue, initialValue); + const valueChanged = currentValue !== initialValue; if (valueChanged && modifications.length > 0) { violations.push({ @@ -271,17 +226,11 @@ class ConventionRules { * Check stack pointer restoration */ static validateStackPointer(frame, currentStackPointer) { - const spEnter = toBigIntSafe(frame.enterStackPointer); - const spNow = toBigIntSafe(currentStackPointer); - if (spEnter === null || spNow === null || spEnter !== spNow) { - const enterStr = - spEnter !== null - ? `0x${spEnter.toString(16)}` - : String(frame.enterStackPointer); - const nowStr = - spNow !== null - ? `0x${spNow.toString(16)}` - : String(currentStackPointer); + const spEnter = frame.enterStackPointer; + const spNow = currentStackPointer; + if (spEnter !== spNow) { + const enterStr = `0x${spEnter.toString(16)}`; + const nowStr = `0x${spNow.toString(16)}`; return [ { rule: "STACK_NOT_RESTORED", From 9bdc68ac84ca585a77e49ccd024881b08bbb2870 Mon Sep 17 00:00:00 2001 From: ALVAROPING1 Date: Wed, 18 Mar 2026 23:30:56 +0100 Subject: [PATCH 40/85] refactor(sentinel): return error data as an object instead of a string Removes dumb stringify => parse string flow in the web UI --- src/cli/validator.mts | 16 ++-- src/core/capi/stack.mts | 11 +-- src/core/events.mts | 16 +++- src/core/sentinel/sentinel.mjs | 38 ++++++---- src/web/components/general/NavbarCREATOR.vue | 14 +--- .../mobile/MobileInstructionsView.vue | 18 ++--- .../simulator/SentinelErrorsDropdown.vue | 73 ++++--------------- tests/arch/arch_utils.mts | 10 ++- 8 files changed, 75 insertions(+), 121 deletions(-) diff --git a/src/cli/validator.mts b/src/cli/validator.mts index 219b5623c..ee9aa3c11 100644 --- a/src/cli/validator.mts +++ b/src/cli/validator.mts @@ -23,7 +23,8 @@ import { crex_findReg } from "../../src/core/register/registerLookup.mjs"; import { readRegister } from "../../src/core/register/registerOperations.mjs"; import { raise } from "@/core/capi/validation.mts"; import { ARCH as RISCV } from "@/core/capi/arch/riscv.mjs"; -import { coreEvents, CoreEventTypes } from "@/core/events.mts"; +import { sentinel as sentinelApi } from "@/core/sentinel/sentinel.mjs"; +import { coreEvents, CoreEventTypes, type SentinelErrorEvent } from "@/core/events.mts"; interface ExpectedState { registers?: { [name: string]: number }; @@ -58,11 +59,6 @@ export function executeN(n: number): { error: boolean; msg: string } { return ret; } -interface SentinelEvent { - functionName: string; - message: string; - ok: boolean; -} /** * Validates the execution of a program. @@ -79,9 +75,9 @@ export function validate( sentinel: boolean = true, ): { error: boolean; msg: string } { // subscribe to sentinel events - const sentinelErrors: SentinelEvent[] = []; - coreEvents.on(CoreEventTypes.SENTINEL_ERROR, (event: unknown) => { - sentinelErrors.push(event as SentinelEvent); + const sentinelErrors: SentinelErrorEvent[] = []; + coreEvents.on(CoreEventTypes.SENTINEL_ERROR, event => { + sentinelErrors.push(event); }); // execute program @@ -177,7 +173,7 @@ export function validate( error: true, msg: `Found ${sentinelErrors.length} sentinel errors:\n` + - sentinelErrors.map(e => e.message).join("\n"), + sentinelErrors.map(sentinelApi.formatErrors).join("\n"), }; } diff --git a/src/core/capi/stack.mts b/src/core/capi/stack.mts index c8a8cc7d3..6982c0fd6 100644 --- a/src/core/capi/stack.mts +++ b/src/core/capi/stack.mts @@ -55,9 +55,6 @@ export const STACK = { return; } - // get function name - const currentFunction = sentinel.getCurrentFunction() || "unknown"; - const ret = sentinel.leave(); if (ret.ok) { @@ -65,17 +62,13 @@ export const STACK = { } // emit event for GUI - coreEvents.emit(CoreEventTypes.SENTINEL_ERROR, { - functionName: currentFunction, - message: ret.msg, - ok: false, - }); + coreEvents.emit(CoreEventTypes.SENTINEL_ERROR, ret); // Google Analytics creator_ga( "execute", "execute.exception", - "execute.exception.protection_jrra" + ret.msg, + "execute.exception.protection_jrra", ); }, diff --git a/src/core/events.mts b/src/core/events.mts index 6b8d4ba78..99a4475a2 100644 --- a/src/core/events.mts +++ b/src/core/events.mts @@ -51,14 +51,26 @@ export interface RegisterUpdatedEvent { indexElem: number; } +/** + * Calling convention violation information + */ +export interface SentinelErrorData { + /** ID of the rule broken */ + rule: string, + /** Register in which the rule was broken, if applicable */ + register?: string[], + /** Full error message */ + message: string +} + /** * Emitted when calling convention violations are detected */ export interface SentinelErrorEvent { /** Name of the function that had violations */ functionName: string; - /** Full error message */ - message: string; + /** Violations found on the function */ + errors: SentinelErrorData[]; /** Whether the check passed (always false for error events) */ ok: boolean; } diff --git a/src/core/sentinel/sentinel.mjs b/src/core/sentinel/sentinel.mjs index f5b3a012c..c656e34f1 100644 --- a/src/core/sentinel/sentinel.mjs +++ b/src/core/sentinel/sentinel.mjs @@ -258,7 +258,6 @@ class CallingConventionValidator { const frame = new CallFrame(functionName, stackPointer); this.callStack.push(frame); console_log(`[SENTINEL] Entering function: ${functionName}`, "INFO"); - return { ok: true, msg: "" }; } /** @@ -268,7 +267,13 @@ class CallingConventionValidator { if (this.callStack.length === 0) { return { ok: false, - msg: "Cannot leave function: call stack is empty", + functionName: "unknown", + errors: [ + { + rule: "", + message: "Cannot leave function: call stack is empty", + }, + ], }; } @@ -278,14 +283,14 @@ class CallingConventionValidator { "INFO", ); - const violations = []; + const errors = []; // Validate stack pointer const spViolations = ConventionRules.validateStackPointer( frame, architecture.memory_layout.stack.start, ); - violations.push(...spViolations); + errors.push(...spViolations); // Validate each saved register for (let i = 0; i < REGISTERS.length; i++) { @@ -299,7 +304,7 @@ class CallingConventionValidator { i, j, ); - violations.push(...regViolations); + errors.push(...regViolations); } } } @@ -307,16 +312,11 @@ class CallingConventionValidator { // Pop the frame this.callStack.pop(); - // Return result - if (violations.length > 0) { - const messages = violations.map(v => ` - ${v.message}`).join("\n"); - return { - ok: false, - msg: `Calling convention violations in ${frame.functionName}:\n${messages}`, - }; - } - - return { ok: true, msg: "" }; + return { + ok: errors.length === 0, + functionName: frame.functionName, + errors, + }; } /** @@ -405,7 +405,6 @@ class CallingConventionValidator { reset() { this.callStack = []; this.enter("main"); - return { ok: true, msg: "" }; } /** @@ -445,4 +444,11 @@ export const sentinel = { reset: () => validator.reset(), getCallDepth: () => validator.getCallDepth(), getCurrentFunction: () => validator.getCurrentFunction(), + /** @type {(frameResult: import("../events.mts").SentinelErrorEvent) => string} */ + formatErrors: frameResult => { + const messages = frameResult.errors + .map(v => ` - ${v.message}`) + .join("\n"); + return `Calling convention violations in ${frameResult.functionName}:\n${messages}`; + }, }; diff --git a/src/web/components/general/NavbarCREATOR.vue b/src/web/components/general/NavbarCREATOR.vue index 1f138f757..f546180bd 100644 --- a/src/web/components/general/NavbarCREATOR.vue +++ b/src/web/components/general/NavbarCREATOR.vue @@ -32,7 +32,7 @@ import SentinelErrorsDropdown from "../simulator/SentinelErrorsDropdown.vue"; import ThemeToggle from "./ThemeToggle.vue"; import type { Instruction } from "@/core/assembler/assembler"; import type { BDropdown } from "bootstrap-vue-next"; -import { coreEvents, CoreEventTypes } from "../../../core/events.mts"; +import { coreEvents, CoreEventTypes, type SentinelErrorEvent } from "../../../core/events.mts"; import { remove_library, architecture, load_CREATino } from "@/core/core.mjs"; import { createFile } from "../assembly/MultifileEditor.mjs"; @@ -67,17 +67,9 @@ export default defineComponent({ typeof SentinelErrorsDropdown > | null>(null); - const handleSentinelError = (event: unknown) => { - const errorEvent = event as { - functionName: string; - message: string; - ok: boolean; - }; + const handleSentinelError = (event: SentinelErrorEvent) => { if (sentinelDropdownRef.value) { - sentinelDropdownRef.value.checkForErrors( - { ok: errorEvent.ok, msg: errorEvent.message }, - errorEvent.functionName, - ); + sentinelDropdownRef.value.checkForErrors(event); } }; diff --git a/src/web/components/mobile/MobileInstructionsView.vue b/src/web/components/mobile/MobileInstructionsView.vue index 499014cb2..7911c89fe 100644 --- a/src/web/components/mobile/MobileInstructionsView.vue +++ b/src/web/components/mobile/MobileInstructionsView.vue @@ -28,7 +28,11 @@ import TableExecution from "@/web/components/simulator/TableExecution.vue"; import SimulatorControls from "@/web/components/simulator/SimulatorControls.vue"; import SentinelErrorsDropdown from "@/web/components/simulator/SentinelErrorsDropdown.vue"; import type { Instruction } from "@/core/assembler/assembler"; -import { coreEvents, CoreEventTypes } from "../../../core/events.mts"; +import { + coreEvents, + CoreEventTypes, + type SentinelErrorEvent, +} from "../../../core/events.mts"; export default defineComponent({ props: { @@ -52,17 +56,9 @@ export default defineComponent({ typeof SentinelErrorsDropdown > | null>(null); - const handleSentinelError = (event: unknown) => { - const errorEvent = event as { - functionName: string; - message: string; - ok: boolean; - }; + const handleSentinelError = (event: SentinelErrorEvent) => { if (sentinelDropdownRef.value) { - sentinelDropdownRef.value.checkForErrors( - { ok: errorEvent.ok, msg: errorEvent.message }, - errorEvent.functionName, - ); + sentinelDropdownRef.value.checkForErrors(event); } }; diff --git a/src/web/components/simulator/SentinelErrorsDropdown.vue b/src/web/components/simulator/SentinelErrorsDropdown.vue index b980eff3a..1052b340d 100644 --- a/src/web/components/simulator/SentinelErrorsDropdown.vue +++ b/src/web/components/simulator/SentinelErrorsDropdown.vue @@ -20,16 +20,16 @@ along with CREATOR. If not, see . @@ -174,6 +209,19 @@ export default defineComponent({ Cache Memory + + + @@ -222,6 +270,36 @@ export default defineComponent({ :cache_policy="$root.$data.cache_policy" > + + This validation test runs {{(architecture.config.name === 'SRV32' ? 89 : 122)}} RISC-V programs.
+ These programs are taken from the official RISC-V test repository (riscv-tests), where the correct operation
+ of the full instruction set of the RISC-V specification is verified. +

+ + + + Run tests + + + +
+
+ + + + + + + diff --git a/src/web/components/simulator/SimulatorControls.vue b/src/web/components/simulator/SimulatorControls.vue index 51c2d4135..0f8a6e898 100644 --- a/src/web/components/simulator/SimulatorControls.vue +++ b/src/web/components/simulator/SimulatorControls.vue @@ -302,7 +302,7 @@ function execute_instruction() { } else if (document.app.$data.execution_mode_run === -1) { document.app.$data.execution_mode_run = 1; status.run_program = 1; - SailExecute(document.app.$data.binary, ["--entry-address", /*"0x80000000"*/ document.app.$data.entry_elf.toString(16), "--disable-compressed", "--cache-pol", "1", "-p", "output.elf"]); + SailExecute(document.app.$data.binary, ["--entry-address", document.app.$data.entry_elf.toString(16), "--cache-pol", "1", "-p", "output.elf"]); // console.log("Ejecutado"); } else if (document.app.$data.execution_mode_run !== -1 && document.app.$data.execution_mode_run !== 2){ document.app.$data.execution_mode_run = 1; @@ -413,7 +413,7 @@ function execute_program_packed() { } else if (document.app.$data.execution_mode_run === -1){ status.run_program = 1; document.app.$data.execution_mode_run = 0; - SailExecute(document.app.$data.binary, ["--entry-address", /*"0x80000000"*/ document.app.$data.entry_elf.toString(16), "--disable-compressed", "--cache-pol", "1", "-p", "output.elf"]); + SailExecute(document.app.$data.binary, ["--entry-address", document.app.$data.entry_elf.toString(16), "--cache-pol", "1", "-p", "output.elf"]); } else if (document.app.$data.execution_mode_run !== -1 && document.app.$data.execution_mode_run !== 2){ document.app.$data.execution_mode_run = 0; sailexec._reanudar_ejecucion(parseInt(0,10)); From 59af2d8c1e9b8c78ca5951957f6b705070b6db51 Mon Sep 17 00:00:00 2001 From: Juan Carlos Date: Mon, 23 Mar 2026 13:37:55 +0100 Subject: [PATCH 65/85] upload validation sail tests --- examples/RISCV-32-Sail-Validation/list.json | 536 ++++++++++++++++++ .../rv32mi-p-breakpoint.elf | Bin 0 -> 13148 bytes .../RISCV-32-Sail-Validation/rv32mi-p-csr.elf | Bin 0 -> 13436 bytes .../rv32mi-p-illegal.elf | Bin 0 -> 9272 bytes .../rv32mi-p-ma_addr.elf | Bin 0 -> 13380 bytes .../rv32mi-p-ma_fetch.elf | Bin 0 -> 9004 bytes .../rv32mi-p-mcsr.elf | Bin 0 -> 9020 bytes .../rv32mi-p-sbreak.elf | Bin 0 -> 9028 bytes .../rv32mi-p-scall.elf | Bin 0 -> 9028 bytes .../rv32mi-p-shamt.elf | Bin 0 -> 9048 bytes .../RISCV-32-Sail-Validation/rv32si-p-csr.elf | Bin 0 -> 13388 bytes .../rv32si-p-dirty.elf | Bin 0 -> 13196 bytes .../rv32si-p-ma_fetch.elf | Bin 0 -> 9004 bytes .../rv32si-p-sbreak.elf | Bin 0 -> 9028 bytes .../rv32si-p-scall.elf | Bin 0 -> 9028 bytes .../RISCV-32-Sail-Validation/rv32si-p-wfi.elf | Bin 0 -> 8972 bytes .../rv32ua-p-amoadd_w.elf | Bin 0 -> 9152 bytes .../rv32ua-p-amoand_w.elf | Bin 0 -> 9152 bytes .../rv32ua-p-amomax_w.elf | Bin 0 -> 9152 bytes .../rv32ua-p-amomaxu_w.elf | Bin 0 -> 9152 bytes .../rv32ua-p-amomin_w.elf | Bin 0 -> 9152 bytes .../rv32ua-p-amominu_w.elf | Bin 0 -> 9152 bytes .../rv32ua-p-amoor_w.elf | Bin 0 -> 9152 bytes .../rv32ua-p-amoswap_w.elf | Bin 0 -> 9152 bytes .../rv32ua-p-amoxor_w.elf | Bin 0 -> 9152 bytes .../rv32ua-p-lrsc.elf | Bin 0 -> 14304 bytes .../RISCV-32-Sail-Validation/rv32uc-p-rvc.elf | Bin 0 -> 17780 bytes .../rv32ud-p-fadd.elf | Bin 0 -> 13892 bytes .../rv32ud-p-fclass.elf | Bin 0 -> 13652 bytes .../rv32ud-p-fcmp.elf | Bin 0 -> 14316 bytes .../rv32ud-p-fcvt.elf | Bin 0 -> 13564 bytes .../rv32ud-p-fcvt_w.elf | Bin 0 -> 14432 bytes .../rv32ud-p-fdiv.elf | Bin 0 -> 13724 bytes .../rv32ud-p-fmadd.elf | Bin 0 -> 14064 bytes .../rv32ud-p-fmin.elf | Bin 0 -> 14576 bytes .../rv32uf-p-fadd.elf | Bin 0 -> 13732 bytes .../rv32uf-p-fclass.elf | Bin 0 -> 9204 bytes .../rv32uf-p-fcmp.elf | Bin 0 -> 14076 bytes .../rv32uf-p-fcvt.elf | Bin 0 -> 13280 bytes .../rv32uf-p-fcvt_w.elf | Bin 0 -> 14432 bytes .../rv32uf-p-fdiv.elf | Bin 0 -> 13544 bytes .../rv32uf-p-fmadd.elf | Bin 0 -> 13872 bytes .../rv32uf-p-fmin.elf | Bin 0 -> 14288 bytes .../RISCV-32-Sail-Validation/rv32ui-p-add.elf | Bin 0 -> 9852 bytes .../rv32ui-p-addi.elf | Bin 0 -> 9540 bytes .../RISCV-32-Sail-Validation/rv32ui-p-and.elf | Bin 0 -> 9588 bytes .../rv32ui-p-andi.elf | Bin 0 -> 9276 bytes .../rv32ui-p-auipc.elf | Bin 0 -> 9020 bytes .../RISCV-32-Sail-Validation/rv32ui-p-beq.elf | Bin 0 -> 9444 bytes .../RISCV-32-Sail-Validation/rv32ui-p-bge.elf | Bin 0 -> 9516 bytes .../rv32ui-p-bgeu.elf | Bin 0 -> 9516 bytes .../RISCV-32-Sail-Validation/rv32ui-p-blt.elf | Bin 0 -> 9444 bytes .../rv32ui-p-bltu.elf | Bin 0 -> 9444 bytes .../RISCV-32-Sail-Validation/rv32ui-p-bne.elf | Bin 0 -> 9444 bytes .../rv32ui-p-fence_i.elf | Bin 0 -> 13140 bytes .../RISCV-32-Sail-Validation/rv32ui-p-jal.elf | Bin 0 -> 9072 bytes .../rv32ui-p-jalr.elf | Bin 0 -> 9140 bytes .../RISCV-32-Sail-Validation/rv32ui-p-lb.elf | Bin 0 -> 13608 bytes .../RISCV-32-Sail-Validation/rv32ui-p-lbu.elf | Bin 0 -> 13608 bytes .../RISCV-32-Sail-Validation/rv32ui-p-lh.elf | Bin 0 -> 13608 bytes .../RISCV-32-Sail-Validation/rv32ui-p-lhu.elf | Bin 0 -> 13608 bytes .../RISCV-32-Sail-Validation/rv32ui-p-lui.elf | Bin 0 -> 9088 bytes .../RISCV-32-Sail-Validation/rv32ui-p-lw.elf | Bin 0 -> 13608 bytes .../RISCV-32-Sail-Validation/rv32ui-p-or.elf | Bin 0 -> 9588 bytes .../RISCV-32-Sail-Validation/rv32ui-p-ori.elf | Bin 0 -> 9276 bytes .../RISCV-32-Sail-Validation/rv32ui-p-sb.elf | Bin 0 -> 13836 bytes .../RISCV-32-Sail-Validation/rv32ui-p-sh.elf | Bin 0 -> 13852 bytes .../rv32ui-p-simple.elf | Bin 0 -> 8932 bytes .../RISCV-32-Sail-Validation/rv32ui-p-sll.elf | Bin 0 -> 9948 bytes .../rv32ui-p-slli.elf | Bin 0 -> 9540 bytes .../RISCV-32-Sail-Validation/rv32ui-p-slt.elf | Bin 0 -> 9852 bytes .../rv32ui-p-slti.elf | Bin 0 -> 9540 bytes .../rv32ui-p-sltiu.elf | Bin 0 -> 9540 bytes .../rv32ui-p-sltu.elf | Bin 0 -> 9852 bytes .../RISCV-32-Sail-Validation/rv32ui-p-sra.elf | Bin 0 -> 9972 bytes .../rv32ui-p-srai.elf | Bin 0 -> 9540 bytes .../RISCV-32-Sail-Validation/rv32ui-p-srl.elf | Bin 0 -> 9972 bytes .../rv32ui-p-srli.elf | Bin 0 -> 9540 bytes .../RISCV-32-Sail-Validation/rv32ui-p-sub.elf | Bin 0 -> 9828 bytes .../RISCV-32-Sail-Validation/rv32ui-p-sw.elf | Bin 0 -> 13868 bytes .../RISCV-32-Sail-Validation/rv32ui-p-xor.elf | Bin 0 -> 9588 bytes .../rv32ui-p-xori.elf | Bin 0 -> 9276 bytes .../RISCV-32-Sail-Validation/rv32um-p-div.elf | Bin 0 -> 9180 bytes .../rv32um-p-divu.elf | Bin 0 -> 9180 bytes .../RISCV-32-Sail-Validation/rv32um-p-mul.elf | Bin 0 -> 9828 bytes .../rv32um-p-mulh.elf | Bin 0 -> 9780 bytes .../rv32um-p-mulhsu.elf | Bin 0 -> 9780 bytes .../rv32um-p-mulhu.elf | Bin 0 -> 9780 bytes .../RISCV-32-Sail-Validation/rv32um-p-rem.elf | Bin 0 -> 9180 bytes .../rv32um-p-remu.elf | Bin 0 -> 9180 bytes examples/RISCV-64-Sail-Validation/list.json | 490 ++++++++++++++++ .../rv64mi-p-access.elf | Bin 0 -> 9296 bytes .../rv64mi-p-breakpoint.elf | Bin 0 -> 13488 bytes .../RISCV-64-Sail-Validation/rv64mi-p-csr.elf | Bin 0 -> 13936 bytes .../rv64mi-p-illegal.elf | Bin 0 -> 9648 bytes .../rv64mi-p-ma_addr.elf | Bin 0 -> 13712 bytes .../rv64mi-p-ma_fetch.elf | Bin 0 -> 9296 bytes .../rv64mi-p-mcsr.elf | Bin 0 -> 9320 bytes .../rv64mi-p-sbreak.elf | Bin 0 -> 9328 bytes .../rv64mi-p-scall.elf | Bin 0 -> 9328 bytes .../RISCV-64-Sail-Validation/rv64si-p-csr.elf | Bin 0 -> 13840 bytes .../rv64si-p-dirty.elf | Bin 0 -> 13552 bytes .../rv64si-p-ma_fetch.elf | Bin 0 -> 9296 bytes .../rv64si-p-sbreak.elf | Bin 0 -> 9328 bytes .../rv64si-p-scall.elf | Bin 0 -> 9328 bytes .../RISCV-64-Sail-Validation/rv64si-p-wfi.elf | Bin 0 -> 9256 bytes .../rv64ua-p-amoadd_d.elf | Bin 0 -> 9504 bytes .../rv64ua-p-amoadd_w.elf | Bin 0 -> 9504 bytes .../rv64ua-p-amoand_d.elf | Bin 0 -> 9504 bytes .../rv64ua-p-amoand_w.elf | Bin 0 -> 9504 bytes .../rv64ua-p-amomax_d.elf | Bin 0 -> 9504 bytes .../rv64ua-p-amomax_w.elf | Bin 0 -> 9504 bytes .../rv64ua-p-amomaxu_d.elf | Bin 0 -> 9504 bytes .../rv64ua-p-amomaxu_w.elf | Bin 0 -> 9504 bytes .../rv64ua-p-amomin_d.elf | Bin 0 -> 9504 bytes .../rv64ua-p-amomin_w.elf | Bin 0 -> 9504 bytes .../rv64ua-p-amominu_d.elf | Bin 0 -> 9504 bytes .../rv64ua-p-amominu_w.elf | Bin 0 -> 9504 bytes .../rv64ua-p-amoor_d.elf | Bin 0 -> 9504 bytes .../rv64ua-p-amoor_w.elf | Bin 0 -> 9504 bytes .../rv64ua-p-amoswap_d.elf | Bin 0 -> 9504 bytes .../rv64ua-p-amoswap_w.elf | Bin 0 -> 9504 bytes .../rv64ua-p-amoxor_d.elf | Bin 0 -> 9504 bytes .../rv64ua-p-amoxor_w.elf | Bin 0 -> 9504 bytes .../rv64ua-p-lrsc.elf | Bin 0 -> 14688 bytes .../RISCV-64-Sail-Validation/rv64uc-p-rvc.elf | Bin 0 -> 18392 bytes .../rv64ud-p-fadd.elf | Bin 0 -> 14368 bytes .../rv64ud-p-fclass.elf | Bin 0 -> 9568 bytes .../rv64ud-p-fcmp.elf | Bin 0 -> 14872 bytes .../rv64ud-p-fcvt.elf | Bin 0 -> 14240 bytes .../rv64ud-p-fcvt_w.elf | Bin 0 -> 17408 bytes .../rv64ud-p-fdiv.elf | Bin 0 -> 14168 bytes .../rv64ud-p-fmadd.elf | Bin 0 -> 14568 bytes .../rv64ud-p-fmin.elf | Bin 0 -> 15176 bytes .../rv64ud-p-ldst.elf | Bin 0 -> 13592 bytes .../rv64ud-p-move.elf | Bin 0 -> 15032 bytes .../rv64ud-p-recoding.elf | Bin 0 -> 13800 bytes .../rv64ud-p-structural.elf | Bin 0 -> 9200 bytes .../rv64uf-p-fadd.elf | Bin 0 -> 14208 bytes .../rv64uf-p-fclass.elf | Bin 0 -> 9568 bytes .../rv64uf-p-fcmp.elf | Bin 0 -> 14632 bytes .../rv64uf-p-fcvt.elf | Bin 0 -> 13944 bytes .../rv64uf-p-fcvt_w.elf | Bin 0 -> 16440 bytes .../rv64uf-p-fdiv.elf | Bin 0 -> 13968 bytes .../rv64uf-p-fmadd.elf | Bin 0 -> 14376 bytes .../rv64uf-p-fmin.elf | Bin 0 -> 14888 bytes .../rv64uf-p-ldst.elf | Bin 0 -> 13496 bytes .../rv64uf-p-move.elf | Bin 0 -> 9856 bytes .../rv64uf-p-recoding.elf | Bin 0 -> 13632 bytes .../RISCV-64-Sail-Validation/rv64ui-p-add.elf | Bin 0 -> 10432 bytes .../rv64ui-p-addi.elf | Bin 0 -> 10016 bytes .../rv64ui-p-addiw.elf | Bin 0 -> 10016 bytes .../rv64ui-p-addw.elf | Bin 0 -> 10432 bytes .../RISCV-64-Sail-Validation/rv64ui-p-and.elf | Bin 0 -> 10080 bytes .../rv64ui-p-andi.elf | Bin 0 -> 9664 bytes .../rv64ui-p-auipc.elf | Bin 0 -> 9320 bytes .../RISCV-64-Sail-Validation/rv64ui-p-beq.elf | Bin 0 -> 9888 bytes .../RISCV-64-Sail-Validation/rv64ui-p-bge.elf | Bin 0 -> 9984 bytes .../rv64ui-p-bgeu.elf | Bin 0 -> 9984 bytes .../RISCV-64-Sail-Validation/rv64ui-p-blt.elf | Bin 0 -> 9888 bytes .../rv64ui-p-bltu.elf | Bin 0 -> 9888 bytes .../RISCV-64-Sail-Validation/rv64ui-p-bne.elf | Bin 0 -> 9888 bytes .../rv64ui-p-fence_i.elf | Bin 0 -> 13480 bytes .../RISCV-64-Sail-Validation/rv64ui-p-jal.elf | Bin 0 -> 9384 bytes .../rv64ui-p-jalr.elf | Bin 0 -> 9480 bytes .../RISCV-64-Sail-Validation/rv64ui-p-lb.elf | Bin 0 -> 14104 bytes .../RISCV-64-Sail-Validation/rv64ui-p-lbu.elf | Bin 0 -> 14104 bytes .../RISCV-64-Sail-Validation/rv64ui-p-ld.elf | Bin 0 -> 14120 bytes .../RISCV-64-Sail-Validation/rv64ui-p-lh.elf | Bin 0 -> 14104 bytes .../RISCV-64-Sail-Validation/rv64ui-p-lhu.elf | Bin 0 -> 14104 bytes .../RISCV-64-Sail-Validation/rv64ui-p-lui.elf | Bin 0 -> 9408 bytes .../RISCV-64-Sail-Validation/rv64ui-p-lw.elf | Bin 0 -> 14104 bytes .../RISCV-64-Sail-Validation/rv64ui-p-lwu.elf | Bin 0 -> 14104 bytes .../RISCV-64-Sail-Validation/rv64ui-p-or.elf | Bin 0 -> 10080 bytes .../RISCV-64-Sail-Validation/rv64ui-p-ori.elf | Bin 0 -> 9664 bytes .../RISCV-64-Sail-Validation/rv64ui-p-sb.elf | Bin 0 -> 14416 bytes .../RISCV-64-Sail-Validation/rv64ui-p-sd.elf | Bin 0 -> 14480 bytes .../RISCV-64-Sail-Validation/rv64ui-p-sh.elf | Bin 0 -> 14432 bytes .../rv64ui-p-simple.elf | Bin 0 -> 9200 bytes .../RISCV-64-Sail-Validation/rv64ui-p-sll.elf | Bin 0 -> 10688 bytes .../rv64ui-p-slli.elf | Bin 0 -> 10112 bytes .../rv64ui-p-slliw.elf | Bin 0 -> 10144 bytes .../rv64ui-p-sllw.elf | Bin 0 -> 10720 bytes .../RISCV-64-Sail-Validation/rv64ui-p-slt.elf | Bin 0 -> 10432 bytes .../rv64ui-p-slti.elf | Bin 0 -> 10016 bytes .../rv64ui-p-sltiu.elf | Bin 0 -> 10016 bytes .../rv64ui-p-sltu.elf | Bin 0 -> 10432 bytes .../RISCV-64-Sail-Validation/rv64ui-p-sra.elf | Bin 0 -> 10592 bytes .../rv64ui-p-srai.elf | Bin 0 -> 10016 bytes .../rv64ui-p-sraiw.elf | Bin 0 -> 10208 bytes .../rv64ui-p-sraw.elf | Bin 0 -> 10720 bytes .../RISCV-64-Sail-Validation/rv64ui-p-srl.elf | Bin 0 -> 10592 bytes .../rv64ui-p-srli.elf | Bin 0 -> 10016 bytes .../rv64ui-p-srliw.elf | Bin 0 -> 10144 bytes .../rv64ui-p-srlw.elf | Bin 0 -> 10720 bytes .../RISCV-64-Sail-Validation/rv64ui-p-sub.elf | Bin 0 -> 10400 bytes .../rv64ui-p-subw.elf | Bin 0 -> 10400 bytes .../RISCV-64-Sail-Validation/rv64ui-p-sw.elf | Bin 0 -> 14448 bytes .../RISCV-64-Sail-Validation/rv64ui-p-xor.elf | Bin 0 -> 10080 bytes .../rv64ui-p-xori.elf | Bin 0 -> 9664 bytes .../RISCV-64-Sail-Validation/rv64um-p-div.elf | Bin 0 -> 9536 bytes .../rv64um-p-divu.elf | Bin 0 -> 9536 bytes .../rv64um-p-divuw.elf | Bin 0 -> 9536 bytes .../rv64um-p-divw.elf | Bin 0 -> 9536 bytes .../RISCV-64-Sail-Validation/rv64um-p-mul.elf | Bin 0 -> 10272 bytes .../rv64um-p-mulh.elf | Bin 0 -> 10144 bytes .../rv64um-p-mulhsu.elf | Bin 0 -> 10144 bytes .../rv64um-p-mulhu.elf | Bin 0 -> 10208 bytes .../rv64um-p-mulw.elf | Bin 0 -> 10144 bytes .../RISCV-64-Sail-Validation/rv64um-p-rem.elf | Bin 0 -> 9536 bytes .../rv64um-p-remu.elf | Bin 0 -> 9536 bytes .../rv64um-p-remuw.elf | Bin 0 -> 9536 bytes .../rv64um-p-remw.elf | Bin 0 -> 9568 bytes 213 files changed, 1026 insertions(+) create mode 100644 examples/RISCV-32-Sail-Validation/list.json create mode 100644 examples/RISCV-32-Sail-Validation/rv32mi-p-breakpoint.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32mi-p-csr.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32mi-p-illegal.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32mi-p-ma_addr.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32mi-p-ma_fetch.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32mi-p-mcsr.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32mi-p-sbreak.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32mi-p-scall.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32mi-p-shamt.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32si-p-csr.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32si-p-dirty.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32si-p-ma_fetch.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32si-p-sbreak.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32si-p-scall.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32si-p-wfi.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32ua-p-amoadd_w.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32ua-p-amoand_w.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32ua-p-amomax_w.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32ua-p-amomaxu_w.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32ua-p-amomin_w.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32ua-p-amominu_w.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32ua-p-amoor_w.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32ua-p-amoswap_w.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32ua-p-amoxor_w.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32ua-p-lrsc.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32uc-p-rvc.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32ud-p-fadd.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32ud-p-fclass.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32ud-p-fcmp.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32ud-p-fcvt.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32ud-p-fcvt_w.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32ud-p-fdiv.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32ud-p-fmadd.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32ud-p-fmin.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32uf-p-fadd.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32uf-p-fclass.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32uf-p-fcmp.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32uf-p-fcvt.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32uf-p-fcvt_w.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32uf-p-fdiv.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32uf-p-fmadd.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32uf-p-fmin.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32ui-p-add.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32ui-p-addi.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32ui-p-and.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32ui-p-andi.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32ui-p-auipc.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32ui-p-beq.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32ui-p-bge.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32ui-p-bgeu.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32ui-p-blt.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32ui-p-bltu.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32ui-p-bne.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32ui-p-fence_i.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32ui-p-jal.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32ui-p-jalr.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32ui-p-lb.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32ui-p-lbu.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32ui-p-lh.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32ui-p-lhu.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32ui-p-lui.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32ui-p-lw.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32ui-p-or.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32ui-p-ori.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32ui-p-sb.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32ui-p-sh.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32ui-p-simple.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32ui-p-sll.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32ui-p-slli.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32ui-p-slt.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32ui-p-slti.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32ui-p-sltiu.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32ui-p-sltu.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32ui-p-sra.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32ui-p-srai.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32ui-p-srl.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32ui-p-srli.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32ui-p-sub.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32ui-p-sw.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32ui-p-xor.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32ui-p-xori.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32um-p-div.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32um-p-divu.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32um-p-mul.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32um-p-mulh.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32um-p-mulhsu.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32um-p-mulhu.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32um-p-rem.elf create mode 100644 examples/RISCV-32-Sail-Validation/rv32um-p-remu.elf create mode 100644 examples/RISCV-64-Sail-Validation/list.json create mode 100755 examples/RISCV-64-Sail-Validation/rv64mi-p-access.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64mi-p-breakpoint.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64mi-p-csr.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64mi-p-illegal.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64mi-p-ma_addr.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64mi-p-ma_fetch.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64mi-p-mcsr.elf create mode 100755 examples/RISCV-64-Sail-Validation/rv64mi-p-sbreak.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64mi-p-scall.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64si-p-csr.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64si-p-dirty.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64si-p-ma_fetch.elf create mode 100755 examples/RISCV-64-Sail-Validation/rv64si-p-sbreak.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64si-p-scall.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64si-p-wfi.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ua-p-amoadd_d.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ua-p-amoadd_w.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ua-p-amoand_d.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ua-p-amoand_w.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ua-p-amomax_d.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ua-p-amomax_w.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ua-p-amomaxu_d.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ua-p-amomaxu_w.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ua-p-amomin_d.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ua-p-amomin_w.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ua-p-amominu_d.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ua-p-amominu_w.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ua-p-amoor_d.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ua-p-amoor_w.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ua-p-amoswap_d.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ua-p-amoswap_w.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ua-p-amoxor_d.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ua-p-amoxor_w.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ua-p-lrsc.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64uc-p-rvc.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ud-p-fadd.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ud-p-fclass.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ud-p-fcmp.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ud-p-fcvt.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ud-p-fcvt_w.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ud-p-fdiv.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ud-p-fmadd.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ud-p-fmin.elf create mode 100755 examples/RISCV-64-Sail-Validation/rv64ud-p-ldst.elf create mode 100755 examples/RISCV-64-Sail-Validation/rv64ud-p-move.elf create mode 100755 examples/RISCV-64-Sail-Validation/rv64ud-p-recoding.elf create mode 100755 examples/RISCV-64-Sail-Validation/rv64ud-p-structural.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64uf-p-fadd.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64uf-p-fclass.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64uf-p-fcmp.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64uf-p-fcvt.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64uf-p-fcvt_w.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64uf-p-fdiv.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64uf-p-fmadd.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64uf-p-fmin.elf create mode 100755 examples/RISCV-64-Sail-Validation/rv64uf-p-ldst.elf create mode 100755 examples/RISCV-64-Sail-Validation/rv64uf-p-move.elf create mode 100755 examples/RISCV-64-Sail-Validation/rv64uf-p-recoding.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ui-p-add.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ui-p-addi.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ui-p-addiw.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ui-p-addw.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ui-p-and.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ui-p-andi.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ui-p-auipc.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ui-p-beq.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ui-p-bge.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ui-p-bgeu.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ui-p-blt.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ui-p-bltu.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ui-p-bne.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ui-p-fence_i.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ui-p-jal.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ui-p-jalr.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ui-p-lb.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ui-p-lbu.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ui-p-ld.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ui-p-lh.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ui-p-lhu.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ui-p-lui.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ui-p-lw.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ui-p-lwu.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ui-p-or.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ui-p-ori.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ui-p-sb.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ui-p-sd.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ui-p-sh.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ui-p-simple.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ui-p-sll.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ui-p-slli.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ui-p-slliw.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ui-p-sllw.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ui-p-slt.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ui-p-slti.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ui-p-sltiu.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ui-p-sltu.elf create mode 100644 examples/RISCV-64-Sail-Validation/rv64ui-p-sra.elf create mode 100644 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+
{{ result_log }}
From d905445eb60c1a4f56df3e8140138ef713785163 Mon Sep 17 00:00:00 2001 From: Juan Carlos Date: Fri, 27 Mar 2026 17:37:39 +0100 Subject: [PATCH 81/85] fix Sail validation and ui instruction --- .../assembler/sailAssembler/web/CNAssambler.mjs | 4 ++-- src/core/executor/sailSimRV/sailExecutor.mjs | 4 ++-- src/web/components/ArchitectureView.vue | 15 ++++++++++++--- 3 files changed, 16 insertions(+), 7 deletions(-) diff --git a/src/core/assembler/sailAssembler/web/CNAssambler.mjs b/src/core/assembler/sailAssembler/web/CNAssambler.mjs index 81c969991..d0a8ad000 100644 --- a/src/core/assembler/sailAssembler/web/CNAssambler.mjs +++ b/src/core/assembler/sailAssembler/web/CNAssambler.mjs @@ -897,7 +897,7 @@ export async function dump(file){ instructions.push({ Break: null, Address: "0x" + dumptextinstructions32[i][0], - Label: dumptextinstructions32[i][4], + Label: [dumptextinstructions32[i][4]], loaded: dumptextinstructions32[i][2], user : list_user_instructions[i], L1_I: 0, @@ -959,7 +959,7 @@ export async function dump(file){ instructions.push({ Break: null, Address: "0x" + dumptextinstructions64[i][0], - Label: dumptextinstructions64[i][4], + Label: [dumptextinstructions64[i][4]], loaded: dumptextinstructions64[i][2], user : list_user_instructions[i], L1_I: 0, diff --git a/src/core/executor/sailSimRV/sailExecutor.mjs b/src/core/executor/sailSimRV/sailExecutor.mjs index 7d9b96476..2720d63ee 100644 --- a/src/core/executor/sailSimRV/sailExecutor.mjs +++ b/src/core/executor/sailSimRV/sailExecutor.mjs @@ -64,7 +64,7 @@ export async function SailTest32(){ document.app.$data.testing = true; document.app.$data.c_kernel = false; if (programs.length === 0) - programs = await cargarProgramas32("../../../../examples/RISCV-32-Sail-Validation/list.json"); + programs = await cargarProgramas32("examples/RISCV-32-Sail-Validation/list.json"); for (let index = 0; index < programs.length; index++) { @@ -119,7 +119,7 @@ export async function SailTest64(){ document.app.$data.testing = true; document.app.$data.c_kernel = false; if (programs.length === 0) - programs = await cargarProgramas64("../../../../examples/RISCV-64-Sail-Validation/list.json"); + programs = await cargarProgramas64("examples/RISCV-64-Sail-Validation/list.json"); for (let index = 0; index < programs.length; index++) { diff --git a/src/web/components/ArchitectureView.vue b/src/web/components/ArchitectureView.vue index b051cb082..2eb25c016 100644 --- a/src/web/components/ArchitectureView.vue +++ b/src/web/components/ArchitectureView.vue @@ -94,10 +94,19 @@ export default defineComponent({ updateState(){ this.result_test = document.app.$data.passed_test; if (this.result_test + document.app.$data.failed_test === ((architecture.config.name === 'SRV32' ? 89 : 122)) ){ - this.result_log = "Validation completed.
Your architecture passed the " + (this.result_test / (architecture.config.name === 'SRV32' ? 89 : 122)) * 100 + "%
of the validation tests." + this.result_log = "Validation completed.\n Your architecture passed the " + (this.result_test / (architecture.config.name === 'SRV32' ? 89 : 122)) * 100 + "%\n of the validation tests."; } }, + resetValidationState(){ + this.runned = 0; + this.result_test = 0; + this.running = true; + this.result_log = ""; + document.app.$data.passed_test = 0; + document.app.$data.failed_test = 0; + document.app.$data.testing = false; + }, }, mounted(){ coreEvents.on("update-validation", this.updateState); @@ -273,7 +282,7 @@ export default defineComponent({ + @ok="resetValidationState"> This validation test runs {{(architecture.config.name === 'SRV32' ? 89 : 122)}} RISC-V programs.
These programs are taken from the official RISC-V test repository (riscv-tests), where the correct operation
of the full instruction set of the RISC-V specification is verified. @@ -292,7 +301,7 @@ export default defineComponent({ :max="architecture.config.name === 'SRV32' ? 89 : 122" >
-
{{ result_log }}
+
{{ result_log }}
From def28d976ab09c93f0235207f471629d28e3f2b9 Mon Sep 17 00:00:00 2001 From: ALVAROPING1 Date: Tue, 7 Apr 2026 11:17:49 +0200 Subject: [PATCH 82/85] fix(IO): remove unnecessary writeRegister on main keyboard read function --- src/core/executor/IO.mjs | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/core/executor/IO.mjs b/src/core/executor/IO.mjs index 0ee8aa44a..e57732422 100644 --- a/src/core/executor/IO.mjs +++ b/src/core/executor/IO.mjs @@ -430,8 +430,6 @@ export function keyboard_read(fn_post_read, fn_post_params) { } const val = fn_post_read(document.app.$data.keyboard, fn_post_params); - // Important: Final line char (/=) couns also as a char in lenght - writeRegister(BigInt(val.length), fn_post_params.indexComp, fn_post_params.indexElem); document.app.$data.keyboard = ""; // clear input From 267b7f5fb148927148133ec7cccf809e2f69aba5 Mon Sep 17 00:00:00 2001 From: ALVAROPING1 Date: Tue, 7 Apr 2026 12:06:22 +0200 Subject: [PATCH 83/85] fix(syscall): fix read/print of UTF-8 strings from user --- .../creatorAssembler/creatorAssemblerBase.mjs | 13 +- src/core/capi/syscall.mts | 10 +- src/core/executor/IO.mjs | 4 +- src/core/executor/devices.mts | 11 +- .../examples/test_mips_example_010.s.snap | 5 +- .../examples/test_mips_example_017.s.snap | 130 ++++++++++++++++++ .../examples/test_riscv_example_017.s.snap | 126 +++++++++++++++++ tests/arch/mips/correct.test.mts | 1 + .../correct/examples/test_mips_example_010.s | 4 +- .../correct/examples/test_mips_example_017.s | 34 +++++ tests/arch/riscv/correct.test.mts | 1 + .../correct/examples/test_riscv_example_017.s | 34 +++++ 12 files changed, 351 insertions(+), 22 deletions(-) create mode 100644 tests/arch/__snapshots__/mips/correct/examples/test_mips_example_017.s.snap create mode 100644 tests/arch/__snapshots__/riscv/correct/examples/test_riscv_example_017.s.snap create mode 100644 tests/arch/mips/correct/examples/test_mips_example_017.s create mode 100644 tests/arch/riscv/correct/examples/test_riscv_example_017.s diff --git a/src/core/assembler/creatorAssembler/creatorAssemblerBase.mjs b/src/core/assembler/creatorAssembler/creatorAssemblerBase.mjs index 1fa0fbb46..5abb5cddb 100644 --- a/src/core/assembler/creatorAssembler/creatorAssemblerBase.mjs +++ b/src/core/assembler/creatorAssembler/creatorAssemblerBase.mjs @@ -377,16 +377,9 @@ function loadDataIntoMemory(data_mem, wasmModules) { break; case DataCategoryJS.String: { - const encoder = new TextEncoder(); - let currentAddr = addr; - - for (const ch_h of data.value(false)) { - const bytes = new Uint8Array(4); - const n = encoder.encodeInto(ch_h, bytes).written; - for (let j = 0; j < n; j++) { - main_memory.write(currentAddr, bytes[j]); - currentAddr++; - } + const bytes = new TextEncoder().encode(data.value(false)); + for (let i = 0n; i < bytes.length; i++) { + main_memory.write(addr + i, bytes[i]); } const stringLength = Number(size); diff --git a/src/core/capi/syscall.mts b/src/core/capi/syscall.mts index a3dd571e3..c5708af84 100644 --- a/src/core/capi/syscall.mts +++ b/src/core/capi/syscall.mts @@ -68,14 +68,16 @@ export const SYSCALL = { break; } case "string": { - const buffer = []; + const bytes = []; // read byte by byte until a null terminator is found for (let i = 0; i < mainMemory.getSize(); i++) { - const byte = mainMemory.read((value as bigint) + BigInt(i)); + const byte = mainMemory.read(BigInt(value) + BigInt(i)); if (byte === 0) break; // null terminator - buffer.push(String.fromCharCode(byte)); + bytes.push(byte); } - const msg = buffer.join(""); + // Decode the UTF-8 data to a string + const buffer = new Uint8Array(bytes); + const msg = new TextDecoder().decode(buffer); display_print(msg); break; } diff --git a/src/core/executor/IO.mjs b/src/core/executor/IO.mjs index e57732422..a9857c6aa 100644 --- a/src/core/executor/IO.mjs +++ b/src/core/executor/IO.mjs @@ -175,8 +175,8 @@ export function kbd_read_string(keystroke, params) { const bytes = new TextEncoder().encode(keystroke); // Write the string to memory byte by byte - for (let i = 0n; i < keystroke.length && i < params.size; i++) { - main_memory.write(BigInt(addr + BigInt(i)), bytes[i]); + for (let i = 0n; i < bytes.length && i < params.size; i++) { + main_memory.write(addr + i, bytes[i]); } if (architecture.config.name.includes("SRV")) { diff --git a/src/core/executor/devices.mts b/src/core/executor/devices.mts index f155b53a7..4c16fb46f 100644 --- a/src/core/executor/devices.mts +++ b/src/core/executor/devices.mts @@ -243,14 +243,17 @@ class ConsoleDevice extends Device { // read byte by byte until a null terminator is found const mainMemory = main_memory as Memory; - const buffer = []; + const bytes = []; for (let i = 0; i < mainMemory.getSize(); i++) { const byte = mainMemory.read(BigInt(addr + i)); if (byte === 0) break; // null terminator - buffer.push(String.fromCharCode(byte)); + bytes.push(byte); } - this.#write(buffer.join(""), DataType.String); + // Decode the UTF-8 data to a string + const buffer = new Uint8Array(bytes) + const msg = new TextDecoder().decode(buffer); + this.#write(msg, DataType.String); break; @@ -304,7 +307,7 @@ class ConsoleDevice extends Device { const bytes = new TextEncoder().encode(keystroke); // Write the string to memory byte by byte - for (let i = 0; i < keystroke.length && i < length; i++) { + for (let i = 0; i < bytes.length && i < length; i++) { mainMemory.write(BigInt(addr + i), bytes[i]!); } }); diff --git a/tests/arch/__snapshots__/mips/correct/examples/test_mips_example_010.s.snap b/tests/arch/__snapshots__/mips/correct/examples/test_mips_example_010.s.snap index ebe2c0e70..9a0694c38 100644 --- a/tests/arch/__snapshots__/mips/correct/examples/test_mips_example_010.s.snap +++ b/tests/arch/__snapshots__/mips/correct/examples/test_mips_example_010.s.snap @@ -206,6 +206,9 @@ snapshot[`mips/correct/examples/test_mips_example_010.s 1`] = ` "77": 2, "79": 4, "83": 12, + "84": 3, + "85": 224, + "87": 8, "9": 32, }, registers: { @@ -214,7 +217,7 @@ snapshot[`mips/correct/examples/test_mips_example_010.s 1`] = ` "4,a0": "0x20004b", "5,a1": "0x4a", "8,t0": "0x4a", - PC: "0xfa0", + PC: "0xffffffff", }, sentinel_errors: [], } diff --git a/tests/arch/__snapshots__/mips/correct/examples/test_mips_example_017.s.snap b/tests/arch/__snapshots__/mips/correct/examples/test_mips_example_017.s.snap new file mode 100644 index 000000000..278dc5ad8 --- /dev/null +++ b/tests/arch/__snapshots__/mips/correct/examples/test_mips_example_017.s.snap @@ -0,0 +1,130 @@ +export const snapshot = {}; + +snapshot[`mips/correct/examples/test_mips_example_017.s 1`] = ` +{ + display: "Insert the string: +String in UTF-8: ∀ ∫ ∇ ∈ 🠬 +", + error: false, + keyboard: " String in UTF-8: ∀ ∫ ∇ ∈ 🠬 +", + memory: { + "0": 60, + "1": 1, + "10": 32, + "11": 32, + "12": 32, + "13": 2, + "15": 4, + "19": 12, + "20": 60, + "2097152": 73, + "2097153": 110, + "2097154": 115, + "2097155": 101, + "2097156": 114, + "2097157": 116, + "2097158": 32, + "2097159": 116, + "2097160": 104, + "2097161": 101, + "2097162": 32, + "2097163": 115, + "2097164": 116, + "2097165": 114, + "2097166": 105, + "2097167": 110, + "2097168": 103, + "2097169": 58, + "2097170": 32, + "2097172": 83, + "2097173": 116, + "2097174": 114, + "2097175": 105, + "2097176": 110, + "2097177": 103, + "2097178": 32, + "2097179": 105, + "2097180": 110, + "2097181": 32, + "2097182": 85, + "2097183": 84, + "2097184": 70, + "2097185": 45, + "2097186": 56, + "2097187": 58, + "2097188": 32, + "2097189": 226, + "2097190": 136, + "2097191": 128, + "2097192": 32, + "2097193": 226, + "2097194": 136, + "2097195": 171, + "2097196": 32, + "2097197": 226, + "2097198": 136, + "2097199": 135, + "2097200": 32, + "2097201": 226, + "2097202": 136, + "2097203": 136, + "2097204": 32, + "2097205": 240, + "2097206": 159, + "2097207": 160, + "2097208": 172, + "2097209": 10, + "21": 1, + "23": 32, + "24": 52, + "25": 33, + "27": 20, + "29": 32, + "3": 32, + "30": 32, + "31": 32, + "32": 32, + "33": 5, + "35": 100, + "36": 32, + "37": 2, + "39": 8, + "4": 52, + "43": 12, + "44": 32, + "45": 4, + "47": 10, + "48": 32, + "49": 2, + "5": 33, + "51": 11, + "55": 12, + "56": 60, + "57": 1, + "59": 32, + "60": 52, + "61": 33, + "63": 20, + "65": 32, + "66": 32, + "67": 32, + "68": 32, + "69": 2, + "71": 4, + "75": 12, + "76": 3, + "77": 224, + "79": 8, + "9": 32, + }, + registers: { + "1,at": "0x200014", + "2,v0": "0x4", + "4,a0": "0x200014", + "5,a1": "0x64", + PC: "0xffffffff", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/correct/examples/test_riscv_example_017.s.snap b/tests/arch/__snapshots__/riscv/correct/examples/test_riscv_example_017.s.snap new file mode 100644 index 000000000..a6befab79 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/correct/examples/test_riscv_example_017.s.snap @@ -0,0 +1,126 @@ +export const snapshot = {}; + +snapshot[`riscv/correct/examples/test_riscv_example_017.s 1`] = ` +{ + display: "Insert the string: +String in UTF-8: ∀ ∫ ∇ ∈ 🠬 +", + error: false, + keyboard: " String in UTF-8: ∀ ∫ ∇ ∈ 🠬 +", + memory: { + "1": 32, + "10": 8, + "11": 147, + "15": 115, + "17": 32, + "18": 5, + "19": 23, + "2": 5, + "2097152": 73, + "2097153": 110, + "2097154": 115, + "2097155": 101, + "2097156": 114, + "2097157": 116, + "2097158": 32, + "2097159": 116, + "2097160": 104, + "2097161": 101, + "2097162": 32, + "2097163": 115, + "2097164": 116, + "2097165": 114, + "2097166": 105, + "2097167": 110, + "2097168": 103, + "2097169": 58, + "2097170": 32, + "2097172": 83, + "2097173": 116, + "2097174": 114, + "2097175": 105, + "2097176": 110, + "2097177": 103, + "2097178": 32, + "2097179": 105, + "2097180": 110, + "2097181": 32, + "2097182": 85, + "2097183": 84, + "2097184": 70, + "2097185": 45, + "2097186": 56, + "2097187": 58, + "2097188": 32, + "2097189": 226, + "2097190": 136, + "2097191": 128, + "2097192": 32, + "2097193": 226, + "2097194": 136, + "2097195": 171, + "2097196": 32, + "2097197": 226, + "2097198": 136, + "2097199": 135, + "2097200": 32, + "2097201": 226, + "2097202": 136, + "2097203": 136, + "2097204": 32, + "2097205": 240, + "2097206": 159, + "2097207": 160, + "2097208": 172, + "2097209": 10, + "21": 69, + "22": 5, + "23": 19, + "24": 6, + "25": 64, + "26": 5, + "27": 147, + "29": 128, + "3": 23, + "30": 8, + "31": 147, + "35": 115, + "38": 5, + "39": 23, + "40": 254, + "41": 101, + "42": 5, + "43": 19, + "45": 176, + "46": 8, + "47": 147, + "5": 5, + "51": 115, + "53": 32, + "54": 5, + "55": 23, + "56": 254, + "57": 5, + "58": 5, + "59": 19, + "6": 5, + "61": 64, + "62": 8, + "63": 147, + "67": 115, + "7": 19, + "70": 128, + "71": 103, + "9": 64, + }, + registers: { + "x10,a0": "0x200014", + "x11,a1": "0x64", + "x17,a7": "0x4", + mtime: "0x12", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/mips/correct.test.mts b/tests/arch/mips/correct.test.mts index 2f8c3d80e..96fbc690b 100644 --- a/tests/arch/mips/correct.test.mts +++ b/tests/arch/mips/correct.test.mts @@ -9,6 +9,7 @@ execution_tests( new Map([ ["test_mips_example_009.s", ["123\n", "456\n"]], ["test_mips_example_010.s", [long_str.length + "\n", long_str]], + ["test_mips_example_017.s", ["String in UTF-8: ∀ ∫ ∇ ∈ 🠬\n"]], ]), ); execution_tests( diff --git a/tests/arch/mips/correct/examples/test_mips_example_010.s b/tests/arch/mips/correct/examples/test_mips_example_010.s index 7a926d8bf..c2fe4205f 100644 --- a/tests/arch/mips/correct/examples/test_mips_example_010.s +++ b/tests/arch/mips/correct/examples/test_mips_example_010.s @@ -28,4 +28,6 @@ main: syscall li $v0, 4 - syscall \ No newline at end of file + syscall + + jr $ra diff --git a/tests/arch/mips/correct/examples/test_mips_example_017.s b/tests/arch/mips/correct/examples/test_mips_example_017.s new file mode 100644 index 000000000..5060fbaad --- /dev/null +++ b/tests/arch/mips/correct/examples/test_mips_example_017.s @@ -0,0 +1,34 @@ + +# +# Creator (https://creatorsim.github.io/creator/) +# + +.data + string: .asciiz "Insert the string: " + space: .space 100 + +.text +main: + # print "Insert string..." + la $a0, string + li $v0, 4 + syscall + + # read string + la $a0, space + li $a1, 100 + li $v0, 8 + syscall + + # print enter + la $a0, '\n' + li $v0, 11 + syscall + + # print string + la $a0, space + li $v0, 4 + syscall + + # return + jr $ra diff --git a/tests/arch/riscv/correct.test.mts b/tests/arch/riscv/correct.test.mts index 40942c730..445b6e377 100644 --- a/tests/arch/riscv/correct.test.mts +++ b/tests/arch/riscv/correct.test.mts @@ -9,6 +9,7 @@ execution_tests( new Map([ ["test_riscv_example_009.s", ["123\n", "456\n"]], ["test_riscv_example_010.s", [long_str.length + "\n", long_str]], + ["test_riscv_example_017.s", ["String in UTF-8: ∀ ∫ ∇ ∈ 🠬\n"]], ]), ); execution_tests( diff --git a/tests/arch/riscv/correct/examples/test_riscv_example_017.s b/tests/arch/riscv/correct/examples/test_riscv_example_017.s new file mode 100644 index 000000000..c091b1d8b --- /dev/null +++ b/tests/arch/riscv/correct/examples/test_riscv_example_017.s @@ -0,0 +1,34 @@ + +# +# Creator (https://creatorsim.github.io/creator/) +# + +.data + string: .string "Insert the string: " + space: .zero 100 + +.text +main: + # print "Insert string..." + la a0, string + li a7, 4 + ecall + + # read string + la a0, space + li a1, 100 + li a7, 8 + ecall + + # print enter + la a0, '\n' + li a7, 11 + ecall + + # print string + la a0, space + li a7, 4 + ecall + + # return + jr ra From 0d2875401c9fba91f1185b971731a4be156d12b0 Mon Sep 17 00:00:00 2001 From: Juan Carlos Date: Tue, 7 Apr 2026 15:36:08 +0200 Subject: [PATCH 84/85] fix tohost errors on load elf_sail_file --- .../sailSimRV/wasm/riscv_sim_RV32.wasm | Bin 3659060 -> 3662426 bytes .../sailSimRV/wasm/riscv_sim_RV32vd.wasm | Bin 3739178 -> 3739574 bytes .../sailSimRV/wasm/riscv_sim_RV64.wasm | Bin 3658212 -> 3658240 bytes 3 files changed, 0 insertions(+), 0 deletions(-) diff --git a/src/core/executor/sailSimRV/wasm/riscv_sim_RV32.wasm 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Users will see update notifications daily if they run nightly builds ### For Stable Releases -1. Update `package.json` version to proper semantic version (e.g., `6.0.0`, `6.1.0`) +1. Update `package.json` version to proper semantic version (e.g., `6.0.0`, `6.1.0`, `6.1.1`) 2. Remove prerelease identifiers from package.json version 3. Set `CREATOR_CHANNEL=stable` or leave unset 4. Create a git tag matching the version @@ -183,7 +183,7 @@ checkForUpdates(currentVersion); // For development/beta - keep prerelease: { - "version": "6.1.0-beta" // Automatically treated as nightly + "version": "6.1.1-beta" // Automatically treated as nightly } ``` diff --git a/package.json b/package.json index 11d754988..4e04622b2 100644 --- a/package.json +++ b/package.json @@ -1,6 +1,6 @@ { "name": "creator", - "version": "6.1.0", + "version": "6.1.1", "private": true, "type": "module", "scripts": { diff --git a/src/cli/commands/info.mts b/src/cli/commands/info.mts index 3facdd65d..ce6b8805a 100644 --- a/src/cli/commands/info.mts +++ b/src/cli/commands/info.mts @@ -56,7 +56,7 @@ export function handleAboutCommand(): void { "║" + colorText(" 🚀 CREATOR Core Version:", "33") + ` ${creatorVersion}`.padEnd( - 35 - creatorVersion.length + " 6.1.0".length, + 35 - creatorVersion.length + " 6.1.1".length, ) + "║", ); diff --git a/src/web/components/general/AboutModal.vue b/src/web/components/general/AboutModal.vue index 6c852beba..546958768 100644 --- a/src/web/components/general/AboutModal.vue +++ b/src/web/components/general/AboutModal.vue @@ -29,7 +29,7 @@ interface Props { defineProps(); const contactMail = "creator.arcos.inf.uc3m.es@gmail.com"; -const projectVersion = "6.1.0"; +const projectVersion = "6.1.1"; const projectLicense = "LGPL-3.0"; const repositoryUrl = "https://github.com/creatorsim/creator";

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zzG#W~ifFVuZ2=8>Cgs!nRv%#kxm)V2j!u>-q4Pc~=X&%QM5Kl6#D<(-DL}Dbfd(t* zduTi&Ekw@6U)O8pSfJ508mwY>3tsCrhH=sjs4Hs|lk)d=-T9})WK;bzOHBUVdDHw~ O={!`U6f2wN{Qm*g?I@!F literal 0 HcmV?d00001 From 585a760184c68b794d3131cb25509e072243739e Mon Sep 17 00:00:00 2001 From: ALVAROPING1 Date: Tue, 24 Mar 2026 11:50:41 +0100 Subject: [PATCH 66/85] fix(riscv): fix incorrect definition of bgeu --- architecture/RISCV/RV32IMFD.yml | 2 +- architecture/RISCV/RV64IMFD.yml | 2 +- architecture/RISCV/SRV32.yml | 2 +- architecture/RISCV/SRV64.yml | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/architecture/RISCV/RV32IMFD.yml b/architecture/RISCV/RV32IMFD.yml index 3252d8e83..69adc05b1 100644 --- a/architecture/RISCV/RV32IMFD.yml +++ b/architecture/RISCV/RV32IMFD.yml @@ -1526,7 +1526,7 @@ instructions: - field: funct3 value: "111" definition: | - if (CAPI.FP.int2uint(registers[rs1]) > CAPI.FP.int2uint(registers[rs2])) + if (CAPI.FP.int2uint(registers[rs1]) >= CAPI.FP.int2uint(registers[rs2])) registers.pc = registers.pc + imm; help: Take the branch if registers rs1 is greater than or equal to rs2, using unsigned comparison. diff --git a/architecture/RISCV/RV64IMFD.yml b/architecture/RISCV/RV64IMFD.yml index 6ce1a4e30..2373b993f 100644 --- a/architecture/RISCV/RV64IMFD.yml +++ b/architecture/RISCV/RV64IMFD.yml @@ -1516,7 +1516,7 @@ instructions: - field: funct3 value: "111" definition: | - if (CAPI.FP.int2uint(registers[rs1]) > CAPI.FP.int2uint(registers[rs2])) + if (CAPI.FP.int2uint(registers[rs1]) >= CAPI.FP.int2uint(registers[rs2])) registers.pc = registers.pc + imm; help: Take the branch if registers rs1 is greater than or equal to rs2, using unsigned comparison. diff --git a/architecture/RISCV/SRV32.yml b/architecture/RISCV/SRV32.yml index f6d9fd290..527d075d5 100644 --- a/architecture/RISCV/SRV32.yml +++ b/architecture/RISCV/SRV32.yml @@ -2084,7 +2084,7 @@ instructions: - field: funct3 value: "111" definition: | - if (CAPI.FP.int2uint(registers[rs1]) > CAPI.FP.int2uint(registers[rs2])) + if (CAPI.FP.int2uint(registers[rs1]) >= CAPI.FP.int2uint(registers[rs2])) registers["PC"] = registers["PC"] + imm; help: Take the branch if registers rs1 is greater than or equal to rs2, using unsigned comparison. - name: blt diff --git a/architecture/RISCV/SRV64.yml b/architecture/RISCV/SRV64.yml index 8b80364f5..6a95634a6 100644 --- a/architecture/RISCV/SRV64.yml +++ b/architecture/RISCV/SRV64.yml @@ -2095,7 +2095,7 @@ instructions: - field: funct3 value: "111" definition: | - if (CAPI.FP.int2uint(registers[rs1]) > CAPI.FP.int2uint(registers[rs2])) + if (CAPI.FP.int2uint(registers[rs1]) >= CAPI.FP.int2uint(registers[rs2])) registers["PC"] = registers["PC"] + imm; help: Take the branch if registers rs1 is greater than or equal to rs2, using unsigned comparison. - name: blt From 40b42a915f6e904c052450b29a64dc10c84ee63c Mon Sep 17 00:00:00 2001 From: ALVAROPING1 Date: Tue, 24 Mar 2026 11:51:17 +0100 Subject: [PATCH 67/85] fix(mips): fix unimplemented bc instruction not raising an error --- architecture/MIPS32.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/architecture/MIPS32.yml b/architecture/MIPS32.yml index 8917e14f0..f977956e3 100644 --- a/architecture/MIPS32.yml +++ b/architecture/MIPS32.yml @@ -1208,6 +1208,7 @@ instructions: order: 1 definition: | // Not implemented + CAPI.VALIDATION.raise('bc not implemented'); - name: bc1eqz template: FPU_I From d9bc7a0c2f9202c3b5cdf63da2bdd3be9839c316 Mon Sep 17 00:00:00 2001 From: ALVAROPING1 Date: Tue, 24 Mar 2026 11:51:47 +0100 Subject: [PATCH 68/85] fix(mips): fix incorrect definition of sltu instruction --- architecture/MIPS32.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/architecture/MIPS32.yml b/architecture/MIPS32.yml index f977956e3..7627d4bcb 100644 --- a/architecture/MIPS32.yml +++ b/architecture/MIPS32.yml @@ -3762,7 +3762,7 @@ instructions: startbit: 5 stopbit: 0 value: "101011" - definition: "registers[rd] = CAPI.FP.uint2int(registers[rs]) < CAPI.FP.uint2int(registers[rt]) ? 1n : 0n;" + definition: "registers[rd] = registers[rs] < registers[rt] ? 1n : 0n;" - name: sqrt.d template: Custom type: Arithmetic floating point From 7766a78554c555bd90dbeac39ed8a8a20265ecbf Mon Sep 17 00:00:00 2001 From: ALVAROPING1 Date: Tue, 24 Mar 2026 12:25:39 +0100 Subject: [PATCH 69/85] fix(MIPS): fix bgezal modifying ra when branch wasn't taken --- architecture/MIPS32.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/architecture/MIPS32.yml b/architecture/MIPS32.yml index 7627d4bcb..bcf8f51a5 100644 --- a/architecture/MIPS32.yml +++ b/architecture/MIPS32.yml @@ -1361,9 +1361,9 @@ instructions: - field: imm type: offset_bytes definition: | - const pc = registers.PC - registers.ra = pc if (CAPI.FP.uint2int(registers[rs]) >= 0) { + const pc = registers.PC + registers.ra = pc registers.PC = pc - 4n + imm; CAPI.STACK.beginFrame(registers[rs]); } From 803df07d12594e4e287d77e4b5c6d8570e27b214 Mon Sep 17 00:00:00 2001 From: ALVAROPING1 Date: Tue, 24 Mar 2026 12:06:47 +0100 Subject: [PATCH 70/85] tests: improve conditional branch tests to check all cases --- .../test_mips_instruction_007.s.snap | 144 ++++++++----- .../test_mips_instruction_008.s.snap | 139 +++++++----- .../test_mips_instruction_009.s.snap | 184 +++++++++++----- .../test_mips_instruction_010.s.snap | 182 +++++++++++----- .../test_mips_instruction_011.s.snap | 182 +++++++++++----- .../test_mips_instruction_012.s.snap | 181 +++++++++++----- .../test_mips_instruction_042.s.snap | 202 ++++++++++++------ .../test_mips_instruction_043.s.snap | 161 ++++++++++---- .../test_mips_instruction_044.s.snap | 201 +++++++++++------ .../test_mips_instruction_045.s.snap | 192 +++++++++++------ .../test_mips_instruction_051.s.snap | 72 ++++--- .../test_mips_instruction_052.s.snap | 64 +++--- .../test_mips_instruction_053.s.snap | 91 +++++--- .../test_mips_instruction_054.s.snap | 60 +++--- .../test_mips_instruction_055.s.snap | 70 +++--- .../test_mips_instruction_056.s.snap | 94 ++++---- .../test_mips_instruction_057.s.snap | 86 ++++---- .../test_riscv_instruction_007.s.snap | 134 ++++++++---- .../test_riscv_instruction_008.s.snap | 120 +++++++---- .../test_riscv_instruction_009.s.snap | 129 +++++++---- .../test_riscv_instruction_010.s.snap | 124 +++++++---- .../test_riscv_instruction_011.s.snap | 129 +++++++---- .../test_riscv_instruction_012.s.snap | 124 +++++++---- .../test_riscv_instruction_042.s.snap | 120 +++++++---- .../test_riscv_instruction_043.s.snap | 120 +++++++---- .../test_riscv_instruction_044.s.snap | 118 ++++++---- .../test_riscv_instruction_045.s.snap | 118 ++++++---- .../instructions/test_mips_instruction_007.s | 38 ++-- .../instructions/test_mips_instruction_008.s | 38 ++-- .../instructions/test_mips_instruction_009.s | 39 ++-- .../instructions/test_mips_instruction_010.s | 39 ++-- .../instructions/test_mips_instruction_011.s | 39 ++-- .../instructions/test_mips_instruction_012.s | 39 ++-- .../instructions/test_mips_instruction_042.s | 39 ++-- .../instructions/test_mips_instruction_043.s | 39 ++-- .../instructions/test_mips_instruction_044.s | 39 ++-- .../instructions/test_mips_instruction_045.s | 39 ++-- .../instructions/test_mips_instruction_051.s | 20 +- .../instructions/test_mips_instruction_052.s | 20 +- .../instructions/test_mips_instruction_053.s | 25 ++- .../instructions/test_mips_instruction_054.s | 20 +- .../instructions/test_mips_instruction_055.s | 20 +- .../instructions/test_mips_instruction_056.s | 22 +- .../instructions/test_mips_instruction_057.s | 21 +- .../instructions/test_riscv_instruction_007.s | 39 ++-- .../instructions/test_riscv_instruction_008.s | 38 ++-- .../instructions/test_riscv_instruction_009.s | 39 ++-- .../instructions/test_riscv_instruction_010.s | 40 ++-- .../instructions/test_riscv_instruction_011.s | 39 ++-- .../instructions/test_riscv_instruction_012.s | 40 ++-- .../instructions/test_riscv_instruction_042.s | 39 ++-- .../instructions/test_riscv_instruction_043.s | 39 ++-- .../instructions/test_riscv_instruction_044.s | 39 ++-- .../instructions/test_riscv_instruction_045.s | 39 ++-- 54 files changed, 2881 insertions(+), 1587 deletions(-) diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_007.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_007.s.snap index 6f46b2f72..0c27e1dfc 100644 --- a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_007.s.snap +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_007.s.snap @@ -8,63 +8,111 @@ snapshot[`mips/instructions/test_mips_instruction_007.s 1`] = ` memory: { "0": 60, "1": 1, - "10": 64, + "10": 128, + "100": 32, + "101": 24, + "103": 1, + "104": 18, + "105": 51, + "107": 8, + "108": 32, + "109": 25, "11": 32, - "12": 32, - "13": 9, - "15": 2, - "16": 32, - "17": 10, - "19": 5, - "20": 60, - "21": 1, - "23": 4, - "24": 52, - "25": 33, - "26": 69, - "27": 98, - "29": 32, - "3": 4, - "30": 88, + "111": 1, + "112": 3, + "113": 224, + "115": 8, + "12": 60, + "13": 1, + "14": 255, + "15": 255, + "16": 52, + "17": 33, + "18": 255, + "19": 246, + "2": 255, + "21": 32, + "22": 136, + "23": 32, + "24": 32, + "25": 18, + "27": 15, + "28": 32, + "29": 19, + "3": 255, "31": 32, - "32": 17, - "33": 104, - "35": 16, + "32": 18, + "33": 16, + "35": 8, "36": 32, - "37": 14, - "39": 34, + "37": 8, + "39": 1, "4": 52, - "40": 32, - "41": 2, - "43": 10, - "47": 12, - "48": 32, - "49": 12, + "40": 18, + "41": 48, + "43": 8, + "44": 32, + "45": 9, + "47": 1, + "48": 18, + "49": 17, "5": 33, - "51": 11, + "51": 8, "52": 32, - "53": 13, - "54": 2, - "55": 43, - "56": 17, - "57": 8, - "58": 255, - "59": 236, - "6": 69, - "7": 98, + "53": 10, + "55": 1, + "56": 18, + "57": 82, + "59": 8, + "6": 255, + "60": 32, + "61": 11, + "63": 1, + "64": 18, + "65": 114, + "67": 8, + "68": 32, + "69": 12, + "7": 216, + "71": 1, + "72": 18, + "73": 83, + "75": 8, + "76": 32, + "77": 13, + "79": 1, + "80": 18, + "81": 80, + "83": 8, + "84": 32, + "85": 14, + "87": 1, + "88": 18, + "89": 18, "9": 32, + "91": 8, + "92": 32, + "93": 15, + "95": 1, + "96": 18, + "97": 113, + "99": 8, }, registers: { - "1,at": "0x44562", - "10,t2": "0x5", - "11,t3": "0x44562", - "12,t4": "0xb", - "13,t5": "0x22b", - "14,t6": "0x22", - "2,v0": "0xa", - "8,t0": "0x44562", - "9,t1": "0x2", - PC: "0x30", + "1,at": "0xfffffff6", + "10,t2": "0x1", + "12,t4": "0x1", + "13,t5": "0x1", + "14,t6": "0x1", + "15,t7": "0x1", + "16,s0": "0xffffffd8", + "17,s1": "0xfffffff6", + "18,s2": "0xf", + "19,s3": "0x20", + "24,t8": "0x1", + "25,t9": "0x1", + "9,t1": "0x1", + PC: "0xffffffff", }, sentinel_errors: [], } diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_008.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_008.s.snap index 8658cac21..786f74a51 100644 --- a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_008.s.snap +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_008.s.snap @@ -8,64 +8,105 @@ snapshot[`mips/instructions/test_mips_instruction_008.s 1`] = ` memory: { "0": 60, "1": 1, - "10": 64, + "10": 128, + "100": 32, + "101": 24, + "103": 1, + "104": 22, + "105": 51, + "107": 8, + "108": 32, + "109": 25, "11": 32, - "12": 32, - "13": 9, - "15": 2, - "16": 32, - "17": 10, - "19": 5, - "20": 60, - "21": 1, - "23": 4, - "24": 52, - "25": 33, - "26": 69, - "27": 98, - "29": 32, - "3": 4, - "30": 88, + "111": 1, + "112": 3, + "113": 224, + "115": 8, + "12": 60, + "13": 1, + "14": 255, + "15": 255, + "16": 52, + "17": 33, + "18": 255, + "19": 246, + "2": 255, + "21": 32, + "22": 136, + "23": 32, + "24": 32, + "25": 18, + "27": 15, + "28": 32, + "29": 19, + "3": 255, "31": 32, - "32": 21, - "33": 10, - "35": 16, + "32": 22, + "33": 16, + "35": 8, "36": 32, - "37": 14, - "39": 34, + "37": 8, + "39": 1, "4": 52, - "40": 32, - "41": 2, - "43": 10, - "47": 12, - "48": 32, - "49": 12, + "40": 22, + "41": 48, + "43": 8, + "44": 32, + "45": 9, + "47": 1, + "48": 22, + "49": 17, "5": 33, - "50": 7, - "51": 84, + "51": 8, "52": 32, - "53": 13, - "54": 2, - "55": 43, - "56": 21, - "57": 72, - "58": 255, - "59": 236, - "6": 69, - "7": 98, + "53": 10, + "55": 1, + "56": 22, + "57": 82, + "59": 8, + "6": 255, + "60": 32, + "61": 11, + "63": 1, + "64": 22, + "65": 114, + "67": 8, + "68": 32, + "69": 12, + "7": 216, + "71": 1, + "72": 22, + "73": 83, + "75": 8, + "76": 32, + "77": 13, + "79": 1, + "80": 22, + "81": 80, + "83": 8, + "84": 32, + "85": 14, + "87": 1, + "88": 22, + "89": 18, "9": 32, + "91": 8, + "92": 32, + "93": 15, + "95": 1, + "96": 22, + "97": 113, + "99": 8, }, registers: { - "1,at": "0x44562", - "10,t2": "0x5", - "11,t3": "0x44562", - "12,t4": "0x754", - "13,t5": "0x22b", - "14,t6": "0x22", - "2,v0": "0xa", - "8,t0": "0x44562", - "9,t1": "0x2", - PC: "0x30", + "1,at": "0xfffffff6", + "11,t3": "0x1", + "16,s0": "0xffffffd8", + "17,s1": "0xfffffff6", + "18,s2": "0xf", + "19,s3": "0x20", + "8,t0": "0x1", + PC: "0xffffffff", }, sentinel_errors: [], } diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_009.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_009.s.snap index 1d0ade045..62e719e21 100644 --- a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_009.s.snap +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_009.s.snap @@ -6,74 +6,150 @@ snapshot[`mips/instructions/test_mips_instruction_009.s 1`] = ` error: false, keyboard: "", memory: { - "0": 32, - "1": 8, - "11": 5, + "0": 60, + "1": 1, + "10": 128, + "100": 32, + "101": 13, + "103": 1, + "104": 2, + "105": 18, + "106": 8, + "107": 42, + "108": 20, + "109": 1, + "11": 32, + "111": 8, + "112": 32, + "113": 14, + "115": 1, + "116": 2, + "117": 80, + "118": 8, + "119": 42, "12": 60, + "120": 20, + "121": 1, + "123": 8, + "124": 32, + "125": 15, + "127": 1, + "128": 2, + "129": 51, "13": 1, - "15": 4, + "130": 8, + "131": 42, + "132": 20, + "133": 1, + "135": 8, + "136": 32, + "137": 24, + "139": 1, + "14": 255, + "140": 2, + "141": 113, + "142": 8, + "143": 42, + "144": 20, + "145": 1, + "147": 8, + "148": 32, + "149": 25, + "15": 255, + "151": 1, + "152": 3, + "153": 224, + "155": 8, "16": 52, "17": 33, - "18": 69, - "19": 98, - "2": 1, + "18": 255, + "19": 246, + "2": 255, "21": 32, - "22": 88, + "22": 136, "23": 32, - "24": 1, - "25": 10, - "26": 8, - "27": 42, - "28": 20, - "29": 1, - "3": 105, - "31": 24, - "32": 1, - "33": 40, + "24": 32, + "25": 18, + "27": 15, + "28": 32, + "29": 19, + "3": 255, + "31": 32, + "32": 2, + "33": 16, "34": 8, "35": 42, "36": 20, "37": 1, - "39": 16, - "4": 32, + "39": 8, + "4": 52, "40": 32, - "41": 14, - "43": 34, - "44": 32, - "45": 2, - "47": 10, - "5": 9, - "51": 12, + "41": 8, + "43": 1, + "44": 2, + "45": 17, + "46": 8, + "47": 42, + "48": 20, + "49": 1, + "5": 33, + "51": 8, "52": 32, - "53": 12, - "55": 11, - "56": 32, - "57": 13, - "58": 2, - "59": 43, - "60": 1, - "61": 141, - "62": 8, - "63": 42, - "64": 20, - "65": 1, - "66": 255, - "67": 232, - "7": 2, - "8": 32, - "9": 10, + "53": 9, + "55": 1, + "56": 2, + "57": 48, + "58": 8, + "59": 42, + "6": 255, + "60": 20, + "61": 1, + "63": 8, + "64": 32, + "65": 10, + "67": 1, + "68": 2, + "69": 82, + "7": 216, + "70": 8, + "71": 42, + "72": 20, + "73": 1, + "75": 8, + "76": 32, + "77": 11, + "79": 1, + "80": 2, + "81": 83, + "82": 8, + "83": 42, + "84": 20, + "85": 1, + "87": 8, + "88": 32, + "89": 12, + "9": 32, + "91": 1, + "92": 2, + "93": 114, + "94": 8, + "95": 42, + "96": 20, + "97": 1, + "99": 8, }, registers: { - "1,at": "0x1", - "10,t2": "0x5", - "11,t3": "0x44562", - "12,t4": "0xb", - "13,t5": "0x22b", - "14,t6": "0x22", - "2,v0": "0xa", - "8,t0": "0x169", - "9,t1": "0x2", - PC: "0x34", + "10,t2": "0x1", + "11,t3": "0x1", + "13,t5": "0x1", + "15,t7": "0x1", + "16,s0": "0xffffffd8", + "17,s1": "0xfffffff6", + "18,s2": "0xf", + "19,s3": "0x20", + "25,t9": "0x1", + "8,t0": "0x1", + PC: "0xffffffff", }, sentinel_errors: [], } diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_010.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_010.s.snap index 32ea81a2b..ad98b092a 100644 --- a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_010.s.snap +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_010.s.snap @@ -6,74 +6,148 @@ snapshot[`mips/instructions/test_mips_instruction_010.s 1`] = ` error: false, keyboard: "", memory: { - "0": 32, - "1": 8, - "11": 5, + "0": 60, + "1": 1, + "10": 128, + "100": 32, + "101": 13, + "103": 1, + "104": 2, + "105": 18, + "106": 8, + "107": 42, + "108": 16, + "109": 1, + "11": 32, + "111": 8, + "112": 32, + "113": 14, + "115": 1, + "116": 2, + "117": 80, + "118": 8, + "119": 42, "12": 60, + "120": 16, + "121": 1, + "123": 8, + "124": 32, + "125": 15, + "127": 1, + "128": 2, + "129": 51, "13": 1, - "15": 4, + "130": 8, + "131": 42, + "132": 16, + "133": 1, + "135": 8, + "136": 32, + "137": 24, + "139": 1, + "14": 255, + "140": 2, + "141": 113, + "142": 8, + "143": 42, + "144": 16, + "145": 1, + "147": 8, + "148": 32, + "149": 25, + "15": 255, + "151": 1, + "152": 3, + "153": 224, + "155": 8, "16": 52, "17": 33, - "18": 69, - "19": 98, - "2": 1, + "18": 255, + "19": 246, + "2": 255, "21": 32, - "22": 88, + "22": 136, "23": 32, - "24": 1, - "25": 11, - "26": 8, - "27": 42, - "28": 16, - "29": 1, - "3": 105, - "31": 24, - "32": 1, - "33": 104, + "24": 32, + "25": 18, + "27": 15, + "28": 32, + "29": 19, + "3": 255, + "31": 32, + "32": 2, + "33": 16, "34": 8, "35": 42, "36": 16, "37": 1, - "39": 16, - "4": 32, + "39": 8, + "4": 52, "40": 32, - "41": 14, - "43": 34, - "44": 32, - "45": 2, - "47": 10, - "5": 9, - "51": 12, + "41": 8, + "43": 1, + "44": 2, + "45": 17, + "46": 8, + "47": 42, + "48": 16, + "49": 1, + "5": 33, + "51": 8, "52": 32, - "53": 12, - "54": 7, - "55": 84, - "56": 32, - "57": 13, - "58": 2, - "59": 43, - "60": 1, - "61": 141, - "62": 8, - "63": 42, - "64": 16, - "65": 1, - "66": 255, - "67": 232, - "7": 2, - "8": 32, - "9": 10, + "53": 9, + "55": 1, + "56": 2, + "57": 48, + "58": 8, + "59": 42, + "6": 255, + "60": 16, + "61": 1, + "63": 8, + "64": 32, + "65": 10, + "67": 1, + "68": 2, + "69": 82, + "7": 216, + "70": 8, + "71": 42, + "72": 16, + "73": 1, + "75": 8, + "76": 32, + "77": 11, + "79": 1, + "80": 2, + "81": 83, + "82": 8, + "83": 42, + "84": 16, + "85": 1, + "87": 8, + "88": 32, + "89": 12, + "9": 32, + "91": 1, + "92": 2, + "93": 114, + "94": 8, + "95": 42, + "96": 16, + "97": 1, + "99": 8, }, registers: { - "10,t2": "0x5", - "11,t3": "0x44562", - "12,t4": "0x754", - "13,t5": "0x22b", - "14,t6": "0x22", - "2,v0": "0xa", - "8,t0": "0x169", - "9,t1": "0x2", - PC: "0x34", + "12,t4": "0x1", + "14,t6": "0x1", + "16,s0": "0xffffffd8", + "17,s1": "0xfffffff6", + "18,s2": "0xf", + "19,s3": "0x20", + "24,t8": "0x1", + "9,t1": "0x1", + PC: "0xffffffff", }, sentinel_errors: [], } diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_011.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_011.s.snap index 84df901c2..febfa25e6 100644 --- a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_011.s.snap +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_011.s.snap @@ -6,75 +6,151 @@ snapshot[`mips/instructions/test_mips_instruction_011.s 1`] = ` error: false, keyboard: "", memory: { - "0": 32, - "1": 8, - "11": 5, + "0": 60, + "1": 1, + "10": 128, + "100": 32, + "101": 13, + "103": 1, + "104": 2, + "105": 18, + "106": 8, + "107": 43, + "108": 20, + "109": 1, + "11": 32, + "111": 8, + "112": 32, + "113": 14, + "115": 1, + "116": 2, + "117": 80, + "118": 8, + "119": 43, "12": 60, + "120": 20, + "121": 1, + "123": 8, + "124": 32, + "125": 15, + "127": 1, + "128": 2, + "129": 51, "13": 1, - "15": 4, + "130": 8, + "131": 43, + "132": 20, + "133": 1, + "135": 8, + "136": 32, + "137": 24, + "139": 1, + "14": 255, + "140": 2, + "141": 113, + "142": 8, + "143": 43, + "144": 20, + "145": 1, + "147": 8, + "148": 32, + "149": 25, + "15": 255, + "151": 1, + "152": 3, + "153": 224, + "155": 8, "16": 52, "17": 33, - "18": 69, - "19": 98, - "2": 1, + "18": 255, + "19": 246, + "2": 255, "21": 32, - "22": 88, + "22": 136, "23": 32, - "24": 1, - "25": 10, - "26": 8, - "27": 43, - "28": 20, - "29": 1, - "3": 105, - "31": 24, - "32": 1, - "33": 40, + "24": 32, + "25": 18, + "27": 15, + "28": 32, + "29": 19, + "3": 255, + "31": 32, + "32": 2, + "33": 16, "34": 8, "35": 43, "36": 20, "37": 1, - "39": 16, - "4": 32, + "39": 8, + "4": 52, "40": 32, - "41": 14, - "43": 34, - "44": 32, - "45": 2, - "47": 10, - "5": 9, - "51": 12, + "41": 8, + "43": 1, + "44": 2, + "45": 17, + "46": 8, + "47": 43, + "48": 20, + "49": 1, + "5": 33, + "51": 8, "52": 32, - "53": 12, - "54": 7, - "55": 84, - "56": 32, - "57": 13, - "58": 2, + "53": 9, + "55": 1, + "56": 2, + "57": 48, + "58": 8, "59": 43, - "60": 1, - "61": 172, - "62": 8, - "63": 43, - "64": 20, - "65": 1, - "66": 255, - "67": 232, - "7": 2, - "8": 32, - "9": 10, + "6": 255, + "60": 20, + "61": 1, + "63": 8, + "64": 32, + "65": 10, + "67": 1, + "68": 2, + "69": 82, + "7": 216, + "70": 8, + "71": 43, + "72": 20, + "73": 1, + "75": 8, + "76": 32, + "77": 11, + "79": 1, + "80": 2, + "81": 83, + "82": 8, + "83": 43, + "84": 20, + "85": 1, + "87": 8, + "88": 32, + "89": 12, + "9": 32, + "91": 1, + "92": 2, + "93": 114, + "94": 8, + "95": 43, + "96": 20, + "97": 1, + "99": 8, }, registers: { "1,at": "0x1", - "10,t2": "0x5", - "11,t3": "0x44562", - "12,t4": "0x754", - "13,t5": "0x22b", - "14,t6": "0x22", - "2,v0": "0xa", - "8,t0": "0x169", - "9,t1": "0x2", - PC: "0x34", + "10,t2": "0x1", + "11,t3": "0x1", + "13,t5": "0x1", + "14,t6": "0x1", + "16,s0": "0xffffffd8", + "17,s1": "0xfffffff6", + "18,s2": "0xf", + "19,s3": "0x20", + "24,t8": "0x1", + "8,t0": "0x1", + PC: "0xffffffff", }, sentinel_errors: [], } diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_012.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_012.s.snap index 5e91a5ec5..83fb2eda3 100644 --- a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_012.s.snap +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_012.s.snap @@ -6,74 +6,149 @@ snapshot[`mips/instructions/test_mips_instruction_012.s 1`] = ` error: false, keyboard: "", memory: { - "0": 32, - "1": 8, - "11": 5, + "0": 60, + "1": 1, + "10": 128, + "100": 32, + "101": 13, + "103": 1, + "104": 2, + "105": 18, + "106": 8, + "107": 43, + "108": 16, + "109": 1, + "11": 32, + "111": 8, + "112": 32, + "113": 14, + "115": 1, + "116": 2, + "117": 80, + "118": 8, + "119": 43, "12": 60, + "120": 16, + "121": 1, + "123": 8, + "124": 32, + "125": 15, + "127": 1, + "128": 2, + "129": 51, "13": 1, - "15": 4, + "130": 8, + "131": 43, + "132": 16, + "133": 1, + "135": 8, + "136": 32, + "137": 24, + "139": 1, + "14": 255, + "140": 2, + "141": 113, + "142": 8, + "143": 43, + "144": 16, + "145": 1, + "147": 8, + "148": 32, + "149": 25, + "15": 255, + "151": 1, + "152": 3, + "153": 224, + "155": 8, "16": 52, "17": 33, - "18": 69, - "19": 98, - "2": 1, + "18": 255, + "19": 246, + "2": 255, "21": 32, - "22": 88, + "22": 136, "23": 32, - "24": 1, - "25": 11, - "26": 8, - "27": 43, - "28": 16, - "29": 1, - "3": 105, - "31": 24, - "32": 1, - "33": 106, + "24": 32, + "25": 18, + "27": 15, + "28": 32, + "29": 19, + "3": 255, + "31": 32, + "32": 2, + "33": 16, "34": 8, "35": 43, "36": 16, "37": 1, - "39": 16, - "4": 32, + "39": 8, + "4": 52, "40": 32, - "41": 14, - "43": 34, - "44": 32, - "45": 2, - "47": 10, - "5": 9, - "51": 12, + "41": 8, + "43": 1, + "44": 2, + "45": 17, + "46": 8, + "47": 43, + "48": 16, + "49": 1, + "5": 33, + "51": 8, "52": 32, - "53": 12, - "54": 7, - "55": 84, - "56": 32, - "57": 13, - "58": 2, + "53": 9, + "55": 1, + "56": 2, + "57": 48, + "58": 8, "59": 43, - "60": 1, - "61": 141, - "62": 8, - "63": 43, - "64": 16, - "65": 1, - "66": 255, - "67": 232, - "7": 2, - "8": 32, - "9": 10, + "6": 255, + "60": 16, + "61": 1, + "63": 8, + "64": 32, + "65": 10, + "67": 1, + "68": 2, + "69": 82, + "7": 216, + "70": 8, + "71": 43, + "72": 16, + "73": 1, + "75": 8, + "76": 32, + "77": 11, + "79": 1, + "80": 2, + "81": 83, + "82": 8, + "83": 43, + "84": 16, + "85": 1, + "87": 8, + "88": 32, + "89": 12, + "9": 32, + "91": 1, + "92": 2, + "93": 114, + "94": 8, + "95": 43, + "96": 16, + "97": 1, + "99": 8, }, registers: { - "10,t2": "0x5", - "11,t3": "0x44562", - "12,t4": "0x754", - "13,t5": "0x22b", - "14,t6": "0x22", - "2,v0": "0xa", - "8,t0": "0x169", - "9,t1": "0x2", - PC: "0x34", + "1,at": "0x1", + "12,t4": "0x1", + "15,t7": "0x1", + "16,s0": "0xffffffd8", + "17,s1": "0xfffffff6", + "18,s2": "0xf", + "19,s3": "0x20", + "25,t9": "0x1", + "9,t1": "0x1", + PC: "0xffffffff", }, sentinel_errors: [], } diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_042.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_042.s.snap index 543a522b7..8e7d77879 100644 --- a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_042.s.snap +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_042.s.snap @@ -6,69 +6,151 @@ snapshot[`mips/instructions/test_mips_instruction_042.s 1`] = ` error: false, keyboard: "", memory: { - "0": 32, - "1": 8, - "11": 5, - "12": 32, - "13": 11, - "14": 2, - "15": 31, - "16": 1, - "17": 9, - "18": 8, - "19": 42, - "2": 3, - "20": 20, - "21": 1, - "23": 24, - "24": 1, - "25": 104, - "26": 8, - "27": 42, - "28": 20, - "29": 1, - "3": 114, - "31": 16, - "32": 32, - "33": 14, - "35": 34, - "36": 32, - "37": 2, - "39": 10, - "4": 32, - "43": 12, - "44": 32, - "45": 12, - "47": 11, - "48": 32, - "49": 13, - "5": 9, - "50": 2, - "51": 43, - "52": 1, - "53": 141, - "54": 8, - "55": 42, - "56": 20, - "57": 1, - "58": 255, - "59": 232, - "6": 3, - "7": 113, - "8": 32, - "9": 10, + "0": 60, + "1": 1, + "10": 128, + "100": 32, + "101": 13, + "103": 1, + "104": 2, + "105": 80, + "106": 8, + "107": 42, + "108": 20, + "109": 1, + "11": 32, + "111": 8, + "112": 32, + "113": 14, + "115": 1, + "116": 2, + "117": 18, + "118": 8, + "119": 42, + "12": 60, + "120": 20, + "121": 1, + "123": 8, + "124": 32, + "125": 15, + "127": 1, + "128": 2, + "129": 113, + "13": 1, + "130": 8, + "131": 42, + "132": 20, + "133": 1, + "135": 8, + "136": 32, + "137": 24, + "139": 1, + "14": 255, + "140": 2, + "141": 51, + "142": 8, + "143": 42, + "144": 20, + "145": 1, + "147": 8, + "148": 32, + "149": 25, + "15": 255, + "151": 1, + "152": 3, + "153": 224, + "155": 8, + "16": 52, + "17": 33, + "18": 255, + "19": 246, + "2": 255, + "21": 32, + "22": 136, + "23": 32, + "24": 32, + "25": 18, + "27": 15, + "28": 32, + "29": 19, + "3": 255, + "31": 32, + "32": 2, + "33": 16, + "34": 8, + "35": 42, + "36": 20, + "37": 1, + "39": 8, + "4": 52, + "40": 32, + "41": 8, + "43": 1, + "44": 2, + "45": 48, + "46": 8, + "47": 42, + "48": 20, + "49": 1, + "5": 33, + "51": 8, + "52": 32, + "53": 9, + "55": 1, + "56": 2, + "57": 17, + "58": 8, + "59": 42, + "6": 255, + "60": 20, + "61": 1, + "63": 8, + "64": 32, + "65": 10, + "67": 1, + "68": 2, + "69": 82, + "7": 216, + "70": 8, + "71": 42, + "72": 20, + "73": 1, + "75": 8, + "76": 32, + "77": 11, + "79": 1, + "80": 2, + "81": 114, + "82": 8, + "83": 42, + "84": 20, + "85": 1, + "87": 8, + "88": 32, + "89": 12, + "9": 32, + "91": 1, + "92": 2, + "93": 83, + "94": 8, + "95": 42, + "96": 20, + "97": 1, + "99": 8, }, registers: { "1,at": "0x1", - "10,t2": "0x5", - "11,t3": "0x21f", - "12,t4": "0xb", - "13,t5": "0x22b", - "14,t6": "0x22", - "2,v0": "0xa", - "8,t0": "0x372", - "9,t1": "0x371", - PC: "0x2c", + "11,t3": "0x1", + "12,t4": "0x1", + "14,t6": "0x1", + "16,s0": "0xffffffd8", + "17,s1": "0xfffffff6", + "18,s2": "0xf", + "19,s3": "0x20", + "24,t8": "0x1", + "8,t0": "0x1", + "9,t1": "0x1", + PC: "0xffffffff", }, sentinel_errors: [], } diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_043.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_043.s.snap index f20aee26f..80e65b40d 100644 --- a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_043.s.snap +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_043.s.snap @@ -8,81 +8,148 @@ snapshot[`mips/instructions/test_mips_instruction_043.s 1`] = ` memory: { "0": 60, "1": 1, - "10": 64, + "10": 128, + "100": 32, + "101": 13, + "103": 1, + "104": 2, + "105": 80, + "106": 8, + "107": 43, + "108": 20, + "109": 1, "11": 32, + "111": 8, + "112": 32, + "113": 14, + "115": 1, + "116": 2, + "117": 18, + "118": 8, + "119": 43, "12": 60, + "120": 20, + "121": 1, + "123": 8, + "124": 32, + "125": 15, + "127": 1, + "128": 2, + "129": 113, "13": 1, + "130": 8, + "131": 43, + "132": 20, + "133": 1, + "135": 8, + "136": 32, + "137": 24, + "139": 1, "14": 255, + "140": 2, + "141": 51, + "142": 8, + "143": 43, + "144": 20, + "145": 1, + "147": 8, + "148": 32, + "149": 25, "15": 255, + "151": 1, + "152": 3, + "153": 224, + "155": 8, "16": 52, "17": 33, - "18": 252, - "19": 143, + "18": 255, + "19": 246, "2": 255, "21": 32, - "22": 72, + "22": 136, "23": 32, "24": 32, - "25": 10, - "27": 5, + "25": 18, + "27": 15, "28": 32, - "29": 11, + "29": 19, "3": 255, - "30": 2, - "31": 31, - "32": 1, - "33": 40, + "31": 32, + "32": 2, + "33": 16, "34": 8, "35": 43, "36": 20, "37": 1, - "39": 24, + "39": 8, "4": 52, - "40": 1, - "41": 75, - "42": 8, - "43": 43, - "44": 20, - "45": 1, - "47": 16, - "48": 32, - "49": 14, + "40": 32, + "41": 8, + "43": 1, + "44": 2, + "45": 48, + "46": 8, + "47": 43, + "48": 20, + "49": 1, "5": 33, - "51": 34, + "51": 8, "52": 32, - "53": 2, - "55": 10, - "59": 12, - "6": 252, - "60": 32, - "61": 12, - "63": 11, + "53": 9, + "55": 1, + "56": 2, + "57": 17, + "58": 8, + "59": 43, + "6": 255, + "60": 20, + "61": 1, + "63": 8, "64": 32, - "65": 13, - "66": 2, - "67": 43, - "68": 1, - "69": 141, - "7": 142, + "65": 10, + "67": 1, + "68": 2, + "69": 82, + "7": 216, "70": 8, "71": 43, "72": 20, "73": 1, - "74": 255, - "75": 232, + "75": 8, + "76": 32, + "77": 11, + "79": 1, + "80": 2, + "81": 114, + "82": 8, + "83": 43, + "84": 20, + "85": 1, + "87": 8, + "88": 32, + "89": 12, "9": 32, + "91": 1, + "92": 2, + "93": 83, + "94": 8, + "95": 43, + "96": 20, + "97": 1, + "99": 8, }, registers: { - "1,at": "0x1", - "10,t2": "0x5", - "11,t3": "0x21f", - "12,t4": "0xb", - "13,t5": "0x22b", - "14,t6": "0x22", - "2,v0": "0xa", - "8,t0": "0xfffffc8e", - "9,t1": "0xfffffc8f", - PC: "0x3c", + "11,t3": "0x1", + "12,t4": "0x1", + "15,t7": "0x1", + "16,s0": "0xffffffd8", + "17,s1": "0xfffffff6", + "18,s2": "0xf", + "19,s3": "0x20", + "25,t9": "0x1", + "8,t0": "0x1", + "9,t1": "0x1", + PC: "0xffffffff", }, sentinel_errors: [], } diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_044.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_044.s.snap index ac7db661b..b51139178 100644 --- a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_044.s.snap +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_044.s.snap @@ -6,68 +6,149 @@ snapshot[`mips/instructions/test_mips_instruction_044.s 1`] = ` error: false, keyboard: "", memory: { - "0": 32, - "1": 8, - "11": 5, - "12": 32, - "13": 11, - "14": 2, - "15": 31, - "16": 1, - "17": 40, - "18": 8, - "19": 42, - "2": 3, - "20": 16, - "21": 1, - "23": 24, - "24": 1, - "25": 106, - "26": 8, - "27": 42, - "28": 16, - "29": 1, - "3": 114, - "31": 16, - "32": 32, - "33": 14, - "35": 34, - "36": 32, - "37": 2, - "39": 10, - "4": 32, - "43": 12, - "44": 32, - "45": 12, - "47": 11, - "48": 32, - "49": 13, - "5": 9, - "50": 2, - "51": 43, - "52": 1, - "53": 172, - "54": 8, - "55": 42, - "56": 16, - "57": 1, - "58": 255, - "59": 232, - "6": 3, - "7": 113, - "8": 32, - "9": 10, + "0": 60, + "1": 1, + "10": 128, + "100": 32, + "101": 13, + "103": 1, + "104": 2, + "105": 80, + "106": 8, + "107": 42, + "108": 16, + "109": 1, + "11": 32, + "111": 8, + "112": 32, + "113": 14, + "115": 1, + "116": 2, + "117": 18, + "118": 8, + "119": 42, + "12": 60, + "120": 16, + "121": 1, + "123": 8, + "124": 32, + "125": 15, + "127": 1, + "128": 2, + "129": 113, + "13": 1, + "130": 8, + "131": 42, + "132": 16, + "133": 1, + "135": 8, + "136": 32, + "137": 24, + "139": 1, + "14": 255, + "140": 2, + "141": 51, + "142": 8, + "143": 42, + "144": 16, + "145": 1, + "147": 8, + "148": 32, + "149": 25, + "15": 255, + "151": 1, + "152": 3, + "153": 224, + "155": 8, + "16": 52, + "17": 33, + "18": 255, + "19": 246, + "2": 255, + "21": 32, + "22": 136, + "23": 32, + "24": 32, + "25": 18, + "27": 15, + "28": 32, + "29": 19, + "3": 255, + "31": 32, + "32": 2, + "33": 16, + "34": 8, + "35": 42, + "36": 16, + "37": 1, + "39": 8, + "4": 52, + "40": 32, + "41": 8, + "43": 1, + "44": 2, + "45": 48, + "46": 8, + "47": 42, + "48": 16, + "49": 1, + "5": 33, + "51": 8, + "52": 32, + "53": 9, + "55": 1, + "56": 2, + "57": 17, + "58": 8, + "59": 42, + "6": 255, + "60": 16, + "61": 1, + "63": 8, + "64": 32, + "65": 10, + "67": 1, + "68": 2, + "69": 82, + "7": 216, + "70": 8, + "71": 42, + "72": 16, + "73": 1, + "75": 8, + "76": 32, + "77": 11, + "79": 1, + "80": 2, + "81": 114, + "82": 8, + "83": 42, + "84": 16, + "85": 1, + "87": 8, + "88": 32, + "89": 12, + "9": 32, + "91": 1, + "92": 2, + "93": 83, + "94": 8, + "95": 42, + "96": 16, + "97": 1, + "99": 8, }, registers: { - "10,t2": "0x5", - "11,t3": "0x21f", - "12,t4": "0xb", - "13,t5": "0x22b", - "14,t6": "0x22", - "2,v0": "0xa", - "8,t0": "0x372", - "9,t1": "0x371", - PC: "0x2c", + "1,at": "0x1", + "10,t2": "0x1", + "13,t5": "0x1", + "15,t7": "0x1", + "16,s0": "0xffffffd8", + "17,s1": "0xfffffff6", + "18,s2": "0xf", + "19,s3": "0x20", + "25,t9": "0x1", + PC: "0xffffffff", }, sentinel_errors: [], } diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_045.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_045.s.snap index d9a0adfac..0a13b7fa6 100644 --- a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_045.s.snap +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_045.s.snap @@ -8,94 +8,146 @@ snapshot[`mips/instructions/test_mips_instruction_045.s 1`] = ` memory: { "0": 60, "1": 1, - "10": 64, + "10": 128, + "100": 32, + "101": 13, + "103": 1, + "104": 2, + "105": 80, + "106": 8, + "107": 43, + "108": 16, + "109": 1, "11": 32, + "111": 8, + "112": 32, + "113": 14, + "115": 1, + "116": 2, + "117": 18, + "118": 8, + "119": 43, "12": 60, + "120": 16, + "121": 1, + "123": 8, + "124": 32, + "125": 15, + "127": 1, + "128": 2, + "129": 113, "13": 1, + "130": 8, + "131": 43, + "132": 16, + "133": 1, + "135": 8, + "136": 32, + "137": 24, + "139": 1, "14": 255, + "140": 2, + "141": 51, + "142": 8, + "143": 43, + "144": 16, + "145": 1, + "147": 8, + "148": 32, + "149": 25, "15": 255, + "151": 1, + "152": 3, + "153": 224, + "155": 8, "16": 52, "17": 33, - "18": 252, - "19": 143, + "18": 255, + "19": 246, "2": 255, "21": 32, - "22": 72, + "22": 136, "23": 32, "24": 32, - "25": 10, - "27": 5, - "28": 60, - "29": 1, + "25": 18, + "27": 15, + "28": 32, + "29": 19, "3": 255, - "30": 255, - "31": 255, - "32": 52, - "33": 33, - "34": 253, - "35": 225, - "37": 32, - "38": 88, - "39": 32, + "31": 32, + "32": 2, + "33": 16, + "34": 8, + "35": 43, + "36": 16, + "37": 1, + "39": 8, "4": 52, - "40": 1, - "41": 9, - "42": 8, - "43": 43, - "44": 16, - "45": 1, - "47": 24, - "48": 1, - "49": 105, + "40": 32, + "41": 8, + "43": 1, + "44": 2, + "45": 48, + "46": 8, + "47": 43, + "48": 16, + "49": 1, "5": 33, - "50": 8, - "51": 43, - "52": 16, - "53": 1, - "55": 16, - "56": 32, - "57": 14, - "59": 34, - "6": 252, - "60": 32, - "61": 2, - "63": 10, - "67": 12, - "68": 32, - "69": 12, - "7": 142, - "71": 11, - "72": 60, + "51": 8, + "52": 32, + "53": 9, + "55": 1, + "56": 2, + "57": 17, + "58": 8, + "59": 43, + "6": 255, + "60": 16, + "61": 1, + "63": 8, + "64": 32, + "65": 10, + "67": 1, + "68": 2, + "69": 82, + "7": 216, + "70": 8, + "71": 43, + "72": 16, "73": 1, - "74": 255, - "75": 255, - "76": 52, - "77": 33, - "78": 253, - "79": 213, - "81": 32, - "82": 104, - "83": 32, - "84": 1, - "85": 141, - "86": 8, - "87": 43, - "88": 16, - "89": 1, + "75": 8, + "76": 32, + "77": 11, + "79": 1, + "80": 2, + "81": 114, + "82": 8, + "83": 43, + "84": 16, + "85": 1, + "87": 8, + "88": 32, + "89": 12, "9": 32, - "90": 255, - "91": 224, + "91": 1, + "92": 2, + "93": 83, + "94": 8, + "95": 43, + "96": 16, + "97": 1, + "99": 8, }, registers: { - "10,t2": "0x5", - "11,t3": "0xfffffde1", - "12,t4": "0xb", - "13,t5": "0xfffffdd5", - "14,t6": "0x22", - "2,v0": "0xa", - "8,t0": "0xfffffc8e", - "9,t1": "0xfffffc8f", - PC: "0x44", + "10,t2": "0x1", + "13,t5": "0x1", + "14,t6": "0x1", + "16,s0": "0xffffffd8", + "17,s1": "0xfffffff6", + "18,s2": "0xf", + "19,s3": "0x20", + "24,t8": "0x1", + PC: "0xffffffff", }, sentinel_errors: [], } diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_051.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_051.s.snap index 1087c338e..1f2aa07a3 100644 --- a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_051.s.snap +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_051.s.snap @@ -6,46 +6,48 @@ snapshot[`mips/instructions/test_mips_instruction_051.s 1`] = ` error: false, keyboard: "", memory: { - "0": 32, - "1": 8, - "10": 255, - "11": 255, - "12": 52, - "13": 33, - "14": 255, - "15": 255, - "17": 32, - "18": 80, - "19": 32, - "20": 16, - "21": 9, - "23": 16, - "24": 32, - "25": 14, - "27": 34, + "0": 60, + "1": 1, + "10": 128, + "11": 32, + "12": 32, + "13": 17, + "15": 15, + "16": 16, + "17": 16, + "19": 8, + "2": 255, + "20": 32, + "21": 8, + "23": 1, + "24": 16, + "25": 17, + "27": 8, "28": 32, - "29": 2, - "3": 1, - "31": 10, - "35": 12, + "29": 9, + "3": 255, + "31": 1, + "32": 16, + "35": 8, "36": 32, - "37": 12, - "4": 32, - "40": 16, - "41": 12, - "42": 255, - "43": 240, - "5": 9, - "8": 60, - "9": 1, + "37": 10, + "39": 1, + "4": 52, + "40": 3, + "41": 224, + "43": 8, + "5": 33, + "6": 255, + "7": 246, + "9": 32, }, registers: { - "1,at": "0xffffffff", - "10,t2": "0xffffffff", - "14,t6": "0x22", - "2,v0": "0xa", + "1,at": "0xfffffff6", + "16,s0": "0xfffffff6", + "17,s1": "0xf", "8,t0": "0x1", - PC: "0x24", + "9,t1": "0x1", + PC: "0xffffffff", }, sentinel_errors: [], } diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_052.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_052.s.snap index 3e48bb1cb..d51c1d707 100644 --- a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_052.s.snap +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_052.s.snap @@ -6,38 +6,48 @@ snapshot[`mips/instructions/test_mips_instruction_052.s 1`] = ` error: false, keyboard: "", memory: { - "0": 32, - "1": 8, - "11": 20, - "12": 5, - "13": 1, - "15": 16, - "16": 32, - "17": 14, - "19": 34, + "0": 60, + "1": 1, + "10": 128, + "11": 32, + "12": 32, + "13": 17, + "15": 15, + "16": 6, + "17": 1, + "19": 8, + "2": 255, "20": 32, - "21": 2, - "23": 10, - "27": 12, + "21": 8, + "23": 1, + "24": 6, + "25": 33, + "27": 8, "28": 32, - "29": 12, - "3": 1, - "31": 2, - "32": 5, - "33": 129, - "34": 255, - "35": 240, - "4": 32, - "5": 9, - "8": 5, - "9": 33, + "29": 9, + "3": 255, + "31": 1, + "32": 4, + "33": 1, + "35": 8, + "36": 32, + "37": 10, + "39": 1, + "4": 52, + "40": 3, + "41": 224, + "43": 8, + "5": 33, + "6": 255, + "7": 246, + "9": 32, }, registers: { - "12,t4": "0x2", - "14,t6": "0x22", - "2,v0": "0xa", + "1,at": "0xfffffff6", + "16,s0": "0xfffffff6", + "17,s1": "0xf", "8,t0": "0x1", - PC: "0x1c", + PC: "0xffffffff", }, sentinel_errors: [], } diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_053.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_053.s.snap index 62966623a..bac734e38 100644 --- a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_053.s.snap +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_053.s.snap @@ -6,39 +6,72 @@ snapshot[`mips/instructions/test_mips_instruction_053.s 1`] = ` error: false, keyboard: "", memory: { - "0": 32, - "1": 8, - "11": 20, - "12": 5, + "0": 60, + "1": 1, + "10": 128, + "11": 32, + "12": 32, "13": 17, - "15": 16, - "16": 32, - "17": 14, - "19": 34, - "20": 32, - "21": 2, - "23": 10, - "27": 12, - "28": 32, - "29": 12, - "3": 1, - "31": 2, - "32": 5, - "33": 145, - "34": 255, - "35": 240, - "4": 32, - "5": 9, - "8": 5, - "9": 49, + "15": 15, + "16": 3, + "17": 224, + "18": 96, + "19": 32, + "2": 255, + "20": 6, + "21": 17, + "23": 8, + "24": 32, + "25": 8, + "27": 1, + "28": 3, + "29": 224, + "3": 255, + "30": 104, + "31": 32, + "32": 6, + "33": 49, + "35": 8, + "36": 32, + "37": 9, + "39": 1, + "4": 52, + "40": 3, + "41": 224, + "42": 112, + "43": 32, + "44": 4, + "45": 17, + "47": 8, + "48": 32, + "49": 10, + "5": 33, + "51": 1, + "52": 3, + "53": 224, + "54": 120, + "55": 32, + "56": 1, + "57": 128, + "58": 248, + "59": 32, + "6": 255, + "60": 3, + "61": 224, + "63": 8, + "7": 246, + "9": 32, }, registers: { - "12,t4": "0x2", - "14,t6": "0x22", - "2,v0": "0xa", - "31,ra": "0x24", + "1,at": "0xfffffff6", + "12,t4": "0xffffffff", + "13,t5": "0xffffffff", + "14,t6": "0x24", + "15,t7": "0x30", + "16,s0": "0xfffffff6", + "17,s1": "0xf", "8,t0": "0x1", - PC: "0x1c", + PC: "0xffffffff", }, sentinel_errors: [], } diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_054.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_054.s.snap index 4f5d8f033..f9d4a0491 100644 --- a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_054.s.snap +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_054.s.snap @@ -6,37 +6,47 @@ snapshot[`mips/instructions/test_mips_instruction_054.s 1`] = ` error: false, keyboard: "", memory: { - "0": 32, - "1": 8, - "11": 20, - "12": 29, - "15": 16, - "16": 32, - "17": 14, - "19": 34, + "0": 60, + "1": 1, + "10": 128, + "11": 32, + "12": 32, + "13": 17, + "15": 15, + "16": 30, + "19": 8, + "2": 255, "20": 32, - "21": 2, - "23": 10, - "27": 12, + "21": 8, + "23": 1, + "24": 30, + "25": 32, + "27": 8, "28": 32, - "29": 12, - "3": 1, - "31": 2, - "32": 29, - "33": 128, - "34": 255, - "35": 240, - "4": 32, - "5": 9, - "8": 29, + "29": 9, + "3": 255, + "31": 1, + "32": 28, + "35": 8, + "36": 32, + "37": 10, + "39": 1, + "4": 52, + "40": 3, + "41": 224, + "43": 8, + "5": 33, + "6": 255, + "7": 246, "9": 32, }, registers: { - "12,t4": "0x2", - "14,t6": "0x22", - "2,v0": "0xa", + "1,at": "0xfffffff6", + "10,t2": "0x1", + "16,s0": "0xfffffff6", + "17,s1": "0xf", "8,t0": "0x1", - PC: "0x1c", + PC: "0xffffffff", }, sentinel_errors: [], } diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_055.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_055.s.snap index 4d9144f27..7699164be 100644 --- a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_055.s.snap +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_055.s.snap @@ -6,46 +6,46 @@ snapshot[`mips/instructions/test_mips_instruction_055.s 1`] = ` error: false, keyboard: "", memory: { - "0": 32, - "1": 8, - "10": 255, - "11": 255, - "13": 32, - "14": 72, - "15": 32, - "16": 25, - "19": 20, - "20": 25, - "21": 32, - "23": 16, - "24": 32, - "25": 14, - "27": 34, + "0": 60, + "1": 1, + "10": 128, + "11": 32, + "12": 32, + "13": 17, + "15": 15, + "16": 26, + "19": 8, + "2": 255, + "20": 32, + "21": 8, + "23": 1, + "24": 26, + "25": 32, + "27": 8, "28": 32, - "29": 2, - "3": 1, - "31": 10, - "35": 12, + "29": 9, + "3": 255, + "31": 1, + "32": 24, + "35": 8, "36": 32, - "37": 12, - "4": 60, - "40": 25, - "41": 128, - "42": 255, - "43": 240, - "5": 1, + "37": 10, + "39": 1, + "4": 52, + "40": 3, + "41": 224, + "43": 8, + "5": 33, "6": 255, - "7": 255, - "8": 52, - "9": 33, + "7": 246, + "9": 32, }, registers: { - "1,at": "0xffffffff", - "14,t6": "0x22", - "2,v0": "0xa", - "8,t0": "0x1", - "9,t1": "0xffffffff", - PC: "0x24", + "1,at": "0xfffffff6", + "16,s0": "0xfffffff6", + "17,s1": "0xf", + "9,t1": "0x1", + PC: "0xffffffff", }, sentinel_errors: [], } diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_056.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_056.s.snap index 2c0eec16a..0bdaab423 100644 --- a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_056.s.snap +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_056.s.snap @@ -6,65 +6,47 @@ snapshot[`mips/instructions/test_mips_instruction_056.s 1`] = ` error: false, keyboard: "", memory: { - "0": 32, - "1": 8, - "10": 2, - "11": 31, - "12": 1, - "13": 9, - "14": 8, - "15": 42, - "16": 20, - "17": 1, - "19": 24, - "2": 3, - "20": 1, - "21": 73, - "22": 8, - "23": 42, - "24": 20, - "25": 1, - "27": 16, + "0": 60, + "1": 1, + "10": 128, + "11": 32, + "12": 32, + "13": 17, + "15": 15, + "16": 6, + "19": 8, + "2": 255, + "20": 32, + "21": 8, + "23": 1, + "24": 6, + "25": 32, + "27": 8, "28": 32, - "29": 14, - "3": 114, - "31": 34, - "32": 32, - "33": 2, - "35": 10, - "39": 12, - "4": 32, - "40": 32, - "41": 12, - "43": 11, - "44": 32, - "45": 13, - "46": 2, - "47": 43, - "48": 1, - "49": 141, - "5": 9, - "50": 8, - "51": 42, - "52": 20, - "53": 1, - "54": 255, - "55": 232, - "6": 3, - "7": 113, - "8": 32, - "9": 10, + "29": 9, + "3": 255, + "31": 1, + "32": 4, + "35": 8, + "36": 32, + "37": 10, + "39": 1, + "4": 52, + "40": 3, + "41": 224, + "43": 8, + "5": 33, + "6": 255, + "7": 246, + "9": 32, }, registers: { - "1,at": "0x1", - "10,t2": "0x21f", - "12,t4": "0xb", - "13,t5": "0x22b", - "14,t6": "0x22", - "2,v0": "0xa", - "8,t0": "0x372", - "9,t1": "0x371", - PC: "0x28", + "1,at": "0xfffffff6", + "10,t2": "0x1", + "16,s0": "0xfffffff6", + "17,s1": "0xf", + "9,t1": "0x1", + PC: "0xffffffff", }, sentinel_errors: [], } diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_057.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_057.s.snap index 4784adc3c..898dd3b3e 100644 --- a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_057.s.snap +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_057.s.snap @@ -6,59 +6,47 @@ snapshot[`mips/instructions/test_mips_instruction_057.s 1`] = ` error: false, keyboard: "", memory: { - "0": 32, - "1": 8, - "10": 255, - "11": 255, - "12": 52, - "13": 33, - "14": 255, - "15": 255, - "17": 32, - "18": 80, - "19": 32, - "20": 20, + "0": 60, + "1": 1, + "10": 128, + "11": 32, + "12": 32, + "13": 17, + "15": 15, + "16": 20, + "17": 16, + "19": 8, + "2": 255, + "20": 32, "21": 8, - "23": 16, - "24": 32, - "25": 14, - "27": 34, + "23": 1, + "24": 20, + "25": 17, + "27": 8, "28": 32, - "29": 2, - "3": 1, - "31": 10, - "35": 12, - "36": 60, - "37": 1, - "39": 3, - "4": 32, - "40": 52, - "41": 33, - "42": 151, - "43": 99, - "45": 32, - "46": 96, - "47": 32, - "48": 32, - "49": 13, - "5": 9, - "51": 170, - "52": 20, - "53": 12, - "54": 255, - "55": 228, - "8": 60, - "9": 1, + "29": 9, + "3": 255, + "31": 1, + "32": 20, + "35": 8, + "36": 32, + "37": 10, + "39": 1, + "4": 52, + "40": 3, + "41": 224, + "43": 8, + "5": 33, + "6": 255, + "7": 246, + "9": 32, }, registers: { - "1,at": "0x39763", - "10,t2": "0xffffffff", - "12,t4": "0x39763", - "13,t5": "0xaa", - "14,t6": "0x22", - "2,v0": "0xa", - "8,t0": "0x1", - PC: "0x24", + "1,at": "0xfffffff6", + "10,t2": "0x1", + "16,s0": "0xfffffff6", + "17,s1": "0xf", + PC: "0xffffffff", }, sentinel_errors: [], } diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_007.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_007.s.snap index 3d1143eed..cae413741 100644 --- a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_007.s.snap +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_007.s.snap @@ -6,60 +6,100 @@ snapshot[`riscv/instructions/test_riscv_instruction_007.s 1`] = ` error: false, keyboard: "", memory: { - "1": 4, + "0": 253, + "1": 128, "10": 3, - "11": 19, - "13": 80, - "14": 3, - "15": 147, - "17": 4, - "18": 68, - "19": 55, - "2": 66, - "20": 86, - "21": 36, + "11": 147, + "12": 2, + "14": 14, + "15": 19, + "17": 82, + "18": 132, + "19": 99, + "2": 2, + "21": 16, "22": 4, "23": 19, - "25": 83, - "26": 138, + "25": 98, + "26": 132, "27": 99, - "29": 98, - "3": 183, - "30": 136, - "31": 99, - "32": 2, - "33": 32, - "34": 14, - "35": 19, - "37": 160, - "38": 8, - "39": 147, - "4": 86, - "43": 115, - "45": 176, - "46": 2, + "29": 16, + "3": 147, + "30": 4, + "31": 147, + "33": 83, + "34": 4, + "35": 99, + "37": 16, + "38": 9, + "39": 19, + "4": 255, + "41": 115, + "42": 132, + "43": 99, + "45": 16, + "46": 9, "47": 147, - "48": 34, - "49": 176, - "5": 34, - "50": 3, - "51": 19, - "52": 254, - "54": 6, - "55": 227, - "6": 130, - "7": 147, - "9": 32, + "48": 1, + "49": 195, + "5": 96, + "50": 132, + "51": 99, + "53": 16, + "54": 10, + "55": 19, + "57": 126, + "58": 4, + "59": 99, + "6": 3, + "61": 16, + "62": 10, + "63": 147, + "65": 114, + "66": 132, + "67": 99, + "69": 16, + "7": 19, + "70": 11, + "71": 19, + "73": 83, + "74": 132, + "75": 99, + "77": 16, + "78": 11, + "79": 147, + "80": 1, + "81": 195, + "82": 4, + "83": 99, + "85": 16, + "86": 12, + "87": 19, + "89": 110, + "9": 240, + "90": 4, + "91": 99, + "93": 16, + "94": 12, + "95": 147, + "98": 128, + "99": 103, }, registers: { - "x17,a7": "0xa", - "x28,t3": "0x22", - "x5,t0": "0x44562", - "x6,t1": "0x2", - "x7,t2": "0x5", - "x8,fp,s0": "0x44562", - mtime: "0xb", - pc: "0x2c", + "x18,s2": "0x1", + "x20,s4": "0x1", + "x21,s5": "0x1", + "x22,s6": "0x1", + "x23,s7": "0x1", + "x24,s8": "0x1", + "x25,s9": "0x1", + "x28,t3": "0x20", + "x5,t0": "0xffffffd8", + "x6,t1": "0xfffffff6", + "x7,t2": "0xf", + "x9,s1": "0x1", + mtime: "0x17", + pc: "0xfffffffe", }, sentinel_errors: [], } diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_008.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_008.s.snap index 61a54cef8..573efd478 100644 --- a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_008.s.snap +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_008.s.snap @@ -6,56 +6,94 @@ snapshot[`riscv/instructions/test_riscv_instruction_008.s 1`] = ` error: false, keyboard: "", memory: { - "0": 22, - "1": 144, + "0": 253, + "1": 128, "10": 3, "11": 147, - "13": 4, - "14": 68, - "15": 55, - "16": 86, - "17": 36, - "18": 4, - "19": 19, + "12": 2, + "14": 14, + "15": 19, + "17": 82, + "18": 148, + "19": 99, "2": 2, - "21": 114, - "22": 152, - "23": 99, - "24": 2, - "25": 32, - "26": 14, - "27": 19, - "29": 160, + "21": 16, + "22": 4, + "23": 19, + "25": 98, + "26": 148, + "27": 99, + "29": 16, "3": 147, - "30": 8, + "30": 4, "31": 147, - "35": 115, - "36": 117, - "37": 64, - "38": 2, - "39": 147, - "40": 34, - "41": 176, - "42": 3, - "43": 19, - "44": 254, - "45": 98, - "46": 150, - "47": 227, - "5": 32, + "33": 83, + "34": 20, + "35": 99, + "37": 16, + "38": 9, + "39": 19, + "4": 255, + "41": 115, + "42": 148, + "43": 99, + "45": 16, + "46": 9, + "47": 147, + "48": 1, + "49": 195, + "5": 96, + "50": 148, + "51": 99, + "53": 16, + "54": 10, + "55": 19, + "57": 126, + "58": 20, + "59": 99, "6": 3, + "61": 16, + "62": 10, + "63": 147, + "65": 114, + "66": 148, + "67": 99, + "69": 16, "7": 19, - "9": 80, + "70": 11, + "71": 19, + "73": 83, + "74": 148, + "75": 99, + "77": 16, + "78": 11, + "79": 147, + "80": 1, + "81": 195, + "82": 20, + "83": 99, + "85": 16, + "86": 12, + "87": 19, + "89": 110, + "9": 240, + "90": 20, + "91": 99, + "93": 16, + "94": 12, + "95": 147, + "98": 128, + "99": 103, }, registers: { - "x17,a7": "0xa", - "x28,t3": "0x22", - "x5,t0": "0x754", - "x6,t1": "0x22b", - "x7,t2": "0x5", - "x8,fp,s0": "0x44562", - mtime: "0xc", - pc: "0x24", + "x19,s3": "0x1", + "x28,t3": "0x20", + "x5,t0": "0xffffffd8", + "x6,t1": "0xfffffff6", + "x7,t2": "0xf", + "x8,fp,s0": "0x1", + mtime: "0x11", + pc: "0xfffffffe", }, sentinel_errors: [], } diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_009.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_009.s.snap index 86fa6b008..dab57a18e 100644 --- a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_009.s.snap +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_009.s.snap @@ -6,61 +6,98 @@ snapshot[`riscv/instructions/test_riscv_instruction_009.s 1`] = ` error: false, keyboard: "", memory: { - "0": 22, - "1": 144, + "0": 253, + "1": 128, "10": 3, "11": 147, - "13": 4, - "14": 68, - "15": 55, - "16": 86, - "17": 36, - "18": 4, - "19": 19, + "12": 2, + "14": 14, + "15": 19, + "17": 82, + "18": 196, + "19": 99, "2": 2, - "21": 114, - "22": 202, - "23": 99, - "25": 83, - "26": 72, + "21": 16, + "22": 4, + "23": 19, + "25": 98, + "26": 196, "27": 99, - "28": 2, - "29": 32, + "29": 16, "3": 147, - "30": 14, - "31": 19, - "33": 160, - "34": 8, - "35": 147, - "39": 115, - "40": 117, - "41": 64, - "42": 4, - "43": 147, - "44": 34, - "45": 176, - "46": 5, - "47": 19, - "48": 254, - "49": 149, - "5": 32, - "50": 70, - "51": 227, + "30": 4, + "31": 147, + "33": 83, + "34": 68, + "35": 99, + "37": 16, + "38": 9, + "39": 19, + "4": 255, + "41": 115, + "42": 196, + "43": 99, + "45": 16, + "46": 9, + "47": 147, + "48": 1, + "49": 195, + "5": 96, + "50": 196, + "51": 99, + "53": 16, + "54": 10, + "55": 19, + "57": 126, + "58": 68, + "59": 99, "6": 3, + "61": 16, + "62": 10, + "63": 147, + "65": 114, + "66": 196, + "67": 99, + "69": 16, "7": 19, - "9": 80, + "70": 11, + "71": 19, + "73": 83, + "74": 196, + "75": 99, + "77": 16, + "78": 11, + "79": 147, + "80": 1, + "81": 195, + "82": 68, + "83": 99, + "85": 16, + "86": 12, + "87": 19, + "89": 110, + "9": 240, + "90": 68, + "91": 99, + "93": 16, + "94": 12, + "95": 147, + "98": 128, + "99": 103, }, registers: { - "x10,a0": "0x22b", - "x17,a7": "0xa", - "x28,t3": "0x22", - "x5,t0": "0x169", - "x6,t1": "0x2", - "x7,t2": "0x5", - "x8,fp,s0": "0x44562", - "x9,s1": "0x754", - mtime: "0xd", - pc: "0x28", + "x18,s2": "0x1", + "x19,s3": "0x1", + "x21,s5": "0x1", + "x23,s7": "0x1", + "x25,s9": "0x1", + "x28,t3": "0x20", + "x5,t0": "0xffffffd8", + "x6,t1": "0xfffffff6", + "x7,t2": "0xf", + "x8,fp,s0": "0x1", + mtime: "0x15", + pc: "0xfffffffe", }, sentinel_errors: [], } diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_010.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_010.s.snap index 99f9ae882..e787a2eb9 100644 --- a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_010.s.snap +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_010.s.snap @@ -6,60 +6,96 @@ snapshot[`riscv/instructions/test_riscv_instruction_010.s 1`] = ` error: false, keyboard: "", memory: { - "0": 22, - "1": 144, + "0": 253, + "1": 128, "10": 3, "11": 147, - "13": 4, - "14": 68, - "15": 55, - "16": 86, - "17": 36, - "18": 4, - "19": 19, + "12": 2, + "14": 14, + "15": 19, + "17": 82, + "18": 212, + "19": 99, "2": 2, - "21": 130, - "22": 218, - "23": 99, - "25": 84, - "26": 88, + "21": 16, + "22": 4, + "23": 19, + "25": 98, + "26": 212, "27": 99, - "28": 2, - "29": 32, + "29": 16, "3": 147, - "30": 14, - "31": 19, - "33": 160, - "34": 8, - "35": 147, - "39": 115, - "40": 117, - "41": 64, - "42": 2, - "43": 147, - "44": 34, - "45": 176, - "46": 15, + "30": 4, + "31": 147, + "33": 83, + "34": 84, + "35": 99, + "37": 16, + "38": 9, + "39": 19, + "4": 255, + "41": 115, + "42": 212, + "43": 99, + "45": 16, + "46": 9, "47": 147, - "48": 254, - "49": 98, - "5": 32, - "50": 214, - "51": 227, + "48": 1, + "49": 195, + "5": 96, + "50": 212, + "51": 99, + "53": 16, + "54": 10, + "55": 19, + "57": 126, + "58": 84, + "59": 99, "6": 3, + "61": 16, + "62": 10, + "63": 147, + "65": 114, + "66": 212, + "67": 99, + "69": 16, "7": 19, - "9": 80, + "70": 11, + "71": 19, + "73": 83, + "74": 212, + "75": 99, + "77": 16, + "78": 11, + "79": 147, + "80": 1, + "81": 195, + "82": 84, + "83": 99, + "85": 16, + "86": 12, + "87": 19, + "89": 110, + "9": 240, + "90": 84, + "91": 99, + "93": 16, + "94": 12, + "95": 147, + "98": 128, + "99": 103, }, registers: { - "x17,a7": "0xa", - "x28,t3": "0x22", - "x31,t6": "0x22b", - "x5,t0": "0x754", - "x6,t1": "0x2", - "x7,t2": "0x5", - "x8,fp,s0": "0x44562", - mtime: "0xd", - pc: "0x28", + "x20,s4": "0x1", + "x22,s6": "0x1", + "x24,s8": "0x1", + "x28,t3": "0x20", + "x5,t0": "0xffffffd8", + "x6,t1": "0xfffffff6", + "x7,t2": "0xf", + "x9,s1": "0x1", + mtime: "0x13", + pc: "0xfffffffe", }, sentinel_errors: [], } diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_011.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_011.s.snap index e0c5bd98b..1b80d8fd7 100644 --- a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_011.s.snap +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_011.s.snap @@ -6,61 +6,98 @@ snapshot[`riscv/instructions/test_riscv_instruction_011.s 1`] = ` error: false, keyboard: "", memory: { - "0": 22, - "1": 144, + "0": 253, + "1": 128, "10": 3, "11": 147, - "13": 4, - "14": 68, - "15": 55, - "16": 86, - "17": 36, - "18": 4, - "19": 19, + "12": 2, + "14": 14, + "15": 19, + "17": 82, + "18": 228, + "19": 99, "2": 2, - "21": 114, - "22": 234, - "23": 99, - "25": 83, - "26": 104, + "21": 16, + "22": 4, + "23": 19, + "25": 98, + "26": 228, "27": 99, - "28": 2, - "29": 32, + "29": 16, "3": 147, - "30": 14, - "31": 19, - "33": 160, - "34": 8, - "35": 147, - "39": 115, - "40": 117, - "41": 64, - "42": 4, - "43": 147, - "44": 34, - "45": 176, - "46": 5, - "47": 19, - "48": 254, - "49": 149, - "5": 32, - "50": 102, - "51": 227, + "30": 4, + "31": 147, + "33": 83, + "34": 100, + "35": 99, + "37": 16, + "38": 9, + "39": 19, + "4": 255, + "41": 115, + "42": 228, + "43": 99, + "45": 16, + "46": 9, + "47": 147, + "48": 1, + "49": 195, + "5": 96, + "50": 228, + "51": 99, + "53": 16, + "54": 10, + "55": 19, + "57": 126, + "58": 100, + "59": 99, "6": 3, + "61": 16, + "62": 10, + "63": 147, + "65": 114, + "66": 228, + "67": 99, + "69": 16, "7": 19, - "9": 80, + "70": 11, + "71": 19, + "73": 83, + "74": 228, + "75": 99, + "77": 16, + "78": 11, + "79": 147, + "80": 1, + "81": 195, + "82": 100, + "83": 99, + "85": 16, + "86": 12, + "87": 19, + "89": 110, + "9": 240, + "90": 100, + "91": 99, + "93": 16, + "94": 12, + "95": 147, + "98": 128, + "99": 103, }, registers: { - "x10,a0": "0x22b", - "x17,a7": "0xa", - "x28,t3": "0x22", - "x5,t0": "0x169", - "x6,t1": "0x2", - "x7,t2": "0x5", - "x8,fp,s0": "0x44562", - "x9,s1": "0x754", - mtime: "0xd", - pc: "0x28", + "x18,s2": "0x1", + "x19,s3": "0x1", + "x21,s5": "0x1", + "x22,s6": "0x1", + "x24,s8": "0x1", + "x28,t3": "0x20", + "x5,t0": "0xffffffd8", + "x6,t1": "0xfffffff6", + "x7,t2": "0xf", + "x8,fp,s0": "0x1", + mtime: "0x15", + pc: "0xfffffffe", }, sentinel_errors: [], } diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_012.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_012.s.snap index aa0c49dab..1aa342334 100644 --- a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_012.s.snap +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_012.s.snap @@ -6,60 +6,96 @@ snapshot[`riscv/instructions/test_riscv_instruction_012.s 1`] = ` error: false, keyboard: "", memory: { - "0": 22, - "1": 144, + "0": 253, + "1": 128, "10": 3, "11": 147, - "13": 4, - "14": 68, - "15": 55, - "16": 86, - "17": 36, - "18": 4, - "19": 19, + "12": 2, + "14": 14, + "15": 19, + "17": 82, + "18": 244, + "19": 99, "2": 2, - "21": 130, - "22": 250, - "23": 99, - "25": 84, - "26": 120, + "21": 16, + "22": 4, + "23": 19, + "25": 98, + "26": 244, "27": 99, - "28": 2, - "29": 32, + "29": 16, "3": 147, - "30": 14, - "31": 19, - "33": 160, - "34": 8, - "35": 147, - "39": 115, - "40": 117, - "41": 64, - "42": 2, - "43": 147, - "44": 34, - "45": 176, - "46": 15, + "30": 4, + "31": 147, + "33": 83, + "34": 116, + "35": 99, + "37": 16, + "38": 9, + "39": 19, + "4": 255, + "41": 115, + "42": 244, + "43": 99, + "45": 16, + "46": 9, "47": 147, - "48": 254, - "49": 98, - "5": 32, - "50": 246, - "51": 227, + "48": 1, + "49": 195, + "5": 96, + "50": 244, + "51": 99, + "53": 16, + "54": 10, + "55": 19, + "57": 126, + "58": 116, + "59": 99, "6": 3, + "61": 16, + "62": 10, + "63": 147, + "65": 114, + "66": 244, + "67": 99, + "69": 16, "7": 19, - "9": 80, + "70": 11, + "71": 19, + "73": 83, + "74": 244, + "75": 99, + "77": 16, + "78": 11, + "79": 147, + "80": 1, + "81": 195, + "82": 116, + "83": 99, + "85": 16, + "86": 12, + "87": 19, + "89": 110, + "9": 240, + "90": 116, + "91": 99, + "93": 16, + "94": 12, + "95": 147, + "98": 128, + "99": 103, }, registers: { - "x17,a7": "0xa", - "x28,t3": "0x22", - "x31,t6": "0x22b", - "x5,t0": "0x754", - "x6,t1": "0x2", - "x7,t2": "0x5", - "x8,fp,s0": "0x44562", - mtime: "0xd", - pc: "0x28", + "x20,s4": "0x1", + "x23,s7": "0x1", + "x25,s9": "0x1", + "x28,t3": "0x20", + "x5,t0": "0xffffffd8", + "x6,t1": "0xfffffff6", + "x7,t2": "0xf", + "x9,s1": "0x1", + mtime: "0x13", + pc: "0xfffffffe", }, sentinel_errors: [], } diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_042.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_042.s.snap index 26f51e141..7961a6ee0 100644 --- a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_042.s.snap +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_042.s.snap @@ -6,56 +6,98 @@ snapshot[`riscv/instructions/test_riscv_instruction_042.s 1`] = ` error: false, keyboard: "", memory: { - "0": 55, - "1": 32, + "0": 253, + "1": 128, "10": 3, "11": 147, - "12": 33, - "13": 240, - "14": 4, + "12": 2, + "14": 14, "15": 19, - "17": 98, - "18": 202, + "17": 82, + "18": 196, "19": 99, "2": 2, - "21": 84, - "22": 72, - "23": 99, - "24": 2, - "25": 32, - "26": 14, - "27": 19, - "29": 160, + "21": 16, + "22": 4, + "23": 19, + "25": 83, + "26": 68, + "27": 99, + "29": 16, "3": 147, - "30": 8, + "30": 4, "31": 147, - "35": 115, - "37": 176, - "38": 2, - "39": 147, - "4": 55, - "40": 34, - "41": 176, - "42": 3, - "43": 19, - "44": 254, - "45": 98, - "46": 198, - "47": 227, - "5": 16, + "33": 98, + "34": 196, + "35": 99, + "37": 16, + "38": 9, + "39": 19, + "4": 255, + "41": 115, + "42": 196, + "43": 99, + "45": 16, + "46": 9, + "47": 147, + "49": 126, + "5": 96, + "50": 68, + "51": 99, + "53": 16, + "54": 10, + "55": 19, + "56": 1, + "57": 195, + "58": 196, + "59": 99, "6": 3, + "61": 16, + "62": 10, + "63": 147, + "65": 83, + "66": 196, + "67": 99, + "69": 16, "7": 19, - "9": 80, + "70": 11, + "71": 19, + "73": 114, + "74": 196, + "75": 99, + "77": 16, + "78": 11, + "79": 147, + "81": 110, + "82": 68, + "83": 99, + "85": 16, + "86": 12, + "87": 19, + "88": 1, + "89": 195, + "9": 240, + "90": 68, + "91": 99, + "93": 16, + "94": 12, + "95": 147, + "98": 128, + "99": 103, }, registers: { - "x17,a7": "0xa", - "x28,t3": "0x22", - "x5,t0": "0xb", - "x6,t1": "0x22b", - "x7,t2": "0x5", - "x8,fp,s0": "0x21f", - mtime: "0xc", - pc: "0x24", + "x19,s3": "0x1", + "x20,s4": "0x1", + "x22,s6": "0x1", + "x24,s8": "0x1", + "x28,t3": "0x20", + "x5,t0": "0xffffffd8", + "x6,t1": "0xfffffff6", + "x7,t2": "0xf", + "x8,fp,s0": "0x1", + "x9,s1": "0x1", + mtime: "0x15", + pc: "0xfffffffe", }, sentinel_errors: [], } diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_043.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_043.s.snap index 883965a92..757333ebb 100644 --- a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_043.s.snap +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_043.s.snap @@ -6,56 +6,98 @@ snapshot[`riscv/instructions/test_riscv_instruction_043.s 1`] = ` error: false, keyboard: "", memory: { - "0": 200, - "1": 224, + "0": 253, + "1": 128, "10": 3, "11": 147, - "12": 33, - "13": 240, - "14": 4, + "12": 2, + "14": 14, "15": 19, - "17": 83, - "18": 106, + "17": 82, + "18": 228, "19": 99, "2": 2, - "21": 131, - "22": 232, - "23": 99, - "24": 2, - "25": 32, - "26": 14, - "27": 19, - "29": 160, + "21": 16, + "22": 4, + "23": 19, + "25": 83, + "26": 100, + "27": 99, + "29": 16, "3": 147, - "30": 8, + "30": 4, "31": 147, - "35": 115, - "37": 176, - "38": 2, - "39": 147, - "4": 200, - "40": 34, - "41": 176, - "42": 3, - "43": 19, - "44": 254, - "45": 98, - "46": 230, - "47": 227, - "5": 240, + "33": 98, + "34": 228, + "35": 99, + "37": 16, + "38": 9, + "39": 19, + "4": 255, + "41": 115, + "42": 228, + "43": 99, + "45": 16, + "46": 9, + "47": 147, + "49": 126, + "5": 96, + "50": 100, + "51": 99, + "53": 16, + "54": 10, + "55": 19, + "56": 1, + "57": 195, + "58": 228, + "59": 99, "6": 3, + "61": 16, + "62": 10, + "63": 147, + "65": 83, + "66": 228, + "67": 99, + "69": 16, "7": 19, - "9": 80, + "70": 11, + "71": 19, + "73": 114, + "74": 228, + "75": 99, + "77": 16, + "78": 11, + "79": 147, + "81": 110, + "82": 100, + "83": 99, + "85": 16, + "86": 12, + "87": 19, + "88": 1, + "89": 195, + "9": 240, + "90": 100, + "91": 99, + "93": 16, + "94": 12, + "95": 147, + "98": 128, + "99": 103, }, registers: { - "x17,a7": "0xa", - "x28,t3": "0x22", - "x5,t0": "0xb", - "x6,t1": "0x22b", - "x7,t2": "0x5", - "x8,fp,s0": "0x21f", - mtime: "0xc", - pc: "0x24", + "x19,s3": "0x1", + "x20,s4": "0x1", + "x23,s7": "0x1", + "x25,s9": "0x1", + "x28,t3": "0x20", + "x5,t0": "0xffffffd8", + "x6,t1": "0xfffffff6", + "x7,t2": "0xf", + "x8,fp,s0": "0x1", + "x9,s1": "0x1", + mtime: "0x15", + pc: "0xfffffffe", }, sentinel_errors: [], } diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_044.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_044.s.snap index b85443449..1b6f31f38 100644 --- a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_044.s.snap +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_044.s.snap @@ -6,56 +6,96 @@ snapshot[`riscv/instructions/test_riscv_instruction_044.s 1`] = ` error: false, keyboard: "", memory: { - "0": 55, - "1": 32, + "0": 253, + "1": 128, "10": 3, "11": 147, - "12": 33, - "13": 240, - "14": 4, + "12": 2, + "14": 14, "15": 19, - "17": 83, - "18": 90, + "17": 82, + "18": 212, "19": 99, "2": 2, - "21": 116, - "22": 88, - "23": 99, - "24": 2, - "25": 32, - "26": 14, - "27": 19, - "29": 160, + "21": 16, + "22": 4, + "23": 19, + "25": 83, + "26": 84, + "27": 99, + "29": 16, "3": 147, - "30": 8, + "30": 4, "31": 147, - "35": 115, - "37": 176, - "38": 2, - "39": 147, - "4": 55, - "40": 34, - "41": 176, - "42": 3, - "43": 19, - "44": 254, - "45": 83, - "46": 86, - "47": 227, - "5": 16, + "33": 98, + "34": 212, + "35": 99, + "37": 16, + "38": 9, + "39": 19, + "4": 255, + "41": 115, + "42": 212, + "43": 99, + "45": 16, + "46": 9, + "47": 147, + "49": 126, + "5": 96, + "50": 84, + "51": 99, + "53": 16, + "54": 10, + "55": 19, + "56": 1, + "57": 195, + "58": 212, + "59": 99, "6": 3, + "61": 16, + "62": 10, + "63": 147, + "65": 83, + "66": 212, + "67": 99, + "69": 16, "7": 19, - "9": 80, + "70": 11, + "71": 19, + "73": 114, + "74": 212, + "75": 99, + "77": 16, + "78": 11, + "79": 147, + "81": 110, + "82": 84, + "83": 99, + "85": 16, + "86": 12, + "87": 19, + "88": 1, + "89": 195, + "9": 240, + "90": 84, + "91": 99, + "93": 16, + "94": 12, + "95": 147, + "98": 128, + "99": 103, }, registers: { - "x17,a7": "0xa", - "x28,t3": "0x22", - "x5,t0": "0xb", - "x6,t1": "0x22b", - "x7,t2": "0x5", - "x8,fp,s0": "0x21f", - mtime: "0xc", - pc: "0x24", + "x18,s2": "0x1", + "x21,s5": "0x1", + "x23,s7": "0x1", + "x25,s9": "0x1", + "x28,t3": "0x20", + "x5,t0": "0xffffffd8", + "x6,t1": "0xfffffff6", + "x7,t2": "0xf", + mtime: "0x13", + pc: "0xfffffffe", }, sentinel_errors: [], } diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_045.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_045.s.snap index c468a7b0c..22cd08d99 100644 --- a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_045.s.snap +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_045.s.snap @@ -6,56 +6,96 @@ snapshot[`riscv/instructions/test_riscv_instruction_045.s 1`] = ` error: false, keyboard: "", memory: { - "0": 200, - "1": 224, + "0": 253, + "1": 128, "10": 3, "11": 147, - "12": 222, - "13": 16, - "14": 4, + "12": 2, + "14": 14, "15": 19, - "17": 98, - "18": 218, + "17": 82, + "18": 244, "19": 99, "2": 2, - "21": 100, - "22": 88, - "23": 99, - "24": 2, - "25": 32, - "26": 14, - "27": 19, - "29": 160, + "21": 16, + "22": 4, + "23": 19, + "25": 83, + "26": 116, + "27": 99, + "29": 16, "3": 147, - "30": 8, + "30": 4, "31": 147, - "35": 115, - "37": 176, - "38": 2, - "39": 147, - "4": 200, - "40": 221, - "41": 80, - "42": 3, - "43": 19, - "44": 254, - "45": 98, - "46": 214, - "47": 227, - "5": 240, + "33": 98, + "34": 244, + "35": 99, + "37": 16, + "38": 9, + "39": 19, + "4": 255, + "41": 115, + "42": 244, + "43": 99, + "45": 16, + "46": 9, + "47": 147, + "49": 126, + "5": 96, + "50": 116, + "51": 99, + "53": 16, + "54": 10, + "55": 19, + "56": 1, + "57": 195, + "58": 244, + "59": 99, "6": 3, + "61": 16, + "62": 10, + "63": 147, + "65": 83, + "66": 244, + "67": 99, + "69": 16, "7": 19, - "9": 80, + "70": 11, + "71": 19, + "73": 114, + "74": 244, + "75": 99, + "77": 16, + "78": 11, + "79": 147, + "81": 110, + "82": 116, + "83": 99, + "85": 16, + "86": 12, + "87": 19, + "88": 1, + "89": 195, + "9": 240, + "90": 116, + "91": 99, + "93": 16, + "94": 12, + "95": 147, + "98": 128, + "99": 103, }, registers: { - "x17,a7": "0xa", - "x28,t3": "0x22", - "x5,t0": "0xb", - "x6,t1": "0xfffffdd5", - "x7,t2": "0x5", - "x8,fp,s0": "0xfffffde1", - mtime: "0xc", - pc: "0x24", + "x18,s2": "0x1", + "x21,s5": "0x1", + "x22,s6": "0x1", + "x24,s8": "0x1", + "x28,t3": "0x20", + "x5,t0": "0xffffffd8", + "x6,t1": "0xfffffff6", + "x7,t2": "0xf", + mtime: "0x13", + pc: "0xfffffffe", }, sentinel_errors: [], } diff --git a/tests/arch/mips/instructions/test_mips_instruction_007.s b/tests/arch/mips/instructions/test_mips_instruction_007.s index d63d8f503..20c750789 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_007.s +++ b/tests/arch/mips/instructions/test_mips_instruction_007.s @@ -5,18 +5,30 @@ .text main: - li $t0, 0x44562 - li $t1, 2 - li $t2, 5 - li $t3, 0x44562 - beq $t0, $t3, jump1 + li $s0, -40 + li $s1, -10 + li $s2, 15 + li $s3, 32 - jump2: - li $t6, 34 - li $v0, 10 - syscall + beq $s0, $s0, j0 + li $t0, 1 +j0: beq $s0, $s1, j1 + li $t1, 1 +j1: beq $s1, $s0, j2 + li $t2, 1 +j2: beq $s2, $s2, j3 + li $t3, 1 +j3: beq $s2, $s3, j4 + li $t4, 1 +j4: beq $s3, $s2, j5 + li $t5, 1 +j5: beq $s0, $s2, j6 + li $t6, 1 +j6: beq $s2, $s0, j7 + li $t7, 1 +j7: beq $s1, $s3, j8 + li $t8, 1 +j8: beq $s3, $s1, end + li $t9, 1 - jump1: - li $t4, 11 - li $t5, 555 - beq $t0, $t0, jump2 +end: jr $ra diff --git a/tests/arch/mips/instructions/test_mips_instruction_008.s b/tests/arch/mips/instructions/test_mips_instruction_008.s index 303d953e3..d9f9b6771 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_008.s +++ b/tests/arch/mips/instructions/test_mips_instruction_008.s @@ -5,18 +5,30 @@ .text main: - li $t0, 0x44562 - li $t1, 2 - li $t2, 5 - li $t3, 0x44562 - bne $t2, $t0, jump1 + li $s0, -40 + li $s1, -10 + li $s2, 15 + li $s3, 32 - jump2: - li $t6, 34 - li $v0, 10 - syscall + bne $s0, $s0, j0 + li $t0, 1 +j0: bne $s0, $s1, j1 + li $t1, 1 +j1: bne $s1, $s0, j2 + li $t2, 1 +j2: bne $s2, $s2, j3 + li $t3, 1 +j3: bne $s2, $s3, j4 + li $t4, 1 +j4: bne $s3, $s2, j5 + li $t5, 1 +j5: bne $s0, $s2, j6 + li $t6, 1 +j6: bne $s2, $s0, j7 + li $t7, 1 +j7: bne $s1, $s3, j8 + li $t8, 1 +j8: bne $s3, $s1, end + li $t9, 1 - jump1: - li $t4, 0x754 - li $t5, 555 - bne $t0, $t2, jump2 +end: jr $ra diff --git a/tests/arch/mips/instructions/test_mips_instruction_009.s b/tests/arch/mips/instructions/test_mips_instruction_009.s index 1db9d8bf7..0a9abf99c 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_009.s +++ b/tests/arch/mips/instructions/test_mips_instruction_009.s @@ -5,19 +5,30 @@ .text main: - li $t0, 361 - li $t1, 2 - li $t2, 5 - li $t3, 0x44562 - blt $t0, $t2, jump1 - blt $t1, $t0, jump1 + li $s0, -40 + li $s1, -10 + li $s2, 15 + li $s3, 32 - jump2: - li $t6, 34 - li $v0, 10 - syscall + blt $s0, $s0, j0 + li $t0, 1 +j0: blt $s0, $s1, j1 + li $t1, 1 +j1: blt $s1, $s0, j2 + li $t2, 1 +j2: blt $s2, $s2, j3 + li $t3, 1 +j3: blt $s2, $s3, j4 + li $t4, 1 +j4: blt $s3, $s2, j5 + li $t5, 1 +j5: blt $s0, $s2, j6 + li $t6, 1 +j6: blt $s2, $s0, j7 + li $t7, 1 +j7: blt $s1, $s3, j8 + li $t8, 1 +j8: blt $s3, $s1, end + li $t9, 1 - jump1: - li $t4, 11 - li $t5, 555 - blt $t4, $t5, jump2 +end: jr $ra diff --git a/tests/arch/mips/instructions/test_mips_instruction_010.s b/tests/arch/mips/instructions/test_mips_instruction_010.s index 0340eec1a..e8fd815f5 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_010.s +++ b/tests/arch/mips/instructions/test_mips_instruction_010.s @@ -5,19 +5,30 @@ .text main: - li $t0, 361 - li $t1, 2 - li $t2, 5 - li $t3, 0x44562 - bge $t0, $t3, jump1 - bge $t3, $t0, jump1 + li $s0, -40 + li $s1, -10 + li $s2, 15 + li $s3, 32 - jump2: - li $t6, 34 - li $v0, 10 - syscall + bge $s0, $s0, j0 + li $t0, 1 +j0: bge $s0, $s1, j1 + li $t1, 1 +j1: bge $s1, $s0, j2 + li $t2, 1 +j2: bge $s2, $s2, j3 + li $t3, 1 +j3: bge $s2, $s3, j4 + li $t4, 1 +j4: bge $s3, $s2, j5 + li $t5, 1 +j5: bge $s0, $s2, j6 + li $t6, 1 +j6: bge $s2, $s0, j7 + li $t7, 1 +j7: bge $s1, $s3, j8 + li $t8, 1 +j8: bge $s3, $s1, end + li $t9, 1 - jump1: - li $t4, 0x754 - li $t5, 555 - bge $t4, $t5, jump2 +end: jr $ra diff --git a/tests/arch/mips/instructions/test_mips_instruction_011.s b/tests/arch/mips/instructions/test_mips_instruction_011.s index a12ad0d9b..ab3b572c4 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_011.s +++ b/tests/arch/mips/instructions/test_mips_instruction_011.s @@ -5,19 +5,30 @@ .text main: - li $t0, 361 - li $t1, 2 - li $t2, 5 - li $t3, 0x44562 - bltu $t0, $t2, jump1 - bltu $t1, $t0, jump1 + li $s0, -40 + li $s1, -10 + li $s2, 15 + li $s3, 32 - jump2: - li $t6, 34 - li $v0, 10 - syscall + bltu $s0, $s0, j0 + li $t0, 1 +j0: bltu $s0, $s1, j1 + li $t1, 1 +j1: bltu $s1, $s0, j2 + li $t2, 1 +j2: bltu $s2, $s2, j3 + li $t3, 1 +j3: bltu $s2, $s3, j4 + li $t4, 1 +j4: bltu $s3, $s2, j5 + li $t5, 1 +j5: bltu $s0, $s2, j6 + li $t6, 1 +j6: bltu $s2, $s0, j7 + li $t7, 1 +j7: bltu $s1, $s3, j8 + li $t8, 1 +j8: bltu $s3, $s1, end + li $t9, 1 - jump1: - li $t4, 0x754 - li $t5, 555 - bltu $t5, $t4, jump2 +end: jr $ra diff --git a/tests/arch/mips/instructions/test_mips_instruction_012.s b/tests/arch/mips/instructions/test_mips_instruction_012.s index e6cecd784..1d1e51304 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_012.s +++ b/tests/arch/mips/instructions/test_mips_instruction_012.s @@ -5,19 +5,30 @@ .text main: - li $t0, 361 - li $t1, 2 - li $t2, 5 - li $t3, 0x44562 - bgeu $t0, $t3, jump1 - bgeu $t3, $t2, jump1 + li $s0, -40 + li $s1, -10 + li $s2, 15 + li $s3, 32 - jump2: - li $t6, 34 - li $v0, 10 - syscall + bgeu $s0, $s0, j0 + li $t0, 1 +j0: bgeu $s0, $s1, j1 + li $t1, 1 +j1: bgeu $s1, $s0, j2 + li $t2, 1 +j2: bgeu $s2, $s2, j3 + li $t3, 1 +j3: bgeu $s2, $s3, j4 + li $t4, 1 +j4: bgeu $s3, $s2, j5 + li $t5, 1 +j5: bgeu $s0, $s2, j6 + li $t6, 1 +j6: bgeu $s2, $s0, j7 + li $t7, 1 +j7: bgeu $s1, $s3, j8 + li $t8, 1 +j8: bgeu $s3, $s1, end + li $t9, 1 - jump1: - li $t4, 0x754 - li $t5, 555 - bgeu $t4, $t5, jump2 +end: jr $ra diff --git a/tests/arch/mips/instructions/test_mips_instruction_042.s b/tests/arch/mips/instructions/test_mips_instruction_042.s index a4658fc3e..bd5e0c85a 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_042.s +++ b/tests/arch/mips/instructions/test_mips_instruction_042.s @@ -5,19 +5,30 @@ .text main: - li $t0, 882 - li $t1, 881 - li $t2, 5 - li $t3, 543 - bgt $t1, $t0, jump1 - bgt $t0, $t3, jump1 + li $s0, -40 + li $s1, -10 + li $s2, 15 + li $s3, 32 - jump2: - li $t6, 34 - li $v0, 10 - syscall + bgt $s0, $s0, j0 + li $t0, 1 +j0: bgt $s0, $s1, j1 + li $t1, 1 +j1: bgt $s1, $s0, j2 + li $t2, 1 +j2: bgt $s2, $s2, j3 + li $t3, 1 +j3: bgt $s2, $s3, j4 + li $t4, 1 +j4: bgt $s3, $s2, j5 + li $t5, 1 +j5: bgt $s0, $s2, j6 + li $t6, 1 +j6: bgt $s2, $s0, j7 + li $t7, 1 +j7: bgt $s1, $s3, j8 + li $t8, 1 +j8: bgt $s3, $s1, end + li $t9, 1 - jump1: - li $t4, 11 - li $t5, 555 - bgt $t5, $t4, jump2 +end: jr $ra diff --git a/tests/arch/mips/instructions/test_mips_instruction_043.s b/tests/arch/mips/instructions/test_mips_instruction_043.s index 8eaf28802..b93bf6ec3 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_043.s +++ b/tests/arch/mips/instructions/test_mips_instruction_043.s @@ -5,19 +5,30 @@ .text main: - li $t0, -882 - li $t1, -881 - li $t2, 5 - li $t3, 543 - bgtu $t0, $t1, jump1 - bgtu $t3, $t2, jump1 + li $s0, -40 + li $s1, -10 + li $s2, 15 + li $s3, 32 - jump2: - li $t6, 34 - li $v0, 10 - syscall + bgtu $s0, $s0, j0 + li $t0, 1 +j0: bgtu $s0, $s1, j1 + li $t1, 1 +j1: bgtu $s1, $s0, j2 + li $t2, 1 +j2: bgtu $s2, $s2, j3 + li $t3, 1 +j3: bgtu $s2, $s3, j4 + li $t4, 1 +j4: bgtu $s3, $s2, j5 + li $t5, 1 +j5: bgtu $s0, $s2, j6 + li $t6, 1 +j6: bgtu $s2, $s0, j7 + li $t7, 1 +j7: bgtu $s1, $s3, j8 + li $t8, 1 +j8: bgtu $s3, $s1, end + li $t9, 1 - jump1: - li $t4, 11 - li $t5, 555 - bgtu $t5, $t4, jump2 +end: jr $ra diff --git a/tests/arch/mips/instructions/test_mips_instruction_044.s b/tests/arch/mips/instructions/test_mips_instruction_044.s index b3d941fdd..9885838e7 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_044.s +++ b/tests/arch/mips/instructions/test_mips_instruction_044.s @@ -5,19 +5,30 @@ .text main: - li $t0, 882 - li $t1, 881 - li $t2, 5 - li $t3, 543 - ble $t0, $t1, jump1 - ble $t2, $t3, jump1 + li $s0, -40 + li $s1, -10 + li $s2, 15 + li $s3, 32 - jump2: - li $t6, 34 - li $v0, 10 - syscall + ble $s0, $s0, j0 + li $t0, 1 +j0: ble $s0, $s1, j1 + li $t1, 1 +j1: ble $s1, $s0, j2 + li $t2, 1 +j2: ble $s2, $s2, j3 + li $t3, 1 +j3: ble $s2, $s3, j4 + li $t4, 1 +j4: ble $s3, $s2, j5 + li $t5, 1 +j5: ble $s0, $s2, j6 + li $t6, 1 +j6: ble $s2, $s0, j7 + li $t7, 1 +j7: ble $s1, $s3, j8 + li $t8, 1 +j8: ble $s3, $s1, end + li $t9, 1 - jump1: - li $t4, 11 - li $t5, 555 - ble $t4, $t5, jump2 +end: jr $ra diff --git a/tests/arch/mips/instructions/test_mips_instruction_045.s b/tests/arch/mips/instructions/test_mips_instruction_045.s index 2e586c4f4..a2a90b916 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_045.s +++ b/tests/arch/mips/instructions/test_mips_instruction_045.s @@ -5,19 +5,30 @@ .text main: - li $t0, -882 - li $t1, -881 - li $t2, 5 - li $t3, -543 - bleu $t1, $t0, jump1 - bleu $t1, $t3, jump1 + li $s0, -40 + li $s1, -10 + li $s2, 15 + li $s3, 32 - jump2: - li $t6, 34 - li $v0, 10 - syscall + bleu $s0, $s0, j0 + li $t0, 1 +j0: bleu $s0, $s1, j1 + li $t1, 1 +j1: bleu $s1, $s0, j2 + li $t2, 1 +j2: bleu $s2, $s2, j3 + li $t3, 1 +j3: bleu $s2, $s3, j4 + li $t4, 1 +j4: bleu $s3, $s2, j5 + li $t5, 1 +j5: bleu $s0, $s2, j6 + li $t6, 1 +j6: bleu $s2, $s0, j7 + li $t7, 1 +j7: bleu $s1, $s3, j8 + li $t8, 1 +j8: bleu $s3, $s1, end + li $t9, 1 - jump1: - li $t4, 11 - li $t5, -555 - bleu $t5, $t4, jump2 +end: jr $ra diff --git a/tests/arch/mips/instructions/test_mips_instruction_051.s b/tests/arch/mips/instructions/test_mips_instruction_051.s index 061fd3373..28d33774b 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_051.s +++ b/tests/arch/mips/instructions/test_mips_instruction_051.s @@ -5,16 +5,14 @@ .text main: - li $t0, 1 - li $t1, 0 - li $t2, -1 - beqz $t1, jump1 + li $s0, -10 + li $s1, 15 - jump2: - li $t6, 34 - li $v0, 10 - syscall + beqz $s0, j0 + li $t0, 1 +j0: beqz $s1, j1 + li $t1, 1 +j1: beqz $0, end + li $t2, 1 - jump1: - li $t4, 0 - beqz $t4, jump2 +end: jr $ra diff --git a/tests/arch/mips/instructions/test_mips_instruction_052.s b/tests/arch/mips/instructions/test_mips_instruction_052.s index 4b5d9025d..b2c4476aa 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_052.s +++ b/tests/arch/mips/instructions/test_mips_instruction_052.s @@ -5,16 +5,14 @@ .text main: - li $t0, 1 - li $t1, 0 - bgez $t1, jump1 - bgez $t0, jump1 + li $s0, -10 + li $s1, 15 - jump2: - li $t6, 34 - li $v0, 10 - syscall + bgez $s0, j0 + li $t0, 1 +j0: bgez $s1, j1 + li $t1, 1 +j1: bgez $0, end + li $t2, 1 - jump1: - li $t4, 2 - bgez $t4, jump2 +end: jr $ra diff --git a/tests/arch/mips/instructions/test_mips_instruction_053.s b/tests/arch/mips/instructions/test_mips_instruction_053.s index bd616b8a4..0c5f02b1e 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_053.s +++ b/tests/arch/mips/instructions/test_mips_instruction_053.s @@ -5,16 +5,19 @@ .text main: - li $t0, 1 - li $t1, 0 - bgezal $t1, jump1 - bgezal $t0, jump1 + li $s0, -10 + li $s1, 15 + move $t4, $ra - jump2: - li $t6, 34 - li $v0, 10 - syscall + bgezal $s0, j0 + li $t0, 1 +j0: move $t5, $ra + bgezal $s1, j1 + li $t1, 1 +j1: move $t6, $ra + bgezal $0, end + li $t2, 1 +end: move $t7, $ra - jump1: - li $t4, 2 - bgezal $t4, jump2 + move $ra, $t4 + jr $ra diff --git a/tests/arch/mips/instructions/test_mips_instruction_054.s b/tests/arch/mips/instructions/test_mips_instruction_054.s index 5ef6f8858..ff25bfbc2 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_054.s +++ b/tests/arch/mips/instructions/test_mips_instruction_054.s @@ -5,16 +5,14 @@ .text main: - li $t0, 1 - li $t1, 0 - bgtz $t1, jump1 - bgtz $t0, jump1 + li $s0, -10 + li $s1, 15 - jump2: - li $t6, 34 - li $v0, 10 - syscall + bgtz $s0, j0 + li $t0, 1 +j0: bgtz $s1, j1 + li $t1, 1 +j1: bgtz $0, end + li $t2, 1 - jump1: - li $t4, 2 - bgtz $t4, jump2 +end: jr $ra diff --git a/tests/arch/mips/instructions/test_mips_instruction_055.s b/tests/arch/mips/instructions/test_mips_instruction_055.s index 0abfb5f6f..4828fb850 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_055.s +++ b/tests/arch/mips/instructions/test_mips_instruction_055.s @@ -5,16 +5,14 @@ .text main: - li $t0, 1 - li $t1, -1 - blez $t0, jump1 - blez $t1, jump1 + li $s0, -10 + li $s1, 15 - jump2: - li $t6, 34 - li $v0, 10 - syscall + blez $s0, j0 + li $t0, 1 +j0: blez $s1, j1 + li $t1, 1 +j1: blez $0, end + li $t2, 1 - jump1: - li $t4, 0 - blez $t4, jump2 +end: jr $ra diff --git a/tests/arch/mips/instructions/test_mips_instruction_056.s b/tests/arch/mips/instructions/test_mips_instruction_056.s index 966a2dcec..ebbfbea42 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_056.s +++ b/tests/arch/mips/instructions/test_mips_instruction_056.s @@ -5,18 +5,14 @@ .text main: - li $t0, 882 - li $t1, 881 - li $t2, 543 - blt $t0, $t1, jump1 - blt $t2, $t1, jump1 + li $s0, -10 + li $s1, 15 - jump2: - li $t6, 34 - li $v0, 10 - syscall + bltz $s0, j0 + li $t0, 1 +j0: bltz $s1, j1 + li $t1, 1 +j1: bltz $0, end + li $t2, 1 - jump1: - li $t4, 11 - li $t5, 555 - blt $t4, $t5, jump2 +end: jr $ra diff --git a/tests/arch/mips/instructions/test_mips_instruction_057.s b/tests/arch/mips/instructions/test_mips_instruction_057.s index 8ecbe5dd5..37bce784f 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_057.s +++ b/tests/arch/mips/instructions/test_mips_instruction_057.s @@ -5,17 +5,14 @@ .text main: - li $t0, 1 - li $t1, 0 - li $t2, -1 - bnez $t0, jump1 + li $s0, -10 + li $s1, 15 - jump2: - li $t6, 34 - li $v0, 10 - syscall + bnez $s0, j0 + li $t0, 1 +j0: bnez $s1, j1 + li $t1, 1 +j1: bnez $0, end + li $t2, 1 - jump1: - li $t4, 235363 - li $t5, 0xAA - bnez $t4, jump2 +end: jr $ra diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_007.s b/tests/arch/riscv/instructions/test_riscv_instruction_007.s index cf3a3dea5..0d7cc9674 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_007.s +++ b/tests/arch/riscv/instructions/test_riscv_instruction_007.s @@ -5,19 +5,30 @@ .text main: - li x5, 0x44562 - li x6, 2 - li x7, 5 - li x8, 0x44562 - beq x7, x5, jump1 - beq x5, x6, jump1 + li t0, -40 + li t1, -10 + li t2, 15 + li t3, 32 - jump2: - li t3, 34 - li a7, 10 - ecall + beq t0, t0, j0 + li s0, 1 +j0: beq t0, t1, j1 + li s1, 1 +j1: beq t1, t0, j2 + li s2, 1 +j2: beq t2, t2, j3 + li s3, 1 +j3: beq t2, t3, j4 + li s4, 1 +j4: beq t3, t2, j5 + li s5, 1 +j5: beq t0, t2, j6 + li s6, 1 +j6: beq t2, t0, j7 + li s7, 1 +j7: beq t1, t3, j8 + li s8, 1 +j8: beq t3, t1, end + li s9, 1 - jump1: - li x5, 11 - li x6, 555 - beq x0, x0, jump2 +end: jr ra diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_008.s b/tests/arch/riscv/instructions/test_riscv_instruction_008.s index 512216c24..f6b2657e0 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_008.s +++ b/tests/arch/riscv/instructions/test_riscv_instruction_008.s @@ -5,18 +5,30 @@ .text main: - li x5, 361 - li x6, 2 - li x7, 5 - li x8, 0x44562 - bne x5, x7, jump1 + li t0, -40 + li t1, -10 + li t2, 15 + li t3, 32 - jump2: - li t3, 34 - li a7, 10 - ecall + bne t0, t0, j0 + li s0, 1 +j0: bne t0, t1, j1 + li s1, 1 +j1: bne t1, t0, j2 + li s2, 1 +j2: bne t2, t2, j3 + li s3, 1 +j3: bne t2, t3, j4 + li s4, 1 +j4: bne t3, t2, j5 + li s5, 1 +j5: bne t0, t2, j6 + li s6, 1 +j6: bne t2, t0, j7 + li s7, 1 +j7: bne t1, t3, j8 + li s8, 1 +j8: bne t3, t1, end + li s9, 1 - jump1: - li x5, 0x754 - li x6, 555 - bne x5, x6, jump2 +end: jr ra diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_009.s b/tests/arch/riscv/instructions/test_riscv_instruction_009.s index ff148e7f8..aaa296f7a 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_009.s +++ b/tests/arch/riscv/instructions/test_riscv_instruction_009.s @@ -5,19 +5,30 @@ .text main: - li x5, 361 - li x6, 2 - li x7, 5 - li x8, 0x44562 - blt x5, x7, jump1 - blt x6, x5, jump1 + li t0, -40 + li t1, -10 + li t2, 15 + li t3, 32 - jump2: - li t3, 34 - li a7, 10 - ecall + blt t0, t0, j0 + li s0, 1 +j0: blt t0, t1, j1 + li s1, 1 +j1: blt t1, t0, j2 + li s2, 1 +j2: blt t2, t2, j3 + li s3, 1 +j3: blt t2, t3, j4 + li s4, 1 +j4: blt t3, t2, j5 + li s5, 1 +j5: blt t0, t2, j6 + li s6, 1 +j6: blt t2, t0, j7 + li s7, 1 +j7: blt t1, t3, j8 + li s8, 1 +j8: blt t3, t1, end + li s9, 1 - jump1: - li x9, 0x754 - li x10, 555 - blt x10, x9, jump2 +end: jr ra diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_010.s b/tests/arch/riscv/instructions/test_riscv_instruction_010.s index 0169ef8bd..6463d2a44 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_010.s +++ b/tests/arch/riscv/instructions/test_riscv_instruction_010.s @@ -5,20 +5,30 @@ .text main: - li x5, 361 - li x6, 2 - li x7, 5 - li x8, 0x44562 - bge x5, x8, jump1 - bge x8, x5, jump1 - - jump2: - li t3, 34 - li a7, 10 - ecall + li t0, -40 + li t1, -10 + li t2, 15 + li t3, 32 - jump1: - li x5, 0x754 - li t6, 555 - bge x5, x6, jump2 + bge t0, t0, j0 + li s0, 1 +j0: bge t0, t1, j1 + li s1, 1 +j1: bge t1, t0, j2 + li s2, 1 +j2: bge t2, t2, j3 + li s3, 1 +j3: bge t2, t3, j4 + li s4, 1 +j4: bge t3, t2, j5 + li s5, 1 +j5: bge t0, t2, j6 + li s6, 1 +j6: bge t2, t0, j7 + li s7, 1 +j7: bge t1, t3, j8 + li s8, 1 +j8: bge t3, t1, end + li s9, 1 +end: jr ra diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_011.s b/tests/arch/riscv/instructions/test_riscv_instruction_011.s index 63348a230..d3e9ca304 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_011.s +++ b/tests/arch/riscv/instructions/test_riscv_instruction_011.s @@ -5,19 +5,30 @@ .text main: - li x5, 361 - li x6, 2 - li x7, 5 - li x8, 0x44562 - bltu x5, x7, jump1 - bltu x6, x5, jump1 + li t0, -40 + li t1, -10 + li t2, 15 + li t3, 32 - jump2: - li t3, 34 - li a7, 10 - ecall + bltu t0, t0, j0 + li s0, 1 +j0: bltu t0, t1, j1 + li s1, 1 +j1: bltu t1, t0, j2 + li s2, 1 +j2: bltu t2, t2, j3 + li s3, 1 +j3: bltu t2, t3, j4 + li s4, 1 +j4: bltu t3, t2, j5 + li s5, 1 +j5: bltu t0, t2, j6 + li s6, 1 +j6: bltu t2, t0, j7 + li s7, 1 +j7: bltu t1, t3, j8 + li s8, 1 +j8: bltu t3, t1, end + li s9, 1 - jump1: - li x9, 0x754 - li x10, 555 - bltu x10, x9, jump2 +end: jr ra diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_012.s b/tests/arch/riscv/instructions/test_riscv_instruction_012.s index 00dcd7b82..5b86789b4 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_012.s +++ b/tests/arch/riscv/instructions/test_riscv_instruction_012.s @@ -5,20 +5,30 @@ .text main: - li x5, 361 - li x6, 2 - li x7, 5 - li x8, 0x44562 - bgeu x5, x8, jump1 - bgeu x8, x5, jump1 - - jump2: - li t3, 34 - li a7, 10 - ecall + li t0, -40 + li t1, -10 + li t2, 15 + li t3, 32 - jump1: - li x5, 0x754 - li t6, 555 - bgeu x5, x6, jump2 + bgeu t0, t0, j0 + li s0, 1 +j0: bgeu t0, t1, j1 + li s1, 1 +j1: bgeu t1, t0, j2 + li s2, 1 +j2: bgeu t2, t2, j3 + li s3, 1 +j3: bgeu t2, t3, j4 + li s4, 1 +j4: bgeu t3, t2, j5 + li s5, 1 +j5: bgeu t0, t2, j6 + li s6, 1 +j6: bgeu t2, t0, j7 + li s7, 1 +j7: bgeu t1, t3, j8 + li s8, 1 +j8: bgeu t3, t1, end + li s9, 1 +end: jr ra diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_042.s b/tests/arch/riscv/instructions/test_riscv_instruction_042.s index ca3df7384..5e6cea4c0 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_042.s +++ b/tests/arch/riscv/instructions/test_riscv_instruction_042.s @@ -5,19 +5,30 @@ .text main: - li x5, 882 - li x6, 881 - li x7, 5 - li x8, 543 - bgt x6, x5, jump1 - bgt x5, x8, jump1 + li t0, -40 + li t1, -10 + li t2, 15 + li t3, 32 - jump2: - li t3, 34 - li a7, 10 - ecall + bgt t0, t0, j0 + li s0, 1 +j0: bgt t0, t1, j1 + li s1, 1 +j1: bgt t1, t0, j2 + li s2, 1 +j2: bgt t2, t2, j3 + li s3, 1 +j3: bgt t2, t3, j4 + li s4, 1 +j4: bgt t3, t2, j5 + li s5, 1 +j5: bgt t0, t2, j6 + li s6, 1 +j6: bgt t2, t0, j7 + li s7, 1 +j7: bgt t1, t3, j8 + li s8, 1 +j8: bgt t3, t1, end + li s9, 1 - jump1: - li x5, 11 - li x6, 555 - bgt x6, x5, jump2 +end: jr ra diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_043.s b/tests/arch/riscv/instructions/test_riscv_instruction_043.s index 94823d18a..b67f6d2cf 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_043.s +++ b/tests/arch/riscv/instructions/test_riscv_instruction_043.s @@ -5,19 +5,30 @@ .text main: - li x5, -882 - li x6, -881 - li x7, 5 - li x8, 543 - bgtu x5, x6, jump1 - bgtu x8, x7, jump1 + li t0, -40 + li t1, -10 + li t2, 15 + li t3, 32 - jump2: - li t3, 34 - li a7, 10 - ecall + bgtu t0, t0, j0 + li s0, 1 +j0: bgtu t0, t1, j1 + li s1, 1 +j1: bgtu t1, t0, j2 + li s2, 1 +j2: bgtu t2, t2, j3 + li s3, 1 +j3: bgtu t2, t3, j4 + li s4, 1 +j4: bgtu t3, t2, j5 + li s5, 1 +j5: bgtu t0, t2, j6 + li s6, 1 +j6: bgtu t2, t0, j7 + li s7, 1 +j7: bgtu t1, t3, j8 + li s8, 1 +j8: bgtu t3, t1, end + li s9, 1 - jump1: - li x5, 11 - li x6, 555 - bgtu x6, x5, jump2 +end: jr ra diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_044.s b/tests/arch/riscv/instructions/test_riscv_instruction_044.s index 3d01c9b49..6b84468ac 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_044.s +++ b/tests/arch/riscv/instructions/test_riscv_instruction_044.s @@ -5,19 +5,30 @@ .text main: - li x5, 882 - li x6, 881 - li x7, 5 - li x8, 543 - ble x5, x6, jump1 - ble x7, x8, jump1 + li t0, -40 + li t1, -10 + li t2, 15 + li t3, 32 - jump2: - li t3, 34 - li a7, 10 - ecall + ble t0, t0, j0 + li s0, 1 +j0: ble t0, t1, j1 + li s1, 1 +j1: ble t1, t0, j2 + li s2, 1 +j2: ble t2, t2, j3 + li s3, 1 +j3: ble t2, t3, j4 + li s4, 1 +j4: ble t3, t2, j5 + li s5, 1 +j5: ble t0, t2, j6 + li s6, 1 +j6: ble t2, t0, j7 + li s7, 1 +j7: ble t1, t3, j8 + li s8, 1 +j8: ble t3, t1, end + li s9, 1 - jump1: - li x5, 11 - li x6, 555 - ble x5, x6, jump2 +end: jr ra diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_045.s b/tests/arch/riscv/instructions/test_riscv_instruction_045.s index c5cd3d611..1fbdaaa97 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_045.s +++ b/tests/arch/riscv/instructions/test_riscv_instruction_045.s @@ -5,19 +5,30 @@ .text main: - li x5, -882 - li x6, -881 - li x7, 5 - li x8, -543 - ble x6, x5, jump1 - ble x6, x8, jump1 + li t0, -40 + li t1, -10 + li t2, 15 + li t3, 32 - jump2: - li t3, 34 - li a7, 10 - ecall + bleu t0, t0, j0 + li s0, 1 +j0: bleu t0, t1, j1 + li s1, 1 +j1: bleu t1, t0, j2 + li s2, 1 +j2: bleu t2, t2, j3 + li s3, 1 +j3: bleu t2, t3, j4 + li s4, 1 +j4: bleu t3, t2, j5 + li s5, 1 +j5: bleu t0, t2, j6 + li s6, 1 +j6: bleu t2, t0, j7 + li s7, 1 +j7: bleu t1, t3, j8 + li s8, 1 +j8: bleu t3, t1, end + li s9, 1 - jump1: - li x5, 11 - li x6, -555 - ble x6, x5, jump2 +end: jr ra From 8161c919dde441a54e9bbd47d6edbf789605afc5 Mon Sep 17 00:00:00 2001 From: ALVAROPING1 Date: Tue, 24 Mar 2026 12:40:00 +0100 Subject: [PATCH 71/85] fix(riscv): fix incorrect definition of bgez pseudoinstruction --- architecture/RISCV/RV32IMFD.yml | 2 +- architecture/RISCV/RV64IMFD.yml | 2 +- architecture/RISCV/SRV32.yml | 2 +- architecture/RISCV/SRV64.yml | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/architecture/RISCV/RV32IMFD.yml b/architecture/RISCV/RV32IMFD.yml index 69adc05b1..a08013f0c 100644 --- a/architecture/RISCV/RV32IMFD.yml +++ b/architecture/RISCV/RV32IMFD.yml @@ -3713,7 +3713,7 @@ pseudoinstructions: - field: off type: offset_bytes definition: | - bge reg1, x0, off; + bge rs1, x0, off; help: Take the branch if the value in register rs1 is greater or equal to 0. - name: bgt diff --git a/architecture/RISCV/RV64IMFD.yml b/architecture/RISCV/RV64IMFD.yml index 2373b993f..6f20ce849 100644 --- a/architecture/RISCV/RV64IMFD.yml +++ b/architecture/RISCV/RV64IMFD.yml @@ -3906,7 +3906,7 @@ pseudoinstructions: - field: off type: offset_bytes definition: | - bge reg1, x0, off; + bge rs1, x0, off; help: Take the branch if the value in register rs1 is zero. - name: bgt diff --git a/architecture/RISCV/SRV32.yml b/architecture/RISCV/SRV32.yml index 527d075d5..1bc57cd10 100644 --- a/architecture/RISCV/SRV32.yml +++ b/architecture/RISCV/SRV32.yml @@ -4230,7 +4230,7 @@ pseudoinstructions: - field: off type: offset_bytes definition: | - bge reg1, x0, off; + bge rs1, x0, off; help: Take the branch if the value in register rs1 is zero. - name: bgt diff --git a/architecture/RISCV/SRV64.yml b/architecture/RISCV/SRV64.yml index 6a95634a6..ff392e157 100644 --- a/architecture/RISCV/SRV64.yml +++ b/architecture/RISCV/SRV64.yml @@ -4218,7 +4218,7 @@ pseudoinstructions: - field: off type: offset_bytes definition: | - bge reg1, x0, off; + bge rs1, x0, off; help: Take the branch if the value in register rs1 is zero. - name: bgt From 315d58056c441aeeebb0d7c36a16c558574a9314 Mon Sep 17 00:00:00 2001 From: ALVAROPING1 Date: Tue, 24 Mar 2026 12:40:28 +0100 Subject: [PATCH 72/85] tests(riscv): add missing comparison with 0 conditional branch tests --- .../test_riscv_instruction_066.s.snap | 46 +++++++++++++++++++ .../test_riscv_instruction_067.s.snap | 45 ++++++++++++++++++ .../test_riscv_instruction_068.s.snap | 46 +++++++++++++++++++ .../test_riscv_instruction_069.s.snap | 45 ++++++++++++++++++ .../test_riscv_instruction_070.s.snap | 46 +++++++++++++++++++ .../test_riscv_instruction_071.s.snap | 45 ++++++++++++++++++ .../instructions/test_riscv_instruction_066.s | 18 ++++++++ .../instructions/test_riscv_instruction_067.s | 18 ++++++++ .../instructions/test_riscv_instruction_068.s | 18 ++++++++ .../instructions/test_riscv_instruction_069.s | 18 ++++++++ .../instructions/test_riscv_instruction_070.s | 18 ++++++++ .../instructions/test_riscv_instruction_071.s | 18 ++++++++ 12 files changed, 381 insertions(+) create mode 100644 tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_066.s.snap create mode 100644 tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_067.s.snap create mode 100644 tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_068.s.snap create mode 100644 tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_069.s.snap create mode 100644 tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_070.s.snap create mode 100644 tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_071.s.snap create mode 100644 tests/arch/riscv/instructions/test_riscv_instruction_066.s create mode 100644 tests/arch/riscv/instructions/test_riscv_instruction_067.s create mode 100644 tests/arch/riscv/instructions/test_riscv_instruction_068.s create mode 100644 tests/arch/riscv/instructions/test_riscv_instruction_069.s create mode 100644 tests/arch/riscv/instructions/test_riscv_instruction_070.s create mode 100644 tests/arch/riscv/instructions/test_riscv_instruction_071.s diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_066.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_066.s.snap new file mode 100644 index 000000000..79925257c --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_066.s.snap @@ -0,0 +1,46 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_066.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 255, + "1": 96, + "10": 4, + "11": 99, + "13": 16, + "14": 2, + "15": 147, + "17": 4, + "18": 132, + "19": 99, + "2": 4, + "21": 16, + "22": 3, + "23": 19, + "26": 4, + "27": 99, + "29": 16, + "3": 19, + "30": 3, + "31": 147, + "34": 128, + "35": 103, + "5": 240, + "6": 4, + "7": 147, + "9": 4, + }, + registers: { + "x5,t0": "0x1", + "x6,t1": "0x1", + "x8,fp,s0": "0xfffffff6", + "x9,s1": "0xf", + mtime: "0x8", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_067.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_067.s.snap new file mode 100644 index 000000000..4f66d5b21 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_067.s.snap @@ -0,0 +1,45 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_067.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 255, + "1": 96, + "10": 84, + "11": 99, + "13": 16, + "14": 2, + "15": 147, + "17": 4, + "18": 212, + "19": 99, + "2": 4, + "21": 16, + "22": 3, + "23": 19, + "26": 84, + "27": 99, + "29": 16, + "3": 19, + "30": 3, + "31": 147, + "34": 128, + "35": 103, + "5": 240, + "6": 4, + "7": 147, + "9": 4, + }, + registers: { + "x5,t0": "0x1", + "x8,fp,s0": "0xfffffff6", + "x9,s1": "0xf", + mtime: "0x7", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_068.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_068.s.snap new file mode 100644 index 000000000..eb123788e --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_068.s.snap @@ -0,0 +1,46 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_068.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 255, + "1": 96, + "10": 68, + "11": 99, + "13": 16, + "14": 2, + "15": 147, + "17": 144, + "18": 68, + "19": 99, + "2": 4, + "21": 16, + "22": 3, + "23": 19, + "26": 68, + "27": 99, + "29": 16, + "3": 19, + "30": 3, + "31": 147, + "34": 128, + "35": 103, + "5": 240, + "6": 4, + "7": 147, + "9": 128, + }, + registers: { + "x5,t0": "0x1", + "x7,t2": "0x1", + "x8,fp,s0": "0xfffffff6", + "x9,s1": "0xf", + mtime: "0x8", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_069.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_069.s.snap new file mode 100644 index 000000000..8d818f7d5 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_069.s.snap @@ -0,0 +1,45 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_069.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 255, + "1": 96, + "10": 84, + "11": 99, + "13": 16, + "14": 2, + "15": 147, + "17": 144, + "18": 84, + "19": 99, + "2": 4, + "21": 16, + "22": 3, + "23": 19, + "26": 84, + "27": 99, + "29": 16, + "3": 19, + "30": 3, + "31": 147, + "34": 128, + "35": 103, + "5": 240, + "6": 4, + "7": 147, + "9": 128, + }, + registers: { + "x6,t1": "0x1", + "x8,fp,s0": "0xfffffff6", + "x9,s1": "0xf", + mtime: "0x7", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_070.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_070.s.snap new file mode 100644 index 000000000..4c9749394 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_070.s.snap @@ -0,0 +1,46 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_070.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 255, + "1": 96, + "10": 68, + "11": 99, + "13": 16, + "14": 2, + "15": 147, + "17": 4, + "18": 196, + "19": 99, + "2": 4, + "21": 16, + "22": 3, + "23": 19, + "26": 68, + "27": 99, + "29": 16, + "3": 19, + "30": 3, + "31": 147, + "34": 128, + "35": 103, + "5": 240, + "6": 4, + "7": 147, + "9": 4, + }, + registers: { + "x6,t1": "0x1", + "x7,t2": "0x1", + "x8,fp,s0": "0xfffffff6", + "x9,s1": "0xf", + mtime: "0x8", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_071.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_071.s.snap new file mode 100644 index 000000000..d6b3e9bc8 --- /dev/null +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_071.s.snap @@ -0,0 +1,45 @@ +export const snapshot = {}; + +snapshot[`riscv/instructions/test_riscv_instruction_071.s 1`] = ` +{ + display: "", + error: false, + keyboard: "", + memory: { + "0": 255, + "1": 96, + "10": 20, + "11": 99, + "13": 16, + "14": 2, + "15": 147, + "17": 4, + "18": 148, + "19": 99, + "2": 4, + "21": 16, + "22": 3, + "23": 19, + "26": 20, + "27": 99, + "29": 16, + "3": 19, + "30": 3, + "31": 147, + "34": 128, + "35": 103, + "5": 240, + "6": 4, + "7": 147, + "9": 4, + }, + registers: { + "x7,t2": "0x1", + "x8,fp,s0": "0xfffffff6", + "x9,s1": "0xf", + mtime: "0x7", + pc: "0xfffffffe", + }, + sentinel_errors: [], +} +`; diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_066.s b/tests/arch/riscv/instructions/test_riscv_instruction_066.s new file mode 100644 index 000000000..6f8c6b60a --- /dev/null +++ b/tests/arch/riscv/instructions/test_riscv_instruction_066.s @@ -0,0 +1,18 @@ + +# +# Creator (https://creatorsim.github.io/creator/) +# + +.text + main: + li s0, -10 + li s1, 15 + + beqz s0, j0 + li t0, 1 +j0: beqz s1, j1 + li t1, 1 +j1: beqz x0, end + li t2, 1 + +end: jr ra diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_067.s b/tests/arch/riscv/instructions/test_riscv_instruction_067.s new file mode 100644 index 000000000..60b9c325d --- /dev/null +++ b/tests/arch/riscv/instructions/test_riscv_instruction_067.s @@ -0,0 +1,18 @@ + +# +# Creator (https://creatorsim.github.io/creator/) +# + +.text + main: + li s0, -10 + li s1, 15 + + bgez s0, j0 + li t0, 1 +j0: bgez s1, j1 + li t1, 1 +j1: bgez x0, end + li t2, 1 + +end: jr ra diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_068.s b/tests/arch/riscv/instructions/test_riscv_instruction_068.s new file mode 100644 index 000000000..c83042bd2 --- /dev/null +++ b/tests/arch/riscv/instructions/test_riscv_instruction_068.s @@ -0,0 +1,18 @@ + +# +# Creator (https://creatorsim.github.io/creator/) +# + +.text + main: + li s0, -10 + li s1, 15 + + bgtz s0, j0 + li t0, 1 +j0: bgtz s1, j1 + li t1, 1 +j1: bgtz x0, end + li t2, 1 + +end: jr ra diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_069.s b/tests/arch/riscv/instructions/test_riscv_instruction_069.s new file mode 100644 index 000000000..447bd11c4 --- /dev/null +++ b/tests/arch/riscv/instructions/test_riscv_instruction_069.s @@ -0,0 +1,18 @@ + +# +# Creator (https://creatorsim.github.io/creator/) +# + +.text + main: + li s0, -10 + li s1, 15 + + blez s0, j0 + li t0, 1 +j0: blez s1, j1 + li t1, 1 +j1: blez x0, end + li t2, 1 + +end: jr ra diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_070.s b/tests/arch/riscv/instructions/test_riscv_instruction_070.s new file mode 100644 index 000000000..5318bf129 --- /dev/null +++ b/tests/arch/riscv/instructions/test_riscv_instruction_070.s @@ -0,0 +1,18 @@ + +# +# Creator (https://creatorsim.github.io/creator/) +# + +.text + main: + li s0, -10 + li s1, 15 + + bltz s0, j0 + li t0, 1 +j0: bltz s1, j1 + li t1, 1 +j1: bltz x0, end + li t2, 1 + +end: jr ra diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_071.s b/tests/arch/riscv/instructions/test_riscv_instruction_071.s new file mode 100644 index 000000000..d0e91ed9c --- /dev/null +++ b/tests/arch/riscv/instructions/test_riscv_instruction_071.s @@ -0,0 +1,18 @@ + +# +# Creator (https://creatorsim.github.io/creator/) +# + +.text + main: + li s0, -10 + li s1, 15 + + bnez s0, j0 + li t0, 1 +j0: bnez s1, j1 + li t1, 1 +j1: bnez x0, end + li t2, 1 + +end: jr ra From 897e32e56238e2b2ff67d5ea5853001b627e4424 Mon Sep 17 00:00:00 2001 From: ALVAROPING1 Date: Tue, 24 Mar 2026 13:03:39 +0100 Subject: [PATCH 73/85] fix(MIPS): fix lb/lh not sign-extending loaded values --- architecture/MIPS32.yml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/architecture/MIPS32.yml b/architecture/MIPS32.yml index bcf8f51a5..0dc2002ce 100644 --- a/architecture/MIPS32.yml +++ b/architecture/MIPS32.yml @@ -2364,7 +2364,8 @@ instructions: suffix: ) order: 3 definition: | - registers[reg1] = CAPI.MEM.read(registers[reg2]+val, 1, reg1, false); + const result = CAPI.MEM.read(registers[reg2]+val, 1, reg1, false); + registers[reg1] = CAPI.FP.int2uint(CAPI.FP.uint2int(result, 8)); - name: lbu template: Custom type: Memory access @@ -2484,7 +2485,8 @@ instructions: let addr = registers[reg2] + val; if (CAPI.VALIDATION.isMisaligned(addr, 2)) CAPI.VALIDATION.raise('The memory must be aligned'); - registers[reg1] = CAPI.MEM.read(addr, 2, reg1, false); + const result = CAPI.MEM.read(addr, 2, reg1, false); + registers[reg1] = CAPI.FP.int2uint(CAPI.FP.uint2int(result, 16)); - name: lhu template: Custom type: Memory access From 04a62feaed2f9a0d08b88c82156dde46671f5034 Mon Sep 17 00:00:00 2001 From: ALVAROPING1 Date: Tue, 24 Mar 2026 13:18:53 +0100 Subject: [PATCH 74/85] fix(MIPS): fix sb/sh not writing the correct bits to memory --- architecture/MIPS32.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/architecture/MIPS32.yml b/architecture/MIPS32.yml index 0dc2002ce..7c01aae82 100644 --- a/architecture/MIPS32.yml +++ b/architecture/MIPS32.yml @@ -3495,7 +3495,7 @@ instructions: stopbit: 0 order: 2 space: false - definition: "CAPI.MEM.write(registers[base]+off, 1, registers[rt], rt, 'byte', false);" + definition: "CAPI.MEM.write(registers[base]+off, 1, BigInt.asUintN(8, registers[rt]), rt, 'byte', false);" - name: sdc1 template: Custom type: Memory access @@ -3577,7 +3577,7 @@ instructions: let addr = registers[base] + off; if (CAPI.VALIDATION.isMisaligned(addr, 2)) CAPI.VALIDATION.raise('The memory must be aligned'); - CAPI.MEM.write(addr, 2, registers[rt], rt, 'half', false); + CAPI.MEM.write(addr, 2, BigInt.asUintN(16, registers[rt]), rt, 'half', false); - name: sll template: Custom type: Arithmetic integer From 8a0b64bfe87916dabf17f739cc64fae438495a53 Mon Sep 17 00:00:00 2001 From: ALVAROPING1 Date: Tue, 24 Mar 2026 13:28:26 +0100 Subject: [PATCH 75/85] tests: improve load/store byte/half signed/unsigned instruction tests --- .../examples/test_mips_example_013.s.snap | 2 +- .../test_mips_instruction_013.s.snap | 116 ++++++++++++------ .../test_mips_instruction_014.s.snap | 83 ++++++++----- .../examples/test_riscv_example_013.s.snap | 2 +- .../test_riscv_instruction_013.s.snap | 95 ++++++++------ .../test_riscv_instruction_014.s.snap | 79 +++++++----- .../correct/examples/test_mips_example_013.s | 2 +- .../instructions/test_mips_instruction_013.s | 15 ++- .../instructions/test_mips_instruction_014.s | 17 ++- .../correct/examples/test_riscv_example_013.s | 2 +- .../instructions/test_riscv_instruction_013.s | 13 +- .../instructions/test_riscv_instruction_014.s | 12 +- 12 files changed, 279 insertions(+), 159 deletions(-) diff --git a/tests/arch/__snapshots__/mips/correct/examples/test_mips_example_013.s.snap b/tests/arch/__snapshots__/mips/correct/examples/test_mips_example_013.s.snap index e1ad6b48b..54a59dbe0 100644 --- a/tests/arch/__snapshots__/mips/correct/examples/test_mips_example_013.s.snap +++ b/tests/arch/__snapshots__/mips/correct/examples/test_mips_example_013.s.snap @@ -11,7 +11,7 @@ snapshot[`mips/correct/examples/test_mips_example_013.s 1`] = ` "13": 32, "14": 64, "15": 32, - "16": 129, + "16": 145, "17": 4, "2097152": 83, "2097153": 116, diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_013.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_013.s.snap index c2afafd66..e5ced23d7 100644 --- a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_013.s.snap +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_013.s.snap @@ -9,46 +9,80 @@ snapshot[`mips/instructions/test_mips_instruction_013.s 1`] = ` "0": 60, "1": 1, "10": 64, - "100": 60, - "101": 1, - "103": 32, - "104": 52, - "105": 33, - "107": 12, - "109": 32, + "100": 133, + "101": 82, + "103": 2, + "104": 60, + "105": 1, + "107": 32, + "108": 52, + "109": 33, "11": 32, - "110": 200, - "111": 32, - "112": 163, - "113": 45, + "111": 8, + "112": 148, + "113": 51, "116": 60, "117": 1, "119": 32, "12": 60, "120": 52, "121": 33, - "123": 14, + "123": 12, "125": 32, "126": 200, "127": 32, - "128": 167, - "129": 47, + "128": 175, + "129": 43, "13": 1, - "132": 3, - "133": 224, - "135": 8, + "132": 60, + "133": 1, + "135": 32, + "136": 52, + "137": 33, + "139": 16, + "141": 32, + "142": 200, + "143": 32, + "144": 163, + "145": 45, + "148": 163, + "149": 48, "15": 32, + "151": 1, + "152": 60, + "153": 1, + "155": 32, + "156": 52, + "157": 33, + "159": 18, "16": 52, + "161": 32, + "162": 200, + "163": 32, + "164": 167, + "165": 47, + "168": 167, + "169": 50, "17": 33, + "171": 2, + "172": 3, + "173": 224, + "175": 8, "19": 4, "2097155": 14, "2097156": 127, + "2097157": 214, "2097158": 127, "2097159": 255, - "2097163": 14, - "2097164": 127, - "2097166": 127, - "2097167": 255, + "2097160": 207, + "2097161": 199, + "2097167": 14, + "2097168": 127, + "2097169": 214, + "2097170": 127, + "2097171": 255, + "2097172": 207, + "2097173": 199, "21": 32, "22": 72, "23": 32, @@ -83,39 +117,43 @@ snapshot[`mips/instructions/test_mips_instruction_013.s 1`] = ` "63": 4, "64": 144, "65": 46, - "68": 133, - "69": 79, + "68": 129, + "69": 48, + "71": 1, "72": 60, "73": 1, "75": 32, "76": 52, "77": 33, - "79": 6, - "80": 148, - "81": 56, - "84": 60, - "85": 1, - "87": 32, - "88": 52, - "89": 33, + "79": 5, + "80": 144, + "81": 49, + "84": 133, + "85": 79, + "88": 60, + "89": 1, "9": 32, - "91": 8, - "93": 32, - "94": 200, - "95": 32, - "96": 175, - "97": 43, + "91": 32, + "92": 52, + "93": 33, + "95": 6, + "96": 148, + "97": 56, }, registers: { - "1,at": "0x20000e", + "1,at": "0x200012", "10,t2": "0x200006", "11,t3": "0xe", "12,t4": "0xe", "13,t5": "0x7f", "14,t6": "0x7f", "15,t7": "0x7fff", + "16,s0": "0xffffffd6", + "17,s1": "0xd6", + "18,s2": "0xffffcfc7", + "19,s3": "0xcfc7", "24,t8": "0x7fff", - "25,t9": "0x20000e", + "25,t9": "0x200012", "8,t0": "0x200000", "9,t1": "0x200004", PC: "0xffffffff", diff --git a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_014.s.snap b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_014.s.snap index ad613abdf..67841c660 100644 --- a/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_014.s.snap +++ b/tests/arch/__snapshots__/mips/instructions/test_mips_instruction_014.s.snap @@ -17,51 +17,74 @@ snapshot[`mips/instructions/test_mips_instruction_014.s 1`] = ` "17": 33, "19": 2, "2097152": 127, - "2097154": 255, + "2097153": 214, + "2097154": 127, "2097155": 255, + "2097156": 207, + "2097157": 199, + "2097160": 127, + "2097161": 214, + "2097162": 127, + "2097163": 255, + "2097164": 207, + "2097165": 199, "21": 32, "22": 72, "23": 32, "24": 145, "25": 10, - "28": 149, - "29": 43, + "28": 145, + "29": 16, "3": 32, - "32": 60, - "33": 1, - "35": 32, - "36": 52, - "37": 33, - "39": 4, + "31": 1, + "32": 149, + "33": 43, + "36": 149, + "37": 49, + "39": 2, "4": 52, - "41": 32, - "42": 96, + "40": 60, + "41": 1, "43": 32, - "44": 161, - "45": 141, - "48": 60, - "49": 1, + "44": 52, + "45": 33, + "47": 8, + "49": 32, "5": 33, + "50": 96, "51": 32, - "52": 52, - "53": 33, - "55": 6, - "57": 32, - "58": 112, - "59": 32, - "60": 165, - "61": 207, - "64": 3, - "65": 224, - "67": 8, + "52": 161, + "53": 138, + "56": 161, + "57": 144, + "59": 1, + "60": 60, + "61": 1, + "63": 32, + "64": 52, + "65": 33, + "67": 10, + "69": 32, + "70": 112, + "71": 32, + "72": 165, + "73": 203, + "76": 165, + "77": 209, + "79": 2, + "80": 3, + "81": 224, + "83": 8, "9": 32, }, registers: { - "1,at": "0x200006", + "1,at": "0x20000a", "10,t2": "0x7f", - "11,t3": "0xffff", - "12,t4": "0x200004", - "14,t6": "0x200006", + "11,t3": "0x7fff", + "12,t4": "0x200008", + "14,t6": "0x20000a", + "16,s0": "0xd6", + "17,s1": "0xcfc7", "8,t0": "0x200000", "9,t1": "0x200002", PC: "0xffffffff", diff --git a/tests/arch/__snapshots__/riscv/correct/examples/test_riscv_example_013.s.snap b/tests/arch/__snapshots__/riscv/correct/examples/test_riscv_example_013.s.snap index 312fa8936..2945b12bf 100644 --- a/tests/arch/__snapshots__/riscv/correct/examples/test_riscv_example_013.s.snap +++ b/tests/arch/__snapshots__/riscv/correct/examples/test_riscv_example_013.s.snap @@ -10,7 +10,7 @@ snapshot[`riscv/correct/examples/test_riscv_example_013.s 1`] = ` "10": 130, "11": 147, "13": 2, - "14": 133, + "14": 197, "15": 3, "19": 115, "2": 8, diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_013.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_013.s.snap index 28d1fef2f..387107b8b 100644 --- a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_013.s.snap +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_013.s.snap @@ -20,12 +20,18 @@ snapshot[`riscv/instructions/test_riscv_instruction_013.s 1`] = ` "20": 255, "2097155": 14, "2097156": 127, + "2097157": 214, "2097158": 127, "2097159": 255, - "2097163": 14, - "2097164": 127, - "2097166": 127, - "2097167": 255, + "2097160": 207, + "2097161": 199, + "2097167": 14, + "2097168": 127, + "2097169": 214, + "2097170": 127, + "2097171": 255, + "2097172": 207, + "2097173": 199, "21": 99, "22": 131, "23": 147, @@ -36,54 +42,67 @@ snapshot[`riscv/instructions/test_riscv_instruction_013.s 1`] = ` "3": 151, "30": 5, "31": 3, - "33": 3, - "34": 150, - "35": 3, - "37": 32, - "38": 7, - "39": 23, - "40": 254, - "41": 71, - "42": 7, - "43": 19, - "45": 135, - "46": 32, - "47": 35, - "49": 32, + "33": 19, + "34": 5, + "35": 131, + "37": 3, + "38": 150, + "39": 3, + "41": 35, + "42": 150, + "43": 131, + "45": 32, + "46": 7, + "47": 23, + "48": 254, + "49": 7, "5": 2, "50": 7, - "51": 23, - "52": 253, - "53": 199, - "54": 7, - "55": 19, - "57": 167, - "59": 35, + "51": 19, + "53": 135, + "54": 32, + "55": 35, + "57": 32, + "58": 7, + "59": 23, "6": 130, - "61": 32, + "60": 253, + "61": 135, "62": 7, - "63": 23, - "64": 253, - "65": 39, - "66": 7, - "67": 19, - "69": 199, + "63": 19, + "65": 167, + "67": 35, + "69": 183, "7": 147, - "70": 16, - "71": 35, - "74": 128, - "75": 103, + "71": 163, + "73": 32, + "74": 7, + "75": 23, + "76": 252, + "77": 167, + "78": 7, + "79": 19, + "81": 199, + "82": 16, + "83": 35, + "85": 215, + "86": 17, + "87": 35, "9": 32, + "90": 128, + "91": 103, }, registers: { "x10,a0": "0x7f", + "x11,a1": "0xd6", "x12,a2": "0x7fff", - "x14,a4": "0x20000e", + "x13,a3": "0xcfc7", + "x14,a4": "0x200012", "x5,t0": "0x200000", "x6,t1": "0x200004", "x7,t2": "0x200006", "x8,fp,s0": "0xe", - mtime: "0x13", + mtime: "0x17", pc: "0xfffffffe", }, sentinel_errors: [], diff --git a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_014.s.snap b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_014.s.snap index a292e0e0c..f2cb72804 100644 --- a/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_014.s.snap +++ b/tests/arch/__snapshots__/riscv/instructions/test_riscv_instruction_014.s.snap @@ -18,48 +18,67 @@ snapshot[`riscv/instructions/test_riscv_instruction_014.s 1`] = ` "19": 3, "2": 3, "2097152": 127, - "2097154": 255, + "2097153": 214, + "2097154": 127, "2097155": 255, - "2097156": 127, - "2097158": 255, - "2097159": 255, - "21": 3, - "22": 214, - "23": 3, - "25": 32, - "26": 7, - "27": 23, - "28": 254, - "29": 199, + "2097156": 207, + "2097157": 199, + "2097158": 127, + "2097159": 214, + "2097160": 127, + "2097161": 255, + "2097162": 207, + "2097163": 199, + "21": 19, + "22": 69, + "23": 131, + "25": 3, + "26": 214, + "27": 3, + "29": 35, "3": 23, - "30": 7, - "31": 19, - "33": 167, - "35": 35, - "37": 32, + "30": 214, + "31": 131, + "33": 32, + "34": 7, + "35": 23, + "36": 254, + "37": 103, "38": 7, - "39": 23, - "40": 254, - "41": 39, - "42": 7, - "43": 19, - "45": 199, - "46": 16, - "47": 35, + "39": 19, + "41": 167, + "43": 35, + "45": 183, + "47": 163, + "49": 32, "5": 3, - "50": 128, - "51": 103, + "50": 7, + "51": 23, + "52": 253, + "53": 135, + "54": 7, + "55": 19, + "57": 199, + "58": 16, + "59": 35, "6": 3, + "61": 215, + "62": 17, + "63": 35, + "66": 128, + "67": 103, "7": 19, "9": 32, }, registers: { "x10,a0": "0x7f", - "x12,a2": "0xffff", - "x14,a4": "0x200006", + "x11,a1": "0xd6", + "x12,a2": "0x7fff", + "x13,a3": "0xcfc7", + "x14,a4": "0x200008", "x6,t1": "0x200000", "x7,t2": "0x200002", - mtime: "0xd", + mtime: "0x11", pc: "0xfffffffe", }, sentinel_errors: [], diff --git a/tests/arch/mips/correct/examples/test_mips_example_013.s b/tests/arch/mips/correct/examples/test_mips_example_013.s index 074a0c3c3..279860f79 100644 --- a/tests/arch/mips/correct/examples/test_mips_example_013.s +++ b/tests/arch/mips/correct/examples/test_mips_example_013.s @@ -9,7 +9,7 @@ .text main: li $v0, 1 la $t0, utf8 -loop: lb $a0, 0($t0) +loop: lbu $a0, 0($t0) syscall addi $t0, $t0, 1 bne $a0, $zero, loop diff --git a/tests/arch/mips/instructions/test_mips_instruction_013.s b/tests/arch/mips/instructions/test_mips_instruction_013.s index db2d72275..255a08455 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_013.s +++ b/tests/arch/mips/instructions/test_mips_instruction_013.s @@ -5,15 +5,16 @@ .data w1: .word 14 - b1: .byte 127 + b1: .byte 127, -42 .align 1 - h1: .half 32767 + h1: .half 32767, -12345 + .align 2 w2: .space 4 - b2: .space 1 + b2: .space 2 .align 1 - h2: .space 2 + h2: .space 4 .text main: @@ -27,17 +28,23 @@ main: lb $t5, 0($t1) lbu $t6, b1 + lb $s0, 1($t1) + lbu $s1, b1 + 1 lh $t7, 0($t2) lhu $t8, h1 + lh $s2, 2($t2) + lhu $s3, h1 + 2 la $t9, w2 sw $t3, 0($t9) la $t9, b2 sb $t5, 0($t9) + sb $s0, 1($t9) la $t9, h2 sh $t7, 0($t9) + sh $s2, 2($t9) jr $ra diff --git a/tests/arch/mips/instructions/test_mips_instruction_014.s b/tests/arch/mips/instructions/test_mips_instruction_014.s index d2b77184c..80178d397 100644 --- a/tests/arch/mips/instructions/test_mips_instruction_014.s +++ b/tests/arch/mips/instructions/test_mips_instruction_014.s @@ -4,13 +4,14 @@ # .data - b1: .byte 127 + b1: .byte 127, -42 .align 1 - h1: .half 65535 - b2: .space 1 + h1: .half 32767, -12345 + .align 2 + b2: .space 2 .align 1 - h2: .space 2 + h2: .space 4 .text main: @@ -19,12 +20,16 @@ main: la $t1, h1 lbu $t2, 0($t0) + lbu $s0, 1($t0) lhu $t3, 0($t1) + lhu $s1, 2($t1) la $t4, b2 - sb $t5, 0($t4) + sb $t2, 0($t4) + sb $s0, 1($t4) la $t6, h2 - sh $t7, 0($t6) + sh $t3, 0($t6) + sh $s1, 2($t6) jr $ra diff --git a/tests/arch/riscv/correct/examples/test_riscv_example_013.s b/tests/arch/riscv/correct/examples/test_riscv_example_013.s index 07643a3c4..fa6b18fc9 100644 --- a/tests/arch/riscv/correct/examples/test_riscv_example_013.s +++ b/tests/arch/riscv/correct/examples/test_riscv_example_013.s @@ -9,7 +9,7 @@ .text main: li a7, 1 la t0, utf8 -loop: lb a0, 0(t0) +loop: lbu a0, 0(t0) ecall addi t0, t0, 1 bne a0, zero, loop diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_013.s b/tests/arch/riscv/instructions/test_riscv_instruction_013.s index 3f01a3201..8505e6ef6 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_013.s +++ b/tests/arch/riscv/instructions/test_riscv_instruction_013.s @@ -5,15 +5,16 @@ .data w1: .word 14 - b1: .byte 127 + b1: .byte 127, -42 .align 1 - h1: .half 32767 + h1: .half 32767, -12345 + .align 2 w2: .zero 4 - b2: .zero 1 + b2: .zero 2 .align 1 - h2: .zero 2 + h2: .zero 4 .text main: @@ -26,9 +27,11 @@ main: #lw x9, w1 # Memory[w1] -> x9 lb x10, 0(x6) # Memory[x6] -> x10 + lb x11, 1(x6) # Memory[x6+1] -> x11 #lb x11, b1 # Memory[b1] -> x11 lh x12, 0 (x7) # Memory[x7] -> x12 + lh x13, 2 (x7) # Memory[x7+2] -> x12 #lh x13, h1 # Memory[h1] -> x13 la x14, w2 # w2 address -> x14 @@ -36,8 +39,10 @@ main: la x14, b2 # b2 address -> x14 sb x10, 0(x14) # x10 -> Memory[b2] + sb x11, 1(x14) # x11 -> Memory[b2+1] la x14, h2 # h2 address -> x14 sh x12, 0(x14) # x12 -> Memory[h2] + sh x13, 2(x14) # x13 -> Memory[h2+2] jr ra diff --git a/tests/arch/riscv/instructions/test_riscv_instruction_014.s b/tests/arch/riscv/instructions/test_riscv_instruction_014.s index 3ec4dc88b..09dcb5c8a 100644 --- a/tests/arch/riscv/instructions/test_riscv_instruction_014.s +++ b/tests/arch/riscv/instructions/test_riscv_instruction_014.s @@ -4,13 +4,13 @@ # .data - b1: .byte 127 + b1: .byte 127, -42 .align 1 - h1: .half 65535 - b2: .zero 1 + h1: .half 32767, -12345 + b2: .zero 2 .align 1 - h2: .zero 2 + h2: .zero 4 .text main: @@ -19,13 +19,17 @@ main: la x7, h1 # h1 address -> x7 lbu x10, 0(x6) # Memory[x6] -> x10 + lbu x11, 1(x6) # Memory[x6+1] -> x13 lhu x12, 0 (x7) # Memory[x7] -> x12 + lhu x13, 2 (x7) # Memory[x7+2] -> x13 la x14, b2 # b2 address -> x14 sb x10, 0(x14) # x10 -> Memory[b2] + sb x11, 1(x14) # x11 -> Memory[b2+1] la x14, h2 # h2 address -> x14 sh x12, 0(x14) # x12 -> Memory[h2] + sh x13, 2(x14) # x13 -> Memory[h2+2] jr ra From bd849cf3a5dee5ca4c5d5e07c2ca3676d77c37df Mon Sep 17 00:00:00 2001 From: ALVAROPING1 Date: Thu, 26 Mar 2026 13:17:04 +0100 Subject: [PATCH 76/85] tests: remove redundant simulator reset slowing down tests --- tests/unit/arch/simulator-test-utils.mts | 2 -- 1 file changed, 2 deletions(-) diff --git a/tests/unit/arch/simulator-test-utils.mts b/tests/unit/arch/simulator-test-utils.mts index 651010265..9f087eb06 100644 --- a/tests/unit/arch/simulator-test-utils.mts +++ b/tests/unit/arch/simulator-test-utils.mts @@ -167,8 +167,6 @@ export async function compileAssembly( throw new Error(`Failed to compile assembly: ${compileResult.msg}`); } - creator.reset(); - return compileResult; } From c6e16e062733043c74759272200f07cbe5bb2dec Mon Sep 17 00:00:00 2001 From: ALVAROPING1 Date: Thu, 26 Mar 2026 13:32:08 +0100 Subject: [PATCH 77/85] docs: added how to run/update snapshot tests --- docs/dev.md | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/docs/dev.md b/docs/dev.md index 15369b840..ede2329b7 100644 --- a/docs/dev.md +++ b/docs/dev.md @@ -80,12 +80,23 @@ bun format ``` ### Run Tests + Unit tests (with [Deno](https://deno.com/)) + ```sh deno test -A --unstable-node-globals --parallel ``` +Integration tests use [Deno's snapshot testing](https://docs.deno.com/examples/snapshot_test_tutorial/). +They store the last known good result, and compare new results against the +stored snapshots to verify them (showing the differences if they don't match). +For this reason, the snapshots should always be committed to the repo. They are +run along with the other tests using the command above. The snapshots can be +created/updated automatically with: +```sh +deno test -A --unstable-node-globals --parallel -- --update +``` ## Backend RPC Server This project includes a JSON RPC server that exposes the CREATOR emulator's core functionalities. From 578bb163dcab4d6d66b16b56c376a0eb1cf2297a Mon Sep 17 00:00:00 2001 From: ALVAROPING1 Date: Thu, 26 Mar 2026 14:08:37 +0100 Subject: [PATCH 78/85] fix(Calculator): fix not being allowed to type hex/binary numbers --- src/web/components/simulator/Calculator.vue | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/src/web/components/simulator/Calculator.vue b/src/web/components/simulator/Calculator.vue index 587e9f769..1c6896dee 100644 --- a/src/web/components/simulator/Calculator.vue +++ b/src/web/components/simulator/Calculator.vue @@ -107,7 +107,7 @@ export default defineComponent({ convertFromDecimal() { try { this.error = ""; - const value = parseFloat(this.decimalInput); + const value = parseFloat(this.decimalInput || 0); if (isNaN(value)) { this.error = "Invalid decimal number"; @@ -152,23 +152,22 @@ export default defineComponent({ this.error = ""; let hexStr = this.hexInput.replace(/^0x/i, "").replace(/\s/g, ""); - if (!/^[0-9a-fA-F]+$/.test(hexStr)) { + if (!/^[0-9a-fA-F]*$/.test(hexStr)) { this.error = "Invalid hexadecimal value"; return; } + const size = Math.ceil(this.formatBits / 4); + hexStr = hexStr.padStart(size, "0").slice(-size); if (this.format === "ieee32") { - hexStr = hexStr.padStart(8, "0").substring(0, 8); this.decimalValue = hex2float("0x" + hexStr); this.binaryValue = float2bin(this.decimalValue); - this.hexValue = "0x" + hexStr.toUpperCase(); } else { // IEEE 64 - hexStr = hexStr.padStart(16, "0").substring(0, 16); this.decimalValue = hex2double("0x" + hexStr); this.binaryValue = double2bin(this.decimalValue); - this.hexValue = "0x" + hexStr.toUpperCase(); } + this.hexValue = "0x" + hexStr.toUpperCase(); this.updateBreakdown(); this.updateInputs(); @@ -182,13 +181,13 @@ export default defineComponent({ this.error = ""; let binStr = this.binaryInput.replace(/\s/g, ""); - if (!/^[01]+$/.test(binStr)) { + if (!/^[01]*$/.test(binStr)) { this.error = "Invalid binary value"; return; } const expectedBits = this.formatBits; - binStr = binStr.padStart(expectedBits, "0").substring(0, expectedBits); + binStr = binStr.padStart(expectedBits, "0").slice(-expectedBits); this.binaryValue = binStr; From b803f9ba6ce8c355d4d7c118b1d4efa574011ad4 Mon Sep 17 00:00:00 2001 From: ALVAROPING1 Date: Thu, 26 Mar 2026 14:09:33 +0100 Subject: [PATCH 79/85] chore(creatorAssemblerBase): auto-format file --- .../creatorAssembler/creatorAssemblerBase.mjs | 65 +++++++++---------- 1 file changed, 32 insertions(+), 33 deletions(-) diff --git a/src/core/assembler/creatorAssembler/creatorAssemblerBase.mjs b/src/core/assembler/creatorAssembler/creatorAssemblerBase.mjs index bac6e44e0..1fa0fbb46 100644 --- a/src/core/assembler/creatorAssembler/creatorAssemblerBase.mjs +++ b/src/core/assembler/creatorAssembler/creatorAssemblerBase.mjs @@ -142,7 +142,7 @@ function loadLibraryIfPresent(instructions) { // Convert hex string to binary string let binaryString = ""; for (let i = 0; i < loadedLibrary.binary.length; i += 2) { - const hexByte = loadedLibrary.binary.slice(i, i+2); + const hexByte = loadedLibrary.binary.slice(i, i + 2); const byte = parseInt(hexByte, 16); binaryString += byte.toString(2).padStart(8, "0"); } @@ -161,7 +161,10 @@ function loadLibraryIfPresent(instructions) { // Process each instruction let currentAddr = 0; for (let i = 0; i < binaryString.length; i += instructionSizeBits) { - const instructionBinary = binaryString.slice(i, i + instructionSizeBits); + const instructionBinary = binaryString.slice( + i, + i + instructionSizeBits, + ); const symbolName = symbolsByAddr.get(currentAddr); const hasSymbol = symbolName !== undefined; @@ -195,8 +198,7 @@ function loadLibraryIfPresent(instructions) { function loadDataIntoMemory(data_mem, wasmModules) { const { DataCategoryJS } = wasmModules; const wordSizeBytes = - newArchitecture.config.word_size / - newArchitecture.config.byte_size; + newArchitecture.config.word_size / newArchitecture.config.byte_size; for (let i = 0; i < data_mem.length; i++) { const data = data_mem[i]; const addr = data.address(); @@ -389,12 +391,7 @@ function loadDataIntoMemory(data_mem, wasmModules) { const stringLength = Number(size); const stringType = "string"; - main_memory.addHint( - addr, - labels, - stringType, - stringLength * 8, - ); + main_memory.addHint(addr, labels, stringType, stringLength * 8); break; } @@ -406,12 +403,7 @@ function loadDataIntoMemory(data_mem, wasmModules) { const spaceType = category === DataCategoryJS.Padding ? "padding" : "space"; - main_memory.addHint( - addr, - labels, - spaceType, - Number(size) * 8, - ); + main_memory.addHint(addr, labels, spaceType, Number(size) * 8); break; } @@ -429,23 +421,20 @@ function writeBinaryToMemory(binary, baseAddr) { // Split into words, reverse order, and concatenate const words = []; for (let j = 0; j < binary.length; j += WORDSIZE) { - words.push(binary.slice(j, j+WORDSIZE)); + words.push(binary.slice(j, j + WORDSIZE)); } const reversedBinary = words.reverse().join(""); for (let j = 0; j < reversedBinary.length; j += WORDSIZE) { - const wordBinary = reversedBinary.slice(j, j+WORDSIZE); + const wordBinary = reversedBinary.slice(j, j + WORDSIZE); const wordBytes = []; for (let k = 0; k < wordBinary.length; k += BYTESIZE) { - const byte = parseInt(wordBinary.slice(k, k+BYTESIZE), 2); + const byte = parseInt(wordBinary.slice(k, k + BYTESIZE), 2); wordBytes.push(byte); } - main_memory.writeWord( - BigInt(baseAddr + j / BYTESIZE), - wordBytes, - ); + main_memory.writeWord(BigInt(baseAddr + j / BYTESIZE), wordBytes); } } @@ -459,7 +448,7 @@ function writeLibraryToMemory() { let binaryString = ""; for (let i = 0; i < loadedLibrary.binary.length; i += 2) { - const hexByte = loadedLibrary.binary.slice(i, i+2); + const hexByte = loadedLibrary.binary.slice(i, i + 2); const byte = parseInt(hexByte, 16); binaryString += byte.toString(2).padStart(8, "0"); } @@ -469,8 +458,11 @@ function writeLibraryToMemory() { const instructionSizeBytes = instructionSizeBits / 8; for (let i = 0; i < binaryString.length; i += instructionSizeBits) { - const instructionBinary = binaryString.slice(i, i+instructionSizeBits); - writeBinaryToMemory(instructionBinary, currentAddr) + const instructionBinary = binaryString.slice( + i, + i + instructionSizeBits, + ); + writeBinaryToMemory(instructionBinary, currentAddr); currentAddr += instructionSizeBytes; } } @@ -484,7 +476,7 @@ function writeInstructionsToMemory(instructions, library_instructions) { for (let i = library_instructions; i < instructions.length; i++) { const instruction = instructions[i]; const addr = parseInt(instruction.Address, 16); - writeBinaryToMemory(instruction.binary, addr) + writeBinaryToMemory(instruction.binary, addr); } } @@ -518,7 +510,7 @@ export function assembleCreatorLibrary(code, wasmModules, ansi_color) { 0, // library_offset (not used for library compilation) "{}", // no library labels true, // library flag - ansi_color? Color.Ansi : Color.Html, + ansi_color ? Color.Ansi : Color.Html, ); // Library compilation: only binary instructions @@ -545,12 +537,14 @@ export function assembleCreatorLibrary(code, wasmModules, ansi_color) { const data_mem = compiled.data; loadDataIntoMemory(data_mem, wasmModules); } catch (error) { - return handleError(error, ansi_color) + return handleError(error, ansi_color); } // Mark global labels on library instructions for (const instruction of libraryInstructions) { - instruction.Label = instruction.Label.filter(label => label_table[label].global); + instruction.Label = instruction.Label.filter( + label => label_table[label].global, + ); if (instruction.Label.length > 0) { instruction.globl = true; } @@ -604,7 +598,7 @@ export function assembleCreatorProgram(code, wasmModules, ansi_color) { library_offset, labels_json, false, // not a library - ansi_color? Color.Ansi : Color.Html, + ansi_color ? Color.Ansi : Color.Html, ); // Normal compilation: populate instructions for execution/display @@ -631,7 +625,7 @@ export function assembleCreatorProgram(code, wasmModules, ansi_color) { const data_mem = compiled.data; loadDataIntoMemory(data_mem, wasmModules); } catch (error) { - return handleError(error, ansi_color) + return handleError(error, ansi_color); } // Write library binary to memory if present @@ -669,7 +663,12 @@ export function assembleCreatorProgram(code, wasmModules, ansi_color) { * @param {boolean} ansi_color - Whether to use ANSI or HTML colors (default: HTML) * @returns {Object} Compilation result */ -export function assembleCreatorBase(code, library, wasmModules, ansi_color = false) { +export function assembleCreatorBase( + code, + library, + wasmModules, + ansi_color = false, +) { if (library) { return assembleCreatorLibrary(code, wasmModules, ansi_color); } else { From 96f8f4256dd39c4364cbc91624f75610eedd8e8e Mon Sep 17 00:00:00 2001 From: Juan Carlos Cano Date: Fri, 27 Mar 2026 12:15:36 +0100 Subject: [PATCH 80/85] Change result_log display from v-html to interpolation --- src/web/components/ArchitectureView.vue | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/web/components/ArchitectureView.vue b/src/web/components/ArchitectureView.vue index 1df3d7a30..b051cb082 100644 --- a/src/web/components/ArchitectureView.vue +++ b/src/web/components/ArchitectureView.vue @@ -292,7 +292,7 @@ export default defineComponent({ :max="architecture.config.name === 'SRV32' ? 89 : 122" >
-