From b87af6e5f290fa1332ad378239826137cf3dd369 Mon Sep 17 00:00:00 2001 From: Diego Camarmas Date: Tue, 17 Feb 2026 15:39:37 +0100 Subject: [PATCH] blez pseudoinstruction definition fixed --- architecture/RISCV/RV32IMFD.yml | 4 ++-- architecture/RISCV/RV64IMFD.yml | 2 +- src/core/core.mjs | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/architecture/RISCV/RV32IMFD.yml b/architecture/RISCV/RV32IMFD.yml index 5d24d6f98..8cc988d99 100644 --- a/architecture/RISCV/RV32IMFD.yml +++ b/architecture/RISCV/RV32IMFD.yml @@ -7,6 +7,7 @@ version: 2.0.0 config: name: RV32 word_size: 32 + byte_size: 8 description: RISC-V is an instruction set architecture (ISA) based on the RISC type and its hardware is free. This architecture was created in 2010 at the University of California, Berkeley. endianness: big_endian memory_alignment: true @@ -16,7 +17,6 @@ config: comment_prefix: "#" start_address: 0x0 pc_offset: -4 - byte_size: 8 plugin: riscv assemblers: - name: CreatorAssembler @@ -3835,7 +3835,7 @@ pseudoinstructions: - field: off type: offset_bytes definition: | - ble x0, rs1, off; + bge x0, rs1, off; - name: bltz fields: diff --git a/architecture/RISCV/RV64IMFD.yml b/architecture/RISCV/RV64IMFD.yml index 5c0888686..e358d6212 100644 --- a/architecture/RISCV/RV64IMFD.yml +++ b/architecture/RISCV/RV64IMFD.yml @@ -3866,7 +3866,7 @@ pseudoinstructions: - field: off type: offset_bytes definition: | - ble x0, rs1, off; + bge x0, rs1, off; - name: bltz fields: diff --git a/src/core/core.mjs b/src/core/core.mjs index 80e4e175f..ba293341e 100644 --- a/src/core/core.mjs +++ b/src/core/core.mjs @@ -88,7 +88,7 @@ export let ENDIANNESSARR = []; /** @type {import("./core.d.ts").RegisterBank[]} */ export let REGISTERS; export let REGISTERS_BACKUP = []; -export const register_size_bits = 64; //TODO: load from architecture +export const register_size_bits = 32; //TODO: load from architecture /** @type {Memory} */ export let main_memory; /** @type {StackTracker} */