Skip to content
This repository was archived by the owner on Feb 12, 2026. It is now read-only.

Commit 5b6dc6a

Browse files
authored
Delay adjustments (#72)
* Adjusted delay for start signal for MPs. * Adjusted magic delay for PC_start in test bench. * Adjusted delay on FileWriters in test bench.
1 parent 650336f commit 5b6dc6a

1 file changed

Lines changed: 5 additions & 5 deletions

File tree

WriteVHDLSyntax.py

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -132,7 +132,7 @@ def writeTBMemoryStimulusProcess(initial_proc):
132132
string_mem += " -- Process to start first module in chain & generate its BX counter input.\n"
133133
string_mem += " -- Also releases reset flag.\n"
134134
string_mem += " constant CLK_RESET : natural := 5; -- Any low number OK.\n"
135-
string_mem += " variable CLK_COUNT : natural := 4; -- Magic adjustment (ryd)\n" if "IR" not in initial_proc else " variable CLK_COUNT : natural := MAX_ENTRIES - CLK_RESET;\n"
135+
string_mem += " variable CLK_COUNT : natural := 2; -- Magic adjustment (ryd)\n" if "IR" not in initial_proc else " variable CLK_COUNT : natural := MAX_ENTRIES - CLK_RESET;\n"
136136
string_mem += " variable EVENT_COUNT : integer := -1;\n"
137137
string_mem += " variable v_line : line; -- Line for debug\n"
138138
string_mem += " begin\n\n"
@@ -1315,13 +1315,13 @@ def writeTBMemoryWriteInstance(mtypeB, memList, proc, proc_up, bxbitwidth, is_bi
13151315
else:
13161316
string_mem += " PAGE_LENGTH".ljust(str_len)+"=> 1024,\n"
13171317
if "VMSME" in mem:
1318-
string_mem += " CLK_CNT_INIT".ljust(str_len)+"=> -17,\n" #-17 is emperically determined to allign the FileWriter BX with the data stream
1318+
string_mem += " CLK_CNT_INIT".ljust(str_len)+"=> -21,\n" #-21 is emperically determined to allign the FileWriter BX with the data stream
13191319
if "MPROJ" in mem :
13201320
string_mem += " NUM_TPAGES".ljust(str_len)+"=> 4,\n"
13211321
string_mem += " PAGE_LENGTH".ljust(str_len)+"=> 64,\n"
1322-
string_mem += " CLK_CNT_INIT".ljust(str_len)+"=> -17,\n" #-17 is emperically determined to allign the FileWriter BX with the data stream
1322+
string_mem += " CLK_CNT_INIT".ljust(str_len)+"=> -21,\n" #-21 is emperically determined to allign the FileWriter BX with the data stream
13231323
if "FM" in mem :
1324-
string_mem += " CLK_CNT_INIT".ljust(str_len)+"=> -17,\n" #-17 is emperically determined to allign the FileWriter BX with the data stream
1324+
string_mem += " CLK_CNT_INIT".ljust(str_len)+"=> -21,\n" #-21 is emperically determined to allign the FileWriter BX with the data stream
13251325
string_mem += " NUM_PAGES".ljust(str_len)+"=> " + str(2**bxbitwidth) + "\n"
13261326
string_mem += " )\n"
13271327
string_mem += " port map (\n"
@@ -1523,7 +1523,7 @@ def writeStartSwitchAndInternalBX(module,mem,extraports=False, delay = 0, first_
15231523

15241524
int_ctrl_func += " LATCH_PC_VMSMER: entity work.tf_pipeline_slr_xing\n"
15251525
startsignal_parameter_list = " NUM_SLR => 3,\n"
1526-
startsignal_parameter_list += " DELAY => (2, 119, 2),\n"
1526+
startsignal_parameter_list += " DELAY => (2, 124, 2),\n"
15271527
startsignal_parameter_list += " USE_SRL => (false, true, false),\n"
15281528
int_ctrl_func += " generic map (\n"+startsignal_parameter_list.rstrip(",\n")+"\n )\n"
15291529

0 commit comments

Comments
 (0)