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Questions about some errors when running simulation or tests #42

@ingmarfjolla

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@ingmarfjolla

Hello! I'm not sure if I missed a dependency somewhere (or needed to do anything else to get things working), but I'm trying to run make test and make simulation in the respective pre-built /builds/RV64... directories and getting a couple of different errors.

I'm currently on M1 Mac OS Ventura.

  1. I tried running make simulation in the iverilog directories, but it seems like it was still expecting verilator / bsc to be installed, so I installed Verilator but now it seems to be failing with :
%Error-NEEDTIMINGOPT: Verilog_RTL/mkPLIC_16_2_7.v:25483:4: Use --timing or --no-timing to specify how delays should be handled
                                                         : ... note: In instance 'mkTop_HW_Side.soc_top.core.plic'
25483 |    #0;
      |    ^
                      Verilog_RTL/mkCore.v:2314:1: ... note: In file included from 'mkCore.v'
                      Verilog_RTL/mkSoC_Top.v:1127:1: ... note: In file included from 'mkSoC_Top.v'
                      Verilog_RTL/mkTop_HW_Side_edited.v:227:1: ... note: In file included from 'mkTop_HW_Side_edited.v'
%Error: Exiting due to too many errors encountered; --error-limit=50

I'm not sure if I missed anything there.

  1. When I run make test , I get an error saying :
elf_to_hex.c:15:10: fatal error: 'gelf.h' file not found
#include <gelf.h>
         ^~~~~~~~
1 error generated.
make[1]: *** [elf_to_hex] Error 1

I tried fixing the path to my compiler, but it didn't seem to have any effect. I'm not sure the best way to debug this and tried with clang/gcc/g++.

Sorry for the amount of questions, and thank you for any guidance!

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