diff --git a/scripts/gen_gpu.sh b/scripts/gen_gpu.sh index c4038ba..16eb89b 100644 --- a/scripts/gen_gpu.sh +++ b/scripts/gen_gpu.sh @@ -7,10 +7,18 @@ LLVM_DIR=`dirname $LLVM_DIR` LLVM_DIR=`dirname $LLVM_DIR` echo "Using LLVM rooted at : $LLVM_DIR" +if [ "$BUILD_MODE" = "debug" ]; then + MLIR_BUILD="debug_build" + CONFIG="Debug" +else + MLIR_BUILD="build" + CONFIG="Release" +fi + +# Default cmake command CMAKE="cmake" -MLIR_BUILD="build" -CONFIG="Release" +# Process options while getopts "d:m:c:" opt do case "$opt" in @@ -24,7 +32,7 @@ echo "Using cmake command : $CMAKE" echo "Using MLIR_BUILD : $MLIR_BUILD" echo "Using configuration : $CONFIG" -# run this from the build directory +# Run the cmake command from the build directory $CMAKE -G Ninja .. -DCMAKE_EXPORT_COMPILE_COMMANDS=1 \ -DMLIR_DIR=$LLVM_DIR/$MLIR_BUILD/lib/cmake/mlir \ -DLLVM_BUILD_DIRECTORY=$LLVM_DIR/$MLIR_BUILD/ \ @@ -33,4 +41,4 @@ $CMAKE -G Ninja .. -DCMAKE_EXPORT_COMPILE_COMMANDS=1 \ # -DAMD_GPU_SUPPORT=ON # -DCMAKE_C_COMPILER=clang -DCMAKE_CXX_COMPILER=clang++ # -DLLVM_ENABLE_LLD=ON -# -DCMAKE_CXX_FLAGS="-std=c++17" +# -DCMAKE_CXX_FLAGS="-std=c++17" \ No newline at end of file diff --git a/scripts/setupPythonEnv.sh b/scripts/setupPythonEnv.sh index 8dcc0ed..984d0f1 100755 --- a/scripts/setupPythonEnv.sh +++ b/scripts/setupPythonEnv.sh @@ -4,7 +4,11 @@ SCRIPTPATH=`dirname $SCRIPT` TREEBEARD_DIR=`dirname $SCRIPTPATH` echo "Using Treebeard rooted at : $TREEBEARD_DIR" -BUILD_DIR="build" +if [ "$BUILD_MODE" = "debug" ]; then + BUILD_DIR="debug_build" +else + BUILD_DIR="build" +fi while getopts "m:" opt do diff --git a/scripts/setupSilvanForge.sh b/scripts/setupSilvanForge.sh index 07d0bcb..be3144a 100644 --- a/scripts/setupSilvanForge.sh +++ b/scripts/setupSilvanForge.sh @@ -2,29 +2,48 @@ git clone https://github.com/asprasad/llvm-project.git cd llvm-project/ git checkout release/16.x -mkdir build -cd build -cmake -G Ninja ../llvm -DLLVM_ENABLE_PROJECTS="llvm;clang;lld;mlir;openmp" -DLLVM_BUILD_EXAMPLES=ON -DLLVM_TARGETS_TO_BUILD="X86;NVPTX;AMDGPU" -DCMAKE_BUILD_TYPE=Release -DLLVM_ENABLE_ASSERTIONS=ON -DCMAKE_C_COMPILER=clang -DCMAKE_CXX_COMPILER=clang++ -DLLVM_ENABLE_LLD=ON -DMLIR_ENABLE_CUDA_RUNNER=ON -DMLIR_INCLUDE_INTEGRATION_TESTS=ON + +if [ "$BUILD_MODE" = "debug" ]; then + BUILD_DIR="debug_build" + CONFIG="Debug" +else + BUILD_DIR="build" + CONFIG="Release" +fi + +mkdir -p $BUILD_DIR +cd $BUILD_DIR +cmake -G Ninja ../llvm -DLLVM_ENABLE_PROJECTS="llvm;clang;lld;mlir;openmp" -DLLVM_BUILD_EXAMPLES=ON -DLLVM_TARGETS_TO_BUILD="X86;NVPTX;AMDGPU" -DCMAKE_BUILD_TYPE=$CONFIG -DLLVM_ENABLE_ASSERTIONS=ON -DCMAKE_C_COMPILER=clang -DCMAKE_CXX_COMPILER=clang++ -DLLVM_ENABLE_LLD=ON -DMLIR_ENABLE_CUDA_RUNNER=ON -DMLIR_INCLUDE_INTEGRATION_TESTS=ON cmake --build . # Clone and build Treebeard cd ../mlir/examples -git clone https://github.com/asprasad/treebeard.git + +if [ ! -d "treebeard" ]; then + git clone https://github.com/asprasad/treebeard.git +else + echo "'treebeard' directory already exists. Skipping clone." +fi + cd treebeard # Checkout branch with changes made for silvanforge git checkout silvanforge -mkdir build -cd build +mkdir -p $BUILD_DIR +cd $BUILD_DIR bash ../scripts/gen_gpu.sh cmake --build . # Clone and build Tahoe cd ../../ -git clone https://github.com/sampathrg/Tahoe.git + +if [ ! -d "Tahoe" ]; then + git clone https://github.com/sampathrg/Tahoe.git +else + echo "'Tahoe' directory already exists. Skipping clone." +fi + cd Tahoe git checkout tahoe-expts make - - diff --git a/src/gpu/GPUSimtPass.cpp b/src/gpu/GPUSimtPass.cpp index 2b17e4b..5dec0e7 100644 --- a/src/gpu/GPUSimtPass.cpp +++ b/src/gpu/GPUSimtPass.cpp @@ -160,7 +160,28 @@ void ConvertTraverseToSimtTraverse(mlir::MLIRContext &context, mlir::ModuleOp module) { // llvm::DebugFlag = true; // Lower from high-level IR to mid-level IR + + // Check if the environment variable PRINT_AFTER_ALL is set + const char *printAfterAllEnv = std::getenv("PRINT_AFTER_ALL"); + bool printAfterAll = printAfterAllEnv && std::string(printAfterAllEnv) == "true"; + + if(printAfterAll) + context.disableMultithreading(); + + mlir::PassManager pm(&context); + + // If PRINT_AFTER_ALL is set to "true", enable IR printing + if (printAfterAll) { + /* Enable Print After All For Debugging */ + pm.enableIRPrinting( + [=](mlir::Pass *a, Operation *b) { return false; }, // Don't print before passes + [=](mlir::Pass *a, Operation *b) { return true; }, // Print after every pass + true, // Print at module scope + false // Print after every pass, regardless of changes + ); + } + pm.addPass(std::make_unique()); if (mlir::failed(pm.run(module))) { diff --git a/src/gpu/GPUSupportUtils.cpp b/src/gpu/GPUSupportUtils.cpp index c1fd6b0..19dd0a7 100644 --- a/src/gpu/GPUSupportUtils.cpp +++ b/src/gpu/GPUSupportUtils.cpp @@ -416,7 +416,28 @@ bool isThreadLoop(scf::ParallelOp parallelOp) { } void GreedilyMapParallelLoopsToGPU(mlir::ModuleOp module) { - mlir::PassManager pm(module.getContext()); + + // Check if the environment variable PRINT_AFTER_ALL is set + const char *printAfterAllEnv = std::getenv("PRINT_AFTER_ALL"); + bool printAfterAll = printAfterAllEnv && std::string(printAfterAllEnv) == "true"; + + if(printAfterAll) + module.getContext()->disableMultithreading(); + + + mlir::PassManager pm(module.getContext()); + + // If PRINT_AFTER_ALL is set to "true", enable IR printing + if (printAfterAll) { + /* Enable Print After All For Debugging */ + pm.enableIRPrinting( + [=](mlir::Pass *a, Operation *b) { return false; }, // Don't print before passes + [=](mlir::Pass *a, Operation *b) { return true; }, // Print after every pass + true, // Print at module scope + false // Print after every pass, regardless of changes + ); + } + mlir::OpPassManager &optPM = pm.nest(); optPM.addPass(createGpuMapParallelLoopsPass()); @@ -427,7 +448,26 @@ void GreedilyMapParallelLoopsToGPU(mlir::ModuleOp module) { void ConvertParallelLoopsToGPU(mlir::MLIRContext &context, mlir::ModuleOp module) { + // Check if the environment variable PRINT_AFTER_ALL is set + const char *printAfterAllEnv = std::getenv("PRINT_AFTER_ALL"); + bool printAfterAll = printAfterAllEnv && std::string(printAfterAllEnv) == "true"; + + if(printAfterAll) + context.disableMultithreading(); + + mlir::PassManager pm(&context); + + // If PRINT_AFTER_ALL is set to "true", enable IR printing + if (printAfterAll) { + /* Enable Print After All For Debugging */ + pm.enableIRPrinting( + [=](mlir::Pass *a, Operation *b) { return false; }, // Don't print before passes + [=](mlir::Pass *a, Operation *b) { return true; }, // Print after every pass + true, // Print at module scope + false // Print after every pass, regardless of changes + ); + } mlir::OpPassManager &optPM = pm.nest(); // optPM.addPass(std::make_unique()); optPM.addPass(createParallelLoopToGpuPass()); @@ -441,7 +481,26 @@ void ConvertParallelLoopsToGPU(mlir::MLIRContext &context, } void OutlineGPUKernels(mlir::MLIRContext &context, mlir::ModuleOp module) { + // Check if the environment variable PRINT_AFTER_ALL is set + const char *printAfterAllEnv = std::getenv("PRINT_AFTER_ALL"); + bool printAfterAll = printAfterAllEnv && std::string(printAfterAllEnv) == "true"; + + if(printAfterAll) + context.disableMultithreading(); + + mlir::PassManager pm(&context); + + // If PRINT_AFTER_ALL is set to "true", enable IR printing + if (printAfterAll) { + /* Enable Print After All For Debugging */ + pm.enableIRPrinting( + [=](mlir::Pass *a, Operation *b) { return false; }, // Don't print before passes + [=](mlir::Pass *a, Operation *b) { return true; }, // Print after every pass + true, // Print at module scope + false // Print after every pass, regardless of changes + ); + } pm.addPass(createGpuKernelOutliningPass()); if (mlir::failed(pm.run(module))) { @@ -450,7 +509,26 @@ void OutlineGPUKernels(mlir::MLIRContext &context, mlir::ModuleOp module) { } void RunCanonicalizerPass(mlir::MLIRContext &context, mlir::ModuleOp module) { + // Check if the environment variable PRINT_AFTER_ALL is set + const char *printAfterAllEnv = std::getenv("PRINT_AFTER_ALL"); + bool printAfterAll = printAfterAllEnv && std::string(printAfterAllEnv) == "true"; + + if(printAfterAll) + context.disableMultithreading(); + + mlir::PassManager pm(&context); + + // If PRINT_AFTER_ALL is set to "true", enable IR printing + if (printAfterAll) { + /* Enable Print After All For Debugging */ + pm.enableIRPrinting( + [=](mlir::Pass *a, Operation *b) { return false; }, // Don't print before passes + [=](mlir::Pass *a, Operation *b) { return true; }, // Print after every pass + true, // Print at module scope + false // Print after every pass, regardless of changes + ); + } mlir::GreedyRewriteConfig config; std::vector disabledPatterns = { "(anonymous namespace)::MergeNestedParallelLoops"}; diff --git a/src/gpu/LowerGPUToLLVM.cpp b/src/gpu/LowerGPUToLLVM.cpp index c4366b9..51dd05a 100644 --- a/src/gpu/LowerGPUToLLVM.cpp +++ b/src/gpu/LowerGPUToLLVM.cpp @@ -561,7 +561,27 @@ void LowerGPUToLLVM( InitializeGPUTarget(compileInfo); // llvm::DebugFlag = true; // Lower from high-level IR to mid-level IR + + // Check if the environment variable PRINT_AFTER_ALL is set + const char *printAfterAllEnv = std::getenv("PRINT_AFTER_ALL"); + bool printAfterAll = printAfterAllEnv && std::string(printAfterAllEnv) == "true"; + + if(printAfterAll) + context.disableMultithreading(); + + mlir::PassManager pm(&context); + + // If PRINT_AFTER_ALL is set to "true", enable IR printing + if (printAfterAll) { + /* Enable Print After All For Debugging */ + pm.enableIRPrinting( + [=](mlir::Pass *a, Operation *b) { return false; }, // Don't print before passes + [=](mlir::Pass *a, Operation *b) { return true; }, // Print after every pass + true, // Print at module scope + false // Print after every pass, regardless of changes + ); + } // pm.addPass(createConvertSCFToCFPass()); pm.addPass(createGpuKernelOutliningPass()); // pm.addPass(std::make_unique()); diff --git a/src/main.cpp b/src/main.cpp index 9e5e299..e9c5f60 100644 --- a/src/main.cpp +++ b/src/main.cpp @@ -9,6 +9,8 @@ #include "json/xgboostparser.h" #include #include +#include "llvm/Support/CommandLine.h" +#include "llvm/Support/InitLLVM.h" namespace TreeBeard { namespace test { @@ -17,6 +19,19 @@ void generateRandomXGBoostModels(const std::string &dirName); } // namespace test } // namespace TreeBeard +// Commmand line options + +using namespace llvm; +static cl::opt printAfterAll("print-treebeard-ir-after-all", + cl::desc("Print IR after each pass"), cl::init(false)); + +static cl::opt individual("individual", cl::desc("Enable individual mode"), cl::init(false)); + +static cl::opt testName("testname", cl::desc("Test name"), + cl::value_desc("name"), cl::init(""), cl::Hidden); + + + bool EqualsString(char *arg, const std::string &str) { return (std::string(arg) == str); } @@ -387,6 +402,21 @@ bool GenerateRandomXGBoostBenchmarksIfNeeded(int argc, char *argv[]) { } int main(int argc, char *argv[]) { + cl::ParseCommandLineOptions(argc, argv, "TreeBread Runner"); + + // Check if 'printAfterAll' is used without 'individual' + if (printAfterAll && !individual) { + llvm::errs() << "Error: 'print-treebeard-ir-after-all' can only be used with " + "'individual' flag.\n"; + return 1; + } + + // Check if 'testName' is used without 'individual' + if (!testName.empty() && !individual) { + llvm::errs() << "Error: 'testname' can only be used with 'individual' flag.\n"; + return 1; + } + SetInsertDebugHelpers(argc, argv); SetInsertPrintVectors(argc, argv); SetPerfNotificationListener(argc, argv); @@ -406,7 +436,21 @@ int main(int argc, char *argv[]) { return 0; else if (GenerateRandomXGBoostBenchmarksIfNeeded(argc, argv)) return 0; - else { + else if (individual) { + + // If printAfterAll is true, set the environment variable + if (printAfterAll) { + setenv("PRINT_AFTER_ALL", "true", 1); // Set the environment variable + } + + std::string individualTestName = testName; + TreeBeard::test::RunIndividualTests(individualTestName); + + // Unset the environment variable after the tests are run + if (printAfterAll) { + unsetenv("PRINT_AFTER_ALL"); // Unset the environment variable + } + } else { std::cout << "TreeBeard: A compiler for gradient boosting tree inference.\n"; TreeBeard::test::RunTests(); diff --git a/src/mlir/ConvertNodeTypeToIndexType.cpp b/src/mlir/ConvertNodeTypeToIndexType.cpp index 06b714e..4cc3521 100644 --- a/src/mlir/ConvertNodeTypeToIndexType.cpp +++ b/src/mlir/ConvertNodeTypeToIndexType.cpp @@ -173,7 +173,27 @@ namespace decisionforest void ConvertNodeTypeToIndexType(mlir::MLIRContext& context, mlir::ModuleOp module) { // llvm::DebugFlag = true; // Lower from high-level IR to mid-level IR + + // Check if the environment variable PRINT_AFTER_ALL is set + const char *printAfterAllEnv = std::getenv("PRINT_AFTER_ALL"); + bool printAfterAll = printAfterAllEnv && std::string(printAfterAllEnv) == "true"; + + if(printAfterAll) + context.disableMultithreading(); + + mlir::PassManager pm(&context); + + // If PRINT_AFTER_ALL is set to "true", enable IR printing + if (printAfterAll) { + /* Enable Print After All For Debugging */ + pm.enableIRPrinting( + [=](mlir::Pass *a, Operation *b) { return false; }, // Don't print before passes + [=](mlir::Pass *a, Operation *b) { return true; }, // Print after every pass + true, // Print at module scope + false // Print after every pass, regardless of changes + ); + } pm.addPass(std::make_unique()); if (mlir::failed(pm.run(module))) { diff --git a/src/mlir/GPUAutoSchedule.cpp b/src/mlir/GPUAutoSchedule.cpp index a048006..12be9ab 100644 --- a/src/mlir/GPUAutoSchedule.cpp +++ b/src/mlir/GPUAutoSchedule.cpp @@ -983,7 +983,26 @@ int32_t NUM_RUNS = 200; void DoGPUAutoSchedule(mlir::MLIRContext &context, mlir::ModuleOp module, const TreeBeard::GPUAutoScheduleOptions &options) { + // Check if the environment variable PRINT_AFTER_ALL is set + const char *printAfterAllEnv = std::getenv("PRINT_AFTER_ALL"); + bool printAfterAll = printAfterAllEnv && std::string(printAfterAllEnv) == "true"; + + if(printAfterAll) + context.disableMultithreading(); + + mlir::PassManager pm(&context); + + // If PRINT_AFTER_ALL is set to "true", enable IR printing + if (printAfterAll) { + /* Enable Print After All For Debugging */ + pm.enableIRPrinting( + [=](mlir::Pass *a, Operation *b) { return false; }, // Don't print before passes + [=](mlir::Pass *a, Operation *b) { return true; }, // Print after every pass + true, // Print at module scope + false // Print after every pass, regardless of changes + ); + } mlir::OpPassManager &optPM = pm.nest(); optPM.addPass(std::make_unique()); // TODO pipelineSize needs to be added to CompilerOptions diff --git a/src/mlir/LowerEnsembleToMemrefs.cpp b/src/mlir/LowerEnsembleToMemrefs.cpp index d346b71..de90da5 100644 --- a/src/mlir/LowerEnsembleToMemrefs.cpp +++ b/src/mlir/LowerEnsembleToMemrefs.cpp @@ -960,7 +960,26 @@ void LowerEnsembleToMemrefs(mlir::MLIRContext &context, mlir::ModuleOp module, // Lower from mid-level IR to low-level IR representation->InitRepresentation(); + // Check if the environment variable PRINT_AFTER_ALL is set + const char *printAfterAllEnv = std::getenv("PRINT_AFTER_ALL"); + bool printAfterAll = printAfterAllEnv && std::string(printAfterAllEnv) == "true"; + + if(printAfterAll) + context.disableMultithreading(); + + mlir::PassManager pm(&context); + + // If PRINT_AFTER_ALL is set to "true", enable IR printing + if (printAfterAll) { + /* Enable Print After All For Debugging */ + pm.enableIRPrinting( + [=](mlir::Pass *a, Operation *b) { return false; }, // Don't print before passes + [=](mlir::Pass *a, Operation *b) { return true; }, // Print after every pass + true, // Print at module scope + false // Print after every pass, regardless of changes + ); + } pm.addPass(std::make_unique(serializer, representation)); @@ -978,7 +997,27 @@ void LowerGPUEnsembleToMemrefs( // llvm::DebugFlag = true; representation->InitRepresentation(); // Lower from high-level IR to mid-level IR + + // Check if the environment variable PRINT_AFTER_ALL is set + const char *printAfterAllEnv = std::getenv("PRINT_AFTER_ALL"); + bool printAfterAll = printAfterAllEnv && std::string(printAfterAllEnv) == "true"; + + if(printAfterAll) + context.disableMultithreading(); + + mlir::PassManager pm(&context); + + // If PRINT_AFTER_ALL is set to "true", enable IR printing + if (printAfterAll) { + /* Enable Print After All For Debugging */ + pm.enableIRPrinting( + [=](mlir::Pass *a, Operation *b) { return false; }, // Don't print before passes + [=](mlir::Pass *a, Operation *b) { return true; }, // Print after every pass + true, // Print at module scope + false // Print after every pass, regardless of changes + ); + } pm.addPass(std::make_unique( serializer, representation)); diff --git a/src/mlir/LowerToLLVM.cpp b/src/mlir/LowerToLLVM.cpp index 401a129..263e77b 100644 --- a/src/mlir/LowerToLLVM.cpp +++ b/src/mlir/LowerToLLVM.cpp @@ -186,7 +186,27 @@ void LowerToLLVM(mlir::MLIRContext &context, mlir::ModuleOp module, std::shared_ptr representation) { // llvm::DebugFlag = true; // Lower from low-level IR to LLVM IR + + // Check if the environment variable PRINT_AFTER_ALL is set + const char *printAfterAllEnv = std::getenv("PRINT_AFTER_ALL"); + bool printAfterAll = printAfterAllEnv && std::string(printAfterAllEnv) == "true"; + + if(printAfterAll) + context.disableMultithreading(); + + mlir::PassManager pm(&context); + + // If PRINT_AFTER_ALL is set to "true", enable IR printing + if (printAfterAll) { + /* Enable Print After All For Debugging */ + pm.enableIRPrinting( + [=](mlir::Pass *a, Operation *b) { return false; }, // Don't print before passes + [=](mlir::Pass *a, Operation *b) { return true; }, // Print after every pass + true, // Print at module scope + false // Print after every pass, regardless of changes + ); + } pm.addPass(memref::createExpandStridedMetadataPass()); pm.addPass( std::make_unique(representation)); diff --git a/src/mlir/LowerToMidLevelIR.cpp b/src/mlir/LowerToMidLevelIR.cpp index 49505e9..130043a 100644 --- a/src/mlir/LowerToMidLevelIR.cpp +++ b/src/mlir/LowerToMidLevelIR.cpp @@ -1464,7 +1464,28 @@ void LowerFromHighLevelToMidLevelIR(mlir::MLIRContext &context, mlir::ModuleOp module) { // llvm::DebugFlag = true; // Lower from high-level IR to mid-level IR + + // Check if the environment variable PRINT_AFTER_ALL is set + const char *printAfterAllEnv = std::getenv("PRINT_AFTER_ALL"); + bool printAfterAll = printAfterAllEnv && std::string(printAfterAllEnv) == "true"; + + if(printAfterAll) + context.disableMultithreading(); + + mlir::PassManager pm(&context); + + // If PRINT_AFTER_ALL is set to "true", enable IR printing + if (printAfterAll) { + /* Enable Print After All For Debugging */ + pm.enableIRPrinting( + [=](mlir::Pass *a, Operation *b) { return false; }, // Don't print before passes + [=](mlir::Pass *a, Operation *b) { return true; }, // Print after every pass + true, // Print at module scope + false // Print after every pass, regardless of changes + ); + } + pm.addPass(std::make_unique()); AddWalkDecisionTreeOpLoweringPass(pm); diff --git a/src/mlir/ProbabilityBasedTilingTransform.cpp b/src/mlir/ProbabilityBasedTilingTransform.cpp index cef5824..1bf7f68 100644 --- a/src/mlir/ProbabilityBasedTilingTransform.cpp +++ b/src/mlir/ProbabilityBasedTilingTransform.cpp @@ -240,7 +240,26 @@ namespace mlir namespace decisionforest { void DoProbabilityBasedTiling(mlir::MLIRContext& context, mlir::ModuleOp module, int32_t tileSize, int32_t tileShapeBitWidth) { + // Check if the environment variable PRINT_AFTER_ALL is set + const char *printAfterAllEnv = std::getenv("PRINT_AFTER_ALL"); + bool printAfterAll = printAfterAllEnv && std::string(printAfterAllEnv) == "true"; + + if(printAfterAll) + context.disableMultithreading(); + + mlir::PassManager pm(&context); + + // If PRINT_AFTER_ALL is set to "true", enable IR printing + if (printAfterAll) { + /* Enable Print After All For Debugging */ + pm.enableIRPrinting( + [=](mlir::Pass *a, Operation *b) { return false; }, // Don't print before passes + [=](mlir::Pass *a, Operation *b) { return true; }, // Print after every pass + true, // Print at module scope + false // Print after every pass, regardless of changes + ); + } pm.addPass(std::make_unique(tileSize, tileShapeBitWidth)); if (mlir::failed(pm.run(module))) { @@ -249,7 +268,26 @@ void DoProbabilityBasedTiling(mlir::MLIRContext& context, mlir::ModuleOp module, } void DoHybridTiling(mlir::MLIRContext& context, mlir::ModuleOp module, int32_t tileSize, int32_t tileShapeBitWidth) { + // Check if the environment variable PRINT_AFTER_ALL is set + const char *printAfterAllEnv = std::getenv("PRINT_AFTER_ALL"); + bool printAfterAll = printAfterAllEnv && std::string(printAfterAllEnv) == "true"; + + if(printAfterAll) + context.disableMultithreading(); + + mlir::PassManager pm(&context); + + // If PRINT_AFTER_ALL is set to "true", enable IR printing + if (printAfterAll) { + /* Enable Print After All For Debugging */ + pm.enableIRPrinting( + [=](mlir::Pass *a, Operation *b) { return false; }, // Don't print before passes + [=](mlir::Pass *a, Operation *b) { return true; }, // Print after every pass + true, // Print at module scope + false // Print after every pass, regardless of changes + ); + } pm.addPass(std::make_unique(tileSize, tileShapeBitWidth, true, 0.20)); if (mlir::failed(pm.run(module))) { diff --git a/src/mlir/ReorderTiledTreesByDepth.cpp b/src/mlir/ReorderTiledTreesByDepth.cpp index 96cda8b..d7742c2 100644 --- a/src/mlir/ReorderTiledTreesByDepth.cpp +++ b/src/mlir/ReorderTiledTreesByDepth.cpp @@ -482,7 +482,26 @@ namespace decisionforest { void DoReorderTreesByDepth(mlir::MLIRContext &context, mlir::ModuleOp module, int32_t pipelineSize, int32_t numCores, int32_t parallelTreeBatches) { + // Check if the environment variable PRINT_AFTER_ALL is set + const char *printAfterAllEnv = std::getenv("PRINT_AFTER_ALL"); + bool printAfterAll = printAfterAllEnv && std::string(printAfterAllEnv) == "true"; + + if(printAfterAll) + context.disableMultithreading(); + + mlir::PassManager pm(&context); + + // If PRINT_AFTER_ALL is set to "true", enable IR printing + if (printAfterAll) { + /* Enable Print After All For Debugging */ + pm.enableIRPrinting( + [=](mlir::Pass *a, Operation *b) { return false; }, // Don't print before passes + [=](mlir::Pass *a, Operation *b) { return true; }, // Print after every pass + true, // Print at module scope + false // Print after every pass, regardless of changes + ); + } pm.addPass(std::make_unique()); // TODO pipelineSize needs to be added to CompilerOptions pm.addPass(std::make_unique(pipelineSize, numCores, diff --git a/src/mlir/UniformTilingTransformation.cpp b/src/mlir/UniformTilingTransformation.cpp index bc05126..1c0a2cc 100644 --- a/src/mlir/UniformTilingTransformation.cpp +++ b/src/mlir/UniformTilingTransformation.cpp @@ -245,7 +245,26 @@ namespace decisionforest { void DoUniformTiling(mlir::MLIRContext &context, mlir::ModuleOp module, int32_t tileSize, int32_t tileShapeBitWidth, bool makeAllLeavesSameDepth) { + // Check if the environment variable PRINT_AFTER_ALL is set + const char *printAfterAllEnv = std::getenv("PRINT_AFTER_ALL"); + bool printAfterAll = printAfterAllEnv && std::string(printAfterAllEnv) == "true"; + + if(printAfterAll) + context.disableMultithreading(); + + mlir::PassManager pm(&context); + + // If PRINT_AFTER_ALL is set to "true", enable IR printing + if (printAfterAll) { + /* Enable Print After All For Debugging */ + pm.enableIRPrinting( + [=](mlir::Pass *a, Operation *b) { return false; }, // Don't print before passes + [=](mlir::Pass *a, Operation *b) { return true; }, // Print after every pass + true, // Print at module scope + false // Print after every pass, regardless of changes + ); + } pm.addPass(std::make_unique(tileSize, tileShapeBitWidth, makeAllLeavesSameDepth)); @@ -256,7 +275,26 @@ void DoUniformTiling(mlir::MLIRContext &context, mlir::ModuleOp module, void padTreesToMakeAllLeavesSameDepth(mlir::MLIRContext &context, mlir::ModuleOp module) { + // Check if the environment variable PRINT_AFTER_ALL is set + const char *printAfterAllEnv = std::getenv("PRINT_AFTER_ALL"); + bool printAfterAll = printAfterAllEnv && std::string(printAfterAllEnv) == "true"; + + if(printAfterAll) + context.disableMultithreading(); + + mlir::PassManager pm(&context); + + // If PRINT_AFTER_ALL is set to "true", enable IR printing + if (printAfterAll) { + /* Enable Print After All For Debugging */ + pm.enableIRPrinting( + [=](mlir::Pass *a, Operation *b) { return false; }, // Don't print before passes + [=](mlir::Pass *a, Operation *b) { return true; }, // Print after every pass + true, // Print at module scope + false // Print after every pass, regardless of changes + ); + } mlir::OpPassManager &optPM = pm.nest(); optPM.addPass(std::make_unique()); diff --git a/src/reduction/CooperativeReduce.cpp b/src/reduction/CooperativeReduce.cpp index d25b976..1be5911 100644 --- a/src/reduction/CooperativeReduce.cpp +++ b/src/reduction/CooperativeReduce.cpp @@ -390,7 +390,27 @@ struct ConvertReductionsToCooperativeReductions void runConvertToCooperativeReducePass(mlir::MLIRContext &context, mlir::ModuleOp module) { // llvm::DebugFlag = true; + + // Check if the environment variable PRINT_AFTER_ALL is set + const char *printAfterAllEnv = std::getenv("PRINT_AFTER_ALL"); + bool printAfterAll = printAfterAllEnv && std::string(printAfterAllEnv) == "true"; + + if(printAfterAll) + context.disableMultithreading(); + + mlir::PassManager pm(&context); + + // If PRINT_AFTER_ALL is set to "true", enable IR printing + if (printAfterAll) { + /* Enable Print After All For Debugging */ + pm.enableIRPrinting( + [=](mlir::Pass *a, Operation *b) { return false; }, // Don't print before passes + [=](mlir::Pass *a, Operation *b) { return true; }, // Print after every pass + true, // Print at module scope + false // Print after every pass, regardless of changes + ); + } auto &nestedPM = pm.nest(); nestedPM.addPass( std::make_unique()); diff --git a/src/reduction/LegalizeReduceOpPass.cpp b/src/reduction/LegalizeReduceOpPass.cpp index 2605ce1..a410e00 100644 --- a/src/reduction/LegalizeReduceOpPass.cpp +++ b/src/reduction/LegalizeReduceOpPass.cpp @@ -879,7 +879,27 @@ struct LegalizeReductions void legalizeReductions(mlir::MLIRContext &context, mlir::ModuleOp module) { // llvm::DebugFlag = true; // Lower from high-level IR to mid-level IR + + // Check if the environment variable PRINT_AFTER_ALL is set + const char *printAfterAllEnv = std::getenv("PRINT_AFTER_ALL"); + bool printAfterAll = printAfterAllEnv && std::string(printAfterAllEnv) == "true"; + + if(printAfterAll) + context.disableMultithreading(); + + mlir::PassManager pm(&context); + + // If PRINT_AFTER_ALL is set to "true", enable IR printing + if (printAfterAll) { + /* Enable Print After All For Debugging */ + pm.enableIRPrinting( + [=](mlir::Pass *a, Operation *b) { return false; }, // Don't print before passes + [=](mlir::Pass *a, Operation *b) { return true; }, // Print after every pass + true, // Print at module scope + false // Print after every pass, regardless of changes + ); + } mlir::OpPassManager &optPM = pm.nest(); optPM.addPass(std::make_unique()); @@ -892,7 +912,27 @@ void legalizeReductions(mlir::MLIRContext &context, mlir::ModuleOp module) { void lowerLinalgToLoops(mlir::MLIRContext &context, mlir::ModuleOp module) { // llvm::DebugFlag = true; // Lower from high-level IR to mid-level IR + + // Check if the environment variable PRINT_AFTER_ALL is set + const char *printAfterAllEnv = std::getenv("PRINT_AFTER_ALL"); + bool printAfterAll = printAfterAllEnv && std::string(printAfterAllEnv) == "true"; + + if(printAfterAll) + context.disableMultithreading(); + + mlir::PassManager pm(&context); + + // If PRINT_AFTER_ALL is set to "true", enable IR printing + if (printAfterAll) { + /* Enable Print After All For Debugging */ + pm.enableIRPrinting( + [=](mlir::Pass *a, Operation *b) { return false; }, // Don't print before passes + [=](mlir::Pass *a, Operation *b) { return true; }, // Print after every pass + true, // Print at module scope + false // Print after every pass, regardless of changes + ); + } mlir::OpPassManager &optPM = pm.nest(); optPM.addPass(createConvertLinalgToLoopsPass()); diff --git a/src/reduction/LowerReduceOps.cpp b/src/reduction/LowerReduceOps.cpp index b852f81..1616e55 100644 --- a/src/reduction/LowerReduceOps.cpp +++ b/src/reduction/LowerReduceOps.cpp @@ -1476,7 +1476,27 @@ namespace decisionforest { void lowerReduceToMemref(mlir::MLIRContext &context, mlir::ModuleOp module) { // llvm::DebugFlag = true; // Lower from high-level IR to mid-level IR + + // Check if the environment variable PRINT_AFTER_ALL is set + const char *printAfterAllEnv = std::getenv("PRINT_AFTER_ALL"); + bool printAfterAll = printAfterAllEnv && std::string(printAfterAllEnv) == "true"; + + if(printAfterAll) + context.disableMultithreading(); + + mlir::PassManager pm(&context); + + // If PRINT_AFTER_ALL is set to "true", enable IR printing + if (printAfterAll) { + /* Enable Print After All For Debugging */ + pm.enableIRPrinting( + [=](mlir::Pass *a, Operation *b) { return false; }, // Don't print before passes + [=](mlir::Pass *a, Operation *b) { return true; }, // Print after every pass + true, // Print at module scope + false // Print after every pass, regardless of changes + ); + } mlir::OpPassManager &optPM = pm.nest(); optPM.addPass(std::make_unique()); diff --git a/src/test/TestMain.cpp b/src/test/TestMain.cpp index d68020c..6b5d652 100644 --- a/src/test/TestMain.cpp +++ b/src/test/TestMain.cpp @@ -19,6 +19,7 @@ #include #include + using namespace mlir::decisionforest; namespace TreeBeard { @@ -892,6 +893,7 @@ bool Test_TileSize8_Year_TestInputs_CPUAutoSchedule_TreeParallel_f32i16( bool Test_GPUCodeGeneration_Abalone_SparseRep_f32i16_B32_iterativeCachedPartialForestStrategy_NoCache_SharedReduce( TestArgs_t &args); + void InitializeVectorWithRandValues(std::vector &vec) { for (size_t i = 0; i < vec.size(); ++i) vec[i] = (double)rand() / RAND_MAX; @@ -1638,6 +1640,568 @@ bool Test_SplitSchedule(TestArgs_t &args) { return true; } + +std::map testFuncMap = { + {"Test_TiledCodeGeneration_LeftHeavy_BatchSize1", Test_TiledCodeGeneration_LeftHeavy_BatchSize1}, + {"Test_TiledCodeGeneration_RightHeavy_BatchSize1", Test_TiledCodeGeneration_RightHeavy_BatchSize1}, + {"Test_TiledCodeGeneration_BalancedTree_BatchSize1", Test_TiledCodeGeneration_BalancedTree_BatchSize1}, + {"Test_TiledCodeGeneration_LeftAndRightHeavy_BatchSize1", Test_TiledCodeGeneration_LeftAndRightHeavy_BatchSize1}, + {"Test_TiledCodeGeneration_RightHeavy_BatchSize1_Int8TileShape", Test_TiledCodeGeneration_RightHeavy_BatchSize1_Int8TileShape}, + {"Test_TiledCodeGeneration_LeftHeavy_BatchSize1_Int8TileShape", Test_TiledCodeGeneration_LeftHeavy_BatchSize1_Int8TileShape}, + {"Test_TiledCodeGeneration_RightHeavy_BatchSize1_Int16TileShape", Test_TiledCodeGeneration_RightHeavy_BatchSize1_Int16TileShape}, + {"Test_TiledCodeGeneration_LeftHeavy_BatchSize1_Int16TileShape", Test_TiledCodeGeneration_LeftHeavy_BatchSize1_Int16TileShape}, + {"Test_TiledCodeGeneration_LeftAndRightHeavy_BatchSize1_Int8TileSize", Test_TiledCodeGeneration_LeftAndRightHeavy_BatchSize1_Int8TileSize}, + {"Test_TiledCodeGeneration_LeftAndRightHeavy_BatchSize1_Int16TileSize", Test_TiledCodeGeneration_LeftAndRightHeavy_BatchSize1_Int16TileSize}, + {"Test_UniformTiling_LeftHeavy_BatchSize1", Test_UniformTiling_LeftHeavy_BatchSize1}, + {"Test_UniformTiling_RightHeavy_BatchSize1", Test_UniformTiling_RightHeavy_BatchSize1}, + {"Test_UniformTiling_Balanced_BatchSize1", Test_UniformTiling_Balanced_BatchSize1}, + {"Test_UniformTiling_LeftfAndRighttHeavy_BatchSize1", Test_UniformTiling_LeftfAndRighttHeavy_BatchSize1}, + {"Test_UniformTiling_LeftHeavy_BatchSize1_Int8TileShape", Test_UniformTiling_LeftHeavy_BatchSize1_Int8TileShape}, + {"Test_UniformTiling_RightHeavy_BatchSize1_Int8TileShape", Test_UniformTiling_RightHeavy_BatchSize1_Int8TileShape}, + {"Test_UniformTiling_Balanced_BatchSize1_Int8TileShape", Test_UniformTiling_Balanced_BatchSize1_Int8TileShape}, + {"Test_UniformTiling_LeftfAndRighttHeavy_BatchSize1_Int8TileShape", Test_UniformTiling_LeftfAndRighttHeavy_BatchSize1_Int8TileShape}, + {"Test_UniformTiling_LeftHeavy_BatchSize1_Int16TileShape", Test_UniformTiling_LeftHeavy_BatchSize1_Int16TileShape}, + {"Test_UniformTiling_RightHeavy_BatchSize1_Int16TileShape", Test_UniformTiling_RightHeavy_BatchSize1_Int16TileShape}, + {"Test_UniformTiling_Balanced_BatchSize1_Int16TileShape", Test_UniformTiling_Balanced_BatchSize1_Int16TileShape}, + {"Test_UniformTiling_LeftfAndRighttHeavy_BatchSize1_Int16TileShape", Test_UniformTiling_LeftfAndRighttHeavy_BatchSize1_Int16TileShape}, + {"Test_UniformTiling_RandomXGBoostJSONs_1Tree_BatchSize1", Test_UniformTiling_RandomXGBoostJSONs_1Tree_BatchSize1}, + {"Test_UniformTiling_RandomXGBoostJSONs_2Trees_BatchSize1", Test_UniformTiling_RandomXGBoostJSONs_2Trees_BatchSize1}, + {"Test_UniformTiling_RandomXGBoostJSONs_4Trees_BatchSize1", Test_UniformTiling_RandomXGBoostJSONs_4Trees_BatchSize1}, + {"Test_UniformTiling_RandomXGBoostJSONs_1Tree_BatchSize2", Test_UniformTiling_RandomXGBoostJSONs_1Tree_BatchSize2}, + {"Test_UniformTiling_RandomXGBoostJSONs_2Trees_BatchSize2", Test_UniformTiling_RandomXGBoostJSONs_2Trees_BatchSize2}, + {"Test_UniformTiling_RandomXGBoostJSONs_4Trees_BatchSize2", Test_UniformTiling_RandomXGBoostJSONs_4Trees_BatchSize2}, + {"Test_UniformTiling_RandomXGBoostJSONs_1Tree_BatchSize4", Test_UniformTiling_RandomXGBoostJSONs_1Tree_BatchSize4}, + {"Test_UniformTiling_RandomXGBoostJSONs_2Trees_BatchSize4", Test_UniformTiling_RandomXGBoostJSONs_2Trees_BatchSize4}, + {"Test_UniformTiling_RandomXGBoostJSONs_4Trees_BatchSize4", Test_UniformTiling_RandomXGBoostJSONs_4Trees_BatchSize4}, + {"Test_UniformTiling_RandomXGBoostJSONs_1Tree_BatchSize4_Int8TileShape", Test_UniformTiling_RandomXGBoostJSONs_1Tree_BatchSize4_Int8TileShape}, + {"Test_UniformTiling_RandomXGBoostJSONs_1Tree_BatchSize4_Int16TileShape", Test_UniformTiling_RandomXGBoostJSONs_1Tree_BatchSize4_Int16TileShape}, + {"Test_UniformTiling_RandomXGBoostJSONs_2Trees_BatchSize4_Int8TileShape", Test_UniformTiling_RandomXGBoostJSONs_2Trees_BatchSize4_Int8TileShape}, + {"Test_UniformTiling_RandomXGBoostJSONs_2Trees_BatchSize4_Int16TileShape", Test_UniformTiling_RandomXGBoostJSONs_2Trees_BatchSize4_Int16TileShape}, + {"Test_UniformTiling_RandomXGBoostJSONs_4Trees_BatchSize4_Int8TileShape", Test_UniformTiling_RandomXGBoostJSONs_4Trees_BatchSize4_Int8TileShape}, + {"Test_UniformTiling_RandomXGBoostJSONs_4Trees_BatchSize4_Int16TileShape", Test_UniformTiling_RandomXGBoostJSONs_4Trees_BatchSize4_Int16TileShape}, + {"Test_Scalar_Abalone", Test_Scalar_Abalone}, + {"Test_TileSize2_Abalone", Test_TileSize2_Abalone}, + {"Test_TileSize3_Abalone", Test_TileSize3_Abalone}, + {"Test_TileSize4_Abalone", Test_TileSize4_Abalone}, + {"Test_TileSize8_Abalone", Test_TileSize8_Abalone}, + {"Test_Scalar_Airline", Test_Scalar_Airline}, + {"Test_TileSize2_Airline", Test_TileSize2_Airline}, + {"Test_TileSize3_Airline", Test_TileSize3_Airline}, + {"Test_TileSize4_Airline", Test_TileSize4_Airline}, + {"Test_TileSize8_Airline", Test_TileSize8_Airline}, + {"Test_Scalar_AirlineOHE", Test_Scalar_AirlineOHE}, + {"Test_TileSize2_AirlineOHE", Test_TileSize2_AirlineOHE}, + {"Test_TileSize3_AirlineOHE", Test_TileSize3_AirlineOHE}, + {"Test_TileSize4_AirlineOHE", Test_TileSize4_AirlineOHE}, + {"Test_TileSize8_AirlineOHE", Test_TileSize8_AirlineOHE}, + {"Test_Scalar_Bosch", Test_Scalar_Bosch}, + {"Test_TileSize2_Bosch", Test_TileSize2_Bosch}, + {"Test_TileSize3_Bosch", Test_TileSize3_Bosch}, + {"Test_TileSize4_Bosch", Test_TileSize4_Bosch}, + {"Test_TileSize8_Bosch", Test_TileSize8_Bosch}, + {"Test_Scalar_Epsilon", Test_Scalar_Epsilon}, + {"Test_TileSize2_Epsilon", Test_TileSize2_Epsilon}, + {"Test_TileSize3_Epsilon", Test_TileSize3_Epsilon}, + {"Test_TileSize4_Epsilon", Test_TileSize4_Epsilon}, + {"Test_TileSize8_Epsilon", Test_TileSize8_Epsilon}, + {"Test_Scalar_Higgs", Test_Scalar_Higgs}, + {"Test_TileSize2_Higgs", Test_TileSize2_Higgs}, + {"Test_TileSize3_Higgs", Test_TileSize3_Higgs}, + {"Test_TileSize4_Higgs", Test_TileSize4_Higgs}, + {"Test_TileSize8_Higgs", Test_TileSize8_Higgs}, + {"Test_TileSize1_Letters_Int8Type", Test_TileSize1_Letters_Int8Type}, + {"Test_TileSize2_Letters_Int8Type", Test_TileSize2_Letters_Int8Type}, + {"Test_TileSize3_Letters_Int8Type", Test_TileSize3_Letters_Int8Type}, + {"Test_TileSize4_Letters_Int8Type", Test_TileSize4_Letters_Int8Type}, + {"Test_TileSize8_Letters_Int8Type", Test_TileSize8_Letters_Int8Type}, + {"Test_Scalar_Year", Test_Scalar_Year}, + {"Test_TileSize2_Year", Test_TileSize2_Year}, + {"Test_TileSize3_Year", Test_TileSize3_Year}, + {"Test_TileSize4_Year", Test_TileSize4_Year}, + {"Test_TileSize8_Year", Test_TileSize8_Year}, + {"Test_TileSize1_CovType_Int8Type", Test_TileSize1_CovType_Int8Type}, + {"Test_TileSize2_CovType_Int8Type", Test_TileSize2_CovType_Int8Type}, + {"Test_TileSize3_CovType_Int8Type", Test_TileSize3_CovType_Int8Type}, + {"Test_TileSize4_CovType_Int8Type", Test_TileSize4_CovType_Int8Type}, + {"Test_TileSize8_CovType_Int8Type", Test_TileSize8_CovType_Int8Type}, + {"Test_SparseCodeGeneration_LeftHeavy_BatchSize1_I32ChildIdx", Test_SparseCodeGeneration_LeftHeavy_BatchSize1_I32ChildIdx}, + {"Test_SparseCodeGeneration_RightHeavy_BatchSize1_I32ChildIdx", Test_SparseCodeGeneration_RightHeavy_BatchSize1_I32ChildIdx}, + {"Test_SparseCodeGeneration_RightAndLeftHeavy_BatchSize1_I32ChildIdx", Test_SparseCodeGeneration_RightAndLeftHeavy_BatchSize1_I32ChildIdx}, + {"Test_SparseCodeGeneration_LeftHeavy_BatchSize2_I32ChildIdx", Test_SparseCodeGeneration_LeftHeavy_BatchSize2_I32ChildIdx}, + {"Test_SparseCodeGeneration_RightHeavy_BatchSize2_I32ChildIdx", Test_SparseCodeGeneration_RightHeavy_BatchSize2_I32ChildIdx}, + {"Test_SparseCodeGeneration_RightAndLeftHeavy_BatchSize2_I32ChildIdx", Test_SparseCodeGeneration_RightAndLeftHeavy_BatchSize2_I32ChildIdx}, + {"Test_Sparse_RandomXGBoostJSONs_1Tree_BatchSize1", Test_Sparse_RandomXGBoostJSONs_1Tree_BatchSize1}, + {"Test_Sparse_RandomXGBoostJSONs_1Tree_BatchSize2", Test_Sparse_RandomXGBoostJSONs_1Tree_BatchSize2}, + {"Test_Sparse_RandomXGBoostJSONs_1Tree_BatchSize4", Test_Sparse_RandomXGBoostJSONs_1Tree_BatchSize4}, + {"Test_Sparse_RandomXGBoostJSONs_2Trees_BatchSize1", Test_Sparse_RandomXGBoostJSONs_2Trees_BatchSize1}, + {"Test_Sparse_RandomXGBoostJSONs_2Trees_BatchSize2", Test_Sparse_RandomXGBoostJSONs_2Trees_BatchSize2}, + {"Test_Sparse_RandomXGBoostJSONs_2Trees_BatchSize4", Test_Sparse_RandomXGBoostJSONs_2Trees_BatchSize4}, + {"Test_Sparse_RandomXGBoostJSONs_4Trees_BatchSize1", Test_Sparse_RandomXGBoostJSONs_4Trees_BatchSize1}, + {"Test_Sparse_RandomXGBoostJSONs_4Trees_BatchSize2", Test_Sparse_RandomXGBoostJSONs_4Trees_BatchSize2}, + {"Test_Sparse_RandomXGBoostJSONs_4Trees_BatchSize4", Test_Sparse_RandomXGBoostJSONs_4Trees_BatchSize4}, + {"Test_Sparse_RandomXGBoostJSONs_1Tree_BatchSize1_Float", Test_Sparse_RandomXGBoostJSONs_1Tree_BatchSize1_Float}, + {"Test_Sparse_RandomXGBoostJSONs_1Tree_BatchSize2_Float", Test_Sparse_RandomXGBoostJSONs_1Tree_BatchSize2_Float}, + {"Test_Sparse_RandomXGBoostJSONs_1Tree_BatchSize4_Float", Test_Sparse_RandomXGBoostJSONs_1Tree_BatchSize4_Float}, + {"Test_Sparse_RandomXGBoostJSONs_2Trees_BatchSize1_Float", Test_Sparse_RandomXGBoostJSONs_2Trees_BatchSize1_Float}, + {"Test_Sparse_RandomXGBoostJSONs_2Trees_BatchSize2_Float", Test_Sparse_RandomXGBoostJSONs_2Trees_BatchSize2_Float}, + {"Test_Sparse_RandomXGBoostJSONs_2Trees_BatchSize4_Float", Test_Sparse_RandomXGBoostJSONs_2Trees_BatchSize4_Float}, + {"Test_Sparse_RandomXGBoostJSONs_4Trees_BatchSize1_Float", Test_Sparse_RandomXGBoostJSONs_4Trees_BatchSize1_Float}, + {"Test_Sparse_RandomXGBoostJSONs_4Trees_BatchSize2_Float", Test_Sparse_RandomXGBoostJSONs_4Trees_BatchSize2_Float}, + {"Test_Sparse_RandomXGBoostJSONs_4Trees_BatchSize4_Float", Test_Sparse_RandomXGBoostJSONs_4Trees_BatchSize4_Float}, + {"Test_SparseTiledCodeGeneration_LeftHeavy_BatchSize1", Test_SparseTiledCodeGeneration_LeftHeavy_BatchSize1}, + {"Test_SparseTiledCodeGeneration_LeftHeavy_BatchSize1_Int16TileShape", Test_SparseTiledCodeGeneration_LeftHeavy_BatchSize1_Int16TileShape}, + {"Test_SparseTiledCodeGeneration_LeftHeavy_BatchSize1_Int8TileShape", Test_SparseTiledCodeGeneration_LeftHeavy_BatchSize1_Int8TileShape}, + {"Test_SparseTiledCodeGeneration_LeftAndRightHeavy_BatchSize1_Int8TileSize", Test_SparseTiledCodeGeneration_LeftAndRightHeavy_BatchSize1_Int8TileSize}, + {"Test_SparseTiledCodeGeneration_LeftAndRightHeavy_BatchSize1", Test_SparseTiledCodeGeneration_LeftAndRightHeavy_BatchSize1}, + {"Test_SparseTiledCodeGeneration_LeftAndRightHeavy_BatchSize1_Int16TileSize", Test_SparseTiledCodeGeneration_LeftAndRightHeavy_BatchSize1_Int16TileSize}, + {"Test_SparseTiledCodeGeneration_RightHeavy_BatchSize1", Test_SparseTiledCodeGeneration_RightHeavy_BatchSize1}, + {"Test_SparseTiledCodeGeneration_RightHeavy_BatchSize1_Int16TileShape", Test_SparseTiledCodeGeneration_RightHeavy_BatchSize1_Int16TileShape}, + {"Test_SparseTiledCodeGeneration_RightHeavy_BatchSize1_Int8TileShape", Test_SparseTiledCodeGeneration_RightHeavy_BatchSize1_Int8TileShape}, + {"Test_SparseUniformTiling_RandomXGBoostJSONs_2Trees_BatchSize4", Test_SparseUniformTiling_RandomXGBoostJSONs_2Trees_BatchSize4}, + {"Test_SparseUniformTiling_RandomXGBoostJSONs_4Trees_BatchSize4", Test_SparseUniformTiling_RandomXGBoostJSONs_4Trees_BatchSize4}, + {"Test_SparseScalar_Abalone", Test_SparseScalar_Abalone}, + {"Test_SparseTileSize2_Abalone", Test_SparseTileSize2_Abalone}, + {"Test_SparseTileSize3_Abalone", Test_SparseTileSize3_Abalone}, + {"Test_SparseTileSize4_Abalone", Test_SparseTileSize4_Abalone}, + {"Test_SparseTileSize8_Abalone", Test_SparseTileSize8_Abalone}, + {"Test_SparseScalar_Airline", Test_SparseScalar_Airline}, + {"Test_SparseTileSize2_Airline", Test_SparseTileSize2_Airline}, + {"Test_SparseTileSize3_Airline", Test_SparseTileSize3_Airline}, + {"Test_SparseTileSize4_Airline", Test_SparseTileSize4_Airline}, + {"Test_SparseTileSize8_Airline", Test_SparseTileSize8_Airline}, + {"Test_SparseScalar_AirlineOHE", Test_SparseScalar_AirlineOHE}, + {"Test_SparseTileSize2_AirlineOHE", Test_SparseTileSize2_AirlineOHE}, + {"Test_SparseTileSize3_AirlineOHE", Test_SparseTileSize3_AirlineOHE}, + {"Test_SparseTileSize4_AirlineOHE", Test_SparseTileSize4_AirlineOHE}, + {"Test_SparseTileSize8_AirlineOHE", Test_SparseTileSize8_AirlineOHE}, + {"Test_SparseScalar_Bosch", Test_SparseScalar_Bosch}, + {"Test_SparseTileSize2_Bosch", Test_SparseTileSize2_Bosch}, + {"Test_SparseTileSize3_Bosch", Test_SparseTileSize3_Bosch}, + {"Test_SparseTileSize4_Bosch", Test_SparseTileSize4_Bosch}, + {"Test_SparseTileSize8_Bosch", Test_SparseTileSize8_Bosch}, + {"Test_SparseTileSize8_CovType_Int8Type", Test_SparseTileSize8_CovType_Int8Type}, + {"Test_SparseScalar_CovType_Int8Type", Test_SparseScalar_CovType_Int8Type}, + {"Test_SparseScalar_Letters_Int8Type", Test_SparseScalar_Letters_Int8Type}, + {"Test_SparseTileSize8_Letters_Int8Type", Test_SparseTileSize8_Letters_Int8Type}, + {"Test_SparseScalar_Epsilon", Test_SparseScalar_Epsilon}, + {"Test_SparseTileSize2_Epsilon", Test_SparseTileSize2_Epsilon}, + {"Test_SparseTileSize3_Epsilon", Test_SparseTileSize3_Epsilon}, + {"Test_SparseTileSize4_Epsilon", Test_SparseTileSize4_Epsilon}, + {"Test_SparseTileSize8_Epsilon", Test_SparseTileSize8_Epsilon}, + {"Test_SparseScalar_Higgs", Test_SparseScalar_Higgs}, + {"Test_SparseTileSize2_Higgs", Test_SparseTileSize2_Higgs}, + {"Test_SparseTileSize3_Higgs", Test_SparseTileSize3_Higgs}, + {"Test_SparseTileSize4_Higgs", Test_SparseTileSize4_Higgs}, + {"Test_SparseTileSize8_Higgs", Test_SparseTileSize8_Higgs}, + {"Test_SparseScalar_Year", Test_SparseScalar_Year}, + {"Test_SparseTileSize2_Year", Test_SparseTileSize2_Year}, + {"Test_SparseTileSize3_Year", Test_SparseTileSize3_Year}, + {"Test_SparseTileSize4_Year", Test_SparseTileSize4_Year}, + {"Test_SparseTileSize8_Year", Test_SparseTileSize8_Year}, + {"Test_TileSize8_Abalone_TestInputs", Test_TileSize8_Abalone_TestInputs}, + {"Test_TileSize8_Airline_TestInputs", Test_TileSize8_Airline_TestInputs}, + {"Test_TileSize8_AirlineOHE_TestInputs", Test_TileSize8_AirlineOHE_TestInputs}, + {"Test_TileSize8_Epsilon_TestInputs", Test_TileSize8_Epsilon_TestInputs}, + {"Test_TileSize8_Higgs_TestInputs", Test_TileSize8_Higgs_TestInputs}, + {"Test_TileSize8_Year_TestInputs", Test_TileSize8_Year_TestInputs}, + {"Test_TileSize8_CovType_TestInputs", Test_TileSize8_CovType_TestInputs}, + {"Test_CodeGeneration_LeftHeavy_BatchSize2_XGBoostSchedule", Test_CodeGeneration_LeftHeavy_BatchSize2_XGBoostSchedule}, + {"Test_CodeGeneration_RightHeavy_BatchSize2_XGBoostSchedule", Test_CodeGeneration_RightHeavy_BatchSize2_XGBoostSchedule}, + {"Test_CodeGeneration_AddRightAndLeftHeavyTrees_BatchSize2_XGBoostSchedule", Test_CodeGeneration_AddRightAndLeftHeavyTrees_BatchSize2_XGBoostSchedule}, + {"Test_CodeGeneration_LeftHeavy_BatchSize8_CacheInputSchedule", Test_CodeGeneration_LeftHeavy_BatchSize8_CacheInputSchedule}, + {"Test_CodeGeneration_RightHeavy_BatchSize2_CacheInputSchedule", Test_CodeGeneration_RightHeavy_BatchSize2_CacheInputSchedule}, + {"Test_CodeGeneration_AddRightAndLeftHeavyTrees_BatchSize2_CacheInputSchedule", Test_CodeGeneration_AddRightAndLeftHeavyTrees_BatchSize2_CacheInputSchedule}, + {"Test_Scalar_Abalone_OneTreeAtATimeSchedule", Test_Scalar_Abalone_OneTreeAtATimeSchedule}, + {"Test_TileSize2_Abalone_OneTreeAtATimeSchedule", Test_TileSize2_Abalone_OneTreeAtATimeSchedule}, + {"Test_TileSize3_Abalone_OneTreeAtATimeSchedule", Test_TileSize3_Abalone_OneTreeAtATimeSchedule}, + {"Test_TileSize4_Abalone_OneTreeAtATimeSchedule", Test_TileSize4_Abalone_OneTreeAtATimeSchedule}, + {"Test_TileSize8_Abalone_OneTreeAtATimeSchedule", Test_TileSize8_Abalone_OneTreeAtATimeSchedule}, + {"Test_Scalar_Airline_OneTreeAtATimeSchedule", Test_Scalar_Airline_OneTreeAtATimeSchedule}, + {"Test_TileSize2_Airline_OneTreeAtATimeSchedule", Test_TileSize2_Airline_OneTreeAtATimeSchedule}, + {"Test_TileSize3_Airline_OneTreeAtATimeSchedule", Test_TileSize3_Airline_OneTreeAtATimeSchedule}, + {"Test_TileSize4_Airline_OneTreeAtATimeSchedule", Test_TileSize4_Airline_OneTreeAtATimeSchedule}, + {"Test_TileSize8_Airline_OneTreeAtATimeSchedule", Test_TileSize8_Airline_OneTreeAtATimeSchedule}, + {"Test_Scalar_AirlineOHE_OneTreeAtATimeSchedule", Test_Scalar_AirlineOHE_OneTreeAtATimeSchedule}, + {"Test_TileSize2_AirlineOHE_OneTreeAtATimeSchedule", Test_TileSize2_AirlineOHE_OneTreeAtATimeSchedule}, + {"Test_TileSize3_AirlineOHE_OneTreeAtATimeSchedule", Test_TileSize3_AirlineOHE_OneTreeAtATimeSchedule}, + {"Test_TileSize4_AirlineOHE_OneTreeAtATimeSchedule", Test_TileSize4_AirlineOHE_OneTreeAtATimeSchedule}, + {"Test_TileSize8_AirlineOHE_OneTreeAtATimeSchedule", Test_TileSize8_AirlineOHE_OneTreeAtATimeSchedule}, + {"Test_Scalar_Bosch_OneTreeAtATimeSchedule", Test_Scalar_Bosch_OneTreeAtATimeSchedule}, + {"Test_TileSize2_Bosch_OneTreeAtATimeSchedule", Test_TileSize2_Bosch_OneTreeAtATimeSchedule}, + {"Test_TileSize3_Bosch_OneTreeAtATimeSchedule", Test_TileSize3_Bosch_OneTreeAtATimeSchedule}, + {"Test_TileSize4_Bosch_OneTreeAtATimeSchedule", Test_TileSize4_Bosch_OneTreeAtATimeSchedule}, + {"Test_TileSize8_Bosch_OneTreeAtATimeSchedule", Test_TileSize8_Bosch_OneTreeAtATimeSchedule}, + {"Test_Scalar_CovType_OneTreeAtATimeSchedule", Test_Scalar_CovType_OneTreeAtATimeSchedule}, + {"Test_TileSize8_CovType_OneTreeAtATimeSchedule", Test_TileSize8_CovType_OneTreeAtATimeSchedule}, + {"Test_Scalar_Epsilon_OneTreeAtATimeSchedule", Test_Scalar_Epsilon_OneTreeAtATimeSchedule}, + {"Test_TileSize2_Epsilon_OneTreeAtATimeSchedule", Test_TileSize2_Epsilon_OneTreeAtATimeSchedule}, + {"Test_TileSize3_Epsilon_OneTreeAtATimeSchedule", Test_TileSize3_Epsilon_OneTreeAtATimeSchedule}, + {"Test_TileSize4_Epsilon_OneTreeAtATimeSchedule", Test_TileSize4_Epsilon_OneTreeAtATimeSchedule}, + {"Test_TileSize8_Epsilon_OneTreeAtATimeSchedule", Test_TileSize8_Epsilon_OneTreeAtATimeSchedule}, + {"Test_Scalar_Higgs_OneTreeAtATimeSchedule", Test_Scalar_Higgs_OneTreeAtATimeSchedule}, + {"Test_TileSize2_Higgs_OneTreeAtATimeSchedule", Test_TileSize2_Higgs_OneTreeAtATimeSchedule}, + {"Test_TileSize3_Higgs_OneTreeAtATimeSchedule", Test_TileSize3_Higgs_OneTreeAtATimeSchedule}, + {"Test_TileSize4_Higgs_OneTreeAtATimeSchedule", Test_TileSize4_Higgs_OneTreeAtATimeSchedule}, + {"Test_TileSize8_Higgs_OneTreeAtATimeSchedule", Test_TileSize8_Higgs_OneTreeAtATimeSchedule}, + {"Test_Scalar_Year_OneTreeAtATimeSchedule", Test_Scalar_Year_OneTreeAtATimeSchedule}, + {"Test_TileSize2_Year_OneTreeAtATimeSchedule", Test_TileSize2_Year_OneTreeAtATimeSchedule}, + {"Test_TileSize3_Year_OneTreeAtATimeSchedule", Test_TileSize3_Year_OneTreeAtATimeSchedule}, + {"Test_TileSize4_Year_OneTreeAtATimeSchedule", Test_TileSize4_Year_OneTreeAtATimeSchedule}, + {"Test_TileSize8_Year_OneTreeAtATimeSchedule", Test_TileSize8_Year_OneTreeAtATimeSchedule}, + {"Test_TileSize8_Abalone_TestInputs_TiledSchedule", Test_TileSize8_Abalone_TestInputs_TiledSchedule}, + {"Test_TileSize8_AirlineOHE_TestInputs_TiledSchedule", Test_TileSize8_AirlineOHE_TestInputs_TiledSchedule}, + {"Test_TileSize8_Airline_TestInputs_TiledSchedule", Test_TileSize8_Airline_TestInputs_TiledSchedule}, + {"Test_TileSize8_Epsilon_TestInputs_TiledSchedule", Test_TileSize8_Epsilon_TestInputs_TiledSchedule}, + {"Test_TileSize8_Higgs_TestInputs_TiledSchedule", Test_TileSize8_Higgs_TestInputs_TiledSchedule}, + {"Test_TileSize8_Year_TestInputs_TiledSchedule", Test_TileSize8_Year_TestInputs_TiledSchedule}, + {"Test_SparseTileSize8_Letters_TiledSchedule", Test_SparseTileSize8_Letters_TiledSchedule}, + + // Sparse code gen tests with loops interchanged + {"Test_SparseScalar_Abalone_OneTreeAtATimeSchedule", Test_SparseScalar_Abalone_OneTreeAtATimeSchedule}, + {"Test_SparseTileSize8_Abalone_OneTreeAtATimeSchedule", Test_SparseTileSize8_Abalone_OneTreeAtATimeSchedule}, + {"Test_SparseScalar_Airline_OneTreeAtATimeSchedule", Test_SparseScalar_Airline_OneTreeAtATimeSchedule}, + {"Test_SparseTileSize8_Airline_OneTreeAtATimeSchedule", Test_SparseTileSize8_Airline_OneTreeAtATimeSchedule}, + {"Test_SparseScalar_AirlineOHE_OneTreeAtATimeSchedule", Test_SparseScalar_AirlineOHE_OneTreeAtATimeSchedule}, + {"Test_SparseTileSize8_AirlineOHE_OneTreeAtATimeSchedule", Test_SparseTileSize8_AirlineOHE_OneTreeAtATimeSchedule}, + {"Test_SparseScalar_Bosch_OneTreeAtATimeSchedule", Test_SparseScalar_Bosch_OneTreeAtATimeSchedule}, + {"Test_SparseTileSize8_Bosch_OneTreeAtATimeSchedule", Test_SparseTileSize8_Bosch_OneTreeAtATimeSchedule}, + {"Test_SparseScalar_CovType_OneTreeAtATimeSchedule", Test_SparseScalar_CovType_OneTreeAtATimeSchedule}, + {"Test_SparseTileSize8_CovType_OneTreeAtATimeSchedule", Test_SparseTileSize8_CovType_OneTreeAtATimeSchedule}, + {"Test_SparseScalar_Letters_OneTreeAtATimeSchedule", Test_SparseScalar_Letters_OneTreeAtATimeSchedule}, + {"Test_SparseTileSize8_Letters_OneTreeAtATimeSchedule", Test_SparseTileSize8_Letters_OneTreeAtATimeSchedule}, + {"Test_SparseTileSize8_Letters_TiledSchedule", Test_SparseTileSize8_Letters_TiledSchedule}, + {"Test_SparseScalar_Epsilon_OneTreeAtATimeSchedule", Test_SparseScalar_Epsilon_OneTreeAtATimeSchedule}, + {"Test_SparseTileSize8_Epsilon_OneTreeAtATimeSchedule", Test_SparseTileSize8_Epsilon_OneTreeAtATimeSchedule}, + {"Test_SparseScalar_Higgs_OneTreeAtATimeSchedule", Test_SparseScalar_Higgs_OneTreeAtATimeSchedule}, + {"Test_SparseTileSize8_Higgs_OneTreeAtATimeSchedule", Test_SparseTileSize8_Higgs_OneTreeAtATimeSchedule}, + {"Test_SparseScalar_Year_OneTreeAtATimeSchedule", Test_SparseScalar_Year_OneTreeAtATimeSchedule}, + {"Test_SparseTileSize8_Year_OneTreeAtATimeSchedule", Test_SparseTileSize8_Year_OneTreeAtATimeSchedule}, + + // Sparse code gen tests with loops tiled + {"Test_SparseTileSize8_Abalone_TestInputs_TiledSchedule", Test_SparseTileSize8_Abalone_TestInputs_TiledSchedule}, + {"Test_SparseTileSize8_AirlineOHE_TestInputs_TiledSchedule", Test_SparseTileSize8_AirlineOHE_TestInputs_TiledSchedule}, + {"Test_SparseTileSize8_Airline_TestInputs_TiledSchedule", Test_SparseTileSize8_Airline_TestInputs_TiledSchedule}, + {"Test_SparseTileSize8_Epsilon_TestInputs_TiledSchedule", Test_SparseTileSize8_Epsilon_TestInputs_TiledSchedule}, + {"Test_SparseTileSize8_Higgs_TestInputs_TiledSchedule", Test_SparseTileSize8_Higgs_TestInputs_TiledSchedule}, + {"Test_SparseTileSize8_Year_TestInputs_TiledSchedule", Test_SparseTileSize8_Year_TestInputs_TiledSchedule}, + + // Stats tests + {"Test_AbaloneStatGenerationAndReading", Test_AbaloneStatGenerationAndReading}, + {"Test_AirlineStatGenerationAndReading", Test_AirlineStatGenerationAndReading}, + {"Test_AirlineOHEStatGenerationAndReading", Test_AirlineOHEStatGenerationAndReading}, + {"Test_CovtypeStatGenerationAndReading", Test_CovtypeStatGenerationAndReading}, + {"Test_EpsilonStatGenerationAndReading", Test_EpsilonStatGenerationAndReading}, + {"Test_HiggsStatGenerationAndReading", Test_HiggsStatGenerationAndReading}, + {"Test_YearStatGenerationAndReading", Test_YearStatGenerationAndReading}, + + // Sparse Probabilistic Tiling Tests + {"Test_SparseProbabilisticTiling_TileSize8_Abalone", Test_SparseProbabilisticTiling_TileSize8_Abalone}, + {"Test_SparseProbabilisticTiling_TileSize8_Airline", Test_SparseProbabilisticTiling_TileSize8_Airline}, + {"Test_SparseProbabilisticTiling_TileSize8_AirlineOHE", Test_SparseProbabilisticTiling_TileSize8_AirlineOHE}, + {"Test_SparseProbabilisticTiling_TileSize8_Covtype", Test_SparseProbabilisticTiling_TileSize8_Covtype}, + {"Test_SparseProbabilisticTiling_TileSize8_Epsilon", Test_SparseProbabilisticTiling_TileSize8_Epsilon}, + {"Test_SparseProbabilisticTiling_TileSize8_Higgs", Test_SparseProbabilisticTiling_TileSize8_Higgs}, + {"Test_SparseProbabilisticTiling_TileSize8_Year", Test_SparseProbabilisticTiling_TileSize8_Year}, + + // Tiled tree padding tests + {"Test_PadTiledTree_BalancedTree_TileSize2", Test_PadTiledTree_BalancedTree_TileSize2}, + {"Test_PadTiledTree_BalancedTree_TileSize2_2", Test_PadTiledTree_BalancedTree_TileSize2_2}, + {"Test_PadTiledTree_BalancedTree_TileSize3", Test_PadTiledTree_BalancedTree_TileSize3}, + {"Test_RandomXGBoostJSONs_1Tree_BatchSize4_EqualDepth_TileSize8", Test_RandomXGBoostJSONs_1Tree_BatchSize4_EqualDepth_TileSize8}, + {"Test_RandomXGBoostJSONs_2Trees_BatchSize4_EqualDepth_TileSize8", Test_RandomXGBoostJSONs_2Trees_BatchSize4_EqualDepth_TileSize8}, + {"Test_RandomXGBoostJSONs_4Trees_BatchSize4_EqualDepth_TileSize8", Test_RandomXGBoostJSONs_4Trees_BatchSize4_EqualDepth_TileSize8}, + {"Test_TileSize8_Abalone_TestInputs_MakeLeavesSameDepth", Test_TileSize8_Abalone_TestInputs_MakeLeavesSameDepth}, + {"Test_TileSize8_AirlineOHE_TestInputs_MakeLeavesSameDepth", Test_TileSize8_AirlineOHE_TestInputs_MakeLeavesSameDepth}, + {"Test_TileSize8_Airline_TestInputs_MakeLeavesSameDepth", Test_TileSize8_Airline_TestInputs_MakeLeavesSameDepth}, + {"Test_TileSize8_Epsilon_TestInputs_MakeLeavesSameDepth", Test_TileSize8_Epsilon_TestInputs_MakeLeavesSameDepth}, + {"Test_TileSize8_Higgs_TestInputs_MakeLeavesSameDepth", Test_TileSize8_Higgs_TestInputs_MakeLeavesSameDepth}, + {"Test_TileSize8_Year_TestInputs_MakeLeavesSameDepth", Test_TileSize8_Year_TestInputs_MakeLeavesSameDepth}, + {"Test_TileSize8_CovType_TestInputs_MakeLeavesSameDepth", Test_TileSize8_CovType_TestInputs_MakeLeavesSameDepth}, + {"Test_TileSize8_Abalone_TestInputs_ReorderTrees", Test_TileSize8_Abalone_TestInputs_ReorderTrees}, + + // // Split Schedule + {"Test_TileSize8_Abalone_TestInputs_SwapAndSplitTreeIndex", Test_TileSize8_Abalone_TestInputs_SwapAndSplitTreeIndex}, + {"Test_TileSize8_AirlineOHE_TestInputs_SwapAndSplitTreeIndex", Test_TileSize8_AirlineOHE_TestInputs_SwapAndSplitTreeIndex}, + {"Test_TileSize8_Airline_TestInputs_SwapAndSplitTreeIndex", Test_TileSize8_Airline_TestInputs_SwapAndSplitTreeIndex}, + {"Test_TileSize8_Epsilon_TestInputs_SwapAndSplitTreeIndex", Test_TileSize8_Epsilon_TestInputs_SwapAndSplitTreeIndex}, + {"Test_TileSize8_Higgs_TestInputs_SwapAndSplitTreeIndex", Test_TileSize8_Higgs_TestInputs_SwapAndSplitTreeIndex}, + {"Test_TileSize8_Year_TestInputs_SwapAndSplitTreeIndex", Test_TileSize8_Year_TestInputs_SwapAndSplitTreeIndex}, + +#ifdef OMP_SUPPORT + {"Test_TileSize8_Abalone_TestInputs_ParallelBatch", Test_TileSize8_Abalone_TestInputs_ParallelBatch}, + {"Test_TileSize8_Airline_TestInputs_ParallelBatch", Test_TileSize8_Airline_TestInputs_ParallelBatch}, + {"Test_TileSize8_AirlineOHE_TestInputs_ParallelBatch", Test_TileSize8_AirlineOHE_TestInputs_ParallelBatch}, + {"Test_TileSize8_Covtype_TestInputs_ParallelBatch", Test_TileSize8_Covtype_TestInputs_ParallelBatch}, + {"Test_TileSize8_Letters_TestInputs_ParallelBatch", Test_TileSize8_Letters_TestInputs_ParallelBatch}, + {"Test_TileSize8_Epsilon_TestInputs_ParallelBatch", Test_TileSize8_Epsilon_TestInputs_ParallelBatch}, + {"Test_TileSize8_Higgs_TestInputs_ParallelBatch", Test_TileSize8_Higgs_TestInputs_ParallelBatch}, + {"Test_TileSize8_Year_TestInputs_ParallelBatch", Test_TileSize8_Year_TestInputs_ParallelBatch}, +#endif // OMP_SUPPORT + + // Pipelining + Unrolling tests + {"Test_RandomXGBoostJSONs_1Tree_BatchSize8_TileSize2_4Pipelined", Test_RandomXGBoostJSONs_1Tree_BatchSize8_TileSize2_4Pipelined}, + {"Test_RandomXGBoostJSONs_4Trees_BatchSize4_4Pipelined", Test_RandomXGBoostJSONs_4Trees_BatchSize4_4Pipelined}, + {"Test_TileSize3_Letters_2Pipelined_Int8Type", Test_TileSize3_Letters_2Pipelined_Int8Type}, + {"Test_TileSize4_Letters_3Pipelined_Int8Type", Test_TileSize4_Letters_3Pipelined_Int8Type}, + {"Test_TileSize8_Letters_5Pipelined_Int8Type", Test_TileSize8_Letters_5Pipelined_Int8Type}, + {"Test_SparseTileSize8_4Pipelined_Bosch", Test_SparseTileSize8_4Pipelined_Bosch}, + {"Test_TileSize8_Abalone_4Pipelined_TestInputs", Test_TileSize8_Abalone_4Pipelined_TestInputs}, + {"Test_TileSize8_CovType_4Pipelined_TestInputs", Test_TileSize8_CovType_4Pipelined_TestInputs}, + {"Test_SparseTileSize8_Pipeline4_Airline", Test_SparseTileSize8_Pipeline4_Airline}, + {"Test_SparseTileSize8_Pipelined4_AirlineOHE", Test_SparseTileSize8_Pipelined4_AirlineOHE}, + {"Test_SparseTileSize8_Pipelined_Year", Test_SparseTileSize8_Pipelined_Year}, + {"Test_SparseTileSize8_Pipelined_Higgs", Test_SparseTileSize8_Pipelined_Higgs}, + {"Test_SparseTileSize8_Pipelined_Epsilon", Test_SparseTileSize8_Pipelined_Epsilon}, + + {"Test_TileSize8_Abalone_4PipelinedTrees_TestInputs", Test_TileSize8_Abalone_4PipelinedTrees_TestInputs}, + {"Test_TileSize8_Abalone_PipelinedTreesPeeling_TestInputs", Test_TileSize8_Abalone_PipelinedTreesPeeling_TestInputs}, + + // Hybrid Tiling + {"Test_WalkPeeling_BalancedTree_TileSize2", Test_WalkPeeling_BalancedTree_TileSize2}, + {"Test_HybridTilingAndPeeling_RandomXGBoostJSONs_4Tree_FloatBatchSize4", Test_HybridTilingAndPeeling_RandomXGBoostJSONs_4Tree_FloatBatchSize4}, + {"Test_HybridTilingAndPeeling_RandomXGBoostJSONs_1Tree_FloatBatchSize4", Test_HybridTilingAndPeeling_RandomXGBoostJSONs_1Tree_FloatBatchSize4}, + {"Test_HybridTilingAndPeeling_RandomXGBoostJSONs_2Tree_FloatBatchSize4", Test_HybridTilingAndPeeling_RandomXGBoostJSONs_2Tree_FloatBatchSize4}, + {"Test_UniformAndHybridTilingAndPeeling_RandomXGBoostJSONs_2Tree_FloatBatchSize4", Test_UniformAndHybridTilingAndPeeling_RandomXGBoostJSONs_2Tree_FloatBatchSize4}, + {"Test_UniformAndHybridTilingAndPeeling_RandomXGBoostJSONs_4Tree_FloatBatchSize4", Test_UniformAndHybridTilingAndPeeling_RandomXGBoostJSONs_4Tree_FloatBatchSize4}, + {"Test_PeeledHybridProbabilisticTiling_TileSize8_Year", Test_PeeledHybridProbabilisticTiling_TileSize8_Year}, + {"Test_PeeledHybridProbabilisticTiling_TileSize8_Letters", Test_PeeledHybridProbabilisticTiling_TileSize8_Letters}, + {"Test_PeeledHybridProbabilisticTiling_TileSize8_Epsilon", Test_PeeledHybridProbabilisticTiling_TileSize8_Epsilon}, + {"Test_PeeledHybridProbabilisticTiling_TileSize8_Higgs", Test_PeeledHybridProbabilisticTiling_TileSize8_Higgs}, + {"Test_PeeledHybridProbabilisticTiling_TileSize8_AirlineOHE", Test_PeeledHybridProbabilisticTiling_TileSize8_AirlineOHE}, + {"Test_PeeledHybridProbabilisticTiling_TileSize8_Covtype", Test_PeeledHybridProbabilisticTiling_TileSize8_Covtype}, + {"Test_PeeledHybridProbabilisticTiling_TileSize8_Airline", Test_PeeledHybridProbabilisticTiling_TileSize8_Airline}, + {"Test_PeeledHybridProbabilisticTiling_TileSize8_Abalone", Test_PeeledHybridProbabilisticTiling_TileSize8_Abalone}, + + #ifdef TREEBEARD_GPU_SUPPORT + // GPU model buffer initialization tests (scalar) + {"Test_GPUModelInit_LeftHeavy_Scalar_DoubleInt", Test_GPUModelInit_LeftHeavy_Scalar_DoubleInt}, + {"Test_GPUModelInit_RightHeavy_Scalar_DoubleInt", Test_GPUModelInit_RightHeavy_Scalar_DoubleInt}, + {"Test_GPUModelInit_Balanced_Scalar_DoubleInt", Test_GPUModelInit_Balanced_Scalar_DoubleInt}, + {"Test_GPUModelInit_LeftAndRightHeavy_Scalar_DoubleInt", Test_GPUModelInit_LeftAndRightHeavy_Scalar_DoubleInt}, + {"Test_GPUModelInit_LeftHeavy_Scalar_FloatInt", Test_GPUModelInit_LeftHeavy_Scalar_FloatInt}, + {"Test_GPUModelInit_RightHeavy_Scalar_FloatInt", Test_GPUModelInit_RightHeavy_Scalar_FloatInt}, + {"Test_GPUModelInit_Balanced_Scalar_FloatInt", Test_GPUModelInit_Balanced_Scalar_FloatInt}, + {"Test_GPUModelInit_LeftAndRightHeavy_Scalar_FloatInt", Test_GPUModelInit_LeftAndRightHeavy_Scalar_FloatInt}, + {"Test_GPUModelInit_LeftHeavy_Scalar_FloatInt16", Test_GPUModelInit_LeftHeavy_Scalar_FloatInt16}, + {"Test_GPUModelInit_RightHeavy_Scalar_FloatInt16", Test_GPUModelInit_RightHeavy_Scalar_FloatInt16}, + {"Test_GPUModelInit_Balanced_Scalar_FloatInt16", Test_GPUModelInit_Balanced_Scalar_FloatInt16}, + {"Test_GPUModelInit_LeftAndRightHeavy_Scalar_FloatInt16", Test_GPUModelInit_LeftAndRightHeavy_Scalar_FloatInt16}, + + {"Test_GPUModelInit_LeftHeavy_Reorg_DoubleInt", Test_GPUModelInit_LeftHeavy_Reorg_DoubleInt}, + {"Test_GPUModelInit_RightHeavy_Reorg_DoubleInt", Test_GPUModelInit_RightHeavy_Reorg_DoubleInt}, + {"Test_GPUModelInit_Balanced_Reorg_DoubleInt", Test_GPUModelInit_Balanced_Reorg_DoubleInt}, + {"Test_GPUModelInit_LeftAndRightHeavy_Reorg_DoubleInt", Test_GPUModelInit_LeftAndRightHeavy_Reorg_DoubleInt}, + {"Test_GPUModelInit_LeftHeavy_Reorg_FloatInt", Test_GPUModelInit_LeftHeavy_Reorg_FloatInt}, + {"Test_GPUModelInit_RightHeavy_Reorg_FloatInt", Test_GPUModelInit_RightHeavy_Reorg_FloatInt}, + {"Test_GPUModelInit_Balanced_Reorg_FloatInt", Test_GPUModelInit_Balanced_Reorg_FloatInt}, + {"Test_GPUModelInit_LeftAndRightHeavy_Reorg_FloatInt", Test_GPUModelInit_LeftAndRightHeavy_Reorg_FloatInt}, + {"Test_GPUModelInit_LeftHeavy_Reorg_FloatInt16", Test_GPUModelInit_LeftHeavy_Reorg_FloatInt16}, + {"Test_GPUModelInit_RightHeavy_Reorg_FloatInt16", Test_GPUModelInit_RightHeavy_Reorg_FloatInt16}, + {"Test_GPUModelInit_Balanced_Reorg_FloatInt16", Test_GPUModelInit_Balanced_Reorg_FloatInt16}, + {"Test_GPUModelInit_LeftAndRightHeavy_Reorg_FloatInt16", Test_GPUModelInit_LeftAndRightHeavy_Reorg_FloatInt16}, + + // Basic Array Scalar GPU Codegen Tests + {"Test_GPUCodeGeneration_LeftHeavy_DoubleInt32_BatchSize32", Test_GPUCodeGeneration_LeftHeavy_DoubleInt32_BatchSize32}, + {"Test_GPUCodeGeneration_RightHeavy_DoubleInt32_BatchSize32", Test_GPUCodeGeneration_RightHeavy_DoubleInt32_BatchSize32}, + {"Test_GPUCodeGeneration_Balanced_DoubleInt32_BatchSize32", Test_GPUCodeGeneration_Balanced_DoubleInt32_BatchSize32}, + {"Test_GPUCodeGeneration_LeftAndRightHeavy_DoubleInt32_BatchSize32", Test_GPUCodeGeneration_LeftAndRightHeavy_DoubleInt32_BatchSize32}, + {"Test_GPUCodeGeneration_LeftHeavy_FloatInt16_BatchSize32", Test_GPUCodeGeneration_LeftHeavy_FloatInt16_BatchSize32}, + {"Test_GPUCodeGeneration_RightHeavy_FloatInt16_BatchSize32", Test_GPUCodeGeneration_RightHeavy_FloatInt16_BatchSize32}, + {"Test_GPUCodeGeneration_Balanced_FloatInt16_BatchSize32", Test_GPUCodeGeneration_Balanced_FloatInt16_BatchSize32}, + {"Test_GPUCodeGeneration_LeftAndRightHeavy_FloatInt16_BatchSize32", Test_GPUCodeGeneration_LeftAndRightHeavy_FloatInt16_BatchSize32}, + + // Basic scalar sparse GPU codegen tests + {"Test_SparseGPUCodeGeneration_LeftHeavy_DoubleInt32_BatchSize32", Test_SparseGPUCodeGeneration_LeftHeavy_DoubleInt32_BatchSize32}, + {"Test_SparseGPUCodeGeneration_RightHeavy_DoubleInt32_BatchSize32", Test_SparseGPUCodeGeneration_RightHeavy_DoubleInt32_BatchSize32}, + {"Test_SparseGPUCodeGeneration_Balanced_DoubleInt32_BatchSize32", Test_SparseGPUCodeGeneration_Balanced_DoubleInt32_BatchSize32}, + {"Test_SparseGPUCodeGeneration_LeftAndRightHeavy_DoubleInt32_BatchSize32", Test_SparseGPUCodeGeneration_LeftAndRightHeavy_DoubleInt32_BatchSize32}, + {"Test_SparseGPUCodeGeneration_LeftHeavy_FloatInt16_ChI16_BatchSize32", Test_SparseGPUCodeGeneration_LeftHeavy_FloatInt16_ChI16_BatchSize32}, + {"Test_SparseGPUCodeGeneration_RightHeavy_FloatInt16_ChI16_BatchSize32", Test_SparseGPUCodeGeneration_RightHeavy_FloatInt16_ChI16_BatchSize32}, + {"Test_SparseGPUCodeGeneration_Balanced_FloatInt16_ChI16_BatchSize32", Test_SparseGPUCodeGeneration_Balanced_FloatInt16_ChI16_BatchSize32}, + {"Test_SparseGPUCodeGeneration_LeftAndRightHeavy_FloatInt16_ChI16_BatchSize32", Test_SparseGPUCodeGeneration_LeftAndRightHeavy_FloatInt16_ChI16_BatchSize32}, + + // Basic reorg forest tests + {"Test_ReorgGPUCodeGeneration_LeftHeavy_DoubleInt32_BatchSize32", Test_ReorgGPUCodeGeneration_LeftHeavy_DoubleInt32_BatchSize32}, + {"Test_ReorgGPUCodeGeneration_RightHeavy_DoubleInt32_BatchSize32", Test_ReorgGPUCodeGeneration_RightHeavy_DoubleInt32_BatchSize32}, + {"Test_ReorgGPUCodeGeneration_Balanced_DoubleInt32_BatchSize32", Test_ReorgGPUCodeGeneration_Balanced_DoubleInt32_BatchSize32}, + {"Test_ReorgGPUCodeGeneration_LeftAndRightHeavy_DoubleInt32_BatchSize32", Test_ReorgGPUCodeGeneration_LeftAndRightHeavy_DoubleInt32_BatchSize32}, + {"Test_ReorgGPUCodeGeneration_LeftHeavy_FloatInt16_BatchSize32", Test_ReorgGPUCodeGeneration_LeftHeavy_FloatInt16_BatchSize32}, + {"Test_ReorgGPUCodeGeneration_RightHeavy_FloatInt16_BatchSize32", Test_ReorgGPUCodeGeneration_RightHeavy_FloatInt16_BatchSize32}, + {"Test_ReorgGPUCodeGeneration_LeftAndRightHeavy_FloatInt16_BatchSize32", Test_ReorgGPUCodeGeneration_LeftAndRightHeavy_FloatInt16_BatchSize32}, + {"Test_ReorgGPUCodeGeneration_LeftRightAndBalanced_FloatInt16_BatchSize32", Test_ReorgGPUCodeGeneration_LeftRightAndBalanced_FloatInt16_BatchSize32}, + + // Basic GPU caching tests + {"Test_SimpleSharedMem_LeftRightAndBalanced", Test_SimpleSharedMem_LeftRightAndBalanced}, + {"Test_SimpleSharedMem_LeftHeavy", Test_SimpleSharedMem_LeftHeavy}, + {"Test_SimpleSharedMem_LeftHeavy_F32I16", Test_SimpleSharedMem_LeftHeavy_F32I16}, + {"Test_SimpleSharedMem_LeftRightAndBalanced_F32I16", Test_SimpleSharedMem_LeftRightAndBalanced_F32I16}, + + {"Test_SimpleSharedMem_LeftHeavy_ReorgRep", Test_SimpleSharedMem_LeftHeavy_ReorgRep}, + {"Test_SimpleSharedMem_LeftRightAndBalanced_Reorg", Test_SimpleSharedMem_LeftRightAndBalanced_Reorg}, + {"Test_SimpleSharedMem_LeftHeavy_ReorgRep_F32I16", Test_SimpleSharedMem_LeftHeavy_ReorgRep_F32I16}, + {"Test_SimpleSharedMem_LeftRightAndBalanced_Reorg_F32I16", Test_SimpleSharedMem_LeftRightAndBalanced_Reorg_F32I16}, + + {"Test_SimpleSharedMem_LeftHeavy_SparseRep", Test_SimpleSharedMem_LeftHeavy_SparseRep}, + {"Test_SimpleSharedMem_LeftRightAndBalanced_SparseRep", Test_SimpleSharedMem_LeftRightAndBalanced_SparseRep}, + {"Test_SimpleSharedMem_LeftHeavy_SparseRep_F32I16", Test_SimpleSharedMem_LeftHeavy_SparseRep_F32I16}, + {"Test_SimpleSharedMem_LeftRightAndBalanced_SparseRep_F32I16", Test_SimpleSharedMem_LeftRightAndBalanced_SparseRep_F32I16}, + {"Test_InputSharedMem_LeftHeavy", Test_InputSharedMem_LeftHeavy}, + {"Test_InputSharedMem_RightHeavy", Test_InputSharedMem_RightHeavy}, + {"Test_InputSharedMem_LeftRightAndBalanced", Test_InputSharedMem_LeftRightAndBalanced}, + + // Simple GPU Tiling tests + {"Test_TiledSparseGPU_LeftHeavy_DblI32_B32_TSz2", Test_TiledSparseGPU_LeftHeavy_DblI32_B32_TSz2}, + {"Test_TiledSparseGPU_RightHeavy_DblI32_B32_TSz2", Test_TiledSparseGPU_RightHeavy_DblI32_B32_TSz2}, + {"Test_TiledSparseGPU_Balanced_DblI32_B32_TSz2", Test_TiledSparseGPU_Balanced_DblI32_B32_TSz2}, + {"Test_TiledSparseGPU_LeftAndRightHeavy_DblI32_B32_TSz2", Test_TiledSparseGPU_LeftAndRightHeavy_DblI32_B32_TSz2}, + {"Test_TiledSparseGPU_LeftHeavy_FltI16_B32_TSz2", Test_TiledSparseGPU_LeftHeavy_FltI16_B32_TSz2}, + {"Test_TiledSparseGPU_RightHeavy_FltI16_B32_TSz2", Test_TiledSparseGPU_RightHeavy_FltI16_B32_TSz2}, + {"Test_TiledSparseGPU_Balanced_FltI16_B32_TSz2", Test_TiledSparseGPU_Balanced_FltI16_B32_TSz2}, + {"Test_TiledSparseGPU_LeftAndRightHeavy_FltI16_B32_TSz2", Test_TiledSparseGPU_LeftAndRightHeavy_FltI16_B32_TSz2}, + + {"Test_TiledArrayGPU_LeftHeavy_DblI32_B32_TSz2", Test_TiledArrayGPU_LeftHeavy_DblI32_B32_TSz2}, + {"Test_TiledArrayGPU_RightHeavy_DblI32_B32_TSz2", Test_TiledArrayGPU_RightHeavy_DblI32_B32_TSz2}, + {"Test_TiledArrayGPU_Balanced_DblI32_B32_TSz2", Test_TiledArrayGPU_Balanced_DblI32_B32_TSz2}, + {"Test_TiledArrayGPU_LeftAndRightHeavy_DblI32_B32_TSz2", Test_TiledArrayGPU_LeftAndRightHeavy_DblI32_B32_TSz2}, + {"Test_TiledArrayGPU_LeftHeavy_FltI16_B32_TSz2", Test_TiledArrayGPU_LeftHeavy_FltI16_B32_TSz2}, + {"Test_TiledArrayGPU_RightHeavy_FltI16_B32_TSz2", Test_TiledArrayGPU_RightHeavy_FltI16_B32_TSz2}, + {"Test_TiledArrayGPU_Balanced_FltI16_B32_TSz2", Test_TiledArrayGPU_Balanced_FltI16_B32_TSz2}, + {"Test_TiledArrayGPU_LeftAndRightHeavy_FltI16_B32_TSz2", Test_TiledArrayGPU_LeftAndRightHeavy_FltI16_B32_TSz2}, + + // Tiling + Caching + {"Test_TiledCachedArrayGPU_LeftHeavy_DblI32_B32_TSz2", Test_TiledCachedArrayGPU_LeftHeavy_DblI32_B32_TSz2}, + {"Test_TiledCachedArrayGPU_RightHeavy_DblI32_B32_TSz2", Test_TiledCachedArrayGPU_RightHeavy_DblI32_B32_TSz2}, + {"Test_TiledCachedArrayGPU_Balanced_DblI32_B32_TSz2", Test_TiledCachedArrayGPU_Balanced_DblI32_B32_TSz2}, + {"Test_TiledCachedArrayGPU_LeftAndRightHeavy_DblI32_B32_TSz2", Test_TiledCachedArrayGPU_LeftAndRightHeavy_DblI32_B32_TSz2}, + {"Test_TiledCachedArrayGPU_LeftRightAndBalanced_DblI32_B32_TSz2", Test_TiledCachedArrayGPU_LeftRightAndBalanced_DblI32_B32_TSz2}, + {"Test_TiledCachedArrayGPU_LeftHeavy_FltI16_B32_TSz2", Test_TiledCachedArrayGPU_LeftHeavy_FltI16_B32_TSz2}, + {"Test_TiledCachedArrayGPU_RightHeavy_FltI16_B32_TSz2", Test_TiledCachedArrayGPU_RightHeavy_FltI16_B32_TSz2}, + {"Test_TiledCachedArrayGPU_Balanced_FltI16_B32_TSz2", Test_TiledCachedArrayGPU_Balanced_FltI16_B32_TSz2}, + {"Test_TiledCachedArrayGPU_LeftAndRightHeavy_FltI16_B32_TSz2", Test_TiledCachedArrayGPU_LeftAndRightHeavy_FltI16_B32_TSz2}, + {"Test_TiledCachedArrayGPU_LeftRightAndBalanced_FltI16_B32_TSz2", Test_TiledCachedArrayGPU_LeftRightAndBalanced_FltI16_B32_TSz2}, + + {"Test_TiledCachedSparseGPU_LeftHeavy_DblI32_B32_TSz2", Test_TiledCachedSparseGPU_LeftHeavy_DblI32_B32_TSz2}, + {"Test_TiledCachedSparseGPU_RightHeavy_DblI32_B32_TSz2", Test_TiledCachedSparseGPU_RightHeavy_DblI32_B32_TSz2}, + {"Test_TiledCachedSparseGPU_Balanced_DblI32_B32_TSz2", Test_TiledCachedSparseGPU_Balanced_DblI32_B32_TSz2}, + {"Test_TiledCachedSparseGPU_LeftAndRightHeavy_DblI32_B32_TSz2", Test_TiledCachedSparseGPU_LeftAndRightHeavy_DblI32_B32_TSz2}, + {"Test_TiledCachedSparseGPU_LeftHeavy_FltI16_B32_TSz2", Test_TiledCachedSparseGPU_LeftHeavy_FltI16_B32_TSz2}, + {"Test_TiledCachedSparseGPU_RightHeavy_FltI16_B32_TSz2", Test_TiledCachedSparseGPU_RightHeavy_FltI16_B32_TSz2}, + {"Test_TiledCachedSparseGPU_Balanced_FltI16_B32_TSz2", Test_TiledCachedSparseGPU_Balanced_FltI16_B32_TSz2}, + {"Test_TiledCachedSparseGPU_LeftAndRightHeavy_FltI16_B32_TSz2", Test_TiledCachedSparseGPU_LeftAndRightHeavy_FltI16_B32_TSz2}, + {"Test_TiledCachedSparseGPU_LeftRightAndBalanced_DblI32_B32_TSz2", Test_TiledCachedSparseGPU_LeftRightAndBalanced_DblI32_B32_TSz2}, + {"Test_TiledCachedSparseGPU_LeftRightAndBalanced_FltI16_B32_TSz2", Test_TiledCachedSparseGPU_LeftRightAndBalanced_FltI16_B32_TSz2}, + + // GPU Synthetic XGB tests -- scalar + {"Test_GPU_1TreeXGB_Array_Scalar", Test_GPU_1TreeXGB_Array_Scalar}, + {"Test_GPU_2TreeXGB_Array_Scalar", Test_GPU_2TreeXGB_Array_Scalar}, + {"Test_GPU_4TreeXGB_Array_Scalar", Test_GPU_4TreeXGB_Array_Scalar}, + {"Test_GPU_1TreeXGB_Array_Scalar_f32i16", Test_GPU_1TreeXGB_Array_Scalar_f32i16}, + {"Test_GPU_2TreeXGB_Array_Scalar_f32i16", Test_GPU_2TreeXGB_Array_Scalar_f32i16}, + {"Test_GPU_4TreeXGB_Array_Scalar_f32i16", Test_GPU_4TreeXGB_Array_Scalar_f32i16}, + {"Test_GPU_1TreeXGB_Sparse_Scalar", Test_GPU_1TreeXGB_Sparse_Scalar}, + {"Test_GPU_2TreeXGB_Sparse_Scalar", Test_GPU_2TreeXGB_Sparse_Scalar}, + {"Test_GPU_4TreeXGB_Sparse_Scalar", Test_GPU_4TreeXGB_Sparse_Scalar}, + {"Test_GPU_1TreeXGB_Sparse_Scalar_f32i16", Test_GPU_1TreeXGB_Sparse_Scalar_f32i16}, + {"Test_GPU_2TreeXGB_Sparse_Scalar_f32i16", Test_GPU_2TreeXGB_Sparse_Scalar_f32i16}, + {"Test_GPU_4TreeXGB_Sparse_Scalar_f32i16", Test_GPU_4TreeXGB_Sparse_Scalar_f32i16}, + {"Test_GPU_1TreeXGB_Reorg_Scalar", Test_GPU_1TreeXGB_Reorg_Scalar}, + {"Test_GPU_2TreeXGB_Reorg_Scalar", Test_GPU_2TreeXGB_Reorg_Scalar}, + {"Test_GPU_4TreeXGB_Reorg_Scalar", Test_GPU_4TreeXGB_Reorg_Scalar}, + {"Test_GPU_1TreeXGB_Reorg_Scalar_f32i16", Test_GPU_1TreeXGB_Reorg_Scalar_f32i16}, + {"Test_GPU_2TreeXGB_Reorg_Scalar_f32i16", Test_GPU_2TreeXGB_Reorg_Scalar_f32i16}, + {"Test_GPU_4TreeXGB_Reorg_Scalar_f32i16", Test_GPU_4TreeXGB_Reorg_Scalar_f32i16}, + + // GPU Synthetic XGB tests -- tile4 + {"Test_GPU_1TreeXGB_Sparse_Tile4", Test_GPU_1TreeXGB_Sparse_Tile4}, + {"Test_GPU_2TreeXGB_Sparse_Tile4", Test_GPU_2TreeXGB_Sparse_Tile4}, + {"Test_GPU_4TreeXGB_Sparse_Tile4", Test_GPU_4TreeXGB_Sparse_Tile4}, + {"Test_GPU_1TreeXGB_Sparse_Tile4_f32i16", Test_GPU_1TreeXGB_Sparse_Tile4_f32i16}, + {"Test_GPU_2TreeXGB_Sparse_Tile4_f32i16", Test_GPU_2TreeXGB_Sparse_Tile4_f32i16}, + {"Test_GPU_4TreeXGB_Sparse_Tile4_f32i16", Test_GPU_4TreeXGB_Sparse_Tile4_f32i16}, + {"Test_GPU_1TreeXGB_Array_Tile4", Test_GPU_1TreeXGB_Array_Tile4}, + {"Test_GPU_2TreeXGB_Array_Tile4", Test_GPU_2TreeXGB_Array_Tile4}, + {"Test_GPU_4TreeXGB_Array_Tile4", Test_GPU_4TreeXGB_Array_Tile4}, + {"Test_GPU_1TreeXGB_Array_Tile4_f32i16", Test_GPU_1TreeXGB_Array_Tile4_f32i16}, + {"Test_GPU_2TreeXGB_Array_Tile4_f32i16", Test_GPU_2TreeXGB_Array_Tile4_f32i16}, + {"Test_GPU_4TreeXGB_Array_Tile4_f32i16", Test_GPU_4TreeXGB_Array_Tile4_f32i16}, + + // GPU Synthetic XGB tests -- Shared Forest -- Scalar + {"Test_GPU_SharedForest_1TreeXGB_Reorg_Scalar", Test_GPU_SharedForest_1TreeXGB_Reorg_Scalar}, + {"Test_GPU_SharedForest_2TreeXGB_Reorg_Scalar", Test_GPU_SharedForest_2TreeXGB_Reorg_Scalar}, + // {"Test_GPU_SharedForest_4TreeXGB_Reorg_Scalar", Test_GPU_SharedForest_4TreeXGB_Reorg_Scalar}, // Commented out + {"Test_GPU_SharedForest_1TreeXGB_Reorg_Scalar_f32i16", Test_GPU_SharedForest_1TreeXGB_Reorg_Scalar_f32i16}, + {"Test_GPU_SharedForest_2TreeXGB_Reorg_Scalar_f32i16", Test_GPU_SharedForest_2TreeXGB_Reorg_Scalar_f32i16}, + {"Test_GPU_SharedForest_4TreeXGB_Reorg_Scalar_f32i16", Test_GPU_SharedForest_4TreeXGB_Reorg_Scalar_f32i16}, + + {"Test_GPU_SharedForest_1TreeXGB_Array_Scalar", Test_GPU_SharedForest_1TreeXGB_Array_Scalar}, + // {"Test_GPU_SharedForest_2TreeXGB_Array_Scalar", Test_GPU_SharedForest_2TreeXGB_Array_Scalar}, // Commented out + // {"Test_GPU_SharedForest_4TreeXGB_Array_Scalar", Test_GPU_SharedForest_4TreeXGB_Array_Scalar}, // Commented out + {"Test_GPU_SharedForest_1TreeXGB_Array_Scalar_f32i16", Test_GPU_SharedForest_1TreeXGB_Array_Scalar_f32i16}, + {"Test_GPU_SharedForest_2TreeXGB_Array_Scalar_f32i16", Test_GPU_SharedForest_2TreeXGB_Array_Scalar_f32i16}, + // {"Test_GPU_SharedForest_4TreeXGB_Array_Scalar_f32i16", Test_GPU_SharedForest_4TreeXGB_Array_Scalar_f32i16}, // Commented out + + {"Test_GPU_SharedForest_1TreeXGB_Sparse_Scalar", Test_GPU_SharedForest_1TreeXGB_Sparse_Scalar}, + {"Test_GPU_SharedForest_2TreeXGB_Sparse_Scalar", Test_GPU_SharedForest_2TreeXGB_Sparse_Scalar}, + {"Test_GPU_SharedForest_4TreeXGB_Sparse_Scalar", Test_GPU_SharedForest_4TreeXGB_Sparse_Scalar}, + {"Test_GPU_SharedForest_1TreeXGB_Sparse_Scalar_f32i16", Test_GPU_SharedForest_1TreeXGB_Sparse_Scalar_f32i16}, + {"Test_GPU_SharedForest_2TreeXGB_Sparse_Scalar_f32i16", Test_GPU_SharedForest_2TreeXGB_Sparse_Scalar_f32i16}, + {"Test_GPU_SharedForest_4TreeXGB_Sparse_Scalar_f32i16", Test_GPU_SharedForest_4TreeXGB_Sparse_Scalar_f32i16}, + + // GPU Synthetic XGB tests -- Cache Partial Forest -- Scalar + // NOTE: These schedules are different than Tahoe's partial shared forest schedule + {"Test_GPU_CachePartialForest1Tree_2TreeXGB_Sparse_Scalar", Test_GPU_CachePartialForest1Tree_2TreeXGB_Sparse_Scalar}, + {"Test_GPU_CachePartialForest2Trees_4TreeXGB_Sparse_Scalar", Test_GPU_CachePartialForest2Trees_4TreeXGB_Sparse_Scalar}, + {"Test_GPU_CachePartialForest2Trees_2TreeXGB_Sparse_Scalar_f32i16", Test_GPU_CachePartialForest2Trees_2TreeXGB_Sparse_Scalar_f32i16}, + {"Test_GPU_CachePartialForest2Trees_4TreeXGB_Sparse_Scalar_f32i16", Test_GPU_CachePartialForest2Trees_4TreeXGB_Sparse_Scalar_f32i16}, + + {"Test_GPU_CachePartialForest1Tree_2TreeXGB_Reorg_Scalar", Test_GPU_CachePartialForest1Tree_2TreeXGB_Reorg_Scalar}, + {"Test_GPU_CachePartialForest2Trees_4TreeXGB_Reorg_Scalar", Test_GPU_CachePartialForest2Trees_4TreeXGB_Reorg_Scalar}, + {"Test_GPU_CachePartialForest2Trees_2TreeXGB_Reorg_Scalar_f32i16", Test_GPU_CachePartialForest2Trees_2TreeXGB_Reorg_Scalar_f32i16}, + {"Test_GPU_CachePartialForest2Trees_4TreeXGB_Reorg_Scalar_f32i16", Test_GPU_CachePartialForest2Trees_4TreeXGB_Reorg_Scalar_f32i16}, + + // Adding the new test entries + {"Test_GPU_CachePartialForest1Tree_2TreeXGB_Array_Scalar", Test_GPU_CachePartialForest1Tree_2TreeXGB_Array_Scalar}, + {"Test_GPU_CachePartialForest1Tree_4TreeXGB_Array_Scalar", Test_GPU_CachePartialForest1Tree_4TreeXGB_Array_Scalar}, + {"Test_GPU_CachePartialForest2Trees_2TreeXGB_Array_Scalar_f32i16", Test_GPU_CachePartialForest2Trees_2TreeXGB_Array_Scalar_f32i16}, + {"Test_GPU_CachePartialForest2Trees_4TreeXGB_Array_Scalar_f32i16", Test_GPU_CachePartialForest2Trees_4TreeXGB_Array_Scalar_f32i16}, + {"Test_ScalarSparseGPU_TwiceLeftRightBalanced_TahoeShdInpMultiRow_FltI16_B32", Test_ScalarSparseGPU_TwiceLeftRightBalanced_TahoeShdInpMultiRow_FltI16_B32}, + {"Test_ScalarSparseGPU_LeftRightAndBalanced_TahoeShdInpMultiRow_FltI16_B32", Test_ScalarSparseGPU_LeftRightAndBalanced_TahoeShdInpMultiRow_FltI16_B32}, + {"Test_ScalarSparseGPU_LeftRightAndBalanced_TahoeShdInp_FltI16_B32", Test_ScalarSparseGPU_LeftRightAndBalanced_TahoeShdInp_FltI16_B32}, + {"Test_ScalarSparseGPU_TwiceLeftRightBalanced_IterShdPartialForest_FltI16_B32", Test_ScalarSparseGPU_TwiceLeftRightBalanced_IterShdPartialForest_FltI16_B32}, + {"Test_GPU_TahoeSharedDataStrategy_2TreeXGB_Sparse_Scalar", Test_GPU_TahoeSharedDataStrategy_2TreeXGB_Sparse_Scalar}, + {"Test_GPU_TahoeSharedDataStrategy_4TreeXGB_Sparse_Scalar", Test_GPU_TahoeSharedDataStrategy_4TreeXGB_Sparse_Scalar}, + {"Test_GPU_TahoeSharedDataStrategy_2TreeXGB_Sparse_Scalar_f32i16", Test_GPU_TahoeSharedDataStrategy_2TreeXGB_Sparse_Scalar_f32i16}, + {"Test_GPU_TahoeSharedDataStrategy_4TreeXGB_Sparse_Scalar_f32i16", Test_GPU_TahoeSharedDataStrategy_4TreeXGB_Sparse_Scalar_f32i16}, + {"Test_GPU_TahoeSharedDataStrategy_2TreeXGB_Array_Scalar", Test_GPU_TahoeSharedDataStrategy_2TreeXGB_Array_Scalar}, + {"Test_GPU_TahoeSharedDataStrategy_4TreeXGB_Array_Scalar", Test_GPU_TahoeSharedDataStrategy_4TreeXGB_Array_Scalar}, + {"Test_GPU_TahoeSharedDataStrategy_2TreeXGB_Array_Scalar_f32i16", Test_GPU_TahoeSharedDataStrategy_2TreeXGB_Array_Scalar_f32i16}, + {"Test_GPU_TahoeSharedDataStrategy_4TreeXGB_Array_Scalar_f32i16", Test_GPU_TahoeSharedDataStrategy_4TreeXGB_Array_Scalar_f32i16}, + {"Test_GPU_TahoeSharedDataStrategy_2TreeXGB_Reorg_Scalar", Test_GPU_TahoeSharedDataStrategy_2TreeXGB_Reorg_Scalar}, + {"Test_GPU_TahoeSharedDataStrategy_4TreeXGB_Reorg_Scalar", Test_GPU_TahoeSharedDataStrategy_4TreeXGB_Reorg_Scalar}, + {"Test_GPU_TahoeSharedDataStrategy_2TreeXGB_Reorg_Scalar_f32i16", Test_GPU_TahoeSharedDataStrategy_2TreeXGB_Reorg_Scalar_f32i16}, + {"Test_GPU_TahoeSharedDataStrategy_4TreeXGB_Reorg_Scalar_f32i16", Test_GPU_TahoeSharedDataStrategy_4TreeXGB_Reorg_Scalar_f32i16}, + {"Test_GPU_iterativeCachedPartialForestStrategy_4TreeXGB_Array_Scalar_f32i16", Test_GPU_iterativeCachedPartialForestStrategy_4TreeXGB_Array_Scalar_f32i16}, + {"Test_GPU_iterativeCachedPartialForestStrategy_4TreeXGB_Sparse_Scalar", Test_GPU_iterativeCachedPartialForestStrategy_4TreeXGB_Sparse_Scalar}, + {"Test_GPU_iterativeCachedPartialForestStrategy_4TreeXGB_Sparse_Scalar_f32i16", Test_GPU_iterativeCachedPartialForestStrategy_4TreeXGB_Sparse_Scalar_f32i16}, + {"Test_GPU_iterativeCachedPartialForestStrategy_4TreeXGB_Reorg_Scalar", Test_GPU_iterativeCachedPartialForestStrategy_4TreeXGB_Reorg_Scalar}, + {"Test_GPU_iterativeCachedPartialForestStrategy_4TreeXGB_Reorg_Scalar_f32i16", Test_GPU_iterativeCachedPartialForestStrategy_4TreeXGB_Reorg_Scalar_f32i16}, + // GPU Tree parallelization tests - Tile size 4 + {"Test_GPU_iterativeCachedPartialForestStrategy_4TreeXGB_Sparse_Tile4", Test_GPU_iterativeCachedPartialForestStrategy_4TreeXGB_Sparse_Tile4}, + {"Test_GPU_iterativeCachedPartialForestStrategy_4TreeXGB_Sparse_Tile4_f32i16", Test_GPU_iterativeCachedPartialForestStrategy_4TreeXGB_Sparse_Tile4_f32i16}, + {"Test_ScalarSparseGPU_TwiceLeftRightBalanced_iterCachedPartialForest_NoCache_SharedReduce_FltI16_B64", Test_ScalarSparseGPU_TwiceLeftRightBalanced_iterCachedPartialForest_NoCache_SharedReduce_FltI16_B64}, + {"Test_ScalarSparseGPU_TwiceLeftRightBalanced_iterCachedPartialForest_NoCache_SpecializedTreeLoop_FltI16_B64", Test_ScalarSparseGPU_TwiceLeftRightBalanced_iterCachedPartialForest_NoCache_SpecializedTreeLoop_FltI16_B64}, + // Tree Parallelization Multi-class tests + {"Test_GPUCodeGeneration_Covtype_SparseRep_f32i16_B32_iterativeCachedPartialForestStrategy_NoCache", Test_GPUCodeGeneration_Covtype_SparseRep_f32i16_B32_iterativeCachedPartialForestStrategy_NoCache}, + {"Test_ScalarSparseGPU_TwiceLeftRightBalanced_AutoScheduleCachedTrees", Test_ScalarSparseGPU_TwiceLeftRightBalanced_AutoScheduleCachedTrees}, + {"Test_ScalarSparseGPU_TwiceLeftRightBalanced_AutoScheduleCachedRows", Test_ScalarSparseGPU_TwiceLeftRightBalanced_AutoScheduleCachedRows}, + {"Test_ScalarSparseGPU_TwiceLeftRightBalanced_AutoScheduleBasic", Test_ScalarSparseGPU_TwiceLeftRightBalanced_AutoScheduleBasic}, + {"Test_GPUCodeGeneration_Covtype_SparseRep_f32i16_B32_iterativeCachedPartialForestStrategy_NoCache_SharedReduce", Test_GPUCodeGeneration_Covtype_SparseRep_f32i16_B32_iterativeCachedPartialForestStrategy_NoCache_SharedReduce} +#endif // TREEBEARD_GPU_SUPPORT + + //————————————— Add more missing tests from the TEST_LIST_ENTRY here ——————————————————————————// +}; + + #define RUN_ALL_TESTS #ifdef RUN_ALL_TESTS @@ -2964,6 +3528,36 @@ void RunTestsImpl(TestDescriptor *testsToRun, size_t numberOfTests) { << std::endl; } + +// Function to create a TestDescriptor dynamically +#define RED "\033[31m" +#define RESET "\033[0m" + +TestDescriptor createTestDescriptor(const std::string &testName) { + auto it = testFuncMap.find(testName); + if (it != testFuncMap.end()) { + // Test found in the map, return the TestDescriptor + return {testName, it->second}; + } else { + // Print the error message in red and abort the program + std::cerr << RED << "Error: "<< RESET <<"Test not found: " + testName << std::endl; + std::abort(); // Stops the program immediately + } +} + +void RunIndividualTests(const std::string &individualTestName) { + // Create the TestDescriptor dynamically + TestDescriptor testDesc = createTestDescriptor(individualTestName); + + // You can now use the test descriptor to run the test + TestArgs_t args; + bool pass = RunTest(testDesc, args, 1); + std::cout << underline + << (pass ? boldGreen + "\nTest Passed." + : boldRed + "\nTest Failed.") + << reset; +} + void RunTests() { RunTestsImpl(testList, numTests); } void RunSanityTests() { RunTestsImpl(sanityTestList, numSanityTests); } diff --git a/src/test/TestUtilsCommon.h b/src/test/TestUtilsCommon.h index 6680541..83c4326 100644 --- a/src/test/TestUtilsCommon.h +++ b/src/test/TestUtilsCommon.h @@ -13,6 +13,7 @@ #include "GPUExecutionHelper.h" #include "GPUSupportUtils.h" + namespace mlir { class MLIRContext; } @@ -152,6 +153,7 @@ void RunSanityTests(); void RunXGBoostBenchmarks(); void RunXGBoostParallelBenchmarks(); void RunXGBoostGPUBenchmarks(); +void RunIndividualTests(const std::string &individualTestName); // ===---------------------------------------------=== // // Configuration for tests