Need documentation on implementation

[kallisti5]

As the basic FPGA logic has been written, we should document current FPGA sizing and pin connections.

[ianhan]

Pin connections are based on platform and decided based on the top entity
wire mapping to the tool chain device configuration. This core is portable
to any reasonably sized FPGA.

It may serve you better to get a few FPGA projects under your belt before
digging into this one.
On Oct 21, 2014 4:40 PM, "Alexander von Gluck IV" notifications@github.com
wrote:

As the basic FPGA logic has been written, we should document current FPGA
sizing and pin connections.

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Reply to this email directly or view it on GitHub
#5.

[asicguy]

Thanks for the interest guys. This code is based on the original #9 ASICs, but it is rewritten code. It has been used in a number of FPGA and also an ASIC implementation.
I had hoped to have more time to work on it. I still need to upload the rest of the tests. My goal is to move it to open source simulators, but not much time. I would recommend Verilator as it handles System Verilog and Verilog (some of the TB is in SV).

Glad you guys find it interesting. Some drivers and getting it to work on an SOC platform would be a great start.

-Frank

From: Alexander von Gluck IV <notifications@github.commailto:notifications@github.com>
Reply-To: asicguy/gplgpu <reply@reply.github.commailto:reply@reply.github.com>
Date: Tuesday, October 21, 2014 at 7:40 PM
To: asicguy/gplgpu <gplgpu@noreply.github.commailto:gplgpu@noreply.github.com>
Subject: [gplgpu] Need documentation on implementation (#5)

As the basic FPGA logic has been written, we should document current FPGA sizing and pin connections.

—
Reply to this email directly or view it on GitHubhttps://github.com//issues/5.

[kallisti5]

Here is an example using verilator:

kallisti5@eris hdl :) $ verilator -Wno-CASEX -Wno-CASEINCOMPLETE -cc -I/home/kallisti5/Code/gplgpu/hdl/include clk_gen/clk_gen.v
kallisti5@eris hdl :) $ cd obj_dir/
kallisti5@eris obj_dir :) $ ls
Vclk_gen_classes.mk  Vclk_gen.h   Vclk_gen__Syms.cpp  Vclk_gen__ver.d
Vclk_gen.cpp         Vclk_gen.mk  Vclk_gen__Syms.h    Vclk_gen__verFiles.dat
kallisti5@eris obj_dir :) $ make -f Vclk_gen.mk
/usr/bin/perl /usr/local/share/verilator/bin/verilator_includer Vclk_gen.cpp > Vclk_gen__ALLcls.cpp
g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_TRACE=0 -DVM_COVERAGE=0 -Wno-char-subscripts -Wno-parentheses-equality -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable       -c -o Vclk_gen__ALLcls.o Vclk_gen__ALLcls.cpp
/usr/bin/perl /usr/local/share/verilator/bin/verilator_includer Vclk_gen__Syms.cpp > Vclk_gen__ALLsup.cpp
g++  -I.  -MMD -I/usr/local/share/verilator/include -I/usr/local/share/verilator/include/vltstd -DVL_PRINTF=printf -DVM_TRACE=0 -DVM_COVERAGE=0 -Wno-char-subscripts -Wno-parentheses-equality -Wno-sign-compare -Wno-uninitialized -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable       -c -o Vclk_gen__ALLsup.o Vclk_gen__ALLsup.cpp
      Archiving Vclk_gen__ALL.a ...
ar r Vclk_gen__ALL.a Vclk_gen__ALLcls.o Vclk_gen__ALLsup.o
ar: creating Vclk_gen__ALL.a
ranlib Vclk_gen__ALL.a

Definitely having more luck with the open source stuff vs Altera's software... but I get lost in GUI's easily :P

[kallisti5]

I may not be able to help with the verilog code at this time, but I might be able to clean up the build infrastructure. What would really help is some documentation on what verilog code at what location is required for a basic card implementation. I see some Altera project files, but they only cover a small subset of the verilog code

[kallisti5]

Food for thought, targeting a small demo board for now may be helpful in developing on this code.

For example:

EP4CE6E22C8N (6k LE)
http://www.ebay.com/itm/EP4CE6-EP4CE6E22C8N-FPGA-ALTERA-Cyclone-IV-Development-Evaluation-Board-Core-Kit-/251194059567?pt=LH_DefaultDomain_0&hash=item3a7c552b2f

http://www.ebay.com/itm/EP4CE6-EP4CE6E22C8N-ALTERA-FPGA-Cyclone-IV-Development-Evaluation-Board-Core-Kit-/231074176951?pt=LH_DefaultDomain_0&hash=item35cd181fb7

or

EP4CE10F17C8N (10k LE)

http://www.ebay.com/itm/ALTERA-FPGA-EP4CE10F17C8N-EP4CE10-Cyclone-IV-Development-Evaluation-Core-Board-/261181065297?pt=LH_DefaultDomain_0&hash=item3ccf9ac851

Anyone have any numbers on required logic elements?

That way base boards could be easily developed around the FPGA without the worry of soldering the tiny FPGA pin pitch :-)

[asicguy]

I don’t have hard numbers on hand, and it depends on what you are trying to do.
If you were going to build a PCI card:

VGA w/ dumb framebuffer (PCI) is about 10K LE might be 6K
2D is about 20K LE
3D (everything) is about 85K LE. (You actually end up becoming DSP block limited)

If you removed some components like PCI and put it in an SOC part, you would save 1-3K LE.

These numbers are from memory from Altera parts.

-Frank

From: Alexander von Gluck IV <notifications@github.commailto:notifications@github.com>
Reply-To: asicguy/gplgpu <reply@reply.github.commailto:reply@reply.github.com>
Date: Friday, October 24, 2014 at 11:36 AM
To: asicguy/gplgpu <gplgpu@noreply.github.commailto:gplgpu@noreply.github.com>
Cc: Francis Bruno <fbruno@asicsolutions.commailto:fbruno@asicsolutions.com>
Subject: Re: [gplgpu] Need documentation on implementation (#5)

Food for thought, targeting a small demo board for now may be helpful in developing on this code.

For example:

EP4CE6E22C8N (6k LE)
http://www.ebay.com/itm/EP4CE6-EP4CE6E22C8N-FPGA-ALTERA-Cyclone-IV-Development-Evaluation-Board-Core-Kit-/251194059567?pt=LH_DefaultDomain_0&hash=item3a7c552b2f

http://www.ebay.com/itm/EP4CE6-EP4CE6E22C8N-ALTERA-FPGA-Cyclone-IV-Development-Evaluation-Board-Core-Kit-/231074176951?pt=LH_DefaultDomain_0&hash=item35cd181fb7

or

EP4CE10F17C8N (10k LE)

http://www.ebay.com/itm/ALTERA-FPGA-EP4CE10F17C8N-EP4CE10-Cyclone-IV-Development-Evaluation-Core-Board-/261181065297?pt=LH_DefaultDomain_0&hash=item3ccf9ac851

Anyone have any numbers on required logic elements?

That way base boards could be easily developed around the FPGA without the worry of soldering the tiny FPGA pin pitch :-)

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Reply to this email directly or view it on GitHubhttps://github.com//issues/5#issuecomment-60404582.