diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index b12fd29f8e944..0580fb2dfe8dd 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -30,6 +30,21 @@ config ARCH_CHIP_PIC32MZ ---help--- Microchip PIC32MZ (MIPS32) +config ARCH_CHIP_JZ4780 + bool "JZ4780" + select ARCH_MIPS32 + select ARCH_MIPS_XBURST1 + select ARCH_HAVE_IRQPRIO + select ARCH_VECNOTIRQ + select ARCH_HAVE_RESET + select ARCH_HAVE_SERIAL_TERMIOS + select MIPS32_HAVE_DCACHE + select MIPS32_HAVE_ICACHE + select MIPS32_USE_WAIT_INSTRUCTION + select MIPS32_USE_SYSCALL_INSTRUCTION + ---help--- + Ingenic JZ4780 (MIPS32) + config ARCH_CHIP_MIPS_CUSTOM bool "Custom MIPS chip" select ARCH_CHIP_CUSTOM @@ -57,6 +72,10 @@ config ARCH_MIPS_M5150 default n select ARCH_HAVE_MICROMIPS +config ARCH_MIPS_XBURST1 + bool + default n + config ARCH_HAVE_EIC bool default n @@ -82,10 +101,12 @@ config ARCH_CHIP string default "pic32mx" if ARCH_CHIP_PIC32MX default "pic32mz" if ARCH_CHIP_PIC32MZ + default "jz4780" if ARCH_CHIP_JZ4780 source "arch/mips/src/common/Kconfig" source "arch/mips/src/mips32/Kconfig" source "arch/mips/src/pic32mx/Kconfig" source "arch/mips/src/pic32mz/Kconfig" +source "arch/mips/src/jz4780/Kconfig" endif diff --git a/arch/mips/include/jz4780/chip.h b/arch/mips/include/jz4780/chip.h new file mode 100644 index 0000000000000..ef112aa7bff05 --- /dev/null +++ b/arch/mips/include/jz4780/chip.h @@ -0,0 +1,157 @@ +/**************************************************************************** + * arch/mips/include/jz4780/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_MIPS_INCLUDE_JZ4780_CHIP_H +#define __ARCH_MIPS_INCLUDE_JZ4780_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define CKPCR 0xB0003040 +#define CKPCR_CK32CTL_RTCLK (3 << 1) + +#define JZINTC_BASE 0xB0001000 + +#define ICMSR0 (JZINTC_BASE + 0x08) +#define ICMCR0 (JZINTC_BASE + 0x0C) +#define ICPR0 (JZINTC_BASE + 0x10) +#define ICMSR1 (JZINTC_BASE + 0x28) +#define ICMCR1 (JZINTC_BASE + 0x2C) +#define ICPR1 (JZINTC_BASE + 0x30) + +#define JZTMR_BASE 0xB0002000 + +#define WD_TDR (JZTMR_BASE + 0x00) // u16: Watchdog Timer Data +#define WD_TCER (JZTMR_BASE + 0x04) // u8 : Watchdog Counter Enable +#define WD_TCNT (JZTMR_BASE + 0x08) // u16: Watchdog Timer Counter +#define WD_TCSR (JZTMR_BASE + 0x0C) // u16: Watchdog Timer Control + +#define TCSR_PRESCALE(x) ((x) << 3) +#define TCSR_DIV_16 2 + +#define TCSR_EXT_EN (1 << 2) +#define TCSR_RTC_EN (1 << 1) +#define TCSR_PCK_EN (1 << 0) + +#define TCER_TCEN (1 << 0) + +#define OSTDR (JZTMR_BASE + 0xe0) +#define OSTCNTL (JZTMR_BASE + 0xe4) +#define OSTCNTH (JZTMR_BASE + 0xe8) +#define OSTCSR (JZTMR_BASE + 0xec) + +#define TESR (JZTMR_BASE + 0x14) + +#define TESR_OSTEN (1 << 15) +#define TESR_TCEN(n) (1 << (n)) + +#define TMSR (JZTMR_BASE + 0x34) +#define TMCR (JZTMR_BASE + 0x38) +#define TMCR_OSTMCL (1 << 15) +#define TMCR_FMCL5 (1 << 5) +#define TMCR_FMCL(n) (1 << (n)) + +#define TFR (JZTMR_BASE + 0x20) + +#define TFCR (JZTMR_BASE + 0x28) +#define TFCR_OSTFCL (1 << 15) +#define TFCR_FFCL5 (1 << 5) +#define TFCR_FFCL(n) (1 << (n)) + +#define TCNT(n) (JZTMR_BASE + 0x48 + (n)*0x10) +#define TCSR(n) (JZTMR_BASE + 0x4C + (n)*0x10) +#define TDFR(n) (JZTMR_BASE + 0x40 + (n)*0x10) + +#define TICKS_PER_MS (48000/16) + +#define CHIP_JZ4780 1 +#define CHIP_NPORTS 6 /* 6 ports (A-F) */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: jz_physregaddr + * + * Description: + * Give the virtual address of a register, return the physical address of + * the register + * + ****************************************************************************/ + +uintptr_t jz_physregaddr(uintptr_t virtregaddr); + +/**************************************************************************** + * Name: jz_physramaddr + * + * Description: + * Give the virtual address of a RAM memory location, return the physical + * address of that location. + * + ****************************************************************************/ + +uintptr_t jz_physramaddr(uintptr_t vramaddr); + +/**************************************************************************** + * Name: jz_virtramaddr + * + * Description: + * Give the physical address of a RAM memory location, return the virtual + * address of that location. + * + ****************************************************************************/ + +uintptr_t jz_virtramaddr(uintptr_t physramaddr); + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_MIPS_INCLUDE_JZ4780_CHIP_H */ diff --git a/arch/mips/include/jz4780/cp0.h b/arch/mips/include/jz4780/cp0.h new file mode 100644 index 0000000000000..956606d10b67d --- /dev/null +++ b/arch/mips/include/jz4780/cp0.h @@ -0,0 +1,464 @@ +/**************************************************************************** + * arch/mips/include/jz4780/cp0.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_MIPS_INCLUDE_JZ4780_CP0_H +#define __ARCH_MIPS_INCLUDE_JZ4780_CP0_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* CP0 Register Addresses ***************************************************/ + +/* CP0 Registers ************************************************************/ + +/* Register Number: 0 Sel: 0 Name: Index + * Compliance Level: Required for TLB-based MMU; Optional otherwise. + * To be provided + */ + +/* Register Number: 1 Sel: 0 Name: Random + * Compliance Level: Required for TLB-based MMU; Optional otherwise. + * To be provided + */ + +/* Register Number: 2 Sel: 0 Name: EntryLo0 + * Compliance Level: Required for TLB-based MMU; Optional otherwise. + * To be provided + */ + +/* Register Number: 3 Sel: 0 Name: EntryLo1 + * Compliance Level: Required for TLB-based MMU; Optional otherwise. + * To be provided + */ + +/* Register Number: 4 Sel: 0 Name: Context + * Compliance Level: Required for TLB-based MMU; Optional otherwise. + * To be provided + */ + +/* Register Number: 4 Sel: 2 Name: UserLocal + * Function: User read/write register + * Compliance Level: Required for TLB-based MMU; Optional otherwise. + * To be provided + */ + +/* Register Number: 5 Sel: 0 Name: PageMask + * Function: Used for reading from and writing to the TLB + * Compliance Level: Required for TLB-based MMU; Optional otherwise. + * To be provided + */ + +/* Register Number: 5 Sel: 1 Name: PageGrain + * Function: Enable or disable the read and execute inhibit bits in the + * EntryLo0 and EntryLo1 registers. + * Compliance Level: Required for TLB-based MMU; Optional otherwise. + * To be provided + */ + +/* Register Number: 6 Sel: 0 Name: Wired + * Compliance Level: Required for TLB-based MMU; Optional otherwise. + * To be provided + */ + +/* Register Number: 7 Sel: 0 Name: HWREna + * Function: Enables access via the RDHWR instruction to selected hardware + * registers in non-privileged mode. + * Compliance Level: (Reserved for future extensions) + */ + +#define CP0_HWRENA_SHIFT (0) /* Bits 0-3: Enable access to a hardware resource */ +#define CP0_HWRENA_MASK (15 << CP0_HWRENA_SHIFT) +# define CP0_HWRENA_BIT0 (1 << CP0_HWRENA_SHIFT) +# define CP0_HWRENA_BIT1 (2 << CP0_HWRENA_SHIFT) +# define CP0_HWRENA_BIT2 (4 << CP0_HWRENA_SHIFT) +# define CP0_HWRENA_BIT3 (8 << CP0_HWRENA_SHIFT) +#define CP0_HWRENA_ULR (1 << 29) /* Bit 29: User Local Register bit */ + +/* Register Number: 8 Sel: 0 Name: BadVAddr + * Function: Reports the address for the most recent address-related + * exception + * Compliance Level: Required. + * + * See arch/mips/include/mips32/cp0.h + * + * Register Number: 9 Sel: 0 Name: Count + * Function: Processor cycle count + * Compliance Level: Required. + * + * See arch/mips/include/mips32/cp0.h + */ + +/* Register Number: 10 Sel: 0 Name: EntryHi + * Compliance Level: Required for TLB-based MMU; Optional otherwise. + */ + +/* Register Number: 11 Sel: 0 Name: Compare + * Function: Timer interrupt control + * Compliance Level: Required. + * + * See arch/mips/include/mips32/cp0.h + */ + +/* Register Number: 12 Sel: 0 Name: Status + * Function: Processor status and control + * Compliance Level: Required. + * + * See arch/mips/include/mips32/cp0.h + */ + +#undef CP0_STATUS_UX +#undef CP0_STATUS_SX +#undef CP0_STATUS_KX +#undef CP0_STATUS_IMPL +#undef CP0_STATUS_IMPL_SHIFT +#undef CP0_STATUS_IMPL_MASK +#undef CP0_STATUS_PX +#undef CP0_STATUS_FR +#undef CP0_STATUS_CU1 +#undef CP0_STATUS_CU2 +#undef CP0_STATUS_CU3 + +/* 2. The following field is of a different width. Apparently, it + * excludes the software interrupt bits. + * + * CP0_STATUS_IM Bits 8-15: Interrupt Mask + * Vs. + * CP0_STATUS_IPL Bits 10-16+18: Interrupt priority level + * Bits 8-9 reserved + */ + +#define CP0_STATUS_IPL_SHIFT (10) /* Bits 10-16+18: Interrupt priority level */ +#define CP0_STATUS_IPL_MASK (0x17f << CP0_STATUS_IPL_SHIFT) + +/* 3. Supervisor mode not supported + * CP0_STATUS_KSU Bits 3-4: Operating mode (with supervisor mode) + */ + +#undef CP0_STATUS_KSU_SUPER + +/* Register Number: 12 Sel: 1 Name: IntCtl */ + +#define CP0_INTCTL_VS_SHIFT (5) /* Bits 5-9: Vector spacing bits */ +#define CP0_INTCTL_VS_MASK (0x1f << CP0_INTCTL_VS_SHIFT) +# define CP0_INTCTL_VS_0BYTES (0x00 << CP0_INTCTL_VS_SHIFT) +# define CP0_INTCTL_VS_32BYTES (0x01 << CP0_INTCTL_VS_SHIFT) +# define CP0_INTCTL_VS_64BYTES (0x02 << CP0_INTCTL_VS_SHIFT) +# define CP0_INTCTL_VS_128BYTES (0x04 << CP0_INTCTL_VS_SHIFT) +# define CP0_INTCTL_VS_256BYTES (0x08 << CP0_INTCTL_VS_SHIFT) +# define CP0_INTCTL_VS_512BYTES (0x10 << CP0_INTCTL_VS_SHIFT) + +/* Register Number: 12 Sel: 4 Name: View_Ipl + * To be provided + */ + +/* Register Number: 12 Sel: 5 Name: SRSMap2 + * To be provided + */ + +/* Register Number: 13 Sel: 0 Name: Cause + * Function: Cause of last general exception + * Compliance Level: Required. + * + * See arch/mips/include/mips32/cp0.h + */ + +/* Register Number: 13 Sel: 4 Name: View_RIPL + * To be provided + */ + +/* Register Number: 13 Sel: 5 Name: NestedExc + * To be provided + */ + +/* Register Number: 14 Sel: 0 Name: EPC + * Function: Program counter at last exception + * Compliance Level: Required. + * + * See arch/mips/include/mips32/cp0.h + */ + +/* Register Number: 14 Sel: 2 Name: NestedEPC + * To be provided + */ + +/* Register Number: 15 Sel: 0 Name: PRId + * Function: Processor identification and revision + * Compliance Level: Required. + * + * See arch/mips/include/mips32/cp0.h + */ + +#undef CP0_PRID_OPTIONS_SHIFT +#undef CP0_PRID_OPTIONS_MASK + +/* Register Number: 15 Sel: 1 Name: EBASE */ + +/* Register Number: 15 Sel: 2 Name: CDMMBase + * To be provided + */ + +/* Register Number: 16 Sel: 0 Name: Config + * Function: Configuration register + * Compliance Level: Required. + * + * See arch/mips/include/mips32/cp0.h + * 1. JZ4780 is always little-endian. + * 2. Implementation specific bits defined. + */ + +#undef CP0_CONFIG_MT_NONE +#undef CP0_CONFIG_MT_TLB +#undef CP0_CONFIG_MT_BAT + +#undef CP0_CONFIG_IMPL_SHIFT +#undef CP0_CONFIG_IMPL_MASK + +#define CP0_CONFIG_K0_SHIFT (0) /* Bits 0-2: KSEG0 cache */ +#define CP0_CONFIG_K0_MASK (7 << CP0_CONFIG_K0_SHIFT) +#define CP0_CONFIG_K0_WT (0 << CP0_CONFIG_K0_SHIFT) +#define CP0_CONFIG_K0_UNCACHED (2 << CP0_CONFIG_K0_SHIFT) +#define CP0_CONFIG_K0_WB (3 << CP0_CONFIG_K0_SHIFT) + +#define CP0_CONFIG_DS (1 << 16) /* Dual SRAM bit */ +#define CP0_CONFIG_BM (1 << 16) /* Burst Mode bit */ +#define CP0_CONFIG_MM_SHIFT (17) /* Bits 17-18: Merge Mode bits */ +#define CP0_CONFIG_MM_MASK (3 << CP0_CONFIG_MM_SHIFT) +# define CP0_CONFIG_MM_PROHIBITED (0 << CP0_CONFIG_MM_SHIFT) +# define CP0_CONFIG_MM_ALLOWED (2 << CP0_CONFIG_MM_SHIFT) +#define CP0_CONFIG_MDU (1 << 20) +#define CP0_CONFIG_SB (1 << 21) +#define CP0_CONFIG_UDI (1 << 22) +#define CPO_CONFIG_DSP (1 << 23) +#define CPO_CONFIG_ISP (1 << 24) +#define CP0_CONFIG_KU_SHIFT (25) +#define CP0_CONFIG_KU_MASK (7 << CP0_CONFIG_KU_SHIFT) +# define CP0_CONFIG_KU_UNCACHED (2 << CP0_CONFIG_KU_SHIFT) +# define CP0_CONFIG_KU_CACHEABLE (3 << CP0_CONFIG_KU_SHIFT) +#define CP0_CONFIG_K23_SHIFT (28) +#define CP0_CONFIG_K23_MASK (7 << CP0_CONFIG_K23_SHIFT) +# define CP0_CONFIG_K23_UNCACHED (2 << CP0_CONFIG_K23_SHIFT) +# define CP0_CONFIG_K23_CACHEABLE (3 << CP0_CONFIG_K23_SHIFT) + +/* Register Number: 16 Sel: 1 Name: Config1 + * Function: Configuration register 1 + * Compliance Level: Required. + * + * See arch/mips/include/mips32/cp0.h + * + * Register Number: 16 Sel: 2 Name: Config2 + * Function: Configuration register 2 + * Compliance Level: Optional. + * + * See arch/mips/include/mips32/cp0.h + */ + +#undef CP0_CONFIG2_TBS_SHIFT +#undef CP0_CONFIG2_TBS_MASK + +/* Register Number: 16 Sel: 3 Name: Config3 + * Function: Configuration register 3 + * Compliance Level: Optional. + * + * See arch/mips/include/mips32/cp0.h + */ + +/* Register Number: 16 Sel: 4 Name: Config4 + * To be provided + */ + +/* Register Number: 16 Sel: 5 Name: Config5 + * To be provided + */ + +/* Register Number: 16 Sel: 7 Name: Config7 + * To be provided + */ + +/* Register Number: 17 Sel: 0 Name: LLAddr + * Compliance Level: Optional. + * To be provided + */ + +/* Register Number: 18 Sel: 0 Name: WatchLo + * Compliance Level: Optional. + * To be provided + */ + +/* Register Number: 19 Sel: 0 Name: WatchHi + * Compliance Level: Optional. + * To be provided + */ + +/* Register Number: 20-22 Reserved + * Compliance Level: Optional. + */ + +/* Register Number: 23 Sel: 0 Name: Debug + * Function: EJTAG Debug register + * Compliance Level: Optional. + */ + +/* Register Number: 23 Sel: 1 Name: TraceControl + * Function: EJTAG Debug register + * Compliance Level: Optional. + * To be provided + */ + +/* Register Number: 23 Sel: 2 Name: TraceControl2 + * Function: EJTAG Debug register + * Compliance Level: Optional. + * To be provided + */ + +/* Register Number: 23 Sel: 3 Name: UserTraceData1 + * Function: EJTAG Debug register + * Compliance Level: Optional. + * To be provided + */ + +/* Register Number: 23 Sel: 4 Name: TraceBPC + * Function: EJTAG Debug register + * Compliance Level: Optional. + * To be provided + */ + +/* Register Number: 23 Sel: 5 Name: Debug2 + * Function: EJTAG Debug register + * Compliance Level: Optional. + * To be provided + */ + +/* Register Number: 24 Sel: 0 Name: DEPC + * Function: Program counter at last EJTAG debug exception + * Compliance Level: Optional. + * + * See arch/mips/include/mips32/cp0.h + */ + +/* Register Number: 24 Sel: 3 Name: UserTraceData2 + * Function: EJTAG user trace data 2 register + * Compliance Level: Optional. + * To be provided + */ + +/* Register Number: 25 Sel: 0 Name: PerfCtl0 + * Function: Performance counter 0 control + * Compliance Level: Optional. + * To be provided + */ + +/* Register Number: 25 Sel: 1 Name: PerfCnt0 + * Function: Performance counter 0 + * Compliance Level: Optional. + * To be provided + */ + +/* Register Number: 25 Sel: 2 Name: PerfCtl1 + * Function: Performance counter 1 control + * Compliance Level: Optional. + * To be provided + */ + +/* Register Number: 25 Sel: 3 Name: PerfCnt1 + * Function: Performance counter 1 + * Compliance Level: Optional. + * To be provided + */ + +/* Register Number: 26 Sel: 0 Name: ErrCtl + * Function: Software test enable of way-select and data RAM arrays for + * I-Cache and D-Cache + * Compliance Level: Optional. + * To be provided + */ + +/* Register Number: 27 Reserved + * Compliance Level: Recommended/Optional. + */ + +/* Register Number: 28 Sel: 0 Name: TagLo + * Function: Low-order portion of cache tag interface + * Compliance Level: Optional. + * To be provided + */ + +/* Register Number: 28 Sel: 1 Name: DataLo + * Function: Low-order portion of cache tag interface + * Compliance Level: Optional. + * To be provided + */ + +/* Register Number: 29 Reserved + * Compliance Level: Recommended/Optional. + */ + +/* Register Number: 30 Sel: 0 Name: ErrorEPC + * Function: Program counter at last error + * Compliance Level: Required. + * + * See arch/mips/include/mips32/cp0.h + * + * Register Number: 31 Sel: 0 Name: DeSAVE + * Function: EJTAG debug exception save register + * Compliance Level: Optional. + * + * See arch/mips/include/mips32/cp0.h + */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_MIPS_INCLUDE_JZ4780_CP0_H */ diff --git a/arch/mips/include/jz4780/irq.h b/arch/mips/include/jz4780/irq.h new file mode 100644 index 0000000000000..d8349ee831fce --- /dev/null +++ b/arch/mips/include/jz4780/irq.h @@ -0,0 +1,200 @@ +/**************************************************************************** + * arch/mips/include/jz4780/irq.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly + * through nuttx/irq.h + */ + +#ifndef __ARCH_MIPS_INCLUDE_JZ4780_IRQ_H +#define __ARCH_MIPS_INCLUDE_JZ4780_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#if defined(CHIP_JZ4780) +# include +#else +# error "Unknown JZ4780 family +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Inline functions + ****************************************************************************/ + +/**************************************************************************** + * Name: cp0_getintctl + * + * Description: + * Get the CP0 IntCtl register + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline uint32_t cp0_getintctl(void) +{ + register uint32_t intctl; + __asm__ __volatile__ + ( + "\t.set push\n" + "\t.set noat\n" + "\t mfc0 %0, $12, 1\n" /* Get CP0 IntCtl register */ + "\t.set pop\n" + : "=r" (intctl) + : + : "memory" + ); + + return intctl; +} + +/**************************************************************************** + * Name: cp0_putintctl + * + * Description: + * Write the CP0 IntCtl register + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void cp0_putintctl(uint32_t intctl) +{ + __asm__ __volatile__ + ( + "\t.set push\n" + "\t.set noat\n" + "\t.set noreorder\n" + "\tmtc0 %0, $12, 1\n" /* Set the IntCtl to the provided value */ + "\t.set pop\n" + : + : "r" (intctl) + : "memory" + ); +} + +/**************************************************************************** + * Name: cp0_getebase + * + * Description: + * Get the CP0 EBASE register + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline uint32_t cp0_getebase(void) +{ + register uint32_t ebase; + __asm__ __volatile__ + ( + "\t.set push\n" + "\t.set noat\n" + "\t mfc0 %0, $15, 1\n" /* Get CP0 EBASE register */ + "\t.set pop\n" + : "=r" (ebase) + : + : "memory" + ); + + return ebase; +} + +/**************************************************************************** + * Name: cp0_putebase + * + * Description: + * Write the CP0 EBASE register + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void cp0_putebase(uint32_t ebase) +{ + __asm__ __volatile__ + ( + "\t.set push\n" + "\t.set noat\n" + "\t.set noreorder\n" + "\tmtc0 %0, $15, 1\n" /* Set the EBASE to the provided value */ + "\t.set pop\n" + : + : "r" (ebase) + : "memory" + ); +} + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_MIPS_INCLUDE_JZ4780_IRQ_H */ + diff --git a/arch/mips/include/jz4780/irq_jz4780.h b/arch/mips/include/jz4780/irq_jz4780.h new file mode 100644 index 0000000000000..d72c65ad79783 --- /dev/null +++ b/arch/mips/include/jz4780/irq_jz4780.h @@ -0,0 +1,160 @@ +/**************************************************************************** + * arch/mips/include/jz4780/irq_jz4780.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* This file should never be included directly but, rather, only indirectly + * through nuttx/irq.h + */ + +#ifndef __ARCH_MIPS_INCLUDE_JZ4780_IRQ_JZ4780_H +#define __ARCH_MIPS_INCLUDE_JZ4780_IRQ_JZ4780_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Interrupt vector numbers. These should be used to attach to interrupts + * and to change interrupt priorities. + */ + +#define IRQ_OFFSET1 32 +#define IRQ_VIRTUAL 32 + +/* Interrupts from Source 0 */ + +#define JZ4780_IRQ_LCD 31 +#define JZ4780_IRQ_CIM 30 +#define JZ4780_IRQ_IPU 29 +#define JZ4780_IRQ_GPS 28 +#define JZ4780_IRQ_TCU0 27 +#define JZ4780_IRQ_TCU1 26 +#define JZ4780_IRQ_TCU2 25 +#define JZ4780_IRQ_GPS_1MS 24 +#define JZ4780_IRQ_LCD1 23 +#define JZ4780_IRQ_IPU1 22 +#define JZ4780_IRQ_OTG 21 +#define JZ4780_IRQ_EHCI 20 +#define JZ4780_IRQ_X2D 19 +#define JZ4780_IRQ_SADC 18 +#define JZ4780_IRQ_GPIOA 17 +#define JZ4780_IRQ_GPIOB 16 +#define JZ4780_IRQ_GPIOC 15 +#define JZ4780_IRQ_GPIOD 14 +#define JZ4780_IRQ_GPIOE 13 +#define JZ4780_IRQ_GPIOF 12 +#define JZ4780_IRQ_TSSI1 11 +#define JZ4780_IRQ_PDMA 10 +#define JZ4780_IRQ_TSSI0 9 +#define JZ4780_IRQ_SSI0 8 +#define JZ4780_IRQ_SSI1 7 +#define JZ4780_IRQ_RSRV0 6 +#define JZ4780_IRQ_OHCI 5 +#define JZ4780_IRQ_HDMI_WKUP 4 +#define JZ4780_IRQ_HDMI 3 +#define JZ4780_IRQ_BCH 2 +#define JZ4780_IRQ_AIC0 1 +#define JZ4780_IRQ_AIC1 0 + +/* Interrupts from Source 1 */ + +#define JZ4780_IRQ_GPU (31 + IRQ_OFFSET1) +#define JZ4780_IRQ_VPU (30 + IRQ_OFFSET1) +#define JZ4780_IRQ_PDMAM (29 + IRQ_OFFSET1) +#define JZ4780_IRQ_SMB0 (28 + IRQ_OFFSET1) +#define JZ4780_IRQ_SMB1 (27 + IRQ_OFFSET1) +#define JZ4780_IRQ_SMB2 (26 + IRQ_OFFSET1) +#define JZ4780_IRQ_SMB3 (25 + IRQ_OFFSET1) +#define JZ4780_IRQ_SMB4 (24 + IRQ_OFFSET1) +#define JZ4780_IRQ_ETHC (23 + IRQ_OFFSET1) +#define JZ4780_IRQ_NEMC (22 + IRQ_OFFSET1) +#define JZ4780_IRQ_RSRVD1 (21 + IRQ_OFFSET1) +#define JZ4780_IRQ_DDR (20 + IRQ_OFFSET1) +#define JZ4780_IRQ_UART0 (19 + IRQ_OFFSET1) +#define JZ4780_IRQ_UART1 (18 + IRQ_OFFSET1) +#define JZ4780_IRQ_UART2 (17 + IRQ_OFFSET1) +#define JZ4780_IRQ_UART3 (16 + IRQ_OFFSET1) +#define JZ4780_IRQ_CPM (15 + IRQ_OFFSET1) +#define JZ4780_IRQ_HARB0 (14 + IRQ_OFFSET1) +#define JZ4780_IRQ_RSRVD2 (13 + IRQ_OFFSET1) +#define JZ4780_IRQ_HARB2 (12 + IRQ_OFFSET1) +#define JZ4780_IRQ_COMPRESS (11 + IRQ_OFFSET1) +#define JZ4780_IRQ_GPVLC (10 + IRQ_OFFSET1) +#define JZ4780_IRQ_KBC ( 9 + IRQ_OFFSET1) +#define JZ4780_IRQ_PCM0 ( 8 + IRQ_OFFSET1) +#define JZ4780_IRQ_RSVD3 ( 7 + IRQ_OFFSET1) +#define JZ4780_IRQ_SCC ( 6 + IRQ_OFFSET1) +#define JZ4780_IRQ_MSC0 ( 5 + IRQ_OFFSET1) +#define JZ4780_IRQ_MSC1 ( 4 + IRQ_OFFSET1) +#define JZ4780_IRQ_MSC2 ( 3 + IRQ_OFFSET1) +#define JZ4780_IRQ_UART4 ( 2 + IRQ_OFFSET1) +#define JZ4780_IRQ_OWI ( 1 + IRQ_OFFSET1) +#define JZ4780_IRQ_RTC ( 0 + IRQ_OFFSET1) + +/* Virtual interrupts */ + +#define IRQ_SWINT0 ( 8 + IRQ_OFFSET1 + IRQ_VIRTUAL) +#define IRQ_TMR7 ( 7 + IRQ_OFFSET1 + IRQ_VIRTUAL) +#define IRQ_TMR6 ( 6 + IRQ_OFFSET1 + IRQ_VIRTUAL) +#define IRQ_TMR4 ( 4 + IRQ_OFFSET1 + IRQ_VIRTUAL) +#define IRQ_TMR3 ( 3 + IRQ_OFFSET1 + IRQ_VIRTUAL) +#define IRQ_TMR1 ( 1 + IRQ_OFFSET1 + IRQ_VIRTUAL) +#define IRQ_TMR0 ( 0 + IRQ_OFFSET1 + IRQ_VIRTUAL) + +#define NR_IRQS (IRQ_OFFSET1 + IRQ_VIRTUAL + 32) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Inline functions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_MIPS_INCLUDE_JZ4780_IRQ_JZ4780_H */ + diff --git a/arch/mips/src/common/mips_idle.c b/arch/mips/src/common/mips_idle.c index 21fc3a492e42a..0db6c44c453ee 100644 --- a/arch/mips/src/common/mips_idle.c +++ b/arch/mips/src/common/mips_idle.c @@ -60,5 +60,19 @@ void up_idle(void) * sleep in a reduced power mode until an interrupt occurs to save power */ +# if defined(CONFIG_MIPS32_USE_WAIT_INSTRUCTION) + + __asm__ __volatile__ + ( + ".set push\n" + ".set noreorder\n" + "wait\n" + "nop\n" + ".set pop" + : : : "memory" + ); + +# endif + #endif } diff --git a/arch/mips/src/jz4780/Kconfig b/arch/mips/src/jz4780/Kconfig new file mode 100644 index 0000000000000..8e71b3c649a71 --- /dev/null +++ b/arch/mips/src/jz4780/Kconfig @@ -0,0 +1,7 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_CHIP_JZ4780 +endif diff --git a/arch/mips/src/jz4780/Make.defs b/arch/mips/src/jz4780/Make.defs new file mode 100644 index 0000000000000..884c425e5b3d7 --- /dev/null +++ b/arch/mips/src/jz4780/Make.defs @@ -0,0 +1,49 @@ +############################################################################ +# arch/mips/src/jz4780/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +# The start-up, "head", file + +HEAD_ASRC = jz4780_head.S + +# Common MIPS files + +CMN_ASRCS = mips_syscall0.S fork.S mips_cache.S +CMN_CSRCS += mips_allocateheap.c mips_copystate.c mips_createstack.c +CMN_CSRCS += mips_doirq.c mips_exit.c mips_getintstack.c mips_initialize.c +CMN_CSRCS += mips_initialstate.c mips_irq.c mips_lowputs.c +CMN_CSRCS += mips_modifyreg8.c mips_modifyreg16.c mips_modifyreg32.c +CMN_CSRCS += mips_nputs.c mips_releasestack.c mips_registerdump.c +CMN_CSRCS += mips_schedulesigaction.c mips_sigdeliver.c mips_swint0.c +CMN_CSRCS += mips_stackframe.c mips_switchcontext.c mips_saveusercontext.c +CMN_CSRCS += mips_usestack.c mips_fork.c + +# Configuration dependent common files + +ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) +CMN_CSRCS += mips_idle.c +endif + +# Required JZ4780 files + +CHIP_ASRCS = +CHIP_CSRCS = jz4780_lowinit.c jz4780_exception.c jz4780_decodeirq.c +CHIP_CSRCS += jz4780_irq.c jz4780_timerisr.c diff --git a/arch/mips/src/jz4780/chip.h b/arch/mips/src/jz4780/chip.h new file mode 100644 index 0000000000000..58884353e1b72 --- /dev/null +++ b/arch/mips/src/jz4780/chip.h @@ -0,0 +1,65 @@ +/**************************************************************************** + * arch/mips/src/jz4780/chip.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_MIPS_SRC_JZ4780_CHIP_H +#define __ARCH_MIPS_SRC_JZ4780_CHIP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_MIPS_SRC_JZ4780_CHIP_H */ diff --git a/arch/mips/src/jz4780/hardware/jz4780_pinmap.h b/arch/mips/src/jz4780/hardware/jz4780_pinmap.h new file mode 100644 index 0000000000000..ba2a892181153 --- /dev/null +++ b/arch/mips/src/jz4780/hardware/jz4780_pinmap.h @@ -0,0 +1,36 @@ +/**************************************************************************** + * arch/mips/src/jz4780/hardware/jz4780_pinmap.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_MIPS_SRC_JZ4780_HARDWARE_JZ4780_PINMAP_H +#define __ARCH_MIPS_SRC_JZ4780_HARDWARE_JZ4780_PINMAP_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#endif /* __ARCH_MIPS_SRC_JZ4780_JZ4780_PINMAP_H */ diff --git a/arch/mips/src/jz4780/jz4780_decodeirq.c b/arch/mips/src/jz4780/jz4780_decodeirq.c new file mode 100644 index 0000000000000..e5202859efa69 --- /dev/null +++ b/arch/mips/src/jz4780/jz4780_decodeirq.c @@ -0,0 +1,191 @@ +/**************************************************************************** + * arch/mips/src/jz4780/jz4780_decodeirq.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include + +#include +#include +#include +#include +#include + +#include "mips_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: jz4780_decodeirq + * + * Description: + * Called from assembly language logic when an interrupt exception occurs. + * This function decodes and dispatches the interrupt. + * + ****************************************************************************/ + +uint32_t *jz4780_decodeirq(uint32_t *regs) +{ + struct tcb_s **running_task = &g_running_tasks[this_cpu()]; + + if (*running_task != NULL) + { + mips_copystate((*running_task)->xcp.regs, regs); + } + + unsigned int source = getreg32(ICPR0); + unsigned int source1 = getreg32(ICPR1); + + int irq = -1; + if (source != 0) + { + irq = 31 - __builtin_clz(source); + } + else if (source1 != 0) + { + irq = 32 + 31 - __builtin_clz(source1); + } + + /* If the board supports LEDs, turn on an LED now to indicate that we are + * processing an interrupt. + */ + + board_autoled_on(LED_INIRQ); + + /* Save the current value of g_current_regs (to support nested interrupt + * handling). Then set g_current_regs to regs, indicating that this is + * the interrupted context that is being processed now. + */ + + DEBUGASSERT(up_current_regs() == NULL); + up_set_current_regs(regs); + + if (irq == JZ4780_IRQ_TCU1) + { + putreg32(TFCR_FFCL5, TFCR); + } + else if (irq == JZ4780_IRQ_TCU2) + { + uint32_t tfcr = getreg32(TFR) & 0xdf; + if (!tfcr) + { + irq = -1; + } + else + { + int n = 31 - __builtin_clz(tfcr); + putreg32(TFCR_FFCL(n), TFCR); + irq = IRQ_TMR0 + n; + } + } + + if (irq >= 0) + { + /* Deliver the IRQ */ + + irq_dispatch(irq, regs); + } + + /* If a context switch occurred while processing the interrupt then + * g_current_regs may have change value. If we return any value different + * from the input regs, then the lower level will know that a context + * switch occurred during interrupt processing. + */ + + regs = up_current_regs(); + +#if defined(CONFIG_ARCH_FPU) || defined(CONFIG_ARCH_ADDRENV) + /* Check for a context switch. If a context switch occurred, then + * g_current_regs will have a different value than it did on entry. If an + * interrupt level context switch has occurred, then restore the floating + * point state and the establish the correct address environment before + * returning from the interrupt. + */ + + if (regs != up_current_regs()) + { +#ifdef CONFIG_ARCH_FPU + /* Restore floating point registers */ + + up_restorefpu(up_current_regs()); +#endif + +#ifdef CONFIG_ARCH_ADDRENV + /* Make sure that the address environment for the previously + * running task is closed down gracefully (data caches dump, + * MMU flushed) and set up the address environment for the new + * thread at the head of the ready-to-run list. + */ + + (void)group_addrenv(NULL); +#endif + } +#endif + + up_set_current_regs(NULL); + board_autoled_off(LED_INIRQ); + + return regs; +} + +/**************************************************************************** + * Name: jz4780_swint0 + * + * Description: + * Called from assembly language logic when an interrupt exception occurs. + * Software interrupts are unused on this platform + * + ****************************************************************************/ + +uint32_t *jz4780_swint0(uint32_t *regs) +{ + /* Leave this here so we can test exception handler placement */ + + _alert("Unexpected software interrupt\n"); + return regs; +} + diff --git a/arch/mips/src/jz4780/jz4780_exception.c b/arch/mips/src/jz4780/jz4780_exception.c new file mode 100644 index 0000000000000..83f5d261e0dfd --- /dev/null +++ b/arch/mips/src/jz4780/jz4780_exception.c @@ -0,0 +1,269 @@ +/**************************************************************************** + * arch/mips/src/jz4780/jz4780_exception.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +#include "mips_internal.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: jz4780_exception + * + * Description: + * Called from assembly language logic on all other exceptions. + * + ****************************************************************************/ + +uint32_t *jz4780_exception(uint32_t *regs) +{ + uint32_t cause; + uint32_t epc; + + /* If the board supports LEDs, turn on an LED now to indicate that we are + * processing an interrupt. + */ + + board_autoled_on(LED_INIRQ); + + /* Get the cause of the exception from the CAUSE register */ + + asm volatile("\tmfc0 %0,$13,0\n" : "=r"(cause)); + asm volatile("\tmfc0 %0,$14,0\n" : "=r"(epc)); + + if ((cause & CP0_CAUSE_EXCCODE_MASK) == CP0_CAUSE_EXCCODE_SYS) + { + if (cause & CP0_CAUSE_BD) + { + /* Syscall in delay slot! + * EPC points to the Branch. We need to skip the Branch (4) + * AND the Syscall in the delay slot (4). + */ + + regs[REG_EPC] += 8; + } + else + { + /* Standard syscall. Just skip the syscall instruction itself. */ + + regs[REG_EPC] += 4; + } + + switch (regs[REG_A0]) + { + /* A0=SYS_save_context: This is a save context command: + * + * int up_saveusercontext(void *saveregs); + * + * At this point, the following values are saved in context: + * + * A0 = SYS_save_context + * A1 = saveregs + * + * In this case, we simply need to copy the current registers to + * the save register space references in the saved R1 and return. + */ + + case SYS_save_context: + { + DEBUGASSERT(regs[REG_A1] != 0); + mips_copystate((uint32_t *)regs[REG_A1], regs); + } + break; + + /* A0=SYS_restore_context: This a restore context command: + * + * void + * up_fullcontextrestore(uint32_t *restoreregs) noreturn_function; + * + * At this point, the following values are saved in context: + * + * A0 = SYS_restore_context + * A1 = restoreregs + * + * In this case, we simply need to set g_current_regs to restore + * the register area referenced in the saved R1. + * context == g_current_regs is the normal exception return. By + * setting g_current_regs equals to context[R1], we force the + * return to the saved context referenced in R1. + */ + + case SYS_restore_context: + { + DEBUGASSERT(regs[REG_A1] != 0); + up_set_current_regs((uint32_t *)regs[REG_A1]); + } + break; + + /* A0=SYS_switch_context: This a switch context command: + * + * void mips_switchcontext(uint32_t *saveregs, + * uint32_t *restoreregs); + * + * At this point, the following values are saved in context: + * + * A0 = SYS_switch_context + * A1 = saveregs + * A2 = restoreregs + * + * In this case, we save the context registers to the save register + * area referenced by the saved contents of A1 and then set + * g_current_regs to the save register area referenced by the saved + * contents of A2. + */ + + case SYS_switch_context: + { + DEBUGASSERT(regs[REG_A1] != 0 && regs[REG_A2] != 0); + mips_copystate((uint32_t *)regs[REG_A1], regs); + up_set_current_regs((uint32_t *)regs[REG_A2]); + } + break; + + default: + { + svcerr("ERROR: Bad SYS call: %" PRId32 "\n", regs[REG_A0]); + } + break; + } + + regs = up_current_regs(); + up_set_current_regs(NULL); + board_autoled_off(LED_INIRQ); + return regs; + } + +#ifdef CONFIG_DEBUG_INFO + switch (cause & CP0_CAUSE_EXCCODE_MASK) + { + case CP0_CAUSE_EXCCODE_INT: /* Interrupt */ + _alert("EXCEPTION: Interrupt" + " CAUSE: %x EPC: %x\n", cause, epc); + break; + case CP0_CAUSE_EXCCODE_TLBL: /* TLB exception (load or instruction fetch) */ + _alert("EXCEPTION: TLB exception (load or instruction fetch)" + " CAUSE: %x EPC:%x\n", cause, epc); + break; + case CP0_CAUSE_EXCCODE_TLBS: /* TLB exception (store) */ + _alert("EXCEPTION: TLB exception (store)" + " CAUSE: %x EPC: %x\n", cause, epc); + break; + case CP0_CAUSE_EXCCODE_ADEL: /* Address error exception (load or instruction fetch) */ + _alert("EXCEPTION: Address error exception (load or instruction fetch)" + " CAUSE: %x EPC: %x\n", cause, epc); + break; + case CP0_CAUSE_EXCCODE_ADES: /* Address error exception (store) */ + _alert("EXCEPTION: Address error exception (store)" + " CAUSE: %x EPC: %x\n", cause, epc); + break; + case CP0_CAUSE_EXCCODE_IBE: /* Bus error exception (instruction fetch) */ + _alert("EXCEPTION: Bus error exception (instruction fetch)" + " CAUSE: %x EPC: %x\n", cause, epc); + break; + case CP0_CAUSE_EXCCODE_DBE: /* Bus error exception (data reference: load or store) */ + _alert("EXCEPTION: Bus error exception (data reference: load or store)" + " CAUSE: %x EPC: %x\n", cause, epc); + break; + case CP0_CAUSE_EXCCODE_SYS: /* Syscall exception */ + _alert("EXCEPTION: Syscall exception" + " CAUSE: %x EPC: %x\n", cause, epc); + break; + case CP0_CAUSE_EXCCODE_BP: /* Breakpoint exception */ + _alert("EXCEPTION: Breakpoint exception" + " CAUSE: %x EPC: %x\n", cause, epc); + break; + case CP0_CAUSE_EXCCODE_RI: /* Reserved instruction exception */ + _alert("EXCEPTION: Reserved instruction exception" + " CAUSE: %x EPC: %x\n", cause, epc); + break; + case CP0_CAUSE_EXCCODE_CPU: /* Coprocessor Unusable exception */ + _alert("EXCEPTION: Coprocessor Unusable exception" + " CAUSE: %x EPC: %x\n", cause, epc); + break; + case CP0_CAUSE_EXCCODE_OV: /* Arithmetic Overflow exception */ + _alert("EXCEPTION: Arithmetic Overflow exception" + " CAUSE: %x EPC: %x\n", cause, epc); + break; + case CP0_CAUSE_EXCCODE_TR: /* Trap exception */ + _alert("EXCEPTION: Trap exception" + " CAUSE: %x EPC: %x\n", cause, epc); + break; + case CP0_CAUSE_EXCCODE_FPE: /* Floating point exception */ + _alert("EXCEPTION: Floating point exception" + " CAUSE: %x EPC: %x\n", cause, epc); + break; + case CP0_CAUSE_EXCCODE_C2E: /* Precise Coprocessor 2 exceptions */ + _alert("EXCEPTION: Precise Coprocessor 2 exceptions" + " CAUSE: %x EPC: %x\n", cause, epc); + break; + case CP0_CAUSE_EXCCODE_MDMX: /* MDMX Unusable (MIPS64) */ + _alert("EXCEPTION: MDMX Unusable (MIPS64)" + " CAUSE: %x EPC: %x\n", cause, epc); + break; + case CP0_CAUSE_EXCCODE_WATCH: /* WatchHi/WatchLo address */ + _alert("EXCEPTION: WatchHi/WatchLo address" + " CAUSE: %x EPC: %x\n", cause, epc); + break; + case CP0_CAUSE_EXCCODE_MCHECK: /* Machine check */ + _alert("EXCEPTION: Machine check" + " CAUSE: %x EPC: %x\n", cause, epc); + break; + case CP0_CAUSE_EXCCODE_CACHEERR: /* Cache error */ + _alert("EXCEPTION: Cache error" + " CAUSE: %x EPC: %x\n", cause, epc); + break; + default: + _alert("EXCEPTION: Unknown" + " CAUSE: %x EPC: %x\n", cause, epc); + break; + } +#else + _alert("EXCEPTION: CAUSE: %x EPC: %x\n", cause, epc); +#endif + up_dump_register(regs); + + /* Crash with currents_regs set so that we can dump the register + * contents. + */ + + up_set_current_regs(regs); + PANIC_WITH_REGS("panic", regs); + return regs; /* Won't get here */ +} diff --git a/arch/mips/src/jz4780/jz4780_excptmacros.h b/arch/mips/src/jz4780/jz4780_excptmacros.h new file mode 100644 index 0000000000000..2b0762af5cf5d --- /dev/null +++ b/arch/mips/src/jz4780/jz4780_excptmacros.h @@ -0,0 +1,259 @@ +/***************************************************************************** + * arch/mips/src/jz4780/jz4780_excptmacros.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + *****************************************************************************/ + +#ifndef __ARCH_MIPS_SRC_JZ4780_EXCPTMACROS_H +#define __ARCH_MIPS_SRC_JZ4780_EXCPTMACROS_H + +/***************************************************************************** + * Included Files + *****************************************************************************/ + +#include + +#include +#include + +#ifdef __ASSEMBLY__ + +/***************************************************************************** + * Pre-processor Definitions + *****************************************************************************/ + +/***************************************************************************** + * Public Symbols + *****************************************************************************/ + +/***************************************************************************** + * Assembly Language Macros + *****************************************************************************/ + +/***************************************************************************** + * Name: EXCPT_PROLOGUE + * + * Description: + * Provides the "prologue" logic that should appear at the beginning of + * every exception handler. + * + * On Entry: + * sp - Points to the top of the stack + * tmp - Is a register the can be modified for scratch usage (after it has + * been saved) k0 and k1 - Since we are in an exception handler, these are + * available for use + * + * At completion: + * Register state is saved on the stack; All registers are available for + * usage except sp and k1: + * + * - sp points the beginning of the register save area + * - k1 holds the value of the STATUS register + * + * The following registers are modified: k0, k1, sp, a0 + * + *****************************************************************************/ + + .macro EXCPT_PROLOGUE, tmp + .set noat + + mfc0 k0, MIPS32_CP0_EPC + mfc0 k1, MIPS32_CP0_STATUS + + addiu sp, sp, -XCPTCONTEXT_SIZE + + /* Save the EPC and STATUS in the register context array */ + + sw k0, REG_EPC(sp) + sw k1, REG_STATUS(sp) + + /* Save floating point registers */ + + mfhi k0 + sw k0, REG_MFHI(sp) + mflo k0 + sw k0, REG_MFLO(sp) + + /* Save general purpose registers */ + + /* $1: at_reg, assembler temporary */ + + sw $1, REG_AT(sp) + + /* $2-$3 = v0-v1: Return value registers */ + + sw v0, REG_V0(sp) + sw v1, REG_V1(sp) + + /* $4-$7 = a0-a3: Argument registers */ + + sw a0, REG_A0(sp) + sw a1, REG_A1(sp) + sw a2, REG_A2(sp) + sw a3, REG_A3(sp) + + /* $8-$15 = t0-t7: Volatile registers */ + + sw t0, REG_T0(sp) + sw t1, REG_T1(sp) + sw t2, REG_T2(sp) + sw t3, REG_T3(sp) + sw t4, REG_T4(sp) + sw t5, REG_T5(sp) + sw t6, REG_T6(sp) + sw t7, REG_T7(sp) + + /* $16-$23 = s0-s7: Static registers */ + + sw s0, REG_S0(sp) + sw s1, REG_S1(sp) + sw s2, REG_S2(sp) + sw s3, REG_S3(sp) + sw s4, REG_S4(sp) + sw s5, REG_S5(sp) + sw s6, REG_S6(sp) + sw s7, REG_S7(sp) + + /* $24-25 = t8-t9: More Volatile registers */ + + sw t8, REG_T8(sp) + sw t9, REG_T9(sp) + +#ifdef MIPS32_SAVE_GP + sw gp, REG_GP(sp) +#endif + + /* $30 = either s8 or fp: Depends if a frame pointer is used or not */ + + sw s8, REG_S8(sp) + + /* $31 = ra: Return address */ + + sw ra, REG_RA(sp) + + addiu \tmp, sp, XCPTCONTEXT_SIZE + sw \tmp, REG_SP(sp) + .endm + +/***************************************************************************** + * Name: EXCPT_EPILOGUE + * + * Description: + * Provides the "epilogue" logic that should appear at the end of every + * exception handler. + * + * On input: + * regs - points to the register save structure. NOTE: This *may not* be + * an address lying in a stack! It might be an address in a TCB! + * Interrupts are disabled (via 'di') + * + * On completion: + * All registers restored + * eret is executed to return from the exception + * + *****************************************************************************/ + + .macro EXCPT_EPILOGUE, regs + .set noat + + /* Use k1 as the pointer to the register save array. */ + + move k1, \regs + + /* Restore the floating point register state */ + + lw k0, REG_MFLO(k1) + mtlo k0 + lw k0, REG_MFHI(k1) + mthi k0 + + /* Restore general purpose registers */ + + /* $1: at_reg, assembler temporary */ + + lw $1, REG_AT(k1) + + /* $2-$3 = v0-v1: Return value registers */ + + lw v0, REG_V0(k1) + lw v1, REG_V1(k1) + + /* $4-$7 = a0-a3: Argument registers */ + + lw a0, REG_A0(k1) + lw a1, REG_A1(k1) + lw a2, REG_A2(k1) + lw a3, REG_A3(k1) + + /* $8-$15 = t0-t7: Volatile registers */ + + lw t0, REG_T0(k1) + lw t1, REG_T1(k1) + lw t2, REG_T2(k1) + lw t3, REG_T3(k1) + lw t4, REG_T4(k1) + lw t5, REG_T5(k1) + lw t6, REG_T6(k1) + lw t7, REG_T7(k1) + + /* $16-$23 = s0-s7: Static registers */ + + lw s0, REG_S0(k1) + lw s1, REG_S1(k1) + lw s2, REG_S2(k1) + lw s3, REG_S3(k1) + lw s4, REG_S4(k1) + lw s5, REG_S5(k1) + lw s6, REG_S6(k1) + lw s7, REG_S7(k1) + + /* $24-25 = t8-t9: More Volatile registers */ + + lw t8, REG_T8(k1) + lw t9, REG_T9(k1) + +#ifdef MIPS32_SAVE_GP + lw gp, REG_GP(k1) +#endif + + /* $29 = sp: Stack pointer */ + + lw sp, REG_SP(k1) + + /* $30 = either s8 or fp: Depends if a frame pointer is used or not */ + + lw s8, REG_S8(k1) + + /* $31 = ra: Return address */ + + lw ra, REG_RA(k1) + + /* Finally, restore CP status and the EPC */ + + lw k0, REG_STATUS(k1) + lw k1, REG_EPC(k1) + mtc0 k0, MIPS32_CP0_STATUS + ehb + mtc0 k1, MIPS32_CP0_EPC + eret + nop + .endm + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_MIPS_SRC_JZ4780_EXCPTMACROS_H */ diff --git a/arch/mips/src/jz4780/jz4780_head.S b/arch/mips/src/jz4780/jz4780_head.S new file mode 100644 index 0000000000000..5af5b296da397 --- /dev/null +++ b/arch/mips/src/jz4780/jz4780_head.S @@ -0,0 +1,392 @@ +/**************************************************************************** + * arch/mips/src/jz4780/jz4780_head.S + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "jz4780_excptmacros.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define JZ4780_STACK_BASE _ebss +#define JZ4780_STACK_TOP _ebss + CONFIG_IDLETHREAD_STACKSIZE - 8 + +#define JZ4780_HEAP_BASE JZ4780_STACK_TOP + +/**************************************************************************** + * Public Symbols + ****************************************************************************/ + + .file "jz4780_head.S" + + /* Exported symbols */ + + .global __reset + .global __start + .global halt + .global g_idle_topstack + + /* Imported symbols */ + + .global nx_start + .global jz4780_exception + .global jz4780_decodeirq + .global jz4780_swint0 + + /* This file contains 32-bit assembly code */ + + .set nomips16 + + +/**************************************************************************** + * Name: _gen_exception + * + * Description: + * General Exception Vector Handler. Jumps to _exception_handler. + * + * Input Parameters: + * None + * + * Returned Value: + * Does not return + * + ****************************************************************************/ + + .section .gen_excpt,"ax",@progbits + .set noreorder + .ent _gen_exception + +_gen_exception: + la k0, _exception_handler + jr k0 + nop + .end _gen_exception + +/**************************************************************************** + * Name: _ebase_exception + * + * Description: + * Interrupt Exception Vector Handlers. + * + * Input Parameters: + * None + * + * Returned Value: + * Does not return + * + ****************************************************************************/ + + .section .ebase_excpt,"ax",@progbits + .set noreorder + .ent _ebase_exception + +_ebase_exception: + la k0, _swint_handler + jr k0 + nop + .end _ebase_exception + + + .section .ebase_excpt1,"ax",@progbits + .set noreorder + .ent _ebase_exception1 + +_ebase_exception1: + la k0, _int_handler + jr k0 + nop + .end _ebase_exception1 + + + .section .ebase_excpt2,"ax",@progbits + .set noreorder + .ent _ebase_exception2 + +_ebase_exception2: + la k0, _int_handler + jr k0 + nop + .end _ebase_exception2 + + + .section .ebase_excpt3,"ax",@progbits + .set noreorder + .ent _ebase_exception3 + +_ebase_exception3: + la k0, _int_handler + jr k0 + nop + .end _ebase_exception3 + + +/**************************************************************************** + * Name: _bev_exception + * + * Description: + * Boot Exception Vector Handler. Jumps to _exception_handler. + * + * Input Parameters: + * None + * + * Returned Value: + * Does not return + * + ****************************************************************************/ + + .section .bev_excpt,"ax",@progbits + .set noreorder + .ent _bev_exception + +_bev_exception: + la k0, _exception_handler + jr k0 + nop + .end _bev_exception + +/**************************************************************************** + * Name: _int_exception + * + * Description: + * Interrupt Exception Vector Handler. Jumps to _int_handler. + * + * Input Parameters: + * None + * + * Returned Value: + * Does not return + * + ****************************************************************************/ + + .section .int_excpt,"ax",@progbits + .set noreorder + .ent _int_exception + +_int_exception: + la k0, _int_handler + jr k0 + nop + .end _int_exception + +/**************************************************************************** + * Name: __start + * + * Description: + * This is the KSEG0 startup code. It receives control from the reset + * entry point. This prepares the processor to execute C code, performs + * some very low-level initialization, then starts NuttX (via __start_nuttx) + * + * Input Parameters: + * None + * + * Returned Value: + * Does not return + * + ****************************************************************************/ + + .section .start, "ax", @progbits + .set noreorder + .ent __start + +__start: + + /* Initialize the stack pointer */ + + la sp, JZ4780_STACK_TOP + + /* Initialize the global pointer (gp). _gp is initialized by the linker + * script to point to the "middle" of the small variables region. + */ + + la gp, _gp + + /* Clear uninitialized data sections */ + + la t0, _sbss + la t1, _ebss + b .Lbsscheck + nop + +.Lbssloop: + sw zero, 0x0(t0) + sw zero, 0x4(t0) + sw zero, 0x8(t0) + sw zero, 0xc(t0) + addu t0, 16 + +.Lbsscheck: + bltu t0, t1, .Lbssloop + nop + + /* Copy initialized data from program flash to data memory */ + + la t0, _data_loaddr + la t1, _sdata + la t2, _edata + b .Ldatacheck + nop + +.Ldataloop: + lw t3, (t0) + sw t3, (t1) + addu t0, 4 + addu t1, 4 + +.Ldatacheck: + bltu t1, t2, .Ldataloop + nop + + /* Start NuttX. We do this via a thunk in the text section so that + * a normal jump and link can be used, enabling the startup code + * to work properly whether main is written in MIPS16 or MIPS32 + * code. I.e., the linker will correctly adjust the JAL to JALX if + * necessary + */ + + la t0, __start_nuttx + jr t0 + nop + .end __start + +/**************************************************************************** + * Name: _exception_handler + * + * Description: + * BEV/General exception handler. Calls jz4780_exception() + * + ****************************************************************************/ + + .section .bev_handler, "ax", @progbits + .set noreorder + .ent _exception_handler + +_exception_handler: + EXCPT_PROLOGUE t0 + move a0, sp + la t0, jz4780_exception + jalr ra, t0 + nop + EXCPT_EPILOGUE v0 + .end _exception_handler + +/**************************************************************************** + * Name: _swint_handler + * + * Description: + * Interrupt exception handler. Calls up_decodeirq() + * + ****************************************************************************/ + + .section .swint_handler, "ax", @progbits + .set noreorder + .ent _swint_handler + +_swint_handler: + EXCPT_PROLOGUE t0 + move a0, sp + la t0, jz4780_swint0 + jalr ra, t0 + nop + EXCPT_EPILOGUE v0 + .end _swint_handler + + +/**************************************************************************** + * Name: _int_handler + * + * Description: + * Interrupt exception handler. Calls up_decodeirq() + * + ****************************************************************************/ + + .section .int_handler, "ax", @progbits + .set noreorder + .ent _int_handler + +_int_handler: + EXCPT_PROLOGUE t0 + move a0, sp + la t0, jz4780_decodeirq + jalr ra, t0 + nop + EXCPT_EPILOGUE v0 + .end _int_handler + +/**************************************************************************** + * Name: __start_nuttx + * + * Description: + * + * Input Parameters: + * None + * + * Returned Value: + * Does not return + * + ****************************************************************************/ + + .text + .ent __start_nuttx + +__start_nuttx: + + /* Perform low level initialization */ + + la t0, jz4780_lowinit + jalr ra, t0 + nop + + /* Call nx_start */ + + la t0, nx_start + jalr ra, t0 + nop + + /* Just in case main returns, go into an infinite loop */ + +halt: +1: + b 1b + nop + .end __start_nuttx + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* This global variable is unsigned int g_idle_topstack and is exported here only + * because of its coupling to idle thread stack. + */ + + .sdata + .type g_idle_topstack, object +g_idle_topstack: + .long JZ4780_HEAP_BASE + .size g_idle_topstack, .-g_idle_topstack diff --git a/arch/mips/src/jz4780/jz4780_irq.c b/arch/mips/src/jz4780/jz4780_irq.c new file mode 100644 index 0000000000000..dcec1dd7fd6aa --- /dev/null +++ b/arch/mips/src/jz4780/jz4780_irq.c @@ -0,0 +1,234 @@ +/**************************************************************************** + * arch/mips/src/jz4780/jz4780_irq.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include +#include + +#include "mips_internal.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Interrupt controller definitions *****************************************/ + +/* Number of interrupt enable/interrupt status registers */ + +#define INT_NREGS ((NR_IRQS + 31) >> 5) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: jz4780_prioritize_irq + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_irqinitialize + ****************************************************************************/ + +void up_irqinitialize(void) +{ + uint32_t regval; + + /* Disable all interrupts */ + + putreg32(0xffffffff, ICMSR0); + putreg32(0xffffffff, ICMSR1); + + cp0_putebase(0x80000000); + + /* Set the INTCTL vector spacing to non-zero */ + + regval = cp0_getintctl() & ~(0b1111 << 5); + regval |= 1 << 5; + cp0_putintctl(regval); + + /* Set the IV bit in the CAUSE register */ + + cp0_putcause(cp0_getcause() | CP0_CAUSE_IV); + + /* Clear the EXL and BEV bits in the STATUS register */ + + regval = cp0_getstatus(); + regval &= ~(CP0_STATUS_ERL | CP0_STATUS_EXL | CP0_STATUS_BEV); + cp0_putstatus(regval); + + /* Initialize GPIO change notification handling */ + +#ifdef CONFIG_JZ4780_GPIOIRQ + jz4780_gpioirqinitialize(); +#endif + + /* Attach and enable software interrupts */ + + irq_attach(IRQ_SWINT0, mips_swint0, NULL); + up_enable_irq(IRQ_SWINT0); + + /* And finally, enable interrupts */ + + /* Enable Interrupts */ + + asm volatile("ei %0" : "=r"(regval)); + +#ifndef CONFIG_SUPPRESS_INTERRUPTS + /* Then enable all interrupt levels */ + + up_irq_restore(CP0_STATUS_IM_ALL); +#else + /* Enable only software interrupts */ + + up_irq_restore(CP0_STATUS_IM_SWINTS); +#endif +} + +/**************************************************************************** + * Name: up_disable_irq + * + * Description: + * Disable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_disable_irq(int irq) +{ + DEBUGASSERT((unsigned)irq < NR_IRQS); + + if (irq >= IRQ_TMR0 && irq <= IRQ_TMR7) + { + uint32_t n = irq - IRQ_TMR0; + putreg32(TMCR_FMCL(n), TMSR); + } + else if (irq < 32) + { + if (irq == JZ4780_IRQ_TCU1) + { + putreg32(TMCR_FMCL5, TMSR); + } + + putreg32(1 << irq, ICMSR0); + } + else if (irq < 64) + { + putreg32(1 << (irq % 32), ICMSR1); + } +} + +/**************************************************************************** + * Name: up_enable_irq + * + * Description: + * Enable the IRQ specified by 'irq' + * + ****************************************************************************/ + +void up_enable_irq(int irq) +{ + DEBUGASSERT((unsigned)irq < NR_IRQS); + + if (irq >= IRQ_TMR0 && irq <= IRQ_TMR7) + { + uint32_t n = irq - IRQ_TMR0; + putreg32(TMCR_FMCL(n), TMCR); + putreg32(1 << JZ4780_IRQ_TCU2, ICMCR0); + } + else if (irq < 32) + { + if (irq == JZ4780_IRQ_TCU1) + { + putreg32(TMCR_FMCL5, TMCR); + } + + putreg32(1 << irq, ICMCR0); + } + else if (irq < 64) + { + putreg32(1 << (irq % 32), ICMCR1); + } +} + +/**************************************************************************** + * Name: up_pending_irq + * + * Description: + * Return true if the interrupt is pending and unmasked. + * + ****************************************************************************/ + +bool up_pending_irq(int irq) +{ + DEBUGASSERT((unsigned)irq < NR_IRQS); + + if (irq < 32) + { + return getreg32(ICPR0) & 1 << irq; + } + else if (irq < 64) + { + return getreg32(ICPR1) & 1 << (irq % 32); + } + + return false; +} + +/**************************************************************************** + * Name: up_clrpend_irq + * + * Description: + * Clear any pending interrupt + * + ****************************************************************************/ + +void mips_clrpend_irq(int irq) +{ + /* Acknowledge the interrupt by clearing the associated bit in the IFS + * register. It is necessary to do this BEFORE lowering the interrupt + * priority level otherwise recursive interrupts would occur. + */ +} + +void mips_clrpend_sw0(void) +{ + mips_clrpend_irq(IRQ_SWINT0); +} diff --git a/arch/mips/src/jz4780/jz4780_lowinit.c b/arch/mips/src/jz4780/jz4780_lowinit.c new file mode 100644 index 0000000000000..46b5650917246 --- /dev/null +++ b/arch/mips/src/jz4780/jz4780_lowinit.c @@ -0,0 +1,186 @@ +/**************************************************************************** + * arch/mips/src/jz4780/jz4780_lowinit.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "mips_internal.h" + +#include "jz4780_lowinit.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: jz4780_pbclk + * + * Description: + * Configure peripheral bus clocking + * + * Assumptions: + * Interrupts are disabled. + * + ****************************************************************************/ + +static inline void jz4780_pbclk(void) +{ + putreg32(CKPCR_CK32CTL_RTCLK, CKPCR); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: jz4780_lowinit + * + * Description: + * This performs basic low-level initialization of the system. + * + * Assumptions: + * Interrupts have not yet been enabled. + * + ****************************************************************************/ + +void jz4780_lowinit(void) +{ + /* Configure peripheral clocking */ + + jz4780_pbclk(); + + /* Perform early serial initialization (so that we will have debug output + * available as soon as possible). + */ + +#ifdef USE_EARLYSERIALINIT + u16550_earlyserialinit(); +#endif + + /* Perform board-level initialization */ + + jz4780_boardinitialize(); +} + +/**************************************************************************** + * Name: uart_getreg(), uart_putreg() + * + * Description: + * These functions must be provided by the processor-specific code in order + * to correctly access 16550 registers + * + ****************************************************************************/ + +uart_datawidth_t uart_getreg(struct u16550_s *priv, unsigned int offset) +{ + return *(volatile uart_addrwidth_t *)(priv->uartbase + offset); +} + +void uart_putreg(struct u16550_s *priv, unsigned int offset, + uart_datawidth_t value) +{ + *(volatile uart_addrwidth_t *)(priv->uartbase + offset) = value; +} + +/**************************************************************************** + * Name: mips_serialinit + * + * Description: + * Register serial console and serial ports. This assumes + * that mips_earlyserialinit was called previously. + * + ****************************************************************************/ + +void mips_serialinit(void) +{ + u16550_serialinit(); +} + +/**************************************************************************** + * Name: jz_physramaddr + * + * Description: + * Given the virtual address of a RAM memory location, return the physical + * address of that location. + * + ****************************************************************************/ + +uintptr_t jz_physramaddr(uintptr_t virtramaddr) +{ + return virtramaddr & 0x1fffffff; +} + +/**************************************************************************** + * Name: jz_virtramaddr + * + * Description: + * Give the physical address of a RAM memory location, return the virtual + * address of that location. + * + ****************************************************************************/ + +uintptr_t jz_virtramaddr(uintptr_t physramaddr) +{ + if ((physramaddr & 0xffffffe0) == 0) + { + return 0; + } + + return 0x80000000 | physramaddr; +} + +#if CONFIG_MM_REGIONS > 1 +void mips_addregion(void) +{ +} +#endif diff --git a/arch/mips/src/jz4780/jz4780_lowinit.h b/arch/mips/src/jz4780/jz4780_lowinit.h new file mode 100644 index 0000000000000..b7b5691857154 --- /dev/null +++ b/arch/mips/src/jz4780/jz4780_lowinit.h @@ -0,0 +1,89 @@ +/***************************************************************************** + * arch/mips/src/jz4780/jz4780_lowinit.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + *****************************************************************************/ + +#ifndef __ARCH_MIPS_SRC_JZ4780_JZ4780_LOWINIT_H +#define __ARCH_MIPS_SRC_JZ4780_JZ4780_LOWINIT_H + +/***************************************************************************** + * Included Files + *****************************************************************************/ + +#include +#include + +#include +#include "mips_internal.h" + +/***************************************************************************** + * Pre-processor Definitions + *****************************************************************************/ + +/***************************************************************************** + * Public Types + *****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/***************************************************************************** + * Public Data + *****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/***************************************************************************** + * Public Function Prototypes + *****************************************************************************/ + +/***************************************************************************** + * Name: jz4780_lowinit + * + * Description: + * This performs basic low-level initialization of the system. + * + *****************************************************************************/ + +void jz4780_lowinit(void); + +/***************************************************************************** + * Name: jz4780_boardinitialize + * + * Description: + * This function must be provided by the board-specific logic + * + *****************************************************************************/ + +void jz4780_boardinitialize(void); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_MIPS_SRC_JZ4780_JZ4780_LOWINIT_H */ diff --git a/arch/mips/src/jz4780/jz4780_timerisr.c b/arch/mips/src/jz4780/jz4780_timerisr.c new file mode 100644 index 0000000000000..ceb633edb430f --- /dev/null +++ b/arch/mips/src/jz4780/jz4780_timerisr.c @@ -0,0 +1,152 @@ +/**************************************************************************** + * arch/mips/src/jz4780/jz4780_timerisr.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "clock/clock.h" +#include "mips_internal.h" + +#include "mips_internal.h" +#include "jz4780_lowinit.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static void reboot_s(int sec) +{ + putreg8(0, WD_TCER); + putreg16(0, WD_TCNT); + putreg16(32*sec, WD_TDR); + putreg16(TCSR_PRESCALE(5) | TCSR_RTC_EN, WD_TCSR); + putreg8(TCER_TCEN, WD_TCER); + + for (; ; ) + { + } +} + +/**************************************************************************** + * Function: jzjz_timerisr + * + * Description: + * The timer ISR will perform a variety of services for various portions + * of the systems. + * + ****************************************************************************/ + +static int jz_timerisr(int irq, uint32_t *regs, void *arg) +{ + /* Clear the pending timer interrupt */ + + mips_clrpend_irq(JZ4780_IRQ_TCU0); + + putreg32(TFCR_OSTFCL, TFCR); + + /* Process timer interrupt */ + + nxsched_process_timer(); + return 0; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: mips_timer_initialize + * + * Description: + * This function is called during start-up to initialize + * the timer interrupt. + * + ****************************************************************************/ + +void up_timer_initialize(void) +{ + putreg32(0, OSTCNTL); + putreg32(0, OSTCNTH); + + putreg16(TCSR_PRESCALE(TCSR_DIV_16) | TCSR_EXT_EN, OSTCSR); + + putreg32(TICKS_PER_MS * CONFIG_USEC_PER_TICK / 1000, OSTDR); + + putreg32(TESR_OSTEN, TESR); + putreg32(TMCR_OSTMCL, TMCR); + + /* Configure the timer interrupt */ + + mips_clrpend_irq(JZ4780_IRQ_TCU0); + + /* Attach the timer interrupt vector */ + + (void)irq_attach(JZ4780_IRQ_TCU0, (xcpt_t)jz_timerisr, NULL); + + /* And enable the timer interrupt */ + + up_enable_irq(JZ4780_IRQ_TCU0); +} + +#ifdef CONFIG_BOARDCTL_RESET + +/**************************************************************************** + * Name: board_reset + * + * Description: + * Reset board. Support for this function is required by board-level + * logic if CONFIG_BOARDCTL_RESET is selected. + * + * Input Parameters: + * status - Status information provided with the reset event. This + * meaning of this status information is board-specific. If not + * used by a board, the value zero may be provided in calls to + * board_reset(). + * + * Returned Value: + * If this function returns, then it was not possible to power-off the + * board due to some constraints. The return value int this case is a + * board-specific reason for the failure to shutdown. + * + ****************************************************************************/ + +int board_reset(int status) +{ + reboot_s(1); + return 0; +} + +#endif /* CONFIG_BOARDCTL_RESET */ diff --git a/arch/mips/src/mips32/Kconfig b/arch/mips/src/mips32/Kconfig index d8ea58a360108..4269c372928d7 100644 --- a/arch/mips/src/mips32/Kconfig +++ b/arch/mips/src/mips32/Kconfig @@ -6,9 +6,14 @@ if ARCH_MIPS32 comment "MIPS32 Configuration Options" +config ALLOW_MICROCHIP_TOOLS + bool + default y if !ARCH_MIPS_XBURST1 + default n if ARCH_MIPS_XBURST1 + choice prompt "Toolchain Selection" - default MIPS32_TOOLCHAIN_MICROCHIPW_LITE if TOOLCHAIN_WINDOWS + default MIPS32_TOOLCHAIN_MICROCHIPW_LITE if TOOLCHAIN_WINDOWS && ALLOW_MICROCHIP_TOOLS default MIPS32_TOOLCHAIN_GNU_ELF if !TOOLCHAIN_WINDOWS config MIPS32_TOOLCHAIN_GNU_ELF @@ -20,51 +25,51 @@ config MIPS32_TOOLCHAIN_GNU_ELF config MIPS32_TOOLCHAIN_MICROCHIPL_XC32 bool "Microchip XC32 toolchain under Linux" - depends on HOST_LINUX + depends on HOST_LINUX && ALLOW_MICROCHIP_TOOLS select ARCH_TOOLCHAIN_GNU config MIPS32_TOOLCHAIN_MICROCHIPL bool "Microchip C32 toolchain under Linux" - depends on HOST_LINUX + depends on HOST_LINUX && ALLOW_MICROCHIP_TOOLS select ARCH_TOOLCHAIN_GNU config MIPS32_TOOLCHAIN_MICROCHIPL_LITE bool "Microchip C32 toolchain under Linux (Lite edition)" - depends on HOST_LINUX + depends on HOST_LINUX && ALLOW_MICROCHIP_TOOLS select ARCH_TOOLCHAIN_GNU config MIPS32_TOOLCHAIN_MICROCHIPW_XC32 bool "Microchip XC32 toolchain under Windows" - depends on TOOLCHAIN_WINDOWS + depends on TOOLCHAIN_WINDOWS && ALLOW_MICROCHIP_TOOLS select CYGWIN_WINTOOL if WINDOWS_CYGWIN select ARCH_TOOLCHAIN_GNU config MIPS32_TOOLCHAIN_MICROCHIPW bool "Microchip C32 toolchain under Windows" - depends on TOOLCHAIN_WINDOWS + depends on TOOLCHAIN_WINDOWS && ALLOW_MICROCHIP_TOOLS select CYGWIN_WINTOOL if WINDOWS_CYGWIN select ARCH_TOOLCHAIN_GNU config MIPS32_TOOLCHAIN_MICROCHIPW_LITE bool "Microchip C32 toolchain under Windows (Lite edition)" - depends on TOOLCHAIN_WINDOWS + depends on TOOLCHAIN_WINDOWS && ALLOW_MICROCHIP_TOOLS select CYGWIN_WINTOOL if WINDOWS_CYGWIN select ARCH_TOOLCHAIN_GNU config MIPS32_TOOLCHAIN_MICROCHIPOPENL bool "microchipOpen toolchain under Linux" - depends on HOST_LINUX + depends on HOST_LINUX && ALLOW_MICROCHIP_TOOLS select ARCH_TOOLCHAIN_GNU config MIPS32_TOOLCHAIN_PINGUINOW bool "Pinguino mips-elf toolchain under Windows" - depends on TOOLCHAIN_WINDOWS + depends on TOOLCHAIN_WINDOWS && ALLOW_MICROCHIP_TOOLS select CYGWIN_WINTOOL if WINDOWS_CYGWIN select ARCH_TOOLCHAIN_GNU config MIPS32_TOOLCHAIN_PINGUINOL bool "Pinguino mips-elf toolchain under macOS or Linux" - depends on HOST_LINUX || HOST_MACOS + depends on (HOST_LINUX || HOST_MACOS) && ALLOW_MICROCHIP_TOOLS select ARCH_TOOLCHAIN_GNU config MIPS32_TOOLCHAIN_SOURCERY_CODEBENCH_LITE @@ -96,6 +101,10 @@ config MIPS32_USE_SYSCALL_INSTRUCTION bool default n +config MIPS32_USE_WAIT_INSTRUCTION + bool + default n + config MIPS32_HAVE_ICACHE bool default n diff --git a/boards/Kconfig b/boards/Kconfig index c9be61afe4416..dc2c9e13c3c71 100644 --- a/boards/Kconfig +++ b/boards/Kconfig @@ -127,6 +127,13 @@ config ARCH_BOARD_C5471EVM NuttX runs on the ARM core and is built with a GNU arm-nuttx-elf toolchain*. This port is complete and verified. +config ARCH_BOARD_CI20 + bool "MIPS Creator CI20" + depends on ARCH_CHIP_JZ4780 + select BOARDCTL_RESET + ---help--- + This MIPS Creator CI20 port is incomplete. + config ARCH_BOARD_CIRCUIT_EXPRESS bool "Adafruit Circuit Express" depends on ARCH_CHIP_SAMD21G18A @@ -3693,6 +3700,7 @@ config ARCH_BOARD default "bambino-200e" if ARCH_BOARD_BAMBINO_200E default "bl602evb" if ARCH_BOARD_BL602EVB default "c5471evm" if ARCH_BOARD_C5471EVM + default "ci20" if ARCH_BOARD_CI20 default "circuit-express" if ARCH_BOARD_CIRCUIT_EXPRESS default "clicker2-stm32" if ARCH_BOARD_CLICKER2_STM32 default "cloudctrl" if ARCH_BOARD_CLOUDCTRL @@ -4119,6 +4127,9 @@ endif if ARCH_BOARD_C5471EVM source "boards/arm/c5471/c5471evm/Kconfig" endif +if ARCH_BOARD_CI20 +source "boards/mips/jz4780/ci20/Kconfig" +endif if ARCH_BOARD_SPRESENSE source "boards/arm/cxd56xx/spresense/Kconfig" endif @@ -5651,7 +5662,7 @@ config BOARD_ETC_ROMFS_PASSWD_RANDOMIZE_KEYS Application Configuration -> File System Utilities -> Password file support. -comment " If not randomizing: set KEY1..4 at App Config -> File System Utilities -> Password file support" +comment "If not randomizing: set KEY1..4 at App Config -> File System Utilities -> Password file support" depends on !BOARD_ETC_ROMFS_PASSWD_RANDOMIZE_KEYS config BOARD_ETC_ROMFS_PASSWD_UID diff --git a/boards/mips/jz4780/ci20/Kconfig b/boards/mips/jz4780/ci20/Kconfig new file mode 100644 index 0000000000000..078d0af7de6b8 --- /dev/null +++ b/boards/mips/jz4780/ci20/Kconfig @@ -0,0 +1,7 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_CI20 +endif diff --git a/boards/mips/jz4780/ci20/configs/nsh/defconfig b/boards/mips/jz4780/ci20/configs/nsh/defconfig new file mode 100644 index 0000000000000..0832ef1dfd85e --- /dev/null +++ b/boards/mips/jz4780/ci20/configs/nsh/defconfig @@ -0,0 +1,69 @@ +# +# This file is autogenerated: PLEASE DO NOT EDIT IT. +# +# You can use "make menuconfig" to make any modifications to the installed .config file. +# You can then do "make savedefconfig" to generate a new defconfig file that includes your +# modifications. +# +# CONFIG_NDEBUG is not set +CONFIG_16550_ADDRWIDTH=32 +CONFIG_16550_REGWIDTH=32 +CONFIG_16550_SUPRESS_CONFIG=y +CONFIG_16550_UART0=y +CONFIG_16550_UART0_BASE=0xB0030000 +CONFIG_16550_UART0_CLOCK=14745600 +CONFIG_16550_UART0_IRQ=51 +CONFIG_16550_UART0_SERIAL_CONSOLE=y +CONFIG_16550_UART=y +CONFIG_ARCH="mips" +CONFIG_ARCH_BOARD="ci20" +CONFIG_ARCH_BOARD_CI20=y +CONFIG_ARCH_CHIP="jz4780" +CONFIG_ARCH_CHIP_JZ4780=y +CONFIG_ARCH_MIPS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_BOARD_LOOPSPERMSEC=72450 +CONFIG_BUILTIN=y +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_FS=y +CONFIG_DEBUG_FS_ERROR=y +CONFIG_DEBUG_FS_WARN=y +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_FAT_LCNAMES=y +CONFIG_FAT_LFN=y +CONFIG_FS_FAT=y +CONFIG_FS_PROCFS=y +CONFIG_GRAN=y +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_INIT_ENTRYPOINT="nsh_main" +CONFIG_MIPS32_DCACHE=y +CONFIG_MIPS32_DCACHE_SIZE=32768 +CONFIG_MIPS32_DLINE_SIZE=32 +CONFIG_MIPS32_ICACHE=y +CONFIG_MIPS32_ICACHE_SIZE=32768 +CONFIG_MIPS32_ILINE_SIZE=32 +CONFIG_MIPS32_KSEG0_IBASE=0x80000000 +CONFIG_MQ_MAXMSGSIZE=64 +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_READLINE=y +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_PREALLOC_TIMERS=4 +CONFIG_RAM_SIZE=33554432 +CONFIG_RAM_START=0x80000000 +CONFIG_READLINE_CMD_HISTORY=y +CONFIG_READLINE_TABCOMPLETION=y +CONFIG_RR_INTERVAL=200 +CONFIG_SCHED_LPWORK=y +CONFIG_SCHED_LPWORKPRIORITY=50 +CONFIG_SCHED_WAITPID=y +CONFIG_START_DAY=7 +CONFIG_START_MONTH=7 +CONFIG_START_YEAR=2026 +CONFIG_SYSTEM_NSH=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_UBOOT_UIMAGE=y +CONFIG_UIMAGE_ENTRY_POINT=0x800004AC +CONFIG_UIMAGE_LOAD_ADDRESS=0x80000180 +CONFIG_WQUEUE_NOTIFIER=y diff --git a/boards/mips/jz4780/ci20/include/board.h b/boards/mips/jz4780/ci20/include/board.h new file mode 100644 index 0000000000000..b01d367356f41 --- /dev/null +++ b/boards/mips/jz4780/ci20/include/board.h @@ -0,0 +1,69 @@ +/**************************************************************************** + * boards/mips/jz4780/ci20/include/board.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __BOARDS_MIPS_JZ4780_CI20_INCLUDE_BOARD_H +#define __BOARDS_MIPS_JZ4780_CI20_INCLUDE_BOARD_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_MIPS_JZ4780_CI20_INCLUDE_BOARD_H */ + diff --git a/boards/mips/jz4780/ci20/scripts/Make.defs b/boards/mips/jz4780/ci20/scripts/Make.defs new file mode 100644 index 0000000000000..8ce44d506f0bf --- /dev/null +++ b/boards/mips/jz4780/ci20/scripts/Make.defs @@ -0,0 +1,38 @@ +############################################################################ +# boards/mips/jz4780/ci20/scripts/Make.defs +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +include $(TOPDIR)/.config +include $(TOPDIR)/tools/Config.mk +include $(TOPDIR)/arch/mips/src/mips32/Toolchain.defs + +LDSCRIPT = mips-debug.ld + +ARCHSCRIPT += $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT) + +CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) +AFLAGS := $(CFLAGS) -D__ASSEMBLY__ + +CFLAGS += -Wno-format -G 0 diff --git a/boards/mips/jz4780/ci20/scripts/mips-debug.ld b/boards/mips/jz4780/ci20/scripts/mips-debug.ld new file mode 100644 index 0000000000000..d99172a9be3e4 --- /dev/null +++ b/boards/mips/jz4780/ci20/scripts/mips-debug.ld @@ -0,0 +1,215 @@ +/**************************************************************************** + * boards/mips/jz4780/ci20/scripts/mips-debug.ld + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/* Memory Regions ***********************************************************/ + +MEMORY +{ + kseg0_progmem (rx) : ORIGIN = 0x80020000, LENGTH = 32M + + kseg0_genexcpt (rx) : ORIGIN = 0x80000180, LENGTH = 128 + kseg0_ebexcpt0 (rx) : ORIGIN = 0x80000200, LENGTH = 32 + kseg0_ebexcpt1 (rx) : ORIGIN = 0x80000220, LENGTH = 32 + kseg0_ebexcpt2 (rx) : ORIGIN = 0x80000240, LENGTH = 32 + kseg0_ebexcpt3 (rx) : ORIGIN = 0x80000260, LENGTH = 32 + kseg0_ebexcpt4 (rx) : ORIGIN = 0x80000280, LENGTH = 32 + kseg0_ebexcpt5 (rx) : ORIGIN = 0x800002A0, LENGTH = 32 + kseg0_ebexcpt6 (rx) : ORIGIN = 0x800002C0, LENGTH = 32 + kseg0_ebexcpt7 (rx) : ORIGIN = 0x800002E0, LENGTH = 32 + kseg0_bevexcpt (rx) : ORIGIN = 0x80000380, LENGTH = 128 + kseg0_intexcpt (rx) : ORIGIN = 0x80000400, LENGTH = 128 + kseg0_dbgexcpt (rx) : ORIGIN = 0x80000480, LENGTH = 16 + kseg0_bootmem (rx) : ORIGIN = 0x800004ac, LENGTH = 8192-1196 +} + +OUTPUT_FORMAT("elf32-tradlittlemips") +OUTPUT_ARCH(mips) +ENTRY(__start) + +SECTIONS +{ + .gen_excpt : + { + KEEP (*(.gen_excpt)) + } > kseg0_genexcpt + + .ebase_excpt : + { + KEEP (*(.ebase_excpt)) + } > kseg0_ebexcpt0 + + .ebase_excpt1 : + { + KEEP (*(.ebase_excpt1)) + } > kseg0_ebexcpt1 + + .ebase_excpt2 : + { + KEEP (*(.ebase_excpt2)) + } > kseg0_ebexcpt2 + + .bev_excpt : + { + KEEP (*(.bev_excpt)) + } > kseg0_bevexcpt + + .int_excpt : + { + KEEP (*(.int_excpt)) + } > kseg0_intexcpt + + .dbg_excpt = ORIGIN(kseg0_dbgexcpt); + + .start : + { + /* KSEG0 Reset startup logic */ + + *(.start) + + /* KSEG0 exception handlers */ + + *(.nmi_handler) + *(.bev_handler) + *(.int_handler) + *(.swint_handler) + } > kseg0_bootmem + + /* Program FLASH sections */ + + .text : + { + _stext = ABSOLUTE(.); + *(.text .text.*) + *(.stub) + KEEP (*(.text.*personality*)) + *(.gnu.linkonce.t.*) + *(.gnu.warning) + *(.mips16.fn.*) + *(.mips16.call.*) + + /* Read-only data is included in the text section */ + + *(.rodata .rodata.*) + *(.rodata1) + *(.gnu.linkonce.r.*) + + /* Small initialized constant global and static data */ + + *(.sdata2 .sdata2.*) + *(.gnu.linkonce.s2.*) + + /* Uninitialized constant global and static data */ + + *(.sbss2 .sbss2.*) + *(.gnu.linkonce.sb2.*) + _etext = ABSOLUTE(.); + } > kseg0_progmem + + /* Initialization data begins here in progmem */ + + _data_loaddr = LOADADDR(.data); + + .eh_frame_hdr : { *(.eh_frame_hdr) *(.eh_frame_entry .eh_frame_entry.*) } + .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) } + + .data : + { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + KEEP (*(.gnu.linkonce.d.*personality*)) + *(.data1) + } > kseg0_progmem + + .eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) } + _gp = ALIGN(16) + 0x7FF0 ; + + .got : + { + *(.got.plt) *(.got) + } > kseg0_progmem + + .sdata : + { + *(.sdata .sdata.* .gnu.linkonce.s.*) + _edata = ABSOLUTE(.); + } > kseg0_progmem + + .bss : + { + _sbss = ABSOLUTE(.); + *(.dynsbss) + *(.sbss .sbss.* .gnu.linkonce.sb.*) + *(.scommon) + *(.dynbss) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(0x8); + _ebss = ABSOLUTE(.); + } > kseg0_progmem + + /* Stabs debugging sections */ + + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + + /* DWARF debug sections */ + /* DWARF 1 */ + + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + + /* GNU DWARF 1 extensions */ + + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + + /* DWARF 1.1 and DWARF 2 */ + + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + + /* DWARF 2 */ + + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + + /* SGI/MIPS DWARF 2 extensions */ + + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + + /DISCARD/ : { *(.note.GNU-stack) } +} diff --git a/boards/mips/jz4780/ci20/src/.gitignore b/boards/mips/jz4780/ci20/src/.gitignore new file mode 100644 index 0000000000000..726d936e1e339 --- /dev/null +++ b/boards/mips/jz4780/ci20/src/.gitignore @@ -0,0 +1,2 @@ +/.depend +/Make.dep diff --git a/boards/mips/jz4780/ci20/src/Makefile b/boards/mips/jz4780/ci20/src/Makefile new file mode 100644 index 0000000000000..75e98ad71421e --- /dev/null +++ b/boards/mips/jz4780/ci20/src/Makefile @@ -0,0 +1,28 @@ +############################################################################ +# boards/mips/jz4780/ci20/src/Makefile +# +# SPDX-License-Identifier: Apache-2.0 +# +# Licensed to the Apache Software Foundation (ASF) under one or more +# contributor license agreements. See the NOTICE file distributed with +# this work for additional information regarding copyright ownership. The +# ASF licenses this file to you under the Apache License, Version 2.0 (the +# "License"); you may not use this file except in compliance with the +# License. You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the +# License for the specific language governing permissions and limitations +# under the License. +# +############################################################################ + +-include $(TOPDIR)/Make.defs + +ASRCS = +CSRCS = jz4780_boot.c jz4780_bringup.c + +include $(TOPDIR)/boards/Board.mk diff --git a/boards/mips/jz4780/ci20/src/ci20.h b/boards/mips/jz4780/ci20/src/ci20.h new file mode 100644 index 0000000000000..95c4d365ddf17 --- /dev/null +++ b/boards/mips/jz4780/ci20/src/ci20.h @@ -0,0 +1,108 @@ +/**************************************************************************** + * boards/mips/jz4780/ci20/src/ci20.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifndef __BOARDS_MIPS_JZ4780_CI20_SRC_CI20_H +#define __BOARDS_MIPS_JZ4780_CI20_SRC_CI20_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* LEDs *********************************************************************/ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Inline Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: jz4780_led_initialize + * + * Description: + * Configure on-board LEDs if LED support has been selected. + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_LEDS +void jz4780_led_initialize(void); +#endif + +/**************************************************************************** + * Name: jz4780_bringup + * + * Description: + * Bring up board features + * + ****************************************************************************/ + +int jz4780_bringup(void); + +/**************************************************************************** + * Name: jz_dma_alloc_init + * + * Description: + * Called to create a FAT DMA allocator + * + * Returned Value: + * 0 on success or -ENOMEM + * + ****************************************************************************/ + +#if defined (CONFIG_FAT_DMAMEMORY) +int jz_dma_alloc_init(void); +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __BOARDS_MIPS_JZ4780_CI20_SRC_CI20_H */ diff --git a/boards/mips/jz4780/ci20/src/jz4780_boot.c b/boards/mips/jz4780/ci20/src/jz4780_boot.c new file mode 100644 index 0000000000000..4c9f7ac633ca0 --- /dev/null +++ b/boards/mips/jz4780/ci20/src/jz4780_boot.c @@ -0,0 +1,84 @@ +/**************************************************************************** + * boards/mips/jz4780/ci20/src/jz4780_boot.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include + +#include "ci20.h" +#include "hardware/jz4780_pinmap.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: jz4780_boardinitialize + * + * Description: + * This entry point is called early in the initialization after all memory + * has been configured and mapped but before any devices have been + * initialized. + * + ****************************************************************************/ + +void jz4780_boardinitialize(void) +{ +} + +/**************************************************************************** + * Name: board_late_initialize + * + * Description: + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will be + * called immediately after up_initialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_LATE_INITIALIZE +void board_late_initialize(void) +{ + /* Perform board initialization */ + + jz4780_bringup(); +} +#endif /* CONFIG_BOARD_LATE_INITIALIZE */ diff --git a/boards/mips/jz4780/ci20/src/jz4780_bringup.c b/boards/mips/jz4780/ci20/src/jz4780_bringup.c new file mode 100644 index 0000000000000..7282d79cad475 --- /dev/null +++ b/boards/mips/jz4780/ci20/src/jz4780_bringup.c @@ -0,0 +1,82 @@ +/**************************************************************************** + * boards/mips/jz4780/ci20/src/jz4780_bringup.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include + +#include "ci20.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: jz4780_bringup + * + * Description: + * Bring up board features + * + ****************************************************************************/ + +int jz4780_bringup(void) +{ + int ret = OK; + +#ifdef CONFIG_FS_PROCFS + /* Mount the procfs file system */ + + ret = nx_mount(NULL, "/proc", "procfs", 0, NULL); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n", + ret); + } +#endif + + return ret; +} diff --git a/boards/mips/jz4780/drivers/Kconfig b/boards/mips/jz4780/drivers/Kconfig new file mode 100644 index 0000000000000..f72f3c094ce4c --- /dev/null +++ b/boards/mips/jz4780/drivers/Kconfig @@ -0,0 +1,4 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# diff --git a/drivers/serial/uart_16550.c b/drivers/serial/uart_16550.c index 6278cab0728c2..d51574ad310bf 100644 --- a/drivers/serial/uart_16550.c +++ b/drivers/serial/uart_16550.c @@ -1583,7 +1583,8 @@ static void u16550_send(struct uart_dev_s *dev, int ch) static ssize_t u16550_sendbuf(struct uart_dev_s *dev, const void *buffer, size_t size) { - for (size_t i = 0; i < size; i++) + size_t i; + for (i = 0; i < size; i++) { while (!u16550_txready(dev)); u16550_send(dev, ((const unsigned char *)buffer)[i]); diff --git a/mm/mm_gran/mm_grantable.c b/mm/mm_gran/mm_grantable.c index 4fc78949a3601..70c61786b3ee8 100644 --- a/mm/mm_gran/mm_grantable.c +++ b/mm/mm_gran/mm_grantable.c @@ -260,6 +260,7 @@ bool gran_match(const gran_t *gran, size_t posi, size_t size, bool used, int gran_search(const gran_t *gran, size_t size) { int ret = -EINVAL; + size_t i; if (gran == NULL || gran->ngranules < size) { @@ -267,7 +268,7 @@ int gran_search(const gran_t *gran, size_t size) } ret = -ENOMEM; - for (size_t i = 0; i <= gran->ngranules - size; i++) + for (i = 0; i <= gran->ngranules - size; i++) { if (gran_match(gran, i, size, 0, &i)) {