diff --git a/arch/risc-v/src/common/espressif/Make.defs b/arch/risc-v/src/common/espressif/Make.defs index 83b63741cfb90..f1d10a6439c9b 100644 --- a/arch/risc-v/src/common/espressif/Make.defs +++ b/arch/risc-v/src/common/espressif/Make.defs @@ -207,7 +207,7 @@ endif ESP_HAL_3RDPARTY_REPO = esp-hal-3rdparty ifndef ESP_HAL_3RDPARTY_VERSION - ESP_HAL_3RDPARTY_VERSION = a85ce2f1bad9f745090146eb30a18d91b8ddd309 + ESP_HAL_3RDPARTY_VERSION = 6c272b562a73107a852d44b9c6fb5df57245cbd7 endif ifndef ESP_HAL_3RDPARTY_URL diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig index bc148aec0737d..5f25569d86687 100644 --- a/arch/xtensa/Kconfig +++ b/arch/xtensa/Kconfig @@ -22,6 +22,7 @@ config ARCH_CHIP_ESP32 select ARCH_HAVE_TESTSET select ARCH_HAVE_TEXT_HEAP select ARCH_VECNOTIRQ + select ARCH_MINIMAL_VECTORTABLE select LIBC_PREVENT_STRING_KERNEL select LIBC_ARCH_MEMCPY if BUILD_FLAT select LIBC_ARCH_MEMCHR if BUILD_FLAT @@ -56,6 +57,7 @@ config ARCH_CHIP_ESP32S2 select ARCH_HAVE_RESET select ARCH_HAVE_TEXT_HEAP select ARCH_VECNOTIRQ + select ARCH_MINIMAL_VECTORTABLE select LIBC_ARCH_MEMCPY select LIBC_ARCH_MEMCHR select LIBC_ARCH_MEMCMP @@ -92,6 +94,7 @@ config ARCH_CHIP_ESP32S3 select ARCH_DCACHE select ARCH_ICACHE select ARCH_VECNOTIRQ + select ARCH_MINIMAL_VECTORTABLE select LIBC_PREVENT_STRING_KERNEL select LIBC_ARCH_MEMCPY if BUILD_FLAT select LIBC_ARCH_MEMCHR if BUILD_FLAT diff --git a/arch/xtensa/include/esp32/irq.h b/arch/xtensa/include/esp32/irq.h index 3bc5270d6a6ef..6d603dbb55598 100644 --- a/arch/xtensa/include/esp32/irq.h +++ b/arch/xtensa/include/esp32/irq.h @@ -39,7 +39,7 @@ /* CPU interrupt flags: * These flags can be used to specify which interrupt qualities the - * code calling esp32_setup_irq needs. + * code calling esp_setup_irq needs. */ #define ESP32_CPUINT_FLAG_LEVEL (1 << 0) /* Level-triggered interrupt */ @@ -190,24 +190,39 @@ */ /* IRQ numbers for internal interrupts that are dispatched like peripheral - * interrupts + * interrupts. These use negative source IDs for internal CPU interrupts. */ +#define ETS_INTERNAL_TIMER0_INTR_SOURCE -1 /* Platform timer 0 interrupt source */ +#define ETS_INTERNAL_TIMER1_INTR_SOURCE -2 /* Platform timer 1 interrupt source */ +#define ETS_INTERNAL_TIMER2_INTR_SOURCE -3 /* Platform timer 2 interrupt source */ +#define ETS_INTERNAL_SW0_INTR_SOURCE -4 /* Software int source 1 */ +#define ETS_INTERNAL_SW1_INTR_SOURCE -5 /* Software int source 2 */ +#define ETS_INTERNAL_PROFILING_INTR_SOURCE -6 /* Int source for profiling */ + +#define ETS_INTERNAL_INTR_SOURCE_OFF (-ETS_INTERNAL_PROFILING_INTR_SOURCE) + +#define XTENSA_NIRQ_INTERNAL ETS_INTERNAL_INTR_SOURCE_OFF /* Number of dispatch internal interrupts */ +#define XTENSA_IRQ_DEMUX ETS_INTERNAL_INTR_SOURCE_OFF + 0 /* Demultiplexing IRQ for peripheral interrupts */ +#define XTENSA_IRQ_SYSCALL ETS_INTERNAL_INTR_SOURCE_OFF + 1 /* User interrupt w/EXCCAUSE=syscall */ +#define XTENSA_IRQ_FIRSTPERIPH ETS_INTERNAL_INTR_SOURCE_OFF + 2 /* First peripheral IRQ number */ + +/* Legacy definitions for compatibility */ + #define XTENSA_IRQ_TIMER0 0 /* INTERRUPT, bit 6 */ #define XTENSA_IRQ_TIMER1 1 /* INTERRUPT, bit 15 */ #define XTENSA_IRQ_TIMER2 2 /* INTERRUPT, bit 16 */ -#define XTENSA_IRQ_SYSCALL 3 /* User interrupt w/EXCCAUSE=syscall */ #define XTENSA_IRQ_SWINT 4 /* Software interrupt */ -#define XTENSA_NIRQ_INTERNAL 5 /* Number of dispatch internal interrupts */ -#define XTENSA_IRQ_FIRSTPERIPH 5 /* First peripheral IRQ number */ - /* IRQ numbers for peripheral interrupts coming through the Interrupt * Matrix. */ -#define ESP32_IRQ2PERIPH(irq) ((irq)-XTENSA_IRQ_FIRSTPERIPH) -#define ESP32_PERIPH2IRQ(id) ((id)+XTENSA_IRQ_FIRSTPERIPH) +#define ESP32_IRQ2PERIPH(irq) ((irq) - XTENSA_IRQ_FIRSTPERIPH) +#define ESP32_PERIPH2IRQ(id) ((id) + XTENSA_IRQ_FIRSTPERIPH) + +#define ESP_IRQ2SOURCE(irq) ESP32_IRQ2PERIPH(irq) +#define ESP_SOURCE2IRQ(id) ESP32_PERIPH2IRQ(id) /* PRO_INTR_STATUS_REG_0 / APP_INTR_STATUS_REG_0 */ @@ -299,7 +314,7 @@ #define ESP32_NIRQ_PERIPH ESP32_NPERIPHERALS -#ifdef CONFIG_ESP32_GPIO_IRQ +#ifdef CONFIG_ESPRESSIF_GPIO_IRQ /* The PRO and APP CPU have different interrupts sources for the GPIO * peripheral. Each CPU needs to allocate a separate interrupt and attach @@ -325,6 +340,8 @@ # define ESP32_LAST_GPIOIRQ (ESP32_FIRST_GPIOIRQ+ESP32_NIRQ_GPIO-1) # define ESP32_PIN2IRQ(p) ((p) + ESP32_FIRST_GPIOIRQ) # define ESP32_IRQ2PIN(i) ((i) - ESP32_FIRST_GPIOIRQ) +# define ESP_PIN2IRQ(p) ESP32_PIN2IRQ(p) +# define ESP_IRQ2PIN(i) ESP32_IRQ2PIN(i) #else # define ESP32_NIRQ_GPIO 0 #endif @@ -477,7 +494,7 @@ * Inline functions ****************************************************************************/ -#ifdef CONFIG_ESP32_GPIO_IRQ +#ifdef CONFIG_ESPRESSIF_GPIO_IRQ #ifdef CONFIG_SMP static inline_function int esp32_irq_gpio(int cpu) { diff --git a/arch/xtensa/include/esp32s2/irq.h b/arch/xtensa/include/esp32s2/irq.h index 8a96597f21146..d5b31d268c63b 100644 --- a/arch/xtensa/include/esp32s2/irq.h +++ b/arch/xtensa/include/esp32s2/irq.h @@ -197,14 +197,19 @@ * interrupts */ -#define XTENSA_IRQ_TIMER0 0 /* INTERRUPT, bit 6 */ -#define XTENSA_IRQ_TIMER1 1 /* INTERRUPT, bit 15 */ -#define XTENSA_IRQ_TIMER2 2 /* INTERRUPT, bit 16 */ -#define XTENSA_IRQ_SYSCALL 3 /* User interrupt w/EXCCAUSE=syscall */ -#define XTENSA_IRQ_SWINT 4 /* Software interrupt */ +#define ETS_INTERNAL_TIMER0_INTR_SOURCE -1 /* Platform timer 0 interrupt source */ +#define ETS_INTERNAL_TIMER1_INTR_SOURCE -2 /* Platform timer 1 interrupt source */ +#define ETS_INTERNAL_TIMER2_INTR_SOURCE -3 /* Platform timer 2 interrupt source */ +#define ETS_INTERNAL_SW0_INTR_SOURCE -4 /* Software int source 1 */ +#define ETS_INTERNAL_SW1_INTR_SOURCE -5 /* Software int source 2 */ +#define ETS_INTERNAL_PROFILING_INTR_SOURCE -6 /* Int source for profiling */ -#define XTENSA_NIRQ_INTERNAL 5 /* Number of dispatch internal interrupts */ -#define XTENSA_IRQ_FIRSTPERIPH 5 /* First peripheral IRQ number */ +#define ETS_INTERNAL_INTR_SOURCE_OFF (-ETS_INTERNAL_PROFILING_INTR_SOURCE) + +#define XTENSA_NIRQ_INTERNAL ETS_INTERNAL_INTR_SOURCE_OFF /* Number of dispatch internal interrupts */ +#define XTENSA_IRQ_DEMUX ETS_INTERNAL_INTR_SOURCE_OFF + 0 /* Demultiplexing IRQ for peripheral interrupts */ +#define XTENSA_IRQ_SYSCALL ETS_INTERNAL_INTR_SOURCE_OFF + 1 /* User interrupt w/EXCCAUSE=syscall */ +#define XTENSA_IRQ_FIRSTPERIPH ETS_INTERNAL_INTR_SOURCE_OFF + 2 /* First peripheral IRQ number */ /* IRQ numbers for peripheral interrupts coming through the Interrupt * Matrix. @@ -213,6 +218,9 @@ #define ESP32S2_IRQ2PERIPH(irq) ((irq) - XTENSA_IRQ_FIRSTPERIPH) #define ESP32S2_PERIPH2IRQ(id) ((id) + XTENSA_IRQ_FIRSTPERIPH) +#define ESP_IRQ2SOURCE(irq) ESP32S2_IRQ2PERIPH(irq) +#define ESP_SOURCE2IRQ(id) ESP32S2_PERIPH2IRQ(id) + #define ESP32S2_IRQ_MAC (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_MAC) #define ESP32S2_IRQ_MAC_NMI (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_PERIPH_MAC_NMI) @@ -304,12 +312,14 @@ * interrupt handler. The second to the decoded GPIO interrupt handler. */ -#ifdef CONFIG_ESP32S2_GPIO_IRQ +#ifdef CONFIG_ESPRESSIF_GPIO_IRQ # define ESP32S2_NIRQ_GPIO 47 # define ESP32S2_FIRST_GPIOIRQ (XTENSA_NIRQ_INTERNAL + ESP32S2_NIRQ_PERIPH) # define ESP32S2_LAST_GPIOIRQ (ESP32S2_FIRST_GPIOIRQ + ESP32S2_NIRQ_GPIO - 1) # define ESP32S2_PIN2IRQ(p) ((p) + ESP32S2_FIRST_GPIOIRQ) # define ESP32S2_IRQ2PIN(i) ((i) - ESP32S2_FIRST_GPIOIRQ) +# define ESP_PIN2IRQ(p) ESP32S2_PIN2IRQ(p) +# define ESP_IRQ2PIN(i) ESP32S2_IRQ2PIN(i) #else # define ESP32S2_NIRQ_GPIO 0 #endif @@ -360,7 +370,7 @@ /* Total number of interrupts */ -#define NR_IRQS (XTENSA_NIRQ_INTERNAL + ESP32S2_NIRQ_PERIPH + ESP32S2_NIRQ_GPIO + ESP32S2_NIRQ_RTCIO) +#define NR_IRQS (XTENSA_IRQ_FIRSTPERIPH + ESP32S2_NIRQ_PERIPH + ESP32S2_NIRQ_GPIO + ESP32S2_NIRQ_RTCIO) /* Xtensa CPU Interrupts. * diff --git a/arch/xtensa/include/esp32s3/irq.h b/arch/xtensa/include/esp32s3/irq.h index 06de3c37e713c..efa7dd878dd47 100644 --- a/arch/xtensa/include/esp32s3/irq.h +++ b/arch/xtensa/include/esp32s3/irq.h @@ -41,7 +41,7 @@ /* CPU interrupt flags: * These flags can be used to specify which interrupt qualities the - * code calling esp32s3_setup_irq needs. + * code calling esp_setup_irq needs. */ #define ESP32S3_CPUINT_FLAG_LEVEL (1 << 0) /* Level-triggered interrupt */ @@ -156,7 +156,6 @@ #define ESP32S3_PERIPH_AES 77 #define ESP32S3_PERIPH_SHA 78 #define ESP32S3_PERIPH_INT_FROM_CPU0 79 - #define ESP32S3_PERIPH_INT_FROM_CPU1 80 #define ESP32S3_PERIPH_INT_FROM_CPU2 81 #define ESP32S3_PERIPH_INT_FROM_CPU3 82 @@ -201,14 +200,19 @@ * interrupts. */ -#define XTENSA_IRQ_TIMER0 0 /* INTERRUPT, bit 6 */ -#define XTENSA_IRQ_TIMER1 1 /* INTERRUPT, bit 15 */ -#define XTENSA_IRQ_TIMER2 2 /* INTERRUPT, bit 16 */ -#define XTENSA_IRQ_SYSCALL 3 /* User interrupt w/EXCCAUSE=syscall */ -#define XTENSA_IRQ_SWINT 4 /* Software interrupt */ +#define ETS_INTERNAL_TIMER0_INTR_SOURCE -1 /* Platform timer 0 interrupt source */ +#define ETS_INTERNAL_TIMER1_INTR_SOURCE -2 /* Platform timer 1 interrupt source */ +#define ETS_INTERNAL_TIMER2_INTR_SOURCE -3 /* Platform timer 2 interrupt source */ +#define ETS_INTERNAL_SW0_INTR_SOURCE -4 /* Software int source 1 */ +#define ETS_INTERNAL_SW1_INTR_SOURCE -5 /* Software int source 2 */ +#define ETS_INTERNAL_PROFILING_INTR_SOURCE -6 /* Int source for profiling */ + +#define ETS_INTERNAL_INTR_SOURCE_OFF (-ETS_INTERNAL_PROFILING_INTR_SOURCE) -#define XTENSA_NIRQ_INTERNAL 5 /* Number of dispatch internal interrupts */ -#define XTENSA_IRQ_FIRSTPERIPH 5 /* First peripheral IRQ number */ +#define XTENSA_NIRQ_INTERNAL ETS_INTERNAL_INTR_SOURCE_OFF /* Number of dispatch internal interrupts */ +#define XTENSA_IRQ_DEMUX ETS_INTERNAL_INTR_SOURCE_OFF + 0 /* Demultiplexing IRQ for peripheral interrupts */ +#define XTENSA_IRQ_SYSCALL ETS_INTERNAL_INTR_SOURCE_OFF + 1 /* User interrupt w/EXCCAUSE=syscall */ +#define XTENSA_IRQ_FIRSTPERIPH ETS_INTERNAL_INTR_SOURCE_OFF + 2 /* First peripheral IRQ number */ /* IRQ numbers for peripheral interrupts coming through the Interrupt * Matrix. @@ -217,6 +221,9 @@ #define ESP32S3_IRQ2PERIPH(irq) ((irq) - XTENSA_IRQ_FIRSTPERIPH) #define ESP32S3_PERIPH2IRQ(id) ((id) + XTENSA_IRQ_FIRSTPERIPH) +#define ESP_IRQ2SOURCE(irq) ESP32S3_IRQ2PERIPH(irq) +#define ESP_SOURCE2IRQ(id) ESP32S3_PERIPH2IRQ(id) + #define ESP32S3_IRQ_MAC (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_MAC) #define ESP32S3_IRQ_MAC_NMI (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_MAC_NMI) #define ESP32S3_IRQ_PWR (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_PERIPH_PWR) @@ -329,7 +336,7 @@ #define ESP32S3_NIRQ_PERIPH ESP32S3_NPERIPHERALS -#ifdef CONFIG_ESP32S3_GPIO_IRQ +#ifdef CONFIG_ESPRESSIF_GPIO_IRQ /* Second level GPIO interrupts. GPIO interrupts are decoded and dispatched * as a second level of decoding: The first level dispatches to the GPIO @@ -341,6 +348,8 @@ # define ESP32S3_LAST_GPIOIRQ (ESP32S3_FIRST_GPIOIRQ + ESP32S3_NIRQ_GPIO - 1) # define ESP32S3_PIN2IRQ(p) ((p) + ESP32S3_FIRST_GPIOIRQ) # define ESP32S3_IRQ2PIN(i) ((i) - ESP32S3_FIRST_GPIOIRQ) +# define ESP_PIN2IRQ(p) ESP32S3_PIN2IRQ(p) +# define ESP_IRQ2PIN(i) ESP32S3_IRQ2PIN(i) #else # define ESP32S3_NIRQ_GPIO 0 #endif @@ -392,7 +401,7 @@ /* Total number of interrupts */ -#define NR_IRQS (XTENSA_NIRQ_INTERNAL + ESP32S3_NIRQ_PERIPH + ESP32S3_NIRQ_GPIO + ESP32S3_NIRQ_RTCIO) +#define NR_IRQS (XTENSA_IRQ_FIRSTPERIPH + ESP32S3_NIRQ_PERIPH + ESP32S3_NIRQ_GPIO + ESP32S3_NIRQ_RTCIO) /* Xtensa CPU Interrupts. * diff --git a/arch/xtensa/src/common/espressif/Kconfig b/arch/xtensa/src/common/espressif/Kconfig index 9e3171aee1284..91c097d614e5a 100644 --- a/arch/xtensa/src/common/espressif/Kconfig +++ b/arch/xtensa/src/common/espressif/Kconfig @@ -1,3 +1,73 @@ +menu "Espressif Log Level" + visible if DEBUG_FEATURES + +config ESPRESSIF_LOG_LEVEL_NONE + bool "NONE" + depends on !DEBUG_FEATURES && !DEBUG_ERROR && !DEBUG_WARN && !DEBUG_INFO + default y + ---help--- + No log output from Espressif log messages. + +config ESPRESSIF_LOG_LEVEL_ERROR + bool "ERROR" + depends on DEBUG_ERROR + default y + ---help--- + Display critical errors from Espressif log messages. + +config ESPRESSIF_LOG_LEVEL_WARN + bool "WARN" + depends on DEBUG_WARN + default y + ---help--- + Display warning messages from Espressif log messages. + +config ESPRESSIF_LOG_LEVEL_INFO + bool "INFO" + depends on DEBUG_INFO + default y + ---help--- + Display information messages from Espressif log messages. + +config ESPRESSIF_LOG_LEVEL_DEBUG + bool "DEBUG" + depends on DEBUG_INFO + default n + ---help--- + Display extra information from Espressif log messages. + +config ESPRESSIF_LOG_LEVEL_VERBOSE + bool "VERBOSE" + depends on DEBUG_INFO + default n + ---help--- + Display bigger chunks of debugging information, or frequent messages + which can potentially flood the output from Espressif log messages. + +config ESPRESSIF_LOG_LEVEL + int + default 5 if ESPRESSIF_LOG_LEVEL_VERBOSE + default 4 if ESPRESSIF_LOG_LEVEL_DEBUG + default 3 if ESPRESSIF_LOG_LEVEL_INFO + default 2 if ESPRESSIF_LOG_LEVEL_WARN + default 1 if ESPRESSIF_LOG_LEVEL_ERROR + default 0 if ESPRESSIF_LOG_LEVEL_NONE + +endmenu # Espressif Log Level + +menu "Interrupt Configuration" + +config ESPRESSIF_IRAM_ISR_DEBUG + bool "Enable debugging of the IRAM-enabled interrupts" + default n + ---help--- + This option enables keeping track of the IRAM-enabled interrupts by + registering its execution when non-IRAM interrupts are disabled. It + keeps track of the IRQ executed and register how many times since + boot it was executed. + +endmenu # Interrupt Configuration + config ESP_RMT bool "Remote Control Module (RMT)" default n @@ -132,9 +202,9 @@ config ESPRESSIF_I2S0 select ESPRESSIF_I2S select I2S select ESP32S3_DMA if ARCH_CHIP_ESP32S3 - select ESP32S3_GPIO_IRQ if ARCH_CHIP_ESP32S3 - select ESP32S2_GPIO_IRQ if ARCH_CHIP_ESP32S2 - select ESP32_GPIO_IRQ if ARCH_CHIP_ESP32 + select ESPRESSIF_GPIO_IRQ if ARCH_CHIP_ESP32S3 + select ESPRESSIF_GPIO_IRQ if ARCH_CHIP_ESP32S2 + select ESPRESSIF_GPIO_IRQ if ARCH_CHIP_ESP32 select SCHED_HPWORK select ARCH_DMA @@ -145,8 +215,8 @@ config ESPRESSIF_I2S1 select ESPRESSIF_I2S select I2S select ESP32S3_DMA if ARCH_CHIP_ESP32S3 - select ESP32S3_GPIO_IRQ if ARCH_CHIP_ESP32S3 - select ESP32_GPIO_IRQ if ARCH_CHIP_ESP32 + select ESPRESSIF_GPIO_IRQ if ARCH_CHIP_ESP32S3 + select ESPRESSIF_GPIO_IRQ if ARCH_CHIP_ESP32 select SCHED_HPWORK select ARCH_DMA @@ -219,6 +289,12 @@ config ESPRESSIF_DEDICATED_GPIO It can work as pin grouping and you can use any pin up to 8 pins for input and 8 pins for output for dedicated gpio in total. +config ESPRESSIF_GPIO_IRQ + bool "GPIO pin interrupts" + default n + ---help--- + Enable support for interrupting GPIO pins. + config ESPRESSIF_DEDICATED_GPIO_IRQ bool "Dedicated GPIO IRQ" depends on ESPRESSIF_DEDICATED_GPIO && ARCH_CHIP_ESP32S2 @@ -520,7 +596,17 @@ endmenu # LP Core (Low-power core) Coprocessor Configuration menu "PM Configuration" -if PM && !ARCH_CHIP_ESP32 +config ESPRESSIF_AUTO_SLEEP + bool "Auto-sleep" + depends on !ARCH_CHIP_ESP32H2 + default n + select PM + select ESPRESSIF_HR_TIMER + select ESP32_TICKLESS if ARCH_CHIP_ESP32 + ---help--- + Enable Auto-sleep + +if PM config PM_EXT1_WAKEUP bool "PM EXT1 Wakeup" @@ -643,18 +729,28 @@ config PM_EXT1_WAKEUP_RTC_GPIO17 config PM_EXT1_WAKEUP_RTC_GPIO18 bool "RTC_GPIO18" + depends on ARCH_CHIP_ESP32S2 || ARCH_CHIP_ESP32S3 default n ---help--- Enable RTC GPIO18 as an EXT1 wakeup source. config PM_EXT1_WAKEUP_RTC_GPIO19 bool "RTC_GPIO19" + depends on ARCH_CHIP_ESP32S2 || ARCH_CHIP_ESP32S3 default n ---help--- Enable RTC GPIO19 as an EXT1 wakeup source. config PM_EXT1_WAKEUP_RTC_GPIO20 bool "RTC_GPIO20" + depends on ARCH_CHIP_ESP32S2 || ARCH_CHIP_ESP32S3 + default n + ---help--- + Enable RTC GPIO20 as an EXT1 wakeup source. + +config PM_EXT1_WAKEUP_RTC_GPIO21 + bool "RTC_GPIO21" + depends on ARCH_CHIP_ESP32S2 || ARCH_CHIP_ESP32S3 default n ---help--- Enable RTC GPIO20 as an EXT1 wakeup source. @@ -688,7 +784,8 @@ config PM_EXT0_WAKEUP_GPIO int "EXT0 Wakeup GPIO" depends on PM_EXT0_WAKEUP default 0 - range 0 20 + range 0 17 if ARCH_CHIP_ESP32 + range 0 21 if ARCH_CHIP_ESP32S2 || ARCH_CHIP_ESP32S3 ---help--- GPIO to wake the device up from PM_STANDBY or PM_SLEEP using as EXT0 wakeup GPIO @@ -708,6 +805,7 @@ endmenu # PM_EXT0_WAKEUP_SOURCES config PM_ULP_WAKEUP bool "PM ULP Wakeup" + depends on !ARCH_CHIP_ESP32 default n ---help--- Enable ULP coprocessor wakeup functionality. @@ -726,6 +824,12 @@ config PM_GPIO_WAKEUP menu "PM GPIO Wakeup Sources" depends on PM_GPIO_WAKEUP +config PM_GPIO_WAKEUP_GPIO0 + bool "GPIO0" + default n + ---help--- + Enable GPIO0 as an GPIO wakeup source. + config PM_GPIO_WAKEUP_GPIO1 bool "GPIO1" default n @@ -854,67 +958,175 @@ config PM_GPIO_WAKEUP_GPIO21 config PM_GPIO_WAKEUP_GPIO22 bool "GPIO22" - depends on !ARCH_CHIP_ESP32C3_GENERIC default n ---help--- Enable GPIO22 as an GPIO wakeup source. config PM_GPIO_WAKEUP_GPIO23 bool "GPIO23" - depends on !ARCH_CHIP_ESP32C3_GENERIC default n ---help--- Enable GPIO23 as an GPIO wakeup source. config PM_GPIO_WAKEUP_GPIO24 bool "GPIO24" - depends on !ARCH_CHIP_ESP32C3_GENERIC default n ---help--- Enable GPIO24 as an GPIO wakeup source. config PM_GPIO_WAKEUP_GPIO25 bool "GPIO25" - depends on !ARCH_CHIP_ESP32C3_GENERIC default n ---help--- Enable GPIO25 as an GPIO wakeup source. config PM_GPIO_WAKEUP_GPIO26 bool "GPIO26" - depends on !ARCH_CHIP_ESP32C3_GENERIC default n ---help--- Enable GPIO26 as an GPIO wakeup source. config PM_GPIO_WAKEUP_GPIO27 bool "GPIO27" - depends on !ARCH_CHIP_ESP32C3_GENERIC default n ---help--- Enable GPIO27 as an GPIO wakeup source. config PM_GPIO_WAKEUP_GPIO28 bool "GPIO28" - depends on ARCH_CHIP_ESP32C6 default n ---help--- Enable GPIO28 as an GPIO wakeup source. config PM_GPIO_WAKEUP_GPIO29 bool "GPIO29" - depends on ARCH_CHIP_ESP32C6 default n ---help--- Enable GPIO29 as an GPIO wakeup source. config PM_GPIO_WAKEUP_GPIO30 bool "GPIO30" - depends on ARCH_CHIP_ESP32C6 default n ---help--- Enable GPIO30 as an GPIO wakeup source. +config PM_GPIO_WAKEUP_GPIO31 + bool "GPIO31" + default n + ---help--- + Enable GPIO31 as an GPIO wakeup source. + +config PM_GPIO_WAKEUP_GPIO32 + bool "GPIO32" + default n + ---help--- + Enable GPIO32 as an GPIO wakeup source. + +config PM_GPIO_WAKEUP_GPIO33 + bool "GPIO33" + default n + ---help--- + Enable GPIO33 as an GPIO wakeup source. + +config PM_GPIO_WAKEUP_GPIO34 + bool "GPIO34" + default n + ---help--- + Enable GPIO34 as an GPIO wakeup source. + +config PM_GPIO_WAKEUP_GPIO35 + bool "GPIO35" + default n + ---help--- + Enable GPIO35 as an GPIO wakeup source. + +config PM_GPIO_WAKEUP_GPIO36 + bool "GPIO36" + default n + ---help--- + Enable GPIO36 as an GPIO wakeup source. + +config PM_GPIO_WAKEUP_GPIO37 + bool "GPIO37" + default n + ---help--- + Enable GPIO37 as an GPIO wakeup source. + +config PM_GPIO_WAKEUP_GPIO38 + bool "GPIO38" + default n + ---help--- + Enable GPIO38 as an GPIO wakeup source. + +config PM_GPIO_WAKEUP_GPIO39 + bool "GPIO39" + default n + ---help--- + Enable GPIO39 as an GPIO wakeup source. + +config PM_GPIO_WAKEUP_GPIO40 + bool "GPIO40" + depends on ARCH_CHIP_ESP32S2 || ARCH_CHIP_ESP32S3 + default n + ---help--- + Enable GPIO40 as an GPIO wakeup source. + +config PM_GPIO_WAKEUP_GPIO41 + bool "GPIO41" + depends on ARCH_CHIP_ESP32S2 || ARCH_CHIP_ESP32S3 + default n + ---help--- + Enable GPIO41 as an GPIO wakeup source. + +config PM_GPIO_WAKEUP_GPIO42 + bool "GPIO42" + depends on ARCH_CHIP_ESP32S2 || ARCH_CHIP_ESP32S3 + default n + ---help--- + Enable GPIO42 as an GPIO wakeup source. + +config PM_GPIO_WAKEUP_GPIO43 + bool "GPIO43" + depends on ARCH_CHIP_ESP32S2 || ARCH_CHIP_ESP32S3 + default n + ---help--- + Enable GPIO43 as an GPIO wakeup source. + +config PM_GPIO_WAKEUP_GPIO44 + bool "GPIO44" + depends on ARCH_CHIP_ESP32S2 || ARCH_CHIP_ESP32S3 + default n + ---help--- + Enable GPIO44 as an GPIO wakeup source. + +config PM_GPIO_WAKEUP_GPIO45 + bool "GPIO45" + depends on ARCH_CHIP_ESP32S2 || ARCH_CHIP_ESP32S3 + default n + ---help--- + Enable GPIO45 as an GPIO wakeup source. + +config PM_GPIO_WAKEUP_GPIO46 + bool "GPIO46" + depends on ARCH_CHIP_ESP32S2 || ARCH_CHIP_ESP32S3 + default n + ---help--- + Enable GPIO46 as an GPIO wakeup source. + +config PM_GPIO_WAKEUP_GPIO47 + bool "GPIO47" + depends on ARCH_CHIP_ESP32S3 + default n + ---help--- + Enable GPIO47 as an GPIO wakeup source. + +config PM_GPIO_WAKEUP_GPIO48 + bool "GPIO48" + depends on ARCH_CHIP_ESP32S3 + default n + ---help--- + Enable GPIO48 as an GPIO wakeup source. + choice PM_GPIO_WAKEUP_TRIGGER_MODE prompt "PM GPIO Wakeup Trigger Mode" default PM_GPIO_WAKEUP_TRIGGER_ANY_LOW @@ -931,7 +1143,7 @@ endmenu # PM_GPIO_WAKEUP_SOURCES config PM_UART_WAKEUP bool "PM UART Wakeup" - depends on ESP32S3_UART0 || ESP32S3_UART1 + depends on ESP32_UART0 || ESP32_UART1 || ESP32S3_UART0 || ESP32S3_UART1 default n ---help--- Enable UART wakeup functionality. @@ -943,15 +1155,17 @@ menu "PM UART Wakeup Sources" choice PM_UART_WAKEUP_UART_NUM prompt "PM UART Wakeup UART Number" + default PM_UART_WAKEUP_UART0 if ESP32_UART0 + default PM_UART_WAKEUP_UART1 if ESP32_UART1 default PM_UART_WAKEUP_UART0 if ESP32S3_UART0 default PM_UART_WAKEUP_UART1 if ESP32S3_UART1 config PM_UART_WAKEUP_UART0 - depends on ESP32S3_UART0 + depends on ESP32_UART0 || ESP32S3_UART0 bool "Wake the chip up when UART0 gets a data" config PM_UART_WAKEUP_UART1 - depends on ESP32S3_UART1 + depends on ESP32_UART1 || ESP32S3_UART1 bool "Wake the chip up when UART1 gets a data" endchoice # PM_UART_WAKEUP_UART_NUM @@ -986,7 +1200,7 @@ config PM_SLEEP_WAKEUP_NSEC ---help--- Number of additional nanoseconds to wait in PM_SLEEP. -endif # PM && !ARCH_CHIP_ESP32 +endif # PM endmenu # PM Configuration @@ -2262,3 +2476,12 @@ config ESPRESSIF_BLE_INTERRUPT_SAVE_STATUS Number of interrupt save status variables to keep track. Increase it if any related bug is found. endmenu # BLE Configuration + +config ESPRESSIF_HR_TIMER + bool + default RTC_DRIVER + ---help--- + A high-resolution hardware timer for supporting the management of + kernel events. + The HR Timer is built on top of the System Timer (SYSTIMER) peripheral. + Timer callbacks are dispatched from a high-priority kernel task. diff --git a/arch/xtensa/src/common/espressif/Make.defs b/arch/xtensa/src/common/espressif/Make.defs index 1b1a63efc7af9..2b6f5161a8005 100644 --- a/arch/xtensa/src/common/espressif/Make.defs +++ b/arch/xtensa/src/common/espressif/Make.defs @@ -20,6 +20,10 @@ # ############################################################################ +# Silent preprocessor warnings + +CFLAGS += -Wno-shadow -Wno-undef + ifeq ($(CONFIG_ESP_RMT),y) CHIP_CSRCS += esp_rmt.c ifeq ($(CONFIG_WS2812_NON_SPI_DRIVER),y) @@ -124,19 +128,26 @@ ifeq ($(CONFIG_ESPRESSIF_ADC),y) CHIP_CSRCS += esp_adc.c endif -ifneq ($(CONFIG_ARCH_CHIP_ESP32),y) ifeq ($(CONFIG_PM),y) ifneq ($(CONFIG_ARCH_CUSTOM_PMINIT),y) CHIP_CSRCS += esp_pm_initialize.c endif CHIP_CSRCS += esp_pm.c -LDFLAGS += -u esp_timer_init_include_func endif + +CHIP_CSRCS += esp_efuse.c esp_irq.c esp_xtensa_intr.c esp_gpio.c + +ifeq ($(CONFIG_RTC_DRIVER),y) +CHIP_CSRCS += esp_rtc.c endif -CHIP_CSRCS += esp_efuse.c +ifeq ($(CONFIG_ESPRESSIF_HR_TIMER),y) +CHIP_CSRCS += esp_timer_adapter.c +endif LDFLAGS += -u esp_system_include_startup_funcs +LDFLAGS += -u esp_timer_init_include_func + ifeq ($(CONFIG_ESPRESSIF_EFUSE),y) LDFLAGS += -u esp_efuse_startup_include_func endif diff --git a/arch/xtensa/src/common/espressif/Wireless.mk b/arch/xtensa/src/common/espressif/Wireless.mk index e8dfa5cc85094..2cab205f30215 100644 --- a/arch/xtensa/src/common/espressif/Wireless.mk +++ b/arch/xtensa/src/common/espressif/Wireless.mk @@ -20,6 +20,8 @@ # ############################################################################ +WIFI_WPA_SUPPLICANT = chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)wpa_supplicant + ifeq ($(CONFIG_ARCH_CHIP_ESP32),y) INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bt$(DELIM)include$(DELIM)$(CHIP_SERIES)$(DELIM)include endif @@ -27,6 +29,7 @@ ifeq ($(CONFIG_ARCH_CHIP_ESP32S3),y) INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bt$(DELIM)include$(DELIM)esp32c3$(DELIM)include endif INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_coex$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_wifi$(DELIM)$(DELIM)wifi_apps$(DELIM)roaming_app$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)$(CHIP_SERIES)$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)include$(DELIM)esp_wifi @@ -59,21 +62,32 @@ ifeq ($(CONFIG_WPA_WAPI_PSK),y) EXTRA_LIBS += -lwapi endif +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)src +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)esp_supplicant$(DELIM)include + +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_wifi$(DELIM)src$(DELIM)wifi_init.c + ifeq ($(CONFIG_ESPRESSIF_WIFI),y) ## ESP-IDF's mbedTLS - VPATH += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)library -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)library INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port$(DELIM)include$(DELIM)aes +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port$(DELIM)psa_driver$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)tf-psa-crypto$(DELIM)drivers$(DELIM)builtin$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)tf-psa-crypto$(DELIM)drivers$(DELIM)builtin$(DELIM)src +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)include$(DELIM)mbedtls ### Define Espressif's configs for mbedTLS CFLAGS += $(DEFINE_PREFIX)MBEDTLS_CONFIG_FILE="" +VPATH += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)tf-psa-crypto$(DELIM)drivers$(DELIM)builtin$(DELIM)src + CHIP_CSRCS += aes.c CHIP_CSRCS += aria.c CHIP_CSRCS += bignum_core.c @@ -110,20 +124,47 @@ CHIP_CSRCS += hmac_drbg.c CHIP_CSRCS += rsa_alt_helpers.c CHIP_CSRCS += ecdh.c CHIP_CSRCS += pk_ecc.c +CHIP_CSRCS += pk_rsa.c +CHIP_CSRCS += psa_util.c +CHIP_CSRCS += psa_crypto_ffdh.c +CHIP_CSRCS += psa_crypto_ecp.c +CHIP_CSRCS += psa_crypto_rsa.c +CHIP_CSRCS += psa_crypto_cipher.c +CHIP_CSRCS += psa_crypto_mac.c +CHIP_CSRCS += psa_crypto_hash.c + +VPATH += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)tf-psa-crypto$(DELIM)core + +CHIP_CSRCS += psa_crypto_client.c +CHIP_CSRCS += psa_crypto_driver_wrappers_no_static.c +CHIP_CSRCS += psa_crypto_slot_management.c +CHIP_CSRCS += psa_crypto_storage.c +CHIP_CSRCS += psa_crypto.c +CHIP_CSRCS += psa_its_file.c +CHIP_CSRCS += tf_psa_crypto_config.c +CHIP_CSRCS += tf_psa_crypto_version.c VPATH += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port +CHIP_CSRCS += esp_psa_crypto_init.c + CHIP_CSRCS += esp_hardware.c CHIP_CSRCS += esp_mem.c CHIP_CSRCS += esp_timing.c -VPATH += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port$(DELIM)md +# Ensure PSA crypto initialization is included in the build -CHIP_CSRCS += esp_md.c +LDFLAGS += -u mbedtls_psa_crypto_init_include_impl -## WPA Supplicant +VPATH += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port$(DELIM)psa_driver$(DELIM)esp_mac +ifneq ($(CONFIG_ARCH_CHIP_ESP32),y) +CHIP_CSRCS += psa_crypto_driver_esp_hmac_opaque.c +endif -WIFI_WPA_SUPPLICANT = chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)wpa_supplicant +VPATH += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port$(DELIM)psa_driver$(DELIM)esp_md +CHIP_CSRCS += psa_crypto_driver_esp_md5.c + +## WPA Supplicant CFLAGS += $(DEFINE_PREFIX)__ets__ CFLAGS += $(DEFINE_PREFIX)CONFIG_CRYPTO_MBEDTLS @@ -132,14 +173,18 @@ CFLAGS += $(DEFINE_PREFIX)CONFIG_IEEE80211W CFLAGS += $(DEFINE_PREFIX)CONFIG_WPA3_SAE CFLAGS += $(DEFINE_PREFIX)EAP_PEER_METHOD CFLAGS += $(DEFINE_PREFIX)ESP_PLATFORM=1 +CFLAGS += $(DEFINE_PREFIX)TF_PSA_CRYPTO_USER_CONFIG_FILE=\"mbedtls/esp_config.h\" CFLAGS += $(DEFINE_PREFIX)ESP_SUPPLICANT CFLAGS += $(DEFINE_PREFIX)ESPRESSIF_USE CFLAGS += $(DEFINE_PREFIX)IEEE8021X_EAPOL CFLAGS += $(DEFINE_PREFIX)USE_WPA2_TASK CFLAGS += $(DEFINE_PREFIX)CONFIG_SHA256 -CFLAGS += $(DEFINE_PREFIX)CONFIG_SAE CFLAGS += $(DEFINE_PREFIX)USE_WPS_TASK +ifeq ($(CONFIG_ESPRESSIF_WIFI_SOFTAP_SAE_SUPPORT),y) +CFLAGS += $(DEFINE_PREFIX)CONFIG_SAE +endif + ifeq ($(CONFIG_ESPRESSIF_WIFI_ENABLE_SAE_PK),y) CFLAGS += $(DEFINE_PREFIX)CONFIG_SAE_PK endif @@ -160,9 +205,6 @@ ifeq ($(CONFIG_ESPRESSIF_WIFI_GMAC_SUPPORT),y) CFLAGS += $(DEFINE_PREFIX)CONFIG_GMAC endif -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)src - VPATH += $(WIFI_WPA_SUPPLICANT)$(DELIM)src$(DELIM)ap INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)src$(DELIM)ap @@ -193,7 +235,6 @@ VPATH += $(WIFI_WPA_SUPPLICANT)$(DELIM)src$(DELIM)crypto CHIP_CSRCS += aes-ccm.c CHIP_CSRCS += aes-gcm.c -CHIP_CSRCS += aes-omac1.c CHIP_CSRCS += aes-unwrap.c CHIP_CSRCS += aes-wrap.c CHIP_CSRCS += ccmp.c @@ -246,8 +287,6 @@ CHIP_CSRCS += os_xtensa.c ## ESP Supplicant (Espressif's WPA supplicant extension) -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)esp_supplicant$(DELIM)include - VPATH += $(WIFI_WPA_SUPPLICANT)$(DELIM)esp_supplicant$(DELIM)src INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)$(WIFI_WPA_SUPPLICANT)$(DELIM)esp_supplicant$(DELIM)src @@ -272,7 +311,6 @@ CHIP_CSRCS += crypto_mbedtls.c CHIP_CSRCS += tls_mbedtls.c CHIP_CSRCS += aes-siv.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_wifi$(DELIM)src$(DELIM)wifi_init.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_wifi$(DELIM)src$(DELIM)lib_printf.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_wifi$(DELIM)regulatory$(DELIM)esp_wifi_regulatory.c diff --git a/arch/xtensa/src/common/espressif/esp_adc.c b/arch/xtensa/src/common/espressif/esp_adc.c index 756f652f80674..f1e669a8a813c 100644 --- a/arch/xtensa/src/common/espressif/esp_adc.c +++ b/arch/xtensa/src/common/espressif/esp_adc.c @@ -45,16 +45,16 @@ #include "hal/adc_oneshot_hal.h" #include "hal/adc_ll.h" #include "hal/sar_ctrl_ll.h" -#include "soc/adc_periph.h" +#include "hal/adc_periph.h" #include "soc/periph_defs.h" #include "esp_clk_tree.h" #ifdef CONFIG_ARCH_CHIP_ESP32 -#include "esp32_gpio.h" +#include "esp_gpio.h" #elif defined(CONFIG_ARCH_CHIP_ESP32S2) -#include "esp32s2_gpio.h" +#include "espressif/esp_gpio.h" #elif defined(CONFIG_ARCH_CHIP_ESP32S3) -#include "esp32s3_gpio.h" +#include "esp_gpio.h" #endif /**************************************************************************** @@ -66,15 +66,12 @@ #endif #ifdef CONFIG_ARCH_CHIP_ESP32 -# define esp_configgpio esp32_configgpio # define GPIO_ADC_FUNCTION FUNCTION_3 #endif #ifdef CONFIG_ARCH_CHIP_ESP32S2 -# define esp_configgpio esp32s2_configgpio # define GPIO_ADC_FUNCTION FUNCTION_2 #endif #ifdef CONFIG_ARCH_CHIP_ESP32S3 -# define esp_configgpio esp32s3_configgpio # define GPIO_ADC_FUNCTION FUNCTION_2 #endif diff --git a/arch/xtensa/src/common/espressif/esp_dedic_gpio.c b/arch/xtensa/src/common/espressif/esp_dedic_gpio.c index a1780a54d26a4..3dde327b95632 100644 --- a/arch/xtensa/src/common/espressif/esp_dedic_gpio.c +++ b/arch/xtensa/src/common/espressif/esp_dedic_gpio.c @@ -46,19 +46,14 @@ #include "chip.h" #include "esp_dedic_gpio.h" -#if defined(CONFIG_ARCH_CHIP_ESP32S3) -#include "esp32s3_gpio.h" -#elif defined(CONFIG_ARCH_CHIP_ESP32S2) -#include "esp32s2_irq.h" -#include "esp32s2_gpio.h" -#endif - +#include "espressif/esp_gpio.h" #if defined(CONFIG_ARCH_CHIP_ESP32S2) #include "soc/dedic_gpio_struct.h" #endif #include "hal/dedic_gpio_ll.h" #include "hal/dedic_gpio_cpu_ll.h" -#include "soc/dedic_gpio_periph.h" +#include "hal/dedic_gpio_periph.h" +#include "hal/dedic_gpio_caps.h" #include "soc/gpio_sig_map.h" #include "periph_ctrl.h" #include "soc/soc_caps.h" @@ -71,19 +66,11 @@ ****************************************************************************/ #if defined(CONFIG_ARCH_CHIP_ESP32S3) -#define esp_configgpio esp32s3_configgpio -#define esp_gpio_matrix_in esp32s3_gpio_matrix_in -#define esp_gpio_matrix_out esp32s3_gpio_matrix_out #define ESP_IRQ_PRIORITY_DEFAULT ESP32S3_INT_PRIO_DEF -#define ESP_IRQ_TRIGGER_LEVEL ESP32S3_CPUINT_LEVEL +#define ESP_IRQ_TRIGGER_LEVEL ESP_IRQ_TRIGGER_LEVEL #elif defined(CONFIG_ARCH_CHIP_ESP32S2) -#define esp_setup_irq esp32s2_setup_irq -#define esp_teardown_irq esp32s2_teardown_irq -#define esp_configgpio esp32s2_configgpio -#define esp_gpio_matrix_in esp32s2_gpio_matrix_in -#define esp_gpio_matrix_out esp32s2_gpio_matrix_out #define ESP_IRQ_PRIORITY_DEFAULT ESP32S2_INT_PRIO_DEF -#define ESP_IRQ_TRIGGER_LEVEL ESP32S2_CPUINT_LEVEL +#define ESP_IRQ_TRIGGER_LEVEL ESP_IRQ_TRIGGER_LEVEL #endif /**************************************************************************** @@ -252,7 +239,7 @@ static int IRAM_ATTR esp_dedic_gpio_isr_default(int irq, void *context, } /**************************************************************************** - * Name: esp_pcnt_isr_register + * Name: esp_dedic_gpio_isr_register * * Description: * This function registers an interrupt service routine (ISR) for the @@ -271,29 +258,23 @@ static int IRAM_ATTR esp_dedic_gpio_isr_default(int irq, void *context, static int esp_dedic_gpio_isr_register(void) { int cpuint; +#ifndef CONFIG_ARCH_CHIP_ESP32S2 int ret; +#endif int cpu = this_cpu(); uint32_t status; cpuint = esp_setup_irq(dedic_gpio_periph_signals.irq, ESP_IRQ_PRIORITY_DEFAULT, - ESP_IRQ_TRIGGER_LEVEL); + ESP_IRQ_TRIGGER_LEVEL, + esp_dedic_gpio_isr_default, + &dedic_gpio_common[cpu]); if (cpuint < 0) { cperr("Failed to allocate a CPU interrupt.\n"); return ERROR; } - ret = irq_attach(dedic_gpio_periph_signals.irq + XTENSA_IRQ_FIRSTPERIPH, - esp_dedic_gpio_isr_default, - &dedic_gpio_common[cpu]); - if (ret < 0) - { - cperr("Couldn't attach IRQ to handler.\n"); - esp_teardown_irq(dedic_gpio_periph_signals.irq, cpuint); - return ERROR; - } - status = dedic_gpio_ll_get_interrupt_status(dedic_gpio_common[cpu].dev); dedic_gpio_ll_clear_interrupt_status(dedic_gpio_common[cpu].dev, status); up_enable_irq(dedic_gpio_periph_signals.irq + XTENSA_IRQ_FIRSTPERIPH); @@ -538,9 +519,9 @@ struct file *esp_dedic_gpio_new_bundle( } dedic_gpio_common[cpu].out_occupied_mask = - UINT32_MAX & ~((1 << SOC_DEDIC_GPIO_OUT_CHANNELS_NUM) - 1); + UINT32_MAX & ~((1 << DEDIC_GPIO_CAPS_GET(OUT_CHANS_PER_CPU)) - 1); dedic_gpio_common[cpu].in_occupied_mask = - UINT32_MAX & ~((1 << SOC_DEDIC_GPIO_IN_CHANNELS_NUM) - 1); + UINT32_MAX & ~((1 << DEDIC_GPIO_CAPS_GET(IN_CHANS_PER_CPU)) - 1); spin_unlock_irqrestore(&dedic_gpio_common[cpu].spinlock, flags); } @@ -557,11 +538,12 @@ struct file *esp_dedic_gpio_new_bundle( out_offset = 0; if (config->flags->output_enable) { - if (config->array_size > SOC_DEDIC_GPIO_OUT_CHANNELS_NUM) + if (config->array_size > DEDIC_GPIO_CAPS_GET(OUT_CHANS_PER_CPU)) { - gpioerr("ERROR: array size(%d) exceeds maximum supported out\ + gpioerr("ERROR: array size(%d) exceeds maximum supported out \ channels(%d)\n", - config->array_size, SOC_DEDIC_GPIO_OUT_CHANNELS_NUM); + config->array_size, + DEDIC_GPIO_CAPS_GET(OUT_CHANS_PER_CPU)); free(priv); return NULL; } @@ -569,8 +551,9 @@ struct file *esp_dedic_gpio_new_bundle( flags = spin_lock_irqsave(&dedic_gpio_common[cpu].spinlock); for (int i = 0; - i <= SOC_DEDIC_GPIO_OUT_CHANNELS_NUM - config->array_size; - i++) + i <= (DEDIC_GPIO_CAPS_GET(OUT_CHANS_PER_CPU) - \ + config->array_size); + i++) { if ((dedic_gpio_common[cpu].out_occupied_mask & (pattern << i)) == 0) @@ -608,11 +591,12 @@ struct file *esp_dedic_gpio_new_bundle( if (config->flags->input_enable) { - if (config->array_size > SOC_DEDIC_GPIO_IN_CHANNELS_NUM) + if (config->array_size > DEDIC_GPIO_CAPS_GET(IN_CHANS_PER_CPU)) { gpioerr("ERROR: array size(%d) exceeds maximum supported in\ channels(%d)\n", - config->array_size, SOC_DEDIC_GPIO_IN_CHANNELS_NUM); + config->array_size, + DEDIC_GPIO_CAPS_GET(IN_CHANS_PER_CPU)); free(priv); return NULL; } @@ -620,8 +604,9 @@ struct file *esp_dedic_gpio_new_bundle( flags = spin_lock_irqsave(&dedic_gpio_common[cpu].spinlock); for (int i = 0; - i <= SOC_DEDIC_GPIO_IN_CHANNELS_NUM - config->array_size; - i++) + i <= (DEDIC_GPIO_CAPS_GET(IN_CHANS_PER_CPU) - \ + config->array_size); + i++) { if ((dedic_gpio_common[cpu].in_occupied_mask & (pattern << i)) == 0) diff --git a/arch/xtensa/src/common/espressif/esp_efuse.c b/arch/xtensa/src/common/espressif/esp_efuse.c index 813a7a291062b..a964feccf8abc 100644 --- a/arch/xtensa/src/common/espressif/esp_efuse.c +++ b/arch/xtensa/src/common/espressif/esp_efuse.c @@ -42,6 +42,7 @@ #include "xtensa.h" #include "soc/syscon_reg.h" #include "esp_efuse_table.h" +#include "hal/efuse_ll.h" #endif /**************************************************************************** @@ -345,16 +346,9 @@ uint32_t esp_efuse_hal_chip_revision(void) uint32_t combine_value; uint32_t chip_ver = 0; - esp_efuse_read_field_blob(ESP_EFUSE_CHIP_VER_REV1, - &eco_bit0, - ESP_EFUSE_CHIP_VER_REV1[0]->bit_count); - esp_efuse_read_field_blob(ESP_EFUSE_CHIP_VER_REV2, - &eco_bit1, - ESP_EFUSE_CHIP_VER_REV2[0]->bit_count); - esp_efuse_read_field_blob(ESP_EFUSE_WAFER_VERSION_MINOR, - &minor_chip_version, - ESP_EFUSE_WAFER_VERSION_MINOR[0]->bit_count); - + eco_bit0 = efuse_ll_get_chip_ver_rev1(); + eco_bit1 = efuse_ll_get_chip_ver_rev2(); + minor_chip_version = efuse_ll_get_chip_wafer_version_minor(); eco_bit2 = (getreg32(SYSCON_DATE_REG) & 0x80000000) >> 31; combine_value = (eco_bit2 << 2) | (eco_bit1 << 1) | eco_bit0; diff --git a/arch/xtensa/src/common/espressif/esp_espnow_pktradio.c b/arch/xtensa/src/common/espressif/esp_espnow_pktradio.c index 541299cdf9591..da5156f675c7f 100644 --- a/arch/xtensa/src/common/espressif/esp_espnow_pktradio.c +++ b/arch/xtensa/src/common/espressif/esp_espnow_pktradio.c @@ -47,7 +47,7 @@ #include #include "xtensa.h" -#include "xtensa_attr.h" + #include "esp_now.h" #include "esp_mac.h" #include "esp_espnow_pktradio.h" diff --git a/arch/xtensa/src/common/espressif/esp_gpio.c b/arch/xtensa/src/common/espressif/esp_gpio.c new file mode 100644 index 0000000000000..a7387a4dd395d --- /dev/null +++ b/arch/xtensa/src/common/espressif/esp_gpio.c @@ -0,0 +1,457 @@ +/**************************************************************************** + * arch/xtensa/src/common/espressif/esp_gpio.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/* Config */ + +#include + +/* Libc */ + +#include +#include +#include +#include + +/* NuttX */ + +#include +#include +#include +#include + +/* Arch */ + +#include "xtensa.h" + +#include "esp_gpio.h" +#include "esp_irq.h" + +/* HAL */ + +#include "esp_err.h" +#include "soc/interrupts.h" +#include "esp_rom_gpio.h" +#include "hal/gpio_hal.h" +#include "driver/gpio.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define ESP_INTR_FLAG_DEFAULT 0 + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static gpio_hal_context_t g_gpio_hal = +{ + .dev = GPIO_HAL_GET_HW(GPIO_PORT_0) +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp_intr_handler_adapter + * + * Description: + * This function acts as an adapter to bridge interrupt service routines + * between NuttX and the Espressif's interrupt service routine. It is + * called when a GPIO interrupt occurs, retrieves the function pointer and + * associated data from the 'intr_adapter_from_nuttx' structure passed as + * an argument, and invokes the original user-provided interrupt handler + * with the IRQ number and user argument. + * + * Input Parameters: + * arg - Pointer to a structure of type 'intr_adapter_from_nuttx' that + * holds the handler function, the associated IRQ, the context, and + * the user argument. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +#ifdef CONFIG_ESPRESSIF_GPIO_IRQ +static void esp_intr_handler_adapter(void *arg) +{ + struct intr_adapter_from_nuttx *adapter; + + adapter = (struct intr_adapter_from_nuttx *)arg; + + adapter->func(adapter->irq, adapter->context, adapter->arg); +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp_configgpio + * + * Description: + * Configure a GPIO pin based on encoded pin attributes. + * + * Input Parameters: + * pin - GPIO pin to be configured. + * attr - Attributes to be configured for the selected GPIO pin. + * The following attributes are accepted: + * - Direction (OUTPUT or INPUT) + * - Pull (PULLUP, PULLDOWN or OPENDRAIN) + * - Function (if not provided, assume function GPIO by + * default) + * - Drive strength (if not provided, assume DRIVE_2 by + * default) + * + * Returned Value: + * Zero (OK) on success, or -1 (ERROR) in case of failure. + * + ****************************************************************************/ + +int esp_configgpio(int pin, gpio_pinattr_t attr) +{ + DEBUGASSERT(pin >= 0 && pin < SOC_GPIO_PIN_COUNT); + + /* Handle input pins */ + + if ((attr & INPUT) != 0) + { + gpio_hal_input_enable(&g_gpio_hal, pin); + } + else + { + gpio_hal_input_disable(&g_gpio_hal, pin); + } + + if ((attr & OPEN_DRAIN) != 0) + { + gpio_hal_od_enable(&g_gpio_hal, pin); + } + else + { + gpio_hal_od_disable(&g_gpio_hal, pin); + } + + if ((attr & OUTPUT) != 0) + { + gpio_hal_output_enable(&g_gpio_hal, pin); + } + else + { + gpio_hal_output_disable(&g_gpio_hal, pin); + } + + if ((attr & PULLUP) != 0) + { + gpio_pullup_en(pin); + } + else + { + gpio_pullup_dis(pin); + } + + if ((attr & PULLDOWN) != 0) + { + gpio_pulldown_en(pin); + } + else + { + gpio_pulldown_dis(pin); + } + + gpio_hal_set_intr_type(&g_gpio_hal, pin, + (attr & INTR_TYPE_MASK) >> INTR_TYPE_SHIFT); + + if ((attr & DRIVE_MASK) != 0) + { + uint32_t val = ((attr & DRIVE_MASK) >> DRIVE_SHIFT) - 1; + gpio_hal_set_drive_capability(&g_gpio_hal, pin, val); + } + else + { + gpio_hal_set_drive_capability(&g_gpio_hal, pin, + GPIO_DRIVE_CAP_DEFAULT); + } + + if ((attr & FUNCTION_MASK) != 0) + { + uint32_t val = ((attr & FUNCTION_MASK) >> FUNCTION_SHIFT) - 1; + gpio_hal_func_sel(&g_gpio_hal, pin, val); + } + else + { + gpio_hal_func_sel(&g_gpio_hal, pin, PIN_FUNC_GPIO); + } + + return OK; +} + +/**************************************************************************** + * Name: esp_gpio_matrix_in + * + * Description: + * Set GPIO input to a signal. + * NOTE: one GPIO can receive inputs from several signals. + * + * Input Parameters: + * pin - GPIO pin to be configured. + * - If pin == 0x3c, cancel input to the signal, input 0 + * to signal. + * - If pin == 0x3a, input nothing to signal. + * - If pin == 0x38, cancel input to the signal, input 1 + * to signal. + * signal_idx - Signal index. + * inv - Flag indicating whether the signal is inverted. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp_gpio_matrix_in(uint32_t pin, uint32_t signal_idx, bool inv) +{ + esp_rom_gpio_connect_in_signal(pin, signal_idx, inv); +} + +/**************************************************************************** + * Name: esp_gpio_matrix_out + * + * Description: + * Set signal output to GPIO. + * NOTE: one signal can output to several GPIOs. + * + * Input Parameters: + * pin - GPIO pin to be configured. + * signal_idx - Signal index. + * - If signal_idx == 0x100, cancel output to the GPIO. + * out_inv - Flag indicating whether the signal output is inverted. + * oen_inv - Flag indicating whether the signal output enable is + * inverted. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp_gpio_matrix_out(uint32_t pin, uint32_t signal_idx, bool out_inv, + bool oen_inv) +{ + esp_rom_gpio_connect_out_signal(pin, signal_idx, out_inv, oen_inv); +} + +/**************************************************************************** + * Name: esp_gpiowrite + * + * Description: + * Write one or zero to the selected GPIO pin + * + * Input Parameters: + * pin - GPIO pin to be modified. + * value - The value to be written (0 or 1). + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp_gpiowrite(int pin, bool value) +{ + DEBUGASSERT(pin >= 0 && pin <= SOC_GPIO_PIN_COUNT); + + gpio_hal_set_level(&g_gpio_hal, pin, value); +} + +/**************************************************************************** + * Name: esp_gpioread + * + * Description: + * Read one or zero from the selected GPIO pin + * + * Input Parameters: + * pin - GPIO pin to be read. + * + * Returned Value: + * The boolean representation of the input value (true/false). + * + ****************************************************************************/ + +bool esp_gpioread(int pin) +{ + DEBUGASSERT(pin >= 0 && pin <= SOC_GPIO_PIN_COUNT); + + return gpio_hal_get_level(&g_gpio_hal, pin) != 0; +} + +/**************************************************************************** + * Name: esp_gpioirqinitialize + * + * Description: + * Initialize logic to support a second level of interrupt decoding for + * GPIO pins. + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +#ifdef CONFIG_ESPRESSIF_GPIO_IRQ +void esp_gpioirqinitialize(void) +{ + /* Setup the GPIO interrupt. */ + + gpio_install_isr_service(ESP_INTR_FLAG_DEFAULT); +} +#endif + +/**************************************************************************** + * Name: esp_gpioirqenable + * + * Description: + * Enable the interrupt for specified GPIO + * + * Input Parameters: + * id - GPIO to be enabled. + * + * Returned Value: + * Zero (OK) on success, or -1 (ERROR) in case of failure. + * + ****************************************************************************/ + +#ifdef CONFIG_ESPRESSIF_GPIO_IRQ +int esp_gpioirqenable(int id) +{ + esp_err_t esp_ret; + + esp_ret = gpio_intr_enable(id); + if (esp_ret != ESP_OK) + { + gpioerr("gpio_intr_enable() failed: %d\n", esp_ret); + return -ERROR; + } + + return OK; +} +#endif + +/**************************************************************************** + * Name: esp_gpioirqdisable + * + * Description: + * Disable the interrupt for specified GPIO + * + * Input Parameters: + * id - GPIO to be disabled. + * + * Returned Value: + * Zero (OK) on success, or -1 (ERROR) in case of failure. + * + ****************************************************************************/ + +#ifdef CONFIG_ESPRESSIF_GPIO_IRQ +int esp_gpioirqdisable(int id) +{ + esp_err_t esp_ret; + + esp_ret = gpio_intr_disable(id); + if (esp_ret != ESP_OK) + { + gpioerr("gpio_intr_disable() failed: %d\n", esp_ret); + return -ERROR; + } + + return OK; +} +#endif + +/**************************************************************************** + * Name: esp_gpio_irq + * + * Description: + * Register or unregister a button interrupt handler for the specified + * button ID. Passing a non-NULL handler attaches and enables the ISR for + * the button; passing NULL disables the interrupt and removes any + * previously registered handler. + * + * Input Parameters: + * id - Identifies the button to be monitored. + * irqhandler - The handler to be called when the interrupt occurs. + * Set to NULL to disable the interrupt. + * arg - Pointer to the argument that will be provided to the + * interrupt handler. + * + * Returned Value: + * Zero (OK) on success; a negated errno value on failure. + * + ****************************************************************************/ + +#ifdef CONFIG_ESPRESSIF_GPIO_IRQ +int esp_gpio_irq(int id, xcpt_t irqhandler, void *arg) +{ + int ret; + int irq = ESP_PIN2IRQ(id); + + if (NULL != irqhandler) + { + esp_err_t esp_ret; + struct intr_adapter_from_nuttx *adapter; + + gpioinfo("Attach %p\n", irqhandler); + + adapter = kmm_calloc(1, sizeof(struct intr_adapter_from_nuttx)); + if (adapter == NULL) + { + gpioerr("kmm_calloc() failed\n"); + return -ERROR; + } + + adapter->func = irqhandler; + adapter->irq = irq; + adapter->context = NULL; + adapter->arg = arg; + + esp_ret = gpio_isr_handler_add(id, esp_intr_handler_adapter, + (void *)adapter); + if (esp_ret != ESP_OK) + { + gpioerr("gpio_isr_handler_add() failed: %d\n", ret); + return -ERROR; + } + } + else + { + gpioinfo("Disable the interrupt\n"); + gpio_isr_handler_remove(id); + } + + return OK; +} +#endif diff --git a/arch/xtensa/src/esp32s2/esp32s2_gpio.h b/arch/xtensa/src/common/espressif/esp_gpio.h similarity index 69% rename from arch/xtensa/src/esp32s2/esp32s2_gpio.h rename to arch/xtensa/src/common/espressif/esp_gpio.h index 0e68f75eae29a..a046eb7258389 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_gpio.h +++ b/arch/xtensa/src/common/espressif/esp_gpio.h @@ -1,5 +1,7 @@ /**************************************************************************** - * arch/xtensa/src/esp32s2/esp32s2_gpio.h + * arch/xtensa/src/common/espressif/esp_gpio.h + * + * SPDX-License-Identifier: Apache-2.0 * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,14 +20,15 @@ * ****************************************************************************/ -#ifndef __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_GPIO_H -#define __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_GPIO_H +#ifndef __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_GPIO_H +#define __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_GPIO_H /**************************************************************************** * Included Files ****************************************************************************/ #include +#include #include #include @@ -34,17 +37,17 @@ * Pre-processor Definitions ****************************************************************************/ -#define MATRIX_DETACH_OUT_SIG 0x100 /* Detach an OUTPUT signal */ -#define MATRIX_DETACH_IN_LOW_PIN 0x3c /* Detach non-inverted INPUT sig */ -#define MATRIX_DETACH_IN_LOW_HIGH 0x38 /* Detach inverted INPUT signal */ + #define MATRIX_DETACH_OUT_SIG 0x100 /* Detach an OUTPUT signal */ + #define MATRIX_DETACH_IN_LOW_PIN 0x3c /* Detach non-inverted INPUT signal */ + #define MATRIX_DETACH_IN_LOW_HIGH 0x38 /* Detach inverted INPUT signal */ -/* Bit-encoded input to esp32s2_configgpio() ********************************/ +/* Bit-encoded input to esp_configgpio() ************************************/ -/* Encoded pin attributes used with esp32s2_configgpio() +/* Encoded pin attributes used with esp_configgpio() * - * 8 7 6 5 4 3 2 1 0 - * -- -- -- -- -- -- -- -- -- - * FN FN FN OD PD PU F O I + * 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 + * -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- + * IT IT IT DR DR DR FN FN FN OD PD PU F O I */ #define MODE_SHIFT 0 @@ -75,6 +78,15 @@ # define DRIVE_2 (3 << DRIVE_SHIFT) # define DRIVE_3 (4 << DRIVE_SHIFT) +#define INTR_TYPE_SHIFT 12 +#define INTR_TYPE_MASK (7 << INTR_TYPE_SHIFT) +# define DISABLED (0 << INTR_TYPE_SHIFT) +# define RISING (1 << INTR_TYPE_SHIFT) +# define FALLING (2 << INTR_TYPE_SHIFT) +# define CHANGE (3 << INTR_TYPE_SHIFT) +# define ONLOW (4 << INTR_TYPE_SHIFT) +# define ONHIGH (5 << INTR_TYPE_SHIFT) + #define INPUT_PULLUP (INPUT | PULLUP) #define INPUT_PULLDOWN (INPUT | PULLDOWN) #define OUTPUT_OPEN_DRAIN (OUTPUT | OPEN_DRAIN) @@ -93,33 +105,6 @@ # define OUTPUT_FUNCTION_5 (OUTPUT_FUNCTION | FUNCTION_5) # define OUTPUT_FUNCTION_6 (OUTPUT_FUNCTION | FUNCTION_6) -/* Interrupt type used with esp32s2_gpioirqenable() */ - -#define DISABLED 0x00 -#define RISING 0x01 -#define FALLING 0x02 -#define CHANGE 0x03 -#define ONLOW 0x04 -#define ONHIGH 0x05 - -/* Check whether it is a valid GPIO number */ - -#define GPIO_IS_VALID_GPIO(gpio_num) ((gpio_num >= 0) && \ - (((1ULL << (gpio_num)) & \ - SOC_GPIO_VALID_GPIO_MASK) != 0)) - -/* Check whether it can be a valid GPIO number of output mode */ - -#define GPIO_IS_VALID_OUTPUT_GPIO(gpio_num) \ - ((gpio_num >= 0) && \ - (((1ULL << (gpio_num)) & SOC_GPIO_VALID_OUTPUT_GPIO_MASK) != 0)) - -/* Check whether it can be a valid digital I/O pad */ - -#define GPIO_IS_VALID_DIGITAL_IO_PAD(gpio_num) \ - ((gpio_num >= 0) && \ - (((1ULL << (gpio_num)) & SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK) != 0)) - /**************************************************************************** * Public Types ****************************************************************************/ @@ -149,172 +134,194 @@ extern "C" ****************************************************************************/ /**************************************************************************** - * Name: esp32s2_gpioirqinitialize + * Name: esp_configgpio * * Description: - * Initialize logic to support a second level of interrupt decoding for - * GPIO pins. + * Configure a GPIO pin based on encoded pin attributes. * * Input Parameters: - * None. + * pin - GPIO pin to be configured. + * attr - Attributes to be configured for the selected GPIO pin. + * The following attributes are accepted: + * - Direction (OUTPUT or INPUT) + * - Pull (PULLUP, PULLDOWN or OPENDRAIN) + * - Function (if not provided, assume function GPIO by + * default) + * - Drive strength (if not provided, assume DRIVE_2 by + * default) + * + * Returned Value: + * Zero (OK) on success, or -1 (ERROR) in case of failure. + * + ****************************************************************************/ + +int esp_configgpio(int pin, gpio_pinattr_t attr); + +/**************************************************************************** + * Name: esp_gpio_matrix_in + * + * Description: + * Set GPIO input to a signal. + * NOTE: one GPIO can receive inputs from several signals. + * + * Input Parameters: + * pin - GPIO pin to be configured. + * - If pin == 0x3c, cancel input to the signal, input 0 + * to signal. + * - If pin == 0x3a, input nothing to signal. + * - If pin == 0x38, cancel input to the signal, input 1 + * to signal. + * signal_idx - Signal index. + * inv - Flag indicating whether the signal is inverted. * * Returned Value: * None. * ****************************************************************************/ -#ifdef CONFIG_ESP32S2_GPIO_IRQ -void esp32s2_gpioirqinitialize(void); -#else -# define esp32s2_gpioirqinitialize() -#endif +void esp_gpio_matrix_in(uint32_t pin, uint32_t signal_idx, bool inv); /**************************************************************************** - * Name: esp32s2_configgpio + * Name: esp_gpio_matrix_out * * Description: - * Configure a GPIO pin based on encoded pin attributes. + * Set signal output to GPIO. + * NOTE: one signal can output to several GPIOs. * * Input Parameters: * pin - GPIO pin to be configured. - * attr - Attributes to be configured for the selected GPIO pin. - * The following attributes are accepted: - * - Direction (OUTPUT or INPUT) - * - Pull (PULLUP, PULLDOWN or OPENDRAIN) - * - Function (if not provided, assume function GPIO by - * default) - * - Drive strength (if not provided, assume DRIVE_2 by - * default) + * signal_idx - Signal index. + * - If signal_idx == 0x100, cancel output to the GPIO. + * out_inv - Flag indicating whether the signal output is inverted. + * oen_inv - Flag indicating whether the signal output enable is + * inverted. * * Returned Value: - * Zero (OK) on success, or -1 (ERROR) in case of failure. + * None. * ****************************************************************************/ -int esp32s2_configgpio(int pin, gpio_pinattr_t attr); +void esp_gpio_matrix_out(uint32_t pin, uint32_t signal_idx, bool out_inv, + bool oen_inv); /**************************************************************************** - * Name: esp32s2_gpiowrite + * Name: esp_gpiowrite * * Description: - * Write one or zero to the selected GPIO pin. + * Write one or zero to the selected GPIO pin * * Input Parameters: - * pin - GPIO pin to be written. - * value - Value to be written to the GPIO pin. True will output - * 1 (one) to the GPIO, while false will output 0 (zero). + * pin - GPIO pin to be modified. + * value - The value to be written (0 or 1). * * Returned Value: * None. * ****************************************************************************/ -void esp32s2_gpiowrite(int pin, bool value); +void esp_gpiowrite(int pin, bool value); /**************************************************************************** - * Name: esp32s2_gpioread + * Name: esp_gpioread * * Description: - * Read one or zero from the selected GPIO pin. + * Read one or zero from the selected GPIO pin * * Input Parameters: * pin - GPIO pin to be read. * * Returned Value: - * True in case the read value is 1 (one). If 0 (zero), then false will be - * returned. + * The boolean representation of the input value (true/false). * ****************************************************************************/ -bool esp32s2_gpioread(int pin); +bool esp_gpioread(int pin); /**************************************************************************** - * Name: esp32s2_gpioirqenable + * Name: esp_gpioirqinitialize * * Description: - * Enable the interrupt for the specified GPIO IRQ. + * Initialize logic to support a second level of interrupt decoding for + * GPIO pins. * * Input Parameters: - * irq - Identifier of the interrupt request. - * intrtype - Interrupt type, select from gpio_intrtype_t. + * None. * * Returned Value: * None. * ****************************************************************************/ -#ifdef CONFIG_ESP32S2_GPIO_IRQ -void esp32s2_gpioirqenable(int irq, gpio_intrtype_t intrtype); +#ifdef CONFIG_ESPRESSIF_GPIO_IRQ +void esp_gpioirqinitialize(void); #else -# define esp32s2_gpioirqenable(irq,intrtype) +# define esp_gpioirqinitialize() #endif /**************************************************************************** - * Name: esp32s2_gpioirqdisable + * Name: esp_gpioirqenable * * Description: - * Disable the interrupt for the specified GPIO IRQ. + * Enable the interrupt for specified GPIO * * Input Parameters: - * irq - Identifier of the interrupt request. + * id - GPIO to be enabled. * * Returned Value: - * None. + * Zero (OK) on success, or -1 (ERROR) in case of failure. * ****************************************************************************/ -#ifdef CONFIG_ESP32S2_GPIO_IRQ -void esp32s2_gpioirqdisable(int irq); +#ifdef CONFIG_ESPRESSIF_GPIO_IRQ +int esp_gpioirqenable(int id); #else -# define esp32s2_gpioirqdisable(irq) +# define esp_gpioirqenable(id) #endif /**************************************************************************** - * Name: esp32s2_gpio_matrix_in + * Name: esp_gpioirqdisable * * Description: - * Set GPIO input to a signal. - * NOTE: one GPIO can receive inputs from several signals. + * Disable the interrupt for specified GPIO * * Input Parameters: - * pin - GPIO pin to be configured. - * - If pin == 0x3c, cancel input to the signal, input 0 - * to signal. - * - If pin == 0x3a, input nothing to signal. - * - If pin == 0x38, cancel input to the signal, input 1 - * to signal. - * signal_idx - Signal index. - * inv - Flag indicating whether the signal is inverted. + * id - GPIO to be disabled. * * Returned Value: - * None. + * Zero (OK) on success, or -1 (ERROR) in case of failure. * ****************************************************************************/ -void esp32s2_gpio_matrix_in(uint32_t pin, uint32_t signal_idx, bool inv); +#ifdef CONFIG_ESPRESSIF_GPIO_IRQ +int esp_gpioirqdisable(int id); +#else +# define esp_gpioirqdisable(id) +#endif /**************************************************************************** - * Name: esp32s2_gpio_matrix_out + * Name: esp_gpio_irq * * Description: - * Set signal output to GPIO. - * NOTE: one signal can output to several GPIOs. + * Register or unregister a button interrupt handler for the specified + * button ID. Passing a non-NULL handler attaches and enables the ISR for + * the button; passing NULL disables the interrupt and removes any + * previously registered handler. * * Input Parameters: - * pin - GPIO pin to be configured. - * signal_idx - Signal index. - * - If signal_idx == 0x100, cancel output to the GPIO. - * out_inv - Flag indicating whether the signal output is inverted. - * oen_inv - Flag indicating whether the signal output enable is - * inverted. + * id - Identifies the button to be monitored. + * irqhandler - The handler to be called when the interrupt occurs. + * Set to NULL to disable the interrupt. + * arg - Pointer to the argument that will be provided to the + * interrupt handler. * * Returned Value: - * None. + * Zero (OK) on success; a negated errno value on failure. * ****************************************************************************/ -void esp32s2_gpio_matrix_out(uint32_t pin, uint32_t signal_idx, bool out_inv, - bool oen_inv); +#ifdef CONFIG_ESPRESSIF_GPIO_IRQ +int esp_gpio_irq(int id, xcpt_t irqhandler, void *arg); +#endif #ifdef __cplusplus } @@ -322,4 +329,4 @@ void esp32s2_gpio_matrix_out(uint32_t pin, uint32_t signal_idx, bool out_inv, #undef EXTERN #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_GPIO_H */ +#endif /* __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_GPIO_H */ diff --git a/arch/xtensa/src/esp32s3/esp32s3_rtc_lowerhalf.h b/arch/xtensa/src/common/espressif/esp_hr_timer.h similarity index 52% rename from arch/xtensa/src/esp32s3/esp32s3_rtc_lowerhalf.h rename to arch/xtensa/src/common/espressif/esp_hr_timer.h index 3546c0474faf2..2443db8dccd89 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_rtc_lowerhalf.h +++ b/arch/xtensa/src/common/espressif/esp_hr_timer.h @@ -1,5 +1,7 @@ /**************************************************************************** - * arch/xtensa/src/esp32s3/esp32s3_rtc_lowerhalf.h + * arch/xtensa/src/common/espressif/esp_hr_timer.h + * + * SPDX-License-Identifier: Apache-2.0 * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,39 +20,15 @@ * ****************************************************************************/ -#ifndef __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_RTC_LOWERHALF_H -#define __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_RTC_LOWERHALF_H +#ifndef __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_HR_TIMER_H +#define __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_HR_TIMER_H /**************************************************************************** * Included Files ****************************************************************************/ -#include - -#ifdef CONFIG_RTC_DRIVER - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32s3_rtc_driverinit - * - * Description: - * Bind the configuration timer to a timer lower half instance and register - * the timer drivers at 'devpath' - * - * Input Parameters: - * None - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned - * to indicate the nature of any failure. - * - ****************************************************************************/ - -int esp32s3_rtc_driverinit(void); +/* This is a compatibility wrapper for the new ESP-HAL timer adapter */ -#endif /* CONFIG_RTC_DRIVER */ +#include "esp_timer_adapter.h" -#endif /* __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_RTC_LOWERHALF_H */ +#endif /* __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_HR_TIMER_H */ diff --git a/arch/xtensa/src/common/espressif/esp_i2c_bitbang.c b/arch/xtensa/src/common/espressif/esp_i2c_bitbang.c index e1f117e4b66d6..d5ee93a8822ce 100644 --- a/arch/xtensa/src/common/espressif/esp_i2c_bitbang.c +++ b/arch/xtensa/src/common/espressif/esp_i2c_bitbang.c @@ -33,16 +33,16 @@ #include #include "espressif/esp_i2c_bitbang.h" +#include "espressif/esp_gpio.h" -#if defined(CONFIG_ARCH_CHIP_ESP32S3) -#include "esp32s3_gpio.h" -#include "hardware/esp32s3_gpio_sigmap.h" +#if defined(CONFIG_ARCH_CHIP_ESP32) +# include "esp32_gpio_sigmap.h" #elif defined(CONFIG_ARCH_CHIP_ESP32S2) -#include "esp32s2_gpio.h" -#include "esp32s2_gpio_sigmap.h" +# include "esp32s2_gpio_sigmap.h" +#elif defined(CONFIG_ARCH_CHIP_ESP32S3) +# include "esp32s3_gpio_sigmap.h" #else -#include "esp32_gpio.h" -#include "esp32_gpio_sigmap.h" +# error "Unsupported chip" #endif /**************************************************************************** @@ -50,22 +50,22 @@ ****************************************************************************/ #if defined(CONFIG_ARCH_CHIP_ESP32S3) -#define CONFIG_GPIO(pin, attr) esp32s3_configgpio(pin, attr) -#define GPIO_MATRIX_OUT(pin, idx, inv, en_inv) esp32s3_gpio_matrix_out(pin, \ +#define CONFIG_GPIO(pin, attr) esp_configgpio(pin, attr) +#define GPIO_MATRIX_OUT(pin, idx, inv, en_inv) esp_gpio_matrix_out(pin, \ idx, inv, en_inv) -#define GPIO_WRITE(pin, value) esp32s3_gpiowrite(pin, value) +#define GPIO_WRITE(pin, value) esp_gpiowrite(pin, value) #define GPIO_READ(pin) esp32s3_gpioread(pin) #elif defined(CONFIG_ARCH_CHIP_ESP32S2) -#define CONFIG_GPIO(pin, attr) esp32s2_configgpio(pin, attr) -#define GPIO_MATRIX_OUT(pin, idx, inv, en_inv) esp32s2_gpio_matrix_out(pin, \ +#define CONFIG_GPIO(pin, attr) esp_configgpio(pin, attr) +#define GPIO_MATRIX_OUT(pin, idx, inv, en_inv) esp_gpio_matrix_out(pin, \ idx, inv, en_inv) -#define GPIO_WRITE(pin, value) esp32s2_gpiowrite(pin, value) -#define GPIO_READ(pin) esp32s2_gpioread(pin) +#define GPIO_WRITE(pin, value) esp_gpiowrite(pin, value) +#define GPIO_READ(pin) esp_gpioread(pin) #else -#define CONFIG_GPIO(pin, attr) esp32_configgpio(pin, attr) -#define GPIO_MATRIX_OUT(pin, idx, inv, en_inv) esp32_gpio_matrix_out(pin, \ +#define CONFIG_GPIO(pin, attr) esp_configgpio(pin, attr) +#define GPIO_MATRIX_OUT(pin, idx, inv, en_inv) esp_gpio_matrix_out(pin, \ idx, inv, en_inv) -#define GPIO_WRITE(pin, value) esp32_gpiowrite(pin, value) +#define GPIO_WRITE(pin, value) esp_gpiowrite(pin, value) #define GPIO_READ(pin) esp3_gpioread(pin) #endif diff --git a/arch/xtensa/src/common/espressif/esp_i2c_slave.c b/arch/xtensa/src/common/espressif/esp_i2c_slave.c index 59a6db001c7a5..f2d8a15a1cb52 100644 --- a/arch/xtensa/src/common/espressif/esp_i2c_slave.c +++ b/arch/xtensa/src/common/espressif/esp_i2c_slave.c @@ -54,16 +54,16 @@ #include "esp_i2c_slave.h" #include "xtensa.h" #if defined(CONFIG_ARCH_CHIP_ESP32S3) -#include "esp32s3_gpio.h" -#include "esp32s3_irq.h" +#include "esp_gpio.h" +#include "esp_irq.h" #include "hardware/esp32s3_gpio_sigmap.h" #elif defined(CONFIG_ARCH_CHIP_ESP32S2) -#include "esp32s2_gpio.h" -#include "esp32s2_irq.h" +#include "espressif/esp_gpio.h" +#include "espressif/esp_irq.h" #include "esp32s2_gpio_sigmap.h" #else -#include "esp32_gpio.h" -#include "esp32_irq.h" +#include "esp_gpio.h" +#include "esp_irq.h" #include "esp32_gpio_sigmap.h" #endif @@ -73,7 +73,7 @@ #include "hal/i2c_ll.h" #include "soc/system_reg.h" #include "soc/gpio_sig_map.h" -#include "soc/i2c_periph.h" +#include "hal/i2c_periph.h" /**************************************************************************** * Pre-processor Definitions @@ -85,48 +85,21 @@ #define CONFIG_ESPRESSIF_I2C1_SCLPIN CONFIG_ESP32S3_I2C1_SCLPIN #define CONFIG_ESPRESSIF_I2C1_SDAPIN CONFIG_ESP32S3_I2C1_SDAPIN #define ESP_IRQ_I2C_EXT0 ESP32S3_IRQ_I2C_EXT0 -#define ESP_IRQ_TRIGGER_LEVEL ESP32S3_CPUINT_LEVEL #define ESP_IRQ_PRIORITY_DEFAULT ESP32S3_INT_PRIO_DEF -#define esp_setup_irq esp32s3_setup_irq -#define esp_teardown_irq esp32s3_teardown_irq -#define esp_gpiowrite(pin, value) esp32s3_gpiowrite(pin, value) -#define esp_configgpio(pin, attr) esp32s3_configgpio(pin, attr) -#define esp_gpio_matrix_in(pin, idx, inv) esp32s3_gpio_matrix_in(pin, \ - idx, inv) -#define esp_gpio_matrix_out(pin, idx, inv, en_inv) esp32s3_gpio_matrix_out(pin, \ - idx, inv, en_inv) #elif defined(CONFIG_ARCH_CHIP_ESP32S2) #define CONFIG_ESPRESSIF_I2C0_SCLPIN CONFIG_ESP32S2_I2C0_SCLPIN #define CONFIG_ESPRESSIF_I2C0_SDAPIN CONFIG_ESP32S2_I2C0_SDAPIN #define CONFIG_ESPRESSIF_I2C1_SCLPIN CONFIG_ESP32S2_I2C1_SCLPIN #define CONFIG_ESPRESSIF_I2C1_SDAPIN CONFIG_ESP32S2_I2C1_SDAPIN #define ESP_IRQ_I2C_EXT0 ESP32S2_IRQ_I2C_EXT0 -#define ESP_IRQ_TRIGGER_LEVEL ESP32S2_CPUINT_LEVEL #define ESP_IRQ_PRIORITY_DEFAULT ESP32S2_INT_PRIO_DEF -#define esp_setup_irq esp32s2_setup_irq -#define esp_teardown_irq esp32s2_teardown_irq -#define esp_gpiowrite(pin, value) esp32s2_gpiowrite(pin, value) -#define esp_configgpio(pin, attr) esp32s2_configgpio(pin, attr) -#define esp_gpio_matrix_in(pin, idx, inv, en_inv) esp32s2_gpio_matrix_in(pin, \ - idx, inv, en_inv) -#define esp_gpio_matrix_out(pin, idx, inv, en_inv) esp32s2_gpio_matrix_out(pin, \ - idx, inv, en_inv) #else #define CONFIG_ESPRESSIF_I2C0_SCLPIN CONFIG_ESP32_I2C0_SCLPIN #define CONFIG_ESPRESSIF_I2C0_SDAPIN CONFIG_ESP32_I2C0_SDAPIN #define CONFIG_ESPRESSIF_I2C1_SCLPIN CONFIG_ESP32_I2C1_SCLPIN #define CONFIG_ESPRESSIF_I2C1_SDAPIN CONFIG_ESP32_I2C1_SDAPIN #define ESP_IRQ_I2C_EXT0 ESP32_IRQ_I2C_EXT0 -#define ESP_IRQ_TRIGGER_LEVEL ESP32_CPUINT_LEVEL #define ESP_IRQ_PRIORITY_DEFAULT 1 -#define esp_setup_irq esp32_setup_irq -#define esp_teardown_irq esp32_teardown_irq -#define esp_gpiowrite(pin, value) esp32_gpiowrite(pin, value) -#define esp_configgpio(pin, attr) esp32_configgpio(pin, attr) -#define esp_gpio_matrix_in(pin, idx, inv) esp32_gpio_matrix_in(pin, \ - idx, inv) -#define esp_gpio_matrix_out(pin, idx, inv) esp32_gpio_matrix_out(pin, \ - idx, inv) #endif #define I2C_FIFO_FULL_THRESH_VAL 28 @@ -935,20 +908,13 @@ struct i2c_slave_s *esp_i2cbus_slave_initialize(int port, int addr) /* Disable the previous IRQ */ up_disable_irq(config->irq); - esp_teardown_irq( -#ifndef CONFIG_ARCH_CHIP_ESP32S2 - this_cpu(), -#endif - config->periph, priv->cpuint); + esp_teardown_irq(config->periph, priv->cpuint); } - priv->cpuint = esp_setup_irq( -#ifndef CONFIG_ARCH_CHIP_ESP32S2 - this_cpu(), -#endif - config->periph, + priv->cpuint = esp_setup_irq(config->periph, ESP_IRQ_PRIORITY_DEFAULT, - ESP_IRQ_TRIGGER_LEVEL); + ESP_IRQ_TRIGGER_LEVEL, + esp_i2c_slave_irq, priv); if (priv->cpuint < 0) { /* Failed to allocate a CPU interrupt of this type. */ @@ -959,23 +925,6 @@ struct i2c_slave_s *esp_i2cbus_slave_initialize(int port, int addr) return NULL; } - ret = irq_attach(config->irq, esp_i2c_slave_irq, priv); - if (ret != OK) - { - /* Failed to attach IRQ, free the allocated CPU interrupt */ - - esp_teardown_irq( -#ifndef CONFIG_ARCH_CHIP_ESP32S2 - this_cpu(), -#endif - config->periph, priv->cpuint); - priv->cpuint = -ENOMEM; - priv->refs--; - nxmutex_unlock(&priv->lock); - - return NULL; - } - /* Enable the CPU interrupt that is linked to the I2C device. */ up_enable_irq(config->irq); diff --git a/arch/xtensa/src/common/espressif/esp_i2s.c b/arch/xtensa/src/common/espressif/esp_i2s.c index 40f4ea4511344..a506d753ee387 100644 --- a/arch/xtensa/src/common/espressif/esp_i2s.c +++ b/arch/xtensa/src/common/espressif/esp_i2s.c @@ -39,34 +39,32 @@ #include #include "xtensa.h" +#include "esp_gpio.h" +#include "esp_irq.h" #include "esp_i2s.h" -#if defined(CONFIG_ARCH_CHIP_ESP32S3) -#include "esp32s3_gpio.h" -#include "hardware/esp32s3_gpio_sigmap.h" -#include "esp32s3_dma.h" -#include "hardware/esp32s3_dma.h" -#include "esp32s3_irq.h" + +#if defined(CONFIG_ARCH_CHIP_ESP32) +# include "esp32_dma.h" #elif defined(CONFIG_ARCH_CHIP_ESP32S2) -#include "esp32s2_gpio.h" -#include "hardware/esp32s2_gpio_sigmap.h" -#include "esp32s2_dma.h" -#include "esp32s2_irq.h" -#else -#include "esp32_gpio.h" -#include "esp32_dma.h" -#include "esp32_irq.h" +# include "espressif/esp_gpio.h" +# include "hardware/esp32s2_gpio_sigmap.h" +# include "esp32s2_dma.h" +#elif defined(CONFIG_ARCH_CHIP_ESP32S3) +# include "hardware/esp32s3_gpio_sigmap.h" +# include "esp32s3_dma.h" +# include "hardware/esp32s3_dma.h" #endif #include "hal/i2s_hal.h" #include "hal/i2s_ll.h" -#include "soc/i2s_periph.h" +#include "hal/i2s_periph.h" #include "soc/i2s_reg.h" #include "hal/i2s_types.h" #include "soc/gpio_sig_map.h" #include "periph_ctrl.h" #if defined(CONFIG_ARCH_CHIP_ESP32S3) # include "soc/gdma_reg.h" -# include "soc/gdma_periph.h" +# include "hal/gdma_periph.h" # include "hal/gdma_ll.h" #endif @@ -82,49 +80,27 @@ ****************************************************************************/ #if defined(CONFIG_ARCH_CHIP_ESP32S3) -#define esp_setup_irq esp32s3_setup_irq -#define esp_teardown_irq esp32s3_teardown_irq -#define esp_configgpio esp32s3_configgpio -#define esp_gpio_matrix_in esp32s3_gpio_matrix_in -#define esp_gpio_matrix_out esp32s3_gpio_matrix_out -#define esp_gpiowrite esp32s3_gpiowrite #define esp_dma_init esp32s3_dma_init #define esp_dma_request esp32s3_dma_request #define esp_dma_setup esp32s3_dma_setup #define esp_dma_load esp32s3_dma_load #define esp_dma_enable esp32s3_dma_enable #define ESP_IRQ_PRIORITY_DEFAULT ESP32S3_INT_PRIO_DEF -#define ESP_IRQ_TRIGGER_LEVEL ESP32S3_CPUINT_LEVEL +#define ESP_IRQ_TRIGGER_LEVEL ESP_IRQ_TRIGGER_LEVEL #define ESPRESSIF_DMA_BUFLEN_MAX ESP32S3_DMA_BUFLEN_MAX #define ESPRESSIF_DMA_PERIPH_I2S ESP32S3_DMA_PERIPH_I2S1 -#define ESP_SOURCE2IRQ ESP32S3_PERIPH2IRQ #define esp_dmadesc_s esp32s3_dmadesc_s #elif defined(CONFIG_ARCH_CHIP_ESP32S2) -#define esp_setup_irq esp32s2_setup_irq -#define esp_teardown_irq esp32s2_teardown_irq -#define esp_configgpio esp32s2_configgpio -#define esp_gpio_matrix_in esp32s2_gpio_matrix_in -#define esp_gpio_matrix_out esp32s2_gpio_matrix_out -#define esp_gpiowrite esp32s2_gpiowrite #define esp_dma_setup esp32s2_dma_init -#define ESP_SOURCE2IRQ ESP32S2_PERIPH2IRQ #define esp_dmadesc_s esp32s2_dmadesc_s #define ESPRESSIF_DMA_BUFLEN_MAX ESP32S2_DMA_DATALEN_MAX #define ESP_IRQ_PRIORITY_DEFAULT ESP32S2_INT_PRIO_DEF -#define ESP_IRQ_TRIGGER_LEVEL ESP32S2_CPUINT_LEVEL #define I2S0O_SD_OUT_IDX I2S0O_DATA_OUT23_IDX #define I2S0I_SD_IN_IDX I2S0I_DATA_IN15_IDX #define I2S0_MCLK_OUT_IDX CLK_I2S_MUX_IDX #elif defined(CONFIG_ARCH_CHIP_ESP32) -#define esp_setup_irq esp32_setup_irq -#define esp_teardown_irq esp32_teardown_irq -#define esp_configgpio esp32_configgpio -#define esp_gpio_matrix_in esp32_gpio_matrix_in -#define esp_gpio_matrix_out esp32_gpio_matrix_out -#define esp_gpiowrite esp32_gpiowrite #define esp_dma_setup esp32_dma_init #define esp_dmadesc_s esp32_dmadesc_s -#define ESP_SOURCE2IRQ ESP32_PERIPH2IRQ #define ESPRESSIF_DMA_BUFLEN_MAX ESP32_DMA_DATALEN_MAX #define I2S0O_SD_OUT_IDX I2S0O_DATA_OUT23_IDX #define I2S0I_SD_IN_IDX I2S0I_DATA_IN15_IDX @@ -133,7 +109,6 @@ #define I2S1I_SD_IN_IDX I2S1I_DATA_IN15_IDX #define I2S1_MCLK_OUT_IDX -1 #define ESP_IRQ_PRIORITY_DEFAULT 1 -#define ESP_IRQ_TRIGGER_LEVEL ESP32_CPUINT_LEVEL #endif #if defined(CONFIG_ESPRESSIF_I2S0_DATA_BIT_WIDTH_8BIT) || \ @@ -343,7 +318,6 @@ typedef enum struct esp_i2s_config_s { uint32_t port; /* I2S port */ - periph_module_t module; /* I2S peripheral module */ uint32_t role; /* I2S port role (master or slave) */ uint8_t data_width; /* I2S sample data width */ uint32_t rate; /* I2S sample-rate */ @@ -588,7 +562,6 @@ i2s_hal_clock_info_t clk_info_i2s0 = static const struct esp_i2s_config_s esp_i2s0_config = { .port = 0, - .module = PERIPH_I2S0_MODULE, #ifdef CONFIG_ESPRESSIF_I2S0_ROLE_MASTER .role = I2S_ROLE_MASTER, #else @@ -662,7 +635,6 @@ i2s_hal_clock_info_t clk_info_i2s1 = static const struct esp_i2s_config_s esp_i2s1_config = { .port = 1, - .module = PERIPH_I2S1_MODULE, #ifdef CONFIG_ESPRESSIF_I2S1_ROLE_MASTER .role = I2S_ROLE_MASTER, #else @@ -1584,8 +1556,6 @@ static void i2s_configure(struct esp_i2s_s *priv) /* Set peripheral clock and clear reset */ - periph_module_enable(priv->config->module); - i2s_hal_init(priv->config->ctx, priv->config->port); I2S_RCC_ATOMIC() { @@ -3094,9 +3064,11 @@ static int i2s_dma_setup(struct esp_i2s_s *priv) { periph = gdma_periph_signals.groups[0].pairs[priv->dma_channel].tx_irq_id; - int cpuint = esp_setup_irq(priv->cpu, - periph, 1, - ESP_IRQ_TRIGGER_LEVEL); + + ASSERT(this_cpu() == priv->cpu); + int cpuint = esp_setup_irq(periph, 1, + ESP_IRQ_TRIGGER_LEVEL, + i2s_interrupt, priv); if (cpuint < 0) { i2serr("Failed to allocate a CPU interrupt.\n"); @@ -3104,15 +3076,6 @@ static int i2s_dma_setup(struct esp_i2s_s *priv) } priv->tx_irq = ESP_SOURCE2IRQ(periph); - ret = irq_attach(priv->tx_irq, i2s_interrupt, priv); - if (ret != OK) - { - i2serr("Couldn't attach IRQ to handler.\n"); - esp_teardown_irq(priv->cpu, - periph, - cpuint); - return ret; - } } # endif /* I2S_HAVE_TX */ @@ -3121,9 +3084,11 @@ static int i2s_dma_setup(struct esp_i2s_s *priv) { periph = gdma_periph_signals.groups[0].pairs[priv->dma_channel].rx_irq_id; - int cpuint = esp_setup_irq(priv->cpu, - periph, 1, - ESP_IRQ_TRIGGER_LEVEL); + + ASSERT(this_cpu() == priv->cpu); + int cpuint = esp_setup_irq(periph, 1, + ESP_IRQ_TRIGGER_LEVEL, + i2s_interrupt, priv); if (cpuint < 0) { i2serr("Failed to allocate a CPU interrupt.\n"); @@ -3131,15 +3096,6 @@ static int i2s_dma_setup(struct esp_i2s_s *priv) } priv->rx_irq = ESP_SOURCE2IRQ(periph); - ret = irq_attach(priv->rx_irq, i2s_interrupt, priv); - if (ret != OK) - { - i2serr("Couldn't attach IRQ to handler.\n"); - esp_teardown_irq(priv->cpu, - periph, - cpuint); - return ret; - } } # endif /* I2S_HAVE_RX */ #else @@ -3153,31 +3109,15 @@ static int i2s_dma_setup(struct esp_i2s_s *priv) priv->cpu = this_cpu(); periph = i2s_periph_signal[priv->config->port].irq; - int cpuint = esp_setup_irq( -# ifndef CONFIG_ARCH_CHIP_ESP32S2 - priv->cpu, -# endif - periph, 1, - ESP_IRQ_TRIGGER_LEVEL); + int cpuint = esp_setup_irq(periph, + ESP_IRQ_PRIORITY_DEFAULT, + ESP_IRQ_TRIGGER_LEVEL, + i2s_interrupt, priv); if (cpuint < 0) { i2serr("Failed to allocate a CPU interrupt.\n"); return ERROR; } - - int irq = ESP_SOURCE2IRQ(periph); - ret = irq_attach(irq, i2s_interrupt, priv); - if (ret != OK) - { - i2serr("Couldn't attach IRQ to handler.\n"); - esp_teardown_irq( -#ifndef CONFIG_ARCH_CHIP_ESP32S2 - priv->cpu, -#endif - periph, - cpuint); - return ret; - } #endif return OK; diff --git a/arch/xtensa/src/common/espressif/esp_irq.c b/arch/xtensa/src/common/espressif/esp_irq.c new file mode 100644 index 0000000000000..618f7074319c7 --- /dev/null +++ b/arch/xtensa/src/common/espressif/esp_irq.c @@ -0,0 +1,955 @@ +/**************************************************************************** + * arch/xtensa/src/common/espressif/esp_irq.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include "xtensa.h" + +#include "esp_irq.h" + +#include "esp_intr_alloc.h" +#include "esp_attr.h" +#include "esp_bit_defs.h" +#include "esp_cpu.h" +#include "esp_rom_sys.h" +#include "rom/ets_sys.h" + +#if defined(CONFIG_ARCH_CHIP_ESP32) +# include "hardware/esp32_soc.h" +# include "esp_gpio.h" +# include "esp32_rtc_gpio.h" +# ifdef CONFIG_SMP +# include "esp32_smp.h" +# define ESP_FROMCPU1_PERIPH ESP32_PERIPH_CPU_CPU1 +# define ESP_FROMCPU1_IRQ ESP32_IRQ_CPU_CPU1 +# define esp_fromcpu1_interrupt esp32_fromcpu1_interrupt +# endif +# define ESP_NCPUINTS ESP32_NCPUINTS +# define ESP_NPERIPHERALS ESP32_NPERIPHERALS +# define ESP_CPUINT_PERIPHSET ESP32_CPUINT_PERIPHSET +# define ESP_IRQ_DEMUX XTENSA_IRQ_DEMUX - ETS_INTERNAL_INTR_SOURCE_OFF +# define ESP_IRQ_SYSCALL XTENSA_IRQ_SYSCALL - ETS_INTERNAL_INTR_SOURCE_OFF +# define ESP_IRQ_FIRSTPERIPH XTENSA_IRQ_FIRSTPERIPH +#elif defined(CONFIG_ARCH_CHIP_ESP32S2) +# include "hardware/esp32s2_soc.h" +# include "esp_gpio.h" +# include "esp32s2_rtc_gpio.h" +# define ESP_NCPUINTS ESP32S2_NCPUINTS +# define ESP_NPERIPHERALS ESP32S2_NPERIPHERALS +# define ESP_CPUINT_PERIPHSET ESP32S2_CPUINT_PERIPHSET +# define ESP_IRQ_DEMUX XTENSA_IRQ_DEMUX - ETS_INTERNAL_INTR_SOURCE_OFF +# define ESP_IRQ_SYSCALL XTENSA_IRQ_SYSCALL - ETS_INTERNAL_INTR_SOURCE_OFF +# define ESP_IRQ_FIRSTPERIPH XTENSA_IRQ_FIRSTPERIPH +#elif defined(CONFIG_ARCH_CHIP_ESP32S3) +# include "hardware/esp32s3_soc.h" +# include "esp_gpio.h" +# include "esp32s3_rtc_gpio.h" +# include "esp32s3_userspace.h" +# ifdef CONFIG_SMP +# include "esp32s3_smp.h" +# define ESP_FROMCPU1_PERIPH ESP32S3_PERIPH_INT_FROM_CPU1 +# define ESP_FROMCPU1_IRQ ESP32S3_IRQ_INT_FROM_CPU1 +# define esp_fromcpu1_interrupt esp32s3_fromcpu1_interrupt +# endif +# define ESP_NCPUINTS ESP32S3_NCPUINTS +# define ESP_NPERIPHERALS ESP32S3_NPERIPHERALS +# define ESP_CPUINT_PERIPHSET ESP32S3_CPUINT_PERIPHSET +# define ESP_IRQ_DEMUX XTENSA_IRQ_DEMUX - ETS_INTERNAL_INTR_SOURCE_OFF +# define ESP_IRQ_SYSCALL XTENSA_IRQ_SYSCALL - ETS_INTERNAL_INTR_SOURCE_OFF +# define ESP_IRQ_FIRSTPERIPH XTENSA_IRQ_FIRSTPERIPH +#endif + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifdef CONFIG_SMP_NCPUS +# define ESP_NCPUS CONFIG_SMP_NCPUS +#else +# define ESP_NCPUS 1 +#endif + +#if defined(CONFIG_ARCH_CHIP_ESP32S3) && defined(CONFIG_BUILD_PROTECTED) +# define esp_pmsirqinitialize() esp32s3_pmsirqinitialize() +#else +# define esp_pmsirqinitialize() +#endif + +#ifdef CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC +# ifndef CONFIG_ARCH_IRQ_TO_NDX +# error "CONFIG_ARCH_IRQ_TO_NDX must be enabled for Xtensa-based \ + Espressif SoCs. Run 'make menuconfig' to select it." +# endif +# if CONFIG_ARCH_NUSER_INTERRUPTS != 2 +# error "CONFIG_ARCH_NUSER_INTERRUPTS must be 2 for Xtensa-based \ + Espressif SoCs. Run 'make menuconfig' to set it." +# endif +#else +# error "CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC must be enabled for \ + Xtensa-based Espressif SoCs. Additionally, enable \ + CONFIG_ARCH_IRQ_TO_NDX and set CONFIG_ARCH_NUSER_INTERRUPTS to 2.\ + Run 'make menuconfig' to select and set these options." +#endif + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static void esp_clear_handle(int cpu, int irq); + +/* External functions from esp_xtensa_intr.c */ + +extern void esp_xtensa_intr_init(void); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Map an IRQ to a handle to which the interrupt source is attached to. */ + +static volatile intr_handle_t g_handle_map[CONFIG_SMP_NCPUS][NR_IRQS]; + +#ifdef CONFIG_ESPRESSIF_IRAM_ISR_DEBUG +/* The g_iram_count keeps track of how many times such an IRQ ran when the + * non-IRAM interrupts were disabled. + */ + +static uint64_t g_iram_count[CONFIG_SMP_NCPUS][NR_IRQS]; +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 15 +/* In the SMP configuration, we will need custom interrupt stacks. + * These definitions provide the aligned stack allocations. + */ + +# define INTSTACK_ALLOC (CONFIG_SMP_NCPUS * INTSTACK_SIZE) + +static uint32_t g_intstackalloc[INTSTACK_ALLOC >> 2]; + +/* These definitions provide the "top" of the push-down stacks. */ + +uintptr_t g_cpu_intstack_top[CONFIG_SMP_NCPUS] = +{ + (uintptr_t)g_intstackalloc + INTSTACK_SIZE, +#if CONFIG_SMP_NCPUS > 1 + (uintptr_t)g_intstackalloc + (2 * INTSTACK_SIZE), +#endif /* CONFIG_SMP_NCPUS > 1 */ +}; +#endif /* defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 15 */ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp_cpuint_initialize + * + * Description: + * Initialize CPU interrupts. + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp_cpuint_initialize(void) +{ + uintptr_t regaddr; + int i; +#ifdef CONFIG_SMP + int cpu; +#endif + +#ifdef CONFIG_SMP + /* Which CPU are we initializing */ + + cpu = this_cpu(); + DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS); +#endif + + /* Initialize the Xtensa interrupt handler table first. + * This MUST be called before any interrupt can fire to ensure + * all handlers are properly initialized to the default handler. + */ + + esp_xtensa_intr_init(); + + /* Disable all CPU interrupts on this CPU */ + + xtensa_disable_all(); +} + +#ifdef CONFIG_ESPRESSIF_IRAM_ISR_DEBUG + +/**************************************************************************** + * Name: esp_iram_interrupt_record + * + * Description: + * This function keeps track of the IRQs that ran when non-IRAM interrupts + * are disabled and enables debugging of the IRAM-enabled interrupts. + * + * Input Parameters: + * irq - The IRQ associated with a CPU interrupt + * cpu - The CPU associated with the CPU interrupt + * + * Returned Value: + * None. + * + ****************************************************************************/ + +IRAM_ATTR static void esp_irq_iram_interrupt_record(int irq, int cpu) +{ + irqstate_t flags = enter_critical_section(); + + g_iram_count[cpu][irq]++; + + leave_critical_section(flags); +} +#endif + +IRAM_ATTR static void isr_adapter_func(void *arg) +{ + struct intr_adapter_from_nuttx *isr_adapter_args; + + isr_adapter_args = (struct intr_adapter_from_nuttx *)arg; + + isr_adapter_args->func(isr_adapter_args->irq, + isr_adapter_args->context, + isr_adapter_args->arg); +} + +/**************************************************************************** + * Name: esp_cpuint_to_irq + * + * Description: + * Find an IRQ associated with a given CPU interrupt by searching through + * g_handle_map. For shared interrupts, multiple IRQs may map to the same + * CPU interrupt - this function returns the first one found. + * + * Input Parameters: + * cpuint - The CPU interrupt number + * cpu - The CPU core + * + * Returned Value: + * The IRQ number, or -1 if not found. + * + ****************************************************************************/ + +IRAM_ATTR static int esp_cpuint_to_irq(int cpuint, int cpu) +{ + int irq; + intr_handle_t handle; + + for (irq = 0; irq < NR_IRQS; irq++) + { + handle = g_handle_map[cpu][irq]; + if (handle != IRQ_UNMAPPED && handle != NULL) + { + if (esp_intr_get_intno(handle) == cpuint && + esp_intr_get_cpu(handle) == cpu) + { + return irq; + } + } + } + + return -1; +} + +/**************************************************************************** + * Name: esp_isr_demultiplexing + * + * Description: + * Demultiplexing interrupt handler. All peripheral interrupts are + * dispatched through this single handler, which then calls the + * appropriate peripheral handler registered via esp_setup_irq. + * + * Input Parameters: + * irq - The IRQ number (XTENSA_IRQ_DEMUX) + * context - Saved processor state + * arg - Unused + * + * Returned Value: + * Always returns OK. + * + ****************************************************************************/ + +IRAM_ATTR static int esp_isr_demultiplexing(int irq, void *context, + void *arg) +{ + int cpuint = esp_get_cpuint(this_cpu(), irq); + intr_handler_t handler; + struct intr_adapter_from_nuttx *handler_arg; + + /* Validate cpuint - if invalid, the interrupt was not properly + * registered via esp_setup_irq. This is a bug that needs to be fixed. + */ + + if (cpuint < 0 || cpuint >= SOC_CPU_INTR_NUM) + { + irqwarn("IRQ %d has invalid cpuint=%d (not registered)", irq, cpuint); + return OK; + } + + handler = (intr_handler_t)esp_cpu_intr_get_handler(cpuint); + handler_arg = (struct intr_adapter_from_nuttx *) + esp_cpu_intr_get_handler_arg(cpuint); + + /* If the handler is the isr_adapter_func, then we need to set the irq + * and context to the handler_arg. This is true for all interrupts set via + * esp_setup_irq. Exceptions are the interrupts set directly by the + * underlying hardware, like Wi-Fi. + */ + + if (handler == &isr_adapter_func) + { + handler_arg->irq = irq; + handler_arg->context = context; + } + + if (handler) + { + (*handler)(handler_arg); + } + else + { + /* Handler not found in _xt_interrupt_table. + * This happens when irq_attach was used instead of esp_setup_irq + * with a non-NULL handler. Peripheral handlers must be set via + * esp_setup_irq() when using ARCH_MINIMAL_VECTORTABLE. + */ + + irqwarn("No handler for irq=%d cpuint=%d\n", irq, cpuint); + } + + return OK; +} + +/**************************************************************************** + * Name: xtensa_attach_fromcpu1_interrupt + ****************************************************************************/ + +#ifdef CONFIG_SMP +static inline void xtensa_attach_fromcpu1_interrupt(void) +{ + int cpuint; + + /* Connect all CPU peripheral source to allocated CPU interrupt */ + + cpuint = esp_setup_irq(ESP_FROMCPU1_PERIPH, 1, + ESP_IRQ_TRIGGER_LEVEL, + esp_fromcpu1_interrupt, NULL); + DEBUGASSERT(cpuint >= 0); + + /* Enable the inter-CPU interrupt. */ + + up_enable_irq(ESP_FROMCPU1_IRQ); +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_irq_to_ndx + * + * Description: + * Irq to ndx + * + ****************************************************************************/ + +IRAM_ATTR int up_irq_to_ndx(int irq) +{ + return irq == XTENSA_IRQ_SYSCALL ? ESP_IRQ_SYSCALL : ESP_IRQ_DEMUX; +} + +/**************************************************************************** + * Name: up_irqinitialize + * + * Description: + * Complete initialization of the interrupt system and enable normal, + * interrupt processing. + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void up_irqinitialize(void) +{ + int i; + int j; + + /* Indicate that no interrupt sources are assigned to CPU interrupts */ + + for (i = 0; i < NR_IRQS; i++) + { + for (j = 0; j < CONFIG_SMP_NCPUS; j++) + { + g_handle_map[j][i] = IRQ_UNMAPPED; + } + } + + /* Initialize CPU interrupts */ + + esp_cpuint_initialize(); + +#ifdef CONFIG_SMP + /* Attach and enable the inter-CPU interrupt */ + + xtensa_attach_fromcpu1_interrupt(); +#endif + + /* Initialize GPIO interrupt support */ + +#ifdef CONFIG_ESPRESSIF_GPIO_IRQ + esp_gpioirqinitialize(); +#endif + + /* Initialize RTCIO interrupt support */ + + esp_rtcioirqinitialize(); + + /* Initialize interrupt handler for the PMS violation ISR */ + + esp_pmsirqinitialize(); + +#ifndef CONFIG_SUPPRESS_INTERRUPTS + /* Attach the demultiplexing interrupt handler */ + + irq_attach(XTENSA_IRQ_DEMUX, esp_isr_demultiplexing, NULL); + + /* Attach the software interrupt - must be done before enabling interrupts + * to avoid unexpected interrupt errors if a syscall happens early. + */ + + irq_attach(XTENSA_IRQ_SYSCALL, xtensa_swint, NULL); + + /* And finally, enable interrupts. Also clears PS.EXCM */ + + xtensa_color_intstack(); + up_irq_enable(); +#endif +} + +/**************************************************************************** + * Name: xtensa_int_decode + * + * Description: + * Determine the peripheral that generated the interrupt and dispatch + * handling to the registered interrupt handler via xtensa_irq_dispatch(). + * + * Input Parameters: + * cpuints - Set of pending interrupts valid for this level + * regs - Saves processor state on the stack + * + * Returned Value: + * Normally the same value as regs is returned. But, in the event of an + * interrupt level context switch, the returned value will, instead point + * to the saved processor state in the TCB of the newly started task. + * + ****************************************************************************/ + +IRAM_ATTR uint32_t *xtensa_int_decode(uint32_t *cpuints, uint32_t *regs) +{ + uint32_t mask; + int bit; + int cpu = this_cpu(); + +#ifdef CONFIG_ARCH_LEDS_CPU_ACTIVITY + board_autoled_on(LED_CPU); +#endif + + /* Skip over zero bits, eight at a time */ + + for (bit = 0, mask = 0xff; + bit < ESP_NCPUINTS && (cpuints[0] & mask) == 0; + bit += 8, mask <<= 8); + + /* Process each pending CPU interrupt */ + + for (; bit < ESP_NCPUINTS && cpuints[0] != 0; bit++) + { + mask = 1 << bit; + if ((cpuints[0] & mask) != 0) + { + /* Extract the IRQ number from the handle map. + * For shared interrupts, multiple IRQs may share the same CPU + * interrupt - we get the first one found. The actual dispatch + * happens through the handler in _xt_interrupt_table. + */ + + int irq = esp_cpuint_to_irq(bit, cpu); + + if (irq < 0) + { + /* No handle found for this CPU interrupt. This can happen + * if the interrupt was triggered but not properly registered. + */ + + irqwarn("No IRQ found for cpuint=%d cpu=%d\n", bit, cpu); + xtensa_intclear(bit); + cpuints[0] &= ~mask; + continue; + } + +#ifdef CONFIG_ESPRESSIF_IRAM_ISR_DEBUG + /* Check if non-IRAM interrupts are disabled */ + + if (esp_intr_noniram_is_disabled(cpu)) + { + /* Sum-up the IRAM-enabled counter associated with the IRQ */ + + esp_irq_iram_interrupt_record(irq, cpu); + } +#endif + + /* Clear software or edge-triggered interrupt */ + + xtensa_intclear(bit); + + /* Dispatch the CPU interrupt. + * + * NOTE that regs may be altered in the case of an interrupt + * level context switch. + */ + + regs = xtensa_irq_dispatch(irq, regs); + + /* Clear the bit in the pending interrupt so that perhaps + * we can exit the look early. + */ + + cpuints[0] &= ~mask; + } + } + + return regs; +} + +/**************************************************************************** + * Name: up_enable_irq + * + * Description: + * Enable the interrupt specified by 'irq'. + * + * Input Parameters: + * irq - IRQ number. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void up_enable_irq(int irq) +{ + esp_err_t ret; + intr_handle_t intr_handle = esp_get_handle(this_cpu(), irq); + + if (intr_handle == IRQ_UNMAPPED) + { + irqwarn("IRQ %d not mapped to handle\n", irq); + return; + } + + ret = esp_intr_enable(intr_handle); + if (ret != ESP_OK) + { + irqerr("Failed to enable interrupt %d\n", irq); + } +} + +/**************************************************************************** + * Name: up_disable_irq + * + * Description: + * Disable the interrupt specified by 'irq'. + * + * Input Parameters: + * irq - IRQ number. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void up_disable_irq(int irq) +{ + esp_err_t ret; + intr_handle_t intr_handle; + + if (irq < XTENSA_IRQ_FIRSTPERIPH) + { + /* Internal interrupt - these are handled differently */ + + return; + } + + intr_handle = esp_get_handle(this_cpu(), irq); + if (intr_handle == IRQ_UNMAPPED) + { + return; + } + + ret = esp_intr_disable(intr_handle); + if (ret != ESP_OK) + { + irqerr("Failed to disable interrupt %d\n", irq); + } +} + +/**************************************************************************** + * Name: esp_setup_irq + * + * Description: + * Configure an IRQ. It allocates a CPU interrupt of the given + * priority and type and attaches a given interrupt source to it. + * + * Input Parameters: + * source - Interrupt source (see irq.h) to be assigned to + * a CPU interrupt. + * priority - Interrupt priority. + * type - Interrupt trigger type. + * handler - Interrupt handler. + * arg - Interrupt handler argument. + * + * Returned Value: + * Allocated CPU interrupt or a negated errno value on failure. + * + ****************************************************************************/ + +int esp_setup_irq(int source, + irq_priority_t priority, + int type, + xcpt_t handler, + void *arg) +{ + return esp_setup_irq_intrstatus(source, priority, type, 0, 0, + handler, arg); +} + +int esp_setup_irq_with_flags(int source, + int flags, + xcpt_t handler, + void *arg) +{ + return esp_setup_irq_with_flags_intrstatus(source, flags, 0, 0, + handler, arg); +} + +int esp_setup_irq_intrstatus(int source, + irq_priority_t priority, + int type, + uint32_t intrstatusreg, + uint32_t intrstatusmask, + xcpt_t handler, + void *arg) +{ + int flags; + + flags = (1 << priority); + flags |= type == ESP_IRQ_TRIGGER_EDGE ? ESP_INTR_FLAG_EDGE : 0; + flags |= ESP_INTR_FLAG_INTRDISABLED; + + return esp_setup_irq_with_flags_intrstatus(source, + flags, + intrstatusreg, + intrstatusmask, + handler, + arg); +} + +int esp_setup_irq_with_flags_intrstatus(int source, + int flags, + uint32_t intrstatusreg, + uint32_t intrstatusmask, + xcpt_t handler, + void *arg) +{ + struct intr_adapter_from_nuttx *isr_adapter_args; + esp_err_t ret; + intr_handle_t ret_handle; + int cpuint; + int irq; + + irqinfo("source = %d\n", source); + + isr_adapter_args = kmm_calloc(1, sizeof(struct intr_adapter_from_nuttx)); + if (isr_adapter_args == NULL) + { + irqerr("Failed to kmm_calloc\n"); + return -EINVAL; + } + + isr_adapter_args->func = handler; + isr_adapter_args->arg = arg; + + ret = esp_intr_alloc_intrstatus(source, + flags, + intrstatusreg, + intrstatusmask, + isr_adapter_func, + isr_adapter_args, + &ret_handle); + if (ret != ESP_OK) + { + irqerr("Failed to allocate interrupt for source %d\n", source); + kmm_free(isr_adapter_args); + return -EINVAL; + } + + cpuint = esp_intr_get_intno(ret_handle); + + if (source < 0) + { + irq = source + ETS_INTERNAL_INTR_SOURCE_OFF; + } + else + { + irq = ESP_SOURCE2IRQ(source); + } + + /* Store the handle. The handle already contains the CPU interrupt and + * CPU information, so no additional mapping is needed. + */ + + esp_set_handle(this_cpu(), irq, ret_handle); + + return cpuint; +} + +/**************************************************************************** + * Name: esp_teardown_irq + * + * Description: + * This function undoes the operations done by esp_setup_irq. + * It detaches an interrupt source from a CPU interrupt and frees the + * CPU interrupt. + * + * Input Parameters: + * source - Interrupt source (see irq.h) to be detached from the + * CPU interrupt. + * cpuint - CPU interrupt from which the interrupt source will + * be detached. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp_teardown_irq(int source, int cpuint) +{ + esp_err_t ret; + int cpu = this_cpu(); + int irq = ESP_SOURCE2IRQ(source); + intr_handle_t intr_handle = esp_get_handle(cpu, irq); + + UNUSED(cpuint); + + if (intr_handle == IRQ_UNMAPPED) + { + irqwarn("No handle found for source %d\n", source); + return; + } + + ret = esp_intr_free(intr_handle); + if (ret != ESP_OK) + { + irqerr("Failed to free interrupt %d\n", source); + } + + esp_clear_handle(cpu, irq); +} + +/**************************************************************************** + * Name: esp_set_handle + * + * Description: + * This function sets the handle associated with an IRQ + * + * Input Parameters: + * cpu - The CPU associated with the IRQ + * irq - The IRQ associated with a CPU interrupt + * handle - The handle to be associated with the IRQ + * + * Returned Value: + * OK on success; A negated errno value on failure. + * + ****************************************************************************/ + +int esp_set_handle(int cpu, int irq, intr_handle_t handle) +{ + intr_handle_t current_handle = g_handle_map[cpu][irq]; + + if (current_handle != IRQ_UNMAPPED) + { + irqinfo("IRQ %d already has a handle\n", irq); + return -EINVAL; + } + + g_handle_map[cpu][irq] = handle; + + return OK; +} + +/**************************************************************************** + * Name: esp_get_handle + * + * Description: + * This function gets the handle associated with an IRQ + * + * Input Parameters: + * cpu - The CPU associated with the IRQ + * irq - The IRQ associated with a CPU interrupt + * + * Returned Value: + * The handle associated with the IRQ or IRQ_UNMAPPED if no handle is + * associated with the IRQ. + * + ****************************************************************************/ + +intr_handle_t esp_get_handle(int cpu, int irq) +{ + return g_handle_map[cpu][irq]; +} + +/**************************************************************************** + * Name: esp_clear_handle + * + * Description: + * This function clears the handle associated with an IRQ + * + * Input Parameters: + * irq - The IRQ associated with a CPU interrupt + * + * Returned Value: + * The handle associated with the IRQ or IRQ_UNMAPPED if no handle is + * associated with the IRQ. + * + ****************************************************************************/ + +static void esp_clear_handle(int cpu, int irq) +{ + g_handle_map[cpu][irq] = IRQ_UNMAPPED; +} + +/**************************************************************************** + * Name: esp_get_cpuint + * + * Description: + * This function returns the CPU interrupt associated with an IRQ + * + * Input Parameters: + * cpu - The CPU associated with the IRQ + * irq - The IRQ associated with a CPU interrupt + * + * Returned Value: + * The CPU interrupt associated with such IRQ or a negated errno value on + * failure. + * + ****************************************************************************/ + +IRAM_ATTR int esp_get_cpuint(int cpu, int irq) +{ + intr_handle_t intr_handle = esp_get_handle(cpu, irq); + + if (intr_handle != IRQ_UNMAPPED && intr_handle != NULL) + { + return esp_intr_get_intno(intr_handle); + } + + return -EINVAL; +} + +/**************************************************************************** + * Name: up_get_intstackbase + * + * Description: + * Return a pointer to the "alloc" the correct interrupt stack allocation + * for the current CPU. + * + ****************************************************************************/ + +#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 15 +uintptr_t up_get_intstackbase(int cpu) +{ + return g_cpu_intstack_top[cpu] - INTSTACK_SIZE; +} +#endif + +/**************************************************************************** + * Name: esp_get_iram_interrupt_records + * + * Description: + * This function copies the vector that keeps track of the IRQs that ran + * when non-IRAM interrupts were disabled. + * + * Input Parameters: + * + * irq_count - A previously allocated pointer to store the counter of the + * interrupts that ran when non-IRAM interrupts were disabled. + * cpu - The CPU to retrieve the interrupt records for + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_ESPRESSIF_IRAM_ISR_DEBUG +void esp_get_iram_interrupt_records(uint64_t *irq_count, int cpu) +{ + irqstate_t flags = enter_critical_section(); + + memcpy(irq_count, &g_iram_count[cpu], sizeof(uint64_t) * NR_IRQS); + + leave_critical_section(flags); +} +#endif diff --git a/arch/xtensa/src/common/espressif/esp_irq.h b/arch/xtensa/src/common/espressif/esp_irq.h new file mode 100644 index 0000000000000..5197d68d73b32 --- /dev/null +++ b/arch/xtensa/src/common/espressif/esp_irq.h @@ -0,0 +1,296 @@ +/**************************************************************************** + * arch/xtensa/src/common/espressif/esp_irq.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_IRQ_H +#define __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_IRQ_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "esp_intr_types.h" +#include "esp_intr_alloc.h" +#include "soc/interrupts.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define IRQ_UNMAPPED (intr_handle_t)NULL + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/* CPU interrupt flags. + * esp_setup_irq() will check bit 1 for IRAM requirement and + * bit 0 for trigger type. + * + * OR'ed values of irq_trigger_e and irq_iram_e define interrupt type. + * | IRAM | TRIGGER | + * Bits | 1 | 0 | + */ + +/* CPU interrupt trigger types */ + +typedef enum irq_trigger_e +{ + ESP_IRQ_TRIGGER_LEVEL = 0, /* Level-triggered interrupts */ + ESP_IRQ_TRIGGER_EDGE = 1, /* Edge-triggered interrupts */ +} irq_trigger_t; + +/* CPU interrupt IRAM enabled */ + +typedef enum irq_iram_e +{ + ESP_IRQ_NON_IRAM = (0 << 1), /* Non-IRAM interrupt */ + ESP_IRQ_IRAM = (1 << 1), /* IRAM interrupt */ +} irq_iram_t; + +/* CPU interrupt priority levels */ + +typedef enum irq_priority_e +{ + ESP_IRQ_PRIORITY_1 = 1, /* Priority Level 1 */ + ESP_IRQ_PRIORITY_2 = 2, /* Priority Level 2 */ + ESP_IRQ_PRIORITY_3 = 3, /* Priority Level 3 */ + ESP_IRQ_PRIORITY_4 = 4, /* Priority Level 4 */ + ESP_IRQ_PRIORITY_5 = 5, /* Priority Level 5 */ + ESP_IRQ_PRIORITY_DEFAULT = ESP_IRQ_PRIORITY_1 /* Default Priority */ +} irq_priority_t; + +/* Adapter from NuttX to Espressif's interrupt handler */ + +struct intr_adapter_from_nuttx +{ + int (*func)(int irq, void *context, void *arg); /* Interrupt callback function */ + int irq; /* Interrupt number */ + void *context; /* Interrupt context */ + void *arg; /* Interrupt private data */ +}; + +struct intr_adapter_to_nuttx +{ + void (*handler)(void *arg); /* Interrupt handler */ + void *arg; /* Interrupt handler argument */ +}; + +/**************************************************************************** + * Public Functions Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp_setup_irq + * + * Description: + * This function sets up the IRQ. It allocates a CPU interrupt of the given + * priority and type and attaches it to a given interrupt source. + * + * Input Parameters: + * source - The interrupt source from irq.h to be assigned to + * a CPU interrupt. + * priority - Interrupt priority. + * type - Interrupt trigger type. + * handler - Interrupt handler. + * arg - Interrupt handler argument. + * + * Returned Value: + * Allocated CPU interrupt on success, or a negated errno on failure. + * + ****************************************************************************/ + +int esp_setup_irq(int source, + irq_priority_t priority, + int type, + xcpt_t handler, + void *arg); + +int esp_setup_irq_with_flags(int source, + int flags, + xcpt_t handler, + void *arg); + +int esp_setup_irq_intrstatus(int source, + irq_priority_t priority, + int type, + uint32_t intrstatusreg, + uint32_t intrstatusmask, + xcpt_t handler, + void *arg); + +int esp_setup_irq_with_flags_intrstatus(int source, + int flags, + uint32_t intrstatusreg, + uint32_t intrstatusmask, + xcpt_t handler, + void *arg); + +/**************************************************************************** + * Name: esp_teardown_irq + * + * Description: + * This function undoes the operations done by esp_setup_irq. + * It detaches an interrupt source from a CPU interrupt and frees the + * CPU interrupt. + * + * Input Parameters: + * source - The interrupt source from irq.h to be detached from the + * CPU interrupt. + * cpuint - The CPU interrupt from which the interrupt source will + * be detached. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp_teardown_irq(int source, int cpuint); + +/**************************************************************************** + * Name: esp_get_cpuint + * + * Description: + * This function returns the CPU interrupt associated with an IRQ + * + * Input Parameters: + * cpu - The CPU associated with the IRQ + * irq - The IRQ associated with a CPU interrupt + * + * Returned Value: + * The CPU interrupt associated with such IRQ or a negated errno value on + * failure. + * + ****************************************************************************/ + +int esp_get_cpuint(int cpu, int irq); + +/**************************************************************************** + * Name: esp_set_handle + * + * Description: + * This function sets the handle associated with an IRQ + * + * Input Parameters: + * cpu - The CPU associated with the IRQ + * irq - The IRQ associated with a CPU interrupt + * handle - The handle to be associated with the IRQ + * + * Returned Value: + * OK on success; A negated errno value on failure. + * + ****************************************************************************/ + +int esp_set_handle(int cpu, int irq, intr_handle_t handle); + +/**************************************************************************** + * Name: esp_get_handle + * + * Description: + * This function gets the handle associated with an IRQ + * + * Input Parameters: + * cpu - The CPU associated with the IRQ + * irq - The IRQ associated with a CPU interrupt + * + * Returned Value: + * The handle associated with the IRQ or IRQ_UNMAPPED if no handle is + * associated with the IRQ. + * + ****************************************************************************/ + +intr_handle_t esp_get_handle(int cpu, int irq); + +/**************************************************************************** + * Name: esp_cpuint_initialize + * + * Description: + * Initialize CPU interrupts. + * + * Input Parameters: + * None. + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned on + * any failure. + * + ****************************************************************************/ + +void esp_cpuint_initialize(void); + +/**************************************************************************** + * Name: esp_get_iram_interrupt_records + * + * Description: + * This function copies the vector that keeps track of the IRQs that ran + * when non-IRAM interrupts were disabled. + * + * Input Parameters: + * + * irq_count - A previously allocated pointer to store the counter of the + * interrupts that ran when non-IRAM interrupts were disabled. + * cpu - The CPU to retrieve the interrupt records for + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_ESPRESSIF_IRAM_ISR_DEBUG +void esp_get_iram_interrupt_records(uint64_t *irq_count, int cpu); +#endif + +/**************************************************************************** + * Name: esp_dump_cpuint_map + * + * Description: + * Dump the contents of g_handle_map for debugging purposes. + * This function is useful when debugging unexpected interrupt handlers. + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp_dump_cpuint_map(void); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_IRQ_H */ diff --git a/arch/xtensa/src/common/espressif/esp_ledc.c b/arch/xtensa/src/common/espressif/esp_ledc.c index 172d89936f6d2..fca32117c9c44 100644 --- a/arch/xtensa/src/common/espressif/esp_ledc.c +++ b/arch/xtensa/src/common/espressif/esp_ledc.c @@ -37,15 +37,15 @@ #include "esp_ledc.h" #include "xtensa.h" -#if defined(CONFIG_ARCH_CHIP_ESP32S3) -#include "esp32s3_gpio.h" -#include "hardware/esp32s3_gpio_sigmap.h" +#if defined(CONFIG_ARCH_CHIP_ESP32) +# include "esp_gpio.h" +# include "hardware/esp32_gpio_sigmap.h" #elif defined(CONFIG_ARCH_CHIP_ESP32S2) -#include "esp32s2_gpio.h" -#include "hardware/esp32s2_gpio_sigmap.h" -#else -#include "esp32_gpio.h" -#include "hardware/esp32_gpio_sigmap.h" +# include "espressif/esp_gpio.h" +# include "hardware/esp32s2_gpio_sigmap.h" +#elif defined(CONFIG_ARCH_CHIP_ESP32S3) +# include "esp_gpio.h" +# include "hardware/esp32s3_gpio_sigmap.h" #endif #include "esp_private/periph_ctrl.h" @@ -61,8 +61,6 @@ ****************************************************************************/ #if defined(CONFIG_ARCH_CHIP_ESP32S3) -# define esp_configgpio esp32s3_configgpio -# define esp_gpio_matrix_out esp32s3_gpio_matrix_out # ifdef CONFIG_ESP32S3_LEDC # define CONFIG_ESPRESSIF_LEDC_CHANNEL0_PIN CONFIG_ESP32S3_LEDC_CHANNEL0_PIN # define CONFIG_ESPRESSIF_LEDC_CHANNEL1_PIN CONFIG_ESP32S3_LEDC_CHANNEL1_PIN @@ -94,8 +92,6 @@ # endif /* CONFIG_ESP32S3_LEDC_TIM3 */ # endif /* CONFIG_ESP32S3_LEDC */ #elif defined(CONFIG_ARCH_CHIP_ESP32S2) -# define esp_configgpio esp32s2_configgpio -# define esp_gpio_matrix_out esp32s2_gpio_matrix_out # ifdef CONFIG_ESP32S2_LEDC # define CONFIG_ESPRESSIF_LEDC_CHANNEL0_PIN CONFIG_ESP32S2_LEDC_CHANNEL0_PIN # define CONFIG_ESPRESSIF_LEDC_CHANNEL1_PIN CONFIG_ESP32S2_LEDC_CHANNEL1_PIN @@ -540,7 +536,6 @@ static bool ledc_ctx_create(void) ledc_hal_init(&(ledc_new_mode_obj->ledc_hal), LEDC_LOW_SPEED_MODE); ledc_new_mode_obj->glb_clk = LEDC_SLOW_CLK_UNINIT; p_ledc_obj = ledc_new_mode_obj; - periph_module_enable(PERIPH_LEDC_MODULE); } } @@ -1235,7 +1230,7 @@ static int ledc_channel_output_enable(ledc_channel_t channel) } ledc_hal_set_sig_out_en(&(p_ledc_obj->ledc_hal), channel, true); - ledc_hal_set_duty_start(&(p_ledc_obj->ledc_hal), channel, true); + ledc_hal_set_duty_start(&(p_ledc_obj->ledc_hal), channel); return OK; } @@ -1270,7 +1265,7 @@ static int ledc_channel_output_disable(ledc_channel_t channel) ledc_hal_set_idle_level(&(p_ledc_obj->ledc_hal), channel, 0); ledc_hal_set_sig_out_en(&(p_ledc_obj->ledc_hal), channel, false); - ledc_hal_set_duty_start(&(p_ledc_obj->ledc_hal), channel, false); + ledc_hal_set_duty_start(&(p_ledc_obj->ledc_hal), channel); leave_critical_section(flags); return OK; @@ -1532,10 +1527,19 @@ static int pwm_shutdown(struct pwm_lowerhalf_s *dev) if (p_ledc_obj != NULL) { - periph_module_disable(PERIPH_LEDC_MODULE); kmm_free(p_ledc_obj); p_ledc_obj = NULL; s_ledc_slow_clk_rc_fast_freq = 0; + LEDC_BUS_CLOCK_ATOMIC() + { + ledc_ll_enable_bus_clock(false); + ledc_ll_enable_reset_reg(true); + } + + LEDC_FUNC_CLOCK_ATOMIC() + { + ledc_ll_enable_clock(LEDC_LL_GET_HW(), false); + } } else { diff --git a/arch/xtensa/src/common/espressif/esp_loader.c b/arch/xtensa/src/common/espressif/esp_loader.c index 62223322502f6..f35720f36d943 100644 --- a/arch/xtensa/src/common/espressif/esp_loader.c +++ b/arch/xtensa/src/common/espressif/esp_loader.c @@ -47,7 +47,7 @@ # include "bootloader_flash_priv.h" #ifdef CONFIG_ESPRESSIF_SIMPLE_BOOT # include "bootloader_init.h" -# include "esp_rom_uart.h" +# include "esp_rom_serial_output.h" # include "esp_rom_sys.h" # include "esp_app_format.h" #endif diff --git a/arch/xtensa/src/common/espressif/esp_mcpwm.c b/arch/xtensa/src/common/espressif/esp_mcpwm.c index 1f1995fcc77c7..0185728594678 100644 --- a/arch/xtensa/src/common/espressif/esp_mcpwm.c +++ b/arch/xtensa/src/common/espressif/esp_mcpwm.c @@ -46,21 +46,22 @@ #include "xtensa.h" #ifdef CONFIG_ARCH_CHIP_ESP32 #include "hardware/esp32_soc.h" -#include "esp32_gpio.h" -#include "esp32_irq.h" +#include "esp_gpio.h" +#include "esp_irq.h" #elif CONFIG_ARCH_CHIP_ESP32S3 #include "hardware/esp32s3_soc.h" -#include "esp32s3_gpio.h" -#include "esp32s3_irq.h" +#include "esp_gpio.h" +#include "esp_irq.h" #endif #include "hal/mcpwm_hal.h" #include "hal/mcpwm_ll.h" #include "hal/mcpwm_types.h" -#include "soc/mcpwm_periph.h" +#include "hal/mcpwm_periph.h" #include "periph_ctrl.h" #include "esp_clk_tree.h" -#include "hal/clk_tree_hal.h" +#include "esp_private/esp_clk_tree_common.h" +#include "soc/clk_tree_defs.h" #ifdef CONFIG_ESP_MCPWM @@ -68,22 +69,10 @@ * Pre-processor Definitions ****************************************************************************/ +#define MCPWM_DEV_CLK_PRESCALE 1 + #define MCPWM_CAPTURE_DEFAULT_GROUP 0 -#ifdef CONFIG_ARCH_CHIP_ESP32 -# define esp_configgpio esp32_configgpio -# define esp_gpio_matrix_in esp32_gpio_matrix_in -# define esp_gpio_matrix_out esp32_gpio_matrix_out -# define esp_setup_irq esp32_setup_irq -# define esp_teardown_irq esp32_teardown_irq -# define ESP_CPUINT_LEVEL ESP32_CPUINT_LEVEL -#elif CONFIG_ARCH_CHIP_ESP32S3 -# define esp_configgpio esp32s3_configgpio -# define esp_gpio_matrix_in esp32s3_gpio_matrix_in -# define esp_gpio_matrix_out esp32s3_gpio_matrix_out -# define esp_setup_irq esp32s3_setup_irq -# define esp_teardown_irq esp32s3_teardown_irq -# define ESP_CPUINT_LEVEL ESP32S3_CPUINT_LEVEL -#endif + #ifdef CONFIG_ESP_MCPWM_MOTOR_BDC /* Peak counter at 13330 in up-down mode allows frequencies at a prescale * of: 2 kHz @ 2; 1.5 kHz @ 3; 1.2 kHz @ 4; 1 kHz @ 5. @@ -154,6 +143,7 @@ struct mcpwm_dev_common_s spinlock_t mcpwm_spinlock; bool initialized; /* MCPWM periph. and HAL has been initialized */ bool isr_initialized; /* Shared ISR has been initialized */ + int group_prescale; }; #ifdef CONFIG_ESP_MCPWM_MOTOR @@ -233,7 +223,7 @@ static void esp_mcpwm_group_start(void); static int esp_mcpwm_capture_set_gpio( struct mcpwm_cap_channel_lowerhalf_s *lower); -/* Upper-half functions required by capture driver */ +/* Lower half methods required by capture driver */ static int esp_capture_start(struct cap_lowerhalf_s *lower); static int esp_capture_stop(struct cap_lowerhalf_s *lower); @@ -309,6 +299,7 @@ static struct mcpwm_dev_common_s g_mcpwm_common = .group.group_id = 0, .initialized = false, .isr_initialized = false, + .group_prescale = MCPWM_DEV_CLK_PRESCALE, }; /* Motor specific data structures */ @@ -419,8 +410,31 @@ static struct mcpwm_cap_channel_lowerhalf_s mcpwm_cap_ch2_lowerhalf = static void esp_mcpwm_group_start(void) { - periph_module_enable(PERIPH_PWM0_MODULE); - mcpwm_hal_init(&g_mcpwm_common.hal, &g_mcpwm_common.group); + mcpwm_hal_context_t *hal = &g_mcpwm_common.hal; + + /* HAL and MCPWM Initialization */ + + PERIPH_RCC_ATOMIC() + { + mcpwm_ll_enable_bus_clock(g_mcpwm_common.group.group_id, true); + mcpwm_ll_reset_register(g_mcpwm_common.group.group_id); + mcpwm_ll_group_enable_clock(g_mcpwm_common.group.group_id, true); + } + + mcpwm_hal_init(hal, &g_mcpwm_common.group); + + esp_clk_tree_enable_src( + (soc_module_clk_t)MCPWM_CAPTURE_CLK_SRC_DEFAULT, true); + + PERIPH_RCC_ATOMIC() + { + mcpwm_ll_group_set_clock_source(g_mcpwm_common.group.group_id, + MCPWM_CAPTURE_CLK_SRC_DEFAULT); + + mcpwm_ll_group_set_clock_prescale(g_mcpwm_common.group.group_id, + g_mcpwm_common.group_prescale); + } + g_mcpwm_common.initialized = true; } @@ -465,7 +479,7 @@ static int esp_motor_setup(struct motor_lowerhalf_s *dev) mtrinfo("State: %d\n", priv->state.state); - esp_clk_tree_src_get_freq_hz(SOC_MOD_CLK_PLL_F160M, + esp_clk_tree_src_get_freq_hz(MCPWM_TIMER_CLK_SRC_DEFAULT, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &base_clock); @@ -1320,7 +1334,7 @@ static int esp_mcpwm_fault_gpio_config(struct mcpwm_motor_lowerhalf_s *lower, if (!enable) { esp_gpio_matrix_in(0x3a, - mcpwm_periph_signals.groups[MCPWM_CAPTURE_DEFAULT_GROUP].\ + soc_mcpwm_signals[MCPWM_CAPTURE_DEFAULT_GROUP].\ gpio_faults[lower->fault_id].fault_sig, false); return OK; @@ -1335,7 +1349,7 @@ static int esp_mcpwm_fault_gpio_config(struct mcpwm_motor_lowerhalf_s *lower, esp_gpio_matrix_in( lower->fault_pin, - mcpwm_periph_signals.groups[MCPWM_CAPTURE_DEFAULT_GROUP].\ + soc_mcpwm_signals[MCPWM_CAPTURE_DEFAULT_GROUP].\ gpio_faults[lower->fault_id].fault_sig, false); @@ -1397,13 +1411,13 @@ static int esp_mcpwm_motor_set_gpio(struct mcpwm_motor_lowerhalf_s *lower, esp_gpio_matrix_out( lower->generator_pins[MCPWM_GENERATOR_0], - mcpwm_periph_signals.groups[MCPWM_CAPTURE_DEFAULT_GROUP].\ + soc_mcpwm_signals[MCPWM_CAPTURE_DEFAULT_GROUP].\ operators[lower->channel_id].generators[MCPWM_GENERATOR_0].pwm_sig, false, false); esp_gpio_matrix_out( lower->generator_pins[MCPWM_GENERATOR_1], - mcpwm_periph_signals.groups[MCPWM_CAPTURE_DEFAULT_GROUP].\ + soc_mcpwm_signals[MCPWM_CAPTURE_DEFAULT_GROUP].\ operators[lower->channel_id].generators[MCPWM_GENERATOR_1].pwm_sig, false, false); @@ -1411,14 +1425,12 @@ static int esp_mcpwm_motor_set_gpio(struct mcpwm_motor_lowerhalf_s *lower, #ifdef CONFIG_ESP_MCPWM_TEST_LOOPBACK esp_gpio_matrix_out(CONFIG_ESP_MCPWM_CAPTURE_CH0_GPIO, - mcpwm_periph_signals.\ - groups[MCPWM_CAPTURE_DEFAULT_GROUP].\ + soc_mcpwm_signals[MCPWM_CAPTURE_DEFAULT_GROUP].\ operators[lower->channel_id].\ generators[MCPWM_GENERATOR_0].pwm_sig, 0, 0); esp_gpio_matrix_out(CONFIG_ESP_MCPWM_CAPTURE_CH1_GPIO, - mcpwm_periph_signals.\ - groups[MCPWM_CAPTURE_DEFAULT_GROUP].\ + soc_mcpwm_signals[MCPWM_CAPTURE_DEFAULT_GROUP].\ operators[lower->channel_id].\ generators[MCPWM_GENERATOR_1].pwm_sig, 0, 0); @@ -1554,6 +1566,9 @@ static int esp_capture_getduty(struct cap_lowerhalf_s *lower, { struct mcpwm_cap_channel_lowerhalf_s *priv = ( struct mcpwm_cap_channel_lowerhalf_s *)lower; + + DEBUGASSERT(priv != NULL); + *duty = priv->duty; cpinfo("Get duty called from channel %d\n", priv->channel_id); return OK; @@ -1582,6 +1597,9 @@ static int esp_capture_getfreq(struct cap_lowerhalf_s *lower, { struct mcpwm_cap_channel_lowerhalf_s *priv = ( struct mcpwm_cap_channel_lowerhalf_s *)lower; + + DEBUGASSERT(priv != NULL); + *freq = priv->freq; cpinfo("Get freq called from channel %d\n", priv->channel_id); return OK; @@ -1641,7 +1659,7 @@ static int esp_mcpwm_capture_set_gpio( mcpwm_hal_context_t *hal = &lower->common->hal; int ret; - ret = esp_configgpio(lower->gpio_pin, INPUT_FUNCTION | INPUT_PULLUP); + ret = esp_configgpio(lower->gpio_pin, INPUT | PULLUP); if (ret < 0) { cperr("Failed configuring GPIO pin\n"); @@ -1650,7 +1668,7 @@ static int esp_mcpwm_capture_set_gpio( esp_gpio_matrix_in( lower->gpio_pin, - mcpwm_periph_signals.groups[MCPWM_CAPTURE_DEFAULT_GROUP].\ + soc_mcpwm_signals[MCPWM_CAPTURE_DEFAULT_GROUP].\ captures[lower->channel_id].cap_sig, false); @@ -1681,26 +1699,22 @@ static int esp_mcpwm_isr_register(int (*fn)(int, void *, void *), void *arg) { int cpuint; int ret; - int cpu = this_cpu(); DEBUGASSERT(fn); - cpuint = esp_setup_irq(cpu, mcpwm_periph_signals.groups[0].irq_id, - 1, ESP_CPUINT_LEVEL); + cpuint = esp_setup_irq(soc_mcpwm_signals[MCPWM_CAPTURE_DEFAULT_GROUP].\ + irq_id, + 1, ESP_IRQ_TRIGGER_LEVEL, + fn, + arg); if (cpuint < 0) { cperr("Failed to allocate a CPU interrupt.\n"); return -ENOMEM; } - ret = irq_attach(mcpwm_periph_signals.groups[0].irq_id + - XTENSA_IRQ_FIRSTPERIPH, fn, arg); - if (ret < 0) - { - cperr("Couldn't attach IRQ to handler.\n"); - esp_teardown_irq(cpu, mcpwm_periph_signals.groups[0].irq_id, cpuint); - return ret; - } + up_enable_irq(ESP_SOURCE2IRQ( + soc_mcpwm_signals[MCPWM_CAPTURE_DEFAULT_GROUP].irq_id)); return ret; } @@ -1989,6 +2003,7 @@ struct motor_lowerhalf_s *esp_motor_bdc_initialize(int channel, struct cap_lowerhalf_s *esp_mcpwm_capture_initialize(int channel, int pin) { struct mcpwm_cap_channel_lowerhalf_s *lower = NULL; + uint32_t group_clock; if (!g_mcpwm_common.initialized) { @@ -1997,8 +2012,7 @@ struct cap_lowerhalf_s *esp_mcpwm_capture_initialize(int channel, int pin) if (!g_mcpwm_common.isr_initialized) { - esp_mcpwm_isr_register(mcpwm_driver_isr_default, - &g_mcpwm_common); + esp_mcpwm_isr_register(mcpwm_driver_isr_default, &g_mcpwm_common); g_mcpwm_common.isr_initialized = true; } @@ -2024,8 +2038,17 @@ struct cap_lowerhalf_s *esp_mcpwm_capture_initialize(int channel, int pin) return NULL; } - lower->clock = clk_hal_apb_get_freq_hz(); + esp_clk_tree_src_get_freq_hz(MCPWM_CAPTURE_CLK_SRC_DEFAULT, + ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, + &group_clock); + + /* Set the clock to be used when calculating frequency */ + lower->gpio_pin = pin; + lower->clock = group_clock / g_mcpwm_common.group_prescale; + + /* Configure GPIO pin */ + esp_mcpwm_capture_set_gpio(lower); return (struct cap_lowerhalf_s *) lower; diff --git a/arch/xtensa/src/common/espressif/esp_openeth.c b/arch/xtensa/src/common/espressif/esp_openeth.c index 130a458f434f2..35019588b8eb3 100644 --- a/arch/xtensa/src/common/espressif/esp_openeth.c +++ b/arch/xtensa/src/common/espressif/esp_openeth.c @@ -514,8 +514,9 @@ int esp_openeth_initialize(void) /* Setup interrupts */ - priv->cpuint = OPENETH_SETUP_IRQ(0, OPENETH_PERIPH_MAC, - 1, OPENETH_CPUINT_LEVEL); + priv->cpuint = OPENETH_SETUP_IRQ(OPENETH_PERIPH_MAC, + 1, OPENETH_CPUINT_LEVEL, + openeth_isr_handler, priv); if (priv->cpuint < 0) { nerr("ERROR: Failed allocate interrupt\n"); @@ -531,10 +532,6 @@ int esp_openeth_initialize(void) "\x00\x02\x03\x04\x05\x06\x07\x08", ETH_ALEN); openeth_set_addr(priv->dev.netdev.d_mac.ether.ether_addr_octet); - /* Attach the interrupt */ - - ret = irq_attach(OPENETH_IRQ_MAC, openeth_isr_handler, priv); - /* Register the device with the OS so that socket IOCTLs can be * performed. */ diff --git a/arch/xtensa/src/common/espressif/esp_pcnt.c b/arch/xtensa/src/common/espressif/esp_pcnt.c index 2a8d42e7620e9..1f594738ade06 100644 --- a/arch/xtensa/src/common/espressif/esp_pcnt.c +++ b/arch/xtensa/src/common/espressif/esp_pcnt.c @@ -47,20 +47,20 @@ #include "esp_pcnt.h" #include "chip.h" #if defined(CONFIG_ARCH_CHIP_ESP32S3) -#include "esp32s3_irq.h" -#include "esp32s3_gpio.h" +#include "esp_irq.h" +#include "esp_gpio.h" #elif defined(CONFIG_ARCH_CHIP_ESP32S2) -#include "esp32s2_irq.h" -#include "esp32s2_gpio.h" +#include "espressif/esp_irq.h" +#include "espressif/esp_gpio.h" #elif defined(CONFIG_ARCH_CHIP_ESP32) -#include "esp32_irq.h" -#include "esp32_gpio.h" +#include "esp_irq.h" +#include "esp_gpio.h" #endif #include "hal/pcnt_hal.h" #include "hal/pcnt_ll.h" #include "periph_ctrl.h" -#include "soc/pcnt_periph.h" +#include "hal/pcnt_periph.h" #include "soc/pcnt_reg.h" #include "soc/pcnt_struct.h" #include "soc/gpio_pins.h" @@ -70,32 +70,23 @@ * Pre-processor Definitions ****************************************************************************/ -#define PCNT_UNIT_COUNT SOC_PCNT_GROUPS * SOC_PCNT_UNITS_PER_GROUP -#define GET_UNIT_ID_FROM_RET_CHAN(chan_id) (int)(chan_id/SOC_PCNT_CHANNELS_PER_UNIT) -#define GET_CHAN_ID_FROM_RET_CHAN(unit_id, chan_id) (chan_id - (SOC_PCNT_CHANNELS_PER_UNIT * unit_id)) -#define CREATE_RET_CHAN_ID(unit_id, chan_id) ((SOC_PCNT_CHANNELS_PER_UNIT * unit_id) + chan_id) +#define PCNT_UNIT_COUNT PCNT_LL_GET(INST_NUM) * PCNT_LL_GET(UNITS_PER_INST) +#define GET_UNIT_ID_FROM_RET_CHAN(chan_id) (int)(chan_id / PCNT_LL_GET(CHANS_PER_UNIT)) +#define GET_CHAN_ID_FROM_RET_CHAN(unit_id, chan_id) (chan_id - (PCNT_LL_GET(CHANS_PER_UNIT) * unit_id)) +#define CREATE_RET_CHAN_ID(unit_id, chan_id) ((PCNT_LL_GET(CHANS_PER_UNIT) * unit_id) + chan_id) #if defined(CONFIG_ARCH_CHIP_ESP32S3) -#define esp_setup_irq esp32s3_setup_irq -#define esp_teardown_irq esp32s3_teardown_irq -#define esp_configgpio esp32s3_configgpio -#define esp_gpio_matrix_in esp32s3_gpio_matrix_in #define ESP_IRQ_PRIORITY_DEFAULT ESP32S3_INT_PRIO_DEF -#define ESP_IRQ_TRIGGER_LEVEL ESP32S3_CPUINT_LEVEL #elif defined(CONFIG_ARCH_CHIP_ESP32S2) -#define esp_setup_irq esp32s2_setup_irq -#define esp_teardown_irq esp32s2_teardown_irq -#define esp_configgpio esp32s2_configgpio -#define esp_gpio_matrix_in esp32s2_gpio_matrix_in #define ESP_IRQ_PRIORITY_DEFAULT ESP32S2_INT_PRIO_DEF -#define ESP_IRQ_TRIGGER_LEVEL ESP32S2_CPUINT_LEVEL #elif defined(CONFIG_ARCH_CHIP_ESP32) -#define esp_setup_irq esp32_setup_irq -#define esp_teardown_irq esp32_teardown_irq -#define esp_configgpio esp32_configgpio -#define esp_gpio_matrix_in esp32_gpio_matrix_in #define ESP_IRQ_PRIORITY_DEFAULT 1 -#define ESP_IRQ_TRIGGER_LEVEL ESP32_CPUINT_LEVEL +#endif + +#if !SOC_RCC_IS_INDEPENDENT +# define PCNT_RCC_ATOMIC() PERIPH_RCC_ATOMIC() +#else +# define PCNT_RCC_ATOMIC() #endif /**************************************************************************** @@ -136,7 +127,7 @@ struct esp_pcnt_priv_s spinlock_t lock; /* Device specific lock. */ int (*cb)(int, void *, void *); /* User defined callback */ uint32_t accum_value; /* Accumulator value of overflowed PCNT unit */ - bool channels[SOC_PCNT_CHANNELS_PER_UNIT]; /* Channel information of PCNT unit */ + bool channels[PCNT_LL_GET(CHANS_PER_UNIT)]; /* Channel information of PCNT unit */ struct esp_pcnt_watch_point_priv_s watchers[PCNT_LL_WATCH_EVENT_MAX]; /* array of PCNT watchers */ }; @@ -148,8 +139,7 @@ static int esp_pcnt_open(struct cap_lowerhalf_s *dev); static int esp_pcnt_close(struct cap_lowerhalf_s *dev); static int IRAM_ATTR esp_pcnt_isr_default(int irq, void *context, void *arg); -static int esp_pcnt_isr_register(int (*fn)(int, void *, void *), - int intr_alloc_flags); +static int esp_pcnt_isr_register(int (*fn)(int, void *, void *), void *arg); static int esp_pcnt_ioctl(struct cap_lowerhalf_s *dev, int cmd, unsigned long arg); static int esp_pcnt_unit_enable(struct cap_lowerhalf_s *dev); @@ -405,13 +395,13 @@ static int IRAM_ATTR esp_pcnt_isr_default(int irq, void *context, struct esp_pcnt_watch_event_data_s data; irqstate_t flags; - for (unit_id = 0; unit_id < SOC_PCNT_UNITS_PER_GROUP; unit_id++) + for (unit_id = 0; unit_id < PCNT_LL_GET(UNITS_PER_INST); unit_id++) { if (intr_status & PCNT_LL_UNIT_WATCH_EVENT(unit_id)) break; } - if (unit_id < SOC_PCNT_UNITS_PER_GROUP) + if (unit_id < PCNT_LL_GET(UNITS_PER_INST)) { unit = &pcnt_units[unit_id]; pcnt_ll_clear_intr_status(ctx.dev, PCNT_LL_UNIT_WATCH_EVENT(unit_id)); @@ -461,7 +451,7 @@ static int IRAM_ATTR esp_pcnt_isr_default(int irq, void *context, * * Input Parameters: * fn - Pointer to the ISR function. - * intr_alloc_flags - Flags for the interrupt allocation. + * arg - Pointer to the argument to be passed to the ISR. * * Returned Value: * Returns OK on successful registration of the ISR; a negated errno value @@ -469,44 +459,29 @@ static int IRAM_ATTR esp_pcnt_isr_default(int irq, void *context, * ****************************************************************************/ -static int esp_pcnt_isr_register(int (*fn)(int, void *, void *), - int intr_alloc_flags) +static int esp_pcnt_isr_register(int (*fn)(int, void *, void *), void *arg) { + struct intr_adapter_from_nuttx *adapter; int cpuint; +#ifndef CONFIG_ARCH_CHIP_ESP32S2 int ret; int cpu = this_cpu(); +#endif DEBUGASSERT(fn); - - cpuint = esp_setup_irq( -#ifndef CONFIG_ARCH_CHIP_ESP32S2 - cpu, -#endif - pcnt_periph_signals.groups[0].irq, + cpuint = esp_setup_irq(soc_pcnt_signals[0].irq_id, ESP_IRQ_PRIORITY_DEFAULT, - ESP_IRQ_TRIGGER_LEVEL); + ESP_IRQ_TRIGGER_LEVEL, + fn, + arg); + if (cpuint < 0) { cperr("Failed to allocate a CPU interrupt.\n"); return ERROR; } - ret = irq_attach((pcnt_periph_signals.groups[0].irq + - XTENSA_IRQ_FIRSTPERIPH), - fn, - 0); - if (ret < 0) - { - cperr("Couldn't attach IRQ to handler.\n"); - esp_teardown_irq( -#ifndef CONFIG_ARCH_CHIP_ESP32S2 - cpu, -#endif - pcnt_periph_signals.groups[0].irq, cpuint); - return ERROR; - } - - up_enable_irq(pcnt_periph_signals.groups[0].irq + XTENSA_IRQ_FIRSTPERIPH); + up_enable_irq(soc_pcnt_signals[0].irq_id + XTENSA_IRQ_FIRSTPERIPH); return OK; } @@ -878,8 +853,12 @@ struct cap_lowerhalf_s *esp_pcnt_new_unit( if (g_pcnt_refs++ == 0) { - periph_module_enable(PERIPH_PCNT_MODULE); - periph_module_reset(PERIPH_PCNT_MODULE); + PCNT_RCC_ATOMIC() + { + pcnt_ll_enable_bus_clock(0, true); + pcnt_ll_reset_register(0); + } + pcnt_hal_init(&ctx, 0); } @@ -985,7 +964,7 @@ int esp_pcnt_del_unit(struct cap_lowerhalf_s *dev) return ERROR; } - for (i = 0; i < SOC_PCNT_CHANNELS_PER_UNIT; i++) + for (i = 0; i < PCNT_LL_GET(CHANS_PER_UNIT); i++) { if (!priv->channels[i]) { @@ -1009,12 +988,12 @@ int esp_pcnt_del_unit(struct cap_lowerhalf_s *dev) g_pcnt_refs--; if (g_pcnt_refs == 0) { - periph_module_disable(PERIPH_PCNT_MODULE); - esp_teardown_irq( -#ifndef CONFIG_ARCH_CHIP_ESP32S2 - cpu, -#endif - pcnt_periph_signals.groups[0].irq, -ENOMEM); + PCNT_RCC_ATOMIC() + { + pcnt_ll_enable_bus_clock(0, false); + } + + esp_teardown_irq(soc_pcnt_signals[0].irq_id, -ENOMEM); } spin_unlock_irqrestore(&priv->lock, flags); @@ -1124,7 +1103,7 @@ int esp_pcnt_unit_add_watch_point(struct cap_lowerhalf_s *dev, else { - int thres_num = SOC_PCNT_THRES_POINT_PER_UNIT - 1; + int thres_num = PCNT_LL_GET(THRES_POINT_PER_UNIT) - 1; switch (thres_num) { case 1: @@ -1279,7 +1258,6 @@ int esp_pcnt_new_channel(struct cap_lowerhalf_s *dev, int gpio_mode; int virt_gpio; int ret_id = 0; - const pcnt_signal_conn_t *chan; if (!config) { @@ -1299,7 +1277,7 @@ int esp_pcnt_new_channel(struct cap_lowerhalf_s *dev, return ERROR; } - for (int i = 0; i < SOC_PCNT_CHANNELS_PER_UNIT; i++) + for (int i = 0; i < PCNT_LL_GET(CHANS_PER_UNIT); i++) { if (!priv->channels[i]) { @@ -1318,13 +1296,13 @@ int esp_pcnt_new_channel(struct cap_lowerhalf_s *dev, (config->flags && ESP_PCNT_CHAN_IO_LOOPBACK ? OUTPUT_FUNCTION : 0); virt_gpio = (config->flags && ESP_PCNT_CHAN_VIRT_LVL_IO_LVL) ? GPIO_MATRIX_CONST_ONE_INPUT : GPIO_MATRIX_CONST_ZERO_INPUT; - chan = &pcnt_periph_signals; if (config->edge_gpio_num >= 0) { esp_configgpio(config->edge_gpio_num, gpio_mode); esp_gpio_matrix_in(config->edge_gpio_num, - chan->groups[0].units[unit_id].channels[channel_id].pulse_sig, + soc_pcnt_signals[0].units[unit_id].channels[channel_id].\ + pulse_sig_id_matrix, (config->flags && ESP_PCNT_CHAN_INVERT_EDGE_IN)); } else @@ -1332,7 +1310,8 @@ int esp_pcnt_new_channel(struct cap_lowerhalf_s *dev, /* using virtual IO */ esp_gpio_matrix_in(virt_gpio, - chan->groups[0].units[unit_id].channels[channel_id].pulse_sig, + soc_pcnt_signals[0].units[unit_id].channels[channel_id].\ + pulse_sig_id_matrix, (config->flags && ESP_PCNT_CHAN_INVERT_EDGE_IN)); } @@ -1340,7 +1319,8 @@ int esp_pcnt_new_channel(struct cap_lowerhalf_s *dev, { esp_configgpio(config->level_gpio_num, gpio_mode); esp_gpio_matrix_in(config->level_gpio_num, - chan->groups[0].units[unit_id].channels[channel_id].control_sig, + soc_pcnt_signals[0].units[unit_id].channels[channel_id].\ + ctl_sig_id_matrix, (config->flags && ESP_PCNT_CHAN_INVERT_LVL_IN)); } else @@ -1348,7 +1328,8 @@ int esp_pcnt_new_channel(struct cap_lowerhalf_s *dev, /* using virtual IO */ esp_gpio_matrix_in(virt_gpio, - chan->groups[0].units[unit_id].channels[channel_id].control_sig, + soc_pcnt_signals[0].units[unit_id].channels[channel_id].\ + ctl_sig_id_matrix, (config->flags && ESP_PCNT_CHAN_INVERT_LVL_IN)); } diff --git a/arch/xtensa/src/common/espressif/esp_pm.c b/arch/xtensa/src/common/espressif/esp_pm.c index 639dd3b737dd1..e161dc0dc9a29 100644 --- a/arch/xtensa/src/common/espressif/esp_pm.c +++ b/arch/xtensa/src/common/espressif/esp_pm.c @@ -31,24 +31,30 @@ #include #include "esp_pm.h" +#include "esp_hr_timer.h" + #ifdef CONFIG_SCHED_TICKLESS -# include "esp_tickless.h" +# if defined(CONFIG_ARCH_CHIP_ESP32) +# include "esp32_tickless.h" +# elif defined(CONFIG_ARCH_CHIP_ESP32S2) +# include "esp32s2_tickless.h" +# elif defined(CONFIG_ARCH_CHIP_ESP32S3) +# include "esp32s3_tickless.h" +# endif #endif #include "esp_sleep.h" #include "soc/rtc.h" #include "esp_sleep_internal.h" #include "esp_pmu.h" +#include "esp_attr.h" +#include "esp_private/pm_impl.h" #ifdef CONFIG_PM_EXT1_WAKEUP # include "driver/rtc_io.h" #endif #ifdef CONFIG_PM_GPIO_WAKEUP # include "driver/gpio.h" # include "hal/gpio_types.h" -# if defined(CONFIG_ARCH_CHIP_ESP32S3) -# include "esp32s3_gpio.h" -# elif defined(CONFIG_ARCH_CHIP_ESP32S2) -# include "esp32s2_gpio.h" -#endif +# include "esp_gpio.h" #endif #ifdef CONFIG_PM_UART_WAKEUP # include "driver/uart_wakeup.h" @@ -60,11 +66,17 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ - -#if defined(CONFIG_ARCH_CHIP_ESP32S3) -#define esp_configgpio esp32s3_configgpio -#elif defined(CONFIG_ARCH_CHIP_ESP32S2) -#define esp_configgpio esp32s2_configgpio +#ifdef CONFIG_PM_EXT0_WAKEUP +# define EXT0_WAIT_TIME_US 5000000 +#endif +#ifdef CONFIG_PM_EXT1_WAKEUP +# define EXT1_WAIT_TIME_US 5000000 +#endif +#ifdef CONFIG_PM_GPIO_WAKEUP +# define GPIO_WAIT_TIME_US 5000000 +#endif +#ifdef CONFIG_PM_UART_WAKEUP +# define UART_WAIT_TIME_US 5000000 #endif /**************************************************************************** @@ -92,7 +104,9 @@ const char *g_wakeup_reasons[] = "" }; -static _Atomic uint32_t pm_wakelock = 0; +static esp_sleep_wakeup_cause_t g_last_wakeup_reason = + ESP_SLEEP_WAKEUP_UNDEFINED; +static uint64_t g_last_wakeup_time = 0; /**************************************************************************** * Private Functions @@ -360,7 +374,60 @@ static uint64_t IRAM_ATTR esp_pm_get_gpio_mask(void) #ifdef CONFIG_PM_GPIO_WAKEUP_GPIO30 io_mask |= BIT(30); #endif - +#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO31 + io_mask |= BIT(31); +#endif +#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO32 + io_mask |= BIT(32); +#endif +#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO33 + io_mask |= BIT(33); +#endif +#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO34 + io_mask |= BIT(34); +#endif +#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO35 + io_mask |= BIT(35); +#endif +#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO36 + io_mask |= BIT(36); +#endif +#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO37 + io_mask |= BIT(37); +#endif +#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO38 + io_mask |= BIT(38); +#endif +#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO39 + io_mask |= BIT(39); +#endif +#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO40 + io_mask |= BIT(40); +#endif +#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO41 + io_mask |= BIT(41); +#endif +#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO42 + io_mask |= BIT(42); +#endif +#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO43 + io_mask |= BIT(43); +#endif +#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO44 + io_mask |= BIT(44); +#endif +#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO45 + io_mask |= BIT(45); +#endif +#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO46 + io_mask |= BIT(46); +#endif +#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO47 + io_mask |= BIT(47); +#endif +#ifdef CONFIG_PM_GPIO_WAKEUP_GPIO48 + io_mask |= BIT(48); +#endif return io_mask; } @@ -435,6 +502,161 @@ static void IRAM_ATTR esp_pm_uart_wakeup_prepare(void) } #endif /* CONFIG_PM_UART_WAKEUP */ +#ifdef CONFIG_ESPRESSIF_AUTO_SLEEP + +/**************************************************************************** + * Name: esp_pm_skip_light_sleep + * + * Description: + * Callback for the power manager's "skip light sleep" hook. This function + * checks if the system should defer entering light sleep after waking up + * from any supported wakeup source (EXT0, EXT1, GPIO, UART). It compares + * the current time to the last wakeup time for each source. If the system + * is still within the configured guard window for any wakeup source, it + * returns true to skip light sleep and let peripheral activity finish. If + * the guard window has elapsed or there was no wakeup, it returns false + * and allows light sleep to proceed. + * + * Placed in IRAM because it runs in timing-critical power management + * decision paths. + * + * Input Parameters: + * None + * + * Returned Value: + * true - Skip light sleep (recent EXT0, EXT1, GPIO, or UART wakeup still + * within the configured guard window). + * false - Allow light sleep (no relevant wakeup or guard window elapsed). + * + ****************************************************************************/ + +static bool IRAM_ATTR esp_pm_skip_light_sleep(void) +{ + bool skip = false; +#if defined(CONFIG_PM_EXT0_WAKEUP) || \ + defined(CONFIG_PM_EXT1_WAKEUP) || \ + defined(CONFIG_PM_GPIO_WAKEUP) || \ + defined(CONFIG_PM_UART_WAKEUP) + uint64_t current_time = esp_hr_timer_time_us(); +#endif + +#ifdef CONFIG_PM_EXT0_WAKEUP + if (g_last_wakeup_reason == ESP_SLEEP_WAKEUP_EXT0 && + current_time < (g_last_wakeup_time + EXT0_WAIT_TIME_US)) + { + pwrinfo("EXT0 wakeup still within guard window\n"); + skip = true; + } +#endif + +#ifdef CONFIG_PM_EXT1_WAKEUP + if (g_last_wakeup_reason == ESP_SLEEP_WAKEUP_EXT1 && + current_time < (g_last_wakeup_time + EXT1_WAIT_TIME_US)) + { + pwrinfo("EXT1 wakeup still within guard window\n"); + skip = true; + } +#endif + +#ifdef CONFIG_PM_GPIO_WAKEUP + if (g_last_wakeup_reason == ESP_SLEEP_WAKEUP_GPIO && + current_time < (g_last_wakeup_time + GPIO_WAIT_TIME_US)) + { + pwrinfo("GPIO wakeup still within guard window\n"); + skip = true; + } +#endif + +#ifdef CONFIG_PM_UART_WAKEUP + if (g_last_wakeup_reason == ESP_SLEEP_WAKEUP_UART && + current_time < (g_last_wakeup_time + UART_WAIT_TIME_US)) + { + pwrinfo("UART wakeup still within guard window\n"); + skip = true; + } +#endif + + return skip; +} + +/**************************************************************************** + * Name: esp_pm_light_sleep_exit_cb + * + * Description: + * Store wakeup reason and timestamp on light sleep exit. + * + * Input Parameters: + * sleep_time_us - Actual sleep time in microseconds (unused). + * arg - User callback argument (unused). + * + * Returned Value: + * ESP_OK + * + ****************************************************************************/ + +static esp_err_t IRAM_ATTR esp_pm_light_sleep_exit_cb(int64_t sleep_time_us, + void *arg) +{ + esp_sleep_wakeup_cause_t wc; + uint64_t tw; + + UNUSED(sleep_time_us); + UNUSED(arg); + + wc = esp_sleep_get_wakeup_cause(); + tw = esp_hr_timer_time_us(); + + esp_pm_wakeup_set_last_reason((int32_t)wc); + esp_pm_wakeup_set_last_time(tw); + + return ESP_OK; +} +#endif /* CONFIG_ESPRESSIF_AUTO_SLEEP */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp_pm_wakeup_set_last_reason + * + * Description: + * Store the sleep exit wakeup cause after light sleep. + * + * Input Parameters: + * reason - Value from esp_sleep_get_wakeup_cause(). + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp_pm_wakeup_set_last_reason(int32_t reason) +{ + g_last_wakeup_reason = reason; +} + +/**************************************************************************** + * Name: esp_pm_wakeup_set_last_time + * + * Description: + * Store the high-resolution timestamp (microseconds) for the last light + * sleep exit, together with the cause from + * esp_pm_wakeup_set_last_reason(). + * + * Input Parameters: + * time_us - Time from esp_hr_timer_time_us() at exit from light sleep. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp_pm_wakeup_set_last_time(uint64_t time_us) +{ + g_last_wakeup_time = time_us; +} + /**************************************************************************** * Name: esp_pm_sleep_enable_timer_wakeup * @@ -449,15 +671,11 @@ static void IRAM_ATTR esp_pm_uart_wakeup_prepare(void) * ****************************************************************************/ -static void esp_pm_sleep_enable_timer_wakeup(uint64_t time_in_us) +void esp_pm_sleep_enable_timer_wakeup(uint64_t time_in_us) { esp_sleep_enable_timer_wakeup(time_in_us); } -/**************************************************************************** - * Public Functions - ****************************************************************************/ - /**************************************************************************** * Name: esp_pm_light_sleep_start * @@ -601,59 +819,85 @@ void esp_pmsleep(uint64_t time_in_us) esp_pm_deep_sleep_start(); } +#ifdef CONFIG_ESPRESSIF_AUTO_SLEEP + /**************************************************************************** - * Name: esp_pm_lockacquire + * Name: esp_pmconfigure * * Description: - * Take a power management lock + * Configure power manager. * * Input Parameters: - * None + * None. * * Returned Value: - * None + * Returns OK on success; a negated errno value on failure. * ****************************************************************************/ -void IRAM_ATTR esp_pm_lockacquire(void) +int esp_pmconfigure(void) { - ++pm_wakelock; -} + int ret; + esp_err_t err = ESP_OK; +#ifdef CONFIG_PM_EXT1_WAKEUP + int64_t ext1_mask; +#endif +#ifdef CONFIG_PM_GPIO_WAKEUP + int64_t gpio_mask; +#endif + esp_pm_config_t pm_config = + { + .max_freq_mhz = CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ, + .min_freq_mhz = CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ, +#ifdef CONFIG_ESPRESSIF_AUTO_SLEEP + .light_sleep_enable = true +#endif + }; -/**************************************************************************** - * Name: esp_pm_lockrelease - * - * Description: - * Release the lock taken using esp_pm_lockacquire. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ + ret = esp_pm_configure(&pm_config); + if (ret != OK) + { + return ret; + } -void IRAM_ATTR esp_pm_lockrelease(void) -{ - --pm_wakelock; -} +#ifdef CONFIG_PM_EXT0_WAKEUP + esp_pm_ext0_wakeup_prepare(); +#endif +#ifdef CONFIG_PM_EXT1_WAKEUP + esp_pm_ext1_wakeup_prepare(); +#endif +#ifdef CONFIG_PM_GPIO_WAKEUP + esp_pm_gpio_wakeup_prepare(); +#endif +#ifdef CONFIG_PM_UART_WAKEUP + esp_pm_uart_wakeup_prepare(); +#endif /* CONFIG_PM_UART_WAKEUP */ -/**************************************************************************** - * Name: esp_pm_lockstatus - * - * Description: - * Return power management lock status. - * - * Input Parameters: - * None - * - * Returned Value: - * Current pm_wakelock count - * - ****************************************************************************/ + err = esp_pm_register_skip_light_sleep_callback( + esp_pm_skip_light_sleep); + if (err != ESP_OK) + { + pwrerr("Failed to register skip light sleep callback: %d\n", err); + return -ENOMEM; + } -uint32_t IRAM_ATTR esp_pm_lockstatus(void) -{ - return pm_wakelock; + esp_pm_sleep_cbs_register_config_t sleep_cbs = + { + .enter_cb = NULL, + .exit_cb = esp_pm_light_sleep_exit_cb, + .enter_cb_user_arg = NULL, + .exit_cb_user_arg = NULL, + .enter_cb_prior = 0, + .exit_cb_prior = 0, + }; + + err = esp_pm_light_sleep_register_cbs(&sleep_cbs); + if (err != ESP_OK) + { + pwrerr("Failed to register light sleep callbacks: %d\n", err); + return -ENOMEM; + } + + return ret; } +#endif /* CONFIG_ESPRESSIF_AUTO_SLEEP */ diff --git a/arch/xtensa/src/common/espressif/esp_pm.h b/arch/xtensa/src/common/espressif/esp_pm.h index c12cff991c8e9..7c3c1dfe56993 100644 --- a/arch/xtensa/src/common/espressif/esp_pm.h +++ b/arch/xtensa/src/common/espressif/esp_pm.h @@ -44,11 +44,32 @@ extern "C" #endif #ifdef CONFIG_PM +/**************************************************************************** + * Public Types + ****************************************************************************/ + +typedef bool (*skip_light_sleep_cb_t)(void); /**************************************************************************** * Public Function Prototypes ****************************************************************************/ +/**************************************************************************** + * Name: esp_pm_sleep_enable_timer_wakeup + * + * Description: + * Configure wakeup interval + * + * Input Parameters: + * time_in_us - Sleep duration in microseconds. + * + * Returned Value: + * None + * + ****************************************************************************/ + +void esp_pm_sleep_enable_timer_wakeup(uint64_t time_in_us); + /**************************************************************************** * Name: esp_pm_light_sleep_start * @@ -115,52 +136,57 @@ void esp_pmstandby(uint64_t time_in_us); void esp_pmsleep(uint64_t time_in_us); /**************************************************************************** - * Name: esp_pm_lockacquire + * Name: esp_pmconfigure * * Description: - * Take a power management lock + * Configure power manager. * * Input Parameters: * None * * Returned Value: - * None + * Returns OK on success; a negated errno value on failure. * ****************************************************************************/ -void esp_pm_lockacquire(void); +#ifdef CONFIG_ESPRESSIF_AUTO_SLEEP +int esp_pmconfigure(void); +#endif /**************************************************************************** - * Name: esp_pm_lockrelease + * Name: esp_pm_wakeup_set_last_reason * * Description: - * Release the lock taken using esp_pm_lockacquire. + * Store the sleep exit wakeup cause after light sleep. Used with + * esp_pm_wakeup_set_last_time() so the skip-light-sleep hook can + * detect a recent UART wakeup. * * Input Parameters: - * None + * reason - Value from esp_sleep_get_wakeup_cause(). * * Returned Value: * None * ****************************************************************************/ -void esp_pm_lockrelease(void); +void esp_pm_wakeup_set_last_reason(int32_t reason); /**************************************************************************** - * Name: esp_pm_lockstatus + * Name: esp_pm_wakeup_set_last_time * * Description: - * Return power management lock status. + * Store the high-resolution timestamp (microseconds) aligned with + * the wakeup cause set by esp_pm_wakeup_set_last_reason(). * * Input Parameters: - * None + * time_us - Time from esp_hr_timer_time_us() at exit from light sleep. * * Returned Value: - * Current pm_wakelock count + * None * ****************************************************************************/ -uint32_t esp_pm_lockstatus(void); +void esp_pm_wakeup_set_last_time(uint64_t time_us); #endif /* CONFIG_PM */ diff --git a/arch/xtensa/src/common/espressif/esp_rmt.c b/arch/xtensa/src/common/espressif/esp_rmt.c index 7e7a9ccb7cc2a..2108962474a3e 100644 --- a/arch/xtensa/src/common/espressif/esp_rmt.c +++ b/arch/xtensa/src/common/espressif/esp_rmt.c @@ -43,29 +43,16 @@ #include #include -#include "xtensa.h" -#ifdef CONFIG_ARCH_CHIP_ESP32 -#include "hardware/esp32_soc.h" -#include "esp32_gpio.h" -#include "esp32_irq.h" -#elif CONFIG_ARCH_CHIP_ESP32S2 -#include "hardware/esp32s2_soc.h" -#include "esp32s2_gpio.h" -#include "esp32s2_irq.h" -#elif CONFIG_ARCH_CHIP_ESP32S3 -#include "hardware/esp32s3_soc.h" -#include "esp32s3_gpio.h" -#include "esp32s3_irq.h" -#endif +#include "esp_irq.h" -#include "hal/gpio_types.h" -#include "hal/rmt_hal.h" -#include "hal/rmt_ll.h" -#include "periph_ctrl.h" -#include "soc/gpio_sig_map.h" -#include "soc/rmt_periph.h" -#include "soc/soc_caps.h" -#include "esp_clk_tree.h" +#include "esp_err.h" +#include "driver/rmt_types.h" +#include "driver/rmt_rx.h" +#include "driver/rmt_tx.h" +#include "driver/rmt_encoder.h" +#include "driver/rmt_common.h" +#include "esp_private/rmt.h" +#include "rmt_private.h" #include "esp_rmt.h" @@ -88,186 +75,22 @@ #define RMT_ENCODE_RX_CHANNEL(decode_chan) \ ((decode_chan + RMT_RX_CHANNEL_ENCODING_START)) -/* Default configuration for TX channel */ - -#define RMT_DEFAULT_CONFIG_TX(gpio, channel_id) \ - { \ - .rmt_mode = RMT_MODE_TX, \ - .channel = channel_id, \ - .gpio_num = gpio, \ - .clk_div = RMT_DEFAULT_CLK_DIV, \ - .mem_block_num = 1, \ - .flags = 0, \ - .tx_config = { \ - .carrier_freq_hz = 38000, \ - .carrier_level = RMT_CARRIER_LEVEL_HIGH, \ - .idle_level = RMT_IDLE_LEVEL_LOW, \ - .carrier_duty_percent = 33, \ - .loop_count = 0, \ - .carrier_en = false, \ - .loop_en = false, \ - .idle_output_en = true, \ - } \ - } - -/* Default configuration for RX channel */ - -#define RMT_DEFAULT_CONFIG_RX(gpio, channel_id) \ - { \ - .rmt_mode = RMT_MODE_RX, \ - .channel = channel_id, \ - .gpio_num = gpio, \ - .clk_div = RMT_DEFAULT_CLK_DIV, \ - .mem_block_num = 1, \ - .flags = 0, \ - .rx_config = { \ - .idle_threshold = 12000, \ - .filter_ticks_thresh = 100, \ - .filter_en = true, \ - } \ - } - -#define rmt_item32_t rmt_symbol_word_t - -#ifdef CONFIG_ARCH_CHIP_ESP32 -# define esp_configgpio esp32_configgpio -# define esp_gpio_matrix_out esp32_gpio_matrix_out -# define esp_gpio_matrix_in esp32_gpio_matrix_in -# define esp_setup_irq esp32_setup_irq -# define esp_teardown_irq esp32_teardown_irq - -# define GPIO_OUT_FUNC OUTPUT_FUNCTION_3 -# define GPIO_IN_FUNC INPUT_FUNCTION_3 -# define ESP_CPUINT_LEVEL ESP32_CPUINT_LEVEL - -#elif CONFIG_ARCH_CHIP_ESP32S2 -# define esp_configgpio esp32s2_configgpio -# define esp_gpio_matrix_out esp32s2_gpio_matrix_out -# define esp_gpio_matrix_in esp32s2_gpio_matrix_in -# define esp_setup_irq esp32s2_setup_irq -# define esp_teardown_irq esp32s2_teardown_irq - -# define GPIO_OUT_FUNC OUTPUT_FUNCTION_2 -# define GPIO_IN_FUNC INPUT_FUNCTION_2 -# define ESP_CPUINT_LEVEL ESP32S2_CPUINT_LEVEL - -#elif CONFIG_ARCH_CHIP_ESP32S3 -# define esp_configgpio esp32s3_configgpio -# define esp_gpio_matrix_out esp32s3_gpio_matrix_out -# define esp_gpio_matrix_in esp32s3_gpio_matrix_in -# define esp_setup_irq esp32s3_setup_irq -# define esp_teardown_irq esp32s3_teardown_irq - -# define GPIO_OUT_FUNC OUTPUT_FUNCTION_2 -# define GPIO_IN_FUNC INPUT_FUNCTION_2 -# define ESP_CPUINT_LEVEL ESP32S3_CPUINT_LEVEL +#if SOC_PERIPH_CLK_CTRL_SHARED +#define RMT_CLOCK_SRC_ATOMIC() PERIPH_RCC_ATOMIC() +#else +#define RMT_CLOCK_SRC_ATOMIC() +#endif +#if !SOC_RCC_IS_INDEPENDENT +#define RMT_RCC_ATOMIC() PERIPH_RCC_ATOMIC() +#else +#define RMT_RCC_ATOMIC() #endif /**************************************************************************** * Private Types ****************************************************************************/ -/* RMT channel ID */ - -enum rmt_channel_e -{ - RMT_CHANNEL_0, /* RMT channel number 0 */ - RMT_CHANNEL_1, /* RMT channel number 1 */ - RMT_CHANNEL_2, /* RMT channel number 2 */ - RMT_CHANNEL_3, /* RMT channel number 3 */ -#if SOC_RMT_CHANNELS_PER_GROUP > 4 - RMT_CHANNEL_4, /* RMT channel number 4 */ - RMT_CHANNEL_5, /* RMT channel number 5 */ - RMT_CHANNEL_6, /* RMT channel number 6 */ - RMT_CHANNEL_7, /* RMT channel number 7 */ -#endif - RMT_CHANNEL_MAX /* Number of RMT channels */ -}; - -typedef enum rmt_channel_e rmt_channel_t; - -/* RMT Channel Working Mode (TX or RX) */ - -enum rmt_mode_e -{ - RMT_MODE_TX, /* RMT TX mode */ - RMT_MODE_RX, /* RMT RX mode */ - RMT_MODE_MAX -}; - -typedef enum rmt_mode_e rmt_mode_t; - -/* RMT Idle Level */ - -enum rmt_idle_level_e -{ - RMT_IDLE_LEVEL_LOW, /* RMT TX idle level: low Level */ - RMT_IDLE_LEVEL_HIGH, /* RMT TX idle level: high Level */ - RMT_IDLE_LEVEL_MAX, -}; - -typedef enum rmt_idle_level_e rmt_idle_level_t; - -/* RMT Carrier Level */ - -enum rmt_carrier_level_e -{ - RMT_CARRIER_LEVEL_LOW, /* RMT carrier wave is modulated for low Level output */ - RMT_CARRIER_LEVEL_HIGH, /* RMT carrier wave is modulated for high Level output */ - RMT_CARRIER_LEVEL_MAX -}; - -typedef enum rmt_carrier_level_e rmt_carrier_level_t; - -/* RMT Channel Status */ - -enum rmt_channel_status_e -{ - RMT_CHANNEL_UNINIT, /* RMT channel uninitialized */ - RMT_CHANNEL_IDLE, /* RMT channel status idle */ - RMT_CHANNEL_BUSY, /* RMT channel status busy */ -}; - -typedef enum rmt_channel_status_e rmt_channel_status_t; - -/* RMT hardware memory layout */ - -struct rmt_channel_data_s -{ - volatile rmt_item32_t data32[SOC_RMT_MEM_WORDS_PER_CHANNEL]; -}; - -struct rmt_mem_s -{ - struct rmt_channel_data_s chan[SOC_RMT_CHANNELS_PER_GROUP]; -}; - -typedef struct rmt_mem_s rmt_mem_t; - -struct rmt_dev_common_s -{ - rmt_hal_context_t hal; /* HAL context */ - rmutex_t rmt_driver_isr_lock; - - /* Mutex lock for protecting concurrent register/unregister of the RMT - * channels' ISR. - */ - - spinlock_t rmt_spinlock; - - /* Bitmask of installed drivers' channels, used to protect concurrent - * register/unregister of the RMT channels' ISR. - */ - - uint8_t rmt_driver_channels; - bool rmt_module_enabled; - - /* Bitmap of channels already added in the synchronous group */ - - uint32_t synchro_channel_mask; -}; - struct rmt_dev_lowerhalf_s { /* The following block is part of the upper-half device struct */ @@ -279,118 +102,19 @@ struct rmt_dev_lowerhalf_s /* The following is private to the ESP32 RMT driver */ - rmt_mode_t mode; - struct rmt_dev_common_s *common; /* RMT peripheral common parameters */ -}; - -struct rmt_obj_s -{ - size_t tx_offset; - size_t tx_len_rem; - size_t tx_sub_len; - bool wait_done; /* Mark whether wait tx done */ - bool loop_autostop; /* Mark whether loop auto-stop is enabled */ - rmt_channel_t channel; - const rmt_item32_t *tx_data; - sem_t tx_sem; -#ifdef CONFIG_SPIRAM_USE_MALLOC - int intr_alloc_flags; - sem_t tx_sem_buffer; -#endif - rmt_item32_t *tx_buf; - struct circbuf_s rx_buf; - sem_t rx_sem; -#ifdef SOC_RMT_SUPPORT_RX_PINGPONG - rmt_item32_t *rx_item_buf; - uint32_t rx_item_buf_size; - uint32_t rx_item_len; - int rx_item_start_idx; -#endif - void *tx_context; - size_t sample_size_remain; - const uint8_t *sample_cur; -}; - -typedef struct rmt_obj_s rmt_obj_t; - -/* Data struct of RMT TX configure parameters */ - -struct rmt_tx_config_s -{ - uint32_t carrier_freq_hz; /* RMT carrier frequency */ - rmt_carrier_level_t carrier_level; /* Level of the RMT output, when the carrier is applied */ - rmt_idle_level_t idle_level; /* RMT idle level */ - uint8_t carrier_duty_percent; /* RMT carrier duty (%) */ - uint32_t loop_count; /* Maximum loop count, only take effect for chips that is capable of `SOC_RMT_SUPPORT_TX_LOOP_COUNT` */ - bool carrier_en; /* RMT carrier enable */ - bool loop_en; /* Enable sending RMT items in a loop */ - bool idle_output_en; /* RMT idle level output enable */ -}; - -/* Data struct of RMT RX configure parameters */ - -struct rmt_rx_config_s -{ - uint16_t idle_threshold; /* RMT RX idle threshold */ - uint8_t filter_ticks_thresh; /* RMT filter tick number */ - bool filter_en; /* RMT receiver filter enable */ -#if SOC_RMT_SUPPORT_RX_DEMODULATION - bool rm_carrier; /* RMT receiver remove carrier enable */ - uint32_t carrier_freq_hz; /* RMT carrier frequency */ - uint8_t carrier_duty_percent; /* RMT carrier duty (%) */ - rmt_carrier_level_t carrier_level; /* The level to remove the carrier */ -#endif -}; - -struct rmt_channel_config_s -{ - rmt_mode_t rmt_mode; /* RMT mode: transmitter or receiver */ - rmt_channel_t channel; /* RMT channel */ - int gpio_num; /* RMT GPIO number */ - uint8_t clk_div; /* RMT channel counter divider */ - uint8_t mem_block_num; /* RMT memory block number */ - uint32_t flags; /* RMT channel extra configurations, OR'd with RMT_CHANNEL_FLAGS_[*] */ - union - { - struct rmt_tx_config_s tx_config; /* RMT TX parameter */ - struct rmt_rx_config_s rx_config; /* RMT RX parameter */ - }; + rmt_channel_handle_t handle; + rmt_encoder_handle_t encoder; }; /**************************************************************************** * Private Function Prototypes ****************************************************************************/ -static void rmt_module_enable(void); -static int rmt_rx_start(rmt_channel_t channel, bool rx_idx_rst); -static int rmt_tx_start(rmt_channel_t channel, bool tx_idx_rst); -static int rmt_set_tx_loop_mode(rmt_channel_t channel, bool loop_en); -static int rmt_set_tx_thr_intr_en(rmt_channel_t channel, bool en, - uint16_t evt_thresh); -static int rmt_set_gpio(rmt_channel_t channel, rmt_mode_t mode, - gpio_num_t gpio_num, bool invert_signal); -static bool rmt_is_channel_number_valid(rmt_channel_t channel, uint8_t mode); -static int rmt_internal_config(rmt_dev_t *dev, - const struct rmt_channel_config_s *rmt_param); -static int rmt_config(const struct rmt_channel_config_s *rmt_param); -static void rmt_fill_memory(rmt_channel_t channel, const rmt_item32_t *item, - uint16_t item_num, uint16_t mem_offset); -static int rmt_isr_register(int (*fn)(int, void *, void *), void *arg, - int intr_alloc_flags); -static int rmt_driver_isr_default(int irq, void *context, void *arg); -static int rmt_driver_install(rmt_channel_t channel, size_t rx_buf_size, - int intr_alloc_flags); -static int rmt_write_items(rmt_channel_t channel, - const rmt_item32_t *rmt_item, - int item_num, - bool wait_tx_done); static ssize_t esp_rmt_read(struct rmt_dev_s *dev, char *buffer, - size_t buflen); + size_t buflen); static ssize_t esp_rmt_write(struct rmt_dev_s *dev, const char *buffer, size_t buflen); -static struct rmt_dev_s - *esp_rmtinitialize(struct rmt_channel_config_s config); /**************************************************************************** * Private Data @@ -402,1592 +126,334 @@ static const struct rmt_ops_s g_rmtops = .write = esp_rmt_write, }; -static struct rmt_dev_common_s g_rmtdev_common = -{ - .hal.regs = &RMT, - .rmt_driver_isr_lock = NXRMUTEX_INITIALIZER, - .rmt_driver_channels = 0, - .rmt_module_enabled = false, - .synchro_channel_mask = 0 -}; - -static struct rmt_obj_s *p_rmt_obj[RMT_CHANNEL_MAX]; - -#ifdef CONFIG_RMT_LOOP_TEST_MODE -static rmt_channel_t g_tx_channel = RMT_CHANNEL_MAX; -static rmt_channel_t g_rx_channel = RMT_CHANNEL_MAX; -#endif - -#if SOC_RMT_CHANNEL_CLK_INDEPENDENT -uint32_t g_rmt_source_clock_hz[RMT_CHANNEL_MAX]; -#else -uint32_t g_rmt_source_clock_hz; -#endif - -/* RMTMEM address is declared in .peripherals.ld */ - -extern rmt_mem_t RMTMEM; - /**************************************************************************** * Private Functions ****************************************************************************/ /**************************************************************************** - * Name: rmt_module_enable + * Name: esp_rmt_read * * Description: - * This function enables the RMT (Remote Control) module if it's not - * already enabled. + * This function reads data from the RMT device. + * It starts the RMT module in receiving mode for a specific channel and + * checks for any errors. If an error occurs during the start of the RMT + * module, it returns the error code. Please note that this function + * starts the receiver, but the actual data is read from the ring buffer + * by the upper half driver. * * Input Parameters: - * None. + * dev - Pointer to the RMT device structure. + * buffer - Pointer to the buffer where the read data should be stored. + * buflen - The maximum amount of data to be read. * * Returned Value: - * None. + * Returns the number of bytes read from the RMT device; a negated errno + * value is returned on any failure. * ****************************************************************************/ -static void rmt_module_enable(void) +static ssize_t esp_rmt_read(struct rmt_dev_s *dev, char *buffer, + size_t buflen) { - irqstate_t flags; + esp_err_t esp_ret; + struct rmt_dev_lowerhalf_s *priv = (struct rmt_dev_lowerhalf_s *)dev; + rmt_receive_config_t receive_config = + { + .signal_range_min_ns = 1250, + .signal_range_max_ns = 3000000, + }; - flags = spin_lock_irqsave(&g_rmtdev_common.rmt_spinlock); + DEBUGASSERT((buflen % 4) == 0); - if (g_rmtdev_common.rmt_module_enabled == false) + if ((buflen / 4) > (CONFIG_RMT_DEFAULT_RX_BUFFER_SIZE / 4)) { - periph_module_reset(PERIPH_RMT_MODULE); - periph_module_enable(PERIPH_RMT_MODULE); - g_rmtdev_common.rmt_module_enabled = true; + rmtwarn("WARN: RMT RX buffer (%d bytes) is smaller than requested " + "read bytes (%d bytes). A partial read will take place!\n", + CONFIG_RMT_DEFAULT_RX_BUFFER_SIZE, + buflen); } - spin_unlock_irqrestore(&g_rmtdev_common.rmt_spinlock, flags); -} - -/**************************************************************************** - * Name: rmt_set_rx_thr_intr_en - * - * Description: - * This function enables or disables the RMT RX threshold interrupt. When - * the number of received items reaches the threshold, an interrupt is - * triggered if this feature is enabled. - * - * Input Parameters: - * channel - The RMT channel. - * en - Enable (true) or disable (false) the RX threshold int. - * evt_thresh - The number of received items that triggers the interrupt. - * - * Returned Value: - * Returns 0 on success; a negated errno value is returned on any failure. - * - ****************************************************************************/ - -#ifdef SOC_RMT_SUPPORT_RX_PINGPONG -static int rmt_set_rx_thr_intr_en(rmt_channel_t channel, bool en, - uint16_t evt_thresh) -{ - irqstate_t flags; - uint32_t mask; - - DEBUGASSERT(RMT_IS_RX_CHANNEL(channel) && channel < RMT_CHANNEL_MAX); - - if (en) +#ifndef SOC_RMT_SUPPORT_RX_PINGPONG + if ((buflen / 4) > RMT_MEM_ITEM_NUM) { - uint32_t item_block_len = - rmt_ll_rx_get_mem_blocks(g_rmtdev_common.hal.regs, - RMT_DECODE_RX_CHANNEL(channel)) * - RMT_MEM_ITEM_NUM; - - if (evt_thresh >= item_block_len) - { - rmterr("Invalid threshold value %d\n", evt_thresh); - return -EINVAL; - } - - flags = spin_lock_irqsave(&g_rmtdev_common.rmt_spinlock); - rmt_ll_rx_set_limit(g_rmtdev_common.hal.regs, - RMT_DECODE_RX_CHANNEL(channel), evt_thresh); - mask = RMT_LL_EVENT_RX_THRES(RMT_DECODE_RX_CHANNEL(channel)); - rmt_ll_enable_interrupt(g_rmtdev_common.hal.regs, mask, true); - spin_unlock_irqrestore(&g_rmtdev_common.rmt_spinlock, flags); + rmtwarn("WARN: RMT RX channel is able to receive up to " + "%d RMT items (%d bytes)!", + RMT_MEM_ITEM_NUM, RMT_MEM_ITEM_NUM * 4); } - else +#endif + + esp_ret = rmt_receive(priv->handle, buffer, + buflen, &receive_config); + if (esp_ret != ESP_OK) { - flags = spin_lock_irqsave(&g_rmtdev_common.rmt_spinlock); - mask = RMT_LL_EVENT_RX_THRES(RMT_DECODE_RX_CHANNEL(channel)); - rmt_ll_enable_interrupt(g_rmtdev_common.hal.regs, mask, false); - spin_unlock_irqrestore(&g_rmtdev_common.rmt_spinlock, flags); + rmterr("Failed to Receive RMT data"); + return -ERROR; } - return OK; + return (ssize_t)0; } -#endif /**************************************************************************** - * Name: rmt_rx_start + * Name: esp_rmt_write * * Description: - * This function starts the RMT module in receiving mode for a specific - * channel. + * This function writes data to the RMT memory for a specific channel. It + * asserts that the length of the data is a multiple of 4, then calls the + * rmt_write_items function to write the items to the RMT memory. * * Input Parameters: - * channel - The RMT peripheral channel number. - * rx_idx_rst - If true, the RX index for the channel is reset, which means - * the receiving process will start from the beginning of the - * RMT memory block. + * dev - Pointer to the RMT device structure. + * buffer - Pointer to the data to be written to the RMT memory. + * buflen - The length of the data to be written. * * Returned Value: - * Returns OK on successful start of the RMT module in receiving mode; a - * negated errno value is returned on any failure. + * Returns the number of items written to the RMT memory. * ****************************************************************************/ -static int rmt_rx_start(rmt_channel_t channel, bool rx_idx_rst) +static ssize_t esp_rmt_write(struct rmt_dev_s *dev, const char *buffer, + size_t buflen) { - irqstate_t flags; - rmt_channel_t ch = RMT_DECODE_RX_CHANNEL(channel); -#ifdef SOC_RMT_SUPPORT_RX_PINGPONG - const uint32_t item_block_len = - rmt_ll_rx_get_mem_blocks(g_rmtdev_common.hal.regs, ch) * - RMT_MEM_ITEM_NUM; -#endif - - DEBUGASSERT(RMT_IS_RX_CHANNEL(channel)); - - flags = spin_lock_irqsave(&g_rmtdev_common.rmt_spinlock); - - rmt_ll_rx_enable(g_rmtdev_common.hal.regs, ch, false); - if (rx_idx_rst) + struct rmt_dev_lowerhalf_s *priv = (struct rmt_dev_lowerhalf_s *)dev; + rmt_transmit_config_t tx_config = { - rmt_ll_rx_reset_pointer(g_rmtdev_common.hal.regs, ch); - } - - rmt_ll_clear_interrupt_status(g_rmtdev_common.hal.regs, - RMT_LL_EVENT_RX_DONE(ch)); - rmt_ll_enable_interrupt(g_rmtdev_common.hal.regs, - RMT_LL_EVENT_RX_DONE(ch), true); - -#ifdef SOC_RMT_SUPPORT_RX_PINGPONG - p_rmt_obj[channel]->rx_item_start_idx = 0; - p_rmt_obj[channel]->rx_item_len = 0; - rmt_set_rx_thr_intr_en(channel, true, item_block_len / 2); -#endif + .loop_count = 0, + }; - rmt_ll_rx_enable(g_rmtdev_common.hal.regs, ch, true); + DEBUGASSERT((buflen % 4) == 0); - spin_unlock_irqrestore(&g_rmtdev_common.rmt_spinlock, flags); + rmt_transmit(priv->handle, priv->encoder, buffer, buflen, &tx_config); + rmt_tx_wait_all_done(priv->handle, -1); - return OK; + return (ssize_t)buflen; } -/**************************************************************************** - * Name: rmt_tx_start - * - * Description: - * This function starts sending RMT items from the specific channel. - * - * Input Parameters: - * channel - The RMT peripheral channel number. - * tx_idx_rst - Set it true to reset memory index for TX. - * - * Returned Value: - * Returns OK on successful start of transmission. - * - ****************************************************************************/ - -static int rmt_tx_start(rmt_channel_t channel, bool tx_idx_rst) +static size_t encoder_callback(const void *data, size_t data_size, + size_t symbols_written, size_t symbols_free, + rmt_symbol_word_t *symbols, bool *done, + void *arg) { - irqstate_t flags; + size_t data_pos = symbols_written; + rmt_symbol_word_t data_bytes = + (rmt_symbol_word_t)((uint32_t *)data)[data_pos]; + + /* Encode a single symbol */ - DEBUGASSERT(RMT_IS_TX_CHANNEL(channel)); + symbols[0] = data_bytes; - flags = spin_lock_irqsave(&g_rmtdev_common.rmt_spinlock); - if (tx_idx_rst) + if (((symbols_written + 1) * 4) == data_size) { - rmt_ll_tx_reset_pointer(g_rmtdev_common.hal.regs, channel); + *done = true; } - rmt_ll_clear_interrupt_status(g_rmtdev_common.hal.regs, - RMT_LL_EVENT_TX_DONE(channel)); + return 1; +} - /* Enable tx end interrupt in non-loop mode */ +static bool rmt_rx_done_callback(rmt_channel_handle_t channel, + const rmt_rx_done_event_data_t *edata, + void *user_data) +{ + struct rmt_dev_lowerhalf_s *priv = (struct rmt_dev_lowerhalf_s *)user_data; - if (!rmt_ll_tx_is_loop_enabled(g_rmtdev_common.hal.regs, channel)) - { - rmt_ll_enable_interrupt(g_rmtdev_common.hal.regs, - RMT_LL_EVENT_TX_DONE(channel), true); - } - else + int bytes = circbuf_write(priv->circbuf, + edata->received_symbols, + edata->num_symbols * 4); + + nxsem_post(priv->recvsem); + if (bytes < (edata->num_symbols * 4)) { -#if SOC_RMT_SUPPORT_TX_LOOP_COUNT - rmt_ll_tx_reset_loop_count(g_rmtdev_common.hal.regs, channel); - rmt_ll_tx_enable_loop_count(g_rmtdev_common.hal.regs, channel, true); - rmt_ll_clear_interrupt_status(g_rmtdev_common.hal.regs, - RMT_LL_EVENT_TX_LOOP_END(channel)); - rmt_ll_enable_interrupt(g_rmtdev_common.hal.regs, - RMT_LL_EVENT_TX_LOOP_END(channel), true); -#endif + rmterr("RMT RX BUFFER FULL"); } - rmt_ll_tx_start(g_rmtdev_common.hal.regs, channel); - spin_unlock_irqrestore(&g_rmtdev_common.rmt_spinlock, flags); - - return OK; + return 0; } /**************************************************************************** - * Name: rmt_set_tx_loop_mode - * - * Description: - * This function enables or disables the loop mode for RMT transmission on - * the specified channel. The loop mode, when enabled, allows the RMT - * transmitter to continuously send items. - * - * Input Parameters: - * channel - The RMT peripheral channel number. - * loop_en - A boolean indicating whether to enable (true) or disable - * (false) the loop mode. - * - * Returned Value: - * Returns OK on successful setting of the loop mode. - * + * Public Functions ****************************************************************************/ -static int rmt_set_tx_loop_mode(rmt_channel_t channel, bool loop_en) -{ - irqstate_t flags; - - DEBUGASSERT(RMT_IS_TX_CHANNEL(channel)); - - flags = spin_lock_irqsave(&g_rmtdev_common.rmt_spinlock); - rmt_ll_tx_enable_loop(g_rmtdev_common.hal.regs, channel, loop_en); - spin_unlock_irqrestore(&g_rmtdev_common.rmt_spinlock, flags); - - return OK; -} - /**************************************************************************** - * Name: rmt_set_tx_thr_intr_en + * Name: esp_rmt_tx_init * * Description: - * This function enables or disables the RMT TX threshold interrupt for the - * specified channel. The threshold is set to trigger an interrupt when the - * number of transmitted items reaches the specified value. + * Initialize the selected RMT device in TX mode * * Input Parameters: - * channel - The RMT peripheral channel number. - * en - A boolean indicating whether to enable (true) or disable - * (false) the TX threshold interrupt. - * evt_thresh - The number of transmitted items at which to trigger the - * interrupt. + * tx_pin - The pin used for the TX channel * * Returned Value: - * Returns OK on successful setting of the interrupt. + * Valid RMT device structure reference on success; NULL, otherwise. * ****************************************************************************/ -static int rmt_set_tx_thr_intr_en(rmt_channel_t channel, bool en, - uint16_t evt_thresh) +struct rmt_dev_s *esp_rmt_tx_init(int tx_pin) { - irqstate_t flags; - - DEBUGASSERT(RMT_IS_TX_CHANNEL(channel)); + int channel_id; + esp_err_t ret; + struct rmt_dev_lowerhalf_s *priv; + rmt_channel_handle_t tx_chan = NULL; + rmt_encoder_handle_t simple_encoder = NULL; + rmt_tx_channel_config_t tx_chan_config = + { + .clk_src = RMT_CLK_SRC_DEFAULT, /* select source clock */ + .gpio_num = tx_pin, + .mem_block_symbols = 64, /* increase the block size can make the LED less flickering */ + .resolution_hz = 10000000, + .trans_queue_depth = 4, /* set the number of transactions that can be pending in the background */ + }; - if (en) + const rmt_simple_encoder_config_t simple_encoder_cfg = { - uint32_t item_block_len = - rmt_ll_tx_get_mem_blocks(g_rmtdev_common.hal.regs, channel) * \ - RMT_MEM_ITEM_NUM; - - DEBUGASSERT(evt_thresh <= item_block_len); + .callback = encoder_callback + }; - flags = spin_lock_irqsave(&g_rmtdev_common.rmt_spinlock); - rmt_ll_tx_set_limit(g_rmtdev_common.hal.regs, channel, evt_thresh); - rmt_ll_enable_interrupt(g_rmtdev_common.hal.regs, - RMT_LL_EVENT_TX_THRES(channel), true); - spin_unlock_irqrestore(&g_rmtdev_common.rmt_spinlock, flags); - } - else + ret = rmt_new_tx_channel(&tx_chan_config, &tx_chan); + if (ret != ESP_OK) { - flags = spin_lock_irqsave(&g_rmtdev_common.rmt_spinlock); - rmt_ll_enable_interrupt(g_rmtdev_common.hal.regs, - RMT_LL_EVENT_TX_THRES(channel), false); - spin_unlock_irqrestore(&g_rmtdev_common.rmt_spinlock, flags); + rmterr("Failed to Initialize RMT TX channel"); + return NULL; } - return OK; -} - -/**************************************************************************** - * Name: rmt_set_gpio - * - * Description: - * This function configures the GPIO for the specified RMT (Remote Control) - * channel and mode. It sets the GPIO to the appropriate input or output - * function based on the mode, and configures the signal inversion if - * necessary. - * - * Input Parameters: - * channel - The RMT peripheral channel number. - * mode - The mode of operation for the RMT channel (RMT_MODE_TX - * for transmission, RMT_MODE_RX for reception). - * gpio_num - The GPIO number to configure for the RMT channel. - * invert_signal - A boolean indicating whether to invert the signal. - * - * Returned Value: - * Returns OK on successful configuration of the GPIO. - * - ****************************************************************************/ - -static int rmt_set_gpio(rmt_channel_t channel, rmt_mode_t mode, - gpio_num_t gpio_num, bool invert_signal) -{ - int ret; + ret = rmt_new_simple_encoder(&simple_encoder_cfg, &simple_encoder); + if (ret != ESP_OK) + { + rmterr("Failed to Initialize RMT Simple Encoder"); + return NULL; + } - DEBUGASSERT(channel < RMT_CHANNEL_MAX); - DEBUGASSERT(mode < RMT_MODE_MAX); - DEBUGASSERT((GPIO_IS_VALID_GPIO(gpio_num) && (mode == RMT_MODE_RX)) || - (GPIO_IS_VALID_OUTPUT_GPIO(gpio_num) && - (mode == RMT_MODE_TX))); + ret = rmt_enable(tx_chan); + if (ret != ESP_OK) + { + rmterr("Failed to Enable RMT TX channel"); + return NULL; + } - if (mode == RMT_MODE_TX) + priv = kmm_zalloc(sizeof(struct rmt_dev_lowerhalf_s)); + if (priv) { - DEBUGASSERT(RMT_IS_TX_CHANNEL(channel)); - esp_configgpio(gpio_num, GPIO_OUT_FUNC); - esp_gpio_matrix_out( - gpio_num, - rmt_periph_signals.groups[0].channels[channel].tx_sig, - invert_signal, 0); + priv->ops = &g_rmtops; + priv->handle = tx_chan; + priv->encoder = simple_encoder; } else { - DEBUGASSERT(RMT_IS_RX_CHANNEL(channel)); - esp_configgpio(gpio_num, GPIO_IN_FUNC); - esp_gpio_matrix_in( - gpio_num, - rmt_periph_signals.groups[0].channels[channel].rx_sig, - invert_signal); + rmterr("ERROR: memory allocation failed\n"); + return NULL; } - return OK; -} - -/**************************************************************************** - * Name: rmt_is_channel_number_valid - * - * Description: - * This function checks if the provided RMT channel number is valid for the - * specified mode (TX or RX). For RX mode, it checks if the channel number - * is within the range of valid RX channels and less than the maximum - * channel number. For TX mode, it checks if the channel number is a valid - * TX channel. - * - * Input Parameters: - * channel - The RMT peripheral channel number. - * mode - The mode of operation for the RMT channel (RMT_MODE_TX for - * transmission, RMT_MODE_RX for reception). - * - * Returned Value: - * Returns true if the channel number is valid, false otherwise. - * - ****************************************************************************/ - -static bool rmt_is_channel_number_valid(rmt_channel_t channel, uint8_t mode) -{ - if (mode == RMT_MODE_RX) + ret = rmt_get_channel_id(tx_chan, &channel_id); + if (ret != ESP_OK) { - return RMT_IS_RX_CHANNEL(channel) && (channel < RMT_CHANNEL_MAX); + rmterr("Failed to Get RMT RX channel ID"); + return NULL; } - return (channel >= 0) && RMT_IS_TX_CHANNEL(channel); + priv->minor = channel_id + RMT_TX_CHANNEL_OFFSET_IN_GROUP; + + return (struct rmt_dev_s *)priv; } /**************************************************************************** - * Name: rmt_internal_config + * Name: esp_rmt_rx_init * * Description: - * This function configures the RMT peripheral with provided parameters. - * It sets the mode (TX or RX), channel, GPIO number, memory block number, - * clock divider, carrier frequency, and carrier enable flag. It also - * configures the clock source, memory access, idle level, carrier - * modulation, and other settings based on the mode and parameters. + * Initialize the selected RMT device in RX mode * * Input Parameters: - * dev - Pointer to the RMT peripheral device structure. - * rmt_param - Pointer to the structure containing the RMT channel - * configuration parameters. + * rx_pin - The pin used for the RX channel * * Returned Value: - * Returns OK on successful configuration of the RMT peripheral. + * Valid RMT device structure reference on success; NULL, otherwise. * ****************************************************************************/ -static int rmt_internal_config(rmt_dev_t *dev, - const struct rmt_channel_config_s *rmt_param) +struct rmt_dev_s *esp_rmt_rx_init(int rx_pin) { - uint8_t mode = rmt_param->rmt_mode; - uint8_t channel = rmt_param->channel; - uint8_t gpio_num = rmt_param->gpio_num; - uint8_t mem_cnt = rmt_param->mem_block_num; - uint8_t clk_div = rmt_param->clk_div; - uint32_t carrier_freq_hz = rmt_param->tx_config.carrier_freq_hz; - bool carrier_en = rmt_param->tx_config.carrier_en; - uint32_t rmt_source_clk_hz; - irqstate_t flags; - - if (!rmt_is_channel_number_valid(channel, mode)) + int channel_id; + esp_err_t esp_ret; + int ret; + struct rmt_dev_lowerhalf_s *priv; + rmt_channel_handle_t rx_chan = NULL; + rmt_rx_channel_config_t rx_channel_cfg = { - rmterr("Invalid channel number %u for %s mode!", - channel, mode == RMT_MODE_TX ? "transmitter" : "receiver"); - return -EINVAL; - } + .clk_src = RMT_CLK_SRC_DEFAULT, + .resolution_hz = 10000000, + .mem_block_symbols = SOC_RMT_MEM_WORDS_PER_CHANNEL, /* amount of RMT symbols that the channel can store at a time */ + .gpio_num = rx_pin, + }; - DEBUGASSERT(mem_cnt + channel <= SOC_RMT_CHANNELS_PER_GROUP && - mem_cnt > 0); - DEBUGASSERT(clk_div > 0); + rmt_rx_event_callbacks_t cbs = + { + .on_recv_done = rmt_rx_done_callback, + }; - if (mode == RMT_MODE_TX && carrier_en && carrier_freq_hz <= 0) + esp_ret = rmt_new_rx_channel(&rx_channel_cfg, &rx_chan); + if (esp_ret != ESP_OK) { - return -EINVAL; + rmterr("Failed to Initialize RMT RX channel"); + return NULL; } - flags = spin_lock_irqsave(&g_rmtdev_common.rmt_spinlock); - - rmt_ll_enable_mem_access_nonfifo(dev, true); - - if (rmt_param->flags & RMT_CHANNEL_FLAGS_AWARE_DFS) + priv = kmm_zalloc(sizeof(struct rmt_dev_lowerhalf_s)); + if (priv) { -#if SOC_RMT_SUPPORT_XTAL - - /* clock src: XTAL_CLK */ - - esp_clk_tree_src_get_freq_hz((soc_module_clk_t)RMT_BASECLK_XTAL, - ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, - &rmt_source_clk_hz); - rmt_ll_set_group_clock_src(dev, channel, - (rmt_clock_source_t)RMT_BASECLK_XTAL, - 1, 0, 0); -#elif SOC_RMT_SUPPORT_REF_TICK - - /* clock src: REF_CLK */ - - esp_clk_tree_src_get_freq_hz((soc_module_clk_t)RMT_BASECLK_REF, - ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, - &rmt_source_clk_hz); - rmt_ll_set_group_clock_src(dev, channel, - (rmt_clock_source_t)RMT_BASECLK_REF, - 1, 0, 0); -#else -#error "No clock source is aware of DFS" -#endif + priv->ops = &g_rmtops; + priv->handle = rx_chan; } else { - /* fallback to use default clock source */ - - esp_clk_tree_src_get_freq_hz((soc_module_clk_t)RMT_BASECLK_DEFAULT, - ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, - &rmt_source_clk_hz); - rmt_ll_set_group_clock_src(dev, channel, - (rmt_clock_source_t)RMT_BASECLK_DEFAULT, - 1, 0, 0); + rmterr("ERROR: memory allocation failed\n"); + return NULL; } - spin_unlock_irqrestore(&g_rmtdev_common.rmt_spinlock, flags); - -#if SOC_RMT_CHANNEL_CLK_INDEPENDENT - g_rmt_source_clock_hz[channel] = rmt_source_clk_hz; -#else - if (g_rmt_source_clock_hz && rmt_source_clk_hz != g_rmt_source_clock_hz) + esp_ret = rmt_get_channel_id(rx_chan, &channel_id); + if (esp_ret != ESP_OK) { - rmterr("RMT clock source has been configured to %"PRIu32" by other " - "channel, now reconfigure it to %"PRIu32"", - g_rmt_source_clock_hz, rmt_source_clk_hz); + rmterr("Failed to Get RMT RX channel ID"); + return NULL; } - g_rmt_source_clock_hz = rmt_source_clk_hz; -#endif - rmtinfo("rmt_source_clk_hz: %"PRIu32, rmt_source_clk_hz); + priv->minor = channel_id + RMT_RX_CHANNEL_OFFSET_IN_GROUP; - if (mode == RMT_MODE_TX) + priv->recvsem = kmm_zalloc(sizeof(sem_t)); + if (priv->recvsem == NULL) { - uint16_t carrier_duty_percent = - rmt_param->tx_config.carrier_duty_percent; - uint8_t carrier_level = rmt_param->tx_config.carrier_level; - uint8_t idle_level = rmt_param->tx_config.idle_level; - - flags = spin_lock_irqsave(&g_rmtdev_common.rmt_spinlock); - rmt_ll_tx_set_channel_clock_div(dev, channel, clk_div); - rmt_ll_tx_set_mem_blocks(dev, channel, mem_cnt); - rmt_ll_tx_reset_pointer(dev, channel); - rmt_ll_tx_enable_loop(dev, channel, rmt_param->tx_config.loop_en); -#if SOC_RMT_SUPPORT_TX_LOOP_COUNT - if (rmt_param->tx_config.loop_en) - { - rmt_ll_tx_set_loop_count(dev, channel, - rmt_param->tx_config.loop_count); - } -#endif + rmterr("ERROR: memory allocation failed\n"); + return NULL; + } - /* always enable tx ping-pong */ + nxsem_init(priv->recvsem, 0, 0); - rmt_ll_tx_enable_wrap(dev, channel, true); - - /* Set idle level */ - - rmt_ll_tx_fix_idle_level(dev, channel, idle_level, - rmt_param->tx_config.idle_output_en); - - /* Set carrier */ - - rmt_ll_tx_enable_carrier_modulation(dev, channel, carrier_en); - if (carrier_en) - { - uint32_t duty_div; - uint32_t duty_h; - uint32_t duty_l; - duty_div = rmt_source_clk_hz / carrier_freq_hz; - duty_h = duty_div * carrier_duty_percent / 100; - duty_l = duty_div - duty_h; - rmt_ll_tx_set_carrier_level(dev, channel, carrier_level); - rmt_ll_tx_set_carrier_high_low_ticks(dev, channel, duty_h, duty_l); - } - else - { - rmt_ll_tx_set_carrier_level(dev, channel, 0); - } - - spin_unlock_irqrestore(&g_rmtdev_common.rmt_spinlock, flags); - - rmtinfo("Rmt Tx Channel %u|Gpio %u|Sclk_Hz %"PRIu32"|Div %u|Carrier_Hz" - " %"PRIu32"|Duty %u", channel, gpio_num, rmt_source_clk_hz, - clk_div, carrier_freq_hz, carrier_duty_percent); - } - else if (RMT_MODE_RX == mode) - { - uint8_t filter_cnt = rmt_param->rx_config.filter_ticks_thresh; - uint16_t threshold = rmt_param->rx_config.idle_threshold; - - flags = spin_lock_irqsave(&g_rmtdev_common.rmt_spinlock); - rmt_ll_rx_set_channel_clock_div(dev, RMT_DECODE_RX_CHANNEL(channel), - clk_div); - rmt_ll_rx_set_mem_blocks(dev, RMT_DECODE_RX_CHANNEL(channel), mem_cnt); - rmt_ll_rx_reset_pointer(dev, RMT_DECODE_RX_CHANNEL(channel)); - rmt_ll_rx_set_mem_owner(dev, RMT_DECODE_RX_CHANNEL(channel), - RMT_LL_MEM_OWNER_HW); - - /* Set idle threshold */ - - rmt_ll_rx_set_idle_thres(dev, RMT_DECODE_RX_CHANNEL(channel), - threshold); - - /* Set RX filter */ - - rmt_ll_rx_set_filter_thres(dev, RMT_DECODE_RX_CHANNEL(channel), - filter_cnt); - rmt_ll_rx_enable_filter(dev, RMT_DECODE_RX_CHANNEL(channel), - rmt_param->rx_config.filter_en); - -#ifdef SOC_RMT_SUPPORT_RX_PINGPONG - - /* always enable rx ping-pong */ - - rmt_ll_rx_enable_wrap(dev, RMT_DECODE_RX_CHANNEL(channel), true); -#endif - -#if SOC_RMT_SUPPORT_RX_DEMODULATION - rmt_ll_rx_enable_carrier_demodulation(dev, - RMT_DECODE_RX_CHANNEL(channel), - rmt_param->rx_config.rm_carrier); - if (rmt_param->rx_config.rm_carrier) - { - uint32_t duty_total; - uint32_t duty_high; - uint32_t ch_clk_div = - rmt_ll_rx_get_channel_clock_div(dev, - RMT_DECODE_RX_CHANNEL(channel)); - duty_total = rmt_source_clk_hz / \ - ch_clk_div / \ - rmt_param->rx_config.carrier_freq_hz; - duty_high = duty_total * - rmt_param->rx_config.carrier_duty_percent / 100; - - /* there could be residual in timing the carrier pulse, so double - * enlarge the theoretical value. - */ - - rmt_ll_rx_set_carrier_high_low_ticks( - dev, RMT_DECODE_RX_CHANNEL(channel), duty_high * 2, - (duty_total - duty_high) * 2); - rmt_ll_rx_set_carrier_level(dev, RMT_DECODE_RX_CHANNEL(channel), - rmt_param->rx_config.carrier_level); - } -#endif - - spin_unlock_irqrestore(&g_rmtdev_common.rmt_spinlock, flags); - - rmtinfo("Rmt Rx Channel %u|Gpio %u|Sclk_Hz %"PRIu32"|Div %u|Threshold " - "%u|Filter %u", channel, gpio_num, rmt_source_clk_hz, clk_div, - threshold, filter_cnt); - } - - return OK; -} - -/**************************************************************************** - * Name: rmt_config - * - * Description: - * This function configures the RMT channel with the provided parameters. - * It enables the RMT module, sets the GPIO for the RMT channel, and - * configures the RMT peripheral using the internal configuration function. - * - * Input Parameters: - * rmt_param - Pointer to the structure containing the RMT channel - * configuration parameters. - * - * Returned Value: - * Returns OK on successful configuration of the RMT channel; a negated - * errno value is returned on any failure. - * - ****************************************************************************/ - -static int rmt_config(const struct rmt_channel_config_s *rmt_param) -{ - int ret = ERROR; - - rmt_module_enable(); - - rmt_set_gpio(rmt_param->channel, rmt_param->rmt_mode, rmt_param->gpio_num, - rmt_param->flags & RMT_CHANNEL_FLAGS_INVERT_SIG); - - ret = rmt_internal_config(&RMT, rmt_param); - - return ret; -} - -/**************************************************************************** - * Name: rmt_fill_memory - * - * Description: - * This function fills the RMT memory with the provided items. It copies - * the items from the source to the RMT memory for the specified channel, - * starting at the specified memory offset. - * - * Input Parameters: - * channel - The RMT peripheral channel number. - * item - Pointer to the items to be copied to the RMT memory. - * item_num - The number of items to be copied. - * mem_offset - The memory offset at which to start copying. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -static void IRAM_ATTR rmt_fill_memory(rmt_channel_t channel, - const rmt_item32_t *item, - uint16_t item_num, - uint16_t mem_offset) -{ - uint32_t *from = (uint32_t *)item; - volatile uint32_t *to = - (volatile uint32_t *)&RMTMEM.chan[channel].data32[0].val; - - to += mem_offset; - - while (item_num--) - { - *to++ = *from++; - } -} - -/**************************************************************************** - * Name: rmt_isr_register - * - * Description: - * This function registers an interrupt service routine (ISR) for the RMT - * peripheral. It allocates a CPU interrupt, attaches the ISR to the - * interrupt, and returns the status of the operation. - * - * Input Parameters: - * fn - Pointer to the ISR function. - * arg - Pointer to the argument to be passed to the ISR. - * intr_alloc_flags - Flags for the interrupt allocation. - * - * Returned Value: - * Returns OK on successful registration of the ISR; a negated errno value - * is returned on any failure. - * - ****************************************************************************/ - -static int rmt_isr_register(int (*fn)(int, void *, void *), void *arg, - int intr_alloc_flags) -{ - int cpuint; - int ret; - int cpu = this_cpu(); - - DEBUGASSERT(fn); - DEBUGASSERT(g_rmtdev_common.rmt_driver_channels == 0); - - cpuint = esp_setup_irq( -#ifndef CONFIG_ARCH_CHIP_ESP32S2 - cpu, -#endif - rmt_periph_signals.groups[0].irq, 1, ESP_CPUINT_LEVEL); - if (cpuint < 0) - { - rmterr("Failed to allocate a CPU interrupt.\n"); - return -ENOMEM; - } - - ret = irq_attach(rmt_periph_signals.groups[0].irq + XTENSA_IRQ_FIRSTPERIPH, - fn, &g_rmtdev_common.hal); - if (ret < 0) - { - rmterr("Couldn't attach IRQ to handler.\n"); - esp_teardown_irq( -#ifndef CONFIG_ARCH_CHIP_ESP32S2 - cpu, -#endif - rmt_periph_signals.groups[0].irq, cpuint); - return ret; - } - - return ret; -} - -/**************************************************************************** - * Name: rmt_driver_isr_default - * - * Description: - * This function is the default interrupt service routine (ISR) for the RMT - * peripheral. It handles TX end, TX threshold, RX end, RX threshold, loop - * count, RX error, and TX error interrupts. For each interrupt type, it - * checks the status, clears the interrupt, and performs the appropriate - * actions based on the RMT object associated with the channel. - * - * Input Parameters: - * irq - The interrupt request number. - * context - Pointer to the interrupt context. - * arg - Pointer to the argument to be passed to the ISR. - * - * Returned Value: - * Returns OK after handling all active interrupts. - * - ****************************************************************************/ - -static int IRAM_ATTR rmt_driver_isr_default(int irq, void *context, - void *arg) -{ - uint32_t status = 0; - rmt_item32_t *addr = NULL; - uint8_t channel = 0; - rmt_hal_context_t *hal = (rmt_hal_context_t *)arg; - - /* Tx end interrupt */ - - status = rmt_ll_get_tx_end_interrupt_status(hal->regs); - while (status) - { - channel = __builtin_ffs(status) - 1; - status &= ~(1 << channel); - rmt_obj_t *p_rmt = p_rmt_obj[channel]; - if (p_rmt) - { - nxsem_post(&p_rmt->tx_sem); - rmt_ll_tx_reset_pointer(g_rmtdev_common.hal.regs, channel); - p_rmt->tx_data = NULL; - p_rmt->tx_len_rem = 0; - p_rmt->tx_offset = 0; - p_rmt->tx_sub_len = 0; - p_rmt->sample_cur = NULL; - } - - rmt_ll_clear_interrupt_status(hal->regs, - RMT_LL_EVENT_TX_DONE(channel)); - } - - /* Tx thres interrupt */ - - status = rmt_ll_get_tx_thres_interrupt_status(hal->regs); - while (status) - { - channel = __builtin_ffs(status) - 1; - status &= ~(1 << channel); - rmt_obj_t *p_rmt = p_rmt_obj[channel]; - if (p_rmt) - { - const rmt_item32_t *pdata = p_rmt->tx_data; - size_t len_rem = p_rmt->tx_len_rem; - rmt_idle_level_t idle_level = - rmt_ll_tx_get_idle_level(hal->regs, channel); - rmt_item32_t stop_data = (rmt_item32_t) - { - .level0 = idle_level, - .duration0 = 0, - }; - - if (len_rem >= p_rmt->tx_sub_len) - { - rmt_fill_memory(channel, pdata, p_rmt->tx_sub_len, - p_rmt->tx_offset); - p_rmt->tx_data += p_rmt->tx_sub_len; - p_rmt->tx_len_rem -= p_rmt->tx_sub_len; - } - else if (len_rem == 0) - { - rmt_fill_memory(channel, &stop_data, 1, p_rmt->tx_offset); - } - else - { - rmt_fill_memory(channel, pdata, len_rem, p_rmt->tx_offset); - rmt_fill_memory(channel, &stop_data, 1, - p_rmt->tx_offset + len_rem); - p_rmt->tx_data += len_rem; - p_rmt->tx_len_rem -= len_rem; - } - - if (p_rmt->tx_offset == 0) - { - p_rmt->tx_offset = p_rmt->tx_sub_len; - } - else - { - p_rmt->tx_offset = 0; - } - } - - rmt_ll_clear_interrupt_status(hal->regs, - RMT_LL_EVENT_TX_THRES(channel)); - } - - /* Rx end interrupt */ - - status = rmt_ll_get_rx_end_interrupt_status(hal->regs); - while (status) - { - channel = __builtin_ffs(status) - 1; - status &= ~(1 << channel); - rmt_obj_t *p_rmt = p_rmt_obj[RMT_ENCODE_RX_CHANNEL(channel)]; - if (p_rmt) - { - int item_len; - rmt_ll_rx_enable(g_rmtdev_common.hal.regs, channel, false); - item_len = - rmt_ll_rx_get_memory_writer_offset(g_rmtdev_common.hal.regs, - channel); - rmt_ll_rx_set_mem_owner(g_rmtdev_common.hal.regs, channel, - RMT_LL_MEM_OWNER_SW); - if (circbuf_is_init(&p_rmt->rx_buf)) - { - int bytes; - - addr = (rmt_item32_t *) - RMTMEM.chan[RMT_ENCODE_RX_CHANNEL(channel)].data32; -#ifdef SOC_RMT_SUPPORT_RX_PINGPONG - if (item_len > p_rmt->rx_item_start_idx) - { - item_len = item_len - p_rmt->rx_item_start_idx; - } - - /* Check for RX buffer max length */ - - if ((p_rmt->rx_item_len + item_len) > \ - (p_rmt->rx_item_buf_size / 4)) - { - int remaining_len = (p_rmt->rx_item_buf_size / 4) - \ - p_rmt->rx_item_len; - rmterr("ERROR: RX buffer too small: %d items dropped\n", - item_len - remaining_len); - item_len = remaining_len; - } - - memcpy((void *)(p_rmt->rx_item_buf + p_rmt->rx_item_len), - (void *)(addr + p_rmt->rx_item_start_idx), - item_len * 4); - p_rmt->rx_item_len += item_len; - bytes = circbuf_write(&p_rmt->rx_buf, - (void *)(p_rmt->rx_item_buf), - p_rmt->rx_item_len * 4); -#else - bytes = circbuf_write(&p_rmt->rx_buf, (void *)addr, - item_len * 4); -#endif - nxsem_post(&p_rmt->rx_sem); - if (bytes < (item_len * 4)) - { - rmterr("RMT RX BUFFER FULL"); - } - } - else - { - rmterr("RMT RX BUFFER ERROR"); - } - -#ifdef SOC_RMT_SUPPORT_RX_PINGPONG - p_rmt->rx_item_start_idx = 0; - p_rmt->rx_item_len = 0; - memset((void *)p_rmt->rx_item_buf, 0, p_rmt->rx_item_buf_size); -#endif - rmt_ll_rx_reset_pointer(g_rmtdev_common.hal.regs, channel); - rmt_ll_rx_set_mem_owner(g_rmtdev_common.hal.regs, channel, - RMT_LL_MEM_OWNER_HW); - rmt_ll_rx_enable(g_rmtdev_common.hal.regs, channel, true); - } - - rmt_ll_clear_interrupt_status(hal->regs, - RMT_LL_EVENT_RX_DONE(channel)); - } - -#ifdef SOC_RMT_SUPPORT_RX_PINGPONG - - /* Rx thres interrupt */ - - status = rmt_ll_get_rx_thres_interrupt_status(hal->regs); - while (status) - { - int mem_item_size; - int rx_thres_lim; - int item_len; - - channel = __builtin_ffs(status) - 1; - status &= ~(1 << channel); - rmt_obj_t *p_rmt = p_rmt_obj[RMT_ENCODE_RX_CHANNEL(channel)]; - mem_item_size = rmt_ll_rx_get_mem_blocks(g_rmtdev_common.hal.regs, - channel) * RMT_MEM_ITEM_NUM; - rx_thres_lim = rmt_ll_rx_get_limit(g_rmtdev_common.hal.regs, channel); - item_len = (p_rmt->rx_item_start_idx == 0) ? rx_thres_lim : \ - (mem_item_size - rx_thres_lim); - if ((p_rmt->rx_item_len + item_len) > (p_rmt->rx_item_buf_size / 4)) - { - int remaining_len = (p_rmt->rx_item_buf_size / 4) - \ - p_rmt->rx_item_len; - rmterr("ERROR: RX buffer too small!\n"); - item_len = remaining_len; - } - - rmt_ll_rx_set_mem_owner(g_rmtdev_common.hal.regs, channel, - RMT_LL_MEM_OWNER_SW); - memcpy( - (void *)(p_rmt->rx_item_buf + p_rmt->rx_item_len), - (void *)(RMTMEM.chan[RMT_ENCODE_RX_CHANNEL(channel)].data32 \ - + p_rmt->rx_item_start_idx), item_len * 4); - rmt_ll_rx_set_mem_owner(g_rmtdev_common.hal.regs, channel, - RMT_LL_MEM_OWNER_HW); - p_rmt->rx_item_len += item_len; - p_rmt->rx_item_start_idx += item_len; - if (p_rmt->rx_item_start_idx >= mem_item_size) - { - p_rmt->rx_item_start_idx = 0; - } - - rmt_ll_clear_interrupt_status(hal->regs, - RMT_LL_EVENT_RX_THRES(channel)); - } -#endif - -#if SOC_RMT_SUPPORT_TX_LOOP_COUNT - - /* loop count interrupt */ - - status = rmt_ll_get_tx_loop_interrupt_status(hal->regs); - while (status) - { - channel = __builtin_ffs(status) - 1; - status &= ~(1 << channel); - rmt_obj_t *p_rmt = p_rmt_obj[channel]; - if (p_rmt) - { - if (p_rmt->loop_autostop) - { -#ifndef SOC_RMT_SUPPORT_TX_LOOP_AUTO_STOP - - /* hardware doesn't support automatically stop output so driver - * should stop output here (possibility already overshotted - * several us). - */ - - rmt_ll_tx_stop(g_rmtdev_common.hal.regs, channel); - rmt_ll_tx_reset_pointer(g_rmtdev_common.hal.regs, channel); -#endif - } - - nxsem_post(&p_rmt->tx_sem); - } - - rmt_ll_clear_interrupt_status(hal->regs, - RMT_LL_EVENT_TX_LOOP_END(channel)); - } -#endif - - /* RX Err interrupt */ - - status = rmt_ll_get_rx_err_interrupt_status(hal->regs); - while (status) - { - channel = __builtin_ffs(status) - 1; - status &= ~(1 << channel); - rmt_obj_t *p_rmt = p_rmt_obj[RMT_ENCODE_RX_CHANNEL(channel)]; - if (p_rmt) - { - /* Reset the receiver's write/read addresses to prevent endless - * err interrupts. - */ - - rmt_ll_rx_reset_pointer(g_rmtdev_common.hal.regs, channel); - rmtinfo("RMT RX channel %d error", channel); - rmtinfo("status: 0x%08" PRIx32 "", - rmt_ll_rx_get_status_word(g_rmtdev_common.hal.regs, - channel)); - } - - rmt_ll_clear_interrupt_status(hal->regs, - RMT_LL_EVENT_RX_ERROR(channel)); - } - - /* TX Err interrupt */ - - status = rmt_ll_get_tx_err_interrupt_status(hal->regs); - while (status) - { - channel = __builtin_ffs(status) - 1; - status &= ~(1 << channel); - rmt_obj_t *p_rmt = p_rmt_obj[channel]; - if (p_rmt) - { - /* Reset the transmitter's write/read addresses to prevent - * endless err interrupts. - */ - - rmt_ll_tx_reset_pointer(g_rmtdev_common.hal.regs, channel); - rmtinfo("RMT TX channel %d error", channel); - rmtinfo("status: 0x%08" PRIx32 "", - rmt_ll_tx_get_status_word(g_rmtdev_common.hal.regs, - channel)); - } - - rmt_ll_clear_interrupt_status(hal->regs, - RMT_LL_EVENT_TX_ERROR(channel)); - } - - return OK; -} - -/**************************************************************************** - * Name: rmt_driver_install - * - * Description: - * This function installs the RMT driver for a specific channel. It - * allocates memory for the RMT object, initializes the object properties, - * and sets up the RX buffer if specified. It also registers the default - * ISR if this is the first RMT channel using the driver, and resets the - * RMT channel. - * - * Input Parameters: - * channel - The RMT peripheral channel number. - * rx_buf_size - The size of the RX buffer. - * intr_alloc_flags - Flags for the interrupt allocation. - * - * Returned Value: - * Returns OK on successful installation of the RMT driver; a negated errno - * value is returned on any failure. - * - ****************************************************************************/ - -static int rmt_driver_install(rmt_channel_t channel, size_t rx_buf_size, - int intr_alloc_flags) -{ - DEBUGASSERT(channel < RMT_CHANNEL_MAX); - - int ret = OK; - - if (p_rmt_obj[channel]) - { - rmtwarn("RMT driver already installed"); - return ERROR; - } - -#if CONFIG_RINGBUF_PLACE_ISR_FUNCTIONS_INTO_FLASH - if (intr_alloc_flags & ESP_INTR_FLAG_IRAM) - { - rmterr("ringbuf ISR functions in flash, but used in IRAM interrupt"); - return -EINVAL; - } -#endif - -#ifndef CONFIG_SPIRAM_USE_MALLOC - p_rmt_obj[channel] = kmm_calloc(1, sizeof(rmt_obj_t)); -#else - if (!(intr_alloc_flags & ESP_INTR_FLAG_IRAM)) - { - p_rmt_obj[channel] = calloc(1, sizeof(rmt_obj_t)); - } - else - { - p_rmt_obj[channel] = kmm_calloc(1, sizeof(rmt_obj_t)); - } -#endif - - if (p_rmt_obj[channel] == NULL) - { - rmterr("RMT driver malloc error"); - return -ENOMEM; - } - - p_rmt_obj[channel]->tx_len_rem = 0; - p_rmt_obj[channel]->tx_data = NULL; - p_rmt_obj[channel]->channel = channel; - p_rmt_obj[channel]->tx_offset = 0; - p_rmt_obj[channel]->tx_sub_len = 0; - p_rmt_obj[channel]->wait_done = false; - p_rmt_obj[channel]->loop_autostop = false; - -#ifndef CONFIG_SPIRAM_USE_MALLOC - nxsem_init(&p_rmt_obj[channel]->tx_sem, 0, 0); - nxsem_init(&p_rmt_obj[channel]->rx_sem, 0, 0); -#endif - - nxsem_post(&p_rmt_obj[channel]->tx_sem); - - if (!circbuf_is_init(&p_rmt_obj[channel]->rx_buf) && rx_buf_size > 0) - { - circbuf_init(&p_rmt_obj[channel]->rx_buf, NULL, rx_buf_size); - } - -#ifdef SOC_RMT_SUPPORT_RX_PINGPONG - if (p_rmt_obj[channel]->rx_item_buf == NULL && rx_buf_size > 0) - { -# ifndef CONFIG_SPIRAM_USE_MALLOC - p_rmt_obj[channel]->rx_item_buf = kmm_calloc(1, rx_buf_size); -# else - if (!(p_rmt_obj[channel]->intr_alloc_flags & ESP_INTR_FLAG_IRAM)) - { - p_rmt_obj[channel]->rx_item_buf = calloc(1, rx_buf_size); - } - else - { - p_rmt_obj[channel]->rx_item_buf = kmm_calloc(1, rx_buf_size); - } - -# endif - if (p_rmt_obj[channel]->rx_item_buf == NULL) - { - rmterr("RMT malloc fail"); - nxsem_destroy(&p_rmt_obj[channel]->rx_sem); - return -ENOMEM; - } - - p_rmt_obj[channel]->rx_item_buf_size = rx_buf_size; - } -#endif - - nxrmutex_lock(&(g_rmtdev_common.rmt_driver_isr_lock)); - - if (g_rmtdev_common.rmt_driver_channels == 0) - { - /* first RMT channel using driver */ - - ret = rmt_isr_register(rmt_driver_isr_default, &g_rmtdev_common.hal, - intr_alloc_flags); - } - - if (ret == OK) - { - g_rmtdev_common.rmt_driver_channels |= BIT(channel); - } - - nxrmutex_unlock(&(g_rmtdev_common.rmt_driver_isr_lock)); - - rmt_module_enable(); - - if (RMT_IS_RX_CHANNEL(channel)) - { - rmt_hal_rx_channel_reset(&g_rmtdev_common.hal, - RMT_DECODE_RX_CHANNEL(channel)); - } - else - { - rmt_hal_tx_channel_reset(&g_rmtdev_common.hal, channel); - } - - return OK; -} - -/**************************************************************************** - * Name: rmt_write_items - * - * Description: - * This function writes items to the RMT memory for a specific channel. It - * checks the validity of the parameters, calculates the memory blocks and - * item lengths, and fills the memory with the items. If the number of - * items is greater than the memory block length, it enables the TX - * threshold interrupt and sets up the remaining items to be sent. If the - * number of items is less than the memory block length, it fills the - * remaining memory with idle level items. It then starts the TX process - * and waits for it to finish if specified. - * - * Input Parameters: - * channel - The RMT peripheral channel number. - * rmt_item - Pointer to the items to be written to the RMT memory. - * item_num - The number of items to be written. - * wait_tx_done - Flag to indicate whether to wait for the TX process to - * finish. - * - * Returned Value: - * Returns OK on successful writing of the items to the RMT memory; a - * negated errno value is returned on any failure. - * - ****************************************************************************/ - -static int rmt_write_items(rmt_channel_t channel, - const rmt_item32_t *rmt_item, - int item_num, - bool wait_tx_done) -{ - DEBUGASSERT(RMT_IS_TX_CHANNEL(channel)); - DEBUGASSERT(p_rmt_obj[channel]); - DEBUGASSERT(rmt_item); - DEBUGASSERT(item_num > 0); - - uint32_t mem_blocks = rmt_ll_tx_get_mem_blocks(g_rmtdev_common.hal.regs, - channel); - - DEBUGASSERT(mem_blocks + channel <= SOC_RMT_CHANNELS_PER_GROUP); -#ifdef CONFIG_SPIRAM_USE_MALLOC - if (p_rmt_obj[channel]->intr_alloc_flags & ESP_INTR_FLAG_IRAM) - { - if (!esp_ptr_internal(rmt_item)) - { - rmterr(RMT_PSRAM_BUFFER_WARN_STR); - return ESP_ERR_INVALID_ARG; - } - } -#endif - - rmt_obj_t *p_rmt = p_rmt_obj[channel]; - int item_block_len = mem_blocks * RMT_MEM_ITEM_NUM; - int item_sub_len = mem_blocks * RMT_MEM_ITEM_NUM / 2; - int len_rem = item_num; - nxsem_wait(&p_rmt->tx_sem); - - /* fill the memory block first */ - - if (item_num >= item_block_len) - { - rmt_fill_memory(channel, rmt_item, item_block_len, 0); - len_rem -= item_block_len; - rmt_set_tx_loop_mode(channel, false); - rmt_set_tx_thr_intr_en(channel, 1, item_sub_len); - p_rmt->tx_data = rmt_item + item_block_len; - p_rmt->tx_len_rem = len_rem; - p_rmt->tx_offset = 0; - p_rmt->tx_sub_len = item_sub_len; - } - else - { - rmt_idle_level_t idle_level; - rmt_fill_memory(channel, rmt_item, len_rem, 0); - idle_level = rmt_ll_tx_get_idle_level(g_rmtdev_common.hal.regs, - channel); - rmt_item32_t stop_data = (rmt_item32_t) - { - .level0 = idle_level, - .duration0 = 0, - }; - - rmt_fill_memory(channel, &stop_data, 1, len_rem); - p_rmt->tx_len_rem = 0; - } - - rmt_tx_start(channel, true); - p_rmt->wait_done = wait_tx_done; - if (wait_tx_done) - { - /* wait loop done */ - - if (rmt_ll_tx_is_loop_enabled(g_rmtdev_common.hal.regs, channel)) - { -#if SOC_RMT_SUPPORT_TX_LOOP_COUNT - nxsem_wait(&p_rmt->tx_sem); - nxsem_post(&p_rmt->tx_sem); -#endif - } - else - { - /* wait tx end */ - - nxsem_wait(&p_rmt->tx_sem); - nxsem_post(&p_rmt->tx_sem); - } - } - - return OK; -} - -/**************************************************************************** - * Name: esp_rmt_read - * - * Description: - * This function reads data from the RMT device. - * It starts the RMT module in receiving mode for a specific channel and - * checks for any errors. If an error occurs during the start of the RMT - * module, it returns the error code. Please note that this function - * starts the receiver, but the actual data is read from the ring buffer - * by the upper half driver. - * - * Input Parameters: - * dev - Pointer to the RMT device structure. - * buffer - Pointer to the buffer where the read data should be stored. - * buflen - The maximum amount of data to be read. - * - * Returned Value: - * Returns the number of bytes read from the RMT device; a negated errno - * value is returned on any failure. - * - ****************************************************************************/ - -static ssize_t esp_rmt_read(struct rmt_dev_s *dev, char *buffer, - size_t buflen) -{ - struct rmt_dev_lowerhalf_s *priv = (struct rmt_dev_lowerhalf_s *)dev; - rmt_mode_t mode = priv->mode; - int channel = priv->minor; - int ret; - ssize_t nread; - - if (mode != RMT_MODE_RX) + priv->circbuf = kmm_zalloc(sizeof(struct circbuf_s)); + if (priv->circbuf == NULL) { - rmterr("ERROR: RMT channel %d is not in RX mode\n", channel); - return -EINVAL; - } - - DEBUGASSERT((buflen % 4) == 0); - - if ((buflen / 4) > (CONFIG_RMT_DEFAULT_RX_BUFFER_SIZE / 4)) - { - rmtwarn("WARN: RMT RX buffer (%d bytes) is smaller than requested " - "read bytes (%d bytes). A partial read will take place!\n", - CONFIG_RMT_DEFAULT_RX_BUFFER_SIZE, - buflen); - } - -#ifndef SOC_RMT_SUPPORT_RX_PINGPONG - if ((buflen / 4) > RMT_MEM_ITEM_NUM) - { - rmtwarn("WARN: RMT RX channel is able to receive up to " - "%d RMT items (%d bytes)!", - RMT_MEM_ITEM_NUM, RMT_MEM_ITEM_NUM * 4); - } -#endif - - ret = rmt_rx_start(channel, true); - if (ret < 0) - { - rmterr("ERROR: rmt_rx_start failed: %d\n", ret); - return (ssize_t)ret; + rmterr("ERROR: memory allocation failed\n"); + return NULL; } - return (ssize_t)ret; -} - -/**************************************************************************** - * Name: esp_rmt_write - * - * Description: - * This function writes data to the RMT memory for a specific channel. It - * asserts that the length of the data is a multiple of 4, then calls the - * rmt_write_items function to write the items to the RMT memory. - * - * Input Parameters: - * dev - Pointer to the RMT device structure. - * buffer - Pointer to the data to be written to the RMT memory. - * buflen - The length of the data to be written. - * - * Returned Value: - * Returns the number of items written to the RMT memory. - * - ****************************************************************************/ - -static ssize_t esp_rmt_write(struct rmt_dev_s *dev, const char *buffer, - size_t buflen) -{ - struct rmt_dev_lowerhalf_s *priv = (struct rmt_dev_lowerhalf_s *)dev; - rmt_mode_t mode = priv->mode; - int channel = priv->minor; - int ret; - struct timespec timeout; - - if (mode != RMT_MODE_TX) + ret = circbuf_init(priv->circbuf, NULL, + CONFIG_RMT_DEFAULT_RX_BUFFER_SIZE); + if (ret != OK) { - rmterr("ERROR: RMT channel %d is not in TX mode\n", channel); - return -EINVAL; + rmterr("Failed to Initialize RMT RX buffer"); + return NULL; } - DEBUGASSERT((buflen % 4) == 0); - - ret = rmt_write_items(channel, (const rmt_item32_t *)buffer, - (buflen / 4), true); - - if (ret < 0) + esp_ret = rmt_rx_register_event_callbacks(rx_chan, &cbs, priv); + if (esp_ret != ESP_OK) { - rmterr("ERROR: rmt_write_items failed: %d\n", ret); - return (ssize_t)0; + rmterr("Failed to Register RMT RX event callbacks"); + return NULL; } - return (ssize_t)buflen; -} - -/**************************************************************************** - * Name: esp_rmtinitialize - * - * Description: - * This function initializes the specified RMT (Remote Control) device - * with the provided configuration. - * - * Input Parameters: - * config - A structure containing the configuration settings for the - * RMT channel to be initialized. - * - * Returned Value: - * On success, this function returns a valid pointer to the RMT device - * structure. If the initialization fails, it returns NULL. - * - ****************************************************************************/ - -static struct rmt_dev_s - *esp_rmtinitialize(struct rmt_channel_config_s config) -{ - struct rmt_dev_lowerhalf_s *priv; - int ret; -#ifdef CONFIG_RMT_LOOP_TEST_MODE - uint8_t channel; -#endif - -#if (CONFIG_RMT_DEFAULT_RX_BUFFER_SIZE % 4) != 0 -# error "CONFIG_RMT_DEFAULT_RX_BUFFER_SIZE must be a multiple of 4" -#endif - - priv = kmm_zalloc(sizeof(struct rmt_dev_lowerhalf_s)); - if (priv) - { - ret = rmt_config(&config); - if (ret < 0) - { - rmterr("ERROR: rmt_config failed: %d\n", ret); - return NULL; - } - -#ifdef CONFIG_RMT_LOOP_TEST_MODE - if (config.rmt_mode == RMT_MODE_TX) - { - if (g_tx_channel != RMT_CHANNEL_MAX) - { - rmterr("ERROR: only one TX channel can be used in loop test " - "mode\n"); - PANIC(); - } - - g_tx_channel = config.channel; - } - else - { - if (g_rx_channel != RMT_CHANNEL_MAX) - { - rmterr("ERROR: only one RX channel can be used in loop test " - "mode\n"); - PANIC(); - } - - g_rx_channel = config.channel; - } - - if (g_rx_channel != RMT_CHANNEL_MAX && g_tx_channel != RMT_CHANNEL_MAX) - { - esp_configgpio(config.gpio_num, GPIO_OUT_FUNC | GPIO_IN_FUNC); - esp_gpio_matrix_out(config.gpio_num, - RMT_SIG_OUT0_IDX + g_tx_channel, - 0, 0); - esp_gpio_matrix_in(config.gpio_num, - RMT_SIG_IN0_IDX + g_rx_channel, - 0); - rmtwarn("RX channel %d and TX channel %d are used in loop test " - "mode\n", g_rx_channel, g_tx_channel); - } -#endif - - ret = rmt_driver_install(config.channel, - config.rmt_mode == RMT_MODE_RX ? \ - CONFIG_RMT_DEFAULT_RX_BUFFER_SIZE : 0, 0); - if (ret < 0) - { - rmterr("ERROR: rmt_driver_install failed: %d\n", ret); - return NULL; - } - - priv->ops = &g_rmtops; - priv->recvsem = &p_rmt_obj[config.channel]->rx_sem; - priv->circbuf = &p_rmt_obj[config.channel]->rx_buf; - priv->minor = config.channel; - - priv->common = &g_rmtdev_common; - priv->mode = config.rmt_mode; - } - else + esp_ret = rmt_enable(rx_chan); + if (esp_ret != ESP_OK) { - rmterr("ERROR: memory allocation failed\n"); + rmterr("Failed to Enable RMT RX channel"); return NULL; } return (struct rmt_dev_s *)priv; } -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: esp_rmt_tx_init - * - * Description: - * Initialize the selected RMT device in TX mode - * - * Input Parameters: - * ch - The RMT's channel that will be used - * pin - The pin used for the TX channel - * - * Returned Value: - * Valid RMT device structure reference on success; NULL, otherwise. - * - ****************************************************************************/ - -struct rmt_dev_s *esp_rmt_tx_init(int ch, int pin) -{ - struct rmt_channel_config_s config = RMT_DEFAULT_CONFIG_TX(pin, ch); - - return esp_rmtinitialize(config); -} - -/**************************************************************************** - * Name: esp_rmt_rx_init - * - * Description: - * Initialize the selected RMT device in RC mode - * - * Input Parameters: - * ch - The RMT's channel that will be used - * pin - The pin used for the RX channel - * - * Returned Value: - * Valid RMT device structure reference on success; NULL, otherwise. - * - ****************************************************************************/ - -struct rmt_dev_s *esp_rmt_rx_init(int ch, int pin) -{ - struct rmt_channel_config_s config = RMT_DEFAULT_CONFIG_RX(pin, ch); - - return esp_rmtinitialize(config); -} - #endif diff --git a/arch/xtensa/src/common/espressif/esp_rmt.h b/arch/xtensa/src/common/espressif/esp_rmt.h index a58988a73d7a9..943db6a88ba48 100644 --- a/arch/xtensa/src/common/espressif/esp_rmt.h +++ b/arch/xtensa/src/common/espressif/esp_rmt.h @@ -20,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_RMT_H -#define __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_RMT_H +#ifndef __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_RMT_NEW_H +#define __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_RMT_NEW_H /**************************************************************************** * Included Files @@ -68,38 +68,36 @@ extern "C" #if defined(CONFIG_ESP_RMT) /**************************************************************************** - * Name: esp_rmt_tx_init + * Name: esp_rmt_rx_init * * Description: - * Initialize the selected RMT device in TX mode + * Initialize the selected RMT device in RX mode * * Input Parameters: - * ch - The RMT's channel that will be used - * pin - The pin used for the TX channel + * rx_pin - The pin used for the RX channel * * Returned Value: * Valid RMT device structure reference on success; NULL, otherwise. * ****************************************************************************/ -struct rmt_dev_s *esp_rmt_tx_init(int ch, int pin); +struct rmt_dev_s *esp_rmt_rx_init(int rx_pin); /**************************************************************************** - * Name: esp_rmt_rx_init + * Name: esp_rmt_tx_init * * Description: - * Initialize the selected RMT device in RC mode + * Initialize the selected RMT device in TX mode * * Input Parameters: - * ch - The RMT's channel that will be used - * pin - The pin used for the RX channel + * tx_pin - The pin used for the TX channel * * Returned Value: * Valid RMT device structure reference on success; NULL, otherwise. * ****************************************************************************/ -struct rmt_dev_s *esp_rmt_rx_init(int ch, int pin); +struct rmt_dev_s *esp_rmt_tx_init(int tx_pin); #endif @@ -108,4 +106,4 @@ struct rmt_dev_s *esp_rmt_rx_init(int ch, int pin); #endif #endif /* __ASSEMBLY__ */ -#endif /* __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_RMT_H */ +#endif /* __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_RMT_NEW_H */ diff --git a/arch/xtensa/src/common/espressif/esp_rtc.c b/arch/xtensa/src/common/espressif/esp_rtc.c new file mode 100644 index 0000000000000..63ea7a54f6528 --- /dev/null +++ b/arch/xtensa/src/common/espressif/esp_rtc.c @@ -0,0 +1,895 @@ +/**************************************************************************** + * arch/xtensa/src/common/espressif/esp_rtc.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "clock/clock.h" + +#include "esp_timer_adapter.h" +#include "esp_rtc.h" +#include "esp_rtc_time.h" +#include "xtensa.h" + +#include "esp_attr.h" +#include "soc/rtc.h" + +#include "rom/rtc.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The magic data for the struct esp_rtc_backup_s that is in RTC slow + * memory. + */ + +#define MAGIC_RTC_SAVE (UINT64_C(0x11223344556677)) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +#ifdef CONFIG_RTC_DRIVER + +#ifdef CONFIG_RTC_ALARM +struct alm_cbinfo_s +{ + struct esp_hr_timer_s *alarm_hdl; /* Timer id point to here */ + rtc_alarm_callback_t ac_cb; /* Client callback function */ + volatile void *ac_arg; /* Argument to pass with the callback function */ + uint64_t deadline_us; + uint8_t index; +}; +#endif /* CONFIG_RTC_ALARM */ + +/* This is the private type for the RTC state. It must be cast compatible + * with struct rtc_lowerhalf_s. + */ + +struct esp_rtc_lowerhalf_s +{ + /* This is the contained reference to the read-only, lower-half + * operations vtable (which may lie in FLASH or ROM) + */ + + const struct rtc_ops_s *ops; +#ifdef CONFIG_RTC_ALARM + /* Alarm callback information */ + + struct alm_cbinfo_s alarmcb[CONFIG_RTC_NALARMS]; +#endif /* CONFIG_RTC_ALARM */ + + spinlock_t lock; +}; + +#endif/* CONFIG_RTC_DRIVER */ + +struct esp_rtc_backup_s +{ + uint64_t magic; + int64_t offset; /* Offset time from RTC HW value */ + int64_t reserved0; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Prototypes for static methods in struct rtc_ops_s */ + +#ifdef CONFIG_RTC_DRIVER +static int esp_rtc_rdtime(struct rtc_lowerhalf_s *lower, + struct rtc_time *rtctime); +static int esp_rtc_settime(struct rtc_lowerhalf_s *lower, + const struct rtc_time *rtctime); +static bool esp_rtc_havesettime(struct rtc_lowerhalf_s *lower); + +#ifdef CONFIG_RTC_ALARM +static void IRAM_ATTR rtc_hr_timer_cb(void *arg); +static int esp_rtc_setalarm(struct rtc_lowerhalf_s *lower, + const struct lower_setalarm_s *alarminfo); +static int esp_rtc_setrelative(struct rtc_lowerhalf_s *lower, + const struct lower_setrelative_s *alarminfo); +static int esp_rtc_cancelalarm(struct rtc_lowerhalf_s *lower, + int alarmid); +static int esp_rtc_rdalarm(struct rtc_lowerhalf_s *lower, + struct lower_rdalarm_s *alarminfo); +#endif /* CONFIG_RTC_ALARM */ +#endif /* CONFIG_RTC_DRIVER */ + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_RTC_DRIVER +/* RTC driver operations */ + +static const struct rtc_ops_s g_rtc_ops = +{ + .rdtime = esp_rtc_rdtime, + .settime = esp_rtc_settime, + .havesettime = esp_rtc_havesettime, +#ifdef CONFIG_RTC_ALARM + .setalarm = esp_rtc_setalarm, + .setrelative = esp_rtc_setrelative, + .cancelalarm = esp_rtc_cancelalarm, + .rdalarm = esp_rtc_rdalarm, +#endif /* CONFIG_RTC_ALARM */ +}; + +/* RTC device state */ + +static struct esp_rtc_lowerhalf_s g_rtc_lowerhalf = +{ + .ops = &g_rtc_ops +}; + +/* Flag for tracking HR Timer enable status */ + +static bool g_hr_timer_enabled = false; + +#endif /* CONFIG_RTC_DRIVER */ + +/* Saved data for persistent RTC time */ + +static RTC_DATA_ATTR struct esp_rtc_backup_s g_rtc_saved_data; +static struct esp_rtc_backup_s *g_rtc_save; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +volatile bool g_rtc_enabled = false; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp_rtc_set_boot_time + * + * Description: + * Set time to RTC register to replace the original boot time. + * + * Input Parameters: + * time_us - set time in microseconds. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void IRAM_ATTR esp_rtc_set_boot_time(uint64_t time_us) +{ + putreg32((uint32_t)(time_us & UINT32_MAX), RTC_BOOT_TIME_LOW_REG); + putreg32((uint32_t)(time_us >> 32), RTC_BOOT_TIME_HIGH_REG); +} + +/**************************************************************************** + * Name: esp_rtc_get_boot_time + * + * Description: + * Get time of RTC register to indicate the original boot time. + * + * Input Parameters: + * None. + * + * Returned Value: + * Boot time in microseconds. + * + ****************************************************************************/ + +static uint64_t IRAM_ATTR esp_rtc_get_boot_time(void) +{ + return ((uint64_t)getreg32(RTC_BOOT_TIME_LOW_REG)) + + (((uint64_t)getreg32(RTC_BOOT_TIME_HIGH_REG)) << 32); +} + +/**************************************************************************** + * Name: rtc_hr_timer_cb + * + * Description: + * Callback to be called upon HR-Timer expiration. + * + * Input Parameters: + * arg - Information about the HR-Timer configuration. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +#if defined(CONFIG_RTC_DRIVER) && defined(CONFIG_RTC_ALARM) +static void IRAM_ATTR rtc_hr_timer_cb(void *arg) +{ + struct alm_cbinfo_s *cbinfo = (struct alm_cbinfo_s *)arg; + rtc_alarm_callback_t cb; + void *cb_arg; + int alminfo_id; + + DEBUGASSERT(cbinfo != NULL); + + alminfo_id = cbinfo->index; + + if (cbinfo->ac_cb != NULL) + { + /* Alarm callback */ + + cb = cbinfo->ac_cb; + cb_arg = (void *)cbinfo->ac_arg; + cbinfo->ac_cb = NULL; + cbinfo->ac_arg = NULL; + cbinfo->deadline_us = 0; + cb(cb_arg, alminfo_id); + } +} +#endif /* CONFIG_RTC_DRIVER */ + +/**************************************************************************** + * Name: esp_rtc_rdtime + * + * Description: + * Return the current RTC time. + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure. + * rcttime - The location in which to return the current RTC time. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_DRIVER + +#ifdef CONFIG_RTC_HIRES +static int esp_rtc_rdtime(struct rtc_lowerhalf_s *lower, + struct rtc_time *rtctime) +{ + struct timespec ts; + int ret; + + /* Get the higher resolution time */ + + ret = up_rtc_gettime(&ts); + if (ret < 0) + { + goto errout; + } + + /* Convert the one second epoch time to a struct tmThis operation + * depends on the fact that struct rtc_time and struct tm are cast + * compatible. + */ + + if (!gmtime_r(&ts.tv_sec, (struct tm *)rtctime)) + { + ret = -get_errno(); + goto errout; + } + + return OK; + +errout: + rtcerr("Failed to get RTC time: %d\n", ret); + return ret; +} + +#else /* !CONFIG_RTC_HIRES */ + +static int esp_rtc_rdtime(struct rtc_lowerhalf_s *lower, + struct rtc_time *rtctime) +{ + time_t timer; + + /* The resolution of time is only 1 second */ + + timer = up_rtc_time(); + + /* Convert the one second epoch time to a struct tm */ + + if (gmtime_r(&timer, (struct tm *)rtctime) == 0) + { + int errcode = get_errno(); + DEBUGASSERT(errcode > 0); + + rtcerr("gmtime_r failed: %d\n", errcode); + return -errcode; + } + + return OK; +} +#endif /* CONFIG_RTC_HIRES */ + +#endif /* CONFIG_RTC_DRIVER */ + +/**************************************************************************** + * Name: esp_rtc_settime + * + * Description: + * Implement the settime() method of the RTC driver interface. + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure. + * rcttime - The new time to set. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_DRIVER +static int esp_rtc_settime(struct rtc_lowerhalf_s *lower, + const struct rtc_time *rtctime) +{ + struct timespec ts; + + /* Convert the struct rtc_time to a time_t. Here we assume that struct + * rtc_time is cast compatible with struct tm. + */ + + ts.tv_sec = mktime((struct tm *)rtctime); + ts.tv_nsec = 0; + + /* Now set the time (with a accuracy of seconds) */ + + return up_rtc_settime(&ts); +} +#endif /* CONFIG_RTC_DRIVER */ + +/**************************************************************************** + * Name: esp_rtc_havesettime + * + * Description: + * Implement the havesettime() method of the RTC driver interface. + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure. + * + * Returned Value: + * True if RTC date-time have been previously set, false otherwise. + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_DRIVER +static bool esp_rtc_havesettime(struct rtc_lowerhalf_s *lower) +{ + return esp_rtc_get_boot_time() != 0; +} +#endif /* CONFIG_RTC_DRIVER */ + +/**************************************************************************** + * Name: esp_rtc_setalarm + * + * Description: + * Set a new alarm. This function implements the setalarm() method of the + * RTC driver interface. + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure. + * alarminfo - Provided information needed to set the alarm. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +#if defined(CONFIG_RTC_DRIVER) && defined(CONFIG_RTC_ALARM) +static int esp_rtc_setalarm_nolock(struct rtc_lowerhalf_s *lower, + const struct lower_setalarm_s *alarminfo) +{ + struct esp_rtc_lowerhalf_s *priv = (struct esp_rtc_lowerhalf_s *)lower; + struct alm_cbinfo_s *cbinfo; + uint64_t timeout; + int id; + + DEBUGASSERT(priv != NULL); + DEBUGASSERT(alarminfo != NULL); + + timeout = mktime((struct tm *)&alarminfo->time); + + /* Set the alarm in RT-Timer */ + + id = alarminfo->id; + cbinfo = &priv->alarmcb[id]; + + if (cbinfo->ac_cb != NULL) + { + return -EBUSY; + } + + /* Create the RT-Timer alarm */ + + if (cbinfo->alarm_hdl == NULL) + { + struct esp_hr_timer_args_s hr_timer_args; + int ret; + + cbinfo->index = id; + hr_timer_args.arg = cbinfo; + hr_timer_args.callback = rtc_hr_timer_cb; + + ret = esp_hr_timer_create(&hr_timer_args, &cbinfo->alarm_hdl); + if (ret < 0) + { + rtcerr("Failed to create HR Timer=%d\n", ret); + + return ret; + } + } + + cbinfo->ac_cb = alarminfo->cb; + cbinfo->ac_arg = alarminfo->priv; + cbinfo->deadline_us = timeout * USEC_PER_SEC; + + rtcinfo("Starting alarm ID %d\n", id); + + esp_hr_timer_start(cbinfo->alarm_hdl, cbinfo->deadline_us, false); + + return OK; +} + +static int esp_rtc_setalarm(struct rtc_lowerhalf_s *lower, + const struct lower_setalarm_s *alarminfo) +{ + struct esp_rtc_lowerhalf_s *priv = (struct esp_rtc_lowerhalf_s *)lower; + irqstate_t flags; + int ret; + + flags = spin_lock_irqsave(&priv->lock); + ret = esp_rtc_setalarm_nolock(lower, alarminfo); + spin_unlock_irqrestore(&priv->lock, flags); + + return ret; +} +#endif /* CONFIG_RTC_DRIVER && CONFIG_RTC_ALARM */ + +/**************************************************************************** + * Name: esp_rtc_setrelative + * + * Description: + * Set a new alarm relative to the current time. This function implements + * the setrelative() method of the RTC driver interface. + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure. + * alarminfo - Provided information needed to set the alarm. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +#if defined(CONFIG_RTC_DRIVER) && defined(CONFIG_RTC_ALARM) +static int esp_rtc_setrelative(struct rtc_lowerhalf_s *lower, + const struct lower_setrelative_s *alarminfo) +{ + struct esp_rtc_lowerhalf_s *priv = (struct esp_rtc_lowerhalf_s *)lower; + struct lower_setalarm_s setalarm; + time_t seconds; + int ret = -EINVAL; + irqstate_t flags; + + DEBUGASSERT(lower != NULL && alarminfo != NULL); + + if (alarminfo->reltime > 0) + { + flags = spin_lock_irqsave(&priv->lock); + + seconds = alarminfo->reltime; + gmtime_r(&seconds, (struct tm *)&setalarm.time); + + /* The set the alarm using this absolute time */ + + setalarm.id = alarminfo->id; + setalarm.cb = alarminfo->cb; + setalarm.priv = alarminfo->priv; + ret = esp_rtc_setalarm_nolock(lower, &setalarm); + + spin_unlock_irqrestore(&priv->lock, flags); + } + + return ret; +} +#endif /* CONFIG_RTC_DRIVER && CONFIG_RTC_ALARM */ + +/**************************************************************************** + * Name: esp_rtc_cancelalarm + * + * Description: + * Cancel the current alarm. This function implements the cancelalarm() + * method of the RTC driver interface. + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure. + * alarmid - ID of the alarm to be cancelled. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +#if defined(CONFIG_RTC_DRIVER) && defined(CONFIG_RTC_ALARM) +static int esp_rtc_cancelalarm(struct rtc_lowerhalf_s *lower, int alarmid) +{ + struct esp_rtc_lowerhalf_s *priv; + struct alm_cbinfo_s *cbinfo; + irqstate_t flags; + + DEBUGASSERT(lower != NULL); + + priv = (struct esp_rtc_lowerhalf_s *)lower; + + /* Set the alarm in hardware and enable interrupts */ + + cbinfo = &priv->alarmcb[alarmid]; + + if (cbinfo->ac_cb == NULL) + { + return -ENODATA; + } + + flags = spin_lock_irqsave(&priv->lock); + + /* Stop and delete the alarm */ + + rtcinfo("Cancelling alarm ID %d\n", alarmid); + + esp_hr_timer_stop(cbinfo->alarm_hdl); + esp_hr_timer_delete(cbinfo->alarm_hdl); + + cbinfo->ac_cb = NULL; + cbinfo->deadline_us = 0; + cbinfo->alarm_hdl = NULL; + + spin_unlock_irqrestore(&priv->lock, flags); + + return OK; +} +#endif /* CONFIG_RTC_DRIVER && CONFIG_RTC_ALARM */ + +/**************************************************************************** + * Name: esp_rtc_rdalarm + * + * Description: + * Query the RTC alarm. + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure. + * alarminfo - Provided information needed to query the alarm. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +#if defined(CONFIG_RTC_DRIVER) && defined(CONFIG_RTC_ALARM) +static int esp_rtc_rdalarm(struct rtc_lowerhalf_s *lower, + struct lower_rdalarm_s *alarminfo) +{ + struct esp_rtc_lowerhalf_s *priv; + struct timespec ts; + struct alm_cbinfo_s *cbinfo; + irqstate_t flags; + + DEBUGASSERT(lower != NULL); + DEBUGASSERT(alarminfo != NULL); + DEBUGASSERT(alarminfo->time != NULL); + + priv = (struct esp_rtc_lowerhalf_s *)lower; + + flags = spin_lock_irqsave(&priv->lock); + + /* Get the alarm according to the alarm ID */ + + cbinfo = &priv->alarmcb[alarminfo->id]; + + ts.tv_sec = (esp_hr_timer_time_us() + g_rtc_save->offset + + cbinfo->deadline_us) / USEC_PER_SEC; + ts.tv_nsec = ((esp_hr_timer_time_us() + g_rtc_save->offset + + cbinfo->deadline_us) % USEC_PER_SEC) * NSEC_PER_USEC; + + localtime_r((const time_t *)&ts.tv_sec, + (struct tm *)alarminfo->time); + + spin_unlock_irqrestore(&priv->lock, flags); + + return OK; +} +#endif /* CONFIG_RTC_DRIVER && CONFIG_RTC_ALARM */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_rtc_time + * + * Description: + * Get the current time in seconds. This is similar to the standard time() + * function. This interface is only required if the low-resolution + * RTC/counter hardware implementation is selected. It is only used by the + * RTOS during initialization to set up the system time when CONFIG_RTC is + * set but CONFIG_RTC_HIRES is not set. + * + * Input Parameters: + * None. + * + * Returned Value: + * Current time in seconds. + * + ****************************************************************************/ + +#ifndef CONFIG_RTC_HIRES +time_t up_rtc_time(void) +{ + uint64_t time_us; + irqstate_t flags; + + flags = spin_lock_irqsave(&g_rtc_lowerhalf.lock); + +#ifdef CONFIG_RTC_DRIVER + /* NOTE: HR-Timer starts to work after the board is initialized, and the + * RTC controller starts works after up_rtc_initialize is initialized. + * Since the system clock starts to work before the board is initialized, + * if CONFIG_RTC is enabled, the system time must be matched by the time + * of the RTC controller (up_rtc_initialize has already been initialized, + * and HR-Timer cannot work). + */ + + /* Determine if HR-Timer is started */ + + if (g_hr_timer_enabled) + { + /* Get the time from HR-Timer, the time interval between RTC + * controller and HR-Timer is stored in g_rtc_save->offset. + */ + + time_us = esp_hr_timer_time_us() + g_rtc_save->offset + + esp_rtc_get_boot_time(); + } + else +#endif + { + /* Get the time from RTC controller */ + + time_us = esp_rtc_get_time_us() + esp_rtc_get_boot_time(); + } + + spin_unlock_irqrestore(&g_rtc_lowerhalf.lock, flags); + + return (time_t)(time_us / USEC_PER_SEC); +} +#endif /* !CONFIG_RTC_HIRES */ + +/**************************************************************************** + * Name: up_rtc_gettime + * + * Description: + * Get the current time from the high resolution RTC time or HR-Timer. This + * interface is only supported by the high-resolution RTC/counter hardware + * implementation. It is used to replace the system timer. + * + * Input Parameters: + * tp - The location to return the RTC time or HR-Timer value. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_HIRES +int up_rtc_gettime(struct timespec *tp) +{ + irqstate_t flags; + uint64_t time_us; + + flags = spin_lock_irqsave(&g_rtc_lowerhalf.lock); + +#ifdef CONFIG_RTC_DRIVER + if (g_hr_timer_enabled) + { + time_us = esp_hr_timer_time_us() + g_rtc_save->offset + + esp_rtc_get_boot_time(); + } + else +#endif + { + time_us = esp_rtc_get_time_us() + esp_rtc_get_boot_time(); + } + + tp->tv_sec = time_us / USEC_PER_SEC; + tp->tv_nsec = (time_us % USEC_PER_SEC) * NSEC_PER_USEC; + + spin_unlock_irqrestore(&g_rtc_lowerhalf.lock, flags); + + return OK; +} +#endif /* CONFIG_RTC_HIRES */ + +/**************************************************************************** + * Name: up_rtc_settime + * + * Description: + * Set the RTC to the provided time. All RTC implementations must be + * able to set their time based on a standard timespec. + * + * Input Parameters: + * ts - Time to set. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +int up_rtc_settime(const struct timespec *ts) +{ + uint64_t now_us; + uint64_t rtc_offset_us; + irqstate_t flags; + + DEBUGASSERT(ts != NULL && ts->tv_nsec < NSEC_PER_SEC); + + flags = spin_lock_irqsave(&g_rtc_lowerhalf.lock); + + now_us = ((uint64_t) ts->tv_sec) * USEC_PER_SEC + + ts->tv_nsec / NSEC_PER_USEC; + +#ifdef CONFIG_RTC_DRIVER + if (g_hr_timer_enabled) + { + /* Set based on HR-Timer offset value */ + + rtc_offset_us = now_us - esp_hr_timer_time_us(); + } + else +#endif + { + /* Set based on the offset value of the RTC controller */ + + rtc_offset_us = now_us - esp_rtc_get_time_us(); + } + + g_rtc_save->offset = 0; + + esp_rtc_set_boot_time(rtc_offset_us); + + spin_unlock_irqrestore(&g_rtc_lowerhalf.lock, flags); + + return OK; +} + +/**************************************************************************** + * Name: up_rtc_initialize + * + * Description: + * Initialize the hardware RTC according to the selected configuration. + * This function is called once during the OS initialization sequence. + * + * Input Parameters: + * None. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +int up_rtc_initialize(void) +{ + g_rtc_save = &g_rtc_saved_data; + + /* If saved data is invalid, clear offset information */ + + if (g_rtc_save->magic != MAGIC_RTC_SAVE) + { + g_rtc_save->magic = MAGIC_RTC_SAVE; + g_rtc_save->offset = 0; + esp_rtc_set_boot_time(0); + } + +#ifdef CONFIG_RTC_HIRES + /* Synchronize the base time to the RTC time */ + + up_rtc_gettime(&g_basetime); +#endif + + g_rtc_enabled = true; + + return OK; +} + +/**************************************************************************** + * Name: esp_rtc_driverinit + * + * Description: + * Initialize and register an RTC lower half driver. + * + * Input Parameters: + * None. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_DRIVER +int esp_rtc_driverinit(void) +{ + struct rtc_lowerhalf_s *lower = (struct rtc_lowerhalf_s *)&g_rtc_lowerhalf; + + /* Initialize RTC */ + + int ret = up_rtc_initialize(); + if (ret < 0) + { + return ret; + } + + ret = rtc_initialize(0, lower); + if (ret < 0) + { + return ret; + } + + /* Enable HR-Timer */ + + ret = esp_hr_timer_init(); + if (ret < 0) + { + return ret; + } + + spin_lock_init(&g_rtc_lowerhalf.lock); + g_hr_timer_enabled = true; + + /* Get the time difference between HR Timer and RTC */ + + g_rtc_save->offset = esp_rtc_get_time_us() - esp_hr_timer_time_us(); + + return ret; +} +#endif /* CONFIG_RTC_DRIVER */ diff --git a/arch/xtensa/src/esp32/esp32_rtc_lowerhalf.h b/arch/xtensa/src/common/espressif/esp_rtc.h similarity index 73% rename from arch/xtensa/src/esp32/esp32_rtc_lowerhalf.h rename to arch/xtensa/src/common/espressif/esp_rtc.h index a5ef77ed98dbc..3ca78b9a4edff 100644 --- a/arch/xtensa/src/esp32/esp32_rtc_lowerhalf.h +++ b/arch/xtensa/src/common/espressif/esp_rtc.h @@ -1,5 +1,7 @@ /**************************************************************************** - * arch/xtensa/src/esp32/esp32_rtc_lowerhalf.h + * arch/xtensa/src/common/espressif/esp_rtc.h + * + * SPDX-License-Identifier: Apache-2.0 * * Licensed to the Apache Software Foundation (ASF) under one or more * contributor license agreements. See the NOTICE file distributed with @@ -18,8 +20,8 @@ * ****************************************************************************/ -#ifndef __ARCH_XTENSA_SRC_ESP32_ESP32_RTC_LOWERHALF_H -#define __ARCH_XTENSA_SRC_ESP32_ESP32_RTC_LOWERHALF_H +#ifndef __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_RTC_H +#define __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_RTC_H /**************************************************************************** * Included Files @@ -27,30 +29,25 @@ #include -#ifdef CONFIG_RTC_DRIVER - /**************************************************************************** * Public Function Prototypes ****************************************************************************/ /**************************************************************************** - * Name: esp32_rtc_driverinit + * Name: esp_rtc_driverinit * * Description: - * Bind the configuration timer to a timer lower half instance and register - * the timer drivers at 'devpath' + * Initialize and register an RTC lower half driver. * * Input Parameters: - * None + * None. * * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned - * to indicate the nature of any failure. + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. * ****************************************************************************/ -int esp32_rtc_driverinit(void); - -#endif /* CONFIG_RTC_DRIVER */ +int esp_rtc_driverinit(void); -#endif /* __ARCH_XTENSA_SRC_ESP32_ESP32_RTC_LOWERHALF_H */ +#endif /* __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_RTC_H */ diff --git a/arch/xtensa/src/common/espressif/esp_sdm.c b/arch/xtensa/src/common/espressif/esp_sdm.c index 6c4e208d3ff5a..64c31d21b720d 100644 --- a/arch/xtensa/src/common/espressif/esp_sdm.c +++ b/arch/xtensa/src/common/espressif/esp_sdm.c @@ -42,40 +42,27 @@ #include #include "esp_sdm.h" +#include "hal/gpio_ll.h" #if defined(CONFIG_ARCH_CHIP_ESP32S3) -#include "esp32s3_gpio.h" +#include "esp_gpio.h" #include "hardware/esp32s3_soc.h" #elif defined(CONFIG_ARCH_CHIP_ESP32S2) -#include "esp32s2_gpio.h" +#include "espressif/esp_gpio.h" #include "hardware/esp32s2_soc.h" #elif defined(CONFIG_ARCH_CHIP_ESP32) -#include "esp32_gpio.h" -#include "hardware/esp32_soc.h" +#include "esp_gpio.h" #endif #include "esp_clk_tree.h" #include "hal/sdm_hal.h" #include "hal/sdm_ll.h" -#include "soc/sdm_periph.h" +#include "hal/sdm_periph.h" +#include "hal/sdm_caps.h" /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -#if defined(CONFIG_ARCH_CHIP_ESP32S3) -#define esp_configgpio esp32s3_configgpio -#define esp_gpio_matrix_in esp32s3_gpio_matrix_in -#define esp_gpio_matrix_out esp32s3_gpio_matrix_out -#elif defined(CONFIG_ARCH_CHIP_ESP32S2) -#define esp_configgpio esp32s2_configgpio -#define esp_gpio_matrix_in esp32s2_gpio_matrix_in -#define esp_gpio_matrix_out esp32s2_gpio_matrix_out -#elif defined(CONFIG_ARCH_CHIP_ESP32) -#define esp_configgpio esp32_configgpio -#define esp_gpio_matrix_in esp32_gpio_matrix_in -#define esp_gpio_matrix_out esp32_gpio_matrix_out -#endif - /**************************************************************************** * Private Types ****************************************************************************/ @@ -92,18 +79,18 @@ struct esp_sdm_channel_priv_s struct esp_sdm_group_priv_s { - int group_id; /* Group ID, index from 0 */ - spinlock_t spinlock; /* Spinlock for protecting concurrent operations */ - sdm_hal_context_t hal; /* Common layer context */ - soc_periph_sdm_clk_src_t clk_src; /* Clock source */ - struct esp_sdm_channel_priv_s *channels[SOC_SDM_CHANNELS_PER_GROUP]; /* Array of SDM channels */ + int group_id; /* Group ID, index from 0 */ + spinlock_t spinlock; /* Spinlock for protecting concurrent operations */ + sdm_hal_context_t hal; /* Common layer context */ + soc_periph_sdm_clk_src_t clk_src; /* Clock source */ + struct esp_sdm_channel_priv_s *channels[SDM_CAPS_GET(CHANS_PER_INST)]; /* Array of SDM channels */ }; struct esp_sdm_priv_s { - rmutex_t lock; /* Lock for protecting concurrent operations */ - struct esp_sdm_group_priv_s *groups[SOC_SDM_GROUPS]; /* SDM group pool */ - int group_ref_counts[SOC_SDM_GROUPS]; /* Reference count used to protect group install/uninstall */ + rmutex_t lock; /* Lock for protecting concurrent operations */ + struct esp_sdm_group_priv_s *groups[SDM_CAPS_GET(INST_NUM)]; /* SDM group pool */ + int group_ref_counts[SDM_CAPS_GET(INST_NUM)]; /* Reference count used to protect group install/uninstall */ }; /**************************************************************************** @@ -382,7 +369,7 @@ struct esp_sdm_channel_priv_s *esp_sdm_create_config_channel( esp_configgpio(config.gpio_num, attr); esp_gpio_matrix_out(config.gpio_num, - sigma_delta_periph_signals.channels[ret->chan_id].sd_sig, + soc_sdm_signals[group_id].channels[ret->chan_id].sig_id_matrix, (config.flags && INVERT_OUT), false); esp_clk_tree_src_get_freq_hz(g_esp_sdm.groups[ret->group_id]->clk_src, @@ -431,7 +418,7 @@ static struct esp_sdm_group_priv_s *esp_sdm_init( DEBUGASSERT(GPIO_IS_VALID_GPIO(config.gpio_num)); - for (i = 0; i < SOC_SDM_GROUPS; i++) + for (i = 0; i < SDM_CAPS_GET(INST_NUM); i++) { nxrmutex_lock(&(g_esp_sdm.lock)); if (g_esp_sdm.groups[i] == NULL) @@ -445,16 +432,21 @@ static struct esp_sdm_group_priv_s *esp_sdm_init( } else { + sdm_hal_init_config_t hal_config = + { + .group_id = group_id, + }; + g_esp_sdm.groups[i]->group_id = i; g_esp_sdm.groups[i]->clk_src = SDM_CLK_SRC_DEFAULT; group_id = i; - sdm_hal_init(&g_esp_sdm.groups[i]->hal, i); + sdm_hal_init(&g_esp_sdm.groups[i]->hal, &hal_config); sdm_ll_enable_clock(g_esp_sdm.groups[i]->hal.dev, true); ainfo("new group (%d) at %p\n", i, g_esp_sdm.groups[i]); break; } } - else if (g_esp_sdm.group_ref_counts[i] < SOC_SDM_CHANNELS_PER_GROUP) + else if (g_esp_sdm.group_ref_counts[i] < SDM_CAPS_GET(CHANS_PER_INST)) { group_id = i; break; @@ -462,7 +454,7 @@ static struct esp_sdm_group_priv_s *esp_sdm_init( } if (g_esp_sdm.group_ref_counts[group_id] >= - SOC_SDM_CHANNELS_PER_GROUP) + SDM_CAPS_GET(CHANS_PER_INST)) { aerr("ERROR! No free slot available\n"); return NULL; @@ -473,7 +465,7 @@ static struct esp_sdm_group_priv_s *esp_sdm_init( nxrmutex_unlock(&(g_esp_sdm.lock)); flags = spin_lock_irqsave(&group->spinlock); - for (j = 0; j < SOC_SDM_CHANNELS_PER_GROUP; j++) + for (j = 0; j < SDM_CAPS_GET(CHANS_PER_INST); j++) { if (group->channels[j] == NULL) { @@ -541,7 +533,7 @@ int esp_sdm_create_channel(struct esp_sdm_chan_config_s config, DEBUGASSERT(GPIO_IS_VALID_GPIO(config.gpio_num)); - for (i = 0; i < SOC_SDM_CHANNELS_PER_GROUP; i++) + for (i = 0; i < SDM_CAPS_GET(CHANS_PER_INST); i++) { if (group->channels[i] == NULL) { @@ -602,7 +594,7 @@ struct dac_dev_s *esp_sdminitialize(struct esp_sdm_chan_config_s config) { ret->ad_priv = (void *)sdm; ret->ad_ops = &ops; - ret->ad_nchannel = SOC_SDM_CHANNELS_PER_GROUP; + ret->ad_nchannel = SDM_CAPS_GET(CHANS_PER_INST); } return (struct dac_dev_s *)ret; diff --git a/arch/xtensa/src/common/espressif/esp_sha.c b/arch/xtensa/src/common/espressif/esp_sha.c index d9e1274b906d2..ebe106828ef79 100644 --- a/arch/xtensa/src/common/espressif/esp_sha.c +++ b/arch/xtensa/src/common/espressif/esp_sha.c @@ -39,11 +39,19 @@ #include "esp_sha.h" #include "esp_private/periph_ctrl.h" +#include "esp_private/esp_crypto_lock_internal.h" #include "soc/periph_defs.h" +#include "hal/sha_ll.h" #include "hal/sha_hal.h" #include "soc/soc_caps.h" #include "rom/cache.h" +/* Crypto DMA, shared between AES and SHA */ + +#if SOC_AES_CRYPTO_DMA && SOC_SHA_CRYPTO_DMA +# include "hal/crypto_dma_ll.h" +#endif + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -276,6 +284,7 @@ int esp_sha1_update(struct esp_sha1_context_s *ctx, return ret; } + sha_hal_set_mode(ctx->mode); if (ctx->sha_state == ESP_SHA_STATE_INIT) { ctx->first_block = true; @@ -500,6 +509,7 @@ int esp_sha256_update(struct esp_sha256_context_s *ctx, return ret; } + sha_hal_set_mode(ctx->mode); if (ctx->sha_state == ESP_SHA_STATE_INIT) { ctx->first_block = true; @@ -721,6 +731,7 @@ int esp_sha512_update(struct esp_sha512_context_s *ctx, return ret; } + sha_hal_set_mode(ctx->mode); if (ctx->sha_state == ESP_SHA_STATE_INIT) { ctx->first_block = true; @@ -852,7 +863,17 @@ int esp_sha_init(void) { if (!g_sha_inited) { - periph_module_enable(PERIPH_SHA_MODULE); + SHA_RCC_ATOMIC() + { + sha_ll_enable_bus_clock(true); + sha_ll_reset_register(); + +#if SOC_SHA_CRYPTO_DMA + crypto_dma_ll_enable_bus_clock(true); + crypto_dma_ll_reset_register(); +#endif + } + g_sha_inited = true; } else diff --git a/arch/xtensa/src/common/espressif/esp_spi_bitbang.c b/arch/xtensa/src/common/espressif/esp_spi_bitbang.c index 25133e649ba3f..f2d517efa4abe 100644 --- a/arch/xtensa/src/common/espressif/esp_spi_bitbang.c +++ b/arch/xtensa/src/common/espressif/esp_spi_bitbang.c @@ -43,13 +43,13 @@ #include #if defined(CONFIG_ARCH_CHIP_ESP32S3) -#include "esp32s3_gpio.h" +#include "esp_gpio.h" #include "hardware/esp32s3_gpio_sigmap.h" #elif defined(CONFIG_ARCH_CHIP_ESP32S2) -#include "esp32s2_gpio.h" +#include "espressif/esp_gpio.h" #include "esp32s2_gpio_sigmap.h" #else -#include "esp32_gpio.h" +#include "esp_gpio.h" #include "esp32_gpio_sigmap.h" #endif @@ -58,16 +58,17 @@ ****************************************************************************/ #if defined(CONFIG_ARCH_CHIP_ESP32S3) -#define CONFIG_GPIO(pin, attr) esp32s3_configgpio(pin, attr) -#define GPIO_MATRIX_OUT(pin, idx, inv, en_inv) esp32s3_gpio_matrix_out(pin, \ +#define CONFIG_GPIO(pin, attr) esp_configgpio(pin, attr) +#define GPIO_MATRIX_OUT(pin, idx, inv, en_inv) esp_gpio_matrix_out(pin, \ idx, inv, en_inv) #elif defined(CONFIG_ARCH_CHIP_ESP32S2) -#define CONFIG_GPIO(pin, attr) esp32s2_configgpio(pin, attr) -#define GPIO_MATRIX_OUT(pin, idx, inv, en_inv) esp32s2_gpio_matrix_out(pin, \ +#define CONFIG_GPIO(pin, attr) esp_configgpio(pin, attr) +#define GPIO_MATRIX_OUT(pin, idx, inv, en_inv) esp_gpio_matrix_out(pin, \ idx, inv, en_inv) -#else -#define CONFIG_GPIO(pin, attr) esp32_configgpio(pin, attr) -#define GPIO_MATRIX_OUT(pin, idx, inv, en_inv) esp32_gpio_matrix_out(pin, \ +#else#if defined(CONFIG_ARCH_CHIP_ESP32) +#endif +#define CONFIG_GPIO(pin, attr) esp_configgpio(pin, attr) +#define GPIO_MATRIX_OUT(pin, idx, inv, en_inv) esp_gpio_matrix_out(pin, \ idx, inv, en_inv) #endif @@ -231,11 +232,10 @@ struct spi_dev_s *esp_spi_bitbang_init(void) GPIO_WRITE(CONFIG_ESPRESSIF_SPI_BITBANG_MOSIPIN, true); GPIO_WRITE(CONFIG_ESPRESSIF_SPI_BITBANG_CLKPIN, true); -#if CONFIG_ESPRESSIF_SPI_SWCS CONFIG_GPIO(CONFIG_ESPRESSIF_SPI_BITBANG_CSPIN, OUTPUT_FUNCTION_1); GPIO_MATRIX_OUT(CONFIG_ESPRESSIF_SPI_BITBANG_CSPIN, SIG_GPIO_OUT_IDX, 0, 0); -#endif + CONFIG_GPIO(CONFIG_ESPRESSIF_SPI_BITBANG_MOSIPIN, OUTPUT_FUNCTION_1); GPIO_MATRIX_OUT(CONFIG_ESPRESSIF_SPI_BITBANG_MOSIPIN, SIG_GPIO_OUT_IDX, 0, 0); diff --git a/arch/xtensa/src/common/espressif/esp_spi_bitbang.h b/arch/xtensa/src/common/espressif/esp_spi_bitbang.h index b01a12bc75956..7a84c11fedb76 100644 --- a/arch/xtensa/src/common/espressif/esp_spi_bitbang.h +++ b/arch/xtensa/src/common/espressif/esp_spi_bitbang.h @@ -47,11 +47,11 @@ extern "C" #include #include #if defined(CONFIG_ARCH_CHIP_ESP32S3) -#include "esp32s3_gpio.h" +#include "esp_gpio.h" #elif defined(CONFIG_ARCH_CHIP_ESP32S2) -#include "esp32s2_gpio.h" +#include "espressif/esp_gpio.h" #else -#include "esp32_gpio.h" +#include "esp_gpio.h" #endif /**************************************************************************** @@ -59,13 +59,13 @@ extern "C" ****************************************************************************/ #if defined(CONFIG_ARCH_CHIP_ESP32S3) -#define GPIO_WRITE(pin, value) esp32s3_gpiowrite(pin, value) -#define GPIO_READ(pin) esp32s3_gpioread(pin) +#define GPIO_WRITE(pin, value) esp_gpiowrite(pin, value) +#define GPIO_READ(pin) esp_gpioread(pin) #elif defined(CONFIG_ARCH_CHIP_ESP32S2) -#define GPIO_WRITE(pin, value) esp32s2_gpiowrite(pin, value) -#define GPIO_READ(pin) esp32s2_gpioread(pin) +#define GPIO_WRITE(pin, value) esp_gpiowrite(pin, value) +#define GPIO_READ(pin) esp_gpioread(pin) #else -#define GPIO_WRITE(pin, value) esp32_gpiowrite(pin, value) +#define GPIO_WRITE(pin, value) esp_gpiowrite(pin, value) #define GPIO_READ(pin) esp3_gpioread(pin) #endif diff --git a/arch/xtensa/src/common/espressif/esp_spiflash.c b/arch/xtensa/src/common/espressif/esp_spiflash.c index 3eee233913548..1970aad988325 100644 --- a/arch/xtensa/src/common/espressif/esp_spiflash.c +++ b/arch/xtensa/src/common/espressif/esp_spiflash.c @@ -45,11 +45,11 @@ #include "bootloader_flash_priv.h" #if defined(CONFIG_ARCH_CHIP_ESP32) -# include "esp32_irq.h" +# include "esp_irq.h" #elif defined(CONFIG_ARCH_CHIP_ESP32S2) -# include "esp32s2_irq.h" +# include "espressif/esp_irq.h" #else -# include "esp32s3_irq.h" +# include "esp_irq.h" #endif /**************************************************************************** @@ -64,17 +64,6 @@ # error "SPIRAM requires legacy SPI Flash driver" #endif -#if defined(CONFIG_ARCH_CHIP_ESP32) -# define esp_intr_noniram_enable esp32_irq_noniram_enable -# define esp_intr_noniram_disable esp32_irq_noniram_disable -#elif defined(CONFIG_ARCH_CHIP_ESP32S2) -# define esp_intr_noniram_disable esp32s2_irq_noniram_disable -# define esp_intr_noniram_enable esp32s2_irq_noniram_enable -#else -# define esp_intr_noniram_enable esp32s3_irq_noniram_enable -# define esp_intr_noniram_disable esp32s3_irq_noniram_disable -#endif - #ifdef CONFIG_ESPRESSIF_EFUSE_VIRTUAL_KEEP_IN_FLASH #define ENCRYPTION_IS_VIRTUAL (!efuse_hal_flash_encryption_enabled()) #else @@ -493,126 +482,6 @@ static bool aligned_flash_erase(size_t addr, size_t size) } #endif /* CONFIG_ESP_FLASH_ENCRYPTION */ -/**************************************************************************** - * Name: spi_flash_op_block_task - * - * Description: - * Disable the non-IRAM interrupts on the other core (the one that isn't - * handling the SPI flash operation) and notify that the SPI flash - * operation can start. Wait on a busy loop until it's finished and then - * re-enable the non-IRAM interrupts. - * - * Input Parameters: - * argc - Not used. - * argv - Not used. - * - * Returned Value: - * Zero (OK) is returned on success. A negated errno value is returned to - * indicate the nature of any failure. - * - ****************************************************************************/ - -#ifdef CONFIG_SMP -static int spi_flash_op_block_task(int argc, char *argv[]) -{ - struct tcb_s *tcb = this_task(); - int cpu = this_cpu(); - - for (; ; ) - { - DEBUGASSERT((1 << cpu) & tcb->affinity); - /* Wait for a request from the other CPU to suspend interrupts - * and cache on this CPU. - */ - - nxsem_wait(&g_cpu_prepare_sem[cpu]); - - sched_lock(); - esp_intr_noniram_disable(); - - s_flash_op_complete = false; - s_flash_op_can_start = true; - while (!s_flash_op_complete) - { - /* Wait for a request to restore interrupts and cache on this CPU. - * This indicates SPI Flash operation is complete. - */ - } - - esp_intr_noniram_enable(); - sched_unlock(); - } - - return OK; -} - -/**************************************************************************** - * Name: spiflash_init_spi_flash_op_block_task - * - * Description: - * Starts a kernel thread that waits for a semaphore indicating that a SPI - * flash operation is going to take place in the other CPU. - * - * Input Parameters: - * cpu - The CPU core that will run the created task to wait on a busy - * loop while the SPI flash operation finishes - * - * Returned Value: - * 0 (OK) on success; A negated errno value on failure. - * - ****************************************************************************/ - -static int spiflash_init_spi_flash_op_block_task(int cpu) -{ - FAR struct tcb_s *tcb; - int ret; - char *argv[2]; - char arg1[32]; - cpu_set_t cpuset; - - snprintf(arg1, sizeof(arg1), "%p", &cpu); - argv[0] = arg1; - argv[1] = NULL; - - /* Allocate a TCB for the new task. */ - - tcb = kmm_zalloc(sizeof(struct tcb_s)); - if (!tcb) - { - serr("ERROR: Failed to allocate TCB\n"); - return -ENOMEM; - } - - /* Setup the task type */ - - tcb->flags = TCB_FLAG_TTYPE_KERNEL | TCB_FLAG_FREE_TCB; - - /* Initialize the task */ - - ret = nxtask_init(tcb, "spiflash_op", - SCHED_PRIORITY_MAX, - NULL, SPIFLASH_OP_TASK_STACKSIZE, - spi_flash_op_block_task, argv, environ, NULL); - if (ret < OK) - { - kmm_free(tcb); - return ret; - } - - /* Set the affinity */ - - CPU_ZERO(&cpuset); - CPU_SET(cpu, &cpuset); - tcb->affinity = cpuset; - - /* Activate the task */ - - nxtask_activate(tcb); - - return ret; -} -#endif - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -770,44 +639,3 @@ int esp_spiflash_erase(uint32_t address, uint32_t length) return ret; } - -/**************************************************************************** - * Name: esp_spiflash_init - * - * Description: - * Initialize ESP SPI flash driver. - * SPI Flash actual chip initialization initial is done by esp_start on - * STARTUP_FN hook. - * - * Input Parameters: - * None. - * - * Returned Value: - * OK if success or a negative value if fail. - * - ****************************************************************************/ - -int esp_spiflash_init(void) -{ - int ret = OK; - int cpu; - -#ifdef CONFIG_SMP - sched_lock(); - - for (cpu = 0; cpu < CONFIG_SMP_NCPUS; cpu++) - { - ret = spiflash_init_spi_flash_op_block_task(cpu); - if (ret != OK) - { - return ret; - } - } - - sched_unlock(); -#else - UNUSED(cpu); -#endif - - return ret; -} diff --git a/arch/xtensa/src/common/espressif/esp_spiflash.h b/arch/xtensa/src/common/espressif/esp_spiflash.h index d4f95f9f2d8ad..b8222e39429a6 100644 --- a/arch/xtensa/src/common/espressif/esp_spiflash.h +++ b/arch/xtensa/src/common/espressif/esp_spiflash.h @@ -106,22 +106,6 @@ int esp_spiflash_erase(uint32_t address, uint32_t length); int esp_spiflash_write(uint32_t address, const void *buffer, uint32_t length); -/**************************************************************************** - * Name: esp_spiflash_init - * - * Description: - * Initialize ESP SPI flash driver. - * - * Input Parameters: - * None. - * - * Returned Value: - * OK if success or a negative value if fail. - * - ****************************************************************************/ - -int esp_spiflash_init(void); - #ifdef __cplusplus } #endif diff --git a/arch/xtensa/src/common/espressif/esp_temperature_sensor.c b/arch/xtensa/src/common/espressif/esp_temperature_sensor.c index a3a72257b0884..a1091198849f0 100644 --- a/arch/xtensa/src/common/espressif/esp_temperature_sensor.c +++ b/arch/xtensa/src/common/espressif/esp_temperature_sensor.c @@ -61,8 +61,7 @@ #include "hal/regi2c_ctrl.h" #include "hal/temperature_sensor_ll.h" #include "hal/temperature_sensor_types.h" -#include "soc/temperature_sensor_periph.h" -#include "esp_efuse_rtc_calib.h" +#include "hal/temperature_sensor_periph.h" #include "hal/adc_ll.h" /**************************************************************************** @@ -105,7 +104,6 @@ struct esp_temp_priv_s const temperature_sensor_attribute_t *tsens_attribute; /* Attribute struct of the common layer */ struct esp_temp_sensor_config_t cfg; /* Configuration struct of the common layer */ temperature_sensor_clk_src_t clk_src; /* Clock source to use */ - int module; /* Peripheral module */ int refs; /* Reference count */ mutex_t lock; /* Mutual exclusion mutex */ #ifdef CONFIG_ESPRESSIF_TEMP_UORB @@ -197,7 +195,6 @@ struct esp_temp_priv_s esp_temp_priv = 0 }, .clk_src = TEMPERATURE_SENSOR_CLK_SRC_DEFAULT, - .module = PERIPH_TEMPSENSOR_MODULE, .refs = 0, .lock = NXMUTEX_INITIALIZER, #ifdef CONFIG_ESPRESSIF_TEMP_UORB @@ -321,11 +318,10 @@ static int temperature_sensor_choose_best_range(struct esp_temp_priv_s *priv) static int temperature_sensor_read_delta_t(void) { - if (esp_efuse_rtc_calib_get_tsens_val(&g_delta_t) != OK) + g_delta_t = temperature_sensor_ll_load_calib_param(); + if (g_delta_t == 0) { - snwarn("Calibration failed"); - g_delta_t = 0; - return ERROR; + snwarn("No calibration param in eFuse"); } sninfo("delta_T = %f", g_delta_t); diff --git a/arch/xtensa/src/common/espressif/esp_timer_adapter.c b/arch/xtensa/src/common/espressif/esp_timer_adapter.c new file mode 100644 index 0000000000000..221d818b45eb9 --- /dev/null +++ b/arch/xtensa/src/common/espressif/esp_timer_adapter.c @@ -0,0 +1,492 @@ +/**************************************************************************** + * arch/xtensa/src/common/espressif/esp_timer_adapter.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "esp_timer.h" +#include "esp_timer_adapter.h" + +#include "esp_private/esp_timer_private.h" +#include "esp_timer_impl.h" + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* HR timer data structure wrapping HAL esp_timer (internal definition) */ + +struct esp_hr_timer_s +{ + esp_timer_handle_t hal_timer; /* HAL timer handle */ + uint64_t timeout; /* Timeout value */ + uint64_t alarm; /* Timeout period */ + void (*callback)(void *arg); /* Callback function */ + void *arg; /* Private data */ + uint16_t flags; /* Supported features */ + enum esp_hr_timer_state_e state; /* Timer state */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static void esp_hr_timer_callback_wrapper(void *arg); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static spinlock_t g_hr_timer_lock = SP_UNLOCKED; +static bool g_hr_timer_initialized = false; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp_hr_timer_callback_wrapper + * + * Description: + * Adapter callback used by esp_timer to dispatch to the upper-layer timer + * callback and update the timer state. + * + * Input Parameters: + * arg - Pointer to struct esp_hr_timer_s. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void esp_hr_timer_callback_wrapper(void *arg) +{ + struct esp_hr_timer_s *timer = (struct esp_hr_timer_s *)arg; + + if (timer && timer->callback) + { + timer->state = HR_TIMER_TIMEOUT; + timer->callback(timer->arg); + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: esp_hr_timer_create + * + * Description: + * Create a high-resolution timer instance and initialize it from the + * provided arguments. + * + * Input Parameters: + * args - Timer creation arguments. + * timer_handle - Location where the created timer handle is returned. + * + * Returned Value: + * OK on success; a negated errno value on failure. + * + ****************************************************************************/ + +int esp_hr_timer_create(const struct esp_hr_timer_args_s *args, + struct esp_hr_timer_s **timer_handle) +{ + struct esp_hr_timer_s *timer; + esp_timer_create_args_t hal_args; + esp_err_t ret; + + if (args == NULL || timer_handle == NULL || args->callback == NULL) + { + return -EINVAL; + } + + timer = kmm_zalloc(sizeof(struct esp_hr_timer_s)); + if (timer == NULL) + { + return -ENOMEM; + } + + timer->callback = args->callback; + timer->arg = args->arg; + timer->flags = HR_TIMER_NOFLAGS; + timer->state = HR_TIMER_IDLE; + + hal_args.callback = esp_hr_timer_callback_wrapper; + hal_args.arg = timer; + hal_args.dispatch_method = ESP_TIMER_TASK; + hal_args.name = args->name ? args->name : "nuttx_hr"; + hal_args.skip_unhandled_events = args->skip_unhandled_events; + + ret = esp_timer_create(&hal_args, &timer->hal_timer); + if (ret != ESP_OK) + { + kmm_free(timer); + return -EINVAL; + } + + *timer_handle = timer; + return OK; +} + +/**************************************************************************** + * Name: esp_hr_timer_start + * + * Description: + * Start a high-resolution timer in one-shot or periodic mode. + * + * Input Parameters: + * timer - Timer instance to start. + * timeout - Timeout period in microseconds. + * repeat - True for periodic mode, false for one-shot mode. + * + * Returned Value: + * OK on success; ERROR on failure. + * + ****************************************************************************/ + +int esp_hr_timer_start(struct esp_hr_timer_s *timer, + uint64_t timeout, + bool repeat) +{ + esp_err_t ret; + + if (timer == NULL) + { + return ERROR; + } + + timer->timeout = timeout; + + if (repeat) + { + timer->flags |= HR_TIMER_REPEAT; + ret = esp_timer_start_periodic(timer->hal_timer, timeout); + } + else + { + timer->flags &= ~HR_TIMER_REPEAT; + ret = esp_timer_start_once(timer->hal_timer, timeout); + } + + if (ret == ESP_OK) + { + timer->state = HR_TIMER_READY; + return OK; + } + + return ERROR; +} + +/**************************************************************************** + * Name: esp_hr_timer_start_once + * + * Description: + * Start a high-resolution timer in one-shot mode. + * + * Input Parameters: + * timer - Timer instance to start. + * timeout - One-shot timeout in microseconds. + * + * Returned Value: + * OK on success; ERROR on failure. + * + ****************************************************************************/ + +int esp_hr_timer_start_once(struct esp_hr_timer_s *timer, uint64_t timeout) +{ + return esp_hr_timer_start(timer, timeout, false); +} + +/**************************************************************************** + * Name: esp_hr_timer_start_periodic + * + * Description: + * Start a high-resolution timer in periodic mode. + * + * Input Parameters: + * timer - Timer instance to start. + * timeout - Period interval in microseconds. + * + * Returned Value: + * OK on success; ERROR on failure. + * + ****************************************************************************/ + +int esp_hr_timer_start_periodic(struct esp_hr_timer_s *timer, + uint64_t timeout) +{ + return esp_hr_timer_start(timer, timeout, true); +} + +/**************************************************************************** + * Name: esp_hr_timer_stop + * + * Description: + * Stop a running high-resolution timer. + * + * Input Parameters: + * timer - Timer instance to stop. + * + * Returned Value: + * OK on success; ERROR on failure. + * + ****************************************************************************/ + +int esp_hr_timer_stop(struct esp_hr_timer_s *timer) +{ + esp_err_t ret; + + if (timer == NULL) + { + return ERROR; + } + + ret = esp_timer_stop(timer->hal_timer); + if (ret == ESP_OK) + { + timer->state = HR_TIMER_IDLE; + return OK; + } + + return ERROR; +} + +/**************************************************************************** + * Name: esp_hr_timer_stop_nolock + * + * Description: + * Stop a running high-resolution timer without taking any adapter lock. + * + * Input Parameters: + * timer - Timer instance to stop. + * + * Returned Value: + * OK on success; ERROR on failure. + * + ****************************************************************************/ + +int esp_hr_timer_stop_nolock(struct esp_hr_timer_s *timer) +{ + /* esp_timer already handles its own locking */ + + return esp_hr_timer_stop(timer); +} + +/**************************************************************************** + * Name: esp_hr_timer_delete + * + * Description: + * Delete a timer instance and release associated resources. + * + * Input Parameters: + * timer - Timer instance to delete. + * + * Returned Value: + * OK on success; ERROR on failure. + * + ****************************************************************************/ + +int esp_hr_timer_delete(struct esp_hr_timer_s *timer) +{ + esp_err_t ret; + + if (timer == NULL) + { + return ERROR; + } + + timer->state = HR_TIMER_DELETE; + + ret = esp_timer_delete(timer->hal_timer); + if (ret == ESP_OK) + { + kmm_free(timer); + return OK; + } + + return ERROR; +} + +/**************************************************************************** + * Name: esp_hr_timer_time_us + * + * Description: + * Return the current high-resolution timer time in microseconds. + * + * Input Parameters: + * None. + * + * Returned Value: + * Current timer time in microseconds. + * + ****************************************************************************/ + +uint64_t esp_hr_timer_time_us(void) +{ + return esp_timer_impl_get_time(); +} + +/**************************************************************************** + * Name: esp_hr_timer_get_alarm + * + * Description: + * Return the timestamp of the next scheduled timer alarm. + * + * Input Parameters: + * None. + * + * Returned Value: + * Absolute time in microseconds for the next alarm. + * + ****************************************************************************/ + +uint64_t esp_hr_timer_get_alarm(void) +{ + return esp_timer_get_next_alarm(); +} + +/**************************************************************************** + * Name: esp_hr_timer_calibration + * + * Description: + * Apply a timer calibration adjustment. + * The HAL esp_timer backend does not support calibration, so this is a + * no-op. + * + * Input Parameters: + * time_us - Calibration adjustment in microseconds. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp_hr_timer_calibration(uint64_t time_us) +{ + /* HAL esp_timer doesn't support calibration */ +} + +/**************************************************************************** + * Name: esp_hr_timer_set + * + * Description: + * Set the high-resolution timer counter to a specific timestamp. + * + * Input Parameters: + * new_us - New timer value in microseconds. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp_hr_timer_set(uint64_t new_us) +{ + /* Use HAL function to set timer */ + + esp_timer_private_set(new_us); +} + +/**************************************************************************** + * Name: esp_hr_timer_lock + * + * Description: + * Acquire the adapter lock used to serialize timer operations. + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp_hr_timer_lock(void) +{ + spin_lock(&g_hr_timer_lock); +} + +/**************************************************************************** + * Name: esp_hr_timer_unlock + * + * Description: + * Release the adapter lock used to serialize timer operations. + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp_hr_timer_unlock(void) +{ + spin_unlock(&g_hr_timer_lock); +} + +/**************************************************************************** + * Name: esp_hr_timer_init + * + * Description: + * Initialize the timer adapter and the underlying ESP timer subsystem. + * + * Input Parameters: + * None. + * + * Returned Value: + * OK on success; ERROR on failure. + * + ****************************************************************************/ + +int esp_hr_timer_init(void) +{ + esp_err_t ret; + + if (g_hr_timer_initialized) + { + return OK; + } + + /* Initialize the timer subsystem */ + + ret = esp_timer_init(); + if (ret == ESP_OK) + { + g_hr_timer_initialized = true; + return OK; + } + + return ERROR; +} diff --git a/arch/xtensa/src/common/espressif/esp_timer_adapter.h b/arch/xtensa/src/common/espressif/esp_timer_adapter.h new file mode 100644 index 0000000000000..abaa15c1254ec --- /dev/null +++ b/arch/xtensa/src/common/espressif/esp_timer_adapter.h @@ -0,0 +1,324 @@ +/**************************************************************************** + * arch/xtensa/src/common/espressif/esp_timer_adapter.h + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_TIMER_ADAPTER_H +#define __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_TIMER_ADAPTER_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define HR_TIMER_NOFLAGS (0) /* Timer supports no feature */ +#define HR_TIMER_REPEAT (1 << 0) /* Timer supports repeat mode */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* HR Timer state (simplified for adapter) */ + +enum esp_hr_timer_state_e +{ + HR_TIMER_IDLE, /* Timer is not counting */ + HR_TIMER_READY, /* Timer is counting */ + HR_TIMER_TIMEOUT, /* Timer timed out */ + HR_TIMER_DELETE /* Timer is to be deleted */ +}; + +/* Forward declaration - opaque type */ + +struct esp_hr_timer_s; + +/* HR Timer creation arguments data structure */ + +struct esp_hr_timer_args_s +{ + void (*callback)(void *arg); /* Callback function */ + void *arg; /* Private data */ + const char *name; /* Timer name */ + bool skip_unhandled_events; /* Skip unhandled events for periodic timers */ +}; + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: esp_hr_timer_create + * + * Description: + * Create a high-resolution timer instance and initialize it from the + * provided arguments. + * + * Input Parameters: + * args - Timer creation arguments. + * timer_handle - Location where the created timer handle is returned. + * + * Returned Value: + * OK on success; a negated errno value on failure. + * + ****************************************************************************/ + +int esp_hr_timer_create(const struct esp_hr_timer_args_s *args, + struct esp_hr_timer_s **timer_handle); + +/**************************************************************************** + * Name: esp_hr_timer_start + * + * Description: + * Start a high-resolution timer in one-shot or periodic mode. + * + * Input Parameters: + * timer - Timer instance to start. + * timeout - Timeout period in microseconds. + * repeat - True for periodic mode, false for one-shot mode. + * + * Returned Value: + * OK on success; ERROR on failure. + * + ****************************************************************************/ + +int esp_hr_timer_start(struct esp_hr_timer_s *timer, + uint64_t timeout, + bool repeat); + +/**************************************************************************** + * Name: esp_hr_timer_start_once + * + * Description: + * Start a high-resolution timer in one-shot mode. + * + * Input Parameters: + * timer - Timer instance to start. + * timeout - One-shot timeout in microseconds. + * + * Returned Value: + * OK on success; ERROR on failure. + * + ****************************************************************************/ + +int esp_hr_timer_start_once(struct esp_hr_timer_s *timer, uint64_t timeout); + +/**************************************************************************** + * Name: esp_hr_timer_start_periodic + * + * Description: + * Start a high-resolution timer in periodic mode. + * + * Input Parameters: + * timer - Timer instance to start. + * timeout - Period interval in microseconds. + * + * Returned Value: + * OK on success; ERROR on failure. + * + ****************************************************************************/ + +int esp_hr_timer_start_periodic(struct esp_hr_timer_s *timer, + uint64_t timeout); + +/**************************************************************************** + * Name: esp_hr_timer_stop + * + * Description: + * Stop a running high-resolution timer. + * + * Input Parameters: + * timer - Timer instance to stop. + * + * Returned Value: + * OK on success; ERROR on failure. + * + ****************************************************************************/ + +int esp_hr_timer_stop(struct esp_hr_timer_s *timer); + +/**************************************************************************** + * Name: esp_hr_timer_stop_nolock + * + * Description: + * Stop a running high-resolution timer without taking any adapter lock. + * + * Input Parameters: + * timer - Timer instance to stop. + * + * Returned Value: + * OK on success; ERROR on failure. + * + ****************************************************************************/ + +int esp_hr_timer_stop_nolock(struct esp_hr_timer_s *timer); + +/**************************************************************************** + * Name: esp_hr_timer_delete + * + * Description: + * Delete a timer instance and release associated resources. + * + * Input Parameters: + * timer - Timer instance to delete. + * + * Returned Value: + * OK on success; ERROR on failure. + * + ****************************************************************************/ + +int esp_hr_timer_delete(struct esp_hr_timer_s *timer); + +/**************************************************************************** + * Name: esp_hr_timer_time_us + * + * Description: + * Return the current high-resolution timer time in microseconds. + * + * Input Parameters: + * None. + * + * Returned Value: + * Current timer time in microseconds. + * + ****************************************************************************/ + +uint64_t esp_hr_timer_time_us(void); + +/**************************************************************************** + * Name: esp_hr_timer_get_alarm + * + * Description: + * Return the timestamp of the next scheduled timer alarm. + * + * Input Parameters: + * None. + * + * Returned Value: + * Absolute time in microseconds for the next alarm. + * + ****************************************************************************/ + +uint64_t esp_hr_timer_get_alarm(void); + +/**************************************************************************** + * Name: esp_hr_timer_calibration + * + * Description: + * Apply a timer calibration adjustment. + * The ESP timer backend does not support calibration, so this operation + * is a no-op. + * + * Input Parameters: + * time_us - Calibration adjustment in microseconds. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp_hr_timer_calibration(uint64_t time_us); + +/**************************************************************************** + * Name: esp_hr_timer_set + * + * Description: + * Set the high-resolution timer counter to a specific timestamp. + * + * Input Parameters: + * new_us - New timer value in microseconds. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp_hr_timer_set(uint64_t new_us); + +/**************************************************************************** + * Name: esp_hr_timer_lock + * + * Description: + * Acquire the adapter lock used to serialize timer operations. + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp_hr_timer_lock(void); + +/**************************************************************************** + * Name: esp_hr_timer_unlock + * + * Description: + * Release the adapter lock used to serialize timer operations. + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp_hr_timer_unlock(void); + +/**************************************************************************** + * Name: esp_hr_timer_init + * + * Description: + * Initialize the timer adapter and the underlying ESP timer subsystem. + * + * Input Parameters: + * None. + * + * Returned Value: + * OK on success; ERROR on failure. + * + ****************************************************************************/ + +int esp_hr_timer_init(void); + +#ifdef __cplusplus +} +#endif +#undef EXTERN + +#endif /* __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_TIMER_ADAPTER_H */ diff --git a/arch/xtensa/src/common/espressif/esp_ulp.mk b/arch/xtensa/src/common/espressif/esp_ulp.mk index 401c95574cdde..98ed52eff9d6c 100644 --- a/arch/xtensa/src/common/espressif/esp_ulp.mk +++ b/arch/xtensa/src/common/espressif/esp_ulp.mk @@ -36,6 +36,14 @@ ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO) ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)ulp ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_common$(DELIM)include +ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ana_conv$(DELIM)include +ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ana_conv$(DELIM)$(CHIP_SERIES)$(DELIM)include +ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpio$(DELIM)include +ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpio$(DELIM)$(CHIP_SERIES)$(DELIM)include +ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_i2c$(DELIM)include +ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_i2c$(DELIM)$(CHIP_SERIES)$(DELIM)include +ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_touch_sens$(DELIM)include +ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_touch_sens$(DELIM)$(CHIP_SERIES)$(DELIM)include ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)include ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)private_include @@ -68,7 +76,6 @@ ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)c ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)ulp$(DELIM)ulp_riscv$(DELIM)ulp_core$(DELIM)include ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)include ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)$(CHIP_SERIES)$(DELIM)include -ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)esp_driver_gpio$(DELIM)include ULP_INCLUDES += $(INCDIR_PREFIX)$(CHIP)$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)esp_driver_uart$(DELIM)include # Linker scripts diff --git a/arch/xtensa/src/common/espressif/esp_wireless.c b/arch/xtensa/src/common/espressif/esp_wireless.c index 4131893546eb2..a9b6425668158 100644 --- a/arch/xtensa/src/common/espressif/esp_wireless.c +++ b/arch/xtensa/src/common/espressif/esp_wireless.c @@ -38,25 +38,24 @@ #include "hardware/esp32_dport.h" #include "hardware/esp32_emac.h" #include "hardware/esp32_soc.h" -#include "esp32_irq.h" +#include "esp_irq.h" #include "esp32_partition.h" #elif CONFIG_ARCH_CHIP_ESP32S2 -#include "hardware/esp32s2_efuse.h" -#include "hardware/esp32s2_rtccntl.h" +#include "soc/efuse_reg.h" #include "hardware/esp32s2_soc.h" #include "hardware/esp32s2_syscon.h" #include "hardware/esp32s2_system.h" -#include "esp32s2_irq.h" +#include "espressif/esp_irq.h" /* #include "esp32s2_partition.h" */ #elif CONFIG_ARCH_CHIP_ESP32S3 -#include "hardware/esp32s3_efuse.h" -#include "hardware/esp32s3_rtccntl.h" +#include "soc/efuse_reg.h" #include "hardware/esp32s3_soc.h" #include "hardware/esp32s3_syscon.h" #include "hardware/esp32s3_system.h" -#include "esp32s3_irq.h" +#include "esp_irq.h" #include "esp32s3_partition.h" #endif +#include "esp_hr_timer.h" #include "esp_private/phy.h" #ifdef CONFIG_ESPRESSIF_WIFI @@ -85,26 +84,16 @@ # define SWI_PERIPH ESP32_PERIPH_CPU_CPU2 # define esp_partition_read esp32_partition_read # define esp_partition_write esp32_partition_write -# define esp_setup_irq esp32_setup_irq -# define esp_teardown_irq esp32_teardown_irq #elif CONFIG_ARCH_CHIP_ESP32S2 # define SWI_IRQ ESP32S2_IRQ_INT_FROM_CPU2 # define SWI_PERIPH ESP32S2_PERIPH_INT_FROM_CPU2 # define esp_partition_read esp32s2_partition_read # define esp_partition_write esp32s2_partition_write -# define esp_setup_irq esp32s2_setup_irq -# define esp_teardown_irq esp32s2_teardown_irq #elif CONFIG_ARCH_CHIP_ESP32S3 # define SWI_IRQ ESP32S3_IRQ_INT_FROM_CPU2 # define SWI_PERIPH ESP32S3_PERIPH_INT_FROM_CPU2 # define esp_partition_read esp32s3_partition_read # define esp_partition_write esp32s3_partition_write -# define rt_timer_create esp32s3_rt_timer_create -# define rt_timer_start esp32s3_rt_timer_start -# define rt_timer_stop esp32s3_rt_timer_stop -# define rt_timer_delete esp32s3_rt_timer_delete -# define esp_setup_irq esp32s3_setup_irq -# define esp_teardown_irq esp32s3_teardown_irq #endif /**************************************************************************** @@ -302,13 +291,13 @@ static inline void phy_digital_regs_load(void) * Wireless software interrupt callback function. * * Parameters: - * cpuint - CPU interrupt index - * context - Context data from the ISR - * arg - NULL + * irq - The IRQ number; + * context - The interrupt context; + * arg - Parameter for the interrupt handler * * Returned Value: - * Zero (OK) is returned on success. A negated errno value is returned on - * failure. + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. * ****************************************************************************/ @@ -941,137 +930,6 @@ int esp_phy_update_country_info(const char *country) return OK; } -/**************************************************************************** - * Name: esp_timer_create - * - * Description: - * Create timer with given arguments - * - * Input Parameters: - * create_args - Timer arguments data pointer - * out_handle - Timer handle pointer - * - * Returned Value: - * 0 if success or -1 if fail - * - ****************************************************************************/ - -int esp_timer_create(const esp_timer_create_args_t *create_args, - esp_timer_handle_t *out_handle) -{ - int ret; - struct rt_timer_args_s rt_timer_args; - struct rt_timer_s *rt_timer; - - rt_timer_args.arg = create_args->arg; - rt_timer_args.callback = create_args->callback; - - ret = rt_timer_create(&rt_timer_args, &rt_timer); - if (ret != 0) - { - wlerr("Failed to create rt_timer error=%d\n", ret); - return ret; - } - - *out_handle = (esp_timer_handle_t)rt_timer; - - return 0; -} - -/**************************************************************************** - * Name: esp_timer_start_once - * - * Description: - * Start timer with one shot mode - * - * Input Parameters: - * timer - Timer handle pointer - * timeout_us - Timeout value by micro second - * - * Returned Value: - * 0 if success or -1 if fail - * - ****************************************************************************/ - -int esp_timer_start_once(esp_timer_handle_t timer, uint64_t timeout_us) -{ - struct rt_timer_s *rt_timer = (struct rt_timer_s *)timer; - - rt_timer_start(rt_timer, timeout_us, false); - - return 0; -} - -/**************************************************************************** - * Name: esp_timer_start_periodic - * - * Description: - * Start timer with periodic mode - * - * Input Parameters: - * timer - Timer handle pointer - * period - Timeout value by micro second - * - * Returned Value: - * 0 if success or -1 if fail - * - ****************************************************************************/ - -int esp_timer_start_periodic(esp_timer_handle_t timer, uint64_t period) -{ - struct rt_timer_s *rt_timer = (struct rt_timer_s *)timer; - - rt_timer_start(rt_timer, period, true); - - return 0; -} - -/**************************************************************************** - * Name: esp_timer_stop - * - * Description: - * Stop timer - * - * Input Parameters: - * timer - Timer handle pointer - * - * Returned Value: - * 0 if success or -1 if fail - * - ****************************************************************************/ - -int esp_timer_stop(esp_timer_handle_t timer) -{ - struct rt_timer_s *rt_timer = (struct rt_timer_s *)timer; - - rt_timer_stop(rt_timer); - - return 0; -} - -/**************************************************************************** - * Name: esp_timer_delete - * - * Description: - * Delete timer and free resource - * - * Input Parameters: - * timer - Timer handle pointer - * - * Returned Value: - * 0 if success or -1 if fail - * - ****************************************************************************/ - -int esp_timer_delete(esp_timer_handle_t timer) -{ - struct rt_timer_s *rt_timer = (struct rt_timer_s *)timer; - - rt_timer_delete(rt_timer); - - return 0; -} - /**************************************************************************** * Name: esp_init_semcache * @@ -1274,11 +1132,24 @@ int esp_wireless_init(void) } #ifdef CONFIG_ARCH_CHIP_ESP32 - priv->cpuint = esp_setup_irq(0, SWI_PERIPH, 1, ESP32_CPUINT_LEVEL); + priv->cpuint = esp_setup_irq(SWI_PERIPH, + 1, + ESP_IRQ_TRIGGER_LEVEL, + esp_swi_irq, + NULL); #elif CONFIG_ARCH_CHIP_ESP32S2 - priv->cpuint = esp_setup_irq(SWI_PERIPH, ESP32S2_INT_PRIO_DEF, 0); + priv->cpuint = esp_setup_irq(SWI_PERIPH, + ESP32S2_INT_PRIO_DEF, + ESP_IRQ_TRIGGER_LEVEL, + esp_swi_irq, + NULL); #elif CONFIG_ARCH_CHIP_ESP32S3 - priv->cpuint = esp_setup_irq(0, SWI_PERIPH, ESP32S3_INT_PRIO_DEF, 0); + ASSERT(this_cpu() == 0); + priv->cpuint = esp_setup_irq(SWI_PERIPH, + ESP32S3_INT_PRIO_DEF, + ESP_IRQ_TRIGGER_LEVEL, + esp_swi_irq, + NULL); #endif if (priv->cpuint < 0) { @@ -1291,22 +1162,6 @@ int esp_wireless_init(void) return ret; } - ret = irq_attach(SWI_IRQ, esp_swi_irq, NULL); - if (ret < 0) - { -#ifdef CONFIG_ARCH_CHIP_ESP32 - esp_teardown_irq(0, SWI_PERIPH, priv->cpuint); -#elif CONFIG_ARCH_CHIP_ESP32S2 - esp_teardown_irq(SWI_PERIPH, priv->cpuint); -#elif CONFIG_ARCH_CHIP_ESP32S3 - esp_teardown_irq(0, SWI_PERIPH, priv->cpuint); -#endif - leave_critical_section(flags); - wlerr("ERROR: Failed to attach IRQ ret=%d\n", ret); - - return ret; - } - list_initialize(&priv->sc_list); list_initialize(&priv->qc_list); #ifdef CONFIG_ARCH_CHIP_ESP32 @@ -1349,14 +1204,7 @@ int esp_wireless_deinit(void) if (priv->ref == 0) { up_disable_irq(SWI_IRQ); - irq_detach(SWI_IRQ); -#ifdef CONFIG_ARCH_CHIP_ESP32 - esp_teardown_irq(0, SWI_PERIPH, priv->cpuint); -#elif CONFIG_ARCH_CHIP_ESP32S2 esp_teardown_irq(SWI_PERIPH, priv->cpuint); -#elif CONFIG_ARCH_CHIP_ESP32S3 - esp_teardown_irq(0, SWI_PERIPH, priv->cpuint); -#endif } } diff --git a/arch/xtensa/src/common/espressif/esp_wireless.h b/arch/xtensa/src/common/espressif/esp_wireless.h index 0c0d8f76bc201..b812591347774 100644 --- a/arch/xtensa/src/common/espressif/esp_wireless.h +++ b/arch/xtensa/src/common/espressif/esp_wireless.h @@ -33,16 +33,8 @@ #include #include -#ifdef CONFIG_ARCH_CHIP_ESP32 -#include "xtensa_attr.h" -#include "esp32_rt_timer.h" -#elif CONFIG_ARCH_CHIP_ESP32S2 -#include "esp_attr.h" -#include "esp32s2_rt_timer.h" -#elif CONFIG_ARCH_CHIP_ESP32S3 #include "esp_attr.h" -#include "esp32s3_rt_timer.h" -#endif +#include "esp_hr_timer.h" #ifdef CONFIG_ESPRESSIF_WIFI # include "os.h" diff --git a/arch/xtensa/src/common/espressif/esp_wlan_netdev.c b/arch/xtensa/src/common/espressif/esp_wlan_netdev.c index 63f6c2714c896..2315af64fd9db 100644 --- a/arch/xtensa/src/common/espressif/esp_wlan_netdev.c +++ b/arch/xtensa/src/common/espressif/esp_wlan_netdev.c @@ -970,14 +970,14 @@ void IRAM_ATTR esp_wifi_tx_done_cb(uint8_t ifidx, bool txstatus) { #ifdef ESP_WLAN_HAS_STA - if (ifidx == ESP_IF_WIFI_STA) + if (ifidx == WIFI_IF_STA) { netdev_lower_txdone(&g_wlan_sta.dev); } #endif #ifdef ESP_WLAN_HAS_SOFTAP - if (ifidx == ESP_IF_WIFI_AP) + if (ifidx == WIFI_IF_AP) { netdev_lower_txdone(&g_wlan_softap.dev); } diff --git a/arch/xtensa/src/common/espressif/esp_ws2812.c b/arch/xtensa/src/common/espressif/esp_ws2812.c index ac15bf3dd673d..c6104e357c0a5 100644 --- a/arch/xtensa/src/common/espressif/esp_ws2812.c +++ b/arch/xtensa/src/common/espressif/esp_ws2812.c @@ -35,6 +35,8 @@ #include "hal/rmt_types.h" #include "soc/soc.h" +#include "esp_private/rmt.h" +#include "driver/rmt_common.h" #include "esp_rmt.h" @@ -67,6 +69,21 @@ struct rgbw_led_s }; }; +struct rmt_dev_lowerhalf_s +{ + /* The following block is part of the upper-half device struct */ + + const struct rmt_ops_s *ops; + struct circbuf_s *circbuf; + sem_t *recvsem; + int minor; + + /* The following is private to the ESP32 RMT driver */ + + rmt_channel_handle_t handle; + rmt_encoder_handle_t encoder; +}; + struct esp_ws2812_dev_s { struct rmt_dev_s *rmt; @@ -151,15 +168,19 @@ static uint32_t map_byte_to_words(struct esp_ws2812_dev_s *dev, uint16_t t0l; uint16_t t1h; uint16_t t1l; - uint32_t clock_period_ps; + uint32_t resolution_hz; uint32_t rmt_period_ps; + esp_err_t ret; + struct rmt_dev_lowerhalf_s *priv = (struct rmt_dev_lowerhalf_s *)dev->rmt; -#if SOC_RMT_CHANNEL_CLK_INDEPENDENT - clock_period_ps = 1000000000000 / g_rmt_source_clock_hz[dev->rmt->minor]; -#else - clock_period_ps = 1000000000000 / g_rmt_source_clock_hz; -#endif - rmt_period_ps = clock_period_ps / RMT_DEFAULT_CLK_DIV; + ret = rmt_get_channel_resolution(priv->handle, &resolution_hz); + if (ret != ESP_OK) + { + lederr("esp_ws2812 map_byte_to_words failed: %d\n", ret); + return 0; + } + + rmt_period_ps = 1000000000000 / resolution_hz; /* Calculate the RMT period to encode WS2812 frames */ diff --git a/arch/xtensa/src/common/espressif/esp_xtensa_intr.c b/arch/xtensa/src/common/espressif/esp_xtensa_intr.c new file mode 100644 index 0000000000000..22b5ba92358a1 --- /dev/null +++ b/arch/xtensa/src/common/espressif/esp_xtensa_intr.c @@ -0,0 +1,153 @@ +/**************************************************************************** + * arch/xtensa/src/common/espressif/esp_xtensa_intr.c + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include + +#include "xtensa.h" +#include "esp_rom_sys.h" +#include "esp_attr.h" +#include "platform/os.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef XCHAL_NUM_INTERRUPTS +# define XCHAL_NUM_INTERRUPTS 32 +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* Handler table entry structure - must match HAL's xt_handler_table_entry */ + +typedef struct xt_handler_table_entry +{ + void *handler; + void *arg; +} xt_handler_table_entry; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* Interrupt handler table - exported as _xt_interrupt_table for HAL + * compatibility. The HAL's xtensa_intr.c expects this to be defined + * externally (originally in assembly). + */ + +xt_handler_table_entry + _xt_interrupt_table[XCHAL_NUM_INTERRUPTS * OS_PORT_NUM_PROCESSORS]; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: xt_ints_on + * + * Description: + * Enables a set of interrupts. + * + * Input Parameters: + * mask - Bit mask of interrupts to be enabled. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void xt_ints_on(unsigned int mask) +{ + uint32_t intenable; + + __asm__ __volatile__("rsr %0, intenable" : "=r"(intenable)); + intenable |= mask; + __asm__ __volatile__("wsr %0, intenable; rsync" :: "r"(intenable)); +} + +/**************************************************************************** + * Name: xt_ints_off + * + * Description: + * Disables a set of interrupts. + * + * Input Parameters: + * mask - Bit mask of interrupts to be disabled. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void xt_ints_off(unsigned int mask) +{ + uint32_t intenable; + + __asm__ __volatile__("rsr %0, intenable" : "=r"(intenable)); + intenable &= ~mask; + __asm__ __volatile__("wsr %0, intenable; rsync" :: "r"(intenable)); +} + +/**************************************************************************** + * Name: esp_xtensa_intr_init + * + * Description: + * Initialize the interrupt handler table by setting all handlers to the + * default unhandled interrupt handler (provided by HAL's xtensa_intr.c). + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +void esp_xtensa_intr_init(void) +{ + int i; + + for (i = 0; i < (XCHAL_NUM_INTERRUPTS * OS_PORT_NUM_PROCESSORS); i++) + { + /* Calling xt_set_interrupt_handler with f=NULL sets the handler + * to xt_unhandled_interrupt (defined in HAL's xtensa_intr.c) + */ + + xt_set_interrupt_handler(i, NULL, (void *)(uintptr_t)i); + } +} diff --git a/arch/xtensa/src/esp32/Kconfig b/arch/xtensa/src/esp32/Kconfig index c4f2e5bef791c..a4af2e80e7505 100644 --- a/arch/xtensa/src/esp32/Kconfig +++ b/arch/xtensa/src/esp32/Kconfig @@ -196,9 +196,13 @@ config ESP32_XTAL_26MHz endchoice # On-board Crystal Frequency config ESP32_RT_TIMER - bool "Real-time Timer" + bool "Real-Time Timer" default n - select ESP32_TIMER0 + select ESPRESSIF_HR_TIMER + ---help--- + Deprecated: Use ESPRESSIF_HR_TIMER instead. + This option is kept for backward compatibility and automatically + selects the common ESPRESSIF_HR_TIMER configuration. config ESP32_RUN_IRAM bool "Run from IRAM" @@ -336,7 +340,7 @@ config ESP32_I2S0 bool "I2S 0" default n select ARCH_DMA - select ESP32_GPIO_IRQ + select ESPRESSIF_GPIO_IRQ select ESPRESSIF_I2S0 if ESP32_I2S0 @@ -466,7 +470,7 @@ config ESP32_I2S1 bool "I2S 1" default n select ARCH_DMA - select ESP32_GPIO_IRQ + select ESPRESSIF_GPIO_IRQ select ESPRESSIF_I2S1 if ESP32_I2S1 @@ -618,7 +622,7 @@ config ESP32_SPI2 bool "SPI 2" default n select ESP32_SPI - select ESP32_GPIO_IRQ + select ESPRESSIF_GPIO_IRQ select SPI select ESPRESSIF_SPI_PERIPH @@ -626,7 +630,7 @@ config ESP32_SPI3 bool "SPI 3" default n select ESP32_SPI - select ESP32_GPIO_IRQ + select ESPRESSIF_GPIO_IRQ select SPI select ESPRESSIF_SPI_PERIPH @@ -829,12 +833,16 @@ menu "Interrupt Configuration" config ESP32_IRAM_ISR_DEBUG bool "Enable debugging of the IRAM-enabled interrupts" default n + select ESPRESSIF_IRAM_ISR_DEBUG ---help--- This option enables keeping track of the IRAM-enabled interrupts by registering its execution when non-IRAM interrupts are disabled. It keeps track of the IRQ executed and register how many times since boot it was executed. + This option is kept for backwards compatibility and automatically + selects CONFIG_ESPRESSIF_IRAM_ISR_DEBUG. + endmenu # Interrupt Configuration menu "Memory Configuration" @@ -893,9 +901,11 @@ endmenu # Memory Configuration config ESP32_GPIO_IRQ bool "GPIO pin interrupts" + select ESPRESSIF_GPIO_IRQ default n ---help--- - Enable support for interrupting GPIO pins + This is a deprecated Kconfig macro. Its kept for retrocompatibility only. + Use "CONFIG_ESPRESSIF_GPIO_IRQ" instead. config ESP32_RTCIO_IRQ bool "RTC IO interrupts" @@ -2204,26 +2214,6 @@ endif endmenu # PHY -menu "Real-Time Timer" - depends on ESP32_RT_TIMER - -config ESP32_RT_TIMER_TASK_NAME - string "Timer task name" - default "rt_timer" - -config ESP32_RT_TIMER_TASK_PRIORITY - int "Timer task priority" - default 223 - ---help--- - Priority level of the RT Timer task. - Must be lower than the SCHED_HPWORKPRIORITY. - -config ESP32_RT_TIMER_TASK_STACK_SIZE - int "Timer task stack size" - default 2048 - -endmenu # Real-Time Timer - if ESP32_TIMER menu "Timer/counter Configuration" @@ -2879,12 +2869,9 @@ endmenu # Application Image Configuration config ESP32_AUTO_SLEEP bool "Auto-sleep" default n - select PM - select ESP32_RT_TIMER - select ESP32_TIMER0 - select ESP32_TICKLESS + select ESPRESSIF_AUTO_SLEEP ---help--- - Enable ESP32 Auto-sleep + This is a deprecated option. Use ESPRESSIF_AUTO_SLEEP instead. config ESP32_TICKLESS bool "Enable ESP32 tickless OS" diff --git a/arch/xtensa/src/esp32/Make.defs b/arch/xtensa/src/esp32/Make.defs index 178bfffb63688..807f7de0ed243 100644 --- a/arch/xtensa/src/esp32/Make.defs +++ b/arch/xtensa/src/esp32/Make.defs @@ -32,9 +32,9 @@ endif # Required ESP32 files (arch/xtensa/src/esp32) -CHIP_CSRCS = esp32_allocateheap.c esp32_clockconfig.c esp32_gpio.c +CHIP_CSRCS = esp32_allocateheap.c CHIP_CSRCS += esp32_systemreset.c esp32_resetcause.c -CHIP_CSRCS += esp32_irq.c esp32_region.c esp32_rtc_gpio.c +CHIP_CSRCS += esp32_region.c esp32_rtc_gpio.c CHIP_CSRCS += esp32_user.c esp32_libc_stubs.c CHIP_CSRCS += esp32_dma.c @@ -55,13 +55,6 @@ else CHIP_CSRCS += esp32_timerisr.c endif -ifeq ($(CONFIG_PM),y) -ifneq ($(CONFIG_ARCH_CUSTOM_PMINIT),y) -CHIP_CSRCS += esp32_pminitialize.c -endif -CHIP_CSRCS += esp32_pm.c -endif - ifeq ($(CONFIG_XTENSA_IMEM_USE_SEPARATE_HEAP),y) CHIP_CSRCS += esp32_imm.c endif @@ -164,10 +157,6 @@ ifeq ($(CONFIG_ARCH_USE_TEXT_HEAP),y) CHIP_CSRCS += esp32_textheap.c endif -ifeq ($(CONFIG_ESP32_RT_TIMER),y) -CHIP_CSRCS += esp32_rt_timer.c -endif - ifeq ($(CONFIG_ESP32_TOUCH),y) CHIP_CSRCS += esp32_touch.c endif @@ -184,13 +173,6 @@ ifeq ($(CONFIG_CRYPTO_CRYPTODEV_HARDWARE),y) CHIP_CSRCS += esp32_crypto.c endif -ifeq ($(CONFIG_ESP32_RTC),y) -CHIP_CSRCS += esp32_rtc.c -ifeq ($(CONFIG_RTC_DRIVER),y) -CHIP_CSRCS += esp32_rtc_lowerhalf.c -endif -endif - ifeq ($(CONFIG_ESP32_OPENETH),y) CHIP_CSRCS += esp_openeth.c endif @@ -212,7 +194,7 @@ endif ESP_HAL_3RDPARTY_REPO = esp-hal-3rdparty ifndef ESP_HAL_3RDPARTY_VERSION - ESP_HAL_3RDPARTY_VERSION = b9472bd56b916cced7447e25c2b2e1390d7e0d90 + ESP_HAL_3RDPARTY_VERSION = 6c272b562a73107a852d44b9c6fb5df57245cbd7 endif ifndef ESP_HAL_3RDPARTY_URL @@ -252,13 +234,16 @@ chip/$(ESP_HAL_3RDPARTY_REPO): $(Q) echo "Cloning Espressif HAL for 3rd Party Platforms" $(Q) $(call CLONE_ESP_HAL_3RDPARTY_REPO) ifneq ($(USE_NXTMPDIR_ESP_REPO_DIRECTLY),y) + $(Q) echo "Espressif HAL for 3rd Party Platforms: cleaning current repository..." + $(Q) git -C chip/$(ESP_HAL_3RDPARTY_REPO) clean -ffdx + $(Q) git -C chip/$(ESP_HAL_3RDPARTY_REPO) reset --quiet --hard --recurse-submodules || true $(Q) echo "Espressif HAL for 3rd Party Platforms: ${ESP_HAL_3RDPARTY_VERSION}" $(Q) git -C chip/$(ESP_HAL_3RDPARTY_REPO) checkout --quiet $(ESP_HAL_3RDPARTY_VERSION) endif # Silent preprocessor warnings -CFLAGS += -Wno-undef -Wno-unused-variable -fno-jump-tables -fno-tree-switch-conversion +CFLAGS += -Wno-undef -Wno-unused-variable -fno-jump-tables -fno-tree-switch-conversion -Wno-deprecated-declarations # Enable strict volatile bitfield access diff --git a/arch/xtensa/src/esp32/chip.h b/arch/xtensa/src/esp32/chip.h index 47412cf93aa84..39f6c1d68d746 100644 --- a/arch/xtensa/src/esp32/chip.h +++ b/arch/xtensa/src/esp32/chip.h @@ -32,7 +32,7 @@ #if defined(CONFIG_ESP32_OPENETH) && !defined(__ASSEMBLY__) #include "hardware/esp32_soc.h" -#include "esp32_irq.h" +#include "esp_irq.h" #endif /**************************************************************************** @@ -41,9 +41,9 @@ #if defined(CONFIG_ESP32_OPENETH) #define OPENETH_PERIPH_MAC ESP32_PERIPH_EMAC -#define OPENETH_CPUINT_LEVEL ESP32_CPUINT_LEVEL +#define OPENETH_CPUINT_LEVEL ESP_IRQ_TRIGGER_LEVEL #define OPENETH_IRQ_MAC ESP32_IRQ_EMAC -#define OPENETH_SETUP_IRQ esp32_setup_irq +#define OPENETH_SETUP_IRQ esp_setup_irq #define RX_BUF_COUNT CONFIG_ESP32_OPENETH_DMA_RX_BUFFER_NUM #endif diff --git a/arch/xtensa/src/esp32/esp32_ble_adapter.c b/arch/xtensa/src/esp32/esp32_ble_adapter.c index a2980b03ada98..895c2da667585 100644 --- a/arch/xtensa/src/esp32/esp32_ble_adapter.c +++ b/arch/xtensa/src/esp32/esp32_ble_adapter.c @@ -52,12 +52,12 @@ #include "hardware/esp32_dport.h" #include "hardware/wdev_reg.h" #include "xtensa.h" -#include "xtensa_attr.h" + #include "utils/memory_reserve.h" -#include "esp32_rt_timer.h" +#include "esp_hr_timer.h" #include "espressif/esp_wireless.h" #include "espressif/esp_wifi_utils.h" -#include "esp32_irq.h" +#include "esp_irq.h" #include "esp_bt.h" #include "esp_log.h" @@ -128,12 +128,6 @@ # define BLE_TASK_EVENT_QUEUE_LEN 8 #endif -#ifdef CONFIG_ESPRESSIF_BLE_INTERRUPT_SAVE_STATUS -# define NR_IRQSTATE_FLAGS CONFIG_ESPRESSIF_BLE_INTERRUPT_SAVE_STATUS -#else -# define NR_IRQSTATE_FLAGS 3 -#endif - #define RTC_CLK_CAL_FRACT 19 /* Number of fractional bits in values returned by rtc_clk_cal */ /**************************************************************************** @@ -297,10 +291,31 @@ struct irqstate_list_s irqstate_t flags; }; +typedef struct shared_vector_desc_t shared_vector_desc_t; +typedef struct vector_desc_t vector_desc_t; + +typedef struct intr_handle_data_t +{ + vector_desc_t *vector_desc; + shared_vector_desc_t *shared_vector_desc; +} intr_handle_data_t; + +struct vector_desc_t +{ + int flags: 16; + unsigned int cpu: 1; + unsigned int intno: 5; + int source: 16; + shared_vector_desc_t *shared_vec_info; + vector_desc_t *next; +}; + /**************************************************************************** * Private Function Prototypes ****************************************************************************/ +extern vector_desc_t *get_desc_for_int(int intno, int cpu); + /**************************************************************************** * Functions to be registered to struct osi_funcs_s ****************************************************************************/ @@ -313,7 +328,6 @@ struct irqstate_list_s */ static xt_handler ble_set_isr(int n, xt_handler f, void *arg); -static void ints_on(unsigned int mask); static void IRAM_ATTR interrupt_disable(void); static void IRAM_ATTR interrupt_restore(void); static void IRAM_ATTR task_yield_from_isr(void); @@ -409,7 +423,6 @@ static void IRAM_ATTR cause_sw_intr(void *arg); static void btdm_slp_tmr_customer_callback(void * arg); static void IRAM_ATTR btdm_slp_tmr_callback(void *arg); #endif -static int IRAM_ATTR esp_int_adpt_cb(int irq, void *context, void *arg); static void btdm_wakeup_request_callback(void * arg); static void btdm_controller_mem_init(void); static uint32_t btdm_config_mask_load(void); @@ -507,7 +520,7 @@ static struct osi_funcs_s g_osi_funcs_ro = { ._version = OSI_VERSION, ._set_isr = ble_set_isr, - ._ints_on = ints_on, + ._ints_on = xt_ints_on, ._interrupt_disable = interrupt_disable, ._interrupt_restore = interrupt_restore, ._task_yield = task_yield_from_isr, @@ -683,11 +696,9 @@ static DRAM_ATTR bool g_btdm_allow_light_sleep; /* BT interrupt private data */ -static sq_queue_t g_ble_int_flags_free; +irqstate_t g_ble_int_flags; -static sq_queue_t g_ble_int_flags_used; - -static struct irqstate_list_s g_ble_int_flags[NR_IRQSTATE_FLAGS]; +static int g_ble_int_count = 0; /* Cached queue control variables */ @@ -827,75 +838,55 @@ static inline void btdm_check_and_init_bb(void) static xt_handler ble_set_isr(int n, xt_handler f, void *arg) { int ret; - uint32_t tmp; - struct irq_adpt_s *adapter; - int irq = esp32_getirq(0, n); - - wlinfo("n=%d f=%p arg=%p irq=%d\n", n, f, arg, irq); + intr_handle_t handle; + int irq; - if (g_irqvector[irq].handler && - g_irqvector[irq].handler != irq_unexpected_isr) + switch (n) { - wlinfo("irq=%d has been set handler=%p\n", irq, - g_irqvector[irq].handler); - return NULL; - } + case 5: + { + irq = ESP_SOURCE2IRQ(ETS_RWBT_INTR_SOURCE); + } + break; - tmp = sizeof(struct irq_adpt_s); - adapter = kmm_malloc(tmp); - if (!adapter) - { - wlerr("Failed to alloc %" PRIu32 " memory\n", tmp); - DEBUGPANIC(); - return NULL; + case 7: + { + irq = ETS_INTERNAL_SW0_INTR_SOURCE + \ + ETS_INTERNAL_INTR_SOURCE_OFF; + } + break; + + case 8: + { + irq = ESP_SOURCE2IRQ(ETS_BT_BB_INTR_SOURCE); + } + break; + + default: + { + wlerr("ERROR: Invalid interrupt number %d\n", n); + return NULL; + } } - adapter->func = f; - adapter->arg = arg; + wlinfo("n=%d f=%p arg=%p irq=%d\n", n, f, arg, irq); - ret = irq_attach(irq, esp_int_adpt_cb, adapter); - if (ret) + handle = kmm_calloc(1, sizeof(intr_handle_data_t)); + if (handle == NULL) { - wlerr("Failed to attach IRQ %d\n", irq); - DEBUGPANIC(); + wlerr("Failed to kmm_calloc\n"); return NULL; } - return NULL; -} + handle->vector_desc = get_desc_for_int(n, this_cpu()); -/**************************************************************************** - * Name: ints_on - * - * Description: - * Enable BLE interrupt - * - * Input Parameters: - * mask - Mask used to indicate the bits to enable interrupt. - * - * Returned Value: - * None - * - ****************************************************************************/ + /* Register the handle - it contains all needed information (cpuint, cpu) */ -static void ints_on(unsigned int mask) -{ - uint32_t bit; - int irq; + esp_set_handle(this_cpu(), irq, handle); - for (int i = 0; i < 32; i++) - { - bit = 1 << i; - if (bit & mask) - { - irq = esp32_getirq(0, i); - DEBUGVERIFY(esp32_irq_set_iram_isr(irq)); - up_enable_irq(irq); - wlinfo("Enabled bit %d\n", irq); - } - } + xt_set_interrupt_handler(n, (xt_handler)f, arg); - UNUSED(irq); + return NULL; } /**************************************************************************** @@ -917,13 +908,12 @@ static void IRAM_ATTR interrupt_disable(void) { struct irqstate_list_s *irqstate; - irqstate = (struct irqstate_list_s *)sq_remlast(&g_ble_int_flags_free); - - ASSERT(irqstate != NULL); - - irqstate->flags = enter_critical_section(); + if (g_ble_int_count == 0) + { + g_ble_int_flags = enter_critical_section(); + } - sq_addlast((sq_entry_t *)irqstate, &g_ble_int_flags_used); + g_ble_int_count++; } /**************************************************************************** @@ -945,13 +935,12 @@ static void IRAM_ATTR interrupt_restore(void) { struct irqstate_list_s *irqstate; - irqstate = (struct irqstate_list_s *)sq_remlast(&g_ble_int_flags_used); - - ASSERT(irqstate != NULL); - - leave_critical_section(irqstate->flags); + g_ble_int_count--; - sq_addlast((sq_entry_t *)irqstate, &g_ble_int_flags_free); + if (g_ble_int_count == 0) + { + leave_critical_section(g_ble_int_flags); + } } /**************************************************************************** @@ -2567,31 +2556,6 @@ static void IRAM_ATTR btdm_slp_tmr_callback(void *arg) } #endif -/**************************************************************************** - * Name: esp_int_adpt_cb - * - * Description: - * BT interrupt adapter callback function - * - * Input Parameters: - * irq - Number of the IRQ that generated the interrupt - * context - Interrupt register state save info (not used) - * arg - Argument passed to the interrupt callback - * - * Returned Value: - * OK - * - ****************************************************************************/ - -static int IRAM_ATTR esp_int_adpt_cb(int irq, void *context, void *arg) -{ - struct irq_adpt_s *adapter = (struct irq_adpt_s *)arg; - - adapter->func(adapter->arg); - - return OK; -} - /**************************************************************************** * Name: btdm_wakeup_request_callback * @@ -2905,17 +2869,7 @@ int esp32_bt_controller_init(void) return -EIO; } - /* Initialize list of interrupt flags to enable chained critical sections - * to return successfully. - */ - - sq_init(&g_ble_int_flags_free); - sq_init(&g_ble_int_flags_used); - - for (i = 0; i < NR_IRQSTATE_FLAGS; i++) - { - sq_addlast((sq_entry_t *)&g_ble_int_flags[i], &g_ble_int_flags_free); - } + g_ble_int_count = 0; #ifdef CONFIG_ESPRESSIF_SPIFLASH diff --git a/arch/xtensa/src/esp32/esp32_clockconfig.c b/arch/xtensa/src/esp32/esp32_clockconfig.c deleted file mode 100644 index 54675e151e003..0000000000000 --- a/arch/xtensa/src/esp32/esp32_clockconfig.c +++ /dev/null @@ -1,218 +0,0 @@ -/**************************************************************************** - * arch/xtensa/src/esp32/esp32_clockconfig.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include "xtensa.h" -#include "xtensa_attr.h" -#include "hardware/esp32_dport.h" -#include "hardware/esp32_soc.h" -#include "hardware/esp32_uart.h" -#include "esp32_rtc.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef CONFIG_ESP_CONSOLE_UART_NUM -#define CONFIG_ESP_CONSOLE_UART_NUM 0 -#endif - -#define DEFAULT_CPU_FREQ 80 - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -enum cpu_freq_e -{ - CPU_80M = 0, - CPU_160M = 1, - CPU_240M = 2, -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32_uart_tx_wait_idle - * - * Description: - * Wait until uart tx full empty and the last char send ok. - * - * Input Parameters: - * uart_no - 0 for UART0, 1 for UART1, 2 for UART2 - * - * Returned Value: - * None - * - ****************************************************************************/ - -static inline void esp32_uart_tx_wait_idle(uint8_t uart_no) -{ - uint32_t status; - do - { - status = getreg32(UART_STATUS_REG(uart_no)); - - /* either tx count or state is non-zero */ - } - while ((status & (UART_ST_UTX_OUT_M | UART_TXFIFO_CNT_M)) != 0); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -extern uint32_t g_ticks_per_us_pro; -#ifdef CONFIG_SMP -extern uint32_t g_ticks_per_us_app; -#endif - -/**************************************************************************** - * Name: esp32_update_cpu_freq - * - * Description: - * Set the real CPU ticks per us to the ets, so that ets_delay_us - * will be accurate. Call this function when CPU frequency is changed. - * - * Input Parameters: - * ticks_per_us - CPU ticks per us - * - * Returned Value: - * None - * - ****************************************************************************/ - -void IRAM_ATTR esp32_update_cpu_freq(uint32_t ticks_per_us) -{ - /* Update scale factors used by esp_rom_delay_us */ - - g_ticks_per_us_pro = ticks_per_us; -#ifdef CONFIG_SMP - g_ticks_per_us_app = ticks_per_us; -#endif -} - -/**************************************************************************** - * Name: esp32_set_cpu_freq - * - * Description: - * Switch to one of PLL-based frequencies. - * Current frequency can be XTAL or PLL. - * - * Input Parameters: - * cpu_freq_mhz - new CPU frequency - * - * Returned Value: - * None - * - ****************************************************************************/ - -void IRAM_ATTR esp32_set_cpu_freq(int cpu_freq_mhz) -{ - int dbias = DIG_DBIAS_80M_160M; - int per_conf = CPU_240M; - uint32_t value; - - switch (cpu_freq_mhz) - { - case 160: - per_conf = CPU_160M; - break; - - case 240: - dbias = DIG_DBIAS_240M; - per_conf = CPU_240M; - break; - - case 80: - per_conf = CPU_80M; - - default: - break; - } - - value = (((80 * MHZ) >> 12) & UINT16_MAX) | - ((((80 * MHZ) >> 12) & UINT16_MAX) << 16); - putreg32(per_conf, DPORT_CPU_PER_CONF_REG); - REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, dbias); - REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, - RTC_CNTL_SOC_CLK_SEL_PLL); - putreg32(value, RTC_APB_FREQ_REG); - esp32_update_cpu_freq(cpu_freq_mhz); - esp32_rtc_wait_for_slow_cycle(); -} - -/**************************************************************************** - * Name: esp32_clockconfig - * - * Description: - * Called to initialize the ESP32. This does whatever setup is needed to - * put the SoC in a usable state. This includes the initialization of - * clocking using the settings in board.h. - * - ****************************************************************************/ - -void esp32_clockconfig(void) -{ - uint32_t freq_mhz = CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ; - uint32_t old_freq_mhz; - uint32_t source_freq_mhz; - enum esp32_rtc_xtal_freq_e xtal_freq = RTC_XTAL_FREQ_40M; - - old_freq_mhz = esp_rtc_clk_get_cpu_freq(); - if (old_freq_mhz == freq_mhz) - { - return; - } - - switch (freq_mhz) - { - case 240: - source_freq_mhz = RTC_PLL_FREQ_480M; - break; - - case 160: - source_freq_mhz = RTC_PLL_FREQ_320M; - break; - - case 80: - source_freq_mhz = RTC_PLL_FREQ_320M; - break; - - default: - return; - } - - esp32_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM); - esp32_rtc_update_to_xtal(xtal_freq, 1); - esp32_rtc_bbpll_enable(); - esp32_rtc_bbpll_configure(xtal_freq, source_freq_mhz); - esp32_set_cpu_freq(freq_mhz); -} diff --git a/arch/xtensa/src/esp32/esp32_clockconfig.h b/arch/xtensa/src/esp32/esp32_clockconfig.h deleted file mode 100644 index 39b6490b04bc6..0000000000000 --- a/arch/xtensa/src/esp32/esp32_clockconfig.h +++ /dev/null @@ -1,82 +0,0 @@ -/**************************************************************************** - * arch/xtensa/src/esp32/esp32_clockconfig.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_XTENSA_SRC_ESP32_ESP32_CLOCKCONFIG_H -#define __ARCH_XTENSA_SRC_ESP32_ESP32_CLOCKCONFIG_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "esp_private/esp_clk.h" - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32_update_cpu_freq - * - * Description: - * Set the real CPU ticks per us to the ets, so that ets_delay_us - * will be accurate. Call this function when CPU frequency is changed. - * - * Input Parameters: - * ticks_per_us - CPU ticks per us - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32_update_cpu_freq(uint32_t ticks_per_us); - -/**************************************************************************** - * Name: esp32_set_cpu_freq - * - * Description: - * Switch to one of PLL-based frequencies. - * Current frequency can be XTAL or PLL. - * - * Input Parameters: - * cpu_freq_mhz - new CPU frequency - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32_set_cpu_freq(int cpu_freq_mhz); - -/**************************************************************************** - * Name: esp32_clockconfig - * - * Description: - * Called to initialize the ESP32. This does whatever setup is needed to - * put the SoC in a usable state. This includes the initialization of - * clocking using the settings in board.h. - * - ****************************************************************************/ - -void esp32_clockconfig(void); - -#endif /* __ARCH_XTENSA_SRC_ESP32_ESP32_CLOCKCONFIG_H */ diff --git a/arch/xtensa/src/esp32/esp32_cpustart.c b/arch/xtensa/src/esp32/esp32_cpustart.c index 2e78e316de4e9..a28a76437a305 100644 --- a/arch/xtensa/src/esp32/esp32_cpustart.c +++ b/arch/xtensa/src/esp32/esp32_cpustart.c @@ -38,12 +38,13 @@ #include "xtensa.h" #include "hardware/esp32_dport.h" -#include "hardware/esp32_rtccntl.h" +#include "soc/rtc_cntl_reg.h" #include "esp32_region.h" -#include "esp32_irq.h" +#include "espressif/esp_irq.h" #include "esp32_smp.h" -#include "esp32_gpio.h" +#include "esp32_start.h" +#include "espressif/esp_gpio.h" /**************************************************************************** * Private Data @@ -63,21 +64,24 @@ extern void ets_set_appcpu_boot_addr(uint32_t start); /**************************************************************************** * Name: xtensa_attach_fromcpu0_interrupt + * + * Description: + * Attach the inter-CPU interrupt for CPU1 to receive from CPU0. + * This is called during early CPU1 boot. + * ****************************************************************************/ -static inline void xtensa_attach_fromcpu0_interrupt(void) +static inline void IRAM_ATTR xtensa_attach_fromcpu0_interrupt(void) { int cpuint; /* Connect all CPU peripheral source to allocated CPU interrupt */ - cpuint = esp32_setup_irq(1, ESP32_PERIPH_CPU_CPU0, 1, ESP32_CPUINT_LEVEL); + cpuint = esp_setup_irq(ESP32_PERIPH_CPU_CPU0, 1, + ESP_IRQ_TRIGGER_LEVEL, esp32_fromcpu0_interrupt, + NULL); DEBUGASSERT(cpuint >= 0); - /* Attach the inter-CPU interrupt. */ - - irq_attach(ESP32_IRQ_CPU_CPU0, (xcpt_t)esp32_fromcpu0_interrupt, NULL); - /* Enable the inter 0 CPU interrupts. */ up_enable_irq(ESP32_IRQ_CPU_CPU0); @@ -126,10 +130,6 @@ void IRAM_ATTR xtensa_appcpu_start(void) sched_note_cpu_started(tcb); #endif - /* Signal to the PRO CPU that the APP CPU has started. */ - - g_appcpu_started = true; - /* Move CPU0 exception vectors to IRAM */ __asm__ __volatile__ ("wsr %0, vecbase\n"::"r" (_init_start)); @@ -140,30 +140,18 @@ void IRAM_ATTR xtensa_appcpu_start(void) /* Initialize CPU interrupts */ - esp32_cpuint_initialize(); - - /* Attach and enable internal interrupts */ + esp_cpuint_initialize(); /* Attach and enable the inter-CPU interrupt */ xtensa_attach_fromcpu0_interrupt(); - /* Enable the software interrupt */ - - up_enable_irq(XTENSA_IRQ_SWINT); - /* Dump registers so that we can see what is going to happen on return */ #if 0 up_dump_register(tcb->xcp.regs); #endif -#ifdef CONFIG_ESP32_GPIO_IRQ - /* Initialize GPIO interrupt support */ - - esp32_gpioirqinitialize(1); -#endif - #ifndef CONFIG_SUPPRESS_INTERRUPTS /* And Enable interrupts */ @@ -174,6 +162,12 @@ void IRAM_ATTR xtensa_appcpu_start(void) xtensa_set_cpenable(CONFIG_XTENSA_CP_INITSET); #endif + sys_startup_fn(); + + /* Signal to the PRO CPU that the APP CPU has started. */ + + g_appcpu_started = true; + /* Then switch contexts. This instantiates the exception context of the * tcb at the head of the assigned task list. In this case, this should * be the CPUs NULL task. @@ -275,4 +269,3 @@ int up_cpu_start(int cpu) return OK; } - diff --git a/arch/xtensa/src/esp32/esp32_emac.c b/arch/xtensa/src/esp32/esp32_emac.c index ae65a018b507f..e1980a805f1c7 100644 --- a/arch/xtensa/src/esp32/esp32_emac.c +++ b/arch/xtensa/src/esp32/esp32_emac.c @@ -55,13 +55,12 @@ #endif #include "xtensa.h" -#include "xtensa_attr.h" #include "hardware/esp32_gpio_sigmap.h" #include "hardware/esp32_dport.h" #include "hardware/esp32_emac.h" -#include "esp32_gpio.h" -#include "esp32_irq.h" +#include "esp_gpio.h" +#include "esp_irq.h" #include @@ -514,25 +513,25 @@ static int emac_read_mac(uint8_t *mac) static void emac_init_gpio(void) { - esp32_configgpio(EMAC_TXEN_PIN, OUTPUT_FUNCTION_6); - esp32_configgpio(EMAC_TXDO_PIN, OUTPUT_FUNCTION_6); - esp32_configgpio(EMAC_TXD1_PIN, OUTPUT_FUNCTION_6); + esp_configgpio(EMAC_TXEN_PIN, OUTPUT_FUNCTION_6); + esp_configgpio(EMAC_TXDO_PIN, OUTPUT_FUNCTION_6); + esp_configgpio(EMAC_TXD1_PIN, OUTPUT_FUNCTION_6); - esp32_configgpio(EMAC_RXDO_PIN, INPUT_FUNCTION_6); - esp32_configgpio(EMAC_RXD1_PIN, INPUT_FUNCTION_6); - esp32_configgpio(EMAC_RXDV_PIN, INPUT_FUNCTION_6); + esp_configgpio(EMAC_RXDO_PIN, INPUT_FUNCTION_6); + esp_configgpio(EMAC_RXD1_PIN, INPUT_FUNCTION_6); + esp_configgpio(EMAC_RXDV_PIN, INPUT_FUNCTION_6); - esp32_configgpio(EMAC_ICLK_PIN, INPUT_FUNCTION_6); + esp_configgpio(EMAC_ICLK_PIN, INPUT_FUNCTION_6); - esp32_configgpio(EMAC_MDC_PIN, OUTPUT | FUNCTION_3); - esp32_gpio_matrix_out(EMAC_MDC_PIN, EMAC_MDC_O_IDX, 0, 0); + esp_configgpio(EMAC_MDC_PIN, OUTPUT | FUNCTION_3); + esp_gpio_matrix_out(EMAC_MDC_PIN, EMAC_MDC_O_IDX, 0, 0); - esp32_configgpio(EMAC_MDIO_PIN, OUTPUT | INPUT | FUNCTION_3); - esp32_gpio_matrix_out(EMAC_MDIO_PIN, EMAC_MDO_O_IDX, 0, 0); - esp32_gpio_matrix_in(EMAC_MDIO_PIN, EMAC_MDI_I_IDX, 0); + esp_configgpio(EMAC_MDIO_PIN, OUTPUT | INPUT | FUNCTION_3); + esp_gpio_matrix_out(EMAC_MDIO_PIN, EMAC_MDO_O_IDX, 0, 0); + esp_gpio_matrix_in(EMAC_MDIO_PIN, EMAC_MDI_I_IDX, 0); #ifdef CONFIG_ESP32_ETH_ENABLE_PHY_RSTPIN - esp32_configgpio(EMAC_PHYRST_PIN, OUTPUT | PULLUP); + esp_configgpio(EMAC_PHYRST_PIN, OUTPUT | PULLUP); #endif } @@ -564,9 +563,9 @@ static int emac_config(void) /* Hardware reset PHY chip */ - esp32_gpiowrite(EMAC_PHYRST_PIN, false); + esp_gpiowrite(EMAC_PHYRST_PIN, false); up_udelay(50); - esp32_gpiowrite(EMAC_PHYRST_PIN, true); + esp_gpiowrite(EMAC_PHYRST_PIN, true); #endif /* Open hardware clock */ @@ -2047,8 +2046,11 @@ int esp32_emac_init(void) memset(priv, 0, sizeof(struct esp32_emac_s)); priv->cpu = this_cpu(); - priv->cpuint = esp32_setup_irq(priv->cpu, ESP32_PERIPH_EMAC, - 1, ESP32_CPUINT_LEVEL); + priv->cpuint = esp_setup_irq(ESP32_PERIPH_EMAC, + 1, + ESP_IRQ_TRIGGER_LEVEL, + emac_interrupt, + priv); if (priv->cpuint < 0) { nerr("ERROR: Failed alloc interrupt\n"); @@ -2057,15 +2059,6 @@ int esp32_emac_init(void) goto error; } - ret = irq_attach(ESP32_IRQ_EMAC, emac_interrupt, priv); - if (ret != 0) - { - nerr("ERROR: Failed attach interrupt\n"); - - ret = -ENOMEM; - goto errout_with_attachirq; - } - /* Initialize the driver structure */ priv->dev.d_ifup = emac_ifup; /* I/F up (new IP address) callback */ @@ -2098,7 +2091,7 @@ int esp32_emac_init(void) return 0; errout_with_attachirq: - esp32_teardown_irq(priv->cpu, ESP32_PERIPH_EMAC, priv->cpuint); + esp_teardown_irq(ESP32_PERIPH_EMAC, priv->cpuint); error: return ret; diff --git a/arch/xtensa/src/esp32/esp32_freerun.c b/arch/xtensa/src/esp32/esp32_freerun.c index 796e50c2de682..5276a728b5c09 100644 --- a/arch/xtensa/src/esp32/esp32_freerun.c +++ b/arch/xtensa/src/esp32/esp32_freerun.c @@ -36,7 +36,6 @@ #include #include -#include "esp32_clockconfig.h" #include "esp32_freerun.h" #ifdef CONFIG_ESP32_FREERUN diff --git a/arch/xtensa/src/esp32/esp32_gpio.c b/arch/xtensa/src/esp32/esp32_gpio.c deleted file mode 100644 index fe56b82a84a6e..0000000000000 --- a/arch/xtensa/src/esp32/esp32_gpio.c +++ /dev/null @@ -1,625 +0,0 @@ -/**************************************************************************** - * arch/xtensa/src/esp32/esp32_gpio.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include - -#include -#include -#include - -#include "xtensa.h" - -#include "soc/soc_caps.h" - -#include "hardware/esp32_iomux.h" -#include "hardware/esp32_gpio.h" - -#include "esp32_irq.h" -#include "esp32_rtc_gpio.h" - -#include "esp32_gpio.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define NGPIO_HPINS (ESP32_NIRQ_GPIO - 32) -#define NGPIO_HMASK ((UINT32_C(1) << NGPIO_HPINS) - 1) -#define _NA_ 0xff - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_ESP32_GPIO_IRQ -static int g_gpio_cpuint[CONFIG_SMP_NCPUS]; -#endif - -static const uint8_t g_pin2func[40] = -{ - 0x44, 0x88, 0x40, 0x84, 0x48, 0x6c, 0x60, 0x64, /* 0-7 */ - 0x68, 0x54, 0x58, 0x5c, 0x34, 0x38, 0x30, 0x3c, /* 8-15 */ - 0x4c, 0x50, 0x70, 0x74, _NA_, 0x7c, 0x80, 0x8c, /* 16-19, N/A, 21-23 */ - _NA_, 0x24, 0x28, 0x2c, _NA_, _NA_, _NA_, _NA_, /* N/A, 25-27, N/A, N/A, N/A, N/A */ - 0x1c, 0x20, 0x14, 0x18, 0x04, 0x08, 0x0c, 0x10 /* 32-39 */ -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: gpio_is_valid_rtc_gpio - * - * Description: - * Determine if the specified GPIO is a valid RTC GPIO. - * - * Input Parameters: - * gpio_num - GPIO pin to be checked. - * - * Returned Value: - * True if valid. False otherwise. - * - ****************************************************************************/ - -static inline bool gpio_is_valid_rtc_gpio(uint32_t gpio_num) -{ - return (gpio_num < GPIO_PIN_COUNT && g_gpio_to_rtcio_map[gpio_num] >= 0); -} - -/**************************************************************************** - * Name: rtc_gpio_is_pull_supported - * - * Description: - * Determine if the specified rtcio_num supports pull-up/pull-down. - * - * Input Parameters: - * rtcio_num - RTC GPIO to be checked. - * - * Returned Value: - * True if pull-up/pull-down supported. False otherwise. - * - ****************************************************************************/ - -static inline bool rtc_gpio_is_pull_supported(uint32_t rtcio_num) -{ - /* Pins 34 through 39 use RTC channels 0 to 5 and don't support PU/PD */ - - return (rtcio_num > 5); -} - -/**************************************************************************** - * Name: gpio_dispatch - * - * Description: - * Second level dispatch for GPIO interrupt handling. - * - ****************************************************************************/ - -#ifdef CONFIG_ESP32_GPIO_IRQ -static void gpio_dispatch(int irq, uint32_t status, uint32_t *regs) -{ - uint32_t mask; - int i; - - /* Check each bit in the status register */ - - for (i = 0; i < 32 && status != 0; i++) - { - /* Check if there is an interrupt pending for this pin */ - - mask = (UINT32_C(1) << i); - if ((status & mask) != 0) - { - /* Yes... perform the second level dispatch */ - - irq_dispatch(irq + i, regs); - - /* Clear the bit in the status so that we might execute this loop - * sooner. - */ - - status &= ~mask; - } - } -} -#endif - -/**************************************************************************** - * Name: gpio_interrupt - * - * Description: - * GPIO interrupt handler. - * - ****************************************************************************/ - -#ifdef CONFIG_ESP32_GPIO_IRQ -static int gpio_interrupt(int irq, void *context, void *arg) -{ - uint32_t status; - - /* Read and clear the lower GPIO interrupt status */ - - status = getreg32(GPIO_STATUS_REG); - putreg32(status, GPIO_STATUS_W1TC_REG); - - /* Dispatch pending interrupts in the lower GPIO status register */ - - gpio_dispatch(ESP32_FIRST_GPIOIRQ, status, (uint32_t *)context); - - /* Read and clear the upper GPIO interrupt status */ - - status = getreg32(GPIO_STATUS1_REG) & NGPIO_HMASK; - putreg32(status, GPIO_STATUS1_W1TC_REG); - - /* Dispatch pending interrupts in the lower GPIO status register */ - - gpio_dispatch(ESP32_FIRST_GPIOIRQ + 32, status, (uint32_t *)context); - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32_configgpio - * - * Description: - * Configure a GPIO pin based on encoded pin attributes. - * - * Input Parameters: - * pin - GPIO pin to be configured - * attr - Attributes to be configured for the selected GPIO pin. - * The following attributes are accepted: - * - Direction (OUTPUT or INPUT) - * - Pull (PULLUP, PULLDOWN or OPENDRAIN) - * - Function (if not provided, assume function GPIO by default) - * - Drive strength (if not provided, assume DRIVE_2 by default) - * - * Returned Value: - * Zero (OK) on success, or -1 (ERROR) in case of failure. - * - ****************************************************************************/ - -int esp32_configgpio(int pin, gpio_pinattr_t attr) -{ - uintptr_t regaddr; - uint32_t func; - uint32_t cntrl; - - DEBUGASSERT(pin >= 0 && pin <= ESP32_NGPIOS); - - /* Handle input pins */ - - func = 0; - cntrl = 0; - - if ((attr & INPUT) != 0) - { - if (pin < 32) - { - putreg32((UINT32_C(1) << pin), GPIO_ENABLE_W1TC_REG); - } - else - { - putreg32((UINT32_C(1) << (pin - 32)), GPIO_ENABLE1_W1TC_REG); - } - - /* Input enable */ - - func |= FUN_IE; - - /* Some pins only support Pull-Up and Pull-Down resistor on RTC GPIO */ - - if (gpio_is_valid_rtc_gpio(pin)) - { - uint32_t rtc_gpio_idx = g_gpio_to_rtcio_map[pin]; - uint32_t regval; - uint32_t rtc_gpio_pin; - bool en_pu = false; - bool en_pd = false; - - if ((attr & PULLUP) != 0) - { - ASSERT(rtc_gpio_is_pull_supported(rtc_gpio_idx)); - en_pu = true; - } - else if ((attr & PULLDOWN) != 0) - { - ASSERT(rtc_gpio_is_pull_supported(rtc_gpio_idx)); - en_pd = true; - } - - /* Get the pin register */ - - rtc_gpio_pin = g_rtc_io_desc[rtc_gpio_idx].reg; - - /* Read the current value from RTC GPIO pin */ - - regval = getreg32(rtc_gpio_pin); - - /* RTC_IO_X32P (GPIO32) uses different PU/PD bits */ - - if (rtc_gpio_idx == RTCIO_GPIO32_CHANNEL) - { - /* First, disable PU/PD */ - - regval &= ~SPECIAL_RTC_PU_BIT; - regval &= ~SPECIAL_RTC_PD_BIT; - - /* Enable PU/PD, if needed */ - - regval |= en_pu ? SPECIAL_RTC_PU_BIT : 0; - regval |= en_pd ? SPECIAL_RTC_PD_BIT : 0; - } - else - { - /* First, disable PU/PD */ - - regval &= ~DEFAULT_RTC_PU_BIT; - regval &= ~DEFAULT_RTC_PD_BIT; - - /* Enable PU/PD, if needed */ - - regval |= en_pu ? DEFAULT_RTC_PU_BIT : 0; - regval |= en_pd ? DEFAULT_RTC_PD_BIT : 0; - } - - putreg32(regval, rtc_gpio_pin); - } - else if ((attr & PULLUP) != 0) - { - func |= FUN_PU; - } - else if (attr & PULLDOWN) - { - func |= FUN_PD; - } - } - - /* Handle output pins */ - - if ((attr & OUTPUT) != 0) - { - if (pin < 32) - { - putreg32((UINT32_C(1) << pin), GPIO_ENABLE_W1TS_REG); - } - else - { - putreg32((UINT32_C(1) << (pin - 32)), GPIO_ENABLE1_W1TS_REG); - } - } - - /* Configure the pad's function */ - - if ((attr & FUNCTION_MASK) != 0) - { - uint32_t val = ((attr & FUNCTION_MASK) >> FUNCTION_SHIFT) - 1; - func |= val << MCU_SEL_S; - } - else - { - /* Function not provided, assuming function GPIO by default */ - - func |= (uint32_t)(PIN_FUNC_GPIO << MCU_SEL_S); - } - - /* Configure the pad's drive strength */ - - if ((attr & DRIVE_MASK) != 0) - { - uint32_t val = ((attr & DRIVE_MASK) >> DRIVE_SHIFT) - 1; - func |= val << FUN_DRV_S; - } - else - { - /* Drive strength not provided, assuming strength 2 by default */ - - func |= UINT32_C(2) << FUN_DRV_S; - } - - if ((attr & OPEN_DRAIN) != 0) - { - cntrl |= (1 << GPIO_PIN_PAD_DRIVER_S); - } - - regaddr = DR_REG_IO_MUX_BASE + g_pin2func[pin]; - putreg32(func, regaddr); - - regaddr = GPIO_REG(pin); - putreg32(cntrl, regaddr); - return OK; -} - -/**************************************************************************** - * Name: esp32_gpiowrite - * - * Description: - * Write one or zero to the selected GPIO pin - * - ****************************************************************************/ - -void esp32_gpiowrite(int pin, bool value) -{ - DEBUGASSERT(pin >= 0 && pin <= ESP32_NGPIOS); - - if (value) - { - if (pin < 32) - { - putreg32((uint32_t)(UINT32_C(1) << pin), GPIO_OUT_W1TS_REG); - } - else - { - putreg32((uint32_t)(UINT32_C(1) << (pin - 32)), - GPIO_OUT1_W1TS_REG); - } - } - else - { - if (pin < 32) - { - putreg32((uint32_t)(UINT32_C(1) << pin), GPIO_OUT_W1TC_REG); - } - else - { - putreg32((uint32_t)(UINT32_C(1) << (pin - 32)), - GPIO_OUT1_W1TC_REG); - } - } -} - -/**************************************************************************** - * Name: esp32_gpioread - * - * Description: - * Read one or zero from the selected GPIO pin - * - ****************************************************************************/ - -bool esp32_gpioread(int pin) -{ - uint32_t regval; - - DEBUGASSERT(pin >= 0 && pin <= ESP32_NGPIOS); - - if (pin < 32) - { - regval = getreg32(GPIO_IN_REG); - return ((regval >> pin) & 1) != 0; - } - else - { - regval = getreg32(GPIO_IN1_REG); - return ((regval >> (pin - 32)) & 1) != 0; - } -} - -/**************************************************************************** - * Name: esp32_gpioirqinitialize - * - * Description: - * Initialize logic to support a second level of interrupt decoding for - * GPIO pins. - * - ****************************************************************************/ - -#ifdef CONFIG_ESP32_GPIO_IRQ -void esp32_gpioirqinitialize(int cpu) -{ -#ifdef CONFIG_SMP - DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS); -#else - DEBUGASSERT(cpu == 0); -#endif - - /* Setup the GPIO interrupt. */ - - g_gpio_cpuint[cpu] = esp32_setup_irq(cpu, ESP32_PERIPH_CPU_GPIO, - 1, ESP32_CPUINT_LEVEL); - DEBUGASSERT(g_gpio_cpuint[cpu] >= 0); - - /* Attach and enable the interrupt handler */ - - DEBUGVERIFY(irq_attach(esp32_irq_gpio(cpu), gpio_interrupt, NULL)); - up_enable_irq(esp32_irq_gpio(cpu)); -} -#endif - -/**************************************************************************** - * Name: esp32_gpioirqenable - * - * Description: - * Enable the COPY interrupt for specified GPIO IRQ - * - ****************************************************************************/ - -#ifdef CONFIG_ESP32_GPIO_IRQ -void esp32_gpioirqenable(int irq, gpio_intrtype_t intrtype) -{ - uintptr_t regaddr; - uint32_t regval; - int pin; - int cpu = this_cpu(); - - DEBUGASSERT(irq >= ESP32_FIRST_GPIOIRQ && irq <= ESP32_LAST_GPIOIRQ); - - /* Convert the IRQ number to a pin number */ - - pin = ESP32_IRQ2PIN(irq); - - /* Get the address of the GPIO PIN register for this pin */ - - up_disable_irq(esp32_irq_gpio(cpu)); - - regaddr = GPIO_REG(pin); - regval = getreg32(regaddr); - regval &= ~(GPIO_PIN_INT_ENA_M | GPIO_PIN_INT_TYPE_M); - - /* Set the pin ENA field: - * - * Bit 0: APP CPU interrupt enable - * Bit 1: APP CPU non-maskable interrupt enable - * Bit 3: PRO CPU interrupt enable - * Bit 4: PRO CPU non-maskable interrupt enable - * Bit 5: SDIO's extent interrupt enable. - */ - -#ifdef CONFIG_SMP - if (cpu != 0) - { - /* APP_CPU */ - - regval |= ((1 << 0) << GPIO_PIN_INT_ENA_S); - } - else -#endif - { - /* PRO_CPU */ - - regval |= ((1 << 2) << GPIO_PIN_INT_ENA_S); - } - - regval |= (intrtype << GPIO_PIN_INT_TYPE_S); - putreg32(regval, regaddr); - - up_enable_irq(esp32_irq_gpio(cpu)); -} -#endif - -/**************************************************************************** - * Name: esp32_gpioirqdisable - * - * Description: - * Disable the interrupt for specified GPIO IRQ - * - ****************************************************************************/ - -#ifdef CONFIG_ESP32_GPIO_IRQ -void esp32_gpioirqdisable(int irq) -{ - uintptr_t regaddr; - uint32_t regval; - int pin; - int cpu = this_cpu(); - - DEBUGASSERT(irq >= ESP32_FIRST_GPIOIRQ && irq <= ESP32_LAST_GPIOIRQ); - - /* Convert the IRQ number to a pin number */ - - pin = ESP32_IRQ2PIN(irq); - - /* Get the address of the GPIO PIN register for this pin */ - - up_disable_irq(esp32_irq_gpio(cpu)); - - regaddr = GPIO_REG(pin); - regval = getreg32(regaddr); - regval &= ~(GPIO_PIN_INT_ENA_M | GPIO_PIN_INT_TYPE_M); - putreg32(regval, regaddr); - - up_enable_irq(esp32_irq_gpio(cpu)); -} -#endif - -/**************************************************************************** - * Name: esp32_gpio_matrix_in - * - * Description: - * Set gpio input to a signal - * NOTE: one gpio can input to several signals - * If gpio == 0x30, cancel input to the signal, input 0 to signal - * If gpio == 0x38, cancel input to the signal, input 1 to signal, - * for I2C pad - * - ****************************************************************************/ - -void esp32_gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv) -{ - uint32_t regaddr = GPIO_FUNC0_IN_SEL_CFG_REG + (signal_idx * 4); - uint32_t regval = (gpio << GPIO_FUNC0_IN_SEL_S); - - if (inv) - { - regval |= GPIO_FUNC0_IN_INV_SEL; - } - - if (gpio != 0x34) - { - regval |= GPIO_SIG0_IN_SEL; - } - - putreg32(regval, regaddr); -} - -/**************************************************************************** - * Name: esp32_gpio_matrix_out - * - * Description: - * Set signal output to gpio - * NOTE: one signal can output to several gpios - * If signal_idx == 0x100, cancel output put to the gpio - * - ****************************************************************************/ - -void esp32_gpio_matrix_out(uint32_t gpio, uint32_t signal_idx, bool out_inv, - bool oen_inv) -{ - uint32_t regaddr = GPIO_FUNC0_OUT_SEL_CFG_REG + (gpio * 4); - uint32_t regval = signal_idx << GPIO_FUNC0_OUT_SEL_S; - - if (gpio >= GPIO_PIN_COUNT) - { - return; - } - - if (gpio < 32) - { - putreg32((UINT32_C(1) << gpio), GPIO_ENABLE_W1TS_REG); - } - else - { - putreg32((UINT32_C(1) << (gpio - 32)), GPIO_ENABLE1_W1TS_REG); - } - - if (out_inv) - { - regval |= GPIO_FUNC0_OUT_INV_SEL; - } - - if (oen_inv) - { - regval |= GPIO_FUNC0_OEN_INV_SEL; - } - - putreg32(regval, regaddr); -} diff --git a/arch/xtensa/src/esp32/esp32_gpio.h b/arch/xtensa/src/esp32/esp32_gpio.h deleted file mode 100644 index a581bbac76973..0000000000000 --- a/arch/xtensa/src/esp32/esp32_gpio.h +++ /dev/null @@ -1,273 +0,0 @@ -/**************************************************************************** - * arch/xtensa/src/esp32/esp32_gpio.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_XTENSA_SRC_ESP32_ESP32_GPIO_H -#define __ARCH_XTENSA_SRC_ESP32_ESP32_GPIO_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define MATRIX_DETACH_OUT_SIG 0x100 /* Detach an OUTPUT signal */ -#define MATRIX_DETACH_IN_LOW_PIN 0x30 /* Detach non-inverted INPUT signal */ -#define MATRIX_DETACH_IN_LOW_HIGH 0x38 /* Detach inverted INPUT signal */ - -/* Bit-encoded input to esp32_configgpio() **********************************/ - -/* Encoded pin attributes used with esp32_configgpio() - * - * 8 7 6 5 4 3 2 1 0 - * -- -- -- -- -- -- -- -- -- - * FN FN FN OD PD PU F O I - */ - -#define PINMODE_SHIFT 0 -#define PINMODE_MASK (7 << PINMODE_SHIFT) -# define INPUT (1 << 0) -# define OUTPUT (1 << 1) -# define FUNCTION (1 << 2) - -#define PULLUP (1 << 3) -#define PULLDOWN (1 << 4) -#define OPEN_DRAIN (1 << 5) - -#define FUNCTION_SHIFT 6 -#define FUNCTION_MASK (7 << FUNCTION_SHIFT) -# define FUNCTION_1 (1 << FUNCTION_SHIFT) -# define FUNCTION_2 (2 << FUNCTION_SHIFT) -# define FUNCTION_3 (3 << FUNCTION_SHIFT) -# define FUNCTION_4 (4 << FUNCTION_SHIFT) -# define FUNCTION_5 (5 << FUNCTION_SHIFT) -# define FUNCTION_6 (6 << FUNCTION_SHIFT) - -#define DRIVE_SHIFT 9 -#define DRIVE_MASK (7 << DRIVE_SHIFT) -# define DRIVE_0 (1 << DRIVE_SHIFT) -# define DRIVE_1 (2 << DRIVE_SHIFT) -# define DRIVE_2 (3 << DRIVE_SHIFT) -# define DRIVE_3 (4 << DRIVE_SHIFT) - -#define INPUT_PULLUP (INPUT | PULLUP) -#define INPUT_PULLDOWN (INPUT | PULLDOWN) -#define OUTPUT_OPEN_DRAIN (OUTPUT | OPEN_DRAIN) -#define INPUT_FUNCTION (INPUT | FUNCTION) -# define INPUT_FUNCTION_1 (INPUT_FUNCTION | FUNCTION_1) -# define INPUT_FUNCTION_2 (INPUT_FUNCTION | FUNCTION_2) -# define INPUT_FUNCTION_3 (INPUT_FUNCTION | FUNCTION_3) -# define INPUT_FUNCTION_4 (INPUT_FUNCTION | FUNCTION_4) -# define INPUT_FUNCTION_5 (INPUT_FUNCTION | FUNCTION_5) -# define INPUT_FUNCTION_6 (INPUT_FUNCTION | FUNCTION_6) -#define OUTPUT_FUNCTION (OUTPUT | FUNCTION) -# define OUTPUT_FUNCTION_1 (OUTPUT_FUNCTION | FUNCTION_1) -# define OUTPUT_FUNCTION_2 (OUTPUT_FUNCTION | FUNCTION_2) -# define OUTPUT_FUNCTION_3 (OUTPUT_FUNCTION | FUNCTION_3) -# define OUTPUT_FUNCTION_4 (OUTPUT_FUNCTION | FUNCTION_4) -# define OUTPUT_FUNCTION_5 (OUTPUT_FUNCTION | FUNCTION_5) -# define OUTPUT_FUNCTION_6 (OUTPUT_FUNCTION | FUNCTION_6) - -/* Interrupt type used with esp32_gpioirqenable() */ - -#define DISABLED 0x00 -#define RISING 0x01 -#define FALLING 0x02 -#define CHANGE 0x03 -#define ONLOW 0x04 -#define ONHIGH 0x05 -#define ONLOW_WE 0x0c -#define ONHIGH_WE 0x0d - -/* Check whether it is a valid GPIO number */ - -#define GPIO_IS_VALID_GPIO(gpio_num) ((gpio_num >= 0) && \ - (((1ULL << (gpio_num)) & \ - SOC_GPIO_VALID_GPIO_MASK) != 0)) - -/* Check whether it can be a valid GPIO number of output mode */ - -#define GPIO_IS_VALID_OUTPUT_GPIO(gpio_num) \ - ((gpio_num >= 0) && \ - (((1ULL << (gpio_num)) & SOC_GPIO_VALID_OUTPUT_GPIO_MASK) != 0)) - -/* Check whether it can be a valid digital I/O pad */ - -#define GPIO_IS_VALID_DIGITAL_IO_PAD(gpio_num) \ - ((gpio_num >= 0) && \ - (((1ULL << (gpio_num)) & SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK) != 0)) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -/* Must be big enough to hold the above encodings */ - -typedef uint16_t gpio_pinattr_t; -typedef uint8_t gpio_intrtype_t; - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Inline Functions - ****************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32_gpioirqinitialize - * - * Description: - * Initialize logic to support a second level of interrupt decoding for - * GPIO pins. - * - ****************************************************************************/ - -#ifdef CONFIG_ESP32_GPIO_IRQ -void esp32_gpioirqinitialize(int c); -#else -# define esp32_gpioirqinitialize(c) -#endif - -/**************************************************************************** - * Name: esp32_configgpio - * - * Description: - * Configure a GPIO pin based on encoded pin attributes. - * - * Input Parameters: - * pin - GPIO pin to be configured - * attr - Attributes to be configured for the selected GPIO pin. - * The following attributes are accepted: - * - Direction (OUTPUT or INPUT) - * - Pull (PULLUP, PULLDOWN or OPENDRAIN) - * - Function (if not provided, assume function GPIO by default) - * - Drive strength (if not provided, assume DRIVE_2 by default) - * - * Returned Value: - * Zero (OK) on success, or -1 (ERROR) in case of failure. - * - ****************************************************************************/ - -int esp32_configgpio(int pin, gpio_pinattr_t attr); - -/**************************************************************************** - * Name: esp32_gpiowrite - * - * Description: - * Write one or zero to the selected GPIO pin - * - ****************************************************************************/ - -void esp32_gpiowrite(int pin, bool value); - -/**************************************************************************** - * Name: esp32_gpioread - * - * Description: - * Read one or zero from the selected GPIO pin - * - ****************************************************************************/ - -bool esp32_gpioread(int pin); - -/**************************************************************************** - * Name: esp32_gpioirqenable - * - * Description: - * Enable the interrupt for specified GPIO IRQ - * - ****************************************************************************/ - -#ifdef CONFIG_ESP32_GPIO_IRQ -void esp32_gpioirqenable(int irq, gpio_intrtype_t intrtype); -#else -# define esp32_gpioirqenable(irq,intrtype) -#endif - -/**************************************************************************** - * Name: esp32_gpioirqdisable - * - * Description: - * Disable the interrupt for specified GPIO IRQ - * - ****************************************************************************/ - -#ifdef CONFIG_ESP32_GPIO_IRQ -void esp32_gpioirqdisable(int irq); -#else -# define esp32_gpioirqdisable(irq) -#endif - -/**************************************************************************** - * Name: esp32_gpio_matrix_in - * - * Description: - * Set gpio input to a signal - * NOTE: one gpio can input to several signals - * If gpio == 0x30, cancel input to the signal, input 0 to signal - * If gpio == 0x38, cancel input to the signal, input 1 to signal, - * for I2C pad - * - ****************************************************************************/ - -void esp32_gpio_matrix_in(uint32_t gpio, uint32_t signal_idx, bool inv); - -/**************************************************************************** - * Name: esp32_gpio_matrix_out - * - * Description: - * Set signal output to gpio - * NOTE: one signal can output to several gpios - * If signal_idx == 0x100, cancel output put to the gpio - * - ****************************************************************************/ - -void esp32_gpio_matrix_out(uint32_t gpio, uint32_t signal_idx, bool out_inv, - bool oen_inv); - -#ifdef __cplusplus -} -#endif -#undef EXTERN - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_XTENSA_SRC_ESP32_ESP32_GPIO_H */ diff --git a/arch/xtensa/src/esp32/esp32_i2c.c b/arch/xtensa/src/esp32/esp32_i2c.c index 59040c07e7050..0238d391a2379 100644 --- a/arch/xtensa/src/esp32/esp32_i2c.c +++ b/arch/xtensa/src/esp32/esp32_i2c.c @@ -47,8 +47,8 @@ #include #include "esp32_i2c.h" -#include "esp32_gpio.h" -#include "esp32_irq.h" +#include "esp_gpio.h" +#include "esp_irq.h" #include "xtensa.h" #include "hardware/esp32_gpio_sigmap.h" @@ -648,22 +648,19 @@ static void esp32_i2c_init(struct esp32_i2c_priv_s *priv) { const struct esp32_i2c_config_s *config = priv->config; - esp32_gpiowrite(config->scl_pin, 1); - esp32_gpiowrite(config->sda_pin, 1); + esp_gpiowrite(config->scl_pin, 1); + esp_gpiowrite(config->sda_pin, 1); - esp32_configgpio(config->scl_pin, INPUT | - OUTPUT | - OPEN_DRAIN | - FUNCTION_3); - esp32_gpio_matrix_out(config->scl_pin, config->scl_outsig, 0, 0); - esp32_gpio_matrix_in(config->scl_pin, config->scl_insig, 0); + esp_configgpio(config->scl_pin, INPUT | OPEN_DRAIN | FUNCTION_3); + esp_gpio_matrix_out(config->scl_pin, config->scl_outsig, 0, 0); + esp_gpio_matrix_in(config->scl_pin, config->scl_insig, 0); - esp32_configgpio(config->sda_pin, INPUT | + esp_configgpio(config->sda_pin, INPUT | OUTPUT | OPEN_DRAIN | FUNCTION_3); - esp32_gpio_matrix_out(config->sda_pin, config->sda_outsig, 0, 0); - esp32_gpio_matrix_in(config->sda_pin, config->sda_insig, 0); + esp_gpio_matrix_out(config->sda_pin, config->sda_outsig, 0, 0); + esp_gpio_matrix_in(config->sda_pin, config->sda_insig, 0); modifyreg32(DPORT_PERIP_CLK_EN_REG, 0, config->clk_bit); modifyreg32(DPORT_PERIP_RST_EN_REG, config->rst_bit, 0); @@ -1008,19 +1005,19 @@ static int esp32_i2c_clear_bus(struct esp32_i2c_priv_s *priv) /* Use GPIO configuration to un-wedge the bus */ - esp32_configgpio(config->scl_pin, INPUT_PULLUP | OUTPUT_OPEN_DRAIN); - esp32_gpio_matrix_out(config->scl_pin, SIG_GPIO_OUT_IDX, 0, 0); - esp32_configgpio(config->sda_pin, INPUT_PULLUP | OUTPUT_OPEN_DRAIN); - esp32_gpio_matrix_out(config->sda_pin, SIG_GPIO_OUT_IDX, 0, 0); + esp_configgpio(config->scl_pin, INPUT_PULLUP | OUTPUT_OPEN_DRAIN); + esp_gpio_matrix_out(config->scl_pin, SIG_GPIO_OUT_IDX, 0, 0); + esp_configgpio(config->sda_pin, INPUT_PULLUP | OUTPUT_OPEN_DRAIN); + esp_gpio_matrix_out(config->sda_pin, SIG_GPIO_OUT_IDX, 0, 0); /* Set SDA to high */ - esp32_gpiowrite(config->sda_pin, 1); + esp_gpiowrite(config->sda_pin, 1); /* Clock the bus until any slaves currently driving it let it go. */ clock_count = 0; - while (!esp32_gpioread(config->sda_pin)) + while (!esp_gpioread(config->sda_pin)) { /* Give up if we have tried too hard */ @@ -1036,7 +1033,7 @@ static int esp32_i2c_clear_bus(struct esp32_i2c_priv_s *priv) */ stretch_count = 0; - while (!esp32_gpioread(config->scl_pin)) + while (!esp_gpioread(config->scl_pin)) { /* Give up if we have tried too hard */ @@ -1051,12 +1048,12 @@ static int esp32_i2c_clear_bus(struct esp32_i2c_priv_s *priv) /* Drive SCL low */ - esp32_gpiowrite(config->scl_pin, 0); + esp_gpiowrite(config->scl_pin, 0); up_udelay(10); /* Drive SCL high again */ - esp32_gpiowrite(config->scl_pin, 1); + esp_gpiowrite(config->scl_pin, 1); up_udelay(10); } @@ -1064,13 +1061,13 @@ static int esp32_i2c_clear_bus(struct esp32_i2c_priv_s *priv) * state machines. */ - esp32_gpiowrite(config->sda_pin, 0); + esp_gpiowrite(config->sda_pin, 0); up_udelay(10); - esp32_gpiowrite(config->scl_pin, 0); + esp_gpiowrite(config->scl_pin, 0); up_udelay(10); - esp32_gpiowrite(config->scl_pin, 1); + esp_gpiowrite(config->scl_pin, 1); up_udelay(10); - esp32_gpiowrite(config->sda_pin, 1); + esp_gpiowrite(config->sda_pin, 1); up_udelay(10); ret = OK; @@ -1501,8 +1498,11 @@ struct i2c_master_s *esp32_i2cbus_initialize(int port) /* Set up to receive peripheral interrupts on the current CPU */ priv->cpu = this_cpu(); - priv->cpuint = esp32_setup_irq(priv->cpu, config->periph, - 1, ESP32_CPUINT_LEVEL); + priv->cpuint = esp_setup_irq(config->periph, + 1, + ESP_IRQ_TRIGGER_LEVEL, + esp32_i2c_irq, + priv); if (priv->cpuint < 0) { /* Failed to allocate a CPU interrupt of this type */ @@ -1513,16 +1513,6 @@ struct i2c_master_s *esp32_i2cbus_initialize(int port) return NULL; } - ret = irq_attach(config->irq, esp32_i2c_irq, priv); - if (ret != OK) - { - esp32_teardown_irq(priv->cpu, config->periph, priv->cpuint); - priv->refs--; - - nxmutex_unlock(&priv->lock); - return NULL; - } - up_enable_irq(config->irq); #endif @@ -1560,7 +1550,7 @@ int esp32_i2cbus_uninitialize(struct i2c_master_s *dev) #ifndef CONFIG_I2C_POLLED up_disable_irq(priv->config->irq); - esp32_teardown_irq(priv->cpu, priv->config->periph, priv->cpuint); + esp_teardown_irq(priv->config->periph, priv->cpuint); #endif esp32_i2c_deinit(priv); diff --git a/arch/xtensa/src/esp32/esp32_i2s.c b/arch/xtensa/src/esp32/esp32_i2s.c index a52f57a6896f9..c9d93fde92cbb 100644 --- a/arch/xtensa/src/esp32/esp32_i2s.c +++ b/arch/xtensa/src/esp32/esp32_i2s.c @@ -52,8 +52,8 @@ #include #include "esp32_i2s.h" -#include "esp32_gpio.h" -#include "esp32_irq.h" +#include "esp_gpio.h" +#include "esp_irq.h" #include "esp32_dma.h" #include "xtensa.h" @@ -1467,9 +1467,9 @@ static void i2s_configure(struct esp32_i2s_s *priv) if (priv->config->dout_pin != I2S_GPIO_UNUSED) { - esp32_gpiowrite(priv->config->dout_pin, 1); - esp32_configgpio(priv->config->dout_pin, OUTPUT_FUNCTION_3); - esp32_gpio_matrix_out(priv->config->dout_pin, + esp_gpiowrite(priv->config->dout_pin, 1); + esp_configgpio(priv->config->dout_pin, OUTPUT_FUNCTION_3); + esp_gpio_matrix_out(priv->config->dout_pin, priv->config->dout_outsig, 0, 0); } @@ -1477,8 +1477,8 @@ static void i2s_configure(struct esp32_i2s_s *priv) if (priv->config->din_pin != I2S_GPIO_UNUSED) { - esp32_configgpio(priv->config->din_pin, INPUT_FUNCTION_3); - esp32_gpio_matrix_in(priv->config->din_pin, + esp_configgpio(priv->config->din_pin, INPUT_FUNCTION_3); + esp_gpio_matrix_in(priv->config->din_pin, priv->config->din_insig, 0); } @@ -1488,14 +1488,14 @@ static void i2s_configure(struct esp32_i2s_s *priv) { /* For "tx + slave" mode, select TX signal index for ws and bck */ - esp32_gpiowrite(priv->config->ws_pin, 1); - esp32_configgpio(priv->config->ws_pin, INPUT_FUNCTION_3); - esp32_gpio_matrix_in(priv->config->ws_pin, + esp_gpiowrite(priv->config->ws_pin, 1); + esp_configgpio(priv->config->ws_pin, INPUT_FUNCTION_3); + esp_gpio_matrix_in(priv->config->ws_pin, priv->config->ws_out_insig, 0); - esp32_gpiowrite(priv->config->bclk_pin, 1); - esp32_configgpio(priv->config->bclk_pin, INPUT_FUNCTION_3); - esp32_gpio_matrix_in(priv->config->bclk_pin, + esp_gpiowrite(priv->config->bclk_pin, 1); + esp_configgpio(priv->config->bclk_pin, INPUT_FUNCTION_3); + esp_gpio_matrix_in(priv->config->bclk_pin, priv->config->bclk_out_insig, 0); } else @@ -1504,14 +1504,14 @@ static void i2s_configure(struct esp32_i2s_s *priv) * index for ws and bck. */ - esp32_gpiowrite(priv->config->ws_pin, 1); - esp32_configgpio(priv->config->ws_pin, INPUT_FUNCTION_3); - esp32_gpio_matrix_in(priv->config->ws_pin, + esp_gpiowrite(priv->config->ws_pin, 1); + esp_configgpio(priv->config->ws_pin, INPUT_FUNCTION_3); + esp_gpio_matrix_in(priv->config->ws_pin, priv->config->ws_in_insig, 0); - esp32_gpiowrite(priv->config->bclk_pin, 1); - esp32_configgpio(priv->config->bclk_pin, INPUT_FUNCTION_3); - esp32_gpio_matrix_in(priv->config->bclk_pin, + esp_gpiowrite(priv->config->bclk_pin, 1); + esp_configgpio(priv->config->bclk_pin, INPUT_FUNCTION_3); + esp_gpio_matrix_in(priv->config->bclk_pin, priv->config->bclk_in_insig, 0); } } @@ -1528,8 +1528,8 @@ static void i2s_configure(struct esp32_i2s_s *priv) i2sinfo("Configuring GPIO%" PRIu8 " to output master clock\n", priv->config->mclk_pin); - esp32_configgpio(priv->config->mclk_pin, OUTPUT_FUNCTION_2); - esp32_gpio_matrix_out(priv->config->mclk_pin, + esp_configgpio(priv->config->mclk_pin, OUTPUT_FUNCTION_2); + esp_gpio_matrix_out(priv->config->mclk_pin, SIG_GPIO_OUT_IDX, 0, 0); if (priv->config->mclk_pin == 0) @@ -1553,14 +1553,14 @@ static void i2s_configure(struct esp32_i2s_s *priv) { /* For "rx + master" mode, select RX signal index for ws and bck */ - esp32_gpiowrite(priv->config->ws_pin, 1); - esp32_configgpio(priv->config->ws_pin, OUTPUT_FUNCTION_3); - esp32_gpio_matrix_out(priv->config->ws_pin, + esp_gpiowrite(priv->config->ws_pin, 1); + esp_configgpio(priv->config->ws_pin, OUTPUT_FUNCTION_3); + esp_gpio_matrix_out(priv->config->ws_pin, priv->config->ws_in_outsig, 0, 0); - esp32_gpiowrite(priv->config->bclk_pin, 1); - esp32_configgpio(priv->config->bclk_pin, OUTPUT_FUNCTION_3); - esp32_gpio_matrix_out(priv->config->bclk_pin, + esp_gpiowrite(priv->config->bclk_pin, 1); + esp_configgpio(priv->config->bclk_pin, OUTPUT_FUNCTION_3); + esp_gpio_matrix_out(priv->config->bclk_pin, priv->config->bclk_in_outsig, 0, 0); } else @@ -1569,14 +1569,14 @@ static void i2s_configure(struct esp32_i2s_s *priv) * index for ws and bck. */ - esp32_gpiowrite(priv->config->ws_pin, 1); - esp32_configgpio(priv->config->ws_pin, OUTPUT_FUNCTION_3); - esp32_gpio_matrix_out(priv->config->ws_pin, + esp_gpiowrite(priv->config->ws_pin, 1); + esp_configgpio(priv->config->ws_pin, OUTPUT_FUNCTION_3); + esp_gpio_matrix_out(priv->config->ws_pin, priv->config->ws_out_outsig, 0, 0); - esp32_gpiowrite(priv->config->bclk_pin, 1); - esp32_configgpio(priv->config->bclk_pin, OUTPUT_FUNCTION_3); - esp32_gpio_matrix_out(priv->config->bclk_pin, + esp_gpiowrite(priv->config->bclk_pin, 1); + esp_configgpio(priv->config->bclk_pin, OUTPUT_FUNCTION_3); + esp_gpio_matrix_out(priv->config->bclk_pin, priv->config->bclk_out_outsig, 0, 0); } } @@ -3004,24 +3004,17 @@ static int i2s_dma_setup(struct esp32_i2s_s *priv) /* Set up to receive peripheral interrupts on the current CPU */ priv->cpu = this_cpu(); - priv->cpuint = esp32_setup_irq(priv->cpu, priv->config->periph, - 1, ESP32_CPUINT_LEVEL); + priv->cpuint = esp_setup_irq(priv->config->periph, + 1, + ESP_IRQ_TRIGGER_LEVEL, + i2s_interrupt, + priv); if (priv->cpuint < 0) { i2serr("Failed to allocate a CPU interrupt.\n"); return priv->cpuint; } - ret = irq_attach(priv->config->irq, i2s_interrupt, priv); - if (ret != OK) - { - i2serr("Couldn't attach IRQ to handler.\n"); - esp32_teardown_irq(priv->cpu, - priv->config->periph, - priv->cpuint); - return ret; - } - return OK; } diff --git a/arch/xtensa/src/esp32/esp32_idle.c b/arch/xtensa/src/esp32/esp32_idle.c index 45769863f307e..2757d2d767d8c 100644 --- a/arch/xtensa/src/esp32/esp32_idle.c +++ b/arch/xtensa/src/esp32/esp32_idle.c @@ -35,17 +35,22 @@ #include #include -#include "esp32_pm.h" +#include "espressif/esp_pm.h" #include "xtensa.h" -#ifdef CONFIG_ESP32_RT_TIMER -#include "esp32_rt_timer.h" +#ifdef CONFIG_ESPRESSIF_HR_TIMER +#include "esp_hr_timer.h" #endif #ifdef CONFIG_SCHED_TICKLESS #include "esp32_tickless.h" #endif +#ifdef CONFIG_ESPRESSIF_AUTO_SLEEP +#include "esp_private/pm_impl.h" +#include "platform/os.h" +#endif + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -113,58 +118,11 @@ static spinlock_t g_esp32_idle_lock = SP_UNLOCKED; #ifdef CONFIG_PM static void esp32_idlepm(void) { - irqstate_t flags; - #ifdef CONFIG_ESP32_AUTO_SLEEP - flags = spin_lock_irqsave(&g_esp32_idle_lock); - if (esp32_pm_lockstatus() == 0) - { - uint64_t os_start_us; - uint64_t os_end_us; - uint64_t os_step_us; - uint64_t hw_start_us; - uint64_t hw_end_us; - uint64_t hw_step_us; - uint64_t rtc_diff_us; - struct timespec ts; - uint64_t os_idle_us = up_get_idletime(); - uint64_t hw_idle_us = rt_timer_get_alarm(); - uint64_t sleep_us = MIN(os_idle_us, hw_idle_us); - if (sleep_us > EXPECTED_IDLE_TIME_US) - { - sleep_us -= EARLY_WAKEUP_US; - - esp32_sleep_enable_timer_wakeup(sleep_us); - - up_timer_gettime(&ts); - os_start_us = (ts.tv_sec * USEC_PER_SEC + - ts.tv_nsec / NSEC_PER_USEC); - hw_start_us = rt_timer_time_us(); - - esp32_light_sleep_start(&rtc_diff_us); - - hw_end_us = rt_timer_time_us(); - up_timer_gettime(&ts); - os_end_us = (ts.tv_sec * USEC_PER_SEC + - ts.tv_nsec / NSEC_PER_USEC); - hw_step_us = rtc_diff_us - (hw_end_us - hw_start_us); - os_step_us = rtc_diff_us - (os_end_us - os_start_us); - DEBUGASSERT(hw_step_us > 0); - DEBUGASSERT(os_step_us > 0); - - /* Adjust current RT timer by a certain value. */ - - rt_timer_calibration(hw_step_us); - - /* Adjust system time by a certain value. */ - - up_step_idletime((uint32_t)os_step_us); - } - } - - spin_unlock_irqrestore(&g_esp32_idle_lock, flags); + esp_os_application_sleep(); #else /* CONFIG_ESP32_AUTO_SLEEP */ static enum pm_state_e oldstate = PM_NORMAL; + irqstate_t flags; enum pm_state_e newstate; int ret; int count; @@ -226,8 +184,8 @@ static void esp32_idlepm(void) { /* Enter Force-sleep mode */ - esp32_pmstandby(CONFIG_PM_ALARM_SEC * 1000000 + - CONFIG_PM_ALARM_NSEC / 1000); + esp_pmstandby(CONFIG_PM_ALARM_SEC * 1000000 + + CONFIG_PM_ALARM_NSEC / 1000); } break; @@ -235,8 +193,8 @@ static void esp32_idlepm(void) { /* Enter Deep-sleep mode */ - esp32_pmsleep(CONFIG_PM_SLEEP_WAKEUP_SEC * 1000000 + - CONFIG_PM_SLEEP_WAKEUP_NSEC / 1000); + esp_pmsleep(CONFIG_PM_SLEEP_WAKEUP_SEC * 1000000 + + CONFIG_PM_SLEEP_WAKEUP_NSEC / 1000); } default: @@ -289,8 +247,13 @@ void up_idle(void) */ BEGIN_IDLE(); -#if XCHAL_HAVE_INTERRUPTS +#ifdef CONFIG_ESPRESSIF_AUTO_SLEEP + esp_pm_impl_idle_hook(); + esp_pm_impl_waiti(); +#else +# if XCHAL_HAVE_INTERRUPTS __asm__ __volatile__ ("waiti 0"); +# endif #endif END_IDLE(); diff --git a/arch/xtensa/src/esp32/esp32_irq.c b/arch/xtensa/src/esp32/esp32_irq.c deleted file mode 100644 index ec80d2c0bc4a2..0000000000000 --- a/arch/xtensa/src/esp32/esp32_irq.c +++ /dev/null @@ -1,1335 +0,0 @@ -/**************************************************************************** - * arch/xtensa/src/esp32/esp32_irq.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include "xtensa.h" - -#include "hardware/esp32_dport.h" - -#include "esp32_smp.h" -#include "esp32_gpio.h" -#include "esp32_rtc_gpio.h" - -#include "esp32_irq.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Interrupt stack definitions for SMP */ - -#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 15 -# define INTSTACK_ALLOC (CONFIG_SMP_NCPUS * INTSTACK_SIZE) -#endif - -/* IRQ to CPU and CPU interrupts mapping: - * - * Encoding: CIIIIIII - * C: CPU that enabled the interrupt (0 = PRO, 1 = APP). - * I: Associated CPU interrupt. - */ - -#define IRQ_UNMAPPED 0xff -#define IRQ_GETCPU(m) (((m) & 0x80) >> 0x07) -#define IRQ_GETCPUINT(m) ((m) & 0x7f) -#define IRQ_MKMAP(c, i) (((c) << 0x07) | (i)) - -/* CPU interrupts to peripheral mapping: - * - * Encoding: EPPPPPPP - * E: CPU interrupt status (0 = Disabled, 1 = Enabled). - * P: Attached peripheral. - */ - -#define CPUINT_UNASSIGNED 0x7f -#define CPUINT_GETEN(m) (((m) & 0x80) >> 0x07) -#define CPUINT_GETIRQ(m) ((m) & 0x7f) -#define CPUINT_ASSIGN(c) (((c) & 0x7f) | 0x80) -#define CPUINT_DISABLE(m) ((m) & 0x7f) -#define CPUINT_ENABLE(m) ((m) | 0x80) - -/* Mapping Peripheral IDs to map register addresses. */ - -#define DPORT_PRO_MAP_REGADDR(n) (DR_REG_DPORT_BASE + 0x104 + ((n) << 2)) -#define DPORT_APP_MAP_REGADDR(n) (DR_REG_DPORT_BASE + 0x218 + ((n) << 2)) - -/* CPU interrupts can be detached from any peripheral source by setting the - * map register to an internal CPU interrupt (6, 7, 11, 15, 16, or 29). - */ - -#define NO_CPUINT ESP32_CPUINT_TIMER0 - -/* Priority range is 1-5 */ - -#define ESP32_MIN_PRIORITY 1 -#define ESP32_MAX_PRIORITY 5 -#define ESP32_PRIO_INDEX(p) ((p) - ESP32_MIN_PRIORITY) - -#ifdef CONFIG_ESPRESSIF_WIFI -# define ESP32_WIFI_RESERVE_INT (1 << ESP32_CPUINT_MAC) -#else -# define ESP32_WIFI_RESERVE_INT 0 -#endif - -#ifdef CONFIG_ESPRESSIF_BLE -# define ESP32_BLE_RESERVE_INT ((1 << ESP32_PERIPH_BT_BB_NMI) | \ - (1 << ESP32_PERIPH_RWBLE_IRQ) | \ - (1 << ESP32_PERIPH_RWBT_NMI)) -#else -# define ESP32_BLE_RESERVE_INT 0 -#endif - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 15 -/* In the SMP configuration, we will need custom interrupt stacks. - * These definitions provide the aligned stack allocations. - */ - -static uint32_t g_intstackalloc[INTSTACK_ALLOC >> 2]; - -/* These definitions provide the "top" of the push-down stacks. */ - -uintptr_t g_cpu_intstack_top[CONFIG_SMP_NCPUS] = -{ - (uintptr_t)g_intstackalloc + INTSTACK_SIZE, -#if CONFIG_SMP_NCPUS > 1 - (uintptr_t)g_intstackalloc + (2 * INTSTACK_SIZE), -#endif /* CONFIG_SMP_NCPUS > 1 */ -}; -#endif /* defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 15 */ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Maps a CPU interrupt to the IRQ of the attached peripheral interrupt */ - -static uint8_t g_cpu0_intmap[ESP32_NCPUINTS]; -#ifdef CONFIG_SMP -static uint8_t g_cpu1_intmap[ESP32_NCPUINTS]; -#endif - -static volatile uint8_t g_irqmap[NR_IRQS]; - -/* g_intenable[] is a shadow copy of the per-CPU INTENABLE register - * content. - */ - -static uint32_t g_intenable[CONFIG_SMP_NCPUS]; - -/* g_non_iram_int_mask[] is a bitmask of the interrupts that should be - * disabled during a SPI flash operation. Non-IRAM interrupts should always - * be disabled, but interrupts place on IRAM are able to run during a SPI - * flash operation. - */ - -static uint32_t g_non_iram_int_mask[CONFIG_SMP_NCPUS]; - -/* g_non_iram_int_disabled[] keeps track of the interrupts disabled during - * a SPI flash operation. - */ - -static uint32_t g_non_iram_int_disabled[CONFIG_SMP_NCPUS]; - -/* Per-CPU flag to indicate that non-IRAM interrupts were disabled */ - -static bool g_non_iram_int_disabled_flag[CONFIG_SMP_NCPUS]; - -/* Bitsets for free, unallocated CPU interrupts available to peripheral - * devices. - */ - -static uint32_t g_cpu0_freeints = ESP32_CPUINT_PERIPHSET & - ~(ESP32_WIFI_RESERVE_INT | - ESP32_BLE_RESERVE_INT); - -#ifdef CONFIG_SMP -static uint32_t g_cpu1_freeints = ESP32_CPUINT_PERIPHSET; -#endif - -/* Bitsets for each interrupt priority 1-5 */ - -static const uint32_t g_priority[5] = -{ - ESP32_INTPRI1_MASK, - ESP32_INTPRI2_MASK, - ESP32_INTPRI3_MASK, - ESP32_INTPRI4_MASK, - ESP32_INTPRI5_MASK -}; - -#ifdef CONFIG_ESP32_IRAM_ISR_DEBUG -/* The g_iram_count keeps track of how many times such an IRQ ran when the - * non-IRAM interrupts were disabled. - */ - -static uint64_t g_iram_count[NR_IRQS]; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32_irq_dump - * - * Description: - * Dump some interesting NVIC registers - * - ****************************************************************************/ - -#if defined(CONFIG_DEBUG_IRQ_INFO) -static void esp32_irq_dump(const char *msg, int irq) -{ - irqstate_t flags; - - flags = enter_critical_section(); -#warning Missing logic - leave_critical_section(flags); -} -#else -# define esp32_irq_dump(msg, irq) -#endif - -/**************************************************************************** - * Name: xtensa_attach_fromcpu1_interrupt - ****************************************************************************/ - -#ifdef CONFIG_SMP -static inline void xtensa_attach_fromcpu1_interrupt(void) -{ - int cpuint; - - /* Connect all CPU peripheral source to allocated CPU interrupt */ - - cpuint = esp32_setup_irq(0, ESP32_PERIPH_CPU_CPU1, 1, ESP32_CPUINT_LEVEL); - DEBUGASSERT(cpuint >= 0); - - /* Attach the inter-CPU interrupt. */ - - irq_attach(ESP32_IRQ_CPU_CPU1, (xcpt_t)esp32_fromcpu1_interrupt, NULL); - - /* Enable the inter 0 CPU interrupt. */ - - up_enable_irq(ESP32_IRQ_CPU_CPU1); -} -#endif - -/**************************************************************************** - * Name: esp32_intinfo - * - * Description: - * Return the CPU interrupt map of the given CPU and the register map - * of the given peripheral. - * - ****************************************************************************/ - -static void esp32_intinfo(int cpu, int periphid, - uintptr_t *regaddr, uint8_t **intmap) -{ -#ifdef CONFIG_SMP - DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS); - - if (cpu != 0) - { - *regaddr = DPORT_APP_MAP_REGADDR(periphid); - *intmap = g_cpu1_intmap; - } - else -#endif - { - *regaddr = DPORT_PRO_MAP_REGADDR(periphid); - *intmap = g_cpu0_intmap; - } -} - -/**************************************************************************** - * Name: esp32_getcpuint - * - * Description: - * Get a free CPU interrupt for a peripheral device. This function will - * not ignore all of the pre-allocated CPU interrupts for internal - * devices. - * - * Input Parameters: - * cpu - CPU core to query for CPU interrupt candidates - * intmask - mask of candidate CPU interrupts. The CPU interrupt will be - * be allocated from free interrupts within this set - * - * Returned Value: - * On success, a CPU interrupt number is returned. - * A negated errno is returned on failure. - * - ****************************************************************************/ - -static int esp32_getcpuint(int cpu, uint32_t intmask) -{ - uint32_t *freeints; - uint32_t bitmask; - uint32_t intset; - int cpuint; - int ret = -ENOMEM; - - /* Check if there are CPU interrupts with the requested properties - * available. - */ - -#ifdef CONFIG_SMP - if (cpu != 0) - { - freeints = &g_cpu1_freeints; - } - else -#endif - { - freeints = &g_cpu0_freeints; - } - - intset = *freeints & intmask; - if (intset != 0) - { - /* Skip over initial unavailable CPU interrupts quickly in groups - * of 8 interrupt. - */ - - for (cpuint = 0, bitmask = 0xff; - cpuint <= ESP32_CPUINT_MAX && (intset & bitmask) == 0; - cpuint += 8, bitmask <<= 8); - - /* Search for an unallocated CPU interrupt number in the remaining - * intset. - */ - - for (; cpuint <= ESP32_CPUINT_MAX; cpuint++) - { - /* If the bit corresponding to the CPU interrupt is '1', then - * that CPU interrupt is available. - */ - - bitmask = 1ul << cpuint; - if ((intset & bitmask) != 0) - { - /* Got it! */ - - *freeints &= ~bitmask; - ret = cpuint; - break; - } - } - } - - /* Enable the CPU interrupt now. The interrupt is still not attached - * to any peripheral and thus has no effect. - */ - - if (ret >= 0) - { - xtensa_enable_cpuint(&g_intenable[cpu], ret); - } - - return ret; -} - -/**************************************************************************** - * Name: esp32_alloc_cpuint - * - * Description: - * Allocate a level CPU interrupt - * - * Input Parameters: - * cpu - CPU core to query for CPU interrupt candidates - * priority - Priority of the CPU interrupt (1-5) - * type - Interrupt type (level or edge). - * - * Returned Value: - * On success, the allocated CPU interrupt number is returned. - * A negated errno is returned on failure. The only possible failure - * is that all CPU interrupts of the requested type have already been - * allocated. - * - ****************************************************************************/ - -static int esp32_alloc_cpuint(int cpu, int priority, int type) -{ - uint32_t mask; - - DEBUGASSERT(priority >= ESP32_MIN_PRIORITY && - priority <= ESP32_MAX_PRIORITY); - DEBUGASSERT(type & ESP32_CPUINT_TRIGGER_MASK); - - if ((type & (ESP32_CPUINT_LEVEL | ESP32_CPUINT_EDGE)) == 0) - { - irqerr("Either the level or edege-triggered flag must be selected"); - return -EINVAL; - } - - if ((type & ESP32_CPUINT_LEVEL) != 0) - { - /* Check if there are any level CPU interrupts available at the - * requested interrupt priority. - */ - - mask = g_priority[ESP32_PRIO_INDEX(priority)] & ESP32_CPUINT_LEVELSET; - } - else - { - /* Check if there are any edge CPU interrupts available at the - * requested interrupt priority. - */ - - mask = g_priority[ESP32_PRIO_INDEX(priority)] & ESP32_CPUINT_EDGESET; - } - - return esp32_getcpuint(cpu, mask); -} - -/**************************************************************************** - * Name: esp32_free_cpuint - * - * Description: - * Free a previously allocated CPU interrupt - * - * Input Parameters: - * The CPU interrupt number to be freed - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void esp32_free_cpuint(int cpuint) -{ - uint32_t *freeints; - uint32_t bitmask; - - DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32_CPUINT_MAX); - - /* Mark the CPU interrupt as available */ - - bitmask = 1ul << cpuint; - -#ifdef CONFIG_SMP - if (this_cpu() != 0) - { - freeints = &g_cpu1_freeints; - } - else -#endif - { - freeints = &g_cpu0_freeints; - } - - DEBUGASSERT((*freeints & bitmask) == 0); - *freeints |= bitmask; -} - -#ifdef CONFIG_ESP32_IRAM_ISR_DEBUG - -/**************************************************************************** - * Name: esp32_iram_interrupt_record - * - * Description: - * This function keeps track of the IRQs that ran when non-IRAM interrupts - * are disabled and enables debugging of the IRAM-enabled interrupts. - * - * Input Parameters: - * irq - The IRQ associated with a CPU interrupt - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp32_irq_iram_interrupt_record(int irq) -{ - irqstate_t flags = enter_critical_section(); - - g_iram_count[irq]++; - - leave_critical_section(flags); -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_irqinitialize - ****************************************************************************/ - -void up_irqinitialize(void) -{ - int i; - - /* All CPU ints are non-IRAM interrupts at the beginning and should be - * disabled during a SPI flash operation - */ - - for (i = 0; i < CONFIG_SMP_NCPUS; i++) - { - g_non_iram_int_mask[i] = UINT32_MAX; - } - - for (i = 0; i < NR_IRQS; i++) - { - g_irqmap[i] = IRQ_UNMAPPED; - } - - /* Hard code special cases. */ - - g_irqmap[XTENSA_IRQ_TIMER0] = IRQ_MKMAP(0, ESP32_CPUINT_TIMER0); - g_irqmap[XTENSA_IRQ_SWINT] = IRQ_MKMAP(0, ESP32_CPUINT_SOFTWARE1); - g_irqmap[XTENSA_IRQ_SWINT] = IRQ_MKMAP(1, ESP32_CPUINT_SOFTWARE1); - -#ifdef CONFIG_ESPRESSIF_WIFI - g_irqmap[ESP32_IRQ_MAC] = IRQ_MKMAP(0, ESP32_CPUINT_MAC); -#endif - -#ifdef CONFIG_ESPRESSIF_BLE - g_irqmap[ESP32_IRQ_BT_BB_NMI] = IRQ_MKMAP(0, ESP32_PERIPH_BT_BB_NMI); - g_irqmap[ESP32_IRQ_RWBT_NMI] = IRQ_MKMAP(0, ESP32_PERIPH_RWBT_NMI); - g_irqmap[ESP32_IRQ_RWBLE_IRQ] = IRQ_MKMAP(0, ESP32_PERIPH_RWBLE_IRQ); -#endif - - /* Initialize CPU interrupts */ - - esp32_cpuint_initialize(); - - /* Reserve CPU0 interrupt for some special drivers */ - -#ifdef CONFIG_ESPRESSIF_WIFI - g_cpu0_intmap[ESP32_CPUINT_MAC] = CPUINT_ASSIGN(ESP32_IRQ_MAC); - xtensa_enable_cpuint(&g_intenable[0], ESP32_CPUINT_MAC); -#endif - -#ifdef CONFIG_ESPRESSIF_BLE - g_cpu0_intmap[ESP32_PERIPH_BT_BB_NMI] = CPUINT_ASSIGN(ESP32_IRQ_BT_BB_NMI); - g_cpu0_intmap[ESP32_PERIPH_RWBT_NMI] = CPUINT_ASSIGN(ESP32_IRQ_RWBT_NMI); - g_cpu0_intmap[ESP32_PERIPH_RWBLE_IRQ] = CPUINT_ASSIGN(ESP32_IRQ_RWBLE_IRQ); - xtensa_enable_cpuint(&g_intenable[0], ESP32_PERIPH_BT_BB_NMI); - xtensa_enable_cpuint(&g_intenable[0], ESP32_PERIPH_RWBT_NMI); - xtensa_enable_cpuint(&g_intenable[0], ESP32_PERIPH_RWBLE_IRQ); -#endif - - /* Attach and enable internal interrupts */ - -#ifdef CONFIG_SMP - /* Attach and enable the inter-CPU interrupt */ - - xtensa_attach_fromcpu1_interrupt(); -#endif - - esp32_irq_dump("initial", NR_IRQS); - -#ifdef CONFIG_ESP32_GPIO_IRQ - /* Initialize GPIO interrupt support */ - - esp32_gpioirqinitialize(0); -#endif - - /* Initialize RTCIO interrupt support */ - - esp32_rtcioirqinitialize(); - -#ifndef CONFIG_SUPPRESS_INTERRUPTS - /* And finally, enable interrupts. Also clears PS.EXCM */ - - xtensa_color_intstack(); - up_irq_enable(); -#endif - - /* Attach the software interrupt */ - - irq_attach(XTENSA_IRQ_SYSCALL, xtensa_swint, NULL); -} - -/**************************************************************************** - * Name: up_disable_irq - * - * Description: - * Disable the IRQ specified by 'irq' - * - ****************************************************************************/ - -void up_disable_irq(int irq) -{ - int cpu = IRQ_GETCPU(g_irqmap[irq]); - int cpuint = IRQ_GETCPUINT(g_irqmap[irq]); - - if (g_irqmap[irq] == IRQ_UNMAPPED) - { - /* This interrupt is already disabled. */ - - return; - } - - DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32_CPUINT_MAX); - DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS); - - if (irq < XTENSA_NIRQ_INTERNAL) - { - /* This is an internal CPU interrupt, it cannot be disabled using - * the Interrupt Matrix. - */ - -#ifdef CONFIG_SMP - int me = this_cpu(); - if (me != cpu) - { - /* It was the other CPU that enabled this interrupt. */ - - return; - } -#endif - - xtensa_disable_cpuint(&g_intenable[cpu], cpuint); - } - else - { - /* A peripheral interrupt, use the Interrupt Matrix to disable it. */ - - int periph = ESP32_IRQ2PERIPH(irq); - uintptr_t regaddr; - uint8_t *intmap; - -#ifdef CONFIG_ESP32_GPIO_IRQ -#ifdef CONFIG_SMP - /* The APP's CPU GPIO is a special case. See esp32/irq.h */ - - if (irq == ESP32_IRQ_APPCPU_GPIO) - { - periph = ESP32_PERIPH_CPU_GPIO; - } -#endif -#endif - - DEBUGASSERT(periph >= 0 && periph < ESP32_NPERIPHERALS); - esp32_intinfo(cpu, periph, ®addr, &intmap); - - intmap[cpuint] = CPUINT_DISABLE(intmap[cpuint]); - putreg32(NO_CPUINT, regaddr); - } -} - -/**************************************************************************** - * Name: up_enable_irq - * - * Description: - * Enable the IRQ specified by 'irq' - * - ****************************************************************************/ - -void up_enable_irq(int irq) -{ - int cpuint = IRQ_GETCPUINT(g_irqmap[irq]); - - DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32_CPUINT_MAX); - - if (irq < XTENSA_NIRQ_INTERNAL) - { - /* For internal interrupts, use the current CPU. We can't enable other - * CPUs' internal interrupts. - * The CPU interrupt can still be taken from the map as internal - * interrupts have the same number for all CPUs. In this case then - * we are just overwriting the cpu part of the map. - */ - - int cpu = this_cpu(); - - /* Enable the CPU interrupt now for internal CPU. */ - - xtensa_enable_cpuint(&g_intenable[cpu], cpuint); - } - else - { - /* Retrieve the CPU that enabled this interrupt from the IRQ map. - * - * For peripheral interrupts we rely on the interrupt matrix to manage - * interrupts. The interrupt matrix registers are available for both - * CPUs. - */ - - int cpu = IRQ_GETCPU(g_irqmap[irq]); - - /* Check if the registered ISR for this IRQ is intended to be run from - * IRAM. If so, check if its interrupt handler is located in IRAM. - */ - - bool isr_in_iram = !((g_non_iram_int_mask[cpu] & (1 << cpuint)) > 0); - - xcpt_t handler = g_irqvector[irq].handler; - - if (isr_in_iram && handler && !esp32_ptr_iram(handler)) - { - irqerr("Interrupt handler isn't in IRAM (0x08%" PRIx16 ")", - (intptr_t)handler); - PANIC(); - } - - DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS); - - /* For peripheral interrupts, attach the interrupt to the peripheral; - * the CPU interrupt was already enabled when allocated. - */ - - int periph = ESP32_IRQ2PERIPH(irq); - uintptr_t regaddr; - uint8_t *intmap; - -#ifdef CONFIG_ESP32_GPIO_IRQ -#ifdef CONFIG_SMP - /* The APP's CPU GPIO is a special case. See esp32/irq.h */ - - if (irq == ESP32_IRQ_APPCPU_GPIO) - { - periph = ESP32_PERIPH_CPU_GPIO; - } -#endif -#endif - - DEBUGASSERT(periph >= 0 && periph < ESP32_NPERIPHERALS); - - esp32_intinfo(cpu, periph, ®addr, &intmap); - - intmap[cpuint] = CPUINT_ENABLE(intmap[cpuint]); - putreg32(cpuint, regaddr); - } -} - -/**************************************************************************** - * Name: up_get_intstackbase - * - * Description: - * Return a pointer to the "alloc" the correct interrupt stack allocation - * for the current CPU. - * - ****************************************************************************/ - -#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 15 -uintptr_t up_get_intstackbase(int cpu) -{ - return g_cpu_intstack_top[cpu] - INTSTACK_SIZE; -} -#endif - -/**************************************************************************** - * Name: esp32_cpuint_initialize - * - * Description: - * Initialize CPU interrupts - * - * Input Parameters: - * None - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned on - * any failure. - * - ****************************************************************************/ - -int esp32_cpuint_initialize(void) -{ - uintptr_t regaddr; - uint8_t *intmap; -#ifdef CONFIG_SMP - int cpu; -#endif - int i; - -#ifdef CONFIG_SMP - /* Which CPU are we initializing */ - - cpu = this_cpu(); - DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS); -#endif - - /* Disable all CPU interrupts on this CPU */ - - xtensa_disable_all(); - - /* Detach all peripheral sources PRO CPU interrupts */ - - for (i = 0; i < ESP32_NPERIPHERALS; i++) - { -#ifdef CONFIG_SMP - if (cpu != 0) - { - regaddr = DPORT_APP_MAP_REGADDR(i); - } - else -#endif - { - regaddr = DPORT_PRO_MAP_REGADDR(i); - } - - putreg32(NO_CPUINT, regaddr); - } - - /* Initialize CPU interrupt-to-IRQ mapping table */ - -#ifdef CONFIG_SMP - if (cpu != 0) - { - intmap = g_cpu1_intmap; - } - else -#endif - { - intmap = g_cpu0_intmap; - } - - /* Indicate that no peripheral interrupts are assigned to CPU interrupts */ - - memset(intmap, CPUINT_UNASSIGNED, ESP32_NCPUINTS); - - /* Special case the 6 internal interrupts. - * - * CPU interrupt bit IRQ number - * --------------------------- --------------------- - * ESP32_CPUINT_TIMER0 6 XTENSA_IRQ_TIMER0 0 - * ESP32_CPUINT_SOFTWARE0 7 Not yet defined - * ESP32_CPUINT_PROFILING 11 Not yet defined - * ESP32_CPUINT_TIMER1 15 XTENSA_IRQ_TIMER1 1 - * ESP32_CPUINT_TIMER2 16 XTENSA_IRQ_TIMER2 2 - * ESP32_CPUINT_SOFTWARE1 29 XTENSA_IRQ_SWINT 4 - */ - - intmap[ESP32_CPUINT_TIMER0] = CPUINT_ASSIGN(XTENSA_IRQ_TIMER0); - intmap[ESP32_CPUINT_TIMER1] = CPUINT_ASSIGN(XTENSA_IRQ_TIMER1); - intmap[ESP32_CPUINT_TIMER2] = CPUINT_ASSIGN(XTENSA_IRQ_TIMER2); - intmap[ESP32_CPUINT_SOFTWARE1] = CPUINT_ASSIGN(XTENSA_IRQ_SWINT); - - return OK; -} - -/**************************************************************************** - * Name: esp32_setup_irq - * - * Description: - * This function sets up the IRQ. It allocates a CPU interrupt of the given - * priority and associated flags and attaches it to the given peripheral. - * - * Input Parameters: - * cpu - The CPU to receive the interrupt 0=PRO CPU 1=APP CPU - * periphid - The peripheral number from irq.h to be assigned to - * a CPU interrupt. - * priority - Interrupt's priority (1 - 5). - * flags - An ORred mask of the ESP32_CPUINT_FLAG_* defines. These - * restrict the choice of interrupts that this routine can - * choose from. - * - * Returned Value: - * The allocated CPU interrupt on success, a negated errno value on - * failure. - * - ****************************************************************************/ - -int esp32_setup_irq(int cpu, int periphid, int priority, int flags) -{ - irqstate_t irqstate; - uintptr_t regaddr; - uint8_t *intmap; - int irq; - int cpuint; - - irqstate = enter_critical_section(); - - /* Setting up an IRQ includes the following steps: - * 1. Allocate a CPU interrupt. - * 2. Attach that CPU interrupt to the peripheral. - * 3. Map the CPU interrupt to the IRQ to ease searching later. - * 4. Check if its ISR is intended to run from IRAM. - */ - - cpuint = esp32_alloc_cpuint(cpu, priority, flags); - if (cpuint < 0) - { - irqerr("Unable to allocate CPU interrupt for priority=%d and flags=%d", - priority, flags); - leave_critical_section(irqstate); - - return cpuint; - } - - irq = ESP32_PERIPH2IRQ(periphid); - -#ifdef CONFIG_ESP32_GPIO_IRQ -#ifdef CONFIG_SMP - if (cpu == 1 && periphid == ESP32_PERIPH_CPU_GPIO) - { - irq = ESP32_IRQ_APPCPU_GPIO; - } -#endif -#endif - - DEBUGASSERT(periphid >= 0 && periphid < ESP32_NPERIPHERALS); - DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32_CPUINT_MAX); - - esp32_intinfo(cpu, periphid, ®addr, &intmap); - - DEBUGASSERT(intmap[cpuint] == CPUINT_UNASSIGNED); - - intmap[cpuint] = CPUINT_ASSIGN(periphid + XTENSA_IRQ_FIRSTPERIPH); - g_irqmap[irq] = IRQ_MKMAP(cpu, cpuint); - - if ((flags & ESP32_CPUINT_FLAG_IRAM) != 0) - { - esp32_irq_set_iram_isr(irq); - } - else - { - esp32_irq_unset_iram_isr(irq); - } - - putreg32(cpuint, regaddr); - - leave_critical_section(irqstate); - - return cpuint; -} - -/**************************************************************************** - * Name: esp32_teardown_irq - * - * Description: - * This function undoes the operations done by esp32_setup_irq. - * It detaches a peripheral interrupt from a CPU interrupt and frees the - * CPU interrupt. - * - * Input Parameters: - * cpu - The CPU to receive the interrupt 0=PRO CPU 1=APP CPU - * periphid - The peripheral number from irq.h to be detached from the - * CPU interrupt. - * cpuint - The CPU interrupt from which the peripheral interrupt will - * be detached. - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32_teardown_irq(int cpu, int periphid, int cpuint) -{ - irqstate_t irqstate; - uintptr_t regaddr; - uint8_t *intmap; - int irq; - - irqstate = enter_critical_section(); - - /* Tearing down an IRQ includes the following steps: - * 1. Free the previously allocated CPU interrupt. - * 2. Detach the interrupt from the peripheral. - * 3. Unmap the IRQ from the IRQ-to-cpuint map. - */ - - esp32_free_cpuint(cpuint); - - irq = ESP32_PERIPH2IRQ(periphid); - - DEBUGASSERT(periphid >= 0 && periphid < ESP32_NPERIPHERALS); - - esp32_intinfo(cpu, periphid, ®addr, &intmap); - - DEBUGASSERT(intmap[cpuint] != CPUINT_UNASSIGNED); - intmap[cpuint] = CPUINT_UNASSIGNED; - g_irqmap[irq] = IRQ_UNMAPPED; - - putreg32(NO_CPUINT, regaddr); - - leave_critical_section(irqstate); -} - -/**************************************************************************** - * Name: esp32_getirq - * - * Description: - * This function returns the IRQ associated with a CPU interrupt - * - * Input Parameters: - * cpu - The CPU core of the IRQ being queried - * cpuint - The CPU interrupt associated to the IRQ - * - * Returned Value: - * The IRQ associated with such CPU interrupt or CPUINT_UNASSIGNED if - * IRQ is not yet assigned to a CPU interrupt. - * - ****************************************************************************/ - -int esp32_getirq(int cpu, int cpuint) -{ - uint8_t *intmap; - -#ifdef CONFIG_SMP - /* Select PRO or APP CPU interrupt mapping table */ - - if (cpu != 0) - { - intmap = g_cpu1_intmap; - } - else -#endif - { - intmap = g_cpu0_intmap; - } - - return CPUINT_GETIRQ(intmap[cpuint]); -} - -/**************************************************************************** - * Name: esp32_getcpuint_from_irq - * - * Description: - * This function returns the CPU interrupt associated with an IRQ - * - * Input Parameters: - * irq - The IRQ associated with a CPU interrupt - * cpu - Pointer to store the CPU core of the CPU interrupt - * - * Returned Value: - * The CPU interrupt associated with such IRQ or IRQ_UNMAPPED if - * CPU interrupt is not mapped to an IRQ. - * - ****************************************************************************/ - -int esp32_getcpuint_from_irq(int irq, int *cpu) -{ - (*cpu) = (int)IRQ_GETCPU(g_irqmap[irq]); - - return IRQ_GETCPUINT(g_irqmap[irq]); -} - -/**************************************************************************** - * Name: xtensa_int_decode - * - * Description: - * Determine the peripheral that generated the interrupt and dispatch - * handling to the registered interrupt handler via xtensa_irq_dispatch(). - * - * Input Parameters: - * cpuints - Set of pending interrupts valid for this level - * regs - Saves processor state on the stack - * - * Returned Value: - * Normally the same value as regs is returned. But, in the event of an - * interrupt level context switch, the returned value will, instead point - * to the saved processor state in the TCB of the newly started task. - * - ****************************************************************************/ - -uint32_t *xtensa_int_decode(uint32_t *cpuints, uint32_t *regs) -{ - uint8_t *intmap; - uint32_t mask; - int bit; - int cpu; - -#ifdef CONFIG_ARCH_LEDS_CPU_ACTIVITY - board_autoled_on(LED_CPU); -#endif - - /* Select PRO or APP CPU interrupt mapping table */ - - cpu = this_cpu(); - -#ifdef CONFIG_SMP - if (cpu != 0) - { - intmap = g_cpu1_intmap; - } - else -#endif - { - intmap = g_cpu0_intmap; - } - - /* Skip over zero bits, eight at a time */ - - for (bit = 0, mask = 0xff; - bit < ESP32_NCPUINTS && (cpuints[0] & mask) == 0; - bit += 8, mask <<= 8); - - /* Process each pending CPU interrupt */ - - for (; bit < ESP32_NCPUINTS && cpuints[0] != 0; bit++) - { - mask = 1 << bit; - if ((cpuints[0] & mask) != 0) - { - /* Extract the IRQ number from the mapping table */ - - uint8_t irq = CPUINT_GETIRQ(intmap[bit]); - - DEBUGASSERT(CPUINT_GETEN(intmap[bit])); - DEBUGASSERT(irq != CPUINT_UNASSIGNED); - -#ifdef CONFIG_ESP32_IRAM_ISR_DEBUG - /* Check if non-IRAM interrupts are disabled */ - - if (esp32_irq_noniram_status(cpu) == 0) - { - /* Sum-up the IRAM-enabled counter associated with the IRQ */ - - esp32_irq_iram_interrupt_record(irq); - } -#endif - - /* Clear software or edge-triggered interrupt */ - - xtensa_intclear(bit); - - /* Dispatch the CPU interrupt. - * - * NOTE that regs may be altered in the case of an interrupt - * level context switch. - */ - - regs = xtensa_irq_dispatch((int)irq, regs); - - /* Clear the bit in the pending interrupt so that perhaps - * we can exit the look early. - */ - - cpuints[0] &= ~mask; - } - } - - UNUSED(cpu); - - return regs; -} - -/**************************************************************************** - * Name: esp32_irq_noniram_disable - * - * Description: - * Disable interrupts that aren't specifically marked as running from IRAM - * - * Input Parameters: - * None - * - * Input Parameters: - * None - * - ****************************************************************************/ - -void esp32_irq_noniram_disable(void) -{ - irqstate_t irqstate; - uint32_t mask; - int bit; - int cpu; - uint32_t oldint; - uint32_t non_iram_ints; - - irqstate = enter_critical_section(); - cpu = this_cpu(); - non_iram_ints = g_non_iram_int_mask[cpu]; - - ASSERT(!g_non_iram_int_disabled_flag[cpu]); - - g_non_iram_int_disabled_flag[cpu] = true; - oldint = g_intenable[cpu]; - - for (bit = 0; bit < ESP32_NCPUINTS; bit++) - { - mask = 1 << bit; - if ((non_iram_ints & mask) != 0) - { - xtensa_disable_cpuint(&g_intenable[cpu], bit); - } - } - - g_non_iram_int_disabled[cpu] = oldint & non_iram_ints; - - leave_critical_section(irqstate); -} - -/**************************************************************************** - * Name: esp32_irq_noniram_enable - * - * Description: - * Re-enable interrupts disabled by esp32_irq_noniram_disable - * - * Input Parameters: - * None - * - * Input Parameters: - * None - * - ****************************************************************************/ - -void esp32_irq_noniram_enable(void) -{ - irqstate_t irqstate; - uint32_t mask; - int bit; - int cpu; - uint32_t non_iram_ints; - - irqstate = enter_critical_section(); - cpu = this_cpu(); - non_iram_ints = g_non_iram_int_disabled[cpu]; - - ASSERT(g_non_iram_int_disabled_flag[cpu]); - - g_non_iram_int_disabled_flag[cpu] = false; - - for (bit = 0; bit < ESP32_NCPUINTS; bit++) - { - mask = 1 << bit; - if ((non_iram_ints & mask) != 0) - { - xtensa_enable_cpuint(&g_intenable[cpu], bit); - } - } - - leave_critical_section(irqstate); -} - -/**************************************************************************** - * Name: esp32_irq_noniram_status - * - * Description: - * Get the current status of non-IRAM interrupts on a specific CPU core - * - * Input Parameters: - * cpu - The CPU to check the non-IRAM interrupts state - * - * Returned Value: - * true if non-IRAM interrupts are enabled, false otherwise. - * - ****************************************************************************/ - -bool esp32_irq_noniram_status(int cpu) -{ - DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS); - - return !g_non_iram_int_disabled_flag[cpu]; -} - -/**************************************************************************** - * Name: esp32_irq_set_iram_isr - * - * Description: - * Set the ISR associated to an IRQ as a IRAM-enabled ISR. - * - * Input Parameters: - * irq - The associated IRQ to set - * - * Returned Value: - * OK on success; A negated errno value on failure. - * - ****************************************************************************/ - -int esp32_irq_set_iram_isr(int irq) -{ - int cpu; - int cpuint = esp32_getcpuint_from_irq(irq, &cpu); - - if (cpuint == IRQ_UNMAPPED) - { - return -EINVAL; - } - - g_non_iram_int_mask[cpu] &= ~(1 << cpuint); - - return OK; -} - -/**************************************************************************** - * Name: esp32_irq_unset_iram_isr - * - * Description: - * Set the ISR associated to an IRQ as a non-IRAM ISR. - * - * Input Parameters: - * irq - The associated IRQ to set - * - * Returned Value: - * OK on success; A negated errno value on failure. - * - ****************************************************************************/ - -int esp32_irq_unset_iram_isr(int irq) -{ - int cpu; - int cpuint = esp32_getcpuint_from_irq(irq, &cpu); - - if (cpuint == IRQ_UNMAPPED) - { - return -EINVAL; - } - - g_non_iram_int_mask[cpu] |= (1 << cpuint); - - return OK; -} - -#ifdef CONFIG_ESP32_IRAM_ISR_DEBUG - -/**************************************************************************** - * Name: esp32_get_iram_interrupt_records - * - * Description: - * This function copies the vector that keeps track of the IRQs that ran - * when non-IRAM interrupts were disabled. - * - * Input Parameters: - * - * irq_count - A previously allocated pointer to store the counter of the - * interrupts that ran when non-IRAM interrupts were disabled. - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32_get_iram_interrupt_records(uint64_t *irq_count) -{ - irqstate_t flags = enter_critical_section(); - - memcpy(irq_count, &g_iram_count, sizeof(uint64_t) * NR_IRQS); - - leave_critical_section(flags); -} -#endif diff --git a/arch/xtensa/src/esp32/esp32_irq.h b/arch/xtensa/src/esp32/esp32_irq.h deleted file mode 100644 index ba2947792401c..0000000000000 --- a/arch/xtensa/src/esp32/esp32_irq.h +++ /dev/null @@ -1,263 +0,0 @@ -/**************************************************************************** - * arch/xtensa/src/esp32/esp32_irq.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_XTENSA_SRC_ESP32_ESP32_IRQ_H -#define __ARCH_XTENSA_SRC_ESP32_ESP32_IRQ_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* CPU interrupt types. */ - -#define ESP32_CPUINT_LEVEL ESP32_CPUINT_FLAG_LEVEL -#define ESP32_CPUINT_EDGE ESP32_CPUINT_FLAG_EDGE - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32_cpuint_initialize - * - * Description: - * Initialize CPU interrupts - * - * Input Parameters: - * None - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned on - * any failure. - * - ****************************************************************************/ - -int esp32_cpuint_initialize(void); - -/**************************************************************************** - * Name: esp32_setup_irq - * - * Description: - * This function sets up the IRQ. It allocates a CPU interrupt of the given - * priority and associated flags and attaches it to the given peripheral. - * - * Input Parameters: - * cpu - The CPU to receive the interrupt 0=PRO CPU 1=APP CPU - * periphid - The peripheral number from irq.h to be assigned to - * a CPU interrupt. - * priority - Interrupt's priority (1 - 5). - * flags - An ORred mask of the ESP32_CPUINT_FLAG_* defines. These - * restrict the choice of interrupts that this routine can - * choose from. - * - * Returned Value: - * The allocated CPU interrupt on success, a negated errno value on - * failure. - * - ****************************************************************************/ - -int esp32_setup_irq(int cpu, int periphid, int priority, int flags); - -/**************************************************************************** - * Name: esp32_teardown_irq - * - * Description: - * This function undoes the operations done by esp32_setup_irq. - * It detaches a peripheral interrupt from a CPU interrupt and frees the - * CPU interrupt. - * - * Input Parameters: - * cpu - The CPU to receive the interrupt 0=PRO CPU 1=APP CPU - * periphid - The peripheral number from irq.h to be detached from the - * CPU interrupt. - * cpuint - The CPU interrupt from which the peripheral interrupt will - * be detached. - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32_teardown_irq(int cpu, int periphid, int cpuint); - -/**************************************************************************** - * Name: esp32_getirq - * - * Description: - * This function returns the IRQ associated with a CPU interrupt - * - * Input Parameters: - * cpu - The CPU core of the IRQ being queried - * cpuint - The CPU interrupt associated to the IRQ - * - * Returned Value: - * The IRQ associated with such CPU interrupt or CPUINT_UNASSIGNED if - * IRQ is not yet assigned to a CPU interrupt. - * - ****************************************************************************/ - -int esp32_getirq(int cpu, int cpuint); - -/**************************************************************************** - * Name: esp32_getcpuint_from_irq - * - * Description: - * This function returns the CPU interrupt associated with an IRQ - * - * Input Parameters: - * irq - The IRQ associated with a CPU interrupt - * cpu - Pointer to store the CPU core of the CPU interrupt - * - * Returned Value: - * The CPU interrupt associated with such IRQ or IRQ_UNMAPPED if - * CPU interrupt is not mapped to an IRQ. - * - ****************************************************************************/ - -int esp32_getcpuint_from_irq(int irq, int *cpu); - -/**************************************************************************** - * Name: esp32_irq_noniram_disable - * - * Description: - * Disable interrupts that aren't specifically marked as running from IRAM - * - * Input Parameters: - * None - * - * Input Parameters: - * None - * - ****************************************************************************/ - -void esp32_irq_noniram_disable(void); - -/**************************************************************************** - * Name: esp32_irq_noniram_enable - * - * Description: - * Re-enable interrupts disabled by esp32_irq_noniram_disable - * - * Input Parameters: - * None - * - * Input Parameters: - * None - * - ****************************************************************************/ - -void esp32_irq_noniram_enable(void); - -/**************************************************************************** - * Name: esp32_irq_noniram_status - * - * Description: - * Get the current status of non-IRAM interrupts on a specific CPU core - * - * Input Parameters: - * cpu - The CPU to check the non-IRAM interrupts state - * - * Returned Value: - * true if non-IRAM interrupts are enabled, false otherwise. - * - ****************************************************************************/ - -bool esp32_irq_noniram_status(int cpu); - -/**************************************************************************** - * Name: esp32_irq_set_iram_isr - * - * Description: - * Set the ISR associated to an IRQ as a IRAM-enabled ISR. - * - * Input Parameters: - * irq - The associated IRQ to set - * - * Returned Value: - * OK on success; A negated errno value on failure. - * - ****************************************************************************/ - -int esp32_irq_set_iram_isr(int irq); - -/**************************************************************************** - * Name: esp32_irq_unset_iram_isr - * - * Description: - * Set the ISR associated to an IRQ as a non-IRAM ISR. - * - * Input Parameters: - * irq - The associated IRQ to set - * - * Returned Value: - * OK on success; A negated errno value on failure. - * - ****************************************************************************/ - -int esp32_irq_unset_iram_isr(int irq); - -#ifdef CONFIG_ESP32_IRAM_ISR_DEBUG - -/**************************************************************************** - * Name: esp32_get_iram_interrupt_records - * - * Description: - * This function copies the vector that keeps track of the IRQs that ran - * when non-IRAM interrupts were disabled. - * - * Input Parameters: - * - * irq_count - A previously allocated pointer to store the counter of the - * interrupts that ran when non-IRAM interrupts were disabled. - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32_get_iram_interrupt_records(uint64_t *irq_count); -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_XTENSA_SRC_ESP32_ESP32_IRQ_H */ diff --git a/arch/xtensa/src/esp32/esp32_ledc.c b/arch/xtensa/src/esp32/esp32_ledc.c index d93e47645d704..62e6d3862e386 100644 --- a/arch/xtensa/src/esp32/esp32_ledc.c +++ b/arch/xtensa/src/esp32/esp32_ledc.c @@ -31,8 +31,8 @@ #include #include -#include "esp32_clockconfig.h" -#include "esp32_gpio.h" +#include "esp_clk.h" +#include "esp_gpio.h" #include "esp32_ledc.h" #include "xtensa.h" @@ -576,8 +576,8 @@ static int pwm_setup(struct pwm_lowerhalf_s *dev) pwminfo("channel%d --> pin%d\n", priv->chans[i].num, priv->chans[i].pin); - esp32_configgpio(priv->chans[i].pin, OUTPUT | PULLUP); - esp32_gpio_matrix_out(priv->chans[i].pin, + esp_configgpio(priv->chans[i].pin, OUTPUT | PULLUP); + esp_gpio_matrix_out(priv->chans[i].pin, LEDC_LS_SIG_OUT0_IDX + priv->chans[i].num, 0, 0); } diff --git a/arch/xtensa/src/esp32/esp32_libc_stubs.c b/arch/xtensa/src/esp32/esp32_libc_stubs.c index 2cd2bf069591f..6adf18af0a186 100644 --- a/arch/xtensa/src/esp32/esp32_libc_stubs.c +++ b/arch/xtensa/src/esp32/esp32_libc_stubs.c @@ -35,6 +35,7 @@ #include #include #include +#include #include "rom/esp32_libc_stubs.h" @@ -165,6 +166,11 @@ void _raise_r(struct _reent *r) void _lock_init(_lock_t *lock) { + if (sched_idletask()) + { + return; + } + *lock = 0; mutex_t *mutex = (mutex_t *)kmm_malloc(sizeof(mutex_t)); @@ -176,6 +182,11 @@ void _lock_init(_lock_t *lock) void _lock_init_recursive(_lock_t *lock) { + if (sched_idletask()) + { + return; + } + *lock = 0; rmutex_t *rmutex = (rmutex_t *)kmm_malloc(sizeof(rmutex_t)); @@ -187,6 +198,11 @@ void _lock_init_recursive(_lock_t *lock) void _lock_close(_lock_t *lock) { + if (sched_idletask()) + { + return; + } + mutex_t *mutex = (mutex_t *)(*lock); nxmutex_destroy(mutex); @@ -196,6 +212,11 @@ void _lock_close(_lock_t *lock) void _lock_close_recursive(_lock_t *lock) { + if (sched_idletask()) + { + return; + } + rmutex_t *rmutex = (rmutex_t *)(*lock); nxrmutex_destroy(rmutex); @@ -205,6 +226,11 @@ void _lock_close_recursive(_lock_t *lock) void _lock_acquire(_lock_t *lock) { + if (sched_idletask()) + { + return; + } + if ((*lock) == 0) { mutex_t *mutex = (mutex_t *)kmm_malloc(sizeof(mutex_t)); @@ -219,6 +245,11 @@ void _lock_acquire(_lock_t *lock) void _lock_acquire_recursive(_lock_t *lock) { + if (sched_idletask()) + { + return; + } + if ((*lock) == 0) { rmutex_t *rmutex = (rmutex_t *)kmm_malloc(sizeof(rmutex_t)); @@ -233,6 +264,11 @@ void _lock_acquire_recursive(_lock_t *lock) int _lock_try_acquire(_lock_t *lock) { + if (sched_idletask()) + { + return -EPERM; + } + if ((*lock) == 0) { mutex_t *mutex = (mutex_t *)kmm_malloc(sizeof(mutex_t)); @@ -247,6 +283,11 @@ int _lock_try_acquire(_lock_t *lock) int _lock_try_acquire_recursive(_lock_t *lock) { + if (sched_idletask()) + { + return -EPERM; + } + if ((*lock) == 0) { rmutex_t *rmutex = (rmutex_t *)kmm_malloc(sizeof(rmutex_t)); @@ -261,6 +302,11 @@ int _lock_try_acquire_recursive(_lock_t *lock) void _lock_release(_lock_t *lock) { + if (sched_idletask()) + { + return; + } + mutex_t *mutex = (mutex_t *)(*lock); nxmutex_unlock(mutex); @@ -268,6 +314,11 @@ void _lock_release(_lock_t *lock) void _lock_release_recursive(_lock_t *lock) { + if (sched_idletask()) + { + return; + } + rmutex_t *rmutex = (rmutex_t *)(*lock); nxrmutex_unlock(rmutex); diff --git a/arch/xtensa/src/esp32/esp32_oneshot.c b/arch/xtensa/src/esp32/esp32_oneshot.c index ecd05952acd51..4b1280a57fe19 100644 --- a/arch/xtensa/src/esp32/esp32_oneshot.c +++ b/arch/xtensa/src/esp32/esp32_oneshot.c @@ -37,8 +37,8 @@ #include "hardware/esp32_soc.h" +#include "esp_clk.h" #include "esp32_tim.h" -#include "esp32_clockconfig.h" #include "esp32_oneshot.h" #ifdef CONFIG_ESP32_ONESHOT diff --git a/arch/xtensa/src/esp32/esp32_pm.c b/arch/xtensa/src/esp32/esp32_pm.c deleted file mode 100644 index d10b20ad88ff4..0000000000000 --- a/arch/xtensa/src/esp32/esp32_pm.c +++ /dev/null @@ -1,1167 +0,0 @@ -/**************************************************************************** - * arch/xtensa/src/esp32/esp32_pm.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#ifdef CONFIG_PM - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "hardware/esp32_rtccntl.h" -#include "hardware/esp32_uart.h" -#include "hardware/esp32_dport.h" -#include "xtensa.h" -#include "xtensa_attr.h" -#include "esp32_rtc.h" -#include "esp32_clockconfig.h" -#include "esp32_pm.h" -#include "esp32_resetcause.h" - -#ifdef CONFIG_ESP32_RT_TIMER -#include "esp32_rt_timer.h" -#endif - -#ifdef CONFIG_SCHED_TICKLESS -#include "esp32_tickless.h" -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* If light sleep time is less than that, don't power down flash */ - -#define FLASH_PD_MIN_SLEEP_TIME_US 2000 - -/* Minimal amount of time we can sleep for. */ - -#define LIGHT_SLEEP_MIN_TIME_US 200 - -/* Time from VDD_SDIO power up to first flash read in ROM code */ - -#define VDD_SDIO_POWERUP_TO_FLASH_READ_US 700 - -/* Extra time it takes to enter and exit light sleep and deep sleep */ - -#define LIGHT_SLEEP_TIME_OVERHEAD_US (250 + 30 * 240 / CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ) -#define DEEP_SLEEP_TIME_OVERHEAD_US (250 + 100 * 240 / CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ) - -#define ESP32_DEEP_SLEEP_WAKEUP_DELAY 2000 - -#define RTC_VDDSDIO_TIEH_1_8V 0 /* TIEH field value for 1.8V VDDSDIO */ -#define RTC_VDDSDIO_TIEH_3_3V 1 /* TIEH field value for 3.3V VDDSDIO */ - -#define RTC_EXT0_TRIG_EN BIT(0) /* EXT0 GPIO wakeup */ -#define RTC_EXT1_TRIG_EN BIT(1) /* EXT1 GPIO wakeup */ -#define RTC_GPIO_TRIG_EN BIT(2) /* GPIO wakeup (light sleep only) */ -#define RTC_TIMER_TRIG_EN BIT(3) /* Timer wakeup */ -#define RTC_SDIO_TRIG_EN BIT(4) /* SDIO wakeup (light sleep only) */ -#define RTC_MAC_TRIG_EN BIT(5) /* MAC wakeup (light sleep only) */ -#define RTC_UART0_TRIG_EN BIT(6) /* UART0 wakeup (light sleep only) */ -#define RTC_UART1_TRIG_EN BIT(7) /* UART1 wakeup (light sleep only) */ -#define RTC_TOUCH_TRIG_EN BIT(8) /* Touch wakeup */ -#define RTC_ULP_TRIG_EN BIT(9) /* ULP wakeup */ -#define RTC_BT_TRIG_EN BIT(10) /* BT wakeup (light sleep only) */ - -#define RTC_ENTRY_ADDR_REG RTC_CNTL_STORE6_REG -#define RTC_MEMORY_CRC_REG RTC_CNTL_STORE7_REG - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* Power down options */ - -enum esp32_sleep_pd_option_e -{ - /* Power down the power domain in sleep mode */ - - ESP_PD_OPTION_OFF, - - /* Keep power domain enabled during sleep mode */ - - ESP_PD_OPTION_ON, - - /* Keep power domain enabled in sleep mode if it is needed - * by one of the wakeup options, otherwise power it down. - */ - - ESP_PD_OPTION_AUTO -}; - -/* Power domains which can be powered down in sleep mode. */ - -enum esp_sleep_pd_domain_e -{ - ESP_PD_DOMAIN_RTC_PERIPH, /* RTC IO, sensors and ULP co-processor */ - ESP_PD_DOMAIN_RTC_SLOW_MEM, /* RTC slow memory */ - ESP_PD_DOMAIN_RTC_FAST_MEM, /* RTC fast memory */ - ESP_PD_DOMAIN_XTAL, /* XTAL oscillator */ - ESP_PD_DOMAIN_MAX /* Number of domains */ -}; - -/* Internal structure which holds all requested deep sleep parameters. */ - -struct esp32_sleep_config_t -{ - enum esp32_sleep_pd_option_e pd_options[ESP_PD_DOMAIN_MAX]; - uint64_t sleep_duration; - uint32_t wakeup_triggers : 11; - uint32_t ext1_trigger_mode : 1; - uint32_t ext1_rtc_gpio_mask : 18; - uint32_t ext0_trigger_level : 1; - uint32_t ext0_rtc_gpio_num : 5; - uint32_t sleep_time_adjustment; - uint64_t rtc_ticks_at_sleep_start; -}; - -/* Structure describing vddsdio configuration. */ - -struct rtc_vddsdio_config_s -{ - uint32_t force : 1; /* If 1, use configuration from RTC registers; if 0, use EFUSE/bootstrapping pins. */ - uint32_t enable : 1; /* Enable VDDSDIO regulator */ - uint32_t tieh : 1; /* Select VDDSDIO voltage. One of RTC_VDDSDIO_TIEH_1_8V, RTC_VDDSDIO_TIEH_3_3V */ - uint32_t drefh : 2; /* Tuning parameter for VDDSDIO regulator */ - uint32_t drefm : 2; /* Tuning parameter for VDDSDIO regulator */ - uint32_t drefl : 2; /* Tuning parameter for VDDSDIO regulator */ -}; - -/* Function type for stub to run on wake from sleep */ - -typedef void (*esp_deep_sleep_wake_stub_fn_t)(void); - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static void esp32_timer_wakeup_prepare(void); -static void IRAM_ATTR esp32_flush_uarts(void); -static void IRAM_ATTR esp32_suspend_uarts(void); -static void IRAM_ATTR esp32_resume_uarts(void); -static uint32_t esp32_get_power_down_flags(void); -static inline void esp32_uart_tx_wait_idle(uint8_t uart_no); -static void IRAM_ATTR esp32_set_vddsdio_config( - struct rtc_vddsdio_config_s config); -static int IRAM_ATTR esp32_get_vddsdio_config( - struct rtc_vddsdio_config_s *config); -int IRAM_ATTR esp32_light_sleep_inner(uint32_t pd_flags, - uint32_t time_us, struct rtc_vddsdio_config_s config); -static int IRAM_ATTR esp32_configure_cpu_freq(uint32_t cpu_freq_mhz); -static inline bool IRAM_ATTR esp32_ptr_executable(const void *p); -static void esp32_set_deep_sleep_wake_stub( - esp_deep_sleep_wake_stub_fn_t new_stub); -static void RTC_IRAM_ATTR esp32_wake_deep_sleep(void); -static esp_deep_sleep_wake_stub_fn_t esp32_get_deep_sleep_wake_stub(void); - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -extern uint32_t g_ticks_per_us_pro; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct esp32_sleep_config_t s_config = -{ - .pd_options = - { ESP_PD_OPTION_AUTO, ESP_PD_OPTION_AUTO, ESP_PD_OPTION_AUTO }, - .wakeup_triggers = 0 -}; - -static _Atomic uint32_t pm_wakelock = 0; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/* CPU do while loop for some time. */ - -extern void ets_delay_us(uint32_t us); - -/* Set CRC of Fast RTC memory 0-0x7ff into RTC STORE7. */ - -extern void set_rtc_memory_crc(void); - -/* Set the real CPU ticks per us to the ets, - * so that ets_delay_us will be accurate. - */ - -extern void ets_update_cpu_frequency_rom(uint32_t ticks_per_us); - -/* Get xtal_freq value, If value not stored in RTC_STORE5, than store. */ - -extern uint32_t ets_get_detected_xtal_freq(void); - -/**************************************************************************** - * Name: esp32_uart_tx_wait_idle - * - * Description: - * Wait until uart tx full empty and the last char send ok. - * - * Input Parameters: - * uart_no - 0 for UART0, 1 for UART1, 2 for UART2 - * - * Returned Value: - * None - * - ****************************************************************************/ - -static inline void esp32_uart_tx_wait_idle(uint8_t uart_no) -{ - uint32_t status; - do - { - status = getreg32(UART_STATUS_REG(uart_no)); - - /* either tx count or state is non-zero */ - } - while ((status & (UART_ST_UTX_OUT_M | UART_TXFIFO_CNT_M)) != 0); -} - -/**************************************************************************** - * Name: esp32_flush_uarts - * - * Description: - * Wait until UART0/UART1/UART2 tx full empty and the last char send ok - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void IRAM_ATTR esp32_flush_uarts(void) -{ - int i; - - for (i = 0; i < ESP32_NUARTS; ++i) - { - esp32_uart_tx_wait_idle(i); - } -} - -/**************************************************************************** - * Name: esp32_suspend_uarts - * - * Description: - * Suspend UART0/UART1/UART2 output - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void IRAM_ATTR esp32_suspend_uarts(void) -{ - int i; - - for (i = 0; i < ESP32_NUARTS; ++i) - { - modifyreg32(UART_FLOW_CONF_REG(i), 0, UART_FORCE_XOFF); - while (REG_GET_FIELD(UART_STATUS_REG(i), UART_ST_UTX_OUT) != 0); - } -} - -/**************************************************************************** - * Name: esp32_resume_uarts - * - * Description: - * Re-enable UART0/UART1/UART2 output - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void IRAM_ATTR esp32_resume_uarts(void) -{ - int i; - - for (i = 0; i < ESP32_NUARTS; ++i) - { - modifyreg32(UART_FLOW_CONF_REG(i), UART_FORCE_XOFF, 0); - modifyreg32(UART_FLOW_CONF_REG(i), 0, UART_FORCE_XON); - modifyreg32(UART_FLOW_CONF_REG(i), UART_FORCE_XON, 0); - } -} - -/**************************************************************************** - * Name: esp32_get_power_down_flags - * - * Description: - * Get power domains that can be powered down - * - * Input Parameters: - * None - * - * Returned Value: - * Power domains - * - ****************************************************************************/ - -static uint32_t esp32_get_power_down_flags(void) -{ - uint32_t pd_flags = 0; - - if (s_config.pd_options[ESP_PD_DOMAIN_RTC_FAST_MEM] == ESP_PD_OPTION_AUTO) - { - s_config.pd_options[ESP_PD_DOMAIN_RTC_FAST_MEM] = ESP_PD_OPTION_ON; - } - - if (s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] == ESP_PD_OPTION_AUTO) - { - if (s_config.wakeup_triggers & (RTC_EXT0_TRIG_EN | RTC_GPIO_TRIG_EN)) - { - s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] = ESP_PD_OPTION_ON; - } - else if (s_config.wakeup_triggers & - (RTC_TOUCH_TRIG_EN | RTC_ULP_TRIG_EN)) - { - /* In both rev. 0 and rev. 1 of ESP32, - * forcing power up of prevents ULP timer - * and touch FSMs from working correctly. - */ - - s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] = ESP_PD_OPTION_OFF; - } - } - - if (s_config.pd_options[ESP_PD_DOMAIN_XTAL] == ESP_PD_OPTION_AUTO) - { - s_config.pd_options[ESP_PD_DOMAIN_XTAL] = ESP_PD_OPTION_OFF; - } - - /* Prepare flags based on the selected options */ - - if (s_config.pd_options[ESP_PD_DOMAIN_RTC_FAST_MEM] != ESP_PD_OPTION_ON) - { - pd_flags |= RTC_SLEEP_PD_RTC_FAST_MEM; - } - - if (s_config.pd_options[ESP_PD_DOMAIN_RTC_SLOW_MEM] != ESP_PD_OPTION_ON) - { - pd_flags |= RTC_SLEEP_PD_RTC_SLOW_MEM; - } - - if (s_config.pd_options[ESP_PD_DOMAIN_RTC_PERIPH] != ESP_PD_OPTION_ON) - { - pd_flags |= RTC_SLEEP_PD_RTC_PERIPH; - } - - if (s_config.pd_options[ESP_PD_DOMAIN_XTAL] != ESP_PD_OPTION_ON) - { - pd_flags |= RTC_SLEEP_PD_XTAL; - } - - return pd_flags; -} - -/**************************************************************************** - * Name: esp32_timer_wakeup_prepare - * - * Description: - * Configure timer to wake-up - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void esp32_timer_wakeup_prepare(void) -{ - uint32_t period; - int64_t sleep_duration; - int64_t rtc_count_delta; - - period = getreg32(RTC_SLOW_CLK_CAL_REG); - sleep_duration = (int64_t) s_config.sleep_duration - - (int64_t) s_config.sleep_time_adjustment; - - if (sleep_duration < 0) - { - sleep_duration = 0; - } - - rtc_count_delta = esp32_rtc_time_us_to_slowclk(sleep_duration, period); - esp32_rtc_sleep_set_wakeup_time(s_config.rtc_ticks_at_sleep_start + - rtc_count_delta); -} - -/**************************************************************************** - * Name: esp32_set_vddsdio_config - * - * Description: - * Set new VDDSDIO configuration using RTC registers. - * - * Input Parameters: - * New VDDSDIO configuration - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void IRAM_ATTR esp32_set_vddsdio_config( - struct rtc_vddsdio_config_s config) -{ - uint32_t val = 0; - val |= (config.force << RTC_CNTL_SDIO_FORCE_S); - val |= (config.enable << RTC_CNTL_XPD_SDIO_REG_S); - val |= (config.drefh << RTC_CNTL_DREFH_SDIO_S); - val |= (config.drefm << RTC_CNTL_DREFM_SDIO_S); - val |= (config.drefl << RTC_CNTL_DREFL_SDIO_S); - val |= (config.tieh << RTC_CNTL_SDIO_TIEH_S); - val |= RTC_CNTL_SDIO_PD_EN; - putreg32((uint32_t)val, RTC_CNTL_SDIO_CONF_REG); -} - -/**************************************************************************** - * Name: esp32_get_vddsdio_config - * - * Description: - * Get current VDDSDIO configuration. - * - * Input Parameters: - * Incoming parameter address of VDDSDIO configuration to be saved - * - * Returned Value: - * Zero (OK) is returned on success. - * - ****************************************************************************/ - -static int IRAM_ATTR esp32_get_vddsdio_config( - struct rtc_vddsdio_config_s *config) -{ - struct rtc_vddsdio_config_s *result = config; - uint32_t efuse_reg; - uint32_t strap_reg; - uint32_t sdio_conf_reg = getreg32(RTC_CNTL_SDIO_CONF_REG); - - result->drefh = (sdio_conf_reg & RTC_CNTL_DREFH_SDIO_M) - >> RTC_CNTL_DREFH_SDIO_S; - result->drefm = (sdio_conf_reg & RTC_CNTL_DREFM_SDIO_M) - >> RTC_CNTL_DREFM_SDIO_S; - result->drefl = (sdio_conf_reg & RTC_CNTL_DREFL_SDIO_M) - >> RTC_CNTL_DREFL_SDIO_S; - - if (sdio_conf_reg & RTC_CNTL_SDIO_FORCE) - { - /* Get configuration from RTC */ - - result->force = 1; - result->enable = (sdio_conf_reg & RTC_CNTL_XPD_SDIO_REG_M) - >> RTC_CNTL_XPD_SDIO_REG_S; - result->tieh = (sdio_conf_reg & RTC_CNTL_SDIO_TIEH_M) - >> RTC_CNTL_SDIO_TIEH_S; - - return OK; - } - - efuse_reg = getreg32(EFUSE_BLK0_RDATA4_REG); - - if (efuse_reg & EFUSE_RD_XPD_SDIO_FORCE) - { - /* Get configuration from EFUSE */ - - result->force = 0; - result->enable = (efuse_reg & EFUSE_RD_XPD_SDIO_REG_M) - >> EFUSE_RD_XPD_SDIO_REG_S; - result->tieh = (efuse_reg & EFUSE_RD_XPD_SDIO_TIEH_M) - >> EFUSE_RD_XPD_SDIO_TIEH_S; - - if (REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, - EFUSE_RD_BLK3_PART_RESERVE) == 0) - { - result->drefh = (efuse_reg >> 8) & 0x3; - result->drefm = (efuse_reg >> 10) & 0x3; - result->drefl = (efuse_reg >> 12) & 0x3; - } - - return OK; - } - - /* Otherwise, VDD_SDIO is controlled by bootstrapping pin */ - - strap_reg = getreg32(GPIO_STRAP_REG); - result->force = 0; - result->tieh = (strap_reg & BIT(5)) ? RTC_VDDSDIO_TIEH_1_8V - : RTC_VDDSDIO_TIEH_3_3V; - result->enable = 1; - - return OK; -} - -/**************************************************************************** - * Name: esp32_sleep_start - * - * Description: - * Enter low power mode. - * - * Input Parameters: - * Power domains - * - * Returned Value: - * 0 is returned on success or a negated errno value is returned - * - ****************************************************************************/ - -static int IRAM_ATTR esp32_sleep_start(uint32_t pd_flags) -{ - int result; - uint32_t cur_freq; - - /* Stop UART output so that output is not lost due to APB frequency change. - * For light sleep, suspend UART output - it will resume after wakeup. - * For deep sleep, wait for the contents of UART FIFO to be sent. - */ - - if (pd_flags & RTC_SLEEP_PD_DIG) - { - esp32_flush_uarts(); - } - else - { - esp32_suspend_uarts(); - } - - /* Save current frequency and switch to XTAL */ - - cur_freq = esp_rtc_clk_get_cpu_freq(); - esp32_rtc_cpu_freq_set_xtal(); - - /* Enter sleep */ - - esp32_rtc_sleep_init(pd_flags); - - /* Configure timer wakeup */ - - if ((s_config.wakeup_triggers & RTC_TIMER_TRIG_EN) - && s_config.sleep_duration > 0) - { - esp32_timer_wakeup_prepare(); - } - - result = esp32_rtc_sleep_start(s_config.wakeup_triggers, 0); - - /* Restore CPU frequency */ - - if (esp32_configure_cpu_freq(cur_freq) != OK) - { - pwrwarn("WARNING: Failed to restore CPU frequency" - "Configure cpu frequency %" PRIu32 ".\n", cur_freq); - } - - /* Re-enable UART output */ - - esp32_resume_uarts(); - - return result; -} - -/**************************************************************************** - * Name: esp32_light_sleep_inner - * - * Description: - * Enter low power mode, then wait for flash to be ready on wakeup - * - * Input Parameters: - * pd_flags - Power domains - * time_us - Time to wait for spi_flash become ready - * config - VDDSDIO configuration - * - * Returned Value: - * 0 is returned on success or a negated errno value is returned - * - ****************************************************************************/ - -int esp32_light_sleep_inner(uint32_t pd_flags, - uint32_t time_us, struct rtc_vddsdio_config_s config) -{ - /* Enter sleep */ - - int err = esp32_sleep_start(pd_flags); - - /* If VDDSDIO regulator was controlled by RTC registers before sleep. - * restore the configuration. - */ - - if (config.force) - { - esp32_set_vddsdio_config(config); - } - - /* If SPI flash was powered down, wait for it to become ready. */ - - if (pd_flags & RTC_SLEEP_PD_VDDSDIO) - { - /* Wait for the flash chip to start up. */ - - ets_delay_us(time_us); - } - - return err; -} - -/**************************************************************************** - * Name: esp32_configure_cpu_freq - * - * Description: - * Switch to new CPU frequencies. - * - * Input Parameters: - * cpu_freq_mhz - new CPU frequency - * - * Returned Value: - * 0 is returned on success or a negated errno value is returned - * - ****************************************************************************/ - -static int IRAM_ATTR esp32_configure_cpu_freq(uint32_t cpu_freq_mhz) -{ - uint32_t soc_clk_sel; - uint32_t source_freq_mhz; - enum esp32_rtc_xtal_freq_e xtal_freq; - - if (cpu_freq_mhz == 240) - { - source_freq_mhz = RTC_PLL_FREQ_480M; - } - else if(cpu_freq_mhz == 80 || cpu_freq_mhz == 160) - { - source_freq_mhz = RTC_PLL_FREQ_320M; - } - else - { - return -EINVAL; - } - - xtal_freq = esp32_rtc_clk_xtal_freq_get(); - soc_clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL); - - if (soc_clk_sel != RTC_CNTL_SOC_CLK_SEL_XTL) - { - esp32_rtc_update_to_xtal(xtal_freq, 1); - esp32_rtc_wait_for_slow_cycle(); - } - - if (soc_clk_sel == RTC_CNTL_SOC_CLK_SEL_PLL) - { - esp32_rtc_bbpll_disable(); - } - - esp32_rtc_bbpll_enable(); - esp32_rtc_wait_for_slow_cycle(); - esp32_rtc_bbpll_configure(xtal_freq, source_freq_mhz); - esp32_set_cpu_freq(cpu_freq_mhz); - - return OK; -} - -/**************************************************************************** - * Name: esp32_ptr_executable - * - * Description: - * Check if point p in a compatible memory area of IRAM - * - * Input Parameters: - * p - Memory address - * - * Returned Value: - * True if in memory area or false if not. - * - ****************************************************************************/ - -static inline bool IRAM_ATTR esp32_ptr_executable(const void *p) -{ - intptr_t ip = (intptr_t) p; - - return (ip >= SOC_IROM_LOW && ip < SOC_IROM_HIGH) - || (ip >= SOC_IRAM_LOW && ip < SOC_IRAM_HIGH) - || (ip >= SOC_IROM_MASK_LOW && ip < SOC_IROM_MASK_HIGH) -#if defined(SOC_CACHE_APP_LOW) - || (ip >= SOC_CACHE_APP_LOW && ip < SOC_CACHE_APP_HIGH) -#endif - || (ip >= SOC_RTC_IRAM_LOW && ip < SOC_RTC_IRAM_HIGH); -} - -/**************************************************************************** - * Name: esp32_set_deep_sleep_wake_stub - * - * Description: - * Install a new stub at runtime to run on wake from deep sleep. - * - * Input Parameters: - * new_stub - Function type for stub to run on wake from sleep - * - * Returned Value: - * None. - * - ****************************************************************************/ - -static void esp32_set_deep_sleep_wake_stub( - esp_deep_sleep_wake_stub_fn_t new_stub) -{ - putreg32((uint32_t)new_stub, RTC_ENTRY_ADDR_REG); - set_rtc_memory_crc(); -} - -/**************************************************************************** - * Name: esp32_get_deep_sleep_wake_stub - * - * Description: - * Get current wake from deep sleep stub. - * - * Input Parameters: - * None - * - * Returned Value: - * Current wake from deep sleep stub, or NULL if no stub is installed. - * - ****************************************************************************/ - -static esp_deep_sleep_wake_stub_fn_t esp32_get_deep_sleep_wake_stub(void) -{ - uint32_t stored_crc = 0; - uint32_t calc_crc = 0; - esp_deep_sleep_wake_stub_fn_t stub_ptr = NULL; - - stored_crc = getreg32(RTC_MEMORY_CRC_REG); - set_rtc_memory_crc(); - calc_crc = getreg32(RTC_MEMORY_CRC_REG); - putreg32(stored_crc, RTC_MEMORY_CRC_REG); - - if (stored_crc != calc_crc) - { - return NULL; - } - - stub_ptr = (esp_deep_sleep_wake_stub_fn_t) getreg32(RTC_ENTRY_ADDR_REG); - if (!esp32_ptr_executable(stub_ptr)) - { - return NULL; - } - - return stub_ptr; -} - -/**************************************************************************** - * Name: esp32_wake_deep_sleep - * - * Description: - * Default stub to run on wake from deep sleep. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void RTC_IRAM_ATTR esp32_wake_deep_sleep(void) -{ - /* Clear MMU for CPU 0 */ - - putreg32(getreg32(DPORT_PRO_CACHE_CTRL1_REG) | DPORT_PRO_CACHE_MMU_IA_CLR, - DPORT_PRO_CACHE_CTRL1_REG); - putreg32(getreg32(DPORT_PRO_CACHE_CTRL1_REG) & - (~DPORT_PRO_CACHE_MMU_IA_CLR), DPORT_PRO_CACHE_CTRL1_REG); - -#if ESP32_DEEP_SLEEP_WAKEUP_DELAY > 0 - /* ROM code has not started yet, so we need to set delay factor - * used by ets_delay_us first. - */ - - ets_update_cpu_frequency_rom(ets_get_detected_xtal_freq() / 1000000); - - /* This delay is configured in menuconfig, it can be used to give - * the flash chip some time to become ready. - */ - - ets_delay_us(ESP32_DEEP_SLEEP_WAKEUP_DELAY); -#endif -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32_sleep_enable_timer_wakeup - * - * Description: - * Configure wake-up interval - * - * Input Parameters: - * time_in_us - Configure wake-up time interval - * - * Returned Value: - * None - * - ****************************************************************************/ - -void IRAM_ATTR esp32_sleep_enable_timer_wakeup(uint64_t time_in_us) -{ - s_config.wakeup_triggers |= RTC_TIMER_TRIG_EN; - s_config.sleep_duration = time_in_us; -} - -/**************************************************************************** - * Name: esp32_light_sleep_start - * - * Description: - * Enter sleep mode - * - * Input Parameters: - * sleep_time - Actual sleep time - * - * Returned Value: - * 0 is returned on success or a negated errno value is returned - * - ****************************************************************************/ - -int esp32_light_sleep_start(uint64_t *sleep_time) -{ - irqstate_t flags; - uint32_t pd_flags; - uint32_t flash_enable_time_us; -#ifndef CONFIG_ESP32_SPIRAM - uint32_t vddsdio_pd_sleep_duration; -#endif - struct rtc_vddsdio_config_s vddsdio_config; - int ret = OK; - - flags = enter_critical_section(); - s_config.rtc_ticks_at_sleep_start = esp32_rtc_time_get(); - - /* Decide which power domains can be powered down */ - - pd_flags = esp32_get_power_down_flags(); - - /* Amount of time to subtract from actual sleep time. - * This is spent on entering and leaving light sleep. - */ - - s_config.sleep_time_adjustment = LIGHT_SLEEP_TIME_OVERHEAD_US; - - /* Decide if VDD_SDIO needs to be powered down; - * If it needs to be powered down, adjust sleep time. - */ - - flash_enable_time_us = VDD_SDIO_POWERUP_TO_FLASH_READ_US - + ESP32_DEEP_SLEEP_WAKEUP_DELAY; - -#ifndef CONFIG_ESP32_SPIRAM - vddsdio_pd_sleep_duration = MAX(FLASH_PD_MIN_SLEEP_TIME_US, - flash_enable_time_us + LIGHT_SLEEP_TIME_OVERHEAD_US - + LIGHT_SLEEP_MIN_TIME_US); - - if (s_config.sleep_duration > vddsdio_pd_sleep_duration) - { - pd_flags |= RTC_SLEEP_PD_VDDSDIO; - s_config.sleep_time_adjustment += flash_enable_time_us; - } -#endif - - esp32_get_vddsdio_config(&vddsdio_config); - - /* Enter sleep, then wait for flash to be ready on wakeup */ - - ret = esp32_light_sleep_inner(pd_flags, flash_enable_time_us, - vddsdio_config); - if (sleep_time != NULL) - { - *sleep_time = esp32_rtc_time_slowclk_to_us(esp32_rtc_time_get() - - s_config.rtc_ticks_at_sleep_start, esp32_clk_slowclk_cal_get()); - } - - leave_critical_section(flags); - return ret; -} - -/**************************************************************************** - * Name: esp32_pminit - * - * Description: - * Initialize force sleep parameters. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32_pminit(void) -{ - /* Initialize RTC parameters */ - - esp32_rtc_init(); - esp32_rtc_clk_set(); -} - -/**************************************************************************** - * Name: esp32_pmstandby - * - * Description: - * Enter force sleep. - * - * Input Parameters: - * time_in_us - force sleep time interval - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32_pmstandby(uint64_t time_in_us) -{ - uint64_t rtc_diff_us; -#ifdef CONFIG_ESP32_RT_TIMER - uint64_t hw_start_us; - uint64_t hw_end_us; - uint64_t hw_diff_us; -#endif - - /* don't power down XTAL - powering it up takes different time on. */ - - esp32_sleep_enable_timer_wakeup(time_in_us); - -#ifdef CONFIG_ESP32_RT_TIMER - /* Get rt-timer timestamp before entering sleep */ - - hw_start_us = rt_timer_time_us(); -#endif - - esp32_light_sleep_start(&rtc_diff_us); - -#ifdef CONFIG_ESP32_RT_TIMER - /* Get rt-timer timestamp after waking up from sleep */ - - hw_end_us = rt_timer_time_us(); - hw_diff_us = hw_end_us - hw_start_us; - DEBUGASSERT(rtc_diff_us > hw_diff_us); - - rt_timer_calibration(rtc_diff_us - hw_diff_us); -#endif - -#ifdef CONFIG_SCHED_TICKLESS - up_step_idletime((uint32_t)time_in_us); -#endif - - pwrinfo("Returned from auto-sleep, slept for %" PRIu32 " ms\n", - (uint32_t)(rtc_diff_us) / 1000); -} - -/**************************************************************************** - * Name: esp32_sleep_get_wakeup_cause - * - * Description: - * Get the wakeup source which caused wakeup from sleep. - * - * Input Parameters: - * None - * - * Returned Value: - * Cause of wake up from last sleep - * (one of enum esp32_sleep_source_e values). - * - ****************************************************************************/ - -enum esp32_sleep_source_e esp32_sleep_get_wakeup_cause(void) -{ - uint32_t wakeup_cause; - if (esp32_resetcause(0) != ESP32_RESETCAUSE_CORE_DPSP) - { - return ESP_SLEEP_WAKEUP_UNDEFINED; - } - - wakeup_cause = REG_GET_FIELD(RTC_CNTL_WAKEUP_STATE_REG, - RTC_CNTL_WAKEUP_CAUSE); - if (wakeup_cause & RTC_EXT0_TRIG_EN) - { - return ESP_SLEEP_WAKEUP_EXT0; - } - else if (wakeup_cause & RTC_EXT1_TRIG_EN) - { - return ESP_SLEEP_WAKEUP_EXT1; - } - else if (wakeup_cause & RTC_TIMER_TRIG_EN) - { - return ESP_SLEEP_WAKEUP_TIMER; - } - else if (wakeup_cause & RTC_TOUCH_TRIG_EN) - { - return ESP_SLEEP_WAKEUP_TOUCHPAD; - } - else if (wakeup_cause & RTC_ULP_TRIG_EN) - { - return ESP_SLEEP_WAKEUP_ULP; - } - else if (wakeup_cause & RTC_GPIO_TRIG_EN) - { - return ESP_SLEEP_WAKEUP_GPIO; - } - else if (wakeup_cause & (RTC_UART0_TRIG_EN | RTC_UART1_TRIG_EN)) - { - return ESP_SLEEP_WAKEUP_UART; - } - else - { - return ESP_SLEEP_WAKEUP_UNDEFINED; - } -} - -/**************************************************************************** - * Name: esp32_deep_sleep_start - * - * Description: - * Enter deep sleep mode - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32_deep_sleep_start(void) -{ - uint32_t pd_flags; - - /* record current RTC time */ - - s_config.rtc_ticks_at_sleep_start = esp32_rtc_time_get(); - - /* Configure wake stub */ - - if (esp32_get_deep_sleep_wake_stub() == NULL) - { - esp32_set_deep_sleep_wake_stub(esp32_wake_deep_sleep); - } - - /* Decide which power domains can be powered down */ - - pd_flags = esp32_get_power_down_flags(); - - /* Correct the sleep time */ - - s_config.sleep_time_adjustment = DEEP_SLEEP_TIME_OVERHEAD_US; - - /* Enter deep sleep */ - - esp32_sleep_start(RTC_SLEEP_PD_DIG | RTC_SLEEP_PD_VDDSDIO - | RTC_SLEEP_PD_XTAL | pd_flags); - - /* Because RTC is in a slower clock domain than the CPU, it - * can take several CPU cycles for the sleep mode to start. - */ - - while (1); -} - -/**************************************************************************** - * Name: esp32_pmsleep - * - * Description: - * Enter deep sleep. - * - * Input Parameters: - * time_in_us - deep sleep time interval - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32_pmsleep(uint64_t time_in_us) -{ - esp32_sleep_enable_timer_wakeup(time_in_us); - esp32_deep_sleep_start(); -} - -/**************************************************************************** - * Name: esp32_pm_lockacquire - * - * Description: - * Take a power management lock - * - ****************************************************************************/ - -void IRAM_ATTR esp32_pm_lockacquire(void) -{ - ++pm_wakelock; -} - -/**************************************************************************** - * Name: esp32_pm_lockrelease - * - * Description: - * Release the lock taken using esp32_pm_lockacquire. - * - ****************************************************************************/ - -void IRAM_ATTR esp32_pm_lockrelease(void) -{ - --pm_wakelock; -} - -/**************************************************************************** - * Name: esp32_pm_lockstatus - * - * Description: - * Return power management lock status. - * - ****************************************************************************/ - -uint32_t IRAM_ATTR esp32_pm_lockstatus(void) -{ - return pm_wakelock; -} - -#endif /* CONFIG_PM */ diff --git a/arch/xtensa/src/esp32/esp32_pm.h b/arch/xtensa/src/esp32/esp32_pm.h deleted file mode 100644 index 5a375b8c2be5d..0000000000000 --- a/arch/xtensa/src/esp32/esp32_pm.h +++ /dev/null @@ -1,248 +0,0 @@ -/**************************************************************************** - * arch/xtensa/src/esp32/esp32_pm.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#ifndef __ARCH_XTENSA_SRC_ESP32_ESP32_PM_H -#define __ARCH_XTENSA_SRC_ESP32_ESP32_PM_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -#ifdef CONFIG_PM - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/* Sleep wakeup cause */ - -enum esp32_sleep_source_e -{ -/* In case of deep sleep, reset was not caused by exit from deep sleep */ - - ESP_SLEEP_WAKEUP_UNDEFINED, - -/* Not a wakeup cause, used to disable all wakeup sources with - * esp_sleep_disable_wakeup_source - */ - - ESP_SLEEP_WAKEUP_ALL, - -/* Wakeup caused by external signal using RTC_IO */ - - ESP_SLEEP_WAKEUP_EXT0, - -/* Wakeup caused by external signal using RTC_CNTL */ - - ESP_SLEEP_WAKEUP_EXT1, - -/* Wakeup caused by timer */ - - ESP_SLEEP_WAKEUP_TIMER, - -/* Wakeup caused by touchpad */ - - ESP_SLEEP_WAKEUP_TOUCHPAD, - -/* Wakeup caused by ULP program */ - - ESP_SLEEP_WAKEUP_ULP, - -/* Wakeup caused by GPIO (light sleep only) */ - - ESP_SLEEP_WAKEUP_GPIO, - -/* Wakeup caused by UART (light sleep only) */ - - ESP_SLEEP_WAKEUP_UART, -}; - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32_sleep_enable_timer_wakeup - * - * Description: - * Configure wake-up interval - * - * Input Parameters: - * time_in_us - Configure wake-up time interval - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32_sleep_enable_timer_wakeup(uint64_t time_in_us); - -/**************************************************************************** - * Name: esp32_light_sleep_start - * - * Description: - * Enter sleep mode - * - * Input Parameters: - * sleep_time - Actual sleep time - * - * Returned Value: - * 0 is returned on success or a negated errno value is returned - * - ****************************************************************************/ - -int esp32_light_sleep_start(uint64_t *sleep_time); - -/**************************************************************************** - * Name: esp32_pminit - * - * Description: - * Initialize force sleep parameters. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32_pminit(void); - -/**************************************************************************** - * Name: esp32_pmstandby - * - * Description: - * Enter force sleep time interval. - * - * Input Parameters: - * time_in_us - force sleep time interval - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32_pmstandby(uint64_t time_in_us); - -/**************************************************************************** - * Name: esp32_sleep_get_wakeup_cause - * - * Description: - * Get the wakeup source which caused wakeup from sleep. - * - * Input Parameters: - * None - * - * Returned Value: - * enum esp32_sleep_source_e - Cause of wake up from last sleep. - * - ****************************************************************************/ - -enum esp32_sleep_source_e esp32_sleep_get_wakeup_cause(void); - -/**************************************************************************** - * Name: esp32_deep_sleep_start - * - * Description: - * Enter deep sleep mode - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32_deep_sleep_start(void); - -/**************************************************************************** - * Name: esp32_pmsleep - * - * Description: - * Enter deep sleep. - * - * Input Parameters: - * time_in_us - deep sleep time interval - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32_pmsleep(uint64_t time_in_us); - -/**************************************************************************** - * Name: esp32_pm_lockacquire - * - * Description: - * Take a power management lock - * - ****************************************************************************/ - -void esp32_pm_lockacquire(void); - -/**************************************************************************** - * Name: esp32_pm_lockrelease - * - * Description: - * Release the lock taken using esp32_pm_lock. - * - ****************************************************************************/ - -void esp32_pm_lockrelease(void); - -/**************************************************************************** - * Name: esp32_pm_lockstatus - * - * Description: - * Return power management lock status. - * - ****************************************************************************/ - -uint32_t esp32_pm_lockstatus(void); - -#endif /* CONFIG_PM */ - -#ifdef __cplusplus -} -#endif -#undef EXTERN - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_XTENSA_SRC_ESP32_ESP32_PM_H */ diff --git a/arch/xtensa/src/esp32/esp32_pminitialize.c b/arch/xtensa/src/esp32/esp32_pminitialize.c index ab83241c1f492..09cbf129e8562 100644 --- a/arch/xtensa/src/esp32/esp32_pminitialize.c +++ b/arch/xtensa/src/esp32/esp32_pminitialize.c @@ -26,7 +26,7 @@ #include #include "xtensa.h" -#include "esp32_pm.h" +#include "espressif/esp_pm.h" #ifdef CONFIG_PM diff --git a/arch/xtensa/src/esp32/esp32_psram.c b/arch/xtensa/src/esp32/esp32_psram.c index bedf346d681ba..26293bfd0fb26 100644 --- a/arch/xtensa/src/esp32/esp32_psram.c +++ b/arch/xtensa/src/esp32/esp32_psram.c @@ -32,19 +32,18 @@ #include #include "xtensa.h" -#include "xtensa_attr.h" -#include "esp32_rtc.h" -#include "esp32_gpio.h" + +#include "espressif/esp_rtc.h" +#include "esp_gpio.h" #include "esp32_psram.h" #include "hardware/esp32_spi.h" #include "hardware/esp32_dport.h" #include "hardware/esp32_iomux.h" -#include "hardware/esp32_rtccntl.h" +#include "soc/rtc_cntl_reg.h" #include "hardware/esp32_gpio_sigmap.h" #include "rom/esp32_efuse.h" #include "rom/esp32_spiflash.h" -#include "hardware/esp32_efuse.h" #ifdef CONFIG_ESP32_SPIRAM @@ -1144,12 +1143,12 @@ psram_2t_mode_enable(psram_spi_num_t spi_num) */ GPIO_OUTPUT_SET(CONFIG_D0WD_PSRAM_CS_IO, 1); - esp32_gpio_matrix_out(CONFIG_D0WD_PSRAM_CS_IO, SIG_GPIO_OUT_IDX, 0, 0); + esp_gpio_matrix_out(CONFIG_D0WD_PSRAM_CS_IO, SIG_GPIO_OUT_IDX, 0, 0); - esp32_gpio_matrix_out(PSRAM_SPID_SD1_IO, SPIQ_OUT_IDX, 0, 0); - esp32_gpio_matrix_in(PSRAM_SPID_SD1_IO, SPIQ_IN_IDX, 0); - esp32_gpio_matrix_out(PSRAM_SPIQ_SD0_IO, SPID_OUT_IDX, 0, 0); - esp32_gpio_matrix_in(PSRAM_SPIQ_SD0_IO, SPID_IN_IDX, 0); + esp_gpio_matrix_out(PSRAM_SPID_SD1_IO, SPIQ_OUT_IDX, 0, 0); + esp_gpio_matrix_in(PSRAM_SPID_SD1_IO, SPIQ_IN_IDX, 0); + esp_gpio_matrix_out(PSRAM_SPIQ_SD0_IO, SPID_OUT_IDX, 0, 0); + esp_gpio_matrix_in(PSRAM_SPIQ_SD0_IO, SPID_IN_IDX, 0); uint32_t w_data_2t[4] = { @@ -1166,12 +1165,12 @@ psram_2t_mode_enable(psram_spi_num_t spi_num) psram_cmd_recv_start(spi_num, NULL, 0, PSRAM_CMD_SPI); psram_cmd_end(spi_num); - esp32_gpio_matrix_out(PSRAM_SPIQ_SD0_IO, SPIQ_OUT_IDX, 0, 0); - esp32_gpio_matrix_in(PSRAM_SPIQ_SD0_IO, SPIQ_IN_IDX, 0); - esp32_gpio_matrix_out(PSRAM_SPID_SD1_IO, SPID_OUT_IDX, 0, 0); - esp32_gpio_matrix_in(PSRAM_SPID_SD1_IO, SPID_IN_IDX, 0); + esp_gpio_matrix_out(PSRAM_SPIQ_SD0_IO, SPIQ_OUT_IDX, 0, 0); + esp_gpio_matrix_in(PSRAM_SPIQ_SD0_IO, SPIQ_IN_IDX, 0); + esp_gpio_matrix_out(PSRAM_SPID_SD1_IO, SPID_OUT_IDX, 0, 0); + esp_gpio_matrix_in(PSRAM_SPID_SD1_IO, SPID_IN_IDX, 0); - esp32_gpio_matrix_out(CONFIG_D0WD_PSRAM_CS_IO, SPICS1_OUT_IDX, 0, 0); + esp_gpio_matrix_out(CONFIG_D0WD_PSRAM_CS_IO, SPICS1_OUT_IDX, 0, 0); /* setp4: send cmd 0x5f * send one more bit clock after send cmd @@ -1403,16 +1402,16 @@ static void IRAM_ATTR psram_gpio_config(psram_io_t *psram_io, * version. */ - esp32_gpio_matrix_out(psram_io->flash_cs_io, SPICS0_OUT_IDX, 0, 0); - esp32_gpio_matrix_out(psram_io->psram_cs_io, SPICS1_OUT_IDX, 0, 0); - esp32_gpio_matrix_out(psram_io->psram_spiq_sd0_io, SPIQ_OUT_IDX, 0, 0); - esp32_gpio_matrix_in(psram_io->psram_spiq_sd0_io, SPIQ_IN_IDX, 0); - esp32_gpio_matrix_out(psram_io->psram_spid_sd1_io, SPID_OUT_IDX, 0, 0); - esp32_gpio_matrix_in(psram_io->psram_spid_sd1_io, SPID_IN_IDX, 0); - esp32_gpio_matrix_out(psram_io->psram_spiwp_sd3_io, SPIWP_OUT_IDX, 0, 0); - esp32_gpio_matrix_in(psram_io->psram_spiwp_sd3_io, SPIWP_IN_IDX, 0); - esp32_gpio_matrix_out(psram_io->psram_spihd_sd2_io, SPIHD_OUT_IDX, 0, 0); - esp32_gpio_matrix_in(psram_io->psram_spihd_sd2_io, SPIHD_IN_IDX, 0); + esp_gpio_matrix_out(psram_io->flash_cs_io, SPICS0_OUT_IDX, 0, 0); + esp_gpio_matrix_out(psram_io->psram_cs_io, SPICS1_OUT_IDX, 0, 0); + esp_gpio_matrix_out(psram_io->psram_spiq_sd0_io, SPIQ_OUT_IDX, 0, 0); + esp_gpio_matrix_in(psram_io->psram_spiq_sd0_io, SPIQ_IN_IDX, 0); + esp_gpio_matrix_out(psram_io->psram_spid_sd1_io, SPID_OUT_IDX, 0, 0); + esp_gpio_matrix_in(psram_io->psram_spid_sd1_io, SPID_IN_IDX, 0); + esp_gpio_matrix_out(psram_io->psram_spiwp_sd3_io, SPIWP_OUT_IDX, 0, 0); + esp_gpio_matrix_in(psram_io->psram_spiwp_sd3_io, SPIWP_IN_IDX, 0); + esp_gpio_matrix_out(psram_io->psram_spihd_sd2_io, SPIHD_OUT_IDX, 0, 0); + esp_gpio_matrix_in(psram_io->psram_spihd_sd2_io, SPIHD_IN_IDX, 0); /* select pin function gpio */ @@ -1421,23 +1420,23 @@ static void IRAM_ATTR psram_gpio_config(psram_io_t *psram_io, { /* flash clock signal should come from IO MUX. */ - esp32_configgpio(psram_io->flash_clk_io, OUTPUT_FUNCTION_2); + esp_configgpio(psram_io->flash_clk_io, OUTPUT_FUNCTION_2); } else { /* flash clock signal should come from GPIO matrix. */ - esp32_configgpio(psram_io->flash_clk_io, OUTPUT_FUNCTION_3); + esp_configgpio(psram_io->flash_clk_io, OUTPUT_FUNCTION_3); } - esp32_configgpio(psram_io->flash_cs_io, OUTPUT | FUNCTION_3); - esp32_configgpio(psram_io->psram_cs_io, OUTPUT | FUNCTION_3); - esp32_configgpio(psram_io->psram_clk_io, OUTPUT | FUNCTION_3); - esp32_configgpio(psram_io->psram_spiq_sd0_io, OUTPUT | INPUT | FUNCTION_3); - esp32_configgpio(psram_io->psram_spid_sd1_io, OUTPUT | INPUT | FUNCTION_3); - esp32_configgpio(psram_io->psram_spihd_sd2_io, + esp_configgpio(psram_io->flash_cs_io, OUTPUT | FUNCTION_3); + esp_configgpio(psram_io->psram_cs_io, OUTPUT | FUNCTION_3); + esp_configgpio(psram_io->psram_clk_io, OUTPUT | FUNCTION_3); + esp_configgpio(psram_io->psram_spiq_sd0_io, OUTPUT | INPUT | FUNCTION_3); + esp_configgpio(psram_io->psram_spid_sd1_io, OUTPUT | INPUT | FUNCTION_3); + esp_configgpio(psram_io->psram_spihd_sd2_io, OUTPUT | INPUT | FUNCTION_3); - esp32_configgpio(psram_io->psram_spiwp_sd3_io, + esp_configgpio(psram_io->psram_spiwp_sd3_io, OUTPUT | INPUT | FUNCTION_3); #if 0 @@ -1630,7 +1629,7 @@ psram_enable(int mode, int vaddrmode) /* psram init */ switch (mode) { case PSRAM_CACHE_F80M_S80M: - esp32_gpio_matrix_out(psram_io.psram_clk_io, SPICLK_OUT_IDX, 0, 0); + esp_gpio_matrix_out(psram_io.psram_clk_io, SPICLK_OUT_IDX, 0, 0); break; case PSRAM_CACHE_F80M_S40M: case PSRAM_CACHE_F40M_S40M: @@ -1649,21 +1648,21 @@ psram_enable(int mode, int vaddrmode) /* psram init */ */ minfo("clk_mode == PSRAM_CLK_MODE_DCLK\n"); - esp32_gpio_matrix_out(PSRAM_INTERNAL_IO_28, + esp_gpio_matrix_out(PSRAM_INTERNAL_IO_28, SPICLK_OUT_IDX, 0, 0); - esp32_gpio_matrix_in(PSRAM_INTERNAL_IO_28, + esp_gpio_matrix_in(PSRAM_INTERNAL_IO_28, SIG_IN_FUNC224_IDX, 0); - esp32_gpio_matrix_out(PSRAM_INTERNAL_IO_29, + esp_gpio_matrix_out(PSRAM_INTERNAL_IO_29, SIG_IN_FUNC224_IDX, 0, 0); - esp32_gpio_matrix_in(PSRAM_INTERNAL_IO_29, + esp_gpio_matrix_in(PSRAM_INTERNAL_IO_29, SIG_IN_FUNC225_IDX, 0); - esp32_gpio_matrix_out(psram_io.psram_clk_io, + esp_gpio_matrix_out(psram_io.psram_clk_io, SIG_IN_FUNC225_IDX, 0, 0); } else { minfo("clk_io == OUT_IDX\n"); - esp32_gpio_matrix_out(psram_io.psram_clk_io, + esp_gpio_matrix_out(psram_io.psram_clk_io, SPICLK_OUT_IDX, 0, 0); } break; @@ -1706,7 +1705,7 @@ psram_enable(int mode, int vaddrmode) /* psram init */ * ourselves */ - esp32_gpio_matrix_out(psram_io.psram_clk_io, + esp_gpio_matrix_out(psram_io.psram_clk_io, PSRAM_CLK_SIGNAL, 0, 0); /* use spi3 clock,but use spi1 data/cs wires @@ -1737,9 +1736,9 @@ psram_enable(int mode, int vaddrmode) /* psram init */ */ s_clk_mode = PSRAM_CLK_MODE_NORM; - esp32_gpio_matrix_out(PSRAM_INTERNAL_IO_28, SIG_GPIO_OUT_IDX, 0, 0); - esp32_gpio_matrix_out(PSRAM_INTERNAL_IO_29, SIG_GPIO_OUT_IDX, 0, 0); - esp32_gpio_matrix_out(psram_io.psram_clk_io, SPICLK_OUT_IDX, 0, 0); + esp_gpio_matrix_out(PSRAM_INTERNAL_IO_28, SIG_GPIO_OUT_IDX, 0, 0); + esp_gpio_matrix_out(PSRAM_INTERNAL_IO_29, SIG_GPIO_OUT_IDX, 0, 0); + esp_gpio_matrix_out(psram_io.psram_clk_io, SPICLK_OUT_IDX, 0, 0); } /* Update cs timing according to psram driving method. */ diff --git a/arch/xtensa/src/esp32/esp32_qencoder.c b/arch/xtensa/src/esp32/esp32_qencoder.c index cde8c1ad53b01..7ccb558f0f7a9 100644 --- a/arch/xtensa/src/esp32/esp32_qencoder.c +++ b/arch/xtensa/src/esp32/esp32_qencoder.c @@ -38,8 +38,8 @@ #include #include "chip.h" -#include "esp32_gpio.h" -#include "esp32_irq.h" +#include "esp_gpio.h" +#include "esp_irq.h" #include "xtensa.h" #include "hardware/esp32_soc.h" @@ -608,19 +608,19 @@ static int esp32_setup(struct qe_lowerhalf_s *lower) /* Configure GPIO pins as Input with Pull-Up enabled */ - esp32_configgpio(priv->config->ch0_gpio, INPUT_FUNCTION_3 | PULLUP); - esp32_configgpio(priv->config->ch1_gpio, INPUT_FUNCTION_3 | PULLUP); + esp_configgpio(priv->config->ch0_gpio, INPUT_FUNCTION_3 | PULLUP); + esp_configgpio(priv->config->ch1_gpio, INPUT_FUNCTION_3 | PULLUP); /* Connect Channel A (ch0_gpio) and Channel B (ch1_gpio) crossed for X4 */ - esp32_gpio_matrix_in(priv->config->ch0_gpio, + esp_gpio_matrix_in(priv->config->ch0_gpio, priv->config->ch0_pulse_sig, 0); - esp32_gpio_matrix_in(priv->config->ch1_gpio, + esp_gpio_matrix_in(priv->config->ch1_gpio, priv->config->ch0_ctrl_sig, 0); - esp32_gpio_matrix_in(priv->config->ch1_gpio, + esp_gpio_matrix_in(priv->config->ch1_gpio, priv->config->ch1_pulse_sig, 0); - esp32_gpio_matrix_in(priv->config->ch0_gpio, + esp_gpio_matrix_in(priv->config->ch0_gpio, priv->config->ch1_ctrl_sig, 0); /* Clear the Reset bit to enable the Pulse Counter */ diff --git a/arch/xtensa/src/esp32/esp32_resetcause.c b/arch/xtensa/src/esp32/esp32_resetcause.c index 5f0c52e591ccd..762cd1bbbe3e9 100644 --- a/arch/xtensa/src/esp32/esp32_resetcause.c +++ b/arch/xtensa/src/esp32/esp32_resetcause.c @@ -30,7 +30,7 @@ #include #include "xtensa.h" -#include "hardware/esp32_rtccntl.h" +#include "soc/rtc_cntl_reg.h" #include "esp32_resetcause.h" diff --git a/arch/xtensa/src/esp32/esp32_rng.c b/arch/xtensa/src/esp32/esp32_rng.c index 4d83b6a5b3d78..6c776b1a37b28 100644 --- a/arch/xtensa/src/esp32/esp32_rng.c +++ b/arch/xtensa/src/esp32/esp32_rng.c @@ -40,9 +40,8 @@ #include #include "xtensa.h" -#include "xtensa_attr.h" + #include "hardware/wdev_reg.h" -#include "esp32_clockconfig.h" #include "esp_random.h" diff --git a/arch/xtensa/src/esp32/esp32_rt_timer.c b/arch/xtensa/src/esp32/esp32_rt_timer.c deleted file mode 100644 index e923e5c3598eb..0000000000000 --- a/arch/xtensa/src/esp32/esp32_rt_timer.c +++ /dev/null @@ -1,768 +0,0 @@ -/**************************************************************************** - * arch/xtensa/src/esp32/esp32_rt_timer.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this args for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include "hardware/esp32_soc.h" -#include "esp32_tim.h" -#include "esp32_rt_timer.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifdef CONFIG_SCHED_HPWORKPRIORITY -# if CONFIG_ESP32_RT_TIMER_TASK_PRIORITY >= CONFIG_SCHED_HPWORKPRIORITY -# error "RT timer priority should be smaller that high-prio workqueue" -# endif -#endif - -#define RT_TIMER_TASK_NAME CONFIG_ESP32_RT_TIMER_TASK_NAME -#define RT_TIMER_TASK_PRIORITY CONFIG_ESP32_RT_TIMER_TASK_PRIORITY -#define RT_TIMER_TASK_STACK_SIZE CONFIG_ESP32_RT_TIMER_TASK_STACK_SIZE - -#define ESP32_TIMER_PRESCALER (APB_CLK_FREQ / (1000 * 1000)) -#define ESP32_RT_TIMER 0 /* Timer 0 */ - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct esp32_rt_priv_s -{ - pid_t pid; - - sem_t toutsem; - - struct list_node runlist; - struct list_node toutlist; - - spinlock_t lock; - struct esp32_tim_dev_s *timer; -}; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct esp32_rt_priv_s g_rt_priv = -{ - .pid = INVALID_PROCESS_ID, - .toutsem = SEM_INITIALIZER(0), -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: start_rt_timer - * - * Description: - * Start the timer by inserting it into the running list and reset the - * hardware timer alarm value if this timer is at the head of the list. - * - * Input Parameters: - * timer - RT timer pointer - * timeout - Timeout value - * repeat - repeat mode (true: enabled, false: disabled) - * - * Returned Value: - * None. - * - ****************************************************************************/ - -static void start_rt_timer(struct rt_timer_s *timer, - uint64_t timeout, - bool repeat) -{ - struct rt_timer_s *p; - bool inserted = false; - uint64_t counter; - struct esp32_rt_priv_s *priv = &g_rt_priv; - - /* Only idle timer can be started */ - - if (timer->state == RT_TIMER_IDLE) - { - /* Calculate the timer's alarm value */ - - ESP32_TIM_GETCTR(priv->timer, &counter); - timer->timeout = timeout; - timer->alarm = timer->timeout + counter; - - if (repeat) - { - timer->flags |= RT_TIMER_REPEAT; - } - else - { - timer->flags &= ~RT_TIMER_REPEAT; - } - - /* Scan the timer list and insert the new timer into previous - * node of timer whose alarm value is larger than new one - */ - - list_for_every_entry(&priv->runlist, p, struct rt_timer_s, list) - { - if (p->alarm > timer->alarm) - { - list_add_before(&p->list, &timer->list); - inserted = true; - break; - } - } - - /* If we didn't find a larger one, insert the new timer at the tail - * of the list. - */ - - if (!inserted) - { - list_add_tail(&priv->runlist, &timer->list); - } - - timer->state = RT_TIMER_READY; - - /* If this timer is at the head of the list */ - - if (timer == container_of(priv->runlist.next, struct rt_timer_s, list)) - { - /* Reset the hardware timer alarm */ - - ESP32_TIM_SETALRVL(priv->timer, timer->alarm); - ESP32_TIM_SETALRM(priv->timer, true); - } - } -} - -/**************************************************************************** - * Name: stop_rt_timer - * - * Description: - * Stop the timer by removing it from the running list and reset the - * hardware timer alarm value if this timer is at the head of list. - * - * Input Parameters: - * timer - RT timer pointer - * - * Returned Value: - * None. - * - ****************************************************************************/ - -static void stop_rt_timer(struct rt_timer_s *timer) -{ - bool ishead; - struct rt_timer_s *next_timer; - uint64_t alarm; - struct esp32_rt_priv_s *priv = &g_rt_priv; - - /* "start" function can set the timer's repeat flag, and function "stop" - * should remove this flag. - */ - - timer->flags &= ~RT_TIMER_REPEAT; - - /* Only timers in "ready" state can be stopped */ - - if (timer->state == RT_TIMER_READY) - { - /* Check if the timer is at the head of the list */ - - if (timer == container_of(priv->runlist.next, struct rt_timer_s, list)) - { - ishead = true; - } - else - { - ishead = false; - } - - list_delete(&timer->list); - timer->state = RT_TIMER_IDLE; - - /* If the timer is at the head of the list */ - - if (ishead) - { - if (!list_is_empty(&priv->runlist)) - { - /* Set the value from the next timer as the new hardware timer - * alarm value - */ - - next_timer = container_of(priv->runlist.next, - struct rt_timer_s, - list); - alarm = next_timer->alarm; - - ESP32_TIM_SETALRVL(priv->timer, alarm); - ESP32_TIM_SETALRM(priv->timer, true); - } - } - } -} - -/**************************************************************************** - * Name: delete_rt_timer - * - * Description: - * Delete the timer by removing it from the list, then set the timer's - * state to "RT_TIMER_DELETE" and finally insert it into the work list - * to let the rt-timer's thread to delete it and free the resources. - * - * Input Parameters: - * timer - RT timer pointer - * - * Returned Value: - * None. - * - ****************************************************************************/ - -static void delete_rt_timer(struct rt_timer_s *timer) -{ - irqstate_t flags; - struct esp32_rt_priv_s *priv = &g_rt_priv; - - flags = enter_critical_section(); - - if (timer->state == RT_TIMER_READY) - { - stop_rt_timer(timer); - } - else if (timer->state == RT_TIMER_TIMEOUT) - { - list_delete(&timer->list); - } - else if (timer->state == RT_TIMER_DELETE) - { - goto exit; - } - - list_add_after(&priv->toutlist, &timer->list); - timer->state = RT_TIMER_DELETE; - -exit: - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: rt_timer_thread - * - * Description: - * RT timer working thread: Waits for a timeout semaphore, scans - * the timeout list and processes all the timers in the list. - * - * Input Parameters: - * argc - Not used - * argv - Not used - * - * Returned Value: - * 0. - * - ****************************************************************************/ - -static int rt_timer_thread(int argc, char *argv[]) -{ - int ret; - irqstate_t flags; - struct rt_timer_s *timer; - enum rt_timer_state_e raw_state; - struct esp32_rt_priv_s *priv = &g_rt_priv; - - while (1) - { - /* Waiting for all the timers to time out */ - - ret = nxsem_wait(&priv->toutsem); - if (ret) - { - tmrerr("ERROR: Wait priv->toutsem error=%d\n", ret); - ASSERT(0); - } - - flags = spin_lock_irqsave(&priv->lock); - - /* Process all the timers in the list */ - - while (!list_is_empty(&priv->toutlist)) - { - /* Get the first timer in the list */ - - timer = container_of(priv->toutlist.next, struct rt_timer_s, list); - - /* Cache the raw state to decide how to deal with this timer */ - - raw_state = timer->state; - - /* Delete the timer from list */ - - list_delete(&timer->list); - - /* Set timer's state to idle so it can be restarted by the user. */ - - timer->state = RT_TIMER_IDLE; - - spin_unlock_irqrestore(&priv->lock, flags); - - if (raw_state == RT_TIMER_TIMEOUT) - { - timer->callback(timer->arg); - } - else if (raw_state == RT_TIMER_DELETE) - { - kmm_free(timer); - } - - /* Enter critical section for next scanning list */ - - flags = spin_lock_irqsave(&priv->lock); - - if (raw_state == RT_TIMER_TIMEOUT) - { - /* Check if the timer is in "repeat" mode */ - - if (timer->flags & RT_TIMER_REPEAT) - { - start_rt_timer(timer, timer->timeout, true); - } - } - } - - spin_unlock_irqrestore(&priv->lock, flags); - } - - return 0; -} - -/**************************************************************************** - * Name: rt_timer_isr - * - * Description: - * Hardware timer interrupt service routine. - * - * Input Parameters: - * irq - Not used - * context - Not used - * arg - Not used - * - * Returned Value: - * 0. - * - ****************************************************************************/ - -static int rt_timer_isr(int irq, void *context, void *arg) -{ - irqstate_t flags; - struct rt_timer_s *timer; - uint64_t alarm; - uint64_t counter; - struct esp32_rt_priv_s *priv = &g_rt_priv; - - /* Clear interrupt register status */ - - ESP32_TIM_ACKINT(priv->timer); - - /* Wake up the thread to process timed-out timers */ - - nxsem_post(&priv->toutsem); - - flags = spin_lock_irqsave(&priv->lock); - - /* Check if there is a timer running */ - - if (!list_is_empty(&priv->runlist)) - { - /* When stop/delete timer, in the same time the hardware timer - * interrupt triggers, function "stop/delete" remove the timer - * from running list, so the 1st timer is not which triggers. - */ - - timer = container_of(priv->runlist.next, struct rt_timer_s, list); - ESP32_TIM_GETCTR(priv->timer, &counter); - if (timer->alarm <= counter) - { - /* Remove the first timer in the running list and add it to - * the timeout list. - * - * Set the timer's state to be RT_TIMER_TIMEOUT to avoid - * other operations. - */ - - list_delete(&timer->list); - timer->state = RT_TIMER_TIMEOUT; - list_add_after(&priv->toutlist, &timer->list); - - /* Check if there is a timer running */ - - if (!list_is_empty(&priv->runlist)) - { - /* Reset hardware timer alarm with next timer's alarm value */ - - timer = container_of(priv->runlist.next, - struct rt_timer_s, list); - alarm = timer->alarm; - - ESP32_TIM_SETALRVL(priv->timer, alarm); - ESP32_TIM_SETALRM(priv->timer, true); - } - } - } - - spin_unlock_irqrestore(&priv->lock, flags); - - return 0; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: rt_timer_create - * - * Description: - * Create a RT timer from the provided arguments. - * - * Input Parameters: - * args - Input RT timer creation arguments - * timer_handle - Output RT timer handle pointer - * - * Returned Value: - * 0 is returned on success. Otherwise, a negated errno value is returned. - * - ****************************************************************************/ - -int rt_timer_create(const struct rt_timer_args_s *args, - struct rt_timer_s **timer_handle) -{ - struct rt_timer_s *timer; - - timer = kmm_malloc(sizeof(*timer)); - if (!timer) - { - tmrerr("ERROR: Failed to allocate %d bytes\n", sizeof(*timer)); - return -ENOMEM; - } - - timer->callback = args->callback; - timer->arg = args->arg; - timer->flags = RT_TIMER_NOFLAGS; - timer->state = RT_TIMER_IDLE; - list_initialize(&timer->list); - - *timer_handle = timer; - - return 0; -} - -/**************************************************************************** - * Name: rt_timer_start - * - * Description: - * Start the RT timer. - * - * Input Parameters: - * timer - RT timer pointer - * timeout - Timeout value - * repeat - repeat mode (true: enabled, false: disabled) - * - * Returned Value: - * None - * - ****************************************************************************/ - -void rt_timer_start(struct rt_timer_s *timer, - uint64_t timeout, - bool repeat) -{ - irqstate_t flags; - struct esp32_rt_priv_s *priv = &g_rt_priv; - - flags = spin_lock_irqsave(&priv->lock); - - stop_rt_timer(timer); - start_rt_timer(timer, timeout, repeat); - - spin_unlock_irqrestore(&priv->lock, flags); -} - -/**************************************************************************** - * Name: rt_timer_stop - * - * Description: - * Stop the RT timer. - * - * Input Parameters: - * timer - RT timer pointer - * - * Returned Value: - * None - * - ****************************************************************************/ - -void rt_timer_stop(struct rt_timer_s *timer) -{ - irqstate_t flags; - struct esp32_rt_priv_s *priv = &g_rt_priv; - - flags = spin_lock_irqsave(&priv->lock); - stop_rt_timer(timer); - spin_unlock_irqrestore(&priv->lock, flags); -} - -/**************************************************************************** - * Name: rt_timer_delete - * - * Description: - * Stop and delete RT timer. - * - * Input Parameters: - * timer - RT timer pointer - * - * Returned Value: - * None - * - ****************************************************************************/ - -void rt_timer_delete(struct rt_timer_s *timer) -{ - delete_rt_timer(timer); -} - -/**************************************************************************** - * Name: rt_timer_time_us - * - * Description: - * Get time of the RT timer in microseconds. - * - * Input Parameters: - * None - * - * Returned Value: - * Time of the RT timer in microseconds. - * - ****************************************************************************/ - -uint64_t IRAM_ATTR rt_timer_time_us(void) -{ - uint64_t counter; - struct esp32_rt_priv_s *priv = &g_rt_priv; - - ESP32_TIM_GETCTR(priv->timer, &counter); - - return counter; -} - -/**************************************************************************** - * Name: rt_timer_get_alarm - * - * Description: - * Get the timestamp when the next timeout is expected to occur. - * - * Input Parameters: - * None - * - * Returned Value: - * Timestamp of the nearest timer event in microseconds. - * - ****************************************************************************/ - -uint64_t IRAM_ATTR rt_timer_get_alarm(void) -{ - irqstate_t flags; - uint64_t counter; - struct esp32_rt_priv_s *priv = &g_rt_priv; - uint64_t alarm_value = 0; - - flags = spin_lock_irqsave(&priv->lock); - - ESP32_TIM_GETCTR(priv->timer, &counter); - ESP32_TIM_GETALRVL(priv->timer, &alarm_value); - - if (alarm_value <= counter) - { - alarm_value = 0; - } - else - { - alarm_value -= counter; - } - - spin_unlock_irqrestore(&priv->lock, flags); - - return alarm_value; -} - -/**************************************************************************** - * Name: rt_timer_calibration - * - * Description: - * Adjust current RT timer by a certain value. - * - * Input Parameters: - * time_us - adjustment to apply to the RT timer in microseconds. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void IRAM_ATTR rt_timer_calibration(uint64_t time_us) -{ - uint64_t counter; - struct esp32_rt_priv_s *priv = &g_rt_priv; - irqstate_t flags; - - flags = spin_lock_irqsave(&priv->lock); - - ESP32_TIM_GETCTR(priv->timer, &counter); - counter += time_us; - ESP32_TIM_SETCTR(priv->timer, counter); - ESP32_TIM_RLD_NOW(priv->timer); - - spin_unlock_irqrestore(&priv->lock, flags); -} - -/**************************************************************************** - * Name: esp32_rt_timer_init - * - * Description: - * Initialize ESP32 RT timer. - * - * Input Parameters: - * timer_no - Hardware timer number - * - * Returned Value: - * 0 is returned on success. Otherwise, a negated errno value is returned. - * - ****************************************************************************/ - -int esp32_rt_timer_init(void) -{ - int pid; - irqstate_t flags; - struct esp32_tim_dev_s *tim; - struct esp32_rt_priv_s *priv = &g_rt_priv; - - tim = esp32_tim_init(ESP32_RT_TIMER); - if (!tim) - { - tmrerr("ERROR: Failed to initialize ESP32 timer0\n"); - return -EINVAL; - } - - pid = kthread_create(RT_TIMER_TASK_NAME, - RT_TIMER_TASK_PRIORITY, - RT_TIMER_TASK_STACK_SIZE, - rt_timer_thread, - NULL); - if (pid < 0) - { - tmrerr("ERROR: Failed to create RT timer task error=%d\n", pid); - esp32_tim_deinit(tim); - return pid; - } - - list_initialize(&priv->runlist); - list_initialize(&priv->toutlist); - - priv->timer = tim; - priv->pid = (pid_t)pid; - - flags = enter_critical_section(); - - /* ESP32 hardware timer configuration: - * - 1 counter = 1us - * - Counter increase mode - * - Non-reload mode - */ - - ESP32_TIM_SETPRE(tim, ESP32_TIMER_PRESCALER); - ESP32_TIM_SETMODE(tim, ESP32_TIM_MODE_UP); - ESP32_TIM_SETARLD(tim, false); - ESP32_TIM_CLEAR(tim); - - ESP32_TIM_SETISR(tim, rt_timer_isr, NULL); - ESP32_TIM_ENABLEINT(tim); - - ESP32_TIM_START(tim); - - leave_critical_section(flags); - - return 0; -} - -/**************************************************************************** - * Name: esp32_rt_timer_deinit - * - * Description: - * Deinitialize ESP32 RT timer. - * - * Input Parameters: - * None - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp32_rt_timer_deinit(void) -{ - irqstate_t flags; - struct esp32_rt_priv_s *priv = &g_rt_priv; - - flags = spin_lock_irqsave(&priv->lock); - - ESP32_TIM_STOP(priv->timer); - esp32_tim_deinit(priv->timer); - priv->timer = NULL; - - spin_unlock_irqrestore(&priv->lock, flags); - - if (priv->pid != INVALID_PROCESS_ID) - { - kthread_delete(priv->pid); - priv->pid = INVALID_PROCESS_ID; - } -} - diff --git a/arch/xtensa/src/esp32/esp32_rt_timer.h b/arch/xtensa/src/esp32/esp32_rt_timer.h deleted file mode 100644 index 5ca5903d545e9..0000000000000 --- a/arch/xtensa/src/esp32/esp32_rt_timer.h +++ /dev/null @@ -1,244 +0,0 @@ -/**************************************************************************** - * arch/xtensa/src/esp32/esp32_rt_timer.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_XTENSA_SRC_ESP32_ESP32_RT_TIMER_H -#define __ARCH_XTENSA_SRC_ESP32_ESP32_RT_TIMER_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define RT_TIMER_NOFLAGS (0) /* Timer supports no feature */ -#define RT_TIMER_REPEAT (1 << 0) /* Timer supports repeat mode */ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/* RT timer state */ - -enum rt_timer_state_e -{ - RT_TIMER_IDLE, /* Timer is not counting */ - RT_TIMER_READY, /* Timer is counting */ - RT_TIMER_TIMEOUT, /* Timer timed out */ - RT_TIMER_DELETE /* Timer is to be delete */ -}; - -/* RT timer data structure */ - -struct rt_timer_s -{ - uint64_t timeout; /* Timeout value */ - uint64_t alarm; /* Timeout period */ - void (*callback)(void *arg); /* Callback function */ - void *arg; /* Private data */ - uint16_t flags; /* Supported features */ - enum rt_timer_state_e state; /* Timer state */ - struct list_node list; /* Working list */ -}; - -/* RT timer creation arguments data structure */ - -struct rt_timer_args_s -{ - void (*callback)(void *arg); /* Callback function */ - void *arg; /* Private data */ -}; - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: rt_timer_create - * - * Description: - * Create a RT timer from the provided arguments. - * - * Input Parameters: - * args - Input RT timer creation arguments - * timer_handle - Output RT timer handle pointer - * - * Returned Value: - * 0 is returned on success. Otherwise, a negated errno value is returned. - * - ****************************************************************************/ - -int rt_timer_create(const struct rt_timer_args_s *args, - struct rt_timer_s **timer_handle); - -/**************************************************************************** - * Name: rt_timer_start - * - * Description: - * Start the RT timer. - * - * Input Parameters: - * timer - RT timer pointer - * timeout - Timeout value - * repeat - repeat mode (true: enabled, false: disabled) - * - * Returned Value: - * None - * - ****************************************************************************/ - -void rt_timer_start(struct rt_timer_s *timer, - uint64_t timeout, - bool repeat); - -/**************************************************************************** - * Name: rt_timer_stop - * - * Description: - * Stop the RT timer. - * - * Input Parameters: - * timer - RT timer pointer - * - * Returned Value: - * None - * - ****************************************************************************/ - -void rt_timer_stop(struct rt_timer_s *timer); - -/**************************************************************************** - * Name: rt_timer_delete - * - * Description: - * Stop and delete the RT timer. - * - * Input Parameters: - * timer - RT timer pointer - * - * Returned Value: - * None - * - ****************************************************************************/ - -void rt_timer_delete(struct rt_timer_s *timer); - -/**************************************************************************** - * Name: rt_timer_time_us - * - * Description: - * Get time of the RT timer in microseconds. - * - * Input Parameters: - * None - * - * Returned Value: - * Time of the RT timer in microseconds. - * - ****************************************************************************/ - -uint64_t rt_timer_time_us(void); - -/**************************************************************************** - * Name: rt_timer_get_alarm - * - * Description: - * Get the timestamp when the next timeout is expected to occur. - * - * Input Parameters: - * None - * - * Returned Value: - * Timestamp of the nearest timer event in microseconds. - * - ****************************************************************************/ - -uint64_t rt_timer_get_alarm(void); - -/**************************************************************************** - * Name: rt_timer_calibration - * - * Description: - * Adjust current RT timer by a certain value. - * - * Input Parameters: - * time_us - adjustment to apply to the RT timer in microseconds. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void rt_timer_calibration(uint64_t time_us); - -/**************************************************************************** - * Name: esp32_rt_timer_init - * - * Description: - * Initialize ESP32 RT timer. - * - * Input Parameters: - * None - * - * Returned Value: - * 0 is returned on success. Otherwise, a negated errno value is returned. - * - ****************************************************************************/ - -int esp32_rt_timer_init(void); - -/**************************************************************************** - * Name: esp32_rt_timer_deinit - * - * Description: - * Deinitialize ESP32 RT timer. - * - * Input Parameters: - * None - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp32_rt_timer_deinit(void); - -#ifdef __cplusplus -} -#endif -#undef EXTERN - -#endif /* __ARCH_XTENSA_SRC_ESP32_ESP32_RT_TIMER_H */ diff --git a/arch/xtensa/src/esp32/esp32_rtc.c b/arch/xtensa/src/esp32/esp32_rtc.c deleted file mode 100644 index c344d5787c067..0000000000000 --- a/arch/xtensa/src/esp32/esp32_rtc.c +++ /dev/null @@ -1,2277 +0,0 @@ -/**************************************************************************** - * arch/xtensa/src/esp32/esp32_rtc.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include -#include - -#include "clock/clock.h" - -#include "esp32_clockconfig.h" -#include "esp32_rt_timer.h" - -#include "hardware/esp32_apb_ctrl.h" -#include "hardware/esp32_rtccntl.h" -#include "hardware/esp32_rtc_io.h" -#include "hardware/esp32_dport.h" -#include "hardware/esp32_i2s.h" - -#include "xtensa.h" -#include "xtensa_attr.h" - -#include "esp32_rtc.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Various delays to be programmed into power control state machines */ - -#define RTC_CNTL_XTL_BUF_WAIT_SLP 2 -#define RTC_CNTL_CK8M_WAIT_SLP 4 -#define OTHER_BLOCKS_POWERUP 1 -#define OTHER_BLOCKS_WAIT 1 - -#define ROM_RAM_POWERUP_CYCLES OTHER_BLOCKS_POWERUP -#define ROM_RAM_WAIT_CYCLES OTHER_BLOCKS_WAIT - -#define WIFI_POWERUP_CYCLES OTHER_BLOCKS_POWERUP -#define WIFI_WAIT_CYCLES OTHER_BLOCKS_WAIT - -#define RTC_POWERUP_CYCLES OTHER_BLOCKS_POWERUP -#define RTC_WAIT_CYCLES OTHER_BLOCKS_WAIT - -#define DG_WRAP_POWERUP_CYCLES OTHER_BLOCKS_POWERUP -#define DG_WRAP_WAIT_CYCLES OTHER_BLOCKS_WAIT - -#define RTC_MEM_POWERUP_CYCLES OTHER_BLOCKS_POWERUP -#define RTC_MEM_WAIT_CYCLES OTHER_BLOCKS_WAIT - -#define RTC_CNTL_PLL_BUF_WAIT_SLP 2 - -#define DELAY_FAST_CLK_SWITCH 3 - -#define XTAL_32K_DAC_VAL 1 -#define XTAL_32K_DRES_VAL 3 -#define XTAL_32K_DBIAS_VAL 0 - -#define XTAL_32K_EXT_DAC_VAL 2 -#define XTAL_32K_EXT_DRES_VAL 3 -#define XTAL_32K_EXT_DBIAS_VAL 1 - -#define DELAY_SLOW_CLK_SWITCH 300 - -#define DELAY_8M_ENABLE 50 - -#define RETRY_CAL_EXT 1 - -/* Lower threshold for a reasonably-looking calibration value for a 32k XTAL. - * The ideal value (assuming 32768 Hz frequency) - * is 1000000/32768*(2**19) = 16*10^6. - */ - -#define MIN_32K_XTAL_CAL_VAL 15000000L - -/* Frequency of the 8M oscillator is 8.5MHz +/- 5%, at the default DCAP - * setting - */ - -#define RTC_FAST_CLK_FREQ_8M 8500000 -#define RTC_SLOW_CLK_FREQ_150K 150000 -#define RTC_SLOW_CLK_FREQ_8MD256 (RTC_FAST_CLK_FREQ_8M / 256) -#define RTC_SLOW_CLK_FREQ_32K 32768 - -/* Number of fractional bits in values returned by rtc_clk_cal */ - -#define RTC_CLK_CAL_FRACT 19 - -/* With the default value of CK8M_DFREQ, - * 8M clock frequency is 8.5 MHz +/- 7% - */ - -#define RTC_FAST_CLK_FREQ_APPROX 8500000 - -/* Disable logging from the ROM code. */ - -#define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16)) - -/* Default initializer for esp32_rtc_sleep_config_t - * This initializer sets all fields to "reasonable" values - * (e.g. suggested for production use) based on a combination - * of RTC_SLEEP_PD_x flags. - */ - -#define RTC_SLEEP_CONFIG_DEFAULT(sleep_flags) { \ - .lslp_mem_inf_fpu = 0, \ - .rtc_mem_inf_fpu = 0, \ - .rtc_mem_inf_follow_cpu = ((sleep_flags) & RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU) ? 1 : 0, \ - .rtc_fastmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_FAST_MEM) ? 1 : 0, \ - .rtc_slowmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_SLOW_MEM) ? 1 : 0, \ - .rtc_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_PERIPH) ? 1 : 0, \ - .wifi_pd_en = 0, \ - .rom_mem_pd_en = 0, \ - .deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, \ - .wdt_flashboot_mod_en = 0, \ - .dig_dbias_wak = RTC_CNTL_DBIAS_1V10, \ - .dig_dbias_slp = RTC_CNTL_DBIAS_0V90, \ - .rtc_dbias_wak = RTC_CNTL_DBIAS_1V10, \ - .rtc_dbias_slp = RTC_CNTL_DBIAS_0V90, \ - .lslp_meminf_pd = 1, \ - .vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, \ - .xtal_fpu = ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1 \ -} - -/* Initializer for rtc_sleep_pd_config_t which - * sets all flags to the same value - */ - -#define RTC_SLEEP_PD_CONFIG_ALL(val) {\ - .dig_pd = (val), \ - .rtc_pd = (val), \ - .cpu_pd = (val), \ - .i2s_pd = (val), \ - .bb_pd = (val), \ - .nrx_pd = (val), \ - .fe_pd = (val), \ -} - -/* The magic data for the struct esp32_rtc_backup_s that is in RTC slow - * memory. - */ - -#define MAGIC_RTC_SAVE UINT64_C(0x11223344556677) - -/* RTC Memory & Store Register usage */ - -#define RTC_SLOW_CLK_CAL_REG RTC_CNTL_STORE1_REG /* RTC_SLOW_CLK calibration value */ -#define RTC_BOOT_TIME_LOW_REG RTC_CNTL_STORE2_REG /* Boot time, low word */ -#define RTC_BOOT_TIME_HIGH_REG RTC_CNTL_STORE3_REG /* Boot time, high word */ -#define RTC_XTAL_FREQ_REG RTC_CNTL_STORE4_REG /* External XTAL frequency */ -#define RTC_APB_FREQ_REG RTC_CNTL_STORE5_REG /* APB bus frequency */ -#define RTC_ENTRY_ADDR_REG RTC_CNTL_STORE6_REG /* FAST_RTC_MEMORY_ENTRY */ -#define RTC_RESET_CAUSE_REG RTC_CNTL_STORE6_REG -#define RTC_MEMORY_CRC_REG RTC_CNTL_STORE7_REG /* FAST_RTC_MEMORY_CRC */ - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* RTC power and clock control initialization settings */ - -struct esp32_rtc_priv_s -{ - uint32_t ck8m_wait : 8; /* Number of rtc_fast_clk cycles to wait for 8M clock to be ready */ - uint32_t xtal_wait : 8; /* Number of rtc_fast_clk cycles to wait for XTAL clock to be ready */ - uint32_t pll_wait : 8; /* Number of rtc_fast_clk cycles to wait for PLL to be ready */ - uint32_t clkctl_init : 1; /* Perform clock control related initialization */ - uint32_t pwrctl_init : 1; /* Perform power control related initialization */ - uint32_t rtc_dboost_fpd : 1; /* Force power down RTC_DBOOST */ -}; - -/* sleep configuration for rtc_sleep_init function */ - -struct esp32_rtc_sleep_config_s -{ - uint32_t lslp_mem_inf_fpu : 1; /* force normal voltage in sleep mode (digital domain memory) */ - uint32_t rtc_mem_inf_fpu : 1; /* force normal voltage in sleep mode (RTC memory) */ - uint32_t rtc_mem_inf_follow_cpu : 1; /* keep low voltage in sleep mode (even if ULP/touch is used) */ - uint32_t rtc_fastmem_pd_en : 1; /* power down RTC fast memory */ - uint32_t rtc_slowmem_pd_en : 1; /* power down RTC slow memory */ - uint32_t rtc_peri_pd_en : 1; /* power down RTC peripherals */ - uint32_t wifi_pd_en : 1; /* power down Wi-Fi */ - uint32_t rom_mem_pd_en : 1; /* power down main RAM and ROM */ - uint32_t deep_slp : 1; /* power down digital domain */ - uint32_t wdt_flashboot_mod_en : 1; /* enable WDT flashboot mode */ - uint32_t dig_dbias_wak : 3; /* set bias for digital domain, in active mode */ - uint32_t dig_dbias_slp : 3; /* set bias for digital domain, in sleep mode */ - uint32_t rtc_dbias_wak : 3; /* set bias for RTC domain, in active mode */ - uint32_t rtc_dbias_slp : 3; /* set bias for RTC domain, in sleep mode */ - uint32_t lslp_meminf_pd : 1; /* remove all peripheral force power up flags */ - uint32_t vddsdio_pd_en : 1; /* power down VDDSDIO regulator */ - uint32_t xtal_fpu : 1; /* keep main XTAL powered up in sleep */ -}; - -/* Power down flags for rtc_sleep_pd function */ - -struct esp32_rtc_sleep_pd_config_s -{ - uint32_t dig_pd : 1; /* Set to 1 to power down digital part in sleep */ - uint32_t rtc_pd : 1; /* Set to 1 to power down RTC memories in sleep */ - uint32_t cpu_pd : 1; /* Set to 1 to power down digital memories and CPU in sleep */ - uint32_t i2s_pd : 1; /* Set to 1 to power down I2S in sleep */ - uint32_t bb_pd : 1; /* Set to 1 to power down Wi-Fi in sleep */ - uint32_t nrx_pd : 1; /* Set to 1 to power down Wi-Fi in sleep */ - uint32_t fe_pd : 1; /* Set to 1 to power down Wi-Fi in sleep */ -}; - -#ifdef CONFIG_RTC_ALARM -struct alm_cbinfo_s -{ - struct rt_timer_s *alarm_hdl; /* Timer id point to here */ - volatile alm_callback_t ac_cb; /* Client callback function */ - volatile void *ac_arg; /* Argument to pass with the callback function */ - uint64_t deadline_us; - uint8_t index; -}; -#endif - -struct esp32_rtc_backup_s -{ - uint64_t magic; - int64_t offset; /* Offset time from RTC HW value */ - int64_t reserved0; -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static void IRAM_ATTR esp32_rtc_sleep_pd( - struct esp32_rtc_sleep_pd_config_s cfg); -static inline bool esp32_clk_val_is_valid(uint32_t val); -static void IRAM_ATTR esp32_rtc_clk_fast_freq_set( - enum esp32_rtc_fast_freq_e fast_freq); -static uint32_t IRAM_ATTR esp32_rtc_clk_cal_internal( - enum esp32_rtc_cal_sel_e cal_clk, uint32_t slowclk_cycles); -static void IRAM_ATTR esp32_rtc_clk_slow_freq_set( - enum esp32_rtc_slow_freq_e slow_freq); -static void esp32_select_rtc_slow_clk(enum esp32_slow_clk_sel_e slow_clk); -static void esp32_rtc_clk_32k_enable(int ac, int res, int bias); -static void IRAM_ATTR esp32_rtc_clk_8m_enable(bool clk_8m_en, bool d256_en); - -#ifdef CONFIG_RTC_ALARM -static void IRAM_ATTR esp32_rt_cb_handler(void *arg); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct esp32_rtc_priv_s esp32_rtc_priv = -{ - .ck8m_wait = RTC_CNTL_CK8M_WAIT_DEFAULT, - .xtal_wait = RTC_CNTL_XTL_BUF_WAIT_DEFAULT, - .pll_wait = RTC_CNTL_PLL_BUF_WAIT_DEFAULT, - .clkctl_init = 1, - .pwrctl_init = 1, - .rtc_dboost_fpd = 1 -}; - -/* Callback to use when the alarm expires */ - -#ifdef CONFIG_RTC_ALARM -static struct alm_cbinfo_s g_alarmcb[RTC_ALARM_LAST]; -#endif - -static RTC_DATA_ATTR struct esp32_rtc_backup_s rtc_saved_data; - -/* Saved data for persistent RTC time */ - -static struct esp32_rtc_backup_s *g_rtc_save; -static bool g_rt_timer_enabled = false; -static spinlock_t g_rtc_lock = SP_UNLOCKED; - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -volatile bool g_rtc_enabled = false; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32_rtc_sleep_pd - * - * Description: - * Configure whether certain peripherals are powered down in deep sleep. - * - * Input Parameters: - * cfg - power down flags as rtc_sleep_pd_config_t structure - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void IRAM_ATTR esp32_rtc_sleep_pd( - struct esp32_rtc_sleep_pd_config_s cfg) -{ - REG_SET_FIELD(RTC_CNTL_DIG_PWC_REG, - RTC_CNTL_LSLP_MEM_FORCE_PU, ~cfg.dig_pd); - REG_SET_FIELD(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_LPU, ~cfg.rtc_pd); - REG_SET_FIELD(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_LPU, ~cfg.rtc_pd); - REG_SET_FIELD(DPORT_MEM_PD_MASK_REG, DPORT_LSLP_MEM_PD_MASK, ~cfg.cpu_pd); - REG_SET_FIELD(I2S_PD_CONF_REG(0), I2S_PLC_MEM_FORCE_PU, ~cfg.i2s_pd); - REG_SET_FIELD(I2S_PD_CONF_REG(0), I2S_FIFO_FORCE_PU, ~cfg.i2s_pd); - REG_SET_FIELD(BBPD_CTRL, BB_FFT_FORCE_PU, ~cfg.bb_pd); - REG_SET_FIELD(BBPD_CTRL, BB_DC_EST_FORCE_PU, ~cfg.bb_pd); - REG_SET_FIELD(NRXPD_CTRL, NRX_RX_ROT_FORCE_PU, ~cfg.nrx_pd); - REG_SET_FIELD(NRXPD_CTRL, NRX_VIT_FORCE_PU, ~cfg.nrx_pd); - REG_SET_FIELD(NRXPD_CTRL, NRX_DEMAP_FORCE_PU, ~cfg.nrx_pd); - REG_SET_FIELD(FE_GEN_CTRL, FE_IQ_EST_FORCE_PU, ~cfg.fe_pd); - REG_SET_FIELD(FE2_TX_INTERP_CTRL, FE2_TX_INF_FORCE_PU, ~cfg.fe_pd); -} - -/**************************************************************************** - * Name: esp32_rtc_clk_fast_freq_set - * - * Description: - * Select source for RTC_FAST_CLK. - * - * Input Parameters: - * cfg - Clock source (one of enum esp32_rtc_fast_freq_e values) - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void IRAM_ATTR esp32_rtc_clk_fast_freq_set( - enum esp32_rtc_fast_freq_e fast_freq) -{ - REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL, fast_freq); - up_udelay(DELAY_FAST_CLK_SWITCH); -} - -/**************************************************************************** - * Name: esp32_clk_val_is_valid - * - * Description: - * Values of RTC_XTAL_FREQ_REG and RTC_APB_FREQ_REG are - * stored as two copies in lower and upper 16-bit halves. - * These are the routines to work with such a representation. - * - * Input Parameters: - * val - register value - * - * Returned Value: - * true: Valid register value. - * false: Invalid register value. - * - ****************************************************************************/ - -static inline bool esp32_clk_val_is_valid(uint32_t val) -{ - return (val & 0xffff) == ((val >> 16) & 0xffff) - && val != 0 && val != UINT32_MAX; -} - -/**************************************************************************** - * Name: esp32_rtc_clk_cal_internal - * - * Description: - * Clock calibration function used by rtc_clk_cal and rtc_clk_cal_ratio - * - * Input Parameters: - * cal_clk - which clock to calibrate - * slowclk_cycles - number of slow clock cycles to count. - * - * Returned Value: - * Number of XTAL clock cycles within the given number of slow clock - * cycles. - * In case of error, return 0 cycle. - * - ****************************************************************************/ - -static uint32_t IRAM_ATTR esp32_rtc_clk_cal_internal( - enum esp32_rtc_cal_sel_e cal_clk, uint32_t slowclk_cycles) -{ - uint32_t expected_freq; - uint32_t us_time_estimate; - uint32_t us_timer_max; - uint32_t clks_state; - uint32_t clks_mask; - int timeout_us; - enum esp32_rtc_slow_freq_e slow_freq; - enum esp32_rtc_xtal_freq_e xtal_freq; - - /* Get the current state */ - - clks_mask = (RTC_CNTL_DIG_XTAL32K_EN_M | RTC_CNTL_DIG_CLK8M_D256_EN_M); - clks_state = getreg32(RTC_CNTL_CLK_CONF_REG); - clks_state &= clks_mask; - - /* Enable requested clock (150k clock is always on) */ - - if (cal_clk == RTC_CAL_32K_XTAL && !(clks_state & RTC_CNTL_DIG_XTAL32K_EN)) - { - REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN, 1); - } - else if (cal_clk == RTC_CAL_8MD256 && - !(clks_state & RTC_CNTL_DIG_CLK8M_D256_EN)) - { - modifyreg32(RTC_CNTL_CLK_CONF_REG, 0, RTC_CNTL_DIG_CLK8M_D256_EN); - } - - /* Prepare calibration */ - - REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, cal_clk); - modifyreg32(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING, 0); - REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, slowclk_cycles); - - /* Figure out how long to wait for calibration to finish */ - - slow_freq = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL); - - if (cal_clk == RTC_CAL_32K_XTAL || slow_freq == RTC_SLOW_FREQ_32K_XTAL) - { - expected_freq = 32768; /* standard 32k XTAL */ - } - else if (cal_clk == RTC_CAL_8MD256 || slow_freq == RTC_SLOW_FREQ_8MD256) - { - expected_freq = RTC_FAST_CLK_FREQ_APPROX / 256; - } - else - { - expected_freq = 150000; /* 150k internal oscillator */ - } - - us_time_estimate = (uint32_t) (((uint64_t) slowclk_cycles) * - MHZ / expected_freq); - - /* Check if the required number of slowclk_cycles - * may result in an overflow of TIMG_RTC_CALI_VALUE. - */ - - xtal_freq = esp32_rtc_clk_xtal_freq_get(); - if (xtal_freq == RTC_XTAL_FREQ_AUTO) - { - /* XTAL frequency is not known yet; assume worst case (40 MHz) */ - - xtal_freq = RTC_XTAL_FREQ_40M; - } - - us_timer_max = TIMG_RTC_CALI_VALUE / (uint32_t) xtal_freq; - - if (us_time_estimate >= us_timer_max) - { - rtcerr("Estimated time overflows TIMG_RTC_CALI_VALUE\n"); - return 0; - } - - /* Start calibration */ - - modifyreg32(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START, 0); - modifyreg32(TIMG_RTCCALICFG_REG(0), 0, TIMG_RTC_CALI_START); - - /* Wait the expected time calibration should take */ - - up_udelay(us_time_estimate); - - /* Wait for calibration to finish up to another us_time_estimate */ - - timeout_us = us_time_estimate; - while (!(getreg32(TIMG_RTCCALICFG_REG(0)) & - TIMG_RTC_CALI_RDY) && (timeout_us > 0)) - { - timeout_us--; - up_udelay(1); - } - - /* Restore the previous clocks states */ - - modifyreg32(RTC_CNTL_CLK_CONF_REG, clks_mask, clks_state); - - /* Verify if this calibration occurred within the timeout */ - - if (timeout_us == 0) - { - /* Timed out waiting for calibration */ - - rtcerr("Timed out waiting for calibration\n"); - return 0; - } - - return REG_GET_FIELD(TIMG_RTCCALICFG1_REG(0), TIMG_RTC_CALI_VALUE); -} - -/**************************************************************************** - * Name: esp32_rtc_clk_slow_freq_set - * - * Description: - * Select source for RTC_SLOW_CLK - * - * Input Parameters: - * slow_freq - Select source for RTC_SLOW_CLK - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void IRAM_ATTR esp32_rtc_clk_slow_freq_set( - enum esp32_rtc_slow_freq_e slow_freq) -{ - REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL, slow_freq); - - REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN, - (slow_freq == RTC_SLOW_FREQ_32K_XTAL) ? 1 : 0); - - up_udelay(DELAY_SLOW_CLK_SWITCH); -} - -/**************************************************************************** - * Name: esp32_rtc_clk_32k_enable - * - * Description: - * Enable 32 kHz XTAL oscillator - * - * Input Parameters: - * ac - The current of XTAL oscillator. - * res - The resistance of XTAL oscillator. - * bias - The bias voltage of XTAL oscillator. - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void esp32_rtc_clk_32k_enable(int ac, int res, int bias) -{ - modifyreg32(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_X32P_RDE | RTC_IO_X32P_RUE | - RTC_IO_X32N_RUE | RTC_IO_X32N_RDE | RTC_IO_X32N_FUN_IE | - RTC_IO_X32P_FUN_IE, RTC_IO_X32N_MUX_SEL | RTC_IO_X32P_MUX_SEL); - - /* Set the parameters of xtal */ - - REG_SET_FIELD(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_DAC_XTAL_32K, ac); - REG_SET_FIELD(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_DRES_XTAL_32K, res); - REG_SET_FIELD(RTC_IO_XTAL_32K_PAD_REG, RTC_IO_DBIAS_XTAL_32K, bias); - - /* Power up external xtal */ - - modifyreg32(RTC_IO_XTAL_32K_PAD_REG, 0, RTC_IO_XPD_XTAL_32K_M); -} - -/**************************************************************************** - * Name: esp32_rtc_clk_8m_enable - * - * Description: - * Enable or disable 8 MHz internal oscillator - * - * Input Parameters: - * clk_8m_en - true to enable 8MHz generator, false to disable - * d256_en - true to enable /256 divider, false to disable - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void IRAM_ATTR esp32_rtc_clk_8m_enable(bool clk_8m_en, bool d256_en) -{ - if (clk_8m_en) - { - modifyreg32(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M, 0); - - /* no need to wait once enabled by software */ - - REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, 1); - if (d256_en) - { - modifyreg32(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV, 0); - } - else - { - modifyreg32(RTC_CNTL_CLK_CONF_REG, 0, RTC_CNTL_ENB_CK8M_DIV); - } - - up_udelay(DELAY_8M_ENABLE); - } - else - { - modifyreg32(RTC_CNTL_CLK_CONF_REG, 0, RTC_CNTL_ENB_CK8M); - REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, - RTC_CNTL_CK8M_WAIT_DEFAULT); - } -} - -/**************************************************************************** - * Name: esp32_select_rtc_slow_clk - * - * Description: - * Selects an clock source for RTC. - * - * Input Parameters: - * slow_clk - RTC SLOW_CLK frequency values - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void esp32_select_rtc_slow_clk(enum esp32_slow_clk_sel_e slow_clk) -{ - /* Number of times to repeat 32k XTAL calibration before giving up and - * switching to the internal RC. - */ - - int retry_32k_xtal = RETRY_CAL_EXT; - uint32_t cal_val = 0; - uint64_t cal_dividend; - enum esp32_rtc_slow_freq_e rtc_slow_freq = slow_clk & - RTC_CNTL_ANA_CLK_RTC_SEL_V; - - do - { - if (rtc_slow_freq == RTC_SLOW_FREQ_32K_XTAL) - { - /* 32k XTAL oscillator needs to be enabled and running before - * it can be used. Hardware doesn't have a direct way of checking - * if the oscillator is running. Here we use rtc_clk_cal function - * to count the number of main XTAL cycles in the given number of - * 32k XTAL oscillator cycles. If the 32k XTAL has not started up, - * calibration will time out, returning 0. - */ - - rtcinfo("Waiting for 32k oscillator to start up\n"); - if (slow_clk == SLOW_CLK_32K_XTAL) - { - esp32_rtc_clk_32k_enable(XTAL_32K_DAC_VAL, XTAL_32K_DRES_VAL, - XTAL_32K_DBIAS_VAL); - } - else if (slow_clk == SLOW_CLK_32K_EXT_OSC) - { - esp32_rtc_clk_32k_enable(XTAL_32K_EXT_DAC_VAL, - XTAL_32K_EXT_DRES_VAL, XTAL_32K_EXT_DBIAS_VAL); - } - - if (SLOW_CLK_CAL_CYCLES > 0) - { - cal_val = esp32_rtc_clk_cal(RTC_CAL_32K_XTAL, - SLOW_CLK_CAL_CYCLES); - if (cal_val == 0 || cal_val < MIN_32K_XTAL_CAL_VAL) - { - if (retry_32k_xtal-- > 0) - { - continue; - } - - rtc_slow_freq = RTC_SLOW_FREQ_RTC; - } - } - } - else if (rtc_slow_freq == RTC_SLOW_FREQ_8MD256) - { - esp32_rtc_clk_8m_enable(true, true); - } - - esp32_rtc_clk_slow_freq_set(rtc_slow_freq); - if (SLOW_CLK_CAL_CYCLES > 0) - { - /* 32k XTAL oscillator has some frequency drift at startup. Improve - * calibration routine to wait until the frequency is stable. - */ - - cal_val = esp32_rtc_clk_cal(RTC_CAL_RTC_MUX, - SLOW_CLK_CAL_CYCLES); - } - else - { - cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL; - cal_val = (uint32_t) (cal_dividend / - esp32_rtc_clk_slow_freq_get_hz()); - } - } - while (cal_val == 0); - rtcinfo("RTC_SLOW_CLK calibration value: %" PRIu32 "\n", cal_val); - putreg32((uint32_t)cal_val, RTC_SLOW_CLK_CAL_REG); -} - -#ifdef CONFIG_RTC_ALARM - -/**************************************************************************** - * Name: esp32_rt_cb_handler - * - * Description: - * RT-Timer service routine - * - * Input Parameters: - * arg - Information about the RT-Timer configuration. - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void IRAM_ATTR esp32_rt_cb_handler(void *arg) -{ - struct alm_cbinfo_s *cbinfo = (struct alm_cbinfo_s *)arg; - alm_callback_t cb; - void *cb_arg; - int alminfo_id; - - DEBUGASSERT(cbinfo != NULL); - alminfo_id = cbinfo->index; - DEBUGASSERT((RTC_ALARM0 <= alminfo_id) && - (alminfo_id < RTC_ALARM_LAST)); - - if (cbinfo->ac_cb != NULL) - { - /* Alarm callback */ - - cb = cbinfo->ac_cb; - cb_arg = (void *)cbinfo->ac_arg; - cbinfo->ac_cb = NULL; - cbinfo->ac_arg = NULL; - cbinfo->deadline_us = 0; - cb(cb_arg, alminfo_id); - } -} - -#endif /* CONFIG_RTC_ALARM */ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32_rtc_clk_slow_freq_get_hz - * - * Description: - * Get the approximate frequency of RTC_SLOW_CLK, in Hz - * - * Input Parameters: - * None - * - * Returned Value: - * slow_clk_freq - RTC_SLOW_CLK frequency, in Hz - * - ****************************************************************************/ - -uint32_t IRAM_ATTR esp32_rtc_clk_slow_freq_get_hz(void) -{ - enum esp32_rtc_slow_freq_e slow_clk_freq = - REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL); - switch (slow_clk_freq) - { - case RTC_SLOW_FREQ_RTC: - return RTC_SLOW_CLK_FREQ_150K; - - case RTC_SLOW_FREQ_32K_XTAL: - return RTC_SLOW_CLK_FREQ_32K; - - case RTC_SLOW_FREQ_8MD256: - return RTC_SLOW_CLK_FREQ_8MD256; - } - - return OK; -} - -/**************************************************************************** - * Name: esp32_rtc_clk_fast_freq_get_hz - * - * Description: - * Get fast_clk_rtc source in Hz. - * - * Input Parameters: - * None - * - * Returned Value: - * The clock source in Hz. - * - ****************************************************************************/ - -uint32_t IRAM_ATTR esp32_rtc_clk_fast_freq_get_hz(void) -{ - return RTC_FAST_CLK_FREQ_APPROX; -} - -/**************************************************************************** - * Name: esp32_rtc_get_slow_clk_rtc - * - * Description: - * Get slow_clk_rtc source. - * - * Input Parameters: - * None - * - * Returned Value: - * The clock source: - * - SLOW_CK - * - CK_XTAL_32K - * - CK8M_D256_OUT - * - ****************************************************************************/ - -enum esp32_rtc_slow_freq_e IRAM_ATTR esp32_rtc_get_slow_clk(void) -{ - enum esp32_rtc_slow_freq_e slow_freq; - - /* Get the clock source for slow_clk_rtc */ - - slow_freq = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL); - - return slow_freq; -} - -/**************************************************************************** - * Name: esp32_rtc_clk_cal - * - * Description: - * Measure RTC slow clock's period, based on main XTAL frequency - * - * Input Parameters: - * cal_clk - clock to be measured - * slowclk_cycles - number of slow clock cycles to average - * - * Returned Value: - * Average slow clock period in microseconds, Q13.19 fixed point format - * or 0 if calibration has timed out - * - ****************************************************************************/ - -uint32_t IRAM_ATTR esp32_rtc_clk_cal(enum esp32_rtc_cal_sel_e cal_clk, - uint32_t slowclk_cycles) -{ - enum esp32_rtc_xtal_freq_e xtal_freq; - uint64_t xtal_cycles; - uint64_t divider; - uint64_t period_64; - uint32_t period; - - xtal_freq = esp32_rtc_clk_xtal_freq_get(); - xtal_cycles = esp32_rtc_clk_cal_internal(cal_clk, slowclk_cycles); - divider = ((uint64_t)xtal_freq) * slowclk_cycles; - period_64 = ((xtal_cycles << RTC_CLK_CAL_FRACT) + divider / 2 - 1) - / divider; - period = (uint32_t)(period_64 & UINT32_MAX); - - return period; -} - -/**************************************************************************** - * Name: esp32_rtc_clk_xtal_freq_get - * - * Description: - * Get main XTAL frequency - * - * Input Parameters: - * None - * - * Returned Value: - * XTAL frequency (one of enum esp32_rtc_xtal_freq_e values) - * - ****************************************************************************/ - -enum esp32_rtc_xtal_freq_e IRAM_ATTR esp32_rtc_clk_xtal_freq_get(void) -{ - /* We may have already written XTAL value into RTC_XTAL_FREQ_REG */ - - uint32_t xtal_freq_reg = getreg32(RTC_XTAL_FREQ_REG); - - if (!esp32_clk_val_is_valid(xtal_freq_reg)) - { - return RTC_XTAL_FREQ_AUTO; - } - - return (xtal_freq_reg & ~RTC_DISABLE_ROM_LOG) & UINT16_MAX; -} - -/**************************************************************************** - * Name: esp32_rtc_update_to_xtal - * - * Description: - * Switch to XTAL frequency, does not disable the PLL - * - * Input Parameters: - * freq - XTAL frequency - * div - REF_TICK divider - * - * Returned Value: - * none - * - ****************************************************************************/ - -void IRAM_ATTR esp32_rtc_update_to_xtal(int freq, int div) -{ - uint32_t value = (((freq * MHZ) >> 12) & UINT16_MAX) - | ((((freq * MHZ) >> 12) & UINT16_MAX) << 16); - esp32_update_cpu_freq(freq); - - /* set divider from XTAL to APB clock */ - - REG_SET_FIELD(APB_CTRL_SYSCLK_CONF_REG, APB_CTRL_PRE_DIV_CNT, div - 1); - - /* adjust ref_tick */ - - modifyreg32(APB_CTRL_XTAL_TICK_CONF_REG, 0, - (freq * MHZ) / REF_CLK_FREQ - 1); - - /* switch clock source */ - - REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL, - RTC_CNTL_SOC_CLK_SEL_XTL); - putreg32(value, RTC_APB_FREQ_REG); - - /* lower the voltage */ - - if (freq <= 2) - { - REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_2M); - } - else - { - REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_XTAL); - } -} - -/**************************************************************************** - * Name: esp32_rtc_bbpll_enable - * - * Description: - * Reset BBPLL configuration. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void IRAM_ATTR esp32_rtc_bbpll_enable(void) -{ - modifyreg32(RTC_CNTL_OPTIONS0_REG, - RTC_CNTL_BIAS_I2C_FORCE_PD | RTC_CNTL_BB_I2C_FORCE_PD | - RTC_CNTL_BBPLL_FORCE_PD | RTC_CNTL_BBPLL_I2C_FORCE_PD, 0); - - /* reset BBPLL configuration */ - - I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_IR_CAL_DELAY, - BBPLL_IR_CAL_DELAY_VAL); - I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_IR_CAL_EXT_CAP, - BBPLL_IR_CAL_EXT_CAP_VAL); - I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_ENB_FCAL, - BBPLL_OC_ENB_FCAL_VAL); - I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_ENB_VCON, - BBPLL_OC_ENB_VCON_VAL); - I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_BBADC_CAL_7_0, - BBPLL_BBADC_CAL_7_0_VAL); -} - -/**************************************************************************** - * Name: esp32_rtc_bbpll_configure - * - * Description: - * Configure main XTAL frequency values according to pll_freq. - * - * Input Parameters: - * xtal_freq - XTAL frequency values - * pll_freq - PLL frequency values - * - * Returned Value: - * None - * - ****************************************************************************/ - -void IRAM_ATTR esp32_rtc_bbpll_configure( - enum esp32_rtc_xtal_freq_e xtal_freq, int pll_freq) -{ - static uint8_t div_ref = 0; - static uint8_t div7_0 = 0; - static uint8_t div10_8 = 0; - static uint8_t lref = 0 ; - static uint8_t dcur = 0; - static uint8_t bw = 0; - uint8_t i2c_bbpll_lref = 0; - uint8_t i2c_bbpll_div_7_0 = 0; - uint8_t i2c_bbpll_dcur = 0; - - if (pll_freq == RTC_PLL_FREQ_320M) - { - /* Raise the voltage, if needed */ - - REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, - DIG_DBIAS_80M_160M); - - /* Configure 320M PLL */ - - switch (xtal_freq) - { - case RTC_XTAL_FREQ_40M: - { - div_ref = 0; - div7_0 = 32; - div10_8 = 0; - lref = 0; - dcur = 6; - bw = 3; - } - break; - - case RTC_XTAL_FREQ_26M: - { - div_ref = 12; - div7_0 = 224; - div10_8 = 4; - lref = 1; - dcur = 0; - bw = 1; - } - break; - - case RTC_XTAL_FREQ_24M: - { - div_ref = 11; - div7_0 = 224; - div10_8 = 4; - lref = 1; - dcur = 0; - bw = 1; - } - break; - - default: - { - div_ref = 12; - div7_0 = 224; - div10_8 = 4; - lref = 0; - dcur = 0; - bw = 0; - } - break; - } - - I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_ENDIV5, BBPLL_ENDIV5_VAL_320M); - I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_BBADC_DSMP, - BBPLL_BBADC_DSMP_VAL_320M); - } - else - { - /* Raise the voltage */ - - REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_240M); - up_udelay(DELAY_PLL_DBIAS_RAISE); - - /* Configure 480M PLL */ - - switch (xtal_freq) - { - case RTC_XTAL_FREQ_40M: - { - div_ref = 0; - div7_0 = 28; - div10_8 = 0; - lref = 0; - dcur = 6; - bw = 3; - } - break; - - case RTC_XTAL_FREQ_26M: - { - div_ref = 12; - div7_0 = 144; - div10_8 = 4; - lref = 1; - dcur = 0; - bw = 1; - } - break; - - case RTC_XTAL_FREQ_24M: - { - div_ref = 11; - div7_0 = 144; - div10_8 = 4; - lref = 1; - dcur = 0; - bw = 1; - } - break; - - default: - { - div_ref = 12; - div7_0 = 224; - div10_8 = 4; - lref = 0; - dcur = 0; - bw = 0; - } - break; - } - - I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_ENDIV5, BBPLL_ENDIV5_VAL_480M); - I2C_WRITEREG_RTC(I2C_BBPLL, - I2C_BBPLL_BBADC_DSMP, BBPLL_BBADC_DSMP_VAL_480M); - } - - i2c_bbpll_lref = (lref << 7) | (div10_8 << 4) | (div_ref); - i2c_bbpll_div_7_0 = div7_0; - i2c_bbpll_dcur = (bw << 6) | dcur; - I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_LREF, i2c_bbpll_lref); - I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_DIV_7_0, i2c_bbpll_div_7_0); - I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_DCUR, i2c_bbpll_dcur); -} - -/**************************************************************************** - * Name: esp32_rtc_clk_set - * - * Description: - * Set RTC CLK frequency. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32_rtc_clk_set(void) -{ - enum esp32_rtc_fast_freq_e fast_freq = RTC_FAST_FREQ_8M; - enum esp32_slow_clk_sel_e slow_clk = SLOW_CLK_150K; - -#if defined(CONFIG_ESP32_RTC_CLK_SRC_EXT_XTAL) - slow_clk = SLOW_CLK_32K_XTAL; -#elif defined(CONFIG_ESP32_RTC_CLK_SRC_EXT_OSC) - slow_clk = SLOW_CLK_32K_EXT_OSC; -#elif defined(CONFIG_ESP32_RTC_CLK_SRC_INT_8MD256) - slow_clk = SLOW_CLK_8MD256; -#endif - - esp32_rtc_clk_fast_freq_set(fast_freq); - esp32_select_rtc_slow_clk(slow_clk); -} - -/**************************************************************************** - * Name: esp32_rtc_init - * - * Description: - * Initialize RTC clock and power control related functions. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void IRAM_ATTR esp32_rtc_init(void) -{ - struct esp32_rtc_priv_s *priv = &esp32_rtc_priv; - - modifyreg32(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PVTMON_PU | - RTC_CNTL_TXRF_I2C_PU | RTC_CNTL_RFRX_PBUS_PU | - RTC_CNTL_CKGEN_I2C_PU | RTC_CNTL_PLL_I2C_PU, 0); - - REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, priv->pll_wait); - REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, priv->xtal_wait); - REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, priv->ck8m_wait); - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN, - RTC_CNTL_DBG_ATTEN_DEFAULT); - - modifyreg32(RTC_CNTL_BIAS_CONF_REG, 0, - RTC_CNTL_DEC_HEARTBEAT_WIDTH | RTC_CNTL_INC_HEARTBEAT_PERIOD); - - /* Reset RTC bias to default value (needed if waking up from deep sleep) */ - - REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_1V10); - REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_SLP, RTC_CNTL_DBIAS_1V10); - if (priv->clkctl_init) - { - /* clear CMMU clock force on */ - - modifyreg32(DPORT_PRO_CACHE_CTRL1_REG, DPORT_PRO_CMMU_FORCE_ON, 0); - modifyreg32(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CMMU_FORCE_ON, 0); - - /* clear rom clock force on */ - - modifyreg32(DPORT_ROM_FO_CTRL_REG, - (DPORT_SHARE_ROM_FO << DPORT_SHARE_ROM_FO_S), 0); - modifyreg32(DPORT_ROM_FO_CTRL_REG, DPORT_APP_ROM_FO | - DPORT_PRO_ROM_FO, 0); - - /* clear sram clock force on */ - - modifyreg32(DPORT_SRAM_FO_CTRL_0_REG, DPORT_SRAM_FO_0, 0); - modifyreg32(DPORT_SRAM_FO_CTRL_1_REG, DPORT_SRAM_FO_1, 0); - - /* clear tag clock force on */ - - modifyreg32(DPORT_TAG_FO_CTRL_REG, DPORT_APP_CACHE_TAG_FORCE_ON | - DPORT_PRO_CACHE_TAG_FORCE_ON, 0); - } - - if (priv->pwrctl_init) - { - modifyreg32(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU, 0); - - /* cancel xtal force pu */ - - modifyreg32(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_XTL_FORCE_PU, 0); - - /* cancel BIAS force pu */ - - modifyreg32(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_CORE_FORCE_PU | - RTC_CNTL_BIAS_I2C_FORCE_PU | RTC_CNTL_BIAS_FORCE_NOSLEEP, 0); - - /* bias follow 8M */ - - modifyreg32(RTC_CNTL_OPTIONS0_REG, 0, RTC_CNTL_BIAS_CORE_FOLW_8M | - RTC_CNTL_BIAS_I2C_FOLW_8M | RTC_CNTL_BIAS_SLEEP_FOLW_8M); - - /* CLEAR APLL close */ - - modifyreg32(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PU, - RTC_CNTL_PLLA_FORCE_PD); - modifyreg32(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BBPLL_FORCE_PU | - RTC_CNTL_BBPLL_I2C_FORCE_PU, 0); - - /* cancel RTC REG force PU */ - - modifyreg32(RTC_CNTL_REG, RTC_CNTL_FORCE_PU | - RTC_CNTL_DBOOST_FORCE_PU, 0); - if (priv->rtc_dboost_fpd) - { - modifyreg32(RTC_CNTL_REG, 0, RTC_CNTL_DBOOST_FORCE_PD); - } - else - { - modifyreg32(RTC_CNTL_REG, RTC_CNTL_DBOOST_FORCE_PD, 0); - } - - /* cancel digital pu force */ - - modifyreg32(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU | - RTC_CNTL_DG_WRAP_FORCE_PU | RTC_CNTL_WIFI_FORCE_PU | - RTC_CNTL_CPU_ROM_RAM_FORCE_PU , 0); - modifyreg32(RTC_CNTL_PWC_REG, RTC_CNTL_MEM_FORCE_PU | - RTC_CNTL_PWC_FORCE_PU, 0); - modifyreg32(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_WRAP_FORCE_NOISO | - RTC_CNTL_WIFI_FORCE_NOISO | RTC_CNTL_CPU_ROM_RAM_FORCE_NOISO, 0); - modifyreg32(RTC_CNTL_PWC_REG, RTC_CNTL_MEM_FORCE_NOISO | - RTC_CNTL_FORCE_NOISO, 0); - - /* cancel digital PADS force no iso */ - - modifyreg32(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD | - RTC_CNTL_DG_PAD_FORCE_NOISO, 0); - } -} - -/**************************************************************************** - * Name: esp32_rtc_time_get - * - * Description: - * Get current value of RTC counter. - * - * Input Parameters: - * None - * - * Returned Value: - * current value of RTC counter - * - ****************************************************************************/ - -uint64_t IRAM_ATTR esp32_rtc_time_get(void) -{ - uint64_t rtc_time; - - modifyreg32(RTC_CNTL_TIME_UPDATE_REG, 0, RTC_CNTL_TIME_UPDATE); - - /* might take 1 RTC slowclk period, don't flood RTC bus */ - - while ((getreg32(RTC_CNTL_TIME_UPDATE_REG) & RTC_CNTL_TIME_VALID) == 0) - { - up_udelay(1); - } - - modifyreg32(RTC_CNTL_INT_CLR_REG, 0, RTC_CNTL_TIME_VALID_INT_CLR); - rtc_time = getreg32(RTC_CNTL_TIME0_REG); - rtc_time |= ((uint64_t) getreg32(RTC_CNTL_TIME1_REG)) << 32; - - return rtc_time; -} - -/**************************************************************************** - * Name: esp32_rtc_time_us_to_slowclk - * - * Description: - * Convert time interval from microseconds to RTC_SLOW_CLK cycles. - * - * Input Parameters: - * time_in_us - Time interval in microseconds - * slow_clk_period - Period of slow clock in microseconds - * - * Returned Value: - * Number of slow clock cycles - * - ****************************************************************************/ - -uint64_t IRAM_ATTR esp32_rtc_time_us_to_slowclk(uint64_t time_in_us, - uint32_t period) -{ - uint64_t slow_clk_cycles = 0; - uint64_t max_time_in_us = (UINT64_C(1) << 45) - 1; - - /* Handle overflow that would happen if time_in_us >= 2^45 */ - - while (time_in_us > max_time_in_us) - { - time_in_us -= max_time_in_us; - slow_clk_cycles += ((max_time_in_us << RTC_CLK_CAL_FRACT) / period); - } - - slow_clk_cycles += ((time_in_us << RTC_CLK_CAL_FRACT) / period); - - return slow_clk_cycles; -} - -/**************************************************************************** - * Name: esp32_rtc_time_slowclk_to_us - * - * Description: - * Convert time interval from RTC_SLOW_CLK to microseconds - * - * Input Parameters: - * rtc_cycles - Time interval in RTC_SLOW_CLK cycles - * period - Period of slow clock in microseconds - * - * Returned Value: - * Time interval in microseconds - * - ****************************************************************************/ - -uint64_t IRAM_ATTR esp32_rtc_time_slowclk_to_us(uint64_t rtc_cycles, - uint32_t period) -{ - return (rtc_cycles * period) >> RTC_CLK_CAL_FRACT; -} - -/**************************************************************************** - * Name: esp32_clk_slowclk_cal_get - * - * Description: - * Get the calibration value of RTC slow clock. - * - * Input Parameters: - * None - * - * Returned Value: - * the calibration value obtained using rtc_clk_cal - * - ****************************************************************************/ - -uint32_t IRAM_ATTR esp32_clk_slowclk_cal_get(void) -{ - return getreg32(RTC_SLOW_CLK_CAL_REG); -} - -/**************************************************************************** - * Name: esp32_rtc_bbpll_disable - * - * Description: - * disable BBPLL. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void IRAM_ATTR esp32_rtc_bbpll_disable(void) -{ - uint32_t apll_fpd; - modifyreg32(RTC_CNTL_OPTIONS0_REG, 0, RTC_CNTL_BB_I2C_FORCE_PD | - RTC_CNTL_BBPLL_FORCE_PD | RTC_CNTL_BBPLL_I2C_FORCE_PD); - - /* is APLL under force power down? */ - - apll_fpd = REG_GET_FIELD(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD); - - if (apll_fpd) - { - /* then also power down the internal I2C bus */ - - modifyreg32(RTC_CNTL_OPTIONS0_REG, 0, RTC_CNTL_BIAS_I2C_FORCE_PD); - } -} - -/**************************************************************************** - * Name: esp32_rtc_sleep_set_wakeup_time - * - * Description: - * Set target value of RTC counter for RTC_TIMER_TRIG_EN wakeup source. - * - * Input Parameters: - * t - value of RTC counter at which wakeup from sleep will happen. - * - * Returned Value: - * None - * - ****************************************************************************/ - -void IRAM_ATTR esp32_rtc_sleep_set_wakeup_time(uint64_t t) -{ - putreg32(t & UINT32_MAX, RTC_CNTL_SLP_TIMER0_REG); - putreg32((uint32_t)(t >> 32), RTC_CNTL_SLP_TIMER1_REG); -} - -/**************************************************************************** - * Name: esp32_rtc_wait_for_slow_cycle - * - * Description: - * Busy loop until next RTC_SLOW_CLK cycle. - * - * Input Parameters: - * None - * - * Returned Value: - * none - * - ****************************************************************************/ - -void IRAM_ATTR esp32_rtc_wait_for_slow_cycle(void) -{ - modifyreg32(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING | - TIMG_RTC_CALI_START, 0); - modifyreg32(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY, 0); - REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, - RTC_CAL_RTC_MUX); - - /* Request to run calibration for 0 slow clock cycles. - * RDY bit will be set on the nearest slow clock cycle. - */ - - REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, 0); - modifyreg32(TIMG_RTCCALICFG_REG(0), 0, TIMG_RTC_CALI_START); - - /* RDY needs some time to go low */ - - up_udelay(1); - - while (!(getreg32(TIMG_RTCCALICFG_REG(0)) & TIMG_RTC_CALI_RDY)) - { - up_udelay(1); - } -} - -/**************************************************************************** - * Name: esp32_rtc_cpu_freq_set_xtal - * - * Description: - * Switch CPU clock source to XTAL - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void IRAM_ATTR esp32_rtc_cpu_freq_set_xtal(void) -{ - int freq_mhz = (int) esp32_rtc_clk_xtal_freq_get(); - esp32_rtc_update_to_xtal(freq_mhz, 1); - esp32_rtc_wait_for_slow_cycle(); - esp32_rtc_bbpll_disable(); -} - -/**************************************************************************** - * Name: esp_rtc_clk_get_cpu_freq - * - * Description: - * Get the currently used CPU frequency configuration. - * - * Input Parameters: - * None - * - * Returned Value: - * CPU frequency - * - ****************************************************************************/ - -int IRAM_ATTR esp_rtc_clk_get_cpu_freq(void) -{ - uint32_t source_freq_mhz; - uint32_t div; - uint32_t soc_clk_sel; - uint32_t cpuperiod_sel; - int freq_mhz = 0; - - soc_clk_sel = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_SOC_CLK_SEL); - switch (soc_clk_sel) - { - case RTC_CNTL_SOC_CLK_SEL_XTL: - { - div = REG_GET_FIELD(APB_CTRL_SYSCLK_CONF_REG, - APB_CTRL_PRE_DIV_CNT) + 1; - source_freq_mhz = (uint32_t) esp32_rtc_clk_xtal_freq_get(); - freq_mhz = source_freq_mhz / div; - } - break; - - case RTC_CNTL_SOC_CLK_SEL_PLL: - { - cpuperiod_sel = REG_GET_FIELD(DPORT_CPU_PER_CONF_REG, - DPORT_CPUPERIOD_SEL); - if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_80) - { - freq_mhz = 80; - } - else if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_160) - { - freq_mhz = 160; - } - else if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_240) - { - freq_mhz = 240; - } - else - { - DEBUGPANIC(); - } - } - break; - - case RTC_CNTL_SOC_CLK_SEL_8M: - { - freq_mhz = 8; - } - break; - - case RTC_CNTL_SOC_CLK_SEL_APLL: - default: - DEBUGPANIC(); - } - - return freq_mhz; -} - -/**************************************************************************** - * Name: esp32_rtc_sleep_init - * - * Description: - * Prepare the chip to enter sleep mode - * - * Input Parameters: - * flags - sleep mode configuration - * - * Returned Value: - * None - * - ****************************************************************************/ - -void IRAM_ATTR esp32_rtc_sleep_init(uint32_t flags) -{ - struct esp32_rtc_sleep_config_s cfg = RTC_SLEEP_CONFIG_DEFAULT(flags); - - struct esp32_rtc_sleep_pd_config_s pd_cfg = - RTC_SLEEP_PD_CONFIG_ALL(cfg.lslp_meminf_pd); - - /* set 5 PWC state machine times to fit in main state machine time */ - - REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, - RTC_CNTL_PLL_BUF_WAIT_SLP); - REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, - RTC_CNTL_XTL_BUF_WAIT_SLP); - REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, - RTC_CNTL_CK8M_WAIT_SLP); - - /* set shortest possible sleep time limit */ - - REG_SET_FIELD(RTC_CNTL_TIMER5_REG, RTC_CNTL_MIN_SLP_VAL, - RTC_CNTL_MIN_SLP_VAL_MIN); - - /* set rom&ram timer */ - - REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_ROM_RAM_POWERUP_TIMER, - ROM_RAM_POWERUP_CYCLES); - REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_ROM_RAM_WAIT_TIMER, - ROM_RAM_WAIT_CYCLES); - - /* set wifi timer */ - - REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_WIFI_POWERUP_TIMER, - WIFI_POWERUP_CYCLES); - REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_WIFI_WAIT_TIMER, - WIFI_WAIT_CYCLES); - - /* set rtc peri timer */ - - REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_POWERUP_TIMER, - RTC_POWERUP_CYCLES); - REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_WAIT_TIMER, - RTC_WAIT_CYCLES); - - /* set digital wrap timer */ - - REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_DG_WRAP_POWERUP_TIMER, - DG_WRAP_POWERUP_CYCLES); - REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_DG_WRAP_WAIT_TIMER, - DG_WRAP_WAIT_CYCLES); - - /* set rtc memory timer */ - - REG_SET_FIELD(RTC_CNTL_TIMER5_REG, RTC_CNTL_RTCMEM_POWERUP_TIMER, - RTC_MEM_POWERUP_CYCLES); - REG_SET_FIELD(RTC_CNTL_TIMER5_REG, RTC_CNTL_RTCMEM_WAIT_TIMER, - RTC_MEM_WAIT_CYCLES); - - REG_SET_FIELD(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU, - cfg.lslp_mem_inf_fpu); - esp32_rtc_sleep_pd(pd_cfg); - - if (cfg.rtc_mem_inf_fpu) - { - modifyreg32(RTC_CNTL_PWC_REG, 0, RTC_CNTL_MEM_FORCE_PU); - } - else - { - modifyreg32(RTC_CNTL_PWC_REG, RTC_CNTL_MEM_FORCE_PU, 0); - } - - if (cfg.rtc_mem_inf_follow_cpu) - { - modifyreg32(RTC_CNTL_PWC_REG, 0, RTC_CNTL_MEM_FOLW_CPU); - } - else - { - modifyreg32(RTC_CNTL_PWC_REG, RTC_CNTL_MEM_FOLW_CPU, 0); - } - - if (cfg.rtc_fastmem_pd_en) - { - modifyreg32(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_PU | - RTC_CNTL_FASTMEM_FORCE_NOISO, RTC_CNTL_FASTMEM_PD_EN); - } - else - { - modifyreg32(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_PD_EN, - RTC_CNTL_FASTMEM_FORCE_PU | RTC_CNTL_FASTMEM_FORCE_NOISO); - } - - if (cfg.rtc_slowmem_pd_en) - { - modifyreg32(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_PU | - RTC_CNTL_SLOWMEM_FORCE_NOISO, RTC_CNTL_SLOWMEM_PD_EN); - } - else - { - modifyreg32(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_PD_EN, - RTC_CNTL_SLOWMEM_FORCE_PU | RTC_CNTL_SLOWMEM_FORCE_NOISO); - } - - if (cfg.rtc_peri_pd_en) - { - modifyreg32(RTC_CNTL_PWC_REG, 0, RTC_CNTL_PD_EN); - } - else - { - modifyreg32(RTC_CNTL_PWC_REG, RTC_CNTL_PD_EN, 0); - } - - if (cfg.wifi_pd_en) - { - modifyreg32(RTC_CNTL_DIG_PWC_REG, 0, RTC_CNTL_WIFI_PD_EN); - } - else - { - modifyreg32(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN, 0); - } - - if (cfg.rom_mem_pd_en) - { - modifyreg32(RTC_CNTL_DIG_PWC_REG, 0, RTC_CNTL_CPU_ROM_RAM_PD_EN); - } - else - { - modifyreg32(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_CPU_ROM_RAM_PD_EN, 0); - } - - if (cfg.deep_slp) - { - modifyreg32(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_ISO | - RTC_CNTL_DG_PAD_FORCE_NOISO, 0); - modifyreg32(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_FORCE_PU | - RTC_CNTL_DG_WRAP_FORCE_PD, RTC_CNTL_DG_WRAP_PD_EN); - modifyreg32(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_FORCE_NOSLEEP, 0); - - /* Shut down parts of RTC which may have been left - * enabled by the wireless drivers. - */ - - modifyreg32(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_CKGEN_I2C_PU | - RTC_CNTL_PLL_I2C_PU | RTC_CNTL_RFRX_PBUS_PU | - RTC_CNTL_TXRF_I2C_PU, 0); - } - else - { - modifyreg32(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN, 0); - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN, 0); - } - - REG_SET_FIELD(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_XTL_FORCE_PU, cfg.xtal_fpu); - - if (REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL) == - RTC_SLOW_FREQ_8MD256) - { - modifyreg32(RTC_CNTL_CLK_CONF_REG, 0, RTC_CNTL_CK8M_FORCE_PU); - } - else - { - modifyreg32(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU, 0); - } - - /* Keep the RTC8M_CLK on in light_sleep mode if the - * ledc low-speed channel is clocked by RTC8M_CLK. - */ - - if (!cfg.deep_slp && GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, - RTC_CNTL_DIG_CLK8M_EN_M)) - { - REG_CLR_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PD); - REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU); - } - - /* enable VDDSDIO control by state machine */ - - modifyreg32(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_FORCE, 0); - REG_SET_FIELD(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_PD_EN, - cfg.vddsdio_pd_en); - REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_SLP, cfg.rtc_dbias_slp); - REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_WAK, cfg.rtc_dbias_wak); - REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, cfg.dig_dbias_wak); - REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_SLP, cfg.dig_dbias_slp); -} - -/**************************************************************************** - * Name: esp32_rtc_sleep_start - * - * Description: - * Enter force sleep mode. - * - * Input Parameters: - * wakeup_opt - bit mask wake up reasons to enable - * reject_opt - bit mask of sleep reject reasons. - * - * Returned Value: - * non-zero if sleep was rejected by hardware - * - ****************************************************************************/ - -int IRAM_ATTR esp32_rtc_sleep_start(uint32_t wakeup_opt, - uint32_t reject_opt) -{ - int reject; - REG_SET_FIELD(RTC_CNTL_WAKEUP_STATE_REG, RTC_CNTL_WAKEUP_ENA, wakeup_opt); - putreg32((uint32_t)reject_opt, RTC_CNTL_SLP_REJECT_CONF_REG); - - /* Start entry into sleep mode */ - - modifyreg32(RTC_CNTL_STATE0_REG, 0, RTC_CNTL_SLEEP_EN); - - while ((getreg32(RTC_CNTL_INT_RAW_REG) & - (RTC_CNTL_SLP_REJECT_INT_RAW | RTC_CNTL_SLP_WAKEUP_INT_RAW)) == 0); - - /* In deep sleep mode, we never get here */ - - reject = REG_GET_FIELD(RTC_CNTL_INT_RAW_REG, RTC_CNTL_SLP_REJECT_INT_RAW); - - modifyreg32(RTC_CNTL_INT_CLR_REG, 0, - RTC_CNTL_SLP_REJECT_INT_CLR | RTC_CNTL_SLP_WAKEUP_INT_CLR); - - /* restore DBG_ATTEN to the default value */ - - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN, - RTC_CNTL_DBG_ATTEN_DEFAULT); - return reject; -} - -/**************************************************************************** - * Name: esp32_rtc_get_time_us - * - * Description: - * Get current value of RTC counter in microseconds - * - * Input Parameters: - * None - * - * Returned Value: - * Current value of RTC counter in microseconds - * - ****************************************************************************/ - -uint64_t esp32_rtc_get_time_us(void) -{ - const uint32_t cal = getreg32(RTC_SLOW_CLK_CAL_REG); - const uint64_t rtc_this_ticks = esp32_rtc_time_get(); - - /* RTC counter result is up to 2^48, calibration factor is up to 2^24, - * for a 32kHz clock. We need to calculate (assuming no overflow): - * (ticks * cal) >> RTC_CLK_CAL_FRACT. An overflow in the (ticks * cal) - * multiplication would cause time to wrap around after approximately - * 13 days, which is probably not enough for some applications. - * Therefore multiplication is split into two terms, for the lower 32-bit - * and the upper 16-bit parts of "ticks", i.e.: - * ((ticks_low + 2^32 * ticks_high) * cal) >> RTC_CLK_CAL_FRACT - */ - - const uint64_t ticks_low = rtc_this_ticks & UINT32_MAX; - const uint64_t ticks_high = rtc_this_ticks >> 32; - const uint64_t delta_time_us = ((ticks_low * cal) >> RTC_CLK_CAL_FRACT) + - ((ticks_high * cal) << (32 - RTC_CLK_CAL_FRACT)); - - return delta_time_us; -} - -/**************************************************************************** - * Name: esp32_rtc_set_boot_time - * - * Description: - * Set time to RTC register to replace the original boot time. - * - * Input Parameters: - * time_us - set time in microseconds. - * - * Returned Value: - * None - * - ****************************************************************************/ - -void IRAM_ATTR esp32_rtc_set_boot_time(uint64_t time_us) -{ - putreg32((uint32_t)(time_us & UINT32_MAX), RTC_BOOT_TIME_LOW_REG); - putreg32((uint32_t)(time_us >> 32), RTC_BOOT_TIME_HIGH_REG); -} - -/**************************************************************************** - * Name: esp32_rtc_get_boot_time - * - * Description: - * Get time of RTC register to indicate the original boot time. - * - * Input Parameters: - * None - * - * Returned Value: - * time_us - get time in microseconds. - * - ****************************************************************************/ - -uint64_t IRAM_ATTR esp32_rtc_get_boot_time(void) -{ - return ((uint64_t)getreg32(RTC_BOOT_TIME_LOW_REG)) - + (((uint64_t)getreg32(RTC_BOOT_TIME_HIGH_REG)) << 32); -} - -/**************************************************************************** - * Name: up_rtc_time - * - * Description: - * Get the current time in seconds. This is similar to the standard time() - * function. This interface is only required if the low-resolution - * RTC/counter hardware implementation is selected. It is only used by the - * RTOS during initialization to set up the system time when CONFIG_RTC is - * set but CONFIG_RTC_HIRES is not set. - * - * Input Parameters: - * None - * - * Returned Value: - * The current time in seconds - * - ****************************************************************************/ - -#ifndef CONFIG_RTC_HIRES -time_t up_rtc_time(void) -{ - uint64_t time_us; - irqstate_t flags; - - flags = spin_lock_irqsave(&g_rtc_lock); - - /* NOTE: RT-Timer starts to work after the board is initialized, and the - * RTC controller starts works after up_rtc_initialize is initialized. - * Since the system clock starts to work before the board is initialized, - * if CONFIG_RTC is enabled, the system time must be matched by the time - * of the RTC controller (up_rtc_initialize has already been initialized, - * and RT-Timer cannot work). - */ - - /* Determine if RT-Timer is started */ - - if (g_rt_timer_enabled == true) - { - /* Get the time from RT-Timer, the time interval between RTC - * controller and RT-Timer is stored in g_rtc_save->offset. - */ - - time_us = rt_timer_time_us() + g_rtc_save->offset + - esp32_rtc_get_boot_time(); - } - else - { - /* Get the time from RTC controller. */ - - time_us = esp32_rtc_get_time_us() + - esp32_rtc_get_boot_time(); - } - - spin_unlock_irqrestore(&g_rtc_lock, flags); - - return (time_t)(time_us / USEC_PER_SEC); -} -#endif /* !CONFIG_RTC_HIRES */ - -/**************************************************************************** - * Name: up_rtc_settime - * - * Description: - * Set the RTC to the provided time. All RTC implementations must be - * able to set their time based on a standard timespec. - * - * Input Parameters: - * ts - the time to use - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -int up_rtc_settime(const struct timespec *ts) -{ - irqstate_t flags; - uint64_t now_us; - uint64_t rtc_offset_us; - - DEBUGASSERT(ts != NULL && ts->tv_nsec < NSEC_PER_SEC); - flags = spin_lock_irqsave(&g_rtc_lock); - - now_us = ((uint64_t) ts->tv_sec) * USEC_PER_SEC + - ts->tv_nsec / NSEC_PER_USEC; - if (g_rt_timer_enabled == true) - { - /* Set based on RT-Timer offset value. */ - - rtc_offset_us = now_us - rt_timer_time_us(); - } - else - { - /* Set based on the offset value of the RT controller. */ - - rtc_offset_us = now_us - esp32_rtc_get_time_us(); - } - - g_rtc_save->offset = 0; - esp32_rtc_set_boot_time(rtc_offset_us); - - spin_unlock_irqrestore(&g_rtc_lock, flags); - - return OK; -} - -/**************************************************************************** - * Name: up_rtc_initialize - * - * Description: - * Initialize the hardware RTC per the selected configuration. - * This function is called once during the OS initialization sequence - * - * Input Parameters: - * None - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -int up_rtc_initialize(void) -{ -#ifndef CONFIG_PM - /* Initialize RTC controller parameters */ - - esp32_rtc_init(); - esp32_rtc_clk_set(); -#endif - - g_rtc_save = &rtc_saved_data; - - /* If saved data is invalid, clear offset information */ - - if (g_rtc_save->magic != MAGIC_RTC_SAVE) - { - g_rtc_save->magic = MAGIC_RTC_SAVE; - g_rtc_save->offset = 0; - esp32_rtc_set_boot_time(0); - } - -#ifdef CONFIG_RTC_HIRES - /* Synchronize the base time to the RTC time */ - - up_rtc_gettime(&g_basetime); -#endif - - g_rtc_enabled = true; - - return OK; -} - -/**************************************************************************** - * Name: up_rtc_gettime - * - * Description: - * Get the current time from the high resolution RTC time or RT-Timer. This - * interface is only supported by the high-resolution RTC/counter hardware - * implementation. It is used to replace the system timer. - * - * Input Parameters: - * tp - The location to return the RTC time or RT-Timer value. - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_HIRES -int up_rtc_gettime(struct timespec *tp) -{ - irqstate_t flags; - uint64_t time_us; - - flags = spin_lock_irqsave(&g_rtc_lock); - - if (g_rt_timer_enabled == true) - { - time_us = rt_timer_time_us() + g_rtc_save->offset + - esp32_rtc_get_boot_time(); - } - else - { - time_us = esp32_rtc_get_time_us() + esp32_rtc_get_boot_time(); - } - - tp->tv_sec = time_us / USEC_PER_SEC; - tp->tv_nsec = (time_us % USEC_PER_SEC) * NSEC_PER_USEC; - - spin_unlock_irqrestore(&g_rtc_lock, flags); - - return OK; -} -#endif /* CONFIG_RTC_HIRES */ - -#ifdef CONFIG_RTC_ALARM - -/**************************************************************************** - * Name: up_rtc_setalarm - * - * Description: - * Set up an alarm. - * - * Input Parameters: - * alminfo - Information about the alarm configuration. - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -int up_rtc_setalarm(struct alm_setalarm_s *alminfo) -{ - struct rt_timer_args_s rt_timer_args; - struct alm_cbinfo_s *cbinfo; - irqstate_t flags; - int ret = -EBUSY; - int id; - - DEBUGASSERT(alminfo != NULL); - DEBUGASSERT((RTC_ALARM0 <= alminfo->as_id) && - (alminfo->as_id < RTC_ALARM_LAST)); - - /* Set the alarm in RT-Timer */ - - id = alminfo->as_id; - cbinfo = &g_alarmcb[id]; - - if (cbinfo->ac_cb == NULL) - { - /* Create the RT-Timer alarm */ - - flags = spin_lock_irqsave(&g_rtc_lock); - - if (cbinfo->alarm_hdl == NULL) - { - cbinfo->index = id; - rt_timer_args.arg = cbinfo; - rt_timer_args.callback = esp32_rt_cb_handler; - ret = rt_timer_create(&rt_timer_args, &cbinfo->alarm_hdl); - if (ret < 0) - { - rtcerr("ERROR: Failed to create rt_timer error=%d\n", ret); - spin_unlock_irqrestore(&g_rtc_lock, flags); - return ret; - } - } - - cbinfo->ac_cb = alminfo->as_cb; - cbinfo->ac_arg = alminfo->as_arg; - cbinfo->deadline_us = alminfo->as_time.tv_sec * USEC_PER_SEC + - alminfo->as_time.tv_nsec / NSEC_PER_USEC; - - if (cbinfo->alarm_hdl == NULL) - { - rtcerr("ERROR: failed to create alarm timer\n"); - } - else - { - rtcinfo("Start RTC alarm.\n"); - rt_timer_start(cbinfo->alarm_hdl, cbinfo->deadline_us, false); - ret = OK; - } - - spin_unlock_irqrestore(&g_rtc_lock, flags); - } - - return ret; -} - -/**************************************************************************** - * Name: up_rtc_cancelalarm - * - * Description: - * Cancel an alarm. - * - * Input Parameters: - * alarmid - Identifies the alarm to be cancelled - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -int up_rtc_cancelalarm(enum alm_id_e alarmid) -{ - struct alm_cbinfo_s *cbinfo; - irqstate_t flags; - int ret = -ENODATA; - - DEBUGASSERT((RTC_ALARM0 <= alarmid) && - (alarmid < RTC_ALARM_LAST)); - - /* Set the alarm in hardware and enable interrupts */ - - cbinfo = &g_alarmcb[alarmid]; - - if (cbinfo->ac_cb != NULL) - { - flags = spin_lock_irqsave_nopreempt(&g_rtc_lock); - - /* Stop and delete the alarm */ - - rtcinfo("Cancel RTC alarm.\n"); - rt_timer_stop(cbinfo->alarm_hdl); - rt_timer_delete(cbinfo->alarm_hdl); - cbinfo->ac_cb = NULL; - cbinfo->deadline_us = 0; - cbinfo->alarm_hdl = NULL; - - spin_unlock_irqrestore_nopreempt(&g_rtc_lock, flags); - - ret = OK; - } - - return ret; -} - -/**************************************************************************** - * Name: up_rtc_rdalarm - * - * Description: - * Query an alarm configured in hardware. - * - * Input Parameters: - * tp - Location to return the timer match register. - * alarmid - Identifies the alarm to get. - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -int up_rtc_rdalarm(struct timespec *tp, uint32_t alarmid) -{ - irqstate_t flags; - struct alm_cbinfo_s *cbinfo; - DEBUGASSERT(tp != NULL); - DEBUGASSERT((RTC_ALARM0 <= alarmid) && - (alarmid < RTC_ALARM_LAST)); - - flags = spin_lock_irqsave(&g_rtc_lock); - - /* Get the alarm according to the alarmid */ - - cbinfo = &g_alarmcb[alarmid]; - - tp->tv_sec = (rt_timer_time_us() + g_rtc_save->offset + - cbinfo->deadline_us) / USEC_PER_SEC; - tp->tv_nsec = ((rt_timer_time_us() + g_rtc_save->offset + - cbinfo->deadline_us) % USEC_PER_SEC) * NSEC_PER_USEC; - - spin_unlock_irqrestore(&g_rtc_lock, flags); - - return OK; -} - -#endif /* CONFIG_RTC_ALARM */ - -/**************************************************************************** - * Name: up_rtc_timer_init - * - * Description: - * Init RTC timer. - * - * Input Parameters: - * None - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -int up_rtc_timer_init(void) -{ - /* RT-Timer enabled */ - - g_rt_timer_enabled = true; - - /* Get the time difference between rt_timer and RTC timer */ - - g_rtc_save->offset = esp32_rtc_get_time_us() - rt_timer_time_us(); - - return OK; -} diff --git a/arch/xtensa/src/esp32/esp32_rtc.h b/arch/xtensa/src/esp32/esp32_rtc.h deleted file mode 100644 index c0ad2eec68d89..0000000000000 --- a/arch/xtensa/src/esp32/esp32_rtc.h +++ /dev/null @@ -1,713 +0,0 @@ -/**************************************************************************** - * arch/xtensa/src/esp32/esp32_rtc.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#ifndef __ARCH_XTENSA_SRC_ESP32_ESP32_RTC_H -#define __ARCH_XTENSA_SRC_ESP32_ESP32_RTC_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include -#include -#include "hardware/esp32_soc.h" - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Number of cycles to wait from the 32k XTAL oscillator to - * consider it running. Larger values increase startup delay. - * Smaller values may cause false positive detection - * (i.e. oscillator runs for a few cycles and then stops). - */ - -#define SLOW_CLK_CAL_CYCLES 1024 - -/* Indicates that 32k oscillator gets input from external oscillator - * instead of a crystal. - */ - -#define EXT_OSC_FLAG BIT(3) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/* Possible main XTAL frequency values. - * Enum values should be equal to frequency in MHz. - */ - -enum esp32_rtc_xtal_freq_e -{ - RTC_XTAL_FREQ_AUTO = 0, /* Automatic XTAL frequency detection */ - RTC_XTAL_FREQ_40M = 40, /* 40 MHz XTAL */ - RTC_XTAL_FREQ_26M = 26, /* 26 MHz XTAL */ - RTC_XTAL_FREQ_24M = 24, /* 24 MHz XTAL */ -}; - -/* RTC SLOW_CLK frequency values */ - -enum esp32_rtc_slow_freq_e -{ - RTC_SLOW_FREQ_RTC = 0, /* Internal 150 kHz RC oscillator */ - RTC_SLOW_FREQ_32K_XTAL = 1, /* External 32 kHz XTAL */ - RTC_SLOW_FREQ_8MD256 = 2, /* Internal 8 MHz RC oscillator, divided by 256 */ -}; - -/* RTC FAST_CLK frequency values */ - -enum esp32_rtc_fast_freq_e -{ - RTC_FAST_FREQ_XTALD4 = 0, /* Main XTAL, divided by 4 */ - RTC_FAST_FREQ_8M = 1, /* Internal 8 MHz RC oscillator */ -}; - -/* This is almost the same as esp32_rtc_slow_freq_e, except that we define - * an extra enum member for the external 32k oscillator. For convenience, - * lower 2 bits should correspond to esp32_rtc_slow_freq_e values. - */ - -enum esp32_slow_clk_sel_e -{ - /* Internal 150 kHz RC oscillator */ - - SLOW_CLK_150K = RTC_SLOW_FREQ_RTC, - - /* External 32 kHz XTAL */ - - SLOW_CLK_32K_XTAL = RTC_SLOW_FREQ_32K_XTAL, - - /* Internal 8 MHz RC oscillator, divided by 256 */ - - SLOW_CLK_8MD256 = RTC_SLOW_FREQ_8MD256, - - /* External 32k oscillator connected to 32K_XP pin */ - - SLOW_CLK_32K_EXT_OSC = RTC_SLOW_FREQ_32K_XTAL | EXT_OSC_FLAG -}; - -/* Clock source to be calibrated using rtc_clk_cal function */ - -enum esp32_rtc_cal_sel_e -{ - RTC_CAL_RTC_MUX = 0, /* Currently selected RTC SLOW_CLK */ - RTC_CAL_8MD256 = 1, /* Internal 8 MHz RC oscillator, divided by 256 */ - RTC_CAL_32K_XTAL = 2 /* External 32 kHz XTAL */ -}; - -#ifdef CONFIG_RTC_ALARM - -/* The form of an alarm callback */ - -typedef void (*alm_callback_t)(void *arg, unsigned int alarmid); - -enum alm_id_e -{ - RTC_ALARM0 = 0, /* RTC ALARM 0 */ - RTC_ALARM1 = 1, /* RTC ALARM 1 */ - RTC_ALARM_LAST, -}; - -/* Structure used to pass parameters to set an alarm */ - -struct alm_setalarm_s -{ - int as_id; /* enum alm_id_e */ - struct timespec as_time; /* Alarm expiration time */ - alm_callback_t as_cb; /* Callback (if non-NULL) */ - void *as_arg; /* Argument for callback */ -}; - -#endif /* CONFIG_RTC_ALARM */ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32_rtc_clk_slow_freq_get_hz - * - * Description: - * Get the approximate frequency of RTC_SLOW_CLK, in Hz - * - * Input Parameters: - * None - * - * Returned Value: - * slow_clk_freq - RTC_SLOW_CLK frequency, in Hz - * - ****************************************************************************/ - -uint32_t esp32_rtc_clk_slow_freq_get_hz(void); - -/**************************************************************************** - * Name: esp32_rtc_clk_fast_freq_get_hz - * - * Description: - * Get fast_clk_rtc source in Hz. - * - * Input Parameters: - * None - * - * Returned Value: - * The clock source in Hz. - * - ****************************************************************************/ - -uint32_t esp32_rtc_clk_fast_freq_get_hz(void); - -/**************************************************************************** - * Name: esp32_rtc_get_slow_clk_rtc - * - * Description: - * Get slow_clk_rtc source. - * - * Input Parameters: - * None - * - * Returned Value: - * The clock source: - * - SLOW_CK - * - CK_XTAL_32K - * - CK8M_D256_OUT - * - ****************************************************************************/ - -enum esp32_rtc_slow_freq_e esp32_rtc_get_slow_clk(void); - -/**************************************************************************** - * Name: esp32_rtc_clk_cal - * - * Description: - * Measure RTC slow clock's period, based on main XTAL frequency - * - * Input Parameters: - * cal_clk - clock to be measured - * slowclk_cycles - number of slow clock cycles to average - * - * Returned Value: - * Average slow clock period in microseconds, Q13.19 fixed point format - * or 0 if calibration has timed out - * - ****************************************************************************/ - -uint32_t esp32_rtc_clk_cal(enum esp32_rtc_cal_sel_e cal_clk, - uint32_t slowclk_cycles); - -/**************************************************************************** - * Name: esp32_rtc_clk_xtal_freq_get - * - * Description: - * Get main XTAL frequency - * - * Input Parameters: - * None - * - * Returned Value: - * XTAL frequency (one of enum esp32_rtc_xtal_freq_e values) - * - ****************************************************************************/ - -enum esp32_rtc_xtal_freq_e esp32_rtc_clk_xtal_freq_get(void); - -/**************************************************************************** - * Name: esp32_rtc_update_to_xtal - * - * Description: - * Switch to XTAL frequency, does not disable the PLL - * - * Input Parameters: - * freq - XTAL frequency - * div - REF_TICK divider - * - * Returned Value: - * none - * - ****************************************************************************/ - -void esp32_rtc_update_to_xtal(int freq, int div); - -/**************************************************************************** - * Name: esp32_rtc_bbpll_enable - * - * Description: - * Reset BBPLL configuration. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32_rtc_bbpll_enable(void); - -/**************************************************************************** - * Name: esp32_rtc_bbpll_configure - * - * Description: - * Configure main XTAL frequency values according to pll_freq. - * - * Input Parameters: - * xtal_freq - XTAL frequency values - * pll_freq - PLL frequency values - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32_rtc_bbpll_configure( - enum esp32_rtc_xtal_freq_e xtal_freq, int pll_freq); - -/**************************************************************************** - * Name: esp32_rtc_clk_set - * - * Description: - * Set RTC CLK frequency. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32_rtc_clk_set(void); - -/**************************************************************************** - * Name: esp32_rtc_init - * - * Description: - * Initialize RTC clock and power control related functions. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32_rtc_init(void); - -/**************************************************************************** - * Name: esp32_rtc_time_get - * - * Description: - * Get current value of RTC counter. - * - * Input Parameters: - * None - * - * Returned Value: - * current value of RTC counter - * - ****************************************************************************/ - -uint64_t esp32_rtc_time_get(void); - -/**************************************************************************** - * Name: esp32_rtc_time_us_to_slowclk - * - * Description: - * Convert time interval from microseconds to RTC_SLOW_CLK cycles. - * - * Input Parameters: - * time_in_us - Time interval in microseconds - * slow_clk_period - Period of slow clock in microseconds - * - * Returned Value: - * number of slow clock cycles - * - ****************************************************************************/ - -uint64_t esp32_rtc_time_us_to_slowclk(uint64_t time_in_us, uint32_t period); - -/**************************************************************************** - * Name: esp32_rtc_time_slowclk_to_us - * - * Description: - * Convert time interval from RTC_SLOW_CLK to microseconds - * - * Input Parameters: - * rtc_cycles - Time interval in RTC_SLOW_CLK cycles - * period - Period of slow clock in microseconds - * - * Returned Value: - * Time interval in microseconds - * - ****************************************************************************/ - -uint64_t esp32_rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period); - -/**************************************************************************** - * Name: esp32_clk_slowclk_cal_get - * - * Description: - * Get the calibration value of RTC slow clock. - * - * Input Parameters: - * None - * - * Returned Value: - * the calibration value obtained using rtc_clk_cal - * - ****************************************************************************/ - -uint32_t esp32_clk_slowclk_cal_get(void); - -/**************************************************************************** - * Name: esp32_rtc_bbpll_disable - * - * Description: - * disable BBPLL. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32_rtc_bbpll_disable(void); - -/**************************************************************************** - * Name: esp32_rtc_sleep_set_wakeup_time - * - * Description: - * Set target value of RTC counter for RTC_TIMER_TRIG_EN wakeup source. - * - * Input Parameters: - * t - value of RTC counter at which wakeup from sleep will happen. - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32_rtc_sleep_set_wakeup_time(uint64_t t); - -/**************************************************************************** - * Name: esp32_rtc_wait_for_slow_cycle - * - * Description: - * Busy loop until next RTC_SLOW_CLK cycle. - * - * Input Parameters: - * None - * - * Returned Value: - * none - * - ****************************************************************************/ - -void esp32_rtc_wait_for_slow_cycle(void); - -/**************************************************************************** - * Name: esp32_rtc_cpu_freq_set_xtal - * - * Description: - * Switch CPU clock source to XTAL - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32_rtc_cpu_freq_set_xtal(void); - -/**************************************************************************** - * Name: esp_rtc_clk_get_cpu_freq - * - * Description: - * Get the currently used CPU frequency configuration. - * - * Input Parameters: - * None - * - * Returned Value: - * CPU frequency - * - ****************************************************************************/ - -int esp_rtc_clk_get_cpu_freq(void); - -/**************************************************************************** - * Name: esp32_rtc_sleep_init - * - * Description: - * Prepare the chip to enter sleep mode - * - * Input Parameters: - * flags - sleep mode configuration - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32_rtc_sleep_init(uint32_t flags); - -/**************************************************************************** - * Name: esp32_rtc_sleep_start - * - * Description: - * Enter force sleep mode. - * - * Input Parameters: - * wakeup_opt - bit mask wake up reasons to enable - * reject_opt - bit mask of sleep reject reasons. - * - * Returned Value: - * non-zero if sleep was rejected by hardware - * - ****************************************************************************/ - -int esp32_rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt); - -/**************************************************************************** - * Name: esp32_rtc_get_time_us - * - * Description: - * Get current value of RTC counter in microseconds - * - * Input Parameters: - * None - * - * Returned Value: - * Current value of RTC counter in microseconds - * - ****************************************************************************/ - -uint64_t esp32_rtc_get_time_us(void); - -/**************************************************************************** - * Name: esp32_rtc_set_boot_time - * - * Description: - * Set time to RTC register to replace the original boot time. - * - * Input Parameters: - * time_us - set time in microseconds. - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32_rtc_set_boot_time(uint64_t time_us); - -/**************************************************************************** - * Name: esp32_rtc_get_boot_time - * - * Description: - * Get time of RTC register to indicate the original boot time. - * - * Input Parameters: - * None - * - * Returned Value: - * time_us - get time in microseconds. - * - ****************************************************************************/ - -uint64_t esp32_rtc_get_boot_time(void); - -#ifdef CONFIG_RTC_DRIVER - -/**************************************************************************** - * Name: up_rtc_time - * - * Description: - * Get the current time in seconds. This is similar to the standard time() - * function. This interface is only required if the low-resolution - * RTC/counter hardware implementation selected. It is only used by the - * RTOS during initialization to set up the system time when CONFIG_RTC is - * set but neither CONFIG_RTC_HIRES nor CONFIG_RTC_DATETIME are set. - * - * Input Parameters: - * None - * - * Returned Value: - * The current time in seconds - * - ****************************************************************************/ - -#ifndef CONFIG_RTC_HIRES -time_t up_rtc_time(void); -#endif - -/**************************************************************************** - * Name: up_rtc_settime - * - * Description: - * Set the RTC to the provided time. All RTC implementations must be - * able to set their time based on a standard timespec. - * - * Input Parameters: - * tp - the time to use - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -int up_rtc_settime(const struct timespec *ts); - -/**************************************************************************** - * Name: up_rtc_initialize - * - * Description: - * Initialize the hardware RTC per the selected configuration. - * This function is called once during the OS initialization sequence - * - * Input Parameters: - * None - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -int up_rtc_initialize(void); - -/**************************************************************************** - * Name: up_rtc_gettime - * - * Description: - * Get the current time from the high resolution RTC clock/counter. This - * interface is only supported by the high-resolution RTC/counter hardware - * implementation. It is used to replace the system timer. - * - * Input Parameters: - * tp - The location to return the high resolution time value. - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_HIRES -int up_rtc_gettime(struct timespec *tp); -#endif - -#ifdef CONFIG_RTC_ALARM - -/**************************************************************************** - * Name: up_rtc_setalarm - * - * Description: - * Set up an alarm. - * - * Input Parameters: - * alminfo - Information about the alarm configuration. - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -int up_rtc_setalarm(struct alm_setalarm_s *alminfo); - -/**************************************************************************** - * Name: up_rtc_cancelalarm - * - * Description: - * Cancel an alaram. - * - * Input Parameters: - * alarmid - Identifies the alarm to be cancelled - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -int up_rtc_cancelalarm(enum alm_id_e alarmid); - -/**************************************************************************** - * Name: up_rtc_rdalarm - * - * Description: - * Query an alarm configured in hardware. - * - * Input Parameters: - * tp - Location to return the timer match register. - * alarmid - Identifies the alarm to be cancelled - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -int up_rtc_rdalarm(struct timespec *tp, uint32_t alarmid); - -#endif /* CONFIG_RTC_ALARM */ - -/**************************************************************************** - * Name: up_rtc_timer_init - * - * Description: - * Init RTC timer. - * - * Input Parameters: - * None - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -int up_rtc_timer_init(void); - -#endif /* CONFIG_RTC_DRIVER */ - -#ifdef __cplusplus -} -#endif -#undef EXTERN - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_XTENSA_SRC_ESP32_ESP32_RTC_H */ diff --git a/arch/xtensa/src/esp32/esp32_rtc_gpio.c b/arch/xtensa/src/esp32/esp32_rtc_gpio.c index aa750de7e0aa4..175563ec372ce 100644 --- a/arch/xtensa/src/esp32/esp32_rtc_gpio.c +++ b/arch/xtensa/src/esp32/esp32_rtc_gpio.c @@ -34,7 +34,7 @@ #include #include "xtensa.h" -#include "esp32_irq.h" +#include "espressif/esp_irq.h" #include "esp32_rtc_gpio.h" #include "hardware/esp32_pinmap.h" #include "hardware/esp32_rtc_io.h" @@ -57,6 +57,14 @@ enum rtcio_lh_out_mode_e RTCIO_OUTPUT_OD = 0x1, /* RTCIO output mode is open-drain. */ }; +/* Structure to store RTC GPIO interrupt handlers */ + +struct rtcio_handler_s +{ + xcpt_t handler; /* User interrupt handler */ + void *arg; /* Argument for handler */ +}; + /**************************************************************************** * Private Data ****************************************************************************/ @@ -64,6 +72,7 @@ enum rtcio_lh_out_mode_e #ifdef CONFIG_ESP32_RTCIO_IRQ static int g_rtcio_cpuint; static uint32_t last_status; +static struct rtcio_handler_s g_rtcio_handlers[ESP32_NIRQ_RTCIO_PERIPH]; #endif static const uint32_t rtc_gpio_to_addr[] = @@ -119,6 +128,7 @@ static inline bool is_valid_rtc_gpio(uint32_t rtcio_num) * * Input Parameters: * irq - The IRQ number; + * context - The interrupt context; * reg_status - Pointer to a copy of the interrupt status register. * * Returned Value: @@ -127,7 +137,7 @@ static inline bool is_valid_rtc_gpio(uint32_t rtcio_num) ****************************************************************************/ #ifdef CONFIG_ESP32_RTCIO_IRQ -static void rtcio_dispatch(int irq, uint32_t *reg_status) +static void rtcio_dispatch(int irq, void *context, uint32_t *reg_status) { uint32_t status = *reg_status; uint32_t mask; @@ -142,11 +152,14 @@ static void rtcio_dispatch(int irq, uint32_t *reg_status) mask = (UINT32_C(1) << i); if ((status & mask) != 0) { - /* Yes... perform the second level dispatch. The IRQ context will - * contain the contents of the status register. - */ + /* Call the registered handler if one exists */ - irq_dispatch(irq + i, (void *)reg_status); + if (g_rtcio_handlers[i].handler != NULL) + { + g_rtcio_handlers[i].handler(irq, + (void *)reg_status, + g_rtcio_handlers[i].arg); + } /* Clear the bit in the status so that we might execute this loop * sooner. @@ -184,7 +197,7 @@ static int rtcio_interrupt(int irq, void *context, void *arg) /* Dispatch pending interrupts in the RTC status register */ - rtcio_dispatch(ESP32_FIRST_RTCIOIRQ_PERIPH, &last_status); + rtcio_dispatch(irq, context, &last_status); return OK; } @@ -327,7 +340,7 @@ int esp32_configrtcio(int rtcio_num, rtcio_pinattr_t attr) } /**************************************************************************** - * Name: esp32_rtcioirqinitialize + * Name: esp_rtcioirqinitialize * * Description: * Initialize logic to support a second level of interrupt decoding for @@ -336,18 +349,27 @@ int esp32_configrtcio(int rtcio_num, rtcio_pinattr_t attr) ****************************************************************************/ #ifdef CONFIG_ESP32_RTCIO_IRQ -void esp32_rtcioirqinitialize(void) +void esp_rtcioirqinitialize(void) { - /* Setup the RTCIO interrupt. */ + int i; - int cpu = this_cpu(); - g_rtcio_cpuint = esp32_setup_irq(cpu, ESP32_PERIPH_RTC_CORE, - 1, ESP32_CPUINT_LEVEL); + /* Initialize handler array */ + + for (i = 0; i < ESP32_NIRQ_RTCIO_PERIPH; i++) + { + g_rtcio_handlers[i].handler = NULL; + g_rtcio_handlers[i].arg = NULL; + } + + /* Setup the RTCIO interrupt with handler. */ + + g_rtcio_cpuint = esp_setup_irq(ESP32_PERIPH_RTC_CORE, + 1, ESP_IRQ_TRIGGER_LEVEL, + rtcio_interrupt, NULL); DEBUGASSERT(g_rtcio_cpuint >= 0); - /* Attach and enable the interrupt handler */ + /* Enable the interrupt */ - DEBUGVERIFY(irq_attach(ESP32_IRQ_RTC_CORE, rtcio_interrupt, NULL)); up_enable_irq(ESP32_IRQ_RTC_CORE); } #endif @@ -417,3 +439,81 @@ void esp32_rtcioirqdisable(int irq) up_enable_irq(ESP32_IRQ_RTC_CORE); } #endif + +/**************************************************************************** + * Name: esp32_rtcioirqattach + * + * Description: + * Attach an interrupt handler to a specified RTC IRQ + * + * Input Parameters: + * irq - RTC IRQ number to attach the handler to + * handler - Interrupt handler function + * arg - Argument to pass to the handler + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32_RTCIO_IRQ +int esp32_rtcioirqattach(int irq, xcpt_t handler, void *arg) +{ + int bit; + + DEBUGASSERT(irq >= ESP32_FIRST_RTCIOIRQ_PERIPH && + irq <= ESP32_LAST_RTCIOIRQ_PERIPH); + + /* Convert the IRQ number to the corresponding bit */ + + bit = irq - ESP32_FIRST_RTCIOIRQ_PERIPH; + + DEBUGASSERT(bit >= 0 && bit < ESP32_NIRQ_RTCIO_PERIPH); + + /* Store the handler and argument */ + + g_rtcio_handlers[bit].handler = handler; + g_rtcio_handlers[bit].arg = arg; + + return OK; +} +#endif + +/**************************************************************************** + * Name: esp32_rtcioirqdetach + * + * Description: + * Detach an interrupt handler from a specified RTC IRQ + * + * Input Parameters: + * irq - RTC IRQ number to detach the handler from + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32_RTCIO_IRQ +int esp32_rtcioirqdetach(int irq) +{ + int bit; + + DEBUGASSERT(irq >= ESP32_FIRST_RTCIOIRQ_PERIPH && + irq <= ESP32_LAST_RTCIOIRQ_PERIPH); + + /* Convert the IRQ number to the corresponding bit */ + + bit = irq - ESP32_FIRST_RTCIOIRQ_PERIPH; + + DEBUGASSERT(bit >= 0 && bit < ESP32_NIRQ_RTCIO_PERIPH); + + /* Clear the handler and argument */ + + g_rtcio_handlers[bit].handler = NULL; + g_rtcio_handlers[bit].arg = NULL; + + return OK; +} +#endif diff --git a/arch/xtensa/src/esp32/esp32_rtc_gpio.h b/arch/xtensa/src/esp32/esp32_rtc_gpio.h index bad6cd4a506b2..ea57af03a8208 100644 --- a/arch/xtensa/src/esp32/esp32_rtc_gpio.h +++ b/arch/xtensa/src/esp32/esp32_rtc_gpio.h @@ -25,9 +25,8 @@ * Included Files ****************************************************************************/ -#include "hardware/esp32_gpio.h" #include "hardware/esp32_rtc_io.h" -#include "hardware/esp32_rtccntl.h" +#include "soc/rtc_cntl_reg.h" /**************************************************************************** * Pre-processor Definitions @@ -163,50 +162,6 @@ typedef uint16_t rtcio_pinattr_t; * Public Data ****************************************************************************/ -static const int g_gpio_to_rtcio_map[GPIO_PIN_COUNT + 1] = -{ - RTCIO_GPIO0_CHANNEL, /* GPIO0 */ - -1, /* GPIO1 not supported */ - RTCIO_GPIO2_CHANNEL, /* GPIO2 */ - -1, /* GPIO3 not supported */ - RTCIO_GPIO4_CHANNEL, /* GPIO4 */ - -1, /* GPIO5 not supported */ - -1, /* GPIO6 not supported */ - -1, /* GPIO7 not supported */ - -1, /* GPIO8 not supported */ - -1, /* GPIO9 not supported */ - -1, /* GPIO10 not supported */ - -1, /* GPIO11 not supported */ - RTCIO_GPIO12_CHANNEL, /* GPIO12 */ - RTCIO_GPIO13_CHANNEL, /* GPIO13 */ - RTCIO_GPIO14_CHANNEL, /* GPIO14 */ - RTCIO_GPIO15_CHANNEL, /* GPIO15 */ - -1, /* GPIO16 not supported */ - -1, /* GPIO17 not supported */ - -1, /* GPIO18 not supported */ - -1, /* GPIO19 not supported */ - -1, /* GPIO20 not supported */ - -1, /* GPIO21 not supported */ - -1, /* GPIO22 not supported */ - -1, /* GPIO23 not supported */ - -1, /* GPIO24 not supported */ - RTCIO_GPIO25_CHANNEL, /* GPIO25 */ - RTCIO_GPIO26_CHANNEL, /* GPIO26 */ - RTCIO_GPIO27_CHANNEL, /* GPIO27 */ - -1, /* GPIO28 not supported */ - -1, /* GPIO29 not supported */ - -1, /* GPIO30 not supported */ - -1, /* GPIO31 not supported */ - RTCIO_GPIO32_CHANNEL, /* GPIO32 */ - RTCIO_GPIO33_CHANNEL, /* GPIO33 */ - RTCIO_GPIO34_CHANNEL, /* GPIO34 */ - RTCIO_GPIO35_CHANNEL, /* GPIO35 */ - RTCIO_GPIO36_CHANNEL, /* GPIO36 */ - RTCIO_GPIO37_CHANNEL, /* GPIO37 */ - RTCIO_GPIO38_CHANNEL, /* GPIO38 */ - RTCIO_GPIO39_CHANNEL /* GPIO39 */ -}; - static const rtc_io_desc_t g_rtc_io_desc[RTC_GPIO_NUMBER] = { /* REG @@ -542,7 +497,7 @@ static const rtc_io_desc_t g_rtc_io_desc[RTC_GPIO_NUMBER] = int esp32_configrtcio(int rtcio_num, rtcio_pinattr_t attr); /**************************************************************************** - * Name: esp32_rtcioirqinitialize + * Name: esp_rtcioirqinitialize * * Description: * Initialize logic to support a second level of interrupt decoding for @@ -551,9 +506,9 @@ int esp32_configrtcio(int rtcio_num, rtcio_pinattr_t attr); ****************************************************************************/ #ifdef CONFIG_ESP32_RTCIO_IRQ -void esp32_rtcioirqinitialize(void); +void esp_rtcioirqinitialize(void); #else -# define esp32_rtcioirqinitialize() +# define esp_rtcioirqinitialize() #endif /**************************************************************************** @@ -584,4 +539,47 @@ void esp32_rtcioirqdisable(int irq); # define esp32_rtcioirqdisable(irq) #endif +/**************************************************************************** + * Name: esp32_rtcioirqattach + * + * Description: + * Attach an interrupt handler to a specified RTC IRQ + * + * Input Parameters: + * irq - RTC IRQ number to attach the handler to + * handler - Interrupt handler function + * arg - Argument to pass to the handler + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32_RTCIO_IRQ +int esp32_rtcioirqattach(int irq, xcpt_t handler, void *arg); +#else +# define esp32_rtcioirqattach(irq, handler, arg) (-ENOSYS) +#endif +/**************************************************************************** + * Name: esp32_rtcioirqdetach + * + * Description: + * Detach an interrupt handler from a specified RTC IRQ + * + * Input Parameters: + * irq - RTC IRQ number to detach the handler from + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32_RTCIO_IRQ +int esp32_rtcioirqdetach(int irq); +#else +# define esp32_rtcioirqdetach(irq) (-ENOSYS) +#endif + #endif /* __ARCH_XTENSA_SRC_ESP32_ESP32_RTC_GPIO_H */ diff --git a/arch/xtensa/src/esp32/esp32_rtc_lowerhalf.c b/arch/xtensa/src/esp32/esp32_rtc_lowerhalf.c deleted file mode 100644 index cebe6b5a0b8a5..0000000000000 --- a/arch/xtensa/src/esp32/esp32_rtc_lowerhalf.c +++ /dev/null @@ -1,559 +0,0 @@ -/**************************************************************************** - * arch/xtensa/src/esp32/esp32_rtc_lowerhalf.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include -#include -#include -#include -#include -#include - -#include -#include - -#include "esp32_rtc.h" -#include "hardware/esp32_tim.h" - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -#ifdef CONFIG_RTC_ALARM -struct esp32_cbinfo_s -{ - volatile rtc_alarm_callback_t cb; /* Callback when the alarm expires */ - volatile void *priv; /* Private argurment to accompany callback */ -}; -#endif - -/* This is the private type for the RTC state. It must be cast compatible - * with struct rtc_lowerhalf_s. - */ - -struct esp32_lowerhalf_s -{ - /* This is the contained reference to the read-only, lower-half - * operations vtable (which may lie in FLASH or ROM) - */ - - const struct rtc_ops_s *ops; - spinlock_t lock; -#ifdef CONFIG_RTC_ALARM - /* Alarm callback information */ - - struct esp32_cbinfo_s cbinfo[RTC_ALARM_LAST]; -#endif -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Prototypes for static methods in struct rtc_ops_s */ - -static int rtc_lh_rdtime(struct rtc_lowerhalf_s *lower, - struct rtc_time *rtctime); -static int rtc_lh_settime(struct rtc_lowerhalf_s *lower, - const struct rtc_time *rtctime); -static bool rtc_lh_havesettime(struct rtc_lowerhalf_s *lower); - -#ifdef CONFIG_RTC_ALARM -static void rtc_lh_alarm_callback(void *arg, unsigned int alarmid); -static int rtc_lh_setalarm(struct rtc_lowerhalf_s *lower, - const struct lower_setalarm_s *alarminfo); -static int rtc_lh_setrelative(struct rtc_lowerhalf_s *lower, - const struct lower_setrelative_s *alarminfo); -static int rtc_lh_cancelalarm(struct rtc_lowerhalf_s *lower, - int alarmid); -static int rtc_lh_rdalarm(struct rtc_lowerhalf_s *lower, - struct lower_rdalarm_s *alarminfo); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* ESP32 RTC driver operations */ - -static const struct rtc_ops_s g_rtc_ops = -{ - .rdtime = rtc_lh_rdtime, - .settime = rtc_lh_settime, - .havesettime = rtc_lh_havesettime, -#ifdef CONFIG_RTC_ALARM - .setalarm = rtc_lh_setalarm, - .setrelative = rtc_lh_setrelative, - .cancelalarm = rtc_lh_cancelalarm, - .rdalarm = rtc_lh_rdalarm, -#endif -}; - -/* ESP32 RTC device state */ - -static struct esp32_lowerhalf_s g_rtc_lowerhalf = -{ - .ops = &g_rtc_ops, - .lock = SP_UNLOCKED -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: rtc_lh_alarm_callback - * - * Description: - * This is the function that is called from the RTC driver when the alarm - * goes off. It just invokes the upper half drivers callback. - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_ALARM -static void rtc_lh_alarm_callback(void *arg, unsigned int alarmid) -{ - struct esp32_lowerhalf_s *lower; - struct esp32_cbinfo_s *cbinfo; - rtc_alarm_callback_t cb; - void *priv; - - DEBUGASSERT((RTC_ALARM0 <= alarmid) && (alarmid < RTC_ALARM_LAST)); - - lower = (struct esp32_lowerhalf_s *)arg; - cbinfo = &lower->cbinfo[alarmid]; - - /* Sample and clear the callback information to minimize the window in - * time in which race conditions can occur. - */ - - cb = (rtc_alarm_callback_t)cbinfo->cb; - priv = (void *)cbinfo->priv; - - cbinfo->cb = NULL; - cbinfo->priv = NULL; - - /* Perform the callback */ - - if (cb != NULL) - { - cb(priv, alarmid); - } -} -#endif /* CONFIG_RTC_ALARM */ - -/**************************************************************************** - * Name: rtc_lh_rdtime - * - * Description: - * Returns the current RTC time. - * - * Input Parameters: - * lower - A reference to RTC lower half driver state structure - * rcttime - The location in which to return the current RTC time. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on any failure. - * - ****************************************************************************/ - -static int rtc_lh_rdtime(struct rtc_lowerhalf_s *lower, - struct rtc_time *rtctime) -{ -#if defined(CONFIG_RTC_HIRES) - struct timespec ts; - int ret; - - /* Get the higher resolution time */ - - ret = up_rtc_gettime(&ts); - if (ret < 0) - { - goto errout; - } - - /* Convert the one second epoch time to a struct tm. This operation - * depends on the fact that struct rtc_time and struct tm are cast - * compatible. - */ - - if (!gmtime_r(&ts.tv_sec, (struct tm *)rtctime)) - { - ret = -get_errno(); - goto errout; - } - - return OK; - -errout: - rtcerr("ERROR: failed to get RTC time: %d\n", ret); - return ret; - -#else - time_t timer; - - /* The resolution of time is only 1 second */ - - timer = up_rtc_time(); - - /* Convert the one second epoch time to a struct tm */ - - if (gmtime_r(&timer, (struct tm *)rtctime) == 0) - { - int errcode = get_errno(); - DEBUGASSERT(errcode > 0); - - rtcerr("ERROR: gmtime_r failed: %d\n", errcode); - return -errcode; - } - - return OK; -#endif -} - -/**************************************************************************** - * Name: rtc_lh_settime - * - * Description: - * Implements the settime() method of the RTC driver interface - * - * Input Parameters: - * lower - A reference to RTC lower half driver state structure - * rcttime - The new time to set - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on any failure. - * - ****************************************************************************/ - -static int rtc_lh_settime(struct rtc_lowerhalf_s *lower, - const struct rtc_time *rtctime) -{ - struct timespec ts; - - /* Convert the struct rtc_time to a time_t. Here we assume that struct - * rtc_time is cast compatible with struct tm. - */ - - ts.tv_sec = mktime((struct tm *)rtctime); - ts.tv_nsec = 0; - - /* Now set the time (with a accuracy of seconds) */ - - return up_rtc_settime(&ts); -} - -/**************************************************************************** - * Name: rtc_lh_havesettime - * - * Description: - * Implements the havesettime() method of the RTC driver interface - * - * Input Parameters: - * lower - A reference to RTC lower half driver state structure - * - * Returned Value: - * Returns true if RTC date-time have been previously set. - * - ****************************************************************************/ - -static bool rtc_lh_havesettime(struct rtc_lowerhalf_s *lower) -{ - if (esp32_rtc_get_boot_time() == 0) - { - return false; - } - - return true; -} - -/**************************************************************************** - * Name: rtc_lh_setalarm - * - * Description: - * Set a new alarm. This function implements the setalarm() method of the - * RTC driver interface - * - * Input Parameters: - * lower - A reference to RTC lower half driver state structure - * alarminfo - Provided information needed to set the alarm - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on any failure. - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_ALARM -static int rtc_lh_setalarm(struct rtc_lowerhalf_s *lower, - const struct lower_setalarm_s *alarminfo) -{ - struct esp32_lowerhalf_s *priv; - struct esp32_cbinfo_s *cbinfo; - struct alm_setalarm_s lowerinfo; - int ret; - - DEBUGASSERT(lower != NULL && alarminfo != NULL); - DEBUGASSERT((RTC_ALARM0 <= alarminfo->id) && - (alarminfo->id < RTC_ALARM_LAST)); - - priv = (struct esp32_lowerhalf_s *)lower; - - /* Remember the callback information */ - - cbinfo = &priv->cbinfo[alarminfo->id]; - cbinfo->cb = alarminfo->cb; - cbinfo->priv = alarminfo->priv; - - /* Set the alarm */ - - lowerinfo.as_id = alarminfo->id; - lowerinfo.as_cb = rtc_lh_alarm_callback; - lowerinfo.as_arg = priv; - - /* Convert the RTC time to a timespec (1 second accuracy) */ - - lowerinfo.as_time.tv_sec = mktime((struct tm *)&alarminfo->time); - lowerinfo.as_time.tv_nsec = 0; - - /* And set the alarm */ - - ret = up_rtc_setalarm(&lowerinfo); - if (ret < 0) - { - cbinfo->cb = NULL; - cbinfo->priv = NULL; - } - - return ret; -} -#endif /* CONFIG_RTC_ALARM */ - -/**************************************************************************** - * Name: rtc_lh_setrelative - * - * Description: - * Set a new alarm relative to the current time. This function implements - * the setrelative() method of the RTC driver interface - * - * Input Parameters: - * lower - A reference to RTC lower half driver state structure - * alarminfo - Provided information needed to set the alarm - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on any failure. - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_ALARM -static int rtc_lh_setrelative(struct rtc_lowerhalf_s *lower, - const struct lower_setrelative_s *alarminfo) -{ - struct esp32_lowerhalf_s *priv = (struct esp32_lowerhalf_s *)lower; - struct lower_setalarm_s setalarm; - time_t seconds; - int ret = -EINVAL; - irqstate_t flags; - - DEBUGASSERT(lower != NULL && alarminfo != NULL); - DEBUGASSERT((RTC_ALARM0 <= alarminfo->id) && - (alarminfo->id < RTC_ALARM_LAST)); - - if (alarminfo->reltime > 0) - { - flags = spin_lock_irqsave(&priv->lock); - - seconds = alarminfo->reltime; - gmtime_r(&seconds, (struct tm *)&setalarm.time); - - /* The set the alarm using this absolute time */ - - setalarm.id = alarminfo->id; - setalarm.cb = alarminfo->cb; - setalarm.priv = alarminfo->priv; - ret = rtc_lh_setalarm(lower, &setalarm); - - spin_unlock_irqrestore(&priv->lock, flags); - } - - return ret; -} -#endif /* CONFIG_RTC_ALARM */ - -/**************************************************************************** - * Name: rtc_lh_cancelalarm - * - * Description: - * Cancel the current alarm. This function implements the cancelalarm() - * method of the RTC driver interface - * - * Input Parameters: - * lower - A reference to RTC lower half driver state structure - * alarmid - the alarm id - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on any failure. - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_ALARM -static int rtc_lh_cancelalarm(struct rtc_lowerhalf_s *lower, int alarmid) -{ - struct esp32_lowerhalf_s *priv; - struct esp32_cbinfo_s *cbinfo; - - DEBUGASSERT(lower != NULL); - DEBUGASSERT((RTC_ALARM0 <= alarmid) && (alarmid < RTC_ALARM_LAST)); - - priv = (struct esp32_lowerhalf_s *)lower; - - /* Nullify callback information to reduce window for race conditions */ - - cbinfo = &priv->cbinfo[alarmid]; - cbinfo->cb = NULL; - cbinfo->priv = NULL; - - /* Then cancel the alarm */ - - return up_rtc_cancelalarm((enum alm_id_e)alarmid); -} -#endif /* CONFIG_RTC_ALARM */ - -/**************************************************************************** - * Name: rtc_lh_rdalarm - * - * Description: - * Query the RTC alarm. - * - * Input Parameters: - * lower - A reference to RTC lower half driver state structure - * alarminfo - Provided information needed to query the alarm - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on any failure. - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_ALARM -static int rtc_lh_rdalarm(struct rtc_lowerhalf_s *lower, - struct lower_rdalarm_s *alarminfo) -{ - struct esp32_lowerhalf_s *priv = (struct esp32_lowerhalf_s *)lower; - struct timespec ts; - int ret; - irqstate_t flags; - - DEBUGASSERT(lower != NULL && alarminfo != NULL && alarminfo->time != NULL); - DEBUGASSERT((RTC_ALARM0 <= alarminfo->id) && - (alarminfo->id < RTC_ALARM_LAST)); - - flags = spin_lock_irqsave(&priv->lock); - - ret = up_rtc_rdalarm(&ts, alarminfo->id); - localtime_r((const time_t *)&ts.tv_sec, - (struct tm *)alarminfo->time); - - spin_unlock_irqrestore(&priv->lock, flags); - - return ret; -} -#endif /* CONFIG_RTC_ALARM */ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32_rtc_lowerhalf - * - * Description: - * Instantiate the RTC lower half driver for the ESP32. - * - * Input Parameters: - * None - * - * Returned Value: - * On success, a non-NULL RTC lower interface is returned. NULL is - * returned on any failure. - * - ****************************************************************************/ - -struct rtc_lowerhalf_s *esp32_rtc_lowerhalf(void) -{ - return (struct rtc_lowerhalf_s *)&g_rtc_lowerhalf; -} - -/**************************************************************************** - * Name: esp32_rtc_driverinit - * - * Description: - * Bind the configuration timer to a timer lower half instance and register - * the timer drivers at 'devpath' - * - * Input Parameters: - * None - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned - * to indicate the nature of any failure. - * - ****************************************************************************/ - -int esp32_rtc_driverinit(void) -{ - int ret = ERROR; - struct rtc_lowerhalf_s *lower; - - /* Instantiate the ESP32 lower-half RTC driver */ - - lower = esp32_rtc_lowerhalf(); - if (lower == NULL) - { - return ret; - } - else - { - /* Bind the lower half driver and register the combined RTC driver - * as /dev/rtc0 - */ - - ret = rtc_initialize(0, lower); - } - - /* Init RTC timer */ - - up_rtc_timer_init(); - - return ret; -} diff --git a/arch/xtensa/src/esp32/esp32_serial.c b/arch/xtensa/src/esp32/esp32_serial.c index 65ff458d795c1..eadd49ec7d0d6 100644 --- a/arch/xtensa/src/esp32/esp32_serial.c +++ b/arch/xtensa/src/esp32/esp32_serial.c @@ -53,8 +53,10 @@ #include "hardware/esp32_uhci.h" #include "hardware/esp32_dma.h" #include "esp32_config.h" -#include "esp32_gpio.h" -#include "esp32_irq.h" +#include "driver/uart_wakeup.h" +#include "esp_sleep.h" +#include "espressif/esp_gpio.h" +#include "espressif/esp_irq.h" #include "esp32_dma.h" #include "hardware/esp32_dport.h" @@ -401,6 +403,7 @@ static struct esp32_dev_s g_uart0priv = .parity = CONFIG_UART0_PARITY, .bits = CONFIG_UART0_BITS, .stopbits2 = CONFIG_UART0_2STOP, + .cpuint = -ENOMEM, #ifdef CONFIG_SERIAL_TXDMA # ifdef CONFIG_ESP32_UART0_TXDMA .txdma = true, /* TX DMA enabled for this UART */ @@ -488,6 +491,7 @@ static struct esp32_dev_s g_uart1priv = .parity = CONFIG_UART1_PARITY, .bits = CONFIG_UART1_BITS, .stopbits2 = CONFIG_UART1_2STOP, + .cpuint = -ENOMEM, #ifdef CONFIG_SERIAL_TXDMA # ifdef CONFIG_ESP32_UART1_TXDMA .txdma = true, /* TX DMA enabled for this UART */ @@ -575,6 +579,7 @@ static struct esp32_dev_s g_uart2priv = .parity = CONFIG_UART2_PARITY, .bits = CONFIG_UART2_BITS, .stopbits2 = CONFIG_UART2_2STOP, + .cpuint = -ENOMEM, #ifdef CONFIG_SERIAL_TXDMA # ifdef CONFIG_ESP32_UART2_TXDMA .txdma = true, /* TX DMA enabled for this UART */ @@ -997,6 +1002,7 @@ static int esp32_setup(struct uart_dev_s *dev) #endif #endif + return OK; } @@ -1052,13 +1058,13 @@ static void esp32_shutdown(struct uart_dev_s *dev) static int esp32_attach(struct uart_dev_s *dev) { struct esp32_dev_s *priv = (struct esp32_dev_s *)dev->priv; - int ret = OK; + + DEBUGASSERT(priv->cpuint == -ENOMEM); /* Set up to receive peripheral interrupts on the current CPU */ - priv->cpu = this_cpu(); - priv->cpuint = esp32_setup_irq(priv->cpu, priv->config->periph, - 1, ESP32_CPUINT_LEVEL); + priv->cpuint = esp_setup_irq(priv->config->periph, 1, + ESP_IRQ_TRIGGER_LEVEL, esp32_interrupt, dev); if (priv->cpuint < 0) { /* Failed to allocate a CPU interrupt of this type */ @@ -1066,19 +1072,13 @@ static int esp32_attach(struct uart_dev_s *dev) return priv->cpuint; } - /* Attach and enable the IRQ */ - - ret = irq_attach(priv->config->irq, esp32_interrupt, dev); - if (ret == OK) - { - /* Enable the CPU interrupt (RX and TX interrupts are still disabled - * in the UART - */ + /* Enable the CPU interrupt (RX and TX interrupts are still disabled + * in the UART) + */ - up_enable_irq(priv->config->irq); - } + up_enable_irq(priv->config->irq); - return ret; + return OK; } /**************************************************************************** @@ -1095,15 +1095,11 @@ static void esp32_detach(struct uart_dev_s *dev) { struct esp32_dev_s *priv = (struct esp32_dev_s *)dev->priv; - /* Disable and detach the CPU interrupt */ + /* Disable and teardown the CPU interrupt */ up_disable_irq(priv->config->irq); - irq_detach(priv->config->irq); - - /* Disassociate the peripheral interrupt from the CPU interrupt */ - - esp32_teardown_irq(priv->cpu, priv->config->periph, priv->cpuint); - priv->cpuint = -1; + esp_teardown_irq(priv->config->periph, priv->cpuint); + priv->cpuint = -ENOMEM; } #ifdef CONFIG_SERIAL_TXDMA @@ -1160,8 +1156,6 @@ static inline void dma_disable_int(uint8_t dma_chan) static void dma_attach(uint8_t dma_chan) { int dma_cpuint; - int cpu; - int ret; int periph; int irq; @@ -1186,8 +1180,8 @@ static void dma_attach(uint8_t dma_chan) /* Set up to receive peripheral interrupts on the current CPU */ - cpu = this_cpu(); - dma_cpuint = esp32_setup_irq(cpu, periph, 1, ESP32_CPUINT_LEVEL); + dma_cpuint = esp_setup_irq(periph, 1, ESP_IRQ_TRIGGER_LEVEL, + esp32_interrupt_dma, NULL); if (dma_cpuint < 0) { /* Failed to allocate a CPU interrupt of this type */ @@ -1196,17 +1190,9 @@ static void dma_attach(uint8_t dma_chan) return; } - ret = irq_attach(irq, esp32_interrupt_dma, NULL); - if (ret == OK) - { - /* Enable the CPU interrupt */ + /* Enable the CPU interrupt */ - up_enable_irq(irq); - } - else - { - dmaerr("Couldn't attach IRQ to handler.\n"); - } + up_enable_irq(irq); } /**************************************************************************** @@ -1399,7 +1385,7 @@ static int esp32_interrupt(int cpuint, void *context, void *arg) nfifo = REG_MASK(status, UART_TXFIFO_CNT); if (nfifo == 0) { - esp32_gpiowrite(priv->config->rs485_dir_gpio, + esp_gpiowrite(priv->config->rs485_dir_gpio, !priv->config->rs485_dir_polarity); } } @@ -1757,7 +1743,7 @@ static void esp32_send(struct uart_dev_s *dev, int ch) #ifdef HAVE_RS485 if (priv->config->rs485_dir_gpio != 0) { - esp32_gpiowrite(priv->config->rs485_dir_gpio, + esp_gpiowrite(priv->config->rs485_dir_gpio, priv->config->rs485_dir_polarity); } #endif @@ -1888,18 +1874,18 @@ static void esp32_config_pins(struct esp32_dev_s *priv) * This "?" is the Unicode replacement character (U+FFFD) */ - esp32_gpiowrite(priv->config->txpin, true); - esp32_configgpio(priv->config->txpin, OUTPUT_FUNCTION_3); - esp32_gpio_matrix_out(priv->config->txpin, priv->config->txsig, 0, 0); + esp_gpiowrite(priv->config->txpin, true); + esp_configgpio(priv->config->txpin, OUTPUT_FUNCTION_3); + esp_gpio_matrix_out(priv->config->txpin, priv->config->txsig, 0, 0); - esp32_configgpio(priv->config->rxpin, INPUT_FUNCTION_3); - esp32_gpio_matrix_in(priv->config->rxpin, priv->config->rxsig, 0); + esp_configgpio(priv->config->rxpin, INPUT_FUNCTION_3); + esp_gpio_matrix_in(priv->config->rxpin, priv->config->rxsig, 0); #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) { - esp32_configgpio(priv->config->rtspin, OUTPUT_FUNCTION_3); - esp32_gpio_matrix_out(priv->config->rtspin, priv->config->rtssig, + esp_configgpio(priv->config->rtspin, OUTPUT_FUNCTION_3); + esp_gpio_matrix_out(priv->config->rtspin, priv->config->rtssig, 0, 0); } @@ -1907,18 +1893,18 @@ static void esp32_config_pins(struct esp32_dev_s *priv) #ifdef CONFIG_SERIAL_OFLOWCONTROL if (priv->oflow) { - esp32_configgpio(priv->config->ctspin, INPUT_FUNCTION_3); - esp32_gpio_matrix_in(priv->config->ctspin, priv->config->ctssig, 0); + esp_configgpio(priv->config->ctspin, INPUT_FUNCTION_3); + esp_gpio_matrix_in(priv->config->ctspin, priv->config->ctssig, 0); } #endif #ifdef HAVE_RS485 if (priv->config->rs485_dir_gpio != 0) { - esp32_configgpio(priv->config->rs485_dir_gpio, OUTPUT_FUNCTION_3); - esp32_gpio_matrix_out(priv->config->rs485_dir_gpio, + esp_configgpio(priv->config->rs485_dir_gpio, OUTPUT_FUNCTION_3); + esp_gpio_matrix_out(priv->config->rs485_dir_gpio, SIG_GPIO_OUT_IDX, 0, 0); - esp32_gpiowrite(priv->config->rs485_dir_gpio, + esp_gpiowrite(priv->config->rs485_dir_gpio, !priv->config->rs485_dir_polarity); } #endif diff --git a/arch/xtensa/src/esp32/esp32_sha.c b/arch/xtensa/src/esp32/esp32_sha.c index 6e2caf0697bf3..f166e6434faa7 100644 --- a/arch/xtensa/src/esp32/esp32_sha.c +++ b/arch/xtensa/src/esp32/esp32_sha.c @@ -38,8 +38,10 @@ #include "xtensa.h" +#include "hal/sha_ll.h" #include "hal/sha_hal.h" #include "periph_ctrl.h" +#include "esp_private/esp_crypto_lock_internal.h" #include "esp32_sha.h" @@ -384,7 +386,17 @@ int esp32_sha_init(void) { if (!g_sha_inited) { - periph_module_enable(PERIPH_SHA_MODULE); + SHA_RCC_ATOMIC() + { + sha_ll_enable_bus_clock(true); + sha_ll_reset_register(); + + #if SOC_SHA_CRYPTO_DMA + crypto_dma_ll_enable_bus_clock(true); + crypto_dma_ll_reset_register(); + #endif + } + g_sha_inited = true; } else @@ -396,4 +408,3 @@ int esp32_sha_init(void) } #endif - diff --git a/arch/xtensa/src/esp32/esp32_spi.c b/arch/xtensa/src/esp32/esp32_spi.c index c64ac2d7be19b..990211c06251a 100644 --- a/arch/xtensa/src/esp32/esp32_spi.c +++ b/arch/xtensa/src/esp32/esp32_spi.c @@ -47,8 +47,8 @@ #include #include "esp32_spi.h" -#include "esp32_gpio.h" -#include "esp32_irq.h" +#include "esp_gpio.h" +#include "esp_irq.h" #include "esp32_dma.h" #include "xtensa.h" @@ -562,7 +562,7 @@ static void esp32_spi_select(struct spi_dev_s *dev, #ifdef CONFIG_ESP32_SPI_SWCS struct esp32_spi_priv_s *priv = (struct esp32_spi_priv_s *)dev; - esp32_gpiowrite(priv->config->cs_pin, !selected); + esp_gpiowrite(priv->config->cs_pin, !selected); #endif spiinfo("devid: %08" PRIx32 " CS: %s\n", @@ -1344,66 +1344,66 @@ static void esp32_spi_init(struct spi_dev_s *dev) const struct esp32_spi_config_s *config = priv->config; uint32_t regval; - esp32_gpiowrite(config->cs_pin, 1); - esp32_gpiowrite(config->clk_pin, 1); + esp_gpiowrite(config->cs_pin, 1); + esp_gpiowrite(config->clk_pin, 1); if (config->flags & ESP32_SPI_IO_W) { - esp32_gpiowrite(config->mosi_pin, 1); + esp_gpiowrite(config->mosi_pin, 1); } if (config->flags & ESP32_SPI_IO_R) { - esp32_gpiowrite(config->miso_pin, 1); + esp_gpiowrite(config->miso_pin, 1); } #ifdef CONFIG_ESP32_SPI_SWCS - esp32_configgpio(config->cs_pin, OUTPUT); - esp32_gpio_matrix_out(config->cs_pin, SIG_GPIO_OUT_IDX, 0, 0); + esp_configgpio(config->cs_pin, OUTPUT); + esp_gpio_matrix_out(config->cs_pin, SIG_GPIO_OUT_IDX, 0, 0); #endif if (esp32_spi_iomux(priv)) { #ifndef CONFIG_ESP32_SPI_SWCS - esp32_configgpio(config->cs_pin, OUTPUT_FUNCTION_2); - esp32_gpio_matrix_out(config->cs_pin, SIG_GPIO_OUT_IDX, 0, 0); + esp_configgpio(config->cs_pin, OUTPUT_FUNCTION_2); + esp_gpio_matrix_out(config->cs_pin, SIG_GPIO_OUT_IDX, 0, 0); #endif - esp32_configgpio(config->clk_pin, OUTPUT_FUNCTION_2); - esp32_gpio_matrix_out(config->clk_pin, SIG_GPIO_OUT_IDX, 0, 0); + esp_configgpio(config->clk_pin, OUTPUT_FUNCTION_2); + esp_gpio_matrix_out(config->clk_pin, SIG_GPIO_OUT_IDX, 0, 0); if (config->flags & ESP32_SPI_IO_W) { - esp32_configgpio(config->mosi_pin, OUTPUT_FUNCTION_2); - esp32_gpio_matrix_out(config->mosi_pin, SIG_GPIO_OUT_IDX, 0, 0); + esp_configgpio(config->mosi_pin, OUTPUT_FUNCTION_2); + esp_gpio_matrix_out(config->mosi_pin, SIG_GPIO_OUT_IDX, 0, 0); } if (config->flags & ESP32_SPI_IO_R) { - esp32_configgpio(config->miso_pin, INPUT_FUNCTION_2 | PULLUP); - esp32_gpio_matrix_out(config->miso_pin, SIG_GPIO_OUT_IDX, 0, 0); + esp_configgpio(config->miso_pin, INPUT_FUNCTION_2 | PULLUP); + esp_gpio_matrix_out(config->miso_pin, SIG_GPIO_OUT_IDX, 0, 0); } } else { #ifndef CONFIG_ESP32_SPI_SWCS - esp32_configgpio(config->cs_pin, OUTPUT_FUNCTION_3); - esp32_gpio_matrix_out(config->cs_pin, config->cs_outsig, 0, 0); + esp_configgpio(config->cs_pin, OUTPUT_FUNCTION_3); + esp_gpio_matrix_out(config->cs_pin, config->cs_outsig, 0, 0); #endif - esp32_configgpio(config->clk_pin, OUTPUT_FUNCTION_3); - esp32_gpio_matrix_out(config->clk_pin, config->clk_outsig, 0, 0); + esp_configgpio(config->clk_pin, OUTPUT_FUNCTION_3); + esp_gpio_matrix_out(config->clk_pin, config->clk_outsig, 0, 0); if (config->flags & ESP32_SPI_IO_W) { - esp32_configgpio(config->mosi_pin, OUTPUT_FUNCTION_3); - esp32_gpio_matrix_out(config->mosi_pin, config->mosi_outsig, 0, 0); + esp_configgpio(config->mosi_pin, OUTPUT_FUNCTION_3); + esp_gpio_matrix_out(config->mosi_pin, config->mosi_outsig, 0, 0); } if (config->flags & ESP32_SPI_IO_R) { - esp32_configgpio(config->miso_pin, INPUT_FUNCTION_3 | PULLUP); - esp32_gpio_matrix_in(config->miso_pin, config->miso_insig, 0); + esp_configgpio(config->miso_pin, INPUT_FUNCTION_3 | PULLUP); + esp_gpio_matrix_in(config->miso_pin, config->miso_insig, 0); } } @@ -1552,24 +1552,17 @@ struct spi_dev_s *esp32_spibus_initialize(int port) /* Set up to receive peripheral interrupts on the current CPU */ priv->cpu = this_cpu(); - priv->cpuint = esp32_setup_irq(priv->cpu, priv->config->periph, - 1, ESP32_CPUINT_LEVEL); + priv->cpuint = esp_setup_irq(priv->config->periph, + 1, + ESP_IRQ_TRIGGER_LEVEL, + esp32_spi_interrupt, + priv); if (priv->cpuint < 0) { nxmutex_unlock(&priv->lock); return NULL; } - ret = irq_attach(priv->config->irq, esp32_spi_interrupt, priv); - if (ret != OK) - { - esp32_teardown_irq(priv->cpu, - priv->config->periph, - priv->cpuint); - nxmutex_unlock(&priv->lock); - return NULL; - } - up_enable_irq(priv->config->irq); } @@ -1615,9 +1608,7 @@ int esp32_spibus_uninitialize(struct spi_dev_s *dev) if (priv->config->use_dma) { up_disable_irq(priv->config->irq); - esp32_teardown_irq(priv->cpu, - priv->config->periph, - priv->cpuint); + esp_teardown_irq(priv->config->periph, priv->cpuint); } esp32_spi_deinit(dev); diff --git a/arch/xtensa/src/esp32/esp32_spi_slave.c b/arch/xtensa/src/esp32/esp32_spi_slave.c index 0de9852f35ed9..6d320fb518e14 100644 --- a/arch/xtensa/src/esp32/esp32_spi_slave.c +++ b/arch/xtensa/src/esp32/esp32_spi_slave.c @@ -49,8 +49,8 @@ #include #include "esp32_spi.h" -#include "esp32_gpio.h" -#include "esp32_irq.h" +#include "esp_gpio.h" +#include "esp_irq.h" #include "esp32_dma.h" #include "xtensa.h" @@ -874,7 +874,7 @@ static int esp32_spislv_interrupt(int irq, void *context, void *arg) } #endif - if (priv->process == true && esp32_gpioread(priv->config->cs_pin)) + if (priv->process == true && esp_gpioread(priv->config->cs_pin)) { priv->process = false; SPIS_DEV_SELECT(priv->dev, false); @@ -905,61 +905,61 @@ static void esp32_spislv_initialize(struct spi_slave_ctrlr_s *ctrlr) const struct esp32_spislv_config_s *config = priv->config; uint32_t regval; - esp32_gpiowrite(config->cs_pin, 1); - esp32_gpiowrite(config->clk_pin, 1); + esp_gpiowrite(config->cs_pin, 1); + esp_gpiowrite(config->clk_pin, 1); if (config->flags & ESP32_SPI_IO_R) { - esp32_gpiowrite(config->mosi_pin, 1); + esp_gpiowrite(config->mosi_pin, 1); } #ifdef ESP32_SPI_SLAVE_HAS_TX if (config->flags & ESP32_SPI_IO_W) { - esp32_gpiowrite(config->miso_pin, 1); + esp_gpiowrite(config->miso_pin, 1); } #endif if (esp32_spi_iomux(priv)) { - esp32_configgpio(config->cs_pin, INPUT_FUNCTION_2 | PULLUP); - esp32_configgpio(config->clk_pin, INPUT_FUNCTION_2 | PULLUP); + esp_configgpio(config->cs_pin, INPUT_FUNCTION_2 | PULLUP); + esp_configgpio(config->clk_pin, INPUT_FUNCTION_2 | PULLUP); #ifdef ESP32_SPI_SLAVE_HAS_TX if (config->flags & ESP32_SPI_IO_W) { - esp32_configgpio(config->miso_pin, OUTPUT_FUNCTION_2); + esp_configgpio(config->miso_pin, OUTPUT_FUNCTION_2); } #endif if (config->flags & ESP32_SPI_IO_R) { - esp32_configgpio(config->mosi_pin, INPUT_FUNCTION_2 | PULLUP); + esp_configgpio(config->mosi_pin, INPUT_FUNCTION_2 | PULLUP); } } else { - esp32_configgpio(config->cs_pin, INPUT_FUNCTION_3 | PULLUP); - esp32_gpio_matrix_out(config->cs_pin, config->cs_outsig, 0, 0); - esp32_gpio_matrix_in(config->cs_pin, config->cs_insig, 0); + esp_configgpio(config->cs_pin, INPUT_FUNCTION_3 | PULLUP); + esp_gpio_matrix_out(config->cs_pin, config->cs_outsig, 0, 0); + esp_gpio_matrix_in(config->cs_pin, config->cs_insig, 0); - esp32_configgpio(config->clk_pin, INPUT_FUNCTION_3 | PULLUP); - esp32_gpio_matrix_out(config->clk_pin, config->clk_outsig, 0, 0); - esp32_gpio_matrix_in(config->clk_pin, config->clk_insig, 0); + esp_configgpio(config->clk_pin, INPUT_FUNCTION_3 | PULLUP); + esp_gpio_matrix_out(config->clk_pin, config->clk_outsig, 0, 0); + esp_gpio_matrix_in(config->clk_pin, config->clk_insig, 0); if (config->flags & ESP32_SPI_IO_R) { - esp32_configgpio(config->mosi_pin, INPUT_FUNCTION_3 | PULLUP); - esp32_gpio_matrix_out(config->mosi_pin, config->mosi_outsig, 0, 0); - esp32_gpio_matrix_in(config->mosi_pin, config->mosi_insig, 0); + esp_configgpio(config->mosi_pin, INPUT_FUNCTION_3 | PULLUP); + esp_gpio_matrix_out(config->mosi_pin, config->mosi_outsig, 0, 0); + esp_gpio_matrix_in(config->mosi_pin, config->mosi_insig, 0); } #ifdef ESP32_SPI_SLAVE_HAS_TX if (config->flags & ESP32_SPI_IO_W) { - esp32_configgpio(config->miso_pin, OUTPUT_FUNCTION_3); - esp32_gpio_matrix_out(config->miso_pin, config->miso_outsig, 0, 0); - esp32_gpio_matrix_in(config->miso_pin, config->miso_insig, 0); + esp_configgpio(config->miso_pin, OUTPUT_FUNCTION_3); + esp_gpio_matrix_out(config->miso_pin, config->miso_outsig, 0, 0); + esp_gpio_matrix_in(config->miso_pin, config->miso_insig, 0); } #endif } @@ -1027,7 +1027,7 @@ static void esp32_spislv_initialize(struct spi_slave_ctrlr_s *ctrlr) esp32_spi_set_regbits(priv, SPI_SLAVE_OFFSET, SPI_SYNC_RESET_M); esp32_spi_reset_regbits(priv, SPI_SLAVE_OFFSET, SPI_SYNC_RESET_M); - esp32_gpioirqenable(ESP32_PIN2IRQ(config->cs_pin), RISING); + esp_gpioirqenable(ESP32_PIN2IRQ(config->cs_pin), RISING); esp32_spi_reset_regbits(priv, SPI_SLAVE_OFFSET, SPI_TRANS_DONE_M); } @@ -1050,7 +1050,7 @@ static void esp32_spislv_deinit(struct spi_slave_ctrlr_s *ctrlr) { struct esp32_spislv_priv_s *priv = (struct esp32_spislv_priv_s *)ctrlr; - esp32_gpioirqdisable(ESP32_PIN2IRQ(priv->config->cs_pin)); + esp_gpioirqdisable(ESP32_PIN2IRQ(priv->config->cs_pin)); esp32_spi_reset_regbits(priv, SPI_SLAVE_OFFSET, SPI_INT_EN_M); if (priv->dma_chan) @@ -1163,7 +1163,7 @@ static void esp32_spislv_unbind(struct spi_slave_ctrlr_s *ctrlr) up_disable_irq(priv->config->irq); - esp32_gpioirqdisable(ESP32_PIN2IRQ(priv->config->cs_pin)); + esp_gpioirqdisable(ESP32_PIN2IRQ(priv->config->cs_pin)); esp32_spi_reset_regbits(priv, SPI_SLAVE_OFFSET, SPI_INT_EN_M); if (priv->dma_chan) { @@ -1400,26 +1400,27 @@ struct spi_slave_ctrlr_s *esp32_spislv_ctrlr_initialize(int port) priv->dma_chan = 0; } - DEBUGVERIFY(irq_attach(ESP32_PIN2IRQ(priv->config->cs_pin), - esp32_io_interrupt, - priv)); + /* Attach IRQ for CS pin interrupt */ - /* Set up to receive peripheral interrupts on the current CPU */ - - priv->cpu = this_cpu(); - priv->cpuint = esp32_setup_irq(priv->cpu, priv->config->periph, - 1, ESP32_CPUINT_LEVEL); - - ret = irq_attach(priv->config->irq, esp32_spislv_interrupt, priv); - if (ret != OK) + ret = esp_gpio_irq(priv->config->cs_pin, + esp32_io_interrupt, + priv); + if (ret < 0) { - esp32_teardown_irq(priv->cpu, priv->config->periph, priv->cpuint); - + spierr("esp_gpio_irq() failed: %d\n", ret); spin_unlock_irqrestore(&priv->lock, flags); - return NULL; } + /* Set up to receive peripheral interrupts on the current CPU */ + + priv->cpu = this_cpu(); + priv->cpuint = esp_setup_irq(priv->config->periph, + 1, + ESP_IRQ_TRIGGER_LEVEL, + esp32_spislv_interrupt, + priv); + priv->refs++; spin_unlock_irqrestore(&priv->lock, flags); @@ -1462,7 +1463,7 @@ int esp32_spislv_ctrlr_uninitialize(struct spi_slave_ctrlr_s *ctrlr) } up_disable_irq(priv->config->irq); - esp32_teardown_irq(priv->cpu, priv->config->periph, priv->cpuint); + esp_teardown_irq(priv->config->periph, priv->cpuint); esp32_spislv_deinit(ctrlr); spin_unlock_irqrestore(&priv->lock, flags); diff --git a/arch/xtensa/src/esp32/esp32_spicache.c b/arch/xtensa/src/esp32/esp32_spicache.c index 292ff233701de..cb0e0d989bdb9 100644 --- a/arch/xtensa/src/esp32/esp32_spicache.c +++ b/arch/xtensa/src/esp32/esp32_spicache.c @@ -34,7 +34,6 @@ #include #include "xtensa.h" -#include "xtensa_attr.h" #include "hardware/esp32_soc.h" #include "hardware/esp32_spi.h" diff --git a/arch/xtensa/src/esp32/esp32_spicache.h b/arch/xtensa/src/esp32/esp32_spicache.h index 54c6c33e51867..071ff4d1e8638 100644 --- a/arch/xtensa/src/esp32/esp32_spicache.h +++ b/arch/xtensa/src/esp32/esp32_spicache.h @@ -31,8 +31,6 @@ #include #include -#include "xtensa_attr.h" - #ifndef __ASSEMBLY__ #undef EXTERN diff --git a/arch/xtensa/src/esp32/esp32_spiflash.c b/arch/xtensa/src/esp32/esp32_spiflash.c index 2d658b5d1a6e1..1a1b26e7fb3a7 100644 --- a/arch/xtensa/src/esp32/esp32_spiflash.c +++ b/arch/xtensa/src/esp32/esp32_spiflash.c @@ -45,20 +45,18 @@ #include "sched/sched.h" #include "xtensa.h" -#include "xtensa_attr.h" #include "rom/esp32_spiflash.h" #include "hardware/esp32_soc.h" #include "hardware/esp32_spi.h" #include "hardware/esp32_dport.h" -#include "hardware/esp32_efuse.h" #include "esp32_spicache.h" #ifdef CONFIG_ESP32_SPIRAM #include "esp32_spiram.h" #endif -#include "esp32_irq.h" +#include "esp_irq.h" #include "esp32_spiflash.h" @@ -509,7 +507,7 @@ void esp32_spiflash_opstart(void) nxsched_set_priority(tcb, saved_priority); - esp32_irq_noniram_disable(); + esp_intr_noniram_disable(); spi_disable_cache(cpu); #ifdef CONFIG_SMP @@ -548,7 +546,7 @@ void esp32_spiflash_opdone(void) g_flash_op_complete = true; - esp32_irq_noniram_enable(); + esp_intr_noniram_enable(); sched_unlock(); @@ -2509,7 +2507,7 @@ static int spi_flash_op_block_task(int argc, char *argv[]) sched_lock(); - esp32_irq_noniram_disable(); + esp_intr_noniram_disable(); /* g_flash_op_complete flag is cleared on *this* CPU, otherwise the * other CPU may reset the flag back to false before this task has a @@ -2532,7 +2530,7 @@ static int spi_flash_op_block_task(int argc, char *argv[]) /* Restore interrupts that aren't located in IRAM */ - esp32_irq_noniram_enable(); + esp_intr_noniram_enable(); sched_unlock(); } diff --git a/arch/xtensa/src/esp32/esp32_spiflash.h b/arch/xtensa/src/esp32/esp32_spiflash.h index 67e9dbe2e8782..fd16b709950af 100644 --- a/arch/xtensa/src/esp32/esp32_spiflash.h +++ b/arch/xtensa/src/esp32/esp32_spiflash.h @@ -31,8 +31,6 @@ #include #include -#include "xtensa_attr.h" - #ifndef __ASSEMBLY__ #undef EXTERN diff --git a/arch/xtensa/src/esp32/esp32_spiram.c b/arch/xtensa/src/esp32/esp32_spiram.c index 297437b8b52d0..a44536b827182 100644 --- a/arch/xtensa/src/esp32/esp32_spiram.c +++ b/arch/xtensa/src/esp32/esp32_spiram.c @@ -39,7 +39,7 @@ #include "esp32_spiram.h" #include "esp32_psram.h" #include "xtensa.h" -#include "xtensa_attr.h" + #include "hardware/esp32_soc.h" #include "hardware/esp32_dport.h" diff --git a/arch/xtensa/src/esp32/esp32_spiram.h b/arch/xtensa/src/esp32/esp32_spiram.h index 065c538998c13..52004e3b0120d 100644 --- a/arch/xtensa/src/esp32/esp32_spiram.h +++ b/arch/xtensa/src/esp32/esp32_spiram.h @@ -28,7 +28,7 @@ #include #include #include -#include "xtensa_attr.h" +#include "esp_attr.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/xtensa/src/esp32/esp32_start.c b/arch/xtensa/src/esp32/esp32_start.c index 0b95dae720e6f..fde27ea5db775 100644 --- a/arch/xtensa/src/esp32/esp32_start.c +++ b/arch/xtensa/src/esp32/esp32_start.c @@ -33,9 +33,7 @@ #include #include "xtensa.h" -#include "xtensa_attr.h" -#include "esp32_clockconfig.h" #include "esp32_region.h" #include "esp32_start.h" #include "esp32_spiram.h" @@ -44,11 +42,16 @@ # include "esp32_userspace.h" #endif #include "hardware/esp32_dport.h" -#include "hardware/esp32_rtccntl.h" +#include "soc/rtc_cntl_reg.h" +#include "rom/rtc.h" +#include "esp_rom_sys.h" #include "rom/esp32_libc_stubs.h" #include "espressif/esp_loader.h" #include "espressif/esp_efuse.h" #include "esp_private/startup_internal.h" +#include "esp_clk_internal.h" +#include "esp_cpu.h" +#include "esp_sleep.h" #include "esp_private/spi_flash_os.h" #include "esp_private/esp_mmu_map_private.h" #include "bootloader_flash_config.h" @@ -82,6 +85,16 @@ #endif +/* On chips with different virtual address space for flash and PSRAM, code in + * flash is not available before XIP is initialized. Hence, these functions + * have to be in the IRAM. + */ + +#define MSPI_INIT_ATTR NOINLINE_ATTR static + +#define RWDT_RESET RESET_REASON_CORE_RTC_WDT +#define MWDT_RESET RESET_REASON_CORE_MWDT0 + /**************************************************************************** * Private Types ****************************************************************************/ @@ -142,8 +155,88 @@ uint32_t g_idlestack[IDLETHREAD_STACKWORDS] * Private Functions ****************************************************************************/ +/**************************************************************************** + * Name: sys_rtc_init + * + * Description: + * Initialize RTC and power-related hardware early in the startup path. + * When CONFIG_BOOTLOADER_WDT_ENABLE is not set, if the reset was caused + * by the RTC watchdog (RWDT) or main system watchdog (MWDT) on any core + * (e.g. from a panic handler), the RTC WDT is disabled so the system can + * continue. Then esp_rtc_init() is called to configure power/RTC; after + * this, MSPI timing tuning can be performed. + * + * Input Parameters: + * rst_reas - Array of reset reasons per CPU core (indexed by core id). + * + * Returned Value: + * None + * + ****************************************************************************/ + +MSPI_INIT_ATTR void sys_rtc_init(const soc_reset_reason_t *rst_reas) +{ +#ifndef CONFIG_BOOTLOADER_WDT_ENABLE + /* From panic handler we can be reset by RWDT or TG0WDT */ + + if (rst_reas[0] == RWDT_RESET || rst_reas[0] == MWDT_RESET +#ifdef CONFIG_SMP + || rst_reas[1] == RWDT_RESET || rst_reas[1] == MWDT_RESET +#endif + ) + { + wdt_hal_context_t rtc_wdt_ctx = RWDT_HAL_CONTEXT_DEFAULT(); + wdt_hal_write_protect_disable(&rtc_wdt_ctx); + wdt_hal_disable(&rtc_wdt_ctx); + wdt_hal_write_protect_enable(&rtc_wdt_ctx); + } +#endif + + /* Configure the power related stuff. After this the MSPI timing tuning can + * be done. + */ + + esp_rtc_init(); +} + +/**************************************************************************** + * Name: get_reset_reason + * + * Description: + * Fill the given array with the reset reason for each CPU core from ROM. + * Core 0 is always filled; when CONFIG_SMP is set, core 1 is also filled. + * + * Input Parameters: + * rst_reas - Array to receive reset reasons (indexed by core id). + * + * Returned Value: + * None + * + ****************************************************************************/ + +FORCE_INLINE_ATTR IRAM_ATTR +void get_reset_reason(soc_reset_reason_t *rst_reas) +{ + rst_reas[0] = esp_rom_get_reset_reason(0); +#ifdef CONFIG_SMP + rst_reas[1] = esp_rom_get_reset_reason(1); +#endif +} + static noreturn_function void __esp32_start(void) { +#ifdef CONFIG_SMP + soc_reset_reason_t rst_reas[SOC_CPU_CORES_NUM] = + { + [0 ... SOC_CPU_CORES_NUM - 1] = RESET_REASON_CHIP_POWER_ON + }; +#else + soc_reset_reason_t rst_reas[1] = + { + RESET_REASON_CHIP_POWER_ON + }; +#endif + uint32_t regval unused_data; uint32_t chip_rev; #ifndef CONFIG_ESPRESSIF_SIMPLE_BOOT @@ -214,6 +307,10 @@ static noreturn_function void __esp32_start(void) putreg32(regval, DPORT_APPCPU_CTRL_B_REG); #endif + get_reset_reason(rst_reas); + + sys_rtc_init(rst_reas); + /* The 2nd stage bootloader enables RTC WDT to check on startup sequence * related issues in application. Hence disable that as we are about to * start the NuttX environment. @@ -221,9 +318,9 @@ static noreturn_function void __esp32_start(void) esp32_wdt_early_deinit(); - /* Set CPU frequency configured in board.h */ + /* Initialize RTC controller and set CPU frequency */ - esp32_clockconfig(); + esp_clk_init(); #ifndef CONFIG_SUPPRESS_UART_CONFIG /* Configure the UART so we can get debug output */ @@ -289,10 +386,6 @@ static noreturn_function void __esp32_start(void) showprogress('C'); #endif - SYS_STARTUP_FN(); - - showprogress('D'); - chip_rev = esp_efuse_hal_chip_revision(); _info("ESP32 chip revision is v%" PRId32 ".%01ld\n", @@ -325,6 +418,48 @@ static noreturn_function void __esp32_start(void) * Public Functions ****************************************************************************/ +/**************************************************************************** + * Name: xtensa_soc_initialize + * + * Description: + * Initialize SoC-specific initialization. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void weak_function xtensa_soc_initialize(void) +{ + sys_startup_fn(); +} + +/**************************************************************************** + * Name: sys_startup_fn + * + * Description: + * Execute the system layer startup function for the current CPU core. + * This function calls the appropriate startup function from the per-CPU + * startup function array (g_startup_fn) based on the current core ID. + * The SYS_STARTUP_FN() macro retrieves the core ID, indexes into the + * g_startup_fn array, and invokes the corresponding startup function. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void sys_startup_fn(void) +{ + SYS_STARTUP_FN(); +} + /**************************************************************************** * Name: __start * diff --git a/arch/xtensa/src/esp32/esp32_start.h b/arch/xtensa/src/esp32/esp32_start.h index 97393fb182658..78e530ab9671f 100644 --- a/arch/xtensa/src/esp32/esp32_start.h +++ b/arch/xtensa/src/esp32/esp32_start.h @@ -33,6 +33,26 @@ * Pre-processor Definitions ****************************************************************************/ +/**************************************************************************** + * Name: sys_startup_fn + * + * Description: + * Execute the system layer startup function for the current CPU core. + * This function calls the appropriate startup function from the per-CPU + * startup function array (g_startup_fn) based on the current core ID. + * The SYS_STARTUP_FN() macro retrieves the core ID, indexes into the + * g_startup_fn array, and invokes the corresponding startup function. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void sys_startup_fn(void); + /**************************************************************************** * Name: esp32_board_initialize * diff --git a/arch/xtensa/src/esp32/esp32_systemreset.c b/arch/xtensa/src/esp32/esp32_systemreset.c index a2ddcb71103f2..2238cc90bd7bc 100644 --- a/arch/xtensa/src/esp32/esp32_systemreset.c +++ b/arch/xtensa/src/esp32/esp32_systemreset.c @@ -30,7 +30,7 @@ #include #include "xtensa.h" -#include "hardware/esp32_rtccntl.h" +#include "soc/rtc_cntl_reg.h" #include "esp32_systemreset.h" /**************************************************************************** diff --git a/arch/xtensa/src/esp32/esp32_tickless.c b/arch/xtensa/src/esp32/esp32_tickless.c index d621f7d71c310..3e6a0fa228ec2 100644 --- a/arch/xtensa/src/esp32/esp32_tickless.c +++ b/arch/xtensa/src/esp32/esp32_tickless.c @@ -61,8 +61,9 @@ #include #include "xtensa.h" -#include "xtensa_attr.h" #include "xtensa_counter.h" +#include "esp_irq.h" +#include "esp_attr.h" #ifdef CONFIG_SCHED_TICKLESS @@ -494,11 +495,16 @@ void up_timer_initialize(void) /* Attach the timer interrupt */ - irq_attach(XTENSA_IRQ_TIMER0, (xcpt_t)up_timer_expire, NULL); + esp_setup_irq(ETS_INTERNAL_TIMER0_INTR_SOURCE, + ESP_IRQ_PRIORITY_1, + 0, + up_timer_expire, + NULL); /* Enable the timer 0 CPU interrupt. */ - up_enable_irq(XTENSA_IRQ_TIMER0); + up_enable_irq(ETS_INTERNAL_TIMER0_INTR_SOURCE + + ETS_INTERNAL_INTR_SOURCE_OFF); } /**************************************************************************** diff --git a/arch/xtensa/src/esp32/esp32_tim.c b/arch/xtensa/src/esp32/esp32_tim.c index e908300c4687d..042a84f200008 100644 --- a/arch/xtensa/src/esp32/esp32_tim.c +++ b/arch/xtensa/src/esp32/esp32_tim.c @@ -33,7 +33,7 @@ #include "hardware/esp32_tim.h" -#include "esp32_irq.h" +#include "espressif/esp_irq.h" #include "esp32_tim.h" @@ -530,8 +530,8 @@ static int esp32_tim_setisr(struct esp32_tim_dev_s *dev, xcpt_t handler, */ up_disable_irq(tim->irq); - esp32_teardown_irq(tim->core, tim->periph, tim->cpuint); - irq_detach(tim->irq); + esp_teardown_irq(tim->periph, tim->cpuint); + tim->cpuint = -ENOMEM; tim->core = -ENODEV; } @@ -551,8 +551,10 @@ static int esp32_tim_setisr(struct esp32_tim_dev_s *dev, xcpt_t handler, /* Set up to receive peripheral interrupts on the current CPU */ tim->core = this_cpu(); - tim->cpuint = esp32_setup_irq(tim->core, tim->periph, - tim->priority, ESP32_CPUINT_LEVEL); + tim->cpuint = esp_setup_irq(tim->periph, + tim->priority, + ESP_IRQ_TRIGGER_LEVEL, + handler, arg); if (tim->cpuint < 0) { tmrerr("ERROR: No CPU Interrupt available"); @@ -560,16 +562,6 @@ static int esp32_tim_setisr(struct esp32_tim_dev_s *dev, xcpt_t handler, goto errout; } - /* Associate an IRQ Number (from the timer) to an ISR */ - - ret = irq_attach(tim->irq, handler, arg); - if (ret != OK) - { - esp32_teardown_irq(tim->core, tim->periph, tim->cpuint); - tmrerr("ERROR: Failed to associate an IRQ Number"); - goto errout; - } - /* Enable the CPU Interrupt that is linked to the timer */ up_enable_irq(tim->irq); diff --git a/arch/xtensa/src/esp32/esp32_tim_lowerhalf.c b/arch/xtensa/src/esp32/esp32_tim_lowerhalf.c index 819091bbe413a..2927d0419e0fe 100644 --- a/arch/xtensa/src/esp32/esp32_tim_lowerhalf.c +++ b/arch/xtensa/src/esp32/esp32_tim_lowerhalf.c @@ -39,7 +39,7 @@ #include "hardware/esp32_soc.h" -#include "esp32_clockconfig.h" +#include "esp_clk.h" #include "esp32_tim.h" /**************************************************************************** diff --git a/arch/xtensa/src/esp32/esp32_timerisr.c b/arch/xtensa/src/esp32/esp32_timerisr.c index f0fce0ea21daf..fd4810436f0bd 100644 --- a/arch/xtensa/src/esp32/esp32_timerisr.c +++ b/arch/xtensa/src/esp32/esp32_timerisr.c @@ -35,6 +35,7 @@ #include "clock/clock.h" #include "xtensa_counter.h" #include "xtensa.h" +#include "esp_irq.h" /**************************************************************************** * Private data @@ -65,7 +66,7 @@ static uint32_t g_tick_divisor; * ****************************************************************************/ -static int esp32_timerisr(int irq, uint32_t *regs, void *arg) +static int esp32_timerisr(int irq, void *regs, void *arg) { uint32_t divisor; uint32_t compare; @@ -131,9 +132,14 @@ void up_timer_initialize(void) /* Attach the timer interrupt */ - irq_attach(XTENSA_IRQ_TIMER0, (xcpt_t)esp32_timerisr, NULL); + esp_setup_irq(ETS_INTERNAL_TIMER0_INTR_SOURCE, + ESP_IRQ_PRIORITY_1, + 0, + esp32_timerisr, + NULL); /* Enable the timer 0 CPU interrupt. */ - up_enable_irq(XTENSA_IRQ_TIMER0); + up_enable_irq(ETS_INTERNAL_TIMER0_INTR_SOURCE + + ETS_INTERNAL_INTR_SOURCE_OFF); } diff --git a/arch/xtensa/src/esp32/esp32_touch.c b/arch/xtensa/src/esp32/esp32_touch.c index 5f008dd7fbc7f..1e36361a58815 100644 --- a/arch/xtensa/src/esp32/esp32_touch.c +++ b/arch/xtensa/src/esp32/esp32_touch.c @@ -37,10 +37,12 @@ #include "xtensa.h" -#include "esp32_gpio.h" -#include "esp32_irq.h" -#include "esp32_rt_timer.h" -#include "esp32_rtc.h" +#include "esp_gpio.h" +#include "esp_irq.h" +#include "esp_hr_timer.h" +#include "espressif/esp_rtc.h" +#include "soc/rtc.h" +#include "esp32_rtc_gpio.h" #include "esp32_touch.h" #include "esp32_touch_lowerhalf.h" @@ -71,11 +73,19 @@ struct touch_config_meas_mode_s enum touch_tie_opt_e tie_opt; }; +#ifdef CONFIG_ESP32_TOUCH_IRQ +struct touchirq_handler_s +{ + xcpt_t handler; + void *arg; +}; +#endif + #ifdef CONFIG_ESP32_TOUCH_FILTER struct touch_filter_s { - struct rt_timer_args_s filter_timer_args; - struct rt_timer_s *filter_timer_handler; + struct esp_hr_timer_args_s filter_timer_args; + struct esp_hr_timer_s *filter_timer_handler; uint16_t filtered_val[TOUCH_SENSOR_PINS]; uint16_t raw_val[TOUCH_SENSOR_PINS]; uint32_t period_ms; @@ -122,8 +132,10 @@ static struct touch_filter_s *touch_pad_filter = NULL; static uint16_t touch_pad_isr_enabled = 0x0000; static int touch_last_irq = -1; static int (*touch_release_cb)(int, void *, void *) = NULL; -static struct rt_timer_args_s irq_timer_args; -static struct rt_timer_s *irq_timer_handler = NULL; +static struct touchirq_handler_s + g_touchirq_handlers[ESP32_NIRQ_RTCIO_TOUCHPAD]; +static struct esp_hr_timer_args_s irq_timer_args; +static struct esp_hr_timer_s *irq_timer_handler = NULL; #endif static mutex_t *touch_mux = NULL; static uint16_t touch_pad_init_bit = 0x0000; @@ -162,9 +174,9 @@ static int touch_interrupt(int irq, void *context, void *arg) status = touch_lh_read_trigger_status_mask(); touch_lh_clear_trigger_status_mask(); - rt_timer_start(irq_timer_handler, - CONFIG_ESP32_TOUCH_IRQ_INTERVAL_MS * USEC_PER_MSEC, - false); + esp_hr_timer_start_once(irq_timer_handler, + CONFIG_ESP32_TOUCH_IRQ_INTERVAL_MS * \ + USEC_PER_MSEC); /* Read and clear the touch interrupt status */ @@ -174,8 +186,16 @@ static int touch_interrupt(int irq, void *context, void *arg) (touch_pad_isr_enabled >> i) & (status >> i) & 0x1) { - touch_last_irq = ESP32_FIRST_RTCIOIRQ_TOUCHPAD + i; - irq_dispatch(touch_last_irq, context); + int touch_irq = ESP32_FIRST_RTCIOIRQ_TOUCHPAD + i; + + touch_last_irq = touch_irq; + + if (g_touchirq_handlers[i].handler != NULL) + { + g_touchirq_handlers[i].handler(touch_irq, + context, + g_touchirq_handlers[i].arg); + } } } @@ -201,13 +221,31 @@ static int touch_interrupt(int irq, void *context, void *arg) #ifdef CONFIG_ESP32_TOUCH_IRQ static void touch_restore_irq(void *arg) { - if (touch_last_irq > 0 && touch_release_cb != NULL) + iinfo("touch_restore_irq: entry\n"); + if (touch_last_irq >= ESP32_FIRST_RTCIOIRQ_TOUCHPAD && + touch_last_irq <= ESP32_LAST_RTCIOIRQ_TOUCHPAD) { - /* Call the button interrupt handler again so we can detect touch pad - * releases - */ + int bit = ESP32_IRQ2TOUCHPAD(touch_last_irq); - touch_release_cb(touch_last_irq, NULL, NULL); + if (bit >= 0 && bit < ESP32_NIRQ_RTCIO_TOUCHPAD && + g_touchirq_handlers[bit].handler != NULL) + { + /* Call the button interrupt handler again so we can detect touch + * pad releases. + */ + + g_touchirq_handlers[bit].handler(touch_last_irq, + NULL, + g_touchirq_handlers[bit].arg); + } + else if (touch_release_cb != NULL) + { + /* Backward compatible fallback for users of the old release + * callback API. + */ + + touch_release_cb(touch_last_irq, NULL, NULL); + } } touch_lh_intr_enable(); @@ -258,14 +296,26 @@ static void touch_init(void) touch_lh_start_fsm(); #ifdef CONFIG_ESP32_TOUCH_IRQ - irq_timer_args.arg = NULL; irq_timer_args.callback = touch_restore_irq; - rt_timer_create(&(irq_timer_args), &(irq_timer_handler)); + irq_timer_args.arg = NULL; + irq_timer_args.name = "touch_irq"; + irq_timer_args.skip_unhandled_events = false; - int ret = irq_attach(ESP32_IRQ_RTC_TOUCH, touch_interrupt, NULL); - if (ret < 0) + if (esp_hr_timer_create(&irq_timer_args, &irq_timer_handler) != OK) + { + ierr("ERROR: esp_hr_timer_create(irq) failed\n"); + } + + int ret = esp32_rtcioirqattach(ESP32_IRQ_RTC_TOUCH, + touch_interrupt, + NULL); + if (ret != OK) + { + ierr("ERROR: esp32_rtcioirqattach() failed: %d\n", ret); + } + else { - ierr("ERROR: irq_attach() failed: %d\n", ret); + esp32_rtcioirqenable(ESP32_IRQ_RTC_TOUCH); } #endif @@ -349,9 +399,8 @@ static void touch_filter_cb(void *arg) } } - rt_timer_start(touch_pad_filter->filter_timer_handler, - touch_pad_filter->period_ms * USEC_PER_MSEC, - false); + esp_hr_timer_start_once(touch_pad_filter->filter_timer_handler, + touch_pad_filter->period_ms * USEC_PER_MSEC); nxmutex_unlock(touch_mux); } @@ -391,10 +440,20 @@ static void touch_filter_start(uint32_t filter_period_ms) return; } - touch_pad_filter->filter_timer_args.arg = NULL; touch_pad_filter->filter_timer_args.callback = touch_filter_cb; - rt_timer_create(&(touch_pad_filter->filter_timer_args), - &(touch_pad_filter->filter_timer_handler)); + touch_pad_filter->filter_timer_args.arg = NULL; + touch_pad_filter->filter_timer_args.name = "touch_filter"; + touch_pad_filter->filter_timer_args.skip_unhandled_events = false; + + if (esp_hr_timer_create(&touch_pad_filter->filter_timer_args, + &touch_pad_filter->filter_timer_handler) != OK) + { + ierr("ERROR: esp_hr_timer_create(filter) failed\n"); + kmm_free(touch_pad_filter); + touch_pad_filter = NULL; + nxmutex_unlock(touch_mux); + return; + } touch_pad_filter->period_ms = filter_period_ms; } @@ -515,8 +574,8 @@ static void touch_config(enum touch_pad_e tp) uint32_t wait_time_ms = 0; uint16_t sleep_time = touch_lh_get_sleep_time(); uint16_t meas_cycle = touch_lh_get_meas_time(); - uint32_t rtc_slow_clk_freq = esp32_rtc_clk_slow_freq_get_hz(); - uint32_t rtc_fast_clk_freq = esp32_rtc_clk_fast_freq_get_hz(); + uint32_t rtc_slow_clk_freq = rtc_clk_slow_freq_get_hz(); + uint32_t rtc_fast_clk_freq = RTC_FAST_CLK_FREQ_APPROX; touch_set_group_mask((1 << tp), (1 << tp), (1 << tp)); /* If the FSM mode is 'TOUCH_FSM_MODE_TIMER', The data will be ready @@ -837,6 +896,84 @@ void esp32_touchirqdisable(int irq) } #endif +/**************************************************************************** + * Name: esp32_touchirqattach + * + * Description: + * Attach an interrupt handler to a specified touch pad IRQ. + * + * Input Parameters: + * irq - Touch pad IRQ number to attach the handler to + * handler - Interrupt handler function + * arg - Argument to pass to the handler + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32_TOUCH_IRQ +int esp32_touchirqattach(int irq, xcpt_t handler, void *arg) +{ + int bit; + + DEBUGASSERT(irq >= ESP32_FIRST_RTCIOIRQ_TOUCHPAD && + irq <= ESP32_LAST_RTCIOIRQ_TOUCHPAD); + + bit = ESP32_IRQ2TOUCHPAD(irq); + if (bit < 0 || bit >= ESP32_NIRQ_RTCIO_TOUCHPAD) + { + return -EINVAL; + } + + g_touchirq_handlers[bit].handler = handler; + g_touchirq_handlers[bit].arg = arg; + + return OK; +} + +/**************************************************************************** + * Name: esp32_touchirqdetach + * + * Description: + * Detach the interrupt handler for the specified touch pad IRQ and + * disable the interrupt. + * + * Input Parameters: + * irq - Touch pad IRQ number to detach. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +int esp32_touchirqdetach(int irq) +{ + int bit; + + DEBUGASSERT(irq >= ESP32_FIRST_RTCIOIRQ_TOUCHPAD && + irq <= ESP32_LAST_RTCIOIRQ_TOUCHPAD); + + bit = ESP32_IRQ2TOUCHPAD(irq); + if (bit < 0 || bit >= ESP32_NIRQ_RTCIO_TOUCHPAD) + { + return -EINVAL; + } + + touch_lh_intr_disable(); + + g_touchirq_handlers[bit].handler = NULL; + g_touchirq_handlers[bit].arg = NULL; + touch_pad_isr_enabled &= (~(UINT32_C(1) << bit)); + + touch_lh_intr_enable(); + + return OK; +} +#endif + /**************************************************************************** * Name: esp32_touchregisterreleasecb * @@ -845,9 +982,11 @@ void esp32_touchirqdisable(int irq) * ****************************************************************************/ +#ifdef CONFIG_ESP32_TOUCH_IRQ void esp32_touchregisterreleasecb(int (*func)(int, void *, void *)) { DEBUGASSERT(func != NULL); touch_release_cb = func; } +#endif diff --git a/arch/xtensa/src/esp32/esp32_touch.h b/arch/xtensa/src/esp32/esp32_touch.h index d48d3b4c61f4c..c696641173dcc 100644 --- a/arch/xtensa/src/esp32/esp32_touch.h +++ b/arch/xtensa/src/esp32/esp32_touch.h @@ -26,6 +26,7 @@ ****************************************************************************/ #include +#include #include #include @@ -207,6 +208,51 @@ void esp32_touchirqdisable(int irq); # define esp32_touchirqdisable(irq) #endif +/**************************************************************************** + * Name: esp32_touchirqattach + * + * Description: + * Attach an interrupt handler to a specified touch pad IRQ. + * + * Input Parameters: + * irq - Touch pad IRQ number to attach the handler to + * handler - Interrupt handler function + * arg - Argument to pass to the handler + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32_TOUCH_IRQ +int esp32_touchirqattach(int irq, xcpt_t handler, void *arg); +#else +# define esp32_touchirqattach(irq, handler, arg) -EINVAL +#endif + +/**************************************************************************** + * Name: esp32_touchirqdetach + * + * Description: + * Detach the interrupt handler for the specified touch pad IRQ and + * disable the interrupt. + * + * Input Parameters: + * irq - Touch pad IRQ number to detach. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32_TOUCH_IRQ +int esp32_touchirqdetach(int irq); +#else +# define esp32_touchirqdetach(irq) (-EINVAL) +#endif + /**************************************************************************** * Name: esp32_touchregisterreleasecb * diff --git a/arch/xtensa/src/esp32/esp32_touch_lowerhalf.h b/arch/xtensa/src/esp32/esp32_touch_lowerhalf.h index 59e727ac308cb..bfd7462c3073e 100644 --- a/arch/xtensa/src/esp32/esp32_touch_lowerhalf.h +++ b/arch/xtensa/src/esp32/esp32_touch_lowerhalf.h @@ -33,11 +33,11 @@ #include "xtensa.h" #include "hardware/esp32_rtc_io.h" -#include "hardware/esp32_rtccntl.h" +#include "soc/rtc_cntl_reg.h" #include "hardware/esp32_touch.h" #include "hardware/esp32_sens.h" -#include "esp32_rt_timer.h" +#include "esp_hr_timer.h" #include "esp32_rtc_gpio.h" /**************************************************************************** diff --git a/arch/xtensa/src/esp32/esp32_twai.c b/arch/xtensa/src/esp32/esp32_twai.c index 09b06ba8a9340..515d8f6bac8b9 100644 --- a/arch/xtensa/src/esp32/esp32_twai.c +++ b/arch/xtensa/src/esp32/esp32_twai.c @@ -41,10 +41,10 @@ #include "xtensa.h" -#include "esp32_gpio.h" +#include "esp_gpio.h" #include "esp32_twai.h" -#include "esp32_irq.h" -#include "esp32_clockconfig.h" +#include "esp_irq.h" +#include "esp_clk.h" #include "hardware/esp32_dport.h" #include "hardware/esp32_gpio_sigmap.h" @@ -476,8 +476,11 @@ static int esp32twai_setup(struct can_dev_s *dev) } priv->cpu = this_cpu(); - priv->cpuint = esp32_setup_irq(priv->cpu, priv->periph, - 1, ESP32_CPUINT_LEVEL); + priv->cpuint = esp_setup_irq(priv->periph, + 1, + ESP_IRQ_TRIGGER_LEVEL, + esp32twai_interrupt, + dev); if (priv->cpuint < 0) { /* Failed to allocate a CPU interrupt of this type. */ @@ -488,18 +491,6 @@ static int esp32twai_setup(struct can_dev_s *dev) return ret; } - ret = irq_attach(priv->irq, esp32twai_interrupt, dev); - if (ret != OK) - { - /* Failed to attach IRQ, so CPU interrupt must be freed. */ - - esp32_teardown_irq(priv->cpu, priv->periph, priv->cpuint); - priv->cpuint = -ENOMEM; - spin_unlock_irqrestore(&priv->lock, flags); - - return ret; - } - /* Enable the CPU interrupt that is linked to the TWAI device. */ up_enable_irq(priv->irq); @@ -538,13 +529,9 @@ static void esp32twai_shutdown(struct can_dev_s *dev) up_disable_irq(priv->irq); - /* Dissociate the IRQ from the ISR */ - - irq_detach(priv->irq); - /* Free cpu interrupt that is attached to this peripheral */ - esp32_teardown_irq(priv->cpu, priv->periph, priv->cpuint); + esp_teardown_irq(priv->periph, priv->cpuint); priv->cpuint = -ENOMEM; } } @@ -1235,11 +1222,11 @@ struct can_dev_s *esp32_twaiinitialize(int port) /* Configure CAN GPIO pins */ - esp32_gpio_matrix_out(CONFIG_ESP32_TWAI0_TXPIN, TWAI_TX_IDX, 0, 0); - esp32_configgpio(CONFIG_ESP32_TWAI0_TXPIN, OUTPUT_FUNCTION_1); + esp_gpio_matrix_out(CONFIG_ESP32_TWAI0_TXPIN, TWAI_TX_IDX, 0, 0); + esp_configgpio(CONFIG_ESP32_TWAI0_TXPIN, OUTPUT_FUNCTION_1); - esp32_configgpio(CONFIG_ESP32_TWAI0_RXPIN, INPUT_FUNCTION_1); - esp32_gpio_matrix_in(CONFIG_ESP32_TWAI0_RXPIN, TWAI_RX_IDX, 0); + esp_configgpio(CONFIG_ESP32_TWAI0_RXPIN, INPUT_FUNCTION_1); + esp_gpio_matrix_in(CONFIG_ESP32_TWAI0_RXPIN, TWAI_RX_IDX, 0); spin_unlock_irqrestore(&g_twai0priv.lock, flags); } diff --git a/arch/xtensa/src/esp32/esp32_userspace.c b/arch/xtensa/src/esp32/esp32_userspace.c index 22960f41968df..1730e9c55c4ec 100644 --- a/arch/xtensa/src/esp32/esp32_userspace.c +++ b/arch/xtensa/src/esp32/esp32_userspace.c @@ -35,7 +35,6 @@ #include "chip.h" #include "xtensa.h" -#include "xtensa_attr.h" #ifdef CONFIG_ESP32_USER_DATA_EXTMEM #include "esp32_spiram.h" #endif diff --git a/arch/xtensa/src/esp32/esp32_wdt.c b/arch/xtensa/src/esp32/esp32_wdt.c index d29ae20306ea8..6f448ceab098a 100644 --- a/arch/xtensa/src/esp32/esp32_wdt.c +++ b/arch/xtensa/src/esp32/esp32_wdt.c @@ -29,18 +29,42 @@ #include #include "xtensa.h" #include "hardware/esp32_tim.h" -#include "hardware/esp32_rtccntl.h" +#include "soc/rtc_cntl_reg.h" +#include "hal/rwdt_ll.h" #include "esp32_wdt.h" -#include "esp32_irq.h" -#include "esp32_rtc.h" +#include "espressif/esp_irq.h" +#include "soc/rtc.h" #include "esp32_rtc_gpio.h" /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ +/* Offset relative to each watchdog timer instance memory base */ + +#define RWDT_CONFIG0_OFFSET 0x0098 +#define XTWDT_CONFIG0_OFFSET 0x0060 + +/* RWDT */ + +#define RWDT_STAGE0_TIMEOUT_OFFSET 0x009C +#define RWDT_STAGE1_TIMEOUT_OFFSET 0x00A0 +#define RWDT_STAGE2_TIMEOUT_OFFSET 0x00A4 +#define RWDT_STAGE3_TIMEOUT_OFFSET 0x00A8 +#define RWDT_FEED_OFFSET 0x00AC +#define RWDT_WP_REG 0x00B0 +#define RWDT_INT_ENA_REG_OFFSET 0x0040 +#define RWDT_INT_CLR_REG_OFFSET 0x004c + +/* XTWDT */ + +#define XTWDT_TIMEOUT_OFFSET 0x00f8 +#define XTWDT_CLK_PRESCALE_OFFSET 0x00f4 +#define XTWDT_INT_ENA_REG_OFFSET 0x0040 + /* Helpers for converting from Q13.19 fixed-point format to float */ +#define SLOW_CLK_CAL_CYCLES 1024 #define N 19 #define Q_TO_FLOAT(x) ((float)x/(float)(1<irq == ESP32_IRQ_RTC_WDT) + if (wdt->cpuint >= 0) { - esp32_rtcioirqdisable(wdt->irq); - irq_detach(wdt->irq); - } - else +#ifdef CONFIG_ESP32_RWDT + if (wdt->irq == ESP32_IRQ_RTC_WDT) + { + esp32_rtcioirqdisable(wdt->irq); + esp32_rtcioirqdetach(wdt->irq); + } + else #endif - { - if (wdt->cpuint >= 0) { /* Disable CPU Interrupt, free a previously allocated * CPU Interrupt */ up_disable_irq(wdt->irq); - esp32_teardown_irq(wdt->cpu, wdt->periph, wdt->cpuint); - irq_detach(wdt->irq); - wdt->cpuint = -ENOMEM; + esp_teardown_irq(wdt->periph, wdt->cpuint); } - - goto errout; } + + goto errout; } /* Otherwise set callback and enable interrupt */ @@ -749,7 +771,9 @@ static int esp32_wdt_setisr(struct esp32_wdt_dev_s *dev, xcpt_t handler, #ifdef CONFIG_ESP32_RWDT if (wdt->irq == ESP32_IRQ_RTC_WDT) { - ret = irq_attach(wdt->irq, handler, arg); + /* RTC interrupts use special RTC IRQ handling */ + + ret = esp32_rtcioirqattach(wdt->irq, handler, arg); if (ret != OK) { @@ -763,9 +787,9 @@ static int esp32_wdt_setisr(struct esp32_wdt_dev_s *dev, xcpt_t handler, else #endif { - wdt->cpu = this_cpu(); - wdt->cpuint = esp32_setup_irq(wdt->cpu, wdt->periph, - 1, ESP32_CPUINT_LEVEL); + wdt->cpuint = esp_setup_irq(wdt->periph, 1, + ESP_IRQ_TRIGGER_LEVEL, + handler, arg); if (wdt->cpuint < 0) { tmrerr("ERROR: No CPU Interrupt available"); @@ -773,18 +797,7 @@ static int esp32_wdt_setisr(struct esp32_wdt_dev_s *dev, xcpt_t handler, goto errout; } - /* Associate an IRQ Number (from the WDT) to an ISR */ - - ret = irq_attach(wdt->irq, handler, arg); - - if (ret != OK) - { - esp32_teardown_irq(wdt->cpu, wdt->periph, wdt->cpuint); - tmrerr("ERROR: Failed to associate an IRQ Number"); - goto errout; - } - - /* Enable the CPU Interrupt that is linked to the wdt */ + /* Enable the CPU Interrupt that is linked to the WDT */ up_enable_irq(wdt->irq); } @@ -956,17 +969,6 @@ struct esp32_wdt_dev_s *esp32_wdt_init(uint8_t wdt_id) { wdt = &g_esp32_rwdt_priv; - /* If RTC was not initialized in a previous - * stage by the PM or by clock_initialize() - * Then, init the RTC clock configuration here. - */ - -#if !defined(CONFIG_PM) && !defined(CONFIG_RTC) - /* Initialize RTC controller parameters */ - - esp32_rtc_init(); - esp32_rtc_clk_set(); -#endif break; } diff --git a/arch/xtensa/src/esp32/esp32_wifi_adapter.c b/arch/xtensa/src/esp32/esp32_wifi_adapter.c index 3fa4829ec4ec0..8184637044a89 100644 --- a/arch/xtensa/src/esp32/esp32_wifi_adapter.c +++ b/arch/xtensa/src/esp32/esp32_wifi_adapter.c @@ -43,20 +43,21 @@ #include #include "xtensa.h" -#include "xtensa_attr.h" #include "hardware/esp32_dport.h" #include "hardware/esp32_emac.h" #include "espressif/esp_wireless.h" #include "esp32_wifi_adapter.h" -#include "esp32_rt_timer.h" - +#include "esp_hr_timer.h" +#include "esp_irq.h" +#include "esp_cpu.h" #include "espressif/esp_wireless.h" #include "espressif/esp_wifi_utils.h" +#include "platform/os.h" #include "periph_ctrl.h" #ifdef CONFIG_PM -# include "esp32_pm.h" +# include "espressif/esp_pm.h" #endif #ifdef CONFIG_ESPRESSIF_BLE @@ -78,29 +79,31 @@ * Private Types ****************************************************************************/ -/* Wi-Fi interrupt adapter private data */ +/* Wi-Fi time private data */ -struct irq_adpt +struct time_adpt { - void (*func)(void *arg); /* Interrupt callback function */ - void *arg; /* Interrupt private data */ + time_t sec; /* Second value */ + suseconds_t usec; /* Micro second value */ }; -/* Wi-Fi message queue private data */ +typedef struct shared_vector_desc_t shared_vector_desc_t; +typedef struct vector_desc_t vector_desc_t; -struct mq_adpt +typedef struct intr_handle_data_t { - struct file mq; /* Message queue handle */ - uint32_t msgsize; /* Message size */ - char name[16]; /* Message queue name */ -}; + vector_desc_t *vector_desc; + shared_vector_desc_t *shared_vector_desc; +} intr_handle_data_t; -/* Wi-Fi time private data */ - -struct time_adpt +struct vector_desc_t { - time_t sec; /* Second value */ - suseconds_t usec; /* Micro second value */ + int flags: 16; + unsigned int cpu: 1; + unsigned int intno: 5; + int source: 16; + shared_vector_desc_t *shared_vec_info; + vector_desc_t *next; }; /**************************************************************************** @@ -116,12 +119,12 @@ static int is_in_isr_wrapper(void); #endif /* CONFIG_ESPRESSIF_WIFI_BT_COEXIST */ static bool wifi_env_is_chip(void); -static void wifi_set_intr(int32_t cpu_no, uint32_t intr_source, - uint32_t intr_num, int32_t intr_prio); -static void wifi_clear_intr(uint32_t intr_source, uint32_t intr_num); -static void esp_set_isr(int32_t n, void *f, void *arg); -static void esp32_ints_on(uint32_t mask); -static void esp32_ints_off(uint32_t mask); +static void set_intr_wrapper(int32_t cpu_no, uint32_t intr_source, + uint32_t intr_num, int32_t intr_prio); +static void clear_intr_wrapper(uint32_t intr_source, uint32_t intr_num); +static void set_isr_wrapper(int32_t n, void *f, void *arg); +static void esp_cpu_intr_enable(uint32_t mask); +static void esp_cpu_intr_disable(uint32_t mask); static bool wifi_is_from_isr(void); static void *esp_spin_lock_create(void); static void esp_spin_lock_delete(void *lock); @@ -180,8 +183,8 @@ static uint32_t esp_get_free_heap_size(void); static uint32_t esp_rand(void); static void esp_dport_access_stall_other_cpu_start(void); static void esp_dport_access_stall_other_cpu_end(void); -static void wifi_apb80m_request(void); -static void wifi_apb80m_release(void); +static void wifi_apb80m_request_wrapper(void); +static void wifi_apb80m_release_wrapper(void); static void esp_phy_enable_wrapper(void); static void esp_phy_disable_wrapper(void); static int esp_wifi_read_mac(uint8_t *mac, unsigned int type); @@ -268,6 +271,13 @@ static int coex_schm_flexible_period_set_wrapper(uint8_t period); static uint8_t coex_schm_flexible_period_get_wrapper(void); static void * coex_schm_get_phase_by_idx_wrapper(int phase_idx); +extern vector_desc_t *get_desc_for_int(int intno, int cpu); + +#ifdef CONFIG_PM_ENABLE +extern void wifi_apb80m_request(void); +extern void wifi_apb80m_release(void); +#endif + /**************************************************************************** * Private Data ****************************************************************************/ @@ -311,11 +321,11 @@ wifi_osi_funcs_t g_wifi_osi_funcs = { ._version = ESP_WIFI_OS_ADAPTER_VERSION, ._env_is_chip = wifi_env_is_chip, - ._set_intr = wifi_set_intr, - ._clear_intr = wifi_clear_intr, - ._set_isr = esp_set_isr, - ._ints_on = esp32_ints_on, - ._ints_off = esp32_ints_off, + ._set_intr = set_intr_wrapper, + ._clear_intr = clear_intr_wrapper, + ._set_isr = set_isr_wrapper, + ._ints_on = esp_cpu_intr_enable, + ._ints_off = esp_cpu_intr_disable, ._is_from_isr = wifi_is_from_isr, ._spin_lock_create = esp_spin_lock_create, ._spin_lock_delete = esp_spin_lock_delete, @@ -361,8 +371,8 @@ wifi_osi_funcs_t g_wifi_osi_funcs = esp_dport_access_stall_other_cpu_start, ._dport_access_stall_other_cpu_end_wrap = esp_dport_access_stall_other_cpu_end, - ._wifi_apb80m_request = wifi_apb80m_request, - ._wifi_apb80m_release = wifi_apb80m_release, + ._wifi_apb80m_request = wifi_apb80m_request_wrapper, + ._wifi_apb80m_release = wifi_apb80m_release_wrapper, ._phy_disable = esp_phy_disable_wrapper, ._phy_enable = esp_phy_enable_wrapper, ._phy_common_clock_enable = esp_phy_common_clock_enable, @@ -441,31 +451,6 @@ wifi_osi_funcs_t g_wifi_osi_funcs = * Private Functions ****************************************************************************/ -/**************************************************************************** - * Name: esp_int_adpt_cb - * - * Description: - * Wi-Fi interrupt adapter callback function - * - * Input Parameters: - * irq - Number of the IRQ that generated the interrupt - * context - Interrupt register state save info (not used) - * arg - Argument passed to the interrupt callback - * - * Returned Value: - * OK - * - ****************************************************************************/ - -static int esp_int_adpt_cb(int irq, void *context, void *arg) -{ - struct irq_adpt *adapter = (struct irq_adpt *)arg; - - adapter->func(adapter->arg); - - return 0; -} - /**************************************************************************** * Name: esp_thread_semphr_free * @@ -512,7 +497,7 @@ static void esp_update_time(struct timespec *timespec, uint32_t ticks) } /**************************************************************************** - * Name: esp_set_isr + * Name: set_isr_wrapper * * Description: * Register interrupt function @@ -527,88 +512,9 @@ static void esp_update_time(struct timespec *timespec, uint32_t ticks) * ****************************************************************************/ -static void esp_set_isr(int32_t n, void *f, void *arg) +static void set_isr_wrapper(int32_t n, void *f, void *arg) { - int ret; - uint32_t tmp; - struct irq_adpt *adapter; - int irq = n + XTENSA_IRQ_FIRSTPERIPH; - - wlinfo("n=%" PRId32 " f=%p arg=%p irq=%d\n", n, f, arg, irq); - - if (g_irqvector[irq].handler && - g_irqvector[irq].handler != irq_unexpected_isr) - { - wlinfo("irq=%d has been set handler=%p\n", irq, - g_irqvector[irq].handler); - return; - } - - tmp = sizeof(struct irq_adpt); - adapter = kmm_malloc(tmp); - if (!adapter) - { - wlerr("Failed to alloc %" PRIu32 " memory\n", tmp); - PANIC(); - return; - } - - adapter->func = f; - adapter->arg = arg; - - ret = irq_attach(irq, esp_int_adpt_cb, adapter); - if (ret) - { - wlerr("Failed to attach IRQ %d\n", irq); - PANIC(); - return; - } -} - -/**************************************************************************** - * Name: esp32_ints_on - * - * Description: - * Enable Wi-Fi interrupt - * - * Input Parameters: - * mask - No mean - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void esp32_ints_on(uint32_t mask) -{ - int irq = __builtin_ffs(mask) - 1; - - wlinfo("INFO mask=0x08%" PRIx32 " irq=%d\n", mask, irq); - - up_enable_irq(ESP32_IRQ_MAC); -} - -/**************************************************************************** - * Name: esp32_ints_off - * - * Description: - * Disable Wi-Fi interrupt - * - * Input Parameters: - * mask - No mean - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void esp32_ints_off(uint32_t mask) -{ - uint32_t irq = __builtin_ffs(mask) - 1; - - wlinfo("INFO mask=0x08%" PRIx32 " irq=%" PRIu32 "\n", mask, irq); - - up_disable_irq(ESP32_IRQ_MAC); + xt_set_interrupt_handler(n, (xt_handler)f, arg); } /**************************************************************************** @@ -1843,7 +1749,7 @@ static bool wifi_env_is_chip(void) } /**************************************************************************** - * Name: wifi_set_intr + * Name: set_intr_wrapper * * Description: * Do nothing @@ -1859,24 +1765,43 @@ static bool wifi_env_is_chip(void) * ****************************************************************************/ -static void wifi_set_intr(int32_t cpu_no, uint32_t intr_source, +static void set_intr_wrapper(int32_t cpu_no, uint32_t intr_source, uint32_t intr_num, int32_t intr_prio) { + intr_handle_t handle; + int irq = ESP_SOURCE2IRQ(intr_source); + wlinfo("cpu_no=%" PRId32 ", intr_source=%" PRIu32 ", intr_num=%" PRIu32 ", intr_prio=%" PRId32 "\n", cpu_no, intr_source, intr_num, intr_prio); + + esp_rom_route_intr_matrix(cpu_no, intr_source, intr_num); + + handle = kmm_calloc(1, sizeof(intr_handle_data_t)); + if (handle == NULL) + { + wlerr("Failed to kmm_calloc\n"); + return; + } + + handle->vector_desc = get_desc_for_int(intr_num, cpu_no); + handle->vector_desc->source = intr_source; + + /* Register the handle - it contains all needed information (cpuint, cpu) */ + + esp_set_handle(cpu_no, irq, handle); } /**************************************************************************** - * Name: wifi_clear_intr + * Name: clear_intr_wrapper * * Description: * Don't support * ****************************************************************************/ -static void IRAM_ATTR wifi_clear_intr(uint32_t intr_source, - uint32_t intr_num) +static void IRAM_ATTR clear_intr_wrapper(uint32_t intr_source, + uint32_t intr_num) { } @@ -1971,10 +1896,10 @@ static void esp_dport_access_stall_other_cpu_end(void) * ****************************************************************************/ -static void wifi_apb80m_request(void) +static void IRAM_ATTR wifi_apb80m_request_wrapper(void) { -#ifdef CONFIG_ESP32_AUTO_SLEEP - esp32_pm_lockacquire(); +#ifdef CONFIG_PM_ENABLE + wifi_apb80m_request(); #endif } @@ -1986,10 +1911,10 @@ static void wifi_apb80m_request(void) * ****************************************************************************/ -static void wifi_apb80m_release(void) +static void IRAM_ATTR wifi_apb80m_release_wrapper(void) { -#ifdef CONFIG_ESP32_AUTO_SLEEP - esp32_pm_lockrelease(); +#ifdef CONFIG_PM_ENABLE + wifi_apb80m_release(); #endif } @@ -2320,7 +2245,7 @@ static void wifi_rtc_disable_iso(void) int64_t esp32_timer_get_time(void) { - return (int64_t)rt_timer_time_us(); + return (int64_t)esp_hr_timer_time_us(); } /**************************************************************************** diff --git a/arch/xtensa/src/esp32/hal.mk b/arch/xtensa/src/esp32/hal.mk index fabdc8de9ce1f..56ba95d7de7e1 100644 --- a/arch/xtensa/src/esp32/hal.mk +++ b/arch/xtensa/src/esp32/hal.mk @@ -20,6 +20,8 @@ # Include header paths +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)private_include @@ -30,30 +32,91 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_adc$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_adc$(DELIM)interface INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_adc$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_blockdev$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_common$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_event$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ana_conv$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ana_conv$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_dma$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_dma$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpio$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpio$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_i2c$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_i2c$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_i2s$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_i2s$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_mcpwm$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_mcpwm$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_mspi$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_mspi$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_parlio$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_parlio$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_pcnt$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_pcnt$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_rmt$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_rmt$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_timg$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_timg$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_twai$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_twai$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_touch_sens$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_touch_sens$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_usb$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_usb$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_wdt$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_wdt$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)dma$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_dma$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)etm$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include$(DELIM)esp_private INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include$(DELIM)soc +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include$(DELIM)soc$(DELIM)$(CHIP_SERIES) +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)heap$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)xtensa$(DELIM)deprecated_include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)xtensa$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)xtensa$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)ldo$(DELIM)include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi_timing_tuning$(DELIM)include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi_timing_tuning$(DELIM)tuning_scheme_impl$(DELIM)include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi_timing_tuning$(DELIM)port$(DELIM)$(CHIP_SERIES) +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi$(DELIM)mspi_intr$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi$(DELIM)mspi_timing_tuning$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi$(DELIM)mspi_timing_tuning$(DELIM)tuning_scheme_impl$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi$(DELIM)mspi_timing_tuning$(DELIM)port$(DELIM)$(CHIP_SERIES) INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)power_supply$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_clock$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_clock$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_pmu$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_pmu$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ledc$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ledc$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_security$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_security$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_uart$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_uart$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpspi$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpspi$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_rtc_timer$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_rtc_timer$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_security$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)include$(DELIM)esp_private INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_mm$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_pm +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_pm$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)$(CHIP_SERIES)$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES) INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)include$(DELIM)$(CHIP_SERIES) +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)include$(DELIM)$(CHIP_SERIES)$(DELIM)rom INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)include$(DELIM)esp32$(DELIM)rom INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)include$(DELIM)private INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)public_compat INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_timer$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_timer$(DELIM)private_include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_wifi$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)$(CHIP_SERIES)$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)include @@ -61,24 +124,37 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)log_level$(DELIM)tag_log_level +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port$(DELIM)include$(DELIM)aes +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port$(DELIM)psa_driver$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)newlib$(DELIM)priv_include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)tf-psa-crypto$(DELIM)drivers$(DELIM)builtin$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)tf-psa-crypto$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)tf-psa-crypto$(DELIM)core +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_libc$(DELIM)priv_include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)register INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)xtensa$(DELIM)baremetal INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)xtensa$(DELIM)$(CHIP_SERIES)$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)xtensa$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)xtensa$(DELIM)deprecated_include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)private_include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)bootloader_flash$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)include$(DELIM)spi_flash +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)include$(DELIM)esp_flash_chips INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_app_format$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_gpio$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_rmt$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_rmt$(DELIM)src +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_rmt$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_uart$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)$(CHIP_SERIES)$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)esp_driver_gpio$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)include$(DELIM)mbedtls +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)esp_libc$(DELIM)platform_include + # Linker scripts ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.api.ld @@ -107,67 +183,92 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_adc$(DELIM)$(CHIP_SERIES)$(DELIM)adc_cali_line_fitting.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_app_format$(DELIM)esp_app_desc.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_common$(DELIM)src$(DELIM)esp_err_to_name.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_touch_sens$(DELIM)touch_sens_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)adc_share_hw_ctrl.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)clk_ctrl_os.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)clk_utils.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)cpu.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)esp_clk.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)esp_gpio_reserve.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)esp_memory_utils.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)hw_random.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mac_addr.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi_timing_tuning$(DELIM)mspi_timing_tuning.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi$(DELIM)mspi_timing_tuning$(DELIM)mspi_timing_tuning.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)periph_ctrl.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)sar_periph_ctrl.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)cpu_region_protect.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)esp_clk_tree.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_clk.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_sleep.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_init.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_time.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)esp_clk_tree_common.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)regi2c_ctrl.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)rtc_module.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)sleep_event.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)sleep_gpio.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)sleep_modem.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)sleep_modes.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)sleep_uart.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)power_supply$(DELIM)brownout.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_libc$(DELIM)src$(DELIM)port$(DELIM)esp_time_impl.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_mm$(DELIM)esp_mmu_map.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_mm$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)ext_mem_layout.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_mm$(DELIM)esp_cache.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_mm$(DELIM)esp_cache_utils.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_mm$(DELIM)esp_cache_msync.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_mm$(DELIM)cache_esp32.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)$(CHIP_SERIES)$(DELIM)phy_init_data.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)src$(DELIM)phy_common.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)src$(DELIM)phy_init.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_uart.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_wdt.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_pm$(DELIM)pm_locks.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_pm$(DELIM)pm_impl.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_sys.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_print.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_crc.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_serial_output.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_spiflash.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_efuse.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_gpio.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)esp_err.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)esp_system.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)startup.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)startup_funcs.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)system_time.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)cpu_start.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)clk.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)system_internal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)adc_hal_common.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)adc_oneshot_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)$(CHIP_SERIES)$(DELIM)clk_tree_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_timer$(DELIM)src$(DELIM)esp_timer.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_timer$(DELIM)src$(DELIM)esp_timer_init.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_timer$(DELIM)src$(DELIM)esp_timer_impl_lac.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_timer$(DELIM)src$(DELIM)system_time.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_timer$(DELIM)src$(DELIM)esp_timer_impl_common.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ana_conv$(DELIM)adc_hal_common.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ana_conv$(DELIM)adc_oneshot_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_clock$(DELIM)$(CHIP_SERIES)$(DELIM)clk_tree_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)$(CHIP_SERIES)$(DELIM)efuse_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)brownout_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_pmu$(DELIM)brownout_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)efuse_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)gpio_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)ledc_hal_iram.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)ledc_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)pcnt_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)rmt_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)sdm_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)i2s_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)mcpwm_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)timer_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)uart_hal_iram.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)uart_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpio$(DELIM)gpio_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ledc$(DELIM)ledc_hal_iram.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ledc$(DELIM)ledc_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_pcnt$(DELIM)pcnt_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_rmt$(DELIM)rmt_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpio$(DELIM)sdm_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_i2s$(DELIM)i2s_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_mcpwm$(DELIM)mcpwm_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_timg$(DELIM)timer_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_uart$(DELIM)uart_hal_iram.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_uart$(DELIM)uart_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)mmu_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)i2c_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)sha_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_i2c$(DELIM)i2c_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_security$(DELIM)sha_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)hal_utils.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)spi_flash_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)spi_flash_hal_iram.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)wdt_hal_iram.c - -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)spi_flash_encrypt_hal_iram.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_mspi$(DELIM)spi_flash_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_mspi$(DELIM)spi_flash_hal_iram.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_mspi$(DELIM)spi_flash_encrypt_hal_iram.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_wdt$(DELIM)wdt_hal_iram.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)$(CHIP_SERIES)$(DELIM)cache_hal_esp32.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_security$(DELIM)mpu_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)dport_access_common.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)spi_flash_wrap.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)spi_flash_os_func_noos.c @@ -194,25 +295,53 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)noos$(DELIM)log_timestamp.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)os$(DELIM)log_write.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)os$(DELIM)util.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port$(DELIM)sha$(DELIM)core$(DELIM)esp_sha256.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)adc_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ana_conv$(DELIM)$(CHIP_SERIES)$(DELIM)adc_periph.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)gpio_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)ledc_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)pcnt_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)rmt_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)sdm_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)i2c_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)i2s_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)mcpwm_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ledc$(DELIM)$(CHIP_SERIES)$(DELIM)ledc_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_pcnt$(DELIM)$(CHIP_SERIES)$(DELIM)pcnt_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_rmt$(DELIM)$(CHIP_SERIES)$(DELIM)rmt_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpio$(DELIM)$(CHIP_SERIES)$(DELIM)sdm_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpio$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_io_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_i2c$(DELIM)$(CHIP_SERIES)$(DELIM)i2c_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_i2s$(DELIM)$(CHIP_SERIES)$(DELIM)i2s_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_mcpwm$(DELIM)$(CHIP_SERIES)$(DELIM)mcpwm_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_rmt$(DELIM)src$(DELIM)rmt_common.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_rmt$(DELIM)src$(DELIM)rmt_encoder.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_rmt$(DELIM)src$(DELIM)rmt_encoder_bytes.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_rmt$(DELIM)src$(DELIM)rmt_encoder_copy.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_rmt$(DELIM)src$(DELIM)rmt_encoder_simple.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_rmt$(DELIM)src$(DELIM)rmt_rx.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_rmt$(DELIM)src$(DELIM)rmt_tx.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_gpio$(DELIM)src$(DELIM)gpio.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_gpio$(DELIM)src$(DELIM)rtc_io.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_uart$(DELIM)src$(DELIM)uart_wakeup.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)platform$(DELIM)os.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)heap_caps.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)newlib$(DELIM)newlib$(DELIM)libc$(DELIM)misc$(DELIM)init.c + +# Security components (for WiFi/crypto support) +# Note: ESP32 doesn't support HMAC, so esp_security sources are excluded -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)esp_driver_gpio$(DELIM)src$(DELIM)rtc_io.c +# Interrupt allocator +# NOTE: ESP-IDF's xtensa_intr_asm.S cannot be used because it conflicts with +# NuttX's Xtensa core macro definitions. Instead, esp_xtensa_intr.c provides +# NuttX-native implementations of xt_ints_on, xt_ints_off, and related functions. +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)intr_alloc.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)esp_cpu_intr.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)xtensa$(DELIM)xtensa_intr.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)interrupts.c + +# IPC (Inter-Processor Communication) for SMP + +ifeq ($(CONFIG_SMP),y) +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)esp_system$(DELIM)esp_ipc.c +endif # Bootloader files CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)flash_encrypt.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)bootloader_flash$(DELIM)src$(DELIM)bootloader_flash.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)bootloader_flash$(DELIM)src$(DELIM)bootloader_flash_config_${CHIP_SERIES}.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_spiflash.c ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y) CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)bootloader_banner_wrap.c @@ -224,7 +353,6 @@ ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y) CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_common_loader.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)bootloader_flash$(DELIM)src$(DELIM)flash_qio_mode.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_clock_init.c - CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_clock_loader.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_efuse.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_mem.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_random.c @@ -233,11 +361,10 @@ ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y) CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)${CHIP_SERIES}$(DELIM)bootloader_soc.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_sha.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_clk_init.c - CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_sys.c - CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_crc.c - CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)mpu_hal.c LDFLAGS += --wrap=bootloader_print_banner endif +LDFLAGS += -u esp_timer_init_include_func + CFLAGS += ${DEFINE_PREFIX}ESP_PLATFORM=1 diff --git a/arch/xtensa/src/esp32/hardware/esp32_rtccntl.h b/arch/xtensa/src/esp32/hardware/esp32_rtccntl.h deleted file mode 100644 index 29a20dcc288bb..0000000000000 --- a/arch/xtensa/src/esp32/hardware/esp32_rtccntl.h +++ /dev/null @@ -1,3075 +0,0 @@ -/**************************************************************************** - * arch/xtensa/src/esp32/hardware/esp32_rtccntl.h - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_RTCCNTL_H -#define __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_RTCCNTL_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include "esp32_soc.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* WDT defines */ - -/* Offset relative to each watchdog timer instance memory base */ - -/* RWDT */ -#define RWDT_CONFIG0_OFFSET 0x008c -#define RWDT_STAGE0_TIMEOUT_OFFSET 0x0090 -#define RWDT_STAGE1_TIMEOUT_OFFSET 0x0094 -#define RWDT_STAGE2_TIMEOUT_OFFSET 0x0098 -#define RWDT_STAGE3_TIMEOUT_OFFSET 0x009c -#define RWDT_WP_REG 0x00a4 -#define RWDT_FEED_OFFSET 0x00a0 -#define RCLK_CONF_REG_OFFSET 0x0070 -#define RWDT_INT_ENA_REG_OFFSET 0x003c -#define RWDT_INT_CLR_REG_OFFSET 0x0048 - -/* The value that needs to be written to RTC_CNTL_WDT_WKEY to - * write-enable the wdt registers - */ - -#define RTC_CNTL_WDT_WKEY_VALUE 0x50d83aa1 - -/* CLK */ -#define CK_XTAL_32K_MASK (BIT(30)) -#define CK8M_D256_OUT_MASK (BIT(31)) - -#define RTC_CNTL_OPTIONS0_REG (DR_REG_RTCCNTL_BASE + 0x0) - -/* RTC_CNTL_SW_SYS_RST : WO ;bitpos:[31] ;default: 1'd0 ; */ - -/* Description: SW system reset */ - -#define RTC_CNTL_SW_SYS_RST (BIT(31)) -#define RTC_CNTL_SW_SYS_RST_M (BIT(31)) -#define RTC_CNTL_SW_SYS_RST_V 0x1 -#define RTC_CNTL_SW_SYS_RST_S 31 - -/* RTC_CNTL_DG_WRAP_FORCE_NORST : R/W ;bitpos:[30] ;default: 1'd0 ; */ - -/* Description: digital core force no reset in deep sleep */ - -#define RTC_CNTL_DG_WRAP_FORCE_NORST (BIT(30)) -#define RTC_CNTL_DG_WRAP_FORCE_NORST_M (BIT(30)) -#define RTC_CNTL_DG_WRAP_FORCE_NORST_V 0x1 -#define RTC_CNTL_DG_WRAP_FORCE_NORST_S 30 - -/* RTC_CNTL_DG_WRAP_FORCE_RST : R/W ;bitpos:[29] ;default: 1'd0 ; */ - -/* Description: digital wrap force reset in deep sleep */ - -#define RTC_CNTL_DG_WRAP_FORCE_RST (BIT(29)) -#define RTC_CNTL_DG_WRAP_FORCE_RST_M (BIT(29)) -#define RTC_CNTL_DG_WRAP_FORCE_RST_V 0x1 -#define RTC_CNTL_DG_WRAP_FORCE_RST_S 29 - -/* RTC_CNTL_ANALOG_FORCE_NOISO : R/W ;bitpos:[28] ;default: 1'd1 ; */ - -/* Description: */ - -#define RTC_CNTL_ANALOG_FORCE_NOISO (BIT(28)) -#define RTC_CNTL_ANALOG_FORCE_NOISO_M (BIT(28)) -#define RTC_CNTL_ANALOG_FORCE_NOISO_V 0x1 -#define RTC_CNTL_ANALOG_FORCE_NOISO_S 28 - -/* RTC_CNTL_PLL_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */ - -/* Description: */ - -#define RTC_CNTL_PLL_FORCE_NOISO (BIT(27)) -#define RTC_CNTL_PLL_FORCE_NOISO_M (BIT(27)) -#define RTC_CNTL_PLL_FORCE_NOISO_V 0x1 -#define RTC_CNTL_PLL_FORCE_NOISO_S 27 - -/* RTC_CNTL_XTL_FORCE_NOISO : R/W ;bitpos:[26] ;default: 1'd1 ; */ - -/* Description: */ - -#define RTC_CNTL_XTL_FORCE_NOISO (BIT(26)) -#define RTC_CNTL_XTL_FORCE_NOISO_M (BIT(26)) -#define RTC_CNTL_XTL_FORCE_NOISO_V 0x1 -#define RTC_CNTL_XTL_FORCE_NOISO_S 26 - -/* RTC_CNTL_ANALOG_FORCE_ISO : R/W ;bitpos:[25] ;default: 1'd0 ; */ - -/* Description: */ - -#define RTC_CNTL_ANALOG_FORCE_ISO (BIT(25)) -#define RTC_CNTL_ANALOG_FORCE_ISO_M (BIT(25)) -#define RTC_CNTL_ANALOG_FORCE_ISO_V 0x1 -#define RTC_CNTL_ANALOG_FORCE_ISO_S 25 - -/* RTC_CNTL_PLL_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */ - -/* Description: */ - -#define RTC_CNTL_PLL_FORCE_ISO (BIT(24)) -#define RTC_CNTL_PLL_FORCE_ISO_M (BIT(24)) -#define RTC_CNTL_PLL_FORCE_ISO_V 0x1 -#define RTC_CNTL_PLL_FORCE_ISO_S 24 - -/* RTC_CNTL_XTL_FORCE_ISO : R/W ;bitpos:[23] ;default: 1'd0 ; */ - -/* Description: */ - -#define RTC_CNTL_XTL_FORCE_ISO (BIT(23)) -#define RTC_CNTL_XTL_FORCE_ISO_M (BIT(23)) -#define RTC_CNTL_XTL_FORCE_ISO_V 0x1 -#define RTC_CNTL_XTL_FORCE_ISO_S 23 - -/* RTC_CNTL_BIAS_CORE_FORCE_PU : R/W ;bitpos:[22] ;default: 1'd1 ; */ - -/* Description: BIAS_CORE force power up */ - -#define RTC_CNTL_BIAS_CORE_FORCE_PU (BIT(22)) -#define RTC_CNTL_BIAS_CORE_FORCE_PU_M (BIT(22)) -#define RTC_CNTL_BIAS_CORE_FORCE_PU_V 0x1 -#define RTC_CNTL_BIAS_CORE_FORCE_PU_S 22 - -/* RTC_CNTL_BIAS_CORE_FORCE_PD : R/W ;bitpos:[21] ;default: 1'b0 ; */ - -/* Description: BIAS_CORE force power down */ - -#define RTC_CNTL_BIAS_CORE_FORCE_PD (BIT(21)) -#define RTC_CNTL_BIAS_CORE_FORCE_PD_M (BIT(21)) -#define RTC_CNTL_BIAS_CORE_FORCE_PD_V 0x1 -#define RTC_CNTL_BIAS_CORE_FORCE_PD_S 21 - -/* RTC_CNTL_BIAS_CORE_FOLW_8M : R/W ;bitpos:[20] ;default: 1'd0 ; */ - -/* Description: BIAS_CORE follow CK8M */ - -#define RTC_CNTL_BIAS_CORE_FOLW_8M (BIT(20)) -#define RTC_CNTL_BIAS_CORE_FOLW_8M_M (BIT(20)) -#define RTC_CNTL_BIAS_CORE_FOLW_8M_V 0x1 -#define RTC_CNTL_BIAS_CORE_FOLW_8M_S 20 - -/* RTC_CNTL_BIAS_I2C_FORCE_PU : R/W ;bitpos:[19] ;default: 1'd1 ; */ - -/* Description: BIAS_I2C force power up */ - -#define RTC_CNTL_BIAS_I2C_FORCE_PU (BIT(19)) -#define RTC_CNTL_BIAS_I2C_FORCE_PU_M (BIT(19)) -#define RTC_CNTL_BIAS_I2C_FORCE_PU_V 0x1 -#define RTC_CNTL_BIAS_I2C_FORCE_PU_S 19 - -/* RTC_CNTL_BIAS_I2C_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b0 ; */ - -/* Description: BIAS_I2C force power down */ - -#define RTC_CNTL_BIAS_I2C_FORCE_PD (BIT(18)) -#define RTC_CNTL_BIAS_I2C_FORCE_PD_M (BIT(18)) -#define RTC_CNTL_BIAS_I2C_FORCE_PD_V 0x1 -#define RTC_CNTL_BIAS_I2C_FORCE_PD_S 18 - -/* RTC_CNTL_BIAS_I2C_FOLW_8M : R/W ;bitpos:[17] ;default: 1'd0 ; */ - -/* Description: BIAS_I2C follow CK8M */ - -#define RTC_CNTL_BIAS_I2C_FOLW_8M (BIT(17)) -#define RTC_CNTL_BIAS_I2C_FOLW_8M_M (BIT(17)) -#define RTC_CNTL_BIAS_I2C_FOLW_8M_V 0x1 -#define RTC_CNTL_BIAS_I2C_FOLW_8M_S 17 - -/* RTC_CNTL_BIAS_FORCE_NOSLEEP : R/W ;bitpos:[16] ;default: 1'd1 ; */ - -/* Description: BIAS_SLEEP force no sleep */ - -#define RTC_CNTL_BIAS_FORCE_NOSLEEP (BIT(16)) -#define RTC_CNTL_BIAS_FORCE_NOSLEEP_M (BIT(16)) -#define RTC_CNTL_BIAS_FORCE_NOSLEEP_V 0x1 -#define RTC_CNTL_BIAS_FORCE_NOSLEEP_S 16 - -/* RTC_CNTL_BIAS_FORCE_SLEEP : R/W ;bitpos:[15] ;default: 1'b0 ; */ - -/* Description: BIAS_SLEEP force sleep */ - -#define RTC_CNTL_BIAS_FORCE_SLEEP (BIT(15)) -#define RTC_CNTL_BIAS_FORCE_SLEEP_M (BIT(15)) -#define RTC_CNTL_BIAS_FORCE_SLEEP_V 0x1 -#define RTC_CNTL_BIAS_FORCE_SLEEP_S 15 - -/* RTC_CNTL_BIAS_SLEEP_FOLW_8M : R/W ;bitpos:[14] ;default: 1'b0 ; */ - -/* Description: BIAS_SLEEP follow CK8M */ - -#define RTC_CNTL_BIAS_SLEEP_FOLW_8M (BIT(14)) -#define RTC_CNTL_BIAS_SLEEP_FOLW_8M_M (BIT(14)) -#define RTC_CNTL_BIAS_SLEEP_FOLW_8M_V 0x1 -#define RTC_CNTL_BIAS_SLEEP_FOLW_8M_S 14 - -/* RTC_CNTL_XTL_FORCE_PU : R/W ;bitpos:[13] ;default: 1'd1 ; */ - -/* Description: crystall force power up */ - -#define RTC_CNTL_XTL_FORCE_PU (BIT(13)) -#define RTC_CNTL_XTL_FORCE_PU_M (BIT(13)) -#define RTC_CNTL_XTL_FORCE_PU_V 0x1 -#define RTC_CNTL_XTL_FORCE_PU_S 13 - -/* RTC_CNTL_XTL_FORCE_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */ - -/* Description: crystall force power down */ - -#define RTC_CNTL_XTL_FORCE_PD (BIT(12)) -#define RTC_CNTL_XTL_FORCE_PD_M (BIT(12)) -#define RTC_CNTL_XTL_FORCE_PD_V 0x1 -#define RTC_CNTL_XTL_FORCE_PD_S 12 - -/* RTC_CNTL_BBPLL_FORCE_PU : R/W ;bitpos:[11] ;default: 1'd0 ; */ - -/* Description: BB_PLL force power up */ - -#define RTC_CNTL_BBPLL_FORCE_PU (BIT(11)) -#define RTC_CNTL_BBPLL_FORCE_PU_M (BIT(11)) -#define RTC_CNTL_BBPLL_FORCE_PU_V 0x1 -#define RTC_CNTL_BBPLL_FORCE_PU_S 11 - -/* RTC_CNTL_BBPLL_FORCE_PD : R/W ;bitpos:[10] ;default: 1'b0 ; */ - -/* Description: BB_PLL force power down */ - -#define RTC_CNTL_BBPLL_FORCE_PD (BIT(10)) -#define RTC_CNTL_BBPLL_FORCE_PD_M (BIT(10)) -#define RTC_CNTL_BBPLL_FORCE_PD_V 0x1 -#define RTC_CNTL_BBPLL_FORCE_PD_S 10 - -/* RTC_CNTL_BBPLL_I2C_FORCE_PU : R/W ;bitpos:[9] ;default: 1'd0 ; */ - -/* Description: BB_PLL_I2C force power up */ - -#define RTC_CNTL_BBPLL_I2C_FORCE_PU (BIT(9)) -#define RTC_CNTL_BBPLL_I2C_FORCE_PU_M (BIT(9)) -#define RTC_CNTL_BBPLL_I2C_FORCE_PU_V 0x1 -#define RTC_CNTL_BBPLL_I2C_FORCE_PU_S 9 - -/* RTC_CNTL_BBPLL_I2C_FORCE_PD : R/W ;bitpos:[8] ;default: 1'b0 ; */ - -/* Description: BB_PLL _I2C force power down */ - -#define RTC_CNTL_BBPLL_I2C_FORCE_PD (BIT(8)) -#define RTC_CNTL_BBPLL_I2C_FORCE_PD_M (BIT(8)) -#define RTC_CNTL_BBPLL_I2C_FORCE_PD_V 0x1 -#define RTC_CNTL_BBPLL_I2C_FORCE_PD_S 8 - -/* RTC_CNTL_BB_I2C_FORCE_PU : R/W ;bitpos:[7] ;default: 1'd0 ; */ - -/* Description: BB_I2C force power up */ - -#define RTC_CNTL_BB_I2C_FORCE_PU (BIT(7)) -#define RTC_CNTL_BB_I2C_FORCE_PU_M (BIT(7)) -#define RTC_CNTL_BB_I2C_FORCE_PU_V 0x1 -#define RTC_CNTL_BB_I2C_FORCE_PU_S 7 - -/* RTC_CNTL_BB_I2C_FORCE_PD : R/W ;bitpos:[6] ;default: 1'b0 ; */ - -/* Description: BB_I2C force power down */ - -#define RTC_CNTL_BB_I2C_FORCE_PD (BIT(6)) -#define RTC_CNTL_BB_I2C_FORCE_PD_M (BIT(6)) -#define RTC_CNTL_BB_I2C_FORCE_PD_V 0x1 -#define RTC_CNTL_BB_I2C_FORCE_PD_S 6 - -/* RTC_CNTL_SW_PROCPU_RST : WO ;bitpos:[5] ;default: 1'b0 ; */ - -/* Description: PRO CPU SW reset */ - -#define RTC_CNTL_SW_PROCPU_RST (BIT(5)) -#define RTC_CNTL_SW_PROCPU_RST_M (BIT(5)) -#define RTC_CNTL_SW_PROCPU_RST_V 0x1 -#define RTC_CNTL_SW_PROCPU_RST_S 5 - -/* RTC_CNTL_SW_APPCPU_RST : WO ;bitpos:[4] ;default: 1'b0 ; */ - -/* Description: APP CPU SW reset */ - -#define RTC_CNTL_SW_APPCPU_RST (BIT(4)) -#define RTC_CNTL_SW_APPCPU_RST_M (BIT(4)) -#define RTC_CNTL_SW_APPCPU_RST_V 0x1 -#define RTC_CNTL_SW_APPCPU_RST_S 4 - -/* RTC_CNTL_SW_STALL_PROCPU_C0 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */ - -/* Description: {reg_sw_stall_procpu_c1[5:0] - * reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU - */ - -#define RTC_CNTL_SW_STALL_PROCPU_C0 0x00000003 -#define RTC_CNTL_SW_STALL_PROCPU_C0_M ((RTC_CNTL_SW_STALL_PROCPU_C0_V)<<(RTC_CNTL_SW_STALL_PROCPU_C0_S)) -#define RTC_CNTL_SW_STALL_PROCPU_C0_V 0x3 -#define RTC_CNTL_SW_STALL_PROCPU_C0_S 2 - -/* RTC_CNTL_SW_STALL_APPCPU_C0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ - -/* Description: {reg_sw_stall_appcpu_c1[5:0] - * reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU - */ - -#define RTC_CNTL_SW_STALL_APPCPU_C0 0x00000003 -#define RTC_CNTL_SW_STALL_APPCPU_C0_M ((RTC_CNTL_SW_STALL_APPCPU_C0_V)<<(RTC_CNTL_SW_STALL_APPCPU_C0_S)) -#define RTC_CNTL_SW_STALL_APPCPU_C0_V 0x3 -#define RTC_CNTL_SW_STALL_APPCPU_C0_S 0 - -#define RTC_CNTL_SLP_TIMER0_REG (DR_REG_RTCCNTL_BASE + 0x4) - -/* RTC_CNTL_SLP_VAL_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ - -/* Description: RTC sleep timer low 32 bits */ - -#define RTC_CNTL_SLP_VAL_LO 0xFFFFFFFF -#define RTC_CNTL_SLP_VAL_LO_M ((RTC_CNTL_SLP_VAL_LO_V)<<(RTC_CNTL_SLP_VAL_LO_S)) -#define RTC_CNTL_SLP_VAL_LO_V 0xFFFFFFFF -#define RTC_CNTL_SLP_VAL_LO_S 0 - -#define RTC_CNTL_SLP_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x8) - -/* RTC_CNTL_MAIN_TIMER_ALARM_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */ - -/* Description: timer alarm enable bit */ - -#define RTC_CNTL_MAIN_TIMER_ALARM_EN (BIT(16)) -#define RTC_CNTL_MAIN_TIMER_ALARM_EN_M (BIT(16)) -#define RTC_CNTL_MAIN_TIMER_ALARM_EN_V 0x1 -#define RTC_CNTL_MAIN_TIMER_ALARM_EN_S 16 - -/* RTC_CNTL_SLP_VAL_HI : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ - -/* Description: RTC sleep timer high 16 bits */ - -#define RTC_CNTL_SLP_VAL_HI 0x0000FFFF -#define RTC_CNTL_SLP_VAL_HI_M ((RTC_CNTL_SLP_VAL_HI_V)<<(RTC_CNTL_SLP_VAL_HI_S)) -#define RTC_CNTL_SLP_VAL_HI_V 0xFFFF -#define RTC_CNTL_SLP_VAL_HI_S 0 - -#define RTC_CNTL_TIME_UPDATE_REG (DR_REG_RTCCNTL_BASE + 0xc) - -/* RTC_CNTL_TIME_UPDATE : WO ;bitpos:[31] ;default: 1'h0 ; */ - -/* Description: Set 1: to update register with RTC timer */ - -#define RTC_CNTL_TIME_UPDATE (BIT(31)) -#define RTC_CNTL_TIME_UPDATE_M (BIT(31)) -#define RTC_CNTL_TIME_UPDATE_V 0x1 -#define RTC_CNTL_TIME_UPDATE_S 31 - -/* RTC_CNTL_TIME_VALID : RO ;bitpos:[30] ;default: 1'b0 ; */ - -/* Description: To indicate the register is updated */ - -#define RTC_CNTL_TIME_VALID (BIT(30)) -#define RTC_CNTL_TIME_VALID_M (BIT(30)) -#define RTC_CNTL_TIME_VALID_V 0x1 -#define RTC_CNTL_TIME_VALID_S 30 - -#define RTC_CNTL_TIME0_REG (DR_REG_RTCCNTL_BASE + 0x10) - -/* RTC_CNTL_TIME_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; */ - -/* Description: RTC timer low 32 bits */ - -#define RTC_CNTL_TIME_LO 0xFFFFFFFF -#define RTC_CNTL_TIME_LO_M ((RTC_CNTL_TIME_LO_V)<<(RTC_CNTL_TIME_LO_S)) -#define RTC_CNTL_TIME_LO_V 0xFFFFFFFF -#define RTC_CNTL_TIME_LO_S 0 - -#define RTC_CNTL_TIME1_REG (DR_REG_RTCCNTL_BASE + 0x14) - -/* RTC_CNTL_TIME_HI : RO ;bitpos:[15:0] ;default: 16'h0 ; */ - -/* Description: RTC timer high 16 bits */ - -#define RTC_CNTL_TIME_HI 0x0000FFFF -#define RTC_CNTL_TIME_HI_M ((RTC_CNTL_TIME_HI_V)<<(RTC_CNTL_TIME_HI_S)) -#define RTC_CNTL_TIME_HI_V 0xFFFF -#define RTC_CNTL_TIME_HI_S 0 - -#define RTC_CNTL_STATE0_REG (DR_REG_RTCCNTL_BASE + 0x18) - -/* RTC_CNTL_SLEEP_EN : R/W ;bitpos:[31] ;default: 1'd0 ; */ - -/* Description: sleep enable bit */ - -#define RTC_CNTL_SLEEP_EN (BIT(31)) -#define RTC_CNTL_SLEEP_EN_M (BIT(31)) -#define RTC_CNTL_SLEEP_EN_V 0x1 -#define RTC_CNTL_SLEEP_EN_S 31 - -/* RTC_CNTL_SLP_REJECT : R/W ;bitpos:[30] ;default: 1'd0 ; */ - -/* Description: sleep reject bit */ - -#define RTC_CNTL_SLP_REJECT (BIT(30)) -#define RTC_CNTL_SLP_REJECT_M (BIT(30)) -#define RTC_CNTL_SLP_REJECT_V 0x1 -#define RTC_CNTL_SLP_REJECT_S 30 - -/* RTC_CNTL_SLP_WAKEUP : R/W ;bitpos:[29] ;default: 1'd0 ; */ - -/* Description: sleep wakeup bit */ - -#define RTC_CNTL_SLP_WAKEUP (BIT(29)) -#define RTC_CNTL_SLP_WAKEUP_M (BIT(29)) -#define RTC_CNTL_SLP_WAKEUP_V 0x1 -#define RTC_CNTL_SLP_WAKEUP_S 29 - -/* RTC_CNTL_SDIO_ACTIVE_IND : RO ;bitpos:[28] ;default: 1'd0 ; */ - -/* Description: SDIO active indication */ - -#define RTC_CNTL_SDIO_ACTIVE_IND (BIT(28)) -#define RTC_CNTL_SDIO_ACTIVE_IND_M (BIT(28)) -#define RTC_CNTL_SDIO_ACTIVE_IND_V 0x1 -#define RTC_CNTL_SDIO_ACTIVE_IND_S 28 - -/* RTC_CNTL_ULP_CP_SLP_TIMER_EN : R/W ;bitpos:[24] ;default: 1'd0 ; */ - -/* Description: ULP-coprocessor timer enable bit */ - -#define RTC_CNTL_ULP_CP_SLP_TIMER_EN (BIT(24)) -#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_M (BIT(24)) -#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_V 0x1 -#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_S 24 - -/* RTC_CNTL_TOUCH_SLP_TIMER_EN : R/W ;bitpos:[23] ;default: 1'd0 ; */ - -/* Description: touch timer enable bit */ - -#define RTC_CNTL_TOUCH_SLP_TIMER_EN (BIT(23)) -#define RTC_CNTL_TOUCH_SLP_TIMER_EN_M (BIT(23)) -#define RTC_CNTL_TOUCH_SLP_TIMER_EN_V 0x1 -#define RTC_CNTL_TOUCH_SLP_TIMER_EN_S 23 - -/* RTC_CNTL_APB2RTC_BRIDGE_SEL : R/W ;bitpos:[22] ;default: 1'd0 ; */ - -/* Description: 1: APB to RTC using bridge 0: APB to RTC using sync */ - -#define RTC_CNTL_APB2RTC_BRIDGE_SEL (BIT(22)) -#define RTC_CNTL_APB2RTC_BRIDGE_SEL_M (BIT(22)) -#define RTC_CNTL_APB2RTC_BRIDGE_SEL_V 0x1 -#define RTC_CNTL_APB2RTC_BRIDGE_SEL_S 22 - -/* RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN : R/W ;bitpos:[21] ;default: 1'd1 ; */ - -/* Description: ULP-coprocessor force wake up */ - -#define RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN (BIT(21)) -#define RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN_M (BIT(21)) -#define RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN_V 0x1 -#define RTC_CNTL_ULP_CP_WAKEUP_FORCE_EN_S 21 - -/* RTC_CNTL_TOUCH_WAKEUP_FORCE_EN : R/W ;bitpos:[20] ;default: 1'd1 ; */ - -/* Description: touch controller force wake up */ - -#define RTC_CNTL_TOUCH_WAKEUP_FORCE_EN (BIT(20)) -#define RTC_CNTL_TOUCH_WAKEUP_FORCE_EN_M (BIT(20)) -#define RTC_CNTL_TOUCH_WAKEUP_FORCE_EN_V 0x1 -#define RTC_CNTL_TOUCH_WAKEUP_FORCE_EN_S 20 - -#define RTC_CNTL_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x1c) - -/* RTC_CNTL_PLL_BUF_WAIT : R/W ;bitpos:[31:24] ;default: 8'd40 ; */ - -/* Description: PLL wait cycles in slow_clk_rtc */ - -#define RTC_CNTL_PLL_BUF_WAIT 0x000000FF -#define RTC_CNTL_PLL_BUF_WAIT_M ((RTC_CNTL_PLL_BUF_WAIT_V)<<(RTC_CNTL_PLL_BUF_WAIT_S)) -#define RTC_CNTL_PLL_BUF_WAIT_V 0xFF -#define RTC_CNTL_PLL_BUF_WAIT_S 24 -#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 20 - -/* RTC_CNTL_XTL_BUF_WAIT : R/W ;bitpos:[23:14] ;default: 10'd80 ; */ - -/* Description: XTAL wait cycles in slow_clk_rtc */ - -#define RTC_CNTL_XTL_BUF_WAIT 0x000003FF -#define RTC_CNTL_XTL_BUF_WAIT_M ((RTC_CNTL_XTL_BUF_WAIT_V)<<(RTC_CNTL_XTL_BUF_WAIT_S)) -#define RTC_CNTL_XTL_BUF_WAIT_V 0x3FF -#define RTC_CNTL_XTL_BUF_WAIT_S 14 -#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 20 - -/* RTC_CNTL_CK8M_WAIT : R/W ;bitpos:[13:6] ;default: 8'h10 ; */ - -/* Description: CK8M wait cycles in slow_clk_rtc */ - -#define RTC_CNTL_CK8M_WAIT 0x000000FF -#define RTC_CNTL_CK8M_WAIT_M ((RTC_CNTL_CK8M_WAIT_V)<<(RTC_CNTL_CK8M_WAIT_S)) -#define RTC_CNTL_CK8M_WAIT_V 0xFF -#define RTC_CNTL_CK8M_WAIT_S 6 -#define RTC_CNTL_CK8M_WAIT_DEFAULT 20 - -/* RTC_CNTL_CPU_STALL_WAIT : R/W ;bitpos:[5:1] ;default: 5'd1 ; */ - -/* Description: CPU stall wait cycles in fast_clk_rtc */ - -#define RTC_CNTL_CPU_STALL_WAIT 0x0000001F -#define RTC_CNTL_CPU_STALL_WAIT_M ((RTC_CNTL_CPU_STALL_WAIT_V)<<(RTC_CNTL_CPU_STALL_WAIT_S)) -#define RTC_CNTL_CPU_STALL_WAIT_V 0x1F -#define RTC_CNTL_CPU_STALL_WAIT_S 1 - -/* RTC_CNTL_CPU_STALL_EN : R/W ;bitpos:[0] ;default: 1'd1 ; */ - -/* Description: CPU stall enable bit */ - -#define RTC_CNTL_CPU_STALL_EN (BIT(0)) -#define RTC_CNTL_CPU_STALL_EN_M (BIT(0)) -#define RTC_CNTL_CPU_STALL_EN_V 0x1 -#define RTC_CNTL_CPU_STALL_EN_S 0 - -#define RTC_CNTL_TIMER2_REG (DR_REG_RTCCNTL_BASE + 0x20) - -/* RTC_CNTL_MIN_TIME_CK8M_OFF : R/W ;bitpos:[31:24] ;default: 8'h1 ; */ - -/* Description: minimal cycles in slow_clk_rtc for CK8M in power down state */ - -#define RTC_CNTL_MIN_TIME_CK8M_OFF 0x000000FF -#define RTC_CNTL_MIN_TIME_CK8M_OFF_M ((RTC_CNTL_MIN_TIME_CK8M_OFF_V)<<(RTC_CNTL_MIN_TIME_CK8M_OFF_S)) -#define RTC_CNTL_MIN_TIME_CK8M_OFF_V 0xFF -#define RTC_CNTL_MIN_TIME_CK8M_OFF_S 24 - -/* RTC_CNTL_ULPCP_TOUCH_START_WAIT : R/W ;bitpos:[23:15] ;default: 9'h10 ; */ - -/* Description: wait cycles in slow_clk_rtc before ULP-coprocessor / - * touch controller start to work - */ - -#define RTC_CNTL_ULPCP_TOUCH_START_WAIT 0x000001FF -#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_M ((RTC_CNTL_ULPCP_TOUCH_START_WAIT_V)<<(RTC_CNTL_ULPCP_TOUCH_START_WAIT_S)) -#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_V 0x1FF -#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_S 15 - -#define RTC_CNTL_TIMER3_REG (DR_REG_RTCCNTL_BASE + 0x24) - -/* RTC_CNTL_ROM_RAM_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'd10 ; */ - -/* Description: */ - -#define RTC_CNTL_ROM_RAM_POWERUP_TIMER 0x0000007F -#define RTC_CNTL_ROM_RAM_POWERUP_TIMER_M ((RTC_CNTL_ROM_RAM_POWERUP_TIMER_V)<<(RTC_CNTL_ROM_RAM_POWERUP_TIMER_S)) -#define RTC_CNTL_ROM_RAM_POWERUP_TIMER_V 0x7F -#define RTC_CNTL_ROM_RAM_POWERUP_TIMER_S 25 - -/* RTC_CNTL_ROM_RAM_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h16 ; */ - -/* Description: */ - -#define RTC_CNTL_ROM_RAM_WAIT_TIMER 0x000001FF -#define RTC_CNTL_ROM_RAM_WAIT_TIMER_M ((RTC_CNTL_ROM_RAM_WAIT_TIMER_V)<<(RTC_CNTL_ROM_RAM_WAIT_TIMER_S)) -#define RTC_CNTL_ROM_RAM_WAIT_TIMER_V 0x1FF -#define RTC_CNTL_ROM_RAM_WAIT_TIMER_S 16 - -/* RTC_CNTL_WIFI_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */ - -/* Description: */ - -#define RTC_CNTL_WIFI_POWERUP_TIMER 0x0000007F -#define RTC_CNTL_WIFI_POWERUP_TIMER_M ((RTC_CNTL_WIFI_POWERUP_TIMER_V)<<(RTC_CNTL_WIFI_POWERUP_TIMER_S)) -#define RTC_CNTL_WIFI_POWERUP_TIMER_V 0x7F -#define RTC_CNTL_WIFI_POWERUP_TIMER_S 9 - -/* RTC_CNTL_WIFI_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */ - -/* Description: */ - -#define RTC_CNTL_WIFI_WAIT_TIMER 0x000001FF -#define RTC_CNTL_WIFI_WAIT_TIMER_M ((RTC_CNTL_WIFI_WAIT_TIMER_V)<<(RTC_CNTL_WIFI_WAIT_TIMER_S)) -#define RTC_CNTL_WIFI_WAIT_TIMER_V 0x1FF -#define RTC_CNTL_WIFI_WAIT_TIMER_S 0 - -#define RTC_CNTL_TIMER4_REG (DR_REG_RTCCNTL_BASE + 0x28) - -/* RTC_CNTL_DG_WRAP_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h8 ; */ - -/* Description: */ - -#define RTC_CNTL_DG_WRAP_POWERUP_TIMER 0x0000007F -#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_M ((RTC_CNTL_DG_WRAP_POWERUP_TIMER_V)<<(RTC_CNTL_DG_WRAP_POWERUP_TIMER_S)) -#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_V 0x7F -#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_S 25 - -/* RTC_CNTL_DG_WRAP_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h20 ; */ - -/* Description: */ - -#define RTC_CNTL_DG_WRAP_WAIT_TIMER 0x000001FF -#define RTC_CNTL_DG_WRAP_WAIT_TIMER_M ((RTC_CNTL_DG_WRAP_WAIT_TIMER_V)<<(RTC_CNTL_DG_WRAP_WAIT_TIMER_S)) -#define RTC_CNTL_DG_WRAP_WAIT_TIMER_V 0x1FF -#define RTC_CNTL_DG_WRAP_WAIT_TIMER_S 16 - -/* RTC_CNTL_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */ - -/* Description: */ - -#define RTC_CNTL_POWERUP_TIMER 0x0000007F -#define RTC_CNTL_POWERUP_TIMER_M ((RTC_CNTL_POWERUP_TIMER_V)<<(RTC_CNTL_POWERUP_TIMER_S)) -#define RTC_CNTL_POWERUP_TIMER_V 0x7F -#define RTC_CNTL_POWERUP_TIMER_S 9 - -/* RTC_CNTL_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */ - -/* Description: */ - -#define RTC_CNTL_WAIT_TIMER 0x000001FF -#define RTC_CNTL_WAIT_TIMER_M ((RTC_CNTL_WAIT_TIMER_V)<<(RTC_CNTL_WAIT_TIMER_S)) -#define RTC_CNTL_WAIT_TIMER_V 0x1FF -#define RTC_CNTL_WAIT_TIMER_S 0 - -#define RTC_CNTL_TIMER5_REG (DR_REG_RTCCNTL_BASE + 0x2c) - -/* RTC_CNTL_RTCMEM_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h9 ; */ - -/* Description: */ - -#define RTC_CNTL_RTCMEM_POWERUP_TIMER 0x0000007F -#define RTC_CNTL_RTCMEM_POWERUP_TIMER_M ((RTC_CNTL_RTCMEM_POWERUP_TIMER_V)<<(RTC_CNTL_RTCMEM_POWERUP_TIMER_S)) -#define RTC_CNTL_RTCMEM_POWERUP_TIMER_V 0x7F -#define RTC_CNTL_RTCMEM_POWERUP_TIMER_S 25 - -/* RTC_CNTL_RTCMEM_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h14 ; */ - -/* Description: */ - -#define RTC_CNTL_RTCMEM_WAIT_TIMER 0x000001FF -#define RTC_CNTL_RTCMEM_WAIT_TIMER_M ((RTC_CNTL_RTCMEM_WAIT_TIMER_V)<<(RTC_CNTL_RTCMEM_WAIT_TIMER_S)) -#define RTC_CNTL_RTCMEM_WAIT_TIMER_V 0x1FF -#define RTC_CNTL_RTCMEM_WAIT_TIMER_S 16 - -/* RTC_CNTL_MIN_SLP_VAL : R/W ;bitpos:[15:8] ;default: 8'h80 ; */ - -/* description: minimal sleep cycles in slow_clk_rtc */ - -#define RTC_CNTL_MIN_SLP_VAL 0x000000ff -#define RTC_CNTL_MIN_SLP_VAL_M ((RTC_CNTL_MIN_SLP_VAL_V)<<(RTC_CNTL_MIN_SLP_VAL_S)) -#define RTC_CNTL_MIN_SLP_VAL_V 0xff -#define RTC_CNTL_MIN_SLP_VAL_S 8 -#define RTC_CNTL_MIN_SLP_VAL_MIN 2 - -/* RTC_CNTL_ULP_CP_SUBTIMER_PREDIV : R/W ;bitpos:[7:0] ;default: 8'd1 ; */ - -/* Description: */ - -#define RTC_CNTL_ULP_CP_SUBTIMER_PREDIV 0x000000FF -#define RTC_CNTL_ULP_CP_SUBTIMER_PREDIV_M ((RTC_CNTL_ULP_CP_SUBTIMER_PREDIV_V)<<(RTC_CNTL_ULP_CP_SUBTIMER_PREDIV_S)) -#define RTC_CNTL_ULP_CP_SUBTIMER_PREDIV_V 0xFF -#define RTC_CNTL_ULP_CP_SUBTIMER_PREDIV_S 0 - -#define RTC_CNTL_ANA_CONF_REG (DR_REG_RTCCNTL_BASE + 0x30) - -/* RTC_CNTL_PLL_I2C_PU : R/W ;bitpos:[31] ;default: 1'd0 ; */ - -/* Description: 1: PLL_I2C power up otherwise power down */ - -#define RTC_CNTL_PLL_I2C_PU (BIT(31)) -#define RTC_CNTL_PLL_I2C_PU_M (BIT(31)) -#define RTC_CNTL_PLL_I2C_PU_V 0x1 -#define RTC_CNTL_PLL_I2C_PU_S 31 - -/* RTC_CNTL_CKGEN_I2C_PU : R/W ;bitpos:[30] ;default: 1'd0 ; */ - -/* Description: 1: CKGEN_I2C power up otherwise power down */ - -#define RTC_CNTL_CKGEN_I2C_PU (BIT(30)) -#define RTC_CNTL_CKGEN_I2C_PU_M (BIT(30)) -#define RTC_CNTL_CKGEN_I2C_PU_V 0x1 -#define RTC_CNTL_CKGEN_I2C_PU_S 30 - -/* RTC_CNTL_RFRX_PBUS_PU : R/W ;bitpos:[28] ;default: 1'd0 ; */ - -/* Description: 1: RFRX_PBUS power up otherwise power down */ - -#define RTC_CNTL_RFRX_PBUS_PU (BIT(28)) -#define RTC_CNTL_RFRX_PBUS_PU_M (BIT(28)) -#define RTC_CNTL_RFRX_PBUS_PU_V 0x1 -#define RTC_CNTL_RFRX_PBUS_PU_S 28 - -/* RTC_CNTL_TXRF_I2C_PU : R/W ;bitpos:[27] ;default: 1'd0 ; */ - -/* Description: 1: TXRF_I2C power up otherwise power down */ - -#define RTC_CNTL_TXRF_I2C_PU (BIT(27)) -#define RTC_CNTL_TXRF_I2C_PU_M (BIT(27)) -#define RTC_CNTL_TXRF_I2C_PU_V 0x1 -#define RTC_CNTL_TXRF_I2C_PU_S 27 - -/* RTC_CNTL_PVTMON_PU : R/W ;bitpos:[26] ;default: 1'b0 ; */ - -/* Description: 1: PVTMON power up otherwise power down */ - -#define RTC_CNTL_PVTMON_PU (BIT(26)) -#define RTC_CNTL_PVTMON_PU_M (BIT(26)) -#define RTC_CNTL_PVTMON_PU_V 0x1 -#define RTC_CNTL_PVTMON_PU_S 26 - -/* RTC_CNTL_BBPLL_CAL_SLP_START : R/W ;bitpos:[25] ;default: 1'b0 ; */ - -/* Description: start BBPLL calibration during sleep */ - -#define RTC_CNTL_BBPLL_CAL_SLP_START (BIT(25)) -#define RTC_CNTL_BBPLL_CAL_SLP_START_M (BIT(25)) -#define RTC_CNTL_BBPLL_CAL_SLP_START_V 0x1 -#define RTC_CNTL_BBPLL_CAL_SLP_START_S 25 - -/* RTC_CNTL_PLLA_FORCE_PU : R/W ;bitpos:[24] ;default: 1'b0 ; */ - -/* Description: PLLA force power up */ - -#define RTC_CNTL_PLLA_FORCE_PU (BIT(24)) -#define RTC_CNTL_PLLA_FORCE_PU_M (BIT(24)) -#define RTC_CNTL_PLLA_FORCE_PU_V 0x1 -#define RTC_CNTL_PLLA_FORCE_PU_S 24 - -/* RTC_CNTL_PLLA_FORCE_PD : R/W ;bitpos:[23] ;default: 1'b1 ; */ - -/* Description: PLLA force power down */ - -#define RTC_CNTL_PLLA_FORCE_PD (BIT(23)) -#define RTC_CNTL_PLLA_FORCE_PD_M (BIT(23)) -#define RTC_CNTL_PLLA_FORCE_PD_V 0x1 -#define RTC_CNTL_PLLA_FORCE_PD_S 23 - -#define RTC_CNTL_RESET_STATE_REG (DR_REG_RTCCNTL_BASE + 0x34) - -/* RTC_CNTL_PROCPU_STAT_VECTOR_SEL : R/W ;bitpos:[13] ;default: 1'b1 ; */ - -/* Description: PRO CPU state vector sel */ - -#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL (BIT(13)) -#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_M (BIT(13)) -#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_V 0x1 -#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_S 13 - -/* RTC_CNTL_APPCPU_STAT_VECTOR_SEL : R/W ;bitpos:[12] ;default: 1'b1 ; */ - -/* Description: APP CPU state vector sel */ - -#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL (BIT(12)) -#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_M (BIT(12)) -#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_V 0x1 -#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_S 12 - -/* RTC_CNTL_RESET_CAUSE_APPCPU : RO ;bitpos:[11:6] ;default: 0 ; */ - -/* Description: reset cause of APP CPU */ - -#define RTC_CNTL_RESET_CAUSE_APPCPU 0x0000003F -#define RTC_CNTL_RESET_CAUSE_APPCPU_M ((RTC_CNTL_RESET_CAUSE_APPCPU_V)<<(RTC_CNTL_RESET_CAUSE_APPCPU_S)) -#define RTC_CNTL_RESET_CAUSE_APPCPU_V 0x3F -#define RTC_CNTL_RESET_CAUSE_APPCPU_S 6 - -/* RTC_CNTL_RESET_CAUSE_PROCPU : RO ;bitpos:[5:0] ;default: 0 ; */ - -/* Description: reset cause of PRO CPU */ - -#define RTC_CNTL_RESET_CAUSE_PROCPU 0x0000003F -#define RTC_CNTL_RESET_CAUSE_PROCPU_M ((RTC_CNTL_RESET_CAUSE_PROCPU_V)<<(RTC_CNTL_RESET_CAUSE_PROCPU_S)) -#define RTC_CNTL_RESET_CAUSE_PROCPU_V 0x3F -#define RTC_CNTL_RESET_CAUSE_PROCPU_S 0 - -#define RTC_CNTL_WAKEUP_STATE_REG (DR_REG_RTCCNTL_BASE + 0x38) - -/* RTC_CNTL_GPIO_WAKEUP_FILTER : R/W ;bitpos:[22] ;default: 1'd0 ; */ - -/* Description: enable filter for gpio wakeup event */ - -#define RTC_CNTL_GPIO_WAKEUP_FILTER (BIT(22)) -#define RTC_CNTL_GPIO_WAKEUP_FILTER_M (BIT(22)) -#define RTC_CNTL_GPIO_WAKEUP_FILTER_V 0x1 -#define RTC_CNTL_GPIO_WAKEUP_FILTER_S 22 - -/* RTC_CNTL_WAKEUP_ENA : R/W ;bitpos:[21:11] ;default: 11'b1100 ; */ - -/* Description: wakeup enable bitmap */ - -#define RTC_CNTL_WAKEUP_ENA 0x000007FF -#define RTC_CNTL_WAKEUP_ENA_M ((RTC_CNTL_WAKEUP_ENA_V)<<(RTC_CNTL_WAKEUP_ENA_S)) -#define RTC_CNTL_WAKEUP_ENA_V 0x7FF -#define RTC_CNTL_WAKEUP_ENA_S 11 - -/* RTC_CNTL_WAKEUP_CAUSE : RO ;bitpos:[10:0] ;default: 11'h0 ; */ - -/* Description: wakeup cause */ - -#define RTC_CNTL_WAKEUP_CAUSE 0x000007FF -#define RTC_CNTL_WAKEUP_CAUSE_M ((RTC_CNTL_WAKEUP_CAUSE_V)<<(RTC_CNTL_WAKEUP_CAUSE_S)) -#define RTC_CNTL_WAKEUP_CAUSE_V 0x7FF -#define RTC_CNTL_WAKEUP_CAUSE_S 0 - -#define RTC_CNTL_INT_ENA_REG (DR_REG_RTCCNTL_BASE + 0x3c) - -/* RTC_CNTL_MAIN_TIMER_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ - -/* Description: enable RTC main timer interrupt */ - -#define RTC_CNTL_MAIN_TIMER_INT_ENA (BIT(8)) -#define RTC_CNTL_MAIN_TIMER_INT_ENA_M (BIT(8)) -#define RTC_CNTL_MAIN_TIMER_INT_ENA_V 0x1 -#define RTC_CNTL_MAIN_TIMER_INT_ENA_S 8 - -/* RTC_CNTL_BROWN_OUT_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ - -/* Description: enable brown out interrupt */ - -#define RTC_CNTL_BROWN_OUT_INT_ENA (BIT(7)) -#define RTC_CNTL_BROWN_OUT_INT_ENA_M (BIT(7)) -#define RTC_CNTL_BROWN_OUT_INT_ENA_V 0x1 -#define RTC_CNTL_BROWN_OUT_INT_ENA_S 7 - -/* RTC_CNTL_TOUCH_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ - -/* Description: enable touch interrupt */ - -#define RTC_CNTL_TOUCH_INT_ENA (BIT(6)) -#define RTC_CNTL_TOUCH_INT_ENA_M (BIT(6)) -#define RTC_CNTL_TOUCH_INT_ENA_V 0x1 -#define RTC_CNTL_TOUCH_INT_ENA_S 6 - -/* RTC_CNTL_ULP_CP_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ - -/* Description: enable ULP-coprocessor interrupt */ - -#define RTC_CNTL_ULP_CP_INT_ENA (BIT(5)) -#define RTC_CNTL_ULP_CP_INT_ENA_M (BIT(5)) -#define RTC_CNTL_ULP_CP_INT_ENA_V 0x1 -#define RTC_CNTL_ULP_CP_INT_ENA_S 5 - -/* RTC_CNTL_TIME_VALID_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ - -/* Description: enable RTC time valid interrupt */ - -#define RTC_CNTL_TIME_VALID_INT_ENA (BIT(4)) -#define RTC_CNTL_TIME_VALID_INT_ENA_M (BIT(4)) -#define RTC_CNTL_TIME_VALID_INT_ENA_V 0x1 -#define RTC_CNTL_TIME_VALID_INT_ENA_S 4 - -/* RTC_CNTL_WDT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ - -/* Description: enable RTC WDT interrupt */ - -#define RTC_CNTL_WDT_INT_ENA (BIT(3)) -#define RTC_CNTL_WDT_INT_ENA_M (BIT(3)) -#define RTC_CNTL_WDT_INT_ENA_V 0x1 -#define RTC_CNTL_WDT_INT_ENA_S 3 - -/* RTC_CNTL_SDIO_IDLE_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ - -/* Description: enable SDIO idle interrupt */ - -#define RTC_CNTL_SDIO_IDLE_INT_ENA (BIT(2)) -#define RTC_CNTL_SDIO_IDLE_INT_ENA_M (BIT(2)) -#define RTC_CNTL_SDIO_IDLE_INT_ENA_V 0x1 -#define RTC_CNTL_SDIO_IDLE_INT_ENA_S 2 - -/* RTC_CNTL_SLP_REJECT_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ - -/* Description: enable sleep reject interrupt */ - -#define RTC_CNTL_SLP_REJECT_INT_ENA (BIT(1)) -#define RTC_CNTL_SLP_REJECT_INT_ENA_M (BIT(1)) -#define RTC_CNTL_SLP_REJECT_INT_ENA_V 0x1 -#define RTC_CNTL_SLP_REJECT_INT_ENA_S 1 - -/* RTC_CNTL_SLP_WAKEUP_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ - -/* Description: enable sleep wakeup interrupt */ - -#define RTC_CNTL_SLP_WAKEUP_INT_ENA (BIT(0)) -#define RTC_CNTL_SLP_WAKEUP_INT_ENA_M (BIT(0)) -#define RTC_CNTL_SLP_WAKEUP_INT_ENA_V 0x1 -#define RTC_CNTL_SLP_WAKEUP_INT_ENA_S 0 - -#define RTC_CNTL_INT_RAW_REG (DR_REG_RTCCNTL_BASE + 0x40) - -/* RTC_CNTL_MAIN_TIMER_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ - -/* Description: RTC main timer interrupt raw */ - -#define RTC_CNTL_MAIN_TIMER_INT_RAW (BIT(8)) -#define RTC_CNTL_MAIN_TIMER_INT_RAW_M (BIT(8)) -#define RTC_CNTL_MAIN_TIMER_INT_RAW_V 0x1 -#define RTC_CNTL_MAIN_TIMER_INT_RAW_S 8 - -/* RTC_CNTL_BROWN_OUT_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ - -/* Description: brown out interrupt raw */ - -#define RTC_CNTL_BROWN_OUT_INT_RAW (BIT(7)) -#define RTC_CNTL_BROWN_OUT_INT_RAW_M (BIT(7)) -#define RTC_CNTL_BROWN_OUT_INT_RAW_V 0x1 -#define RTC_CNTL_BROWN_OUT_INT_RAW_S 7 - -/* RTC_CNTL_TOUCH_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ - -/* Description: touch interrupt raw */ - -#define RTC_CNTL_TOUCH_INT_RAW (BIT(6)) -#define RTC_CNTL_TOUCH_INT_RAW_M (BIT(6)) -#define RTC_CNTL_TOUCH_INT_RAW_V 0x1 -#define RTC_CNTL_TOUCH_INT_RAW_S 6 - -/* RTC_CNTL_ULP_CP_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ - -/* Description: ULP-coprocessor interrupt raw */ - -#define RTC_CNTL_ULP_CP_INT_RAW (BIT(5)) -#define RTC_CNTL_ULP_CP_INT_RAW_M (BIT(5)) -#define RTC_CNTL_ULP_CP_INT_RAW_V 0x1 -#define RTC_CNTL_ULP_CP_INT_RAW_S 5 - -/* RTC_CNTL_TIME_VALID_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ - -/* Description: RTC time valid interrupt raw */ - -#define RTC_CNTL_TIME_VALID_INT_RAW (BIT(4)) -#define RTC_CNTL_TIME_VALID_INT_RAW_M (BIT(4)) -#define RTC_CNTL_TIME_VALID_INT_RAW_V 0x1 -#define RTC_CNTL_TIME_VALID_INT_RAW_S 4 - -/* RTC_CNTL_WDT_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ - -/* Description: RTC WDT interrupt raw */ - -#define RTC_CNTL_WDT_INT_RAW (BIT(3)) -#define RTC_CNTL_WDT_INT_RAW_M (BIT(3)) -#define RTC_CNTL_WDT_INT_RAW_V 0x1 -#define RTC_CNTL_WDT_INT_RAW_S 3 - -/* RTC_CNTL_SDIO_IDLE_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ - -/* Description: SDIO idle interrupt raw */ - -#define RTC_CNTL_SDIO_IDLE_INT_RAW (BIT(2)) -#define RTC_CNTL_SDIO_IDLE_INT_RAW_M (BIT(2)) -#define RTC_CNTL_SDIO_IDLE_INT_RAW_V 0x1 -#define RTC_CNTL_SDIO_IDLE_INT_RAW_S 2 - -/* RTC_CNTL_SLP_REJECT_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ - -/* Description: sleep reject interrupt raw */ - -#define RTC_CNTL_SLP_REJECT_INT_RAW (BIT(1)) -#define RTC_CNTL_SLP_REJECT_INT_RAW_M (BIT(1)) -#define RTC_CNTL_SLP_REJECT_INT_RAW_V 0x1 -#define RTC_CNTL_SLP_REJECT_INT_RAW_S 1 - -/* RTC_CNTL_SLP_WAKEUP_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ - -/* Description: sleep wakeup interrupt raw */ - -#define RTC_CNTL_SLP_WAKEUP_INT_RAW (BIT(0)) -#define RTC_CNTL_SLP_WAKEUP_INT_RAW_M (BIT(0)) -#define RTC_CNTL_SLP_WAKEUP_INT_RAW_V 0x1 -#define RTC_CNTL_SLP_WAKEUP_INT_RAW_S 0 - -#define RTC_CNTL_INT_ST_REG (DR_REG_RTCCNTL_BASE + 0x44) - -/* RTC_CNTL_MAIN_TIMER_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ - -/* Description: RTC main timer interrupt state */ - -#define RTC_CNTL_MAIN_TIMER_INT_ST (BIT(8)) -#define RTC_CNTL_MAIN_TIMER_INT_ST_M (BIT(8)) -#define RTC_CNTL_MAIN_TIMER_INT_ST_V 0x1 -#define RTC_CNTL_MAIN_TIMER_INT_ST_S 8 - -/* RTC_CNTL_BROWN_OUT_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ - -/* Description: brown out interrupt state */ - -#define RTC_CNTL_BROWN_OUT_INT_ST (BIT(7)) -#define RTC_CNTL_BROWN_OUT_INT_ST_M (BIT(7)) -#define RTC_CNTL_BROWN_OUT_INT_ST_V 0x1 -#define RTC_CNTL_BROWN_OUT_INT_ST_S 7 - -/* RTC_CNTL_TOUCH_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ - -/* Description: touch interrupt state */ - -#define RTC_CNTL_TOUCH_INT_ST (BIT(6)) -#define RTC_CNTL_TOUCH_INT_ST_M (BIT(6)) -#define RTC_CNTL_TOUCH_INT_ST_V 0x1 -#define RTC_CNTL_TOUCH_INT_ST_S 6 - -/* RTC_CNTL_SAR_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ - -/* Description: ULP-coprocessor interrupt state */ - -#define RTC_CNTL_SAR_INT_ST (BIT(5)) -#define RTC_CNTL_SAR_INT_ST_M (BIT(5)) -#define RTC_CNTL_SAR_INT_ST_V 0x1 -#define RTC_CNTL_SAR_INT_ST_S 5 - -/* RTC_CNTL_TIME_VALID_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ - -/* Description: RTC time valid interrupt state */ - -#define RTC_CNTL_TIME_VALID_INT_ST (BIT(4)) -#define RTC_CNTL_TIME_VALID_INT_ST_M (BIT(4)) -#define RTC_CNTL_TIME_VALID_INT_ST_V 0x1 -#define RTC_CNTL_TIME_VALID_INT_ST_S 4 - -/* RTC_CNTL_WDT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ - -/* Description: RTC WDT interrupt state */ - -#define RTC_CNTL_WDT_INT_ST (BIT(3)) -#define RTC_CNTL_WDT_INT_ST_M (BIT(3)) -#define RTC_CNTL_WDT_INT_ST_V 0x1 -#define RTC_CNTL_WDT_INT_ST_S 3 - -/* RTC_CNTL_SDIO_IDLE_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ - -/* Description: SDIO idle interrupt state */ - -#define RTC_CNTL_SDIO_IDLE_INT_ST (BIT(2)) -#define RTC_CNTL_SDIO_IDLE_INT_ST_M (BIT(2)) -#define RTC_CNTL_SDIO_IDLE_INT_ST_V 0x1 -#define RTC_CNTL_SDIO_IDLE_INT_ST_S 2 - -/* RTC_CNTL_SLP_REJECT_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ - -/* Description: sleep reject interrupt state */ - -#define RTC_CNTL_SLP_REJECT_INT_ST (BIT(1)) -#define RTC_CNTL_SLP_REJECT_INT_ST_M (BIT(1)) -#define RTC_CNTL_SLP_REJECT_INT_ST_V 0x1 -#define RTC_CNTL_SLP_REJECT_INT_ST_S 1 - -/* RTC_CNTL_SLP_WAKEUP_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ - -/* Description: sleep wakeup interrupt state */ - -#define RTC_CNTL_SLP_WAKEUP_INT_ST (BIT(0)) -#define RTC_CNTL_SLP_WAKEUP_INT_ST_M (BIT(0)) -#define RTC_CNTL_SLP_WAKEUP_INT_ST_V 0x1 -#define RTC_CNTL_SLP_WAKEUP_INT_ST_S 0 - -#define RTC_CNTL_INT_CLR_REG (DR_REG_RTCCNTL_BASE + 0x48) - -/* RTC_CNTL_MAIN_TIMER_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ - -/* Description: Clear RTC main timer interrupt state */ - -#define RTC_CNTL_MAIN_TIMER_INT_CLR (BIT(8)) -#define RTC_CNTL_MAIN_TIMER_INT_CLR_M (BIT(8)) -#define RTC_CNTL_MAIN_TIMER_INT_CLR_V 0x1 -#define RTC_CNTL_MAIN_TIMER_INT_CLR_S 8 - -/* RTC_CNTL_BROWN_OUT_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ - -/* Description: Clear brown out interrupt state */ - -#define RTC_CNTL_BROWN_OUT_INT_CLR (BIT(7)) -#define RTC_CNTL_BROWN_OUT_INT_CLR_M (BIT(7)) -#define RTC_CNTL_BROWN_OUT_INT_CLR_V 0x1 -#define RTC_CNTL_BROWN_OUT_INT_CLR_S 7 - -/* RTC_CNTL_TOUCH_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ - -/* Description: Clear touch interrupt state */ - -#define RTC_CNTL_TOUCH_INT_CLR (BIT(6)) -#define RTC_CNTL_TOUCH_INT_CLR_M (BIT(6)) -#define RTC_CNTL_TOUCH_INT_CLR_V 0x1 -#define RTC_CNTL_TOUCH_INT_CLR_S 6 - -/* RTC_CNTL_SAR_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ - -/* Description: Clear ULP-coprocessor interrupt state */ - -#define RTC_CNTL_SAR_INT_CLR (BIT(5)) -#define RTC_CNTL_SAR_INT_CLR_M (BIT(5)) -#define RTC_CNTL_SAR_INT_CLR_V 0x1 -#define RTC_CNTL_SAR_INT_CLR_S 5 - -/* RTC_CNTL_TIME_VALID_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ - -/* Description: Clear RTC time valid interrupt state */ - -#define RTC_CNTL_TIME_VALID_INT_CLR (BIT(4)) -#define RTC_CNTL_TIME_VALID_INT_CLR_M (BIT(4)) -#define RTC_CNTL_TIME_VALID_INT_CLR_V 0x1 -#define RTC_CNTL_TIME_VALID_INT_CLR_S 4 - -/* RTC_CNTL_WDT_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ - -/* Description: Clear RTC WDT interrupt state */ - -#define RTC_CNTL_WDT_INT_CLR (BIT(3)) -#define RTC_CNTL_WDT_INT_CLR_M (BIT(3)) -#define RTC_CNTL_WDT_INT_CLR_V 0x1 -#define RTC_CNTL_WDT_INT_CLR_S 3 - -/* RTC_CNTL_SDIO_IDLE_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ - -/* Description: Clear SDIO idle interrupt state */ - -#define RTC_CNTL_SDIO_IDLE_INT_CLR (BIT(2)) -#define RTC_CNTL_SDIO_IDLE_INT_CLR_M (BIT(2)) -#define RTC_CNTL_SDIO_IDLE_INT_CLR_V 0x1 -#define RTC_CNTL_SDIO_IDLE_INT_CLR_S 2 - -/* RTC_CNTL_SLP_REJECT_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ - -/* Description: Clear sleep reject interrupt state */ - -#define RTC_CNTL_SLP_REJECT_INT_CLR (BIT(1)) -#define RTC_CNTL_SLP_REJECT_INT_CLR_M (BIT(1)) -#define RTC_CNTL_SLP_REJECT_INT_CLR_V 0x1 -#define RTC_CNTL_SLP_REJECT_INT_CLR_S 1 - -/* RTC_CNTL_SLP_WAKEUP_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ - -/* Description: Clear sleep wakeup interrupt state */ - -#define RTC_CNTL_SLP_WAKEUP_INT_CLR (BIT(0)) -#define RTC_CNTL_SLP_WAKEUP_INT_CLR_M (BIT(0)) -#define RTC_CNTL_SLP_WAKEUP_INT_CLR_V 0x1 -#define RTC_CNTL_SLP_WAKEUP_INT_CLR_S 0 - -#define RTC_CNTL_STORE0_REG (DR_REG_RTCCNTL_BASE + 0x4c) - -/* RTC_CNTL_SCRATCH0 : R/W ;bitpos:[31:0] ;default: 0 ; */ - -/* Description: 32-bit general purpose retention register */ - -#define RTC_CNTL_SCRATCH0 0xFFFFFFFF -#define RTC_CNTL_SCRATCH0_M ((RTC_CNTL_SCRATCH0_V)<<(RTC_CNTL_SCRATCH0_S)) -#define RTC_CNTL_SCRATCH0_V 0xFFFFFFFF -#define RTC_CNTL_SCRATCH0_S 0 - -#define RTC_CNTL_STORE1_REG (DR_REG_RTCCNTL_BASE + 0x50) - -#define RTC_SLOW_CLK_CAL_REG RTC_CNTL_STORE1_REG - -/* RTC_CNTL_SCRATCH1 : R/W ;bitpos:[31:0] ;default: 0 ; */ - -/* Description: 32-bit general purpose retention register */ - -#define RTC_CNTL_SCRATCH1 0xFFFFFFFF -#define RTC_CNTL_SCRATCH1_M ((RTC_CNTL_SCRATCH1_V)<<(RTC_CNTL_SCRATCH1_S)) -#define RTC_CNTL_SCRATCH1_V 0xFFFFFFFF -#define RTC_CNTL_SCRATCH1_S 0 - -#define RTC_CNTL_STORE2_REG (DR_REG_RTCCNTL_BASE + 0x54) - -/* RTC_CNTL_SCRATCH2 : R/W ;bitpos:[31:0] ;default: 0 ; */ - -/* Description: 32-bit general purpose retention register */ - -#define RTC_CNTL_SCRATCH2 0xFFFFFFFF -#define RTC_CNTL_SCRATCH2_M ((RTC_CNTL_SCRATCH2_V)<<(RTC_CNTL_SCRATCH2_S)) -#define RTC_CNTL_SCRATCH2_V 0xFFFFFFFF -#define RTC_CNTL_SCRATCH2_S 0 - -#define RTC_CNTL_STORE3_REG (DR_REG_RTCCNTL_BASE + 0x58) - -/* RTC_CNTL_SCRATCH3 : R/W ;bitpos:[31:0] ;default: 0 ; */ - -/* Description: 32-bit general purpose retention register */ - -#define RTC_CNTL_SCRATCH3 0xFFFFFFFF -#define RTC_CNTL_SCRATCH3_M ((RTC_CNTL_SCRATCH3_V)<<(RTC_CNTL_SCRATCH3_S)) -#define RTC_CNTL_SCRATCH3_V 0xFFFFFFFF -#define RTC_CNTL_SCRATCH3_S 0 - -#define RTC_CNTL_EXT_XTL_CONF_REG (DR_REG_RTCCNTL_BASE + 0x5c) - -/* RTC_CNTL_XTL_EXT_CTR_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ - -/* Description: enable control XTAL by external pads */ - -#define RTC_CNTL_XTL_EXT_CTR_EN (BIT(31)) -#define RTC_CNTL_XTL_EXT_CTR_EN_M (BIT(31)) -#define RTC_CNTL_XTL_EXT_CTR_EN_V 0x1 -#define RTC_CNTL_XTL_EXT_CTR_EN_S 31 - -/* RTC_CNTL_XTL_EXT_CTR_LV : R/W ;bitpos:[30] ;default: 1'b0 ; */ - -/* Description: - * 0: power down XTAL at high level - * 1: power down XTAL at low level - */ - -#define RTC_CNTL_XTL_EXT_CTR_LV (BIT(30)) -#define RTC_CNTL_XTL_EXT_CTR_LV_M (BIT(30)) -#define RTC_CNTL_XTL_EXT_CTR_LV_V 0x1 -#define RTC_CNTL_XTL_EXT_CTR_LV_S 30 - -#define RTC_CNTL_EXT_WAKEUP_CONF_REG (DR_REG_RTCCNTL_BASE + 0x60) - -/* RTC_CNTL_EXT_WAKEUP1_LV : R/W ;bitpos:[31] ;default: 1'b0 ; */ - -/* Description: - * 0: external wakeup at low level - * 1: external wakeup at high level - */ - -#define RTC_CNTL_EXT_WAKEUP1_LV (BIT(31)) -#define RTC_CNTL_EXT_WAKEUP1_LV_M (BIT(31)) -#define RTC_CNTL_EXT_WAKEUP1_LV_V 0x1 -#define RTC_CNTL_EXT_WAKEUP1_LV_S 31 - -/* RTC_CNTL_EXT_WAKEUP0_LV : R/W ;bitpos:[30] ;default: 1'b0 ; */ - -/* Description: - * 0: external wakeup at low level - * 1: external wakeup at high level - */ - -#define RTC_CNTL_EXT_WAKEUP0_LV (BIT(30)) -#define RTC_CNTL_EXT_WAKEUP0_LV_M (BIT(30)) -#define RTC_CNTL_EXT_WAKEUP0_LV_V 0x1 -#define RTC_CNTL_EXT_WAKEUP0_LV_S 30 - -#define RTC_CNTL_SLP_REJECT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x64) - -/* RTC_CNTL_REJECT_CAUSE : RO ;bitpos:[31:28] ;default: 4'b0 ; */ - -/* Description: sleep reject cause */ - -#define RTC_CNTL_REJECT_CAUSE 0x0000000F -#define RTC_CNTL_REJECT_CAUSE_M ((RTC_CNTL_REJECT_CAUSE_V)<<(RTC_CNTL_REJECT_CAUSE_S)) -#define RTC_CNTL_REJECT_CAUSE_V 0xF -#define RTC_CNTL_REJECT_CAUSE_S 28 - -/* RTC_CNTL_DEEP_SLP_REJECT_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */ - -/* Description: enable reject for deep sleep */ - -#define RTC_CNTL_DEEP_SLP_REJECT_EN (BIT(27)) -#define RTC_CNTL_DEEP_SLP_REJECT_EN_M (BIT(27)) -#define RTC_CNTL_DEEP_SLP_REJECT_EN_V 0x1 -#define RTC_CNTL_DEEP_SLP_REJECT_EN_S 27 - -/* RTC_CNTL_LIGHT_SLP_REJECT_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */ - -/* Description: enable reject for light sleep */ - -#define RTC_CNTL_LIGHT_SLP_REJECT_EN (BIT(26)) -#define RTC_CNTL_LIGHT_SLP_REJECT_EN_M (BIT(26)) -#define RTC_CNTL_LIGHT_SLP_REJECT_EN_V 0x1 -#define RTC_CNTL_LIGHT_SLP_REJECT_EN_S 26 - -/* RTC_CNTL_SDIO_REJECT_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */ - -/* Description: enable SDIO reject */ - -#define RTC_CNTL_SDIO_REJECT_EN (BIT(25)) -#define RTC_CNTL_SDIO_REJECT_EN_M (BIT(25)) -#define RTC_CNTL_SDIO_REJECT_EN_V 0x1 -#define RTC_CNTL_SDIO_REJECT_EN_S 25 - -/* RTC_CNTL_GPIO_REJECT_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ - -/* Description: enable GPIO reject */ - -#define RTC_CNTL_GPIO_REJECT_EN (BIT(24)) -#define RTC_CNTL_GPIO_REJECT_EN_M (BIT(24)) -#define RTC_CNTL_GPIO_REJECT_EN_V 0x1 -#define RTC_CNTL_GPIO_REJECT_EN_S 24 - -#define RTC_CNTL_CPU_PERIOD_CONF_REG (DR_REG_RTCCNTL_BASE + 0x68) - -/* RTC_CNTL_CPUPERIOD_SEL : R/W ;bitpos:[31:30] ;default: 2'b00 ; */ - -/* Description: CPU period sel */ - -#define RTC_CNTL_CPUPERIOD_SEL 0x00000003 -#define RTC_CNTL_CPUPERIOD_SEL_M ((RTC_CNTL_CPUPERIOD_SEL_V)<<(RTC_CNTL_CPUPERIOD_SEL_S)) -#define RTC_CNTL_CPUPERIOD_SEL_V 0x3 -#define RTC_CNTL_CPUPERIOD_SEL_S 30 - -/* RTC_CNTL_CPUSEL_CONF : R/W ;bitpos:[29] ;default: 1'b0 ; */ - -/* Description: CPU sel option */ - -#define RTC_CNTL_CPUSEL_CONF (BIT(29)) -#define RTC_CNTL_CPUSEL_CONF_M (BIT(29)) -#define RTC_CNTL_CPUSEL_CONF_V 0x1 -#define RTC_CNTL_CPUSEL_CONF_S 29 - -#define RTC_CNTL_SDIO_ACT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x6c) - -/* RTC_CNTL_SDIO_ACT_DNUM : R/W ;bitpos:[31:22] ;default: 10'b0 ; */ - -/* Description: */ - -#define RTC_CNTL_SDIO_ACT_DNUM 0x000003FF -#define RTC_CNTL_SDIO_ACT_DNUM_M ((RTC_CNTL_SDIO_ACT_DNUM_V)<<(RTC_CNTL_SDIO_ACT_DNUM_S)) -#define RTC_CNTL_SDIO_ACT_DNUM_V 0x3FF -#define RTC_CNTL_SDIO_ACT_DNUM_S 22 - -#define RTC_CNTL_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x70) - -/* RTC_CNTL_ANA_CLK_RTC_SEL : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ - -/* Description: slow_clk_rtc sel. - * 0: SLOW_CK - * 1: CK_XTAL_32K - * 2: CK8M_D256_OUT - */ - -#define RTC_CNTL_ANA_CLK_RTC_SEL 0x00000003 -#define RTC_CNTL_ANA_CLK_RTC_SEL_M ((RTC_CNTL_ANA_CLK_RTC_SEL_V)<<(RTC_CNTL_ANA_CLK_RTC_SEL_S)) -#define RTC_CNTL_ANA_CLK_RTC_SEL_V 0x3 -#define RTC_CNTL_ANA_CLK_RTC_SEL_S 30 - -/* RTC_CNTL_FAST_CLK_RTC_SEL : R/W ;bitpos:[29] ;default: 1'b0 ; */ - -/* Description: fast_clk_rtc sel. 0: XTAL div 4 1: CK8M */ - -#define RTC_CNTL_FAST_CLK_RTC_SEL (BIT(29)) -#define RTC_CNTL_FAST_CLK_RTC_SEL_M (BIT(29)) -#define RTC_CNTL_FAST_CLK_RTC_SEL_V 0x1 -#define RTC_CNTL_FAST_CLK_RTC_SEL_S 29 - -/* RTC_CNTL_CK8M_FORCE_PU : R/W ;bitpos:[26] ;default: 1'd0 ; */ - -/* Description: CK8M force power up */ - -#define RTC_CNTL_CK8M_FORCE_PU (BIT(26)) -#define RTC_CNTL_CK8M_FORCE_PU_M (BIT(26)) -#define RTC_CNTL_CK8M_FORCE_PU_V 0x1 -#define RTC_CNTL_CK8M_FORCE_PU_S 26 - -/* RTC_CNTL_CK8M_FORCE_PD : R/W ;bitpos:[25] ;default: 1'd0 ; */ - -/* Description: CK8M force power down */ - -#define RTC_CNTL_CK8M_FORCE_PD (BIT(25)) -#define RTC_CNTL_CK8M_FORCE_PD_M (BIT(25)) -#define RTC_CNTL_CK8M_FORCE_PD_V 0x1 -#define RTC_CNTL_CK8M_FORCE_PD_S 25 - -/* RTC_CNTL_CK8M_DFREQ : R/W ;bitpos:[24:17] ;default: 8'd0 ; */ - -/* Description: CK8M_DFREQ */ - -#define RTC_CNTL_CK8M_DFREQ 0x000000FF -#define RTC_CNTL_CK8M_DFREQ_M ((RTC_CNTL_CK8M_DFREQ_V)<<(RTC_CNTL_CK8M_DFREQ_S)) -#define RTC_CNTL_CK8M_DFREQ_V 0xFF -#define RTC_CNTL_CK8M_DFREQ_S 17 - -/* RTC_CNTL_CK8M_FORCE_NOGATING : R/W ;bitpos:[16] ;default: 1'd0 ; */ - -/* Description: CK8M force no gating during sleep */ - -#define RTC_CNTL_CK8M_FORCE_NOGATING (BIT(16)) -#define RTC_CNTL_CK8M_FORCE_NOGATING_M (BIT(16)) -#define RTC_CNTL_CK8M_FORCE_NOGATING_V 0x1 -#define RTC_CNTL_CK8M_FORCE_NOGATING_S 16 - -/* RTC_CNTL_XTAL_FORCE_NOGATING : R/W ;bitpos:[15] ;default: 1'd0 ; */ - -/* Description: XTAL force no gating during sleep */ - -#define RTC_CNTL_XTAL_FORCE_NOGATING (BIT(15)) -#define RTC_CNTL_XTAL_FORCE_NOGATING_M (BIT(15)) -#define RTC_CNTL_XTAL_FORCE_NOGATING_V 0x1 -#define RTC_CNTL_XTAL_FORCE_NOGATING_S 15 - -/* RTC_CNTL_CK8M_DIV_SEL : R/W ;bitpos:[14:12] ;default: 3'd2 ; */ - -/* Description: divider = reg_ck8m_div_sel + 1 */ - -#define RTC_CNTL_CK8M_DIV_SEL 0x00000007 -#define RTC_CNTL_CK8M_DIV_SEL_M ((RTC_CNTL_CK8M_DIV_SEL_V)<<(RTC_CNTL_CK8M_DIV_SEL_S)) -#define RTC_CNTL_CK8M_DIV_SEL_V 0x7 -#define RTC_CNTL_CK8M_DIV_SEL_S 12 - -/* RTC_CNTL_CK8M_DFREQ_FORCE : R/W ;bitpos:[11] ;default: 1'd0 ; */ - -/* Description: */ - -#define RTC_CNTL_CK8M_DFREQ_FORCE (BIT(11)) -#define RTC_CNTL_CK8M_DFREQ_FORCE_M (BIT(11)) -#define RTC_CNTL_CK8M_DFREQ_FORCE_V 0x1 -#define RTC_CNTL_CK8M_DFREQ_FORCE_S 11 - -/* RTC_CNTL_DIG_CLK8M_EN : R/W ;bitpos:[10] ;default: 1'd0 ; */ - -/* Description: - * enable CK8M for digital core (no relationship with RTC core) - */ - -#define RTC_CNTL_DIG_CLK8M_EN (BIT(10)) -#define RTC_CNTL_DIG_CLK8M_EN_M (BIT(10)) -#define RTC_CNTL_DIG_CLK8M_EN_V 0x1 -#define RTC_CNTL_DIG_CLK8M_EN_S 10 - -/* RTC_CNTL_DIG_CLK8M_D256_EN : R/W ;bitpos:[9] ;default: 1'd1 ; */ - -/* Description: - * enable CK8M_D256_OUT for digital core (no relationship with RTC core) - */ - -#define RTC_CNTL_DIG_CLK8M_D256_EN (BIT(9)) -#define RTC_CNTL_DIG_CLK8M_D256_EN_M (BIT(9)) -#define RTC_CNTL_DIG_CLK8M_D256_EN_V 0x1 -#define RTC_CNTL_DIG_CLK8M_D256_EN_S 9 - -/* RTC_CNTL_DIG_XTAL32K_EN : R/W ;bitpos:[8] ;default: 1'd0 ; */ - -/* Description: - * enable CK_XTAL_32K for digital core (no relationship with RTC core) - */ - -#define RTC_CNTL_DIG_XTAL32K_EN (BIT(8)) -#define RTC_CNTL_DIG_XTAL32K_EN_M (BIT(8)) -#define RTC_CNTL_DIG_XTAL32K_EN_V 0x1 -#define RTC_CNTL_DIG_XTAL32K_EN_S 8 - -/* RTC_CNTL_ENB_CK8M_DIV : R/W ;bitpos:[7] ;default: 1'd0 ; */ - -/* Description: - * 1: CK8M_D256_OUT is actually CK8M - * 0: CK8M_D256_OUT is CK8M divided by 256 - */ - -#define RTC_CNTL_ENB_CK8M_DIV (BIT(7)) -#define RTC_CNTL_ENB_CK8M_DIV_M (BIT(7)) -#define RTC_CNTL_ENB_CK8M_DIV_V 0x1 -#define RTC_CNTL_ENB_CK8M_DIV_S 7 - -/* RTC_CNTL_ENB_CK8M : R/W ;bitpos:[6] ;default: 1'd0 ; */ - -/* Description: disable CK8M and CK8M_D256_OUT */ - -#define RTC_CNTL_ENB_CK8M (BIT(6)) -#define RTC_CNTL_ENB_CK8M_M (BIT(6)) -#define RTC_CNTL_ENB_CK8M_V 0x1 -#define RTC_CNTL_ENB_CK8M_S 6 - -/* RTC_CNTL_CK8M_DIV : R/W ;bitpos:[5:4] ;default: 2'b01 ; */ - -/* Description: CK8M_D256_OUT divider. - * 00: div128 - * 01: div256 - * 10: div512 - * 11: div1024 - */ - -#define RTC_CNTL_CK8M_DIV 0x00000003 -#define RTC_CNTL_CK8M_DIV_M ((RTC_CNTL_CK8M_DIV_V)<<(RTC_CNTL_CK8M_DIV_S)) -#define RTC_CNTL_CK8M_DIV_V 0x3 -#define RTC_CNTL_CK8M_DIV_S 4 - -#define RTC_CNTL_SDIO_CONF_REG (DR_REG_RTCCNTL_BASE + 0x74) - -/* RTC_CNTL_XPD_SDIO_REG : R/W ;bitpos:[31] ;default: 1'd0 ; */ - -/* Description: SW option for XPD_SDIO_REG. - * Only active when reg_sdio_force = 1 - */ - -#define RTC_CNTL_XPD_SDIO_REG (BIT(31)) -#define RTC_CNTL_XPD_SDIO_REG_M (BIT(31)) -#define RTC_CNTL_XPD_SDIO_REG_V 0x1 -#define RTC_CNTL_XPD_SDIO_REG_S 31 - -/* RTC_CNTL_DREFH_SDIO : R/W ;bitpos:[30:29] ;default: 2'b00 ; */ - -/* Description: SW option for DREFH_SDIO. - * Only active when reg_sdio_force = 1 - */ - -#define RTC_CNTL_DREFH_SDIO 0x00000003 -#define RTC_CNTL_DREFH_SDIO_M ((RTC_CNTL_DREFH_SDIO_V)<<(RTC_CNTL_DREFH_SDIO_S)) -#define RTC_CNTL_DREFH_SDIO_V 0x3 -#define RTC_CNTL_DREFH_SDIO_S 29 - -/* RTC_CNTL_DREFM_SDIO : R/W ;bitpos:[28:27] ;default: 2'b00 ; */ - -/* Description: SW option for DREFM_SDIO. - * Only active when reg_sdio_force = 1 - */ - -#define RTC_CNTL_DREFM_SDIO 0x00000003 -#define RTC_CNTL_DREFM_SDIO_M ((RTC_CNTL_DREFM_SDIO_V)<<(RTC_CNTL_DREFM_SDIO_S)) -#define RTC_CNTL_DREFM_SDIO_V 0x3 -#define RTC_CNTL_DREFM_SDIO_S 27 - -/* RTC_CNTL_DREFL_SDIO : R/W ;bitpos:[26:25] ;default: 2'b01 ; */ - -/* Description: SW option for DREFL_SDIO. - * Only active when reg_sdio_force = 1 - */ - -#define RTC_CNTL_DREFL_SDIO 0x00000003 -#define RTC_CNTL_DREFL_SDIO_M ((RTC_CNTL_DREFL_SDIO_V)<<(RTC_CNTL_DREFL_SDIO_S)) -#define RTC_CNTL_DREFL_SDIO_V 0x3 -#define RTC_CNTL_DREFL_SDIO_S 25 - -/* RTC_CNTL_REG1P8_READY : RO ;bitpos:[24] ;default: 1'd0 ; */ - -/* Description: read only register for REG1P8_READY */ - -#define RTC_CNTL_REG1P8_READY (BIT(24)) -#define RTC_CNTL_REG1P8_READY_M (BIT(24)) -#define RTC_CNTL_REG1P8_READY_V 0x1 -#define RTC_CNTL_REG1P8_READY_S 24 - -/* RTC_CNTL_SDIO_TIEH : R/W ;bitpos:[23] ;default: 1'd1 ; */ - -/* Description: SW option for SDIO_TIEH. - * Only active when reg_sdio_force = 1 - */ - -#define RTC_CNTL_SDIO_TIEH (BIT(23)) -#define RTC_CNTL_SDIO_TIEH_M (BIT(23)) -#define RTC_CNTL_SDIO_TIEH_V 0x1 -#define RTC_CNTL_SDIO_TIEH_S 23 - -/* RTC_CNTL_SDIO_FORCE : R/W ;bitpos:[22] ;default: 1'd0 ; */ - -/* Description: 1: use SW option to control SDIO_REG 0: use state machine */ - -#define RTC_CNTL_SDIO_FORCE (BIT(22)) -#define RTC_CNTL_SDIO_FORCE_M (BIT(22)) -#define RTC_CNTL_SDIO_FORCE_V 0x1 -#define RTC_CNTL_SDIO_FORCE_S 22 - -/* RTC_CNTL_SDIO_PD_EN : R/W ;bitpos:[21] ;default: 1'd1 ; */ - -/* Description: power down SDIO_REG in sleep. - * Only active when reg_sdio_force = 0 - */ - -#define RTC_CNTL_SDIO_PD_EN (BIT(21)) -#define RTC_CNTL_SDIO_PD_EN_M (BIT(21)) -#define RTC_CNTL_SDIO_PD_EN_V 0x1 -#define RTC_CNTL_SDIO_PD_EN_S 21 - -#define RTC_CNTL_BIAS_CONF_REG (DR_REG_RTCCNTL_BASE + 0x78) - -/* RTC_CNTL_RST_BIAS_I2C : R/W ;bitpos:[31] ;default: 1'd0 ; */ - -/* Description: RST_BIAS_I2C */ - -#define RTC_CNTL_RST_BIAS_I2C (BIT(31)) -#define RTC_CNTL_RST_BIAS_I2C_M (BIT(31)) -#define RTC_CNTL_RST_BIAS_I2C_V 0x1 -#define RTC_CNTL_RST_BIAS_I2C_S 31 - -/* RTC_CNTL_DEC_HEARTBEAT_WIDTH : R/W ;bitpos:[30] ;default: 1'd0 ; */ - -/* Description: DEC_HEARTBEAT_WIDTH */ - -#define RTC_CNTL_DEC_HEARTBEAT_WIDTH (BIT(30)) -#define RTC_CNTL_DEC_HEARTBEAT_WIDTH_M (BIT(30)) -#define RTC_CNTL_DEC_HEARTBEAT_WIDTH_V 0x1 -#define RTC_CNTL_DEC_HEARTBEAT_WIDTH_S 30 - -/* RTC_CNTL_INC_HEARTBEAT_PERIOD : R/W ;bitpos:[29] ;default: 1'd0 ; */ - -/* Description: INC_HEARTBEAT_PERIOD */ - -#define RTC_CNTL_INC_HEARTBEAT_PERIOD (BIT(29)) -#define RTC_CNTL_INC_HEARTBEAT_PERIOD_M (BIT(29)) -#define RTC_CNTL_INC_HEARTBEAT_PERIOD_V 0x1 -#define RTC_CNTL_INC_HEARTBEAT_PERIOD_S 29 - -/* RTC_CNTL_DEC_HEARTBEAT_PERIOD : R/W ;bitpos:[28] ;default: 1'd0 ; */ - -/* Description: DEC_HEARTBEAT_PERIOD */ - -#define RTC_CNTL_DEC_HEARTBEAT_PERIOD (BIT(28)) -#define RTC_CNTL_DEC_HEARTBEAT_PERIOD_M (BIT(28)) -#define RTC_CNTL_DEC_HEARTBEAT_PERIOD_V 0x1 -#define RTC_CNTL_DEC_HEARTBEAT_PERIOD_S 28 - -/* RTC_CNTL_INC_HEARTBEAT_REFRESH : R/W ;bitpos:[27] ;default: 1'd0 ; */ - -/* Description: INC_HEARTBEAT_REFRESH */ - -#define RTC_CNTL_INC_HEARTBEAT_REFRESH (BIT(27)) -#define RTC_CNTL_INC_HEARTBEAT_REFRESH_M (BIT(27)) -#define RTC_CNTL_INC_HEARTBEAT_REFRESH_V 0x1 -#define RTC_CNTL_INC_HEARTBEAT_REFRESH_S 27 - -/* RTC_CNTL_ENB_SCK_XTAL : R/W ;bitpos:[26] ;default: 1'd0 ; */ - -/* Description: ENB_SCK_XTAL */ - -#define RTC_CNTL_ENB_SCK_XTAL (BIT(26)) -#define RTC_CNTL_ENB_SCK_XTAL_M (BIT(26)) -#define RTC_CNTL_ENB_SCK_XTAL_V 0x1 -#define RTC_CNTL_ENB_SCK_XTAL_S 26 - -/* RTC_CNTL_DBG_ATTEN : R/W ;bitpos:[25:24] ;default: 2'b00 ; */ - -/* Description: DBG_ATTEN */ - -#define RTC_CNTL_DBG_ATTEN 0x00000003 -#define RTC_CNTL_DBG_ATTEN_M ((RTC_CNTL_DBG_ATTEN_V)<<(RTC_CNTL_DBG_ATTEN_S)) -#define RTC_CNTL_DBG_ATTEN_V 0x3 -#define RTC_CNTL_DBG_ATTEN_S 24 -#define RTC_CNTL_DBG_ATTEN_DEFAULT 3 - -#define RTC_CNTL_REG (DR_REG_RTCCNTL_BASE + 0x7c) - -/* RTC_CNTL_FORCE_PU : R/W ;bitpos:[31] ;default: 1'd1 ; */ - -/* Description: RTC_REG force power up */ - -#define RTC_CNTL_FORCE_PU (BIT(31)) -#define RTC_CNTL_FORCE_PU_M (BIT(31)) -#define RTC_CNTL_FORCE_PU_V 0x1 -#define RTC_CNTL_FORCE_PU_S 31 - -/* RTC_CNTL_FORCE_PD : R/W ;bitpos:[30] ;default: 1'd0 ; */ - -/* Description: RTC_REG force power down (for RTC_REG power down - * means decreasethe voltage to 0.8v or lower ) - */ - -#define RTC_CNTL_FORCE_PD (BIT(30)) -#define RTC_CNTL_FORCE_PD_M (BIT(30)) -#define RTC_CNTL_FORCE_PD_V 0x1 -#define RTC_CNTL_FORCE_PD_S 30 - -/* RTC_CNTL_DBOOST_FORCE_PU : R/W ;bitpos:[29] ;default: 1'd1 ; */ - -/* Description: RTC_DBOOST force power up */ - -#define RTC_CNTL_DBOOST_FORCE_PU (BIT(29)) -#define RTC_CNTL_DBOOST_FORCE_PU_M (BIT(29)) -#define RTC_CNTL_DBOOST_FORCE_PU_V 0x1 -#define RTC_CNTL_DBOOST_FORCE_PU_S 29 - -/* RTC_CNTL_DBOOST_FORCE_PD : R/W ;bitpos:[28] ;default: 1'd0 ; */ - -/* Description: RTC_DBOOST force power down */ - -#define RTC_CNTL_DBOOST_FORCE_PD (BIT(28)) -#define RTC_CNTL_DBOOST_FORCE_PD_M (BIT(28)) -#define RTC_CNTL_DBOOST_FORCE_PD_V 0x1 -#define RTC_CNTL_DBOOST_FORCE_PD_S 28 - -/* RTC_CNTL_DBIAS_WAK : R/W ;bitpos:[27:25] ;default: 3'd4 ; */ - -/* Description: RTC_DBIAS during wakeup */ - -#define RTC_CNTL_DBIAS_WAK 0x00000007 -#define RTC_CNTL_DBIAS_WAK_M ((RTC_CNTL_DBIAS_WAK_V)<<(RTC_CNTL_DBIAS_WAK_S)) -#define RTC_CNTL_DBIAS_WAK_V 0x7 -#define RTC_CNTL_DBIAS_WAK_S 25 - -/* RTC_CNTL_DBIAS_SLP : R/W ;bitpos:[24:22] ;default: 3'd4 ; */ - -/* Description: RTC_DBIAS during sleep */ - -#define RTC_CNTL_DBIAS_SLP 0x00000007 -#define RTC_CNTL_DBIAS_SLP_M ((RTC_CNTL_DBIAS_SLP_V)<<(RTC_CNTL_DBIAS_SLP_S)) -#define RTC_CNTL_DBIAS_SLP_V 0x7 -#define RTC_CNTL_DBIAS_SLP_S 22 - -/* RTC_CNTL_SCK_DCAP : R/W ;bitpos:[21:14] ;default: 8'd0 ; */ - -/* Description: SCK_DCAP */ - -#define RTC_CNTL_SCK_DCAP 0x000000FF -#define RTC_CNTL_SCK_DCAP_M ((RTC_CNTL_SCK_DCAP_V)<<(RTC_CNTL_SCK_DCAP_S)) -#define RTC_CNTL_SCK_DCAP_V 0xFF -#define RTC_CNTL_SCK_DCAP_S 14 - -/* RTC_CNTL_DIG_DBIAS_SLP : R/W ;bitpos:[10:8] ;default: 3'd4 ; */ - -/* Description: DIG_REG_DBIAS during sleep */ - -#define RTC_CNTL_DIG_DBIAS_SLP 0x00000007 -#define RTC_CNTL_DIG_DBIAS_SLP_M ((RTC_CNTL_DIG_DBIAS_SLP_V)<<(RTC_CNTL_DIG_DBIAS_SLP_S)) -#define RTC_CNTL_DIG_DBIAS_SLP_V 0x7 -#define RTC_CNTL_DIG_DBIAS_SLP_S 8 - -/* RTC_CNTL_SCK_DCAP_FORCE : R/W ;bitpos:[7] ;default: 1'd0 ; */ - -/* Description: N/A */ - -#define RTC_CNTL_SCK_DCAP_FORCE (BIT(7)) -#define RTC_CNTL_SCK_DCAP_FORCE_M (BIT(7)) -#define RTC_CNTL_SCK_DCAP_FORCE_V 0x1 -#define RTC_CNTL_SCK_DCAP_FORCE_S 7 - -#define RTC_CNTL_PWC_REG (DR_REG_RTCCNTL_BASE + 0x80) - -/* RTC_CNTL_PD_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */ - -/* Description: enable power down rtc_peri in sleep */ - -#define RTC_CNTL_PD_EN (BIT(20)) -#define RTC_CNTL_PD_EN_M (BIT(20)) -#define RTC_CNTL_PD_EN_V 0x1 -#define RTC_CNTL_PD_EN_S 20 - -/* RTC_CNTL_FORCE_PU : R/W ;bitpos:[19] ;default: 1'd0 ; */ - -/* Description: rtc_peri force power up */ - -#define RTC_CNTL_PWC_FORCE_PU (BIT(19)) -#define RTC_CNTL_PWC_FORCE_PU_M (BIT(19)) -#define RTC_CNTL_PWC_FORCE_PU_V 0x1 -#define RTC_CNTL_PWC_FORCE_PU_S 19 - -/* RTC_CNTL_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b0 ; */ - -/* Description: rtc_peri force power down */ - -#define RTC_CNTL_PWC_FORCE_PD (BIT(18)) -#define RTC_CNTL_PWC_FORCE_PD_M (BIT(18)) -#define RTC_CNTL_PWC_FORCE_PD_V 0x1 -#define RTC_CNTL_PWC_FORCE_PD_S 18 - -/* RTC_CNTL_SLOWMEM_PD_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */ - -/* Description: enable power down RTC memory in sleep */ - -#define RTC_CNTL_SLOWMEM_PD_EN (BIT(17)) -#define RTC_CNTL_SLOWMEM_PD_EN_M (BIT(17)) -#define RTC_CNTL_SLOWMEM_PD_EN_V 0x1 -#define RTC_CNTL_SLOWMEM_PD_EN_S 17 - -/* RTC_CNTL_SLOWMEM_FORCE_PU : R/W ;bitpos:[16] ;default: 1'b1 ; */ - -/* Description: RTC memory force power up */ - -#define RTC_CNTL_SLOWMEM_FORCE_PU (BIT(16)) -#define RTC_CNTL_SLOWMEM_FORCE_PU_M (BIT(16)) -#define RTC_CNTL_SLOWMEM_FORCE_PU_V 0x1 -#define RTC_CNTL_SLOWMEM_FORCE_PU_S 16 - -/* RTC_CNTL_SLOWMEM_FORCE_PD : R/W ;bitpos:[15] ;default: 1'b0 ; */ - -/* Description: RTC memory force power down */ - -#define RTC_CNTL_SLOWMEM_FORCE_PD (BIT(15)) -#define RTC_CNTL_SLOWMEM_FORCE_PD_M (BIT(15)) -#define RTC_CNTL_SLOWMEM_FORCE_PD_V 0x1 -#define RTC_CNTL_SLOWMEM_FORCE_PD_S 15 - -/* RTC_CNTL_FASTMEM_PD_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */ - -/* Description: enable power down fast RTC memory in sleep */ - -#define RTC_CNTL_FASTMEM_PD_EN (BIT(14)) -#define RTC_CNTL_FASTMEM_PD_EN_M (BIT(14)) -#define RTC_CNTL_FASTMEM_PD_EN_V 0x1 -#define RTC_CNTL_FASTMEM_PD_EN_S 14 - -/* RTC_CNTL_FASTMEM_FORCE_PU : R/W ;bitpos:[13] ;default: 1'b1 ; */ - -/* Description: Fast RTC memory force power up */ - -#define RTC_CNTL_FASTMEM_FORCE_PU (BIT(13)) -#define RTC_CNTL_FASTMEM_FORCE_PU_M (BIT(13)) -#define RTC_CNTL_FASTMEM_FORCE_PU_V 0x1 -#define RTC_CNTL_FASTMEM_FORCE_PU_S 13 - -/* RTC_CNTL_FASTMEM_FORCE_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */ - -/* Description: Fast RTC memory force power down */ - -#define RTC_CNTL_FASTMEM_FORCE_PD (BIT(12)) -#define RTC_CNTL_FASTMEM_FORCE_PD_M (BIT(12)) -#define RTC_CNTL_FASTMEM_FORCE_PD_V 0x1 -#define RTC_CNTL_FASTMEM_FORCE_PD_S 12 - -/* RTC_CNTL_SLOWMEM_FORCE_LPU : R/W ;bitpos:[11] ;default: 1'b1 ; */ - -/* Description: RTC memory force no PD */ - -#define RTC_CNTL_SLOWMEM_FORCE_LPU (BIT(11)) -#define RTC_CNTL_SLOWMEM_FORCE_LPU_M (BIT(11)) -#define RTC_CNTL_SLOWMEM_FORCE_LPU_V 0x1 -#define RTC_CNTL_SLOWMEM_FORCE_LPU_S 11 - -/* RTC_CNTL_SLOWMEM_FORCE_LPD : R/W ;bitpos:[10] ;default: 1'b0 ; */ - -/* Description: RTC memory force PD */ - -#define RTC_CNTL_SLOWMEM_FORCE_LPD (BIT(10)) -#define RTC_CNTL_SLOWMEM_FORCE_LPD_M (BIT(10)) -#define RTC_CNTL_SLOWMEM_FORCE_LPD_V 0x1 -#define RTC_CNTL_SLOWMEM_FORCE_LPD_S 10 - -/* RTC_CNTL_SLOWMEM_FOLW_CPU : R/W ;bitpos:[9] ;default: 1'b0 ; */ - -/* Description: 1: RTC memory PD following CPU 0: RTC memory PD - * following RTC state machine - */ - -#define RTC_CNTL_SLOWMEM_FOLW_CPU (BIT(9)) -#define RTC_CNTL_SLOWMEM_FOLW_CPU_M (BIT(9)) -#define RTC_CNTL_SLOWMEM_FOLW_CPU_V 0x1 -#define RTC_CNTL_SLOWMEM_FOLW_CPU_S 9 - -/* RTC_CNTL_FASTMEM_FORCE_LPU : R/W ;bitpos:[8] ;default: 1'b1 ; */ - -/* Description: Fast RTC memory force no PD */ - -#define RTC_CNTL_FASTMEM_FORCE_LPU (BIT(8)) -#define RTC_CNTL_FASTMEM_FORCE_LPU_M (BIT(8)) -#define RTC_CNTL_FASTMEM_FORCE_LPU_V 0x1 -#define RTC_CNTL_FASTMEM_FORCE_LPU_S 8 - -/* RTC_CNTL_FASTMEM_FORCE_LPD : R/W ;bitpos:[7] ;default: 1'b0 ; */ - -/* Description: Fast RTC memory force PD */ - -#define RTC_CNTL_FASTMEM_FORCE_LPD (BIT(7)) -#define RTC_CNTL_FASTMEM_FORCE_LPD_M (BIT(7)) -#define RTC_CNTL_FASTMEM_FORCE_LPD_V 0x1 -#define RTC_CNTL_FASTMEM_FORCE_LPD_S 7 - -/* RTC_CNTL_FASTMEM_FOLW_CPU : R/W ;bitpos:[6] ;default: 1'b0 ; */ - -/* Description: 1: Fast RTC memory PD following CPU 0: fast RTC memory PD - * following RTC state machine - */ - -#define RTC_CNTL_FASTMEM_FOLW_CPU (BIT(6)) -#define RTC_CNTL_FASTMEM_FOLW_CPU_M (BIT(6)) -#define RTC_CNTL_FASTMEM_FOLW_CPU_V 0x1 -#define RTC_CNTL_FASTMEM_FOLW_CPU_S 6 - -/* RTC_CNTL_FORCE_NOISO : R/W ;bitpos:[5] ;default: 1'd1 ; */ - -/* Description: rtc_peri force no ISO */ - -#define RTC_CNTL_FORCE_NOISO (BIT(5)) -#define RTC_CNTL_FORCE_NOISO_M (BIT(5)) -#define RTC_CNTL_FORCE_NOISO_V 0x1 -#define RTC_CNTL_FORCE_NOISO_S 5 - -/* RTC_CNTL_FORCE_ISO : R/W ;bitpos:[4] ;default: 1'd0 ; */ - -/* Description: rtc_peri force ISO */ - -#define RTC_CNTL_FORCE_ISO (BIT(4)) -#define RTC_CNTL_FORCE_ISO_M (BIT(4)) -#define RTC_CNTL_FORCE_ISO_V 0x1 -#define RTC_CNTL_FORCE_ISO_S 4 - -/* RTC_CNTL_SLOWMEM_FORCE_ISO : R/W ;bitpos:[3] ;default: 1'b0 ; */ - -/* Description: RTC memory force ISO */ - -#define RTC_CNTL_SLOWMEM_FORCE_ISO (BIT(3)) -#define RTC_CNTL_SLOWMEM_FORCE_ISO_M (BIT(3)) -#define RTC_CNTL_SLOWMEM_FORCE_ISO_V 0x1 -#define RTC_CNTL_SLOWMEM_FORCE_ISO_S 3 - -/* RTC_CNTL_SLOWMEM_FORCE_NOISO : R/W ;bitpos:[2] ;default: 1'b1 ; */ - -/* Description: RTC memory force no ISO */ - -#define RTC_CNTL_SLOWMEM_FORCE_NOISO (BIT(2)) -#define RTC_CNTL_SLOWMEM_FORCE_NOISO_M (BIT(2)) -#define RTC_CNTL_SLOWMEM_FORCE_NOISO_V 0x1 -#define RTC_CNTL_SLOWMEM_FORCE_NOISO_S 2 - -/* RTC_CNTL_FASTMEM_FORCE_ISO : R/W ;bitpos:[1] ;default: 1'b0 ; */ - -/* Description: Fast RTC memory force ISO */ - -#define RTC_CNTL_FASTMEM_FORCE_ISO (BIT(1)) -#define RTC_CNTL_FASTMEM_FORCE_ISO_M (BIT(1)) -#define RTC_CNTL_FASTMEM_FORCE_ISO_V 0x1 -#define RTC_CNTL_FASTMEM_FORCE_ISO_S 1 - -/* RTC_CNTL_FASTMEM_FORCE_NOISO : R/W ;bitpos:[0] ;default: 1'b1 ; */ - -/* Description: Fast RTC memory force no ISO */ - -#define RTC_CNTL_FASTMEM_FORCE_NOISO (BIT(0)) -#define RTC_CNTL_FASTMEM_FORCE_NOISO_M (BIT(0)) -#define RTC_CNTL_FASTMEM_FORCE_NOISO_V 0x1 -#define RTC_CNTL_FASTMEM_FORCE_NOISO_S 0 - -#define RTC_CNTL_DIG_PWC_REG (DR_REG_RTCCNTL_BASE + 0x84) - -/* RTC_CNTL_DG_WRAP_PD_EN : R/W ;bitpos:[31] ;default: 0 ; */ - -/* Description: enable power down digital core in sleep */ - -#define RTC_CNTL_DG_WRAP_PD_EN (BIT(31)) -#define RTC_CNTL_DG_WRAP_PD_EN_M (BIT(31)) -#define RTC_CNTL_DG_WRAP_PD_EN_V 0x1 -#define RTC_CNTL_DG_WRAP_PD_EN_S 31 - -/* RTC_CNTL_WIFI_PD_EN : R/W ;bitpos:[30] ;default: 0 ; */ - -/* Description: enable power down wifi in sleep */ - -#define RTC_CNTL_WIFI_PD_EN (BIT(30)) -#define RTC_CNTL_WIFI_PD_EN_M (BIT(30)) -#define RTC_CNTL_WIFI_PD_EN_V 0x1 -#define RTC_CNTL_WIFI_PD_EN_S 30 - -/* RTC_CNTL_INTER_RAM4_PD_EN : R/W ;bitpos:[29] ;default: 0 ; */ - -/* Description: enable power down internal SRAM 4 in sleep */ - -#define RTC_CNTL_INTER_RAM4_PD_EN (BIT(29)) -#define RTC_CNTL_INTER_RAM4_PD_EN_M (BIT(29)) -#define RTC_CNTL_INTER_RAM4_PD_EN_V 0x1 -#define RTC_CNTL_INTER_RAM4_PD_EN_S 29 - -/* RTC_CNTL_INTER_RAM3_PD_EN : R/W ;bitpos:[28] ;default: 0 ; */ - -/* Description: enable power down internal SRAM 3 in sleep */ - -#define RTC_CNTL_INTER_RAM3_PD_EN (BIT(28)) -#define RTC_CNTL_INTER_RAM3_PD_EN_M (BIT(28)) -#define RTC_CNTL_INTER_RAM3_PD_EN_V 0x1 -#define RTC_CNTL_INTER_RAM3_PD_EN_S 28 - -/* RTC_CNTL_INTER_RAM2_PD_EN : R/W ;bitpos:[27] ;default: 0 ; */ - -/* Description: enable power down internal SRAM 2 in sleep */ - -#define RTC_CNTL_INTER_RAM2_PD_EN (BIT(27)) -#define RTC_CNTL_INTER_RAM2_PD_EN_M (BIT(27)) -#define RTC_CNTL_INTER_RAM2_PD_EN_V 0x1 -#define RTC_CNTL_INTER_RAM2_PD_EN_S 27 - -/* RTC_CNTL_INTER_RAM1_PD_EN : R/W ;bitpos:[26] ;default: 0 ; */ - -/* Description: enable power down internal SRAM 1 in sleep */ - -#define RTC_CNTL_INTER_RAM1_PD_EN (BIT(26)) -#define RTC_CNTL_INTER_RAM1_PD_EN_M (BIT(26)) -#define RTC_CNTL_INTER_RAM1_PD_EN_V 0x1 -#define RTC_CNTL_INTER_RAM1_PD_EN_S 26 - -/* RTC_CNTL_INTER_RAM0_PD_EN : R/W ;bitpos:[25] ;default: 0 ; */ - -/* Description: enable power down internal SRAM 0 in sleep */ - -#define RTC_CNTL_INTER_RAM0_PD_EN (BIT(25)) -#define RTC_CNTL_INTER_RAM0_PD_EN_M (BIT(25)) -#define RTC_CNTL_INTER_RAM0_PD_EN_V 0x1 -#define RTC_CNTL_INTER_RAM0_PD_EN_S 25 - -/* RTC_CNTL_ROM0_PD_EN : R/W ;bitpos:[24] ;default: 0 ; */ - -/* Description: enable power down ROM in sleep */ - -#define RTC_CNTL_ROM0_PD_EN (BIT(24)) -#define RTC_CNTL_ROM0_PD_EN_M (BIT(24)) -#define RTC_CNTL_ROM0_PD_EN_V 0x1 -#define RTC_CNTL_ROM0_PD_EN_S 24 - -/* RTC_CNTL_DG_WRAP_FORCE_PU : R/W ;bitpos:[20] ;default: 1'd1 ; */ - -/* Description: digital core force power up */ - -#define RTC_CNTL_DG_WRAP_FORCE_PU (BIT(20)) -#define RTC_CNTL_DG_WRAP_FORCE_PU_M (BIT(20)) -#define RTC_CNTL_DG_WRAP_FORCE_PU_V 0x1 -#define RTC_CNTL_DG_WRAP_FORCE_PU_S 20 - -/* RTC_CNTL_DG_WRAP_FORCE_PD : R/W ;bitpos:[19] ;default: 1'b0 ; */ - -/* Description: digital core force power down */ - -#define RTC_CNTL_DG_WRAP_FORCE_PD (BIT(19)) -#define RTC_CNTL_DG_WRAP_FORCE_PD_M (BIT(19)) -#define RTC_CNTL_DG_WRAP_FORCE_PD_V 0x1 -#define RTC_CNTL_DG_WRAP_FORCE_PD_S 19 - -/* RTC_CNTL_WIFI_FORCE_PU : R/W ;bitpos:[18] ;default: 1'd1 ; */ - -/* Description: wifi force power up */ - -#define RTC_CNTL_WIFI_FORCE_PU (BIT(18)) -#define RTC_CNTL_WIFI_FORCE_PU_M (BIT(18)) -#define RTC_CNTL_WIFI_FORCE_PU_V 0x1 -#define RTC_CNTL_WIFI_FORCE_PU_S 18 - -/* RTC_CNTL_WIFI_FORCE_PD : R/W ;bitpos:[17] ;default: 1'b0 ; */ - -/* Description: wifi force power down */ - -#define RTC_CNTL_WIFI_FORCE_PD (BIT(17)) -#define RTC_CNTL_WIFI_FORCE_PD_M (BIT(17)) -#define RTC_CNTL_WIFI_FORCE_PD_V 0x1 -#define RTC_CNTL_WIFI_FORCE_PD_S 17 - -/* RTC_CNTL_INTER_RAM4_FORCE_PU : R/W ;bitpos:[16] ;default: 1'd1 ; */ - -/* Description: internal SRAM 4 force power up */ - -#define RTC_CNTL_INTER_RAM4_FORCE_PU (BIT(16)) -#define RTC_CNTL_INTER_RAM4_FORCE_PU_M (BIT(16)) -#define RTC_CNTL_INTER_RAM4_FORCE_PU_V 0x1 -#define RTC_CNTL_INTER_RAM4_FORCE_PU_S 16 - -/* RTC_CNTL_INTER_RAM4_FORCE_PD : R/W ;bitpos:[15] ;default: 1'b0 ; */ - -/* Description: internal SRAM 4 force power down */ - -#define RTC_CNTL_INTER_RAM4_FORCE_PD (BIT(15)) -#define RTC_CNTL_INTER_RAM4_FORCE_PD_M (BIT(15)) -#define RTC_CNTL_INTER_RAM4_FORCE_PD_V 0x1 -#define RTC_CNTL_INTER_RAM4_FORCE_PD_S 15 - -/* RTC_CNTL_INTER_RAM3_FORCE_PU : R/W ;bitpos:[14] ;default: 1'd1 ; */ - -/* Description: internal SRAM 3 force power up */ - -#define RTC_CNTL_INTER_RAM3_FORCE_PU (BIT(14)) -#define RTC_CNTL_INTER_RAM3_FORCE_PU_M (BIT(14)) -#define RTC_CNTL_INTER_RAM3_FORCE_PU_V 0x1 -#define RTC_CNTL_INTER_RAM3_FORCE_PU_S 14 - -/* RTC_CNTL_INTER_RAM3_FORCE_PD : R/W ;bitpos:[13] ;default: 1'b0 ; */ - -/* Description: internal SRAM 3 force power down */ - -#define RTC_CNTL_INTER_RAM3_FORCE_PD (BIT(13)) -#define RTC_CNTL_INTER_RAM3_FORCE_PD_M (BIT(13)) -#define RTC_CNTL_INTER_RAM3_FORCE_PD_V 0x1 -#define RTC_CNTL_INTER_RAM3_FORCE_PD_S 13 - -/* RTC_CNTL_INTER_RAM2_FORCE_PU : R/W ;bitpos:[12] ;default: 1'd1 ; */ - -/* Description: internal SRAM 2 force power up */ - -#define RTC_CNTL_INTER_RAM2_FORCE_PU (BIT(12)) -#define RTC_CNTL_INTER_RAM2_FORCE_PU_M (BIT(12)) -#define RTC_CNTL_INTER_RAM2_FORCE_PU_V 0x1 -#define RTC_CNTL_INTER_RAM2_FORCE_PU_S 12 - -/* RTC_CNTL_INTER_RAM2_FORCE_PD : R/W ;bitpos:[11] ;default: 1'b0 ; */ - -/* Description: internal SRAM 2 force power down */ - -#define RTC_CNTL_INTER_RAM2_FORCE_PD (BIT(11)) -#define RTC_CNTL_INTER_RAM2_FORCE_PD_M (BIT(11)) -#define RTC_CNTL_INTER_RAM2_FORCE_PD_V 0x1 -#define RTC_CNTL_INTER_RAM2_FORCE_PD_S 11 - -/* RTC_CNTL_INTER_RAM1_FORCE_PU : R/W ;bitpos:[10] ;default: 1'd1 ; */ - -/* Description: internal SRAM 1 force power up */ - -#define RTC_CNTL_INTER_RAM1_FORCE_PU (BIT(10)) -#define RTC_CNTL_INTER_RAM1_FORCE_PU_M (BIT(10)) -#define RTC_CNTL_INTER_RAM1_FORCE_PU_V 0x1 -#define RTC_CNTL_INTER_RAM1_FORCE_PU_S 10 - -/* RTC_CNTL_INTER_RAM1_FORCE_PD : R/W ;bitpos:[9] ;default: 1'b0 ; */ - -/* Description: internal SRAM 1 force power down */ - -#define RTC_CNTL_INTER_RAM1_FORCE_PD (BIT(9)) -#define RTC_CNTL_INTER_RAM1_FORCE_PD_M (BIT(9)) -#define RTC_CNTL_INTER_RAM1_FORCE_PD_V 0x1 -#define RTC_CNTL_INTER_RAM1_FORCE_PD_S 9 - -/* RTC_CNTL_INTER_RAM0_FORCE_PU : R/W ;bitpos:[8] ;default: 1'd1 ; */ - -/* Description: internal SRAM 0 force power up */ - -#define RTC_CNTL_INTER_RAM0_FORCE_PU (BIT(8)) -#define RTC_CNTL_INTER_RAM0_FORCE_PU_M (BIT(8)) -#define RTC_CNTL_INTER_RAM0_FORCE_PU_V 0x1 -#define RTC_CNTL_INTER_RAM0_FORCE_PU_S 8 - -/* RTC_CNTL_INTER_RAM0_FORCE_PD : R/W ;bitpos:[7] ;default: 1'b0 ; */ - -/* Description: internal SRAM 0 force power down */ - -#define RTC_CNTL_INTER_RAM0_FORCE_PD (BIT(7)) -#define RTC_CNTL_INTER_RAM0_FORCE_PD_M (BIT(7)) -#define RTC_CNTL_INTER_RAM0_FORCE_PD_V 0x1 -#define RTC_CNTL_INTER_RAM0_FORCE_PD_S 7 - -/* RTC_CNTL_ROM0_FORCE_PU : R/W ;bitpos:[6] ;default: 1'd1 ; */ - -/* Description: ROM force power up */ - -#define RTC_CNTL_ROM0_FORCE_PU (BIT(6)) -#define RTC_CNTL_ROM0_FORCE_PU_M (BIT(6)) -#define RTC_CNTL_ROM0_FORCE_PU_V 0x1 -#define RTC_CNTL_ROM0_FORCE_PU_S 6 - -/* RTC_CNTL_ROM0_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */ - -/* Description: ROM force power down */ - -#define RTC_CNTL_ROM0_FORCE_PD (BIT(5)) -#define RTC_CNTL_ROM0_FORCE_PD_M (BIT(5)) -#define RTC_CNTL_ROM0_FORCE_PD_V 0x1 -#define RTC_CNTL_ROM0_FORCE_PD_S 5 - -/* RTC_CNTL_LSLP_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */ - -/* Description: memories in digital core force no PD in sleep */ - -#define RTC_CNTL_LSLP_MEM_FORCE_PU (BIT(4)) -#define RTC_CNTL_LSLP_MEM_FORCE_PU_M (BIT(4)) -#define RTC_CNTL_LSLP_MEM_FORCE_PU_V 0x1 -#define RTC_CNTL_LSLP_MEM_FORCE_PU_S 4 - -/* RTC_CNTL_LSLP_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */ - -/* Description: memories in digital core force PD in sleep */ - -#define RTC_CNTL_LSLP_MEM_FORCE_PD (BIT(3)) -#define RTC_CNTL_LSLP_MEM_FORCE_PD_M (BIT(3)) -#define RTC_CNTL_LSLP_MEM_FORCE_PD_V 0x1 -#define RTC_CNTL_LSLP_MEM_FORCE_PD_S 3 - -#define RTC_CNTL_DIG_ISO_REG (DR_REG_RTCCNTL_BASE + 0x88) - -/* RTC_CNTL_DG_WRAP_FORCE_NOISO : R/W ;bitpos:[31] ;default: 1'd1 ; */ - -/* Description: digital core force no ISO */ - -#define RTC_CNTL_DG_WRAP_FORCE_NOISO (BIT(31)) -#define RTC_CNTL_DG_WRAP_FORCE_NOISO_M (BIT(31)) -#define RTC_CNTL_DG_WRAP_FORCE_NOISO_V 0x1 -#define RTC_CNTL_DG_WRAP_FORCE_NOISO_S 31 - -/* RTC_CNTL_DG_WRAP_FORCE_ISO : R/W ;bitpos:[30] ;default: 1'd0 ; */ - -/* Description: digital core force ISO */ - -#define RTC_CNTL_DG_WRAP_FORCE_ISO (BIT(30)) -#define RTC_CNTL_DG_WRAP_FORCE_ISO_M (BIT(30)) -#define RTC_CNTL_DG_WRAP_FORCE_ISO_V 0x1 -#define RTC_CNTL_DG_WRAP_FORCE_ISO_S 30 - -/* RTC_CNTL_WIFI_FORCE_NOISO : R/W ;bitpos:[29] ;default: 1'd1 ; */ - -/* Description: wifi force no ISO */ - -#define RTC_CNTL_WIFI_FORCE_NOISO (BIT(29)) -#define RTC_CNTL_WIFI_FORCE_NOISO_M (BIT(29)) -#define RTC_CNTL_WIFI_FORCE_NOISO_V 0x1 -#define RTC_CNTL_WIFI_FORCE_NOISO_S 29 - -/* RTC_CNTL_WIFI_FORCE_ISO : R/W ;bitpos:[28] ;default: 1'd0 ; */ - -/* Description: wifi force ISO */ - -#define RTC_CNTL_WIFI_FORCE_ISO (BIT(28)) -#define RTC_CNTL_WIFI_FORCE_ISO_M (BIT(28)) -#define RTC_CNTL_WIFI_FORCE_ISO_V 0x1 -#define RTC_CNTL_WIFI_FORCE_ISO_S 28 - -/* RTC_CNTL_INTER_RAM4_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */ - -/* Description: internal SRAM 4 force no ISO */ - -#define RTC_CNTL_INTER_RAM4_FORCE_NOISO (BIT(27)) -#define RTC_CNTL_INTER_RAM4_FORCE_NOISO_M (BIT(27)) -#define RTC_CNTL_INTER_RAM4_FORCE_NOISO_V 0x1 -#define RTC_CNTL_INTER_RAM4_FORCE_NOISO_S 27 - -/* RTC_CNTL_INTER_RAM4_FORCE_ISO : R/W ;bitpos:[26] ;default: 1'd0 ; */ - -/* Description: internal SRAM 4 force ISO */ - -#define RTC_CNTL_INTER_RAM4_FORCE_ISO (BIT(26)) -#define RTC_CNTL_INTER_RAM4_FORCE_ISO_M (BIT(26)) -#define RTC_CNTL_INTER_RAM4_FORCE_ISO_V 0x1 -#define RTC_CNTL_INTER_RAM4_FORCE_ISO_S 26 - -/* RTC_CNTL_INTER_RAM3_FORCE_NOISO : R/W ;bitpos:[25] ;default: 1'd1 ; */ - -/* Description: internal SRAM 3 force no ISO */ - -#define RTC_CNTL_INTER_RAM3_FORCE_NOISO (BIT(25)) -#define RTC_CNTL_INTER_RAM3_FORCE_NOISO_M (BIT(25)) -#define RTC_CNTL_INTER_RAM3_FORCE_NOISO_V 0x1 -#define RTC_CNTL_INTER_RAM3_FORCE_NOISO_S 25 - -/* RTC_CNTL_INTER_RAM3_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */ - -/* Description: internal SRAM 3 force ISO */ - -#define RTC_CNTL_INTER_RAM3_FORCE_ISO (BIT(24)) -#define RTC_CNTL_INTER_RAM3_FORCE_ISO_M (BIT(24)) -#define RTC_CNTL_INTER_RAM3_FORCE_ISO_V 0x1 -#define RTC_CNTL_INTER_RAM3_FORCE_ISO_S 24 - -/* RTC_CNTL_INTER_RAM2_FORCE_NOISO : R/W ;bitpos:[23] ;default: 1'd1 ; */ - -/* Description: internal SRAM 2 force no ISO */ - -#define RTC_CNTL_INTER_RAM2_FORCE_NOISO (BIT(23)) -#define RTC_CNTL_INTER_RAM2_FORCE_NOISO_M (BIT(23)) -#define RTC_CNTL_INTER_RAM2_FORCE_NOISO_V 0x1 -#define RTC_CNTL_INTER_RAM2_FORCE_NOISO_S 23 - -/* RTC_CNTL_INTER_RAM2_FORCE_ISO : R/W ;bitpos:[22] ;default: 1'd0 ; */ - -/* Description: internal SRAM 2 force ISO */ - -#define RTC_CNTL_INTER_RAM2_FORCE_ISO (BIT(22)) -#define RTC_CNTL_INTER_RAM2_FORCE_ISO_M (BIT(22)) -#define RTC_CNTL_INTER_RAM2_FORCE_ISO_V 0x1 -#define RTC_CNTL_INTER_RAM2_FORCE_ISO_S 22 - -/* RTC_CNTL_INTER_RAM1_FORCE_NOISO : R/W ;bitpos:[21] ;default: 1'd1 ; */ - -/* Description: internal SRAM 1 force no ISO */ - -#define RTC_CNTL_INTER_RAM1_FORCE_NOISO (BIT(21)) -#define RTC_CNTL_INTER_RAM1_FORCE_NOISO_M (BIT(21)) -#define RTC_CNTL_INTER_RAM1_FORCE_NOISO_V 0x1 -#define RTC_CNTL_INTER_RAM1_FORCE_NOISO_S 21 - -/* RTC_CNTL_INTER_RAM1_FORCE_ISO : R/W ;bitpos:[20] ;default: 1'd0 ; */ - -/* Description: internal SRAM 1 force ISO */ - -#define RTC_CNTL_INTER_RAM1_FORCE_ISO (BIT(20)) -#define RTC_CNTL_INTER_RAM1_FORCE_ISO_M (BIT(20)) -#define RTC_CNTL_INTER_RAM1_FORCE_ISO_V 0x1 -#define RTC_CNTL_INTER_RAM1_FORCE_ISO_S 20 - -/* RTC_CNTL_INTER_RAM0_FORCE_NOISO : R/W ;bitpos:[19] ;default: 1'd1 ; */ - -/* Description: internal SRAM 0 force no ISO */ - -#define RTC_CNTL_INTER_RAM0_FORCE_NOISO (BIT(19)) -#define RTC_CNTL_INTER_RAM0_FORCE_NOISO_M (BIT(19)) -#define RTC_CNTL_INTER_RAM0_FORCE_NOISO_V 0x1 -#define RTC_CNTL_INTER_RAM0_FORCE_NOISO_S 19 - -/* RTC_CNTL_INTER_RAM0_FORCE_ISO : R/W ;bitpos:[18] ;default: 1'd0 ; */ - -/* Description: internal SRAM 0 force ISO */ - -#define RTC_CNTL_INTER_RAM0_FORCE_ISO (BIT(18)) -#define RTC_CNTL_INTER_RAM0_FORCE_ISO_M (BIT(18)) -#define RTC_CNTL_INTER_RAM0_FORCE_ISO_V 0x1 -#define RTC_CNTL_INTER_RAM0_FORCE_ISO_S 18 - -/* RTC_CNTL_ROM0_FORCE_NOISO : R/W ;bitpos:[17] ;default: 1'd1 ; */ - -/* Description: ROM force no ISO */ - -#define RTC_CNTL_ROM0_FORCE_NOISO (BIT(17)) -#define RTC_CNTL_ROM0_FORCE_NOISO_M (BIT(17)) -#define RTC_CNTL_ROM0_FORCE_NOISO_V 0x1 -#define RTC_CNTL_ROM0_FORCE_NOISO_S 17 - -/* RTC_CNTL_ROM0_FORCE_ISO : R/W ;bitpos:[16] ;default: 1'd0 ; */ - -/* Description: ROM force ISO */ - -#define RTC_CNTL_ROM0_FORCE_ISO (BIT(16)) -#define RTC_CNTL_ROM0_FORCE_ISO_M (BIT(16)) -#define RTC_CNTL_ROM0_FORCE_ISO_V 0x1 -#define RTC_CNTL_ROM0_FORCE_ISO_S 16 - -/* RTC_CNTL_DG_PAD_FORCE_HOLD : R/W ;bitpos:[15] ;default: 1'd0 ; */ - -/* Description: digital pad force hold */ - -#define RTC_CNTL_DG_PAD_FORCE_HOLD (BIT(15)) -#define RTC_CNTL_DG_PAD_FORCE_HOLD_M (BIT(15)) -#define RTC_CNTL_DG_PAD_FORCE_HOLD_V 0x1 -#define RTC_CNTL_DG_PAD_FORCE_HOLD_S 15 - -/* RTC_CNTL_DG_PAD_FORCE_UNHOLD : R/W ;bitpos:[14] ;default: 1'd1 ; */ - -/* Description: digital pad force un-hold */ - -#define RTC_CNTL_DG_PAD_FORCE_UNHOLD (BIT(14)) -#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_M (BIT(14)) -#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_V 0x1 -#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_S 14 - -/* RTC_CNTL_DG_PAD_FORCE_ISO : R/W ;bitpos:[13] ;default: 1'd0 ; */ - -/* Description: digital pad force ISO */ - -#define RTC_CNTL_DG_PAD_FORCE_ISO (BIT(13)) -#define RTC_CNTL_DG_PAD_FORCE_ISO_M (BIT(13)) -#define RTC_CNTL_DG_PAD_FORCE_ISO_V 0x1 -#define RTC_CNTL_DG_PAD_FORCE_ISO_S 13 - -/* RTC_CNTL_DG_PAD_FORCE_NOISO : R/W ;bitpos:[12] ;default: 1'd1 ; */ - -/* Description: digital pad force no ISO */ - -#define RTC_CNTL_DG_PAD_FORCE_NOISO (BIT(12)) -#define RTC_CNTL_DG_PAD_FORCE_NOISO_M (BIT(12)) -#define RTC_CNTL_DG_PAD_FORCE_NOISO_V 0x1 -#define RTC_CNTL_DG_PAD_FORCE_NOISO_S 12 - -/* RTC_CNTL_DG_PAD_AUTOHOLD_EN : R/W ;bitpos:[11] ;default: 1'd0 ; */ - -/* Description: digital pad enable auto-hold */ - -#define RTC_CNTL_DG_PAD_AUTOHOLD_EN (BIT(11)) -#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_M (BIT(11)) -#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_V 0x1 -#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_S 11 - -/* RTC_CNTL_CLR_DG_PAD_AUTOHOLD : WO ;bitpos:[10] ;default: 1'd0 ; */ - -/* Description: wtite only register to clear digital pad auto-hold */ - -#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD (BIT(10)) -#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_M (BIT(10)) -#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_V 0x1 -#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_S 10 - -/* RTC_CNTL_DG_PAD_AUTOHOLD : RO ;bitpos:[9] ;default: 1'd0 ; */ - -/* Description: read only register to indicate digital pad auto-hold status */ - -#define RTC_CNTL_DG_PAD_AUTOHOLD (BIT(9)) -#define RTC_CNTL_DG_PAD_AUTOHOLD_M (BIT(9)) -#define RTC_CNTL_DG_PAD_AUTOHOLD_V 0x1 -#define RTC_CNTL_DG_PAD_AUTOHOLD_S 9 - -/* RTC_CNTL_DIG_ISO_FORCE_ON : R/W ;bitpos:[8] ;default: 1'd0 ; */ - -/* Description: */ - -#define RTC_CNTL_DIG_ISO_FORCE_ON (BIT(8)) -#define RTC_CNTL_DIG_ISO_FORCE_ON_M (BIT(8)) -#define RTC_CNTL_DIG_ISO_FORCE_ON_V 0x1 -#define RTC_CNTL_DIG_ISO_FORCE_ON_S 8 - -/* RTC_CNTL_DIG_ISO_FORCE_OFF : R/W ;bitpos:[7] ;default: 1'd0 ; */ - -/* Description: */ - -#define RTC_CNTL_DIG_ISO_FORCE_OFF (BIT(7)) -#define RTC_CNTL_DIG_ISO_FORCE_OFF_M (BIT(7)) -#define RTC_CNTL_DIG_ISO_FORCE_OFF_V 0x1 -#define RTC_CNTL_DIG_ISO_FORCE_OFF_S 7 - -#define RTC_CNTL_WDTCONFIG0_REG (DR_REG_RTCCNTL_BASE + 0x8c) - -/* RTC_CNTL_WDT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ - -/* Description: enable RTC WDT */ - -#define RTC_CNTL_WDT_EN (BIT(31)) -#define RTC_CNTL_WDT_EN_M (BIT(31)) -#define RTC_CNTL_WDT_EN_V 0x1 -#define RTC_CNTL_WDT_EN_S 31 - -/* RTC_CNTL_WDT_STG0 : R/W ;bitpos:[30:28] ;default: 3'h0 ; */ - -/* Description: 1: interrupt stage en 2: CPU reset stage en 3: system reset - * stage en 4: RTC reset stage en - */ - -#define RTC_CNTL_WDT_STG0 0x00000007 -#define RTC_CNTL_WDT_STG0_M ((RTC_CNTL_WDT_STG0_V)<<(RTC_CNTL_WDT_STG0_S)) -#define RTC_CNTL_WDT_STG0_V 0x7 -#define RTC_CNTL_WDT_STG0_S 28 - -/* RTC_CNTL_WDT_STG1 : R/W ;bitpos:[27:25] ;default: 3'h0 ; */ - -/* Description: 1: interrupt stage en 2: CPU reset stage en 3: system reset - * stage en 4: RTC reset stage en - */ - -#define RTC_CNTL_WDT_STG1 0x00000007 -#define RTC_CNTL_WDT_STG1_M ((RTC_CNTL_WDT_STG1_V)<<(RTC_CNTL_WDT_STG1_S)) -#define RTC_CNTL_WDT_STG1_V 0x7 -#define RTC_CNTL_WDT_STG1_S 25 - -/* RTC_CNTL_WDT_STG2 : R/W ;bitpos:[24:22] ;default: 3'h0 ; */ - -/* Description: 1: interrupt stage en 2: CPU reset stage en 3: system reset - * stage en 4: RTC reset stage en - */ - -#define RTC_CNTL_WDT_STG2 0x00000007 -#define RTC_CNTL_WDT_STG2_M ((RTC_CNTL_WDT_STG2_V)<<(RTC_CNTL_WDT_STG2_S)) -#define RTC_CNTL_WDT_STG2_V 0x7 -#define RTC_CNTL_WDT_STG2_S 22 - -/* RTC_CNTL_WDT_STG3 : R/W ;bitpos:[21:19] ;default: 3'h0 ; */ - -/* Description: 1: interrupt stage en 2: CPU reset stage en 3: system reset - * stage en 4: RTC reset stage en - */ - -#define RTC_CNTL_WDT_STG3 0x00000007 -#define RTC_CNTL_WDT_STG3_M ((RTC_CNTL_WDT_STG3_V)<<(RTC_CNTL_WDT_STG3_S)) -#define RTC_CNTL_WDT_STG3_V 0x7 -#define RTC_CNTL_WDT_STG3_S 19 - -/* RTC_CNTL_WDT_EDGE_INT_EN : R/W ;bitpos:[18] ;default: 1'h0 ; */ - -/* Description: N/A */ - -#define RTC_CNTL_WDT_EDGE_INT_EN (BIT(18)) -#define RTC_CNTL_WDT_EDGE_INT_EN_M (BIT(18)) -#define RTC_CNTL_WDT_EDGE_INT_EN_V 0x1 -#define RTC_CNTL_WDT_EDGE_INT_EN_S 18 - -/* RTC_CNTL_WDT_LEVEL_INT_EN : R/W ;bitpos:[17] ;default: 1'h0 ; */ - -/* Description: N/A */ - -#define RTC_CNTL_WDT_LEVEL_INT_EN (BIT(17)) -#define RTC_CNTL_WDT_LEVEL_INT_EN_M (BIT(17)) -#define RTC_CNTL_WDT_LEVEL_INT_EN_V 0x1 -#define RTC_CNTL_WDT_LEVEL_INT_EN_S 17 - -/* RTC_CNTL_WDT_CPU_RESET_LENGTH : R/W ;bitpos:[16:14] ;default: 3'h1 ; */ - -/* Description: CPU reset counter length */ - -#define RTC_CNTL_WDT_CPU_RESET_LENGTH 0x00000007 -#define RTC_CNTL_WDT_CPU_RESET_LENGTH_M ((RTC_CNTL_WDT_CPU_RESET_LENGTH_V)<<(RTC_CNTL_WDT_CPU_RESET_LENGTH_S)) -#define RTC_CNTL_WDT_CPU_RESET_LENGTH_V 0x7 -#define RTC_CNTL_WDT_CPU_RESET_LENGTH_S 14 - -/* RTC_CNTL_WDT_SYS_RESET_LENGTH : R/W ;bitpos:[13:11] ;default: 3'h1 ; */ - -/* Description: system reset counter length */ - -#define RTC_CNTL_WDT_SYS_RESET_LENGTH 0x00000007 -#define RTC_CNTL_WDT_SYS_RESET_LENGTH_M ((RTC_CNTL_WDT_SYS_RESET_LENGTH_V)<<(RTC_CNTL_WDT_SYS_RESET_LENGTH_S)) -#define RTC_CNTL_WDT_SYS_RESET_LENGTH_V 0x7 -#define RTC_CNTL_WDT_SYS_RESET_LENGTH_S 11 - -/* RTC_CNTL_WDT_FLASHBOOT_MOD_EN : R/W ;bitpos:[10] ;default: 1'h1 ; */ - -/* Description: enable WDT in flash boot */ - -#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN (BIT(10)) -#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_M (BIT(10)) -#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_V 0x1 -#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_S 10 - -/* RTC_CNTL_WDT_PROCPU_RESET_EN : R/W ;bitpos:[9] ;default: 1'd0 ; */ - -/* Description: enable WDT reset PRO CPU */ - -#define RTC_CNTL_WDT_PROCPU_RESET_EN (BIT(9)) -#define RTC_CNTL_WDT_PROCPU_RESET_EN_M (BIT(9)) -#define RTC_CNTL_WDT_PROCPU_RESET_EN_V 0x1 -#define RTC_CNTL_WDT_PROCPU_RESET_EN_S 9 - -/* RTC_CNTL_WDT_APPCPU_RESET_EN : R/W ;bitpos:[8] ;default: 1'd0 ; */ - -/* Description: enable WDT reset APP CPU */ - -#define RTC_CNTL_WDT_APPCPU_RESET_EN (BIT(8)) -#define RTC_CNTL_WDT_APPCPU_RESET_EN_M (BIT(8)) -#define RTC_CNTL_WDT_APPCPU_RESET_EN_V 0x1 -#define RTC_CNTL_WDT_APPCPU_RESET_EN_S 8 - -/* RTC_CNTL_WDT_PAUSE_IN_SLP : R/W ;bitpos:[7] ;default: 1'd1 ; */ - -/* Description: pause WDT in sleep */ - -#define RTC_CNTL_WDT_PAUSE_IN_SLP (BIT(7)) -#define RTC_CNTL_WDT_PAUSE_IN_SLP_M (BIT(7)) -#define RTC_CNTL_WDT_PAUSE_IN_SLP_V 0x1 -#define RTC_CNTL_WDT_PAUSE_IN_SLP_S 7 - -#define RTC_CNTL_WDTCONFIG1_REG (DR_REG_RTCCNTL_BASE + 0x90) - -/* RTC_CNTL_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd128000 ; */ - -/* Description: */ - -#define RTC_CNTL_WDT_STG0_HOLD 0xFFFFFFFF -#define RTC_CNTL_WDT_STG0_HOLD_M ((RTC_CNTL_WDT_STG0_HOLD_V)<<(RTC_CNTL_WDT_STG0_HOLD_S)) -#define RTC_CNTL_WDT_STG0_HOLD_V 0xFFFFFFFF -#define RTC_CNTL_WDT_STG0_HOLD_S 0 - -#define RTC_CNTL_WDTCONFIG2_REG (DR_REG_RTCCNTL_BASE + 0x94) - -/* RTC_CNTL_WDT_STG1_HOLD : R/W ;bitpos:[31:0] ;default: 32'd80000 ; */ - -/* Description: */ - -#define RTC_CNTL_WDT_STG1_HOLD 0xFFFFFFFF -#define RTC_CNTL_WDT_STG1_HOLD_M ((RTC_CNTL_WDT_STG1_HOLD_V)<<(RTC_CNTL_WDT_STG1_HOLD_S)) -#define RTC_CNTL_WDT_STG1_HOLD_V 0xFFFFFFFF -#define RTC_CNTL_WDT_STG1_HOLD_S 0 - -#define RTC_CNTL_WDTCONFIG3_REG (DR_REG_RTCCNTL_BASE + 0x98) - -/* RTC_CNTL_WDT_STG2_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */ - -/* Description: */ - -#define RTC_CNTL_WDT_STG2_HOLD 0xFFFFFFFF -#define RTC_CNTL_WDT_STG2_HOLD_M ((RTC_CNTL_WDT_STG2_HOLD_V)<<(RTC_CNTL_WDT_STG2_HOLD_S)) -#define RTC_CNTL_WDT_STG2_HOLD_V 0xFFFFFFFF -#define RTC_CNTL_WDT_STG2_HOLD_S 0 - -#define RTC_CNTL_WDTCONFIG4_REG (DR_REG_RTCCNTL_BASE + 0x9c) - -/* RTC_CNTL_WDT_STG3_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */ - -/* Description: */ - -#define RTC_CNTL_WDT_STG3_HOLD 0xFFFFFFFF -#define RTC_CNTL_WDT_STG3_HOLD_M ((RTC_CNTL_WDT_STG3_HOLD_V)<<(RTC_CNTL_WDT_STG3_HOLD_S)) -#define RTC_CNTL_WDT_STG3_HOLD_V 0xFFFFFFFF -#define RTC_CNTL_WDT_STG3_HOLD_S 0 - -#define RTC_CNTL_WDTFEED_REG (DR_REG_RTCCNTL_BASE + 0xa0) - -/* RTC_CNTL_WDT_FEED : WO ;bitpos:[31] ;default: 1'd0 ; */ - -/* Description: */ - -#define RTC_CNTL_WDT_FEED (BIT(31)) -#define RTC_CNTL_WDT_FEED_M (BIT(31)) -#define RTC_CNTL_WDT_FEED_V 0x1 -#define RTC_CNTL_WDT_FEED_S 31 - -#define RTC_CNTL_WDTWPROTECT_REG (DR_REG_RTCCNTL_BASE + 0xa4) - -/* RTC_CNTL_WDT_WKEY : R/W ;bitpos:[31:0] ;default: 32'h50d83aa1 ; */ - -/* Description: */ - -#define RTC_CNTL_WDT_WKEY 0xFFFFFFFF -#define RTC_CNTL_WDT_WKEY_M ((RTC_CNTL_WDT_WKEY_V)<<(RTC_CNTL_WDT_WKEY_S)) -#define RTC_CNTL_WDT_WKEY_V 0xFFFFFFFF -#define RTC_CNTL_WDT_WKEY_S 0 - -#define RTC_CNTL_TEST_MUX_REG (DR_REG_RTCCNTL_BASE + 0xa8) - -/* RTC_CNTL_DTEST_RTC : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ - -/* Description: DTEST_RTC */ - -#define RTC_CNTL_DTEST_RTC 0x00000003 -#define RTC_CNTL_DTEST_RTC_M ((RTC_CNTL_DTEST_RTC_V)<<(RTC_CNTL_DTEST_RTC_S)) -#define RTC_CNTL_DTEST_RTC_V 0x3 -#define RTC_CNTL_DTEST_RTC_S 30 - -/* RTC_CNTL_ENT_RTC : R/W ;bitpos:[29] ;default: 1'd0 ; */ - -/* Description: ENT_RTC */ - -#define RTC_CNTL_ENT_RTC (BIT(29)) -#define RTC_CNTL_ENT_RTC_M (BIT(29)) -#define RTC_CNTL_ENT_RTC_V 0x1 -#define RTC_CNTL_ENT_RTC_S 29 - -#define RTC_CNTL_SW_CPU_STALL_REG (DR_REG_RTCCNTL_BASE + 0xac) - -/* RTC_CNTL_SW_STALL_PROCPU_C1 : R/W ;bitpos:[31:26] ;default: 6'b0 ; */ - -/* Description: {reg_sw_stall_procpu_c1[5:0] - * reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU - */ - -#define RTC_CNTL_SW_STALL_PROCPU_C1 0x0000003F -#define RTC_CNTL_SW_STALL_PROCPU_C1_M ((RTC_CNTL_SW_STALL_PROCPU_C1_V)<<(RTC_CNTL_SW_STALL_PROCPU_C1_S)) -#define RTC_CNTL_SW_STALL_PROCPU_C1_V 0x3F -#define RTC_CNTL_SW_STALL_PROCPU_C1_S 26 - -/* RTC_CNTL_SW_STALL_APPCPU_C1 : R/W ;bitpos:[25:20] ;default: 6'b0 ; */ - -/* Description: {reg_sw_stall_appcpu_c1[5:0] - * reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU - */ - -#define RTC_CNTL_SW_STALL_APPCPU_C1 0x0000003F -#define RTC_CNTL_SW_STALL_APPCPU_C1_M ((RTC_CNTL_SW_STALL_APPCPU_C1_V)<<(RTC_CNTL_SW_STALL_APPCPU_C1_S)) -#define RTC_CNTL_SW_STALL_APPCPU_C1_V 0x3F -#define RTC_CNTL_SW_STALL_APPCPU_C1_S 20 - -#define RTC_CNTL_STORE4_REG (DR_REG_RTCCNTL_BASE + 0xb0) - -/* RTC_CNTL_SCRATCH4 : R/W ;bitpos:[31:0] ;default: 0 ; */ - -/* Description: 32-bit general purpose retention register */ - -#define RTC_CNTL_SCRATCH4 0xFFFFFFFF -#define RTC_CNTL_SCRATCH4_M ((RTC_CNTL_SCRATCH4_V)<<(RTC_CNTL_SCRATCH4_S)) -#define RTC_CNTL_SCRATCH4_V 0xFFFFFFFF -#define RTC_CNTL_SCRATCH4_S 0 - -#define RTC_CNTL_STORE5_REG (DR_REG_RTCCNTL_BASE + 0xb4) - -/* RTC_CNTL_SCRATCH5 : R/W ;bitpos:[31:0] ;default: 0 ; */ - -/* Description: 32-bit general purpose retention register */ - -#define RTC_CNTL_SCRATCH5 0xFFFFFFFF -#define RTC_CNTL_SCRATCH5_M ((RTC_CNTL_SCRATCH5_V)<<(RTC_CNTL_SCRATCH5_S)) -#define RTC_CNTL_SCRATCH5_V 0xFFFFFFFF -#define RTC_CNTL_SCRATCH5_S 0 - -#define RTC_CNTL_STORE6_REG (DR_REG_RTCCNTL_BASE + 0xb8) - -/* RTC_CNTL_SCRATCH6 : R/W ;bitpos:[31:0] ;default: 0 ; */ - -/* Description: 32-bit general purpose retention register */ - -#define RTC_CNTL_SCRATCH6 0xFFFFFFFF -#define RTC_CNTL_SCRATCH6_M ((RTC_CNTL_SCRATCH6_V)<<(RTC_CNTL_SCRATCH6_S)) -#define RTC_CNTL_SCRATCH6_V 0xFFFFFFFF -#define RTC_CNTL_SCRATCH6_S 0 - -#define RTC_CNTL_STORE7_REG (DR_REG_RTCCNTL_BASE + 0xbc) - -/* RTC_CNTL_SCRATCH7 : R/W ;bitpos:[31:0] ;default: 0 ; */ - -/* Description: 32-bit general purpose retention register */ - -#define RTC_CNTL_SCRATCH7 0xFFFFFFFF -#define RTC_CNTL_SCRATCH7_M ((RTC_CNTL_SCRATCH7_V)<<(RTC_CNTL_SCRATCH7_S)) -#define RTC_CNTL_SCRATCH7_V 0xFFFFFFFF -#define RTC_CNTL_SCRATCH7_S 0 - -#define RTC_CNTL_DIAG0_REG (DR_REG_RTCCNTL_BASE + 0xc0) - -/* RTC_CNTL_LOW_POWER_DIAG0 : RO ;bitpos:[31:0] ;default: 0 ; */ - -/* Description: */ - -#define RTC_CNTL_LOW_POWER_DIAG0 0xFFFFFFFF -#define RTC_CNTL_LOW_POWER_DIAG0_M ((RTC_CNTL_LOW_POWER_DIAG0_V)<<(RTC_CNTL_LOW_POWER_DIAG0_S)) -#define RTC_CNTL_LOW_POWER_DIAG0_V 0xFFFFFFFF -#define RTC_CNTL_LOW_POWER_DIAG0_S 0 - -#define RTC_CNTL_DIAG1_REG (DR_REG_RTCCNTL_BASE + 0xc4) - -/* RTC_CNTL_LOW_POWER_DIAG1 : RO ;bitpos:[31:0] ;default: 0 ; */ - -/* Description: */ - -#define RTC_CNTL_LOW_POWER_DIAG1 0xFFFFFFFF -#define RTC_CNTL_LOW_POWER_DIAG1_M ((RTC_CNTL_LOW_POWER_DIAG1_V)<<(RTC_CNTL_LOW_POWER_DIAG1_S)) -#define RTC_CNTL_LOW_POWER_DIAG1_V 0xFFFFFFFF -#define RTC_CNTL_LOW_POWER_DIAG1_S 0 - -#define RTC_CNTL_HOLD_FORCE_REG (DR_REG_RTCCNTL_BASE + 0xc8) - -/* RTC_CNTL_X32N_HOLD_FORCE : R/W ;bitpos:[17] ;default: 1'b0 ; */ - -/* Description: */ - -#define RTC_CNTL_X32N_HOLD_FORCE (BIT(17)) -#define RTC_CNTL_X32N_HOLD_FORCE_M (BIT(17)) -#define RTC_CNTL_X32N_HOLD_FORCE_V 0x1 -#define RTC_CNTL_X32N_HOLD_FORCE_S 17 - -/* RTC_CNTL_X32P_HOLD_FORCE : R/W ;bitpos:[16] ;default: 1'b0 ; */ - -/* Description: */ - -#define RTC_CNTL_X32P_HOLD_FORCE (BIT(16)) -#define RTC_CNTL_X32P_HOLD_FORCE_M (BIT(16)) -#define RTC_CNTL_X32P_HOLD_FORCE_V 0x1 -#define RTC_CNTL_X32P_HOLD_FORCE_S 16 - -/* RTC_CNTL_TOUCH_PAD7_HOLD_FORCE : R/W ;bitpos:[15] ;default: 1'b0 ; */ - -/* Description: */ - -#define RTC_CNTL_TOUCH_PAD7_HOLD_FORCE (BIT(15)) -#define RTC_CNTL_TOUCH_PAD7_HOLD_FORCE_M (BIT(15)) -#define RTC_CNTL_TOUCH_PAD7_HOLD_FORCE_V 0x1 -#define RTC_CNTL_TOUCH_PAD7_HOLD_FORCE_S 15 - -/* RTC_CNTL_TOUCH_PAD6_HOLD_FORCE : R/W ;bitpos:[14] ;default: 1'b0 ; */ - -/* Description: */ - -#define RTC_CNTL_TOUCH_PAD6_HOLD_FORCE (BIT(14)) -#define RTC_CNTL_TOUCH_PAD6_HOLD_FORCE_M (BIT(14)) -#define RTC_CNTL_TOUCH_PAD6_HOLD_FORCE_V 0x1 -#define RTC_CNTL_TOUCH_PAD6_HOLD_FORCE_S 14 - -/* RTC_CNTL_TOUCH_PAD5_HOLD_FORCE : R/W ;bitpos:[13] ;default: 1'b0 ; */ - -/* Description: */ - -#define RTC_CNTL_TOUCH_PAD5_HOLD_FORCE (BIT(13)) -#define RTC_CNTL_TOUCH_PAD5_HOLD_FORCE_M (BIT(13)) -#define RTC_CNTL_TOUCH_PAD5_HOLD_FORCE_V 0x1 -#define RTC_CNTL_TOUCH_PAD5_HOLD_FORCE_S 13 - -/* RTC_CNTL_TOUCH_PAD4_HOLD_FORCE : R/W ;bitpos:[12] ;default: 1'b0 ; */ - -/* Description: */ - -#define RTC_CNTL_TOUCH_PAD4_HOLD_FORCE (BIT(12)) -#define RTC_CNTL_TOUCH_PAD4_HOLD_FORCE_M (BIT(12)) -#define RTC_CNTL_TOUCH_PAD4_HOLD_FORCE_V 0x1 -#define RTC_CNTL_TOUCH_PAD4_HOLD_FORCE_S 12 - -/* RTC_CNTL_TOUCH_PAD3_HOLD_FORCE : R/W ;bitpos:[11] ;default: 1'b0 ; */ - -/* Description: */ - -#define RTC_CNTL_TOUCH_PAD3_HOLD_FORCE (BIT(11)) -#define RTC_CNTL_TOUCH_PAD3_HOLD_FORCE_M (BIT(11)) -#define RTC_CNTL_TOUCH_PAD3_HOLD_FORCE_V 0x1 -#define RTC_CNTL_TOUCH_PAD3_HOLD_FORCE_S 11 - -/* RTC_CNTL_TOUCH_PAD2_HOLD_FORCE : R/W ;bitpos:[10] ;default: 1'b0 ; */ - -/* Description: */ - -#define RTC_CNTL_TOUCH_PAD2_HOLD_FORCE (BIT(10)) -#define RTC_CNTL_TOUCH_PAD2_HOLD_FORCE_M (BIT(10)) -#define RTC_CNTL_TOUCH_PAD2_HOLD_FORCE_V 0x1 -#define RTC_CNTL_TOUCH_PAD2_HOLD_FORCE_S 10 - -/* RTC_CNTL_TOUCH_PAD1_HOLD_FORCE : R/W ;bitpos:[9] ;default: 1'b0 ; */ - -/* Description: */ - -#define RTC_CNTL_TOUCH_PAD1_HOLD_FORCE (BIT(9)) -#define RTC_CNTL_TOUCH_PAD1_HOLD_FORCE_M (BIT(9)) -#define RTC_CNTL_TOUCH_PAD1_HOLD_FORCE_V 0x1 -#define RTC_CNTL_TOUCH_PAD1_HOLD_FORCE_S 9 - -/* RTC_CNTL_TOUCH_PAD0_HOLD_FORCE : R/W ;bitpos:[8] ;default: 1'b0 ; */ - -/* Description: */ - -#define RTC_CNTL_TOUCH_PAD0_HOLD_FORCE (BIT(8)) -#define RTC_CNTL_TOUCH_PAD0_HOLD_FORCE_M (BIT(8)) -#define RTC_CNTL_TOUCH_PAD0_HOLD_FORCE_V 0x1 -#define RTC_CNTL_TOUCH_PAD0_HOLD_FORCE_S 8 - -/* RTC_CNTL_SENSE4_HOLD_FORCE : R/W ;bitpos:[7] ;default: 1'b0 ; */ - -/* Description: */ - -#define RTC_CNTL_SENSE4_HOLD_FORCE (BIT(7)) -#define RTC_CNTL_SENSE4_HOLD_FORCE_M (BIT(7)) -#define RTC_CNTL_SENSE4_HOLD_FORCE_V 0x1 -#define RTC_CNTL_SENSE4_HOLD_FORCE_S 7 - -/* RTC_CNTL_SENSE3_HOLD_FORCE : R/W ;bitpos:[6] ;default: 1'b0 ; */ - -/* Description: */ - -#define RTC_CNTL_SENSE3_HOLD_FORCE (BIT(6)) -#define RTC_CNTL_SENSE3_HOLD_FORCE_M (BIT(6)) -#define RTC_CNTL_SENSE3_HOLD_FORCE_V 0x1 -#define RTC_CNTL_SENSE3_HOLD_FORCE_S 6 - -/* RTC_CNTL_SENSE2_HOLD_FORCE : R/W ;bitpos:[5] ;default: 1'b0 ; */ - -/* Description: */ - -#define RTC_CNTL_SENSE2_HOLD_FORCE (BIT(5)) -#define RTC_CNTL_SENSE2_HOLD_FORCE_M (BIT(5)) -#define RTC_CNTL_SENSE2_HOLD_FORCE_V 0x1 -#define RTC_CNTL_SENSE2_HOLD_FORCE_S 5 - -/* RTC_CNTL_SENSE1_HOLD_FORCE : R/W ;bitpos:[4] ;default: 1'b0 ; */ - -/* Description: */ - -#define RTC_CNTL_SENSE1_HOLD_FORCE (BIT(4)) -#define RTC_CNTL_SENSE1_HOLD_FORCE_M (BIT(4)) -#define RTC_CNTL_SENSE1_HOLD_FORCE_V 0x1 -#define RTC_CNTL_SENSE1_HOLD_FORCE_S 4 - -/* RTC_CNTL_PDAC2_HOLD_FORCE : R/W ;bitpos:[3] ;default: 1'b0 ; */ - -/* Description: */ - -#define RTC_CNTL_PDAC2_HOLD_FORCE (BIT(3)) -#define RTC_CNTL_PDAC2_HOLD_FORCE_M (BIT(3)) -#define RTC_CNTL_PDAC2_HOLD_FORCE_V 0x1 -#define RTC_CNTL_PDAC2_HOLD_FORCE_S 3 - -/* RTC_CNTL_PDAC1_HOLD_FORCE : R/W ;bitpos:[2] ;default: 1'b0 ; */ - -/* Description: */ - -#define RTC_CNTL_PDAC1_HOLD_FORCE (BIT(2)) -#define RTC_CNTL_PDAC1_HOLD_FORCE_M (BIT(2)) -#define RTC_CNTL_PDAC1_HOLD_FORCE_V 0x1 -#define RTC_CNTL_PDAC1_HOLD_FORCE_S 2 - -/* RTC_CNTL_ADC2_HOLD_FORCE : R/W ;bitpos:[1] ;default: 1'b0 ; */ - -/* Description: */ - -#define RTC_CNTL_ADC2_HOLD_FORCE (BIT(1)) -#define RTC_CNTL_ADC2_HOLD_FORCE_M (BIT(1)) -#define RTC_CNTL_ADC2_HOLD_FORCE_V 0x1 -#define RTC_CNTL_ADC2_HOLD_FORCE_S 1 - -/* RTC_CNTL_ADC1_HOLD_FORCE : R/W ;bitpos:[0] ;default: 1'b0 ; */ - -/* Description: */ - -#define RTC_CNTL_ADC1_HOLD_FORCE (BIT(0)) -#define RTC_CNTL_ADC1_HOLD_FORCE_M (BIT(0)) -#define RTC_CNTL_ADC1_HOLD_FORCE_V 0x1 -#define RTC_CNTL_ADC1_HOLD_FORCE_S 0 - -#define RTC_CNTL_EXT_WAKEUP1_REG (DR_REG_RTCCNTL_BASE + 0xcc) - -/* RTC_CNTL_EXT_WAKEUP1_STATUS_CLR : WO ;bitpos:[18] ;default: 1'd0 ; */ - -/* Description: clear ext wakeup1 status */ - -#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR (BIT(18)) -#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_M (BIT(18)) -#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_V 0x1 -#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_S 18 - -/* RTC_CNTL_EXT_WAKEUP1_SEL : R/W ;bitpos:[17:0] ;default: 18'd0 ; */ - -/* Description: Bitmap to select RTC pads for ext wakeup1 */ - -#define RTC_CNTL_EXT_WAKEUP1_SEL 0x0003FFFF -#define RTC_CNTL_EXT_WAKEUP1_SEL_M ((RTC_CNTL_EXT_WAKEUP1_SEL_V)<<(RTC_CNTL_EXT_WAKEUP1_SEL_S)) -#define RTC_CNTL_EXT_WAKEUP1_SEL_V 0x3FFFF -#define RTC_CNTL_EXT_WAKEUP1_SEL_S 0 - -#define RTC_CNTL_EXT_WAKEUP1_STATUS_REG (DR_REG_RTCCNTL_BASE + 0xd0) - -/* RTC_CNTL_EXT_WAKEUP1_STATUS : RO ;bitpos:[17:0] ;default: 18'd0 ; */ - -/* Description: ext wakeup1 status */ - -#define RTC_CNTL_EXT_WAKEUP1_STATUS 0x0003FFFF -#define RTC_CNTL_EXT_WAKEUP1_STATUS_M ((RTC_CNTL_EXT_WAKEUP1_STATUS_V)<<(RTC_CNTL_EXT_WAKEUP1_STATUS_S)) -#define RTC_CNTL_EXT_WAKEUP1_STATUS_V 0x3FFFF -#define RTC_CNTL_EXT_WAKEUP1_STATUS_S 0 - -#define RTC_CNTL_BROWN_OUT_REG (DR_REG_RTCCNTL_BASE + 0xd4) - -/* RTC_CNTL_BROWN_OUT_DET : RO ;bitpos:[31] ;default: 1'b0 ; */ - -/* Description: brown out detect */ - -#define RTC_CNTL_BROWN_OUT_DET (BIT(31)) -#define RTC_CNTL_BROWN_OUT_DET_M (BIT(31)) -#define RTC_CNTL_BROWN_OUT_DET_V 0x1 -#define RTC_CNTL_BROWN_OUT_DET_S 31 - -/* RTC_CNTL_BROWN_OUT_ENA : R/W ;bitpos:[30] ;default: 1'b0 ; */ - -/* Description: enable brown out */ - -#define RTC_CNTL_BROWN_OUT_ENA (BIT(30)) -#define RTC_CNTL_BROWN_OUT_ENA_M (BIT(30)) -#define RTC_CNTL_BROWN_OUT_ENA_V 0x1 -#define RTC_CNTL_BROWN_OUT_ENA_S 30 - -/* RTC_CNTL_DBROWN_OUT_THRES : R/W ;bitpos:[29:27] ;default: 3'b010 ; */ - -/* Description: brown out threshold */ - -#define RTC_CNTL_DBROWN_OUT_THRES 0x00000007 -#define RTC_CNTL_DBROWN_OUT_THRES_M ((RTC_CNTL_DBROWN_OUT_THRES_V)<<(RTC_CNTL_DBROWN_OUT_THRES_S)) -#define RTC_CNTL_DBROWN_OUT_THRES_V 0x7 -#define RTC_CNTL_DBROWN_OUT_THRES_S 27 - -/* RTC_CNTL_BROWN_OUT_RST_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */ - -/* Description: enable brown out reset */ - -#define RTC_CNTL_BROWN_OUT_RST_ENA (BIT(26)) -#define RTC_CNTL_BROWN_OUT_RST_ENA_M (BIT(26)) -#define RTC_CNTL_BROWN_OUT_RST_ENA_V 0x1 -#define RTC_CNTL_BROWN_OUT_RST_ENA_S 26 - -/* RTC_CNTL_BROWN_OUT_RST_WAIT : R/W ;bitpos:[25:16] ;default: 10'h3ff ; */ - -/* Description: brown out reset wait cycles */ - -#define RTC_CNTL_BROWN_OUT_RST_WAIT 0x000003FF -#define RTC_CNTL_BROWN_OUT_RST_WAIT_M ((RTC_CNTL_BROWN_OUT_RST_WAIT_V)<<(RTC_CNTL_BROWN_OUT_RST_WAIT_S)) -#define RTC_CNTL_BROWN_OUT_RST_WAIT_V 0x3FF -#define RTC_CNTL_BROWN_OUT_RST_WAIT_S 16 - -/* RTC_CNTL_BROWN_OUT_PD_RF_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ - -/* Description: enable power down RF when brown out happens */ - -#define RTC_CNTL_BROWN_OUT_PD_RF_ENA (BIT(15)) -#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_M (BIT(15)) -#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_V 0x1 -#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_S 15 - -/* RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ - -/* Description: enable close flash when brown out happens */ - -#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA (BIT(14)) -#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_M (BIT(14)) -#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_V 0x1 -#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_S 14 - -#define RTC_MEM_CONF (DR_REG_RTCCNTL_BASE + 0x40 * 4) -#define RTC_MEM_CRC_FINISH (BIT(31)) -#define RTC_MEM_CRC_FINISH_M (BIT(31)) -#define RTC_MEM_CRC_FINISH_V 0x1 -#define RTC_MEM_CRC_FINISH_S (31) -#define RTC_MEM_CRC_LEN (0x7ff) -#define RTC_MEM_CRC_LEN_M ((RTC_MEM_CRC_LEN_V)<<(RTC_MEM_CRC_LEN_S)) -#define RTC_MEM_CRC_LEN_V (0x7ff) -#define RTC_MEM_CRC_LEN_S (20) -#define RTC_MEM_CRC_ADDR (0x7ff) -#define RTC_MEM_CRC_ADDR_M ((RTC_MEM_CRC_ADDR_V)<<(RTC_MEM_CRC_ADDR_S)) -#define RTC_MEM_CRC_ADDR_V (0x7ff) -#define RTC_MEM_CRC_ADDR_S (9) -#define RTC_MEM_CRC_START (BIT(8)) -#define RTC_MEM_CRC_START_M (BIT(8)) -#define RTC_MEM_CRC_START_V 0x1 -#define RTC_MEM_CRC_START_S (8) -#define RTC_MEM_PID_CONF (0xff) -#define RTC_MEM_PID_CONF_M (0xff) -#define RTC_MEM_PID_CONF_V (0xff) -#define RTC_MEM_PID_CONF_S (0) - -#define RTC_MEM_CRC_RES (DR_REG_RTCCNTL_BASE + 0x41 * 4) - -#define RTC_CNTL_DATE_REG (DR_REG_RTCCNTL_BASE + 0x13c) - -/* RTC_CNTL_CNTL_DATE : R/W ;bitpos:[27:0] ;default: 28'h1604280 ; */ - -/* Description: */ - -#define RTC_CNTL_CNTL_DATE 0x0FFFFFFF -#define RTC_CNTL_CNTL_DATE_M ((RTC_CNTL_CNTL_DATE_V)<<(RTC_CNTL_CNTL_DATE_S)) -#define RTC_CNTL_CNTL_DATE_V 0xFFFFFFF -#define RTC_CNTL_CNTL_DATE_S 0 -#define RTC_CNTL_RTC_CNTL_DATE_VERSION 0x1604280 - -/* Useful groups of RTC_CNTL_DIG_PWC_REG bits */ - -#define RTC_CNTL_CPU_ROM_RAM_PD_EN \ - (RTC_CNTL_INTER_RAM4_PD_EN | RTC_CNTL_INTER_RAM3_PD_EN |\ - RTC_CNTL_INTER_RAM2_PD_EN | RTC_CNTL_INTER_RAM1_PD_EN |\ - RTC_CNTL_INTER_RAM0_PD_EN | RTC_CNTL_ROM0_PD_EN) -#define RTC_CNTL_CPU_ROM_RAM_FORCE_PU \ - (RTC_CNTL_INTER_RAM4_FORCE_PU | RTC_CNTL_INTER_RAM3_FORCE_PU |\ - RTC_CNTL_INTER_RAM2_FORCE_PU | RTC_CNTL_INTER_RAM1_FORCE_PU |\ - RTC_CNTL_INTER_RAM0_FORCE_PU | RTC_CNTL_ROM0_FORCE_PU) -#define RTC_CNTL_CPU_ROM_RAM_FORCE_PD \ - (RTC_CNTL_INTER_RAM4_FORCE_PD | RTC_CNTL_INTER_RAM3_FORCE_PD |\ - RTC_CNTL_INTER_RAM2_FORCE_PD | RTC_CNTL_INTER_RAM1_FORCE_PD |\ - RTC_CNTL_INTER_RAM0_FORCE_PD | RTC_CNTL_ROM0_FORCE_PD - -/* Useful groups of RTC_CNTL_PWC_REG bits */ - -#define RTC_CNTL_MEM_FORCE_ISO \ - (RTC_CNTL_SLOWMEM_FORCE_ISO | RTC_CNTL_FASTMEM_FORCE_ISO) -#define RTC_CNTL_MEM_FORCE_NOISO \ - (RTC_CNTL_SLOWMEM_FORCE_NOISO | RTC_CNTL_FASTMEM_FORCE_NOISO) -#define RTC_CNTL_MEM_PD_EN \ - (RTC_CNTL_SLOWMEM_PD_EN | RTC_CNTL_FASTMEM_PD_EN) -#define RTC_CNTL_MEM_FORCE_PU \ - (RTC_CNTL_SLOWMEM_FORCE_PU | RTC_CNTL_FASTMEM_FORCE_PU) -#define RTC_CNTL_MEM_FORCE_PD \ - (RTC_CNTL_SLOWMEM_FORCE_PD | RTC_CNTL_FASTMEM_FORCE_PD) -#define RTC_CNTL_MEM_FOLW_CPU \ - (RTC_CNTL_SLOWMEM_FOLW_CPU | RTC_CNTL_FASTMEM_FOLW_CPU) -#define RTC_CNTL_MEM_FORCE_LPU \ - (RTC_CNTL_SLOWMEM_FORCE_LPU | RTC_CNTL_FASTMEM_FORCE_LPU) -#define RTC_CNTL_MEM_FORCE_LPD \ - (RTC_CNTL_SLOWMEM_FORCE_LPD | RTC_CNTL_FASTMEM_FORCE_LPD) - -/* Useful groups of RTC_CNTL_DIG_ISO_REG bits */ - -#define RTC_CNTL_CPU_ROM_RAM_FORCE_ISO \ - (RTC_CNTL_INTER_RAM4_FORCE_ISO | RTC_CNTL_INTER_RAM3_FORCE_ISO |\ - RTC_CNTL_INTER_RAM2_FORCE_ISO | RTC_CNTL_INTER_RAM1_FORCE_ISO |\ - RTC_CNTL_INTER_RAM0_FORCE_ISO | RTC_CNTL_ROM0_FORCE_ISO) -#define RTC_CNTL_CPU_ROM_RAM_FORCE_NOISO \ - (RTC_CNTL_INTER_RAM4_FORCE_NOISO | RTC_CNTL_INTER_RAM3_FORCE_NOISO |\ - RTC_CNTL_INTER_RAM2_FORCE_NOISO | RTC_CNTL_INTER_RAM1_FORCE_NOISO |\ - RTC_CNTL_INTER_RAM0_FORCE_NOISO | RTC_CNTL_ROM0_FORCE_NOISO) - -/* Deep sleep (power down digital domain) */ - -#define RTC_SLEEP_PD_DIG BIT(0) - -/* Power down RTC peripherals */ - -#define RTC_SLEEP_PD_RTC_PERIPH BIT(1) - -/* Power down RTC SLOW memory */ - -#define RTC_SLEEP_PD_RTC_SLOW_MEM BIT(2) - -/* Power down RTC FAST memory */ - -#define RTC_SLEEP_PD_RTC_FAST_MEM BIT(3) - -/* RTC FAST and SLOW memories are automatically - * powered up and down along with the CPU - */ - -#define RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU BIT(4) - -/* Power down VDDSDIO regulator */ - -#define RTC_SLEEP_PD_VDDSDIO BIT(5) - -/* Power down main XTAL */ - -#define RTC_SLEEP_PD_XTAL BIT(6) - -/* RTC_CNTL_WDT_STGX : */ - -/* description: stage action selection values */ - -#define RTC_WDT_STG_SEL_OFF 0 -#define RTC_WDT_STG_SEL_INT 1 -#define RTC_WDT_STG_SEL_RESET_CPU 2 -#define RTC_WDT_STG_SEL_RESET_SYSTEM 3 -#define RTC_WDT_STG_SEL_RESET_RTC 4 - -/* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, - * RTC_CNTL_DBIAS_SLP, RTC_CNTL_DIG_DBIAS_WAK, - * RTC_CNTL_DIG_DBIAS_SLP values. Valid if RTC_CNTL_DBG_ATTEN is 0. - */ - -#define RTC_CNTL_DBIAS_0V90 0 -#define RTC_CNTL_DBIAS_0V95 1 -#define RTC_CNTL_DBIAS_1V00 2 -#define RTC_CNTL_DBIAS_1V05 3 -#define RTC_CNTL_DBIAS_1V10 4 -#define RTC_CNTL_DBIAS_1V15 5 -#define RTC_CNTL_DBIAS_1V20 6 -#define RTC_CNTL_DBIAS_1V25 7 - -#endif /* __ARCH_XTENSA_SRC_ESP32_HARDWARE_ESP32_RTCCNTL_H */ diff --git a/arch/xtensa/src/esp32/hardware/esp32_soc.h b/arch/xtensa/src/esp32/hardware/esp32_soc.h index 79f5fefa659d6..b00a0a00d80a0 100644 --- a/arch/xtensa/src/esp32/hardware/esp32_soc.h +++ b/arch/xtensa/src/esp32/hardware/esp32_soc.h @@ -30,12 +30,12 @@ #include #include -#include "xtensa_attr.h" -#include "hardware/esp32_efuse.h" - #include #include "soc/soc.h" +#include "soc/efuse_reg.h" +#include "soc/hwcrypto_reg.h" +#include "esp_attr.h" /**************************************************************************** * Pre-processor Definitions @@ -248,59 +248,6 @@ extern int rom_i2c_writereg(int block, int block_id, int reg_add, #define RTC_CNTL_STORE4_REG (DR_REG_RTCCNTL_BASE + 0xb0) #define RTC_XTAL_FREQ_REG RTC_CNTL_STORE4_REG -/* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP, - * RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values. - * Valid if RTC_CNTL_DBG_ATTEN is 0. - */ - -#define RTC_CNTL_DBIAS_1V00 2 -#define RTC_CNTL_DBIAS_1V10 4 -#define RTC_CNTL_DBIAS_1V25 7 - -/* RTC_CNTL_DIG_DBIAS_WAK : R/W ;bitpos:[13:11] ;default: 3'd4 ; */ - -#define RTC_CNTL_DIG_DBIAS_WAK 0x00000007 -#define RTC_CNTL_DIG_DBIAS_WAK_M ((RTC_CNTL_DIG_DBIAS_WAK_V) << (RTC_CNTL_DIG_DBIAS_WAK_S)) -#define RTC_CNTL_DIG_DBIAS_WAK_V 0x7 -#define RTC_CNTL_DIG_DBIAS_WAK_S 11 - -/* RTC_CNTL_SOC_CLK_SEL : R/W ;bitpos:[28:27] ;default: 2'd0 ; - * description: SOC clock sel. 0: XTAL 1: PLL 2: CK8M 3: APLL - */ - -#define RTC_CNTL_SOC_CLK_SEL 0x00000003 -#define RTC_CNTL_SOC_CLK_SEL_M ((RTC_CNTL_SOC_CLK_SEL_V) << (RTC_CNTL_SOC_CLK_SEL_S)) -#define RTC_CNTL_SOC_CLK_SEL_V 0x3 -#define RTC_CNTL_SOC_CLK_SEL_S 27 -#define RTC_CNTL_SOC_CLK_SEL_XTL 0 -#define RTC_CNTL_SOC_CLK_SEL_PLL 1 -#define RTC_CNTL_SOC_CLK_SEL_8M 2 -#define RTC_CNTL_SOC_CLK_SEL_APLL 3 - -/* Core voltage needs to be increased in two cases: - * 1. running at 240 MHz - * 2. running with 80MHz Flash frequency - * There is a record in efuse which indicates the - * proper voltage for these two cases. - */ - -#define RTC_CNTL_DBIAS_HP_VOLT (RTC_CNTL_DBIAS_1V25 - \ - (REG_GET_FIELD(EFUSE_BLK0_RDATA5_REG, \ - EFUSE_RD_VOL_LEVEL_HP_INV))) - -#ifdef CONFIG_ESP32_FLASH_FREQ_80M -#define DIG_DBIAS_80M_160M RTC_CNTL_DBIAS_HP_VOLT -#else -#define DIG_DBIAS_80M_160M RTC_CNTL_DBIAS_1V10 -#endif -#define DIG_DBIAS_240M RTC_CNTL_DBIAS_HP_VOLT -#define DIG_DBIAS_XTAL RTC_CNTL_DBIAS_1V10 -#define DIG_DBIAS_2M RTC_CNTL_DBIAS_1V00 - -#define DIG_DBIAS_240M RTC_CNTL_DBIAS_HP_VOLT -#define DIG_DBIAS_XTAL RTC_CNTL_DBIAS_1V10 -#define DIG_DBIAS_2M RTC_CNTL_DBIAS_1V00 - #define DELAY_PLL_DBIAS_RAISE 3 #define DELAY_PLL_ENABLE_WITH_150K 80 #define DELAY_PLL_ENABLE_WITH_32K 160 diff --git a/arch/xtensa/src/esp32s2/Kconfig b/arch/xtensa/src/esp32s2/Kconfig index 75d3b2869a4aa..06cb50a61bc16 100644 --- a/arch/xtensa/src/esp32s2/Kconfig +++ b/arch/xtensa/src/esp32s2/Kconfig @@ -233,7 +233,7 @@ config ESP32S2_I2S default n select I2S select ARCH_DMA - select ESP32S2_GPIO_IRQ + select ESPRESSIF_GPIO_IRQ select ESPRESSIF_I2S0 ---help--- This is a deprecated Kconfig macro. Its kept for retrocompatibility only. @@ -550,9 +550,11 @@ config ESP32S2_LEDC Enable support to PWM on ESP32S2 using LEDC peripheral. config ESP32S2_RT_TIMER - bool "Real-time Timer" - select ESP32S2_TIMER + bool "Real-Time Timer" default n + select ESPRESSIF_HR_TIMER + ---help--- + Deprecated: Use ESPRESSIF_HR_TIMER instead. endmenu # ESP32-S2 Peripheral Selection @@ -577,8 +579,10 @@ endmenu # Memory Configuration config ESP32S2_GPIO_IRQ bool "GPIO pin interrupts" + select ESPRESSIF_GPIO_IRQ ---help--- - Enable support for interrupting GPIO pins. + This is a deprecated Kconfig macro. Its kept for retrocompatibility only. + Use "CONFIG_ESPRESSIF_GPIO_IRQ" instead. config ESP32S2_RTCIO_IRQ bool "RTC IO interrupts" @@ -606,7 +610,7 @@ config ESP32S2_SPI2_SLAVE bool "SPI2 Slave mode" default n depends on SPI_SLAVE && ESP32S2_SPI2 - select ESP32S2_GPIO_IRQ + select ESPRESSIF_GPIO_IRQ ---help--- Configure SPI2 to operate in Slave mode. @@ -619,7 +623,7 @@ config ESP32S2_SPI3_SLAVE bool "SPI3 Slave mode" default n depends on SPI_SLAVE && ESP32S2_SPI3 - select ESP32S2_GPIO_IRQ + select ESPRESSIF_GPIO_IRQ ---help--- Configure SPI3 to operate in Slave mode. diff --git a/arch/xtensa/src/esp32s2/Make.defs b/arch/xtensa/src/esp32s2/Make.defs index a467f375aef50..91e982e226db1 100644 --- a/arch/xtensa/src/esp32s2/Make.defs +++ b/arch/xtensa/src/esp32s2/Make.defs @@ -28,13 +28,17 @@ HEAD_CSRC = esp32s2_start.c esp32s2_wdt.c # Required ESP32-S2 files (arch/xtensa/src/esp32s2) -CHIP_CSRCS = esp32s2_allocateheap.c esp32s2_clockconfig.c esp32s2_irq.c -CHIP_CSRCS += esp32s2_gpio.c esp32s2_rtc_gpio.c esp32s2_region.c esp32s2_user.c -CHIP_CSRCS += esp32s2_timerisr.c esp32s2_lowputc.c esp32s2_systemreset.c +CHIP_CSRCS = esp32s2_allocateheap.c +CHIP_CSRCS += esp32s2_rtc_gpio.c esp32s2_region.c esp32s2_user.c +CHIP_CSRCS += esp32s2_lowputc.c esp32s2_systemreset.c CHIP_CSRCS += esp32s2_dma.c esp32s2_libc_stubs.c # Configuration-dependent ESP32-S2 files +ifneq ($(CONFIG_SCHED_TICKLESS),y) +CHIP_CSRCS += esp32s2_timerisr.c +endif + ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y) CHIP_CSRCS += esp32s2_idle.c endif @@ -95,10 +99,6 @@ ifeq ($(CONFIG_ESP32S2_FREERUN),y) CHIP_CSRCS += esp32s2_freerun.c endif -ifeq ($(CONFIG_ESP32S2_RT_TIMER),y) -CHIP_CSRCS += esp32s2_rt_timer.c -endif - ifeq ($(CONFIG_ESP32S2_TOUCH),y) CHIP_CSRCS += esp32s2_touch.c endif @@ -115,12 +115,6 @@ CHIP_CSRCS += esp32s2_spiram.c CHIP_CSRCS += esp32s2_psram.c endif -CHIP_CSRCS += esp32s2_rtc.c - -ifeq ($(CONFIG_RTC_DRIVER),y) -CHIP_CSRCS += esp32s2_rtc_lowerhalf.c -endif - ifeq ($(CONFIG_ESPRESSIF_WIFI),y) CHIP_CSRCS += esp32s2_wifi_adapter.c endif @@ -133,13 +127,20 @@ endif ESP_HAL_3RDPARTY_REPO = esp-hal-3rdparty ifndef ESP_HAL_3RDPARTY_VERSION - ESP_HAL_3RDPARTY_VERSION = 6b4f19b48c5ba0e847511b5b21584e797ec795dc + ESP_HAL_3RDPARTY_VERSION = 6c272b562a73107a852d44b9c6fb5df57245cbd7 endif ifndef ESP_HAL_3RDPARTY_URL ESP_HAL_3RDPARTY_URL = https://github.com/espressif/esp-hal-3rdparty.git endif +ifndef DISABLE_GIT_DEPTH +ifndef GIT_DEPTH + GIT_DEPTH=1 +endif + GIT_DEPTH_PARAMETER = --depth=$(GIT_DEPTH) +endif + # When set USE_NXTMPDIR_ESP_REPO_DIRECTLY=y, will directly use esp-hal-3rdparty # under nxtmpdir without CHECK_COMMITSHA, reset, checkout and update. @@ -166,13 +167,16 @@ chip/$(ESP_HAL_3RDPARTY_REPO): $(Q) echo "Cloning Espressif HAL for 3rd Party Platforms" $(Q) $(call CLONE_ESP_HAL_3RDPARTY_REPO) ifneq ($(USE_NXTMPDIR_ESP_REPO_DIRECTLY),y) + $(Q) echo "Espressif HAL for 3rd Party Platforms: cleaning current repository..." + $(Q) git -C chip/$(ESP_HAL_3RDPARTY_REPO) clean -ffdx + $(Q) git -C chip/$(ESP_HAL_3RDPARTY_REPO) reset --quiet --hard --recurse-submodules || true $(Q) echo "Espressif HAL for 3rd Party Platforms: ${ESP_HAL_3RDPARTY_VERSION}" $(Q) git -C chip/$(ESP_HAL_3RDPARTY_REPO) checkout --quiet $(ESP_HAL_3RDPARTY_VERSION) endif # Silent preprocessor warnings -CFLAGS += -Wno-undef -Wno-unused-variable -fno-jump-tables -fno-tree-switch-conversion +CFLAGS += -Wno-undef -Wno-unused-variable -fno-jump-tables -fno-tree-switch-conversion -Wno-deprecated-declarations # Enable strict volatile bitfield access @@ -203,3 +207,5 @@ endif distclean:: $(call DELDIR,chip/$(ESP_HAL_3RDPARTY_REPO)) $(call DELFILE,../../../vefuse.bin) + +INCLUDES += ${INCDIR_PREFIX}$(ARCH_SRCDIR)$(DELIM)common$(DELIM)espressif diff --git a/arch/xtensa/src/esp32s2/esp32s2_clockconfig.c b/arch/xtensa/src/esp32s2/esp32s2_clockconfig.c deleted file mode 100644 index 1fca78e0ac34f..0000000000000 --- a/arch/xtensa/src/esp32s2/esp32s2_clockconfig.c +++ /dev/null @@ -1,283 +0,0 @@ -/**************************************************************************** - * arch/xtensa/src/esp32s2/esp32s2_clockconfig.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include "xtensa.h" -#include "esp_attr.h" -#include "hardware/esp32s2_soc.h" -#include "hardware/esp32s2_uart.h" -#include "hardware/esp32s2_rtccntl.h" -#include "hardware/esp32s2_system.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef CONFIG_ESP_CONSOLE_UART_NUM -#define CONFIG_ESP_CONSOLE_UART_NUM 0 -#endif - -#define DEFAULT_CPU_FREQ 80 - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -enum cpu_freq_e -{ - CPU_80M = 0, - CPU_160M = 1, - CPU_240M = 2, -}; - -enum cpu_clksrc_e -{ - XTAL_CLK, - PLL_CLK, - RTC8M_CLK, - APLL_CLK -}; - -enum pll_freq_e -{ - PLL_320, - PLL_480 -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32s2_cpuclksrc - * - * Description: - * Select a clock source for CPU clock. - * - * Input Parameters: - * src - Any source from cpu_clksrc_e. - * - * Returned Value: - * None - * - ****************************************************************************/ - -static inline void esp32s2_cpuclksrc(enum cpu_clksrc_e src) -{ - uint32_t value; - value = VALUE_TO_FIELD(src, SYSTEM_SOC_CLK_SEL); - modifyreg32(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL_M, value); -} - -/**************************************************************************** - * Name: esp32s2_cpudiv - * - * Description: - * Select a divider for the CPU clk. - * NOTE: The divider is not necessarily the real divisor. See TRM for the - * equivalences. - * - * Input Parameters: - * divider - A value between 0 to 2. - * - * Returned Value: - * None - * - ****************************************************************************/ - -static inline void esp32s2_cpudiv(uint8_t divider) -{ - uint32_t value; - value = VALUE_TO_FIELD(divider, SYSTEM_CPUPERIOD_SEL); - modifyreg32(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPUPERIOD_SEL_M, value); -} - -/**************************************************************************** - * Name: esp32s2_pllfreqsel - * - * Description: - * Select the PLL frequency. - * - * Input Parameters: - * freq - Any clock from enum pll_freq_e - * - * Returned Value: - * None - ****************************************************************************/ - -static inline void esp32s2_pllfreqsel(enum pll_freq_e freq) -{ - uint32_t value; - value = VALUE_TO_FIELD(freq, SYSTEM_PLL_FREQ_SEL); - modifyreg32(SYSTEM_CPU_PER_CONF_REG, SYSTEM_PLL_FREQ_SEL_M, value); -} - -/**************************************************************************** - * Name: esp32s2_uart_tx_wait_idle - * - * Description: - * Wait until uart tx full empty and the last char send ok. - * - * Input Parameters: - * uart_no - 0 for UART0, 1 for UART1, 2 for UART2 - * - * Returned Value: - * None - * - ****************************************************************************/ - -static inline void esp32s2_uart_tx_wait_idle(uint8_t uart_no) -{ - uint32_t status; - do - { - status = getreg32(UART_STATUS_REG(uart_no)); - - /* tx count is non-zero */ - } - while ((status & UART_TXFIFO_CNT_M) != 0); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -extern uint32_t g_ticks_per_us; - -/**************************************************************************** - * Name: esp32s2_update_cpu_freq - * - * Description: - * Set the real CPU ticks per us to the ets, so that ets_delay_us - * will be accurate. Call this function when CPU frequency is changed. - * - * Input Parameters: - * ticks_per_us - CPU ticks per us - * - * Returned Value: - * None - * - ****************************************************************************/ - -void IRAM_ATTR esp32s2_update_cpu_freq(uint32_t ticks_per_us) -{ - /* Update scale factors used by esp_rom_delay_us */ - - g_ticks_per_us = ticks_per_us; -} - -/**************************************************************************** - * Name: esp32s2_set_cpu_freq - * - * Description: - * Switch to one of PLL-based frequencies. - * - * Input Parameters: - * cpu_freq_mhz - Target CPU frequency - * - * Returned Value: - * None - * - ****************************************************************************/ - -void IRAM_ATTR esp32s2_set_cpu_freq(int cpu_freq_mhz) -{ - uint32_t dbias; - uint32_t value; - switch (cpu_freq_mhz) - { - case 80: - /* 80 MHz is obtained from the 480 MHz PLL. - * In this case CPU_CLK = PLL_CLK / 6. Config the PLL as 480 MHz - * with a 6 divider and set the source clock as PLL_CLK. - */ - - dbias = DIG_DBIAS_80M_160M; - esp32s2_cpudiv(0); - break; - - case 160: - /* 160 MHz is obtained from the 480 MHz PLL. - * In this case CPU_CLK = PLL_CLK / 3. Config the PLL as 480 MHz - * with a 3 divider and set the source clock as PLL_CLK. - */ - - dbias = DIG_DBIAS_80M_160M; - esp32s2_cpudiv(1); - break; - - case 240: - /* 160 MHz is obtained from the 480 MHz PLL. - * In this case CPU_CLK = PLL_CLK / 2. Config the PLL as 480 MHz - * with a 2 divider and set the source clock as PLL_CLK. - */ - - dbias = DIG_DBIAS_240M; - esp32s2_cpudiv(2); - break; - - default: - - /* Unsupported clock config. */ - - return; - } - - value = (((80 * MHZ) >> 12) & UINT16_MAX) | - ((((80 * MHZ) >> 12) & UINT16_MAX) << 16); - esp32s2_pllfreqsel(PLL_480); - REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, dbias); - esp32s2_cpuclksrc(PLL_CLK); - putreg32(value, RTC_APB_FREQ_REG); - esp32s2_update_cpu_freq(cpu_freq_mhz); -} - -/**************************************************************************** - * Name: esp32s2_clockconfig - * - * Description: - * Called to initialize the ESP32S2. This does whatever setup is needed to - * put the SoC in a usable state. This includes the initialization of - * clocking using the settings in board.h. - * - ****************************************************************************/ - -void esp32s2_clockconfig(void) -{ - /* Wait for the TX FIFO to unload data */ - -#if defined(CONFIG_UART0_SERIAL_CONSOLE) - esp32s2_uart_tx_wait_idle(0); -#elif defined(CONFIG_UART1_SERIAL_CONSOLE) - esp32s2_uart_tx_wait_idle(1); -#endif - - /* Configure the CPU frequency */ - - esp32s2_set_cpu_freq(CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ); -} diff --git a/arch/xtensa/src/esp32s2/esp32s2_clockconfig.h b/arch/xtensa/src/esp32s2/esp32s2_clockconfig.h deleted file mode 100644 index 3e9b8d4637c95..0000000000000 --- a/arch/xtensa/src/esp32s2/esp32s2_clockconfig.h +++ /dev/null @@ -1,82 +0,0 @@ -/**************************************************************************** - * arch/xtensa/src/esp32s2/esp32s2_clockconfig.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_CLOCKCONFIG_H -#define __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_CLOCKCONFIG_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include "esp_private/esp_clk.h" - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32s2_update_cpu_freq - * - * Description: - * Set the real CPU ticks per us to the ets, so that ets_delay_us - * will be accurate. Call this function when CPU frequency is changed. - * - * Input Parameters: - * ticks_per_us - CPU ticks per us - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32s2_update_cpu_freq(uint32_t ticks_per_us); - -/**************************************************************************** - * Name: esp32s2_set_cpu_freq - * - * Description: - * Switch to one of PLL-based frequencies. - * Current frequency can be XTAL or PLL. - * - * Input Parameters: - * cpu_freq_mhz - new CPU frequency - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32s2_set_cpu_freq(int cpu_freq_mhz); - -/**************************************************************************** - * Name: esp32s2_clockconfig - * - * Description: - * Called to initialize the ESP32S2. This does whatever setup is needed to - * put the SoC in a usable state. This includes the initialization of - * clocking using the settings in board.h. - * - ****************************************************************************/ - -void esp32s2_clockconfig(void); - -#endif /* __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_CLOCKCONFIG_H */ diff --git a/arch/xtensa/src/esp32s2/esp32s2_freerun.c b/arch/xtensa/src/esp32s2/esp32s2_freerun.c index 5eab529e0d485..f4145febf82e7 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_freerun.c +++ b/arch/xtensa/src/esp32s2/esp32s2_freerun.c @@ -36,8 +36,6 @@ #include #include "esp32s2_freerun.h" -#include "esp32s2_clockconfig.h" -#include "esp32s2_gpio.h" #ifdef CONFIG_ESP32S2_FREERUN diff --git a/arch/xtensa/src/esp32s2/esp32s2_gpio.c b/arch/xtensa/src/esp32s2/esp32s2_gpio.c deleted file mode 100644 index 4463899529224..0000000000000 --- a/arch/xtensa/src/esp32s2/esp32s2_gpio.c +++ /dev/null @@ -1,582 +0,0 @@ -/**************************************************************************** - * arch/xtensa/src/esp32s2/esp32s2_gpio.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include - -#include "xtensa.h" - -#include "soc/soc_caps.h" - -#include "esp32s2_gpio.h" -#include "esp32s2_irq.h" -#include "hardware/esp32s2_gpio.h" -#include "hardware/esp32s2_iomux.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define ESP32S2_NPINS 47 - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_ESP32S2_GPIO_IRQ -static int g_gpio_cpuint; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: is_valid_gpio - * - * Description: - * Check if the requested pin is a valid GPIO pin. - * - * Input Parameters: - * pin - Pin to be checked for validity. - * - * Returned Value: - * True if the requested pin is a valid GPIO pin, false otherwise. - * - ****************************************************************************/ - -static inline bool is_valid_gpio(uint32_t pin) -{ - /* ESP32-S2 has 43 GPIO pins numbered from 0 to 21 and 26 to 46 */ - - return pin <= 21 || (pin >= 26 && pin < ESP32S2_NPINS); -} - -/**************************************************************************** - * Name: gpio_dispatch - * - * Description: - * Second level dispatch for GPIO interrupt handling. - * - * Input Parameters: - * irq - GPIO IRQ number. - * status - Value from the GPIO interrupt status clear register. - * regs - Saved CPU context. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -#ifdef CONFIG_ESP32S2_GPIO_IRQ -static void gpio_dispatch(int irq, uint32_t status, uint32_t *regs) -{ - uint32_t mask; - - /* Check each bit in the status register */ - - for (int i = 0; i < 32 && status != 0; i++) - { - /* Check if there is an interrupt pending for this pin */ - - mask = UINT32_C(1) << i; - if ((status & mask) != 0) - { - /* Yes... perform the second level dispatch */ - - irq_dispatch(irq + i, regs); - - /* Clear the bit in the status so that we might execute this loop - * sooner. - */ - - status &= ~mask; - } - } -} -#endif - -/**************************************************************************** - * Name: gpio_interrupt - * - * Description: - * GPIO interrupt handler. - * - * Input Parameters: - * irq - Identifier of the interrupt request. - * context - Context data from the ISR. - * arg - Opaque pointer to the internal driver state structure. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -#ifdef CONFIG_ESP32S2_GPIO_IRQ -static int gpio_interrupt(int irq, void *context, void *arg) -{ - uint32_t status; - - /* Read and clear the lower GPIO interrupt status */ - - status = getreg32(GPIO_STATUS_REG); - putreg32(status, GPIO_STATUS_W1TC_REG); - - /* Dispatch pending interrupts in the lower GPIO status register */ - - gpio_dispatch(ESP32S2_FIRST_GPIOIRQ, status, (uint32_t *)context); - - /* Read and clear the upper GPIO interrupt status */ - - status = getreg32(GPIO_STATUS1_REG) & GPIO_STATUS1_INTERRUPT_M; - putreg32(status, GPIO_STATUS1_W1TC_REG); - - /* Dispatch pending interrupts in the lower GPIO status register */ - - gpio_dispatch(ESP32S2_FIRST_GPIOIRQ + 32, status, (uint32_t *)context); - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32s2_configgpio - * - * Description: - * Configure a GPIO pin based on encoded pin attributes. - * - * Input Parameters: - * pin - GPIO pin to be configured. - * attr - Attributes to be configured for the selected GPIO pin. - * The following attributes are accepted: - * - Direction (OUTPUT or INPUT) - * - Pull (PULLUP, PULLDOWN or OPENDRAIN) - * - Function (if not provided, assume function GPIO by - * default) - * - Drive strength (if not provided, assume DRIVE_2 by - * default) - * - * Returned Value: - * Zero (OK) on success, or -1 (ERROR) in case of failure. - * - ****************************************************************************/ - -int esp32s2_configgpio(int pin, gpio_pinattr_t attr) -{ - uintptr_t regaddr; - uint32_t func; - uint32_t cntrl; - uint32_t pin2func; - - DEBUGASSERT(is_valid_gpio(pin)); - - func = 0; - cntrl = 0; - - /* Handle input pins */ - - if ((attr & INPUT) != 0) - { - if (pin < 32) - { - putreg32(UINT32_C(1) << pin, GPIO_ENABLE_W1TC_REG); - } - else - { - putreg32(UINT32_C(1) << (pin - 32), GPIO_ENABLE1_W1TC_REG); - } - - /* Input enable */ - - func |= FUN_IE; - - if ((attr & PULLUP) != 0) - { - func |= FUN_PU; - } - else if ((attr & PULLDOWN) != 0) - { - func |= FUN_PD; - } - } - - /* Handle output pins */ - - if ((attr & OUTPUT) != 0) - { - if (pin < 32) - { - putreg32(UINT32_C(1) << pin, GPIO_ENABLE_W1TS_REG); - } - else - { - putreg32(UINT32_C(1) << (pin - 32), GPIO_ENABLE1_W1TS_REG); - } - } - - /* Configure the pad's function */ - - if ((attr & FUNCTION_MASK) != 0) - { - uint32_t val = ((attr & FUNCTION_MASK) >> FUNCTION_SHIFT) - 1; - func |= val << MCU_SEL_S; - } - else - { - /* Function not provided, assuming function GPIO by default */ - - func |= (uint32_t)(PIN_FUNC_GPIO << MCU_SEL_S); - } - - /* Configure the pad's drive strength */ - - if ((attr & DRIVE_MASK) != 0) - { - uint32_t val = ((attr & DRIVE_MASK) >> DRIVE_SHIFT) - 1; - func |= val << FUN_DRV_S; - } - else - { - /* Drive strength not provided, assuming strength 2 by default */ - - func |= UINT32_C(2) << FUN_DRV_S; - } - - if ((attr & OPEN_DRAIN) != 0) - { - cntrl |= UINT32_C(1) << GPIO_PIN_PAD_DRIVER_S; - } - - pin2func = (pin + 1) * 4; - regaddr = DR_REG_IO_MUX_BASE + pin2func; - putreg32(func, regaddr); - - regaddr = GPIO_REG(pin); - putreg32(cntrl, regaddr); - return OK; -} - -/**************************************************************************** - * Name: esp32s2_gpiowrite - * - * Description: - * Write one or zero to the selected GPIO pin. - * - * Input Parameters: - * pin - GPIO pin to be written. - * value - Value to be written to the GPIO pin. True will output - * 1 (one) to the GPIO, while false will output 0 (zero). - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp32s2_gpiowrite(int pin, bool value) -{ - DEBUGASSERT(is_valid_gpio(pin)); - - if (value) - { - if (pin < 32) - { - putreg32(UINT32_C(1) << pin, GPIO_OUT_W1TS_REG); - } - else - { - putreg32(UINT32_C(1) << (pin - 32), GPIO_OUT1_W1TS_REG); - } - } - else - { - if (pin < 32) - { - putreg32(UINT32_C(1) << pin, GPIO_OUT_W1TC_REG); - } - else - { - putreg32(UINT32_C(1) << (pin - 32), GPIO_OUT1_W1TC_REG); - } - } -} - -/**************************************************************************** - * Name: esp32s2_gpioread - * - * Description: - * Read one or zero from the selected GPIO pin. - * - * Input Parameters: - * pin - GPIO pin to be read. - * - * Returned Value: - * True in case the read value is 1 (one). If 0 (zero), then false will be - * returned. - * - ****************************************************************************/ - -bool esp32s2_gpioread(int pin) -{ - uint32_t regval; - - DEBUGASSERT(is_valid_gpio(pin)); - - if (pin < 32) - { - regval = getreg32(GPIO_IN_REG); - return ((regval >> pin) & 1) != 0; - } - else - { - regval = getreg32(GPIO_IN1_REG); - return ((regval >> (pin - 32)) & 1) != 0; - } -} - -/**************************************************************************** - * Name: esp32s2_gpioirqinitialize - * - * Description: - * Initialize logic to support a second level of interrupt decoding for - * GPIO pins. - * - * Input Parameters: - * None. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -#ifdef CONFIG_ESP32S2_GPIO_IRQ -void esp32s2_gpioirqinitialize(void) -{ - /* Setup the GPIO interrupt. */ - - g_gpio_cpuint = esp32s2_setup_irq(ESP32S2_PERIPH_GPIO_INT_PRO, - 1, ESP32S2_CPUINT_LEVEL); - DEBUGASSERT(g_gpio_cpuint >= 0); - - /* Attach and enable the interrupt handler */ - - DEBUGVERIFY(irq_attach(ESP32S2_IRQ_GPIO_INT_PRO, gpio_interrupt, NULL)); - up_enable_irq(ESP32S2_IRQ_GPIO_INT_PRO); -} -#endif - -/**************************************************************************** - * Name: esp32s2_gpioirqenable - * - * Description: - * Enable the interrupt for the specified GPIO IRQ. - * - * Input Parameters: - * irq - Identifier of the interrupt request. - * intrtype - Interrupt type, select from gpio_intrtype_t. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -#ifdef CONFIG_ESP32S2_GPIO_IRQ -void esp32s2_gpioirqenable(int irq, gpio_intrtype_t intrtype) -{ - uintptr_t regaddr; - uint32_t regval; - int pin; - - DEBUGASSERT(irq >= ESP32S2_FIRST_GPIOIRQ && irq <= ESP32S2_LAST_GPIOIRQ); - - /* Convert the IRQ number to a pin number */ - - pin = ESP32S2_IRQ2PIN(irq); - - /* Disable the GPIO interrupt during the configuration. */ - - up_disable_irq(ESP32S2_IRQ_GPIO_INT_PRO); - - /* Get the address of the GPIO PIN register for this pin */ - - regaddr = GPIO_REG(pin); - regval = getreg32(regaddr); - regval &= ~(GPIO_PIN_INT_ENA_M | GPIO_PIN_INT_TYPE_M); - - /* Set the pin ENA field */ - - regval |= GPIO_PIN_INT_ENA_M; - regval |= (uint32_t)intrtype << GPIO_PIN_INT_TYPE_S; - putreg32(regval, regaddr); - - /* Configuration done. Re-enable the GPIO interrupt. */ - - up_enable_irq(ESP32S2_IRQ_GPIO_INT_PRO); -} -#endif - -/**************************************************************************** - * Name: esp32s2_gpioirqdisable - * - * Description: - * Disable the interrupt for the specified GPIO IRQ. - * - * Input Parameters: - * irq - Identifier of the interrupt request. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -#ifdef CONFIG_ESP32S2_GPIO_IRQ -void esp32s2_gpioirqdisable(int irq) -{ - uintptr_t regaddr; - uint32_t regval; - int pin; - - DEBUGASSERT(irq >= ESP32S2_FIRST_GPIOIRQ && irq <= ESP32S2_LAST_GPIOIRQ); - - /* Convert the IRQ number to a pin number */ - - pin = ESP32S2_IRQ2PIN(irq); - - /* Disable the GPIO interrupt during the configuration. */ - - up_disable_irq(ESP32S2_IRQ_GPIO_INT_PRO); - - /* Reset the pin ENA and TYPE fields */ - - regaddr = GPIO_REG(pin); - regval = getreg32(regaddr); - regval &= ~(GPIO_PIN_INT_ENA_M | GPIO_PIN_INT_TYPE_M); - putreg32(regval, regaddr); - - /* Configuration done. Re-enable the GPIO interrupt. */ - - up_enable_irq(ESP32S2_IRQ_GPIO_INT_PRO); -} -#endif - -/**************************************************************************** - * Name: esp32s2_gpio_matrix_in - * - * Description: - * Set GPIO input to a signal. - * NOTE: one GPIO can receive inputs from several signals. - * - * Input Parameters: - * pin - GPIO pin to be configured. - * - If pin == 0x3c, cancel input to the signal, input 0 - * to signal. - * - If pin == 0x3a, input nothing to signal. - * - If pin == 0x38, cancel input to the signal, input 1 - * to signal. - * signal_idx - Signal index. - * inv - Flag indicating whether the signal is inverted. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp32s2_gpio_matrix_in(uint32_t pin, uint32_t signal_idx, bool inv) -{ - uint32_t regaddr = GPIO_FUNC0_IN_SEL_CFG_REG + (signal_idx * 4); - uint32_t regval = pin << GPIO_FUNC0_IN_SEL_S; - - if (inv) - { - regval |= GPIO_FUNC0_IN_INV_SEL; - } - - if (pin != 0x3a) - { - regval |= GPIO_SIG0_IN_SEL; - } - - putreg32(regval, regaddr); -} - -/**************************************************************************** - * Name: esp32s2_gpio_matrix_out - * - * Description: - * Set signal output to GPIO. - * NOTE: one signal can output to several GPIOs. - * - * Input Parameters: - * pin - GPIO pin to be configured. - * signal_idx - Signal index. - * - If signal_idx == 0x100, cancel output to the GPIO. - * out_inv - Flag indicating whether the signal output is inverted. - * oen_inv - Flag indicating whether the signal output enable is - * inverted. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp32s2_gpio_matrix_out(uint32_t pin, uint32_t signal_idx, - bool out_inv, bool oen_inv) -{ - uint32_t regaddr = GPIO_FUNC0_OUT_SEL_CFG_REG + (pin * 4); - uint32_t regval = signal_idx << GPIO_FUNC0_OUT_SEL_S; - - DEBUGASSERT(is_valid_gpio(pin)); - - if (pin < 32) - { - putreg32(UINT32_C(1) << pin, GPIO_ENABLE_W1TS_REG); - } - else - { - putreg32(UINT32_C(1) << (pin - 32), GPIO_ENABLE1_W1TS_REG); - } - - if (out_inv) - { - regval |= GPIO_FUNC0_OUT_INV_SEL; - } - - if (oen_inv) - { - regval |= GPIO_FUNC0_OEN_INV_SEL; - } - - putreg32(regval, regaddr); -} diff --git a/arch/xtensa/src/esp32s2/esp32s2_i2c.c b/arch/xtensa/src/esp32s2/esp32s2_i2c.c index 875fe02f19d2f..f8b625d6671e9 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_i2c.c +++ b/arch/xtensa/src/esp32s2/esp32s2_i2c.c @@ -46,9 +46,9 @@ #include -#include "esp32s2_gpio.h" +#include "espressif/esp_gpio.h" #include "esp32s2_i2c.h" -#include "esp32s2_irq.h" +#include "espressif/esp_irq.h" #include "xtensa.h" #include "hardware/esp32s2_gpio_sigmap.h" @@ -749,15 +749,15 @@ static void i2c_init(struct esp32s2_i2c_priv_s *priv) const struct esp32s2_i2c_config_s *config = priv->config; if (priv->id != ESP32S2_RTC_I2C) { - esp32s2_gpiowrite(config->scl_pin, 1); - esp32s2_configgpio(config->scl_pin, INPUT_PULLUP | OUTPUT_OPEN_DRAIN); - esp32s2_gpio_matrix_out(config->scl_pin, config->scl_outsig, 0, 0); - esp32s2_gpio_matrix_in(config->scl_pin, config->scl_insig, 0); + esp_gpiowrite(config->scl_pin, 1); + esp_configgpio(config->scl_pin, INPUT_PULLUP | OUTPUT_OPEN_DRAIN); + esp_gpio_matrix_out(config->scl_pin, config->scl_outsig, 0, 0); + esp_gpio_matrix_in(config->scl_pin, config->scl_insig, 0); - esp32s2_gpiowrite(config->sda_pin, 1); - esp32s2_configgpio(config->sda_pin, INPUT_PULLUP | OUTPUT_OPEN_DRAIN); - esp32s2_gpio_matrix_out(config->sda_pin, config->sda_outsig, 0, 0); - esp32s2_gpio_matrix_in(config->sda_pin, config->sda_insig, 0); + esp_gpiowrite(config->sda_pin, 1); + esp_configgpio(config->sda_pin, INPUT_PULLUP | OUTPUT_OPEN_DRAIN); + esp_gpio_matrix_out(config->sda_pin, config->sda_outsig, 0, 0); + esp_gpio_matrix_in(config->sda_pin, config->sda_insig, 0); /* Enable I2C hardware */ @@ -1698,8 +1698,9 @@ struct i2c_master_s *esp32s2_i2cbus_initialize(int port) /* Set up to receive peripheral interrupts on the current CPU */ - priv->cpuint = esp32s2_setup_irq(config->periph, - 1, ESP32S2_CPUINT_LEVEL); + priv->cpuint = esp_setup_irq(config->periph, + 1, ESP_IRQ_TRIGGER_LEVEL, + i2c_irq, priv); if (priv->cpuint < 0) { /* Failed to allocate a CPU interrupt of this type */ @@ -1710,16 +1711,6 @@ struct i2c_master_s *esp32s2_i2cbus_initialize(int port) return NULL; } - ret = irq_attach(config->irq, i2c_irq, priv); - if (ret != OK) - { - esp32s2_teardown_irq(config->periph, priv->cpuint); - priv->refs--; - - nxmutex_unlock(&priv->lock); - return NULL; - } - up_enable_irq(config->irq); } #endif @@ -1768,7 +1759,7 @@ int esp32s2_i2cbus_uninitialize(struct i2c_master_s *dev) { #ifndef CONFIG_I2C_POLLED up_disable_irq(priv->config->irq); - esp32s2_teardown_irq(priv->config->periph, priv->cpuint); + esp_teardown_irq(priv->config->periph, priv->cpuint); #endif i2c_deinit(priv); diff --git a/arch/xtensa/src/esp32s2/esp32s2_i2s.c b/arch/xtensa/src/esp32s2/esp32s2_i2s.c index 71df6cf021b42..94efbf8de0f05 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_i2s.c +++ b/arch/xtensa/src/esp32s2/esp32s2_i2s.c @@ -50,8 +50,8 @@ #include #include "esp32s2_i2s.h" -#include "esp32s2_gpio.h" -#include "esp32s2_irq.h" +#include "espressif/esp_gpio.h" +#include "espressif/esp_irq.h" #include "esp32s2_dma.h" #include "xtensa.h" @@ -1252,9 +1252,9 @@ static void i2s_configure(struct esp32s2_i2s_s *priv) if (priv->config->dout_pin != I2S_GPIO_UNUSED) { - esp32s2_gpiowrite(priv->config->dout_pin, 1); - esp32s2_configgpio(priv->config->dout_pin, OUTPUT_FUNCTION_2); - esp32s2_gpio_matrix_out(priv->config->dout_pin, + esp_gpiowrite(priv->config->dout_pin, 1); + esp_configgpio(priv->config->dout_pin, OUTPUT_FUNCTION_2); + esp_gpio_matrix_out(priv->config->dout_pin, priv->config->dout_outsig, 0, 0); } @@ -1262,8 +1262,8 @@ static void i2s_configure(struct esp32s2_i2s_s *priv) if (priv->config->din_pin != I2S_GPIO_UNUSED) { - esp32s2_configgpio(priv->config->din_pin, INPUT_FUNCTION_2); - esp32s2_gpio_matrix_in(priv->config->din_pin, + esp_configgpio(priv->config->din_pin, INPUT_FUNCTION_2); + esp_gpio_matrix_in(priv->config->din_pin, priv->config->din_insig, 0); } @@ -1273,14 +1273,14 @@ static void i2s_configure(struct esp32s2_i2s_s *priv) { /* For "tx + slave" mode, select TX signal index for ws and bck */ - esp32s2_gpiowrite(priv->config->ws_pin, 1); - esp32s2_configgpio(priv->config->ws_pin, INPUT_FUNCTION_2); - esp32s2_gpio_matrix_in(priv->config->ws_pin, + esp_gpiowrite(priv->config->ws_pin, 1); + esp_configgpio(priv->config->ws_pin, INPUT_FUNCTION_2); + esp_gpio_matrix_in(priv->config->ws_pin, priv->config->ws_out_insig, 0); - esp32s2_gpiowrite(priv->config->bclk_pin, 1); - esp32s2_configgpio(priv->config->bclk_pin, INPUT_FUNCTION_2); - esp32s2_gpio_matrix_in(priv->config->bclk_pin, + esp_gpiowrite(priv->config->bclk_pin, 1); + esp_configgpio(priv->config->bclk_pin, INPUT_FUNCTION_2); + esp_gpio_matrix_in(priv->config->bclk_pin, priv->config->bclk_out_insig, 0); } else @@ -1289,14 +1289,14 @@ static void i2s_configure(struct esp32s2_i2s_s *priv) * index for ws and bck. */ - esp32s2_gpiowrite(priv->config->ws_pin, 1); - esp32s2_configgpio(priv->config->ws_pin, INPUT_FUNCTION_2); - esp32s2_gpio_matrix_in(priv->config->ws_pin, + esp_gpiowrite(priv->config->ws_pin, 1); + esp_configgpio(priv->config->ws_pin, INPUT_FUNCTION_2); + esp_gpio_matrix_in(priv->config->ws_pin, priv->config->ws_in_insig, 0); - esp32s2_gpiowrite(priv->config->bclk_pin, 1); - esp32s2_configgpio(priv->config->bclk_pin, INPUT_FUNCTION_2); - esp32s2_gpio_matrix_in(priv->config->bclk_pin, + esp_gpiowrite(priv->config->bclk_pin, 1); + esp_configgpio(priv->config->bclk_pin, INPUT_FUNCTION_2); + esp_gpio_matrix_in(priv->config->bclk_pin, priv->config->bclk_in_insig, 0); } } @@ -1311,9 +1311,9 @@ static void i2s_configure(struct esp32s2_i2s_s *priv) i2sinfo("Configuring GPIO%" PRIu8 " to output master clock\n", priv->config->mclk_pin); - esp32s2_gpiowrite(priv->config->mclk_pin, 1); - esp32s2_configgpio(priv->config->mclk_pin, OUTPUT_FUNCTION_2); - esp32s2_gpio_matrix_out(priv->config->mclk_pin, + esp_gpiowrite(priv->config->mclk_pin, 1); + esp_configgpio(priv->config->mclk_pin, OUTPUT_FUNCTION_2); + esp_gpio_matrix_out(priv->config->mclk_pin, priv->config->mclk_out_sig, 0, 0); } @@ -1321,14 +1321,14 @@ static void i2s_configure(struct esp32s2_i2s_s *priv) { /* For "tx + master" mode, select TX signal index for ws and bck */ - esp32s2_gpiowrite(priv->config->ws_pin, 1); - esp32s2_configgpio(priv->config->ws_pin, OUTPUT_FUNCTION_2); - esp32s2_gpio_matrix_out(priv->config->ws_pin, + esp_gpiowrite(priv->config->ws_pin, 1); + esp_configgpio(priv->config->ws_pin, OUTPUT_FUNCTION_2); + esp_gpio_matrix_out(priv->config->ws_pin, priv->config->ws_out_outsig, 0, 0); - esp32s2_gpiowrite(priv->config->bclk_pin, 1); - esp32s2_configgpio(priv->config->bclk_pin, OUTPUT_FUNCTION_2); - esp32s2_gpio_matrix_out(priv->config->bclk_pin, + esp_gpiowrite(priv->config->bclk_pin, 1); + esp_configgpio(priv->config->bclk_pin, OUTPUT_FUNCTION_2); + esp_gpio_matrix_out(priv->config->bclk_pin, priv->config->bclk_out_outsig, 0, 0); } else @@ -1337,14 +1337,14 @@ static void i2s_configure(struct esp32s2_i2s_s *priv) * index for ws and bck. */ - esp32s2_gpiowrite(priv->config->ws_pin, 1); - esp32s2_configgpio(priv->config->ws_pin, OUTPUT_FUNCTION_2); - esp32s2_gpio_matrix_out(priv->config->ws_pin, + esp_gpiowrite(priv->config->ws_pin, 1); + esp_configgpio(priv->config->ws_pin, OUTPUT_FUNCTION_2); + esp_gpio_matrix_out(priv->config->ws_pin, priv->config->ws_in_outsig, 0, 0); - esp32s2_gpiowrite(priv->config->bclk_pin, 1); - esp32s2_configgpio(priv->config->bclk_pin, OUTPUT_FUNCTION_2); - esp32s2_gpio_matrix_out(priv->config->bclk_pin, + esp_gpiowrite(priv->config->bclk_pin, 1); + esp_configgpio(priv->config->bclk_pin, OUTPUT_FUNCTION_2); + esp_gpio_matrix_out(priv->config->bclk_pin, priv->config->bclk_in_outsig, 0, 0); } } @@ -2002,16 +2002,14 @@ static void i2s_rx_channel_stop(struct esp32s2_i2s_s *priv) * Common I2S DMA interrupt handler * * Input Parameters: - * irq - Number of the IRQ that generated the interrupt - * context - Interrupt register state save info * arg - I2S controller private data * * Returned Value: - * Standard interrupt return value. + * None. * ****************************************************************************/ -static int i2s_interrupt(int irq, void *context, void *arg) +static void i2s_interrupt(void *arg) { struct esp32s2_i2s_s *priv = (struct esp32s2_i2s_s *)arg; struct esp32s2_dmadesc_s *cur = NULL; @@ -2049,8 +2047,6 @@ static int i2s_interrupt(int irq, void *context, void *arg) } } #endif /* I2S_HAVE_RX */ - - return 0; } /**************************************************************************** @@ -2645,25 +2641,21 @@ static int i2s_dma_setup(struct esp32s2_i2s_s *priv) putreg32(UINT32_MAX, I2S_INT_CLR_REG); - /* Set up to receive peripheral interrupts on the current CPU */ + /* Set up to receive peripheral interrupts on the current CPU. + * With ARCH_MINIMAL_VECTORTABLE, the handler must be passed directly + * to esp_setup_irq() so it gets stored in the HAL's interrupt table. + */ priv->cpu = this_cpu(); - priv->cpuint = esp32s2_setup_irq(priv->config->periph, 1, - ESP32S2_CPUINT_LEVEL); + priv->cpuint = esp_setup_irq(priv->config->periph, 1, + ESP_IRQ_TRIGGER_LEVEL, + i2s_interrupt, priv); if (priv->cpuint < 0) { i2serr("Failed to allocate a CPU interrupt.\n"); return priv->cpuint; } - ret = irq_attach(priv->config->irq, i2s_interrupt, priv); - if (ret != OK) - { - i2serr("Couldn't attach IRQ to handler.\n"); - esp32s2_teardown_irq(priv->config->periph, priv->cpuint); - return ret; - } - return OK; } diff --git a/arch/xtensa/src/esp32s2/esp32s2_irq.c b/arch/xtensa/src/esp32s2/esp32s2_irq.c deleted file mode 100644 index 4635546d4132b..0000000000000 --- a/arch/xtensa/src/esp32s2/esp32s2_irq.c +++ /dev/null @@ -1,868 +0,0 @@ -/**************************************************************************** - * arch/xtensa/src/esp32s2/esp32s2_irq.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include "xtensa.h" -#ifdef CONFIG_ESP32S2_GPIO_IRQ -#include "esp32s2_gpio.h" -#endif -#include "esp32s2_rtc_gpio.h" -#include "esp32s2_irq.h" -#include "hardware/esp32s2_soc.h" -#include "hardware/esp32s2_system.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define IRQ_UNMAPPED 0xff - -/* CPU interrupts to peripheral mapping: - * - * Encoding: EPPPPPPP - * E: CPU interrupt status (0 = Disabled, 1 = Enabled). - * P: Attached peripheral. - */ - -#define CPUINT_UNASSIGNED 0x7f -#define CPUINT_GETEN(m) (((m) & 0x80) >> 0x07) -#define CPUINT_GETIRQ(m) ((m) & 0x7f) -#define CPUINT_ASSIGN(c) (((c) & 0x7f) | 0x80) -#define CPUINT_DISABLE(m) ((m) & 0x7f) -#define CPUINT_ENABLE(m) ((m) | 0x80) - -/* Mapping Peripheral IDs to map register addresses. */ - -#define CORE_MAP_REGADDR(n) (DR_REG_INTERRUPT_BASE + ((n) << 2)) - -/* CPU interrupts can be detached from any peripheral source by setting the - * map register to an internal CPU interrupt (6, 7, 11, 15, 16, or 29). - */ - -#define NO_CPUINT ESP32S2_CPUINT_TIMER0 - -/* Priority range is 1-5 */ - -#define ESP32S2_MIN_PRIORITY 1 -#define ESP32S2_MAX_PRIORITY 5 -#define ESP32S2_PRIO_INDEX(p) ((p) - ESP32S2_MIN_PRIORITY) - -#ifdef CONFIG_ESPRESSIF_WIFI -# define ESP32S2_WIFI_RESERVE_INT (1 << ESP32S2_CPUINT_MAC) -#else -# define ESP32S2_WIFI_RESERVE_INT 0 -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Maps a CPU interrupt to the IRQ of the attached peripheral interrupt */ - -static uint8_t g_cpu_intmap[ESP32S2_NCPUINTS]; - -static volatile uint8_t g_irqmap[NR_IRQS]; - -/* g_intenable is a shadow copy of the per-CPU INTENABLE register content */ - -static uint32_t g_intenable; - -/* g_non_iram_int_mask is a bitmask of the interrupts that should be - * disabled during a SPI flash operation. Non-IRAM interrupts should always - * be disabled, but interrupts place on IRAM are able to run during a SPI - * flash operation. - */ - -static uint32_t g_non_iram_int_mask; - -/* g_non_iram_int_disabled[] keeps track of the interrupts disabled during - * a SPI flash operation. - */ - -static uint32_t g_non_iram_int_disabled; - -/* Flag to indicate that non-IRAM interrupts were disabled */ - -static bool g_non_iram_int_disabled_flag; - -/* Bitsets for free, unallocated CPU interrupts available to peripheral - * devices. - */ - -static uint32_t g_cpu_freeints = ESP32S2_CPUINT_PERIPHSET & - ~ESP32S2_WIFI_RESERVE_INT; - -/* Bitsets for each interrupt priority 1-5 */ - -static const uint32_t g_priority[5] = -{ - ESP32S2_INTPRI1_MASK, - ESP32S2_INTPRI2_MASK, - ESP32S2_INTPRI3_MASK, - ESP32S2_INTPRI4_MASK, - ESP32S2_INTPRI5_MASK -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32s2_getcpuint - * - * Description: - * Get a free CPU interrupt for a peripheral device. This function will - * not ignore all of the pre-allocated CPU interrupts for internal - * devices. - * - * Input Parameters: - * intmask - mask of candidate CPU interrupts. The CPU interrupt will be - * be allocated from free interrupts within this set - * - * Returned Value: - * On success, a CPU interrupt number is returned. - * A negated errno is returned on failure. - * - ****************************************************************************/ - -static int esp32s2_getcpuint(uint32_t intmask) -{ - uint32_t bitmask; - uint32_t intset; - int cpuint; - int ret = -ENOMEM; - - /* Check if there are CPU interrupts with the requested properties - * available. - */ - - intset = g_cpu_freeints & intmask; - if (intset != 0) - { - /* Skip over initial unavailable CPU interrupts quickly in groups - * of 8 interrupt. - */ - - for (cpuint = 0, bitmask = 0xff; - cpuint <= ESP32S2_CPUINT_MAX && (intset & bitmask) == 0; - cpuint += 8, bitmask <<= 8); - - /* Search for an unallocated CPU interrupt number in the remaining - * intset. - */ - - for (; cpuint <= ESP32S2_CPUINT_MAX; cpuint++) - { - /* If the bit corresponding to the CPU interrupt is '1', then - * that CPU interrupt is available. - */ - - bitmask = 1ul << cpuint; - if ((intset & bitmask) != 0) - { - /* Got it! */ - - g_cpu_freeints &= ~bitmask; - ret = cpuint; - break; - } - } - } - - /* Enable the CPU interrupt now. The interrupt is still not attached - * to any peripheral and thus has no effect. - */ - - if (ret >= 0) - { - xtensa_enable_cpuint(&g_intenable, ret); - } - - return ret; -} - -/**************************************************************************** - * Name: esp32s2_alloc_cpuint - * - * Description: - * Allocate a level CPU interrupt - * - * Input Parameters: - * priority - Priority of the CPU interrupt (1-5) - * type - Interrupt type (level or edge). - * - * Returned Value: - * On success, the allocated CPU interrupt number is returned. - * A negated errno is returned on failure. The only possible failure - * is that all CPU interrupts of the requested type have already been - * allocated. - * - ****************************************************************************/ - -static int esp32s2_alloc_cpuint(int priority, int type) -{ - uint32_t mask; - - DEBUGASSERT(priority >= ESP32S2_MIN_PRIORITY && - priority <= ESP32S2_MAX_PRIORITY); - DEBUGASSERT(type == ESP32S2_CPUINT_LEVEL || - type == ESP32S2_CPUINT_EDGE); - - if (type == ESP32S2_CPUINT_LEVEL) - { - /* Check if there are any level CPU interrupts available at the - * requested interrupt priority. - */ - - mask = g_priority[ESP32S2_PRIO_INDEX(priority)] & - ESP32S2_CPUINT_LEVELSET; - } - else - { - /* Check if there are any edge CPU interrupts available at the - * requested interrupt priority. - */ - - mask = g_priority[ESP32S2_PRIO_INDEX(priority)] & - ESP32S2_CPUINT_EDGESET; - } - - return esp32s2_getcpuint(mask); -} - -/**************************************************************************** - * Name: esp32s2_free_cpuint - * - * Description: - * Free a previously allocated CPU interrupt - * - * Input Parameters: - * The CPU interrupt number to be freed - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void esp32s2_free_cpuint(int cpuint) -{ - uint32_t bitmask; - - DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32S2_CPUINT_MAX); - - /* Mark the CPU interrupt as available */ - - bitmask = 1ul << cpuint; - - DEBUGASSERT((g_cpu_freeints & bitmask) == 0); - - g_cpu_freeints |= bitmask; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_irqinitialize - ****************************************************************************/ - -void up_irqinitialize(void) -{ - int i; - - g_non_iram_int_mask = UINT32_MAX; - - for (i = 0; i < NR_IRQS; i++) - { - g_irqmap[i] = IRQ_UNMAPPED; - } - - /* Hard code special cases. */ - - g_irqmap[XTENSA_IRQ_TIMER0] = ESP32S2_CPUINT_TIMER0; - g_irqmap[XTENSA_IRQ_SWINT] = ESP32S2_CPUINT_SOFTWARE1; -#ifdef CONFIG_ESPRESSIF_WIFI - g_irqmap[ESP32S2_IRQ_MAC] = ESP32S2_CPUINT_MAC; - g_irqmap[ESP32S2_IRQ_PWR] = ESP32S2_CPUINT_PWR; -#endif - - /* Initialize CPU interrupts */ - - esp32s2_cpuint_initialize(); - - /* Reserve interrupt for some special drivers */ - -#ifdef CONFIG_ESPRESSIF_WIFI - g_cpu_intmap[ESP32S2_CPUINT_MAC] = CPUINT_ASSIGN(ESP32S2_IRQ_MAC); - g_cpu_intmap[ESP32S2_CPUINT_PWR] = CPUINT_ASSIGN(ESP32S2_IRQ_PWR); - xtensa_enable_cpuint(&g_intenable, ESP32S2_CPUINT_MAC); -#endif - -#ifdef CONFIG_ESP32S2_GPIO_IRQ - /* Initialize GPIO interrupt support */ - - esp32s2_gpioirqinitialize(); -#endif - - /* Initialize RTCIO interrupt support */ - - esp32s2_rtcioirqinitialize(); - -#ifndef CONFIG_SUPPRESS_INTERRUPTS - /* And finally, enable interrupts. Also clears PS.EXCM */ - - xtensa_color_intstack(); - up_irq_enable(); -#endif - - /* Attach the software interrupt */ - - irq_attach(XTENSA_IRQ_SYSCALL, xtensa_swint, NULL); -} - -/**************************************************************************** - * Name: up_disable_irq - * - * Description: - * Disable the IRQ specified by 'irq' - * - ****************************************************************************/ - -void up_disable_irq(int irq) -{ - int cpuint = g_irqmap[irq]; - - if (cpuint == IRQ_UNMAPPED) - { - /* This interrupt is already disabled. */ - - return; - } - - DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32S2_CPUINT_MAX); - - if (irq < XTENSA_NIRQ_INTERNAL) - { - /* This is an internal CPU interrupt, it cannot be disabled using - * the Interrupt Matrix. - */ - - xtensa_disable_cpuint(&g_intenable, cpuint); - } - else - { - /* A peripheral interrupt, use the Interrupt Matrix to disable it. */ - - int periph = ESP32S2_IRQ2PERIPH(irq); - uintptr_t regaddr = CORE_MAP_REGADDR(periph); - - DEBUGASSERT(periph >= 0 && periph < ESP32S2_NPERIPHERALS); - - g_cpu_intmap[cpuint] = CPUINT_DISABLE(g_cpu_intmap[cpuint]); - putreg32(NO_CPUINT, regaddr); - } -} - -/**************************************************************************** - * Name: up_enable_irq - * - * Description: - * Enable the IRQ specified by 'irq' - * - ****************************************************************************/ - -void up_enable_irq(int irq) -{ - int cpuint = g_irqmap[irq]; - - DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32S2_CPUINT_MAX); - - if (irq < XTENSA_NIRQ_INTERNAL) - { - /* Enable the CPU interrupt now for internal CPU. */ - - xtensa_enable_cpuint(&g_intenable, cpuint); - } - else - { - /* Check if the registered ISR for this IRQ is intended to be run from - * IRAM. If so, check if its interrupt handler is located in IRAM. - */ - - bool isr_in_iram = !((g_non_iram_int_mask & (1 << cpuint)) > 0); - - xcpt_t handler = g_irqvector[irq].handler; - - if (isr_in_iram && handler && !esp32s2_ptr_iram(handler)) - { - irqerr("Interrupt handler isn't in IRAM (%08" PRIxPTR ")", - (intptr_t)handler); - PANIC(); - } - - /* For peripheral interrupts, attach the interrupt to the peripheral; - * the CPU interrupt was already enabled when allocated. - */ - - int periph = ESP32S2_IRQ2PERIPH(irq); - uintptr_t regaddr = CORE_MAP_REGADDR(periph); - - DEBUGASSERT(periph >= 0 && periph < ESP32S2_NPERIPHERALS); - - g_cpu_intmap[cpuint] = CPUINT_ENABLE(g_cpu_intmap[cpuint]); - putreg32(cpuint, regaddr); - } -} - -/**************************************************************************** - * Name: esp32s2_cpuint_initialize - * - * Description: - * Initialize CPU interrupts - * - * Input Parameters: - * None - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned on - * any failure. - * - ****************************************************************************/ - -int esp32s2_cpuint_initialize(void) -{ - uintptr_t regaddr; - int i; - - /* Disable all CPU interrupts on this CPU */ - - xtensa_disable_all(); - - /* Detach all interrupts from peripheral sources */ - - for (i = 0; i < ESP32S2_NPERIPHERALS; i++) - { - regaddr = CORE_MAP_REGADDR(i); - - putreg32(NO_CPUINT, regaddr); - } - - /* Indicate that no peripheral interrupts are assigned to CPU interrupts */ - - memset(g_cpu_intmap, CPUINT_UNASSIGNED, ESP32S2_NCPUINTS); - - /* Special case the 6 internal interrupts. - * - * CPU interrupt bit IRQ number - * ---------------------------- --------------------- - * ESP32S2_CPUINT_TIMER0 6 XTENSA_IRQ_TIMER0 0 - * ESP32S2_CPUINT_SOFTWARE0 7 Not yet defined - * ESP32S2_CPUINT_PROFILING 11 Not yet defined - * ESP32S2_CPUINT_TIMER1 15 XTENSA_IRQ_TIMER1 1 - * ESP32S2_CPUINT_TIMER2 16 XTENSA_IRQ_TIMER2 2 - * ESP32S2_CPUINT_SOFTWARE1 29 XTENSA_IRQ_SWINT 4 - */ - - g_cpu_intmap[ESP32S2_CPUINT_TIMER0] = CPUINT_ASSIGN(XTENSA_IRQ_TIMER0); - g_cpu_intmap[ESP32S2_CPUINT_TIMER1] = CPUINT_ASSIGN(XTENSA_IRQ_TIMER1); - g_cpu_intmap[ESP32S2_CPUINT_TIMER2] = CPUINT_ASSIGN(XTENSA_IRQ_TIMER2); - g_cpu_intmap[ESP32S2_CPUINT_SOFTWARE1] = CPUINT_ASSIGN(XTENSA_IRQ_SWINT); - - return OK; -} - -/**************************************************************************** - * Name: esp32s2_setup_irq - * - * Description: - * This function sets up the IRQ. It allocates a CPU interrupt of the given - * priority and type and attaches it to the given peripheral. - * - * Input Parameters: - * periphid - The peripheral number from irq.h to be assigned to - * a CPU interrupt. - * priority - Interrupt's priority (1 - 5). - * flags - An ORred mask of the ESP32S3_CPUINT_FLAG_* defines. These - * restrict the choice of interrupts that this routine can - * choose from. - * - * Returned Value: - * The allocated CPU interrupt on success, a negated errno value on - * failure. - * - ****************************************************************************/ - -int esp32s2_setup_irq(int periphid, int priority, int flags) -{ - irqstate_t irqstate; - uintptr_t regaddr; - int irq; - int cpuint; - int type; - - if ((flags & ESP32S2_CPUINT_EDGE) != 0) - { - type = ESP32S2_CPUINT_EDGE; - } - else - { - type = ESP32S2_CPUINT_LEVEL; - } - - irqstate = enter_critical_section(); - - /* Setting up an IRQ includes the following steps: - * 1. Allocate a CPU interrupt. - * 2. Attach that CPU interrupt to the peripheral. - * 3. Map the CPU interrupt to the IRQ to ease searching later. - */ - - cpuint = esp32s2_alloc_cpuint(priority, type); - if (cpuint < 0) - { - irqerr("Unable to allocate CPU interrupt for priority=%d and type=%d", - priority, type); - leave_critical_section(irqstate); - - return cpuint; - } - - irq = ESP32S2_PERIPH2IRQ(periphid); - - DEBUGASSERT(periphid >= 0 && periphid < ESP32S2_NPERIPHERALS); - DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32S2_CPUINT_MAX); - DEBUGASSERT(g_cpu_intmap[cpuint] == CPUINT_UNASSIGNED); - - g_cpu_intmap[cpuint] = CPUINT_ASSIGN(periphid + XTENSA_IRQ_FIRSTPERIPH); - g_irqmap[irq] = cpuint; - regaddr = CORE_MAP_REGADDR(periphid); - - if ((flags & ESP32S2_CPUINT_FLAG_IRAM) != 0) - { - esp32s2_irq_set_iram_isr(irq); - } - else - { - esp32s2_irq_unset_iram_isr(irq); - } - - putreg32(cpuint, regaddr); - - leave_critical_section(irqstate); - - return cpuint; -} - -/**************************************************************************** - * Name: esp32s2_teardown_irq - * - * Description: - * This function undoes the operations done by esp32s2_setup_irq. - * It detaches a peripheral interrupt from a CPU interrupt and frees the - * CPU interrupt. - * - * Input Parameters: - * periphid - The peripheral number from irq.h to be detached from the - * CPU interrupt. - * cpuint - The CPU interrupt from which the peripheral interrupt will - * be detached. - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32s2_teardown_irq(int periphid, int cpuint) -{ - irqstate_t irqstate; - uintptr_t regaddr; - int irq; - - irqstate = enter_critical_section(); - - /* Tearing down an IRQ includes the following steps: - * 1. Free the previously allocated CPU interrupt. - * 2. Detach the interrupt from the peripheral. - * 3. Unmap the IRQ from the IRQ-to-cpuint map. - */ - - esp32s2_free_cpuint(cpuint); - - irq = ESP32S2_PERIPH2IRQ(periphid); - - DEBUGASSERT(periphid >= 0 && periphid < ESP32S2_NPERIPHERALS); - - DEBUGASSERT(g_cpu_intmap[cpuint] != CPUINT_UNASSIGNED); - g_cpu_intmap[cpuint] = CPUINT_UNASSIGNED; - g_irqmap[irq] = IRQ_UNMAPPED; - regaddr = CORE_MAP_REGADDR(periphid); - - putreg32(NO_CPUINT, regaddr); - - leave_critical_section(irqstate); -} - -/**************************************************************************** - * Name: xtensa_int_decode - * - * Description: - * Determine the peripheral that generated the interrupt and dispatch - * handling to the registered interrupt handler via xtensa_irq_dispatch(). - * - * Input Parameters: - * cpuints - Set of pending interrupts valid for this level - * regs - Saves processor state on the stack - * - * Returned Value: - * Normally the same value as regs is returned. But, in the event of an - * interrupt level context switch, the returned value will, instead point - * to the saved processor state in the TCB of the newly started task. - * - ****************************************************************************/ - -uint32_t *xtensa_int_decode(uint32_t *cpuints, uint32_t *regs) -{ - uint32_t mask; - int bit; - -#ifdef CONFIG_ARCH_LEDS_CPU_ACTIVITY - board_autoled_on(LED_CPU); -#endif - - /* Skip over zero bits, eight at a time */ - - for (bit = 0, mask = 0xff; - bit < ESP32S2_NCPUINTS && (cpuints[0] & mask) == 0; - bit += 8, mask <<= 8); - - /* Process each pending CPU interrupt */ - - for (; bit < ESP32S2_NCPUINTS && cpuints[0] != 0; bit++) - { - mask = 1 << bit; - if ((cpuints[0] & mask) != 0) - { - /* Extract the IRQ number from the mapping table */ - - uint8_t irq = CPUINT_GETIRQ(g_cpu_intmap[bit]); - - DEBUGASSERT(CPUINT_GETEN(g_cpu_intmap[bit])); - DEBUGASSERT(irq != CPUINT_UNASSIGNED); - - /* Clear software or edge-triggered interrupt */ - - xtensa_intclear(bit); - - /* Dispatch the CPU interrupt. - * - * NOTE that regs may be altered in the case of an interrupt - * level context switch. - */ - - regs = xtensa_irq_dispatch((int)irq, regs); - - /* Clear the bit in the pending interrupt so that perhaps - * we can exit the look early. - */ - - cpuints[0] &= ~mask; - } - } - - return regs; -} - -/**************************************************************************** - * Name: esp32s2_irq_noniram_disable - * - * Description: - * Disable interrupts that aren't specifically marked as running from IRAM - * - * Input Parameters: - * None - * - * Input Parameters: - * None - * - ****************************************************************************/ - -void esp32s2_irq_noniram_disable(void) -{ - irqstate_t irqstate; - uint32_t mask; - int bit; - uint32_t oldint; - uint32_t non_iram_ints; - - irqstate = enter_critical_section(); - non_iram_ints = g_non_iram_int_mask; - - ASSERT(!g_non_iram_int_disabled_flag); - - g_non_iram_int_disabled_flag = true; - oldint = g_intenable; - - for (bit = 0; bit < ESP32S2_NCPUINTS; bit++) - { - mask = 1 << bit; - if ((non_iram_ints & mask) != 0) - { - xtensa_disable_cpuint(&g_intenable, bit); - } - } - - g_non_iram_int_disabled = oldint & non_iram_ints; - - leave_critical_section(irqstate); -} - -/**************************************************************************** - * Name: esp32s2_irq_noniram_enable - * - * Description: - * Re-enable interrupts disabled by esp32s2_irq_noniram_disable - * - * Input Parameters: - * None - * - * Input Parameters: - * None - * - ****************************************************************************/ - -void esp32s2_irq_noniram_enable(void) -{ - irqstate_t irqstate; - uint32_t mask; - int bit; - uint32_t non_iram_ints; - - irqstate = enter_critical_section(); - non_iram_ints = g_non_iram_int_disabled; - - ASSERT(g_non_iram_int_disabled_flag); - - g_non_iram_int_disabled_flag = false; - - for (bit = 0; bit < ESP32S2_NCPUINTS; bit++) - { - mask = 1 << bit; - if ((non_iram_ints & mask) != 0) - { - xtensa_enable_cpuint(&g_intenable, bit); - } - } - - leave_critical_section(irqstate); -} - -/**************************************************************************** - * Name: esp32s2_irq_noniram_status - * - * Description: - * Get the current status of non-IRAM interrupts on a specific CPU core - * - * Input Parameters: - * None. - * - * Returned Value: - * True if non-IRAM interrupts are enabled. False otherwise. - * - ****************************************************************************/ - -bool esp32s2_irq_noniram_status() -{ - return !g_non_iram_int_disabled_flag; -} - -/**************************************************************************** - * Name: esp32s3_irq_set_iram_isr - * - * Description: - * Set the ISR associated to an IRQ as a IRAM-enabled ISR. - * - * Input Parameters: - * irq - The associated IRQ to set - * - * Returned Value: - * OK on success; A negated errno value on failure. - * - ****************************************************************************/ - -int esp32s2_irq_set_iram_isr(int irq) -{ - int cpuint = CPUINT_GETIRQ(g_cpu_intmap[irq]); - - if (cpuint == IRQ_UNMAPPED) - { - return -EINVAL; - } - - g_non_iram_int_mask &= ~(1 << cpuint); - - return OK; -} - -/**************************************************************************** - * Name: esp32s2_irq_unset_iram_isr - * - * Description: - * Set the ISR associated to an IRQ as a non-IRAM ISR. - * - * Input Parameters: - * irq - The associated IRQ to set - * - * Returned Value: - * OK on success; A negated errno value on failure. - * - ****************************************************************************/ - -int esp32s2_irq_unset_iram_isr(int irq) -{ - int cpuint = CPUINT_GETIRQ(g_cpu_intmap[irq]); - - if (cpuint == IRQ_UNMAPPED) - { - return -EINVAL; - } - - g_non_iram_int_mask |= (1 << cpuint); - - return OK; -} diff --git a/arch/xtensa/src/esp32s2/esp32s2_irq.h b/arch/xtensa/src/esp32s2/esp32s2_irq.h deleted file mode 100644 index 7753a28c87293..0000000000000 --- a/arch/xtensa/src/esp32s2/esp32s2_irq.h +++ /dev/null @@ -1,203 +0,0 @@ -/**************************************************************************** - * arch/xtensa/src/esp32s2/esp32s2_irq.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_IRQ_H -#define __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_IRQ_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/* CPU interrupt types. */ - -#define ESP32S2_CPUINT_LEVEL ESP32S2_CPUINT_FLAG_LEVEL -#define ESP32S2_CPUINT_EDGE ESP32S2_CPUINT_FLAG_EDGE - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32s2_cpuint_initialize - * - * Description: - * Initialize CPU interrupts - * - * Input Parameters: - * None - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned on - * any failure. - * - ****************************************************************************/ - -int esp32s2_cpuint_initialize(void); - -/**************************************************************************** - * Name: esp32s2_setup_irq - * - * Description: - * This function sets up the IRQ. It allocates a CPU interrupt of the given - * priority and type and attaches it to the given peripheral. - * - * Input Parameters: - * periphid - The peripheral number from irq.h to be assigned to - * a CPU interrupt. - * priority - Interrupt's priority (1 - 5). - * flags - An ORred mask of the ESP32S3_CPUINT_FLAG_* defines. These - * restrict the choice of interrupts that this routine can - * choose from. - * - * Returned Value: - * The allocated CPU interrupt on success, a negated errno value on - * failure. - * - ****************************************************************************/ - -int esp32s2_setup_irq(int periphid, int priority, int flags); - -/**************************************************************************** - * Name: esp32s2_teardown_irq - * - * Description: - * This function undoes the operations done by esp32s2_setup_irq. - * It detaches a peripheral interrupt from a CPU interrupt and frees the - * CPU interrupt. - * - * Input Parameters: - * periphid - The peripheral number from irq.h to be detached from the - * CPU interrupt. - * cpuint - The CPU interrupt from which the peripheral interrupt will - * be detached. - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32s2_teardown_irq(int periphid, int cpuint); - -/**************************************************************************** - * Name: esp32s2_irq_noniram_disable - * - * Description: - * Disable interrupts that aren't specifically marked as running from IRAM - * - * Input Parameters: - * None - * - * Input Parameters: - * None - * - ****************************************************************************/ - -void esp32s2_irq_noniram_disable(void); - -/**************************************************************************** - * Name: esp32s2_irq_noniram_enable - * - * Description: - * Re-enable interrupts disabled by esp32s2_irq_noniram_disable - * - * Input Parameters: - * None - * - * Input Parameters: - * None - * - ****************************************************************************/ - -void esp32s2_irq_noniram_enable(void); - -/**************************************************************************** - * Name: esp32s2_irq_noniram_status - * - * Description: - * Get the current status of non-IRAM interrupts. - * - * Input Parameters: - * None. - * - * Returned Value: - * True if non-IRAM interrupts are enabled, false otherwise. - * - ****************************************************************************/ - -bool esp32s2_irq_noniram_status(void); - -/**************************************************************************** - * Name: esp32s2_irq_set_iram_isr - * - * Description: - * Set the ISR associated to an IRQ as a IRAM-enabled ISR. - * - * Input Parameters: - * irq - The associated IRQ to set - * - * Returned Value: - * OK on success; A negated errno value on failure. - * - ****************************************************************************/ - -int esp32s2_irq_set_iram_isr(int irq); - -/**************************************************************************** - * Name: esp32s2_irq_unset_iram_isr - * - * Description: - * Set the ISR associated to an IRQ as a non-IRAM ISR. - * - * Input Parameters: - * irq - The associated IRQ to set - * - * Returned Value: - * OK on success; A negated errno value on failure. - * - ****************************************************************************/ - -int esp32s2_irq_unset_iram_isr(int irq); - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_IRQ_H */ diff --git a/arch/xtensa/src/esp32s2/esp32s2_libc_stubs.c b/arch/xtensa/src/esp32s2/esp32s2_libc_stubs.c index 49e353fc4bf28..9c61f6ef4f87a 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_libc_stubs.c +++ b/arch/xtensa/src/esp32s2/esp32s2_libc_stubs.c @@ -35,6 +35,7 @@ #include #include #include +#include #include "rom/esp32s2_libc_stubs.h" @@ -165,6 +166,11 @@ void _raise_r(struct _reent *r) void _lock_init(_lock_t *lock) { + if (sched_idletask()) + { + return; + } + *lock = 0; mutex_t *mutex = (mutex_t *)kmm_malloc(sizeof(mutex_t)); @@ -176,6 +182,11 @@ void _lock_init(_lock_t *lock) void _lock_init_recursive(_lock_t *lock) { + if (sched_idletask()) + { + return; + } + *lock = 0; rmutex_t *rmutex = (rmutex_t *)kmm_malloc(sizeof(rmutex_t)); @@ -187,6 +198,11 @@ void _lock_init_recursive(_lock_t *lock) void _lock_close(_lock_t *lock) { + if (sched_idletask()) + { + return; + } + mutex_t *mutex = (mutex_t *)(*lock); nxmutex_destroy(mutex); @@ -196,6 +212,11 @@ void _lock_close(_lock_t *lock) void _lock_close_recursive(_lock_t *lock) { + if (sched_idletask()) + { + return; + } + rmutex_t *rmutex = (rmutex_t *)(*lock); nxrmutex_destroy(rmutex); @@ -205,6 +226,11 @@ void _lock_close_recursive(_lock_t *lock) void _lock_acquire(_lock_t *lock) { + if (sched_idletask()) + { + return; + } + if ((*lock) == 0) { mutex_t *mutex = (mutex_t *)kmm_malloc(sizeof(mutex_t)); @@ -219,6 +245,11 @@ void _lock_acquire(_lock_t *lock) void _lock_acquire_recursive(_lock_t *lock) { + if (sched_idletask()) + { + return; + } + if ((*lock) == 0) { rmutex_t *rmutex = (rmutex_t *)kmm_malloc(sizeof(rmutex_t)); @@ -233,6 +264,11 @@ void _lock_acquire_recursive(_lock_t *lock) int _lock_try_acquire(_lock_t *lock) { + if (sched_idletask()) + { + return -EPERM; + } + if ((*lock) == 0) { mutex_t *mutex = (mutex_t *)kmm_malloc(sizeof(mutex_t)); @@ -247,6 +283,11 @@ int _lock_try_acquire(_lock_t *lock) int _lock_try_acquire_recursive(_lock_t *lock) { + if (sched_idletask()) + { + return -EPERM; + } + if ((*lock) == 0) { rmutex_t *rmutex = (rmutex_t *)kmm_malloc(sizeof(rmutex_t)); @@ -261,6 +302,11 @@ int _lock_try_acquire_recursive(_lock_t *lock) void _lock_release(_lock_t *lock) { + if (sched_idletask()) + { + return; + } + mutex_t *mutex = (mutex_t *)(*lock); nxmutex_unlock(mutex); @@ -268,6 +314,11 @@ void _lock_release(_lock_t *lock) void _lock_release_recursive(_lock_t *lock) { + if (sched_idletask()) + { + return; + } + rmutex_t *rmutex = (rmutex_t *)(*lock); nxrmutex_unlock(rmutex); diff --git a/arch/xtensa/src/esp32s2/esp32s2_lowputc.c b/arch/xtensa/src/esp32s2/esp32s2_lowputc.c index 89f88f34edcf9..4799a9da1b1aa 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_lowputc.c +++ b/arch/xtensa/src/esp32s2/esp32s2_lowputc.c @@ -37,9 +37,9 @@ #include #include "xtensa.h" -#include "esp32s2_clockconfig.h" #include "esp32s2_config.h" -#include "esp32s2_gpio.h" +#include "espressif/esp_gpio.h" +#include "esp_clk.h" #include "esp32s2_lowputc.h" #include "hardware/esp32s2_gpio_sigmap.h" #include "hardware/esp32s2_soc.h" @@ -716,33 +716,33 @@ void esp32s2_lowputc_config_pins(const struct esp32s2_uart_s *priv) * This "?" is the Unicode replacement character (U+FFFD) */ - esp32s2_gpiowrite(priv->txpin, true); + esp_gpiowrite(priv->txpin, true); /* Route UART TX signal to the selected TX pin */ - esp32s2_gpio_matrix_out(priv->txpin, priv->txsig, 0, 0); + esp_gpio_matrix_out(priv->txpin, priv->txsig, 0, 0); /* Select the GPIO function to the TX pin and * configure as output. */ - esp32s2_configgpio(priv->txpin, OUTPUT_FUNCTION_1); + esp_configgpio(priv->txpin, OUTPUT_FUNCTION_1); /* Select the GPIO function to the RX pin and * configure as input. */ - esp32s2_configgpio(priv->rxpin, INPUT_FUNCTION_1); + esp_configgpio(priv->rxpin, INPUT_FUNCTION_1); /* Route UART RX signal to the selected RX pin */ - esp32s2_gpio_matrix_in(priv->rxpin, priv->rxsig, 0); + esp_gpio_matrix_in(priv->rxpin, priv->rxsig, 0); #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) { - esp32s2_configgpio(priv->rtspin, OUTPUT_FUNCTION_1); - esp32s2_gpio_matrix_out(priv->rtspin, priv->rtssig, + esp_configgpio(priv->rtspin, OUTPUT_FUNCTION_1); + esp_gpio_matrix_out(priv->rtspin, priv->rtssig, 0, 0); } @@ -750,17 +750,17 @@ void esp32s2_lowputc_config_pins(const struct esp32s2_uart_s *priv) #ifdef CONFIG_SERIAL_OFLOWCONTROL if (priv->oflow) { - esp32s2_configgpio(priv->ctspin, INPUT_FUNCTION_1); - esp32s2_gpio_matrix_in(priv->ctspin, priv->ctssig, 0); + esp_configgpio(priv->ctspin, INPUT_FUNCTION_1); + esp_gpio_matrix_in(priv->ctspin, priv->ctssig, 0); } #endif #ifdef HAVE_RS485 if (priv->rs485_dir_gpio != 0) { - esp32s2_configgpio(priv->rs485_dir_gpio, OUTPUT); - esp32s2_gpio_matrix_out(priv->rs485_dir_gpio, SIG_GPIO_OUT_IDX, 0, 0); - esp32s2_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); + esp_configgpio(priv->rs485_dir_gpio, OUTPUT); + esp_gpio_matrix_out(priv->rs485_dir_gpio, SIG_GPIO_OUT_IDX, 0, 0); + esp_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); } #endif } diff --git a/arch/xtensa/src/esp32s2/esp32s2_oneshot.c b/arch/xtensa/src/esp32s2/esp32s2_oneshot.c index 70c25968376b5..a0edc3c10fcf2 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_oneshot.c +++ b/arch/xtensa/src/esp32s2/esp32s2_oneshot.c @@ -39,7 +39,7 @@ #include "hardware/esp32s2_soc.h" #include "esp32s2_tim.h" -#include "esp32s2_clockconfig.h" +#include "esp_clk.h" #include "esp32s2_oneshot.h" #ifdef CONFIG_ESP32S2_ONESHOT @@ -73,12 +73,14 @@ static int esp32s2_oneshot_handler(int irq, void *context, void *arg); * the next level up. * * Input Parameters: - * irq - IRQ associated to that interrupt - * arg - A pointer to the argument provided when the interrupt was - * registered. + * irq - The interrupt number. + * context - The context of the interrupt. + * arg - A pointer to the argument provided when the interrupt was + * registered. * * Returned Value: - * Zero on success; a negated errno value on failure. + * Zero (OK) is returned on success; a negated errno value is returned + * on failure. * ****************************************************************************/ diff --git a/arch/xtensa/src/esp32s2/esp32s2_psram.c b/arch/xtensa/src/esp32s2/esp32s2_psram.c index aba01acbb0408..88b7e5ed1c597 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_psram.c +++ b/arch/xtensa/src/esp32s2/esp32s2_psram.c @@ -30,12 +30,11 @@ #include #include -#include "esp32s2_gpio.h" #include "esp32s2_psram.h" #include "rom/esp32s2_spiflash.h" #include "rom/esp32s2_opi_flash.h" -#include "hardware/esp32s2_efuse.h" +#include "soc/efuse_reg.h" #include "hardware/esp32s2_spi.h" #include "hardware/esp32s2_spi_mem_reg.h" #include "hardware/esp32s2_iomux.h" diff --git a/arch/xtensa/src/esp32s2/esp32s2_rng.c b/arch/xtensa/src/esp32s2/esp32s2_rng.c index af6592348691c..1102c12a6fcd7 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_rng.c +++ b/arch/xtensa/src/esp32s2/esp32s2_rng.c @@ -43,7 +43,6 @@ #include "xtensa.h" #include "esp_attr.h" #include "hardware/wdev_reg.h" -#include "esp32s2_clockconfig.h" #include "esp_random.h" diff --git a/arch/xtensa/src/esp32s2/esp32s2_rt_timer.c b/arch/xtensa/src/esp32s2/esp32s2_rt_timer.c deleted file mode 100644 index ce26aec5e7451..0000000000000 --- a/arch/xtensa/src/esp32s2/esp32s2_rt_timer.c +++ /dev/null @@ -1,839 +0,0 @@ -/**************************************************************************** - * arch/xtensa/src/esp32s2/esp32s2_rt_timer.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this args for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "xtensa.h" -#include "esp_attr.h" - -#include "hardware/esp32s2_soc.h" -#include "hardware/esp32s2_system.h" -#include "hardware/esp32s2_systimer.h" -#include "esp32s2_tim.h" -#include "esp32s2_rt_timer.h" -#include "esp32s2_clockconfig.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifdef CONFIG_SCHED_HPWORKPRIORITY -# if CONFIG_ESP32S2_RT_TIMER_TASK_PRIORITY >= CONFIG_SCHED_HPWORKPRIORITY -# error "RT timer priority should be smaller than high-prio workqueue" -# endif -#endif - -#define RT_TIMER_TASK_NAME CONFIG_ESP32S2_RT_TIMER_TASK_NAME -#define RT_TIMER_TASK_PRIORITY CONFIG_ESP32S2_RT_TIMER_TASK_PRIORITY -#define RT_TIMER_TASK_STACK_SIZE CONFIG_ESP32S2_RT_TIMER_TASK_STACK_SIZE - -/* Timer running at 80 MHz */ - -#define CYCLES_PER_USEC 80 -#define USEC_TO_CYCLES(u) ((u) * CYCLES_PER_USEC) -#define CYCLES_TO_USEC(c) ((c) / CYCLES_PER_USEC) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct esp32s2_rt_priv_s -{ - pid_t pid; - sem_t toutsem; - struct list_node runlist; - struct list_node toutlist; - struct esp32s2_tim_dev_s *timer; -}; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct esp32s2_rt_priv_s g_rt_priv = -{ - .pid = INVALID_PROCESS_ID, - .toutsem = SEM_INITIALIZER(0), -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: start_rt_timer - * - * Description: - * Start the timer by inserting it into the running list and reset the - * hardware timer alarm value if this timer is at the head of the list. - * Larger timeouts go to the end of the list (tail). - * - * Input Parameters: - * timer - RT timer pointer - * timeout - Timeout value - * repeat - repeat mode (true: enabled, false: disabled) - * - * Returned Value: - * None. - * - ****************************************************************************/ - -static void start_rt_timer(struct rt_timer_s *timer, - uint64_t timeout, - bool repeat) -{ - irqstate_t flags; - struct rt_timer_s *temp_p; - bool inserted = false; - uint64_t counter; - struct esp32s2_rt_priv_s *priv = &g_rt_priv; - - flags = enter_critical_section(); - - /* Only idle timer can be started */ - - if (timer->state == RT_TIMER_IDLE) - { - /* Calculate the timer's alarm value */ - - ESP32S2_TIM_GETCTR(priv->timer, &counter); - counter = CYCLES_TO_USEC(counter); - timer->timeout = timeout; - timer->alarm = timer->timeout + counter; - - if (repeat) - { - timer->flags |= RT_TIMER_REPEAT; - } - else - { - timer->flags &= ~RT_TIMER_REPEAT; - } - - /* Scan the timer list and insert the new timer into previous - * node of timer whose alarm value is larger than new one - */ - - list_for_every_entry(&priv->runlist, temp_p, struct rt_timer_s, list) - { - if (temp_p->alarm > timer->alarm) - { - list_add_before(&temp_p->list, &timer->list); - inserted = true; - break; - } - } - - /* If we didn't find a larger one, insert the new timer at the tail - * of the list. - */ - - if (!inserted) - { - list_add_tail(&priv->runlist, &timer->list); - } - - timer->state = RT_TIMER_READY; - - /* If this timer is at the head of the list */ - - if (timer == container_of(priv->runlist.next, - struct rt_timer_s, list)) - { - /* Reset the hardware timer alarm */ - - ESP32S2_TIM_SETALRM(priv->timer, false); - ESP32S2_TIM_SETALRVL(priv->timer, USEC_TO_CYCLES(timer->alarm)); - ESP32S2_TIM_SETALRM(priv->timer, true); - } - } - else - { - tmrwarn("WARN: Timer not in idle mode.\n"\ - "Only idle timer can be started!\n"); - } - - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: stop_rt_timer - * - * Description: - * Stop the timer by removing it from the running list and reset the - * hardware timer alarm value if this timer is at the head of list. - * - * Input Parameters: - * timer - RT timer pointer - * - * Returned Value: - * None. - * - ****************************************************************************/ - -static void stop_rt_timer(struct rt_timer_s *timer) -{ - irqstate_t flags; - bool ishead; - struct rt_timer_s *next_timer; - uint64_t alarm; - struct esp32s2_rt_priv_s *priv = &g_rt_priv; - - flags = enter_critical_section(); - - /* "start" function can set the timer's repeat flag, and "stop" function - * should remove this flag. - */ - - timer->flags &= ~RT_TIMER_REPEAT; - - /* Only timers in "ready" state can be stopped */ - - if (timer->state == RT_TIMER_READY) - { - /* Check if the timer is at the head of the list */ - - if (timer == container_of(priv->runlist.next, - struct rt_timer_s, list)) - { - ishead = true; - } - else - { - ishead = false; - } - - list_delete(&timer->list); - timer->state = RT_TIMER_IDLE; - - /* If the timer is at the head of the list */ - - if (ishead) - { - if (!list_is_empty(&priv->runlist)) - { - /* Set the value from the next timer as the new hardware timer - * alarm value. - */ - - next_timer = container_of(priv->runlist.next, - struct rt_timer_s, - list); - alarm = next_timer->alarm; - - ESP32S2_TIM_SETALRM(priv->timer, false); - ESP32S2_TIM_SETALRVL(priv->timer, USEC_TO_CYCLES(alarm)); - ESP32S2_TIM_SETALRM(priv->timer, true); - } - } - } - - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: delete_rt_timer - * - * Description: - * Delete the timer by removing it from the list, then set the timer's - * state to "RT_TIMER_DELETE" and finally insert it into the work list - * to let the rt-timer's thread to delete it and free the resources. - * - * Input Parameters: - * timer - RT timer pointer - * - * Returned Value: - * None. - * - ****************************************************************************/ - -static void delete_rt_timer(struct rt_timer_s *timer) -{ - int ret; - irqstate_t flags; - struct esp32s2_rt_priv_s *priv = &g_rt_priv; - - flags = enter_critical_section(); - - if (timer->state == RT_TIMER_READY) - { - stop_rt_timer(timer); - } - else if (timer->state == RT_TIMER_TIMEOUT) - { - list_delete(&timer->list); - } - else if (timer->state == RT_TIMER_DELETE) - { - goto exit; - } - - list_add_after(&priv->toutlist, &timer->list); - timer->state = RT_TIMER_DELETE; - - /* Wake up the thread to process deleted timers */ - - ret = nxsem_post(&priv->toutsem); - if (ret < 0) - { - tmrerr("ERROR: Failed to post sem ret=%d\n", ret); - } - -exit: - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: rt_timer_thread - * - * Description: - * RT timer working thread: Waits for a timeout semaphore, scans - * the timeout list and processes all the timers in the list. - * - * Input Parameters: - * argc - Not used - * argv - Not used - * - * Returned Value: - * 0. - * - ****************************************************************************/ - -static int rt_timer_thread(int argc, char *argv[]) -{ - int ret; - irqstate_t flags; - struct rt_timer_s *timer; - enum rt_timer_state_e raw_state; - struct esp32s2_rt_priv_s *priv = &g_rt_priv; - - while (1) - { - /* Waiting for all timers to time out */ - - ret = nxsem_wait(&priv->toutsem); - if (ret) - { - tmrerr("ERROR: Wait priv->toutsem error=%d\n", ret); - ASSERT(0); - } - - flags = enter_critical_section(); - - /* Process all the timers in list */ - - while (!list_is_empty(&priv->toutlist)) - { - /* Get the first timer in the list */ - - timer = container_of(priv->toutlist.next, - struct rt_timer_s, list); - - /* Cache the raw state to decide how to deal with this timer */ - - raw_state = timer->state; - - /* Delete the timer from the list */ - - list_delete(&timer->list); - - /* Set timer's state to idle so it can be restarted by the user. */ - - timer->state = RT_TIMER_IDLE; - - leave_critical_section(flags); - - if (raw_state == RT_TIMER_TIMEOUT) - { - timer->callback(timer->arg); - } - else if (raw_state == RT_TIMER_DELETE) - { - kmm_free(timer); - } - - /* Enter critical section for next scanning list */ - - flags = enter_critical_section(); - - if (raw_state == RT_TIMER_TIMEOUT) - { - /* Check if the timer is in "repeat" mode */ - - if (timer->flags & RT_TIMER_REPEAT) - { - start_rt_timer(timer, timer->timeout, true); - } - } - } - - leave_critical_section(flags); - } - - return 0; -} - -/**************************************************************************** - * Name: rt_timer_isr - * - * Description: - * Hardware timer interrupt service routine. - * - * Input Parameters: - * irq - Not used - * context - Not used - * arg - Not used - * - * Returned Value: - * 0. - * - ****************************************************************************/ - -static int rt_timer_isr(int irq, void *context, void *arg) -{ - int ret; - irqstate_t flags; - struct rt_timer_s *timer; - uint64_t alarm; - uint64_t counter; - bool wake = false; - struct esp32s2_rt_priv_s *priv = &g_rt_priv; - - /* Clear interrupt register status */ - - ESP32S2_TIM_ACKINT(priv->timer); - - flags = enter_critical_section(); - - /* Check if there is a timer running */ - - if (!list_is_empty(&priv->runlist)) - { - /* When stop/delete timer, in the same time the hardware timer - * interrupt triggers, function "stop/delete" remove the timer - * from running list, so the 1st timer is not which triggers. - */ - - timer = container_of(priv->runlist.next, struct rt_timer_s, list); - ESP32S2_TIM_GETCTR(priv->timer, &counter); - counter = CYCLES_TO_USEC(counter); - if (timer->alarm <= counter) - { - /* Remove the first timer from the running list and add it to - * the timeout list. - * - * Set the timer's state to be RT_TIMER_TIMEOUT to avoid - * other operations. - */ - - list_delete(&timer->list); - timer->state = RT_TIMER_TIMEOUT; - list_add_after(&priv->toutlist, &timer->list); - wake = true; - - /* Check if there is a timer running */ - - if (!list_is_empty(&priv->runlist)) - { - /* Reset hardware timer alarm with next timer's alarm value */ - - timer = container_of(priv->runlist.next, - struct rt_timer_s, list); - alarm = timer->alarm; - - ESP32S2_TIM_SETALRM(priv->timer, false); - ESP32S2_TIM_SETALRVL(priv->timer, USEC_TO_CYCLES(alarm)); - } - } - - /* If there is a timer in the list, the alarm should be enabled */ - - ESP32S2_TIM_SETALRM(priv->timer, true); - } - - if (wake) - { - /* Wake up the thread to process timed-out timers */ - - ret = nxsem_post(&priv->toutsem); - if (ret < 0) - { - tmrerr("ERROR: Failed to post sem ret=%d\n", ret); - } - } - - leave_critical_section(flags); - - return 0; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: rt_timer_create - * - * Description: - * Create a RT timer from the provided arguments. - * - * Input Parameters: - * args - Input RT timer creation arguments - * timer_handle - Output RT timer handle pointer - * - * Returned Value: - * 0 is returned on success. Otherwise, a negated errno value is returned. - * - ****************************************************************************/ - -int rt_timer_create(const struct rt_timer_args_s *args, - struct rt_timer_s **timer_handle) -{ - struct rt_timer_s *timer; - - timer = kmm_malloc(sizeof(*timer)); - if (!timer) - { - tmrerr("ERROR: Failed to allocate %d bytes\n", sizeof(*timer)); - return -ENOMEM; - } - - timer->callback = args->callback; - timer->arg = args->arg; - timer->flags = RT_TIMER_NOFLAGS; - timer->state = RT_TIMER_IDLE; - list_initialize(&timer->list); - - *timer_handle = timer; - - return 0; -} - -/**************************************************************************** - * Name: rt_timer_start - * - * Description: - * Start the RT timer. - * - * Input Parameters: - * timer - RT timer pointer - * timeout - Timeout value - * repeat - repeat mode (true: enabled, false: disabled) - * - * Returned Value: - * None - * - ****************************************************************************/ - -void rt_timer_start(struct rt_timer_s *timer, - uint64_t timeout, - bool repeat) -{ - stop_rt_timer(timer); - - start_rt_timer(timer, timeout, repeat); -} - -/**************************************************************************** - * Name: rt_timer_stop - * - * Description: - * Stop the RT timer. - * - * Input Parameters: - * timer - RT timer pointer - * - * Returned Value: - * None - * - ****************************************************************************/ - -void rt_timer_stop(struct rt_timer_s *timer) -{ - stop_rt_timer(timer); -} - -/**************************************************************************** - * Name: rt_timer_delete - * - * Description: - * Stop and delete the RT timer. - * - * Input Parameters: - * timer - RT timer pointer - * - * Returned Value: - * None - * - ****************************************************************************/ - -void rt_timer_delete(struct rt_timer_s *timer) -{ - delete_rt_timer(timer); -} - -/**************************************************************************** - * Name: rt_timer_time_us - * - * Description: - * Get current counter value of the RT timer in microseconds. - * - * Input Parameters: - * None - * - * Returned Value: - * Time of the RT timer in microseconds. - * - ****************************************************************************/ - -uint64_t IRAM_ATTR rt_timer_time_us(void) -{ - uint64_t counter; - struct esp32s2_rt_priv_s *priv = &g_rt_priv; - - ESP32S2_TIM_GETCTR(priv->timer, &counter); - counter = CYCLES_TO_USEC(counter); - - return counter; -} - -/**************************************************************************** - * Name: rt_timer_get_alarm - * - * Description: - * Get the remaining time to the next timeout. - * - * Input Parameters: - * None - * - * Returned Value: - * Timestamp of the nearest timer event in microseconds. - * - ****************************************************************************/ - -uint64_t IRAM_ATTR rt_timer_get_alarm(void) -{ - irqstate_t flags; - uint64_t counter; - struct esp32s2_rt_priv_s *priv = &g_rt_priv; - uint64_t alarm_value = 0; - - flags = enter_critical_section(); - - ESP32S2_TIM_GETCTR(priv->timer, &counter); - counter = CYCLES_TO_USEC(counter); - ESP32S2_TIM_GETALRVL(priv->timer, &alarm_value); - alarm_value = CYCLES_TO_USEC(alarm_value); - - if (alarm_value <= counter) - { - alarm_value = 0; - } - else - { - alarm_value -= counter; - } - - leave_critical_section(flags); - - return alarm_value; -} - -/**************************************************************************** - * Name: rt_timer_calibration - * - * Description: - * Adjust current RT timer by a certain value. - * - * Input Parameters: - * time_us - adjustment to apply to the RT timer in microseconds. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void IRAM_ATTR rt_timer_calibration(uint64_t time_us) -{ - uint64_t counter; - struct esp32s2_rt_priv_s *priv = &g_rt_priv; - irqstate_t flags; - - flags = enter_critical_section(); - ESP32S2_TIM_GETCTR(priv->timer, &counter); - counter = CYCLES_TO_USEC(counter); - counter += time_us; - ESP32S2_TIM_SETCTR(priv->timer, USEC_TO_CYCLES(counter)); - ESP32S2_TIM_RLD_NOW(priv->timer); - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: esp32s2_rt_timer_init - * - * Description: - * Initialize ESP32-S2 RT timer. - * - * Input Parameters: - * None - * - * Returned Value: - * 0 is returned on success. Otherwise, a negated errno value is returned. - * - ****************************************************************************/ - -int esp32s2_rt_timer_init(void) -{ - int pid; - irqstate_t flags; - struct esp32s2_tim_dev_s *tim; - struct esp32s2_rt_priv_s *priv = &g_rt_priv; - uint32_t xtal_clk; - uint16_t pre; - uint16_t ticks; - - tim = esp32s2_tim_init(SYSTIMER_COMP0); - - if (tim == NULL) - { - tmrerr("ERROR: Failed to initialize ESP32-S2 Systimer 0\n"); - return -EINVAL; - } - - pid = kthread_create(RT_TIMER_TASK_NAME, - RT_TIMER_TASK_PRIORITY, - RT_TIMER_TASK_STACK_SIZE, - rt_timer_thread, - NULL); - if (pid < 0) - { - tmrerr("ERROR: Failed to create RT timer task error=%d\n", pid); - esp32s2_tim_deinit(tim); - return pid; - } - - list_initialize(&priv->runlist); - list_initialize(&priv->toutlist); - - priv->pid = (pid_t)pid; - priv->timer = tim; - - flags = enter_critical_section(); - - /* ESP32-S2 hardware timer configuration, acc. TRM V1.0 - * Systimer is clocked by APB_CLK. - * APB_CLK is determined by the source clock of CPU_CLK: - * CPU_CLK source | APB_CLK - * PLL_CLK | 80 MHz - * XTAL_CLK | CPU_CLK = XTAL_CLK / (SYSTEM_PRE_DIV_CNT + 1) - * The systimer period is determined by the step value. - * The step value is 1/(APB_CLK*ticks). - * On ESP32-S2, systimer has a mechanism that automatically - * detects which is the APB_CLK source and uses the step value - * configured for that specific source clock. - */ - - /* PLL step = 1/(80 MHz * t) s, t = 1 -> 80 cycles per us */ - - ESP32S2_TIM_SETSTEP(priv->timer, ESP32S2_TIM_PLL_CLK, 1); - - /* XTAL step = 1/((XTAL_CLK/(DIV +1)) * t) s - * To achieve the same 80 cycles per us, - * t = [(80 MHz * (DIV+1)) / XTAL_CLK] - * Example: XTAL_CLK = 40 MHz and DIV = 3, then t should be - * = ((80 MHz * 4) / 40 MHz) = 8. - */ - - xtal_clk = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_CLK_XTAL_FREQ); - pre = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT); - ticks = ((80 * (pre + 1)) / (xtal_clk)); - ESP32S2_TIM_SETSTEP(priv->timer, ESP32S2_TIM_XTAL_CLK, ticks); - - /* 1) Set Time-Delay work mode. - * 2) Clear the counter. - * 3) Set the ISR. - * 4) Enable timeout interrupt. - * 5) Start the counter. - * NOTE: No interrupt will be triggered until ESP32S2_TIM_SETALRM is set. - */ - - ESP32S2_TIM_SETWORKMODE(priv->timer, ESP32S2_TIM_DELAY_ALRM); - ESP32S2_TIM_CLEAR(priv->timer); - ESP32S2_TIM_SETISR(priv->timer, rt_timer_isr, NULL); - ESP32S2_TIM_ENABLEINT(priv->timer); - - leave_critical_section(flags); - - return 0; -} - -/**************************************************************************** - * Name: esp32s2_rt_timer_deinit - * - * Description: - * Deinitialize ESP32-S2 RT timer. - * - * Input Parameters: - * None - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp32s2_rt_timer_deinit(void) -{ - irqstate_t flags; - struct esp32s2_rt_priv_s *priv = &g_rt_priv; - - flags = enter_critical_section(); - - ESP32S2_TIM_DISABLEINT(priv->timer); - ESP32S2_TIM_SETISR(priv->timer, NULL, NULL); - esp32s2_tim_deinit(priv->timer); - priv->timer = NULL; - - leave_critical_section(flags); - - if (priv->pid != INVALID_PROCESS_ID) - { - kthread_delete(priv->pid); - priv->pid = INVALID_PROCESS_ID; - } -} diff --git a/arch/xtensa/src/esp32s2/esp32s2_rt_timer.h b/arch/xtensa/src/esp32s2/esp32s2_rt_timer.h deleted file mode 100644 index 62030d4e2d81b..0000000000000 --- a/arch/xtensa/src/esp32s2/esp32s2_rt_timer.h +++ /dev/null @@ -1,244 +0,0 @@ -/**************************************************************************** - * arch/xtensa/src/esp32s2/esp32s2_rt_timer.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_RT_TIMER_H -#define __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_RT_TIMER_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define RT_TIMER_NOFLAGS (0) /* Timer supports no feature */ -#define RT_TIMER_REPEAT (1 << 0) /* Timer supports repeat mode */ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/* RT timer state */ - -enum rt_timer_state_e -{ - RT_TIMER_IDLE, /* Timer is not counting */ - RT_TIMER_READY, /* Timer is counting */ - RT_TIMER_TIMEOUT, /* Timer timed out */ - RT_TIMER_DELETE /* Timer is to be delete */ -}; - -/* RT timer data structure */ - -struct rt_timer_s -{ - uint64_t timeout; /* Timeout value */ - uint64_t alarm; /* Timeout period */ - void (*callback)(void *arg); /* Callback function */ - void *arg; /* Private data */ - uint16_t flags; /* Supported features */ - enum rt_timer_state_e state; /* Timer state */ - struct list_node list; /* Working list */ -}; - -/* RT timer creation arguments data structure */ - -struct rt_timer_args_s -{ - void (*callback)(void *arg); /* Callback function */ - void *arg; /* Private data */ -}; - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: rt_timer_create - * - * Description: - * Create a RT timer from the provided arguments. - * - * Input Parameters: - * args - Input RT timer creation arguments - * timer_handle - Output RT timer handle pointer - * - * Returned Value: - * 0 is returned on success. Otherwise, a negated errno value is returned. - * - ****************************************************************************/ - -int rt_timer_create(const struct rt_timer_args_s *args, - struct rt_timer_s **timer_handle); - -/**************************************************************************** - * Name: rt_timer_start - * - * Description: - * Start the RT timer. - * - * Input Parameters: - * timer - RT timer pointer - * timeout - Timeout value - * repeat - repeat mode (true: enabled, false: disabled) - * - * Returned Value: - * None - * - ****************************************************************************/ - -void rt_timer_start(struct rt_timer_s *timer, - uint64_t timeout, - bool repeat); - -/**************************************************************************** - * Name: rt_timer_stop - * - * Description: - * Stop the RT timer. - * - * Input Parameters: - * timer - RT timer pointer - * - * Returned Value: - * None - * - ****************************************************************************/ - -void rt_timer_stop(struct rt_timer_s *timer); - -/**************************************************************************** - * Name: rt_timer_delete - * - * Description: - * Stop and delete the RT timer. - * - * Input Parameters: - * timer - RT timer pointer - * - * Returned Value: - * None - * - ****************************************************************************/ - -void rt_timer_delete(struct rt_timer_s *timer); - -/**************************************************************************** - * Name: rt_timer_time_us - * - * Description: - * Get time of the RT timer in microseconds. - * - * Input Parameters: - * None - * - * Returned Value: - * Time of the RT timer in microseconds. - * - ****************************************************************************/ - -uint64_t rt_timer_time_us(void); - -/**************************************************************************** - * Name: rt_timer_get_alarm - * - * Description: - * Get the timestamp when the next timeout is expected to occur. - * - * Input Parameters: - * None - * - * Returned Value: - * Timestamp of the nearest timer event in microseconds. - * - ****************************************************************************/ - -uint64_t rt_timer_get_alarm(void); - -/**************************************************************************** - * Name: rt_timer_calibration - * - * Description: - * Adjust current RT timer by a certain value. - * - * Input Parameters: - * time_us - adjustment to apply to the RT timer in microseconds. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void rt_timer_calibration(uint64_t time_us); - -/**************************************************************************** - * Name: esp32s2_rt_timer_init - * - * Description: - * Initialize ESP32-S2 RT timer. - * - * Input Parameters: - * None - * - * Returned Value: - * 0 is returned on success. Otherwise, a negated errno value is returned. - * - ****************************************************************************/ - -int esp32s2_rt_timer_init(void); - -/**************************************************************************** - * Name: esp32s2_rt_timer_deinit - * - * Description: - * Deinitialize ESP32-S2 RT timer. - * - * Input Parameters: - * None - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp32s2_rt_timer_deinit(void); - -#ifdef __cplusplus -} -#endif -#undef EXTERN - -#endif /* __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_RT_TIMER_H */ diff --git a/arch/xtensa/src/esp32s2/esp32s2_rtc.c b/arch/xtensa/src/esp32s2/esp32s2_rtc.c deleted file mode 100644 index 0778310fb6082..0000000000000 --- a/arch/xtensa/src/esp32s2/esp32s2_rtc.c +++ /dev/null @@ -1,2777 +0,0 @@ -/**************************************************************************** - * arch/xtensa/src/esp32s2/esp32s2_rtc.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include -#include - -#include "clock/clock.h" - -#include "esp32s2_clockconfig.h" -#include "esp32s2_rt_timer.h" - -#include "hardware/esp32s2_rtccntl.h" -#include "hardware/esp32s2_rtc_io.h" -#include "hardware/esp32s2_system.h" -#include "hardware/esp32s2_i2s.h" - -#include "hardware/esp32s2_rtccntl.h" -#include "hardware/esp32s2_rtc_io.h" -#include "hardware/esp32s2_system.h" -#include "hardware/esp32s2_tim.h" -#include "hardware/regi2c_ctrl.h" -#include "hardware/esp32s2_spi_mem_reg.h" -#include "hardware/esp32s2_syscon.h" -#include "hardware/regi2c_bbpll.h" -#include "hardware/regi2c_lp_bias.h" - -#include "xtensa.h" -#include "esp_attr.h" -#include "soc/extmem_reg.h" - -#include "esp32s2_rtc.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Various delays to be programmed into power control state machines */ - -#define RTC_CNTL_XTL_BUF_WAIT_SLP 2 -#define RTC_CNTL_CK8M_WAIT_SLP 4 -#define OTHER_BLOCKS_POWERUP 1 -#define OTHER_BLOCKS_WAIT 1 - -#define ROM_RAM_POWERUP_CYCLES OTHER_BLOCKS_POWERUP -#define ROM_RAM_WAIT_CYCLES OTHER_BLOCKS_WAIT - -#define WIFI_POWERUP_CYCLES OTHER_BLOCKS_POWERUP -#define WIFI_WAIT_CYCLES OTHER_BLOCKS_WAIT - -#define RTC_POWERUP_CYCLES OTHER_BLOCKS_POWERUP -#define RTC_WAIT_CYCLES OTHER_BLOCKS_WAIT - -#define DG_WRAP_POWERUP_CYCLES OTHER_BLOCKS_POWERUP -#define DG_WRAP_WAIT_CYCLES OTHER_BLOCKS_WAIT - -#define RTC_MEM_POWERUP_CYCLES OTHER_BLOCKS_POWERUP -#define RTC_MEM_WAIT_CYCLES OTHER_BLOCKS_WAIT - -#define RTC_CNTL_PLL_BUF_WAIT_SLP 2 - -#define DELAY_FAST_CLK_SWITCH 3 - -#define XTAL_32K_DAC_VAL 1 -#define XTAL_32K_DRES_VAL 3 -#define XTAL_32K_DBIAS_VAL 0 - -#define XTAL_32K_EXT_DAC_VAL 2 -#define XTAL_32K_EXT_DRES_VAL 3 -#define XTAL_32K_EXT_DBIAS_VAL 1 - -#define DELAY_SLOW_CLK_SWITCH 300 - -#define DELAY_8M_ENABLE 50 - -#define RETRY_CAL_EXT 1 - -/* Lower threshold for a reasonably-looking calibration value - * for a 32KHz XTAL. The ideal value (assuming 32768 Hz frequency) - * is 1000000/32768*(2**19) = 16*10^6. - */ - -#define MIN_32K_XTAL_CAL_VAL 15000000L - -/* Frequency of the 8M oscillator is 8.5MHz +/- 5%, at the default DCAP - * setting - */ - -#define RTC_FAST_CLK_FREQ_8M 8500000 -#define RTC_SLOW_CLK_FREQ_90K 90000 -#define RTC_SLOW_CLK_FREQ_8MD256 (RTC_FAST_CLK_FREQ_8M / 256) -#define RTC_SLOW_CLK_FREQ_32K 32768 - -/* Number of fractional bits in values returned by rtc_clk_cal */ - -#define RTC_CLK_CAL_FRACT 19 - -/* With the default value of CK8M_DFREQ, - * 8M clock frequency is 8.5 MHz +/- 7% - */ - -#define RTC_FAST_CLK_FREQ_APPROX 8500000 -#define RCT_FAST_D256_FREQ_APPROX (RTC_FAST_CLK_FREQ_APPROX / 256) -#define RTC_SLOW_CLK_FREQ_APPROX 32768 - -/* Disable logging from the ROM code. */ - -#define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16)) - -#define RTC_SLEEP_PD_DIG BIT(0) /* Deep sleep (power down - * digital domain) */ -#define RTC_SLEEP_PD_RTC_PERIPH BIT(1) /* Power down RTC peripherals */ -#define RTC_SLEEP_PD_RTC_SLOW_MEM BIT(2) /* Power down RTC SLOW memory */ -#define RTC_SLEEP_PD_RTC_FAST_MEM BIT(3) /* Power down RTC FAST memory */ -#define RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU BIT(4) /* RTC FAST and SLOW memories - * are automatically powered - * up and down along with the - * CPU */ -#define RTC_SLEEP_PD_VDDSDIO BIT(5) /* Power down VDDSDIO - * regulator */ -#define RTC_SLEEP_PD_WIFI BIT(6) /* Power down WIFI */ -#define RTC_SLEEP_PD_INT_8M BIT(7) /* Power down Internal 8M - * oscillator */ -#define RTC_SLEEP_PD_XTAL BIT(8) /* Power down main XTAL */ - -/* These flags are not power domains, but will affect some sleep parameters */ - -#define RTC_SLEEP_DIG_USE_8M BIT(16) -#define RTC_SLEEP_USE_ADC_TESEN_MONITOR BIT(17) -#define RTC_SLEEP_NO_ULTRA_LOW BIT(18) /* Avoid using ultra low - * power in deep sleep, in - * which RTCIO cannot be used - * as input, and RTCMEM can't - * work under high - * temperature */ - -#define is_dslp(pd_flags) ((pd_flags) & RTC_SLEEP_PD_DIG) - -/* set sleep_init default param. */ - -#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT 6 -#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP 0 -#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT 15 -#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_NODROP 0 -#define RTC_CNTL_BIASSLP_SLEEP_DEFAULT 1 -#define RTC_CNTL_BIASSLP_SLEEP_ON 0 -#define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1 -#define RTC_CNTL_PD_CUR_SLEEP_ON 0 - -#define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT 0 -#define RTC_CNTL_BIASSLP_MONITOR_DEFAULT 1 -#define RTC_CNTL_BIASSLP_MONITOR_ON 0 -#define RTC_CNTL_PD_CUR_MONITOR_DEFAULT 1 -#define RTC_CNTL_PD_CUR_MONITOR_ON 0 - -/* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP, - * RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values. - * Valid if RTC_CNTL_DBG_ATTEN is 0. - */ - -#define RTC_CNTL_DBIAS_0V90 0 /* Sleep dig_dbias & rtc_dbias */ -#define RTC_CNTL_DBIAS_0V95 1 /* Digital voltage */ -#define RTC_CNTL_DBIAS_1V00 2 -#define RTC_CNTL_DBIAS_1V05 3 -#define RTC_CNTL_DBIAS_1V10 4 -#define RTC_CNTL_DBIAS_1V15 5 -#define RTC_CNTL_DBIAS_1V20 6 -#define RTC_CNTL_DBIAS_1V25 7 /* Voltage is about 1.34v in fact */ - -/* Default initializer for esp32s2_rtc_sleep_config_t - * This initializer sets all fields to "reasonable" values - * (e.g. suggested for production use) based on a combination - * of RTC_SLEEP_PD_x flags. - */ - -#define RTC_SLEEP_CONFIG_DEFAULT(sleep_flags) { \ - .lslp_mem_inf_fpu = 0, \ - .rtc_mem_inf_follow_cpu = ((sleep_flags) & \ - RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU) ? 1 : 0, \ - .rtc_fastmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_FAST_MEM) ? 1 : 0, \ - .rtc_slowmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_SLOW_MEM) ? 1 : 0, \ - .rtc_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_PERIPH) ? 1 : 0, \ - .wifi_pd_en = (sleep_flags & RTC_SLEEP_PD_WIFI) ? 1 : 0, \ - .int_8m_pd_en = (sleep_flags & RTC_SLEEP_PD_INT_8M) ? 1 : 0, \ - .deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, \ - .wdt_flashboot_mod_en = 0, \ - .dig_dbias_wak = RTC_CNTL_DBIAS_1V10, \ - .dig_dbias_slp = is_dslp(sleep_flags) ? RTC_CNTL_DBIAS_SLP \ - : !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? \ - RTC_CNTL_DBIAS_1V10 : RTC_CNTL_DBIAS_SLP, \ - .rtc_dbias_slp = is_dslp(sleep_flags) ? RTC_CNTL_DBIAS_SLP \ - : !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? \ - RTC_CNTL_DBIAS_1V10 : RTC_CNTL_DBIAS_SLP, \ - .bias_sleep_monitor = 0, \ - .dbg_atten_slp = 0, \ - .pd_cur_monitor = 0, \ - .pd_cur_slp = 0, \ - .rtc_regulator_fpu = 0, \ - .rtc_dbias_wak = RTC_CNTL_DBIAS_1V10, \ - .vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, \ - .xtal_fpu = ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1, \ - .deep_slp_reject = 1, \ - .light_slp_reject = 1, \ -} - -#define X32K_CONFIG_DEFAULT() { \ - .dac = 3, \ - .dres = 3, \ - .dgm = 3, \ - .dbuf = 1, \ -} - -/* Initializer for rtc_sleep_pd_config_t which - * sets all flags to the same value - */ - -#define RTC_SLEEP_PD_CONFIG_ALL(val) { \ - .dig_fpu = (val), \ - .rtc_fpu = (val), \ - .cpu_fpu = (val), \ - .i2s_fpu = (val), \ - .bb_fpu = (val), \ - .nrx_fpu = (val), \ - .fe_fpu = (val), \ -} - -/* Default initializer of struct esp32s2_rtc_config_s. - * This initializer sets all fields to "reasonable" values - * (e.g. suggested for production use). - */ - -#define RTC_CONFIG_DEFAULT() { \ - .ck8m_wait = RTC_CNTL_CK8M_WAIT_DEFAULT, \ - .xtal_wait = RTC_CNTL_XTL_BUF_WAIT_DEFAULT, \ - .pll_wait = RTC_CNTL_PLL_BUF_WAIT_DEFAULT, \ - .clkctl_init = 1, \ - .pwrctl_init = 1, \ - .rtc_dboost_fpd = 1, \ - .xtal_fpu = 0, \ - .bbpll_fpu = 0, \ - .cpu_waiti_clk_gate = 1, \ - .cali_ocode = 0 \ -} - -/* The magic data for the struct esp32s2_rtc_backup_s that is in RTC slow - * memory. - */ - -#define MAGIC_RTC_SAVE UINT64_C(0x11223344556677) - -/* RTC Memory & Store Register usage */ - -#define RTC_SLOW_CLK_CAL_REG RTC_CNTL_STORE1_REG /* RTC_SLOW_CLK - * calibration value */ -#define RTC_BOOT_TIME_LOW_REG RTC_CNTL_STORE2_REG /* Boot time, low word */ -#define RTC_BOOT_TIME_HIGH_REG RTC_CNTL_STORE3_REG /* Boot time, high word */ -#define RTC_XTAL_FREQ_REG RTC_CNTL_STORE4_REG /* External XTAL - * frequency */ -#define RTC_APB_FREQ_REG RTC_CNTL_STORE5_REG /* APB bus frequency */ -#define RTC_ENTRY_ADDR_REG RTC_CNTL_STORE6_REG /* FAST_RTC_MEMORY_ENTRY */ -#define RTC_RESET_CAUSE_REG RTC_CNTL_STORE6_REG -#define RTC_MEMORY_CRC_REG RTC_CNTL_STORE7_REG /* FAST_RTC_MEMORY_CRC */ - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* RTC power and clock control initialization settings */ - -struct esp32s2_rtc_priv_s -{ - uint32_t ck8m_wait : 8; /* Number of rtc_fast_clk cycles to wait - * for 8M clock to be ready */ - uint32_t xtal_wait : 8; /* Number of rtc_fast_clk cycles to wait - * for XTAL clock to be ready */ - uint32_t pll_wait : 8; /* Number of rtc_fast_clk cycles to wait - * for PLL to be ready */ - uint32_t clkctl_init : 1; /* Perform clock control related - * initialization */ - uint32_t pwrctl_init : 1; /* Perform power control related - * initialization */ - uint32_t rtc_dboost_fpd : 1; /* Force power down RTC_DBOOST */ - uint32_t xtal_fpu : 1; - uint32_t bbpll_fpu : 1; - uint32_t cpu_waiti_clk_gate : 1; - uint32_t cali_ocode : 1; /* Calibrate Ocode to make bangap voltage - * more precise. */ -}; - -/* sleep configuration for rtc_sleep_init function */ - -struct esp32s2_rtc_sleep_config_s -{ - uint32_t lslp_mem_inf_fpu : 1; /* Force normal voltage in sleep mode - * (digital domain memory) */ - uint32_t rtc_mem_inf_follow_cpu : 1; /* Keep low voltage in sleep mode - * (even if ULP/touch is used) */ - uint32_t rtc_fastmem_pd_en : 1; /* Power down RTC fast memory */ - uint32_t rtc_slowmem_pd_en : 1; /* Power down RTC slow memory */ - uint32_t rtc_peri_pd_en : 1; /* Power down RTC peripherals */ - uint32_t wifi_pd_en : 1; /* Power down WiFi */ - uint32_t int_8m_pd_en : 1; /* Power down Internal 8M oscillator */ - uint32_t deep_slp : 1; /* Power down digital domain */ - uint32_t wdt_flashboot_mod_en : 1; /* Enable WDT flashboot mode */ - uint32_t dig_dbias_wak : 3; /* Set bias for digital domain, - * in active mode */ - uint32_t dig_dbias_slp : 3; /* Set bias for digital domain, - * in sleep mode */ - uint32_t rtc_dbias_wak : 3; /* Set bias for RTC domain, - * in active mode */ - uint32_t rtc_dbias_slp : 3; /* Set bias for RTC domain, - * in sleep mode */ - uint32_t bias_sleep_monitor : 1; /* Circuit control parameter, - * in monitor mode */ - uint32_t dbg_atten_slp : 4; /* Voltage parameter, in sleep mode */ - uint32_t bias_sleep_slp : 1; /* Circuit control parameter, - * in sleep mode */ - uint32_t pd_cur_monitor : 1; /* Circuit control parameter, - * in monitor mode */ - uint32_t pd_cur_slp : 1; /* Circuit control parameter, - * in sleep mode */ - uint32_t vddsdio_pd_en : 1; /* Power down VDDSDIO regulator */ - uint32_t xtal_fpu : 1; /* Keep main XTAL powered up in - * sleep */ - uint32_t rtc_regulator_fpu : 1; /* Keep rtc regulator powered up - * in sleep */ - uint32_t deep_slp_reject : 1; /* Enable deep sleep reject */ - uint32_t light_slp_reject : 1; /* Enable light sleep reject */ -}; - -/* Power down flags for rtc_sleep_pd function */ - -struct esp32s2_rtc_sleep_pd_config_s -{ - uint32_t dig_fpu : 1; /* Set to 1 to power down digital part in sleep */ - uint32_t rtc_fpu : 1; /* Set to 1 to power down RTC memories in sleep */ - uint32_t cpu_fpu : 1; /* Set to 1 to power down digital memories - * and CPU in sleep */ - uint32_t i2s_fpu : 1; /* Set to 1 to power down I2S in sleep */ - uint32_t bb_fpu : 1; /* Set to 1 to power down Wi-Fi in sleep */ - uint32_t nrx_fpu : 1; /* Set to 1 to power down Wi-Fi in sleep */ - uint32_t fe_fpu : 1; /* Set to 1 to power down Wi-Fi in sleep */ -}; - -#ifdef CONFIG_RTC_ALARM -struct alm_cbinfo_s -{ - struct rt_timer_s *alarm_hdl; /* Timer id point to here */ - volatile alm_callback_t ac_cb; /* Client callback function */ - volatile void *ac_arg; /* Argument to pass with the - * callback function */ - uint64_t deadline_us; - uint8_t index; -}; -#endif - -/* crystal configuration */ - -struct esp32s2_rtc_x32k_config_s -{ - uint32_t dac : 6; - uint32_t dres : 3; - uint32_t dgm : 3; - uint32_t dbuf: 1; -}; - -struct esp32s2_rtc_backup_s -{ - uint64_t magic; - int64_t offset; /* Offset time from RTC HW value */ - int64_t reserved0; -}; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* APB Frequency */ - -static uint32_t g_apb_freq; - -/* Callback to use when the alarm expires */ - -#ifdef CONFIG_RTC_ALARM -static struct alm_cbinfo_s g_alarmcb[RTC_ALARM_LAST]; -#endif - -static RTC_DATA_ATTR struct esp32s2_rtc_backup_s rtc_saved_data; - -/* Saved data for persistent RTC time */ - -static struct esp32s2_rtc_backup_s *g_rtc_save; -static bool g_rt_timer_enabled = false; -static spinlock_t g_rtc_lock = SP_UNLOCKED; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static void IRAM_ATTR esp32s2_rtc_sleep_pd( - struct esp32s2_rtc_sleep_pd_config_s cfg); -static inline bool esp32s2_clk_val_is_valid(uint32_t val); -static void IRAM_ATTR esp32s2_rtc_clk_fast_freq_set( - enum esp32s2_rtc_fast_freq_e fast_freq); -static uint32_t IRAM_ATTR esp32s2_rtc_clk_cal_internal( - enum esp32s2_rtc_cal_sel_e cal_clk, - uint32_t slowclk_cycles); -static int IRAM_ATTR esp32s2_rtc_clk_slow_freq_get(void); -static void IRAM_ATTR esp32s2_rtc_clk_slow_freq_set( - enum esp32s2_rtc_slow_freq_e slow_freq); -static void esp32s2_select_rtc_slow_clk(enum esp32s2_slow_clk_sel_e - slow_clk); -static void esp32s2_rtc_clk_32k_enable(bool enable); -static void IRAM_ATTR esp32s2_rtc_clk_8m_enable(bool clk_8m_en, - bool d256_en); -static void esp32s2_rtc_calibrate_ocode(void); -static void IRAM_ATTR esp32s2_rtc_clk_bbpll_disable(void); -static void IRAM_ATTR esp32s2_rtc_bbpll_configure( - enum esp32s2_rtc_xtal_freq_e xtal_freq, int pll_freq); -static void IRAM_ATTR esp32s2_rtc_clk_cpu_freq_to_8m(void); -static void IRAM_ATTR esp32s2_rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz); - -void IRAM_ATTR esp32s2_rtc_bbpll_disable(void); -void esp32s2_rtc_clk_apb_freq_update(uint32_t apb_freq); -void IRAM_ATTR esp32s2_rtc_update_to_xtal(int freq, int div); -static void esp32s2_wait_dig_dbias_valid(uint64_t rtc_cycles); -uint32_t esp32s2_rtc_clk_apb_freq_get(void); - -#ifdef CONFIG_RTC_ALARM -static void IRAM_ATTR esp32s2_rt_cb_handler(void *arg); -#endif -/**************************************************************************** - * Public Data - ****************************************************************************/ - -volatile bool g_rtc_enabled = false; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/* Set the real CPU ticks per us to the ets, so that ets_delay_us - * will be accurate. Call this function when CPU frequency is changed. - */ - -extern void ets_update_cpu_frequency(uint32_t ticks_per_us); - -/**************************************************************************** - * Name: esp32s2_rtc_sleep_pd - * - * Description: - * Configure whether certain peripherals are powered up in deep sleep. - * - * Input Parameters: - * cfg - power down flags as rtc_sleep_pu_config_t structure - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void IRAM_ATTR - esp32s2_rtc_sleep_pd(struct esp32s2_rtc_sleep_pd_config_s cfg) -{ - REG_SET_FIELD(RTC_CNTL_DIG_PWC_REG, - RTC_CNTL_LSLP_MEM_FORCE_PU, cfg.dig_fpu); - REG_SET_FIELD(RTC_CNTL_PWC_REG, - RTC_CNTL_FASTMEM_FORCE_LPU, cfg.rtc_fpu); - REG_SET_FIELD(RTC_CNTL_PWC_REG, - RTC_CNTL_SLOWMEM_FORCE_LPU, cfg.rtc_fpu); - REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG, - SYSCON_DC_MEM_FORCE_PU, cfg.fe_fpu); - REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG, - SYSCON_PBUS_MEM_FORCE_PU, cfg.fe_fpu); - REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG, - SYSCON_AGC_MEM_FORCE_PU, cfg.fe_fpu); - REG_SET_FIELD(BBPD_CTRL, BB_FFT_FORCE_PU, cfg.bb_fpu); - REG_SET_FIELD(BBPD_CTRL, BB_DC_EST_FORCE_PU, cfg.bb_fpu); - REG_SET_FIELD(NRXPD_CTRL, NRX_RX_ROT_FORCE_PU, cfg.nrx_fpu); - REG_SET_FIELD(NRXPD_CTRL, NRX_VIT_FORCE_PU, cfg.nrx_fpu); - REG_SET_FIELD(NRXPD_CTRL, NRX_DEMAP_FORCE_PU, cfg.nrx_fpu); - REG_SET_FIELD(FE_GEN_CTRL, FE_IQ_EST_FORCE_PU, cfg.fe_fpu); - REG_SET_FIELD(FE2_TX_INTERP_CTRL, FE2_TX_INF_FORCE_PU, cfg.fe_fpu); -} - -/**************************************************************************** - * Name: esp32s2_rtc_clk_fast_freq_set - * - * Description: - * Select source for RTC_FAST_CLK. - * - * Input Parameters: - * fast_freq - Clock source (one of enum esp32s2_rtc_fast_freq_e values) - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void IRAM_ATTR esp32s2_rtc_clk_fast_freq_set( - enum esp32s2_rtc_fast_freq_e fast_freq) -{ - REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL, - fast_freq); - up_udelay(DELAY_FAST_CLK_SWITCH); -} - -/**************************************************************************** - * Name: esp32s2_clk_val_is_valid - * - * Description: - * Values of RTC_XTAL_FREQ_REG and RTC_APB_FREQ_REG are - * stored as two copies in lower and upper 16-bit halves. - * These are the routines to work with such a representation. - * - * Input Parameters: - * val - register value - * - * Returned Value: - * true: Valid register value. - * false: Invalid register value. - * - ****************************************************************************/ - -static inline bool esp32s2_clk_val_is_valid(uint32_t val) -{ - return (val & 0xffff) == ((val >> 16) & 0xffff) - && val != 0 && val != UINT32_MAX; -} - -/**************************************************************************** - * Name: esp32s2_rtc_clk_cal_internal - * - * Description: - * Clock calibration function used by rtc_clk_cal and rtc_clk_cal_ratio - * - * Input Parameters: - * cal_clk - which clock to calibrate - * slowclk_cycles - number of slow clock cycles to count. - * - * Returned Value: - * Number of XTAL clock cycles within the given number of slow clock - * cycles. - * In case of error, return 0 cycle. - * - ****************************************************************************/ - -static uint32_t IRAM_ATTR esp32s2_rtc_clk_cal_internal( - enum esp32s2_rtc_cal_sel_e cal_clk, uint32_t slowclk_cycles) -{ - uint32_t expected_freq; - uint32_t us_time_estimate; - uint32_t clks_state; - uint32_t clks_mask; - uint32_t cal_val; - enum esp32s2_rtc_slow_freq_e slow_freq; - - /* Get the current state */ - - clks_mask = (RTC_CNTL_DIG_XTAL32K_EN_M | RTC_CNTL_DIG_CLK8M_D256_EN_M); - clks_state = getreg32(RTC_CNTL_CLK_CONF_REG); - clks_state &= clks_mask; - - /* On ESP32S2, choosing RTC_CAL_RTC_MUX results in calibration of - * the 150k RTC clock regardless of the currently selected SLOW_CLK. - * The following code emulates ESP32 behavior - */ - - if (cal_clk == RTC_CAL_RTC_MUX) - { - slow_freq = esp32s2_rtc_clk_slow_freq_get(); - if (slow_freq == RTC_SLOW_FREQ_32K_XTAL) - { - cal_clk = RTC_CAL_32K_XTAL; - } - else if (slow_freq == RTC_SLOW_FREQ_8MD256) - { - cal_clk = RTC_CAL_8MD256; - } - } - else if (cal_clk == RTC_CAL_INTERNAL_OSC) - { - cal_clk = RTC_CAL_RTC_MUX; - } - - /* Enable requested clock (150k clock is always on) */ - - if (cal_clk == RTC_CAL_32K_XTAL && !(clks_state & RTC_CNTL_DIG_XTAL32K_EN)) - { - REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN, 1); - } - else if (cal_clk == RTC_CAL_8MD256 && - !(clks_state & RTC_CNTL_DIG_CLK8M_D256_EN)) - { - modifyreg32(RTC_CNTL_CLK_CONF_REG, 0, RTC_CNTL_DIG_CLK8M_D256_EN); - } - - /* Prepare calibration */ - - REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, cal_clk); - modifyreg32(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING, 0); - REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, slowclk_cycles); - - /* Figure out how long to wait for calibration to finish */ - - slow_freq = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, - RTC_CNTL_ANA_CLK_RTC_SEL); - - if (cal_clk == RTC_CAL_32K_XTAL || slow_freq == RTC_SLOW_FREQ_32K_XTAL) - { - expected_freq = 32768; /* Standard 32KHz XTAL */ - } - else if (cal_clk == RTC_CAL_8MD256 || slow_freq == RTC_SLOW_FREQ_8MD256) - { - expected_freq = RTC_FAST_CLK_FREQ_APPROX / 256; - } - else - { - expected_freq = 150000; /* 150k internal oscillator */ - } - - us_time_estimate = (uint32_t) (((uint64_t)slowclk_cycles) * - MHZ / expected_freq); - - /* Start calibration */ - - modifyreg32(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START, 0); - modifyreg32(TIMG_RTCCALICFG_REG(0), 0, TIMG_RTC_CALI_START); - - /* Wait the expected time calibration should take */ - - up_udelay(us_time_estimate); - - /* Wait for calibration to finish up to another us_time_estimate */ - - while (true) - { - if (getreg32(TIMG_RTCCALICFG_REG(0)) & TIMG_RTC_CALI_RDY) - { - cal_val = REG_GET_FIELD(TIMG_RTCCALICFG1_REG(0), - TIMG_RTC_CALI_VALUE); - break; - } - - if (GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT)) - { - cal_val = 0; - break; - } - } - - CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START); - - /* Restore the previous clocks states */ - - modifyreg32(RTC_CNTL_CLK_CONF_REG, clks_mask, clks_state); - - return cal_val; -} - -/**************************************************************************** - * Name: esp32s2_wait_dig_dbias_valid - * - * Description: - * Wait digtial dbias valid - * - * Input Parameters: - * rtc_cycles - RTC count - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void esp32s2_wait_dig_dbias_valid(uint64_t rtc_cycles) -{ - int slow_clk_freq = esp32s2_rtc_clk_slow_freq_get(); - int cal_clk = RTC_CAL_RTC_MUX; - - if (slow_clk_freq == RTC_SLOW_FREQ_32K_XTAL) - { - cal_clk = RTC_CAL_32K_XTAL; - } - else if (slow_clk_freq == RTC_SLOW_FREQ_8MD256) - { - cal_clk = RTC_CAL_8MD256; - } - - esp32s2_rtc_clk_cal(cal_clk, rtc_cycles); -} - -/**************************************************************************** - * Name: esp32s2_rtc_update_to_xtal - * - * Description: - * Switch to XTAL frequency, does not disable the PLL - * - * Input Parameters: - * freq - XTAL frequency - * div - REF_TICK divider - * - * Returned Value: - * none - * - ****************************************************************************/ - -void IRAM_ATTR esp32s2_rtc_update_to_xtal(int freq, int div) -{ - ets_update_cpu_frequency(freq); - esp32s2_wait_dig_dbias_valid(2); - - /* Set divider from XTAL to APB clock. - * Need to set divider to 1 (reg. value 0) first. - */ - - REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT, 0); - REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT, div - 1); - - /* No need to adjust the REF_TICK. - * Switch clock source. - */ - - REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, - SYSTEM_SOC_CLK_SEL, DPORT_SOC_CLK_SEL_XTAL); - - esp32s2_rtc_clk_apb_freq_update(freq * MHZ); -} - -/**************************************************************************** - * Name: esp32s2_rtc_clk_slow_freq_set - * - * Description: - * Select source for RTC_SLOW_CLK - * - * Input Parameters: - * slow_freq - Select source for RTC_SLOW_CLK - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void IRAM_ATTR esp32s2_rtc_clk_slow_freq_set( - enum esp32s2_rtc_slow_freq_e slow_freq) -{ - REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL, - slow_freq); - - REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN, - (slow_freq == RTC_SLOW_FREQ_32K_XTAL) ? 1 : 0); - - up_udelay(DELAY_SLOW_CLK_SWITCH); -} - -/**************************************************************************** - * Name: esp32s2_rtc_clk_32k_enable - * - * Description: - * Enable 32 KHz XTAL oscillator - * - * Input Parameters: - * enable - boolean Enable/Disable - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void IRAM_ATTR esp32s2_rtc_clk_32k_enable(bool enable) -{ - if (enable) - { - struct esp32s2_rtc_x32k_config_s cfg = X32K_CONFIG_DEFAULT(); - - modifyreg32(RTCIO_XTAL_32P_PAD_REG, 0, RTCIO_X32P_MUX_SEL); - modifyreg32(RTCIO_XTAL_32N_PAD_REG, 0, RTCIO_X32N_MUX_SEL); - - REG_SET_FIELD(RTC_CNTL_EXT_XTL_CONF_REG, - RTC_CNTL_DAC_XTAL_32K, cfg.dac); - REG_SET_FIELD(RTC_CNTL_EXT_XTL_CONF_REG, - RTC_CNTL_DRES_XTAL_32K, cfg.dres); - REG_SET_FIELD(RTC_CNTL_EXT_XTL_CONF_REG, - RTC_CNTL_DGM_XTAL_32K, cfg.dgm); - REG_SET_FIELD(RTC_CNTL_EXT_XTL_CONF_REG, - RTC_CNTL_DBUF_XTAL_32K, cfg.dbuf); - modifyreg32(RTC_CNTL_EXT_XTL_CONF_REG, 0, - RTC_CNTL_XPD_XTAL_32K); - } - else - { - modifyreg32(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_XPD_XTAL_32K, - RTC_CNTL_XTAL32K_XPD_FORCE); - } -} - -/**************************************************************************** - * Name: esp32s2_rtc_clk_8m_enable - * - * Description: - * Enable or disable 8 MHz internal oscillator - * - * Input Parameters: - * clk_8m_en - true to enable 8MHz generator, false to disable - * d256_en - true to enable /256 divider, false to disable - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void IRAM_ATTR esp32s2_rtc_clk_8m_enable(bool clk_8m_en, bool d256_en) -{ - if (clk_8m_en) - { - modifyreg32(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M, 0); - - /* No need to wait once enabled by software */ - - REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, 1); - if (d256_en) - { - modifyreg32(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV, 0); - } - else - { - modifyreg32(RTC_CNTL_CLK_CONF_REG, 0, RTC_CNTL_ENB_CK8M_DIV); - } - - up_udelay(DELAY_8M_ENABLE); - } - else - { - modifyreg32(RTC_CNTL_CLK_CONF_REG, 0, RTC_CNTL_ENB_CK8M); - REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, - RTC_CNTL_CK8M_WAIT_DEFAULT); - } -} - -/**************************************************************************** - * Name: esp32s2_select_rtc_slow_clk - * - * Description: - * Selects an clock source for RTC. - * - * Input Parameters: - * slow_clk - RTC SLOW_CLK frequency values - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void esp32s2_select_rtc_slow_clk(enum esp32s2_slow_clk_sel_e slow_clk) -{ - /* Number of times to repeat 32KHz XTAL calibration before giving up and - * switching to the internal RC. - */ - - int retry_32k_xtal = 0; - uint32_t cal_val = 0; - uint64_t cal_dividend; - enum esp32s2_rtc_slow_freq_e rtc_slow_freq = slow_clk & - RTC_CNTL_ANA_CLK_RTC_SEL_V; - - do - { - if (rtc_slow_freq == RTC_SLOW_FREQ_32K_XTAL) - { - /* 32KHz XTAL oscillator needs to be enabled and running before - * it can be used. Hardware doesn't have a direct way of checking - * if the oscillator is running. Here we use rtc_clk_cal function - * to count the number of main XTAL cycles in the given number of - * 32KHz XTAL oscillator cycles. If the 32KHz XTAL has not - * started up, calibration will time out, returning 0. - */ - - rtcinfo("Waiting for 32KHz oscillator to start up\n"); - if (slow_clk == SLOW_CLK_32K_XTAL || - slow_clk == SLOW_CLK_32K_EXT_OSC) - { - esp32s2_rtc_clk_32k_enable(true); - } - - if (SLOW_CLK_CAL_CYCLES > 0) - { - cal_val = esp32s2_rtc_clk_cal(RTC_CAL_32K_XTAL, - SLOW_CLK_CAL_CYCLES); - if (cal_val == 0 || cal_val < MIN_32K_XTAL_CAL_VAL) - { - if (retry_32k_xtal-- > 0) - { - continue; - } - - rtc_slow_freq = RTC_SLOW_FREQ_RTC; - } - } - } - else if (rtc_slow_freq == RTC_SLOW_FREQ_8MD256) - { - esp32s2_rtc_clk_8m_enable(true, true); - } - - esp32s2_rtc_clk_slow_freq_set(rtc_slow_freq); - if (SLOW_CLK_CAL_CYCLES > 0) - { - /* 32KHz XTAL oscillator has some frequency drift at startup. - * Improve calibration routine to wait until - * the frequency is stable. - */ - - cal_val = esp32s2_rtc_clk_cal(RTC_CAL_RTC_MUX, - SLOW_CLK_CAL_CYCLES); - } - else - { - cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL; - cal_val = (uint32_t)(cal_dividend / - esp32s2_rtc_clk_slow_freq_get_hz()); - } - - retry_32k_xtal++; - } - while (cal_val == 0 && retry_32k_xtal < RETRY_CAL_EXT); - rtcinfo("RTC_SLOW_CLK calibration value: %" PRIu32 "\n", cal_val); - putreg32((uint32_t)cal_val, RTC_SLOW_CLK_CAL_REG); -} - -/**************************************************************************** - * Name: esp32s2_rtc_clk_cpu_freq_to_8m - * - * Description: - * Switch CPU frequency to 8 Mhz. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void IRAM_ATTR esp32s2_rtc_clk_cpu_freq_to_8m(void) -{ - int origin_soc_clk = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, - SYSTEM_SOC_CLK_SEL); - int origin_div_cnt = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, - SYSTEM_PRE_DIV_CNT); - ets_update_cpu_frequency(8); - REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_XTAL); - - esp32s2_wait_dig_dbias_valid(2); - - if ((DPORT_SOC_CLK_SEL_XTAL == origin_soc_clk) - && (origin_div_cnt > 4)) - { - esp32s2_wait_dig_dbias_valid(2); - } - - REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT, 0); - REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL, - DPORT_SOC_CLK_SEL_8M); - esp32s2_rtc_clk_apb_freq_update(RTC_FAST_CLK_FREQ_APPROX); -} - -/**************************************************************************** - * Name: esp32s2_rtc_clk_cpu_freq_to_pll_mhz - * - * Description: - * Switch to one of PLL-based frequencies. - * - * Input Parameters: - * cpu_freq_mhz - CPU frequency - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void IRAM_ATTR esp32s2_rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz) -{ - int origin_soc_clk = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, - SYSTEM_SOC_CLK_SEL); - int origin_cpuperiod_sel = REG_GET_FIELD(SYSTEM_CPU_PER_CONF_REG, - SYSTEM_CPUPERIOD_SEL); - int dbias = DIG_DBIAS_80M_160M; - int per_conf = DPORT_CPUPERIOD_SEL_80; - if (cpu_freq_mhz == 80) - { - /* Nothing to do */ - } - else if (cpu_freq_mhz == 160) - { - dbias = DIG_DBIAS_80M_160M; - per_conf = DPORT_CPUPERIOD_SEL_160; - } - else if (cpu_freq_mhz == 240) - { - dbias = DIG_DBIAS_240M; - per_conf = DPORT_CPUPERIOD_SEL_240; - } - else - { - rtcerr("Invalid frequency\n"); - } - - REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, dbias); - REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_WAK, dbias); - - if ((origin_soc_clk == DPORT_SOC_CLK_SEL_XTAL) - || (origin_soc_clk == DPORT_SOC_CLK_SEL_8M) - || (((origin_soc_clk == DPORT_SOC_CLK_SEL_PLL) - && (0 == origin_cpuperiod_sel)))) - { - esp32s2_wait_dig_dbias_valid(2); - } - - REG_SET_FIELD(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPUPERIOD_SEL, per_conf); - REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT, 0); - REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL, - DPORT_SOC_CLK_SEL_PLL); - esp32s2_rtc_clk_apb_freq_update(80 * MHZ); - ets_update_cpu_frequency(cpu_freq_mhz); -} - -#ifdef CONFIG_RTC_ALARM - -/**************************************************************************** - * Name: esp32s2_rt_cb_handler - * - * Description: - * RT-Timer service routine - * - * Input Parameters: - * arg - Information about the RT-Timer configuration. - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void IRAM_ATTR esp32s2_rt_cb_handler(void *arg) -{ - struct alm_cbinfo_s *cbinfo = (struct alm_cbinfo_s *)arg; - alm_callback_t cb; - void *cb_arg; - int alminfo_id; - - DEBUGASSERT(cbinfo != NULL); - alminfo_id = cbinfo->index; - DEBUGASSERT((RTC_ALARM0 <= alminfo_id) && - (alminfo_id < RTC_ALARM_LAST)); - - if (cbinfo->ac_cb != NULL) - { - /* Alarm callback */ - - cb = cbinfo->ac_cb; - cb_arg = (void *)cbinfo->ac_arg; - cbinfo->ac_cb = NULL; - cbinfo->ac_arg = NULL; - cbinfo->deadline_us = 0; - cb(cb_arg, alminfo_id); - } -} - -#endif /* CONFIG_RTC_ALARM */ - -/**************************************************************************** - * Name: esp32s2_rtc_calibrate_ocode - * - * Description: - * Calibrate o-code by software - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void esp32s2_rtc_calibrate_ocode(void) -{ - uint64_t cycle0; - uint64_t timeout_cycle; - uint32_t slow_clk_period; - uint64_t max_delay_cycle; - bool odone_flag = 0; - bool bg_odone_flag = 0; - uint64_t cycle1 = 0; - uint64_t max_delay_time_us = 10000; - struct esp32s2_cpu_freq_config_s freq_config; - - /* Band gap output voltage is sometimes not precise when calibrating - * the o-code by hardware, so we need a software o-code calibration - * (must turn off PLL). - * Method: - * 1. Read current cpu config, save in old_config - * 2. Switch cpu to xtal because PLL will be closed when o-code calibration - * 3. Begin o-code calibration - * 4. Wait o-code calibration done flag or timeout - * 5. Set cpu to old-config - */ - - enum esp32s2_rtc_slow_freq_e slow_clk_freq = - esp32s2_rtc_clk_slow_freq_get(); - enum esp32s2_rtc_slow_freq_e rtc_slow_freq_x32k = - RTC_SLOW_FREQ_32K_XTAL; - enum esp32s2_rtc_slow_freq_e rtc_slow_freq_8md256 = - RTC_SLOW_FREQ_8MD256; - enum esp32s2_rtc_cal_sel_e cal_clk = RTC_CAL_RTC_MUX; - if (slow_clk_freq == rtc_slow_freq_x32k) - { - cal_clk = RTC_CAL_32K_XTAL; - } - else if (slow_clk_freq == rtc_slow_freq_8md256) - { - cal_clk = RTC_CAL_8MD256; - } - - slow_clk_period = esp32s2_rtc_clk_cal(cal_clk, 100); - max_delay_cycle = esp32s2_rtc_time_us_to_slowclk(max_delay_time_us, - slow_clk_period); - cycle0 = esp32s2_rtc_time_get(); - timeout_cycle = cycle0 + max_delay_cycle; - - esp32s2_rtc_clk_cpu_freq_get_config(&freq_config); - esp32s2_rtc_cpu_freq_set_xtal(); - REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_RESETB, 0); - REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_RESETB, 1); - while (1) - { - odone_flag = REGI2C_READ_MASK(I2C_ULP, I2C_ULP_O_DONE_FLAG); - bg_odone_flag = REGI2C_READ_MASK(I2C_ULP, I2C_ULP_BG_O_DONE_FLAG); - cycle1 = esp32s2_rtc_time_get(); - if (odone_flag && bg_odone_flag) - { - break; - } - - if (cycle1 >= timeout_cycle) - { - break; - } - } - - esp32s2_rtc_clk_cpu_freq_set_config(&freq_config); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32s2_rtc_clk_slow_freq_get_hz - * - * Description: - * Get the approximate frequency of RTC_SLOW_CLK, in Hz - * - * Input Parameters: - * None - * - * Returned Value: - * RTC_SLOW_CLK frequency, in Hz - * - ****************************************************************************/ - -static int IRAM_ATTR esp32s2_rtc_clk_slow_freq_get(void) -{ - return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL); -} - -/**************************************************************************** - * Name: esp32s2_rtc_clk_slow_freq_get_hz - * - * Description: - * Get the approximate frequency of RTC_SLOW_CLK, in Hz - * - * Input Parameters: - * None - * - * Returned Value: - * RTC_SLOW_CLK frequency, in Hz - * - ****************************************************************************/ - -uint32_t IRAM_ATTR esp32s2_rtc_clk_slow_freq_get_hz(void) -{ - enum esp32s2_rtc_slow_freq_e slow_clk_freq = - REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, - RTC_CNTL_ANA_CLK_RTC_SEL); - switch (slow_clk_freq) - { - case RTC_SLOW_FREQ_RTC: - return RTC_SLOW_CLK_FREQ_APPROX; - - case RTC_SLOW_FREQ_32K_XTAL: - return RTC_SLOW_CLK_FREQ_APPROX; - - case RTC_SLOW_FREQ_8MD256: - return RCT_FAST_D256_FREQ_APPROX; - } - - return OK; -} - -/**************************************************************************** - * Name: esp32s2_rtc_clk_fast_freq_get_hz - * - * Description: - * Get fast_clk_rtc source in Hz. - * - * Input Parameters: - * None - * - * Returned Value: - * The clock source in Hz. - * - ****************************************************************************/ - -uint32_t IRAM_ATTR esp32s2_rtc_clk_fast_freq_get_hz(void) -{ - return RTC_FAST_CLK_FREQ_APPROX; -} - -/**************************************************************************** - * Name: esp32s2_rtc_get_slow_clk_rtc - * - * Description: - * Get slow_clk_rtc source. - * - * Input Parameters: - * None - * - * Returned Value: - * The clock source: - * - SLOW_CK - * - CK_XTAL_32K - * - CK8M_D256_OUT - * - ****************************************************************************/ - -enum esp32s2_rtc_slow_freq_e IRAM_ATTR esp32s2_rtc_get_slow_clk(void) -{ - enum esp32s2_rtc_slow_freq_e slow_freq; - - /* Get the clock source for slow_clk_rtc */ - - slow_freq = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, - RTC_CNTL_ANA_CLK_RTC_SEL); - - return slow_freq; -} - -/**************************************************************************** - * Name: esp32s2_rtc_clk_cal - * - * Description: - * Measure RTC slow clock's period, based on main XTAL frequency - * - * Input Parameters: - * cal_clk - clock to be measured - * slowclk_cycles - number of slow clock cycles what is to be averaged - * - * Returned Value: - * Average slow clock period in microseconds, Q13.19 fixed point format - * or 0 if calibration has timed out - * - ****************************************************************************/ - -uint32_t IRAM_ATTR esp32s2_rtc_clk_cal(enum esp32s2_rtc_cal_sel_e cal_clk, - uint32_t slowclk_cycles) -{ - enum esp32s2_rtc_xtal_freq_e xtal_freq; - uint64_t xtal_cycles; - uint64_t divider; - uint64_t period_64; - uint32_t period; - - xtal_freq = esp32s2_rtc_clk_xtal_freq_get(); - xtal_cycles = esp32s2_rtc_clk_cal_internal(cal_clk, slowclk_cycles); - divider = ((uint64_t)xtal_freq) * slowclk_cycles; - period_64 = ((xtal_cycles << RTC_CLK_CAL_FRACT) + divider / 2 - 1) - / divider; - period = (uint32_t)(period_64 & UINT32_MAX); - - return period; -} - -/**************************************************************************** - * Name: esp32s2_rtc_clk_xtal_freq_get - * - * Description: - * Get main XTAL frequency - * - * Input Parameters: - * None - * - * Returned Value: - * XTAL frequency (one of enum esp32s2_rtc_xtal_freq_e values) - * - ****************************************************************************/ - -enum esp32s2_rtc_xtal_freq_e IRAM_ATTR esp32s2_rtc_clk_xtal_freq_get(void) -{ - /* We may have already written XTAL value into RTC_XTAL_FREQ_REG */ - - uint32_t xtal_freq_reg = getreg32(RTC_XTAL_FREQ_REG); - - if (!esp32s2_clk_val_is_valid(xtal_freq_reg)) - { - return RTC_XTAL_FREQ_40M; - } - - return (xtal_freq_reg & ~RTC_DISABLE_ROM_LOG) & UINT16_MAX; -} - -/**************************************************************************** - * Name: esp32s2_rtc_clk_bbpll_disable - * - * Description: - * disable BBPLL. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void IRAM_ATTR esp32s2_rtc_clk_bbpll_disable(void) -{ - modifyreg32(RTC_CNTL_OPTIONS0_REG, 0, RTC_CNTL_BB_I2C_FORCE_PD | - RTC_CNTL_BBPLL_FORCE_PD | RTC_CNTL_BBPLL_I2C_FORCE_PD); -} - -/**************************************************************************** - * Name: esp32s2_rtc_bbpll_configure - * - * Description: - * Configure main XTAL frequency values according to pll_freq. - * - * Input Parameters: - * xtal_freq - XTAL frequency values - * pll_freq - PLL frequency values - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void IRAM_ATTR esp32s2_rtc_bbpll_configure( - enum esp32s2_rtc_xtal_freq_e xtal_freq, int pll_freq) -{ - static uint8_t div_ref = 0; - static uint8_t div7_0 = 0; - static uint8_t dr1 = 0 ; - static uint8_t dr3 = 0 ; - static uint8_t dchgp = 0; - static uint8_t dcur = 0; - uint8_t i2c_bbpll_lref = 0; - uint8_t i2c_bbpll_div_7_0 = 0; - uint8_t i2c_bbpll_dcur = 0; - - if (pll_freq == RTC_PLL_FREQ_480M) - { - /* Set this register to let the digital part know 480M PLL is used */ - - modifyreg32(SYSTEM_CPU_PER_CONF_REG, 0, SYSTEM_PLL_FREQ_SEL); - - /* Configure 480M PLL */ - - div_ref = 0; - div7_0 = 8; - dr1 = 0; - dr3 = 0; - dchgp = 5; - dcur = 4; - REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_MODE_HF, 0x6b); - } - else - { - /* Clear this register to let the digital part know 320M PLL is used */ - - modifyreg32(SYSTEM_CPU_PER_CONF_REG, SYSTEM_PLL_FREQ_SEL, 0); - - /* Configure 320M PLL */ - - div_ref = 0; - div7_0 = 4; - dr1 = 0; - dr3 = 0; - dchgp = 5; - dcur = 5; - REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_MODE_HF, 0x69); - } - - i2c_bbpll_lref = (dchgp << I2C_BBPLL_OC_DCHGP_LSB) | (div_ref); - i2c_bbpll_div_7_0 = div7_0; - i2c_bbpll_dcur = (1 << I2C_BBPLL_OC_DLREF_SEL_LSB) | - (2 << I2C_BBPLL_OC_DHREF_SEL_LSB) | dcur; - - REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_REF_DIV, i2c_bbpll_lref); - REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_DIV_7_0, i2c_bbpll_div_7_0); - REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DR1, dr1); - REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DR3, dr3); - REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_DCUR, i2c_bbpll_dcur); - REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DHREF_SEL, 2); - REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DLREF_SEL, 1); -} - -/**************************************************************************** - * Name: esp32s2_rtc_clk_set - * - * Description: - * Set RTC CLK frequency. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32s2_rtc_clk_set(void) -{ - enum esp32s2_rtc_fast_freq_e fast_freq = RTC_FAST_FREQ_8M; - enum esp32s2_slow_clk_sel_e slow_clk = SLOW_CLK_90K; - -#if defined(CONFIG_ESP32S2_RTC_CLK_EXT_XTAL) - slow_clk = SLOW_CLK_32K_XTAL; -#elif defined(CONFIG_ESP32S2_RTC_CLK_EXT_OSC) - slow_clk = SLOW_CLK_32K_EXT_OSC; -#elif defined(CONFIG_ESP32S2_RTC_CLK_INT_8MD256) - slow_clk = SLOW_CLK_8MD256; -#endif - - esp32s2_rtc_clk_fast_freq_set(fast_freq); - esp32s2_select_rtc_slow_clk(slow_clk); -} - -/**************************************************************************** - * Name: esp32s2_rtc_init - * - * Description: - * Initialize RTC clock and power control related functions. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void IRAM_ATTR esp32s2_rtc_init(void) -{ - struct esp32s2_rtc_priv_s cfg = RTC_CONFIG_DEFAULT(); - - modifyreg32(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PVTMON_PU, 0); - - modifyreg32(RTC_CNTL_TIMER1_REG, 0, - cfg.pll_wait ? RTC_CNTL_PLL_BUF_WAIT : 0); - - modifyreg32(RTC_CNTL_TIMER1_REG, 0, - cfg.ck8m_wait ? RTC_CNTL_CK8M_WAIT : 0); - - /* Moved from rtc sleep to rtc init to save sleep function running time */ - - /* Set shortest possible sleep time limit */ - - REG_SET_FIELD(RTC_CNTL_TIMER5_REG, RTC_CNTL_MIN_SLP_VAL, - RTC_CNTL_MIN_SLP_VAL_MIN); - - /* Set wifi timer */ - - REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_WIFI_POWERUP_TIMER, 1); - REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_WIFI_WAIT_TIMER, 1); - - if (cfg.cali_ocode) - { - /* TODO: Use calibration from efuse if configured */ - - esp32s2_rtc_calibrate_ocode(); - } - - if (cfg.clkctl_init) - { - /* Clear CMMU clock force on */ - - modifyreg32(EXTMEM_PRO_CACHE_MMU_POWER_CTRL_REG, - EXTMEM_PRO_CACHE_MMU_MEM_FORCE_ON, 0); - - /* Clear rom clock force on */ - - REG_SET_FIELD(SYSTEM_ROM_CTRL_0_REG, SYSTEM_ROM_FO, 0); - - /* Clear tag clock force on */ - - REG_SET_FIELD(SYSTEM_SRAM_CTRL_0_REG, SYSTEM_SRAM_FO, 0); - - /* Clear tag clock force on */ - - modifyreg32(EXTMEM_PRO_DCACHE_TAG_POWER_CTRL_REG, - EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_ON, 0); - modifyreg32(EXTMEM_PRO_ICACHE_TAG_POWER_CTRL_REG, - EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_ON, 0); - - /* Clear register clock force on */ - - modifyreg32(SPI_MEM_CLOCK_GATE_REG(0), SPI_MEM_CLK_EN, 0); - modifyreg32(SPI_MEM_CLOCK_GATE_REG(1), SPI_MEM_CLK_EN, 0); - } - - if (cfg.pwrctl_init) - { - modifyreg32(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU, 0); - - /* Cancel xtal force pu if no need to force power up - * Cannot cancel xtal force pu if pll is force power on - */ - - if (!(cfg.xtal_fpu || cfg.bbpll_fpu)) - { - modifyreg32(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_XTL_FORCE_PU, 0); - } - else - { - modifyreg32(RTC_CNTL_OPTIONS0_REG, 0, RTC_CNTL_XTL_FORCE_PU); - } - - /* CLEAR APLL close */ - - CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PU); - SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD); - - /* Cancel bbpll force pu if setting no force power up */ - - if (!cfg.bbpll_fpu) - { - modifyreg32(RTC_CNTL_OPTIONS0_REG, - RTC_CNTL_BBPLL_FORCE_PU | - RTC_CNTL_BBPLL_I2C_FORCE_PU | - RTC_CNTL_BB_I2C_FORCE_PU, 0); - } - else - { - modifyreg32(RTC_CNTL_OPTIONS0_REG, 0, - RTC_CNTL_BBPLL_FORCE_PU | - RTC_CNTL_BBPLL_I2C_FORCE_PU | - RTC_CNTL_BB_I2C_FORCE_PU); - } - - /* Cancel RTC REG force PU */ - - modifyreg32(RTC_CNTL_PWC_REG, RTC_CNTL_FORCE_PU, 0); - modifyreg32(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU | - RTC_CNTL_DBOOST_FORCE_PU, 0); - - modifyreg32(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_PU | - RTC_CNTL_FASTMEM_FORCE_PU | - RTC_CNTL_SLOWMEM_FORCE_NOISO | - RTC_CNTL_FASTMEM_FORCE_NOISO, 0); - - if (cfg.rtc_dboost_fpd) - { - modifyreg32(RTC_CNTL_REG, 0, RTC_CNTL_DBOOST_FORCE_PD); - } - else - { - modifyreg32(RTC_CNTL_REG, RTC_CNTL_DBOOST_FORCE_PD, 0); - } - - /* Cancel digital pu force */ - - modifyreg32(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_PU | - RTC_CNTL_FASTMEM_FORCE_PU, 0); - - /* If this mask is enabled, all soc mem cannot enter power down mode - * We should control soc memory power down mode from RTC, so we will - * not touch this register any more - */ - - modifyreg32(SYSTEM_MEM_PD_MASK_REG, SYSTEM_LSLP_MEM_PD_MASK, 0); - - /* If this pd_cfg is set to 1, all memory won't enter low power mode - * during light sleep. - * If this pd_cfg is set to 0, all memory will enter low power mode - * during light sleep. - */ - - struct esp32s2_rtc_sleep_pd_config_s - pu_cfg = RTC_SLEEP_PD_CONFIG_ALL(0); - esp32s2_rtc_sleep_pd(pu_cfg); - - modifyreg32(RTC_CNTL_PWC_REG, RTC_CNTL_DG_WRAP_FORCE_PU, 0); - modifyreg32(RTC_CNTL_PWC_REG, RTC_CNTL_WIFI_FORCE_PU, 0); - modifyreg32(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_WRAP_FORCE_NOISO | - RTC_CNTL_DG_WRAP_FORCE_ISO, 0); - - modifyreg32(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_NOISO | - RTC_CNTL_DG_WRAP_FORCE_NOISO, 0); - - modifyreg32(RTC_CNTL_PWC_REG, RTC_CNTL_FORCE_NOISO, 0); - - /* Cancel digital PADS force no iso */ - - if (cfg.cpu_waiti_clk_gate) - { - modifyreg32(SYSTEM_CPU_PER_CONF_REG, - SYSTEM_CPU_WAIT_MODE_FORCE_ON, 0); - } - else - { - modifyreg32(SYSTEM_CPU_PER_CONF_REG, 0, - SYSTEM_CPU_WAIT_MODE_FORCE_ON); - } - - /* If SYSTEM_CPU_WAIT_MODE_FORCE_ON == 0, the cpu clk will be closed - * when cpu enter WAITI mode - */ - - modifyreg32(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD | - RTC_CNTL_DG_PAD_FORCE_NOISO, 0); - } -} - -/**************************************************************************** - * Name: esp32s2_rtc_time_get - * - * Description: - * Get current value of RTC counter. - * - * Input Parameters: - * None - * - * Returned Value: - * Current value of RTC counter - * - ****************************************************************************/ - -uint64_t IRAM_ATTR esp32s2_rtc_time_get(void) -{ - uint64_t rtc_time; - - modifyreg32(RTC_CNTL_TIME_UPDATE_REG, 0, RTC_CNTL_TIME_UPDATE); - - rtc_time = getreg32(RTC_CNTL_TIME0_REG); - rtc_time |= ((uint64_t) getreg32(RTC_CNTL_TIME1_REG)) << 32; - - return rtc_time; -} - -/**************************************************************************** - * Name: esp32s2_rtc_time_us_to_slowclk - * - * Description: - * Convert time interval from microseconds to RTC_SLOW_CLK cycles. - * - * Input Parameters: - * time_in_us - Time interval in microseconds - * period - Period of slow clock in microseconds - * - * Returned Value: - * Number of slow clock cycles - * - ****************************************************************************/ - -uint64_t IRAM_ATTR esp32s2_rtc_time_us_to_slowclk(uint64_t time_in_us, - uint32_t period) -{ - uint64_t slow_clk_cycles = 0; - uint64_t max_time_in_us = (UINT64_C(1) << 45) - 1; - - /* Handle overflow that would happen if time_in_us >= 2^45 */ - - while (time_in_us > max_time_in_us) - { - time_in_us -= max_time_in_us; - slow_clk_cycles += ((max_time_in_us << RTC_CLK_CAL_FRACT) / period); - } - - slow_clk_cycles += ((time_in_us << RTC_CLK_CAL_FRACT) / period); - - return slow_clk_cycles; -} - -/**************************************************************************** - * Name: esp32s2_rtc_time_slowclk_to_us - * - * Description: - * Convert time interval from RTC_SLOW_CLK to microseconds - * - * Input Parameters: - * rtc_cycles - Time interval in RTC_SLOW_CLK cycles - * period - Period of slow clock in microseconds - * - * Returned Value: - * Time interval in microseconds - * - ****************************************************************************/ - -uint64_t IRAM_ATTR esp32s2_rtc_time_slowclk_to_us(uint64_t rtc_cycles, - uint32_t period) -{ - return (rtc_cycles * period) >> RTC_CLK_CAL_FRACT; -} - -/**************************************************************************** - * Name: esp32s2_clk_slowclk_cal_get - * - * Description: - * Get the calibration value of RTC slow clock. - * - * Input Parameters: - * None - * - * Returned Value: - * The calibration value obtained using rtc_clk_cal - * - ****************************************************************************/ - -uint32_t IRAM_ATTR esp32s2_clk_slowclk_cal_get(void) -{ - return getreg32(RTC_SLOW_CLK_CAL_REG); -} - -/**************************************************************************** - * Name: esp32s2_rtc_sleep_set_wakeup_time - * - * Description: - * Set target value of RTC counter for RTC_TIMER_TRIG_EN wakeup source. - * - * Input Parameters: - * t - value of RTC counter at which wakeup from sleep will happen. - * - * Returned Value: - * None - * - ****************************************************************************/ - -void IRAM_ATTR esp32s2_rtc_sleep_set_wakeup_time(uint64_t t) -{ - putreg32(t & UINT32_MAX, RTC_CNTL_SLP_TIMER0_REG); - putreg32((uint32_t)(t >> 32), RTC_CNTL_SLP_TIMER1_REG); -} - -/**************************************************************************** - * Name: esp32s2_rtc_wait_for_slow_cycle - * - * Description: - * Busy loop until next RTC_SLOW_CLK cycle. - * - * Input Parameters: - * None - * - * Returned Value: - * none - * - ****************************************************************************/ - -void IRAM_ATTR esp32s2_rtc_wait_for_slow_cycle(void) -{ - modifyreg32(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING | - TIMG_RTC_CALI_START, 0); - modifyreg32(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY, 0); - REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, - RTC_CAL_RTC_MUX); - - /* Request to run calibration for 0 slow clock cycles. - * RDY bit will be set on the nearest slow clock cycle. - */ - - REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, 0); - modifyreg32(TIMG_RTCCALICFG_REG(0), 0, TIMG_RTC_CALI_START); - - /* RDY needs some time to go low */ - - up_udelay(1); - - while (!(getreg32(TIMG_RTCCALICFG_REG(0)) & TIMG_RTC_CALI_RDY)) - { - up_udelay(1); - } -} - -/**************************************************************************** - * Name: esp32s2_rtc_clk_apb_freq_update - * - * Description: - * Store new APB frequency value into RTC_APB_FREQ_REG - * - * Input Parameters: - * apb_freq - New APB frequency, in Hz - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32s2_rtc_clk_apb_freq_update(uint32_t apb_freq) -{ - g_apb_freq = apb_freq; -} - -/**************************************************************************** - * Name: esp32s2_rtc_clk_apb_freq_get - * - * Description: - * Get the current stored APB frequency - * - * Input Parameters: - * None - * - * Returned Value: - * The APB frequency value, in Hz. - * - ****************************************************************************/ - -uint32_t esp32s2_rtc_clk_apb_freq_get(void) -{ - return g_apb_freq; -} - -/**************************************************************************** - * Name: esp32s2_rtc_cpu_freq_set_xtal - * - * Description: - * Switch CPU clock source to XTAL - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void IRAM_ATTR esp32s2_rtc_cpu_freq_set_xtal(void) -{ - int freq_mhz = (int) esp32s2_rtc_clk_xtal_freq_get(); - esp32s2_rtc_update_to_xtal(freq_mhz, 1); - esp32s2_rtc_wait_for_slow_cycle(); -} - -/**************************************************************************** - * Name: esp_rtc_clk_get_cpu_freq - * - * Description: - * Get the currently used CPU frequency configuration. - * - * Input Parameters: - * None - * - * Returned Value: - * CPU frequency - * - ****************************************************************************/ - -int IRAM_ATTR esp_rtc_clk_get_cpu_freq(void) -{ - uint32_t source_freq_mhz; - uint32_t div; - uint32_t soc_clk_sel; - uint32_t cpuperiod_sel; - int freq_mhz = 0; - - soc_clk_sel = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL); - switch (soc_clk_sel) - { - case DPORT_SOC_CLK_SEL_XTAL: - { - div = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, - SYSTEM_PRE_DIV_CNT) + 1; - source_freq_mhz = (uint32_t) esp32s2_rtc_clk_xtal_freq_get(); - freq_mhz = source_freq_mhz / div; - } - break; - - case DPORT_SOC_CLK_SEL_PLL: - { - cpuperiod_sel = REG_GET_FIELD(SYSTEM_CPU_PER_CONF_REG, - SYSTEM_CPUPERIOD_SEL); - uint32_t pllfreq_sel = REG_GET_FIELD(SYSTEM_CPU_PER_CONF_REG, - SYSTEM_PLL_FREQ_SEL); - source_freq_mhz = (pllfreq_sel) ? RTC_PLL_FREQ_480M : - RTC_PLL_FREQ_320M; - if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_80) - { - div = (source_freq_mhz == RTC_PLL_FREQ_480M) ? 6 : 4; - freq_mhz = 480 / div; - } - else if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_160) - { - div = 3; - freq_mhz = 480 / div; - } - else if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_240) - { - div = 2; - freq_mhz = 480 / div; - } - else - { - rtcerr("unsupported frequency configuration"); - return -ENODEV; - } - } - break; - - case DPORT_SOC_CLK_SEL_8M: - { - source_freq_mhz = 8; - div = 1; - freq_mhz = source_freq_mhz / div; - } - break; - - default: - { - rtcerr("unsupported frequency configuration"); - return -ENODEV; - } - } - - return freq_mhz; -} - -/**************************************************************************** - * Name: esp32s2_rtc_sleep_init - * - * Description: - * Prepare the chip to enter sleep mode - * - * Input Parameters: - * flags - sleep mode configuration - * - * Returned Value: - * None - * - ****************************************************************************/ - -void IRAM_ATTR esp32s2_rtc_sleep_init(uint32_t flags) -{ - struct esp32s2_rtc_sleep_config_s cfg = RTC_SLEEP_CONFIG_DEFAULT(flags); - - /* Starts here */ - - if (cfg.lslp_mem_inf_fpu) - { - struct esp32s2_rtc_sleep_pd_config_s - pu_cfg = RTC_SLEEP_PD_CONFIG_ALL(1); - esp32s2_rtc_sleep_pd(pu_cfg); - } - - if (cfg.rtc_mem_inf_follow_cpu) - { - modifyreg32(RTC_CNTL_PWC_REG, 0, RTC_CNTL_SLOWMEM_FOLW_CPU | - RTC_CNTL_FASTMEM_FOLW_CPU); - } - else - { - modifyreg32(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FOLW_CPU | - RTC_CNTL_FASTMEM_FOLW_CPU, 0); - } - - if (cfg.rtc_fastmem_pd_en) - { - modifyreg32(RTC_CNTL_PWC_REG, 0, RTC_CNTL_FASTMEM_PD_EN); - modifyreg32(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_PU, 0); - modifyreg32(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_NOISO, 0); - } - else - { - modifyreg32(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_PD_EN, 0); - modifyreg32(RTC_CNTL_PWC_REG, 0, RTC_CNTL_FASTMEM_FORCE_PU); - modifyreg32(RTC_CNTL_PWC_REG, 0, RTC_CNTL_FASTMEM_FORCE_NOISO); - } - - if (cfg.rtc_slowmem_pd_en) - { - modifyreg32(RTC_CNTL_PWC_REG, 0, RTC_CNTL_SLOWMEM_PD_EN); - modifyreg32(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_PU, 0); - modifyreg32(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_NOISO, 0); - } - else - { - modifyreg32(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_PD_EN, 0); - modifyreg32(RTC_CNTL_PWC_REG, 0, RTC_CNTL_SLOWMEM_FORCE_PU); - modifyreg32(RTC_CNTL_PWC_REG, 0, RTC_CNTL_SLOWMEM_FORCE_NOISO); - } - - if (cfg.wifi_pd_en) - { - modifyreg32(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_NOISO | - RTC_CNTL_WIFI_FORCE_ISO, 0); - modifyreg32(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PU, 0); - modifyreg32(RTC_CNTL_DIG_PWC_REG, 0, RTC_CNTL_WIFI_PD_EN); - } - else - { - modifyreg32(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN, 0); - } - - if (cfg.rtc_peri_pd_en) - { - modifyreg32(RTC_CNTL_PWC_REG, 0, RTC_CNTL_PD_EN); - } - else - { - modifyreg32(RTC_CNTL_PWC_REG, RTC_CNTL_PD_EN, 0); - } - - REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_SLP, cfg.rtc_dbias_slp); - REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_SLP, cfg.dig_dbias_slp); - - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_MONITOR, - RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT); - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_MONITOR, - RTC_CNTL_BIASSLP_MONITOR_DEFAULT); - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_DEEP_SLP, - (!cfg.deep_slp && cfg.xtal_fpu) ? RTC_CNTL_BIASSLP_SLEEP_ON : - RTC_CNTL_BIASSLP_SLEEP_DEFAULT); - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_MONITOR, - RTC_CNTL_PD_CUR_MONITOR_DEFAULT); - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_DEEP_SLP, - (!cfg.deep_slp && cfg.xtal_fpu) ? RTC_CNTL_PD_CUR_SLEEP_ON : - RTC_CNTL_PD_CUR_SLEEP_DEFAULT); - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_DEEP_SLP, - cfg.dbg_atten_slp); - - if (cfg.deep_slp) - { - modifyreg32(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_ISO | - RTC_CNTL_DG_PAD_FORCE_NOISO, 0); - - /* Shut down parts of RTC which may have been left - * enabled by the wireless drivers. - */ - - modifyreg32(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_CKGEN_I2C_PU | - RTC_CNTL_PLL_I2C_PU | RTC_CNTL_RFRX_PBUS_PU | - RTC_CNTL_TXRF_I2C_PU, 0); - } - else - { - modifyreg32(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN, 0); - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, - RTC_CNTL_DBG_ATTEN_DEEP_SLP, 0); - } - - REG_SET_FIELD(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_XTL_FORCE_PU, - cfg.xtal_fpu); - - if (REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL) == - RTC_SLOW_FREQ_8MD256) - { - modifyreg32(RTC_CNTL_CLK_CONF_REG, 0, RTC_CNTL_CK8M_FORCE_PU); - } - else - { - modifyreg32(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU, 0); - } - - /* Keep the RTC8M_CLK on in light_sleep mode if the - * ledc low-speed channel is clocked by RTC8M_CLK. - */ - - if (!cfg.deep_slp && GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, - RTC_CNTL_DIG_CLK8M_EN_M)) - { - REG_CLR_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PD); - REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU); - } - - /* Enable VDDSDIO control by state machine */ - - modifyreg32(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_FORCE, 0); - REG_SET_FIELD(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_REG_PD_EN, - cfg.vddsdio_pd_en); - - REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, - RTC_CNTL_DEEP_SLP_REJECT_EN, cfg.deep_slp_reject); - REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, - RTC_CNTL_LIGHT_SLP_REJECT_EN, cfg.light_slp_reject); - - REG_SET_FIELD(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_XTL_FORCE_PU, - cfg.xtal_fpu); -} - -/**************************************************************************** - * Name: esp32s2_rtc_sleep_start - * - * Description: - * Enter force sleep mode. - * - * Input Parameters: - * wakeup_opt - bit mask wake up reasons to enable - * reject_opt - bit mask of sleep reject reasons. - * - * Returned Value: - * Non-zero if sleep was rejected by hardware - * - ****************************************************************************/ - -int IRAM_ATTR esp32s2_rtc_sleep_start(uint32_t wakeup_opt, - uint32_t reject_opt) -{ - int reject; - REG_SET_FIELD(RTC_CNTL_WAKEUP_STATE_REG, - RTC_CNTL_WAKEUP_ENA, wakeup_opt); - putreg32((uint32_t)reject_opt, RTC_CNTL_SLP_REJECT_CONF_REG); - - /* Start entry into sleep mode */ - - modifyreg32(RTC_CNTL_STATE0_REG, 0, RTC_CNTL_SLEEP_EN); - - while ((getreg32(RTC_CNTL_INT_RAW_RTC_REG) & - (RTC_CNTL_SLP_REJECT_INT_RAW | RTC_CNTL_SLP_WAKEUP_INT_RAW)) == 0); - - /* In deep sleep mode, we never get here */ - - reject = REG_GET_FIELD(RTC_CNTL_INT_RAW_RTC_REG, - RTC_CNTL_SLP_REJECT_INT_RAW); - - modifyreg32(RTC_CNTL_INT_CLR_RTC_REG, 0, - RTC_CNTL_SLP_REJECT_INT_CLR | RTC_CNTL_SLP_WAKEUP_INT_CLR); - - /* Restore DBG_ATTEN to the default value */ - - REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_DEEP_SLP, - RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT); - return reject; -} - -/**************************************************************************** - * Name: esp32s2_rtc_clk_cpu_freq_set_config - * - * Description: - * Set CPU frequency configuration. - * - * Input Parameters: - * config - CPU frequency configuration - * - * Returned Value: - * None - * - ****************************************************************************/ - -void IRAM_ATTR esp32s2_rtc_clk_cpu_freq_set_config( - const struct esp32s2_cpu_freq_config_s *config) -{ - uint32_t soc_clk_sel = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, - SYSTEM_SOC_CLK_SEL); - if (config->source == RTC_CPU_FREQ_SRC_XTAL) - { - esp32s2_rtc_update_to_xtal(config->freq_mhz, config->div); - if (soc_clk_sel == DPORT_SOC_CLK_SEL_PLL) - { - esp32s2_rtc_clk_bbpll_disable(); - } - } - else if (config->source == RTC_CPU_FREQ_SRC_PLL) - { - if (soc_clk_sel != DPORT_SOC_CLK_SEL_PLL) - { - modifyreg32(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PD | - RTC_CNTL_BBPLL_FORCE_PD | RTC_CNTL_BBPLL_I2C_FORCE_PD, - 0); - esp32s2_rtc_bbpll_configure(esp32s2_rtc_clk_xtal_freq_get(), - config->source_freq_mhz); - } - - esp32s2_rtc_clk_cpu_freq_to_pll_mhz(config->freq_mhz); - } - else if (config->source == RTC_CPU_FREQ_SRC_8M) - { - esp32s2_rtc_clk_cpu_freq_to_8m(); - if (soc_clk_sel == DPORT_SOC_CLK_SEL_PLL) - { - esp32s2_rtc_clk_bbpll_disable(); - } - } -} - -/**************************************************************************** - * Name: esp32s2_rtc_clk_cpu_freq_get_config - * - * Description: - * Get the currently used CPU frequency configuration. - * - * Input Parameters: - * out_config - CPU frequency configuration - * - * Returned Value: - * None - * - ****************************************************************************/ - -void IRAM_ATTR esp32s2_rtc_clk_cpu_freq_get_config( - struct esp32s2_cpu_freq_config_s *out_config) -{ - uint32_t div = 3; - uint32_t freq_mhz = 160; - uint32_t source_freq_mhz = RTC_PLL_FREQ_480M; - enum esp32s2_rtc_cpu_freq_src_e source = RTC_CPU_FREQ_SRC_PLL; - uint32_t soc_clk_sel = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, - SYSTEM_SOC_CLK_SEL); - switch (soc_clk_sel) - { - case DPORT_SOC_CLK_SEL_XTAL: - { - source = RTC_CPU_FREQ_SRC_XTAL; - div = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, - SYSTEM_PRE_DIV_CNT) + 1; - source_freq_mhz = (uint32_t) esp32s2_rtc_clk_xtal_freq_get(); - freq_mhz = source_freq_mhz / div; - } - break; - - case DPORT_SOC_CLK_SEL_PLL: - { - uint32_t cpuperiod_sel = REG_GET_FIELD(SYSTEM_CPU_PER_CONF_REG, - SYSTEM_CPUPERIOD_SEL); - uint32_t pllfreq_sel = REG_GET_FIELD(SYSTEM_CPU_PER_CONF_REG, - SYSTEM_PLL_FREQ_SEL); - source = RTC_CPU_FREQ_SRC_PLL; - source_freq_mhz = (pllfreq_sel) ? - RTC_PLL_FREQ_480M : RTC_PLL_FREQ_320M; - if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_80) - { - div = (source_freq_mhz == RTC_PLL_FREQ_480M) ? 6 : 4; - freq_mhz = 80; - } - else if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_160) - { - div = (source_freq_mhz == RTC_PLL_FREQ_480M) ? 3 : 2; - div = 3; - freq_mhz = 160; - } - else if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_240) - { - div = 2; - freq_mhz = 240; - } - else - { - return; - } - } - break; - - case DPORT_SOC_CLK_SEL_8M: - { - source = RTC_CPU_FREQ_SRC_8M; - source_freq_mhz = 8; - div = 1; - freq_mhz = source_freq_mhz; - } - break; - - default: - PANIC(); - break; - } - - *out_config = (struct esp32s2_cpu_freq_config_s) - { - .source = source, - .source_freq_mhz = source_freq_mhz, - .div = div, - .freq_mhz = freq_mhz - }; -} - -/**************************************************************************** - * Name: esp32s2_rtc_get_time_us - * - * Description: - * Get current value of RTC counter in microseconds - * - * Input Parameters: - * None - * - * Returned Value: - * Current value of RTC counter in microseconds - * - ****************************************************************************/ - -uint64_t esp32s2_rtc_get_time_us(void) -{ - const uint32_t cal = getreg32(RTC_SLOW_CLK_CAL_REG); - const uint64_t rtc_this_ticks = esp32s2_rtc_time_get(); - - /* RTC counter result is up to 2^48, calibration factor is up to 2^24, - * for a 32KHz clock. We need to calculate (assuming no overflow): - * (ticks * cal) >> RTC_CLK_CAL_FRACT. An overflow in the (ticks * cal) - * multiplication would cause time to wrap around after approximately - * 13 days, which is probably not enough for some applications. - * Therefore multiplication is split into two terms, for the lower 32-bit - * and the upper 16-bit parts of "ticks", i.e.: - * ((ticks_low + 2^32 * ticks_high) * cal) >> RTC_CLK_CAL_FRACT - */ - - const uint64_t ticks_low = rtc_this_ticks & UINT32_MAX; - const uint64_t ticks_high = rtc_this_ticks >> 32; - const uint64_t delta_time_us = ((ticks_low * cal) >> RTC_CLK_CAL_FRACT) + - ((ticks_high * cal) << (32 - RTC_CLK_CAL_FRACT)); - - return delta_time_us; -} - -/**************************************************************************** - * Name: esp32_rtc_bbpll_disable - * - * Description: - * Disable BBPLL. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void IRAM_ATTR esp32s2_rtc_bbpll_disable(void) -{ - modifyreg32(RTC_CNTL_OPTIONS0_REG, 0, RTC_CNTL_BB_I2C_FORCE_PD | - RTC_CNTL_BBPLL_FORCE_PD | RTC_CNTL_BBPLL_I2C_FORCE_PD); -} - -/**************************************************************************** - * Name: esp32s2_rtc_set_boot_time - * - * Description: - * Set time to RTC register to replace the original boot time. - * - * Input Parameters: - * time_us - set time in microseconds. - * - * Returned Value: - * None - * - ****************************************************************************/ - -void IRAM_ATTR esp32s2_rtc_set_boot_time(uint64_t time_us) -{ - putreg32((uint32_t)(time_us & UINT32_MAX), RTC_BOOT_TIME_LOW_REG); - putreg32((uint32_t)(time_us >> 32), RTC_BOOT_TIME_HIGH_REG); -} - -/**************************************************************************** - * Name: esp32s2_rtc_get_boot_time - * - * Description: - * Get time of RTC register to indicate the original boot time. - * - * Input Parameters: - * None - * - * Returned Value: - * Get time in microseconds. - * - ****************************************************************************/ - -uint64_t IRAM_ATTR esp32s2_rtc_get_boot_time(void) -{ - return ((uint64_t)getreg32(RTC_BOOT_TIME_LOW_REG)) - + (((uint64_t)getreg32(RTC_BOOT_TIME_HIGH_REG)) << 32); -} - -/**************************************************************************** - * Name: up_rtc_time - * - * Description: - * Get the current time in seconds. This is similar to the standard time() - * function. This interface is only required if the low-resolution - * RTC/counter hardware implementation is selected. It is only used by the - * RTOS during initialization to set up the system time when CONFIG_RTC is - * set but CONFIG_RTC_HIRES is not set. - * - * Input Parameters: - * None - * - * Returned Value: - * The current time in seconds - * - ****************************************************************************/ - -#ifndef CONFIG_RTC_HIRES -time_t up_rtc_time(void) -{ - uint64_t time_us; - irqstate_t flags; - - flags = spin_lock_irqsave(&g_rtc_lock); - - /* NOTE: RT-Timer starts to work after the board is initialized, and the - * RTC controller starts works after up_rtc_initialize is initialized. - * Since the system clock starts to work before the board is initialized, - * if CONFIG_RTC is enabled, the system time must be matched by the time - * of the RTC controller (up_rtc_initialize has already been initialized, - * and RT-Timer cannot work). - */ - - /* Determine if RT-Timer is started */ - - if (g_rt_timer_enabled == true) - { - /* Get the time from RT-Timer, the time interval between RTC - * controller and RT-Timer is stored in g_rtc_save->offset. - */ - - time_us = rt_timer_time_us() + g_rtc_save->offset + - esp32s2_rtc_get_boot_time(); - } - else - { - /* Get the time from RTC controller. */ - - time_us = esp32s2_rtc_get_time_us() + esp32s2_rtc_get_boot_time(); - } - - spin_unlock_irqrestore(&g_rtc_lock, flags); - - return (time_t)(time_us / USEC_PER_SEC); -} -#endif /* !CONFIG_RTC_HIRES */ - -/**************************************************************************** - * Name: up_rtc_settime - * - * Description: - * Set the RTC to the provided time. All RTC implementations must be - * able to set their time based on a standard timespec. - * - * Input Parameters: - * ts - the time to use - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -int up_rtc_settime(const struct timespec *ts) -{ - irqstate_t flags; - uint64_t now_us; - uint64_t rtc_offset_us; - - DEBUGASSERT(ts != NULL && ts->tv_nsec < NSEC_PER_SEC); - flags = spin_lock_irqsave(&g_rtc_lock); - - now_us = ((uint64_t) ts->tv_sec) * USEC_PER_SEC + - ts->tv_nsec / NSEC_PER_USEC; - if (g_rt_timer_enabled == true) - { - /* Set based on RT-Timer offset value. */ - - rtc_offset_us = now_us - rt_timer_time_us(); - } - else - { - /* Set based on the offset value of the RT controller. */ - - rtc_offset_us = now_us - esp32s2_rtc_get_time_us(); - } - - g_rtc_save->offset = 0; - esp32s2_rtc_set_boot_time(rtc_offset_us); - - spin_unlock_irqrestore(&g_rtc_lock, flags); - - return OK; -} - -/**************************************************************************** - * Name: up_rtc_initialize - * - * Description: - * Initialize the hardware RTC per the selected configuration. - * This function is called once during the OS initialization sequence - * - * Input Parameters: - * None - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -int up_rtc_initialize(void) -{ - g_rtc_save = &rtc_saved_data; - - /* If saved data is invalid, clear offset information */ - - if (g_rtc_save->magic != MAGIC_RTC_SAVE) - { - g_rtc_save->magic = MAGIC_RTC_SAVE; - g_rtc_save->offset = 0; - esp32s2_rtc_set_boot_time(0); - } - -#ifdef CONFIG_RTC_HIRES - /* Synchronize the base time to the RTC time */ - - up_rtc_gettime(&g_basetime); -#endif - - g_rtc_enabled = true; - - return OK; -} - -/**************************************************************************** - * Name: up_rtc_gettime - * - * Description: - * Get the current time from the high resolution RTC time or RT-Timer. This - * interface is only supported by the high-resolution RTC/counter hardware - * implementation. It is used to replace the system timer. - * - * Input Parameters: - * tp - The location to return the RTC time or RT-Timer value. - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_HIRES -int up_rtc_gettime(struct timespec *tp) -{ - irqstate_t flags; - uint64_t time_us; - - flags = spin_lock_irqsave(&g_rtc_lock); - - if (g_rt_timer_enabled == true) - { - time_us = rt_timer_time_us() + g_rtc_save->offset + - esp32s2_rtc_get_boot_time(); - } - else - { - time_us = esp32s2_rtc_get_time_us() + esp32s2_rtc_get_boot_time(); - } - - tp->tv_sec = time_us / USEC_PER_SEC; - tp->tv_nsec = (time_us % USEC_PER_SEC) * NSEC_PER_USEC; - - spin_unlock_irqrestore(&g_rtc_lock, flags); - - return OK; -} -#endif /* CONFIG_RTC_HIRES */ - -#ifdef CONFIG_RTC_ALARM - -/**************************************************************************** - * Name: up_rtc_setalarm - * - * Description: - * Set up an alarm. - * - * Input Parameters: - * alminfo - Information about the alarm configuration. - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -int up_rtc_setalarm(struct alm_setalarm_s *alminfo) -{ - struct rt_timer_args_s rt_timer_args; - struct alm_cbinfo_s *cbinfo; - irqstate_t flags; - int ret = -EBUSY; - int id; - - DEBUGASSERT(alminfo != NULL); - DEBUGASSERT((RTC_ALARM0 <= alminfo->as_id) && - (alminfo->as_id < RTC_ALARM_LAST)); - - /* Set the alarm in RT-Timer */ - - id = alminfo->as_id; - cbinfo = &g_alarmcb[id]; - - if (cbinfo->ac_cb == NULL) - { - /* Create the RT-Timer alarm */ - - flags = spin_lock_irqsave(&g_rtc_lock); - - if (cbinfo->alarm_hdl == NULL) - { - cbinfo->index = id; - rt_timer_args.arg = cbinfo; - rt_timer_args.callback = esp32s2_rt_cb_handler; - ret = rt_timer_create(&rt_timer_args, &cbinfo->alarm_hdl); - if (ret < 0) - { - rtcerr("ERROR: Failed to create rt_timer error=%d\n", ret); - spin_unlock_irqrestore(&g_rtc_lock, flags); - return ret; - } - } - - cbinfo->ac_cb = alminfo->as_cb; - cbinfo->ac_arg = alminfo->as_arg; - cbinfo->deadline_us = alminfo->as_time.tv_sec * USEC_PER_SEC + - alminfo->as_time.tv_nsec / NSEC_PER_USEC; - - if (cbinfo->alarm_hdl == NULL) - { - rtcerr("ERROR: failed to create alarm timer\n"); - } - else - { - rtcinfo("Start RTC alarm.\n"); - rt_timer_start(cbinfo->alarm_hdl, cbinfo->deadline_us, false); - ret = OK; - } - - spin_unlock_irqrestore(&g_rtc_lock, flags); - } - - return ret; -} - -/**************************************************************************** - * Name: up_rtc_cancelalarm - * - * Description: - * Cancel an alarm. - * - * Input Parameters: - * alarmid - Identifies the alarm to be cancelled - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -int up_rtc_cancelalarm(enum alm_id_e alarmid) -{ - struct alm_cbinfo_s *cbinfo; - irqstate_t flags; - int ret = -ENODATA; - - DEBUGASSERT((RTC_ALARM0 <= alarmid) && - (alarmid < RTC_ALARM_LAST)); - - /* Set the alarm in hardware and enable interrupts */ - - cbinfo = &g_alarmcb[alarmid]; - - if (cbinfo->ac_cb != NULL) - { - flags = spin_lock_irqsave_nopreempt(&g_rtc_lock); - - /* Stop and delete the alarm */ - - rtcinfo("Cancel RTC alarm.\n"); - rt_timer_stop(cbinfo->alarm_hdl); - rt_timer_delete(cbinfo->alarm_hdl); - cbinfo->ac_cb = NULL; - cbinfo->deadline_us = 0; - cbinfo->alarm_hdl = NULL; - - spin_unlock_irqrestore_nopreempt(&g_rtc_lock, flags); - - ret = OK; - } - - return ret; -} - -/**************************************************************************** - * Name: up_rtc_rdalarm - * - * Description: - * Query an alarm configured in hardware. - * - * Input Parameters: - * tp - Location to return the timer match register. - * alarmid - Identifies the alarm to get. - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -int up_rtc_rdalarm(struct timespec *tp, uint32_t alarmid) -{ - irqstate_t flags; - struct alm_cbinfo_s *cbinfo; - DEBUGASSERT(tp != NULL); - DEBUGASSERT((RTC_ALARM0 <= alarmid) && - (alarmid < RTC_ALARM_LAST)); - - flags = spin_lock_irqsave(&g_rtc_lock); - - /* Get the alarm according to the alarmid */ - - cbinfo = &g_alarmcb[alarmid]; - - tp->tv_sec = (rt_timer_time_us() + g_rtc_save->offset + - cbinfo->deadline_us) / USEC_PER_SEC; - tp->tv_nsec = ((rt_timer_time_us() + g_rtc_save->offset + - cbinfo->deadline_us) % USEC_PER_SEC) * NSEC_PER_USEC; - - spin_unlock_irqrestore(&g_rtc_lock, flags); - - return OK; -} - -#endif /* CONFIG_RTC_ALARM */ - -/**************************************************************************** - * Name: up_rtc_timer_init - * - * Description: - * Init RTC timer. - * - * Input Parameters: - * None - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -int up_rtc_timer_init(void) -{ - /* RT-Timer enabled */ - - g_rt_timer_enabled = true; - - /* Get the time difference between rt_timer and RTC timer */ - - g_rtc_save->offset = esp32s2_rtc_get_time_us() - - rt_timer_time_us(); - - return OK; -} diff --git a/arch/xtensa/src/esp32s2/esp32s2_rtc.h b/arch/xtensa/src/esp32s2/esp32s2_rtc.h deleted file mode 100644 index 74b64fc05fdc6..0000000000000 --- a/arch/xtensa/src/esp32s2/esp32s2_rtc.h +++ /dev/null @@ -1,755 +0,0 @@ -/**************************************************************************** - * arch/xtensa/src/esp32s2/esp32s2_rtc.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#ifndef __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_RTC_H -#define __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_RTC_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include -#include -#include "hardware/esp32s2_soc.h" - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Number of cycles to wait from the 32KHz XTAL oscillator to - * consider it running. Larger values increase startup delay. - * Smaller values may cause false positive detection - * (i.e. oscillator runs for a few cycles and then stops). - */ - -#define SLOW_CLK_CAL_CYCLES 1024 - -/* Indicates that 32KHz oscillator gets input from external oscillator - * instead of a crystal. - */ - -#define EXT_OSC_FLAG BIT(3) - -/* Number of fractional bits in values returned by rtc_clk_cal */ - -#define RTC_CLK_CAL_FRACT 19 - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/* CPU clock source */ - -enum esp32s2_rtc_cpu_freq_src_e -{ - RTC_CPU_FREQ_SRC_XTAL, /* XTAL */ - RTC_CPU_FREQ_SRC_PLL, /* PLL (480M or 320M) */ - RTC_CPU_FREQ_SRC_8M, /* Internal 8M RTC oscillator */ -}; - -/* Possible main XTAL frequency values. - * Enum values should be equal to frequency in MHz. - */ - -enum esp32s2_rtc_xtal_freq_e -{ - RTC_XTAL_FREQ_40M = 40, /* 40 MHz XTAL */ -}; - -/* RTC SLOW_CLK frequency values */ - -enum esp32s2_rtc_slow_freq_e -{ - RTC_SLOW_FREQ_RTC = 0, /* Internal 150 kHz RC oscillator */ - RTC_SLOW_FREQ_32K_XTAL = 1, /* External 32 kHz XTAL */ - RTC_SLOW_FREQ_8MD256 = 2, /* Internal 8 MHz RC oscillator, divided - * by 256 */ -}; - -/* RTC FAST_CLK frequency values */ - -enum esp32s2_rtc_fast_freq_e -{ - RTC_FAST_FREQ_XTALD4 = 0, /* Main XTAL, divided by 4 */ - RTC_FAST_FREQ_8M = 1, /* Internal 8 MHz RC oscillator */ -}; - -/* This is almost the same as esp32s2_rtc_slow_freq_e, except that we define - * an extra enum member for the external 32KHz oscillator. For convenience, - * lower 2 bits should correspond to esp32s2_rtc_slow_freq_e values. - */ - -enum esp32s2_slow_clk_sel_e -{ - /* Internal 90 kHz RC oscillator */ - - SLOW_CLK_90K = RTC_SLOW_FREQ_RTC, - - /* External 32 kHz XTAL */ - - SLOW_CLK_32K_XTAL = RTC_SLOW_FREQ_32K_XTAL, - - /* Internal 8 MHz RC oscillator, divided by 256 */ - - SLOW_CLK_8MD256 = RTC_SLOW_FREQ_8MD256, - - /* External 32KHz oscillator connected to 32K_XP pin */ - - SLOW_CLK_32K_EXT_OSC = RTC_SLOW_FREQ_32K_XTAL | EXT_OSC_FLAG -}; - -/* Clock source to be calibrated using rtc_clk_cal function */ - -enum esp32s2_rtc_cal_sel_e -{ - RTC_CAL_RTC_MUX = 0, /* Currently selected RTC SLOW_CLK */ - RTC_CAL_8MD256 = 1, /* Internal 8 MHz RC oscillator, divided by 256 */ - RTC_CAL_32K_XTAL = 2, /* External 32 kHz XTAL */ - RTC_CAL_INTERNAL_OSC = 3 /* Internal 150 kHz oscillator */ -}; - -/* CPU clock configuration structure */ - -struct esp32s2_cpu_freq_config_s -{ - /* The clock from which CPU clock is derived */ - - enum esp32s2_rtc_cpu_freq_src_e source; - uint32_t source_freq_mhz; /* Source clock frequency */ - uint32_t div; /* Divider, freq_mhz = source_freq_mhz / div */ - uint32_t freq_mhz; /* CPU clock frequency */ -}; - -#ifdef CONFIG_RTC_ALARM - -/* The form of an alarm callback */ - -typedef void (*alm_callback_t)(void *arg, unsigned int alarmid); - -enum alm_id_e -{ - RTC_ALARM0 = 0, /* RTC ALARM 0 */ - RTC_ALARM1 = 1, /* RTC ALARM 1 */ - RTC_ALARM_LAST, -}; - -/* Structure used to pass parameters to set an alarm */ - -struct alm_setalarm_s -{ - int as_id; /* enum alm_id_e */ - struct timespec as_time; /* Alarm expiration time */ - alm_callback_t as_cb; /* Callback (if non-NULL) */ - void *as_arg; /* Argument for callback */ -}; - -#endif /* CONFIG_RTC_ALARM */ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32s2_rtc_clk_slow_freq_get_hz - * - * Description: - * Get the approximate frequency of RTC_SLOW_CLK, in Hz - * - * Input Parameters: - * None - * - * Returned Value: - * RTC_SLOW_CLK frequency, in Hz - * - ****************************************************************************/ - -uint32_t esp32s2_rtc_clk_slow_freq_get_hz(void); - -/**************************************************************************** - * Name: esp32s2_rtc_clk_fast_freq_get_hz - * - * Description: - * Get fast_clk_rtc source in Hz. - * - * Input Parameters: - * None - * - * Returned Value: - * The clock source in Hz. - * - ****************************************************************************/ - -uint32_t esp32s2_rtc_clk_fast_freq_get_hz(void); - -/**************************************************************************** - * Name: esp32s2_rtc_get_slow_clk_rtc - * - * Description: - * Get slow_clk_rtc source. - * - * Input Parameters: - * None - * - * Returned Value: - * The clock source: - * - SLOW_CK - * - CK_XTAL_32K - * - CK8M_D256_OUT - * - ****************************************************************************/ - -enum esp32s2_rtc_slow_freq_e esp32s2_rtc_get_slow_clk(void); - -/**************************************************************************** - * Name: esp32s2_rtc_clk_cal - * - * Description: - * Measure RTC slow clock's period, based on main XTAL frequency - * - * Input Parameters: - * cal_clk - clock to be measured - * slowclk_cycles - number of slow clock cycles what is to be averaged - * - * Returned Value: - * Average slow clock period in microseconds, Q13.19 fixed point format - * or 0 if calibration has timed out - * - ****************************************************************************/ - -uint32_t esp32s2_rtc_clk_cal(enum esp32s2_rtc_cal_sel_e cal_clk, - uint32_t slowclk_cycles); - -/**************************************************************************** - * Name: esp32s2_rtc_clk_xtal_freq_get - * - * Description: - * Get main XTAL frequency - * - * Input Parameters: - * None - * - * Returned Value: - * XTAL frequency (one of enum esp32s2_rtc_xtal_freq_e values) - * - ****************************************************************************/ - -enum esp32s2_rtc_xtal_freq_e esp32s2_rtc_clk_xtal_freq_get(void); - -/**************************************************************************** - * Name: esp32s2_rtc_update_to_xtal - * - * Description: - * Switch to XTAL frequency, does not disable the PLL - * - * Input Parameters: - * freq - XTAL frequency - * div - REF_TICK divider - * - * Returned Value: - * none - * - ****************************************************************************/ - -void esp32s2_rtc_update_to_xtal(int freq, int div); - -/**************************************************************************** - * Name: esp32s2_rtc_bbpll_enable - * - * Description: - * Reset BBPLL configuration. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32s2_rtc_bbpll_enable(void); - -/**************************************************************************** - * Name: esp32s2_rtc_clk_set - * - * Description: - * Set RTC CLK frequency. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32s2_rtc_clk_set(void); - -/**************************************************************************** - * Name: esp32s2_rtc_init - * - * Description: - * Initialize RTC clock and power control related functions. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32s2_rtc_init(void); - -/**************************************************************************** - * Name: esp32s2_rtc_time_get - * - * Description: - * Get current value of RTC counter. - * - * Input Parameters: - * None - * - * Returned Value: - * Current value of RTC counter - * - ****************************************************************************/ - -uint64_t esp32s2_rtc_time_get(void); - -/**************************************************************************** - * Name: esp32s2_rtc_time_us_to_slowclk - * - * Description: - * Convert time interval from microseconds to RTC_SLOW_CLK cycles. - * - * Input Parameters: - * time_in_us - Time interval in microseconds - * period - Period of slow clock in microseconds - * - * Returned Value: - * number of slow clock cycles - * - ****************************************************************************/ - -uint64_t esp32s2_rtc_time_us_to_slowclk(uint64_t time_in_us, - uint32_t period); - -/**************************************************************************** - * Name: esp32s2_rtc_time_slowclk_to_us - * - * Description: - * Convert time interval from RTC_SLOW_CLK to microseconds - * - * Input Parameters: - * rtc_cycles - Time interval in RTC_SLOW_CLK cycles - * period - Period of slow clock in microseconds - * - * Returned Value: - * Time interval in microseconds - * - ****************************************************************************/ - -uint64_t esp32s2_rtc_time_slowclk_to_us(uint64_t rtc_cycles, - uint32_t period); - -/**************************************************************************** - * Name: esp32s2_clk_slowclk_cal_get - * - * Description: - * Get the calibration value of RTC slow clock. - * - * Input Parameters: - * None - * - * Returned Value: - * The calibration value obtained using rtc_clk_cal - * - ****************************************************************************/ - -uint32_t esp32s2_clk_slowclk_cal_get(void); - -/**************************************************************************** - * Name: esp32s2_rtc_bbpll_disable - * - * Description: - * Disable BBPLL. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32s2_rtc_bbpll_disable(void); - -/**************************************************************************** - * Name: esp32s2_rtc_sleep_set_wakeup_time - * - * Description: - * Set target value of RTC counter for RTC_TIMER_TRIG_EN wakeup source. - * - * Input Parameters: - * t - value of RTC counter at which wakeup from sleep will happen. - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32s2_rtc_sleep_set_wakeup_time(uint64_t t); - -/**************************************************************************** - * Name: esp32s2_rtc_wait_for_slow_cycle - * - * Description: - * Busy loop until next RTC_SLOW_CLK cycle. - * - * Input Parameters: - * None - * - * Returned Value: - * none - * - ****************************************************************************/ - -void esp32s2_rtc_wait_for_slow_cycle(void); - -/**************************************************************************** - * Name: esp32s2_rtc_cpu_freq_set_xtal - * - * Description: - * Switch CPU clock source to XTAL - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32s2_rtc_cpu_freq_set_xtal(void); - -/**************************************************************************** - * Name: esp_rtc_clk_get_cpu_freq - * - * Description: - * Get the currently used CPU frequency configuration. - * - * Input Parameters: - * None - * - * Returned Value: - * CPU frequency - * - ****************************************************************************/ - -int esp_rtc_clk_get_cpu_freq(void); - -/**************************************************************************** - * Name: esp32s2_rtc_sleep_init - * - * Description: - * Prepare the chip to enter sleep mode - * - * Input Parameters: - * flags - sleep mode configuration - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32s2_rtc_sleep_init(uint32_t flags); - -/**************************************************************************** - * Name: esp32s2_rtc_sleep_start - * - * Description: - * Enter force sleep mode. - * - * Input Parameters: - * wakeup_opt - bit mask wake up reasons to enable - * reject_opt - bit mask of sleep reject reasons. - * - * Returned Value: - * Non-zero if sleep was rejected by hardware - * - ****************************************************************************/ - -int esp32s2_rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt); - -/**************************************************************************** - * Name: esp32s2_rtc_get_time_us - * - * Description: - * Get current value of RTC counter in microseconds - * - * Input Parameters: - * None - * - * Returned Value: - * Current value of RTC counter in microseconds - * - ****************************************************************************/ - -uint64_t esp32s2_rtc_get_time_us(void); - -/**************************************************************************** - * Name: esp32s2_rtc_set_boot_time - * - * Description: - * Set time to RTC register to replace the original boot time. - * - * Input Parameters: - * time_us - set time in microseconds. - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32s2_rtc_set_boot_time(uint64_t time_us); - -/**************************************************************************** - * Name: esp32s2_rtc_get_boot_time - * - * Description: - * Get time of RTC register to indicate the original boot time. - * - * Input Parameters: - * None - * - * Returned Value: - * Get time in microseconds. - * - ****************************************************************************/ - -uint64_t esp32s2_rtc_get_boot_time(void); - -/**************************************************************************** - * Name: esp32s2_rtc_clk_cpu_freq_set_config - * - * Description: - * Set CPU frequency configuration. - * - * Input Parameters: - * config - CPU frequency configuration - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32s2_rtc_clk_cpu_freq_set_config( - const struct esp32s2_cpu_freq_config_s *config); - -/**************************************************************************** - * Name: esp32s2_rtc_clk_cpu_freq_get_config - * - * Description: - * Get the currently used CPU frequency configuration. - * - * Input Parameters: - * out_config - CPU frequency configuration - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32s2_rtc_clk_cpu_freq_get_config( - struct esp32s2_cpu_freq_config_s *out_config); - -#ifdef CONFIG_RTC_DRIVER - -/**************************************************************************** - * Name: up_rtc_time - * - * Description: - * Get the current time in seconds. This is similar to the standard time() - * function. This interface is only required if the low-resolution - * RTC/counter hardware implementation selected. It is only used by the - * RTOS during initialization to set up the system time when CONFIG_RTC is - * set but neither CONFIG_RTC_HIRES nor CONFIG_RTC_DATETIME are set. - * - * Input Parameters: - * None - * - * Returned Value: - * The current time in seconds - * - ****************************************************************************/ - -#ifndef CONFIG_RTC_HIRES -time_t up_rtc_time(void); -#endif - -/**************************************************************************** - * Name: up_rtc_settime - * - * Description: - * Set the RTC to the provided time. All RTC implementations must be - * able to set their time based on a standard timespec. - * - * Input Parameters: - * tp - the time to use - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -int up_rtc_settime(const struct timespec *ts); - -/**************************************************************************** - * Name: up_rtc_initialize - * - * Description: - * Initialize the hardware RTC per the selected configuration. - * This function is called once during the OS initialization sequence - * - * Input Parameters: - * None - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -int up_rtc_initialize(void); - -/**************************************************************************** - * Name: up_rtc_gettime - * - * Description: - * Get the current time from the high resolution RTC clock/counter. This - * interface is only supported by the high-resolution RTC/counter hardware - * implementation. It is used to replace the system timer. - * - * Input Parameters: - * tp - The location to return the high resolution time value. - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_HIRES -int up_rtc_gettime(struct timespec *tp); -#endif - -#ifdef CONFIG_RTC_ALARM - -/**************************************************************************** - * Name: up_rtc_setalarm - * - * Description: - * Set up an alarm. - * - * Input Parameters: - * alminfo - Information about the alarm configuration. - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -int up_rtc_setalarm(struct alm_setalarm_s *alminfo); - -/**************************************************************************** - * Name: up_rtc_cancelalarm - * - * Description: - * Cancel an alaram. - * - * Input Parameters: - * alarmid - Identifies the alarm to be cancelled - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -int up_rtc_cancelalarm(enum alm_id_e alarmid); - -/**************************************************************************** - * Name: up_rtc_rdalarm - * - * Description: - * Query an alarm configured in hardware. - * - * Input Parameters: - * tp - Location to return the timer match register. - * alarmid - Identifies the alarm to be cancelled - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -int up_rtc_rdalarm(struct timespec *tp, uint32_t alarmid); - -#endif /* CONFIG_RTC_ALARM */ - -/**************************************************************************** - * Name: up_rtc_timer_init - * - * Description: - * Init RTC timer. - * - * Input Parameters: - * None - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -int up_rtc_timer_init(void); - -#endif /* CONFIG_RTC_DRIVER */ - -#ifdef __cplusplus -} -#endif -#undef EXTERN - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_RTC_H */ diff --git a/arch/xtensa/src/esp32s2/esp32s2_rtc_gpio.c b/arch/xtensa/src/esp32s2/esp32s2_rtc_gpio.c index 312159f71984c..65dbfea485b7d 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_rtc_gpio.c +++ b/arch/xtensa/src/esp32s2/esp32s2_rtc_gpio.c @@ -34,7 +34,7 @@ #include #include "xtensa.h" -#include "esp32s2_irq.h" +#include "espressif/esp_irq.h" #include "esp32s2_rtc_gpio.h" #include "hardware/esp32s2_rtc_io.h" #include "hardware/esp32s2_sens.h" @@ -57,6 +57,14 @@ enum rtcio_lh_out_mode_e RTCIO_OUTPUT_OD = 0x1, /* RTCIO output mode is open-drain. */ }; +/* Structure to store RTC GPIO interrupt handlers */ + +struct rtcio_handler_s +{ + xcpt_t handler; /* User interrupt handler */ + void *arg; /* Argument for handler */ +}; + /**************************************************************************** * Private Data ****************************************************************************/ @@ -64,6 +72,7 @@ enum rtcio_lh_out_mode_e #ifdef CONFIG_ESP32S2_RTCIO_IRQ static int g_rtcio_cpuint; static uint32_t last_status; +static struct rtcio_handler_s g_rtcio_handlers[ESP32S2_NIRQ_RTCIO_PERIPH]; #endif static const uint32_t rtc_gpio_to_addr[] = @@ -123,6 +132,7 @@ static inline bool is_valid_rtc_gpio(uint32_t rtcio_num) * * Input Parameters: * irq - The IRQ number; + * context - The interrupt context; * reg_status - Pointer to a copy of the interrupt status register. * * Returned Value: @@ -131,7 +141,7 @@ static inline bool is_valid_rtc_gpio(uint32_t rtcio_num) ****************************************************************************/ #ifdef CONFIG_ESP32S2_RTCIO_IRQ -static void rtcio_dispatch(int irq, uint32_t *reg_status) +static void rtcio_dispatch(int irq, void *context, uint32_t *reg_status) { uint32_t status = *reg_status; uint32_t mask; @@ -146,11 +156,14 @@ static void rtcio_dispatch(int irq, uint32_t *reg_status) mask = (UINT32_C(1) << i); if ((status & mask) != 0) { - /* Yes... perform the second level dispatch. The IRQ context will - * contain the contents of the status register. - */ + /* Call the registered handler if one exists */ - irq_dispatch(irq + i, (void *)reg_status); + if (g_rtcio_handlers[i].handler != NULL) + { + g_rtcio_handlers[i].handler(irq, + (void *)reg_status, + g_rtcio_handlers[i].arg); + } /* Clear the bit in the status so that we might execute this loop * sooner. @@ -183,12 +196,12 @@ static int rtcio_interrupt(int irq, void *context, void *arg) { /* Read and clear the lower RTC interrupt status */ - last_status = getreg32(RTC_CNTL_INT_ST_RTC_REG); - putreg32(last_status, RTC_CNTL_INT_CLR_RTC_REG); + last_status = getreg32(RTC_CNTL_INT_ST_REG); + putreg32(last_status, RTC_CNTL_INT_CLR_REG); /* Dispatch pending interrupts in the RTC status register */ - rtcio_dispatch(ESP32S2_FIRST_RTCIOIRQ_PERIPH, &last_status); + rtcio_dispatch(irq, context, &last_status); return OK; } @@ -383,7 +396,7 @@ void esp32s2_rtciowrite(int rtcio_num, bool value) } /**************************************************************************** - * Name: esp32s2_rtcioirqinitialize + * Name: esp_rtcioirqinitialize * * Description: * Initialize logic to support a second level of interrupt decoding for @@ -392,17 +405,27 @@ void esp32s2_rtciowrite(int rtcio_num, bool value) ****************************************************************************/ #ifdef CONFIG_ESP32S2_RTCIO_IRQ -void esp32s2_rtcioirqinitialize(void) +void esp_rtcioirqinitialize(void) { - /* Setup the RTCIO interrupt. */ + int i; - g_rtcio_cpuint = esp32s2_setup_irq(ESP32S2_PERIPH_RTC_CORE, - 1, ESP32S2_CPUINT_LEVEL); + /* Initialize handler array */ + + for (i = 0; i < ESP32S2_NIRQ_RTCIO_PERIPH; i++) + { + g_rtcio_handlers[i].handler = NULL; + g_rtcio_handlers[i].arg = NULL; + } + + /* Setup the RTCIO interrupt with handler. */ + + g_rtcio_cpuint = esp_setup_irq(ESP32S2_PERIPH_RTC_CORE, + 1, ESP_IRQ_TRIGGER_LEVEL, + rtcio_interrupt, NULL); DEBUGASSERT(g_rtcio_cpuint >= 0); - /* Attach and enable the interrupt handler */ + /* Enable the interrupt */ - DEBUGVERIFY(irq_attach(ESP32S2_IRQ_RTC_CORE, rtcio_interrupt, NULL)); up_enable_irq(ESP32S2_IRQ_RTC_CORE); } #endif @@ -418,7 +441,7 @@ void esp32s2_rtcioirqinitialize(void) #ifdef CONFIG_ESP32S2_RTCIO_IRQ void esp32s2_rtcioirqenable(int irq) { - uintptr_t regaddr = RTC_CNTL_INT_ENA_RTC_REG; + uintptr_t regaddr = RTC_CNTL_INT_ENA_REG; uint32_t regval; int bit; @@ -451,7 +474,7 @@ void esp32s2_rtcioirqenable(int irq) #ifdef CONFIG_ESP32S2_RTCIO_IRQ void esp32s2_rtcioirqdisable(int irq) { - uintptr_t regaddr = RTC_CNTL_INT_ENA_RTC_REG; + uintptr_t regaddr = RTC_CNTL_INT_ENA_REG; uint32_t regval; int bit; @@ -472,3 +495,81 @@ void esp32s2_rtcioirqdisable(int irq) up_enable_irq(ESP32S2_IRQ_RTC_CORE); } #endif + +/**************************************************************************** + * Name: esp32s2_rtcioirqattach + * + * Description: + * Attach an interrupt handler to a specified RTC IRQ + * + * Input Parameters: + * irq - RTC IRQ number to attach the handler to + * handler - Interrupt handler function + * arg - Argument to pass to the handler + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32S2_RTCIO_IRQ +int esp32s2_rtcioirqattach(int irq, xcpt_t handler, void *arg) +{ + int bit; + + DEBUGASSERT(irq >= ESP32S2_FIRST_RTCIOIRQ_PERIPH && + irq <= ESP32S2_LAST_RTCIOIRQ_PERIPH); + + /* Convert the IRQ number to the corresponding bit */ + + bit = irq - ESP32S2_FIRST_RTCIOIRQ_PERIPH; + + DEBUGASSERT(bit >= 0 && bit < ESP32S2_NIRQ_RTCIO_PERIPH); + + /* Store the handler and argument */ + + g_rtcio_handlers[bit].handler = handler; + g_rtcio_handlers[bit].arg = arg; + + return OK; +} +#endif + +/**************************************************************************** + * Name: esp32s2_rtcioirqdetach + * + * Description: + * Detach an interrupt handler from a specified RTC IRQ + * + * Input Parameters: + * irq - RTC IRQ number to detach the handler from + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32S2_RTCIO_IRQ +int esp32s2_rtcioirqdetach(int irq) +{ + int bit; + + DEBUGASSERT(irq >= ESP32S2_FIRST_RTCIOIRQ_PERIPH && + irq <= ESP32S2_LAST_RTCIOIRQ_PERIPH); + + /* Convert the IRQ number to the corresponding bit */ + + bit = irq - ESP32S2_FIRST_RTCIOIRQ_PERIPH; + + DEBUGASSERT(bit >= 0 && bit < ESP32S2_NIRQ_RTCIO_PERIPH); + + /* Clear the handler and argument */ + + g_rtcio_handlers[bit].handler = NULL; + g_rtcio_handlers[bit].arg = NULL; + + return OK; +} +#endif diff --git a/arch/xtensa/src/esp32s2/esp32s2_rtc_gpio.h b/arch/xtensa/src/esp32s2/esp32s2_rtc_gpio.h index 5f46508790dfd..756c35257b2ac 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_rtc_gpio.h +++ b/arch/xtensa/src/esp32s2/esp32s2_rtc_gpio.h @@ -31,7 +31,7 @@ #include #include "hardware/esp32s2_rtc_io.h" -#include "hardware/esp32s2_rtccntl.h" +#include "soc/rtc_cntl_reg.h" /**************************************************************************** * Pre-processor Definitions @@ -608,7 +608,7 @@ int esp32s2_rtcioread(int rtcio_num); void esp32s2_rtciowrite(int rtcio_num, bool value); /**************************************************************************** - * Name: esp32s2_rtcioirqinitialize + * Name: esp_rtcioirqinitialize * * Description: * Initialize logic to support a second level of interrupt decoding for @@ -617,9 +617,9 @@ void esp32s2_rtciowrite(int rtcio_num, bool value); ****************************************************************************/ #ifdef CONFIG_ESP32S2_RTCIO_IRQ -void esp32s2_rtcioirqinitialize(void); +void esp_rtcioirqinitialize(void); #else -# define esp32s2_rtcioirqinitialize() +# define esp_rtcioirqinitialize() #endif /**************************************************************************** @@ -650,5 +650,49 @@ void esp32s2_rtcioirqdisable(int irq); # define esp32s2_rtcioirqdisable(irq) #endif +/**************************************************************************** + * Name: esp32s2_rtcioirqattach + * + * Description: + * Attach an interrupt handler to a specified RTC IRQ + * + * Input Parameters: + * irq - RTC IRQ number to attach the handler to + * handler - Interrupt handler function + * arg - Argument to pass to the handler + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32S2_RTCIO_IRQ +int esp32s2_rtcioirqattach(int irq, xcpt_t handler, void *arg); +#else +# define esp32s2_rtcioirqattach(irq, handler, arg) (-ENOSYS) +#endif + +/**************************************************************************** + * Name: esp32s2_rtcioirqdetach + * + * Description: + * Detach an interrupt handler from a specified RTC IRQ + * + * Input Parameters: + * irq - RTC IRQ number to detach the handler from + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32S2_RTCIO_IRQ +int esp32s2_rtcioirqdetach(int irq); +#else +# define esp32s2_rtcioirqdetach(irq) (-ENOSYS) +#endif + #endif /* __ASSEMBLY__ */ #endif /* __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_RTC_GPIO_H */ diff --git a/arch/xtensa/src/esp32s2/esp32s2_rtc_lowerhalf.c b/arch/xtensa/src/esp32s2/esp32s2_rtc_lowerhalf.c deleted file mode 100644 index 03a668ce17546..0000000000000 --- a/arch/xtensa/src/esp32s2/esp32s2_rtc_lowerhalf.c +++ /dev/null @@ -1,558 +0,0 @@ -/**************************************************************************** - * arch/xtensa/src/esp32s2/esp32s2_rtc_lowerhalf.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include -#include -#include -#include -#include -#include - -#include -#include - -#include "esp32s2_rtc.h" -#include "hardware/esp32s2_tim.h" - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -#ifdef CONFIG_RTC_ALARM -struct esp32s2_cbinfo_s -{ - volatile rtc_alarm_callback_t cb; /* Callback when the alarm expires */ - volatile void *priv; /* Private argument to accompany callback */ -}; -#endif - -/* This is the private type for the RTC state. It must be cast compatible - * with struct rtc_lowerhalf_s. - */ - -struct esp32s2_lowerhalf_s -{ - /* This is the contained reference to the read-only, lower-half - * operations vtable (which may lie in FLASH or ROM) - */ - - const struct rtc_ops_s *ops; - spinlock_t lock; -#ifdef CONFIG_RTC_ALARM - /* Alarm callback information */ - - struct esp32s2_cbinfo_s cbinfo[RTC_ALARM_LAST]; -#endif -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Prototypes for static methods in struct rtc_ops_s */ - -static int rtc_lh_rdtime(struct rtc_lowerhalf_s *lower, - struct rtc_time *rtctime); -static int rtc_lh_settime(struct rtc_lowerhalf_s *lower, - const struct rtc_time *rtctime); -static bool rtc_lh_havesettime(struct rtc_lowerhalf_s *lower); - -#ifdef CONFIG_RTC_ALARM -static void rtc_lh_alarm_callback(void *arg, unsigned int alarmid); -static int rtc_lh_setalarm(struct rtc_lowerhalf_s *lower, - const struct lower_setalarm_s *alarminfo); -static int rtc_lh_setrelative(struct rtc_lowerhalf_s *lower, - const struct lower_setrelative_s *alarminfo); -static int rtc_lh_cancelalarm(struct rtc_lowerhalf_s *lower, int alarmid); -static int rtc_lh_rdalarm(struct rtc_lowerhalf_s *lower, - struct lower_rdalarm_s *alarminfo); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* ESP32S2 RTC driver operations */ - -static const struct rtc_ops_s g_rtc_ops = -{ - .rdtime = rtc_lh_rdtime, - .settime = rtc_lh_settime, - .havesettime = rtc_lh_havesettime, -#ifdef CONFIG_RTC_ALARM - .setalarm = rtc_lh_setalarm, - .setrelative = rtc_lh_setrelative, - .cancelalarm = rtc_lh_cancelalarm, - .rdalarm = rtc_lh_rdalarm, -#endif -}; - -/* ESP32S2 RTC device state */ - -static struct esp32s2_lowerhalf_s g_rtc_lowerhalf = -{ - .ops = &g_rtc_ops, - .lock = SP_UNLOCKED, -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: rtc_lh_alarm_callback - * - * Description: - * This is the function that is called from the RTC driver when the alarm - * goes off. It just invokes the upper half drivers callback. - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_ALARM -static void rtc_lh_alarm_callback(void *arg, unsigned int alarmid) -{ - struct esp32s2_lowerhalf_s *lower; - struct esp32s2_cbinfo_s *cbinfo; - rtc_alarm_callback_t cb; - void *priv; - - DEBUGASSERT((RTC_ALARM0 <= alarmid) && (alarmid < RTC_ALARM_LAST)); - - lower = (struct esp32s2_lowerhalf_s *)arg; - cbinfo = &lower->cbinfo[alarmid]; - - /* Sample and clear the callback information to minimize the window in - * time in which race conditions can occur. - */ - - cb = (rtc_alarm_callback_t)cbinfo->cb; - priv = (void *)cbinfo->priv; - - cbinfo->cb = NULL; - cbinfo->priv = NULL; - - /* Perform the callback */ - - if (cb != NULL) - { - cb(priv, alarmid); - } -} -#endif /* CONFIG_RTC_ALARM */ - -/**************************************************************************** - * Name: rtc_lh_rdtime - * - * Description: - * Returns the current RTC time. - * - * Input Parameters: - * lower - A reference to RTC lower half driver state structure - * rcttime - The location in which to return the current RTC time. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on any failure. - * - ****************************************************************************/ - -static int rtc_lh_rdtime(struct rtc_lowerhalf_s *lower, - struct rtc_time *rtctime) -{ -#if defined(CONFIG_RTC_HIRES) - struct timespec ts; - int ret; - - /* Get the higher resolution time */ - - ret = up_rtc_gettime(&ts); - if (ret < 0) - { - goto errout; - } - - /* Convert the one second epoch time to a struct tm. This operation - * depends on the fact that struct rtc_time and struct tm are cast - * compatible. - */ - - if (!gmtime_r(&ts.tv_sec, (struct tm *)rtctime)) - { - ret = -get_errno(); - goto errout; - } - - return OK; - -errout: - rtcerr("ERROR: failed to get RTC time: %d\n", ret); - return ret; - -#else - time_t timer; - - /* The resolution of time is only 1 second */ - - timer = up_rtc_time(); - - /* Convert the one second epoch time to a struct tm */ - - if (gmtime_r(&timer, (struct tm *)rtctime) == 0) - { - int errcode = get_errno(); - DEBUGASSERT(errcode > 0); - - rtcerr("ERROR: gmtime_r failed: %d\n", errcode); - return -errcode; - } - - return OK; -#endif -} - -/**************************************************************************** - * Name: rtc_lh_settime - * - * Description: - * Implements the settime() method of the RTC driver interface - * - * Input Parameters: - * lower - A reference to RTC lower half driver state structure - * rcttime - The new time to set - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on any failure. - * - ****************************************************************************/ - -static int rtc_lh_settime(struct rtc_lowerhalf_s *lower, - const struct rtc_time *rtctime) -{ - struct timespec ts; - - /* Convert the struct rtc_time to a time_t. Here we assume that struct - * rtc_time is cast compatible with struct tm. - */ - - ts.tv_sec = mktime((struct tm *)rtctime); - ts.tv_nsec = 0; - - /* Now set the time (with an accuracy of seconds) */ - - return up_rtc_settime(&ts); -} - -/**************************************************************************** - * Name: rtc_lh_havesettime - * - * Description: - * Implements the havesettime() method of the RTC driver interface - * - * Input Parameters: - * lower - A reference to RTC lower half driver state structure - * - * Returned Value: - * Returns true if RTC date-time has been previously set. - * - ****************************************************************************/ - -static bool rtc_lh_havesettime(struct rtc_lowerhalf_s *lower) -{ - if (esp32s2_rtc_get_boot_time() == 0) - { - return false; - } - - return true; -} - -/**************************************************************************** - * Name: rtc_lh_setalarm - * - * Description: - * Set a new alarm. This function implements the setalarm() method of the - * RTC driver interface - * - * Input Parameters: - * lower - A reference to RTC lower half driver state structure - * alarminfo - Provided information needed to set the alarm - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on any failure. - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_ALARM -static int rtc_lh_setalarm(struct rtc_lowerhalf_s *lower, - const struct lower_setalarm_s *alarminfo) -{ - struct esp32s2_lowerhalf_s *priv; - struct esp32s2_cbinfo_s *cbinfo; - struct alm_setalarm_s lowerinfo; - int ret; - - DEBUGASSERT(lower != NULL && alarminfo != NULL); - DEBUGASSERT((RTC_ALARM0 <= alarminfo->id) && - (alarminfo->id < RTC_ALARM_LAST)); - - priv = (struct esp32s2_lowerhalf_s *)lower; - - /* Remember the callback information */ - - cbinfo = &priv->cbinfo[alarminfo->id]; - cbinfo->cb = alarminfo->cb; - cbinfo->priv = alarminfo->priv; - - /* Set the alarm */ - - lowerinfo.as_id = alarminfo->id; - lowerinfo.as_cb = rtc_lh_alarm_callback; - lowerinfo.as_arg = priv; - - /* Convert the RTC time to a timespec (1 second accuracy) */ - - lowerinfo.as_time.tv_sec = mktime((struct tm *)&alarminfo->time); - lowerinfo.as_time.tv_nsec = 0; - - /* And set the alarm */ - - ret = up_rtc_setalarm(&lowerinfo); - if (ret < 0) - { - cbinfo->cb = NULL; - cbinfo->priv = NULL; - } - - return ret; -} -#endif /* CONFIG_RTC_ALARM */ - -/**************************************************************************** - * Name: rtc_lh_setrelative - * - * Description: - * Set a new alarm relative to the current time. This function implements - * the setrelative() method of the RTC driver interface - * - * Input Parameters: - * lower - A reference to RTC lower half driver state structure - * alarminfo - Provided information needed to set the alarm - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on any failure. - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_ALARM -static int rtc_lh_setrelative(struct rtc_lowerhalf_s *lower, - const struct lower_setrelative_s *alarminfo) -{ - struct esp32s2_lowerhalf_s *priv = (struct esp32s2_lowerhalf_s *)lower; - struct lower_setalarm_s setalarm; - time_t seconds; - int ret = -EINVAL; - irqstate_t flags; - - DEBUGASSERT(lower != NULL && alarminfo != NULL); - DEBUGASSERT((RTC_ALARM0 <= alarminfo->id) && - (alarminfo->id < RTC_ALARM_LAST)); - - if (alarminfo->reltime > 0) - { - flags = spin_lock_irqsave(&priv->lock); - - seconds = alarminfo->reltime; - gmtime_r(&seconds, (struct tm *)&setalarm.time); - - /* The set the alarm using this absolute time */ - - setalarm.id = alarminfo->id; - setalarm.cb = alarminfo->cb; - setalarm.priv = alarminfo->priv; - ret = rtc_lh_setalarm(lower, &setalarm); - - spin_unlock_irqrestore(&priv->lock, flags); - } - - return ret; -} -#endif /* CONFIG_RTC_ALARM */ - -/**************************************************************************** - * Name: rtc_lh_cancelalarm - * - * Description: - * Cancel the current alarm. This function implements the cancelalarm() - * method of the RTC driver interface - * - * Input Parameters: - * lower - A reference to RTC lower half driver state structure - * alarmid - the alarm id - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on any failure. - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_ALARM -static int rtc_lh_cancelalarm(struct rtc_lowerhalf_s *lower, int alarmid) -{ - struct esp32s2_lowerhalf_s *priv; - struct esp32s2_cbinfo_s *cbinfo; - - DEBUGASSERT(lower != NULL); - DEBUGASSERT((RTC_ALARM0 <= alarmid) && (alarmid < RTC_ALARM_LAST)); - - priv = (struct esp32s2_lowerhalf_s *)lower; - - /* Nullify callback information to reduce window for race conditions */ - - cbinfo = &priv->cbinfo[alarmid]; - cbinfo->cb = NULL; - cbinfo->priv = NULL; - - /* Then cancel the alarm */ - - return up_rtc_cancelalarm((enum alm_id_e)alarmid); -} -#endif /* CONFIG_RTC_ALARM */ - -/**************************************************************************** - * Name: rtc_lh_rdalarm - * - * Description: - * Query the RTC alarm. - * - * Input Parameters: - * lower - A reference to RTC lower half driver state structure - * alarminfo - Provided information needed to query the alarm - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on any failure. - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_ALARM -static int rtc_lh_rdalarm(struct rtc_lowerhalf_s *lower, - struct lower_rdalarm_s *alarminfo) -{ - struct esp32s2_lowerhalf_s *priv = (struct esp32s2_lowerhalf_s *)lower; - struct timespec ts; - int ret; - irqstate_t flags; - - DEBUGASSERT(lower != NULL && alarminfo != NULL && alarminfo->time != NULL); - DEBUGASSERT((RTC_ALARM0 <= alarminfo->id) && - (alarminfo->id < RTC_ALARM_LAST)); - - flags = spin_lock_irqsave(&priv->lock); - - ret = up_rtc_rdalarm(&ts, alarminfo->id); - localtime_r((const time_t *)&ts.tv_sec, - (struct tm *)alarminfo->time); - - spin_unlock_irqrestore(&priv->lock, flags); - - return ret; -} -#endif /* CONFIG_RTC_ALARM */ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32s2_rtc_lowerhalf - * - * Description: - * Instantiate the RTC lower half driver for the ESP32S2. - * - * Input Parameters: - * None - * - * Returned Value: - * On success, a non-NULL RTC lower interface is returned. NULL is - * returned on any failure. - * - ****************************************************************************/ - -struct rtc_lowerhalf_s *esp32s2_rtc_lowerhalf(void) -{ - return (struct rtc_lowerhalf_s *)&g_rtc_lowerhalf; -} - -/**************************************************************************** - * Name: esp32s2_rtc_driverinit - * - * Description: - * Bind the configuration timer to a timer lower half instance and register - * the timer drivers at 'devpath' - * - * Input Parameters: - * None - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned - * to indicate the nature of any failure. - * - ****************************************************************************/ - -int esp32s2_rtc_driverinit(void) -{ - int ret = ERROR; - struct rtc_lowerhalf_s *lower; - - /* Instantiate the ESP32S2 lower-half RTC driver */ - - lower = esp32s2_rtc_lowerhalf(); - if (lower == NULL) - { - return ret; - } - else - { - /* Bind the lower half driver and register the combined RTC driver - * as /dev/rtc0 - */ - - ret = rtc_initialize(0, lower); - } - - /* Init RTC timer */ - - up_rtc_timer_init(); - - return ret; -} diff --git a/arch/xtensa/src/esp32s2/esp32s2_rtc_lowerhalf.h b/arch/xtensa/src/esp32s2/esp32s2_rtc_lowerhalf.h deleted file mode 100644 index ecf80cace926b..0000000000000 --- a/arch/xtensa/src/esp32s2/esp32s2_rtc_lowerhalf.h +++ /dev/null @@ -1,56 +0,0 @@ -/**************************************************************************** - * arch/xtensa/src/esp32s2/esp32s2_rtc_lowerhalf.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_RTC_LOWERHALF_H -#define __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_RTC_LOWERHALF_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#ifdef CONFIG_RTC_DRIVER - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32s2_rtc_driverinit - * - * Description: - * Bind the configuration timer to a timer lower half instance and register - * the timer drivers at 'devpath' - * - * Input Parameters: - * None - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned - * to indicate the nature of any failure. - * - ****************************************************************************/ - -int esp32s2_rtc_driverinit(void); - -#endif /* CONFIG_RTC_DRIVER */ - -#endif /* __ARCH_XTENSA_SRC_ESP32S2_ESP32S2_RTC_LOWERHALF_H */ diff --git a/arch/xtensa/src/esp32s2/esp32s2_serial.c b/arch/xtensa/src/esp32s2/esp32s2_serial.c index 9363e6ed48fb7..93153e361cf11 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_serial.c +++ b/arch/xtensa/src/esp32s2/esp32s2_serial.c @@ -43,9 +43,9 @@ #include "xtensa.h" #include "esp32s2_config.h" -#include "esp32s2_irq.h" +#include "espressif/esp_irq.h" #include "esp32s2_lowputc.h" -#include "esp32s2_gpio.h" +#include "espressif/esp_gpio.h" #include "hardware/esp32s2_uart.h" #include "hardware/esp32s2_system.h" @@ -244,7 +244,7 @@ static int uart_handler(int irq, void *context, void *arg) { if (dev->xmit.tail == dev->xmit.head) { - esp32s2_gpiowrite(priv->rs485_dir_gpio, + esp_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); } } @@ -464,14 +464,13 @@ static void esp32s2_shutdown(struct uart_dev_s *dev) static int esp32s2_attach(struct uart_dev_s *dev) { struct esp32s2_uart_s *priv = dev->priv; - int ret; DEBUGASSERT(priv->cpuint == -ENOMEM); - /* Set up to receive peripheral interrupts */ + /* Set up to receive peripheral interrupts on the current CPU */ - priv->cpuint = esp32s2_setup_irq(priv->periph, priv->int_pri, - ESP32S2_CPUINT_LEVEL); + priv->cpuint = esp_setup_irq(priv->periph, priv->int_pri, + ESP_IRQ_TRIGGER_LEVEL, uart_handler, dev); if (priv->cpuint < 0) { /* Failed to allocate a CPU interrupt of this type */ @@ -479,19 +478,13 @@ static int esp32s2_attach(struct uart_dev_s *dev) return priv->cpuint; } - /* Attach and enable the IRQ */ - - ret = irq_attach(priv->irq, uart_handler, dev); - if (ret == OK) - { - /* Enable the CPU interrupt (RX and TX interrupts are still disabled - * in the UART - */ + /* Enable the CPU interrupt (RX and TX interrupts are still disabled + * in the UART) + */ - up_enable_irq(priv->irq); - } + up_enable_irq(priv->irq); - return ret; + return OK; } /**************************************************************************** @@ -513,14 +506,15 @@ static void esp32s2_detach(struct uart_dev_s *dev) DEBUGASSERT(priv->cpuint != -ENOMEM); - /* Disable and detach the CPU interrupt */ + /* Disable the CPU interrupt */ up_disable_irq(priv->irq); - irq_detach(priv->irq); - /* Disassociate the peripheral interrupt from the CPU interrupt */ + /* Disassociate the peripheral interrupt from the CPU interrupt. + * This also clears the handler from the HAL's interrupt table. + */ - esp32s2_teardown_irq(priv->periph, priv->cpuint); + esp_teardown_irq(priv->periph, priv->cpuint); priv->cpuint = -ENOMEM; } @@ -705,7 +699,7 @@ static void esp32s2_send(struct uart_dev_s *dev, int ch) #ifdef HAVE_RS485 if (priv->rs485_dir_gpio != 0) { - esp32s2_gpiowrite(priv->rs485_dir_gpio, priv->rs485_dir_polarity); + esp_gpiowrite(priv->rs485_dir_gpio, priv->rs485_dir_polarity); } #endif diff --git a/arch/xtensa/src/esp32s2/esp32s2_spi.c b/arch/xtensa/src/esp32s2/esp32s2_spi.c index e87012c119b40..b42a171c52bf1 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_spi.c +++ b/arch/xtensa/src/esp32s2/esp32s2_spi.c @@ -46,8 +46,8 @@ #include #include "esp32s2_spi.h" -#include "esp32s2_irq.h" -#include "esp32s2_gpio.h" +#include "espressif/esp_irq.h" +#include "espressif/esp_gpio.h" #if defined(CONFIG_ESP32S2_SPI2_DMA) || defined(CONFIG_ESP32S2_SPI3_DMA) #include "esp32s2_dma.h" @@ -638,7 +638,7 @@ static void esp32s2_spi_select(struct spi_dev_s *dev, #if SPI_HAVE_SWCS struct esp32s2_spi_priv_s *priv = (struct esp32s2_spi_priv_s *)dev; - esp32s2_gpiowrite(priv->config->cs_pin, !selected); + esp_gpiowrite(priv->config->cs_pin, !selected); #endif spiinfo("devid: %08" PRIx32 " CS: %s\n", @@ -1496,14 +1496,14 @@ static void esp32s2_spi_init(struct spi_dev_s *dev) const uint32_t id = config->id; uint32_t regval; - esp32s2_gpiowrite(config->cs_pin, true); - esp32s2_gpiowrite(config->mosi_pin, true); - esp32s2_gpiowrite(config->miso_pin, true); - esp32s2_gpiowrite(config->clk_pin, true); + esp_gpiowrite(config->cs_pin, true); + esp_gpiowrite(config->mosi_pin, true); + esp_gpiowrite(config->miso_pin, true); + esp_gpiowrite(config->clk_pin, true); #if SPI_HAVE_SWCS - esp32s2_configgpio(config->cs_pin, OUTPUT_FUNCTION_1); - esp32s2_gpio_matrix_out(config->cs_pin, SIG_GPIO_OUT_IDX, 0, 0); + esp_configgpio(config->cs_pin, OUTPUT_FUNCTION_1); + esp_gpio_matrix_out(config->cs_pin, SIG_GPIO_OUT_IDX, 0, 0); #endif /* SPI3 doesn't have IOMUX, if SPI3 is enabled use GPIO Matrix for both */ @@ -1511,32 +1511,32 @@ static void esp32s2_spi_init(struct spi_dev_s *dev) if (esp32s2_spi_iomux(priv)) { #if !SPI_HAVE_SWCS - esp32s2_configgpio(config->cs_pin, OUTPUT_FUNCTION_5); - esp32s2_gpio_matrix_out(config->cs_pin, SIG_GPIO_OUT_IDX, 0, 0); + esp_configgpio(config->cs_pin, OUTPUT_FUNCTION_5); + esp_gpio_matrix_out(config->cs_pin, SIG_GPIO_OUT_IDX, 0, 0); #endif - esp32s2_configgpio(config->mosi_pin, OUTPUT_FUNCTION_5); - esp32s2_gpio_matrix_out(config->mosi_pin, SIG_GPIO_OUT_IDX, 0, 0); + esp_configgpio(config->mosi_pin, OUTPUT_FUNCTION_5); + esp_gpio_matrix_out(config->mosi_pin, SIG_GPIO_OUT_IDX, 0, 0); - esp32s2_configgpio(config->miso_pin, INPUT_FUNCTION_5 | PULLUP); - esp32s2_gpio_matrix_out(config->miso_pin, SIG_GPIO_OUT_IDX, 0, 0); + esp_configgpio(config->miso_pin, INPUT_FUNCTION_5 | PULLUP); + esp_gpio_matrix_out(config->miso_pin, SIG_GPIO_OUT_IDX, 0, 0); - esp32s2_configgpio(config->clk_pin, OUTPUT_FUNCTION_5); - esp32s2_gpio_matrix_out(config->clk_pin, SIG_GPIO_OUT_IDX, 0, 0); + esp_configgpio(config->clk_pin, OUTPUT_FUNCTION_5); + esp_gpio_matrix_out(config->clk_pin, SIG_GPIO_OUT_IDX, 0, 0); } else { #if !SPI_HAVE_SWCS - esp32s2_configgpio(config->cs_pin, OUTPUT); - esp32s2_gpio_matrix_out(config->cs_pin, config->cs_outsig, 0, 0); + esp_configgpio(config->cs_pin, OUTPUT); + esp_gpio_matrix_out(config->cs_pin, config->cs_outsig, 0, 0); #endif - esp32s2_configgpio(config->mosi_pin, OUTPUT); - esp32s2_gpio_matrix_out(config->mosi_pin, config->mosi_outsig, 0, 0); + esp_configgpio(config->mosi_pin, OUTPUT); + esp_gpio_matrix_out(config->mosi_pin, config->mosi_outsig, 0, 0); - esp32s2_configgpio(config->miso_pin, INPUT | PULLUP); - esp32s2_gpio_matrix_in(config->miso_pin, config->miso_insig, 0); + esp_configgpio(config->miso_pin, INPUT | PULLUP); + esp_gpio_matrix_in(config->miso_pin, config->miso_insig, 0); - esp32s2_configgpio(config->clk_pin, OUTPUT); - esp32s2_gpio_matrix_out(config->clk_pin, config->clk_outsig, 0, 0); + esp_configgpio(config->clk_pin, OUTPUT); + esp_gpio_matrix_out(config->clk_pin, config->clk_outsig, 0, 0); } modifyreg32(SYSTEM_PERIP_CLK_EN0_REG, 0, config->clk_bit); @@ -1681,17 +1681,17 @@ struct spi_dev_s *esp32s2_spibus_initialize(int port) /* Disable the provided CPU Interrupt to configure it. */ up_disable_irq(priv->config->irq); - esp32s2_teardown_irq(priv->config->periph, priv->cpuint); - irq_detach(priv->config->irq); + esp_teardown_irq(priv->config->periph, priv->cpuint); priv->cpuint = -ENOMEM; } /* Set up to receive peripheral interrupts on the current CPU */ - priv->cpuint = esp32s2_setup_irq(priv->config->periph, - ESP32S2_INT_PRIO_DEF, - ESP32S2_CPUINT_LEVEL); + priv->cpuint = esp_setup_irq(priv->config->periph, + ESP32S2_INT_PRIO_DEF, + ESP_IRQ_TRIGGER_LEVEL, + esp32s2_spi_interrupt, priv); if (priv->cpuint < 0) { /* Failed to allocate a CPU interrupt of this type. */ @@ -1700,19 +1700,6 @@ struct spi_dev_s *esp32s2_spibus_initialize(int port) return NULL; } - /* Attach and enable the IRQ */ - - if (irq_attach(priv->config->irq, esp32s2_spi_interrupt, priv) != OK) - { - /* Failed to attach IRQ, so CPU interrupt must be freed. */ - - esp32s2_teardown_irq(priv->config->periph, priv->cpuint); - priv->cpuint = -ENOMEM; - nxmutex_unlock(&priv->lock); - - return NULL; - } - /* Enable the CPU interrupt that is linked to the SPI device. */ up_enable_irq(priv->config->irq); @@ -1759,8 +1746,7 @@ int esp32s2_spibus_uninitialize(struct spi_dev_s *dev) #if defined(CONFIG_ESP32S2_SPI2_DMA) || defined(CONFIG_ESP32S2_SPI3_DMA) up_disable_irq(priv->config->irq); - esp32s2_teardown_irq(priv->config->periph, priv->cpuint); - irq_detach(priv->config->irq); + esp_teardown_irq(priv->config->periph, priv->cpuint); priv->cpuint = -ENOMEM; diff --git a/arch/xtensa/src/esp32s2/esp32s2_spi_slave.c b/arch/xtensa/src/esp32s2/esp32s2_spi_slave.c index 397aefb105575..c3a9518bc0dd2 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_spi_slave.c +++ b/arch/xtensa/src/esp32s2/esp32s2_spi_slave.c @@ -45,8 +45,8 @@ #include #include "esp32s2_spi.h" -#include "esp32s2_irq.h" -#include "esp32s2_gpio.h" +#include "espressif/esp_irq.h" +#include "espressif/esp_gpio.h" #ifdef CONFIG_ESP32S2_SPI_DMA #include "esp32s2_dma.h" @@ -217,7 +217,7 @@ struct spislave_priv_s /* SPI Slave controller interrupt handlers */ static int spislave_cs_interrupt(int irq, void *context, void *arg); -static int spislave_periph_interrupt(int irq, void *context, void *arg); +static void spislave_periph_interrupt(void *arg); /* SPI Slave controller internal functions */ @@ -947,7 +947,7 @@ static void spislave_prepare_next_tx(struct spislave_priv_s *priv) * ****************************************************************************/ -static int spislave_periph_interrupt(int irq, void *context, void *arg) +static void spislave_periph_interrupt(void *arg) { struct spislave_priv_s *priv = (struct spislave_priv_s *)arg; uint32_t regval = getreg32(SPI_SLAVE1_REG(priv->config->id)); @@ -983,7 +983,7 @@ static int spislave_periph_interrupt(int irq, void *context, void *arg) spislave_prepare_next_tx(priv); - if (priv->is_processing && esp32s2_gpioread(priv->config->cs_pin)) + if (priv->is_processing && esp_gpioread(priv->config->cs_pin)) { priv->is_processing = false; SPIS_DEV_SELECT(priv->dev, false); @@ -992,8 +992,6 @@ static int spislave_periph_interrupt(int irq, void *context, void *arg) /* Clear the trans_done interrupt flag */ setbits(int_clear, SPI_DMA_INT_CLR_REG(priv->config->id)); - - return 0; } /**************************************************************************** @@ -1066,16 +1064,16 @@ static void spislave_initializ_iomux(struct spislave_priv_s *priv) uint32_t attr = INPUT_FUNCTION_5 | DRIVE_0; const struct spislave_config_s *config = priv->config; - esp32s2_configgpio(config->cs_pin, attr); - esp32s2_configgpio(config->clk_pin, attr); + esp_configgpio(config->cs_pin, attr | RISING); + esp_configgpio(config->clk_pin, attr); - esp32s2_gpio_matrix_out(config->cs_pin, SIG_GPIO_OUT_IDX, 0, 0); - esp32s2_gpio_matrix_out(config->clk_pin, SIG_GPIO_OUT_IDX, 0, 0); - esp32s2_gpio_matrix_out(config->mosi_pin, SIG_GPIO_OUT_IDX, 0, 0); - esp32s2_gpio_matrix_out(config->miso_pin, SIG_GPIO_OUT_IDX, 0, 0); + esp_gpio_matrix_out(config->cs_pin, SIG_GPIO_OUT_IDX, 0, 0); + esp_gpio_matrix_out(config->clk_pin, SIG_GPIO_OUT_IDX, 0, 0); + esp_gpio_matrix_out(config->mosi_pin, SIG_GPIO_OUT_IDX, 0, 0); + esp_gpio_matrix_out(config->miso_pin, SIG_GPIO_OUT_IDX, 0, 0); - esp32s2_configgpio(config->mosi_pin, attr); - esp32s2_configgpio(config->miso_pin, OUTPUT_FUNCTION_5); + esp_configgpio(config->mosi_pin, attr); + esp_configgpio(config->miso_pin, OUTPUT_FUNCTION_5); } #endif @@ -1099,17 +1097,17 @@ static void spislave_initializ_iomatrix(struct spislave_priv_s *priv) uint32_t attr = INPUT | DRIVE_0; const struct spislave_config_s *config = priv->config; - esp32s2_configgpio(config->cs_pin, attr); - esp32s2_gpio_matrix_in(config->cs_pin, config->cs_insig, 0); + esp_configgpio(config->cs_pin, attr | RISING); + esp_gpio_matrix_in(config->cs_pin, config->cs_insig, 0); - esp32s2_configgpio(config->clk_pin, attr); - esp32s2_gpio_matrix_in(config->clk_pin, config->clk_insig, 0); + esp_configgpio(config->clk_pin, attr); + esp_gpio_matrix_in(config->clk_pin, config->clk_insig, 0); - esp32s2_configgpio(config->mosi_pin, attr); - esp32s2_gpio_matrix_in(config->mosi_pin, config->mosi_insig, 0); + esp_configgpio(config->mosi_pin, attr); + esp_gpio_matrix_in(config->mosi_pin, config->mosi_insig, 0); - esp32s2_configgpio(config->miso_pin, OUTPUT); - esp32s2_gpio_matrix_out(config->miso_pin, config->miso_outsig, 0, 0); + esp_configgpio(config->miso_pin, OUTPUT); + esp_gpio_matrix_out(config->miso_pin, config->miso_outsig, 0, 0); } #endif @@ -1205,7 +1203,7 @@ static void spislave_initialize(struct spi_slave_ctrlr_s *ctrlr) spislave_dma_init(priv); #endif - esp32s2_gpioirqenable(ESP32S2_PIN2IRQ(config->cs_pin), RISING); + esp_gpioirqenable(config->cs_pin); /* Force a transaction done interrupt. * This interrupt won't fire yet because we initialized the SPI interrupt @@ -1237,7 +1235,7 @@ static void spislave_deinitialize(struct spi_slave_ctrlr_s *ctrlr) { struct spislave_priv_s *priv = (struct spislave_priv_s *)ctrlr; - esp32s2_gpioirqdisable(ESP32S2_PIN2IRQ(priv->config->cs_pin)); + esp_gpioirqdisable(priv->config->cs_pin); /* Disable the trans_done interrupt */ @@ -1374,7 +1372,7 @@ static void spislave_unbind(struct spi_slave_ctrlr_s *ctrlr) up_disable_irq(priv->config->irq); - esp32s2_gpioirqdisable(ESP32S2_PIN2IRQ(priv->config->cs_pin)); + esp_gpioirqdisable(priv->config->cs_pin); /* Disable the trans_done interrupt */ @@ -1596,6 +1594,7 @@ struct spi_slave_ctrlr_s *esp32s2_spislave_ctrlr_initialize(int port) struct spi_slave_ctrlr_s *spislave_dev; struct spislave_priv_s *priv; irqstate_t flags; + int ret; switch (port) { @@ -1626,28 +1625,25 @@ struct spi_slave_ctrlr_s *esp32s2_spislave_ctrlr_initialize(int port) /* Attach IRQ for CS pin interrupt */ - DEBUGVERIFY(irq_attach(ESP32S2_PIN2IRQ(priv->config->cs_pin), - spislave_cs_interrupt, - priv)); - - priv->cpu = this_cpu(); - priv->cpuint = esp32s2_setup_irq(priv->config->periph, - ESP32S2_INT_PRIO_DEF, - ESP32S2_CPUINT_LEVEL); - if (priv->cpuint < 0) + ret = esp_gpio_irq(priv->config->cs_pin, + spislave_cs_interrupt, + priv); + if (ret < 0) { - /* Failed to allocate a CPU interrupt of this type. */ - + spierr("esp_gpio_irq() failed: %d\n", ret); leave_critical_section(flags); - return NULL; } - if (irq_attach(priv->config->irq, spislave_periph_interrupt, priv) != OK) + priv->cpu = this_cpu(); + priv->cpuint = esp_setup_irq(priv->config->periph, + ESP32S2_INT_PRIO_DEF, + ESP_IRQ_TRIGGER_LEVEL, + spislave_periph_interrupt, priv); + if (priv->cpuint < 0) { - /* Failed to attach IRQ, so CPU interrupt must be freed. */ + /* Failed to allocate a CPU interrupt of this type. */ - esp32s2_teardown_irq(priv->config->periph, priv->cpuint); leave_critical_section(flags); return NULL; @@ -1695,7 +1691,7 @@ int esp32s2_spislave_ctrlr_uninitialize(struct spi_slave_ctrlr_s *ctrlr) } up_disable_irq(priv->config->irq); - esp32s2_teardown_irq(priv->config->periph, priv->cpuint); + esp_teardown_irq(priv->config->periph, priv->cpuint); priv->cpuint = -ENOMEM; spislave_deinitialize(ctrlr); diff --git a/arch/xtensa/src/esp32s2/esp32s2_start.c b/arch/xtensa/src/esp32s2/esp32s2_start.c index b524c7449f2d7..4d85c3c1eb04e 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_start.c +++ b/arch/xtensa/src/esp32s2/esp32s2_start.c @@ -35,13 +35,11 @@ #include "hardware/esp32s2_cache_memory.h" #include "rom/esp32s2_libc_stubs.h" -#include "esp32s2_clockconfig.h" #include "esp32s2_region.h" #include "esp32s2_spiram.h" #include "esp32s2_start.h" #include "esp32s2_lowputc.h" #include "esp32s2_wdt.h" -#include "esp32s2_rtc.h" #include "espressif/esp_loader.h" #include "soc/extmem_reg.h" @@ -128,6 +126,8 @@ extern void cache_allocate_sram(cache_layout_t sram0_layout, cache_layout_t sram3_layout); extern void esp_config_data_cache_mode(void); extern void cache_enable_dcache(uint32_t autoload); +extern void esp_config_instruction_cache_mode(void); +extern void esp_config_data_cache_mode(void); /**************************************************************************** * Private Function Prototypes @@ -160,59 +160,6 @@ uint32_t g_idlestack[IDLETHREAD_STACKWORDS] * Private Functions ****************************************************************************/ -/**************************************************************************** - * Name: configure_cpu_caches - * - * Description: - * Configure the Instruction and Data CPU caches. - * - * Input Parameters: - * None. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -static void IRAM_ATTR configure_cpu_caches(void) -{ - cache_size_t cache_size; - cache_ways_t cache_ways; - cache_line_size_t cache_line_size; - - /* Configure the mode of instruction cache: cache size, cache associated - * ways, cache line size. - */ - -#ifdef CONFIG_ESP32S2_INSTRUCTION_CACHE_8KB - cache_allocate_sram(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_INVALID, - CACHE_MEMORY_INVALID, CACHE_MEMORY_INVALID); - cache_size = CACHE_SIZE_HALF; -#else - cache_allocate_sram(CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_ICACHE_HIGH, - CACHE_MEMORY_INVALID, CACHE_MEMORY_INVALID); - cache_size = CACHE_SIZE_FULL; -#endif - - cache_ways = CACHE_4WAYS_ASSOC; - -#if defined(CONFIG_ESP32S2_INSTRUCTION_CACHE_LINE_16B) - cache_line_size = CACHE_LINE_SIZE_16B; -#else - cache_line_size = CACHE_LINE_SIZE_32B; -#endif - - cache_suspend_icache(); - cache_set_icache_mode(cache_size, cache_ways, cache_line_size); - cache_invalidate_icache_all(); - cache_resume_icache(0); - -#if defined(CONFIG_ESP32S2_SPIRAM_BOOT_INIT) - esp_config_data_cache_mode(); - cache_enable_dcache(0); -#endif -} - /**************************************************************************** * Name: __esp32s2_start * @@ -287,21 +234,18 @@ static void noreturn_function IRAM_ATTR __esp32s2_start(void) esp32s2_wdt_early_deinit(); - /* Initialize RTC parameters */ - - esp32s2_rtc_init(); - esp32s2_rtc_clk_set(); - - /* Set CPU frequency configured in board.h */ + /* Initialize RTC controller and set CPU frequency */ - esp32s2_clockconfig(); + esp_clk_init(); -#ifndef CONFIG_SUPPRESS_UART_CONFIG /* Configure the UART so we can get debug output */ +#ifndef CONFIG_SUPPRESS_UART_CONFIG esp32s2_lowsetup(); #endif + esp_perip_clk_init(); + #ifdef USE_EARLYSERIALINIT /* Perform early serial initialization */ @@ -342,10 +286,6 @@ static void noreturn_function IRAM_ATTR __esp32s2_start(void) showprogress('B'); - SYS_STARTUP_FN(); - - showprogress('C'); - /* Bring up NuttX */ nx_start(); @@ -356,6 +296,48 @@ static void noreturn_function IRAM_ATTR __esp32s2_start(void) * Public Functions ****************************************************************************/ +/**************************************************************************** + * Name: xtensa_soc_initialize + * + * Description: + * Initialize SoC-specific initialization. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void weak_function xtensa_soc_initialize(void) +{ + sys_startup_fn(); +} + +/**************************************************************************** + * Name: sys_startup_fn + * + * Description: + * Execute the system layer startup function for the current CPU core. + * This function calls the appropriate startup function from the per-CPU + * startup function array (g_startup_fn) based on the current core ID. + * The SYS_STARTUP_FN() macro retrieves the core ID, indexes into the + * g_startup_fn array, and invokes the corresponding startup function. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void sys_startup_fn(void) +{ + SYS_STARTUP_FN(); +} + /**************************************************************************** * Name: __start * @@ -398,7 +380,21 @@ noreturn_function void IRAM_ATTR __start(void) #endif - configure_cpu_caches(); + /* Configure the mode of instruction cache : cache size, cache associated + * ways, cache line size. + */ + + esp_config_instruction_cache_mode(); + + /* If we need use SPIRAM, we should use data cache, or if we want to access + * rodata, we also should use data cache. + * Configure the mode of data : cache size, cache associated ways, cache + * line size. + * Enable data cache, so if we don't use SPIRAM, it just works. + */ + + esp_config_data_cache_mode(); + cache_enable_dcache(0); __esp32s2_start(); diff --git a/arch/xtensa/src/esp32s2/esp32s2_start.h b/arch/xtensa/src/esp32s2/esp32s2_start.h index 42628243da129..74d252800de9a 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_start.h +++ b/arch/xtensa/src/esp32s2/esp32s2_start.h @@ -33,6 +33,26 @@ * Pre-processor Definitions ****************************************************************************/ +/**************************************************************************** + * Name: sys_startup_fn + * + * Description: + * Execute the system layer startup function for the current CPU core. + * This function calls the appropriate startup function from the per-CPU + * startup function array (g_startup_fn) based on the current core ID. + * The SYS_STARTUP_FN() macro retrieves the core ID, indexes into the + * g_startup_fn array, and invokes the corresponding startup function. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void sys_startup_fn(void); + /**************************************************************************** * Name: esp32s2_board_initialize * diff --git a/arch/xtensa/src/esp32s2/esp32s2_systemreset.c b/arch/xtensa/src/esp32s2/esp32s2_systemreset.c index 2f730758f3272..93ca69fabf456 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_systemreset.c +++ b/arch/xtensa/src/esp32s2/esp32s2_systemreset.c @@ -30,7 +30,7 @@ #include #include "xtensa.h" -#include "hardware/esp32s2_rtccntl.h" +#include "soc/rtc_cntl_reg.h" #include "esp32s2_systemreset.h" /**************************************************************************** diff --git a/arch/xtensa/src/esp32s2/esp32s2_tim.c b/arch/xtensa/src/esp32s2/esp32s2_tim.c index 1f1be2d0efe35..5ec7fcd824537 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_tim.c +++ b/arch/xtensa/src/esp32s2/esp32s2_tim.c @@ -33,7 +33,7 @@ #include #include "xtensa.h" -#include "esp32s2_irq.h" +#include "espressif/esp_irq.h" #include "esp32s2_tim.h" #include "hardware/esp32s2_system.h" #include "hardware/esp32s2_systimer.h" @@ -234,22 +234,6 @@ struct esp32s2_tim_priv_s g_esp32s2_tim3_priv = }; #endif -#ifdef CONFIG_ESP32S2_RT_TIMER -/* SYSTIMER */ - -struct esp32s2_tim_priv_s g_esp32s2_tim4_priv = -{ - .ops = &esp32s2_systim_ops, - .gid = -ENODEV, /* There's no group in systimer */ - .tid = SYSTIMER_COMP0, /* Systimer contains 1 counter and 3 comps */ - .int_pri = ESP32S2_INT_PRIO_DEF, - .periph = ESP32S2_PERIPH_SYSTIMER_TARGET0, /* Peripheral ID */ - .irq = ESP32S2_IRQ_SYSTIMER_TARGET0, /* Interrupt ID */ - .cpuint = -ENOMEM, /* CPU interrupt assigned to this timer */ - .inuse = false, -}; -#endif - /**************************************************************************** * Private Functions ****************************************************************************/ @@ -964,8 +948,7 @@ static int esp32s2_tim_setisr(struct esp32s2_tim_dev_s *dev, */ up_disable_irq(priv->irq); - esp32s2_teardown_irq(priv->periph, priv->cpuint); - irq_detach(priv->irq); + esp_teardown_irq(priv->periph, priv->cpuint); priv->cpuint = -ENOMEM; } @@ -984,13 +967,14 @@ static int esp32s2_tim_setisr(struct esp32s2_tim_dev_s *dev, if (priv->tid == SYSTIMER_COMP0) { - priv->cpuint = esp32s2_setup_irq(priv->periph, priv->int_pri, - ESP32S2_CPUINT_EDGE); + priv->cpuint = esp_setup_irq(priv->periph, priv->int_pri, + ESP_IRQ_TRIGGER_EDGE, handler, arg); } else { - priv->cpuint = esp32s2_setup_irq(priv->periph, priv->int_pri, - ESP32S2_CPUINT_LEVEL); + priv->cpuint = esp_setup_irq(priv->periph, priv->int_pri, + ESP_IRQ_TRIGGER_LEVEL, + handler, arg); } if (priv->cpuint < 0) @@ -1000,16 +984,6 @@ static int esp32s2_tim_setisr(struct esp32s2_tim_dev_s *dev, goto errout; } - /* Associate an IRQ Number (from the timer) to an ISR */ - - ret = irq_attach(priv->irq, handler, arg); - if (ret != OK) - { - esp32s2_teardown_irq(priv->periph, priv->cpuint); - tmrerr("ERROR: Failed to associate an IRQ Number"); - goto errout; - } - /* Enable the CPU Interrupt that is linked to the timer */ up_enable_irq(priv->irq); @@ -1239,22 +1213,6 @@ struct esp32s2_tim_dev_s *esp32s2_tim_init(int timer) break; } #endif - -#ifdef CONFIG_ESP32S2_RT_TIMER - case SYSTIMER_COMP0: - { - tim = &g_esp32s2_tim4_priv; - - /* Enable Systimer peripheral clock and reset it */ - - modifyreg32(SYSTEM_PERIP_CLK_EN0_REG, 0, SYSTEM_SYSTIMER_CLK_EN); - modifyreg32(SYSTEM_PERIP_RST_EN0_REG, 0, SYSTEM_SYSTIMER_RST); - modifyreg32(SYSTEM_PERIP_RST_EN0_REG, SYSTEM_SYSTIMER_RST, 0); - modifyreg32(SYSTIMER_CONF_REG, 0, SYSTIMER_CLK_EN - | SYSTIMER_CLK_FO); - break; - } -#endif } if (tim->gid == GROUP0) diff --git a/arch/xtensa/src/esp32s2/esp32s2_tim_lowerhalf.c b/arch/xtensa/src/esp32s2/esp32s2_tim_lowerhalf.c index 88afe5f2afed5..0dc78b5b39f2e 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_tim_lowerhalf.c +++ b/arch/xtensa/src/esp32s2/esp32s2_tim_lowerhalf.c @@ -39,7 +39,7 @@ #include "hardware/esp32s2_soc.h" #include "esp32s2_tim.h" -#include "esp32s2_clockconfig.h" +#include "esp_clk.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/xtensa/src/esp32s2/esp32s2_timerisr.c b/arch/xtensa/src/esp32s2/esp32s2_timerisr.c index 9220364c225d2..4d9b27ca3cdf2 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_timerisr.c +++ b/arch/xtensa/src/esp32s2/esp32s2_timerisr.c @@ -35,6 +35,7 @@ #include "clock/clock.h" #include "xtensa.h" #include "xtensa_counter.h" +#include "esp_irq.h" /**************************************************************************** * Private data @@ -65,7 +66,7 @@ static uint32_t g_tick_divisor; * ****************************************************************************/ -static int esp32s2_timerisr(int irq, uint32_t *regs, void *arg) +static int esp32s2_timerisr(int irq, void *regs, void *arg) { uint32_t divisor; uint32_t compare; @@ -131,9 +132,14 @@ void up_timer_initialize(void) /* Attach the timer interrupt */ - irq_attach(XTENSA_IRQ_TIMER0, (xcpt_t)esp32s2_timerisr, NULL); + esp_setup_irq(ETS_INTERNAL_TIMER0_INTR_SOURCE, + ESP_IRQ_PRIORITY_1, + 0, + esp32s2_timerisr, + NULL); /* Enable the timer 0 CPU interrupt. */ - up_enable_irq(XTENSA_IRQ_TIMER0); + up_enable_irq(ETS_INTERNAL_TIMER0_INTR_SOURCE + + ETS_INTERNAL_INTR_SOURCE_OFF); } diff --git a/arch/xtensa/src/esp32s2/esp32s2_touch.c b/arch/xtensa/src/esp32s2/esp32s2_touch.c index dfe93e75c7f1e..8ddbae18f03c8 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_touch.c +++ b/arch/xtensa/src/esp32s2/esp32s2_touch.c @@ -36,8 +36,9 @@ #include "xtensa.h" -#include "esp32s2_gpio.h" -#include "esp32s2_irq.h" +#include "espressif/esp_gpio.h" +#include "espressif/esp_irq.h" +#include "espressif/esp_hr_timer.h" #include "esp32s2_touch.h" #include "esp32s2_touch_lowerhalf.h" @@ -64,6 +65,14 @@ struct touch_config_meas_mode_s enum touch_tie_opt_e tie_opt; }; +#ifdef CONFIG_ESP32S2_TOUCH_IRQ +struct touchirq_handler_s +{ + xcpt_t handler; + void *arg; +}; +#endif + /**************************************************************************** * Private Function Prototypes ****************************************************************************/ @@ -92,8 +101,10 @@ static uint16_t touch_pad_isr_enabled; static enum touch_intr_mask_e touch_pad_isr_types; static int touch_last_irq = -1; static int (*touch_release_cb)(int, void *, void *); -static struct rt_timer_args_s irq_timer_args; -static struct rt_timer_s *irq_timer_handler; +static struct touchirq_handler_s + g_touchirq_handlers[ESP32S2_NIRQ_RTCIO_TOUCHPAD]; +static struct esp_hr_timer_args_s irq_timer_args; +static struct esp_hr_timer_s *irq_timer_handler = NULL; #endif /**************************************************************************** @@ -177,9 +188,9 @@ static int touch_interrupt(int irq, void *context, void *arg) touch_lh_intr_disable(touch_pad_isr_types); - rt_timer_start(irq_timer_handler, - CONFIG_ESP32S2_TOUCH_IRQ_INTERVAL_MS * USEC_PER_MSEC, - false); + esp_hr_timer_start_once(irq_timer_handler, + CONFIG_ESP32S2_TOUCH_IRQ_INTERVAL_MS * \ + USEC_PER_MSEC); /* Read and clear the touch interrupt status */ @@ -193,7 +204,14 @@ static int touch_interrupt(int irq, void *context, void *arg) { if ((touch_pad_isr_enabled >> pad_num) & 0x1) { - irq_dispatch(touch_last_irq, context); + if (pad_num >= 0 && pad_num < ESP32S2_NIRQ_RTCIO_TOUCHPAD && + g_touchirq_handlers[pad_num].handler != NULL) + { + g_touchirq_handlers[pad_num].handler( + touch_last_irq, + context, + g_touchirq_handlers[pad_num].arg); + } } } @@ -219,13 +237,25 @@ static int touch_interrupt(int irq, void *context, void *arg) #ifdef CONFIG_ESP32S2_TOUCH_IRQ static void touch_restore_irq(void *arg) { - if (touch_last_irq > 0 && touch_release_cb != NULL) + if (touch_last_irq >= ESP32S2_FIRST_RTCIOIRQ_TOUCHPAD && + touch_last_irq <= ESP32S2_LAST_RTCIOIRQ_TOUCHPAD) { - /* Call the button interrupt handler again so we can detect touch pad - * releases - */ + int bit = ESP32S2_IRQ2TOUCHPAD(touch_last_irq); + + if (bit >= 0 && bit < ESP32S2_NIRQ_RTCIO_TOUCHPAD && + g_touchirq_handlers[bit].handler != NULL) + { + /* Call the button interrupt handler again so we can detect touch + * pad releases. + */ - touch_release_cb(touch_last_irq, NULL, NULL); + g_touchirq_handlers[bit].handler(touch_last_irq, NULL, + g_touchirq_handlers[bit].arg); + } + else if (touch_release_cb != NULL) + { + touch_release_cb(touch_last_irq, NULL, NULL); + } } touch_lh_intr_enable(touch_pad_isr_types); @@ -314,7 +344,13 @@ static void touch_init(struct touch_config_s *config) #ifdef CONFIG_ESP32S2_TOUCH_IRQ irq_timer_args.arg = NULL; irq_timer_args.callback = touch_restore_irq; - rt_timer_create(&(irq_timer_args), &(irq_timer_handler)); + irq_timer_args.name = "touch_irq"; + irq_timer_args.skip_unhandled_events = false; + + if (esp_hr_timer_create(&irq_timer_args, &irq_timer_handler) != OK) + { + ierr("ERROR: esp_hr_timer_create(irq) failed\n"); + } touch_pad_isr_types = TOUCH_INTR_MASK_ACTIVE | TOUCH_INTR_MASK_INACTIVE | @@ -322,29 +358,29 @@ static void touch_init(struct touch_config_s *config) int ret = 0; - ret |= irq_attach(ESP32S2_IRQ_RTC_TOUCH_DONE, - touch_interrupt, - NULL); + ret |= esp32s2_rtcioirqattach(ESP32S2_IRQ_RTC_TOUCH_DONE, + touch_interrupt, + NULL); - ret |= irq_attach(ESP32S2_IRQ_RTC_TOUCH_ACTIVE, - touch_interrupt, - NULL); + ret |= esp32s2_rtcioirqattach(ESP32S2_IRQ_RTC_TOUCH_ACTIVE, + touch_interrupt, + NULL); - ret |= irq_attach(ESP32S2_IRQ_RTC_TOUCH_INACTIVE, - touch_interrupt, - NULL); + ret |= esp32s2_rtcioirqattach(ESP32S2_IRQ_RTC_TOUCH_INACTIVE, + touch_interrupt, + NULL); - ret |= irq_attach(ESP32S2_IRQ_RTC_TOUCH_SCAN_DONE, - touch_interrupt, - NULL); + ret |= esp32s2_rtcioirqattach(ESP32S2_IRQ_RTC_TOUCH_SCAN_DONE, + touch_interrupt, + NULL); - ret |= irq_attach(ESP32S2_IRQ_RTC_TOUCH_TIMEOUT, - touch_interrupt, - NULL); + ret |= esp32s2_rtcioirqattach(ESP32S2_IRQ_RTC_TOUCH_TIMEOUT, + touch_interrupt, + NULL); if (ret < 0) { - ierr("ERROR: irq_attach() failed.\n"); + ierr("ERROR: esp32s2_touchirqattach() failed.\n"); } #endif @@ -687,6 +723,84 @@ void esp32s2_touchirqdisable(int irq) } #endif +/**************************************************************************** + * Name: esp32s2_touchirqattach + * + * Description: + * Attach an interrupt handler to a specified touch pad IRQ. + * + * Input Parameters: + * irq - Touch pad IRQ number to attach the handler to + * handler - Interrupt handler function + * arg - Argument to pass to the handler + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32S2_TOUCH_IRQ +int esp32s2_touchirqattach(int irq, xcpt_t handler, void *arg) +{ + int bit; + + DEBUGASSERT(irq >= ESP32S2_FIRST_RTCIOIRQ_TOUCHPAD && + irq <= ESP32S2_LAST_RTCIOIRQ_TOUCHPAD); + + bit = ESP32S2_IRQ2TOUCHPAD(irq); + if (bit < 0 || bit >= ESP32S2_NIRQ_RTCIO_TOUCHPAD) + { + return -EINVAL; + } + + g_touchirq_handlers[bit].handler = handler; + g_touchirq_handlers[bit].arg = arg; + + return OK; +} + +/**************************************************************************** + * Name: esp32s2_touchirqdetach + * + * Description: + * Detach the interrupt handler for the specified touch pad IRQ and + * disable the interrupt. + * + * Input Parameters: + * irq - Touch pad IRQ number to detach. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +int esp32s2_touchirqdetach(int irq) +{ + int bit; + + DEBUGASSERT(irq >= ESP32S2_FIRST_RTCIOIRQ_TOUCHPAD && + irq <= ESP32S2_LAST_RTCIOIRQ_TOUCHPAD); + + bit = ESP32S2_IRQ2TOUCHPAD(irq); + if (bit < 0 || bit >= ESP32S2_NIRQ_RTCIO_TOUCHPAD) + { + return -EINVAL; + } + + touch_lh_intr_disable(touch_pad_isr_types); + + g_touchirq_handlers[bit].handler = NULL; + g_touchirq_handlers[bit].arg = NULL; + touch_pad_isr_enabled &= (~(UINT32_C(1) << bit)); + + touch_lh_intr_enable(touch_pad_isr_types); + + return OK; +} +#endif + /**************************************************************************** * Name: esp32s2_touchregisterreleasecb * @@ -701,9 +815,11 @@ void esp32s2_touchirqdisable(int irq) * ****************************************************************************/ +#ifdef CONFIG_ESP32S2_TOUCH_IRQ void esp32s2_touchregisterreleasecb(int (*func)(int, void *, void *)) { DEBUGASSERT(func != NULL); touch_release_cb = func; } +#endif diff --git a/arch/xtensa/src/esp32s2/esp32s2_touch.h b/arch/xtensa/src/esp32s2/esp32s2_touch.h index f843e94069fa2..687913a6decfd 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_touch.h +++ b/arch/xtensa/src/esp32s2/esp32s2_touch.h @@ -26,6 +26,7 @@ ****************************************************************************/ #include +#include #include #include #include @@ -244,6 +245,51 @@ void esp32s2_touchirqdisable(int irq); # define esp32s2_touchirqdisable(irq) #endif +/**************************************************************************** + * Name: esp32s2_touchirqattach + * + * Description: + * Attach an interrupt handler to a specified touch pad IRQ. + * + * Input Parameters: + * irq - Touch pad IRQ number to attach the handler to + * handler - Interrupt handler function + * arg - Argument to pass to the handler + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32S2_TOUCH_IRQ +int esp32s2_touchirqattach(int irq, xcpt_t handler, void *arg); +#else +# define esp32s2_touchirqattach(irq, handler, arg) (-EINVAL) +#endif + +/**************************************************************************** + * Name: esp32s2_touchirqdetach + * + * Description: + * Detach the interrupt handler for the specified touch pad IRQ and + * disable the interrupt. + * + * Input Parameters: + * irq - Touch pad IRQ number to detach. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32S2_TOUCH_IRQ +int esp32s2_touchirqdetach(int irq); +#else +# define esp32s2_touchirqdetach(irq) (-EINVAL) +#endif + /**************************************************************************** * Name: esp32s2_touchregisterreleasecb * diff --git a/arch/xtensa/src/esp32s2/esp32s2_touch_lowerhalf.h b/arch/xtensa/src/esp32s2/esp32s2_touch_lowerhalf.h index 024bb2cea8bda..9fd001fc9d07b 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_touch_lowerhalf.h +++ b/arch/xtensa/src/esp32s2/esp32s2_touch_lowerhalf.h @@ -33,11 +33,10 @@ #include "xtensa.h" #include "hardware/esp32s2_rtc_io.h" -#include "hardware/esp32s2_rtccntl.h" +#include "soc/rtc_cntl_reg.h" #include "hardware/esp32s2_touch.h" #include "hardware/esp32s2_sens.h" -#include "esp32s2_rt_timer.h" #include "esp32s2_rtc_gpio.h" /**************************************************************************** @@ -990,35 +989,35 @@ static inline void touch_lh_intr_enable(enum touch_intr_mask_e int_mask) { if (int_mask & TOUCH_INTR_MASK_DONE) { - REG_SET_FIELD(RTC_CNTL_INT_ENA_RTC_REG, + REG_SET_FIELD(RTC_CNTL_INT_ENA_REG, RTC_CNTL_TOUCH_DONE_INT_ENA, true); } if (int_mask & TOUCH_INTR_MASK_ACTIVE) { - REG_SET_FIELD(RTC_CNTL_INT_ENA_RTC_REG, + REG_SET_FIELD(RTC_CNTL_INT_ENA_REG, RTC_CNTL_TOUCH_ACTIVE_INT_ENA, true); } if (int_mask & TOUCH_INTR_MASK_INACTIVE) { - REG_SET_FIELD(RTC_CNTL_INT_ENA_RTC_REG, + REG_SET_FIELD(RTC_CNTL_INT_ENA_REG, RTC_CNTL_TOUCH_INACTIVE_INT_ENA, true); } if (int_mask & TOUCH_INTR_MASK_SCAN_DONE) { - REG_SET_FIELD(RTC_CNTL_INT_ENA_RTC_REG, + REG_SET_FIELD(RTC_CNTL_INT_ENA_REG, RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA, true); } if (int_mask & TOUCH_INTR_MASK_TIMEOUT) { - REG_SET_FIELD(RTC_CNTL_INT_ENA_RTC_REG, + REG_SET_FIELD(RTC_CNTL_INT_ENA_REG, RTC_CNTL_TOUCH_TIMEOUT_INT_ENA, true); } @@ -1042,35 +1041,35 @@ static inline void touch_lh_intr_disable(enum touch_intr_mask_e int_mask) { if (int_mask & TOUCH_INTR_MASK_DONE) { - REG_SET_FIELD(RTC_CNTL_INT_ENA_RTC_REG, + REG_SET_FIELD(RTC_CNTL_INT_ENA_REG, RTC_CNTL_TOUCH_DONE_INT_ENA, false); } if (int_mask & TOUCH_INTR_MASK_ACTIVE) { - REG_SET_FIELD(RTC_CNTL_INT_ENA_RTC_REG, + REG_SET_FIELD(RTC_CNTL_INT_ENA_REG, RTC_CNTL_TOUCH_ACTIVE_INT_ENA, false); } if (int_mask & TOUCH_INTR_MASK_INACTIVE) { - REG_SET_FIELD(RTC_CNTL_INT_ENA_RTC_REG, + REG_SET_FIELD(RTC_CNTL_INT_ENA_REG, RTC_CNTL_TOUCH_INACTIVE_INT_ENA, false); } if (int_mask & TOUCH_INTR_MASK_SCAN_DONE) { - REG_SET_FIELD(RTC_CNTL_INT_ENA_RTC_REG, + REG_SET_FIELD(RTC_CNTL_INT_ENA_REG, RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA, false); } if (int_mask & TOUCH_INTR_MASK_TIMEOUT) { - REG_SET_FIELD(RTC_CNTL_INT_ENA_RTC_REG, + REG_SET_FIELD(RTC_CNTL_INT_ENA_REG, RTC_CNTL_TOUCH_TIMEOUT_INT_ENA, false); } @@ -1094,35 +1093,35 @@ static inline void touch_lh_intr_clear(enum touch_intr_mask_e int_mask) { if (int_mask & TOUCH_INTR_MASK_DONE) { - REG_SET_FIELD(RTC_CNTL_INT_CLR_RTC_REG, + REG_SET_FIELD(RTC_CNTL_INT_CLR_REG, RTC_CNTL_TOUCH_DONE_INT_CLR, true); } if (int_mask & TOUCH_INTR_MASK_ACTIVE) { - REG_SET_FIELD(RTC_CNTL_INT_CLR_RTC_REG, + REG_SET_FIELD(RTC_CNTL_INT_CLR_REG, RTC_CNTL_TOUCH_ACTIVE_INT_CLR, true); } if (int_mask & TOUCH_INTR_MASK_INACTIVE) { - REG_SET_FIELD(RTC_CNTL_INT_CLR_RTC_REG, + REG_SET_FIELD(RTC_CNTL_INT_CLR_REG, RTC_CNTL_TOUCH_INACTIVE_INT_CLR, true); } if (int_mask & TOUCH_INTR_MASK_SCAN_DONE) { - REG_SET_FIELD(RTC_CNTL_INT_CLR_RTC_REG, + REG_SET_FIELD(RTC_CNTL_INT_CLR_REG, RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR, true); } if (int_mask & TOUCH_INTR_MASK_TIMEOUT) { - REG_SET_FIELD(RTC_CNTL_INT_CLR_RTC_REG, + REG_SET_FIELD(RTC_CNTL_INT_CLR_REG, RTC_CNTL_TOUCH_TIMEOUT_INT_CLR, true); } @@ -1144,7 +1143,7 @@ static inline void touch_lh_intr_clear(enum touch_intr_mask_e int_mask) static inline uint32_t touch_lh_read_intr_status_mask(void) { - uint32_t intr_st = getreg32(RTC_CNTL_INT_ST_RTC_REG); + uint32_t intr_st = getreg32(RTC_CNTL_INT_ST_REG); uint32_t intr_msk = 0; if (intr_st & RTC_CNTL_TOUCH_DONE_INT_ST_M) @@ -1526,19 +1525,19 @@ static inline void touch_lh_filter_set_noise_thres(uint32_t noise_thr) /* config2 in IDF */ REG_SET_FIELD(RTC_CNTL_TOUCH_FILTER_CTRL_REG, - RTC_CNTL_TOUCH_NEG_NOISE_THRES, + RTC_CNTL_TOUCH_CONFIG2, noise_thr); /* config1 in IDF */ REG_SET_FIELD(RTC_CNTL_TOUCH_FILTER_CTRL_REG, - RTC_CNTL_TOUCH_NEG_NOISE_LIMIT, + RTC_CNTL_TOUCH_CONFIG1, 0xf); /* config3 in IDF */ REG_SET_FIELD(RTC_CNTL_TOUCH_FILTER_CTRL_REG, - RTC_CNTL_TOUCH_HYSTERESIS, + RTC_CNTL_TOUCH_CONFIG3, 2); } diff --git a/arch/xtensa/src/esp32s2/esp32s2_twai.c b/arch/xtensa/src/esp32s2/esp32s2_twai.c index eab1bfd7bec12..19e3330a43cd2 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_twai.c +++ b/arch/xtensa/src/esp32s2/esp32s2_twai.c @@ -40,10 +40,10 @@ #include "xtensa.h" -#include "esp32s2_gpio.h" +#include "espressif/esp_gpio.h" #include "esp32s2_twai.h" -#include "esp32s2_irq.h" -#include "esp32s2_clockconfig.h" +#include "espressif/esp_irq.h" +#include "esp_clk.h" #include "hardware/esp32s2_system.h" #include "hardware/esp32s2_gpio_sigmap.h" @@ -467,9 +467,10 @@ static int esp32s2twai_setup(struct can_dev_s *dev) up_disable_irq(priv->irq); } - priv->cpuint = esp32s2_setup_irq(priv->periph, - ESP32S2_INT_PRIO_DEF, - ESP32S2_CPUINT_LEVEL); + priv->cpuint = esp_setup_irq(priv->periph, + ESP32S2_INT_PRIO_DEF, + ESP_IRQ_TRIGGER_LEVEL, + esp32s2twai_interrupt, dev); if (priv->cpuint < 0) { /* Failed to allocate a CPU interrupt of this type. */ @@ -480,18 +481,6 @@ static int esp32s2twai_setup(struct can_dev_s *dev) return ret; } - ret = irq_attach(priv->irq, esp32s2twai_interrupt, dev); - if (ret != OK) - { - /* Failed to attach IRQ, so CPU interrupt must be freed. */ - - esp32s2_teardown_irq(priv->periph, priv->cpuint); - priv->cpuint = -ENOMEM; - leave_critical_section(flags); - - return ret; - } - /* Enable the CPU interrupt that is linked to the TWAI device. */ up_enable_irq(priv->irq); @@ -530,13 +519,9 @@ static void esp32s2twai_shutdown(struct can_dev_s *dev) up_disable_irq(priv->irq); - /* Dissociate the IRQ from the ISR */ - - irq_detach(priv->irq); - /* Free cpu interrupt that is attached to this peripheral */ - esp32s2_teardown_irq(priv->periph, priv->cpuint); + esp_teardown_irq(priv->periph, priv->cpuint); priv->cpuint = -ENOMEM; } } @@ -1243,11 +1228,11 @@ struct can_dev_s *esp32s2_twaiinitialize(void) /* Configure CAN GPIO pins */ - esp32s2_configgpio(CONFIG_ESP32S2_TWAI_TXPIN, OUTPUT_FUNCTION_2); - esp32s2_gpio_matrix_out(CONFIG_ESP32S2_TWAI_TXPIN, TWAI_TX_IDX, 0, 0); + esp_configgpio(CONFIG_ESP32S2_TWAI_TXPIN, OUTPUT_FUNCTION_2); + esp_gpio_matrix_out(CONFIG_ESP32S2_TWAI_TXPIN, TWAI_TX_IDX, 0, 0); - esp32s2_configgpio(CONFIG_ESP32S2_TWAI_RXPIN, INPUT_FUNCTION_2); - esp32s2_gpio_matrix_in(CONFIG_ESP32S2_TWAI_RXPIN, TWAI_RX_IDX, 0); + esp_configgpio(CONFIG_ESP32S2_TWAI_RXPIN, INPUT_FUNCTION_2); + esp_gpio_matrix_in(CONFIG_ESP32S2_TWAI_RXPIN, TWAI_RX_IDX, 0); leave_critical_section(flags); #endif diff --git a/arch/xtensa/src/esp32s2/esp32s2_wdt.c b/arch/xtensa/src/esp32s2/esp32s2_wdt.c index 7420a762c461b..7e6ff827d37c3 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_wdt.c +++ b/arch/xtensa/src/esp32s2/esp32s2_wdt.c @@ -30,14 +30,15 @@ #include #include "xtensa.h" -#include "esp32s2_irq.h" +#include "espressif/esp_irq.h" #include "esp32s2_rtc_gpio.h" -#include "esp32s2_rtc.h" -#include "esp32s2_wdt.h" -#include "hardware/esp32s2_efuse.h" -#include "hardware/esp32s2_rtccntl.h" +#include "soc/efuse_reg.h" +#include "soc/rtc_cntl_reg.h" +#include "hal/rwdt_ll.h" #include "hardware/esp32s2_tim.h" +#include "esp32s2_wdt.h" +#include "soc/rtc.h" #include "soc/periph_defs.h" #include "esp_private/periph_ctrl.h" @@ -45,7 +46,31 @@ * Pre-processor Definitions ****************************************************************************/ -/* Helpers for converting from Q13.19 fixed-point format to float */ +/* Offset relative to each watchdog timer instance memory base */ + +#define RWDT_CONFIG0_OFFSET 0x0094 +#define XTWDT_CONFIG0_OFFSET 0x0060 + +/* RWDT */ + +#define RWDT_STAGE0_TIMEOUT_OFFSET 0x0098 +#define RWDT_STAGE1_TIMEOUT_OFFSET 0x009c +#define RWDT_STAGE2_TIMEOUT_OFFSET 0x00a0 +#define RWDT_STAGE3_TIMEOUT_OFFSET 0x00a4 +#define RWDT_FEED_OFFSET 0x00a8 +#define RWDT_WP_REG 0x00ac +#define RWDT_INT_ENA_REG_OFFSET 0x0040 +#define RWDT_INT_CLR_REG_OFFSET 0x004c + +/* XTWDT */ + +#define XTWDT_TIMEOUT_OFFSET 0x00f4 +#define XTWDT_CLK_PRESCALE_OFFSET 0x00f0 +#define XTWDT_INT_ENA_REG_OFFSET 0x0040 + +/* Number of cycles for RTC_SLOW_CLK calibration */ + +#define SLOW_CLK_CAL_CYCLES 1024 #define N 19 #define Q_TO_FLOAT(x) ((float)x/(float)(1<irq == ESP32S2_IRQ_RTC_XTAL32K_DEAD) { esp32s2_rtcioirqdisable(wdt->irq); - irq_detach(wdt->irq); + esp32s2_rtcioirqdetach(wdt->irq); } else #endif @@ -773,8 +793,7 @@ static int32_t wdt_setisr(struct esp32s2_wdt_dev_s *dev, xcpt_t handler, */ up_disable_irq(wdt->irq); - esp32s2_teardown_irq(wdt->periph, wdt->cpuint); - irq_detach(wdt->irq); + esp_teardown_irq(wdt->periph, wdt->cpuint); } } @@ -791,7 +810,9 @@ static int32_t wdt_setisr(struct esp32s2_wdt_dev_s *dev, xcpt_t handler, if (wdt->irq == ESP32S2_IRQ_RTC_WDT || wdt->irq == ESP32S2_IRQ_RTC_XTAL32K_DEAD) { - ret = irq_attach(wdt->irq, handler, arg); + /* RTC interrupts use special RTC IRQ handling */ + + ret = esp32s2_rtcioirqattach(wdt->irq, handler, arg); if (ret != OK) { @@ -805,8 +826,9 @@ static int32_t wdt_setisr(struct esp32s2_wdt_dev_s *dev, xcpt_t handler, else #endif { - wdt->cpuint = esp32s2_setup_irq(wdt->periph, 1, - ESP32S2_CPUINT_LEVEL); + wdt->cpuint = esp_setup_irq(wdt->periph, 1, + ESP_IRQ_TRIGGER_LEVEL, + handler, arg); if (wdt->cpuint < 0) { wderr("ERROR: No CPU Interrupt available"); @@ -814,16 +836,6 @@ static int32_t wdt_setisr(struct esp32s2_wdt_dev_s *dev, xcpt_t handler, goto errout; } - /* Associate an IRQ Number (from the WDT) to an ISR */ - - ret = irq_attach(wdt->irq, handler, arg); - if (ret != OK) - { - esp32s2_teardown_irq(wdt->periph, wdt->cpuint); - wderr("ERROR: Failed to associate an IRQ Number"); - goto errout; - } - /* Enable the CPU Interrupt that is linked to the WDT */ up_enable_irq(wdt->irq); diff --git a/arch/xtensa/src/esp32s2/esp32s2_wdt.h b/arch/xtensa/src/esp32s2/esp32s2_wdt.h index c9d5b1da2bf5c..f3a0fe92b17b8 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_wdt.h +++ b/arch/xtensa/src/esp32s2/esp32s2_wdt.h @@ -30,6 +30,10 @@ #include #include +#include + +#include "esp32s2_wdt_lowerhalf.h" +#include "esp_irq.h" /**************************************************************************** * Pre-processor Definitions @@ -75,16 +79,6 @@ * Public Types ****************************************************************************/ -/* Instances of Watchdog Timer */ - -enum esp32s2_wdt_inst_e -{ - ESP32S2_WDT_MWDT0 = 0, /* Main System Watchdog Timer (MWDT) of Timer Group 0 */ - ESP32S2_WDT_MWDT1, /* Main System Watchdog Timer (MWDT) of Timer Group 1 */ - ESP32S2_WDT_RWDT, /* RTC Watchdog Timer (RWDT) */ - ESP32S2_WDT_XTWDT /* XTAL32K Watchdog Timer (XTWDT) */ -}; - /* Stages of a Watchdog Timer. A WDT has 4 stages. */ enum esp32s2_wdt_stage_e @@ -115,6 +109,15 @@ enum esp32s2_wdt_stage_action_e */ }; +/* Type of the WDT Peripheral */ + +enum wdt_peripheral_e +{ + RTC, + TIMER, + XTAL32K, +}; + /* ESP32-S2 WDT device */ struct esp32s2_wdt_dev_s @@ -150,7 +153,8 @@ struct esp32s2_wdt_ops_s /* WDT interrupts */ - int32_t (*setisr)(struct esp32s2_wdt_dev_s *dev, xcpt_t handler, + int32_t (*setisr)(struct esp32s2_wdt_dev_s *dev, + xcpt_t handler, void *arg); void (*enableint)(struct esp32s2_wdt_dev_s *dev); void (*disableint)(struct esp32s2_wdt_dev_s *dev); diff --git a/arch/xtensa/src/esp32s2/esp32s2_wdt_lowerhalf.c b/arch/xtensa/src/esp32s2/esp32s2_wdt_lowerhalf.c index 31dde6059dcb0..595b9b11956e1 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_wdt_lowerhalf.c +++ b/arch/xtensa/src/esp32s2/esp32s2_wdt_lowerhalf.c @@ -37,10 +37,13 @@ #include "xtensa.h" #include "esp32s2_wdt.h" -#include "esp32s2_rtc.h" + #include "esp32s2_wdt_lowerhalf.h" #include "hardware/esp32s2_soc.h" +#include "soc/periph_defs.h" +#include "esp_private/periph_ctrl.h" + /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ @@ -91,13 +94,6 @@ * Private Types ****************************************************************************/ -enum wdt_peripheral_e -{ - RTC, - TIMER, - XTAL32K, -}; - /* This structure provides the private representation of the "lower-half" * driver state structure. This structure must be cast-compatible with the * well-known watchdog_lowerhalf_s structure. @@ -706,6 +702,8 @@ static int wdt_handler(int irq, void *context, void *arg) { struct esp32s2_wdt_lowerhalf_s *priv = (struct esp32s2_wdt_lowerhalf_s *)arg; + struct esp32s2_wdt_priv_s *wdt = + (struct esp32s2_wdt_priv_s *)priv->wdt; /* Run the user callback */ diff --git a/arch/xtensa/src/esp32s2/esp32s2_wdt_lowerhalf.h b/arch/xtensa/src/esp32s2/esp32s2_wdt_lowerhalf.h index a3bbd256ee486..cbc19de269864 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_wdt_lowerhalf.h +++ b/arch/xtensa/src/esp32s2/esp32s2_wdt_lowerhalf.h @@ -25,12 +25,20 @@ * Included Files ****************************************************************************/ -#include "esp32s2_wdt.h" - /**************************************************************************** * Public Types ****************************************************************************/ +/* Instances of Watchdog Timer */ + +enum esp32s2_wdt_inst_e +{ + ESP32S2_WDT_MWDT0 = 0, /* Main System Watchdog Timer (MWDT) of Timer Group 0 */ + ESP32S2_WDT_MWDT1, /* Main System Watchdog Timer (MWDT) of Timer Group 1 */ + ESP32S2_WDT_RWDT, /* RTC Watchdog Timer (RWDT) */ + ESP32S2_WDT_XTWDT /* XTAL32K Watchdog Timer (XTWDT) */ +}; + /**************************************************************************** * Public Function Prototypes ****************************************************************************/ diff --git a/arch/xtensa/src/esp32s2/esp32s2_wifi_adapter.c b/arch/xtensa/src/esp32s2/esp32s2_wifi_adapter.c index b00f7115d1b58..46ba7d4fde86f 100644 --- a/arch/xtensa/src/esp32s2/esp32s2_wifi_adapter.c +++ b/arch/xtensa/src/esp32s2/esp32s2_wifi_adapter.c @@ -43,11 +43,15 @@ #include "xtensa.h" #include "esp_attr.h" +#include "esp_irq.h" +#include "esp_cpu.h" #include "hardware/esp32s2_system.h" -#include "hardware/esp32s2_rtccntl.h" +#include "soc/rtc_cntl_reg.h" +#include "rom/rtc.h" #include "espressif/esp_wireless.h" #include "espressif/esp_wifi_utils.h" +#include "platform/os.h" #include "periph_ctrl.h" @@ -64,29 +68,31 @@ * Private Types ****************************************************************************/ -/* Wi-Fi interrupt adapter private data */ +/* Wi-Fi time private data */ -struct irq_adpt +struct time_adpt { - void (*func)(void *arg); /* Interrupt callback function */ - void *arg; /* Interrupt private data */ + time_t sec; /* Second value */ + suseconds_t usec; /* Micro second value */ }; -/* Wi-Fi message queue private data */ +typedef struct shared_vector_desc_t shared_vector_desc_t; +typedef struct vector_desc_t vector_desc_t; -struct mq_adpt +typedef struct intr_handle_data_t { - struct file mq; /* Message queue handle */ - uint32_t msgsize; /* Message size */ - char name[16]; /* Message queue name */ -}; - -/* Wi-Fi time private data */ + vector_desc_t *vector_desc; + shared_vector_desc_t *shared_vector_desc; +} intr_handle_data_t; -struct time_adpt +struct vector_desc_t { - time_t sec; /* Second value */ - suseconds_t usec; /* Micro second value */ + int flags: 16; + unsigned int cpu: 1; + unsigned int intno: 5; + int source: 16; + shared_vector_desc_t *shared_vec_info; + vector_desc_t *next; }; /**************************************************************************** @@ -94,12 +100,10 @@ struct time_adpt ****************************************************************************/ static bool wifi_env_is_chip(void); -static void wifi_set_intr(int32_t cpu_no, uint32_t intr_source, +static void set_intr_wrapper(int32_t cpu_no, uint32_t intr_source, uint32_t intr_num, int32_t intr_prio); -static void wifi_clear_intr(uint32_t intr_source, uint32_t intr_num); -static void esp_set_isr(int32_t n, void *f, void *arg); -static void esp32s2_ints_on(uint32_t mask); -static void esp32s2_ints_off(uint32_t mask); +static void clear_intr_wrapper(uint32_t intr_source, uint32_t intr_num); +static void set_isr_wrapper(int32_t n, void *f, void *arg); static bool wifi_is_from_isr(void); static void *esp_spin_lock_create(void); static void esp_spin_lock_delete(void *lock); @@ -257,11 +261,11 @@ wifi_osi_funcs_t g_wifi_osi_funcs = { ._version = ESP_WIFI_OS_ADAPTER_VERSION, ._env_is_chip = wifi_env_is_chip, - ._set_intr = wifi_set_intr, - ._clear_intr = wifi_clear_intr, - ._set_isr = esp_set_isr, - ._ints_on = esp32s2_ints_on, - ._ints_off = esp32s2_ints_off, + ._set_intr = set_intr_wrapper, + ._clear_intr = clear_intr_wrapper, + ._set_isr = set_isr_wrapper, + ._ints_on = esp_cpu_intr_enable, + ._ints_off = esp_cpu_intr_disable, ._is_from_isr = wifi_is_from_isr, ._spin_lock_create = esp_spin_lock_create, ._spin_lock_delete = esp_spin_lock_delete, @@ -386,29 +390,6 @@ wifi_osi_funcs_t g_wifi_osi_funcs = * Private Functions ****************************************************************************/ -/**************************************************************************** - * Name: esp_int_adpt_cb - * - * Description: - * Wi-Fi interrupt adapter callback function - * - * Input Parameters: - * arg - interrupt adapter private data - * - * Returned Value: - * 0 on success - * - ****************************************************************************/ - -static int esp_int_adpt_cb(int irq, void *context, void *arg) -{ - struct irq_adpt *adapter = (struct irq_adpt *)arg; - - adapter->func(adapter->arg); - - return 0; -} - /**************************************************************************** * Name: esp_thread_semphr_free * @@ -455,7 +436,7 @@ static void esp_update_time(struct timespec *timespec, uint32_t ticks) } /**************************************************************************** - * Name: esp_set_isr + * Name: set_isr_wrapper * * Description: * Register interrupt function @@ -470,98 +451,9 @@ static void esp_update_time(struct timespec *timespec, uint32_t ticks) * ****************************************************************************/ -static void esp_set_isr(int32_t n, void *f, void *arg) -{ - int ret; - uint32_t tmp; - struct irq_adpt *adapter; - int irq = n + XTENSA_IRQ_FIRSTPERIPH; - - wlinfo("n=%ld f=%p arg=%p", n, f, arg); - - if (g_irqvector[irq].handler && - g_irqvector[irq].handler != irq_unexpected_isr) - { - wlinfo("irq=%d has been set handler=%p\n", irq, - g_irqvector[irq].handler); - return; - } - - tmp = sizeof(struct irq_adpt); - adapter = kmm_malloc(tmp); - if (!adapter) - { - wlerr("Failed to alloc %" PRIu32 " memory\n", tmp); - PANIC(); - return; - } - - adapter->func = f; - adapter->arg = arg; - - ret = irq_attach(ESP32S2_IRQ_MAC, esp_int_adpt_cb, adapter); - if (ret) - { - wlerr("Failed to attach IRQ %d\n", irq); - PANIC(); - return; - } - - ret = irq_attach(ESP32S2_IRQ_PWR, esp_int_adpt_cb, adapter); - if (ret) - { - wlerr("Failed to attach IRQ %d\n", irq); - PANIC(); - return; - } -} - -/**************************************************************************** - * Name: esp32s2_ints_on - * - * Description: - * Enable Wi-Fi interrupt - * - * Input Parameters: - * mask - No mean - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void esp32s2_ints_on(uint32_t mask) -{ - int irq = __builtin_ffs(mask) - 1; - - wlinfo("INFO mask=%08lx irq=%d\n", mask, irq); - - up_enable_irq(ESP32S2_IRQ_MAC); - up_enable_irq(ESP32S2_IRQ_PWR); -} - -/**************************************************************************** - * Name: esp32s2_ints_off - * - * Description: - * Disable Wi-Fi interrupt - * - * Input Parameters: - * mask - No mean - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void esp32s2_ints_off(uint32_t mask) +static void set_isr_wrapper(int32_t n, void *f, void *arg) { - uint32_t irq = __builtin_ffs(mask) - 1; - - wlinfo("INFO mask=%08" PRIu32 " irq=%" PRIu32 "\n", mask, irq); - - up_disable_irq(ESP32S2_IRQ_MAC); - up_disable_irq(ESP32S2_IRQ_PWR); + xt_set_interrupt_handler(n, (xt_handler)f, arg); } /**************************************************************************** @@ -1709,7 +1601,7 @@ static bool wifi_env_is_chip(void) } /**************************************************************************** - * Name: wifi_set_intr + * Name: set_intr_wrapper * * Description: * Do nothing @@ -1725,23 +1617,54 @@ static bool wifi_env_is_chip(void) * ****************************************************************************/ -static void wifi_set_intr(int32_t cpu_no, uint32_t intr_source, +static void set_intr_wrapper(int32_t cpu_no, uint32_t intr_source, uint32_t intr_num, int32_t intr_prio) { + intr_handle_t handle; + int irq = ESP_SOURCE2IRQ(intr_source); + wlinfo("cpu_no=%" PRId32 ", intr_source=%" PRIu32 ", intr_num=%" PRIu32 ", intr_prio=%" PRId32 "\n", cpu_no, intr_source, intr_num, intr_prio); + + esp_rom_route_intr_matrix(cpu_no, intr_source, intr_num); + + handle = kmm_calloc(1, sizeof(intr_handle_data_t)); + if (handle == NULL) + { + wlerr("Failed to kmm_calloc\n"); + return; + } + + handle->vector_desc = kmm_calloc(1, sizeof(vector_desc_t)); + if (handle->vector_desc == NULL) + { + wlerr("Failed to kmm_calloc\n"); + kmm_free(handle); + return; + } + + handle->vector_desc->intno = intr_num; + handle->vector_desc->cpu = cpu_no; + handle->vector_desc->source = intr_source; + handle->vector_desc->shared_vec_info = NULL; + handle->vector_desc->next = NULL; + handle->shared_vector_desc = NULL; + + /* Register the handle - it contains all needed information (cpuint, cpu) */ + + esp_set_handle(cpu_no, irq, handle); } /**************************************************************************** - * Name: wifi_clear_intr + * Name: clear_intr_wrapper * * Description: * Don't support * ****************************************************************************/ -static void IRAM_ATTR wifi_clear_intr(uint32_t intr_source, +static void IRAM_ATTR clear_intr_wrapper(uint32_t intr_source, uint32_t intr_num) { } @@ -2146,7 +2069,7 @@ static void wifi_clock_disable(void) int64_t esp32s2_timer_get_time(void) { - return (int64_t)rt_timer_time_us(); + return (int64_t)esp_hr_timer_time_us(); } /**************************************************************************** diff --git a/arch/xtensa/src/esp32s2/hal.mk b/arch/xtensa/src/esp32s2/hal.mk index 0018f3530b705..0d99c6589ee9f 100644 --- a/arch/xtensa/src/esp32s2/hal.mk +++ b/arch/xtensa/src/esp32s2/hal.mk @@ -30,19 +30,73 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_adc$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_adc$(DELIM)interface INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_adc$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_blockdev$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_common$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_event$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ana_conv$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ana_conv$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_clock$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_clock$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_dma$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_dma$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpio$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpio$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpspi$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpspi$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_i2c$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_i2c$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_i2s$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_i2s$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ledc$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ledc$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_mcpwm$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_mcpwm$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_mspi$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_mspi$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_parlio$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_parlio$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_pcnt$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_pcnt$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_pmu$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_pmu$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_rmt$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_rmt$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_rtc_timer$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_rtc_timer$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_security$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_security$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_timg$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_timg$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_twai$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_twai$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_touch_sens$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_touch_sens$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_uart$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_uart$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_usb$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_usb$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_wdt$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_wdt$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)dma$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_dma$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)etm$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include$(DELIM)esp_private INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include$(DELIM)soc +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include$(DELIM)soc$(DELIM)$(CHIP_SERIES) INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)ldo$(DELIM)include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi_timing_tuning$(DELIM)include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi_timing_tuning$(DELIM)tuning_scheme_impl$(DELIM)include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi_timing_tuning$(DELIM)port$(DELIM)$(CHIP_SERIES) +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi$(DELIM)mspi_intr$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi$(DELIM)mspi_timing_tuning$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi$(DELIM)mspi_timing_tuning$(DELIM)tuning_scheme_impl$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi$(DELIM)mspi_timing_tuning$(DELIM)port$(DELIM)$(CHIP_SERIES) INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)power_supply$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_mm$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)heap$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_pm +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_pm$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_security$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)$(CHIP_SERIES)$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES) @@ -50,6 +104,7 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)include$(DELIM)$(CHIP_SERIES) INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)include$(DELIM)$(CHIP_SERIES)$(DELIM)rom +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_security$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)include @@ -61,19 +116,20 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)$(CHIP_SERIES)$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)platform_port$(DELIM)include - INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)log_level$(DELIM)tag_log_level INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)log_level$(DELIM)tag_log_level$(DELIM)linked_list +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port$(DELIM)include$(DELIM)aes +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port$(DELIM)psa_driver$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)newlib -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)newlib$(DELIM)priv_include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)tf-psa-crypto$(DELIM)drivers$(DELIM)builtin$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)tf-psa-crypto$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)tf-psa-crypto$(DELIM)core +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_libc$(DELIM)priv_include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)register INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)xtensa$(DELIM)deprecated_include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)esp_driver_gpio$(DELIM)include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)include$(DELIM)mbedtls - INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)register @@ -81,15 +137,21 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)xtensa$(DELIM)$(CHIP_SERIES)$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)xtensa$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)include$(DELIM)spi_flash +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)include$(DELIM)esp_flash_chips +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)include$(DELIM)esp_private INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_app_format$(DELIM)include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)$(CHIP_SERIES)$(DELIM)include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)ulp$(DELIM)ulp_common INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)ulp$(DELIM)ulp_common$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)ulp$(DELIM)ulp_riscv$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)ulp$(DELIM)ulp_riscv$(DELIM)shared INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)ulp$(DELIM)ulp_riscv$(DELIM)shared$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_gpio$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)include$(DELIM)mbedtls +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)esp_libc$(DELIM)platform_include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_rmt$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_rmt$(DELIM)src # Linker scripts @@ -107,9 +169,6 @@ endif # Source files -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)esp_driver_gpio$(DELIM)src$(DELIM)rtc_io.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)esp_security$(DELIM)src$(DELIM)esp_crypto_lock.c - CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_adc$(DELIM)adc_cali.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_adc$(DELIM)$(CHIP_SERIES)$(DELIM)adc_cali_line_fitting.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)src$(DELIM)esp_efuse_fields.c @@ -117,25 +176,28 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efus CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)src$(DELIM)esp_efuse_api.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)src$(DELIM)esp_efuse_startup.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)src$(DELIM)efuse_controller$(DELIM)keys$(DELIM)with_key_purposes$(DELIM)esp_efuse_api_key.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)esp_efuse_rtc_calib.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)esp_efuse_rtc_table.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)esp_efuse_fields.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)esp_efuse_table.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)$(CHIP_SERIES)$(DELIM)esp_efuse_utility.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_app_format$(DELIM)esp_app_desc.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_common$(DELIM)src$(DELIM)esp_err_to_name.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi_timing_tuning$(DELIM)mspi_timing_tuning.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi$(DELIM)mspi_timing_tuning$(DELIM)mspi_timing_tuning.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)sleep_modes.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)sleep_uart.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)power_supply$(DELIM)brownout.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_mm$(DELIM)esp_mmu_map.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_mm$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)ext_mem_layout.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_mm$(DELIM)esp_cache.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_mm$(DELIM)esp_cache_utils.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_mm$(DELIM)esp_cache_msync.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)$(CHIP_SERIES)$(DELIM)phy_init_data.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_pm$(DELIM)pm_locks.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_pm$(DELIM)pm_impl.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)hal_utils.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)spi_flash_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)spi_flash_hal_iram.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)spi_flash_hal_gpspi.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)spi_flash_encrypt_hal_iram.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_mspi$(DELIM)spi_flash_encrypt_hal_iram.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_mspi$(DELIM)spi_flash_hal_gpspi.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_mspi$(DELIM)spi_flash_hal_iram.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_mspi$(DELIM)spi_flash_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)log_level$(DELIM)log_level.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)log_level$(DELIM)tag_log_level$(DELIM)tag_log_level.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)log_level$(DELIM)tag_log_level$(DELIM)linked_list$(DELIM)log_linked_list.c @@ -144,9 +206,11 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)noos$(DELIM)log_timestamp.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)os$(DELIM)log_write.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)os$(DELIM)util.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port$(DELIM)sha$(DELIM)core$(DELIM)esp_sha256.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_gpio$(DELIM)src$(DELIM)gpio.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_gpio$(DELIM)src$(DELIM)rtc_io.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)adc_share_hw_ctrl.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)clk_ctrl_os.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)esp_gpio_reserve.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)clk_utils.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)cpu.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)esp_clk.c @@ -165,13 +229,21 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)systimer.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)esp_clk_tree_common.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)regi2c_ctrl.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)rtc_module.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)sleep_event.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)sleep_gpio.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)sleep_modem.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_libc$(DELIM)src$(DELIM)port$(DELIM)esp_time_impl.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)src$(DELIM)phy_init.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)src$(DELIM)phy_common.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_sys.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_print.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_crc.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_serial_output.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_spiflash.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_efuse.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_gpio.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_regi2c_$(CHIP_SERIES).c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_wdt.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)esp_err.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)esp_system.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)startup.c @@ -179,49 +251,49 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)system_time.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)clk.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)system_internal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_timer$(DELIM)src$(DELIM)esp_timer_impl_common.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_timer$(DELIM)src$(DELIM)esp_timer_impl_systimer.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_timer$(DELIM)src$(DELIM)esp_timer.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_timer$(DELIM)src$(DELIM)esp_timer_init.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_timer$(DELIM)src$(DELIM)esp_timer_impl_systimer.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_timer$(DELIM)src$(DELIM)system_time.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)adc_hal_common.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)adc_oneshot_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)aes_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)$(CHIP_SERIES)$(DELIM)clk_tree_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_timer$(DELIM)src$(DELIM)esp_timer_impl_common.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ana_conv$(DELIM)adc_hal_common.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ana_conv$(DELIM)adc_oneshot_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_security$(DELIM)aes_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_clock$(DELIM)$(CHIP_SERIES)$(DELIM)clk_tree_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)$(CHIP_SERIES)$(DELIM)efuse_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)wdt_hal_iram.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_wdt$(DELIM)wdt_hal_iram.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)cache_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)mpu_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_security$(DELIM)mpu_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)mmu_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)i2c_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)brownout_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_i2c$(DELIM)i2c_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_pmu$(DELIM)brownout_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)efuse_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)gpio_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)ledc_hal_iram.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)ledc_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)pcnt_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)rmt_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)rtc_io_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)sdm_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)i2s_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)sha_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)timer_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)touch_sens_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpio$(DELIM)gpio_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ledc$(DELIM)ledc_hal_iram.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ledc$(DELIM)ledc_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_pcnt$(DELIM)pcnt_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_rmt$(DELIM)rmt_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpio$(DELIM)rtc_io_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpio$(DELIM)sdm_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_i2s$(DELIM)i2s_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_security$(DELIM)sha_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_timg$(DELIM)timer_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_touch_sens$(DELIM)touch_sens_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)systimer_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)uart_hal_iram.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)uart_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)newlib$(DELIM)src$(DELIM)port$(DELIM)esp_time_impl.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_uart$(DELIM)uart_hal_iram.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_uart$(DELIM)uart_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)dport_access_common.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)adc_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)dedic_gpio_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ana_conv$(DELIM)$(CHIP_SERIES)$(DELIM)adc_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpio$(DELIM)$(CHIP_SERIES)$(DELIM)dedic_gpio_periph.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)gpio_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)ledc_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)pcnt_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)rmt_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_io_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)sdm_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)i2c_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)i2s_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)temperature_sensor_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ledc$(DELIM)$(CHIP_SERIES)$(DELIM)ledc_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_pcnt$(DELIM)$(CHIP_SERIES)$(DELIM)pcnt_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_rmt$(DELIM)$(CHIP_SERIES)$(DELIM)rmt_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpio$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_io_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpio$(DELIM)$(CHIP_SERIES)$(DELIM)sdm_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_i2c$(DELIM)$(CHIP_SERIES)$(DELIM)i2c_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_i2s$(DELIM)$(CHIP_SERIES)$(DELIM)i2s_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ana_conv$(DELIM)$(CHIP_SERIES)$(DELIM)temperature_sensor_periph.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)spi_flash_wrap.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)spi_flash_os_func_noos.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)spi_flash_os_func_app.c @@ -247,6 +319,32 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)ulp$ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)ulp$(DELIM)ulp_riscv$(DELIM)ulp_riscv_lock.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)ulp$(DELIM)ulp_riscv$(DELIM)ulp_riscv_i2c.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)io_mux.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_rmt$(DELIM)src$(DELIM)rmt_common.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_rmt$(DELIM)src$(DELIM)rmt_encoder.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_rmt$(DELIM)src$(DELIM)rmt_encoder_bytes.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_rmt$(DELIM)src$(DELIM)rmt_encoder_copy.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_rmt$(DELIM)src$(DELIM)rmt_encoder_simple.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_rmt$(DELIM)src$(DELIM)rmt_rx.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_rmt$(DELIM)src$(DELIM)rmt_tx.c + +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)platform$(DELIM)os.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)heap_caps.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)newlib$(DELIM)newlib$(DELIM)libc$(DELIM)misc$(DELIM)init.c + +# Interrupt allocator +# NOTE: ESP-IDF's xtensa_intr_asm.S cannot be used because it conflicts with +# NuttX's Xtensa core macro definitions. Instead, esp_xtensa_intr.c provides +# NuttX-native implementations of xt_ints_on, xt_ints_off, and related functions. +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)intr_alloc.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)esp_cpu_intr.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)xtensa$(DELIM)xtensa_intr.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)interrupts.c + +# Security components (for WiFi/crypto support) + +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_security$(DELIM)src$(DELIM)esp_hmac.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_security$(DELIM)src$(DELIM)esp_crypto_periph_clk.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_security$(DELIM)src$(DELIM)esp_crypto_lock.c # Bootloader files CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)${CHIP_SERIES}$(DELIM)bootloader_soc.c @@ -265,17 +363,12 @@ ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y) CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)bootloader_flash$(DELIM)src$(DELIM)bootloader_flash_config_${CHIP_SERIES}.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)bootloader_flash$(DELIM)src$(DELIM)flash_qio_mode.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_clock_init.c - CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_clock_loader.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_efuse.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_mem.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_random.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)esp_image_format.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_sha.c - CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)${CHIP_SERIES}$(DELIM)uart_periph.c - CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_uart.c - CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_sys.c - CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_spiflash.c - CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_crc.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_uart$(DELIM)${CHIP_SERIES}$(DELIM)uart_periph.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_cache_esp32s2_esp32s3.c LDFLAGS += --wrap=bootloader_print_banner diff --git a/arch/xtensa/src/esp32s2/hardware/esp32s2_efuse.h b/arch/xtensa/src/esp32s2/hardware/esp32s2_efuse.h deleted file mode 100644 index b02af55ef291e..0000000000000 --- a/arch/xtensa/src/esp32s2/hardware/esp32s2_efuse.h +++ /dev/null @@ -1,3305 +0,0 @@ -/**************************************************************************** - * arch/xtensa/src/esp32s2/hardware/esp32s2_efuse.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_EFUSE_H -#define __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_EFUSE_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include "esp32s2_soc.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* EFUSE_PGM_DATA0_REG register - * Register 0 that stores data to be programmed. - */ - -#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x0) - -/* EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0; - * The content of the 0th 32-bit data to be programmed. - */ - -#define EFUSE_PGM_DATA_0 0xFFFFFFFF -#define EFUSE_PGM_DATA_0_M (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S) -#define EFUSE_PGM_DATA_0_V 0xFFFFFFFF -#define EFUSE_PGM_DATA_0_S 0 - -/* EFUSE_PGM_DATA1_REG register - * Register 1 that stores data to be programmed. - */ - -#define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x4) - -/* EFUSE_PGM_DATA_1 : R/W; bitpos: [31:0]; default: 0; - * The content of the 1th 32-bit data to be programmed. - */ - -#define EFUSE_PGM_DATA_1 0xFFFFFFFF -#define EFUSE_PGM_DATA_1_M (EFUSE_PGM_DATA_1_V << EFUSE_PGM_DATA_1_S) -#define EFUSE_PGM_DATA_1_V 0xFFFFFFFF -#define EFUSE_PGM_DATA_1_S 0 - -/* EFUSE_PGM_DATA2_REG register - * Register 2 that stores data to be programmed. - */ - -#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x8) - -/* EFUSE_PGM_DATA_2 : R/W; bitpos: [31:0]; default: 0; - * The content of the 2th 32-bit data to be programmed. - */ - -#define EFUSE_PGM_DATA_2 0xFFFFFFFF -#define EFUSE_PGM_DATA_2_M (EFUSE_PGM_DATA_2_V << EFUSE_PGM_DATA_2_S) -#define EFUSE_PGM_DATA_2_V 0xFFFFFFFF -#define EFUSE_PGM_DATA_2_S 0 - -/* EFUSE_PGM_DATA3_REG register - * Register 3 that stores data to be programmed. - */ - -#define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0xc) - -/* EFUSE_PGM_DATA_3 : R/W; bitpos: [31:0]; default: 0; - * The content of the 3th 32-bit data to be programmed. - */ - -#define EFUSE_PGM_DATA_3 0xFFFFFFFF -#define EFUSE_PGM_DATA_3_M (EFUSE_PGM_DATA_3_V << EFUSE_PGM_DATA_3_S) -#define EFUSE_PGM_DATA_3_V 0xFFFFFFFF -#define EFUSE_PGM_DATA_3_S 0 - -/* EFUSE_PGM_DATA4_REG register - * Register 4 that stores data to be programmed. - */ - -#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x10) - -/* EFUSE_PGM_DATA_4 : R/W; bitpos: [31:0]; default: 0; - * The content of the 4th 32-bit data to be programmed. - */ - -#define EFUSE_PGM_DATA_4 0xFFFFFFFF -#define EFUSE_PGM_DATA_4_M (EFUSE_PGM_DATA_4_V << EFUSE_PGM_DATA_4_S) -#define EFUSE_PGM_DATA_4_V 0xFFFFFFFF -#define EFUSE_PGM_DATA_4_S 0 - -/* EFUSE_PGM_DATA5_REG register - * Register 5 that stores data to be programmed. - */ - -#define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x14) - -/* EFUSE_PGM_DATA_5 : R/W; bitpos: [31:0]; default: 0; - * The content of the 5th 32-bit data to be programmed. - */ - -#define EFUSE_PGM_DATA_5 0xFFFFFFFF -#define EFUSE_PGM_DATA_5_M (EFUSE_PGM_DATA_5_V << EFUSE_PGM_DATA_5_S) -#define EFUSE_PGM_DATA_5_V 0xFFFFFFFF -#define EFUSE_PGM_DATA_5_S 0 - -/* EFUSE_PGM_DATA6_REG register - * Register 6 that stores data to be programmed. - */ - -#define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x18) - -/* EFUSE_PGM_DATA_6 : R/W; bitpos: [31:0]; default: 0; - * The content of the 6th 32-bit data to be programmed. - */ - -#define EFUSE_PGM_DATA_6 0xFFFFFFFF -#define EFUSE_PGM_DATA_6_M (EFUSE_PGM_DATA_6_V << EFUSE_PGM_DATA_6_S) -#define EFUSE_PGM_DATA_6_V 0xFFFFFFFF -#define EFUSE_PGM_DATA_6_S 0 - -/* EFUSE_PGM_DATA7_REG register - * Register 7 that stores data to be programmed. - */ - -#define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x1c) - -/* EFUSE_PGM_DATA_7 : R/W; bitpos: [31:0]; default: 0; - * The content of the 7th 32-bit data to be programmed. - */ - -#define EFUSE_PGM_DATA_7 0xFFFFFFFF -#define EFUSE_PGM_DATA_7_M (EFUSE_PGM_DATA_7_V << EFUSE_PGM_DATA_7_S) -#define EFUSE_PGM_DATA_7_V 0xFFFFFFFF -#define EFUSE_PGM_DATA_7_S 0 - -/* EFUSE_PGM_CHECK_VALUE0_REG register - * Register 0 that stores the RS code to be programmed. - */ - -#define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x20) - -/* EFUSE_PGM_RS_DATA_0 : R/W; bitpos: [31:0]; default: 0; - * The content of the 0th 32-bit RS code to be programmed. - */ - -#define EFUSE_PGM_RS_DATA_0 0xFFFFFFFF -#define EFUSE_PGM_RS_DATA_0_M (EFUSE_PGM_RS_DATA_0_V << EFUSE_PGM_RS_DATA_0_S) -#define EFUSE_PGM_RS_DATA_0_V 0xFFFFFFFF -#define EFUSE_PGM_RS_DATA_0_S 0 - -/* EFUSE_PGM_CHECK_VALUE1_REG register - * Register 1 that stores the RS code to be programmed. - */ - -#define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x24) - -/* EFUSE_PGM_RS_DATA_1 : R/W; bitpos: [31:0]; default: 0; - * The content of the 1th 32-bit RS code to be programmed. - */ - -#define EFUSE_PGM_RS_DATA_1 0xFFFFFFFF -#define EFUSE_PGM_RS_DATA_1_M (EFUSE_PGM_RS_DATA_1_V << EFUSE_PGM_RS_DATA_1_S) -#define EFUSE_PGM_RS_DATA_1_V 0xFFFFFFFF -#define EFUSE_PGM_RS_DATA_1_S 0 - -/* EFUSE_PGM_CHECK_VALUE2_REG register - * Register 2 that stores the RS code to be programmed. - */ - -#define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x28) - -/* EFUSE_PGM_RS_DATA_2 : R/W; bitpos: [31:0]; default: 0; - * The content of the 2th 32-bit RS code to be programmed. - */ - -#define EFUSE_PGM_RS_DATA_2 0xFFFFFFFF -#define EFUSE_PGM_RS_DATA_2_M (EFUSE_PGM_RS_DATA_2_V << EFUSE_PGM_RS_DATA_2_S) -#define EFUSE_PGM_RS_DATA_2_V 0xFFFFFFFF -#define EFUSE_PGM_RS_DATA_2_S 0 - -/* EFUSE_RD_WR_DIS_REG register - * Register 0 of BLOCK0. - */ - -#define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x2c) - -/* EFUSE_WR_DIS : RO; bitpos: [31:0]; default: 0; - * Disables programming of individual eFuses. - */ - -#define EFUSE_WR_DIS 0xFFFFFFFF -#define EFUSE_WR_DIS_M (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S) -#define EFUSE_WR_DIS_V 0xFFFFFFFF -#define EFUSE_WR_DIS_S 0 - -/* EFUSE_RD_REPEAT_DATA0_REG register - * Register 1 of BLOCK0. - */ - -#define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30) - -/* EFUSE_VDD_SPI_DREFH : RO; bitpos: [31:30]; default: 0; - * SPI regulator high voltage reference. - */ - -#define EFUSE_VDD_SPI_DREFH 0x00000003 -#define EFUSE_VDD_SPI_DREFH_M (EFUSE_VDD_SPI_DREFH_V << EFUSE_VDD_SPI_DREFH_S) -#define EFUSE_VDD_SPI_DREFH_V 0x00000003 -#define EFUSE_VDD_SPI_DREFH_S 30 - -/* EFUSE_VDD_SPI_MODECURLIM : RO; bitpos: [29]; default: 0; - * SPI regulator switches current limit mode. - */ - -#define EFUSE_VDD_SPI_MODECURLIM (BIT(29)) -#define EFUSE_VDD_SPI_MODECURLIM_M (EFUSE_VDD_SPI_MODECURLIM_V << EFUSE_VDD_SPI_MODECURLIM_S) -#define EFUSE_VDD_SPI_MODECURLIM_V 0x00000001 -#define EFUSE_VDD_SPI_MODECURLIM_S 29 - -/* EFUSE_RPT4_RESERVED0 : RO; bitpos: [28:27]; default: 0; - * Reserved (used for four backups method). - */ - -#define EFUSE_RPT4_RESERVED0 0x00000003 -#define EFUSE_RPT4_RESERVED0_M (EFUSE_RPT4_RESERVED0_V << EFUSE_RPT4_RESERVED0_S) -#define EFUSE_RPT4_RESERVED0_V 0x00000003 -#define EFUSE_RPT4_RESERVED0_S 27 - -/* EFUSE_USB_FORCE_NOPERSIST : RO; bitpos: [26]; default: 0; - * If set, forces USB BVALID to 1. - */ - -#define EFUSE_USB_FORCE_NOPERSIST (BIT(26)) -#define EFUSE_USB_FORCE_NOPERSIST_M (EFUSE_USB_FORCE_NOPERSIST_V << EFUSE_USB_FORCE_NOPERSIST_S) -#define EFUSE_USB_FORCE_NOPERSIST_V 0x00000001 -#define EFUSE_USB_FORCE_NOPERSIST_S 26 - -/* EFUSE_EXT_PHY_ENABLE : RO; bitpos: [25]; default: 0; - * Set this bit to enable external USB PHY. - */ - -#define EFUSE_EXT_PHY_ENABLE (BIT(25)) -#define EFUSE_EXT_PHY_ENABLE_M (EFUSE_EXT_PHY_ENABLE_V << EFUSE_EXT_PHY_ENABLE_S) -#define EFUSE_EXT_PHY_ENABLE_V 0x00000001 -#define EFUSE_EXT_PHY_ENABLE_S 25 - -/* EFUSE_USB_EXCHG_PINS : RO; bitpos: [24]; default: 0; - * Set this bit to exchange USB D+ and D- pins. - */ - -#define EFUSE_USB_EXCHG_PINS (BIT(24)) -#define EFUSE_USB_EXCHG_PINS_M (EFUSE_USB_EXCHG_PINS_V << EFUSE_USB_EXCHG_PINS_S) -#define EFUSE_USB_EXCHG_PINS_V 0x00000001 -#define EFUSE_USB_EXCHG_PINS_S 24 - -/* EFUSE_USB_DREFL : RO; bitpos: [23:22]; default: 0; - * Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of - * 80 mV, stored in eFuse. - */ - -#define EFUSE_USB_DREFL 0x00000003 -#define EFUSE_USB_DREFL_M (EFUSE_USB_DREFL_V << EFUSE_USB_DREFL_S) -#define EFUSE_USB_DREFL_V 0x00000003 -#define EFUSE_USB_DREFL_S 22 - -/* EFUSE_USB_DREFH : RO; bitpos: [21:20]; default: 0; - * Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 - * mV, stored in eFuse. - */ - -#define EFUSE_USB_DREFH 0x00000003 -#define EFUSE_USB_DREFH_M (EFUSE_USB_DREFH_V << EFUSE_USB_DREFH_S) -#define EFUSE_USB_DREFH_V 0x00000003 -#define EFUSE_USB_DREFH_S 20 - -/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO; bitpos: [19]; default: 0; - * Disables flash encryption when in download boot modes. - */ - -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT (BIT(19)) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001 -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 19 - -/* EFUSE_HARD_DIS_JTAG : RO; bitpos: [18]; default: 0; - * Hardware disables JTAG permanently. - */ - -#define EFUSE_HARD_DIS_JTAG (BIT(18)) -#define EFUSE_HARD_DIS_JTAG_M (EFUSE_HARD_DIS_JTAG_V << EFUSE_HARD_DIS_JTAG_S) -#define EFUSE_HARD_DIS_JTAG_V 0x00000001 -#define EFUSE_HARD_DIS_JTAG_S 18 - -/* EFUSE_SOFT_DIS_JTAG : RO; bitpos: [17]; default: 0; - * Software disables JTAG. When software disabled, JTAG can be activated - * temporarily by HMAC peripheral. - */ - -#define EFUSE_SOFT_DIS_JTAG (BIT(17)) -#define EFUSE_SOFT_DIS_JTAG_M (EFUSE_SOFT_DIS_JTAG_V << EFUSE_SOFT_DIS_JTAG_S) -#define EFUSE_SOFT_DIS_JTAG_V 0x00000001 -#define EFUSE_SOFT_DIS_JTAG_S 17 - -/* EFUSE_DIS_EFUSE_ATE_WR : RO; bitpos: [16]; default: 0; */ - -#define EFUSE_DIS_EFUSE_ATE_WR (BIT(16)) -#define EFUSE_DIS_EFUSE_ATE_WR_M (EFUSE_DIS_EFUSE_ATE_WR_V << EFUSE_DIS_EFUSE_ATE_WR_S) -#define EFUSE_DIS_EFUSE_ATE_WR_V 0x00000001 -#define EFUSE_DIS_EFUSE_ATE_WR_S 16 - -/* EFUSE_DIS_BOOT_REMAP : RO; bitpos: [15]; default: 0; - * Disables capability to Remap RAM to ROM address space. - */ - -#define EFUSE_DIS_BOOT_REMAP (BIT(15)) -#define EFUSE_DIS_BOOT_REMAP_M (EFUSE_DIS_BOOT_REMAP_V << EFUSE_DIS_BOOT_REMAP_S) -#define EFUSE_DIS_BOOT_REMAP_V 0x00000001 -#define EFUSE_DIS_BOOT_REMAP_S 15 - -/* EFUSE_DIS_CAN : RO; bitpos: [14]; default: 0; - * Set this bit to disable CAN function. - */ - -#define EFUSE_DIS_CAN (BIT(14)) -#define EFUSE_DIS_CAN_M (EFUSE_DIS_CAN_V << EFUSE_DIS_CAN_S) -#define EFUSE_DIS_CAN_V 0x00000001 -#define EFUSE_DIS_CAN_S 14 - -/* EFUSE_DIS_USB : RO; bitpos: [13]; default: 0; - * Set this bit to disable USB function. - */ - -#define EFUSE_DIS_USB (BIT(13)) -#define EFUSE_DIS_USB_M (EFUSE_DIS_USB_V << EFUSE_DIS_USB_S) -#define EFUSE_DIS_USB_V 0x00000001 -#define EFUSE_DIS_USB_S 13 - -/* EFUSE_DIS_FORCE_DOWNLOAD : RO; bitpos: [12]; default: 0; - * Set this bit to disable the function that forces chip into download mode. - */ - -#define EFUSE_DIS_FORCE_DOWNLOAD (BIT(12)) -#define EFUSE_DIS_FORCE_DOWNLOAD_M (EFUSE_DIS_FORCE_DOWNLOAD_V << EFUSE_DIS_FORCE_DOWNLOAD_S) -#define EFUSE_DIS_FORCE_DOWNLOAD_V 0x00000001 -#define EFUSE_DIS_FORCE_DOWNLOAD_S 12 - -/* EFUSE_DIS_DOWNLOAD_DCACHE : RO; bitpos: [11]; default: 0; - * Disables Dcache when SoC is in Download mode. - */ - -#define EFUSE_DIS_DOWNLOAD_DCACHE (BIT(11)) -#define EFUSE_DIS_DOWNLOAD_DCACHE_M (EFUSE_DIS_DOWNLOAD_DCACHE_V << EFUSE_DIS_DOWNLOAD_DCACHE_S) -#define EFUSE_DIS_DOWNLOAD_DCACHE_V 0x00000001 -#define EFUSE_DIS_DOWNLOAD_DCACHE_S 11 - -/* EFUSE_DIS_DOWNLOAD_ICACHE : RO; bitpos: [10]; default: 0; - * Disables Icache when SoC is in Download mode. - */ - -#define EFUSE_DIS_DOWNLOAD_ICACHE (BIT(10)) -#define EFUSE_DIS_DOWNLOAD_ICACHE_M (EFUSE_DIS_DOWNLOAD_ICACHE_V << EFUSE_DIS_DOWNLOAD_ICACHE_S) -#define EFUSE_DIS_DOWNLOAD_ICACHE_V 0x00000001 -#define EFUSE_DIS_DOWNLOAD_ICACHE_S 10 - -/* EFUSE_DIS_DCACHE : RO; bitpos: [9]; default: 0; - * Set this bit to disable Dcache. - */ - -#define EFUSE_DIS_DCACHE (BIT(9)) -#define EFUSE_DIS_DCACHE_M (EFUSE_DIS_DCACHE_V << EFUSE_DIS_DCACHE_S) -#define EFUSE_DIS_DCACHE_V 0x00000001 -#define EFUSE_DIS_DCACHE_S 9 - -/* EFUSE_DIS_ICACHE : RO; bitpos: [8]; default: 0; - * Set this bit to disable Icache. - */ - -#define EFUSE_DIS_ICACHE (BIT(8)) -#define EFUSE_DIS_ICACHE_M (EFUSE_DIS_ICACHE_V << EFUSE_DIS_ICACHE_S) -#define EFUSE_DIS_ICACHE_V 0x00000001 -#define EFUSE_DIS_ICACHE_S 8 - -/* EFUSE_DIS_RTC_RAM_BOOT : RO; bitpos: [7]; default: 0; - * Set this bit to disable boot from RTC RAM. - */ - -#define EFUSE_DIS_RTC_RAM_BOOT (BIT(7)) -#define EFUSE_DIS_RTC_RAM_BOOT_M (EFUSE_DIS_RTC_RAM_BOOT_V << EFUSE_DIS_RTC_RAM_BOOT_S) -#define EFUSE_DIS_RTC_RAM_BOOT_V 0x00000001 -#define EFUSE_DIS_RTC_RAM_BOOT_S 7 - -/* EFUSE_RD_DIS : RO; bitpos: [6:0]; default: 0; - * Disables software reading from individual eFuse blocks (BLOCK4-10). - */ - -#define EFUSE_RD_DIS 0x0000007F -#define EFUSE_RD_DIS_M (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S) -#define EFUSE_RD_DIS_V 0x0000007F -#define EFUSE_RD_DIS_S 0 - -/* EFUSE_RD_REPEAT_DATA1_REG register - * Register 2 of BLOCK0. - */ - -#define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x34) - -/* EFUSE_KEY_PURPOSE_1 : RO; bitpos: [31:28]; default: 0; - * Purpose of KEY1. Refer to Table Key Purpose Values. - */ - -#define EFUSE_KEY_PURPOSE_1 0x0000000F -#define EFUSE_KEY_PURPOSE_1_M (EFUSE_KEY_PURPOSE_1_V << EFUSE_KEY_PURPOSE_1_S) -#define EFUSE_KEY_PURPOSE_1_V 0x0000000F -#define EFUSE_KEY_PURPOSE_1_S 28 - -/* EFUSE_KEY_PURPOSE_0 : RO; bitpos: [27:24]; default: 0; - * Purpose of KEY0. Refer to Table Key Purpose Values. - */ - -#define EFUSE_KEY_PURPOSE_0 0x0000000F -#define EFUSE_KEY_PURPOSE_0_M (EFUSE_KEY_PURPOSE_0_V << EFUSE_KEY_PURPOSE_0_S) -#define EFUSE_KEY_PURPOSE_0_V 0x0000000F -#define EFUSE_KEY_PURPOSE_0_S 24 - -/* EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO; bitpos: [23]; default: 0; - * If set, revokes use of secure boot key digest 2. - */ - -#define EFUSE_SECURE_BOOT_KEY_REVOKE2 (BIT(23)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_S) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V 0x00000001 -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S 23 - -/* EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO; bitpos: [22]; default: 0; - * If set, revokes use of secure boot key digest 1. - */ - -#define EFUSE_SECURE_BOOT_KEY_REVOKE1 (BIT(22)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_S) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V 0x00000001 -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S 22 - -/* EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO; bitpos: [21]; default: 0; - * If set, revokes use of secure boot key digest 0. - */ - -#define EFUSE_SECURE_BOOT_KEY_REVOKE0 (BIT(21)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_S) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V 0x00000001 -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S 21 - -/* EFUSE_SPI_BOOT_CRYPT_CNT : RO; bitpos: [20:18]; default: 0; - * Enables encryption and decryption, when an SPI boot mode is set. Feature - * is enabled 1 or 3 bits are set in the eFuse, disabled otherwise. - */ - -#define EFUSE_SPI_BOOT_CRYPT_CNT 0x00000007 -#define EFUSE_SPI_BOOT_CRYPT_CNT_M (EFUSE_SPI_BOOT_CRYPT_CNT_V << EFUSE_SPI_BOOT_CRYPT_CNT_S) -#define EFUSE_SPI_BOOT_CRYPT_CNT_V 0x00000007 -#define EFUSE_SPI_BOOT_CRYPT_CNT_S 18 - -/* EFUSE_WDT_DELAY_SEL : RO; bitpos: [17:16]; default: 0; - * Selects RTC watchdog timeout threshold at startup. 0: 40,000 slow clock - * cycles; 1: 80,000 slow clock cycles; 2: 160,000 slow clock cycles; 3: - * 320,000 slow clock cycles. - */ - -#define EFUSE_WDT_DELAY_SEL 0x00000003 -#define EFUSE_WDT_DELAY_SEL_M (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S) -#define EFUSE_WDT_DELAY_SEL_V 0x00000003 -#define EFUSE_WDT_DELAY_SEL_S 16 - -/* EFUSE_VDD_SPI_DCAP : RO; bitpos: [15:14]; default: 0; - * Prevents SPI regulator from overshoot. - */ - -#define EFUSE_VDD_SPI_DCAP 0x00000003 -#define EFUSE_VDD_SPI_DCAP_M (EFUSE_VDD_SPI_DCAP_V << EFUSE_VDD_SPI_DCAP_S) -#define EFUSE_VDD_SPI_DCAP_V 0x00000003 -#define EFUSE_VDD_SPI_DCAP_S 14 - -/* EFUSE_VDD_SPI_INIT : RO; bitpos: [13:12]; default: 0; - * Adds resistor from LDO output to ground. 0: no resistance; 1: 6 K; 2: 4 - * K; 3: 2 K. - */ - -#define EFUSE_VDD_SPI_INIT 0x00000003 -#define EFUSE_VDD_SPI_INIT_M (EFUSE_VDD_SPI_INIT_V << EFUSE_VDD_SPI_INIT_S) -#define EFUSE_VDD_SPI_INIT_V 0x00000003 -#define EFUSE_VDD_SPI_INIT_S 12 - -/* EFUSE_VDD_SPI_DCURLIM : RO; bitpos: [11:9]; default: 0; - * Tunes the current limit threshold of SPI regulator when tieh=0, about 800 - * mA/(8+d). - */ - -#define EFUSE_VDD_SPI_DCURLIM 0x00000007 -#define EFUSE_VDD_SPI_DCURLIM_M (EFUSE_VDD_SPI_DCURLIM_V << EFUSE_VDD_SPI_DCURLIM_S) -#define EFUSE_VDD_SPI_DCURLIM_V 0x00000007 -#define EFUSE_VDD_SPI_DCURLIM_S 9 - -/* EFUSE_VDD_SPI_ENCURLIM : RO; bitpos: [8]; default: 0; - * Set SPI regulator to 1 to enable output current limit. - */ - -#define EFUSE_VDD_SPI_ENCURLIM (BIT(8)) -#define EFUSE_VDD_SPI_ENCURLIM_M (EFUSE_VDD_SPI_ENCURLIM_V << EFUSE_VDD_SPI_ENCURLIM_S) -#define EFUSE_VDD_SPI_ENCURLIM_V 0x00000001 -#define EFUSE_VDD_SPI_ENCURLIM_S 8 - -/* EFUSE_VDD_SPI_EN_INIT : RO; bitpos: [7]; default: 0; - * Set SPI regulator to 0 to configure init[1:0]=0. - */ - -#define EFUSE_VDD_SPI_EN_INIT (BIT(7)) -#define EFUSE_VDD_SPI_EN_INIT_M (EFUSE_VDD_SPI_EN_INIT_V << EFUSE_VDD_SPI_EN_INIT_S) -#define EFUSE_VDD_SPI_EN_INIT_V 0x00000001 -#define EFUSE_VDD_SPI_EN_INIT_S 7 - -/* EFUSE_VDD_SPI_FORCE : RO; bitpos: [6]; default: 0; - * Set this bit to use XPD_VDD_PSI_REG and VDD_SPI_TIEH to configure VDD_SPI - * LDO. - */ - -#define EFUSE_VDD_SPI_FORCE (BIT(6)) -#define EFUSE_VDD_SPI_FORCE_M (EFUSE_VDD_SPI_FORCE_V << EFUSE_VDD_SPI_FORCE_S) -#define EFUSE_VDD_SPI_FORCE_V 0x00000001 -#define EFUSE_VDD_SPI_FORCE_S 6 - -/* EFUSE_VDD_SPI_TIEH : RO; bitpos: [5]; default: 0; - * If VDD_SPI_FORCE is 1, determines VDD_SPI voltage. 0: VDD_SPI connects to - * 1.8 V LDO; 1: VDD_SPI connects to VDD_RTC_IO. - */ - -#define EFUSE_VDD_SPI_TIEH (BIT(5)) -#define EFUSE_VDD_SPI_TIEH_M (EFUSE_VDD_SPI_TIEH_V << EFUSE_VDD_SPI_TIEH_S) -#define EFUSE_VDD_SPI_TIEH_V 0x00000001 -#define EFUSE_VDD_SPI_TIEH_S 5 - -/* EFUSE_VDD_SPI_XPD : RO; bitpos: [4]; default: 0; - * If VDD_SPI_FORCE is 1, this value determines if the VDD_SPI regulator is - * powered on. - */ - -#define EFUSE_VDD_SPI_XPD (BIT(4)) -#define EFUSE_VDD_SPI_XPD_M (EFUSE_VDD_SPI_XPD_V << EFUSE_VDD_SPI_XPD_S) -#define EFUSE_VDD_SPI_XPD_V 0x00000001 -#define EFUSE_VDD_SPI_XPD_S 4 - -/* EFUSE_VDD_SPI_DREFL : RO; bitpos: [3:2]; default: 0; - * SPI regulator low voltage reference. - */ - -#define EFUSE_VDD_SPI_DREFL 0x00000003 -#define EFUSE_VDD_SPI_DREFL_M (EFUSE_VDD_SPI_DREFL_V << EFUSE_VDD_SPI_DREFL_S) -#define EFUSE_VDD_SPI_DREFL_V 0x00000003 -#define EFUSE_VDD_SPI_DREFL_S 2 - -/* EFUSE_VDD_SPI_DREFM : RO; bitpos: [1:0]; default: 0; - * SPI regulator medium voltage reference. - */ - -#define EFUSE_VDD_SPI_DREFM 0x00000003 -#define EFUSE_VDD_SPI_DREFM_M (EFUSE_VDD_SPI_DREFM_V << EFUSE_VDD_SPI_DREFM_S) -#define EFUSE_VDD_SPI_DREFM_V 0x00000003 -#define EFUSE_VDD_SPI_DREFM_S 0 - -/* EFUSE_RD_REPEAT_DATA2_REG register - * Register 3 of BLOCK0. - */ - -#define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x38) - -/* EFUSE_FLASH_TPUW : RO; bitpos: [31:28]; default: 0; - * Configures flash startup delay after SoC power-up, in unit of (ms/2). - * When the value is 15, delay is 7.5 ms. - */ - -#define EFUSE_FLASH_TPUW 0x0000000F -#define EFUSE_FLASH_TPUW_M (EFUSE_FLASH_TPUW_V << EFUSE_FLASH_TPUW_S) -#define EFUSE_FLASH_TPUW_V 0x0000000F -#define EFUSE_FLASH_TPUW_S 28 - -/* EFUSE_RPT4_RESERVED1 : RO; bitpos: [27:22]; default: 0; - * Reserved (used for four backups method). - */ - -#define EFUSE_RPT4_RESERVED1 0x0000003F -#define EFUSE_RPT4_RESERVED1_M (EFUSE_RPT4_RESERVED1_V << EFUSE_RPT4_RESERVED1_S) -#define EFUSE_RPT4_RESERVED1_V 0x0000003F -#define EFUSE_RPT4_RESERVED1_S 22 - -/* EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO; bitpos: [21]; default: 0; - * Set this bit to enable aggressive secure boot key revocation mode. - */ - -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE (BIT(21)) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V 0x00000001 -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S 21 - -/* EFUSE_SECURE_BOOT_EN : RO; bitpos: [20]; default: 0; - * Set this bit to enable secure boot. - */ - -#define EFUSE_SECURE_BOOT_EN (BIT(20)) -#define EFUSE_SECURE_BOOT_EN_M (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S) -#define EFUSE_SECURE_BOOT_EN_V 0x00000001 -#define EFUSE_SECURE_BOOT_EN_S 20 - -/* EFUSE_KEY_PURPOSE_6 : RO; bitpos: [19:16]; default: 0; - * Purpose of KEY6. Refer to Table Key Purpose Values. - */ - -#define EFUSE_KEY_PURPOSE_6 0x0000000F -#define EFUSE_KEY_PURPOSE_6_M (EFUSE_KEY_PURPOSE_6_V << EFUSE_KEY_PURPOSE_6_S) -#define EFUSE_KEY_PURPOSE_6_V 0x0000000F -#define EFUSE_KEY_PURPOSE_6_S 16 - -/* EFUSE_KEY_PURPOSE_5 : RO; bitpos: [15:12]; default: 0; - * Purpose of KEY5. Refer to Table Key Purpose Values. - */ - -#define EFUSE_KEY_PURPOSE_5 0x0000000F -#define EFUSE_KEY_PURPOSE_5_M (EFUSE_KEY_PURPOSE_5_V << EFUSE_KEY_PURPOSE_5_S) -#define EFUSE_KEY_PURPOSE_5_V 0x0000000F -#define EFUSE_KEY_PURPOSE_5_S 12 - -/* EFUSE_KEY_PURPOSE_4 : RO; bitpos: [11:8]; default: 0; - * Purpose of KEY4. Refer to Table Key Purpose Values. - */ - -#define EFUSE_KEY_PURPOSE_4 0x0000000F -#define EFUSE_KEY_PURPOSE_4_M (EFUSE_KEY_PURPOSE_4_V << EFUSE_KEY_PURPOSE_4_S) -#define EFUSE_KEY_PURPOSE_4_V 0x0000000F -#define EFUSE_KEY_PURPOSE_4_S 8 - -/* EFUSE_KEY_PURPOSE_3 : RO; bitpos: [7:4]; default: 0; - * Purpose of KEY3. Refer to Table Key Purpose Values. - */ - -#define EFUSE_KEY_PURPOSE_3 0x0000000F -#define EFUSE_KEY_PURPOSE_3_M (EFUSE_KEY_PURPOSE_3_V << EFUSE_KEY_PURPOSE_3_S) -#define EFUSE_KEY_PURPOSE_3_V 0x0000000F -#define EFUSE_KEY_PURPOSE_3_S 4 - -/* EFUSE_KEY_PURPOSE_2 : RO; bitpos: [3:0]; default: 0; - * Purpose of KEY2. Refer to Table Key Purpose Values. - */ - -#define EFUSE_KEY_PURPOSE_2 0x0000000F -#define EFUSE_KEY_PURPOSE_2_M (EFUSE_KEY_PURPOSE_2_V << EFUSE_KEY_PURPOSE_2_S) -#define EFUSE_KEY_PURPOSE_2_V 0x0000000F -#define EFUSE_KEY_PURPOSE_2_S 0 - -/* EFUSE_RD_REPEAT_DATA3_REG register - * Register 4 of BLOCK0. - */ - -#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x3c) - -/* EFUSE_RPT4_RESERVED2 : RO; bitpos: [31:27]; default: 0; - * Reserved (used for four backups method). - */ - -#define EFUSE_RPT4_RESERVED2 0x0000001F -#define EFUSE_RPT4_RESERVED2_M (EFUSE_RPT4_RESERVED2_V << EFUSE_RPT4_RESERVED2_S) -#define EFUSE_RPT4_RESERVED2_V 0x0000001F -#define EFUSE_RPT4_RESERVED2_S 27 - -/* EFUSE_SECURE_VERSION : RO; bitpos: [26:11]; default: 0; - * Secure version (used by ESP-IDF anti-rollback feature). - */ - -#define EFUSE_SECURE_VERSION 0x0000FFFF -#define EFUSE_SECURE_VERSION_M (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S) -#define EFUSE_SECURE_VERSION_V 0x0000FFFF -#define EFUSE_SECURE_VERSION_S 11 - -/* EFUSE_FORCE_SEND_RESUME : RO; bitpos: [10]; default: 0; - * If set, forces ROM code to send an SPI flash resume command during SPI - * boot. - */ - -#define EFUSE_FORCE_SEND_RESUME (BIT(10)) -#define EFUSE_FORCE_SEND_RESUME_M (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S) -#define EFUSE_FORCE_SEND_RESUME_V 0x00000001 -#define EFUSE_FORCE_SEND_RESUME_S 10 - -/* EFUSE_FLASH_TYPE : RO; bitpos: [9]; default: 0; - * SPI flash type. 0: maximum four data lines, 1: eight data lines. - */ - -#define EFUSE_FLASH_TYPE (BIT(9)) -#define EFUSE_FLASH_TYPE_M (EFUSE_FLASH_TYPE_V << EFUSE_FLASH_TYPE_S) -#define EFUSE_FLASH_TYPE_V 0x00000001 -#define EFUSE_FLASH_TYPE_S 9 - -/* EFUSE_PIN_POWER_SELECTION : RO; bitpos: [8]; default: 0; - * Set default power supply for GPIO33-GPIO37, set when SPI flash is - * initialized. 0: VDD3P3_CPU; 1: VDD_SPI. - */ - -#define EFUSE_PIN_POWER_SELECTION (BIT(8)) -#define EFUSE_PIN_POWER_SELECTION_M (EFUSE_PIN_POWER_SELECTION_V << EFUSE_PIN_POWER_SELECTION_S) -#define EFUSE_PIN_POWER_SELECTION_V 0x00000001 -#define EFUSE_PIN_POWER_SELECTION_S 8 - -/* EFUSE_UART_PRINT_CONTROL : RO; bitpos: [7:6]; default: 0; - * Set the default UART boot message output mode. - * & - * 00: Enabled.# - * 01: Enable when GPIO46 is low at reset.# - * 10: Enable when GPIO46 is high at reset.# - * 11: Disabled. - * & - */ - -#define EFUSE_UART_PRINT_CONTROL 0x00000003 -#define EFUSE_UART_PRINT_CONTROL_M (EFUSE_UART_PRINT_CONTROL_V << EFUSE_UART_PRINT_CONTROL_S) -#define EFUSE_UART_PRINT_CONTROL_V 0x00000003 -#define EFUSE_UART_PRINT_CONTROL_S 6 - -/* EFUSE_ENABLE_SECURITY_DOWNLOAD : RO; bitpos: [5]; default: 0; - * Set this bit to enable secure UART download mode (read/write flash only). - */ - -#define EFUSE_ENABLE_SECURITY_DOWNLOAD (BIT(5)) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_S) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V 0x00000001 -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S 5 - -/* EFUSE_DIS_USB_DOWNLOAD_MODE : RO; bitpos: [4]; default: 0; - * Set this bit to disable use of USB in UART download boot mode. - */ - -#define EFUSE_DIS_USB_DOWNLOAD_MODE (BIT(4)) -#define EFUSE_DIS_USB_DOWNLOAD_MODE_M (EFUSE_DIS_USB_DOWNLOAD_MODE_V << EFUSE_DIS_USB_DOWNLOAD_MODE_S) -#define EFUSE_DIS_USB_DOWNLOAD_MODE_V 0x00000001 -#define EFUSE_DIS_USB_DOWNLOAD_MODE_S 4 - -/* EFUSE_RPT4_RESERVED3 : RO; bitpos: [3]; default: 0; - * Reserved (used for four backups method). - */ - -#define EFUSE_RPT4_RESERVED3 (BIT(3)) -#define EFUSE_RPT4_RESERVED3_M (EFUSE_RPT4_RESERVED3_V << EFUSE_RPT4_RESERVED3_S) -#define EFUSE_RPT4_RESERVED3_V 0x00000001 -#define EFUSE_RPT4_RESERVED3_S 3 - -/* EFUSE_UART_PRINT_CHANNEL : RO; bitpos: [2]; default: 0; - * Selects the default UART for printing boot messages. 0: UART0; 1: UART1. - */ - -#define EFUSE_UART_PRINT_CHANNEL (BIT(2)) -#define EFUSE_UART_PRINT_CHANNEL_M (EFUSE_UART_PRINT_CHANNEL_V << EFUSE_UART_PRINT_CHANNEL_S) -#define EFUSE_UART_PRINT_CHANNEL_V 0x00000001 -#define EFUSE_UART_PRINT_CHANNEL_S 2 - -/* EFUSE_DIS_LEGACY_SPI_BOOT : RO; bitpos: [1]; default: 0; - * Set this bit to disable Legacy SPI boot mode. - */ - -#define EFUSE_DIS_LEGACY_SPI_BOOT (BIT(1)) -#define EFUSE_DIS_LEGACY_SPI_BOOT_M (EFUSE_DIS_LEGACY_SPI_BOOT_V << EFUSE_DIS_LEGACY_SPI_BOOT_S) -#define EFUSE_DIS_LEGACY_SPI_BOOT_V 0x00000001 -#define EFUSE_DIS_LEGACY_SPI_BOOT_S 1 - -/* EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [0]; default: 0; - * Set this bit to disable all download boot modes. - */ - -#define EFUSE_DIS_DOWNLOAD_MODE (BIT(0)) -#define EFUSE_DIS_DOWNLOAD_MODE_M (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S) -#define EFUSE_DIS_DOWNLOAD_MODE_V 0x00000001 -#define EFUSE_DIS_DOWNLOAD_MODE_S 0 - -/* EFUSE_RD_REPEAT_DATA4_REG register - * Register 5 of BLOCK0. - */ - -#define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40) - -/* EFUSE_RPT4_RESERVED4 : RO; bitpos: [23:0]; default: 0; - * Reserved (used for four backups method). - */ - -#define EFUSE_RPT4_RESERVED4 0x00FFFFFF -#define EFUSE_RPT4_RESERVED4_M (EFUSE_RPT4_RESERVED4_V << EFUSE_RPT4_RESERVED4_S) -#define EFUSE_RPT4_RESERVED4_V 0x00FFFFFF -#define EFUSE_RPT4_RESERVED4_S 0 - -/* EFUSE_RD_MAC_SPI_SYS_0_REG register - * Register 0 of BLOCK1. - */ - -#define EFUSE_RD_MAC_SPI_SYS_0_REG (DR_REG_EFUSE_BASE + 0x44) - -/* EFUSE_MAC_0 : RO; bitpos: [31:0]; default: 0; - * Stores the low 32 bits of MAC address. - */ - -#define EFUSE_MAC_0 0xFFFFFFFF -#define EFUSE_MAC_0_M (EFUSE_MAC_0_V << EFUSE_MAC_0_S) -#define EFUSE_MAC_0_V 0xFFFFFFFF -#define EFUSE_MAC_0_S 0 - -/* EFUSE_RD_MAC_SPI_SYS_1_REG register - * Register 1 of BLOCK1. - */ - -#define EFUSE_RD_MAC_SPI_SYS_1_REG (DR_REG_EFUSE_BASE + 0x48) - -/* EFUSE_SPI_PAD_CONF_0 : RO; bitpos: [31:16]; default: 0; - * Stores the zeroth part of SPI_PAD_CONF. - */ - -#define EFUSE_SPI_PAD_CONF_0 0x0000FFFF -#define EFUSE_SPI_PAD_CONF_0_M (EFUSE_SPI_PAD_CONF_0_V << EFUSE_SPI_PAD_CONF_0_S) -#define EFUSE_SPI_PAD_CONF_0_V 0x0000FFFF -#define EFUSE_SPI_PAD_CONF_0_S 16 - -/* EFUSE_MAC_1 : RO; bitpos: [15:0]; default: 0; - * Stores the high 16 bits of MAC address. - */ - -#define EFUSE_MAC_1 0x0000FFFF -#define EFUSE_MAC_1_M (EFUSE_MAC_1_V << EFUSE_MAC_1_S) -#define EFUSE_MAC_1_V 0x0000FFFF -#define EFUSE_MAC_1_S 0 - -/* EFUSE_RD_MAC_SPI_SYS_2_REG register - * Register 2 of BLOCK1. - */ - -#define EFUSE_RD_MAC_SPI_SYS_2_REG (DR_REG_EFUSE_BASE + 0x4c) - -/* EFUSE_SPI_PAD_CONF_1 : RO; bitpos: [31:0]; default: 0; - * Stores the first part of SPI_PAD_CONF. - */ - -#define EFUSE_SPI_PAD_CONF_1 0xFFFFFFFF -#define EFUSE_SPI_PAD_CONF_1_M (EFUSE_SPI_PAD_CONF_1_V << EFUSE_SPI_PAD_CONF_1_S) -#define EFUSE_SPI_PAD_CONF_1_V 0xFFFFFFFF -#define EFUSE_SPI_PAD_CONF_1_S 0 - -/* EFUSE_RD_MAC_SPI_SYS_3_REG register - * Register 3 of BLOCK1. - */ - -#define EFUSE_RD_MAC_SPI_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50) - -/* EFUSE_SYS_DATA_PART0_0 : RO; bitpos: [31:18]; default: 0; - * Stores the zeroth part of the zeroth part of system data. - */ - -#define EFUSE_SYS_DATA_PART0_0 0x00003FFF -#define EFUSE_SYS_DATA_PART0_0_M (EFUSE_SYS_DATA_PART0_0_V << EFUSE_SYS_DATA_PART0_0_S) -#define EFUSE_SYS_DATA_PART0_0_V 0x00003FFF -#define EFUSE_SYS_DATA_PART0_0_S 18 - -/* EFUSE_SPI_PAD_CONF_2 : RO; bitpos: [17:0]; default: 0; - * Stores the second part of SPI_PAD_CONF. - */ - -#define EFUSE_SPI_PAD_CONF_2 0x0003FFFF -#define EFUSE_SPI_PAD_CONF_2_M (EFUSE_SPI_PAD_CONF_2_V << EFUSE_SPI_PAD_CONF_2_S) -#define EFUSE_SPI_PAD_CONF_2_V 0x0003FFFF -#define EFUSE_SPI_PAD_CONF_2_S 0 - -/* EFUSE_RD_MAC_SPI_SYS_4_REG register - * Register 4 of BLOCK1. - */ - -#define EFUSE_RD_MAC_SPI_SYS_4_REG (DR_REG_EFUSE_BASE + 0x54) - -/* EFUSE_SYS_DATA_PART0_1 : RO; bitpos: [31:0]; default: 0; - * Stores the fist part of the zeroth part of system data. - */ - -#define EFUSE_SYS_DATA_PART0_1 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART0_1_M (EFUSE_SYS_DATA_PART0_1_V << EFUSE_SYS_DATA_PART0_1_S) -#define EFUSE_SYS_DATA_PART0_1_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART0_1_S 0 - -/* EFUSE_RD_MAC_SPI_SYS_5_REG register - * Register 5 of BLOCK1. - */ - -#define EFUSE_RD_MAC_SPI_SYS_5_REG (DR_REG_EFUSE_BASE + 0x58) - -/* EFUSE_SYS_DATA_PART0_2 : RO; bitpos: [31:0]; default: 0; - * Stores the second part of the zeroth part of system data. - */ - -#define EFUSE_SYS_DATA_PART0_2 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART0_2_M (EFUSE_SYS_DATA_PART0_2_V << EFUSE_SYS_DATA_PART0_2_S) -#define EFUSE_SYS_DATA_PART0_2_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART0_2_S 0 - -/* EFUSE_RD_SYS_DATA_PART1_0_REG register - * Register 0 of BLOCK2 (system). - */ - -#define EFUSE_RD_SYS_DATA_PART1_0_REG (DR_REG_EFUSE_BASE + 0x5c) - -/* EFUSE_SYS_DATA_PART1_0 : RO; bitpos: [31:0]; default: 0; - * Stores the 0th 32 bits of the first part of system data. - */ - -#define EFUSE_SYS_DATA_PART1_0 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_0_M (EFUSE_SYS_DATA_PART1_0_V << EFUSE_SYS_DATA_PART1_0_S) -#define EFUSE_SYS_DATA_PART1_0_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_0_S 0 - -/* EFUSE_RD_SYS_DATA_PART1_1_REG register - * Register 1 of BLOCK2 (system). - */ - -#define EFUSE_RD_SYS_DATA_PART1_1_REG (DR_REG_EFUSE_BASE + 0x60) - -/* EFUSE_SYS_DATA_PART1_1 : RO; bitpos: [31:0]; default: 0; - * Stores the 1th 32 bits of the first part of system data. - */ - -#define EFUSE_SYS_DATA_PART1_1 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_1_M (EFUSE_SYS_DATA_PART1_1_V << EFUSE_SYS_DATA_PART1_1_S) -#define EFUSE_SYS_DATA_PART1_1_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_1_S 0 - -/* EFUSE_RD_SYS_DATA_PART1_2_REG register - * Register 2 of BLOCK2 (system). - */ - -#define EFUSE_RD_SYS_DATA_PART1_2_REG (DR_REG_EFUSE_BASE + 0x64) - -/* EFUSE_SYS_DATA_PART1_2 : RO; bitpos: [31:0]; default: 0; - * Stores the 2th 32 bits of the first part of system data. - */ - -#define EFUSE_SYS_DATA_PART1_2 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_2_M (EFUSE_SYS_DATA_PART1_2_V << EFUSE_SYS_DATA_PART1_2_S) -#define EFUSE_SYS_DATA_PART1_2_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_2_S 0 - -/* EFUSE_RD_SYS_DATA_PART1_3_REG register - * Register 3 of BLOCK2 (system). - */ - -#define EFUSE_RD_SYS_DATA_PART1_3_REG (DR_REG_EFUSE_BASE + 0x68) - -/* EFUSE_SYS_DATA_PART1_3 : RO; bitpos: [31:0]; default: 0; - * Stores the 3th 32 bits of the first part of system data. - */ - -#define EFUSE_SYS_DATA_PART1_3 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_3_M (EFUSE_SYS_DATA_PART1_3_V << EFUSE_SYS_DATA_PART1_3_S) -#define EFUSE_SYS_DATA_PART1_3_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_3_S 0 - -/* EFUSE_RD_SYS_DATA_PART1_4_REG register - * Register 4 of BLOCK2 (system). - */ - -#define EFUSE_RD_SYS_DATA_PART1_4_REG (DR_REG_EFUSE_BASE + 0x6c) - -/* EFUSE_SYS_DATA_PART1_4 : RO; bitpos: [31:0]; default: 0; - * Stores the 4th 32 bits of the first part of system data. - */ - -#define EFUSE_SYS_DATA_PART1_4 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_4_M (EFUSE_SYS_DATA_PART1_4_V << EFUSE_SYS_DATA_PART1_4_S) -#define EFUSE_SYS_DATA_PART1_4_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_4_S 0 - -/* EFUSE_RD_SYS_DATA_PART1_5_REG register - * Register 5 of BLOCK2 (system). - */ - -#define EFUSE_RD_SYS_DATA_PART1_5_REG (DR_REG_EFUSE_BASE + 0x70) - -/* EFUSE_SYS_DATA_PART1_5 : RO; bitpos: [31:0]; default: 0; - * Stores the 5th 32 bits of the first part of system data. - */ - -#define EFUSE_SYS_DATA_PART1_5 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_5_M (EFUSE_SYS_DATA_PART1_5_V << EFUSE_SYS_DATA_PART1_5_S) -#define EFUSE_SYS_DATA_PART1_5_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_5_S 0 - -/* EFUSE_RD_SYS_DATA_PART1_6_REG register - * Register 6 of BLOCK2 (system). - */ - -#define EFUSE_RD_SYS_DATA_PART1_6_REG (DR_REG_EFUSE_BASE + 0x74) - -/* EFUSE_SYS_DATA_PART1_6 : RO; bitpos: [31:0]; default: 0; - * Stores the 6th 32 bits of the first part of system data. - */ - -#define EFUSE_SYS_DATA_PART1_6 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_6_M (EFUSE_SYS_DATA_PART1_6_V << EFUSE_SYS_DATA_PART1_6_S) -#define EFUSE_SYS_DATA_PART1_6_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_6_S 0 - -/* EFUSE_RD_SYS_DATA_PART1_7_REG register - * Register 7 of BLOCK2 (system). - */ - -#define EFUSE_RD_SYS_DATA_PART1_7_REG (DR_REG_EFUSE_BASE + 0x78) - -/* EFUSE_SYS_DATA_PART1_7 : RO; bitpos: [31:0]; default: 0; - * Stores the 7th 32 bits of the first part of system data. - */ - -#define EFUSE_SYS_DATA_PART1_7 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_7_M (EFUSE_SYS_DATA_PART1_7_V << EFUSE_SYS_DATA_PART1_7_S) -#define EFUSE_SYS_DATA_PART1_7_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART1_7_S 0 - -/* EFUSE_RD_USR_DATA0_REG register - * Register 0 of BLOCK3 (user). - */ - -#define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x7c) - -/* EFUSE_USR_DATA0 : RO; bitpos: [31:0]; default: 0; - * Stores the 0th 32 bits of BLOCK3 (user). - */ - -#define EFUSE_USR_DATA0 0xFFFFFFFF -#define EFUSE_USR_DATA0_M (EFUSE_USR_DATA0_V << EFUSE_USR_DATA0_S) -#define EFUSE_USR_DATA0_V 0xFFFFFFFF -#define EFUSE_USR_DATA0_S 0 - -/* EFUSE_RD_USR_DATA1_REG register - * Register 1 of BLOCK3 (user). - */ - -#define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x80) - -/* EFUSE_USR_DATA1 : RO; bitpos: [31:0]; default: 0; - * Stores the 1th 32 bits of BLOCK3 (user). - */ - -#define EFUSE_USR_DATA1 0xFFFFFFFF -#define EFUSE_USR_DATA1_M (EFUSE_USR_DATA1_V << EFUSE_USR_DATA1_S) -#define EFUSE_USR_DATA1_V 0xFFFFFFFF -#define EFUSE_USR_DATA1_S 0 - -/* EFUSE_RD_USR_DATA2_REG register - * Register 2 of BLOCK3 (user). - */ - -#define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x84) - -/* EFUSE_USR_DATA2 : RO; bitpos: [31:0]; default: 0; - * Stores the 2th 32 bits of BLOCK3 (user). - */ - -#define EFUSE_USR_DATA2 0xFFFFFFFF -#define EFUSE_USR_DATA2_M (EFUSE_USR_DATA2_V << EFUSE_USR_DATA2_S) -#define EFUSE_USR_DATA2_V 0xFFFFFFFF -#define EFUSE_USR_DATA2_S 0 - -/* EFUSE_RD_USR_DATA3_REG register - * Register 3 of BLOCK3 (user). - */ - -#define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x88) - -/* EFUSE_USR_DATA3 : RO; bitpos: [31:0]; default: 0; - * Stores the 3th 32 bits of BLOCK3 (user). - */ - -#define EFUSE_USR_DATA3 0xFFFFFFFF -#define EFUSE_USR_DATA3_M (EFUSE_USR_DATA3_V << EFUSE_USR_DATA3_S) -#define EFUSE_USR_DATA3_V 0xFFFFFFFF -#define EFUSE_USR_DATA3_S 0 - -/* EFUSE_RD_USR_DATA4_REG register - * Register 4 of BLOCK3 (user). - */ - -#define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x8c) - -/* EFUSE_USR_DATA4 : RO; bitpos: [31:0]; default: 0; - * Stores the 4th 32 bits of BLOCK3 (user). - */ - -#define EFUSE_USR_DATA4 0xFFFFFFFF -#define EFUSE_USR_DATA4_M (EFUSE_USR_DATA4_V << EFUSE_USR_DATA4_S) -#define EFUSE_USR_DATA4_V 0xFFFFFFFF -#define EFUSE_USR_DATA4_S 0 - -/* EFUSE_RD_USR_DATA5_REG register - * Register 5 of BLOCK3 (user). - */ - -#define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x90) - -/* EFUSE_USR_DATA5 : RO; bitpos: [31:0]; default: 0; - * Stores the 5th 32 bits of BLOCK3 (user). - */ - -#define EFUSE_USR_DATA5 0xFFFFFFFF -#define EFUSE_USR_DATA5_M (EFUSE_USR_DATA5_V << EFUSE_USR_DATA5_S) -#define EFUSE_USR_DATA5_V 0xFFFFFFFF -#define EFUSE_USR_DATA5_S 0 - -/* EFUSE_RD_USR_DATA6_REG register - * Register 6 of BLOCK3 (user). - */ - -#define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94) - -/* EFUSE_USR_DATA6 : RO; bitpos: [31:0]; default: 0; - * Stores the 6th 32 bits of BLOCK3 (user). - */ - -#define EFUSE_USR_DATA6 0xFFFFFFFF -#define EFUSE_USR_DATA6_M (EFUSE_USR_DATA6_V << EFUSE_USR_DATA6_S) -#define EFUSE_USR_DATA6_V 0xFFFFFFFF -#define EFUSE_USR_DATA6_S 0 - -/* EFUSE_RD_USR_DATA7_REG register - * Register 7 of BLOCK3 (user). - */ - -#define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98) - -/* EFUSE_USR_DATA7 : RO; bitpos: [31:0]; default: 0; - * Stores the 7th 32 bits of BLOCK3 (user). - */ - -#define EFUSE_USR_DATA7 0xFFFFFFFF -#define EFUSE_USR_DATA7_M (EFUSE_USR_DATA7_V << EFUSE_USR_DATA7_S) -#define EFUSE_USR_DATA7_V 0xFFFFFFFF -#define EFUSE_USR_DATA7_S 0 - -/* EFUSE_RD_KEY0_DATA0_REG register - * Register 0 of BLOCK4 (KEY0). - */ - -#define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0x9c) - -/* EFUSE_KEY0_DATA0 : RO; bitpos: [31:0]; default: 0; - * Stores the 0th 32 bits of KEY0. - */ - -#define EFUSE_KEY0_DATA0 0xFFFFFFFF -#define EFUSE_KEY0_DATA0_M (EFUSE_KEY0_DATA0_V << EFUSE_KEY0_DATA0_S) -#define EFUSE_KEY0_DATA0_V 0xFFFFFFFF -#define EFUSE_KEY0_DATA0_S 0 - -/* EFUSE_RD_KEY0_DATA1_REG register - * Register 1 of BLOCK4 (KEY0). - */ - -#define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0xa0) - -/* EFUSE_KEY0_DATA1 : RO; bitpos: [31:0]; default: 0; - * Stores the 1th 32 bits of KEY0. - */ - -#define EFUSE_KEY0_DATA1 0xFFFFFFFF -#define EFUSE_KEY0_DATA1_M (EFUSE_KEY0_DATA1_V << EFUSE_KEY0_DATA1_S) -#define EFUSE_KEY0_DATA1_V 0xFFFFFFFF -#define EFUSE_KEY0_DATA1_S 0 - -/* EFUSE_RD_KEY0_DATA2_REG register - * Register 2 of BLOCK4 (KEY0). - */ - -#define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0xa4) - -/* EFUSE_KEY0_DATA2 : RO; bitpos: [31:0]; default: 0; - * Stores the 2th 32 bits of KEY0. - */ - -#define EFUSE_KEY0_DATA2 0xFFFFFFFF -#define EFUSE_KEY0_DATA2_M (EFUSE_KEY0_DATA2_V << EFUSE_KEY0_DATA2_S) -#define EFUSE_KEY0_DATA2_V 0xFFFFFFFF -#define EFUSE_KEY0_DATA2_S 0 - -/* EFUSE_RD_KEY0_DATA3_REG register - * Register 3 of BLOCK4 (KEY0). - */ - -#define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0xa8) - -/* EFUSE_KEY0_DATA3 : RO; bitpos: [31:0]; default: 0; - * Stores the 3th 32 bits of KEY0. - */ - -#define EFUSE_KEY0_DATA3 0xFFFFFFFF -#define EFUSE_KEY0_DATA3_M (EFUSE_KEY0_DATA3_V << EFUSE_KEY0_DATA3_S) -#define EFUSE_KEY0_DATA3_V 0xFFFFFFFF -#define EFUSE_KEY0_DATA3_S 0 - -/* EFUSE_RD_KEY0_DATA4_REG register - * Register 4 of BLOCK4 (KEY0). - */ - -#define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0xac) - -/* EFUSE_KEY0_DATA4 : RO; bitpos: [31:0]; default: 0; - * Stores the 4th 32 bits of KEY0. - */ - -#define EFUSE_KEY0_DATA4 0xFFFFFFFF -#define EFUSE_KEY0_DATA4_M (EFUSE_KEY0_DATA4_V << EFUSE_KEY0_DATA4_S) -#define EFUSE_KEY0_DATA4_V 0xFFFFFFFF -#define EFUSE_KEY0_DATA4_S 0 - -/* EFUSE_RD_KEY0_DATA5_REG register - * Register 5 of BLOCK4 (KEY0). - */ - -#define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0xb0) - -/* EFUSE_KEY0_DATA5 : RO; bitpos: [31:0]; default: 0; - * Stores the 5th 32 bits of KEY0. - */ - -#define EFUSE_KEY0_DATA5 0xFFFFFFFF -#define EFUSE_KEY0_DATA5_M (EFUSE_KEY0_DATA5_V << EFUSE_KEY0_DATA5_S) -#define EFUSE_KEY0_DATA5_V 0xFFFFFFFF -#define EFUSE_KEY0_DATA5_S 0 - -/* EFUSE_RD_KEY0_DATA6_REG register - * Register 6 of BLOCK4 (KEY0). - */ - -#define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0xb4) - -/* EFUSE_KEY0_DATA6 : RO; bitpos: [31:0]; default: 0; - * Stores the 6th 32 bits of KEY0. - */ - -#define EFUSE_KEY0_DATA6 0xFFFFFFFF -#define EFUSE_KEY0_DATA6_M (EFUSE_KEY0_DATA6_V << EFUSE_KEY0_DATA6_S) -#define EFUSE_KEY0_DATA6_V 0xFFFFFFFF -#define EFUSE_KEY0_DATA6_S 0 - -/* EFUSE_RD_KEY0_DATA7_REG register - * Register 7 of BLOCK4 (KEY0). - */ - -#define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0xb8) - -/* EFUSE_KEY0_DATA7 : RO; bitpos: [31:0]; default: 0; - * Stores the 7th 32 bits of KEY0. - */ - -#define EFUSE_KEY0_DATA7 0xFFFFFFFF -#define EFUSE_KEY0_DATA7_M (EFUSE_KEY0_DATA7_V << EFUSE_KEY0_DATA7_S) -#define EFUSE_KEY0_DATA7_V 0xFFFFFFFF -#define EFUSE_KEY0_DATA7_S 0 - -/* EFUSE_RD_KEY1_DATA0_REG register - * Register 0 of BLOCK5 (KEY1). - */ - -#define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0xbc) - -/* EFUSE_KEY1_DATA0 : RO; bitpos: [31:0]; default: 0; - * Stores the 0th 32 bits of KEY1. - */ - -#define EFUSE_KEY1_DATA0 0xFFFFFFFF -#define EFUSE_KEY1_DATA0_M (EFUSE_KEY1_DATA0_V << EFUSE_KEY1_DATA0_S) -#define EFUSE_KEY1_DATA0_V 0xFFFFFFFF -#define EFUSE_KEY1_DATA0_S 0 - -/* EFUSE_RD_KEY1_DATA1_REG register - * Register 1 of BLOCK5 (KEY1). - */ - -#define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0xc0) - -/* EFUSE_KEY1_DATA1 : RO; bitpos: [31:0]; default: 0; - * Stores the 1th 32 bits of KEY1. - */ - -#define EFUSE_KEY1_DATA1 0xFFFFFFFF -#define EFUSE_KEY1_DATA1_M (EFUSE_KEY1_DATA1_V << EFUSE_KEY1_DATA1_S) -#define EFUSE_KEY1_DATA1_V 0xFFFFFFFF -#define EFUSE_KEY1_DATA1_S 0 - -/* EFUSE_RD_KEY1_DATA2_REG register - * Register 2 of BLOCK5 (KEY1). - */ - -#define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0xc4) - -/* EFUSE_KEY1_DATA2 : RO; bitpos: [31:0]; default: 0; - * Stores the 2th 32 bits of KEY1. - */ - -#define EFUSE_KEY1_DATA2 0xFFFFFFFF -#define EFUSE_KEY1_DATA2_M (EFUSE_KEY1_DATA2_V << EFUSE_KEY1_DATA2_S) -#define EFUSE_KEY1_DATA2_V 0xFFFFFFFF -#define EFUSE_KEY1_DATA2_S 0 - -/* EFUSE_RD_KEY1_DATA3_REG register - * Register 3 of BLOCK5 (KEY1). - */ - -#define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0xc8) - -/* EFUSE_KEY1_DATA3 : RO; bitpos: [31:0]; default: 0; - * Stores the 3th 32 bits of KEY1. - */ - -#define EFUSE_KEY1_DATA3 0xFFFFFFFF -#define EFUSE_KEY1_DATA3_M (EFUSE_KEY1_DATA3_V << EFUSE_KEY1_DATA3_S) -#define EFUSE_KEY1_DATA3_V 0xFFFFFFFF -#define EFUSE_KEY1_DATA3_S 0 - -/* EFUSE_RD_KEY1_DATA4_REG register - * Register 4 of BLOCK5 (KEY1). - */ - -#define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0xcc) - -/* EFUSE_KEY1_DATA4 : RO; bitpos: [31:0]; default: 0; - * Stores the 4th 32 bits of KEY1. - */ - -#define EFUSE_KEY1_DATA4 0xFFFFFFFF -#define EFUSE_KEY1_DATA4_M (EFUSE_KEY1_DATA4_V << EFUSE_KEY1_DATA4_S) -#define EFUSE_KEY1_DATA4_V 0xFFFFFFFF -#define EFUSE_KEY1_DATA4_S 0 - -/* EFUSE_RD_KEY1_DATA5_REG register - * Register 5 of BLOCK5 (KEY1). - */ - -#define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0xd0) - -/* EFUSE_KEY1_DATA5 : RO; bitpos: [31:0]; default: 0; - * Stores the 5th 32 bits of KEY1. - */ - -#define EFUSE_KEY1_DATA5 0xFFFFFFFF -#define EFUSE_KEY1_DATA5_M (EFUSE_KEY1_DATA5_V << EFUSE_KEY1_DATA5_S) -#define EFUSE_KEY1_DATA5_V 0xFFFFFFFF -#define EFUSE_KEY1_DATA5_S 0 - -/* EFUSE_RD_KEY1_DATA6_REG register - * Register 6 of BLOCK5 (KEY1). - */ - -#define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0xd4) - -/* EFUSE_KEY1_DATA6 : RO; bitpos: [31:0]; default: 0; - * Stores the 6th 32 bits of KEY1. - */ - -#define EFUSE_KEY1_DATA6 0xFFFFFFFF -#define EFUSE_KEY1_DATA6_M (EFUSE_KEY1_DATA6_V << EFUSE_KEY1_DATA6_S) -#define EFUSE_KEY1_DATA6_V 0xFFFFFFFF -#define EFUSE_KEY1_DATA6_S 0 - -/* EFUSE_RD_KEY1_DATA7_REG register - * Register 7 of BLOCK5 (KEY1). - */ - -#define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0xd8) - -/* EFUSE_KEY1_DATA7 : RO; bitpos: [31:0]; default: 0; - * Stores the 7th 32 bits of KEY1. - */ - -#define EFUSE_KEY1_DATA7 0xFFFFFFFF -#define EFUSE_KEY1_DATA7_M (EFUSE_KEY1_DATA7_V << EFUSE_KEY1_DATA7_S) -#define EFUSE_KEY1_DATA7_V 0xFFFFFFFF -#define EFUSE_KEY1_DATA7_S 0 - -/* EFUSE_RD_KEY2_DATA0_REG register - * Register 0 of BLOCK6 (KEY2). - */ - -#define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0xdc) - -/* EFUSE_KEY2_DATA0 : RO; bitpos: [31:0]; default: 0; - * Stores the 0th 32 bits of KEY2. - */ - -#define EFUSE_KEY2_DATA0 0xFFFFFFFF -#define EFUSE_KEY2_DATA0_M (EFUSE_KEY2_DATA0_V << EFUSE_KEY2_DATA0_S) -#define EFUSE_KEY2_DATA0_V 0xFFFFFFFF -#define EFUSE_KEY2_DATA0_S 0 - -/* EFUSE_RD_KEY2_DATA1_REG register - * Register 1 of BLOCK6 (KEY2). - */ - -#define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0xe0) - -/* EFUSE_KEY2_DATA1 : RO; bitpos: [31:0]; default: 0; - * Stores the 1th 32 bits of KEY2. - */ - -#define EFUSE_KEY2_DATA1 0xFFFFFFFF -#define EFUSE_KEY2_DATA1_M (EFUSE_KEY2_DATA1_V << EFUSE_KEY2_DATA1_S) -#define EFUSE_KEY2_DATA1_V 0xFFFFFFFF -#define EFUSE_KEY2_DATA1_S 0 - -/* EFUSE_RD_KEY2_DATA2_REG register - * Register 2 of BLOCK6 (KEY2). - */ - -#define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0xe4) - -/* EFUSE_KEY2_DATA2 : RO; bitpos: [31:0]; default: 0; - * Stores the 2th 32 bits of KEY2. - */ - -#define EFUSE_KEY2_DATA2 0xFFFFFFFF -#define EFUSE_KEY2_DATA2_M (EFUSE_KEY2_DATA2_V << EFUSE_KEY2_DATA2_S) -#define EFUSE_KEY2_DATA2_V 0xFFFFFFFF -#define EFUSE_KEY2_DATA2_S 0 - -/* EFUSE_RD_KEY2_DATA3_REG register - * Register 3 of BLOCK6 (KEY2). - */ - -#define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0xe8) - -/* EFUSE_KEY2_DATA3 : RO; bitpos: [31:0]; default: 0; - * Stores the 3th 32 bits of KEY2. - */ - -#define EFUSE_KEY2_DATA3 0xFFFFFFFF -#define EFUSE_KEY2_DATA3_M (EFUSE_KEY2_DATA3_V << EFUSE_KEY2_DATA3_S) -#define EFUSE_KEY2_DATA3_V 0xFFFFFFFF -#define EFUSE_KEY2_DATA3_S 0 - -/* EFUSE_RD_KEY2_DATA4_REG register - * Register 4 of BLOCK6 (KEY2). - */ - -#define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0xec) - -/* EFUSE_KEY2_DATA4 : RO; bitpos: [31:0]; default: 0; - * Stores the 4th 32 bits of KEY2. - */ - -#define EFUSE_KEY2_DATA4 0xFFFFFFFF -#define EFUSE_KEY2_DATA4_M (EFUSE_KEY2_DATA4_V << EFUSE_KEY2_DATA4_S) -#define EFUSE_KEY2_DATA4_V 0xFFFFFFFF -#define EFUSE_KEY2_DATA4_S 0 - -/* EFUSE_RD_KEY2_DATA5_REG register - * Register 5 of BLOCK6 (KEY2). - */ - -#define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0xf0) - -/* EFUSE_KEY2_DATA5 : RO; bitpos: [31:0]; default: 0; - * Stores the 5th 32 bits of KEY2. - */ - -#define EFUSE_KEY2_DATA5 0xFFFFFFFF -#define EFUSE_KEY2_DATA5_M (EFUSE_KEY2_DATA5_V << EFUSE_KEY2_DATA5_S) -#define EFUSE_KEY2_DATA5_V 0xFFFFFFFF -#define EFUSE_KEY2_DATA5_S 0 - -/* EFUSE_RD_KEY2_DATA6_REG register - * Register 6 of BLOCK6 (KEY2). - */ - -#define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0xf4) - -/* EFUSE_KEY2_DATA6 : RO; bitpos: [31:0]; default: 0; - * Stores the 6th 32 bits of KEY2. - */ - -#define EFUSE_KEY2_DATA6 0xFFFFFFFF -#define EFUSE_KEY2_DATA6_M (EFUSE_KEY2_DATA6_V << EFUSE_KEY2_DATA6_S) -#define EFUSE_KEY2_DATA6_V 0xFFFFFFFF -#define EFUSE_KEY2_DATA6_S 0 - -/* EFUSE_RD_KEY2_DATA7_REG register - * Register 7 of BLOCK6 (KEY2). - */ - -#define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0xf8) - -/* EFUSE_KEY2_DATA7 : RO; bitpos: [31:0]; default: 0; - * Stores the 7th 32 bits of KEY2. - */ - -#define EFUSE_KEY2_DATA7 0xFFFFFFFF -#define EFUSE_KEY2_DATA7_M (EFUSE_KEY2_DATA7_V << EFUSE_KEY2_DATA7_S) -#define EFUSE_KEY2_DATA7_V 0xFFFFFFFF -#define EFUSE_KEY2_DATA7_S 0 - -/* EFUSE_RD_KEY3_DATA0_REG register - * Register 0 of BLOCK7 (KEY3). - */ - -#define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0xfc) - -/* EFUSE_KEY3_DATA0 : RO; bitpos: [31:0]; default: 0; - * Stores the 0th 32 bits of KEY3. - */ - -#define EFUSE_KEY3_DATA0 0xFFFFFFFF -#define EFUSE_KEY3_DATA0_M (EFUSE_KEY3_DATA0_V << EFUSE_KEY3_DATA0_S) -#define EFUSE_KEY3_DATA0_V 0xFFFFFFFF -#define EFUSE_KEY3_DATA0_S 0 - -/* EFUSE_RD_KEY3_DATA1_REG register - * Register 1 of BLOCK7 (KEY3). - */ - -#define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE_BASE + 0x100) - -/* EFUSE_KEY3_DATA1 : RO; bitpos: [31:0]; default: 0; - * Stores the 1th 32 bits of KEY3. - */ - -#define EFUSE_KEY3_DATA1 0xFFFFFFFF -#define EFUSE_KEY3_DATA1_M (EFUSE_KEY3_DATA1_V << EFUSE_KEY3_DATA1_S) -#define EFUSE_KEY3_DATA1_V 0xFFFFFFFF -#define EFUSE_KEY3_DATA1_S 0 - -/* EFUSE_RD_KEY3_DATA2_REG register - * Register 2 of BLOCK7 (KEY3). - */ - -#define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE_BASE + 0x104) - -/* EFUSE_KEY3_DATA2 : RO; bitpos: [31:0]; default: 0; - * Stores the 2th 32 bits of KEY3. - */ - -#define EFUSE_KEY3_DATA2 0xFFFFFFFF -#define EFUSE_KEY3_DATA2_M (EFUSE_KEY3_DATA2_V << EFUSE_KEY3_DATA2_S) -#define EFUSE_KEY3_DATA2_V 0xFFFFFFFF -#define EFUSE_KEY3_DATA2_S 0 - -/* EFUSE_RD_KEY3_DATA3_REG register - * Register 3 of BLOCK7 (KEY3). - */ - -#define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE_BASE + 0x108) - -/* EFUSE_KEY3_DATA3 : RO; bitpos: [31:0]; default: 0; - * Stores the 3th 32 bits of KEY3. - */ - -#define EFUSE_KEY3_DATA3 0xFFFFFFFF -#define EFUSE_KEY3_DATA3_M (EFUSE_KEY3_DATA3_V << EFUSE_KEY3_DATA3_S) -#define EFUSE_KEY3_DATA3_V 0xFFFFFFFF -#define EFUSE_KEY3_DATA3_S 0 - -/* EFUSE_RD_KEY3_DATA4_REG register - * Register 4 of BLOCK7 (KEY3). - */ - -#define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE_BASE + 0x10c) - -/* EFUSE_KEY3_DATA4 : RO; bitpos: [31:0]; default: 0; - * Stores the 4th 32 bits of KEY3. - */ - -#define EFUSE_KEY3_DATA4 0xFFFFFFFF -#define EFUSE_KEY3_DATA4_M (EFUSE_KEY3_DATA4_V << EFUSE_KEY3_DATA4_S) -#define EFUSE_KEY3_DATA4_V 0xFFFFFFFF -#define EFUSE_KEY3_DATA4_S 0 - -/* EFUSE_RD_KEY3_DATA5_REG register - * Register 5 of BLOCK7 (KEY3). - */ - -#define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE_BASE + 0x110) - -/* EFUSE_KEY3_DATA5 : RO; bitpos: [31:0]; default: 0; - * Stores the 5th 32 bits of KEY3. - */ - -#define EFUSE_KEY3_DATA5 0xFFFFFFFF -#define EFUSE_KEY3_DATA5_M (EFUSE_KEY3_DATA5_V << EFUSE_KEY3_DATA5_S) -#define EFUSE_KEY3_DATA5_V 0xFFFFFFFF -#define EFUSE_KEY3_DATA5_S 0 - -/* EFUSE_RD_KEY3_DATA6_REG register - * Register 6 of BLOCK7 (KEY3). - */ - -#define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE_BASE + 0x114) - -/* EFUSE_KEY3_DATA6 : RO; bitpos: [31:0]; default: 0; - * Stores the 6th 32 bits of KEY3. - */ - -#define EFUSE_KEY3_DATA6 0xFFFFFFFF -#define EFUSE_KEY3_DATA6_M (EFUSE_KEY3_DATA6_V << EFUSE_KEY3_DATA6_S) -#define EFUSE_KEY3_DATA6_V 0xFFFFFFFF -#define EFUSE_KEY3_DATA6_S 0 - -/* EFUSE_RD_KEY3_DATA7_REG register - * Register 7 of BLOCK7 (KEY3). - */ - -#define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE_BASE + 0x118) - -/* EFUSE_KEY3_DATA7 : RO; bitpos: [31:0]; default: 0; - * Stores the 7th 32 bits of KEY3. - */ - -#define EFUSE_KEY3_DATA7 0xFFFFFFFF -#define EFUSE_KEY3_DATA7_M (EFUSE_KEY3_DATA7_V << EFUSE_KEY3_DATA7_S) -#define EFUSE_KEY3_DATA7_V 0xFFFFFFFF -#define EFUSE_KEY3_DATA7_S 0 - -/* EFUSE_RD_KEY4_DATA0_REG register - * Register 0 of BLOCK8 (KEY4). - */ - -#define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE_BASE + 0x11c) - -/* EFUSE_KEY4_DATA0 : RO; bitpos: [31:0]; default: 0; - * Stores the 0th 32 bits of KEY4. - */ - -#define EFUSE_KEY4_DATA0 0xFFFFFFFF -#define EFUSE_KEY4_DATA0_M (EFUSE_KEY4_DATA0_V << EFUSE_KEY4_DATA0_S) -#define EFUSE_KEY4_DATA0_V 0xFFFFFFFF -#define EFUSE_KEY4_DATA0_S 0 - -/* EFUSE_RD_KEY4_DATA1_REG register - * Register 1 of BLOCK8 (KEY4). - */ - -#define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE_BASE + 0x120) - -/* EFUSE_KEY4_DATA1 : RO; bitpos: [31:0]; default: 0; - * Stores the 1th 32 bits of KEY4. - */ - -#define EFUSE_KEY4_DATA1 0xFFFFFFFF -#define EFUSE_KEY4_DATA1_M (EFUSE_KEY4_DATA1_V << EFUSE_KEY4_DATA1_S) -#define EFUSE_KEY4_DATA1_V 0xFFFFFFFF -#define EFUSE_KEY4_DATA1_S 0 - -/* EFUSE_RD_KEY4_DATA2_REG register - * Register 2 of BLOCK8 (KEY4). - */ - -#define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE_BASE + 0x124) - -/* EFUSE_KEY4_DATA2 : RO; bitpos: [31:0]; default: 0; - * Stores the 2th 32 bits of KEY4. - */ - -#define EFUSE_KEY4_DATA2 0xFFFFFFFF -#define EFUSE_KEY4_DATA2_M (EFUSE_KEY4_DATA2_V << EFUSE_KEY4_DATA2_S) -#define EFUSE_KEY4_DATA2_V 0xFFFFFFFF -#define EFUSE_KEY4_DATA2_S 0 - -/* EFUSE_RD_KEY4_DATA3_REG register - * Register 3 of BLOCK8 (KEY4). - */ - -#define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE_BASE + 0x128) - -/* EFUSE_KEY4_DATA3 : RO; bitpos: [31:0]; default: 0; - * Stores the 3th 32 bits of KEY4. - */ - -#define EFUSE_KEY4_DATA3 0xFFFFFFFF -#define EFUSE_KEY4_DATA3_M (EFUSE_KEY4_DATA3_V << EFUSE_KEY4_DATA3_S) -#define EFUSE_KEY4_DATA3_V 0xFFFFFFFF -#define EFUSE_KEY4_DATA3_S 0 - -/* EFUSE_RD_KEY4_DATA4_REG register - * Register 4 of BLOCK8 (KEY4). - */ - -#define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE_BASE + 0x12c) - -/* EFUSE_KEY4_DATA4 : RO; bitpos: [31:0]; default: 0; - * Stores the 4th 32 bits of KEY4. - */ - -#define EFUSE_KEY4_DATA4 0xFFFFFFFF -#define EFUSE_KEY4_DATA4_M (EFUSE_KEY4_DATA4_V << EFUSE_KEY4_DATA4_S) -#define EFUSE_KEY4_DATA4_V 0xFFFFFFFF -#define EFUSE_KEY4_DATA4_S 0 - -/* EFUSE_RD_KEY4_DATA5_REG register - * Register 5 of BLOCK8 (KEY4). - */ - -#define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE_BASE + 0x130) - -/* EFUSE_KEY4_DATA5 : RO; bitpos: [31:0]; default: 0; - * Stores the 5th 32 bits of KEY4. - */ - -#define EFUSE_KEY4_DATA5 0xFFFFFFFF -#define EFUSE_KEY4_DATA5_M (EFUSE_KEY4_DATA5_V << EFUSE_KEY4_DATA5_S) -#define EFUSE_KEY4_DATA5_V 0xFFFFFFFF -#define EFUSE_KEY4_DATA5_S 0 - -/* EFUSE_RD_KEY4_DATA6_REG register - * Register 6 of BLOCK8 (KEY4). - */ - -#define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE_BASE + 0x134) - -/* EFUSE_KEY4_DATA6 : RO; bitpos: [31:0]; default: 0; - * Stores the 6th 32 bits of KEY4. - */ - -#define EFUSE_KEY4_DATA6 0xFFFFFFFF -#define EFUSE_KEY4_DATA6_M (EFUSE_KEY4_DATA6_V << EFUSE_KEY4_DATA6_S) -#define EFUSE_KEY4_DATA6_V 0xFFFFFFFF -#define EFUSE_KEY4_DATA6_S 0 - -/* EFUSE_RD_KEY4_DATA7_REG register - * Register 7 of BLOCK8 (KEY4). - */ - -#define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE_BASE + 0x138) - -/* EFUSE_KEY4_DATA7 : RO; bitpos: [31:0]; default: 0; - * Stores the 7th 32 bits of KEY4. - */ - -#define EFUSE_KEY4_DATA7 0xFFFFFFFF -#define EFUSE_KEY4_DATA7_M (EFUSE_KEY4_DATA7_V << EFUSE_KEY4_DATA7_S) -#define EFUSE_KEY4_DATA7_V 0xFFFFFFFF -#define EFUSE_KEY4_DATA7_S 0 - -/* EFUSE_RD_KEY5_DATA0_REG register - * Register 0 of BLOCK9 (KEY5). - */ - -#define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE_BASE + 0x13c) - -/* EFUSE_KEY5_DATA0 : RO; bitpos: [31:0]; default: 0; - * Stores the 0th 32 bits of KEY5. - */ - -#define EFUSE_KEY5_DATA0 0xFFFFFFFF -#define EFUSE_KEY5_DATA0_M (EFUSE_KEY5_DATA0_V << EFUSE_KEY5_DATA0_S) -#define EFUSE_KEY5_DATA0_V 0xFFFFFFFF -#define EFUSE_KEY5_DATA0_S 0 - -/* EFUSE_RD_KEY5_DATA1_REG register - * Register 1 of BLOCK9 (KEY5). - */ - -#define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE_BASE + 0x140) - -/* EFUSE_KEY5_DATA1 : RO; bitpos: [31:0]; default: 0; - * Stores the 1th 32 bits of KEY5. - */ - -#define EFUSE_KEY5_DATA1 0xFFFFFFFF -#define EFUSE_KEY5_DATA1_M (EFUSE_KEY5_DATA1_V << EFUSE_KEY5_DATA1_S) -#define EFUSE_KEY5_DATA1_V 0xFFFFFFFF -#define EFUSE_KEY5_DATA1_S 0 - -/* EFUSE_RD_KEY5_DATA2_REG register - * Register 2 of BLOCK9 (KEY5). - */ - -#define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE_BASE + 0x144) - -/* EFUSE_KEY5_DATA2 : RO; bitpos: [31:0]; default: 0; - * Stores the 2th 32 bits of KEY5. - */ - -#define EFUSE_KEY5_DATA2 0xFFFFFFFF -#define EFUSE_KEY5_DATA2_M (EFUSE_KEY5_DATA2_V << EFUSE_KEY5_DATA2_S) -#define EFUSE_KEY5_DATA2_V 0xFFFFFFFF -#define EFUSE_KEY5_DATA2_S 0 - -/* EFUSE_RD_KEY5_DATA3_REG register - * Register 3 of BLOCK9 (KEY5). - */ - -#define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE_BASE + 0x148) - -/* EFUSE_KEY5_DATA3 : RO; bitpos: [31:0]; default: 0; - * Stores the 3th 32 bits of KEY5. - */ - -#define EFUSE_KEY5_DATA3 0xFFFFFFFF -#define EFUSE_KEY5_DATA3_M (EFUSE_KEY5_DATA3_V << EFUSE_KEY5_DATA3_S) -#define EFUSE_KEY5_DATA3_V 0xFFFFFFFF -#define EFUSE_KEY5_DATA3_S 0 - -/* EFUSE_RD_KEY5_DATA4_REG register - * Register 4 of BLOCK9 (KEY5). - */ - -#define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE_BASE + 0x14c) - -/* EFUSE_KEY5_DATA4 : RO; bitpos: [31:0]; default: 0; - * Stores the 4th 32 bits of KEY5. - */ - -#define EFUSE_KEY5_DATA4 0xFFFFFFFF -#define EFUSE_KEY5_DATA4_M (EFUSE_KEY5_DATA4_V << EFUSE_KEY5_DATA4_S) -#define EFUSE_KEY5_DATA4_V 0xFFFFFFFF -#define EFUSE_KEY5_DATA4_S 0 - -/* EFUSE_RD_KEY5_DATA5_REG register - * Register 5 of BLOCK9 (KEY5). - */ - -#define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE_BASE + 0x150) - -/* EFUSE_KEY5_DATA5 : RO; bitpos: [31:0]; default: 0; - * Stores the 5th 32 bits of KEY5. - */ - -#define EFUSE_KEY5_DATA5 0xFFFFFFFF -#define EFUSE_KEY5_DATA5_M (EFUSE_KEY5_DATA5_V << EFUSE_KEY5_DATA5_S) -#define EFUSE_KEY5_DATA5_V 0xFFFFFFFF -#define EFUSE_KEY5_DATA5_S 0 - -/* EFUSE_RD_KEY5_DATA6_REG register - * Register 6 of BLOCK9 (KEY5). - */ - -#define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE_BASE + 0x154) - -/* EFUSE_KEY5_DATA6 : RO; bitpos: [31:0]; default: 0; - * Stores the 6th 32 bits of KEY5. - */ - -#define EFUSE_KEY5_DATA6 0xFFFFFFFF -#define EFUSE_KEY5_DATA6_M (EFUSE_KEY5_DATA6_V << EFUSE_KEY5_DATA6_S) -#define EFUSE_KEY5_DATA6_V 0xFFFFFFFF -#define EFUSE_KEY5_DATA6_S 0 - -/* EFUSE_RD_KEY5_DATA7_REG register - * Register 7 of BLOCK9 (KEY5). - */ - -#define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE_BASE + 0x158) - -/* EFUSE_KEY5_DATA7 : RO; bitpos: [31:0]; default: 0; - * Stores the 7th 32 bits of KEY5. - */ - -#define EFUSE_KEY5_DATA7 0xFFFFFFFF -#define EFUSE_KEY5_DATA7_M (EFUSE_KEY5_DATA7_V << EFUSE_KEY5_DATA7_S) -#define EFUSE_KEY5_DATA7_V 0xFFFFFFFF -#define EFUSE_KEY5_DATA7_S 0 - -/* EFUSE_RD_SYS_DATA_PART2_0_REG register - * Register 0 of BLOCK10 (system). - */ - -#define EFUSE_RD_SYS_DATA_PART2_0_REG (DR_REG_EFUSE_BASE + 0x15c) - -/* EFUSE_SYS_DATA_PART2_0 : RO; bitpos: [31:0]; default: 0; - * Stores the 0th 32 bits of the 2nd part of system data. - */ - -#define EFUSE_SYS_DATA_PART2_0 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_0_M (EFUSE_SYS_DATA_PART2_0_V << EFUSE_SYS_DATA_PART2_0_S) -#define EFUSE_SYS_DATA_PART2_0_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_0_S 0 - -/* EFUSE_RD_SYS_DATA_PART2_1_REG register - * Register 1 of BLOCK10 (system). - */ - -#define EFUSE_RD_SYS_DATA_PART2_1_REG (DR_REG_EFUSE_BASE + 0x160) - -/* EFUSE_SYS_DATA_PART2_1 : RO; bitpos: [31:0]; default: 0; - * Stores the 1th 32 bits of the 2nd part of system data. - */ - -#define EFUSE_SYS_DATA_PART2_1 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_1_M (EFUSE_SYS_DATA_PART2_1_V << EFUSE_SYS_DATA_PART2_1_S) -#define EFUSE_SYS_DATA_PART2_1_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_1_S 0 - -/* EFUSE_RD_SYS_DATA_PART2_2_REG register - * Register 2 of BLOCK10 (system). - */ - -#define EFUSE_RD_SYS_DATA_PART2_2_REG (DR_REG_EFUSE_BASE + 0x164) - -/* EFUSE_SYS_DATA_PART2_2 : RO; bitpos: [31:0]; default: 0; - * Stores the 2th 32 bits of the 2nd part of system data. - */ - -#define EFUSE_SYS_DATA_PART2_2 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_2_M (EFUSE_SYS_DATA_PART2_2_V << EFUSE_SYS_DATA_PART2_2_S) -#define EFUSE_SYS_DATA_PART2_2_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_2_S 0 - -/* EFUSE_RD_SYS_DATA_PART2_3_REG register - * Register 3 of BLOCK10 (system). - */ - -#define EFUSE_RD_SYS_DATA_PART2_3_REG (DR_REG_EFUSE_BASE + 0x168) - -/* EFUSE_SYS_DATA_PART2_3 : RO; bitpos: [31:0]; default: 0; - * Stores the 3th 32 bits of the 2nd part of system data. - */ - -#define EFUSE_SYS_DATA_PART2_3 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_3_M (EFUSE_SYS_DATA_PART2_3_V << EFUSE_SYS_DATA_PART2_3_S) -#define EFUSE_SYS_DATA_PART2_3_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_3_S 0 - -/* EFUSE_RD_SYS_DATA_PART2_4_REG register - * Register 4 of BLOCK10 (system). - */ - -#define EFUSE_RD_SYS_DATA_PART2_4_REG (DR_REG_EFUSE_BASE + 0x16c) - -/* EFUSE_SYS_DATA_PART2_4 : RO; bitpos: [31:0]; default: 0; - * Stores the 4th 32 bits of the 2nd part of system data. - */ - -#define EFUSE_SYS_DATA_PART2_4 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_4_M (EFUSE_SYS_DATA_PART2_4_V << EFUSE_SYS_DATA_PART2_4_S) -#define EFUSE_SYS_DATA_PART2_4_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_4_S 0 - -/* EFUSE_RD_SYS_DATA_PART2_5_REG register - * Register 5 of BLOCK10 (system). - */ - -#define EFUSE_RD_SYS_DATA_PART2_5_REG (DR_REG_EFUSE_BASE + 0x170) - -/* EFUSE_SYS_DATA_PART2_5 : RO; bitpos: [31:0]; default: 0; - * Stores the 5th 32 bits of the 2nd part of system data. - */ - -#define EFUSE_SYS_DATA_PART2_5 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_5_M (EFUSE_SYS_DATA_PART2_5_V << EFUSE_SYS_DATA_PART2_5_S) -#define EFUSE_SYS_DATA_PART2_5_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_5_S 0 - -/* EFUSE_RD_SYS_DATA_PART2_6_REG register - * Register 6 of BLOCK10 (system). - */ - -#define EFUSE_RD_SYS_DATA_PART2_6_REG (DR_REG_EFUSE_BASE + 0x174) - -/* EFUSE_SYS_DATA_PART2_6 : RO; bitpos: [31:0]; default: 0; - * Stores the 6th 32 bits of the 2nd part of system data. - */ - -#define EFUSE_SYS_DATA_PART2_6 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_6_M (EFUSE_SYS_DATA_PART2_6_V << EFUSE_SYS_DATA_PART2_6_S) -#define EFUSE_SYS_DATA_PART2_6_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_6_S 0 - -/* EFUSE_RD_SYS_DATA_PART2_7_REG register - * Register 7 of BLOCK10 (system). - */ - -#define EFUSE_RD_SYS_DATA_PART2_7_REG (DR_REG_EFUSE_BASE + 0x178) - -/* EFUSE_SYS_DATA_PART2_7 : RO; bitpos: [31:0]; default: 0; - * Stores the 7th 32 bits of the 2nd part of system data. - */ - -#define EFUSE_SYS_DATA_PART2_7 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_7_M (EFUSE_SYS_DATA_PART2_7_V << EFUSE_SYS_DATA_PART2_7_S) -#define EFUSE_SYS_DATA_PART2_7_V 0xFFFFFFFF -#define EFUSE_SYS_DATA_PART2_7_S 0 - -/* EFUSE_RD_REPEAT_ERR0_REG register - * Programming error record register 0 of BLOCK0. - */ - -#define EFUSE_RD_REPEAT_ERR0_REG (DR_REG_EFUSE_BASE + 0x17c) - -/* EFUSE_VDD_SPI_DREFH_ERR : RO; bitpos: [31:30]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_VDD_SPI_DREFH. - */ - -#define EFUSE_VDD_SPI_DREFH_ERR 0x00000003 -#define EFUSE_VDD_SPI_DREFH_ERR_M (EFUSE_VDD_SPI_DREFH_ERR_V << EFUSE_VDD_SPI_DREFH_ERR_S) -#define EFUSE_VDD_SPI_DREFH_ERR_V 0x00000003 -#define EFUSE_VDD_SPI_DREFH_ERR_S 30 - -/* EFUSE_VDD_SPI_MODECURLIM_ERR : RO; bitpos: [29]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_VDD_SPI_MODECURLIM. - */ - -#define EFUSE_VDD_SPI_MODECURLIM_ERR (BIT(29)) -#define EFUSE_VDD_SPI_MODECURLIM_ERR_M (EFUSE_VDD_SPI_MODECURLIM_ERR_V << EFUSE_VDD_SPI_MODECURLIM_ERR_S) -#define EFUSE_VDD_SPI_MODECURLIM_ERR_V 0x00000001 -#define EFUSE_VDD_SPI_MODECURLIM_ERR_S 29 - -/* EFUSE_RPT4_RESERVED0_ERR : RO; bitpos: [28:27]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_RPT4_RESERVED0. - */ - -#define EFUSE_RPT4_RESERVED0_ERR 0x00000003 -#define EFUSE_RPT4_RESERVED0_ERR_M (EFUSE_RPT4_RESERVED0_ERR_V << EFUSE_RPT4_RESERVED0_ERR_S) -#define EFUSE_RPT4_RESERVED0_ERR_V 0x00000003 -#define EFUSE_RPT4_RESERVED0_ERR_S 27 - -/* EFUSE_USB_FORCE_NOPERSIST_ERR : RO; bitpos: [26]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_USB_FORCE_NOPERSIST. - */ - -#define EFUSE_USB_FORCE_NOPERSIST_ERR (BIT(26)) -#define EFUSE_USB_FORCE_NOPERSIST_ERR_M (EFUSE_USB_FORCE_NOPERSIST_ERR_V << EFUSE_USB_FORCE_NOPERSIST_ERR_S) -#define EFUSE_USB_FORCE_NOPERSIST_ERR_V 0x00000001 -#define EFUSE_USB_FORCE_NOPERSIST_ERR_S 26 - -/* EFUSE_EXT_PHY_ENABLE_ERR : RO; bitpos: [25]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_EXT_PHY_ENABLE. - */ - -#define EFUSE_EXT_PHY_ENABLE_ERR (BIT(25)) -#define EFUSE_EXT_PHY_ENABLE_ERR_M (EFUSE_EXT_PHY_ENABLE_ERR_V << EFUSE_EXT_PHY_ENABLE_ERR_S) -#define EFUSE_EXT_PHY_ENABLE_ERR_V 0x00000001 -#define EFUSE_EXT_PHY_ENABLE_ERR_S 25 - -/* EFUSE_USB_EXCHG_PINS_ERR : RO; bitpos: [24]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_USB_EXCHG_PINS. - */ - -#define EFUSE_USB_EXCHG_PINS_ERR (BIT(24)) -#define EFUSE_USB_EXCHG_PINS_ERR_M (EFUSE_USB_EXCHG_PINS_ERR_V << EFUSE_USB_EXCHG_PINS_ERR_S) -#define EFUSE_USB_EXCHG_PINS_ERR_V 0x00000001 -#define EFUSE_USB_EXCHG_PINS_ERR_S 24 - -/* EFUSE_USB_DREFL_ERR : RO; bitpos: [23:22]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_USB_DREFL. - */ - -#define EFUSE_USB_DREFL_ERR 0x00000003 -#define EFUSE_USB_DREFL_ERR_M (EFUSE_USB_DREFL_ERR_V << EFUSE_USB_DREFL_ERR_S) -#define EFUSE_USB_DREFL_ERR_V 0x00000003 -#define EFUSE_USB_DREFL_ERR_S 22 - -/* EFUSE_USB_DREFH_ERR : RO; bitpos: [21:20]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_USB_DREFH. - */ - -#define EFUSE_USB_DREFH_ERR 0x00000003 -#define EFUSE_USB_DREFH_ERR_M (EFUSE_USB_DREFH_ERR_V << EFUSE_USB_DREFH_ERR_S) -#define EFUSE_USB_DREFH_ERR_V 0x00000003 -#define EFUSE_USB_DREFH_ERR_S 20 - -/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO; bitpos: [19]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT. - */ - -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR (BIT(19)) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V 0x00000001 -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S 19 - -/* EFUSE_HARD_DIS_JTAG_ERR : RO; bitpos: [18]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_HARD_DIS_JTAG. - */ - -#define EFUSE_HARD_DIS_JTAG_ERR (BIT(18)) -#define EFUSE_HARD_DIS_JTAG_ERR_M (EFUSE_HARD_DIS_JTAG_ERR_V << EFUSE_HARD_DIS_JTAG_ERR_S) -#define EFUSE_HARD_DIS_JTAG_ERR_V 0x00000001 -#define EFUSE_HARD_DIS_JTAG_ERR_S 18 - -/* EFUSE_SOFT_DIS_JTAG_ERR : RO; bitpos: [17]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_SOFT_DIS_JTAG. - */ - -#define EFUSE_SOFT_DIS_JTAG_ERR (BIT(17)) -#define EFUSE_SOFT_DIS_JTAG_ERR_M (EFUSE_SOFT_DIS_JTAG_ERR_V << EFUSE_SOFT_DIS_JTAG_ERR_S) -#define EFUSE_SOFT_DIS_JTAG_ERR_V 0x00000001 -#define EFUSE_SOFT_DIS_JTAG_ERR_S 17 - -/* EFUSE_DIS_EFUSE_ATE_WR_ERR : RO; bitpos: [16]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_DIS_EFUSE_ATE_WR. - */ - -#define EFUSE_DIS_EFUSE_ATE_WR_ERR (BIT(16)) -#define EFUSE_DIS_EFUSE_ATE_WR_ERR_M (EFUSE_DIS_EFUSE_ATE_WR_ERR_V << EFUSE_DIS_EFUSE_ATE_WR_ERR_S) -#define EFUSE_DIS_EFUSE_ATE_WR_ERR_V 0x00000001 -#define EFUSE_DIS_EFUSE_ATE_WR_ERR_S 16 - -/* EFUSE_DIS_BOOT_REMAP_ERR : RO; bitpos: [15]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_DIS_BOOT_REMAP. - */ - -#define EFUSE_DIS_BOOT_REMAP_ERR (BIT(15)) -#define EFUSE_DIS_BOOT_REMAP_ERR_M (EFUSE_DIS_BOOT_REMAP_ERR_V << EFUSE_DIS_BOOT_REMAP_ERR_S) -#define EFUSE_DIS_BOOT_REMAP_ERR_V 0x00000001 -#define EFUSE_DIS_BOOT_REMAP_ERR_S 15 - -/* EFUSE_DIS_CAN_ERR : RO; bitpos: [14]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_DIS_CAN. - */ - -#define EFUSE_DIS_CAN_ERR (BIT(14)) -#define EFUSE_DIS_CAN_ERR_M (EFUSE_DIS_CAN_ERR_V << EFUSE_DIS_CAN_ERR_S) -#define EFUSE_DIS_CAN_ERR_V 0x00000001 -#define EFUSE_DIS_CAN_ERR_S 14 - -/* EFUSE_DIS_USB_ERR : RO; bitpos: [13]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_DIS_USB. - */ - -#define EFUSE_DIS_USB_ERR (BIT(13)) -#define EFUSE_DIS_USB_ERR_M (EFUSE_DIS_USB_ERR_V << EFUSE_DIS_USB_ERR_S) -#define EFUSE_DIS_USB_ERR_V 0x00000001 -#define EFUSE_DIS_USB_ERR_S 13 - -/* EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO; bitpos: [12]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_DIS_FORCE_DOWNLOAD. - */ - -#define EFUSE_DIS_FORCE_DOWNLOAD_ERR (BIT(12)) -#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M (EFUSE_DIS_FORCE_DOWNLOAD_ERR_V << EFUSE_DIS_FORCE_DOWNLOAD_ERR_S) -#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V 0x00000001 -#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S 12 - -/* EFUSE_DIS_DOWNLOAD_DCACHE_ERR : RO; bitpos: [11]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_DIS_DOWNLOAD_DCACHE. - */ - -#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR (BIT(11)) -#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_M (EFUSE_DIS_DOWNLOAD_DCACHE_ERR_V << EFUSE_DIS_DOWNLOAD_DCACHE_ERR_S) -#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_V 0x00000001 -#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_S 11 - -/* EFUSE_DIS_DOWNLOAD_ICACHE_ERR : RO; bitpos: [10]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_DIS_DOWNLOAD_ICACHE. - */ - -#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR (BIT(10)) -#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_M (EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V << EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S) -#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V 0x00000001 -#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S 10 - -/* EFUSE_DIS_DCACHE_ERR : RO; bitpos: [9]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_DIS_DCACHE. - */ - -#define EFUSE_DIS_DCACHE_ERR (BIT(9)) -#define EFUSE_DIS_DCACHE_ERR_M (EFUSE_DIS_DCACHE_ERR_V << EFUSE_DIS_DCACHE_ERR_S) -#define EFUSE_DIS_DCACHE_ERR_V 0x00000001 -#define EFUSE_DIS_DCACHE_ERR_S 9 - -/* EFUSE_DIS_ICACHE_ERR : RO; bitpos: [8]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_DIS_ICACHE. - */ - -#define EFUSE_DIS_ICACHE_ERR (BIT(8)) -#define EFUSE_DIS_ICACHE_ERR_M (EFUSE_DIS_ICACHE_ERR_V << EFUSE_DIS_ICACHE_ERR_S) -#define EFUSE_DIS_ICACHE_ERR_V 0x00000001 -#define EFUSE_DIS_ICACHE_ERR_S 8 - -/* EFUSE_DIS_RTC_RAM_BOOT_ERR : RO; bitpos: [7]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_DIS_RTC_RAM_BOOT. - */ - -#define EFUSE_DIS_RTC_RAM_BOOT_ERR (BIT(7)) -#define EFUSE_DIS_RTC_RAM_BOOT_ERR_M (EFUSE_DIS_RTC_RAM_BOOT_ERR_V << EFUSE_DIS_RTC_RAM_BOOT_ERR_S) -#define EFUSE_DIS_RTC_RAM_BOOT_ERR_V 0x00000001 -#define EFUSE_DIS_RTC_RAM_BOOT_ERR_S 7 - -/* EFUSE_RD_DIS_ERR : RO; bitpos: [6:0]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_RD_DIS. - */ - -#define EFUSE_RD_DIS_ERR 0x0000007F -#define EFUSE_RD_DIS_ERR_M (EFUSE_RD_DIS_ERR_V << EFUSE_RD_DIS_ERR_S) -#define EFUSE_RD_DIS_ERR_V 0x0000007F -#define EFUSE_RD_DIS_ERR_S 0 - -/* EFUSE_RD_REPEAT_ERR1_REG register - * Programming error record register 1 of BLOCK0. - */ - -#define EFUSE_RD_REPEAT_ERR1_REG (DR_REG_EFUSE_BASE + 0x180) - -/* EFUSE_KEY_PURPOSE_1_ERR : RO; bitpos: [31:28]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_KEY_PURPOSE_1. - */ - -#define EFUSE_KEY_PURPOSE_1_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_1_ERR_M (EFUSE_KEY_PURPOSE_1_ERR_V << EFUSE_KEY_PURPOSE_1_ERR_S) -#define EFUSE_KEY_PURPOSE_1_ERR_V 0x0000000F -#define EFUSE_KEY_PURPOSE_1_ERR_S 28 - -/* EFUSE_KEY_PURPOSE_0_ERR : RO; bitpos: [27:24]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_KEY_PURPOSE_0. - */ - -#define EFUSE_KEY_PURPOSE_0_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_0_ERR_M (EFUSE_KEY_PURPOSE_0_ERR_V << EFUSE_KEY_PURPOSE_0_ERR_S) -#define EFUSE_KEY_PURPOSE_0_ERR_V 0x0000000F -#define EFUSE_KEY_PURPOSE_0_ERR_S 24 - -/* EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO; bitpos: [23]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_SECURE_BOOT_KEY_REVOKE2. - */ - -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR (BIT(23)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V 0x00000001 -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S 23 - -/* EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO; bitpos: [22]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_SECURE_BOOT_KEY_REVOKE1. - */ - -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR (BIT(22)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V 0x00000001 -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S 22 - -/* EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO; bitpos: [21]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_SECURE_BOOT_KEY_REVOKE0. - */ - -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR (BIT(21)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V 0x00000001 -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S 21 - -/* EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO; bitpos: [20:18]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_SPI_BOOT_CRYPT_CNT. - */ - -#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR 0x00000007 -#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M (EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V << EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S) -#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V 0x00000007 -#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S 18 - -/* EFUSE_WDT_DELAY_SEL_ERR : RO; bitpos: [17:16]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_WDT_DELAY_SEL. - */ - -#define EFUSE_WDT_DELAY_SEL_ERR 0x00000003 -#define EFUSE_WDT_DELAY_SEL_ERR_M (EFUSE_WDT_DELAY_SEL_ERR_V << EFUSE_WDT_DELAY_SEL_ERR_S) -#define EFUSE_WDT_DELAY_SEL_ERR_V 0x00000003 -#define EFUSE_WDT_DELAY_SEL_ERR_S 16 - -/* EFUSE_VDD_SPI_DCAP_ERR : RO; bitpos: [15:14]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_VDD_SPI_DCAP. - */ - -#define EFUSE_VDD_SPI_DCAP_ERR 0x00000003 -#define EFUSE_VDD_SPI_DCAP_ERR_M (EFUSE_VDD_SPI_DCAP_ERR_V << EFUSE_VDD_SPI_DCAP_ERR_S) -#define EFUSE_VDD_SPI_DCAP_ERR_V 0x00000003 -#define EFUSE_VDD_SPI_DCAP_ERR_S 14 - -/* EFUSE_VDD_SPI_INIT_ERR : RO; bitpos: [13:12]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_VDD_SPI_INIT. - */ - -#define EFUSE_VDD_SPI_INIT_ERR 0x00000003 -#define EFUSE_VDD_SPI_INIT_ERR_M (EFUSE_VDD_SPI_INIT_ERR_V << EFUSE_VDD_SPI_INIT_ERR_S) -#define EFUSE_VDD_SPI_INIT_ERR_V 0x00000003 -#define EFUSE_VDD_SPI_INIT_ERR_S 12 - -/* EFUSE_VDD_SPI_DCURLIM_ERR : RO; bitpos: [11:9]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_VDD_SPI_DCURLIM. - */ - -#define EFUSE_VDD_SPI_DCURLIM_ERR 0x00000007 -#define EFUSE_VDD_SPI_DCURLIM_ERR_M (EFUSE_VDD_SPI_DCURLIM_ERR_V << EFUSE_VDD_SPI_DCURLIM_ERR_S) -#define EFUSE_VDD_SPI_DCURLIM_ERR_V 0x00000007 -#define EFUSE_VDD_SPI_DCURLIM_ERR_S 9 - -/* EFUSE_VDD_SPI_ENCURLIM_ERR : RO; bitpos: [8]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_VDD_SPI_ENCURLIM. - */ - -#define EFUSE_VDD_SPI_ENCURLIM_ERR (BIT(8)) -#define EFUSE_VDD_SPI_ENCURLIM_ERR_M (EFUSE_VDD_SPI_ENCURLIM_ERR_V << EFUSE_VDD_SPI_ENCURLIM_ERR_S) -#define EFUSE_VDD_SPI_ENCURLIM_ERR_V 0x00000001 -#define EFUSE_VDD_SPI_ENCURLIM_ERR_S 8 - -/* EFUSE_VDD_SPI_EN_INIT_ERR : RO; bitpos: [7]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_VDD_SPI_EN_INIT. - */ - -#define EFUSE_VDD_SPI_EN_INIT_ERR (BIT(7)) -#define EFUSE_VDD_SPI_EN_INIT_ERR_M (EFUSE_VDD_SPI_EN_INIT_ERR_V << EFUSE_VDD_SPI_EN_INIT_ERR_S) -#define EFUSE_VDD_SPI_EN_INIT_ERR_V 0x00000001 -#define EFUSE_VDD_SPI_EN_INIT_ERR_S 7 - -/* EFUSE_VDD_SPI_FORCE_ERR : RO; bitpos: [6]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_VDD_SPI_FORCE. - */ - -#define EFUSE_VDD_SPI_FORCE_ERR (BIT(6)) -#define EFUSE_VDD_SPI_FORCE_ERR_M (EFUSE_VDD_SPI_FORCE_ERR_V << EFUSE_VDD_SPI_FORCE_ERR_S) -#define EFUSE_VDD_SPI_FORCE_ERR_V 0x00000001 -#define EFUSE_VDD_SPI_FORCE_ERR_S 6 - -/* EFUSE_VDD_SPI_TIEH_ERR : RO; bitpos: [5]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_VDD_SPI_TIEH. - */ - -#define EFUSE_VDD_SPI_TIEH_ERR (BIT(5)) -#define EFUSE_VDD_SPI_TIEH_ERR_M (EFUSE_VDD_SPI_TIEH_ERR_V << EFUSE_VDD_SPI_TIEH_ERR_S) -#define EFUSE_VDD_SPI_TIEH_ERR_V 0x00000001 -#define EFUSE_VDD_SPI_TIEH_ERR_S 5 - -/* EFUSE_VDD_SPI_XPD_ERR : RO; bitpos: [4]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_VDD_SPI_XPD. - */ - -#define EFUSE_VDD_SPI_XPD_ERR (BIT(4)) -#define EFUSE_VDD_SPI_XPD_ERR_M (EFUSE_VDD_SPI_XPD_ERR_V << EFUSE_VDD_SPI_XPD_ERR_S) -#define EFUSE_VDD_SPI_XPD_ERR_V 0x00000001 -#define EFUSE_VDD_SPI_XPD_ERR_S 4 - -/* EFUSE_VDD_SPI_DREFL_ERR : RO; bitpos: [3:2]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_VDD_SPI_DREFL. - */ - -#define EFUSE_VDD_SPI_DREFL_ERR 0x00000003 -#define EFUSE_VDD_SPI_DREFL_ERR_M (EFUSE_VDD_SPI_DREFL_ERR_V << EFUSE_VDD_SPI_DREFL_ERR_S) -#define EFUSE_VDD_SPI_DREFL_ERR_V 0x00000003 -#define EFUSE_VDD_SPI_DREFL_ERR_S 2 - -/* EFUSE_VDD_SPI_DREFM_ERR : RO; bitpos: [1:0]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_VDD_SPI_DREFM. - */ - -#define EFUSE_VDD_SPI_DREFM_ERR 0x00000003 -#define EFUSE_VDD_SPI_DREFM_ERR_M (EFUSE_VDD_SPI_DREFM_ERR_V << EFUSE_VDD_SPI_DREFM_ERR_S) -#define EFUSE_VDD_SPI_DREFM_ERR_V 0x00000003 -#define EFUSE_VDD_SPI_DREFM_ERR_S 0 - -/* EFUSE_RD_REPEAT_ERR2_REG register - * Programming error record register 2 of BLOCK0. - */ - -#define EFUSE_RD_REPEAT_ERR2_REG (DR_REG_EFUSE_BASE + 0x184) - -/* EFUSE_FLASH_TPUW_ERR : RO; bitpos: [31:28]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_FLASH_TPUW. - */ - -#define EFUSE_FLASH_TPUW_ERR 0x0000000F -#define EFUSE_FLASH_TPUW_ERR_M (EFUSE_FLASH_TPUW_ERR_V << EFUSE_FLASH_TPUW_ERR_S) -#define EFUSE_FLASH_TPUW_ERR_V 0x0000000F -#define EFUSE_FLASH_TPUW_ERR_S 28 - -/* EFUSE_RPT4_RESERVED1_ERR : RO; bitpos: [27:22]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_RPT4_RESERVED1. - */ - -#define EFUSE_RPT4_RESERVED1_ERR 0x0000003F -#define EFUSE_RPT4_RESERVED1_ERR_M (EFUSE_RPT4_RESERVED1_ERR_V << EFUSE_RPT4_RESERVED1_ERR_S) -#define EFUSE_RPT4_RESERVED1_ERR_V 0x0000003F -#define EFUSE_RPT4_RESERVED1_ERR_S 22 - -/* EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO; bitpos: [21]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE. - */ - -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR (BIT(21)) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V 0x00000001 -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S 21 - -/* EFUSE_SECURE_BOOT_EN_ERR : RO; bitpos: [20]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_SECURE_BOOT_EN. - */ - -#define EFUSE_SECURE_BOOT_EN_ERR (BIT(20)) -#define EFUSE_SECURE_BOOT_EN_ERR_M (EFUSE_SECURE_BOOT_EN_ERR_V << EFUSE_SECURE_BOOT_EN_ERR_S) -#define EFUSE_SECURE_BOOT_EN_ERR_V 0x00000001 -#define EFUSE_SECURE_BOOT_EN_ERR_S 20 - -/* EFUSE_KEY_PURPOSE_6_ERR : RO; bitpos: [19:16]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_KEY_PURPOSE_6. - */ - -#define EFUSE_KEY_PURPOSE_6_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_6_ERR_M (EFUSE_KEY_PURPOSE_6_ERR_V << EFUSE_KEY_PURPOSE_6_ERR_S) -#define EFUSE_KEY_PURPOSE_6_ERR_V 0x0000000F -#define EFUSE_KEY_PURPOSE_6_ERR_S 16 - -/* EFUSE_KEY_PURPOSE_5_ERR : RO; bitpos: [15:12]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_KEY_PURPOSE_5. - */ - -#define EFUSE_KEY_PURPOSE_5_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_5_ERR_M (EFUSE_KEY_PURPOSE_5_ERR_V << EFUSE_KEY_PURPOSE_5_ERR_S) -#define EFUSE_KEY_PURPOSE_5_ERR_V 0x0000000F -#define EFUSE_KEY_PURPOSE_5_ERR_S 12 - -/* EFUSE_KEY_PURPOSE_4_ERR : RO; bitpos: [11:8]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_KEY_PURPOSE_4. - */ - -#define EFUSE_KEY_PURPOSE_4_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_4_ERR_M (EFUSE_KEY_PURPOSE_4_ERR_V << EFUSE_KEY_PURPOSE_4_ERR_S) -#define EFUSE_KEY_PURPOSE_4_ERR_V 0x0000000F -#define EFUSE_KEY_PURPOSE_4_ERR_S 8 - -/* EFUSE_KEY_PURPOSE_3_ERR : RO; bitpos: [7:4]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_KEY_PURPOSE_3. - */ - -#define EFUSE_KEY_PURPOSE_3_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_3_ERR_M (EFUSE_KEY_PURPOSE_3_ERR_V << EFUSE_KEY_PURPOSE_3_ERR_S) -#define EFUSE_KEY_PURPOSE_3_ERR_V 0x0000000F -#define EFUSE_KEY_PURPOSE_3_ERR_S 4 - -/* EFUSE_KEY_PURPOSE_2_ERR : RO; bitpos: [3:0]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_KEY_PURPOSE_2. - */ - -#define EFUSE_KEY_PURPOSE_2_ERR 0x0000000F -#define EFUSE_KEY_PURPOSE_2_ERR_M (EFUSE_KEY_PURPOSE_2_ERR_V << EFUSE_KEY_PURPOSE_2_ERR_S) -#define EFUSE_KEY_PURPOSE_2_ERR_V 0x0000000F -#define EFUSE_KEY_PURPOSE_2_ERR_S 0 - -/* EFUSE_RD_REPEAT_ERR3_REG register - * Programming error record register 3 of BLOCK0. - */ - -#define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188) - -/* EFUSE_RPT4_RESERVED2_ERR : RO; bitpos: [31:27]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_RPT4_RESERVED2. - */ - -#define EFUSE_RPT4_RESERVED2_ERR 0x0000001F -#define EFUSE_RPT4_RESERVED2_ERR_M (EFUSE_RPT4_RESERVED2_ERR_V << EFUSE_RPT4_RESERVED2_ERR_S) -#define EFUSE_RPT4_RESERVED2_ERR_V 0x0000001F -#define EFUSE_RPT4_RESERVED2_ERR_S 27 - -/* EFUSE_SECURE_VERSION_ERR : RO; bitpos: [26:11]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_SECURE_VERSION. - */ - -#define EFUSE_SECURE_VERSION_ERR 0x0000FFFF -#define EFUSE_SECURE_VERSION_ERR_M (EFUSE_SECURE_VERSION_ERR_V << EFUSE_SECURE_VERSION_ERR_S) -#define EFUSE_SECURE_VERSION_ERR_V 0x0000FFFF -#define EFUSE_SECURE_VERSION_ERR_S 11 - -/* EFUSE_FORCE_SEND_RESUME_ERR : RO; bitpos: [10]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_FORCE_SEND_RESUME. - */ - -#define EFUSE_FORCE_SEND_RESUME_ERR (BIT(10)) -#define EFUSE_FORCE_SEND_RESUME_ERR_M (EFUSE_FORCE_SEND_RESUME_ERR_V << EFUSE_FORCE_SEND_RESUME_ERR_S) -#define EFUSE_FORCE_SEND_RESUME_ERR_V 0x00000001 -#define EFUSE_FORCE_SEND_RESUME_ERR_S 10 - -/* EFUSE_FLASH_TYPE_ERR : RO; bitpos: [9]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_FLASH_TYPE. - */ - -#define EFUSE_FLASH_TYPE_ERR (BIT(9)) -#define EFUSE_FLASH_TYPE_ERR_M (EFUSE_FLASH_TYPE_ERR_V << EFUSE_FLASH_TYPE_ERR_S) -#define EFUSE_FLASH_TYPE_ERR_V 0x00000001 -#define EFUSE_FLASH_TYPE_ERR_S 9 - -/* EFUSE_PIN_POWER_SELECTION_ERR : RO; bitpos: [8]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_PIN_POWER_SELECTION. - */ - -#define EFUSE_PIN_POWER_SELECTION_ERR (BIT(8)) -#define EFUSE_PIN_POWER_SELECTION_ERR_M (EFUSE_PIN_POWER_SELECTION_ERR_V << EFUSE_PIN_POWER_SELECTION_ERR_S) -#define EFUSE_PIN_POWER_SELECTION_ERR_V 0x00000001 -#define EFUSE_PIN_POWER_SELECTION_ERR_S 8 - -/* EFUSE_UART_PRINT_CONTROL_ERR : RO; bitpos: [7:6]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_UART_PRINT_CONTROL. - */ - -#define EFUSE_UART_PRINT_CONTROL_ERR 0x00000003 -#define EFUSE_UART_PRINT_CONTROL_ERR_M (EFUSE_UART_PRINT_CONTROL_ERR_V << EFUSE_UART_PRINT_CONTROL_ERR_S) -#define EFUSE_UART_PRINT_CONTROL_ERR_V 0x00000003 -#define EFUSE_UART_PRINT_CONTROL_ERR_S 6 - -/* EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO; bitpos: [5]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_ENABLE_SECURITY_DOWNLOAD. - */ - -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR (BIT(5)) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V 0x00000001 -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S 5 - -/* EFUSE_DIS_USB_DOWNLOAD_MODE_ERR : RO; bitpos: [4]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_DIS_USB_DOWNLOAD_MODE. - */ - -#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR (BIT(4)) -#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_S) -#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_V 0x00000001 -#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_S 4 - -/* EFUSE_RPT4_RESERVED3_ERR : RO; bitpos: [3]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_RPT4_RESERVED3. - */ - -#define EFUSE_RPT4_RESERVED3_ERR (BIT(3)) -#define EFUSE_RPT4_RESERVED3_ERR_M (EFUSE_RPT4_RESERVED3_ERR_V << EFUSE_RPT4_RESERVED3_ERR_S) -#define EFUSE_RPT4_RESERVED3_ERR_V 0x00000001 -#define EFUSE_RPT4_RESERVED3_ERR_S 3 - -/* EFUSE_UART_PRINT_CHANNEL_ERR : RO; bitpos: [2]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_UART_PRINT_CHANNEL. - */ - -#define EFUSE_UART_PRINT_CHANNEL_ERR (BIT(2)) -#define EFUSE_UART_PRINT_CHANNEL_ERR_M (EFUSE_UART_PRINT_CHANNEL_ERR_V << EFUSE_UART_PRINT_CHANNEL_ERR_S) -#define EFUSE_UART_PRINT_CHANNEL_ERR_V 0x00000001 -#define EFUSE_UART_PRINT_CHANNEL_ERR_S 2 - -/* EFUSE_DIS_LEGACY_SPI_BOOT_ERR : RO; bitpos: [1]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_DIS_LEGACY_SPI_BOOT. - */ - -#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR (BIT(1)) -#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_M (EFUSE_DIS_LEGACY_SPI_BOOT_ERR_V << EFUSE_DIS_LEGACY_SPI_BOOT_ERR_S) -#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_V 0x00000001 -#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_S 1 - -/* EFUSE_DIS_DOWNLOAD_MODE_ERR : RO; bitpos: [0]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_DIS_DOWNLOAD_MODE. - */ - -#define EFUSE_DIS_DOWNLOAD_MODE_ERR (BIT(0)) -#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_DOWNLOAD_MODE_ERR_S) -#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V 0x00000001 -#define EFUSE_DIS_DOWNLOAD_MODE_ERR_S 0 - -/* EFUSE_RD_REPEAT_ERR4_REG register - * Programming error record register 4 of BLOCK0. - */ - -#define EFUSE_RD_REPEAT_ERR4_REG (DR_REG_EFUSE_BASE + 0x190) - -/* EFUSE_RPT4_RESERVED4_ERR : RO; bitpos: [23:0]; default: 0; - * If any bit in this parameter is 1, means a programming error in - * EFUSE_RPT4_RESERVED4. - */ - -#define EFUSE_RPT4_RESERVED4_ERR 0x00FFFFFF -#define EFUSE_RPT4_RESERVED4_ERR_M (EFUSE_RPT4_RESERVED4_ERR_V << EFUSE_RPT4_RESERVED4_ERR_S) -#define EFUSE_RPT4_RESERVED4_ERR_V 0x00FFFFFF -#define EFUSE_RPT4_RESERVED4_ERR_S 0 - -/* EFUSE_RD_RS_ERR0_REG register - * Programming error record register 0 of BLOCK1-10. - */ - -#define EFUSE_RD_RS_ERR0_REG (DR_REG_EFUSE_BASE + 0x1c0) - -/* EFUSE_KEY4_FAIL : RO; bitpos: [31]; default: 0; - * 0: Means no failure and that the data of KEY4 is reliable; 1: Means that - * programming KEY4 failed and the number of error bytes is over 5. - */ - -#define EFUSE_KEY4_FAIL (BIT(31)) -#define EFUSE_KEY4_FAIL_M (EFUSE_KEY4_FAIL_V << EFUSE_KEY4_FAIL_S) -#define EFUSE_KEY4_FAIL_V 0x00000001 -#define EFUSE_KEY4_FAIL_S 31 - -/* EFUSE_KEY4_ERR_NUM : RO; bitpos: [30:28]; default: 0; - * The value of this signal means the number of error bytes in KEY4. - */ - -#define EFUSE_KEY4_ERR_NUM 0x00000007 -#define EFUSE_KEY4_ERR_NUM_M (EFUSE_KEY4_ERR_NUM_V << EFUSE_KEY4_ERR_NUM_S) -#define EFUSE_KEY4_ERR_NUM_V 0x00000007 -#define EFUSE_KEY4_ERR_NUM_S 28 - -/* EFUSE_KEY3_FAIL : RO; bitpos: [27]; default: 0; - * 0: Means no failure and that the data of KEY3 is reliable; 1: Means that - * programming KEY3 failed and the number of error bytes is over 5. - */ - -#define EFUSE_KEY3_FAIL (BIT(27)) -#define EFUSE_KEY3_FAIL_M (EFUSE_KEY3_FAIL_V << EFUSE_KEY3_FAIL_S) -#define EFUSE_KEY3_FAIL_V 0x00000001 -#define EFUSE_KEY3_FAIL_S 27 - -/* EFUSE_KEY3_ERR_NUM : RO; bitpos: [26:24]; default: 0; - * The value of this signal means the number of error bytes in KEY3. - */ - -#define EFUSE_KEY3_ERR_NUM 0x00000007 -#define EFUSE_KEY3_ERR_NUM_M (EFUSE_KEY3_ERR_NUM_V << EFUSE_KEY3_ERR_NUM_S) -#define EFUSE_KEY3_ERR_NUM_V 0x00000007 -#define EFUSE_KEY3_ERR_NUM_S 24 - -/* EFUSE_KEY2_FAIL : RO; bitpos: [23]; default: 0; - * 0: Means no failure and that the data of KEY2 is reliable; 1: Means that - * programming KEY2 failed and the number of error bytes is over 5. - */ - -#define EFUSE_KEY2_FAIL (BIT(23)) -#define EFUSE_KEY2_FAIL_M (EFUSE_KEY2_FAIL_V << EFUSE_KEY2_FAIL_S) -#define EFUSE_KEY2_FAIL_V 0x00000001 -#define EFUSE_KEY2_FAIL_S 23 - -/* EFUSE_KEY2_ERR_NUM : RO; bitpos: [22:20]; default: 0; - * The value of this signal means the number of error bytes in KEY2. - */ - -#define EFUSE_KEY2_ERR_NUM 0x00000007 -#define EFUSE_KEY2_ERR_NUM_M (EFUSE_KEY2_ERR_NUM_V << EFUSE_KEY2_ERR_NUM_S) -#define EFUSE_KEY2_ERR_NUM_V 0x00000007 -#define EFUSE_KEY2_ERR_NUM_S 20 - -/* EFUSE_KEY1_FAIL : RO; bitpos: [19]; default: 0; - * 0: Means no failure and that the data of KEY1 is reliable; 1: Means that - * programming KEY1 failed and the number of error bytes is over 5. - */ - -#define EFUSE_KEY1_FAIL (BIT(19)) -#define EFUSE_KEY1_FAIL_M (EFUSE_KEY1_FAIL_V << EFUSE_KEY1_FAIL_S) -#define EFUSE_KEY1_FAIL_V 0x00000001 -#define EFUSE_KEY1_FAIL_S 19 - -/* EFUSE_KEY1_ERR_NUM : RO; bitpos: [18:16]; default: 0; - * The value of this signal means the number of error bytes in KEY1. - */ - -#define EFUSE_KEY1_ERR_NUM 0x00000007 -#define EFUSE_KEY1_ERR_NUM_M (EFUSE_KEY1_ERR_NUM_V << EFUSE_KEY1_ERR_NUM_S) -#define EFUSE_KEY1_ERR_NUM_V 0x00000007 -#define EFUSE_KEY1_ERR_NUM_S 16 - -/* EFUSE_KEY0_FAIL : RO; bitpos: [15]; default: 0; - * 0: Means no failure and that the data of KEY0 is reliable; 1: Means that - * programming KEY0 failed and the number of error bytes is over 5. - */ - -#define EFUSE_KEY0_FAIL (BIT(15)) -#define EFUSE_KEY0_FAIL_M (EFUSE_KEY0_FAIL_V << EFUSE_KEY0_FAIL_S) -#define EFUSE_KEY0_FAIL_V 0x00000001 -#define EFUSE_KEY0_FAIL_S 15 - -/* EFUSE_KEY0_ERR_NUM : RO; bitpos: [14:12]; default: 0; - * The value of this signal means the number of error bytes in KEY0. - */ - -#define EFUSE_KEY0_ERR_NUM 0x00000007 -#define EFUSE_KEY0_ERR_NUM_M (EFUSE_KEY0_ERR_NUM_V << EFUSE_KEY0_ERR_NUM_S) -#define EFUSE_KEY0_ERR_NUM_V 0x00000007 -#define EFUSE_KEY0_ERR_NUM_S 12 - -/* EFUSE_USR_DATA_FAIL : RO; bitpos: [11]; default: 0; - * 0: Means no failure and that the data of BLOCK3 is reliable; 1: Means - * that programming BLOCK3 data failed and the number of error bytes is over - * 5. - */ - -#define EFUSE_USR_DATA_FAIL (BIT(11)) -#define EFUSE_USR_DATA_FAIL_M (EFUSE_USR_DATA_FAIL_V << EFUSE_USR_DATA_FAIL_S) -#define EFUSE_USR_DATA_FAIL_V 0x00000001 -#define EFUSE_USR_DATA_FAIL_S 11 - -/* EFUSE_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0; - * The value of this signal means the number of error bytes in BLOCK3. - */ - -#define EFUSE_USR_DATA_ERR_NUM 0x00000007 -#define EFUSE_USR_DATA_ERR_NUM_M (EFUSE_USR_DATA_ERR_NUM_V << EFUSE_USR_DATA_ERR_NUM_S) -#define EFUSE_USR_DATA_ERR_NUM_V 0x00000007 -#define EFUSE_USR_DATA_ERR_NUM_S 8 - -/* EFUSE_SYS_PART1_FAIL : RO; bitpos: [7]; default: 0; - * 0: Means no failure and that the data of BLOCK2 is reliable; 1: Means - * that programming BLOCK2 data failed and the number of error bytes is over - * 5. - */ - -#define EFUSE_SYS_PART1_FAIL (BIT(7)) -#define EFUSE_SYS_PART1_FAIL_M (EFUSE_SYS_PART1_FAIL_V << EFUSE_SYS_PART1_FAIL_S) -#define EFUSE_SYS_PART1_FAIL_V 0x00000001 -#define EFUSE_SYS_PART1_FAIL_S 7 - -/* EFUSE_SYS_PART1_NUM : RO; bitpos: [6:4]; default: 0; - * The value of this signal means the number of error bytes in BLOCK2. - */ - -#define EFUSE_SYS_PART1_NUM 0x00000007 -#define EFUSE_SYS_PART1_NUM_M (EFUSE_SYS_PART1_NUM_V << EFUSE_SYS_PART1_NUM_S) -#define EFUSE_SYS_PART1_NUM_V 0x00000007 -#define EFUSE_SYS_PART1_NUM_S 4 - -/* EFUSE_MAC_SPI_8M_FAIL : RO; bitpos: [3]; default: 0; - * 0: Means no failure and that the data of BLOCK1 is reliable; 1: Means - * that programming BLOCK1 data failed and the number of error bytes is over - * 5. - */ - -#define EFUSE_MAC_SPI_8M_FAIL (BIT(3)) -#define EFUSE_MAC_SPI_8M_FAIL_M (EFUSE_MAC_SPI_8M_FAIL_V << EFUSE_MAC_SPI_8M_FAIL_S) -#define EFUSE_MAC_SPI_8M_FAIL_V 0x00000001 -#define EFUSE_MAC_SPI_8M_FAIL_S 3 - -/* EFUSE_MAC_SPI_8M_ERR_NUM : RO; bitpos: [2:0]; default: 0; - * The value of this signal means the number of error bytes in BLOCK1. - */ - -#define EFUSE_MAC_SPI_8M_ERR_NUM 0x00000007 -#define EFUSE_MAC_SPI_8M_ERR_NUM_M (EFUSE_MAC_SPI_8M_ERR_NUM_V << EFUSE_MAC_SPI_8M_ERR_NUM_S) -#define EFUSE_MAC_SPI_8M_ERR_NUM_V 0x00000007 -#define EFUSE_MAC_SPI_8M_ERR_NUM_S 0 - -/* EFUSE_RD_RS_ERR1_REG register - * Programming error record register 1 of BLOCK1-10. - */ - -#define EFUSE_RD_RS_ERR1_REG (DR_REG_EFUSE_BASE + 0x1c4) - -/* EFUSE_SYS_PART2_FAIL : RO; bitpos: [7]; default: 0; - * 0: Means no failure and that the data of BLOCK10 is reliable; 1: Means - * that programming BLOCK10 data failed and the number of error bytes is - * over 5. - */ - -#define EFUSE_SYS_PART2_FAIL (BIT(7)) -#define EFUSE_SYS_PART2_FAIL_M (EFUSE_SYS_PART2_FAIL_V << EFUSE_SYS_PART2_FAIL_S) -#define EFUSE_SYS_PART2_FAIL_V 0x00000001 -#define EFUSE_SYS_PART2_FAIL_S 7 - -/* EFUSE_SYS_PART2_ERR_NUM : RO; bitpos: [6:4]; default: 0; - * The value of this signal means the number of error bytes in BLOCK10. - */ - -#define EFUSE_SYS_PART2_ERR_NUM 0x00000007 -#define EFUSE_SYS_PART2_ERR_NUM_M (EFUSE_SYS_PART2_ERR_NUM_V << EFUSE_SYS_PART2_ERR_NUM_S) -#define EFUSE_SYS_PART2_ERR_NUM_V 0x00000007 -#define EFUSE_SYS_PART2_ERR_NUM_S 4 - -/* EFUSE_KEY5_FAIL : RO; bitpos: [3]; default: 0; - * 0: Means no failure and that the data of KEY5 is reliable; 1: Means that - * programming user data failed and the number of error bytes is over 5. - */ - -#define EFUSE_KEY5_FAIL (BIT(3)) -#define EFUSE_KEY5_FAIL_M (EFUSE_KEY5_FAIL_V << EFUSE_KEY5_FAIL_S) -#define EFUSE_KEY5_FAIL_V 0x00000001 -#define EFUSE_KEY5_FAIL_S 3 - -/* EFUSE_KEY5_ERR_NUM : RO; bitpos: [2:0]; default: 0; - * The value of this signal means the number of error bytes in KEY5. - */ - -#define EFUSE_KEY5_ERR_NUM 0x00000007 -#define EFUSE_KEY5_ERR_NUM_M (EFUSE_KEY5_ERR_NUM_V << EFUSE_KEY5_ERR_NUM_S) -#define EFUSE_KEY5_ERR_NUM_V 0x00000007 -#define EFUSE_KEY5_ERR_NUM_S 0 - -/* EFUSE_CLK_REG register - * eFuse clock configuration register. - */ - -#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1c8) - -/* EFUSE_CLK_EN : R/W; bitpos: [16]; default: 0; - * If set, forces to enable clock signal of eFuse memory. - */ - -#define EFUSE_CLK_EN (BIT(16)) -#define EFUSE_CLK_EN_M (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S) -#define EFUSE_CLK_EN_V 0x00000001 -#define EFUSE_CLK_EN_S 16 - -/* EFUSE_EFUSE_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0; - * If set, forces eFuse SRAM into working mode. - */ - -#define EFUSE_EFUSE_MEM_FORCE_PU (BIT(2)) -#define EFUSE_EFUSE_MEM_FORCE_PU_M (EFUSE_EFUSE_MEM_FORCE_PU_V << EFUSE_EFUSE_MEM_FORCE_PU_S) -#define EFUSE_EFUSE_MEM_FORCE_PU_V 0x00000001 -#define EFUSE_EFUSE_MEM_FORCE_PU_S 2 - -/* EFUSE_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 1; - * If set, forces to activate clock signal of eFuse SRAM. - */ - -#define EFUSE_MEM_CLK_FORCE_ON (BIT(1)) -#define EFUSE_MEM_CLK_FORCE_ON_M (EFUSE_MEM_CLK_FORCE_ON_V << EFUSE_MEM_CLK_FORCE_ON_S) -#define EFUSE_MEM_CLK_FORCE_ON_V 0x00000001 -#define EFUSE_MEM_CLK_FORCE_ON_S 1 - -/* EFUSE_EFUSE_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0; - * If set, forces eFuse SRAM into power-saving mode. - */ - -#define EFUSE_EFUSE_MEM_FORCE_PD (BIT(0)) -#define EFUSE_EFUSE_MEM_FORCE_PD_M (EFUSE_EFUSE_MEM_FORCE_PD_V << EFUSE_EFUSE_MEM_FORCE_PD_S) -#define EFUSE_EFUSE_MEM_FORCE_PD_V 0x00000001 -#define EFUSE_EFUSE_MEM_FORCE_PD_S 0 - -/* EFUSE_CONF_REG register - * eFuse operation mode configuration register. - */ - -#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc) - -/* EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0; - * 0x5A5A: Operate programming command; 0x5AA5: Operate read command. - */ - -#define EFUSE_OP_CODE 0x0000FFFF -#define EFUSE_OP_CODE_M (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S) -#define EFUSE_OP_CODE_V 0x0000FFFF -#define EFUSE_OP_CODE_S 0 - -/* EFUSE_STATUS_REG register - * eFuse status register. - */ - -#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1d0) - -/* EFUSE_REPEAT_ERR_CNT : RO; bitpos: [17:10]; default: 0; - * Indicates the number of error bits during programming BLOCK0. - */ - -#define EFUSE_REPEAT_ERR_CNT 0x000000FF -#define EFUSE_REPEAT_ERR_CNT_M (EFUSE_REPEAT_ERR_CNT_V << EFUSE_REPEAT_ERR_CNT_S) -#define EFUSE_REPEAT_ERR_CNT_V 0x000000FF -#define EFUSE_REPEAT_ERR_CNT_S 10 - -/* EFUSE_OTP_VDDQ_IS_SW : RO; bitpos: [9]; default: 0; - * The value of OTP_VDDQ_IS_SW. - */ - -#define EFUSE_OTP_VDDQ_IS_SW (BIT(9)) -#define EFUSE_OTP_VDDQ_IS_SW_M (EFUSE_OTP_VDDQ_IS_SW_V << EFUSE_OTP_VDDQ_IS_SW_S) -#define EFUSE_OTP_VDDQ_IS_SW_V 0x00000001 -#define EFUSE_OTP_VDDQ_IS_SW_S 9 - -/* EFUSE_OTP_PGENB_SW : RO; bitpos: [8]; default: 0; - * The value of OTP_PGENB_SW. - */ - -#define EFUSE_OTP_PGENB_SW (BIT(8)) -#define EFUSE_OTP_PGENB_SW_M (EFUSE_OTP_PGENB_SW_V << EFUSE_OTP_PGENB_SW_S) -#define EFUSE_OTP_PGENB_SW_V 0x00000001 -#define EFUSE_OTP_PGENB_SW_S 8 - -/* EFUSE_OTP_CSB_SW : RO; bitpos: [7]; default: 0; - * The value of OTP_CSB_SW. - */ - -#define EFUSE_OTP_CSB_SW (BIT(7)) -#define EFUSE_OTP_CSB_SW_M (EFUSE_OTP_CSB_SW_V << EFUSE_OTP_CSB_SW_S) -#define EFUSE_OTP_CSB_SW_V 0x00000001 -#define EFUSE_OTP_CSB_SW_S 7 - -/* EFUSE_OTP_STROBE_SW : RO; bitpos: [6]; default: 0; - * The value of OTP_STROBE_SW. - */ - -#define EFUSE_OTP_STROBE_SW (BIT(6)) -#define EFUSE_OTP_STROBE_SW_M (EFUSE_OTP_STROBE_SW_V << EFUSE_OTP_STROBE_SW_S) -#define EFUSE_OTP_STROBE_SW_V 0x00000001 -#define EFUSE_OTP_STROBE_SW_S 6 - -/* EFUSE_OTP_VDDQ_C_SYNC2 : RO; bitpos: [5]; default: 0; - * The value of OTP_VDDQ_C_SYNC2. - */ - -#define EFUSE_OTP_VDDQ_C_SYNC2 (BIT(5)) -#define EFUSE_OTP_VDDQ_C_SYNC2_M (EFUSE_OTP_VDDQ_C_SYNC2_V << EFUSE_OTP_VDDQ_C_SYNC2_S) -#define EFUSE_OTP_VDDQ_C_SYNC2_V 0x00000001 -#define EFUSE_OTP_VDDQ_C_SYNC2_S 5 - -/* EFUSE_OTP_LOAD_SW : RO; bitpos: [4]; default: 0; - * The value of OTP_LOAD_SW. - */ - -#define EFUSE_OTP_LOAD_SW (BIT(4)) -#define EFUSE_OTP_LOAD_SW_M (EFUSE_OTP_LOAD_SW_V << EFUSE_OTP_LOAD_SW_S) -#define EFUSE_OTP_LOAD_SW_V 0x00000001 -#define EFUSE_OTP_LOAD_SW_S 4 - -/* EFUSE_STATE : RO; bitpos: [3:0]; default: 0; - * Indicates the state of the eFuse state machine. - */ - -#define EFUSE_STATE 0x0000000F -#define EFUSE_STATE_M (EFUSE_STATE_V << EFUSE_STATE_S) -#define EFUSE_STATE_V 0x0000000F -#define EFUSE_STATE_S 0 - -/* EFUSE_CMD_REG register - * eFuse command register. - */ - -#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1d4) - -/* EFUSE_BLK_NUM : R/W; bitpos: [5:2]; default: 0; - * The serial number of the block to be programmed. Value 0-10 corresponds - * to block number 0-10, respectively. - */ - -#define EFUSE_BLK_NUM 0x0000000F -#define EFUSE_BLK_NUM_M (EFUSE_BLK_NUM_V << EFUSE_BLK_NUM_S) -#define EFUSE_BLK_NUM_V 0x0000000F -#define EFUSE_BLK_NUM_S 2 - -/* EFUSE_PGM_CMD : R/W; bitpos: [1]; default: 0; - * Set this bit to send programming command. - */ - -#define EFUSE_PGM_CMD (BIT(1)) -#define EFUSE_PGM_CMD_M (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S) -#define EFUSE_PGM_CMD_V 0x00000001 -#define EFUSE_PGM_CMD_S 1 - -/* EFUSE_READ_CMD : R/W; bitpos: [0]; default: 0; - * Set this bit to send read command. - */ - -#define EFUSE_READ_CMD (BIT(0)) -#define EFUSE_READ_CMD_M (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S) -#define EFUSE_READ_CMD_V 0x00000001 -#define EFUSE_READ_CMD_S 0 - -/* EFUSE_INT_RAW_REG register - * eFuse raw interrupt register. - */ - -#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1d8) - -/* EFUSE_PGM_DONE_INT_RAW : RO; bitpos: [1]; default: 0; - * The raw bit signal for pgm_done interrupt. - */ - -#define EFUSE_PGM_DONE_INT_RAW (BIT(1)) -#define EFUSE_PGM_DONE_INT_RAW_M (EFUSE_PGM_DONE_INT_RAW_V << EFUSE_PGM_DONE_INT_RAW_S) -#define EFUSE_PGM_DONE_INT_RAW_V 0x00000001 -#define EFUSE_PGM_DONE_INT_RAW_S 1 - -/* EFUSE_READ_DONE_INT_RAW : RO; bitpos: [0]; default: 0; - * The raw bit signal for read_done interrupt. - */ - -#define EFUSE_READ_DONE_INT_RAW (BIT(0)) -#define EFUSE_READ_DONE_INT_RAW_M (EFUSE_READ_DONE_INT_RAW_V << EFUSE_READ_DONE_INT_RAW_S) -#define EFUSE_READ_DONE_INT_RAW_V 0x00000001 -#define EFUSE_READ_DONE_INT_RAW_S 0 - -/* EFUSE_INT_ST_REG register - * eFuse interrupt status register. - */ - -#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1dc) - -/* EFUSE_PGM_DONE_INT_ST : RO; bitpos: [1]; default: 0; - * The status signal for pgm_done interrupt. - */ - -#define EFUSE_PGM_DONE_INT_ST (BIT(1)) -#define EFUSE_PGM_DONE_INT_ST_M (EFUSE_PGM_DONE_INT_ST_V << EFUSE_PGM_DONE_INT_ST_S) -#define EFUSE_PGM_DONE_INT_ST_V 0x00000001 -#define EFUSE_PGM_DONE_INT_ST_S 1 - -/* EFUSE_READ_DONE_INT_ST : RO; bitpos: [0]; default: 0; - * The status signal for read_done interrupt. - */ - -#define EFUSE_READ_DONE_INT_ST (BIT(0)) -#define EFUSE_READ_DONE_INT_ST_M (EFUSE_READ_DONE_INT_ST_V << EFUSE_READ_DONE_INT_ST_S) -#define EFUSE_READ_DONE_INT_ST_V 0x00000001 -#define EFUSE_READ_DONE_INT_ST_S 0 - -/* EFUSE_INT_ENA_REG register - * eFuse interrupt enable register. - */ - -#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1e0) - -/* EFUSE_PGM_DONE_INT_ENA : R/W; bitpos: [1]; default: 0; - * The enable signal for pgm_done interrupt. - */ - -#define EFUSE_PGM_DONE_INT_ENA (BIT(1)) -#define EFUSE_PGM_DONE_INT_ENA_M (EFUSE_PGM_DONE_INT_ENA_V << EFUSE_PGM_DONE_INT_ENA_S) -#define EFUSE_PGM_DONE_INT_ENA_V 0x00000001 -#define EFUSE_PGM_DONE_INT_ENA_S 1 - -/* EFUSE_READ_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; - * The enable signal for read_done interrupt. - */ - -#define EFUSE_READ_DONE_INT_ENA (BIT(0)) -#define EFUSE_READ_DONE_INT_ENA_M (EFUSE_READ_DONE_INT_ENA_V << EFUSE_READ_DONE_INT_ENA_S) -#define EFUSE_READ_DONE_INT_ENA_V 0x00000001 -#define EFUSE_READ_DONE_INT_ENA_S 0 - -/* EFUSE_INT_CLR_REG register - * eFuse interrupt clear register. - */ - -#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1e4) - -/* EFUSE_PGM_DONE_INT_CLR : WO; bitpos: [1]; default: 0; - * The clear signal for pgm_done interrupt. - */ - -#define EFUSE_PGM_DONE_INT_CLR (BIT(1)) -#define EFUSE_PGM_DONE_INT_CLR_M (EFUSE_PGM_DONE_INT_CLR_V << EFUSE_PGM_DONE_INT_CLR_S) -#define EFUSE_PGM_DONE_INT_CLR_V 0x00000001 -#define EFUSE_PGM_DONE_INT_CLR_S 1 - -/* EFUSE_READ_DONE_INT_CLR : WO; bitpos: [0]; default: 0; - * The clear signal for read_done interrupt. - */ - -#define EFUSE_READ_DONE_INT_CLR (BIT(0)) -#define EFUSE_READ_DONE_INT_CLR_M (EFUSE_READ_DONE_INT_CLR_V << EFUSE_READ_DONE_INT_CLR_S) -#define EFUSE_READ_DONE_INT_CLR_V 0x00000001 -#define EFUSE_READ_DONE_INT_CLR_S 0 - -/* EFUSE_DAC_CONF_REG register - * Controls the eFuse programming voltage. - */ - -#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1e8) - -/* EFUSE_OE_CLR : R/W; bitpos: [17]; default: 0; - * Reduces the power supply of the programming voltage. - */ - -#define EFUSE_OE_CLR (BIT(17)) -#define EFUSE_OE_CLR_M (EFUSE_OE_CLR_V << EFUSE_OE_CLR_S) -#define EFUSE_OE_CLR_V 0x00000001 -#define EFUSE_OE_CLR_S 17 - -/* EFUSE_DAC_NUM : R/W; bitpos: [16:9]; default: 255; - * Controls the rising period of the programming voltage. - */ - -#define EFUSE_DAC_NUM 0x000000FF -#define EFUSE_DAC_NUM_M (EFUSE_DAC_NUM_V << EFUSE_DAC_NUM_S) -#define EFUSE_DAC_NUM_V 0x000000FF -#define EFUSE_DAC_NUM_S 9 - -/* EFUSE_DAC_CLK_PAD_SEL : R/W; bitpos: [8]; default: 0; - * Don't care. - */ - -#define EFUSE_DAC_CLK_PAD_SEL (BIT(8)) -#define EFUSE_DAC_CLK_PAD_SEL_M (EFUSE_DAC_CLK_PAD_SEL_V << EFUSE_DAC_CLK_PAD_SEL_S) -#define EFUSE_DAC_CLK_PAD_SEL_V 0x00000001 -#define EFUSE_DAC_CLK_PAD_SEL_S 8 - -/* EFUSE_DAC_CLK_DIV : R/W; bitpos: [7:0]; default: 28; - * Controls the division factor of the rising clock of the programming - * voltage. - */ - -#define EFUSE_DAC_CLK_DIV 0x000000FF -#define EFUSE_DAC_CLK_DIV_M (EFUSE_DAC_CLK_DIV_V << EFUSE_DAC_CLK_DIV_S) -#define EFUSE_DAC_CLK_DIV_V 0x000000FF -#define EFUSE_DAC_CLK_DIV_S 0 - -/* EFUSE_RD_TIM_CONF_REG register - * Configures read timing parameters. - */ - -#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1ec) - -/* EFUSE_READ_INIT_NUM : R/W; bitpos: [31:24]; default: 18; - * Configures the initial read time of eFuse. - */ - -#define EFUSE_READ_INIT_NUM 0x000000FF -#define EFUSE_READ_INIT_NUM_M (EFUSE_READ_INIT_NUM_V << EFUSE_READ_INIT_NUM_S) -#define EFUSE_READ_INIT_NUM_V 0x000000FF -#define EFUSE_READ_INIT_NUM_S 24 - -/* EFUSE_TSUR_A : R/W; bitpos: [23:16]; default: 1; - * Configures the setup time of read operation. - */ - -#define EFUSE_TSUR_A 0x000000FF -#define EFUSE_TSUR_A_M (EFUSE_TSUR_A_V << EFUSE_TSUR_A_S) -#define EFUSE_TSUR_A_V 0x000000FF -#define EFUSE_TSUR_A_S 16 - -/* EFUSE_TRD : R/W; bitpos: [15:8]; default: 1; - * Configures the length of pulse of read operation. - */ - -#define EFUSE_TRD 0x000000FF -#define EFUSE_TRD_M (EFUSE_TRD_V << EFUSE_TRD_S) -#define EFUSE_TRD_V 0x000000FF -#define EFUSE_TRD_S 8 - -/* EFUSE_THR_A : R/W; bitpos: [7:0]; default: 1; - * Configures the hold time of read operation. - */ - -#define EFUSE_THR_A 0x000000FF -#define EFUSE_THR_A_M (EFUSE_THR_A_V << EFUSE_THR_A_S) -#define EFUSE_THR_A_V 0x000000FF -#define EFUSE_THR_A_S 0 - -/* EFUSE_WR_TIM_CONF0_REG register - * Configuration register 0 of eFuse programming timing parameters. - */ - -#define EFUSE_WR_TIM_CONF0_REG (DR_REG_EFUSE_BASE + 0x1f0) - -/* EFUSE_TPGM : R/W; bitpos: [31:16]; default: 200; - * Configures the length of pulse during programming 1 to eFuse. - */ - -#define EFUSE_TPGM 0x0000FFFF -#define EFUSE_TPGM_M (EFUSE_TPGM_V << EFUSE_TPGM_S) -#define EFUSE_TPGM_V 0x0000FFFF -#define EFUSE_TPGM_S 16 - -/* EFUSE_TPGM_INACTIVE : R/W; bitpos: [15:8]; default: 1; - * Configures the length of pulse during programming 0 to eFuse. - */ - -#define EFUSE_TPGM_INACTIVE 0x000000FF -#define EFUSE_TPGM_INACTIVE_M (EFUSE_TPGM_INACTIVE_V << EFUSE_TPGM_INACTIVE_S) -#define EFUSE_TPGM_INACTIVE_V 0x000000FF -#define EFUSE_TPGM_INACTIVE_S 8 - -/* EFUSE_THP_A : R/W; bitpos: [7:0]; default: 1; - * Configures the hold time of programming operation. - */ - -#define EFUSE_THP_A 0x000000FF -#define EFUSE_THP_A_M (EFUSE_THP_A_V << EFUSE_THP_A_S) -#define EFUSE_THP_A_V 0x000000FF -#define EFUSE_THP_A_S 0 - -/* EFUSE_WR_TIM_CONF1_REG register - * Configuration register 1 of eFuse programming timing parameters. - */ - -#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1f4) - -/* EFUSE_PWR_ON_NUM : R/W; bitpos: [23:8]; default: 10368; - * Configures the power up time for VDDQ. - */ - -#define EFUSE_PWR_ON_NUM 0x0000FFFF -#define EFUSE_PWR_ON_NUM_M (EFUSE_PWR_ON_NUM_V << EFUSE_PWR_ON_NUM_S) -#define EFUSE_PWR_ON_NUM_V 0x0000FFFF -#define EFUSE_PWR_ON_NUM_S 8 - -/* EFUSE_TSUP_A : R/W; bitpos: [7:0]; default: 1; - * Configures the setup time of programming operation. - */ - -#define EFUSE_TSUP_A 0x000000FF -#define EFUSE_TSUP_A_M (EFUSE_TSUP_A_V << EFUSE_TSUP_A_S) -#define EFUSE_TSUP_A_V 0x000000FF -#define EFUSE_TSUP_A_S 0 - -/* EFUSE_WR_TIM_CONF2_REG register - * Configuration register 2 of eFuse programming timing parameters. - */ - -#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1f8) - -/* EFUSE_PWR_OFF_NUM : R/W; bitpos: [15:0]; default: 400; - * Configures the power outage time for VDDQ. - */ - -#define EFUSE_PWR_OFF_NUM 0x0000FFFF -#define EFUSE_PWR_OFF_NUM_M (EFUSE_PWR_OFF_NUM_V << EFUSE_PWR_OFF_NUM_S) -#define EFUSE_PWR_OFF_NUM_V 0x0000FFFF -#define EFUSE_PWR_OFF_NUM_S 0 - -/* EFUSE_DATE_REG register - * eFuse version register. - */ - -#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1fc) - -/* EFUSE_EFUSE_DATE : R/W; bitpos: [31:0]; default: 419959040; - * Stores eFuse version. - */ - -#define EFUSE_EFUSE_DATE 0xFFFFFFFF -#define EFUSE_EFUSE_DATE_M (EFUSE_EFUSE_DATE_V << EFUSE_EFUSE_DATE_S) -#define EFUSE_EFUSE_DATE_V 0xFFFFFFFF -#define EFUSE_EFUSE_DATE_S 0 - -#define EFUSE_SPICONFIG_SPI_DEFAULTS 0 -#define EFUSE_SPICONFIG_HSPI_DEFAULTS 1 - -#define EFUSE_SPICONFIG_RET_SPICLK_MASK 0x3f -#define EFUSE_SPICONFIG_RET_SPICLK_SHIFT 0 -#define EFUSE_SPICONFIG_RET_SPICLK(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPICLK_SHIFT) & EFUSE_SPICONFIG_RET_SPICLK_MASK) - -#define EFUSE_SPICONFIG_RET_SPIQ_MASK 0x3f -#define EFUSE_SPICONFIG_RET_SPIQ_SHIFT 6 -#define EFUSE_SPICONFIG_RET_SPIQ(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPIQ_SHIFT) & EFUSE_SPICONFIG_RET_SPIQ_MASK) - -#define EFUSE_SPICONFIG_RET_SPID_MASK 0x3f -#define EFUSE_SPICONFIG_RET_SPID_SHIFT 12 -#define EFUSE_SPICONFIG_RET_SPID(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPID_SHIFT) & EFUSE_SPICONFIG_RET_SPID_MASK) - -#define EFUSE_SPICONFIG_RET_SPICS0_MASK 0x3f -#define EFUSE_SPICONFIG_RET_SPICS0_SHIFT 18 -#define EFUSE_SPICONFIG_RET_SPICS0(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPICS0_SHIFT) & EFUSE_SPICONFIG_RET_SPICS0_MASK) - -#define EFUSE_SPICONFIG_RET_SPIHD_MASK 0x3f -#define EFUSE_SPICONFIG_RET_SPIHD_SHIFT 24 -#define EFUSE_SPICONFIG_RET_SPIHD(ret) (((ret) >> EFUSE_SPICONFIG_RET_SPIHD_SHIFT) & EFUSE_SPICONFIG_RET_SPIHD_MASK) - -#endif /* __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_EFUSE_H */ diff --git a/arch/xtensa/src/esp32s2/hardware/esp32s2_rtccntl.h b/arch/xtensa/src/esp32s2/hardware/esp32s2_rtccntl.h deleted file mode 100644 index f175d24d8a2e7..0000000000000 --- a/arch/xtensa/src/esp32s2/hardware/esp32s2_rtccntl.h +++ /dev/null @@ -1,5087 +0,0 @@ -/**************************************************************************** - * arch/xtensa/src/esp32s2/hardware/esp32s2_rtccntl.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_RTCCNTL_H -#define __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_RTCCNTL_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include "esp32s2_soc.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Offset relative to each watchdog timer instance memory base */ - -#define RWDT_CONFIG0_OFFSET 0x0094 -#define XTWDT_CONFIG0_OFFSET 0x0060 - -/* RWDT */ - -#define RWDT_STAGE0_TIMEOUT_OFFSET 0x0098 -#define RWDT_STAGE1_TIMEOUT_OFFSET 0x009c -#define RWDT_STAGE2_TIMEOUT_OFFSET 0x00a0 -#define RWDT_STAGE3_TIMEOUT_OFFSET 0x00a4 -#define RWDT_FEED_OFFSET 0x00a8 -#define RWDT_WP_REG 0x00ac -#define RWDT_INT_ENA_REG_OFFSET 0x0040 -#define RWDT_INT_CLR_REG_OFFSET 0x004c - -/* XTWDT */ - -#define XTWDT_TIMEOUT_OFFSET 0x00f4 -#define XTWDT_CLK_PRESCALE_OFFSET 0x00f0 -#define XTWDT_INT_ENA_REG_OFFSET 0x0040 - -/* The value that needs to be written to RTC_CNTL_WDT_WKEY to - * write-enable the wdt registers - */ - -#define RTC_CNTL_WDT_WKEY_VALUE 0x50d83aa1 - -/* The value that needs to be written to RTC_CNTL_SWD_WPROTECT_REG - * to write-enable the wdt registers - */ - -#define RTC_CNTL_SWD_WKEY_VALUE 0x8f1d312a - -#define RTC_CNTL_TIME0_REG RTC_CNTL_TIME_LOW0_REG -#define RTC_CNTL_TIME1_REG RTC_CNTL_TIME_HIGH0_REG - -#define DPORT_CPUPERIOD_SEL_80 0 -#define DPORT_CPUPERIOD_SEL_160 1 -#define DPORT_CPUPERIOD_SEL_240 2 - -#define DPORT_SOC_CLK_SEL_XTAL 0 -#define DPORT_SOC_CLK_SEL_PLL 1 -#define DPORT_SOC_CLK_SEL_8M 2 - -#define RTC_APB_FREQ_REG RTC_CNTL_STORE5_REG - -/* RTC_CNTL_OPTIONS0_REG register - * set xtal and pll power and sw reset register - */ - -#define RTC_CNTL_OPTIONS0_REG (DR_REG_RTCCNTL_BASE + 0x0) - -/* RTC_CNTL_SW_SYS_RST : WO; bitpos: [31]; default: 0; - * SW system reset - */ - -#define RTC_CNTL_SW_SYS_RST (BIT(31)) -#define RTC_CNTL_SW_SYS_RST_M (RTC_CNTL_SW_SYS_RST_V << RTC_CNTL_SW_SYS_RST_S) -#define RTC_CNTL_SW_SYS_RST_V 0x00000001 -#define RTC_CNTL_SW_SYS_RST_S 31 - -/* RTC_CNTL_DG_WRAP_FORCE_NORST : R/W; bitpos: [30]; default: 0; - * digital core force no reset in deep sleep - */ - -#define RTC_CNTL_DG_WRAP_FORCE_NORST (BIT(30)) -#define RTC_CNTL_DG_WRAP_FORCE_NORST_M (RTC_CNTL_DG_WRAP_FORCE_NORST_V << RTC_CNTL_DG_WRAP_FORCE_NORST_S) -#define RTC_CNTL_DG_WRAP_FORCE_NORST_V 0x00000001 -#define RTC_CNTL_DG_WRAP_FORCE_NORST_S 30 - -/* RTC_CNTL_DG_WRAP_FORCE_RST : R/W; bitpos: [29]; default: 0; - * digital wrap force reset in deep sleep - */ - -#define RTC_CNTL_DG_WRAP_FORCE_RST (BIT(29)) -#define RTC_CNTL_DG_WRAP_FORCE_RST_M (RTC_CNTL_DG_WRAP_FORCE_RST_V << RTC_CNTL_DG_WRAP_FORCE_RST_S) -#define RTC_CNTL_DG_WRAP_FORCE_RST_V 0x00000001 -#define RTC_CNTL_DG_WRAP_FORCE_RST_S 29 - -/* RTC_CNTL_ANALOG_FORCE_NOISO : R/W; bitpos: [28]; default: 1; */ - -#define RTC_CNTL_ANALOG_FORCE_NOISO (BIT(28)) -#define RTC_CNTL_ANALOG_FORCE_NOISO_M (RTC_CNTL_ANALOG_FORCE_NOISO_V << RTC_CNTL_ANALOG_FORCE_NOISO_S) -#define RTC_CNTL_ANALOG_FORCE_NOISO_V 0x00000001 -#define RTC_CNTL_ANALOG_FORCE_NOISO_S 28 - -/* RTC_CNTL_PLL_FORCE_NOISO : R/W; bitpos: [27]; default: 1; */ - -#define RTC_CNTL_PLL_FORCE_NOISO (BIT(27)) -#define RTC_CNTL_PLL_FORCE_NOISO_M (RTC_CNTL_PLL_FORCE_NOISO_V << RTC_CNTL_PLL_FORCE_NOISO_S) -#define RTC_CNTL_PLL_FORCE_NOISO_V 0x00000001 -#define RTC_CNTL_PLL_FORCE_NOISO_S 27 - -/* RTC_CNTL_XTL_FORCE_NOISO : R/W; bitpos: [26]; default: 1; */ - -#define RTC_CNTL_XTL_FORCE_NOISO (BIT(26)) -#define RTC_CNTL_XTL_FORCE_NOISO_M (RTC_CNTL_XTL_FORCE_NOISO_V << RTC_CNTL_XTL_FORCE_NOISO_S) -#define RTC_CNTL_XTL_FORCE_NOISO_V 0x00000001 -#define RTC_CNTL_XTL_FORCE_NOISO_S 26 - -/* RTC_CNTL_ANALOG_FORCE_ISO : R/W; bitpos: [25]; default: 0; */ - -#define RTC_CNTL_ANALOG_FORCE_ISO (BIT(25)) -#define RTC_CNTL_ANALOG_FORCE_ISO_M (RTC_CNTL_ANALOG_FORCE_ISO_V << RTC_CNTL_ANALOG_FORCE_ISO_S) -#define RTC_CNTL_ANALOG_FORCE_ISO_V 0x00000001 -#define RTC_CNTL_ANALOG_FORCE_ISO_S 25 - -/* RTC_CNTL_PLL_FORCE_ISO : R/W; bitpos: [24]; default: 0; */ - -#define RTC_CNTL_PLL_FORCE_ISO (BIT(24)) -#define RTC_CNTL_PLL_FORCE_ISO_M (RTC_CNTL_PLL_FORCE_ISO_V << RTC_CNTL_PLL_FORCE_ISO_S) -#define RTC_CNTL_PLL_FORCE_ISO_V 0x00000001 -#define RTC_CNTL_PLL_FORCE_ISO_S 24 - -/* RTC_CNTL_XTL_FORCE_ISO : R/W; bitpos: [23]; default: 0; */ - -#define RTC_CNTL_XTL_FORCE_ISO (BIT(23)) -#define RTC_CNTL_XTL_FORCE_ISO_M (RTC_CNTL_XTL_FORCE_ISO_V << RTC_CNTL_XTL_FORCE_ISO_S) -#define RTC_CNTL_XTL_FORCE_ISO_V 0x00000001 -#define RTC_CNTL_XTL_FORCE_ISO_S 23 - -/* RTC_CNTL_XTL_FORCE_PU : R/W; bitpos: [13]; default: 1; - * crystall force power up - */ - -#define RTC_CNTL_XTL_FORCE_PU (BIT(13)) -#define RTC_CNTL_XTL_FORCE_PU_M (RTC_CNTL_XTL_FORCE_PU_V << RTC_CNTL_XTL_FORCE_PU_S) -#define RTC_CNTL_XTL_FORCE_PU_V 0x00000001 -#define RTC_CNTL_XTL_FORCE_PU_S 13 - -/* RTC_CNTL_XTL_FORCE_PD : R/W; bitpos: [12]; default: 0; - * crystall force power down - */ - -#define RTC_CNTL_XTL_FORCE_PD (BIT(12)) -#define RTC_CNTL_XTL_FORCE_PD_M (RTC_CNTL_XTL_FORCE_PD_V << RTC_CNTL_XTL_FORCE_PD_S) -#define RTC_CNTL_XTL_FORCE_PD_V 0x00000001 -#define RTC_CNTL_XTL_FORCE_PD_S 12 - -/* RTC_CNTL_BBPLL_FORCE_PU : R/W; bitpos: [11]; default: 0; - * BB_PLL force power up - */ - -#define RTC_CNTL_BBPLL_FORCE_PU (BIT(11)) -#define RTC_CNTL_BBPLL_FORCE_PU_M (RTC_CNTL_BBPLL_FORCE_PU_V << RTC_CNTL_BBPLL_FORCE_PU_S) -#define RTC_CNTL_BBPLL_FORCE_PU_V 0x00000001 -#define RTC_CNTL_BBPLL_FORCE_PU_S 11 - -/* RTC_CNTL_BBPLL_FORCE_PD : R/W; bitpos: [10]; default: 0; - * BB_PLL force power down - */ - -#define RTC_CNTL_BBPLL_FORCE_PD (BIT(10)) -#define RTC_CNTL_BBPLL_FORCE_PD_M (RTC_CNTL_BBPLL_FORCE_PD_V << RTC_CNTL_BBPLL_FORCE_PD_S) -#define RTC_CNTL_BBPLL_FORCE_PD_V 0x00000001 -#define RTC_CNTL_BBPLL_FORCE_PD_S 10 - -/* RTC_CNTL_BBPLL_I2C_FORCE_PU : R/W; bitpos: [9]; default: 0; - * BB_PLL_I2C force power up - */ - -#define RTC_CNTL_BBPLL_I2C_FORCE_PU (BIT(9)) -#define RTC_CNTL_BBPLL_I2C_FORCE_PU_M (RTC_CNTL_BBPLL_I2C_FORCE_PU_V << RTC_CNTL_BBPLL_I2C_FORCE_PU_S) -#define RTC_CNTL_BBPLL_I2C_FORCE_PU_V 0x00000001 -#define RTC_CNTL_BBPLL_I2C_FORCE_PU_S 9 - -/* RTC_CNTL_BBPLL_I2C_FORCE_PD : R/W; bitpos: [8]; default: 0; - * BB_PLL _I2C force power down - */ - -#define RTC_CNTL_BBPLL_I2C_FORCE_PD (BIT(8)) -#define RTC_CNTL_BBPLL_I2C_FORCE_PD_M (RTC_CNTL_BBPLL_I2C_FORCE_PD_V << RTC_CNTL_BBPLL_I2C_FORCE_PD_S) -#define RTC_CNTL_BBPLL_I2C_FORCE_PD_V 0x00000001 -#define RTC_CNTL_BBPLL_I2C_FORCE_PD_S 8 - -/* RTC_CNTL_BB_I2C_FORCE_PU : R/W; bitpos: [7]; default: 0; - * BB_I2C force power up - */ - -#define RTC_CNTL_BB_I2C_FORCE_PU (BIT(7)) -#define RTC_CNTL_BB_I2C_FORCE_PU_M (RTC_CNTL_BB_I2C_FORCE_PU_V << RTC_CNTL_BB_I2C_FORCE_PU_S) -#define RTC_CNTL_BB_I2C_FORCE_PU_V 0x00000001 -#define RTC_CNTL_BB_I2C_FORCE_PU_S 7 - -/* RTC_CNTL_BB_I2C_FORCE_PD : R/W; bitpos: [6]; default: 0; - * BB_I2C force power down - */ - -#define RTC_CNTL_BB_I2C_FORCE_PD (BIT(6)) -#define RTC_CNTL_BB_I2C_FORCE_PD_M (RTC_CNTL_BB_I2C_FORCE_PD_V << RTC_CNTL_BB_I2C_FORCE_PD_S) -#define RTC_CNTL_BB_I2C_FORCE_PD_V 0x00000001 -#define RTC_CNTL_BB_I2C_FORCE_PD_S 6 - -/* RTC_CNTL_SW_PROCPU_RST : WO; bitpos: [5]; default: 0; - * PRO CPU SW reset - */ - -#define RTC_CNTL_SW_PROCPU_RST (BIT(5)) -#define RTC_CNTL_SW_PROCPU_RST_M (RTC_CNTL_SW_PROCPU_RST_V << RTC_CNTL_SW_PROCPU_RST_S) -#define RTC_CNTL_SW_PROCPU_RST_V 0x00000001 -#define RTC_CNTL_SW_PROCPU_RST_S 5 - -/* RTC_CNTL_SW_APPCPU_RST : WO; bitpos: [4]; default: 0; - * APP CPU SW reset - */ - -#define RTC_CNTL_SW_APPCPU_RST (BIT(4)) -#define RTC_CNTL_SW_APPCPU_RST_M (RTC_CNTL_SW_APPCPU_RST_V << RTC_CNTL_SW_APPCPU_RST_S) -#define RTC_CNTL_SW_APPCPU_RST_V 0x00000001 -#define RTC_CNTL_SW_APPCPU_RST_S 4 - -/* RTC_CNTL_SW_STALL_PROCPU_C0 : R/W; bitpos: [3:2]; default: 0; - * {reg_sw_stall_procpu_c1[5:0] , reg_sw_stall_procpu_c0[1:0]} == 0x86 will - * stall PRO CPU - */ - -#define RTC_CNTL_SW_STALL_PROCPU_C0 0x00000003 -#define RTC_CNTL_SW_STALL_PROCPU_C0_M (RTC_CNTL_SW_STALL_PROCPU_C0_V << RTC_CNTL_SW_STALL_PROCPU_C0_S) -#define RTC_CNTL_SW_STALL_PROCPU_C0_V 0x00000003 -#define RTC_CNTL_SW_STALL_PROCPU_C0_S 2 - -/* RTC_CNTL_SW_STALL_APPCPU_C0 : R/W; bitpos: [1:0]; default: 0; - * {reg_sw_stall_appcpu_c1[5:0] , reg_sw_stall_appcpu_c0[1:0]} == 0x86 will - * stall APP CPU - */ - -#define RTC_CNTL_SW_STALL_APPCPU_C0 0x00000003 -#define RTC_CNTL_SW_STALL_APPCPU_C0_M (RTC_CNTL_SW_STALL_APPCPU_C0_V << RTC_CNTL_SW_STALL_APPCPU_C0_S) -#define RTC_CNTL_SW_STALL_APPCPU_C0_V 0x00000003 -#define RTC_CNTL_SW_STALL_APPCPU_C0_S 0 - -/* RTC_CNTL_SLP_TIMER0_REG register - * rtc_sleep_timer0 register - */ - -#define RTC_CNTL_SLP_TIMER0_REG (DR_REG_RTCCNTL_BASE + 0x4) - -/* RTC_CNTL_SLP_VAL_LO : R/W; bitpos: [31:0]; default: 0; - * RTC sleep timer low 32 bits - */ - -#define RTC_CNTL_SLP_VAL_LO 0xFFFFFFFF -#define RTC_CNTL_SLP_VAL_LO_M (RTC_CNTL_SLP_VAL_LO_V << RTC_CNTL_SLP_VAL_LO_S) -#define RTC_CNTL_SLP_VAL_LO_V 0xFFFFFFFF -#define RTC_CNTL_SLP_VAL_LO_S 0 - -/* RTC_CNTL_SLP_TIMER1_REG register - * rtc_sleep_timer1 register - */ - -#define RTC_CNTL_SLP_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x8) - -/* RTC_CNTL_MAIN_TIMER_ALARM_EN : WO; bitpos: [16]; default: 0; - * timer alarm enable bit - */ - -#define RTC_CNTL_MAIN_TIMER_ALARM_EN (BIT(16)) -#define RTC_CNTL_MAIN_TIMER_ALARM_EN_M (RTC_CNTL_MAIN_TIMER_ALARM_EN_V << RTC_CNTL_MAIN_TIMER_ALARM_EN_S) -#define RTC_CNTL_MAIN_TIMER_ALARM_EN_V 0x00000001 -#define RTC_CNTL_MAIN_TIMER_ALARM_EN_S 16 - -/* RTC_CNTL_SLP_VAL_HI : R/W; bitpos: [15:0]; default: 0; - * RTC sleep timer high 16 bits - */ - -#define RTC_CNTL_SLP_VAL_HI 0x0000FFFF -#define RTC_CNTL_SLP_VAL_HI_M (RTC_CNTL_SLP_VAL_HI_V << RTC_CNTL_SLP_VAL_HI_S) -#define RTC_CNTL_SLP_VAL_HI_V 0x0000FFFF -#define RTC_CNTL_SLP_VAL_HI_S 0 - -/* RTC_CNTL_TIME_UPDATE_REG register - * rtc time update register - */ - -#define RTC_CNTL_TIME_UPDATE_REG (DR_REG_RTCCNTL_BASE + 0xc) - -/* RTC_CNTL_TIME_UPDATE : WO; bitpos: [31]; default: 0; - * Set 1: to update register with RTC timer - */ - -#define RTC_CNTL_TIME_UPDATE (BIT(31)) -#define RTC_CNTL_TIME_UPDATE_M (RTC_CNTL_TIME_UPDATE_V << RTC_CNTL_TIME_UPDATE_S) -#define RTC_CNTL_TIME_UPDATE_V 0x00000001 -#define RTC_CNTL_TIME_UPDATE_S 31 - -/* RTC_CNTL_TIMER_SYS_RST : R/W; bitpos: [29]; default: 0; - * enable to record system reset time - */ - -#define RTC_CNTL_TIMER_SYS_RST (BIT(29)) -#define RTC_CNTL_TIMER_SYS_RST_M (RTC_CNTL_TIMER_SYS_RST_V << RTC_CNTL_TIMER_SYS_RST_S) -#define RTC_CNTL_TIMER_SYS_RST_V 0x00000001 -#define RTC_CNTL_TIMER_SYS_RST_S 29 - -/* RTC_CNTL_TIMER_XTL_OFF : R/W; bitpos: [28]; default: 0; - * Enable to record 40M XTAL OFF time - */ - -#define RTC_CNTL_TIMER_XTL_OFF (BIT(28)) -#define RTC_CNTL_TIMER_XTL_OFF_M (RTC_CNTL_TIMER_XTL_OFF_V << RTC_CNTL_TIMER_XTL_OFF_S) -#define RTC_CNTL_TIMER_XTL_OFF_V 0x00000001 -#define RTC_CNTL_TIMER_XTL_OFF_S 28 - -/* RTC_CNTL_TIMER_SYS_STALL : R/W; bitpos: [27]; default: 0; - * Enable to record system stall time - */ - -#define RTC_CNTL_TIMER_SYS_STALL (BIT(27)) -#define RTC_CNTL_TIMER_SYS_STALL_M (RTC_CNTL_TIMER_SYS_STALL_V << RTC_CNTL_TIMER_SYS_STALL_S) -#define RTC_CNTL_TIMER_SYS_STALL_V 0x00000001 -#define RTC_CNTL_TIMER_SYS_STALL_S 27 - -/* RTC_CNTL_TIME_LOW0_REG register - * RTC timer0 low 32 bits - */ - -#define RTC_CNTL_TIME_LOW0_REG (DR_REG_RTCCNTL_BASE + 0x10) - -/* RTC_CNTL_TIMER_VALUE0_LOW : RO; bitpos: [31:0]; default: 0; - * RTC timer low 32 bits - */ - -#define RTC_CNTL_TIMER_VALUE0_LOW 0xFFFFFFFF -#define RTC_CNTL_TIMER_VALUE0_LOW_M (RTC_CNTL_TIMER_VALUE0_LOW_V << RTC_CNTL_TIMER_VALUE0_LOW_S) -#define RTC_CNTL_TIMER_VALUE0_LOW_V 0xFFFFFFFF -#define RTC_CNTL_TIMER_VALUE0_LOW_S 0 - -/* RTC_CNTL_TIME_HIGH0_REG register - * RTC timer0 high16 bits - */ - -#define RTC_CNTL_TIME_HIGH0_REG (DR_REG_RTCCNTL_BASE + 0x14) - -/* RTC_CNTL_TIMER_VALUE0_HIGH : RO; bitpos: [15:0]; default: 0; - * RTC timer high 16 bits - */ - -#define RTC_CNTL_TIMER_VALUE0_HIGH 0x0000FFFF -#define RTC_CNTL_TIMER_VALUE0_HIGH_M (RTC_CNTL_TIMER_VALUE0_HIGH_V << RTC_CNTL_TIMER_VALUE0_HIGH_S) -#define RTC_CNTL_TIMER_VALUE0_HIGH_V 0x0000FFFF -#define RTC_CNTL_TIMER_VALUE0_HIGH_S 0 - -/* RTC_CNTL_STATE0_REG register - * configure sleep/reject/wakeup state - */ - -#define RTC_CNTL_STATE0_REG (DR_REG_RTCCNTL_BASE + 0x18) - -/* RTC_CNTL_SLEEP_EN : R/W; bitpos: [31]; default: 0; - * sleep enable bit - */ - -#define RTC_CNTL_SLEEP_EN (BIT(31)) -#define RTC_CNTL_SLEEP_EN_M (RTC_CNTL_SLEEP_EN_V << RTC_CNTL_SLEEP_EN_S) -#define RTC_CNTL_SLEEP_EN_V 0x00000001 -#define RTC_CNTL_SLEEP_EN_S 31 - -/* RTC_CNTL_SLP_REJECT : R/W; bitpos: [30]; default: 0; - * leep reject bit - */ - -#define RTC_CNTL_SLP_REJECT (BIT(30)) -#define RTC_CNTL_SLP_REJECT_M (RTC_CNTL_SLP_REJECT_V << RTC_CNTL_SLP_REJECT_S) -#define RTC_CNTL_SLP_REJECT_V 0x00000001 -#define RTC_CNTL_SLP_REJECT_S 30 - -/* RTC_CNTL_SLP_WAKEUP : R/W; bitpos: [29]; default: 0; - * leep wakeup bit - */ - -#define RTC_CNTL_SLP_WAKEUP (BIT(29)) -#define RTC_CNTL_SLP_WAKEUP_M (RTC_CNTL_SLP_WAKEUP_V << RTC_CNTL_SLP_WAKEUP_S) -#define RTC_CNTL_SLP_WAKEUP_V 0x00000001 -#define RTC_CNTL_SLP_WAKEUP_S 29 - -/* RTC_CNTL_SDIO_ACTIVE_IND : RO; bitpos: [28]; default: 0; - * SDIO active indication - */ - -#define RTC_CNTL_SDIO_ACTIVE_IND (BIT(28)) -#define RTC_CNTL_SDIO_ACTIVE_IND_M (RTC_CNTL_SDIO_ACTIVE_IND_V << RTC_CNTL_SDIO_ACTIVE_IND_S) -#define RTC_CNTL_SDIO_ACTIVE_IND_V 0x00000001 -#define RTC_CNTL_SDIO_ACTIVE_IND_S 28 - -/* RTC_CNTL_APB2RTC_BRIDGE_SEL : R/W; bitpos: [22]; default: 0; - * 1: APB to RTC using bridge 0: APB to RTC using sync - */ - -#define RTC_CNTL_APB2RTC_BRIDGE_SEL (BIT(22)) -#define RTC_CNTL_APB2RTC_BRIDGE_SEL_M (RTC_CNTL_APB2RTC_BRIDGE_SEL_V << RTC_CNTL_APB2RTC_BRIDGE_SEL_S) -#define RTC_CNTL_APB2RTC_BRIDGE_SEL_V 0x00000001 -#define RTC_CNTL_APB2RTC_BRIDGE_SEL_S 22 - -/* RTC_CNTL_SLP_REJECT_CAUSE_CLR : WO ;bitpos:[1] ;default: 1'b0 ; - *description: clear rtc sleep reject cause - */ - -#define RTC_CNTL_SLP_REJECT_CAUSE_CLR (BIT(1)) -#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_M (BIT(1)) -#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_V 0x1 -#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_S 1 - -/* RTC_CNTL_SW_CPU_INT : WO; bitpos: [0]; default: 0; - * rtc software interrupt to main cpu - */ - -#define RTC_CNTL_SW_CPU_INT (BIT(0)) -#define RTC_CNTL_SW_CPU_INT_M (RTC_CNTL_SW_CPU_INT_V << RTC_CNTL_SW_CPU_INT_S) -#define RTC_CNTL_SW_CPU_INT_V 0x00000001 -#define RTC_CNTL_SW_CPU_INT_S 0 - -/* RTC_CNTL_TIMER1_REG register - * configure time that wait analog state stable - */ - -#define RTC_CNTL_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x1c) - -/* RTC_CNTL_PLL_BUF_WAIT : R/W; bitpos: [31:24]; default: 40; - * PLL wait cycles in slow_clk_rtc - */ - -#define RTC_CNTL_PLL_BUF_WAIT 0x000000FF -#define RTC_CNTL_PLL_BUF_WAIT_M (RTC_CNTL_PLL_BUF_WAIT_V << RTC_CNTL_PLL_BUF_WAIT_S) -#define RTC_CNTL_PLL_BUF_WAIT_V 0x000000FF -#define RTC_CNTL_PLL_BUF_WAIT_S 24 -#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 20 - -/* RTC_CNTL_XTL_BUF_WAIT : R/W; bitpos: [23:14]; default: 80; - * XTAL wait cycles in slow_clk_rtc - */ - -#define RTC_CNTL_XTL_BUF_WAIT 0x000003FF -#define RTC_CNTL_XTL_BUF_WAIT_M (RTC_CNTL_XTL_BUF_WAIT_V << RTC_CNTL_XTL_BUF_WAIT_S) -#define RTC_CNTL_XTL_BUF_WAIT_V 0x000003FF -#define RTC_CNTL_XTL_BUF_WAIT_S 14 -#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 20 - -/* RTC_CNTL_CK8M_WAIT : R/W; bitpos: [13:6]; default: 16; - * CK8M wait cycles in slow_clk_rtc - */ - -#define RTC_CNTL_CK8M_WAIT 0x000000FF -#define RTC_CNTL_CK8M_WAIT_M (RTC_CNTL_CK8M_WAIT_V << RTC_CNTL_CK8M_WAIT_S) -#define RTC_CNTL_CK8M_WAIT_V 0x000000FF -#define RTC_CNTL_CK8M_WAIT_S 6 -#define RTC_CNTL_CK8M_WAIT_DEFAULT 20 - -/* RTC_CNTL_CPU_STALL_WAIT : R/W; bitpos: [5:1]; default: 1; - * CPU stall wait cycles in fast_clk_rtc - */ - -#define RTC_CNTL_CPU_STALL_WAIT 0x0000001F -#define RTC_CNTL_CPU_STALL_WAIT_M (RTC_CNTL_CPU_STALL_WAIT_V << RTC_CNTL_CPU_STALL_WAIT_S) -#define RTC_CNTL_CPU_STALL_WAIT_V 0x0000001F -#define RTC_CNTL_CPU_STALL_WAIT_S 1 - -/* RTC_CNTL_CPU_STALL_EN : R/W; bitpos: [0]; default: 1; - * CPU stall enable bit - */ - -#define RTC_CNTL_CPU_STALL_EN (BIT(0)) -#define RTC_CNTL_CPU_STALL_EN_M (RTC_CNTL_CPU_STALL_EN_V << RTC_CNTL_CPU_STALL_EN_S) -#define RTC_CNTL_CPU_STALL_EN_V 0x00000001 -#define RTC_CNTL_CPU_STALL_EN_S 0 - -/* RTC_CNTL_TIMER2_REG register - * configure time that wait analog state stable - */ - -#define RTC_CNTL_TIMER2_REG (DR_REG_RTCCNTL_BASE + 0x20) - -/* RTC_CNTL_MIN_TIME_CK8M_OFF : R/W; bitpos: [31:24]; default: 1; - * minimal cycles in slow_clk_rtc for CK8M in power down state - */ - -#define RTC_CNTL_MIN_TIME_CK8M_OFF 0x000000FF -#define RTC_CNTL_MIN_TIME_CK8M_OFF_M (RTC_CNTL_MIN_TIME_CK8M_OFF_V << RTC_CNTL_MIN_TIME_CK8M_OFF_S) -#define RTC_CNTL_MIN_TIME_CK8M_OFF_V 0x000000FF -#define RTC_CNTL_MIN_TIME_CK8M_OFF_S 24 - -/* RTC_CNTL_ULPCP_TOUCH_START_WAIT : R/W; bitpos: [23:15]; default: 16; - * wait cycles in slow_clk_rtc before ULP-coprocessor / touch controller - * start to work - */ - -#define RTC_CNTL_ULPCP_TOUCH_START_WAIT 0x000001FF -#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_M (RTC_CNTL_ULPCP_TOUCH_START_WAIT_V << RTC_CNTL_ULPCP_TOUCH_START_WAIT_S) -#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_V 0x000001FF -#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_S 15 - -/* RTC_CNTL_TIMER3_REG register - * configure some wait time for power on - */ - -#define RTC_CNTL_TIMER3_REG (DR_REG_RTCCNTL_BASE + 0x24) - -/* RTC_CNTL_ROM_RAM_POWERUP_TIMER : R/W; bitpos: [31:25]; default: 10; */ - -#define RTC_CNTL_ROM_RAM_POWERUP_TIMER 0x0000007F -#define RTC_CNTL_ROM_RAM_POWERUP_TIMER_M (RTC_CNTL_ROM_RAM_POWERUP_TIMER_V << RTC_CNTL_ROM_RAM_POWERUP_TIMER_S) -#define RTC_CNTL_ROM_RAM_POWERUP_TIMER_V 0x0000007F -#define RTC_CNTL_ROM_RAM_POWERUP_TIMER_S 25 - -/* RTC_CNTL_ROM_RAM_WAIT_TIMER : R/W; bitpos: [24:16]; default: 22; */ - -#define RTC_CNTL_ROM_RAM_WAIT_TIMER 0x000001FF -#define RTC_CNTL_ROM_RAM_WAIT_TIMER_M (RTC_CNTL_ROM_RAM_WAIT_TIMER_V << RTC_CNTL_ROM_RAM_WAIT_TIMER_S) -#define RTC_CNTL_ROM_RAM_WAIT_TIMER_V 0x000001FF -#define RTC_CNTL_ROM_RAM_WAIT_TIMER_S 16 - -/* RTC_CNTL_WIFI_POWERUP_TIMER : R/W; bitpos: [15:9]; default: 5; */ - -#define RTC_CNTL_WIFI_POWERUP_TIMER 0x0000007F -#define RTC_CNTL_WIFI_POWERUP_TIMER_M (RTC_CNTL_WIFI_POWERUP_TIMER_V << RTC_CNTL_WIFI_POWERUP_TIMER_S) -#define RTC_CNTL_WIFI_POWERUP_TIMER_V 0x0000007F -#define RTC_CNTL_WIFI_POWERUP_TIMER_S 9 - -/* RTC_CNTL_WIFI_WAIT_TIMER : R/W; bitpos: [8:0]; default: 8; */ - -#define RTC_CNTL_WIFI_WAIT_TIMER 0x000001FF -#define RTC_CNTL_WIFI_WAIT_TIMER_M (RTC_CNTL_WIFI_WAIT_TIMER_V << RTC_CNTL_WIFI_WAIT_TIMER_S) -#define RTC_CNTL_WIFI_WAIT_TIMER_V 0x000001FF -#define RTC_CNTL_WIFI_WAIT_TIMER_S 0 - -/* RTC_CNTL_TIMER4_REG register - * configure some wait time for power on - */ - -#define RTC_CNTL_TIMER4_REG (DR_REG_RTCCNTL_BASE + 0x28) - -/* RTC_CNTL_DG_WRAP_POWERUP_TIMER : R/W; bitpos: [31:25]; default: 8; */ - -#define RTC_CNTL_DG_WRAP_POWERUP_TIMER 0x0000007F -#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_M (RTC_CNTL_DG_WRAP_POWERUP_TIMER_V << RTC_CNTL_DG_WRAP_POWERUP_TIMER_S) -#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_V 0x0000007F -#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_S 25 - -/* RTC_CNTL_DG_WRAP_WAIT_TIMER : R/W; bitpos: [24:16]; default: 32; */ - -#define RTC_CNTL_DG_WRAP_WAIT_TIMER 0x000001FF -#define RTC_CNTL_DG_WRAP_WAIT_TIMER_M (RTC_CNTL_DG_WRAP_WAIT_TIMER_V << RTC_CNTL_DG_WRAP_WAIT_TIMER_S) -#define RTC_CNTL_DG_WRAP_WAIT_TIMER_V 0x000001FF -#define RTC_CNTL_DG_WRAP_WAIT_TIMER_S 16 - -/* RTC_CNTL_POWERUP_TIMER : R/W; bitpos: [15:9]; default: 5; */ - -#define RTC_CNTL_POWERUP_TIMER 0x0000007F -#define RTC_CNTL_POWERUP_TIMER_M (RTC_CNTL_POWERUP_TIMER_V << RTC_CNTL_POWERUP_TIMER_S) -#define RTC_CNTL_POWERUP_TIMER_V 0x0000007F -#define RTC_CNTL_POWERUP_TIMER_S 9 - -/* RTC_CNTL_WAIT_TIMER : R/W; bitpos: [8:0]; default: 8; */ - -#define RTC_CNTL_WAIT_TIMER 0x000001FF -#define RTC_CNTL_WAIT_TIMER_M (RTC_CNTL_WAIT_TIMER_V << RTC_CNTL_WAIT_TIMER_S) -#define RTC_CNTL_WAIT_TIMER_V 0x000001FF -#define RTC_CNTL_WAIT_TIMER_S 0 - -/* RTC_CNTL_TIMER5_REG register - * Configure minimal sleep cycles register - */ - -#define RTC_CNTL_TIMER5_REG (DR_REG_RTCCNTL_BASE + 0x2c) - -/* RTC_CNTL_RTCMEM_POWERUP_TIMER : R/W; bitpos: [31:25]; default: 9; */ - -#define RTC_CNTL_RTCMEM_POWERUP_TIMER 0x0000007F -#define RTC_CNTL_RTCMEM_POWERUP_TIMER_M (RTC_CNTL_RTCMEM_POWERUP_TIMER_V << RTC_CNTL_RTCMEM_POWERUP_TIMER_S) -#define RTC_CNTL_RTCMEM_POWERUP_TIMER_V 0x0000007F -#define RTC_CNTL_RTCMEM_POWERUP_TIMER_S 25 - -/* RTC_CNTL_RTCMEM_WAIT_TIMER : R/W; bitpos: [24:16]; default: 20; */ - -#define RTC_CNTL_RTCMEM_WAIT_TIMER 0x000001FF -#define RTC_CNTL_RTCMEM_WAIT_TIMER_M (RTC_CNTL_RTCMEM_WAIT_TIMER_V << RTC_CNTL_RTCMEM_WAIT_TIMER_S) -#define RTC_CNTL_RTCMEM_WAIT_TIMER_V 0x000001FF -#define RTC_CNTL_RTCMEM_WAIT_TIMER_S 16 - -/* RTC_CNTL_MIN_SLP_VAL : R/W; bitpos: [15:8]; default: 128; - * minimal sleep cycles in slow_clk_rtc - */ - -#define RTC_CNTL_MIN_SLP_VAL 0x000000FF -#define RTC_CNTL_MIN_SLP_VAL_M (RTC_CNTL_MIN_SLP_VAL_V << RTC_CNTL_MIN_SLP_VAL_S) -#define RTC_CNTL_MIN_SLP_VAL_V 0x000000FF -#define RTC_CNTL_MIN_SLP_VAL_S 8 -#define RTC_CNTL_MIN_SLP_VAL_MIN 2 - -/* RTC_CNTL_TIMER6_REG register - * Configure minimal sleep cycles register - */ - -#define RTC_CNTL_TIMER6_REG (DR_REG_RTCCNTL_BASE + 0x30) - -/* RTC_CNTL_DG_DCDC_POWERUP_TIMER : R/W; bitpos: [31:25]; default: 8; */ - -#define RTC_CNTL_DG_DCDC_POWERUP_TIMER 0x0000007F -#define RTC_CNTL_DG_DCDC_POWERUP_TIMER_M (RTC_CNTL_DG_DCDC_POWERUP_TIMER_V << RTC_CNTL_DG_DCDC_POWERUP_TIMER_S) -#define RTC_CNTL_DG_DCDC_POWERUP_TIMER_V 0x0000007F -#define RTC_CNTL_DG_DCDC_POWERUP_TIMER_S 25 - -/* RTC_CNTL_DG_DCDC_WAIT_TIMER : R/W; bitpos: [24:16]; default: 32; */ - -#define RTC_CNTL_DG_DCDC_WAIT_TIMER 0x000001FF -#define RTC_CNTL_DG_DCDC_WAIT_TIMER_M (RTC_CNTL_DG_DCDC_WAIT_TIMER_V << RTC_CNTL_DG_DCDC_WAIT_TIMER_S) -#define RTC_CNTL_DG_DCDC_WAIT_TIMER_V 0x000001FF -#define RTC_CNTL_DG_DCDC_WAIT_TIMER_S 16 - -/* RTC_CNTL_ANA_CONF_REG register - * configure some i2c and plla power - */ - -#define RTC_CNTL_ANA_CONF_REG (DR_REG_RTCCNTL_BASE + 0x34) - -/* RTC_CNTL_PLL_I2C_PU : R/W; bitpos: [31]; default: 0; - * 1. PLL_I2C power up ,otherwise power down - */ - -#define RTC_CNTL_PLL_I2C_PU (BIT(31)) -#define RTC_CNTL_PLL_I2C_PU_M (RTC_CNTL_PLL_I2C_PU_V << RTC_CNTL_PLL_I2C_PU_S) -#define RTC_CNTL_PLL_I2C_PU_V 0x00000001 -#define RTC_CNTL_PLL_I2C_PU_S 31 - -/* RTC_CNTL_CKGEN_I2C_PU : R/W; bitpos: [30]; default: 0; - * 1: CKGEN_I2C power up , otherwise power down - */ - -#define RTC_CNTL_CKGEN_I2C_PU (BIT(30)) -#define RTC_CNTL_CKGEN_I2C_PU_M (RTC_CNTL_CKGEN_I2C_PU_V << RTC_CNTL_CKGEN_I2C_PU_S) -#define RTC_CNTL_CKGEN_I2C_PU_V 0x00000001 -#define RTC_CNTL_CKGEN_I2C_PU_S 30 - -/* RTC_CNTL_RFRX_PBUS_PU : R/W; bitpos: [28]; default: 0; - * 1: RFRX_PBUS power up , otherwise power down - */ - -#define RTC_CNTL_RFRX_PBUS_PU (BIT(28)) -#define RTC_CNTL_RFRX_PBUS_PU_M (RTC_CNTL_RFRX_PBUS_PU_V << RTC_CNTL_RFRX_PBUS_PU_S) -#define RTC_CNTL_RFRX_PBUS_PU_V 0x00000001 -#define RTC_CNTL_RFRX_PBUS_PU_S 28 - -/* RTC_CNTL_TXRF_I2C_PU : R/W; bitpos: [27]; default: 0; - * 1: TXRF_I2C power up , otherwise power down - */ - -#define RTC_CNTL_TXRF_I2C_PU (BIT(27)) -#define RTC_CNTL_TXRF_I2C_PU_M (RTC_CNTL_TXRF_I2C_PU_V << RTC_CNTL_TXRF_I2C_PU_S) -#define RTC_CNTL_TXRF_I2C_PU_V 0x00000001 -#define RTC_CNTL_TXRF_I2C_PU_S 27 - -/* RTC_CNTL_PVTMON_PU : R/W; bitpos: [26]; default: 0; - * 1: PVTMON power up , otherwise power down - */ - -#define RTC_CNTL_PVTMON_PU (BIT(26)) -#define RTC_CNTL_PVTMON_PU_M (RTC_CNTL_PVTMON_PU_V << RTC_CNTL_PVTMON_PU_S) -#define RTC_CNTL_PVTMON_PU_V 0x00000001 -#define RTC_CNTL_PVTMON_PU_S 26 - -/* RTC_CNTL_BBPLL_CAL_SLP_START : R/W; bitpos: [25]; default: 0; - * start BBPLL calibration during sleep - */ - -#define RTC_CNTL_BBPLL_CAL_SLP_START (BIT(25)) -#define RTC_CNTL_BBPLL_CAL_SLP_START_M (RTC_CNTL_BBPLL_CAL_SLP_START_V << RTC_CNTL_BBPLL_CAL_SLP_START_S) -#define RTC_CNTL_BBPLL_CAL_SLP_START_V 0x00000001 -#define RTC_CNTL_BBPLL_CAL_SLP_START_S 25 - -/* RTC_CNTL_PLLA_FORCE_PU : R/W; bitpos: [24]; default: 0; - * PLLA force power up - */ - -#define RTC_CNTL_PLLA_FORCE_PU (BIT(24)) -#define RTC_CNTL_PLLA_FORCE_PU_M (RTC_CNTL_PLLA_FORCE_PU_V << RTC_CNTL_PLLA_FORCE_PU_S) -#define RTC_CNTL_PLLA_FORCE_PU_V 0x00000001 -#define RTC_CNTL_PLLA_FORCE_PU_S 24 - -/* RTC_CNTL_PLLA_FORCE_PD : R/W; bitpos: [23]; default: 1; - * PLLA force power down - */ - -#define RTC_CNTL_PLLA_FORCE_PD (BIT(23)) -#define RTC_CNTL_PLLA_FORCE_PD_M (RTC_CNTL_PLLA_FORCE_PD_V << RTC_CNTL_PLLA_FORCE_PD_S) -#define RTC_CNTL_PLLA_FORCE_PD_V 0x00000001 -#define RTC_CNTL_PLLA_FORCE_PD_S 23 - -/* RTC_CNTL_SAR_I2C_FORCE_PU : R/W; bitpos: [22]; default: 0; - * SAR_I2C force power up - */ - -#define RTC_CNTL_SAR_I2C_FORCE_PU (BIT(22)) -#define RTC_CNTL_SAR_I2C_FORCE_PU_M (RTC_CNTL_SAR_I2C_FORCE_PU_V << RTC_CNTL_SAR_I2C_FORCE_PU_S) -#define RTC_CNTL_SAR_I2C_FORCE_PU_V 0x00000001 -#define RTC_CNTL_SAR_I2C_FORCE_PU_S 22 - -/* RTC_CNTL_SAR_I2C_FORCE_PD : R/W; bitpos: [21]; default: 1; - * SAR_I2C force power down - */ - -#define RTC_CNTL_SAR_I2C_FORCE_PD (BIT(21)) -#define RTC_CNTL_SAR_I2C_FORCE_PD_M (RTC_CNTL_SAR_I2C_FORCE_PD_V << RTC_CNTL_SAR_I2C_FORCE_PD_S) -#define RTC_CNTL_SAR_I2C_FORCE_PD_V 0x00000001 -#define RTC_CNTL_SAR_I2C_FORCE_PD_S 21 - -/* RTC_CNTL_GLITCH_RST_EN : R/W; bitpos: [20]; default: 0; - * enable glitch reset if system detect glitch - */ - -#define RTC_CNTL_GLITCH_RST_EN (BIT(20)) -#define RTC_CNTL_GLITCH_RST_EN_M (RTC_CNTL_GLITCH_RST_EN_V << RTC_CNTL_GLITCH_RST_EN_S) -#define RTC_CNTL_GLITCH_RST_EN_V 0x00000001 -#define RTC_CNTL_GLITCH_RST_EN_S 20 - -/* RTC_CNTL_I2C_RESET_POR_FORCE_PU : R/W; bitpos: [19]; default: 0; - * SLEEP_I2CPOR force pu - */ - -#define RTC_CNTL_I2C_RESET_POR_FORCE_PU (BIT(19)) -#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_M (RTC_CNTL_I2C_RESET_POR_FORCE_PU_V << RTC_CNTL_I2C_RESET_POR_FORCE_PU_S) -#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_V 0x00000001 -#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_S 19 - -/* RTC_CNTL_I2C_RESET_POR_FORCE_PD : R/W; bitpos: [18]; default: 1; - * SLEEP_I2CPOR force pd - */ - -#define RTC_CNTL_I2C_RESET_POR_FORCE_PD (BIT(18)) -#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_M (RTC_CNTL_I2C_RESET_POR_FORCE_PD_V << RTC_CNTL_I2C_RESET_POR_FORCE_PD_S) -#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_V 0x00000001 -#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_S 18 - -/* RTC_CNTL_RESET_STATE_REG register - * reset cause state register - */ - -#define RTC_CNTL_RESET_STATE_REG (DR_REG_RTCCNTL_BASE + 0x38) - -/* RTC_CNTL_PROCPU_STAT_VECTOR_SEL : R/W; bitpos: [13]; default: 1; - * PRO CPU state vector sel - */ - -#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL (BIT(13)) -#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_M (RTC_CNTL_PROCPU_STAT_VECTOR_SEL_V << RTC_CNTL_PROCPU_STAT_VECTOR_SEL_S) -#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_V 0x00000001 -#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_S 13 - -/* RTC_CNTL_APPCPU_STAT_VECTOR_SEL : R/W; bitpos: [12]; default: 1; - * APP CPU state vector sel - */ - -#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL (BIT(12)) -#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_M (RTC_CNTL_APPCPU_STAT_VECTOR_SEL_V << RTC_CNTL_APPCPU_STAT_VECTOR_SEL_S) -#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_V 0x00000001 -#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_S 12 - -/* RTC_CNTL_RESET_CAUSE_APPCPU : RO; bitpos: [11:6]; default: 0; - * reset cause of APP CPU - */ - -#define RTC_CNTL_RESET_CAUSE_APPCPU 0x0000003F -#define RTC_CNTL_RESET_CAUSE_APPCPU_M (RTC_CNTL_RESET_CAUSE_APPCPU_V << RTC_CNTL_RESET_CAUSE_APPCPU_S) -#define RTC_CNTL_RESET_CAUSE_APPCPU_V 0x0000003F -#define RTC_CNTL_RESET_CAUSE_APPCPU_S 6 - -/* RTC_CNTL_RESET_CAUSE_PROCPU : RO; bitpos: [5:0]; default: 0; - * reset cause of PRO CPU - */ - -#define RTC_CNTL_RESET_CAUSE_PROCPU 0x0000003F -#define RTC_CNTL_RESET_CAUSE_PROCPU_M (RTC_CNTL_RESET_CAUSE_PROCPU_V << RTC_CNTL_RESET_CAUSE_PROCPU_S) -#define RTC_CNTL_RESET_CAUSE_PROCPU_V 0x0000003F -#define RTC_CNTL_RESET_CAUSE_PROCPU_S 0 - -/* RTC_CNTL_WAKEUP_STATE_REG register - * wakeup enable register - */ - -#define RTC_CNTL_WAKEUP_STATE_REG (DR_REG_RTCCNTL_BASE + 0x3c) - -/* RTC_CNTL_WAKEUP_ENA : R/W; bitpos: [31:15]; default: 12; - * wakeup enable bitmap - */ - -#define RTC_CNTL_WAKEUP_ENA 0x0001FFFF -#define RTC_CNTL_WAKEUP_ENA_M (RTC_CNTL_WAKEUP_ENA_V << RTC_CNTL_WAKEUP_ENA_S) -#define RTC_CNTL_WAKEUP_ENA_V 0x0001FFFF -#define RTC_CNTL_WAKEUP_ENA_S 15 - -/* RTC_CNTL_INT_ENA_RTC_REG register - * rtc interrupt enable register - */ - -#define RTC_CNTL_INT_ENA_RTC_REG (DR_REG_RTCCNTL_BASE + 0x40) - -/* RTC_CNTL_GLITCH_DET_INT_ENA : R/W; bitpos: [19]; default: 0; - * enable gitch det interrupt - */ - -#define RTC_CNTL_GLITCH_DET_INT_ENA (BIT(19)) -#define RTC_CNTL_GLITCH_DET_INT_ENA_M (RTC_CNTL_GLITCH_DET_INT_ENA_V << RTC_CNTL_GLITCH_DET_INT_ENA_S) -#define RTC_CNTL_GLITCH_DET_INT_ENA_V 0x00000001 -#define RTC_CNTL_GLITCH_DET_INT_ENA_S 19 - -/* RTC_CNTL_TOUCH_TIMEOUT_INT_ENA : R/W; bitpos: [18]; default: 0; - * enable touch timeout interrupt - */ - -#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA (BIT(18)) -#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_M (RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_V << RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_S) -#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_V 0x00000001 -#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_S 18 - -/* RTC_CNTL_COCPU_TRAP_INT_ENA : R/W; bitpos: [17]; default: 0; - * enable cocpu trap interrupt - */ - -#define RTC_CNTL_COCPU_TRAP_INT_ENA (BIT(17)) -#define RTC_CNTL_COCPU_TRAP_INT_ENA_M (RTC_CNTL_COCPU_TRAP_INT_ENA_V << RTC_CNTL_COCPU_TRAP_INT_ENA_S) -#define RTC_CNTL_COCPU_TRAP_INT_ENA_V 0x00000001 -#define RTC_CNTL_COCPU_TRAP_INT_ENA_S 17 - -/* RTC_CNTL_XTAL32K_DEAD_INT_ENA : R/W; bitpos: [16]; default: 0; - * enable xtal32k_dead interrupt - */ - -#define RTC_CNTL_XTAL32K_DEAD_INT_ENA (BIT(16)) -#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_M (RTC_CNTL_XTAL32K_DEAD_INT_ENA_V << RTC_CNTL_XTAL32K_DEAD_INT_ENA_S) -#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_V 0x00000001 -#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_S 16 - -/* RTC_CNTL_SWD_INT_ENA : R/W; bitpos: [15]; default: 0; - * enable super watch dog interrupt - */ - -#define RTC_CNTL_SWD_INT_ENA (BIT(15)) -#define RTC_CNTL_SWD_INT_ENA_M (RTC_CNTL_SWD_INT_ENA_V << RTC_CNTL_SWD_INT_ENA_S) -#define RTC_CNTL_SWD_INT_ENA_V 0x00000001 -#define RTC_CNTL_SWD_INT_ENA_S 15 - -/* RTC_CNTL_SARADC2_INT_ENA : R/W; bitpos: [14]; default: 0; - * enable saradc2 interrupt - */ - -#define RTC_CNTL_SARADC2_INT_ENA (BIT(14)) -#define RTC_CNTL_SARADC2_INT_ENA_M (RTC_CNTL_SARADC2_INT_ENA_V << RTC_CNTL_SARADC2_INT_ENA_S) -#define RTC_CNTL_SARADC2_INT_ENA_V 0x00000001 -#define RTC_CNTL_SARADC2_INT_ENA_S 14 - -/* RTC_CNTL_COCPU_INT_ENA : R/W; bitpos: [13]; default: 0; - * enable riscV cocpu interrupt - */ - -#define RTC_CNTL_COCPU_INT_ENA (BIT(13)) -#define RTC_CNTL_COCPU_INT_ENA_M (RTC_CNTL_COCPU_INT_ENA_V << RTC_CNTL_COCPU_INT_ENA_S) -#define RTC_CNTL_COCPU_INT_ENA_V 0x00000001 -#define RTC_CNTL_COCPU_INT_ENA_S 13 - -/* RTC_CNTL_TSENS_INT_ENA : R/W; bitpos: [12]; default: 0; - * enable tsens interrupt - */ - -#define RTC_CNTL_TSENS_INT_ENA (BIT(12)) -#define RTC_CNTL_TSENS_INT_ENA_M (RTC_CNTL_TSENS_INT_ENA_V << RTC_CNTL_TSENS_INT_ENA_S) -#define RTC_CNTL_TSENS_INT_ENA_V 0x00000001 -#define RTC_CNTL_TSENS_INT_ENA_S 12 - -/* RTC_CNTL_SARADC1_INT_ENA : R/W; bitpos: [11]; default: 0; - * enable saradc1 interrupt - */ - -#define RTC_CNTL_SARADC1_INT_ENA (BIT(11)) -#define RTC_CNTL_SARADC1_INT_ENA_M (RTC_CNTL_SARADC1_INT_ENA_V << RTC_CNTL_SARADC1_INT_ENA_S) -#define RTC_CNTL_SARADC1_INT_ENA_V 0x00000001 -#define RTC_CNTL_SARADC1_INT_ENA_S 11 - -/* RTC_CNTL_MAIN_TIMER_INT_ENA : R/W; bitpos: [10]; default: 0; - * enable RTC main timer interrupt - */ - -#define RTC_CNTL_MAIN_TIMER_INT_ENA (BIT(10)) -#define RTC_CNTL_MAIN_TIMER_INT_ENA_M (RTC_CNTL_MAIN_TIMER_INT_ENA_V << RTC_CNTL_MAIN_TIMER_INT_ENA_S) -#define RTC_CNTL_MAIN_TIMER_INT_ENA_V 0x00000001 -#define RTC_CNTL_MAIN_TIMER_INT_ENA_S 10 - -/* RTC_CNTL_BROWN_OUT_INT_ENA : R/W; bitpos: [9]; default: 0; - * enable brown out interrupt - */ - -#define RTC_CNTL_BROWN_OUT_INT_ENA (BIT(9)) -#define RTC_CNTL_BROWN_OUT_INT_ENA_M (RTC_CNTL_BROWN_OUT_INT_ENA_V << RTC_CNTL_BROWN_OUT_INT_ENA_S) -#define RTC_CNTL_BROWN_OUT_INT_ENA_V 0x00000001 -#define RTC_CNTL_BROWN_OUT_INT_ENA_S 9 - -/* RTC_CNTL_TOUCH_INACTIVE_INT_ENA : R/W; bitpos: [8]; default: 0; - * enable touch inactive interrupt - */ - -#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA (BIT(8)) -#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_M (RTC_CNTL_TOUCH_INACTIVE_INT_ENA_V << RTC_CNTL_TOUCH_INACTIVE_INT_ENA_S) -#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_V 0x00000001 -#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_S 8 - -/* RTC_CNTL_TOUCH_ACTIVE_INT_ENA : R/W; bitpos: [7]; default: 0; - * enable touch active interrupt - */ - -#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA (BIT(7)) -#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_M (RTC_CNTL_TOUCH_ACTIVE_INT_ENA_V << RTC_CNTL_TOUCH_ACTIVE_INT_ENA_S) -#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_V 0x00000001 -#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_S 7 - -/* RTC_CNTL_TOUCH_DONE_INT_ENA : R/W; bitpos: [6]; default: 0; - * enable touch done interrupt - */ - -#define RTC_CNTL_TOUCH_DONE_INT_ENA (BIT(6)) -#define RTC_CNTL_TOUCH_DONE_INT_ENA_M (RTC_CNTL_TOUCH_DONE_INT_ENA_V << RTC_CNTL_TOUCH_DONE_INT_ENA_S) -#define RTC_CNTL_TOUCH_DONE_INT_ENA_V 0x00000001 -#define RTC_CNTL_TOUCH_DONE_INT_ENA_S 6 - -/* RTC_CNTL_ULP_CP_INT_ENA : R/W; bitpos: [5]; default: 0; - * enable ULP-coprocessor interrupt - */ - -#define RTC_CNTL_ULP_CP_INT_ENA (BIT(5)) -#define RTC_CNTL_ULP_CP_INT_ENA_M (RTC_CNTL_ULP_CP_INT_ENA_V << RTC_CNTL_ULP_CP_INT_ENA_S) -#define RTC_CNTL_ULP_CP_INT_ENA_V 0x00000001 -#define RTC_CNTL_ULP_CP_INT_ENA_S 5 - -/* RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA : R/W; bitpos: [4]; default: 0; - * enable touch scan done interrupt - */ - -#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA (BIT(4)) -#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_M (RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_V << RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_S) -#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_V 0x00000001 -#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_S 4 - -/* RTC_CNTL_WDT_INT_ENA : R/W; bitpos: [3]; default: 0; - * enable RTC WDT interrupt - */ - -#define RTC_CNTL_WDT_INT_ENA (BIT(3)) -#define RTC_CNTL_WDT_INT_ENA_M (RTC_CNTL_WDT_INT_ENA_V << RTC_CNTL_WDT_INT_ENA_S) -#define RTC_CNTL_WDT_INT_ENA_V 0x00000001 -#define RTC_CNTL_WDT_INT_ENA_S 3 - -/* RTC_CNTL_SDIO_IDLE_INT_ENA : R/W; bitpos: [2]; default: 0; - * enable SDIO idle interrupt - */ - -#define RTC_CNTL_SDIO_IDLE_INT_ENA (BIT(2)) -#define RTC_CNTL_SDIO_IDLE_INT_ENA_M (RTC_CNTL_SDIO_IDLE_INT_ENA_V << RTC_CNTL_SDIO_IDLE_INT_ENA_S) -#define RTC_CNTL_SDIO_IDLE_INT_ENA_V 0x00000001 -#define RTC_CNTL_SDIO_IDLE_INT_ENA_S 2 - -/* RTC_CNTL_SLP_REJECT_INT_ENA : R/W; bitpos: [1]; default: 0; - * enable sleep reject interrupt - */ - -#define RTC_CNTL_SLP_REJECT_INT_ENA (BIT(1)) -#define RTC_CNTL_SLP_REJECT_INT_ENA_M (RTC_CNTL_SLP_REJECT_INT_ENA_V << RTC_CNTL_SLP_REJECT_INT_ENA_S) -#define RTC_CNTL_SLP_REJECT_INT_ENA_V 0x00000001 -#define RTC_CNTL_SLP_REJECT_INT_ENA_S 1 - -/* RTC_CNTL_SLP_WAKEUP_INT_ENA : R/W; bitpos: [0]; default: 0; - * enable sleep wakeup interrupt - */ - -#define RTC_CNTL_SLP_WAKEUP_INT_ENA (BIT(0)) -#define RTC_CNTL_SLP_WAKEUP_INT_ENA_M (RTC_CNTL_SLP_WAKEUP_INT_ENA_V << RTC_CNTL_SLP_WAKEUP_INT_ENA_S) -#define RTC_CNTL_SLP_WAKEUP_INT_ENA_V 0x00000001 -#define RTC_CNTL_SLP_WAKEUP_INT_ENA_S 0 - -/* RTC_CNTL_INT_RAW_RTC_REG register - * rtc_interrupt raw register - */ - -#define RTC_CNTL_INT_RAW_RTC_REG (DR_REG_RTCCNTL_BASE + 0x44) - -/* RTC_CNTL_GLITCH_DET_INT_RAW : RO; bitpos: [19]; default: 0; - * glitch_det_interrupt_raw - */ - -#define RTC_CNTL_GLITCH_DET_INT_RAW (BIT(19)) -#define RTC_CNTL_GLITCH_DET_INT_RAW_M (RTC_CNTL_GLITCH_DET_INT_RAW_V << RTC_CNTL_GLITCH_DET_INT_RAW_S) -#define RTC_CNTL_GLITCH_DET_INT_RAW_V 0x00000001 -#define RTC_CNTL_GLITCH_DET_INT_RAW_S 19 - -/* RTC_CNTL_TOUCH_TIMEOUT_INT_RAW : RO; bitpos: [18]; default: 0; - * touch timeout interrupt raw - */ - -#define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW (BIT(18)) -#define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW_M (RTC_CNTL_TOUCH_TIMEOUT_INT_RAW_V << RTC_CNTL_TOUCH_TIMEOUT_INT_RAW_S) -#define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW_V 0x00000001 -#define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW_S 18 - -/* RTC_CNTL_COCPU_TRAP_INT_RAW : RO; bitpos: [17]; default: 0; - * cocpu trap interrupt raw - */ - -#define RTC_CNTL_COCPU_TRAP_INT_RAW (BIT(17)) -#define RTC_CNTL_COCPU_TRAP_INT_RAW_M (RTC_CNTL_COCPU_TRAP_INT_RAW_V << RTC_CNTL_COCPU_TRAP_INT_RAW_S) -#define RTC_CNTL_COCPU_TRAP_INT_RAW_V 0x00000001 -#define RTC_CNTL_COCPU_TRAP_INT_RAW_S 17 - -/* RTC_CNTL_XTAL32K_DEAD_INT_RAW : RO; bitpos: [16]; default: 0; - * xtal32k dead detection interrupt raw - */ - -#define RTC_CNTL_XTAL32K_DEAD_INT_RAW (BIT(16)) -#define RTC_CNTL_XTAL32K_DEAD_INT_RAW_M (RTC_CNTL_XTAL32K_DEAD_INT_RAW_V << RTC_CNTL_XTAL32K_DEAD_INT_RAW_S) -#define RTC_CNTL_XTAL32K_DEAD_INT_RAW_V 0x00000001 -#define RTC_CNTL_XTAL32K_DEAD_INT_RAW_S 16 - -/* RTC_CNTL_SWD_INT_RAW : RO; bitpos: [15]; default: 0; - * super watch dog interrupt raw - */ - -#define RTC_CNTL_SWD_INT_RAW (BIT(15)) -#define RTC_CNTL_SWD_INT_RAW_M (RTC_CNTL_SWD_INT_RAW_V << RTC_CNTL_SWD_INT_RAW_S) -#define RTC_CNTL_SWD_INT_RAW_V 0x00000001 -#define RTC_CNTL_SWD_INT_RAW_S 15 - -/* RTC_CNTL_SARADC2_INT_RAW : RO; bitpos: [14]; default: 0; - * saradc2 interrupt raw - */ - -#define RTC_CNTL_SARADC2_INT_RAW (BIT(14)) -#define RTC_CNTL_SARADC2_INT_RAW_M (RTC_CNTL_SARADC2_INT_RAW_V << RTC_CNTL_SARADC2_INT_RAW_S) -#define RTC_CNTL_SARADC2_INT_RAW_V 0x00000001 -#define RTC_CNTL_SARADC2_INT_RAW_S 14 - -/* RTC_CNTL_COCPU_INT_RAW : RO; bitpos: [13]; default: 0; - * riscV cocpu interrupt raw - */ - -#define RTC_CNTL_COCPU_INT_RAW (BIT(13)) -#define RTC_CNTL_COCPU_INT_RAW_M (RTC_CNTL_COCPU_INT_RAW_V << RTC_CNTL_COCPU_INT_RAW_S) -#define RTC_CNTL_COCPU_INT_RAW_V 0x00000001 -#define RTC_CNTL_COCPU_INT_RAW_S 13 - -/* RTC_CNTL_TSENS_INT_RAW : RO; bitpos: [12]; default: 0; - * tsens interrupt raw - */ - -#define RTC_CNTL_TSENS_INT_RAW (BIT(12)) -#define RTC_CNTL_TSENS_INT_RAW_M (RTC_CNTL_TSENS_INT_RAW_V << RTC_CNTL_TSENS_INT_RAW_S) -#define RTC_CNTL_TSENS_INT_RAW_V 0x00000001 -#define RTC_CNTL_TSENS_INT_RAW_S 12 - -/* RTC_CNTL_SARADC1_INT_RAW : RO; bitpos: [11]; default: 0; - * saradc1 interrupt raw - */ - -#define RTC_CNTL_SARADC1_INT_RAW (BIT(11)) -#define RTC_CNTL_SARADC1_INT_RAW_M (RTC_CNTL_SARADC1_INT_RAW_V << RTC_CNTL_SARADC1_INT_RAW_S) -#define RTC_CNTL_SARADC1_INT_RAW_V 0x00000001 -#define RTC_CNTL_SARADC1_INT_RAW_S 11 - -/* RTC_CNTL_MAIN_TIMER_INT_RAW : RO; bitpos: [10]; default: 0; - * RTC main timer interrupt raw - */ - -#define RTC_CNTL_MAIN_TIMER_INT_RAW (BIT(10)) -#define RTC_CNTL_MAIN_TIMER_INT_RAW_M (RTC_CNTL_MAIN_TIMER_INT_RAW_V << RTC_CNTL_MAIN_TIMER_INT_RAW_S) -#define RTC_CNTL_MAIN_TIMER_INT_RAW_V 0x00000001 -#define RTC_CNTL_MAIN_TIMER_INT_RAW_S 10 - -/* RTC_CNTL_BROWN_OUT_INT_RAW : RO; bitpos: [9]; default: 0; - * brown out interrupt raw - */ - -#define RTC_CNTL_BROWN_OUT_INT_RAW (BIT(9)) -#define RTC_CNTL_BROWN_OUT_INT_RAW_M (RTC_CNTL_BROWN_OUT_INT_RAW_V << RTC_CNTL_BROWN_OUT_INT_RAW_S) -#define RTC_CNTL_BROWN_OUT_INT_RAW_V 0x00000001 -#define RTC_CNTL_BROWN_OUT_INT_RAW_S 9 - -/* RTC_CNTL_TOUCH_INACTIVE_INT_RAW : RO; bitpos: [8]; default: 0; - * touch inactive interrupt raw - */ - -#define RTC_CNTL_TOUCH_INACTIVE_INT_RAW (BIT(8)) -#define RTC_CNTL_TOUCH_INACTIVE_INT_RAW_M (RTC_CNTL_TOUCH_INACTIVE_INT_RAW_V << RTC_CNTL_TOUCH_INACTIVE_INT_RAW_S) -#define RTC_CNTL_TOUCH_INACTIVE_INT_RAW_V 0x00000001 -#define RTC_CNTL_TOUCH_INACTIVE_INT_RAW_S 8 - -/* RTC_CNTL_TOUCH_ACTIVE_INT_RAW : RO; bitpos: [7]; default: 0; - * touch active interrupt raw - */ - -#define RTC_CNTL_TOUCH_ACTIVE_INT_RAW (BIT(7)) -#define RTC_CNTL_TOUCH_ACTIVE_INT_RAW_M (RTC_CNTL_TOUCH_ACTIVE_INT_RAW_V << RTC_CNTL_TOUCH_ACTIVE_INT_RAW_S) -#define RTC_CNTL_TOUCH_ACTIVE_INT_RAW_V 0x00000001 -#define RTC_CNTL_TOUCH_ACTIVE_INT_RAW_S 7 - -/* RTC_CNTL_TOUCH_DONE_INT_RAW : RO; bitpos: [6]; default: 0; - * touch interrupt raw - */ - -#define RTC_CNTL_TOUCH_DONE_INT_RAW (BIT(6)) -#define RTC_CNTL_TOUCH_DONE_INT_RAW_M (RTC_CNTL_TOUCH_DONE_INT_RAW_V << RTC_CNTL_TOUCH_DONE_INT_RAW_S) -#define RTC_CNTL_TOUCH_DONE_INT_RAW_V 0x00000001 -#define RTC_CNTL_TOUCH_DONE_INT_RAW_S 6 - -/* RTC_CNTL_ULP_CP_INT_RAW : RO; bitpos: [5]; default: 0; - * ULP-coprocessor interrupt raw - */ - -#define RTC_CNTL_ULP_CP_INT_RAW (BIT(5)) -#define RTC_CNTL_ULP_CP_INT_RAW_M (RTC_CNTL_ULP_CP_INT_RAW_V << RTC_CNTL_ULP_CP_INT_RAW_S) -#define RTC_CNTL_ULP_CP_INT_RAW_V 0x00000001 -#define RTC_CNTL_ULP_CP_INT_RAW_S 5 - -/* RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW : RO; bitpos: [4]; default: 0; - * touch complete a loop interrupt raw - */ - -#define RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW (BIT(4)) -#define RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW_M (RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW_V << RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW_S) -#define RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW_V 0x00000001 -#define RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW_S 4 - -/* RTC_CNTL_WDT_INT_RAW : RO; bitpos: [3]; default: 0; - * RTC WDT interrupt raw - */ - -#define RTC_CNTL_WDT_INT_RAW (BIT(3)) -#define RTC_CNTL_WDT_INT_RAW_M (RTC_CNTL_WDT_INT_RAW_V << RTC_CNTL_WDT_INT_RAW_S) -#define RTC_CNTL_WDT_INT_RAW_V 0x00000001 -#define RTC_CNTL_WDT_INT_RAW_S 3 - -/* RTC_CNTL_SDIO_IDLE_INT_RAW : RO; bitpos: [2]; default: 0; - * SDIO idle interrupt raw - */ - -#define RTC_CNTL_SDIO_IDLE_INT_RAW (BIT(2)) -#define RTC_CNTL_SDIO_IDLE_INT_RAW_M (RTC_CNTL_SDIO_IDLE_INT_RAW_V << RTC_CNTL_SDIO_IDLE_INT_RAW_S) -#define RTC_CNTL_SDIO_IDLE_INT_RAW_V 0x00000001 -#define RTC_CNTL_SDIO_IDLE_INT_RAW_S 2 - -/* RTC_CNTL_SLP_REJECT_INT_RAW : RO; bitpos: [1]; default: 0; - * sleep reject interrupt raw - */ - -#define RTC_CNTL_SLP_REJECT_INT_RAW (BIT(1)) -#define RTC_CNTL_SLP_REJECT_INT_RAW_M (RTC_CNTL_SLP_REJECT_INT_RAW_V << RTC_CNTL_SLP_REJECT_INT_RAW_S) -#define RTC_CNTL_SLP_REJECT_INT_RAW_V 0x00000001 -#define RTC_CNTL_SLP_REJECT_INT_RAW_S 1 - -/* RTC_CNTL_SLP_WAKEUP_INT_RAW : RO; bitpos: [0]; default: 0; - * sleep wakeup interrupt raw - */ - -#define RTC_CNTL_SLP_WAKEUP_INT_RAW (BIT(0)) -#define RTC_CNTL_SLP_WAKEUP_INT_RAW_M (RTC_CNTL_SLP_WAKEUP_INT_RAW_V << RTC_CNTL_SLP_WAKEUP_INT_RAW_S) -#define RTC_CNTL_SLP_WAKEUP_INT_RAW_V 0x00000001 -#define RTC_CNTL_SLP_WAKEUP_INT_RAW_S 0 - -/* RTC_CNTL_INT_ST_RTC_REG register - * rtc_interrupt state register - */ - -#define RTC_CNTL_INT_ST_RTC_REG (DR_REG_RTCCNTL_BASE + 0x48) - -/* RTC_CNTL_GLITCH_DET_INT_ST : RO; bitpos: [19]; default: 0; - * glitch_det_interrupt state - */ - -#define RTC_CNTL_GLITCH_DET_INT_ST (BIT(19)) -#define RTC_CNTL_GLITCH_DET_INT_ST_M (RTC_CNTL_GLITCH_DET_INT_ST_V << RTC_CNTL_GLITCH_DET_INT_ST_S) -#define RTC_CNTL_GLITCH_DET_INT_ST_V 0x00000001 -#define RTC_CNTL_GLITCH_DET_INT_ST_S 19 - -/* RTC_CNTL_TOUCH_TIMEOUT_INT_ST : RO; bitpos: [18]; default: 0; - * Touch timeout interrupt state - */ - -#define RTC_CNTL_TOUCH_TIMEOUT_INT_ST (BIT(18)) -#define RTC_CNTL_TOUCH_TIMEOUT_INT_ST_M (RTC_CNTL_TOUCH_TIMEOUT_INT_ST_V << RTC_CNTL_TOUCH_TIMEOUT_INT_ST_S) -#define RTC_CNTL_TOUCH_TIMEOUT_INT_ST_V 0x00000001 -#define RTC_CNTL_TOUCH_TIMEOUT_INT_ST_S 18 - -/* RTC_CNTL_COCPU_TRAP_INT_ST : RO; bitpos: [17]; default: 0; - * cocpu trap interrupt state - */ - -#define RTC_CNTL_COCPU_TRAP_INT_ST (BIT(17)) -#define RTC_CNTL_COCPU_TRAP_INT_ST_M (RTC_CNTL_COCPU_TRAP_INT_ST_V << RTC_CNTL_COCPU_TRAP_INT_ST_S) -#define RTC_CNTL_COCPU_TRAP_INT_ST_V 0x00000001 -#define RTC_CNTL_COCPU_TRAP_INT_ST_S 17 - -/* RTC_CNTL_XTAL32K_DEAD_INT_ST : RO; bitpos: [16]; default: 0; - * xtal32k dead detection interrupt state - */ - -#define RTC_CNTL_XTAL32K_DEAD_INT_ST (BIT(16)) -#define RTC_CNTL_XTAL32K_DEAD_INT_ST_M (RTC_CNTL_XTAL32K_DEAD_INT_ST_V << RTC_CNTL_XTAL32K_DEAD_INT_ST_S) -#define RTC_CNTL_XTAL32K_DEAD_INT_ST_V 0x00000001 -#define RTC_CNTL_XTAL32K_DEAD_INT_ST_S 16 - -/* RTC_CNTL_SWD_INT_ST : RO; bitpos: [15]; default: 0; - * super watch dog interrupt state - */ - -#define RTC_CNTL_SWD_INT_ST (BIT(15)) -#define RTC_CNTL_SWD_INT_ST_M (RTC_CNTL_SWD_INT_ST_V << RTC_CNTL_SWD_INT_ST_S) -#define RTC_CNTL_SWD_INT_ST_V 0x00000001 -#define RTC_CNTL_SWD_INT_ST_S 15 - -/* RTC_CNTL_SARADC2_INT_ST : RO; bitpos: [14]; default: 0; - * saradc2 interrupt state - */ - -#define RTC_CNTL_SARADC2_INT_ST (BIT(14)) -#define RTC_CNTL_SARADC2_INT_ST_M (RTC_CNTL_SARADC2_INT_ST_V << RTC_CNTL_SARADC2_INT_ST_S) -#define RTC_CNTL_SARADC2_INT_ST_V 0x00000001 -#define RTC_CNTL_SARADC2_INT_ST_S 14 - -/* RTC_CNTL_COCPU_INT_ST : RO; bitpos: [13]; default: 0; - * riscV cocpu interrupt state - */ - -#define RTC_CNTL_COCPU_INT_ST (BIT(13)) -#define RTC_CNTL_COCPU_INT_ST_M (RTC_CNTL_COCPU_INT_ST_V << RTC_CNTL_COCPU_INT_ST_S) -#define RTC_CNTL_COCPU_INT_ST_V 0x00000001 -#define RTC_CNTL_COCPU_INT_ST_S 13 - -/* RTC_CNTL_TSENS_INT_ST : RO; bitpos: [12]; default: 0; - * tsens interrupt state - */ - -#define RTC_CNTL_TSENS_INT_ST (BIT(12)) -#define RTC_CNTL_TSENS_INT_ST_M (RTC_CNTL_TSENS_INT_ST_V << RTC_CNTL_TSENS_INT_ST_S) -#define RTC_CNTL_TSENS_INT_ST_V 0x00000001 -#define RTC_CNTL_TSENS_INT_ST_S 12 - -/* RTC_CNTL_SARADC1_INT_ST : RO; bitpos: [11]; default: 0; - * saradc1 interrupt state - */ - -#define RTC_CNTL_SARADC1_INT_ST (BIT(11)) -#define RTC_CNTL_SARADC1_INT_ST_M (RTC_CNTL_SARADC1_INT_ST_V << RTC_CNTL_SARADC1_INT_ST_S) -#define RTC_CNTL_SARADC1_INT_ST_V 0x00000001 -#define RTC_CNTL_SARADC1_INT_ST_S 11 - -/* RTC_CNTL_MAIN_TIMER_INT_ST : RO; bitpos: [10]; default: 0; - * RTC main timer interrupt state - */ - -#define RTC_CNTL_MAIN_TIMER_INT_ST (BIT(10)) -#define RTC_CNTL_MAIN_TIMER_INT_ST_M (RTC_CNTL_MAIN_TIMER_INT_ST_V << RTC_CNTL_MAIN_TIMER_INT_ST_S) -#define RTC_CNTL_MAIN_TIMER_INT_ST_V 0x00000001 -#define RTC_CNTL_MAIN_TIMER_INT_ST_S 10 - -/* RTC_CNTL_BROWN_OUT_INT_ST : RO; bitpos: [9]; default: 0; - * brown out interrupt state - */ - -#define RTC_CNTL_BROWN_OUT_INT_ST (BIT(9)) -#define RTC_CNTL_BROWN_OUT_INT_ST_M (RTC_CNTL_BROWN_OUT_INT_ST_V << RTC_CNTL_BROWN_OUT_INT_ST_S) -#define RTC_CNTL_BROWN_OUT_INT_ST_V 0x00000001 -#define RTC_CNTL_BROWN_OUT_INT_ST_S 9 - -/* RTC_CNTL_TOUCH_INACTIVE_INT_ST : RO; bitpos: [8]; default: 0; - * touch inactive interrupt state - */ - -#define RTC_CNTL_TOUCH_INACTIVE_INT_ST (BIT(8)) -#define RTC_CNTL_TOUCH_INACTIVE_INT_ST_M (RTC_CNTL_TOUCH_INACTIVE_INT_ST_V << RTC_CNTL_TOUCH_INACTIVE_INT_ST_S) -#define RTC_CNTL_TOUCH_INACTIVE_INT_ST_V 0x00000001 -#define RTC_CNTL_TOUCH_INACTIVE_INT_ST_S 8 - -/* RTC_CNTL_TOUCH_ACTIVE_INT_ST : RO; bitpos: [7]; default: 0; - * touch active interrupt state - */ - -#define RTC_CNTL_TOUCH_ACTIVE_INT_ST (BIT(7)) -#define RTC_CNTL_TOUCH_ACTIVE_INT_ST_M (RTC_CNTL_TOUCH_ACTIVE_INT_ST_V << RTC_CNTL_TOUCH_ACTIVE_INT_ST_S) -#define RTC_CNTL_TOUCH_ACTIVE_INT_ST_V 0x00000001 -#define RTC_CNTL_TOUCH_ACTIVE_INT_ST_S 7 - -/* RTC_CNTL_TOUCH_DONE_INT_ST : RO; bitpos: [6]; default: 0; - * touch done interrupt state - */ - -#define RTC_CNTL_TOUCH_DONE_INT_ST (BIT(6)) -#define RTC_CNTL_TOUCH_DONE_INT_ST_M (RTC_CNTL_TOUCH_DONE_INT_ST_V << RTC_CNTL_TOUCH_DONE_INT_ST_S) -#define RTC_CNTL_TOUCH_DONE_INT_ST_V 0x00000001 -#define RTC_CNTL_TOUCH_DONE_INT_ST_S 6 - -/* RTC_CNTL_ULP_CP_INT_ST : RO; bitpos: [5]; default: 0; - * ULP-coprocessor interrupt state - */ - -#define RTC_CNTL_ULP_CP_INT_ST (BIT(5)) -#define RTC_CNTL_ULP_CP_INT_ST_M (RTC_CNTL_ULP_CP_INT_ST_V << RTC_CNTL_ULP_CP_INT_ST_S) -#define RTC_CNTL_ULP_CP_INT_ST_V 0x00000001 -#define RTC_CNTL_ULP_CP_INT_ST_S 5 - -/* RTC_CNTL_TOUCH_SCAN_DONE_INT_ST : RO; bitpos: [4]; default: 0; - * touch complete a loop interrupt state - */ - -#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ST (BIT(4)) -#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ST_M (RTC_CNTL_TOUCH_SCAN_DONE_INT_ST_V << RTC_CNTL_TOUCH_SCAN_DONE_INT_ST_S) -#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ST_V 0x00000001 -#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ST_S 4 - -/* RTC_CNTL_WDT_INT_ST : RO; bitpos: [3]; default: 0; - * RTC WDT interrupt state - */ - -#define RTC_CNTL_WDT_INT_ST (BIT(3)) -#define RTC_CNTL_WDT_INT_ST_M (RTC_CNTL_WDT_INT_ST_V << RTC_CNTL_WDT_INT_ST_S) -#define RTC_CNTL_WDT_INT_ST_V 0x00000001 -#define RTC_CNTL_WDT_INT_ST_S 3 - -/* RTC_CNTL_SDIO_IDLE_INT_ST : RO; bitpos: [2]; default: 0; - * SDIO idle interrupt state - */ - -#define RTC_CNTL_SDIO_IDLE_INT_ST (BIT(2)) -#define RTC_CNTL_SDIO_IDLE_INT_ST_M (RTC_CNTL_SDIO_IDLE_INT_ST_V << RTC_CNTL_SDIO_IDLE_INT_ST_S) -#define RTC_CNTL_SDIO_IDLE_INT_ST_V 0x00000001 -#define RTC_CNTL_SDIO_IDLE_INT_ST_S 2 - -/* RTC_CNTL_SLP_REJECT_INT_ST : RO; bitpos: [1]; default: 0; - * sleep reject interrupt state - */ - -#define RTC_CNTL_SLP_REJECT_INT_ST (BIT(1)) -#define RTC_CNTL_SLP_REJECT_INT_ST_M (RTC_CNTL_SLP_REJECT_INT_ST_V << RTC_CNTL_SLP_REJECT_INT_ST_S) -#define RTC_CNTL_SLP_REJECT_INT_ST_V 0x00000001 -#define RTC_CNTL_SLP_REJECT_INT_ST_S 1 - -/* RTC_CNTL_SLP_WAKEUP_INT_ST : RO; bitpos: [0]; default: 0; - * sleep wakeup interrupt state - */ - -#define RTC_CNTL_SLP_WAKEUP_INT_ST (BIT(0)) -#define RTC_CNTL_SLP_WAKEUP_INT_ST_M (RTC_CNTL_SLP_WAKEUP_INT_ST_V << RTC_CNTL_SLP_WAKEUP_INT_ST_S) -#define RTC_CNTL_SLP_WAKEUP_INT_ST_V 0x00000001 -#define RTC_CNTL_SLP_WAKEUP_INT_ST_S 0 - -/* RTC_CNTL_INT_CLR_RTC_REG register - * Clear rtc_interrupt register - */ - -#define RTC_CNTL_INT_CLR_RTC_REG (DR_REG_RTCCNTL_BASE + 0x4c) - -/* RTC_CNTL_GLITCH_DET_INT_CLR : WO; bitpos: [19]; default: 0; - * Clear glitch det interrupt state - */ - -#define RTC_CNTL_GLITCH_DET_INT_CLR (BIT(19)) -#define RTC_CNTL_GLITCH_DET_INT_CLR_M (RTC_CNTL_GLITCH_DET_INT_CLR_V << RTC_CNTL_GLITCH_DET_INT_CLR_S) -#define RTC_CNTL_GLITCH_DET_INT_CLR_V 0x00000001 -#define RTC_CNTL_GLITCH_DET_INT_CLR_S 19 - -/* RTC_CNTL_TOUCH_TIMEOUT_INT_CLR : WO; bitpos: [18]; default: 0; - * Clear touch timeout interrupt state - */ - -#define RTC_CNTL_TOUCH_TIMEOUT_INT_CLR (BIT(18)) -#define RTC_CNTL_TOUCH_TIMEOUT_INT_CLR_M (RTC_CNTL_TOUCH_TIMEOUT_INT_CLR_V << RTC_CNTL_TOUCH_TIMEOUT_INT_CLR_S) -#define RTC_CNTL_TOUCH_TIMEOUT_INT_CLR_V 0x00000001 -#define RTC_CNTL_TOUCH_TIMEOUT_INT_CLR_S 18 - -/* RTC_CNTL_COCPU_TRAP_INT_CLR : WO; bitpos: [17]; default: 0; - * Clear cocpu trap interrupt state - */ - -#define RTC_CNTL_COCPU_TRAP_INT_CLR (BIT(17)) -#define RTC_CNTL_COCPU_TRAP_INT_CLR_M (RTC_CNTL_COCPU_TRAP_INT_CLR_V << RTC_CNTL_COCPU_TRAP_INT_CLR_S) -#define RTC_CNTL_COCPU_TRAP_INT_CLR_V 0x00000001 -#define RTC_CNTL_COCPU_TRAP_INT_CLR_S 17 - -/* RTC_CNTL_XTAL32K_DEAD_INT_CLR : WO; bitpos: [16]; default: 0; - * Clear RTC WDT interrupt state - */ - -#define RTC_CNTL_XTAL32K_DEAD_INT_CLR (BIT(16)) -#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_M (RTC_CNTL_XTAL32K_DEAD_INT_CLR_V << RTC_CNTL_XTAL32K_DEAD_INT_CLR_S) -#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_V 0x00000001 -#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_S 16 - -/* RTC_CNTL_SWD_INT_CLR : WO; bitpos: [15]; default: 0; - * Clear super watch dog interrupt state - */ - -#define RTC_CNTL_SWD_INT_CLR (BIT(15)) -#define RTC_CNTL_SWD_INT_CLR_M (RTC_CNTL_SWD_INT_CLR_V << RTC_CNTL_SWD_INT_CLR_S) -#define RTC_CNTL_SWD_INT_CLR_V 0x00000001 -#define RTC_CNTL_SWD_INT_CLR_S 15 - -/* RTC_CNTL_SARADC2_INT_CLR : WO; bitpos: [14]; default: 0; - * Clear saradc2 interrupt state - */ - -#define RTC_CNTL_SARADC2_INT_CLR (BIT(14)) -#define RTC_CNTL_SARADC2_INT_CLR_M (RTC_CNTL_SARADC2_INT_CLR_V << RTC_CNTL_SARADC2_INT_CLR_S) -#define RTC_CNTL_SARADC2_INT_CLR_V 0x00000001 -#define RTC_CNTL_SARADC2_INT_CLR_S 14 - -/* RTC_CNTL_COCPU_INT_CLR : WO; bitpos: [13]; default: 0; - * Clear riscV cocpu interrupt state - */ - -#define RTC_CNTL_COCPU_INT_CLR (BIT(13)) -#define RTC_CNTL_COCPU_INT_CLR_M (RTC_CNTL_COCPU_INT_CLR_V << RTC_CNTL_COCPU_INT_CLR_S) -#define RTC_CNTL_COCPU_INT_CLR_V 0x00000001 -#define RTC_CNTL_COCPU_INT_CLR_S 13 - -/* RTC_CNTL_TSENS_INT_CLR : WO; bitpos: [12]; default: 0; - * Clear tsens interrupt state - */ - -#define RTC_CNTL_TSENS_INT_CLR (BIT(12)) -#define RTC_CNTL_TSENS_INT_CLR_M (RTC_CNTL_TSENS_INT_CLR_V << RTC_CNTL_TSENS_INT_CLR_S) -#define RTC_CNTL_TSENS_INT_CLR_V 0x00000001 -#define RTC_CNTL_TSENS_INT_CLR_S 12 - -/* RTC_CNTL_SARADC1_INT_CLR : WO; bitpos: [11]; default: 0; - * Clear saradc1 interrupt state - */ - -#define RTC_CNTL_SARADC1_INT_CLR (BIT(11)) -#define RTC_CNTL_SARADC1_INT_CLR_M (RTC_CNTL_SARADC1_INT_CLR_V << RTC_CNTL_SARADC1_INT_CLR_S) -#define RTC_CNTL_SARADC1_INT_CLR_V 0x00000001 -#define RTC_CNTL_SARADC1_INT_CLR_S 11 - -/* RTC_CNTL_MAIN_TIMER_INT_CLR : WO; bitpos: [10]; default: 0; - * Clear RTC main timer interrupt state - */ - -#define RTC_CNTL_MAIN_TIMER_INT_CLR (BIT(10)) -#define RTC_CNTL_MAIN_TIMER_INT_CLR_M (RTC_CNTL_MAIN_TIMER_INT_CLR_V << RTC_CNTL_MAIN_TIMER_INT_CLR_S) -#define RTC_CNTL_MAIN_TIMER_INT_CLR_V 0x00000001 -#define RTC_CNTL_MAIN_TIMER_INT_CLR_S 10 - -/* RTC_CNTL_BROWN_OUT_INT_CLR : WO; bitpos: [9]; default: 0; - * Clear brown out interrupt state - */ - -#define RTC_CNTL_BROWN_OUT_INT_CLR (BIT(9)) -#define RTC_CNTL_BROWN_OUT_INT_CLR_M (RTC_CNTL_BROWN_OUT_INT_CLR_V << RTC_CNTL_BROWN_OUT_INT_CLR_S) -#define RTC_CNTL_BROWN_OUT_INT_CLR_V 0x00000001 -#define RTC_CNTL_BROWN_OUT_INT_CLR_S 9 - -/* RTC_CNTL_TOUCH_INACTIVE_INT_CLR : WO; bitpos: [8]; default: 0; - * Clear touch inactive interrupt state - */ - -#define RTC_CNTL_TOUCH_INACTIVE_INT_CLR (BIT(8)) -#define RTC_CNTL_TOUCH_INACTIVE_INT_CLR_M (RTC_CNTL_TOUCH_INACTIVE_INT_CLR_V << RTC_CNTL_TOUCH_INACTIVE_INT_CLR_S) -#define RTC_CNTL_TOUCH_INACTIVE_INT_CLR_V 0x00000001 -#define RTC_CNTL_TOUCH_INACTIVE_INT_CLR_S 8 - -/* RTC_CNTL_TOUCH_ACTIVE_INT_CLR : WO; bitpos: [7]; default: 0; - * Clear touch active interrupt state - */ - -#define RTC_CNTL_TOUCH_ACTIVE_INT_CLR (BIT(7)) -#define RTC_CNTL_TOUCH_ACTIVE_INT_CLR_M (RTC_CNTL_TOUCH_ACTIVE_INT_CLR_V << RTC_CNTL_TOUCH_ACTIVE_INT_CLR_S) -#define RTC_CNTL_TOUCH_ACTIVE_INT_CLR_V 0x00000001 -#define RTC_CNTL_TOUCH_ACTIVE_INT_CLR_S 7 - -/* RTC_CNTL_TOUCH_DONE_INT_CLR : WO; bitpos: [6]; default: 0; - * Clear touch done interrupt state - */ - -#define RTC_CNTL_TOUCH_DONE_INT_CLR (BIT(6)) -#define RTC_CNTL_TOUCH_DONE_INT_CLR_M (RTC_CNTL_TOUCH_DONE_INT_CLR_V << RTC_CNTL_TOUCH_DONE_INT_CLR_S) -#define RTC_CNTL_TOUCH_DONE_INT_CLR_V 0x00000001 -#define RTC_CNTL_TOUCH_DONE_INT_CLR_S 6 - -/* RTC_CNTL_ULP_CP_INT_CLR : WO; bitpos: [5]; default: 0; - * Clear ULP-coprocessor interrupt state - */ - -#define RTC_CNTL_ULP_CP_INT_CLR (BIT(5)) -#define RTC_CNTL_ULP_CP_INT_CLR_M (RTC_CNTL_ULP_CP_INT_CLR_V << RTC_CNTL_ULP_CP_INT_CLR_S) -#define RTC_CNTL_ULP_CP_INT_CLR_V 0x00000001 -#define RTC_CNTL_ULP_CP_INT_CLR_S 5 - -/* RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR : WO; bitpos: [4]; default: 0; - * Clear touch complete a loop interrupt state - */ - -#define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR (BIT(4)) -#define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR_M (RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR_V << RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR_S) -#define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR_V 0x00000001 -#define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR_S 4 - -/* RTC_CNTL_WDT_INT_CLR : WO; bitpos: [3]; default: 0; - * Clear RTC WDT interrupt state - */ - -#define RTC_CNTL_WDT_INT_CLR (BIT(3)) -#define RTC_CNTL_WDT_INT_CLR_M (RTC_CNTL_WDT_INT_CLR_V << RTC_CNTL_WDT_INT_CLR_S) -#define RTC_CNTL_WDT_INT_CLR_V 0x00000001 -#define RTC_CNTL_WDT_INT_CLR_S 3 - -/* RTC_CNTL_SDIO_IDLE_INT_CLR : WO; bitpos: [2]; default: 0; - * Clear SDIO idle interrupt state - */ - -#define RTC_CNTL_SDIO_IDLE_INT_CLR (BIT(2)) -#define RTC_CNTL_SDIO_IDLE_INT_CLR_M (RTC_CNTL_SDIO_IDLE_INT_CLR_V << RTC_CNTL_SDIO_IDLE_INT_CLR_S) -#define RTC_CNTL_SDIO_IDLE_INT_CLR_V 0x00000001 -#define RTC_CNTL_SDIO_IDLE_INT_CLR_S 2 - -/* RTC_CNTL_SLP_REJECT_INT_CLR : WO; bitpos: [1]; default: 0; - * Clear sleep reject interrupt state - */ - -#define RTC_CNTL_SLP_REJECT_INT_CLR (BIT(1)) -#define RTC_CNTL_SLP_REJECT_INT_CLR_M (RTC_CNTL_SLP_REJECT_INT_CLR_V << RTC_CNTL_SLP_REJECT_INT_CLR_S) -#define RTC_CNTL_SLP_REJECT_INT_CLR_V 0x00000001 -#define RTC_CNTL_SLP_REJECT_INT_CLR_S 1 - -/* RTC_CNTL_SLP_WAKEUP_INT_CLR : WO; bitpos: [0]; default: 0; - * Clear sleep wakeup interrupt state - */ - -#define RTC_CNTL_SLP_WAKEUP_INT_CLR (BIT(0)) -#define RTC_CNTL_SLP_WAKEUP_INT_CLR_M (RTC_CNTL_SLP_WAKEUP_INT_CLR_V << RTC_CNTL_SLP_WAKEUP_INT_CLR_S) -#define RTC_CNTL_SLP_WAKEUP_INT_CLR_V 0x00000001 -#define RTC_CNTL_SLP_WAKEUP_INT_CLR_S 0 - -/* RTC_CNTL_STORE0_REG register - * reservation register0 - */ - -#define RTC_CNTL_STORE0_REG (DR_REG_RTCCNTL_BASE + 0x50) - -/* RTC_CNTL_SCRATCH0 : R/W; bitpos: [31:0]; default: 0; - * reservation register0 - */ - -#define RTC_CNTL_SCRATCH0 0xFFFFFFFF -#define RTC_CNTL_SCRATCH0_M (RTC_CNTL_SCRATCH0_V << RTC_CNTL_SCRATCH0_S) -#define RTC_CNTL_SCRATCH0_V 0xFFFFFFFF -#define RTC_CNTL_SCRATCH0_S 0 - -/* RTC_CNTL_STORE1_REG register - * reservation register1 - */ - -#define RTC_CNTL_STORE1_REG (DR_REG_RTCCNTL_BASE + 0x54) - -#define RTC_SLOW_CLK_CAL_REG RTC_CNTL_STORE1_REG - -/* RTC_CNTL_SCRATCH1 : R/W; bitpos: [31:0]; default: 0; - * reservation register1 - */ - -#define RTC_CNTL_SCRATCH1 0xFFFFFFFF -#define RTC_CNTL_SCRATCH1_M (RTC_CNTL_SCRATCH1_V << RTC_CNTL_SCRATCH1_S) -#define RTC_CNTL_SCRATCH1_V 0xFFFFFFFF -#define RTC_CNTL_SCRATCH1_S 0 - -/* RTC_CNTL_STORE2_REG register - * reservation register2 - */ - -#define RTC_CNTL_STORE2_REG (DR_REG_RTCCNTL_BASE + 0x58) - -/* RTC_CNTL_SCRATCH2 : R/W; bitpos: [31:0]; default: 0; - * reservation register2 - */ - -#define RTC_CNTL_SCRATCH2 0xFFFFFFFF -#define RTC_CNTL_SCRATCH2_M (RTC_CNTL_SCRATCH2_V << RTC_CNTL_SCRATCH2_S) -#define RTC_CNTL_SCRATCH2_V 0xFFFFFFFF -#define RTC_CNTL_SCRATCH2_S 0 - -/* RTC_CNTL_STORE3_REG register - * reservation register3 - */ - -#define RTC_CNTL_STORE3_REG (DR_REG_RTCCNTL_BASE + 0x5c) - -/* RTC_CNTL_SCRATCH3 : R/W; bitpos: [31:0]; default: 0; - * reservation register3 - */ - -#define RTC_CNTL_SCRATCH3 0xFFFFFFFF -#define RTC_CNTL_SCRATCH3_M (RTC_CNTL_SCRATCH3_V << RTC_CNTL_SCRATCH3_S) -#define RTC_CNTL_SCRATCH3_V 0xFFFFFFFF -#define RTC_CNTL_SCRATCH3_S 0 - -/* RTC_CNTL_EXT_XTL_CONF_REG register - * configure 32k xtal register - */ - -#define RTC_CNTL_EXT_XTL_CONF_REG (DR_REG_RTCCNTL_BASE + 0x60) - -/* RTC_CNTL_XTL_EXT_CTR_EN : R/W; bitpos: [31]; default: 0; - * enable gpio power down XTAL - */ - -#define RTC_CNTL_XTL_EXT_CTR_EN (BIT(31)) -#define RTC_CNTL_XTL_EXT_CTR_EN_M (RTC_CNTL_XTL_EXT_CTR_EN_V << RTC_CNTL_XTL_EXT_CTR_EN_S) -#define RTC_CNTL_XTL_EXT_CTR_EN_V 0x00000001 -#define RTC_CNTL_XTL_EXT_CTR_EN_S 31 - -/* RTC_CNTL_XTL_EXT_CTR_LV : R/W; bitpos: [30]; default: 0; - * 0: power down XTAL at high level 1: power down XTAL at low level - */ - -#define RTC_CNTL_XTL_EXT_CTR_LV (BIT(30)) -#define RTC_CNTL_XTL_EXT_CTR_LV_M (RTC_CNTL_XTL_EXT_CTR_LV_V << RTC_CNTL_XTL_EXT_CTR_LV_S) -#define RTC_CNTL_XTL_EXT_CTR_LV_V 0x00000001 -#define RTC_CNTL_XTL_EXT_CTR_LV_S 30 - -/* RTC_CNTL_XTAL32K_GPIO_SEL : R/W; bitpos: [23]; default: 0; - * XTAL_32K sel. 0: external XTAL_32K 1: CLK from RTC pad X32P_C - */ - -#define RTC_CNTL_XTAL32K_GPIO_SEL (BIT(23)) -#define RTC_CNTL_XTAL32K_GPIO_SEL_M (RTC_CNTL_XTAL32K_GPIO_SEL_V << RTC_CNTL_XTAL32K_GPIO_SEL_S) -#define RTC_CNTL_XTAL32K_GPIO_SEL_V 0x00000001 -#define RTC_CNTL_XTAL32K_GPIO_SEL_S 23 - -/* RTC_CNTL_WDT_STATE : RO; bitpos: [22:20]; default: 0; - * state of 32k_wdt - */ - -#define RTC_CNTL_WDT_STATE 0x00000007 -#define RTC_CNTL_WDT_STATE_M (RTC_CNTL_WDT_STATE_V << RTC_CNTL_WDT_STATE_S) -#define RTC_CNTL_WDT_STATE_V 0x00000007 -#define RTC_CNTL_WDT_STATE_S 20 - -/* RTC_CNTL_DAC_XTAL_32K : R/W; bitpos: [19:17]; default: 3; - * DAC_XTAL_32K - */ - -#define RTC_CNTL_DAC_XTAL_32K 0x00000007 -#define RTC_CNTL_DAC_XTAL_32K_M (RTC_CNTL_DAC_XTAL_32K_V << RTC_CNTL_DAC_XTAL_32K_S) -#define RTC_CNTL_DAC_XTAL_32K_V 0x00000007 -#define RTC_CNTL_DAC_XTAL_32K_S 17 - -/* RTC_CNTL_XPD_XTAL_32K : R/W; bitpos: [16]; default: 0; - * XPD_XTAL_32K - */ - -#define RTC_CNTL_XPD_XTAL_32K (BIT(16)) -#define RTC_CNTL_XPD_XTAL_32K_M (RTC_CNTL_XPD_XTAL_32K_V << RTC_CNTL_XPD_XTAL_32K_S) -#define RTC_CNTL_XPD_XTAL_32K_V 0x00000001 -#define RTC_CNTL_XPD_XTAL_32K_S 16 - -/* RTC_CNTL_DRES_XTAL_32K : R/W; bitpos: [15:13]; default: 3; - * DRES_XTAL_32K - */ - -#define RTC_CNTL_DRES_XTAL_32K 0x00000007 -#define RTC_CNTL_DRES_XTAL_32K_M (RTC_CNTL_DRES_XTAL_32K_V << RTC_CNTL_DRES_XTAL_32K_S) -#define RTC_CNTL_DRES_XTAL_32K_V 0x00000007 -#define RTC_CNTL_DRES_XTAL_32K_S 13 - -/* RTC_CNTL_DGM_XTAL_32K : R/W; bitpos: [12:10]; default: 3; - * xtal_32k gm control - */ - -#define RTC_CNTL_DGM_XTAL_32K 0x00000007 -#define RTC_CNTL_DGM_XTAL_32K_M (RTC_CNTL_DGM_XTAL_32K_V << RTC_CNTL_DGM_XTAL_32K_S) -#define RTC_CNTL_DGM_XTAL_32K_V 0x00000007 -#define RTC_CNTL_DGM_XTAL_32K_S 10 - -/* RTC_CNTL_DBUF_XTAL_32K : R/W; bitpos: [9]; default: 0; - * 0: single-end buffer 1: differential buffer - */ - -#define RTC_CNTL_DBUF_XTAL_32K (BIT(9)) -#define RTC_CNTL_DBUF_XTAL_32K_M (RTC_CNTL_DBUF_XTAL_32K_V << RTC_CNTL_DBUF_XTAL_32K_S) -#define RTC_CNTL_DBUF_XTAL_32K_V 0x00000001 -#define RTC_CNTL_DBUF_XTAL_32K_S 9 - -/* RTC_CNTL_ENCKINIT_XTAL_32K : R/W; bitpos: [8]; default: 0; - * apply an internal clock to help xtal 32k to start - */ - -#define RTC_CNTL_ENCKINIT_XTAL_32K (BIT(8)) -#define RTC_CNTL_ENCKINIT_XTAL_32K_M (RTC_CNTL_ENCKINIT_XTAL_32K_V << RTC_CNTL_ENCKINIT_XTAL_32K_S) -#define RTC_CNTL_ENCKINIT_XTAL_32K_V 0x00000001 -#define RTC_CNTL_ENCKINIT_XTAL_32K_S 8 - -/* RTC_CNTL_XTAL32K_XPD_FORCE : R/W; bitpos: [7]; default: 1; - * Xtal 32k xpd control by sw or fsm - */ - -#define RTC_CNTL_XTAL32K_XPD_FORCE (BIT(7)) -#define RTC_CNTL_XTAL32K_XPD_FORCE_M (RTC_CNTL_XTAL32K_XPD_FORCE_V << RTC_CNTL_XTAL32K_XPD_FORCE_S) -#define RTC_CNTL_XTAL32K_XPD_FORCE_V 0x00000001 -#define RTC_CNTL_XTAL32K_XPD_FORCE_S 7 - -/* RTC_CNTL_XTAL32K_AUTO_RETURN : R/W; bitpos: [6]; default: 0; - * xtal 32k switch back xtal when xtal is restarted - */ - -#define RTC_CNTL_XTAL32K_AUTO_RETURN (BIT(6)) -#define RTC_CNTL_XTAL32K_AUTO_RETURN_M (RTC_CNTL_XTAL32K_AUTO_RETURN_V << RTC_CNTL_XTAL32K_AUTO_RETURN_S) -#define RTC_CNTL_XTAL32K_AUTO_RETURN_V 0x00000001 -#define RTC_CNTL_XTAL32K_AUTO_RETURN_S 6 - -/* RTC_CNTL_XTAL32K_AUTO_RESTART : R/W; bitpos: [5]; default: 0; - * xtal 32k restart xtal when xtal is dead - */ - -#define RTC_CNTL_XTAL32K_AUTO_RESTART (BIT(5)) -#define RTC_CNTL_XTAL32K_AUTO_RESTART_M (RTC_CNTL_XTAL32K_AUTO_RESTART_V << RTC_CNTL_XTAL32K_AUTO_RESTART_S) -#define RTC_CNTL_XTAL32K_AUTO_RESTART_V 0x00000001 -#define RTC_CNTL_XTAL32K_AUTO_RESTART_S 5 - -/* RTC_CNTL_XTAL32K_AUTO_BACKUP : R/W; bitpos: [4]; default: 0; - * xtal 32k switch to back up clock when xtal is dead - */ - -#define RTC_CNTL_XTAL32K_AUTO_BACKUP (BIT(4)) -#define RTC_CNTL_XTAL32K_AUTO_BACKUP_M (RTC_CNTL_XTAL32K_AUTO_BACKUP_V << RTC_CNTL_XTAL32K_AUTO_BACKUP_S) -#define RTC_CNTL_XTAL32K_AUTO_BACKUP_V 0x00000001 -#define RTC_CNTL_XTAL32K_AUTO_BACKUP_S 4 - -/* RTC_CNTL_XTAL32K_EXT_CLK_FO : R/W; bitpos: [3]; default: 0; - * xtal 32k external xtal clock force on - */ - -#define RTC_CNTL_XTAL32K_EXT_CLK_FO (BIT(3)) -#define RTC_CNTL_XTAL32K_EXT_CLK_FO_M (RTC_CNTL_XTAL32K_EXT_CLK_FO_V << RTC_CNTL_XTAL32K_EXT_CLK_FO_S) -#define RTC_CNTL_XTAL32K_EXT_CLK_FO_V 0x00000001 -#define RTC_CNTL_XTAL32K_EXT_CLK_FO_S 3 - -/* RTC_CNTL_XTAL32K_WDT_RESET : R/W; bitpos: [2]; default: 0; - * xtal 32k watch dog sw reset - */ - -#define RTC_CNTL_XTAL32K_WDT_RESET (BIT(2)) -#define RTC_CNTL_XTAL32K_WDT_RESET_M (RTC_CNTL_XTAL32K_WDT_RESET_V << RTC_CNTL_XTAL32K_WDT_RESET_S) -#define RTC_CNTL_XTAL32K_WDT_RESET_V 0x00000001 -#define RTC_CNTL_XTAL32K_WDT_RESET_S 2 - -/* RTC_CNTL_XTAL32K_WDT_CLK_FO : R/W; bitpos: [1]; default: 0; - * xtal 32k watch dog clock force on - */ - -#define RTC_CNTL_XTAL32K_WDT_CLK_FO (BIT(1)) -#define RTC_CNTL_XTAL32K_WDT_CLK_FO_M (RTC_CNTL_XTAL32K_WDT_CLK_FO_V << RTC_CNTL_XTAL32K_WDT_CLK_FO_S) -#define RTC_CNTL_XTAL32K_WDT_CLK_FO_V 0x00000001 -#define RTC_CNTL_XTAL32K_WDT_CLK_FO_S 1 - -/* RTC_CNTL_XTAL32K_WDT_EN : R/W; bitpos: [0]; default: 0; - * xtal 32k watch dog enable - */ - -#define RTC_CNTL_XTAL32K_WDT_EN (BIT(0)) -#define RTC_CNTL_XTAL32K_WDT_EN_M (RTC_CNTL_XTAL32K_WDT_EN_V << RTC_CNTL_XTAL32K_WDT_EN_S) -#define RTC_CNTL_XTAL32K_WDT_EN_V 0x00000001 -#define RTC_CNTL_XTAL32K_WDT_EN_S 0 - -/* RTC_CNTL_EXT_WAKEUP_CONF_REG register - * configure gpio wakeup register - */ - -#define RTC_CNTL_EXT_WAKEUP_CONF_REG (DR_REG_RTCCNTL_BASE + 0x64) - -/* RTC_CNTL_EXT_WAKEUP1_LV : R/W; bitpos: [31]; default: 0; - * 0: external wakeup at low level 1: external wakeup at high level - */ - -#define RTC_CNTL_EXT_WAKEUP1_LV (BIT(31)) -#define RTC_CNTL_EXT_WAKEUP1_LV_M (RTC_CNTL_EXT_WAKEUP1_LV_V << RTC_CNTL_EXT_WAKEUP1_LV_S) -#define RTC_CNTL_EXT_WAKEUP1_LV_V 0x00000001 -#define RTC_CNTL_EXT_WAKEUP1_LV_S 31 - -/* RTC_CNTL_EXT_WAKEUP0_LV : R/W; bitpos: [30]; default: 0; - * 0: external wakeup at low level 1: external wakeup at high level - */ - -#define RTC_CNTL_EXT_WAKEUP0_LV (BIT(30)) -#define RTC_CNTL_EXT_WAKEUP0_LV_M (RTC_CNTL_EXT_WAKEUP0_LV_V << RTC_CNTL_EXT_WAKEUP0_LV_S) -#define RTC_CNTL_EXT_WAKEUP0_LV_V 0x00000001 -#define RTC_CNTL_EXT_WAKEUP0_LV_S 30 - -/* RTC_CNTL_GPIO_WAKEUP_FILTER : R/W; bitpos: [29]; default: 0; - * enable filter for gpio wakeup event - */ - -#define RTC_CNTL_GPIO_WAKEUP_FILTER (BIT(29)) -#define RTC_CNTL_GPIO_WAKEUP_FILTER_M (RTC_CNTL_GPIO_WAKEUP_FILTER_V << RTC_CNTL_GPIO_WAKEUP_FILTER_S) -#define RTC_CNTL_GPIO_WAKEUP_FILTER_V 0x00000001 -#define RTC_CNTL_GPIO_WAKEUP_FILTER_S 29 - -/* RTC_CNTL_SLP_REJECT_CONF_REG register - * configure sleep reject register - */ - -#define RTC_CNTL_SLP_REJECT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x68) - -/* RTC_CNTL_DEEP_SLP_REJECT_EN : R/W; bitpos: [31]; default: 0; - * enable reject for deep sleep - */ - -#define RTC_CNTL_DEEP_SLP_REJECT_EN (BIT(31)) -#define RTC_CNTL_DEEP_SLP_REJECT_EN_M (RTC_CNTL_DEEP_SLP_REJECT_EN_V << RTC_CNTL_DEEP_SLP_REJECT_EN_S) -#define RTC_CNTL_DEEP_SLP_REJECT_EN_V 0x00000001 -#define RTC_CNTL_DEEP_SLP_REJECT_EN_S 31 - -/* RTC_CNTL_LIGHT_SLP_REJECT_EN : R/W; bitpos: [30]; default: 0; - * enable reject for light sleep - */ - -#define RTC_CNTL_LIGHT_SLP_REJECT_EN (BIT(30)) -#define RTC_CNTL_LIGHT_SLP_REJECT_EN_M (RTC_CNTL_LIGHT_SLP_REJECT_EN_V << RTC_CNTL_LIGHT_SLP_REJECT_EN_S) -#define RTC_CNTL_LIGHT_SLP_REJECT_EN_V 0x00000001 -#define RTC_CNTL_LIGHT_SLP_REJECT_EN_S 30 - -/* RTC_CNTL_SLEEP_REJECT_ENA : R/W; bitpos: [29:13]; default: 0; - * sleep reject enable - */ - -#define RTC_CNTL_SLEEP_REJECT_ENA 0x0001FFFF -#define RTC_CNTL_SLEEP_REJECT_ENA_M (RTC_CNTL_SLEEP_REJECT_ENA_V << RTC_CNTL_SLEEP_REJECT_ENA_S) -#define RTC_CNTL_SLEEP_REJECT_ENA_V 0x0001FFFF -#define RTC_CNTL_SLEEP_REJECT_ENA_S 13 - -/* RTC_CNTL_CPU_PERIOD_CONF_REG register - * CPU sel option - */ - -#define RTC_CNTL_CPU_PERIOD_CONF_REG (DR_REG_RTCCNTL_BASE + 0x6c) - -/* RTC_CNTL_CPUPERIOD_SEL : R/W; bitpos: [31:30]; default: 0; */ - -#define RTC_CNTL_CPUPERIOD_SEL 0x00000003 -#define RTC_CNTL_CPUPERIOD_SEL_M (RTC_CNTL_CPUPERIOD_SEL_V << RTC_CNTL_CPUPERIOD_SEL_S) -#define RTC_CNTL_CPUPERIOD_SEL_V 0x00000003 -#define RTC_CNTL_CPUPERIOD_SEL_S 30 - -/* RTC_CNTL_CPUSEL_CONF : R/W; bitpos: [29]; default: 0; - * CPU sel option - */ - -#define RTC_CNTL_CPUSEL_CONF (BIT(29)) -#define RTC_CNTL_CPUSEL_CONF_M (RTC_CNTL_CPUSEL_CONF_V << RTC_CNTL_CPUSEL_CONF_S) -#define RTC_CNTL_CPUSEL_CONF_V 0x00000001 -#define RTC_CNTL_CPUSEL_CONF_S 29 - -/* RTC_CNTL_SDIO_ACT_CONF_REG register - * configure sdio active register - */ - -#define RTC_CNTL_SDIO_ACT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x70) - -/* RTC_CNTL_SDIO_ACT_DNUM : R/W; bitpos: [31:22]; default: 0; - * configure sdio act dnum - */ - -#define RTC_CNTL_SDIO_ACT_DNUM 0x000003FF -#define RTC_CNTL_SDIO_ACT_DNUM_M (RTC_CNTL_SDIO_ACT_DNUM_V << RTC_CNTL_SDIO_ACT_DNUM_S) -#define RTC_CNTL_SDIO_ACT_DNUM_V 0x000003FF -#define RTC_CNTL_SDIO_ACT_DNUM_S 22 - -/* RTC_CNTL_CLK_CONF_REG register - * configure rtc clk register - */ - -#define RTC_CNTL_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x74) - -/* RTC_CNTL_ANA_CLK_RTC_SEL : R/W; bitpos: [31:30]; default: 0; - * slow clk sel 0 : 90K rtc_clk 1 : 32k XTAL 2 : 8md256 - */ - -#define RTC_CNTL_ANA_CLK_RTC_SEL 0x00000003 -#define RTC_CNTL_ANA_CLK_RTC_SEL_M (RTC_CNTL_ANA_CLK_RTC_SEL_V << RTC_CNTL_ANA_CLK_RTC_SEL_S) -#define RTC_CNTL_ANA_CLK_RTC_SEL_V 0x00000003 -#define RTC_CNTL_ANA_CLK_RTC_SEL_S 30 - -/* RTC_CNTL_FAST_CLK_RTC_SEL : R/W; bitpos: [29]; default: 0; - * fast_clk_rtc sel. 0: XTAL div 4 1: CK8M - */ - -#define RTC_CNTL_FAST_CLK_RTC_SEL (BIT(29)) -#define RTC_CNTL_FAST_CLK_RTC_SEL_M (RTC_CNTL_FAST_CLK_RTC_SEL_V << RTC_CNTL_FAST_CLK_RTC_SEL_S) -#define RTC_CNTL_FAST_CLK_RTC_SEL_V 0x00000001 -#define RTC_CNTL_FAST_CLK_RTC_SEL_S 29 - -/* RTC_CNTL_CK8M_FORCE_PU : R/W; bitpos: [26]; default: 0; - * CK8M force power up - */ - -#define RTC_CNTL_CK8M_FORCE_PU (BIT(26)) -#define RTC_CNTL_CK8M_FORCE_PU_M (RTC_CNTL_CK8M_FORCE_PU_V << RTC_CNTL_CK8M_FORCE_PU_S) -#define RTC_CNTL_CK8M_FORCE_PU_V 0x00000001 -#define RTC_CNTL_CK8M_FORCE_PU_S 26 - -/* RTC_CNTL_CK8M_FORCE_PD : R/W; bitpos: [25]; default: 0; - * CK8M force power down - */ - -#define RTC_CNTL_CK8M_FORCE_PD (BIT(25)) -#define RTC_CNTL_CK8M_FORCE_PD_M (RTC_CNTL_CK8M_FORCE_PD_V << RTC_CNTL_CK8M_FORCE_PD_S) -#define RTC_CNTL_CK8M_FORCE_PD_V 0x00000001 -#define RTC_CNTL_CK8M_FORCE_PD_S 25 - -/* RTC_CNTL_CK8M_DFREQ : R/W; bitpos: [24:17]; default: 172; - * CK8M_DFREQ - */ - -#define RTC_CNTL_CK8M_DFREQ 0x000000FF -#define RTC_CNTL_CK8M_DFREQ_M (RTC_CNTL_CK8M_DFREQ_V << RTC_CNTL_CK8M_DFREQ_S) -#define RTC_CNTL_CK8M_DFREQ_V 0x000000FF -#define RTC_CNTL_CK8M_DFREQ_S 17 - -/* RTC_CNTL_CK8M_FORCE_NOGATING : R/W; bitpos: [16]; default: 0; - * CK8M force no gating during sleep - */ - -#define RTC_CNTL_CK8M_FORCE_NOGATING (BIT(16)) -#define RTC_CNTL_CK8M_FORCE_NOGATING_M (RTC_CNTL_CK8M_FORCE_NOGATING_V << RTC_CNTL_CK8M_FORCE_NOGATING_S) -#define RTC_CNTL_CK8M_FORCE_NOGATING_V 0x00000001 -#define RTC_CNTL_CK8M_FORCE_NOGATING_S 16 - -/* RTC_CNTL_XTAL_FORCE_NOGATING : R/W; bitpos: [15]; default: 0; - * XTAL force no gating during sleep - */ - -#define RTC_CNTL_XTAL_FORCE_NOGATING (BIT(15)) -#define RTC_CNTL_XTAL_FORCE_NOGATING_M (RTC_CNTL_XTAL_FORCE_NOGATING_V << RTC_CNTL_XTAL_FORCE_NOGATING_S) -#define RTC_CNTL_XTAL_FORCE_NOGATING_V 0x00000001 -#define RTC_CNTL_XTAL_FORCE_NOGATING_S 15 - -/* RTC_CNTL_CK8M_DIV_SEL : R/W; bitpos: [14:12]; default: 3; - * divider = reg_ck8m_div_sel + 1 - */ - -#define RTC_CNTL_CK8M_DIV_SEL 0x00000007 -#define RTC_CNTL_CK8M_DIV_SEL_M (RTC_CNTL_CK8M_DIV_SEL_V << RTC_CNTL_CK8M_DIV_SEL_S) -#define RTC_CNTL_CK8M_DIV_SEL_V 0x00000007 -#define RTC_CNTL_CK8M_DIV_SEL_S 12 - -/* RTC_CNTL_DIG_CLK8M_EN : R/W; bitpos: [10]; default: 0; - * enable CK8M for digital core (no relationship with RTC core) - */ - -#define RTC_CNTL_DIG_CLK8M_EN (BIT(10)) -#define RTC_CNTL_DIG_CLK8M_EN_M (RTC_CNTL_DIG_CLK8M_EN_V << RTC_CNTL_DIG_CLK8M_EN_S) -#define RTC_CNTL_DIG_CLK8M_EN_V 0x00000001 -#define RTC_CNTL_DIG_CLK8M_EN_S 10 - -/* RTC_CNTL_DIG_CLK8M_D256_EN : R/W; bitpos: [9]; default: 1; - * enable CK8M_D256_OUT for digital core (no relationship with RTC core) - */ - -#define RTC_CNTL_DIG_CLK8M_D256_EN (BIT(9)) -#define RTC_CNTL_DIG_CLK8M_D256_EN_M (RTC_CNTL_DIG_CLK8M_D256_EN_V << RTC_CNTL_DIG_CLK8M_D256_EN_S) -#define RTC_CNTL_DIG_CLK8M_D256_EN_V 0x00000001 -#define RTC_CNTL_DIG_CLK8M_D256_EN_S 9 - -/* RTC_CNTL_DIG_XTAL32K_EN : R/W; bitpos: [8]; default: 0; - * enable CK_XTAL_32K for digital core (no relationship with RTC core) - */ - -#define RTC_CNTL_DIG_XTAL32K_EN (BIT(8)) -#define RTC_CNTL_DIG_XTAL32K_EN_M (RTC_CNTL_DIG_XTAL32K_EN_V << RTC_CNTL_DIG_XTAL32K_EN_S) -#define RTC_CNTL_DIG_XTAL32K_EN_V 0x00000001 -#define RTC_CNTL_DIG_XTAL32K_EN_S 8 - -/* RTC_CNTL_ENB_CK8M_DIV : R/W; bitpos: [7]; default: 0; - * 1: CK8M_D256_OUT is actually CK8M 0: CK8M_D256_OUT is CK8M divided by - * 256 - */ - -#define RTC_CNTL_ENB_CK8M_DIV (BIT(7)) -#define RTC_CNTL_ENB_CK8M_DIV_M (RTC_CNTL_ENB_CK8M_DIV_V << RTC_CNTL_ENB_CK8M_DIV_S) -#define RTC_CNTL_ENB_CK8M_DIV_V 0x00000001 -#define RTC_CNTL_ENB_CK8M_DIV_S 7 - -/* RTC_CNTL_ENB_CK8M : R/W; bitpos: [6]; default: 0; - * disable CK8M and CK8M_D256_OUT - */ - -#define RTC_CNTL_ENB_CK8M (BIT(6)) -#define RTC_CNTL_ENB_CK8M_M (RTC_CNTL_ENB_CK8M_V << RTC_CNTL_ENB_CK8M_S) -#define RTC_CNTL_ENB_CK8M_V 0x00000001 -#define RTC_CNTL_ENB_CK8M_S 6 - -/* RTC_CNTL_CK8M_DIV : R/W; bitpos: [5:4]; default: 1; - * CK8M_D256_OUT divider. 00: div128 01: div256 10: div512 11: - * div1024. - */ - -#define RTC_CNTL_CK8M_DIV 0x00000003 -#define RTC_CNTL_CK8M_DIV_M (RTC_CNTL_CK8M_DIV_V << RTC_CNTL_CK8M_DIV_S) -#define RTC_CNTL_CK8M_DIV_V 0x00000003 -#define RTC_CNTL_CK8M_DIV_S 4 - -/* RTC_CNTL_CK8M_DIV_SEL_VLD : R/W; bitpos: [3]; default: 1; - * used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel - * then set vld to actually switch the clk - */ - -#define RTC_CNTL_CK8M_DIV_SEL_VLD (BIT(3)) -#define RTC_CNTL_CK8M_DIV_SEL_VLD_M (RTC_CNTL_CK8M_DIV_SEL_VLD_V << RTC_CNTL_CK8M_DIV_SEL_VLD_S) -#define RTC_CNTL_CK8M_DIV_SEL_VLD_V 0x00000001 -#define RTC_CNTL_CK8M_DIV_SEL_VLD_S 3 - -/* RTC_CNTL_SLOW_CLK_CONF_REG register - * configure rtc slow clk register - */ - -#define RTC_CNTL_SLOW_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x78) - -/* RTC_CNTL_SLOW_CLK_NEXT_EDGE : R/W; bitpos: [31]; default: 0; */ - -#define RTC_CNTL_SLOW_CLK_NEXT_EDGE (BIT(31)) -#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_M (RTC_CNTL_SLOW_CLK_NEXT_EDGE_V << RTC_CNTL_SLOW_CLK_NEXT_EDGE_S) -#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_V 0x00000001 -#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_S 31 - -/* RTC_CNTL_ANA_CLK_DIV : R/W; bitpos: [30:23]; default: 0; - * rtc_clk divider - */ - -#define RTC_CNTL_ANA_CLK_DIV 0x000000FF -#define RTC_CNTL_ANA_CLK_DIV_M (RTC_CNTL_ANA_CLK_DIV_V << RTC_CNTL_ANA_CLK_DIV_S) -#define RTC_CNTL_ANA_CLK_DIV_V 0x000000FF -#define RTC_CNTL_ANA_CLK_DIV_S 23 - -/* RTC_CNTL_ANA_CLK_DIV_VLD : R/W; bitpos: [22]; default: 1; - * used to sync div bus. clear vld before set reg_rtc_ana_clk_div then set - * vld to actually switch the clk - */ - -#define RTC_CNTL_ANA_CLK_DIV_VLD (BIT(22)) -#define RTC_CNTL_ANA_CLK_DIV_VLD_M (RTC_CNTL_ANA_CLK_DIV_VLD_V << RTC_CNTL_ANA_CLK_DIV_VLD_S) -#define RTC_CNTL_ANA_CLK_DIV_VLD_V 0x00000001 -#define RTC_CNTL_ANA_CLK_DIV_VLD_S 22 - -/* RTC_CNTL_SDIO_CONF_REG register - * configure vddsdio register - */ - -#define RTC_CNTL_SDIO_CONF_REG (DR_REG_RTCCNTL_BASE + 0x7c) - -/* RTC_CNTL_XPD_SDIO_REG : R/W; bitpos: [31]; default: 0; - * SW option for XPD_VOOSDIO. Only active when reg_sdio_force = 1 - */ - -#define RTC_CNTL_XPD_SDIO_REG (BIT(31)) -#define RTC_CNTL_XPD_SDIO_REG_M (RTC_CNTL_XPD_SDIO_REG_V << RTC_CNTL_XPD_SDIO_REG_S) -#define RTC_CNTL_XPD_SDIO_REG_V 0x00000001 -#define RTC_CNTL_XPD_SDIO_REG_S 31 - -/* RTC_CNTL_DREFH_SDIO : R/W; bitpos: [30:29]; default: 0; - * SW option for DREFH_SDIO. Only active when reg_sdio_force = 1 - */ - -#define RTC_CNTL_DREFH_SDIO 0x00000003 -#define RTC_CNTL_DREFH_SDIO_M (RTC_CNTL_DREFH_SDIO_V << RTC_CNTL_DREFH_SDIO_S) -#define RTC_CNTL_DREFH_SDIO_V 0x00000003 -#define RTC_CNTL_DREFH_SDIO_S 29 - -/* RTC_CNTL_DREFM_SDIO : R/W; bitpos: [28:27]; default: 0; - * SW option for DREFM_SDIO. Only active when reg_sdio_force = 1 - */ - -#define RTC_CNTL_DREFM_SDIO 0x00000003 -#define RTC_CNTL_DREFM_SDIO_M (RTC_CNTL_DREFM_SDIO_V << RTC_CNTL_DREFM_SDIO_S) -#define RTC_CNTL_DREFM_SDIO_V 0x00000003 -#define RTC_CNTL_DREFM_SDIO_S 27 - -/* RTC_CNTL_DREFL_SDIO : R/W; bitpos: [26:25]; default: 1; - * SW option for DREFL_SDIO. Only active when reg_sdio_force = 1 - */ - -#define RTC_CNTL_DREFL_SDIO 0x00000003 -#define RTC_CNTL_DREFL_SDIO_M (RTC_CNTL_DREFL_SDIO_V << RTC_CNTL_DREFL_SDIO_S) -#define RTC_CNTL_DREFL_SDIO_V 0x00000003 -#define RTC_CNTL_DREFL_SDIO_S 25 - -/* RTC_CNTL_REG1P8_READY : RO; bitpos: [24]; default: 0; - * read only register for REG1P8_READY - */ - -#define RTC_CNTL_REG1P8_READY (BIT(24)) -#define RTC_CNTL_REG1P8_READY_M (RTC_CNTL_REG1P8_READY_V << RTC_CNTL_REG1P8_READY_S) -#define RTC_CNTL_REG1P8_READY_V 0x00000001 -#define RTC_CNTL_REG1P8_READY_S 24 - -/* RTC_CNTL_SDIO_TIEH : R/W; bitpos: [23]; default: 1; - * SW option for SDIO_TIEH. Only active when reg_sdio_force = 1 - */ - -#define RTC_CNTL_SDIO_TIEH (BIT(23)) -#define RTC_CNTL_SDIO_TIEH_M (RTC_CNTL_SDIO_TIEH_V << RTC_CNTL_SDIO_TIEH_S) -#define RTC_CNTL_SDIO_TIEH_V 0x00000001 -#define RTC_CNTL_SDIO_TIEH_S 23 - -/* RTC_CNTL_SDIO_FORCE : R/W; bitpos: [22]; default: 0; - * 1: use SW option to control SDIO_REG 0: use state machine - */ - -#define RTC_CNTL_SDIO_FORCE (BIT(22)) -#define RTC_CNTL_SDIO_FORCE_M (RTC_CNTL_SDIO_FORCE_V << RTC_CNTL_SDIO_FORCE_S) -#define RTC_CNTL_SDIO_FORCE_V 0x00000001 -#define RTC_CNTL_SDIO_FORCE_S 22 - -/* RTC_CNTL_SDIO_REG_PD_EN : R/W; bitpos: [21]; default: 1; - * power down SDIO_REG in sleep. Only active when reg_sdio_force = 0 - */ - -#define RTC_CNTL_SDIO_REG_PD_EN (BIT(21)) -#define RTC_CNTL_SDIO_REG_PD_EN_M (RTC_CNTL_SDIO_REG_PD_EN_V << RTC_CNTL_SDIO_REG_PD_EN_S) -#define RTC_CNTL_SDIO_REG_PD_EN_V 0x00000001 -#define RTC_CNTL_SDIO_REG_PD_EN_S 21 - -/* RTC_CNTL_SDIO_ENCURLIM : R/W; bitpos: [20]; default: 1; - * enable current limit - */ - -#define RTC_CNTL_SDIO_ENCURLIM (BIT(20)) -#define RTC_CNTL_SDIO_ENCURLIM_M (RTC_CNTL_SDIO_ENCURLIM_V << RTC_CNTL_SDIO_ENCURLIM_S) -#define RTC_CNTL_SDIO_ENCURLIM_V 0x00000001 -#define RTC_CNTL_SDIO_ENCURLIM_S 20 - -/* RTC_CNTL_SDIO_MODECURLIM : R/W; bitpos: [19]; default: 0; - * select current limit mode - */ - -#define RTC_CNTL_SDIO_MODECURLIM (BIT(19)) -#define RTC_CNTL_SDIO_MODECURLIM_M (RTC_CNTL_SDIO_MODECURLIM_V << RTC_CNTL_SDIO_MODECURLIM_S) -#define RTC_CNTL_SDIO_MODECURLIM_V 0x00000001 -#define RTC_CNTL_SDIO_MODECURLIM_S 19 - -/* RTC_CNTL_SDIO_DCURLIM : R/W; bitpos: [18:16]; default: 0; - * tune current limit threshold when tieh = 0. About 800mA/(8+d) - */ - -#define RTC_CNTL_SDIO_DCURLIM 0x00000007 -#define RTC_CNTL_SDIO_DCURLIM_M (RTC_CNTL_SDIO_DCURLIM_V << RTC_CNTL_SDIO_DCURLIM_S) -#define RTC_CNTL_SDIO_DCURLIM_V 0x00000007 -#define RTC_CNTL_SDIO_DCURLIM_S 16 - -/* RTC_CNTL_SDIO_EN_INITI : R/W; bitpos: [15]; default: 1; - * 0 to set init[1:0]=0 - */ - -#define RTC_CNTL_SDIO_EN_INITI (BIT(15)) -#define RTC_CNTL_SDIO_EN_INITI_M (RTC_CNTL_SDIO_EN_INITI_V << RTC_CNTL_SDIO_EN_INITI_S) -#define RTC_CNTL_SDIO_EN_INITI_V 0x00000001 -#define RTC_CNTL_SDIO_EN_INITI_S 15 - -/* RTC_CNTL_SDIO_INITI : R/W; bitpos: [14:13]; default: 1; - * add resistor from ldo output to ground. 0: no res 1: 6k 2: 4k 3: 2k - */ - -#define RTC_CNTL_SDIO_INITI 0x00000003 -#define RTC_CNTL_SDIO_INITI_M (RTC_CNTL_SDIO_INITI_V << RTC_CNTL_SDIO_INITI_S) -#define RTC_CNTL_SDIO_INITI_V 0x00000003 -#define RTC_CNTL_SDIO_INITI_S 13 - -/* RTC_CNTL_SDIO_DCAP : R/W; bitpos: [12:11]; default: 3; - * ability to prevent LDO from overshoot - */ - -#define RTC_CNTL_SDIO_DCAP 0x00000003 -#define RTC_CNTL_SDIO_DCAP_M (RTC_CNTL_SDIO_DCAP_V << RTC_CNTL_SDIO_DCAP_S) -#define RTC_CNTL_SDIO_DCAP_V 0x00000003 -#define RTC_CNTL_SDIO_DCAP_S 11 - -/* RTC_CNTL_SDIO_DTHDRV : R/W; bitpos: [10:9]; default: 3; - * Tieh = 1 mode drive ability. Initially set to 0 to limit charge current - * set to 3 after several us. - */ - -#define RTC_CNTL_SDIO_DTHDRV 0x00000003 -#define RTC_CNTL_SDIO_DTHDRV_M (RTC_CNTL_SDIO_DTHDRV_V << RTC_CNTL_SDIO_DTHDRV_S) -#define RTC_CNTL_SDIO_DTHDRV_V 0x00000003 -#define RTC_CNTL_SDIO_DTHDRV_S 9 - -/* RTC_CNTL_SDIO_TIMER_TARGET : R/W; bitpos: [7:0]; default: 10; - * timer count to apply reg_sdio_dcap after sdio power on - */ - -#define RTC_CNTL_SDIO_TIMER_TARGET 0x000000FF -#define RTC_CNTL_SDIO_TIMER_TARGET_M (RTC_CNTL_SDIO_TIMER_TARGET_V << RTC_CNTL_SDIO_TIMER_TARGET_S) -#define RTC_CNTL_SDIO_TIMER_TARGET_V 0x000000FF -#define RTC_CNTL_SDIO_TIMER_TARGET_S 0 - -/* RTC_CNTL_BIAS_CONF_REG register - * configure power register - */ - -#define RTC_CNTL_BIAS_CONF_REG (DR_REG_RTCCNTL_BASE + 0x80) - -/* RTC_CNTL_RST_BIAS_I2C : R/W; bitpos: [31]; default: 0; */ - -#define RTC_CNTL_RST_BIAS_I2C (BIT(31)) -#define RTC_CNTL_RST_BIAS_I2C_M (RTC_CNTL_RST_BIAS_I2C_V << RTC_CNTL_RST_BIAS_I2C_S) -#define RTC_CNTL_RST_BIAS_I2C_V 0x00000001 -#define RTC_CNTL_RST_BIAS_I2C_S 31 - -/* RTC_CNTL_DEC_HEARTBEAT_WIDTH : R/W; bitpos: [30]; default: 0; - * DEC_HEARTBEAT_WIDTH - */ - -#define RTC_CNTL_DEC_HEARTBEAT_WIDTH (BIT(30)) -#define RTC_CNTL_DEC_HEARTBEAT_WIDTH_M (RTC_CNTL_DEC_HEARTBEAT_WIDTH_V << RTC_CNTL_DEC_HEARTBEAT_WIDTH_S) -#define RTC_CNTL_DEC_HEARTBEAT_WIDTH_V 0x00000001 -#define RTC_CNTL_DEC_HEARTBEAT_WIDTH_S 30 - -/* RTC_CNTL_INC_HEARTBEAT_PERIOD : R/W; bitpos: [29]; default: 0; - * INC_HEARTBEAT_PERIOD - */ - -#define RTC_CNTL_INC_HEARTBEAT_PERIOD (BIT(29)) -#define RTC_CNTL_INC_HEARTBEAT_PERIOD_M (RTC_CNTL_INC_HEARTBEAT_PERIOD_V << RTC_CNTL_INC_HEARTBEAT_PERIOD_S) -#define RTC_CNTL_INC_HEARTBEAT_PERIOD_V 0x00000001 -#define RTC_CNTL_INC_HEARTBEAT_PERIOD_S 29 - -/* RTC_CNTL_DEC_HEARTBEAT_PERIOD : R/W; bitpos: [28]; default: 0; - * DEC_HEARTBEAT_PERIOD - */ - -#define RTC_CNTL_DEC_HEARTBEAT_PERIOD (BIT(28)) -#define RTC_CNTL_DEC_HEARTBEAT_PERIOD_M (RTC_CNTL_DEC_HEARTBEAT_PERIOD_V << RTC_CNTL_DEC_HEARTBEAT_PERIOD_S) -#define RTC_CNTL_DEC_HEARTBEAT_PERIOD_V 0x00000001 -#define RTC_CNTL_DEC_HEARTBEAT_PERIOD_S 28 - -/* RTC_CNTL_INC_HEARTBEAT_REFRESH : R/W; bitpos: [27]; default: 0; - * INC_HEARTBEAT_REFRESH - */ - -#define RTC_CNTL_INC_HEARTBEAT_REFRESH (BIT(27)) -#define RTC_CNTL_INC_HEARTBEAT_REFRESH_M (RTC_CNTL_INC_HEARTBEAT_REFRESH_V << RTC_CNTL_INC_HEARTBEAT_REFRESH_S) -#define RTC_CNTL_INC_HEARTBEAT_REFRESH_V 0x00000001 -#define RTC_CNTL_INC_HEARTBEAT_REFRESH_S 27 - -/* RTC_CNTL_ENB_SCK_XTAL : R/W; bitpos: [26]; default: 0; - * ENB_SCK_XTAL - */ - -#define RTC_CNTL_ENB_SCK_XTAL (BIT(26)) -#define RTC_CNTL_ENB_SCK_XTAL_M (RTC_CNTL_ENB_SCK_XTAL_V << RTC_CNTL_ENB_SCK_XTAL_S) -#define RTC_CNTL_ENB_SCK_XTAL_V 0x00000001 -#define RTC_CNTL_ENB_SCK_XTAL_S 26 - -/* RTC_CNTL_DBG_ATTEN_MONITOR : R/W; bitpos: [25:22]; default: 0; - * DBG_ATTEN when rtc in monitor state - */ - -#define RTC_CNTL_DBG_ATTEN_MONITOR 0x0000000F -#define RTC_CNTL_DBG_ATTEN_MONITOR_M (RTC_CNTL_DBG_ATTEN_MONITOR_V << RTC_CNTL_DBG_ATTEN_MONITOR_S) -#define RTC_CNTL_DBG_ATTEN_MONITOR_V 0x0000000F -#define RTC_CNTL_DBG_ATTEN_MONITOR_S 22 - -/* RTC_CNTL_DBG_ATTEN_DEEP_SLP : R/W; bitpos: [21:18]; default: 0; - * DBG_ATTEN when rtc in sleep state - */ - -#define RTC_CNTL_DBG_ATTEN_DEEP_SLP 0x0000000F -#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_M (RTC_CNTL_DBG_ATTEN_DEEP_SLP_V << RTC_CNTL_DBG_ATTEN_DEEP_SLP_S) -#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_V 0x0000000F -#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_S 18 - -/* RTC_CNTL_BIAS_SLEEP_MONITOR : R/W; bitpos: [17]; default: 0; - * bias_sleep when rtc in monitor state - */ - -#define RTC_CNTL_BIAS_SLEEP_MONITOR (BIT(17)) -#define RTC_CNTL_BIAS_SLEEP_MONITOR_M (RTC_CNTL_BIAS_SLEEP_MONITOR_V << RTC_CNTL_BIAS_SLEEP_MONITOR_S) -#define RTC_CNTL_BIAS_SLEEP_MONITOR_V 0x00000001 -#define RTC_CNTL_BIAS_SLEEP_MONITOR_S 17 - -/* RTC_CNTL_BIAS_SLEEP_DEEP_SLP : R/W; bitpos: [16]; default: 1; - * bias_sleep when rtc in sleep_state - */ - -#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP (BIT(16)) -#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_M (RTC_CNTL_BIAS_SLEEP_DEEP_SLP_V << RTC_CNTL_BIAS_SLEEP_DEEP_SLP_S) -#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_V 0x00000001 -#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_S 16 - -/* RTC_CNTL_PD_CUR_MONITOR : R/W; bitpos: [15]; default: 0; - * xpd cur when rtc in monitor state - */ - -#define RTC_CNTL_PD_CUR_MONITOR (BIT(15)) -#define RTC_CNTL_PD_CUR_MONITOR_M (RTC_CNTL_PD_CUR_MONITOR_V << RTC_CNTL_PD_CUR_MONITOR_S) -#define RTC_CNTL_PD_CUR_MONITOR_V 0x00000001 -#define RTC_CNTL_PD_CUR_MONITOR_S 15 - -/* RTC_CNTL_PD_CUR_DEEP_SLP : R/W; bitpos: [14]; default: 0; - * xpd cur when rtc in sleep_state - */ - -#define RTC_CNTL_PD_CUR_DEEP_SLP (BIT(14)) -#define RTC_CNTL_PD_CUR_DEEP_SLP_M (RTC_CNTL_PD_CUR_DEEP_SLP_V << RTC_CNTL_PD_CUR_DEEP_SLP_S) -#define RTC_CNTL_PD_CUR_DEEP_SLP_V 0x00000001 -#define RTC_CNTL_PD_CUR_DEEP_SLP_S 14 - -/* RTC_CNTL_BIAS_BUF_MONITOR : R/W; bitpos: [13]; default: 0; - * open bias buf when rtc in monitor state - */ - -#define RTC_CNTL_BIAS_BUF_MONITOR (BIT(13)) -#define RTC_CNTL_BIAS_BUF_MONITOR_M (RTC_CNTL_BIAS_BUF_MONITOR_V << RTC_CNTL_BIAS_BUF_MONITOR_S) -#define RTC_CNTL_BIAS_BUF_MONITOR_V 0x00000001 -#define RTC_CNTL_BIAS_BUF_MONITOR_S 13 - -/* RTC_CNTL_BIAS_BUF_DEEP_SLP : R/W; bitpos: [12]; default: 0; - * open bias buf when rtc in deep sleep - */ - -#define RTC_CNTL_BIAS_BUF_DEEP_SLP (BIT(12)) -#define RTC_CNTL_BIAS_BUF_DEEP_SLP_M (RTC_CNTL_BIAS_BUF_DEEP_SLP_V << RTC_CNTL_BIAS_BUF_DEEP_SLP_S) -#define RTC_CNTL_BIAS_BUF_DEEP_SLP_V 0x00000001 -#define RTC_CNTL_BIAS_BUF_DEEP_SLP_S 12 - -/* RTC_CNTL_BIAS_BUF_WAKE : R/W; bitpos: [11]; default: 1; - * open bias buf when rtc in wakeup - */ - -#define RTC_CNTL_BIAS_BUF_WAKE (BIT(11)) -#define RTC_CNTL_BIAS_BUF_WAKE_M (RTC_CNTL_BIAS_BUF_WAKE_V << RTC_CNTL_BIAS_BUF_WAKE_S) -#define RTC_CNTL_BIAS_BUF_WAKE_V 0x00000001 -#define RTC_CNTL_BIAS_BUF_WAKE_S 11 - -/* RTC_CNTL_BIAS_BUF_IDLE : R/W; bitpos: [10]; default: 0; - * open bias buf when system in active - */ - -#define RTC_CNTL_BIAS_BUF_IDLE (BIT(10)) -#define RTC_CNTL_BIAS_BUF_IDLE_M (RTC_CNTL_BIAS_BUF_IDLE_V << RTC_CNTL_BIAS_BUF_IDLE_S) -#define RTC_CNTL_BIAS_BUF_IDLE_V 0x00000001 -#define RTC_CNTL_BIAS_BUF_IDLE_S 10 - -/* RTC_CNTL_REG register - * configure rtc/dig regulator register - */ -#define RTC_CNTL_DIG_DBIAS_0V85 0 -#define RTC_CNTL_DIG_DBIAS_0V90 1 -#define RTC_CNTL_DIG_DBIAS_0V95 2 -#define RTC_CNTL_DIG_DBIAS_1V00 3 -#define RTC_CNTL_DIG_DBIAS_1V05 4 -#define RTC_CNTL_DIG_DBIAS_1V10 5 -#define RTC_CNTL_DIG_DBIAS_1V15 6 -#define RTC_CNTL_DIG_DBIAS_1V20 7 - -#define RTC_CNTL_REG (DR_REG_RTCCNTL_BASE + 0x84) - -/* RTC_CNTL_REGULATOR_FORCE_PU : R/W; bitpos: [31]; default: 1; - * RTC_REG force power pu - */ - -#define RTC_CNTL_REGULATOR_FORCE_PU (BIT(31)) -#define RTC_CNTL_REGULATOR_FORCE_PU_M (RTC_CNTL_REGULATOR_FORCE_PU_V << RTC_CNTL_REGULATOR_FORCE_PU_S) -#define RTC_CNTL_REGULATOR_FORCE_PU_V 0x00000001 -#define RTC_CNTL_REGULATOR_FORCE_PU_S 31 - -/* RTC_CNTL_REGULATOR_FORCE_PD : R/W; bitpos: [30]; default: 0; - * RTC_REG force power down (for RTC_REG power down means decrease the - * voltage to 0.8v or lower ) - */ - -#define RTC_CNTL_REGULATOR_FORCE_PD (BIT(30)) -#define RTC_CNTL_REGULATOR_FORCE_PD_M (RTC_CNTL_REGULATOR_FORCE_PD_V << RTC_CNTL_REGULATOR_FORCE_PD_S) -#define RTC_CNTL_REGULATOR_FORCE_PD_V 0x00000001 -#define RTC_CNTL_REGULATOR_FORCE_PD_S 30 - -/* RTC_CNTL_DBOOST_FORCE_PU : R/W; bitpos: [29]; default: 1; - * RTC_DBOOST force power up - */ - -#define RTC_CNTL_DBOOST_FORCE_PU (BIT(29)) -#define RTC_CNTL_DBOOST_FORCE_PU_M (RTC_CNTL_DBOOST_FORCE_PU_V << RTC_CNTL_DBOOST_FORCE_PU_S) -#define RTC_CNTL_DBOOST_FORCE_PU_V 0x00000001 -#define RTC_CNTL_DBOOST_FORCE_PU_S 29 - -/* RTC_CNTL_DBOOST_FORCE_PD : R/W; bitpos: [28]; default: 0; - * RTC_DBOOST force power down - */ - -#define RTC_CNTL_DBOOST_FORCE_PD (BIT(28)) -#define RTC_CNTL_DBOOST_FORCE_PD_M (RTC_CNTL_DBOOST_FORCE_PD_V << RTC_CNTL_DBOOST_FORCE_PD_S) -#define RTC_CNTL_DBOOST_FORCE_PD_V 0x00000001 -#define RTC_CNTL_DBOOST_FORCE_PD_S 28 - -/* RTC_CNTL_DBIAS_WAK : R/W; bitpos: [27:25]; default: 4; - * RTC_DBIAS during wakeup - */ - -#define RTC_CNTL_DBIAS_WAK 0x00000007 -#define RTC_CNTL_DBIAS_WAK_M (RTC_CNTL_DBIAS_WAK_V << RTC_CNTL_DBIAS_WAK_S) -#define RTC_CNTL_DBIAS_WAK_V 0x00000007 -#define RTC_CNTL_DBIAS_WAK_S 25 - -/* RTC_CNTL_DBIAS_SLP : R/W; bitpos: [24:22]; default: 4; - * RTC_DBIAS during sleep - */ - -#define RTC_CNTL_DBIAS_SLP 0x00000007 -#define RTC_CNTL_DBIAS_SLP_M (RTC_CNTL_DBIAS_SLP_V << RTC_CNTL_DBIAS_SLP_S) -#define RTC_CNTL_DBIAS_SLP_V 0x00000007 -#define RTC_CNTL_DBIAS_SLP_S 22 - -/* RTC_CNTL_SCK_DCAP : R/W; bitpos: [21:14]; default: 0; - * SCK_DCAP - */ - -#define RTC_CNTL_SCK_DCAP 0x000000FF -#define RTC_CNTL_SCK_DCAP_M (RTC_CNTL_SCK_DCAP_V << RTC_CNTL_SCK_DCAP_S) -#define RTC_CNTL_SCK_DCAP_V 0x000000FF -#define RTC_CNTL_SCK_DCAP_S 14 - -/* RTC_CNTL_DIG_REG_DBIAS_WAK : R/W; bitpos: [13:11]; default: 4; - * DIG_REG_DBIAS during wakeup - */ - -#define RTC_CNTL_DIG_DBIAS_WAK 0x00000007 -#define RTC_CNTL_DIG_DBIAS_WAK_M (RTC_CNTL_DIG_DBIAS_WAK_V << RTC_CNTL_DIG_DBIAS_WAK_S) -#define RTC_CNTL_DIG_DBIAS_WAK_V 0x00000007 -#define RTC_CNTL_DIG_DBIAS_WAK_S 11 - -/* RTC_CNTL_DIG_REG_DBIAS_SLP : R/W; bitpos: [10:8]; default: 4; - * DIG_REG_DBIAS during sleep - */ - -#define RTC_CNTL_DIG_DBIAS_SLP 0x00000007 -#define RTC_CNTL_DIG_DBIAS_SLP_M (RTC_CNTL_DIG_DBIAS_SLP_V << RTC_CNTL_DIG_DBIAS_SLP_S) -#define RTC_CNTL_DIG_DBIAS_SLP_V 0x00000007 -#define RTC_CNTL_DIG_DBIAS_SLP_S 8 - -/* RTC_CNTL_PWC_REG register - * configure rtc power configure - */ - -#define RTC_CNTL_PWC_REG (DR_REG_RTCCNTL_BASE + 0x88) - -/* RTC_CNTL_PAD_FORCE_HOLD : R/W; bitpos: [21]; default: 0; - * rtc pad force hold - */ - -#define RTC_CNTL_PAD_FORCE_HOLD (BIT(21)) -#define RTC_CNTL_PAD_FORCE_HOLD_M (RTC_CNTL_PAD_FORCE_HOLD_V << RTC_CNTL_PAD_FORCE_HOLD_S) -#define RTC_CNTL_PAD_FORCE_HOLD_V 0x00000001 -#define RTC_CNTL_PAD_FORCE_HOLD_S 21 - -/* RTC_CNTL_PD_EN : R/W; bitpos: [20]; default: 0; - * enable power down rtc_peri in sleep - */ - -#define RTC_CNTL_PD_EN (BIT(20)) -#define RTC_CNTL_PD_EN_M (RTC_CNTL_PD_EN_V << RTC_CNTL_PD_EN_S) -#define RTC_CNTL_PD_EN_V 0x00000001 -#define RTC_CNTL_PD_EN_S 20 - -/* RTC_CNTL_FORCE_PU : R/W; bitpos: [19]; default: 0; - * rtc_peri force power up - */ - -#define RTC_CNTL_FORCE_PU (BIT(19)) -#define RTC_CNTL_FORCE_PU_M (RTC_CNTL_FORCE_PU_V << RTC_CNTL_FORCE_PU_S) -#define RTC_CNTL_FORCE_PU_V 0x00000001 -#define RTC_CNTL_FORCE_PU_S 19 - -/* RTC_CNTL_FORCE_PD : R/W; bitpos: [18]; default: 0; - * rtc_peri force power down - */ - -#define RTC_CNTL_FORCE_PD (BIT(18)) -#define RTC_CNTL_FORCE_PD_M (RTC_CNTL_FORCE_PD_V << RTC_CNTL_FORCE_PD_S) -#define RTC_CNTL_FORCE_PD_V 0x00000001 -#define RTC_CNTL_FORCE_PD_S 18 - -/* RTC_CNTL_SLOWMEM_PD_EN : R/W; bitpos: [17]; default: 0; - * enable power down RTC memory in sleep - */ - -#define RTC_CNTL_SLOWMEM_PD_EN (BIT(17)) -#define RTC_CNTL_SLOWMEM_PD_EN_M (RTC_CNTL_SLOWMEM_PD_EN_V << RTC_CNTL_SLOWMEM_PD_EN_S) -#define RTC_CNTL_SLOWMEM_PD_EN_V 0x00000001 -#define RTC_CNTL_SLOWMEM_PD_EN_S 17 - -/* RTC_CNTL_SLOWMEM_FORCE_PU : R/W; bitpos: [16]; default: 1; - * RTC memory force power up - */ - -#define RTC_CNTL_SLOWMEM_FORCE_PU (BIT(16)) -#define RTC_CNTL_SLOWMEM_FORCE_PU_M (RTC_CNTL_SLOWMEM_FORCE_PU_V << RTC_CNTL_SLOWMEM_FORCE_PU_S) -#define RTC_CNTL_SLOWMEM_FORCE_PU_V 0x00000001 -#define RTC_CNTL_SLOWMEM_FORCE_PU_S 16 - -/* RTC_CNTL_SLOWMEM_FORCE_PD : R/W; bitpos: [15]; default: 0; - * RTC memory force power down - */ - -#define RTC_CNTL_SLOWMEM_FORCE_PD (BIT(15)) -#define RTC_CNTL_SLOWMEM_FORCE_PD_M (RTC_CNTL_SLOWMEM_FORCE_PD_V << RTC_CNTL_SLOWMEM_FORCE_PD_S) -#define RTC_CNTL_SLOWMEM_FORCE_PD_V 0x00000001 -#define RTC_CNTL_SLOWMEM_FORCE_PD_S 15 - -/* RTC_CNTL_FASTMEM_PD_EN : R/W; bitpos: [14]; default: 0; - * enable power down fast RTC memory in sleep - */ - -#define RTC_CNTL_FASTMEM_PD_EN (BIT(14)) -#define RTC_CNTL_FASTMEM_PD_EN_M (RTC_CNTL_FASTMEM_PD_EN_V << RTC_CNTL_FASTMEM_PD_EN_S) -#define RTC_CNTL_FASTMEM_PD_EN_V 0x00000001 -#define RTC_CNTL_FASTMEM_PD_EN_S 14 - -/* RTC_CNTL_FASTMEM_FORCE_PU : R/W; bitpos: [13]; default: 1; - * Fast RTC memory force power up - */ - -#define RTC_CNTL_FASTMEM_FORCE_PU (BIT(13)) -#define RTC_CNTL_FASTMEM_FORCE_PU_M (RTC_CNTL_FASTMEM_FORCE_PU_V << RTC_CNTL_FASTMEM_FORCE_PU_S) -#define RTC_CNTL_FASTMEM_FORCE_PU_V 0x00000001 -#define RTC_CNTL_FASTMEM_FORCE_PU_S 13 - -/* RTC_CNTL_FASTMEM_FORCE_PD : R/W; bitpos: [12]; default: 0; - * Fast RTC memory force power down - */ - -#define RTC_CNTL_FASTMEM_FORCE_PD (BIT(12)) -#define RTC_CNTL_FASTMEM_FORCE_PD_M (RTC_CNTL_FASTMEM_FORCE_PD_V << RTC_CNTL_FASTMEM_FORCE_PD_S) -#define RTC_CNTL_FASTMEM_FORCE_PD_V 0x00000001 -#define RTC_CNTL_FASTMEM_FORCE_PD_S 12 - -/* RTC_CNTL_SLOWMEM_FORCE_LPU : R/W; bitpos: [11]; default: 1; - * RTC memory force no PD - */ - -#define RTC_CNTL_SLOWMEM_FORCE_LPU (BIT(11)) -#define RTC_CNTL_SLOWMEM_FORCE_LPU_M (RTC_CNTL_SLOWMEM_FORCE_LPU_V << RTC_CNTL_SLOWMEM_FORCE_LPU_S) -#define RTC_CNTL_SLOWMEM_FORCE_LPU_V 0x00000001 -#define RTC_CNTL_SLOWMEM_FORCE_LPU_S 11 - -/* RTC_CNTL_SLOWMEM_FORCE_LPD : R/W; bitpos: [10]; default: 0; - * RTC memory force PD - */ - -#define RTC_CNTL_SLOWMEM_FORCE_LPD (BIT(10)) -#define RTC_CNTL_SLOWMEM_FORCE_LPD_M (RTC_CNTL_SLOWMEM_FORCE_LPD_V << RTC_CNTL_SLOWMEM_FORCE_LPD_S) -#define RTC_CNTL_SLOWMEM_FORCE_LPD_V 0x00000001 -#define RTC_CNTL_SLOWMEM_FORCE_LPD_S 10 - -/* RTC_CNTL_SLOWMEM_FOLW_CPU : R/W; bitpos: [9]; default: 0; - * 1: RTC memory PD following CPU 0: RTC memory PD following RTC state - * machine - */ - -#define RTC_CNTL_SLOWMEM_FOLW_CPU (BIT(9)) -#define RTC_CNTL_SLOWMEM_FOLW_CPU_M (RTC_CNTL_SLOWMEM_FOLW_CPU_V << RTC_CNTL_SLOWMEM_FOLW_CPU_S) -#define RTC_CNTL_SLOWMEM_FOLW_CPU_V 0x00000001 -#define RTC_CNTL_SLOWMEM_FOLW_CPU_S 9 - -/* RTC_CNTL_FASTMEM_FORCE_LPU : R/W; bitpos: [8]; default: 1; - * Fast RTC memory force no PD - */ - -#define RTC_CNTL_FASTMEM_FORCE_LPU (BIT(8)) -#define RTC_CNTL_FASTMEM_FORCE_LPU_M (RTC_CNTL_FASTMEM_FORCE_LPU_V << RTC_CNTL_FASTMEM_FORCE_LPU_S) -#define RTC_CNTL_FASTMEM_FORCE_LPU_V 0x00000001 -#define RTC_CNTL_FASTMEM_FORCE_LPU_S 8 - -/* RTC_CNTL_FASTMEM_FORCE_LPD : R/W; bitpos: [7]; default: 0; - * Fast RTC memory force PD - */ - -#define RTC_CNTL_FASTMEM_FORCE_LPD (BIT(7)) -#define RTC_CNTL_FASTMEM_FORCE_LPD_M (RTC_CNTL_FASTMEM_FORCE_LPD_V << RTC_CNTL_FASTMEM_FORCE_LPD_S) -#define RTC_CNTL_FASTMEM_FORCE_LPD_V 0x00000001 -#define RTC_CNTL_FASTMEM_FORCE_LPD_S 7 - -/* RTC_CNTL_FASTMEM_FOLW_CPU : R/W; bitpos: [6]; default: 0; - * 1: Fast RTC memory PD following CPU 0: fast RTC memory PD following RTC - * state machine - */ - -#define RTC_CNTL_FASTMEM_FOLW_CPU (BIT(6)) -#define RTC_CNTL_FASTMEM_FOLW_CPU_M (RTC_CNTL_FASTMEM_FOLW_CPU_V << RTC_CNTL_FASTMEM_FOLW_CPU_S) -#define RTC_CNTL_FASTMEM_FOLW_CPU_V 0x00000001 -#define RTC_CNTL_FASTMEM_FOLW_CPU_S 6 - -/* RTC_CNTL_FORCE_NOISO : R/W; bitpos: [5]; default: 1; - * rtc_peri force no ISO - */ - -#define RTC_CNTL_FORCE_NOISO (BIT(5)) -#define RTC_CNTL_FORCE_NOISO_M (RTC_CNTL_FORCE_NOISO_V << RTC_CNTL_FORCE_NOISO_S) -#define RTC_CNTL_FORCE_NOISO_V 0x00000001 -#define RTC_CNTL_FORCE_NOISO_S 5 - -/* RTC_CNTL_FORCE_ISO : R/W; bitpos: [4]; default: 0; - * rtc_peri force ISO - */ - -#define RTC_CNTL_FORCE_ISO (BIT(4)) -#define RTC_CNTL_FORCE_ISO_M (RTC_CNTL_FORCE_ISO_V << RTC_CNTL_FORCE_ISO_S) -#define RTC_CNTL_FORCE_ISO_V 0x00000001 -#define RTC_CNTL_FORCE_ISO_S 4 - -/* RTC_CNTL_SLOWMEM_FORCE_ISO : R/W; bitpos: [3]; default: 0; - * RTC memory force ISO - */ - -#define RTC_CNTL_SLOWMEM_FORCE_ISO (BIT(3)) -#define RTC_CNTL_SLOWMEM_FORCE_ISO_M (RTC_CNTL_SLOWMEM_FORCE_ISO_V << RTC_CNTL_SLOWMEM_FORCE_ISO_S) -#define RTC_CNTL_SLOWMEM_FORCE_ISO_V 0x00000001 -#define RTC_CNTL_SLOWMEM_FORCE_ISO_S 3 - -/* RTC_CNTL_SLOWMEM_FORCE_NOISO : R/W; bitpos: [2]; default: 1; - * RTC memory force no ISO - */ - -#define RTC_CNTL_SLOWMEM_FORCE_NOISO (BIT(2)) -#define RTC_CNTL_SLOWMEM_FORCE_NOISO_M (RTC_CNTL_SLOWMEM_FORCE_NOISO_V << RTC_CNTL_SLOWMEM_FORCE_NOISO_S) -#define RTC_CNTL_SLOWMEM_FORCE_NOISO_V 0x00000001 -#define RTC_CNTL_SLOWMEM_FORCE_NOISO_S 2 - -/* RTC_CNTL_FASTMEM_FORCE_ISO : R/W; bitpos: [1]; default: 0; - * Fast RTC memory force ISO - */ - -#define RTC_CNTL_FASTMEM_FORCE_ISO (BIT(1)) -#define RTC_CNTL_FASTMEM_FORCE_ISO_M (RTC_CNTL_FASTMEM_FORCE_ISO_V << RTC_CNTL_FASTMEM_FORCE_ISO_S) -#define RTC_CNTL_FASTMEM_FORCE_ISO_V 0x00000001 -#define RTC_CNTL_FASTMEM_FORCE_ISO_S 1 - -/* RTC_CNTL_FASTMEM_FORCE_NOISO : R/W; bitpos: [0]; default: 1; - * Fast RTC memory force no ISO - */ - -#define RTC_CNTL_FASTMEM_FORCE_NOISO (BIT(0)) -#define RTC_CNTL_FASTMEM_FORCE_NOISO_M (RTC_CNTL_FASTMEM_FORCE_NOISO_V << RTC_CNTL_FASTMEM_FORCE_NOISO_S) -#define RTC_CNTL_FASTMEM_FORCE_NOISO_V 0x00000001 -#define RTC_CNTL_FASTMEM_FORCE_NOISO_S 0 - -/* RTC_CNTL_DIG_PWC_REG register - * configure power of digital core - */ - -#define RTC_CNTL_DIG_PWC_REG (DR_REG_RTCCNTL_BASE + 0x8c) - -/* RTC_CNTL_DG_WRAP_PD_EN : R/W; bitpos: [31]; default: 0; - * enable power down digital core in sleep - */ - -#define RTC_CNTL_DG_WRAP_PD_EN (BIT(31)) -#define RTC_CNTL_DG_WRAP_PD_EN_M (RTC_CNTL_DG_WRAP_PD_EN_V << RTC_CNTL_DG_WRAP_PD_EN_S) -#define RTC_CNTL_DG_WRAP_PD_EN_V 0x00000001 -#define RTC_CNTL_DG_WRAP_PD_EN_S 31 - -/* RTC_CNTL_WIFI_PD_EN : R/W; bitpos: [30]; default: 0; - * enable power down wifi in sleep - */ - -#define RTC_CNTL_WIFI_PD_EN (BIT(30)) -#define RTC_CNTL_WIFI_PD_EN_M (RTC_CNTL_WIFI_PD_EN_V << RTC_CNTL_WIFI_PD_EN_S) -#define RTC_CNTL_WIFI_PD_EN_V 0x00000001 -#define RTC_CNTL_WIFI_PD_EN_S 30 - -/* RTC_CNTL_INTER_RAM4_PD_EN : R/W; bitpos: [29]; default: 0; - * enable power down internal SRAM 4 in sleep - */ - -#define RTC_CNTL_INTER_RAM4_PD_EN (BIT(29)) -#define RTC_CNTL_INTER_RAM4_PD_EN_M (RTC_CNTL_INTER_RAM4_PD_EN_V << RTC_CNTL_INTER_RAM4_PD_EN_S) -#define RTC_CNTL_INTER_RAM4_PD_EN_V 0x00000001 -#define RTC_CNTL_INTER_RAM4_PD_EN_S 29 - -/* RTC_CNTL_INTER_RAM3_PD_EN : R/W; bitpos: [28]; default: 0; - * enable power down internal SRAM 3 in sleep - */ - -#define RTC_CNTL_INTER_RAM3_PD_EN (BIT(28)) -#define RTC_CNTL_INTER_RAM3_PD_EN_M (RTC_CNTL_INTER_RAM3_PD_EN_V << RTC_CNTL_INTER_RAM3_PD_EN_S) -#define RTC_CNTL_INTER_RAM3_PD_EN_V 0x00000001 -#define RTC_CNTL_INTER_RAM3_PD_EN_S 28 - -/* RTC_CNTL_INTER_RAM2_PD_EN : R/W; bitpos: [27]; default: 0; - * enable power down internal SRAM 2 in sleep - */ - -#define RTC_CNTL_INTER_RAM2_PD_EN (BIT(27)) -#define RTC_CNTL_INTER_RAM2_PD_EN_M (RTC_CNTL_INTER_RAM2_PD_EN_V << RTC_CNTL_INTER_RAM2_PD_EN_S) -#define RTC_CNTL_INTER_RAM2_PD_EN_V 0x00000001 -#define RTC_CNTL_INTER_RAM2_PD_EN_S 27 - -/* RTC_CNTL_INTER_RAM1_PD_EN : R/W; bitpos: [26]; default: 0; - * enable power down internal SRAM 1 in sleep - */ - -#define RTC_CNTL_INTER_RAM1_PD_EN (BIT(26)) -#define RTC_CNTL_INTER_RAM1_PD_EN_M (RTC_CNTL_INTER_RAM1_PD_EN_V << RTC_CNTL_INTER_RAM1_PD_EN_S) -#define RTC_CNTL_INTER_RAM1_PD_EN_V 0x00000001 -#define RTC_CNTL_INTER_RAM1_PD_EN_S 26 - -/* RTC_CNTL_INTER_RAM0_PD_EN : R/W; bitpos: [25]; default: 0; - * enable power down internal SRAM 0 in sleep - */ - -#define RTC_CNTL_INTER_RAM0_PD_EN (BIT(25)) -#define RTC_CNTL_INTER_RAM0_PD_EN_M (RTC_CNTL_INTER_RAM0_PD_EN_V << RTC_CNTL_INTER_RAM0_PD_EN_S) -#define RTC_CNTL_INTER_RAM0_PD_EN_V 0x00000001 -#define RTC_CNTL_INTER_RAM0_PD_EN_S 25 - -/* RTC_CNTL_ROM0_PD_EN : R/W; bitpos: [24]; default: 0; - * enable power down ROM in sleep - */ - -#define RTC_CNTL_ROM0_PD_EN (BIT(24)) -#define RTC_CNTL_ROM0_PD_EN_M (RTC_CNTL_ROM0_PD_EN_V << RTC_CNTL_ROM0_PD_EN_S) -#define RTC_CNTL_ROM0_PD_EN_V 0x00000001 -#define RTC_CNTL_ROM0_PD_EN_S 24 - -/* RTC_CNTL_DG_DCDC_PD_EN : R/W; bitpos: [23]; default: 0; - * enable power down digital dcdc in sleep - */ - -#define RTC_CNTL_DG_DCDC_PD_EN (BIT(23)) -#define RTC_CNTL_DG_DCDC_PD_EN_M (RTC_CNTL_DG_DCDC_PD_EN_V << RTC_CNTL_DG_DCDC_PD_EN_S) -#define RTC_CNTL_DG_DCDC_PD_EN_V 0x00000001 -#define RTC_CNTL_DG_DCDC_PD_EN_S 23 - -/* RTC_CNTL_DG_DCDC_FORCE_PU : R/W; bitpos: [22]; default: 1; - * digital dcdc force power up - */ - -#define RTC_CNTL_DG_DCDC_FORCE_PU (BIT(22)) -#define RTC_CNTL_DG_DCDC_FORCE_PU_M (RTC_CNTL_DG_DCDC_FORCE_PU_V << RTC_CNTL_DG_DCDC_FORCE_PU_S) -#define RTC_CNTL_DG_DCDC_FORCE_PU_V 0x00000001 -#define RTC_CNTL_DG_DCDC_FORCE_PU_S 22 - -/* RTC_CNTL_DG_DCDC_FORCE_PD : R/W; bitpos: [21]; default: 0; - * digital dcdc force power down - */ - -#define RTC_CNTL_DG_DCDC_FORCE_PD (BIT(21)) -#define RTC_CNTL_DG_DCDC_FORCE_PD_M (RTC_CNTL_DG_DCDC_FORCE_PD_V << RTC_CNTL_DG_DCDC_FORCE_PD_S) -#define RTC_CNTL_DG_DCDC_FORCE_PD_V 0x00000001 -#define RTC_CNTL_DG_DCDC_FORCE_PD_S 21 - -/* RTC_CNTL_DG_WRAP_FORCE_PU : R/W; bitpos: [20]; default: 1; - * digital core force power up - */ - -#define RTC_CNTL_DG_WRAP_FORCE_PU (BIT(20)) -#define RTC_CNTL_DG_WRAP_FORCE_PU_M (RTC_CNTL_DG_WRAP_FORCE_PU_V << RTC_CNTL_DG_WRAP_FORCE_PU_S) -#define RTC_CNTL_DG_WRAP_FORCE_PU_V 0x00000001 -#define RTC_CNTL_DG_WRAP_FORCE_PU_S 20 - -/* RTC_CNTL_DG_WRAP_FORCE_PD : R/W; bitpos: [19]; default: 0; - * digital core force power down - */ - -#define RTC_CNTL_DG_WRAP_FORCE_PD (BIT(19)) -#define RTC_CNTL_DG_WRAP_FORCE_PD_M (RTC_CNTL_DG_WRAP_FORCE_PD_V << RTC_CNTL_DG_WRAP_FORCE_PD_S) -#define RTC_CNTL_DG_WRAP_FORCE_PD_V 0x00000001 -#define RTC_CNTL_DG_WRAP_FORCE_PD_S 19 - -/* RTC_CNTL_WIFI_FORCE_PU : R/W; bitpos: [18]; default: 1; - * wifi force power up - */ - -#define RTC_CNTL_WIFI_FORCE_PU (BIT(18)) -#define RTC_CNTL_WIFI_FORCE_PU_M (RTC_CNTL_WIFI_FORCE_PU_V << RTC_CNTL_WIFI_FORCE_PU_S) -#define RTC_CNTL_WIFI_FORCE_PU_V 0x00000001 -#define RTC_CNTL_WIFI_FORCE_PU_S 18 - -/* RTC_CNTL_WIFI_FORCE_PD : R/W; bitpos: [17]; default: 0; - * wifi force power down - */ - -#define RTC_CNTL_WIFI_FORCE_PD (BIT(17)) -#define RTC_CNTL_WIFI_FORCE_PD_M (RTC_CNTL_WIFI_FORCE_PD_V << RTC_CNTL_WIFI_FORCE_PD_S) -#define RTC_CNTL_WIFI_FORCE_PD_V 0x00000001 -#define RTC_CNTL_WIFI_FORCE_PD_S 17 - -/* RTC_CNTL_INTER_RAM4_FORCE_PU : R/W; bitpos: [16]; default: 1; - * internal SRAM 4 force power up - */ - -#define RTC_CNTL_INTER_RAM4_FORCE_PU (BIT(16)) -#define RTC_CNTL_INTER_RAM4_FORCE_PU_M (RTC_CNTL_INTER_RAM4_FORCE_PU_V << RTC_CNTL_INTER_RAM4_FORCE_PU_S) -#define RTC_CNTL_INTER_RAM4_FORCE_PU_V 0x00000001 -#define RTC_CNTL_INTER_RAM4_FORCE_PU_S 16 - -/* RTC_CNTL_INTER_RAM4_FORCE_PD : R/W; bitpos: [15]; default: 0; - * internal SRAM 4 force power down - */ - -#define RTC_CNTL_INTER_RAM4_FORCE_PD (BIT(15)) -#define RTC_CNTL_INTER_RAM4_FORCE_PD_M (RTC_CNTL_INTER_RAM4_FORCE_PD_V << RTC_CNTL_INTER_RAM4_FORCE_PD_S) -#define RTC_CNTL_INTER_RAM4_FORCE_PD_V 0x00000001 -#define RTC_CNTL_INTER_RAM4_FORCE_PD_S 15 - -/* RTC_CNTL_INTER_RAM3_FORCE_PU : R/W; bitpos: [14]; default: 1; - * internal SRAM 3 force power up - */ - -#define RTC_CNTL_INTER_RAM3_FORCE_PU (BIT(14)) -#define RTC_CNTL_INTER_RAM3_FORCE_PU_M (RTC_CNTL_INTER_RAM3_FORCE_PU_V << RTC_CNTL_INTER_RAM3_FORCE_PU_S) -#define RTC_CNTL_INTER_RAM3_FORCE_PU_V 0x00000001 -#define RTC_CNTL_INTER_RAM3_FORCE_PU_S 14 - -/* RTC_CNTL_INTER_RAM3_FORCE_PD : R/W; bitpos: [13]; default: 0; - * internal SRAM 3 force power down - */ - -#define RTC_CNTL_INTER_RAM3_FORCE_PD (BIT(13)) -#define RTC_CNTL_INTER_RAM3_FORCE_PD_M (RTC_CNTL_INTER_RAM3_FORCE_PD_V << RTC_CNTL_INTER_RAM3_FORCE_PD_S) -#define RTC_CNTL_INTER_RAM3_FORCE_PD_V 0x00000001 -#define RTC_CNTL_INTER_RAM3_FORCE_PD_S 13 - -/* RTC_CNTL_INTER_RAM2_FORCE_PU : R/W; bitpos: [12]; default: 1; - * internal SRAM 2 force power up - */ - -#define RTC_CNTL_INTER_RAM2_FORCE_PU (BIT(12)) -#define RTC_CNTL_INTER_RAM2_FORCE_PU_M (RTC_CNTL_INTER_RAM2_FORCE_PU_V << RTC_CNTL_INTER_RAM2_FORCE_PU_S) -#define RTC_CNTL_INTER_RAM2_FORCE_PU_V 0x00000001 -#define RTC_CNTL_INTER_RAM2_FORCE_PU_S 12 - -/* RTC_CNTL_INTER_RAM2_FORCE_PD : R/W; bitpos: [11]; default: 0; - * internal SRAM 2 force power down - */ - -#define RTC_CNTL_INTER_RAM2_FORCE_PD (BIT(11)) -#define RTC_CNTL_INTER_RAM2_FORCE_PD_M (RTC_CNTL_INTER_RAM2_FORCE_PD_V << RTC_CNTL_INTER_RAM2_FORCE_PD_S) -#define RTC_CNTL_INTER_RAM2_FORCE_PD_V 0x00000001 -#define RTC_CNTL_INTER_RAM2_FORCE_PD_S 11 - -/* RTC_CNTL_INTER_RAM1_FORCE_PU : R/W; bitpos: [10]; default: 1; - * internal SRAM 1 force power up - */ - -#define RTC_CNTL_INTER_RAM1_FORCE_PU (BIT(10)) -#define RTC_CNTL_INTER_RAM1_FORCE_PU_M (RTC_CNTL_INTER_RAM1_FORCE_PU_V << RTC_CNTL_INTER_RAM1_FORCE_PU_S) -#define RTC_CNTL_INTER_RAM1_FORCE_PU_V 0x00000001 -#define RTC_CNTL_INTER_RAM1_FORCE_PU_S 10 - -/* RTC_CNTL_INTER_RAM1_FORCE_PD : R/W; bitpos: [9]; default: 0; - * internal SRAM 1 force power down - */ - -#define RTC_CNTL_INTER_RAM1_FORCE_PD (BIT(9)) -#define RTC_CNTL_INTER_RAM1_FORCE_PD_M (RTC_CNTL_INTER_RAM1_FORCE_PD_V << RTC_CNTL_INTER_RAM1_FORCE_PD_S) -#define RTC_CNTL_INTER_RAM1_FORCE_PD_V 0x00000001 -#define RTC_CNTL_INTER_RAM1_FORCE_PD_S 9 - -/* RTC_CNTL_INTER_RAM0_FORCE_PU : R/W; bitpos: [8]; default: 1; - * internal SRAM 0 force power up - */ - -#define RTC_CNTL_INTER_RAM0_FORCE_PU (BIT(8)) -#define RTC_CNTL_INTER_RAM0_FORCE_PU_M (RTC_CNTL_INTER_RAM0_FORCE_PU_V << RTC_CNTL_INTER_RAM0_FORCE_PU_S) -#define RTC_CNTL_INTER_RAM0_FORCE_PU_V 0x00000001 -#define RTC_CNTL_INTER_RAM0_FORCE_PU_S 8 - -/* RTC_CNTL_INTER_RAM0_FORCE_PD : R/W; bitpos: [7]; default: 0; - * internal SRAM 0 force power down - */ - -#define RTC_CNTL_INTER_RAM0_FORCE_PD (BIT(7)) -#define RTC_CNTL_INTER_RAM0_FORCE_PD_M (RTC_CNTL_INTER_RAM0_FORCE_PD_V << RTC_CNTL_INTER_RAM0_FORCE_PD_S) -#define RTC_CNTL_INTER_RAM0_FORCE_PD_V 0x00000001 -#define RTC_CNTL_INTER_RAM0_FORCE_PD_S 7 - -/* RTC_CNTL_ROM0_FORCE_PU : R/W; bitpos: [6]; default: 1; - * ROM force power up - */ - -#define RTC_CNTL_ROM0_FORCE_PU (BIT(6)) -#define RTC_CNTL_ROM0_FORCE_PU_M (RTC_CNTL_ROM0_FORCE_PU_V << RTC_CNTL_ROM0_FORCE_PU_S) -#define RTC_CNTL_ROM0_FORCE_PU_V 0x00000001 -#define RTC_CNTL_ROM0_FORCE_PU_S 6 - -/* RTC_CNTL_ROM0_FORCE_PD : R/W; bitpos: [5]; default: 0; - * ROM force power down - */ - -#define RTC_CNTL_ROM0_FORCE_PD (BIT(5)) -#define RTC_CNTL_ROM0_FORCE_PD_M (RTC_CNTL_ROM0_FORCE_PD_V << RTC_CNTL_ROM0_FORCE_PD_S) -#define RTC_CNTL_ROM0_FORCE_PD_V 0x00000001 -#define RTC_CNTL_ROM0_FORCE_PD_S 5 - -/* RTC_CNTL_LSLP_MEM_FORCE_PU : R/W; bitpos: [4]; default: 1; - * memories in digital core force no PD in sleep - */ - -#define RTC_CNTL_LSLP_MEM_FORCE_PU (BIT(4)) -#define RTC_CNTL_LSLP_MEM_FORCE_PU_M (RTC_CNTL_LSLP_MEM_FORCE_PU_V << RTC_CNTL_LSLP_MEM_FORCE_PU_S) -#define RTC_CNTL_LSLP_MEM_FORCE_PU_V 0x00000001 -#define RTC_CNTL_LSLP_MEM_FORCE_PU_S 4 - -/* RTC_CNTL_LSLP_MEM_FORCE_PD : R/W; bitpos: [3]; default: 0; - * memories in digital core force PD in sleep - */ - -#define RTC_CNTL_LSLP_MEM_FORCE_PD (BIT(3)) -#define RTC_CNTL_LSLP_MEM_FORCE_PD_M (RTC_CNTL_LSLP_MEM_FORCE_PD_V << RTC_CNTL_LSLP_MEM_FORCE_PD_S) -#define RTC_CNTL_LSLP_MEM_FORCE_PD_V 0x00000001 -#define RTC_CNTL_LSLP_MEM_FORCE_PD_S 3 - -/* RTC_CNTL_DIG_ISO_REG register - * configure ISO of digital core - */ - -#define RTC_CNTL_DIG_ISO_REG (DR_REG_RTCCNTL_BASE + 0x90) - -/* RTC_CNTL_DG_WRAP_FORCE_NOISO : R/W; bitpos: [31]; default: 1; - * digital core force no ISO - */ - -#define RTC_CNTL_DG_WRAP_FORCE_NOISO (BIT(31)) -#define RTC_CNTL_DG_WRAP_FORCE_NOISO_M (RTC_CNTL_DG_WRAP_FORCE_NOISO_V << RTC_CNTL_DG_WRAP_FORCE_NOISO_S) -#define RTC_CNTL_DG_WRAP_FORCE_NOISO_V 0x00000001 -#define RTC_CNTL_DG_WRAP_FORCE_NOISO_S 31 - -/* RTC_CNTL_DG_WRAP_FORCE_ISO : R/W; bitpos: [30]; default: 0; - * digital core force ISO - */ - -#define RTC_CNTL_DG_WRAP_FORCE_ISO (BIT(30)) -#define RTC_CNTL_DG_WRAP_FORCE_ISO_M (RTC_CNTL_DG_WRAP_FORCE_ISO_V << RTC_CNTL_DG_WRAP_FORCE_ISO_S) -#define RTC_CNTL_DG_WRAP_FORCE_ISO_V 0x00000001 -#define RTC_CNTL_DG_WRAP_FORCE_ISO_S 30 - -/* RTC_CNTL_WIFI_FORCE_NOISO : R/W; bitpos: [29]; default: 1; - * wifi force no ISO - */ - -#define RTC_CNTL_WIFI_FORCE_NOISO (BIT(29)) -#define RTC_CNTL_WIFI_FORCE_NOISO_M (RTC_CNTL_WIFI_FORCE_NOISO_V << RTC_CNTL_WIFI_FORCE_NOISO_S) -#define RTC_CNTL_WIFI_FORCE_NOISO_V 0x00000001 -#define RTC_CNTL_WIFI_FORCE_NOISO_S 29 - -/* RTC_CNTL_WIFI_FORCE_ISO : R/W; bitpos: [28]; default: 0; - * wifi force ISO - */ - -#define RTC_CNTL_WIFI_FORCE_ISO (BIT(28)) -#define RTC_CNTL_WIFI_FORCE_ISO_M (RTC_CNTL_WIFI_FORCE_ISO_V << RTC_CNTL_WIFI_FORCE_ISO_S) -#define RTC_CNTL_WIFI_FORCE_ISO_V 0x00000001 -#define RTC_CNTL_WIFI_FORCE_ISO_S 28 - -/* RTC_CNTL_INTER_RAM4_FORCE_NOISO : R/W; bitpos: [27]; default: 1; - * internal SRAM 4 force no ISO - */ - -#define RTC_CNTL_INTER_RAM4_FORCE_NOISO (BIT(27)) -#define RTC_CNTL_INTER_RAM4_FORCE_NOISO_M (RTC_CNTL_INTER_RAM4_FORCE_NOISO_V << RTC_CNTL_INTER_RAM4_FORCE_NOISO_S) -#define RTC_CNTL_INTER_RAM4_FORCE_NOISO_V 0x00000001 -#define RTC_CNTL_INTER_RAM4_FORCE_NOISO_S 27 - -/* RTC_CNTL_INTER_RAM4_FORCE_ISO : R/W; bitpos: [26]; default: 0; - * internal SRAM 4 force ISO - */ - -#define RTC_CNTL_INTER_RAM4_FORCE_ISO (BIT(26)) -#define RTC_CNTL_INTER_RAM4_FORCE_ISO_M (RTC_CNTL_INTER_RAM4_FORCE_ISO_V << RTC_CNTL_INTER_RAM4_FORCE_ISO_S) -#define RTC_CNTL_INTER_RAM4_FORCE_ISO_V 0x00000001 -#define RTC_CNTL_INTER_RAM4_FORCE_ISO_S 26 - -/* RTC_CNTL_INTER_RAM3_FORCE_NOISO : R/W; bitpos: [25]; default: 1; - * internal SRAM 3 force no ISO - */ - -#define RTC_CNTL_INTER_RAM3_FORCE_NOISO (BIT(25)) -#define RTC_CNTL_INTER_RAM3_FORCE_NOISO_M (RTC_CNTL_INTER_RAM3_FORCE_NOISO_V << RTC_CNTL_INTER_RAM3_FORCE_NOISO_S) -#define RTC_CNTL_INTER_RAM3_FORCE_NOISO_V 0x00000001 -#define RTC_CNTL_INTER_RAM3_FORCE_NOISO_S 25 - -/* RTC_CNTL_INTER_RAM3_FORCE_ISO : R/W; bitpos: [24]; default: 0; - * internal SRAM 3 force ISO - */ - -#define RTC_CNTL_INTER_RAM3_FORCE_ISO (BIT(24)) -#define RTC_CNTL_INTER_RAM3_FORCE_ISO_M (RTC_CNTL_INTER_RAM3_FORCE_ISO_V << RTC_CNTL_INTER_RAM3_FORCE_ISO_S) -#define RTC_CNTL_INTER_RAM3_FORCE_ISO_V 0x00000001 -#define RTC_CNTL_INTER_RAM3_FORCE_ISO_S 24 - -/* RTC_CNTL_INTER_RAM2_FORCE_NOISO : R/W; bitpos: [23]; default: 1; - * internal SRAM 2 force no ISO - */ - -#define RTC_CNTL_INTER_RAM2_FORCE_NOISO (BIT(23)) -#define RTC_CNTL_INTER_RAM2_FORCE_NOISO_M (RTC_CNTL_INTER_RAM2_FORCE_NOISO_V << RTC_CNTL_INTER_RAM2_FORCE_NOISO_S) -#define RTC_CNTL_INTER_RAM2_FORCE_NOISO_V 0x00000001 -#define RTC_CNTL_INTER_RAM2_FORCE_NOISO_S 23 - -/* RTC_CNTL_INTER_RAM2_FORCE_ISO : R/W; bitpos: [22]; default: 0; - * internal SRAM 2 force ISO - */ - -#define RTC_CNTL_INTER_RAM2_FORCE_ISO (BIT(22)) -#define RTC_CNTL_INTER_RAM2_FORCE_ISO_M (RTC_CNTL_INTER_RAM2_FORCE_ISO_V << RTC_CNTL_INTER_RAM2_FORCE_ISO_S) -#define RTC_CNTL_INTER_RAM2_FORCE_ISO_V 0x00000001 -#define RTC_CNTL_INTER_RAM2_FORCE_ISO_S 22 - -/* RTC_CNTL_INTER_RAM1_FORCE_NOISO : R/W; bitpos: [21]; default: 1; - * internal SRAM 1 force no ISO - */ - -#define RTC_CNTL_INTER_RAM1_FORCE_NOISO (BIT(21)) -#define RTC_CNTL_INTER_RAM1_FORCE_NOISO_M (RTC_CNTL_INTER_RAM1_FORCE_NOISO_V << RTC_CNTL_INTER_RAM1_FORCE_NOISO_S) -#define RTC_CNTL_INTER_RAM1_FORCE_NOISO_V 0x00000001 -#define RTC_CNTL_INTER_RAM1_FORCE_NOISO_S 21 - -/* RTC_CNTL_INTER_RAM1_FORCE_ISO : R/W; bitpos: [20]; default: 0; - * internal SRAM 1 force ISO - */ - -#define RTC_CNTL_INTER_RAM1_FORCE_ISO (BIT(20)) -#define RTC_CNTL_INTER_RAM1_FORCE_ISO_M (RTC_CNTL_INTER_RAM1_FORCE_ISO_V << RTC_CNTL_INTER_RAM1_FORCE_ISO_S) -#define RTC_CNTL_INTER_RAM1_FORCE_ISO_V 0x00000001 -#define RTC_CNTL_INTER_RAM1_FORCE_ISO_S 20 - -/* RTC_CNTL_INTER_RAM0_FORCE_NOISO : R/W; bitpos: [19]; default: 1; - * internal SRAM 0 force no ISO - */ - -#define RTC_CNTL_INTER_RAM0_FORCE_NOISO (BIT(19)) -#define RTC_CNTL_INTER_RAM0_FORCE_NOISO_M (RTC_CNTL_INTER_RAM0_FORCE_NOISO_V << RTC_CNTL_INTER_RAM0_FORCE_NOISO_S) -#define RTC_CNTL_INTER_RAM0_FORCE_NOISO_V 0x00000001 -#define RTC_CNTL_INTER_RAM0_FORCE_NOISO_S 19 - -/* RTC_CNTL_INTER_RAM0_FORCE_ISO : R/W; bitpos: [18]; default: 0; - * internal SRAM 0 force ISO - */ - -#define RTC_CNTL_INTER_RAM0_FORCE_ISO (BIT(18)) -#define RTC_CNTL_INTER_RAM0_FORCE_ISO_M (RTC_CNTL_INTER_RAM0_FORCE_ISO_V << RTC_CNTL_INTER_RAM0_FORCE_ISO_S) -#define RTC_CNTL_INTER_RAM0_FORCE_ISO_V 0x00000001 -#define RTC_CNTL_INTER_RAM0_FORCE_ISO_S 18 - -/* RTC_CNTL_ROM0_FORCE_NOISO : R/W; bitpos: [17]; default: 1; - * ROM force no ISO - */ - -#define RTC_CNTL_ROM0_FORCE_NOISO (BIT(17)) -#define RTC_CNTL_ROM0_FORCE_NOISO_M (RTC_CNTL_ROM0_FORCE_NOISO_V << RTC_CNTL_ROM0_FORCE_NOISO_S) -#define RTC_CNTL_ROM0_FORCE_NOISO_V 0x00000001 -#define RTC_CNTL_ROM0_FORCE_NOISO_S 17 - -/* RTC_CNTL_ROM0_FORCE_ISO : R/W; bitpos: [16]; default: 0; - * ROM force ISO - */ - -#define RTC_CNTL_ROM0_FORCE_ISO (BIT(16)) -#define RTC_CNTL_ROM0_FORCE_ISO_M (RTC_CNTL_ROM0_FORCE_ISO_V << RTC_CNTL_ROM0_FORCE_ISO_S) -#define RTC_CNTL_ROM0_FORCE_ISO_V 0x00000001 -#define RTC_CNTL_ROM0_FORCE_ISO_S 16 - -/* RTC_CNTL_DG_PAD_FORCE_HOLD : R/W; bitpos: [15]; default: 0; - * digital pad force hold - */ - -#define RTC_CNTL_DG_PAD_FORCE_HOLD (BIT(15)) -#define RTC_CNTL_DG_PAD_FORCE_HOLD_M (RTC_CNTL_DG_PAD_FORCE_HOLD_V << RTC_CNTL_DG_PAD_FORCE_HOLD_S) -#define RTC_CNTL_DG_PAD_FORCE_HOLD_V 0x00000001 -#define RTC_CNTL_DG_PAD_FORCE_HOLD_S 15 - -/* RTC_CNTL_DG_PAD_FORCE_UNHOLD : R/W; bitpos: [14]; default: 1; - * digital pad force un-hold - */ - -#define RTC_CNTL_DG_PAD_FORCE_UNHOLD (BIT(14)) -#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_M (RTC_CNTL_DG_PAD_FORCE_UNHOLD_V << RTC_CNTL_DG_PAD_FORCE_UNHOLD_S) -#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_V 0x00000001 -#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_S 14 - -/* RTC_CNTL_DG_PAD_FORCE_ISO : R/W; bitpos: [13]; default: 0; - * digital pad force ISO - */ - -#define RTC_CNTL_DG_PAD_FORCE_ISO (BIT(13)) -#define RTC_CNTL_DG_PAD_FORCE_ISO_M (RTC_CNTL_DG_PAD_FORCE_ISO_V << RTC_CNTL_DG_PAD_FORCE_ISO_S) -#define RTC_CNTL_DG_PAD_FORCE_ISO_V 0x00000001 -#define RTC_CNTL_DG_PAD_FORCE_ISO_S 13 - -/* RTC_CNTL_DG_PAD_FORCE_NOISO : R/W; bitpos: [12]; default: 1; - * digital pad force no ISO - */ - -#define RTC_CNTL_DG_PAD_FORCE_NOISO (BIT(12)) -#define RTC_CNTL_DG_PAD_FORCE_NOISO_M (RTC_CNTL_DG_PAD_FORCE_NOISO_V << RTC_CNTL_DG_PAD_FORCE_NOISO_S) -#define RTC_CNTL_DG_PAD_FORCE_NOISO_V 0x00000001 -#define RTC_CNTL_DG_PAD_FORCE_NOISO_S 12 - -/* RTC_CNTL_DG_PAD_AUTOHOLD_EN : R/W; bitpos: [11]; default: 0; - * digital pad enable auto-hold - */ - -#define RTC_CNTL_DG_PAD_AUTOHOLD_EN (BIT(11)) -#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_M (RTC_CNTL_DG_PAD_AUTOHOLD_EN_V << RTC_CNTL_DG_PAD_AUTOHOLD_EN_S) -#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_V 0x00000001 -#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_S 11 - -/* RTC_CNTL_CLR_DG_PAD_AUTOHOLD : WO; bitpos: [10]; default: 0; - * wtite only register to clear digital pad auto-hold - */ - -#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD (BIT(10)) -#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_M (RTC_CNTL_CLR_DG_PAD_AUTOHOLD_V << RTC_CNTL_CLR_DG_PAD_AUTOHOLD_S) -#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_V 0x00000001 -#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_S 10 - -/* RTC_CNTL_DG_PAD_AUTOHOLD : RO; bitpos: [9]; default: 0; - * read only register to indicate digital pad auto-hold status - */ - -#define RTC_CNTL_DG_PAD_AUTOHOLD (BIT(9)) -#define RTC_CNTL_DG_PAD_AUTOHOLD_M (RTC_CNTL_DG_PAD_AUTOHOLD_V << RTC_CNTL_DG_PAD_AUTOHOLD_S) -#define RTC_CNTL_DG_PAD_AUTOHOLD_V 0x00000001 -#define RTC_CNTL_DG_PAD_AUTOHOLD_S 9 - -/* RTC_CNTL_DIG_ISO_FORCE_ON : R/W; bitpos: [8]; default: 0; */ - -#define RTC_CNTL_DIG_ISO_FORCE_ON (BIT(8)) -#define RTC_CNTL_DIG_ISO_FORCE_ON_M (RTC_CNTL_DIG_ISO_FORCE_ON_V << RTC_CNTL_DIG_ISO_FORCE_ON_S) -#define RTC_CNTL_DIG_ISO_FORCE_ON_V 0x00000001 -#define RTC_CNTL_DIG_ISO_FORCE_ON_S 8 - -/* RTC_CNTL_DIG_ISO_FORCE_OFF : R/W; bitpos: [7]; default: 0; */ - -#define RTC_CNTL_DIG_ISO_FORCE_OFF (BIT(7)) -#define RTC_CNTL_DIG_ISO_FORCE_OFF_M (RTC_CNTL_DIG_ISO_FORCE_OFF_V << RTC_CNTL_DIG_ISO_FORCE_OFF_S) -#define RTC_CNTL_DIG_ISO_FORCE_OFF_V 0x00000001 -#define RTC_CNTL_DIG_ISO_FORCE_OFF_S 7 - -/* RTC_CNTL_WDTCONFIG0_REG register - * configure rtc watch dog register - */ - -#define RTC_CNTL_WDTCONFIG0_REG (DR_REG_RTCCNTL_BASE + 0x94) - -/* RTC_CNTL_WDT_EN : R/W; bitpos: [31]; default: 0; - * enable rtc wdt - */ - -#define RTC_CNTL_WDT_EN (BIT(31)) -#define RTC_CNTL_WDT_EN_M (RTC_CNTL_WDT_EN_V << RTC_CNTL_WDT_EN_S) -#define RTC_CNTL_WDT_EN_V 0x00000001 -#define RTC_CNTL_WDT_EN_S 31 - -/* RTC_CNTL_WDT_STG0 : R/W; bitpos: [30:28]; default: 0; - * 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en - * 4: RTC reset stage en - */ - -#define RTC_CNTL_WDT_STG0 0x00000007 -#define RTC_CNTL_WDT_STG0_M (RTC_CNTL_WDT_STG0_V << RTC_CNTL_WDT_STG0_S) -#define RTC_CNTL_WDT_STG0_V 0x00000007 -#define RTC_CNTL_WDT_STG0_S 28 - -/* RTC_CNTL_WDT_STG1 : R/W; bitpos: [27:25]; default: 0; - * 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en - * 4: RTC reset stage en - */ - -#define RTC_CNTL_WDT_STG1 0x00000007 -#define RTC_CNTL_WDT_STG1_M (RTC_CNTL_WDT_STG1_V << RTC_CNTL_WDT_STG1_S) -#define RTC_CNTL_WDT_STG1_V 0x00000007 -#define RTC_CNTL_WDT_STG1_S 25 - -/* RTC_CNTL_WDT_STG2 : R/W; bitpos: [24:22]; default: 0; - * 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en - * 4: RTC reset stage en - */ - -#define RTC_CNTL_WDT_STG2 0x00000007 -#define RTC_CNTL_WDT_STG2_M (RTC_CNTL_WDT_STG2_V << RTC_CNTL_WDT_STG2_S) -#define RTC_CNTL_WDT_STG2_V 0x00000007 -#define RTC_CNTL_WDT_STG2_S 22 - -/* RTC_CNTL_WDT_STG3 : R/W; bitpos: [21:19]; default: 0; - * 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en - * 4: RTC reset stage en - */ - -#define RTC_CNTL_WDT_STG3 0x00000007 -#define RTC_CNTL_WDT_STG3_M (RTC_CNTL_WDT_STG3_V << RTC_CNTL_WDT_STG3_S) -#define RTC_CNTL_WDT_STG3_V 0x00000007 -#define RTC_CNTL_WDT_STG3_S 19 - -/* RTC_CNTL_WDT_STGX : - * description: stage action selection values - */ - -#define RTC_WDT_STG_SEL_OFF 0 -#define RTC_WDT_STG_SEL_INT 1 -#define RTC_WDT_STG_SEL_RESET_CPU 2 -#define RTC_WDT_STG_SEL_RESET_SYSTEM 3 -#define RTC_WDT_STG_SEL_RESET_RTC 4 - -/* RTC_CNTL_WDT_CPU_RESET_LENGTH : R/W; bitpos: [18:16]; default: 1; - * CPU reset counter length - */ - -#define RTC_CNTL_WDT_CPU_RESET_LENGTH 0x00000007 -#define RTC_CNTL_WDT_CPU_RESET_LENGTH_M (RTC_CNTL_WDT_CPU_RESET_LENGTH_V << RTC_CNTL_WDT_CPU_RESET_LENGTH_S) -#define RTC_CNTL_WDT_CPU_RESET_LENGTH_V 0x00000007 -#define RTC_CNTL_WDT_CPU_RESET_LENGTH_S 16 - -/* RTC_CNTL_WDT_SYS_RESET_LENGTH : R/W; bitpos: [15:13]; default: 1; - * system reset counter length - */ - -#define RTC_CNTL_WDT_SYS_RESET_LENGTH 0x00000007 -#define RTC_CNTL_WDT_SYS_RESET_LENGTH_M (RTC_CNTL_WDT_SYS_RESET_LENGTH_V << RTC_CNTL_WDT_SYS_RESET_LENGTH_S) -#define RTC_CNTL_WDT_SYS_RESET_LENGTH_V 0x00000007 -#define RTC_CNTL_WDT_SYS_RESET_LENGTH_S 13 - -/* RTC_CNTL_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [12]; default: 1; - * enable WDT in flash boot - */ - -#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN (BIT(12)) -#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_M (RTC_CNTL_WDT_FLASHBOOT_MOD_EN_V << RTC_CNTL_WDT_FLASHBOOT_MOD_EN_S) -#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_V 0x00000001 -#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_S 12 - -/* RTC_CNTL_WDT_PROCPU_RESET_EN : R/W; bitpos: [11]; default: 0; - * enable WDT reset PRO CPU - */ - -#define RTC_CNTL_WDT_PROCPU_RESET_EN (BIT(11)) -#define RTC_CNTL_WDT_PROCPU_RESET_EN_M (RTC_CNTL_WDT_PROCPU_RESET_EN_V << RTC_CNTL_WDT_PROCPU_RESET_EN_S) -#define RTC_CNTL_WDT_PROCPU_RESET_EN_V 0x00000001 -#define RTC_CNTL_WDT_PROCPU_RESET_EN_S 11 - -/* RTC_CNTL_WDT_APPCPU_RESET_EN : R/W; bitpos: [10]; default: 0; - * enable WDT reset APP CPU - */ - -#define RTC_CNTL_WDT_APPCPU_RESET_EN (BIT(10)) -#define RTC_CNTL_WDT_APPCPU_RESET_EN_M (RTC_CNTL_WDT_APPCPU_RESET_EN_V << RTC_CNTL_WDT_APPCPU_RESET_EN_S) -#define RTC_CNTL_WDT_APPCPU_RESET_EN_V 0x00000001 -#define RTC_CNTL_WDT_APPCPU_RESET_EN_S 10 - -/* RTC_CNTL_WDT_PAUSE_IN_SLP : R/W; bitpos: [9]; default: 1; - * pause WDT in sleep - */ - -#define RTC_CNTL_WDT_PAUSE_IN_SLP (BIT(9)) -#define RTC_CNTL_WDT_PAUSE_IN_SLP_M (RTC_CNTL_WDT_PAUSE_IN_SLP_V << RTC_CNTL_WDT_PAUSE_IN_SLP_S) -#define RTC_CNTL_WDT_PAUSE_IN_SLP_V 0x00000001 -#define RTC_CNTL_WDT_PAUSE_IN_SLP_S 9 - -/* RTC_CNTL_WDT_CHIP_RESET_EN : R/W; bitpos: [8]; default: 0; - * wdt reset whole chip enable - */ - -#define RTC_CNTL_WDT_CHIP_RESET_EN (BIT(8)) -#define RTC_CNTL_WDT_CHIP_RESET_EN_M (RTC_CNTL_WDT_CHIP_RESET_EN_V << RTC_CNTL_WDT_CHIP_RESET_EN_S) -#define RTC_CNTL_WDT_CHIP_RESET_EN_V 0x00000001 -#define RTC_CNTL_WDT_CHIP_RESET_EN_S 8 - -/* RTC_CNTL_WDT_CHIP_RESET_WIDTH : R/W; bitpos: [7:0]; default: 20; - * chip reset siginal pulse width - */ - -#define RTC_CNTL_WDT_CHIP_RESET_WIDTH 0x000000FF -#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_M (RTC_CNTL_WDT_CHIP_RESET_WIDTH_V << RTC_CNTL_WDT_CHIP_RESET_WIDTH_S) -#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_V 0x000000FF -#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_S 0 - -/* RTC_CNTL_WDTCONFIG1_REG register - * Configure hold time of rtc wdt at level1 - */ - -#define RTC_CNTL_WDTCONFIG1_REG (DR_REG_RTCCNTL_BASE + 0x98) - -/* RTC_CNTL_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 200000; - * Configure hold time of rtc wdt at level1 - */ - -#define RTC_CNTL_WDT_STG0_HOLD 0xFFFFFFFF -#define RTC_CNTL_WDT_STG0_HOLD_M (RTC_CNTL_WDT_STG0_HOLD_V << RTC_CNTL_WDT_STG0_HOLD_S) -#define RTC_CNTL_WDT_STG0_HOLD_V 0xFFFFFFFF -#define RTC_CNTL_WDT_STG0_HOLD_S 0 - -/* RTC_CNTL_WDTCONFIG2_REG register - * Configure hold time of rtc wdt at level2 - */ - -#define RTC_CNTL_WDTCONFIG2_REG (DR_REG_RTCCNTL_BASE + 0x9c) - -/* RTC_CNTL_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 80000; - * Configure hold time of rtc wdt at level2 - */ - -#define RTC_CNTL_WDT_STG1_HOLD 0xFFFFFFFF -#define RTC_CNTL_WDT_STG1_HOLD_M (RTC_CNTL_WDT_STG1_HOLD_V << RTC_CNTL_WDT_STG1_HOLD_S) -#define RTC_CNTL_WDT_STG1_HOLD_V 0xFFFFFFFF -#define RTC_CNTL_WDT_STG1_HOLD_S 0 - -/* RTC_CNTL_WDTCONFIG3_REG register - * Configure hold time of rtc wdt at level3 - */ - -#define RTC_CNTL_WDTCONFIG3_REG (DR_REG_RTCCNTL_BASE + 0xa0) - -/* RTC_CNTL_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 4095; - * Configure hold time of rtc wdt at level3 - */ - -#define RTC_CNTL_WDT_STG2_HOLD 0xFFFFFFFF -#define RTC_CNTL_WDT_STG2_HOLD_M (RTC_CNTL_WDT_STG2_HOLD_V << RTC_CNTL_WDT_STG2_HOLD_S) -#define RTC_CNTL_WDT_STG2_HOLD_V 0xFFFFFFFF -#define RTC_CNTL_WDT_STG2_HOLD_S 0 - -/* RTC_CNTL_WDTCONFIG4_REG register - * Configure hold time of rtc wdt at level4 - */ - -#define RTC_CNTL_WDTCONFIG4_REG (DR_REG_RTCCNTL_BASE + 0xa4) - -/* RTC_CNTL_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 4095; - * Configure hold time of rtc wdt at level4 - */ - -#define RTC_CNTL_WDT_STG3_HOLD 0xFFFFFFFF -#define RTC_CNTL_WDT_STG3_HOLD_M (RTC_CNTL_WDT_STG3_HOLD_V << RTC_CNTL_WDT_STG3_HOLD_S) -#define RTC_CNTL_WDT_STG3_HOLD_V 0xFFFFFFFF -#define RTC_CNTL_WDT_STG3_HOLD_S 0 - -/* RTC_CNTL_WDTFEED_REG register - * feed rtc wdt by sw - */ - -#define RTC_CNTL_WDTFEED_REG (DR_REG_RTCCNTL_BASE + 0xa8) - -/* RTC_CNTL_WDT_FEED : WO; bitpos: [31]; default: 0; - * Set 1 to feed rtc wdt - */ - -#define RTC_CNTL_WDT_FEED (BIT(31)) -#define RTC_CNTL_WDT_FEED_M (RTC_CNTL_WDT_FEED_V << RTC_CNTL_WDT_FEED_S) -#define RTC_CNTL_WDT_FEED_V 0x00000001 -#define RTC_CNTL_WDT_FEED_S 31 - -/* RTC_CNTL_WDTWPROTECT_REG register - * configure rtc wdt write protect - */ - -#define RTC_CNTL_WDTWPROTECT_REG (DR_REG_RTCCNTL_BASE + 0xac) - -/* RTC_CNTL_WDT_WKEY : R/W; bitpos: [31:0]; default: 1356348065; - * wdt_wprotectn - */ - -#define RTC_CNTL_WDT_WKEY 0xFFFFFFFF -#define RTC_CNTL_WDT_WKEY_M (RTC_CNTL_WDT_WKEY_V << RTC_CNTL_WDT_WKEY_S) -#define RTC_CNTL_WDT_WKEY_V 0xFFFFFFFF -#define RTC_CNTL_WDT_WKEY_S 0 - -/* RTC_CNTL_SWD_CONF_REG register - * configure super watch dog - */ - -#define RTC_CNTL_SWD_CONF_REG (DR_REG_RTCCNTL_BASE + 0xb0) - -/* RTC_CNTL_SWD_AUTO_FEED_EN : R/W; bitpos: [31]; default: 0; - * automatically feed swd when int comes - */ - -#define RTC_CNTL_SWD_AUTO_FEED_EN (BIT(31)) -#define RTC_CNTL_SWD_AUTO_FEED_EN_M (RTC_CNTL_SWD_AUTO_FEED_EN_V << RTC_CNTL_SWD_AUTO_FEED_EN_S) -#define RTC_CNTL_SWD_AUTO_FEED_EN_V 0x00000001 -#define RTC_CNTL_SWD_AUTO_FEED_EN_S 31 - -/* RTC_CNTL_SWD_DISABLE : R/W; bitpos: [30]; default: 0; - * disable SWD - */ - -#define RTC_CNTL_SWD_DISABLE (BIT(30)) -#define RTC_CNTL_SWD_DISABLE_M (RTC_CNTL_SWD_DISABLE_V << RTC_CNTL_SWD_DISABLE_S) -#define RTC_CNTL_SWD_DISABLE_V 0x00000001 -#define RTC_CNTL_SWD_DISABLE_S 30 - -/* RTC_CNTL_SWD_FEED : WO; bitpos: [29]; default: 0; - * Sw feed swd - */ - -#define RTC_CNTL_SWD_FEED (BIT(29)) -#define RTC_CNTL_SWD_FEED_M (RTC_CNTL_SWD_FEED_V << RTC_CNTL_SWD_FEED_S) -#define RTC_CNTL_SWD_FEED_V 0x00000001 -#define RTC_CNTL_SWD_FEED_S 29 - -/* RTC_CNTL_SWD_RST_FLAG_CLR : WO; bitpos: [28]; default: 0; - * reset swd reset flag - */ - -#define RTC_CNTL_SWD_RST_FLAG_CLR (BIT(28)) -#define RTC_CNTL_SWD_RST_FLAG_CLR_M (RTC_CNTL_SWD_RST_FLAG_CLR_V << RTC_CNTL_SWD_RST_FLAG_CLR_S) -#define RTC_CNTL_SWD_RST_FLAG_CLR_V 0x00000001 -#define RTC_CNTL_SWD_RST_FLAG_CLR_S 28 - -/* RTC_CNTL_SWD_SIGNAL_WIDTH : R/W; bitpos: [27:18]; default: 300; - * adjust signal width send to swd - */ - -#define RTC_CNTL_SWD_SIGNAL_WIDTH 0x000003FF -#define RTC_CNTL_SWD_SIGNAL_WIDTH_M (RTC_CNTL_SWD_SIGNAL_WIDTH_V << RTC_CNTL_SWD_SIGNAL_WIDTH_S) -#define RTC_CNTL_SWD_SIGNAL_WIDTH_V 0x000003FF -#define RTC_CNTL_SWD_SIGNAL_WIDTH_S 18 - -/* RTC_CNTL_SWD_FEED_INT : RO; bitpos: [1]; default: 0; - * swd interrupt for feeding - */ - -#define RTC_CNTL_SWD_FEED_INT (BIT(1)) -#define RTC_CNTL_SWD_FEED_INT_M (RTC_CNTL_SWD_FEED_INT_V << RTC_CNTL_SWD_FEED_INT_S) -#define RTC_CNTL_SWD_FEED_INT_V 0x00000001 -#define RTC_CNTL_SWD_FEED_INT_S 1 - -/* RTC_CNTL_SWD_RESET_FLAG : RO; bitpos: [0]; default: 0; - * swd reset flag - */ - -#define RTC_CNTL_SWD_RESET_FLAG (BIT(0)) -#define RTC_CNTL_SWD_RESET_FLAG_M (RTC_CNTL_SWD_RESET_FLAG_V << RTC_CNTL_SWD_RESET_FLAG_S) -#define RTC_CNTL_SWD_RESET_FLAG_V 0x00000001 -#define RTC_CNTL_SWD_RESET_FLAG_S 0 - -/* RTC_CNTL_SWD_WPROTECT_REG register - * configure super watch dog write protect - */ - -#define RTC_CNTL_SWD_WPROTECT_REG (DR_REG_RTCCNTL_BASE + 0xb4) - -/* RTC_CNTL_SWD_WKEY : R/W; bitpos: [31:0]; default: 2401055018; - * swd write protect - */ - -#define RTC_CNTL_SWD_WKEY 0xFFFFFFFF -#define RTC_CNTL_SWD_WKEY_M (RTC_CNTL_SWD_WKEY_V << RTC_CNTL_SWD_WKEY_S) -#define RTC_CNTL_SWD_WKEY_V 0xFFFFFFFF -#define RTC_CNTL_SWD_WKEY_S 0 - -/* RTC_CNTL_SW_CPU_STALL_REG register - * configure cpu stall register - */ - -#define RTC_CNTL_SW_CPU_STALL_REG (DR_REG_RTCCNTL_BASE + 0xb8) - -/* RTC_CNTL_SW_STALL_PROCPU_C1 : R/W; bitpos: [31:26]; default: 0; - * enable cpu enter stall status by sw - */ - -#define RTC_CNTL_SW_STALL_PROCPU_C1 0x0000003F -#define RTC_CNTL_SW_STALL_PROCPU_C1_M (RTC_CNTL_SW_STALL_PROCPU_C1_V << RTC_CNTL_SW_STALL_PROCPU_C1_S) -#define RTC_CNTL_SW_STALL_PROCPU_C1_V 0x0000003F -#define RTC_CNTL_SW_STALL_PROCPU_C1_S 26 - -/* RTC_CNTL_SW_STALL_APPCPU_C1 : R/W; bitpos: [25:20]; default: 0; - * {reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == 0x86 will - * stall APP CPU - */ - -#define RTC_CNTL_SW_STALL_APPCPU_C1 0x0000003F -#define RTC_CNTL_SW_STALL_APPCPU_C1_M (RTC_CNTL_SW_STALL_APPCPU_C1_V << RTC_CNTL_SW_STALL_APPCPU_C1_S) -#define RTC_CNTL_SW_STALL_APPCPU_C1_V 0x0000003F -#define RTC_CNTL_SW_STALL_APPCPU_C1_S 20 - -/* RTC_CNTL_STORE4_REG register - * reservation register4 - */ - -#define RTC_CNTL_STORE4_REG (DR_REG_RTCCNTL_BASE + 0xbc) - -/* RTC_CNTL_SCRATCH4 : R/W; bitpos: [31:0]; default: 0; - * reservation register4 - */ - -#define RTC_CNTL_SCRATCH4 0xFFFFFFFF -#define RTC_CNTL_SCRATCH4_M (RTC_CNTL_SCRATCH4_V << RTC_CNTL_SCRATCH4_S) -#define RTC_CNTL_SCRATCH4_V 0xFFFFFFFF -#define RTC_CNTL_SCRATCH4_S 0 - -/* RTC_CNTL_STORE5_REG register - * reservation register5 - */ - -#define RTC_CNTL_STORE5_REG (DR_REG_RTCCNTL_BASE + 0xc0) - -/* RTC_CNTL_SCRATCH5 : R/W; bitpos: [31:0]; default: 0; - * reservation register5 - */ - -#define RTC_CNTL_SCRATCH5 0xFFFFFFFF -#define RTC_CNTL_SCRATCH5_M (RTC_CNTL_SCRATCH5_V << RTC_CNTL_SCRATCH5_S) -#define RTC_CNTL_SCRATCH5_V 0xFFFFFFFF -#define RTC_CNTL_SCRATCH5_S 0 - -/* RTC_CNTL_STORE6_REG register - * reservation register6 - */ - -#define RTC_CNTL_STORE6_REG (DR_REG_RTCCNTL_BASE + 0xc4) - -/* RTC_CNTL_SCRATCH6 : R/W; bitpos: [31:0]; default: 0; - * reservation register6 - */ - -#define RTC_CNTL_SCRATCH6 0xFFFFFFFF -#define RTC_CNTL_SCRATCH6_M (RTC_CNTL_SCRATCH6_V << RTC_CNTL_SCRATCH6_S) -#define RTC_CNTL_SCRATCH6_V 0xFFFFFFFF -#define RTC_CNTL_SCRATCH6_S 0 - -/* RTC_CNTL_STORE7_REG register - * reservation register7 - */ - -#define RTC_CNTL_STORE7_REG (DR_REG_RTCCNTL_BASE + 0xc8) - -/* RTC_CNTL_SCRATCH7 : R/W; bitpos: [31:0]; default: 0; - * reservation register7 - */ - -#define RTC_CNTL_SCRATCH7 0xFFFFFFFF -#define RTC_CNTL_SCRATCH7_M (RTC_CNTL_SCRATCH7_V << RTC_CNTL_SCRATCH7_S) -#define RTC_CNTL_SCRATCH7_V 0xFFFFFFFF -#define RTC_CNTL_SCRATCH7_S 0 - -/* RTC_CNTL_LOW_POWER_ST_REG register - * rtc main state machine status - */ - -#define RTC_CNTL_LOW_POWER_ST_REG (DR_REG_RTCCNTL_BASE + 0xcc) - -/* RTC_CNTL_MAIN_STATE : RO; bitpos: [31:28]; default: 0; - * rtc main state machine status - */ - -#define RTC_CNTL_MAIN_STATE 0x0000000F -#define RTC_CNTL_MAIN_STATE_M (RTC_CNTL_MAIN_STATE_V << RTC_CNTL_MAIN_STATE_S) -#define RTC_CNTL_MAIN_STATE_V 0x0000000F -#define RTC_CNTL_MAIN_STATE_S 28 - -/* RTC_CNTL_MAIN_STATE_IN_IDLE : RO; bitpos: [27]; default: 0; - * rtc main state machine is in idle state - */ - -#define RTC_CNTL_MAIN_STATE_IN_IDLE (BIT(27)) -#define RTC_CNTL_MAIN_STATE_IN_IDLE_M (RTC_CNTL_MAIN_STATE_IN_IDLE_V << RTC_CNTL_MAIN_STATE_IN_IDLE_S) -#define RTC_CNTL_MAIN_STATE_IN_IDLE_V 0x00000001 -#define RTC_CNTL_MAIN_STATE_IN_IDLE_S 27 - -/* RTC_CNTL_MAIN_STATE_IN_SLP : RO; bitpos: [26]; default: 0; - * rtc main state machine is in sleep state - */ - -#define RTC_CNTL_MAIN_STATE_IN_SLP (BIT(26)) -#define RTC_CNTL_MAIN_STATE_IN_SLP_M (RTC_CNTL_MAIN_STATE_IN_SLP_V << RTC_CNTL_MAIN_STATE_IN_SLP_S) -#define RTC_CNTL_MAIN_STATE_IN_SLP_V 0x00000001 -#define RTC_CNTL_MAIN_STATE_IN_SLP_S 26 - -/* RTC_CNTL_MAIN_STATE_IN_WAIT_XTL : RO; bitpos: [25]; default: 0; - * rtc main state machine is in wait xtal state - */ - -#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL (BIT(25)) -#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_M (RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_V << RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_S) -#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_V 0x00000001 -#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_S 25 - -/* RTC_CNTL_MAIN_STATE_IN_WAIT_PLL : RO; bitpos: [24]; default: 0; - * rtc main state machine is in wait pll state - */ - -#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL (BIT(24)) -#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_M (RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_V << RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_S) -#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_V 0x00000001 -#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_S 24 - -/* RTC_CNTL_MAIN_STATE_IN_WAIT_8M : RO; bitpos: [23]; default: 0; - * rtc main state machine is in wait 8m state - */ - -#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M (BIT(23)) -#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_M (RTC_CNTL_MAIN_STATE_IN_WAIT_8M_V << RTC_CNTL_MAIN_STATE_IN_WAIT_8M_S) -#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_V 0x00000001 -#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_S 23 - -/* RTC_CNTL_IN_LOW_POWER_STATE : RO; bitpos: [22]; default: 0; - * rtc main state machine is in the states of low power - */ - -#define RTC_CNTL_IN_LOW_POWER_STATE (BIT(22)) -#define RTC_CNTL_IN_LOW_POWER_STATE_M (RTC_CNTL_IN_LOW_POWER_STATE_V << RTC_CNTL_IN_LOW_POWER_STATE_S) -#define RTC_CNTL_IN_LOW_POWER_STATE_V 0x00000001 -#define RTC_CNTL_IN_LOW_POWER_STATE_S 22 - -/* RTC_CNTL_IN_WAKEUP_STATE : RO; bitpos: [21]; default: 0; - * rtc main state machine is in the states of wakeup process - */ - -#define RTC_CNTL_IN_WAKEUP_STATE (BIT(21)) -#define RTC_CNTL_IN_WAKEUP_STATE_M (RTC_CNTL_IN_WAKEUP_STATE_V << RTC_CNTL_IN_WAKEUP_STATE_S) -#define RTC_CNTL_IN_WAKEUP_STATE_V 0x00000001 -#define RTC_CNTL_IN_WAKEUP_STATE_S 21 - -/* RTC_CNTL_MAIN_STATE_WAIT_END : RO; bitpos: [20]; default: 0; - * rtc main state machine has been waited for some cycles - */ - -#define RTC_CNTL_MAIN_STATE_WAIT_END (BIT(20)) -#define RTC_CNTL_MAIN_STATE_WAIT_END_M (RTC_CNTL_MAIN_STATE_WAIT_END_V << RTC_CNTL_MAIN_STATE_WAIT_END_S) -#define RTC_CNTL_MAIN_STATE_WAIT_END_V 0x00000001 -#define RTC_CNTL_MAIN_STATE_WAIT_END_S 20 - -/* RTC_CNTL_RDY_FOR_WAKEUP : RO; bitpos: [19]; default: 0; - * rtc is ready to receive wake up trigger from wake up source - */ - -#define RTC_CNTL_RDY_FOR_WAKEUP (BIT(19)) -#define RTC_CNTL_RDY_FOR_WAKEUP_M (RTC_CNTL_RDY_FOR_WAKEUP_V << RTC_CNTL_RDY_FOR_WAKEUP_S) -#define RTC_CNTL_RDY_FOR_WAKEUP_V 0x00000001 -#define RTC_CNTL_RDY_FOR_WAKEUP_S 19 - -/* RTC_CNTL_MAIN_STATE_PLL_ON : RO; bitpos: [18]; default: 0; - * rtc main state machine is in states that pll should be running - */ - -#define RTC_CNTL_MAIN_STATE_PLL_ON (BIT(18)) -#define RTC_CNTL_MAIN_STATE_PLL_ON_M (RTC_CNTL_MAIN_STATE_PLL_ON_V << RTC_CNTL_MAIN_STATE_PLL_ON_S) -#define RTC_CNTL_MAIN_STATE_PLL_ON_V 0x00000001 -#define RTC_CNTL_MAIN_STATE_PLL_ON_S 18 - -/* RTC_CNTL_MAIN_STATE_XTAL_ISO : RO; bitpos: [17]; default: 0; - * no use any more - */ - -#define RTC_CNTL_MAIN_STATE_XTAL_ISO (BIT(17)) -#define RTC_CNTL_MAIN_STATE_XTAL_ISO_M (RTC_CNTL_MAIN_STATE_XTAL_ISO_V << RTC_CNTL_MAIN_STATE_XTAL_ISO_S) -#define RTC_CNTL_MAIN_STATE_XTAL_ISO_V 0x00000001 -#define RTC_CNTL_MAIN_STATE_XTAL_ISO_S 17 - -/* RTC_CNTL_COCPU_STATE_DONE : RO; bitpos: [16]; default: 0; - * ulp/cocpu is done - */ - -#define RTC_CNTL_COCPU_STATE_DONE (BIT(16)) -#define RTC_CNTL_COCPU_STATE_DONE_M (RTC_CNTL_COCPU_STATE_DONE_V << RTC_CNTL_COCPU_STATE_DONE_S) -#define RTC_CNTL_COCPU_STATE_DONE_V 0x00000001 -#define RTC_CNTL_COCPU_STATE_DONE_S 16 - -/* RTC_CNTL_COCPU_STATE_SLP : RO; bitpos: [15]; default: 0; - * ulp/cocpu is in sleep state - */ - -#define RTC_CNTL_COCPU_STATE_SLP (BIT(15)) -#define RTC_CNTL_COCPU_STATE_SLP_M (RTC_CNTL_COCPU_STATE_SLP_V << RTC_CNTL_COCPU_STATE_SLP_S) -#define RTC_CNTL_COCPU_STATE_SLP_V 0x00000001 -#define RTC_CNTL_COCPU_STATE_SLP_S 15 - -/* RTC_CNTL_COCPU_STATE_SWITCH : RO; bitpos: [14]; default: 0; - * ulp/cocpu is about to working. Switch rtc main state - */ - -#define RTC_CNTL_COCPU_STATE_SWITCH (BIT(14)) -#define RTC_CNTL_COCPU_STATE_SWITCH_M (RTC_CNTL_COCPU_STATE_SWITCH_V << RTC_CNTL_COCPU_STATE_SWITCH_S) -#define RTC_CNTL_COCPU_STATE_SWITCH_V 0x00000001 -#define RTC_CNTL_COCPU_STATE_SWITCH_S 14 - -/* RTC_CNTL_COCPU_STATE_START : RO; bitpos: [13]; default: 0; - * ulp/cocpu should start to work - */ - -#define RTC_CNTL_COCPU_STATE_START (BIT(13)) -#define RTC_CNTL_COCPU_STATE_START_M (RTC_CNTL_COCPU_STATE_START_V << RTC_CNTL_COCPU_STATE_START_S) -#define RTC_CNTL_COCPU_STATE_START_V 0x00000001 -#define RTC_CNTL_COCPU_STATE_START_S 13 - -/* RTC_CNTL_TOUCH_STATE_DONE : RO; bitpos: [12]; default: 0; - * touch is done - */ - -#define RTC_CNTL_TOUCH_STATE_DONE (BIT(12)) -#define RTC_CNTL_TOUCH_STATE_DONE_M (RTC_CNTL_TOUCH_STATE_DONE_V << RTC_CNTL_TOUCH_STATE_DONE_S) -#define RTC_CNTL_TOUCH_STATE_DONE_V 0x00000001 -#define RTC_CNTL_TOUCH_STATE_DONE_S 12 - -/* RTC_CNTL_TOUCH_STATE_SLP : RO; bitpos: [11]; default: 0; - * touch is in sleep state - */ - -#define RTC_CNTL_TOUCH_STATE_SLP (BIT(11)) -#define RTC_CNTL_TOUCH_STATE_SLP_M (RTC_CNTL_TOUCH_STATE_SLP_V << RTC_CNTL_TOUCH_STATE_SLP_S) -#define RTC_CNTL_TOUCH_STATE_SLP_V 0x00000001 -#define RTC_CNTL_TOUCH_STATE_SLP_S 11 - -/* RTC_CNTL_TOUCH_STATE_SWITCH : RO; bitpos: [10]; default: 0; - * touch is about to working. Switch rtc main state - */ - -#define RTC_CNTL_TOUCH_STATE_SWITCH (BIT(10)) -#define RTC_CNTL_TOUCH_STATE_SWITCH_M (RTC_CNTL_TOUCH_STATE_SWITCH_V << RTC_CNTL_TOUCH_STATE_SWITCH_S) -#define RTC_CNTL_TOUCH_STATE_SWITCH_V 0x00000001 -#define RTC_CNTL_TOUCH_STATE_SWITCH_S 10 - -/* RTC_CNTL_TOUCH_STATE_START : RO; bitpos: [9]; default: 0; - * touch should start to work - */ - -#define RTC_CNTL_TOUCH_STATE_START (BIT(9)) -#define RTC_CNTL_TOUCH_STATE_START_M (RTC_CNTL_TOUCH_STATE_START_V << RTC_CNTL_TOUCH_STATE_START_S) -#define RTC_CNTL_TOUCH_STATE_START_V 0x00000001 -#define RTC_CNTL_TOUCH_STATE_START_S 9 - -/* RTC_CNTL_XPD_DIG : RO; bitpos: [8]; default: 0; - * digital wrap power down - */ - -#define RTC_CNTL_XPD_DIG (BIT(8)) -#define RTC_CNTL_XPD_DIG_M (RTC_CNTL_XPD_DIG_V << RTC_CNTL_XPD_DIG_S) -#define RTC_CNTL_XPD_DIG_V 0x00000001 -#define RTC_CNTL_XPD_DIG_S 8 - -/* RTC_CNTL_DIG_ISO : RO; bitpos: [7]; default: 0; - * digital wrap iso - */ - -#define RTC_CNTL_DIG_ISO (BIT(7)) -#define RTC_CNTL_DIG_ISO_M (RTC_CNTL_DIG_ISO_V << RTC_CNTL_DIG_ISO_S) -#define RTC_CNTL_DIG_ISO_V 0x00000001 -#define RTC_CNTL_DIG_ISO_S 7 - -/* RTC_CNTL_XPD_WIFI : RO; bitpos: [6]; default: 0; - * wifi wrap power down - */ - -#define RTC_CNTL_XPD_WIFI (BIT(6)) -#define RTC_CNTL_XPD_WIFI_M (RTC_CNTL_XPD_WIFI_V << RTC_CNTL_XPD_WIFI_S) -#define RTC_CNTL_XPD_WIFI_V 0x00000001 -#define RTC_CNTL_XPD_WIFI_S 6 - -/* RTC_CNTL_WIFI_ISO : RO; bitpos: [5]; default: 0; - * wifi iso - */ - -#define RTC_CNTL_WIFI_ISO (BIT(5)) -#define RTC_CNTL_WIFI_ISO_M (RTC_CNTL_WIFI_ISO_V << RTC_CNTL_WIFI_ISO_S) -#define RTC_CNTL_WIFI_ISO_V 0x00000001 -#define RTC_CNTL_WIFI_ISO_S 5 - -/* RTC_CNTL_XPD_RTC_PERI : RO; bitpos: [4]; default: 0; - * rtc peripheral power down - */ - -#define RTC_CNTL_XPD_RTC_PERI (BIT(4)) -#define RTC_CNTL_XPD_RTC_PERI_M (RTC_CNTL_XPD_RTC_PERI_V << RTC_CNTL_XPD_RTC_PERI_S) -#define RTC_CNTL_XPD_RTC_PERI_V 0x00000001 -#define RTC_CNTL_XPD_RTC_PERI_S 4 - -/* RTC_CNTL_PERI_ISO : RO; bitpos: [3]; default: 0; - * rtc peripheral iso - */ - -#define RTC_CNTL_PERI_ISO (BIT(3)) -#define RTC_CNTL_PERI_ISO_M (RTC_CNTL_PERI_ISO_V << RTC_CNTL_PERI_ISO_S) -#define RTC_CNTL_PERI_ISO_V 0x00000001 -#define RTC_CNTL_PERI_ISO_S 3 - -/* RTC_CNTL_XPD_DIG_DCDC : RO; bitpos: [2]; default: 0; - * External DCDC power down - */ - -#define RTC_CNTL_XPD_DIG_DCDC (BIT(2)) -#define RTC_CNTL_XPD_DIG_DCDC_M (RTC_CNTL_XPD_DIG_DCDC_V << RTC_CNTL_XPD_DIG_DCDC_S) -#define RTC_CNTL_XPD_DIG_DCDC_V 0x00000001 -#define RTC_CNTL_XPD_DIG_DCDC_S 2 - -/* RTC_CNTL_XPD_ROM0 : RO; bitpos: [0]; default: 0; - * rom0 power down - */ - -#define RTC_CNTL_XPD_ROM0 (BIT(0)) -#define RTC_CNTL_XPD_ROM0_M (RTC_CNTL_XPD_ROM0_V << RTC_CNTL_XPD_ROM0_S) -#define RTC_CNTL_XPD_ROM0_V 0x00000001 -#define RTC_CNTL_XPD_ROM0_S 0 - -/* RTC_CNTL_DIAG0_REG register - * debug register - */ - -#define RTC_CNTL_DIAG0_REG (DR_REG_RTCCNTL_BASE + 0xd0) - -/* RTC_CNTL_LOW_POWER_DIAG1 : RO; bitpos: [31:0]; default: 0; */ - -#define RTC_CNTL_LOW_POWER_DIAG1 0xFFFFFFFF -#define RTC_CNTL_LOW_POWER_DIAG1_M (RTC_CNTL_LOW_POWER_DIAG1_V << RTC_CNTL_LOW_POWER_DIAG1_S) -#define RTC_CNTL_LOW_POWER_DIAG1_V 0xFFFFFFFF -#define RTC_CNTL_LOW_POWER_DIAG1_S 0 - -/* RTC_CNTL_PAD_HOLD_REG register - * configure rtc pad hold register - */ - -#define RTC_CNTL_PAD_HOLD_REG (DR_REG_RTCCNTL_BASE + 0xd4) - -/* RTC_CNTL_PAD21_HOLD : R/W; bitpos: [21]; default: 0; - * set rtc_pad21_hold - */ - -#define RTC_CNTL_PAD21_HOLD (BIT(21)) -#define RTC_CNTL_PAD21_HOLD_M (RTC_CNTL_PAD21_HOLD_V << RTC_CNTL_PAD21_HOLD_S) -#define RTC_CNTL_PAD21_HOLD_V 0x00000001 -#define RTC_CNTL_PAD21_HOLD_S 21 - -/* RTC_CNTL_PAD20_HOLD : R/W; bitpos: [20]; default: 0; - * set rtc_pad20_hold - */ - -#define RTC_CNTL_PAD20_HOLD (BIT(20)) -#define RTC_CNTL_PAD20_HOLD_M (RTC_CNTL_PAD20_HOLD_V << RTC_CNTL_PAD20_HOLD_S) -#define RTC_CNTL_PAD20_HOLD_V 0x00000001 -#define RTC_CNTL_PAD20_HOLD_S 20 - -/* RTC_CNTL_PAD19_HOLD : R/W; bitpos: [19]; default: 0; - * set rtc_pad19_hold - */ - -#define RTC_CNTL_PAD19_HOLD (BIT(19)) -#define RTC_CNTL_PAD19_HOLD_M (RTC_CNTL_PAD19_HOLD_V << RTC_CNTL_PAD19_HOLD_S) -#define RTC_CNTL_PAD19_HOLD_V 0x00000001 -#define RTC_CNTL_PAD19_HOLD_S 19 - -/* RTC_CNTL_PDAC2_HOLD : R/W; bitpos: [18]; default: 0; - * set pdac2_hold - */ - -#define RTC_CNTL_PDAC2_HOLD (BIT(18)) -#define RTC_CNTL_PDAC2_HOLD_M (RTC_CNTL_PDAC2_HOLD_V << RTC_CNTL_PDAC2_HOLD_S) -#define RTC_CNTL_PDAC2_HOLD_V 0x00000001 -#define RTC_CNTL_PDAC2_HOLD_S 18 - -/* RTC_CNTL_PDAC1_HOLD : R/W; bitpos: [17]; default: 0; - * set pdac1_hold - */ - -#define RTC_CNTL_PDAC1_HOLD (BIT(17)) -#define RTC_CNTL_PDAC1_HOLD_M (RTC_CNTL_PDAC1_HOLD_V << RTC_CNTL_PDAC1_HOLD_S) -#define RTC_CNTL_PDAC1_HOLD_V 0x00000001 -#define RTC_CNTL_PDAC1_HOLD_S 17 - -/* RTC_CNTL_X32N_HOLD : R/W; bitpos: [16]; default: 0; - * set x32n_hold - */ - -#define RTC_CNTL_X32N_HOLD (BIT(16)) -#define RTC_CNTL_X32N_HOLD_M (RTC_CNTL_X32N_HOLD_V << RTC_CNTL_X32N_HOLD_S) -#define RTC_CNTL_X32N_HOLD_V 0x00000001 -#define RTC_CNTL_X32N_HOLD_S 16 - -/* RTC_CNTL_X32P_HOLD : R/W; bitpos: [15]; default: 0; - * Set x32p_hold - */ - -#define RTC_CNTL_X32P_HOLD (BIT(15)) -#define RTC_CNTL_X32P_HOLD_M (RTC_CNTL_X32P_HOLD_V << RTC_CNTL_X32P_HOLD_S) -#define RTC_CNTL_X32P_HOLD_V 0x00000001 -#define RTC_CNTL_X32P_HOLD_S 15 - -/* RTC_CNTL_TOUCH_PAD14_HOLD : R/W; bitpos: [14]; default: 0; - * set touch_pad14_hold - */ - -#define RTC_CNTL_TOUCH_PAD14_HOLD (BIT(14)) -#define RTC_CNTL_TOUCH_PAD14_HOLD_M (RTC_CNTL_TOUCH_PAD14_HOLD_V << RTC_CNTL_TOUCH_PAD14_HOLD_S) -#define RTC_CNTL_TOUCH_PAD14_HOLD_V 0x00000001 -#define RTC_CNTL_TOUCH_PAD14_HOLD_S 14 - -/* RTC_CNTL_TOUCH_PAD13_HOLD : R/W; bitpos: [13]; default: 0; - * set touch_pad13_hold - */ - -#define RTC_CNTL_TOUCH_PAD13_HOLD (BIT(13)) -#define RTC_CNTL_TOUCH_PAD13_HOLD_M (RTC_CNTL_TOUCH_PAD13_HOLD_V << RTC_CNTL_TOUCH_PAD13_HOLD_S) -#define RTC_CNTL_TOUCH_PAD13_HOLD_V 0x00000001 -#define RTC_CNTL_TOUCH_PAD13_HOLD_S 13 - -/* RTC_CNTL_TOUCH_PAD12_HOLD : R/W; bitpos: [12]; default: 0; - * set touch_pad12_hold - */ - -#define RTC_CNTL_TOUCH_PAD12_HOLD (BIT(12)) -#define RTC_CNTL_TOUCH_PAD12_HOLD_M (RTC_CNTL_TOUCH_PAD12_HOLD_V << RTC_CNTL_TOUCH_PAD12_HOLD_S) -#define RTC_CNTL_TOUCH_PAD12_HOLD_V 0x00000001 -#define RTC_CNTL_TOUCH_PAD12_HOLD_S 12 - -/* RTC_CNTL_TOUCH_PAD11_HOLD : R/W; bitpos: [11]; default: 0; - * set touch_pad11_hold - */ - -#define RTC_CNTL_TOUCH_PAD11_HOLD (BIT(11)) -#define RTC_CNTL_TOUCH_PAD11_HOLD_M (RTC_CNTL_TOUCH_PAD11_HOLD_V << RTC_CNTL_TOUCH_PAD11_HOLD_S) -#define RTC_CNTL_TOUCH_PAD11_HOLD_V 0x00000001 -#define RTC_CNTL_TOUCH_PAD11_HOLD_S 11 - -/* RTC_CNTL_TOUCH_PAD10_HOLD : R/W; bitpos: [10]; default: 0; - * set touch_pad10_hold - */ - -#define RTC_CNTL_TOUCH_PAD10_HOLD (BIT(10)) -#define RTC_CNTL_TOUCH_PAD10_HOLD_M (RTC_CNTL_TOUCH_PAD10_HOLD_V << RTC_CNTL_TOUCH_PAD10_HOLD_S) -#define RTC_CNTL_TOUCH_PAD10_HOLD_V 0x00000001 -#define RTC_CNTL_TOUCH_PAD10_HOLD_S 10 - -/* RTC_CNTL_TOUCH_PAD9_HOLD : R/W; bitpos: [9]; default: 0; - * set touch_pad9_hold - */ - -#define RTC_CNTL_TOUCH_PAD9_HOLD (BIT(9)) -#define RTC_CNTL_TOUCH_PAD9_HOLD_M (RTC_CNTL_TOUCH_PAD9_HOLD_V << RTC_CNTL_TOUCH_PAD9_HOLD_S) -#define RTC_CNTL_TOUCH_PAD9_HOLD_V 0x00000001 -#define RTC_CNTL_TOUCH_PAD9_HOLD_S 9 - -/* RTC_CNTL_TOUCH_PAD8_HOLD : R/W; bitpos: [8]; default: 0; - * set touch_pad8_hold - */ - -#define RTC_CNTL_TOUCH_PAD8_HOLD (BIT(8)) -#define RTC_CNTL_TOUCH_PAD8_HOLD_M (RTC_CNTL_TOUCH_PAD8_HOLD_V << RTC_CNTL_TOUCH_PAD8_HOLD_S) -#define RTC_CNTL_TOUCH_PAD8_HOLD_V 0x00000001 -#define RTC_CNTL_TOUCH_PAD8_HOLD_S 8 - -/* RTC_CNTL_TOUCH_PAD7_HOLD : R/W; bitpos: [7]; default: 0; - * set touch_pad7_hold - */ - -#define RTC_CNTL_TOUCH_PAD7_HOLD (BIT(7)) -#define RTC_CNTL_TOUCH_PAD7_HOLD_M (RTC_CNTL_TOUCH_PAD7_HOLD_V << RTC_CNTL_TOUCH_PAD7_HOLD_S) -#define RTC_CNTL_TOUCH_PAD7_HOLD_V 0x00000001 -#define RTC_CNTL_TOUCH_PAD7_HOLD_S 7 - -/* RTC_CNTL_TOUCH_PAD6_HOLD : R/W; bitpos: [6]; default: 0; - * set touch_pad6_hold - */ - -#define RTC_CNTL_TOUCH_PAD6_HOLD (BIT(6)) -#define RTC_CNTL_TOUCH_PAD6_HOLD_M (RTC_CNTL_TOUCH_PAD6_HOLD_V << RTC_CNTL_TOUCH_PAD6_HOLD_S) -#define RTC_CNTL_TOUCH_PAD6_HOLD_V 0x00000001 -#define RTC_CNTL_TOUCH_PAD6_HOLD_S 6 - -/* RTC_CNTL_TOUCH_PAD5_HOLD : R/W; bitpos: [5]; default: 0; - * set touch_pad5_hold - */ - -#define RTC_CNTL_TOUCH_PAD5_HOLD (BIT(5)) -#define RTC_CNTL_TOUCH_PAD5_HOLD_M (RTC_CNTL_TOUCH_PAD5_HOLD_V << RTC_CNTL_TOUCH_PAD5_HOLD_S) -#define RTC_CNTL_TOUCH_PAD5_HOLD_V 0x00000001 -#define RTC_CNTL_TOUCH_PAD5_HOLD_S 5 - -/* RTC_CNTL_TOUCH_PAD4_HOLD : R/W; bitpos: [4]; default: 0; - * set touch_pad4_hold - */ - -#define RTC_CNTL_TOUCH_PAD4_HOLD (BIT(4)) -#define RTC_CNTL_TOUCH_PAD4_HOLD_M (RTC_CNTL_TOUCH_PAD4_HOLD_V << RTC_CNTL_TOUCH_PAD4_HOLD_S) -#define RTC_CNTL_TOUCH_PAD4_HOLD_V 0x00000001 -#define RTC_CNTL_TOUCH_PAD4_HOLD_S 4 - -/* RTC_CNTL_TOUCH_PAD3_HOLD : R/W; bitpos: [3]; default: 0; - * set touch_pad3_hold - */ - -#define RTC_CNTL_TOUCH_PAD3_HOLD (BIT(3)) -#define RTC_CNTL_TOUCH_PAD3_HOLD_M (RTC_CNTL_TOUCH_PAD3_HOLD_V << RTC_CNTL_TOUCH_PAD3_HOLD_S) -#define RTC_CNTL_TOUCH_PAD3_HOLD_V 0x00000001 -#define RTC_CNTL_TOUCH_PAD3_HOLD_S 3 - -/* RTC_CNTL_TOUCH_PAD2_HOLD : R/W; bitpos: [2]; default: 0; - * set touch_pad2_hold - */ - -#define RTC_CNTL_TOUCH_PAD2_HOLD (BIT(2)) -#define RTC_CNTL_TOUCH_PAD2_HOLD_M (RTC_CNTL_TOUCH_PAD2_HOLD_V << RTC_CNTL_TOUCH_PAD2_HOLD_S) -#define RTC_CNTL_TOUCH_PAD2_HOLD_V 0x00000001 -#define RTC_CNTL_TOUCH_PAD2_HOLD_S 2 - -/* RTC_CNTL_TOUCH_PAD1_HOLD : R/W; bitpos: [1]; default: 0; - * set touch_pad1_hold - */ - -#define RTC_CNTL_TOUCH_PAD1_HOLD (BIT(1)) -#define RTC_CNTL_TOUCH_PAD1_HOLD_M (RTC_CNTL_TOUCH_PAD1_HOLD_V << RTC_CNTL_TOUCH_PAD1_HOLD_S) -#define RTC_CNTL_TOUCH_PAD1_HOLD_V 0x00000001 -#define RTC_CNTL_TOUCH_PAD1_HOLD_S 1 - -/* RTC_CNTL_TOUCH_PAD0_HOLD : R/W; bitpos: [0]; default: 0; - * set touch_pad0_hold - */ - -#define RTC_CNTL_TOUCH_PAD0_HOLD (BIT(0)) -#define RTC_CNTL_TOUCH_PAD0_HOLD_M (RTC_CNTL_TOUCH_PAD0_HOLD_V << RTC_CNTL_TOUCH_PAD0_HOLD_S) -#define RTC_CNTL_TOUCH_PAD0_HOLD_V 0x00000001 -#define RTC_CNTL_TOUCH_PAD0_HOLD_S 0 - -/* RTC_CNTL_DIG_PAD_HOLD_REG register - * configure digital pad hold register - */ - -#define RTC_CNTL_DIG_PAD_HOLD_REG (DR_REG_RTCCNTL_BASE + 0xd8) - -/* RTC_CNTL_DIG_PAD_HOLD : R/W; bitpos: [31:0]; default: 0; - * Hold GPIO21~GPIO45 base on bitmap - */ - -#define RTC_CNTL_DIG_PAD_HOLD 0xFFFFFFFF -#define RTC_CNTL_DIG_PAD_HOLD_M (RTC_CNTL_DIG_PAD_HOLD_V << RTC_CNTL_DIG_PAD_HOLD_S) -#define RTC_CNTL_DIG_PAD_HOLD_V 0xFFFFFFFF -#define RTC_CNTL_DIG_PAD_HOLD_S 0 - -/* RTC_CNTL_EXT_WAKEUP1_REG register - * configure EXT1 wakeup register - */ - -#define RTC_CNTL_EXT_WAKEUP1_REG (DR_REG_RTCCNTL_BASE + 0xdc) - -/* RTC_CNTL_EXT_WAKEUP1_STATUS_CLR : WO; bitpos: [22]; default: 0; - * clear ext wakeup1 status - */ - -#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR (BIT(22)) -#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_M (RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_V << RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_S) -#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_V 0x00000001 -#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_S 22 - -/* RTC_CNTL_EXT_WAKEUP1_SEL : R/W; bitpos: [21:0]; default: 0; - * Bitmap to select RTC pads for ext wakeup1 - */ - -#define RTC_CNTL_EXT_WAKEUP1_SEL 0x003FFFFF -#define RTC_CNTL_EXT_WAKEUP1_SEL_M (RTC_CNTL_EXT_WAKEUP1_SEL_V << RTC_CNTL_EXT_WAKEUP1_SEL_S) -#define RTC_CNTL_EXT_WAKEUP1_SEL_V 0x003FFFFF -#define RTC_CNTL_EXT_WAKEUP1_SEL_S 0 - -/* RTC_CNTL_EXT_WAKEUP1_STATUS_REG register - * EXT1 wakeup source register - */ - -#define RTC_CNTL_EXT_WAKEUP1_STATUS_REG (DR_REG_RTCCNTL_BASE + 0xe0) - -/* RTC_CNTL_EXT_WAKEUP1_STATUS : RO; bitpos: [21:0]; default: 0; - * ext wakeup1 status - */ - -#define RTC_CNTL_EXT_WAKEUP1_STATUS 0x003FFFFF -#define RTC_CNTL_EXT_WAKEUP1_STATUS_M (RTC_CNTL_EXT_WAKEUP1_STATUS_V << RTC_CNTL_EXT_WAKEUP1_STATUS_S) -#define RTC_CNTL_EXT_WAKEUP1_STATUS_V 0x003FFFFF -#define RTC_CNTL_EXT_WAKEUP1_STATUS_S 0 - -/* RTC_CNTL_BROWN_OUT_REG register - * configure brownout register - */ - -#define RTC_CNTL_BROWN_OUT_REG (DR_REG_RTCCNTL_BASE + 0xe4) - -/* RTC_CNTL_BROWN_OUT_DET : RO; bitpos: [31]; default: 0; - * status of brown detcet signal - */ - -#define RTC_CNTL_BROWN_OUT_DET (BIT(31)) -#define RTC_CNTL_BROWN_OUT_DET_M (RTC_CNTL_BROWN_OUT_DET_V << RTC_CNTL_BROWN_OUT_DET_S) -#define RTC_CNTL_BROWN_OUT_DET_V 0x00000001 -#define RTC_CNTL_BROWN_OUT_DET_S 31 - -/* RTC_CNTL_BROWN_OUT_ENA : R/W; bitpos: [30]; default: 0; - * enable brown out - */ - -#define RTC_CNTL_BROWN_OUT_ENA (BIT(30)) -#define RTC_CNTL_BROWN_OUT_ENA_M (RTC_CNTL_BROWN_OUT_ENA_V << RTC_CNTL_BROWN_OUT_ENA_S) -#define RTC_CNTL_BROWN_OUT_ENA_V 0x00000001 -#define RTC_CNTL_BROWN_OUT_ENA_S 30 - -/* RTC_CNTL_BROWN_OUT_CNT_CLR : WO; bitpos: [29]; default: 0; - * clear brown out counter - */ - -#define RTC_CNTL_BROWN_OUT_CNT_CLR (BIT(29)) -#define RTC_CNTL_BROWN_OUT_CNT_CLR_M (RTC_CNTL_BROWN_OUT_CNT_CLR_V << RTC_CNTL_BROWN_OUT_CNT_CLR_S) -#define RTC_CNTL_BROWN_OUT_CNT_CLR_V 0x00000001 -#define RTC_CNTL_BROWN_OUT_CNT_CLR_S 29 - -/* RTC_CNTL_BROWN_OUT_RST_SEL : R/W; bitpos: [27]; default: 0; - * 1: chip reset 0: sys_reset - */ - -#define RTC_CNTL_BROWN_OUT_RST_SEL (BIT(27)) -#define RTC_CNTL_BROWN_OUT_RST_SEL_M (RTC_CNTL_BROWN_OUT_RST_SEL_V << RTC_CNTL_BROWN_OUT_RST_SEL_S) -#define RTC_CNTL_BROWN_OUT_RST_SEL_V 0x00000001 -#define RTC_CNTL_BROWN_OUT_RST_SEL_S 27 - -/* RTC_CNTL_BROWN_OUT_RST_ENA : R/W; bitpos: [26]; default: 0; - * enable brown out reset - */ - -#define RTC_CNTL_BROWN_OUT_RST_ENA (BIT(26)) -#define RTC_CNTL_BROWN_OUT_RST_ENA_M (RTC_CNTL_BROWN_OUT_RST_ENA_V << RTC_CNTL_BROWN_OUT_RST_ENA_S) -#define RTC_CNTL_BROWN_OUT_RST_ENA_V 0x00000001 -#define RTC_CNTL_BROWN_OUT_RST_ENA_S 26 - -/* RTC_CNTL_BROWN_OUT_RST_WAIT : R/W; bitpos: [25:16]; default: 1023; - * brown out reset wait cycles - */ - -#define RTC_CNTL_BROWN_OUT_RST_WAIT 0x000003FF -#define RTC_CNTL_BROWN_OUT_RST_WAIT_M (RTC_CNTL_BROWN_OUT_RST_WAIT_V << RTC_CNTL_BROWN_OUT_RST_WAIT_S) -#define RTC_CNTL_BROWN_OUT_RST_WAIT_V 0x000003FF -#define RTC_CNTL_BROWN_OUT_RST_WAIT_S 16 - -/* RTC_CNTL_BROWN_OUT_PD_RF_ENA : R/W; bitpos: [15]; default: 0; - * enable power down RF when brown out happens - */ - -#define RTC_CNTL_BROWN_OUT_PD_RF_ENA (BIT(15)) -#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_M (RTC_CNTL_BROWN_OUT_PD_RF_ENA_V << RTC_CNTL_BROWN_OUT_PD_RF_ENA_S) -#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_V 0x00000001 -#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_S 15 - -/* RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA : R/W; bitpos: [14]; default: 0; - * enable close flash when brown out happens - */ - -#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA (BIT(14)) -#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_M (RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_V << RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_S) -#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_V 0x00000001 -#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_S 14 - -/* RTC_CNTL_BROWN_OUT_INT_WAIT : R/W; bitpos: [13:4]; default: 767; - * brown out interrupt wait cycles - */ - -#define RTC_CNTL_BROWN_OUT_INT_WAIT 0x000003FF -#define RTC_CNTL_BROWN_OUT_INT_WAIT_M (RTC_CNTL_BROWN_OUT_INT_WAIT_V << RTC_CNTL_BROWN_OUT_INT_WAIT_S) -#define RTC_CNTL_BROWN_OUT_INT_WAIT_V 0x000003FF -#define RTC_CNTL_BROWN_OUT_INT_WAIT_S 4 - -/* RTC_CNTL_BROWN_OUT2_ENA : R/W; bitpos: [0]; default: 1; - * enable brown_out2 to start chip reset - */ - -#define RTC_CNTL_BROWN_OUT2_ENA (BIT(0)) -#define RTC_CNTL_BROWN_OUT2_ENA_M (RTC_CNTL_BROWN_OUT2_ENA_V << RTC_CNTL_BROWN_OUT2_ENA_S) -#define RTC_CNTL_BROWN_OUT2_ENA_V 0x00000001 -#define RTC_CNTL_BROWN_OUT2_ENA_S 0 - -/* RTC_CNTL_TIME_LOW1_REG register - * RTC timer1 low 32 bits - */ - -#define RTC_CNTL_TIME_LOW1_REG (DR_REG_RTCCNTL_BASE + 0xe8) - -/* RTC_CNTL_TIMER_VALUE1_LOW : RO; bitpos: [31:0]; default: 0; - * RTC timer low 32 bits - */ - -#define RTC_CNTL_TIMER_VALUE1_LOW 0xFFFFFFFF -#define RTC_CNTL_TIMER_VALUE1_LOW_M (RTC_CNTL_TIMER_VALUE1_LOW_V << RTC_CNTL_TIMER_VALUE1_LOW_S) -#define RTC_CNTL_TIMER_VALUE1_LOW_V 0xFFFFFFFF -#define RTC_CNTL_TIMER_VALUE1_LOW_S 0 - -/* RTC_CNTL_TIME_HIGH1_REG register - * RTC timer1 high 16 bits - */ - -#define RTC_CNTL_TIME_HIGH1_REG (DR_REG_RTCCNTL_BASE + 0xec) - -/* RTC_CNTL_TIMER_VALUE1_HIGH : RO; bitpos: [15:0]; default: 0; - * RTC timer high 16 bits - */ - -#define RTC_CNTL_TIMER_VALUE1_HIGH 0x0000FFFF -#define RTC_CNTL_TIMER_VALUE1_HIGH_M (RTC_CNTL_TIMER_VALUE1_HIGH_V << RTC_CNTL_TIMER_VALUE1_HIGH_S) -#define RTC_CNTL_TIMER_VALUE1_HIGH_V 0x0000FFFF -#define RTC_CNTL_TIMER_VALUE1_HIGH_S 0 - -/* RTC_CNTL_XTAL32K_CLK_FACTOR_REG register - * configure xtal32k backup fatcor register - */ - -#define RTC_CNTL_XTAL32K_CLK_FACTOR_REG (DR_REG_RTCCNTL_BASE + 0xf0) - -/* RTC_CNTL_XTAL32K_CLK_FACTOR : R/W; bitpos: [31:0]; default: 0; - * xtal 32k watch dog backup clock factor - */ - -#define RTC_CNTL_XTAL32K_CLK_FACTOR 0xFFFFFFFF -#define RTC_CNTL_XTAL32K_CLK_FACTOR_M (RTC_CNTL_XTAL32K_CLK_FACTOR_V << RTC_CNTL_XTAL32K_CLK_FACTOR_S) -#define RTC_CNTL_XTAL32K_CLK_FACTOR_V 0xFFFFFFFF -#define RTC_CNTL_XTAL32K_CLK_FACTOR_S 0 - -/* RTC_CNTL_XTAL32K_CONF_REG register - * configure xtal32k register - */ - -#define RTC_CNTL_XTAL32K_CONF_REG (DR_REG_RTCCNTL_BASE + 0xf4) - -/* RTC_CNTL_XTAL32K_STABLE_THRES : R/W; bitpos: [31:28]; default: 0; - * if restarted xtal32k period is smaller than this it is regarded as stable - */ - -#define RTC_CNTL_XTAL32K_STABLE_THRES 0x0000000F -#define RTC_CNTL_XTAL32K_STABLE_THRES_M (RTC_CNTL_XTAL32K_STABLE_THRES_V << RTC_CNTL_XTAL32K_STABLE_THRES_S) -#define RTC_CNTL_XTAL32K_STABLE_THRES_V 0x0000000F -#define RTC_CNTL_XTAL32K_STABLE_THRES_S 28 - -/* RTC_CNTL_XTAL32K_WDT_TIMEOUT : R/W; bitpos: [27:20]; default: 255; - * If no clock detected for this amount of time 32k is regarded as dead - */ - -#define RTC_CNTL_XTAL32K_WDT_TIMEOUT 0x000000FF -#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_M (RTC_CNTL_XTAL32K_WDT_TIMEOUT_V << RTC_CNTL_XTAL32K_WDT_TIMEOUT_S) -#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_V 0x000000FF -#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_S 20 - -/* RTC_CNTL_XTAL32K_RESTART_WAIT : R/W; bitpos: [19:4]; default: 0; - * cycles to wait to repower on xtal 32k - */ - -#define RTC_CNTL_XTAL32K_RESTART_WAIT 0x0000FFFF -#define RTC_CNTL_XTAL32K_RESTART_WAIT_M (RTC_CNTL_XTAL32K_RESTART_WAIT_V << RTC_CNTL_XTAL32K_RESTART_WAIT_S) -#define RTC_CNTL_XTAL32K_RESTART_WAIT_V 0x0000FFFF -#define RTC_CNTL_XTAL32K_RESTART_WAIT_S 4 - -/* RTC_CNTL_XTAL32K_RETURN_WAIT : R/W; bitpos: [3:0]; default: 0; - * cycles to wait to return normal xtal 32k - */ - -#define RTC_CNTL_XTAL32K_RETURN_WAIT 0x0000000F -#define RTC_CNTL_XTAL32K_RETURN_WAIT_M (RTC_CNTL_XTAL32K_RETURN_WAIT_V << RTC_CNTL_XTAL32K_RETURN_WAIT_S) -#define RTC_CNTL_XTAL32K_RETURN_WAIT_V 0x0000000F -#define RTC_CNTL_XTAL32K_RETURN_WAIT_S 0 - -/* RTC_CNTL_ULP_CP_TIMER_REG register - * Description - */ - -#define RTC_CNTL_ULP_CP_TIMER_REG (DR_REG_RTCCNTL_BASE + 0xf8) - -/* RTC_CNTL_ULP_CP_SLP_TIMER_EN : R/W; bitpos: [31]; default: 0; - * ULP-coprocessor timer enable bit - */ - -#define RTC_CNTL_ULP_CP_SLP_TIMER_EN (BIT(31)) -#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_M (RTC_CNTL_ULP_CP_SLP_TIMER_EN_V << RTC_CNTL_ULP_CP_SLP_TIMER_EN_S) -#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_V 0x00000001 -#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_S 31 - -/* RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR : WO; bitpos: [30]; default: 0; - * ULP-coprocessor wakeup by GPIO state clear - */ - -#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR (BIT(30)) -#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_M (RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_V << RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_S) -#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_V 0x00000001 -#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_S 30 - -/* RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA : R/W; bitpos: [29]; default: 0; - * ULP-coprocessor wakeup by GPIO enable - */ - -#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA (BIT(29)) -#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_M (RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_V << RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_S) -#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_V 0x00000001 -#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_S 29 - -/* RTC_CNTL_ULP_CP_PC_INIT : R/W; bitpos: [10:0]; default: 0; - * ULP-coprocessor PC initial address - */ - -#define RTC_CNTL_ULP_CP_PC_INIT 0x000007ff -#define RTC_CNTL_ULP_CP_PC_INIT_M (RTC_CNTL_ULP_CP_PC_INIT_V << RTC_CNTL_ULP_CP_PC_INIT_S) -#define RTC_CNTL_ULP_CP_PC_INIT_V 0x000007ff -#define RTC_CNTL_ULP_CP_PC_INIT_S 0 - -/* RTC_CNTL_ULP_CP_CTRL_REG register - * Description - */ - -#define RTC_CNTL_ULP_CP_CTRL_REG (DR_REG_RTCCNTL_BASE + 0xfc) - -/* RTC_CNTL_ULP_CP_START_TOP : R/W; bitpos: [31]; default: 0; - * Write 1 to start ULP-coprocessor - */ - -#define RTC_CNTL_ULP_CP_START_TOP (BIT(31)) -#define RTC_CNTL_ULP_CP_START_TOP_M (RTC_CNTL_ULP_CP_START_TOP_V << RTC_CNTL_ULP_CP_START_TOP_S) -#define RTC_CNTL_ULP_CP_START_TOP_V 0x00000001 -#define RTC_CNTL_ULP_CP_START_TOP_S 31 - -/* RTC_CNTL_ULP_CP_FORCE_START_TOP : R/W; bitpos: [30]; default: 0; - * 1: ULP-coprocessor is started by SW - */ - -#define RTC_CNTL_ULP_CP_FORCE_START_TOP (BIT(30)) -#define RTC_CNTL_ULP_CP_FORCE_START_TOP_M (RTC_CNTL_ULP_CP_FORCE_START_TOP_V << RTC_CNTL_ULP_CP_FORCE_START_TOP_S) -#define RTC_CNTL_ULP_CP_FORCE_START_TOP_V 0x00000001 -#define RTC_CNTL_ULP_CP_FORCE_START_TOP_S 30 - -/* RTC_CNTL_ULP_CP_RESET : R/W; bitpos: [29]; default: 0; - * ulp coprocessor clk software reset - */ - -#define RTC_CNTL_ULP_CP_RESET (BIT(29)) -#define RTC_CNTL_ULP_CP_RESET_M (RTC_CNTL_ULP_CP_RESET_V << RTC_CNTL_ULP_CP_RESET_S) -#define RTC_CNTL_ULP_CP_RESET_V 0x00000001 -#define RTC_CNTL_ULP_CP_RESET_S 29 - -/* RTC_CNTL_ULP_CP_CLK_FO : R/W; bitpos: [28]; default: 0; - * ulp coprocessor clk force on - */ - -#define RTC_CNTL_ULP_CP_CLK_FO (BIT(28)) -#define RTC_CNTL_ULP_CP_CLK_FO_M (RTC_CNTL_ULP_CP_CLK_FO_V << RTC_CNTL_ULP_CP_CLK_FO_S) -#define RTC_CNTL_ULP_CP_CLK_FO_V 0x00000001 -#define RTC_CNTL_ULP_CP_CLK_FO_S 28 - -/* RTC_CNTL_ULP_CP_MEM_OFFST_CLR : WO; bitpos: [22]; default: 0; */ - -#define RTC_CNTL_ULP_CP_MEM_OFFST_CLR (BIT(22)) -#define RTC_CNTL_ULP_CP_MEM_OFFST_CLR_M (RTC_CNTL_ULP_CP_MEM_OFFST_CLR_V << RTC_CNTL_ULP_CP_MEM_OFFST_CLR_S) -#define RTC_CNTL_ULP_CP_MEM_OFFST_CLR_V 0x00000001 -#define RTC_CNTL_ULP_CP_MEM_OFFST_CLR_S 22 - -/* RTC_CNTL_ULP_CP_MEM_ADDR_SIZE : R/W; bitpos: [21:11]; default: 512; */ - -#define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE 0x000007ff -#define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_M (RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_V << RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_S) -#define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_V 0x000007ff -#define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_S 11 - -/* RTC_CNTL_ULP_CP_MEM_ADDR_INIT : R/W; bitpos: [10:0]; default: 512; */ - -#define RTC_CNTL_ULP_CP_MEM_ADDR_INIT 0x000007ff -#define RTC_CNTL_ULP_CP_MEM_ADDR_INIT_M (RTC_CNTL_ULP_CP_MEM_ADDR_INIT_V << RTC_CNTL_ULP_CP_MEM_ADDR_INIT_S) -#define RTC_CNTL_ULP_CP_MEM_ADDR_INIT_V 0x000007ff -#define RTC_CNTL_ULP_CP_MEM_ADDR_INIT_S 0 - -/* RTC_CNTL_COCPU_CTRL_REG register - * Description - */ - -#define RTC_CNTL_COCPU_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x100) - -/* RTC_CNTL_COCPU_SW_INT_TRIGGER : WO; bitpos: [26]; default: 0; - * trigger cocpu register interrupt - */ - -#define RTC_CNTL_COCPU_SW_INT_TRIGGER (BIT(26)) -#define RTC_CNTL_COCPU_SW_INT_TRIGGER_M (RTC_CNTL_COCPU_SW_INT_TRIGGER_V << RTC_CNTL_COCPU_SW_INT_TRIGGER_S) -#define RTC_CNTL_COCPU_SW_INT_TRIGGER_V 0x00000001 -#define RTC_CNTL_COCPU_SW_INT_TRIGGER_S 26 - -/* RTC_CNTL_COCPU_DONE : R/W; bitpos: [25]; default: 0; - * done signal used by riscv to control timer. - */ - -#define RTC_CNTL_COCPU_DONE (BIT(25)) -#define RTC_CNTL_COCPU_DONE_M (RTC_CNTL_COCPU_DONE_V << RTC_CNTL_COCPU_DONE_S) -#define RTC_CNTL_COCPU_DONE_V 0x00000001 -#define RTC_CNTL_COCPU_DONE_S 25 - -/* RTC_CNTL_COCPU_DONE_FORCE : R/W; bitpos: [24]; default: 0; - * 1: select riscv done 0: select ulp done - */ - -#define RTC_CNTL_COCPU_DONE_FORCE (BIT(24)) -#define RTC_CNTL_COCPU_DONE_FORCE_M (RTC_CNTL_COCPU_DONE_FORCE_V << RTC_CNTL_COCPU_DONE_FORCE_S) -#define RTC_CNTL_COCPU_DONE_FORCE_V 0x00000001 -#define RTC_CNTL_COCPU_DONE_FORCE_S 24 - -/* RTC_CNTL_COCPU_SEL : R/W; bitpos: [23]; default: 1; - * 1: old ULP 0: new riscV - */ - -#define RTC_CNTL_COCPU_SEL (BIT(23)) -#define RTC_CNTL_COCPU_SEL_M (RTC_CNTL_COCPU_SEL_V << RTC_CNTL_COCPU_SEL_S) -#define RTC_CNTL_COCPU_SEL_V 0x00000001 -#define RTC_CNTL_COCPU_SEL_S 23 - -/* RTC_CNTL_COCPU_SHUT_RESET_EN : R/W; bitpos: [22]; default: 0; - * to reset cocpu - */ - -#define RTC_CNTL_COCPU_SHUT_RESET_EN (BIT(22)) -#define RTC_CNTL_COCPU_SHUT_RESET_EN_M (RTC_CNTL_COCPU_SHUT_RESET_EN_V << RTC_CNTL_COCPU_SHUT_RESET_EN_S) -#define RTC_CNTL_COCPU_SHUT_RESET_EN_V 0x00000001 -#define RTC_CNTL_COCPU_SHUT_RESET_EN_S 22 - -/* RTC_CNTL_COCPU_SHUT_2_CLK_DIS : R/W; bitpos: [21:14]; default: 40; - * time from shut cocpu to disable clk - */ - -#define RTC_CNTL_COCPU_SHUT_2_CLK_DIS 0x000000ff -#define RTC_CNTL_COCPU_SHUT_2_CLK_DIS_M (RTC_CNTL_COCPU_SHUT_2_CLK_DIS_V << RTC_CNTL_COCPU_SHUT_2_CLK_DIS_S) -#define RTC_CNTL_COCPU_SHUT_2_CLK_DIS_V 0x000000ff -#define RTC_CNTL_COCPU_SHUT_2_CLK_DIS_S 14 - -/* RTC_CNTL_COCPU_SHUT : R/W; bitpos: [13]; default: 0; - * to shut cocpu - */ - -#define RTC_CNTL_COCPU_SHUT (BIT(13)) -#define RTC_CNTL_COCPU_SHUT_M (RTC_CNTL_COCPU_SHUT_V << RTC_CNTL_COCPU_SHUT_S) -#define RTC_CNTL_COCPU_SHUT_V 0x00000001 -#define RTC_CNTL_COCPU_SHUT_S 13 - -/* RTC_CNTL_COCPU_START_2_INTR_EN : R/W; bitpos: [12:7]; default: 16; - * time from start cocpu to give start interrupt - */ - -#define RTC_CNTL_COCPU_START_2_INTR_EN 0x0000003f -#define RTC_CNTL_COCPU_START_2_INTR_EN_M (RTC_CNTL_COCPU_START_2_INTR_EN_V << RTC_CNTL_COCPU_START_2_INTR_EN_S) -#define RTC_CNTL_COCPU_START_2_INTR_EN_V 0x0000003f -#define RTC_CNTL_COCPU_START_2_INTR_EN_S 7 - -/* RTC_CNTL_COCPU_START_2_RESET_DIS : R/W; bitpos: [6:1]; default: 8; - * time from start cocpu to pull down reset - */ - -#define RTC_CNTL_COCPU_START_2_RESET_DIS 0x0000003f -#define RTC_CNTL_COCPU_START_2_RESET_DIS_M (RTC_CNTL_COCPU_START_2_RESET_DIS_V << RTC_CNTL_COCPU_START_2_RESET_DIS_S) -#define RTC_CNTL_COCPU_START_2_RESET_DIS_V 0x0000003f -#define RTC_CNTL_COCPU_START_2_RESET_DIS_S 1 - -/* RTC_CNTL_COCPU_CLK_FO : R/W; bitpos: [0]; default: 0; - * cocpu clk force on - */ - -#define RTC_CNTL_COCPU_CLK_FO (BIT(0)) -#define RTC_CNTL_COCPU_CLK_FO_M (RTC_CNTL_COCPU_CLK_FO_V << RTC_CNTL_COCPU_CLK_FO_S) -#define RTC_CNTL_COCPU_CLK_FO_V 0x00000001 -#define RTC_CNTL_COCPU_CLK_FO_S 0 - -/* RTC_CNTL_TOUCH_CTRL1_REG register - * Description - */ - -#define RTC_CNTL_TOUCH_CTRL1_REG (DR_REG_RTCCNTL_BASE + 0x104) - -/* RTC_CNTL_TOUCH_MEAS_NUM : R/W; bitpos: [31:16]; default: 4096; - * the meas length (in 8MHz) - */ - -#define RTC_CNTL_TOUCH_MEAS_NUM 0x0000ffff -#define RTC_CNTL_TOUCH_MEAS_NUM_M (RTC_CNTL_TOUCH_MEAS_NUM_V << RTC_CNTL_TOUCH_MEAS_NUM_S) -#define RTC_CNTL_TOUCH_MEAS_NUM_V 0x0000ffff -#define RTC_CNTL_TOUCH_MEAS_NUM_S 16 - -/* RTC_CNTL_TOUCH_SLEEP_CYCLES : R/W; bitpos: [15:0]; default: 256; - * sleep cycles for timer - */ - -#define RTC_CNTL_TOUCH_SLEEP_CYCLES 0x0000ffff -#define RTC_CNTL_TOUCH_SLEEP_CYCLES_M (RTC_CNTL_TOUCH_SLEEP_CYCLES_V << RTC_CNTL_TOUCH_SLEEP_CYCLES_S) -#define RTC_CNTL_TOUCH_SLEEP_CYCLES_V 0x0000ffff -#define RTC_CNTL_TOUCH_SLEEP_CYCLES_S 0 - -/* RTC_CNTL_TOUCH_CTRL2_REG register - * Description - */ - -#define RTC_CNTL_TOUCH_CTRL2_REG (DR_REG_RTCCNTL_BASE + 0x108) - -/* RTC_CNTL_TOUCH_CLKGATE_EN : R/W; bitpos: [31]; default: 0; - * touch clock enable - */ - -#define RTC_CNTL_TOUCH_CLKGATE_EN (BIT(31)) -#define RTC_CNTL_TOUCH_CLKGATE_EN_M (RTC_CNTL_TOUCH_CLKGATE_EN_V << RTC_CNTL_TOUCH_CLKGATE_EN_S) -#define RTC_CNTL_TOUCH_CLKGATE_EN_V 0x00000001 -#define RTC_CNTL_TOUCH_CLKGATE_EN_S 31 - -/* RTC_CNTL_TOUCH_CLK_FO : R/W; bitpos: [30]; default: 0; - * touch clock force on - */ - -#define RTC_CNTL_TOUCH_CLK_FO (BIT(30)) -#define RTC_CNTL_TOUCH_CLK_FO_M (RTC_CNTL_TOUCH_CLK_FO_V << RTC_CNTL_TOUCH_CLK_FO_S) -#define RTC_CNTL_TOUCH_CLK_FO_V 0x00000001 -#define RTC_CNTL_TOUCH_CLK_FO_S 30 - -/* RTC_CNTL_TOUCH_RESET : R/W; bitpos: [29]; default: 0; - * reset upgrade touch - */ - -#define RTC_CNTL_TOUCH_RESET (BIT(29)) -#define RTC_CNTL_TOUCH_RESET_M (RTC_CNTL_TOUCH_RESET_V << RTC_CNTL_TOUCH_RESET_S) -#define RTC_CNTL_TOUCH_RESET_V 0x00000001 -#define RTC_CNTL_TOUCH_RESET_S 29 - -/* RTC_CNTL_TOUCH_TIMER_FORCE_DONE : R/W; bitpos: [28:27]; default: 0; - * force touch timer done - */ - -#define RTC_CNTL_TOUCH_TIMER_FORCE_DONE 0x00000003 -#define RTC_CNTL_TOUCH_TIMER_FORCE_DONE_M (RTC_CNTL_TOUCH_TIMER_FORCE_DONE_V << RTC_CNTL_TOUCH_TIMER_FORCE_DONE_S) -#define RTC_CNTL_TOUCH_TIMER_FORCE_DONE_V 0x00000003 -#define RTC_CNTL_TOUCH_TIMER_FORCE_DONE_S 27 - -/* RTC_CNTL_TOUCH_SLP_CYC_DIV : R/W; bitpos: [26:25]; default: 0; - * when a touch pad is active, sleep cycle could be divided by this number - */ - -#define RTC_CNTL_TOUCH_SLP_CYC_DIV 0x00000003 -#define RTC_CNTL_TOUCH_SLP_CYC_DIV_M (RTC_CNTL_TOUCH_SLP_CYC_DIV_V << RTC_CNTL_TOUCH_SLP_CYC_DIV_S) -#define RTC_CNTL_TOUCH_SLP_CYC_DIV_V 0x00000003 -#define RTC_CNTL_TOUCH_SLP_CYC_DIV_S 25 - -/* RTC_CNTL_TOUCH_XPD_WAIT : R/W; bitpos: [24:17]; default: 4; - * the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD - */ - -#define RTC_CNTL_TOUCH_XPD_WAIT 0x000000ff -#define RTC_CNTL_TOUCH_XPD_WAIT_M (RTC_CNTL_TOUCH_XPD_WAIT_V << RTC_CNTL_TOUCH_XPD_WAIT_S) -#define RTC_CNTL_TOUCH_XPD_WAIT_V 0x000000ff -#define RTC_CNTL_TOUCH_XPD_WAIT_S 17 - -/* RTC_CNTL_TOUCH_START_FORCE : R/W; bitpos: [16]; default: 0; - * 1: to start touch fsm by SW - */ - -#define RTC_CNTL_TOUCH_START_FORCE (BIT(16)) -#define RTC_CNTL_TOUCH_START_FORCE_M (RTC_CNTL_TOUCH_START_FORCE_V << RTC_CNTL_TOUCH_START_FORCE_S) -#define RTC_CNTL_TOUCH_START_FORCE_V 0x00000001 -#define RTC_CNTL_TOUCH_START_FORCE_S 16 - -/* RTC_CNTL_TOUCH_START_EN : R/W; bitpos: [15]; default: 0; - * 1: start touch fsm - */ - -#define RTC_CNTL_TOUCH_START_EN (BIT(15)) -#define RTC_CNTL_TOUCH_START_EN_M (RTC_CNTL_TOUCH_START_EN_V << RTC_CNTL_TOUCH_START_EN_S) -#define RTC_CNTL_TOUCH_START_EN_V 0x00000001 -#define RTC_CNTL_TOUCH_START_EN_S 15 - -/* RTC_CNTL_TOUCH_START_FSM_EN : R/W; bitpos: [14]; default: 1; - * 1: TOUCH_START & TOUCH_XPD is controlled by touch fsm - */ - -#define RTC_CNTL_TOUCH_START_FSM_EN (BIT(14)) -#define RTC_CNTL_TOUCH_START_FSM_EN_M (RTC_CNTL_TOUCH_START_FSM_EN_V << RTC_CNTL_TOUCH_START_FSM_EN_S) -#define RTC_CNTL_TOUCH_START_FSM_EN_V 0x00000001 -#define RTC_CNTL_TOUCH_START_FSM_EN_S 14 - -/* RTC_CNTL_TOUCH_SLP_TIMER_EN : R/W; bitpos: [13]; default: 0; - * touch timer enable bit - */ - -#define RTC_CNTL_TOUCH_SLP_TIMER_EN (BIT(13)) -#define RTC_CNTL_TOUCH_SLP_TIMER_EN_M (RTC_CNTL_TOUCH_SLP_TIMER_EN_V << RTC_CNTL_TOUCH_SLP_TIMER_EN_S) -#define RTC_CNTL_TOUCH_SLP_TIMER_EN_V 0x00000001 -#define RTC_CNTL_TOUCH_SLP_TIMER_EN_S 13 - -/* RTC_CNTL_TOUCH_DBIAS : R/W; bitpos: [12]; default: 0; - * 1:use self bias 0:use bandgap bias - */ - -#define RTC_CNTL_TOUCH_DBIAS (BIT(12)) -#define RTC_CNTL_TOUCH_DBIAS_M (RTC_CNTL_TOUCH_DBIAS_V << RTC_CNTL_TOUCH_DBIAS_S) -#define RTC_CNTL_TOUCH_DBIAS_V 0x00000001 -#define RTC_CNTL_TOUCH_DBIAS_S 12 - -/* RTC_CNTL_TOUCH_REFC : R/W; bitpos: [11:9]; default: 0; - * TOUCH pad0 reference cap - */ - -#define RTC_CNTL_TOUCH_REFC 0x00000007 -#define RTC_CNTL_TOUCH_REFC_M (RTC_CNTL_TOUCH_REFC_V << RTC_CNTL_TOUCH_REFC_S) -#define RTC_CNTL_TOUCH_REFC_V 0x00000007 -#define RTC_CNTL_TOUCH_REFC_S 9 - -/* RTC_CNTL_TOUCH_XPD_BIAS : R/W; bitpos: [8]; default: 0; - * TOUCH_XPD_BIAS - */ - -#define RTC_CNTL_TOUCH_XPD_BIAS (BIT(8)) -#define RTC_CNTL_TOUCH_XPD_BIAS_M (RTC_CNTL_TOUCH_XPD_BIAS_V << RTC_CNTL_TOUCH_XPD_BIAS_S) -#define RTC_CNTL_TOUCH_XPD_BIAS_V 0x00000001 -#define RTC_CNTL_TOUCH_XPD_BIAS_S 8 - -/* RTC_CNTL_TOUCH_DREFH : R/W; bitpos: [7:6]; default: 3; - * TOUCH_DREFH - */ - -#define RTC_CNTL_TOUCH_DREFH 0x00000003 -#define RTC_CNTL_TOUCH_DREFH_M (RTC_CNTL_TOUCH_DREFH_V << RTC_CNTL_TOUCH_DREFH_S) -#define RTC_CNTL_TOUCH_DREFH_V 0x00000003 -#define RTC_CNTL_TOUCH_DREFH_S 6 - -/* RTC_CNTL_TOUCH_DREFL : R/W; bitpos: [5:4]; default: 0; - * TOUCH_DREFL - */ - -#define RTC_CNTL_TOUCH_DREFL 0x00000003 -#define RTC_CNTL_TOUCH_DREFL_M (RTC_CNTL_TOUCH_DREFL_V << RTC_CNTL_TOUCH_DREFL_S) -#define RTC_CNTL_TOUCH_DREFL_V 0x00000003 -#define RTC_CNTL_TOUCH_DREFL_S 4 - -/* RTC_CNTL_TOUCH_DRANGE : R/W; bitpos: [3:2]; default: 3; - * TOUCH_DRANGE - */ - -#define RTC_CNTL_TOUCH_DRANGE 0x00000003 -#define RTC_CNTL_TOUCH_DRANGE_M (RTC_CNTL_TOUCH_DRANGE_V << RTC_CNTL_TOUCH_DRANGE_S) -#define RTC_CNTL_TOUCH_DRANGE_V 0x00000003 -#define RTC_CNTL_TOUCH_DRANGE_S 2 - -/* RTC_CNTL_TOUCH_SCAN_CTRL_REG register - * Description - */ - -#define RTC_CNTL_TOUCH_SCAN_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x10c) - -/* RTC_CNTL_TOUCH_OUT_RING : R/W; bitpos: [31:28]; default: 15; - * select out ring pad - */ - -#define RTC_CNTL_TOUCH_OUT_RING 0x0000000f -#define RTC_CNTL_TOUCH_OUT_RING_M (RTC_CNTL_TOUCH_OUT_RING_V << RTC_CNTL_TOUCH_OUT_RING_S) -#define RTC_CNTL_TOUCH_OUT_RING_V 0x0000000f -#define RTC_CNTL_TOUCH_OUT_RING_S 28 - -/* RTC_CNTL_TOUCH_BUFDRV : R/W; bitpos: [27:25]; default: 0; - * touch7 buffer driver strength - */ - -#define RTC_CNTL_TOUCH_BUFDRV 0x00000007 -#define RTC_CNTL_TOUCH_BUFDRV_M (RTC_CNTL_TOUCH_BUFDRV_V << RTC_CNTL_TOUCH_BUFDRV_S) -#define RTC_CNTL_TOUCH_BUFDRV_V 0x00000007 -#define RTC_CNTL_TOUCH_BUFDRV_S 25 - -/* RTC_CNTL_TOUCH_SCAN_PAD_MAP : R/W; bitpos: [24:10]; default: 0; - * touch scan mode pad enable map - */ - -#define RTC_CNTL_TOUCH_SCAN_PAD_MAP 0x00007fff -#define RTC_CNTL_TOUCH_SCAN_PAD_MAP_M (RTC_CNTL_TOUCH_SCAN_PAD_MAP_V << RTC_CNTL_TOUCH_SCAN_PAD_MAP_S) -#define RTC_CNTL_TOUCH_SCAN_PAD_MAP_V 0x00007fff -#define RTC_CNTL_TOUCH_SCAN_PAD_MAP_S 10 - -/* RTC_CNTL_TOUCH_SHIELD_PAD_EN : R/W; bitpos: [9]; default: 0; - * touch pad14 will be used as shield - */ - -#define RTC_CNTL_TOUCH_SHIELD_PAD_EN (BIT(9)) -#define RTC_CNTL_TOUCH_SHIELD_PAD_EN_M (RTC_CNTL_TOUCH_SHIELD_PAD_EN_V << RTC_CNTL_TOUCH_SHIELD_PAD_EN_S) -#define RTC_CNTL_TOUCH_SHIELD_PAD_EN_V 0x00000001 -#define RTC_CNTL_TOUCH_SHIELD_PAD_EN_S 9 - -/* RTC_CNTL_TOUCH_INACTIVE_CONNECTION : R/W; bitpos: [8]; default: 1; - * inactive touch pads connect to 1: gnd 0: HighZ - */ - -#define RTC_CNTL_TOUCH_INACTIVE_CONNECTION (BIT(8)) -#define RTC_CNTL_TOUCH_INACTIVE_CONNECTION_M (RTC_CNTL_TOUCH_INACTIVE_CONNECTION_V << RTC_CNTL_TOUCH_INACTIVE_CONNECTION_S) -#define RTC_CNTL_TOUCH_INACTIVE_CONNECTION_V 0x00000001 -#define RTC_CNTL_TOUCH_INACTIVE_CONNECTION_S 8 - -/* RTC_CNTL_TOUCH_DENOISE_EN : R/W; bitpos: [2]; default: 0; - * touch pad0 will be used to de-noise - */ - -#define RTC_CNTL_TOUCH_DENOISE_EN (BIT(2)) -#define RTC_CNTL_TOUCH_DENOISE_EN_M (RTC_CNTL_TOUCH_DENOISE_EN_V << RTC_CNTL_TOUCH_DENOISE_EN_S) -#define RTC_CNTL_TOUCH_DENOISE_EN_V 0x00000001 -#define RTC_CNTL_TOUCH_DENOISE_EN_S 2 - -/* RTC_CNTL_TOUCH_DENOISE_RES : R/W; bitpos: [1:0]; default: 2; - * De-noise resolution: 12/10/8/4 bit - */ - -#define RTC_CNTL_TOUCH_DENOISE_RES 0x00000003 -#define RTC_CNTL_TOUCH_DENOISE_RES_M (RTC_CNTL_TOUCH_DENOISE_RES_V << RTC_CNTL_TOUCH_DENOISE_RES_S) -#define RTC_CNTL_TOUCH_DENOISE_RES_V 0x00000003 -#define RTC_CNTL_TOUCH_DENOISE_RES_S 0 - -/* RTC_CNTL_TOUCH_SLP_THRES_REG register - * Description - */ - -#define RTC_CNTL_TOUCH_SLP_THRES_REG (DR_REG_RTCCNTL_BASE + 0x110) - -/* RTC_CNTL_TOUCH_SLP_PAD : R/W; bitpos: [31:27]; default: 15; - * N/A - */ - -#define RTC_CNTL_TOUCH_SLP_PAD 0x0000001f -#define RTC_CNTL_TOUCH_SLP_PAD_M (RTC_CNTL_TOUCH_SLP_PAD_V << RTC_CNTL_TOUCH_SLP_PAD_S) -#define RTC_CNTL_TOUCH_SLP_PAD_V 0x0000001f -#define RTC_CNTL_TOUCH_SLP_PAD_S 27 - -/* RTC_CNTL_TOUCH_SLP_APPROACH_EN : R/W; bitpos: [26]; default: 0; - * sleep pad approach function enable - */ - -#define RTC_CNTL_TOUCH_SLP_APPROACH_EN (BIT(26)) -#define RTC_CNTL_TOUCH_SLP_APPROACH_EN_M (RTC_CNTL_TOUCH_SLP_APPROACH_EN_V << RTC_CNTL_TOUCH_SLP_APPROACH_EN_S) -#define RTC_CNTL_TOUCH_SLP_APPROACH_EN_V 0x00000001 -#define RTC_CNTL_TOUCH_SLP_APPROACH_EN_S 26 - -/* RTC_CNTL_TOUCH_SLP_TH : R/W; bitpos: [21:0]; default: 0; - * the threshold for sleep touch pad - */ - -#define RTC_CNTL_TOUCH_SLP_TH 0x003fffff -#define RTC_CNTL_TOUCH_SLP_TH_M (RTC_CNTL_TOUCH_SLP_TH_V << RTC_CNTL_TOUCH_SLP_TH_S) -#define RTC_CNTL_TOUCH_SLP_TH_V 0x003fffff -#define RTC_CNTL_TOUCH_SLP_TH_S 0 - -/* RTC_CNTL_TOUCH_APPROACH_REG register - * Description - */ - -#define RTC_CNTL_TOUCH_APPROACH_REG (DR_REG_RTCCNTL_BASE + 0x114) - -/* RTC_CNTL_TOUCH_APPROACH_MEAS_TIME : R/W; bitpos: [31:24]; default: 80; - * approach pads total meas times - */ - -#define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME 0x000000ff -#define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_M (RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_V << RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_S) -#define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_V 0x000000ff -#define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_S 24 - -/* RTC_CNTL_TOUCH_SLP_CHANNEL_CLR : WO; bitpos: [23]; default: 0; - * clear touch slp channel - */ - -#define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR (BIT(23)) -#define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_M (RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_V << RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_S) -#define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_V 0x00000001 -#define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_S 23 - -/* RTC_CNTL_TOUCH_FILTER_CTRL_REG register - * Description - */ - -#define RTC_CNTL_TOUCH_FILTER_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x118) - -/* RTC_CNTL_TOUCH_FILTER_EN : R/W; bitpos: [31]; default: 1; - * touch filter enable - */ - -#define RTC_CNTL_TOUCH_FILTER_EN (BIT(31)) -#define RTC_CNTL_TOUCH_FILTER_EN_M (RTC_CNTL_TOUCH_FILTER_EN_V << RTC_CNTL_TOUCH_FILTER_EN_S) -#define RTC_CNTL_TOUCH_FILTER_EN_V 0x00000001 -#define RTC_CNTL_TOUCH_FILTER_EN_S 31 - -/* RTC_CNTL_TOUCH_FILTER_MODE : R/W; bitpos: [30:28]; default: 1; - * 0: IIR ? 1: IIR ? 2: IIR 1/8 3: Jitter - */ - -#define RTC_CNTL_TOUCH_FILTER_MODE 0x00000007 -#define RTC_CNTL_TOUCH_FILTER_MODE_M (RTC_CNTL_TOUCH_FILTER_MODE_V << RTC_CNTL_TOUCH_FILTER_MODE_S) -#define RTC_CNTL_TOUCH_FILTER_MODE_V 0x00000007 -#define RTC_CNTL_TOUCH_FILTER_MODE_S 28 - -/* RTC_CNTL_TOUCH_DEBOUNCE : R/W; bitpos: [27:25]; default: 3; - * debounce counter - */ - -#define RTC_CNTL_TOUCH_DEBOUNCE 0x00000007 -#define RTC_CNTL_TOUCH_DEBOUNCE_M (RTC_CNTL_TOUCH_DEBOUNCE_V << RTC_CNTL_TOUCH_DEBOUNCE_S) -#define RTC_CNTL_TOUCH_DEBOUNCE_V 0x00000007 -#define RTC_CNTL_TOUCH_DEBOUNCE_S 25 - -/* RTC_CNTL_TOUCH_HYSTERESIS : R/W; bitpos: [24:23]; default: 1; - * N/A - */ - -#define RTC_CNTL_TOUCH_HYSTERESIS 0x00000003 -#define RTC_CNTL_TOUCH_HYSTERESIS_M (RTC_CNTL_TOUCH_HYSTERESIS_V << RTC_CNTL_TOUCH_HYSTERESIS_S) -#define RTC_CNTL_TOUCH_HYSTERESIS_V 0x00000003 -#define RTC_CNTL_TOUCH_HYSTERESIS_S 23 - -/* RTC_CNTL_TOUCH_NOISE_THRES : R/W; bitpos: [22:21]; default: 1; - * N/A - */ - -#define RTC_CNTL_TOUCH_NOISE_THRES 0x00000003 -#define RTC_CNTL_TOUCH_NOISE_THRES_M (RTC_CNTL_TOUCH_NOISE_THRES_V << RTC_CNTL_TOUCH_NOISE_THRES_S) -#define RTC_CNTL_TOUCH_NOISE_THRES_V 0x00000003 -#define RTC_CNTL_TOUCH_NOISE_THRES_S 21 - -/* RTC_CNTL_TOUCH_NEG_NOISE_THRES : R/W; bitpos: [20:19]; default: 1; - * N/A - */ - -#define RTC_CNTL_TOUCH_NEG_NOISE_THRES 0x00000003 -#define RTC_CNTL_TOUCH_NEG_NOISE_THRES_M (RTC_CNTL_TOUCH_NEG_NOISE_THRES_V << RTC_CNTL_TOUCH_NEG_NOISE_THRES_S) -#define RTC_CNTL_TOUCH_NEG_NOISE_THRES_V 0x00000003 -#define RTC_CNTL_TOUCH_NEG_NOISE_THRES_S 19 - -/* RTC_CNTL_TOUCH_NEG_NOISE_LIMIT : R/W; bitpos: [18:15]; default: 5; - * negative threshold counter limit - */ - -#define RTC_CNTL_TOUCH_NEG_NOISE_LIMIT 0x0000000f -#define RTC_CNTL_TOUCH_NEG_NOISE_LIMIT_M (RTC_CNTL_TOUCH_NEG_NOISE_LIMIT_V << RTC_CNTL_TOUCH_NEG_NOISE_LIMIT_S) -#define RTC_CNTL_TOUCH_NEG_NOISE_LIMIT_V 0x0000000f -#define RTC_CNTL_TOUCH_NEG_NOISE_LIMIT_S 15 - -/* RTC_CNTL_TOUCH_JITTER_STEP : R/W; bitpos: [14:11]; default: 1; - * touch jitter step - */ - -#define RTC_CNTL_TOUCH_JITTER_STEP 0x0000000f -#define RTC_CNTL_TOUCH_JITTER_STEP_M (RTC_CNTL_TOUCH_JITTER_STEP_V << RTC_CNTL_TOUCH_JITTER_STEP_S) -#define RTC_CNTL_TOUCH_JITTER_STEP_V 0x0000000f -#define RTC_CNTL_TOUCH_JITTER_STEP_S 11 - -/* RTC_CNTL_TOUCH_SMOOTH_LVL : R/W; bitpos: [10:9]; default: 0; - * touch jitter step - */ - -#define RTC_CNTL_TOUCH_SMOOTH_LVL 0x00000003 -#define RTC_CNTL_TOUCH_SMOOTH_LVL_M (RTC_CNTL_TOUCH_SMOOTH_LVL_V << RTC_CNTL_TOUCH_SMOOTH_LVL_S) -#define RTC_CNTL_TOUCH_SMOOTH_LVL_V 0x00000003 -#define RTC_CNTL_TOUCH_SMOOTH_LVL_S 9 - -/* RTC_CNTL_USB_CONF_REG register - * configure usb control register - */ - -#define RTC_CNTL_USB_CONF_REG (DR_REG_RTCCNTL_BASE + 0x11c) - -/* RTC_CNTL_IO_MUX_RESET_DISABLE : R/W; bitpos: [18]; default: 0; */ - -#define RTC_CNTL_IO_MUX_RESET_DISABLE (BIT(18)) -#define RTC_CNTL_IO_MUX_RESET_DISABLE_M (RTC_CNTL_IO_MUX_RESET_DISABLE_V << RTC_CNTL_IO_MUX_RESET_DISABLE_S) -#define RTC_CNTL_IO_MUX_RESET_DISABLE_V 0x00000001 -#define RTC_CNTL_IO_MUX_RESET_DISABLE_S 18 - -/* RTC_CNTL_USB_RESET_DISABLE : R/W; bitpos: [17]; default: 0; */ - -#define RTC_CNTL_USB_RESET_DISABLE (BIT(17)) -#define RTC_CNTL_USB_RESET_DISABLE_M (RTC_CNTL_USB_RESET_DISABLE_V << RTC_CNTL_USB_RESET_DISABLE_S) -#define RTC_CNTL_USB_RESET_DISABLE_V 0x00000001 -#define RTC_CNTL_USB_RESET_DISABLE_S 17 - -/* RTC_CNTL_USB_TX_EN_OVERRIDE : R/W; bitpos: [16]; default: 0; */ - -#define RTC_CNTL_USB_TX_EN_OVERRIDE (BIT(16)) -#define RTC_CNTL_USB_TX_EN_OVERRIDE_M (RTC_CNTL_USB_TX_EN_OVERRIDE_V << RTC_CNTL_USB_TX_EN_OVERRIDE_S) -#define RTC_CNTL_USB_TX_EN_OVERRIDE_V 0x00000001 -#define RTC_CNTL_USB_TX_EN_OVERRIDE_S 16 - -/* RTC_CNTL_USB_TX_EN : R/W; bitpos: [15]; default: 0; */ - -#define RTC_CNTL_USB_TX_EN (BIT(15)) -#define RTC_CNTL_USB_TX_EN_M (RTC_CNTL_USB_TX_EN_V << RTC_CNTL_USB_TX_EN_S) -#define RTC_CNTL_USB_TX_EN_V 0x00000001 -#define RTC_CNTL_USB_TX_EN_S 15 - -/* RTC_CNTL_USB_TXP : R/W; bitpos: [14]; default: 0; */ - -#define RTC_CNTL_USB_TXP (BIT(14)) -#define RTC_CNTL_USB_TXP_M (RTC_CNTL_USB_TXP_V << RTC_CNTL_USB_TXP_S) -#define RTC_CNTL_USB_TXP_V 0x00000001 -#define RTC_CNTL_USB_TXP_S 14 - -/* RTC_CNTL_USB_TXM : R/W; bitpos: [13]; default: 0; */ - -#define RTC_CNTL_USB_TXM (BIT(13)) -#define RTC_CNTL_USB_TXM_M (RTC_CNTL_USB_TXM_V << RTC_CNTL_USB_TXM_S) -#define RTC_CNTL_USB_TXM_V 0x00000001 -#define RTC_CNTL_USB_TXM_S 13 - -/* RTC_CNTL_USB_PAD_ENABLE : R/W; bitpos: [12]; default: 0; */ - -#define RTC_CNTL_USB_PAD_ENABLE (BIT(12)) -#define RTC_CNTL_USB_PAD_ENABLE_M (RTC_CNTL_USB_PAD_ENABLE_V << RTC_CNTL_USB_PAD_ENABLE_S) -#define RTC_CNTL_USB_PAD_ENABLE_V 0x00000001 -#define RTC_CNTL_USB_PAD_ENABLE_S 12 - -/* RTC_CNTL_USB_PAD_ENABLE_OVERRIDE : R/W; bitpos: [11]; default: 0; */ - -#define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE (BIT(11)) -#define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_M (RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_V << RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_S) -#define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_V 0x00000001 -#define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_S 11 - -/* RTC_CNTL_USB_PULLUP_VALUE : R/W; bitpos: [10]; default: 0; */ - -#define RTC_CNTL_USB_PULLUP_VALUE (BIT(10)) -#define RTC_CNTL_USB_PULLUP_VALUE_M (RTC_CNTL_USB_PULLUP_VALUE_V << RTC_CNTL_USB_PULLUP_VALUE_S) -#define RTC_CNTL_USB_PULLUP_VALUE_V 0x00000001 -#define RTC_CNTL_USB_PULLUP_VALUE_S 10 - -/* RTC_CNTL_USB_DM_PULLDOWN : R/W; bitpos: [9]; default: 0; */ - -#define RTC_CNTL_USB_DM_PULLDOWN (BIT(9)) -#define RTC_CNTL_USB_DM_PULLDOWN_M (RTC_CNTL_USB_DM_PULLDOWN_V << RTC_CNTL_USB_DM_PULLDOWN_S) -#define RTC_CNTL_USB_DM_PULLDOWN_V 0x00000001 -#define RTC_CNTL_USB_DM_PULLDOWN_S 9 - -/* RTC_CNTL_USB_DM_PULLUP : R/W; bitpos: [8]; default: 0; */ - -#define RTC_CNTL_USB_DM_PULLUP (BIT(8)) -#define RTC_CNTL_USB_DM_PULLUP_M (RTC_CNTL_USB_DM_PULLUP_V << RTC_CNTL_USB_DM_PULLUP_S) -#define RTC_CNTL_USB_DM_PULLUP_V 0x00000001 -#define RTC_CNTL_USB_DM_PULLUP_S 8 - -/* RTC_CNTL_USB_DP_PULLDOWN : R/W; bitpos: [7]; default: 0; */ - -#define RTC_CNTL_USB_DP_PULLDOWN (BIT(7)) -#define RTC_CNTL_USB_DP_PULLDOWN_M (RTC_CNTL_USB_DP_PULLDOWN_V << RTC_CNTL_USB_DP_PULLDOWN_S) -#define RTC_CNTL_USB_DP_PULLDOWN_V 0x00000001 -#define RTC_CNTL_USB_DP_PULLDOWN_S 7 - -/* RTC_CNTL_USB_DP_PULLUP : R/W; bitpos: [6]; default: 0; */ - -#define RTC_CNTL_USB_DP_PULLUP (BIT(6)) -#define RTC_CNTL_USB_DP_PULLUP_M (RTC_CNTL_USB_DP_PULLUP_V << RTC_CNTL_USB_DP_PULLUP_S) -#define RTC_CNTL_USB_DP_PULLUP_V 0x00000001 -#define RTC_CNTL_USB_DP_PULLUP_S 6 - -/* RTC_CNTL_USB_PAD_PULL_OVERRIDE : R/W; bitpos: [5]; default: 0; */ - -#define RTC_CNTL_USB_PAD_PULL_OVERRIDE (BIT(5)) -#define RTC_CNTL_USB_PAD_PULL_OVERRIDE_M (RTC_CNTL_USB_PAD_PULL_OVERRIDE_V << RTC_CNTL_USB_PAD_PULL_OVERRIDE_S) -#define RTC_CNTL_USB_PAD_PULL_OVERRIDE_V 0x00000001 -#define RTC_CNTL_USB_PAD_PULL_OVERRIDE_S 5 - -/* RTC_CNTL_USB_VREF_OVERRIDE : R/W; bitpos: [4]; default: 0; */ - -#define RTC_CNTL_USB_VREF_OVERRIDE (BIT(4)) -#define RTC_CNTL_USB_VREF_OVERRIDE_M (RTC_CNTL_USB_VREF_OVERRIDE_V << RTC_CNTL_USB_VREF_OVERRIDE_S) -#define RTC_CNTL_USB_VREF_OVERRIDE_V 0x00000001 -#define RTC_CNTL_USB_VREF_OVERRIDE_S 4 - -/* RTC_CNTL_USB_VREFL : R/W; bitpos: [3:2]; default: 0; */ - -#define RTC_CNTL_USB_VREFL 0x00000003 -#define RTC_CNTL_USB_VREFL_M (RTC_CNTL_USB_VREFL_V << RTC_CNTL_USB_VREFL_S) -#define RTC_CNTL_USB_VREFL_V 0x00000003 -#define RTC_CNTL_USB_VREFL_S 2 - -/* RTC_CNTL_USB_VREFH : R/W; bitpos: [1:0]; default: 0; */ - -#define RTC_CNTL_USB_VREFH 0x00000003 -#define RTC_CNTL_USB_VREFH_M (RTC_CNTL_USB_VREFH_V << RTC_CNTL_USB_VREFH_S) -#define RTC_CNTL_USB_VREFH_V 0x00000003 -#define RTC_CNTL_USB_VREFH_S 0 - -/* RTC_CNTL_TOUCH_TIMEOUT_CTRL_REG register - * Description - */ - -#define RTC_CNTL_TOUCH_TIMEOUT_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x120) - -/* RTC_CNTL_TOUCH_TIMEOUT_EN : R/W; bitpos: [22]; default: 1; - * N/A - */ - -#define RTC_CNTL_TOUCH_TIMEOUT_EN (BIT(22)) -#define RTC_CNTL_TOUCH_TIMEOUT_EN_M (RTC_CNTL_TOUCH_TIMEOUT_EN_V << RTC_CNTL_TOUCH_TIMEOUT_EN_S) -#define RTC_CNTL_TOUCH_TIMEOUT_EN_V 0x00000001 -#define RTC_CNTL_TOUCH_TIMEOUT_EN_S 22 - -/* RTC_CNTL_TOUCH_TIMEOUT_NUM : R/W; bitpos: [21:0]; default: 4194303; - * N/A - */ - -#define RTC_CNTL_TOUCH_TIMEOUT_NUM 0x003fffff -#define RTC_CNTL_TOUCH_TIMEOUT_NUM_M (RTC_CNTL_TOUCH_TIMEOUT_NUM_V << RTC_CNTL_TOUCH_TIMEOUT_NUM_S) -#define RTC_CNTL_TOUCH_TIMEOUT_NUM_V 0x003fffff -#define RTC_CNTL_TOUCH_TIMEOUT_NUM_S 0 - -/* RTC_CNTL_SLP_REJECT_CAUSE_REG register - * Stores the reject-to-sleep cause. - */ - -#define RTC_CNTL_SLP_REJECT_CAUSE_REG (DR_REG_RTCCNTL_BASE + 0x124) - -/* RTC_CNTL_REJECT_CAUSE : RO; bitpos: [16:0]; default: 0; - * Stores the reject-to-sleep cause. - */ - -#define RTC_CNTL_REJECT_CAUSE 0x0001ffff -#define RTC_CNTL_REJECT_CAUSE_M (RTC_CNTL_REJECT_CAUSE_V << RTC_CNTL_REJECT_CAUSE_S) -#define RTC_CNTL_REJECT_CAUSE_V 0x0001ffff -#define RTC_CNTL_REJECT_CAUSE_S 0 - -/* RTC_CNTL_OPTION1_REG register - * RTC option register - */ - -#define RTC_CNTL_OPTION1_REG (DR_REG_RTCCNTL_BASE + 0x128) - -/* RTC_CNTL_FORCE_DOWNLOAD_BOOT : R/W; bitpos: [0]; default: 0; - * Set this bit to force the chip to boot from the download mode. - */ - -#define RTC_CNTL_FORCE_DOWNLOAD_BOOT (BIT(0)) -#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_M (RTC_CNTL_FORCE_DOWNLOAD_BOOT_V << RTC_CNTL_FORCE_DOWNLOAD_BOOT_S) -#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_V 0x00000001 -#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_S 0 - -/* RTC_CNTL_SLP_WAKEUP_CAUSE_REG register - * Stores the sleep-to-wakeup cause. - */ - -#define RTC_CNTL_SLP_WAKEUP_CAUSE_REG (DR_REG_RTCCNTL_BASE + 0x12c) - -/* RTC_CNTL_WAKEUP_CAUSE : RO; bitpos: [16:0]; default: 0; - * Stores the wakeup cause. - */ - -#define RTC_CNTL_WAKEUP_CAUSE 0x0001ffff -#define RTC_CNTL_WAKEUP_CAUSE_M (RTC_CNTL_WAKEUP_CAUSE_V << RTC_CNTL_WAKEUP_CAUSE_S) -#define RTC_CNTL_WAKEUP_CAUSE_V 0x0001ffff -#define RTC_CNTL_WAKEUP_CAUSE_S 0 - -/* RTC_CNTL_ULP_CP_TIMER_1_REG register - * Description - */ - -#define RTC_CNTL_ULP_CP_TIMER_1_REG (DR_REG_RTCCNTL_BASE + 0x130) - -/* RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE : R/W; bitpos: [31:8]; default: 200; - * sleep cycles for ULP-coprocessor timer - */ - -#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE 0x00ffffff -#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_M (RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V << RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S) -#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V 0x00ffffff -#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S 8 - -/* RTC_CNTL_DATE_REG register */ - -#define RTC_CNTL_DATE_REG (DR_REG_RTCCNTL_BASE + 0x138) - -/* RTC_CNTL_CNTL_DATE : R/W; bitpos: [27:0]; default: 26239377; */ - -#define RTC_CNTL_CNTL_DATE 0x0fffffff -#define RTC_CNTL_CNTL_DATE_M (RTC_CNTL_CNTL_DATE_V << RTC_CNTL_CNTL_DATE_S) -#define RTC_CNTL_CNTL_DATE_V 0x0fffffff -#define RTC_CNTL_CNTL_DATE_S 0 - -#endif /* __ARCH_XTENSA_SRC_ESP32S2_HARDWARE_ESP32S2_RTCCNTL_H */ diff --git a/arch/xtensa/src/esp32s3/Kconfig b/arch/xtensa/src/esp32s3/Kconfig index d6679ffed8b64..e0488a18f3917 100644 --- a/arch/xtensa/src/esp32s3/Kconfig +++ b/arch/xtensa/src/esp32s3/Kconfig @@ -444,7 +444,7 @@ config ESP32S3_I2S0 bool "I2S 0" default n select ESP32S3_DMA - select ESP32S3_GPIO_IRQ + select ESPRESSIF_GPIO_IRQ select SCHED_HPWORK select ESPRESSIF_I2S0 @@ -555,7 +555,7 @@ config ESP32S3_I2S1 bool "I2S 1" default n select ESP32S3_DMA - select ESP32S3_GPIO_IRQ + select ESPRESSIF_GPIO_IRQ select SCHED_HPWORK select ESPRESSIF_I2S1 @@ -700,7 +700,7 @@ config ESP32S3_SPI2 default n select ESP32S3_SPI select SPI - select ESP32S3_GPIO_IRQ if SPI_SLAVE + select ESPRESSIF_GPIO_IRQ if SPI_SLAVE select ESPRESSIF_SPI_PERIPH config ESP32S3_SPI3 @@ -708,7 +708,7 @@ config ESP32S3_SPI3 default n select ESP32S3_SPI select SPI - select ESP32S3_GPIO_IRQ if SPI_SLAVE + select ESPRESSIF_GPIO_IRQ if SPI_SLAVE select ESPRESSIF_SPI_PERIPH config ESP32S3_DMA @@ -913,8 +913,12 @@ config ESP32S3_XTWDT_BACKUP_CLK_ENABLE config ESP32S3_RT_TIMER bool "Real-Time Timer" default n + select ESPRESSIF_HR_TIMER ---help--- - Real-Time Timer is relying upon the Systimer 1. + Deprecated: Use ESPRESSIF_HR_TIMER instead. + This option is kept for backward compatibility and automatically + selects the common ESPRESSIF_HR_TIMER configuration. + config ESP32S3_WCL bool "World Controller" @@ -954,12 +958,16 @@ menu "Interrupt Configuration" config ESP32S3_IRAM_ISR_DEBUG bool "Enable debugging of the IRAM-enabled interrupts" default n + select ESPRESSIF_IRAM_ISR_DEBUG ---help--- This option enables keeping track of the IRAM-enabled interrupts by registering its execution when non-IRAM interrupts are disabled. It keeps track of the IRQ executed and register how many times since boot it was executed. + This option is kept for backwards compatibility and automatically + selects CONFIG_ESPRESSIF_IRAM_ISR_DEBUG. + endmenu # Interrupt Configuration menu "SPI RAM Configuration" @@ -1173,9 +1181,11 @@ endmenu # Memory Configuration config ESP32S3_GPIO_IRQ bool "GPIO pin interrupts" + select ESPRESSIF_GPIO_IRQ default n ---help--- - Enable support for interrupting GPIO pins. + This is a deprecated Kconfig macro. Its kept for retrocompatibility only. + Use "CONFIG_ESPRESSIF_GPIO_IRQ" instead. config ESP32S3_RTCIO_IRQ bool "RTC IO interrupts" @@ -1241,6 +1251,8 @@ config ESP32S3_SPI_SLAVE_BUFSIZE default 2048 depends on SPI_SLAVE +if ESP32S3_SPI2 + config ESP32S3_SPI2_CSPIN int "SPI2 CS Pin" default 10 @@ -1273,6 +1285,10 @@ config ESP32S3_SPI2_IO3PIN range 0 48 depends on ESP32S3_SPI_IO_QIO +endif # ESP32S3_SPI2 + +if ESP32S3_SPI3 + config ESP32S3_SPI3_CSPIN int "SPI3 CS Pin" default 10 @@ -1305,6 +1321,8 @@ config ESP32S3_SPI3_IO3PIN range 0 48 depends on ESP32S3_SPI_IO_QIO +endif # ESP32S3_SPI3 + endmenu # SPI configuration menu "UART Configuration" @@ -1807,27 +1825,6 @@ config ESP32S3_SYSTEM_BBPLL_RECALIB endmenu # "RTC Configuration" - -menu "Real-Time Timer Configuration" - depends on ESP32S3_RT_TIMER - -config ESP32S3_RT_TIMER_TASK_NAME - string "Real-Time Timer task name" - default "rt_timer" - -config ESP32S3_RT_TIMER_TASK_PRIORITY - int "Real-Time Timer task priority" - default 223 - ---help--- - Priority level of the RT Timer task. - Must be lower than the SCHED_HPWORKPRIORITY. - -config ESP32S3_RT_TIMER_TASK_STACK_SIZE - int "Real-Time Timer task stack size" - default 2048 - -endmenu # Real-Time Timer Configuration - config ESP32S3_TICKLESS bool "Enable Tickless OS" default n diff --git a/arch/xtensa/src/esp32s3/Make.defs b/arch/xtensa/src/esp32s3/Make.defs index 3e13b4a7925cc..2805b63979204 100644 --- a/arch/xtensa/src/esp32s3/Make.defs +++ b/arch/xtensa/src/esp32s3/Make.defs @@ -28,9 +28,9 @@ HEAD_CSRC = esp32s3_start.c # Required ESP32-S3 files (arch/xtensa/src/esp32s3) -CHIP_CSRCS = esp32s3_cache.c esp32s3_irq.c esp32s3_clockconfig.c esp32s3_region.c +CHIP_CSRCS = esp32s3_cache.c esp32s3_region.c CHIP_CSRCS += esp32s3_systemreset.c esp32s3_user.c esp32s3_allocateheap.c esp32s3_reset_reasons.c -CHIP_CSRCS += esp32s3_wdt.c esp32s3_gpio.c esp32s3_lowputc.c esp32s3_serial.c +CHIP_CSRCS += esp32s3_wdt.c esp32s3_lowputc.c esp32s3_serial.c CHIP_CSRCS += esp32s3_rtc_gpio.c esp32s3_libc_stubs.c esp32s3_spi_timing.c # Configuration-dependent ESP32-S3 files @@ -91,10 +91,6 @@ ifeq ($(CONFIG_ESP32S3_DMA),y) CHIP_CSRCS += esp32s3_dma.c endif -ifeq ($(CONFIG_ESP32S3_RT_TIMER),y) -CHIP_CSRCS += esp32s3_rt_timer.c -endif - ifeq ($(CONFIG_ESP32S3_I2C),y) ifeq ($(CONFIG_ESPRESSIF_I2C_PERIPH_MASTER_MODE),y) CHIP_CSRCS += esp32s3_i2c.c @@ -163,12 +159,6 @@ ifeq ($(CONFIG_ESP32S3_OTG_DEVICE),y) CHIP_CSRCS += esp32s3_otg_device.c endif -CHIP_CSRCS += esp32s3_rtc.c - -ifeq ($(CONFIG_RTC_DRIVER),y) -CHIP_CSRCS += esp32s3_rtc_lowerhalf.c -endif - ifeq ($(CONFIG_ESP32S3_LCD),y) CHIP_CSRCS += esp32s3_lcd.c endif @@ -202,7 +192,7 @@ endif ESP_HAL_3RDPARTY_REPO = esp-hal-3rdparty ifndef ESP_HAL_3RDPARTY_VERSION - ESP_HAL_3RDPARTY_VERSION = 6b4f19b48c5ba0e847511b5b21584e797ec795dc + ESP_HAL_3RDPARTY_VERSION = 6c272b562a73107a852d44b9c6fb5df57245cbd7 endif ifndef ESP_HAL_3RDPARTY_URL @@ -228,7 +218,7 @@ define CLONE_ESP_HAL_3RDPARTY_REPO endef else define CLONE_ESP_HAL_3RDPARTY_REPO - $(call CHECK_COMMITSHA, $(NXTMPDIR)/$(ESP_HAL_3RDPARTY_REPO),$(ESP_HAL_3RDPARTY_VERSION)) +$(call CHECK_COMMITSHA, $(NXTMPDIR)/$(ESP_HAL_3RDPARTY_REPO),$(ESP_HAL_3RDPARTY_VERSION)) $(call CLONE, $(ESP_HAL_3RDPARTY_URL),chip/$(ESP_HAL_3RDPARTY_REPO),$(NXTMPDIR)/$(ESP_HAL_3RDPARTY_REPO)) endef endif @@ -242,13 +232,17 @@ chip/$(ESP_HAL_3RDPARTY_REPO): $(Q) echo "Cloning Espressif HAL for 3rd Party Platforms" $(Q) $(call CLONE_ESP_HAL_3RDPARTY_REPO) ifneq ($(USE_NXTMPDIR_ESP_REPO_DIRECTLY),y) + $(Q) echo "Espressif HAL for 3rd Party Platforms: cleaning current repository..." + $(Q) git -C chip/$(ESP_HAL_3RDPARTY_REPO) clean -ffdx + $(Q) git -C chip/$(ESP_HAL_3RDPARTY_REPO) reset --quiet --hard --recurse-submodules || true $(Q) echo "Espressif HAL for 3rd Party Platforms: ${ESP_HAL_3RDPARTY_VERSION}" $(Q) git -C chip/$(ESP_HAL_3RDPARTY_REPO) checkout --quiet $(ESP_HAL_3RDPARTY_VERSION) endif # Silent preprocessor warnings -CFLAGS += -Wno-undef -Wno-unused-variable -fno-jump-tables -fno-tree-switch-conversion +CFLAGS += -Wno-undef -Wno-unused-variable -fno-jump-tables -fno-tree-switch-conversion -Wno-deprecated-declarations + CFLAGS += ${DEFINE_PREFIX}_RETARGETABLE_LOCKING # Enable strict volatile bitfield access @@ -284,3 +278,5 @@ endif distclean:: $(call DELDIR,chip/$(ESP_HAL_3RDPARTY_REPO)) $(call DELFILE,../../../vefuse.bin) + +INCLUDES += ${INCDIR_PREFIX}$(ARCH_SRCDIR)$(DELIM)common$(DELIM)espressif diff --git a/arch/xtensa/src/esp32s3/chip.h b/arch/xtensa/src/esp32s3/chip.h index de74a17c482a5..a2d0400093b61 100644 --- a/arch/xtensa/src/esp32s3/chip.h +++ b/arch/xtensa/src/esp32s3/chip.h @@ -32,7 +32,7 @@ #if defined(CONFIG_ESP32S3_OPENETH) && !defined(__ASSEMBLY__) #include "hardware/esp32s3_soc.h" -#include "esp32s3_irq.h" +#include "esp_irq.h" #endif /**************************************************************************** @@ -41,9 +41,9 @@ #if defined(CONFIG_ESP32S3_OPENETH) #define OPENETH_PERIPH_MAC ESP32S3_PERIPH_MAC -#define OPENETH_CPUINT_LEVEL ESP32S3_CPUINT_LEVEL +#define OPENETH_CPUINT_LEVEL ESP_IRQ_TRIGGER_LEVEL #define OPENETH_IRQ_MAC ESP32S3_IRQ_MAC -#define OPENETH_SETUP_IRQ esp32s3_setup_irq +#define OPENETH_SETUP_IRQ esp_setup_irq #define RX_BUF_COUNT CONFIG_ESP32S3_OPENETH_DMA_RX_BUFFER_NUM #endif diff --git a/arch/xtensa/src/esp32s3/esp32s3_ble_adapter.c b/arch/xtensa/src/esp32s3/esp32s3_ble_adapter.c index 5fb079aac397c..3fd7fda5e0467 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_ble_adapter.c +++ b/arch/xtensa/src/esp32s3/esp32s3_ble_adapter.c @@ -48,16 +48,17 @@ #include #include -#include "hardware/esp32s3_rtccntl.h" +#include "soc/rtc_cntl_reg.h" #include "hardware/esp32s3_syscon.h" #include "hardware/wdev_reg.h" #include "xtensa.h" #include "esp_attr.h" -#include "esp32s3_irq.h" -#include "esp32s3_rt_timer.h" -#include "esp32s3_rtc.h" +#include "esp_irq.h" +#include "esp_hr_timer.h" #include "espressif/esp_wireless.h" +#include "soc/rtc.h" + #include "esp_bt.h" #include "esp_log.h" #include "esp_mac.h" @@ -99,45 +100,15 @@ #define OSI_VERSION 0x0001000a #define OSI_MAGIC_VALUE 0xfadebead -#define BLE_PWR_HDL_INVL 0xffff - #ifdef CONFIG_ESPRESSIF_SPIFLASH # define BLE_TASK_EVENT_QUEUE_ITEM_SIZE 8 # define BLE_TASK_EVENT_QUEUE_LEN 8 #endif -#ifdef CONFIG_ESPRESSIF_BLE_INTERRUPT_SAVE_STATUS -# define NR_IRQSTATE_FLAGS CONFIG_ESPRESSIF_BLE_INTERRUPT_SAVE_STATUS -#else -# define NR_IRQSTATE_FLAGS 3 -#endif - /**************************************************************************** * Private Types ****************************************************************************/ -/* Pack using bitfields for better memory use */ - -typedef struct vector_desc_s vector_desc_t; - -struct vector_desc_s -{ - int flags: 16; - unsigned int cpu: 1; - unsigned int intno: 5; - int source: 8; - void *shared_vec_info; - vector_desc_t *next; -}; - -/** Interrupt handler associated data structure */ - -struct intr_handle_data_t -{ - vector_desc_t *vector_desc; - void *shared_vector_desc; -}; - /* VHCI function interface */ typedef struct vhci_host_callback_s @@ -146,16 +117,6 @@ typedef struct vhci_host_callback_s int (*notify_host_recv)(uint8_t *data, uint16_t len); /* callback used to notify that the controller has a packet to send to the host */ } vhci_host_callback_t; -typedef struct -{ - int source; /* ISR source */ - int flags; /* ISR alloc flag */ - void (*fn)(void *); /* ISR function */ - void *arg; /* ISR function args */ - intr_handle_t *handle; /* ISR handle */ - esp_err_t ret; -} btdm_isr_alloc_t; - /* BLE OS function */ struct osi_funcs_s @@ -479,9 +440,6 @@ extern int api_vhci_host_register_callback(const vhci_host_callback_t /* TX power */ -extern int ble_txpwr_set(int power_type, uint16_t handle, int power_level); -extern int ble_txpwr_get(int power_type, uint16_t handle); - extern int coex_core_ble_conn_dyn_prio_get(bool *low, bool *high); extern void coex_pti_v2(void); @@ -641,11 +599,9 @@ static DRAM_ATTR void * g_light_sleep_pm_lock; /* BT interrupt private data */ -static sq_queue_t g_ble_int_flags_free; - -static sq_queue_t g_ble_int_flags_used; +irqstate_t g_ble_int_flags; -static struct irqstate_list_s g_ble_int_flags[NR_IRQSTATE_FLAGS]; +static int g_ble_int_count = 0; /* Cached queue control variables */ @@ -763,9 +719,7 @@ static int interrupt_alloc_wrapper(int cpu_id, void *arg, void **ret_handle) { - btdm_isr_alloc_t *p; - struct intr_handle_data_t *handle; - vector_desc_t *vd; + struct intr_adapter_to_nuttx *isr_adapter_args; int ret = OK; int cpuint; int irq; @@ -773,57 +727,24 @@ static int interrupt_alloc_wrapper(int cpu_id, wlinfo("cpu_id=%d , source=%d , handler=%p, arg=%p, ret_handle=%p\n", cpu_id, source, handler, arg, ret_handle); - p = kmm_calloc(1, sizeof(btdm_isr_alloc_t)); - if (p == NULL) - { - return ESP_ERR_NOT_FOUND; - } - - handle = kmm_calloc(1, sizeof(struct intr_handle_data_t)); - if (handle == NULL) + isr_adapter_args = kmm_calloc(1, sizeof(struct intr_adapter_to_nuttx)); + if (isr_adapter_args == NULL) { - free(p); - return ESP_ERR_NOT_FOUND; + irqerr("Failed to kmm_calloc\n"); + return ESP_ERR_NO_MEM; } - p->source = source; - p->flags = ESP_INTR_FLAG_LEVEL2 | ESP_INTR_FLAG_IRAM; - p->fn = handler; - p->arg = arg; - p->handle = (intr_handle_t *)ret_handle; + isr_adapter_args->handler = handler; + isr_adapter_args->arg = arg; - cpuint = esp32s3_setup_irq(cpu_id, source, 2, ESP32S3_CPUINT_LEVEL); + cpuint = esp_setup_irq(source, 2, ESP_IRQ_TRIGGER_LEVEL, esp_int_adpt_cb, + isr_adapter_args); if (cpuint < 0) { - kmm_free(handle); - return ESP_ERR_NOT_FOUND; - } - - vd = kmm_calloc(1, sizeof(vector_desc_t)); - if (vd == NULL) - { - kmm_free(handle); return ESP_ERR_NOT_FOUND; } - vd->intno = cpuint; - vd->cpu = cpu_id; - vd->source = source; - - irq = esp32s3_getirq(cpu_id, cpuint); - - handle->vector_desc = vd; - handle->shared_vector_desc = vd->shared_vec_info; - - *(p->handle) = handle; - - ret = irq_attach(irq, esp_int_adpt_cb, p); - if (ret != OK) - { - kmm_free(p); - kmm_free(handle); - return ESP_ERR_NOT_FOUND; - } + (*ret_handle) = (void *)esp_get_handle(cpu_id, ESP_SOURCE2IRQ(source)); return ESP_OK; } @@ -868,13 +789,12 @@ static void IRAM_ATTR global_interrupt_disable(void) { struct irqstate_list_s *irqstate; - irqstate = (struct irqstate_list_s *)sq_remlast(&g_ble_int_flags_free); - - ASSERT(irqstate != NULL); - - irqstate->flags = enter_critical_section(); + if (g_ble_int_count == 0) + { + g_ble_int_flags = enter_critical_section(); + } - sq_addlast((sq_entry_t *)irqstate, &g_ble_int_flags_used); + g_ble_int_count++; } /**************************************************************************** @@ -896,13 +816,12 @@ static void IRAM_ATTR global_interrupt_restore(void) { struct irqstate_list_s *irqstate; - irqstate = (struct irqstate_list_s *)sq_remlast(&g_ble_int_flags_used); - - ASSERT(irqstate != NULL); - - leave_critical_section(irqstate->flags); + g_ble_int_count--; - sq_addlast((sq_entry_t *)irqstate, &g_ble_int_flags_free); + if (g_ble_int_count == 0) + { + leave_critical_section(g_ble_int_flags); + } } /**************************************************************************** @@ -1001,7 +920,7 @@ static void semphr_delete_wrapper(void *semphr) * hptw - Unused. * * Returned Value: - * True if success or false if fail + * True * ****************************************************************************/ @@ -2039,30 +1958,7 @@ static void * coex_schm_curr_phase_get_wrapper(void) static int interrupt_enable_wrapper(void *handle) { - intr_handle_t isr = (intr_handle_t)handle; - int ret = ESP_OK; - int cpuint; - int irq; - - cpuint = isr->vector_desc->intno; - - irq = esp32s3_getirq(0, cpuint); - if (irq == 127) - { - wlerr("CPU interrupt is not assigned!\n"); - return ESP_ERR_INVALID_ARG; - } - - ret = esp32s3_irq_set_iram_isr(irq); - if (ret != ESP_OK) - { - wlerr("Failed to set IRAM ISR\n"); - return ESP_ERR_INVALID_ARG; - } - - up_enable_irq(irq); - - return ret == OK ? ESP_OK : ESP_ERR_INVALID_ARG; + return esp_intr_enable((intr_handle_t)handle); } /**************************************************************************** @@ -2083,23 +1979,7 @@ static int interrupt_enable_wrapper(void *handle) static int interrupt_disable_wrapper(void *handle) { - intr_handle_t isr = (intr_handle_t)handle; - int ret = ESP_OK; - int cpuint; - int irq; - - cpuint = isr->vector_desc->intno; - - irq = esp32s3_getirq(0, cpuint); - if (irq == 127) - { - wlerr("CPU interrupt is not assigned!\n"); - return ESP_ERR_INVALID_ARG; - } - - up_disable_irq(irq); - - return ret == OK ? ESP_OK : ESP_ERR_INVALID_ARG; + return esp_intr_disable((intr_handle_t)handle); } /**************************************************************************** @@ -2326,7 +2206,7 @@ static IRAM_ATTR int32_t esp_queue_send_generic(void *queue, void *item, * Transform ticks to time and add this time to timespec value * * Input Parameters: - * ticks - System ticks + * ticks - System ticks * * Output Parameters: * timespec - Input timespec data pointer @@ -2373,7 +2253,10 @@ static void IRAM_ATTR btdm_slp_tmr_callback(void *arg) * BT interrupt adapter callback function * * Input Parameters: - * arg - interrupt adapter private data + * irq - IRQ associated to that interrupt. + * context - Interrupt register state save info. + * arg - A pointer to the argument provided when the interrupt + * was registered. * * Returned Value: * NuttX error code @@ -2382,9 +2265,11 @@ static void IRAM_ATTR btdm_slp_tmr_callback(void *arg) static int IRAM_ATTR esp_int_adpt_cb(int irq, void *context, void *arg) { - btdm_isr_alloc_t *p = (btdm_isr_alloc_t *)arg; + struct intr_adapter_to_nuttx *isr_adapter_args; + + isr_adapter_args = (struct intr_adapter_to_nuttx *)arg; - p->fn(p->arg); + isr_adapter_args->handler(isr_adapter_args->arg); return OK; } @@ -2572,7 +2457,7 @@ static esp_err_t btdm_low_power_mode_init(esp_bt_controller_config_t *cfg) { /* check whether or not EXT_CRYS is working */ - if (esp32s3_rtc_clk_slow_freq_get() != + if (rtc_clk_slow_src_get() != SOC_RTC_SLOW_CLK_SRC_XTAL32K) { wlwarn("32.768kHz XTAL not detected, fall back to main" @@ -2587,7 +2472,7 @@ static esp_err_t btdm_low_power_mode_init(esp_bt_controller_config_t *cfg) { /* Internal 136kHz RC oscillator */ - if (esp32s3_rtc_clk_slow_freq_get() == + if (rtc_clk_slow_src_get() == SOC_RTC_SLOW_CLK_SRC_RC_SLOW) { wlwarn("Internal 136kHz RC oscillator. The accuracy of " @@ -3082,7 +2967,7 @@ static void coex_bt_wakeup_request_end(void) static IRAM_ATTR int64_t get_time_us_wrapper(void) { - return (int64_t)esp32s3_rt_timer_time_us(); + return (int64_t)esp_hr_timer_time_us(); } /**************************************************************************** @@ -3159,75 +3044,6 @@ uint32_t get_ble_controller_free_heap_size(void) return mm_heapfree(USR_HEAP); } -/**************************************************************************** - * Other Functions - ****************************************************************************/ - -int32_t esp_ble_to_errno(int err) -{ - int ret; - - if (err < ESP_ERR_WIFI_BASE) - { - /* Unmask component error bits */ - - ret = err & 0xfff; - - switch (ret) - { - case ESP_OK: - ret = OK; - break; - case ESP_ERR_NO_MEM: - ret = -ENOMEM; - break; - - case ESP_ERR_INVALID_ARG: - ret = -EINVAL; - break; - - case ESP_ERR_INVALID_STATE: - ret = -EIO; - break; - - case ESP_ERR_INVALID_SIZE: - ret = -EINVAL; - break; - - case ESP_ERR_NOT_FOUND: - ret = -ENOSYS; - break; - - case ESP_ERR_NOT_SUPPORTED: - ret = -ENOSYS; - break; - - case ESP_ERR_TIMEOUT: - ret = -ETIMEDOUT; - break; - - case ESP_ERR_INVALID_MAC: - ret = -EINVAL; - break; - - default: - ret = ERROR; - break; - } - } - else - { - ret = ERROR; - } - - if (ret != OK) - { - wlerr("ERROR: %s\n", esp_err_to_name(err)); - } - - return ret; -} - /**************************************************************************** * Name: esp32s3_bt_controller_init * @@ -3250,13 +3066,7 @@ int esp32s3_bt_controller_init(void) int i; int err; - sq_init(&g_ble_int_flags_free); - sq_init(&g_ble_int_flags_used); - - for (i = 0; i < NR_IRQSTATE_FLAGS; i++) - { - sq_addlast((sq_entry_t *)&g_ble_int_flags[i], &g_ble_int_flags_free); - } + g_ble_int_count = 0; if (g_btdm_controller_status != ESP_BT_CONTROLLER_STATUS_IDLE) { @@ -3381,9 +3191,9 @@ int esp32s3_bt_controller_init(void) error: - bt_controller_deinit_internal (); + bt_controller_deinit_internal(); - return esp_ble_to_errno(err); + return esp_wifi_to_errno(err); } /**************************************************************************** diff --git a/arch/xtensa/src/esp32s3/esp32s3_clockconfig.c b/arch/xtensa/src/esp32s3/esp32s3_clockconfig.c deleted file mode 100644 index 0ff404b25a93f..0000000000000 --- a/arch/xtensa/src/esp32s3/esp32s3_clockconfig.c +++ /dev/null @@ -1,271 +0,0 @@ -/**************************************************************************** - * arch/xtensa/src/esp32s3/esp32s3_clockconfig.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include "xtensa.h" -#include "esp_attr.h" -#include "hardware/esp32s3_soc.h" -#include "hardware/esp32s3_uart.h" -#include "hardware/esp32s3_system.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define DEFAULT_CPU_FREQ 80 - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -enum cpu_freq_e -{ - CPU_80M = 0, - CPU_160M = 1, - CPU_240M = 2, -}; - -enum cpu_clksrc_e -{ - XTAL_CLK, - PLL_CLK, - FOSC_CLK -}; - -enum pll_freq_e -{ - PLL_320, - PLL_480 -}; - -/**************************************************************************** - * ROM Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: ets_update_cpu_frequency - * - * Description: - * Set the real CPU ticks per us to the ets, so that ets_delay_us will be - * accurate. Call this function when CPU frequency is changed. - * - * Input Parameters: - * ticks_per_us - CPU ticks per us. - * - * Returned Value: - * None - * - ****************************************************************************/ - -extern void ets_update_cpu_frequency(uint32_t ticks_per_us); - -/**************************************************************************** - * Name: ets_get_cpu_frequency - * - * Description: - * Get the real CPU ticks per us to the ets. - * This function do not return real CPU ticks per us, just the record in - * ets. It can be used to check with the real CPU frequency. - * - * Input Parameters: - * None. - * - * Returned Value: - * CPU ticks per us record in ets. - * - ****************************************************************************/ - -extern uint32_t ets_get_cpu_frequency(void); - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32s3_cpuclksrc - * - * Description: - * Select a clock source for CPU clock. - * - * Input Parameters: - * src - Any source from cpu_clksrc_e. - * - * Returned Value: - * None - * - ****************************************************************************/ - -static inline void esp32s3_cpuclksrc(enum cpu_clksrc_e src) -{ - uint32_t value; - value = VALUE_TO_FIELD(src, SYSTEM_SOC_CLK_SEL); - modifyreg32(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL_M, value); -} - -/**************************************************************************** - * Name: esp32s3_cpudiv - * - * Description: - * Select a divider for the CPU clk. - * NOTE: The divider is not necessarily the real divisor. See TRM for the - * equivalences. - * - * Input Parameters: - * divider - A value between 0 to 2. - * - * Returned Value: - * None - * - ****************************************************************************/ - -static inline void esp32s3_cpudiv(uint8_t divider) -{ - uint32_t value; - value = VALUE_TO_FIELD(divider, SYSTEM_CPUPERIOD_SEL); - modifyreg32(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPUPERIOD_SEL_M, value); -} - -/**************************************************************************** - * Name: esp32s3_pllfreqsel - * - * Description: - * Select the PLL frequency. - * - * Input Parameters: - * freq - Any clock from enum pll_freq_e - * - * Returned Value: - * None - ****************************************************************************/ - -static inline void esp32s3_pllfreqsel(enum pll_freq_e freq) -{ - uint32_t value; - value = VALUE_TO_FIELD(freq, SYSTEM_PLL_FREQ_SEL); - modifyreg32(SYSTEM_CPU_PER_CONF_REG, SYSTEM_PLL_FREQ_SEL_M, value); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32s3_update_cpu_freq - * - * Description: - * Set the real CPU ticks per us to the ets, so that ets_delay_us - * will be accurate. Call this function when CPU frequency is changed. - * - * Input Parameters: - * ticks_per_us - CPU ticks per us - * - * Returned Value: - * None - * - ****************************************************************************/ - -void IRAM_ATTR esp32s3_update_cpu_freq(uint32_t ticks_per_us) -{ - /* Update scale factors used by esp_rom_delay_us */ - - ets_update_cpu_frequency(ticks_per_us); -} - -/**************************************************************************** - * Name: esp32s3_set_cpu_freq - * - * Description: - * Switch to one of PLL-based frequencies. - * - * Input Parameters: - * cpu_freq_mhz - Target CPU frequency - * - * Returned Value: - * None - * - ****************************************************************************/ - -void IRAM_ATTR esp32s3_set_cpu_freq(int cpu_freq_mhz) -{ - switch (cpu_freq_mhz) - { - case 80: - /* 80 MHz is obtained from the 480 MHz PLL. - * In this case CPU_CLK = PLL_CLK / 6. Config the PLL as 480 MHz - * with a 6 divider and set the source clock as PLL_CLK. - */ - - esp32s3_cpudiv(0); - break; - - case 160: - /* 160 MHz is obtained from the 480 MHz PLL. - * In this case CPU_CLK = PLL_CLK / 3. Config the PLL as 480 MHz - * with a 3 divider and set the source clock as PLL_CLK. - */ - - esp32s3_cpudiv(1); - break; - - case 240: - /* 240 MHz is obtained from the 480 MHz PLL. - * In this case CPU_CLK = PLL_CLK / 2. Config the PLL as 480 MHz - * with a 2 divider and set the source clock as PLL_CLK. - */ - - esp32s3_cpudiv(2); - break; - - default: - - /* Unsupported clock config. */ - - return; - } - - esp32s3_pllfreqsel(PLL_480); - esp32s3_cpuclksrc(PLL_CLK); - esp32s3_update_cpu_freq(cpu_freq_mhz); -} - -/**************************************************************************** - * Name: esp32s3_clockconfig - * - * Description: - * Called to initialize the ESP32-S3. This does whatever setup is needed to - * put the SoC in a usable state. This includes the initialization of - * clocking using the settings in board.h. - * - ****************************************************************************/ - -void esp32s3_clockconfig(void) -{ - /* Configure the CPU frequency */ - - esp32s3_set_cpu_freq(CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ); -} diff --git a/arch/xtensa/src/esp32s3/esp32s3_clockconfig.h b/arch/xtensa/src/esp32s3/esp32s3_clockconfig.h deleted file mode 100644 index c93c20fb8ba91..0000000000000 --- a/arch/xtensa/src/esp32s3/esp32s3_clockconfig.h +++ /dev/null @@ -1,90 +0,0 @@ -/**************************************************************************** - * arch/xtensa/src/esp32s3/esp32s3_clockconfig.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_CLOCKCONFIG_H -#define __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_CLOCKCONFIG_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -#include "esp_private/esp_clk.h" - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32s3_update_cpu_freq - * - * Description: - * Set the real CPU ticks per us to the ets, so that ets_delay_us - * will be accurate. Call this function when CPU frequency is changed. - * - * Input Parameters: - * ticks_per_us - CPU ticks per us - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp32s3_update_cpu_freq(uint32_t ticks_per_us); - -/**************************************************************************** - * Name: esp32s3_set_cpu_freq - * - * Description: - * Switch to one of PLL-based frequencies. - * Current frequency can be XTAL or PLL. - * - * Input Parameters: - * cpu_freq_mhz - new CPU frequency - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp32s3_set_cpu_freq(int cpu_freq_mhz); - -/**************************************************************************** - * Name: esp32s3_clockconfig - * - * Description: - * Called to initialize the ESP32-S3. This does whatever setup is needed to - * put the SoC in a usable state. This includes the initialization of - * clocking using the settings in board.h. - * - * Input Parameters: - * None. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp32s3_clockconfig(void); - -#endif /* __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_CLOCKCONFIG_H */ diff --git a/arch/xtensa/src/esp32s3/esp32s3_cpustart.c b/arch/xtensa/src/esp32s3/esp32s3_cpustart.c index afb48b79b0efc..210aa4b84a017 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_cpustart.c +++ b/arch/xtensa/src/esp32s3/esp32s3_cpustart.c @@ -33,15 +33,22 @@ #include #include #include +#include #include "sched/sched.h" #include "xtensa.h" -#include "esp32s3_irq.h" +#include "esp_irq.h" #include "esp32s3_region.h" #include "esp32s3_smp.h" -#include "hardware/esp32s3_rtccntl.h" +#include "esp32s3_start.h" +#include "soc/rtc_cntl_reg.h" #include "hardware/esp32s3_system.h" +#include "esp_attr.h" +#include "esp_cpu.h" +#include "rom/ets_sys.h" +#include "soc/interrupt_core1_reg.h" + /**************************************************************************** * Private Data ****************************************************************************/ @@ -60,23 +67,25 @@ extern void ets_set_appcpu_boot_addr(uint32_t start); /**************************************************************************** * Name: xtensa_attach_fromcpu0_interrupt + * + * Description: + * Attach the inter-CPU interrupt for CPU1 WITHOUT using malloc. + * This is called during early CPU1 boot when malloc is not available. + * We use direct register programming instead of esp_intr_alloc. + * ****************************************************************************/ -static inline void xtensa_attach_fromcpu0_interrupt(void) +static inline void IRAM_ATTR xtensa_attach_fromcpu0_interrupt(void) { int cpuint; /* Connect all CPU peripheral source to allocated CPU interrupt */ - cpuint = esp32s3_setup_irq(1, ESP32S3_PERIPH_INT_FROM_CPU0, 1, - ESP32S3_CPUINT_LEVEL); + cpuint = esp_setup_irq(ESP32S3_PERIPH_INT_FROM_CPU0, 1, + ESP_IRQ_TRIGGER_LEVEL, esp32s3_fromcpu0_interrupt, + NULL); DEBUGASSERT(cpuint >= 0); - /* Attach the inter-CPU interrupt. */ - - irq_attach(ESP32S3_IRQ_INT_FROM_CPU0, (xcpt_t)esp32s3_fromcpu0_interrupt, - NULL); - /* Enable the inter 0 CPU interrupts. */ up_enable_irq(ESP32S3_IRQ_INT_FROM_CPU0); @@ -102,7 +111,7 @@ static inline void xtensa_attach_fromcpu0_interrupt(void) * ****************************************************************************/ -void xtensa_appcpu_start(void) +void IRAM_ATTR xtensa_appcpu_start(void) { struct tcb_s *tcb = this_task(); register uint32_t sp; @@ -125,10 +134,6 @@ void xtensa_appcpu_start(void) sched_note_cpu_started(tcb); #endif - /* Signal to the PRO CPU that the APP CPU has started. */ - - g_appcpu_started = true; - /* Move CPU0 exception vectors to IRAM */ __asm__ __volatile__ ("wsr %0, vecbase\n"::"r" (_init_start)); @@ -139,15 +144,13 @@ void xtensa_appcpu_start(void) /* Initialize CPU interrupts */ - esp32s3_cpuint_initialize(); + esp_cpuint_initialize(); /* Attach and enable the inter-CPU interrupt */ xtensa_attach_fromcpu0_interrupt(); - /* Enable the software interrupt */ - - up_enable_irq(XTENSA_IRQ_SWINT); + /* NOTE: Intentionally not enabling the software interrupt here */ #ifndef CONFIG_SUPPRESS_INTERRUPTS /* And Enable interrupts */ @@ -159,6 +162,12 @@ void xtensa_appcpu_start(void) xtensa_set_cpenable(CONFIG_XTENSA_CP_INITSET); #endif + sys_startup_fn(); + + /* Signal to the PRO CPU that the APP CPU has started. */ + + g_appcpu_started = true; + /* Then switch contexts. This instantiates the exception context of the * tcb at the head of the assigned task list. In this case, this should * be the CPUs NULL task. @@ -218,13 +227,13 @@ int up_cpu_start(int cpu) regval = getreg32(SYSTEM_CORE_1_CONTROL_0_REG); if ((regval & SYSTEM_CONTROL_CORE_1_CLKGATE_EN) == 0) { - regval = getreg32(RTC_CNTL_RTC_SW_CPU_STALL_REG); + regval = getreg32(RTC_CNTL_SW_CPU_STALL_REG); regval &= ~RTC_CNTL_SW_STALL_APPCPU_C1_M; - putreg32(regval, RTC_CNTL_RTC_SW_CPU_STALL_REG); + putreg32(regval, RTC_CNTL_SW_CPU_STALL_REG); - regval = getreg32(RTC_CNTL_RTC_OPTIONS0_REG); + regval = getreg32(RTC_CNTL_OPTIONS0_REG); regval &= ~RTC_CNTL_SW_STALL_APPCPU_C0_M; - putreg32(regval, RTC_CNTL_RTC_OPTIONS0_REG); + putreg32(regval, RTC_CNTL_OPTIONS0_REG); /* Enable clock gating for the APP CPU */ @@ -259,4 +268,3 @@ int up_cpu_start(int cpu) return OK; } - diff --git a/arch/xtensa/src/esp32s3/esp32s3_dma.c b/arch/xtensa/src/esp32s3/esp32s3_dma.c index 81310b8feda7b..4afc9cbafc7b7 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_dma.c +++ b/arch/xtensa/src/esp32s3/esp32s3_dma.c @@ -45,7 +45,7 @@ #include "hardware/esp32s3_soc.h" #include "hardware/esp32s3_system.h" -#include "soc/gdma_periph.h" +#include "hal/gdma_periph.h" #include "hal/gdma_hal.h" #include "hal/gdma_types.h" #include "hal/gdma_ll.h" diff --git a/arch/xtensa/src/esp32s3/esp32s3_freerun.c b/arch/xtensa/src/esp32s3/esp32s3_freerun.c index 0c554fbdeb904..d4a364c321f35 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_freerun.c +++ b/arch/xtensa/src/esp32s3/esp32s3_freerun.c @@ -36,9 +36,9 @@ #include #include -#include "esp32s3_clockconfig.h" +#include "esp_clk.h" #include "esp32s3_freerun.h" -#include "esp32s3_gpio.h" +#include "esp_gpio.h" #ifdef CONFIG_ESP32S3_FREERUN diff --git a/arch/xtensa/src/esp32s3/esp32s3_gpio.c b/arch/xtensa/src/esp32s3/esp32s3_gpio.c deleted file mode 100644 index 05159a63949c8..0000000000000 --- a/arch/xtensa/src/esp32s3/esp32s3_gpio.c +++ /dev/null @@ -1,626 +0,0 @@ -/**************************************************************************** - * arch/xtensa/src/esp32s3/esp32s3_gpio.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include - -#include "xtensa.h" - -#include "soc/soc_caps.h" - -#include "esp32s3_gpio.h" -#include "esp32s3_irq.h" -#include "hardware/esp32s3_gpio.h" -#include "hardware/esp32s3_iomux.h" -#include "hardware/esp32s3_usb_serial_jtag.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define ESP32S3_NPINS 49 - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -#ifdef CONFIG_ESP32S3_GPIO_IRQ -static int g_gpio_cpuint; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: is_valid_gpio - * - * Description: - * Check if the requested pin is a valid GPIO pin. - * - * Input Parameters: - * pin - Pin to be checked for validity. - * - * Returned Value: - * True if the requested pin is a valid GPIO pin, false otherwise. - * - ****************************************************************************/ - -static inline bool is_valid_gpio(uint32_t pin) -{ - /* ESP32-S3 has 45 GPIO pins numbered from 0 to 21 and 26 to 48 */ - - return pin <= 21 || (pin >= 26 && pin < ESP32S3_NPINS); -} - -/**************************************************************************** - * Name: gpio_dispatch - * - * Description: - * Second level dispatch for GPIO interrupt handling. - * - * Input Parameters: - * irq - GPIO IRQ number. - * status - Value from the GPIO interrupt status clear register. - * regs - Saved CPU context. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -#ifdef CONFIG_ESP32S3_GPIO_IRQ -static void gpio_dispatch(int irq, uint32_t status, uint32_t *regs) -{ - uint32_t mask; - int i; - - /* Check each bit in the status register */ - - for (i = 0; i < 32 && status != 0; i++) - { - /* Check if there is an interrupt pending for this pin */ - - mask = UINT32_C(1) << i; - if ((status & mask) != 0) - { - /* Yes... perform the second level dispatch */ - - irq_dispatch(irq + i, regs); - - /* Clear the bit in the status so that we might execute this loop - * sooner. - */ - - status &= ~mask; - } - } -} -#endif - -/**************************************************************************** - * Name: gpio_interrupt - * - * Description: - * GPIO interrupt handler. - * - * Input Parameters: - * irq - Identifier of the interrupt request. - * context - Context data from the ISR. - * arg - Opaque pointer to the internal driver state structure. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on failure. - * - ****************************************************************************/ - -#ifdef CONFIG_ESP32S3_GPIO_IRQ -static int gpio_interrupt(int irq, void *context, void *arg) -{ - uint32_t status; - - /* Read and clear the lower GPIO interrupt status */ - - status = getreg32(GPIO_STATUS_REG); - putreg32(status, GPIO_STATUS_W1TC_REG); - - /* Dispatch pending interrupts in the lower GPIO status register */ - - gpio_dispatch(ESP32S3_FIRST_GPIOIRQ, status, (uint32_t *)context); - - /* Read and clear the upper GPIO interrupt status */ - - status = getreg32(GPIO_STATUS1_REG); - putreg32(status, GPIO_STATUS1_W1TC_REG); - - /* Dispatch pending interrupts in the lower GPIO status register */ - - gpio_dispatch(ESP32S3_FIRST_GPIOIRQ + 32, status, (uint32_t *)context); - return OK; -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32s3_configgpio - * - * Description: - * Configure a GPIO pin based on encoded pin attributes. - * - * Input Parameters: - * pin - GPIO pin to be configured. - * attr - Attributes to be configured for the selected GPIO pin. - * The following attributes are accepted: - * - Direction (OUTPUT or INPUT) - * - Pull (PULLUP, PULLDOWN or OPENDRAIN) - * - Function (if not provided, assume function GPIO by - * default) - * - Drive strength (if not provided, assume DRIVE_2 by - * default) - * - * Returned Value: - * Zero (OK) on success, or -1 (ERROR) in case of failure. - * - ****************************************************************************/ - -int esp32s3_configgpio(uint32_t pin, gpio_pinattr_t attr) -{ - uintptr_t regaddr; - uint32_t func; - uint32_t cntrl; - uint32_t pin2func; - - DEBUGASSERT(is_valid_gpio(pin)); - - func = 0; - cntrl = 0; - - /* if pin 19 or 20 disable the USB/JTAG function and pull-up */ - - if (pin == 19 || pin == 20) - { - uint32_t regval; - regval = getreg32(USB_SERIAL_JTAG_CONF0_REG); - regval &= ~(USB_SERIAL_JTAG_USB_PAD_ENABLE | - USB_SERIAL_JTAG_DP_PULLUP); - putreg32(regval, USB_SERIAL_JTAG_CONF0_REG); - } - - /* Handle input pins */ - - if ((attr & INPUT) != 0) - { - if (pin < 32) - { - putreg32((UINT32_C(1) << pin), GPIO_ENABLE_W1TC_REG); - } - else - { - putreg32((UINT32_C(1) << (pin - 32)), GPIO_ENABLE1_W1TC_REG); - } - - /* Input enable */ - - func |= FUN_IE; - - if ((attr & PULLUP) != 0) - { - func |= FUN_PU; - } - else if ((attr & PULLDOWN) != 0) - { - func |= FUN_PD; - } - } - - /* Handle output pins */ - - if ((attr & OUTPUT) != 0) - { - if (pin < 32) - { - putreg32((UINT32_C(1) << pin), GPIO_ENABLE_W1TS_REG); - } - else - { - putreg32((UINT32_C(1) << (pin - 32)), GPIO_ENABLE1_W1TS_REG); - } - } - - /* Configure the pad's function */ - - if ((attr & FUNCTION_MASK) != 0) - { - uint32_t val = ((attr & FUNCTION_MASK) >> FUNCTION_SHIFT) - 1; - func |= val << MCU_SEL_S; - } - else - { - /* Function not provided, assuming function GPIO by default */ - - func |= (uint32_t)(PIN_FUNC_GPIO << MCU_SEL_S); - } - - /* Configure the pad's drive strength */ - - if ((attr & DRIVE_MASK) != 0) - { - uint32_t val = ((attr & DRIVE_MASK) >> DRIVE_SHIFT) - 1; - func |= val << FUN_DRV_S; - } - else - { - /* Drive strength not provided, assuming strength 2 by default */ - - func |= UINT32_C(2) << FUN_DRV_S; - } - - if ((attr & OPEN_DRAIN) != 0) - { - cntrl |= (1 << GPIO_PIN_PAD_DRIVER_S); - } - - /* Set the pin function to its register */ - - pin2func = (pin + 1) * 4; - regaddr = REG_IO_MUX_BASE + pin2func; - putreg32(func, regaddr); - - regaddr = GPIO_REG(pin); - putreg32(cntrl, regaddr); - return OK; -} - -/**************************************************************************** - * Name: esp32s3_gpiowrite - * - * Description: - * Write one or zero to the selected GPIO pin. - * - * Input Parameters: - * pin - GPIO pin to be written. - * value - Value to be written to the GPIO pin. True will output - * 1 (one) to the GPIO, while false will output 0 (zero). - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp32s3_gpiowrite(int pin, bool value) -{ - DEBUGASSERT(is_valid_gpio(pin)); - - if (value) - { - if (pin < 32) - { - putreg32(UINT32_C(1) << pin, GPIO_OUT_W1TS_REG); - } - else - { - putreg32(UINT32_C(1) << (pin - 32), GPIO_OUT1_W1TS_REG); - } - } - else - { - if (pin < 32) - { - putreg32(UINT32_C(1) << pin, GPIO_OUT_W1TC_REG); - } - else - { - putreg32(UINT32_C(1) << (pin - 32), GPIO_OUT1_W1TC_REG); - } - } -} - -/**************************************************************************** - * Name: esp32s3_gpioread - * - * Description: - * Read one or zero from the selected GPIO pin. - * - * Input Parameters: - * pin - GPIO pin to be read. - * - * Returned Value: - * True in case the read value is 1 (one). If 0 (zero), then false will be - * returned. - * - ****************************************************************************/ - -bool esp32s3_gpioread(int pin) -{ - uint32_t regval; - - DEBUGASSERT(is_valid_gpio(pin)); - - if (pin < 32) - { - regval = getreg32(GPIO_IN_REG); - return ((regval >> pin) & 1) != 0; - } - else - { - regval = getreg32(GPIO_IN1_REG); - return ((regval >> (pin - 32)) & 1) != 0; - } -} - -/**************************************************************************** - * Name: esp32s3_gpioirqinitialize - * - * Description: - * Initialize logic to support a second level of interrupt decoding for - * GPIO pins. - * - * Input Parameters: - * None. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -#ifdef CONFIG_ESP32S3_GPIO_IRQ -void esp32s3_gpioirqinitialize(void) -{ - int cpu; - - /* Setup the GPIO interrupt. */ - - cpu = this_cpu(); - - g_gpio_cpuint = esp32s3_setup_irq(cpu, ESP32S3_PERIPH_GPIO_INT_CPU, 1, - ESP32S3_CPUINT_LEVEL); - DEBUGASSERT(g_gpio_cpuint >= 0); - - /* Attach and enable the interrupt handler */ - - DEBUGVERIFY(irq_attach(ESP32S3_IRQ_GPIO_INT_CPU, gpio_interrupt, NULL)); - up_enable_irq(ESP32S3_IRQ_GPIO_INT_CPU); -} -#endif - -/**************************************************************************** - * Name: esp32s3_gpioirqenable - * - * Description: - * Enable the interrupt for the specified GPIO IRQ. - * - * Input Parameters: - * irq - Identifier of the interrupt request. - * intrtype - Interrupt type, select from gpio_intrtype_t. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -#ifdef CONFIG_ESP32S3_GPIO_IRQ -void esp32s3_gpioirqenable(int irq, gpio_intrtype_t intrtype) -{ - uintptr_t regaddr; - uint32_t regval; - int pin; - - DEBUGASSERT(irq >= ESP32S3_FIRST_GPIOIRQ && irq <= ESP32S3_LAST_GPIOIRQ); - - /* Convert the IRQ number to a pin number */ - - pin = ESP32S3_IRQ2PIN(irq); - - /* Disable the GPIO interrupt during the configuration. */ - - up_disable_irq(ESP32S3_IRQ_GPIO_INT_CPU); - - /* Get the address of the GPIO PIN register for this pin */ - - regaddr = GPIO_REG(pin); - regval = getreg32(regaddr); - regval &= ~(GPIO_PIN0_INT_ENA_M | GPIO_PIN0_INT_TYPE_M); - - /* Set the pin ENA field. - * On ESP32-S3, CPU0 and CPU1 share the same interrupt enable bit. - */ - - regval |= GPIO_PIN0_INT_ENA_M; - regval |= (uint32_t)intrtype << GPIO_PIN0_INT_TYPE_S; - putreg32(regval, regaddr); - - /* Clear pending GPIO interrupt status before enable IRQ */ - - if (pin < 32) - { - putreg32(1 << pin, GPIO_STATUS_W1TC_REG); - } - else - { - putreg32(1 << (pin - 32), GPIO_STATUS1_W1TC_REG); - } - - /* Configuration done. Re-enable the GPIO interrupt. */ - - up_enable_irq(ESP32S3_IRQ_GPIO_INT_CPU); -} -#endif - -/**************************************************************************** - * Name: esp32s3_gpioirqdisable - * - * Description: - * Disable the interrupt for the specified GPIO IRQ. - * - * Input Parameters: - * irq - Identifier of the interrupt request. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -#ifdef CONFIG_ESP32S3_GPIO_IRQ -void esp32s3_gpioirqdisable(int irq) -{ - uintptr_t regaddr; - uint32_t regval; - int pin; - - DEBUGASSERT(irq >= ESP32S3_FIRST_GPIOIRQ && irq <= ESP32S3_LAST_GPIOIRQ); - - /* Convert the IRQ number to a pin number */ - - pin = ESP32S3_IRQ2PIN(irq); - - /* Disable the GPIO interrupt during the configuration. */ - - up_disable_irq(ESP32S3_IRQ_GPIO_INT_CPU); - - /* Reset the pin ENA and TYPE fields */ - - regaddr = GPIO_REG(pin); - regval = getreg32(regaddr); - regval &= ~(GPIO_PIN0_INT_ENA_M | GPIO_PIN0_INT_TYPE_M); - putreg32(regval, regaddr); - - /* Clear pending GPIO interrupt status before enable IRQ */ - - if (pin < 32) - { - putreg32(1 << pin, GPIO_STATUS_W1TC_REG); - } - else - { - putreg32(1 << (pin - 32), GPIO_STATUS1_W1TC_REG); - } - - /* Configuration done. Re-enable the GPIO interrupt. */ - - up_enable_irq(ESP32S3_IRQ_GPIO_INT_CPU); -} -#endif - -/**************************************************************************** - * Name: esp32s3_gpio_matrix_in - * - * Description: - * Set GPIO input to a signal. - * NOTE: one GPIO can receive inputs from several signals. - * - * Input Parameters: - * pin - GPIO pin to be configured. - * - If pin == 0x3c, cancel input to the signal, input 0 - * to signal. - * - If pin == 0x3a, input nothing to signal. - * - If pin == 0x38, cancel input to the signal, input 1 - * to signal. - * signal_idx - Signal index. - * inv - Flag indicating whether the signal is inverted. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp32s3_gpio_matrix_in(uint32_t pin, uint32_t signal_idx, bool inv) -{ - uint32_t regaddr = GPIO_FUNC0_IN_SEL_CFG_REG + (signal_idx * 4); - uint32_t regval = pin << GPIO_FUNC0_IN_SEL_S; - - if (inv) - { - regval |= GPIO_FUNC0_IN_INV_SEL; - } - - if (pin != 0x3a) - { - regval |= GPIO_SIG0_IN_SEL; - } - - putreg32(regval, regaddr); -} - -/**************************************************************************** - * Name: esp32s3_gpio_matrix_out - * - * Description: - * Set signal output to GPIO. - * NOTE: one signal can output to several GPIOs. - * - * Input Parameters: - * pin - GPIO pin to be configured. - * signal_idx - Signal index. - * - If signal_idx == 0x100, cancel output to the GPIO. - * out_inv - Flag indicating whether the signal output is inverted. - * oen_inv - Flag indicating whether the signal output enable is - * inverted. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp32s3_gpio_matrix_out(uint32_t pin, uint32_t signal_idx, bool out_inv, - bool oen_inv) -{ - uint32_t regaddr = GPIO_FUNC0_OUT_SEL_CFG_REG + (pin * 4); - uint32_t regval = signal_idx << GPIO_FUNC0_OUT_SEL_S; - - DEBUGASSERT(is_valid_gpio(pin)); - - if (pin < 32) - { - putreg32((UINT32_C(1) << pin), GPIO_ENABLE_W1TS_REG); - } - else - { - putreg32((UINT32_C(1) << (pin - 32)), GPIO_ENABLE1_W1TS_REG); - } - - if (out_inv) - { - regval |= GPIO_FUNC0_OUT_INV_SEL; - } - - if (oen_inv) - { - regval |= GPIO_FUNC0_OEN_INV_SEL; - } - - putreg32(regval, regaddr); -} - diff --git a/arch/xtensa/src/esp32s3/esp32s3_gpio.h b/arch/xtensa/src/esp32s3/esp32s3_gpio.h deleted file mode 100644 index 8bcdafba85f42..0000000000000 --- a/arch/xtensa/src/esp32s3/esp32s3_gpio.h +++ /dev/null @@ -1,325 +0,0 @@ -/**************************************************************************** - * arch/xtensa/src/esp32s3/esp32s3_gpio.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_GPIO_H -#define __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_GPIO_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define MATRIX_DETACH_OUT_SIG 0x100 /* Detach an OUTPUT signal */ -#define MATRIX_DETACH_IN_LOW_PIN 0x3c /* Detach non-inverted INPUT signal */ -#define MATRIX_DETACH_IN_LOW_HIGH 0x38 /* Detach inverted INPUT signal */ - -/* Bit-encoded input to esp32s3_configgpio() ********************************/ - -/* Encoded pin attributes used with esp32s3_configgpio() - * - * 8 7 6 5 4 3 2 1 0 - * -- -- -- -- -- -- -- -- -- - * FN FN FN OD PD PU F O I - */ - -#define MODE_SHIFT 0 -#define MODE_MASK (7 << MODE_SHIFT) -# define INPUT (1 << 0) -# define OUTPUT (1 << 1) -# define FUNCTION (1 << 2) - -#define PULL_SHIFT 3 -#define PULL_MASK (7 << PULL_SHIFT) -# define PULLUP (1 << 3) -# define PULLDOWN (1 << 4) -# define OPEN_DRAIN (1 << 5) - -#define FUNCTION_SHIFT 6 -#define FUNCTION_MASK (7 << FUNCTION_SHIFT) -# define FUNCTION_1 (1 << FUNCTION_SHIFT) -# define FUNCTION_2 (2 << FUNCTION_SHIFT) -# define FUNCTION_3 (3 << FUNCTION_SHIFT) -# define FUNCTION_4 (4 << FUNCTION_SHIFT) -# define FUNCTION_5 (5 << FUNCTION_SHIFT) -# define FUNCTION_6 (6 << FUNCTION_SHIFT) - -#define DRIVE_SHIFT 9 -#define DRIVE_MASK (7 << DRIVE_SHIFT) -# define DRIVE_0 (1 << DRIVE_SHIFT) -# define DRIVE_1 (2 << DRIVE_SHIFT) -# define DRIVE_2 (3 << DRIVE_SHIFT) -# define DRIVE_3 (4 << DRIVE_SHIFT) - -#define INPUT_PULLUP (INPUT | PULLUP) -#define INPUT_PULLDOWN (INPUT | PULLDOWN) -#define OUTPUT_OPEN_DRAIN (OUTPUT | OPEN_DRAIN) -#define INPUT_FUNCTION (INPUT | FUNCTION) -# define INPUT_FUNCTION_1 (INPUT_FUNCTION | FUNCTION_1) -# define INPUT_FUNCTION_2 (INPUT_FUNCTION | FUNCTION_2) -# define INPUT_FUNCTION_3 (INPUT_FUNCTION | FUNCTION_3) -# define INPUT_FUNCTION_4 (INPUT_FUNCTION | FUNCTION_4) -# define INPUT_FUNCTION_5 (INPUT_FUNCTION | FUNCTION_5) -# define INPUT_FUNCTION_6 (INPUT_FUNCTION | FUNCTION_6) -#define OUTPUT_FUNCTION (OUTPUT | FUNCTION) -# define OUTPUT_FUNCTION_1 (OUTPUT_FUNCTION | FUNCTION_1) -# define OUTPUT_FUNCTION_2 (OUTPUT_FUNCTION | FUNCTION_2) -# define OUTPUT_FUNCTION_3 (OUTPUT_FUNCTION | FUNCTION_3) -# define OUTPUT_FUNCTION_4 (OUTPUT_FUNCTION | FUNCTION_4) -# define OUTPUT_FUNCTION_5 (OUTPUT_FUNCTION | FUNCTION_5) -# define OUTPUT_FUNCTION_6 (OUTPUT_FUNCTION | FUNCTION_6) - -/* Interrupt type used with esp32s3_gpioirqenable() */ - -#define DISABLED 0x00 -#define RISING 0x01 -#define FALLING 0x02 -#define CHANGE 0x03 -#define ONLOW 0x04 -#define ONHIGH 0x05 - -/* Check whether it is a valid GPIO number */ - -#define GPIO_IS_VALID_GPIO(gpio_num) ((gpio_num >= 0) && \ - (((1ULL << (gpio_num)) & \ - SOC_GPIO_VALID_GPIO_MASK) != 0)) - -/* Check whether it can be a valid GPIO number of output mode */ - -#define GPIO_IS_VALID_OUTPUT_GPIO(gpio_num) \ - ((gpio_num >= 0) && \ - (((1ULL << (gpio_num)) & SOC_GPIO_VALID_OUTPUT_GPIO_MASK) != 0)) - -/* Check whether it can be a valid digital I/O pad */ - -#define GPIO_IS_VALID_DIGITAL_IO_PAD(gpio_num) \ - ((gpio_num >= 0) && \ - (((1ULL << (gpio_num)) & SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK) != 0)) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -/* Must be big enough to hold the above encodings */ - -typedef uint16_t gpio_pinattr_t; -typedef uint8_t gpio_intrtype_t; - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32s3_gpioirqinitialize - * - * Description: - * Initialize logic to support a second level of interrupt decoding for - * GPIO pins. - * - * Input Parameters: - * None. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -#ifdef CONFIG_ESP32S3_GPIO_IRQ -void esp32s3_gpioirqinitialize(void); -#else -# define esp32s3_gpioirqinitialize() -#endif - -/**************************************************************************** - * Name: esp32s3_configgpio - * - * Description: - * Configure a GPIO pin based on encoded pin attributes. - * - * Input Parameters: - * pin - GPIO pin to be configured. - * attr - Attributes to be configured for the selected GPIO pin. - * The following attributes are accepted: - * - Direction (OUTPUT or INPUT) - * - Pull (PULLUP, PULLDOWN or OPENDRAIN) - * - Function (if not provided, assume function GPIO by - * default) - * - Drive strength (if not provided, assume DRIVE_2 by - * default) - * - * Returned Value: - * Zero (OK) on success, or -1 (ERROR) in case of failure. - * - ****************************************************************************/ - -int esp32s3_configgpio(uint32_t pin, gpio_pinattr_t attr); - -/**************************************************************************** - * Name: esp32s3_gpiowrite - * - * Description: - * Write one or zero to the selected GPIO pin. - * - * Input Parameters: - * pin - GPIO pin to be written. - * value - Value to be written to the GPIO pin. True will output - * 1 (one) to the GPIO, while false will output 0 (zero). - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp32s3_gpiowrite(int pin, bool value); - -/**************************************************************************** - * Name: esp32s3_gpioread - * - * Description: - * Read one or zero from the selected GPIO pin. - * - * Input Parameters: - * pin - GPIO pin to be read. - * - * Returned Value: - * True in case the read value is 1 (one). If 0 (zero), then false will be - * returned. - * - ****************************************************************************/ - -bool esp32s3_gpioread(int pin); - -/**************************************************************************** - * Name: esp32s3_gpioirqenable - * - * Description: - * Enable the interrupt for the specified GPIO IRQ. - * - * Input Parameters: - * irq - Identifier of the interrupt request. - * intrtype - Interrupt type, select from gpio_intrtype_t. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -#ifdef CONFIG_ESP32S3_GPIO_IRQ -void esp32s3_gpioirqenable(int irq, gpio_intrtype_t intrtype); -#else -# define esp32s3_gpioirqenable(irq,intrtype) -#endif - -/**************************************************************************** - * Name: esp32s3_gpioirqdisable - * - * Description: - * Disable the interrupt for the specified GPIO IRQ. - * - * Input Parameters: - * irq - Identifier of the interrupt request. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -#ifdef CONFIG_ESP32S3_GPIO_IRQ -void esp32s3_gpioirqdisable(int irq); -#else -# define esp32s3_gpioirqdisable(irq) -#endif - -/**************************************************************************** - * Name: esp32s3_gpio_matrix_in - * - * Description: - * Set GPIO input to a signal. - * NOTE: one GPIO can receive inputs from several signals. - * - * Input Parameters: - * pin - GPIO pin to be configured. - * - If pin == 0x3c, cancel input to the signal, input 0 - * to signal. - * - If pin == 0x3a, input nothing to signal. - * - If pin == 0x38, cancel input to the signal, input 1 - * to signal. - * signal_idx - Signal index. - * inv - Flag indicating whether the signal is inverted. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp32s3_gpio_matrix_in(uint32_t pin, uint32_t signal_idx, bool inv); - -/**************************************************************************** - * Name: esp32s3_gpio_matrix_out - * - * Description: - * Set signal output to GPIO. - * NOTE: one signal can output to several GPIOs. - * - * Input Parameters: - * pin - GPIO pin to be configured. - * signal_idx - Signal index. - * - If signal_idx == 0x100, cancel output to the GPIO. - * out_inv - Flag indicating whether the signal output is inverted. - * oen_inv - Flag indicating whether the signal output enable is - * inverted. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp32s3_gpio_matrix_out(uint32_t pin, uint32_t signal_idx, bool out_inv, - bool oen_inv); - -#ifdef __cplusplus -} -#endif -#undef EXTERN - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_GPIO_H */ diff --git a/arch/xtensa/src/esp32s3/esp32s3_i2c.c b/arch/xtensa/src/esp32s3/esp32s3_i2c.c index fdad5f4aade9f..c571bb37ee100 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_i2c.c +++ b/arch/xtensa/src/esp32s3/esp32s3_i2c.c @@ -46,9 +46,9 @@ #include -#include "esp32s3_gpio.h" +#include "esp_gpio.h" #include "esp32s3_i2c.h" -#include "esp32s3_irq.h" +#include "esp_irq.h" #include "xtensa.h" #include "hardware/esp32s3_gpio_sigmap.h" @@ -781,15 +781,15 @@ static void i2c_init(struct esp32s3_i2c_priv_s *priv) const struct esp32s3_i2c_config_s *config = priv->config; if (priv->id != ESP32S3_RTC_I2C) { - esp32s3_gpiowrite(config->scl_pin, 1); - esp32s3_configgpio(config->scl_pin, INPUT_PULLUP | OUTPUT_OPEN_DRAIN); - esp32s3_gpio_matrix_out(config->scl_pin, config->scl_outsig, 0, 0); - esp32s3_gpio_matrix_in(config->scl_pin, config->scl_insig, 0); + esp_gpiowrite(config->scl_pin, 1); + esp_configgpio(config->scl_pin, INPUT_PULLUP | OUTPUT_OPEN_DRAIN); + esp_gpio_matrix_out(config->scl_pin, config->scl_outsig, 0, 0); + esp_gpio_matrix_in(config->scl_pin, config->scl_insig, 0); - esp32s3_gpiowrite(config->sda_pin, 1); - esp32s3_configgpio(config->sda_pin, INPUT_PULLUP | OUTPUT_OPEN_DRAIN); - esp32s3_gpio_matrix_out(config->sda_pin, config->sda_outsig, 0, 0); - esp32s3_gpio_matrix_in(config->sda_pin, config->sda_insig, 0); + esp_gpiowrite(config->sda_pin, 1); + esp_configgpio(config->sda_pin, INPUT_PULLUP | OUTPUT_OPEN_DRAIN); + esp_gpio_matrix_out(config->sda_pin, config->sda_outsig, 0, 0); + esp_gpio_matrix_in(config->sda_pin, config->sda_insig, 0); /* Enable I2C hardware */ @@ -1731,8 +1731,11 @@ struct i2c_master_s *esp32s3_i2cbus_initialize(int port) /* Set up to receive peripheral interrupts on the current CPU */ priv->cpu = this_cpu(); - priv->cpuint = esp32s3_setup_irq(priv->cpu, config->periph, - 1, ESP32S3_CPUINT_LEVEL); + priv->cpuint = esp_setup_irq(config->periph, + 1, + ESP_IRQ_TRIGGER_LEVEL, + i2c_irq, + priv); if (priv->cpuint < 0) { /* Failed to allocate a CPU interrupt of this type */ @@ -1743,16 +1746,6 @@ struct i2c_master_s *esp32s3_i2cbus_initialize(int port) return NULL; } - ret = irq_attach(config->irq, i2c_irq, priv); - if (ret != OK) - { - esp32s3_teardown_irq(priv->cpu, config->periph, priv->cpuint); - priv->refs--; - - nxmutex_unlock(&priv->lock); - return NULL; - } - up_enable_irq(config->irq); } #endif @@ -1801,7 +1794,7 @@ int esp32s3_i2cbus_uninitialize(struct i2c_master_s *dev) { #ifndef CONFIG_I2C_POLLED up_disable_irq(priv->config->irq); - esp32s3_teardown_irq(priv->cpu, priv->config->periph, priv->cpuint); + esp_teardown_irq(priv->config->periph, priv->cpuint); #endif i2c_deinit(priv); diff --git a/arch/xtensa/src/esp32s3/esp32s3_irq.c b/arch/xtensa/src/esp32s3/esp32s3_irq.c deleted file mode 100644 index a47b01beb9773..0000000000000 --- a/arch/xtensa/src/esp32s3/esp32s3_irq.c +++ /dev/null @@ -1,1265 +0,0 @@ -/**************************************************************************** - * arch/xtensa/src/esp32s3/esp32s3_irq.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include -#include - -#include "xtensa.h" - -#include "esp32s3_gpio.h" -#include "esp32s3_rtc_gpio.h" -#include "esp32s3_irq.h" -#ifdef CONFIG_SMP -#include "esp32s3_smp.h" -#endif -#include "esp32s3_userspace.h" -#include "hardware/esp32s3_interrupt_core0.h" -#ifdef CONFIG_SMP -#include "hardware/esp32s3_interrupt_core1.h" -#endif -#include "hardware/esp32s3_soc.h" -#include "hardware/esp32s3_system.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Interrupt stack definitions for SMP */ - -#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 15 -# define INTSTACK_ALLOC (CONFIG_SMP_NCPUS * INTSTACK_SIZE) -#endif - -/* IRQ to CPU and CPU interrupts mapping: - * - * Encoding: CIIIIIII - * C: CPU that enabled the interrupt (0 = PRO, 1 = APP). - * I: Associated CPU interrupt. - */ - -#define IRQ_UNMAPPED 0xff -#define IRQ_GETCPU(m) (((m) & 0x80) >> 0x07) -#define IRQ_GETCPUINT(m) ((m) & 0x7f) -#define IRQ_MKMAP(c, i) (((c) << 0x07) | (i)) - -/* CPU interrupts to peripheral mapping: - * - * Encoding: EPPPPPPP - * E: CPU interrupt status (0 = Disabled, 1 = Enabled). - * P: Attached peripheral. - */ - -#define CPUINT_UNASSIGNED 0x7f -#define CPUINT_GETEN(m) (((m) & 0x80) >> 0x07) -#define CPUINT_GETIRQ(m) ((m) & 0x7f) -#define CPUINT_ASSIGN(c) (((c) & 0x7f) | 0x80) -#define CPUINT_DISABLE(m) ((m) & 0x7f) -#define CPUINT_ENABLE(m) ((m) | 0x80) - -/* Mapping Peripheral IDs to map register addresses. */ - -#define CORE0_MAP_REGADDR(n) (DR_REG_INTERRUPT_CORE0_BASE + ((n) << 2)) -#ifdef CONFIG_SMP -# define CORE1_MAP_REGADDR(n) (DR_REG_INTERRUPT_CORE1_BASE + ((n) << 2)) -#endif - -/* CPU interrupts can be detached from any peripheral source by setting the - * map register to an internal CPU interrupt (6, 7, 11, 15, 16, or 29). - */ - -#define NO_CPUINT ESP32S3_CPUINT_TIMER0 - -/* Priority range is 1-5 */ - -#define ESP32S3_MIN_PRIORITY 1 -#define ESP32S3_MAX_PRIORITY 5 -#define ESP32S3_PRIO_INDEX(p) ((p) - ESP32S3_MIN_PRIORITY) - -#ifdef CONFIG_ESPRESSIF_WIFI -# define ESP32S3_WIFI_RESERVE_INT (1 << ESP32S3_CPUINT_MAC) -#else -# define ESP32S3_WIFI_RESERVE_INT 0 -#endif - -/**************************************************************************** - * Public Data - ****************************************************************************/ - -#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 15 -/* In the SMP configuration, we will need custom interrupt stacks. - * These definitions provide the aligned stack allocations. - */ - -static uint32_t g_intstackalloc[INTSTACK_ALLOC >> 2]; - -/* These definitions provide the "top" of the push-down stacks. */ - -uintptr_t g_cpu_intstack_top[CONFIG_SMP_NCPUS] = -{ - (uintptr_t)g_intstackalloc + INTSTACK_SIZE, -#if CONFIG_SMP_NCPUS > 1 - (uintptr_t)g_intstackalloc + (2 * INTSTACK_SIZE), -#endif /* CONFIG_SMP_NCPUS > 1 */ -}; -#endif /* defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 15 */ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* Maps a CPU interrupt to the IRQ of the attached peripheral interrupt */ - -static uint8_t g_cpu0_intmap[ESP32S3_NCPUINTS]; -#ifdef CONFIG_SMP -static uint8_t g_cpu1_intmap[ESP32S3_NCPUINTS]; -#endif - -static volatile uint8_t g_irqmap[NR_IRQS]; - -/* g_intenable[] is a shadow copy of the per-CPU INTENABLE register - * content. - */ - -static uint32_t g_intenable[CONFIG_SMP_NCPUS]; - -/* g_non_iram_int_mask[] is a bitmask of the interrupts that should be - * disabled during a SPI flash operation. Non-IRAM interrupts should always - * be disabled, but interrupts place on IRAM are able to run during a SPI - * flash operation. - */ - -static uint32_t g_non_iram_int_mask[CONFIG_SMP_NCPUS]; - -/* g_non_iram_int_disabled[] keeps track of the interrupts disabled during - * a SPI flash operation. - */ - -static uint32_t g_non_iram_int_disabled[CONFIG_SMP_NCPUS]; - -/* Per-CPU flag to indicate that non-IRAM interrupts were disabled */ - -static bool g_non_iram_int_disabled_flag[CONFIG_SMP_NCPUS]; - -/* Bitsets for free, unallocated CPU interrupts available to peripheral - * devices. - */ - -static uint32_t g_cpu0_freeints = ESP32S3_CPUINT_PERIPHSET & - ~ESP32S3_WIFI_RESERVE_INT; - -#ifdef CONFIG_SMP -static uint32_t g_cpu1_freeints = ESP32S3_CPUINT_PERIPHSET; -#endif - -/* Bitsets for each interrupt priority 1-5 */ - -static const uint32_t g_priority[5] = -{ - ESP32S3_INTPRI1_MASK, - ESP32S3_INTPRI2_MASK, - ESP32S3_INTPRI3_MASK, - ESP32S3_INTPRI4_MASK, - ESP32S3_INTPRI5_MASK -}; - -#ifdef CONFIG_ESP32S3_IRAM_ISR_DEBUG -/* The g_iram_count keeps track of how many times such an IRQ ran when the - * non-IRAM interrupts were disabled. - */ - -static uint64_t g_iram_count[NR_IRQS]; -#endif - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: xtensa_attach_fromcpu1_interrupt - ****************************************************************************/ - -#ifdef CONFIG_SMP -static inline void xtensa_attach_fromcpu1_interrupt(void) -{ - int cpuint; - - /* Connect all CPU peripheral source to allocated CPU interrupt */ - - cpuint = esp32s3_setup_irq(0, ESP32S3_PERIPH_INT_FROM_CPU1, 1, - ESP32S3_CPUINT_LEVEL); - DEBUGASSERT(cpuint >= 0); - - /* Attach the inter-CPU interrupt. */ - - irq_attach(ESP32S3_IRQ_INT_FROM_CPU1, (xcpt_t)esp32s3_fromcpu1_interrupt, - NULL); - - /* Enable the inter-CPU interrupt. */ - - up_enable_irq(ESP32S3_IRQ_INT_FROM_CPU1); -} -#endif - -/**************************************************************************** - * Name: esp32s3_intinfo - * - * Description: - * Return the CPU interrupt map of the given CPU and the register map - * of the given peripheral. - * - ****************************************************************************/ - -static void esp32s3_intinfo(int cpu, int periphid, - uintptr_t *regaddr, uint8_t **intmap) -{ -#ifdef CONFIG_SMP - DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS); - - if (cpu != 0) - { - *regaddr = CORE1_MAP_REGADDR(periphid); - *intmap = g_cpu1_intmap; - } - else -#endif - { - *regaddr = CORE0_MAP_REGADDR(periphid); - *intmap = g_cpu0_intmap; - } -} - -/**************************************************************************** - * Name: esp32s3_getcpuint - * - * Description: - * Get a free CPU interrupt for a peripheral device. This function will - * not ignore all of the pre-allocated CPU interrupts for internal - * devices. - * - * Input Parameters: - * cpu - CPU core to query for CPU interrupt candidates - * intmask - mask of candidate CPU interrupts. The CPU interrupt will be - * be allocated from free interrupts within this set - * - * Returned Value: - * On success, a CPU interrupt number is returned. - * A negated errno is returned on failure. - * - ****************************************************************************/ - -static int esp32s3_getcpuint(int cpu, uint32_t intmask) -{ - uint32_t *freeints; - uint32_t bitmask; - uint32_t intset; - int cpuint; - int ret = -ENOMEM; - - /* Check if there are CPU interrupts with the requested properties - * available. - */ - -#ifdef CONFIG_SMP - if (cpu != 0) - { - freeints = &g_cpu1_freeints; - } - else -#endif - { - freeints = &g_cpu0_freeints; - } - - intset = *freeints & intmask; - if (intset != 0) - { - /* Skip over initial unavailable CPU interrupts quickly in groups - * of 8 interrupt. - */ - - for (cpuint = 0, bitmask = 0xff; - cpuint <= ESP32S3_CPUINT_MAX && (intset & bitmask) == 0; - cpuint += 8, bitmask <<= 8); - - /* Search for an unallocated CPU interrupt number in the remaining - * intset. - */ - - for (; cpuint <= ESP32S3_CPUINT_MAX; cpuint++) - { - /* If the bit corresponding to the CPU interrupt is '1', then - * that CPU interrupt is available. - */ - - bitmask = 1ul << cpuint; - if ((intset & bitmask) != 0) - { - /* Got it! */ - - *freeints &= ~bitmask; - ret = cpuint; - break; - } - } - } - - /* Enable the CPU interrupt now. The interrupt is still not attached - * to any peripheral and thus has no effect. - */ - - if (ret >= 0) - { - xtensa_enable_cpuint(&g_intenable[cpu], ret); - } - - return ret; -} - -/**************************************************************************** - * Name: esp32s3_alloc_cpuint - * - * Description: - * Allocate a level CPU interrupt - * - * Input Parameters: - * cpu - CPU core to query for CPU interrupt candidates - * priority - Priority of the CPU interrupt (1-5) - * type - Interrupt type (level or edge). - * - * Returned Value: - * On success, the allocated CPU interrupt number is returned. - * A negated errno is returned on failure. The only possible failure - * is that all CPU interrupts of the requested type have already been - * allocated. - * - ****************************************************************************/ - -static int esp32s3_alloc_cpuint(int cpu, int priority, int type) -{ - uint32_t mask; - - DEBUGASSERT(priority >= ESP32S3_MIN_PRIORITY && - priority <= ESP32S3_MAX_PRIORITY); - DEBUGASSERT(type == ESP32S3_CPUINT_LEVEL); - - /* Check if there are any level CPU interrupts available at the - * requested interrupt priority. - */ - - mask = g_priority[ESP32S3_PRIO_INDEX(priority)] & - ESP32S3_CPUINT_LEVELSET; - - return esp32s3_getcpuint(cpu, mask); -} - -/**************************************************************************** - * Name: esp32s3_free_cpuint - * - * Description: - * Free a previously allocated CPU interrupt - * - * Input Parameters: - * The CPU interrupt number to be freed - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void esp32s3_free_cpuint(int cpuint) -{ - uint32_t *freeints; - uint32_t bitmask; - - DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32S3_CPUINT_MAX); - - /* Mark the CPU interrupt as available */ - - bitmask = 1ul << cpuint; - -#ifdef CONFIG_SMP - if (this_cpu() != 0) - { - freeints = &g_cpu1_freeints; - } - else -#endif - { - freeints = &g_cpu0_freeints; - } - - DEBUGASSERT((*freeints & bitmask) == 0); - *freeints |= bitmask; -} - -#ifdef CONFIG_ESP32S3_IRAM_ISR_DEBUG - -/**************************************************************************** - * Name: esp32s3_iram_interrupt_record - * - * Description: - * This function keeps track of the IRQs that ran when non-IRAM interrupts - * are disabled and enables debugging of the IRAM-enabled interrupts. - * - * Input Parameters: - * irq - The IRQ associated with a CPU interrupt - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp32s3_irq_iram_interrupt_record(int irq) -{ - irqstate_t flags = enter_critical_section(); - - g_iram_count[irq]++; - - leave_critical_section(flags); -} -#endif - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: up_irqinitialize - ****************************************************************************/ - -void up_irqinitialize(void) -{ - int i; - - /* All CPU ints are non-IRAM interrupts at the beginning and should be - * disabled during a SPI flash operation - */ - - for (i = 0; i < CONFIG_SMP_NCPUS; i++) - { - g_non_iram_int_mask[i] = UINT32_MAX; - } - - for (i = 0; i < NR_IRQS; i++) - { - g_irqmap[i] = IRQ_UNMAPPED; - } - - /* Hard code special cases. */ - - g_irqmap[XTENSA_IRQ_TIMER0] = IRQ_MKMAP(0, ESP32S3_CPUINT_TIMER0); - g_irqmap[XTENSA_IRQ_SWINT] = IRQ_MKMAP(0, ESP32S3_CPUINT_SOFTWARE1); - g_irqmap[XTENSA_IRQ_SWINT] = IRQ_MKMAP(1, ESP32S3_CPUINT_SOFTWARE1); - -#ifdef CONFIG_ESPRESSIF_WIFI - g_irqmap[ESP32S3_IRQ_MAC] = IRQ_MKMAP(0, ESP32S3_CPUINT_MAC); - g_irqmap[ESP32S3_IRQ_PWR] = IRQ_MKMAP(0, ESP32S3_CPUINT_PWR); -#endif - - /* Initialize CPU interrupts */ - - esp32s3_cpuint_initialize(); - - /* Reserve CPU0 interrupt for some special drivers */ - -#ifdef CONFIG_ESPRESSIF_WIFI - g_cpu0_intmap[ESP32S3_CPUINT_MAC] = CPUINT_ASSIGN(ESP32S3_IRQ_MAC); - g_cpu0_intmap[ESP32S3_CPUINT_PWR] = CPUINT_ASSIGN(ESP32S3_IRQ_PWR); - xtensa_enable_cpuint(&g_intenable[0], ESP32S3_CPUINT_MAC); -#endif - -#ifdef CONFIG_SMP - /* Attach and enable the inter-CPU interrupt */ - - xtensa_attach_fromcpu1_interrupt(); -#endif - - /* Initialize GPIO interrupt support */ - - esp32s3_gpioirqinitialize(); - - /* Initialize RTCIO interrupt support */ - - esp32s3_rtcioirqinitialize(); - - /* Initialize interrupt handler for the PMS violation ISR */ - - esp32s3_pmsirqinitialize(); - -#ifndef CONFIG_SUPPRESS_INTERRUPTS - /* And finally, enable interrupts. Also clears PS.EXCM */ - - xtensa_color_intstack(); - up_irq_enable(); -#endif - - /* Attach the software interrupt */ - - irq_attach(XTENSA_IRQ_SYSCALL, xtensa_swint, NULL); -} - -/**************************************************************************** - * Name: up_disable_irq - * - * Description: - * Disable the IRQ specified by 'irq' - * - ****************************************************************************/ - -void up_disable_irq(int irq) -{ - int cpu = IRQ_GETCPU(g_irqmap[irq]); - int cpuint = IRQ_GETCPUINT(g_irqmap[irq]); - - if (g_irqmap[irq] == IRQ_UNMAPPED) - { - /* This interrupt is already disabled. */ - - return; - } - - DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32S3_CPUINT_MAX); - DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS); - - if (irq < XTENSA_NIRQ_INTERNAL) - { - /* This is an internal CPU interrupt, it cannot be disabled using - * the Interrupt Matrix. - */ - -#ifdef CONFIG_SMP - int me = this_cpu(); - if (me != cpu) - { - /* It was the other CPU that enabled this interrupt. */ - - return; - } -#endif - - xtensa_disable_cpuint(&g_intenable[cpu], cpuint); - } - else - { - /* A peripheral interrupt, use the Interrupt Matrix to disable it. */ - - int periph = ESP32S3_IRQ2PERIPH(irq); - uintptr_t regaddr; - uint8_t *intmap; - - DEBUGASSERT(periph >= 0 && periph < ESP32S3_NPERIPHERALS); - esp32s3_intinfo(cpu, periph, ®addr, &intmap); - - intmap[cpuint] = CPUINT_DISABLE(intmap[cpuint]); - putreg32(NO_CPUINT, regaddr); - } -} - -/**************************************************************************** - * Name: up_enable_irq - * - * Description: - * Enable the IRQ specified by 'irq' - * - ****************************************************************************/ - -void up_enable_irq(int irq) -{ - int cpuint = IRQ_GETCPUINT(g_irqmap[irq]); - - DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32S3_CPUINT_MAX); - - if (irq < XTENSA_NIRQ_INTERNAL) - { - /* For internal interrupts, use the current CPU. We can't enable other - * CPUs' internal interrupts. - * The CPU interrupt can still be taken from the map as internal - * interrupts have the same number for all CPUs. In this case then - * we are just overwriting the cpu part of the map. - */ - - int cpu = this_cpu(); - - /* Enable the CPU interrupt now for internal CPU. */ - - xtensa_enable_cpuint(&g_intenable[cpu], cpuint); - } - else - { - /* Retrieve the CPU that enabled this interrupt from the IRQ map. - * - * For peripheral interrupts we rely on the interrupt matrix to manage - * interrupts. The interrupt matrix registers are available for both - * CPUs. - */ - - int cpu = IRQ_GETCPU(g_irqmap[irq]); - - /* Check if the registered ISR for this IRQ is intended to be run from - * IRAM. If so, check if its interrupt handler is located in IRAM. - */ - - bool isr_in_iram = !((g_non_iram_int_mask[cpu] & (1 << cpuint)) > 0); - - xcpt_t handler = g_irqvector[irq].handler; - - if (isr_in_iram && handler && !esp32s3_ptr_iram(handler)) - { - irqerr("Interrupt handler isn't in IRAM (%08" PRIxPTR ")", - (intptr_t)handler); - PANIC(); - } - - DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS); - - /* For peripheral interrupts, attach the interrupt to the peripheral; - * the CPU interrupt was already enabled when allocated. - */ - - int periph = ESP32S3_IRQ2PERIPH(irq); - uintptr_t regaddr; - uint8_t *intmap; - - DEBUGASSERT(periph >= 0 && periph < ESP32S3_NPERIPHERALS); - - esp32s3_intinfo(cpu, periph, ®addr, &intmap); - - intmap[cpuint] = CPUINT_ENABLE(intmap[cpuint]); - putreg32(cpuint, regaddr); - } -} - -/**************************************************************************** - * Name: up_get_intstackbase - * - * Description: - * Return a pointer to the "alloc" the correct interrupt stack allocation - * for the current CPU. - * - ****************************************************************************/ - -#if defined(CONFIG_SMP) && CONFIG_ARCH_INTERRUPTSTACK > 15 -uintptr_t up_get_intstackbase(int cpu) -{ - return g_cpu_intstack_top[cpu] - INTSTACK_SIZE; -} -#endif - -/**************************************************************************** - * Name: esp32s3_cpuint_initialize - * - * Description: - * Initialize CPU interrupts - * - * Input Parameters: - * None - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned on - * any failure. - * - ****************************************************************************/ - -int esp32s3_cpuint_initialize(void) -{ - uintptr_t regaddr; - uint8_t *intmap; -#ifdef CONFIG_SMP - int cpu; -#endif - int i; - -#ifdef CONFIG_SMP - /* Which CPU are we initializing */ - - cpu = this_cpu(); - DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS); -#endif - - /* Disable all CPU interrupts on this CPU */ - - xtensa_disable_all(); - - /* Detach all peripheral sources PRO CPU interrupts */ - - for (i = 0; i < ESP32S3_NPERIPHERALS; i++) - { -#ifdef CONFIG_SMP - if (cpu != 0) - { - regaddr = CORE1_MAP_REGADDR(i); - } - else -#endif - { - regaddr = CORE0_MAP_REGADDR(i); - } - - putreg32(NO_CPUINT, regaddr); - } - - /* Initialize CPU interrupt-to-IRQ mapping table */ - -#ifdef CONFIG_SMP - if (cpu != 0) - { - intmap = g_cpu1_intmap; - } - else -#endif - { - intmap = g_cpu0_intmap; - } - - /* Indicate that no peripheral interrupts are assigned to CPU interrupts */ - - memset(intmap, CPUINT_UNASSIGNED, ESP32S3_NCPUINTS); - - /* Special case the 6 internal interrupts. - * - * CPU interrupt bit IRQ number - * ---------------------------- --------------------- - * ESP32S3_CPUINT_TIMER0 6 XTENSA_IRQ_TIMER0 0 - * ESP32S3_CPUINT_SOFTWARE0 7 Not yet defined - * ESP32S3_CPUINT_PROFILING 11 Not yet defined - * ESP32S3_CPUINT_TIMER1 15 XTENSA_IRQ_TIMER1 1 - * ESP32S3_CPUINT_TIMER2 16 XTENSA_IRQ_TIMER2 2 - * ESP32S3_CPUINT_SOFTWARE1 29 XTENSA_IRQ_SWINT 4 - */ - - intmap[ESP32S3_CPUINT_TIMER0] = CPUINT_ASSIGN(XTENSA_IRQ_TIMER0); - intmap[ESP32S3_CPUINT_TIMER1] = CPUINT_ASSIGN(XTENSA_IRQ_TIMER1); - intmap[ESP32S3_CPUINT_TIMER2] = CPUINT_ASSIGN(XTENSA_IRQ_TIMER2); - intmap[ESP32S3_CPUINT_SOFTWARE1] = CPUINT_ASSIGN(XTENSA_IRQ_SWINT); - - return OK; -} - -/**************************************************************************** - * Name: esp32s3_setup_irq - * - * Description: - * This function sets up the IRQ. It allocates a CPU interrupt of the given - * priority and associated flags and attaches it to the given peripheral. - * - * Input Parameters: - * cpu - The CPU to receive the interrupt 0=PRO CPU 1=APP CPU - * periphid - The peripheral number from irq.h to be assigned to - * a CPU interrupt. - * priority - Interrupt's priority (1 - 5). - * flags - An ORred mask of the ESP32S3_CPUINT_FLAG_* defines. These - * restrict the choice of interrupts that this routine can - * choose from. - * - * Returned Value: - * The allocated CPU interrupt on success, a negated errno value on - * failure. - * - ****************************************************************************/ - -int esp32s3_setup_irq(int cpu, int periphid, int priority, int flags) -{ - irqstate_t irqstate; - uintptr_t regaddr; - uint8_t *intmap; - int irq; - int cpuint; - - if ((flags & ESP32S3_CPUINT_EDGE) != 0) - { - irqerr("Only level-enabled interrupts are available"); - return -EINVAL; - } - - if (priority > XCHAL_EXCM_LEVEL) - { - irqerr("Invalid priority %d\n", priority); - return -EINVAL; - } - - irqstate = enter_critical_section(); - - /* Setting up an IRQ includes the following steps: - * 1. Allocate a CPU interrupt. - * 2. Check if its ISR is intended to run from IRAM. - * 3. Attach that CPU interrupt to the peripheral. - * 4. Map the CPU interrupt to the IRQ to ease searching later. - */ - - cpuint = esp32s3_alloc_cpuint(cpu, priority, ESP32S3_CPUINT_LEVEL); - if (cpuint < 0) - { - irqerr("Unable to allocate CPU interrupt for priority=%d and flags=%d", - priority, flags); - leave_critical_section(irqstate); - - return cpuint; - } - - irq = ESP32S3_PERIPH2IRQ(periphid); - - DEBUGASSERT(periphid >= 0 && periphid < ESP32S3_NPERIPHERALS); - DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32S3_CPUINT_MAX); - - esp32s3_intinfo(cpu, periphid, ®addr, &intmap); - - DEBUGASSERT(intmap[cpuint] == CPUINT_UNASSIGNED); - - intmap[cpuint] = CPUINT_ASSIGN(periphid + XTENSA_IRQ_FIRSTPERIPH); - g_irqmap[irq] = IRQ_MKMAP(cpu, cpuint); - - if ((flags & ESP32S3_CPUINT_FLAG_IRAM) != 0) - { - esp32s3_irq_set_iram_isr(irq); - } - else - { - esp32s3_irq_unset_iram_isr(irq); - } - - putreg32(cpuint, regaddr); - - leave_critical_section(irqstate); - - return cpuint; -} - -/**************************************************************************** - * Name: esp32s3_teardown_irq - * - * Description: - * This function undoes the operations done by esp32s3_setup_irq. - * It detaches a peripheral interrupt from a CPU interrupt and frees the - * CPU interrupt. - * - * Input Parameters: - * cpu - The CPU to receive the interrupt 0=PRO CPU 1=APP CPU - * periphid - The peripheral number from irq.h to be detached from the - * CPU interrupt. - * cpuint - The CPU interrupt from which the peripheral interrupt will - * be detached. - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32s3_teardown_irq(int cpu, int periphid, int cpuint) -{ - irqstate_t irqstate; - uintptr_t regaddr; - uint8_t *intmap; - int irq; - - irqstate = enter_critical_section(); - - /* Tearing down an IRQ includes the following steps: - * 1. Free the previously allocated CPU interrupt. - * 2. Detach the interrupt from the peripheral. - * 3. Unmap the IRQ from the IRQ-to-cpuint map. - */ - - esp32s3_free_cpuint(cpuint); - - irq = ESP32S3_PERIPH2IRQ(periphid); - - DEBUGASSERT(periphid >= 0 && periphid < ESP32S3_NPERIPHERALS); - - esp32s3_intinfo(cpu, periphid, ®addr, &intmap); - - DEBUGASSERT(intmap[cpuint] != CPUINT_UNASSIGNED); - intmap[cpuint] = CPUINT_UNASSIGNED; - g_irqmap[irq] = IRQ_UNMAPPED; - - putreg32(NO_CPUINT, regaddr); - - leave_critical_section(irqstate); -} - -/**************************************************************************** - * Name: esp32s3_getirq - * - * Description: - * This function returns the IRQ associated with a CPU interrupt - * - * Input Parameters: - * cpu - The CPU core of the IRQ being queried - * cpuint - The CPU interrupt associated to the IRQ - * - * Returned Value: - * The IRQ associated with such CPU interrupt or CPUINT_UNASSIGNED if - * IRQ is not yet assigned to a CPU interrupt. - * - ****************************************************************************/ - -int esp32s3_getirq(int cpu, int cpuint) -{ - uint8_t *intmap; - -#ifdef CONFIG_SMP - /* Select PRO or APP CPU interrupt mapping table */ - - if (cpu != 0) - { - intmap = g_cpu1_intmap; - } - else -#endif - { - intmap = g_cpu0_intmap; - } - - return CPUINT_GETIRQ(intmap[cpuint]); -} - -/**************************************************************************** - * Name: esp32s3_getcpuint_from_irq - * - * Description: - * This function returns the CPU interrupt associated with an IRQ - * - * Input Parameters: - * irq - The IRQ associated with a CPU interrupt - * cpu - Pointer to store the CPU core of the CPU interrupt - * - * Returned Value: - * The CPU interrupt associated with such IRQ or IRQ_UNMAPPED if - * CPU interrupt is not mapped to an IRQ. - * - ****************************************************************************/ - -int esp32s3_getcpuint_from_irq(int irq, int *cpu) -{ - (*cpu) = (int)IRQ_GETCPU(g_irqmap[irq]); - - return IRQ_GETCPUINT(g_irqmap[irq]); -} - -/**************************************************************************** - * Name: xtensa_int_decode - * - * Description: - * Determine the peripheral that generated the interrupt and dispatch - * handling to the registered interrupt handler via xtensa_irq_dispatch(). - * - * Input Parameters: - * cpuints - Set of pending interrupts valid for this level - * regs - Saves processor state on the stack - * - * Returned Value: - * Normally the same value as regs is returned. But, in the event of an - * interrupt level context switch, the returned value will, instead point - * to the saved processor state in the TCB of the newly started task. - * - ****************************************************************************/ - -uint32_t *xtensa_int_decode(uint32_t *cpuints, uint32_t *regs) -{ - uint8_t *intmap; - uint32_t mask; - int bit; - int cpu; - -#ifdef CONFIG_ARCH_LEDS_CPU_ACTIVITY - board_autoled_on(LED_CPU); -#endif - /* Select PRO or APP CPU interrupt mapping table */ - - cpu = this_cpu(); - -#ifdef CONFIG_SMP - if (cpu != 0) - { - intmap = g_cpu1_intmap; - } - else -#endif - { - intmap = g_cpu0_intmap; - } - - /* Skip over zero bits, eight at a time */ - - for (bit = 0, mask = 0xff; - bit < ESP32S3_NCPUINTS && (cpuints[0] & mask) == 0; - bit += 8, mask <<= 8); - - /* Process each pending CPU interrupt */ - - for (; bit < ESP32S3_NCPUINTS && cpuints[0] != 0; bit++) - { - mask = 1 << bit; - if ((cpuints[0] & mask) != 0) - { - /* Extract the IRQ number from the mapping table */ - - uint8_t irq = CPUINT_GETIRQ(intmap[bit]); - - DEBUGASSERT(CPUINT_GETEN(intmap[bit])); - DEBUGASSERT(irq != CPUINT_UNASSIGNED); - -#ifdef CONFIG_ESP32S3_IRAM_ISR_DEBUG - /* Check if non-IRAM interrupts are disabled */ - - if (esp32s3_irq_noniram_status(cpu) == 0) - { - /* Sum-up the IRAM-enabled counter associated with the IRQ */ - - esp32s3_irq_iram_interrupt_record(irq); - } -#endif - - /* Clear software or edge-triggered interrupt */ - - xtensa_intclear(bit); - - /* Dispatch the CPU interrupt. - * - * NOTE that regs may be altered in the case of an interrupt - * level context switch. - */ - - regs = xtensa_irq_dispatch((int)irq, regs); - - /* Clear the bit in the pending interrupt so that perhaps - * we can exit the look early. - */ - - cpuints[0] &= ~mask; - } - } - - UNUSED(cpu); - - return regs; -} - -/**************************************************************************** - * Name: esp32s3_irq_noniram_disable - * - * Description: - * Disable interrupts that aren't specifically marked as running from IRAM - * - * Input Parameters: - * None - * - * Input Parameters: - * None - * - ****************************************************************************/ - -void esp32s3_irq_noniram_disable(void) -{ - irqstate_t irqstate; - uint32_t mask; - int bit; - int cpu; - uint32_t oldint; - uint32_t non_iram_ints; - - irqstate = enter_critical_section(); - cpu = this_cpu(); - non_iram_ints = g_non_iram_int_mask[cpu]; - - ASSERT(!g_non_iram_int_disabled_flag[cpu]); - - g_non_iram_int_disabled_flag[cpu] = true; - oldint = g_intenable[cpu]; - - for (bit = 0; bit < ESP32S3_NCPUINTS; bit++) - { - mask = 1 << bit; - if ((non_iram_ints & mask) != 0) - { - xtensa_disable_cpuint(&g_intenable[cpu], bit); - } - } - - g_non_iram_int_disabled[cpu] = oldint & non_iram_ints; - - leave_critical_section(irqstate); -} - -/**************************************************************************** - * Name: esp32s3_irq_noniram_enable - * - * Description: - * Re-enable interrupts disabled by esp32s3_irq_noniram_disable - * - * Input Parameters: - * None - * - * Input Parameters: - * None - * - ****************************************************************************/ - -void esp32s3_irq_noniram_enable(void) -{ - irqstate_t irqstate; - uint32_t mask; - int bit; - int cpu; - uint32_t non_iram_ints; - - irqstate = enter_critical_section(); - cpu = this_cpu(); - non_iram_ints = g_non_iram_int_disabled[cpu]; - - ASSERT(g_non_iram_int_disabled_flag[cpu]); - - g_non_iram_int_disabled_flag[cpu] = false; - - for (bit = 0; bit < ESP32S3_NCPUINTS; bit++) - { - mask = 1 << bit; - if ((non_iram_ints & mask) != 0) - { - xtensa_enable_cpuint(&g_intenable[cpu], bit); - } - } - - leave_critical_section(irqstate); -} - -/**************************************************************************** - * Name: esp32s3_irq_noniram_status - * - * Description: - * Get the current status of non-IRAM interrupts on a specific CPU core - * - * Input Parameters: - * cpu - The CPU to check the non-IRAM interrupts state - * - * Returned Value: - * true if non-IRAM interrupts are enabled, false otherwise. - * - ****************************************************************************/ - -bool esp32s3_irq_noniram_status(int cpu) -{ - DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS); - - return !g_non_iram_int_disabled_flag[cpu]; -} - -/**************************************************************************** - * Name: esp32s3_irq_set_iram_isr - * - * Description: - * Set the ISR associated to an IRQ as a IRAM-enabled ISR. - * - * Input Parameters: - * irq - The associated IRQ to set - * - * Returned Value: - * OK on success; A negated errno value on failure. - * - ****************************************************************************/ - -int esp32s3_irq_set_iram_isr(int irq) -{ - int cpu; - int cpuint = esp32s3_getcpuint_from_irq(irq, &cpu); - - if (cpuint == IRQ_UNMAPPED) - { - return -EINVAL; - } - - g_non_iram_int_mask[cpu] &= ~(1 << cpuint); - - return OK; -} - -/**************************************************************************** - * Name: esp32s3_irq_unset_iram_isr - * - * Description: - * Set the ISR associated to an IRQ as a non-IRAM ISR. - * - * Input Parameters: - * irq - The associated IRQ to set - * - * Returned Value: - * OK on success; A negated errno value on failure. - * - ****************************************************************************/ - -int esp32s3_irq_unset_iram_isr(int irq) -{ - int cpu; - int cpuint = esp32s3_getcpuint_from_irq(irq, &cpu); - - if (cpuint == IRQ_UNMAPPED) - { - return -EINVAL; - } - - g_non_iram_int_mask[cpu] |= (1 << cpuint); - - return OK; -} - -#ifdef CONFIG_ESP32S3_IRAM_ISR_DEBUG - -/**************************************************************************** - * Name: esp32s3_get_iram_interrupt_records - * - * Description: - * This function copies the vector that keeps track of the IRQs that ran - * when non-IRAM interrupts were disabled. - * - * Input Parameters: - * - * irq_count - A previously allocated pointer to store the counter of the - * interrupts that ran when non-IRAM interrupts were disabled. - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32s3_get_iram_interrupt_records(uint64_t *irq_count) -{ - irqstate_t flags = enter_critical_section(); - - memcpy(irq_count, &g_iram_count, sizeof(uint64_t) * NR_IRQS); - - leave_critical_section(flags); -} -#endif diff --git a/arch/xtensa/src/esp32s3/esp32s3_irq.h b/arch/xtensa/src/esp32s3/esp32s3_irq.h deleted file mode 100644 index 9a36b6813c65b..0000000000000 --- a/arch/xtensa/src/esp32s3/esp32s3_irq.h +++ /dev/null @@ -1,263 +0,0 @@ -/**************************************************************************** - * arch/xtensa/src/esp32s3/esp32s3_irq.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_IRQ_H -#define __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_IRQ_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/* CPU interrupt types. */ - -#define ESP32S3_CPUINT_LEVEL ESP32S3_CPUINT_FLAG_LEVEL -#define ESP32S3_CPUINT_EDGE ESP32S3_CPUINT_FLAG_EDGE - -/**************************************************************************** - * Public Functions Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32s3_cpuint_initialize - * - * Description: - * Initialize CPU interrupts - * - * Input Parameters: - * None - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned on - * any failure. - * - ****************************************************************************/ - -int esp32s3_cpuint_initialize(void); - -/**************************************************************************** - * Name: esp32s3_setup_irq - * - * Description: - * This function sets up the IRQ. It allocates a CPU interrupt of the given - * priority and type and attaches it to the given peripheral. - * - * Input Parameters: - * cpu - The CPU to receive the interrupt 0=PRO CPU 1=APP CPU - * periphid - The peripheral number from irq.h to be assigned to - * a CPU interrupt. - * priority - Interrupt's priority (1 - 5). - * flags - An ORred mask of the ESP32S3_CPUINT_FLAG_* defines. These - * restrict the choice of interrupts that this routine can - * choose from. - * - * Returned Value: - * The allocated CPU interrupt on success, a negated errno value on - * failure. - * - ****************************************************************************/ - -int esp32s3_setup_irq(int cpu, int periphid, int priority, int flags); - -/**************************************************************************** - * Name: esp32s3_teardown_irq - * - * Description: - * This function undoes the operations done by esp32s3_setup_irq. - * It detaches a peripheral interrupt from a CPU interrupt and frees the - * CPU interrupt. - * - * Input Parameters: - * cpu - The CPU to receive the interrupt 0=PRO CPU 1=APP CPU - * periphid - The peripheral number from irq.h to be detached from the - * CPU interrupt. - * cpuint - The CPU interrupt from which the peripheral interrupt will - * be detached. - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32s3_teardown_irq(int cpu, int periphid, int cpuint); - -/**************************************************************************** - * Name: esp32s3_getirq - * - * Description: - * This function returns the IRQ associated with a CPU interrupt - * - * Input Parameters: - * cpu - The CPU core of the IRQ being queried - * cpuint - The CPU interrupt associated to the IRQ - * - * Returned Value: - * The IRQ associated with such CPU interrupt or CPUINT_UNASSIGNED if - * IRQ is not yet assigned to a CPU interrupt. - * - ****************************************************************************/ - -int esp32s3_getirq(int cpu, int cpuint); - -/**************************************************************************** - * Name: esp32s3_getcpuint_from_irq - * - * Description: - * This function returns the CPU interrupt associated with an IRQ - * - * Input Parameters: - * irq - The IRQ associated with a CPU interrupt - * cpu - Pointer to store the CPU core of the CPU interrupt - * - * Returned Value: - * The CPU interrupt associated with such IRQ or IRQ_UNMAPPED if - * CPU interrupt is not mapped to an IRQ. - * - ****************************************************************************/ - -int esp32s3_getcpuint_from_irq(int irq, int *cpu); - -/**************************************************************************** - * Name: esp32s3_irq_noniram_disable - * - * Description: - * Disable interrupts that aren't specifically marked as running from IRAM - * - * Input Parameters: - * None - * - * Input Parameters: - * None - * - ****************************************************************************/ - -void esp32s3_irq_noniram_disable(void); - -/**************************************************************************** - * Name: esp32s3_irq_noniram_enable - * - * Description: - * Re-enable interrupts disabled by esp32s3_irq_noniram_disable - * - * Input Parameters: - * None - * - * Input Parameters: - * None - * - ****************************************************************************/ - -void esp32s3_irq_noniram_enable(void); - -/**************************************************************************** - * Name: esp32s3_irq_noniram_status - * - * Description: - * Get the current status of non-IRAM interrupts on a specific CPU core - * - * Input Parameters: - * cpu - The CPU to check the non-IRAM interrupts state - * - * Returned Value: - * true if non-IRAM interrupts are enabled, false otherwise. - * - ****************************************************************************/ - -bool esp32s3_irq_noniram_status(int cpu); - -/**************************************************************************** - * Name: esp32s3_irq_set_iram_isr - * - * Description: - * Set the ISR associated to an IRQ as a IRAM-enabled ISR. - * - * Input Parameters: - * irq - The associated IRQ to set - * - * Returned Value: - * OK on success; A negated errno value on failure. - * - ****************************************************************************/ - -int esp32s3_irq_set_iram_isr(int irq); - -/**************************************************************************** - * Name: esp32s3_irq_unset_iram_isr - * - * Description: - * Set the ISR associated to an IRQ as a non-IRAM ISR. - * - * Input Parameters: - * irq - The associated IRQ to set - * - * Returned Value: - * OK on success; A negated errno value on failure. - * - ****************************************************************************/ - -int esp32s3_irq_unset_iram_isr(int irq); - -#ifdef CONFIG_ESP32S3_IRAM_ISR_DEBUG - -/**************************************************************************** - * Name: esp32s3_get_iram_interrupt_records - * - * Description: - * This function copies the vector that keeps track of the IRQs that ran - * when non-IRAM interrupts were disabled. - * - * Input Parameters: - * - * irq_count - A previously allocated pointer to store the counter of the - * interrupts that ran when non-IRAM interrupts were disabled. - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32s3_get_iram_interrupt_records(uint64_t *irq_count); -#endif - -#undef EXTERN -#if defined(__cplusplus) -} -#endif - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_IRQ_H */ diff --git a/arch/xtensa/src/esp32s3/esp32s3_lcd.c b/arch/xtensa/src/esp32s3/esp32s3_lcd.c index bf036064202ba..9895d9987ae77 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_lcd.c +++ b/arch/xtensa/src/esp32s3/esp32s3_lcd.c @@ -37,10 +37,10 @@ #include -#include "esp32s3_clockconfig.h" -#include "esp32s3_gpio.h" +#include "esp_clk.h" +#include "esp_gpio.h" #include "esp32s3_dma.h" -#include "esp32s3_irq.h" +#include "esp_irq.h" #include "xtensa.h" #include "hardware/esp32s3_system.h" @@ -823,8 +823,8 @@ static void esp32s3_lcd_gpio_config(void) { const struct pin_config_s *pins_config = &config->pins_config[i]; - esp32s3_configgpio(pins_config->num, OUTPUT); - esp32s3_gpio_matrix_out(pins_config->num, pins_config->signal, 0, 0); + esp_configgpio(pins_config->num, OUTPUT); + esp_gpio_matrix_out(pins_config->num, pins_config->signal, 0, 0); } } @@ -969,13 +969,15 @@ static int esp32s3_lcd_config(void) flags = spin_lock_irqsave(&priv->lock); priv->cpu = this_cpu(); - priv->cpuint = esp32s3_setup_irq(priv->cpu, - ESP32S3_PERIPH_LCD_CAM, - ESP32S3_INT_PRIO_DEF, - ESP32S3_CPUINT_LEVEL); - DEBUGASSERT(priv->cpuint >= 0); - - DEBUGASSERT(irq_attach(ESP32S3_IRQ_LCD_CAM, lcd_interrupt, priv) == 0); + priv->cpuint = esp_setup_irq(ESP32S3_PERIPH_LCD_CAM, + ESP32S3_INT_PRIO_DEF, + ESP_IRQ_TRIGGER_LEVEL, + lcd_interrupt, + priv); + if (priv->cpuint < 0) + { + return ERROR; + } spin_unlock_irqrestore(&priv->lock, flags); diff --git a/arch/xtensa/src/esp32s3/esp32s3_lowputc.c b/arch/xtensa/src/esp32s3/esp32s3_lowputc.c index d7ff0c9a590c1..61bb8a9711271 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_lowputc.c +++ b/arch/xtensa/src/esp32s3/esp32s3_lowputc.c @@ -47,8 +47,8 @@ #include "periph_ctrl.h" -#include "esp32s3_clockconfig.h" -#include "esp32s3_gpio.h" +#include "esp_clk.h" +#include "esp_gpio.h" #include "esp32s3_lowputc.h" @@ -706,7 +706,10 @@ void esp32s3_lowputc_send_byte(const struct esp32s3_uart_s *priv, void esp32s3_lowputc_enable_sysclk(const struct esp32s3_uart_s *priv) { - periph_module_enable(PERIPH_UART0_MODULE + priv->id); + if (priv->id > 0) + { + periph_module_enable(PERIPH_UART1_MODULE + (priv->id - 1)); + } } /**************************************************************************** @@ -880,55 +883,55 @@ void esp32s3_lowputc_config_pins(const struct esp32s3_uart_s *priv) * This "?" is the Unicode replacement character (U+FFFD) */ - esp32s3_gpiowrite(priv->txpin, true); + esp_gpiowrite(priv->txpin, true); if (uart_is_iomux(priv)) { - esp32s3_gpio_matrix_out(priv->txpin, SIG_GPIO_OUT_IDX, 0, 0); - esp32s3_configgpio(priv->txpin, priv->id == 1 ? OUTPUT_FUNCTION_3 : + esp_gpio_matrix_out(priv->txpin, SIG_GPIO_OUT_IDX, 0, 0); + esp_configgpio(priv->txpin, priv->id == 1 ? OUTPUT_FUNCTION_3 : OUTPUT_FUNCTION_1); - esp32s3_configgpio(priv->rxpin, priv->id == 1 ? INPUT_FUNCTION_3 : + esp_configgpio(priv->rxpin, priv->id == 1 ? INPUT_FUNCTION_3 : INPUT_FUNCTION_1); - esp32s3_gpio_matrix_out(priv->rxpin, SIG_GPIO_OUT_IDX, 0, 0); + esp_gpio_matrix_out(priv->rxpin, SIG_GPIO_OUT_IDX, 0, 0); #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) { - esp32s3_configgpio(priv->rtspin, OUTPUT_FUNCTION_3); - esp32s3_gpio_matrix_out(priv->rtspin, SIG_GPIO_OUT_IDX, 0, 0); + esp_configgpio(priv->rtspin, OUTPUT_FUNCTION_3); + esp_gpio_matrix_out(priv->rtspin, SIG_GPIO_OUT_IDX, 0, 0); } #endif #ifdef CONFIG_SERIAL_OFLOWCONTROL if (priv->oflow) { - esp32s3_configgpio(priv->ctspin, INPUT_FUNCTION_3); - esp32s3_gpio_matrix_out(priv->ctspin, SIG_GPIO_OUT_IDX, 0, 0); + esp_configgpio(priv->ctspin, INPUT_FUNCTION_3); + esp_gpio_matrix_out(priv->ctspin, SIG_GPIO_OUT_IDX, 0, 0); } #endif } else { - esp32s3_gpio_matrix_out(priv->txpin, priv->txsig, 0, 0); - esp32s3_configgpio(priv->txpin, OUTPUT_FUNCTION_2); + esp_gpio_matrix_out(priv->txpin, priv->txsig, 0, 0); + esp_configgpio(priv->txpin, OUTPUT_FUNCTION_2); - esp32s3_configgpio(priv->rxpin, INPUT_FUNCTION_2); - esp32s3_gpio_matrix_in(priv->rxpin, priv->rxsig, 0); + esp_configgpio(priv->rxpin, INPUT_FUNCTION_2); + esp_gpio_matrix_in(priv->rxpin, priv->rxsig, 0); #ifdef CONFIG_SERIAL_IFLOWCONTROL if (priv->iflow) { - esp32s3_configgpio(priv->rtspin, OUTPUT_FUNCTION_2); - esp32s3_gpio_matrix_out(priv->rtspin, priv->rtssig, 0, 0); + esp_configgpio(priv->rtspin, OUTPUT_FUNCTION_2); + esp_gpio_matrix_out(priv->rtspin, priv->rtssig, 0, 0); } #endif #ifdef CONFIG_SERIAL_OFLOWCONTROL if (priv->oflow) { - esp32s3_configgpio(priv->ctspin, INPUT_FUNCTION_2); - esp32s3_gpio_matrix_in(priv->ctspin, priv->ctssig, 0); + esp_configgpio(priv->ctspin, INPUT_FUNCTION_2); + esp_gpio_matrix_in(priv->ctspin, priv->ctssig, 0); } #endif } @@ -936,9 +939,9 @@ void esp32s3_lowputc_config_pins(const struct esp32s3_uart_s *priv) #ifdef HAVE_RS485 if (priv->rs485_dir_gpio != 0) { - esp32s3_configgpio(priv->rs485_dir_gpio, OUTPUT); - esp32s3_gpio_matrix_out(priv->rs485_dir_gpio, SIG_GPIO_OUT_IDX, 0, 0); - esp32s3_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); + esp_configgpio(priv->rs485_dir_gpio, OUTPUT); + esp_gpio_matrix_out(priv->rs485_dir_gpio, SIG_GPIO_OUT_IDX, 0, 0); + esp_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); } #endif } @@ -959,11 +962,11 @@ void esp32s3_lowputc_restore_pins(const struct esp32s3_uart_s *priv) { /* Configure the pins */ - esp32s3_configgpio(priv->txpin, INPUT); - esp32s3_gpio_matrix_out(priv->txpin, MATRIX_DETACH_OUT_SIG, false, false); + esp_configgpio(priv->txpin, INPUT); + esp_gpio_matrix_out(priv->txpin, MATRIX_DETACH_OUT_SIG, false, false); - esp32s3_configgpio(priv->rxpin, INPUT); - esp32s3_gpio_matrix_in(priv->rxpin, MATRIX_DETACH_IN_LOW_PIN, false); + esp_configgpio(priv->rxpin, INPUT); + esp_gpio_matrix_in(priv->rxpin, MATRIX_DETACH_IN_LOW_PIN, false); } /**************************************************************************** diff --git a/arch/xtensa/src/esp32s3/esp32s3_lowputc.h b/arch/xtensa/src/esp32s3/esp32s3_lowputc.h index 8680dd09ddc31..aac979a6a239f 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_lowputc.h +++ b/arch/xtensa/src/esp32s3/esp32s3_lowputc.h @@ -40,8 +40,7 @@ #include #include "chip.h" -#include "esp32s3_irq.h" -#include "hardware/esp32s3_uart.h" +#include "esp_irq.h" #include "hardware/esp32s3_gpio_sigmap.h" #include "esp32s3_config.h" diff --git a/arch/xtensa/src/esp32s3/esp32s3_oneshot.c b/arch/xtensa/src/esp32s3/esp32s3_oneshot.c index ee2105e8c5091..961b471680e45 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_oneshot.c +++ b/arch/xtensa/src/esp32s3/esp32s3_oneshot.c @@ -36,7 +36,7 @@ #include #include -#include "esp32s3_clockconfig.h" +#include "esp_clk.h" #include "esp32s3_oneshot.h" #include "esp32s3_tim.h" #include "hardware/esp32s3_soc.h" diff --git a/arch/xtensa/src/esp32s3/esp32s3_otg_device.c b/arch/xtensa/src/esp32s3/esp32s3_otg_device.c index 6f98a3d7b3d9d..b5b3e34826702 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_otg_device.c +++ b/arch/xtensa/src/esp32s3/esp32s3_otg_device.c @@ -49,10 +49,10 @@ #include "hardware/esp32s3_system.h" #include "hardware/esp32s3_gpio_sigmap.h" #include "hardware/esp32s3_usb_wrap.h" -#include "hardware/esp32s3_rtccntl.h" +#include "soc/rtc_cntl_reg.h" #include "hardware/esp32s3_pinmap.h" -#include "esp32s3_gpio.h" -#include "esp32s3_irq.h" +#include "esp_gpio.h" +#include "esp_irq.h" #include "esp32s3_otg.h" /**************************************************************************** @@ -5309,9 +5309,9 @@ static void esp32s3_hwinitialize(struct esp32s3_usbdev_s *priv) /* Configure USB PHY */ - regval = esp32s3_getreg(RTC_CNTL_RTC_USB_CONF_REG); + regval = esp32s3_getreg(RTC_CNTL_USB_CONF_REG); regval |= RTC_CNTL_SW_HW_USB_PHY_SEL | RTC_CNTL_SW_USB_PHY_SEL; - esp32s3_putreg(regval, RTC_CNTL_RTC_USB_CONF_REG); + esp32s3_putreg(regval, RTC_CNTL_USB_CONF_REG); /* Set USB DM and DP pin pull-down */ @@ -5608,8 +5608,8 @@ void xtensa_usbinitialize(void) /* Configure OTG alternate function pins */ - esp32s3_configgpio(USB_IOMUX_DM, DRIVE_3); - esp32s3_configgpio(USB_IOMUX_DP, DRIVE_3); + esp_configgpio(USB_IOMUX_DM, DRIVE_3); + esp_configgpio(USB_IOMUX_DP, DRIVE_3); /* USB_OTG_IDDIG_IN_IDX: connected connector is mini-B side * USB_SRP_BVALID_IN_IDX: HIGH to force USB device mode @@ -5617,16 +5617,16 @@ void xtensa_usbinitialize(void) * USB_OTG_AVALID_IN_IDX: HIGH to force USB host mode */ - esp32s3_gpio_matrix_in(MATRIX_DETACH_IN_LOW_HIGH, + esp_gpio_matrix_in(MATRIX_DETACH_IN_LOW_HIGH, USB_OTG_IDDIG_IN_IDX, false); - esp32s3_gpio_matrix_in(MATRIX_DETACH_IN_LOW_HIGH, + esp_gpio_matrix_in(MATRIX_DETACH_IN_LOW_HIGH, USB_SRP_BVALID_IN_IDX, false); - esp32s3_gpio_matrix_in(MATRIX_DETACH_IN_LOW_HIGH, + esp_gpio_matrix_in(MATRIX_DETACH_IN_LOW_HIGH, USB_OTG_VBUSVALID_IN_IDX, false); - esp32s3_gpio_matrix_in(MATRIX_DETACH_IN_LOW_PIN, + esp_gpio_matrix_in(MATRIX_DETACH_IN_LOW_PIN, USB_OTG_AVALID_IN_IDX, false); @@ -5643,13 +5643,13 @@ void xtensa_usbinitialize(void) /* Attach the OTG interrupt handler */ priv->cpu = this_cpu(); - priv->cpuint = esp32s3_setup_irq(priv->cpu, ESP32S3_PERIPH_USB, - 1, ESP32S3_CPUINT_LEVEL); + priv->cpuint = esp_setup_irq(ESP32S3_PERIPH_USB, + 1, + ESP_IRQ_TRIGGER_LEVEL, + esp32s3_usbinterrupt, + NULL); DEBUGASSERT(priv->cpuint >= 0); - ret = irq_attach(ESP32S3_IRQ_USB, esp32s3_usbinterrupt, NULL); - DEBUGASSERT(ret == 0); - /* Initialize the USB OTG core */ esp32s3_hwinitialize(priv); @@ -5701,7 +5701,6 @@ void xtensa_usbuninitialize(void) /* Disable and detach IRQs */ up_disable_irq(ESP32S3_IRQ_USB); - irq_detach(ESP32S3_IRQ_USB); /* Disable all endpoint interrupts */ diff --git a/arch/xtensa/src/esp32s3/esp32s3_psram_octal.c b/arch/xtensa/src/esp32s3/esp32s3_psram_octal.c index fbc75823c97b2..dc54c8c2f987e 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_psram_octal.c +++ b/arch/xtensa/src/esp32s3/esp32s3_psram_octal.c @@ -29,7 +29,7 @@ #include "xtensa.h" -#include "esp32s3_gpio.h" +#include "esp_gpio.h" #include "esp32s3_psram.h" #include "esp32s3_spi_timing.h" diff --git a/arch/xtensa/src/esp32s3/esp32s3_psram_quad.c b/arch/xtensa/src/esp32s3/esp32s3_psram_quad.c index bd40995fbad74..62b709c81902b 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_psram_quad.c +++ b/arch/xtensa/src/esp32s3/esp32s3_psram_quad.c @@ -27,7 +27,7 @@ #include #include -#include "esp32s3_gpio.h" +#include "esp_gpio.h" #include "esp32s3_psram.h" #include "esp32s3_spi_timing.h" @@ -358,12 +358,12 @@ static void psram_gpio_config(void) if (cs1_io == SPI_CS1_GPIO_NUM) { - esp32s3_gpio_matrix_out(cs1_io, SPICS1_OUT_IDX, 0, 0); + esp_gpio_matrix_out(cs1_io, SPICS1_OUT_IDX, 0, 0); } else { - esp32s3_configgpio(cs1_io, OUTPUT); - esp32s3_gpio_matrix_out(cs1_io, SIG_GPIO_OUT_IDX, 0, 0); + esp_configgpio(cs1_io, OUTPUT); + esp_gpio_matrix_out(cs1_io, SIG_GPIO_OUT_IDX, 0, 0); } g_psram_cs_io = cs1_io; diff --git a/arch/xtensa/src/esp32s3/esp32s3_qspi.c b/arch/xtensa/src/esp32s3/esp32s3_qspi.c index 57c8d621e43a2..97848155ce424 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_qspi.c +++ b/arch/xtensa/src/esp32s3/esp32s3_qspi.c @@ -52,8 +52,8 @@ #include "hardware/esp32s3_soc.h" #include "hardware/esp32s3_system.h" -#include "esp32s3_irq.h" -#include "esp32s3_gpio.h" +#include "esp_irq.h" +#include "esp_gpio.h" #include "esp32s3_qspi.h" #ifdef CONFIG_ESP32S3_SPI_DMA @@ -1257,22 +1257,22 @@ static void esp32s3_qspi_init_iomux(struct esp32s3_qspi_priv_s *priv) uint32_t attr = OUTPUT_FUNCTION_5; const struct esp32s3_qspi_config_s *config = priv->config; - esp32s3_configgpio(config->cs_pin, attr); - esp32s3_configgpio(config->clk_pin, attr); + esp_configgpio(config->cs_pin, attr); + esp_configgpio(config->clk_pin, attr); attr |= INPUT; - esp32s3_configgpio(config->mosi_pin, attr); - esp32s3_configgpio(config->miso_pin, attr); - esp32s3_configgpio(config->io2_pin, attr); - esp32s3_configgpio(config->io3_pin, attr); - - esp32s3_gpio_matrix_out(config->cs_pin, SIG_GPIO_OUT_IDX, 0, 0); - esp32s3_gpio_matrix_out(config->clk_pin, SIG_GPIO_OUT_IDX, 0, 0); - esp32s3_gpio_matrix_out(config->mosi_pin, SIG_GPIO_OUT_IDX, 0, 0); - esp32s3_gpio_matrix_out(config->miso_pin, SIG_GPIO_OUT_IDX, 0, 0); - esp32s3_gpio_matrix_out(config->io2_pin, SIG_GPIO_OUT_IDX, 0, 0); - esp32s3_gpio_matrix_out(config->io3_pin, SIG_GPIO_OUT_IDX, 0, 0); + esp_configgpio(config->mosi_pin, attr); + esp_configgpio(config->miso_pin, attr); + esp_configgpio(config->io2_pin, attr); + esp_configgpio(config->io3_pin, attr); + + esp_gpio_matrix_out(config->cs_pin, SIG_GPIO_OUT_IDX, 0, 0); + esp_gpio_matrix_out(config->clk_pin, SIG_GPIO_OUT_IDX, 0, 0); + esp_gpio_matrix_out(config->mosi_pin, SIG_GPIO_OUT_IDX, 0, 0); + esp_gpio_matrix_out(config->miso_pin, SIG_GPIO_OUT_IDX, 0, 0); + esp_gpio_matrix_out(config->io2_pin, SIG_GPIO_OUT_IDX, 0, 0); + esp_gpio_matrix_out(config->io3_pin, SIG_GPIO_OUT_IDX, 0, 0); } #endif @@ -1296,29 +1296,29 @@ static void esp32s3_qspi_init_iomatrix(struct esp32s3_qspi_priv_s *priv) uint32_t attr = OUTPUT; const struct esp32s3_qspi_config_s *config = priv->config; - esp32s3_configgpio(config->cs_pin, OUTPUT); - esp32s3_gpio_matrix_out(config->cs_pin, config->cs_outsig, 0, 0); + esp_configgpio(config->cs_pin, OUTPUT); + esp_gpio_matrix_out(config->cs_pin, config->cs_outsig, 0, 0); - esp32s3_configgpio(config->clk_pin, OUTPUT); - esp32s3_gpio_matrix_out(config->clk_pin, config->clk_outsig, 0, 0); + esp_configgpio(config->clk_pin, OUTPUT); + esp_gpio_matrix_out(config->clk_pin, config->clk_outsig, 0, 0); attr |= INPUT; - esp32s3_configgpio(config->mosi_pin, attr); - esp32s3_gpio_matrix_in(config->mosi_pin, config->mosi_insig, 0); - esp32s3_gpio_matrix_out(config->mosi_pin, config->mosi_outsig, 0, 0); + esp_configgpio(config->mosi_pin, attr); + esp_gpio_matrix_in(config->mosi_pin, config->mosi_insig, 0); + esp_gpio_matrix_out(config->mosi_pin, config->mosi_outsig, 0, 0); - esp32s3_configgpio(config->miso_pin, attr); - esp32s3_gpio_matrix_in(config->miso_pin, config->miso_insig, 0); - esp32s3_gpio_matrix_out(config->miso_pin, config->miso_outsig, 0, 0); + esp_configgpio(config->miso_pin, attr); + esp_gpio_matrix_in(config->miso_pin, config->miso_insig, 0); + esp_gpio_matrix_out(config->miso_pin, config->miso_outsig, 0, 0); - esp32s3_configgpio(config->io2_pin, attr); - esp32s3_gpio_matrix_in(config->io2_pin, config->io2_insig, 0); - esp32s3_gpio_matrix_out(config->io2_pin, config->io2_outsig, 0, 0); + esp_configgpio(config->io2_pin, attr); + esp_gpio_matrix_in(config->io2_pin, config->io2_insig, 0); + esp_gpio_matrix_out(config->io2_pin, config->io2_outsig, 0, 0); - esp32s3_configgpio(config->io3_pin, attr); - esp32s3_gpio_matrix_in(config->io3_pin, config->io3_insig, 0); - esp32s3_gpio_matrix_out(config->io3_pin, config->io3_outsig, 0, 0); + esp_configgpio(config->io3_pin, attr); + esp_gpio_matrix_in(config->io3_pin, config->io3_insig, 0); + esp_gpio_matrix_out(config->io3_pin, config->io3_outsig, 0, 0); } #endif @@ -1629,9 +1629,11 @@ struct qspi_dev_s *esp32s3_qspibus_initialize(int port) /* Set up to receive peripheral interrupts on the current CPU */ priv->cpu = this_cpu(); - priv->cpuint = esp32s3_setup_irq(priv->cpu, priv->config->periph, - ESP32S3_INT_PRIO_DEF, - ESP32S3_CPUINT_LEVEL); + priv->cpuint = esp_setup_irq(priv->config->periph, + ESP32S3_INT_PRIO_DEF, + ESP_IRQ_TRIGGER_LEVEL, + esp32s3_qspi_interrupt, + priv); if (priv->cpuint < 0) { /* Failed to allocate a CPU interrupt of this type. */ @@ -1640,19 +1642,6 @@ struct qspi_dev_s *esp32s3_qspibus_initialize(int port) return NULL; } - /* Attach and enable the IRQ */ - - if (irq_attach(priv->config->irq, esp32s3_qspi_interrupt, priv) != OK) - { - /* Failed to attach IRQ, so CPU interrupt must be freed. */ - - esp32s3_teardown_irq(priv->cpu, priv->config->periph, priv->cpuint); - priv->cpuint = -ENOMEM; - nxmutex_unlock(&priv->lock); - - return NULL; - } - /* Enable the CPU interrupt that is linked to the QSPI device. */ up_enable_irq(priv->config->irq); @@ -1662,8 +1651,7 @@ struct qspi_dev_s *esp32s3_qspibus_initialize(int port) { #ifdef CONFIG_ESP32S3_SPI_DMA up_disable_irq(priv->config->irq); - esp32s3_teardown_irq(priv->cpu, priv->config->periph, priv->cpuint); - irq_detach(priv->config->irq); + esp_teardown_irq(priv->config->periph, priv->cpuint); priv->cpuint = -ENOMEM; #endif nxmutex_unlock(&priv->lock); @@ -1709,9 +1697,7 @@ int esp32s3_qspibus_uninitialize(struct qspi_dev_s *dev) #ifdef CONFIG_ESP32S3_SPI_DMA up_disable_irq(priv->config->irq); - esp32s3_teardown_irq(priv->cpu, priv->config->periph, priv->cpuint); - irq_detach(priv->config->irq); - + esp_teardown_irq(priv->config->periph, priv->cpuint); priv->cpuint = -ENOMEM; #endif diff --git a/arch/xtensa/src/esp32s3/esp32s3_reset_reasons.c b/arch/xtensa/src/esp32s3/esp32s3_reset_reasons.c index 5e60cb969164a..37e545aa7e990 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_reset_reasons.c +++ b/arch/xtensa/src/esp32s3/esp32s3_reset_reasons.c @@ -30,7 +30,7 @@ #include #include "xtensa.h" -#include "hardware/esp32s3_rtccntl.h" +#include "soc/rtc_cntl_reg.h" #include "esp32s3_reset_reasons.h" @@ -52,7 +52,7 @@ soc_reset_reason_t esp32s3_reset_reasons(int cpu) uint32_t regshift; uint32_t regval; - regval = getreg32(RTC_CNTL_RTC_RESET_STATE_REG); + regval = getreg32(RTC_CNTL_RESET_STATE_REG); #ifdef CONFIG_SMP if (cpu != 0) diff --git a/arch/xtensa/src/esp32s3/esp32s3_rng.c b/arch/xtensa/src/esp32s3/esp32s3_rng.c index 63f1e891f9ebe..ffe8fe1ada43b 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_rng.c +++ b/arch/xtensa/src/esp32s3/esp32s3_rng.c @@ -43,7 +43,7 @@ #include "xtensa.h" #include "esp_attr.h" #include "hardware/wdev_reg.h" -#include "esp32s3_clockconfig.h" +#include "esp_clk.h" #include "esp_random.h" diff --git a/arch/xtensa/src/esp32s3/esp32s3_rt_timer.c b/arch/xtensa/src/esp32s3/esp32s3_rt_timer.c deleted file mode 100644 index 7762dfabafbb7..0000000000000 --- a/arch/xtensa/src/esp32s3/esp32s3_rt_timer.c +++ /dev/null @@ -1,1054 +0,0 @@ -/**************************************************************************** - * arch/xtensa/src/esp32s3/esp32s3_rt_timer.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this args for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include -#include -#include -#include - -#include "xtensa.h" -#include "esp_attr.h" -#include "esp32s3_irq.h" -#include "esp32s3_rt_timer.h" -#include "hardware/esp32s3_soc.h" -#include "hardware/esp32s3_system.h" -#include "hardware/esp32s3_systimer.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define RT_TIMER_TASK_NAME CONFIG_ESP32S3_RT_TIMER_TASK_NAME -#define RT_TIMER_TASK_PRIORITY CONFIG_ESP32S3_RT_TIMER_TASK_PRIORITY -#define RT_TIMER_TASK_STACK_SIZE CONFIG_ESP32S3_RT_TIMER_TASK_STACK_SIZE - -#ifdef CONFIG_SCHED_HPWORKPRIORITY -static_assert(RT_TIMER_TASK_PRIORITY < CONFIG_SCHED_HPWORKPRIORITY, - "RT Timer priority should be smaller than high-prio workqueue"); -#endif - -/* Timer running at 16 MHz */ - -#define CYCLES_PER_USEC 16 -#define USEC_TO_CYCLES(u) ((u) * CYCLES_PER_USEC) -#define CYCLES_TO_USEC(c) ((c) / CYCLES_PER_USEC) - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -struct esp32s3_rt_priv_s -{ - pid_t pid; /* PID of RT Timer kernel thread */ - int cpuint; /* CPU interrupt assigned to this timer */ - int core; /* Core that is taking care of the timer - * interrupts - */ - sem_t toutsem; /* Semaphore for synchronizing access to list - * of timed-out timers - */ - struct list_node runlist; /* List of timers in the running state */ - struct list_node toutlist; /* List of timed-out timers */ - spinlock_t lock; /* Device-specific lock */ -}; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -static struct esp32s3_rt_priv_s g_rt_priv = -{ - .pid = INVALID_PROCESS_ID, - .cpuint = -ENOMEM, - .core = -ENODEV, - .toutsem = SEM_INITIALIZER(0), -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: rt_timer_getcounter - * - * Description: - * Get the current counter value. - * - * Input Parameters: - * None. - * - * Returned Value: - * Current counter value. - * - ****************************************************************************/ - -static inline uint64_t rt_timer_getcounter(void) -{ - uint32_t lo; - uint32_t lo_start; - uint32_t hi; - uint64_t counter; - - /* Trigger an update event */ - - modifyreg32(SYSTIMER_UNIT1_OP_REG, 0, SYSTIMER_TIMER_UNIT1_UPDATE); - - /* Wait until the value is valid */ - - while ((getreg32(SYSTIMER_UNIT1_OP_REG) & - SYSTIMER_TIMER_UNIT1_VALUE_VALID) != - SYSTIMER_TIMER_UNIT1_VALUE_VALID); - - /* Read LO, HI, then LO again, check that LO returns the same value. - * This accounts for the case when an interrupt may happen between reading - * HI and LO values, and this function may get called from the ISR. - * In this case, the repeated read will return consistent values. - */ - - lo_start = getreg32(SYSTIMER_UNIT1_VALUE_LO_REG); - do - { - lo = lo_start; - hi = getreg32(SYSTIMER_UNIT1_VALUE_HI_REG); - lo_start = getreg32(SYSTIMER_UNIT1_VALUE_LO_REG); - } - while (lo_start != lo); - - counter = ((uint64_t) hi << 32) | lo; - - return counter; -} - -/**************************************************************************** - * Name: rt_timer_setcounter - * - * Description: - * Set the counter value. - * - * Input Parameters: - * value - The value to be loaded to the counter. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -static inline void rt_timer_setcounter(uint64_t value) -{ - /* Set counter value */ - - putreg32(value & SYSTIMER_TIMER_UNIT1_VALUE_LO_V, - SYSTIMER_UNIT1_VALUE_LO_REG); - putreg32((value >> 32) & SYSTIMER_TIMER_UNIT1_VALUE_HI_V, - SYSTIMER_UNIT1_VALUE_HI_REG); - - /* Apply counter value */ - - putreg32(SYSTIMER_TIMER_UNIT1_LOAD, SYSTIMER_UNIT1_LOAD_REG); -} - -/**************************************************************************** - * Name: rt_timer_getalarmvalue - * - * Description: - * Get the alarm value. - * - * Input Parameters: - * None. - * - * Returned Value: - * Remaining ticks for expiration. - * - ****************************************************************************/ - -static inline uint64_t rt_timer_getalarmvalue(void) -{ - uint32_t hi = getreg32(SYSTIMER_TARGET2_HI_REG); - uint32_t lo = getreg32(SYSTIMER_TARGET2_LO_REG); - uint64_t ticks = ((uint64_t) hi << 32) | lo; - - return ticks; -} - -/**************************************************************************** - * Name: rt_timer_setalarmvalue - * - * Description: - * Set the value that will trigger an alarm when the counter value matches - * this value. - * - * Input Parameters: - * value - The alarm value. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -static inline void rt_timer_setalarmvalue(uint64_t value) -{ - /* Set alarm value */ - - putreg32(value & 0xffffffff, SYSTIMER_TARGET2_LO_REG); - putreg32((value >> 32) & 0xfffff, SYSTIMER_TARGET2_HI_REG); - - /* Apply alarm value */ - - putreg32(SYSTIMER_TIMER_COMP2_LOAD, SYSTIMER_COMP2_LOAD_REG); -} - -/**************************************************************************** - * Name: rt_timer_setalarm - * - * Description: - * Enable/Disable the alarm. - * - * Input Parameters: - * enable - A variable to indicate the action. If true, enable - * the alarm, otherwise disable it. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -static void rt_timer_setalarm(bool enable) -{ - if (enable) - { - modifyreg32(SYSTIMER_CONF_REG, 0, SYSTIMER_TARGET2_WORK_EN); - } - else - { - modifyreg32(SYSTIMER_CONF_REG, SYSTIMER_TARGET2_WORK_EN, 0); - } -} - -/**************************************************************************** - * Name: rt_timer_setisr - * - * Description: - * Allocate a CPU Interrupt, connect the peripheral source to this - * Interrupt, register the callback and enable the CPU Interrupt. - * In case a NULL handler is provided, deallocate the interrupt and - * unregister the previously provided handler. - * - * Input Parameters: - * handler - Callback to be invoked on timer interrupt. - * arg - Argument to be passed to the handler callback. - * - * Returned Values: - * Zero (OK) is returned on success. A negated errno value is returned to - * indicate the nature of any failure. - * - ****************************************************************************/ - -static int rt_timer_setisr(xcpt_t handler, void *arg) -{ - struct esp32s3_rt_priv_s *priv = &g_rt_priv; - int ret = OK; - - /* Disable interrupt when callback is removed. */ - - if (handler == NULL) - { - /* If a CPU Interrupt was previously allocated, then deallocate it */ - - if (priv->cpuint != -ENOMEM) - { - /* Disable CPU Interrupt, free a previously allocated - * CPU Interrupt - */ - - up_disable_irq(ESP32S3_IRQ_SYSTIMER_TARGET2); - esp32s3_teardown_irq(priv->core, ESP32S3_PERIPH_SYSTIMER_TARGET2, - priv->cpuint); - irq_detach(ESP32S3_IRQ_SYSTIMER_TARGET2); - - priv->cpuint = -ENOMEM; - priv->core = -ENODEV; - } - } - - /* Otherwise set callback and enable interrupt */ - - else - { - if (priv->cpuint != -ENOMEM) - { - /* Disable the previous IRQ */ - - up_disable_irq(ESP32S3_IRQ_SYSTIMER_TARGET2); - } - - /* Set up to receive peripheral interrupts on the current CPU */ - - priv->core = this_cpu(); - priv->cpuint = esp32s3_setup_irq(priv->core, - ESP32S3_PERIPH_SYSTIMER_TARGET2, - 1, ESP32S3_CPUINT_LEVEL); - if (priv->cpuint < 0) - { - tmrerr("ERROR: No CPU Interrupt available"); - ret = priv->cpuint; - goto errout; - } - - /* Associate an IRQ Number (from the timer) to an ISR */ - - ret = irq_attach(ESP32S3_IRQ_SYSTIMER_TARGET2, handler, arg); - if (ret != OK) - { - esp32s3_teardown_irq(priv->core, ESP32S3_PERIPH_SYSTIMER_TARGET2, - priv->cpuint); - tmrerr("ERROR: Failed to associate an IRQ Number"); - goto errout; - } - - /* Enable the CPU Interrupt that is linked to the timer */ - - up_enable_irq(ESP32S3_IRQ_SYSTIMER_TARGET2); - } - -errout: - return ret; -} - -/**************************************************************************** - * Name: start_rt_timer - * - * Description: - * Start the timer by inserting it into the running list and reset the - * hardware timer alarm value if this timer is at the head of the list. - * Larger timeouts go to the end of the list (tail). - * - * Input Parameters: - * timer - Pointer to the RT Timer state structure. - * timeout - Timeout value. - * repeat - Repeat mode (true: enabled, false: disabled). - * - * Returned Value: - * None. - * - ****************************************************************************/ - -static void start_rt_timer(struct rt_timer_s *timer, - uint64_t timeout, - bool repeat) -{ - struct esp32s3_rt_priv_s *priv = &g_rt_priv; - - /* Only idle timer can be started */ - - if (timer->state == RT_TIMER_IDLE) - { - struct rt_timer_s *temp_p; - bool inserted = false; - - /* Calculate the timer's alarm value */ - - uint64_t counter = rt_timer_getcounter(); - counter = CYCLES_TO_USEC(counter); - timer->timeout = timeout; - timer->alarm = timer->timeout + counter; - - if (repeat) - { - timer->flags |= RT_TIMER_REPEAT; - } - else - { - timer->flags &= ~RT_TIMER_REPEAT; - } - - /* Scan the timer list and insert the new timer into previous node of - * timer whose alarm value is larger than new one. - */ - - list_for_every_entry(&priv->runlist, temp_p, struct rt_timer_s, list) - { - if (temp_p->alarm > timer->alarm) - { - list_add_before(&temp_p->list, &timer->list); - inserted = true; - break; - } - } - - /* If we didn't find a larger one, insert the new timer at the tail of - * the list. - */ - - if (!inserted) - { - list_add_tail(&priv->runlist, &timer->list); - } - - timer->state = RT_TIMER_READY; - - /* Check if this timer is at the head of the list */ - - if (timer == container_of(priv->runlist.next, struct rt_timer_s, list)) - { - /* Reset the hardware timer alarm */ - - rt_timer_setalarm(false); - rt_timer_setalarmvalue(USEC_TO_CYCLES(timer->alarm)); - rt_timer_setalarm(true); - } - } - else - { - tmrwarn("Timer not in idle mode. Only idle timer can be started!\n"); - } -} - -/**************************************************************************** - * Name: stop_rt_timer - * - * Description: - * Stop the timer by removing it from the running list and reset the - * hardware timer alarm value if this timer is at the head of list. - * - * Input Parameters: - * timer - Pointer to the RT Timer state structure. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -static void stop_rt_timer(struct rt_timer_s *timer) -{ - struct esp32s3_rt_priv_s *priv = &g_rt_priv; - - /* "start" function can set the timer's repeat flag, and "stop" function - * should remove this flag. - */ - - timer->flags &= ~RT_TIMER_REPEAT; - - /* Only timers in "ready" state can be stopped */ - - if (timer->state == RT_TIMER_READY) - { - bool ishead; - - /* Check if the timer is at the head of the list */ - - if (timer == container_of(priv->runlist.next, - struct rt_timer_s, list)) - { - ishead = true; - } - else - { - ishead = false; - } - - list_delete(&timer->list); - timer->state = RT_TIMER_IDLE; - - if (ishead) - { - if (!list_is_empty(&priv->runlist)) - { - /* Set the value from the next timer as the new hardware timer - * alarm value. - */ - - struct rt_timer_s *next_timer = - container_of(priv->runlist.next, struct rt_timer_s, list); - - rt_timer_setalarm(false); - rt_timer_setalarmvalue(USEC_TO_CYCLES(next_timer->alarm)); - rt_timer_setalarm(true); - } - } - } -} - -/**************************************************************************** - * Name: rt_timer_thread - * - * Description: - * RT Timer working thread: Waits for a timeout semaphore, scans the - * timeout list and processes all the timers in the list. - * - * Input Parameters: - * argc - Not used. - * argv - Not used. - * - * Returned Value: - * Zero (OK) is returned on success. A negated errno value is returned to - * indicate the nature of any failure. - * - ****************************************************************************/ - -static int rt_timer_thread(int argc, char *argv[]) -{ - struct esp32s3_rt_priv_s *priv = &g_rt_priv; - - while (1) - { - /* Waiting for all timers to time out */ - - DEBUGVERIFY(nxsem_wait_uninterruptible(&priv->toutsem)); - - irqstate_t flags = spin_lock_irqsave(&priv->lock); - - /* Process all the timers in list */ - - while (!list_is_empty(&priv->toutlist)) - { - /* Get the first timer in the list */ - - struct rt_timer_s *timer = container_of(priv->toutlist.next, - struct rt_timer_s, list); - - /* Cache the raw state to decide how to deal with this timer */ - - enum rt_timer_state_e raw_state = timer->state; - - /* Delete the timer from the list */ - - list_delete(&timer->list); - - /* Set timer's state to idle so it can be restarted by the user. */ - - timer->state = RT_TIMER_IDLE; - - spin_unlock_irqrestore(&priv->lock, flags); - - if (raw_state == RT_TIMER_TIMEOUT) - { - timer->callback(timer->arg); - } - else if (raw_state == RT_TIMER_DELETE) - { - kmm_free(timer); - } - - /* Enter critical section for next scanning list */ - - flags = spin_lock_irqsave(&priv->lock); - - if (raw_state == RT_TIMER_TIMEOUT) - { - /* Check if the timer is in "repeat" mode */ - - if ((timer->flags & RT_TIMER_REPEAT) != 0) - { - start_rt_timer(timer, timer->timeout, true); - } - } - } - - spin_unlock_irqrestore(&priv->lock, flags); - } - - return OK; -} - -/**************************************************************************** - * Name: rt_timer_isr - * - * Description: - * Hardware timer interrupt service routine. - * - * Input Parameters: - * dev - Pointer to the driver state structure. - * handler - Callback to be invoked on timer interrupt. - * arg - Argument to be passed to the handler callback. - * - * Returned Value: - * Zero (OK) is returned on success. A negated errno value is returned to - * indicate the nature of any failure. - * - ****************************************************************************/ - -static int rt_timer_isr(int irq, void *context, void *arg) -{ - irqstate_t flags; - bool wake = false; - struct esp32s3_rt_priv_s *priv = &g_rt_priv; - - /* Clear interrupt register status */ - - modifyreg32(SYSTIMER_INT_CLR_REG, 0, SYSTIMER_TARGET2_INT_CLR); - - flags = enter_critical_section(); - - /* Check if there is a timer running */ - - if (!list_is_empty(&priv->runlist)) - { - struct rt_timer_s *timer; - - /* When stop/delete timer, at the same time the hardware timer - * interrupt triggers, function "stop/delete" removes the timer - * from running list, so the timer at head is not is not the one being - * triggered. - */ - - uint64_t counter = rt_timer_getcounter(); - counter = CYCLES_TO_USEC(counter); - timer = container_of(priv->runlist.next, struct rt_timer_s, list); - if (timer->alarm <= counter) - { - /* Remove the first timer from the running list and add it to - * the timeout list. - * - * Set the timer's state to RT_TIMER_TIMEOUT to avoid any other - * operations. - */ - - list_delete(&timer->list); - timer->state = RT_TIMER_TIMEOUT; - list_add_after(&priv->toutlist, &timer->list); - wake = true; - - /* Check if there is a timer running */ - - if (!list_is_empty(&priv->runlist)) - { - /* Reset hardware timer alarm with next timer's alarm value */ - - timer = container_of(priv->runlist.next, - struct rt_timer_s, list); - - rt_timer_setalarm(false); - rt_timer_setalarmvalue(USEC_TO_CYCLES(timer->alarm)); - } - } - - /* If there is a timer in the list, the alarm should be enabled */ - - rt_timer_setalarm(true); - } - - if (wake) - { - /* Wake up the thread to process timed-out timers */ - - int ret = nxsem_post(&priv->toutsem); - if (ret < 0) - { - tmrerr("ERROR: Failed to post sem ret=%d\n", ret); - } - } - - leave_critical_section(flags); - - return OK; -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32s3_rt_timer_create - * - * Description: - * Create an RT Timer from the provided arguments. - * - * Input Parameters: - * args - RT Timer creation arguments. - * - * Output Parameters: - * timer_handle - Pointer to RT Timer handle. - * - * Returned Value: - * Zero (OK) is returned on success. A negated errno value is returned to - * indicate the nature of any failure. - * - ****************************************************************************/ - -int esp32s3_rt_timer_create(const struct rt_timer_args_s *args, - struct rt_timer_s **timer_handle) -{ - struct rt_timer_s *timer; - - DEBUGASSERT(args != NULL); - DEBUGASSERT(args->callback != NULL); - - timer = kmm_malloc(sizeof(*timer)); - if (timer == NULL) - { - tmrerr("ERROR: Failed to allocate %d bytes\n", sizeof(*timer)); - return -ENOMEM; - } - - timer->callback = args->callback; - timer->arg = args->arg; - timer->flags = RT_TIMER_NOFLAGS; - timer->state = RT_TIMER_IDLE; - list_initialize(&timer->list); - - *timer_handle = timer; - - return OK; -} - -/**************************************************************************** - * Name: esp32s3_rt_timer_start - * - * Description: - * Start the RT Timer. - * - * Input Parameters: - * timer - Pointer to the RT Timer state structure. - * timeout - Timeout value. - * repeat - Repeat mode (true: enabled, false: disabled). - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp32s3_rt_timer_start(struct rt_timer_s *timer, - uint64_t timeout, - bool repeat) -{ - irqstate_t flags; - struct esp32s3_rt_priv_s *priv = &g_rt_priv; - - flags = spin_lock_irqsave(&priv->lock); - - stop_rt_timer(timer); - - start_rt_timer(timer, timeout, repeat); - - spin_unlock_irqrestore(&priv->lock, flags); -} - -/**************************************************************************** - * Name: esp32s3_rt_timer_stop - * - * Description: - * Stop the RT Timer. - * - * Input Parameters: - * timer - Pointer to the RT Timer state structure. - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32s3_rt_timer_stop(struct rt_timer_s *timer) -{ - irqstate_t flags; - struct esp32s3_rt_priv_s *priv = &g_rt_priv; - - flags = spin_lock_irqsave(&priv->lock); - stop_rt_timer(timer); - spin_unlock_irqrestore(&priv->lock, flags); -} - -/**************************************************************************** - * Name: esp32s3_rt_timer_delete - * - * Description: - * Stop and delete the RT Timer. - * - * Delete the timer by removing it from the list, then set the timer's - * state to "RT_TIMER_DELETE" and finally insert it into the work list - * to let the RT Timer's thread to delete it and free the resources. - * - * Input Parameters: - * timer - Pointer to the RT Timer state structure. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp32s3_rt_timer_delete(struct rt_timer_s *timer) -{ - int ret; - irqstate_t flags; - struct esp32s3_rt_priv_s *priv = &g_rt_priv; - - flags = enter_critical_section(); - - if (timer->state == RT_TIMER_READY) - { - stop_rt_timer(timer); - } - else if (timer->state == RT_TIMER_TIMEOUT) - { - list_delete(&timer->list); - } - else if (timer->state == RT_TIMER_DELETE) - { - goto exit; - } - - list_add_after(&priv->toutlist, &timer->list); - timer->state = RT_TIMER_DELETE; - - /* Wake up the thread to process deleted timers */ - - ret = nxsem_post(&priv->toutsem); - if (ret < 0) - { - tmrerr("ERROR: Failed to post sem ret=%d\n", ret); - } - -exit: - leave_critical_section(flags); -} - -/**************************************************************************** - * Name: esp32s3_rt_timer_time_us - * - * Description: - * Get current counter value of the RT Timer in microseconds. - * - * Input Parameters: - * None. - * - * Returned Value: - * Time of the RT Timer in microseconds. - * - ****************************************************************************/ - -uint64_t IRAM_ATTR esp32s3_rt_timer_time_us(void) -{ - uint64_t counter = rt_timer_getcounter(); - counter = CYCLES_TO_USEC(counter); - - return counter; -} - -/**************************************************************************** - * Name: esp32s3_rt_timer_get_alarm - * - * Description: - * Get the remaining time to the next timeout. - * - * Input Parameters: - * None. - * - * Returned Value: - * Timestamp of the nearest timer event in microseconds. - * - ****************************************************************************/ - -uint64_t IRAM_ATTR esp32s3_rt_timer_get_alarm(void) -{ - irqstate_t flags; - uint64_t counter; - uint64_t alarm_value = 0; - struct esp32s3_rt_priv_s *priv = &g_rt_priv; - - flags = spin_lock_irqsave(&priv->lock); - - counter = rt_timer_getcounter(); - counter = CYCLES_TO_USEC(counter); - - alarm_value = rt_timer_getalarmvalue(); - alarm_value = CYCLES_TO_USEC(alarm_value); - - if (alarm_value <= counter) - { - alarm_value = 0; - } - else - { - alarm_value -= counter; - } - - spin_unlock_irqrestore(&priv->lock, flags); - - return alarm_value; -} - -/**************************************************************************** - * Name: esp32s3_rt_timer_calibration - * - * Description: - * Adjust current RT Timer by a certain value. - * - * Input Parameters: - * time_us - Adjustment to apply to the RT Timer in microseconds. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void IRAM_ATTR esp32s3_rt_timer_calibration(uint64_t time_us) -{ - irqstate_t flags; - uint64_t counter; - struct esp32s3_rt_priv_s *priv = &g_rt_priv; - - flags = spin_lock_irqsave(&priv->lock); - counter = rt_timer_getcounter(); - counter = CYCLES_TO_USEC(counter); - counter += time_us; - rt_timer_setcounter(USEC_TO_CYCLES(counter)); - spin_unlock_irqrestore(&priv->lock, flags); -} - -/**************************************************************************** - * Name: esp32s3_rt_timer_init - * - * Description: - * Initialize ESP32-S3 RT Timer. - * - * Input Parameters: - * None. - * - * Returned Value: - * Zero (OK) is returned on success. A negated errno value is returned to - * indicate the nature of any failure. - * - ****************************************************************************/ - -int esp32s3_rt_timer_init(void) -{ - int pid; - irqstate_t flags; - struct esp32s3_rt_priv_s *priv = &g_rt_priv; - - pid = kthread_create(RT_TIMER_TASK_NAME, - RT_TIMER_TASK_PRIORITY, - RT_TIMER_TASK_STACK_SIZE, - rt_timer_thread, - NULL); - if (pid < 0) - { - tmrerr("ERROR: Failed to create RT Timer task error=%d\n", pid); - return pid; - } - - list_initialize(&priv->runlist); - list_initialize(&priv->toutlist); - - priv->pid = (pid_t)pid; - - flags = enter_critical_section(); - - /* ESP32-S3 hardware timer configuration: - * 1 count = 1/16 us - * 1) Set Alarm mode (non-periodic). - * 2) Clear the counter. - * 3) Set the ISR. - * 4) Enable timeout interrupt. - * 5) Start the counter. - * NOTE: No interrupt will be triggered until rt_timer_setalarm is set. - */ - - /* Clock and reset of Systimer peripheral is already performed in - * up_timer_initialize(), either in esp32s3_timerisr.c or in - * esp32s3_tickless.c. - * Set comparator 2 to use counter 1 and set the mode to oneshot mode, - * i.e., disable periodic mode. - */ - - modifyreg32(SYSTIMER_TARGET2_CONF_REG, SYSTIMER_TARGET2_PERIOD_MODE, - SYSTIMER_TARGET2_TIMER_UNIT_SEL); - - rt_timer_setcounter(0); - rt_timer_setisr(rt_timer_isr, NULL); - - /* Ensure Systimer 1 keeps running even when the CPUs are temporarily - * stalled. - * This is required for the correct operation of the Wi-Fi driver. - */ - - modifyreg32(SYSTIMER_CONF_REG, SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN, 0); - modifyreg32(SYSTIMER_CONF_REG, SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN, 0); - - /* Enable interrupts */ - - modifyreg32(SYSTIMER_INT_CLR_REG, 0, SYSTIMER_TARGET2_INT_CLR); - modifyreg32(SYSTIMER_INT_ENA_REG, 0, SYSTIMER_TARGET2_INT_ENA); - - /* Start counter 1 */ - - modifyreg32(SYSTIMER_CONF_REG, 0, SYSTIMER_TIMER_UNIT1_WORK_EN); - - leave_critical_section(flags); - - return OK; -} - -/**************************************************************************** - * Name: esp32s3_rt_timer_deinit - * - * Description: - * Deinitialize ESP32-S3 RT Timer. - * - * Input Parameters: - * None. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp32s3_rt_timer_deinit(void) -{ - irqstate_t flags; - struct esp32s3_rt_priv_s *priv = &g_rt_priv; - - flags = spin_lock_irqsave(&priv->lock); - - /* Stop counter 1 */ - - modifyreg32(SYSTIMER_CONF_REG, SYSTIMER_TIMER_UNIT1_WORK_EN, 0); - - /* Disable interrupts */ - - modifyreg32(SYSTIMER_INT_ENA_REG, SYSTIMER_TARGET2_INT_ENA, 0); - modifyreg32(SYSTIMER_INT_CLR_REG, SYSTIMER_TARGET2_INT_CLR, 0); - - rt_timer_setisr(NULL, NULL); - - spin_unlock_irqrestore(&priv->lock, flags); - - if (priv->pid != INVALID_PROCESS_ID) - { - kthread_delete(priv->pid); - priv->pid = INVALID_PROCESS_ID; - } -} diff --git a/arch/xtensa/src/esp32s3/esp32s3_rt_timer.h b/arch/xtensa/src/esp32s3/esp32s3_rt_timer.h deleted file mode 100644 index 5bf725ea39ef7..0000000000000 --- a/arch/xtensa/src/esp32s3/esp32s3_rt_timer.h +++ /dev/null @@ -1,244 +0,0 @@ -/**************************************************************************** - * arch/xtensa/src/esp32s3/esp32s3_rt_timer.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_RT_TIMER_H -#define __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_RT_TIMER_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include - -#include -#include - -#include - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -#define RT_TIMER_NOFLAGS (0) /* Timer supports no feature */ -#define RT_TIMER_REPEAT (1 << 0) /* Timer supports repeat mode */ - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/* RT timer state */ - -enum rt_timer_state_e -{ - RT_TIMER_IDLE, /* Timer is not counting */ - RT_TIMER_READY, /* Timer is counting */ - RT_TIMER_TIMEOUT, /* Timer timed out */ - RT_TIMER_DELETE /* Timer is to be delete */ -}; - -/* RT timer data structure */ - -struct rt_timer_s -{ - uint64_t timeout; /* Timeout value */ - uint64_t alarm; /* Timeout period */ - void (*callback)(void *arg); /* Callback function */ - void *arg; /* Private data */ - uint16_t flags; /* Supported features */ - enum rt_timer_state_e state; /* Timer state */ - struct list_node list; /* Working list */ -}; - -/* RT timer creation arguments data structure */ - -struct rt_timer_args_s -{ - void (*callback)(void *arg); /* Callback function */ - void *arg; /* Private data */ -}; - -#if defined(__cplusplus) -extern "C" -{ -#endif - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32s3_rt_timer_create - * - * Description: - * Create an RT Timer from the provided arguments. - * - * Input Parameters: - * args - RT Timer creation arguments. - * - * Output Parameters: - * timer_handle - Pointer to RT Timer handle. - * - * Returned Value: - * Zero (OK) is returned on success. A negated errno value is returned to - * indicate the nature of any failure. - * - ****************************************************************************/ - -int esp32s3_rt_timer_create(const struct rt_timer_args_s *args, - struct rt_timer_s **timer_handle); - -/**************************************************************************** - * Name: esp32s3_rt_timer_start - * - * Description: - * Start the RT Timer. - * - * Input Parameters: - * timer - Pointer to the RT Timer state structure. - * timeout - Timeout value. - * repeat - Repeat mode (true: enabled, false: disabled). - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp32s3_rt_timer_start(struct rt_timer_s *timer, - uint64_t timeout, - bool repeat); - -/**************************************************************************** - * Name: esp32s3_rt_timer_stop - * - * Description: - * Stop the RT Timer. - * - * Input Parameters: - * timer - Pointer to the RT Timer state structure. - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32s3_rt_timer_stop(struct rt_timer_s *timer); - -/**************************************************************************** - * Name: esp32s3_rt_timer_delete - * - * Description: - * Stop and delete the RT Timer. - * - * Input Parameters: - * timer - Pointer to the RT Timer state structure. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp32s3_rt_timer_delete(struct rt_timer_s *timer); - -/**************************************************************************** - * Name: esp32s3_rt_timer_time_us - * - * Description: - * Get current counter value of the RT Timer in microseconds. - * - * Input Parameters: - * None. - * - * Returned Value: - * Time of the RT Timer in microseconds. - * - ****************************************************************************/ - -uint64_t esp32s3_rt_timer_time_us(void); - -/**************************************************************************** - * Name: esp32s3_rt_timer_get_alarm - * - * Description: - * Get the remaining time to the next timeout. - * - * Input Parameters: - * None. - * - * Returned Value: - * Timestamp of the nearest timer event in microseconds. - * - ****************************************************************************/ - -uint64_t esp32s3_rt_timer_get_alarm(void); - -/**************************************************************************** - * Name: esp32s3_rt_timer_calibration - * - * Description: - * Adjust current RT Timer by a certain value. - * - * Input Parameters: - * time_us - Adjustment to apply to the RT Timer in microseconds. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp32s3_rt_timer_calibration(uint64_t time_us); - -/**************************************************************************** - * Name: esp32s3_rt_timer_init - * - * Description: - * Initialize ESP32-S3 RT Timer. - * - * Input Parameters: - * None. - * - * Returned Value: - * Zero (OK) is returned on success. A negated errno value is returned to - * indicate the nature of any failure. - * - ****************************************************************************/ - -int esp32s3_rt_timer_init(void); - -/**************************************************************************** - * Name: esp32s3_rt_timer_deinit - * - * Description: - * Deinitialize ESP32-S3 RT Timer. - * - * Input Parameters: - * None. - * - * Returned Value: - * None. - * - ****************************************************************************/ - -void esp32s3_rt_timer_deinit(void); - -#ifdef __cplusplus -} -#endif - -#endif /* __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_RT_TIMER_H */ diff --git a/arch/xtensa/src/esp32s3/esp32s3_rtc.c b/arch/xtensa/src/esp32s3/esp32s3_rtc.c deleted file mode 100644 index 1ec45adc91aaf..0000000000000 --- a/arch/xtensa/src/esp32s3/esp32s3_rtc.c +++ /dev/null @@ -1,3112 +0,0 @@ -/**************************************************************************** - * arch/xtensa/src/esp32s3/esp32s3_rtc.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include - -#include -#include - -#include "clock/clock.h" - -#include "esp32s3_clockconfig.h" -#include "esp32s3_rt_timer.h" -#include "esp32s3_reset_reasons.h" - -#include "hardware/esp32s3_bb.h" -#include "hardware/esp32s3_nrx.h" -#include "hardware/esp32s3_fe.h" -#include "hardware/esp32s3_rtccntl.h" -#include "hardware/esp32s3_rtc_io.h" -#include "hardware/esp32s3_system.h" -#include "hardware/esp32s3_tim.h" -#include "hardware/esp32s3_apb_ctrl.h" -#include "hardware/regi2c_dig_reg.h" -#include "hardware/regi2c_ctrl.h" -#include "hardware/esp32s3_syscon.h" -#include "hardware/regi2c_bbpll.h" -#include "hardware/regi2c_lp_bias.h" - -#include "xtensa.h" -#include "esp_attr.h" -#include "soc/extmem_reg.h" -#include "soc/spi_mem_reg.h" - -#include "esp32s3_rtc.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Various delays to be programmed into power control state machines */ - -#define RTC_CNTL_XTL_BUF_WAIT_SLP 2 -#define RTC_CNTL_CK8M_WAIT_SLP 4 -#define OTHER_BLOCKS_POWERUP 1 -#define OTHER_BLOCKS_WAIT 1 - -#define ROM_RAM_POWERUP_CYCLES OTHER_BLOCKS_POWERUP -#define ROM_RAM_WAIT_CYCLES OTHER_BLOCKS_WAIT - -#define WIFI_POWERUP_CYCLES OTHER_BLOCKS_POWERUP -#define WIFI_WAIT_CYCLES OTHER_BLOCKS_WAIT - -#define RTC_POWERUP_CYCLES OTHER_BLOCKS_POWERUP -#define RTC_WAIT_CYCLES OTHER_BLOCKS_WAIT - -#define DG_WRAP_POWERUP_CYCLES OTHER_BLOCKS_POWERUP -#define DG_WRAP_WAIT_CYCLES OTHER_BLOCKS_WAIT - -#define RTC_MEM_POWERUP_CYCLES OTHER_BLOCKS_POWERUP -#define RTC_MEM_WAIT_CYCLES OTHER_BLOCKS_WAIT - -#define RTC_CNTL_PLL_BUF_WAIT_SLP 2 - -#define DELAY_FAST_CLK_SWITCH 3 - -#define XTAL_32K_DAC_VAL 1 -#define XTAL_32K_DRES_VAL 3 -#define XTAL_32K_DBIAS_VAL 0 - -#define XTAL_32K_EXT_DAC_VAL 2 -#define XTAL_32K_EXT_DRES_VAL 3 -#define XTAL_32K_EXT_DBIAS_VAL 1 - -#define DELAY_SLOW_CLK_SWITCH 300 - -#define DELAY_8M_ENABLE 50 - -#define RETRY_CAL_EXT 1 - -#define CLK_LL_PLL_80M_FREQ_MHZ (80) -#define CLK_LL_PLL_160M_FREQ_MHZ (160) -#define CLK_LL_PLL_240M_FREQ_MHZ (240) - -/* Lower threshold for a reasonably-looking calibration value for a 32k XTAL. - * The ideal value (assuming 32768 Hz frequency) - * is 1000000/32768*(2**19) = 16*10^6. - */ - -#define MIN_32K_XTAL_CAL_VAL 15000000L - -/* Frequency of the 8M oscillator is 8.5MHz +/- 5%, at the default DCAP - * setting - */ - -#define RTC_FAST_CLK_FREQ_APPROX 17500000 -#define RCT_FAST_D256_FREQ_APPROX (RTC_FAST_CLK_FREQ_APPROX / 256) -#define RTC_SLOW_CLK_FREQ_APPROX 32768 - -/* Disable logging from the ROM code. */ - -#define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16)) - -/* Set sleep_init default param */ - -#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT (5) -#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP (0) -#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT (14) -#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_ULTRA_LOW (15) -#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_NODROP (0) -#define RTC_CNTL_BIASSLP_SLEEP_DEFAULT (1) -#define RTC_CNTL_BIASSLP_SLEEP_ON (0) -#define RTC_CNTL_PD_CUR_SLEEP_DEFAULT (1) -#define RTC_CNTL_PD_CUR_SLEEP_ON (0) -#define RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT (0xf) - -#define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT (0) -#define RTC_CNTL_BIASSLP_MONITOR_DEFAULT (1) -#define RTC_CNTL_BIASSLP_MONITOR_ON (0) -#define RTC_CNTL_PD_CUR_MONITOR_DEFAULT (1) -#define RTC_CNTL_PD_CUR_MONITOR_ON (0) - -/* Set LDO slave during CPU switch */ - -#define DEFAULT_LDO_SLAVE 0x7 - -/* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP, - * RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values. - * Valid if RTC_CNTL_DBG_ATTEN is 0. - */ - -#define RTC_CNTL_DBIAS_SLP 0 /* sleep dig_dbias & rtc_dbias */ -#define RTC_CNTL_DBIAS_0V90 13 /* digital voltage */ -#define RTC_CNTL_DBIAS_0V95 16 -#define RTC_CNTL_DBIAS_1V00 18 -#define RTC_CNTL_DBIAS_1V05 20 -#define RTC_CNTL_DBIAS_1V10 23 -#define RTC_CNTL_DBIAS_1V15 25 -#define RTC_CNTL_DBIAS_1V20 28 -#define RTC_CNTL_DBIAS_1V25 30 -#define RTC_CNTL_DBIAS_1V30 31 /* voltage is about 1.34v in fact */ - -/* Default initializer for esp32s3_rtc_sleep_config_t - * This initializer sets all fields to "reasonable" values - * (e.g. suggested for production use) based on a combination - * of RTC_SLEEP_PD_x flags. - */ - -#define is_dslp(pd_flags) ((pd_flags) & RTC_SLEEP_PD_DIG) - -#define RTC_SLEEP_CONFIG_DEFAULT(sleep_flags) { \ - .lslp_mem_inf_fpu = 0, \ - .rtc_mem_inf_follow_cpu = ((sleep_flags) & RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU) ? 1 : 0, \ - .rtc_fastmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_FAST_MEM) ? 1 : 0, \ - .rtc_slowmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_SLOW_MEM) ? 1 : 0, \ - .rtc_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_PERIPH) ? 1 : 0, \ - .wifi_pd_en = ((sleep_flags) & RTC_SLEEP_PD_WIFI) ? 1 : 0, \ - .bt_pd_en = ((sleep_flags) & RTC_SLEEP_PD_BT) ? 1 : 0, \ - .cpu_pd_en = ((sleep_flags) & RTC_SLEEP_PD_CPU) ? 1 : 0, \ - .int_8m_pd_en = ((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? 1 : 0, \ - .dig_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_DIG_PERIPH) ? 1 : 0, \ - .deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, \ - .wdt_flashboot_mod_en = 0, \ - .vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, \ - .xtal_fpu = ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1, \ - .deep_slp_reject = 1, \ - .light_slp_reject = 1, \ - .rtc_dbias_slp = RTC_CNTL_DBIAS_1V10, \ -} - -#define X32K_CONFIG_DEFAULT() { \ - .dac = 3, \ - .dres = 3, \ - .dgm = 3, \ - .dbuf = 1, \ -} - -/* Initializer for rtc_sleep_pu_config_t which sets all flags - * to the same value - */ - -#define RTC_SLEEP_PU_CONFIG_ALL(val) {\ - .dig_fpu = (val), \ - .rtc_fpu = (val), \ - .cpu_fpu = (val), \ - .i2s_fpu = (val), \ - .bb_fpu = (val), \ - .nrx_fpu = (val), \ - .fe_fpu = (val), \ - .sram_fpu = (val), \ - .rom_ram_fpu = (val), \ -} - -/* Default initializer of struct esp32s3_rtc_config_s. - * This initializer sets all fields to "reasonable" values - * (e.g. suggested for production use). - */ - -#define RTC_CONFIG_DEFAULT() {\ - .ck8m_wait = RTC_CNTL_CK8M_WAIT_DEFAULT, \ - .xtal_wait = RTC_CNTL_XTL_BUF_WAIT_DEFAULT, \ - .pll_wait = RTC_CNTL_PLL_BUF_WAIT_DEFAULT, \ - .clkctl_init = 1, \ - .pwrctl_init = 1, \ - .rtc_dboost_fpd = 1, \ - .xtal_fpu = 0, \ - .bbpll_fpu = 0, \ - .cpu_waiti_clk_gate = 1, \ - .cali_ocode = 0 \ -} - -/* The magic data for the struct esp32s3_rtc_backup_s that is in RTC slow - * memory. - */ - -#define MAGIC_RTC_SAVE UINT64_C(0x11223344556677) - -/* RTC Memory & Store Register usage */ - -#define RTC_SLOW_CLK_CAL_REG RTC_CNTL_RTC_STORE1_REG /* RTC_SLOW_CLK calibration value */ -#define RTC_BOOT_TIME_LOW_REG RTC_CNTL_RTC_STORE2_REG /* Boot time, low word */ -#define RTC_BOOT_TIME_HIGH_REG RTC_CNTL_RTC_STORE3_REG /* Boot time, high word */ -#define RTC_XTAL_FREQ_REG RTC_CNTL_RTC_STORE4_REG /* External XTAL frequency */ -#define RTC_APB_FREQ_REG RTC_CNTL_RTC_STORE5_REG /* APB bus frequency */ -#define RTC_ENTRY_ADDR_REG RTC_CNTL_RTC_STORE6_REG /* FAST_RTC_MEMORY_ENTRY */ -#define RTC_RESET_CAUSE_REG RTC_CNTL_RTC_STORE6_REG -#define RTC_MEMORY_CRC_REG RTC_CNTL_RTC_STORE7_REG /* FAST_RTC_MEMORY_CRC */ - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -/* RTC power and clock control initialization settings */ - -struct esp32s3_rtc_priv_s -{ - uint32_t ck8m_wait : 8; /* Number of rtc_fast_clk cycles to wait for 8M clock to be ready */ - uint32_t xtal_wait : 8; /* Number of rtc_fast_clk cycles to wait for XTAL clock to be ready */ - uint32_t pll_wait : 8; /* Number of rtc_fast_clk cycles to wait for PLL to be ready */ - uint32_t clkctl_init : 1; /* Perform clock control related initialization */ - uint32_t pwrctl_init : 1; /* Perform power control related initialization */ - uint32_t rtc_dboost_fpd : 1; /* Force power down RTC_DBOOST */ - uint32_t xtal_fpu : 1; - uint32_t bbpll_fpu : 1; - uint32_t cpu_waiti_clk_gate : 1; - uint32_t cali_ocode : 1; /* Calibrate Ocode to make bangap voltage more precise */ -}; - -/* sleep configuration for rtc_sleep_init function */ - -struct esp32s3_rtc_sleep_config_s -{ - uint32_t lslp_mem_inf_fpu : 1; /* force normal voltage in sleep mode (digital domain memory) */ - uint32_t rtc_mem_inf_follow_cpu : 1; /* keep low voltage in sleep mode (even if ULP/touch is used) */ - uint32_t rtc_fastmem_pd_en : 1; /* power down RTC fast memory */ - uint32_t rtc_slowmem_pd_en : 1; /* power down RTC slow memory */ - uint32_t rtc_peri_pd_en : 1; /* power down RTC peripherals */ - uint32_t wifi_pd_en : 1; /* power down Wi-Fi */ - uint32_t bt_pd_en : 1; /* power down BT */ - uint32_t cpu_pd_en : 1; /* power down CPU, but not restart when lightsleep */ - uint32_t int_8m_pd_en : 1; /* power down internal 8MHz oscillator */ - uint32_t dig_peri_pd_en : 1; /* power down digital peripherals */ - uint32_t deep_slp : 1; /* power down digital domain */ - uint32_t wdt_flashboot_mod_en : 1; /* enable WDT flashboot mode */ - uint32_t dig_dbias_slp : 5; /* set bias for digital domain, in sleep mode */ - uint32_t rtc_dbias_slp : 5; /* set bias for RTC domain, in sleep mode */ - uint32_t bias_sleep_monitor : 1; /* circuit control parameter, in monitor mode */ - uint32_t dbg_atten_slp : 4; /* voltage parameter, in sleep mode */ - uint32_t bias_sleep_slp : 1; /* circuit control parameter, in sleep mode */ - uint32_t pd_cur_monitor : 1; /* circuit control parameter, in monitor mode */ - uint32_t pd_cur_slp : 1; /* circuit control parameter, in sleep mode */ - uint32_t vddsdio_pd_en : 1; /* power down VDDSDIO regulator */ - uint32_t xtal_fpu : 1; /* keep main XTAL powered up in sleep */ - uint32_t rtc_regulator_fpu : 1; /* keep rtc regulator powered up in sleep */ - uint32_t deep_slp_reject : 1; - uint32_t light_slp_reject : 1; -}; - -/* Power up flags for rtc_sleep_pu function */ - -struct esp32s3_rtc_sleep_pu_config_s -{ - uint32_t dig_fpu : 1; /* Set to 1 to power UP digital part in sleep */ - uint32_t rtc_fpu : 1; /* Set to 1 to power UP RTC memories in sleep */ - uint32_t cpu_fpu : 1; /* Set to 1 to power UP digital memories and CPU in sleep */ - uint32_t i2s_fpu : 1; /* Set to 1 to power UP I2S in sleep */ - uint32_t bb_fpu : 1; /* Set to 1 to power UP WiFi in sleep */ - uint32_t nrx_fpu : 1; /* Set to 1 to power UP WiFi in sleep */ - uint32_t fe_fpu : 1; /* Set to 1 to power UP WiFi in sleep */ - uint32_t sram_fpu : 1; /* Set to 1 to power UP SRAM in sleep */ - uint32_t rom_ram_fpu : 1; /* Set to 1 to power UP ROM/IRAM0_DRAM0 in sleep */ -}; - -/* crystal configuration */ - -struct esp32s3_rtc_x32k_config_s -{ - uint32_t dac : 6; - uint32_t dres : 3; - uint32_t dgm : 3; - uint32_t dbuf: 1; -}; - -#ifdef CONFIG_RTC_ALARM -struct alm_cbinfo_s -{ - struct rt_timer_s *alarm_hdl; /* Timer id point to here */ - volatile alm_callback_t ac_cb; /* Client callback function */ - volatile void *ac_arg; /* Argument to pass with the callback function */ - uint64_t deadline_us; - uint8_t index; -}; -#endif - -struct esp32s3_rtc_backup_s -{ - uint64_t magic; - int64_t offset; /* Offset time from RTC HW value */ - int64_t reserved0; -}; - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* APB Frequency */ - -static uint32_t g_apb_freq; - -/* Callback to use when the alarm expires */ - -#ifdef CONFIG_RTC_ALARM -static struct alm_cbinfo_s g_alarmcb[RTC_ALARM_LAST]; -#endif - -static RTC_DATA_ATTR struct esp32s3_rtc_backup_s rtc_saved_data; - -/* Saved data for persistent RTC time */ - -static struct esp32s3_rtc_backup_s *g_rtc_save; -static bool g_rt_timer_enabled = false; -static uint32_t g_dig_dbias_pvt_240m = 28; -static uint32_t g_rtc_dbias_pvt_240m = 28; -static uint32_t g_dig_dbias_pvt_non_240m = 27; -static uint32_t g_rtc_dbias_pvt_non_240m = 27; - -static spinlock_t g_rtc_lock = SP_UNLOCKED; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -static void IRAM_ATTR esp32s3_rtc_sleep_pu( - struct esp32s3_rtc_sleep_pu_config_s cfg); -static inline bool esp32s3_clk_val_is_valid(uint32_t val); -static void IRAM_ATTR esp32s3_rtc_clk_fast_freq_set( - enum esp32s3_rtc_fast_freq_e fast_freq); -static uint32_t IRAM_ATTR esp32s3_rtc_clk_cal_internal( - enum esp32s3_rtc_cal_sel_e cal_clk, - uint32_t slowclk_cycles); -static void IRAM_ATTR esp32s3_rtc_clk_slow_freq_set( - enum esp32s3_rtc_slow_freq_e slow_freq); -static void esp32s3_select_rtc_slow_clk(enum esp32s3_slow_clk_sel_e - slow_clk); -static void esp32s3_rtc_clk_32k_enable(bool enable); -static void IRAM_ATTR esp32s3_rtc_clk_8m_enable(bool clk_8m_en, - bool d256_en); -static void esp32s3_rtc_calibrate_ocode(void); -static void IRAM_ATTR esp32s3_rtc_bbpll_disable(void); -static void IRAM_ATTR esp32s3_rtc_bbpll_enable(void); -static void IRAM_ATTR esp32s3_rtc_bbpll_configure( - enum esp32s3_rtc_xtal_freq_e xtal_freq, int pll_freq); -static void IRAM_ATTR esp32s3_rtc_clk_cpu_freq_to_8m(void); -static void IRAM_ATTR esp32s3_rtc_clk_cpu_freq_to_pll_mhz( - int cpu_freq_mhz); -void esp32s3_rtc_clk_apb_freq_update(uint32_t apb_freq); -void IRAM_ATTR esp32s3_rtc_update_to_xtal(int freq, int div); -uint32_t esp32s3_rtc_clk_apb_freq_get(void); - -#ifdef CONFIG_RTC_ALARM -static void IRAM_ATTR esp32s3_rt_cb_handler(void *arg); -#endif -/**************************************************************************** - * Public Data - ****************************************************************************/ - -volatile bool g_rtc_enabled = false; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/* Set the real CPU ticks per us to the ets, so that ets_delay_us - * will be accurate. Call this function when CPU frequency is changed. - */ - -extern void ets_update_cpu_frequency(uint32_t ticks_per_us); - -/* Pauses execution for us microseconds */ - -extern void esp_rom_delay_us(uint32_t us); - -/* Get the reset reason for CPU. */ - -extern soc_reset_reason_t esp_rom_get_reset_reason(int cpu_no); - -/**************************************************************************** - * Name: esp32s3_rtc_sleep_pu - * - * Description: - * Configure whether certain peripherals are powered up in deep sleep. - * - * Input Parameters: - * cfg - Power down flags as rtc_sleep_pu_config_t structure - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void IRAM_ATTR - esp32s3_rtc_sleep_pu(struct esp32s3_rtc_sleep_pu_config_s cfg) -{ - REG_SET_FIELD(RTC_CNTL_DIG_PWC_REG, - RTC_CNTL_LSLP_MEM_FORCE_PU, cfg.dig_fpu); - REG_SET_FIELD(RTC_CNTL_RTC_PWC_REG, - RTC_CNTL_RTC_FASTMEM_FORCE_LPU, cfg.rtc_fpu); - REG_SET_FIELD(RTC_CNTL_RTC_PWC_REG, - RTC_CNTL_RTC_SLOWMEM_FORCE_LPU, cfg.rtc_fpu); - REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG, - SYSCON_DC_MEM_FORCE_PU, cfg.fe_fpu); - REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG, - SYSCON_PBUS_MEM_FORCE_PU, cfg.fe_fpu); - REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG, - SYSCON_AGC_MEM_FORCE_PU, cfg.fe_fpu); - REG_SET_FIELD(BBPD_CTRL, BB_FFT_FORCE_PU, cfg.bb_fpu); - REG_SET_FIELD(BBPD_CTRL, BB_DC_EST_FORCE_PU, cfg.bb_fpu); - REG_SET_FIELD(NRXPD_CTRL, NRX_RX_ROT_FORCE_PU, cfg.nrx_fpu); - REG_SET_FIELD(NRXPD_CTRL, NRX_VIT_FORCE_PU, cfg.nrx_fpu); - REG_SET_FIELD(NRXPD_CTRL, NRX_DEMAP_FORCE_PU, cfg.nrx_fpu); - REG_SET_FIELD(FE_GEN_CTRL, FE_IQ_EST_FORCE_PU, cfg.fe_fpu); - REG_SET_FIELD(FE2_TX_INTERP_CTRL, FE2_TX_INF_FORCE_PU, cfg.fe_fpu); - - if (cfg.sram_fpu) - { - REG_SET_FIELD(SYSCON_MEM_POWER_UP_REG, - SYSCON_SRAM_POWER_UP, SYSCON_SRAM_POWER_UP); - } - else - { - REG_SET_FIELD(SYSCON_MEM_POWER_UP_REG, SYSCON_SRAM_POWER_UP, 0); - } - - if (cfg.rom_ram_fpu) - { - REG_SET_FIELD(SYSCON_MEM_POWER_UP_REG, SYSCON_ROM_POWER_UP, - SYSCON_ROM_POWER_UP); - } - else - { - REG_SET_FIELD(SYSCON_MEM_POWER_UP_REG, SYSCON_ROM_POWER_UP, 0); - } -} - -/**************************************************************************** - * Name: esp32s3_rtc_clk_fast_freq_set - * - * Description: - * Select source for RTC_FAST_CLK. - * - * Input Parameters: - * cfg - Clock source (one of enum esp32s3_rtc_fast_freq_e values) - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void IRAM_ATTR esp32s3_rtc_clk_fast_freq_set( - enum esp32s3_rtc_fast_freq_e fast_freq) -{ - REG_SET_FIELD(RTC_CNTL_RTC_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL, - fast_freq); - up_udelay(DELAY_FAST_CLK_SWITCH); -} - -/**************************************************************************** - * Name: esp32s3_clk_val_is_valid - * - * Description: - * Values of RTC_XTAL_FREQ_REG and RTC_APB_FREQ_REG are - * stored as two copies in lower and upper 16-bit halves. - * These are the routines to work with such a representation. - * - * Input Parameters: - * val - Register value - * - * Returned Value: - * true: Valid register value. - * false: Invalid register value. - * - ****************************************************************************/ - -static inline bool esp32s3_clk_val_is_valid(uint32_t val) -{ - return (val & 0xffff) == ((val >> 16) & 0xffff) - && val != 0 && val != UINT32_MAX; -} - -/**************************************************************************** - * Name: esp32s3_rtc_clk_cal_internal - * - * Description: - * Clock calibration function used by rtc_clk_cal and rtc_clk_cal_ratio - * - * Input Parameters: - * cal_clk - Which clock to calibrate - * slowclk_cycles - Number of slow clock cycles to count. - * - * Returned Value: - * Number of XTAL clock cycles within the given number of slow clock - * cycles. - * In case of error, return 0 cycle. - * - ****************************************************************************/ - -static uint32_t IRAM_ATTR esp32s3_rtc_clk_cal_internal( - enum esp32s3_rtc_cal_sel_e cal_clk, uint32_t slowclk_cycles) -{ - uint32_t expected_freq; - uint32_t us_time_estimate; - uint32_t clks_state; - uint32_t clks_mask; - uint32_t cal_val; - enum esp32s3_rtc_slow_freq_e slow_freq; - - /* Get the current state */ - - clks_mask = (RTC_CNTL_DIG_XTAL32K_EN_M | RTC_CNTL_DIG_CLK8M_D256_EN_M); - clks_state = getreg32(RTC_CNTL_RTC_CLK_CONF_REG); - clks_state &= clks_mask; - - /* On ESP32S3, choosing RTC_CAL_RTC_MUX results in calibration of - * the 150k RTC clock regardless of the currently selected SLOW_CLK. - * The following code emulates ESP32 behavior - */ - - if (cal_clk == RTC_CAL_RTC_MUX) - { - slow_freq = esp32s3_rtc_clk_slow_freq_get(); - if (slow_freq == RTC_SLOW_FREQ_32K_XTAL) - { - cal_clk = RTC_CAL_32K_XTAL; - } - else if (slow_freq == RTC_SLOW_FREQ_8MD256) - { - cal_clk = RTC_CAL_8MD256; - } - } - else if (cal_clk == RTC_CAL_INTERNAL_OSC) - { - cal_clk = RTC_CAL_RTC_MUX; - } - - /* Enable requested clock (150k clock is always on) */ - - if (cal_clk == RTC_CAL_32K_XTAL && !(clks_state & RTC_CNTL_DIG_XTAL32K_EN)) - { - REG_SET_FIELD(RTC_CNTL_RTC_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN, 1); - } - else if (cal_clk == RTC_CAL_8MD256 && - !(clks_state & RTC_CNTL_DIG_CLK8M_D256_EN)) - { - modifyreg32(RTC_CNTL_RTC_CLK_CONF_REG, 0, RTC_CNTL_DIG_CLK8M_D256_EN); - } - - /* Prepare calibration */ - - REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, cal_clk); - modifyreg32(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING, 0); - REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, slowclk_cycles); - - /* Figure out how long to wait for calibration to finish */ - - slow_freq = REG_GET_FIELD(RTC_CNTL_RTC_CLK_CONF_REG, - RTC_CNTL_ANA_CLK_RTC_SEL); - - if (cal_clk == RTC_CAL_32K_XTAL || slow_freq == RTC_SLOW_FREQ_32K_XTAL) - { - expected_freq = 32768; /* Standard 32k XTAL */ - } - else if (cal_clk == RTC_CAL_8MD256 || slow_freq == RTC_SLOW_FREQ_8MD256) - { - expected_freq = RTC_FAST_CLK_FREQ_APPROX / 256; - } - else - { - expected_freq = 150000; /* 150k internal oscillator */ - } - - us_time_estimate = (uint32_t) (((uint64_t)slowclk_cycles) * - MHZ / expected_freq); - - /* Start calibration */ - - modifyreg32(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START, 0); - modifyreg32(TIMG_RTCCALICFG_REG(0), 0, TIMG_RTC_CALI_START); - - /* Wait the expected time calibration should take */ - - up_udelay(us_time_estimate); - - /* Wait for calibration to finish up to another us_time_estimate */ - - while (true) - { - if (getreg32(TIMG_RTCCALICFG_REG(0)) & TIMG_RTC_CALI_RDY) - { - cal_val = REG_GET_FIELD(TIMG_RTCCALICFG1_REG(0), - TIMG_RTC_CALI_VALUE); - break; - } - - if (GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT)) - { - cal_val = 0; - break; - } - } - - CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START); - - /* Restore the previous clocks states */ - - modifyreg32(RTC_CNTL_RTC_CLK_CONF_REG, clks_mask, clks_state); - - return cal_val; -} - -/**************************************************************************** - * Name: esp32s3_rtc_update_to_xtal - * - * Description: - * Switch to XTAL frequency, does not disable the PLL - * - * Input Parameters: - * freq - XTAL frequency - * div - REF_TICK divider - * - * Returned Value: - * none - * - ****************************************************************************/ - -void IRAM_ATTR esp32s3_rtc_update_to_xtal(int freq, int div) -{ - struct esp32s3_cpu_freq_config_s cur_config = - { - 0 - }; - - esp32s3_rtc_clk_cpu_freq_get_config(&cur_config); - ets_update_cpu_frequency(freq); - - /* Set divider from XTAL to APB clock. - * Need to set divider to 1 (reg. value 0) first. - */ - - REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT, 0); - REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT, div - 1); - - /* No need to adjust the REF_TICK. - * Switch clock source. - */ - - REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, - SYSTEM_SOC_CLK_SEL, DPORT_SOC_CLK_SEL_XTAL); - - esp32s3_rtc_clk_apb_freq_update(freq * MHZ); - - if (cur_config.freq_mhz == 240) - { - REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, - g_rtc_dbias_pvt_non_240m); - REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, - g_dig_dbias_pvt_non_240m); - esp_rom_delay_us(40); - } - - REG_SET_FIELD(RTC_CNTL_DATE_REG, RTC_CNTL_SLAVE_PD, DEFAULT_LDO_SLAVE); -} - -/**************************************************************************** - * Name: esp32s3_rtc_clk_slow_freq_set - * - * Description: - * Select source for RTC_SLOW_CLK - * - * Input Parameters: - * slow_freq - Select source for RTC_SLOW_CLK - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void IRAM_ATTR esp32s3_rtc_clk_slow_freq_set( - enum esp32s3_rtc_slow_freq_e slow_freq) -{ - REG_SET_FIELD(RTC_CNTL_RTC_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL, - slow_freq); - - REG_SET_FIELD(RTC_CNTL_RTC_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN, - (slow_freq == RTC_SLOW_FREQ_32K_XTAL) ? 1 : 0); - - up_udelay(DELAY_SLOW_CLK_SWITCH); -} - -/**************************************************************************** - * Name: esp32s3_rtc_clk_32k_enable - * - * Description: - * Enable 32 kHz XTAL oscillator - * - * Input Parameters: - * enable - True to enable, false to disable - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void IRAM_ATTR esp32s3_rtc_clk_32k_enable(bool enable) -{ - if (enable) - { - struct esp32s3_rtc_x32k_config_s cfg = X32K_CONFIG_DEFAULT(); - - modifyreg32(RTCIO_XTAL_32P_PAD_REG, 0, RTCIO_X32P_MUX_SEL); - modifyreg32(RTCIO_XTAL_32N_PAD_REG, 0, RTCIO_X32N_MUX_SEL); - - REG_SET_FIELD(RTC_CNTL_RTC_EXT_XTL_CONF_REG, - RTC_CNTL_DAC_XTAL_32K, cfg.dac); - REG_SET_FIELD(RTC_CNTL_RTC_EXT_XTL_CONF_REG, - RTC_CNTL_DRES_XTAL_32K, cfg.dres); - REG_SET_FIELD(RTC_CNTL_RTC_EXT_XTL_CONF_REG, - RTC_CNTL_DGM_XTAL_32K, cfg.dgm); - REG_SET_FIELD(RTC_CNTL_RTC_EXT_XTL_CONF_REG, - RTC_CNTL_DBUF_XTAL_32K, cfg.dbuf); - modifyreg32(RTC_CNTL_RTC_EXT_XTL_CONF_REG, 0, - RTC_CNTL_XPD_XTAL_32K); - } - else - { - modifyreg32(RTC_CNTL_RTC_EXT_XTL_CONF_REG, RTC_CNTL_XPD_XTAL_32K, - RTC_CNTL_XTAL32K_XPD_FORCE); - } -} - -/**************************************************************************** - * Name: esp32s3_rtc_clk_8m_enable - * - * Description: - * Enable or disable 8 MHz internal oscillator - * - * Input Parameters: - * clk_8m_en - True to enable 8MHz generator, false to disable - * d256_en - True to enable /256 divider, false to disable - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void IRAM_ATTR esp32s3_rtc_clk_8m_enable(bool clk_8m_en, bool d256_en) -{ - if (clk_8m_en) - { - modifyreg32(RTC_CNTL_RTC_CLK_CONF_REG, RTC_CNTL_ENB_CK8M, 0); - - /* no need to wait once enabled by software */ - - REG_SET_FIELD(RTC_CNTL_RTC_TIMER1_REG, RTC_CNTL_CK8M_WAIT, 1); - if (d256_en) - { - modifyreg32(RTC_CNTL_RTC_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV, 0); - } - else - { - modifyreg32(RTC_CNTL_RTC_CLK_CONF_REG, 0, RTC_CNTL_ENB_CK8M_DIV); - } - - up_udelay(DELAY_8M_ENABLE); - } - else - { - modifyreg32(RTC_CNTL_RTC_CLK_CONF_REG, 0, RTC_CNTL_ENB_CK8M); - REG_SET_FIELD(RTC_CNTL_RTC_TIMER1_REG, RTC_CNTL_CK8M_WAIT, - RTC_CNTL_CK8M_WAIT_DEFAULT); - } -} - -/**************************************************************************** - * Name: esp32s3_select_rtc_slow_clk - * - * Description: - * Selects an clock source for RTC. - * - * Input Parameters: - * slow_clk - RTC SLOW_CLK frequency values - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void esp32s3_select_rtc_slow_clk(enum esp32s3_slow_clk_sel_e slow_clk) -{ - /* Number of times to repeat 32k XTAL calibration before giving up and - * switching to the internal RC. - */ - - int retry_32k_xtal = 0; - uint32_t cal_val = 0; - uint64_t cal_dividend; - enum esp32s3_rtc_slow_freq_e rtc_slow_freq = slow_clk & - RTC_CNTL_ANA_CLK_RTC_SEL_V; - - do - { - if (rtc_slow_freq == RTC_SLOW_FREQ_32K_XTAL) - { - /* 32k XTAL oscillator needs to be enabled and running before - * it can be used. Hardware doesn't have a direct way of checking - * if the oscillator is running. Here we use rtc_clk_cal function - * to count the number of main XTAL cycles in the given number of - * 32k XTAL oscillator cycles. If the 32k XTAL has not started up, - * calibration will time out, returning 0. - */ - - rtcinfo("Waiting for 32k oscillator to start up\n"); - if (slow_clk == SLOW_CLK_32K_XTAL || - slow_clk == SLOW_CLK_32K_EXT_OSC) - { - esp32s3_rtc_clk_32k_enable(true); - } - - if (SLOW_CLK_CAL_CYCLES > 0) - { - cal_val = esp32s3_rtc_clk_cal(RTC_CAL_32K_XTAL, - SLOW_CLK_CAL_CYCLES); - if (cal_val == 0 || cal_val < MIN_32K_XTAL_CAL_VAL) - { - if (retry_32k_xtal-- > 0) - { - continue; - } - - rtc_slow_freq = RTC_SLOW_FREQ_RTC; - } - } - } - else if (rtc_slow_freq == RTC_SLOW_FREQ_8MD256) - { - esp32s3_rtc_clk_8m_enable(true, true); - } - - esp32s3_rtc_clk_slow_freq_set(rtc_slow_freq); - if (SLOW_CLK_CAL_CYCLES > 0) - { - /* 32k XTAL oscillator has some frequency drift at startup. Improve - * calibration routine to wait until the frequency is stable. - */ - - cal_val = esp32s3_rtc_clk_cal(RTC_CAL_RTC_MUX, - SLOW_CLK_CAL_CYCLES); - } - else - { - cal_dividend = (1ULL << RTC_CLK_CAL_FRACT) * 1000000ULL; - cal_val = (uint32_t)(cal_dividend / - esp32s3_rtc_clk_slow_freq_get_hz()); - } - - retry_32k_xtal++; - } - while (cal_val == 0 && retry_32k_xtal < RETRY_CAL_EXT); - rtcinfo("RTC_SLOW_CLK calibration value: %" PRIu32 "\n", cal_val); - putreg32((uint32_t)cal_val, RTC_SLOW_CLK_CAL_REG); -} - -/**************************************************************************** - * Name: esp32s3_rtc_clk_cpu_freq_to_8m - * - * Description: - * Switch CPU frequency to 8 Mhz. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void IRAM_ATTR esp32s3_rtc_clk_cpu_freq_to_8m(void) -{ - ets_update_cpu_frequency(20); - REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT, 0); - REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL, 2); - esp32s3_rtc_clk_apb_freq_update(RTC_FAST_CLK_FREQ_APPROX); - REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, - g_rtc_dbias_pvt_non_240m); - REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, - g_dig_dbias_pvt_non_240m); - REG_SET_FIELD(RTC_CNTL_DATE_REG, RTC_CNTL_SLAVE_PD, - DEFAULT_LDO_SLAVE); -} - -/**************************************************************************** - * Name: esp32s3_rtc_clk_cpu_freq_to_pll_mhz - * - * Description: - * Switch to one of PLL-based frequencies. - * - * Input Parameters: - * cpu_freq_mhz - CPU frequency - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void IRAM_ATTR esp32s3_rtc_clk_cpu_freq_to_pll_mhz( - int cpu_freq_mhz) -{ - /* There are totally 6 LDO slaves(all on by default). At the moment of - * switching LDO slave, LDO voltage will also change instantaneously. - * LDO slave can reduce the voltage change caused by switching frequency. - * CPU frequency <= 40M : just open 3 LDO slaves; CPU frequency = 80M : - * open 4 LDO slaves; CPU frequency = 160M : open 5 LDO slaves; - * CPU frequency = 240M : open 6 LDO slaves; LDO voltage will decrease - * at the moment of switching from low frequency to high frequency; - * otherwise, LDO voltage will increase.In order to reduce LDO voltage - * drop, LDO voltage should rise first then fall. - */ - - int pd_slave = cpu_freq_mhz / 80; - struct esp32s3_cpu_freq_config_s cur_config = - { - 0 - }; - - esp32s3_rtc_clk_cpu_freq_get_config(&cur_config); - - /* cpu_frequency < 240M: dbias = pvt-dig + 2; - * cpu_frequency = 240M: dbias = pvt-dig + 3; - */ - - if (cpu_freq_mhz > cur_config.freq_mhz) - { - if (cpu_freq_mhz == 240) - { - REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, - g_rtc_dbias_pvt_240m); - REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, - g_dig_dbias_pvt_240m); - esp_rom_delay_us(40); - } - - REG_SET_FIELD(RTC_CNTL_DATE_REG, RTC_CNTL_SLAVE_PD, - DEFAULT_LDO_SLAVE >> pd_slave); - } - - switch (cpu_freq_mhz) - { - case CLK_LL_PLL_80M_FREQ_MHZ: - REG_SET_FIELD(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPUPERIOD_SEL, 0); - break; - - case CLK_LL_PLL_160M_FREQ_MHZ: - REG_SET_FIELD(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPUPERIOD_SEL, 1); - break; - - case CLK_LL_PLL_240M_FREQ_MHZ: - REG_SET_FIELD(SYSTEM_CPU_PER_CONF_REG, SYSTEM_CPUPERIOD_SEL, 2); - break; - - default: - DEBUGASSERT(0); - } - - REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_PRE_DIV_CNT, 0); - - /* switch clock source */ - - REG_SET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL, - DPORT_SOC_CLK_SEL_PLL); - esp32s3_rtc_clk_apb_freq_update(80 * MHZ); - ets_update_cpu_frequency(cpu_freq_mhz); - - if (cpu_freq_mhz < cur_config.freq_mhz) - { - if (cur_config.freq_mhz == 240) - { - REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, - g_rtc_dbias_pvt_non_240m); - REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, - g_dig_dbias_pvt_non_240m); - esp_rom_delay_us(40); - } - - REG_SET_FIELD(RTC_CNTL_DATE_REG, RTC_CNTL_SLAVE_PD, - DEFAULT_LDO_SLAVE >> pd_slave); - } -} - -#ifdef CONFIG_RTC_ALARM - -/**************************************************************************** - * Name: esp32s3_rt_cb_handler - * - * Description: - * RT-Timer service routine - * - * Input Parameters: - * arg - Information about the RT-Timer configuration. - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void IRAM_ATTR esp32s3_rt_cb_handler(void *arg) -{ - struct alm_cbinfo_s *cbinfo = (struct alm_cbinfo_s *)arg; - alm_callback_t cb; - void *cb_arg; - int alminfo_id; - - DEBUGASSERT(cbinfo != NULL); - alminfo_id = cbinfo->index; - DEBUGASSERT((RTC_ALARM0 <= alminfo_id) && - (alminfo_id < RTC_ALARM_LAST)); - - if (cbinfo->ac_cb != NULL) - { - /* Alarm callback */ - - cb = cbinfo->ac_cb; - cb_arg = (void *)cbinfo->ac_arg; - cbinfo->ac_cb = NULL; - cbinfo->ac_arg = NULL; - cbinfo->deadline_us = 0; - cb(cb_arg, alminfo_id); - } -} - -#endif /* CONFIG_RTC_ALARM */ - -/**************************************************************************** - * Name: esp32s3_rtc_calibrate_ocode - * - * Description: - * Calibrate o-code by software - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void esp32s3_rtc_calibrate_ocode(void) -{ - uint64_t cycle0; - uint64_t timeout_cycle; - uint32_t slow_clk_period; - uint64_t max_delay_cycle; - bool odone_flag = 0; - bool bg_odone_flag = 0; - uint64_t cycle1 = 0; - uint64_t max_delay_time_us = 10000; - struct esp32s3_cpu_freq_config_s freq_config = - { - 0 - }; - - /* Bandgap output voltage is not precise when calibrate o-code by hardware - * sometimes, so need software o-code calibration (must turn off PLL). - * Method: - * 1. read current cpu config, save in old_config - * 2. switch cpu to xtal because PLL will be closed when o-code calibration - * 3. begin o-code calibration - * 4. wait o-code calibration done flag or timeout - * 5. set cpu to old-config - */ - - enum esp32s3_rtc_slow_freq_e slow_clk_freq = - esp32s3_rtc_clk_slow_freq_get(); - enum esp32s3_rtc_slow_freq_e rtc_slow_freq_x32k = - RTC_SLOW_FREQ_32K_XTAL; - enum esp32s3_rtc_slow_freq_e rtc_slow_freq_8md256 = - RTC_SLOW_FREQ_8MD256; - enum esp32s3_rtc_cal_sel_e cal_clk = RTC_CAL_RTC_MUX; - if (slow_clk_freq == rtc_slow_freq_x32k) - { - cal_clk = RTC_CAL_32K_XTAL; - } - else if (slow_clk_freq == rtc_slow_freq_8md256) - { - cal_clk = RTC_CAL_8MD256; - } - - slow_clk_period = esp32s3_rtc_clk_cal(cal_clk, 100); - max_delay_cycle = esp32s3_rtc_time_us_to_slowclk(max_delay_time_us, - slow_clk_period); - cycle0 = esp32s3_rtc_time_get(); - timeout_cycle = cycle0 + max_delay_cycle; - - esp32s3_rtc_clk_cpu_freq_get_config(&freq_config); - esp32s3_rtc_cpu_freq_set_xtal(); - REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_RESETB, 0); - REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_RESETB, 1); - while (1) - { - odone_flag = REGI2C_READ_MASK(I2C_ULP, I2C_ULP_O_DONE_FLAG); - bg_odone_flag = REGI2C_READ_MASK(I2C_ULP, I2C_ULP_BG_O_DONE_FLAG); - cycle1 = esp32s3_rtc_time_get(); - if (odone_flag && bg_odone_flag) - { - break; - } - - if (cycle1 >= timeout_cycle) - { - break; - } - } - - esp32s3_rtc_clk_cpu_freq_set_config(&freq_config); -} - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32s3_rtc_clk_slow_freq_get - * - * Description: - * This function gets the frequency of the slow clock from the RTC. - * - * Input Parameters: - * None - * - * Returned Value: - * The frequency of the slow clock from the RTC. - * - ****************************************************************************/ - -int IRAM_ATTR esp32s3_rtc_clk_slow_freq_get(void) -{ - return REG_GET_FIELD(RTC_CNTL_RTC_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL); -} - -/**************************************************************************** - * Name: esp32s3_rtc_clk_slow_freq_get_hz - * - * Description: - * Get the approximate frequency of RTC_SLOW_CLK, in Hz - * - * Input Parameters: - * None - * - * Returned Value: - * slow_clk_freq - RTC_SLOW_CLK frequency, in Hz - * - ****************************************************************************/ - -uint32_t IRAM_ATTR esp32s3_rtc_clk_slow_freq_get_hz(void) -{ - enum esp32s3_rtc_slow_freq_e slow_clk_freq = - REG_GET_FIELD(RTC_CNTL_RTC_CLK_CONF_REG, - RTC_CNTL_ANA_CLK_RTC_SEL); - switch (slow_clk_freq) - { - case RTC_SLOW_FREQ_RTC: - return RTC_SLOW_CLK_FREQ_APPROX; - - case RTC_SLOW_FREQ_32K_XTAL: - return RTC_SLOW_CLK_FREQ_APPROX; - - case RTC_SLOW_FREQ_8MD256: - return RCT_FAST_D256_FREQ_APPROX; - } - - return OK; -} - -/**************************************************************************** - * Name: esp32s3_rtc_clk_fast_freq_get_hz - * - * Description: - * Get fast_clk_rtc source in Hz. - * - * Input Parameters: - * None - * - * Returned Value: - * The clock source in Hz. - * - ****************************************************************************/ - -uint32_t IRAM_ATTR esp32s3_rtc_clk_fast_freq_get_hz(void) -{ - return RTC_FAST_CLK_FREQ_APPROX; -} - -/**************************************************************************** - * Name: esp32s3_rtc_get_slow_clk_rtc - * - * Description: - * Get slow_clk_rtc source. - * - * Input Parameters: - * None - * - * Returned Value: - * The clock source: - * - SLOW_CK - * - CK_XTAL_32K - * - CK8M_D256_OUT - * - ****************************************************************************/ - -enum esp32s3_rtc_slow_freq_e IRAM_ATTR esp32s3_rtc_get_slow_clk(void) -{ - enum esp32s3_rtc_slow_freq_e slow_freq; - - /* Get the clock source for slow_clk_rtc */ - - slow_freq = REG_GET_FIELD(RTC_CNTL_RTC_CLK_CONF_REG, - RTC_CNTL_ANA_CLK_RTC_SEL); - - return slow_freq; -} - -/**************************************************************************** - * Name: esp32s3_rtc_clk_cal - * - * Description: - * Measure RTC slow clock's period, based on main XTAL frequency - * - * Input Parameters: - * cal_clk - Clock to be measured - * slowclk_cycles - Number of slow clock cycles to average - * - * Returned Value: - * Average slow clock period in microseconds, Q13.19 fixed point format - * or 0 if calibration has timed out - * - ****************************************************************************/ - -uint32_t IRAM_ATTR esp32s3_rtc_clk_cal(enum esp32s3_rtc_cal_sel_e cal_clk, - uint32_t slowclk_cycles) -{ - enum esp32s3_rtc_xtal_freq_e xtal_freq; - uint64_t xtal_cycles; - uint64_t divider; - uint64_t period_64; - uint32_t period; - - xtal_freq = esp32s3_rtc_clk_xtal_freq_get(); - xtal_cycles = esp32s3_rtc_clk_cal_internal(cal_clk, slowclk_cycles); - divider = ((uint64_t)xtal_freq) * slowclk_cycles; - period_64 = ((xtal_cycles << RTC_CLK_CAL_FRACT) + divider / 2 - 1) - / divider; - period = (uint32_t)(period_64 & UINT32_MAX); - - return period; -} - -/**************************************************************************** - * Name: esp32s3_rtc_clk_xtal_freq_get - * - * Description: - * Get main XTAL frequency - * - * Input Parameters: - * None - * - * Returned Value: - * XTAL frequency (one of enum esp32s3_rtc_xtal_freq_e values) - * - ****************************************************************************/ - -enum esp32s3_rtc_xtal_freq_e IRAM_ATTR esp32s3_rtc_clk_xtal_freq_get(void) -{ - /* We may have already written XTAL value into RTC_XTAL_FREQ_REG */ - - uint32_t xtal_freq_reg = getreg32(RTC_XTAL_FREQ_REG); - - if (!esp32s3_clk_val_is_valid(xtal_freq_reg)) - { - return RTC_XTAL_FREQ_40M; - } - - return (xtal_freq_reg & ~RTC_DISABLE_ROM_LOG) & UINT16_MAX; -} - -/**************************************************************************** - * Name: esp32_rtc_bbpll_disable - * - * Description: - * Power down BBPLL circuit. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void IRAM_ATTR esp32s3_rtc_bbpll_disable(void) -{ - modifyreg32(RTC_CNTL_RTC_OPTIONS0_REG, 0, RTC_CNTL_BB_I2C_FORCE_PD | - RTC_CNTL_BBPLL_FORCE_PD | RTC_CNTL_BBPLL_I2C_FORCE_PD); -} - -/**************************************************************************** - * Name: esp32s3_rtc_bbpll_enable - * - * Description: - * Power up BBPLL circuit. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void IRAM_ATTR esp32s3_rtc_bbpll_enable(void) -{ - modifyreg32(RTC_CNTL_RTC_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PD | - RTC_CNTL_BBPLL_FORCE_PD | RTC_CNTL_BBPLL_I2C_FORCE_PD, 0); -} - -/**************************************************************************** - * Name: esp32s3_rtc_bbpll_configure - * - * Description: - * Configure main XTAL frequency values according to pll_freq. - * - * Input Parameters: - * xtal_freq - XTAL frequency values - * pll_freq - PLL frequency values - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void IRAM_ATTR esp32s3_rtc_bbpll_configure( - enum esp32s3_rtc_xtal_freq_e xtal_freq, int pll_freq) -{ - uint8_t div_ref = 0; - uint8_t div7_0 = 0; - uint8_t dr1 = 0; - uint8_t dr3 = 0; - uint8_t dchgp = 0; - uint8_t dcur = 0; - uint8_t dbias = 3; - uint8_t i2c_bbpll_lref = 0; - uint8_t i2c_bbpll_div_7_0 = 0; - uint8_t i2c_bbpll_dcur = 0; - - switch (pll_freq) - { - case RTC_PLL_FREQ_320M: - REG_SET_FIELD(SYSTEM_CPU_PER_CONF_REG, SYSTEM_PLL_FREQ_SEL, 0); - break; - - case RTC_PLL_FREQ_480M: - REG_SET_FIELD(SYSTEM_CPU_PER_CONF_REG, SYSTEM_PLL_FREQ_SEL, 1); - break; - - default: - DEBUGASSERT(0); - } - - modifyreg32(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_HIGH, 0); - modifyreg32(I2C_MST_ANA_CONF0_REG, 0, I2C_MST_BBPLL_STOP_FORCE_LOW); - - if (pll_freq == RTC_PLL_FREQ_480M) - { - /* Configure 480M PLL */ - - switch (xtal_freq) - { - case RTC_XTAL_FREQ_40M: - { - div_ref = 0; - div7_0 = 8; - dr1 = 0; - dr3 = 0; - dchgp = 5; - dcur = 3; - } - break; - - case RTC_XTAL_FREQ_32M: - { - div_ref = 1; - div7_0 = 26; - dr1 = 1; - dr3 = 1; - dchgp = 4; - dcur = 0; - } - break; - - default: - { - div_ref = 0; - div7_0 = 8; - dr1 = 0; - dr3 = 0; - dchgp = 5; - dcur = 3; - } - break; - } - - REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_MODE_HF, 0x6b); - } - else - { - /* Configure 320M PLL */ - - switch (xtal_freq) - { - case RTC_XTAL_FREQ_40M: - { - div_ref = 0; - div7_0 = 4; - dr1 = 0; - dr3 = 0; - dchgp = 5; - dcur = 3; - } - break; - - case RTC_XTAL_FREQ_32M: - { - div_ref = 1; - div7_0 = 6; - dr1 = 0; - dr3 = 0; - dchgp = 5; - dcur = 3; - } - break; - - default: - { - div_ref = 0; - div7_0 = 4; - dr1 = 0; - dr3 = 0; - dchgp = 5; - dcur = 3; - } - break; - } - - REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_MODE_HF, 0x69); - } - - i2c_bbpll_lref = (dchgp << I2C_BBPLL_OC_DCHGP_LSB) | (div_ref); - i2c_bbpll_div_7_0 = div7_0; - i2c_bbpll_dcur = (1 << I2C_BBPLL_OC_DLREF_SEL_LSB) | - (3 << I2C_BBPLL_OC_DHREF_SEL_LSB) | dcur; - - REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_REF_DIV, i2c_bbpll_lref); - REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_DIV_7_0, i2c_bbpll_div_7_0); - REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DR1, dr1); - REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_DR3, dr3); - REGI2C_WRITE(I2C_BBPLL, I2C_BBPLL_OC_DCUR, i2c_bbpll_dcur); - REGI2C_WRITE_MASK(I2C_BBPLL, I2C_BBPLL_OC_VCO_DBIAS, dbias); - - /* Wait calibration done */ - - while (!(getreg32(I2C_MST_ANA_CONF0_REG) & I2C_MST_BBPLL_CAL_DONE)); - - /* Delay 10us after calibration done to fix bbpll calibration may - * stop early. - */ - - esp_rom_delay_us(10); - - /* BBPLL calibration stop */ - - modifyreg32(I2C_MST_ANA_CONF0_REG, I2C_MST_BBPLL_STOP_FORCE_LOW, - I2C_MST_BBPLL_STOP_FORCE_HIGH); -} - -/**************************************************************************** - * Name: esp32s3_rtc_clk_set - * - * Description: - * Set RTC CLK frequency. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32s3_rtc_clk_set(void) -{ - enum esp32s3_rtc_fast_freq_e fast_freq = RTC_FAST_FREQ_8M; - enum esp32s3_slow_clk_sel_e slow_clk = SLOW_CLK_150K; - -#if defined(CONFIG_ESP32S3_RTC_CLK_EXT_XTAL) - slow_clk = SLOW_CLK_32K_XTAL; -#elif defined(CONFIG_ESP32S3_RTC_CLK_EXT_OSC) - slow_clk = SLOW_CLK_32K_EXT_OSC; -#elif defined(CONFIG_ESP32S3_RTC_CLK_INT_8MD256) - slow_clk = SLOW_CLK_8MD256; -#endif - - esp32s3_rtc_clk_fast_freq_set(fast_freq); - esp32s3_select_rtc_slow_clk(slow_clk); -} - -/**************************************************************************** - * Name: esp32s3_rtc_init - * - * Description: - * Initialize RTC clock and power control related functions. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void IRAM_ATTR esp32s3_rtc_init(void) -{ - struct esp32s3_rtc_priv_s cfg = RTC_CONFIG_DEFAULT(); - soc_reset_reason_t rst_reas = esp_rom_get_reset_reason(0); - - /* When power on, we need to set `cali_ocode` to 1, to do a OCode - * calibration, which will calibrate the rtc reference voltage to a - * tested value - */ - - if (rst_reas == RESET_REASON_CHIP_POWER_ON) - { - cfg.cali_ocode = 1; - } - - /* When run rtc_init, it maybe deep sleep reset. Since we power down modem - * in deep sleep, after wakeup from deep sleep, these fields are changed - * and not reset. We will access two BB regs(BBPD_CTRL and NRXPD_CTRL) in - * rtc_sleep_pu. If PD modem and no iso, CPU will stuck when access these - * two BB regs and finally triggle RTC WDT. So need to clear modem Force - * PD. No worry about the power consumption, Because modem Force PD will - * be set at the end of this function. - */ - - modifyreg32(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_ISO, 0); - modifyreg32(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PD, 0); - - REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_RTC_REG, 0); - REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_XPD_DIG_REG, 0); - - modifyreg32(RTC_CNTL_RTC_ANA_CONF_REG, RTC_CNTL_PVTMON_PU, 0); - - REG_SET_FIELD(RTC_CNTL_RTC_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, - cfg.pll_wait); - REG_SET_FIELD(RTC_CNTL_RTC_TIMER1_REG, RTC_CNTL_CK8M_WAIT, - cfg.ck8m_wait); - - /* Moved from rtc sleep to rtc init to save sleep function running time */ - - /* set shortest possible sleep time limit */ - - REG_SET_FIELD(RTC_CNTL_RTC_TIMER5_REG, RTC_CNTL_MIN_SLP_VAL, - RTC_CNTL_MIN_SLP_VAL_MIN); - - /* set wifi timer */ - - REG_SET_FIELD(RTC_CNTL_RTC_TIMER3_REG, RTC_CNTL_WIFI_POWERUP_TIMER, 1); - REG_SET_FIELD(RTC_CNTL_RTC_TIMER3_REG, RTC_CNTL_WIFI_WAIT_TIMER, 1); - - /* set bt timer */ - - REG_SET_FIELD(RTC_CNTL_RTC_TIMER3_REG, RTC_CNTL_BT_POWERUP_TIMER, 1); - REG_SET_FIELD(RTC_CNTL_RTC_TIMER3_REG, RTC_CNTL_BT_WAIT_TIMER, 1); - - REG_SET_FIELD(RTC_CNTL_RTC_TIMER6_REG, RTC_CNTL_CPU_TOP_POWERUP_TIMER, 1); - REG_SET_FIELD(RTC_CNTL_RTC_TIMER6_REG, RTC_CNTL_CPU_TOP_WAIT_TIMER, 1); - - /* Set rtc peri timer */ - - REG_SET_FIELD(RTC_CNTL_RTC_TIMER4_REG, RTC_CNTL_RTC_POWERUP_TIMER, 1); - REG_SET_FIELD(RTC_CNTL_RTC_TIMER4_REG, RTC_CNTL_RTC_WAIT_TIMER, 1); - - /* Set digital wrap timer */ - - REG_SET_FIELD(RTC_CNTL_RTC_TIMER4_REG, RTC_CNTL_DG_WRAP_POWERUP_TIMER, 1); - REG_SET_FIELD(RTC_CNTL_RTC_TIMER4_REG, RTC_CNTL_DG_WRAP_WAIT_TIMER, 1); - REG_SET_FIELD(RTC_CNTL_RTC_TIMER6_REG, RTC_CNTL_DG_PERI_POWERUP_TIMER, 1); - REG_SET_FIELD(RTC_CNTL_RTC_TIMER6_REG, RTC_CNTL_DG_PERI_WAIT_TIMER, 1); - - /* Reset RTC bias to default value (needed if waking up from deep sleep) */ - - REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG_SLEEP, - RTC_CNTL_DBIAS_1V10); - REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, - RTC_CNTL_DBIAS_1V10); - - /* Set the wait time to the default value. */ - - REG_SET_FIELD(RTC_CNTL_RTC_TIMER2_REG, RTC_CNTL_ULPCP_TOUCH_START_WAIT, - RTC_CNTL_ULPCP_TOUCH_START_WAIT_DEFAULT); - if (cfg.cali_ocode) - { - /* TODO: Use calibration from efuse if configured */ - - esp32s3_rtc_calibrate_ocode(); - } - - REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG, - g_rtc_dbias_pvt_non_240m); - REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG, - g_dig_dbias_pvt_non_240m); - if (cfg.clkctl_init) - { - /* clear CMMU clock force on */ - - modifyreg32(EXTMEM_CACHE_MMU_POWER_CTRL_REG, - EXTMEM_CACHE_MMU_MEM_FORCE_ON, 0); - - /* clear clkgate force on */ - - putreg32(0, SYSCON_CLKGATE_FORCE_ON_REG); - - /* clear tag clock force on */ - - modifyreg32(EXTMEM_DCACHE_TAG_POWER_CTRL_REG, - EXTMEM_DCACHE_TAG_MEM_FORCE_ON, 0); - modifyreg32(EXTMEM_ICACHE_TAG_POWER_CTRL_REG, - EXTMEM_ICACHE_TAG_MEM_FORCE_ON, 0); - - /* clear register clock force on */ - - modifyreg32(SPI_MEM_CLOCK_GATE_REG(0), SPI_MEM_CLK_EN, 0); - modifyreg32(SPI_MEM_CLOCK_GATE_REG(1), SPI_MEM_CLK_EN, 0); - } - - if (cfg.pwrctl_init) - { - modifyreg32(RTC_CNTL_RTC_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU, 0); - - /* Cancel xtal force pu if no need to force power up - * Cannot cancel xtal force pu if pll is force power on - */ - - if (!(cfg.xtal_fpu || cfg.bbpll_fpu)) - { - modifyreg32(RTC_CNTL_RTC_OPTIONS0_REG, RTC_CNTL_XTL_FORCE_PU, 0); - } - else - { - modifyreg32(RTC_CNTL_RTC_OPTIONS0_REG, 0, RTC_CNTL_XTL_FORCE_PU); - } - - /* Open sar_i2c protect function to avoid sar_i2c reset when rtc_ldo - * is low - */ - - modifyreg32(RTC_CNTL_RTC_ANA_CONF_REG, - RTC_CNTL_I2C_RESET_POR_FORCE_PD, 0); - - /* Cancel bbpll force pu if setting no force power up */ - - if (!cfg.bbpll_fpu) - { - modifyreg32(RTC_CNTL_RTC_OPTIONS0_REG, - RTC_CNTL_BBPLL_FORCE_PU | - RTC_CNTL_BBPLL_I2C_FORCE_PU | - RTC_CNTL_BB_I2C_FORCE_PU, 0); - } - else - { - modifyreg32(RTC_CNTL_RTC_OPTIONS0_REG, 0, - RTC_CNTL_BBPLL_FORCE_PU | - RTC_CNTL_BBPLL_I2C_FORCE_PU | - RTC_CNTL_BB_I2C_FORCE_PU); - } - - /* Cancel RTC REG force PU */ - - modifyreg32(RTC_CNTL_RTC_PWC_REG, RTC_CNTL_RTC_FORCE_PU, 0); - modifyreg32(RTC_CNTL_RTC_REG, RTC_CNTL_RTC_REGULATOR_FORCE_PU | - RTC_CNTL_RTC_DBOOST_FORCE_PU, 0); - - modifyreg32(RTC_CNTL_RTC_PWC_REG, RTC_CNTL_RTC_SLOWMEM_FORCE_NOISO | - RTC_CNTL_RTC_FASTMEM_FORCE_NOISO, 0); - - if (cfg.rtc_dboost_fpd) - { - modifyreg32(RTC_CNTL_RTC_REG, 0, RTC_CNTL_RTC_DBOOST_FORCE_PD); - } - else - { - modifyreg32(RTC_CNTL_RTC_REG, RTC_CNTL_RTC_DBOOST_FORCE_PD, 0); - } - - /* Clear i2c_reset_protect pd force */ - - modifyreg32(RTC_CNTL_RTC_ANA_CONF_REG, - RTC_CNTL_I2C_RESET_POR_FORCE_PD, 0); - - /* If this mask is enabled, all soc mem cannot enter power down mode - * We should control soc memory power down mode from RTC, so we will - * not touch this register any more - */ - - modifyreg32(SYSTEM_MEM_PD_MASK_REG, SYSTEM_LSLP_MEM_PD_MASK, 0); - - /* If this pd_cfg is set to 1, all memory won't enter low power mode - * during light sleep. - * If this pd_cfg is set to 0, all memory will enter low power mode - * during light sleep. - */ - - struct esp32s3_rtc_sleep_pu_config_s - pu_cfg = RTC_SLEEP_PU_CONFIG_ALL(0); - esp32s3_rtc_sleep_pu(pu_cfg); - - modifyreg32(RTC_CNTL_RTC_PWC_REG, RTC_CNTL_DG_WRAP_FORCE_PU, 0); - modifyreg32(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_WRAP_FORCE_NOISO | - RTC_CNTL_DG_WRAP_FORCE_ISO, 0); - - modifyreg32(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_NOISO | - RTC_CNTL_WIFI_FORCE_ISO, 0); - modifyreg32(RTC_CNTL_RTC_PWC_REG, RTC_CNTL_WIFI_FORCE_PU, 0); - - modifyreg32(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_BT_FORCE_NOISO | - RTC_CNTL_BT_FORCE_ISO, 0); - modifyreg32(RTC_CNTL_RTC_PWC_REG, RTC_CNTL_BT_FORCE_PU, 0); - - modifyreg32(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_CPU_TOP_FORCE_NOISO | - RTC_CNTL_CPU_TOP_FORCE_ISO, 0); - modifyreg32(RTC_CNTL_RTC_PWC_REG, RTC_CNTL_CPU_TOP_FORCE_PU, 0); - - modifyreg32(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PERI_FORCE_NOISO | - RTC_CNTL_DG_PERI_FORCE_ISO, 0); - modifyreg32(RTC_CNTL_RTC_PWC_REG, RTC_CNTL_DG_PERI_FORCE_PU, 0); - - modifyreg32(RTC_CNTL_RTC_PWC_REG, RTC_CNTL_RTC_FORCE_NOISO | - RTC_CNTL_RTC_FORCE_ISO | - RTC_CNTL_RTC_FORCE_PU, 0); - - /* cancel digital PADS force no iso */ - - if (cfg.cpu_waiti_clk_gate) - { - modifyreg32(SYSTEM_CPU_PER_CONF_REG, - SYSTEM_CPU_WAIT_MODE_FORCE_ON, 0); - } - else - { - modifyreg32(SYSTEM_CPU_PER_CONF_REG, 0, - SYSTEM_CPU_WAIT_MODE_FORCE_ON); - } - - /* If SYSTEM_CPU_WAIT_MODE_FORCE_ON == 0, the cpu clk will be closed - * when cpu enter WAITI mode - */ - - modifyreg32(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD | - RTC_CNTL_DG_PAD_FORCE_NOISO, 0); - } - - /* force power down wifi and bt power domain */ - - modifyreg32(RTC_CNTL_DIG_ISO_REG, 0, RTC_CNTL_WIFI_FORCE_ISO); - modifyreg32(RTC_CNTL_DIG_PWC_REG, 0, RTC_CNTL_WIFI_FORCE_PD); - putreg32(0, RTC_CNTL_INT_ENA_RTC_REG); - putreg32(UINT32_MAX, RTC_CNTL_INT_CLR_RTC_REG); -} - -/**************************************************************************** - * Name: esp32s3_rtc_time_get - * - * Description: - * Get current value of RTC counter. - * - * Input Parameters: - * None - * - * Returned Value: - * current value of RTC counter - * - ****************************************************************************/ - -uint64_t IRAM_ATTR esp32s3_rtc_time_get(void) -{ - uint64_t rtc_time; - - modifyreg32(RTC_CNTL_RTC_TIME_UPDATE_REG, 0, RTC_CNTL_RTC_TIME_UPDATE); - - rtc_time = getreg32(RTC_CNTL_TIME0_REG); - rtc_time |= ((uint64_t) getreg32(RTC_CNTL_TIME1_REG)) << 32; - - return rtc_time; -} - -/**************************************************************************** - * Name: esp32s3_rtc_time_us_to_slowclk - * - * Description: - * Convert time interval from microseconds to RTC_SLOW_CLK cycles. - * - * Input Parameters: - * time_in_us - Time interval in microseconds - * slow_clk_period - Period of slow clock in microseconds - * - * Returned Value: - * Number of slow clock cycles - * - ****************************************************************************/ - -uint64_t IRAM_ATTR esp32s3_rtc_time_us_to_slowclk(uint64_t time_in_us, - uint32_t period) -{ - uint64_t slow_clk_cycles = 0; - uint64_t max_time_in_us = (UINT64_C(1) << 45) - 1; - - /* Handle overflow that would happen if time_in_us >= 2^45 */ - - while (time_in_us > max_time_in_us) - { - time_in_us -= max_time_in_us; - slow_clk_cycles += ((max_time_in_us << RTC_CLK_CAL_FRACT) / period); - } - - slow_clk_cycles += ((time_in_us << RTC_CLK_CAL_FRACT) / period); - - return slow_clk_cycles; -} - -/**************************************************************************** - * Name: esp32s3_rtc_time_slowclk_to_us - * - * Description: - * Convert time interval from RTC_SLOW_CLK to microseconds - * - * Input Parameters: - * rtc_cycles - Time interval in RTC_SLOW_CLK cycles - * period - Period of slow clock in microseconds - * - * Returned Value: - * Time interval in microseconds - * - ****************************************************************************/ - -uint64_t IRAM_ATTR esp32s3_rtc_time_slowclk_to_us(uint64_t rtc_cycles, - uint32_t period) -{ - return (rtc_cycles * period) >> RTC_CLK_CAL_FRACT; -} - -/**************************************************************************** - * Name: esp32s3_clk_slowclk_cal_get - * - * Description: - * Get the calibration value of RTC slow clock. - * - * Input Parameters: - * None - * - * Returned Value: - * the calibration value obtained using rtc_clk_cal - * - ****************************************************************************/ - -uint32_t IRAM_ATTR esp32s3_clk_slowclk_cal_get(void) -{ - return getreg32(RTC_SLOW_CLK_CAL_REG); -} - -/**************************************************************************** - * Name: esp32s3_rtc_sleep_set_wakeup_time - * - * Description: - * Set target value of RTC counter for RTC_TIMER_TRIG_EN wakeup source. - * - * Input Parameters: - * t - Value of RTC counter at which wakeup from sleep will happen. - * - * Returned Value: - * None - * - ****************************************************************************/ - -void IRAM_ATTR esp32s3_rtc_sleep_set_wakeup_time(uint64_t t) -{ - putreg32(t & UINT32_MAX, RTC_CNTL_RTC_SLP_TIMER0_REG); - putreg32((uint32_t)(t >> 32), RTC_CNTL_RTC_SLP_TIMER1_REG); - modifyreg32(RTC_CNTL_INT_CLR_RTC_REG, 0, - RTC_CNTL_RTC_MAIN_TIMER_INT_CLR_M); - modifyreg32(RTC_CNTL_RTC_SLP_TIMER1_REG, 0, - RTC_CNTL_RTC_MAIN_TIMER_ALARM_EN_M); -} - -/**************************************************************************** - * Name: esp32s3_rtc_wait_for_slow_cycle - * - * Description: - * Busy loop until next RTC_SLOW_CLK cycle. - * - * Input Parameters: - * None - * - * Returned Value: - * none - * - ****************************************************************************/ - -void IRAM_ATTR esp32s3_rtc_wait_for_slow_cycle(void) -{ - modifyreg32(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING | - TIMG_RTC_CALI_START, 0); - modifyreg32(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY, 0); - REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, - RTC_CAL_RTC_MUX); - - /* Request to run calibration for 0 slow clock cycles. - * RDY bit will be set on the nearest slow clock cycle. - */ - - REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, 0); - modifyreg32(TIMG_RTCCALICFG_REG(0), 0, TIMG_RTC_CALI_START); - - /* RDY needs some time to go low */ - - up_udelay(1); - - while (!(getreg32(TIMG_RTCCALICFG_REG(0)) & TIMG_RTC_CALI_RDY)) - { - up_udelay(1); - } -} - -void esp32s3_rtc_clk_apb_freq_update(uint32_t apb_freq) -{ - g_apb_freq = apb_freq; -} - -uint32_t esp32s3_rtc_clk_apb_freq_get(void) -{ - return g_apb_freq; -} - -/**************************************************************************** - * Name: esp32s3_rtc_cpu_freq_set_xtal - * - * Description: - * Switch CPU clock source to XTAL - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void IRAM_ATTR esp32s3_rtc_cpu_freq_set_xtal(void) -{ - int freq_mhz = (int)esp32s3_rtc_clk_xtal_freq_get(); - esp32s3_rtc_update_to_xtal(freq_mhz, 1); - esp32s3_rtc_bbpll_disable(); -} - -/**************************************************************************** - * Name: esp_rtc_clk_get_cpu_freq - * - * Description: - * Get the currently used CPU frequency configuration. - * - * Input Parameters: - * None - * - * Returned Value: - * CPU frequency - * - ****************************************************************************/ - -int IRAM_ATTR esp_rtc_clk_get_cpu_freq(void) -{ - uint32_t source_freq_mhz; - uint32_t div; - uint32_t soc_clk_sel; - uint32_t cpuperiod_sel; - int freq_mhz = 0; - - soc_clk_sel = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, SYSTEM_SOC_CLK_SEL); - switch (soc_clk_sel) - { - case DPORT_SOC_CLK_SEL_XTAL: - { - div = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, - SYSTEM_PRE_DIV_CNT) + 1; - source_freq_mhz = (uint32_t) esp32s3_rtc_clk_xtal_freq_get(); - freq_mhz = source_freq_mhz / div; - } - break; - - case DPORT_SOC_CLK_SEL_PLL: - { - cpuperiod_sel = REG_GET_FIELD(SYSTEM_CPU_PER_CONF_REG, - SYSTEM_CPUPERIOD_SEL); - uint32_t pllfreq_sel = REG_GET_FIELD(SYSTEM_CPU_PER_CONF_REG, - SYSTEM_PLL_FREQ_SEL); - source_freq_mhz = (pllfreq_sel) ? RTC_PLL_FREQ_480M : - RTC_PLL_FREQ_320M; - if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_80) - { - div = (source_freq_mhz == RTC_PLL_FREQ_480M) ? 6 : 4; - freq_mhz = 480 / div; - } - else if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_160) - { - div = 3; - freq_mhz = 480 / div; - } - else if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_240) - { - div = 2; - freq_mhz = 480 / div; - } - else - { - rtcerr("unsupported frequency configuration"); - return -ENODEV; - } - } - break; - - case DPORT_SOC_CLK_SEL_8M: - { - source_freq_mhz = 8; - div = 1; - freq_mhz = source_freq_mhz / div; - } - break; - - default: - { - rtcerr("unsupported frequency configuration"); - return -ENODEV; - } - } - - return freq_mhz; -} - -/**************************************************************************** - * Name: esp32s3_rtc_sleep_init - * - * Description: - * Prepare the chip to enter sleep mode - * - * Input Parameters: - * flags - sleep mode configuration - * - * Returned Value: - * None - * - ****************************************************************************/ - -void IRAM_ATTR esp32s3_rtc_sleep_init(uint32_t flags) -{ - struct esp32s3_rtc_sleep_config_s cfg = RTC_SLEEP_CONFIG_DEFAULT(flags); - if (flags & RTC_SLEEP_PD_DIG) - { - DEBUGASSERT(flags & RTC_SLEEP_PD_XTAL); - cfg.dig_dbias_slp = 0; - - /* RTC voltage from high to low */ - - if ((flags & RTC_SLEEP_USE_ADC_TESEN_MONITOR) || - (!(flags & RTC_SLEEP_PD_INT_8M))) - { - /* RTC voltage in sleep mode >= 0.9v if 8MD256 select as RTC - * slow clock src, only need dbg_atten_slp set to 0 - * Support all features: - * - 8MD256 as RTC slow clock src - * - ADC/Temperature sensor in monitor mode (ULP) - * (also need pd_cur_monitor = 0) - * - RTC IO as input - * - RTC Memory at high temperature - * - ULP - * - Touch sensor - */ - - cfg.rtc_regulator_fpu = 1; - cfg.dbg_atten_slp = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_NODROP; - } - else if (flags & RTC_SLEEP_NO_ULTRA_LOW) - { - /* RTC voltage in sleep mode >= 0.7v (default mode): - * Support follow features: - * - RTC IO as input - * - RTC Memory at high temperature - * - ULP - * - Touch sensor - */ - - cfg.rtc_regulator_fpu = 1; - cfg.dbg_atten_slp = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT; - } - else - { - /* RTC regulator not opened and rtc voltage is about 0.66v - * (ultra low power). - * Support follow features: - * - ULP - * - Touch sensor - */ - - cfg.rtc_regulator_fpu = 0; - cfg.dbg_atten_slp = RTC_CNTL_DBG_ATTEN_DEEPSLEEP_ULTRA_LOW; - } - } - else - { - cfg.rtc_regulator_fpu = 1; - - /* Voltage from high to low */ - - if ((flags & RTC_SLEEP_DIG_USE_8M) || !(flags & RTC_SLEEP_PD_XTAL)) - { - /* digital voltage not less than 1.1v, rtc voltage is about 1.1v - * Support all features: - * - XTAL - * - RC 8M used by digital system - * - 8MD256 as RTC slow clock src (only need dbg_atten_slp to 0) - * - ADC/Temperature sensor in monitor mode (ULP) - * (also need pd_cur_monitor = 0) - * - ULP - * - Touch sensor - */ - - cfg.dbg_atten_slp = RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP; - cfg.dig_dbias_slp = RTC_CNTL_DBIAS_1V10; - } - else if (!(flags & RTC_SLEEP_PD_INT_8M)) - { - /* dbg_atten_slp need to set to 0. - * digital voltage is about 0.67v, rtc voltage is about 1.1v - * Support features: - * - 8MD256 as RTC slow clock src - * - ADC/Temperature sensor in monitor mode (ULP) - * (also need pd_cur_monitor = 0) - * - ULP - * - Touch sensor - */ - - cfg.dbg_atten_slp = RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_NODROP; - cfg.dig_dbias_slp = 0; - } - else - { - /* digital voltage not less than 0.6v, rtc voltage is about 0.95v - * Support features: - * - ADC/Temperature sensor in monitor mode (ULP) - * (also need pd_cur_monitor = 0) - * - ULP - * - Touch sensor - */ - - cfg.dbg_atten_slp = RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT; - cfg.dig_dbias_slp = RTC_CNTL_DBIAS_SLP; - } - } - - if (!(flags & RTC_SLEEP_PD_XTAL)) - { - cfg.bias_sleep_monitor = RTC_CNTL_BIASSLP_MONITOR_ON; - cfg.pd_cur_monitor = RTC_CNTL_PD_CUR_MONITOR_ON; - cfg.bias_sleep_slp = RTC_CNTL_BIASSLP_SLEEP_ON; - cfg.pd_cur_slp = RTC_CNTL_PD_CUR_SLEEP_ON; - } - else - { - cfg.bias_sleep_monitor = RTC_CNTL_BIASSLP_MONITOR_DEFAULT; - cfg.pd_cur_monitor = (flags & RTC_SLEEP_USE_ADC_TESEN_MONITOR) ? - RTC_CNTL_PD_CUR_MONITOR_ON : - RTC_CNTL_PD_CUR_MONITOR_DEFAULT; - - cfg.bias_sleep_slp = RTC_CNTL_BIASSLP_SLEEP_DEFAULT; - cfg.pd_cur_slp = RTC_CNTL_PD_CUR_SLEEP_DEFAULT; - } - - /* Starts here */ - - if (cfg.lslp_mem_inf_fpu) - { - struct esp32s3_rtc_sleep_pu_config_s - pu_cfg = RTC_SLEEP_PU_CONFIG_ALL(1); - esp32s3_rtc_sleep_pu(pu_cfg); - } - - if (cfg.wifi_pd_en) - { - modifyreg32(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_NOISO | - RTC_CNTL_WIFI_FORCE_ISO, 0); - modifyreg32(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PU, 0); - modifyreg32(RTC_CNTL_DIG_PWC_REG, 0, RTC_CNTL_WIFI_PD_EN); - } - else - { - modifyreg32(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN, 0); - } - - if (cfg.bt_pd_en) - { - modifyreg32(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_BT_FORCE_NOISO | - RTC_CNTL_BT_FORCE_ISO, 0); - modifyreg32(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_FORCE_PU, 0); - modifyreg32(RTC_CNTL_DIG_PWC_REG, 0, RTC_CNTL_BT_PD_EN); - } - else - { - modifyreg32(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_PD_EN, 0); - } - - if (cfg.cpu_pd_en) - { - modifyreg32(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_CPU_TOP_FORCE_NOISO | - RTC_CNTL_CPU_TOP_FORCE_ISO, 0); - modifyreg32(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_CPU_TOP_FORCE_PU, - RTC_CNTL_CPU_TOP_PD_EN); - } - else - { - modifyreg32(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_CPU_TOP_PD_EN, 0); - } - - if (cfg.dig_peri_pd_en) - { - modifyreg32(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PERI_FORCE_NOISO | - RTC_CNTL_DG_PERI_FORCE_ISO, 0); - modifyreg32(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_PERI_FORCE_PU, - RTC_CNTL_DG_PERI_PD_EN); - } - else - { - modifyreg32(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_PERI_PD_EN, 0); - } - - if (cfg.rtc_peri_pd_en) - { - modifyreg32(RTC_CNTL_RTC_PWC_REG, RTC_CNTL_RTC_FORCE_NOISO | - RTC_CNTL_RTC_FORCE_ISO | RTC_CNTL_RTC_FORCE_PU, - RTC_CNTL_RTC_PD_EN); - } - else - { - modifyreg32(RTC_CNTL_RTC_PWC_REG, RTC_CNTL_RTC_PD_EN, 0); - } - - DEBUGASSERT(!cfg.pd_cur_monitor || cfg.bias_sleep_monitor); - DEBUGASSERT(!cfg.pd_cur_slp || cfg.bias_sleep_slp); - REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_RTC_DREG_SLEEP, - cfg.rtc_dbias_slp); - REGI2C_WRITE_MASK(I2C_DIG_REG, I2C_DIG_REG_EXT_DIG_DREG_SLEEP, - cfg.dig_dbias_slp); - - REG_SET_FIELD(RTC_CNTL_RTC_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_DEEP_SLP, - cfg.dbg_atten_slp); - REG_SET_FIELD(RTC_CNTL_RTC_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_DEEP_SLP, - cfg.bias_sleep_slp); - REG_SET_FIELD(RTC_CNTL_RTC_BIAS_CONF_REG, RTC_CNTL_PD_CUR_DEEP_SLP, - cfg.pd_cur_slp); - REG_SET_FIELD(RTC_CNTL_RTC_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_MONITOR, - RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT); - REG_SET_FIELD(RTC_CNTL_RTC_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_MONITOR, - cfg.bias_sleep_monitor); - REG_SET_FIELD(RTC_CNTL_RTC_BIAS_CONF_REG, RTC_CNTL_PD_CUR_MONITOR, - cfg.pd_cur_monitor); - - if (cfg.deep_slp) - { - modifyreg32(RTC_CNTL_DIG_PWC_REG, 0, RTC_CNTL_DG_WRAP_PD_EN); - modifyreg32(RTC_CNTL_RTC_ANA_CONF_REG, RTC_CNTL_CKGEN_I2C_PU | - RTC_CNTL_PLL_I2C_PU | RTC_CNTL_RFRX_PBUS_PU | - RTC_CNTL_TXRF_I2C_PU, 0); - } - else - { - REG_SET_FIELD(RTC_CNTL_RTC_REGULATOR_DRV_CTRL_REG, - RTC_CNTL_DG_VDD_DRV_B_SLP, - RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT); - modifyreg32(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN, 0); - } - - /* Mem force pu */ - - modifyreg32(RTC_CNTL_DIG_PWC_REG, 0, RTC_CNTL_LSLP_MEM_FORCE_PU); - modifyreg32(RTC_CNTL_RTC_PWC_REG, 0, RTC_CNTL_RTC_FASTMEM_FORCE_LPU | - RTC_CNTL_RTC_SLOWMEM_FORCE_LPU); - REG_SET_FIELD(RTC_CNTL_RTC_REG, RTC_CNTL_RTC_REGULATOR_FORCE_PU, - cfg.rtc_regulator_fpu); - if (!cfg.int_8m_pd_en) - { - REG_SET_BIT(RTC_CNTL_RTC_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU); - } - else - { - REG_CLR_BIT(RTC_CNTL_RTC_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU); - } - - /* Enable VDDSDIO control by state machine */ - - REG_CLR_BIT(RTC_CNTL_RTC_SDIO_CONF_REG, RTC_CNTL_SDIO_FORCE); - REG_SET_FIELD(RTC_CNTL_RTC_SDIO_CONF_REG, RTC_CNTL_SDIO_REG_PD_EN, - cfg.vddsdio_pd_en); - REG_SET_FIELD(RTC_CNTL_RTC_SLP_REJECT_CONF_REG, - RTC_CNTL_DEEP_SLP_REJECT_EN, cfg.deep_slp_reject); - REG_SET_FIELD(RTC_CNTL_RTC_SLP_REJECT_CONF_REG, - RTC_CNTL_LIGHT_SLP_REJECT_EN, cfg.light_slp_reject); - - /* Set wait cycle for touch or COCPU after deep sleep and light sleep. */ - - REG_SET_FIELD(RTC_CNTL_RTC_TIMER2_REG, - RTC_CNTL_ULPCP_TOUCH_START_WAIT, - RTC_CNTL_ULPCP_TOUCH_START_WAIT_IN_SLEEP); - - REG_SET_FIELD(RTC_CNTL_RTC_OPTIONS0_REG, - RTC_CNTL_XTL_FORCE_PU, cfg.xtal_fpu); - REG_SET_FIELD(RTC_CNTL_RTC_CLK_CONF_REG, - RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING, cfg.xtal_fpu); -} - -/**************************************************************************** - * Name: esp32s3_rtc_sleep_start - * - * Description: - * Enter force sleep mode. - * - * Input Parameters: - * wakeup_opt - Bit mask wake up reasons to enable - * reject_opt - Bit mask of sleep reject reasons. - * - * Returned Value: - * non-zero if sleep was rejected by hardware - * - ****************************************************************************/ - -int IRAM_ATTR esp32s3_rtc_sleep_start(uint32_t wakeup_opt, - uint32_t reject_opt) -{ - int reject; - REG_SET_FIELD(RTC_CNTL_RTC_WAKEUP_STATE_REG, - RTC_CNTL_RTC_WAKEUP_ENA, wakeup_opt); - REG_SET_FIELD(RTC_CNTL_RTC_SLP_REJECT_CONF_REG, - RTC_CNTL_RTC_SLEEP_REJECT_ENA, reject_opt); - - modifyreg32(RTC_CNTL_INT_CLR_RTC_REG, 0, - RTC_CNTL_SLP_REJECT_INT_CLR | RTC_CNTL_SLP_WAKEUP_INT_CLR); - - /* Start entry into sleep mode */ - - modifyreg32(RTC_CNTL_RTC_STATE0_REG, 0, RTC_CNTL_SLEEP_EN); - - while ((getreg32(RTC_CNTL_INT_RAW_RTC_REG) & - (RTC_CNTL_SLP_REJECT_INT_RAW | RTC_CNTL_SLP_WAKEUP_INT_RAW)) == 0); - - /* In deep sleep mode, we never get here */ - - reject = REG_GET_FIELD(RTC_CNTL_INT_RAW_RTC_REG, - RTC_CNTL_SLP_REJECT_INT_RAW); - - modifyreg32(RTC_CNTL_INT_CLR_RTC_REG, 0, - RTC_CNTL_SLP_REJECT_INT_CLR | RTC_CNTL_SLP_WAKEUP_INT_CLR); - - /* Recover default wait cycle for touch or COCPU after wakeup. */ - - REG_SET_FIELD(RTC_CNTL_RTC_TIMER2_REG, RTC_CNTL_ULPCP_TOUCH_START_WAIT, - RTC_CNTL_ULPCP_TOUCH_START_WAIT_DEFAULT); - - return reject; -} - -void esp32s3_rtc_ext1_prepare(uint32_t trigger_mode, uint32_t rtc_gpio_mask) -{ - if (rtc_gpio_mask > 0) - { - modifyreg32(RTC_CNTL_RTC_EXT_WAKEUP1_REG, 0 , - RTC_CNTL_EXT_WAKEUP1_STATUS_CLR | rtc_gpio_mask); - modifyreg32(RTC_CNTL_RTC_EXT_WAKEUP_CONF_REG, 0, - (trigger_mode << RTC_CNTL_EXT_WAKEUP1_LV_S) | \ - RTC_CNTL_GPIO_WAKEUP_FILTER); - } -} - -/**************************************************************************** - * Name: esp32s3_rtc_clk_cpu_freq_set_config - * - * Description: - * Set CPU frequency configuration. - * - * Input Parameters: - * config - CPU frequency configuration - * - * Returned Value: - * None - * - ****************************************************************************/ - -void IRAM_ATTR esp32s3_rtc_clk_cpu_freq_set_config( - const struct esp32s3_cpu_freq_config_s *config) -{ - uint32_t soc_clk_sel = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, - SYSTEM_SOC_CLK_SEL); - if (config->source == RTC_CPU_FREQ_SRC_XTAL) - { - esp32s3_rtc_update_to_xtal(config->freq_mhz, config->div); - if (soc_clk_sel == DPORT_SOC_CLK_SEL_PLL) - { - esp32s3_rtc_bbpll_disable(); - } - } - else if (config->source == RTC_CPU_FREQ_SRC_PLL) - { - if (soc_clk_sel != DPORT_SOC_CLK_SEL_PLL) - { - esp32s3_rtc_bbpll_enable(); - modifyreg32(RTC_CNTL_RTC_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PD | - RTC_CNTL_BBPLL_FORCE_PD | RTC_CNTL_BBPLL_I2C_FORCE_PD, 0); - esp32s3_rtc_bbpll_configure(esp32s3_rtc_clk_xtal_freq_get(), - config->source_freq_mhz); - } - - esp32s3_rtc_clk_cpu_freq_to_pll_mhz(config->freq_mhz); - } - else if (config->source == RTC_CPU_FREQ_SRC_8M) - { - esp32s3_rtc_clk_cpu_freq_to_8m(); - if (soc_clk_sel == DPORT_SOC_CLK_SEL_PLL) - { - esp32s3_rtc_bbpll_disable(); - } - } -} - -/**************************************************************************** - * Name: esp32s3_rtc_clk_cpu_freq_get_config - * - * Description: - * Get the currently used CPU frequency configuration. - * - * Input Parameters: - * None - * - * Returned Value: - * CPU clock configuration structure - * - ****************************************************************************/ - -void IRAM_ATTR esp32s3_rtc_clk_cpu_freq_get_config( - struct esp32s3_cpu_freq_config_s *out_config) -{ - uint32_t div = 3; - uint32_t freq_mhz = 160; - uint32_t source_freq_mhz = RTC_PLL_FREQ_480M; - enum esp32s3_rtc_cpu_freq_src_e source = RTC_CPU_FREQ_SRC_PLL; - uint32_t soc_clk_sel = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, - SYSTEM_SOC_CLK_SEL); - switch (soc_clk_sel) - { - case DPORT_SOC_CLK_SEL_XTAL: - { - source = RTC_CPU_FREQ_SRC_XTAL; - div = REG_GET_FIELD(SYSTEM_SYSCLK_CONF_REG, - SYSTEM_PRE_DIV_CNT) + 1; - source_freq_mhz = (uint32_t) esp32s3_rtc_clk_xtal_freq_get(); - freq_mhz = source_freq_mhz / div; - } - break; - - case DPORT_SOC_CLK_SEL_PLL: - { - uint32_t cpuperiod_sel = REG_GET_FIELD(SYSTEM_CPU_PER_CONF_REG, - SYSTEM_CPUPERIOD_SEL); - uint32_t pllfreq_sel = REG_GET_FIELD(SYSTEM_CPU_PER_CONF_REG, - SYSTEM_PLL_FREQ_SEL); - source = RTC_CPU_FREQ_SRC_PLL; - source_freq_mhz = (pllfreq_sel) ? - RTC_PLL_FREQ_480M : RTC_PLL_FREQ_320M; - if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_80) - { - div = (source_freq_mhz == RTC_PLL_FREQ_480M) ? 6 : 4; - freq_mhz = 80; - } - else if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_160) - { - div = (source_freq_mhz == RTC_PLL_FREQ_480M) ? 3 : 2; - div = 3; - freq_mhz = 160; - } - else if (cpuperiod_sel == DPORT_CPUPERIOD_SEL_240) - { - div = 2; - freq_mhz = 240; - } - else - { - return; - } - } - break; - - case DPORT_SOC_CLK_SEL_8M: - { - source = RTC_CPU_FREQ_SRC_8M; - source_freq_mhz = 8; - div = 1; - freq_mhz = source_freq_mhz; - } - break; - - default: - PANIC(); - break; - } - - *out_config = (struct esp32s3_cpu_freq_config_s) - { - .source = source, - .source_freq_mhz = source_freq_mhz, - .div = div, - .freq_mhz = freq_mhz - }; -} - -/**************************************************************************** - * Name: esp32s3_rtc_get_time_us - * - * Description: - * Get current value of RTC counter in microseconds - * - * Input Parameters: - * None - * - * Returned Value: - * Current value of RTC counter in microseconds - * - ****************************************************************************/ - -uint64_t esp32s3_rtc_get_time_us(void) -{ - const uint32_t cal = getreg32(RTC_SLOW_CLK_CAL_REG); - const uint64_t rtc_this_ticks = esp32s3_rtc_time_get(); - - /* RTC counter result is up to 2^48, calibration factor is up to 2^24, - * for a 32kHz clock. We need to calculate (assuming no overflow): - * (ticks * cal) >> RTC_CLK_CAL_FRACT. An overflow in the (ticks * cal) - * multiplication would cause time to wrap around after approximately - * 13 days, which is probably not enough for some applications. - * Therefore multiplication is split into two terms, for the lower 32-bit - * and the upper 16-bit parts of "ticks", i.e.: - * ((ticks_low + 2^32 * ticks_high) * cal) >> RTC_CLK_CAL_FRACT - */ - - const uint64_t ticks_low = rtc_this_ticks & UINT32_MAX; - const uint64_t ticks_high = rtc_this_ticks >> 32; - const uint64_t delta_time_us = ((ticks_low * cal) >> RTC_CLK_CAL_FRACT) + - ((ticks_high * cal) << (32 - RTC_CLK_CAL_FRACT)); - - return delta_time_us; -} - -/**************************************************************************** - * Name: esp32c3_rtc_sleep_low_init - * - * Description: - * Low level initialize for rtc state machine waiting - * cycles after waking up. - * - * Input Parameters: - * slowclk_period - Re-calibrated slow clock period - * - * Returned Value: - * None - * - ****************************************************************************/ - -void IRAM_ATTR esp32s3_rtc_sleep_low_init(uint32_t slowclk_period) -{ - /* Set 5 PWC state machine times to fit in main state machine time */ - - REG_SET_FIELD(RTC_CNTL_RTC_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, - RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES); - REG_SET_FIELD(RTC_CNTL_RTC_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, - esp32s3_rtc_time_us_to_slowclk( - RTC_CNTL_XTL_BUF_WAIT_SLP_US, slowclk_period)); - REG_SET_FIELD(RTC_CNTL_RTC_TIMER1_REG, RTC_CNTL_CK8M_WAIT, - RTC_CNTL_CK8M_WAIT_SLP_CYCLES); -} - -/**************************************************************************** - * Name: esp32s3_rtc_set_boot_time - * - * Description: - * Set time to RTC register to replace the original boot time. - * - * Input Parameters: - * time_us - Set time in microseconds. - * - * Returned Value: - * None - * - ****************************************************************************/ - -void IRAM_ATTR esp32s3_rtc_set_boot_time(uint64_t time_us) -{ - putreg32((uint32_t)(time_us & UINT32_MAX), RTC_BOOT_TIME_LOW_REG); - putreg32((uint32_t)(time_us >> 32), RTC_BOOT_TIME_HIGH_REG); -} - -/**************************************************************************** - * Name: esp32s3_rtc_get_boot_time - * - * Description: - * Get time of RTC register to indicate the original boot time. - * - * Input Parameters: - * None - * - * Returned Value: - * time_us - Get time in microseconds. - * - ****************************************************************************/ - -uint64_t IRAM_ATTR esp32s3_rtc_get_boot_time(void) -{ - return ((uint64_t)getreg32(RTC_BOOT_TIME_LOW_REG)) - + (((uint64_t)getreg32(RTC_BOOT_TIME_HIGH_REG)) << 32); -} - -/**************************************************************************** - * Name: esp32s3_rtc_recalib_bbpll - * - * Description: - * Re-calibration BBPLL, workaround for bootloader not calibration well - * issue. - * - * Input Parameters: - * None - * - * Returned Value: - * None. - * - ****************************************************************************/ - -#ifdef CONFIG_ESP32S3_SYSTEM_BBPLL_RECALIB -void IRAM_ATTR esp32s3_rtc_recalib_bbpll(void) -{ - struct esp32s3_cpu_freq_config_s freq_config = - { - 0 - }; - - esp32s3_rtc_clk_cpu_freq_get_config(&freq_config); - - /* There are two paths we arrive here: 1.CPU reset. 2.Other reset reasons. - * - For other reasons, the bootloader will set CPU source to BBPLL and - * enable it. But there are calibration issues. Turn off the BBPLL and - * do calibration again to fix the issue. - * - For CPU reset, the CPU source will be set to XTAL, while the BBPLL - * is kept to meet USB Serial JTAG's requirements. In this case, we - * don't touch BBPLL to avoid USJ disconnection. - */ - - if (freq_config.source == RTC_CPU_FREQ_SRC_PLL) - { - esp32s3_rtc_cpu_freq_set_xtal(); - esp32s3_rtc_clk_cpu_freq_set_config(&freq_config); - } -} -#endif - -/**************************************************************************** - * Name: up_rtc_time - * - * Description: - * Get the current time in seconds. This is similar to the standard time() - * function. This interface is only required if the low-resolution - * RTC/counter hardware implementation is selected. It is only used by the - * RTOS during initialization to set up the system time when CONFIG_RTC is - * set but CONFIG_RTC_HIRES is not set. - * - * Input Parameters: - * None - * - * Returned Value: - * The current time in seconds - * - ****************************************************************************/ - -#ifndef CONFIG_RTC_HIRES -time_t up_rtc_time(void) -{ - uint64_t time_us; - irqstate_t flags; - - flags = spin_lock_irqsave(&g_rtc_lock); - - /* NOTE: RT-Timer starts to work after the board is initialized, and the - * RTC controller starts works after up_rtc_initialize is initialized. - * Since the system clock starts to work before the board is initialized, - * if CONFIG_RTC is enabled, the system time must be matched by the time - * of the RTC controller (up_rtc_initialize has already been initialized, - * and RT-Timer cannot work). - */ - - /* Determine if RT-Timer is started */ - - if (g_rt_timer_enabled == true) - { - /* Get the time from RT-Timer, the time interval between RTC - * controller and RT-Timer is stored in g_rtc_save->offset. - */ - - time_us = esp32s3_rt_timer_time_us() + g_rtc_save->offset + - esp32s3_rtc_get_boot_time(); - } - else - { - /* Get the time from RTC controller. */ - - time_us = esp32s3_rtc_get_time_us() + - esp32s3_rtc_get_boot_time(); - } - - spin_unlock_irqrestore(&g_rtc_lock, flags); - - return (time_t)(time_us / USEC_PER_SEC); -} -#endif /* !CONFIG_RTC_HIRES */ - -/**************************************************************************** - * Name: up_rtc_settime - * - * Description: - * Set the RTC to the provided time. All RTC implementations must be - * able to set their time based on a standard timespec. - * - * Input Parameters: - * ts - The time to use - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -int up_rtc_settime(const struct timespec *ts) -{ - irqstate_t flags; - uint64_t now_us; - uint64_t rtc_offset_us; - - DEBUGASSERT(ts != NULL && ts->tv_nsec < NSEC_PER_SEC); - flags = spin_lock_irqsave(&g_rtc_lock); - - now_us = ((uint64_t) ts->tv_sec) * USEC_PER_SEC + - ts->tv_nsec / NSEC_PER_USEC; - if (g_rt_timer_enabled == true) - { - /* Set based on RT-Timer offset value. */ - - rtc_offset_us = now_us - esp32s3_rt_timer_time_us(); - } - else - { - /* Set based on the offset value of the RT controller. */ - - rtc_offset_us = now_us - esp32s3_rtc_get_time_us(); - } - - g_rtc_save->offset = 0; - esp32s3_rtc_set_boot_time(rtc_offset_us); - - spin_unlock_irqrestore(&g_rtc_lock, flags); - - return OK; -} - -/**************************************************************************** - * Name: up_rtc_initialize - * - * Description: - * Initialize the hardware RTC per the selected configuration. - * This function is called once during the OS initialization sequence - * - * Input Parameters: - * None - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -int up_rtc_initialize(void) -{ - g_rtc_save = &rtc_saved_data; - - /* If saved data is invalid, clear offset information */ - - if (g_rtc_save->magic != MAGIC_RTC_SAVE) - { - g_rtc_save->magic = MAGIC_RTC_SAVE; - g_rtc_save->offset = 0; - esp32s3_rtc_set_boot_time(0); - } - -#ifdef CONFIG_RTC_HIRES - /* Synchronize the base time to the RTC time */ - - up_rtc_gettime(&g_basetime); -#endif - - g_rtc_enabled = true; - - return OK; -} - -/**************************************************************************** - * Name: up_rtc_gettime - * - * Description: - * Get the current time from the high resolution RTC time or RT-Timer. This - * interface is only supported by the high-resolution RTC/counter hardware - * implementation. It is used to replace the system timer. - * - * Input Parameters: - * tp - The location to return the RTC time or RT-Timer value. - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_HIRES -int up_rtc_gettime(struct timespec *tp) -{ - irqstate_t flags; - uint64_t time_us; - - flags = spin_lock_irqsave(&g_rtc_lock); - - if (g_rt_timer_enabled == true) - { - time_us = esp32s3_rt_timer_time_us() + g_rtc_save->offset + - esp32s3_rtc_get_boot_time(); - } - else - { - time_us = esp32s3_rtc_get_time_us() + esp32s3_rtc_get_boot_time(); - } - - tp->tv_sec = time_us / USEC_PER_SEC; - tp->tv_nsec = (time_us % USEC_PER_SEC) * NSEC_PER_USEC; - - spin_unlock_irqrestore(&g_rtc_lock, flags); - - return OK; -} -#endif /* CONFIG_RTC_HIRES */ - -#ifdef CONFIG_RTC_ALARM - -/**************************************************************************** - * Name: up_rtc_setalarm - * - * Description: - * Set up an alarm. - * - * Input Parameters: - * alminfo - Information about the alarm configuration. - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -int up_rtc_setalarm(struct alm_setalarm_s *alminfo) -{ - struct rt_timer_args_s rt_timer_args; - struct alm_cbinfo_s *cbinfo; - irqstate_t flags; - int ret = -EBUSY; - int id; - - DEBUGASSERT(alminfo != NULL); - DEBUGASSERT((RTC_ALARM0 <= alminfo->as_id) && - (alminfo->as_id < RTC_ALARM_LAST)); - - /* Set the alarm in RT-Timer */ - - id = alminfo->as_id; - cbinfo = &g_alarmcb[id]; - - if (cbinfo->ac_cb == NULL) - { - /* Create the RT-Timer alarm */ - - flags = spin_lock_irqsave(&g_rtc_lock); - - if (cbinfo->alarm_hdl == NULL) - { - cbinfo->index = id; - rt_timer_args.arg = cbinfo; - rt_timer_args.callback = esp32s3_rt_cb_handler; - ret = esp32s3_rt_timer_create(&rt_timer_args, &cbinfo->alarm_hdl); - if (ret < 0) - { - rtcerr("ERROR: Failed to create rt_timer error=%d\n", ret); - spin_unlock_irqrestore(&g_rtc_lock, flags); - return ret; - } - } - - cbinfo->ac_cb = alminfo->as_cb; - cbinfo->ac_arg = alminfo->as_arg; - cbinfo->deadline_us = alminfo->as_time.tv_sec * USEC_PER_SEC + - alminfo->as_time.tv_nsec / NSEC_PER_USEC; - - if (cbinfo->alarm_hdl == NULL) - { - rtcerr("ERROR: failed to create alarm timer\n"); - } - else - { - rtcinfo("Start RTC alarm.\n"); - esp32s3_rt_timer_start(cbinfo->alarm_hdl, - cbinfo->deadline_us, false); - ret = OK; - } - - spin_unlock_irqrestore(&g_rtc_lock, flags); - } - - return ret; -} - -/**************************************************************************** - * Name: up_rtc_cancelalarm - * - * Description: - * Cancel an alarm. - * - * Input Parameters: - * alarmid - Identifies the alarm to be cancelled - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -int up_rtc_cancelalarm(enum alm_id_e alarmid) -{ - struct alm_cbinfo_s *cbinfo; - irqstate_t flags; - int ret = -ENODATA; - - DEBUGASSERT((RTC_ALARM0 <= alarmid) && - (alarmid < RTC_ALARM_LAST)); - - /* Set the alarm in hardware and enable interrupts */ - - cbinfo = &g_alarmcb[alarmid]; - - if (cbinfo->ac_cb != NULL) - { - flags = spin_lock_irqsave(&g_rtc_lock); - - /* Stop and delete the alarm */ - - rtcinfo("Cancel RTC alarm.\n"); - esp32s3_rt_timer_stop(cbinfo->alarm_hdl); - esp32s3_rt_timer_delete(cbinfo->alarm_hdl); - cbinfo->ac_cb = NULL; - cbinfo->deadline_us = 0; - cbinfo->alarm_hdl = NULL; - - spin_unlock_irqrestore(&g_rtc_lock, flags); - - ret = OK; - } - - return ret; -} - -/**************************************************************************** - * Name: up_rtc_rdalarm - * - * Description: - * Query an alarm configured in hardware. - * - * Input Parameters: - * tp - Location to return the timer match register. - * alarmid - Identifies the alarm to get. - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -int up_rtc_rdalarm(struct timespec *tp, uint32_t alarmid) -{ - irqstate_t flags; - struct alm_cbinfo_s *cbinfo; - DEBUGASSERT(tp != NULL); - DEBUGASSERT((RTC_ALARM0 <= alarmid) && - (alarmid < RTC_ALARM_LAST)); - - flags = spin_lock_irqsave(&g_rtc_lock); - - /* Get the alarm according to the alarmid */ - - cbinfo = &g_alarmcb[alarmid]; - - tp->tv_sec = (esp32s3_rt_timer_time_us() + g_rtc_save->offset + - cbinfo->deadline_us) / USEC_PER_SEC; - tp->tv_nsec = ((esp32s3_rt_timer_time_us() + g_rtc_save->offset + - cbinfo->deadline_us) % USEC_PER_SEC) * NSEC_PER_USEC; - - spin_unlock_irqrestore(&g_rtc_lock, flags); - - return OK; -} - -#endif /* CONFIG_RTC_ALARM */ - -/**************************************************************************** - * Name: up_rtc_timer_init - * - * Description: - * Init RTC timer. - * - * Input Parameters: - * None - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -int up_rtc_timer_init(void) -{ - /* RT-Timer enabled */ - - g_rt_timer_enabled = true; - - /* Get the time difference between rt_timer and RTC timer */ - - g_rtc_save->offset = esp32s3_rtc_get_time_us() - - esp32s3_rt_timer_time_us(); - - return OK; -} diff --git a/arch/xtensa/src/esp32s3/esp32s3_rtc.h b/arch/xtensa/src/esp32s3/esp32s3_rtc.h deleted file mode 100644 index 32763e3538ba2..0000000000000 --- a/arch/xtensa/src/esp32s3/esp32s3_rtc.h +++ /dev/null @@ -1,807 +0,0 @@ -/**************************************************************************** - * arch/xtensa/src/esp32s3/esp32s3_rtc.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#ifndef __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_RTC_H -#define __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_RTC_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include -#include -#include -#include "hardware/esp32s3_soc.h" - -#ifndef __ASSEMBLY__ - -#undef EXTERN -#if defined(__cplusplus) -#define EXTERN extern "C" -extern "C" -{ -#else -#define EXTERN extern -#endif - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Number of cycles to wait from the 32k XTAL oscillator to - * consider it running. Larger values increase startup delay. - * Smaller values may cause false positive detection - * (i.e. oscillator runs for a few cycles and then stops). - */ - -#define SLOW_CLK_CAL_CYCLES 1024 - -/* Indicates that 32k oscillator gets input from external oscillator - * instead of a crystal. - */ - -#define EXT_OSC_FLAG BIT(3) - -/* Number of fractional bits in values returned by rtc_clk_cal */ - -#define RTC_CLK_CAL_FRACT 19 - -/* Cycles for RTC Timer clock source (internal oscillator) calibrate */ - -#define RTC_CLK_SRC_CAL_CYCLES (10) - -#define RTC_CNTL_XTL_BUF_WAIT_SLP_US (250) -#define RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES (1) -#define RTC_CNTL_CK8M_WAIT_SLP_CYCLES (4) -#define RTC_CNTL_WAKEUP_DELAY_CYCLES (4) - -#define RTC_CNTL_CK8M_DFREQ_DEFAULT 100 -#define RTC_CNTL_SCK_DCAP_DEFAULT 255 - -#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_IN_SLEEP (0xFF) -#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_DEFAULT (0x10) - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/* CPU clock source */ - -enum esp32s3_rtc_cpu_freq_src_e -{ - RTC_CPU_FREQ_SRC_XTAL, /* XTAL */ - RTC_CPU_FREQ_SRC_PLL, /* PLL (480M or 320M) */ - RTC_CPU_FREQ_SRC_8M, /* Internal 8M RTC oscillator */ -}; - -/* Possible main XTAL frequency values. - * Enum values should be equal to frequency in MHz. - */ - -enum esp32s3_rtc_xtal_freq_e -{ - RTC_XTAL_FREQ_32M = 32, /* 32 MHz XTAL */ - RTC_XTAL_FREQ_40M = 40, /* 40 MHz XTAL */ -}; - -/* RTC SLOW_CLK frequency values */ - -enum esp32s3_rtc_slow_freq_e -{ - RTC_SLOW_FREQ_RTC = 0, /* Internal 150 kHz RC oscillator */ - RTC_SLOW_FREQ_32K_XTAL = 1, /* External 32 kHz XTAL */ - RTC_SLOW_FREQ_8MD256 = 2, /* Internal 8 MHz RC oscillator, divided by 256 */ -}; - -/* RTC FAST_CLK frequency values */ - -enum esp32s3_rtc_fast_freq_e -{ - RTC_FAST_FREQ_XTALD4 = 0, /* Main XTAL, divided by 4 */ - RTC_FAST_FREQ_8M = 1, /* Internal 8 MHz RC oscillator */ -}; - -/* This is almost the same as esp32s3_rtc_slow_freq_e, except that we define - * an extra enum member for the external 32k oscillator. For convenience, - * lower 2 bits should correspond to esp32s3_rtc_slow_freq_e values. - */ - -enum esp32s3_slow_clk_sel_e -{ - /* Internal 150 kHz RC oscillator */ - - SLOW_CLK_150K = RTC_SLOW_FREQ_RTC, - - /* External 32 kHz XTAL */ - - SLOW_CLK_32K_XTAL = RTC_SLOW_FREQ_32K_XTAL, - - /* Internal 8 MHz RC oscillator, divided by 256 */ - - SLOW_CLK_8MD256 = RTC_SLOW_FREQ_8MD256, - - /* External 32k oscillator connected to 32K_XP pin */ - - SLOW_CLK_32K_EXT_OSC = RTC_SLOW_FREQ_32K_XTAL | EXT_OSC_FLAG -}; - -/* Clock source to be calibrated using rtc_clk_cal function */ - -enum esp32s3_rtc_cal_sel_e -{ - RTC_CAL_RTC_MUX = 0, /* Currently selected RTC SLOW_CLK */ - RTC_CAL_8MD256 = 1, /* Internal 8 MHz RC oscillator, divided by 256 */ - RTC_CAL_32K_XTAL = 2, /* External 32 kHz XTAL */ - RTC_CAL_INTERNAL_OSC = 3 /* Internal 150 kHz oscillator */ -}; - -/* CPU clock configuration structure */ - -struct esp32s3_cpu_freq_config_s -{ - /* The clock from which CPU clock is derived */ - - enum esp32s3_rtc_cpu_freq_src_e source; - uint32_t source_freq_mhz; /* Source clock frequency */ - uint32_t div; /* Divider, freq_mhz = source_freq_mhz / div */ - uint32_t freq_mhz; /* CPU clock frequency */ -}; - -#ifdef CONFIG_RTC_ALARM - -/* The form of an alarm callback */ - -typedef void (*alm_callback_t)(void *arg, unsigned int alarmid); - -enum alm_id_e -{ - RTC_ALARM0 = 0, /* RTC ALARM 0 */ - RTC_ALARM1 = 1, /* RTC ALARM 1 */ - RTC_ALARM_LAST, -}; - -/* Structure used to pass parameters to set an alarm */ - -struct alm_setalarm_s -{ - int as_id; /* enum alm_id_e */ - struct timespec as_time; /* Alarm expiration time */ - alm_callback_t as_cb; /* Callback (if non-NULL) */ - void *as_arg; /* Argument for callback */ -}; - -#endif /* CONFIG_RTC_ALARM */ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32s3_rtc_clk_slow_freq_get - * - * Description: - * This function gets the frequency of the slow clock from the RTC. - * - * Input Parameters: - * None - * - * Returned Value: - * The frequency of the slow clock from the RTC. - * - ****************************************************************************/ - -int esp32s3_rtc_clk_slow_freq_get(void); - -/**************************************************************************** - * Name: esp32s3_rtc_clk_slow_freq_get_hz - * - * Description: - * Get the approximate frequency of RTC_SLOW_CLK, in Hz - * - * Input Parameters: - * None - * - * Returned Value: - * slow_clk_freq - RTC_SLOW_CLK frequency, in Hz - * - ****************************************************************************/ - -uint32_t esp32s3_rtc_clk_slow_freq_get_hz(void); - -/**************************************************************************** - * Name: esp32s3_rtc_clk_fast_freq_get_hz - * - * Description: - * Get fast_clk_rtc source in Hz. - * - * Input Parameters: - * None - * - * Returned Value: - * The clock source in Hz. - * - ****************************************************************************/ - -uint32_t esp32s3_rtc_clk_fast_freq_get_hz(void); - -/**************************************************************************** - * Name: esp32s3_rtc_get_slow_clk_rtc - * - * Description: - * Get slow_clk_rtc source. - * - * Input Parameters: - * None - * - * Returned Value: - * The clock source: - * - SLOW_CK - * - CK_XTAL_32K - * - CK8M_D256_OUT - * - ****************************************************************************/ - -enum esp32s3_rtc_slow_freq_e esp32s3_rtc_get_slow_clk(void); - -/**************************************************************************** - * Name: esp32s3_rtc_clk_cal - * - * Description: - * Measure RTC slow clock's period, based on main XTAL frequency - * - * Input Parameters: - * cal_clk - clock to be measured - * slowclk_cycles - number of slow clock cycles to average - * - * Returned Value: - * Average slow clock period in microseconds, Q13.19 fixed point format - * or 0 if calibration has timed out - * - ****************************************************************************/ - -uint32_t esp32s3_rtc_clk_cal(enum esp32s3_rtc_cal_sel_e cal_clk, - uint32_t slowclk_cycles); - -/**************************************************************************** - * Name: esp32s3_rtc_clk_xtal_freq_get - * - * Description: - * Get main XTAL frequency - * - * Input Parameters: - * None - * - * Returned Value: - * XTAL frequency (one of enum esp32s3_rtc_xtal_freq_e values) - * - ****************************************************************************/ - -enum esp32s3_rtc_xtal_freq_e esp32s3_rtc_clk_xtal_freq_get(void); - -/**************************************************************************** - * Name: esp32s3_rtc_update_to_xtal - * - * Description: - * Switch to XTAL frequency, does not disable the PLL - * - * Input Parameters: - * freq - XTAL frequency - * div - REF_TICK divider - * - * Returned Value: - * none - * - ****************************************************************************/ - -void esp32s3_rtc_update_to_xtal(int freq, int div); - -/**************************************************************************** - * Name: esp32s3_rtc_clk_set - * - * Description: - * Set RTC CLK frequency. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32s3_rtc_clk_set(void); - -/**************************************************************************** - * Name: esp32s3_rtc_init - * - * Description: - * Initialize RTC clock and power control related functions. - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32s3_rtc_init(void); - -/**************************************************************************** - * Name: esp32s3_rtc_time_get - * - * Description: - * Get current value of RTC counter. - * - * Input Parameters: - * None - * - * Returned Value: - * current value of RTC counter - * - ****************************************************************************/ - -uint64_t esp32s3_rtc_time_get(void); - -/**************************************************************************** - * Name: esp32s3_rtc_sleep_low_init - * - * Description: - * Low level initialize for rtc state machine waiting - * cycles after waking up. - * - * Input Parameters: - * slowclk_period - Re-calibrated slow clock period - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32s3_rtc_sleep_low_init(uint32_t slowclk_period); - -/**************************************************************************** - * Name: esp32s3_rtc_time_us_to_slowclk - * - * Description: - * Convert time interval from microseconds to RTC_SLOW_CLK cycles. - * - * Input Parameters: - * time_in_us - Time interval in microseconds - * slow_clk_period - Period of slow clock in microseconds - * - * Returned Value: - * number of slow clock cycles - * - ****************************************************************************/ - -uint64_t esp32s3_rtc_time_us_to_slowclk(uint64_t time_in_us, - uint32_t period); - -/**************************************************************************** - * Name: esp32s3_rtc_time_slowclk_to_us - * - * Description: - * Convert time interval from RTC_SLOW_CLK to microseconds - * - * Input Parameters: - * rtc_cycles - Time interval in RTC_SLOW_CLK cycles - * period - Period of slow clock in microseconds - * - * Returned Value: - * Time interval in microseconds - * - ****************************************************************************/ - -uint64_t esp32s3_rtc_time_slowclk_to_us(uint64_t rtc_cycles, - uint32_t period); - -/**************************************************************************** - * Name: esp32s3_clk_slowclk_cal_get - * - * Description: - * Get the calibration value of RTC slow clock. - * - * Input Parameters: - * None - * - * Returned Value: - * the calibration value obtained using rtc_clk_cal - * - ****************************************************************************/ - -uint32_t esp32s3_clk_slowclk_cal_get(void); - -/**************************************************************************** - * Name: esp32s3_rtc_sleep_set_wakeup_time - * - * Description: - * Set target value of RTC counter for RTC_TIMER_TRIG_EN wakeup source. - * - * Input Parameters: - * t - value of RTC counter at which wakeup from sleep will happen. - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32s3_rtc_sleep_set_wakeup_time(uint64_t t); - -/**************************************************************************** - * Name: esp32s3_rtc_wait_for_slow_cycle - * - * Description: - * Busy loop until next RTC_SLOW_CLK cycle. - * - * Input Parameters: - * None - * - * Returned Value: - * none - * - ****************************************************************************/ - -void esp32s3_rtc_wait_for_slow_cycle(void); - -/**************************************************************************** - * Name: esp32s3_rtc_cpu_freq_set_xtal - * - * Description: - * Switch CPU clock source to XTAL - * - * Input Parameters: - * None - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32s3_rtc_cpu_freq_set_xtal(void); - -/**************************************************************************** - * Name: esp_rtc_clk_get_cpu_freq - * - * Description: - * Get the currently used CPU frequency configuration. - * - * Input Parameters: - * None - * - * Returned Value: - * CPU frequency - * - ****************************************************************************/ - -int esp_rtc_clk_get_cpu_freq(void); - -/**************************************************************************** - * Name: esp32s3_rtc_sleep_init - * - * Description: - * Prepare the chip to enter sleep mode - * - * Input Parameters: - * flags - sleep mode configuration - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32s3_rtc_sleep_init(uint32_t flags); - -/**************************************************************************** - * Name: esp32s3_rtc_ext1_prepare - * - * Description: - * Configure RTC_EXT1 wakeup sources - * - * Input Parameters: - * trigger_mode - trigger mode for RTC_EXT1 wakeup sources - * rtc_gpio_mask - mask of GPIOs to be used as RTC_EXT1 wakeup sources - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32s3_rtc_ext1_prepare(uint32_t trigger_mode, uint32_t rtc_gpio_mask); - -/**************************************************************************** - * Name: esp32s3_rtc_sleep_start - * - * Description: - * Enter force sleep mode. - * - * Input Parameters: - * wakeup_opt - bit mask wake up reasons to enable - * reject_opt - bit mask of sleep reject reasons. - * - * Returned Value: - * non-zero if sleep was rejected by hardware - * - ****************************************************************************/ - -int esp32s3_rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt); - -/**************************************************************************** - * Name: esp32s3_rtc_get_time_us - * - * Description: - * Get current value of RTC counter in microseconds - * - * Input Parameters: - * None - * - * Returned Value: - * Current value of RTC counter in microseconds - * - ****************************************************************************/ - -uint64_t esp32s3_rtc_get_time_us(void); - -/**************************************************************************** - * Name: esp32s3_rtc_set_boot_time - * - * Description: - * Set time to RTC register to replace the original boot time. - * - * Input Parameters: - * time_us - set time in microseconds. - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32s3_rtc_set_boot_time(uint64_t time_us); - -/**************************************************************************** - * Name: esp32s3_rtc_get_boot_time - * - * Description: - * Get time of RTC register to indicate the original boot time. - * - * Input Parameters: - * None - * - * Returned Value: - * time_us - get time in microseconds. - * - ****************************************************************************/ - -uint64_t esp32s3_rtc_get_boot_time(void); - -/**************************************************************************** - * Name: esp32s3_rtc_clk_cpu_freq_set_config - * - * Description: - * Set CPU frequency configuration. - * - * Input Parameters: - * config - CPU frequency configuration - * - * Returned Value: - * None - * - ****************************************************************************/ - -void esp32s3_rtc_clk_cpu_freq_set_config( - const struct esp32s3_cpu_freq_config_s *config); - -/**************************************************************************** - * Name: esp32s3_rtc_clk_cpu_freq_get_config - * - * Description: - * Get the currently used CPU frequency configuration. - * - * Input Parameters: - * None - * - * Returned Value: - * CPU clock configuration structure - * - ****************************************************************************/ - -void esp32s3_rtc_clk_cpu_freq_get_config( - struct esp32s3_cpu_freq_config_s *out_config); - -/**************************************************************************** - * Name: esp32s3_rtc_recalib_bbpll - * - * Description: - * Re-calibration BBPLL, workaround for bootloader not calibration well - * issue. - * - * Input Parameters: - * None - * - * Returned Value: - * None. - * - ****************************************************************************/ - -#ifdef CONFIG_ESP32S3_SYSTEM_BBPLL_RECALIB -void esp32s3_rtc_recalib_bbpll(void); -#endif - -#ifdef CONFIG_RTC_DRIVER - -/**************************************************************************** - * Name: up_rtc_time - * - * Description: - * Get the current time in seconds. This is similar to the standard time() - * function. This interface is only required if the low-resolution - * RTC/counter hardware implementation selected. It is only used by the - * RTOS during initialization to set up the system time when CONFIG_RTC is - * set but neither CONFIG_RTC_HIRES nor CONFIG_RTC_DATETIME are set. - * - * Input Parameters: - * None - * - * Returned Value: - * The current time in seconds - * - ****************************************************************************/ - -#ifndef CONFIG_RTC_HIRES -time_t up_rtc_time(void); -#endif - -/**************************************************************************** - * Name: up_rtc_settime - * - * Description: - * Set the RTC to the provided time. All RTC implementations must be - * able to set their time based on a standard timespec. - * - * Input Parameters: - * tp - the time to use - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -int up_rtc_settime(const struct timespec *ts); - -/**************************************************************************** - * Name: up_rtc_initialize - * - * Description: - * Initialize the hardware RTC per the selected configuration. - * This function is called once during the OS initialization sequence - * - * Input Parameters: - * None - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -int up_rtc_initialize(void); - -/**************************************************************************** - * Name: up_rtc_gettime - * - * Description: - * Get the current time from the high resolution RTC clock/counter. This - * interface is only supported by the high-resolution RTC/counter hardware - * implementation. It is used to replace the system timer. - * - * Input Parameters: - * tp - The location to return the high resolution time value. - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_HIRES -int up_rtc_gettime(struct timespec *tp); -#endif - -#ifdef CONFIG_RTC_ALARM - -/**************************************************************************** - * Name: up_rtc_setalarm - * - * Description: - * Set up an alarm. - * - * Input Parameters: - * alminfo - Information about the alarm configuration. - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -int up_rtc_setalarm(struct alm_setalarm_s *alminfo); - -/**************************************************************************** - * Name: up_rtc_cancelalarm - * - * Description: - * Cancel an alaram. - * - * Input Parameters: - * alarmid - Identifies the alarm to be cancelled - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -int up_rtc_cancelalarm(enum alm_id_e alarmid); - -/**************************************************************************** - * Name: up_rtc_rdalarm - * - * Description: - * Query an alarm configured in hardware. - * - * Input Parameters: - * tp - Location to return the timer match register. - * alarmid - Identifies the alarm to be cancelled - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -int up_rtc_rdalarm(struct timespec *tp, uint32_t alarmid); - -#endif /* CONFIG_RTC_ALARM */ - -/**************************************************************************** - * Name: up_rtc_timer_init - * - * Description: - * Init RTC timer. - * - * Input Parameters: - * None - * - * Returned Value: - * Zero (OK) on success; a negated errno on failure - * - ****************************************************************************/ - -int up_rtc_timer_init(void); - -#endif /* CONFIG_RTC_DRIVER */ - -#ifdef __cplusplus -} -#endif -#undef EXTERN - -#endif /* __ASSEMBLY__ */ -#endif /* __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_RTC_H */ diff --git a/arch/xtensa/src/esp32s3/esp32s3_rtc_gpio.c b/arch/xtensa/src/esp32s3/esp32s3_rtc_gpio.c index 0e082379effd0..8c86cadeb7d50 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_rtc_gpio.c +++ b/arch/xtensa/src/esp32s3/esp32s3_rtc_gpio.c @@ -34,7 +34,7 @@ #include #include "xtensa.h" -#include "esp32s3_irq.h" +#include "esp_irq.h" #include "esp32s3_rtc_gpio.h" #include "hardware/esp32s3_pinmap.h" #include "hardware/esp32s3_rtc_io.h" @@ -59,6 +59,14 @@ enum rtcio_lh_out_mode_e RTCIO_OUTPUT_OD = 0x1, /* RTCIO output mode is open-drain. */ }; +/* Structure to store RTC GPIO interrupt handlers */ + +struct rtcio_handler_s +{ + xcpt_t handler; /* User interrupt handler */ + void *arg; /* Argument for handler */ +}; + /**************************************************************************** * Private Data ****************************************************************************/ @@ -66,6 +74,7 @@ enum rtcio_lh_out_mode_e #ifdef CONFIG_ESP32S3_RTCIO_IRQ static int g_rtcio_cpuint; static uint32_t last_status; +static struct rtcio_handler_s g_rtcio_handlers[ESP32S3_NIRQ_RTCIO_PERIPH]; #endif static const uint32_t rtc_gpio_to_addr[] = @@ -129,6 +138,7 @@ static inline bool is_valid_rtc_gpio(uint32_t rtcio_num) * * Input Parameters: * irq - The IRQ number; + * context - The interrupt context; * reg_status - Pointer to a copy of the interrupt status register. * * Returned Value: @@ -137,7 +147,7 @@ static inline bool is_valid_rtc_gpio(uint32_t rtcio_num) ****************************************************************************/ #ifdef CONFIG_ESP32S3_RTCIO_IRQ -static void rtcio_dispatch(int irq, uint32_t *reg_status) +static void rtcio_dispatch(int irq, void *context, uint32_t *reg_status) { uint32_t status = *reg_status; uint32_t mask; @@ -152,11 +162,14 @@ static void rtcio_dispatch(int irq, uint32_t *reg_status) mask = (UINT32_C(1) << i); if ((status & mask) != 0) { - /* Yes... perform the second level dispatch. The IRQ context will - * contain the contents of the status register. - */ + /* Call the registered handler if one exists */ - irq_dispatch(irq + i, (void *)reg_status); + if (g_rtcio_handlers[i].handler != NULL) + { + g_rtcio_handlers[i].handler(irq, + (void *)reg_status, + g_rtcio_handlers[i].arg); + } /* Clear the bit in the status so that we might execute this loop * sooner. @@ -189,12 +202,12 @@ static int rtcio_interrupt(int irq, void *context, void *arg) { /* Read and clear the lower RTC interrupt status */ - last_status = getreg32(RTC_CNTL_INT_ST_RTC_REG); - putreg32(last_status, RTC_CNTL_INT_CLR_RTC_REG); + last_status = getreg32(RTC_CNTL_INT_ST_REG); + putreg32(last_status, RTC_CNTL_INT_CLR_REG); /* Dispatch pending interrupts in the RTC status register */ - rtcio_dispatch(ESP32S3_FIRST_RTCIOIRQ_PERIPH, &last_status); + rtcio_dispatch(irq, context, &last_status); return OK; } @@ -427,7 +440,7 @@ void esp32s3_rtciowrite(int rtcio_num, bool value) } /**************************************************************************** - * Name: esp32s3_rtcioirqinitialize + * Name: esp_rtcioirqinitialize * * Description: * Initialize logic to support a second level of interrupt decoding for @@ -442,18 +455,27 @@ void esp32s3_rtciowrite(int rtcio_num, bool value) ****************************************************************************/ #ifdef CONFIG_ESP32S3_RTCIO_IRQ -void esp32s3_rtcioirqinitialize(void) +void esp_rtcioirqinitialize(void) { - /* Setup the RTCIO interrupt. */ + int i; + + /* Initialize handler array */ - int cpu = this_cpu(); - g_rtcio_cpuint = esp32s3_setup_irq(cpu, ESP32S3_PERIPH_RTC_CORE, - 1, ESP32S3_CPUINT_LEVEL); + for (i = 0; i < ESP32S3_NIRQ_RTCIO_PERIPH; i++) + { + g_rtcio_handlers[i].handler = NULL; + g_rtcio_handlers[i].arg = NULL; + } + + /* Setup the RTCIO interrupt with handler. */ + + g_rtcio_cpuint = esp_setup_irq(ESP32S3_PERIPH_RTC_CORE, + 1, ESP_IRQ_TRIGGER_LEVEL, + rtcio_interrupt, NULL); DEBUGASSERT(g_rtcio_cpuint >= 0); - /* Attach and enable the interrupt handler */ + /* Enable the interrupt */ - DEBUGVERIFY(irq_attach(ESP32S3_IRQ_RTC_CORE, rtcio_interrupt, NULL)); up_enable_irq(ESP32S3_IRQ_RTC_CORE); } #endif @@ -475,7 +497,7 @@ void esp32s3_rtcioirqinitialize(void) #ifdef CONFIG_ESP32S3_RTCIO_IRQ void esp32s3_rtcioirqenable(int irq) { - uintptr_t regaddr = RTC_CNTL_INT_ENA_RTC_REG; + uintptr_t regaddr = RTC_CNTL_INT_ENA_REG; uint32_t regval; int bit; @@ -514,7 +536,7 @@ void esp32s3_rtcioirqenable(int irq) #ifdef CONFIG_ESP32S3_RTCIO_IRQ void esp32s3_rtcioirqdisable(int irq) { - uintptr_t regaddr = RTC_CNTL_INT_ENA_RTC_REG; + uintptr_t regaddr = RTC_CNTL_INT_ENA_REG; uint32_t regval; int bit; @@ -535,3 +557,81 @@ void esp32s3_rtcioirqdisable(int irq) up_enable_irq(ESP32S3_IRQ_RTC_CORE); } #endif + +/**************************************************************************** + * Name: esp32s3_rtcioirqattach + * + * Description: + * Attach an interrupt handler to a specified RTC IRQ + * + * Input Parameters: + * irq - RTC IRQ number to attach the handler to + * handler - Interrupt handler function + * arg - Argument to pass to the handler + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32S3_RTCIO_IRQ +int esp32s3_rtcioirqattach(int irq, xcpt_t handler, void *arg) +{ + int bit; + + DEBUGASSERT(irq >= ESP32S3_FIRST_RTCIOIRQ_PERIPH && + irq <= ESP32S3_LAST_RTCIOIRQ_PERIPH); + + /* Convert the IRQ number to the corresponding bit */ + + bit = irq - ESP32S3_FIRST_RTCIOIRQ_PERIPH; + + DEBUGASSERT(bit >= 0 && bit < ESP32S3_NIRQ_RTCIO_PERIPH); + + /* Store the handler and argument */ + + g_rtcio_handlers[bit].handler = handler; + g_rtcio_handlers[bit].arg = arg; + + return OK; +} +#endif + +/**************************************************************************** + * Name: esp32s3_rtcioirqdetach + * + * Description: + * Detach an interrupt handler from a specified RTC IRQ + * + * Input Parameters: + * irq - RTC IRQ number to detach the handler from + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32S3_RTCIO_IRQ +int esp32s3_rtcioirqdetach(int irq) +{ + int bit; + + DEBUGASSERT(irq >= ESP32S3_FIRST_RTCIOIRQ_PERIPH && + irq <= ESP32S3_LAST_RTCIOIRQ_PERIPH); + + /* Convert the IRQ number to the corresponding bit */ + + bit = irq - ESP32S3_FIRST_RTCIOIRQ_PERIPH; + + DEBUGASSERT(bit >= 0 && bit < ESP32S3_NIRQ_RTCIO_PERIPH); + + /* Clear the handler and argument */ + + g_rtcio_handlers[bit].handler = NULL; + g_rtcio_handlers[bit].arg = NULL; + + return OK; +} +#endif diff --git a/arch/xtensa/src/esp32s3/esp32s3_rtc_gpio.h b/arch/xtensa/src/esp32s3/esp32s3_rtc_gpio.h index 0700f2e68ad24..ee388d6464d7e 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_rtc_gpio.h +++ b/arch/xtensa/src/esp32s3/esp32s3_rtc_gpio.h @@ -31,7 +31,7 @@ #include #include "hardware/esp32s3_rtc_io.h" -#include "hardware/esp32s3_rtccntl.h" +#include "soc/rtc_cntl_reg.h" /**************************************************************************** * Pre-processor Definitions @@ -508,7 +508,7 @@ static const rtc_io_desc_t g_rtc_io_desc[RTC_GPIO_NUMBER] = RTCIO_RTC_PAD19_SLP_IE_M, RTCIO_RTC_PAD19_SLP_OE_M, 0, - RTC_CNTL_RTC_PAD19_HOLD_M, + RTC_CNTL_PAD19_HOLD_M, RTCIO_RTC_PAD19_DRV_V, RTCIO_RTC_PAD19_DRV_S, RTCIO_CHANNEL_19_GPIO_NUM @@ -524,7 +524,7 @@ static const rtc_io_desc_t g_rtc_io_desc[RTC_GPIO_NUMBER] = RTCIO_RTC_PAD20_SLP_IE_M, RTCIO_RTC_PAD20_SLP_OE_M, 0, - RTC_CNTL_RTC_PAD20_HOLD_M, + RTC_CNTL_PAD20_HOLD_M, RTCIO_RTC_PAD20_DRV_V, RTCIO_RTC_PAD20_DRV_S, RTCIO_CHANNEL_20_GPIO_NUM @@ -540,7 +540,7 @@ static const rtc_io_desc_t g_rtc_io_desc[RTC_GPIO_NUMBER] = RTCIO_RTC_PAD21_SLP_IE_M, RTCIO_RTC_PAD21_SLP_OE_M, 0, - RTC_CNTL_RTC_PAD21_HOLD_M, + RTC_CNTL_PAD21_HOLD_M, RTCIO_RTC_PAD21_DRV_V, RTCIO_RTC_PAD21_DRV_S, RTCIO_CHANNEL_21_GPIO_NUM @@ -609,7 +609,7 @@ int esp32s3_rtcioread(int rtcio_num); void esp32s3_rtciowrite(int rtcio_num, bool value); /**************************************************************************** - * Name: esp32s3_rtcioirqinitialize + * Name: esp_rtcioirqinitialize * * Description: * Initialize logic to support a second level of interrupt decoding for @@ -624,9 +624,9 @@ void esp32s3_rtciowrite(int rtcio_num, bool value); ****************************************************************************/ #ifdef CONFIG_ESP32S3_RTCIO_IRQ -void esp32s3_rtcioirqinitialize(void); +void esp_rtcioirqinitialize(void); #else -# define esp32s3_rtcioirqinitialize() +# define esp_rtcioirqinitialize() #endif /**************************************************************************** @@ -669,5 +669,48 @@ void esp32s3_rtcioirqdisable(int irq); # define esp32s3_rtcioirqdisable(irq) #endif +/**************************************************************************** + * Name: esp32s3_rtcioirqattach + * + * Description: + * Attach an interrupt handler to a specified RTC IRQ + * + * Input Parameters: + * irq - RTC IRQ number to attach the handler to + * handler - Interrupt handler function + * arg - Argument to pass to the handler + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32S3_RTCIO_IRQ +int esp32s3_rtcioirqattach(int irq, xcpt_t handler, void *arg); +#else +# define esp32s3_rtcioirqattach(irq, handler, arg) (-ENOSYS) +#endif +/**************************************************************************** + * Name: esp32s3_rtcioirqdetach + * + * Description: + * Detach an interrupt handler from a specified RTC IRQ + * + * Input Parameters: + * irq - RTC IRQ number to detach the handler from + * + * Returned Value: + * Zero (OK) is returned on success; A negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32S3_RTCIO_IRQ +int esp32s3_rtcioirqdetach(int irq); +#else +# define esp32s3_rtcioirqdetach(irq) (-ENOSYS) +#endif + #endif /* __ASSEMBLY__ */ #endif /* __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_RTC_GPIO_H */ diff --git a/arch/xtensa/src/esp32s3/esp32s3_rtc_lowerhalf.c b/arch/xtensa/src/esp32s3/esp32s3_rtc_lowerhalf.c deleted file mode 100644 index 483625e492954..0000000000000 --- a/arch/xtensa/src/esp32s3/esp32s3_rtc_lowerhalf.c +++ /dev/null @@ -1,559 +0,0 @@ -/**************************************************************************** - * arch/xtensa/src/esp32s3/esp32s3_rtc_lowerhalf.c - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include -#include - -#include -#include -#include -#include -#include -#include - -#include -#include - -#include "esp32s3_rtc.h" -#include "hardware/esp32s3_tim.h" - -/**************************************************************************** - * Private Types - ****************************************************************************/ - -#ifdef CONFIG_RTC_ALARM -struct esp32s3_cbinfo_s -{ - volatile rtc_alarm_callback_t cb; /* Callback when the alarm expires */ - volatile void *priv; /* Private argurment to accompany callback */ -}; -#endif - -/* This is the private type for the RTC state. It must be cast compatible - * with struct rtc_lowerhalf_s. - */ - -struct esp32s3_lowerhalf_s -{ - /* This is the contained reference to the read-only, lower-half - * operations vtable (which may lie in FLASH or ROM) - */ - - const struct rtc_ops_s *ops; - spinlock_t lock; -#ifdef CONFIG_RTC_ALARM - /* Alarm callback information */ - - struct esp32s3_cbinfo_s cbinfo[RTC_ALARM_LAST]; -#endif -}; - -/**************************************************************************** - * Private Function Prototypes - ****************************************************************************/ - -/* Prototypes for static methods in struct rtc_ops_s */ - -static int rtc_lh_rdtime(struct rtc_lowerhalf_s *lower, - struct rtc_time *rtctime); -static int rtc_lh_settime(struct rtc_lowerhalf_s *lower, - const struct rtc_time *rtctime); -static bool rtc_lh_havesettime(struct rtc_lowerhalf_s *lower); - -#ifdef CONFIG_RTC_ALARM -static void rtc_lh_alarm_callback(void *arg, unsigned int alarmid); -static int rtc_lh_setalarm(struct rtc_lowerhalf_s *lower, - const struct lower_setalarm_s *alarminfo); -static int rtc_lh_setrelative(struct rtc_lowerhalf_s *lower, - const struct lower_setrelative_s *alarminfo); -static int rtc_lh_cancelalarm(struct rtc_lowerhalf_s *lower, - int alarmid); -static int rtc_lh_rdalarm(struct rtc_lowerhalf_s *lower, - struct lower_rdalarm_s *alarminfo); -#endif - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/* ESP32 RTC driver operations */ - -static const struct rtc_ops_s g_rtc_ops = -{ - .rdtime = rtc_lh_rdtime, - .settime = rtc_lh_settime, - .havesettime = rtc_lh_havesettime, -#ifdef CONFIG_RTC_ALARM - .setalarm = rtc_lh_setalarm, - .setrelative = rtc_lh_setrelative, - .cancelalarm = rtc_lh_cancelalarm, - .rdalarm = rtc_lh_rdalarm, -#endif -}; - -/* ESP32 RTC device state */ - -static struct esp32s3_lowerhalf_s g_rtc_lowerhalf = -{ - .ops = &g_rtc_ops, - .lock = SP_UNLOCKED, -}; - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: rtc_lh_alarm_callback - * - * Description: - * This is the function that is called from the RTC driver when the alarm - * goes off. It just invokes the upper half drivers callback. - * - * Returned Value: - * None - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_ALARM -static void rtc_lh_alarm_callback(void *arg, unsigned int alarmid) -{ - struct esp32s3_lowerhalf_s *lower; - struct esp32s3_cbinfo_s *cbinfo; - rtc_alarm_callback_t cb; - void *priv; - - DEBUGASSERT((RTC_ALARM0 <= alarmid) && (alarmid < RTC_ALARM_LAST)); - - lower = (struct esp32s3_lowerhalf_s *)arg; - cbinfo = &lower->cbinfo[alarmid]; - - /* Sample and clear the callback information to minimize the window in - * time in which race conditions can occur. - */ - - cb = (rtc_alarm_callback_t)cbinfo->cb; - priv = (void *)cbinfo->priv; - - cbinfo->cb = NULL; - cbinfo->priv = NULL; - - /* Perform the callback */ - - if (cb != NULL) - { - cb(priv, alarmid); - } -} -#endif /* CONFIG_RTC_ALARM */ - -/**************************************************************************** - * Name: rtc_lh_rdtime - * - * Description: - * Returns the current RTC time. - * - * Input Parameters: - * lower - A reference to RTC lower half driver state structure - * rcttime - The location in which to return the current RTC time. - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on any failure. - * - ****************************************************************************/ - -static int rtc_lh_rdtime(struct rtc_lowerhalf_s *lower, - struct rtc_time *rtctime) -{ -#if defined(CONFIG_RTC_HIRES) - struct timespec ts; - int ret; - - /* Get the higher resolution time */ - - ret = up_rtc_gettime(&ts); - if (ret < 0) - { - goto errout; - } - - /* Convert the one second epoch time to a struct tm. This operation - * depends on the fact that struct rtc_time and struct tm are cast - * compatible. - */ - - if (!gmtime_r(&ts.tv_sec, (struct tm *)rtctime)) - { - ret = -get_errno(); - goto errout; - } - - return OK; - -errout: - rtcerr("ERROR: failed to get RTC time: %d\n", ret); - return ret; - -#else - time_t timer; - - /* The resolution of time is only 1 second */ - - timer = up_rtc_time(); - - /* Convert the one second epoch time to a struct tm */ - - if (gmtime_r(&timer, (struct tm *)rtctime) == 0) - { - int errcode = get_errno(); - DEBUGASSERT(errcode > 0); - - rtcerr("ERROR: gmtime_r failed: %d\n", errcode); - return -errcode; - } - - return OK; -#endif -} - -/**************************************************************************** - * Name: rtc_lh_settime - * - * Description: - * Implements the settime() method of the RTC driver interface - * - * Input Parameters: - * lower - A reference to RTC lower half driver state structure - * rcttime - The new time to set - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on any failure. - * - ****************************************************************************/ - -static int rtc_lh_settime(struct rtc_lowerhalf_s *lower, - const struct rtc_time *rtctime) -{ - struct timespec ts; - - /* Convert the struct rtc_time to a time_t. Here we assume that struct - * rtc_time is cast compatible with struct tm. - */ - - ts.tv_sec = mktime((struct tm *)rtctime); - ts.tv_nsec = 0; - - /* Now set the time (with a accuracy of seconds) */ - - return up_rtc_settime(&ts); -} - -/**************************************************************************** - * Name: rtc_lh_havesettime - * - * Description: - * Implements the havesettime() method of the RTC driver interface - * - * Input Parameters: - * lower - A reference to RTC lower half driver state structure - * - * Returned Value: - * Returns true if RTC date-time have been previously set. - * - ****************************************************************************/ - -static bool rtc_lh_havesettime(struct rtc_lowerhalf_s *lower) -{ - if (esp32s3_rtc_get_boot_time() == 0) - { - return false; - } - - return true; -} - -/**************************************************************************** - * Name: rtc_lh_setalarm - * - * Description: - * Set a new alarm. This function implements the setalarm() method of the - * RTC driver interface - * - * Input Parameters: - * lower - A reference to RTC lower half driver state structure - * alarminfo - Provided information needed to set the alarm - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on any failure. - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_ALARM -static int rtc_lh_setalarm(struct rtc_lowerhalf_s *lower, - const struct lower_setalarm_s *alarminfo) -{ - struct esp32s3_lowerhalf_s *priv; - struct esp32s3_cbinfo_s *cbinfo; - struct alm_setalarm_s lowerinfo; - int ret; - - DEBUGASSERT(lower != NULL && alarminfo != NULL); - DEBUGASSERT((RTC_ALARM0 <= alarminfo->id) && - (alarminfo->id < RTC_ALARM_LAST)); - - priv = (struct esp32s3_lowerhalf_s *)lower; - - /* Remember the callback information */ - - cbinfo = &priv->cbinfo[alarminfo->id]; - cbinfo->cb = alarminfo->cb; - cbinfo->priv = alarminfo->priv; - - /* Set the alarm */ - - lowerinfo.as_id = alarminfo->id; - lowerinfo.as_cb = rtc_lh_alarm_callback; - lowerinfo.as_arg = priv; - - /* Convert the RTC time to a timespec (1 second accuracy) */ - - lowerinfo.as_time.tv_sec = mktime((struct tm *)&alarminfo->time); - lowerinfo.as_time.tv_nsec = 0; - - /* And set the alarm */ - - ret = up_rtc_setalarm(&lowerinfo); - if (ret < 0) - { - cbinfo->cb = NULL; - cbinfo->priv = NULL; - } - - return ret; -} -#endif /* CONFIG_RTC_ALARM */ - -/**************************************************************************** - * Name: rtc_lh_setrelative - * - * Description: - * Set a new alarm relative to the current time. This function implements - * the setrelative() method of the RTC driver interface - * - * Input Parameters: - * lower - A reference to RTC lower half driver state structure - * alarminfo - Provided information needed to set the alarm - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on any failure. - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_ALARM -static int rtc_lh_setrelative(struct rtc_lowerhalf_s *lower, - const struct lower_setrelative_s *alarminfo) -{ - struct esp32s3_lowerhalf_s *priv = (struct esp32s3_lowerhalf_s *)lower; - struct lower_setalarm_s setalarm; - time_t seconds; - int ret = -EINVAL; - irqstate_t flags; - - DEBUGASSERT(lower != NULL && alarminfo != NULL); - DEBUGASSERT((RTC_ALARM0 <= alarminfo->id) && - (alarminfo->id < RTC_ALARM_LAST)); - - if (alarminfo->reltime > 0) - { - flags = spin_lock_irqsave(&priv->lock); - - seconds = alarminfo->reltime; - gmtime_r(&seconds, (struct tm *)&setalarm.time); - - /* The set the alarm using this absolute time */ - - setalarm.id = alarminfo->id; - setalarm.cb = alarminfo->cb; - setalarm.priv = alarminfo->priv; - ret = rtc_lh_setalarm(lower, &setalarm); - - spin_unlock_irqrestore(&priv->lock, flags); - } - - return ret; -} -#endif /* CONFIG_RTC_ALARM */ - -/**************************************************************************** - * Name: rtc_lh_cancelalarm - * - * Description: - * Cancel the current alarm. This function implements the cancelalarm() - * method of the RTC driver interface - * - * Input Parameters: - * lower - A reference to RTC lower half driver state structure - * alarmid - the alarm id - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on any failure. - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_ALARM -static int rtc_lh_cancelalarm(struct rtc_lowerhalf_s *lower, int alarmid) -{ - struct esp32s3_lowerhalf_s *priv; - struct esp32s3_cbinfo_s *cbinfo; - - DEBUGASSERT(lower != NULL); - DEBUGASSERT((RTC_ALARM0 <= alarmid) && (alarmid < RTC_ALARM_LAST)); - - priv = (struct esp32s3_lowerhalf_s *)lower; - - /* Nullify callback information to reduce window for race conditions */ - - cbinfo = &priv->cbinfo[alarmid]; - cbinfo->cb = NULL; - cbinfo->priv = NULL; - - /* Then cancel the alarm */ - - return up_rtc_cancelalarm((enum alm_id_e)alarmid); -} -#endif /* CONFIG_RTC_ALARM */ - -/**************************************************************************** - * Name: rtc_lh_rdalarm - * - * Description: - * Query the RTC alarm. - * - * Input Parameters: - * lower - A reference to RTC lower half driver state structure - * alarminfo - Provided information needed to query the alarm - * - * Returned Value: - * Zero (OK) is returned on success; a negated errno value is returned - * on any failure. - * - ****************************************************************************/ - -#ifdef CONFIG_RTC_ALARM -static int rtc_lh_rdalarm(struct rtc_lowerhalf_s *lower, - struct lower_rdalarm_s *alarminfo) -{ - struct esp32s3_lowerhalf_s *priv = (struct esp32s3_lowerhalf_s *)lower; - struct timespec ts; - int ret; - irqstate_t flags; - - DEBUGASSERT(lower != NULL && alarminfo != NULL && alarminfo->time != NULL); - DEBUGASSERT((RTC_ALARM0 <= alarminfo->id) && - (alarminfo->id < RTC_ALARM_LAST)); - - flags = spin_lock_irqsave(&priv->lock); - - ret = up_rtc_rdalarm(&ts, alarminfo->id); - localtime_r((const time_t *)&ts.tv_sec, - (struct tm *)alarminfo->time); - - spin_unlock_irqrestore(&priv->lock, flags); - - return ret; -} -#endif /* CONFIG_RTC_ALARM */ - -/**************************************************************************** - * Public Functions - ****************************************************************************/ - -/**************************************************************************** - * Name: esp32s3_rtc_lowerhalf - * - * Description: - * Instantiate the RTC lower half driver for the ESP32. - * - * Input Parameters: - * None - * - * Returned Value: - * On success, a non-NULL RTC lower interface is returned. NULL is - * returned on any failure. - * - ****************************************************************************/ - -struct rtc_lowerhalf_s *esp32s3_rtc_lowerhalf(void) -{ - return (struct rtc_lowerhalf_s *)&g_rtc_lowerhalf; -} - -/**************************************************************************** - * Name: esp32s3_rtc_driverinit - * - * Description: - * Bind the configuration timer to a timer lower half instance and register - * the timer drivers at 'devpath' - * - * Input Parameters: - * None - * - * Returned Value: - * Zero (OK) is returned on success; A negated errno value is returned - * to indicate the nature of any failure. - * - ****************************************************************************/ - -int esp32s3_rtc_driverinit(void) -{ - int ret = ERROR; - struct rtc_lowerhalf_s *lower; - - /* Instantiate the ESP32 lower-half RTC driver */ - - lower = esp32s3_rtc_lowerhalf(); - if (lower == NULL) - { - return ret; - } - else - { - /* Bind the lower half driver and register the combined RTC driver - * as /dev/rtc0 - */ - - ret = rtc_initialize(0, lower); - } - - /* Init RTC timer */ - - up_rtc_timer_init(); - - return ret; -} diff --git a/arch/xtensa/src/esp32s3/esp32s3_sdmmc.c b/arch/xtensa/src/esp32s3/esp32s3_sdmmc.c index d49bc0e479002..bdad94ddef8cb 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_sdmmc.c +++ b/arch/xtensa/src/esp32s3/esp32s3_sdmmc.c @@ -44,8 +44,8 @@ #endif #include "xtensa.h" -#include "esp32s3_gpio.h" -#include "esp32s3_irq.h" +#include "esp_gpio.h" +#include "esp_irq.h" #include "hardware/esp32s3_sdmmc.h" #include "hardware/esp32s3_system.h" #include "hardware/esp32s3_gpio_sigmap.h" @@ -547,16 +547,16 @@ static int esp32s3_ciu_sendcmd(uint32_t cmd, uint32_t arg) static void configure_pin(uint8_t gpio_pin, uint8_t sdio_pin, gpio_pinattr_t attr) { - esp32s3_configgpio(gpio_pin, attr); + esp_configgpio(gpio_pin, attr); if (attr & INPUT) { - esp32s3_gpio_matrix_in(gpio_pin, sdio_pin, false); + esp_gpio_matrix_in(gpio_pin, sdio_pin, false); } if (attr & OUTPUT) { - esp32s3_gpio_matrix_out(gpio_pin, sdio_pin, false, false); + esp_gpio_matrix_out(gpio_pin, sdio_pin, false, false); } } @@ -1632,38 +1632,38 @@ static int esp32s3_attach(struct sdio_dev_s *dev) uint32_t regval; struct esp32s3_dev_s *priv = (struct esp32s3_dev_s *)dev; - ret = esp32s3_setup_irq(this_cpu(), ESP32S3_PERIPH_SDIO_HOST, - 1, ESP32S3_CPUINT_LEVEL); - DEBUGASSERT(ret >= 0); - - /* Attach the SDIO interrupt handler */ - - ret = irq_attach(ESP32S3_IRQ_SDIO_HOST, esp32s3_interrupt, dev); - if (ret == OK) + ret = esp_setup_irq(ESP32S3_PERIPH_SDIO_HOST, + 1, + ESP_IRQ_TRIGGER_LEVEL, + esp32s3_interrupt, + dev); + if (ret < 0) { - /* Disable all interrupts at the SD card controller and clear static - * interrupt flags - */ + return -ENOMEM; + } - esp32s3_putreg(0, ESP32S3_SDMMC_INTMASK); - esp32s3_putreg(SDMMC_INT_ALL(priv->slot), ESP32S3_SDMMC_RINTSTS); + /* Disable all interrupts at the SD card controller and clear static + * interrupt flags + */ - /* Enable Interrupts to happen when the INTMASK is activated */ + esp32s3_putreg(0, ESP32S3_SDMMC_INTMASK); + esp32s3_putreg(SDMMC_INT_ALL(priv->slot), ESP32S3_SDMMC_RINTSTS); - regval = esp32s3_getreg(ESP32S3_SDMMC_CTRL); - regval |= SDMMC_CTRL_INTENABLE; - esp32s3_putreg(regval, ESP32S3_SDMMC_CTRL); + /* Enable Interrupts to happen when the INTMASK is activated */ - /* Enable card detection interrupts */ + regval = esp32s3_getreg(ESP32S3_SDMMC_CTRL); + regval |= SDMMC_CTRL_INTENABLE; + esp32s3_putreg(regval, ESP32S3_SDMMC_CTRL); - esp32s3_putreg(SDCARD_INT_CDET, ESP32S3_SDMMC_INTMASK); + /* Enable card detection interrupts */ - /* Enable SD card interrupts at the NVIC. They can now be enabled at - * the SD card controller as needed. - */ + esp32s3_putreg(SDCARD_INT_CDET, ESP32S3_SDMMC_INTMASK); - up_enable_irq(ESP32S3_IRQ_SDIO_HOST); - } + /* Enable SD card interrupts at the NVIC. They can now be enabled at + * the SD card controller as needed. + */ + + up_enable_irq(ESP32S3_IRQ_SDIO_HOST); return ret; } @@ -2966,11 +2966,11 @@ struct sdio_dev_s *sdio_initialize(int slotno) configure_pin(CONFIG_ESP32S3_SDMMC_D0, priv->sdio_pins->d0, INPUT | OUTPUT | PULLUP); - esp32s3_gpio_matrix_in(GPIO_MATRIX_CONST_ONE_INPUT, + esp_gpio_matrix_in(GPIO_MATRIX_CONST_ONE_INPUT, priv->slot_info->card_int, false); - esp32s3_gpio_matrix_in(GPIO_MATRIX_CONST_ZERO_INPUT, + esp_gpio_matrix_in(GPIO_MATRIX_CONST_ZERO_INPUT, priv->slot_info->card_detect, false); - esp32s3_gpio_matrix_in(GPIO_MATRIX_CONST_ONE_INPUT, + esp_gpio_matrix_in(GPIO_MATRIX_CONST_ONE_INPUT, priv->slot_info->write_protect, true); return &priv->dev; diff --git a/arch/xtensa/src/esp32s3/esp32s3_serial.c b/arch/xtensa/src/esp32s3/esp32s3_serial.c index 90833091432b7..e334205fcaace 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_serial.c +++ b/arch/xtensa/src/esp32s3/esp32s3_serial.c @@ -43,9 +43,9 @@ #include "xtensa.h" #include "esp32s3_config.h" -#include "esp32s3_irq.h" +#include "esp_irq.h" #include "esp32s3_lowputc.h" -#include "esp32s3_gpio.h" +#include "esp_gpio.h" #include "hardware/esp32s3_uart.h" #include "hardware/esp32s3_system.h" @@ -323,8 +323,7 @@ static int uart_handler(int irq, void *context, void *arg) { if (dev->xmit.tail == dev->xmit.head) { - esp32s3_gpiowrite(priv->rs485_dir_gpio, - !priv->rs485_dir_polarity); + esp_gpiowrite(priv->rs485_dir_gpio, !priv->rs485_dir_polarity); } } #endif @@ -545,15 +544,14 @@ static void esp32s3_shutdown(struct uart_dev_s *dev) static int esp32s3_attach(struct uart_dev_s *dev) { struct esp32s3_uart_s *priv = dev->priv; - int ret; DEBUGASSERT(priv->cpuint == -ENOMEM); /* Set up to receive peripheral interrupts on the current CPU */ priv->cpu = this_cpu(); - priv->cpuint = esp32s3_setup_irq(priv->cpu, priv->periph, priv->int_pri, - ESP32S3_CPUINT_LEVEL); + priv->cpuint = esp_setup_irq(priv->periph, priv->int_pri, + ESP_IRQ_TRIGGER_LEVEL, uart_handler, dev); if (priv->cpuint < 0) { /* Failed to allocate a CPU interrupt of this type */ @@ -561,19 +559,9 @@ static int esp32s3_attach(struct uart_dev_s *dev) return priv->cpuint; } - /* Attach and enable the IRQ */ + up_enable_irq(priv->irq); - ret = irq_attach(priv->irq, uart_handler, dev); - if (ret == OK) - { - /* Enable the CPU interrupt (RX and TX interrupts are still disabled - * in the UART - */ - - up_enable_irq(priv->irq); - } - - return ret; + return OK; } /**************************************************************************** @@ -598,11 +586,10 @@ static void esp32s3_detach(struct uart_dev_s *dev) /* Disable and detach the CPU interrupt */ up_disable_irq(priv->irq); - irq_detach(priv->irq); /* Disassociate the peripheral interrupt from the CPU interrupt */ - esp32s3_teardown_irq(priv->cpu, priv->periph, priv->cpuint); + esp_teardown_irq(priv->periph, priv->cpuint); priv->cpuint = -ENOMEM; } @@ -793,7 +780,7 @@ static void esp32s3_send(struct uart_dev_s *dev, int ch) #ifdef HAVE_RS485 if (priv->rs485_dir_gpio != 0) { - esp32s3_gpiowrite(priv->rs485_dir_gpio, priv->rs485_dir_polarity); + esp_gpiowrite(priv->rs485_dir_gpio, priv->rs485_dir_polarity); } #endif diff --git a/arch/xtensa/src/esp32s3/esp32s3_spi.c b/arch/xtensa/src/esp32s3/esp32s3_spi.c index a509617add9b7..56e8949e641f4 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_spi.c +++ b/arch/xtensa/src/esp32s3/esp32s3_spi.c @@ -45,8 +45,8 @@ #include #include "esp32s3_spi.h" -#include "esp32s3_irq.h" -#include "esp32s3_gpio.h" +#include "esp_irq.h" +#include "esp_gpio.h" #ifdef CONFIG_ESP32S3_SPI_DMA #include "esp32s3_dma.h" @@ -597,7 +597,7 @@ static void esp32s3_spi_select(struct spi_dev_s *dev, if (priv->config->cs_pin >= 0) { - esp32s3_gpiowrite(priv->config->cs_pin, !selected); + esp_gpiowrite(priv->config->cs_pin, !selected); } #endif @@ -1426,7 +1426,7 @@ static int esp32s3_spi_init(struct spi_dev_s *dev) if (config->cs_pin >= 0) { - esp32s3_gpiowrite(config->cs_pin, true); + esp_gpiowrite(config->cs_pin, true); } #ifdef CONFIG_ESP32S3_SPI_UDCS #ifdef CONFIG_ESP32S3_SPI2 @@ -1445,21 +1445,21 @@ static int esp32s3_spi_init(struct spi_dev_s *dev) if (config->mosi_pin >= 0) { - esp32s3_gpiowrite(config->mosi_pin, true); + esp_gpiowrite(config->mosi_pin, true); } if (config->miso_pin >= 0) { - esp32s3_gpiowrite(config->miso_pin, true); + esp_gpiowrite(config->miso_pin, true); } - esp32s3_gpiowrite(config->clk_pin, true); + esp_gpiowrite(config->clk_pin, true); #if SPI_HAVE_SWCS if (config->cs_pin >= 0) { - esp32s3_configgpio(config->cs_pin, OUTPUT_FUNCTION_1); - esp32s3_gpio_matrix_out(config->cs_pin, SIG_GPIO_OUT_IDX, 0, 0); + esp_configgpio(config->cs_pin, OUTPUT_FUNCTION_1); + esp_gpio_matrix_out(config->cs_pin, SIG_GPIO_OUT_IDX, 0, 0); } #ifdef CONFIG_ESP32S3_SPI_UDCS #ifdef CONFIG_ESP32S3_SPI2 @@ -1484,51 +1484,51 @@ static int esp32s3_spi_init(struct spi_dev_s *dev) #if !SPI_HAVE_SWCS if (config->cs_pin >= 0) { - esp32s3_configgpio(config->cs_pin, OUTPUT_FUNCTION_5); - esp32s3_gpio_matrix_out(config->cs_pin, SIG_GPIO_OUT_IDX, 0, 0); + esp_configgpio(config->cs_pin, OUTPUT_FUNCTION_5); + esp_gpio_matrix_out(config->cs_pin, SIG_GPIO_OUT_IDX, 0, 0); } #endif if (config->mosi_pin >= 0) { - esp32s3_configgpio(config->mosi_pin, OUTPUT_FUNCTION_5); - esp32s3_gpio_matrix_out(config->mosi_pin, SIG_GPIO_OUT_IDX, 0, 0); + esp_configgpio(config->mosi_pin, OUTPUT_FUNCTION_5); + esp_gpio_matrix_out(config->mosi_pin, SIG_GPIO_OUT_IDX, 0, 0); } if (config->miso_pin >= 0) { - esp32s3_configgpio(config->miso_pin, INPUT_FUNCTION_5 | PULLUP); - esp32s3_gpio_matrix_out(config->miso_pin, SIG_GPIO_OUT_IDX, 0, 0); + esp_configgpio(config->miso_pin, INPUT_FUNCTION_5 | PULLUP); + esp_gpio_matrix_out(config->miso_pin, SIG_GPIO_OUT_IDX, 0, 0); } - esp32s3_configgpio(config->clk_pin, OUTPUT_FUNCTION_5); - esp32s3_gpio_matrix_out(config->clk_pin, SIG_GPIO_OUT_IDX, 0, 0); + esp_configgpio(config->clk_pin, OUTPUT_FUNCTION_5); + esp_gpio_matrix_out(config->clk_pin, SIG_GPIO_OUT_IDX, 0, 0); } else { #if !SPI_HAVE_SWCS if (config->cs_pin >= 0) { - esp32s3_configgpio(config->cs_pin, OUTPUT); - esp32s3_gpio_matrix_out(config->cs_pin, config->cs_outsig, 0, 0); + esp_configgpio(config->cs_pin, OUTPUT); + esp_gpio_matrix_out(config->cs_pin, config->cs_outsig, 0, 0); } #endif if (config->mosi_pin >= 0) { - esp32s3_configgpio(config->mosi_pin, OUTPUT); - esp32s3_gpio_matrix_out(config->mosi_pin, + esp_configgpio(config->mosi_pin, OUTPUT); + esp_gpio_matrix_out(config->mosi_pin, config->mosi_outsig, 0, 0); } if (config->miso_pin >= 0) { - esp32s3_configgpio(config->miso_pin, INPUT | PULLUP); - esp32s3_gpio_matrix_in(config->miso_pin, config->miso_insig, 0); + esp_configgpio(config->miso_pin, INPUT | PULLUP); + esp_gpio_matrix_in(config->miso_pin, config->miso_insig, 0); } - esp32s3_configgpio(config->clk_pin, OUTPUT); - esp32s3_gpio_matrix_out(config->clk_pin, config->clk_outsig, 0, 0); + esp_configgpio(config->clk_pin, OUTPUT); + esp_gpio_matrix_out(config->clk_pin, config->clk_outsig, 0, 0); } modifyreg32(SYSTEM_PERIP_CLK_EN0_REG, 0, config->clk_bit); @@ -1683,8 +1683,7 @@ struct spi_dev_s *esp32s3_spibus_initialize(int port) /* Disable the provided CPU Interrupt to configure it. */ up_disable_irq(priv->config->irq); - esp32s3_teardown_irq(priv->cpu, priv->config->periph, priv->cpuint); - irq_detach(priv->config->irq); + esp_teardown_irq(priv->config->periph, priv->cpuint); priv->cpuint = -ENOMEM; priv->cpu = -ENODEV; @@ -1693,9 +1692,11 @@ struct spi_dev_s *esp32s3_spibus_initialize(int port) /* Set up to receive peripheral interrupts on the current CPU */ priv->cpu = this_cpu(); - priv->cpuint = esp32s3_setup_irq(priv->cpu, priv->config->periph, - ESP32S3_INT_PRIO_DEF, - ESP32S3_CPUINT_LEVEL); + priv->cpuint = esp_setup_irq(priv->config->periph, + ESP32S3_INT_PRIO_DEF, + ESP_IRQ_TRIGGER_LEVEL, + esp32s3_spi_interrupt, + priv); if (priv->cpuint < 0) { /* Failed to allocate a CPU interrupt of this type. */ @@ -1704,19 +1705,6 @@ struct spi_dev_s *esp32s3_spibus_initialize(int port) return NULL; } - /* Attach and enable the IRQ */ - - if (irq_attach(priv->config->irq, esp32s3_spi_interrupt, priv) != OK) - { - /* Failed to attach IRQ, so CPU interrupt must be freed. */ - - esp32s3_teardown_irq(priv->cpu, priv->config->periph, priv->cpuint); - priv->cpuint = -ENOMEM; - nxmutex_unlock(&priv->lock); - - return NULL; - } - /* Enable the CPU interrupt that is linked to the SPI device. */ up_enable_irq(priv->config->irq); @@ -1726,8 +1714,7 @@ struct spi_dev_s *esp32s3_spibus_initialize(int port) { #ifdef CONFIG_ESP32S3_SPI_DMA up_disable_irq(priv->config->irq); - esp32s3_teardown_irq(priv->cpu, priv->config->periph, priv->cpuint); - irq_detach(priv->config->irq); + esp_teardown_irq(priv->config->periph, priv->cpuint); priv->cpuint = -ENOMEM; #endif nxmutex_unlock(&priv->lock); @@ -1774,8 +1761,7 @@ int esp32s3_spibus_uninitialize(struct spi_dev_s *dev) #ifdef CONFIG_ESP32S3_SPI_DMA up_disable_irq(priv->config->irq); - esp32s3_teardown_irq(priv->cpu, priv->config->periph, priv->cpuint); - irq_detach(priv->config->irq); + esp_teardown_irq(priv->config->periph, priv->cpuint); priv->cpuint = -ENOMEM; diff --git a/arch/xtensa/src/esp32s3/esp32s3_spi_slave.c b/arch/xtensa/src/esp32s3/esp32s3_spi_slave.c index 0731025150173..3c03edc005ec8 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_spi_slave.c +++ b/arch/xtensa/src/esp32s3/esp32s3_spi_slave.c @@ -45,8 +45,8 @@ #include #include "esp32s3_spi.h" -#include "esp32s3_irq.h" -#include "esp32s3_gpio.h" +#include "esp_irq.h" +#include "esp_gpio.h" #ifdef CONFIG_ESP32S3_SPI_DMA #include "esp32s3_dma.h" @@ -1085,7 +1085,7 @@ static int spislave_periph_interrupt(int irq, void *context, void *arg) } #endif - if (priv->is_processing && esp32s3_gpioread(priv->config->cs_pin)) + if (priv->is_processing && esp_gpioread(priv->config->cs_pin)) { priv->is_processing = false; SPIS_DEV_SELECT(priv->dev, false); @@ -1196,27 +1196,27 @@ static void spislave_initializ_iomux(struct spislave_priv_s *priv) uint32_t attr = INPUT_FUNCTION_5 | DRIVE_0; const struct spislave_config_s *config = priv->config; - esp32s3_configgpio(config->cs_pin, attr); - esp32s3_configgpio(config->clk_pin, attr); + esp_configgpio(config->cs_pin, attr); + esp_configgpio(config->clk_pin, attr); - esp32s3_gpio_matrix_out(config->cs_pin, SIG_GPIO_OUT_IDX, 0, 0); - esp32s3_gpio_matrix_out(config->clk_pin, SIG_GPIO_OUT_IDX, 0, 0); - esp32s3_gpio_matrix_out(config->mosi_pin, SIG_GPIO_OUT_IDX, 0, 0); - esp32s3_gpio_matrix_out(config->miso_pin, SIG_GPIO_OUT_IDX, 0, 0); + esp_gpio_matrix_out(config->cs_pin, SIG_GPIO_OUT_IDX, 0, 0); + esp_gpio_matrix_out(config->clk_pin, SIG_GPIO_OUT_IDX, 0, 0); + esp_gpio_matrix_out(config->mosi_pin, SIG_GPIO_OUT_IDX, 0, 0); + esp_gpio_matrix_out(config->miso_pin, SIG_GPIO_OUT_IDX, 0, 0); #ifdef CONFIG_ESP32S3_SPI_IO_QIO attr |= OUTPUT; - esp32s3_configgpio(config->mosi_pin, attr); - esp32s3_configgpio(config->miso_pin, attr); - esp32s3_configgpio(config->io2_pin, attr); - esp32s3_configgpio(config->io3_pin, attr); + esp_configgpio(config->mosi_pin, attr); + esp_configgpio(config->miso_pin, attr); + esp_configgpio(config->io2_pin, attr); + esp_configgpio(config->io3_pin, attr); - esp32s3_gpio_matrix_out(config->io2_pin, SIG_GPIO_OUT_IDX, 0, 0); - esp32s3_gpio_matrix_out(config->io3_pin, SIG_GPIO_OUT_IDX, 0, 0); + esp_gpio_matrix_out(config->io2_pin, SIG_GPIO_OUT_IDX, 0, 0); + esp_gpio_matrix_out(config->io3_pin, SIG_GPIO_OUT_IDX, 0, 0); #else - esp32s3_configgpio(config->mosi_pin, attr); - esp32s3_configgpio(config->miso_pin, OUTPUT_FUNCTION_5); + esp_configgpio(config->mosi_pin, attr); + esp_configgpio(config->miso_pin, OUTPUT_FUNCTION_5); #endif } #endif @@ -1241,36 +1241,36 @@ static void spislave_initializ_iomatrix(struct spislave_priv_s *priv) uint32_t attr = INPUT | DRIVE_0; const struct spislave_config_s *config = priv->config; - esp32s3_configgpio(config->cs_pin, attr); - esp32s3_gpio_matrix_in(config->cs_pin, config->cs_insig, 0); + esp_configgpio(config->cs_pin, attr | RISING); + esp_gpio_matrix_in(config->cs_pin, config->cs_insig, 0); - esp32s3_configgpio(config->clk_pin, attr); - esp32s3_gpio_matrix_in(config->clk_pin, config->clk_insig, 0); + esp_configgpio(config->clk_pin, attr); + esp_gpio_matrix_in(config->clk_pin, config->clk_insig, 0); # ifdef CONFIG_ESP32S3_SPI_IO_QIO attr |= OUTPUT; - esp32s3_configgpio(config->mosi_pin, attr); - esp32s3_gpio_matrix_in(config->mosi_pin, config->mosi_insig, 0); - esp32s3_gpio_matrix_out(config->mosi_pin, config->mosi_outsig, 0, 0); + esp_configgpio(config->mosi_pin, attr); + esp_gpio_matrix_in(config->mosi_pin, config->mosi_insig, 0); + esp_gpio_matrix_out(config->mosi_pin, config->mosi_outsig, 0, 0); - esp32s3_configgpio(config->miso_pin, attr); - esp32s3_gpio_matrix_in(config->miso_pin, config->miso_insig, 0); - esp32s3_gpio_matrix_out(config->miso_pin, config->miso_outsig, 0, 0); + esp_configgpio(config->miso_pin, attr); + esp_gpio_matrix_in(config->miso_pin, config->miso_insig, 0); + esp_gpio_matrix_out(config->miso_pin, config->miso_outsig, 0, 0); - esp32s3_configgpio(config->io2_pin, attr); - esp32s3_gpio_matrix_in(config->io2_pin, config->io2_insig, 0); - esp32s3_gpio_matrix_out(config->io2_pin, config->io2_outsig, 0, 0); + esp_configgpio(config->io2_pin, attr); + esp_gpio_matrix_in(config->io2_pin, config->io2_insig, 0); + esp_gpio_matrix_out(config->io2_pin, config->io2_outsig, 0, 0); - esp32s3_configgpio(config->io3_pin, attr); - esp32s3_gpio_matrix_in(config->io3_pin, config->io3_insig, 0); - esp32s3_gpio_matrix_out(config->io3_pin, config->io3_outsig, 0, 0); + esp_configgpio(config->io3_pin, attr); + esp_gpio_matrix_in(config->io3_pin, config->io3_insig, 0); + esp_gpio_matrix_out(config->io3_pin, config->io3_outsig, 0, 0); # else - esp32s3_configgpio(config->mosi_pin, attr); - esp32s3_gpio_matrix_in(config->mosi_pin, config->mosi_insig, 0); + esp_configgpio(config->mosi_pin, attr); + esp_gpio_matrix_in(config->mosi_pin, config->mosi_insig, 0); - esp32s3_configgpio(config->miso_pin, OUTPUT); - esp32s3_gpio_matrix_out(config->miso_pin, config->miso_outsig, 0, 0); + esp_configgpio(config->miso_pin, OUTPUT); + esp_gpio_matrix_out(config->miso_pin, config->miso_outsig, 0, 0); # endif } #endif @@ -1376,7 +1376,7 @@ static int spislave_initialize(struct spi_slave_ctrlr_s *ctrlr) } #endif - esp32s3_gpioirqenable(ESP32S3_PIN2IRQ(config->cs_pin), RISING); + esp_gpioirqenable(config->cs_pin); /* Force a transaction done interrupt. * This interrupt won't fire yet because we initialized the SPI interrupt @@ -1414,7 +1414,7 @@ static void spislave_deinitialize(struct spi_slave_ctrlr_s *ctrlr) { struct spislave_priv_s *priv = (struct spislave_priv_s *)ctrlr; - esp32s3_gpioirqdisable(ESP32S3_PIN2IRQ(priv->config->cs_pin)); + esp_gpioirqdisable(priv->config->cs_pin); /* Disable the trans_done interrupt */ @@ -1555,7 +1555,7 @@ static void spislave_unbind(struct spi_slave_ctrlr_s *ctrlr) up_disable_irq(priv->config->irq); - esp32s3_gpioirqdisable(ESP32S3_PIN2IRQ(priv->config->cs_pin)); + esp_gpioirqdisable(priv->config->cs_pin); /* Disable the trans_done interrupt */ @@ -1785,6 +1785,7 @@ struct spi_slave_ctrlr_s *esp32s3_spislave_ctrlr_initialize(int port) struct spi_slave_ctrlr_s *spislave_dev; struct spislave_priv_s *priv; irqstate_t flags; + int ret; switch (port) { @@ -1815,29 +1816,26 @@ struct spi_slave_ctrlr_s *esp32s3_spislave_ctrlr_initialize(int port) /* Attach IRQ for CS pin interrupt */ - DEBUGVERIFY(irq_attach(ESP32S3_PIN2IRQ(priv->config->cs_pin), - spislave_cs_interrupt, - priv)); - - priv->cpu = this_cpu(); - priv->cpuint = esp32s3_setup_irq(priv->cpu, - priv->config->periph, - ESP32S3_INT_PRIO_DEF, - ESP32S3_CPUINT_LEVEL); - if (priv->cpuint < 0) + ret = esp_gpio_irq(priv->config->cs_pin, + spislave_cs_interrupt, + priv); + if (ret < 0) { - /* Failed to allocate a CPU interrupt of this type. */ - - spin_unlock_irqrestore(&priv->lock, flags); - + spierr("esp_gpio_irq() failed: %d\n", ret); + leave_critical_section(flags); return NULL; } - if (irq_attach(priv->config->irq, spislave_periph_interrupt, priv) != OK) + priv->cpu = this_cpu(); + priv->cpuint = esp_setup_irq(priv->config->periph, + ESP32S3_INT_PRIO_DEF, + ESP_IRQ_TRIGGER_LEVEL, + spislave_periph_interrupt, + priv); + if (priv->cpuint < 0) { - /* Failed to attach IRQ, so CPU interrupt must be freed. */ + /* Failed to allocate a CPU interrupt of this type. */ - esp32s3_teardown_irq(priv->cpu, priv->config->periph, priv->cpuint); spin_unlock_irqrestore(&priv->lock, flags); return NULL; @@ -1885,7 +1883,7 @@ int esp32s3_spislave_ctrlr_uninitialize(struct spi_slave_ctrlr_s *ctrlr) } up_disable_irq(priv->config->irq); - esp32s3_teardown_irq(priv->cpu, priv->config->periph, priv->cpuint); + esp_teardown_irq(priv->config->periph, priv->cpuint); priv->cpuint = -ENOMEM; spislave_deinitialize(ctrlr); diff --git a/arch/xtensa/src/esp32s3/esp32s3_spi_timing.c b/arch/xtensa/src/esp32s3/esp32s3_spi_timing.c index ea544f0e28202..972cf508f5783 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_spi_timing.c +++ b/arch/xtensa/src/esp32s3/esp32s3_spi_timing.c @@ -27,7 +27,7 @@ #include #include "xtensa.h" -#include "esp32s3_gpio.h" +#include "esp_gpio.h" #include "esp32s3_psram.h" #include "esp32s3_spi_timing.h" #include "hardware/esp32s3_iomux.h" diff --git a/arch/xtensa/src/esp32s3/esp32s3_spiflash.c b/arch/xtensa/src/esp32s3/esp32s3_spiflash.c index ee6498a1e92cb..e89b659bdf643 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_spiflash.c +++ b/arch/xtensa/src/esp32s3/esp32s3_spiflash.c @@ -43,10 +43,10 @@ #include "xtensa.h" #include "esp_attr.h" -#include "hardware/esp32s3_efuse.h" +#include "soc/efuse_reg.h" #include "hardware/esp32s3_cache_memory.h" #include "rom/esp32s3_spiflash.h" -#include "esp32s3_irq.h" +#include "esp_irq.h" #include "esp32s3_spiflash.h" #include "spi_flash_defs.h" @@ -384,7 +384,7 @@ void spiflash_start(void) nxsched_set_priority(tcb, saved_priority); - esp32s3_irq_noniram_disable(); + esp_intr_noniram_disable(); spiflash_suspend_cache(); } @@ -418,7 +418,7 @@ void spiflash_end(void) g_flash_op_complete = true; - esp32s3_irq_noniram_enable(); + esp_intr_noniram_enable(); sched_unlock(); @@ -948,7 +948,7 @@ static int spi_flash_op_block_task(int argc, char *argv[]) sched_lock(); - esp32s3_irq_noniram_disable(); + esp_intr_noniram_disable(); /* g_flash_op_complete flag is cleared on *this* CPU, otherwise the * other CPU may reset the flag back to false before this task has a @@ -971,7 +971,7 @@ static int spi_flash_op_block_task(int argc, char *argv[]) /* Restore interrupts that aren't located in IRAM */ - esp32s3_irq_noniram_enable(); + esp_intr_noniram_enable(); sched_unlock(); } diff --git a/arch/xtensa/src/esp32s3/esp32s3_start.c b/arch/xtensa/src/esp32s3/esp32s3_start.c index eccd7dc2711d0..ecf6d42bdceca 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_start.c +++ b/arch/xtensa/src/esp32s3/esp32s3_start.c @@ -35,10 +35,17 @@ #include "esp32s3_start.h" #include "esp32s3_lowputc.h" -#include "esp32s3_clockconfig.h" +#include "esp_clk.h" #include "esp32s3_region.h" -#include "esp32s3_rtc.h" #include "esp32s3_spiram.h" + +#include "esp_clk_internal.h" + +/* Undefine macros that conflict with HAL definitions */ + +#undef RTC_FAST_CLK_FREQ_8M + +#include "soc/rtc.h" #include "esp32s3_wdt.h" #include "esp32s3_dma.h" #ifdef CONFIG_BUILD_PROTECTED @@ -71,6 +78,7 @@ #include "esp_clk_internal.h" #include "periph_ctrl.h" +#include "rom/ets_sys.h" #include "esp_private/startup_internal.h" @@ -175,7 +183,11 @@ extern uintptr_t _ext_ram_bss_start; extern uintptr_t _ext_ram_bss_end; #endif -/* Address of the CPU0 IDLE thread */ +/* Address of the IDLE thread stacks. + * In SMP mode, we only use g_idlestack[0] for CPU0's IDLE stack. + * CPU1+ IDLE stacks are allocated dynamically by up_cpu_idlestack(). + * The array is sized for 1 CPU to minimize BSS usage. + */ uint32_t g_idlestack[IDLETHREAD_STACKWORDS] aligned_data(16) locate_data(".noinit"); @@ -347,14 +359,9 @@ noinstrument_function void noreturn_function IRAM_ATTR __esp32s3_start(void) esp_flash_app_init(); - /* Initialize RTC controller parameters */ + /* Initialize RTC controller and set CPU frequency */ - esp32s3_rtc_init(); - esp32s3_rtc_clk_set(); - - /* Set CPU frequency configured in board.h */ - - esp32s3_clockconfig(); + esp_clk_init(); /* Initialize peripherals parameters */ @@ -374,14 +381,6 @@ noinstrument_function void noreturn_function IRAM_ATTR __esp32s3_start(void) showprogress('A'); - /* The PLL provided by bootloader is not stable enough, do calibration - * again here so that we can use better clock for the timing tuning. - */ - -#ifdef CONFIG_ESP32S3_SYSTEM_BBPLL_RECALIB - esp32s3_rtc_recalib_bbpll(); -#endif - esp32s3_spi_timing_set_mspi_flash_tuning(); #if defined(CONFIG_ESP32S3_SPIRAM_BOOT_INIT) if (esp_spiram_init() != OK) @@ -442,8 +441,6 @@ noinstrument_function void noreturn_function IRAM_ATTR __esp32s3_start(void) showprogress('C'); #endif - SYS_STARTUP_FN(); - /* Bring up NuttX */ nx_start(); @@ -454,6 +451,48 @@ noinstrument_function void noreturn_function IRAM_ATTR __esp32s3_start(void) * Public Functions ****************************************************************************/ +/**************************************************************************** + * Name: xtensa_soc_initialize + * + * Description: + * Initialize SoC-specific initialization. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void weak_function xtensa_soc_initialize(void) +{ + sys_startup_fn(); +} + +/**************************************************************************** + * Name: sys_startup_fn + * + * Description: + * Execute the system layer startup function for the current CPU core. + * This function calls the appropriate startup function from the per-CPU + * startup function array (g_startup_fn) based on the current core ID. + * The SYS_STARTUP_FN() macro retrieves the core ID, indexes into the + * g_startup_fn array, and invokes the corresponding startup function. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void sys_startup_fn(void) +{ + SYS_STARTUP_FN(); +} + /**************************************************************************** * Name: __start * diff --git a/arch/xtensa/src/esp32s3/esp32s3_start.h b/arch/xtensa/src/esp32s3/esp32s3_start.h index 306da940b26d4..7f22c97e4cfdc 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_start.h +++ b/arch/xtensa/src/esp32s3/esp32s3_start.h @@ -33,6 +33,26 @@ * Pre-processor Definitions ****************************************************************************/ +/**************************************************************************** + * Name: sys_startup_fn + * + * Description: + * Execute the system layer startup function for the current CPU core. + * This function calls the appropriate startup function from the per-CPU + * startup function array (g_startup_fn) based on the current core ID. + * The SYS_STARTUP_FN() macro retrieves the core ID, indexes into the + * g_startup_fn array, and invokes the corresponding startup function. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void sys_startup_fn(void); + /**************************************************************************** * Name: esp32s3_board_initialize * diff --git a/arch/xtensa/src/esp32s3/esp32s3_systemreset.c b/arch/xtensa/src/esp32s3/esp32s3_systemreset.c index a1f349331f2f3..fbbd0e2bace49 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_systemreset.c +++ b/arch/xtensa/src/esp32s3/esp32s3_systemreset.c @@ -30,7 +30,7 @@ #include #include "xtensa.h" -#include "hardware/esp32s3_rtccntl.h" +#include "soc/rtc_cntl_reg.h" #include "esp32s3_systemreset.h" /**************************************************************************** @@ -142,7 +142,7 @@ void up_shutdown_handler(void) void up_systemreset(void) { - putreg32(RTC_CNTL_SW_SYS_RST, RTC_CNTL_RTC_OPTIONS0_REG); + putreg32(RTC_CNTL_SW_SYS_RST, RTC_CNTL_OPTIONS0_REG); /* Wait for the reset */ diff --git a/arch/xtensa/src/esp32s3/esp32s3_tickless.c b/arch/xtensa/src/esp32s3/esp32s3_tickless.c index e8357b5eb95db..aaff1ddeedcaf 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_tickless.c +++ b/arch/xtensa/src/esp32s3/esp32s3_tickless.c @@ -60,7 +60,7 @@ #include "xtensa.h" #include "chip.h" -#include "esp32s3_irq.h" +#include "esp_irq.h" #include "hardware/esp32s3_systimer.h" #include "hardware/esp32s3_system.h" #include "hardware/esp32s3_soc.h" @@ -472,15 +472,11 @@ void up_timer_initialize(void) g_timer_started = false; - cpuint = esp32s3_setup_irq(0, ESP32S3_PERIPH_SYSTIMER_TARGET0, 1, - ESP32S3_CPUINT_LEVEL); + cpuint = esp_setup_irq(ESP32S3_PERIPH_SYSTIMER_TARGET0, 1, + ESP_IRQ_TRIGGER_LEVEL, tickless_isr, NULL); DEBUGASSERT(cpuint >= 0); - /* Attach the timer interrupt. */ - - irq_attach(ESP32S3_IRQ_SYSTIMER_TARGET0, tickless_isr, NULL); - /* Enable the allocated CPU interrupt. */ up_enable_irq(ESP32S3_IRQ_SYSTIMER_TARGET0); diff --git a/arch/xtensa/src/esp32s3/esp32s3_tim.c b/arch/xtensa/src/esp32s3/esp32s3_tim.c index 95d5fdf878d77..8c3904e30cefd 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_tim.c +++ b/arch/xtensa/src/esp32s3/esp32s3_tim.c @@ -34,8 +34,8 @@ #include "hardware/esp32s3_tim.h" #include "esp32s3_tim.h" -#include "esp32s3_irq.h" -#include "esp32s3_gpio.h" +#include "esp_irq.h" +#include "esp_gpio.h" #include "soc/periph_defs.h" #include "esp_private/periph_ctrl.h" @@ -731,8 +731,7 @@ static int tim_setisr(struct esp32s3_tim_dev_s *dev, xcpt_t handler, */ up_disable_irq(priv->irq); - esp32s3_teardown_irq(priv->core, priv->periph, priv->cpuint); - irq_detach(priv->irq); + esp_teardown_irq(priv->periph, priv->cpuint); priv->cpuint = -ENOMEM; priv->core = -ENODEV; @@ -753,8 +752,10 @@ static int tim_setisr(struct esp32s3_tim_dev_s *dev, xcpt_t handler, /* Set up to receive peripheral interrupts on the current CPU */ priv->core = this_cpu(); - priv->cpuint = esp32s3_setup_irq(priv->core, priv->periph, - priv->priority, ESP32S3_CPUINT_LEVEL); + priv->cpuint = esp_setup_irq(priv->periph, + priv->priority, + ESP_IRQ_TRIGGER_LEVEL, + handler, arg); if (priv->cpuint < 0) { tmrerr("ERROR: No CPU Interrupt available"); @@ -762,16 +763,6 @@ static int tim_setisr(struct esp32s3_tim_dev_s *dev, xcpt_t handler, goto errout; } - /* Associate an IRQ Number (from the timer) to an ISR */ - - ret = irq_attach(priv->irq, handler, arg); - if (ret != OK) - { - esp32s3_teardown_irq(priv->core, priv->periph, priv->cpuint); - tmrerr("ERROR: Failed to associate an IRQ Number"); - goto errout; - } - /* Enable the CPU Interrupt that is linked to the timer */ up_enable_irq(priv->irq); diff --git a/arch/xtensa/src/esp32s3/esp32s3_tim_lowerhalf.c b/arch/xtensa/src/esp32s3/esp32s3_tim_lowerhalf.c index 6fa6f2beab4bf..97d9117ed5268 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_tim_lowerhalf.c +++ b/arch/xtensa/src/esp32s3/esp32s3_tim_lowerhalf.c @@ -41,7 +41,7 @@ #include "esp32s3_tim.h" #include "esp32s3_tim_lowerhalf.h" -#include "esp32s3_clockconfig.h" +#include "esp_clk.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/xtensa/src/esp32s3/esp32s3_timerisr.c b/arch/xtensa/src/esp32s3/esp32s3_timerisr.c index 960c61402809e..e478fe12886d1 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_timerisr.c +++ b/arch/xtensa/src/esp32s3/esp32s3_timerisr.c @@ -33,9 +33,10 @@ #include #include "chip.h" -#include "esp32s3_irq.h" +#include "esp_irq.h" #include "hardware/esp32s3_system.h" #include "hardware/esp32s3_systimer.h" +#include "periph_ctrl.h" #include "xtensa.h" /**************************************************************************** @@ -101,22 +102,28 @@ void up_timer_initialize(void) uint32_t regval; int cpuint; - cpuint = esp32s3_setup_irq(0, ESP32S3_PERIPH_SYSTIMER_TARGET0, 1, - ESP32S3_CPUINT_LEVEL); + cpuint = esp_setup_irq(ETS_SYSTIMER_TARGET0_INTR_SOURCE, + ESP_IRQ_PRIORITY_1, + ESP_IRQ_TRIGGER_LEVEL, + systimer_isr, + NULL); DEBUGASSERT(cpuint >= 0); - /* Attach the timer interrupt. */ - - irq_attach(ESP32S3_IRQ_SYSTIMER_TARGET0, systimer_isr, NULL); - /* Enable the allocated CPU interrupt. */ - up_enable_irq(ESP32S3_IRQ_SYSTIMER_TARGET0); + up_enable_irq(ESP_SOURCE2IRQ(ETS_SYSTIMER_TARGET0_INTR_SOURCE)); + + /* Acquire SYSTIMER peripheral and enable clock/reset only if first user */ - /* Enable timer clock */ + PERIPH_RCC_ACQUIRE_ATOMIC(PERIPH_SYSTIMER_MODULE, ref_count) + { + if (ref_count == 0) + { + modifyreg32(SYSTEM_PERIP_CLK_EN0_REG, 0, SYSTEM_SYSTIMER_CLK_EN); + modifyreg32(SYSTEM_PERIP_RST_EN0_REG, SYSTEM_SYSTIMER_RST, 0); + } + } - modifyreg32(SYSTEM_PERIP_CLK_EN0_REG, 0, SYSTEM_SYSTIMER_CLK_EN); - modifyreg32(SYSTEM_PERIP_RST_EN0_REG, SYSTEM_SYSTIMER_RST, 0); modifyreg32(SYSTIMER_CONF_REG, 0, SYSTIMER_CLK_EN); /* Configure alarm 0 (Comparator 0) */ diff --git a/arch/xtensa/src/esp32s3/esp32s3_touch.c b/arch/xtensa/src/esp32s3/esp32s3_touch.c index c5bd070155b3b..11d3d5af0408f 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_touch.c +++ b/arch/xtensa/src/esp32s3/esp32s3_touch.c @@ -37,8 +37,9 @@ #include "xtensa.h" -#include "esp32s3_gpio.h" -#include "esp32s3_irq.h" +#include "esp_gpio.h" +#include "esp_irq.h" +#include "espressif/esp_hr_timer.h" #include "esp32s3_touch.h" #include "esp32s3_touch_lowerhalf.h" @@ -65,6 +66,14 @@ struct touch_config_meas_mode_s enum touch_tie_opt_e tie_opt; }; +#ifdef CONFIG_ESP32S3_TOUCH_IRQ +struct touchirq_handler_s +{ + xcpt_t handler; + void *arg; +}; +#endif + /**************************************************************************** * Private Function Prototypes ****************************************************************************/ @@ -92,9 +101,11 @@ static uint32_t touch_pad_logic_threshold[TOUCH_SENSOR_PINS]; static uint16_t touch_pad_isr_enabled = 0x0000; static enum touch_intr_mask_e touch_pad_isr_types = 0x0000; static int touch_last_irq = -1; +static struct touchirq_handler_s + g_touchirq_handlers[ESP32S3_NIRQ_RTCIO_TOUCHPAD]; static int (*touch_release_cb)(int, void *, void *) = NULL; -static struct rt_timer_args_s irq_timer_args; -static struct rt_timer_s *irq_timer_handler = NULL; +static struct esp_hr_timer_args_s irq_timer_args; +static struct esp_hr_timer_s *irq_timer_handler = NULL; #endif /**************************************************************************** @@ -128,9 +139,9 @@ static int touch_interrupt(int irq, void *context, void *arg) touch_lh_intr_disable(touch_pad_isr_types); - rt_timer_start(irq_timer_handler, - CONFIG_ESP32S3_TOUCH_IRQ_INTERVAL_MS * USEC_PER_MSEC, - false); + esp_hr_timer_start_once(irq_timer_handler, + CONFIG_ESP32S3_TOUCH_IRQ_INTERVAL_MS * \ + USEC_PER_MSEC); /* Read and clear the touch interrupt status */ @@ -144,7 +155,14 @@ static int touch_interrupt(int irq, void *context, void *arg) { if ((touch_pad_isr_enabled >> pad_num) & 0x1) { - irq_dispatch(touch_last_irq, context); + if (pad_num >= 0 && pad_num < ESP32S3_NIRQ_RTCIO_TOUCHPAD && + g_touchirq_handlers[pad_num].handler != NULL) + { + g_touchirq_handlers[pad_num].handler( + touch_last_irq, + context, + g_touchirq_handlers[pad_num].arg); + } } } @@ -170,13 +188,25 @@ static int touch_interrupt(int irq, void *context, void *arg) #ifdef CONFIG_ESP32S3_TOUCH_IRQ static void touch_restore_irq(void *arg) { - if (touch_last_irq > 0 && touch_release_cb != NULL) + if (touch_last_irq >= ESP32S3_FIRST_RTCIOIRQ_TOUCHPAD && + touch_last_irq <= ESP32S3_LAST_RTCIOIRQ_TOUCHPAD) { - /* Call the button interrupt handler again so we can detect touch pad - * releases - */ + int bit = ESP32S3_IRQ2TOUCHPAD(touch_last_irq); - touch_release_cb(touch_last_irq, NULL, NULL); + if (bit >= 0 && bit < ESP32S3_NIRQ_RTCIO_TOUCHPAD && + g_touchirq_handlers[bit].handler != NULL) + { + /* Call the button interrupt handler again so we can detect touch + * pad releases. + */ + + g_touchirq_handlers[bit].handler(touch_last_irq, NULL, + g_touchirq_handlers[bit].arg); + } + else if (touch_release_cb != NULL) + { + touch_release_cb(touch_last_irq, NULL, NULL); + } } touch_lh_intr_enable(touch_pad_isr_types); @@ -265,7 +295,13 @@ static void touch_init(struct touch_config_s *config) #ifdef CONFIG_ESP32S3_TOUCH_IRQ irq_timer_args.arg = NULL; irq_timer_args.callback = touch_restore_irq; - rt_timer_create(&(irq_timer_args), &(irq_timer_handler)); + irq_timer_args.name = "touch_irq"; + irq_timer_args.skip_unhandled_events = false; + + if (esp_hr_timer_create(&irq_timer_args, &irq_timer_handler) != OK) + { + ierr("ERROR: esp_hr_timer_create(irq) failed\n"); + } touch_pad_isr_types = TOUCH_INTR_MASK_ACTIVE | TOUCH_INTR_MASK_INACTIVE | @@ -638,6 +674,84 @@ void esp32s3_touchirqdisable(int irq) } #endif +/**************************************************************************** + * Name: esp32s3_touchirqattach + * + * Description: + * Attach an interrupt handler to a specified touch pad IRQ. + * + * Input Parameters: + * irq - Touch pad IRQ number to attach the handler to + * handler - Interrupt handler function + * arg - Argument to pass to the handler + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32S3_TOUCH_IRQ +int esp32s3_touchirqattach(int irq, xcpt_t handler, void *arg) +{ + int bit; + + DEBUGASSERT(irq >= ESP32S3_FIRST_RTCIOIRQ_TOUCHPAD && + irq <= ESP32S3_LAST_RTCIOIRQ_TOUCHPAD); + + bit = ESP32S3_IRQ2TOUCHPAD(irq); + if (bit < 0 || bit >= ESP32S3_NIRQ_RTCIO_TOUCHPAD) + { + return -EINVAL; + } + + g_touchirq_handlers[bit].handler = handler; + g_touchirq_handlers[bit].arg = arg; + + return OK; +} + +/**************************************************************************** + * Name: esp32s3_touchirqdetach + * + * Description: + * Detach the interrupt handler for the specified touch pad IRQ and + * disable the interrupt. + * + * Input Parameters: + * irq - Touch pad IRQ number to detach. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +int esp32s3_touchirqdetach(int irq) +{ + int bit; + + DEBUGASSERT(irq >= ESP32S3_FIRST_RTCIOIRQ_TOUCHPAD && + irq <= ESP32S3_LAST_RTCIOIRQ_TOUCHPAD); + + bit = ESP32S3_IRQ2TOUCHPAD(irq); + if (bit < 0 || bit >= ESP32S3_NIRQ_RTCIO_TOUCHPAD) + { + return -EINVAL; + } + + touch_lh_intr_disable(touch_pad_isr_types); + + g_touchirq_handlers[bit].handler = NULL; + g_touchirq_handlers[bit].arg = NULL; + touch_pad_isr_enabled &= (~(UINT32_C(1) << bit)); + + touch_lh_intr_enable(touch_pad_isr_types); + + return OK; +} +#endif + /**************************************************************************** * Name: esp32s3_touchregisterreleasecb * @@ -652,9 +766,11 @@ void esp32s3_touchirqdisable(int irq) * ****************************************************************************/ +#ifdef CONFIG_ESP32S3_TOUCH_IRQ void esp32s3_touchregisterreleasecb(int (*func)(int, void *, void *)) { DEBUGASSERT(func != NULL); touch_release_cb = func; } +#endif diff --git a/arch/xtensa/src/esp32s3/esp32s3_touch.h b/arch/xtensa/src/esp32s3/esp32s3_touch.h index e801a2e138e3d..c5d6710d4cfa9 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_touch.h +++ b/arch/xtensa/src/esp32s3/esp32s3_touch.h @@ -26,6 +26,7 @@ ****************************************************************************/ #include +#include #include #include @@ -243,6 +244,51 @@ void esp32s3_touchirqdisable(int irq); # define esp32s3_touchirqdisable(irq) #endif +/**************************************************************************** + * Name: esp32s3_touchirqattach + * + * Description: + * Attach an interrupt handler to a specified touch pad IRQ. + * + * Input Parameters: + * irq - Touch pad IRQ number to attach the handler to + * handler - Interrupt handler function + * arg - Argument to pass to the handler + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32S3_TOUCH_IRQ +int esp32s3_touchirqattach(int irq, xcpt_t handler, void *arg); +#else +# define esp32s3_touchirqattach(irq, handler, arg) (-EINVAL) +#endif + +/**************************************************************************** + * Name: esp32s3_touchirqdetach + * + * Description: + * Detach the interrupt handler for the specified touch pad IRQ and + * disable the interrupt. + * + * Input Parameters: + * irq - Touch pad IRQ number to detach. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * to indicate the nature of any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_ESP32S3_TOUCH_IRQ +int esp32s3_touchirqdetach(int irq); +#else +# define esp32s3_touchirqdetach(irq) (-EINVAL) +#endif + /**************************************************************************** * Name: esp32s3_touchregisterreleasecb * diff --git a/arch/xtensa/src/esp32s3/esp32s3_touch_lowerhalf.h b/arch/xtensa/src/esp32s3/esp32s3_touch_lowerhalf.h index fe8bca8f23eb2..2465abe86f7ac 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_touch_lowerhalf.h +++ b/arch/xtensa/src/esp32s3/esp32s3_touch_lowerhalf.h @@ -33,11 +33,11 @@ #include "xtensa.h" #include "hardware/esp32s3_rtc_io.h" -#include "hardware/esp32s3_rtccntl.h" +#include "soc/rtc_cntl_reg.h" #include "hardware/esp32s3_touch.h" #include "hardware/esp32s3_sens.h" -#include "esp32s3_rt_timer.h" +#include "espressif/esp_hr_timer.h" #include "esp32s3_rtc_gpio.h" /**************************************************************************** @@ -145,13 +145,13 @@ static inline void touch_lh_set_meas_time(uint16_t meas_time) { /* Touch sensor measure time = meas_cycle / 8Mhz */ - REG_SET_FIELD(RTC_CNTL_RTC_TOUCH_CTRL1_REG, + REG_SET_FIELD(RTC_CNTL_TOUCH_CTRL1_REG, RTC_CNTL_TOUCH_MEAS_NUM, meas_time); /* The waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD */ - REG_SET_FIELD(RTC_CNTL_RTC_TOUCH_CTRL2_REG, + REG_SET_FIELD(RTC_CNTL_TOUCH_CTRL2_REG, RTC_CNTL_TOUCH_XPD_WAIT, TOUCH_MEASURE_WAIT_MAX); } @@ -172,7 +172,7 @@ static inline void touch_lh_set_meas_time(uint16_t meas_time) static inline uint16_t touch_lh_get_meas_time(void) { - return REG_GET_FIELD(RTC_CNTL_RTC_TOUCH_CTRL1_REG, + return REG_GET_FIELD(RTC_CNTL_TOUCH_CTRL1_REG, RTC_CNTL_TOUCH_MEAS_NUM); } @@ -194,7 +194,7 @@ static inline void touch_lh_set_sleep_time(uint16_t sleep_time) { /* Touch sensor sleep cycle Time = sleep_cycle / RTC_SLOW_CLK (150k) */ - REG_SET_FIELD(RTC_CNTL_RTC_TOUCH_CTRL1_REG, + REG_SET_FIELD(RTC_CNTL_TOUCH_CTRL1_REG, RTC_CNTL_TOUCH_SLEEP_CYCLES, sleep_time); } @@ -215,7 +215,7 @@ static inline void touch_lh_set_sleep_time(uint16_t sleep_time) static inline uint16_t touch_lh_get_sleep_time(void) { - return REG_GET_FIELD(RTC_CNTL_RTC_TOUCH_CTRL1_REG, + return REG_GET_FIELD(RTC_CNTL_TOUCH_CTRL1_REG, RTC_CNTL_TOUCH_SLEEP_CYCLES); } @@ -235,7 +235,7 @@ static inline uint16_t touch_lh_get_sleep_time(void) static inline void touch_lh_set_voltage_high(enum touch_high_volt_e refh) { - REG_SET_FIELD(RTC_CNTL_RTC_TOUCH_CTRL2_REG, RTC_CNTL_TOUCH_DREFH, refh); + REG_SET_FIELD(RTC_CNTL_TOUCH_CTRL2_REG, RTC_CNTL_TOUCH_DREFH, refh); } /**************************************************************************** @@ -255,7 +255,7 @@ static inline void touch_lh_set_voltage_high(enum touch_high_volt_e refh) static inline enum touch_high_volt_e touch_lh_get_voltage_high(void) { return (enum touch_high_volt_e) - REG_GET_FIELD(RTC_CNTL_RTC_TOUCH_CTRL2_REG, RTC_CNTL_TOUCH_DREFH); + REG_GET_FIELD(RTC_CNTL_TOUCH_CTRL2_REG, RTC_CNTL_TOUCH_DREFH); } /**************************************************************************** @@ -274,7 +274,7 @@ static inline enum touch_high_volt_e touch_lh_get_voltage_high(void) static inline void touch_lh_set_voltage_low(enum touch_low_volt_e refl) { - REG_SET_FIELD(RTC_CNTL_RTC_TOUCH_CTRL2_REG, RTC_CNTL_TOUCH_DREFL, refl); + REG_SET_FIELD(RTC_CNTL_TOUCH_CTRL2_REG, RTC_CNTL_TOUCH_DREFL, refl); } /**************************************************************************** @@ -294,7 +294,7 @@ static inline void touch_lh_set_voltage_low(enum touch_low_volt_e refl) static inline enum touch_low_volt_e touch_lh_get_voltage_low(void) { return (enum touch_low_volt_e) - REG_GET_FIELD(RTC_CNTL_RTC_TOUCH_CTRL2_REG, RTC_CNTL_TOUCH_DREFL); + REG_GET_FIELD(RTC_CNTL_TOUCH_CTRL2_REG, RTC_CNTL_TOUCH_DREFL); } /**************************************************************************** @@ -314,7 +314,7 @@ static inline enum touch_low_volt_e touch_lh_get_voltage_low(void) static inline void touch_lh_set_voltage_attenuation(enum touch_volt_atten_e atten) { - REG_SET_FIELD(RTC_CNTL_RTC_TOUCH_CTRL2_REG, RTC_CNTL_TOUCH_DRANGE, atten); + REG_SET_FIELD(RTC_CNTL_TOUCH_CTRL2_REG, RTC_CNTL_TOUCH_DRANGE, atten); } /**************************************************************************** @@ -334,7 +334,7 @@ static inline void static inline enum touch_volt_atten_e touch_lh_get_voltage_attenuation(void) { return (enum touch_volt_atten_e) - REG_GET_FIELD(RTC_CNTL_RTC_TOUCH_CTRL2_REG, RTC_CNTL_TOUCH_DRANGE); + REG_GET_FIELD(RTC_CNTL_TOUCH_CTRL2_REG, RTC_CNTL_TOUCH_DRANGE); } /**************************************************************************** @@ -473,7 +473,7 @@ static inline enum touch_tie_opt_e static inline void touch_lh_set_fsm_mode(enum touch_fsm_mode_e mode) { - REG_SET_FIELD(RTC_CNTL_RTC_TOUCH_CTRL2_REG, + REG_SET_FIELD(RTC_CNTL_TOUCH_CTRL2_REG, RTC_CNTL_TOUCH_START_FORCE, mode); } @@ -495,7 +495,7 @@ static inline void touch_lh_set_fsm_mode(enum touch_fsm_mode_e mode) static inline enum touch_fsm_mode_e touch_lh_get_fsm_mode(void) { return (enum touch_fsm_mode_e) - REG_GET_FIELD(RTC_CNTL_RTC_TOUCH_CTRL2_REG, RTC_CNTL_TOUCH_START_FORCE); + REG_GET_FIELD(RTC_CNTL_TOUCH_CTRL2_REG, RTC_CNTL_TOUCH_START_FORCE); } /**************************************************************************** @@ -514,7 +514,7 @@ static inline enum touch_fsm_mode_e touch_lh_get_fsm_mode(void) static inline void touch_lh_clkgate(bool enable) { - REG_SET_FIELD(RTC_CNTL_RTC_TOUCH_CTRL2_REG, + REG_SET_FIELD(RTC_CNTL_TOUCH_CTRL2_REG, RTC_CNTL_TOUCH_CLKGATE_EN, enable); } @@ -535,7 +535,7 @@ static inline void touch_lh_clkgate(bool enable) static inline bool touch_lh_clkgate_get_state(void) { - return (bool) REG_GET_FIELD(RTC_CNTL_RTC_TOUCH_CTRL2_REG, + return (bool) REG_GET_FIELD(RTC_CNTL_TOUCH_CTRL2_REG, RTC_CNTL_TOUCH_CLKGATE_EN); } @@ -557,11 +557,11 @@ static inline bool touch_lh_clkgate_get_state(void) static inline void touch_lh_timer_force_done(void) { - REG_SET_FIELD(RTC_CNTL_RTC_TOUCH_CTRL2_REG, + REG_SET_FIELD(RTC_CNTL_TOUCH_CTRL2_REG, RTC_CNTL_TOUCH_TIMER_FORCE_DONE, TOUCH_LH_TIMER_FORCE_DONE); - REG_SET_FIELD(RTC_CNTL_RTC_TOUCH_CTRL2_REG, + REG_SET_FIELD(RTC_CNTL_TOUCH_CTRL2_REG, RTC_CNTL_TOUCH_TIMER_FORCE_DONE, TOUCH_LH_TIMER_DONE); } @@ -582,17 +582,17 @@ static inline void touch_lh_timer_force_done(void) static inline void touch_lh_start_fsm(void) { - REG_SET_FIELD(RTC_CNTL_RTC_TOUCH_CTRL2_REG, + REG_SET_FIELD(RTC_CNTL_TOUCH_CTRL2_REG, RTC_CNTL_TOUCH_TIMER_FORCE_DONE, TOUCH_LH_TIMER_FORCE_DONE); - REG_SET_FIELD(RTC_CNTL_RTC_TOUCH_CTRL2_REG, + REG_SET_FIELD(RTC_CNTL_TOUCH_CTRL2_REG, RTC_CNTL_TOUCH_TIMER_FORCE_DONE, TOUCH_LH_TIMER_DONE); bool reg_val = (touch_lh_get_fsm_mode() == TOUCH_FSM_MODE_TIMER) ? 1 : 0; - REG_SET_FIELD(RTC_CNTL_RTC_TOUCH_CTRL2_REG, + REG_SET_FIELD(RTC_CNTL_TOUCH_CTRL2_REG, RTC_CNTL_TOUCH_SLP_TIMER_EN, reg_val); } @@ -613,19 +613,19 @@ static inline void touch_lh_start_fsm(void) static inline void touch_lh_stop_fsm(void) { - REG_SET_FIELD(RTC_CNTL_RTC_TOUCH_CTRL2_REG, + REG_SET_FIELD(RTC_CNTL_TOUCH_CTRL2_REG, RTC_CNTL_TOUCH_START_EN, false); - REG_SET_FIELD(RTC_CNTL_RTC_TOUCH_CTRL2_REG, + REG_SET_FIELD(RTC_CNTL_TOUCH_CTRL2_REG, RTC_CNTL_TOUCH_SLP_TIMER_EN, false); - REG_SET_FIELD(RTC_CNTL_RTC_TOUCH_CTRL2_REG, + REG_SET_FIELD(RTC_CNTL_TOUCH_CTRL2_REG, RTC_CNTL_TOUCH_TIMER_FORCE_DONE, TOUCH_LH_TIMER_FORCE_DONE); - REG_SET_FIELD(RTC_CNTL_RTC_TOUCH_CTRL2_REG, + REG_SET_FIELD(RTC_CNTL_TOUCH_CTRL2_REG, RTC_CNTL_TOUCH_TIMER_FORCE_DONE, TOUCH_LH_TIMER_DONE); } @@ -646,7 +646,7 @@ static inline void touch_lh_stop_fsm(void) static inline bool touch_lh_get_fsm_state(void) { - return (bool) REG_GET_FIELD(RTC_CNTL_RTC_TOUCH_CTRL2_REG, + return (bool) REG_GET_FIELD(RTC_CNTL_TOUCH_CTRL2_REG, RTC_CNTL_TOUCH_SLP_TIMER_EN); } @@ -666,11 +666,11 @@ static inline bool touch_lh_get_fsm_state(void) static inline void touch_lh_start_sw_meas(void) { - REG_SET_FIELD(RTC_CNTL_RTC_TOUCH_CTRL2_REG, + REG_SET_FIELD(RTC_CNTL_TOUCH_CTRL2_REG, RTC_CNTL_TOUCH_START_EN, false); - REG_SET_FIELD(RTC_CNTL_RTC_TOUCH_CTRL2_REG, + REG_SET_FIELD(RTC_CNTL_TOUCH_CTRL2_REG, RTC_CNTL_TOUCH_START_EN, true); } @@ -748,7 +748,7 @@ static inline uint16_t touch_lh_get_threshold(enum touch_pad_e tp) static inline void touch_lh_set_channel_mask(uint16_t enable_mask) { - setbits(RTC_CNTL_RTC_TOUCH_SCAN_CTRL_REG, + setbits(RTC_CNTL_TOUCH_SCAN_CTRL_REG, (enable_mask & ((1 << TOUCH_SENSOR_PINS) - 1)) << RTC_CNTL_TOUCH_SCAN_PAD_MAP_S); @@ -773,7 +773,7 @@ static inline void touch_lh_set_channel_mask(uint16_t enable_mask) static inline uint16_t touch_lh_get_channel_mask(void) { - return (REG_GET_FIELD(RTC_CNTL_RTC_TOUCH_SCAN_CTRL_REG, + return (REG_GET_FIELD(RTC_CNTL_TOUCH_SCAN_CTRL_REG, RTC_CNTL_TOUCH_SCAN_PAD_MAP) & REG_GET_FIELD(SENS_SAR_TOUCH_CONF_REG, SENS_TOUCH_OUTEN)); @@ -795,7 +795,7 @@ static inline uint16_t touch_lh_get_channel_mask(void) static inline void touch_lh_clear_channel_mask(uint16_t disable_mask) { - resetbits(RTC_CNTL_RTC_TOUCH_SCAN_CTRL_REG, + resetbits(RTC_CNTL_TOUCH_SCAN_CTRL_REG, (disable_mask & ((1 << TOUCH_SENSOR_PINS) - 1)) << RTC_CNTL_TOUCH_SCAN_PAD_MAP_S); @@ -906,15 +906,15 @@ static inline bool touch_lh_meas_is_done(void) static inline void touch_lh_reset(void) { - REG_SET_FIELD(RTC_CNTL_RTC_TOUCH_CTRL2_REG, + REG_SET_FIELD(RTC_CNTL_TOUCH_CTRL2_REG, RTC_CNTL_TOUCH_RESET, false); - REG_SET_FIELD(RTC_CNTL_RTC_TOUCH_CTRL2_REG, + REG_SET_FIELD(RTC_CNTL_TOUCH_CTRL2_REG, RTC_CNTL_TOUCH_RESET, true); - REG_SET_FIELD(RTC_CNTL_RTC_TOUCH_CTRL2_REG, + REG_SET_FIELD(RTC_CNTL_TOUCH_CTRL2_REG, RTC_CNTL_TOUCH_RESET, false); } @@ -945,7 +945,7 @@ static inline void touch_lh_reset(void) static inline void touch_lh_set_idle_channel_connect(enum touch_conn_type_e type) { - REG_SET_FIELD(RTC_CNTL_RTC_TOUCH_SCAN_CTRL_REG, + REG_SET_FIELD(RTC_CNTL_TOUCH_SCAN_CTRL_REG, RTC_CNTL_TOUCH_INACTIVE_CONNECTION, type); } @@ -977,7 +977,7 @@ static inline enum touch_conn_type_e touch_lh_get_idle_channel_connect(void) { return (enum touch_conn_type_e) - REG_GET_FIELD(RTC_CNTL_RTC_TOUCH_SCAN_CTRL_REG, + REG_GET_FIELD(RTC_CNTL_TOUCH_SCAN_CTRL_REG, RTC_CNTL_TOUCH_INACTIVE_CONNECTION); } @@ -1022,42 +1022,42 @@ static inline void touch_lh_intr_enable(enum touch_intr_mask_e int_mask) if (int_mask & TOUCH_INTR_MASK_DONE) { REG_SET_FIELD(RTC_CNTL_INT_ENA_RTC_W1TS_REG, - RTC_CNTL_RTC_TOUCH_DONE_INT_ENA_W1TS, + RTC_CNTL_TOUCH_DONE_INT_ENA_W1TS, true); } if (int_mask & TOUCH_INTR_MASK_ACTIVE) { REG_SET_FIELD(RTC_CNTL_INT_ENA_RTC_W1TS_REG, - RTC_CNTL_RTC_TOUCH_ACTIVE_INT_ENA_W1TS, + RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TS, true); } if (int_mask & TOUCH_INTR_MASK_INACTIVE) { REG_SET_FIELD(RTC_CNTL_INT_ENA_RTC_W1TS_REG, - RTC_CNTL_RTC_TOUCH_INACTIVE_INT_ENA_W1TS, + RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TS, true); } if (int_mask & TOUCH_INTR_MASK_SCAN_DONE) { REG_SET_FIELD(RTC_CNTL_INT_ENA_RTC_W1TS_REG, - RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_ENA_W1TS, + RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TS, true); } if (int_mask & TOUCH_INTR_MASK_TIMEOUT) { REG_SET_FIELD(RTC_CNTL_INT_ENA_RTC_W1TS_REG, - RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_ENA_W1TS, + RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TS, true); } if (int_mask & TOUCH_INTR_MASK_PROXI_MEAS_DONE) { REG_SET_FIELD(RTC_CNTL_INT_ENA_RTC_W1TS_REG, - RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS, + RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS, true); } } @@ -1081,42 +1081,42 @@ static inline void touch_lh_intr_disable(enum touch_intr_mask_e int_mask) if (int_mask & TOUCH_INTR_MASK_DONE) { REG_SET_FIELD(RTC_CNTL_INT_ENA_RTC_W1TC_REG, - RTC_CNTL_RTC_TOUCH_DONE_INT_ENA_W1TC, + RTC_CNTL_TOUCH_DONE_INT_ENA_W1TC, true); } if (int_mask & TOUCH_INTR_MASK_ACTIVE) { REG_SET_FIELD(RTC_CNTL_INT_ENA_RTC_W1TC_REG, - RTC_CNTL_RTC_TOUCH_ACTIVE_INT_ENA_W1TC, + RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TC, true); } if (int_mask & TOUCH_INTR_MASK_INACTIVE) { REG_SET_FIELD(RTC_CNTL_INT_ENA_RTC_W1TC_REG, - RTC_CNTL_RTC_TOUCH_INACTIVE_INT_ENA_W1TC, + RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TC, true); } if (int_mask & TOUCH_INTR_MASK_SCAN_DONE) { REG_SET_FIELD(RTC_CNTL_INT_ENA_RTC_W1TC_REG, - RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_ENA_W1TC, + RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TC, true); } if (int_mask & TOUCH_INTR_MASK_TIMEOUT) { REG_SET_FIELD(RTC_CNTL_INT_ENA_RTC_W1TC_REG, - RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_ENA_W1TC, + RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TC, true); } if (int_mask & TOUCH_INTR_MASK_PROXI_MEAS_DONE) { REG_SET_FIELD(RTC_CNTL_INT_ENA_RTC_W1TC_REG, - RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC, + RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC, true); } } @@ -1139,43 +1139,43 @@ static inline void touch_lh_intr_clear(enum touch_intr_mask_e int_mask) { if (int_mask & TOUCH_INTR_MASK_DONE) { - REG_SET_FIELD(RTC_CNTL_INT_CLR_RTC_REG, - RTC_CNTL_RTC_TOUCH_DONE_INT_CLR, + REG_SET_FIELD(RTC_CNTL_INT_CLR_REG, + RTC_CNTL_TOUCH_DONE_INT_CLR, true); } if (int_mask & TOUCH_INTR_MASK_ACTIVE) { - REG_SET_FIELD(RTC_CNTL_INT_CLR_RTC_REG, - RTC_CNTL_RTC_TOUCH_ACTIVE_INT_CLR, + REG_SET_FIELD(RTC_CNTL_INT_CLR_REG, + RTC_CNTL_TOUCH_ACTIVE_INT_CLR, true); } if (int_mask & TOUCH_INTR_MASK_INACTIVE) { - REG_SET_FIELD(RTC_CNTL_INT_CLR_RTC_REG, - RTC_CNTL_RTC_TOUCH_INACTIVE_INT_CLR, + REG_SET_FIELD(RTC_CNTL_INT_CLR_REG, + RTC_CNTL_TOUCH_INACTIVE_INT_CLR, true); } if (int_mask & TOUCH_INTR_MASK_SCAN_DONE) { - REG_SET_FIELD(RTC_CNTL_INT_CLR_RTC_REG, - RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_CLR, + REG_SET_FIELD(RTC_CNTL_INT_CLR_REG, + RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR, true); } if (int_mask & TOUCH_INTR_MASK_TIMEOUT) { - REG_SET_FIELD(RTC_CNTL_INT_CLR_RTC_REG, - RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_CLR, + REG_SET_FIELD(RTC_CNTL_INT_CLR_REG, + RTC_CNTL_TOUCH_TIMEOUT_INT_CLR, true); } if (int_mask & TOUCH_INTR_MASK_PROXI_MEAS_DONE) { - REG_SET_FIELD(RTC_CNTL_INT_CLR_RTC_REG, - RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR, + REG_SET_FIELD(RTC_CNTL_INT_CLR_REG, + RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_CLR, true); } } @@ -1196,35 +1196,35 @@ static inline void touch_lh_intr_clear(enum touch_intr_mask_e int_mask) static inline uint32_t touch_lh_read_intr_status_mask(void) { - uint32_t intr_st = getreg32(RTC_CNTL_INT_ST_RTC_REG); + uint32_t intr_st = getreg32(RTC_CNTL_INT_ST_REG); uint32_t intr_msk = 0; - if (intr_st & RTC_CNTL_RTC_TOUCH_DONE_INT_ST_M) + if (intr_st & RTC_CNTL_TOUCH_DONE_INT_ST_M) { intr_msk |= TOUCH_INTR_MASK_DONE; } - if (intr_st & RTC_CNTL_RTC_TOUCH_ACTIVE_INT_ST_M) + if (intr_st & RTC_CNTL_TOUCH_ACTIVE_INT_ST_M) { intr_msk |= TOUCH_INTR_MASK_ACTIVE; } - if (intr_st & RTC_CNTL_RTC_TOUCH_INACTIVE_INT_ST_M) + if (intr_st & RTC_CNTL_TOUCH_INACTIVE_INT_ST_M) { intr_msk |= TOUCH_INTR_MASK_INACTIVE; } - if (intr_st & RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_ST_M) + if (intr_st & RTC_CNTL_TOUCH_SCAN_DONE_INT_ST_M) { intr_msk |= TOUCH_INTR_MASK_SCAN_DONE; } - if (intr_st & RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_ST_M) + if (intr_st & RTC_CNTL_TOUCH_TIMEOUT_INT_ST_M) { intr_msk |= TOUCH_INTR_MASK_TIMEOUT; } - if (intr_st & RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST_M) + if (intr_st & RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ST_M) { intr_msk |= TOUCH_INTR_MASK_PROXI_MEAS_DONE; } @@ -1253,7 +1253,7 @@ static inline uint32_t touch_lh_read_intr_status_mask(void) static inline void touch_lh_timeout_enable(void) { - REG_SET_FIELD(RTC_CNTL_RTC_TOUCH_TIMEOUT_CTRL_REG, + REG_SET_FIELD(RTC_CNTL_TOUCH_TIMEOUT_CTRL_REG, RTC_CNTL_TOUCH_TIMEOUT_EN, true); } @@ -1279,7 +1279,7 @@ static inline void touch_lh_timeout_enable(void) static inline void touch_lh_timeout_disable(void) { - REG_SET_FIELD(RTC_CNTL_RTC_TOUCH_TIMEOUT_CTRL_REG, + REG_SET_FIELD(RTC_CNTL_TOUCH_TIMEOUT_CTRL_REG, RTC_CNTL_TOUCH_TIMEOUT_EN, false); } @@ -1301,7 +1301,7 @@ static inline void touch_lh_timeout_disable(void) static inline void touch_lh_timeout_set_threshold(uint32_t threshold) { - return REG_SET_FIELD(RTC_CNTL_RTC_TOUCH_TIMEOUT_CTRL_REG, + return REG_SET_FIELD(RTC_CNTL_TOUCH_TIMEOUT_CTRL_REG, RTC_CNTL_TOUCH_TIMEOUT_NUM, threshold); } @@ -1323,7 +1323,7 @@ static inline void touch_lh_timeout_set_threshold(uint32_t threshold) static inline uint32_t touch_lh_timeout_get_threshold(void) { - return REG_GET_FIELD(RTC_CNTL_RTC_TOUCH_TIMEOUT_CTRL_REG, + return REG_GET_FIELD(RTC_CNTL_TOUCH_TIMEOUT_CTRL_REG, RTC_CNTL_TOUCH_TIMEOUT_NUM); } @@ -1435,7 +1435,7 @@ static inline void touch_lh_reset_benchmark(enum touch_pad_e tp) static inline void touch_lh_filter_set_filter_mode(enum touch_filter_mode_e mode) { - REG_SET_FIELD(RTC_CNTL_RTC_TOUCH_FILTER_CTRL_REG, + REG_SET_FIELD(RTC_CNTL_TOUCH_FILTER_CTRL_REG, RTC_CNTL_TOUCH_FILTER_MODE, mode); } @@ -1460,7 +1460,7 @@ static inline enum touch_filter_mode_e touch_lh_filter_get_filter_mode(void) { return (enum touch_filter_mode_e) - REG_GET_FIELD(RTC_CNTL_RTC_TOUCH_FILTER_CTRL_REG, + REG_GET_FIELD(RTC_CNTL_TOUCH_FILTER_CTRL_REG, RTC_CNTL_TOUCH_FILTER_MODE); } @@ -1483,7 +1483,7 @@ static inline enum touch_filter_mode_e static inline void touch_lh_filter_set_smooth_mode(enum touch_smooth_mode_e mode) { - REG_SET_FIELD(RTC_CNTL_RTC_TOUCH_FILTER_CTRL_REG, + REG_SET_FIELD(RTC_CNTL_TOUCH_FILTER_CTRL_REG, RTC_CNTL_TOUCH_SMOOTH_LVL, mode); } @@ -1508,7 +1508,7 @@ static inline enum touch_smooth_mode_e touch_lh_filter_get_smooth_mode(void) { return (enum touch_smooth_mode_e) - REG_GET_FIELD(RTC_CNTL_RTC_TOUCH_FILTER_CTRL_REG, + REG_GET_FIELD(RTC_CNTL_TOUCH_FILTER_CTRL_REG, RTC_CNTL_TOUCH_SMOOTH_LVL); } @@ -1530,7 +1530,7 @@ static inline enum touch_smooth_mode_e static inline void touch_lh_filter_set_debounce(uint32_t dbc_cnt) { - REG_SET_FIELD(RTC_CNTL_RTC_TOUCH_FILTER_CTRL_REG, + REG_SET_FIELD(RTC_CNTL_TOUCH_FILTER_CTRL_REG, RTC_CNTL_TOUCH_DEBOUNCE, dbc_cnt); } @@ -1553,7 +1553,7 @@ static inline void touch_lh_filter_set_debounce(uint32_t dbc_cnt) static inline uint32_t touch_lh_filter_get_debounce(void) { - return REG_GET_FIELD(RTC_CNTL_RTC_TOUCH_FILTER_CTRL_REG, + return REG_GET_FIELD(RTC_CNTL_TOUCH_FILTER_CTRL_REG, RTC_CNTL_TOUCH_DEBOUNCE); } @@ -1576,25 +1576,25 @@ static inline uint32_t touch_lh_filter_get_debounce(void) static inline void touch_lh_filter_set_noise_thres(uint32_t noise_thr) { - REG_SET_FIELD(RTC_CNTL_RTC_TOUCH_FILTER_CTRL_REG, + REG_SET_FIELD(RTC_CNTL_TOUCH_FILTER_CTRL_REG, RTC_CNTL_TOUCH_NOISE_THRES, noise_thr); /* config2 in IDF */ - REG_SET_FIELD(RTC_CNTL_RTC_TOUCH_FILTER_CTRL_REG, + REG_SET_FIELD(RTC_CNTL_TOUCH_FILTER_CTRL_REG, RTC_CNTL_TOUCH_NEG_NOISE_THRES, noise_thr); /* config1 in IDF */ - REG_SET_FIELD(RTC_CNTL_RTC_TOUCH_FILTER_CTRL_REG, + REG_SET_FIELD(RTC_CNTL_TOUCH_FILTER_CTRL_REG, RTC_CNTL_TOUCH_NEG_NOISE_LIMIT, 0xf); /* config3 in IDF */ - REG_SET_FIELD(RTC_CNTL_RTC_TOUCH_FILTER_CTRL_REG, + REG_SET_FIELD(RTC_CNTL_TOUCH_FILTER_CTRL_REG, RTC_CNTL_TOUCH_HYSTERESIS, 2); } @@ -1618,7 +1618,7 @@ static inline void touch_lh_filter_set_noise_thres(uint32_t noise_thr) static inline uint32_t touch_lh_filter_get_noise_thres(void) { - return REG_GET_FIELD(RTC_CNTL_RTC_TOUCH_FILTER_CTRL_REG, + return REG_GET_FIELD(RTC_CNTL_TOUCH_FILTER_CTRL_REG, RTC_CNTL_TOUCH_NOISE_THRES); } @@ -1639,7 +1639,7 @@ static inline uint32_t touch_lh_filter_get_noise_thres(void) static inline void touch_lh_filter_set_jitter_step(uint32_t step) { - REG_SET_FIELD(RTC_CNTL_RTC_TOUCH_FILTER_CTRL_REG, + REG_SET_FIELD(RTC_CNTL_TOUCH_FILTER_CTRL_REG, RTC_CNTL_TOUCH_JITTER_STEP, step); } @@ -1661,7 +1661,7 @@ static inline void touch_lh_filter_set_jitter_step(uint32_t step) static inline uint32_t touch_lh_filter_get_jitter_step(void) { - return REG_GET_FIELD(RTC_CNTL_RTC_TOUCH_FILTER_CTRL_REG, + return REG_GET_FIELD(RTC_CNTL_TOUCH_FILTER_CTRL_REG, RTC_CNTL_TOUCH_JITTER_STEP); } @@ -1681,7 +1681,7 @@ static inline uint32_t touch_lh_filter_get_jitter_step(void) static inline void touch_lh_filter_enable(void) { - REG_SET_FIELD(RTC_CNTL_RTC_TOUCH_FILTER_CTRL_REG, + REG_SET_FIELD(RTC_CNTL_TOUCH_FILTER_CTRL_REG, RTC_CNTL_TOUCH_FILTER_EN, true); } @@ -1702,7 +1702,7 @@ static inline void touch_lh_filter_enable(void) static inline void touch_lh_filter_disable(void) { - REG_SET_FIELD(RTC_CNTL_RTC_TOUCH_FILTER_CTRL_REG, + REG_SET_FIELD(RTC_CNTL_TOUCH_FILTER_CTRL_REG, RTC_CNTL_TOUCH_FILTER_EN, false); } @@ -1730,7 +1730,7 @@ static inline void touch_lh_filter_disable(void) static inline void touch_lh_denoise_enable(void) { - REG_SET_FIELD(RTC_CNTL_RTC_TOUCH_FILTER_CTRL_REG, + REG_SET_FIELD(RTC_CNTL_TOUCH_FILTER_CTRL_REG, RTC_CNTL_TOUCH_DENOISE_EN, true); } @@ -1758,7 +1758,7 @@ static inline void touch_lh_denoise_enable(void) static inline void touch_lh_denoise_disable(void) { - REG_SET_FIELD(RTC_CNTL_RTC_TOUCH_FILTER_CTRL_REG, + REG_SET_FIELD(RTC_CNTL_TOUCH_FILTER_CTRL_REG, RTC_CNTL_TOUCH_DENOISE_EN, false); } @@ -1783,7 +1783,7 @@ static inline void touch_lh_denoise_disable(void) static inline void touch_lh_denoise_set_cap_level(enum touch_denoise_cap_e cap_level) { - REG_SET_FIELD(RTC_CNTL_RTC_TOUCH_CTRL2_REG, + REG_SET_FIELD(RTC_CNTL_TOUCH_CTRL2_REG, RTC_CNTL_TOUCH_REFC, cap_level); } @@ -1808,7 +1808,7 @@ static inline void static inline enum touch_denoise_cap_e touch_lh_denoise_get_cap_level(void) { return (enum touch_denoise_cap_e) - REG_GET_FIELD(RTC_CNTL_RTC_TOUCH_CTRL2_REG, RTC_CNTL_TOUCH_REFC); + REG_GET_FIELD(RTC_CNTL_TOUCH_CTRL2_REG, RTC_CNTL_TOUCH_REFC); } /**************************************************************************** @@ -1829,7 +1829,7 @@ static inline enum touch_denoise_cap_e touch_lh_denoise_get_cap_level(void) static inline void touch_lh_denoise_set_grade(enum touch_denoise_grade_e grade) { - REG_SET_FIELD(RTC_CNTL_RTC_TOUCH_SCAN_CTRL_REG, + REG_SET_FIELD(RTC_CNTL_TOUCH_SCAN_CTRL_REG, RTC_CNTL_TOUCH_DENOISE_RES, grade); } @@ -1852,7 +1852,7 @@ static inline void static inline enum touch_denoise_grade_e touch_lh_denoise_get_grade(void) { return (enum touch_denoise_grade_e) - REG_GET_FIELD(RTC_CNTL_RTC_TOUCH_SCAN_CTRL_REG, + REG_GET_FIELD(RTC_CNTL_TOUCH_SCAN_CTRL_REG, RTC_CNTL_TOUCH_DENOISE_RES); } @@ -1891,7 +1891,7 @@ static inline uint32_t touch_lh_denoise_read_data(void) static inline void touch_lh_waterproof_set_guard_pad(enum touch_pad_e tp) { - REG_SET_FIELD(RTC_CNTL_RTC_TOUCH_SCAN_CTRL_REG, + REG_SET_FIELD(RTC_CNTL_TOUCH_SCAN_CTRL_REG, RTC_CNTL_TOUCH_OUT_RING, tp); } @@ -1913,7 +1913,7 @@ static inline void touch_lh_waterproof_set_guard_pad(enum touch_pad_e tp) static inline enum touch_pad_e touch_lh_waterproof_get_guard_pad(void) { return (enum touch_pad_e) - REG_GET_FIELD(RTC_CNTL_RTC_TOUCH_SCAN_CTRL_REG, RTC_CNTL_TOUCH_OUT_RING); + REG_GET_FIELD(RTC_CNTL_TOUCH_SCAN_CTRL_REG, RTC_CNTL_TOUCH_OUT_RING); } /**************************************************************************** @@ -1935,7 +1935,7 @@ static inline enum touch_pad_e touch_lh_waterproof_get_guard_pad(void) static inline void touch_lh_waterproof_set_sheild_driver(enum touch_shield_driver_e level) { - REG_SET_FIELD(RTC_CNTL_RTC_TOUCH_SCAN_CTRL_REG, + REG_SET_FIELD(RTC_CNTL_TOUCH_SCAN_CTRL_REG, RTC_CNTL_TOUCH_BUFDRV, level); } @@ -1960,7 +1960,7 @@ static inline enum touch_shield_driver_e touch_lh_waterproof_get_sheild_driver(void) { return (enum touch_shield_driver_e) - REG_GET_FIELD(RTC_CNTL_RTC_TOUCH_SCAN_CTRL_REG, RTC_CNTL_TOUCH_BUFDRV); + REG_GET_FIELD(RTC_CNTL_TOUCH_SCAN_CTRL_REG, RTC_CNTL_TOUCH_BUFDRV); } /**************************************************************************** @@ -1987,7 +1987,7 @@ static inline enum touch_shield_driver_e static inline void touch_lh_waterproof_enable(void) { - REG_SET_FIELD(RTC_CNTL_RTC_TOUCH_SCAN_CTRL_REG, + REG_SET_FIELD(RTC_CNTL_TOUCH_SCAN_CTRL_REG, RTC_CNTL_TOUCH_SHIELD_PAD_EN, true); } @@ -2016,7 +2016,7 @@ static inline void touch_lh_waterproof_enable(void) static inline void touch_lh_waterproof_disable(void) { - REG_SET_FIELD(RTC_CNTL_RTC_TOUCH_SCAN_CTRL_REG, + REG_SET_FIELD(RTC_CNTL_TOUCH_SCAN_CTRL_REG, RTC_CNTL_TOUCH_SHIELD_PAD_EN, false); } @@ -2096,7 +2096,7 @@ static inline void static inline void touch_lh_proximity_set_meas_times(uint32_t times) { - REG_SET_FIELD(RTC_CNTL_RTC_TOUCH_APPROACH_REG, + REG_SET_FIELD(RTC_CNTL_TOUCH_APPROACH_REG, RTC_CNTL_TOUCH_APPROACH_MEAS_TIME, times); } @@ -2117,7 +2117,7 @@ static inline void touch_lh_proximity_set_meas_times(uint32_t times) static inline uint32_t touch_lh_proximity_get_meas_times(void) { - return REG_GET_FIELD(RTC_CNTL_RTC_TOUCH_APPROACH_REG, + return REG_GET_FIELD(RTC_CNTL_TOUCH_APPROACH_REG, RTC_CNTL_TOUCH_APPROACH_MEAS_TIME); } @@ -2206,7 +2206,7 @@ static inline bool touch_lh_proximity_pad_check(enum touch_pad_e tp) static inline void touch_lh_sleep_set_channel_num(enum touch_pad_e tp) { - REG_SET_FIELD(RTC_CNTL_RTC_TOUCH_SLP_THRES_REG, + REG_SET_FIELD(RTC_CNTL_TOUCH_SLP_THRES_REG, RTC_CNTL_TOUCH_SLP_PAD, tp); } @@ -2229,7 +2229,7 @@ static inline void touch_lh_sleep_set_channel_num(enum touch_pad_e tp) static inline enum touch_pad_e touch_lh_sleep_get_channel_num(void) { return (enum touch_pad_e) - REG_GET_FIELD(RTC_CNTL_RTC_TOUCH_SLP_THRES_REG, RTC_CNTL_TOUCH_SLP_PAD); + REG_GET_FIELD(RTC_CNTL_TOUCH_SLP_THRES_REG, RTC_CNTL_TOUCH_SLP_PAD); } /**************************************************************************** @@ -2253,7 +2253,7 @@ static inline enum touch_pad_e touch_lh_sleep_get_channel_num(void) static inline void touch_lh_sleep_set_threshold(uint32_t touch_thres) { - return REG_SET_FIELD(RTC_CNTL_RTC_TOUCH_SLP_THRES_REG, + return REG_SET_FIELD(RTC_CNTL_TOUCH_SLP_THRES_REG, RTC_CNTL_TOUCH_SLP_TH, touch_thres); } @@ -2279,7 +2279,7 @@ static inline void touch_lh_sleep_set_threshold(uint32_t touch_thres) static inline uint32_t touch_lh_sleep_get_threshold(void) { - return REG_GET_FIELD(RTC_CNTL_RTC_TOUCH_SLP_THRES_REG, + return REG_GET_FIELD(RTC_CNTL_TOUCH_SLP_THRES_REG, RTC_CNTL_TOUCH_SLP_TH); } @@ -2299,7 +2299,7 @@ static inline uint32_t touch_lh_sleep_get_threshold(void) static inline void touch_lh_sleep_enable_approach(void) { - REG_SET_FIELD(RTC_CNTL_RTC_TOUCH_SLP_THRES_REG, + REG_SET_FIELD(RTC_CNTL_TOUCH_SLP_THRES_REG, RTC_CNTL_TOUCH_SLP_APPROACH_EN, true); } @@ -2320,7 +2320,7 @@ static inline void touch_lh_sleep_enable_approach(void) static inline void touch_lh_sleep_disable_approach(void) { - REG_SET_FIELD(RTC_CNTL_RTC_TOUCH_SLP_THRES_REG, + REG_SET_FIELD(RTC_CNTL_TOUCH_SLP_THRES_REG, RTC_CNTL_TOUCH_SLP_APPROACH_EN, false); } @@ -2341,7 +2341,7 @@ static inline void touch_lh_sleep_disable_approach(void) static inline bool touch_lh_sleep_get_approach_status(void) { - return (bool) REG_GET_FIELD(RTC_CNTL_RTC_TOUCH_SLP_THRES_REG, + return (bool) REG_GET_FIELD(RTC_CNTL_TOUCH_SLP_THRES_REG, RTC_CNTL_TOUCH_SLP_APPROACH_EN); } @@ -2408,7 +2408,7 @@ static inline uint32_t touch_lh_sleep_read_smooth(void) static inline uint32_t touch_lh_sleep_read_data(void) { - uint32_t tp = REG_GET_FIELD(RTC_CNTL_RTC_TOUCH_SLP_THRES_REG, + uint32_t tp = REG_GET_FIELD(RTC_CNTL_TOUCH_SLP_THRES_REG, RTC_CNTL_TOUCH_SLP_PAD); REG_SET_FIELD(SENS_SAR_TOUCH_CONF_REG, @@ -2438,7 +2438,7 @@ static inline uint32_t touch_lh_sleep_read_data(void) static inline void touch_lh_sleep_reset_benchmark(void) { - REG_SET_FIELD(RTC_CNTL_RTC_TOUCH_APPROACH_REG, + REG_SET_FIELD(RTC_CNTL_TOUCH_APPROACH_REG, RTC_CNTL_TOUCH_SLP_CHANNEL_CLR, true); } @@ -2459,7 +2459,7 @@ static inline void touch_lh_sleep_reset_benchmark(void) static inline void touch_lh_sleep_low_power(bool is_low_power) { - REG_SET_FIELD(RTC_CNTL_RTC_TOUCH_CTRL2_REG, + REG_SET_FIELD(RTC_CNTL_TOUCH_CTRL2_REG, RTC_CNTL_TOUCH_DBIAS, is_low_power); } @@ -2521,7 +2521,7 @@ static inline uint32_t touch_lh_sleep_read_proximity_cnt(void) static inline enum touch_pad_e touch_lh_get_wakeup_status(void) { return (enum touch_pad_e) - REG_GET_FIELD(RTC_CNTL_RTC_TOUCH_SLP_THRES_REG, + REG_GET_FIELD(RTC_CNTL_TOUCH_SLP_THRES_REG, RTC_CNTL_TOUCH_SLP_PAD); } diff --git a/arch/xtensa/src/esp32s3/esp32s3_twai.c b/arch/xtensa/src/esp32s3/esp32s3_twai.c index 416e9c841c9a3..7837228774092 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_twai.c +++ b/arch/xtensa/src/esp32s3/esp32s3_twai.c @@ -40,10 +40,10 @@ #include "xtensa.h" -#include "esp32s3_gpio.h" +#include "esp_gpio.h" #include "esp32s3_twai.h" -#include "esp32s3_irq.h" -#include "esp32s3_clockconfig.h" +#include "esp_irq.h" +#include "esp_clk.h" #include "periph_ctrl.h" @@ -473,8 +473,11 @@ static int esp32s3twai_setup(struct can_dev_s *dev) } priv->cpu = this_cpu(); - priv->cpuint = esp32s3_setup_irq(priv->cpu, priv->periph, - 1, ESP32S3_CPUINT_LEVEL); + priv->cpuint = esp_setup_irq(priv->periph, + 1, + ESP_IRQ_TRIGGER_LEVEL, + esp32s3twai_interrupt, + dev); if (priv->cpuint < 0) { /* Failed to allocate a CPU interrupt of this type. */ @@ -485,18 +488,6 @@ static int esp32s3twai_setup(struct can_dev_s *dev) return ret; } - ret = irq_attach(priv->irq, esp32s3twai_interrupt, dev); - if (ret != OK) - { - /* Failed to attach IRQ, so CPU interrupt must be freed. */ - - esp32s3_teardown_irq(priv->cpu, priv->periph, priv->cpuint); - priv->cpuint = -ENOMEM; - spin_unlock_irqrestore(&priv->lock, flags); - - return ret; - } - /* Enable the CPU interrupt that is linked to the TWAI device. */ up_enable_irq(priv->irq); @@ -535,13 +526,9 @@ static void esp32s3twai_shutdown(struct can_dev_s *dev) up_disable_irq(priv->irq); - /* Dissociate the IRQ from the ISR */ - - irq_detach(priv->irq); - /* Free cpu interrupt that is attached to this peripheral */ - esp32s3_teardown_irq(priv->cpu, priv->periph, priv->cpuint); + esp_teardown_irq(priv->periph, priv->cpuint); priv->cpuint = -ENOMEM; } } @@ -1239,19 +1226,13 @@ struct can_dev_s *esp32s3_twaiinitialize(void) flags = spin_lock_irqsave(&g_twaipriv.lock); - /* Enable power to the TWAI module and - * Enable clocking to the TWAI module - */ - - periph_module_enable(PERIPH_TWAI_MODULE); - /* Configure CAN GPIO pins */ - esp32s3_configgpio(CONFIG_ESP32S3_TWAI_TXPIN, OUTPUT_FUNCTION_2); - esp32s3_gpio_matrix_out(CONFIG_ESP32S3_TWAI_TXPIN, TWAI_TX_IDX, 0, 0); + esp_configgpio(CONFIG_ESP32S3_TWAI_TXPIN, OUTPUT_FUNCTION_2); + esp_gpio_matrix_out(CONFIG_ESP32S3_TWAI_TXPIN, TWAI_TX_IDX, 0, 0); - esp32s3_configgpio(CONFIG_ESP32S3_TWAI_RXPIN, INPUT_FUNCTION_2); - esp32s3_gpio_matrix_in(CONFIG_ESP32S3_TWAI_RXPIN, TWAI_RX_IDX, 0); + esp_configgpio(CONFIG_ESP32S3_TWAI_RXPIN, INPUT_FUNCTION_2); + esp_gpio_matrix_in(CONFIG_ESP32S3_TWAI_RXPIN, TWAI_RX_IDX, 0); spin_unlock_irqrestore(&g_twaipriv.lock, flags); #endif diff --git a/arch/xtensa/src/esp32s3/esp32s3_usbserial.c b/arch/xtensa/src/esp32s3/esp32s3_usbserial.c index 95deaad626f4c..982c8864ac467 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_usbserial.c +++ b/arch/xtensa/src/esp32s3/esp32s3_usbserial.c @@ -47,7 +47,7 @@ #include "hardware/esp32s3_usb_serial_jtag.h" #include "esp32s3_config.h" -#include "esp32s3_irq.h" +#include "esp_irq.h" /**************************************************************************** * Pre-processor Macros @@ -281,23 +281,21 @@ static int esp32s3_attach(struct uart_dev_s *dev) /* Try to attach the IRQ to a CPU int */ priv->cpu = this_cpu(); - priv->cpuint = esp32s3_setup_irq(priv->cpu, priv->periph, - ESP32S3_INT_PRIO_DEF, - ESP32S3_CPUINT_LEVEL); + priv->cpuint = esp_setup_irq(priv->periph, + ESP32S3_INT_PRIO_DEF, + ESP_IRQ_TRIGGER_LEVEL, + esp32s3_interrupt, + dev); if (priv->cpuint < 0) { return priv->cpuint; } - /* Attach and enable the IRQ */ + /* Enable the IRQ */ - ret = irq_attach(priv->irq, esp32s3_interrupt, dev); - if (ret == OK) - { - up_enable_irq(priv->irq); - } + up_enable_irq(priv->irq); - return ret; + return OK; } /**************************************************************************** @@ -317,8 +315,7 @@ static void esp32s3_detach(struct uart_dev_s *dev) DEBUGASSERT(priv->cpuint != -ENOMEM); up_disable_irq(priv->irq); - irq_detach(priv->irq); - esp32s3_teardown_irq(priv->cpu, priv->periph, priv->cpuint); + esp_teardown_irq(priv->periph, priv->cpuint); priv->cpuint = -ENOMEM; } @@ -478,4 +475,3 @@ void esp32s3_usbserial_write(char ch) esp32s3_send(&g_uart_usbserial, ch); } - diff --git a/arch/xtensa/src/esp32s3/esp32s3_userspace.c b/arch/xtensa/src/esp32s3/esp32s3_userspace.c index 5a30464e55c41..ab8f541a1b18c 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_userspace.c +++ b/arch/xtensa/src/esp32s3/esp32s3_userspace.c @@ -37,7 +37,7 @@ #include "chip.h" #include "xtensa.h" #include "esp_attr.h" -#include "esp32s3_irq.h" +#include "esp_irq.h" #include "esp32s3_userspace.h" #include "hardware/esp32s3_apb_ctrl.h" #include "hardware/esp32s3_cache_memory.h" @@ -1861,24 +1861,14 @@ void esp32s3_userspace(void) void esp32s3_pmsirqinitialize(void) { - VERIFY(esp32s3_setup_irq(0, - ESP32S3_PERIPH_CORE_0_IRAM0_PMS_MONITOR_VIOLATE, - 1, ESP32S3_CPUINT_LEVEL)); - VERIFY(esp32s3_setup_irq(0, - ESP32S3_PERIPH_CORE_0_DRAM0_PMS_MONITOR_VIOLATE, - 1, ESP32S3_CPUINT_LEVEL)); - VERIFY(esp32s3_setup_irq(0, ESP32S3_PERIPH_CACHE_CORE0_ACS, 1, - ESP32S3_CPUINT_LEVEL)); - VERIFY(esp32s3_setup_irq(0, ESP32S3_PERIPH_CORE_0_PIF_PMS_MONITOR_VIOLATE, - 1, ESP32S3_CPUINT_LEVEL)); - - VERIFY(irq_attach(ESP32S3_IRQ_CORE_0_IRAM0_PMS_MONITOR_VIOLATE, - pms_violation_isr, NULL)); - VERIFY(irq_attach(ESP32S3_IRQ_CORE_0_DRAM0_PMS_MONITOR_VIOLATE, - pms_violation_isr, NULL)); - VERIFY(irq_attach(ESP32S3_IRQ_CACHE_CORE0_ACS, pms_violation_isr, NULL)); - VERIFY(irq_attach(ESP32S3_IRQ_CORE_0_PIF_PMS_MONITOR_VIOLATE, - pms_violation_isr, NULL)); + VERIFY(esp_setup_irq(ESP32S3_PERIPH_CORE_0_IRAM0_PMS_MONITOR_VIOLATE, + 1, ESP_IRQ_TRIGGER_LEVEL, pms_violation_isr, NULL)); + VERIFY(esp_setup_irq(ESP32S3_PERIPH_CORE_0_DRAM0_PMS_MONITOR_VIOLATE, + 1, ESP_IRQ_TRIGGER_LEVEL, pms_violation_isr, NULL)); + VERIFY(esp_setup_irq(ESP32S3_PERIPH_CACHE_CORE0_ACS, + 1, ESP_IRQ_TRIGGER_LEVEL, pms_violation_isr, NULL)); + VERIFY(esp_setup_irq(ESP32S3_PERIPH_CORE_0_PIF_PMS_MONITOR_VIOLATE, + 1, ESP_IRQ_TRIGGER_LEVEL, pms_violation_isr, NULL)); up_enable_irq(ESP32S3_IRQ_CORE_0_IRAM0_PMS_MONITOR_VIOLATE); up_enable_irq(ESP32S3_IRQ_CORE_0_DRAM0_PMS_MONITOR_VIOLATE); diff --git a/arch/xtensa/src/esp32s3/esp32s3_wdt.c b/arch/xtensa/src/esp32s3/esp32s3_wdt.c index f234334e08f9b..c1f709fe68603 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_wdt.c +++ b/arch/xtensa/src/esp32s3/esp32s3_wdt.c @@ -30,19 +30,52 @@ #include #include "xtensa.h" -#include "hardware/esp32s3_rtccntl.h" +#include "soc/rtc_cntl_reg.h" #include "hardware/esp32s3_tim.h" -#include "hardware/esp32s3_efuse.h" +#include "soc/efuse_reg.h" +#include "hal/rwdt_ll.h" -#include "esp32s3_irq.h" +#include "espressif/esp_irq.h" #include "esp32s3_rtc_gpio.h" #include "esp32s3_wdt.h" -#include + +/* Undefine macros that conflict with HAL definitions */ + +#undef RTC_CNTL_MIN_SLP_VAL_MIN +#undef RTC_FAST_CLK_FREQ_8M + +#include "soc/rtc.h" /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ +/* Offset relative to each watchdog timer instance memory base */ + +#define RWDT_CONFIG0_OFFSET 0x0098 +#define XTWDT_CONFIG0_OFFSET 0x0060 + +/* RWDT */ + +#define RWDT_STAGE0_TIMEOUT_OFFSET 0x009C +#define RWDT_STAGE1_TIMEOUT_OFFSET 0x00A0 +#define RWDT_STAGE2_TIMEOUT_OFFSET 0x00A4 +#define RWDT_STAGE3_TIMEOUT_OFFSET 0x00A8 +#define RWDT_FEED_OFFSET 0x00AC +#define RWDT_WP_REG 0x00B0 +#define RWDT_INT_ENA_REG_OFFSET 0x0040 +#define RWDT_INT_CLR_REG_OFFSET 0x004c + +/* XTWDT */ + +#define XTWDT_TIMEOUT_OFFSET 0x00f8 +#define XTWDT_CLK_PRESCALE_OFFSET 0x00f4 +#define XTWDT_INT_ENA_REG_OFFSET 0x0040 + +/* Number of cycles for RTC_SLOW_CLK calibration */ + +#define SLOW_CLK_CAL_CYCLES 1024 + /* Helpers for converting from Q13.19 fixed-point format to float */ #define N 19 @@ -64,12 +97,7 @@ * Private Types ****************************************************************************/ -enum wdt_peripheral_e -{ - RTC, - TIMER, - XTAL32K, -}; +/* ESP32-S3 WDT private data */ struct esp32s3_wdt_priv_s { @@ -178,7 +206,7 @@ struct esp32s3_wdt_priv_s g_esp32s3_mwdt1_priv = struct esp32s3_wdt_priv_s g_esp32s3_rwdt_priv = { .ops = &esp32s3_wdt_ops, - .base = RTC_CNTL_RTC_OPTIONS0_REG, + .base = RTC_CNTL_OPTIONS0_REG, .periph = ESP32S3_PERIPH_RTC_CORE, .irq = ESP32S3_IRQ_RTC_WDT, .cpuint = -ENOMEM, @@ -191,7 +219,7 @@ struct esp32s3_wdt_priv_s g_esp32s3_rwdt_priv = struct esp32s3_wdt_priv_s g_esp32s3_xtwdt_priv = { .ops = &esp32s3_wdt_ops, - .base = RTC_CNTL_RTC_OPTIONS0_REG, + .base = RTC_CNTL_OPTIONS0_REG, .periph = ESP32S3_PERIPH_RTC_CORE, .irq = ESP32S3_IRQ_RTC_XTAL32K_DEAD, .cpuint = -ENOMEM, @@ -483,7 +511,7 @@ static void wdt_disablewp(struct esp32s3_wdt_dev_s *dev) if (IS_RWDT(dev)) { - wdt_putreg(dev, RWDT_WP_REG, RTC_CNTL_WDT_WKEY_VALUE); + wdt_putreg(dev, RWDT_WP_REG, TIMG_WDT_WKEY_VALUE); } else if (IS_MWDT(dev)) { @@ -647,7 +675,7 @@ static void wdt_feed(struct esp32s3_wdt_dev_s *dev) if (IS_RWDT(dev)) { - wdt_modifyreg32(dev, RWDT_FEED_OFFSET, 0, RTC_CNTL_RTC_WDT_FEED); + wdt_modifyreg32(dev, RWDT_FEED_OFFSET, 0, RTC_CNTL_WDT_FEED); } else if (IS_MWDT(dev)) { @@ -672,7 +700,7 @@ static void wdt_feed(struct esp32s3_wdt_dev_s *dev) static uint16_t wdt_rtc_clk(struct esp32s3_wdt_dev_s *dev) { - enum esp32s3_rtc_slow_freq_e slow_clk_rtc; + soc_rtc_slow_clk_src_t slow_clk_rtc; uint32_t period_13q19; float period; float cycles_ms; @@ -682,23 +710,23 @@ static uint16_t wdt_rtc_clk(struct esp32s3_wdt_dev_s *dev) * used to calibrate this source. */ - static const enum esp32s3_rtc_cal_sel_e cal_map[] = + static const soc_clk_freq_calculation_src_t cal_map[] = { - RTC_CAL_RTC_MUX, - RTC_CAL_32K_XTAL, - RTC_CAL_8MD256 + CLK_CAL_RTC_SLOW, + CLK_CAL_32K_XTAL, + CLK_CAL_RC_FAST_D256 }; DEBUGASSERT(dev); /* Check which clock is sourcing the slow_clk_rtc */ - slow_clk_rtc = esp32s3_rtc_get_slow_clk(); + slow_clk_rtc = rtc_clk_slow_src_get(); /* Get the slow_clk_rtc period in us in Q13.19 fixed point format */ - period_13q19 = esp32s3_rtc_clk_cal(cal_map[slow_clk_rtc], - SLOW_CLK_CAL_CYCLES); + period_13q19 = rtc_clk_cal(cal_map[slow_clk_rtc], + SLOW_CLK_CAL_CYCLES); /* Assert no error happened during the calibration */ @@ -762,7 +790,7 @@ static int32_t wdt_setisr(struct esp32s3_wdt_dev_s *dev, xcpt_t handler, wdt->irq == ESP32S3_IRQ_RTC_XTAL32K_DEAD) { esp32s3_rtcioirqdisable(wdt->irq); - irq_detach(wdt->irq); + esp32s3_rtcioirqdetach(wdt->irq); } else #endif @@ -772,8 +800,7 @@ static int32_t wdt_setisr(struct esp32s3_wdt_dev_s *dev, xcpt_t handler, */ up_disable_irq(wdt->irq); - esp32s3_teardown_irq(wdt->cpu, wdt->periph, wdt->cpuint); - irq_detach(wdt->irq); + esp_teardown_irq(wdt->periph, wdt->cpuint); wdt->cpuint = -ENOMEM; } } @@ -791,7 +818,7 @@ static int32_t wdt_setisr(struct esp32s3_wdt_dev_s *dev, xcpt_t handler, if (wdt->irq == ESP32S3_IRQ_RTC_WDT || wdt->irq == ESP32S3_IRQ_RTC_XTAL32K_DEAD) { - ret = irq_attach(wdt->irq, handler, arg); + ret = esp32s3_rtcioirqattach(wdt->irq, handler, arg); if (ret != OK) { @@ -806,8 +833,9 @@ static int32_t wdt_setisr(struct esp32s3_wdt_dev_s *dev, xcpt_t handler, #endif { wdt->cpu = this_cpu(); - wdt->cpuint = esp32s3_setup_irq(wdt->cpu, wdt->periph, - 1, ESP32S3_CPUINT_LEVEL); + wdt->cpuint = esp_setup_irq(wdt->periph, + 1, ESP_IRQ_TRIGGER_LEVEL, + handler, arg); if (wdt->cpuint < 0) { wderr("ERROR: No CPU Interrupt available"); @@ -815,16 +843,6 @@ static int32_t wdt_setisr(struct esp32s3_wdt_dev_s *dev, xcpt_t handler, goto errout; } - /* Associate an IRQ Number (from the WDT) to an ISR */ - - ret = irq_attach(wdt->irq, handler, arg); - if (ret != OK) - { - esp32s3_teardown_irq(wdt->cpu, wdt->periph, wdt->cpuint); - wderr("ERROR: Failed to associate an IRQ Number"); - goto errout; - } - /* Enable the CPU Interrupt that is linked to the WDT */ up_enable_irq(wdt->irq); @@ -853,7 +871,7 @@ static void wdt_enableint(struct esp32s3_wdt_dev_s *dev) if (IS_RWDT(dev)) { wdt_modifyreg32(dev, RWDT_INT_ENA_REG_OFFSET, 0, - RTC_CNTL_RTC_WDT_INT_ENA); + RTC_CNTL_WDT_INT_ENA); } else if (IS_MWDT(dev)) { @@ -862,7 +880,7 @@ static void wdt_enableint(struct esp32s3_wdt_dev_s *dev) else { wdt_modifyreg32(dev, XTWDT_INT_ENA_REG_OFFSET, 0, - RTC_CNTL_RTC_XTAL32K_DEAD_INT_ENA); + RTC_CNTL_XTAL32K_DEAD_INT_ENA); } } @@ -883,7 +901,7 @@ static void wdt_disableint(struct esp32s3_wdt_dev_s *dev) if (IS_RWDT(dev)) { - wdt_modifyreg32(dev, RWDT_INT_ENA_REG_OFFSET, RTC_CNTL_RTC_WDT_INT_ENA, + wdt_modifyreg32(dev, RWDT_INT_ENA_REG_OFFSET, RTC_CNTL_WDT_INT_ENA, 0); } else if (IS_MWDT(dev)) @@ -893,7 +911,7 @@ static void wdt_disableint(struct esp32s3_wdt_dev_s *dev) else { wdt_modifyreg32(dev, XTWDT_INT_ENA_REG_OFFSET, - RTC_CNTL_RTC_XTAL32K_DEAD_INT_ENA, 0); + RTC_CNTL_XTAL32K_DEAD_INT_ENA, 0); } } @@ -914,7 +932,7 @@ static void wdt_ackint(struct esp32s3_wdt_dev_s *dev) if (IS_RWDT(dev)) { - wdt_putreg(dev, RWDT_INT_CLR_REG_OFFSET, RTC_CNTL_RTC_WDT_INT_CLR); + wdt_putreg(dev, RWDT_INT_CLR_REG_OFFSET, RTC_CNTL_WDT_INT_CLR); } else if (IS_MWDT(dev)) { @@ -923,7 +941,7 @@ static void wdt_ackint(struct esp32s3_wdt_dev_s *dev) else { wdt_putreg(dev, MWDT_INT_CLR_REG_OFFSET, - RTC_CNTL_RTC_XTAL32K_DEAD_INT_CLR); + RTC_CNTL_XTAL32K_DEAD_INT_CLR); } } @@ -1058,11 +1076,10 @@ struct esp32s3_wdt_dev_s *esp32s3_wdt_init(enum esp32s3_wdt_inst_e wdt_id) void esp32s3_wdt_early_deinit(void) { uint32_t regval; - putreg32(RTC_CNTL_WDT_WKEY_VALUE, RTC_CNTL_RTC_WDTWPROTECT_REG); - regval = getreg32(RTC_CNTL_RTC_WDTCONFIG0_REG); + regval = getreg32(RTC_CNTL_WDTCONFIG0_REG); regval &= ~RTC_CNTL_WDT_EN; - putreg32(regval, RTC_CNTL_RTC_WDTCONFIG0_REG); - putreg32(0, RTC_CNTL_RTC_WDTWPROTECT_REG); + putreg32(regval, RTC_CNTL_WDTCONFIG0_REG); + putreg32(0, RTC_CNTL_WDTWPROTECT_REG); } /**************************************************************************** diff --git a/arch/xtensa/src/esp32s3/esp32s3_wdt.h b/arch/xtensa/src/esp32s3/esp32s3_wdt.h index 4beb711d1d8a2..13d573572dc31 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_wdt.h +++ b/arch/xtensa/src/esp32s3/esp32s3_wdt.h @@ -30,6 +30,10 @@ #include #include +#include + +#include "esp32s3_wdt_lowerhalf.h" +#include "esp_irq.h" /**************************************************************************** * Pre-processor Definitions @@ -75,16 +79,6 @@ * Public Types ****************************************************************************/ -/* Instances of Watchdog Timer */ - -enum esp32s3_wdt_inst_e -{ - ESP32S3_WDT_MWDT0 = 0, /* Main System Watchdog Timer (MWDT) of Timer Group 0 */ - ESP32S3_WDT_MWDT1, /* Main System Watchdog Timer (MWDT) of Timer Group 1 */ - ESP32S3_WDT_RWDT, /* RTC Watchdog Timer (RWDT) */ - ESP32S3_WDT_XTWDT /* XTAL32K Watchdog Timer (XTWDT) */ -}; - /* Stages of a Watchdog Timer. A WDT has 4 stages. */ enum esp32s3_wdt_stage_e @@ -115,6 +109,15 @@ enum esp32s3_wdt_stage_action_e */ }; +/* Type of the WDT Peripheral */ + +enum wdt_peripheral_e +{ + RTC, + TIMER, + XTAL32K, +}; + /* ESP32-S3 WDT device */ struct esp32s3_wdt_dev_s @@ -150,7 +153,8 @@ struct esp32s3_wdt_ops_s /* WDT interrupts */ - int32_t (*setisr)(struct esp32s3_wdt_dev_s *dev, xcpt_t handler, + int32_t (*setisr)(struct esp32s3_wdt_dev_s *dev, + xcpt_t handler, void *arg); void (*enableint)(struct esp32s3_wdt_dev_s *dev); void (*disableint)(struct esp32s3_wdt_dev_s *dev); diff --git a/arch/xtensa/src/esp32s3/esp32s3_wdt_lowerhalf.c b/arch/xtensa/src/esp32s3/esp32s3_wdt_lowerhalf.c index 4c19e449caf3a..ffaf4ae5de0b5 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_wdt_lowerhalf.c +++ b/arch/xtensa/src/esp32s3/esp32s3_wdt_lowerhalf.c @@ -38,10 +38,10 @@ #include "xtensa.h" #include "esp32s3_wdt.h" -#include "esp32s3_rtc.h" #include "esp32s3_wdt_lowerhalf.h" #include "hardware/esp32s3_soc.h" +#include "soc/rtc.h" #include "soc/periph_defs.h" #include "esp_private/periph_ctrl.h" @@ -95,13 +95,6 @@ * Private Types ****************************************************************************/ -enum wdt_peripheral_e -{ - RTC, - TIMER, - XTAL32K, -}; - /* This structure provides the private representation of the "lower-half" * driver state structure. This structure must be cast-compatible with the * well-known watchdog_lowerhalf_s structure. @@ -248,18 +241,18 @@ static int wdt_lh_start(struct watchdog_lowerhalf_s *lower) if (priv->handler == NULL) { - /* Then configure it to reset on wdt expiration */ - - if (priv->peripheral == TIMER) - { - ESP32S3_WDT_STG_CONF(priv->wdt, ESP32S3_WDT_STAGE0, - ESP32S3_WDT_STAGE_ACTION_RESET_SYSTEM); - } - else if (priv->peripheral == RTC) - { - ESP32S3_WDT_STG_CONF(priv->wdt, ESP32S3_WDT_STAGE0, - ESP32S3_WDT_STAGE_ACTION_RESET_RTC); - } + /* Then configure it to reset on wdt expiration */ + + if (priv->peripheral == TIMER) + { + ESP32S3_WDT_STG_CONF(priv->wdt, ESP32S3_WDT_STAGE0, + ESP32S3_WDT_STAGE_ACTION_RESET_SYSTEM); + } + else if (priv->peripheral == RTC) + { + ESP32S3_WDT_STG_CONF(priv->wdt, ESP32S3_WDT_STAGE0, + ESP32S3_WDT_STAGE_ACTION_RESET_RTC); + } } /* User handler was already provided */ @@ -289,7 +282,7 @@ static int wdt_lh_start(struct watchdog_lowerhalf_s *lower) ESP32S3_WDT_LOCK(priv->wdt); } - return OK; + return OK; } /**************************************************************************** @@ -913,7 +906,7 @@ int esp32s3_wdt_initialize(const char *devpath, enum esp32s3_wdt_inst_e wdt) /* Estimate frequency of internal RTC oscillator */ uint32_t rtc_clk_period_us = - esp32s3_rtc_clk_cal(RTC_CAL_INTERNAL_OSC, XT_WDT_CLK_CAL_CYCLES); + rtc_clk_cal(CLK_CAL_RC_SLOW, XT_WDT_CLK_CAL_CYCLES); uint32_t rtc_clk_frequency_khz = wdt_lh_clk_freq_cal(rtc_clk_period_us) / 1000; diff --git a/arch/xtensa/src/esp32s3/esp32s3_wdt_lowerhalf.h b/arch/xtensa/src/esp32s3/esp32s3_wdt_lowerhalf.h index 767772a1670f9..2d5040fd3361d 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_wdt_lowerhalf.h +++ b/arch/xtensa/src/esp32s3/esp32s3_wdt_lowerhalf.h @@ -25,12 +25,20 @@ * Included Files ****************************************************************************/ -#include "esp32s3_wdt.h" - /**************************************************************************** * Public Types ****************************************************************************/ +/* Instances of Watchdog Timer */ + +enum esp32s3_wdt_inst_e +{ + ESP32S3_WDT_MWDT0 = 0, /* Main System Watchdog Timer (MWDT) of Timer Group 0 */ + ESP32S3_WDT_MWDT1, /* Main System Watchdog Timer (MWDT) of Timer Group 1 */ + ESP32S3_WDT_RWDT, /* RTC Watchdog Timer (RWDT) */ + ESP32S3_WDT_XTWDT /* XTAL32K Watchdog Timer (XTWDT) */ +}; + /**************************************************************************** * Public Function Prototypes ****************************************************************************/ diff --git a/arch/xtensa/src/esp32s3/esp32s3_wifi_adapter.c b/arch/xtensa/src/esp32s3/esp32s3_wifi_adapter.c index 0e21ea09efb82..7cc02f2be4a4a 100644 --- a/arch/xtensa/src/esp32s3/esp32s3_wifi_adapter.c +++ b/arch/xtensa/src/esp32s3/esp32s3_wifi_adapter.c @@ -43,9 +43,12 @@ #include "xtensa.h" #include "esp_attr.h" +#include "esp_irq.h" +#include "esp_cpu.h" #include "hardware/esp32s3_system.h" -#include "hardware/esp32s3_rtccntl.h" - +#include "soc/rtc_cntl_reg.h" +#include "rom/rtc.h" +#include "platform/os.h" #include "espressif/esp_wireless.h" #include "espressif/esp_wifi_utils.h" @@ -76,29 +79,31 @@ * Private Types ****************************************************************************/ -/* Wi-Fi interrupt adapter private data */ +/* Wi-Fi time private data */ -struct irq_adpt +struct time_adpt { - void (*func)(void *arg); /* Interrupt callback function */ - void *arg; /* Interrupt private data */ + time_t sec; /* Second value */ + suseconds_t usec; /* Micro second value */ }; -/* Wi-Fi message queue private data */ +typedef struct shared_vector_desc_t shared_vector_desc_t; +typedef struct vector_desc_t vector_desc_t; -struct mq_adpt +typedef struct intr_handle_data_t { - struct file mq; /* Message queue handle */ - uint32_t msgsize; /* Message size */ - char name[16]; /* Message queue name */ -}; + vector_desc_t *vector_desc; + shared_vector_desc_t *shared_vector_desc; +} intr_handle_data_t; -/* Wi-Fi time private data */ - -struct time_adpt +struct vector_desc_t { - time_t sec; /* Second value */ - suseconds_t usec; /* Micro second value */ + int flags: 16; + unsigned int cpu: 1; + unsigned int intno: 5; + int source: 16; + shared_vector_desc_t *shared_vec_info; + vector_desc_t *next; }; /**************************************************************************** @@ -112,12 +117,10 @@ static int is_in_isr_wrapper(void); #endif /* CONFIG_ESPRESSIF_WIFI_BT_COEXIST */ static bool wifi_env_is_chip(void); -static void wifi_set_intr(int32_t cpu_no, uint32_t intr_source, - uint32_t intr_num, int32_t intr_prio); -static void wifi_clear_intr(uint32_t intr_source, uint32_t intr_num); -static void esp_set_isr(int32_t n, void *f, void *arg); -static void esp32s3_ints_on(uint32_t mask); -static void esp32s3_ints_off(uint32_t mask); +static void set_intr_wrapper(int32_t cpu_no, uint32_t intr_source, + uint32_t intr_num, int32_t intr_prio); +static void clear_intr_wrapper(uint32_t intr_source, uint32_t intr_num); +static void set_isr_wrapper(int32_t n, void *f, void *arg); static bool wifi_is_from_isr(void); static void *esp_spin_lock_create(void); static void esp_spin_lock_delete(void *lock); @@ -264,6 +267,8 @@ static int coex_schm_flexible_period_set_wrapper(uint8_t period); static uint8_t coex_schm_flexible_period_get_wrapper(void); static void * coex_schm_get_phase_by_idx_wrapper(int phase_idx); +extern vector_desc_t *get_desc_for_int(int intno, int cpu); + /**************************************************************************** * Private Data ****************************************************************************/ @@ -303,11 +308,11 @@ wifi_osi_funcs_t g_wifi_osi_funcs = { ._version = ESP_WIFI_OS_ADAPTER_VERSION, ._env_is_chip = wifi_env_is_chip, - ._set_intr = wifi_set_intr, - ._clear_intr = wifi_clear_intr, - ._set_isr = esp_set_isr, - ._ints_on = esp32s3_ints_on, - ._ints_off = esp32s3_ints_off, + ._set_intr = set_intr_wrapper, + ._clear_intr = clear_intr_wrapper, + ._set_isr = set_isr_wrapper, + ._ints_on = esp_cpu_intr_enable, + ._ints_off = esp_cpu_intr_disable, ._is_from_isr = wifi_is_from_isr, ._spin_lock_create = esp_spin_lock_create, ._spin_lock_delete = esp_spin_lock_delete, @@ -432,29 +437,6 @@ wifi_osi_funcs_t g_wifi_osi_funcs = * Private Functions ****************************************************************************/ -/**************************************************************************** - * Name: esp_int_adpt_cb - * - * Description: - * Wi-Fi interrupt adapter callback function - * - * Input Parameters: - * arg - interrupt adapter private data - * - * Returned Value: - * 0 on success - * - ****************************************************************************/ - -static int esp_int_adpt_cb(int irq, void *context, void *arg) -{ - struct irq_adpt *adapter = (struct irq_adpt *)arg; - - adapter->func(adapter->arg); - - return 0; -} - /**************************************************************************** * Name: esp_thread_semphr_free * @@ -501,7 +483,7 @@ static void esp_update_time(struct timespec *timespec, uint32_t ticks) } /**************************************************************************** - * Name: esp_set_isr + * Name: set_isr_wrapper * * Description: * Register interrupt function @@ -516,97 +498,9 @@ static void esp_update_time(struct timespec *timespec, uint32_t ticks) * ****************************************************************************/ -static void esp_set_isr(int32_t n, void *f, void *arg) +static void set_isr_wrapper(int32_t n, void *f, void *arg) { - int ret; - uint32_t tmp; - struct irq_adpt *adapter; - int irq = n + XTENSA_IRQ_FIRSTPERIPH; - - wlinfo("n=%" PRId32 " f=%p arg=%p", n, f, arg); - - if (g_irqvector[irq].handler && - g_irqvector[irq].handler != irq_unexpected_isr) - { - wlinfo("irq=%d has been set handler=%p\n", irq, - g_irqvector[irq].handler); - return; - } - - tmp = sizeof(struct irq_adpt); - adapter = kmm_malloc(tmp); - if (!adapter) - { - wlerr("Failed to alloc %" PRIu32 " memory\n", tmp); - PANIC(); - return; - } - - adapter->func = f; - adapter->arg = arg; - - ret = irq_attach(ESP32S3_IRQ_MAC, esp_int_adpt_cb, adapter); - if (ret) - { - wlerr("Failed to attach IRQ %d\n", irq); - PANIC(); - return; - } - - ret = irq_attach(ESP32S3_IRQ_PWR, esp_int_adpt_cb, adapter); - if (ret) - { - wlerr("Failed to attach IRQ %d\n", irq); - PANIC(); - return; - } -} - -/**************************************************************************** - * Name: esp32s3_ints_on - * - * Description: - * Enable Wi-Fi interrupt - * - * Input Parameters: - * mask - No mean - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void esp32s3_ints_on(uint32_t mask) -{ - int irq = __builtin_ffs(mask) - 1; - - wlinfo("INFO mask=%08" PRIx32 " irq=%d\n", mask, irq); - - up_enable_irq(ESP32S3_IRQ_MAC); - up_enable_irq(ESP32S3_IRQ_PWR); -} - -/**************************************************************************** - * Name: esp32s3_ints_off - * - * Description: - * Disable Wi-Fi interrupt - * - * Input Parameters: - * mask - No mean - * - * Returned Value: - * None - * - ****************************************************************************/ - -static void esp32s3_ints_off(uint32_t mask) -{ - uint32_t irq = __builtin_ffs(mask) - 1; - - wlinfo("INFO mask=%08" PRIx32 " irq=%" PRIu32 "\n", mask, irq); - - up_disable_irq(ESP32S3_IRQ_MAC); + xt_set_interrupt_handler(n, (xt_handler)f, arg); } /**************************************************************************** @@ -1841,7 +1735,7 @@ static bool wifi_env_is_chip(void) } /**************************************************************************** - * Name: wifi_set_intr + * Name: set_intr_wrapper * * Description: * Do nothing @@ -1857,24 +1751,44 @@ static bool wifi_env_is_chip(void) * ****************************************************************************/ -static void wifi_set_intr(int32_t cpu_no, uint32_t intr_source, - uint32_t intr_num, int32_t intr_prio) +static void set_intr_wrapper(int32_t cpu_no, uint32_t intr_source, + uint32_t intr_num, int32_t intr_prio) { + intr_handle_t handle; + int irq = ESP_SOURCE2IRQ(intr_source); + wlinfo("cpu_no=%" PRId32 ", intr_source=%" PRIu32 ", intr_num=%" PRIu32 ", intr_prio=%" PRId32 "\n", cpu_no, intr_source, intr_num, intr_prio); + + esp_rom_route_intr_matrix(cpu_no, intr_source, intr_num); + + handle = kmm_calloc(1, sizeof(intr_handle_data_t)); + if (handle == NULL) + { + wlerr("Failed to kmm_calloc\n"); + return; + } + + handle->vector_desc = get_desc_for_int(intr_num, cpu_no); + + handle->vector_desc->source = intr_source; + + /* Register the handle - it contains all needed information (cpuint, cpu) */ + + esp_set_handle(cpu_no, irq, handle); } /**************************************************************************** - * Name: wifi_clear_intr + * Name: clear_intr_wrapper * * Description: * Don't support * ****************************************************************************/ -static void IRAM_ATTR wifi_clear_intr(uint32_t intr_source, - uint32_t intr_num) +static void IRAM_ATTR clear_intr_wrapper(uint32_t intr_source, + uint32_t intr_num) { } @@ -2318,7 +2232,7 @@ static void wifi_rtc_disable_iso(void) int64_t esp32s3_timer_get_time(void) { - return (int64_t)esp32s3_rt_timer_time_us(); + return (int64_t)esp_hr_timer_time_us(); } /**************************************************************************** diff --git a/arch/xtensa/src/esp32s3/hal.mk b/arch/xtensa/src/esp32s3/hal.mk index a2db0bd74d96c..43594c762634b 100644 --- a/arch/xtensa/src/esp32s3/hal.mk +++ b/arch/xtensa/src/esp32s3/hal.mk @@ -18,6 +18,10 @@ # ############################################################################ +EXTRA_LIBPATHS += -L $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)xtensa$(DELIM)$(CHIP_SERIES) + +EXTRA_LIBS += -lxt_hal + # Include header paths INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)$(CHIP_SERIES)$(DELIM)include @@ -30,22 +34,76 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_adc$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_adc$(DELIM)interface INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_adc$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_blockdev$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_common$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_coex$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_event$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ana_conv$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ana_conv$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_clock$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_clock$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_dma$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_dma$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpio$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpio$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpspi$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpspi$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_i2c$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_i2c$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_i2s$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_i2s$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ledc$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ledc$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_mcpwm$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_mcpwm$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_mspi$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_mspi$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_parlio$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_parlio$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_pcnt$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_pcnt$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_pmu$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_pmu$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_rmt$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_rmt$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_rtc_timer$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_rtc_timer$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_security$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_security$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_timg$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_timg$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_touch_sens$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_touch_sens$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_twai$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_twai$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_uart$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_uart$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_usb$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_usb$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_wdt$(DELIM)$(CHIP_SERIES)$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_wdt$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)dma$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_dma$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_dma$(DELIM)src +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)etm$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_timer$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_timer$(DELIM)private_include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include$(DELIM)esp_private INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include$(DELIM)soc +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)include$(DELIM)soc$(DELIM)$(CHIP_SERIES) INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)ldo$(DELIM)include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi_timing_tuning$(DELIM)include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi_timing_tuning$(DELIM)tuning_scheme_impl$(DELIM)include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi_timing_tuning$(DELIM)port$(DELIM)$(CHIP_SERIES) +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi$(DELIM)mspi_intr$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi$(DELIM)mspi_timing_tuning$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi$(DELIM)mspi_timing_tuning$(DELIM)tuning_scheme_impl$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi$(DELIM)mspi_timing_tuning$(DELIM)port$(DELIM)$(CHIP_SERIES) INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)power_supply$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_mm$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_pm +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_pm$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_security$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)$(CHIP_SERIES)$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES) @@ -56,6 +114,8 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)include$(DELIM)private +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_timer$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_timer$(DELIM)private_include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)public_compat INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_timer$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_wifi$(DELIM)include @@ -66,8 +126,14 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)log_level$(DELIM)tag_log_level +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port$(DELIM)include$(DELIM)aes +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port$(DELIM)psa_driver$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)newlib$(DELIM)priv_include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)tf-psa-crypto$(DELIM)drivers$(DELIM)builtin$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)tf-psa-crypto$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)mbedtls$(DELIM)tf-psa-crypto$(DELIM)core +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_libc$(DELIM)priv_include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)register INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)include @@ -77,16 +143,20 @@ INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)private_include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)bootloader_flash$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)include$(DELIM)spi_flash +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)include$(DELIM)esp_flash_chips +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)include$(DELIM)esp_private INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_app_format$(DELIM)include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)esp_driver_gpio$(DELIM)include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)esp_driver_uart$(DELIM)include -INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)include$(DELIM)mbedtls INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)ulp$(DELIM)ulp_common INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)ulp$(DELIM)ulp_common$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)ulp$(DELIM)ulp_riscv$(DELIM)include INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)ulp$(DELIM)ulp_riscv$(DELIM)shared INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)ulp$(DELIM)ulp_riscv$(DELIM)shared$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_gpio$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_rmt$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_rmt$(DELIM)src +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_uart$(DELIM)include +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)include$(DELIM)mbedtls +INCLUDES += $(INCDIR_PREFIX)$(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)esp_libc$(DELIM)platform_include # Linker scripts @@ -96,7 +166,7 @@ ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM) ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.libgcc.ld ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.newlib.ld ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.version.ld -ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).rom.wdt.ld +ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_wdt$(DELIM)$(CHIP_SERIES)$(DELIM)rom.wdt.ld ARCHSCRIPT += $(ARCH_SRCDIR)$(DELIM)chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)ld$(DELIM)$(CHIP_SERIES).peripherals.ld ifeq ($(CONFIG_ESPRESSIF_USE_ULP_RISCV_CORE),y) ARCHSCRIPT += $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)scripts$(DELIM)ulp_aliases.ld @@ -123,7 +193,11 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)clk_ctrl_os.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)clk_utils.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)cpu.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_dma$(DELIM)src$(DELIM)esp_dma_utils.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_dma$(DELIM)src$(DELIM)gdma.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_dma$(DELIM)src$(DELIM)gdma_link.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)esp_clk.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)esp_gpio_reserve.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)esp_memory_utils.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)hw_random.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mac_addr.c @@ -143,62 +217,78 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_sleep.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_time.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)systimer.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi_timing_tuning$(DELIM)mspi_timing_tuning.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi_timing_tuning$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)mspi_timing_config.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi$(DELIM)mspi_timing_tuning$(DELIM)mspi_timing_tuning.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)mspi$(DELIM)mspi_timing_tuning$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)mspi_timing_config.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)esp_clk_tree_common.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)regi2c_ctrl.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)rtc_module.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)sleep_modes.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)sleep_uart.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)power_supply$(DELIM)brownout.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_libc$(DELIM)src$(DELIM)port$(DELIM)esp_time_impl.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_mm$(DELIM)esp_mmu_map.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_mm$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)ext_mem_layout.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_mm$(DELIM)esp_cache.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_mm$(DELIM)esp_cache_msync.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_mm$(DELIM)esp_cache_utils.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)$(CHIP_SERIES)$(DELIM)phy_init_data.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)src$(DELIM)phy_common.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_phy$(DELIM)src$(DELIM)phy_init.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_wdt.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_cache_esp32s2_esp32s3.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_pm$(DELIM)pm_locks.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_pm$(DELIM)pm_impl.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_sys.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_print.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_crc.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_serial_output.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_spiflash.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_efuse.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_gpio.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_cache_esp32s2_esp32s3.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)esp_err.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)esp_system.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)startup.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)startup_funcs.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)system_time.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)clk.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_system$(DELIM)port$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)system_internal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_timer$(DELIM)src$(DELIM)esp_timer_impl_common.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_timer$(DELIM)src$(DELIM)esp_timer_impl_systimer.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_timer$(DELIM)src$(DELIM)esp_timer.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_timer$(DELIM)src$(DELIM)esp_timer_init.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)adc_hal_common.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)adc_oneshot_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)aes_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)$(CHIP_SERIES)$(DELIM)clk_tree_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_timer$(DELIM)src$(DELIM)esp_timer_impl_systimer.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_timer$(DELIM)src$(DELIM)system_time.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_timer$(DELIM)src$(DELIM)esp_timer_impl_common.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ana_conv$(DELIM)adc_hal_common.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ana_conv$(DELIM)adc_oneshot_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_security$(DELIM)aes_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_clock$(DELIM)$(CHIP_SERIES)$(DELIM)clk_tree_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)$(CHIP_SERIES)$(DELIM)efuse_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_cntl_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)brownout_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_pmu$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_cntl_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_pmu$(DELIM)brownout_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)efuse_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)gpio_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)ledc_hal_iram.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)ledc_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)pcnt_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)rmt_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)rtc_io_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)sdm_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)i2s_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)sha_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)mcpwm_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpio$(DELIM)gpio_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ledc$(DELIM)ledc_hal_iram.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ledc$(DELIM)ledc_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_pcnt$(DELIM)pcnt_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_rmt$(DELIM)rmt_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpio$(DELIM)rtc_io_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpio$(DELIM)sdm_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_i2s$(DELIM)i2s_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_security$(DELIM)sha_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_mcpwm$(DELIM)mcpwm_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)systimer_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)timer_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)touch_sens_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_timg$(DELIM)timer_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_touch_sens$(DELIM)touch_sens_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)cache_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)mpu_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_security$(DELIM)mpu_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)mmu_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)i2c_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)uart_hal_iram.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)uart_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_i2c$(DELIM)i2c_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_uart$(DELIM)uart_hal_iram.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_uart$(DELIM)uart_hal.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)hal_utils.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)spi_flash_hal.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)spi_flash_hal_iram.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)spi_flash_hal_gpspi.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)spi_flash_encrypt_hal_iram.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_mspi$(DELIM)spi_flash_hal.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_mspi$(DELIM)spi_flash_hal_iram.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_mspi$(DELIM)spi_flash_hal_gpspi.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_mspi$(DELIM)spi_flash_encrypt_hal_iram.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_dma$(DELIM)gdma_hal_ahb_v1.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_dma$(DELIM)gdma_hal_top.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)log_level$(DELIM)log_level.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)log_level$(DELIM)tag_log_level$(DELIM)tag_log_level.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)log_level$(DELIM)tag_log_level$(DELIM)linked_list$(DELIM)log_linked_list.c @@ -207,22 +297,20 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)noos$(DELIM)log_timestamp.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)os$(DELIM)log_write.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)src$(DELIM)os$(DELIM)util.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)mbedtls$(DELIM)port$(DELIM)sha$(DELIM)core$(DELIM)esp_sha256.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)newlib$(DELIM)src$(DELIM)port$(DELIM)esp_time_impl.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)dport_access_common.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)dedic_gpio_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)gdma_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)adc_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpio$(DELIM)$(CHIP_SERIES)$(DELIM)dedic_gpio_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_dma$(DELIM)$(CHIP_SERIES)$(DELIM)gdma_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ana_conv$(DELIM)$(CHIP_SERIES)$(DELIM)adc_periph.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)gpio_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)ledc_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)pcnt_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)rmt_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_io_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)sdm_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)i2c_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)i2s_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)mcpwm_periph.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)temperature_sensor_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ledc$(DELIM)$(CHIP_SERIES)$(DELIM)ledc_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_pcnt$(DELIM)$(CHIP_SERIES)$(DELIM)pcnt_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_rmt$(DELIM)$(CHIP_SERIES)$(DELIM)rmt_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpio$(DELIM)$(CHIP_SERIES)$(DELIM)rtc_io_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_gpio$(DELIM)$(CHIP_SERIES)$(DELIM)sdm_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_i2c$(DELIM)$(CHIP_SERIES)$(DELIM)i2c_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_i2s$(DELIM)$(CHIP_SERIES)$(DELIM)i2s_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_mcpwm$(DELIM)$(CHIP_SERIES)$(DELIM)mcpwm_periph.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_ana_conv$(DELIM)$(CHIP_SERIES)$(DELIM)temperature_sensor_periph.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)spi_flash_wrap.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)spi_flash_hpm_enable.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)${CHIP_SERIES}$(DELIM)spi_flash_oct_flash_init.c @@ -249,13 +337,39 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)ulp$ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)ulp$(DELIM)ulp_riscv$(DELIM)ulp_riscv.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)ulp$(DELIM)ulp_riscv$(DELIM)ulp_riscv_lock.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)ulp$(DELIM)ulp_riscv$(DELIM)ulp_riscv_i2c.c - -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)esp_driver_gpio$(DELIM)src$(DELIM)gpio.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)esp_driver_gpio$(DELIM)src$(DELIM)rtc_io.c -CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)esp_driver_uart$(DELIM)src$(DELIM)uart_wakeup.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_rmt$(DELIM)src$(DELIM)rmt_common.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_rmt$(DELIM)src$(DELIM)rmt_encoder.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_rmt$(DELIM)src$(DELIM)rmt_encoder_bytes.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_rmt$(DELIM)src$(DELIM)rmt_encoder_copy.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_rmt$(DELIM)src$(DELIM)rmt_encoder_simple.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_rmt$(DELIM)src$(DELIM)rmt_rx.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_rmt$(DELIM)src$(DELIM)rmt_tx.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_gpio$(DELIM)src$(DELIM)gpio.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_gpio$(DELIM)src$(DELIM)rtc_io.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)upper_hal_uart$(DELIM)src$(DELIM)uart_wakeup.c CHIP_ASRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_cache_writeback_esp32s3.S +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)platform$(DELIM)os.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)heap_caps.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)newlib$(DELIM)newlib$(DELIM)libc$(DELIM)misc$(DELIM)init.c + +ifeq ($(CONFIG_SMP),y) +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)nuttx$(DELIM)src$(DELIM)components$(DELIM)esp_system$(DELIM)esp_ipc.c +endif + +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)intr_alloc.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hw_support$(DELIM)port$(DELIM)$(CHIP_SERIES)$(DELIM)esp_cpu_intr.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)xtensa$(DELIM)xtensa_intr.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)interrupts.c + +# Security components (for WiFi/crypto support) + +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_security$(DELIM)src$(DELIM)esp_hmac.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_security$(DELIM)src$(DELIM)esp_crypto_periph_clk.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_security$(DELIM)src$(DELIM)esp_crypto_lock.c +CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_security$(DELIM)hmac_hal.c + # Bootloader files CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)flash_encrypt.c @@ -270,7 +384,6 @@ ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y) CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_common_loader.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)bootloader_flash$(DELIM)src$(DELIM)flash_qio_mode.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_clock_init.c - CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_clock_loader.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_efuse.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_mem.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_random.c @@ -278,11 +391,8 @@ ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y) CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)esp_image_format.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)${CHIP_SERIES}$(DELIM)bootloader_soc.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)bootloader_support$(DELIM)src$(DELIM)bootloader_sha.c - CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)${CHIP_SERIES}$(DELIM)uart_periph.c - CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_uart.c - CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_sys.c + CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_hal_uart$(DELIM)${CHIP_SERIES}$(DELIM)uart_periph.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_systimer.c - CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)esp_rom$(DELIM)patches$(DELIM)esp_rom_spiflash.c CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)efuse$(DELIM)src$(DELIM)esp_efuse_fields.c LDFLAGS += --wrap=bootloader_print_banner diff --git a/arch/xtensa/src/esp32s3/hardware/esp32s3_efuse.h b/arch/xtensa/src/esp32s3/hardware/esp32s3_efuse.h deleted file mode 100644 index 4e5b54de1f858..0000000000000 --- a/arch/xtensa/src/esp32s3/hardware/esp32s3_efuse.h +++ /dev/null @@ -1,3245 +0,0 @@ -/**************************************************************************** - * arch/xtensa/src/esp32s3/hardware/esp32s3_efuse.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_EFUSE_H -#define __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_EFUSE_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include "esp32s3_soc.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* EFUSE_PGM_DATA0_REG register - * Register 0 that stores data to be programmed. - */ - -#define EFUSE_PGM_DATA0_REG (DR_REG_EFUSE_BASE + 0x0) - -/* EFUSE_PGM_DATA_0 : R/W; bitpos: [31:0]; default: 0; - * The content of the 0th 32-bit data to be programmed. - */ - -#define EFUSE_PGM_DATA_0 0xffffffff -#define EFUSE_PGM_DATA_0_M (EFUSE_PGM_DATA_0_V << EFUSE_PGM_DATA_0_S) -#define EFUSE_PGM_DATA_0_V 0xffffffff -#define EFUSE_PGM_DATA_0_S 0 - -/* EFUSE_PGM_DATA1_REG register - * Register 1 that stores data to be programmed. - */ - -#define EFUSE_PGM_DATA1_REG (DR_REG_EFUSE_BASE + 0x4) - -/* EFUSE_PGM_DATA_1 : R/W; bitpos: [31:0]; default: 0; - * The content of the 1st 32-bit data to be programmed. - */ - -#define EFUSE_PGM_DATA_1 0xffffffff -#define EFUSE_PGM_DATA_1_M (EFUSE_PGM_DATA_1_V << EFUSE_PGM_DATA_1_S) -#define EFUSE_PGM_DATA_1_V 0xffffffff -#define EFUSE_PGM_DATA_1_S 0 - -/* EFUSE_PGM_DATA2_REG register - * Register 2 that stores data to be programmed. - */ - -#define EFUSE_PGM_DATA2_REG (DR_REG_EFUSE_BASE + 0x8) - -/* EFUSE_PGM_DATA_2 : R/W; bitpos: [31:0]; default: 0; - * The content of the 2nd 32-bit data to be programmed. - */ - -#define EFUSE_PGM_DATA_2 0xffffffff -#define EFUSE_PGM_DATA_2_M (EFUSE_PGM_DATA_2_V << EFUSE_PGM_DATA_2_S) -#define EFUSE_PGM_DATA_2_V 0xffffffff -#define EFUSE_PGM_DATA_2_S 0 - -/* EFUSE_PGM_DATA3_REG register - * Register 3 that stores data to be programmed. - */ - -#define EFUSE_PGM_DATA3_REG (DR_REG_EFUSE_BASE + 0xc) - -/* EFUSE_PGM_DATA_3 : R/W; bitpos: [31:0]; default: 0; - * The content of the 3rd 32-bit data to be programmed. - */ - -#define EFUSE_PGM_DATA_3 0xffffffff -#define EFUSE_PGM_DATA_3_M (EFUSE_PGM_DATA_3_V << EFUSE_PGM_DATA_3_S) -#define EFUSE_PGM_DATA_3_V 0xffffffff -#define EFUSE_PGM_DATA_3_S 0 - -/* EFUSE_PGM_DATA4_REG register - * Register 4 that stores data to be programmed. - */ - -#define EFUSE_PGM_DATA4_REG (DR_REG_EFUSE_BASE + 0x10) - -/* EFUSE_PGM_DATA_4 : R/W; bitpos: [31:0]; default: 0; - * The content of the 4th 32-bit data to be programmed. - */ - -#define EFUSE_PGM_DATA_4 0xffffffff -#define EFUSE_PGM_DATA_4_M (EFUSE_PGM_DATA_4_V << EFUSE_PGM_DATA_4_S) -#define EFUSE_PGM_DATA_4_V 0xffffffff -#define EFUSE_PGM_DATA_4_S 0 - -/* EFUSE_PGM_DATA5_REG register - * Register 5 that stores data to be programmed. - */ - -#define EFUSE_PGM_DATA5_REG (DR_REG_EFUSE_BASE + 0x14) - -/* EFUSE_PGM_DATA_5 : R/W; bitpos: [31:0]; default: 0; - * The content of the 5th 32-bit data to be programmed. - */ - -#define EFUSE_PGM_DATA_5 0xffffffff -#define EFUSE_PGM_DATA_5_M (EFUSE_PGM_DATA_5_V << EFUSE_PGM_DATA_5_S) -#define EFUSE_PGM_DATA_5_V 0xffffffff -#define EFUSE_PGM_DATA_5_S 0 - -/* EFUSE_PGM_DATA6_REG register - * Register 6 that stores data to be programmed. - */ - -#define EFUSE_PGM_DATA6_REG (DR_REG_EFUSE_BASE + 0x18) - -/* EFUSE_PGM_DATA_6 : R/W; bitpos: [31:0]; default: 0; - * The content of the 6th 32-bit data to be programmed. - */ - -#define EFUSE_PGM_DATA_6 0xffffffff -#define EFUSE_PGM_DATA_6_M (EFUSE_PGM_DATA_6_V << EFUSE_PGM_DATA_6_S) -#define EFUSE_PGM_DATA_6_V 0xffffffff -#define EFUSE_PGM_DATA_6_S 0 - -/* EFUSE_PGM_DATA7_REG register - * Register 7 that stores data to be programmed. - */ - -#define EFUSE_PGM_DATA7_REG (DR_REG_EFUSE_BASE + 0x1c) - -/* EFUSE_PGM_DATA_7 : R/W; bitpos: [31:0]; default: 0; - * The content of the 7th 32-bit data to be programmed. - */ - -#define EFUSE_PGM_DATA_7 0xffffffff -#define EFUSE_PGM_DATA_7_M (EFUSE_PGM_DATA_7_V << EFUSE_PGM_DATA_7_S) -#define EFUSE_PGM_DATA_7_V 0xffffffff -#define EFUSE_PGM_DATA_7_S 0 - -/* EFUSE_PGM_CHECK_VALUE0_REG register - * Register 0 that stores the RS code to be programmed. - */ - -#define EFUSE_PGM_CHECK_VALUE0_REG (DR_REG_EFUSE_BASE + 0x20) - -/* EFUSE_PGM_RS_DATA_0 : R/W; bitpos: [31:0]; default: 0; - * The content of the 0th 32-bit RS code to be programmed. - */ - -#define EFUSE_PGM_RS_DATA_0 0xffffffff -#define EFUSE_PGM_RS_DATA_0_M (EFUSE_PGM_RS_DATA_0_V << EFUSE_PGM_RS_DATA_0_S) -#define EFUSE_PGM_RS_DATA_0_V 0xffffffff -#define EFUSE_PGM_RS_DATA_0_S 0 - -/* EFUSE_PGM_CHECK_VALUE1_REG register - * Register 1 that stores the RS code to be programmed. - */ - -#define EFUSE_PGM_CHECK_VALUE1_REG (DR_REG_EFUSE_BASE + 0x24) - -/* EFUSE_PGM_RS_DATA_1 : R/W; bitpos: [31:0]; default: 0; - * The content of the 1st 32-bit RS code to be programmed. - */ - -#define EFUSE_PGM_RS_DATA_1 0xffffffff -#define EFUSE_PGM_RS_DATA_1_M (EFUSE_PGM_RS_DATA_1_V << EFUSE_PGM_RS_DATA_1_S) -#define EFUSE_PGM_RS_DATA_1_V 0xffffffff -#define EFUSE_PGM_RS_DATA_1_S 0 - -/* EFUSE_PGM_CHECK_VALUE2_REG register - * Register 2 that stores the RS code to be programmed. - */ - -#define EFUSE_PGM_CHECK_VALUE2_REG (DR_REG_EFUSE_BASE + 0x28) - -/* EFUSE_PGM_RS_DATA_2 : R/W; bitpos: [31:0]; default: 0; - * The content of the 2nd 32-bit RS code to be programmed. - */ - -#define EFUSE_PGM_RS_DATA_2 0xffffffff -#define EFUSE_PGM_RS_DATA_2_M (EFUSE_PGM_RS_DATA_2_V << EFUSE_PGM_RS_DATA_2_S) -#define EFUSE_PGM_RS_DATA_2_V 0xffffffff -#define EFUSE_PGM_RS_DATA_2_S 0 - -/* EFUSE_RD_WR_DIS_REG register - * BLOCK0 data register 0. - */ - -#define EFUSE_RD_WR_DIS_REG (DR_REG_EFUSE_BASE + 0x2c) - -/* EFUSE_WR_DIS : RO; bitpos: [31:0]; default: 0; - * Disable programming of individual eFuses. - */ - -#define EFUSE_WR_DIS 0xffffffff -#define EFUSE_WR_DIS_M (EFUSE_WR_DIS_V << EFUSE_WR_DIS_S) -#define EFUSE_WR_DIS_V 0xffffffff -#define EFUSE_WR_DIS_S 0 - -/* EFUSE_RD_REPEAT_DATA0_REG register - * BLOCK0 data register 1. - */ - -#define EFUSE_RD_REPEAT_DATA0_REG (DR_REG_EFUSE_BASE + 0x30) - -/* EFUSE_VDD_SPI_DREFH : RO; bitpos: [31:30]; default: 0; - * SPI regulator high voltage reference. - */ - -#define EFUSE_VDD_SPI_DREFH 0x00000003 -#define EFUSE_VDD_SPI_DREFH_M (EFUSE_VDD_SPI_DREFH_V << EFUSE_VDD_SPI_DREFH_S) -#define EFUSE_VDD_SPI_DREFH_V 0x00000003 -#define EFUSE_VDD_SPI_DREFH_S 30 - -/* EFUSE_VDD_SPI_MODECURLIM : RO; bitpos: [29]; default: 0; - * SPI regulator switches current limit mode. - */ - -#define EFUSE_VDD_SPI_MODECURLIM (BIT(29)) -#define EFUSE_VDD_SPI_MODECURLIM_M (EFUSE_VDD_SPI_MODECURLIM_V << EFUSE_VDD_SPI_MODECURLIM_S) -#define EFUSE_VDD_SPI_MODECURLIM_V 0x00000001 -#define EFUSE_VDD_SPI_MODECURLIM_S 29 - -/* EFUSE_BTLC_GPIO_ENABLE : RO; bitpos: [28:27]; default: 0; - * Bluetooth GPIO signal output security level control. - */ - -#define EFUSE_BTLC_GPIO_ENABLE 0x00000003 -#define EFUSE_BTLC_GPIO_ENABLE_M (EFUSE_BTLC_GPIO_ENABLE_V << EFUSE_BTLC_GPIO_ENABLE_S) -#define EFUSE_BTLC_GPIO_ENABLE_V 0x00000003 -#define EFUSE_BTLC_GPIO_ENABLE_S 27 - -/* EFUSE_EXT_PHY_ENABLE : RO; bitpos: [26]; default: 0; - * Set this bit to enable external PHY. - */ - -#define EFUSE_EXT_PHY_ENABLE (BIT(26)) -#define EFUSE_EXT_PHY_ENABLE_M (EFUSE_EXT_PHY_ENABLE_V << EFUSE_EXT_PHY_ENABLE_S) -#define EFUSE_EXT_PHY_ENABLE_V 0x00000001 -#define EFUSE_EXT_PHY_ENABLE_S 26 - -/* EFUSE_USB_EXCHG_PINS : RO; bitpos: [25]; default: 0; - * Set this bit to exchange USB D+ and D- pins. - */ - -#define EFUSE_USB_EXCHG_PINS (BIT(25)) -#define EFUSE_USB_EXCHG_PINS_M (EFUSE_USB_EXCHG_PINS_V << EFUSE_USB_EXCHG_PINS_S) -#define EFUSE_USB_EXCHG_PINS_V 0x00000001 -#define EFUSE_USB_EXCHG_PINS_S 25 - -/* EFUSE_USB_DREFL : RO; bitpos: [24:23]; default: 0; - * Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of - * 80 mV, stored in eFuse. - */ - -#define EFUSE_USB_DREFL 0x00000003 -#define EFUSE_USB_DREFL_M (EFUSE_USB_DREFL_V << EFUSE_USB_DREFL_S) -#define EFUSE_USB_DREFL_V 0x00000003 -#define EFUSE_USB_DREFL_S 23 - -/* EFUSE_USB_DREFH : RO; bitpos: [22:21]; default: 0; - * Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 - * mV, stored in eFuse. - */ - -#define EFUSE_USB_DREFH 0x00000003 -#define EFUSE_USB_DREFH_M (EFUSE_USB_DREFH_V << EFUSE_USB_DREFH_S) -#define EFUSE_USB_DREFH_V 0x00000003 -#define EFUSE_USB_DREFH_S 21 - -/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO; bitpos: [20]; default: 0; - * Set this bit to disable flash encryption when in download boot modes. - */ - -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT (BIT(20)) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V 0x00000001 -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S 20 - -/* EFUSE_DIS_PAD_JTAG : RO; bitpos: [19]; default: 0; - * Set this bit to disable JTAG in the hard way. JTAG is disabled - * permanently. - */ - -#define EFUSE_DIS_PAD_JTAG (BIT(19)) -#define EFUSE_DIS_PAD_JTAG_M (EFUSE_DIS_PAD_JTAG_V << EFUSE_DIS_PAD_JTAG_S) -#define EFUSE_DIS_PAD_JTAG_V 0x00000001 -#define EFUSE_DIS_PAD_JTAG_S 19 - -/* EFUSE_SOFT_DIS_JTAG : RO; bitpos: [18:16]; default: 0; - * Set these bits to disable JTAG in the soft way (odd number 1 means - * disable ). JTAG can be enabled in HMAC module. - */ - -#define EFUSE_SOFT_DIS_JTAG 0x00000007 -#define EFUSE_SOFT_DIS_JTAG_M (EFUSE_SOFT_DIS_JTAG_V << EFUSE_SOFT_DIS_JTAG_S) -#define EFUSE_SOFT_DIS_JTAG_V 0x00000007 -#define EFUSE_SOFT_DIS_JTAG_S 16 - -/* EFUSE_DIS_APP_CPU : RO; bitpos: [15]; default: 0; - * Disable app cpu. - */ - -#define EFUSE_DIS_APP_CPU (BIT(15)) -#define EFUSE_DIS_APP_CPU_M (EFUSE_DIS_APP_CPU_V << EFUSE_DIS_APP_CPU_S) -#define EFUSE_DIS_APP_CPU_V 0x00000001 -#define EFUSE_DIS_APP_CPU_S 15 - -/* EFUSE_DIS_CAN : RO; bitpos: [14]; default: 0; - * Set this bit to disable CAN function. - */ - -#define EFUSE_DIS_CAN (BIT(14)) -#define EFUSE_DIS_CAN_M (EFUSE_DIS_CAN_V << EFUSE_DIS_CAN_S) -#define EFUSE_DIS_CAN_V 0x00000001 -#define EFUSE_DIS_CAN_S 14 - -/* EFUSE_DIS_USB : RO; bitpos: [13]; default: 0; - * Set this bit to disable USB function. - */ - -#define EFUSE_DIS_USB (BIT(13)) -#define EFUSE_DIS_USB_M (EFUSE_DIS_USB_V << EFUSE_DIS_USB_S) -#define EFUSE_DIS_USB_V 0x00000001 -#define EFUSE_DIS_USB_S 13 - -/* EFUSE_DIS_FORCE_DOWNLOAD : RO; bitpos: [12]; default: 0; - * Set this bit to disable the function that forces chip into download mode. - */ - -#define EFUSE_DIS_FORCE_DOWNLOAD (BIT(12)) -#define EFUSE_DIS_FORCE_DOWNLOAD_M (EFUSE_DIS_FORCE_DOWNLOAD_V << EFUSE_DIS_FORCE_DOWNLOAD_S) -#define EFUSE_DIS_FORCE_DOWNLOAD_V 0x00000001 -#define EFUSE_DIS_FORCE_DOWNLOAD_S 12 - -/* EFUSE_DIS_DOWNLOAD_DCACHE : RO; bitpos: [11]; default: 0; - * Set this bit to disable Dcache in download mode ( boot_mode[3:0] is 0, 1, - * 2, 3, 6, 7). - */ - -#define EFUSE_DIS_DOWNLOAD_DCACHE (BIT(11)) -#define EFUSE_DIS_DOWNLOAD_DCACHE_M (EFUSE_DIS_DOWNLOAD_DCACHE_V << EFUSE_DIS_DOWNLOAD_DCACHE_S) -#define EFUSE_DIS_DOWNLOAD_DCACHE_V 0x00000001 -#define EFUSE_DIS_DOWNLOAD_DCACHE_S 11 - -/* EFUSE_DIS_DOWNLOAD_ICACHE : RO; bitpos: [10]; default: 0; - * Set this bit to disable Icache in download mode (boot_mode[3:0] is 0, 1, - * 2, 3, 6, 7). - */ - -#define EFUSE_DIS_DOWNLOAD_ICACHE (BIT(10)) -#define EFUSE_DIS_DOWNLOAD_ICACHE_M (EFUSE_DIS_DOWNLOAD_ICACHE_V << EFUSE_DIS_DOWNLOAD_ICACHE_S) -#define EFUSE_DIS_DOWNLOAD_ICACHE_V 0x00000001 -#define EFUSE_DIS_DOWNLOAD_ICACHE_S 10 - -/* EFUSE_DIS_DCACHE : RO; bitpos: [9]; default: 0; - * Set this bit to disable Dcache. - */ - -#define EFUSE_DIS_DCACHE (BIT(9)) -#define EFUSE_DIS_DCACHE_M (EFUSE_DIS_DCACHE_V << EFUSE_DIS_DCACHE_S) -#define EFUSE_DIS_DCACHE_V 0x00000001 -#define EFUSE_DIS_DCACHE_S 9 - -/* EFUSE_DIS_ICACHE : RO; bitpos: [8]; default: 0; - * Set this bit to disable Icache. - */ - -#define EFUSE_DIS_ICACHE (BIT(8)) -#define EFUSE_DIS_ICACHE_M (EFUSE_DIS_ICACHE_V << EFUSE_DIS_ICACHE_S) -#define EFUSE_DIS_ICACHE_V 0x00000001 -#define EFUSE_DIS_ICACHE_S 8 - -/* EFUSE_DIS_RTC_RAM_BOOT : RO; bitpos: [7]; default: 0; - * Set this bit to disable boot from RTC RAM. - */ - -#define EFUSE_DIS_RTC_RAM_BOOT (BIT(7)) -#define EFUSE_DIS_RTC_RAM_BOOT_M (EFUSE_DIS_RTC_RAM_BOOT_V << EFUSE_DIS_RTC_RAM_BOOT_S) -#define EFUSE_DIS_RTC_RAM_BOOT_V 0x00000001 -#define EFUSE_DIS_RTC_RAM_BOOT_S 7 - -/* EFUSE_RD_DIS : RO; bitpos: [6:0]; default: 0; - * Set this bit to disable reading from BlOCK4-10. - */ - -#define EFUSE_RD_DIS 0x0000007f -#define EFUSE_RD_DIS_M (EFUSE_RD_DIS_V << EFUSE_RD_DIS_S) -#define EFUSE_RD_DIS_V 0x0000007f -#define EFUSE_RD_DIS_S 0 - -/* EFUSE_RD_REPEAT_DATA1_REG register - * BLOCK0 data register 2. - */ - -#define EFUSE_RD_REPEAT_DATA1_REG (DR_REG_EFUSE_BASE + 0x34) - -/* EFUSE_KEY_PURPOSE_1 : RO; bitpos: [31:28]; default: 0; - * Purpose of Key1. - */ - -#define EFUSE_KEY_PURPOSE_1 0x0000000f -#define EFUSE_KEY_PURPOSE_1_M (EFUSE_KEY_PURPOSE_1_V << EFUSE_KEY_PURPOSE_1_S) -#define EFUSE_KEY_PURPOSE_1_V 0x0000000f -#define EFUSE_KEY_PURPOSE_1_S 28 - -/* EFUSE_KEY_PURPOSE_0 : RO; bitpos: [27:24]; default: 0; - * Purpose of Key0. - */ - -#define EFUSE_KEY_PURPOSE_0 0x0000000f -#define EFUSE_KEY_PURPOSE_0_M (EFUSE_KEY_PURPOSE_0_V << EFUSE_KEY_PURPOSE_0_S) -#define EFUSE_KEY_PURPOSE_0_V 0x0000000f -#define EFUSE_KEY_PURPOSE_0_S 24 - -/* EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO; bitpos: [23]; default: 0; - * Set this bit to enable revoking third secure boot key. - */ - -#define EFUSE_SECURE_BOOT_KEY_REVOKE2 (BIT(23)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_S) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V 0x00000001 -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S 23 - -/* EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO; bitpos: [22]; default: 0; - * Set this bit to enable revoking second secure boot key. - */ - -#define EFUSE_SECURE_BOOT_KEY_REVOKE1 (BIT(22)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_S) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V 0x00000001 -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S 22 - -/* EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO; bitpos: [21]; default: 0; - * Set this bit to enable revoking first secure boot key. - */ - -#define EFUSE_SECURE_BOOT_KEY_REVOKE0 (BIT(21)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_S) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V 0x00000001 -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S 21 - -/* EFUSE_SPI_BOOT_CRYPT_CNT : RO; bitpos: [20:18]; default: 0; - * Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. - * even number of 1: disable. - */ - -#define EFUSE_SPI_BOOT_CRYPT_CNT 0x00000007 -#define EFUSE_SPI_BOOT_CRYPT_CNT_M (EFUSE_SPI_BOOT_CRYPT_CNT_V << EFUSE_SPI_BOOT_CRYPT_CNT_S) -#define EFUSE_SPI_BOOT_CRYPT_CNT_V 0x00000007 -#define EFUSE_SPI_BOOT_CRYPT_CNT_S 18 - -/* EFUSE_WDT_DELAY_SEL : RO; bitpos: [17:16]; default: 0; - * Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: - * 40000. 1: 80000. 2: 160000. 3:320000. - */ - -#define EFUSE_WDT_DELAY_SEL 0x00000003 -#define EFUSE_WDT_DELAY_SEL_M (EFUSE_WDT_DELAY_SEL_V << EFUSE_WDT_DELAY_SEL_S) -#define EFUSE_WDT_DELAY_SEL_V 0x00000003 -#define EFUSE_WDT_DELAY_SEL_S 16 - -/* EFUSE_VDD_SPI_DCAP : RO; bitpos: [15:14]; default: 0; - * Prevents SPI regulator from overshoot. - */ - -#define EFUSE_VDD_SPI_DCAP 0x00000003 -#define EFUSE_VDD_SPI_DCAP_M (EFUSE_VDD_SPI_DCAP_V << EFUSE_VDD_SPI_DCAP_S) -#define EFUSE_VDD_SPI_DCAP_V 0x00000003 -#define EFUSE_VDD_SPI_DCAP_S 14 - -/* EFUSE_VDD_SPI_INIT : RO; bitpos: [13:12]; default: 0; - * Adds resistor from LDO output to ground. 0: no resistance 1: 6 K 2: 4 K - * 3: 2 K. - */ - -#define EFUSE_VDD_SPI_INIT 0x00000003 -#define EFUSE_VDD_SPI_INIT_M (EFUSE_VDD_SPI_INIT_V << EFUSE_VDD_SPI_INIT_S) -#define EFUSE_VDD_SPI_INIT_V 0x00000003 -#define EFUSE_VDD_SPI_INIT_S 12 - -/* EFUSE_VDD_SPI_DCURLIM : RO; bitpos: [11:9]; default: 0; - * Tunes the current limit threshold of SPI regulator when tieh=0, about 800 - * mA/(8+d). - */ - -#define EFUSE_VDD_SPI_DCURLIM 0x00000007 -#define EFUSE_VDD_SPI_DCURLIM_M (EFUSE_VDD_SPI_DCURLIM_V << EFUSE_VDD_SPI_DCURLIM_S) -#define EFUSE_VDD_SPI_DCURLIM_V 0x00000007 -#define EFUSE_VDD_SPI_DCURLIM_S 9 - -/* EFUSE_VDD_SPI_ENCURLIM : RO; bitpos: [8]; default: 0; - * Set SPI regulator to 1 to enable output current limit. - */ - -#define EFUSE_VDD_SPI_ENCURLIM (BIT(8)) -#define EFUSE_VDD_SPI_ENCURLIM_M (EFUSE_VDD_SPI_ENCURLIM_V << EFUSE_VDD_SPI_ENCURLIM_S) -#define EFUSE_VDD_SPI_ENCURLIM_V 0x00000001 -#define EFUSE_VDD_SPI_ENCURLIM_S 8 - -/* EFUSE_VDD_SPI_EN_INIT : RO; bitpos: [7]; default: 0; - * Set SPI regulator to 0 to configure init[1:0]=0. - */ - -#define EFUSE_VDD_SPI_EN_INIT (BIT(7)) -#define EFUSE_VDD_SPI_EN_INIT_M (EFUSE_VDD_SPI_EN_INIT_V << EFUSE_VDD_SPI_EN_INIT_S) -#define EFUSE_VDD_SPI_EN_INIT_V 0x00000001 -#define EFUSE_VDD_SPI_EN_INIT_S 7 - -/* EFUSE_VDD_SPI_FORCE : RO; bitpos: [6]; default: 0; - * Set this bit and force to use the configuration of eFuse to configure - * VDD_SPI. - */ - -#define EFUSE_VDD_SPI_FORCE (BIT(6)) -#define EFUSE_VDD_SPI_FORCE_M (EFUSE_VDD_SPI_FORCE_V << EFUSE_VDD_SPI_FORCE_S) -#define EFUSE_VDD_SPI_FORCE_V 0x00000001 -#define EFUSE_VDD_SPI_FORCE_S 6 - -/* EFUSE_VDD_SPI_TIEH : RO; bitpos: [5]; default: 0; - * SPI regulator output is short connected to VDD3P3_RTC_IO. - */ - -#define EFUSE_VDD_SPI_TIEH (BIT(5)) -#define EFUSE_VDD_SPI_TIEH_M (EFUSE_VDD_SPI_TIEH_V << EFUSE_VDD_SPI_TIEH_S) -#define EFUSE_VDD_SPI_TIEH_V 0x00000001 -#define EFUSE_VDD_SPI_TIEH_S 5 - -/* EFUSE_VDD_SPI_XPD : RO; bitpos: [4]; default: 0; - * SPI regulator power up signal. - */ - -#define EFUSE_VDD_SPI_XPD (BIT(4)) -#define EFUSE_VDD_SPI_XPD_M (EFUSE_VDD_SPI_XPD_V << EFUSE_VDD_SPI_XPD_S) -#define EFUSE_VDD_SPI_XPD_V 0x00000001 -#define EFUSE_VDD_SPI_XPD_S 4 - -/* EFUSE_VDD_SPI_DREFL : RO; bitpos: [3:2]; default: 0; - * SPI regulator low voltage reference. - */ - -#define EFUSE_VDD_SPI_DREFL 0x00000003 -#define EFUSE_VDD_SPI_DREFL_M (EFUSE_VDD_SPI_DREFL_V << EFUSE_VDD_SPI_DREFL_S) -#define EFUSE_VDD_SPI_DREFL_V 0x00000003 -#define EFUSE_VDD_SPI_DREFL_S 2 - -/* EFUSE_VDD_SPI_DREFM : RO; bitpos: [1:0]; default: 0; - * SPI regulator medium voltage reference. - */ - -#define EFUSE_VDD_SPI_DREFM 0x00000003 -#define EFUSE_VDD_SPI_DREFM_M (EFUSE_VDD_SPI_DREFM_V << EFUSE_VDD_SPI_DREFM_S) -#define EFUSE_VDD_SPI_DREFM_V 0x00000003 -#define EFUSE_VDD_SPI_DREFM_S 0 - -/* EFUSE_RD_REPEAT_DATA2_REG register - * BLOCK0 data register 3. - */ - -#define EFUSE_RD_REPEAT_DATA2_REG (DR_REG_EFUSE_BASE + 0x38) - -/* EFUSE_FLASH_TPUW : RO; bitpos: [31:28]; default: 0; - * Configures flash waiting time after power-up, in unit of ms. If the value - * is less than 15, the waiting time is the configurable value. Otherwise, - * the waiting time is twice the configurable value. - */ - -#define EFUSE_FLASH_TPUW 0x0000000f -#define EFUSE_FLASH_TPUW_M (EFUSE_FLASH_TPUW_V << EFUSE_FLASH_TPUW_S) -#define EFUSE_FLASH_TPUW_V 0x0000000f -#define EFUSE_FLASH_TPUW_S 28 - -/* EFUSE_POWER_GLITCH_DSENSE : RO; bitpos: [27:26]; default: 0; - * Sample delay configuration of power glitch. - */ - -#define EFUSE_POWER_GLITCH_DSENSE 0x00000003 -#define EFUSE_POWER_GLITCH_DSENSE_M (EFUSE_POWER_GLITCH_DSENSE_V << EFUSE_POWER_GLITCH_DSENSE_S) -#define EFUSE_POWER_GLITCH_DSENSE_V 0x00000003 -#define EFUSE_POWER_GLITCH_DSENSE_S 26 - -/* EFUSE_USB_PHY_SEL : RO; bitpos: [25]; default: 0; - * This bit is used to switch internal PHY and external PHY for USB OTG and - * USB Device. 0: internal PHY is assigned to USB Device while external PHY - * is assigned to USB OTG. 1: internal PHY is assigned to USB OTG while - * external PHY is assigned to USB Device. - */ - -#define EFUSE_USB_PHY_SEL (BIT(25)) -#define EFUSE_USB_PHY_SEL_M (EFUSE_USB_PHY_SEL_V << EFUSE_USB_PHY_SEL_S) -#define EFUSE_USB_PHY_SEL_V 0x00000001 -#define EFUSE_USB_PHY_SEL_S 25 - -/* EFUSE_STRAP_JTAG_SEL : RO; bitpos: [24]; default: 0; - * Set this bit to enable selection between usb_to_jtag and pad_to_jtag - * through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag - * are equal to 0. - */ - -#define EFUSE_STRAP_JTAG_SEL (BIT(24)) -#define EFUSE_STRAP_JTAG_SEL_M (EFUSE_STRAP_JTAG_SEL_V << EFUSE_STRAP_JTAG_SEL_S) -#define EFUSE_STRAP_JTAG_SEL_V 0x00000001 -#define EFUSE_STRAP_JTAG_SEL_S 24 - -/* EFUSE_DIS_USB_DEVICE : RO; bitpos: [23]; default: 0; - * Set this bit to disable usb device. - */ - -#define EFUSE_DIS_USB_DEVICE (BIT(23)) -#define EFUSE_DIS_USB_DEVICE_M (EFUSE_DIS_USB_DEVICE_V << EFUSE_DIS_USB_DEVICE_S) -#define EFUSE_DIS_USB_DEVICE_V 0x00000001 -#define EFUSE_DIS_USB_DEVICE_S 23 - -/* EFUSE_DIS_USB_JTAG : RO; bitpos: [22]; default: 0; - * Set this bit to disable function of usb switch to jtag in module of usb - * device. - */ - -#define EFUSE_DIS_USB_JTAG (BIT(22)) -#define EFUSE_DIS_USB_JTAG_M (EFUSE_DIS_USB_JTAG_V << EFUSE_DIS_USB_JTAG_S) -#define EFUSE_DIS_USB_JTAG_V 0x00000001 -#define EFUSE_DIS_USB_JTAG_S 22 - -/* EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO; bitpos: [21]; default: 0; - * Set this bit to enable revoking aggressive secure boot. - */ - -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE (BIT(21)) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V 0x00000001 -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S 21 - -/* EFUSE_SECURE_BOOT_EN : RO; bitpos: [20]; default: 0; - * Set this bit to enable secure boot. - */ - -#define EFUSE_SECURE_BOOT_EN (BIT(20)) -#define EFUSE_SECURE_BOOT_EN_M (EFUSE_SECURE_BOOT_EN_V << EFUSE_SECURE_BOOT_EN_S) -#define EFUSE_SECURE_BOOT_EN_V 0x00000001 -#define EFUSE_SECURE_BOOT_EN_S 20 - -/* EFUSE_RPT4_RESERVED0 : RO; bitpos: [19:16]; default: 0; - * Reserved (used for four backups method). - */ - -#define EFUSE_RPT4_RESERVED0 0x0000000f -#define EFUSE_RPT4_RESERVED0_M (EFUSE_RPT4_RESERVED0_V << EFUSE_RPT4_RESERVED0_S) -#define EFUSE_RPT4_RESERVED0_V 0x0000000f -#define EFUSE_RPT4_RESERVED0_S 16 - -/* EFUSE_KEY_PURPOSE_5 : RO; bitpos: [15:12]; default: 0; - * Purpose of Key5. - */ - -#define EFUSE_KEY_PURPOSE_5 0x0000000f -#define EFUSE_KEY_PURPOSE_5_M (EFUSE_KEY_PURPOSE_5_V << EFUSE_KEY_PURPOSE_5_S) -#define EFUSE_KEY_PURPOSE_5_V 0x0000000f -#define EFUSE_KEY_PURPOSE_5_S 12 - -/* EFUSE_KEY_PURPOSE_4 : RO; bitpos: [11:8]; default: 0; - * Purpose of Key4. - */ - -#define EFUSE_KEY_PURPOSE_4 0x0000000f -#define EFUSE_KEY_PURPOSE_4_M (EFUSE_KEY_PURPOSE_4_V << EFUSE_KEY_PURPOSE_4_S) -#define EFUSE_KEY_PURPOSE_4_V 0x0000000f -#define EFUSE_KEY_PURPOSE_4_S 8 - -/* EFUSE_KEY_PURPOSE_3 : RO; bitpos: [7:4]; default: 0; - * Purpose of Key3. - */ - -#define EFUSE_KEY_PURPOSE_3 0x0000000f -#define EFUSE_KEY_PURPOSE_3_M (EFUSE_KEY_PURPOSE_3_V << EFUSE_KEY_PURPOSE_3_S) -#define EFUSE_KEY_PURPOSE_3_V 0x0000000f -#define EFUSE_KEY_PURPOSE_3_S 4 - -/* EFUSE_KEY_PURPOSE_2 : RO; bitpos: [3:0]; default: 0; - * Purpose of Key2. - */ - -#define EFUSE_KEY_PURPOSE_2 0x0000000f -#define EFUSE_KEY_PURPOSE_2_M (EFUSE_KEY_PURPOSE_2_V << EFUSE_KEY_PURPOSE_2_S) -#define EFUSE_KEY_PURPOSE_2_V 0x0000000f -#define EFUSE_KEY_PURPOSE_2_S 0 - -/* EFUSE_RD_REPEAT_DATA3_REG register - * BLOCK0 data register 4. - */ - -#define EFUSE_RD_REPEAT_DATA3_REG (DR_REG_EFUSE_BASE + 0x3c) - -/* EFUSE_RPT4_RESERVED1 : RO; bitpos: [31]; default: 0; - * Reserved (used for four backups method). - */ - -#define EFUSE_RPT4_RESERVED1 (BIT(31)) -#define EFUSE_RPT4_RESERVED1_M (EFUSE_RPT4_RESERVED1_V << EFUSE_RPT4_RESERVED1_S) -#define EFUSE_RPT4_RESERVED1_V 0x00000001 -#define EFUSE_RPT4_RESERVED1_S 31 - -/* EFUSE_POWERGLITCH_EN : RO; bitpos: [30]; default: 0; - * Set this bit to enable power glitch function. - */ - -#define EFUSE_POWERGLITCH_EN (BIT(30)) -#define EFUSE_POWERGLITCH_EN_M (EFUSE_POWERGLITCH_EN_V << EFUSE_POWERGLITCH_EN_S) -#define EFUSE_POWERGLITCH_EN_V 0x00000001 -#define EFUSE_POWERGLITCH_EN_S 30 - -/* EFUSE_SECURE_VERSION : RO; bitpos: [29:14]; default: 0; - * Secure version (used by ESP-IDF anti-rollback feature). - */ - -#define EFUSE_SECURE_VERSION 0x0000ffff -#define EFUSE_SECURE_VERSION_M (EFUSE_SECURE_VERSION_V << EFUSE_SECURE_VERSION_S) -#define EFUSE_SECURE_VERSION_V 0x0000ffff -#define EFUSE_SECURE_VERSION_S 14 - -/* EFUSE_FORCE_SEND_RESUME : RO; bitpos: [13]; default: 0; - * Set this bit to force ROM code to send a resume command during SPI boot. - */ - -#define EFUSE_FORCE_SEND_RESUME (BIT(13)) -#define EFUSE_FORCE_SEND_RESUME_M (EFUSE_FORCE_SEND_RESUME_V << EFUSE_FORCE_SEND_RESUME_S) -#define EFUSE_FORCE_SEND_RESUME_V 0x00000001 -#define EFUSE_FORCE_SEND_RESUME_S 13 - -/* EFUSE_FLASH_ECC_EN : RO; bitpos: [12]; default: 0; - * Set 1 to enable ECC for flash boot. - */ - -#define EFUSE_FLASH_ECC_EN (BIT(12)) -#define EFUSE_FLASH_ECC_EN_M (EFUSE_FLASH_ECC_EN_V << EFUSE_FLASH_ECC_EN_S) -#define EFUSE_FLASH_ECC_EN_V 0x00000001 -#define EFUSE_FLASH_ECC_EN_S 12 - -/* EFUSE_FLASH_PAGE_SIZE : RO; bitpos: [11:10]; default: 0; - * Set Flash page size. - */ - -#define EFUSE_FLASH_PAGE_SIZE 0x00000003 -#define EFUSE_FLASH_PAGE_SIZE_M (EFUSE_FLASH_PAGE_SIZE_V << EFUSE_FLASH_PAGE_SIZE_S) -#define EFUSE_FLASH_PAGE_SIZE_V 0x00000003 -#define EFUSE_FLASH_PAGE_SIZE_S 10 - -/* EFUSE_FLASH_TYPE : RO; bitpos: [9]; default: 0; - * Set the maximum lines of SPI flash. 0: four lines. 1: eight lines. - */ - -#define EFUSE_FLASH_TYPE (BIT(9)) -#define EFUSE_FLASH_TYPE_M (EFUSE_FLASH_TYPE_V << EFUSE_FLASH_TYPE_S) -#define EFUSE_FLASH_TYPE_V 0x00000001 -#define EFUSE_FLASH_TYPE_S 9 - -/* EFUSE_PIN_POWER_SELECTION : RO; bitpos: [8]; default: 0; - * GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU. 1: - * VDD_SPI. - */ - -#define EFUSE_PIN_POWER_SELECTION (BIT(8)) -#define EFUSE_PIN_POWER_SELECTION_M (EFUSE_PIN_POWER_SELECTION_V << EFUSE_PIN_POWER_SELECTION_S) -#define EFUSE_PIN_POWER_SELECTION_V 0x00000001 -#define EFUSE_PIN_POWER_SELECTION_S 8 - -/* EFUSE_UART_PRINT_CONTROL : RO; bitpos: [7:6]; default: 0; - * Set the default UARTboot message output mode. 00: Enabled. 01: Enabled - * when GPIO8 is low at reset. 10: Enabled when GPIO8 is high at reset. - * 11:disabled. - */ - -#define EFUSE_UART_PRINT_CONTROL 0x00000003 -#define EFUSE_UART_PRINT_CONTROL_M (EFUSE_UART_PRINT_CONTROL_V << EFUSE_UART_PRINT_CONTROL_S) -#define EFUSE_UART_PRINT_CONTROL_V 0x00000003 -#define EFUSE_UART_PRINT_CONTROL_S 6 - -/* EFUSE_ENABLE_SECURITY_DOWNLOAD : RO; bitpos: [5]; default: 0; - * Set this bit to enable secure UART download mode. - */ - -#define EFUSE_ENABLE_SECURITY_DOWNLOAD (BIT(5)) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_S) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V 0x00000001 -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S 5 - -/* EFUSE_DIS_USB_DOWNLOAD_MODE : RO; bitpos: [4]; default: 0; - * Set this bit to disable UART download mode through USB. - */ - -#define EFUSE_DIS_USB_DOWNLOAD_MODE (BIT(4)) -#define EFUSE_DIS_USB_DOWNLOAD_MODE_M (EFUSE_DIS_USB_DOWNLOAD_MODE_V << EFUSE_DIS_USB_DOWNLOAD_MODE_S) -#define EFUSE_DIS_USB_DOWNLOAD_MODE_V 0x00000001 -#define EFUSE_DIS_USB_DOWNLOAD_MODE_S 4 - -/* EFUSE_FLASH_ECC_MODE : RO; bitpos: [3]; default: 0; - * Set ECC mode in ROM, 0: ROM would Enable Flash ECC 16to18 byte mode. - * 1:ROM would use 16to17 byte mode. - */ - -#define EFUSE_FLASH_ECC_MODE (BIT(3)) -#define EFUSE_FLASH_ECC_MODE_M (EFUSE_FLASH_ECC_MODE_V << EFUSE_FLASH_ECC_MODE_S) -#define EFUSE_FLASH_ECC_MODE_V 0x00000001 -#define EFUSE_FLASH_ECC_MODE_S 3 - -/* EFUSE_UART_PRINT_CHANNEL : RO; bitpos: [2]; default: 0; - * Selects the default UART print channel. 0: UART0. 1: UART1. - */ - -#define EFUSE_UART_PRINT_CHANNEL (BIT(2)) -#define EFUSE_UART_PRINT_CHANNEL_M (EFUSE_UART_PRINT_CHANNEL_V << EFUSE_UART_PRINT_CHANNEL_S) -#define EFUSE_UART_PRINT_CHANNEL_V 0x00000001 -#define EFUSE_UART_PRINT_CHANNEL_S 2 - -/* EFUSE_DIS_LEGACY_SPI_BOOT : RO; bitpos: [1]; default: 0; - * Set this bit to disable Legacy SPI boot mode (boot_mode[3:0] = 4). - */ - -#define EFUSE_DIS_LEGACY_SPI_BOOT (BIT(1)) -#define EFUSE_DIS_LEGACY_SPI_BOOT_M (EFUSE_DIS_LEGACY_SPI_BOOT_V << EFUSE_DIS_LEGACY_SPI_BOOT_S) -#define EFUSE_DIS_LEGACY_SPI_BOOT_V 0x00000001 -#define EFUSE_DIS_LEGACY_SPI_BOOT_S 1 - -/* EFUSE_DIS_DOWNLOAD_MODE : RO; bitpos: [0]; default: 0; - * Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 3, 6, 7). - */ - -#define EFUSE_DIS_DOWNLOAD_MODE (BIT(0)) -#define EFUSE_DIS_DOWNLOAD_MODE_M (EFUSE_DIS_DOWNLOAD_MODE_V << EFUSE_DIS_DOWNLOAD_MODE_S) -#define EFUSE_DIS_DOWNLOAD_MODE_V 0x00000001 -#define EFUSE_DIS_DOWNLOAD_MODE_S 0 - -/* EFUSE_RD_REPEAT_DATA4_REG register - * BLOCK0 data register 5. - */ - -#define EFUSE_RD_REPEAT_DATA4_REG (DR_REG_EFUSE_BASE + 0x40) - -/* EFUSE_RPT4_RESERVED2 : RO; bitpos: [23:0]; default: 0; - * Reserved (used for four backups method). - */ - -#define EFUSE_RPT4_RESERVED2 0x00ffffff -#define EFUSE_RPT4_RESERVED2_M (EFUSE_RPT4_RESERVED2_V << EFUSE_RPT4_RESERVED2_S) -#define EFUSE_RPT4_RESERVED2_V 0x00ffffff -#define EFUSE_RPT4_RESERVED2_S 0 - -/* EFUSE_RD_MAC_SPI_SYS_0_REG register - * BLOCK1 data register 0. - */ - -#define EFUSE_RD_MAC_SPI_SYS_0_REG (DR_REG_EFUSE_BASE + 0x44) - -/* EFUSE_MAC_0 : RO; bitpos: [31:0]; default: 0; - * Stores the low 32 bits of MAC address. - */ - -#define EFUSE_MAC_0 0xffffffff -#define EFUSE_MAC_0_M (EFUSE_MAC_0_V << EFUSE_MAC_0_S) -#define EFUSE_MAC_0_V 0xffffffff -#define EFUSE_MAC_0_S 0 - -/* EFUSE_RD_MAC_SPI_SYS_1_REG register - * BLOCK1 data register 1. - */ - -#define EFUSE_RD_MAC_SPI_SYS_1_REG (DR_REG_EFUSE_BASE + 0x48) - -/* EFUSE_SPI_PAD_CONF_0 : RO; bitpos: [31:16]; default: 0; - * Stores the zeroth part of SPI_PAD_CONF. - */ - -#define EFUSE_SPI_PAD_CONF_0 0x0000ffff -#define EFUSE_SPI_PAD_CONF_0_M (EFUSE_SPI_PAD_CONF_0_V << EFUSE_SPI_PAD_CONF_0_S) -#define EFUSE_SPI_PAD_CONF_0_V 0x0000ffff -#define EFUSE_SPI_PAD_CONF_0_S 16 - -/* EFUSE_MAC_1 : RO; bitpos: [15:0]; default: 0; - * Stores the high 16 bits of MAC address. - */ - -#define EFUSE_MAC_1 0x0000ffff -#define EFUSE_MAC_1_M (EFUSE_MAC_1_V << EFUSE_MAC_1_S) -#define EFUSE_MAC_1_V 0x0000ffff -#define EFUSE_MAC_1_S 0 - -/* EFUSE_RD_MAC_SPI_SYS_2_REG register - * BLOCK1 data register 2. - */ - -#define EFUSE_RD_MAC_SPI_SYS_2_REG (DR_REG_EFUSE_BASE + 0x4c) - -/* EFUSE_SPI_PAD_CONF_1 : RO; bitpos: [31:0]; default: 0; - * Stores the first part of SPI_PAD_CONF. - */ - -#define EFUSE_SPI_PAD_CONF_1 0xffffffff -#define EFUSE_SPI_PAD_CONF_1_M (EFUSE_SPI_PAD_CONF_1_V << EFUSE_SPI_PAD_CONF_1_S) -#define EFUSE_SPI_PAD_CONF_1_V 0xffffffff -#define EFUSE_SPI_PAD_CONF_1_S 0 - -/* EFUSE_RD_MAC_SPI_SYS_3_REG register - * BLOCK1 data register 3. - */ - -#define EFUSE_RD_MAC_SPI_SYS_3_REG (DR_REG_EFUSE_BASE + 0x50) - -/* EFUSE_SYS_DATA_PART0_0 : RO; bitpos: [31:18]; default: 0; - * Stores the fist 14 bits of the zeroth part of system data. - */ - -#define EFUSE_SYS_DATA_PART0_0 0x00003fff -#define EFUSE_SYS_DATA_PART0_0_M (EFUSE_SYS_DATA_PART0_0_V << EFUSE_SYS_DATA_PART0_0_S) -#define EFUSE_SYS_DATA_PART0_0_V 0x00003fff -#define EFUSE_SYS_DATA_PART0_0_S 18 - -/* EFUSE_SPI_PAD_CONF_2 : RO; bitpos: [17:0]; default: 0; - * Stores the second part of SPI_PAD_CONF. - */ - -#define EFUSE_SPI_PAD_CONF_2 0x0003ffff -#define EFUSE_SPI_PAD_CONF_2_M (EFUSE_SPI_PAD_CONF_2_V << EFUSE_SPI_PAD_CONF_2_S) -#define EFUSE_SPI_PAD_CONF_2_V 0x0003ffff -#define EFUSE_SPI_PAD_CONF_2_S 0 - -/* EFUSE_RD_MAC_SPI_SYS_4_REG register - * BLOCK1 data register 4. - */ - -#define EFUSE_RD_MAC_SPI_SYS_4_REG (DR_REG_EFUSE_BASE + 0x54) - -/* EFUSE_SYS_DATA_PART0_1 : RO; bitpos: [31:0]; default: 0; - * Stores the fist 32 bits of the zeroth part of system data. - */ - -#define EFUSE_SYS_DATA_PART0_1 0xffffffff -#define EFUSE_SYS_DATA_PART0_1_M (EFUSE_SYS_DATA_PART0_1_V << EFUSE_SYS_DATA_PART0_1_S) -#define EFUSE_SYS_DATA_PART0_1_V 0xffffffff -#define EFUSE_SYS_DATA_PART0_1_S 0 - -/* EFUSE_RD_MAC_SPI_SYS_5_REG register - * BLOCK1 data register 5. - */ - -#define EFUSE_RD_MAC_SPI_SYS_5_REG (DR_REG_EFUSE_BASE + 0x58) - -/* EFUSE_SYS_DATA_PART0_2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of the zeroth part of system data. - */ - -#define EFUSE_SYS_DATA_PART0_2 0xffffffff -#define EFUSE_SYS_DATA_PART0_2_M (EFUSE_SYS_DATA_PART0_2_V << EFUSE_SYS_DATA_PART0_2_S) -#define EFUSE_SYS_DATA_PART0_2_V 0xffffffff -#define EFUSE_SYS_DATA_PART0_2_S 0 - -/* EFUSE_RD_SYS_PART1_DATA0_REG register - * Register 0 of BLOCK2 (system). - */ - -#define EFUSE_RD_SYS_PART1_DATA0_REG (DR_REG_EFUSE_BASE + 0x5c) - -/* EFUSE_SYS_DATA_PART1_0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of the first part of system data. - */ - -#define EFUSE_SYS_DATA_PART1_0 0xffffffff -#define EFUSE_SYS_DATA_PART1_0_M (EFUSE_SYS_DATA_PART1_0_V << EFUSE_SYS_DATA_PART1_0_S) -#define EFUSE_SYS_DATA_PART1_0_V 0xffffffff -#define EFUSE_SYS_DATA_PART1_0_S 0 - -/* EFUSE_RD_SYS_PART1_DATA1_REG register - * Register 1 of BLOCK2 (system). - */ - -#define EFUSE_RD_SYS_PART1_DATA1_REG (DR_REG_EFUSE_BASE + 0x60) - -/* EFUSE_SYS_DATA_PART1_1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of the first part of system data. - */ - -#define EFUSE_SYS_DATA_PART1_1 0xffffffff -#define EFUSE_SYS_DATA_PART1_1_M (EFUSE_SYS_DATA_PART1_1_V << EFUSE_SYS_DATA_PART1_1_S) -#define EFUSE_SYS_DATA_PART1_1_V 0xffffffff -#define EFUSE_SYS_DATA_PART1_1_S 0 - -/* EFUSE_RD_SYS_PART1_DATA2_REG register - * Register 2 of BLOCK2 (system). - */ - -#define EFUSE_RD_SYS_PART1_DATA2_REG (DR_REG_EFUSE_BASE + 0x64) - -/* EFUSE_SYS_DATA_PART1_2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of the first part of system data. - */ - -#define EFUSE_SYS_DATA_PART1_2 0xffffffff -#define EFUSE_SYS_DATA_PART1_2_M (EFUSE_SYS_DATA_PART1_2_V << EFUSE_SYS_DATA_PART1_2_S) -#define EFUSE_SYS_DATA_PART1_2_V 0xffffffff -#define EFUSE_SYS_DATA_PART1_2_S 0 - -/* EFUSE_RD_SYS_PART1_DATA3_REG register - * Register 3 of BLOCK2 (system). - */ - -#define EFUSE_RD_SYS_PART1_DATA3_REG (DR_REG_EFUSE_BASE + 0x68) - -/* EFUSE_SYS_DATA_PART1_3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of the first part of system data. - */ - -#define EFUSE_SYS_DATA_PART1_3 0xffffffff -#define EFUSE_SYS_DATA_PART1_3_M (EFUSE_SYS_DATA_PART1_3_V << EFUSE_SYS_DATA_PART1_3_S) -#define EFUSE_SYS_DATA_PART1_3_V 0xffffffff -#define EFUSE_SYS_DATA_PART1_3_S 0 - -/* EFUSE_RD_SYS_PART1_DATA4_REG register - * Register 4 of BLOCK2 (system). - */ - -#define EFUSE_RD_SYS_PART1_DATA4_REG (DR_REG_EFUSE_BASE + 0x6c) - -/* EFUSE_SYS_DATA_PART1_4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of the first part of system data. - */ - -#define EFUSE_SYS_DATA_PART1_4 0xffffffff -#define EFUSE_SYS_DATA_PART1_4_M (EFUSE_SYS_DATA_PART1_4_V << EFUSE_SYS_DATA_PART1_4_S) -#define EFUSE_SYS_DATA_PART1_4_V 0xffffffff -#define EFUSE_SYS_DATA_PART1_4_S 0 - -/* EFUSE_RD_SYS_PART1_DATA5_REG register - * Register 5 of BLOCK2 (system). - */ - -#define EFUSE_RD_SYS_PART1_DATA5_REG (DR_REG_EFUSE_BASE + 0x70) - -/* EFUSE_SYS_DATA_PART1_5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of the first part of system data. - */ - -#define EFUSE_SYS_DATA_PART1_5 0xffffffff -#define EFUSE_SYS_DATA_PART1_5_M (EFUSE_SYS_DATA_PART1_5_V << EFUSE_SYS_DATA_PART1_5_S) -#define EFUSE_SYS_DATA_PART1_5_V 0xffffffff -#define EFUSE_SYS_DATA_PART1_5_S 0 - -/* EFUSE_RD_SYS_PART1_DATA6_REG register - * Register 6 of BLOCK2 (system). - */ - -#define EFUSE_RD_SYS_PART1_DATA6_REG (DR_REG_EFUSE_BASE + 0x74) - -/* EFUSE_SYS_DATA_PART1_6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of the first part of system data. - */ - -#define EFUSE_SYS_DATA_PART1_6 0xffffffff -#define EFUSE_SYS_DATA_PART1_6_M (EFUSE_SYS_DATA_PART1_6_V << EFUSE_SYS_DATA_PART1_6_S) -#define EFUSE_SYS_DATA_PART1_6_V 0xffffffff -#define EFUSE_SYS_DATA_PART1_6_S 0 - -/* EFUSE_RD_SYS_PART1_DATA7_REG register - * Register 7 of BLOCK2 (system). - */ - -#define EFUSE_RD_SYS_PART1_DATA7_REG (DR_REG_EFUSE_BASE + 0x78) - -/* EFUSE_SYS_DATA_PART1_7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of the first part of system data. - */ - -#define EFUSE_SYS_DATA_PART1_7 0xffffffff -#define EFUSE_SYS_DATA_PART1_7_M (EFUSE_SYS_DATA_PART1_7_V << EFUSE_SYS_DATA_PART1_7_S) -#define EFUSE_SYS_DATA_PART1_7_V 0xffffffff -#define EFUSE_SYS_DATA_PART1_7_S 0 - -/* EFUSE_RD_USR_DATA0_REG register - * Register 0 of BLOCK3 (user). - */ - -#define EFUSE_RD_USR_DATA0_REG (DR_REG_EFUSE_BASE + 0x7c) - -/* EFUSE_USR_DATA0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of BLOCK3 (user). - */ - -#define EFUSE_USR_DATA0 0xffffffff -#define EFUSE_USR_DATA0_M (EFUSE_USR_DATA0_V << EFUSE_USR_DATA0_S) -#define EFUSE_USR_DATA0_V 0xffffffff -#define EFUSE_USR_DATA0_S 0 - -/* EFUSE_RD_USR_DATA1_REG register - * Register 1 of BLOCK3 (user). - */ - -#define EFUSE_RD_USR_DATA1_REG (DR_REG_EFUSE_BASE + 0x80) - -/* EFUSE_USR_DATA1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of BLOCK3 (user). - */ - -#define EFUSE_USR_DATA1 0xffffffff -#define EFUSE_USR_DATA1_M (EFUSE_USR_DATA1_V << EFUSE_USR_DATA1_S) -#define EFUSE_USR_DATA1_V 0xffffffff -#define EFUSE_USR_DATA1_S 0 - -/* EFUSE_RD_USR_DATA2_REG register - * Register 2 of BLOCK3 (user). - */ - -#define EFUSE_RD_USR_DATA2_REG (DR_REG_EFUSE_BASE + 0x84) - -/* EFUSE_USR_DATA2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of BLOCK3 (user). - */ - -#define EFUSE_USR_DATA2 0xffffffff -#define EFUSE_USR_DATA2_M (EFUSE_USR_DATA2_V << EFUSE_USR_DATA2_S) -#define EFUSE_USR_DATA2_V 0xffffffff -#define EFUSE_USR_DATA2_S 0 - -/* EFUSE_RD_USR_DATA3_REG register - * Register 3 of BLOCK3 (user). - */ - -#define EFUSE_RD_USR_DATA3_REG (DR_REG_EFUSE_BASE + 0x88) - -/* EFUSE_USR_DATA3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of BLOCK3 (user). - */ - -#define EFUSE_USR_DATA3 0xffffffff -#define EFUSE_USR_DATA3_M (EFUSE_USR_DATA3_V << EFUSE_USR_DATA3_S) -#define EFUSE_USR_DATA3_V 0xffffffff -#define EFUSE_USR_DATA3_S 0 - -/* EFUSE_RD_USR_DATA4_REG register - * Register 4 of BLOCK3 (user). - */ - -#define EFUSE_RD_USR_DATA4_REG (DR_REG_EFUSE_BASE + 0x8c) - -/* EFUSE_USR_DATA4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of BLOCK3 (user). - */ - -#define EFUSE_USR_DATA4 0xffffffff -#define EFUSE_USR_DATA4_M (EFUSE_USR_DATA4_V << EFUSE_USR_DATA4_S) -#define EFUSE_USR_DATA4_V 0xffffffff -#define EFUSE_USR_DATA4_S 0 - -/* EFUSE_RD_USR_DATA5_REG register - * Register 5 of BLOCK3 (user). - */ - -#define EFUSE_RD_USR_DATA5_REG (DR_REG_EFUSE_BASE + 0x90) - -/* EFUSE_USR_DATA5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of BLOCK3 (user). - */ - -#define EFUSE_USR_DATA5 0xffffffff -#define EFUSE_USR_DATA5_M (EFUSE_USR_DATA5_V << EFUSE_USR_DATA5_S) -#define EFUSE_USR_DATA5_V 0xffffffff -#define EFUSE_USR_DATA5_S 0 - -/* EFUSE_RD_USR_DATA6_REG register - * Register 6 of BLOCK3 (user). - */ - -#define EFUSE_RD_USR_DATA6_REG (DR_REG_EFUSE_BASE + 0x94) - -/* EFUSE_USR_DATA6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of BLOCK3 (user). - */ - -#define EFUSE_USR_DATA6 0xffffffff -#define EFUSE_USR_DATA6_M (EFUSE_USR_DATA6_V << EFUSE_USR_DATA6_S) -#define EFUSE_USR_DATA6_V 0xffffffff -#define EFUSE_USR_DATA6_S 0 - -/* EFUSE_RD_USR_DATA7_REG register - * Register 7 of BLOCK3 (user). - */ - -#define EFUSE_RD_USR_DATA7_REG (DR_REG_EFUSE_BASE + 0x98) - -/* EFUSE_USR_DATA7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of BLOCK3 (user). - */ - -#define EFUSE_USR_DATA7 0xffffffff -#define EFUSE_USR_DATA7_M (EFUSE_USR_DATA7_V << EFUSE_USR_DATA7_S) -#define EFUSE_USR_DATA7_V 0xffffffff -#define EFUSE_USR_DATA7_S 0 - -/* EFUSE_RD_KEY0_DATA0_REG register - * Register 0 of BLOCK4 (KEY0). - */ - -#define EFUSE_RD_KEY0_DATA0_REG (DR_REG_EFUSE_BASE + 0x9c) - -/* EFUSE_KEY0_DATA0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY0. - */ - -#define EFUSE_KEY0_DATA0 0xffffffff -#define EFUSE_KEY0_DATA0_M (EFUSE_KEY0_DATA0_V << EFUSE_KEY0_DATA0_S) -#define EFUSE_KEY0_DATA0_V 0xffffffff -#define EFUSE_KEY0_DATA0_S 0 - -/* EFUSE_RD_KEY0_DATA1_REG register - * Register 1 of BLOCK4 (KEY0). - */ - -#define EFUSE_RD_KEY0_DATA1_REG (DR_REG_EFUSE_BASE + 0xa0) - -/* EFUSE_KEY0_DATA1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY0. - */ - -#define EFUSE_KEY0_DATA1 0xffffffff -#define EFUSE_KEY0_DATA1_M (EFUSE_KEY0_DATA1_V << EFUSE_KEY0_DATA1_S) -#define EFUSE_KEY0_DATA1_V 0xffffffff -#define EFUSE_KEY0_DATA1_S 0 - -/* EFUSE_RD_KEY0_DATA2_REG register - * Register 2 of BLOCK4 (KEY0). - */ - -#define EFUSE_RD_KEY0_DATA2_REG (DR_REG_EFUSE_BASE + 0xa4) - -/* EFUSE_KEY0_DATA2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY0. - */ - -#define EFUSE_KEY0_DATA2 0xffffffff -#define EFUSE_KEY0_DATA2_M (EFUSE_KEY0_DATA2_V << EFUSE_KEY0_DATA2_S) -#define EFUSE_KEY0_DATA2_V 0xffffffff -#define EFUSE_KEY0_DATA2_S 0 - -/* EFUSE_RD_KEY0_DATA3_REG register - * Register 3 of BLOCK4 (KEY0). - */ - -#define EFUSE_RD_KEY0_DATA3_REG (DR_REG_EFUSE_BASE + 0xa8) - -/* EFUSE_KEY0_DATA3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY0. - */ - -#define EFUSE_KEY0_DATA3 0xffffffff -#define EFUSE_KEY0_DATA3_M (EFUSE_KEY0_DATA3_V << EFUSE_KEY0_DATA3_S) -#define EFUSE_KEY0_DATA3_V 0xffffffff -#define EFUSE_KEY0_DATA3_S 0 - -/* EFUSE_RD_KEY0_DATA4_REG register - * Register 4 of BLOCK4 (KEY0). - */ - -#define EFUSE_RD_KEY0_DATA4_REG (DR_REG_EFUSE_BASE + 0xac) - -/* EFUSE_KEY0_DATA4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY0. - */ - -#define EFUSE_KEY0_DATA4 0xffffffff -#define EFUSE_KEY0_DATA4_M (EFUSE_KEY0_DATA4_V << EFUSE_KEY0_DATA4_S) -#define EFUSE_KEY0_DATA4_V 0xffffffff -#define EFUSE_KEY0_DATA4_S 0 - -/* EFUSE_RD_KEY0_DATA5_REG register - * Register 5 of BLOCK4 (KEY0). - */ - -#define EFUSE_RD_KEY0_DATA5_REG (DR_REG_EFUSE_BASE + 0xb0) - -/* EFUSE_KEY0_DATA5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY0. - */ - -#define EFUSE_KEY0_DATA5 0xffffffff -#define EFUSE_KEY0_DATA5_M (EFUSE_KEY0_DATA5_V << EFUSE_KEY0_DATA5_S) -#define EFUSE_KEY0_DATA5_V 0xffffffff -#define EFUSE_KEY0_DATA5_S 0 - -/* EFUSE_RD_KEY0_DATA6_REG register - * Register 6 of BLOCK4 (KEY0). - */ - -#define EFUSE_RD_KEY0_DATA6_REG (DR_REG_EFUSE_BASE + 0xb4) - -/* EFUSE_KEY0_DATA6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY0. - */ - -#define EFUSE_KEY0_DATA6 0xffffffff -#define EFUSE_KEY0_DATA6_M (EFUSE_KEY0_DATA6_V << EFUSE_KEY0_DATA6_S) -#define EFUSE_KEY0_DATA6_V 0xffffffff -#define EFUSE_KEY0_DATA6_S 0 - -/* EFUSE_RD_KEY0_DATA7_REG register - * Register 7 of BLOCK4 (KEY0). - */ - -#define EFUSE_RD_KEY0_DATA7_REG (DR_REG_EFUSE_BASE + 0xb8) - -/* EFUSE_KEY0_DATA7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY0. - */ - -#define EFUSE_KEY0_DATA7 0xffffffff -#define EFUSE_KEY0_DATA7_M (EFUSE_KEY0_DATA7_V << EFUSE_KEY0_DATA7_S) -#define EFUSE_KEY0_DATA7_V 0xffffffff -#define EFUSE_KEY0_DATA7_S 0 - -/* EFUSE_RD_KEY1_DATA0_REG register - * Register 0 of BLOCK5 (KEY1). - */ - -#define EFUSE_RD_KEY1_DATA0_REG (DR_REG_EFUSE_BASE + 0xbc) - -/* EFUSE_KEY1_DATA0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY1. - */ - -#define EFUSE_KEY1_DATA0 0xffffffff -#define EFUSE_KEY1_DATA0_M (EFUSE_KEY1_DATA0_V << EFUSE_KEY1_DATA0_S) -#define EFUSE_KEY1_DATA0_V 0xffffffff -#define EFUSE_KEY1_DATA0_S 0 - -/* EFUSE_RD_KEY1_DATA1_REG register - * Register 1 of BLOCK5 (KEY1). - */ - -#define EFUSE_RD_KEY1_DATA1_REG (DR_REG_EFUSE_BASE + 0xc0) - -/* EFUSE_KEY1_DATA1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY1. - */ - -#define EFUSE_KEY1_DATA1 0xffffffff -#define EFUSE_KEY1_DATA1_M (EFUSE_KEY1_DATA1_V << EFUSE_KEY1_DATA1_S) -#define EFUSE_KEY1_DATA1_V 0xffffffff -#define EFUSE_KEY1_DATA1_S 0 - -/* EFUSE_RD_KEY1_DATA2_REG register - * Register 2 of BLOCK5 (KEY1). - */ - -#define EFUSE_RD_KEY1_DATA2_REG (DR_REG_EFUSE_BASE + 0xc4) - -/* EFUSE_KEY1_DATA2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY1. - */ - -#define EFUSE_KEY1_DATA2 0xffffffff -#define EFUSE_KEY1_DATA2_M (EFUSE_KEY1_DATA2_V << EFUSE_KEY1_DATA2_S) -#define EFUSE_KEY1_DATA2_V 0xffffffff -#define EFUSE_KEY1_DATA2_S 0 - -/* EFUSE_RD_KEY1_DATA3_REG register - * Register 3 of BLOCK5 (KEY1). - */ - -#define EFUSE_RD_KEY1_DATA3_REG (DR_REG_EFUSE_BASE + 0xc8) - -/* EFUSE_KEY1_DATA3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY1. - */ - -#define EFUSE_KEY1_DATA3 0xffffffff -#define EFUSE_KEY1_DATA3_M (EFUSE_KEY1_DATA3_V << EFUSE_KEY1_DATA3_S) -#define EFUSE_KEY1_DATA3_V 0xffffffff -#define EFUSE_KEY1_DATA3_S 0 - -/* EFUSE_RD_KEY1_DATA4_REG register - * Register 4 of BLOCK5 (KEY1). - */ - -#define EFUSE_RD_KEY1_DATA4_REG (DR_REG_EFUSE_BASE + 0xcc) - -/* EFUSE_KEY1_DATA4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY1. - */ - -#define EFUSE_KEY1_DATA4 0xffffffff -#define EFUSE_KEY1_DATA4_M (EFUSE_KEY1_DATA4_V << EFUSE_KEY1_DATA4_S) -#define EFUSE_KEY1_DATA4_V 0xffffffff -#define EFUSE_KEY1_DATA4_S 0 - -/* EFUSE_RD_KEY1_DATA5_REG register - * Register 5 of BLOCK5 (KEY1). - */ - -#define EFUSE_RD_KEY1_DATA5_REG (DR_REG_EFUSE_BASE + 0xd0) - -/* EFUSE_KEY1_DATA5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY1. - */ - -#define EFUSE_KEY1_DATA5 0xffffffff -#define EFUSE_KEY1_DATA5_M (EFUSE_KEY1_DATA5_V << EFUSE_KEY1_DATA5_S) -#define EFUSE_KEY1_DATA5_V 0xffffffff -#define EFUSE_KEY1_DATA5_S 0 - -/* EFUSE_RD_KEY1_DATA6_REG register - * Register 6 of BLOCK5 (KEY1). - */ - -#define EFUSE_RD_KEY1_DATA6_REG (DR_REG_EFUSE_BASE + 0xd4) - -/* EFUSE_KEY1_DATA6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY1. - */ - -#define EFUSE_KEY1_DATA6 0xffffffff -#define EFUSE_KEY1_DATA6_M (EFUSE_KEY1_DATA6_V << EFUSE_KEY1_DATA6_S) -#define EFUSE_KEY1_DATA6_V 0xffffffff -#define EFUSE_KEY1_DATA6_S 0 - -/* EFUSE_RD_KEY1_DATA7_REG register - * Register 7 of BLOCK5 (KEY1). - */ - -#define EFUSE_RD_KEY1_DATA7_REG (DR_REG_EFUSE_BASE + 0xd8) - -/* EFUSE_KEY1_DATA7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY1. - */ - -#define EFUSE_KEY1_DATA7 0xffffffff -#define EFUSE_KEY1_DATA7_M (EFUSE_KEY1_DATA7_V << EFUSE_KEY1_DATA7_S) -#define EFUSE_KEY1_DATA7_V 0xffffffff -#define EFUSE_KEY1_DATA7_S 0 - -/* EFUSE_RD_KEY2_DATA0_REG register - * Register 0 of BLOCK6 (KEY2). - */ - -#define EFUSE_RD_KEY2_DATA0_REG (DR_REG_EFUSE_BASE + 0xdc) - -/* EFUSE_KEY2_DATA0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY2. - */ - -#define EFUSE_KEY2_DATA0 0xffffffff -#define EFUSE_KEY2_DATA0_M (EFUSE_KEY2_DATA0_V << EFUSE_KEY2_DATA0_S) -#define EFUSE_KEY2_DATA0_V 0xffffffff -#define EFUSE_KEY2_DATA0_S 0 - -/* EFUSE_RD_KEY2_DATA1_REG register - * Register 1 of BLOCK6 (KEY2). - */ - -#define EFUSE_RD_KEY2_DATA1_REG (DR_REG_EFUSE_BASE + 0xe0) - -/* EFUSE_KEY2_DATA1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY2. - */ - -#define EFUSE_KEY2_DATA1 0xffffffff -#define EFUSE_KEY2_DATA1_M (EFUSE_KEY2_DATA1_V << EFUSE_KEY2_DATA1_S) -#define EFUSE_KEY2_DATA1_V 0xffffffff -#define EFUSE_KEY2_DATA1_S 0 - -/* EFUSE_RD_KEY2_DATA2_REG register - * Register 2 of BLOCK6 (KEY2). - */ - -#define EFUSE_RD_KEY2_DATA2_REG (DR_REG_EFUSE_BASE + 0xe4) - -/* EFUSE_KEY2_DATA2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY2. - */ - -#define EFUSE_KEY2_DATA2 0xffffffff -#define EFUSE_KEY2_DATA2_M (EFUSE_KEY2_DATA2_V << EFUSE_KEY2_DATA2_S) -#define EFUSE_KEY2_DATA2_V 0xffffffff -#define EFUSE_KEY2_DATA2_S 0 - -/* EFUSE_RD_KEY2_DATA3_REG register - * Register 3 of BLOCK6 (KEY2). - */ - -#define EFUSE_RD_KEY2_DATA3_REG (DR_REG_EFUSE_BASE + 0xe8) - -/* EFUSE_KEY2_DATA3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY2. - */ - -#define EFUSE_KEY2_DATA3 0xffffffff -#define EFUSE_KEY2_DATA3_M (EFUSE_KEY2_DATA3_V << EFUSE_KEY2_DATA3_S) -#define EFUSE_KEY2_DATA3_V 0xffffffff -#define EFUSE_KEY2_DATA3_S 0 - -/* EFUSE_RD_KEY2_DATA4_REG register - * Register 4 of BLOCK6 (KEY2). - */ - -#define EFUSE_RD_KEY2_DATA4_REG (DR_REG_EFUSE_BASE + 0xec) - -/* EFUSE_KEY2_DATA4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY2. - */ - -#define EFUSE_KEY2_DATA4 0xffffffff -#define EFUSE_KEY2_DATA4_M (EFUSE_KEY2_DATA4_V << EFUSE_KEY2_DATA4_S) -#define EFUSE_KEY2_DATA4_V 0xffffffff -#define EFUSE_KEY2_DATA4_S 0 - -/* EFUSE_RD_KEY2_DATA5_REG register - * Register 5 of BLOCK6 (KEY2). - */ - -#define EFUSE_RD_KEY2_DATA5_REG (DR_REG_EFUSE_BASE + 0xf0) - -/* EFUSE_KEY2_DATA5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY2. - */ - -#define EFUSE_KEY2_DATA5 0xffffffff -#define EFUSE_KEY2_DATA5_M (EFUSE_KEY2_DATA5_V << EFUSE_KEY2_DATA5_S) -#define EFUSE_KEY2_DATA5_V 0xffffffff -#define EFUSE_KEY2_DATA5_S 0 - -/* EFUSE_RD_KEY2_DATA6_REG register - * Register 6 of BLOCK6 (KEY2). - */ - -#define EFUSE_RD_KEY2_DATA6_REG (DR_REG_EFUSE_BASE + 0xf4) - -/* EFUSE_KEY2_DATA6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY2. - */ - -#define EFUSE_KEY2_DATA6 0xffffffff -#define EFUSE_KEY2_DATA6_M (EFUSE_KEY2_DATA6_V << EFUSE_KEY2_DATA6_S) -#define EFUSE_KEY2_DATA6_V 0xffffffff -#define EFUSE_KEY2_DATA6_S 0 - -/* EFUSE_RD_KEY2_DATA7_REG register - * Register 7 of BLOCK6 (KEY2). - */ - -#define EFUSE_RD_KEY2_DATA7_REG (DR_REG_EFUSE_BASE + 0xf8) - -/* EFUSE_KEY2_DATA7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY2. - */ - -#define EFUSE_KEY2_DATA7 0xffffffff -#define EFUSE_KEY2_DATA7_M (EFUSE_KEY2_DATA7_V << EFUSE_KEY2_DATA7_S) -#define EFUSE_KEY2_DATA7_V 0xffffffff -#define EFUSE_KEY2_DATA7_S 0 - -/* EFUSE_RD_KEY3_DATA0_REG register - * Register 0 of BLOCK7 (KEY3). - */ - -#define EFUSE_RD_KEY3_DATA0_REG (DR_REG_EFUSE_BASE + 0xfc) - -/* EFUSE_KEY3_DATA0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY3. - */ - -#define EFUSE_KEY3_DATA0 0xffffffff -#define EFUSE_KEY3_DATA0_M (EFUSE_KEY3_DATA0_V << EFUSE_KEY3_DATA0_S) -#define EFUSE_KEY3_DATA0_V 0xffffffff -#define EFUSE_KEY3_DATA0_S 0 - -/* EFUSE_RD_KEY3_DATA1_REG register - * Register 1 of BLOCK7 (KEY3). - */ - -#define EFUSE_RD_KEY3_DATA1_REG (DR_REG_EFUSE_BASE + 0x100) - -/* EFUSE_KEY3_DATA1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY3. - */ - -#define EFUSE_KEY3_DATA1 0xffffffff -#define EFUSE_KEY3_DATA1_M (EFUSE_KEY3_DATA1_V << EFUSE_KEY3_DATA1_S) -#define EFUSE_KEY3_DATA1_V 0xffffffff -#define EFUSE_KEY3_DATA1_S 0 - -/* EFUSE_RD_KEY3_DATA2_REG register - * Register 2 of BLOCK7 (KEY3). - */ - -#define EFUSE_RD_KEY3_DATA2_REG (DR_REG_EFUSE_BASE + 0x104) - -/* EFUSE_KEY3_DATA2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY3. - */ - -#define EFUSE_KEY3_DATA2 0xffffffff -#define EFUSE_KEY3_DATA2_M (EFUSE_KEY3_DATA2_V << EFUSE_KEY3_DATA2_S) -#define EFUSE_KEY3_DATA2_V 0xffffffff -#define EFUSE_KEY3_DATA2_S 0 - -/* EFUSE_RD_KEY3_DATA3_REG register - * Register 3 of BLOCK7 (KEY3). - */ - -#define EFUSE_RD_KEY3_DATA3_REG (DR_REG_EFUSE_BASE + 0x108) - -/* EFUSE_KEY3_DATA3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY3. - */ - -#define EFUSE_KEY3_DATA3 0xffffffff -#define EFUSE_KEY3_DATA3_M (EFUSE_KEY3_DATA3_V << EFUSE_KEY3_DATA3_S) -#define EFUSE_KEY3_DATA3_V 0xffffffff -#define EFUSE_KEY3_DATA3_S 0 - -/* EFUSE_RD_KEY3_DATA4_REG register - * Register 4 of BLOCK7 (KEY3). - */ - -#define EFUSE_RD_KEY3_DATA4_REG (DR_REG_EFUSE_BASE + 0x10c) - -/* EFUSE_KEY3_DATA4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY3. - */ - -#define EFUSE_KEY3_DATA4 0xffffffff -#define EFUSE_KEY3_DATA4_M (EFUSE_KEY3_DATA4_V << EFUSE_KEY3_DATA4_S) -#define EFUSE_KEY3_DATA4_V 0xffffffff -#define EFUSE_KEY3_DATA4_S 0 - -/* EFUSE_RD_KEY3_DATA5_REG register - * Register 5 of BLOCK7 (KEY3). - */ - -#define EFUSE_RD_KEY3_DATA5_REG (DR_REG_EFUSE_BASE + 0x110) - -/* EFUSE_KEY3_DATA5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY3. - */ - -#define EFUSE_KEY3_DATA5 0xffffffff -#define EFUSE_KEY3_DATA5_M (EFUSE_KEY3_DATA5_V << EFUSE_KEY3_DATA5_S) -#define EFUSE_KEY3_DATA5_V 0xffffffff -#define EFUSE_KEY3_DATA5_S 0 - -/* EFUSE_RD_KEY3_DATA6_REG register - * Register 6 of BLOCK7 (KEY3). - */ - -#define EFUSE_RD_KEY3_DATA6_REG (DR_REG_EFUSE_BASE + 0x114) - -/* EFUSE_KEY3_DATA6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY3. - */ - -#define EFUSE_KEY3_DATA6 0xffffffff -#define EFUSE_KEY3_DATA6_M (EFUSE_KEY3_DATA6_V << EFUSE_KEY3_DATA6_S) -#define EFUSE_KEY3_DATA6_V 0xffffffff -#define EFUSE_KEY3_DATA6_S 0 - -/* EFUSE_RD_KEY3_DATA7_REG register - * Register 7 of BLOCK7 (KEY3). - */ - -#define EFUSE_RD_KEY3_DATA7_REG (DR_REG_EFUSE_BASE + 0x118) - -/* EFUSE_KEY3_DATA7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY3. - */ - -#define EFUSE_KEY3_DATA7 0xffffffff -#define EFUSE_KEY3_DATA7_M (EFUSE_KEY3_DATA7_V << EFUSE_KEY3_DATA7_S) -#define EFUSE_KEY3_DATA7_V 0xffffffff -#define EFUSE_KEY3_DATA7_S 0 - -/* EFUSE_RD_KEY4_DATA0_REG register - * Register 0 of BLOCK8 (KEY4). - */ - -#define EFUSE_RD_KEY4_DATA0_REG (DR_REG_EFUSE_BASE + 0x11c) - -/* EFUSE_KEY4_DATA0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY4. - */ - -#define EFUSE_KEY4_DATA0 0xffffffff -#define EFUSE_KEY4_DATA0_M (EFUSE_KEY4_DATA0_V << EFUSE_KEY4_DATA0_S) -#define EFUSE_KEY4_DATA0_V 0xffffffff -#define EFUSE_KEY4_DATA0_S 0 - -/* EFUSE_RD_KEY4_DATA1_REG register - * Register 1 of BLOCK8 (KEY4). - */ - -#define EFUSE_RD_KEY4_DATA1_REG (DR_REG_EFUSE_BASE + 0x120) - -/* EFUSE_KEY4_DATA1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY4. - */ - -#define EFUSE_KEY4_DATA1 0xffffffff -#define EFUSE_KEY4_DATA1_M (EFUSE_KEY4_DATA1_V << EFUSE_KEY4_DATA1_S) -#define EFUSE_KEY4_DATA1_V 0xffffffff -#define EFUSE_KEY4_DATA1_S 0 - -/* EFUSE_RD_KEY4_DATA2_REG register - * Register 2 of BLOCK8 (KEY4). - */ - -#define EFUSE_RD_KEY4_DATA2_REG (DR_REG_EFUSE_BASE + 0x124) - -/* EFUSE_KEY4_DATA2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY4. - */ - -#define EFUSE_KEY4_DATA2 0xffffffff -#define EFUSE_KEY4_DATA2_M (EFUSE_KEY4_DATA2_V << EFUSE_KEY4_DATA2_S) -#define EFUSE_KEY4_DATA2_V 0xffffffff -#define EFUSE_KEY4_DATA2_S 0 - -/* EFUSE_RD_KEY4_DATA3_REG register - * Register 3 of BLOCK8 (KEY4). - */ - -#define EFUSE_RD_KEY4_DATA3_REG (DR_REG_EFUSE_BASE + 0x128) - -/* EFUSE_KEY4_DATA3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY4. - */ - -#define EFUSE_KEY4_DATA3 0xffffffff -#define EFUSE_KEY4_DATA3_M (EFUSE_KEY4_DATA3_V << EFUSE_KEY4_DATA3_S) -#define EFUSE_KEY4_DATA3_V 0xffffffff -#define EFUSE_KEY4_DATA3_S 0 - -/* EFUSE_RD_KEY4_DATA4_REG register - * Register 4 of BLOCK8 (KEY4). - */ - -#define EFUSE_RD_KEY4_DATA4_REG (DR_REG_EFUSE_BASE + 0x12c) - -/* EFUSE_KEY4_DATA4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY4. - */ - -#define EFUSE_KEY4_DATA4 0xffffffff -#define EFUSE_KEY4_DATA4_M (EFUSE_KEY4_DATA4_V << EFUSE_KEY4_DATA4_S) -#define EFUSE_KEY4_DATA4_V 0xffffffff -#define EFUSE_KEY4_DATA4_S 0 - -/* EFUSE_RD_KEY4_DATA5_REG register - * Register 5 of BLOCK8 (KEY4). - */ - -#define EFUSE_RD_KEY4_DATA5_REG (DR_REG_EFUSE_BASE + 0x130) - -/* EFUSE_KEY4_DATA5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY4. - */ - -#define EFUSE_KEY4_DATA5 0xffffffff -#define EFUSE_KEY4_DATA5_M (EFUSE_KEY4_DATA5_V << EFUSE_KEY4_DATA5_S) -#define EFUSE_KEY4_DATA5_V 0xffffffff -#define EFUSE_KEY4_DATA5_S 0 - -/* EFUSE_RD_KEY4_DATA6_REG register - * Register 6 of BLOCK8 (KEY4). - */ - -#define EFUSE_RD_KEY4_DATA6_REG (DR_REG_EFUSE_BASE + 0x134) - -/* EFUSE_KEY4_DATA6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY4. - */ - -#define EFUSE_KEY4_DATA6 0xffffffff -#define EFUSE_KEY4_DATA6_M (EFUSE_KEY4_DATA6_V << EFUSE_KEY4_DATA6_S) -#define EFUSE_KEY4_DATA6_V 0xffffffff -#define EFUSE_KEY4_DATA6_S 0 - -/* EFUSE_RD_KEY4_DATA7_REG register - * Register 7 of BLOCK8 (KEY4). - */ - -#define EFUSE_RD_KEY4_DATA7_REG (DR_REG_EFUSE_BASE + 0x138) - -/* EFUSE_KEY4_DATA7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY4. - */ - -#define EFUSE_KEY4_DATA7 0xffffffff -#define EFUSE_KEY4_DATA7_M (EFUSE_KEY4_DATA7_V << EFUSE_KEY4_DATA7_S) -#define EFUSE_KEY4_DATA7_V 0xffffffff -#define EFUSE_KEY4_DATA7_S 0 - -/* EFUSE_RD_KEY5_DATA0_REG register - * Register 0 of BLOCK9 (KEY5). - */ - -#define EFUSE_RD_KEY5_DATA0_REG (DR_REG_EFUSE_BASE + 0x13c) - -/* EFUSE_KEY5_DATA0 : RO; bitpos: [31:0]; default: 0; - * Stores the zeroth 32 bits of KEY5. - */ - -#define EFUSE_KEY5_DATA0 0xffffffff -#define EFUSE_KEY5_DATA0_M (EFUSE_KEY5_DATA0_V << EFUSE_KEY5_DATA0_S) -#define EFUSE_KEY5_DATA0_V 0xffffffff -#define EFUSE_KEY5_DATA0_S 0 - -/* EFUSE_RD_KEY5_DATA1_REG register - * Register 1 of BLOCK9 (KEY5). - */ - -#define EFUSE_RD_KEY5_DATA1_REG (DR_REG_EFUSE_BASE + 0x140) - -/* EFUSE_KEY5_DATA1 : RO; bitpos: [31:0]; default: 0; - * Stores the first 32 bits of KEY5. - */ - -#define EFUSE_KEY5_DATA1 0xffffffff -#define EFUSE_KEY5_DATA1_M (EFUSE_KEY5_DATA1_V << EFUSE_KEY5_DATA1_S) -#define EFUSE_KEY5_DATA1_V 0xffffffff -#define EFUSE_KEY5_DATA1_S 0 - -/* EFUSE_RD_KEY5_DATA2_REG register - * Register 2 of BLOCK9 (KEY5). - */ - -#define EFUSE_RD_KEY5_DATA2_REG (DR_REG_EFUSE_BASE + 0x144) - -/* EFUSE_KEY5_DATA2 : RO; bitpos: [31:0]; default: 0; - * Stores the second 32 bits of KEY5. - */ - -#define EFUSE_KEY5_DATA2 0xffffffff -#define EFUSE_KEY5_DATA2_M (EFUSE_KEY5_DATA2_V << EFUSE_KEY5_DATA2_S) -#define EFUSE_KEY5_DATA2_V 0xffffffff -#define EFUSE_KEY5_DATA2_S 0 - -/* EFUSE_RD_KEY5_DATA3_REG register - * Register 3 of BLOCK9 (KEY5). - */ - -#define EFUSE_RD_KEY5_DATA3_REG (DR_REG_EFUSE_BASE + 0x148) - -/* EFUSE_KEY5_DATA3 : RO; bitpos: [31:0]; default: 0; - * Stores the third 32 bits of KEY5. - */ - -#define EFUSE_KEY5_DATA3 0xffffffff -#define EFUSE_KEY5_DATA3_M (EFUSE_KEY5_DATA3_V << EFUSE_KEY5_DATA3_S) -#define EFUSE_KEY5_DATA3_V 0xffffffff -#define EFUSE_KEY5_DATA3_S 0 - -/* EFUSE_RD_KEY5_DATA4_REG register - * Register 4 of BLOCK9 (KEY5). - */ - -#define EFUSE_RD_KEY5_DATA4_REG (DR_REG_EFUSE_BASE + 0x14c) - -/* EFUSE_KEY5_DATA4 : RO; bitpos: [31:0]; default: 0; - * Stores the fourth 32 bits of KEY5. - */ - -#define EFUSE_KEY5_DATA4 0xffffffff -#define EFUSE_KEY5_DATA4_M (EFUSE_KEY5_DATA4_V << EFUSE_KEY5_DATA4_S) -#define EFUSE_KEY5_DATA4_V 0xffffffff -#define EFUSE_KEY5_DATA4_S 0 - -/* EFUSE_RD_KEY5_DATA5_REG register - * Register 5 of BLOCK9 (KEY5). - */ - -#define EFUSE_RD_KEY5_DATA5_REG (DR_REG_EFUSE_BASE + 0x150) - -/* EFUSE_KEY5_DATA5 : RO; bitpos: [31:0]; default: 0; - * Stores the fifth 32 bits of KEY5. - */ - -#define EFUSE_KEY5_DATA5 0xffffffff -#define EFUSE_KEY5_DATA5_M (EFUSE_KEY5_DATA5_V << EFUSE_KEY5_DATA5_S) -#define EFUSE_KEY5_DATA5_V 0xffffffff -#define EFUSE_KEY5_DATA5_S 0 - -/* EFUSE_RD_KEY5_DATA6_REG register - * Register 6 of BLOCK9 (KEY5). - */ - -#define EFUSE_RD_KEY5_DATA6_REG (DR_REG_EFUSE_BASE + 0x154) - -/* EFUSE_KEY5_DATA6 : RO; bitpos: [31:0]; default: 0; - * Stores the sixth 32 bits of KEY5. - */ - -#define EFUSE_KEY5_DATA6 0xffffffff -#define EFUSE_KEY5_DATA6_M (EFUSE_KEY5_DATA6_V << EFUSE_KEY5_DATA6_S) -#define EFUSE_KEY5_DATA6_V 0xffffffff -#define EFUSE_KEY5_DATA6_S 0 - -/* EFUSE_RD_KEY5_DATA7_REG register - * Register 7 of BLOCK9 (KEY5). - */ - -#define EFUSE_RD_KEY5_DATA7_REG (DR_REG_EFUSE_BASE + 0x158) - -/* EFUSE_KEY5_DATA7 : RO; bitpos: [31:0]; default: 0; - * Stores the seventh 32 bits of KEY5. - */ - -#define EFUSE_KEY5_DATA7 0xffffffff -#define EFUSE_KEY5_DATA7_M (EFUSE_KEY5_DATA7_V << EFUSE_KEY5_DATA7_S) -#define EFUSE_KEY5_DATA7_V 0xffffffff -#define EFUSE_KEY5_DATA7_S 0 - -/* EFUSE_RD_SYS_PART2_DATA0_REG register - * Register 0 of BLOCK10 (system). - */ - -#define EFUSE_RD_SYS_PART2_DATA0_REG (DR_REG_EFUSE_BASE + 0x15c) - -/* EFUSE_SYS_DATA_PART2_0 : RO; bitpos: [31:0]; default: 0; - * Stores the 0th 32 bits of the 2nd part of system data. - */ - -#define EFUSE_SYS_DATA_PART2_0 0xffffffff -#define EFUSE_SYS_DATA_PART2_0_M (EFUSE_SYS_DATA_PART2_0_V << EFUSE_SYS_DATA_PART2_0_S) -#define EFUSE_SYS_DATA_PART2_0_V 0xffffffff -#define EFUSE_SYS_DATA_PART2_0_S 0 - -/* EFUSE_RD_SYS_PART2_DATA1_REG register - * Register 1 of BLOCK9 (KEY5). - */ - -#define EFUSE_RD_SYS_PART2_DATA1_REG (DR_REG_EFUSE_BASE + 0x160) - -/* EFUSE_SYS_DATA_PART2_1 : RO; bitpos: [31:0]; default: 0; - * Stores the 1st 32 bits of the 2nd part of system data. - */ - -#define EFUSE_SYS_DATA_PART2_1 0xffffffff -#define EFUSE_SYS_DATA_PART2_1_M (EFUSE_SYS_DATA_PART2_1_V << EFUSE_SYS_DATA_PART2_1_S) -#define EFUSE_SYS_DATA_PART2_1_V 0xffffffff -#define EFUSE_SYS_DATA_PART2_1_S 0 - -/* EFUSE_RD_SYS_PART2_DATA2_REG register - * Register 2 of BLOCK10 (system). - */ - -#define EFUSE_RD_SYS_PART2_DATA2_REG (DR_REG_EFUSE_BASE + 0x164) - -/* EFUSE_SYS_DATA_PART2_2 : RO; bitpos: [31:0]; default: 0; - * Stores the 2nd 32 bits of the 2nd part of system data. - */ - -#define EFUSE_SYS_DATA_PART2_2 0xffffffff -#define EFUSE_SYS_DATA_PART2_2_M (EFUSE_SYS_DATA_PART2_2_V << EFUSE_SYS_DATA_PART2_2_S) -#define EFUSE_SYS_DATA_PART2_2_V 0xffffffff -#define EFUSE_SYS_DATA_PART2_2_S 0 - -/* EFUSE_RD_SYS_PART2_DATA3_REG register - * Register 3 of BLOCK10 (system). - */ - -#define EFUSE_RD_SYS_PART2_DATA3_REG (DR_REG_EFUSE_BASE + 0x168) - -/* EFUSE_SYS_DATA_PART2_3 : RO; bitpos: [31:0]; default: 0; - * Stores the 3rd 32 bits of the 2nd part of system data. - */ - -#define EFUSE_SYS_DATA_PART2_3 0xffffffff -#define EFUSE_SYS_DATA_PART2_3_M (EFUSE_SYS_DATA_PART2_3_V << EFUSE_SYS_DATA_PART2_3_S) -#define EFUSE_SYS_DATA_PART2_3_V 0xffffffff -#define EFUSE_SYS_DATA_PART2_3_S 0 - -/* EFUSE_RD_SYS_PART2_DATA4_REG register - * Register 4 of BLOCK10 (system). - */ - -#define EFUSE_RD_SYS_PART2_DATA4_REG (DR_REG_EFUSE_BASE + 0x16c) - -/* EFUSE_SYS_DATA_PART2_4 : RO; bitpos: [31:0]; default: 0; - * Stores the 4th 32 bits of the 2nd part of system data. - */ - -#define EFUSE_SYS_DATA_PART2_4 0xffffffff -#define EFUSE_SYS_DATA_PART2_4_M (EFUSE_SYS_DATA_PART2_4_V << EFUSE_SYS_DATA_PART2_4_S) -#define EFUSE_SYS_DATA_PART2_4_V 0xffffffff -#define EFUSE_SYS_DATA_PART2_4_S 0 - -/* EFUSE_RD_SYS_PART2_DATA5_REG register - * Register 5 of BLOCK10 (system). - */ - -#define EFUSE_RD_SYS_PART2_DATA5_REG (DR_REG_EFUSE_BASE + 0x170) - -/* EFUSE_SYS_DATA_PART2_5 : RO; bitpos: [31:0]; default: 0; - * Stores the 5th 32 bits of the 2nd part of system data. - */ - -#define EFUSE_SYS_DATA_PART2_5 0xffffffff -#define EFUSE_SYS_DATA_PART2_5_M (EFUSE_SYS_DATA_PART2_5_V << EFUSE_SYS_DATA_PART2_5_S) -#define EFUSE_SYS_DATA_PART2_5_V 0xffffffff -#define EFUSE_SYS_DATA_PART2_5_S 0 - -/* EFUSE_RD_SYS_PART2_DATA6_REG register - * Register 6 of BLOCK10 (system). - */ - -#define EFUSE_RD_SYS_PART2_DATA6_REG (DR_REG_EFUSE_BASE + 0x174) - -/* EFUSE_SYS_DATA_PART2_6 : RO; bitpos: [31:0]; default: 0; - * Stores the 6th 32 bits of the 2nd part of system data. - */ - -#define EFUSE_SYS_DATA_PART2_6 0xffffffff -#define EFUSE_SYS_DATA_PART2_6_M (EFUSE_SYS_DATA_PART2_6_V << EFUSE_SYS_DATA_PART2_6_S) -#define EFUSE_SYS_DATA_PART2_6_V 0xffffffff -#define EFUSE_SYS_DATA_PART2_6_S 0 - -/* EFUSE_RD_SYS_PART2_DATA7_REG register - * Register 7 of BLOCK10 (system). - */ - -#define EFUSE_RD_SYS_PART2_DATA7_REG (DR_REG_EFUSE_BASE + 0x178) - -/* EFUSE_SYS_DATA_PART2_7 : RO; bitpos: [31:0]; default: 0; - * Stores the 7th 32 bits of the 2nd part of system data. - */ - -#define EFUSE_SYS_DATA_PART2_7 0xffffffff -#define EFUSE_SYS_DATA_PART2_7_M (EFUSE_SYS_DATA_PART2_7_V << EFUSE_SYS_DATA_PART2_7_S) -#define EFUSE_SYS_DATA_PART2_7_V 0xffffffff -#define EFUSE_SYS_DATA_PART2_7_S 0 - -/* EFUSE_RD_REPEAT_ERR0_REG register - * Programming error record register 0 of BLOCK0. - */ - -#define EFUSE_RD_REPEAT_ERR0_REG (DR_REG_EFUSE_BASE + 0x17c) - -/* EFUSE_VDD_SPI_DREFH_ERR : RO; bitpos: [31:30]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_VDD_SPI_DREFH_ERR 0x00000003 -#define EFUSE_VDD_SPI_DREFH_ERR_M (EFUSE_VDD_SPI_DREFH_ERR_V << EFUSE_VDD_SPI_DREFH_ERR_S) -#define EFUSE_VDD_SPI_DREFH_ERR_V 0x00000003 -#define EFUSE_VDD_SPI_DREFH_ERR_S 30 - -/* EFUSE_VDD_SPI_MODECURLIM_ERR : RO; bitpos: [29]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_VDD_SPI_MODECURLIM_ERR (BIT(29)) -#define EFUSE_VDD_SPI_MODECURLIM_ERR_M (EFUSE_VDD_SPI_MODECURLIM_ERR_V << EFUSE_VDD_SPI_MODECURLIM_ERR_S) -#define EFUSE_VDD_SPI_MODECURLIM_ERR_V 0x00000001 -#define EFUSE_VDD_SPI_MODECURLIM_ERR_S 29 - -/* EFUSE_BTLC_GPIO_ENABLE_ERR : RO; bitpos: [28:27]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_BTLC_GPIO_ENABLE_ERR 0x00000003 -#define EFUSE_BTLC_GPIO_ENABLE_ERR_M (EFUSE_BTLC_GPIO_ENABLE_ERR_V << EFUSE_BTLC_GPIO_ENABLE_ERR_S) -#define EFUSE_BTLC_GPIO_ENABLE_ERR_V 0x00000003 -#define EFUSE_BTLC_GPIO_ENABLE_ERR_S 27 - -/* EFUSE_EXT_PHY_ENABLE_ERR : RO; bitpos: [26]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_EXT_PHY_ENABLE_ERR (BIT(26)) -#define EFUSE_EXT_PHY_ENABLE_ERR_M (EFUSE_EXT_PHY_ENABLE_ERR_V << EFUSE_EXT_PHY_ENABLE_ERR_S) -#define EFUSE_EXT_PHY_ENABLE_ERR_V 0x00000001 -#define EFUSE_EXT_PHY_ENABLE_ERR_S 26 - -/* EFUSE_USB_EXCHG_PINS_ERR : RO; bitpos: [25]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_USB_EXCHG_PINS_ERR (BIT(25)) -#define EFUSE_USB_EXCHG_PINS_ERR_M (EFUSE_USB_EXCHG_PINS_ERR_V << EFUSE_USB_EXCHG_PINS_ERR_S) -#define EFUSE_USB_EXCHG_PINS_ERR_V 0x00000001 -#define EFUSE_USB_EXCHG_PINS_ERR_S 25 - -/* EFUSE_USB_DREFL_ERR : RO; bitpos: [24:23]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_USB_DREFL_ERR 0x00000003 -#define EFUSE_USB_DREFL_ERR_M (EFUSE_USB_DREFL_ERR_V << EFUSE_USB_DREFL_ERR_S) -#define EFUSE_USB_DREFL_ERR_V 0x00000003 -#define EFUSE_USB_DREFL_ERR_S 23 - -/* EFUSE_USB_DREFH_ERR : RO; bitpos: [22:21]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_USB_DREFH_ERR 0x00000003 -#define EFUSE_USB_DREFH_ERR_M (EFUSE_USB_DREFH_ERR_V << EFUSE_USB_DREFH_ERR_S) -#define EFUSE_USB_DREFH_ERR_V 0x00000003 -#define EFUSE_USB_DREFH_ERR_S 21 - -/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO; bitpos: [20]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR (BIT(20)) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M (EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V << EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S) -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V 0x00000001 -#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S 20 - -/* EFUSE_DIS_PAD_JTAG_ERR : RO; bitpos: [19]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_DIS_PAD_JTAG_ERR (BIT(19)) -#define EFUSE_DIS_PAD_JTAG_ERR_M (EFUSE_DIS_PAD_JTAG_ERR_V << EFUSE_DIS_PAD_JTAG_ERR_S) -#define EFUSE_DIS_PAD_JTAG_ERR_V 0x00000001 -#define EFUSE_DIS_PAD_JTAG_ERR_S 19 - -/* EFUSE_SOFT_DIS_JTAG_ERR : RO; bitpos: [18:16]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_SOFT_DIS_JTAG_ERR 0x00000007 -#define EFUSE_SOFT_DIS_JTAG_ERR_M (EFUSE_SOFT_DIS_JTAG_ERR_V << EFUSE_SOFT_DIS_JTAG_ERR_S) -#define EFUSE_SOFT_DIS_JTAG_ERR_V 0x00000007 -#define EFUSE_SOFT_DIS_JTAG_ERR_S 16 - -/* EFUSE_DIS_APP_CPU_ERR : RO; bitpos: [15]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_DIS_APP_CPU_ERR (BIT(15)) -#define EFUSE_DIS_APP_CPU_ERR_M (EFUSE_DIS_APP_CPU_ERR_V << EFUSE_DIS_APP_CPU_ERR_S) -#define EFUSE_DIS_APP_CPU_ERR_V 0x00000001 -#define EFUSE_DIS_APP_CPU_ERR_S 15 - -/* EFUSE_DIS_CAN_ERR : RO; bitpos: [14]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_DIS_CAN_ERR (BIT(14)) -#define EFUSE_DIS_CAN_ERR_M (EFUSE_DIS_CAN_ERR_V << EFUSE_DIS_CAN_ERR_S) -#define EFUSE_DIS_CAN_ERR_V 0x00000001 -#define EFUSE_DIS_CAN_ERR_S 14 - -/* EFUSE_DIS_USB_ERR : RO; bitpos: [13]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_DIS_USB_ERR (BIT(13)) -#define EFUSE_DIS_USB_ERR_M (EFUSE_DIS_USB_ERR_V << EFUSE_DIS_USB_ERR_S) -#define EFUSE_DIS_USB_ERR_V 0x00000001 -#define EFUSE_DIS_USB_ERR_S 13 - -/* EFUSE_DIS_FORCE_DOWNLOAD_ERR : RO; bitpos: [12]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_DIS_FORCE_DOWNLOAD_ERR (BIT(12)) -#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_M (EFUSE_DIS_FORCE_DOWNLOAD_ERR_V << EFUSE_DIS_FORCE_DOWNLOAD_ERR_S) -#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_V 0x00000001 -#define EFUSE_DIS_FORCE_DOWNLOAD_ERR_S 12 - -/* EFUSE_DIS_DOWNLOAD_DCACHE_ERR : RO; bitpos: [11]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR (BIT(11)) -#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_M (EFUSE_DIS_DOWNLOAD_DCACHE_ERR_V << EFUSE_DIS_DOWNLOAD_DCACHE_ERR_S) -#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_V 0x00000001 -#define EFUSE_DIS_DOWNLOAD_DCACHE_ERR_S 11 - -/* EFUSE_DIS_DOWNLOAD_ICACHE_ERR : RO; bitpos: [10]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR (BIT(10)) -#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_M (EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V << EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S) -#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_V 0x00000001 -#define EFUSE_DIS_DOWNLOAD_ICACHE_ERR_S 10 - -/* EFUSE_DIS_DCACHE_ERR : RO; bitpos: [9]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_DIS_DCACHE_ERR (BIT(9)) -#define EFUSE_DIS_DCACHE_ERR_M (EFUSE_DIS_DCACHE_ERR_V << EFUSE_DIS_DCACHE_ERR_S) -#define EFUSE_DIS_DCACHE_ERR_V 0x00000001 -#define EFUSE_DIS_DCACHE_ERR_S 9 - -/* EFUSE_DIS_ICACHE_ERR : RO; bitpos: [8]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_DIS_ICACHE_ERR (BIT(8)) -#define EFUSE_DIS_ICACHE_ERR_M (EFUSE_DIS_ICACHE_ERR_V << EFUSE_DIS_ICACHE_ERR_S) -#define EFUSE_DIS_ICACHE_ERR_V 0x00000001 -#define EFUSE_DIS_ICACHE_ERR_S 8 - -/* EFUSE_DIS_RTC_RAM_BOOT_ERR : RO; bitpos: [7]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_DIS_RTC_RAM_BOOT_ERR (BIT(7)) -#define EFUSE_DIS_RTC_RAM_BOOT_ERR_M (EFUSE_DIS_RTC_RAM_BOOT_ERR_V << EFUSE_DIS_RTC_RAM_BOOT_ERR_S) -#define EFUSE_DIS_RTC_RAM_BOOT_ERR_V 0x00000001 -#define EFUSE_DIS_RTC_RAM_BOOT_ERR_S 7 - -/* EFUSE_RD_DIS_ERR : RO; bitpos: [6:0]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_RD_DIS_ERR 0x0000007f -#define EFUSE_RD_DIS_ERR_M (EFUSE_RD_DIS_ERR_V << EFUSE_RD_DIS_ERR_S) -#define EFUSE_RD_DIS_ERR_V 0x0000007f -#define EFUSE_RD_DIS_ERR_S 0 - -/* EFUSE_RD_REPEAT_ERR1_REG register - * Programming error record register 1 of BLOCK0. - */ - -#define EFUSE_RD_REPEAT_ERR1_REG (DR_REG_EFUSE_BASE + 0x180) - -/* EFUSE_KEY_PURPOSE_1_ERR : RO; bitpos: [31:28]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_KEY_PURPOSE_1_ERR 0x0000000f -#define EFUSE_KEY_PURPOSE_1_ERR_M (EFUSE_KEY_PURPOSE_1_ERR_V << EFUSE_KEY_PURPOSE_1_ERR_S) -#define EFUSE_KEY_PURPOSE_1_ERR_V 0x0000000f -#define EFUSE_KEY_PURPOSE_1_ERR_S 28 - -/* EFUSE_KEY_PURPOSE_0_ERR : RO; bitpos: [27:24]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_KEY_PURPOSE_0_ERR 0x0000000f -#define EFUSE_KEY_PURPOSE_0_ERR_M (EFUSE_KEY_PURPOSE_0_ERR_V << EFUSE_KEY_PURPOSE_0_ERR_S) -#define EFUSE_KEY_PURPOSE_0_ERR_V 0x0000000f -#define EFUSE_KEY_PURPOSE_0_ERR_S 24 - -/* EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR : RO; bitpos: [23]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR (BIT(23)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S) -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_V 0x00000001 -#define EFUSE_SECURE_BOOT_KEY_REVOKE2_ERR_S 23 - -/* EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR : RO; bitpos: [22]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR (BIT(22)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S) -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_V 0x00000001 -#define EFUSE_SECURE_BOOT_KEY_REVOKE1_ERR_S 22 - -/* EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR : RO; bitpos: [21]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR (BIT(21)) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_M (EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V << EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S) -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_V 0x00000001 -#define EFUSE_SECURE_BOOT_KEY_REVOKE0_ERR_S 21 - -/* EFUSE_SPI_BOOT_CRYPT_CNT_ERR : RO; bitpos: [20:18]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR 0x00000007 -#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_M (EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V << EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S) -#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_V 0x00000007 -#define EFUSE_SPI_BOOT_CRYPT_CNT_ERR_S 18 - -/* EFUSE_WDT_DELAY_SEL_ERR : RO; bitpos: [17:16]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_WDT_DELAY_SEL_ERR 0x00000003 -#define EFUSE_WDT_DELAY_SEL_ERR_M (EFUSE_WDT_DELAY_SEL_ERR_V << EFUSE_WDT_DELAY_SEL_ERR_S) -#define EFUSE_WDT_DELAY_SEL_ERR_V 0x00000003 -#define EFUSE_WDT_DELAY_SEL_ERR_S 16 - -/* EFUSE_VDD_SPI_DCAP_ERR : RO; bitpos: [15:14]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_VDD_SPI_DCAP_ERR 0x00000003 -#define EFUSE_VDD_SPI_DCAP_ERR_M (EFUSE_VDD_SPI_DCAP_ERR_V << EFUSE_VDD_SPI_DCAP_ERR_S) -#define EFUSE_VDD_SPI_DCAP_ERR_V 0x00000003 -#define EFUSE_VDD_SPI_DCAP_ERR_S 14 - -/* EFUSE_VDD_SPI_INIT_ERR : RO; bitpos: [13:12]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_VDD_SPI_INIT_ERR 0x00000003 -#define EFUSE_VDD_SPI_INIT_ERR_M (EFUSE_VDD_SPI_INIT_ERR_V << EFUSE_VDD_SPI_INIT_ERR_S) -#define EFUSE_VDD_SPI_INIT_ERR_V 0x00000003 -#define EFUSE_VDD_SPI_INIT_ERR_S 12 - -/* EFUSE_VDD_SPI_DCURLIM_ERR : RO; bitpos: [11:9]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_VDD_SPI_DCURLIM_ERR 0x00000007 -#define EFUSE_VDD_SPI_DCURLIM_ERR_M (EFUSE_VDD_SPI_DCURLIM_ERR_V << EFUSE_VDD_SPI_DCURLIM_ERR_S) -#define EFUSE_VDD_SPI_DCURLIM_ERR_V 0x00000007 -#define EFUSE_VDD_SPI_DCURLIM_ERR_S 9 - -/* EFUSE_VDD_SPI_ENCURLIM_ERR : RO; bitpos: [8]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_VDD_SPI_ENCURLIM_ERR (BIT(8)) -#define EFUSE_VDD_SPI_ENCURLIM_ERR_M (EFUSE_VDD_SPI_ENCURLIM_ERR_V << EFUSE_VDD_SPI_ENCURLIM_ERR_S) -#define EFUSE_VDD_SPI_ENCURLIM_ERR_V 0x00000001 -#define EFUSE_VDD_SPI_ENCURLIM_ERR_S 8 - -/* EFUSE_VDD_SPI_EN_INIT_ERR : RO; bitpos: [7]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_VDD_SPI_EN_INIT_ERR (BIT(7)) -#define EFUSE_VDD_SPI_EN_INIT_ERR_M (EFUSE_VDD_SPI_EN_INIT_ERR_V << EFUSE_VDD_SPI_EN_INIT_ERR_S) -#define EFUSE_VDD_SPI_EN_INIT_ERR_V 0x00000001 -#define EFUSE_VDD_SPI_EN_INIT_ERR_S 7 - -/* EFUSE_VDD_SPI_FORCE_ERR : RO; bitpos: [6]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_VDD_SPI_FORCE_ERR (BIT(6)) -#define EFUSE_VDD_SPI_FORCE_ERR_M (EFUSE_VDD_SPI_FORCE_ERR_V << EFUSE_VDD_SPI_FORCE_ERR_S) -#define EFUSE_VDD_SPI_FORCE_ERR_V 0x00000001 -#define EFUSE_VDD_SPI_FORCE_ERR_S 6 - -/* EFUSE_VDD_SPI_TIEH_ERR : RO; bitpos: [5]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_VDD_SPI_TIEH_ERR (BIT(5)) -#define EFUSE_VDD_SPI_TIEH_ERR_M (EFUSE_VDD_SPI_TIEH_ERR_V << EFUSE_VDD_SPI_TIEH_ERR_S) -#define EFUSE_VDD_SPI_TIEH_ERR_V 0x00000001 -#define EFUSE_VDD_SPI_TIEH_ERR_S 5 - -/* EFUSE_VDD_SPI_XPD_ERR : RO; bitpos: [4]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_VDD_SPI_XPD_ERR (BIT(4)) -#define EFUSE_VDD_SPI_XPD_ERR_M (EFUSE_VDD_SPI_XPD_ERR_V << EFUSE_VDD_SPI_XPD_ERR_S) -#define EFUSE_VDD_SPI_XPD_ERR_V 0x00000001 -#define EFUSE_VDD_SPI_XPD_ERR_S 4 - -/* EFUSE_VDD_SPI_DREFL_ERR : RO; bitpos: [3:2]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_VDD_SPI_DREFL_ERR 0x00000003 -#define EFUSE_VDD_SPI_DREFL_ERR_M (EFUSE_VDD_SPI_DREFL_ERR_V << EFUSE_VDD_SPI_DREFL_ERR_S) -#define EFUSE_VDD_SPI_DREFL_ERR_V 0x00000003 -#define EFUSE_VDD_SPI_DREFL_ERR_S 2 - -/* EFUSE_VDD_SPI_DREFM_ERR : RO; bitpos: [1:0]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_VDD_SPI_DREFM_ERR 0x00000003 -#define EFUSE_VDD_SPI_DREFM_ERR_M (EFUSE_VDD_SPI_DREFM_ERR_V << EFUSE_VDD_SPI_DREFM_ERR_S) -#define EFUSE_VDD_SPI_DREFM_ERR_V 0x00000003 -#define EFUSE_VDD_SPI_DREFM_ERR_S 0 - -/* EFUSE_RD_REPEAT_ERR2_REG register - * Programming error record register 2 of BLOCK0. - */ - -#define EFUSE_RD_REPEAT_ERR2_REG (DR_REG_EFUSE_BASE + 0x184) - -/* EFUSE_FLASH_TPUW_ERR : RO; bitpos: [31:28]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_FLASH_TPUW_ERR 0x0000000f -#define EFUSE_FLASH_TPUW_ERR_M (EFUSE_FLASH_TPUW_ERR_V << EFUSE_FLASH_TPUW_ERR_S) -#define EFUSE_FLASH_TPUW_ERR_V 0x0000000f -#define EFUSE_FLASH_TPUW_ERR_S 28 - -/* EFUSE_POWER_GLITCH_DSENSE_ERR : RO; bitpos: [27:26]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_POWER_GLITCH_DSENSE_ERR 0x00000003 -#define EFUSE_POWER_GLITCH_DSENSE_ERR_M (EFUSE_POWER_GLITCH_DSENSE_ERR_V << EFUSE_POWER_GLITCH_DSENSE_ERR_S) -#define EFUSE_POWER_GLITCH_DSENSE_ERR_V 0x00000003 -#define EFUSE_POWER_GLITCH_DSENSE_ERR_S 26 - -/* EFUSE_USB_PHY_SEL_ERR : RO; bitpos: [25]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_USB_PHY_SEL_ERR (BIT(25)) -#define EFUSE_USB_PHY_SEL_ERR_M (EFUSE_USB_PHY_SEL_ERR_V << EFUSE_USB_PHY_SEL_ERR_S) -#define EFUSE_USB_PHY_SEL_ERR_V 0x00000001 -#define EFUSE_USB_PHY_SEL_ERR_S 25 - -/* EFUSE_STRAP_JTAG_SEL_ERR : RO; bitpos: [24]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_STRAP_JTAG_SEL_ERR (BIT(24)) -#define EFUSE_STRAP_JTAG_SEL_ERR_M (EFUSE_STRAP_JTAG_SEL_ERR_V << EFUSE_STRAP_JTAG_SEL_ERR_S) -#define EFUSE_STRAP_JTAG_SEL_ERR_V 0x00000001 -#define EFUSE_STRAP_JTAG_SEL_ERR_S 24 - -/* EFUSE_DIS_USB_DEVICE_ERR : RO; bitpos: [23]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_DIS_USB_DEVICE_ERR (BIT(23)) -#define EFUSE_DIS_USB_DEVICE_ERR_M (EFUSE_DIS_USB_DEVICE_ERR_V << EFUSE_DIS_USB_DEVICE_ERR_S) -#define EFUSE_DIS_USB_DEVICE_ERR_V 0x00000001 -#define EFUSE_DIS_USB_DEVICE_ERR_S 23 - -/* EFUSE_DIS_USB_JTAG_ERR : RO; bitpos: [22]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_DIS_USB_JTAG_ERR (BIT(22)) -#define EFUSE_DIS_USB_JTAG_ERR_M (EFUSE_DIS_USB_JTAG_ERR_V << EFUSE_DIS_USB_JTAG_ERR_S) -#define EFUSE_DIS_USB_JTAG_ERR_V 0x00000001 -#define EFUSE_DIS_USB_JTAG_ERR_S 22 - -/* EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO; bitpos: [21]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR (BIT(21)) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M (EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V << EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S) -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V 0x00000001 -#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S 21 - -/* EFUSE_SECURE_BOOT_EN_ERR : RO; bitpos: [20]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_SECURE_BOOT_EN_ERR (BIT(20)) -#define EFUSE_SECURE_BOOT_EN_ERR_M (EFUSE_SECURE_BOOT_EN_ERR_V << EFUSE_SECURE_BOOT_EN_ERR_S) -#define EFUSE_SECURE_BOOT_EN_ERR_V 0x00000001 -#define EFUSE_SECURE_BOOT_EN_ERR_S 20 - -/* EFUSE_RPT4_RESERVED0_ERR : RO; bitpos: [19:16]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_RPT4_RESERVED0_ERR 0x0000000f -#define EFUSE_RPT4_RESERVED0_ERR_M (EFUSE_RPT4_RESERVED0_ERR_V << EFUSE_RPT4_RESERVED0_ERR_S) -#define EFUSE_RPT4_RESERVED0_ERR_V 0x0000000f -#define EFUSE_RPT4_RESERVED0_ERR_S 16 - -/* EFUSE_KEY_PURPOSE_5_ERR : RO; bitpos: [15:12]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_KEY_PURPOSE_5_ERR 0x0000000f -#define EFUSE_KEY_PURPOSE_5_ERR_M (EFUSE_KEY_PURPOSE_5_ERR_V << EFUSE_KEY_PURPOSE_5_ERR_S) -#define EFUSE_KEY_PURPOSE_5_ERR_V 0x0000000f -#define EFUSE_KEY_PURPOSE_5_ERR_S 12 - -/* EFUSE_KEY_PURPOSE_4_ERR : RO; bitpos: [11:8]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_KEY_PURPOSE_4_ERR 0x0000000f -#define EFUSE_KEY_PURPOSE_4_ERR_M (EFUSE_KEY_PURPOSE_4_ERR_V << EFUSE_KEY_PURPOSE_4_ERR_S) -#define EFUSE_KEY_PURPOSE_4_ERR_V 0x0000000f -#define EFUSE_KEY_PURPOSE_4_ERR_S 8 - -/* EFUSE_KEY_PURPOSE_3_ERR : RO; bitpos: [7:4]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_KEY_PURPOSE_3_ERR 0x0000000f -#define EFUSE_KEY_PURPOSE_3_ERR_M (EFUSE_KEY_PURPOSE_3_ERR_V << EFUSE_KEY_PURPOSE_3_ERR_S) -#define EFUSE_KEY_PURPOSE_3_ERR_V 0x0000000f -#define EFUSE_KEY_PURPOSE_3_ERR_S 4 - -/* EFUSE_KEY_PURPOSE_2_ERR : RO; bitpos: [3:0]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_KEY_PURPOSE_2_ERR 0x0000000f -#define EFUSE_KEY_PURPOSE_2_ERR_M (EFUSE_KEY_PURPOSE_2_ERR_V << EFUSE_KEY_PURPOSE_2_ERR_S) -#define EFUSE_KEY_PURPOSE_2_ERR_V 0x0000000f -#define EFUSE_KEY_PURPOSE_2_ERR_S 0 - -/* EFUSE_RD_REPEAT_ERR3_REG register - * Programming error record register 3 of BLOCK0. - */ - -#define EFUSE_RD_REPEAT_ERR3_REG (DR_REG_EFUSE_BASE + 0x188) - -/* EFUSE_RPT4_RESERVED1_ERR : RO; bitpos: [31]; default: 0; - * Reserved. - */ - -#define EFUSE_RPT4_RESERVED1_ERR (BIT(31)) -#define EFUSE_RPT4_RESERVED1_ERR_M (EFUSE_RPT4_RESERVED1_ERR_V << EFUSE_RPT4_RESERVED1_ERR_S) -#define EFUSE_RPT4_RESERVED1_ERR_V 0x00000001 -#define EFUSE_RPT4_RESERVED1_ERR_S 31 - -/* EFUSE_POWERGLITCH_EN_ERR : RO; bitpos: [30]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_POWERGLITCH_EN_ERR (BIT(30)) -#define EFUSE_POWERGLITCH_EN_ERR_M (EFUSE_POWERGLITCH_EN_ERR_V << EFUSE_POWERGLITCH_EN_ERR_S) -#define EFUSE_POWERGLITCH_EN_ERR_V 0x00000001 -#define EFUSE_POWERGLITCH_EN_ERR_S 30 - -/* EFUSE_SECURE_VERSION_ERR : RO; bitpos: [29:14]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_SECURE_VERSION_ERR 0x0000ffff -#define EFUSE_SECURE_VERSION_ERR_M (EFUSE_SECURE_VERSION_ERR_V << EFUSE_SECURE_VERSION_ERR_S) -#define EFUSE_SECURE_VERSION_ERR_V 0x0000ffff -#define EFUSE_SECURE_VERSION_ERR_S 14 - -/* EFUSE_FORCE_SEND_RESUME_ERR : RO; bitpos: [13]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_FORCE_SEND_RESUME_ERR (BIT(13)) -#define EFUSE_FORCE_SEND_RESUME_ERR_M (EFUSE_FORCE_SEND_RESUME_ERR_V << EFUSE_FORCE_SEND_RESUME_ERR_S) -#define EFUSE_FORCE_SEND_RESUME_ERR_V 0x00000001 -#define EFUSE_FORCE_SEND_RESUME_ERR_S 13 - -/* EFUSE_FLASH_ECC_EN_ERR : RO; bitpos: [12]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_FLASH_ECC_EN_ERR (BIT(12)) -#define EFUSE_FLASH_ECC_EN_ERR_M (EFUSE_FLASH_ECC_EN_ERR_V << EFUSE_FLASH_ECC_EN_ERR_S) -#define EFUSE_FLASH_ECC_EN_ERR_V 0x00000001 -#define EFUSE_FLASH_ECC_EN_ERR_S 12 - -/* EFUSE_FLASH_PAGE_SIZE_ERR : RO; bitpos: [11:10]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_FLASH_PAGE_SIZE_ERR 0x00000003 -#define EFUSE_FLASH_PAGE_SIZE_ERR_M (EFUSE_FLASH_PAGE_SIZE_ERR_V << EFUSE_FLASH_PAGE_SIZE_ERR_S) -#define EFUSE_FLASH_PAGE_SIZE_ERR_V 0x00000003 -#define EFUSE_FLASH_PAGE_SIZE_ERR_S 10 - -/* EFUSE_FLASH_TYPE_ERR : RO; bitpos: [9]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_FLASH_TYPE_ERR (BIT(9)) -#define EFUSE_FLASH_TYPE_ERR_M (EFUSE_FLASH_TYPE_ERR_V << EFUSE_FLASH_TYPE_ERR_S) -#define EFUSE_FLASH_TYPE_ERR_V 0x00000001 -#define EFUSE_FLASH_TYPE_ERR_S 9 - -/* EFUSE_PIN_POWER_SELECTION_ERR : RO; bitpos: [8]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_PIN_POWER_SELECTION_ERR (BIT(8)) -#define EFUSE_PIN_POWER_SELECTION_ERR_M (EFUSE_PIN_POWER_SELECTION_ERR_V << EFUSE_PIN_POWER_SELECTION_ERR_S) -#define EFUSE_PIN_POWER_SELECTION_ERR_V 0x00000001 -#define EFUSE_PIN_POWER_SELECTION_ERR_S 8 - -/* EFUSE_UART_PRINT_CONTROL_ERR : RO; bitpos: [7:6]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_UART_PRINT_CONTROL_ERR 0x00000003 -#define EFUSE_UART_PRINT_CONTROL_ERR_M (EFUSE_UART_PRINT_CONTROL_ERR_V << EFUSE_UART_PRINT_CONTROL_ERR_S) -#define EFUSE_UART_PRINT_CONTROL_ERR_V 0x00000003 -#define EFUSE_UART_PRINT_CONTROL_ERR_S 6 - -/* EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR : RO; bitpos: [5]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR (BIT(5)) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_M (EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V << EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S) -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_V 0x00000001 -#define EFUSE_ENABLE_SECURITY_DOWNLOAD_ERR_S 5 - -/* EFUSE_DIS_USB_DOWNLOAD_MODE_ERR : RO; bitpos: [4]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR (BIT(4)) -#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_S) -#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_V 0x00000001 -#define EFUSE_DIS_USB_DOWNLOAD_MODE_ERR_S 4 - -/* EFUSE_FLASH_ECC_MODE_ERR : RO; bitpos: [3]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_FLASH_ECC_MODE_ERR (BIT(3)) -#define EFUSE_FLASH_ECC_MODE_ERR_M (EFUSE_FLASH_ECC_MODE_ERR_V << EFUSE_FLASH_ECC_MODE_ERR_S) -#define EFUSE_FLASH_ECC_MODE_ERR_V 0x00000001 -#define EFUSE_FLASH_ECC_MODE_ERR_S 3 - -/* EFUSE_UART_PRINT_CHANNEL_ERR : RO; bitpos: [2]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_UART_PRINT_CHANNEL_ERR (BIT(2)) -#define EFUSE_UART_PRINT_CHANNEL_ERR_M (EFUSE_UART_PRINT_CHANNEL_ERR_V << EFUSE_UART_PRINT_CHANNEL_ERR_S) -#define EFUSE_UART_PRINT_CHANNEL_ERR_V 0x00000001 -#define EFUSE_UART_PRINT_CHANNEL_ERR_S 2 - -/* EFUSE_DIS_LEGACY_SPI_BOOT_ERR : RO; bitpos: [1]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR (BIT(1)) -#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_M (EFUSE_DIS_LEGACY_SPI_BOOT_ERR_V << EFUSE_DIS_LEGACY_SPI_BOOT_ERR_S) -#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_V 0x00000001 -#define EFUSE_DIS_LEGACY_SPI_BOOT_ERR_S 1 - -/* EFUSE_DIS_DOWNLOAD_MODE_ERR : RO; bitpos: [0]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_DIS_DOWNLOAD_MODE_ERR (BIT(0)) -#define EFUSE_DIS_DOWNLOAD_MODE_ERR_M (EFUSE_DIS_DOWNLOAD_MODE_ERR_V << EFUSE_DIS_DOWNLOAD_MODE_ERR_S) -#define EFUSE_DIS_DOWNLOAD_MODE_ERR_V 0x00000001 -#define EFUSE_DIS_DOWNLOAD_MODE_ERR_S 0 - -/* EFUSE_RD_REPEAT_ERR4_REG register - * Programming error record register 4 of BLOCK0. - */ - -#define EFUSE_RD_REPEAT_ERR4_REG (DR_REG_EFUSE_BASE + 0x190) - -/* EFUSE_RPT4_RESERVED2_ERR : RO; bitpos: [23:0]; default: 0; - * If any bits in this filed are 1, then it indicates a programming error. - */ - -#define EFUSE_RPT4_RESERVED2_ERR 0x00ffffff -#define EFUSE_RPT4_RESERVED2_ERR_M (EFUSE_RPT4_RESERVED2_ERR_V << EFUSE_RPT4_RESERVED2_ERR_S) -#define EFUSE_RPT4_RESERVED2_ERR_V 0x00ffffff -#define EFUSE_RPT4_RESERVED2_ERR_S 0 - -/* EFUSE_RD_RS_ERR0_REG register - * Programming error record register 0 of BLOCK1-10. - */ - -#define EFUSE_RD_RS_ERR0_REG (DR_REG_EFUSE_BASE + 0x1c0) - -/* EFUSE_KEY4_FAIL : RO; bitpos: [31]; default: 0; - * 0: Means no failure and that the data of key4 is reliable 1: Means that - * programming key4 failed and the number of error bytes is over 6. - */ - -#define EFUSE_KEY4_FAIL (BIT(31)) -#define EFUSE_KEY4_FAIL_M (EFUSE_KEY4_FAIL_V << EFUSE_KEY4_FAIL_S) -#define EFUSE_KEY4_FAIL_V 0x00000001 -#define EFUSE_KEY4_FAIL_S 31 - -/* EFUSE_KEY4_ERR_NUM : RO; bitpos: [30:28]; default: 0; - * The value of this signal means the number of error bytes. - */ - -#define EFUSE_KEY4_ERR_NUM 0x00000007 -#define EFUSE_KEY4_ERR_NUM_M (EFUSE_KEY4_ERR_NUM_V << EFUSE_KEY4_ERR_NUM_S) -#define EFUSE_KEY4_ERR_NUM_V 0x00000007 -#define EFUSE_KEY4_ERR_NUM_S 28 - -/* EFUSE_KEY3_FAIL : RO; bitpos: [27]; default: 0; - * 0: Means no failure and that the data of key3 is reliable 1: Means that - * programming key3 failed and the number of error bytes is over 6. - */ - -#define EFUSE_KEY3_FAIL (BIT(27)) -#define EFUSE_KEY3_FAIL_M (EFUSE_KEY3_FAIL_V << EFUSE_KEY3_FAIL_S) -#define EFUSE_KEY3_FAIL_V 0x00000001 -#define EFUSE_KEY3_FAIL_S 27 - -/* EFUSE_KEY3_ERR_NUM : RO; bitpos: [26:24]; default: 0; - * The value of this signal means the number of error bytes. - */ - -#define EFUSE_KEY3_ERR_NUM 0x00000007 -#define EFUSE_KEY3_ERR_NUM_M (EFUSE_KEY3_ERR_NUM_V << EFUSE_KEY3_ERR_NUM_S) -#define EFUSE_KEY3_ERR_NUM_V 0x00000007 -#define EFUSE_KEY3_ERR_NUM_S 24 - -/* EFUSE_KEY2_FAIL : RO; bitpos: [23]; default: 0; - * 0: Means no failure and that the data of key2 is reliable 1: Means that - * programming key2 failed and the number of error bytes is over 6. - */ - -#define EFUSE_KEY2_FAIL (BIT(23)) -#define EFUSE_KEY2_FAIL_M (EFUSE_KEY2_FAIL_V << EFUSE_KEY2_FAIL_S) -#define EFUSE_KEY2_FAIL_V 0x00000001 -#define EFUSE_KEY2_FAIL_S 23 - -/* EFUSE_KEY2_ERR_NUM : RO; bitpos: [22:20]; default: 0; - * The value of this signal means the number of error bytes. - */ - -#define EFUSE_KEY2_ERR_NUM 0x00000007 -#define EFUSE_KEY2_ERR_NUM_M (EFUSE_KEY2_ERR_NUM_V << EFUSE_KEY2_ERR_NUM_S) -#define EFUSE_KEY2_ERR_NUM_V 0x00000007 -#define EFUSE_KEY2_ERR_NUM_S 20 - -/* EFUSE_KEY1_FAIL : RO; bitpos: [19]; default: 0; - * 0: Means no failure and that the data of key1 is reliable 1: Means that - * programming key1 failed and the number of error bytes is over 6. - */ - -#define EFUSE_KEY1_FAIL (BIT(19)) -#define EFUSE_KEY1_FAIL_M (EFUSE_KEY1_FAIL_V << EFUSE_KEY1_FAIL_S) -#define EFUSE_KEY1_FAIL_V 0x00000001 -#define EFUSE_KEY1_FAIL_S 19 - -/* EFUSE_KEY1_ERR_NUM : RO; bitpos: [18:16]; default: 0; - * The value of this signal means the number of error bytes. - */ - -#define EFUSE_KEY1_ERR_NUM 0x00000007 -#define EFUSE_KEY1_ERR_NUM_M (EFUSE_KEY1_ERR_NUM_V << EFUSE_KEY1_ERR_NUM_S) -#define EFUSE_KEY1_ERR_NUM_V 0x00000007 -#define EFUSE_KEY1_ERR_NUM_S 16 - -/* EFUSE_KEY0_FAIL : RO; bitpos: [15]; default: 0; - * 0: Means no failure and that the data of key0 is reliable 1: Means that - * programming key0 failed and the number of error bytes is over 6. - */ - -#define EFUSE_KEY0_FAIL (BIT(15)) -#define EFUSE_KEY0_FAIL_M (EFUSE_KEY0_FAIL_V << EFUSE_KEY0_FAIL_S) -#define EFUSE_KEY0_FAIL_V 0x00000001 -#define EFUSE_KEY0_FAIL_S 15 - -/* EFUSE_KEY0_ERR_NUM : RO; bitpos: [14:12]; default: 0; - * The value of this signal means the number of error bytes. - */ - -#define EFUSE_KEY0_ERR_NUM 0x00000007 -#define EFUSE_KEY0_ERR_NUM_M (EFUSE_KEY0_ERR_NUM_V << EFUSE_KEY0_ERR_NUM_S) -#define EFUSE_KEY0_ERR_NUM_V 0x00000007 -#define EFUSE_KEY0_ERR_NUM_S 12 - -/* EFUSE_USR_DATA_FAIL : RO; bitpos: [11]; default: 0; - * 0: Means no failure and that the user data is reliable 1: Means that - * programming user data failed and the number of error bytes is over 6. - */ - -#define EFUSE_USR_DATA_FAIL (BIT(11)) -#define EFUSE_USR_DATA_FAIL_M (EFUSE_USR_DATA_FAIL_V << EFUSE_USR_DATA_FAIL_S) -#define EFUSE_USR_DATA_FAIL_V 0x00000001 -#define EFUSE_USR_DATA_FAIL_S 11 - -/* EFUSE_USR_DATA_ERR_NUM : RO; bitpos: [10:8]; default: 0; - * The value of this signal means the number of error bytes. - */ - -#define EFUSE_USR_DATA_ERR_NUM 0x00000007 -#define EFUSE_USR_DATA_ERR_NUM_M (EFUSE_USR_DATA_ERR_NUM_V << EFUSE_USR_DATA_ERR_NUM_S) -#define EFUSE_USR_DATA_ERR_NUM_V 0x00000007 -#define EFUSE_USR_DATA_ERR_NUM_S 8 - -/* EFUSE_SYS_PART1_FAIL : RO; bitpos: [7]; default: 0; - * 0: Means no failure and that the data of system part1 is reliable 1: - * Means that programming user data failed and the number of error bytes is - * over 6. - */ - -#define EFUSE_SYS_PART1_FAIL (BIT(7)) -#define EFUSE_SYS_PART1_FAIL_M (EFUSE_SYS_PART1_FAIL_V << EFUSE_SYS_PART1_FAIL_S) -#define EFUSE_SYS_PART1_FAIL_V 0x00000001 -#define EFUSE_SYS_PART1_FAIL_S 7 - -/* EFUSE_SYS_PART1_NUM : RO; bitpos: [6:4]; default: 0; - * The value of this signal means the number of error bytes. - */ - -#define EFUSE_SYS_PART1_NUM 0x00000007 -#define EFUSE_SYS_PART1_NUM_M (EFUSE_SYS_PART1_NUM_V << EFUSE_SYS_PART1_NUM_S) -#define EFUSE_SYS_PART1_NUM_V 0x00000007 -#define EFUSE_SYS_PART1_NUM_S 4 - -/* EFUSE_MAC_SPI_8M_FAIL : RO; bitpos: [3]; default: 0; - * 0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means - * that programming user data failed and the number of error bytes is over 6. - */ - -#define EFUSE_MAC_SPI_8M_FAIL (BIT(3)) -#define EFUSE_MAC_SPI_8M_FAIL_M (EFUSE_MAC_SPI_8M_FAIL_V << EFUSE_MAC_SPI_8M_FAIL_S) -#define EFUSE_MAC_SPI_8M_FAIL_V 0x00000001 -#define EFUSE_MAC_SPI_8M_FAIL_S 3 - -/* EFUSE_MAC_SPI_8M_ERR_NUM : RO; bitpos: [2:0]; default: 0; - * The value of this signal means the number of error bytes. - */ - -#define EFUSE_MAC_SPI_8M_ERR_NUM 0x00000007 -#define EFUSE_MAC_SPI_8M_ERR_NUM_M (EFUSE_MAC_SPI_8M_ERR_NUM_V << EFUSE_MAC_SPI_8M_ERR_NUM_S) -#define EFUSE_MAC_SPI_8M_ERR_NUM_V 0x00000007 -#define EFUSE_MAC_SPI_8M_ERR_NUM_S 0 - -/* EFUSE_RD_RS_ERR1_REG register - * Programming error record register 1 of BLOCK1-10. - */ - -#define EFUSE_RD_RS_ERR1_REG (DR_REG_EFUSE_BASE + 0x1c4) - -/* EFUSE_SYS_PART2_FAIL : RO; bitpos: [7]; default: 0; - * 0: Means no failure and that the data of system part2 is reliable 1: - * Means that programming user data failed and the number of error bytes is - * over 6. - */ - -#define EFUSE_SYS_PART2_FAIL (BIT(7)) -#define EFUSE_SYS_PART2_FAIL_M (EFUSE_SYS_PART2_FAIL_V << EFUSE_SYS_PART2_FAIL_S) -#define EFUSE_SYS_PART2_FAIL_V 0x00000001 -#define EFUSE_SYS_PART2_FAIL_S 7 - -/* EFUSE_SYS_PART2_ERR_NUM : RO; bitpos: [6:4]; default: 0; - * The value of this signal means the number of error bytes. - */ - -#define EFUSE_SYS_PART2_ERR_NUM 0x00000007 -#define EFUSE_SYS_PART2_ERR_NUM_M (EFUSE_SYS_PART2_ERR_NUM_V << EFUSE_SYS_PART2_ERR_NUM_S) -#define EFUSE_SYS_PART2_ERR_NUM_V 0x00000007 -#define EFUSE_SYS_PART2_ERR_NUM_S 4 - -/* EFUSE_KEY5_FAIL : RO; bitpos: [3]; default: 0; - * 0: Means no failure and that the data of KEY5 is reliable 1: Means that - * programming user data failed and the number of error bytes is over 6. - */ - -#define EFUSE_KEY5_FAIL (BIT(3)) -#define EFUSE_KEY5_FAIL_M (EFUSE_KEY5_FAIL_V << EFUSE_KEY5_FAIL_S) -#define EFUSE_KEY5_FAIL_V 0x00000001 -#define EFUSE_KEY5_FAIL_S 3 - -/* EFUSE_KEY5_ERR_NUM : RO; bitpos: [2:0]; default: 0; - * The value of this signal means the number of error bytes. - */ - -#define EFUSE_KEY5_ERR_NUM 0x00000007 -#define EFUSE_KEY5_ERR_NUM_M (EFUSE_KEY5_ERR_NUM_V << EFUSE_KEY5_ERR_NUM_S) -#define EFUSE_KEY5_ERR_NUM_V 0x00000007 -#define EFUSE_KEY5_ERR_NUM_S 0 - -/* EFUSE_CLK_REG register - * eFuse clcok configuration register. - */ - -#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1c8) - -/* EFUSE_CLK_EN : R/W; bitpos: [16]; default: 0; - * Set this bit and force to enable clock signal of eFuse memory. - */ - -#define EFUSE_CLK_EN (BIT(16)) -#define EFUSE_CLK_EN_M (EFUSE_CLK_EN_V << EFUSE_CLK_EN_S) -#define EFUSE_CLK_EN_V 0x00000001 -#define EFUSE_CLK_EN_S 16 - -/* EFUSE_EFUSE_MEM_FORCE_PU : R/W; bitpos: [2]; default: 0; - * Set this bit to force eFuse SRAM into working mode. - */ - -#define EFUSE_EFUSE_MEM_FORCE_PU (BIT(2)) -#define EFUSE_EFUSE_MEM_FORCE_PU_M (EFUSE_EFUSE_MEM_FORCE_PU_V << EFUSE_EFUSE_MEM_FORCE_PU_S) -#define EFUSE_EFUSE_MEM_FORCE_PU_V 0x00000001 -#define EFUSE_EFUSE_MEM_FORCE_PU_S 2 - -/* EFUSE_MEM_CLK_FORCE_ON : R/W; bitpos: [1]; default: 1; - * Set this bit and force to activate clock signal of eFuse SRAM. - */ - -#define EFUSE_MEM_CLK_FORCE_ON (BIT(1)) -#define EFUSE_MEM_CLK_FORCE_ON_M (EFUSE_MEM_CLK_FORCE_ON_V << EFUSE_MEM_CLK_FORCE_ON_S) -#define EFUSE_MEM_CLK_FORCE_ON_V 0x00000001 -#define EFUSE_MEM_CLK_FORCE_ON_S 1 - -/* EFUSE_EFUSE_MEM_FORCE_PD : R/W; bitpos: [0]; default: 0; - * Set this bit to force eFuse SRAM into power-saving mode. - */ - -#define EFUSE_EFUSE_MEM_FORCE_PD (BIT(0)) -#define EFUSE_EFUSE_MEM_FORCE_PD_M (EFUSE_EFUSE_MEM_FORCE_PD_V << EFUSE_EFUSE_MEM_FORCE_PD_S) -#define EFUSE_EFUSE_MEM_FORCE_PD_V 0x00000001 -#define EFUSE_EFUSE_MEM_FORCE_PD_S 0 - -/* EFUSE_CONF_REG register - * eFuse operation mode configuration register - */ - -#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc) - -/* EFUSE_OP_CODE : R/W; bitpos: [15:0]; default: 0; - * 0x5A5A: Operate programming command 0x5AA5: Operate read command. - */ - -#define EFUSE_OP_CODE 0x0000ffff -#define EFUSE_OP_CODE_M (EFUSE_OP_CODE_V << EFUSE_OP_CODE_S) -#define EFUSE_OP_CODE_V 0x0000ffff -#define EFUSE_OP_CODE_S 0 - -/* EFUSE_STATUS_REG register - * eFuse status register. - */ - -#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1d0) - -/* EFUSE_REPEAT_ERR_CNT : RO; bitpos: [17:10]; default: 0; - * Indicates the number of error bits during programming BLOCK0. - */ - -#define EFUSE_REPEAT_ERR_CNT 0x000000ff -#define EFUSE_REPEAT_ERR_CNT_M (EFUSE_REPEAT_ERR_CNT_V << EFUSE_REPEAT_ERR_CNT_S) -#define EFUSE_REPEAT_ERR_CNT_V 0x000000ff -#define EFUSE_REPEAT_ERR_CNT_S 10 - -/* EFUSE_OTP_VDDQ_IS_SW : RO; bitpos: [9]; default: 0; - * The value of OTP_VDDQ_IS_SW. - */ - -#define EFUSE_OTP_VDDQ_IS_SW (BIT(9)) -#define EFUSE_OTP_VDDQ_IS_SW_M (EFUSE_OTP_VDDQ_IS_SW_V << EFUSE_OTP_VDDQ_IS_SW_S) -#define EFUSE_OTP_VDDQ_IS_SW_V 0x00000001 -#define EFUSE_OTP_VDDQ_IS_SW_S 9 - -/* EFUSE_OTP_PGENB_SW : RO; bitpos: [8]; default: 0; - * The value of OTP_PGENB_SW. - */ - -#define EFUSE_OTP_PGENB_SW (BIT(8)) -#define EFUSE_OTP_PGENB_SW_M (EFUSE_OTP_PGENB_SW_V << EFUSE_OTP_PGENB_SW_S) -#define EFUSE_OTP_PGENB_SW_V 0x00000001 -#define EFUSE_OTP_PGENB_SW_S 8 - -/* EFUSE_OTP_CSB_SW : RO; bitpos: [7]; default: 0; - * The value of OTP_CSB_SW. - */ - -#define EFUSE_OTP_CSB_SW (BIT(7)) -#define EFUSE_OTP_CSB_SW_M (EFUSE_OTP_CSB_SW_V << EFUSE_OTP_CSB_SW_S) -#define EFUSE_OTP_CSB_SW_V 0x00000001 -#define EFUSE_OTP_CSB_SW_S 7 - -/* EFUSE_OTP_STROBE_SW : RO; bitpos: [6]; default: 0; - * The value of OTP_STROBE_SW. - */ - -#define EFUSE_OTP_STROBE_SW (BIT(6)) -#define EFUSE_OTP_STROBE_SW_M (EFUSE_OTP_STROBE_SW_V << EFUSE_OTP_STROBE_SW_S) -#define EFUSE_OTP_STROBE_SW_V 0x00000001 -#define EFUSE_OTP_STROBE_SW_S 6 - -/* EFUSE_OTP_VDDQ_C_SYNC2 : RO; bitpos: [5]; default: 0; - * The value of OTP_VDDQ_C_SYNC2. - */ - -#define EFUSE_OTP_VDDQ_C_SYNC2 (BIT(5)) -#define EFUSE_OTP_VDDQ_C_SYNC2_M (EFUSE_OTP_VDDQ_C_SYNC2_V << EFUSE_OTP_VDDQ_C_SYNC2_S) -#define EFUSE_OTP_VDDQ_C_SYNC2_V 0x00000001 -#define EFUSE_OTP_VDDQ_C_SYNC2_S 5 - -/* EFUSE_OTP_LOAD_SW : RO; bitpos: [4]; default: 0; - * The value of OTP_LOAD_SW. - */ - -#define EFUSE_OTP_LOAD_SW (BIT(4)) -#define EFUSE_OTP_LOAD_SW_M (EFUSE_OTP_LOAD_SW_V << EFUSE_OTP_LOAD_SW_S) -#define EFUSE_OTP_LOAD_SW_V 0x00000001 -#define EFUSE_OTP_LOAD_SW_S 4 - -/* EFUSE_STATE : RO; bitpos: [3:0]; default: 0; - * Indicates the state of the eFuse state machine. - */ - -#define EFUSE_STATE 0x0000000f -#define EFUSE_STATE_M (EFUSE_STATE_V << EFUSE_STATE_S) -#define EFUSE_STATE_V 0x0000000f -#define EFUSE_STATE_S 0 - -/* EFUSE_CMD_REG register - * eFuse command register. - */ - -#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1d4) - -/* EFUSE_BLK_NUM : R/W; bitpos: [5:2]; default: 0; - * The serial number of the block to be programmed. Value 0-10 corresponds - * to block number 0-10, respectively. - */ - -#define EFUSE_BLK_NUM 0x0000000f -#define EFUSE_BLK_NUM_M (EFUSE_BLK_NUM_V << EFUSE_BLK_NUM_S) -#define EFUSE_BLK_NUM_V 0x0000000f -#define EFUSE_BLK_NUM_S 2 - -/* EFUSE_PGM_CMD : R/WS/SC; bitpos: [1]; default: 0; - * Set this bit to send programming command. - */ - -#define EFUSE_PGM_CMD (BIT(1)) -#define EFUSE_PGM_CMD_M (EFUSE_PGM_CMD_V << EFUSE_PGM_CMD_S) -#define EFUSE_PGM_CMD_V 0x00000001 -#define EFUSE_PGM_CMD_S 1 - -/* EFUSE_READ_CMD : R/WS/SC; bitpos: [0]; default: 0; - * Set this bit to send read command. - */ - -#define EFUSE_READ_CMD (BIT(0)) -#define EFUSE_READ_CMD_M (EFUSE_READ_CMD_V << EFUSE_READ_CMD_S) -#define EFUSE_READ_CMD_V 0x00000001 -#define EFUSE_READ_CMD_S 0 - -/* EFUSE_INT_RAW_REG register - * eFuse raw interrupt register. - */ - -#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1d8) - -/* EFUSE_PGM_DONE_INT_RAW : R/WC/SS; bitpos: [1]; default: 0; - * The raw bit signal for pgm_done interrupt. - */ - -#define EFUSE_PGM_DONE_INT_RAW (BIT(1)) -#define EFUSE_PGM_DONE_INT_RAW_M (EFUSE_PGM_DONE_INT_RAW_V << EFUSE_PGM_DONE_INT_RAW_S) -#define EFUSE_PGM_DONE_INT_RAW_V 0x00000001 -#define EFUSE_PGM_DONE_INT_RAW_S 1 - -/* EFUSE_READ_DONE_INT_RAW : R/WC/SS; bitpos: [0]; default: 0; - * The raw bit signal for read_done interrupt. - */ - -#define EFUSE_READ_DONE_INT_RAW (BIT(0)) -#define EFUSE_READ_DONE_INT_RAW_M (EFUSE_READ_DONE_INT_RAW_V << EFUSE_READ_DONE_INT_RAW_S) -#define EFUSE_READ_DONE_INT_RAW_V 0x00000001 -#define EFUSE_READ_DONE_INT_RAW_S 0 - -/* EFUSE_INT_ST_REG register - * eFuse interrupt status register. - */ - -#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1dc) - -/* EFUSE_PGM_DONE_INT_ST : RO; bitpos: [1]; default: 0; - * The status signal for pgm_done interrupt. - */ - -#define EFUSE_PGM_DONE_INT_ST (BIT(1)) -#define EFUSE_PGM_DONE_INT_ST_M (EFUSE_PGM_DONE_INT_ST_V << EFUSE_PGM_DONE_INT_ST_S) -#define EFUSE_PGM_DONE_INT_ST_V 0x00000001 -#define EFUSE_PGM_DONE_INT_ST_S 1 - -/* EFUSE_READ_DONE_INT_ST : RO; bitpos: [0]; default: 0; - * The status signal for read_done interrupt. - */ - -#define EFUSE_READ_DONE_INT_ST (BIT(0)) -#define EFUSE_READ_DONE_INT_ST_M (EFUSE_READ_DONE_INT_ST_V << EFUSE_READ_DONE_INT_ST_S) -#define EFUSE_READ_DONE_INT_ST_V 0x00000001 -#define EFUSE_READ_DONE_INT_ST_S 0 - -/* EFUSE_INT_ENA_REG register - * eFuse interrupt enable register. - */ - -#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1e0) - -/* EFUSE_PGM_DONE_INT_ENA : R/W; bitpos: [1]; default: 0; - * The enable signal for pgm_done interrupt. - */ - -#define EFUSE_PGM_DONE_INT_ENA (BIT(1)) -#define EFUSE_PGM_DONE_INT_ENA_M (EFUSE_PGM_DONE_INT_ENA_V << EFUSE_PGM_DONE_INT_ENA_S) -#define EFUSE_PGM_DONE_INT_ENA_V 0x00000001 -#define EFUSE_PGM_DONE_INT_ENA_S 1 - -/* EFUSE_READ_DONE_INT_ENA : R/W; bitpos: [0]; default: 0; - * The enable signal for read_done interrupt. - */ - -#define EFUSE_READ_DONE_INT_ENA (BIT(0)) -#define EFUSE_READ_DONE_INT_ENA_M (EFUSE_READ_DONE_INT_ENA_V << EFUSE_READ_DONE_INT_ENA_S) -#define EFUSE_READ_DONE_INT_ENA_V 0x00000001 -#define EFUSE_READ_DONE_INT_ENA_S 0 - -/* EFUSE_INT_CLR_REG register - * eFuse interrupt clear register. - */ - -#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1e4) - -/* EFUSE_PGM_DONE_INT_CLR : WO; bitpos: [1]; default: 0; - * The clear signal for pgm_done interrupt. - */ - -#define EFUSE_PGM_DONE_INT_CLR (BIT(1)) -#define EFUSE_PGM_DONE_INT_CLR_M (EFUSE_PGM_DONE_INT_CLR_V << EFUSE_PGM_DONE_INT_CLR_S) -#define EFUSE_PGM_DONE_INT_CLR_V 0x00000001 -#define EFUSE_PGM_DONE_INT_CLR_S 1 - -/* EFUSE_READ_DONE_INT_CLR : WO; bitpos: [0]; default: 0; - * The clear signal for read_done interrupt. - */ - -#define EFUSE_READ_DONE_INT_CLR (BIT(0)) -#define EFUSE_READ_DONE_INT_CLR_M (EFUSE_READ_DONE_INT_CLR_V << EFUSE_READ_DONE_INT_CLR_S) -#define EFUSE_READ_DONE_INT_CLR_V 0x00000001 -#define EFUSE_READ_DONE_INT_CLR_S 0 - -/* EFUSE_DAC_CONF_REG register - * Controls the eFuse programming voltage. - */ - -#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1e8) - -/* EFUSE_OE_CLR : R/W; bitpos: [17]; default: 0; - * Reduces the power supply of the programming voltage. - */ - -#define EFUSE_OE_CLR (BIT(17)) -#define EFUSE_OE_CLR_M (EFUSE_OE_CLR_V << EFUSE_OE_CLR_S) -#define EFUSE_OE_CLR_V 0x00000001 -#define EFUSE_OE_CLR_S 17 - -/* EFUSE_DAC_NUM : R/W; bitpos: [16:9]; default: 255; - * Controls the rising period of the programming voltage. - */ - -#define EFUSE_DAC_NUM 0x000000ff -#define EFUSE_DAC_NUM_M (EFUSE_DAC_NUM_V << EFUSE_DAC_NUM_S) -#define EFUSE_DAC_NUM_V 0x000000ff -#define EFUSE_DAC_NUM_S 9 - -/* EFUSE_DAC_CLK_PAD_SEL : R/W; bitpos: [8]; default: 0; - * Don't care. - */ - -#define EFUSE_DAC_CLK_PAD_SEL (BIT(8)) -#define EFUSE_DAC_CLK_PAD_SEL_M (EFUSE_DAC_CLK_PAD_SEL_V << EFUSE_DAC_CLK_PAD_SEL_S) -#define EFUSE_DAC_CLK_PAD_SEL_V 0x00000001 -#define EFUSE_DAC_CLK_PAD_SEL_S 8 - -/* EFUSE_DAC_CLK_DIV : R/W; bitpos: [7:0]; default: 28; - * Controls the division factor of the rising clock of the programming - * voltage. - */ - -#define EFUSE_DAC_CLK_DIV 0x000000ff -#define EFUSE_DAC_CLK_DIV_M (EFUSE_DAC_CLK_DIV_V << EFUSE_DAC_CLK_DIV_S) -#define EFUSE_DAC_CLK_DIV_V 0x000000ff -#define EFUSE_DAC_CLK_DIV_S 0 - -/* EFUSE_RD_TIM_CONF_REG register - * Configures read timing parameters. - */ - -#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1ec) - -/* EFUSE_READ_INIT_NUM : R/W; bitpos: [31:24]; default: 18; - * Configures the initial read time of eFuse. - */ - -#define EFUSE_READ_INIT_NUM 0x000000ff -#define EFUSE_READ_INIT_NUM_M (EFUSE_READ_INIT_NUM_V << EFUSE_READ_INIT_NUM_S) -#define EFUSE_READ_INIT_NUM_V 0x000000ff -#define EFUSE_READ_INIT_NUM_S 24 - -/* EFUSE_WR_TIM_CONF1_REG register - * Configurarion register 1 of eFuse programming timing parameters. - */ - -#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1f4) - -/* EFUSE_PWR_ON_NUM : R/W; bitpos: [23:8]; default: 10368; - * Configures the power up time for VDDQ. - */ - -#define EFUSE_PWR_ON_NUM 0x0000ffff -#define EFUSE_PWR_ON_NUM_M (EFUSE_PWR_ON_NUM_V << EFUSE_PWR_ON_NUM_S) -#define EFUSE_PWR_ON_NUM_V 0x0000ffff -#define EFUSE_PWR_ON_NUM_S 8 - -/* EFUSE_WR_TIM_CONF2_REG register - * Configurarion register 2 of eFuse programming timing parameters. - */ - -#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1f8) - -/* EFUSE_PWR_OFF_NUM : R/W; bitpos: [15:0]; default: 400; - * Configures the power outage time for VDDQ. - */ - -#define EFUSE_PWR_OFF_NUM 0x0000ffff -#define EFUSE_PWR_OFF_NUM_M (EFUSE_PWR_OFF_NUM_V << EFUSE_PWR_OFF_NUM_S) -#define EFUSE_PWR_OFF_NUM_V 0x0000ffff -#define EFUSE_PWR_OFF_NUM_S 0 - -/* EFUSE_DATE_REG register - * eFuse version register. - */ - -#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1fc) - -/* EFUSE_DATE : R/W; bitpos: [27:0]; default: 34607760; - * Stores eFuse version. - */ - -#define EFUSE_DATE 0x0fffffff -#define EFUSE_DATE_M (EFUSE_DATE_V << EFUSE_DATE_S) -#define EFUSE_DATE_V 0x0fffffff -#define EFUSE_DATE_S 0 - -#endif /* __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_EFUSE_H */ diff --git a/arch/xtensa/src/esp32s3/hardware/esp32s3_rtccntl.h b/arch/xtensa/src/esp32s3/hardware/esp32s3_rtccntl.h deleted file mode 100644 index 7fc7ef4b385be..0000000000000 --- a/arch/xtensa/src/esp32s3/hardware/esp32s3_rtccntl.h +++ /dev/null @@ -1,5914 +0,0 @@ -/**************************************************************************** - * arch/xtensa/src/esp32s3/hardware/esp32s3_rtccntl.h - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - ****************************************************************************/ - -#ifndef __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_RTCCNTL_H -#define __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_RTCCNTL_H - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -#include "esp32s3_soc.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Offset relative to each watchdog timer instance memory base */ - -#define RWDT_CONFIG0_OFFSET 0x0098 -#define XTWDT_CONFIG0_OFFSET 0x0060 - -/* RWDT */ - -#define RWDT_STAGE0_TIMEOUT_OFFSET 0x009C -#define RWDT_STAGE1_TIMEOUT_OFFSET 0x00A0 -#define RWDT_STAGE2_TIMEOUT_OFFSET 0x00A4 -#define RWDT_STAGE3_TIMEOUT_OFFSET 0x00A8 -#define RWDT_FEED_OFFSET 0x00AC -#define RWDT_WP_REG 0x00B0 -#define RWDT_INT_ENA_REG_OFFSET 0x0040 -#define RWDT_INT_CLR_REG_OFFSET 0x004c - -/* XTWDT */ - -#define XTWDT_TIMEOUT_OFFSET 0x00f8 -#define XTWDT_CLK_PRESCALE_OFFSET 0x00f4 -#define XTWDT_INT_ENA_REG_OFFSET 0x0040 - -/* The value that needs to be written to RTC_CNTL_WDT_WKEY to - * write-enable the wdt registers - */ - -#define RTC_CNTL_WDT_WKEY_VALUE 0x50d83aa1 - -/* The value that needs to be written to RTC_CNTL_SWD_WPROTECT_REG - * to write-enable the wdt registers - */ - -#define RTC_CNTL_SWD_WKEY_VALUE 0x8f1d312a - -/* Possible values for RTC_CNTL_WDT_CPU_RESET_LENGTH - * and RTC_CNTL_WDT_SYS_RESET_LENGTH - */ - -#define RTC_WDT_RESET_LENGTH_100_NS 0 -#define RTC_WDT_RESET_LENGTH_200_NS 1 -#define RTC_WDT_RESET_LENGTH_300_NS 2 -#define RTC_WDT_RESET_LENGTH_400_NS 3 -#define RTC_WDT_RESET_LENGTH_500_NS 4 -#define RTC_WDT_RESET_LENGTH_800_NS 5 -#define RTC_WDT_RESET_LENGTH_1600_NS 6 -#define RTC_WDT_RESET_LENGTH_3200_NS 7 - -#define RTC_CNTL_TIME0_REG RTC_CNTL_RTC_TIME_LOW0_REG -#define RTC_CNTL_TIME1_REG RTC_CNTL_RTC_TIME_HIGH0_REG - -/* RTC_CNTL_RTC_OPTIONS0_REG register - * RTC common configure register - */ - -#define RTC_CNTL_RTC_OPTIONS0_REG (DR_REG_RTCCNTL_BASE + 0x0) - -/* RTC_CNTL_SW_SYS_RST : WO; bitpos: [31]; default: 0; - * SW system reset - */ - -#define RTC_CNTL_SW_SYS_RST (BIT(31)) -#define RTC_CNTL_SW_SYS_RST_M (RTC_CNTL_SW_SYS_RST_V << RTC_CNTL_SW_SYS_RST_S) -#define RTC_CNTL_SW_SYS_RST_V 0x00000001 -#define RTC_CNTL_SW_SYS_RST_S 31 - -/* RTC_CNTL_DG_WRAP_FORCE_NORST : R/W; bitpos: [30]; default: 0; - * digital core force no reset in deep sleep - */ - -#define RTC_CNTL_DG_WRAP_FORCE_NORST (BIT(30)) -#define RTC_CNTL_DG_WRAP_FORCE_NORST_M (RTC_CNTL_DG_WRAP_FORCE_NORST_V << RTC_CNTL_DG_WRAP_FORCE_NORST_S) -#define RTC_CNTL_DG_WRAP_FORCE_NORST_V 0x00000001 -#define RTC_CNTL_DG_WRAP_FORCE_NORST_S 30 - -/* RTC_CNTL_DG_WRAP_FORCE_RST : R/W; bitpos: [29]; default: 0; - * digital wrap force reset in deep sleep - */ - -#define RTC_CNTL_DG_WRAP_FORCE_RST (BIT(29)) -#define RTC_CNTL_DG_WRAP_FORCE_RST_M (RTC_CNTL_DG_WRAP_FORCE_RST_V << RTC_CNTL_DG_WRAP_FORCE_RST_S) -#define RTC_CNTL_DG_WRAP_FORCE_RST_V 0x00000001 -#define RTC_CNTL_DG_WRAP_FORCE_RST_S 29 - -/* RTC_CNTL_ANALOG_FORCE_NOISO : R/W; bitpos: [28]; default: 1; - * No public - */ - -#define RTC_CNTL_ANALOG_FORCE_NOISO (BIT(28)) -#define RTC_CNTL_ANALOG_FORCE_NOISO_M (RTC_CNTL_ANALOG_FORCE_NOISO_V << RTC_CNTL_ANALOG_FORCE_NOISO_S) -#define RTC_CNTL_ANALOG_FORCE_NOISO_V 0x00000001 -#define RTC_CNTL_ANALOG_FORCE_NOISO_S 28 - -/* RTC_CNTL_PLL_FORCE_NOISO : R/W; bitpos: [27]; default: 1; - * No public - */ - -#define RTC_CNTL_PLL_FORCE_NOISO (BIT(27)) -#define RTC_CNTL_PLL_FORCE_NOISO_M (RTC_CNTL_PLL_FORCE_NOISO_V << RTC_CNTL_PLL_FORCE_NOISO_S) -#define RTC_CNTL_PLL_FORCE_NOISO_V 0x00000001 -#define RTC_CNTL_PLL_FORCE_NOISO_S 27 - -/* RTC_CNTL_XTL_FORCE_NOISO : R/W; bitpos: [26]; default: 1; - * No public - */ - -#define RTC_CNTL_XTL_FORCE_NOISO (BIT(26)) -#define RTC_CNTL_XTL_FORCE_NOISO_M (RTC_CNTL_XTL_FORCE_NOISO_V << RTC_CNTL_XTL_FORCE_NOISO_S) -#define RTC_CNTL_XTL_FORCE_NOISO_V 0x00000001 -#define RTC_CNTL_XTL_FORCE_NOISO_S 26 - -/* RTC_CNTL_ANALOG_FORCE_ISO : R/W; bitpos: [25]; default: 0; - * No public - */ - -#define RTC_CNTL_ANALOG_FORCE_ISO (BIT(25)) -#define RTC_CNTL_ANALOG_FORCE_ISO_M (RTC_CNTL_ANALOG_FORCE_ISO_V << RTC_CNTL_ANALOG_FORCE_ISO_S) -#define RTC_CNTL_ANALOG_FORCE_ISO_V 0x00000001 -#define RTC_CNTL_ANALOG_FORCE_ISO_S 25 - -/* RTC_CNTL_PLL_FORCE_ISO : R/W; bitpos: [24]; default: 0; - * No public - */ - -#define RTC_CNTL_PLL_FORCE_ISO (BIT(24)) -#define RTC_CNTL_PLL_FORCE_ISO_M (RTC_CNTL_PLL_FORCE_ISO_V << RTC_CNTL_PLL_FORCE_ISO_S) -#define RTC_CNTL_PLL_FORCE_ISO_V 0x00000001 -#define RTC_CNTL_PLL_FORCE_ISO_S 24 - -/* RTC_CNTL_XTL_FORCE_ISO : R/W; bitpos: [23]; default: 0; - * No public - */ - -#define RTC_CNTL_XTL_FORCE_ISO (BIT(23)) -#define RTC_CNTL_XTL_FORCE_ISO_M (RTC_CNTL_XTL_FORCE_ISO_V << RTC_CNTL_XTL_FORCE_ISO_S) -#define RTC_CNTL_XTL_FORCE_ISO_V 0x00000001 -#define RTC_CNTL_XTL_FORCE_ISO_S 23 - -/* RTC_CNTL_XTL_EN_WAIT : R/W; bitpos: [17:14]; default: 2; - * wait bias_sleep and current source wakeup - */ - -#define RTC_CNTL_XTL_EN_WAIT 0x0000000f -#define RTC_CNTL_XTL_EN_WAIT_M (RTC_CNTL_XTL_EN_WAIT_V << RTC_CNTL_XTL_EN_WAIT_S) -#define RTC_CNTL_XTL_EN_WAIT_V 0x0000000f -#define RTC_CNTL_XTL_EN_WAIT_S 14 - -/* RTC_CNTL_XTL_FORCE_PU : R/W; bitpos: [13]; default: 1; - * crystall force power up - */ - -#define RTC_CNTL_XTL_FORCE_PU (BIT(13)) -#define RTC_CNTL_XTL_FORCE_PU_M (RTC_CNTL_XTL_FORCE_PU_V << RTC_CNTL_XTL_FORCE_PU_S) -#define RTC_CNTL_XTL_FORCE_PU_V 0x00000001 -#define RTC_CNTL_XTL_FORCE_PU_S 13 - -/* RTC_CNTL_XTL_FORCE_PD : R/W; bitpos: [12]; default: 0; - * crystall force power down - */ - -#define RTC_CNTL_XTL_FORCE_PD (BIT(12)) -#define RTC_CNTL_XTL_FORCE_PD_M (RTC_CNTL_XTL_FORCE_PD_V << RTC_CNTL_XTL_FORCE_PD_S) -#define RTC_CNTL_XTL_FORCE_PD_V 0x00000001 -#define RTC_CNTL_XTL_FORCE_PD_S 12 - -/* RTC_CNTL_BBPLL_FORCE_PU : R/W; bitpos: [11]; default: 0; - * BB_PLL force power up - */ - -#define RTC_CNTL_BBPLL_FORCE_PU (BIT(11)) -#define RTC_CNTL_BBPLL_FORCE_PU_M (RTC_CNTL_BBPLL_FORCE_PU_V << RTC_CNTL_BBPLL_FORCE_PU_S) -#define RTC_CNTL_BBPLL_FORCE_PU_V 0x00000001 -#define RTC_CNTL_BBPLL_FORCE_PU_S 11 - -/* RTC_CNTL_BBPLL_FORCE_PD : R/W; bitpos: [10]; default: 0; - * BB_PLL force power down - */ - -#define RTC_CNTL_BBPLL_FORCE_PD (BIT(10)) -#define RTC_CNTL_BBPLL_FORCE_PD_M (RTC_CNTL_BBPLL_FORCE_PD_V << RTC_CNTL_BBPLL_FORCE_PD_S) -#define RTC_CNTL_BBPLL_FORCE_PD_V 0x00000001 -#define RTC_CNTL_BBPLL_FORCE_PD_S 10 - -/* RTC_CNTL_BBPLL_I2C_FORCE_PU : R/W; bitpos: [9]; default: 0; - * BB_PLL_I2C force power up - */ - -#define RTC_CNTL_BBPLL_I2C_FORCE_PU (BIT(9)) -#define RTC_CNTL_BBPLL_I2C_FORCE_PU_M (RTC_CNTL_BBPLL_I2C_FORCE_PU_V << RTC_CNTL_BBPLL_I2C_FORCE_PU_S) -#define RTC_CNTL_BBPLL_I2C_FORCE_PU_V 0x00000001 -#define RTC_CNTL_BBPLL_I2C_FORCE_PU_S 9 - -/* RTC_CNTL_BBPLL_I2C_FORCE_PD : R/W; bitpos: [8]; default: 0; - * BB_PLL _I2C force power down - */ - -#define RTC_CNTL_BBPLL_I2C_FORCE_PD (BIT(8)) -#define RTC_CNTL_BBPLL_I2C_FORCE_PD_M (RTC_CNTL_BBPLL_I2C_FORCE_PD_V << RTC_CNTL_BBPLL_I2C_FORCE_PD_S) -#define RTC_CNTL_BBPLL_I2C_FORCE_PD_V 0x00000001 -#define RTC_CNTL_BBPLL_I2C_FORCE_PD_S 8 - -/* RTC_CNTL_BB_I2C_FORCE_PU : R/W; bitpos: [7]; default: 0; - * BB_I2C force power up - */ - -#define RTC_CNTL_BB_I2C_FORCE_PU (BIT(7)) -#define RTC_CNTL_BB_I2C_FORCE_PU_M (RTC_CNTL_BB_I2C_FORCE_PU_V << RTC_CNTL_BB_I2C_FORCE_PU_S) -#define RTC_CNTL_BB_I2C_FORCE_PU_V 0x00000001 -#define RTC_CNTL_BB_I2C_FORCE_PU_S 7 - -/* RTC_CNTL_BB_I2C_FORCE_PD : R/W; bitpos: [6]; default: 0; - * BB_I2C force power down - */ - -#define RTC_CNTL_BB_I2C_FORCE_PD (BIT(6)) -#define RTC_CNTL_BB_I2C_FORCE_PD_M (RTC_CNTL_BB_I2C_FORCE_PD_V << RTC_CNTL_BB_I2C_FORCE_PD_S) -#define RTC_CNTL_BB_I2C_FORCE_PD_V 0x00000001 -#define RTC_CNTL_BB_I2C_FORCE_PD_S 6 - -/* RTC_CNTL_SW_PROCPU_RST : WO; bitpos: [5]; default: 0; - * PRO CPU SW reset - */ - -#define RTC_CNTL_SW_PROCPU_RST (BIT(5)) -#define RTC_CNTL_SW_PROCPU_RST_M (RTC_CNTL_SW_PROCPU_RST_V << RTC_CNTL_SW_PROCPU_RST_S) -#define RTC_CNTL_SW_PROCPU_RST_V 0x00000001 -#define RTC_CNTL_SW_PROCPU_RST_S 5 - -/* RTC_CNTL_SW_APPCPU_RST : WO; bitpos: [4]; default: 0; - * APP CPU SW reset - */ - -#define RTC_CNTL_SW_APPCPU_RST (BIT(4)) -#define RTC_CNTL_SW_APPCPU_RST_M (RTC_CNTL_SW_APPCPU_RST_V << RTC_CNTL_SW_APPCPU_RST_S) -#define RTC_CNTL_SW_APPCPU_RST_V 0x00000001 -#define RTC_CNTL_SW_APPCPU_RST_S 4 - -/* RTC_CNTL_SW_STALL_PROCPU_C0 : R/W; bitpos: [3:2]; default: 0; - * {reg_sw_stall_procpu_c1[5:0], reg_sw_stall_procpu_c0[1:0]} == 0x86 will - * stall PRO CPU - */ - -#define RTC_CNTL_SW_STALL_PROCPU_C0 0x00000003 -#define RTC_CNTL_SW_STALL_PROCPU_C0_M (RTC_CNTL_SW_STALL_PROCPU_C0_V << RTC_CNTL_SW_STALL_PROCPU_C0_S) -#define RTC_CNTL_SW_STALL_PROCPU_C0_V 0x00000003 -#define RTC_CNTL_SW_STALL_PROCPU_C0_S 2 - -/* RTC_CNTL_SW_STALL_APPCPU_C0 : R/W; bitpos: [1:0]; default: 0; - * {reg_sw_stall_appcpu_c1[5:0], reg_sw_stall_appcpu_c0[1:0]} == 0x86 will - * stall APP CPU - */ - -#define RTC_CNTL_SW_STALL_APPCPU_C0 0x00000003 -#define RTC_CNTL_SW_STALL_APPCPU_C0_M (RTC_CNTL_SW_STALL_APPCPU_C0_V << RTC_CNTL_SW_STALL_APPCPU_C0_S) -#define RTC_CNTL_SW_STALL_APPCPU_C0_V 0x00000003 -#define RTC_CNTL_SW_STALL_APPCPU_C0_S 0 - -/* RTC_CNTL_RTC_SLP_TIMER0_REG register - * configure min sleep time - */ - -#define RTC_CNTL_RTC_SLP_TIMER0_REG (DR_REG_RTCCNTL_BASE + 0x4) - -/* RTC_CNTL_SLP_VAL_LO : R/W; bitpos: [31:0]; default: 0; - * RTC sleep timer low 32 bits - */ - -#define RTC_CNTL_SLP_VAL_LO 0xffffffff -#define RTC_CNTL_SLP_VAL_LO_M (RTC_CNTL_SLP_VAL_LO_V << RTC_CNTL_SLP_VAL_LO_S) -#define RTC_CNTL_SLP_VAL_LO_V 0xffffffff -#define RTC_CNTL_SLP_VAL_LO_S 0 - -/* RTC_CNTL_RTC_SLP_TIMER1_REG register - * configure sleep time hi - */ - -#define RTC_CNTL_RTC_SLP_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x8) - -/* RTC_CNTL_RTC_MAIN_TIMER_ALARM_EN : WO; bitpos: [16]; default: 0; - * timer alarm enable bit - */ - -#define RTC_CNTL_RTC_MAIN_TIMER_ALARM_EN (BIT(16)) -#define RTC_CNTL_RTC_MAIN_TIMER_ALARM_EN_M (RTC_CNTL_RTC_MAIN_TIMER_ALARM_EN_V << RTC_CNTL_RTC_MAIN_TIMER_ALARM_EN_S) -#define RTC_CNTL_RTC_MAIN_TIMER_ALARM_EN_V 0x00000001 -#define RTC_CNTL_RTC_MAIN_TIMER_ALARM_EN_S 16 - -/* RTC_CNTL_SLP_VAL_HI : R/W; bitpos: [15:0]; default: 0; - * RTC sleep timer high 16 bits - */ - -#define RTC_CNTL_SLP_VAL_HI 0x0000ffff -#define RTC_CNTL_SLP_VAL_HI_M (RTC_CNTL_SLP_VAL_HI_V << RTC_CNTL_SLP_VAL_HI_S) -#define RTC_CNTL_SLP_VAL_HI_V 0x0000ffff -#define RTC_CNTL_SLP_VAL_HI_S 0 - -/* RTC_CNTL_RTC_TIME_UPDATE_REG register - * update rtc main timer - */ - -#define RTC_CNTL_RTC_TIME_UPDATE_REG (DR_REG_RTCCNTL_BASE + 0xc) - -/* RTC_CNTL_RTC_TIME_UPDATE : WO; bitpos: [31]; default: 0; - * Set 1: to update register with RTC timer - */ - -#define RTC_CNTL_RTC_TIME_UPDATE (BIT(31)) -#define RTC_CNTL_RTC_TIME_UPDATE_M (RTC_CNTL_RTC_TIME_UPDATE_V << RTC_CNTL_RTC_TIME_UPDATE_S) -#define RTC_CNTL_RTC_TIME_UPDATE_V 0x00000001 -#define RTC_CNTL_RTC_TIME_UPDATE_S 31 - -/* RTC_CNTL_TIMER_SYS_RST : R/W; bitpos: [29]; default: 0; - * enable to record system reset time - */ - -#define RTC_CNTL_TIMER_SYS_RST (BIT(29)) -#define RTC_CNTL_TIMER_SYS_RST_M (RTC_CNTL_TIMER_SYS_RST_V << RTC_CNTL_TIMER_SYS_RST_S) -#define RTC_CNTL_TIMER_SYS_RST_V 0x00000001 -#define RTC_CNTL_TIMER_SYS_RST_S 29 - -/* RTC_CNTL_TIMER_XTL_OFF : R/W; bitpos: [28]; default: 0; - * Enable to record 40M XTAL OFF time - */ - -#define RTC_CNTL_TIMER_XTL_OFF (BIT(28)) -#define RTC_CNTL_TIMER_XTL_OFF_M (RTC_CNTL_TIMER_XTL_OFF_V << RTC_CNTL_TIMER_XTL_OFF_S) -#define RTC_CNTL_TIMER_XTL_OFF_V 0x00000001 -#define RTC_CNTL_TIMER_XTL_OFF_S 28 - -/* RTC_CNTL_TIMER_SYS_STALL : R/W; bitpos: [27]; default: 0; - * Enable to record system stall time - */ - -#define RTC_CNTL_TIMER_SYS_STALL (BIT(27)) -#define RTC_CNTL_TIMER_SYS_STALL_M (RTC_CNTL_TIMER_SYS_STALL_V << RTC_CNTL_TIMER_SYS_STALL_S) -#define RTC_CNTL_TIMER_SYS_STALL_V 0x00000001 -#define RTC_CNTL_TIMER_SYS_STALL_S 27 - -/* RTC_CNTL_RTC_TIME_LOW0_REG register - * read rtc_main timer low bits - */ - -#define RTC_CNTL_RTC_TIME_LOW0_REG (DR_REG_RTCCNTL_BASE + 0x10) - -/* RTC_CNTL_RTC_TIMER_VALUE0_LOW : RO; bitpos: [31:0]; default: 0; - * RTC timer low 32 bits - */ - -#define RTC_CNTL_RTC_TIMER_VALUE0_LOW 0xffffffff -#define RTC_CNTL_RTC_TIMER_VALUE0_LOW_M (RTC_CNTL_RTC_TIMER_VALUE0_LOW_V << RTC_CNTL_RTC_TIMER_VALUE0_LOW_S) -#define RTC_CNTL_RTC_TIMER_VALUE0_LOW_V 0xffffffff -#define RTC_CNTL_RTC_TIMER_VALUE0_LOW_S 0 - -/* RTC_CNTL_RTC_TIME_HIGH0_REG register - * read rtc_main timer high bits - */ - -#define RTC_CNTL_RTC_TIME_HIGH0_REG (DR_REG_RTCCNTL_BASE + 0x14) - -/* RTC_CNTL_RTC_TIMER_VALUE0_HIGH : RO; bitpos: [15:0]; default: 0; - * RTC timer high 16 bits - */ - -#define RTC_CNTL_RTC_TIMER_VALUE0_HIGH 0x0000ffff -#define RTC_CNTL_RTC_TIMER_VALUE0_HIGH_M (RTC_CNTL_RTC_TIMER_VALUE0_HIGH_V << RTC_CNTL_RTC_TIMER_VALUE0_HIGH_S) -#define RTC_CNTL_RTC_TIMER_VALUE0_HIGH_V 0x0000ffff -#define RTC_CNTL_RTC_TIMER_VALUE0_HIGH_S 0 - -/* RTC_CNTL_RTC_STATE0_REG register - * configure chip sleep - */ - -#define RTC_CNTL_RTC_STATE0_REG (DR_REG_RTCCNTL_BASE + 0x18) - -/* RTC_CNTL_SLEEP_EN : R/W; bitpos: [31]; default: 0; - * sleep enable bit - */ - -#define RTC_CNTL_SLEEP_EN (BIT(31)) -#define RTC_CNTL_SLEEP_EN_M (RTC_CNTL_SLEEP_EN_V << RTC_CNTL_SLEEP_EN_S) -#define RTC_CNTL_SLEEP_EN_V 0x00000001 -#define RTC_CNTL_SLEEP_EN_S 31 - -/* RTC_CNTL_SLP_REJECT : R/W; bitpos: [30]; default: 0; - * leep reject bit - */ - -#define RTC_CNTL_SLP_REJECT (BIT(30)) -#define RTC_CNTL_SLP_REJECT_M (RTC_CNTL_SLP_REJECT_V << RTC_CNTL_SLP_REJECT_S) -#define RTC_CNTL_SLP_REJECT_V 0x00000001 -#define RTC_CNTL_SLP_REJECT_S 30 - -/* RTC_CNTL_SLP_WAKEUP : R/W; bitpos: [29]; default: 0; - * leep wakeup bit - */ - -#define RTC_CNTL_SLP_WAKEUP (BIT(29)) -#define RTC_CNTL_SLP_WAKEUP_M (RTC_CNTL_SLP_WAKEUP_V << RTC_CNTL_SLP_WAKEUP_S) -#define RTC_CNTL_SLP_WAKEUP_V 0x00000001 -#define RTC_CNTL_SLP_WAKEUP_S 29 - -/* RTC_CNTL_SDIO_ACTIVE_IND : RO; bitpos: [28]; default: 0; - * SDIO active indication - */ - -#define RTC_CNTL_SDIO_ACTIVE_IND (BIT(28)) -#define RTC_CNTL_SDIO_ACTIVE_IND_M (RTC_CNTL_SDIO_ACTIVE_IND_V << RTC_CNTL_SDIO_ACTIVE_IND_S) -#define RTC_CNTL_SDIO_ACTIVE_IND_V 0x00000001 -#define RTC_CNTL_SDIO_ACTIVE_IND_S 28 - -/* RTC_CNTL_APB2RTC_BRIDGE_SEL : R/W; bitpos: [22]; default: 0; - * 1: APB to RTC using bridge, 0: APB to RTC using sync - */ - -#define RTC_CNTL_APB2RTC_BRIDGE_SEL (BIT(22)) -#define RTC_CNTL_APB2RTC_BRIDGE_SEL_M (RTC_CNTL_APB2RTC_BRIDGE_SEL_V << RTC_CNTL_APB2RTC_BRIDGE_SEL_S) -#define RTC_CNTL_APB2RTC_BRIDGE_SEL_V 0x00000001 -#define RTC_CNTL_APB2RTC_BRIDGE_SEL_S 22 - -/* RTC_CNTL_RTC_SLP_REJECT_CAUSE_CLR : WO; bitpos: [1]; default: 0; - * clear rtc sleep reject cause - */ - -#define RTC_CNTL_RTC_SLP_REJECT_CAUSE_CLR (BIT(1)) -#define RTC_CNTL_RTC_SLP_REJECT_CAUSE_CLR_M (RTC_CNTL_RTC_SLP_REJECT_CAUSE_CLR_V << RTC_CNTL_RTC_SLP_REJECT_CAUSE_CLR_S) -#define RTC_CNTL_RTC_SLP_REJECT_CAUSE_CLR_V 0x00000001 -#define RTC_CNTL_RTC_SLP_REJECT_CAUSE_CLR_S 1 - -/* RTC_CNTL_RTC_SW_CPU_INT : WO; bitpos: [0]; default: 0; - * rtc software interrupt to main cpu - */ - -#define RTC_CNTL_RTC_SW_CPU_INT (BIT(0)) -#define RTC_CNTL_RTC_SW_CPU_INT_M (RTC_CNTL_RTC_SW_CPU_INT_V << RTC_CNTL_RTC_SW_CPU_INT_S) -#define RTC_CNTL_RTC_SW_CPU_INT_V 0x00000001 -#define RTC_CNTL_RTC_SW_CPU_INT_S 0 - -/* RTC_CNTL_RTC_TIMER1_REG register - * rtc state wait time - */ - -#define RTC_CNTL_RTC_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x1c) - -/* RTC_CNTL_PLL_BUF_WAIT : R/W; bitpos: [31:24]; default: 40; - * PLL wait cycles in slow_clk_rtc - */ - -#define RTC_CNTL_PLL_BUF_WAIT 0x000000ff -#define RTC_CNTL_PLL_BUF_WAIT_M (RTC_CNTL_PLL_BUF_WAIT_V << RTC_CNTL_PLL_BUF_WAIT_S) -#define RTC_CNTL_PLL_BUF_WAIT_V 0x000000ff -#define RTC_CNTL_PLL_BUF_WAIT_S 24 -#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 20 - -/* RTC_CNTL_XTL_BUF_WAIT : R/W; bitpos: [23:14]; default: 80; - * XTAL wait cycles in slow_clk_rtc - */ - -#define RTC_CNTL_XTL_BUF_WAIT 0x000003ff -#define RTC_CNTL_XTL_BUF_WAIT_M (RTC_CNTL_XTL_BUF_WAIT_V << RTC_CNTL_XTL_BUF_WAIT_S) -#define RTC_CNTL_XTL_BUF_WAIT_V 0x000003ff -#define RTC_CNTL_XTL_BUF_WAIT_S 14 -#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 100 - -/* RTC_CNTL_CK8M_WAIT : R/W; bitpos: [13:6]; default: 16; - * CK8M wait cycles in slow_clk_rtc - */ - -#define RTC_CNTL_CK8M_WAIT 0x000000ff -#define RTC_CNTL_CK8M_WAIT_M (RTC_CNTL_CK8M_WAIT_V << RTC_CNTL_CK8M_WAIT_S) -#define RTC_CNTL_CK8M_WAIT_V 0x000000ff -#define RTC_CNTL_CK8M_WAIT_S 6 -#define RTC_CNTL_CK8M_WAIT_DEFAULT 20 -#define RTC_CK8M_ENABLE_WAIT_DEFAULT 5 - -/* RTC_CNTL_CPU_STALL_WAIT : R/W; bitpos: [5:1]; default: 1; - * CPU stall wait cycles in fast_clk_rtc - */ - -#define RTC_CNTL_CPU_STALL_WAIT 0x0000001f -#define RTC_CNTL_CPU_STALL_WAIT_M (RTC_CNTL_CPU_STALL_WAIT_V << RTC_CNTL_CPU_STALL_WAIT_S) -#define RTC_CNTL_CPU_STALL_WAIT_V 0x0000001f -#define RTC_CNTL_CPU_STALL_WAIT_S 1 - -/* RTC_CNTL_CPU_STALL_EN : R/W; bitpos: [0]; default: 1; - * CPU stall enable bit - */ - -#define RTC_CNTL_CPU_STALL_EN (BIT(0)) -#define RTC_CNTL_CPU_STALL_EN_M (RTC_CNTL_CPU_STALL_EN_V << RTC_CNTL_CPU_STALL_EN_S) -#define RTC_CNTL_CPU_STALL_EN_V 0x00000001 -#define RTC_CNTL_CPU_STALL_EN_S 0 - -/* RTC_CNTL_RTC_TIMER2_REG register - * rtc monitor state delay time - */ - -#define RTC_CNTL_RTC_TIMER2_REG (DR_REG_RTCCNTL_BASE + 0x20) - -/* RTC_CNTL_MIN_TIME_CK8M_OFF : R/W; bitpos: [31:24]; default: 1; - * minimal cycles in slow_clk_rtc for CK8M in power down state - */ - -#define RTC_CNTL_MIN_TIME_CK8M_OFF 0x000000ff -#define RTC_CNTL_MIN_TIME_CK8M_OFF_M (RTC_CNTL_MIN_TIME_CK8M_OFF_V << RTC_CNTL_MIN_TIME_CK8M_OFF_S) -#define RTC_CNTL_MIN_TIME_CK8M_OFF_V 0x000000ff -#define RTC_CNTL_MIN_TIME_CK8M_OFF_S 24 - -/* RTC_CNTL_ULPCP_TOUCH_START_WAIT : R/W; bitpos: [23:15]; default: 16; - * wait cycles in slow_clk_rtc before ULP-coprocessor / touch controller - * start to work - */ - -#define RTC_CNTL_ULPCP_TOUCH_START_WAIT 0x000001ff -#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_M (RTC_CNTL_ULPCP_TOUCH_START_WAIT_V << RTC_CNTL_ULPCP_TOUCH_START_WAIT_S) -#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_V 0x000001ff -#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_S 15 - -/* RTC_CNTL_RTC_TIMER3_REG register - * No public - */ - -#define RTC_CNTL_RTC_TIMER3_REG (DR_REG_RTCCNTL_BASE + 0x24) - -/* RTC_CNTL_BT_POWERUP_TIMER : R/W; bitpos: [31:25]; default: 10; - * No public - */ - -#define RTC_CNTL_BT_POWERUP_TIMER 0x0000007f -#define RTC_CNTL_BT_POWERUP_TIMER_M (RTC_CNTL_BT_POWERUP_TIMER_V << RTC_CNTL_BT_POWERUP_TIMER_S) -#define RTC_CNTL_BT_POWERUP_TIMER_V 0x0000007f -#define RTC_CNTL_BT_POWERUP_TIMER_S 25 - -/* RTC_CNTL_BT_WAIT_TIMER : R/W; bitpos: [24:16]; default: 22; - * No public - */ - -#define RTC_CNTL_BT_WAIT_TIMER 0x000001ff -#define RTC_CNTL_BT_WAIT_TIMER_M (RTC_CNTL_BT_WAIT_TIMER_V << RTC_CNTL_BT_WAIT_TIMER_S) -#define RTC_CNTL_BT_WAIT_TIMER_V 0x000001ff -#define RTC_CNTL_BT_WAIT_TIMER_S 16 - -/* RTC_CNTL_WIFI_POWERUP_TIMER : R/W; bitpos: [15:9]; default: 5; - * No public - */ - -#define RTC_CNTL_WIFI_POWERUP_TIMER 0x0000007f -#define RTC_CNTL_WIFI_POWERUP_TIMER_M (RTC_CNTL_WIFI_POWERUP_TIMER_V << RTC_CNTL_WIFI_POWERUP_TIMER_S) -#define RTC_CNTL_WIFI_POWERUP_TIMER_V 0x0000007f -#define RTC_CNTL_WIFI_POWERUP_TIMER_S 9 - -/* RTC_CNTL_WIFI_WAIT_TIMER : R/W; bitpos: [8:0]; default: 8; - * No public - */ - -#define RTC_CNTL_WIFI_WAIT_TIMER 0x000001ff -#define RTC_CNTL_WIFI_WAIT_TIMER_M (RTC_CNTL_WIFI_WAIT_TIMER_V << RTC_CNTL_WIFI_WAIT_TIMER_S) -#define RTC_CNTL_WIFI_WAIT_TIMER_V 0x000001ff -#define RTC_CNTL_WIFI_WAIT_TIMER_S 0 - -/* RTC_CNTL_RTC_TIMER4_REG register - * No public - */ - -#define RTC_CNTL_RTC_TIMER4_REG (DR_REG_RTCCNTL_BASE + 0x28) - -/* RTC_CNTL_DG_WRAP_POWERUP_TIMER : R/W; bitpos: [31:25]; default: 8; - * No public - */ - -#define RTC_CNTL_DG_WRAP_POWERUP_TIMER 0x0000007f -#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_M (RTC_CNTL_DG_WRAP_POWERUP_TIMER_V << RTC_CNTL_DG_WRAP_POWERUP_TIMER_S) -#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_V 0x0000007f -#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_S 25 - -/* RTC_CNTL_DG_WRAP_WAIT_TIMER : R/W; bitpos: [24:16]; default: 32; - * No public - */ - -#define RTC_CNTL_DG_WRAP_WAIT_TIMER 0x000001ff -#define RTC_CNTL_DG_WRAP_WAIT_TIMER_M (RTC_CNTL_DG_WRAP_WAIT_TIMER_V << RTC_CNTL_DG_WRAP_WAIT_TIMER_S) -#define RTC_CNTL_DG_WRAP_WAIT_TIMER_V 0x000001ff -#define RTC_CNTL_DG_WRAP_WAIT_TIMER_S 16 - -/* RTC_CNTL_RTC_POWERUP_TIMER : R/W; bitpos: [15:9]; default: 5; - * No public - */ - -#define RTC_CNTL_RTC_POWERUP_TIMER 0x0000007f -#define RTC_CNTL_RTC_POWERUP_TIMER_M (RTC_CNTL_RTC_POWERUP_TIMER_V << RTC_CNTL_RTC_POWERUP_TIMER_S) -#define RTC_CNTL_RTC_POWERUP_TIMER_V 0x0000007f -#define RTC_CNTL_RTC_POWERUP_TIMER_S 9 - -/* RTC_CNTL_RTC_WAIT_TIMER : R/W; bitpos: [8:0]; default: 8; - * No public - */ - -#define RTC_CNTL_RTC_WAIT_TIMER 0x000001ff -#define RTC_CNTL_RTC_WAIT_TIMER_M (RTC_CNTL_RTC_WAIT_TIMER_V << RTC_CNTL_RTC_WAIT_TIMER_S) -#define RTC_CNTL_RTC_WAIT_TIMER_V 0x000001ff -#define RTC_CNTL_RTC_WAIT_TIMER_S 0 - -/* RTC_CNTL_RTC_TIMER5_REG register - * configure min sleep time - */ - -#define RTC_CNTL_RTC_TIMER5_REG (DR_REG_RTCCNTL_BASE + 0x2c) - -/* RTC_CNTL_MIN_SLP_VAL : R/W; bitpos: [15:8]; default: 128; - * minimal sleep cycles in slow_clk_rtc - */ - -#define RTC_CNTL_MIN_SLP_VAL 0x000000ff -#define RTC_CNTL_MIN_SLP_VAL_M (RTC_CNTL_MIN_SLP_VAL_V << RTC_CNTL_MIN_SLP_VAL_S) -#define RTC_CNTL_MIN_SLP_VAL_V 0x000000ff -#define RTC_CNTL_MIN_SLP_VAL_S 8 -#define RTC_CNTL_MIN_SLP_VAL_MIN 2 - -/* RTC_CNTL_RTC_TIMER6_REG register - * No public - */ - -#define RTC_CNTL_RTC_TIMER6_REG (DR_REG_RTCCNTL_BASE + 0x30) - -/* RTC_CNTL_DG_PERI_POWERUP_TIMER : R/W; bitpos: [31:25]; default: 8; - * No public - */ - -#define RTC_CNTL_DG_PERI_POWERUP_TIMER 0x0000007f -#define RTC_CNTL_DG_PERI_POWERUP_TIMER_M (RTC_CNTL_DG_PERI_POWERUP_TIMER_V << RTC_CNTL_DG_PERI_POWERUP_TIMER_S) -#define RTC_CNTL_DG_PERI_POWERUP_TIMER_V 0x0000007f -#define RTC_CNTL_DG_PERI_POWERUP_TIMER_S 25 - -/* RTC_CNTL_DG_PERI_WAIT_TIMER : R/W; bitpos: [24:16]; default: 32; - * No public - */ - -#define RTC_CNTL_DG_PERI_WAIT_TIMER 0x000001ff -#define RTC_CNTL_DG_PERI_WAIT_TIMER_M (RTC_CNTL_DG_PERI_WAIT_TIMER_V << RTC_CNTL_DG_PERI_WAIT_TIMER_S) -#define RTC_CNTL_DG_PERI_WAIT_TIMER_V 0x000001ff -#define RTC_CNTL_DG_PERI_WAIT_TIMER_S 16 - -/* RTC_CNTL_CPU_TOP_POWERUP_TIMER : R/W; bitpos: [15:9]; default: 5; - * No public - */ - -#define RTC_CNTL_CPU_TOP_POWERUP_TIMER 0x0000007f -#define RTC_CNTL_CPU_TOP_POWERUP_TIMER_M (RTC_CNTL_CPU_TOP_POWERUP_TIMER_V << RTC_CNTL_CPU_TOP_POWERUP_TIMER_S) -#define RTC_CNTL_CPU_TOP_POWERUP_TIMER_V 0x0000007f -#define RTC_CNTL_CPU_TOP_POWERUP_TIMER_S 9 - -/* RTC_CNTL_CPU_TOP_WAIT_TIMER : R/W; bitpos: [8:0]; default: 8; - * No public - */ - -#define RTC_CNTL_CPU_TOP_WAIT_TIMER 0x000001ff -#define RTC_CNTL_CPU_TOP_WAIT_TIMER_M (RTC_CNTL_CPU_TOP_WAIT_TIMER_V << RTC_CNTL_CPU_TOP_WAIT_TIMER_S) -#define RTC_CNTL_CPU_TOP_WAIT_TIMER_V 0x000001ff -#define RTC_CNTL_CPU_TOP_WAIT_TIMER_S 0 - -/* RTC_CNTL_RTC_ANA_CONF_REG register - * analog configure register - */ - -#define RTC_CNTL_RTC_ANA_CONF_REG (DR_REG_RTCCNTL_BASE + 0x34) - -/* RTC_CNTL_PLL_I2C_PU : R/W; bitpos: [31]; default: 0; - * power on pll i2c - */ - -#define RTC_CNTL_PLL_I2C_PU (BIT(31)) -#define RTC_CNTL_PLL_I2C_PU_M (RTC_CNTL_PLL_I2C_PU_V << RTC_CNTL_PLL_I2C_PU_S) -#define RTC_CNTL_PLL_I2C_PU_V 0x00000001 -#define RTC_CNTL_PLL_I2C_PU_S 31 - -/* RTC_CNTL_CKGEN_I2C_PU : R/W; bitpos: [30]; default: 0; - * 1: CKGEN_I2C power up, otherwise power down - */ - -#define RTC_CNTL_CKGEN_I2C_PU (BIT(30)) -#define RTC_CNTL_CKGEN_I2C_PU_M (RTC_CNTL_CKGEN_I2C_PU_V << RTC_CNTL_CKGEN_I2C_PU_S) -#define RTC_CNTL_CKGEN_I2C_PU_V 0x00000001 -#define RTC_CNTL_CKGEN_I2C_PU_S 30 - -/* RTC_CNTL_RFRX_PBUS_PU : R/W; bitpos: [28]; default: 0; - * 1: RFRX_PBUS power up, otherwise power down - */ - -#define RTC_CNTL_RFRX_PBUS_PU (BIT(28)) -#define RTC_CNTL_RFRX_PBUS_PU_M (RTC_CNTL_RFRX_PBUS_PU_V << RTC_CNTL_RFRX_PBUS_PU_S) -#define RTC_CNTL_RFRX_PBUS_PU_V 0x00000001 -#define RTC_CNTL_RFRX_PBUS_PU_S 28 - -/* RTC_CNTL_TXRF_I2C_PU : R/W; bitpos: [27]; default: 0; - * 1: TXRF_I2C power up, otherwise power down - */ - -#define RTC_CNTL_TXRF_I2C_PU (BIT(27)) -#define RTC_CNTL_TXRF_I2C_PU_M (RTC_CNTL_TXRF_I2C_PU_V << RTC_CNTL_TXRF_I2C_PU_S) -#define RTC_CNTL_TXRF_I2C_PU_V 0x00000001 -#define RTC_CNTL_TXRF_I2C_PU_S 27 - -/* RTC_CNTL_PVTMON_PU : R/W; bitpos: [26]; default: 0; - * 1: PVTMON power up, otherwise power down - */ - -#define RTC_CNTL_PVTMON_PU (BIT(26)) -#define RTC_CNTL_PVTMON_PU_M (RTC_CNTL_PVTMON_PU_V << RTC_CNTL_PVTMON_PU_S) -#define RTC_CNTL_PVTMON_PU_V 0x00000001 -#define RTC_CNTL_PVTMON_PU_S 26 - -/* RTC_CNTL_BBPLL_CAL_SLP_START : R/W; bitpos: [25]; default: 0; - * start BBPLL calibration during sleep - */ - -#define RTC_CNTL_BBPLL_CAL_SLP_START (BIT(25)) -#define RTC_CNTL_BBPLL_CAL_SLP_START_M (RTC_CNTL_BBPLL_CAL_SLP_START_V << RTC_CNTL_BBPLL_CAL_SLP_START_S) -#define RTC_CNTL_BBPLL_CAL_SLP_START_V 0x00000001 -#define RTC_CNTL_BBPLL_CAL_SLP_START_S 25 - -/* RTC_CNTL_ANALOG_TOP_ISO_MONITOR : R/W; bitpos: [24]; default: 0; - * PLLA force power up - */ - -#define RTC_CNTL_ANALOG_TOP_ISO_MONITOR (BIT(24)) -#define RTC_CNTL_ANALOG_TOP_ISO_MONITOR_M (RTC_CNTL_ANALOG_TOP_ISO_MONITOR_V << RTC_CNTL_ANALOG_TOP_ISO_MONITOR_S) -#define RTC_CNTL_ANALOG_TOP_ISO_MONITOR_V 0x00000001 -#define RTC_CNTL_ANALOG_TOP_ISO_MONITOR_S 24 - -/* RTC_CNTL_ANALOG_TOP_ISO_SLEEP : R/W; bitpos: [23]; default: 0; - * PLLA force power down - */ - -#define RTC_CNTL_ANALOG_TOP_ISO_SLEEP (BIT(23)) -#define RTC_CNTL_ANALOG_TOP_ISO_SLEEP_M (RTC_CNTL_ANALOG_TOP_ISO_SLEEP_V << RTC_CNTL_ANALOG_TOP_ISO_SLEEP_S) -#define RTC_CNTL_ANALOG_TOP_ISO_SLEEP_V 0x00000001 -#define RTC_CNTL_ANALOG_TOP_ISO_SLEEP_S 23 - -/* RTC_CNTL_SAR_I2C_PU : R/W; bitpos: [22]; default: 1; - * PLLA force power up - */ - -#define RTC_CNTL_SAR_I2C_PU (BIT(22)) -#define RTC_CNTL_SAR_I2C_PU_M (RTC_CNTL_SAR_I2C_PU_V << RTC_CNTL_SAR_I2C_PU_S) -#define RTC_CNTL_SAR_I2C_PU_V 0x00000001 -#define RTC_CNTL_SAR_I2C_PU_S 22 - -/* RTC_CNTL_GLITCH_RST_EN : R/W; bitpos: [20]; default: 0; - * enable clk glitch - */ - -#define RTC_CNTL_GLITCH_RST_EN (BIT(20)) -#define RTC_CNTL_GLITCH_RST_EN_M (RTC_CNTL_GLITCH_RST_EN_V << RTC_CNTL_GLITCH_RST_EN_S) -#define RTC_CNTL_GLITCH_RST_EN_V 0x00000001 -#define RTC_CNTL_GLITCH_RST_EN_S 20 - -/* RTC_CNTL_I2C_RESET_POR_FORCE_PU : R/W; bitpos: [19]; default: 0; - * force on I2C_RESET_POR - */ - -#define RTC_CNTL_I2C_RESET_POR_FORCE_PU (BIT(19)) -#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_M (RTC_CNTL_I2C_RESET_POR_FORCE_PU_V << RTC_CNTL_I2C_RESET_POR_FORCE_PU_S) -#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_V 0x00000001 -#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_S 19 - -/* RTC_CNTL_I2C_RESET_POR_FORCE_PD : R/W; bitpos: [18]; default: 1; - * force down I2C_RESET_POR - */ - -#define RTC_CNTL_I2C_RESET_POR_FORCE_PD (BIT(18)) -#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_M (RTC_CNTL_I2C_RESET_POR_FORCE_PD_V << RTC_CNTL_I2C_RESET_POR_FORCE_PD_S) -#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_V 0x00000001 -#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_S 18 - -/* RTC_CNTL_RTC_RESET_STATE_REG register - * get reset state - */ - -#define RTC_CNTL_RTC_RESET_STATE_REG (DR_REG_RTCCNTL_BASE + 0x38) - -/* RTC_CNTL_RTC_PRO_DRESET_MASK : R/W; bitpos: [25]; default: 0; - * bypass cpu0 dreset - */ - -#define RTC_CNTL_RTC_PRO_DRESET_MASK (BIT(25)) -#define RTC_CNTL_RTC_PRO_DRESET_MASK_M (RTC_CNTL_RTC_PRO_DRESET_MASK_V << RTC_CNTL_RTC_PRO_DRESET_MASK_S) -#define RTC_CNTL_RTC_PRO_DRESET_MASK_V 0x00000001 -#define RTC_CNTL_RTC_PRO_DRESET_MASK_S 25 - -/* RTC_CNTL_RTC_APP_DRESET_MASK : R/W; bitpos: [24]; default: 0; - * bypass cpu1 dreset - */ - -#define RTC_CNTL_RTC_APP_DRESET_MASK (BIT(24)) -#define RTC_CNTL_RTC_APP_DRESET_MASK_M (RTC_CNTL_RTC_APP_DRESET_MASK_V << RTC_CNTL_RTC_APP_DRESET_MASK_S) -#define RTC_CNTL_RTC_APP_DRESET_MASK_V 0x00000001 -#define RTC_CNTL_RTC_APP_DRESET_MASK_S 24 - -/* RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR : WO; bitpos: [23]; default: 0; - * clear jtag reset flag - */ - -#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR (BIT(23)) -#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR_M (RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR_V << RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR_S) -#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR_V 0x00000001 -#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR_S 23 - -/* RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR : WO; bitpos: [22]; default: 0; - * clear jtag reset flag - */ - -#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR (BIT(22)) -#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR_M (RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR_V << RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR_S) -#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR_V 0x00000001 -#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR_S 22 - -/* RTC_CNTL_RESET_FLAG_JTAG_APPCPU : RO; bitpos: [21]; default: 0; - * jtag reset flag - */ - -#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU (BIT(21)) -#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_M (RTC_CNTL_RESET_FLAG_JTAG_APPCPU_V << RTC_CNTL_RESET_FLAG_JTAG_APPCPU_S) -#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_V 0x00000001 -#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_S 21 - -/* RTC_CNTL_RESET_FLAG_JTAG_PROCPU : RO; bitpos: [20]; default: 0; - * jtag reset flag - */ - -#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU (BIT(20)) -#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_M (RTC_CNTL_RESET_FLAG_JTAG_PROCPU_V << RTC_CNTL_RESET_FLAG_JTAG_PROCPU_S) -#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_V 0x00000001 -#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_S 20 - -/* RTC_CNTL_PROCPU_OCD_HALT_ON_RESET : R/W; bitpos: [19]; default: 0; - * PROCPU OcdHaltOnReset - */ - -#define RTC_CNTL_PROCPU_OCD_HALT_ON_RESET (BIT(19)) -#define RTC_CNTL_PROCPU_OCD_HALT_ON_RESET_M (RTC_CNTL_PROCPU_OCD_HALT_ON_RESET_V << RTC_CNTL_PROCPU_OCD_HALT_ON_RESET_S) -#define RTC_CNTL_PROCPU_OCD_HALT_ON_RESET_V 0x00000001 -#define RTC_CNTL_PROCPU_OCD_HALT_ON_RESET_S 19 - -/* RTC_CNTL_APPCPU_OCD_HALT_ON_RESET : R/W; bitpos: [18]; default: 0; - * APPCPU OcdHaltOnReset - */ - -#define RTC_CNTL_APPCPU_OCD_HALT_ON_RESET (BIT(18)) -#define RTC_CNTL_APPCPU_OCD_HALT_ON_RESET_M (RTC_CNTL_APPCPU_OCD_HALT_ON_RESET_V << RTC_CNTL_APPCPU_OCD_HALT_ON_RESET_S) -#define RTC_CNTL_APPCPU_OCD_HALT_ON_RESET_V 0x00000001 -#define RTC_CNTL_APPCPU_OCD_HALT_ON_RESET_S 18 - -/* RTC_CNTL_RESET_FLAG_APPCPU_CLR : WO; bitpos: [17]; default: 0; - * clear APP CPU reset flag - */ - -#define RTC_CNTL_RESET_FLAG_APPCPU_CLR (BIT(17)) -#define RTC_CNTL_RESET_FLAG_APPCPU_CLR_M (RTC_CNTL_RESET_FLAG_APPCPU_CLR_V << RTC_CNTL_RESET_FLAG_APPCPU_CLR_S) -#define RTC_CNTL_RESET_FLAG_APPCPU_CLR_V 0x00000001 -#define RTC_CNTL_RESET_FLAG_APPCPU_CLR_S 17 - -/* RTC_CNTL_RESET_FLAG_PROCPU_CLR : WO; bitpos: [16]; default: 0; - * clear PRO CPU reset_flag - */ - -#define RTC_CNTL_RESET_FLAG_PROCPU_CLR (BIT(16)) -#define RTC_CNTL_RESET_FLAG_PROCPU_CLR_M (RTC_CNTL_RESET_FLAG_PROCPU_CLR_V << RTC_CNTL_RESET_FLAG_PROCPU_CLR_S) -#define RTC_CNTL_RESET_FLAG_PROCPU_CLR_V 0x00000001 -#define RTC_CNTL_RESET_FLAG_PROCPU_CLR_S 16 - -/* RTC_CNTL_RESET_FLAG_APPCPU : RO; bitpos: [15]; default: 0; - * APP CPU reset flag - */ - -#define RTC_CNTL_RESET_FLAG_APPCPU (BIT(15)) -#define RTC_CNTL_RESET_FLAG_APPCPU_M (RTC_CNTL_RESET_FLAG_APPCPU_V << RTC_CNTL_RESET_FLAG_APPCPU_S) -#define RTC_CNTL_RESET_FLAG_APPCPU_V 0x00000001 -#define RTC_CNTL_RESET_FLAG_APPCPU_S 15 - -/* RTC_CNTL_RESET_FLAG_PROCPU : RO; bitpos: [14]; default: 0; - * PRO CPU reset_flag - */ - -#define RTC_CNTL_RESET_FLAG_PROCPU (BIT(14)) -#define RTC_CNTL_RESET_FLAG_PROCPU_M (RTC_CNTL_RESET_FLAG_PROCPU_V << RTC_CNTL_RESET_FLAG_PROCPU_S) -#define RTC_CNTL_RESET_FLAG_PROCPU_V 0x00000001 -#define RTC_CNTL_RESET_FLAG_PROCPU_S 14 - -/* RTC_CNTL_PROCPU_STAT_VECTOR_SEL : R/W; bitpos: [13]; default: 1; - * PRO CPU state vector sel - */ - -#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL (BIT(13)) -#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_M (RTC_CNTL_PROCPU_STAT_VECTOR_SEL_V << RTC_CNTL_PROCPU_STAT_VECTOR_SEL_S) -#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_V 0x00000001 -#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_S 13 - -/* RTC_CNTL_APPCPU_STAT_VECTOR_SEL : R/W; bitpos: [12]; default: 1; - * APP CPU state vector sel - */ - -#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL (BIT(12)) -#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_M (RTC_CNTL_APPCPU_STAT_VECTOR_SEL_V << RTC_CNTL_APPCPU_STAT_VECTOR_SEL_S) -#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_V 0x00000001 -#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_S 12 - -/* RTC_CNTL_RESET_CAUSE_APPCPU : RO; bitpos: [11:6]; default: 0; - * reset cause of APP CPU - */ - -#define RTC_CNTL_RESET_CAUSE_APPCPU 0x0000003f -#define RTC_CNTL_RESET_CAUSE_APPCPU_M (RTC_CNTL_RESET_CAUSE_APPCPU_V << RTC_CNTL_RESET_CAUSE_APPCPU_S) -#define RTC_CNTL_RESET_CAUSE_APPCPU_V 0x0000003f -#define RTC_CNTL_RESET_CAUSE_APPCPU_S 6 - -/* RTC_CNTL_RESET_CAUSE_PROCPU : RO; bitpos: [5:0]; default: 0; - * reset cause of PRO CPU - */ - -#define RTC_CNTL_RESET_CAUSE_PROCPU 0x0000003f -#define RTC_CNTL_RESET_CAUSE_PROCPU_M (RTC_CNTL_RESET_CAUSE_PROCPU_V << RTC_CNTL_RESET_CAUSE_PROCPU_S) -#define RTC_CNTL_RESET_CAUSE_PROCPU_V 0x0000003f -#define RTC_CNTL_RESET_CAUSE_PROCPU_S 0 - -/* RTC_CNTL_RTC_WAKEUP_STATE_REG register - * configure wakeup state - */ - -#define RTC_CNTL_RTC_WAKEUP_STATE_REG (DR_REG_RTCCNTL_BASE + 0x3c) - -/* RTC_CNTL_RTC_WAKEUP_ENA : R/W; bitpos: [31:15]; default: 12; - * wakeup enable bitmap - */ - -#define RTC_CNTL_RTC_WAKEUP_ENA 0x0001ffff -#define RTC_CNTL_RTC_WAKEUP_ENA_M (RTC_CNTL_RTC_WAKEUP_ENA_V << RTC_CNTL_RTC_WAKEUP_ENA_S) -#define RTC_CNTL_RTC_WAKEUP_ENA_V 0x0001ffff -#define RTC_CNTL_RTC_WAKEUP_ENA_S 15 - -/* RTC_CNTL_INT_ENA_RTC_REG register - * configure rtc interrupt register - */ - -#define RTC_CNTL_INT_ENA_RTC_REG (DR_REG_RTCCNTL_BASE + 0x40) - -/* RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA : R/W; bitpos: [20]; - * default: 0; - * touch approach mode loop interrupt - */ - -#define RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA (BIT(20)) -#define RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_M (RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_V << RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_S) -#define RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_V 0x00000001 -#define RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_S 20 - -/* RTC_CNTL_RTC_GLITCH_DET_INT_ENA : R/W; bitpos: [19]; default: 0; - * enable gitch det interrupt - */ - -#define RTC_CNTL_RTC_GLITCH_DET_INT_ENA (BIT(19)) -#define RTC_CNTL_RTC_GLITCH_DET_INT_ENA_M (RTC_CNTL_RTC_GLITCH_DET_INT_ENA_V << RTC_CNTL_RTC_GLITCH_DET_INT_ENA_S) -#define RTC_CNTL_RTC_GLITCH_DET_INT_ENA_V 0x00000001 -#define RTC_CNTL_RTC_GLITCH_DET_INT_ENA_S 19 - -/* RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_ENA : R/W; bitpos: [18]; default: 0; - * enable touch timeout interrupt - */ - -#define RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_ENA (BIT(18)) -#define RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_ENA_M (RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_ENA_V << RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_ENA_S) -#define RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_ENA_V 0x00000001 -#define RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_ENA_S 18 - -/* RTC_CNTL_RTC_COCPU_TRAP_INT_ENA : R/W; bitpos: [17]; default: 0; - * enable cocpu trap interrupt - */ - -#define RTC_CNTL_RTC_COCPU_TRAP_INT_ENA (BIT(17)) -#define RTC_CNTL_RTC_COCPU_TRAP_INT_ENA_M (RTC_CNTL_RTC_COCPU_TRAP_INT_ENA_V << RTC_CNTL_RTC_COCPU_TRAP_INT_ENA_S) -#define RTC_CNTL_RTC_COCPU_TRAP_INT_ENA_V 0x00000001 -#define RTC_CNTL_RTC_COCPU_TRAP_INT_ENA_S 17 - -/* RTC_CNTL_RTC_XTAL32K_DEAD_INT_ENA : R/W; bitpos: [16]; default: 0; - * enable xtal32k_dead interrupt - */ - -#define RTC_CNTL_RTC_XTAL32K_DEAD_INT_ENA (BIT(16)) -#define RTC_CNTL_RTC_XTAL32K_DEAD_INT_ENA_M (RTC_CNTL_RTC_XTAL32K_DEAD_INT_ENA_V << RTC_CNTL_RTC_XTAL32K_DEAD_INT_ENA_S) -#define RTC_CNTL_RTC_XTAL32K_DEAD_INT_ENA_V 0x00000001 -#define RTC_CNTL_RTC_XTAL32K_DEAD_INT_ENA_S 16 - -/* RTC_CNTL_RTC_SWD_INT_ENA : R/W; bitpos: [15]; default: 0; - * enable super watch dog interrupt - */ - -#define RTC_CNTL_RTC_SWD_INT_ENA (BIT(15)) -#define RTC_CNTL_RTC_SWD_INT_ENA_M (RTC_CNTL_RTC_SWD_INT_ENA_V << RTC_CNTL_RTC_SWD_INT_ENA_S) -#define RTC_CNTL_RTC_SWD_INT_ENA_V 0x00000001 -#define RTC_CNTL_RTC_SWD_INT_ENA_S 15 - -/* RTC_CNTL_RTC_SARADC2_INT_ENA : R/W; bitpos: [14]; default: 0; - * enable saradc2 interrupt - */ - -#define RTC_CNTL_RTC_SARADC2_INT_ENA (BIT(14)) -#define RTC_CNTL_RTC_SARADC2_INT_ENA_M (RTC_CNTL_RTC_SARADC2_INT_ENA_V << RTC_CNTL_RTC_SARADC2_INT_ENA_S) -#define RTC_CNTL_RTC_SARADC2_INT_ENA_V 0x00000001 -#define RTC_CNTL_RTC_SARADC2_INT_ENA_S 14 - -/* RTC_CNTL_RTC_COCPU_INT_ENA : R/W; bitpos: [13]; default: 0; - * enable riscV cocpu interrupt - */ - -#define RTC_CNTL_RTC_COCPU_INT_ENA (BIT(13)) -#define RTC_CNTL_RTC_COCPU_INT_ENA_M (RTC_CNTL_RTC_COCPU_INT_ENA_V << RTC_CNTL_RTC_COCPU_INT_ENA_S) -#define RTC_CNTL_RTC_COCPU_INT_ENA_V 0x00000001 -#define RTC_CNTL_RTC_COCPU_INT_ENA_S 13 - -/* RTC_CNTL_RTC_TSENS_INT_ENA : R/W; bitpos: [12]; default: 0; - * enable tsens interrupt - */ - -#define RTC_CNTL_RTC_TSENS_INT_ENA (BIT(12)) -#define RTC_CNTL_RTC_TSENS_INT_ENA_M (RTC_CNTL_RTC_TSENS_INT_ENA_V << RTC_CNTL_RTC_TSENS_INT_ENA_S) -#define RTC_CNTL_RTC_TSENS_INT_ENA_V 0x00000001 -#define RTC_CNTL_RTC_TSENS_INT_ENA_S 12 - -/* RTC_CNTL_RTC_SARADC1_INT_ENA : R/W; bitpos: [11]; default: 0; - * enable saradc1 interrupt - */ - -#define RTC_CNTL_RTC_SARADC1_INT_ENA (BIT(11)) -#define RTC_CNTL_RTC_SARADC1_INT_ENA_M (RTC_CNTL_RTC_SARADC1_INT_ENA_V << RTC_CNTL_RTC_SARADC1_INT_ENA_S) -#define RTC_CNTL_RTC_SARADC1_INT_ENA_V 0x00000001 -#define RTC_CNTL_RTC_SARADC1_INT_ENA_S 11 - -/* RTC_CNTL_RTC_MAIN_TIMER_INT_ENA : R/W; bitpos: [10]; default: 0; - * enable RTC main timer interrupt - */ - -#define RTC_CNTL_RTC_MAIN_TIMER_INT_ENA (BIT(10)) -#define RTC_CNTL_RTC_MAIN_TIMER_INT_ENA_M (RTC_CNTL_RTC_MAIN_TIMER_INT_ENA_V << RTC_CNTL_RTC_MAIN_TIMER_INT_ENA_S) -#define RTC_CNTL_RTC_MAIN_TIMER_INT_ENA_V 0x00000001 -#define RTC_CNTL_RTC_MAIN_TIMER_INT_ENA_S 10 - -/* RTC_CNTL_RTC_BROWN_OUT_INT_ENA : R/W; bitpos: [9]; default: 0; - * enable brown out interrupt - */ - -#define RTC_CNTL_RTC_BROWN_OUT_INT_ENA (BIT(9)) -#define RTC_CNTL_RTC_BROWN_OUT_INT_ENA_M (RTC_CNTL_RTC_BROWN_OUT_INT_ENA_V << RTC_CNTL_RTC_BROWN_OUT_INT_ENA_S) -#define RTC_CNTL_RTC_BROWN_OUT_INT_ENA_V 0x00000001 -#define RTC_CNTL_RTC_BROWN_OUT_INT_ENA_S 9 - -/* RTC_CNTL_RTC_TOUCH_INACTIVE_INT_ENA : R/W; bitpos: [8]; default: 0; - * enable touch inactive interrupt - */ - -#define RTC_CNTL_RTC_TOUCH_INACTIVE_INT_ENA (BIT(8)) -#define RTC_CNTL_RTC_TOUCH_INACTIVE_INT_ENA_M (RTC_CNTL_RTC_TOUCH_INACTIVE_INT_ENA_V << RTC_CNTL_RTC_TOUCH_INACTIVE_INT_ENA_S) -#define RTC_CNTL_RTC_TOUCH_INACTIVE_INT_ENA_V 0x00000001 -#define RTC_CNTL_RTC_TOUCH_INACTIVE_INT_ENA_S 8 - -/* RTC_CNTL_RTC_TOUCH_ACTIVE_INT_ENA : R/W; bitpos: [7]; default: 0; - * enable touch active interrupt - */ - -#define RTC_CNTL_RTC_TOUCH_ACTIVE_INT_ENA (BIT(7)) -#define RTC_CNTL_RTC_TOUCH_ACTIVE_INT_ENA_M (RTC_CNTL_RTC_TOUCH_ACTIVE_INT_ENA_V << RTC_CNTL_RTC_TOUCH_ACTIVE_INT_ENA_S) -#define RTC_CNTL_RTC_TOUCH_ACTIVE_INT_ENA_V 0x00000001 -#define RTC_CNTL_RTC_TOUCH_ACTIVE_INT_ENA_S 7 - -/* RTC_CNTL_RTC_TOUCH_DONE_INT_ENA : R/W; bitpos: [6]; default: 0; - * enable touch done interrupt - */ - -#define RTC_CNTL_RTC_TOUCH_DONE_INT_ENA (BIT(6)) -#define RTC_CNTL_RTC_TOUCH_DONE_INT_ENA_M (RTC_CNTL_RTC_TOUCH_DONE_INT_ENA_V << RTC_CNTL_RTC_TOUCH_DONE_INT_ENA_S) -#define RTC_CNTL_RTC_TOUCH_DONE_INT_ENA_V 0x00000001 -#define RTC_CNTL_RTC_TOUCH_DONE_INT_ENA_S 6 - -/* RTC_CNTL_RTC_ULP_CP_INT_ENA : R/W; bitpos: [5]; default: 0; - * enable ULP-coprocessor interrupt - */ - -#define RTC_CNTL_RTC_ULP_CP_INT_ENA (BIT(5)) -#define RTC_CNTL_RTC_ULP_CP_INT_ENA_M (RTC_CNTL_RTC_ULP_CP_INT_ENA_V << RTC_CNTL_RTC_ULP_CP_INT_ENA_S) -#define RTC_CNTL_RTC_ULP_CP_INT_ENA_V 0x00000001 -#define RTC_CNTL_RTC_ULP_CP_INT_ENA_S 5 - -/* RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_ENA : R/W; bitpos: [4]; default: 0; - * enable touch scan done interrupt - */ - -#define RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_ENA (BIT(4)) -#define RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_ENA_M (RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_ENA_V << RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_ENA_S) -#define RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_ENA_V 0x00000001 -#define RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_ENA_S 4 - -/* RTC_CNTL_RTC_WDT_INT_ENA : R/W; bitpos: [3]; default: 0; - * enable RTC WDT interrupt - */ - -#define RTC_CNTL_RTC_WDT_INT_ENA (BIT(3)) -#define RTC_CNTL_RTC_WDT_INT_ENA_M (RTC_CNTL_RTC_WDT_INT_ENA_V << RTC_CNTL_RTC_WDT_INT_ENA_S) -#define RTC_CNTL_RTC_WDT_INT_ENA_V 0x00000001 -#define RTC_CNTL_RTC_WDT_INT_ENA_S 3 - -/* RTC_CNTL_SDIO_IDLE_INT_ENA : R/W; bitpos: [2]; default: 0; - * enable SDIO idle interrupt - */ - -#define RTC_CNTL_SDIO_IDLE_INT_ENA (BIT(2)) -#define RTC_CNTL_SDIO_IDLE_INT_ENA_M (RTC_CNTL_SDIO_IDLE_INT_ENA_V << RTC_CNTL_SDIO_IDLE_INT_ENA_S) -#define RTC_CNTL_SDIO_IDLE_INT_ENA_V 0x00000001 -#define RTC_CNTL_SDIO_IDLE_INT_ENA_S 2 - -/* RTC_CNTL_SLP_REJECT_INT_ENA : R/W; bitpos: [1]; default: 0; - * enable sleep reject interrupt - */ - -#define RTC_CNTL_SLP_REJECT_INT_ENA (BIT(1)) -#define RTC_CNTL_SLP_REJECT_INT_ENA_M (RTC_CNTL_SLP_REJECT_INT_ENA_V << RTC_CNTL_SLP_REJECT_INT_ENA_S) -#define RTC_CNTL_SLP_REJECT_INT_ENA_V 0x00000001 -#define RTC_CNTL_SLP_REJECT_INT_ENA_S 1 - -/* RTC_CNTL_SLP_WAKEUP_INT_ENA : R/W; bitpos: [0]; default: 0; - * enable sleep wakeup interrupt - */ - -#define RTC_CNTL_SLP_WAKEUP_INT_ENA (BIT(0)) -#define RTC_CNTL_SLP_WAKEUP_INT_ENA_M (RTC_CNTL_SLP_WAKEUP_INT_ENA_V << RTC_CNTL_SLP_WAKEUP_INT_ENA_S) -#define RTC_CNTL_SLP_WAKEUP_INT_ENA_V 0x00000001 -#define RTC_CNTL_SLP_WAKEUP_INT_ENA_S 0 - -/* RTC_CNTL_INT_RAW_RTC_REG register - * rtc interrupt register - */ - -#define RTC_CNTL_INT_RAW_RTC_REG (DR_REG_RTCCNTL_BASE + 0x44) - -/* RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW : R/W; bitpos: [20]; - * default: 0; - * touch approach mode loop interrupt raw - */ - -#define RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW (BIT(20)) -#define RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW_M (RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW_V << RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW_S) -#define RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW_V 0x00000001 -#define RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_RAW_S 20 - -/* RTC_CNTL_RTC_GLITCH_DET_INT_RAW : RO; bitpos: [19]; default: 0; - * glitch_det_interrupt_raw - */ - -#define RTC_CNTL_RTC_GLITCH_DET_INT_RAW (BIT(19)) -#define RTC_CNTL_RTC_GLITCH_DET_INT_RAW_M (RTC_CNTL_RTC_GLITCH_DET_INT_RAW_V << RTC_CNTL_RTC_GLITCH_DET_INT_RAW_S) -#define RTC_CNTL_RTC_GLITCH_DET_INT_RAW_V 0x00000001 -#define RTC_CNTL_RTC_GLITCH_DET_INT_RAW_S 19 - -/* RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_RAW : RO; bitpos: [18]; default: 0; - * touch timeout interrupt raw - */ - -#define RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_RAW (BIT(18)) -#define RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_RAW_M (RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_RAW_V << RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_RAW_S) -#define RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_RAW_V 0x00000001 -#define RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_RAW_S 18 - -/* RTC_CNTL_RTC_COCPU_TRAP_INT_RAW : RO; bitpos: [17]; default: 0; - * cocpu trap interrupt raw - */ - -#define RTC_CNTL_RTC_COCPU_TRAP_INT_RAW (BIT(17)) -#define RTC_CNTL_RTC_COCPU_TRAP_INT_RAW_M (RTC_CNTL_RTC_COCPU_TRAP_INT_RAW_V << RTC_CNTL_RTC_COCPU_TRAP_INT_RAW_S) -#define RTC_CNTL_RTC_COCPU_TRAP_INT_RAW_V 0x00000001 -#define RTC_CNTL_RTC_COCPU_TRAP_INT_RAW_S 17 - -/* RTC_CNTL_RTC_XTAL32K_DEAD_INT_RAW : RO; bitpos: [16]; default: 0; - * xtal32k dead detection interrupt raw - */ - -#define RTC_CNTL_RTC_XTAL32K_DEAD_INT_RAW (BIT(16)) -#define RTC_CNTL_RTC_XTAL32K_DEAD_INT_RAW_M (RTC_CNTL_RTC_XTAL32K_DEAD_INT_RAW_V << RTC_CNTL_RTC_XTAL32K_DEAD_INT_RAW_S) -#define RTC_CNTL_RTC_XTAL32K_DEAD_INT_RAW_V 0x00000001 -#define RTC_CNTL_RTC_XTAL32K_DEAD_INT_RAW_S 16 - -/* RTC_CNTL_RTC_SWD_INT_RAW : RO; bitpos: [15]; default: 0; - * super watch dog interrupt raw - */ - -#define RTC_CNTL_RTC_SWD_INT_RAW (BIT(15)) -#define RTC_CNTL_RTC_SWD_INT_RAW_M (RTC_CNTL_RTC_SWD_INT_RAW_V << RTC_CNTL_RTC_SWD_INT_RAW_S) -#define RTC_CNTL_RTC_SWD_INT_RAW_V 0x00000001 -#define RTC_CNTL_RTC_SWD_INT_RAW_S 15 - -/* RTC_CNTL_RTC_SARADC2_INT_RAW : RO; bitpos: [14]; default: 0; - * saradc2 interrupt raw - */ - -#define RTC_CNTL_RTC_SARADC2_INT_RAW (BIT(14)) -#define RTC_CNTL_RTC_SARADC2_INT_RAW_M (RTC_CNTL_RTC_SARADC2_INT_RAW_V << RTC_CNTL_RTC_SARADC2_INT_RAW_S) -#define RTC_CNTL_RTC_SARADC2_INT_RAW_V 0x00000001 -#define RTC_CNTL_RTC_SARADC2_INT_RAW_S 14 - -/* RTC_CNTL_RTC_COCPU_INT_RAW : RO; bitpos: [13]; default: 0; - * riscV cocpu interrupt raw - */ - -#define RTC_CNTL_RTC_COCPU_INT_RAW (BIT(13)) -#define RTC_CNTL_RTC_COCPU_INT_RAW_M (RTC_CNTL_RTC_COCPU_INT_RAW_V << RTC_CNTL_RTC_COCPU_INT_RAW_S) -#define RTC_CNTL_RTC_COCPU_INT_RAW_V 0x00000001 -#define RTC_CNTL_RTC_COCPU_INT_RAW_S 13 - -/* RTC_CNTL_RTC_TSENS_INT_RAW : RO; bitpos: [12]; default: 0; - * tsens interrupt raw - */ - -#define RTC_CNTL_RTC_TSENS_INT_RAW (BIT(12)) -#define RTC_CNTL_RTC_TSENS_INT_RAW_M (RTC_CNTL_RTC_TSENS_INT_RAW_V << RTC_CNTL_RTC_TSENS_INT_RAW_S) -#define RTC_CNTL_RTC_TSENS_INT_RAW_V 0x00000001 -#define RTC_CNTL_RTC_TSENS_INT_RAW_S 12 - -/* RTC_CNTL_RTC_SARADC1_INT_RAW : RO; bitpos: [11]; default: 0; - * saradc1 interrupt raw - */ - -#define RTC_CNTL_RTC_SARADC1_INT_RAW (BIT(11)) -#define RTC_CNTL_RTC_SARADC1_INT_RAW_M (RTC_CNTL_RTC_SARADC1_INT_RAW_V << RTC_CNTL_RTC_SARADC1_INT_RAW_S) -#define RTC_CNTL_RTC_SARADC1_INT_RAW_V 0x00000001 -#define RTC_CNTL_RTC_SARADC1_INT_RAW_S 11 - -/* RTC_CNTL_RTC_MAIN_TIMER_INT_RAW : RO; bitpos: [10]; default: 0; - * RTC main timer interrupt raw - */ - -#define RTC_CNTL_RTC_MAIN_TIMER_INT_RAW (BIT(10)) -#define RTC_CNTL_RTC_MAIN_TIMER_INT_RAW_M (RTC_CNTL_RTC_MAIN_TIMER_INT_RAW_V << RTC_CNTL_RTC_MAIN_TIMER_INT_RAW_S) -#define RTC_CNTL_RTC_MAIN_TIMER_INT_RAW_V 0x00000001 -#define RTC_CNTL_RTC_MAIN_TIMER_INT_RAW_S 10 - -/* RTC_CNTL_RTC_BROWN_OUT_INT_RAW : RO; bitpos: [9]; default: 0; - * brown out interrupt raw - */ - -#define RTC_CNTL_RTC_BROWN_OUT_INT_RAW (BIT(9)) -#define RTC_CNTL_RTC_BROWN_OUT_INT_RAW_M (RTC_CNTL_RTC_BROWN_OUT_INT_RAW_V << RTC_CNTL_RTC_BROWN_OUT_INT_RAW_S) -#define RTC_CNTL_RTC_BROWN_OUT_INT_RAW_V 0x00000001 -#define RTC_CNTL_RTC_BROWN_OUT_INT_RAW_S 9 - -/* RTC_CNTL_RTC_TOUCH_INACTIVE_INT_RAW : RO; bitpos: [8]; default: 0; - * touch inactive interrupt raw - */ - -#define RTC_CNTL_RTC_TOUCH_INACTIVE_INT_RAW (BIT(8)) -#define RTC_CNTL_RTC_TOUCH_INACTIVE_INT_RAW_M (RTC_CNTL_RTC_TOUCH_INACTIVE_INT_RAW_V << RTC_CNTL_RTC_TOUCH_INACTIVE_INT_RAW_S) -#define RTC_CNTL_RTC_TOUCH_INACTIVE_INT_RAW_V 0x00000001 -#define RTC_CNTL_RTC_TOUCH_INACTIVE_INT_RAW_S 8 - -/* RTC_CNTL_RTC_TOUCH_ACTIVE_INT_RAW : RO; bitpos: [7]; default: 0; - * touch active interrupt raw - */ - -#define RTC_CNTL_RTC_TOUCH_ACTIVE_INT_RAW (BIT(7)) -#define RTC_CNTL_RTC_TOUCH_ACTIVE_INT_RAW_M (RTC_CNTL_RTC_TOUCH_ACTIVE_INT_RAW_V << RTC_CNTL_RTC_TOUCH_ACTIVE_INT_RAW_S) -#define RTC_CNTL_RTC_TOUCH_ACTIVE_INT_RAW_V 0x00000001 -#define RTC_CNTL_RTC_TOUCH_ACTIVE_INT_RAW_S 7 - -/* RTC_CNTL_RTC_TOUCH_DONE_INT_RAW : RO; bitpos: [6]; default: 0; - * touch interrupt raw - */ - -#define RTC_CNTL_RTC_TOUCH_DONE_INT_RAW (BIT(6)) -#define RTC_CNTL_RTC_TOUCH_DONE_INT_RAW_M (RTC_CNTL_RTC_TOUCH_DONE_INT_RAW_V << RTC_CNTL_RTC_TOUCH_DONE_INT_RAW_S) -#define RTC_CNTL_RTC_TOUCH_DONE_INT_RAW_V 0x00000001 -#define RTC_CNTL_RTC_TOUCH_DONE_INT_RAW_S 6 - -/* RTC_CNTL_RTC_ULP_CP_INT_RAW : RO; bitpos: [5]; default: 0; - * ULP-coprocessor interrupt raw - */ - -#define RTC_CNTL_RTC_ULP_CP_INT_RAW (BIT(5)) -#define RTC_CNTL_RTC_ULP_CP_INT_RAW_M (RTC_CNTL_RTC_ULP_CP_INT_RAW_V << RTC_CNTL_RTC_ULP_CP_INT_RAW_S) -#define RTC_CNTL_RTC_ULP_CP_INT_RAW_V 0x00000001 -#define RTC_CNTL_RTC_ULP_CP_INT_RAW_S 5 - -/* RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_RAW : RO; bitpos: [4]; default: 0; - * enable touch scan done interrupt raw - */ - -#define RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_RAW (BIT(4)) -#define RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_RAW_M (RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_RAW_V << RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_RAW_S) -#define RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_RAW_V 0x00000001 -#define RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_RAW_S 4 - -/* RTC_CNTL_RTC_WDT_INT_RAW : RO; bitpos: [3]; default: 0; - * RTC WDT interrupt raw - */ - -#define RTC_CNTL_RTC_WDT_INT_RAW (BIT(3)) -#define RTC_CNTL_RTC_WDT_INT_RAW_M (RTC_CNTL_RTC_WDT_INT_RAW_V << RTC_CNTL_RTC_WDT_INT_RAW_S) -#define RTC_CNTL_RTC_WDT_INT_RAW_V 0x00000001 -#define RTC_CNTL_RTC_WDT_INT_RAW_S 3 - -/* RTC_CNTL_SDIO_IDLE_INT_RAW : RO; bitpos: [2]; default: 0; - * SDIO idle interrupt raw - */ - -#define RTC_CNTL_SDIO_IDLE_INT_RAW (BIT(2)) -#define RTC_CNTL_SDIO_IDLE_INT_RAW_M (RTC_CNTL_SDIO_IDLE_INT_RAW_V << RTC_CNTL_SDIO_IDLE_INT_RAW_S) -#define RTC_CNTL_SDIO_IDLE_INT_RAW_V 0x00000001 -#define RTC_CNTL_SDIO_IDLE_INT_RAW_S 2 - -/* RTC_CNTL_SLP_REJECT_INT_RAW : RO; bitpos: [1]; default: 0; - * sleep reject interrupt raw - */ - -#define RTC_CNTL_SLP_REJECT_INT_RAW (BIT(1)) -#define RTC_CNTL_SLP_REJECT_INT_RAW_M (RTC_CNTL_SLP_REJECT_INT_RAW_V << RTC_CNTL_SLP_REJECT_INT_RAW_S) -#define RTC_CNTL_SLP_REJECT_INT_RAW_V 0x00000001 -#define RTC_CNTL_SLP_REJECT_INT_RAW_S 1 - -/* RTC_CNTL_SLP_WAKEUP_INT_RAW : RO; bitpos: [0]; default: 0; - * sleep wakeup interrupt raw - */ - -#define RTC_CNTL_SLP_WAKEUP_INT_RAW (BIT(0)) -#define RTC_CNTL_SLP_WAKEUP_INT_RAW_M (RTC_CNTL_SLP_WAKEUP_INT_RAW_V << RTC_CNTL_SLP_WAKEUP_INT_RAW_S) -#define RTC_CNTL_SLP_WAKEUP_INT_RAW_V 0x00000001 -#define RTC_CNTL_SLP_WAKEUP_INT_RAW_S 0 - -/* RTC_CNTL_INT_ST_RTC_REG register - * rtc interrupt register - */ - -#define RTC_CNTL_INT_ST_RTC_REG (DR_REG_RTCCNTL_BASE + 0x48) - -/* RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST : RO; bitpos: [20]; default: - * 0; - * touch approach mode loop interrupt state - */ - -#define RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST (BIT(20)) -#define RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST_M (RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST_V << RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST_S) -#define RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST_V 0x00000001 -#define RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ST_S 20 - -/* RTC_CNTL_RTC_GLITCH_DET_INT_ST : RO; bitpos: [19]; default: 0; - * glitch_det_interrupt state - */ - -#define RTC_CNTL_RTC_GLITCH_DET_INT_ST (BIT(19)) -#define RTC_CNTL_RTC_GLITCH_DET_INT_ST_M (RTC_CNTL_RTC_GLITCH_DET_INT_ST_V << RTC_CNTL_RTC_GLITCH_DET_INT_ST_S) -#define RTC_CNTL_RTC_GLITCH_DET_INT_ST_V 0x00000001 -#define RTC_CNTL_RTC_GLITCH_DET_INT_ST_S 19 - -/* RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_ST : RO; bitpos: [18]; default: 0; - * Touch timeout interrupt state - */ - -#define RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_ST (BIT(18)) -#define RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_ST_M (RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_ST_V << RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_ST_S) -#define RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_ST_V 0x00000001 -#define RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_ST_S 18 - -/* RTC_CNTL_RTC_COCPU_TRAP_INT_ST : RO; bitpos: [17]; default: 0; - * cocpu trap interrupt state - */ - -#define RTC_CNTL_RTC_COCPU_TRAP_INT_ST (BIT(17)) -#define RTC_CNTL_RTC_COCPU_TRAP_INT_ST_M (RTC_CNTL_RTC_COCPU_TRAP_INT_ST_V << RTC_CNTL_RTC_COCPU_TRAP_INT_ST_S) -#define RTC_CNTL_RTC_COCPU_TRAP_INT_ST_V 0x00000001 -#define RTC_CNTL_RTC_COCPU_TRAP_INT_ST_S 17 - -/* RTC_CNTL_RTC_XTAL32K_DEAD_INT_ST : RO; bitpos: [16]; default: 0; - * xtal32k dead detection interrupt state - */ - -#define RTC_CNTL_RTC_XTAL32K_DEAD_INT_ST (BIT(16)) -#define RTC_CNTL_RTC_XTAL32K_DEAD_INT_ST_M (RTC_CNTL_RTC_XTAL32K_DEAD_INT_ST_V << RTC_CNTL_RTC_XTAL32K_DEAD_INT_ST_S) -#define RTC_CNTL_RTC_XTAL32K_DEAD_INT_ST_V 0x00000001 -#define RTC_CNTL_RTC_XTAL32K_DEAD_INT_ST_S 16 - -/* RTC_CNTL_RTC_SWD_INT_ST : RO; bitpos: [15]; default: 0; - * super watch dog interrupt state - */ - -#define RTC_CNTL_RTC_SWD_INT_ST (BIT(15)) -#define RTC_CNTL_RTC_SWD_INT_ST_M (RTC_CNTL_RTC_SWD_INT_ST_V << RTC_CNTL_RTC_SWD_INT_ST_S) -#define RTC_CNTL_RTC_SWD_INT_ST_V 0x00000001 -#define RTC_CNTL_RTC_SWD_INT_ST_S 15 - -/* RTC_CNTL_RTC_SARADC2_INT_ST : RO; bitpos: [14]; default: 0; - * saradc2 interrupt state - */ - -#define RTC_CNTL_RTC_SARADC2_INT_ST (BIT(14)) -#define RTC_CNTL_RTC_SARADC2_INT_ST_M (RTC_CNTL_RTC_SARADC2_INT_ST_V << RTC_CNTL_RTC_SARADC2_INT_ST_S) -#define RTC_CNTL_RTC_SARADC2_INT_ST_V 0x00000001 -#define RTC_CNTL_RTC_SARADC2_INT_ST_S 14 - -/* RTC_CNTL_RTC_COCPU_INT_ST : RO; bitpos: [13]; default: 0; - * riscV cocpu interrupt state - */ - -#define RTC_CNTL_RTC_COCPU_INT_ST (BIT(13)) -#define RTC_CNTL_RTC_COCPU_INT_ST_M (RTC_CNTL_RTC_COCPU_INT_ST_V << RTC_CNTL_RTC_COCPU_INT_ST_S) -#define RTC_CNTL_RTC_COCPU_INT_ST_V 0x00000001 -#define RTC_CNTL_RTC_COCPU_INT_ST_S 13 - -/* RTC_CNTL_RTC_TSENS_INT_ST : RO; bitpos: [12]; default: 0; - * tsens interrupt state - */ - -#define RTC_CNTL_RTC_TSENS_INT_ST (BIT(12)) -#define RTC_CNTL_RTC_TSENS_INT_ST_M (RTC_CNTL_RTC_TSENS_INT_ST_V << RTC_CNTL_RTC_TSENS_INT_ST_S) -#define RTC_CNTL_RTC_TSENS_INT_ST_V 0x00000001 -#define RTC_CNTL_RTC_TSENS_INT_ST_S 12 - -/* RTC_CNTL_RTC_SARADC1_INT_ST : RO; bitpos: [11]; default: 0; - * saradc1 interrupt state - */ - -#define RTC_CNTL_RTC_SARADC1_INT_ST (BIT(11)) -#define RTC_CNTL_RTC_SARADC1_INT_ST_M (RTC_CNTL_RTC_SARADC1_INT_ST_V << RTC_CNTL_RTC_SARADC1_INT_ST_S) -#define RTC_CNTL_RTC_SARADC1_INT_ST_V 0x00000001 -#define RTC_CNTL_RTC_SARADC1_INT_ST_S 11 - -/* RTC_CNTL_RTC_MAIN_TIMER_INT_ST : RO; bitpos: [10]; default: 0; - * RTC main timer interrupt state - */ - -#define RTC_CNTL_RTC_MAIN_TIMER_INT_ST (BIT(10)) -#define RTC_CNTL_RTC_MAIN_TIMER_INT_ST_M (RTC_CNTL_RTC_MAIN_TIMER_INT_ST_V << RTC_CNTL_RTC_MAIN_TIMER_INT_ST_S) -#define RTC_CNTL_RTC_MAIN_TIMER_INT_ST_V 0x00000001 -#define RTC_CNTL_RTC_MAIN_TIMER_INT_ST_S 10 - -/* RTC_CNTL_RTC_BROWN_OUT_INT_ST : RO; bitpos: [9]; default: 0; - * brown out interrupt state - */ - -#define RTC_CNTL_RTC_BROWN_OUT_INT_ST (BIT(9)) -#define RTC_CNTL_RTC_BROWN_OUT_INT_ST_M (RTC_CNTL_RTC_BROWN_OUT_INT_ST_V << RTC_CNTL_RTC_BROWN_OUT_INT_ST_S) -#define RTC_CNTL_RTC_BROWN_OUT_INT_ST_V 0x00000001 -#define RTC_CNTL_RTC_BROWN_OUT_INT_ST_S 9 - -/* RTC_CNTL_RTC_TOUCH_INACTIVE_INT_ST : RO; bitpos: [8]; default: 0; - * touch inactive interrupt state - */ - -#define RTC_CNTL_RTC_TOUCH_INACTIVE_INT_ST (BIT(8)) -#define RTC_CNTL_RTC_TOUCH_INACTIVE_INT_ST_M (RTC_CNTL_RTC_TOUCH_INACTIVE_INT_ST_V << RTC_CNTL_RTC_TOUCH_INACTIVE_INT_ST_S) -#define RTC_CNTL_RTC_TOUCH_INACTIVE_INT_ST_V 0x00000001 -#define RTC_CNTL_RTC_TOUCH_INACTIVE_INT_ST_S 8 - -/* RTC_CNTL_RTC_TOUCH_ACTIVE_INT_ST : RO; bitpos: [7]; default: 0; - * touch active interrupt state - */ - -#define RTC_CNTL_RTC_TOUCH_ACTIVE_INT_ST (BIT(7)) -#define RTC_CNTL_RTC_TOUCH_ACTIVE_INT_ST_M (RTC_CNTL_RTC_TOUCH_ACTIVE_INT_ST_V << RTC_CNTL_RTC_TOUCH_ACTIVE_INT_ST_S) -#define RTC_CNTL_RTC_TOUCH_ACTIVE_INT_ST_V 0x00000001 -#define RTC_CNTL_RTC_TOUCH_ACTIVE_INT_ST_S 7 - -/* RTC_CNTL_RTC_TOUCH_DONE_INT_ST : RO; bitpos: [6]; default: 0; - * touch done interrupt state - */ - -#define RTC_CNTL_RTC_TOUCH_DONE_INT_ST (BIT(6)) -#define RTC_CNTL_RTC_TOUCH_DONE_INT_ST_M (RTC_CNTL_RTC_TOUCH_DONE_INT_ST_V << RTC_CNTL_RTC_TOUCH_DONE_INT_ST_S) -#define RTC_CNTL_RTC_TOUCH_DONE_INT_ST_V 0x00000001 -#define RTC_CNTL_RTC_TOUCH_DONE_INT_ST_S 6 - -/* RTC_CNTL_RTC_ULP_CP_INT_ST : RO; bitpos: [5]; default: 0; - * ULP-coprocessor interrupt state - */ - -#define RTC_CNTL_RTC_ULP_CP_INT_ST (BIT(5)) -#define RTC_CNTL_RTC_ULP_CP_INT_ST_M (RTC_CNTL_RTC_ULP_CP_INT_ST_V << RTC_CNTL_RTC_ULP_CP_INT_ST_S) -#define RTC_CNTL_RTC_ULP_CP_INT_ST_V 0x00000001 -#define RTC_CNTL_RTC_ULP_CP_INT_ST_S 5 - -/* RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_ST : RO; bitpos: [4]; default: 0; - * enable touch scan done interrupt raw - */ - -#define RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_ST (BIT(4)) -#define RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_ST_M (RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_ST_V << RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_ST_S) -#define RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_ST_V 0x00000001 -#define RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_ST_S 4 - -/* RTC_CNTL_RTC_WDT_INT_ST : RO; bitpos: [3]; default: 0; - * RTC WDT interrupt state - */ - -#define RTC_CNTL_RTC_WDT_INT_ST (BIT(3)) -#define RTC_CNTL_RTC_WDT_INT_ST_M (RTC_CNTL_RTC_WDT_INT_ST_V << RTC_CNTL_RTC_WDT_INT_ST_S) -#define RTC_CNTL_RTC_WDT_INT_ST_V 0x00000001 -#define RTC_CNTL_RTC_WDT_INT_ST_S 3 - -/* RTC_CNTL_SDIO_IDLE_INT_ST : RO; bitpos: [2]; default: 0; - * SDIO idle interrupt state - */ - -#define RTC_CNTL_SDIO_IDLE_INT_ST (BIT(2)) -#define RTC_CNTL_SDIO_IDLE_INT_ST_M (RTC_CNTL_SDIO_IDLE_INT_ST_V << RTC_CNTL_SDIO_IDLE_INT_ST_S) -#define RTC_CNTL_SDIO_IDLE_INT_ST_V 0x00000001 -#define RTC_CNTL_SDIO_IDLE_INT_ST_S 2 - -/* RTC_CNTL_SLP_REJECT_INT_ST : RO; bitpos: [1]; default: 0; - * sleep reject interrupt state - */ - -#define RTC_CNTL_SLP_REJECT_INT_ST (BIT(1)) -#define RTC_CNTL_SLP_REJECT_INT_ST_M (RTC_CNTL_SLP_REJECT_INT_ST_V << RTC_CNTL_SLP_REJECT_INT_ST_S) -#define RTC_CNTL_SLP_REJECT_INT_ST_V 0x00000001 -#define RTC_CNTL_SLP_REJECT_INT_ST_S 1 - -/* RTC_CNTL_SLP_WAKEUP_INT_ST : RO; bitpos: [0]; default: 0; - * sleep wakeup interrupt state - */ - -#define RTC_CNTL_SLP_WAKEUP_INT_ST (BIT(0)) -#define RTC_CNTL_SLP_WAKEUP_INT_ST_M (RTC_CNTL_SLP_WAKEUP_INT_ST_V << RTC_CNTL_SLP_WAKEUP_INT_ST_S) -#define RTC_CNTL_SLP_WAKEUP_INT_ST_V 0x00000001 -#define RTC_CNTL_SLP_WAKEUP_INT_ST_S 0 - -/* RTC_CNTL_INT_CLR_RTC_REG register - * rtc interrupt register - */ - -#define RTC_CNTL_INT_CLR_RTC_REG (DR_REG_RTCCNTL_BASE + 0x4c) - -/* RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR : WO; bitpos: [20]; - * default: 0; - * cleartouch approach mode loop interrupt state - */ - -#define RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR (BIT(20)) -#define RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR_M (RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR_V << RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR_S) -#define RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR_V 0x00000001 -#define RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_CLR_S 20 - -/* RTC_CNTL_RTC_GLITCH_DET_INT_CLR : WO; bitpos: [19]; default: 0; - * Clear glitch det interrupt state - */ - -#define RTC_CNTL_RTC_GLITCH_DET_INT_CLR (BIT(19)) -#define RTC_CNTL_RTC_GLITCH_DET_INT_CLR_M (RTC_CNTL_RTC_GLITCH_DET_INT_CLR_V << RTC_CNTL_RTC_GLITCH_DET_INT_CLR_S) -#define RTC_CNTL_RTC_GLITCH_DET_INT_CLR_V 0x00000001 -#define RTC_CNTL_RTC_GLITCH_DET_INT_CLR_S 19 - -/* RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_CLR : WO; bitpos: [18]; default: 0; - * Clear touch timeout interrupt state - */ - -#define RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_CLR (BIT(18)) -#define RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_CLR_M (RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_CLR_V << RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_CLR_S) -#define RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_CLR_V 0x00000001 -#define RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_CLR_S 18 - -/* RTC_CNTL_RTC_COCPU_TRAP_INT_CLR : WO; bitpos: [17]; default: 0; - * Clear cocpu trap interrupt state - */ - -#define RTC_CNTL_RTC_COCPU_TRAP_INT_CLR (BIT(17)) -#define RTC_CNTL_RTC_COCPU_TRAP_INT_CLR_M (RTC_CNTL_RTC_COCPU_TRAP_INT_CLR_V << RTC_CNTL_RTC_COCPU_TRAP_INT_CLR_S) -#define RTC_CNTL_RTC_COCPU_TRAP_INT_CLR_V 0x00000001 -#define RTC_CNTL_RTC_COCPU_TRAP_INT_CLR_S 17 - -/* RTC_CNTL_RTC_XTAL32K_DEAD_INT_CLR : WO; bitpos: [16]; default: 0; - * Clear RTC WDT interrupt state - */ - -#define RTC_CNTL_RTC_XTAL32K_DEAD_INT_CLR (BIT(16)) -#define RTC_CNTL_RTC_XTAL32K_DEAD_INT_CLR_M (RTC_CNTL_RTC_XTAL32K_DEAD_INT_CLR_V << RTC_CNTL_RTC_XTAL32K_DEAD_INT_CLR_S) -#define RTC_CNTL_RTC_XTAL32K_DEAD_INT_CLR_V 0x00000001 -#define RTC_CNTL_RTC_XTAL32K_DEAD_INT_CLR_S 16 - -/* RTC_CNTL_RTC_SWD_INT_CLR : WO; bitpos: [15]; default: 0; - * Clear super watch dog interrupt state - */ - -#define RTC_CNTL_RTC_SWD_INT_CLR (BIT(15)) -#define RTC_CNTL_RTC_SWD_INT_CLR_M (RTC_CNTL_RTC_SWD_INT_CLR_V << RTC_CNTL_RTC_SWD_INT_CLR_S) -#define RTC_CNTL_RTC_SWD_INT_CLR_V 0x00000001 -#define RTC_CNTL_RTC_SWD_INT_CLR_S 15 - -/* RTC_CNTL_RTC_SARADC2_INT_CLR : WO; bitpos: [14]; default: 0; - * Clear saradc2 interrupt state - */ - -#define RTC_CNTL_RTC_SARADC2_INT_CLR (BIT(14)) -#define RTC_CNTL_RTC_SARADC2_INT_CLR_M (RTC_CNTL_RTC_SARADC2_INT_CLR_V << RTC_CNTL_RTC_SARADC2_INT_CLR_S) -#define RTC_CNTL_RTC_SARADC2_INT_CLR_V 0x00000001 -#define RTC_CNTL_RTC_SARADC2_INT_CLR_S 14 - -/* RTC_CNTL_RTC_COCPU_INT_CLR : WO; bitpos: [13]; default: 0; - * Clear riscV cocpu interrupt state - */ - -#define RTC_CNTL_RTC_COCPU_INT_CLR (BIT(13)) -#define RTC_CNTL_RTC_COCPU_INT_CLR_M (RTC_CNTL_RTC_COCPU_INT_CLR_V << RTC_CNTL_RTC_COCPU_INT_CLR_S) -#define RTC_CNTL_RTC_COCPU_INT_CLR_V 0x00000001 -#define RTC_CNTL_RTC_COCPU_INT_CLR_S 13 - -/* RTC_CNTL_RTC_TSENS_INT_CLR : WO; bitpos: [12]; default: 0; - * Clear tsens interrupt state - */ - -#define RTC_CNTL_RTC_TSENS_INT_CLR (BIT(12)) -#define RTC_CNTL_RTC_TSENS_INT_CLR_M (RTC_CNTL_RTC_TSENS_INT_CLR_V << RTC_CNTL_RTC_TSENS_INT_CLR_S) -#define RTC_CNTL_RTC_TSENS_INT_CLR_V 0x00000001 -#define RTC_CNTL_RTC_TSENS_INT_CLR_S 12 - -/* RTC_CNTL_RTC_SARADC1_INT_CLR : WO; bitpos: [11]; default: 0; - * Clear saradc1 interrupt state - */ - -#define RTC_CNTL_RTC_SARADC1_INT_CLR (BIT(11)) -#define RTC_CNTL_RTC_SARADC1_INT_CLR_M (RTC_CNTL_RTC_SARADC1_INT_CLR_V << RTC_CNTL_RTC_SARADC1_INT_CLR_S) -#define RTC_CNTL_RTC_SARADC1_INT_CLR_V 0x00000001 -#define RTC_CNTL_RTC_SARADC1_INT_CLR_S 11 - -/* RTC_CNTL_RTC_MAIN_TIMER_INT_CLR : WO; bitpos: [10]; default: 0; - * Clear RTC main timer interrupt state - */ - -#define RTC_CNTL_RTC_MAIN_TIMER_INT_CLR (BIT(10)) -#define RTC_CNTL_RTC_MAIN_TIMER_INT_CLR_M (RTC_CNTL_RTC_MAIN_TIMER_INT_CLR_V << RTC_CNTL_RTC_MAIN_TIMER_INT_CLR_S) -#define RTC_CNTL_RTC_MAIN_TIMER_INT_CLR_V 0x00000001 -#define RTC_CNTL_RTC_MAIN_TIMER_INT_CLR_S 10 - -/* RTC_CNTL_RTC_BROWN_OUT_INT_CLR : WO; bitpos: [9]; default: 0; - * Clear brown out interrupt state - */ - -#define RTC_CNTL_RTC_BROWN_OUT_INT_CLR (BIT(9)) -#define RTC_CNTL_RTC_BROWN_OUT_INT_CLR_M (RTC_CNTL_RTC_BROWN_OUT_INT_CLR_V << RTC_CNTL_RTC_BROWN_OUT_INT_CLR_S) -#define RTC_CNTL_RTC_BROWN_OUT_INT_CLR_V 0x00000001 -#define RTC_CNTL_RTC_BROWN_OUT_INT_CLR_S 9 - -/* RTC_CNTL_RTC_TOUCH_INACTIVE_INT_CLR : WO; bitpos: [8]; default: 0; - * Clear touch inactive interrupt state - */ - -#define RTC_CNTL_RTC_TOUCH_INACTIVE_INT_CLR (BIT(8)) -#define RTC_CNTL_RTC_TOUCH_INACTIVE_INT_CLR_M (RTC_CNTL_RTC_TOUCH_INACTIVE_INT_CLR_V << RTC_CNTL_RTC_TOUCH_INACTIVE_INT_CLR_S) -#define RTC_CNTL_RTC_TOUCH_INACTIVE_INT_CLR_V 0x00000001 -#define RTC_CNTL_RTC_TOUCH_INACTIVE_INT_CLR_S 8 - -/* RTC_CNTL_RTC_TOUCH_ACTIVE_INT_CLR : WO; bitpos: [7]; default: 0; - * Clear touch active interrupt state - */ - -#define RTC_CNTL_RTC_TOUCH_ACTIVE_INT_CLR (BIT(7)) -#define RTC_CNTL_RTC_TOUCH_ACTIVE_INT_CLR_M (RTC_CNTL_RTC_TOUCH_ACTIVE_INT_CLR_V << RTC_CNTL_RTC_TOUCH_ACTIVE_INT_CLR_S) -#define RTC_CNTL_RTC_TOUCH_ACTIVE_INT_CLR_V 0x00000001 -#define RTC_CNTL_RTC_TOUCH_ACTIVE_INT_CLR_S 7 - -/* RTC_CNTL_RTC_TOUCH_DONE_INT_CLR : WO; bitpos: [6]; default: 0; - * Clear touch done interrupt state - */ - -#define RTC_CNTL_RTC_TOUCH_DONE_INT_CLR (BIT(6)) -#define RTC_CNTL_RTC_TOUCH_DONE_INT_CLR_M (RTC_CNTL_RTC_TOUCH_DONE_INT_CLR_V << RTC_CNTL_RTC_TOUCH_DONE_INT_CLR_S) -#define RTC_CNTL_RTC_TOUCH_DONE_INT_CLR_V 0x00000001 -#define RTC_CNTL_RTC_TOUCH_DONE_INT_CLR_S 6 - -/* RTC_CNTL_RTC_ULP_CP_INT_CLR : WO; bitpos: [5]; default: 0; - * Clear ULP-coprocessor interrupt state - */ - -#define RTC_CNTL_RTC_ULP_CP_INT_CLR (BIT(5)) -#define RTC_CNTL_RTC_ULP_CP_INT_CLR_M (RTC_CNTL_RTC_ULP_CP_INT_CLR_V << RTC_CNTL_RTC_ULP_CP_INT_CLR_S) -#define RTC_CNTL_RTC_ULP_CP_INT_CLR_V 0x00000001 -#define RTC_CNTL_RTC_ULP_CP_INT_CLR_S 5 - -/* RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_CLR : WO; bitpos: [4]; default: 0; - * clear touch scan done interrupt raw - */ - -#define RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_CLR (BIT(4)) -#define RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_CLR_M (RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_CLR_V << RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_CLR_S) -#define RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_CLR_V 0x00000001 -#define RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_CLR_S 4 - -/* RTC_CNTL_RTC_WDT_INT_CLR : WO; bitpos: [3]; default: 0; - * Clear RTC WDT interrupt state - */ - -#define RTC_CNTL_RTC_WDT_INT_CLR (BIT(3)) -#define RTC_CNTL_RTC_WDT_INT_CLR_M (RTC_CNTL_RTC_WDT_INT_CLR_V << RTC_CNTL_RTC_WDT_INT_CLR_S) -#define RTC_CNTL_RTC_WDT_INT_CLR_V 0x00000001 -#define RTC_CNTL_RTC_WDT_INT_CLR_S 3 - -/* RTC_CNTL_SDIO_IDLE_INT_CLR : WO; bitpos: [2]; default: 0; - * Clear SDIO idle interrupt state - */ - -#define RTC_CNTL_SDIO_IDLE_INT_CLR (BIT(2)) -#define RTC_CNTL_SDIO_IDLE_INT_CLR_M (RTC_CNTL_SDIO_IDLE_INT_CLR_V << RTC_CNTL_SDIO_IDLE_INT_CLR_S) -#define RTC_CNTL_SDIO_IDLE_INT_CLR_V 0x00000001 -#define RTC_CNTL_SDIO_IDLE_INT_CLR_S 2 - -/* RTC_CNTL_SLP_REJECT_INT_CLR : WO; bitpos: [1]; default: 0; - * Clear sleep reject interrupt state - */ - -#define RTC_CNTL_SLP_REJECT_INT_CLR (BIT(1)) -#define RTC_CNTL_SLP_REJECT_INT_CLR_M (RTC_CNTL_SLP_REJECT_INT_CLR_V << RTC_CNTL_SLP_REJECT_INT_CLR_S) -#define RTC_CNTL_SLP_REJECT_INT_CLR_V 0x00000001 -#define RTC_CNTL_SLP_REJECT_INT_CLR_S 1 - -/* RTC_CNTL_SLP_WAKEUP_INT_CLR : WO; bitpos: [0]; default: 0; - * Clear sleep wakeup interrupt state - */ - -#define RTC_CNTL_SLP_WAKEUP_INT_CLR (BIT(0)) -#define RTC_CNTL_SLP_WAKEUP_INT_CLR_M (RTC_CNTL_SLP_WAKEUP_INT_CLR_V << RTC_CNTL_SLP_WAKEUP_INT_CLR_S) -#define RTC_CNTL_SLP_WAKEUP_INT_CLR_V 0x00000001 -#define RTC_CNTL_SLP_WAKEUP_INT_CLR_S 0 - -/* RTC_CNTL_RTC_STORE0_REG register - * Reserved register - */ - -#define RTC_CNTL_RTC_STORE0_REG (DR_REG_RTCCNTL_BASE + 0x50) - -/* RTC_CNTL_RTC_SCRATCH0 : R/W; bitpos: [31:0]; default: 0; - * Reserved register - */ - -#define RTC_CNTL_RTC_SCRATCH0 0xffffffff -#define RTC_CNTL_RTC_SCRATCH0_M (RTC_CNTL_RTC_SCRATCH0_V << RTC_CNTL_RTC_SCRATCH0_S) -#define RTC_CNTL_RTC_SCRATCH0_V 0xffffffff -#define RTC_CNTL_RTC_SCRATCH0_S 0 - -/* RTC_CNTL_RTC_STORE1_REG register - * Reserved register - */ - -#define RTC_CNTL_RTC_STORE1_REG (DR_REG_RTCCNTL_BASE + 0x54) - -#define RTC_SLOW_CLK_CAL_REG RTC_CNTL_RTC_STORE1_REG - -/* RTC_CNTL_RTC_SCRATCH1 : R/W; bitpos: [31:0]; default: 0; - * Reserved register - */ - -#define RTC_CNTL_RTC_SCRATCH1 0xffffffff -#define RTC_CNTL_RTC_SCRATCH1_M (RTC_CNTL_RTC_SCRATCH1_V << RTC_CNTL_RTC_SCRATCH1_S) -#define RTC_CNTL_RTC_SCRATCH1_V 0xffffffff -#define RTC_CNTL_RTC_SCRATCH1_S 0 - -/* RTC_CNTL_RTC_STORE2_REG register - * Reserved register - */ - -#define RTC_CNTL_RTC_STORE2_REG (DR_REG_RTCCNTL_BASE + 0x58) - -/* RTC_CNTL_RTC_SCRATCH2 : R/W; bitpos: [31:0]; default: 0; - * Reserved register - */ - -#define RTC_CNTL_RTC_SCRATCH2 0xffffffff -#define RTC_CNTL_RTC_SCRATCH2_M (RTC_CNTL_RTC_SCRATCH2_V << RTC_CNTL_RTC_SCRATCH2_S) -#define RTC_CNTL_RTC_SCRATCH2_V 0xffffffff -#define RTC_CNTL_RTC_SCRATCH2_S 0 - -/* RTC_CNTL_RTC_STORE3_REG register - * Reserved register - */ - -#define RTC_CNTL_RTC_STORE3_REG (DR_REG_RTCCNTL_BASE + 0x5c) - -/* RTC_CNTL_RTC_SCRATCH3 : R/W; bitpos: [31:0]; default: 0; - * Reserved register - */ - -#define RTC_CNTL_RTC_SCRATCH3 0xffffffff -#define RTC_CNTL_RTC_SCRATCH3_M (RTC_CNTL_RTC_SCRATCH3_V << RTC_CNTL_RTC_SCRATCH3_S) -#define RTC_CNTL_RTC_SCRATCH3_V 0xffffffff -#define RTC_CNTL_RTC_SCRATCH3_S 0 - -/* RTC_CNTL_RTC_EXT_XTL_CONF_REG register - * Reserved register - */ - -#define RTC_CNTL_RTC_EXT_XTL_CONF_REG (DR_REG_RTCCNTL_BASE + 0x60) - -/* RTC_CNTL_XTL_EXT_CTR_EN : R/W; bitpos: [31]; default: 0; - * Reserved register - */ - -#define RTC_CNTL_XTL_EXT_CTR_EN (BIT(31)) -#define RTC_CNTL_XTL_EXT_CTR_EN_M (RTC_CNTL_XTL_EXT_CTR_EN_V << RTC_CNTL_XTL_EXT_CTR_EN_S) -#define RTC_CNTL_XTL_EXT_CTR_EN_V 0x00000001 -#define RTC_CNTL_XTL_EXT_CTR_EN_S 31 - -/* RTC_CNTL_XTL_EXT_CTR_LV : R/W; bitpos: [30]; default: 0; - * 0: power down XTAL at high level, 1: power down XTAL at low level - */ - -#define RTC_CNTL_XTL_EXT_CTR_LV (BIT(30)) -#define RTC_CNTL_XTL_EXT_CTR_LV_M (RTC_CNTL_XTL_EXT_CTR_LV_V << RTC_CNTL_XTL_EXT_CTR_LV_S) -#define RTC_CNTL_XTL_EXT_CTR_LV_V 0x00000001 -#define RTC_CNTL_XTL_EXT_CTR_LV_S 30 - -/* RTC_CNTL_RTC_XTAL32K_GPIO_SEL : R/W; bitpos: [23]; default: 0; - * XTAL_32K sel. 0: external XTAL_32K, 1: CLK from RTC pad X32P_C - */ - -#define RTC_CNTL_RTC_XTAL32K_GPIO_SEL (BIT(23)) -#define RTC_CNTL_RTC_XTAL32K_GPIO_SEL_M (RTC_CNTL_RTC_XTAL32K_GPIO_SEL_V << RTC_CNTL_RTC_XTAL32K_GPIO_SEL_S) -#define RTC_CNTL_RTC_XTAL32K_GPIO_SEL_V 0x00000001 -#define RTC_CNTL_RTC_XTAL32K_GPIO_SEL_S 23 - -/* RTC_CNTL_RTC_WDT_STATE : RO; bitpos: [22:20]; default: 0; - * state of 32k_wdt - */ - -#define RTC_CNTL_RTC_WDT_STATE 0x00000007 -#define RTC_CNTL_RTC_WDT_STATE_M (RTC_CNTL_RTC_WDT_STATE_V << RTC_CNTL_RTC_WDT_STATE_S) -#define RTC_CNTL_RTC_WDT_STATE_V 0x00000007 -#define RTC_CNTL_RTC_WDT_STATE_S 20 - -/* RTC_CNTL_DAC_XTAL_32K : R/W; bitpos: [19:17]; default: 3; - * DAC_XTAL_32K - */ - -#define RTC_CNTL_DAC_XTAL_32K 0x00000007 -#define RTC_CNTL_DAC_XTAL_32K_M (RTC_CNTL_DAC_XTAL_32K_V << RTC_CNTL_DAC_XTAL_32K_S) -#define RTC_CNTL_DAC_XTAL_32K_V 0x00000007 -#define RTC_CNTL_DAC_XTAL_32K_S 17 - -/* RTC_CNTL_XPD_XTAL_32K : R/W; bitpos: [16]; default: 0; - * XPD_XTAL_32K - */ - -#define RTC_CNTL_XPD_XTAL_32K (BIT(16)) -#define RTC_CNTL_XPD_XTAL_32K_M (RTC_CNTL_XPD_XTAL_32K_V << RTC_CNTL_XPD_XTAL_32K_S) -#define RTC_CNTL_XPD_XTAL_32K_V 0x00000001 -#define RTC_CNTL_XPD_XTAL_32K_S 16 - -/* RTC_CNTL_DRES_XTAL_32K : R/W; bitpos: [15:13]; default: 3; - * DRES_XTAL_32K - */ - -#define RTC_CNTL_DRES_XTAL_32K 0x00000007 -#define RTC_CNTL_DRES_XTAL_32K_M (RTC_CNTL_DRES_XTAL_32K_V << RTC_CNTL_DRES_XTAL_32K_S) -#define RTC_CNTL_DRES_XTAL_32K_V 0x00000007 -#define RTC_CNTL_DRES_XTAL_32K_S 13 - -/* RTC_CNTL_DGM_XTAL_32K : R/W; bitpos: [12:10]; default: 3; - * xtal_32k gm control - */ - -#define RTC_CNTL_DGM_XTAL_32K 0x00000007 -#define RTC_CNTL_DGM_XTAL_32K_M (RTC_CNTL_DGM_XTAL_32K_V << RTC_CNTL_DGM_XTAL_32K_S) -#define RTC_CNTL_DGM_XTAL_32K_V 0x00000007 -#define RTC_CNTL_DGM_XTAL_32K_S 10 - -/* RTC_CNTL_DBUF_XTAL_32K : R/W; bitpos: [9]; default: 0; - * 0: single-end buffer 1: differential buffer - */ - -#define RTC_CNTL_DBUF_XTAL_32K (BIT(9)) -#define RTC_CNTL_DBUF_XTAL_32K_M (RTC_CNTL_DBUF_XTAL_32K_V << RTC_CNTL_DBUF_XTAL_32K_S) -#define RTC_CNTL_DBUF_XTAL_32K_V 0x00000001 -#define RTC_CNTL_DBUF_XTAL_32K_S 9 - -/* RTC_CNTL_ENCKINIT_XTAL_32K : R/W; bitpos: [8]; default: 0; - * apply an internal clock to help xtal 32k to start - */ - -#define RTC_CNTL_ENCKINIT_XTAL_32K (BIT(8)) -#define RTC_CNTL_ENCKINIT_XTAL_32K_M (RTC_CNTL_ENCKINIT_XTAL_32K_V << RTC_CNTL_ENCKINIT_XTAL_32K_S) -#define RTC_CNTL_ENCKINIT_XTAL_32K_V 0x00000001 -#define RTC_CNTL_ENCKINIT_XTAL_32K_S 8 - -/* RTC_CNTL_XTAL32K_XPD_FORCE : R/W; bitpos: [7]; default: 1; - * Xtal 32k xpd control by sw or fsm - */ - -#define RTC_CNTL_XTAL32K_XPD_FORCE (BIT(7)) -#define RTC_CNTL_XTAL32K_XPD_FORCE_M (RTC_CNTL_XTAL32K_XPD_FORCE_V << RTC_CNTL_XTAL32K_XPD_FORCE_S) -#define RTC_CNTL_XTAL32K_XPD_FORCE_V 0x00000001 -#define RTC_CNTL_XTAL32K_XPD_FORCE_S 7 - -/* RTC_CNTL_XTAL32K_AUTO_RETURN : R/W; bitpos: [6]; default: 0; - * xtal 32k switch back xtal when xtal is restarted - */ - -#define RTC_CNTL_XTAL32K_AUTO_RETURN (BIT(6)) -#define RTC_CNTL_XTAL32K_AUTO_RETURN_M (RTC_CNTL_XTAL32K_AUTO_RETURN_V << RTC_CNTL_XTAL32K_AUTO_RETURN_S) -#define RTC_CNTL_XTAL32K_AUTO_RETURN_V 0x00000001 -#define RTC_CNTL_XTAL32K_AUTO_RETURN_S 6 - -/* RTC_CNTL_XTAL32K_AUTO_RESTART : R/W; bitpos: [5]; default: 0; - * xtal 32k restart xtal when xtal is dead - */ - -#define RTC_CNTL_XTAL32K_AUTO_RESTART (BIT(5)) -#define RTC_CNTL_XTAL32K_AUTO_RESTART_M (RTC_CNTL_XTAL32K_AUTO_RESTART_V << RTC_CNTL_XTAL32K_AUTO_RESTART_S) -#define RTC_CNTL_XTAL32K_AUTO_RESTART_V 0x00000001 -#define RTC_CNTL_XTAL32K_AUTO_RESTART_S 5 - -/* RTC_CNTL_XTAL32K_AUTO_BACKUP : R/W; bitpos: [4]; default: 0; - * xtal 32k switch to back up clock when xtal is dead - */ - -#define RTC_CNTL_XTAL32K_AUTO_BACKUP (BIT(4)) -#define RTC_CNTL_XTAL32K_AUTO_BACKUP_M (RTC_CNTL_XTAL32K_AUTO_BACKUP_V << RTC_CNTL_XTAL32K_AUTO_BACKUP_S) -#define RTC_CNTL_XTAL32K_AUTO_BACKUP_V 0x00000001 -#define RTC_CNTL_XTAL32K_AUTO_BACKUP_S 4 - -/* RTC_CNTL_XTAL32K_EXT_CLK_FO : R/W; bitpos: [3]; default: 0; - * xtal 32k external xtal clock force on - */ - -#define RTC_CNTL_XTAL32K_EXT_CLK_FO (BIT(3)) -#define RTC_CNTL_XTAL32K_EXT_CLK_FO_M (RTC_CNTL_XTAL32K_EXT_CLK_FO_V << RTC_CNTL_XTAL32K_EXT_CLK_FO_S) -#define RTC_CNTL_XTAL32K_EXT_CLK_FO_V 0x00000001 -#define RTC_CNTL_XTAL32K_EXT_CLK_FO_S 3 - -/* RTC_CNTL_XTAL32K_WDT_RESET : R/W; bitpos: [2]; default: 0; - * xtal 32k watch dog sw reset - */ - -#define RTC_CNTL_XTAL32K_WDT_RESET (BIT(2)) -#define RTC_CNTL_XTAL32K_WDT_RESET_M (RTC_CNTL_XTAL32K_WDT_RESET_V << RTC_CNTL_XTAL32K_WDT_RESET_S) -#define RTC_CNTL_XTAL32K_WDT_RESET_V 0x00000001 -#define RTC_CNTL_XTAL32K_WDT_RESET_S 2 - -/* RTC_CNTL_XTAL32K_WDT_CLK_FO : R/W; bitpos: [1]; default: 0; - * xtal 32k watch dog clock force on - */ - -#define RTC_CNTL_XTAL32K_WDT_CLK_FO (BIT(1)) -#define RTC_CNTL_XTAL32K_WDT_CLK_FO_M (RTC_CNTL_XTAL32K_WDT_CLK_FO_V << RTC_CNTL_XTAL32K_WDT_CLK_FO_S) -#define RTC_CNTL_XTAL32K_WDT_CLK_FO_V 0x00000001 -#define RTC_CNTL_XTAL32K_WDT_CLK_FO_S 1 - -/* RTC_CNTL_XTAL32K_WDT_EN : R/W; bitpos: [0]; default: 0; - * xtal 32k watch dog enable - */ - -#define RTC_CNTL_XTAL32K_WDT_EN (BIT(0)) -#define RTC_CNTL_XTAL32K_WDT_EN_M (RTC_CNTL_XTAL32K_WDT_EN_V << RTC_CNTL_XTAL32K_WDT_EN_S) -#define RTC_CNTL_XTAL32K_WDT_EN_V 0x00000001 -#define RTC_CNTL_XTAL32K_WDT_EN_S 0 - -/* RTC_CNTL_RTC_EXT_WAKEUP_CONF_REG register - * ext wakeup configure - */ - -#define RTC_CNTL_RTC_EXT_WAKEUP_CONF_REG (DR_REG_RTCCNTL_BASE + 0x64) - -/* RTC_CNTL_EXT_WAKEUP1_LV : R/W; bitpos: [31]; default: 0; - * 0: external wakeup at low level, 1: external wakeup at high level - */ - -#define RTC_CNTL_EXT_WAKEUP1_LV (BIT(31)) -#define RTC_CNTL_EXT_WAKEUP1_LV_M (RTC_CNTL_EXT_WAKEUP1_LV_V << RTC_CNTL_EXT_WAKEUP1_LV_S) -#define RTC_CNTL_EXT_WAKEUP1_LV_V 0x00000001 -#define RTC_CNTL_EXT_WAKEUP1_LV_S 31 - -/* RTC_CNTL_EXT_WAKEUP0_LV : R/W; bitpos: [30]; default: 0; - * 0: external wakeup at low level, 1: external wakeup at high level - */ - -#define RTC_CNTL_EXT_WAKEUP0_LV (BIT(30)) -#define RTC_CNTL_EXT_WAKEUP0_LV_M (RTC_CNTL_EXT_WAKEUP0_LV_V << RTC_CNTL_EXT_WAKEUP0_LV_S) -#define RTC_CNTL_EXT_WAKEUP0_LV_V 0x00000001 -#define RTC_CNTL_EXT_WAKEUP0_LV_S 30 - -/* RTC_CNTL_GPIO_WAKEUP_FILTER : R/W; bitpos: [29]; default: 0; - * enable filter for gpio wakeup event - */ - -#define RTC_CNTL_GPIO_WAKEUP_FILTER (BIT(29)) -#define RTC_CNTL_GPIO_WAKEUP_FILTER_M (RTC_CNTL_GPIO_WAKEUP_FILTER_V << RTC_CNTL_GPIO_WAKEUP_FILTER_S) -#define RTC_CNTL_GPIO_WAKEUP_FILTER_V 0x00000001 -#define RTC_CNTL_GPIO_WAKEUP_FILTER_S 29 - -/* RTC_CNTL_RTC_SLP_REJECT_CONF_REG register - * reject sleep register - */ - -#define RTC_CNTL_RTC_SLP_REJECT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x68) - -/* RTC_CNTL_DEEP_SLP_REJECT_EN : R/W; bitpos: [31]; default: 0; - * enable reject for deep sleep - */ - -#define RTC_CNTL_DEEP_SLP_REJECT_EN (BIT(31)) -#define RTC_CNTL_DEEP_SLP_REJECT_EN_M (RTC_CNTL_DEEP_SLP_REJECT_EN_V << RTC_CNTL_DEEP_SLP_REJECT_EN_S) -#define RTC_CNTL_DEEP_SLP_REJECT_EN_V 0x00000001 -#define RTC_CNTL_DEEP_SLP_REJECT_EN_S 31 - -/* RTC_CNTL_LIGHT_SLP_REJECT_EN : R/W; bitpos: [30]; default: 0; - * enable reject for light sleep - */ - -#define RTC_CNTL_LIGHT_SLP_REJECT_EN (BIT(30)) -#define RTC_CNTL_LIGHT_SLP_REJECT_EN_M (RTC_CNTL_LIGHT_SLP_REJECT_EN_V << RTC_CNTL_LIGHT_SLP_REJECT_EN_S) -#define RTC_CNTL_LIGHT_SLP_REJECT_EN_V 0x00000001 -#define RTC_CNTL_LIGHT_SLP_REJECT_EN_S 30 - -/* RTC_CNTL_RTC_SLEEP_REJECT_ENA : R/W; bitpos: [29:12]; default: 0; - * sleep reject enable - */ - -#define RTC_CNTL_RTC_SLEEP_REJECT_ENA 0x0003ffff -#define RTC_CNTL_RTC_SLEEP_REJECT_ENA_M (RTC_CNTL_RTC_SLEEP_REJECT_ENA_V << RTC_CNTL_RTC_SLEEP_REJECT_ENA_S) -#define RTC_CNTL_RTC_SLEEP_REJECT_ENA_V 0x0003ffff -#define RTC_CNTL_RTC_SLEEP_REJECT_ENA_S 12 - -/* RTC_CNTL_RTC_CPU_PERIOD_CONF_REG register - * configure cpu freq - */ - -#define RTC_CNTL_RTC_CPU_PERIOD_CONF_REG (DR_REG_RTCCNTL_BASE + 0x6c) - -/* RTC_CNTL_RTC_CPUPERIOD_SEL : R/W; bitpos: [31:30]; default: 0; - * configure cpu freq - */ - -#define RTC_CNTL_RTC_CPUPERIOD_SEL 0x00000003 -#define RTC_CNTL_RTC_CPUPERIOD_SEL_M (RTC_CNTL_RTC_CPUPERIOD_SEL_V << RTC_CNTL_RTC_CPUPERIOD_SEL_S) -#define RTC_CNTL_RTC_CPUPERIOD_SEL_V 0x00000003 -#define RTC_CNTL_RTC_CPUPERIOD_SEL_S 30 - -/* RTC_CNTL_RTC_CPUSEL_CONF : R/W; bitpos: [29]; default: 0; - * CPU sel option - */ - -#define RTC_CNTL_RTC_CPUSEL_CONF (BIT(29)) -#define RTC_CNTL_RTC_CPUSEL_CONF_M (RTC_CNTL_RTC_CPUSEL_CONF_V << RTC_CNTL_RTC_CPUSEL_CONF_S) -#define RTC_CNTL_RTC_CPUSEL_CONF_V 0x00000001 -#define RTC_CNTL_RTC_CPUSEL_CONF_S 29 - -/* RTC_CNTL_RTC_SDIO_ACT_CONF_REG register - * No public - */ - -#define RTC_CNTL_RTC_SDIO_ACT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x70) - -/* RTC_CNTL_SDIO_ACT_DNUM : R/W; bitpos: [31:22]; default: 0; - * No public - */ - -#define RTC_CNTL_SDIO_ACT_DNUM 0x000003ff -#define RTC_CNTL_SDIO_ACT_DNUM_M (RTC_CNTL_SDIO_ACT_DNUM_V << RTC_CNTL_SDIO_ACT_DNUM_S) -#define RTC_CNTL_SDIO_ACT_DNUM_V 0x000003ff -#define RTC_CNTL_SDIO_ACT_DNUM_S 22 - -/* RTC_CNTL_RTC_CLK_CONF_REG register - * configure clock register - */ - -#define RTC_CNTL_RTC_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x74) - -/* RTC_CNTL_ANA_CLK_RTC_SEL : R/W; bitpos: [31:30]; default: 0; - * select slow clock - */ - -#define RTC_CNTL_ANA_CLK_RTC_SEL 0x00000003 -#define RTC_CNTL_ANA_CLK_RTC_SEL_M (RTC_CNTL_ANA_CLK_RTC_SEL_V << RTC_CNTL_ANA_CLK_RTC_SEL_S) -#define RTC_CNTL_ANA_CLK_RTC_SEL_V 0x00000003 -#define RTC_CNTL_ANA_CLK_RTC_SEL_S 30 - -/* RTC_CNTL_FAST_CLK_RTC_SEL : R/W; bitpos: [29]; default: 0; - * fast_clk_rtc sel. 0: XTAL div 4, 1: CK8M - */ - -#define RTC_CNTL_FAST_CLK_RTC_SEL (BIT(29)) -#define RTC_CNTL_FAST_CLK_RTC_SEL_M (RTC_CNTL_FAST_CLK_RTC_SEL_V << RTC_CNTL_FAST_CLK_RTC_SEL_S) -#define RTC_CNTL_FAST_CLK_RTC_SEL_V 0x00000001 -#define RTC_CNTL_FAST_CLK_RTC_SEL_S 29 - -/* RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING : R/W; bitpos: [28]; default: 1; - * force global xtal no gating - */ - -#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING (BIT(28)) -#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_M (RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_V << RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_S) -#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_V 0x00000001 -#define RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING_S 28 - -/* RTC_CNTL_XTAL_GLOBAL_FORCE_GATING : R/W; bitpos: [27]; default: 0; - * force global xtal gating - */ - -#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING (BIT(27)) -#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_M (RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_V << RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_S) -#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_V 0x00000001 -#define RTC_CNTL_XTAL_GLOBAL_FORCE_GATING_S 27 - -/* RTC_CNTL_CK8M_FORCE_PU : R/W; bitpos: [26]; default: 0; - * CK8M force power up - */ - -#define RTC_CNTL_CK8M_FORCE_PU (BIT(26)) -#define RTC_CNTL_CK8M_FORCE_PU_M (RTC_CNTL_CK8M_FORCE_PU_V << RTC_CNTL_CK8M_FORCE_PU_S) -#define RTC_CNTL_CK8M_FORCE_PU_V 0x00000001 -#define RTC_CNTL_CK8M_FORCE_PU_S 26 - -/* RTC_CNTL_CK8M_FORCE_PD : R/W; bitpos: [25]; default: 0; - * CK8M force power down - */ - -#define RTC_CNTL_CK8M_FORCE_PD (BIT(25)) -#define RTC_CNTL_CK8M_FORCE_PD_M (RTC_CNTL_CK8M_FORCE_PD_V << RTC_CNTL_CK8M_FORCE_PD_S) -#define RTC_CNTL_CK8M_FORCE_PD_V 0x00000001 -#define RTC_CNTL_CK8M_FORCE_PD_S 25 - -/* RTC_CNTL_CK8M_DFREQ : R/W; bitpos: [24:17]; default: 172; - * CK8M_DFREQ - */ - -#define RTC_CNTL_CK8M_DFREQ 0x000000ff -#define RTC_CNTL_CK8M_DFREQ_M (RTC_CNTL_CK8M_DFREQ_V << RTC_CNTL_CK8M_DFREQ_S) -#define RTC_CNTL_CK8M_DFREQ_V 0x000000ff -#define RTC_CNTL_CK8M_DFREQ_S 17 - -/* RTC_CNTL_CK8M_FORCE_NOGATING : R/W; bitpos: [16]; default: 0; - * CK8M force no gating during sleep - */ - -#define RTC_CNTL_CK8M_FORCE_NOGATING (BIT(16)) -#define RTC_CNTL_CK8M_FORCE_NOGATING_M (RTC_CNTL_CK8M_FORCE_NOGATING_V << RTC_CNTL_CK8M_FORCE_NOGATING_S) -#define RTC_CNTL_CK8M_FORCE_NOGATING_V 0x00000001 -#define RTC_CNTL_CK8M_FORCE_NOGATING_S 16 - -/* RTC_CNTL_XTAL_FORCE_NOGATING : R/W; bitpos: [15]; default: 0; - * XTAL force no gating during sleep - */ - -#define RTC_CNTL_XTAL_FORCE_NOGATING (BIT(15)) -#define RTC_CNTL_XTAL_FORCE_NOGATING_M (RTC_CNTL_XTAL_FORCE_NOGATING_V << RTC_CNTL_XTAL_FORCE_NOGATING_S) -#define RTC_CNTL_XTAL_FORCE_NOGATING_V 0x00000001 -#define RTC_CNTL_XTAL_FORCE_NOGATING_S 15 - -/* RTC_CNTL_CK8M_DIV_SEL : R/W; bitpos: [14:12]; default: 3; - * divider = reg_ck8m_div_sel + 1 - */ - -#define RTC_CNTL_CK8M_DIV_SEL 0x00000007 -#define RTC_CNTL_CK8M_DIV_SEL_M (RTC_CNTL_CK8M_DIV_SEL_V << RTC_CNTL_CK8M_DIV_SEL_S) -#define RTC_CNTL_CK8M_DIV_SEL_V 0x00000007 -#define RTC_CNTL_CK8M_DIV_SEL_S 12 - -/* RTC_CNTL_DIG_CLK8M_EN : R/W; bitpos: [10]; default: 0; - * enable CK8M for digital core (no relationship with RTC core) - */ - -#define RTC_CNTL_DIG_CLK8M_EN (BIT(10)) -#define RTC_CNTL_DIG_CLK8M_EN_M (RTC_CNTL_DIG_CLK8M_EN_V << RTC_CNTL_DIG_CLK8M_EN_S) -#define RTC_CNTL_DIG_CLK8M_EN_V 0x00000001 -#define RTC_CNTL_DIG_CLK8M_EN_S 10 - -/* RTC_CNTL_DIG_CLK8M_D256_EN : R/W; bitpos: [9]; default: 1; - * enable CK8M_D256_OUT for digital core (no relationship with RTC core) - */ - -#define RTC_CNTL_DIG_CLK8M_D256_EN (BIT(9)) -#define RTC_CNTL_DIG_CLK8M_D256_EN_M (RTC_CNTL_DIG_CLK8M_D256_EN_V << RTC_CNTL_DIG_CLK8M_D256_EN_S) -#define RTC_CNTL_DIG_CLK8M_D256_EN_V 0x00000001 -#define RTC_CNTL_DIG_CLK8M_D256_EN_S 9 - -/* RTC_CNTL_DIG_XTAL32K_EN : R/W; bitpos: [8]; default: 0; - * enable CK_XTAL_32K for digital core (no relationship with RTC core) - */ - -#define RTC_CNTL_DIG_XTAL32K_EN (BIT(8)) -#define RTC_CNTL_DIG_XTAL32K_EN_M (RTC_CNTL_DIG_XTAL32K_EN_V << RTC_CNTL_DIG_XTAL32K_EN_S) -#define RTC_CNTL_DIG_XTAL32K_EN_V 0x00000001 -#define RTC_CNTL_DIG_XTAL32K_EN_S 8 - -/* RTC_CNTL_ENB_CK8M_DIV : R/W; bitpos: [7]; default: 0; - * 1: CK8M_D256_OUT is actually CK8M, 0: CK8M_D256_OUT is CK8M divided by 256 - */ - -#define RTC_CNTL_ENB_CK8M_DIV (BIT(7)) -#define RTC_CNTL_ENB_CK8M_DIV_M (RTC_CNTL_ENB_CK8M_DIV_V << RTC_CNTL_ENB_CK8M_DIV_S) -#define RTC_CNTL_ENB_CK8M_DIV_V 0x00000001 -#define RTC_CNTL_ENB_CK8M_DIV_S 7 - -/* RTC_CNTL_ENB_CK8M : R/W; bitpos: [6]; default: 0; - * disable CK8M and CK8M_D256_OUT - */ - -#define RTC_CNTL_ENB_CK8M (BIT(6)) -#define RTC_CNTL_ENB_CK8M_M (RTC_CNTL_ENB_CK8M_V << RTC_CNTL_ENB_CK8M_S) -#define RTC_CNTL_ENB_CK8M_V 0x00000001 -#define RTC_CNTL_ENB_CK8M_S 6 - -/* RTC_CNTL_CK8M_DIV : R/W; bitpos: [5:4]; default: 1; - * CK8M_D256_OUT divider. 00: div128, 01: div256, 10: div512, 11: div1024. - */ - -#define RTC_CNTL_CK8M_DIV 0x00000003 -#define RTC_CNTL_CK8M_DIV_M (RTC_CNTL_CK8M_DIV_V << RTC_CNTL_CK8M_DIV_S) -#define RTC_CNTL_CK8M_DIV_V 0x00000003 -#define RTC_CNTL_CK8M_DIV_S 4 - -/* RTC_CNTL_CK8M_DIV_SEL_VLD : R/W; bitpos: [3]; default: 1; - * used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel, - * then set vld to actually switch the clk - */ - -#define RTC_CNTL_CK8M_DIV_SEL_VLD (BIT(3)) -#define RTC_CNTL_CK8M_DIV_SEL_VLD_M (RTC_CNTL_CK8M_DIV_SEL_VLD_V << RTC_CNTL_CK8M_DIV_SEL_VLD_S) -#define RTC_CNTL_CK8M_DIV_SEL_VLD_V 0x00000001 -#define RTC_CNTL_CK8M_DIV_SEL_VLD_S 3 - -/* RTC_CNTL_EFUSE_CLK_FORCE_NOGATING : R/W; bitpos: [2]; default: 1; - * force efuse clk nogating - */ - -#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING (BIT(2)) -#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_M (RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_V << RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_S) -#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_V 0x00000001 -#define RTC_CNTL_EFUSE_CLK_FORCE_NOGATING_S 2 - -/* RTC_CNTL_EFUSE_CLK_FORCE_GATING : R/W; bitpos: [1]; default: 0; - * force efuse clk gating - */ - -#define RTC_CNTL_EFUSE_CLK_FORCE_GATING (BIT(1)) -#define RTC_CNTL_EFUSE_CLK_FORCE_GATING_M (RTC_CNTL_EFUSE_CLK_FORCE_GATING_V << RTC_CNTL_EFUSE_CLK_FORCE_GATING_S) -#define RTC_CNTL_EFUSE_CLK_FORCE_GATING_V 0x00000001 -#define RTC_CNTL_EFUSE_CLK_FORCE_GATING_S 1 - -/* RTC_CNTL_RTC_SLOW_CLK_CONF_REG register - * configure slow clk - */ - -#define RTC_CNTL_RTC_SLOW_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x78) - -/* RTC_CNTL_RTC_SLOW_CLK_NEXT_EDGE : R/W; bitpos: [31]; default: 0; - * No public - */ - -#define RTC_CNTL_RTC_SLOW_CLK_NEXT_EDGE (BIT(31)) -#define RTC_CNTL_RTC_SLOW_CLK_NEXT_EDGE_M (RTC_CNTL_RTC_SLOW_CLK_NEXT_EDGE_V << RTC_CNTL_RTC_SLOW_CLK_NEXT_EDGE_S) -#define RTC_CNTL_RTC_SLOW_CLK_NEXT_EDGE_V 0x00000001 -#define RTC_CNTL_RTC_SLOW_CLK_NEXT_EDGE_S 31 - -/* RTC_CNTL_RTC_ANA_CLK_DIV : R/W; bitpos: [30:23]; default: 0; - * rtc clk div - */ - -#define RTC_CNTL_RTC_ANA_CLK_DIV 0x000000ff -#define RTC_CNTL_RTC_ANA_CLK_DIV_M (RTC_CNTL_RTC_ANA_CLK_DIV_V << RTC_CNTL_RTC_ANA_CLK_DIV_S) -#define RTC_CNTL_RTC_ANA_CLK_DIV_V 0x000000ff -#define RTC_CNTL_RTC_ANA_CLK_DIV_S 23 - -/* RTC_CNTL_RTC_ANA_CLK_DIV_VLD : R/W; bitpos: [22]; default: 1; - * used to sync div bus. clear vld before set reg_rtc_ana_clk_div, then set - * vld to actually switch the clk - */ - -#define RTC_CNTL_RTC_ANA_CLK_DIV_VLD (BIT(22)) -#define RTC_CNTL_RTC_ANA_CLK_DIV_VLD_M (RTC_CNTL_RTC_ANA_CLK_DIV_VLD_V << RTC_CNTL_RTC_ANA_CLK_DIV_VLD_S) -#define RTC_CNTL_RTC_ANA_CLK_DIV_VLD_V 0x00000001 -#define RTC_CNTL_RTC_ANA_CLK_DIV_VLD_S 22 - -/* RTC_CNTL_RTC_SDIO_CONF_REG register - * configure flash power - */ - -#define RTC_CNTL_RTC_SDIO_CONF_REG (DR_REG_RTCCNTL_BASE + 0x7c) - -/* RTC_CNTL_XPD_SDIO_REG : R/W; bitpos: [31]; default: 0; - * power on flash regulator - */ - -#define RTC_CNTL_XPD_SDIO_REG (BIT(31)) -#define RTC_CNTL_XPD_SDIO_REG_M (RTC_CNTL_XPD_SDIO_REG_V << RTC_CNTL_XPD_SDIO_REG_S) -#define RTC_CNTL_XPD_SDIO_REG_V 0x00000001 -#define RTC_CNTL_XPD_SDIO_REG_S 31 - -/* RTC_CNTL_DREFH_SDIO : R/W; bitpos: [30:29]; default: 0; - * SW option for DREFH_SDIO. Only active when reg_sdio_force = 1 - */ - -#define RTC_CNTL_DREFH_SDIO 0x00000003 -#define RTC_CNTL_DREFH_SDIO_M (RTC_CNTL_DREFH_SDIO_V << RTC_CNTL_DREFH_SDIO_S) -#define RTC_CNTL_DREFH_SDIO_V 0x00000003 -#define RTC_CNTL_DREFH_SDIO_S 29 - -/* RTC_CNTL_DREFM_SDIO : R/W; bitpos: [28:27]; default: 1; - * SW option for DREFM_SDIO. Only active when reg_sdio_force = 1 - */ - -#define RTC_CNTL_DREFM_SDIO 0x00000003 -#define RTC_CNTL_DREFM_SDIO_M (RTC_CNTL_DREFM_SDIO_V << RTC_CNTL_DREFM_SDIO_S) -#define RTC_CNTL_DREFM_SDIO_V 0x00000003 -#define RTC_CNTL_DREFM_SDIO_S 27 - -/* RTC_CNTL_DREFL_SDIO : R/W; bitpos: [26:25]; default: 1; - * SW option for DREFL_SDIO. Only active when reg_sdio_force = 1 - */ - -#define RTC_CNTL_DREFL_SDIO 0x00000003 -#define RTC_CNTL_DREFL_SDIO_M (RTC_CNTL_DREFL_SDIO_V << RTC_CNTL_DREFL_SDIO_S) -#define RTC_CNTL_DREFL_SDIO_V 0x00000003 -#define RTC_CNTL_DREFL_SDIO_S 25 - -/* RTC_CNTL_REG1P8_READY : RO; bitpos: [24]; default: 0; - * read only register for REG1P8_READY - */ - -#define RTC_CNTL_REG1P8_READY (BIT(24)) -#define RTC_CNTL_REG1P8_READY_M (RTC_CNTL_REG1P8_READY_V << RTC_CNTL_REG1P8_READY_S) -#define RTC_CNTL_REG1P8_READY_V 0x00000001 -#define RTC_CNTL_REG1P8_READY_S 24 - -/* RTC_CNTL_SDIO_TIEH : R/W; bitpos: [23]; default: 1; - * SW option for SDIO_TIEH. Only active when reg_sdio_force = 1 - */ - -#define RTC_CNTL_SDIO_TIEH (BIT(23)) -#define RTC_CNTL_SDIO_TIEH_M (RTC_CNTL_SDIO_TIEH_V << RTC_CNTL_SDIO_TIEH_S) -#define RTC_CNTL_SDIO_TIEH_V 0x00000001 -#define RTC_CNTL_SDIO_TIEH_S 23 - -/* RTC_CNTL_SDIO_FORCE : R/W; bitpos: [22]; default: 0; - * 1: use SW option to control SDIO_REG, 0: use state machine - */ - -#define RTC_CNTL_SDIO_FORCE (BIT(22)) -#define RTC_CNTL_SDIO_FORCE_M (RTC_CNTL_SDIO_FORCE_V << RTC_CNTL_SDIO_FORCE_S) -#define RTC_CNTL_SDIO_FORCE_V 0x00000001 -#define RTC_CNTL_SDIO_FORCE_S 22 - -/* RTC_CNTL_SDIO_REG_PD_EN : R/W; bitpos: [21]; default: 1; - * power down SDIO_REG in sleep. Only active when reg_sdio_force = 0 - */ - -#define RTC_CNTL_SDIO_REG_PD_EN (BIT(21)) -#define RTC_CNTL_SDIO_REG_PD_EN_M (RTC_CNTL_SDIO_REG_PD_EN_V << RTC_CNTL_SDIO_REG_PD_EN_S) -#define RTC_CNTL_SDIO_REG_PD_EN_V 0x00000001 -#define RTC_CNTL_SDIO_REG_PD_EN_S 21 - -/* RTC_CNTL_SDIO_ENCURLIM : R/W; bitpos: [20]; default: 1; - * enable current limit - */ - -#define RTC_CNTL_SDIO_ENCURLIM (BIT(20)) -#define RTC_CNTL_SDIO_ENCURLIM_M (RTC_CNTL_SDIO_ENCURLIM_V << RTC_CNTL_SDIO_ENCURLIM_S) -#define RTC_CNTL_SDIO_ENCURLIM_V 0x00000001 -#define RTC_CNTL_SDIO_ENCURLIM_S 20 - -/* RTC_CNTL_SDIO_MODECURLIM : R/W; bitpos: [19]; default: 0; - * select current limit mode - */ - -#define RTC_CNTL_SDIO_MODECURLIM (BIT(19)) -#define RTC_CNTL_SDIO_MODECURLIM_M (RTC_CNTL_SDIO_MODECURLIM_V << RTC_CNTL_SDIO_MODECURLIM_S) -#define RTC_CNTL_SDIO_MODECURLIM_V 0x00000001 -#define RTC_CNTL_SDIO_MODECURLIM_S 19 - -/* RTC_CNTL_SDIO_DCURLIM : R/W; bitpos: [18:16]; default: 0; - * tune current limit threshold when tieh = 0. About 800mA/(8+d) - */ - -#define RTC_CNTL_SDIO_DCURLIM 0x00000007 -#define RTC_CNTL_SDIO_DCURLIM_M (RTC_CNTL_SDIO_DCURLIM_V << RTC_CNTL_SDIO_DCURLIM_S) -#define RTC_CNTL_SDIO_DCURLIM_V 0x00000007 -#define RTC_CNTL_SDIO_DCURLIM_S 16 - -/* RTC_CNTL_SDIO_EN_INITI : R/W; bitpos: [15]; default: 1; - * 0 to set init[1:0]=0 - */ - -#define RTC_CNTL_SDIO_EN_INITI (BIT(15)) -#define RTC_CNTL_SDIO_EN_INITI_M (RTC_CNTL_SDIO_EN_INITI_V << RTC_CNTL_SDIO_EN_INITI_S) -#define RTC_CNTL_SDIO_EN_INITI_V 0x00000001 -#define RTC_CNTL_SDIO_EN_INITI_S 15 - -/* RTC_CNTL_SDIO_INITI : R/W; bitpos: [14:13]; default: 1; - * add resistor from ldo output to ground. 0: no res, 1: 6k,2:4k,3:2k - */ - -#define RTC_CNTL_SDIO_INITI 0x00000003 -#define RTC_CNTL_SDIO_INITI_M (RTC_CNTL_SDIO_INITI_V << RTC_CNTL_SDIO_INITI_S) -#define RTC_CNTL_SDIO_INITI_V 0x00000003 -#define RTC_CNTL_SDIO_INITI_S 13 - -/* RTC_CNTL_SDIO_DCAP : R/W; bitpos: [12:11]; default: 3; - * ability to prevent LDO from overshoot - */ - -#define RTC_CNTL_SDIO_DCAP 0x00000003 -#define RTC_CNTL_SDIO_DCAP_M (RTC_CNTL_SDIO_DCAP_V << RTC_CNTL_SDIO_DCAP_S) -#define RTC_CNTL_SDIO_DCAP_V 0x00000003 -#define RTC_CNTL_SDIO_DCAP_S 11 - -/* RTC_CNTL_SDIO_DTHDRV : R/W; bitpos: [10:9]; default: 3; - * Tieh = 1 mode drive ability. Initially set to 0 to limit charge current, - * set to 3 after several us. - */ - -#define RTC_CNTL_SDIO_DTHDRV 0x00000003 -#define RTC_CNTL_SDIO_DTHDRV_M (RTC_CNTL_SDIO_DTHDRV_V << RTC_CNTL_SDIO_DTHDRV_S) -#define RTC_CNTL_SDIO_DTHDRV_V 0x00000003 -#define RTC_CNTL_SDIO_DTHDRV_S 9 - -/* RTC_CNTL_SDIO_TIMER_TARGET : R/W; bitpos: [7:0]; default: 10; - * timer count to apply reg_sdio_dcap after sdio power on - */ - -#define RTC_CNTL_SDIO_TIMER_TARGET 0x000000ff -#define RTC_CNTL_SDIO_TIMER_TARGET_M (RTC_CNTL_SDIO_TIMER_TARGET_V << RTC_CNTL_SDIO_TIMER_TARGET_S) -#define RTC_CNTL_SDIO_TIMER_TARGET_V 0x000000ff -#define RTC_CNTL_SDIO_TIMER_TARGET_S 0 - -/* RTC_CNTL_RTC_BIAS_CONF_REG register - * No public - */ - -#define RTC_CNTL_RTC_BIAS_CONF_REG (DR_REG_RTCCNTL_BASE + 0x80) - -/* RTC_CNTL_DBG_ATTEN_WAKEUP : R/W; bitpos: [29:26]; default: 0; - * No public - */ - -#define RTC_CNTL_DBG_ATTEN_WAKEUP 0x0000000f -#define RTC_CNTL_DBG_ATTEN_WAKEUP_M (RTC_CNTL_DBG_ATTEN_WAKEUP_V << RTC_CNTL_DBG_ATTEN_WAKEUP_S) -#define RTC_CNTL_DBG_ATTEN_WAKEUP_V 0x0000000f -#define RTC_CNTL_DBG_ATTEN_WAKEUP_S 26 - -/* RTC_CNTL_DBG_ATTEN_MONITOR : R/W; bitpos: [25:22]; default: 0; - * DBG_ATTEN when rtc in monitor state - */ - -#define RTC_CNTL_DBG_ATTEN_MONITOR 0x0000000f -#define RTC_CNTL_DBG_ATTEN_MONITOR_M (RTC_CNTL_DBG_ATTEN_MONITOR_V << RTC_CNTL_DBG_ATTEN_MONITOR_S) -#define RTC_CNTL_DBG_ATTEN_MONITOR_V 0x0000000f -#define RTC_CNTL_DBG_ATTEN_MONITOR_S 22 - -/* RTC_CNTL_DBG_ATTEN_DEEP_SLP : R/W; bitpos: [21:18]; default: 0; - * DBG_ATTEN when rtc in sleep state - */ - -#define RTC_CNTL_DBG_ATTEN_DEEP_SLP 0x0000000f -#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_M (RTC_CNTL_DBG_ATTEN_DEEP_SLP_V << RTC_CNTL_DBG_ATTEN_DEEP_SLP_S) -#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_V 0x0000000f -#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_S 18 - -/* RTC_CNTL_BIAS_SLEEP_MONITOR : R/W; bitpos: [17]; default: 0; - * bias_sleep when rtc in monitor state - */ - -#define RTC_CNTL_BIAS_SLEEP_MONITOR (BIT(17)) -#define RTC_CNTL_BIAS_SLEEP_MONITOR_M (RTC_CNTL_BIAS_SLEEP_MONITOR_V << RTC_CNTL_BIAS_SLEEP_MONITOR_S) -#define RTC_CNTL_BIAS_SLEEP_MONITOR_V 0x00000001 -#define RTC_CNTL_BIAS_SLEEP_MONITOR_S 17 - -/* RTC_CNTL_BIAS_SLEEP_DEEP_SLP : R/W; bitpos: [16]; default: 1; - * bias_sleep when rtc in sleep_state - */ - -#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP (BIT(16)) -#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_M (RTC_CNTL_BIAS_SLEEP_DEEP_SLP_V << RTC_CNTL_BIAS_SLEEP_DEEP_SLP_S) -#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_V 0x00000001 -#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_S 16 - -/* RTC_CNTL_PD_CUR_MONITOR : R/W; bitpos: [15]; default: 0; - * xpd cur when rtc in monitor state - */ - -#define RTC_CNTL_PD_CUR_MONITOR (BIT(15)) -#define RTC_CNTL_PD_CUR_MONITOR_M (RTC_CNTL_PD_CUR_MONITOR_V << RTC_CNTL_PD_CUR_MONITOR_S) -#define RTC_CNTL_PD_CUR_MONITOR_V 0x00000001 -#define RTC_CNTL_PD_CUR_MONITOR_S 15 - -/* RTC_CNTL_PD_CUR_DEEP_SLP : R/W; bitpos: [14]; default: 0; - * xpd cur when rtc in sleep_state - */ - -#define RTC_CNTL_PD_CUR_DEEP_SLP (BIT(14)) -#define RTC_CNTL_PD_CUR_DEEP_SLP_M (RTC_CNTL_PD_CUR_DEEP_SLP_V << RTC_CNTL_PD_CUR_DEEP_SLP_S) -#define RTC_CNTL_PD_CUR_DEEP_SLP_V 0x00000001 -#define RTC_CNTL_PD_CUR_DEEP_SLP_S 14 - -/* RTC_CNTL_BIAS_BUF_MONITOR : R/W; bitpos: [13]; default: 0; - * No public - */ - -#define RTC_CNTL_BIAS_BUF_MONITOR (BIT(13)) -#define RTC_CNTL_BIAS_BUF_MONITOR_M (RTC_CNTL_BIAS_BUF_MONITOR_V << RTC_CNTL_BIAS_BUF_MONITOR_S) -#define RTC_CNTL_BIAS_BUF_MONITOR_V 0x00000001 -#define RTC_CNTL_BIAS_BUF_MONITOR_S 13 - -/* RTC_CNTL_BIAS_BUF_DEEP_SLP : R/W; bitpos: [12]; default: 0; - * No public - */ - -#define RTC_CNTL_BIAS_BUF_DEEP_SLP (BIT(12)) -#define RTC_CNTL_BIAS_BUF_DEEP_SLP_M (RTC_CNTL_BIAS_BUF_DEEP_SLP_V << RTC_CNTL_BIAS_BUF_DEEP_SLP_S) -#define RTC_CNTL_BIAS_BUF_DEEP_SLP_V 0x00000001 -#define RTC_CNTL_BIAS_BUF_DEEP_SLP_S 12 - -/* RTC_CNTL_BIAS_BUF_WAKE : R/W; bitpos: [11]; default: 1; - * No public - */ - -#define RTC_CNTL_BIAS_BUF_WAKE (BIT(11)) -#define RTC_CNTL_BIAS_BUF_WAKE_M (RTC_CNTL_BIAS_BUF_WAKE_V << RTC_CNTL_BIAS_BUF_WAKE_S) -#define RTC_CNTL_BIAS_BUF_WAKE_V 0x00000001 -#define RTC_CNTL_BIAS_BUF_WAKE_S 11 - -/* RTC_CNTL_BIAS_BUF_IDLE : R/W; bitpos: [10]; default: 0; - * No public - */ - -#define RTC_CNTL_BIAS_BUF_IDLE (BIT(10)) -#define RTC_CNTL_BIAS_BUF_IDLE_M (RTC_CNTL_BIAS_BUF_IDLE_V << RTC_CNTL_BIAS_BUF_IDLE_S) -#define RTC_CNTL_BIAS_BUF_IDLE_V 0x00000001 -#define RTC_CNTL_BIAS_BUF_IDLE_S 10 - -/* RTC_CNTL_RTC_REG register - * configure rtc regulator - */ - -#define RTC_CNTL_RTC_REG (DR_REG_RTCCNTL_BASE + 0x84) - -/* RTC_CNTL_RTC_REGULATOR_FORCE_PU : R/W; bitpos: [31]; default: 1; - * RTC_REG force power on (for RTC_REG power down means decrease the voltage - * to 0.8v or lower ) - */ - -#define RTC_CNTL_RTC_REGULATOR_FORCE_PU (BIT(31)) -#define RTC_CNTL_RTC_REGULATOR_FORCE_PU_M (RTC_CNTL_RTC_REGULATOR_FORCE_PU_V << RTC_CNTL_RTC_REGULATOR_FORCE_PU_S) -#define RTC_CNTL_RTC_REGULATOR_FORCE_PU_V 0x00000001 -#define RTC_CNTL_RTC_REGULATOR_FORCE_PU_S 31 - -/* RTC_CNTL_RTC_REGULATOR_FORCE_PD : R/W; bitpos: [30]; default: 0; - * RTC_REG force power down (for RTC_REG power down means decrease the - * voltage to 0.8v or lower ) - */ - -#define RTC_CNTL_RTC_REGULATOR_FORCE_PD (BIT(30)) -#define RTC_CNTL_RTC_REGULATOR_FORCE_PD_M (RTC_CNTL_RTC_REGULATOR_FORCE_PD_V << RTC_CNTL_RTC_REGULATOR_FORCE_PD_S) -#define RTC_CNTL_RTC_REGULATOR_FORCE_PD_V 0x00000001 -#define RTC_CNTL_RTC_REGULATOR_FORCE_PD_S 30 - -/* RTC_CNTL_RTC_DBOOST_FORCE_PU : R/W; bitpos: [29]; default: 1; - * RTC_DBOOST force power up - */ - -#define RTC_CNTL_RTC_DBOOST_FORCE_PU (BIT(29)) -#define RTC_CNTL_RTC_DBOOST_FORCE_PU_M (RTC_CNTL_RTC_DBOOST_FORCE_PU_V << RTC_CNTL_RTC_DBOOST_FORCE_PU_S) -#define RTC_CNTL_RTC_DBOOST_FORCE_PU_V 0x00000001 -#define RTC_CNTL_RTC_DBOOST_FORCE_PU_S 29 - -/* RTC_CNTL_RTC_DBOOST_FORCE_PD : R/W; bitpos: [28]; default: 0; - * RTC_DBOOST force power down - */ - -#define RTC_CNTL_RTC_DBOOST_FORCE_PD (BIT(28)) -#define RTC_CNTL_RTC_DBOOST_FORCE_PD_M (RTC_CNTL_RTC_DBOOST_FORCE_PD_V << RTC_CNTL_RTC_DBOOST_FORCE_PD_S) -#define RTC_CNTL_RTC_DBOOST_FORCE_PD_V 0x00000001 -#define RTC_CNTL_RTC_DBOOST_FORCE_PD_S 28 - -/* RTC_CNTL_SCK_DCAP : R/W; bitpos: [21:14]; default: 0; - * SCK_DCAP - */ - -#define RTC_CNTL_SCK_DCAP 0x000000ff -#define RTC_CNTL_SCK_DCAP_M (RTC_CNTL_SCK_DCAP_V << RTC_CNTL_SCK_DCAP_S) -#define RTC_CNTL_SCK_DCAP_V 0x000000ff -#define RTC_CNTL_SCK_DCAP_S 14 - -/* RTC_CNTL_DIG_REG_CAL_EN : R/W; bitpos: [7]; default: 0; - * enable dig regulator cali - */ - -#define RTC_CNTL_DIG_REG_CAL_EN (BIT(7)) -#define RTC_CNTL_DIG_REG_CAL_EN_M (RTC_CNTL_DIG_REG_CAL_EN_V << RTC_CNTL_DIG_REG_CAL_EN_S) -#define RTC_CNTL_DIG_REG_CAL_EN_V 0x00000001 -#define RTC_CNTL_DIG_REG_CAL_EN_S 7 - -/* RTC_CNTL_RTC_PWC_REG register - * configure rtc power - */ - -#define RTC_CNTL_RTC_PWC_REG (DR_REG_RTCCNTL_BASE + 0x88) - -/* RTC_CNTL_RTC_PAD_FORCE_HOLD : R/W; bitpos: [21]; default: 0; - * rtc pad force hold - */ - -#define RTC_CNTL_RTC_PAD_FORCE_HOLD (BIT(21)) -#define RTC_CNTL_RTC_PAD_FORCE_HOLD_M (RTC_CNTL_RTC_PAD_FORCE_HOLD_V << RTC_CNTL_RTC_PAD_FORCE_HOLD_S) -#define RTC_CNTL_RTC_PAD_FORCE_HOLD_V 0x00000001 -#define RTC_CNTL_RTC_PAD_FORCE_HOLD_S 21 - -/* RTC_CNTL_RTC_PD_EN : R/W; bitpos: [20]; default: 0; - * enable power down rtc_peri in sleep - */ - -#define RTC_CNTL_RTC_PD_EN (BIT(20)) -#define RTC_CNTL_RTC_PD_EN_M (RTC_CNTL_RTC_PD_EN_V << RTC_CNTL_RTC_PD_EN_S) -#define RTC_CNTL_RTC_PD_EN_V 0x00000001 -#define RTC_CNTL_RTC_PD_EN_S 20 - -/* RTC_CNTL_RTC_FORCE_PU : R/W; bitpos: [19]; default: 0; - * rtc_peri force power up - */ - -#define RTC_CNTL_RTC_FORCE_PU (BIT(19)) -#define RTC_CNTL_RTC_FORCE_PU_M (RTC_CNTL_RTC_FORCE_PU_V << RTC_CNTL_RTC_FORCE_PU_S) -#define RTC_CNTL_RTC_FORCE_PU_V 0x00000001 -#define RTC_CNTL_RTC_FORCE_PU_S 19 - -/* RTC_CNTL_RTC_FORCE_PD : R/W; bitpos: [18]; default: 0; - * rtc_peri force power down - */ - -#define RTC_CNTL_RTC_FORCE_PD (BIT(18)) -#define RTC_CNTL_RTC_FORCE_PD_M (RTC_CNTL_RTC_FORCE_PD_V << RTC_CNTL_RTC_FORCE_PD_S) -#define RTC_CNTL_RTC_FORCE_PD_V 0x00000001 -#define RTC_CNTL_RTC_FORCE_PD_S 18 - -/* RTC_CNTL_RTC_SLOWMEM_FORCE_LPU : R/W; bitpos: [11]; default: 1; - * RTC memory force no PD - */ - -#define RTC_CNTL_RTC_SLOWMEM_FORCE_LPU (BIT(11)) -#define RTC_CNTL_RTC_SLOWMEM_FORCE_LPU_M (RTC_CNTL_RTC_SLOWMEM_FORCE_LPU_V << RTC_CNTL_RTC_SLOWMEM_FORCE_LPU_S) -#define RTC_CNTL_RTC_SLOWMEM_FORCE_LPU_V 0x00000001 -#define RTC_CNTL_RTC_SLOWMEM_FORCE_LPU_S 11 - -/* RTC_CNTL_RTC_SLOWMEM_FORCE_LPD : R/W; bitpos: [10]; default: 0; - * RTC memory force PD - */ - -#define RTC_CNTL_RTC_SLOWMEM_FORCE_LPD (BIT(10)) -#define RTC_CNTL_RTC_SLOWMEM_FORCE_LPD_M (RTC_CNTL_RTC_SLOWMEM_FORCE_LPD_V << RTC_CNTL_RTC_SLOWMEM_FORCE_LPD_S) -#define RTC_CNTL_RTC_SLOWMEM_FORCE_LPD_V 0x00000001 -#define RTC_CNTL_RTC_SLOWMEM_FORCE_LPD_S 10 - -/* RTC_CNTL_RTC_SLOWMEM_FOLW_CPU : R/W; bitpos: [9]; default: 0; - * 1: RTC memory PD following CPU, 0: RTC memory PD following RTC state - * machine - */ - -#define RTC_CNTL_RTC_SLOWMEM_FOLW_CPU (BIT(9)) -#define RTC_CNTL_RTC_SLOWMEM_FOLW_CPU_M (RTC_CNTL_RTC_SLOWMEM_FOLW_CPU_V << RTC_CNTL_RTC_SLOWMEM_FOLW_CPU_S) -#define RTC_CNTL_RTC_SLOWMEM_FOLW_CPU_V 0x00000001 -#define RTC_CNTL_RTC_SLOWMEM_FOLW_CPU_S 9 - -/* RTC_CNTL_RTC_FASTMEM_FORCE_LPU : R/W; bitpos: [8]; default: 1; - * Fast RTC memory force no PD - */ - -#define RTC_CNTL_RTC_FASTMEM_FORCE_LPU (BIT(8)) -#define RTC_CNTL_RTC_FASTMEM_FORCE_LPU_M (RTC_CNTL_RTC_FASTMEM_FORCE_LPU_V << RTC_CNTL_RTC_FASTMEM_FORCE_LPU_S) -#define RTC_CNTL_RTC_FASTMEM_FORCE_LPU_V 0x00000001 -#define RTC_CNTL_RTC_FASTMEM_FORCE_LPU_S 8 - -/* RTC_CNTL_RTC_FASTMEM_FORCE_LPD : R/W; bitpos: [7]; default: 0; - * Fast RTC memory force PD - */ - -#define RTC_CNTL_RTC_FASTMEM_FORCE_LPD (BIT(7)) -#define RTC_CNTL_RTC_FASTMEM_FORCE_LPD_M (RTC_CNTL_RTC_FASTMEM_FORCE_LPD_V << RTC_CNTL_RTC_FASTMEM_FORCE_LPD_S) -#define RTC_CNTL_RTC_FASTMEM_FORCE_LPD_V 0x00000001 -#define RTC_CNTL_RTC_FASTMEM_FORCE_LPD_S 7 - -/* RTC_CNTL_RTC_FASTMEM_FOLW_CPU : R/W; bitpos: [6]; default: 0; - * 1: Fast RTC memory PD following CPU, 0: fast RTC memory PD following RTC - * state machine - */ - -#define RTC_CNTL_RTC_FASTMEM_FOLW_CPU (BIT(6)) -#define RTC_CNTL_RTC_FASTMEM_FOLW_CPU_M (RTC_CNTL_RTC_FASTMEM_FOLW_CPU_V << RTC_CNTL_RTC_FASTMEM_FOLW_CPU_S) -#define RTC_CNTL_RTC_FASTMEM_FOLW_CPU_V 0x00000001 -#define RTC_CNTL_RTC_FASTMEM_FOLW_CPU_S 6 - -/* RTC_CNTL_RTC_FORCE_NOISO : R/W; bitpos: [5]; default: 1; - * rtc_peri force no ISO - */ - -#define RTC_CNTL_RTC_FORCE_NOISO (BIT(5)) -#define RTC_CNTL_RTC_FORCE_NOISO_M (RTC_CNTL_RTC_FORCE_NOISO_V << RTC_CNTL_RTC_FORCE_NOISO_S) -#define RTC_CNTL_RTC_FORCE_NOISO_V 0x00000001 -#define RTC_CNTL_RTC_FORCE_NOISO_S 5 - -/* RTC_CNTL_RTC_FORCE_ISO : R/W; bitpos: [4]; default: 0; - * rtc_peri force ISO - */ - -#define RTC_CNTL_RTC_FORCE_ISO (BIT(4)) -#define RTC_CNTL_RTC_FORCE_ISO_M (RTC_CNTL_RTC_FORCE_ISO_V << RTC_CNTL_RTC_FORCE_ISO_S) -#define RTC_CNTL_RTC_FORCE_ISO_V 0x00000001 -#define RTC_CNTL_RTC_FORCE_ISO_S 4 - -/* RTC_CNTL_RTC_SLOWMEM_FORCE_ISO : R/W; bitpos: [3]; default: 0; - * RTC memory force ISO - */ - -#define RTC_CNTL_RTC_SLOWMEM_FORCE_ISO (BIT(3)) -#define RTC_CNTL_RTC_SLOWMEM_FORCE_ISO_M (RTC_CNTL_RTC_SLOWMEM_FORCE_ISO_V << RTC_CNTL_RTC_SLOWMEM_FORCE_ISO_S) -#define RTC_CNTL_RTC_SLOWMEM_FORCE_ISO_V 0x00000001 -#define RTC_CNTL_RTC_SLOWMEM_FORCE_ISO_S 3 - -/* RTC_CNTL_RTC_SLOWMEM_FORCE_NOISO : R/W; bitpos: [2]; default: 1; - * RTC memory force no ISO - */ - -#define RTC_CNTL_RTC_SLOWMEM_FORCE_NOISO (BIT(2)) -#define RTC_CNTL_RTC_SLOWMEM_FORCE_NOISO_M (RTC_CNTL_RTC_SLOWMEM_FORCE_NOISO_V << RTC_CNTL_RTC_SLOWMEM_FORCE_NOISO_S) -#define RTC_CNTL_RTC_SLOWMEM_FORCE_NOISO_V 0x00000001 -#define RTC_CNTL_RTC_SLOWMEM_FORCE_NOISO_S 2 - -/* RTC_CNTL_RTC_FASTMEM_FORCE_ISO : R/W; bitpos: [1]; default: 0; - * Fast RTC memory force ISO - */ - -#define RTC_CNTL_RTC_FASTMEM_FORCE_ISO (BIT(1)) -#define RTC_CNTL_RTC_FASTMEM_FORCE_ISO_M (RTC_CNTL_RTC_FASTMEM_FORCE_ISO_V << RTC_CNTL_RTC_FASTMEM_FORCE_ISO_S) -#define RTC_CNTL_RTC_FASTMEM_FORCE_ISO_V 0x00000001 -#define RTC_CNTL_RTC_FASTMEM_FORCE_ISO_S 1 - -/* RTC_CNTL_RTC_FASTMEM_FORCE_NOISO : R/W; bitpos: [0]; default: 1; - * Fast RTC memory force no ISO - */ - -#define RTC_CNTL_RTC_FASTMEM_FORCE_NOISO (BIT(0)) -#define RTC_CNTL_RTC_FASTMEM_FORCE_NOISO_M (RTC_CNTL_RTC_FASTMEM_FORCE_NOISO_V << RTC_CNTL_RTC_FASTMEM_FORCE_NOISO_S) -#define RTC_CNTL_RTC_FASTMEM_FORCE_NOISO_V 0x00000001 -#define RTC_CNTL_RTC_FASTMEM_FORCE_NOISO_S 0 - -/* RTC_CNTL_RTC_REGULATOR_DRV_CTRL_REG register - * No public - */ - -#define RTC_CNTL_RTC_REGULATOR_DRV_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x8c) - -/* RTC_CNTL_DG_VDD_DRV_B_MONITOR : R/W; bitpos: [27:20]; default: 0; - * No public - */ - -#define RTC_CNTL_DG_VDD_DRV_B_MONITOR 0x000000ff -#define RTC_CNTL_DG_VDD_DRV_B_MONITOR_M (RTC_CNTL_DG_VDD_DRV_B_MONITOR_V << RTC_CNTL_DG_VDD_DRV_B_MONITOR_S) -#define RTC_CNTL_DG_VDD_DRV_B_MONITOR_V 0x000000ff -#define RTC_CNTL_DG_VDD_DRV_B_MONITOR_S 20 - -/* RTC_CNTL_DG_VDD_DRV_B_SLP : R/W; bitpos: [19:12]; default: 0; - * No public - */ - -#define RTC_CNTL_DG_VDD_DRV_B_SLP 0x000000ff -#define RTC_CNTL_DG_VDD_DRV_B_SLP_M (RTC_CNTL_DG_VDD_DRV_B_SLP_V << RTC_CNTL_DG_VDD_DRV_B_SLP_S) -#define RTC_CNTL_DG_VDD_DRV_B_SLP_V 0x000000ff -#define RTC_CNTL_DG_VDD_DRV_B_SLP_S 12 - -/* RTC_CNTL_RTC_REGULATOR_DRV_B_SLP : R/W; bitpos: [11:6]; default: 0; - * No public - */ - -#define RTC_CNTL_RTC_REGULATOR_DRV_B_SLP 0x0000003f -#define RTC_CNTL_RTC_REGULATOR_DRV_B_SLP_M (RTC_CNTL_RTC_REGULATOR_DRV_B_SLP_V << RTC_CNTL_RTC_REGULATOR_DRV_B_SLP_S) -#define RTC_CNTL_RTC_REGULATOR_DRV_B_SLP_V 0x0000003f -#define RTC_CNTL_RTC_REGULATOR_DRV_B_SLP_S 6 - -/* RTC_CNTL_RTC_REGULATOR_DRV_B_MONITOR : R/W; bitpos: [5:0]; default: 0; - * No public - */ - -#define RTC_CNTL_RTC_REGULATOR_DRV_B_MONITOR 0x0000003f -#define RTC_CNTL_RTC_REGULATOR_DRV_B_MONITOR_M (RTC_CNTL_RTC_REGULATOR_DRV_B_MONITOR_V << RTC_CNTL_RTC_REGULATOR_DRV_B_MONITOR_S) -#define RTC_CNTL_RTC_REGULATOR_DRV_B_MONITOR_V 0x0000003f -#define RTC_CNTL_RTC_REGULATOR_DRV_B_MONITOR_S 0 - -/* RTC_CNTL_DIG_PWC_REG register - * configure digital power - */ - -#define RTC_CNTL_DIG_PWC_REG (DR_REG_RTCCNTL_BASE + 0x90) - -/* RTC_CNTL_DG_WRAP_PD_EN : R/W; bitpos: [31]; default: 0; - * enable power down all digital logic - */ - -#define RTC_CNTL_DG_WRAP_PD_EN (BIT(31)) -#define RTC_CNTL_DG_WRAP_PD_EN_M (RTC_CNTL_DG_WRAP_PD_EN_V << RTC_CNTL_DG_WRAP_PD_EN_S) -#define RTC_CNTL_DG_WRAP_PD_EN_V 0x00000001 -#define RTC_CNTL_DG_WRAP_PD_EN_S 31 - -/* RTC_CNTL_WIFI_PD_EN : R/W; bitpos: [30]; default: 0; - * enable power down wifi in sleep - */ - -#define RTC_CNTL_WIFI_PD_EN (BIT(30)) -#define RTC_CNTL_WIFI_PD_EN_M (RTC_CNTL_WIFI_PD_EN_V << RTC_CNTL_WIFI_PD_EN_S) -#define RTC_CNTL_WIFI_PD_EN_V 0x00000001 -#define RTC_CNTL_WIFI_PD_EN_S 30 - -/* RTC_CNTL_CPU_TOP_PD_EN : R/W; bitpos: [29]; default: 0; - * enable power down internal SRAM 4 in sleep - */ - -#define RTC_CNTL_CPU_TOP_PD_EN (BIT(29)) -#define RTC_CNTL_CPU_TOP_PD_EN_M (RTC_CNTL_CPU_TOP_PD_EN_V << RTC_CNTL_CPU_TOP_PD_EN_S) -#define RTC_CNTL_CPU_TOP_PD_EN_V 0x00000001 -#define RTC_CNTL_CPU_TOP_PD_EN_S 29 - -/* RTC_CNTL_DG_PERI_PD_EN : R/W; bitpos: [28]; default: 0; - * enable power down internal SRAM 3 in sleep - */ - -#define RTC_CNTL_DG_PERI_PD_EN (BIT(28)) -#define RTC_CNTL_DG_PERI_PD_EN_M (RTC_CNTL_DG_PERI_PD_EN_V << RTC_CNTL_DG_PERI_PD_EN_S) -#define RTC_CNTL_DG_PERI_PD_EN_V 0x00000001 -#define RTC_CNTL_DG_PERI_PD_EN_S 28 - -/* RTC_CNTL_BT_PD_EN : R/W; bitpos: [27]; default: 0; - * enable power down internal SRAM 2 in sleep - */ - -#define RTC_CNTL_BT_PD_EN (BIT(27)) -#define RTC_CNTL_BT_PD_EN_M (RTC_CNTL_BT_PD_EN_V << RTC_CNTL_BT_PD_EN_S) -#define RTC_CNTL_BT_PD_EN_V 0x00000001 -#define RTC_CNTL_BT_PD_EN_S 27 - -/* RTC_CNTL_CPU_TOP_FORCE_PU : R/W; bitpos: [22]; default: 1; - * digital dcdc force power up - */ - -#define RTC_CNTL_CPU_TOP_FORCE_PU (BIT(22)) -#define RTC_CNTL_CPU_TOP_FORCE_PU_M (RTC_CNTL_CPU_TOP_FORCE_PU_V << RTC_CNTL_CPU_TOP_FORCE_PU_S) -#define RTC_CNTL_CPU_TOP_FORCE_PU_V 0x00000001 -#define RTC_CNTL_CPU_TOP_FORCE_PU_S 22 - -/* RTC_CNTL_CPU_TOP_FORCE_PD : R/W; bitpos: [21]; default: 0; - * digital dcdc force power down - */ - -#define RTC_CNTL_CPU_TOP_FORCE_PD (BIT(21)) -#define RTC_CNTL_CPU_TOP_FORCE_PD_M (RTC_CNTL_CPU_TOP_FORCE_PD_V << RTC_CNTL_CPU_TOP_FORCE_PD_S) -#define RTC_CNTL_CPU_TOP_FORCE_PD_V 0x00000001 -#define RTC_CNTL_CPU_TOP_FORCE_PD_S 21 - -/* RTC_CNTL_DG_WRAP_FORCE_PU : R/W; bitpos: [20]; default: 1; - * digital core force power up - */ - -#define RTC_CNTL_DG_WRAP_FORCE_PU (BIT(20)) -#define RTC_CNTL_DG_WRAP_FORCE_PU_M (RTC_CNTL_DG_WRAP_FORCE_PU_V << RTC_CNTL_DG_WRAP_FORCE_PU_S) -#define RTC_CNTL_DG_WRAP_FORCE_PU_V 0x00000001 -#define RTC_CNTL_DG_WRAP_FORCE_PU_S 20 - -/* RTC_CNTL_DG_WRAP_FORCE_PD : R/W; bitpos: [19]; default: 0; - * digital core force power down - */ - -#define RTC_CNTL_DG_WRAP_FORCE_PD (BIT(19)) -#define RTC_CNTL_DG_WRAP_FORCE_PD_M (RTC_CNTL_DG_WRAP_FORCE_PD_V << RTC_CNTL_DG_WRAP_FORCE_PD_S) -#define RTC_CNTL_DG_WRAP_FORCE_PD_V 0x00000001 -#define RTC_CNTL_DG_WRAP_FORCE_PD_S 19 - -/* RTC_CNTL_WIFI_FORCE_PU : R/W; bitpos: [18]; default: 1; - * wifi force power up - */ - -#define RTC_CNTL_WIFI_FORCE_PU (BIT(18)) -#define RTC_CNTL_WIFI_FORCE_PU_M (RTC_CNTL_WIFI_FORCE_PU_V << RTC_CNTL_WIFI_FORCE_PU_S) -#define RTC_CNTL_WIFI_FORCE_PU_V 0x00000001 -#define RTC_CNTL_WIFI_FORCE_PU_S 18 - -/* RTC_CNTL_WIFI_FORCE_PD : R/W; bitpos: [17]; default: 0; - * wifi force power down - */ - -#define RTC_CNTL_WIFI_FORCE_PD (BIT(17)) -#define RTC_CNTL_WIFI_FORCE_PD_M (RTC_CNTL_WIFI_FORCE_PD_V << RTC_CNTL_WIFI_FORCE_PD_S) -#define RTC_CNTL_WIFI_FORCE_PD_V 0x00000001 -#define RTC_CNTL_WIFI_FORCE_PD_S 17 - -/* RTC_CNTL_DG_PERI_FORCE_PU : R/W; bitpos: [14]; default: 1; - * internal SRAM 3 force power up - */ - -#define RTC_CNTL_DG_PERI_FORCE_PU (BIT(14)) -#define RTC_CNTL_DG_PERI_FORCE_PU_M (RTC_CNTL_DG_PERI_FORCE_PU_V << RTC_CNTL_DG_PERI_FORCE_PU_S) -#define RTC_CNTL_DG_PERI_FORCE_PU_V 0x00000001 -#define RTC_CNTL_DG_PERI_FORCE_PU_S 14 - -/* RTC_CNTL_DG_PERI_FORCE_PD : R/W; bitpos: [13]; default: 0; - * internal SRAM 3 force power down - */ - -#define RTC_CNTL_DG_PERI_FORCE_PD (BIT(13)) -#define RTC_CNTL_DG_PERI_FORCE_PD_M (RTC_CNTL_DG_PERI_FORCE_PD_V << RTC_CNTL_DG_PERI_FORCE_PD_S) -#define RTC_CNTL_DG_PERI_FORCE_PD_V 0x00000001 -#define RTC_CNTL_DG_PERI_FORCE_PD_S 13 - -/* RTC_CNTL_BT_FORCE_PU : R/W; bitpos: [12]; default: 1; - * internal SRAM 2 force power up - */ - -#define RTC_CNTL_BT_FORCE_PU (BIT(12)) -#define RTC_CNTL_BT_FORCE_PU_M (RTC_CNTL_BT_FORCE_PU_V << RTC_CNTL_BT_FORCE_PU_S) -#define RTC_CNTL_BT_FORCE_PU_V 0x00000001 -#define RTC_CNTL_BT_FORCE_PU_S 12 - -/* RTC_CNTL_BT_FORCE_PD : R/W; bitpos: [11]; default: 0; - * internal SRAM 2 force power down - */ - -#define RTC_CNTL_BT_FORCE_PD (BIT(11)) -#define RTC_CNTL_BT_FORCE_PD_M (RTC_CNTL_BT_FORCE_PD_V << RTC_CNTL_BT_FORCE_PD_S) -#define RTC_CNTL_BT_FORCE_PD_V 0x00000001 -#define RTC_CNTL_BT_FORCE_PD_S 11 - -/* RTC_CNTL_LSLP_MEM_FORCE_PU : R/W; bitpos: [4]; default: 1; - * memories in digital core force no PD in sleep - */ - -#define RTC_CNTL_LSLP_MEM_FORCE_PU (BIT(4)) -#define RTC_CNTL_LSLP_MEM_FORCE_PU_M (RTC_CNTL_LSLP_MEM_FORCE_PU_V << RTC_CNTL_LSLP_MEM_FORCE_PU_S) -#define RTC_CNTL_LSLP_MEM_FORCE_PU_V 0x00000001 -#define RTC_CNTL_LSLP_MEM_FORCE_PU_S 4 - -/* RTC_CNTL_LSLP_MEM_FORCE_PD : R/W; bitpos: [3]; default: 0; - * memories in digital core force PD in sleep - */ - -#define RTC_CNTL_LSLP_MEM_FORCE_PD (BIT(3)) -#define RTC_CNTL_LSLP_MEM_FORCE_PD_M (RTC_CNTL_LSLP_MEM_FORCE_PD_V << RTC_CNTL_LSLP_MEM_FORCE_PD_S) -#define RTC_CNTL_LSLP_MEM_FORCE_PD_V 0x00000001 -#define RTC_CNTL_LSLP_MEM_FORCE_PD_S 3 - -/* RTC_CNTL_DIG_ISO_REG register - * configure digital power isolation - */ - -#define RTC_CNTL_DIG_ISO_REG (DR_REG_RTCCNTL_BASE + 0x94) - -/* RTC_CNTL_DG_WRAP_FORCE_NOISO : R/W; bitpos: [31]; default: 1; - * digita core force no ISO - */ - -#define RTC_CNTL_DG_WRAP_FORCE_NOISO (BIT(31)) -#define RTC_CNTL_DG_WRAP_FORCE_NOISO_M (RTC_CNTL_DG_WRAP_FORCE_NOISO_V << RTC_CNTL_DG_WRAP_FORCE_NOISO_S) -#define RTC_CNTL_DG_WRAP_FORCE_NOISO_V 0x00000001 -#define RTC_CNTL_DG_WRAP_FORCE_NOISO_S 31 - -/* RTC_CNTL_DG_WRAP_FORCE_ISO : R/W; bitpos: [30]; default: 0; - * digital core force ISO - */ - -#define RTC_CNTL_DG_WRAP_FORCE_ISO (BIT(30)) -#define RTC_CNTL_DG_WRAP_FORCE_ISO_M (RTC_CNTL_DG_WRAP_FORCE_ISO_V << RTC_CNTL_DG_WRAP_FORCE_ISO_S) -#define RTC_CNTL_DG_WRAP_FORCE_ISO_V 0x00000001 -#define RTC_CNTL_DG_WRAP_FORCE_ISO_S 30 - -/* RTC_CNTL_WIFI_FORCE_NOISO : R/W; bitpos: [29]; default: 1; - * wifi force no ISO - */ - -#define RTC_CNTL_WIFI_FORCE_NOISO (BIT(29)) -#define RTC_CNTL_WIFI_FORCE_NOISO_M (RTC_CNTL_WIFI_FORCE_NOISO_V << RTC_CNTL_WIFI_FORCE_NOISO_S) -#define RTC_CNTL_WIFI_FORCE_NOISO_V 0x00000001 -#define RTC_CNTL_WIFI_FORCE_NOISO_S 29 - -/* RTC_CNTL_WIFI_FORCE_ISO : R/W; bitpos: [28]; default: 0; - * wifi force ISO - */ - -#define RTC_CNTL_WIFI_FORCE_ISO (BIT(28)) -#define RTC_CNTL_WIFI_FORCE_ISO_M (RTC_CNTL_WIFI_FORCE_ISO_V << RTC_CNTL_WIFI_FORCE_ISO_S) -#define RTC_CNTL_WIFI_FORCE_ISO_V 0x00000001 -#define RTC_CNTL_WIFI_FORCE_ISO_S 28 - -/* RTC_CNTL_CPU_TOP_FORCE_NOISO : R/W; bitpos: [27]; default: 1; - * internal SRAM 4 force no ISO - */ - -#define RTC_CNTL_CPU_TOP_FORCE_NOISO (BIT(27)) -#define RTC_CNTL_CPU_TOP_FORCE_NOISO_M (RTC_CNTL_CPU_TOP_FORCE_NOISO_V << RTC_CNTL_CPU_TOP_FORCE_NOISO_S) -#define RTC_CNTL_CPU_TOP_FORCE_NOISO_V 0x00000001 -#define RTC_CNTL_CPU_TOP_FORCE_NOISO_S 27 - -/* RTC_CNTL_CPU_TOP_FORCE_ISO : R/W; bitpos: [26]; default: 0; - * internal SRAM 4 force ISO - */ - -#define RTC_CNTL_CPU_TOP_FORCE_ISO (BIT(26)) -#define RTC_CNTL_CPU_TOP_FORCE_ISO_M (RTC_CNTL_CPU_TOP_FORCE_ISO_V << RTC_CNTL_CPU_TOP_FORCE_ISO_S) -#define RTC_CNTL_CPU_TOP_FORCE_ISO_V 0x00000001 -#define RTC_CNTL_CPU_TOP_FORCE_ISO_S 26 - -/* RTC_CNTL_DG_PERI_FORCE_NOISO : R/W; bitpos: [25]; default: 1; - * internal SRAM 3 force no ISO - */ - -#define RTC_CNTL_DG_PERI_FORCE_NOISO (BIT(25)) -#define RTC_CNTL_DG_PERI_FORCE_NOISO_M (RTC_CNTL_DG_PERI_FORCE_NOISO_V << RTC_CNTL_DG_PERI_FORCE_NOISO_S) -#define RTC_CNTL_DG_PERI_FORCE_NOISO_V 0x00000001 -#define RTC_CNTL_DG_PERI_FORCE_NOISO_S 25 - -/* RTC_CNTL_DG_PERI_FORCE_ISO : R/W; bitpos: [24]; default: 0; - * internal SRAM 3 force ISO - */ - -#define RTC_CNTL_DG_PERI_FORCE_ISO (BIT(24)) -#define RTC_CNTL_DG_PERI_FORCE_ISO_M (RTC_CNTL_DG_PERI_FORCE_ISO_V << RTC_CNTL_DG_PERI_FORCE_ISO_S) -#define RTC_CNTL_DG_PERI_FORCE_ISO_V 0x00000001 -#define RTC_CNTL_DG_PERI_FORCE_ISO_S 24 - -/* RTC_CNTL_BT_FORCE_NOISO : R/W; bitpos: [23]; default: 1; - * internal SRAM 2 force no ISO - */ - -#define RTC_CNTL_BT_FORCE_NOISO (BIT(23)) -#define RTC_CNTL_BT_FORCE_NOISO_M (RTC_CNTL_BT_FORCE_NOISO_V << RTC_CNTL_BT_FORCE_NOISO_S) -#define RTC_CNTL_BT_FORCE_NOISO_V 0x00000001 -#define RTC_CNTL_BT_FORCE_NOISO_S 23 - -/* RTC_CNTL_BT_FORCE_ISO : R/W; bitpos: [22]; default: 0; - * internal SRAM 2 force ISO - */ - -#define RTC_CNTL_BT_FORCE_ISO (BIT(22)) -#define RTC_CNTL_BT_FORCE_ISO_M (RTC_CNTL_BT_FORCE_ISO_V << RTC_CNTL_BT_FORCE_ISO_S) -#define RTC_CNTL_BT_FORCE_ISO_V 0x00000001 -#define RTC_CNTL_BT_FORCE_ISO_S 22 - -/* RTC_CNTL_DG_PAD_FORCE_HOLD : R/W; bitpos: [15]; default: 0; - * digital pad force hold - */ - -#define RTC_CNTL_DG_PAD_FORCE_HOLD (BIT(15)) -#define RTC_CNTL_DG_PAD_FORCE_HOLD_M (RTC_CNTL_DG_PAD_FORCE_HOLD_V << RTC_CNTL_DG_PAD_FORCE_HOLD_S) -#define RTC_CNTL_DG_PAD_FORCE_HOLD_V 0x00000001 -#define RTC_CNTL_DG_PAD_FORCE_HOLD_S 15 - -/* RTC_CNTL_DG_PAD_FORCE_UNHOLD : R/W; bitpos: [14]; default: 1; - * digital pad force un-hold - */ - -#define RTC_CNTL_DG_PAD_FORCE_UNHOLD (BIT(14)) -#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_M (RTC_CNTL_DG_PAD_FORCE_UNHOLD_V << RTC_CNTL_DG_PAD_FORCE_UNHOLD_S) -#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_V 0x00000001 -#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_S 14 - -/* RTC_CNTL_DG_PAD_FORCE_ISO : R/W; bitpos: [13]; default: 0; - * digital pad force ISO - */ - -#define RTC_CNTL_DG_PAD_FORCE_ISO (BIT(13)) -#define RTC_CNTL_DG_PAD_FORCE_ISO_M (RTC_CNTL_DG_PAD_FORCE_ISO_V << RTC_CNTL_DG_PAD_FORCE_ISO_S) -#define RTC_CNTL_DG_PAD_FORCE_ISO_V 0x00000001 -#define RTC_CNTL_DG_PAD_FORCE_ISO_S 13 - -/* RTC_CNTL_DG_PAD_FORCE_NOISO : R/W; bitpos: [12]; default: 1; - * digital pad force no ISO - */ - -#define RTC_CNTL_DG_PAD_FORCE_NOISO (BIT(12)) -#define RTC_CNTL_DG_PAD_FORCE_NOISO_M (RTC_CNTL_DG_PAD_FORCE_NOISO_V << RTC_CNTL_DG_PAD_FORCE_NOISO_S) -#define RTC_CNTL_DG_PAD_FORCE_NOISO_V 0x00000001 -#define RTC_CNTL_DG_PAD_FORCE_NOISO_S 12 - -/* RTC_CNTL_DG_PAD_AUTOHOLD_EN : R/W; bitpos: [11]; default: 0; - * digital pad enable auto-hold - */ - -#define RTC_CNTL_DG_PAD_AUTOHOLD_EN (BIT(11)) -#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_M (RTC_CNTL_DG_PAD_AUTOHOLD_EN_V << RTC_CNTL_DG_PAD_AUTOHOLD_EN_S) -#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_V 0x00000001 -#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_S 11 - -/* RTC_CNTL_CLR_DG_PAD_AUTOHOLD : WO; bitpos: [10]; default: 0; - * wtite only register to clear digital pad auto-hold - */ - -#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD (BIT(10)) -#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_M (RTC_CNTL_CLR_DG_PAD_AUTOHOLD_V << RTC_CNTL_CLR_DG_PAD_AUTOHOLD_S) -#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_V 0x00000001 -#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_S 10 - -/* RTC_CNTL_DG_PAD_AUTOHOLD : RO; bitpos: [9]; default: 0; - * read only register to indicate digital pad auto-hold status - */ - -#define RTC_CNTL_DG_PAD_AUTOHOLD (BIT(9)) -#define RTC_CNTL_DG_PAD_AUTOHOLD_M (RTC_CNTL_DG_PAD_AUTOHOLD_V << RTC_CNTL_DG_PAD_AUTOHOLD_S) -#define RTC_CNTL_DG_PAD_AUTOHOLD_V 0x00000001 -#define RTC_CNTL_DG_PAD_AUTOHOLD_S 9 - -/* RTC_CNTL_DIG_ISO_FORCE_ON : R/W; bitpos: [8]; default: 0; - * No public - */ - -#define RTC_CNTL_DIG_ISO_FORCE_ON (BIT(8)) -#define RTC_CNTL_DIG_ISO_FORCE_ON_M (RTC_CNTL_DIG_ISO_FORCE_ON_V << RTC_CNTL_DIG_ISO_FORCE_ON_S) -#define RTC_CNTL_DIG_ISO_FORCE_ON_V 0x00000001 -#define RTC_CNTL_DIG_ISO_FORCE_ON_S 8 - -/* RTC_CNTL_DIG_ISO_FORCE_OFF : R/W; bitpos: [7]; default: 1; - * No public - */ - -#define RTC_CNTL_DIG_ISO_FORCE_OFF (BIT(7)) -#define RTC_CNTL_DIG_ISO_FORCE_OFF_M (RTC_CNTL_DIG_ISO_FORCE_OFF_V << RTC_CNTL_DIG_ISO_FORCE_OFF_S) -#define RTC_CNTL_DIG_ISO_FORCE_OFF_V 0x00000001 -#define RTC_CNTL_DIG_ISO_FORCE_OFF_S 7 - -/* RTC_CNTL_RTC_WDTCONFIG0_REG register - * configure rtc watch dog - */ - -#define RTC_CNTL_RTC_WDTCONFIG0_REG (DR_REG_RTCCNTL_BASE + 0x98) - -/* RTC_CNTL_WDT_EN : R/W; bitpos: [31]; default: 0; - * enable rtc watch dog - */ - -#define RTC_CNTL_WDT_EN (BIT(31)) -#define RTC_CNTL_WDT_EN_M (RTC_CNTL_WDT_EN_V << RTC_CNTL_WDT_EN_S) -#define RTC_CNTL_WDT_EN_V 0x00000001 -#define RTC_CNTL_WDT_EN_S 31 - -/* RTC_CNTL_WDT_STG0 : R/W; bitpos: [30:28]; default: 0; - * 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: - * RTC reset stage en - */ - -#define RTC_CNTL_WDT_STG0 0x00000007 -#define RTC_CNTL_WDT_STG0_M (RTC_CNTL_WDT_STG0_V << RTC_CNTL_WDT_STG0_S) -#define RTC_CNTL_WDT_STG0_V 0x00000007 -#define RTC_CNTL_WDT_STG0_S 28 - -/* RTC_CNTL_WDT_STG1 : R/W; bitpos: [27:25]; default: 0; - * 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: - * RTC reset stage en - */ - -#define RTC_CNTL_WDT_STG1 0x00000007 -#define RTC_CNTL_WDT_STG1_M (RTC_CNTL_WDT_STG1_V << RTC_CNTL_WDT_STG1_S) -#define RTC_CNTL_WDT_STG1_V 0x00000007 -#define RTC_CNTL_WDT_STG1_S 25 - -/* RTC_CNTL_WDT_STG2 : R/W; bitpos: [24:22]; default: 0; - * 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: - * RTC reset stage en - */ - -#define RTC_CNTL_WDT_STG2 0x00000007 -#define RTC_CNTL_WDT_STG2_M (RTC_CNTL_WDT_STG2_V << RTC_CNTL_WDT_STG2_S) -#define RTC_CNTL_WDT_STG2_V 0x00000007 -#define RTC_CNTL_WDT_STG2_S 22 - -/* RTC_CNTL_WDT_STG3 : R/W; bitpos: [21:19]; default: 0; - * 1: interrupt stage en 2: CPU reset stage en 3: system reset stage en 4: - * RTC reset stage en - */ - -#define RTC_CNTL_WDT_STG3 0x00000007 -#define RTC_CNTL_WDT_STG3_M (RTC_CNTL_WDT_STG3_V << RTC_CNTL_WDT_STG3_S) -#define RTC_CNTL_WDT_STG3_V 0x00000007 -#define RTC_CNTL_WDT_STG3_S 19 - -/* RTC_CNTL_WDT_CPU_RESET_LENGTH : R/W; bitpos: [18:16]; default: 1; - * CPU reset counter length - */ - -#define RTC_CNTL_WDT_CPU_RESET_LENGTH 0x00000007 -#define RTC_CNTL_WDT_CPU_RESET_LENGTH_M (RTC_CNTL_WDT_CPU_RESET_LENGTH_V << RTC_CNTL_WDT_CPU_RESET_LENGTH_S) -#define RTC_CNTL_WDT_CPU_RESET_LENGTH_V 0x00000007 -#define RTC_CNTL_WDT_CPU_RESET_LENGTH_S 16 - -/* RTC_CNTL_WDT_SYS_RESET_LENGTH : R/W; bitpos: [15:13]; default: 1; - * system reset counter length - */ - -#define RTC_CNTL_WDT_SYS_RESET_LENGTH 0x00000007 -#define RTC_CNTL_WDT_SYS_RESET_LENGTH_M (RTC_CNTL_WDT_SYS_RESET_LENGTH_V << RTC_CNTL_WDT_SYS_RESET_LENGTH_S) -#define RTC_CNTL_WDT_SYS_RESET_LENGTH_V 0x00000007 -#define RTC_CNTL_WDT_SYS_RESET_LENGTH_S 13 - -/* RTC_CNTL_WDT_FLASHBOOT_MOD_EN : R/W; bitpos: [12]; default: 1; - * enable WDT in flash boot - */ - -#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN (BIT(12)) -#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_M (RTC_CNTL_WDT_FLASHBOOT_MOD_EN_V << RTC_CNTL_WDT_FLASHBOOT_MOD_EN_S) -#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_V 0x00000001 -#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_S 12 - -/* RTC_CNTL_WDT_PROCPU_RESET_EN : R/W; bitpos: [11]; default: 0; - * enable WDT reset PRO CPU - */ - -#define RTC_CNTL_WDT_PROCPU_RESET_EN (BIT(11)) -#define RTC_CNTL_WDT_PROCPU_RESET_EN_M (RTC_CNTL_WDT_PROCPU_RESET_EN_V << RTC_CNTL_WDT_PROCPU_RESET_EN_S) -#define RTC_CNTL_WDT_PROCPU_RESET_EN_V 0x00000001 -#define RTC_CNTL_WDT_PROCPU_RESET_EN_S 11 - -/* RTC_CNTL_WDT_APPCPU_RESET_EN : R/W; bitpos: [10]; default: 0; - * enable WDT reset APP CPU - */ - -#define RTC_CNTL_WDT_APPCPU_RESET_EN (BIT(10)) -#define RTC_CNTL_WDT_APPCPU_RESET_EN_M (RTC_CNTL_WDT_APPCPU_RESET_EN_V << RTC_CNTL_WDT_APPCPU_RESET_EN_S) -#define RTC_CNTL_WDT_APPCPU_RESET_EN_V 0x00000001 -#define RTC_CNTL_WDT_APPCPU_RESET_EN_S 10 - -/* RTC_CNTL_WDT_PAUSE_IN_SLP : R/W; bitpos: [9]; default: 1; - * pause WDT in sleep - */ - -#define RTC_CNTL_WDT_PAUSE_IN_SLP (BIT(9)) -#define RTC_CNTL_WDT_PAUSE_IN_SLP_M (RTC_CNTL_WDT_PAUSE_IN_SLP_V << RTC_CNTL_WDT_PAUSE_IN_SLP_S) -#define RTC_CNTL_WDT_PAUSE_IN_SLP_V 0x00000001 -#define RTC_CNTL_WDT_PAUSE_IN_SLP_S 9 - -/* RTC_CNTL_WDT_CHIP_RESET_EN : R/W; bitpos: [8]; default: 0; - * wdt reset whole chip enable - */ - -#define RTC_CNTL_WDT_CHIP_RESET_EN (BIT(8)) -#define RTC_CNTL_WDT_CHIP_RESET_EN_M (RTC_CNTL_WDT_CHIP_RESET_EN_V << RTC_CNTL_WDT_CHIP_RESET_EN_S) -#define RTC_CNTL_WDT_CHIP_RESET_EN_V 0x00000001 -#define RTC_CNTL_WDT_CHIP_RESET_EN_S 8 - -/* RTC_CNTL_WDT_CHIP_RESET_WIDTH : R/W; bitpos: [7:0]; default: 20; - * chip reset siginal pulse width - */ - -#define RTC_CNTL_WDT_CHIP_RESET_WIDTH 0x000000ff -#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_M (RTC_CNTL_WDT_CHIP_RESET_WIDTH_V << RTC_CNTL_WDT_CHIP_RESET_WIDTH_S) -#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_V 0x000000ff -#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_S 0 - -/* RTC_CNTL_RTC_WDTCONFIG1_REG register - * stage0 hold time - */ - -#define RTC_CNTL_RTC_WDTCONFIG1_REG (DR_REG_RTCCNTL_BASE + 0x9c) - -/* RTC_CNTL_WDT_STG0_HOLD : R/W; bitpos: [31:0]; default: 200000; - * stage0 hold time - */ - -#define RTC_CNTL_WDT_STG0_HOLD 0xffffffff -#define RTC_CNTL_WDT_STG0_HOLD_M (RTC_CNTL_WDT_STG0_HOLD_V << RTC_CNTL_WDT_STG0_HOLD_S) -#define RTC_CNTL_WDT_STG0_HOLD_V 0xffffffff -#define RTC_CNTL_WDT_STG0_HOLD_S 0 - -/* RTC_CNTL_RTC_WDTCONFIG2_REG register - * stage1 hold time - */ - -#define RTC_CNTL_RTC_WDTCONFIG2_REG (DR_REG_RTCCNTL_BASE + 0xa0) - -/* RTC_CNTL_WDT_STG1_HOLD : R/W; bitpos: [31:0]; default: 80000; - * stage1 hold time - */ - -#define RTC_CNTL_WDT_STG1_HOLD 0xffffffff -#define RTC_CNTL_WDT_STG1_HOLD_M (RTC_CNTL_WDT_STG1_HOLD_V << RTC_CNTL_WDT_STG1_HOLD_S) -#define RTC_CNTL_WDT_STG1_HOLD_V 0xffffffff -#define RTC_CNTL_WDT_STG1_HOLD_S 0 - -/* RTC_CNTL_RTC_WDTCONFIG3_REG register - * stage2 hold time - */ - -#define RTC_CNTL_RTC_WDTCONFIG3_REG (DR_REG_RTCCNTL_BASE + 0xa4) - -/* RTC_CNTL_WDT_STG2_HOLD : R/W; bitpos: [31:0]; default: 4095; - * stage2 hold time - */ - -#define RTC_CNTL_WDT_STG2_HOLD 0xffffffff -#define RTC_CNTL_WDT_STG2_HOLD_M (RTC_CNTL_WDT_STG2_HOLD_V << RTC_CNTL_WDT_STG2_HOLD_S) -#define RTC_CNTL_WDT_STG2_HOLD_V 0xffffffff -#define RTC_CNTL_WDT_STG2_HOLD_S 0 - -/* RTC_CNTL_RTC_WDTCONFIG4_REG register - * stage3 hold time - */ - -#define RTC_CNTL_RTC_WDTCONFIG4_REG (DR_REG_RTCCNTL_BASE + 0xa8) - -/* RTC_CNTL_WDT_STG3_HOLD : R/W; bitpos: [31:0]; default: 4095; - * stage3 hold time - */ - -#define RTC_CNTL_WDT_STG3_HOLD 0xffffffff -#define RTC_CNTL_WDT_STG3_HOLD_M (RTC_CNTL_WDT_STG3_HOLD_V << RTC_CNTL_WDT_STG3_HOLD_S) -#define RTC_CNTL_WDT_STG3_HOLD_V 0xffffffff -#define RTC_CNTL_WDT_STG3_HOLD_S 0 - -/* RTC_CNTL_RTC_WDTFEED_REG register - * rtc wdt feed - */ - -#define RTC_CNTL_RTC_WDTFEED_REG (DR_REG_RTCCNTL_BASE + 0xac) - -/* RTC_CNTL_RTC_WDT_FEED : WO; bitpos: [31]; default: 0; - * rtc wdt feed - */ - -#define RTC_CNTL_RTC_WDT_FEED (BIT(31)) -#define RTC_CNTL_RTC_WDT_FEED_M (RTC_CNTL_RTC_WDT_FEED_V << RTC_CNTL_RTC_WDT_FEED_S) -#define RTC_CNTL_RTC_WDT_FEED_V 0x00000001 -#define RTC_CNTL_RTC_WDT_FEED_S 31 - -/* RTC_CNTL_RTC_WDTWPROTECT_REG register - * configure rtc watch dog - */ - -#define RTC_CNTL_RTC_WDTWPROTECT_REG (DR_REG_RTCCNTL_BASE + 0xb0) - -/* RTC_CNTL_WDT_WKEY : R/W; bitpos: [31:0]; default: 1356348065; - * rtc watch dog key - */ - -#define RTC_CNTL_WDT_WKEY 0xffffffff -#define RTC_CNTL_WDT_WKEY_M (RTC_CNTL_WDT_WKEY_V << RTC_CNTL_WDT_WKEY_S) -#define RTC_CNTL_WDT_WKEY_V 0xffffffff -#define RTC_CNTL_WDT_WKEY_S 0 - -/* RTC_CNTL_RTC_SWD_CONF_REG register - * configure super watch dog - */ - -#define RTC_CNTL_RTC_SWD_CONF_REG (DR_REG_RTCCNTL_BASE + 0xb4) - -/* RTC_CNTL_SWD_AUTO_FEED_EN : R/W; bitpos: [31]; default: 0; - * automatically feed swd when int comes - */ - -#define RTC_CNTL_SWD_AUTO_FEED_EN (BIT(31)) -#define RTC_CNTL_SWD_AUTO_FEED_EN_M (RTC_CNTL_SWD_AUTO_FEED_EN_V << RTC_CNTL_SWD_AUTO_FEED_EN_S) -#define RTC_CNTL_SWD_AUTO_FEED_EN_V 0x00000001 -#define RTC_CNTL_SWD_AUTO_FEED_EN_S 31 - -/* RTC_CNTL_SWD_DISABLE : R/W; bitpos: [30]; default: 0; - * disable SWD - */ - -#define RTC_CNTL_SWD_DISABLE (BIT(30)) -#define RTC_CNTL_SWD_DISABLE_M (RTC_CNTL_SWD_DISABLE_V << RTC_CNTL_SWD_DISABLE_S) -#define RTC_CNTL_SWD_DISABLE_V 0x00000001 -#define RTC_CNTL_SWD_DISABLE_S 30 - -/* RTC_CNTL_SWD_FEED : WO; bitpos: [29]; default: 0; - * Sw feed swd - */ - -#define RTC_CNTL_SWD_FEED (BIT(29)) -#define RTC_CNTL_SWD_FEED_M (RTC_CNTL_SWD_FEED_V << RTC_CNTL_SWD_FEED_S) -#define RTC_CNTL_SWD_FEED_V 0x00000001 -#define RTC_CNTL_SWD_FEED_S 29 - -/* RTC_CNTL_SWD_RST_FLAG_CLR : WO; bitpos: [28]; default: 0; - * reset swd reset flag - */ - -#define RTC_CNTL_SWD_RST_FLAG_CLR (BIT(28)) -#define RTC_CNTL_SWD_RST_FLAG_CLR_M (RTC_CNTL_SWD_RST_FLAG_CLR_V << RTC_CNTL_SWD_RST_FLAG_CLR_S) -#define RTC_CNTL_SWD_RST_FLAG_CLR_V 0x00000001 -#define RTC_CNTL_SWD_RST_FLAG_CLR_S 28 - -/* RTC_CNTL_SWD_SIGNAL_WIDTH : R/W; bitpos: [27:18]; default: 300; - * adjust signal width send to swd - */ - -#define RTC_CNTL_SWD_SIGNAL_WIDTH 0x000003ff -#define RTC_CNTL_SWD_SIGNAL_WIDTH_M (RTC_CNTL_SWD_SIGNAL_WIDTH_V << RTC_CNTL_SWD_SIGNAL_WIDTH_S) -#define RTC_CNTL_SWD_SIGNAL_WIDTH_V 0x000003ff -#define RTC_CNTL_SWD_SIGNAL_WIDTH_S 18 - -/* RTC_CNTL_SWD_BYPASS_RST : R/W; bitpos: [17]; default: 0; - * bypass super watch dog reset - */ - -#define RTC_CNTL_SWD_BYPASS_RST (BIT(17)) -#define RTC_CNTL_SWD_BYPASS_RST_M (RTC_CNTL_SWD_BYPASS_RST_V << RTC_CNTL_SWD_BYPASS_RST_S) -#define RTC_CNTL_SWD_BYPASS_RST_V 0x00000001 -#define RTC_CNTL_SWD_BYPASS_RST_S 17 - -/* RTC_CNTL_SWD_FEED_INT : RO; bitpos: [1]; default: 0; - * swd interrupt for feeding - */ - -#define RTC_CNTL_SWD_FEED_INT (BIT(1)) -#define RTC_CNTL_SWD_FEED_INT_M (RTC_CNTL_SWD_FEED_INT_V << RTC_CNTL_SWD_FEED_INT_S) -#define RTC_CNTL_SWD_FEED_INT_V 0x00000001 -#define RTC_CNTL_SWD_FEED_INT_S 1 - -/* RTC_CNTL_SWD_RESET_FLAG : RO; bitpos: [0]; default: 0; - * swd reset flag - */ - -#define RTC_CNTL_SWD_RESET_FLAG (BIT(0)) -#define RTC_CNTL_SWD_RESET_FLAG_M (RTC_CNTL_SWD_RESET_FLAG_V << RTC_CNTL_SWD_RESET_FLAG_S) -#define RTC_CNTL_SWD_RESET_FLAG_V 0x00000001 -#define RTC_CNTL_SWD_RESET_FLAG_S 0 - -/* RTC_CNTL_RTC_SWD_WPROTECT_REG register - * super watch dog key - */ - -#define RTC_CNTL_RTC_SWD_WPROTECT_REG (DR_REG_RTCCNTL_BASE + 0xb8) - -/* RTC_CNTL_SWD_WKEY : R/W; bitpos: [31:0]; default: 2401055018; - * super watch dog key - */ - -#define RTC_CNTL_SWD_WKEY 0xffffffff -#define RTC_CNTL_SWD_WKEY_M (RTC_CNTL_SWD_WKEY_V << RTC_CNTL_SWD_WKEY_S) -#define RTC_CNTL_SWD_WKEY_V 0xffffffff -#define RTC_CNTL_SWD_WKEY_S 0 - -/* RTC_CNTL_RTC_SW_CPU_STALL_REG register - * configure cpu stall by sw - */ - -#define RTC_CNTL_RTC_SW_CPU_STALL_REG (DR_REG_RTCCNTL_BASE + 0xbc) - -/* RTC_CNTL_SW_STALL_PROCPU_C1 : R/W; bitpos: [31:26]; default: 0; - * {reg_sw_stall_appcpu_c1[5:0], reg_sw_stall_appcpu_c0[1:0]} == 0x86 will - * stall APP CPU - */ - -#define RTC_CNTL_SW_STALL_PROCPU_C1 0x0000003f -#define RTC_CNTL_SW_STALL_PROCPU_C1_M (RTC_CNTL_SW_STALL_PROCPU_C1_V << RTC_CNTL_SW_STALL_PROCPU_C1_S) -#define RTC_CNTL_SW_STALL_PROCPU_C1_V 0x0000003f -#define RTC_CNTL_SW_STALL_PROCPU_C1_S 26 - -/* RTC_CNTL_SW_STALL_APPCPU_C1 : R/W; bitpos: [25:20]; default: 0; - * {reg_sw_stall_appcpu_c1[5:0], reg_sw_stall_appcpu_c0[1:0]} == 0x86 will - * stall APP CPU - */ - -#define RTC_CNTL_SW_STALL_APPCPU_C1 0x0000003f -#define RTC_CNTL_SW_STALL_APPCPU_C1_M (RTC_CNTL_SW_STALL_APPCPU_C1_V << RTC_CNTL_SW_STALL_APPCPU_C1_S) -#define RTC_CNTL_SW_STALL_APPCPU_C1_V 0x0000003f -#define RTC_CNTL_SW_STALL_APPCPU_C1_S 20 - -/* RTC_CNTL_RTC_STORE4_REG register - * reserved register - */ - -#define RTC_CNTL_RTC_STORE4_REG (DR_REG_RTCCNTL_BASE + 0xc0) - -/* RTC_CNTL_RTC_SCRATCH4 : R/W; bitpos: [31:0]; default: 0; - * reserved register - */ - -#define RTC_CNTL_RTC_SCRATCH4 0xffffffff -#define RTC_CNTL_RTC_SCRATCH4_M (RTC_CNTL_RTC_SCRATCH4_V << RTC_CNTL_RTC_SCRATCH4_S) -#define RTC_CNTL_RTC_SCRATCH4_V 0xffffffff -#define RTC_CNTL_RTC_SCRATCH4_S 0 - -/* RTC_CNTL_RTC_STORE5_REG register - * reserved register - */ - -#define RTC_CNTL_RTC_STORE5_REG (DR_REG_RTCCNTL_BASE + 0xc4) - -/* RTC_CNTL_RTC_SCRATCH5 : R/W; bitpos: [31:0]; default: 0; - * reserved register - */ - -#define RTC_CNTL_RTC_SCRATCH5 0xffffffff -#define RTC_CNTL_RTC_SCRATCH5_M (RTC_CNTL_RTC_SCRATCH5_V << RTC_CNTL_RTC_SCRATCH5_S) -#define RTC_CNTL_RTC_SCRATCH5_V 0xffffffff -#define RTC_CNTL_RTC_SCRATCH5_S 0 - -/* RTC_CNTL_RTC_STORE6_REG register - * reserved register - */ - -#define RTC_CNTL_RTC_STORE6_REG (DR_REG_RTCCNTL_BASE + 0xc8) - -/* RTC_CNTL_RTC_SCRATCH6 : R/W; bitpos: [31:0]; default: 0; - * reserved register - */ - -#define RTC_CNTL_RTC_SCRATCH6 0xffffffff -#define RTC_CNTL_RTC_SCRATCH6_M (RTC_CNTL_RTC_SCRATCH6_V << RTC_CNTL_RTC_SCRATCH6_S) -#define RTC_CNTL_RTC_SCRATCH6_V 0xffffffff -#define RTC_CNTL_RTC_SCRATCH6_S 0 - -/* RTC_CNTL_RTC_STORE7_REG register - * reserved register - */ - -#define RTC_CNTL_RTC_STORE7_REG (DR_REG_RTCCNTL_BASE + 0xcc) - -/* RTC_CNTL_RTC_SCRATCH7 : R/W; bitpos: [31:0]; default: 0; - * reserved register - */ - -#define RTC_CNTL_RTC_SCRATCH7 0xffffffff -#define RTC_CNTL_RTC_SCRATCH7_M (RTC_CNTL_RTC_SCRATCH7_V << RTC_CNTL_RTC_SCRATCH7_S) -#define RTC_CNTL_RTC_SCRATCH7_V 0xffffffff -#define RTC_CNTL_RTC_SCRATCH7_S 0 - -/* RTC_CNTL_RTC_LOW_POWER_ST_REG register - * reserved register - */ - -#define RTC_CNTL_RTC_LOW_POWER_ST_REG (DR_REG_RTCCNTL_BASE + 0xd0) - -/* RTC_CNTL_RTC_MAIN_STATE : RO; bitpos: [31:28]; default: 0; - * rtc main state machine status - */ - -#define RTC_CNTL_RTC_MAIN_STATE 0x0000000f -#define RTC_CNTL_RTC_MAIN_STATE_M (RTC_CNTL_RTC_MAIN_STATE_V << RTC_CNTL_RTC_MAIN_STATE_S) -#define RTC_CNTL_RTC_MAIN_STATE_V 0x0000000f -#define RTC_CNTL_RTC_MAIN_STATE_S 28 - -/* RTC_CNTL_RTC_MAIN_STATE_IN_IDLE : RO; bitpos: [27]; default: 0; - * rtc main state machine is in idle state - */ - -#define RTC_CNTL_RTC_MAIN_STATE_IN_IDLE (BIT(27)) -#define RTC_CNTL_RTC_MAIN_STATE_IN_IDLE_M (RTC_CNTL_RTC_MAIN_STATE_IN_IDLE_V << RTC_CNTL_RTC_MAIN_STATE_IN_IDLE_S) -#define RTC_CNTL_RTC_MAIN_STATE_IN_IDLE_V 0x00000001 -#define RTC_CNTL_RTC_MAIN_STATE_IN_IDLE_S 27 - -/* RTC_CNTL_RTC_MAIN_STATE_IN_SLP : RO; bitpos: [26]; default: 0; - * rtc main state machine is in sleep state - */ - -#define RTC_CNTL_RTC_MAIN_STATE_IN_SLP (BIT(26)) -#define RTC_CNTL_RTC_MAIN_STATE_IN_SLP_M (RTC_CNTL_RTC_MAIN_STATE_IN_SLP_V << RTC_CNTL_RTC_MAIN_STATE_IN_SLP_S) -#define RTC_CNTL_RTC_MAIN_STATE_IN_SLP_V 0x00000001 -#define RTC_CNTL_RTC_MAIN_STATE_IN_SLP_S 26 - -/* RTC_CNTL_RTC_MAIN_STATE_IN_WAIT_XTL : RO; bitpos: [25]; default: 0; - * rtc main state machine is in wait xtal state - */ - -#define RTC_CNTL_RTC_MAIN_STATE_IN_WAIT_XTL (BIT(25)) -#define RTC_CNTL_RTC_MAIN_STATE_IN_WAIT_XTL_M (RTC_CNTL_RTC_MAIN_STATE_IN_WAIT_XTL_V << RTC_CNTL_RTC_MAIN_STATE_IN_WAIT_XTL_S) -#define RTC_CNTL_RTC_MAIN_STATE_IN_WAIT_XTL_V 0x00000001 -#define RTC_CNTL_RTC_MAIN_STATE_IN_WAIT_XTL_S 25 - -/* RTC_CNTL_RTC_MAIN_STATE_IN_WAIT_PLL : RO; bitpos: [24]; default: 0; - * rtc main state machine is in wait pll state - */ - -#define RTC_CNTL_RTC_MAIN_STATE_IN_WAIT_PLL (BIT(24)) -#define RTC_CNTL_RTC_MAIN_STATE_IN_WAIT_PLL_M (RTC_CNTL_RTC_MAIN_STATE_IN_WAIT_PLL_V << RTC_CNTL_RTC_MAIN_STATE_IN_WAIT_PLL_S) -#define RTC_CNTL_RTC_MAIN_STATE_IN_WAIT_PLL_V 0x00000001 -#define RTC_CNTL_RTC_MAIN_STATE_IN_WAIT_PLL_S 24 - -/* RTC_CNTL_RTC_MAIN_STATE_IN_WAIT_8M : RO; bitpos: [23]; default: 0; - * rtc main state machine is in wait 8m state - */ - -#define RTC_CNTL_RTC_MAIN_STATE_IN_WAIT_8M (BIT(23)) -#define RTC_CNTL_RTC_MAIN_STATE_IN_WAIT_8M_M (RTC_CNTL_RTC_MAIN_STATE_IN_WAIT_8M_V << RTC_CNTL_RTC_MAIN_STATE_IN_WAIT_8M_S) -#define RTC_CNTL_RTC_MAIN_STATE_IN_WAIT_8M_V 0x00000001 -#define RTC_CNTL_RTC_MAIN_STATE_IN_WAIT_8M_S 23 - -/* RTC_CNTL_RTC_IN_LOW_POWER_STATE : RO; bitpos: [22]; default: 0; - * rtc main state machine is in the states of low power - */ - -#define RTC_CNTL_RTC_IN_LOW_POWER_STATE (BIT(22)) -#define RTC_CNTL_RTC_IN_LOW_POWER_STATE_M (RTC_CNTL_RTC_IN_LOW_POWER_STATE_V << RTC_CNTL_RTC_IN_LOW_POWER_STATE_S) -#define RTC_CNTL_RTC_IN_LOW_POWER_STATE_V 0x00000001 -#define RTC_CNTL_RTC_IN_LOW_POWER_STATE_S 22 - -/* RTC_CNTL_RTC_IN_WAKEUP_STATE : RO; bitpos: [21]; default: 0; - * rtc main state machine is in the states of wakeup process - */ - -#define RTC_CNTL_RTC_IN_WAKEUP_STATE (BIT(21)) -#define RTC_CNTL_RTC_IN_WAKEUP_STATE_M (RTC_CNTL_RTC_IN_WAKEUP_STATE_V << RTC_CNTL_RTC_IN_WAKEUP_STATE_S) -#define RTC_CNTL_RTC_IN_WAKEUP_STATE_V 0x00000001 -#define RTC_CNTL_RTC_IN_WAKEUP_STATE_S 21 - -/* RTC_CNTL_RTC_MAIN_STATE_WAIT_END : RO; bitpos: [20]; default: 0; - * rtc main state machine has been waited for some cycles - */ - -#define RTC_CNTL_RTC_MAIN_STATE_WAIT_END (BIT(20)) -#define RTC_CNTL_RTC_MAIN_STATE_WAIT_END_M (RTC_CNTL_RTC_MAIN_STATE_WAIT_END_V << RTC_CNTL_RTC_MAIN_STATE_WAIT_END_S) -#define RTC_CNTL_RTC_MAIN_STATE_WAIT_END_V 0x00000001 -#define RTC_CNTL_RTC_MAIN_STATE_WAIT_END_S 20 - -/* RTC_CNTL_RTC_RDY_FOR_WAKEUP : RO; bitpos: [19]; default: 0; - * rtc is ready to receive wake up trigger from wake up source - */ - -#define RTC_CNTL_RTC_RDY_FOR_WAKEUP (BIT(19)) -#define RTC_CNTL_RTC_RDY_FOR_WAKEUP_M (RTC_CNTL_RTC_RDY_FOR_WAKEUP_V << RTC_CNTL_RTC_RDY_FOR_WAKEUP_S) -#define RTC_CNTL_RTC_RDY_FOR_WAKEUP_V 0x00000001 -#define RTC_CNTL_RTC_RDY_FOR_WAKEUP_S 19 - -/* RTC_CNTL_RTC_MAIN_STATE_PLL_ON : RO; bitpos: [18]; default: 0; - * rtc main state machine is in states that pll should be running - */ - -#define RTC_CNTL_RTC_MAIN_STATE_PLL_ON (BIT(18)) -#define RTC_CNTL_RTC_MAIN_STATE_PLL_ON_M (RTC_CNTL_RTC_MAIN_STATE_PLL_ON_V << RTC_CNTL_RTC_MAIN_STATE_PLL_ON_S) -#define RTC_CNTL_RTC_MAIN_STATE_PLL_ON_V 0x00000001 -#define RTC_CNTL_RTC_MAIN_STATE_PLL_ON_S 18 - -/* RTC_CNTL_RTC_MAIN_STATE_XTAL_ISO : RO; bitpos: [17]; default: 0; - * no use any more - */ - -#define RTC_CNTL_RTC_MAIN_STATE_XTAL_ISO (BIT(17)) -#define RTC_CNTL_RTC_MAIN_STATE_XTAL_ISO_M (RTC_CNTL_RTC_MAIN_STATE_XTAL_ISO_V << RTC_CNTL_RTC_MAIN_STATE_XTAL_ISO_S) -#define RTC_CNTL_RTC_MAIN_STATE_XTAL_ISO_V 0x00000001 -#define RTC_CNTL_RTC_MAIN_STATE_XTAL_ISO_S 17 - -/* RTC_CNTL_RTC_COCPU_STATE_DONE : RO; bitpos: [16]; default: 0; - * ulp/cocpu is done - */ - -#define RTC_CNTL_RTC_COCPU_STATE_DONE (BIT(16)) -#define RTC_CNTL_RTC_COCPU_STATE_DONE_M (RTC_CNTL_RTC_COCPU_STATE_DONE_V << RTC_CNTL_RTC_COCPU_STATE_DONE_S) -#define RTC_CNTL_RTC_COCPU_STATE_DONE_V 0x00000001 -#define RTC_CNTL_RTC_COCPU_STATE_DONE_S 16 - -/* RTC_CNTL_RTC_COCPU_STATE_SLP : RO; bitpos: [15]; default: 0; - * ulp/cocpu is in sleep state - */ - -#define RTC_CNTL_RTC_COCPU_STATE_SLP (BIT(15)) -#define RTC_CNTL_RTC_COCPU_STATE_SLP_M (RTC_CNTL_RTC_COCPU_STATE_SLP_V << RTC_CNTL_RTC_COCPU_STATE_SLP_S) -#define RTC_CNTL_RTC_COCPU_STATE_SLP_V 0x00000001 -#define RTC_CNTL_RTC_COCPU_STATE_SLP_S 15 - -/* RTC_CNTL_RTC_COCPU_STATE_SWITCH : RO; bitpos: [14]; default: 0; - * ulp/cocpu is about to working. Switch rtc main state - */ - -#define RTC_CNTL_RTC_COCPU_STATE_SWITCH (BIT(14)) -#define RTC_CNTL_RTC_COCPU_STATE_SWITCH_M (RTC_CNTL_RTC_COCPU_STATE_SWITCH_V << RTC_CNTL_RTC_COCPU_STATE_SWITCH_S) -#define RTC_CNTL_RTC_COCPU_STATE_SWITCH_V 0x00000001 -#define RTC_CNTL_RTC_COCPU_STATE_SWITCH_S 14 - -/* RTC_CNTL_RTC_COCPU_STATE_START : RO; bitpos: [13]; default: 0; - * ulp/cocpu should start to work - */ - -#define RTC_CNTL_RTC_COCPU_STATE_START (BIT(13)) -#define RTC_CNTL_RTC_COCPU_STATE_START_M (RTC_CNTL_RTC_COCPU_STATE_START_V << RTC_CNTL_RTC_COCPU_STATE_START_S) -#define RTC_CNTL_RTC_COCPU_STATE_START_V 0x00000001 -#define RTC_CNTL_RTC_COCPU_STATE_START_S 13 - -/* RTC_CNTL_RTC_TOUCH_STATE_DONE : RO; bitpos: [12]; default: 0; - * touch is done - */ - -#define RTC_CNTL_RTC_TOUCH_STATE_DONE (BIT(12)) -#define RTC_CNTL_RTC_TOUCH_STATE_DONE_M (RTC_CNTL_RTC_TOUCH_STATE_DONE_V << RTC_CNTL_RTC_TOUCH_STATE_DONE_S) -#define RTC_CNTL_RTC_TOUCH_STATE_DONE_V 0x00000001 -#define RTC_CNTL_RTC_TOUCH_STATE_DONE_S 12 - -/* RTC_CNTL_RTC_TOUCH_STATE_SLP : RO; bitpos: [11]; default: 0; - * touch is in sleep state - */ - -#define RTC_CNTL_RTC_TOUCH_STATE_SLP (BIT(11)) -#define RTC_CNTL_RTC_TOUCH_STATE_SLP_M (RTC_CNTL_RTC_TOUCH_STATE_SLP_V << RTC_CNTL_RTC_TOUCH_STATE_SLP_S) -#define RTC_CNTL_RTC_TOUCH_STATE_SLP_V 0x00000001 -#define RTC_CNTL_RTC_TOUCH_STATE_SLP_S 11 - -/* RTC_CNTL_RTC_TOUCH_STATE_SWITCH : RO; bitpos: [10]; default: 0; - * touch is about to working. Switch rtc main state - */ - -#define RTC_CNTL_RTC_TOUCH_STATE_SWITCH (BIT(10)) -#define RTC_CNTL_RTC_TOUCH_STATE_SWITCH_M (RTC_CNTL_RTC_TOUCH_STATE_SWITCH_V << RTC_CNTL_RTC_TOUCH_STATE_SWITCH_S) -#define RTC_CNTL_RTC_TOUCH_STATE_SWITCH_V 0x00000001 -#define RTC_CNTL_RTC_TOUCH_STATE_SWITCH_S 10 - -/* RTC_CNTL_RTC_TOUCH_STATE_START : RO; bitpos: [9]; default: 0; - * touch should start to work - */ - -#define RTC_CNTL_RTC_TOUCH_STATE_START (BIT(9)) -#define RTC_CNTL_RTC_TOUCH_STATE_START_M (RTC_CNTL_RTC_TOUCH_STATE_START_V << RTC_CNTL_RTC_TOUCH_STATE_START_S) -#define RTC_CNTL_RTC_TOUCH_STATE_START_V 0x00000001 -#define RTC_CNTL_RTC_TOUCH_STATE_START_S 9 - -/* RTC_CNTL_XPD_DIG : RO; bitpos: [8]; default: 0; - * digital wrap power down - */ - -#define RTC_CNTL_XPD_DIG (BIT(8)) -#define RTC_CNTL_XPD_DIG_M (RTC_CNTL_XPD_DIG_V << RTC_CNTL_XPD_DIG_S) -#define RTC_CNTL_XPD_DIG_V 0x00000001 -#define RTC_CNTL_XPD_DIG_S 8 - -/* RTC_CNTL_DIG_ISO : RO; bitpos: [7]; default: 0; - * digital wrap iso - */ - -#define RTC_CNTL_DIG_ISO (BIT(7)) -#define RTC_CNTL_DIG_ISO_M (RTC_CNTL_DIG_ISO_V << RTC_CNTL_DIG_ISO_S) -#define RTC_CNTL_DIG_ISO_V 0x00000001 -#define RTC_CNTL_DIG_ISO_S 7 - -/* RTC_CNTL_XPD_WIFI : RO; bitpos: [6]; default: 0; - * wifi wrap power down - */ - -#define RTC_CNTL_XPD_WIFI (BIT(6)) -#define RTC_CNTL_XPD_WIFI_M (RTC_CNTL_XPD_WIFI_V << RTC_CNTL_XPD_WIFI_S) -#define RTC_CNTL_XPD_WIFI_V 0x00000001 -#define RTC_CNTL_XPD_WIFI_S 6 - -/* RTC_CNTL_WIFI_ISO : RO; bitpos: [5]; default: 0; - * wifi iso - */ - -#define RTC_CNTL_WIFI_ISO (BIT(5)) -#define RTC_CNTL_WIFI_ISO_M (RTC_CNTL_WIFI_ISO_V << RTC_CNTL_WIFI_ISO_S) -#define RTC_CNTL_WIFI_ISO_V 0x00000001 -#define RTC_CNTL_WIFI_ISO_S 5 - -/* RTC_CNTL_XPD_RTC_PERI : RO; bitpos: [4]; default: 0; - * rtc peripheral power down - */ - -#define RTC_CNTL_XPD_RTC_PERI (BIT(4)) -#define RTC_CNTL_XPD_RTC_PERI_M (RTC_CNTL_XPD_RTC_PERI_V << RTC_CNTL_XPD_RTC_PERI_S) -#define RTC_CNTL_XPD_RTC_PERI_V 0x00000001 -#define RTC_CNTL_XPD_RTC_PERI_S 4 - -/* RTC_CNTL_RTC_PERI_ISO : RO; bitpos: [3]; default: 0; - * rtc peripheral iso - */ - -#define RTC_CNTL_RTC_PERI_ISO (BIT(3)) -#define RTC_CNTL_RTC_PERI_ISO_M (RTC_CNTL_RTC_PERI_ISO_V << RTC_CNTL_RTC_PERI_ISO_S) -#define RTC_CNTL_RTC_PERI_ISO_V 0x00000001 -#define RTC_CNTL_RTC_PERI_ISO_S 3 - -/* RTC_CNTL_XPD_DIG_DCDC : RO; bitpos: [2]; default: 0; - * External DCDC power down - */ - -#define RTC_CNTL_XPD_DIG_DCDC (BIT(2)) -#define RTC_CNTL_XPD_DIG_DCDC_M (RTC_CNTL_XPD_DIG_DCDC_V << RTC_CNTL_XPD_DIG_DCDC_S) -#define RTC_CNTL_XPD_DIG_DCDC_V 0x00000001 -#define RTC_CNTL_XPD_DIG_DCDC_S 2 - -/* RTC_CNTL_XPD_ROM0 : RO; bitpos: [0]; default: 0; - * rom0 power down - */ - -#define RTC_CNTL_XPD_ROM0 (BIT(0)) -#define RTC_CNTL_XPD_ROM0_M (RTC_CNTL_XPD_ROM0_V << RTC_CNTL_XPD_ROM0_S) -#define RTC_CNTL_XPD_ROM0_V 0x00000001 -#define RTC_CNTL_XPD_ROM0_S 0 - -/* RTC_CNTL_RTC_DIAG0_REG register - * No public - */ - -#define RTC_CNTL_RTC_DIAG0_REG (DR_REG_RTCCNTL_BASE + 0xd4) - -/* RTC_CNTL_RTC_LOW_POWER_DIAG1 : RO; bitpos: [31:0]; default: 0; - * No public - */ - -#define RTC_CNTL_RTC_LOW_POWER_DIAG1 0xffffffff -#define RTC_CNTL_RTC_LOW_POWER_DIAG1_M (RTC_CNTL_RTC_LOW_POWER_DIAG1_V << RTC_CNTL_RTC_LOW_POWER_DIAG1_S) -#define RTC_CNTL_RTC_LOW_POWER_DIAG1_V 0xffffffff -#define RTC_CNTL_RTC_LOW_POWER_DIAG1_S 0 - -/* RTC_CNTL_RTC_PAD_HOLD_REG register - * rtc pad hold configure - */ - -#define RTC_CNTL_RTC_PAD_HOLD_REG (DR_REG_RTCCNTL_BASE + 0xd8) - -/* RTC_CNTL_RTC_PAD21_HOLD : R/W; bitpos: [21]; default: 0; - * hold rtc pad-21 - */ - -#define RTC_CNTL_RTC_PAD21_HOLD (BIT(21)) -#define RTC_CNTL_RTC_PAD21_HOLD_M (RTC_CNTL_RTC_PAD21_HOLD_V << RTC_CNTL_RTC_PAD21_HOLD_S) -#define RTC_CNTL_RTC_PAD21_HOLD_V 0x00000001 -#define RTC_CNTL_RTC_PAD21_HOLD_S 21 - -/* RTC_CNTL_RTC_PAD20_HOLD : R/W; bitpos: [20]; default: 0; - * hold rtc pad-20 - */ - -#define RTC_CNTL_RTC_PAD20_HOLD (BIT(20)) -#define RTC_CNTL_RTC_PAD20_HOLD_M (RTC_CNTL_RTC_PAD20_HOLD_V << RTC_CNTL_RTC_PAD20_HOLD_S) -#define RTC_CNTL_RTC_PAD20_HOLD_V 0x00000001 -#define RTC_CNTL_RTC_PAD20_HOLD_S 20 - -/* RTC_CNTL_RTC_PAD19_HOLD : R/W; bitpos: [19]; default: 0; - * hold rtc pad-19 - */ - -#define RTC_CNTL_RTC_PAD19_HOLD (BIT(19)) -#define RTC_CNTL_RTC_PAD19_HOLD_M (RTC_CNTL_RTC_PAD19_HOLD_V << RTC_CNTL_RTC_PAD19_HOLD_S) -#define RTC_CNTL_RTC_PAD19_HOLD_V 0x00000001 -#define RTC_CNTL_RTC_PAD19_HOLD_S 19 - -/* RTC_CNTL_PDAC2_HOLD : R/W; bitpos: [18]; default: 0; - * hold rtc pad-18 - */ - -#define RTC_CNTL_PDAC2_HOLD (BIT(18)) -#define RTC_CNTL_PDAC2_HOLD_M (RTC_CNTL_PDAC2_HOLD_V << RTC_CNTL_PDAC2_HOLD_S) -#define RTC_CNTL_PDAC2_HOLD_V 0x00000001 -#define RTC_CNTL_PDAC2_HOLD_S 18 - -/* RTC_CNTL_PDAC1_HOLD : R/W; bitpos: [17]; default: 0; - * hold rtc pad-17 - */ - -#define RTC_CNTL_PDAC1_HOLD (BIT(17)) -#define RTC_CNTL_PDAC1_HOLD_M (RTC_CNTL_PDAC1_HOLD_V << RTC_CNTL_PDAC1_HOLD_S) -#define RTC_CNTL_PDAC1_HOLD_V 0x00000001 -#define RTC_CNTL_PDAC1_HOLD_S 17 - -/* RTC_CNTL_X32N_HOLD : R/W; bitpos: [16]; default: 0; - * hold rtc pad-16 - */ - -#define RTC_CNTL_X32N_HOLD (BIT(16)) -#define RTC_CNTL_X32N_HOLD_M (RTC_CNTL_X32N_HOLD_V << RTC_CNTL_X32N_HOLD_S) -#define RTC_CNTL_X32N_HOLD_V 0x00000001 -#define RTC_CNTL_X32N_HOLD_S 16 - -/* RTC_CNTL_X32P_HOLD : R/W; bitpos: [15]; default: 0; - * hold rtc pad-15 - */ - -#define RTC_CNTL_X32P_HOLD (BIT(15)) -#define RTC_CNTL_X32P_HOLD_M (RTC_CNTL_X32P_HOLD_V << RTC_CNTL_X32P_HOLD_S) -#define RTC_CNTL_X32P_HOLD_V 0x00000001 -#define RTC_CNTL_X32P_HOLD_S 15 - -/* RTC_CNTL_TOUCH_PAD14_HOLD : R/W; bitpos: [14]; default: 0; - * hold rtc pad-14 - */ - -#define RTC_CNTL_TOUCH_PAD14_HOLD (BIT(14)) -#define RTC_CNTL_TOUCH_PAD14_HOLD_M (RTC_CNTL_TOUCH_PAD14_HOLD_V << RTC_CNTL_TOUCH_PAD14_HOLD_S) -#define RTC_CNTL_TOUCH_PAD14_HOLD_V 0x00000001 -#define RTC_CNTL_TOUCH_PAD14_HOLD_S 14 - -/* RTC_CNTL_TOUCH_PAD13_HOLD : R/W; bitpos: [13]; default: 0; - * hold rtc pad-13 - */ - -#define RTC_CNTL_TOUCH_PAD13_HOLD (BIT(13)) -#define RTC_CNTL_TOUCH_PAD13_HOLD_M (RTC_CNTL_TOUCH_PAD13_HOLD_V << RTC_CNTL_TOUCH_PAD13_HOLD_S) -#define RTC_CNTL_TOUCH_PAD13_HOLD_V 0x00000001 -#define RTC_CNTL_TOUCH_PAD13_HOLD_S 13 - -/* RTC_CNTL_TOUCH_PAD12_HOLD : R/W; bitpos: [12]; default: 0; - * hold rtc pad-12 - */ - -#define RTC_CNTL_TOUCH_PAD12_HOLD (BIT(12)) -#define RTC_CNTL_TOUCH_PAD12_HOLD_M (RTC_CNTL_TOUCH_PAD12_HOLD_V << RTC_CNTL_TOUCH_PAD12_HOLD_S) -#define RTC_CNTL_TOUCH_PAD12_HOLD_V 0x00000001 -#define RTC_CNTL_TOUCH_PAD12_HOLD_S 12 - -/* RTC_CNTL_TOUCH_PAD11_HOLD : R/W; bitpos: [11]; default: 0; - * hold rtc pad-11 - */ - -#define RTC_CNTL_TOUCH_PAD11_HOLD (BIT(11)) -#define RTC_CNTL_TOUCH_PAD11_HOLD_M (RTC_CNTL_TOUCH_PAD11_HOLD_V << RTC_CNTL_TOUCH_PAD11_HOLD_S) -#define RTC_CNTL_TOUCH_PAD11_HOLD_V 0x00000001 -#define RTC_CNTL_TOUCH_PAD11_HOLD_S 11 - -/* RTC_CNTL_TOUCH_PAD10_HOLD : R/W; bitpos: [10]; default: 0; - * hold rtc pad-10 - */ - -#define RTC_CNTL_TOUCH_PAD10_HOLD (BIT(10)) -#define RTC_CNTL_TOUCH_PAD10_HOLD_M (RTC_CNTL_TOUCH_PAD10_HOLD_V << RTC_CNTL_TOUCH_PAD10_HOLD_S) -#define RTC_CNTL_TOUCH_PAD10_HOLD_V 0x00000001 -#define RTC_CNTL_TOUCH_PAD10_HOLD_S 10 - -/* RTC_CNTL_TOUCH_PAD9_HOLD : R/W; bitpos: [9]; default: 0; - * hold rtc pad-9 - */ - -#define RTC_CNTL_TOUCH_PAD9_HOLD (BIT(9)) -#define RTC_CNTL_TOUCH_PAD9_HOLD_M (RTC_CNTL_TOUCH_PAD9_HOLD_V << RTC_CNTL_TOUCH_PAD9_HOLD_S) -#define RTC_CNTL_TOUCH_PAD9_HOLD_V 0x00000001 -#define RTC_CNTL_TOUCH_PAD9_HOLD_S 9 - -/* RTC_CNTL_TOUCH_PAD8_HOLD : R/W; bitpos: [8]; default: 0; - * hold rtc pad-8 - */ - -#define RTC_CNTL_TOUCH_PAD8_HOLD (BIT(8)) -#define RTC_CNTL_TOUCH_PAD8_HOLD_M (RTC_CNTL_TOUCH_PAD8_HOLD_V << RTC_CNTL_TOUCH_PAD8_HOLD_S) -#define RTC_CNTL_TOUCH_PAD8_HOLD_V 0x00000001 -#define RTC_CNTL_TOUCH_PAD8_HOLD_S 8 - -/* RTC_CNTL_TOUCH_PAD7_HOLD : R/W; bitpos: [7]; default: 0; - * hold rtc pad-7 - */ - -#define RTC_CNTL_TOUCH_PAD7_HOLD (BIT(7)) -#define RTC_CNTL_TOUCH_PAD7_HOLD_M (RTC_CNTL_TOUCH_PAD7_HOLD_V << RTC_CNTL_TOUCH_PAD7_HOLD_S) -#define RTC_CNTL_TOUCH_PAD7_HOLD_V 0x00000001 -#define RTC_CNTL_TOUCH_PAD7_HOLD_S 7 - -/* RTC_CNTL_TOUCH_PAD6_HOLD : R/W; bitpos: [6]; default: 0; - * hold rtc pad-6 - */ - -#define RTC_CNTL_TOUCH_PAD6_HOLD (BIT(6)) -#define RTC_CNTL_TOUCH_PAD6_HOLD_M (RTC_CNTL_TOUCH_PAD6_HOLD_V << RTC_CNTL_TOUCH_PAD6_HOLD_S) -#define RTC_CNTL_TOUCH_PAD6_HOLD_V 0x00000001 -#define RTC_CNTL_TOUCH_PAD6_HOLD_S 6 - -/* RTC_CNTL_TOUCH_PAD5_HOLD : R/W; bitpos: [5]; default: 0; - * hold rtc pad-5 - */ - -#define RTC_CNTL_TOUCH_PAD5_HOLD (BIT(5)) -#define RTC_CNTL_TOUCH_PAD5_HOLD_M (RTC_CNTL_TOUCH_PAD5_HOLD_V << RTC_CNTL_TOUCH_PAD5_HOLD_S) -#define RTC_CNTL_TOUCH_PAD5_HOLD_V 0x00000001 -#define RTC_CNTL_TOUCH_PAD5_HOLD_S 5 - -/* RTC_CNTL_TOUCH_PAD4_HOLD : R/W; bitpos: [4]; default: 0; - * hold rtc pad-4 - */ - -#define RTC_CNTL_TOUCH_PAD4_HOLD (BIT(4)) -#define RTC_CNTL_TOUCH_PAD4_HOLD_M (RTC_CNTL_TOUCH_PAD4_HOLD_V << RTC_CNTL_TOUCH_PAD4_HOLD_S) -#define RTC_CNTL_TOUCH_PAD4_HOLD_V 0x00000001 -#define RTC_CNTL_TOUCH_PAD4_HOLD_S 4 - -/* RTC_CNTL_TOUCH_PAD3_HOLD : R/W; bitpos: [3]; default: 0; - * hold rtc pad-3 - */ - -#define RTC_CNTL_TOUCH_PAD3_HOLD (BIT(3)) -#define RTC_CNTL_TOUCH_PAD3_HOLD_M (RTC_CNTL_TOUCH_PAD3_HOLD_V << RTC_CNTL_TOUCH_PAD3_HOLD_S) -#define RTC_CNTL_TOUCH_PAD3_HOLD_V 0x00000001 -#define RTC_CNTL_TOUCH_PAD3_HOLD_S 3 - -/* RTC_CNTL_TOUCH_PAD2_HOLD : R/W; bitpos: [2]; default: 0; - * hold rtc pad-2 - */ - -#define RTC_CNTL_TOUCH_PAD2_HOLD (BIT(2)) -#define RTC_CNTL_TOUCH_PAD2_HOLD_M (RTC_CNTL_TOUCH_PAD2_HOLD_V << RTC_CNTL_TOUCH_PAD2_HOLD_S) -#define RTC_CNTL_TOUCH_PAD2_HOLD_V 0x00000001 -#define RTC_CNTL_TOUCH_PAD2_HOLD_S 2 - -/* RTC_CNTL_TOUCH_PAD1_HOLD : R/W; bitpos: [1]; default: 0; - * hold rtc pad-1 - */ - -#define RTC_CNTL_TOUCH_PAD1_HOLD (BIT(1)) -#define RTC_CNTL_TOUCH_PAD1_HOLD_M (RTC_CNTL_TOUCH_PAD1_HOLD_V << RTC_CNTL_TOUCH_PAD1_HOLD_S) -#define RTC_CNTL_TOUCH_PAD1_HOLD_V 0x00000001 -#define RTC_CNTL_TOUCH_PAD1_HOLD_S 1 - -/* RTC_CNTL_TOUCH_PAD0_HOLD : R/W; bitpos: [0]; default: 0; - * hold rtc pad0 - */ - -#define RTC_CNTL_TOUCH_PAD0_HOLD (BIT(0)) -#define RTC_CNTL_TOUCH_PAD0_HOLD_M (RTC_CNTL_TOUCH_PAD0_HOLD_V << RTC_CNTL_TOUCH_PAD0_HOLD_S) -#define RTC_CNTL_TOUCH_PAD0_HOLD_V 0x00000001 -#define RTC_CNTL_TOUCH_PAD0_HOLD_S 0 - -/* RTC_CNTL_DIG_PAD_HOLD_REG register - * configure digtal pad hold - */ - -#define RTC_CNTL_DIG_PAD_HOLD_REG (DR_REG_RTCCNTL_BASE + 0xdc) - -/* RTC_CNTL_DIG_PAD_HOLD : R/W; bitpos: [31:0]; default: 0; - * configure digtal pad hold - */ - -#define RTC_CNTL_DIG_PAD_HOLD 0xffffffff -#define RTC_CNTL_DIG_PAD_HOLD_M (RTC_CNTL_DIG_PAD_HOLD_V << RTC_CNTL_DIG_PAD_HOLD_S) -#define RTC_CNTL_DIG_PAD_HOLD_V 0xffffffff -#define RTC_CNTL_DIG_PAD_HOLD_S 0 - -/* RTC_CNTL_RTC_EXT_WAKEUP1_REG register - * configure ext1 wakeup - */ - -#define RTC_CNTL_RTC_EXT_WAKEUP1_REG (DR_REG_RTCCNTL_BASE + 0xe0) - -/* RTC_CNTL_EXT_WAKEUP1_STATUS_CLR : WO; bitpos: [22]; default: 0; - * clear ext wakeup1 status - */ - -#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR (BIT(22)) -#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_M (RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_V << RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_S) -#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_V 0x00000001 -#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_S 22 - -/* RTC_CNTL_EXT_WAKEUP1_SEL : R/W; bitpos: [21:0]; default: 0; - * Bitmap to select RTC pads for ext wakeup1 - */ - -#define RTC_CNTL_EXT_WAKEUP1_SEL 0x003fffff -#define RTC_CNTL_EXT_WAKEUP1_SEL_M (RTC_CNTL_EXT_WAKEUP1_SEL_V << RTC_CNTL_EXT_WAKEUP1_SEL_S) -#define RTC_CNTL_EXT_WAKEUP1_SEL_V 0x003fffff -#define RTC_CNTL_EXT_WAKEUP1_SEL_S 0 - -/* RTC_CNTL_RTC_EXT_WAKEUP1_STATUS_REG register - * check ext wakeup1 status - */ - -#define RTC_CNTL_RTC_EXT_WAKEUP1_STATUS_REG (DR_REG_RTCCNTL_BASE + 0xe4) - -/* RTC_CNTL_EXT_WAKEUP1_STATUS : RO; bitpos: [21:0]; default: 0; - * ext wakeup1 status - */ - -#define RTC_CNTL_EXT_WAKEUP1_STATUS 0x003fffff -#define RTC_CNTL_EXT_WAKEUP1_STATUS_M (RTC_CNTL_EXT_WAKEUP1_STATUS_V << RTC_CNTL_EXT_WAKEUP1_STATUS_S) -#define RTC_CNTL_EXT_WAKEUP1_STATUS_V 0x003fffff -#define RTC_CNTL_EXT_WAKEUP1_STATUS_S 0 - -/* RTC_CNTL_RTC_BROWN_OUT_REG register - * configure brownout - */ - -#define RTC_CNTL_RTC_BROWN_OUT_REG (DR_REG_RTCCNTL_BASE + 0xe8) - -/* RTC_CNTL_RTC_BROWN_OUT_DET : RO; bitpos: [31]; default: 0; - * get brown out detect - */ - -#define RTC_CNTL_RTC_BROWN_OUT_DET (BIT(31)) -#define RTC_CNTL_RTC_BROWN_OUT_DET_M (RTC_CNTL_RTC_BROWN_OUT_DET_V << RTC_CNTL_RTC_BROWN_OUT_DET_S) -#define RTC_CNTL_RTC_BROWN_OUT_DET_V 0x00000001 -#define RTC_CNTL_RTC_BROWN_OUT_DET_S 31 - -/* RTC_CNTL_BROWN_OUT_ENA : R/W; bitpos: [30]; default: 1; - * enable brown out - */ - -#define RTC_CNTL_BROWN_OUT_ENA (BIT(30)) -#define RTC_CNTL_BROWN_OUT_ENA_M (RTC_CNTL_BROWN_OUT_ENA_V << RTC_CNTL_BROWN_OUT_ENA_S) -#define RTC_CNTL_BROWN_OUT_ENA_V 0x00000001 -#define RTC_CNTL_BROWN_OUT_ENA_S 30 - -/* RTC_CNTL_BROWN_OUT_CNT_CLR : WO; bitpos: [29]; default: 0; - * clear brown out counter - */ - -#define RTC_CNTL_BROWN_OUT_CNT_CLR (BIT(29)) -#define RTC_CNTL_BROWN_OUT_CNT_CLR_M (RTC_CNTL_BROWN_OUT_CNT_CLR_V << RTC_CNTL_BROWN_OUT_CNT_CLR_S) -#define RTC_CNTL_BROWN_OUT_CNT_CLR_V 0x00000001 -#define RTC_CNTL_BROWN_OUT_CNT_CLR_S 29 - -/* RTC_CNTL_BROWN_OUT_ANA_RST_EN : R/W; bitpos: [28]; default: 0; - * enable brown out reset en - */ - -#define RTC_CNTL_BROWN_OUT_ANA_RST_EN (BIT(28)) -#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_M (RTC_CNTL_BROWN_OUT_ANA_RST_EN_V << RTC_CNTL_BROWN_OUT_ANA_RST_EN_S) -#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_V 0x00000001 -#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_S 28 - -/* RTC_CNTL_BROWN_OUT_RST_SEL : R/W; bitpos: [27]; default: 0; - * 1: 4-pos reset, 0: sys_reset - */ - -#define RTC_CNTL_BROWN_OUT_RST_SEL (BIT(27)) -#define RTC_CNTL_BROWN_OUT_RST_SEL_M (RTC_CNTL_BROWN_OUT_RST_SEL_V << RTC_CNTL_BROWN_OUT_RST_SEL_S) -#define RTC_CNTL_BROWN_OUT_RST_SEL_V 0x00000001 -#define RTC_CNTL_BROWN_OUT_RST_SEL_S 27 - -/* RTC_CNTL_BROWN_OUT_RST_ENA : R/W; bitpos: [26]; default: 0; - * enable brown out reset - */ - -#define RTC_CNTL_BROWN_OUT_RST_ENA (BIT(26)) -#define RTC_CNTL_BROWN_OUT_RST_ENA_M (RTC_CNTL_BROWN_OUT_RST_ENA_V << RTC_CNTL_BROWN_OUT_RST_ENA_S) -#define RTC_CNTL_BROWN_OUT_RST_ENA_V 0x00000001 -#define RTC_CNTL_BROWN_OUT_RST_ENA_S 26 - -/* RTC_CNTL_BROWN_OUT_RST_WAIT : R/W; bitpos: [25:16]; default: 1023; - * brown out reset wait cycles - */ - -#define RTC_CNTL_BROWN_OUT_RST_WAIT 0x000003ff -#define RTC_CNTL_BROWN_OUT_RST_WAIT_M (RTC_CNTL_BROWN_OUT_RST_WAIT_V << RTC_CNTL_BROWN_OUT_RST_WAIT_S) -#define RTC_CNTL_BROWN_OUT_RST_WAIT_V 0x000003ff -#define RTC_CNTL_BROWN_OUT_RST_WAIT_S 16 - -/* RTC_CNTL_BROWN_OUT_PD_RF_ENA : R/W; bitpos: [15]; default: 0; - * enable power down RF when brown out happens - */ - -#define RTC_CNTL_BROWN_OUT_PD_RF_ENA (BIT(15)) -#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_M (RTC_CNTL_BROWN_OUT_PD_RF_ENA_V << RTC_CNTL_BROWN_OUT_PD_RF_ENA_S) -#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_V 0x00000001 -#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_S 15 - -/* RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA : R/W; bitpos: [14]; default: 0; - * enable close flash when brown out happens - */ - -#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA (BIT(14)) -#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_M (RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_V << RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_S) -#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_V 0x00000001 -#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_S 14 - -/* RTC_CNTL_BROWN_OUT_INT_WAIT : R/W; bitpos: [13:4]; default: 1; - * brown out interrupt wait cycles - */ - -#define RTC_CNTL_BROWN_OUT_INT_WAIT 0x000003ff -#define RTC_CNTL_BROWN_OUT_INT_WAIT_M (RTC_CNTL_BROWN_OUT_INT_WAIT_V << RTC_CNTL_BROWN_OUT_INT_WAIT_S) -#define RTC_CNTL_BROWN_OUT_INT_WAIT_V 0x000003ff -#define RTC_CNTL_BROWN_OUT_INT_WAIT_S 4 - -/* RTC_CNTL_RTC_TIME_LOW1_REG register - * RTC timer low 32 bits - */ - -#define RTC_CNTL_RTC_TIME_LOW1_REG (DR_REG_RTCCNTL_BASE + 0xec) - -/* RTC_CNTL_RTC_TIMER_VALUE1_LOW : RO; bitpos: [31:0]; default: 0; - * RTC timer low 32 bits - */ - -#define RTC_CNTL_RTC_TIMER_VALUE1_LOW 0xffffffff -#define RTC_CNTL_RTC_TIMER_VALUE1_LOW_M (RTC_CNTL_RTC_TIMER_VALUE1_LOW_V << RTC_CNTL_RTC_TIMER_VALUE1_LOW_S) -#define RTC_CNTL_RTC_TIMER_VALUE1_LOW_V 0xffffffff -#define RTC_CNTL_RTC_TIMER_VALUE1_LOW_S 0 - -/* RTC_CNTL_RTC_TIME_HIGH1_REG register - * RTC timer high 16 bits - */ - -#define RTC_CNTL_RTC_TIME_HIGH1_REG (DR_REG_RTCCNTL_BASE + 0xf0) - -/* RTC_CNTL_RTC_TIMER_VALUE1_HIGH : RO; bitpos: [15:0]; default: 0; - * RTC timer high 16 bits - */ - -#define RTC_CNTL_RTC_TIMER_VALUE1_HIGH 0x0000ffff -#define RTC_CNTL_RTC_TIMER_VALUE1_HIGH_M (RTC_CNTL_RTC_TIMER_VALUE1_HIGH_V << RTC_CNTL_RTC_TIMER_VALUE1_HIGH_S) -#define RTC_CNTL_RTC_TIMER_VALUE1_HIGH_V 0x0000ffff -#define RTC_CNTL_RTC_TIMER_VALUE1_HIGH_S 0 - -/* RTC_CNTL_RTC_XTAL32K_CLK_FACTOR_REG register - * xtal 32k watch dog backup clock factor - */ - -#define RTC_CNTL_RTC_XTAL32K_CLK_FACTOR_REG (DR_REG_RTCCNTL_BASE + 0xf4) - -/* RTC_CNTL_XTAL32K_CLK_FACTOR : R/W; bitpos: [31:0]; default: 0; - * xtal 32k watch dog backup clock factor - */ - -#define RTC_CNTL_XTAL32K_CLK_FACTOR 0xffffffff -#define RTC_CNTL_XTAL32K_CLK_FACTOR_M (RTC_CNTL_XTAL32K_CLK_FACTOR_V << RTC_CNTL_XTAL32K_CLK_FACTOR_S) -#define RTC_CNTL_XTAL32K_CLK_FACTOR_V 0xffffffff -#define RTC_CNTL_XTAL32K_CLK_FACTOR_S 0 - -/* RTC_CNTL_RTC_XTAL32K_CONF_REG register - * configure xtal32k - */ - -#define RTC_CNTL_RTC_XTAL32K_CONF_REG (DR_REG_RTCCNTL_BASE + 0xf8) - -/* RTC_CNTL_XTAL32K_STABLE_THRES : R/W; bitpos: [31:28]; default: 0; - * if restarted xtal32k period is smaller than this, it is regarded as stable - */ - -#define RTC_CNTL_XTAL32K_STABLE_THRES 0x0000000f -#define RTC_CNTL_XTAL32K_STABLE_THRES_M (RTC_CNTL_XTAL32K_STABLE_THRES_V << RTC_CNTL_XTAL32K_STABLE_THRES_S) -#define RTC_CNTL_XTAL32K_STABLE_THRES_V 0x0000000f -#define RTC_CNTL_XTAL32K_STABLE_THRES_S 28 - -/* RTC_CNTL_XTAL32K_WDT_TIMEOUT : R/W; bitpos: [27:20]; default: 255; - * If no clock detected for this amount of time 32k is regarded as dead - */ - -#define RTC_CNTL_XTAL32K_WDT_TIMEOUT 0x000000ff -#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_M (RTC_CNTL_XTAL32K_WDT_TIMEOUT_V << RTC_CNTL_XTAL32K_WDT_TIMEOUT_S) -#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_V 0x000000ff -#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_S 20 - -/* RTC_CNTL_XTAL32K_RESTART_WAIT : R/W; bitpos: [19:4]; default: 0; - * cycles to wait to repower on xtal 32k - */ - -#define RTC_CNTL_XTAL32K_RESTART_WAIT 0x0000ffff -#define RTC_CNTL_XTAL32K_RESTART_WAIT_M (RTC_CNTL_XTAL32K_RESTART_WAIT_V << RTC_CNTL_XTAL32K_RESTART_WAIT_S) -#define RTC_CNTL_XTAL32K_RESTART_WAIT_V 0x0000ffff -#define RTC_CNTL_XTAL32K_RESTART_WAIT_S 4 - -/* RTC_CNTL_XTAL32K_RETURN_WAIT : R/W; bitpos: [3:0]; default: 0; - * cycles to wait to return normal xtal 32k - */ - -#define RTC_CNTL_XTAL32K_RETURN_WAIT 0x0000000f -#define RTC_CNTL_XTAL32K_RETURN_WAIT_M (RTC_CNTL_XTAL32K_RETURN_WAIT_V << RTC_CNTL_XTAL32K_RETURN_WAIT_S) -#define RTC_CNTL_XTAL32K_RETURN_WAIT_V 0x0000000f -#define RTC_CNTL_XTAL32K_RETURN_WAIT_S 0 - -/* RTC_CNTL_RTC_ULP_CP_TIMER_REG register - * configure ulp - */ - -#define RTC_CNTL_RTC_ULP_CP_TIMER_REG (DR_REG_RTCCNTL_BASE + 0xfc) - -/* RTC_CNTL_ULP_CP_SLP_TIMER_EN : R/W; bitpos: [31]; default: 0; - * ULP-coprocessor timer enable bit - */ - -#define RTC_CNTL_ULP_CP_SLP_TIMER_EN (BIT(31)) -#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_M (RTC_CNTL_ULP_CP_SLP_TIMER_EN_V << RTC_CNTL_ULP_CP_SLP_TIMER_EN_S) -#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_V 0x00000001 -#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_S 31 - -/* RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR : WO; bitpos: [30]; default: 0; - * ULP-coprocessor wakeup by GPIO state clear - */ - -#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR (BIT(30)) -#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_M (RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_V << RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_S) -#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_V 0x00000001 -#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_S 30 - -/* RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA : R/W; bitpos: [29]; default: 0; - * ULP-coprocessor wakeup by GPIO enable - */ - -#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA (BIT(29)) -#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_M (RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_V << RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_S) -#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_V 0x00000001 -#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_S 29 - -/* RTC_CNTL_ULP_CP_PC_INIT : R/W; bitpos: [10:0]; default: 0; - * ULP-coprocessor PC initial address - */ - -#define RTC_CNTL_ULP_CP_PC_INIT 0x000007ff -#define RTC_CNTL_ULP_CP_PC_INIT_M (RTC_CNTL_ULP_CP_PC_INIT_V << RTC_CNTL_ULP_CP_PC_INIT_S) -#define RTC_CNTL_ULP_CP_PC_INIT_V 0x000007ff -#define RTC_CNTL_ULP_CP_PC_INIT_S 0 - -/* RTC_CNTL_RTC_ULP_CP_CTRL_REG register - * configure ulp - */ - -#define RTC_CNTL_RTC_ULP_CP_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x100) - -/* RTC_CNTL_ULP_CP_START_TOP : R/W; bitpos: [31]; default: 0; - * Write 1 to start ULP-coprocessor - */ - -#define RTC_CNTL_ULP_CP_START_TOP (BIT(31)) -#define RTC_CNTL_ULP_CP_START_TOP_M (RTC_CNTL_ULP_CP_START_TOP_V << RTC_CNTL_ULP_CP_START_TOP_S) -#define RTC_CNTL_ULP_CP_START_TOP_V 0x00000001 -#define RTC_CNTL_ULP_CP_START_TOP_S 31 - -/* RTC_CNTL_ULP_CP_FORCE_START_TOP : R/W; bitpos: [30]; default: 0; - * 1: ULP-coprocessor is started by SW - */ - -#define RTC_CNTL_ULP_CP_FORCE_START_TOP (BIT(30)) -#define RTC_CNTL_ULP_CP_FORCE_START_TOP_M (RTC_CNTL_ULP_CP_FORCE_START_TOP_V << RTC_CNTL_ULP_CP_FORCE_START_TOP_S) -#define RTC_CNTL_ULP_CP_FORCE_START_TOP_V 0x00000001 -#define RTC_CNTL_ULP_CP_FORCE_START_TOP_S 30 - -/* RTC_CNTL_ULP_CP_RESET : R/W; bitpos: [29]; default: 0; - * ulp coprocessor clk software reset - */ - -#define RTC_CNTL_ULP_CP_RESET (BIT(29)) -#define RTC_CNTL_ULP_CP_RESET_M (RTC_CNTL_ULP_CP_RESET_V << RTC_CNTL_ULP_CP_RESET_S) -#define RTC_CNTL_ULP_CP_RESET_V 0x00000001 -#define RTC_CNTL_ULP_CP_RESET_S 29 - -/* RTC_CNTL_ULP_CP_CLK_FO : R/W; bitpos: [28]; default: 0; - * ulp coprocessor clk force on - */ - -#define RTC_CNTL_ULP_CP_CLK_FO (BIT(28)) -#define RTC_CNTL_ULP_CP_CLK_FO_M (RTC_CNTL_ULP_CP_CLK_FO_V << RTC_CNTL_ULP_CP_CLK_FO_S) -#define RTC_CNTL_ULP_CP_CLK_FO_V 0x00000001 -#define RTC_CNTL_ULP_CP_CLK_FO_S 28 - -/* RTC_CNTL_ULP_CP_MEM_OFFST_CLR : WO; bitpos: [22]; default: 0; - * No public - */ - -#define RTC_CNTL_ULP_CP_MEM_OFFST_CLR (BIT(22)) -#define RTC_CNTL_ULP_CP_MEM_OFFST_CLR_M (RTC_CNTL_ULP_CP_MEM_OFFST_CLR_V << RTC_CNTL_ULP_CP_MEM_OFFST_CLR_S) -#define RTC_CNTL_ULP_CP_MEM_OFFST_CLR_V 0x00000001 -#define RTC_CNTL_ULP_CP_MEM_OFFST_CLR_S 22 - -/* RTC_CNTL_ULP_CP_MEM_ADDR_SIZE : R/W; bitpos: [21:11]; default: 512; - * No public - */ - -#define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE 0x000007ff -#define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_M (RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_V << RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_S) -#define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_V 0x000007ff -#define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_S 11 - -/* RTC_CNTL_ULP_CP_MEM_ADDR_INIT : R/W; bitpos: [10:0]; default: 512; - * No public - */ - -#define RTC_CNTL_ULP_CP_MEM_ADDR_INIT 0x000007ff -#define RTC_CNTL_ULP_CP_MEM_ADDR_INIT_M (RTC_CNTL_ULP_CP_MEM_ADDR_INIT_V << RTC_CNTL_ULP_CP_MEM_ADDR_INIT_S) -#define RTC_CNTL_ULP_CP_MEM_ADDR_INIT_V 0x000007ff -#define RTC_CNTL_ULP_CP_MEM_ADDR_INIT_S 0 - -/* RTC_CNTL_RTC_COCPU_CTRL_REG register - * configure ulp-riscv - */ - -#define RTC_CNTL_RTC_COCPU_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x104) - -/* RTC_CNTL_COCPU_CLKGATE_EN : R/W; bitpos: [27]; default: 0; - * open ulp-riscv clk gate - */ - -#define RTC_CNTL_COCPU_CLKGATE_EN (BIT(27)) -#define RTC_CNTL_COCPU_CLKGATE_EN_M (RTC_CNTL_COCPU_CLKGATE_EN_V << RTC_CNTL_COCPU_CLKGATE_EN_S) -#define RTC_CNTL_COCPU_CLKGATE_EN_V 0x00000001 -#define RTC_CNTL_COCPU_CLKGATE_EN_S 27 - -/* RTC_CNTL_COCPU_SW_INT_TRIGGER : WO; bitpos: [26]; default: 0; - * trigger cocpu register interrupt - */ - -#define RTC_CNTL_COCPU_SW_INT_TRIGGER (BIT(26)) -#define RTC_CNTL_COCPU_SW_INT_TRIGGER_M (RTC_CNTL_COCPU_SW_INT_TRIGGER_V << RTC_CNTL_COCPU_SW_INT_TRIGGER_S) -#define RTC_CNTL_COCPU_SW_INT_TRIGGER_V 0x00000001 -#define RTC_CNTL_COCPU_SW_INT_TRIGGER_S 26 - -/* RTC_CNTL_COCPU_DONE : R/W; bitpos: [25]; default: 0; - * done signal used by riscv to control timer. - */ - -#define RTC_CNTL_COCPU_DONE (BIT(25)) -#define RTC_CNTL_COCPU_DONE_M (RTC_CNTL_COCPU_DONE_V << RTC_CNTL_COCPU_DONE_S) -#define RTC_CNTL_COCPU_DONE_V 0x00000001 -#define RTC_CNTL_COCPU_DONE_S 25 - -/* RTC_CNTL_COCPU_DONE_FORCE : R/W; bitpos: [24]; default: 0; - * 1: select riscv done 0: select ulp done - */ - -#define RTC_CNTL_COCPU_DONE_FORCE (BIT(24)) -#define RTC_CNTL_COCPU_DONE_FORCE_M (RTC_CNTL_COCPU_DONE_FORCE_V << RTC_CNTL_COCPU_DONE_FORCE_S) -#define RTC_CNTL_COCPU_DONE_FORCE_V 0x00000001 -#define RTC_CNTL_COCPU_DONE_FORCE_S 24 - -/* RTC_CNTL_COCPU_SEL : R/W; bitpos: [23]; default: 1; - * 1: old ULP 0: new riscV - */ - -#define RTC_CNTL_COCPU_SEL (BIT(23)) -#define RTC_CNTL_COCPU_SEL_M (RTC_CNTL_COCPU_SEL_V << RTC_CNTL_COCPU_SEL_S) -#define RTC_CNTL_COCPU_SEL_V 0x00000001 -#define RTC_CNTL_COCPU_SEL_S 23 - -/* RTC_CNTL_COCPU_SHUT_RESET_EN : R/W; bitpos: [22]; default: 0; - * to reset cocpu - */ - -#define RTC_CNTL_COCPU_SHUT_RESET_EN (BIT(22)) -#define RTC_CNTL_COCPU_SHUT_RESET_EN_M (RTC_CNTL_COCPU_SHUT_RESET_EN_V << RTC_CNTL_COCPU_SHUT_RESET_EN_S) -#define RTC_CNTL_COCPU_SHUT_RESET_EN_V 0x00000001 -#define RTC_CNTL_COCPU_SHUT_RESET_EN_S 22 - -/* RTC_CNTL_COCPU_SHUT_2_CLK_DIS : R/W; bitpos: [21:14]; default: 40; - * time from shut cocpu to disable clk - */ - -#define RTC_CNTL_COCPU_SHUT_2_CLK_DIS 0x000000ff -#define RTC_CNTL_COCPU_SHUT_2_CLK_DIS_M (RTC_CNTL_COCPU_SHUT_2_CLK_DIS_V << RTC_CNTL_COCPU_SHUT_2_CLK_DIS_S) -#define RTC_CNTL_COCPU_SHUT_2_CLK_DIS_V 0x000000ff -#define RTC_CNTL_COCPU_SHUT_2_CLK_DIS_S 14 - -/* RTC_CNTL_COCPU_SHUT : R/W; bitpos: [13]; default: 0; - * to shut cocpu - */ - -#define RTC_CNTL_COCPU_SHUT (BIT(13)) -#define RTC_CNTL_COCPU_SHUT_M (RTC_CNTL_COCPU_SHUT_V << RTC_CNTL_COCPU_SHUT_S) -#define RTC_CNTL_COCPU_SHUT_V 0x00000001 -#define RTC_CNTL_COCPU_SHUT_S 13 - -/* RTC_CNTL_COCPU_START_2_INTR_EN : R/W; bitpos: [12:7]; default: 16; - * time from start cocpu to give start interrupt - */ - -#define RTC_CNTL_COCPU_START_2_INTR_EN 0x0000003f -#define RTC_CNTL_COCPU_START_2_INTR_EN_M (RTC_CNTL_COCPU_START_2_INTR_EN_V << RTC_CNTL_COCPU_START_2_INTR_EN_S) -#define RTC_CNTL_COCPU_START_2_INTR_EN_V 0x0000003f -#define RTC_CNTL_COCPU_START_2_INTR_EN_S 7 - -/* RTC_CNTL_COCPU_START_2_RESET_DIS : R/W; bitpos: [6:1]; default: 8; - * time from start cocpu to pull down reset - */ - -#define RTC_CNTL_COCPU_START_2_RESET_DIS 0x0000003f -#define RTC_CNTL_COCPU_START_2_RESET_DIS_M (RTC_CNTL_COCPU_START_2_RESET_DIS_V << RTC_CNTL_COCPU_START_2_RESET_DIS_S) -#define RTC_CNTL_COCPU_START_2_RESET_DIS_V 0x0000003f -#define RTC_CNTL_COCPU_START_2_RESET_DIS_S 1 - -/* RTC_CNTL_COCPU_CLK_FO : R/W; bitpos: [0]; default: 0; - * cocpu clk force on - */ - -#define RTC_CNTL_COCPU_CLK_FO (BIT(0)) -#define RTC_CNTL_COCPU_CLK_FO_M (RTC_CNTL_COCPU_CLK_FO_V << RTC_CNTL_COCPU_CLK_FO_S) -#define RTC_CNTL_COCPU_CLK_FO_V 0x00000001 -#define RTC_CNTL_COCPU_CLK_FO_S 0 - -/* RTC_CNTL_RTC_TOUCH_CTRL1_REG register - * configure touch controller - */ - -#define RTC_CNTL_RTC_TOUCH_CTRL1_REG (DR_REG_RTCCNTL_BASE + 0x108) - -/* RTC_CNTL_TOUCH_MEAS_NUM : R/W; bitpos: [31:16]; default: 4096; - * the meas length (in 8MHz) - */ - -#define RTC_CNTL_TOUCH_MEAS_NUM 0x0000ffff -#define RTC_CNTL_TOUCH_MEAS_NUM_M (RTC_CNTL_TOUCH_MEAS_NUM_V << RTC_CNTL_TOUCH_MEAS_NUM_S) -#define RTC_CNTL_TOUCH_MEAS_NUM_V 0x0000ffff -#define RTC_CNTL_TOUCH_MEAS_NUM_S 16 - -/* RTC_CNTL_TOUCH_SLEEP_CYCLES : R/W; bitpos: [15:0]; default: 256; - * sleep cycles for timer - */ - -#define RTC_CNTL_TOUCH_SLEEP_CYCLES 0x0000ffff -#define RTC_CNTL_TOUCH_SLEEP_CYCLES_M (RTC_CNTL_TOUCH_SLEEP_CYCLES_V << RTC_CNTL_TOUCH_SLEEP_CYCLES_S) -#define RTC_CNTL_TOUCH_SLEEP_CYCLES_V 0x0000ffff -#define RTC_CNTL_TOUCH_SLEEP_CYCLES_S 0 - -/* RTC_CNTL_RTC_TOUCH_CTRL2_REG register - * configure touch controller - */ - -#define RTC_CNTL_RTC_TOUCH_CTRL2_REG (DR_REG_RTCCNTL_BASE + 0x10c) - -/* RTC_CNTL_TOUCH_CLKGATE_EN : R/W; bitpos: [31]; default: 0; - * touch clock enable - */ - -#define RTC_CNTL_TOUCH_CLKGATE_EN (BIT(31)) -#define RTC_CNTL_TOUCH_CLKGATE_EN_M (RTC_CNTL_TOUCH_CLKGATE_EN_V << RTC_CNTL_TOUCH_CLKGATE_EN_S) -#define RTC_CNTL_TOUCH_CLKGATE_EN_V 0x00000001 -#define RTC_CNTL_TOUCH_CLKGATE_EN_S 31 - -/* RTC_CNTL_TOUCH_CLK_FO : R/W; bitpos: [30]; default: 0; - * touch clock force on - */ - -#define RTC_CNTL_TOUCH_CLK_FO (BIT(30)) -#define RTC_CNTL_TOUCH_CLK_FO_M (RTC_CNTL_TOUCH_CLK_FO_V << RTC_CNTL_TOUCH_CLK_FO_S) -#define RTC_CNTL_TOUCH_CLK_FO_V 0x00000001 -#define RTC_CNTL_TOUCH_CLK_FO_S 30 - -/* RTC_CNTL_TOUCH_RESET : R/W; bitpos: [29]; default: 0; - * reset upgrade touch - */ - -#define RTC_CNTL_TOUCH_RESET (BIT(29)) -#define RTC_CNTL_TOUCH_RESET_M (RTC_CNTL_TOUCH_RESET_V << RTC_CNTL_TOUCH_RESET_S) -#define RTC_CNTL_TOUCH_RESET_V 0x00000001 -#define RTC_CNTL_TOUCH_RESET_S 29 - -/* RTC_CNTL_TOUCH_TIMER_FORCE_DONE : R/W; bitpos: [28:27]; default: 0; - * force touch timer done - */ - -#define RTC_CNTL_TOUCH_TIMER_FORCE_DONE 0x00000003 -#define RTC_CNTL_TOUCH_TIMER_FORCE_DONE_M (RTC_CNTL_TOUCH_TIMER_FORCE_DONE_V << RTC_CNTL_TOUCH_TIMER_FORCE_DONE_S) -#define RTC_CNTL_TOUCH_TIMER_FORCE_DONE_V 0x00000003 -#define RTC_CNTL_TOUCH_TIMER_FORCE_DONE_S 27 - -/* RTC_CNTL_TOUCH_SLP_CYC_DIV : R/W; bitpos: [26:25]; default: 0; - * when a touch pad is active sleep cycle could be divided by this number - */ - -#define RTC_CNTL_TOUCH_SLP_CYC_DIV 0x00000003 -#define RTC_CNTL_TOUCH_SLP_CYC_DIV_M (RTC_CNTL_TOUCH_SLP_CYC_DIV_V << RTC_CNTL_TOUCH_SLP_CYC_DIV_S) -#define RTC_CNTL_TOUCH_SLP_CYC_DIV_V 0x00000003 -#define RTC_CNTL_TOUCH_SLP_CYC_DIV_S 25 - -/* RTC_CNTL_TOUCH_XPD_WAIT : R/W; bitpos: [24:17]; default: 4; - * the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD - */ - -#define RTC_CNTL_TOUCH_XPD_WAIT 0x000000ff -#define RTC_CNTL_TOUCH_XPD_WAIT_M (RTC_CNTL_TOUCH_XPD_WAIT_V << RTC_CNTL_TOUCH_XPD_WAIT_S) -#define RTC_CNTL_TOUCH_XPD_WAIT_V 0x000000ff -#define RTC_CNTL_TOUCH_XPD_WAIT_S 17 - -/* RTC_CNTL_TOUCH_START_FORCE : R/W; bitpos: [16]; default: 0; - * 1: to start touch fsm by SW - */ - -#define RTC_CNTL_TOUCH_START_FORCE (BIT(16)) -#define RTC_CNTL_TOUCH_START_FORCE_M (RTC_CNTL_TOUCH_START_FORCE_V << RTC_CNTL_TOUCH_START_FORCE_S) -#define RTC_CNTL_TOUCH_START_FORCE_V 0x00000001 -#define RTC_CNTL_TOUCH_START_FORCE_S 16 - -/* RTC_CNTL_TOUCH_START_EN : R/W; bitpos: [15]; default: 0; - * 1: start touch fsm - */ - -#define RTC_CNTL_TOUCH_START_EN (BIT(15)) -#define RTC_CNTL_TOUCH_START_EN_M (RTC_CNTL_TOUCH_START_EN_V << RTC_CNTL_TOUCH_START_EN_S) -#define RTC_CNTL_TOUCH_START_EN_V 0x00000001 -#define RTC_CNTL_TOUCH_START_EN_S 15 - -/* RTC_CNTL_TOUCH_START_FSM_EN : R/W; bitpos: [14]; default: 1; - * 1: TOUCH_START & TOUCH_XPD is controlled by touch fsm - */ - -#define RTC_CNTL_TOUCH_START_FSM_EN (BIT(14)) -#define RTC_CNTL_TOUCH_START_FSM_EN_M (RTC_CNTL_TOUCH_START_FSM_EN_V << RTC_CNTL_TOUCH_START_FSM_EN_S) -#define RTC_CNTL_TOUCH_START_FSM_EN_V 0x00000001 -#define RTC_CNTL_TOUCH_START_FSM_EN_S 14 - -/* RTC_CNTL_TOUCH_SLP_TIMER_EN : R/W; bitpos: [13]; default: 0; - * touch timer enable bit - */ - -#define RTC_CNTL_TOUCH_SLP_TIMER_EN (BIT(13)) -#define RTC_CNTL_TOUCH_SLP_TIMER_EN_M (RTC_CNTL_TOUCH_SLP_TIMER_EN_V << RTC_CNTL_TOUCH_SLP_TIMER_EN_S) -#define RTC_CNTL_TOUCH_SLP_TIMER_EN_V 0x00000001 -#define RTC_CNTL_TOUCH_SLP_TIMER_EN_S 13 - -/* RTC_CNTL_TOUCH_DBIAS : R/W; bitpos: [12]; default: 0; - * 1:use self bias 0:use bandgap bias - */ - -#define RTC_CNTL_TOUCH_DBIAS (BIT(12)) -#define RTC_CNTL_TOUCH_DBIAS_M (RTC_CNTL_TOUCH_DBIAS_V << RTC_CNTL_TOUCH_DBIAS_S) -#define RTC_CNTL_TOUCH_DBIAS_V 0x00000001 -#define RTC_CNTL_TOUCH_DBIAS_S 12 - -/* RTC_CNTL_TOUCH_REFC : R/W; bitpos: [11:9]; default: 0; - * TOUCH pad0 reference cap - */ - -#define RTC_CNTL_TOUCH_REFC 0x00000007 -#define RTC_CNTL_TOUCH_REFC_M (RTC_CNTL_TOUCH_REFC_V << RTC_CNTL_TOUCH_REFC_S) -#define RTC_CNTL_TOUCH_REFC_V 0x00000007 -#define RTC_CNTL_TOUCH_REFC_S 9 - -/* RTC_CNTL_TOUCH_XPD_BIAS : R/W; bitpos: [8]; default: 0; - * TOUCH_XPD_BIAS - */ - -#define RTC_CNTL_TOUCH_XPD_BIAS (BIT(8)) -#define RTC_CNTL_TOUCH_XPD_BIAS_M (RTC_CNTL_TOUCH_XPD_BIAS_V << RTC_CNTL_TOUCH_XPD_BIAS_S) -#define RTC_CNTL_TOUCH_XPD_BIAS_V 0x00000001 -#define RTC_CNTL_TOUCH_XPD_BIAS_S 8 - -/* RTC_CNTL_TOUCH_DREFH : R/W; bitpos: [7:6]; default: 3; - * TOUCH_DREFH - */ - -#define RTC_CNTL_TOUCH_DREFH 0x00000003 -#define RTC_CNTL_TOUCH_DREFH_M (RTC_CNTL_TOUCH_DREFH_V << RTC_CNTL_TOUCH_DREFH_S) -#define RTC_CNTL_TOUCH_DREFH_V 0x00000003 -#define RTC_CNTL_TOUCH_DREFH_S 6 - -/* RTC_CNTL_TOUCH_DREFL : R/W; bitpos: [5:4]; default: 0; - * TOUCH_DREFL - */ - -#define RTC_CNTL_TOUCH_DREFL 0x00000003 -#define RTC_CNTL_TOUCH_DREFL_M (RTC_CNTL_TOUCH_DREFL_V << RTC_CNTL_TOUCH_DREFL_S) -#define RTC_CNTL_TOUCH_DREFL_V 0x00000003 -#define RTC_CNTL_TOUCH_DREFL_S 4 - -/* RTC_CNTL_TOUCH_DRANGE : R/W; bitpos: [3:2]; default: 3; - * TOUCH_DRANGE - */ - -#define RTC_CNTL_TOUCH_DRANGE 0x00000003 -#define RTC_CNTL_TOUCH_DRANGE_M (RTC_CNTL_TOUCH_DRANGE_V << RTC_CNTL_TOUCH_DRANGE_S) -#define RTC_CNTL_TOUCH_DRANGE_V 0x00000003 -#define RTC_CNTL_TOUCH_DRANGE_S 2 - -/* RTC_CNTL_RTC_TOUCH_SCAN_CTRL_REG register - * configure touch controller - */ - -#define RTC_CNTL_RTC_TOUCH_SCAN_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x110) - -/* RTC_CNTL_TOUCH_OUT_RING : R/W; bitpos: [31:28]; default: 15; - * select out ring pad - */ - -#define RTC_CNTL_TOUCH_OUT_RING 0x0000000f -#define RTC_CNTL_TOUCH_OUT_RING_M (RTC_CNTL_TOUCH_OUT_RING_V << RTC_CNTL_TOUCH_OUT_RING_S) -#define RTC_CNTL_TOUCH_OUT_RING_V 0x0000000f -#define RTC_CNTL_TOUCH_OUT_RING_S 28 - -/* RTC_CNTL_TOUCH_BUFDRV : R/W; bitpos: [27:25]; default: 0; - * touch7 buffer driver strength - */ - -#define RTC_CNTL_TOUCH_BUFDRV 0x00000007 -#define RTC_CNTL_TOUCH_BUFDRV_M (RTC_CNTL_TOUCH_BUFDRV_V << RTC_CNTL_TOUCH_BUFDRV_S) -#define RTC_CNTL_TOUCH_BUFDRV_V 0x00000007 -#define RTC_CNTL_TOUCH_BUFDRV_S 25 - -/* RTC_CNTL_TOUCH_SCAN_PAD_MAP : R/W; bitpos: [24:10]; default: 0; - * touch scan mode pad enable map - */ - -#define RTC_CNTL_TOUCH_SCAN_PAD_MAP 0x00007fff -#define RTC_CNTL_TOUCH_SCAN_PAD_MAP_M (RTC_CNTL_TOUCH_SCAN_PAD_MAP_V << RTC_CNTL_TOUCH_SCAN_PAD_MAP_S) -#define RTC_CNTL_TOUCH_SCAN_PAD_MAP_V 0x00007fff -#define RTC_CNTL_TOUCH_SCAN_PAD_MAP_S 10 - -/* RTC_CNTL_TOUCH_SHIELD_PAD_EN : R/W; bitpos: [9]; default: 0; - * touch pad14 will be used as shield - */ - -#define RTC_CNTL_TOUCH_SHIELD_PAD_EN (BIT(9)) -#define RTC_CNTL_TOUCH_SHIELD_PAD_EN_M (RTC_CNTL_TOUCH_SHIELD_PAD_EN_V << RTC_CNTL_TOUCH_SHIELD_PAD_EN_S) -#define RTC_CNTL_TOUCH_SHIELD_PAD_EN_V 0x00000001 -#define RTC_CNTL_TOUCH_SHIELD_PAD_EN_S 9 - -/* RTC_CNTL_TOUCH_INACTIVE_CONNECTION : R/W; bitpos: [8]; default: 1; - * inactive touch pads connect to 1: gnd 0: HighZ - */ - -#define RTC_CNTL_TOUCH_INACTIVE_CONNECTION (BIT(8)) -#define RTC_CNTL_TOUCH_INACTIVE_CONNECTION_M (RTC_CNTL_TOUCH_INACTIVE_CONNECTION_V << RTC_CNTL_TOUCH_INACTIVE_CONNECTION_S) -#define RTC_CNTL_TOUCH_INACTIVE_CONNECTION_V 0x00000001 -#define RTC_CNTL_TOUCH_INACTIVE_CONNECTION_S 8 - -/* RTC_CNTL_TOUCH_DENOISE_EN : R/W; bitpos: [2]; default: 0; - * touch pad0 will be used to de-noise - */ - -#define RTC_CNTL_TOUCH_DENOISE_EN (BIT(2)) -#define RTC_CNTL_TOUCH_DENOISE_EN_M (RTC_CNTL_TOUCH_DENOISE_EN_V << RTC_CNTL_TOUCH_DENOISE_EN_S) -#define RTC_CNTL_TOUCH_DENOISE_EN_V 0x00000001 -#define RTC_CNTL_TOUCH_DENOISE_EN_S 2 - -/* RTC_CNTL_TOUCH_DENOISE_RES : R/W; bitpos: [1:0]; default: 2; - * De-noise resolution: 12/10/8/4 bit - */ - -#define RTC_CNTL_TOUCH_DENOISE_RES 0x00000003 -#define RTC_CNTL_TOUCH_DENOISE_RES_M (RTC_CNTL_TOUCH_DENOISE_RES_V << RTC_CNTL_TOUCH_DENOISE_RES_S) -#define RTC_CNTL_TOUCH_DENOISE_RES_V 0x00000003 -#define RTC_CNTL_TOUCH_DENOISE_RES_S 0 - -/* RTC_CNTL_RTC_TOUCH_SLP_THRES_REG register - * configure touch controller - */ - -#define RTC_CNTL_RTC_TOUCH_SLP_THRES_REG (DR_REG_RTCCNTL_BASE + 0x114) - -/* RTC_CNTL_TOUCH_SLP_PAD : R/W; bitpos: [31:27]; default: 15; - * configure which pad as slp pad - */ - -#define RTC_CNTL_TOUCH_SLP_PAD 0x0000001f -#define RTC_CNTL_TOUCH_SLP_PAD_M (RTC_CNTL_TOUCH_SLP_PAD_V << RTC_CNTL_TOUCH_SLP_PAD_S) -#define RTC_CNTL_TOUCH_SLP_PAD_V 0x0000001f -#define RTC_CNTL_TOUCH_SLP_PAD_S 27 - -/* RTC_CNTL_TOUCH_SLP_APPROACH_EN : R/W; bitpos: [26]; default: 0; - * sleep pad approach function enable - */ - -#define RTC_CNTL_TOUCH_SLP_APPROACH_EN (BIT(26)) -#define RTC_CNTL_TOUCH_SLP_APPROACH_EN_M (RTC_CNTL_TOUCH_SLP_APPROACH_EN_V << RTC_CNTL_TOUCH_SLP_APPROACH_EN_S) -#define RTC_CNTL_TOUCH_SLP_APPROACH_EN_V 0x00000001 -#define RTC_CNTL_TOUCH_SLP_APPROACH_EN_S 26 - -/* RTC_CNTL_TOUCH_SLP_TH : R/W; bitpos: [21:0]; default: 0; - * the threshold for sleep touch pad - */ - -#define RTC_CNTL_TOUCH_SLP_TH 0x003fffff -#define RTC_CNTL_TOUCH_SLP_TH_M (RTC_CNTL_TOUCH_SLP_TH_V << RTC_CNTL_TOUCH_SLP_TH_S) -#define RTC_CNTL_TOUCH_SLP_TH_V 0x003fffff -#define RTC_CNTL_TOUCH_SLP_TH_S 0 - -/* RTC_CNTL_RTC_TOUCH_APPROACH_REG register - * configure touch controller - */ - -#define RTC_CNTL_RTC_TOUCH_APPROACH_REG (DR_REG_RTCCNTL_BASE + 0x118) - -/* RTC_CNTL_TOUCH_APPROACH_MEAS_TIME : R/W; bitpos: [31:24]; default: 80; - * approach pads total meas times - */ - -#define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME 0x000000ff -#define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_M (RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_V << RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_S) -#define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_V 0x000000ff -#define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_S 24 - -/* RTC_CNTL_TOUCH_SLP_CHANNEL_CLR : WO; bitpos: [23]; default: 0; - * clear touch slp channel - */ - -#define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR (BIT(23)) -#define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_M (RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_V << RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_S) -#define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_V 0x00000001 -#define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_S 23 - -/* RTC_CNTL_RTC_TOUCH_FILTER_CTRL_REG register - * configure touch controller - */ - -#define RTC_CNTL_RTC_TOUCH_FILTER_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x11c) - -/* RTC_CNTL_TOUCH_FILTER_EN : R/W; bitpos: [31]; default: 1; - * touch filter enable - */ - -#define RTC_CNTL_TOUCH_FILTER_EN (BIT(31)) -#define RTC_CNTL_TOUCH_FILTER_EN_M (RTC_CNTL_TOUCH_FILTER_EN_V << RTC_CNTL_TOUCH_FILTER_EN_S) -#define RTC_CNTL_TOUCH_FILTER_EN_V 0x00000001 -#define RTC_CNTL_TOUCH_FILTER_EN_S 31 - -/* RTC_CNTL_TOUCH_FILTER_MODE : R/W; bitpos: [30:28]; default: 1; - * 0: IIR ? 1: IIR ? 2: IIR 1/8 3: Jitter - */ - -#define RTC_CNTL_TOUCH_FILTER_MODE 0x00000007 -#define RTC_CNTL_TOUCH_FILTER_MODE_M (RTC_CNTL_TOUCH_FILTER_MODE_V << RTC_CNTL_TOUCH_FILTER_MODE_S) -#define RTC_CNTL_TOUCH_FILTER_MODE_V 0x00000007 -#define RTC_CNTL_TOUCH_FILTER_MODE_S 28 - -/* RTC_CNTL_TOUCH_DEBOUNCE : R/W; bitpos: [27:25]; default: 3; - * debounce counter - */ - -#define RTC_CNTL_TOUCH_DEBOUNCE 0x00000007 -#define RTC_CNTL_TOUCH_DEBOUNCE_M (RTC_CNTL_TOUCH_DEBOUNCE_V << RTC_CNTL_TOUCH_DEBOUNCE_S) -#define RTC_CNTL_TOUCH_DEBOUNCE_V 0x00000007 -#define RTC_CNTL_TOUCH_DEBOUNCE_S 25 - -/* RTC_CNTL_TOUCH_HYSTERESIS : R/W; bitpos: [24:23]; default: 1; - * hysteresis - */ - -#define RTC_CNTL_TOUCH_HYSTERESIS 0x00000003 -#define RTC_CNTL_TOUCH_HYSTERESIS_M (RTC_CNTL_TOUCH_HYSTERESIS_V << RTC_CNTL_TOUCH_HYSTERESIS_S) -#define RTC_CNTL_TOUCH_HYSTERESIS_V 0x00000003 -#define RTC_CNTL_TOUCH_HYSTERESIS_S 23 - -/* RTC_CNTL_TOUCH_NOISE_THRES : R/W; bitpos: [22:21]; default: 1; - * noise thres - */ - -#define RTC_CNTL_TOUCH_NOISE_THRES 0x00000003 -#define RTC_CNTL_TOUCH_NOISE_THRES_M (RTC_CNTL_TOUCH_NOISE_THRES_V << RTC_CNTL_TOUCH_NOISE_THRES_S) -#define RTC_CNTL_TOUCH_NOISE_THRES_V 0x00000003 -#define RTC_CNTL_TOUCH_NOISE_THRES_S 21 - -/* RTC_CNTL_TOUCH_NEG_NOISE_THRES : R/W; bitpos: [20:19]; default: 1; - * neg noise thres - */ - -#define RTC_CNTL_TOUCH_NEG_NOISE_THRES 0x00000003 -#define RTC_CNTL_TOUCH_NEG_NOISE_THRES_M (RTC_CNTL_TOUCH_NEG_NOISE_THRES_V << RTC_CNTL_TOUCH_NEG_NOISE_THRES_S) -#define RTC_CNTL_TOUCH_NEG_NOISE_THRES_V 0x00000003 -#define RTC_CNTL_TOUCH_NEG_NOISE_THRES_S 19 - -/* RTC_CNTL_TOUCH_NEG_NOISE_LIMIT : R/W; bitpos: [18:15]; default: 5; - * negative threshold counter limit - */ - -#define RTC_CNTL_TOUCH_NEG_NOISE_LIMIT 0x0000000f -#define RTC_CNTL_TOUCH_NEG_NOISE_LIMIT_M (RTC_CNTL_TOUCH_NEG_NOISE_LIMIT_V << RTC_CNTL_TOUCH_NEG_NOISE_LIMIT_S) -#define RTC_CNTL_TOUCH_NEG_NOISE_LIMIT_V 0x0000000f -#define RTC_CNTL_TOUCH_NEG_NOISE_LIMIT_S 15 - -/* RTC_CNTL_TOUCH_JITTER_STEP : R/W; bitpos: [14:11]; default: 1; - * touch jitter step - */ - -#define RTC_CNTL_TOUCH_JITTER_STEP 0x0000000f -#define RTC_CNTL_TOUCH_JITTER_STEP_M (RTC_CNTL_TOUCH_JITTER_STEP_V << RTC_CNTL_TOUCH_JITTER_STEP_S) -#define RTC_CNTL_TOUCH_JITTER_STEP_V 0x0000000f -#define RTC_CNTL_TOUCH_JITTER_STEP_S 11 - -/* RTC_CNTL_TOUCH_SMOOTH_LVL : R/W; bitpos: [10:9]; default: 0; - * smooth filter factor - */ - -#define RTC_CNTL_TOUCH_SMOOTH_LVL 0x00000003 -#define RTC_CNTL_TOUCH_SMOOTH_LVL_M (RTC_CNTL_TOUCH_SMOOTH_LVL_V << RTC_CNTL_TOUCH_SMOOTH_LVL_S) -#define RTC_CNTL_TOUCH_SMOOTH_LVL_V 0x00000003 -#define RTC_CNTL_TOUCH_SMOOTH_LVL_S 9 - -/* RTC_CNTL_TOUCH_BYPASS_NOISE_THRES : R/W; bitpos: [8]; default: 0; - * bypaas noise thres - */ - -#define RTC_CNTL_TOUCH_BYPASS_NOISE_THRES (BIT(8)) -#define RTC_CNTL_TOUCH_BYPASS_NOISE_THRES_M (RTC_CNTL_TOUCH_BYPASS_NOISE_THRES_V << RTC_CNTL_TOUCH_BYPASS_NOISE_THRES_S) -#define RTC_CNTL_TOUCH_BYPASS_NOISE_THRES_V 0x00000001 -#define RTC_CNTL_TOUCH_BYPASS_NOISE_THRES_S 8 - -/* RTC_CNTL_TOUCH_BYPASS_NEG_NOISE_THRES : R/W; bitpos: [7]; default: 0; - * bypass neg noise thres - */ - -#define RTC_CNTL_TOUCH_BYPASS_NEG_NOISE_THRES (BIT(7)) -#define RTC_CNTL_TOUCH_BYPASS_NEG_NOISE_THRES_M (RTC_CNTL_TOUCH_BYPASS_NEG_NOISE_THRES_V << RTC_CNTL_TOUCH_BYPASS_NEG_NOISE_THRES_S) -#define RTC_CNTL_TOUCH_BYPASS_NEG_NOISE_THRES_V 0x00000001 -#define RTC_CNTL_TOUCH_BYPASS_NEG_NOISE_THRES_S 7 - -/* RTC_CNTL_RTC_USB_CONF_REG register - * usb configure - */ - -#define RTC_CNTL_RTC_USB_CONF_REG (DR_REG_RTCCNTL_BASE + 0x120) - -/* RTC_CNTL_SW_HW_USB_PHY_SEL : R/W; bitpos: [20]; default: 0; - * reg_sw_hw_usb_phy_sel - */ - -#define RTC_CNTL_SW_HW_USB_PHY_SEL (BIT(20)) -#define RTC_CNTL_SW_HW_USB_PHY_SEL_M (RTC_CNTL_SW_HW_USB_PHY_SEL_V << RTC_CNTL_SW_HW_USB_PHY_SEL_S) -#define RTC_CNTL_SW_HW_USB_PHY_SEL_V 0x00000001 -#define RTC_CNTL_SW_HW_USB_PHY_SEL_S 20 - -/* RTC_CNTL_SW_USB_PHY_SEL : R/W; bitpos: [19]; default: 0; - * reg_sw_usb_phy_sel - */ - -#define RTC_CNTL_SW_USB_PHY_SEL (BIT(19)) -#define RTC_CNTL_SW_USB_PHY_SEL_M (RTC_CNTL_SW_USB_PHY_SEL_V << RTC_CNTL_SW_USB_PHY_SEL_S) -#define RTC_CNTL_SW_USB_PHY_SEL_V 0x00000001 -#define RTC_CNTL_SW_USB_PHY_SEL_S 19 - -/* RTC_CNTL_IO_MUX_RESET_DISABLE : R/W; bitpos: [18]; default: 0; - * reg_io_mux_reset_disable - */ - -#define RTC_CNTL_IO_MUX_RESET_DISABLE (BIT(18)) -#define RTC_CNTL_IO_MUX_RESET_DISABLE_M (RTC_CNTL_IO_MUX_RESET_DISABLE_V << RTC_CNTL_IO_MUX_RESET_DISABLE_S) -#define RTC_CNTL_IO_MUX_RESET_DISABLE_V 0x00000001 -#define RTC_CNTL_IO_MUX_RESET_DISABLE_S 18 - -/* RTC_CNTL_USB_RESET_DISABLE : R/W; bitpos: [17]; default: 0; - * reg_usb_reset_disable - */ - -#define RTC_CNTL_USB_RESET_DISABLE (BIT(17)) -#define RTC_CNTL_USB_RESET_DISABLE_M (RTC_CNTL_USB_RESET_DISABLE_V << RTC_CNTL_USB_RESET_DISABLE_S) -#define RTC_CNTL_USB_RESET_DISABLE_V 0x00000001 -#define RTC_CNTL_USB_RESET_DISABLE_S 17 - -/* RTC_CNTL_USB_TX_EN_OVERRIDE : R/W; bitpos: [16]; default: 0; - * reg_usb_tx_en_override - */ - -#define RTC_CNTL_USB_TX_EN_OVERRIDE (BIT(16)) -#define RTC_CNTL_USB_TX_EN_OVERRIDE_M (RTC_CNTL_USB_TX_EN_OVERRIDE_V << RTC_CNTL_USB_TX_EN_OVERRIDE_S) -#define RTC_CNTL_USB_TX_EN_OVERRIDE_V 0x00000001 -#define RTC_CNTL_USB_TX_EN_OVERRIDE_S 16 - -/* RTC_CNTL_USB_TX_EN : R/W; bitpos: [15]; default: 0; - * reg_usb_tx_en - */ - -#define RTC_CNTL_USB_TX_EN (BIT(15)) -#define RTC_CNTL_USB_TX_EN_M (RTC_CNTL_USB_TX_EN_V << RTC_CNTL_USB_TX_EN_S) -#define RTC_CNTL_USB_TX_EN_V 0x00000001 -#define RTC_CNTL_USB_TX_EN_S 15 - -/* RTC_CNTL_USB_TXP : R/W; bitpos: [14]; default: 0; - * reg_usb_txp - */ - -#define RTC_CNTL_USB_TXP (BIT(14)) -#define RTC_CNTL_USB_TXP_M (RTC_CNTL_USB_TXP_V << RTC_CNTL_USB_TXP_S) -#define RTC_CNTL_USB_TXP_V 0x00000001 -#define RTC_CNTL_USB_TXP_S 14 - -/* RTC_CNTL_USB_TXM : R/W; bitpos: [13]; default: 0; - * reg_usb_txm - */ - -#define RTC_CNTL_USB_TXM (BIT(13)) -#define RTC_CNTL_USB_TXM_M (RTC_CNTL_USB_TXM_V << RTC_CNTL_USB_TXM_S) -#define RTC_CNTL_USB_TXM_V 0x00000001 -#define RTC_CNTL_USB_TXM_S 13 - -/* RTC_CNTL_USB_PAD_ENABLE : R/W; bitpos: [12]; default: 0; - * reg_usb_pad_enable - */ - -#define RTC_CNTL_USB_PAD_ENABLE (BIT(12)) -#define RTC_CNTL_USB_PAD_ENABLE_M (RTC_CNTL_USB_PAD_ENABLE_V << RTC_CNTL_USB_PAD_ENABLE_S) -#define RTC_CNTL_USB_PAD_ENABLE_V 0x00000001 -#define RTC_CNTL_USB_PAD_ENABLE_S 12 - -/* RTC_CNTL_USB_PAD_ENABLE_OVERRIDE : R/W; bitpos: [11]; default: 0; - * reg_usb_pad_enable_override - */ - -#define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE (BIT(11)) -#define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_M (RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_V << RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_S) -#define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_V 0x00000001 -#define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_S 11 - -/* RTC_CNTL_USB_PULLUP_VALUE : R/W; bitpos: [10]; default: 0; - * reg_usb_pullup_value - */ - -#define RTC_CNTL_USB_PULLUP_VALUE (BIT(10)) -#define RTC_CNTL_USB_PULLUP_VALUE_M (RTC_CNTL_USB_PULLUP_VALUE_V << RTC_CNTL_USB_PULLUP_VALUE_S) -#define RTC_CNTL_USB_PULLUP_VALUE_V 0x00000001 -#define RTC_CNTL_USB_PULLUP_VALUE_S 10 - -/* RTC_CNTL_USB_DM_PULLDOWN : R/W; bitpos: [9]; default: 0; - * reg_usb_dm_pulldown - */ - -#define RTC_CNTL_USB_DM_PULLDOWN (BIT(9)) -#define RTC_CNTL_USB_DM_PULLDOWN_M (RTC_CNTL_USB_DM_PULLDOWN_V << RTC_CNTL_USB_DM_PULLDOWN_S) -#define RTC_CNTL_USB_DM_PULLDOWN_V 0x00000001 -#define RTC_CNTL_USB_DM_PULLDOWN_S 9 - -/* RTC_CNTL_USB_DM_PULLUP : R/W; bitpos: [8]; default: 0; - * reg_usb_dm_pullup - */ - -#define RTC_CNTL_USB_DM_PULLUP (BIT(8)) -#define RTC_CNTL_USB_DM_PULLUP_M (RTC_CNTL_USB_DM_PULLUP_V << RTC_CNTL_USB_DM_PULLUP_S) -#define RTC_CNTL_USB_DM_PULLUP_V 0x00000001 -#define RTC_CNTL_USB_DM_PULLUP_S 8 - -/* RTC_CNTL_USB_DP_PULLDOWN : R/W; bitpos: [7]; default: 0; - * reg_usb_dp_pulldown - */ - -#define RTC_CNTL_USB_DP_PULLDOWN (BIT(7)) -#define RTC_CNTL_USB_DP_PULLDOWN_M (RTC_CNTL_USB_DP_PULLDOWN_V << RTC_CNTL_USB_DP_PULLDOWN_S) -#define RTC_CNTL_USB_DP_PULLDOWN_V 0x00000001 -#define RTC_CNTL_USB_DP_PULLDOWN_S 7 - -/* RTC_CNTL_USB_DP_PULLUP : R/W; bitpos: [6]; default: 0; - * reg_usb_dp_pullup - */ - -#define RTC_CNTL_USB_DP_PULLUP (BIT(6)) -#define RTC_CNTL_USB_DP_PULLUP_M (RTC_CNTL_USB_DP_PULLUP_V << RTC_CNTL_USB_DP_PULLUP_S) -#define RTC_CNTL_USB_DP_PULLUP_V 0x00000001 -#define RTC_CNTL_USB_DP_PULLUP_S 6 - -/* RTC_CNTL_USB_PAD_PULL_OVERRIDE : R/W; bitpos: [5]; default: 0; - * reg_usb_pad_pull_override - */ - -#define RTC_CNTL_USB_PAD_PULL_OVERRIDE (BIT(5)) -#define RTC_CNTL_USB_PAD_PULL_OVERRIDE_M (RTC_CNTL_USB_PAD_PULL_OVERRIDE_V << RTC_CNTL_USB_PAD_PULL_OVERRIDE_S) -#define RTC_CNTL_USB_PAD_PULL_OVERRIDE_V 0x00000001 -#define RTC_CNTL_USB_PAD_PULL_OVERRIDE_S 5 - -/* RTC_CNTL_USB_VREF_OVERRIDE : R/W; bitpos: [4]; default: 0; - * reg_usb_vref_override - */ - -#define RTC_CNTL_USB_VREF_OVERRIDE (BIT(4)) -#define RTC_CNTL_USB_VREF_OVERRIDE_M (RTC_CNTL_USB_VREF_OVERRIDE_V << RTC_CNTL_USB_VREF_OVERRIDE_S) -#define RTC_CNTL_USB_VREF_OVERRIDE_V 0x00000001 -#define RTC_CNTL_USB_VREF_OVERRIDE_S 4 - -/* RTC_CNTL_USB_VREFL : R/W; bitpos: [3:2]; default: 0; - * reg_usb_vrefl - */ - -#define RTC_CNTL_USB_VREFL 0x00000003 -#define RTC_CNTL_USB_VREFL_M (RTC_CNTL_USB_VREFL_V << RTC_CNTL_USB_VREFL_S) -#define RTC_CNTL_USB_VREFL_V 0x00000003 -#define RTC_CNTL_USB_VREFL_S 2 - -/* RTC_CNTL_USB_VREFH : R/W; bitpos: [1:0]; default: 0; - * reg_usb_vrefh - */ - -#define RTC_CNTL_USB_VREFH 0x00000003 -#define RTC_CNTL_USB_VREFH_M (RTC_CNTL_USB_VREFH_V << RTC_CNTL_USB_VREFH_S) -#define RTC_CNTL_USB_VREFH_V 0x00000003 -#define RTC_CNTL_USB_VREFH_S 0 - -/* RTC_CNTL_RTC_TOUCH_TIMEOUT_CTRL_REG register - * configure touch controller - */ - -#define RTC_CNTL_RTC_TOUCH_TIMEOUT_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x124) - -/* RTC_CNTL_TOUCH_TIMEOUT_EN : R/W; bitpos: [22]; default: 1; - * enable touch timerout - */ - -#define RTC_CNTL_TOUCH_TIMEOUT_EN (BIT(22)) -#define RTC_CNTL_TOUCH_TIMEOUT_EN_M (RTC_CNTL_TOUCH_TIMEOUT_EN_V << RTC_CNTL_TOUCH_TIMEOUT_EN_S) -#define RTC_CNTL_TOUCH_TIMEOUT_EN_V 0x00000001 -#define RTC_CNTL_TOUCH_TIMEOUT_EN_S 22 - -/* RTC_CNTL_TOUCH_TIMEOUT_NUM : R/W; bitpos: [21:0]; default: 4194303; - * configure touch timerout time - */ - -#define RTC_CNTL_TOUCH_TIMEOUT_NUM 0x003fffff -#define RTC_CNTL_TOUCH_TIMEOUT_NUM_M (RTC_CNTL_TOUCH_TIMEOUT_NUM_V << RTC_CNTL_TOUCH_TIMEOUT_NUM_S) -#define RTC_CNTL_TOUCH_TIMEOUT_NUM_V 0x003fffff -#define RTC_CNTL_TOUCH_TIMEOUT_NUM_S 0 - -/* RTC_CNTL_RTC_SLP_REJECT_CAUSE_REG register - * get reject cause - */ - -#define RTC_CNTL_RTC_SLP_REJECT_CAUSE_REG (DR_REG_RTCCNTL_BASE + 0x128) - -/* RTC_CNTL_REJECT_CAUSE : RO; bitpos: [17:0]; default: 0; - * sleep reject cause - */ - -#define RTC_CNTL_REJECT_CAUSE 0x0003ffff -#define RTC_CNTL_REJECT_CAUSE_M (RTC_CNTL_REJECT_CAUSE_V << RTC_CNTL_REJECT_CAUSE_S) -#define RTC_CNTL_REJECT_CAUSE_V 0x0003ffff -#define RTC_CNTL_REJECT_CAUSE_S 0 - -/* RTC_CNTL_RTC_OPTION1_REG register - * rtc common configure - */ - -#define RTC_CNTL_RTC_OPTION1_REG (DR_REG_RTCCNTL_BASE + 0x12c) - -/* RTC_CNTL_FORCE_DOWNLOAD_BOOT : R/W; bitpos: [0]; default: 0; - * force chip entry download boot by sw - */ - -#define RTC_CNTL_FORCE_DOWNLOAD_BOOT (BIT(0)) -#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_M (RTC_CNTL_FORCE_DOWNLOAD_BOOT_V << RTC_CNTL_FORCE_DOWNLOAD_BOOT_S) -#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_V 0x00000001 -#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_S 0 - -/* RTC_CNTL_RTC_SLP_WAKEUP_CAUSE_REG register - * get wakeup cause - */ - -#define RTC_CNTL_RTC_SLP_WAKEUP_CAUSE_REG (DR_REG_RTCCNTL_BASE + 0x130) - -/* RTC_CNTL_WAKEUP_CAUSE : RO; bitpos: [16:0]; default: 0; - * sleep wakeup cause - */ - -#define RTC_CNTL_WAKEUP_CAUSE 0x0001ffff -#define RTC_CNTL_WAKEUP_CAUSE_M (RTC_CNTL_WAKEUP_CAUSE_V << RTC_CNTL_WAKEUP_CAUSE_S) -#define RTC_CNTL_WAKEUP_CAUSE_V 0x0001ffff -#define RTC_CNTL_WAKEUP_CAUSE_S 0 - -/* RTC_CNTL_RTC_ULP_CP_TIMER_1_REG register - * configure ulp sleep time - */ - -#define RTC_CNTL_RTC_ULP_CP_TIMER_1_REG (DR_REG_RTCCNTL_BASE + 0x134) - -/* RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE : R/W; bitpos: [31:8]; default: 200; - * sleep cycles for ULP-coprocessor timer - */ - -#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE 0x00ffffff -#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_M (RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V << RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S) -#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V 0x00ffffff -#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S 8 - -/* RTC_CNTL_INT_ENA_RTC_W1TS_REG register - * oneset rtc interrupt - */ - -#define RTC_CNTL_INT_ENA_RTC_W1TS_REG (DR_REG_RTCCNTL_BASE + 0x138) - -/* RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS : WO; bitpos: [20]; - * default: 0; - * enable touch approach_loop done interrupt - */ - -#define RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS (BIT(20)) -#define RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_M (RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_V << RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_S) -#define RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_V 0x00000001 -#define RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_S 20 - -/* RTC_CNTL_RTC_GLITCH_DET_INT_ENA_W1TS : WO; bitpos: [19]; default: 0; - * enable gitch det interrupt - */ - -#define RTC_CNTL_RTC_GLITCH_DET_INT_ENA_W1TS (BIT(19)) -#define RTC_CNTL_RTC_GLITCH_DET_INT_ENA_W1TS_M (RTC_CNTL_RTC_GLITCH_DET_INT_ENA_W1TS_V << RTC_CNTL_RTC_GLITCH_DET_INT_ENA_W1TS_S) -#define RTC_CNTL_RTC_GLITCH_DET_INT_ENA_W1TS_V 0x00000001 -#define RTC_CNTL_RTC_GLITCH_DET_INT_ENA_W1TS_S 19 - -/* RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_ENA_W1TS : WO; bitpos: [18]; default: 0; - * enable touch timeout interrupt - */ - -#define RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_ENA_W1TS (BIT(18)) -#define RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_ENA_W1TS_M (RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_ENA_W1TS_V << RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_ENA_W1TS_S) -#define RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_ENA_W1TS_V 0x00000001 -#define RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_ENA_W1TS_S 18 - -/* RTC_CNTL_RTC_COCPU_TRAP_INT_ENA_W1TS : WO; bitpos: [17]; default: 0; - * enable cocpu trap interrupt - */ - -#define RTC_CNTL_RTC_COCPU_TRAP_INT_ENA_W1TS (BIT(17)) -#define RTC_CNTL_RTC_COCPU_TRAP_INT_ENA_W1TS_M (RTC_CNTL_RTC_COCPU_TRAP_INT_ENA_W1TS_V << RTC_CNTL_RTC_COCPU_TRAP_INT_ENA_W1TS_S) -#define RTC_CNTL_RTC_COCPU_TRAP_INT_ENA_W1TS_V 0x00000001 -#define RTC_CNTL_RTC_COCPU_TRAP_INT_ENA_W1TS_S 17 - -/* RTC_CNTL_RTC_XTAL32K_DEAD_INT_ENA_W1TS : WO; bitpos: [16]; default: 0; - * enable xtal32k_dead interrupt - */ - -#define RTC_CNTL_RTC_XTAL32K_DEAD_INT_ENA_W1TS (BIT(16)) -#define RTC_CNTL_RTC_XTAL32K_DEAD_INT_ENA_W1TS_M (RTC_CNTL_RTC_XTAL32K_DEAD_INT_ENA_W1TS_V << RTC_CNTL_RTC_XTAL32K_DEAD_INT_ENA_W1TS_S) -#define RTC_CNTL_RTC_XTAL32K_DEAD_INT_ENA_W1TS_V 0x00000001 -#define RTC_CNTL_RTC_XTAL32K_DEAD_INT_ENA_W1TS_S 16 - -/* RTC_CNTL_RTC_SWD_INT_ENA_W1TS : WO; bitpos: [15]; default: 0; - * enable super watch dog interrupt - */ - -#define RTC_CNTL_RTC_SWD_INT_ENA_W1TS (BIT(15)) -#define RTC_CNTL_RTC_SWD_INT_ENA_W1TS_M (RTC_CNTL_RTC_SWD_INT_ENA_W1TS_V << RTC_CNTL_RTC_SWD_INT_ENA_W1TS_S) -#define RTC_CNTL_RTC_SWD_INT_ENA_W1TS_V 0x00000001 -#define RTC_CNTL_RTC_SWD_INT_ENA_W1TS_S 15 - -/* RTC_CNTL_RTC_SARADC2_INT_ENA_W1TS : WO; bitpos: [14]; default: 0; - * enable saradc2 interrupt - */ - -#define RTC_CNTL_RTC_SARADC2_INT_ENA_W1TS (BIT(14)) -#define RTC_CNTL_RTC_SARADC2_INT_ENA_W1TS_M (RTC_CNTL_RTC_SARADC2_INT_ENA_W1TS_V << RTC_CNTL_RTC_SARADC2_INT_ENA_W1TS_S) -#define RTC_CNTL_RTC_SARADC2_INT_ENA_W1TS_V 0x00000001 -#define RTC_CNTL_RTC_SARADC2_INT_ENA_W1TS_S 14 - -/* RTC_CNTL_RTC_COCPU_INT_ENA_W1TS : WO; bitpos: [13]; default: 0; - * enable riscV cocpu interrupt - */ - -#define RTC_CNTL_RTC_COCPU_INT_ENA_W1TS (BIT(13)) -#define RTC_CNTL_RTC_COCPU_INT_ENA_W1TS_M (RTC_CNTL_RTC_COCPU_INT_ENA_W1TS_V << RTC_CNTL_RTC_COCPU_INT_ENA_W1TS_S) -#define RTC_CNTL_RTC_COCPU_INT_ENA_W1TS_V 0x00000001 -#define RTC_CNTL_RTC_COCPU_INT_ENA_W1TS_S 13 - -/* RTC_CNTL_RTC_TSENS_INT_ENA_W1TS : WO; bitpos: [12]; default: 0; - * enable tsens interrupt - */ - -#define RTC_CNTL_RTC_TSENS_INT_ENA_W1TS (BIT(12)) -#define RTC_CNTL_RTC_TSENS_INT_ENA_W1TS_M (RTC_CNTL_RTC_TSENS_INT_ENA_W1TS_V << RTC_CNTL_RTC_TSENS_INT_ENA_W1TS_S) -#define RTC_CNTL_RTC_TSENS_INT_ENA_W1TS_V 0x00000001 -#define RTC_CNTL_RTC_TSENS_INT_ENA_W1TS_S 12 - -/* RTC_CNTL_RTC_SARADC1_INT_ENA_W1TS : WO; bitpos: [11]; default: 0; - * enable saradc1 interrupt - */ - -#define RTC_CNTL_RTC_SARADC1_INT_ENA_W1TS (BIT(11)) -#define RTC_CNTL_RTC_SARADC1_INT_ENA_W1TS_M (RTC_CNTL_RTC_SARADC1_INT_ENA_W1TS_V << RTC_CNTL_RTC_SARADC1_INT_ENA_W1TS_S) -#define RTC_CNTL_RTC_SARADC1_INT_ENA_W1TS_V 0x00000001 -#define RTC_CNTL_RTC_SARADC1_INT_ENA_W1TS_S 11 - -/* RTC_CNTL_RTC_MAIN_TIMER_INT_ENA_W1TS : WO; bitpos: [10]; default: 0; - * enable RTC main timer interrupt - */ - -#define RTC_CNTL_RTC_MAIN_TIMER_INT_ENA_W1TS (BIT(10)) -#define RTC_CNTL_RTC_MAIN_TIMER_INT_ENA_W1TS_M (RTC_CNTL_RTC_MAIN_TIMER_INT_ENA_W1TS_V << RTC_CNTL_RTC_MAIN_TIMER_INT_ENA_W1TS_S) -#define RTC_CNTL_RTC_MAIN_TIMER_INT_ENA_W1TS_V 0x00000001 -#define RTC_CNTL_RTC_MAIN_TIMER_INT_ENA_W1TS_S 10 - -/* RTC_CNTL_RTC_BROWN_OUT_INT_ENA_W1TS : WO; bitpos: [9]; default: 0; - * enable brown out interrupt - */ - -#define RTC_CNTL_RTC_BROWN_OUT_INT_ENA_W1TS (BIT(9)) -#define RTC_CNTL_RTC_BROWN_OUT_INT_ENA_W1TS_M (RTC_CNTL_RTC_BROWN_OUT_INT_ENA_W1TS_V << RTC_CNTL_RTC_BROWN_OUT_INT_ENA_W1TS_S) -#define RTC_CNTL_RTC_BROWN_OUT_INT_ENA_W1TS_V 0x00000001 -#define RTC_CNTL_RTC_BROWN_OUT_INT_ENA_W1TS_S 9 - -/* RTC_CNTL_RTC_TOUCH_INACTIVE_INT_ENA_W1TS : WO; bitpos: [8]; default: 0; - * enable touch inactive interrupt - */ - -#define RTC_CNTL_RTC_TOUCH_INACTIVE_INT_ENA_W1TS (BIT(8)) -#define RTC_CNTL_RTC_TOUCH_INACTIVE_INT_ENA_W1TS_M (RTC_CNTL_RTC_TOUCH_INACTIVE_INT_ENA_W1TS_V << RTC_CNTL_RTC_TOUCH_INACTIVE_INT_ENA_W1TS_S) -#define RTC_CNTL_RTC_TOUCH_INACTIVE_INT_ENA_W1TS_V 0x00000001 -#define RTC_CNTL_RTC_TOUCH_INACTIVE_INT_ENA_W1TS_S 8 - -/* RTC_CNTL_RTC_TOUCH_ACTIVE_INT_ENA_W1TS : WO; bitpos: [7]; default: 0; - * enable touch active interrupt - */ - -#define RTC_CNTL_RTC_TOUCH_ACTIVE_INT_ENA_W1TS (BIT(7)) -#define RTC_CNTL_RTC_TOUCH_ACTIVE_INT_ENA_W1TS_M (RTC_CNTL_RTC_TOUCH_ACTIVE_INT_ENA_W1TS_V << RTC_CNTL_RTC_TOUCH_ACTIVE_INT_ENA_W1TS_S) -#define RTC_CNTL_RTC_TOUCH_ACTIVE_INT_ENA_W1TS_V 0x00000001 -#define RTC_CNTL_RTC_TOUCH_ACTIVE_INT_ENA_W1TS_S 7 - -/* RTC_CNTL_RTC_TOUCH_DONE_INT_ENA_W1TS : WO; bitpos: [6]; default: 0; - * enable touch done interrupt - */ - -#define RTC_CNTL_RTC_TOUCH_DONE_INT_ENA_W1TS (BIT(6)) -#define RTC_CNTL_RTC_TOUCH_DONE_INT_ENA_W1TS_M (RTC_CNTL_RTC_TOUCH_DONE_INT_ENA_W1TS_V << RTC_CNTL_RTC_TOUCH_DONE_INT_ENA_W1TS_S) -#define RTC_CNTL_RTC_TOUCH_DONE_INT_ENA_W1TS_V 0x00000001 -#define RTC_CNTL_RTC_TOUCH_DONE_INT_ENA_W1TS_S 6 - -/* RTC_CNTL_RTC_ULP_CP_INT_ENA_W1TS : WO; bitpos: [5]; default: 0; - * enable ULP-coprocessor interrupt - */ - -#define RTC_CNTL_RTC_ULP_CP_INT_ENA_W1TS (BIT(5)) -#define RTC_CNTL_RTC_ULP_CP_INT_ENA_W1TS_M (RTC_CNTL_RTC_ULP_CP_INT_ENA_W1TS_V << RTC_CNTL_RTC_ULP_CP_INT_ENA_W1TS_S) -#define RTC_CNTL_RTC_ULP_CP_INT_ENA_W1TS_V 0x00000001 -#define RTC_CNTL_RTC_ULP_CP_INT_ENA_W1TS_S 5 - -/* RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_ENA_W1TS : WO; bitpos: [4]; default: 0; - * enable touch scan done interrupt - */ - -#define RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_ENA_W1TS (BIT(4)) -#define RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_ENA_W1TS_M (RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_ENA_W1TS_V << RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_ENA_W1TS_S) -#define RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_ENA_W1TS_V 0x00000001 -#define RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_ENA_W1TS_S 4 - -/* RTC_CNTL_RTC_WDT_INT_ENA_W1TS : WO; bitpos: [3]; default: 0; - * enable RTC WDT interrupt - */ - -#define RTC_CNTL_RTC_WDT_INT_ENA_W1TS (BIT(3)) -#define RTC_CNTL_RTC_WDT_INT_ENA_W1TS_M (RTC_CNTL_RTC_WDT_INT_ENA_W1TS_V << RTC_CNTL_RTC_WDT_INT_ENA_W1TS_S) -#define RTC_CNTL_RTC_WDT_INT_ENA_W1TS_V 0x00000001 -#define RTC_CNTL_RTC_WDT_INT_ENA_W1TS_S 3 - -/* RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS : WO; bitpos: [2]; default: 0; - * enable SDIO idle interrupt - */ - -#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS (BIT(2)) -#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS_M (RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS_V << RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS_S) -#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS_V 0x00000001 -#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS_S 2 - -/* RTC_CNTL_SLP_REJECT_INT_ENA_W1TS : WO; bitpos: [1]; default: 0; - * enable sleep reject interrupt - */ - -#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS (BIT(1)) -#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_M (RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_V << RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_S) -#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_V 0x00000001 -#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_S 1 - -/* RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS : WO; bitpos: [0]; default: 0; - * enable sleep wakeup interrupt - */ - -#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS (BIT(0)) -#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_M (RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_V << RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_S) -#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_V 0x00000001 -#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_S 0 - -/* RTC_CNTL_INT_ENA_RTC_W1TC_REG register - * oneset clr rtc interrupt enable - */ - -#define RTC_CNTL_INT_ENA_RTC_W1TC_REG (DR_REG_RTCCNTL_BASE + 0x13c) - -/* RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC : WO; bitpos: [20]; - * default: 0; - * enable touch approach_loop done interrupt - */ - -#define RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC (BIT(20)) -#define RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_M (RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_V << RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_S) -#define RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_V 0x00000001 -#define RTC_CNTL_RTC_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_S 20 - -/* RTC_CNTL_RTC_GLITCH_DET_INT_ENA_W1TC : WO; bitpos: [19]; default: 0; - * enable gitch det interrupt - */ - -#define RTC_CNTL_RTC_GLITCH_DET_INT_ENA_W1TC (BIT(19)) -#define RTC_CNTL_RTC_GLITCH_DET_INT_ENA_W1TC_M (RTC_CNTL_RTC_GLITCH_DET_INT_ENA_W1TC_V << RTC_CNTL_RTC_GLITCH_DET_INT_ENA_W1TC_S) -#define RTC_CNTL_RTC_GLITCH_DET_INT_ENA_W1TC_V 0x00000001 -#define RTC_CNTL_RTC_GLITCH_DET_INT_ENA_W1TC_S 19 - -/* RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_ENA_W1TC : WO; bitpos: [18]; default: 0; - * enable touch timeout interrupt - */ - -#define RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_ENA_W1TC (BIT(18)) -#define RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_ENA_W1TC_M (RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_ENA_W1TC_V << RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_ENA_W1TC_S) -#define RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_ENA_W1TC_V 0x00000001 -#define RTC_CNTL_RTC_TOUCH_TIMEOUT_INT_ENA_W1TC_S 18 - -/* RTC_CNTL_RTC_COCPU_TRAP_INT_ENA_W1TC : WO; bitpos: [17]; default: 0; - * enable cocpu trap interrupt - */ - -#define RTC_CNTL_RTC_COCPU_TRAP_INT_ENA_W1TC (BIT(17)) -#define RTC_CNTL_RTC_COCPU_TRAP_INT_ENA_W1TC_M (RTC_CNTL_RTC_COCPU_TRAP_INT_ENA_W1TC_V << RTC_CNTL_RTC_COCPU_TRAP_INT_ENA_W1TC_S) -#define RTC_CNTL_RTC_COCPU_TRAP_INT_ENA_W1TC_V 0x00000001 -#define RTC_CNTL_RTC_COCPU_TRAP_INT_ENA_W1TC_S 17 - -/* RTC_CNTL_RTC_XTAL32K_DEAD_INT_ENA_W1TC : WO; bitpos: [16]; default: 0; - * enable xtal32k_dead interrupt - */ - -#define RTC_CNTL_RTC_XTAL32K_DEAD_INT_ENA_W1TC (BIT(16)) -#define RTC_CNTL_RTC_XTAL32K_DEAD_INT_ENA_W1TC_M (RTC_CNTL_RTC_XTAL32K_DEAD_INT_ENA_W1TC_V << RTC_CNTL_RTC_XTAL32K_DEAD_INT_ENA_W1TC_S) -#define RTC_CNTL_RTC_XTAL32K_DEAD_INT_ENA_W1TC_V 0x00000001 -#define RTC_CNTL_RTC_XTAL32K_DEAD_INT_ENA_W1TC_S 16 - -/* RTC_CNTL_RTC_SWD_INT_ENA_W1TC : WO; bitpos: [15]; default: 0; - * enable super watch dog interrupt - */ - -#define RTC_CNTL_RTC_SWD_INT_ENA_W1TC (BIT(15)) -#define RTC_CNTL_RTC_SWD_INT_ENA_W1TC_M (RTC_CNTL_RTC_SWD_INT_ENA_W1TC_V << RTC_CNTL_RTC_SWD_INT_ENA_W1TC_S) -#define RTC_CNTL_RTC_SWD_INT_ENA_W1TC_V 0x00000001 -#define RTC_CNTL_RTC_SWD_INT_ENA_W1TC_S 15 - -/* RTC_CNTL_RTC_SARADC2_INT_ENA_W1TC : WO; bitpos: [14]; default: 0; - * enable saradc2 interrupt - */ - -#define RTC_CNTL_RTC_SARADC2_INT_ENA_W1TC (BIT(14)) -#define RTC_CNTL_RTC_SARADC2_INT_ENA_W1TC_M (RTC_CNTL_RTC_SARADC2_INT_ENA_W1TC_V << RTC_CNTL_RTC_SARADC2_INT_ENA_W1TC_S) -#define RTC_CNTL_RTC_SARADC2_INT_ENA_W1TC_V 0x00000001 -#define RTC_CNTL_RTC_SARADC2_INT_ENA_W1TC_S 14 - -/* RTC_CNTL_RTC_COCPU_INT_ENA_W1TC : WO; bitpos: [13]; default: 0; - * enable riscV cocpu interrupt - */ - -#define RTC_CNTL_RTC_COCPU_INT_ENA_W1TC (BIT(13)) -#define RTC_CNTL_RTC_COCPU_INT_ENA_W1TC_M (RTC_CNTL_RTC_COCPU_INT_ENA_W1TC_V << RTC_CNTL_RTC_COCPU_INT_ENA_W1TC_S) -#define RTC_CNTL_RTC_COCPU_INT_ENA_W1TC_V 0x00000001 -#define RTC_CNTL_RTC_COCPU_INT_ENA_W1TC_S 13 - -/* RTC_CNTL_RTC_TSENS_INT_ENA_W1TC : WO; bitpos: [12]; default: 0; - * enable tsens interrupt - */ - -#define RTC_CNTL_RTC_TSENS_INT_ENA_W1TC (BIT(12)) -#define RTC_CNTL_RTC_TSENS_INT_ENA_W1TC_M (RTC_CNTL_RTC_TSENS_INT_ENA_W1TC_V << RTC_CNTL_RTC_TSENS_INT_ENA_W1TC_S) -#define RTC_CNTL_RTC_TSENS_INT_ENA_W1TC_V 0x00000001 -#define RTC_CNTL_RTC_TSENS_INT_ENA_W1TC_S 12 - -/* RTC_CNTL_RTC_SARADC1_INT_ENA_W1TC : WO; bitpos: [11]; default: 0; - * enable saradc1 interrupt - */ - -#define RTC_CNTL_RTC_SARADC1_INT_ENA_W1TC (BIT(11)) -#define RTC_CNTL_RTC_SARADC1_INT_ENA_W1TC_M (RTC_CNTL_RTC_SARADC1_INT_ENA_W1TC_V << RTC_CNTL_RTC_SARADC1_INT_ENA_W1TC_S) -#define RTC_CNTL_RTC_SARADC1_INT_ENA_W1TC_V 0x00000001 -#define RTC_CNTL_RTC_SARADC1_INT_ENA_W1TC_S 11 - -/* RTC_CNTL_RTC_MAIN_TIMER_INT_ENA_W1TC : WO; bitpos: [10]; default: 0; - * enable RTC main timer interrupt - */ - -#define RTC_CNTL_RTC_MAIN_TIMER_INT_ENA_W1TC (BIT(10)) -#define RTC_CNTL_RTC_MAIN_TIMER_INT_ENA_W1TC_M (RTC_CNTL_RTC_MAIN_TIMER_INT_ENA_W1TC_V << RTC_CNTL_RTC_MAIN_TIMER_INT_ENA_W1TC_S) -#define RTC_CNTL_RTC_MAIN_TIMER_INT_ENA_W1TC_V 0x00000001 -#define RTC_CNTL_RTC_MAIN_TIMER_INT_ENA_W1TC_S 10 - -/* RTC_CNTL_RTC_BROWN_OUT_INT_ENA_W1TC : WO; bitpos: [9]; default: 0; - * enable brown out interrupt - */ - -#define RTC_CNTL_RTC_BROWN_OUT_INT_ENA_W1TC (BIT(9)) -#define RTC_CNTL_RTC_BROWN_OUT_INT_ENA_W1TC_M (RTC_CNTL_RTC_BROWN_OUT_INT_ENA_W1TC_V << RTC_CNTL_RTC_BROWN_OUT_INT_ENA_W1TC_S) -#define RTC_CNTL_RTC_BROWN_OUT_INT_ENA_W1TC_V 0x00000001 -#define RTC_CNTL_RTC_BROWN_OUT_INT_ENA_W1TC_S 9 - -/* RTC_CNTL_RTC_TOUCH_INACTIVE_INT_ENA_W1TC : WO; bitpos: [8]; default: 0; - * enable touch inactive interrupt - */ - -#define RTC_CNTL_RTC_TOUCH_INACTIVE_INT_ENA_W1TC (BIT(8)) -#define RTC_CNTL_RTC_TOUCH_INACTIVE_INT_ENA_W1TC_M (RTC_CNTL_RTC_TOUCH_INACTIVE_INT_ENA_W1TC_V << RTC_CNTL_RTC_TOUCH_INACTIVE_INT_ENA_W1TC_S) -#define RTC_CNTL_RTC_TOUCH_INACTIVE_INT_ENA_W1TC_V 0x00000001 -#define RTC_CNTL_RTC_TOUCH_INACTIVE_INT_ENA_W1TC_S 8 - -/* RTC_CNTL_RTC_TOUCH_ACTIVE_INT_ENA_W1TC : WO; bitpos: [7]; default: 0; - * enable touch active interrupt - */ - -#define RTC_CNTL_RTC_TOUCH_ACTIVE_INT_ENA_W1TC (BIT(7)) -#define RTC_CNTL_RTC_TOUCH_ACTIVE_INT_ENA_W1TC_M (RTC_CNTL_RTC_TOUCH_ACTIVE_INT_ENA_W1TC_V << RTC_CNTL_RTC_TOUCH_ACTIVE_INT_ENA_W1TC_S) -#define RTC_CNTL_RTC_TOUCH_ACTIVE_INT_ENA_W1TC_V 0x00000001 -#define RTC_CNTL_RTC_TOUCH_ACTIVE_INT_ENA_W1TC_S 7 - -/* RTC_CNTL_RTC_TOUCH_DONE_INT_ENA_W1TC : WO; bitpos: [6]; default: 0; - * enable touch done interrupt - */ - -#define RTC_CNTL_RTC_TOUCH_DONE_INT_ENA_W1TC (BIT(6)) -#define RTC_CNTL_RTC_TOUCH_DONE_INT_ENA_W1TC_M (RTC_CNTL_RTC_TOUCH_DONE_INT_ENA_W1TC_V << RTC_CNTL_RTC_TOUCH_DONE_INT_ENA_W1TC_S) -#define RTC_CNTL_RTC_TOUCH_DONE_INT_ENA_W1TC_V 0x00000001 -#define RTC_CNTL_RTC_TOUCH_DONE_INT_ENA_W1TC_S 6 - -/* RTC_CNTL_RTC_ULP_CP_INT_ENA_W1TC : WO; bitpos: [5]; default: 0; - * enable ULP-coprocessor interrupt - */ - -#define RTC_CNTL_RTC_ULP_CP_INT_ENA_W1TC (BIT(5)) -#define RTC_CNTL_RTC_ULP_CP_INT_ENA_W1TC_M (RTC_CNTL_RTC_ULP_CP_INT_ENA_W1TC_V << RTC_CNTL_RTC_ULP_CP_INT_ENA_W1TC_S) -#define RTC_CNTL_RTC_ULP_CP_INT_ENA_W1TC_V 0x00000001 -#define RTC_CNTL_RTC_ULP_CP_INT_ENA_W1TC_S 5 - -/* RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_ENA_W1TC : WO; bitpos: [4]; default: 0; - * enable touch scan done interrupt - */ - -#define RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_ENA_W1TC (BIT(4)) -#define RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_ENA_W1TC_M (RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_ENA_W1TC_V << RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_ENA_W1TC_S) -#define RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_ENA_W1TC_V 0x00000001 -#define RTC_CNTL_RTC_TOUCH_SCAN_DONE_INT_ENA_W1TC_S 4 - -/* RTC_CNTL_RTC_WDT_INT_ENA_W1TC : WO; bitpos: [3]; default: 0; - * enable RTC WDT interrupt - */ - -#define RTC_CNTL_RTC_WDT_INT_ENA_W1TC (BIT(3)) -#define RTC_CNTL_RTC_WDT_INT_ENA_W1TC_M (RTC_CNTL_RTC_WDT_INT_ENA_W1TC_V << RTC_CNTL_RTC_WDT_INT_ENA_W1TC_S) -#define RTC_CNTL_RTC_WDT_INT_ENA_W1TC_V 0x00000001 -#define RTC_CNTL_RTC_WDT_INT_ENA_W1TC_S 3 - -/* RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC : WO; bitpos: [2]; default: 0; - * enable SDIO idle interrupt - */ - -#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC (BIT(2)) -#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC_M (RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC_V << RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC_S) -#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC_V 0x00000001 -#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC_S 2 - -/* RTC_CNTL_SLP_REJECT_INT_ENA_W1TC : WO; bitpos: [1]; default: 0; - * enable sleep reject interrupt - */ - -#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC (BIT(1)) -#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_M (RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_V << RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_S) -#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_V 0x00000001 -#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_S 1 - -/* RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC : WO; bitpos: [0]; default: 0; - * enable sleep wakeup interrupt - */ - -#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC (BIT(0)) -#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_M (RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_V << RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_S) -#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_V 0x00000001 -#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_S 0 - -/* RTC_CNTL_RETENTION_CTRL_REG register - * configure retention - */ - -#define RTC_CNTL_RETENTION_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x140) - -/* RTC_CNTL_RETENTION_WAIT : R/W; bitpos: [31:25]; default: 20; - * wait cycles for rention operation - */ - -#define RTC_CNTL_RETENTION_WAIT 0x0000007f -#define RTC_CNTL_RETENTION_WAIT_M (RTC_CNTL_RETENTION_WAIT_V << RTC_CNTL_RETENTION_WAIT_S) -#define RTC_CNTL_RETENTION_WAIT_V 0x0000007f -#define RTC_CNTL_RETENTION_WAIT_S 25 - -/* RTC_CNTL_RETENTION_EN : R/W; bitpos: [24]; default: 0; - * enable retention - */ - -#define RTC_CNTL_RETENTION_EN (BIT(24)) -#define RTC_CNTL_RETENTION_EN_M (RTC_CNTL_RETENTION_EN_V << RTC_CNTL_RETENTION_EN_S) -#define RTC_CNTL_RETENTION_EN_V 0x00000001 -#define RTC_CNTL_RETENTION_EN_S 24 - -/* RTC_CNTL_RETENTION_CLKOFF_WAIT : R/W; bitpos: [23:20]; default: 3; - * wait clk off cycle - */ - -#define RTC_CNTL_RETENTION_CLKOFF_WAIT 0x0000000f -#define RTC_CNTL_RETENTION_CLKOFF_WAIT_M (RTC_CNTL_RETENTION_CLKOFF_WAIT_V << RTC_CNTL_RETENTION_CLKOFF_WAIT_S) -#define RTC_CNTL_RETENTION_CLKOFF_WAIT_V 0x0000000f -#define RTC_CNTL_RETENTION_CLKOFF_WAIT_S 20 - -/* RTC_CNTL_RETENTION_DONE_WAIT : R/W; bitpos: [19:17]; default: 2; - * wait retention done cycle - */ - -#define RTC_CNTL_RETENTION_DONE_WAIT 0x00000007 -#define RTC_CNTL_RETENTION_DONE_WAIT_M (RTC_CNTL_RETENTION_DONE_WAIT_V << RTC_CNTL_RETENTION_DONE_WAIT_S) -#define RTC_CNTL_RETENTION_DONE_WAIT_V 0x00000007 -#define RTC_CNTL_RETENTION_DONE_WAIT_S 17 - -/* RTC_CNTL_RETENTION_CLK_SEL : R/W; bitpos: [16]; default: 0; - * No public - */ - -#define RTC_CNTL_RETENTION_CLK_SEL (BIT(16)) -#define RTC_CNTL_RETENTION_CLK_SEL_M (RTC_CNTL_RETENTION_CLK_SEL_V << RTC_CNTL_RETENTION_CLK_SEL_S) -#define RTC_CNTL_RETENTION_CLK_SEL_V 0x00000001 -#define RTC_CNTL_RETENTION_CLK_SEL_S 16 - -/* RTC_CNTL_RETENTION_TARGET : R/W; bitpos: [15:14]; default: 0; - * configure retention target cpu and/or tag - */ - -#define RTC_CNTL_RETENTION_TARGET 0x00000003 -#define RTC_CNTL_RETENTION_TARGET_M (RTC_CNTL_RETENTION_TARGET_V << RTC_CNTL_RETENTION_TARGET_S) -#define RTC_CNTL_RETENTION_TARGET_V 0x00000003 -#define RTC_CNTL_RETENTION_TARGET_S 14 - -/* RTC_CNTL_RETENTION_TAG_MODE : R/W; bitpos: [13:10]; default: 0; - * No public - */ - -#define RTC_CNTL_RETENTION_TAG_MODE 0x0000000f -#define RTC_CNTL_RETENTION_TAG_MODE_M (RTC_CNTL_RETENTION_TAG_MODE_V << RTC_CNTL_RETENTION_TAG_MODE_S) -#define RTC_CNTL_RETENTION_TAG_MODE_V 0x0000000f -#define RTC_CNTL_RETENTION_TAG_MODE_S 10 - -/* RTC_CNTL_PG_CTRL_REG register - * configure power glitch - */ - -#define RTC_CNTL_PG_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x144) - -/* RTC_CNTL_POWER_GLITCH_EN : R/W; bitpos: [31]; default: 0; - * enable power glitch - */ - -#define RTC_CNTL_POWER_GLITCH_EN (BIT(31)) -#define RTC_CNTL_POWER_GLITCH_EN_M (RTC_CNTL_POWER_GLITCH_EN_V << RTC_CNTL_POWER_GLITCH_EN_S) -#define RTC_CNTL_POWER_GLITCH_EN_V 0x00000001 -#define RTC_CNTL_POWER_GLITCH_EN_S 31 - -/* RTC_CNTL_POWER_GLITCH_EFUSE_SEL : R/W; bitpos: [30]; default: 0; - * select use analog fib signal - */ - -#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL (BIT(30)) -#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL_M (RTC_CNTL_POWER_GLITCH_EFUSE_SEL_V << RTC_CNTL_POWER_GLITCH_EFUSE_SEL_S) -#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL_V 0x00000001 -#define RTC_CNTL_POWER_GLITCH_EFUSE_SEL_S 30 - -/* RTC_CNTL_POWER_GLITCH_FORCE_PU : R/W; bitpos: [29]; default: 0; - * force power glitch enable - */ - -#define RTC_CNTL_POWER_GLITCH_FORCE_PU (BIT(29)) -#define RTC_CNTL_POWER_GLITCH_FORCE_PU_M (RTC_CNTL_POWER_GLITCH_FORCE_PU_V << RTC_CNTL_POWER_GLITCH_FORCE_PU_S) -#define RTC_CNTL_POWER_GLITCH_FORCE_PU_V 0x00000001 -#define RTC_CNTL_POWER_GLITCH_FORCE_PU_S 29 - -/* RTC_CNTL_POWER_GLITCH_FORCE_PD : R/W; bitpos: [28]; default: 0; - * force power glitch disable - */ - -#define RTC_CNTL_POWER_GLITCH_FORCE_PD (BIT(28)) -#define RTC_CNTL_POWER_GLITCH_FORCE_PD_M (RTC_CNTL_POWER_GLITCH_FORCE_PD_V << RTC_CNTL_POWER_GLITCH_FORCE_PD_S) -#define RTC_CNTL_POWER_GLITCH_FORCE_PD_V 0x00000001 -#define RTC_CNTL_POWER_GLITCH_FORCE_PD_S 28 - -/* RTC_CNTL_POWER_GLITCH_DSENSE : R/W; bitpos: [27:26]; default: 0; - * GLITCH_DSENSE - */ - -#define RTC_CNTL_POWER_GLITCH_DSENSE 0x00000003 -#define RTC_CNTL_POWER_GLITCH_DSENSE_M (RTC_CNTL_POWER_GLITCH_DSENSE_V << RTC_CNTL_POWER_GLITCH_DSENSE_S) -#define RTC_CNTL_POWER_GLITCH_DSENSE_V 0x00000003 -#define RTC_CNTL_POWER_GLITCH_DSENSE_S 26 - -/* RTC_CNTL_RTC_FIB_SEL_REG register - * No public - */ - -#define RTC_CNTL_RTC_FIB_SEL_REG (DR_REG_RTCCNTL_BASE + 0x148) - -/* RTC_CNTL_RTC_FIB_SEL : R/W; bitpos: [2:0]; default: 7; - * No public - */ - -#define RTC_CNTL_RTC_FIB_SEL 0x00000007 -#define RTC_CNTL_RTC_FIB_SEL_M (RTC_CNTL_RTC_FIB_SEL_V << RTC_CNTL_RTC_FIB_SEL_S) -#define RTC_CNTL_RTC_FIB_SEL_V 0x00000007 -#define RTC_CNTL_RTC_FIB_SEL_S 0 - -/* RTC_CNTL_TOUCH_DAC_REG register - * configure touch dac - */ - -#define RTC_CNTL_TOUCH_DAC_REG (DR_REG_RTCCNTL_BASE + 0x14c) - -/* RTC_CNTL_TOUCH_PAD0_DAC : R/W; bitpos: [31:29]; default: 0; - * configure touch pad dac0 - */ - -#define RTC_CNTL_TOUCH_PAD0_DAC 0x00000007 -#define RTC_CNTL_TOUCH_PAD0_DAC_M (RTC_CNTL_TOUCH_PAD0_DAC_V << RTC_CNTL_TOUCH_PAD0_DAC_S) -#define RTC_CNTL_TOUCH_PAD0_DAC_V 0x00000007 -#define RTC_CNTL_TOUCH_PAD0_DAC_S 29 - -/* RTC_CNTL_TOUCH_PAD1_DAC : R/W; bitpos: [28:26]; default: 0; - * configure touch pad dac1 - */ - -#define RTC_CNTL_TOUCH_PAD1_DAC 0x00000007 -#define RTC_CNTL_TOUCH_PAD1_DAC_M (RTC_CNTL_TOUCH_PAD1_DAC_V << RTC_CNTL_TOUCH_PAD1_DAC_S) -#define RTC_CNTL_TOUCH_PAD1_DAC_V 0x00000007 -#define RTC_CNTL_TOUCH_PAD1_DAC_S 26 - -/* RTC_CNTL_TOUCH_PAD2_DAC : R/W; bitpos: [25:23]; default: 0; - * configure touch pad dac2 - */ - -#define RTC_CNTL_TOUCH_PAD2_DAC 0x00000007 -#define RTC_CNTL_TOUCH_PAD2_DAC_M (RTC_CNTL_TOUCH_PAD2_DAC_V << RTC_CNTL_TOUCH_PAD2_DAC_S) -#define RTC_CNTL_TOUCH_PAD2_DAC_V 0x00000007 -#define RTC_CNTL_TOUCH_PAD2_DAC_S 23 - -/* RTC_CNTL_TOUCH_PAD3_DAC : R/W; bitpos: [22:20]; default: 0; - * configure touch pad dac3 - */ - -#define RTC_CNTL_TOUCH_PAD3_DAC 0x00000007 -#define RTC_CNTL_TOUCH_PAD3_DAC_M (RTC_CNTL_TOUCH_PAD3_DAC_V << RTC_CNTL_TOUCH_PAD3_DAC_S) -#define RTC_CNTL_TOUCH_PAD3_DAC_V 0x00000007 -#define RTC_CNTL_TOUCH_PAD3_DAC_S 20 - -/* RTC_CNTL_TOUCH_PAD4_DAC : R/W; bitpos: [19:17]; default: 0; - * configure touch pad dac4 - */ - -#define RTC_CNTL_TOUCH_PAD4_DAC 0x00000007 -#define RTC_CNTL_TOUCH_PAD4_DAC_M (RTC_CNTL_TOUCH_PAD4_DAC_V << RTC_CNTL_TOUCH_PAD4_DAC_S) -#define RTC_CNTL_TOUCH_PAD4_DAC_V 0x00000007 -#define RTC_CNTL_TOUCH_PAD4_DAC_S 17 - -/* RTC_CNTL_TOUCH_PAD5_DAC : R/W; bitpos: [16:14]; default: 0; - * configure touch pad dac5 - */ - -#define RTC_CNTL_TOUCH_PAD5_DAC 0x00000007 -#define RTC_CNTL_TOUCH_PAD5_DAC_M (RTC_CNTL_TOUCH_PAD5_DAC_V << RTC_CNTL_TOUCH_PAD5_DAC_S) -#define RTC_CNTL_TOUCH_PAD5_DAC_V 0x00000007 -#define RTC_CNTL_TOUCH_PAD5_DAC_S 14 - -/* RTC_CNTL_TOUCH_PAD6_DAC : R/W; bitpos: [13:11]; default: 0; - * configure touch pad dac6 - */ - -#define RTC_CNTL_TOUCH_PAD6_DAC 0x00000007 -#define RTC_CNTL_TOUCH_PAD6_DAC_M (RTC_CNTL_TOUCH_PAD6_DAC_V << RTC_CNTL_TOUCH_PAD6_DAC_S) -#define RTC_CNTL_TOUCH_PAD6_DAC_V 0x00000007 -#define RTC_CNTL_TOUCH_PAD6_DAC_S 11 - -/* RTC_CNTL_TOUCH_PAD7_DAC : R/W; bitpos: [10:8]; default: 0; - * configure touch pad dac7 - */ - -#define RTC_CNTL_TOUCH_PAD7_DAC 0x00000007 -#define RTC_CNTL_TOUCH_PAD7_DAC_M (RTC_CNTL_TOUCH_PAD7_DAC_V << RTC_CNTL_TOUCH_PAD7_DAC_S) -#define RTC_CNTL_TOUCH_PAD7_DAC_V 0x00000007 -#define RTC_CNTL_TOUCH_PAD7_DAC_S 8 - -/* RTC_CNTL_TOUCH_PAD8_DAC : R/W; bitpos: [7:5]; default: 0; - * configure touch pad dac8 - */ - -#define RTC_CNTL_TOUCH_PAD8_DAC 0x00000007 -#define RTC_CNTL_TOUCH_PAD8_DAC_M (RTC_CNTL_TOUCH_PAD8_DAC_V << RTC_CNTL_TOUCH_PAD8_DAC_S) -#define RTC_CNTL_TOUCH_PAD8_DAC_V 0x00000007 -#define RTC_CNTL_TOUCH_PAD8_DAC_S 5 - -/* RTC_CNTL_TOUCH_PAD9_DAC : R/W; bitpos: [4:2]; default: 0; - * configure touch pad dac9 - */ - -#define RTC_CNTL_TOUCH_PAD9_DAC 0x00000007 -#define RTC_CNTL_TOUCH_PAD9_DAC_M (RTC_CNTL_TOUCH_PAD9_DAC_V << RTC_CNTL_TOUCH_PAD9_DAC_S) -#define RTC_CNTL_TOUCH_PAD9_DAC_V 0x00000007 -#define RTC_CNTL_TOUCH_PAD9_DAC_S 2 - -/* RTC_CNTL_TOUCH_DAC1_REG register - * configure touch dac - */ - -#define RTC_CNTL_TOUCH_DAC1_REG (DR_REG_RTCCNTL_BASE + 0x150) - -/* RTC_CNTL_TOUCH_PAD10_DAC : R/W; bitpos: [31:29]; default: 0; - * configure touch pad dac10 - */ - -#define RTC_CNTL_TOUCH_PAD10_DAC 0x00000007 -#define RTC_CNTL_TOUCH_PAD10_DAC_M (RTC_CNTL_TOUCH_PAD10_DAC_V << RTC_CNTL_TOUCH_PAD10_DAC_S) -#define RTC_CNTL_TOUCH_PAD10_DAC_V 0x00000007 -#define RTC_CNTL_TOUCH_PAD10_DAC_S 29 - -/* RTC_CNTL_TOUCH_PAD11_DAC : R/W; bitpos: [28:26]; default: 0; - * configure touch pad dac11 - */ - -#define RTC_CNTL_TOUCH_PAD11_DAC 0x00000007 -#define RTC_CNTL_TOUCH_PAD11_DAC_M (RTC_CNTL_TOUCH_PAD11_DAC_V << RTC_CNTL_TOUCH_PAD11_DAC_S) -#define RTC_CNTL_TOUCH_PAD11_DAC_V 0x00000007 -#define RTC_CNTL_TOUCH_PAD11_DAC_S 26 - -/* RTC_CNTL_TOUCH_PAD12_DAC : R/W; bitpos: [25:23]; default: 0; - * configure touch pad dac12 - */ - -#define RTC_CNTL_TOUCH_PAD12_DAC 0x00000007 -#define RTC_CNTL_TOUCH_PAD12_DAC_M (RTC_CNTL_TOUCH_PAD12_DAC_V << RTC_CNTL_TOUCH_PAD12_DAC_S) -#define RTC_CNTL_TOUCH_PAD12_DAC_V 0x00000007 -#define RTC_CNTL_TOUCH_PAD12_DAC_S 23 - -/* RTC_CNTL_TOUCH_PAD13_DAC : R/W; bitpos: [22:20]; default: 0; - * configure touch pad dac13 - */ - -#define RTC_CNTL_TOUCH_PAD13_DAC 0x00000007 -#define RTC_CNTL_TOUCH_PAD13_DAC_M (RTC_CNTL_TOUCH_PAD13_DAC_V << RTC_CNTL_TOUCH_PAD13_DAC_S) -#define RTC_CNTL_TOUCH_PAD13_DAC_V 0x00000007 -#define RTC_CNTL_TOUCH_PAD13_DAC_S 20 - -/* RTC_CNTL_TOUCH_PAD14_DAC : R/W; bitpos: [19:17]; default: 0; - * configure touch pad dac14 - */ - -#define RTC_CNTL_TOUCH_PAD14_DAC 0x00000007 -#define RTC_CNTL_TOUCH_PAD14_DAC_M (RTC_CNTL_TOUCH_PAD14_DAC_V << RTC_CNTL_TOUCH_PAD14_DAC_S) -#define RTC_CNTL_TOUCH_PAD14_DAC_V 0x00000007 -#define RTC_CNTL_TOUCH_PAD14_DAC_S 17 - -/* RTC_CNTL_RTC_COCPU_DISABLE_REG register - * configure ulp disable - */ - -#define RTC_CNTL_RTC_COCPU_DISABLE_REG (DR_REG_RTCCNTL_BASE + 0x154) - -/* RTC_CNTL_DISABLE_RTC_CPU : R/W; bitpos: [31]; default: 0; - * configure ulp disable - */ - -#define RTC_CNTL_DISABLE_RTC_CPU (BIT(31)) -#define RTC_CNTL_DISABLE_RTC_CPU_M (RTC_CNTL_DISABLE_RTC_CPU_V << RTC_CNTL_DISABLE_RTC_CPU_S) -#define RTC_CNTL_DISABLE_RTC_CPU_V 0x00000001 -#define RTC_CNTL_DISABLE_RTC_CPU_S 31 - -/* RTC_CNTL_DATE_REG register - * version register - */ - -#define RTC_CNTL_DATE_REG (DR_REG_RTCCNTL_BASE + 0x1fc) - -/* RTC_CNTL_DATE : R/W; bitpos: [27:0]; default: 34607729; - * version register - */ - -#define RTC_CNTL_DATE 0x0fffffff -#define RTC_CNTL_DATE_M (RTC_CNTL_DATE_V << RTC_CNTL_DATE_S) -#define RTC_CNTL_DATE_V 0x0fffffff -#define RTC_CNTL_DATE_S 0 - -/* LDO SLAVE : R/W ;bitpos:[18:13] ; default: 6'd0 ; */ - -#define RTC_CNTL_SLAVE_PD 0x0000003F -#define RTC_CNTL_SLAVE_PD_M ((RTC_CNTL_SLAVE_PD_V)<<(RTC_CNTL_SLAVE_PD_S)) -#define RTC_CNTL_SLAVE_PD_V 0x3f -#define RTC_CNTL_SLAVE_PD_S 13 - -/* Deep sleep (power down digital domain) */ - -#define RTC_SLEEP_PD_DIG BIT(0) - -/* Power down RTC peripherals */ - -#define RTC_SLEEP_PD_RTC_PERIPH BIT(1) - -/* Power down RTC SLOW memory */ - -#define RTC_SLEEP_PD_RTC_SLOW_MEM BIT(2) - -/* Power down RTC FAST memory */ - -#define RTC_SLEEP_PD_RTC_FAST_MEM BIT(3) - -/* RTC FAST and SLOW memories are automatically - * powered up and down along with the CPU - */ - -#define RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU BIT(4) - -/* Power down VDDSDIO regulator */ - -#define RTC_SLEEP_PD_VDDSDIO BIT(5) - -/* Power down WIFI */ - -#define RTC_SLEEP_PD_WIFI BIT(6) - -/* Power down BT */ - -#define RTC_SLEEP_PD_BT BIT(7) - -/* Power down CPU when in lightsleep, but not restart */ - -#define RTC_SLEEP_PD_CPU BIT(8) - -/* Power down DIG peripherals */ - -#define RTC_SLEEP_PD_DIG_PERIPH BIT(9) - -/* Power down Internal 8M oscillator */ - -#define RTC_SLEEP_PD_INT_8M BIT(10) - -/* Power down main XTAL */ - -#define RTC_SLEEP_PD_XTAL BIT(11) - -/* These flags are not power domains, but will affect some sleep parameters */ - -#define RTC_SLEEP_DIG_USE_8M BIT(16) -#define RTC_SLEEP_USE_ADC_TESEN_MONITOR BIT(17) - -/* Avoid using ultra low power in deep sleep, in which RTCIO cannot - * be used as input, and RTCMEM can't work under high temperature - */ - -#define RTC_SLEEP_NO_ULTRA_LOW BIT(18) - -#endif /* __ARCH_XTENSA_SRC_ESP32S3_HARDWARE_ESP32S3_RTCCNTL_H */ diff --git a/arch/xtensa/src/esp32s3/hardware/esp32s3_soc.h b/arch/xtensa/src/esp32s3/hardware/esp32s3_soc.h index ec98ab84ee774..081a0f989eaea 100644 --- a/arch/xtensa/src/esp32s3/hardware/esp32s3_soc.h +++ b/arch/xtensa/src/esp32s3/hardware/esp32s3_soc.h @@ -61,7 +61,8 @@ /* Peripheral Clock */ -#define RTC_CLK_FREQ (20*1000000) +#define RTC_CLK_FREQ (20 * 1000000) +#define XTAL_CLK_FREQ (40 * 1000000) /* Core voltage needs to be increased in two cases: * 1. running at 240 MHz @@ -89,8 +90,6 @@ #define DPORT_SOC_CLK_SEL_PLL 1 #define DPORT_SOC_CLK_SEL_8M 2 -#define RTC_FAST_CLK_FREQ_8M 8500000 - #ifndef __ASSEMBLY__ /**************************************************************************** diff --git a/boards/Kconfig b/boards/Kconfig index b67776a957f77..6c77ccc761401 100644 --- a/boards/Kconfig +++ b/boards/Kconfig @@ -251,7 +251,7 @@ config ARCH_BOARD_ESP32_AUDIO_KIT depends on ARCH_CHIP_ESP32_A1S select ARCH_HAVE_LEDS select ARCH_HAVE_BUTTONS - select ARCH_HAVE_IRQBUTTONS if ESP32_GPIO_IRQ + select ARCH_HAVE_IRQBUTTONS if ESPRESSIF_GPIO_IRQ ---help--- The Ai-Thinker ESP32-Audio-Kit is a board with the ESP32-A1S module powered by ESP32-D0WD-V3 with 16MB of SPI Flash and 8MB PSRAM, and an @@ -263,7 +263,7 @@ config ARCH_BOARD_ESP32_DEVKITC depends on ARCH_CHIP_ESP32WROOM32 || ARCH_CHIP_ESP32WROOM32_8MB || ARCH_CHIP_ESP32WROOM32_16MB || ARCH_CHIP_ESP32WROVER || ARCH_CHIP_ESP32SOLO1 select ARCH_HAVE_LEDS select ARCH_HAVE_BUTTONS - select ARCH_HAVE_IRQBUTTONS if ESP32_GPIO_IRQ + select ARCH_HAVE_IRQBUTTONS if ESPRESSIF_GPIO_IRQ ---help--- The ESP32 is a dual-core system from Espressif with two Harvard architecture Xtensa LX6 CPUs. All embedded memory, external memory @@ -277,7 +277,7 @@ config ARCH_BOARD_HELTEC_WIFI_LORA32 depends on ARCH_CHIP_ESP32WROOM32 || ARCH_CHIP_ESP32WROOM32_8MB || ARCH_CHIP_ESP32WROOM32_16MB || ARCH_CHIP_ESP32WROVER || ARCH_CHIP_ESP32SOLO1 select ARCH_HAVE_LEDS select ARCH_HAVE_BUTTONS - select ARCH_HAVE_IRQBUTTONS if ESP32_GPIO_IRQ + select ARCH_HAVE_IRQBUTTONS if ESPRESSIF_GPIO_IRQ ---help--- This is a Heltec board with ESP32 and a SX1276 LoRa transceiver. @@ -291,7 +291,7 @@ config ARCH_BOARD_ESP32_ETHERNETKIT bool "Espressif ESP32 Ethernet Kit" depends on ARCH_CHIP_ESP32WROVER select ARCH_HAVE_BUTTONS - select ARCH_HAVE_IRQBUTTONS if ESP32_GPIO_IRQ + select ARCH_HAVE_IRQBUTTONS if ESPRESSIF_GPIO_IRQ ---help--- The ESP32-Ethernet-Kit is an Ethernet-to-Wi-Fi development board that enables Ethernet devices to be interconnected over Wi-Fi. At the same time, to provide @@ -303,7 +303,7 @@ config ARCH_BOARD_ESP32_LYRAT depends on ARCH_CHIP_ESP32WROVER select ARCH_HAVE_LEDS select ARCH_HAVE_BUTTONS - select ARCH_HAVE_IRQBUTTONS if ESP32_GPIO_IRQ + select ARCH_HAVE_IRQBUTTONS if ESPRESSIF_GPIO_IRQ ---help--- ESP32-LyraT is an open-source development board for Espressif Systems' Audio Development Framework (ADF). It is designed for smart speakers and smart-home @@ -313,7 +313,7 @@ config ARCH_BOARD_ESP32_PICO_KIT bool "Espressif ESP32-PICO-KIT V4" depends on ARCH_CHIP_ESP32PICOD4 select ARCH_HAVE_BUTTONS - select ARCH_HAVE_IRQBUTTONS if ESP32_GPIO_IRQ + select ARCH_HAVE_IRQBUTTONS if ESPRESSIF_GPIO_IRQ ---help--- ESP32-PICO-KIT is an ESP32-based mini development board produced by Espressif. The core of this board is ESP32-PICO-D4, a System-in-Package module with complete @@ -328,7 +328,7 @@ config ARCH_BOARD_ESP32_SPARROWKIT depends on ARCH_CHIP_ESP32WROVER select ARCH_HAVE_LEDS select ARCH_HAVE_BUTTONS - select ARCH_HAVE_IRQBUTTONS if ESP32_GPIO_IRQ + select ARCH_HAVE_IRQBUTTONS if ESPRESSIF_GPIO_IRQ ---help--- ESP32-SPARROW-KIT is a custom-made board based on Espressif's ESP32WROVER chip and built upon the ESP32-WROVERKIT board. It is designed for a university @@ -345,7 +345,7 @@ config ARCH_BOARD_ESP32_WROVERKIT depends on ARCH_CHIP_ESP32WROVER select ARCH_HAVE_LEDS select ARCH_HAVE_BUTTONS - select ARCH_HAVE_IRQBUTTONS if ESP32_GPIO_IRQ + select ARCH_HAVE_IRQBUTTONS if ESPRESSIF_GPIO_IRQ ---help--- ESP-WROVER-KIT is an ESP32-based development board produced by Espressif. ESP-WROVER-KIT features the following integrated components: @@ -364,7 +364,7 @@ config ARCH_BOARD_LILYGO_TBEAM_LORA_GPS depends on ARCH_CHIP_ESP32WROOM32 select ARCH_HAVE_LEDS select ARCH_HAVE_BUTTONS - select ARCH_HAVE_IRQBUTTONS if ESP32_GPIO_IRQ + select ARCH_HAVE_IRQBUTTONS if ESPRESSIF_GPIO_IRQ ---help--- LilyGO_TBeam_V1.1 LoRa/GPS is an ESP32 board with LoRa and GPS. More info: https://github.com/Xinyuan-LilyGO/LilyGo-LoRa-Series/ @@ -374,7 +374,7 @@ config ARCH_BOARD_TTGO_LORA_ESP32 depends on ARCH_CHIP_ESP32WROOM32 select ARCH_HAVE_LEDS select ARCH_HAVE_BUTTONS - select ARCH_HAVE_IRQBUTTONS if ESP32_GPIO_IRQ + select ARCH_HAVE_IRQBUTTONS if ESPRESSIF_GPIO_IRQ ---help--- TTGO-LoRa-SX1276-ESP32 is an ESP32 board with LoRa. Usually it comes with an OLED display, but there are options without @@ -402,7 +402,7 @@ config ARCH_BOARD_TTGO_T_DISPLAY_ESP32 depends on ARCH_CHIP_ESP32WROOM32 || ARCH_CHIP_ESP32WROOM32_8MB || ARCH_CHIP_ESP32WROOM32_16MB || ARCH_CHIP_ESP32WROVER || ARCH_CHIP_ESP32SOLO1 select ARCH_HAVE_LEDS select ARCH_HAVE_BUTTONS - select ARCH_HAVE_IRQBUTTONS if ESP32_GPIO_IRQ + select ARCH_HAVE_IRQBUTTONS if ESPRESSIF_GPIO_IRQ ---help--- TTGO-T-DISPLAY-ESP32 is an ESP32 with a TFT Display. This port is for board version 1.1, more info: @@ -461,7 +461,7 @@ config ARCH_BOARD_ESP32S2_KALUGA_1 depends on ARCH_CHIP_ESP32S2WROVER select ARCH_HAVE_LEDS select ARCH_HAVE_BUTTONS - select ARCH_HAVE_IRQBUTTONS if ESP32S2_GPIO_IRQ + select ARCH_HAVE_IRQBUTTONS if ESPRESSIF_GPIO_IRQ ---help--- This is the ESP32-S2-Kaluga-1 board @@ -470,7 +470,7 @@ config ARCH_BOARD_ESP32S2_SAOLA_1 depends on ARCH_CHIP_ESP32S2WROVER select ARCH_HAVE_LEDS select ARCH_HAVE_BUTTONS - select ARCH_HAVE_IRQBUTTONS if ESP32S2_GPIO_IRQ + select ARCH_HAVE_IRQBUTTONS if ESPRESSIF_GPIO_IRQ ---help--- This is the ESP32-S2-Saola-1 board @@ -479,7 +479,7 @@ config ARCH_BOARD_FRANZININHO_WIFI depends on ARCH_CHIP_ESP32S2WROVER select ARCH_HAVE_LEDS select ARCH_HAVE_BUTTONS - select ARCH_HAVE_IRQBUTTONS if ESP32S2_GPIO_IRQ + select ARCH_HAVE_IRQBUTTONS if ESPRESSIF_GPIO_IRQ ---help--- Franzininho Wi-Fi is a development board to evaluate the ESP32-S2 SoC @@ -488,7 +488,7 @@ config ARCH_BOARD_ESP32S3_DEVKIT depends on ARCH_CHIP_ESP32S3WROOM1N4 || ARCH_CHIP_ESP32S3MINI1N8 || ARCH_CHIP_ESP32S3WROOM1N8R2 || ARCH_CHIP_ESP32S3WROOM1N16R8 || ARCH_CHIP_ESP32S3WROOM2N16R8V || ARCH_CHIP_ESP32S3WROOM2N32R8V || ARCH_CHIP_ESP32S3CUSTOM || ARCH_CHIP_ESP32S3WROOM1N8R8 select ARCH_HAVE_LEDS select ARCH_HAVE_BUTTONS - select ARCH_HAVE_IRQBUTTONS if ESP32S3_GPIO_IRQ + select ARCH_HAVE_IRQBUTTONS if ESPRESSIF_GPIO_IRQ ---help--- The ESP32-S3 DevKit features the ESP32-S3 CPU with dual Xtensa LX7 cores. It comes in two flavors, the ESP32-S3-DevKitM-1 and the ESP32-S3-DevKitC-1. @@ -500,7 +500,7 @@ config ARCH_BOARD_ESP32S3_8048S043 bool "ESP32-S3 8048S043" depends on ARCH_CHIP_ESP32S3WROOM1N4 || ARCH_CHIP_ESP32S3MINI1N8 || ARCH_CHIP_ESP32S3WROOM1N8R2 || ARCH_CHIP_ESP32S3WROOM1N16R8 || ARCH_CHIP_ESP32S3WROOM2N16R8V || ARCH_CHIP_ESP32S3WROOM2N32R8V || ARCH_CHIP_ESP32S3CUSTOM || ARCH_CHIP_ESP32S3WROOM1N8R8 select ARCH_HAVE_BUTTONS - select ARCH_HAVE_IRQBUTTONS if ESP32S3_GPIO_IRQ + select ARCH_HAVE_IRQBUTTONS if ESPRESSIF_GPIO_IRQ ---help--- The ESP32-S3 8048S043 features the ESP32-S3 CPU with dual Xtensa LX7 cores. @@ -509,7 +509,7 @@ config ARCH_BOARD_ESP32S3_EYE depends on ARCH_CHIP_ESP32S3WROOM1N4 || ARCH_CHIP_ESP32S3CUSTOM select ARCH_HAVE_LEDS select ARCH_HAVE_BUTTONS - select ARCH_HAVE_IRQBUTTONS if ESP32S3_GPIO_IRQ + select ARCH_HAVE_IRQBUTTONS if ESPRESSIF_GPIO_IRQ ---help--- The ESP32-S3-EYE is a small-sized AI development board produced by Espressif featuring the ESP32-S3 CPU with a 2-Megapixel camera, an LCD display, @@ -520,7 +520,7 @@ config ARCH_BOARD_ESP32S3_LCD_EV depends on ARCH_CHIP_ESP32S3WROOM2N16R8V || ARCH_CHIP_ESP32S3WROOM2N32R8V || ARCH_CHIP_ESP32S3WROOM1N16R16V || ARCH_CHIP_ESP32S3CUSTOM select ARCH_HAVE_LEDS select ARCH_HAVE_BUTTONS - select ARCH_HAVE_IRQBUTTONS if ESP32S3_GPIO_IRQ + select ARCH_HAVE_IRQBUTTONS if ESPRESSIF_GPIO_IRQ ---help--- ESP32-S3-LCD-EV is an ESP32-S3-based development board with a touchscreen. Together with different subboards, ESP32-S3-LCD-EV-Board can drive LCDs with IIC, @@ -537,7 +537,7 @@ config ARCH_BOARD_ESP32S3_LHCBIT bool "ESP32-S3 LHCBit" depends on ARCH_CHIP_ESP32S3WROOM1N16R8 select ARCH_HAVE_BUTTONS - select ARCH_HAVE_IRQBUTTONS if ESP32S3_GPIO_IRQ + select ARCH_HAVE_IRQBUTTONS if ESPRESSIF_GPIO_IRQ ---help--- The ESP32-S3 LHCBit features the ESP32-S3 CPU with dual Xtensa LX7 cores. @@ -546,7 +546,7 @@ config ARCH_BOARD_ESP32S3_XIAO depends on ARCH_CHIP_ESP32S3WROOM1N16R8 || ARCH_CHIP_ESP32S3WROOM1N8R8 select ARCH_HAVE_LEDS select ARCH_HAVE_BUTTONS - select ARCH_HAVE_IRQBUTTONS if ESP32S3_GPIO_IRQ + select ARCH_HAVE_IRQBUTTONS if ESPRESSIF_GPIO_IRQ ---help--- The XIAO-ESP32S3 from Seeed Studio features the ESP32-S3 CPU with dual Xtensa LX7 cores, with 8MiB Octal SPI PSRAM and 8MiB or 16MiB flash. @@ -556,7 +556,7 @@ config ARCH_BOARD_ESP32S3_BOX depends on ARCH_CHIP_ESP32S3WROOM2N16R8V || ARCH_CHIP_ESP32S3WROOM2N32R8V || ARCH_CHIP_ESP32S3CUSTOM select ARCH_HAVE_LEDS select ARCH_HAVE_BUTTONS - select ARCH_HAVE_IRQBUTTONS if ESP32S3_GPIO_IRQ + select ARCH_HAVE_IRQBUTTONS if ESPRESSIF_GPIO_IRQ ---help--- The ESP-BOX is an advanced AIoT, Edge AI, and IIoT applications development platform released by Espressif Systems. The board is built on Espressif’s powerful ESP32-S3 @@ -570,7 +570,7 @@ config ARCH_BOARD_ESP32S3_KORVO_2 depends on ARCH_CHIP_ESP32S3WROOM1N16R8 || ARCH_CHIP_ESP32S3WROOM1N8R8 select ARCH_HAVE_LEDS select ARCH_HAVE_BUTTONS - select ARCH_HAVE_IRQBUTTONS if ESP32S3_GPIO_IRQ + select ARCH_HAVE_IRQBUTTONS if ESPRESSIF_GPIO_IRQ ---help--- The ESP32-S3-Korvo-2 is a multimedia development board based on the ESP32-S3 chip. It is equipped with a two-microphone array which is suitable for voice recognition @@ -585,7 +585,7 @@ config ARCH_BOARD_ESP32S3_MEADOW depends on ARCH_CHIP_ESP32S3WROOM1N4 || ARCH_CHIP_ESP32S3CUSTOM select ARCH_HAVE_LEDS select ARCH_HAVE_BUTTONS - select ARCH_HAVE_IRQBUTTONS if ESP32S3_GPIO_IRQ + select ARCH_HAVE_IRQBUTTONS if ESPRESSIF_GPIO_IRQ ---help--- The ESP32-S3-Meadow is a small-sized board produced by WildernessLabs featuring the ESP32-S3 CPU with 32MiB Octal SPI PSRAM and 64 MiB flash. @@ -595,7 +595,7 @@ config ARCH_BOARD_ESP32S3_LCKFB_SZPI depends on ARCH_CHIP_ESP32S3WROOM1N16R8 select ARCH_HAVE_LEDS select ARCH_HAVE_BUTTONS - select ARCH_HAVE_IRQBUTTONS if ESP32S3_GPIO_IRQ + select ARCH_HAVE_IRQBUTTONS if ESPRESSIF_GPIO_IRQ config ARCH_BOARD_ESP32C6_DEVKITC bool "Espressif ESP32-C6-DevKitC-1" diff --git a/boards/xtensa/esp32/common/include/esp32_board_rmt.h b/boards/xtensa/esp32/common/include/esp32_board_rmt.h index f380ecca16c58..ead412c36f898 100644 --- a/boards/xtensa/esp32/common/include/esp32_board_rmt.h +++ b/boards/xtensa/esp32/common/include/esp32_board_rmt.h @@ -61,7 +61,6 @@ extern "C" * Initialize the RMT peripheral and register an RX device. * * Input Parameters: - * ch - The RMT's channel that will be used * pin - The pin used for the RX channel * * Returned Value: @@ -69,7 +68,7 @@ extern "C" * ****************************************************************************/ -int board_rmt_rxinitialize(int ch, int pin); +int board_rmt_rxinitialize(int pin); /**************************************************************************** * Name: board_rmt_txinitialize @@ -78,7 +77,6 @@ int board_rmt_rxinitialize(int ch, int pin); * Initialize the RMT peripheral and register an TX device. * * Input Parameters: - * ch - The RMT's channel that will be used * pin - The pin used for the TX channel * * Returned Value: @@ -86,7 +84,7 @@ int board_rmt_rxinitialize(int ch, int pin); * ****************************************************************************/ -int board_rmt_txinitialize(int ch, int pin); +int board_rmt_txinitialize(int pin); #endif /* CONFIG_ESP_RMT */ diff --git a/boards/xtensa/esp32/common/scripts/esp32_sections.ld b/boards/xtensa/esp32/common/scripts/esp32_sections.ld index 03ca37c697699..56c026f8d11e3 100644 --- a/boards/xtensa/esp32/common/scripts/esp32_sections.ld +++ b/boards/xtensa/esp32/common/scripts/esp32_sections.ld @@ -170,6 +170,7 @@ SECTIONS *libarch.a:*periph_ctrl.*(.text .text.* .literal .literal.*) *libarch.a:*clk.*(.text .text.* .literal .literal.*) *libarch.a:*efuse_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*efuse_utility.*(.text .text.* .literal .literal.*) *libarch.a:*esp_clk.*(.text .text.* .literal .literal.*) *libarch.a:*esp_clk_tree.*(.text .text.* .literal .literal.*) *libarch.a:*esp_clk_tree_common.*(.text .text.* .literal .literal.*) @@ -221,12 +222,12 @@ SECTIONS *libarch.a:*log_write.*(.literal.esp_log_writev .text.esp_log_writev) *libarch.a:*cpu_region_protect.*(.text .text.* .literal .literal.*) *libarch.a:*flash_qio_mode.*(.text .text.* .literal .literal.*) + *libarch.a:xtensa_intr.*(.literal .literal.* .text .text.*) #ifdef CONFIG_STACK_CANARIES *libc.a:lib_stackchk.*(.literal .text .literal.* .text.*) #endif *libarch.a:esp32_cpuindex.*(.literal .text .literal.* .text.*) - *libarch.a:esp32_irq.*(.literal .text .literal.* .text.*) *libarch.a:esp32_user.*(.literal .text .literal.* .text.*) *libarch.a:xtensa_assert.*(.literal .text .literal.* .text.*) *libarch.a:xtensa_cpuint.*(.literal .text .literal.* .text.*) @@ -235,10 +236,12 @@ SECTIONS *libarch.a:xtensa_modifyreg32.*(.literal .text .literal.* .text.*) *libarch.a:xtensa_saveusercontext.*(.literal .text .literal.* .text.*) *libarch.a:xtensa_testset.*(.literal .text .literal.* .text.*) + *libarch.a:rtc_sleep.*(.literal.rtc_sleep_start .text.rtc_sleep_start) *libc.a:lib_assert.*(.literal .text .literal.* .text.*) *libc.a:lib_utsname.*(.literal .text .literal.* .text.*) *libc.a:sq_remlast.*(.literal .text .literal.* .text.*) + *libc.a:arch_atomic.*(.text .text.* .literal .literal.*) *libdrivers.a:syslog_flush.*(.literal .text .literal.* .text.*) @@ -266,11 +269,20 @@ SECTIONS *libarch.a:spi_flash_os_func_noos.*(.literal .literal.* .text .text.*) *libarch.a:spi_flash_os_func_app.*(.literal .literal.* .text .text.*) *libarch.a:flash_brownout_hook.*(.literal .literal.* .text .text.*) - *libarch.a:esp_cache.*(.literal .literal.* .text .text.*) + *libarch.a:esp_cache_utils.*(.literal .literal.* .text .text.*) *libarch.a:cache_esp32.*(.literal .literal.* .text .text.*) *libarch.a:cache_hal_esp32.*(.literal .literal.* .text .text.*) *libarch.a:cache_utils.*(.literal .literal.* .text .text.*) *libarch.a:memspi_host_driver.*(.literal .literal.* .text .text.*) + *libarch.a:critical_section.*(.literal .literal.* .text .text.*) + *libarch.a:os.*(.literal.nuttx_enter_critical .text.nuttx_enter_critical) + *libarch.a:os.*(.literal.nuttx_exit_critical .text.nuttx_exit_critical) + *libarch.a:intr_alloc.*(.literal.esp_intr_get_intno .text.esp_intr_get_intno) + *libarch.a:intr_alloc.*(.literal.esp_intr_get_cpu .text.esp_intr_get_cpu) + *libarch.a:interrupt.*(.literal.intr_handler_get .text.intr_handler_get) + *libarch.a:interrupt.*(.literal.intr_handler_get_arg .text.intr_handler_get_arg) + *libarch.a:interrupt.*(.literal.intr_get_item .text.intr_get_item) + *libarch.a:interrupt.*(.literal.intr_handler_get_arg .text.intr_handler_get_arg) *(.wifirxiram .wifirxiram.*) *(.wifi0iram .wifi0iram.*) @@ -441,6 +453,7 @@ SECTIONS *libarch.a:*regi2c_ctrl.*(.rodata .rodata.*) *libarch.a:*uart_hal_iram.*(.rodata .rodata.*) *libarch.a:*wdt_hal_iram.*(.rodata .rodata.*) + *libarch.a:*efuse_utility.*(.rodata .rodata.*) *libarch.a:*bootloader_banner_wrap.*(.rodata .rodata.*) *libarch.a:*bootloader_init.*(.rodata .rodata.*) *libarch.a:*bootloader_common.*(.rodata .rodata.*) @@ -484,11 +497,15 @@ SECTIONS *libarch.a:spi_flash_os_func_noos.*(.rodata .rodata.*) *libarch.a:spi_flash_os_func_app.*(.rodata .rodata.*) *libarch.a:flash_brownout_hook.*(.rodata .rodata.*) - *libarch.a:esp_cache.*(.rodata .rodata.*) + *libarch.a:esp_cache_utils.*(.rodata .rodata.*) *libarch.a:cache_esp32.*(.rodata .rodata.*) *libarch.a:cache_utils.*(.rodata .rodata.*) *libarch.a:cache_hal_esp32.*(.rodata .rodata.*) *libarch.a:memspi_host_driver.*(.rodata .rodata.*) + *libarch.a:critical_section.*(.rodata .rodata.*) + *libarch.a:os.*(.rodata.g_int_flags_count .rodata.g_int_flags) + + *libc.a:arch_atomic.*(.rodata .rodata.*) _edata = ABSOLUTE(.); _data_end = ABSOLUTE(.); @@ -614,9 +631,7 @@ SECTIONS . = ALIGN(4); _sinit = ABSOLUTE(.); - __init_array_start = ABSOLUTE(.); KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .ctors SORT(.ctors.*))) - __init_array_end = ABSOLUTE(.); _einit = ABSOLUTE(.); /* Addresses of memory regions reserved via SOC_RESERVE_MEMORY_REGION() */ @@ -709,6 +724,7 @@ SECTIONS .rtc.text : { . = ALIGN(4); + _rtc_data_start = ABSOLUTE(.); *(.rtc.literal .rtc.text) } >rtc_iram_seg AT>ROM @@ -725,21 +741,66 @@ SECTIONS _srtcheap = ABSOLUTE(.); } >rtc_slow_seg AT>ROM - /* - * This section holds RTC data that should have fixed addresses. - * The data are not initialized at power-up and are retained during deep sleep. - */ - .rtc_reserved (NOLOAD): + .rtc.force_slow : + { + . = ALIGN(4); + _rtc_force_slow_start = ABSOLUTE(.); + *(.rtc.force_slow .rtc.force_slow.*) + . = ALIGN(4); + _rtc_force_slow_end = ABSOLUTE(.); + } >rtc_slow_seg AT>ROM + + /* This section holds RTC FAST data that should have fixed addresses. + * The data are not initialized at power-up and are retained during deep + * sleep. + */ + + .rtc_fast_reserved (NOLOAD): { . = ALIGN(4); - _rtc_reserved_start = ABSOLUTE(.); + _rtc_fast_reserved_start = ABSOLUTE(.); + /* New data can only be added here to ensure existing data are not moved. - Because data have adhered to the end of the segment and code is relied on it. - >> put new data here << */ + * Because data have adhered to the end of the segment and code is relied + * on it. + * >> put new data here << + */ - *(.rtc_timer_data_in_rtc_mem .rtc_timer_data_in_rtc_mem.*) KEEP(*(.bootloader_data_rtc_mem .bootloader_data_rtc_mem.*)) - _rtc_reserved_end = ABSOLUTE(.); - } > rtc_reserved_seg + + _rtc_fast_reserved_end = ABSOLUTE(.); + } > rtc_fast_reserved_seg + + _rtc_fast_reserved_length = _rtc_fast_reserved_end - _rtc_fast_reserved_start; + ASSERT((_rtc_fast_reserved_length <= LENGTH(rtc_fast_reserved_seg)), + "RTC FAST reserved segment data does not fit.") + + /* This section holds RTC SLOW data that should have fixed addresses. + * The data are not initialized at power-up and are retained during deep + * sleep. + */ + + .rtc_slow_reserved (NOLOAD): + { + . = ALIGN(4); + _rtc_slow_reserved_start = ABSOLUTE(.); + + /* New data can only be added here to ensure existing data are not moved. + * Because data have adhered to the end of the segment and code is relied + * on it. + * >> put new data here << + */ + + *(.rtc_timer_data_in_rtc_mem .rtc_timer_data_in_rtc_mem.*) + + _rtc_slow_reserved_end = ABSOLUTE(.); + } > rtc_slow_reserved_seg + + _rtc_slow_reserved_length = _rtc_slow_reserved_end - _rtc_slow_reserved_start; + _rtc_reserved_length = _rtc_slow_reserved_length; + + /* Get size of rtc slow data */ + + _rtc_slow_length = (_rtc_force_slow_end - _rtc_data_start); } diff --git a/boards/xtensa/esp32/common/scripts/flat_memory.ld b/boards/xtensa/esp32/common/scripts/flat_memory.ld index bb4895fe12cc3..49c7f90a2a4cb 100644 --- a/boards/xtensa/esp32/common/scripts/flat_memory.ld +++ b/boards/xtensa/esp32/common/scripts/flat_memory.ld @@ -49,6 +49,8 @@ #define RTC_TIMER_RESERVE_RTC (24) #define RESERVE_RTC_MEM (RTC_TIMER_RESERVE_RTC) +#define ESP_BOOTLOADER_RESERVE_RTC (0x0) + MEMORY { #ifdef CONFIG_ESP32_APP_FORMAT_MCUBOOT @@ -148,15 +150,32 @@ MEMORY rtc_iram_seg (RWX) : org = 0x400c0000, len = 0x2000 + /* RTC fast memory (same block as above, rtc_iram_seg), viewed from + * data bus. + */ + + rtc_data_seg(RW) : org = 0x3ff80000, len = 0x2000 - RESERVE_RTC_MEM + /* RTC slow memory (data accessible). Persists over deep sleep. * Start of RTC slow memory is reserved for ULP co-processor code + data, * if enabled. */ + /* We reduced the size of rtc_iram_seg and rtc_data_seg by + * ESP_BOOTLOADER_RESERVE_RTC value. It reserves the amount of RTC fast + * memory that we use for this memory segment. + * This segment is intended for keeping bootloader rtc data + * (s_bootloader_retain_mem, when a Kconfig option is on). The aim of this + * is to keep data that will not be moved around and have a fixed address. + * org = 0x3ff80000 + 0x2000 - ESP_BOOTLOADER_RESERVE_RTC == SOC_RTC_DRAM_HIGH - sizeof(rtc_retain_mem_t) + */ + + rtc_fast_reserved_seg(RW) : org = 0x3ff80000 + 0x2000 - ESP_BOOTLOADER_RESERVE_RTC, len = ESP_BOOTLOADER_RESERVE_RTC + rtc_slow_seg (RW) : org = 0x50000000 + CONFIG_ESP32_ULP_COPROC_RESERVE_MEM, len = 0x1000 - CONFIG_ESP32_ULP_COPROC_RESERVE_MEM - rtc_reserved_seg(RW) : org = 0x50000000 + 0x2000 - RESERVE_RTC_MEM, len = RESERVE_RTC_MEM + rtc_slow_reserved_seg(RW) : org = 0x50000000 + 0x2000 - RESERVE_RTC_MEM, len = RESERVE_RTC_MEM /* External memory, including data and text */ diff --git a/boards/xtensa/esp32/common/scripts/kernel-space.ld b/boards/xtensa/esp32/common/scripts/kernel-space.ld index fb0ab0e6c761f..4a98e369ce3e4 100644 --- a/boards/xtensa/esp32/common/scripts/kernel-space.ld +++ b/boards/xtensa/esp32/common/scripts/kernel-space.ld @@ -125,12 +125,39 @@ SECTIONS *libkarch.a:xtensa_testset.*(.literal .text .literal.* .text.*) *libkarch.a:esp_app_desc.*(.literal .text .literal.* .text.*) + *libc.a:arch_atomic.*(.literal .text .literal.* .text.*) + *libsched.a:sched_suspendscheduler.*(.literal .text .literal.* .text.*) *libsched.a:sched_note.*(.literal .text .literal.* .text.*) *libsched.a:sched_thistask.*(.literal .text .literal.* .text.*) *libsched.a:spinlock.*(.literal .text .literal.* .text.*) *libsched.a:irq_csection.*(.literal .text .literal.* .text.*) *libsched.a:irq_dispatch.*(.literal .text .literal.* .text.*) + *libkarch.a:esp_spiflash.*(.literal .text .literal.* .text.*) + *libkarch.a:esp_flash_api.*(.text .text.* .literal .literal.*) + *libkarch.a:esp_flash_spi_init.*(.text .text.* .literal .literal.*) + *libkarch.a:spi_flash_hal_iram.*(.literal .literal.* .text .text.*) + *libkarch.a:spi_flash_encrypt_hal_iram.*(.text .text.* .literal .literal.*) + *libkarch.a:spi_flash_hal_gpspi.*(.literal .literal.* .text .text.*) + *libkarch.a:spi_flash_chip*.*(.literal .literal.* .text .text.*) + *libkarch.a:spi_flash_wrap.*(.literal .literal.* .text .text.*) + *libkarch.a:spi_flash_os_func_noos.*(.literal .literal.* .text .text.*) + *libkarch.a:spi_flash_os_func_app.*(.literal .literal.* .text .text.*) + *libkarch.a:flash_brownout_hook.*(.literal .literal.* .text .text.*) + *libkarch.a:esp_cache_utils.*(.literal .literal.* .text .text.*) + *libkarch.a:cache_esp32.*(.literal .literal.* .text .text.*) + *libkarch.a:cache_hal_esp32.*(.literal .literal.* .text .text.*) + *libkarch.a:cache_utils.*(.literal .literal.* .text .text.*) + *libkarch.a:memspi_host_driver.*(.literal .literal.* .text .text.*) + *libkarch.a:critical_section.*(.literal .literal.* .text .text.*) + *libkarch.a:os.*(.literal.nuttx_enter_critical .text.nuttx_enter_critical) + *libkarch.a:os.*(.literal.nuttx_exit_critical .text.nuttx_exit_critical) + *libkarch.a:intr_alloc.*(.literal.esp_intr_get_intno .text.esp_intr_get_intno) + *libkarch.a:intr_alloc.*(.literal.esp_intr_get_cpu .text.esp_intr_get_cpu) + *libkarch.a:interrupt.*(.literal.intr_handler_get .text.intr_handler_get) + *libkarch.a:interrupt.*(.literal.intr_handler_get_arg .text.intr_handler_get_arg) + *libkarch.a:interrupt.*(.literal.intr_get_item .text.intr_get_item) + *libkarch.a:interrupt.*(.literal.intr_handler_get_arg .text.intr_handler_get_arg) *(.wifirxiram .wifirxiram.*) *(.wifi0iram .wifi0iram.*) @@ -231,12 +258,17 @@ SECTIONS KEEP (*(.jcr)) *(.dram1 .dram1.*) *libphy.a:(.rodata .rodata.*) + *libkarch.a:esp_cache_utils.*(.rodata .rodata.*) *libkarch.a:esp_spiflash.*(.rodata .rodata.*) *libkarch.a:*esp_clk.*(.rodata .rodata.*) *libkarch.a:xtensa_cpupause.*(.rodata .rodata.*) *libkarch.a:xtensa_copystate.*(.rodata .rodata.*) *libkarch.a:xtensa_interruptcontext.*(.rodata .rodata.*) *libkarch.a:xtensa_testset.*(.rodata .rodata.*) + *libkarch.a:spi_flash_chip*.*(.rodata .rodata.*) + *libkarch.a:critical_section.*(.rodata .rodata.*) + *libkarch.a:os.*(.rodata.g_int_flags_count .rodata.g_int_flags) + *libkc.a:arch_atomic.*(.rodata .rodata.*) *libsched.a:sched_suspendscheduler.*(.rodata .rodata.*) *libsched.a:sched_thistask.*(.rodata .rodata.*) @@ -335,20 +367,85 @@ SECTIONS _etext = .; } >KIROM - /* - * This section holds RTC data that should have fixed addresses. - * The data are not initialized at power-up and are retained during deep sleep. - */ - .rtc_reserved (NOLOAD): + .rtc.text : { . = ALIGN(4); - _rtc_reserved_start = ABSOLUTE(.); + _rtc_data_start = ABSOLUTE(.); + *(.rtc.literal .rtc.text) + } >rtc_iram_seg AT>ROM + + .rtc.data : + { + *(.rtc.data) + *(.rtc.data.*) + *(.rtc.rodata) + *(.rtc.rodata.*) + + /* Whatever is left from the RTC memory is used as a special heap. */ + + . = ALIGN (4); + _srtcheap = ABSOLUTE(.); + } >rtc_slow_seg AT>ROM + + .rtc.force_slow : + { + . = ALIGN(4); + _rtc_force_slow_start = ABSOLUTE(.); + *(.rtc.force_slow .rtc.force_slow.*) + . = ALIGN(4); + _rtc_force_slow_end = ABSOLUTE(.); + } >rtc_slow_seg AT>ROM + + /* This section holds RTC FAST data that should have fixed addresses. + * The data are not initialized at power-up and are retained during deep + * sleep. + */ + + .rtc_fast_reserved (NOLOAD): + { + . = ALIGN(4); + _rtc_fast_reserved_start = ABSOLUTE(.); + /* New data can only be added here to ensure existing data are not moved. - Because data have adhered to the end of the segment and code is relied on it. - >> put new data here << */ + * Because data have adhered to the end of the segment and code is relied + * on it. + * >> put new data here << + */ - *(.rtc_timer_data_in_rtc_mem .rtc_timer_data_in_rtc_mem.*) KEEP(*(.bootloader_data_rtc_mem .bootloader_data_rtc_mem.*)) - _rtc_reserved_end = ABSOLUTE(.); - } > rtc_reserved_seg + + _rtc_fast_reserved_end = ABSOLUTE(.); + } > rtc_fast_reserved_seg + + _rtc_fast_reserved_length = _rtc_fast_reserved_end - _rtc_fast_reserved_start; + ASSERT((_rtc_fast_reserved_length <= LENGTH(rtc_fast_reserved_seg)), + "RTC FAST reserved segment data does not fit.") + + /* This section holds RTC SLOW data that should have fixed addresses. + * The data are not initialized at power-up and are retained during deep + * sleep. + */ + + .rtc_slow_reserved (NOLOAD): + { + . = ALIGN(4); + _rtc_slow_reserved_start = ABSOLUTE(.); + + /* New data can only be added here to ensure existing data are not moved. + * Because data have adhered to the end of the segment and code is relied + * on it. + * >> put new data here << + */ + + *(.rtc_timer_data_in_rtc_mem .rtc_timer_data_in_rtc_mem.*) + + _rtc_slow_reserved_end = ABSOLUTE(.); + } > rtc_slow_reserved_seg + + _rtc_slow_reserved_length = _rtc_slow_reserved_end - _rtc_slow_reserved_start; + _rtc_reserved_length = _rtc_slow_reserved_length; + + /* Get size of rtc slow data */ + + _rtc_slow_length = (_rtc_force_slow_end - _rtc_data_start); } diff --git a/boards/xtensa/esp32/common/scripts/legacy_sections.ld b/boards/xtensa/esp32/common/scripts/legacy_sections.ld index af254b44b414b..59986666ceeb9 100644 --- a/boards/xtensa/esp32/common/scripts/legacy_sections.ld +++ b/boards/xtensa/esp32/common/scripts/legacy_sections.ld @@ -79,7 +79,6 @@ SECTIONS *libc.a:lib_stackchk.*(.literal .text .literal.* .text.*) #endif *libarch.a:esp32_cpuindex.*(.literal .text .literal.* .text.*) - *libarch.a:esp32_irq.*(.literal .text .literal.* .text.*) *libarch.a:esp32_spicache.*(.literal .text .literal.* .text.*) *libarch.a:esp32_spiflash.*(.literal .text .literal.* .text.*) *libarch.a:esp32_user.*(.literal .text .literal.* .text.*) @@ -95,6 +94,7 @@ SECTIONS *libc.a:lib_assert.*(.literal .text .literal.* .text.*) *libc.a:lib_utsname.*(.literal .text .literal.* .text.*) *libc.a:sq_remlast.*(.literal .text .literal.* .text.*) + *libc.a:arch_atomic.*(.literal .text .literal.* .text.*) *libdrivers.a:syslog_flush.*(.literal .text .literal.* .text.*) @@ -287,6 +287,8 @@ SECTIONS *libsched.a:irq_csection.*(.rodata .rodata.*) *libsched.a:irq_dispatch.*(.rodata .rodata.*) + *libc.a:arch_atomic.*(.rodata .rodata.*) + . = ALIGN(4); _edata = ABSOLUTE(.); diff --git a/boards/xtensa/esp32/common/scripts/mcuboot_sections.ld b/boards/xtensa/esp32/common/scripts/mcuboot_sections.ld index da9ecfc0a5dc2..c1c7569f4c4cd 100644 --- a/boards/xtensa/esp32/common/scripts/mcuboot_sections.ld +++ b/boards/xtensa/esp32/common/scripts/mcuboot_sections.ld @@ -178,6 +178,7 @@ SECTIONS *libarch.a:*esp_loader.*(.text .text.* .literal .literal.*) *libc.a:sq_remlast.*(.literal .text .literal.* .text.*) + *libc.a:arch_atomic.*(.literal .text .literal.* .text.*) *(.wifirxiram .wifirxiram.*) *(.wifirxiram .wifi0iram.*) @@ -254,6 +255,7 @@ SECTIONS *libarch.a:*esp_loader.*(.rodata .rodata.*) *libarch.a:*mmu_hal.*(.rodata .rodata.*) *libarch.a:*uart_hal.*(.rodata .rodata.*) + *libc.a:arch_atomic.*(.rodata .rodata.*) _edata = ABSOLUTE(.); . = ALIGN(4); diff --git a/boards/xtensa/esp32/common/scripts/protected_memory.ld b/boards/xtensa/esp32/common/scripts/protected_memory.ld index bdb8f044b6949..08c7b60b13b15 100644 --- a/boards/xtensa/esp32/common/scripts/protected_memory.ld +++ b/boards/xtensa/esp32/common/scripts/protected_memory.ld @@ -36,6 +36,10 @@ #include "esp32_aliases.ld" +#define RTC_TIMER_RESERVE_RTC (24) +#define RESERVE_RTC_MEM (RTC_TIMER_RESERVE_RTC) +#define ESP_BOOTLOADER_RESERVE_RTC (0x0) + MEMORY { metadata (RX) : org = 0x0, len = 0x18 @@ -104,4 +108,35 @@ MEMORY KDROM (R) : org = 0x3f400020, len = 0x80000 - 0x20 UDROM (R) : org = 0x3f480018, len = 0x80000 - ORIGIN(ROM) + + /* RTC fast memory (executable). Persists over deep sleep. */ + + rtc_iram_seg (RWX) : org = 0x400c0000, len = 0x2000 + + /* RTC fast memory (same block as above, rtc_iram_seg), viewed from + * data bus. + */ + + rtc_data_seg(RW) : org = 0x3ff80000, len = 0x2000 - RESERVE_RTC_MEM + + /* RTC slow memory (data accessible). Persists over deep sleep. + * Start of RTC slow memory is reserved for ULP co-processor code + data, + * if enabled. + */ + + /* We reduced the size of rtc_iram_seg and rtc_data_seg by + * ESP_BOOTLOADER_RESERVE_RTC value. It reserves the amount of RTC fast + * memory that we use for this memory segment. + * This segment is intended for keeping bootloader rtc data + * (s_bootloader_retain_mem, when a Kconfig option is on). The aim of this + * is to keep data that will not be moved around and have a fixed address. + * org = 0x3ff80000 + 0x2000 - ESP_BOOTLOADER_RESERVE_RTC == SOC_RTC_DRAM_HIGH - sizeof(rtc_retain_mem_t) + */ + + rtc_fast_reserved_seg(RW) : org = 0x3ff80000 + 0x2000 - ESP_BOOTLOADER_RESERVE_RTC, len = ESP_BOOTLOADER_RESERVE_RTC + + rtc_slow_seg (RW) : org = 0x50000000 + CONFIG_ESP32_ULP_COPROC_RESERVE_MEM, + len = 0x1000 - CONFIG_ESP32_ULP_COPROC_RESERVE_MEM + + rtc_slow_reserved_seg(RW) : org = 0x50000000 + 0x2000 - RESERVE_RTC_MEM, len = RESERVE_RTC_MEM } diff --git a/boards/xtensa/esp32/common/src/esp32_backlight.c b/boards/xtensa/esp32/common/src/esp32_backlight.c index cd78eeae82b34..2c382fa8b9584 100644 --- a/boards/xtensa/esp32/common/src/esp32_backlight.c +++ b/boards/xtensa/esp32/common/src/esp32_backlight.c @@ -32,7 +32,7 @@ #include #include -#include "esp32_gpio.h" +#include "espressif/esp_gpio.h" #include "esp32_backlight.h" /**************************************************************************** @@ -65,19 +65,19 @@ int esp32_set_backlight(uint8_t level) { #ifdef HAVE_BACKLIGHT - esp32_configgpio(DISPLAY_BCKL, OUTPUT); + esp_configgpio(DISPLAY_BCKL, OUTPUT); /* TODO: use PWM to set the display brightness */ if (level == 0) { - esp32_gpiowrite(DISPLAY_BCKL, false); + esp_gpiowrite(DISPLAY_BCKL, false); } else { /* Set full brightness */ - esp32_gpiowrite(DISPLAY_BCKL, true); + esp_gpiowrite(DISPLAY_BCKL, true); } #endif diff --git a/boards/xtensa/esp32/common/src/esp32_board_apa102_lcd.c b/boards/xtensa/esp32/common/src/esp32_board_apa102_lcd.c index e5ceac5ef5349..73326aa93a705 100644 --- a/boards/xtensa/esp32/common/src/esp32_board_apa102_lcd.c +++ b/boards/xtensa/esp32/common/src/esp32_board_apa102_lcd.c @@ -37,7 +37,7 @@ #include #include -#include "esp32_gpio.h" +#include "espressif/esp_gpio.h" #include "esp32_spi.h" /**************************************************************************** @@ -107,4 +107,3 @@ void board_lcd_uninitialize(void) { /* TO-FIX */ } - diff --git a/boards/xtensa/esp32/common/src/esp32_board_apds9960.c b/boards/xtensa/esp32/common/src/esp32_board_apds9960.c index 14b56a46e0486..ef60d077cecde 100644 --- a/boards/xtensa/esp32/common/src/esp32_board_apds9960.c +++ b/boards/xtensa/esp32/common/src/esp32_board_apds9960.c @@ -34,7 +34,7 @@ #include #include "esp32_i2c.h" -#include "esp32_gpio.h" +#include "espressif/esp_gpio.h" #include "esp32_board_apds9960.h" @@ -102,7 +102,6 @@ static int apds9960_irq_attach(struct apds9960_config_s *state, { irqstate_t flags; int ret; - int irq = ESP32_PIN2IRQ(GPIO_APDS9960_INT); sninfo("apds9960_irq_attach\n"); @@ -110,13 +109,13 @@ static int apds9960_irq_attach(struct apds9960_config_s *state, /* Configure the pins that will be used as interrupt input */ - esp32_configgpio(GPIO_APDS9960_INT, INPUT_FUNCTION_3 | PULLUP); + esp_configgpio(GPIO_APDS9960_INT, INPUT_FUNCTION_3 | PULLUP | FALLING); /* Make sure the interrupt is disabled */ - esp32_gpioirqdisable(irq); + esp_gpioirqdisable(ESP_PIN2IRQ(GPIO_APDS9960_INT)); - ret = irq_attach(irq, isr, arg); + ret = esp_gpio_irq(GPIO_APDS9960_INT, isr, arg); if (ret < 0) { leave_critical_section(flags); @@ -126,7 +125,7 @@ static int apds9960_irq_attach(struct apds9960_config_s *state, /* Setup interrupt for Falling Edge */ - esp32_gpioirqenable(irq, FALLING); + esp_gpioirqenable(GPIO_APDS9960_INT); leave_critical_section(flags); diff --git a/boards/xtensa/esp32/common/src/esp32_board_rmt.c b/boards/xtensa/esp32/common/src/esp32_board_rmt.c index e450d36ce8692..24c3effb9d56f 100644 --- a/boards/xtensa/esp32/common/src/esp32_board_rmt.c +++ b/boards/xtensa/esp32/common/src/esp32_board_rmt.c @@ -79,7 +79,6 @@ * Initialize the RMT peripheral and register an RX device. * * Input Parameters: - * ch - The RMT's channel that will be used * pin - The pin used for the RX channel * * Returned Value: @@ -87,11 +86,11 @@ * ****************************************************************************/ -int board_rmt_rxinitialize(int ch, int pin) +int board_rmt_rxinitialize(int pin) { int ret; - struct rmt_dev_s *rmt = esp_rmt_rx_init(ch, pin); + struct rmt_dev_s *rmt = esp_rmt_rx_init(pin); ret = rmtchar_register(rmt); if (ret < 0) @@ -110,7 +109,6 @@ int board_rmt_rxinitialize(int ch, int pin) * Initialize the RMT peripheral and register an TX device. * * Input Parameters: - * ch - The RMT's channel that will be used * pin - The pin used for the TX channel * * Returned Value: @@ -118,7 +116,7 @@ int board_rmt_rxinitialize(int ch, int pin) * ****************************************************************************/ -int board_rmt_txinitialize(int ch, int pin) +int board_rmt_txinitialize(int pin) { int ret; struct rmt_dev_s *rmt; @@ -126,7 +124,7 @@ int board_rmt_txinitialize(int ch, int pin) struct ws2812_dev_s *led; #endif - rmt = esp_rmt_tx_init(ch, pin); + rmt = esp_rmt_tx_init(pin); if (rmt == NULL) { diff --git a/boards/xtensa/esp32/common/src/esp32_board_spi.c b/boards/xtensa/esp32/common/src/esp32_board_spi.c index a714de15afdf0..bf1740066951f 100644 --- a/boards/xtensa/esp32/common/src/esp32_board_spi.c +++ b/boards/xtensa/esp32/common/src/esp32_board_spi.c @@ -33,7 +33,7 @@ #include #include -#include "esp32_gpio.h" +#include "espressif/esp_gpio.h" /**************************************************************************** * Private Functions @@ -80,7 +80,7 @@ static inline int spi_cmddata(struct spi_dev_s *dev, uint32_t devid, * data bits are data or a command. */ - esp32_gpiowrite(DISPLAY_DC, !cmd); + esp_gpiowrite(DISPLAY_DC, !cmd); return OK; } #endif diff --git a/boards/xtensa/esp32/common/src/esp32_board_spiflash.c b/boards/xtensa/esp32/common/src/esp32_board_spiflash.c index 965bf28af11a4..bfcaec02a745a 100644 --- a/boards/xtensa/esp32/common/src/esp32_board_spiflash.c +++ b/boards/xtensa/esp32/common/src/esp32_board_spiflash.c @@ -109,8 +109,9 @@ static int init_ota_partitions(void) { struct mtd_dev_s *mtd; int ret = OK; + int i; - for (int i = 0; i < nitems(g_ota_partition_table); ++i) + for (i = 0; i < nitems(g_ota_partition_table); ++i) { const struct partition_s *part = &g_ota_partition_table[i]; mtd = esp_spiflash_alloc_mtdpart(part->firstblock, part->blocksize); @@ -441,12 +442,6 @@ int board_spiflash_init(void) { int ret = OK; - ret = esp_spiflash_init(); - if (ret < 0) - { - return ret; - } - #ifdef CONFIG_ESP32_HAVE_OTA_PARTITION ret = init_ota_partitions(); if (ret < 0) diff --git a/boards/xtensa/esp32/common/src/esp32_gc9a01.c b/boards/xtensa/esp32/common/src/esp32_gc9a01.c index db17a29ddfeb5..bf754ec570117 100644 --- a/boards/xtensa/esp32/common/src/esp32_gc9a01.c +++ b/boards/xtensa/esp32/common/src/esp32_gc9a01.c @@ -35,7 +35,7 @@ #include #include -#include "esp32_gpio.h" +#include "espressif/esp_gpio.h" #include "esp32_spi.h" /**************************************************************************** @@ -72,21 +72,21 @@ int board_lcd_initialize(void) /* SPI RX is not used. Same pin is used as LCD Data/Command control */ - esp32_configgpio(DISPLAY_DC, OUTPUT); - esp32_gpiowrite(DISPLAY_DC, true); + esp_configgpio(DISPLAY_DC, OUTPUT); + esp_gpiowrite(DISPLAY_DC, true); /* Pull LCD_RESET high */ - esp32_configgpio(DISPLAY_RST, OUTPUT); - esp32_gpiowrite(DISPLAY_RST, false); + esp_configgpio(DISPLAY_RST, OUTPUT); + esp_gpiowrite(DISPLAY_RST, false); up_mdelay(50); - esp32_gpiowrite(DISPLAY_RST, true); + esp_gpiowrite(DISPLAY_RST, true); up_mdelay(50); /* Set full brightness */ - esp32_configgpio(DISPLAY_BCKL, OUTPUT); - esp32_gpiowrite(DISPLAY_BCKL, true); + esp_configgpio(DISPLAY_BCKL, OUTPUT); + esp_gpiowrite(DISPLAY_BCKL, true); return OK; } diff --git a/boards/xtensa/esp32/common/src/esp32_ili9341.c b/boards/xtensa/esp32/common/src/esp32_ili9341.c index c28a8a37f5243..2803e48a918bd 100644 --- a/boards/xtensa/esp32/common/src/esp32_ili9341.c +++ b/boards/xtensa/esp32/common/src/esp32_ili9341.c @@ -40,7 +40,7 @@ #include -#include "esp32_gpio.h" +#include "espressif/esp_gpio.h" #include "esp32_spi.h" #include "hardware/esp32_gpio_sigmap.h" @@ -371,21 +371,21 @@ int board_lcd_initialize(void) /* Initialize non-SPI GPIOs */ - esp32_configgpio(DISPLAY_DC, OUTPUT_FUNCTION_3); - esp32_gpio_matrix_out(DISPLAY_DC, SIG_GPIO_OUT_IDX, 0, 0); + esp_configgpio(DISPLAY_DC, OUTPUT_FUNCTION_3); + esp_gpio_matrix_out(DISPLAY_DC, SIG_GPIO_OUT_IDX, 0, 0); - esp32_configgpio(DISPLAY_RST, INPUT_FUNCTION_3); - esp32_gpio_matrix_out(DISPLAY_RST, SIG_GPIO_OUT_IDX, 0, 0); + esp_configgpio(DISPLAY_RST, INPUT_FUNCTION_3); + esp_gpio_matrix_out(DISPLAY_RST, SIG_GPIO_OUT_IDX, 0, 0); - esp32_configgpio(DISPLAY_BCKL, OUTPUT_FUNCTION_3); - esp32_gpio_matrix_out(DISPLAY_BCKL, SIG_GPIO_OUT_IDX, 0, 0); + esp_configgpio(DISPLAY_BCKL, OUTPUT_FUNCTION_3); + esp_gpio_matrix_out(DISPLAY_BCKL, SIG_GPIO_OUT_IDX, 0, 0); /* Reset ILI9341 */ up_mdelay(10); - esp32_gpiowrite(DISPLAY_RST, false); + esp_gpiowrite(DISPLAY_RST, false); up_mdelay(10); - esp32_gpiowrite(DISPLAY_RST, true); + esp_gpiowrite(DISPLAY_RST, true); up_mdelay(50); /* Configure SPI */ diff --git a/boards/xtensa/esp32/common/src/esp32_mcp2515.c b/boards/xtensa/esp32/common/src/esp32_mcp2515.c index 519c561f95a93..e73cd9d1a5873 100644 --- a/boards/xtensa/esp32/common/src/esp32_mcp2515.c +++ b/boards/xtensa/esp32/common/src/esp32_mcp2515.c @@ -36,7 +36,7 @@ #include "esp32_spi.h" #include "esp32-devkitc.h" -#include "esp32_gpio.h" +#include "espressif/esp_gpio.h" #include "hardware/esp32_gpio_sigmap.h" #if defined(CONFIG_SPI) && defined(CONFIG_ESP32_SPI3) && \ @@ -48,7 +48,7 @@ #define MCP2515_SPI_PORTNO 3 /* On SPI3 */ -#if !defined(CONFIG_ESP32_GPIO_IRQ) +#if !defined(CONFIG_ESPRESSIF_GPIO_IRQ) # error "GPIO interrupts aren't enabled and it is required" #endif @@ -145,7 +145,6 @@ static int mcp2515_attach(struct mcp2515_config_s *state, struct esp32_mcp2515config_s *priv = (struct esp32_mcp2515config_s *)state; irqstate_t flags; - int irq = ESP32_PIN2IRQ(GPIO_MCP2515_IRQ); int ret; caninfo("Saving handler %p\n", handler); @@ -157,9 +156,9 @@ static int mcp2515_attach(struct mcp2515_config_s *state, /* Configure the interrupt */ - esp32_gpioirqdisable(irq); + esp_gpioirqdisable(ESP_PIN2IRQ(GPIO_MCP2515_IRQ)); - ret = irq_attach(irq, mcp2515_interrupt, priv); + ret = esp_gpio_irq(GPIO_MCP2515_IRQ, mcp2515_interrupt, priv); if (ret < 0) { syslog(LOG_ERR, "ERROR: gpint_attach() failed: %d\n", ret); @@ -167,7 +166,7 @@ static int mcp2515_attach(struct mcp2515_config_s *state, return ret; } - esp32_gpioirqenable(irq, FALLING); + esp_gpioirqenable(GPIO_MCP2515_IRQ); leave_critical_section(flags); @@ -208,7 +207,8 @@ int board_mcp2515_initialize(int devno) /* Configure the MCP2515 interrupt pin as an input */ - esp32_configgpio(GPIO_MCP2515_IRQ, INPUT_FUNCTION_3 | PULLDOWN); + esp_configgpio(GPIO_MCP2515_IRQ, + INPUT_FUNCTION_3 | PULLDOWN | FALLING); spi = esp32_spibus_initialize(MCP2515_SPI_PORTNO); if (!spi) diff --git a/boards/xtensa/esp32/common/src/esp32_rgbled.c b/boards/xtensa/esp32/common/src/esp32_rgbled.c index 8668393ac95d1..bc54747af0061 100644 --- a/boards/xtensa/esp32/common/src/esp32_rgbled.c +++ b/boards/xtensa/esp32/common/src/esp32_rgbled.c @@ -43,7 +43,7 @@ #include #include "esp32-sparrow-kit.h" -#include "esp32_gpio.h" +#include "espressif/esp_gpio.h" #include "esp32_ledc.h" #include "esp32_rgbled.h" @@ -151,4 +151,3 @@ int esp32_rgbled_initialize(const char *devname) #else # error "RGB LED bad configuration" #endif - diff --git a/boards/xtensa/esp32/common/src/esp32_ssd1306.c b/boards/xtensa/esp32/common/src/esp32_ssd1306.c index 1b2813c6f35d4..1b2bcd453facb 100644 --- a/boards/xtensa/esp32/common/src/esp32_ssd1306.c +++ b/boards/xtensa/esp32/common/src/esp32_ssd1306.c @@ -39,7 +39,7 @@ # include #endif -#include "esp32_gpio.h" +#include "espressif/esp_gpio.h" #include "esp32_i2c.h" #include "hardware/esp32_gpio_sigmap.h" @@ -87,14 +87,14 @@ int board_lcd_initialize(void) * putting the OLED into reset state. */ - esp32_gpio_matrix_out(GPIO_SSD1306_RST, SIG_GPIO_OUT_IDX, 0, 0); - esp32_configgpio(GPIO_SSD1306_RST, OUTPUT_FUNCTION_3 | INPUT_FUNCTION_3); - esp32_gpiowrite(GPIO_SSD1306_RST, 0); + esp_gpio_matrix_out(GPIO_SSD1306_RST, SIG_GPIO_OUT_IDX, 0, 0); + esp_configgpio(GPIO_SSD1306_RST, OUTPUT_FUNCTION_3 | INPUT_FUNCTION_3); + esp_gpiowrite(GPIO_SSD1306_RST, 0); /* Wait a bit then release the OLED from the reset state */ up_mdelay(20); - esp32_gpiowrite(GPIO_SSD1306_RST, 1); + esp_gpiowrite(GPIO_SSD1306_RST, 1); /* Initialize I2C */ diff --git a/boards/xtensa/esp32/common/src/esp32_ssd1680.c b/boards/xtensa/esp32/common/src/esp32_ssd1680.c index 3a1ebc772dd8e..af6fde6545db7 100644 --- a/boards/xtensa/esp32/common/src/esp32_ssd1680.c +++ b/boards/xtensa/esp32/common/src/esp32_ssd1680.c @@ -39,7 +39,7 @@ #include -#include "esp32_gpio.h" +#include "espressif/esp_gpio.h" #include "esp32_spi.h" #ifdef CONFIG_LCD_SSD1680 @@ -86,7 +86,7 @@ static struct ssd1680_priv_s g_ssd1680_priv = #ifdef DISPLAY_VCC static bool ssd1680_set_vcc(bool state) { - esp32_gpiowrite(DISPLAY_VCC, state); + esp_gpiowrite(DISPLAY_VCC, state); return true; } #endif @@ -94,7 +94,7 @@ static bool ssd1680_set_vcc(bool state) #ifdef DISPLAY_RST static bool ssd1680_set_rst(bool state) { - esp32_gpiowrite(DISPLAY_RST, state); + esp_gpiowrite(DISPLAY_RST, state); return true; } #endif @@ -102,7 +102,7 @@ static bool ssd1680_set_rst(bool state) #ifdef DISPLAY_BUSY static bool ssd1680_check_busy(void) { - return esp32_gpioread(DISPLAY_BUSY); + return esp_gpioread(DISPLAY_BUSY); } #endif @@ -131,24 +131,24 @@ int board_lcd_initialize(void) /* Initialize additional I/O for e-ink display */ - esp32_configgpio(DISPLAY_DC, OUTPUT); + esp_configgpio(DISPLAY_DC, OUTPUT); #ifdef DISPLAY_VCC - esp32_configgpio(DISPLAY_VCC, OUTPUT); + esp_configgpio(DISPLAY_VCC, OUTPUT); lcdinfo("Using pin %d as VCC control\n", DISPLAY_VCC); #else lcdinfo("VCC line is disabled\n"); #endif #ifdef DISPLAY_RST - esp32_configgpio(DISPLAY_RST, OUTPUT); + esp_configgpio(DISPLAY_RST, OUTPUT); lcdinfo("Using pin %d as RESET\n", DISPLAY_RST); #else lcdinfo("RESET line is disabled\n"); #endif #ifdef DISPLAY_BUSY - esp32_configgpio(DISPLAY_BUSY, INPUT | PULLUP); + esp_configgpio(DISPLAY_BUSY, INPUT | PULLUP); lcdinfo("Using pin %d for reading busy state\n", DISPLAY_BUSY); #else diff --git a/boards/xtensa/esp32/common/src/esp32_st7789.c b/boards/xtensa/esp32/common/src/esp32_st7789.c index bdc0298e25d8d..074e3dd5d5d13 100644 --- a/boards/xtensa/esp32/common/src/esp32_st7789.c +++ b/boards/xtensa/esp32/common/src/esp32_st7789.c @@ -40,7 +40,7 @@ #include #include "esp32_spi.h" -#include "esp32_gpio.h" +#include "espressif/esp_gpio.h" /**************************************************************************** * Pre-processor Definitions @@ -86,21 +86,21 @@ int board_lcd_initialize(void) /* SPI RX is not used. Same pin is used as LCD Data/Command control */ - esp32_configgpio(DISPLAY_DC, OUTPUT); - esp32_gpiowrite(DISPLAY_DC, true); + esp_configgpio(DISPLAY_DC, OUTPUT); + esp_gpiowrite(DISPLAY_DC, true); /* Pull LCD_RESET high */ - esp32_configgpio(DISPLAY_RST, OUTPUT); - esp32_gpiowrite(DISPLAY_RST, false); + esp_configgpio(DISPLAY_RST, OUTPUT); + esp_gpiowrite(DISPLAY_RST, false); up_mdelay(1); - esp32_gpiowrite(DISPLAY_RST, true); + esp_gpiowrite(DISPLAY_RST, true); up_mdelay(10); /* Set full brightness */ - esp32_configgpio(DISPLAY_BCKL, OUTPUT); - esp32_gpiowrite(DISPLAY_BCKL, true); + esp_configgpio(DISPLAY_BCKL, OUTPUT); + esp_gpiowrite(DISPLAY_BCKL, true); lcdinfo("LCD successfully initialized"); diff --git a/boards/xtensa/esp32/common/src/esp32_zerocross.c b/boards/xtensa/esp32/common/src/esp32_zerocross.c index 2bbbd94aea100..022edd5a66c21 100644 --- a/boards/xtensa/esp32/common/src/esp32_zerocross.c +++ b/boards/xtensa/esp32/common/src/esp32_zerocross.c @@ -35,7 +35,7 @@ #include #include -#include "esp32_gpio.h" +#include "espressif/esp_gpio.h" #include "hardware/esp32_gpio_sigmap.h" #include "esp32-wrover-kit.h" #include "esp32_zerocross.h" @@ -82,7 +82,6 @@ static void zcross_enable(const struct zc_lowerhalf_s *lower, zc_interrupt_t handler, void *arg) { irqstate_t flags; - int irq = ESP32_PIN2IRQ(GPIO_ZERO_CROSS_IRQ); int ret; flags = enter_critical_section(); @@ -95,16 +94,16 @@ static void zcross_enable(const struct zc_lowerhalf_s *lower, /* Start with all interrupts disabled */ - esp32_gpioirqdisable(irq); + esp_gpioirqdisable(irq); - ret = irq_attach(irq, zcross_interrupt, NULL); + ret = esp_gpio_irq(GPIO_ZERO_CROSS_IRQ, zcross_interrupt, NULL); if (ret < 0) { syslog(LOG_ERR, "ERROR: zcross_enable() failed: %d\n", ret); leave_critical_section(flags); } - esp32_gpioirqenable(irq, RISING); + esp_gpioirqenable(GPIO_ZERO_CROSS_IRQ); leave_critical_section(flags); } @@ -142,7 +141,7 @@ static int zcross_interrupt(int irq, void *context, void *arg) int board_zerocross_initialize(int devno) { - esp32_configgpio(GPIO_ZERO_CROSS_IRQ, INPUT_FUNCTION_3 | PULLUP); + esp_configgpio(GPIO_ZERO_CROSS_IRQ, INPUT_FUNCTION_3 | PULLUP | RISING); /* Register the zero cross device as /dev/zc0 */ diff --git a/boards/xtensa/esp32/esp32-2432S028/configs/lvgl/defconfig b/boards/xtensa/esp32/esp32-2432S028/configs/lvgl/defconfig index a5bce049ff99f..e842db569c234 100644 --- a/boards/xtensa/esp32/esp32-2432S028/configs/lvgl/defconfig +++ b/boards/xtensa/esp32/esp32-2432S028/configs/lvgl/defconfig @@ -17,6 +17,9 @@ CONFIG_ARCH_BOARD_ESP32_2432S028=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/esp32-2432S028/configs/nsh/defconfig b/boards/xtensa/esp32/esp32-2432S028/configs/nsh/defconfig index 2d791ad7f02ba..829c691761f3c 100644 --- a/boards/xtensa/esp32/esp32-2432S028/configs/nsh/defconfig +++ b/boards/xtensa/esp32/esp32-2432S028/configs/nsh/defconfig @@ -14,6 +14,9 @@ CONFIG_ARCH_BOARD_ESP32_2432S028=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/esp32-2432S028/src/esp32_bringup.c b/boards/xtensa/esp32/esp32-2432S028/src/esp32_bringup.c index 92c35370d76a8..43e2dbd9755bf 100644 --- a/boards/xtensa/esp32/esp32-2432S028/src/esp32_bringup.c +++ b/boards/xtensa/esp32/esp32-2432S028/src/esp32_bringup.c @@ -39,7 +39,9 @@ #include #include +#include "espressif/esp_gpio.h" #include "esp32_partition.h" +#include "esp32_start.h" #include @@ -55,6 +57,10 @@ # include "esp32_board_wdt.h" #endif +#ifdef CONFIG_ESPRESSIF_HR_TIMER +# include "espressif/esp_hr_timer.h" +#endif + #ifdef CONFIG_ESP32_SPIFLASH # include "esp32_board_spiflash.h" #endif @@ -72,10 +78,6 @@ # include "esp32_board_pcnt.h" #endif -#ifdef CONFIG_ESP32_RT_TIMER -# include "esp32_rt_timer.h" -#endif - #ifdef CONFIG_LCD_DEV # include # include @@ -171,14 +173,6 @@ int esp32_bringup(void) } #endif -#ifdef CONFIG_ESP32_RT_TIMER - ret = esp32_rt_timer_init(); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize RT timer: %d\n", ret); - } -#endif - #ifdef CONFIG_ESPRESSIF_BLE ret = esp32_ble_initialize(); if (ret) @@ -196,13 +190,21 @@ int esp32_bringup(void) } #endif +#ifdef CONFIG_ESPRESSIF_HR_TIMER + ret = esp_hr_timer_init(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: esp_hr_timer_init() failed: %d\n", ret); + } +#endif + /* First, register the timer drivers and let timer 1 for oneshot * if it is enabled. */ #ifdef CONFIG_TIMER -#if defined(CONFIG_ESP32_TIMER0) && !defined(CONFIG_ESP32_RT_TIMER) +#if defined(CONFIG_ESP32_TIMER0) && !defined(CONFIG_ESPRESSIF_HR_TIMER) ret = esp32_timer_initialize("/dev/timer0", TIMER0); if (ret < 0) { @@ -279,7 +281,7 @@ int esp32_bringup(void) #endif #ifdef CONFIG_DEV_GPIO - ret = esp32_gpio_init(); + ret = esp_gpio_init(); if (ret < 0) { syslog(LOG_ERR, "Failed to initialize GPIO Driver: %d\n", ret); @@ -370,7 +372,7 @@ int esp32_bringup(void) #ifdef CONFIG_RTC_DRIVER /* Instantiate the ESP32 RTC driver */ - ret = esp32_rtc_driverinit(); + ret = esp_rtc_driverinit(); if (ret < 0) { syslog(LOG_ERR, diff --git a/boards/xtensa/esp32/esp32-audio-kit/configs/audio/defconfig b/boards/xtensa/esp32/esp32-audio-kit/configs/audio/defconfig index 09b92984a8cbd..d1797ff4e0b3b 100644 --- a/boards/xtensa/esp32/esp32-audio-kit/configs/audio/defconfig +++ b/boards/xtensa/esp32/esp32-audio-kit/configs/audio/defconfig @@ -19,6 +19,9 @@ CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32_A1S=y CONFIG_ARCH_INTERRUPTSTACK=4096 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_AUDIO=y diff --git a/boards/xtensa/esp32/esp32-audio-kit/configs/nsh/defconfig b/boards/xtensa/esp32/esp32-audio-kit/configs/nsh/defconfig index a500f5a418d3d..09ce681345e1c 100644 --- a/boards/xtensa/esp32/esp32-audio-kit/configs/nsh/defconfig +++ b/boards/xtensa/esp32/esp32-audio-kit/configs/nsh/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32_AUDIO_KIT=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32_A1S=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/esp32-audio-kit/configs/wifi/defconfig b/boards/xtensa/esp32/esp32-audio-kit/configs/wifi/defconfig index faa34e0f0aa94..9f827f3575189 100644 --- a/boards/xtensa/esp32/esp32-audio-kit/configs/wifi/defconfig +++ b/boards/xtensa/esp32/esp32-audio-kit/configs/wifi/defconfig @@ -17,6 +17,9 @@ CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32_A1S=y CONFIG_ARCH_INTERRUPTSTACK=4096 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/esp32-audio-kit/src/esp32_bringup.c b/boards/xtensa/esp32/esp32-audio-kit/src/esp32_bringup.c index de60a22ba4480..a66e77583b7be 100644 --- a/boards/xtensa/esp32/esp32-audio-kit/src/esp32_bringup.c +++ b/boards/xtensa/esp32/esp32-audio-kit/src/esp32_bringup.c @@ -39,8 +39,9 @@ #include #include "esp32_i2c.h" -#include "esp32_gpio.h" +#include "espressif/esp_gpio.h" #include "esp32_partition.h" +#include "esp32_start.h" #include @@ -92,16 +93,16 @@ # include #endif -#ifdef CONFIG_ESP32_RT_TIMER -# include "esp32_rt_timer.h" -#endif - #ifdef CONFIG_LCD_DEV # include #endif #ifdef CONFIG_RTC_DRIVER -# include "esp32_rtc_lowerhalf.h" +# include "espressif/esp_rtc.h" +#endif + +#ifdef CONFIG_ESPRESSIF_HR_TIMER +# include "espressif/esp_hr_timer.h" #endif #ifdef CONFIG_LCD_BACKPACK @@ -201,14 +202,6 @@ int esp32_bringup(void) } #endif -#ifdef CONFIG_ESP32_RT_TIMER - ret = esp32_rt_timer_init(); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize RT timer: %d\n", ret); - } -#endif - #ifdef CONFIG_ESPRESSIF_BLE ret = esp32_ble_initialize(); if (ret) @@ -226,13 +219,21 @@ int esp32_bringup(void) } #endif +#ifdef CONFIG_ESPRESSIF_HR_TIMER + ret = esp_hr_timer_init(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: esp_hr_timer_init() failed: %d\n", ret); + } +#endif + /* First, register the timer drivers and let timer 1 for oneshot * if it is enabled. */ #ifdef CONFIG_TIMER -#if defined(CONFIG_ESP32_TIMER0) && !defined(CONFIG_ESP32_RT_TIMER) +#if defined(CONFIG_ESP32_TIMER0) && !defined(CONFIG_ESPRESSIF_HR_TIMER) ret = esp32_timer_initialize("/dev/timer0", TIMER0); if (ret < 0) { @@ -309,7 +310,7 @@ int esp32_bringup(void) #endif #ifdef CONFIG_DEV_GPIO - ret = esp32_gpio_init(); + ret = esp_gpio_init(); if (ret < 0) { syslog(LOG_ERR, "Failed to initialize GPIO Driver: %d\n", ret); @@ -344,8 +345,8 @@ int esp32_bringup(void) /* Configure ES8388 audio on I2C0 and I2S0 */ - esp32_configgpio(SPEAKER_ENABLE_GPIO, OUTPUT); - esp32_gpiowrite(SPEAKER_ENABLE_GPIO, true); + esp_configgpio(SPEAKER_ENABLE_GPIO, OUTPUT); + esp_gpiowrite(SPEAKER_ENABLE_GPIO, true); ret = esp32_es8388_initialize(ESP32_I2C0, ES8388_I2C_ADDR, ES8388_I2C_FREQ, ESP32_I2S0); @@ -428,7 +429,7 @@ int esp32_bringup(void) #ifdef CONFIG_RTC_DRIVER /* Instantiate the ESP32 RTC driver */ - ret = esp32_rtc_driverinit(); + ret = esp_rtc_driverinit(); if (ret < 0) { syslog(LOG_ERR, diff --git a/boards/xtensa/esp32/esp32-audio-kit/src/esp32_buttons.c b/boards/xtensa/esp32/esp32-audio-kit/src/esp32_buttons.c index af3a68db990ef..39d27f901ea03 100644 --- a/boards/xtensa/esp32/esp32-audio-kit/src/esp32_buttons.c +++ b/boards/xtensa/esp32/esp32-audio-kit/src/esp32_buttons.c @@ -37,7 +37,7 @@ #include #include -#include "esp32_gpio.h" +#include "espressif/esp_gpio.h" #include "esp32-audio-kit.h" @@ -58,7 +58,7 @@ uint32_t board_button_initialize(void) { - esp32_configgpio(BUTTON_BOOT, INPUT_FUNCTION_3 | PULLUP); + esp_configgpio(BUTTON_BOOT, INPUT_FUNCTION_3 | PULLUP | CHANGE); return 1; } @@ -79,13 +79,13 @@ uint32_t board_buttons(void) int i = 0; int n = 0; - bool b0 = esp32_gpioread(BUTTON_BOOT); + bool b0 = esp_gpioread(BUTTON_BOOT); for (i = 0; i < 10; i++) { up_mdelay(1); /* TODO */ - bool b1 = esp32_gpioread(BUTTON_BOOT); + bool b1 = esp_gpioread(BUTTON_BOOT); if (b0 == b1) { @@ -131,38 +131,6 @@ uint32_t board_buttons(void) #ifdef CONFIG_ARCH_IRQBUTTONS int board_button_irq(int id, xcpt_t irqhandler, void *arg) { - int ret; - DEBUGASSERT(id == 0); - - int irq = ESP32_PIN2IRQ(BUTTON_BOOT); - - if (NULL != irqhandler) - { - /* Make sure the interrupt is disabled */ - - esp32_gpioirqdisable(irq); - - ret = irq_attach(irq, irqhandler, arg); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: irq_attach() failed: %d\n", ret); - return ret; - } - - gpioinfo("Attach %p\n", irqhandler); - - gpioinfo("Enabling the interrupt\n"); - - /* Configure the interrupt for rising and falling edges */ - - esp32_gpioirqenable(irq, CHANGE); - } - else - { - gpioinfo("Disable the interrupt\n"); - esp32_gpioirqdisable(irq); - } - - return OK; + return esp_gpio_irq(BUTTON_BOOT, irqhandler, arg); } #endif diff --git a/boards/xtensa/esp32/esp32-audio-kit/src/esp32_gpio.c b/boards/xtensa/esp32/esp32-audio-kit/src/esp32_gpio.c index fa07334a5afff..39975bbd445e2 100644 --- a/boards/xtensa/esp32/esp32-audio-kit/src/esp32_gpio.c +++ b/boards/xtensa/esp32/esp32-audio-kit/src/esp32_gpio.c @@ -37,7 +37,7 @@ #include #include "esp32-audio-kit.h" -#include "esp32_gpio.h" +#include "espressif/esp_gpio.h" #include "hardware/esp32_gpio_sigmap.h" #if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF) @@ -46,7 +46,7 @@ * Pre-processor Definitions ****************************************************************************/ -#if !defined(CONFIG_ESP32_GPIO_IRQ) && BOARD_NGPIOINT > 0 +#if !defined(CONFIG_ESPRESSIF_GPIO_IRQ) && BOARD_NGPIOINT > 0 # error "NGPIOINT is > 0 and GPIO interrupts aren't enabled" #endif @@ -182,7 +182,7 @@ static int gpout_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(esp32gpio->id < BOARD_NGPIOOUT); gpioinfo("Reading...\n"); - *value = esp32_gpioread(g_gpiooutputs[esp32gpio->id]); + *value = esp_gpioread(g_gpiooutputs[esp32gpio->id]); return OK; } @@ -198,7 +198,7 @@ static int gpout_write(struct gpio_dev_s *dev, bool value) DEBUGASSERT(esp32gpio->id < BOARD_NGPIOOUT); gpioinfo("Writing %d\n", (int)value); - esp32_gpiowrite(g_gpiooutputs[esp32gpio->id], value); + esp_gpiowrite(g_gpiooutputs[esp32gpio->id], value); return OK; } #endif @@ -216,7 +216,7 @@ static int gpin_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(esp32gpio->id < BOARD_NGPIOIN); gpioinfo("Reading... pin %" PRIu32 "\n", g_gpioinputs[esp32gpio->id]); - *value = esp32_gpioread(g_gpioinputs[esp32gpio->id]); + *value = esp_gpioread(g_gpioinputs[esp32gpio->id]); return OK; } #endif @@ -252,7 +252,7 @@ static int gpint_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(esp32gpint->esp32gpio.id < BOARD_NGPIOINT); gpioinfo("Reading int pin...\n"); - *value = esp32_gpioread(g_gpiointinputs[esp32gpint->esp32gpio.id]); + *value = esp_gpioread(g_gpiointinputs[esp32gpint->esp32gpio.id]); return OK; } @@ -265,23 +265,26 @@ static int gpint_attach(struct gpio_dev_s *dev, { struct esp32gpint_dev_s *esp32gpint = (struct esp32gpint_dev_s *)dev; - int irq = ESP32_PIN2IRQ(g_gpiointinputs[esp32gpint->esp32gpio.id]); int ret; gpioinfo("Attaching the callback\n"); /* Make sure the interrupt is disabled */ - esp32_gpioirqdisable(irq); - ret = irq_attach(irq, - esp32gpio_interrupt, - &g_gpint[esp32gpint->esp32gpio.id]); + esp_gpioirqdisable(g_gpiointinputs[esp32gpint->esp32gpio.id]); + + ret = esp_gpio_irq(g_gpiointinputs[esp32gpint->esp32gpio.id], + esp32gpio_interrupt, + &g_gpint[esp32gpint->esp32gpio.id]); if (ret < 0) { - syslog(LOG_ERR, "ERROR: gpint_attach() failed: %d\n", ret); return ret; } + /* Make sure the interrupt is disabled */ + + esp_gpioirqdisable(g_gpiointinputs[esp32gpint->esp32gpio.id]); + gpioinfo("Attach %p\n", callback); esp32gpint->callback = callback; return OK; @@ -295,7 +298,6 @@ static int gpint_enable(struct gpio_dev_s *dev, bool enable) { struct esp32gpint_dev_s *esp32gpint = (struct esp32gpint_dev_s *)dev; - int irq = ESP32_PIN2IRQ(g_gpiointinputs[esp32gpint->esp32gpio.id]); if (enable) { @@ -305,13 +307,13 @@ static int gpint_enable(struct gpio_dev_s *dev, bool enable) /* Configure the interrupt for rising edge */ - esp32_gpioirqenable(irq, RISING); + esp_gpioirqenable(g_gpiointinputs[esp32gpint->esp32gpio.id]); } } else { gpioinfo("Disable the interrupt\n"); - esp32_gpioirqdisable(irq); + esp_gpioirqdisable(g_gpiointinputs[esp32gpint->esp32gpio.id]); } return OK; @@ -343,10 +345,9 @@ int esp32_gpio_init(void) /* Configure the pins that will be used as output */ - esp32_gpio_matrix_out(g_gpiooutputs[i], SIG_GPIO_OUT_IDX, 0, 0); - esp32_configgpio(g_gpiooutputs[i], OUTPUT_FUNCTION_3 | - INPUT_FUNCTION_3); - esp32_gpiowrite(g_gpiooutputs[i], 0); + esp_gpio_matrix_out(g_gpiooutputs[i], SIG_GPIO_OUT_IDX, 0, 0); + esp_configgpio(g_gpiooutputs[i], OUTPUT_FUNCTION_3 | INPUT_FUNCTION_3); + esp_gpiowrite(g_gpiooutputs[i], 0); pincount++; } @@ -364,7 +365,7 @@ int esp32_gpio_init(void) /* Configure the pins that will be used as INPUT */ - esp32_configgpio(g_gpioinputs[i], INPUT_FUNCTION_3); + esp_configgpio(g_gpioinputs[i], INPUT_FUNCTION_3 | PULLDOWN); pincount++; } @@ -382,7 +383,8 @@ int esp32_gpio_init(void) /* Configure the pins that will be used as interrupt input */ - esp32_configgpio(g_gpiointinputs[i], INPUT_FUNCTION_3 | PULLDOWN); + esp_configgpio(g_gpiointinputs[i], + INPUT_FUNCTION_3 | PULLUP | FALLING); pincount++; } diff --git a/boards/xtensa/esp32/esp32-audio-kit/src/esp32_userleds.c b/boards/xtensa/esp32/esp32-audio-kit/src/esp32_userleds.c index b9e061a5c6edd..ec6e02916304c 100644 --- a/boards/xtensa/esp32/esp32-audio-kit/src/esp32_userleds.c +++ b/boards/xtensa/esp32/esp32-audio-kit/src/esp32_userleds.c @@ -33,7 +33,7 @@ #include #include -#include "esp32_gpio.h" +#include "espressif/esp_gpio.h" #include "esp32-audio-kit.h" /**************************************************************************** @@ -63,7 +63,7 @@ uint32_t board_userled_initialize(void) for (i = 0; i < BOARD_NLEDS; i++) { - esp32_configgpio(g_ledcfg[i], OUTPUT); + esp_configgpio(g_ledcfg[i], OUTPUT); } return BOARD_NLEDS; @@ -77,7 +77,7 @@ void board_userled(int led, bool ledon) { if ((unsigned)led < BOARD_NLEDS) { - esp32_gpiowrite(g_ledcfg[led], ledon); + esp_gpiowrite(g_ledcfg[led], ledon); } } @@ -91,7 +91,6 @@ void board_userled_all(uint32_t ledset) for (i = 0; i < BOARD_NLEDS; i++) { - esp32_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); + esp_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); } } - diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/adc/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/adc/defconfig index 6eeaec0ab3d95..c00de04173ffc 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/adc/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/adc/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32_DEVKITC=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/audio/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/audio/defconfig index 77955464b5256..d865248dcab77 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/audio/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/audio/defconfig @@ -19,6 +19,9 @@ CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_AUDIO=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/autopm/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/autopm/defconfig index f567f4bc1059d..34a23d971b4a1 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/autopm/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/autopm/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_BOARD_ESP32_DEVKITC=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/ble/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/ble/defconfig index 1f0d7ec32986d..c50eb3ad70847 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/ble/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/ble/defconfig @@ -18,6 +18,9 @@ CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/blewifi/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/blewifi/defconfig index a57b3dbef3384..b35bd5a3b1095 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/blewifi/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/blewifi/defconfig @@ -18,6 +18,9 @@ CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y CONFIG_ARCH_INTERRUPTSTACK=4096 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BCH=y @@ -31,7 +34,6 @@ CONFIG_DISABLE_MQUEUE_NOTIFICATION=y CONFIG_DRIVERS_BLUETOOTH=y CONFIG_DRIVERS_IEEE80211=y CONFIG_DRIVERS_WIRELESS=y -CONFIG_ESP32_RT_TIMER_TASK_STACK_SIZE=4096 CONFIG_ESP32_SPIFLASH=y CONFIG_ESP32_SPIFLASH_SPIFFS=y CONFIG_ESP32_STORAGE_MTD_SIZE=0x80000 diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/bmp280/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/bmp280/defconfig index 45389d598ed18..42b780ced38b1 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/bmp280/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/bmp280/defconfig @@ -17,6 +17,9 @@ CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 @@ -26,9 +29,9 @@ CONFIG_DEBUG_SENSORS=y CONFIG_DEBUG_SENSORS_ERROR=y CONFIG_DEBUG_SENSORS_INFO=y CONFIG_DEBUG_SENSORS_WARN=y -CONFIG_ESP32_GPIO_IRQ=y CONFIG_ESP32_I2C0=y CONFIG_ESP32_UART0=y +CONFIG_ESPRESSIF_GPIO_IRQ=y CONFIG_FS_PROCFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/brickmatch/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/brickmatch/defconfig index 8f11cb3b4f5d8..de0cf482f5d5b 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/brickmatch/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/brickmatch/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32_DEVKITC=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LATE_INITIALIZE=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/buttons/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/buttons/defconfig index 7018ef6083861..7a03e43e2db6f 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/buttons/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/buttons/defconfig @@ -17,12 +17,15 @@ CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y -CONFIG_ESP32_GPIO_IRQ=y CONFIG_ESP32_UART0=y +CONFIG_ESPRESSIF_GPIO_IRQ=y CONFIG_EXAMPLES_BUTTONS=y CONFIG_FS_PROCFS=y CONFIG_HAVE_CXX=y @@ -34,7 +37,6 @@ CONFIG_INPUT=y CONFIG_INPUT_BUTTONS=y CONFIG_INPUT_BUTTONS_LOWER=y CONFIG_INTELHEX_BINARY=y -CONFIG_LINE_MAX=64 CONFIG_MM_REGIONS=3 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/capture/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/capture/defconfig index 50f4b49d377c7..7f6c6d5333e2d 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/capture/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/capture/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32_DEVKITC=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/coremark/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/coremark/defconfig index a46a769f51530..2c859c320dd20 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/coremark/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/coremark/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_SETJMP_H=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/crypto/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/crypto/defconfig index ccbda9a762da0..f6500fcea3e82 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/crypto/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/crypto/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_BOARD_ESP32_DEVKITC=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 @@ -56,4 +59,5 @@ CONFIG_SYSLOG_BUFFER=y CONFIG_SYSTEM_NSH=y CONFIG_TESTING_CRYPTO=y CONFIG_TESTING_CRYPTO_HASH=y +CONFIG_TESTING_CRYPTO_HASH_DISABLE_MD5=y CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/cxx/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/cxx/defconfig index 2cdcd0e62a8ab..2b933afeac698 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/cxx/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/cxx/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32_DEVKITC=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/dac/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/dac/defconfig index e9f6b849473e0..18f58144abd21 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/dac/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/dac/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_BOARD_ESP32_DEVKITC=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/efuse/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/efuse/defconfig index 8360145d5432c..bb19f9d83aa00 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/efuse/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/efuse/defconfig @@ -6,6 +6,7 @@ # modifications. # # CONFIG_ARCH_LEDS is not set +# CONFIG_ESPRESSIF_EFUSE_VIRTUAL is not set # CONFIG_NSH_ARGCAT is not set # CONFIG_NSH_CMDOPT_HEXDUMP is not set CONFIG_ARCH="xtensa" @@ -15,6 +16,10 @@ CONFIG_ARCH_BOARD_ESP32_DEVKITC=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/elf/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/elf/defconfig index 94ae8f5e79581..d805be003e548 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/elf/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/elf/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32_DEVKITC=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BINFMT_CONSTRUCTORS=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/espnow/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/espnow/defconfig index f132e2e94005b..e3a127df96010 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/espnow/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/espnow/defconfig @@ -19,6 +19,9 @@ CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/gpio/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/gpio/defconfig index 2b9d0d6bf7b64..eafdb6c5610a0 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/gpio/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/gpio/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32_DEVKITC=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/i2c/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/i2c/defconfig index 7127a7ae58b8c..bac6c438332e2 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/i2c/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/i2c/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32_DEVKITC=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/i2schar/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/i2schar/defconfig index c3811d2defae4..c5124a41251ea 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/i2schar/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/i2schar/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_BOARD_ESP32_DEVKITC=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_AUDIO=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/knsh/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/knsh/defconfig index be235a0e3e27b..074741effeca5 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/knsh/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/knsh/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_SETJMP_H=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/leds/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/leds/defconfig index cf7fc98dfdd5f..922e86a72d5b8 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/leds/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/leds/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32_DEVKITC=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/match4/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/match4/defconfig index 48c8f9a433be2..4d7d8567714d6 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/match4/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/match4/defconfig @@ -15,14 +15,17 @@ CONFIG_ARCH_BOARD_ESP32_DEVKITC=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LATE_INITIALIZE=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y CONFIG_DEV_GPIO=y -CONFIG_ESP32_GPIO_IRQ=y CONFIG_ESP32_UART0=y +CONFIG_ESPRESSIF_GPIO_IRQ=y CONFIG_ESP_RMT=y CONFIG_EXAMPLES_GPIO=y CONFIG_EXAMPLES_RMTCHAR=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/max6675/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/max6675/defconfig index 0fb7916c4602b..d1b0aa4a2cbe2 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/max6675/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/max6675/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32_DEVKITC=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/mcp2515/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/mcp2515/defconfig index a42f8d0576b47..2d68e5782dca3 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/mcp2515/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/mcp2515/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_BOARD_ESP32_DEVKITC=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/mcuboot_nsh/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/mcuboot_nsh/defconfig index 27a7517548c1b..ff76998156582 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/mcuboot_nsh/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/mcuboot_nsh/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32_DEVKITC=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/mcuboot_slot_confirm/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/mcuboot_slot_confirm/defconfig index 36d3e85b688fc..95abbd6730ddf 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/mcuboot_slot_confirm/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/mcuboot_slot_confirm/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32_DEVKITC=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/mcuboot_update_agent/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/mcuboot_update_agent/defconfig index 783477f344855..e4dcbce029eae 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/mcuboot_update_agent/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/mcuboot_update_agent/defconfig @@ -17,6 +17,9 @@ CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/modbus/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/modbus/defconfig index d60cd07f61b01..237de87183e91 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/modbus/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/modbus/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_BOARD_ESP32_DEVKITC=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/module/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/module/defconfig index cae00e31d3413..42753590d3b28 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/module/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/module/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32_DEVKITC=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARDCTL_ROMDISK=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/motor/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/motor/defconfig index 340e270d532a4..925dafb1c77c8 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/motor/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/motor/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32_DEVKITC=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/mqttc/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/mqttc/defconfig index 71e17b6a69fdd..4d3d1b6eea3f6 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/mqttc/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/mqttc/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_BOARD_ESP32_DEVKITC=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/ms5611/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/ms5611/defconfig index df9c589805afb..fef8e2169acea 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/ms5611/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/ms5611/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32_DEVKITC=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 @@ -23,10 +26,10 @@ CONFIG_DEBUG_FEATURES=y CONFIG_DEBUG_SENSORS=y CONFIG_DEBUG_SENSORS_ERROR=y CONFIG_DEBUG_SENSORS_WARN=y -CONFIG_ESP32_GPIO_IRQ=y CONFIG_ESP32_I2C0=y CONFIG_ESP32_I2C0_SDAPIN=21 CONFIG_ESP32_UART0=y +CONFIG_ESPRESSIF_GPIO_IRQ=y CONFIG_FS_PROCFS=y CONFIG_HAVE_CXX=y CONFIG_HAVE_CXXINITIALIZE=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/nsh/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/nsh/defconfig index eee8077d1edad..7229836adddda 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/nsh/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/nsh/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32_DEVKITC=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/nvblk/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/nvblk/defconfig index f388114b89b5c..bcce19b139d36 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/nvblk/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/nvblk/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32_DEVKITC=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_USE_TEXT_HEAP=y CONFIG_ARCH_XTENSA=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/nxdiag/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/nxdiag/defconfig index 7928c1906feff..a0f0a6a95bfc4 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/nxdiag/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/nxdiag/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32_DEVKITC=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/nxlooper/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/nxlooper/defconfig index e4928b8f325c0..85b6d4e3ce2fc 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/nxlooper/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/nxlooper/defconfig @@ -20,6 +20,9 @@ CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y CONFIG_ARCH_INTERRUPTSTACK=4096 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_AUDIO=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/oneshot/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/oneshot/defconfig index b8c06e412297f..efdef29a9e2c7 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/oneshot/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/oneshot/defconfig @@ -8,7 +8,6 @@ # CONFIG_ARCH_LEDS is not set # CONFIG_NSH_ARGCAT is not set # CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ALARM_ARCH=y CONFIG_ARCH="xtensa" CONFIG_ARCH_BOARD="esp32-devkitc" CONFIG_ARCH_BOARD_COMMON=y @@ -16,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32_DEVKITC=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 @@ -54,5 +56,4 @@ CONFIG_START_YEAR=2011 CONFIG_SYSLOG_BUFFER=y CONFIG_SYSTEM_NSH=y CONFIG_TIMER=y -CONFIG_TIMER_ARCH=y CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/ostest/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/ostest/defconfig index 27cb24d63c45e..80274fc731da4 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/ostest/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/ostest/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32_DEVKITC=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_SETJMP_H=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/pm/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/pm/defconfig index 7230490fe93f1..454424f7366a9 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/pm/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/pm/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32_DEVKITC=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/psram/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/psram/defconfig index 67da7c9bfedea..d87efcca7d3b5 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/psram/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/psram/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/psram_usrheap/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/psram_usrheap/defconfig index 94df13d640698..cb9e5efc38b94 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/psram_usrheap/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/psram_usrheap/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/pwm/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/pwm/defconfig index e4cd2da6c3701..6636af7ad868a 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/pwm/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/pwm/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32_DEVKITC=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/qemu_openeth/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/qemu_openeth/defconfig index 1a8c033ea8c1e..2235c0516f5bb 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/qemu_openeth/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/qemu_openeth/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32_DEVKITC=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/qencoder/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/qencoder/defconfig index d3f4553a6860f..eca38fb91a634 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/qencoder/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/qencoder/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32_DEVKITC=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/random/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/random/defconfig index 02a8f8a2cada2..963056498d32b 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/random/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/random/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32_DEVKITC=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/rmt/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/rmt/defconfig index 5443547ed95ab..3b39a416e344f 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/rmt/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/rmt/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32_DEVKITC=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/romfs/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/romfs/defconfig index 50bb2ea191953..62c050b45cd26 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/romfs/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/romfs/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32_DEVKITC=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/rtc/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/rtc/defconfig index c75d2f737cdab..fb8fecd026a5d 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/rtc/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/rtc/defconfig @@ -15,11 +15,13 @@ CONFIG_ARCH_BOARD_ESP32_DEVKITC=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y -CONFIG_ESP32_RT_TIMER=y CONFIG_ESP32_UART0=y CONFIG_EXAMPLES_ALARM=y CONFIG_FS_PROCFS=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/sdm/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/sdm/defconfig index e3639c6bbfcc0..a7a80389a8b2d 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/sdm/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/sdm/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32_DEVKITC=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/sdmmc_spi/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/sdmmc_spi/defconfig index 1c0f2271f1eb3..a9e39b5a1773e 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/sdmmc_spi/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/sdmmc_spi/defconfig @@ -20,6 +20,9 @@ CONFIG_ARCH_BOARD_ESP32_DEVKITC=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/smp/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/smp/defconfig index 22e1eb9e7b2a6..e1fbe7c830dba 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/smp/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/smp/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_SETJMP_H=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/snake/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/snake/defconfig index 934a0e9fa798d..59ee30803010b 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/snake/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/snake/defconfig @@ -15,14 +15,17 @@ CONFIG_ARCH_BOARD_ESP32_DEVKITC=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LATE_INITIALIZE=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y CONFIG_DEV_GPIO=y -CONFIG_ESP32_GPIO_IRQ=y CONFIG_ESP32_UART0=y +CONFIG_ESPRESSIF_GPIO_IRQ=y CONFIG_ESP_RMT=y CONFIG_EXAMPLES_GPIO=y CONFIG_EXAMPLES_RMTCHAR=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/softap/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/softap/defconfig index 1e9f1b5e1fed3..5f6574438e537 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/softap/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/softap/defconfig @@ -17,6 +17,9 @@ CONFIG_ARCH_BOARD_ESP32_DEVKITC=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/sotest/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/sotest/defconfig index 2e75d3e6ebff5..4613278bfbe23 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/sotest/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/sotest/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32_DEVKITC=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARDCTL_OS_SYMTAB=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/spi/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/spi/defconfig index 82f8e27417336..edd23f0afc9e0 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/spi/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/spi/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32_DEVKITC=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/spiflash/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/spiflash/defconfig index 88f2bc041e668..e666a7c4a4fdd 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/spiflash/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/spiflash/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/sta_softap/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/sta_softap/defconfig index 9f88ada4e633b..d43e2d6f3a46d 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/sta_softap/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/sta_softap/defconfig @@ -18,6 +18,9 @@ CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/tickless/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/tickless/defconfig index 35d9e556b2dd4..dc94c00b8ff4c 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/tickless/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/tickless/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32_DEVKITC=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/timer/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/timer/defconfig index 9b1359135b3e7..e168dbd6fbf7a 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/timer/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/timer/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32_DEVKITC=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 @@ -50,5 +53,4 @@ CONFIG_START_YEAR=2011 CONFIG_SYSLOG_BUFFER=y CONFIG_SYSTEM_NSH=y CONFIG_TIMER=y -CONFIG_TIMER_ARCH=y CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/twai/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/twai/defconfig index 34b852f17fe9a..ac8bd5cb54483 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/twai/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/twai/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32_DEVKITC=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/wamr_wasi_debug/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/wamr_wasi_debug/defconfig index b5706e9e44008..69706fac65f31 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/wamr_wasi_debug/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/wamr_wasi_debug/defconfig @@ -21,6 +21,9 @@ CONFIG_ARCH_BOARD_ESP32_DEVKITC=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/watchdog/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/watchdog/defconfig index 0f395661604dd..f3606881e4ee9 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/watchdog/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/watchdog/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32_DEVKITC=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/watcher/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/watcher/defconfig index 9e3350805365a..b8efc346f4679 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/watcher/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/watcher/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32_DEVKITC=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/wifi/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/wifi/defconfig index 130eb70fa04bb..3fc57e92d63b6 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/wifi/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/wifi/defconfig @@ -18,6 +18,9 @@ CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/wifi_smp/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/wifi_smp/defconfig index ec0ea0ad86f83..5b171f93e1eb0 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/wifi_smp/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/wifi_smp/defconfig @@ -17,6 +17,9 @@ CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_SETJMP_H=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/wifinsh/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/wifinsh/defconfig index 42b65347eab4a..3fc38c9a13cf5 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/wifinsh/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/wifinsh/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_BOARD_ESP32_DEVKITC=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/esp32-devkitc/configs/wifishare/defconfig b/boards/xtensa/esp32/esp32-devkitc/configs/wifishare/defconfig index c56e1d40d05b1..b0c36e803e233 100644 --- a/boards/xtensa/esp32/esp32-devkitc/configs/wifishare/defconfig +++ b/boards/xtensa/esp32/esp32-devkitc/configs/wifishare/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_BOARD_ESP32_DEVKITC=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/xtensa/esp32/esp32-devkitc/src/esp32_bringup.c b/boards/xtensa/esp32/esp32-devkitc/src/esp32_bringup.c index d54042e8b4ee2..6cb4ce2d0151d 100644 --- a/boards/xtensa/esp32/esp32-devkitc/src/esp32_bringup.c +++ b/boards/xtensa/esp32/esp32-devkitc/src/esp32_bringup.c @@ -44,7 +44,9 @@ #if defined(CONFIG_ESPRESSIF_EFUSE) #include "espressif/esp_efuse.h" #endif +#include "espressif/esp_gpio.h" #include "esp32_partition.h" +#include "esp32_start.h" #ifdef CONFIG_USERLED # include @@ -99,6 +101,10 @@ # include "esp32_board_pcnt.h" #endif +#ifdef CONFIG_ESPRESSIF_AUTO_SLEEP +# include "espressif/esp_pm.h" +#endif + #ifdef CONFIG_I2CMULTIPLEXER_TCA9548A # include "esp32_tca9548a.h" #endif @@ -131,10 +137,6 @@ # include "esp32_aes.h" #endif -#ifdef CONFIG_ESP32_RT_TIMER -# include "esp32_rt_timer.h" -#endif - #ifdef CONFIG_INPUT_BUTTONS # include #endif @@ -148,7 +150,11 @@ #endif #ifdef CONFIG_RTC_DRIVER -# include "esp32_rtc_lowerhalf.h" +# include "espressif/esp_rtc.h" +#endif + +#ifdef CONFIG_ESPRESSIF_HR_TIMER +# include "espressif/esp_hr_timer.h" #endif #ifdef CONFIG_SPI_DRIVER @@ -344,14 +350,6 @@ int esp32_bringup(void) } #endif -#ifdef CONFIG_ESP32_RT_TIMER - ret = esp32_rt_timer_init(); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize RT timer: %d\n", ret); - } -#endif - #ifdef CONFIG_ESPRESSIF_WIFI_BT_COEXIST ret = esp32_wifi_bt_coexist_init(); if (ret) @@ -395,13 +393,21 @@ int esp32_bringup(void) } #endif +#ifdef CONFIG_ESPRESSIF_HR_TIMER + ret = esp_hr_timer_init(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: esp_hr_timer_init() failed: %d\n", ret); + } +#endif + /* First, register the timer drivers and let timer 1 for oneshot * if it is enabled. */ #ifdef CONFIG_TIMER -#if defined(CONFIG_ESP32_TIMER0) && !defined(CONFIG_ESP32_RT_TIMER) +#if defined(CONFIG_ESP32_TIMER0) && !defined(CONFIG_ESPRESSIF_HR_TIMER) ret = esp32_timer_initialize("/dev/timer0", TIMER0); if (ret < 0) { @@ -503,6 +509,16 @@ int esp32_bringup(void) } #endif +#ifdef CONFIG_ESPRESSIF_AUTO_SLEEP + /* Configure PM */ + + ret = esp_pmconfigure(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: esp_pmconfigure failed: %d\n", ret); + } +#endif + /* Register the TCA9548A Multiplexer before others I2C drivers to allow it * be used by other drivers. Look at esp32_ms5611.c how to use it. */ @@ -700,13 +716,13 @@ int esp32_bringup(void) #endif #ifdef CONFIG_ESP_RMT - ret = board_rmt_txinitialize(RMT_TXCHANNEL, RMT_OUTPUT_PIN); + ret = board_rmt_txinitialize(RMT_OUTPUT_PIN); if (ret < 0) { syslog(LOG_ERR, "ERROR: board_rmt_txinitialize() failed: %d\n", ret); } - ret = board_rmt_rxinitialize(RMT_RXCHANNEL, RMT_INPUT_PIN); + ret = board_rmt_rxinitialize(RMT_INPUT_PIN); if (ret < 0) { syslog(LOG_ERR, "ERROR: board_rmt_txinitialize() failed: %d\n", ret); @@ -716,7 +732,7 @@ int esp32_bringup(void) #ifdef CONFIG_RTC_DRIVER /* Instantiate the ESP32 RTC driver */ - ret = esp32_rtc_driverinit(); + ret = esp_rtc_driverinit(); if (ret < 0) { syslog(LOG_ERR, diff --git a/boards/xtensa/esp32/esp32-devkitc/src/esp32_buttons.c b/boards/xtensa/esp32/esp32-devkitc/src/esp32_buttons.c index 3fc02201d8815..9f8384e3e1292 100644 --- a/boards/xtensa/esp32/esp32-devkitc/src/esp32_buttons.c +++ b/boards/xtensa/esp32/esp32-devkitc/src/esp32_buttons.c @@ -37,7 +37,7 @@ #include #include -#include "esp32_gpio.h" +#include "espressif/esp_gpio.h" #include "esp32-devkitc.h" @@ -58,7 +58,7 @@ uint32_t board_button_initialize(void) { - esp32_configgpio(BUTTON_BOOT, INPUT_FUNCTION_3 | PULLUP); + esp_configgpio(BUTTON_BOOT, INPUT_FUNCTION_3 | PULLUP | CHANGE); return 1; } @@ -79,13 +79,13 @@ uint32_t board_buttons(void) int i = 0; int n = 0; - bool b0 = esp32_gpioread(BUTTON_BOOT); + bool b0 = esp_gpioread(BUTTON_BOOT); for (i = 0; i < 10; i++) { up_mdelay(1); /* TODO */ - bool b1 = esp32_gpioread(BUTTON_BOOT); + bool b1 = esp_gpioread(BUTTON_BOOT); if (b0 == b1) { @@ -131,38 +131,6 @@ uint32_t board_buttons(void) #ifdef CONFIG_ARCH_IRQBUTTONS int board_button_irq(int id, xcpt_t irqhandler, void *arg) { - int ret; - DEBUGASSERT(id == 0); - - int irq = ESP32_PIN2IRQ(BUTTON_BOOT); - - if (NULL != irqhandler) - { - /* Make sure the interrupt is disabled */ - - esp32_gpioirqdisable(irq); - - ret = irq_attach(irq, irqhandler, arg); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: irq_attach() failed: %d\n", ret); - return ret; - } - - gpioinfo("Attach %p\n", irqhandler); - - gpioinfo("Enabling the interrupt\n"); - - /* Configure the interrupt for rising and falling edges */ - - esp32_gpioirqenable(irq, CHANGE); - } - else - { - gpioinfo("Disable the interrupt\n"); - esp32_gpioirqdisable(irq); - } - - return OK; + return esp_gpio_irq(BUTTON_BOOT, irqhandler, arg); } #endif diff --git a/boards/xtensa/esp32/esp32-devkitc/src/esp32_gpio.c b/boards/xtensa/esp32/esp32-devkitc/src/esp32_gpio.c index fea746cf427aa..c4f090a4b02ce 100644 --- a/boards/xtensa/esp32/esp32-devkitc/src/esp32_gpio.c +++ b/boards/xtensa/esp32/esp32-devkitc/src/esp32_gpio.c @@ -37,7 +37,7 @@ #include #include "esp32-devkitc.h" -#include "esp32_gpio.h" +#include "espressif/esp_gpio.h" #include "hardware/esp32_gpio_sigmap.h" #if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF) @@ -46,7 +46,7 @@ * Pre-processor Definitions ****************************************************************************/ -#if !defined(CONFIG_ESP32_GPIO_IRQ) && BOARD_NGPIOINT > 0 +#if !defined(CONFIG_ESPRESSIF_GPIO_IRQ) && BOARD_NGPIOINT > 0 # error "NGPIOINT is > 0 and GPIO interrupts aren't enabled" #endif @@ -62,11 +62,11 @@ #define GPIO_IN1 18 -/* Interrupt pins. GPIO22 is used as an example, any other inputs could be - * used. +/* Interrupt pins. GPIO0 is used as an example, any other inputs could be + * used. This is the BOOT button. */ -#define GPIO_IRQPIN1 22 +#define GPIO_IRQPIN1 0 /**************************************************************************** * Private Types @@ -182,7 +182,7 @@ static int gpout_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(esp32gpio->id < BOARD_NGPIOOUT); gpioinfo("Reading...\n"); - *value = esp32_gpioread(g_gpiooutputs[esp32gpio->id]); + *value = esp_gpioread(g_gpiooutputs[esp32gpio->id]); return OK; } @@ -198,7 +198,7 @@ static int gpout_write(struct gpio_dev_s *dev, bool value) DEBUGASSERT(esp32gpio->id < BOARD_NGPIOOUT); gpioinfo("Writing %d\n", (int)value); - esp32_gpiowrite(g_gpiooutputs[esp32gpio->id], value); + esp_gpiowrite(g_gpiooutputs[esp32gpio->id], value); return OK; } #endif @@ -216,7 +216,7 @@ static int gpin_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(esp32gpio->id < BOARD_NGPIOIN); gpioinfo("Reading... pin %" PRIu32 "\n", g_gpioinputs[esp32gpio->id]); - *value = esp32_gpioread(g_gpioinputs[esp32gpio->id]); + *value = esp_gpioread(g_gpioinputs[esp32gpio->id]); return OK; } #endif @@ -252,7 +252,7 @@ static int gpint_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(esp32gpint->esp32gpio.id < BOARD_NGPIOINT); gpioinfo("Reading int pin...\n"); - *value = esp32_gpioread(g_gpiointinputs[esp32gpint->esp32gpio.id]); + *value = esp_gpioread(g_gpiointinputs[esp32gpint->esp32gpio.id]); return OK; } @@ -265,23 +265,26 @@ static int gpint_attach(struct gpio_dev_s *dev, { struct esp32gpint_dev_s *esp32gpint = (struct esp32gpint_dev_s *)dev; - int irq = ESP32_PIN2IRQ(g_gpiointinputs[esp32gpint->esp32gpio.id]); int ret; gpioinfo("Attaching the callback\n"); /* Make sure the interrupt is disabled */ - esp32_gpioirqdisable(irq); - ret = irq_attach(irq, - esp32gpio_interrupt, - &g_gpint[esp32gpint->esp32gpio.id]); + esp_gpioirqdisable(g_gpiointinputs[esp32gpint->esp32gpio.id]); + + ret = esp_gpio_irq(g_gpiointinputs[esp32gpint->esp32gpio.id], + esp32gpio_interrupt, + &g_gpint[esp32gpint->esp32gpio.id]); if (ret < 0) { - syslog(LOG_ERR, "ERROR: gpint_attach() failed: %d\n", ret); return ret; } + /* Make sure the interrupt is disabled */ + + esp_gpioirqdisable(g_gpiointinputs[esp32gpint->esp32gpio.id]); + gpioinfo("Attach %p\n", callback); esp32gpint->callback = callback; return OK; @@ -295,7 +298,6 @@ static int gpint_enable(struct gpio_dev_s *dev, bool enable) { struct esp32gpint_dev_s *esp32gpint = (struct esp32gpint_dev_s *)dev; - int irq = ESP32_PIN2IRQ(g_gpiointinputs[esp32gpint->esp32gpio.id]); if (enable) { @@ -305,13 +307,13 @@ static int gpint_enable(struct gpio_dev_s *dev, bool enable) /* Configure the interrupt for rising edge */ - esp32_gpioirqenable(irq, RISING); + esp_gpioirqenable(g_gpiointinputs[esp32gpint->esp32gpio.id]); } } else { gpioinfo("Disable the interrupt\n"); - esp32_gpioirqdisable(irq); + esp_gpioirqdisable(g_gpiointinputs[esp32gpint->esp32gpio.id]); } return OK; @@ -343,10 +345,9 @@ int esp32_gpio_init(void) /* Configure the pins that will be used as output */ - esp32_gpio_matrix_out(g_gpiooutputs[i], SIG_GPIO_OUT_IDX, 0, 0); - esp32_configgpio(g_gpiooutputs[i], OUTPUT_FUNCTION_3 | - INPUT_FUNCTION_3); - esp32_gpiowrite(g_gpiooutputs[i], 0); + esp_gpio_matrix_out(g_gpiooutputs[i], SIG_GPIO_OUT_IDX, 0, 0); + esp_configgpio(g_gpiooutputs[i], OUTPUT_FUNCTION_3 | INPUT_FUNCTION_3); + esp_gpiowrite(g_gpiooutputs[i], 0); pincount++; } @@ -364,7 +365,7 @@ int esp32_gpio_init(void) /* Configure the pins that will be used as INPUT */ - esp32_configgpio(g_gpioinputs[i], INPUT_FUNCTION_3); + esp_configgpio(g_gpioinputs[i], INPUT_FUNCTION_3 | PULLDOWN); pincount++; } @@ -382,7 +383,8 @@ int esp32_gpio_init(void) /* Configure the pins that will be used as interrupt input */ - esp32_configgpio(g_gpiointinputs[i], INPUT_FUNCTION_3 | PULLDOWN); + esp_configgpio(g_gpiointinputs[i], + INPUT_FUNCTION_3 | PULLUP | FALLING); pincount++; } diff --git a/boards/xtensa/esp32/esp32-devkitc/src/esp32_userleds.c b/boards/xtensa/esp32/esp32-devkitc/src/esp32_userleds.c index eea2ae6191aa3..a8637a244cd6b 100644 --- a/boards/xtensa/esp32/esp32-devkitc/src/esp32_userleds.c +++ b/boards/xtensa/esp32/esp32-devkitc/src/esp32_userleds.c @@ -33,7 +33,7 @@ #include #include -#include "esp32_gpio.h" +#include "espressif/esp_gpio.h" #include "esp32-devkitc.h" /**************************************************************************** @@ -61,7 +61,7 @@ uint32_t board_userled_initialize(void) for (i = 0; i < BOARD_NLEDS; i++) { - esp32_configgpio(g_ledcfg[i], OUTPUT); + esp_configgpio(g_ledcfg[i], OUTPUT); } return BOARD_NLEDS; @@ -75,7 +75,7 @@ void board_userled(int led, bool ledon) { if ((unsigned)led < BOARD_NLEDS) { - esp32_gpiowrite(g_ledcfg[led], ledon); + esp_gpiowrite(g_ledcfg[led], ledon); } } @@ -91,7 +91,6 @@ void board_userled_all(uint32_t ledset) for (i = 0; i < BOARD_NLEDS; i++) { - esp32_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); + esp_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); } } - diff --git a/boards/xtensa/esp32/esp32-devkitc/src/esp32_w5500.c b/boards/xtensa/esp32/esp32-devkitc/src/esp32_w5500.c index 272a0e6ff0861..4fd63da63bfff 100644 --- a/boards/xtensa/esp32/esp32-devkitc/src/esp32_w5500.c +++ b/boards/xtensa/esp32/esp32-devkitc/src/esp32_w5500.c @@ -42,8 +42,8 @@ #include "esp32-devkitc.h" #include "esp32_spi.h" -#include "esp32_gpio.h" -#include "hardware/esp32_gpio_sigmap.h" +#include "espressif/esp_gpio.h" +#include "hardware/esp_gpio_sigmap.h" /**************************************************************************** * Pre-processor Definitions @@ -135,25 +135,22 @@ static void up_enable(const struct w5500_lower_s *lower, bool enable) { struct esp32_lower_s *priv = (struct esp32_lower_s *)lower; - int irq = ESP32_PIN2IRQ(GPIO_W5500_INTR); - int ret; - /* Make sure the interrupt is disabled */ - esp32_gpioirqdisable(irq); + esp_gpioirqdisable(irq); DEBUGASSERT(priv->handler); if (enable) { - ret = irq_attach(irq, priv->handler, priv->arg); + int ret = esp_gpio_irq(GPIO_W5500_INTR, priv->handler, priv->arg); if (ret < 0) { - syslog(LOG_ERR, "ERROR: irq_attach() failed: %d\n", ret); + syslog(LOG_ERR, "ERROR: esp_gpio_irq() failed: %d\n", ret); } /* IRQ on rising edge */ - esp32_gpioirqenable(irq, RISING); + esp_gpioirqenable(GPIO_W5500_INTR); } else { @@ -170,7 +167,7 @@ static void up_reset(const struct w5500_lower_s *lower, bool reset) { /* Take W5500 out of reset (active low) */ - esp32_gpiowrite(GPIO_W5500_RESET, !reset); + esp_gpiowrite(GPIO_W5500_RESET, !reset); } /**************************************************************************** @@ -188,13 +185,12 @@ void riscv_netinitialize(void) /* Configure the interrupt pin */ - esp32_configgpio(GPIO_W5500_INTR, INPUT_FUNCTION_1 | PULLDOWN); + esp_configgpio(GPIO_W5500_INTR, INPUT_FUNCTION_1 | PULLDOWN | RISING); /* Configure the reset pin as output */ - esp32_gpio_matrix_out(GPIO_W5500_RESET, SIG_GPIO_OUT_IDX, 0, 0); - esp32_configgpio(GPIO_W5500_RESET, OUTPUT_FUNCTION_1 | - INPUT_FUNCTION_1); + esp_gpio_matrix_out(GPIO_W5500_RESET, SIG_GPIO_OUT_IDX, 0, 0); + esp_configgpio(GPIO_W5500_RESET, OUTPUT_FUNCTION_1 | INPUT_FUNCTION_1); /* Assumptions: * 1) W5500 pins were configured in up_spi.c early in the boot-up phase. @@ -222,4 +218,3 @@ void riscv_netinitialize(void) ninfo("Bound SPI port %d to W5500 device %d\n", W5500_SPI_PORTNO, W5500_DEVNO); } - diff --git a/boards/xtensa/esp32/esp32-ethernet-kit/configs/autopm/defconfig b/boards/xtensa/esp32/esp32-ethernet-kit/configs/autopm/defconfig index e4f59d4871bc4..c4d2b0109aa57 100644 --- a/boards/xtensa/esp32/esp32-ethernet-kit/configs/autopm/defconfig +++ b/boards/xtensa/esp32/esp32-ethernet-kit/configs/autopm/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32_ETHERNETKIT=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/esp32-ethernet-kit/configs/buttons/defconfig b/boards/xtensa/esp32/esp32-ethernet-kit/configs/buttons/defconfig index b0340187df505..65621a1ad25cb 100644 --- a/boards/xtensa/esp32/esp32-ethernet-kit/configs/buttons/defconfig +++ b/boards/xtensa/esp32/esp32-ethernet-kit/configs/buttons/defconfig @@ -16,12 +16,15 @@ CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y -CONFIG_ESP32_GPIO_IRQ=y CONFIG_ESP32_UART0=y +CONFIG_ESPRESSIF_GPIO_IRQ=y CONFIG_EXAMPLES_BUTTONS=y CONFIG_FS_PROCFS=y CONFIG_HAVE_CXX=y diff --git a/boards/xtensa/esp32/esp32-ethernet-kit/configs/ethernet/defconfig b/boards/xtensa/esp32/esp32-ethernet-kit/configs/ethernet/defconfig index ed6e5f35cc3c1..e8a99d074db94 100644 --- a/boards/xtensa/esp32/esp32-ethernet-kit/configs/ethernet/defconfig +++ b/boards/xtensa/esp32/esp32-ethernet-kit/configs/ethernet/defconfig @@ -14,6 +14,9 @@ CONFIG_ARCH_BOARD_ESP32_ETHERNETKIT=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/esp32-ethernet-kit/configs/nsh/defconfig b/boards/xtensa/esp32/esp32-ethernet-kit/configs/nsh/defconfig index 2b6c0f0bb1925..0370a7727f0bb 100644 --- a/boards/xtensa/esp32/esp32-ethernet-kit/configs/nsh/defconfig +++ b/boards/xtensa/esp32/esp32-ethernet-kit/configs/nsh/defconfig @@ -14,6 +14,9 @@ CONFIG_ARCH_BOARD_ESP32_ETHERNETKIT=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/esp32-ethernet-kit/configs/oneshot/defconfig b/boards/xtensa/esp32/esp32-ethernet-kit/configs/oneshot/defconfig index 745e28e76d852..6421764a44740 100644 --- a/boards/xtensa/esp32/esp32-ethernet-kit/configs/oneshot/defconfig +++ b/boards/xtensa/esp32/esp32-ethernet-kit/configs/oneshot/defconfig @@ -7,7 +7,6 @@ # # CONFIG_NSH_ARGCAT is not set # CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ALARM_ARCH=y CONFIG_ARCH="xtensa" CONFIG_ARCH_BOARD="esp32-ethernet-kit" CONFIG_ARCH_BOARD_COMMON=y @@ -15,6 +14,9 @@ CONFIG_ARCH_BOARD_ESP32_ETHERNETKIT=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 @@ -53,5 +55,4 @@ CONFIG_START_YEAR=2011 CONFIG_SYSLOG_BUFFER=y CONFIG_SYSTEM_NSH=y CONFIG_TIMER=y -CONFIG_TIMER_ARCH=y CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/xtensa/esp32/esp32-ethernet-kit/configs/rtc/defconfig b/boards/xtensa/esp32/esp32-ethernet-kit/configs/rtc/defconfig index 5768a157fbe82..bcdc0adad4717 100644 --- a/boards/xtensa/esp32/esp32-ethernet-kit/configs/rtc/defconfig +++ b/boards/xtensa/esp32/esp32-ethernet-kit/configs/rtc/defconfig @@ -14,11 +14,13 @@ CONFIG_ARCH_BOARD_ESP32_ETHERNETKIT=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y -CONFIG_ESP32_RT_TIMER=y CONFIG_ESP32_UART0=y CONFIG_EXAMPLES_ALARM=y CONFIG_FS_PROCFS=y diff --git a/boards/xtensa/esp32/esp32-ethernet-kit/configs/wifi/defconfig b/boards/xtensa/esp32/esp32-ethernet-kit/configs/wifi/defconfig index 7948f6795b9b2..695083abb9fd6 100644 --- a/boards/xtensa/esp32/esp32-ethernet-kit/configs/wifi/defconfig +++ b/boards/xtensa/esp32/esp32-ethernet-kit/configs/wifi/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32_ETHERNETKIT=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/esp32-ethernet-kit/src/esp32_bringup.c b/boards/xtensa/esp32/esp32-ethernet-kit/src/esp32_bringup.c index 9b5352a5c1ddf..dc6db920ad2f6 100644 --- a/boards/xtensa/esp32/esp32-ethernet-kit/src/esp32_bringup.c +++ b/boards/xtensa/esp32/esp32-ethernet-kit/src/esp32_bringup.c @@ -38,6 +38,8 @@ #include #include "esp32_partition.h" +#include "espressif/esp_gpio.h" +#include "esp32_start.h" #ifdef CONFIG_USERLED # include @@ -55,10 +57,6 @@ # include "esp32_board_wdt.h" #endif -#ifdef CONFIG_ESP32_RT_TIMER -# include "esp32_rt_timer.h" -#endif - #ifdef CONFIG_ESP32_SPIFLASH # include "esp32_board_spiflash.h" #endif @@ -76,7 +74,11 @@ #endif #ifdef CONFIG_RTC_DRIVER -# include "esp32_rtc_lowerhalf.h" +# include "espressif/esp_rtc.h" +#endif + +#ifdef CONFIG_ESPRESSIF_HR_TIMER +# include "espressif/esp_hr_timer.h" #endif #ifdef CONFIG_MMCSD_SPI @@ -162,14 +164,6 @@ int esp32_bringup(void) } #endif -#ifdef CONFIG_ESP32_RT_TIMER - ret = esp32_rt_timer_init(); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize RT timer: %d\n", ret); - } -#endif - #ifdef CONFIG_ESPRESSIF_BLE ret = esp32_ble_initialize(); if (ret) @@ -187,13 +181,21 @@ int esp32_bringup(void) } #endif +#ifdef CONFIG_ESPRESSIF_HR_TIMER + ret = esp_hr_timer_init(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: esp_hr_timer_init() failed: %d\n", ret); + } +#endif + /* First, register the timer drivers and let timer 1 for oneshot * if it is enabled. */ #ifdef CONFIG_TIMER -#if defined(CONFIG_ESP32_TIMER0) && !defined(CONFIG_ESP32_RT_TIMER) +#if defined(CONFIG_ESP32_TIMER0) && !defined(CONFIG_ESPRESSIF_HR_TIMER) ret = esp32_timer_initialize("/dev/timer0", TIMER0); if (ret < 0) { @@ -282,7 +284,7 @@ int esp32_bringup(void) #ifdef CONFIG_RTC_DRIVER /* Instantiate the ESP32 RTC driver */ - ret = esp32_rtc_driverinit(); + ret = esp_rtc_driverinit(); if (ret < 0) { syslog(LOG_ERR, diff --git a/boards/xtensa/esp32/esp32-ethernet-kit/src/esp32_buttons.c b/boards/xtensa/esp32/esp32-ethernet-kit/src/esp32_buttons.c index a0a408b812066..e976367d67443 100644 --- a/boards/xtensa/esp32/esp32-ethernet-kit/src/esp32_buttons.c +++ b/boards/xtensa/esp32/esp32-ethernet-kit/src/esp32_buttons.c @@ -37,7 +37,7 @@ #include #include -#include "esp32_gpio.h" +#include "espressif/esp_gpio.h" #include "esp32-ethernet-kit.h" @@ -58,7 +58,7 @@ uint32_t board_button_initialize(void) { - esp32_configgpio(BUTTON_BOOT, INPUT_FUNCTION_3 | PULLUP); + esp_configgpio(BUTTON_BOOT, INPUT_FUNCTION_3 | PULLUP | CHANGE); return 1; } @@ -79,13 +79,13 @@ uint32_t board_buttons(void) int i = 0; int n = 0; - bool b0 = esp32_gpioread(BUTTON_BOOT); + bool b0 = esp_gpioread(BUTTON_BOOT); for (i = 0; i < 10; i++) { up_mdelay(1); /* TODO */ - bool b1 = esp32_gpioread(BUTTON_BOOT); + bool b1 = esp_gpioread(BUTTON_BOOT); if (b0 == b1) { @@ -131,38 +131,6 @@ uint32_t board_buttons(void) #ifdef CONFIG_ARCH_IRQBUTTONS int board_button_irq(int id, xcpt_t irqhandler, void *arg) { - int ret; - DEBUGASSERT(id == 0); - - int irq = ESP32_PIN2IRQ(BUTTON_BOOT); - - if (NULL != irqhandler) - { - /* Make sure the interrupt is disabled */ - - esp32_gpioirqdisable(irq); - - ret = irq_attach(irq, irqhandler, arg); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: irq_attach() failed: %d\n", ret); - return ret; - } - - gpioinfo("Attach %p\n", irqhandler); - - gpioinfo("Enabling the interrupt\n"); - - /* Configure the interrupt for rising and falling edges */ - - esp32_gpioirqenable(irq, CHANGE); - } - else - { - gpioinfo("Disable the interrupt\n"); - esp32_gpioirqdisable(irq); - } - - return OK; + return esp_gpio_irq(BUTTON_BOOT, irqhandler, arg); } #endif diff --git a/boards/xtensa/esp32/esp32-lyrat/configs/audio/defconfig b/boards/xtensa/esp32/esp32-lyrat/configs/audio/defconfig index 802721ee6002a..eac5fe096a208 100644 --- a/boards/xtensa/esp32/esp32-lyrat/configs/audio/defconfig +++ b/boards/xtensa/esp32/esp32-lyrat/configs/audio/defconfig @@ -19,6 +19,9 @@ CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_AUDIO=y diff --git a/boards/xtensa/esp32/esp32-lyrat/configs/buttons/defconfig b/boards/xtensa/esp32/esp32-lyrat/configs/buttons/defconfig index 3ed6b2b51e5db..0d3fa0d35c0c9 100644 --- a/boards/xtensa/esp32/esp32-lyrat/configs/buttons/defconfig +++ b/boards/xtensa/esp32/esp32-lyrat/configs/buttons/defconfig @@ -17,15 +17,18 @@ CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y -CONFIG_ESP32_GPIO_IRQ=y CONFIG_ESP32_TOUCH=y CONFIG_ESP32_TOUCH_FILTER=y CONFIG_ESP32_TOUCH_IRQ=y CONFIG_ESP32_UART0=y +CONFIG_ESPRESSIF_GPIO_IRQ=y CONFIG_EXAMPLES_BUTTONS=y CONFIG_FS_PROCFS=y CONFIG_HAVE_CXX=y diff --git a/boards/xtensa/esp32/esp32-lyrat/configs/nsh/defconfig b/boards/xtensa/esp32/esp32-lyrat/configs/nsh/defconfig index 1813c08b5d6af..d351fbac6c607 100644 --- a/boards/xtensa/esp32/esp32-lyrat/configs/nsh/defconfig +++ b/boards/xtensa/esp32/esp32-lyrat/configs/nsh/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32_LYRAT=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/esp32-lyrat/configs/nxrecorder/defconfig b/boards/xtensa/esp32/esp32-lyrat/configs/nxrecorder/defconfig index cd23636a9f435..6065c2e632f5a 100644 --- a/boards/xtensa/esp32/esp32-lyrat/configs/nxrecorder/defconfig +++ b/boards/xtensa/esp32/esp32-lyrat/configs/nxrecorder/defconfig @@ -20,6 +20,9 @@ CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y CONFIG_ARCH_INTERRUPTSTACK=4096 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_AUDIO=y diff --git a/boards/xtensa/esp32/esp32-lyrat/configs/rtptools/defconfig b/boards/xtensa/esp32/esp32-lyrat/configs/rtptools/defconfig index 953e1f3e484b7..45dcf427807e4 100644 --- a/boards/xtensa/esp32/esp32-lyrat/configs/rtptools/defconfig +++ b/boards/xtensa/esp32/esp32-lyrat/configs/rtptools/defconfig @@ -19,6 +19,9 @@ CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y CONFIG_ARCH_INTERRUPTSTACK=4096 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_AUDIO=y diff --git a/boards/xtensa/esp32/esp32-lyrat/configs/sdmmc_spi/defconfig b/boards/xtensa/esp32/esp32-lyrat/configs/sdmmc_spi/defconfig index 510fc0058715c..c50407f9536b4 100644 --- a/boards/xtensa/esp32/esp32-lyrat/configs/sdmmc_spi/defconfig +++ b/boards/xtensa/esp32/esp32-lyrat/configs/sdmmc_spi/defconfig @@ -20,6 +20,9 @@ CONFIG_ARCH_BOARD_ESP32_LYRAT=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/esp32-lyrat/configs/wifi/defconfig b/boards/xtensa/esp32/esp32-lyrat/configs/wifi/defconfig index 1ec8df534577b..b262f72b2e5c8 100644 --- a/boards/xtensa/esp32/esp32-lyrat/configs/wifi/defconfig +++ b/boards/xtensa/esp32/esp32-lyrat/configs/wifi/defconfig @@ -17,6 +17,9 @@ CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/esp32-lyrat/src/esp32_bringup.c b/boards/xtensa/esp32/esp32-lyrat/src/esp32_bringup.c index 1d2d1eea236f5..7c3bf07d3ec44 100644 --- a/boards/xtensa/esp32/esp32-lyrat/src/esp32_bringup.c +++ b/boards/xtensa/esp32/esp32-lyrat/src/esp32_bringup.c @@ -39,8 +39,9 @@ #include #include "esp32_i2c.h" -#include "esp32_gpio.h" +#include "espressif/esp_gpio.h" #include "esp32_partition.h" +#include "esp32_start.h" #include @@ -92,17 +93,17 @@ # include #endif -#ifdef CONFIG_ESP32_RT_TIMER -# include "esp32_rt_timer.h" -#endif - #ifdef CONFIG_LCD_DEV # include # include #endif #ifdef CONFIG_RTC_DRIVER -# include "esp32_rtc_lowerhalf.h" +# include "espressif/esp_rtc.h" +#endif + +#ifdef CONFIG_ESPRESSIF_HR_TIMER +# include "espressif/esp_hr_timer.h" #endif #ifdef CONFIG_LCD_BACKPACK @@ -202,14 +203,6 @@ int esp32_bringup(void) } #endif -#ifdef CONFIG_ESP32_RT_TIMER - ret = esp32_rt_timer_init(); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize RT timer: %d\n", ret); - } -#endif - #ifdef CONFIG_ESPRESSIF_BLE ret = esp32_ble_initialize(); if (ret) @@ -227,13 +220,21 @@ int esp32_bringup(void) } #endif +#ifdef CONFIG_ESPRESSIF_HR_TIMER + ret = esp_hr_timer_init(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: esp_hr_timer_init() failed: %d\n", ret); + } +#endif + /* First, register the timer drivers and let timer 1 for oneshot * if it is enabled. */ #ifdef CONFIG_TIMER -#if defined(CONFIG_ESP32_TIMER0) && !defined(CONFIG_ESP32_RT_TIMER) +#if defined(CONFIG_ESP32_TIMER0) && !defined(CONFIG_ESPRESSIF_HR_TIMER) ret = esp32_timer_initialize("/dev/timer0", TIMER0); if (ret < 0) { @@ -345,8 +346,8 @@ int esp32_bringup(void) /* Configure ES8388 audio on I2C0 and I2S0 */ - esp32_configgpio(SPEAKER_ENABLE_GPIO, OUTPUT); - esp32_gpiowrite(SPEAKER_ENABLE_GPIO, true); + esp_configgpio(SPEAKER_ENABLE_GPIO, OUTPUT); + esp_gpiowrite(SPEAKER_ENABLE_GPIO, true); ret = esp32_es8388_initialize(ESP32_I2C0, ES8388_I2C_ADDR, ES8388_I2C_FREQ, ESP32_I2S0); @@ -429,7 +430,7 @@ int esp32_bringup(void) #ifdef CONFIG_RTC_DRIVER /* Instantiate the ESP32 RTC driver */ - ret = esp32_rtc_driverinit(); + ret = esp_rtc_driverinit(); if (ret < 0) { syslog(LOG_ERR, diff --git a/boards/xtensa/esp32/esp32-lyrat/src/esp32_buttons.c b/boards/xtensa/esp32/esp32-lyrat/src/esp32_buttons.c index afbf937fed3ee..b3b7bc82a66b4 100644 --- a/boards/xtensa/esp32/esp32-lyrat/src/esp32_buttons.c +++ b/boards/xtensa/esp32/esp32-lyrat/src/esp32_buttons.c @@ -40,7 +40,7 @@ #include #include -#include "esp32_gpio.h" +#include "espressif/esp_gpio.h" #include "esp32_touch.h" #include "esp32-lyrat.h" @@ -167,8 +167,8 @@ uint32_t board_button_initialize(void) /* GPIOs 36 and 39 do not support PULLUP/PULLDOWN */ - esp32_configgpio(BUTTON_MODE, INPUT_FUNCTION_3); - esp32_configgpio(BUTTON_REC, INPUT_FUNCTION_3); + esp_configgpio(BUTTON_MODE, INPUT_FUNCTION_3); + esp_configgpio(BUTTON_REC, INPUT_FUNCTION_3); return NUM_BUTTONS; } @@ -204,9 +204,10 @@ uint32_t board_buttons(void) } else { - b0 = esp32_gpioread(button_info.input.gpio); + int i; + b0 = esp_gpioread(button_info.input.gpio); - for (int i = 0; i < 10; i++) + for (i = 0; i < 10; i++) { up_mdelay(1); @@ -216,7 +217,7 @@ uint32_t board_buttons(void) } else { - b1 = esp32_gpioread(button_info.input.gpio); + b1 = esp_gpioread(button_info.input.gpio); } if (b0 == b1) @@ -282,11 +283,11 @@ int board_button_irq(int id, xcpt_t irqhandler, void *arg) esp32_touchirqdisable(irq); - esp32_touchregisterreleasecb(irqhandler); - ret = irq_attach(irq, irqhandler, arg); + ret = esp32_touchirqattach(irq, irqhandler, arg); if (ret < 0) { - syslog(LOG_ERR, "ERROR: irq_attach() failed: %d\n", ret); + syslog(LOG_ERR, "ERROR: esp32_touchirqattach() failed: %d\n", + ret); return ret; } @@ -307,37 +308,7 @@ int board_button_irq(int id, xcpt_t irqhandler, void *arg) else #endif { - int pin = button_info.input.gpio; - int irq = ESP32_PIN2IRQ(pin); - - if (NULL != irqhandler) - { - /* Make sure the interrupt is disabled */ - - esp32_gpioirqdisable(irq); - - ret = irq_attach(irq, irqhandler, arg); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: irq_attach() failed: %d\n", ret); - return ret; - } - - gpioinfo("Attach %p to pin %d\n", irqhandler, pin); - - gpioinfo("Enabling the interrupt\n"); - - /* Configure the interrupt for rising and falling edges */ - - esp32_gpioirqenable(irq, CHANGE); - } - else - { - gpioinfo("Disabled interrupts from pin %d\n", pin); - esp32_gpioirqdisable(irq); - } - - return OK; + return esp_gpio_irq(button_info.input.gpio, irqhandler, arg); } } #endif diff --git a/boards/xtensa/esp32/esp32-lyrat/src/esp32_gpio.c b/boards/xtensa/esp32/esp32-lyrat/src/esp32_gpio.c index de864768db825..6f81d6981c331 100644 --- a/boards/xtensa/esp32/esp32-lyrat/src/esp32_gpio.c +++ b/boards/xtensa/esp32/esp32-lyrat/src/esp32_gpio.c @@ -37,7 +37,7 @@ #include #include "esp32-lyrat.h" -#include "esp32_gpio.h" +#include "espressif/esp_gpio.h" #include "hardware/esp32_gpio_sigmap.h" #if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF) @@ -46,7 +46,7 @@ * Pre-processor Definitions ****************************************************************************/ -#if !defined(CONFIG_ESP32_GPIO_IRQ) && BOARD_NGPIOINT > 0 +#if !defined(CONFIG_ESPRESSIF_GPIO_IRQ) && BOARD_NGPIOINT > 0 # error "NGPIOINT is > 0 and GPIO interrupts aren't enabled" #endif @@ -182,7 +182,7 @@ static int gpout_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(esp32gpio->id < BOARD_NGPIOOUT); gpioinfo("Reading...\n"); - *value = esp32_gpioread(g_gpiooutputs[esp32gpio->id]); + *value = esp_gpioread(g_gpiooutputs[esp32gpio->id]); return OK; } @@ -198,7 +198,7 @@ static int gpout_write(struct gpio_dev_s *dev, bool value) DEBUGASSERT(esp32gpio->id < BOARD_NGPIOOUT); gpioinfo("Writing %d\n", (int)value); - esp32_gpiowrite(g_gpiooutputs[esp32gpio->id], value); + esp_gpiowrite(g_gpiooutputs[esp32gpio->id], value); return OK; } #endif @@ -216,7 +216,7 @@ static int gpin_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(esp32gpio->id < BOARD_NGPIOIN); gpioinfo("Reading... pin %" PRIu32 "\n", g_gpioinputs[esp32gpio->id]); - *value = esp32_gpioread(g_gpioinputs[esp32gpio->id]); + *value = esp_gpioread(g_gpioinputs[esp32gpio->id]); return OK; } #endif @@ -252,7 +252,7 @@ static int gpint_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(esp32gpint->esp32gpio.id < BOARD_NGPIOINT); gpioinfo("Reading int pin...\n"); - *value = esp32_gpioread(g_gpiointinputs[esp32gpint->esp32gpio.id]); + *value = esp_gpioread(g_gpiointinputs[esp32gpint->esp32gpio.id]); return OK; } @@ -265,23 +265,26 @@ static int gpint_attach(struct gpio_dev_s *dev, { struct esp32gpint_dev_s *esp32gpint = (struct esp32gpint_dev_s *)dev; - int irq = ESP32_PIN2IRQ(g_gpiointinputs[esp32gpint->esp32gpio.id]); int ret; gpioinfo("Attaching the callback\n"); /* Make sure the interrupt is disabled */ - esp32_gpioirqdisable(irq); - ret = irq_attach(irq, - esp32gpio_interrupt, - &g_gpint[esp32gpint->esp32gpio.id]); + esp_gpioirqdisable(g_gpiointinputs[esp32gpint->esp32gpio.id]); + + ret = esp_gpio_irq(g_gpiointinputs[esp32gpint->esp32gpio.id], + esp32gpio_interrupt, + &g_gpint[esp32gpint->esp32gpio.id]); if (ret < 0) { - syslog(LOG_ERR, "ERROR: gpint_attach() failed: %d\n", ret); return ret; } + /* Make sure the interrupt is disabled */ + + esp_gpioirqdisable(g_gpiointinputs[esp32gpint->esp32gpio.id]); + gpioinfo("Attach %p\n", callback); esp32gpint->callback = callback; return OK; @@ -295,7 +298,6 @@ static int gpint_enable(struct gpio_dev_s *dev, bool enable) { struct esp32gpint_dev_s *esp32gpint = (struct esp32gpint_dev_s *)dev; - int irq = ESP32_PIN2IRQ(g_gpiointinputs[esp32gpint->esp32gpio.id]); if (enable) { @@ -305,13 +307,13 @@ static int gpint_enable(struct gpio_dev_s *dev, bool enable) /* Configure the interrupt for rising edge */ - esp32_gpioirqenable(irq, RISING); + esp_gpioirqenable(g_gpiointinputs[esp32gpint->esp32gpio.id]); } } else { gpioinfo("Disable the interrupt\n"); - esp32_gpioirqdisable(irq); + esp_gpioirqdisable(g_gpiointinputs[esp32gpint->esp32gpio.id]); } return OK; @@ -343,10 +345,9 @@ int esp32_gpio_init(void) /* Configure the pins that will be used as output */ - esp32_gpio_matrix_out(g_gpiooutputs[i], SIG_GPIO_OUT_IDX, 0, 0); - esp32_configgpio(g_gpiooutputs[i], OUTPUT_FUNCTION_3 | - INPUT_FUNCTION_3); - esp32_gpiowrite(g_gpiooutputs[i], 0); + esp_gpio_matrix_out(g_gpiooutputs[i], SIG_GPIO_OUT_IDX, 0, 0); + esp_configgpio(g_gpiooutputs[i], OUTPUT_FUNCTION_3 | INPUT_FUNCTION_3); + esp_gpiowrite(g_gpiooutputs[i], 0); pincount++; } @@ -364,7 +365,7 @@ int esp32_gpio_init(void) /* Configure the pins that will be used as INPUT */ - esp32_configgpio(g_gpioinputs[i], INPUT_FUNCTION_3); + esp_configgpio(g_gpioinputs[i], INPUT_FUNCTION_3 | PULLDOWN); pincount++; } @@ -382,7 +383,8 @@ int esp32_gpio_init(void) /* Configure the pins that will be used as interrupt input */ - esp32_configgpio(g_gpiointinputs[i], INPUT_FUNCTION_3 | PULLDOWN); + esp_configgpio(g_gpiointinputs[i], + INPUT_FUNCTION_3 | PULLUP | FALLING); pincount++; } diff --git a/boards/xtensa/esp32/esp32-lyrat/src/esp32_userleds.c b/boards/xtensa/esp32/esp32-lyrat/src/esp32_userleds.c index 300bd8c371393..122d3a3ed37e3 100644 --- a/boards/xtensa/esp32/esp32-lyrat/src/esp32_userleds.c +++ b/boards/xtensa/esp32/esp32-lyrat/src/esp32_userleds.c @@ -33,7 +33,7 @@ #include #include -#include "esp32_gpio.h" +#include "espressif/esp_gpio.h" #include "esp32-lyrat.h" /**************************************************************************** @@ -63,7 +63,7 @@ uint32_t board_userled_initialize(void) for (i = 0; i < BOARD_NLEDS; i++) { - esp32_configgpio(g_ledcfg[i], OUTPUT); + esp_configgpio(g_ledcfg[i], OUTPUT); } return BOARD_NLEDS; @@ -77,7 +77,7 @@ void board_userled(int led, bool ledon) { if ((unsigned)led < BOARD_NLEDS) { - esp32_gpiowrite(g_ledcfg[led], ledon); + esp_gpiowrite(g_ledcfg[led], ledon); } } @@ -91,7 +91,6 @@ void board_userled_all(uint32_t ledset) for (i = 0; i < BOARD_NLEDS; i++) { - esp32_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); + esp_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); } } - diff --git a/boards/xtensa/esp32/esp32-pico-kit/configs/nsh/defconfig b/boards/xtensa/esp32/esp32-pico-kit/configs/nsh/defconfig index 71b45da98b592..7cb9469402a9c 100644 --- a/boards/xtensa/esp32/esp32-pico-kit/configs/nsh/defconfig +++ b/boards/xtensa/esp32/esp32-pico-kit/configs/nsh/defconfig @@ -14,6 +14,9 @@ CONFIG_ARCH_BOARD_ESP32_PICO_KIT=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32PICOD4=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/esp32-pico-kit/src/esp32_bringup.c b/boards/xtensa/esp32/esp32-pico-kit/src/esp32_bringup.c index 0741b6bd28878..84399aa9e1b9c 100644 --- a/boards/xtensa/esp32/esp32-pico-kit/src/esp32_bringup.c +++ b/boards/xtensa/esp32/esp32-pico-kit/src/esp32_bringup.c @@ -46,6 +46,8 @@ #include "espressif/esp_efuse.h" #endif #include "esp32_partition.h" +#include "espressif/esp_gpio.h" +#include "esp32_start.h" #ifdef CONFIG_TIMER #include @@ -87,16 +89,16 @@ # include "esp32_aes.h" #endif -#ifdef CONFIG_ESP32_RT_TIMER -# include "esp32_rt_timer.h" -#endif - #ifdef CONFIG_INPUT_BUTTONS # include #endif #ifdef CONFIG_RTC_DRIVER -# include "esp32_rtc_lowerhalf.h" +# include "espressif/esp_rtc.h" +#endif + +#ifdef CONFIG_ESPRESSIF_HR_TIMER +# include "espressif/esp_hr_timer.h" #endif #ifdef CONFIG_SPI_DRIVER @@ -220,14 +222,6 @@ int esp32_bringup(void) } #endif -#ifdef CONFIG_ESP32_RT_TIMER - ret = esp32_rt_timer_init(); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize RT timer: %d\n", ret); - } -#endif - #ifdef CONFIG_ESPRESSIF_WIFI_BT_COEXIST ret = esp32_wifi_bt_coexist_init(); if (ret) @@ -254,13 +248,21 @@ int esp32_bringup(void) } #endif +#ifdef CONFIG_ESPRESSIF_HR_TIMER + ret = esp_hr_timer_init(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: esp_hr_timer_init() failed: %d\n", ret); + } +#endif + /* First, register the timer drivers and let timer 1 for oneshot * if it is enabled. */ #ifdef CONFIG_TIMER -#if defined(CONFIG_ESP32_TIMER0) && !defined(CONFIG_ESP32_RT_TIMER) +#if defined(CONFIG_ESP32_TIMER0) && !defined(CONFIG_ESPRESSIF_HR_TIMER) ret = esp32_timer_initialize("/dev/timer0", TIMER0); if (ret < 0) { @@ -426,7 +428,7 @@ int esp32_bringup(void) #ifdef CONFIG_RTC_DRIVER /* Instantiate the ESP32 RTC driver */ - ret = esp32_rtc_driverinit(); + ret = esp_rtc_driverinit(); if (ret < 0) { syslog(LOG_ERR, diff --git a/boards/xtensa/esp32/esp32-pico-kit/src/esp32_buttons.c b/boards/xtensa/esp32/esp32-pico-kit/src/esp32_buttons.c index 881741eace89c..3aa1d52308712 100644 --- a/boards/xtensa/esp32/esp32-pico-kit/src/esp32_buttons.c +++ b/boards/xtensa/esp32/esp32-pico-kit/src/esp32_buttons.c @@ -37,7 +37,7 @@ #include #include -#include "esp32_gpio.h" +#include "espressif/esp_gpio.h" #include "esp32-pico-kit.h" @@ -58,7 +58,7 @@ uint32_t board_button_initialize(void) { - esp32_configgpio(BUTTON_BOOT, INPUT_FUNCTION_3 | PULLUP); + esp_configgpio(BUTTON_BOOT, INPUT_FUNCTION_3 | PULLUP | CHANGE); return 1; } @@ -79,13 +79,13 @@ uint32_t board_buttons(void) int i = 0; int n = 0; - bool b0 = esp32_gpioread(BUTTON_BOOT); + bool b0 = esp_gpioread(BUTTON_BOOT); for (i = 0; i < 10; i++) { up_mdelay(1); /* TODO */ - bool b1 = esp32_gpioread(BUTTON_BOOT); + bool b1 = esp_gpioread(BUTTON_BOOT); if (b0 == b1) { @@ -131,38 +131,6 @@ uint32_t board_buttons(void) #ifdef CONFIG_ARCH_IRQBUTTONS int board_button_irq(int id, xcpt_t irqhandler, void *arg) { - int ret; - DEBUGASSERT(id == 0); - - int irq = ESP32_PIN2IRQ(BUTTON_BOOT); - - if (NULL != irqhandler) - { - /* Make sure the interrupt is disabled */ - - esp32_gpioirqdisable(irq); - - ret = irq_attach(irq, irqhandler, arg); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: irq_attach() failed: %d\n", ret); - return ret; - } - - gpioinfo("Attach %p\n", irqhandler); - - gpioinfo("Enabling the interrupt\n"); - - /* Configure the interrupt for rising and falling edges */ - - esp32_gpioirqenable(irq, CHANGE); - } - else - { - gpioinfo("Disable the interrupt\n"); - esp32_gpioirqdisable(irq); - } - - return OK; + return esp_gpio_irq(BUTTON_BOOT, irqhandler, arg); } #endif diff --git a/boards/xtensa/esp32/esp32-pico-kit/src/esp32_gpio.c b/boards/xtensa/esp32/esp32-pico-kit/src/esp32_gpio.c index 1ffe6e08fce5f..9fcd9778cbf45 100644 --- a/boards/xtensa/esp32/esp32-pico-kit/src/esp32_gpio.c +++ b/boards/xtensa/esp32/esp32-pico-kit/src/esp32_gpio.c @@ -37,7 +37,7 @@ #include #include "esp32-pico-kit.h" -#include "esp32_gpio.h" +#include "espressif/esp_gpio.h" #include "hardware/esp32_gpio_sigmap.h" #if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF) @@ -46,7 +46,7 @@ * Pre-processor Definitions ****************************************************************************/ -#if !defined(CONFIG_ESP32_GPIO_IRQ) && BOARD_NGPIOINT > 0 +#if !defined(CONFIG_ESPRESSIF_GPIO_IRQ) && BOARD_NGPIOINT > 0 # error "NGPIOINT is > 0 and GPIO interrupts aren't enabled" #endif @@ -182,7 +182,7 @@ static int gpout_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(esp32gpio->id < BOARD_NGPIOOUT); gpioinfo("Reading...\n"); - *value = esp32_gpioread(g_gpiooutputs[esp32gpio->id]); + *value = esp_gpioread(g_gpiooutputs[esp32gpio->id]); return OK; } @@ -198,7 +198,7 @@ static int gpout_write(struct gpio_dev_s *dev, bool value) DEBUGASSERT(esp32gpio->id < BOARD_NGPIOOUT); gpioinfo("Writing %d\n", (int)value); - esp32_gpiowrite(g_gpiooutputs[esp32gpio->id], value); + esp_gpiowrite(g_gpiooutputs[esp32gpio->id], value); return OK; } #endif @@ -216,7 +216,7 @@ static int gpin_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(esp32gpio->id < BOARD_NGPIOIN); gpioinfo("Reading... pin %" PRIu32 "\n", g_gpioinputs[esp32gpio->id]); - *value = esp32_gpioread(g_gpioinputs[esp32gpio->id]); + *value = esp_gpioread(g_gpioinputs[esp32gpio->id]); return OK; } #endif @@ -252,7 +252,7 @@ static int gpint_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(esp32gpint->esp32gpio.id < BOARD_NGPIOINT); gpioinfo("Reading int pin...\n"); - *value = esp32_gpioread(g_gpiointinputs[esp32gpint->esp32gpio.id]); + *value = esp_gpioread(g_gpiointinputs[esp32gpint->esp32gpio.id]); return OK; } @@ -265,23 +265,26 @@ static int gpint_attach(struct gpio_dev_s *dev, { struct esp32gpint_dev_s *esp32gpint = (struct esp32gpint_dev_s *)dev; - int irq = ESP32_PIN2IRQ(g_gpiointinputs[esp32gpint->esp32gpio.id]); int ret; gpioinfo("Attaching the callback\n"); /* Make sure the interrupt is disabled */ - esp32_gpioirqdisable(irq); - ret = irq_attach(irq, - esp32gpio_interrupt, - &g_gpint[esp32gpint->esp32gpio.id]); + esp_gpioirqdisable(g_gpiointinputs[esp32gpint->esp32gpio.id]); + + ret = esp_gpio_irq(g_gpiointinputs[esp32gpint->esp32gpio.id], + esp32gpio_interrupt, + &g_gpint[esp32gpint->esp32gpio.id]); if (ret < 0) { - syslog(LOG_ERR, "ERROR: gpint_attach() failed: %d\n", ret); return ret; } + /* Make sure the interrupt is disabled */ + + esp_gpioirqdisable(g_gpiointinputs[esp32gpint->esp32gpio.id]); + gpioinfo("Attach %p\n", callback); esp32gpint->callback = callback; return OK; @@ -295,7 +298,6 @@ static int gpint_enable(struct gpio_dev_s *dev, bool enable) { struct esp32gpint_dev_s *esp32gpint = (struct esp32gpint_dev_s *)dev; - int irq = ESP32_PIN2IRQ(g_gpiointinputs[esp32gpint->esp32gpio.id]); if (enable) { @@ -305,13 +307,13 @@ static int gpint_enable(struct gpio_dev_s *dev, bool enable) /* Configure the interrupt for rising edge */ - esp32_gpioirqenable(irq, RISING); + esp_gpioirqenable(g_gpiointinputs[esp32gpint->esp32gpio.id]); } } else { gpioinfo("Disable the interrupt\n"); - esp32_gpioirqdisable(irq); + esp_gpioirqdisable(g_gpiointinputs[esp32gpint->esp32gpio.id]); } return OK; @@ -343,10 +345,9 @@ int esp32_gpio_init(void) /* Configure the pins that will be used as output */ - esp32_gpio_matrix_out(g_gpiooutputs[i], SIG_GPIO_OUT_IDX, 0, 0); - esp32_configgpio(g_gpiooutputs[i], OUTPUT_FUNCTION_3 | - INPUT_FUNCTION_3); - esp32_gpiowrite(g_gpiooutputs[i], 0); + esp_gpio_matrix_out(g_gpiooutputs[i], SIG_GPIO_OUT_IDX, 0, 0); + esp_configgpio(g_gpiooutputs[i], OUTPUT_FUNCTION_3 | INPUT_FUNCTION_3); + esp_gpiowrite(g_gpiooutputs[i], 0); pincount++; } @@ -364,7 +365,7 @@ int esp32_gpio_init(void) /* Configure the pins that will be used as INPUT */ - esp32_configgpio(g_gpioinputs[i], INPUT_FUNCTION_3); + esp_configgpio(g_gpioinputs[i], INPUT_FUNCTION_3 | PULLDOWN); pincount++; } @@ -382,7 +383,8 @@ int esp32_gpio_init(void) /* Configure the pins that will be used as interrupt input */ - esp32_configgpio(g_gpiointinputs[i], INPUT_FUNCTION_3 | PULLDOWN); + esp_configgpio(g_gpiointinputs[i], + INPUT_FUNCTION_3 | PULLUP | FALLING); pincount++; } diff --git a/boards/xtensa/esp32/esp32-sparrow-kit/configs/ble/defconfig b/boards/xtensa/esp32/esp32-sparrow-kit/configs/ble/defconfig index 69e4b496d5ce8..06433e7cb8f82 100644 --- a/boards/xtensa/esp32/esp32-sparrow-kit/configs/ble/defconfig +++ b/boards/xtensa/esp32/esp32-sparrow-kit/configs/ble/defconfig @@ -21,6 +21,9 @@ CONFIG_ARCH_BOARD_ESP32_SPARROWKIT=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_AUDIO=y @@ -103,7 +106,6 @@ CONFIG_START_YEAR=2011 CONFIG_SYSLOG_BUFFER=y CONFIG_SYSTEM_NSH=y CONFIG_TIMER=y -CONFIG_TIMER_ARCH=y CONFIG_UART0_SERIAL_CONSOLE=y CONFIG_WIRELESS=y CONFIG_WIRELESS_BLUETOOTH=y diff --git a/boards/xtensa/esp32/esp32-sparrow-kit/configs/mqttc/defconfig b/boards/xtensa/esp32/esp32-sparrow-kit/configs/mqttc/defconfig index 8167d06a1bfd4..72be12dde513d 100644 --- a/boards/xtensa/esp32/esp32-sparrow-kit/configs/mqttc/defconfig +++ b/boards/xtensa/esp32/esp32-sparrow-kit/configs/mqttc/defconfig @@ -17,6 +17,9 @@ CONFIG_ARCH_BOARD_ESP32_SPARROWKIT=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_AUDIO=y @@ -124,7 +127,6 @@ CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y CONFIG_TIMER=y -CONFIG_TIMER_ARCH=y CONFIG_TLS_TASK_NELEM=4 CONFIG_UART0_SERIAL_CONSOLE=y CONFIG_VIDEO_FB=y diff --git a/boards/xtensa/esp32/esp32-sparrow-kit/configs/nsh/defconfig b/boards/xtensa/esp32/esp32-sparrow-kit/configs/nsh/defconfig index e7b6b911077ec..6e3fd40b456a1 100644 --- a/boards/xtensa/esp32/esp32-sparrow-kit/configs/nsh/defconfig +++ b/boards/xtensa/esp32/esp32-sparrow-kit/configs/nsh/defconfig @@ -20,6 +20,9 @@ CONFIG_ARCH_BOARD_ESP32_SPARROWKIT=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_AUDIO=y @@ -100,6 +103,5 @@ CONFIG_START_YEAR=2011 CONFIG_SYSLOG_BUFFER=y CONFIG_SYSTEM_NSH=y CONFIG_TIMER=y -CONFIG_TIMER_ARCH=y CONFIG_UART0_SERIAL_CONSOLE=y CONFIG_VIDEO_FB=y diff --git a/boards/xtensa/esp32/esp32-sparrow-kit/configs/wifi/defconfig b/boards/xtensa/esp32/esp32-sparrow-kit/configs/wifi/defconfig index 43c7c2d49c777..2f617f8b1a0d4 100644 --- a/boards/xtensa/esp32/esp32-sparrow-kit/configs/wifi/defconfig +++ b/boards/xtensa/esp32/esp32-sparrow-kit/configs/wifi/defconfig @@ -18,6 +18,9 @@ CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_AUDIO=y @@ -128,7 +131,6 @@ CONFIG_SYSTEM_DHCPC_RENEW=y CONFIG_SYSTEM_NSH=y CONFIG_SYSTEM_PING=y CONFIG_TIMER=y -CONFIG_TIMER_ARCH=y CONFIG_TLS_TASK_NELEM=4 CONFIG_UART0_SERIAL_CONSOLE=y CONFIG_VIDEO_FB=y diff --git a/boards/xtensa/esp32/esp32-sparrow-kit/src/esp32_autoleds.c b/boards/xtensa/esp32/esp32-sparrow-kit/src/esp32_autoleds.c index ce3cc25d0c5e4..89f7b1d05a599 100644 --- a/boards/xtensa/esp32/esp32-sparrow-kit/src/esp32_autoleds.c +++ b/boards/xtensa/esp32/esp32-sparrow-kit/src/esp32_autoleds.c @@ -33,7 +33,7 @@ #include #include -#include "esp32_gpio.h" +#include "espressif/esp_gpio.h" #include "esp32-sparrow-kit.h" #ifdef CONFIG_ARCH_LEDS @@ -82,17 +82,17 @@ static inline void led_clrbits(unsigned int clrbits) { if ((clrbits & BOARD_LED1_BIT) != 0) { - esp32_gpiowrite(GPIO_LED1, false); + esp_gpiowrite(GPIO_LED1, false); } if ((clrbits & BOARD_LED2_BIT) != 0) { - esp32_gpiowrite(GPIO_LED2, false); + esp_gpiowrite(GPIO_LED2, false); } if ((clrbits & BOARD_LED3_BIT) != 0) { - esp32_gpiowrite(GPIO_LED3, false); + esp_gpiowrite(GPIO_LED3, false); } } @@ -100,17 +100,17 @@ static inline void led_setbits(unsigned int setbits) { if ((setbits & BOARD_LED1_BIT) != 0) { - esp32_gpiowrite(GPIO_LED1, true); + esp_gpiowrite(GPIO_LED1, true); } if ((setbits & BOARD_LED2_BIT) != 0) { - esp32_gpiowrite(GPIO_LED2, true); + esp_gpiowrite(GPIO_LED2, true); } if ((setbits & BOARD_LED3_BIT) != 0) { - esp32_gpiowrite(GPIO_LED3, true); + esp_gpiowrite(GPIO_LED3, true); } } @@ -126,9 +126,9 @@ void board_autoled_initialize(void) { /* Configure LED1-4 GPIOs for output */ - esp32_configgpio(GPIO_LED1, OUTPUT); - esp32_configgpio(GPIO_LED2, OUTPUT); - esp32_configgpio(GPIO_LED3, OUTPUT); + esp_configgpio(GPIO_LED1, OUTPUT); + esp_configgpio(GPIO_LED2, OUTPUT); + esp_configgpio(GPIO_LED3, OUTPUT); } /**************************************************************************** @@ -141,13 +141,13 @@ void board_autoled_on(int led) switch (led) { case LED_CPU0: - esp32_gpiowrite(GPIO_LED1, true); + esp_gpiowrite(GPIO_LED1, true); break; case LED_CPU1: - esp32_gpiowrite(GPIO_LED2, true); + esp_gpiowrite(GPIO_LED2, true); break; case LED_HEAPALLOCATE: - esp32_gpiowrite(GPIO_LED3, true); + esp_gpiowrite(GPIO_LED3, true); break; default: break; @@ -168,13 +168,13 @@ void board_autoled_off(int led) switch (led) { case LED_CPU0: - esp32_gpiowrite(GPIO_LED1, false); + esp_gpiowrite(GPIO_LED1, false); break; case LED_CPU1: - esp32_gpiowrite(GPIO_LED2, false); + esp_gpiowrite(GPIO_LED2, false); break; case LED_HEAPALLOCATE: - esp32_gpiowrite(GPIO_LED3, false); + esp_gpiowrite(GPIO_LED3, false); break; default: break; diff --git a/boards/xtensa/esp32/esp32-sparrow-kit/src/esp32_bringup.c b/boards/xtensa/esp32/esp32-sparrow-kit/src/esp32_bringup.c index 173e4f97511f2..0b11a9afbc4b8 100644 --- a/boards/xtensa/esp32/esp32-sparrow-kit/src/esp32_bringup.c +++ b/boards/xtensa/esp32/esp32-sparrow-kit/src/esp32_bringup.c @@ -40,6 +40,8 @@ #include #include "esp32_partition.h" +#include "espressif/esp_gpio.h" +#include "esp32_start.h" #include @@ -103,17 +105,17 @@ # include #endif -#ifdef CONFIG_ESP32_RT_TIMER -# include "esp32_rt_timer.h" -#endif - #ifdef CONFIG_LCD_DEV # include # include #endif #ifdef CONFIG_RTC_DRIVER -# include "esp32_rtc_lowerhalf.h" +# include "espressif/esp_rtc.h" +#endif + +#ifdef CONFIG_ESPRESSIF_HR_TIMER +# include "espressif/esp_hr_timer.h" #endif #ifdef CONFIG_LCD_BACKPACK @@ -213,14 +215,6 @@ int esp32_bringup(void) } #endif -#ifdef CONFIG_ESP32_RT_TIMER - ret = esp32_rt_timer_init(); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize RT timer: %d\n", ret); - } -#endif - #ifdef CONFIG_ESPRESSIF_BLE ret = esp32_ble_initialize(); if (ret) @@ -238,13 +232,21 @@ int esp32_bringup(void) } #endif +#ifdef CONFIG_ESPRESSIF_HR_TIMER + ret = esp_hr_timer_init(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: esp_hr_timer_init() failed: %d\n", ret); + } +#endif + /* First, register the timer drivers and let timer 1 for oneshot * if it is enabled. */ #ifdef CONFIG_TIMER -#if defined(CONFIG_ESP32_TIMER0) && !defined(CONFIG_ESP32_RT_TIMER) +#if defined(CONFIG_ESP32_TIMER0) && !defined(CONFIG_ESPRESSIF_HR_TIMER) ret = esp32_timer_initialize("/dev/timer0", TIMER0); if (ret < 0) { @@ -431,7 +433,7 @@ int esp32_bringup(void) #ifdef CONFIG_RTC_DRIVER /* Instantiate the ESP32 RTC driver */ - ret = esp32_rtc_driverinit(); + ret = esp_rtc_driverinit(); if (ret < 0) { syslog(LOG_ERR, diff --git a/boards/xtensa/esp32/esp32-sparrow-kit/src/esp32_buttons.c b/boards/xtensa/esp32/esp32-sparrow-kit/src/esp32_buttons.c index acf459d86e586..618ba50f8d13d 100644 --- a/boards/xtensa/esp32/esp32-sparrow-kit/src/esp32_buttons.c +++ b/boards/xtensa/esp32/esp32-sparrow-kit/src/esp32_buttons.c @@ -37,7 +37,7 @@ #include #include -#include "esp32_gpio.h" +#include "espressif/esp_gpio.h" #include "esp32-sparrow-kit.h" @@ -58,7 +58,7 @@ uint32_t board_button_initialize(void) { - esp32_configgpio(BUTTON_BOOT, INPUT_FUNCTION_3 | PULLUP); + esp_configgpio(BUTTON_BOOT, INPUT_FUNCTION_3 | PULLUP | CHANGE); return 1; } @@ -79,13 +79,13 @@ uint32_t board_buttons(void) int i = 0; int n = 0; - bool b0 = esp32_gpioread(BUTTON_BOOT); + bool b0 = esp_gpioread(BUTTON_BOOT); for (i = 0; i < 10; i++) { up_mdelay(1); /* TODO */ - bool b1 = esp32_gpioread(BUTTON_BOOT); + bool b1 = esp_gpioread(BUTTON_BOOT); if (b0 == b1) { @@ -131,38 +131,6 @@ uint32_t board_buttons(void) #ifdef CONFIG_ARCH_IRQBUTTONS int board_button_irq(int id, xcpt_t irqhandler, void *arg) { - int ret; - DEBUGASSERT(id == 0); - - int irq = ESP32_PIN2IRQ(BUTTON_BOOT); - - if (NULL != irqhandler) - { - /* Make sure the interrupt is disabled */ - - esp32_gpioirqdisable(irq); - - ret = irq_attach(irq, irqhandler, arg); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: irq_attach() failed: %d\n", ret); - return ret; - } - - gpioinfo("Attach %p\n", irqhandler); - - gpioinfo("Enabling the interrupt\n"); - - /* Configure the interrupt for rising and falling edges */ - - esp32_gpioirqenable(irq, CHANGE); - } - else - { - gpioinfo("Disable the interrupt\n"); - esp32_gpioirqdisable(irq); - } - - return OK; + return esp_gpio_irq(BUTTON_BOOT, irqhandler, arg); } #endif diff --git a/boards/xtensa/esp32/esp32-sparrow-kit/src/esp32_gpio.c b/boards/xtensa/esp32/esp32-sparrow-kit/src/esp32_gpio.c index dbf255ac94f28..1417d97aca6e1 100644 --- a/boards/xtensa/esp32/esp32-sparrow-kit/src/esp32_gpio.c +++ b/boards/xtensa/esp32/esp32-sparrow-kit/src/esp32_gpio.c @@ -37,7 +37,7 @@ #include #include "esp32-sparrow-kit.h" -#include "esp32_gpio.h" +#include "espressif/esp_gpio.h" #include "hardware/esp32_gpio_sigmap.h" #if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF) @@ -46,7 +46,7 @@ * Pre-processor Definitions ****************************************************************************/ -#if !defined(CONFIG_ESP32_GPIO_IRQ) && BOARD_NGPIOINT > 0 +#if !defined(CONFIG_ESPRESSIF_GPIO_IRQ) && BOARD_NGPIOINT > 0 # error "NGPIOINT is > 0 and GPIO interrupts aren't enabled" #endif @@ -182,7 +182,7 @@ static int gpout_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(esp32gpio->id < BOARD_NGPIOOUT); gpioinfo("Reading...\n"); - *value = esp32_gpioread(g_gpiooutputs[esp32gpio->id]); + *value = esp_gpioread(g_gpiooutputs[esp32gpio->id]); return OK; } @@ -198,7 +198,7 @@ static int gpout_write(struct gpio_dev_s *dev, bool value) DEBUGASSERT(esp32gpio->id < BOARD_NGPIOOUT); gpioinfo("Writing %d\n", (int)value); - esp32_gpiowrite(g_gpiooutputs[esp32gpio->id], value); + esp_gpiowrite(g_gpiooutputs[esp32gpio->id], value); return OK; } #endif @@ -216,7 +216,7 @@ static int gpin_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(esp32gpio->id < BOARD_NGPIOIN); gpioinfo("Reading... pin %" PRIu32 "\n", g_gpioinputs[esp32gpio->id]); - *value = esp32_gpioread(g_gpioinputs[esp32gpio->id]); + *value = esp_gpioread(g_gpioinputs[esp32gpio->id]); return OK; } #endif @@ -252,7 +252,7 @@ static int gpint_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(esp32gpint->esp32gpio.id < BOARD_NGPIOINT); gpioinfo("Reading int pin...\n"); - *value = esp32_gpioread(g_gpiointinputs[esp32gpint->esp32gpio.id]); + *value = esp_gpioread(g_gpiointinputs[esp32gpint->esp32gpio.id]); return OK; } @@ -265,23 +265,26 @@ static int gpint_attach(struct gpio_dev_s *dev, { struct esp32gpint_dev_s *esp32gpint = (struct esp32gpint_dev_s *)dev; - int irq = ESP32_PIN2IRQ(g_gpiointinputs[esp32gpint->esp32gpio.id]); int ret; gpioinfo("Attaching the callback\n"); /* Make sure the interrupt is disabled */ - esp32_gpioirqdisable(irq); - ret = irq_attach(irq, - esp32gpio_interrupt, - &g_gpint[esp32gpint->esp32gpio.id]); + esp_gpioirqdisable(g_gpiointinputs[esp32gpint->esp32gpio.id]); + + ret = esp_gpio_irq(g_gpiointinputs[esp32gpint->esp32gpio.id], + esp32gpio_interrupt, + &g_gpint[esp32gpint->esp32gpio.id]); if (ret < 0) { - syslog(LOG_ERR, "ERROR: gpint_attach() failed: %d\n", ret); return ret; } + /* Make sure the interrupt is disabled */ + + esp_gpioirqdisable(g_gpiointinputs[esp32gpint->esp32gpio.id]); + gpioinfo("Attach %p\n", callback); esp32gpint->callback = callback; return OK; @@ -295,7 +298,6 @@ static int gpint_enable(struct gpio_dev_s *dev, bool enable) { struct esp32gpint_dev_s *esp32gpint = (struct esp32gpint_dev_s *)dev; - int irq = ESP32_PIN2IRQ(g_gpiointinputs[esp32gpint->esp32gpio.id]); if (enable) { @@ -305,13 +307,13 @@ static int gpint_enable(struct gpio_dev_s *dev, bool enable) /* Configure the interrupt for rising edge */ - esp32_gpioirqenable(irq, RISING); + esp_gpioirqenable(g_gpiointinputs[esp32gpint->esp32gpio.id]); } } else { gpioinfo("Disable the interrupt\n"); - esp32_gpioirqdisable(irq); + esp_gpioirqdisable(g_gpiointinputs[esp32gpint->esp32gpio.id]); } return OK; @@ -343,10 +345,9 @@ int esp32_gpio_init(void) /* Configure the pins that will be used as output */ - esp32_gpio_matrix_out(g_gpiooutputs[i], SIG_GPIO_OUT_IDX, 0, 0); - esp32_configgpio(g_gpiooutputs[i], OUTPUT_FUNCTION_3 | - INPUT_FUNCTION_3); - esp32_gpiowrite(g_gpiooutputs[i], 0); + esp_gpio_matrix_out(g_gpiooutputs[i], SIG_GPIO_OUT_IDX, 0, 0); + esp_configgpio(g_gpiooutputs[i], OUTPUT_FUNCTION_3 | INPUT_FUNCTION_3); + esp_gpiowrite(g_gpiooutputs[i], 0); pincount++; } @@ -364,7 +365,7 @@ int esp32_gpio_init(void) /* Configure the pins that will be used as INPUT */ - esp32_configgpio(g_gpioinputs[i], INPUT_FUNCTION_3); + esp_configgpio(g_gpioinputs[i], INPUT_FUNCTION_3 | PULLDOWN); pincount++; } @@ -382,7 +383,8 @@ int esp32_gpio_init(void) /* Configure the pins that will be used as interrupt input */ - esp32_configgpio(g_gpiointinputs[i], INPUT_FUNCTION_3 | PULLDOWN); + esp_configgpio(g_gpiointinputs[i], + INPUT_FUNCTION_3 | PULLUP | FALLING); pincount++; } diff --git a/boards/xtensa/esp32/esp32-sparrow-kit/src/esp32_userleds.c b/boards/xtensa/esp32/esp32-sparrow-kit/src/esp32_userleds.c index 9402a19eb4a33..c04bff80ac697 100644 --- a/boards/xtensa/esp32/esp32-sparrow-kit/src/esp32_userleds.c +++ b/boards/xtensa/esp32/esp32-sparrow-kit/src/esp32_userleds.c @@ -33,7 +33,7 @@ #include #include -#include "esp32_gpio.h" +#include "espressif/esp_gpio.h" #include "esp32-sparrow-kit.h" /**************************************************************************** @@ -63,7 +63,7 @@ uint32_t board_userled_initialize(void) for (i = 0; i < BOARD_NLEDS; i++) { - esp32_configgpio(g_ledcfg[i], OUTPUT); + esp_configgpio(g_ledcfg[i], OUTPUT); } return BOARD_NLEDS; @@ -77,7 +77,7 @@ void board_userled(int led, bool ledon) { if ((unsigned)led < BOARD_NLEDS) { - esp32_gpiowrite(g_ledcfg[led], ledon); + esp_gpiowrite(g_ledcfg[led], ledon); } } @@ -91,6 +91,6 @@ void board_userled_all(uint32_t ledset) for (i = 0; i < BOARD_NLEDS; i++) { - esp32_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); + esp_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); } } diff --git a/boards/xtensa/esp32/esp32-wrover-kit/configs/autopm/defconfig b/boards/xtensa/esp32/esp32-wrover-kit/configs/autopm/defconfig index 123fddff86dfa..c60f8540fe994 100644 --- a/boards/xtensa/esp32/esp32-wrover-kit/configs/autopm/defconfig +++ b/boards/xtensa/esp32/esp32-wrover-kit/configs/autopm/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_BOARD_ESP32_WROVERKIT=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/esp32-wrover-kit/configs/bmp180/defconfig b/boards/xtensa/esp32/esp32-wrover-kit/configs/bmp180/defconfig index a2de95673adbd..023094565696a 100644 --- a/boards/xtensa/esp32/esp32-wrover-kit/configs/bmp180/defconfig +++ b/boards/xtensa/esp32/esp32-wrover-kit/configs/bmp180/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32_WROVERKIT=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/esp32-wrover-kit/configs/buttons/defconfig b/boards/xtensa/esp32/esp32-wrover-kit/configs/buttons/defconfig index 8c3ec22f3cf3c..1d869095a59a8 100644 --- a/boards/xtensa/esp32/esp32-wrover-kit/configs/buttons/defconfig +++ b/boards/xtensa/esp32/esp32-wrover-kit/configs/buttons/defconfig @@ -17,12 +17,15 @@ CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y -CONFIG_ESP32_GPIO_IRQ=y CONFIG_ESP32_UART0=y +CONFIG_ESPRESSIF_GPIO_IRQ=y CONFIG_EXAMPLES_BUTTONS=y CONFIG_FS_PROCFS=y CONFIG_HAVE_CXX=y diff --git a/boards/xtensa/esp32/esp32-wrover-kit/configs/gpio/defconfig b/boards/xtensa/esp32/esp32-wrover-kit/configs/gpio/defconfig index fd09e45e030d5..a8aa54f7a93e5 100644 --- a/boards/xtensa/esp32/esp32-wrover-kit/configs/gpio/defconfig +++ b/boards/xtensa/esp32/esp32-wrover-kit/configs/gpio/defconfig @@ -15,13 +15,16 @@ CONFIG_ARCH_BOARD_ESP32_WROVERKIT=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y CONFIG_DEV_GPIO=y -CONFIG_ESP32_GPIO_IRQ=y CONFIG_ESP32_UART0=y +CONFIG_ESPRESSIF_GPIO_IRQ=y CONFIG_EXAMPLES_GPIO=y CONFIG_FS_PROCFS=y CONFIG_HAVE_CXX=y diff --git a/boards/xtensa/esp32/esp32-wrover-kit/configs/lcd1602/defconfig b/boards/xtensa/esp32/esp32-wrover-kit/configs/lcd1602/defconfig index be605254d9c6b..5f6d5e7544336 100644 --- a/boards/xtensa/esp32/esp32-wrover-kit/configs/lcd1602/defconfig +++ b/boards/xtensa/esp32/esp32-wrover-kit/configs/lcd1602/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32_WROVERKIT=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/esp32-wrover-kit/configs/leds/defconfig b/boards/xtensa/esp32/esp32-wrover-kit/configs/leds/defconfig index df40c499f6eaa..7d656058f5066 100644 --- a/boards/xtensa/esp32/esp32-wrover-kit/configs/leds/defconfig +++ b/boards/xtensa/esp32/esp32-wrover-kit/configs/leds/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32_WROVERKIT=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/esp32-wrover-kit/configs/lua/defconfig b/boards/xtensa/esp32/esp32-wrover-kit/configs/lua/defconfig index 2bd008f476705..ec37c1bea7119 100644 --- a/boards/xtensa/esp32/esp32-wrover-kit/configs/lua/defconfig +++ b/boards/xtensa/esp32/esp32-wrover-kit/configs/lua/defconfig @@ -22,6 +22,9 @@ CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/esp32-wrover-kit/configs/lvgl/defconfig b/boards/xtensa/esp32/esp32-wrover-kit/configs/lvgl/defconfig index 3681885522542..f874799e432e0 100644 --- a/boards/xtensa/esp32/esp32-wrover-kit/configs/lvgl/defconfig +++ b/boards/xtensa/esp32/esp32-wrover-kit/configs/lvgl/defconfig @@ -18,6 +18,9 @@ CONFIG_ARCH_BOARD_ESP32_WROVERKIT=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/esp32-wrover-kit/configs/nsh/defconfig b/boards/xtensa/esp32/esp32-wrover-kit/configs/nsh/defconfig index 3d1977c956e48..af7ef9bd23e7a 100644 --- a/boards/xtensa/esp32/esp32-wrover-kit/configs/nsh/defconfig +++ b/boards/xtensa/esp32/esp32-wrover-kit/configs/nsh/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32_WROVERKIT=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/esp32-wrover-kit/configs/nx/defconfig b/boards/xtensa/esp32/esp32-wrover-kit/configs/nx/defconfig index d0cc80b28252c..8a1b15ad1bc8a 100644 --- a/boards/xtensa/esp32/esp32-wrover-kit/configs/nx/defconfig +++ b/boards/xtensa/esp32/esp32-wrover-kit/configs/nx/defconfig @@ -19,6 +19,9 @@ CONFIG_ARCH_BOARD_ESP32_WROVERKIT=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/esp32-wrover-kit/configs/oneshot/defconfig b/boards/xtensa/esp32/esp32-wrover-kit/configs/oneshot/defconfig index 015a64588bb80..31ab3ac413b7f 100644 --- a/boards/xtensa/esp32/esp32-wrover-kit/configs/oneshot/defconfig +++ b/boards/xtensa/esp32/esp32-wrover-kit/configs/oneshot/defconfig @@ -7,7 +7,6 @@ # # CONFIG_NSH_ARGCAT is not set # CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ALARM_ARCH=y CONFIG_ARCH="xtensa" CONFIG_ARCH_BOARD="esp32-wrover-kit" CONFIG_ARCH_BOARD_COMMON=y @@ -15,6 +14,9 @@ CONFIG_ARCH_BOARD_ESP32_WROVERKIT=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 @@ -53,5 +55,4 @@ CONFIG_START_YEAR=2011 CONFIG_SYSLOG_BUFFER=y CONFIG_SYSTEM_NSH=y CONFIG_TIMER=y -CONFIG_TIMER_ARCH=y CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/xtensa/esp32/esp32-wrover-kit/configs/rtc/defconfig b/boards/xtensa/esp32/esp32-wrover-kit/configs/rtc/defconfig index 23c007572f04c..553825a6bd251 100644 --- a/boards/xtensa/esp32/esp32-wrover-kit/configs/rtc/defconfig +++ b/boards/xtensa/esp32/esp32-wrover-kit/configs/rtc/defconfig @@ -15,11 +15,13 @@ CONFIG_ARCH_BOARD_ESP32_WROVERKIT=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y -CONFIG_ESP32_RT_TIMER=y CONFIG_ESP32_UART0=y CONFIG_EXAMPLES_ALARM=y CONFIG_FS_PROCFS=y diff --git a/boards/xtensa/esp32/esp32-wrover-kit/configs/sdmmc_spi/defconfig b/boards/xtensa/esp32/esp32-wrover-kit/configs/sdmmc_spi/defconfig index 959d03808656b..05fcbb3fc3026 100644 --- a/boards/xtensa/esp32/esp32-wrover-kit/configs/sdmmc_spi/defconfig +++ b/boards/xtensa/esp32/esp32-wrover-kit/configs/sdmmc_spi/defconfig @@ -20,6 +20,9 @@ CONFIG_ARCH_BOARD_ESP32_WROVERKIT=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/esp32-wrover-kit/configs/wifi/defconfig b/boards/xtensa/esp32/esp32-wrover-kit/configs/wifi/defconfig index 015d856ea6aae..c0619d0bb5655 100644 --- a/boards/xtensa/esp32/esp32-wrover-kit/configs/wifi/defconfig +++ b/boards/xtensa/esp32/esp32-wrover-kit/configs/wifi/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_BOARD_ESP32_WROVERKIT=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/esp32-wrover-kit/src/esp32_autoleds.c b/boards/xtensa/esp32/esp32-wrover-kit/src/esp32_autoleds.c index f7812642776e7..aae46bbf35b67 100644 --- a/boards/xtensa/esp32/esp32-wrover-kit/src/esp32_autoleds.c +++ b/boards/xtensa/esp32/esp32-wrover-kit/src/esp32_autoleds.c @@ -33,7 +33,7 @@ #include #include -#include "esp32_gpio.h" +#include "espressif/esp_gpio.h" #include "esp32-wrover-kit.h" #ifdef CONFIG_ARCH_LEDS @@ -82,17 +82,17 @@ static inline void led_clrbits(unsigned int clrbits) { if ((clrbits & BOARD_LED1_BIT) != 0) { - esp32_gpiowrite(GPIO_LED1, false); + esp_gpiowrite(GPIO_LED1, false); } if ((clrbits & BOARD_LED2_BIT) != 0) { - esp32_gpiowrite(GPIO_LED2, false); + esp_gpiowrite(GPIO_LED2, false); } if ((clrbits & BOARD_LED3_BIT) != 0) { - esp32_gpiowrite(GPIO_LED3, false); + esp_gpiowrite(GPIO_LED3, false); } } @@ -100,17 +100,17 @@ static inline void led_setbits(unsigned int setbits) { if ((setbits & BOARD_LED1_BIT) != 0) { - esp32_gpiowrite(GPIO_LED1, true); + esp_gpiowrite(GPIO_LED1, true); } if ((setbits & BOARD_LED2_BIT) != 0) { - esp32_gpiowrite(GPIO_LED2, true); + esp_gpiowrite(GPIO_LED2, true); } if ((setbits & BOARD_LED3_BIT) != 0) { - esp32_gpiowrite(GPIO_LED3, true); + esp_gpiowrite(GPIO_LED3, true); } } @@ -126,9 +126,9 @@ void board_autoled_initialize(void) { /* Configure LED1-4 GPIOs for output */ - esp32_configgpio(GPIO_LED1, OUTPUT); - esp32_configgpio(GPIO_LED2, OUTPUT); - esp32_configgpio(GPIO_LED3, OUTPUT); + esp_configgpio(GPIO_LED1, OUTPUT); + esp_configgpio(GPIO_LED2, OUTPUT); + esp_configgpio(GPIO_LED3, OUTPUT); } /**************************************************************************** @@ -141,13 +141,13 @@ void board_autoled_on(int led) switch (led) { case LED_CPU0: - esp32_gpiowrite(GPIO_LED1, true); + esp_gpiowrite(GPIO_LED1, true); break; case LED_CPU1: - esp32_gpiowrite(GPIO_LED2, true); + esp_gpiowrite(GPIO_LED2, true); break; case LED_HEAPALLOCATE: - esp32_gpiowrite(GPIO_LED3, true); + esp_gpiowrite(GPIO_LED3, true); break; default: break; @@ -168,13 +168,13 @@ void board_autoled_off(int led) switch (led) { case LED_CPU0: - esp32_gpiowrite(GPIO_LED1, false); + esp_gpiowrite(GPIO_LED1, false); break; case LED_CPU1: - esp32_gpiowrite(GPIO_LED2, false); + esp_gpiowrite(GPIO_LED2, false); break; case LED_HEAPALLOCATE: - esp32_gpiowrite(GPIO_LED3, false); + esp_gpiowrite(GPIO_LED3, false); break; default: break; diff --git a/boards/xtensa/esp32/esp32-wrover-kit/src/esp32_bringup.c b/boards/xtensa/esp32/esp32-wrover-kit/src/esp32_bringup.c index 53ff941e2aa52..e07f5686e0d2a 100644 --- a/boards/xtensa/esp32/esp32-wrover-kit/src/esp32_bringup.c +++ b/boards/xtensa/esp32/esp32-wrover-kit/src/esp32_bringup.c @@ -40,6 +40,8 @@ #include #include "esp32_partition.h" +#include "espressif/esp_gpio.h" +#include "esp32_start.h" #include @@ -87,17 +89,17 @@ # include #endif -#ifdef CONFIG_ESP32_RT_TIMER -# include "esp32_rt_timer.h" -#endif - #ifdef CONFIG_LCD_DEV # include # include #endif #ifdef CONFIG_RTC_DRIVER -# include "esp32_rtc_lowerhalf.h" +# include "espressif/esp_rtc.h" +#endif + +#ifdef CONFIG_ESPRESSIF_HR_TIMER +# include "espressif/esp_hr_timer.h" #endif #ifdef CONFIG_LCD_BACKPACK @@ -201,14 +203,6 @@ int esp32_bringup(void) } #endif -#ifdef CONFIG_ESP32_RT_TIMER - ret = esp32_rt_timer_init(); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize RT timer: %d\n", ret); - } -#endif - #ifdef CONFIG_ESPRESSIF_BLE ret = esp32_ble_initialize(); if (ret) @@ -226,13 +220,21 @@ int esp32_bringup(void) } #endif +#ifdef CONFIG_ESPRESSIF_HR_TIMER + ret = esp_hr_timer_init(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: esp_hr_timer_init() failed: %d\n", ret); + } +#endif + /* First, register the timer drivers and let timer 1 for oneshot * if it is enabled. */ #ifdef CONFIG_TIMER -#if defined(CONFIG_ESP32_TIMER0) && !defined(CONFIG_ESP32_RT_TIMER) +#if defined(CONFIG_ESP32_TIMER0) && !defined(CONFIG_ESPRESSIF_HR_TIMER) ret = esp32_timer_initialize("/dev/timer0", TIMER0); if (ret < 0) { @@ -380,7 +382,7 @@ int esp32_bringup(void) #ifdef CONFIG_RTC_DRIVER /* Instantiate the ESP32 RTC driver */ - ret = esp32_rtc_driverinit(); + ret = esp_rtc_driverinit(); if (ret < 0) { syslog(LOG_ERR, diff --git a/boards/xtensa/esp32/esp32-wrover-kit/src/esp32_buttons.c b/boards/xtensa/esp32/esp32-wrover-kit/src/esp32_buttons.c index 6de3eef25713b..b2f2daf2efc69 100644 --- a/boards/xtensa/esp32/esp32-wrover-kit/src/esp32_buttons.c +++ b/boards/xtensa/esp32/esp32-wrover-kit/src/esp32_buttons.c @@ -37,7 +37,7 @@ #include #include -#include "esp32_gpio.h" +#include "espressif/esp_gpio.h" #include "esp32-wrover-kit.h" @@ -58,7 +58,7 @@ uint32_t board_button_initialize(void) { - esp32_configgpio(BUTTON_BOOT, INPUT_FUNCTION_3 | PULLUP); + esp_configgpio(BUTTON_BOOT, INPUT_FUNCTION_3 | PULLUP | CHANGE); return 1; } @@ -79,13 +79,13 @@ uint32_t board_buttons(void) int i = 0; int n = 0; - bool b0 = esp32_gpioread(BUTTON_BOOT); + bool b0 = esp_gpioread(BUTTON_BOOT); for (i = 0; i < 10; i++) { up_mdelay(1); /* TODO */ - bool b1 = esp32_gpioread(BUTTON_BOOT); + bool b1 = esp_gpioread(BUTTON_BOOT); if (b0 == b1) { @@ -131,38 +131,6 @@ uint32_t board_buttons(void) #ifdef CONFIG_ARCH_IRQBUTTONS int board_button_irq(int id, xcpt_t irqhandler, void *arg) { - int ret; - DEBUGASSERT(id == 0); - - int irq = ESP32_PIN2IRQ(BUTTON_BOOT); - - if (NULL != irqhandler) - { - /* Make sure the interrupt is disabled */ - - esp32_gpioirqdisable(irq); - - ret = irq_attach(irq, irqhandler, arg); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: irq_attach() failed: %d\n", ret); - return ret; - } - - gpioinfo("Attach %p\n", irqhandler); - - gpioinfo("Enabling the interrupt\n"); - - /* Configure the interrupt for rising and falling edges */ - - esp32_gpioirqenable(irq, CHANGE); - } - else - { - gpioinfo("Disable the interrupt\n"); - esp32_gpioirqdisable(irq); - } - - return OK; + return esp_gpio_irq(BUTTON_BOOT, irqhandler, arg); } #endif diff --git a/boards/xtensa/esp32/esp32-wrover-kit/src/esp32_gpio.c b/boards/xtensa/esp32/esp32-wrover-kit/src/esp32_gpio.c index 05e621c8f9631..826451ab0e22c 100644 --- a/boards/xtensa/esp32/esp32-wrover-kit/src/esp32_gpio.c +++ b/boards/xtensa/esp32/esp32-wrover-kit/src/esp32_gpio.c @@ -37,7 +37,7 @@ #include #include "esp32-wrover-kit.h" -#include "esp32_gpio.h" +#include "espressif/esp_gpio.h" #include "hardware/esp32_gpio_sigmap.h" #if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF) @@ -46,7 +46,7 @@ * Pre-processor Definitions ****************************************************************************/ -#if !defined(CONFIG_ESP32_GPIO_IRQ) && BOARD_NGPIOINT > 0 +#if !defined(CONFIG_ESPRESSIF_GPIO_IRQ) && BOARD_NGPIOINT > 0 # error "NGPIOINT is > 0 and GPIO interrupts aren't enabled" #endif @@ -182,7 +182,7 @@ static int gpout_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(esp32gpio->id < BOARD_NGPIOOUT); gpioinfo("Reading...\n"); - *value = esp32_gpioread(g_gpiooutputs[esp32gpio->id]); + *value = esp_gpioread(g_gpiooutputs[esp32gpio->id]); return OK; } @@ -198,7 +198,7 @@ static int gpout_write(struct gpio_dev_s *dev, bool value) DEBUGASSERT(esp32gpio->id < BOARD_NGPIOOUT); gpioinfo("Writing %d\n", (int)value); - esp32_gpiowrite(g_gpiooutputs[esp32gpio->id], value); + esp_gpiowrite(g_gpiooutputs[esp32gpio->id], value); return OK; } #endif @@ -216,7 +216,7 @@ static int gpin_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(esp32gpio->id < BOARD_NGPIOIN); gpioinfo("Reading... pin %" PRIu32 "\n", g_gpioinputs[esp32gpio->id]); - *value = esp32_gpioread(g_gpioinputs[esp32gpio->id]); + *value = esp_gpioread(g_gpioinputs[esp32gpio->id]); return OK; } #endif @@ -252,7 +252,7 @@ static int gpint_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(esp32gpint->esp32gpio.id < BOARD_NGPIOINT); gpioinfo("Reading int pin...\n"); - *value = esp32_gpioread(g_gpiointinputs[esp32gpint->esp32gpio.id]); + *value = esp_gpioread(g_gpiointinputs[esp32gpint->esp32gpio.id]); return OK; } @@ -265,23 +265,26 @@ static int gpint_attach(struct gpio_dev_s *dev, { struct esp32gpint_dev_s *esp32gpint = (struct esp32gpint_dev_s *)dev; - int irq = ESP32_PIN2IRQ(g_gpiointinputs[esp32gpint->esp32gpio.id]); int ret; gpioinfo("Attaching the callback\n"); /* Make sure the interrupt is disabled */ - esp32_gpioirqdisable(irq); - ret = irq_attach(irq, - esp32gpio_interrupt, - &g_gpint[esp32gpint->esp32gpio.id]); + esp_gpioirqdisable(g_gpiointinputs[esp32gpint->esp32gpio.id]); + + ret = esp_gpio_irq(g_gpiointinputs[esp32gpint->esp32gpio.id], + esp32gpio_interrupt, + &g_gpint[esp32gpint->esp32gpio.id]); if (ret < 0) { - syslog(LOG_ERR, "ERROR: gpint_attach() failed: %d\n", ret); return ret; } + /* Make sure the interrupt is disabled */ + + esp_gpioirqdisable(g_gpiointinputs[esp32gpint->esp32gpio.id]); + gpioinfo("Attach %p\n", callback); esp32gpint->callback = callback; return OK; @@ -295,7 +298,6 @@ static int gpint_enable(struct gpio_dev_s *dev, bool enable) { struct esp32gpint_dev_s *esp32gpint = (struct esp32gpint_dev_s *)dev; - int irq = ESP32_PIN2IRQ(g_gpiointinputs[esp32gpint->esp32gpio.id]); if (enable) { @@ -305,13 +307,13 @@ static int gpint_enable(struct gpio_dev_s *dev, bool enable) /* Configure the interrupt for rising edge */ - esp32_gpioirqenable(irq, RISING); + esp_gpioirqenable(g_gpiointinputs[esp32gpint->esp32gpio.id]); } } else { gpioinfo("Disable the interrupt\n"); - esp32_gpioirqdisable(irq); + esp_gpioirqdisable(g_gpiointinputs[esp32gpint->esp32gpio.id]); } return OK; @@ -343,10 +345,9 @@ int esp32_gpio_init(void) /* Configure the pins that will be used as output */ - esp32_gpio_matrix_out(g_gpiooutputs[i], SIG_GPIO_OUT_IDX, 0, 0); - esp32_configgpio(g_gpiooutputs[i], OUTPUT_FUNCTION_3 | - INPUT_FUNCTION_3); - esp32_gpiowrite(g_gpiooutputs[i], 0); + esp_gpio_matrix_out(g_gpiooutputs[i], SIG_GPIO_OUT_IDX, 0, 0); + esp_configgpio(g_gpiooutputs[i], OUTPUT_FUNCTION_3 | INPUT_FUNCTION_3); + esp_gpiowrite(g_gpiooutputs[i], 0); pincount++; } @@ -364,7 +365,7 @@ int esp32_gpio_init(void) /* Configure the pins that will be used as INPUT */ - esp32_configgpio(g_gpioinputs[i], INPUT_FUNCTION_3); + esp_configgpio(g_gpioinputs[i], INPUT_FUNCTION_3 | PULLDOWN); pincount++; } @@ -382,7 +383,8 @@ int esp32_gpio_init(void) /* Configure the pins that will be used as interrupt input */ - esp32_configgpio(g_gpiointinputs[i], INPUT_FUNCTION_3 | PULLDOWN); + esp_configgpio(g_gpiointinputs[i], + INPUT_FUNCTION_3 | PULLUP | FALLING); pincount++; } diff --git a/boards/xtensa/esp32/esp32-wrover-kit/src/esp32_userleds.c b/boards/xtensa/esp32/esp32-wrover-kit/src/esp32_userleds.c index bd060a38c9bcf..b6bebdbace895 100644 --- a/boards/xtensa/esp32/esp32-wrover-kit/src/esp32_userleds.c +++ b/boards/xtensa/esp32/esp32-wrover-kit/src/esp32_userleds.c @@ -33,7 +33,7 @@ #include #include -#include "esp32_gpio.h" +#include "espressif/esp_gpio.h" #include "esp32-wrover-kit.h" /**************************************************************************** @@ -84,7 +84,7 @@ uint32_t board_userled_initialize(void) for (i = 0; i < BOARD_NLEDS; i++) { - esp32_configgpio(g_ledcfg[i], OUTPUT); + esp_configgpio(g_ledcfg[i], OUTPUT); } return BOARD_NLEDS; @@ -98,7 +98,7 @@ void board_userled(int led, bool ledon) { if ((unsigned)led < BOARD_NLEDS) { - esp32_gpiowrite(g_ledcfg[led], ledon); + esp_gpiowrite(g_ledcfg[led], ledon); } } @@ -112,7 +112,6 @@ void board_userled_all(uint32_t ledset) for (i = 0; i < BOARD_NLEDS; i++) { - esp32_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); + esp_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); } } - diff --git a/boards/xtensa/esp32/heltec_wifi_lora32/configs/nsh/defconfig b/boards/xtensa/esp32/heltec_wifi_lora32/configs/nsh/defconfig index 9f1109ed0e235..89b40d74d7f6c 100644 --- a/boards/xtensa/esp32/heltec_wifi_lora32/configs/nsh/defconfig +++ b/boards/xtensa/esp32/heltec_wifi_lora32/configs/nsh/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_HELTEC_WIFI_LORA32=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/heltec_wifi_lora32/configs/sx1276/defconfig b/boards/xtensa/esp32/heltec_wifi_lora32/configs/sx1276/defconfig index 160a52951afa9..dae1d22ad16fc 100644 --- a/boards/xtensa/esp32/heltec_wifi_lora32/configs/sx1276/defconfig +++ b/boards/xtensa/esp32/heltec_wifi_lora32/configs/sx1276/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_BOARD_HELTEC_WIFI_LORA32=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/heltec_wifi_lora32/src/esp32_bringup.c b/boards/xtensa/esp32/heltec_wifi_lora32/src/esp32_bringup.c index b4008c08d04d8..5dc1e6cd70518 100644 --- a/boards/xtensa/esp32/heltec_wifi_lora32/src/esp32_bringup.c +++ b/boards/xtensa/esp32/heltec_wifi_lora32/src/esp32_bringup.c @@ -36,6 +36,12 @@ #include #include +#include "esp32_start.h" + +#ifdef CONFIG_ESPRESSIF_HR_TIMER +# include "espressif/esp_hr_timer.h" +#endif + #include "heltec_wifi_lora32.h" /**************************************************************************** @@ -91,6 +97,14 @@ int esp32_bringup(void) } #endif /* CONFIG_LPWAN_SX127X */ +#ifdef CONFIG_ESPRESSIF_HR_TIMER + ret = esp_hr_timer_init(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: esp_hr_timer_init() failed: %d\n", ret); + } +#endif + /* If we got here then perhaps not all initialization was successful, but * at least enough succeeded to bring-up NSH with perhaps reduced * capabilities. diff --git a/boards/xtensa/esp32/heltec_wifi_lora32/src/esp32_sx127x.c b/boards/xtensa/esp32/heltec_wifi_lora32/src/esp32_sx127x.c index b481c73963419..8eeb5991006e8 100644 --- a/boards/xtensa/esp32/heltec_wifi_lora32/src/esp32_sx127x.c +++ b/boards/xtensa/esp32/heltec_wifi_lora32/src/esp32_sx127x.c @@ -37,7 +37,7 @@ #include #include -#include "esp32_gpio.h" +#include "espressif/esp_gpio.h" #include "esp32_spi.h" #include "hardware/esp32_gpio_sigmap.h" @@ -120,8 +120,8 @@ static void sx127x_chip_reset(void) /* Configure reset as output */ - esp32_gpio_matrix_out(GPIO_SX127X_RESET, SIG_GPIO_OUT_IDX, 0, 0); - esp32_configgpio(GPIO_SX127X_RESET, OUTPUT_FUNCTION_3 | INPUT_FUNCTION_3); + esp_gpio_matrix_out(GPIO_SX127X_RESET, SIG_GPIO_OUT_IDX, 0, 0); + esp_configgpio(GPIO_SX127X_RESET, OUTPUT_FUNCTION_3 | INPUT_FUNCTION_3); /* Set pin to zero */ @@ -203,7 +203,7 @@ int esp32_lpwaninitialize(void) /* Setup DIO0 */ - esp32_configgpio(GPIO_SX127X_DIO0, INPUT_FUNCTION_3 | PULLDOWN); + esp_configgpio(GPIO_SX127X_DIO0, INPUT_FUNCTION_3 | PULLDOWN); /* Init SPI bus */ diff --git a/boards/xtensa/esp32/lilygo_tbeam_lora_gps/configs/gps/defconfig b/boards/xtensa/esp32/lilygo_tbeam_lora_gps/configs/gps/defconfig index d53b8202c94e1..509bfe5b94c55 100644 --- a/boards/xtensa/esp32/lilygo_tbeam_lora_gps/configs/gps/defconfig +++ b/boards/xtensa/esp32/lilygo_tbeam_lora_gps/configs/gps/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_BOARD_LILYGO_TBEAM_LORA_GPS=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROOM32=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/lilygo_tbeam_lora_gps/configs/nsh/defconfig b/boards/xtensa/esp32/lilygo_tbeam_lora_gps/configs/nsh/defconfig index e6871a050c0d6..7e275f3d7a25a 100644 --- a/boards/xtensa/esp32/lilygo_tbeam_lora_gps/configs/nsh/defconfig +++ b/boards/xtensa/esp32/lilygo_tbeam_lora_gps/configs/nsh/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_BOARD_LILYGO_TBEAM_LORA_GPS=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROOM32=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/lilygo_tbeam_lora_gps/configs/sx127x/defconfig b/boards/xtensa/esp32/lilygo_tbeam_lora_gps/configs/sx127x/defconfig index c00292b7f2736..ac74a03e6a7b3 100644 --- a/boards/xtensa/esp32/lilygo_tbeam_lora_gps/configs/sx127x/defconfig +++ b/boards/xtensa/esp32/lilygo_tbeam_lora_gps/configs/sx127x/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_BOARD_LILYGO_TBEAM_LORA_GPS=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROOM32=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/lilygo_tbeam_lora_gps/src/esp32_bringup.c b/boards/xtensa/esp32/lilygo_tbeam_lora_gps/src/esp32_bringup.c index 44393e5b65a42..d250d9febf603 100644 --- a/boards/xtensa/esp32/lilygo_tbeam_lora_gps/src/esp32_bringup.c +++ b/boards/xtensa/esp32/lilygo_tbeam_lora_gps/src/esp32_bringup.c @@ -46,6 +46,8 @@ #include "espressif/esp_efuse.h" #endif #include "esp32_partition.h" +#include "espressif/esp_gpio.h" +#include "esp32_start.h" #ifdef CONFIG_USERLED # include @@ -95,16 +97,16 @@ # include "esp32_aes.h" #endif -#ifdef CONFIG_ESP32_RT_TIMER -# include "esp32_rt_timer.h" -#endif - #ifdef CONFIG_INPUT_BUTTONS # include #endif #ifdef CONFIG_RTC_DRIVER -# include "esp32_rtc_lowerhalf.h" +# include "espressif/esp_rtc.h" +#endif + +#ifdef CONFIG_ESPRESSIF_HR_TIMER +# include "espressif/esp_hr_timer.h" #endif #ifdef CONFIG_SPI_DRIVER @@ -192,14 +194,6 @@ int esp32_bringup(void) } #endif -#ifdef CONFIG_ESP32_RT_TIMER - ret = esp32_rt_timer_init(); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize RT timer: %d\n", ret); - } -#endif - #ifdef CONFIG_LPWAN_SX127X ret = esp32_lpwaninitialize(); if (ret < 0) @@ -228,13 +222,21 @@ int esp32_bringup(void) } #endif +#ifdef CONFIG_ESPRESSIF_HR_TIMER + ret = esp_hr_timer_init(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: esp_hr_timer_init() failed: %d\n", ret); + } +#endif + /* First, register the timer drivers and let timer 1 for oneshot * if it is enabled. */ #ifdef CONFIG_TIMER -#if defined(CONFIG_ESP32_TIMER0) && !defined(CONFIG_ESP32_RT_TIMER) +#if defined(CONFIG_ESP32_TIMER0) && !defined(CONFIG_ESPRESSIF_HR_TIMER) ret = esp32_timer_initialize("/dev/timer0", TIMER0); if (ret < 0) { @@ -390,7 +392,7 @@ int esp32_bringup(void) #ifdef CONFIG_RTC_DRIVER /* Instantiate the ESP32 RTC driver */ - ret = esp32_rtc_driverinit(); + ret = esp_rtc_driverinit(); if (ret < 0) { syslog(LOG_ERR, diff --git a/boards/xtensa/esp32/lilygo_tbeam_lora_gps/src/esp32_buttons.c b/boards/xtensa/esp32/lilygo_tbeam_lora_gps/src/esp32_buttons.c index 9add751242401..b4a30b71d05c2 100644 --- a/boards/xtensa/esp32/lilygo_tbeam_lora_gps/src/esp32_buttons.c +++ b/boards/xtensa/esp32/lilygo_tbeam_lora_gps/src/esp32_buttons.c @@ -37,7 +37,7 @@ #include #include -#include "esp32_gpio.h" +#include "espressif/esp_gpio.h" #include "lilygo_tbeam_lora_gps.h" @@ -58,7 +58,7 @@ uint32_t board_button_initialize(void) { - esp32_configgpio(BUTTON_BOOT, INPUT_FUNCTION_3 | PULLUP); + esp_configgpio(BUTTON_BOOT, INPUT_FUNCTION_3 | PULLUP | CHANGE); return 1; } @@ -79,13 +79,13 @@ uint32_t board_buttons(void) int i = 0; int n = 0; - bool b0 = esp32_gpioread(BUTTON_BOOT); + bool b0 = esp_gpioread(BUTTON_BOOT); for (i = 0; i < 10; i++) { up_mdelay(1); /* TODO */ - bool b1 = esp32_gpioread(BUTTON_BOOT); + bool b1 = esp_gpioread(BUTTON_BOOT); if (b0 == b1) { @@ -131,38 +131,6 @@ uint32_t board_buttons(void) #ifdef CONFIG_ARCH_IRQBUTTONS int board_button_irq(int id, xcpt_t irqhandler, void *arg) { - int ret; - DEBUGASSERT(id == 0); - - int irq = ESP32_PIN2IRQ(BUTTON_BOOT); - - if (NULL != irqhandler) - { - /* Make sure the interrupt is disabled */ - - esp32_gpioirqdisable(irq); - - ret = irq_attach(irq, irqhandler, arg); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: irq_attach() failed: %d\n", ret); - return ret; - } - - gpioinfo("Attach %p\n", irqhandler); - - gpioinfo("Enabling the interrupt\n"); - - /* Configure the interrupt for rising and falling edges */ - - esp32_gpioirqenable(irq, CHANGE); - } - else - { - gpioinfo("Disable the interrupt\n"); - esp32_gpioirqdisable(irq); - } - - return OK; + return esp_gpio_irq(BUTTON_BOOT, irqhandler, arg); } #endif diff --git a/boards/xtensa/esp32/lilygo_tbeam_lora_gps/src/esp32_gpio.c b/boards/xtensa/esp32/lilygo_tbeam_lora_gps/src/esp32_gpio.c index c5b5e923ac725..5b0047551fdb0 100644 --- a/boards/xtensa/esp32/lilygo_tbeam_lora_gps/src/esp32_gpio.c +++ b/boards/xtensa/esp32/lilygo_tbeam_lora_gps/src/esp32_gpio.c @@ -36,7 +36,7 @@ #include -#include "esp32_gpio.h" +#include "espressif/esp_gpio.h" #include "hardware/esp32_gpio_sigmap.h" #include "lilygo_tbeam_lora_gps.h" @@ -47,7 +47,7 @@ * Pre-processor Definitions ****************************************************************************/ -#if !defined(CONFIG_ESP32_GPIO_IRQ) && BOARD_NGPIOINT > 0 +#if !defined(CONFIG_ESPRESSIF_GPIO_IRQ) && BOARD_NGPIOINT > 0 # error "NGPIOINT is > 0 and GPIO interrupts aren't enabled" #endif @@ -183,7 +183,7 @@ static int gpout_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(esp32gpio->id < BOARD_NGPIOOUT); gpioinfo("Reading...\n"); - *value = esp32_gpioread(g_gpiooutputs[esp32gpio->id]); + *value = esp_gpioread(g_gpiooutputs[esp32gpio->id]); return OK; } @@ -199,7 +199,7 @@ static int gpout_write(struct gpio_dev_s *dev, bool value) DEBUGASSERT(esp32gpio->id < BOARD_NGPIOOUT); gpioinfo("Writing %d\n", (int)value); - esp32_gpiowrite(g_gpiooutputs[esp32gpio->id], value); + esp_gpiowrite(g_gpiooutputs[esp32gpio->id], value); return OK; } #endif @@ -217,7 +217,7 @@ static int gpin_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(esp32gpio->id < BOARD_NGPIOIN); gpioinfo("Reading... pin %" PRIu32 "\n", g_gpioinputs[esp32gpio->id]); - *value = esp32_gpioread(g_gpioinputs[esp32gpio->id]); + *value = esp_gpioread(g_gpioinputs[esp32gpio->id]); return OK; } #endif @@ -253,7 +253,7 @@ static int gpint_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(esp32gpint->esp32gpio.id < BOARD_NGPIOINT); gpioinfo("Reading int pin...\n"); - *value = esp32_gpioread(g_gpiointinputs[esp32gpint->esp32gpio.id]); + *value = esp_gpioread(g_gpiointinputs[esp32gpint->esp32gpio.id]); return OK; } @@ -266,23 +266,26 @@ static int gpint_attach(struct gpio_dev_s *dev, { struct esp32gpint_dev_s *esp32gpint = (struct esp32gpint_dev_s *)dev; - int irq = ESP32_PIN2IRQ(g_gpiointinputs[esp32gpint->esp32gpio.id]); int ret; gpioinfo("Attaching the callback\n"); /* Make sure the interrupt is disabled */ - esp32_gpioirqdisable(irq); - ret = irq_attach(irq, - esp32gpio_interrupt, - &g_gpint[esp32gpint->esp32gpio.id]); + esp_gpioirqdisable(g_gpiointinputs[esp32gpint->esp32gpio.id]); + + ret = esp_gpio_irq(g_gpiointinputs[esp32gpint->esp32gpio.id], + esp32gpio_interrupt, + &g_gpint[esp32gpint->esp32gpio.id]); if (ret < 0) { - syslog(LOG_ERR, "ERROR: gpint_attach() failed: %d\n", ret); return ret; } + /* Make sure the interrupt is disabled */ + + esp_gpioirqdisable(g_gpiointinputs[esp32gpint->esp32gpio.id]); + gpioinfo("Attach %p\n", callback); esp32gpint->callback = callback; return OK; @@ -296,7 +299,6 @@ static int gpint_enable(struct gpio_dev_s *dev, bool enable) { struct esp32gpint_dev_s *esp32gpint = (struct esp32gpint_dev_s *)dev; - int irq = ESP32_PIN2IRQ(g_gpiointinputs[esp32gpint->esp32gpio.id]); if (enable) { @@ -306,13 +308,13 @@ static int gpint_enable(struct gpio_dev_s *dev, bool enable) /* Configure the interrupt for rising edge */ - esp32_gpioirqenable(irq, RISING); + esp_gpioirqenable(g_gpiointinputs[esp32gpint->esp32gpio.id]); } } else { gpioinfo("Disable the interrupt\n"); - esp32_gpioirqdisable(irq); + esp_gpioirqdisable(g_gpiointinputs[esp32gpint->esp32gpio.id]); } return OK; @@ -344,10 +346,9 @@ int esp32_gpio_init(void) /* Configure the pins that will be used as output */ - esp32_gpio_matrix_out(g_gpiooutputs[i], SIG_GPIO_OUT_IDX, 0, 0); - esp32_configgpio(g_gpiooutputs[i], OUTPUT_FUNCTION_3 | - INPUT_FUNCTION_3); - esp32_gpiowrite(g_gpiooutputs[i], 0); + esp_gpio_matrix_out(g_gpiooutputs[i], SIG_GPIO_OUT_IDX, 0, 0); + esp_configgpio(g_gpiooutputs[i], OUTPUT_FUNCTION_3 | INPUT_FUNCTION_3); + esp_gpiowrite(g_gpiooutputs[i], 0); pincount++; } @@ -365,7 +366,7 @@ int esp32_gpio_init(void) /* Configure the pins that will be used as INPUT */ - esp32_configgpio(g_gpioinputs[i], INPUT_FUNCTION_3); + esp_configgpio(g_gpioinputs[i], INPUT_FUNCTION_3 | PULLDOWN); pincount++; } @@ -383,7 +384,8 @@ int esp32_gpio_init(void) /* Configure the pins that will be used as interrupt input */ - esp32_configgpio(g_gpiointinputs[i], INPUT_FUNCTION_3 | PULLDOWN); + esp_configgpio(g_gpiointinputs[i], + INPUT_FUNCTION_3 | PULLUP | FALLING); pincount++; } diff --git a/boards/xtensa/esp32/lilygo_tbeam_lora_gps/src/esp32_sx127x.c b/boards/xtensa/esp32/lilygo_tbeam_lora_gps/src/esp32_sx127x.c index 4bea04c860a62..1339eb4698074 100644 --- a/boards/xtensa/esp32/lilygo_tbeam_lora_gps/src/esp32_sx127x.c +++ b/boards/xtensa/esp32/lilygo_tbeam_lora_gps/src/esp32_sx127x.c @@ -37,7 +37,7 @@ #include #include -#include "esp32_gpio.h" +#include "espressif/esp_gpio.h" #include "esp32_spi.h" #include "hardware/esp32_gpio_sigmap.h" @@ -90,13 +90,13 @@ static int sx127x_irq0_attach(xcpt_t isr, void *arg) /* Make sure the interrupt is disabled */ - esp32_gpioirqdisable(irq); + esp_gpioirqdisable(irq); wlinfo("Attach DIO0 IRQ\n"); /* Attach to IRQ on pin connected to DIO0 */ - ret = irq_attach(irq, isr, arg); + ret = esp_gpio_irq(GPIO_SX127X_DIO0, isr, arg); if (ret < 0) { syslog(LOG_ERR, "ERROR: gpint_attach() failed: %d\n", ret); @@ -105,7 +105,7 @@ static int sx127x_irq0_attach(xcpt_t isr, void *arg) /* IRQ on rising edge */ - esp32_gpioirqenable(irq, RISING); + esp_gpioirqenable(irq); return OK; } @@ -120,12 +120,12 @@ static void sx127x_chip_reset(void) /* Configure reset as output */ - esp32_gpio_matrix_out(GPIO_SX127X_RESET, SIG_GPIO_OUT_IDX, 0, 0); - esp32_configgpio(GPIO_SX127X_RESET, OUTPUT_FUNCTION_3 | INPUT_FUNCTION_3); + esp_gpio_matrix_out(GPIO_SX127X_RESET, SIG_GPIO_OUT_IDX, 0, 0); + esp_configgpio(GPIO_SX127X_RESET, OUTPUT_FUNCTION_3 | INPUT_FUNCTION_3); /* Set pin to zero */ - esp32_gpiowrite(GPIO_SX127X_RESET, 0); + esp_gpiowrite(GPIO_SX127X_RESET, 0); /* Wait 1 ms */ @@ -133,7 +133,7 @@ static void sx127x_chip_reset(void) /* Set pin to high */ - esp32_gpiowrite(GPIO_SX127X_RESET, 1); + esp_gpiowrite(GPIO_SX127X_RESET, 1); /* Wait 10 ms */ @@ -203,7 +203,7 @@ int esp32_lpwaninitialize(void) /* Setup DIO0 */ - esp32_configgpio(GPIO_SX127X_DIO0, INPUT_FUNCTION_3 | PULLDOWN); + esp_configgpio(GPIO_SX127X_DIO0, INPUT_FUNCTION_3 | PULLDOWN | RISING); /* Init SPI bus */ diff --git a/boards/xtensa/esp32/lilygo_tbeam_lora_gps/src/esp32_userleds.c b/boards/xtensa/esp32/lilygo_tbeam_lora_gps/src/esp32_userleds.c index 819200f78b955..7acfbb3e461b4 100644 --- a/boards/xtensa/esp32/lilygo_tbeam_lora_gps/src/esp32_userleds.c +++ b/boards/xtensa/esp32/lilygo_tbeam_lora_gps/src/esp32_userleds.c @@ -33,7 +33,7 @@ #include #include -#include "esp32_gpio.h" +#include "espressif/esp_gpio.h" #include "lilygo_tbeam_lora_gps.h" /**************************************************************************** @@ -61,7 +61,7 @@ uint32_t board_userled_initialize(void) for (i = 0; i < BOARD_NLEDS; i++) { - esp32_configgpio(g_ledcfg[i], OUTPUT); + esp_configgpio(g_ledcfg[i], OUTPUT); } return BOARD_NLEDS; @@ -75,7 +75,7 @@ void board_userled(int led, bool ledon) { if ((unsigned)led < BOARD_NLEDS) { - esp32_gpiowrite(g_ledcfg[led], ledon); + esp_gpiowrite(g_ledcfg[led], ledon); } } @@ -91,7 +91,6 @@ void board_userled_all(uint32_t ledset) for (i = 0; i < BOARD_NLEDS; i++) { - esp32_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); + esp_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); } } - diff --git a/boards/xtensa/esp32/ttgo_eink5_v2/configs/fb/defconfig b/boards/xtensa/esp32/ttgo_eink5_v2/configs/fb/defconfig index 177dc8e142424..3350bb967cb79 100644 --- a/boards/xtensa/esp32/ttgo_eink5_v2/configs/fb/defconfig +++ b/boards/xtensa/esp32/ttgo_eink5_v2/configs/fb/defconfig @@ -14,6 +14,9 @@ CONFIG_ARCH_BOARD_TTGO_T5V2_ESP32=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LATE_INITIALIZE=y diff --git a/boards/xtensa/esp32/ttgo_eink5_v2/src/esp32_bringup.c b/boards/xtensa/esp32/ttgo_eink5_v2/src/esp32_bringup.c index 8b23e705c2df3..e0ebcfafad65e 100644 --- a/boards/xtensa/esp32/ttgo_eink5_v2/src/esp32_bringup.c +++ b/boards/xtensa/esp32/ttgo_eink5_v2/src/esp32_bringup.c @@ -50,6 +50,8 @@ #include #include "esp32_partition.h" +#include "espressif/esp_gpio.h" +#include "esp32_start.h" #ifdef CONFIG_USERLED # include @@ -115,16 +117,16 @@ # include "esp32_aes.h" #endif -#ifdef CONFIG_ESP32_RT_TIMER -# include "esp32_rt_timer.h" -#endif - #ifdef CONFIG_INPUT_BUTTONS # include #endif #ifdef CONFIG_RTC_DRIVER -# include "esp32_rtc_lowerhalf.h" +# include "espressif/esp_rtc.h" +#endif + +#ifdef CONFIG_ESPRESSIF_HR_TIMER +# include "espressif/esp_hr_timer.h" #endif #ifdef CONFIG_SPI_DRIVER @@ -270,14 +272,6 @@ int esp32_bringup(void) } #endif -#ifdef CONFIG_ESP32_RT_TIMER - ret = esp32_rt_timer_init(); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize RT timer: %d\n", ret); - } -#endif - #ifdef CONFIG_ESPRESSIF_WIFI_BT_COEXIST ret = esp32_wifi_bt_coexist_init(); if (ret) @@ -304,13 +298,21 @@ int esp32_bringup(void) } #endif +#ifdef CONFIG_ESPRESSIF_HR_TIMER + ret = esp_hr_timer_init(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: esp_hr_timer_init() failed: %d\n", ret); + } +#endif + /* First, register the timer drivers and let timer 1 for oneshot * if it is enabled. */ #ifdef CONFIG_TIMER -#if defined(CONFIG_ESP32_TIMER0) && !defined(CONFIG_ESP32_RT_TIMER) +#if defined(CONFIG_ESP32_TIMER0) && !defined(CONFIG_ESPRESSIF_HR_TIMER) ret = esp32_timer_initialize("/dev/timer0", TIMER0); if (ret < 0) { @@ -495,7 +497,7 @@ int esp32_bringup(void) #ifdef CONFIG_RTC_DRIVER /* Instantiate the ESP32 RTC driver */ - ret = esp32_rtc_driverinit(); + ret = esp_rtc_driverinit(); if (ret < 0) { syslog(LOG_ERR, diff --git a/boards/xtensa/esp32/ttgo_eink5_v2/src/esp32_buttons.c b/boards/xtensa/esp32/ttgo_eink5_v2/src/esp32_buttons.c index fcf05c3ee5ce3..af54ddc41e298 100644 --- a/boards/xtensa/esp32/ttgo_eink5_v2/src/esp32_buttons.c +++ b/boards/xtensa/esp32/ttgo_eink5_v2/src/esp32_buttons.c @@ -37,7 +37,7 @@ #include #include -#include "esp32_gpio.h" +#include "espressif/esp_gpio.h" #include "ttgo_eink5_v2.h" @@ -58,9 +58,9 @@ uint32_t board_button_initialize(void) { - esp32_configgpio(BUTN1, INPUT_FUNCTION_3 | PULLUP); - esp32_configgpio(BUTN2, INPUT_FUNCTION_3 | PULLUP); - esp32_configgpio(BUTN3, INPUT_FUNCTION_3 | PULLUP); + esp_configgpio(BUTN1, INPUT_FUNCTION_3 | PULLUP); + esp_configgpio(BUTN2, INPUT_FUNCTION_3 | PULLUP); + esp_configgpio(BUTN3, INPUT_FUNCTION_3 | PULLUP); return 1; } @@ -81,13 +81,13 @@ uint32_t board_buttons(void) int i = 0; int n = 0; - bool b0 = esp32_gpioread(BUTTON_BOOT); + bool b0 = esp_gpioread(BUTTON_BOOT); for (i = 0; i < 10; i++) { up_mdelay(1); /* TODO */ - bool b1 = esp32_gpioread(BUTTON_BOOT); + bool b1 = esp_gpioread(BUTTON_BOOT); if (b0 == b1) { @@ -133,38 +133,6 @@ uint32_t board_buttons(void) #ifdef CONFIG_ARCH_IRQBUTTONS int board_button_irq(int id, xcpt_t irqhandler, void *arg) { - int ret; - DEBUGASSERT(id == 0); - - int irq = ESP32_PIN2IRQ(BUTTON_BOOT); - - if (NULL != irqhandler) - { - /* Make sure the interrupt is disabled */ - - esp32_gpioirqdisable(irq); - - ret = irq_attach(irq, irqhandler, arg); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: irq_attach() failed: %d\n", ret); - return ret; - } - - gpioinfo("Attach %p\n", irqhandler); - - gpioinfo("Enabling the interrupt\n"); - - /* Configure the interrupt for rising and falling edges */ - - esp32_gpioirqenable(irq, CHANGE); - } - else - { - gpioinfo("Disable the interrupt\n"); - esp32_gpioirqdisable(irq); - } - - return OK; + return esp_gpio_irq(BUTTON_BOOT, irqhandler, arg); } #endif diff --git a/boards/xtensa/esp32/ttgo_eink5_v2/src/esp32_gpio.c b/boards/xtensa/esp32/ttgo_eink5_v2/src/esp32_gpio.c index bbcda57bf7974..04655ec335c63 100644 --- a/boards/xtensa/esp32/ttgo_eink5_v2/src/esp32_gpio.c +++ b/boards/xtensa/esp32/ttgo_eink5_v2/src/esp32_gpio.c @@ -37,7 +37,7 @@ #include #include "ttgo_eink5_v2.h" -#include "esp32_gpio.h" +#include "espressif/esp_gpio.h" #include "hardware/esp32_gpio_sigmap.h" #if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF) @@ -46,7 +46,7 @@ * Pre-processor Definitions ****************************************************************************/ -#if !defined(CONFIG_ESP32_GPIO_IRQ) && BOARD_NGPIOINT > 0 +#if !defined(CONFIG_ESPRESSIF_GPIO_IRQ) && BOARD_NGPIOINT > 0 # error "NGPIOINT is > 0 and GPIO interrupts aren't enabled" #endif @@ -182,7 +182,7 @@ static int gpout_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(esp32gpio->id < BOARD_NGPIOOUT); gpioinfo("Reading...\n"); - *value = esp32_gpioread(g_gpiooutputs[esp32gpio->id]); + *value = esp_gpioread(g_gpiooutputs[esp32gpio->id]); return OK; } @@ -198,7 +198,7 @@ static int gpout_write(struct gpio_dev_s *dev, bool value) DEBUGASSERT(esp32gpio->id < BOARD_NGPIOOUT); gpioinfo("Writing %d\n", (int)value); - esp32_gpiowrite(g_gpiooutputs[esp32gpio->id], value); + esp_gpiowrite(g_gpiooutputs[esp32gpio->id], value); return OK; } #endif @@ -216,7 +216,7 @@ static int gpin_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(esp32gpio->id < BOARD_NGPIOIN); gpioinfo("Reading... pin %" PRIu32 "\n", g_gpioinputs[esp32gpio->id]); - *value = esp32_gpioread(g_gpioinputs[esp32gpio->id]); + *value = esp_gpioread(g_gpioinputs[esp32gpio->id]); return OK; } #endif @@ -252,7 +252,7 @@ static int gpint_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(esp32gpint->esp32gpio.id < BOARD_NGPIOINT); gpioinfo("Reading int pin...\n"); - *value = esp32_gpioread(g_gpiointinputs[esp32gpint->esp32gpio.id]); + *value = esp_gpioread(g_gpiointinputs[esp32gpint->esp32gpio.id]); return OK; } @@ -265,23 +265,26 @@ static int gpint_attach(struct gpio_dev_s *dev, { struct esp32gpint_dev_s *esp32gpint = (struct esp32gpint_dev_s *)dev; - int irq = ESP32_PIN2IRQ(g_gpiointinputs[esp32gpint->esp32gpio.id]); int ret; gpioinfo("Attaching the callback\n"); /* Make sure the interrupt is disabled */ - esp32_gpioirqdisable(irq); - ret = irq_attach(irq, - esp32gpio_interrupt, - &g_gpint[esp32gpint->esp32gpio.id]); + esp_gpioirqdisable(g_gpiointinputs[esp32gpint->esp32gpio.id]); + + ret = esp_gpio_irq(g_gpiointinputs[esp32gpint->esp32gpio.id], + esp32gpio_interrupt, + &g_gpint[esp32gpint->esp32gpio.id]); if (ret < 0) { - syslog(LOG_ERR, "ERROR: gpint_attach() failed: %d\n", ret); return ret; } + /* Make sure the interrupt is disabled */ + + esp_gpioirqdisable(g_gpiointinputs[esp32gpint->esp32gpio.id]); + gpioinfo("Attach %p\n", callback); esp32gpint->callback = callback; return OK; @@ -295,7 +298,6 @@ static int gpint_enable(struct gpio_dev_s *dev, bool enable) { struct esp32gpint_dev_s *esp32gpint = (struct esp32gpint_dev_s *)dev; - int irq = ESP32_PIN2IRQ(g_gpiointinputs[esp32gpint->esp32gpio.id]); if (enable) { @@ -305,13 +307,13 @@ static int gpint_enable(struct gpio_dev_s *dev, bool enable) /* Configure the interrupt for rising edge */ - esp32_gpioirqenable(irq, RISING); + esp_gpioirqenable(g_gpiointinputs[esp32gpint->esp32gpio.id]); } } else { gpioinfo("Disable the interrupt\n"); - esp32_gpioirqdisable(irq); + esp_gpioirqdisable(g_gpiointinputs[esp32gpint->esp32gpio.id]); } return OK; @@ -343,10 +345,9 @@ int esp32_gpio_init(void) /* Configure the pins that will be used as output */ - esp32_gpio_matrix_out(g_gpiooutputs[i], SIG_GPIO_OUT_IDX, 0, 0); - esp32_configgpio(g_gpiooutputs[i], OUTPUT_FUNCTION_3 | - INPUT_FUNCTION_3); - esp32_gpiowrite(g_gpiooutputs[i], 0); + esp_gpio_matrix_out(g_gpiooutputs[i], SIG_GPIO_OUT_IDX, 0, 0); + esp_configgpio(g_gpiooutputs[i], OUTPUT_FUNCTION_3 | INPUT_FUNCTION_3); + esp_gpiowrite(g_gpiooutputs[i], 0); pincount++; } @@ -364,7 +365,7 @@ int esp32_gpio_init(void) /* Configure the pins that will be used as INPUT */ - esp32_configgpio(g_gpioinputs[i], INPUT_FUNCTION_3); + esp_configgpio(g_gpioinputs[i], INPUT_FUNCTION_3 | PULLDOWN); pincount++; } @@ -382,7 +383,8 @@ int esp32_gpio_init(void) /* Configure the pins that will be used as interrupt input */ - esp32_configgpio(g_gpiointinputs[i], INPUT_FUNCTION_3 | PULLDOWN); + esp_configgpio(g_gpiointinputs[i], + INPUT_FUNCTION_3 | PULLUP | FALLING); pincount++; } diff --git a/boards/xtensa/esp32/ttgo_eink5_v2/src/esp32_userleds.c b/boards/xtensa/esp32/ttgo_eink5_v2/src/esp32_userleds.c index 118e0f357ff75..d1e0e9853b3f8 100644 --- a/boards/xtensa/esp32/ttgo_eink5_v2/src/esp32_userleds.c +++ b/boards/xtensa/esp32/ttgo_eink5_v2/src/esp32_userleds.c @@ -33,7 +33,7 @@ #include #include -#include "esp32_gpio.h" +#include "espressif/esp_gpio.h" #include "ttgo_eink5_v2.h" /**************************************************************************** @@ -61,7 +61,7 @@ uint32_t board_userled_initialize(void) for (i = 0; i < BOARD_NLEDS; i++) { - esp32_configgpio(g_ledcfg[i], OUTPUT); + esp_configgpio(g_ledcfg[i], OUTPUT); } return BOARD_NLEDS; @@ -75,7 +75,7 @@ void board_userled(int led, bool ledon) { if ((unsigned)led < BOARD_NLEDS) { - esp32_gpiowrite(g_ledcfg[led], ledon); + esp_gpiowrite(g_ledcfg[led], ledon); } } @@ -91,7 +91,6 @@ void board_userled_all(uint32_t ledset) for (i = 0; i < BOARD_NLEDS; i++) { - esp32_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); + esp_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); } } - diff --git a/boards/xtensa/esp32/ttgo_lora_esp32/configs/nsh/defconfig b/boards/xtensa/esp32/ttgo_lora_esp32/configs/nsh/defconfig index c8edfa381314c..0dc9c5463e845 100644 --- a/boards/xtensa/esp32/ttgo_lora_esp32/configs/nsh/defconfig +++ b/boards/xtensa/esp32/ttgo_lora_esp32/configs/nsh/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_BOARD_TTGO_LORA_ESP32=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROOM32=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/ttgo_lora_esp32/configs/sx127x/defconfig b/boards/xtensa/esp32/ttgo_lora_esp32/configs/sx127x/defconfig index 0f1cfdbaf07d8..8d5d08348cd23 100644 --- a/boards/xtensa/esp32/ttgo_lora_esp32/configs/sx127x/defconfig +++ b/boards/xtensa/esp32/ttgo_lora_esp32/configs/sx127x/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_BOARD_TTGO_LORA_ESP32=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROOM32=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/ttgo_lora_esp32/src/esp32_bringup.c b/boards/xtensa/esp32/ttgo_lora_esp32/src/esp32_bringup.c index e841b9bd9b5bf..ec48ccd78a620 100644 --- a/boards/xtensa/esp32/ttgo_lora_esp32/src/esp32_bringup.c +++ b/boards/xtensa/esp32/ttgo_lora_esp32/src/esp32_bringup.c @@ -46,6 +46,8 @@ #include "espressif/esp_efuse.h" #endif #include "esp32_partition.h" +#include "espressif/esp_gpio.h" +#include "esp32_start.h" #ifdef CONFIG_USERLED # include @@ -95,16 +97,16 @@ # include "esp32_aes.h" #endif -#ifdef CONFIG_ESP32_RT_TIMER -# include "esp32_rt_timer.h" -#endif - #ifdef CONFIG_INPUT_BUTTONS # include #endif #ifdef CONFIG_RTC_DRIVER -# include "esp32_rtc_lowerhalf.h" +# include "espressif/esp_rtc.h" +#endif + +#ifdef CONFIG_ESPRESSIF_HR_TIMER +# include "espressif/esp_hr_timer.h" #endif #ifdef CONFIG_SPI_DRIVER @@ -192,14 +194,6 @@ int esp32_bringup(void) } #endif -#ifdef CONFIG_ESP32_RT_TIMER - ret = esp32_rt_timer_init(); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize RT timer: %d\n", ret); - } -#endif - #ifdef CONFIG_LPWAN_SX127X ret = esp32_lpwaninitialize(); if (ret < 0) @@ -228,13 +222,21 @@ int esp32_bringup(void) } #endif +#ifdef CONFIG_ESPRESSIF_HR_TIMER + ret = esp_hr_timer_init(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: esp_hr_timer_init() failed: %d\n", ret); + } +#endif + /* First, register the timer drivers and let timer 1 for oneshot * if it is enabled. */ #ifdef CONFIG_TIMER -#if defined(CONFIG_ESP32_TIMER0) && !defined(CONFIG_ESP32_RT_TIMER) +#if defined(CONFIG_ESP32_TIMER0) && !defined(CONFIG_ESPRESSIF_HR_TIMER) ret = esp32_timer_initialize("/dev/timer0", TIMER0); if (ret < 0) { @@ -390,7 +392,7 @@ int esp32_bringup(void) #ifdef CONFIG_RTC_DRIVER /* Instantiate the ESP32 RTC driver */ - ret = esp32_rtc_driverinit(); + ret = esp_rtc_driverinit(); if (ret < 0) { syslog(LOG_ERR, diff --git a/boards/xtensa/esp32/ttgo_lora_esp32/src/esp32_buttons.c b/boards/xtensa/esp32/ttgo_lora_esp32/src/esp32_buttons.c index cb006c5b3a9a3..ef4d3eaae5e3f 100644 --- a/boards/xtensa/esp32/ttgo_lora_esp32/src/esp32_buttons.c +++ b/boards/xtensa/esp32/ttgo_lora_esp32/src/esp32_buttons.c @@ -37,7 +37,7 @@ #include #include -#include "esp32_gpio.h" +#include "espressif/esp_gpio.h" #include "ttgo_lora_esp32.h" @@ -58,7 +58,7 @@ uint32_t board_button_initialize(void) { - esp32_configgpio(BUTTON_BOOT, INPUT_FUNCTION_3 | PULLUP); + esp_configgpio(BUTTON_BOOT, INPUT_FUNCTION_3 | PULLUP | CHANGE); return 1; } @@ -79,13 +79,13 @@ uint32_t board_buttons(void) int i = 0; int n = 0; - bool b0 = esp32_gpioread(BUTTON_BOOT); + bool b0 = esp_gpioread(BUTTON_BOOT); for (i = 0; i < 10; i++) { up_mdelay(1); /* TODO */ - bool b1 = esp32_gpioread(BUTTON_BOOT); + bool b1 = esp_gpioread(BUTTON_BOOT); if (b0 == b1) { @@ -131,38 +131,6 @@ uint32_t board_buttons(void) #ifdef CONFIG_ARCH_IRQBUTTONS int board_button_irq(int id, xcpt_t irqhandler, void *arg) { - int ret; - DEBUGASSERT(id == 0); - - int irq = ESP32_PIN2IRQ(BUTTON_BOOT); - - if (NULL != irqhandler) - { - /* Make sure the interrupt is disabled */ - - esp32_gpioirqdisable(irq); - - ret = irq_attach(irq, irqhandler, arg); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: irq_attach() failed: %d\n", ret); - return ret; - } - - gpioinfo("Attach %p\n", irqhandler); - - gpioinfo("Enabling the interrupt\n"); - - /* Configure the interrupt for rising and falling edges */ - - esp32_gpioirqenable(irq, CHANGE); - } - else - { - gpioinfo("Disable the interrupt\n"); - esp32_gpioirqdisable(irq); - } - - return OK; + return esp_gpio_irq(BUTTON_BOOT, irqhandler, arg); } #endif diff --git a/boards/xtensa/esp32/ttgo_lora_esp32/src/esp32_gpio.c b/boards/xtensa/esp32/ttgo_lora_esp32/src/esp32_gpio.c index 688fec02fdccc..1f20f22b8b88d 100644 --- a/boards/xtensa/esp32/ttgo_lora_esp32/src/esp32_gpio.c +++ b/boards/xtensa/esp32/ttgo_lora_esp32/src/esp32_gpio.c @@ -37,7 +37,7 @@ #include #include "ttgo_lora_esp32.h" -#include "esp32_gpio.h" +#include "espressif/esp_gpio.h" #include "hardware/esp32_gpio_sigmap.h" #if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF) @@ -46,7 +46,7 @@ * Pre-processor Definitions ****************************************************************************/ -#if !defined(CONFIG_ESP32_GPIO_IRQ) && BOARD_NGPIOINT > 0 +#if !defined(CONFIG_ESPRESSIF_GPIO_IRQ) && BOARD_NGPIOINT > 0 # error "NGPIOINT is > 0 and GPIO interrupts aren't enabled" #endif @@ -182,7 +182,7 @@ static int gpout_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(esp32gpio->id < BOARD_NGPIOOUT); gpioinfo("Reading...\n"); - *value = esp32_gpioread(g_gpiooutputs[esp32gpio->id]); + *value = esp_gpioread(g_gpiooutputs[esp32gpio->id]); return OK; } @@ -198,7 +198,7 @@ static int gpout_write(struct gpio_dev_s *dev, bool value) DEBUGASSERT(esp32gpio->id < BOARD_NGPIOOUT); gpioinfo("Writing %d\n", (int)value); - esp32_gpiowrite(g_gpiooutputs[esp32gpio->id], value); + esp_gpiowrite(g_gpiooutputs[esp32gpio->id], value); return OK; } #endif @@ -216,7 +216,7 @@ static int gpin_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(esp32gpio->id < BOARD_NGPIOIN); gpioinfo("Reading... pin %" PRIu32 "\n", g_gpioinputs[esp32gpio->id]); - *value = esp32_gpioread(g_gpioinputs[esp32gpio->id]); + *value = esp_gpioread(g_gpioinputs[esp32gpio->id]); return OK; } #endif @@ -252,7 +252,7 @@ static int gpint_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(esp32gpint->esp32gpio.id < BOARD_NGPIOINT); gpioinfo("Reading int pin...\n"); - *value = esp32_gpioread(g_gpiointinputs[esp32gpint->esp32gpio.id]); + *value = esp_gpioread(g_gpiointinputs[esp32gpint->esp32gpio.id]); return OK; } @@ -265,23 +265,26 @@ static int gpint_attach(struct gpio_dev_s *dev, { struct esp32gpint_dev_s *esp32gpint = (struct esp32gpint_dev_s *)dev; - int irq = ESP32_PIN2IRQ(g_gpiointinputs[esp32gpint->esp32gpio.id]); int ret; gpioinfo("Attaching the callback\n"); /* Make sure the interrupt is disabled */ - esp32_gpioirqdisable(irq); - ret = irq_attach(irq, - esp32gpio_interrupt, - &g_gpint[esp32gpint->esp32gpio.id]); + esp_gpioirqdisable(g_gpiointinputs[esp32gpint->esp32gpio.id]); + + ret = esp_gpio_irq(g_gpiointinputs[esp32gpint->esp32gpio.id], + esp32gpio_interrupt, + &g_gpint[esp32gpint->esp32gpio.id]); if (ret < 0) { - syslog(LOG_ERR, "ERROR: gpint_attach() failed: %d\n", ret); return ret; } + /* Make sure the interrupt is disabled */ + + esp_gpioirqdisable(g_gpiointinputs[esp32gpint->esp32gpio.id]); + gpioinfo("Attach %p\n", callback); esp32gpint->callback = callback; return OK; @@ -295,7 +298,6 @@ static int gpint_enable(struct gpio_dev_s *dev, bool enable) { struct esp32gpint_dev_s *esp32gpint = (struct esp32gpint_dev_s *)dev; - int irq = ESP32_PIN2IRQ(g_gpiointinputs[esp32gpint->esp32gpio.id]); if (enable) { @@ -305,13 +307,13 @@ static int gpint_enable(struct gpio_dev_s *dev, bool enable) /* Configure the interrupt for rising edge */ - esp32_gpioirqenable(irq, RISING); + esp_gpioirqenable(g_gpiointinputs[esp32gpint->esp32gpio.id]); } } else { gpioinfo("Disable the interrupt\n"); - esp32_gpioirqdisable(irq); + esp_gpioirqdisable(g_gpiointinputs[esp32gpint->esp32gpio.id]); } return OK; @@ -343,10 +345,9 @@ int esp32_gpio_init(void) /* Configure the pins that will be used as output */ - esp32_gpio_matrix_out(g_gpiooutputs[i], SIG_GPIO_OUT_IDX, 0, 0); - esp32_configgpio(g_gpiooutputs[i], OUTPUT_FUNCTION_3 | - INPUT_FUNCTION_3); - esp32_gpiowrite(g_gpiooutputs[i], 0); + esp_gpio_matrix_out(g_gpiooutputs[i], SIG_GPIO_OUT_IDX, 0, 0); + esp_configgpio(g_gpiooutputs[i], OUTPUT_FUNCTION_3 | INPUT_FUNCTION_3); + esp_gpiowrite(g_gpiooutputs[i], 0); pincount++; } @@ -364,7 +365,7 @@ int esp32_gpio_init(void) /* Configure the pins that will be used as INPUT */ - esp32_configgpio(g_gpioinputs[i], INPUT_FUNCTION_3); + esp_configgpio(g_gpioinputs[i], INPUT_FUNCTION_3 | PULLDOWN); pincount++; } @@ -382,7 +383,8 @@ int esp32_gpio_init(void) /* Configure the pins that will be used as interrupt input */ - esp32_configgpio(g_gpiointinputs[i], INPUT_FUNCTION_3 | PULLDOWN); + esp_configgpio(g_gpiointinputs[i], + INPUT_FUNCTION_3 | PULLUP | FALLING); pincount++; } diff --git a/boards/xtensa/esp32/ttgo_lora_esp32/src/esp32_sx127x.c b/boards/xtensa/esp32/ttgo_lora_esp32/src/esp32_sx127x.c index f28c664d47951..291b4db78904b 100644 --- a/boards/xtensa/esp32/ttgo_lora_esp32/src/esp32_sx127x.c +++ b/boards/xtensa/esp32/ttgo_lora_esp32/src/esp32_sx127x.c @@ -37,7 +37,7 @@ #include #include -#include "esp32_gpio.h" +#include "espressif/esp_gpio.h" #include "esp32_spi.h" #include "hardware/esp32_gpio_sigmap.h" @@ -90,13 +90,13 @@ static int sx127x_irq0_attach(xcpt_t isr, void *arg) /* Make sure the interrupt is disabled */ - esp32_gpioirqdisable(irq); + esp_gpioirqdisable(irq); wlinfo("Attach DIO0 IRQ\n"); /* Attach to IRQ on pin connected to DIO0 */ - ret = irq_attach(irq, isr, arg); + ret = esp_gpio_irq(GPIO_SX127X_DIO0, isr, arg); if (ret < 0) { syslog(LOG_ERR, "ERROR: gpint_attach() failed: %d\n", ret); @@ -105,7 +105,7 @@ static int sx127x_irq0_attach(xcpt_t isr, void *arg) /* IRQ on rising edge */ - esp32_gpioirqenable(irq, RISING); + esp_gpioirqenable(irq); return OK; } @@ -120,12 +120,12 @@ static void sx127x_chip_reset(void) /* Configure reset as output */ - esp32_gpio_matrix_out(GPIO_SX127X_RESET, SIG_GPIO_OUT_IDX, 0, 0); - esp32_configgpio(GPIO_SX127X_RESET, OUTPUT_FUNCTION_3 | INPUT_FUNCTION_3); + esp_gpio_matrix_out(GPIO_SX127X_RESET, SIG_GPIO_OUT_IDX, 0, 0); + esp_configgpio(GPIO_SX127X_RESET, OUTPUT_FUNCTION_3 | INPUT_FUNCTION_3); /* Set pin to zero */ - esp32_gpiowrite(GPIO_SX127X_RESET, 0); + esp_gpiowrite(GPIO_SX127X_RESET, 0); /* Wait 1 ms */ @@ -133,7 +133,7 @@ static void sx127x_chip_reset(void) /* Set pin to high */ - esp32_gpiowrite(GPIO_SX127X_RESET, 1); + esp_gpiowrite(GPIO_SX127X_RESET, 1); /* Wait 10 ms */ @@ -203,7 +203,7 @@ int esp32_lpwaninitialize(void) /* Setup DIO0 */ - esp32_configgpio(GPIO_SX127X_DIO0, INPUT_FUNCTION_3 | PULLDOWN); + esp_configgpio(GPIO_SX127X_DIO0, INPUT_FUNCTION_3 | PULLDOWN | RISING); /* Init SPI bus */ diff --git a/boards/xtensa/esp32/ttgo_lora_esp32/src/esp32_userleds.c b/boards/xtensa/esp32/ttgo_lora_esp32/src/esp32_userleds.c index 09e902ae00ba4..815275cca8770 100644 --- a/boards/xtensa/esp32/ttgo_lora_esp32/src/esp32_userleds.c +++ b/boards/xtensa/esp32/ttgo_lora_esp32/src/esp32_userleds.c @@ -33,7 +33,7 @@ #include #include -#include "esp32_gpio.h" +#include "espressif/esp_gpio.h" #include "ttgo_lora_esp32.h" /**************************************************************************** @@ -61,7 +61,7 @@ uint32_t board_userled_initialize(void) for (i = 0; i < BOARD_NLEDS; i++) { - esp32_configgpio(g_ledcfg[i], OUTPUT); + esp_configgpio(g_ledcfg[i], OUTPUT); } return BOARD_NLEDS; @@ -75,7 +75,7 @@ void board_userled(int led, bool ledon) { if ((unsigned)led < BOARD_NLEDS) { - esp32_gpiowrite(g_ledcfg[led], ledon); + esp_gpiowrite(g_ledcfg[led], ledon); } } @@ -91,7 +91,6 @@ void board_userled_all(uint32_t ledset) for (i = 0; i < BOARD_NLEDS; i++) { - esp32_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); + esp_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); } } - diff --git a/boards/xtensa/esp32/ttgo_t_display_esp32/configs/lvgl_fb/defconfig b/boards/xtensa/esp32/ttgo_t_display_esp32/configs/lvgl_fb/defconfig index c942cb05432f8..0de23c07cd562 100644 --- a/boards/xtensa/esp32/ttgo_t_display_esp32/configs/lvgl_fb/defconfig +++ b/boards/xtensa/esp32/ttgo_t_display_esp32/configs/lvgl_fb/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_BOARD_TTGO_T_DISPLAY_ESP32=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/ttgo_t_display_esp32/configs/lvgl_lcd/defconfig b/boards/xtensa/esp32/ttgo_t_display_esp32/configs/lvgl_lcd/defconfig index d3b8e7f6abc8e..74b35b6b61f7e 100644 --- a/boards/xtensa/esp32/ttgo_t_display_esp32/configs/lvgl_lcd/defconfig +++ b/boards/xtensa/esp32/ttgo_t_display_esp32/configs/lvgl_lcd/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_BOARD_TTGO_T_DISPLAY_ESP32=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/ttgo_t_display_esp32/configs/nsh/defconfig b/boards/xtensa/esp32/ttgo_t_display_esp32/configs/nsh/defconfig index 30e7f150521e9..c9b204a8d92d7 100644 --- a/boards/xtensa/esp32/ttgo_t_display_esp32/configs/nsh/defconfig +++ b/boards/xtensa/esp32/ttgo_t_display_esp32/configs/nsh/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_TTGO_T_DISPLAY_ESP32=y CONFIG_ARCH_CHIP="esp32" CONFIG_ARCH_CHIP_ESP32=y CONFIG_ARCH_CHIP_ESP32WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32/ttgo_t_display_esp32/src/esp32_bringup.c b/boards/xtensa/esp32/ttgo_t_display_esp32/src/esp32_bringup.c index 66d6a2a71686e..56d660dc4bfe0 100644 --- a/boards/xtensa/esp32/ttgo_t_display_esp32/src/esp32_bringup.c +++ b/boards/xtensa/esp32/ttgo_t_display_esp32/src/esp32_bringup.c @@ -46,6 +46,8 @@ #include "espressif/esp_efuse.h" #endif #include "esp32_partition.h" +#include "espressif/esp_gpio.h" +#include "esp32_start.h" #ifdef CONFIG_USERLED # include @@ -115,16 +117,16 @@ # include "esp32_aes.h" #endif -#ifdef CONFIG_ESP32_RT_TIMER -# include "esp32_rt_timer.h" -#endif - #ifdef CONFIG_INPUT_BUTTONS # include #endif #ifdef CONFIG_RTC_DRIVER -# include "esp32_rtc_lowerhalf.h" +# include "espressif/esp_rtc.h" +#endif + +#ifdef CONFIG_ESPRESSIF_HR_TIMER +# include "espressif/esp_hr_timer.h" #endif #ifdef CONFIG_SPI_DRIVER @@ -273,14 +275,6 @@ int esp32_bringup(void) } #endif -#ifdef CONFIG_ESP32_RT_TIMER - ret = esp32_rt_timer_init(); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize RT timer: %d\n", ret); - } -#endif - #ifdef CONFIG_ESPRESSIF_WIFI_BT_COEXIST ret = esp32_wifi_bt_coexist_init(); if (ret) @@ -307,13 +301,21 @@ int esp32_bringup(void) } #endif +#ifdef CONFIG_ESPRESSIF_HR_TIMER + ret = esp_hr_timer_init(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: esp_hr_timer_init() failed: %d\n", ret); + } +#endif + /* First, register the timer drivers and let timer 1 for oneshot * if it is enabled. */ #ifdef CONFIG_TIMER -#if defined(CONFIG_ESP32_TIMER0) && !defined(CONFIG_ESP32_RT_TIMER) +#if defined(CONFIG_ESP32_TIMER0) && !defined(CONFIG_ESPRESSIF_HR_TIMER) ret = esp32_timer_initialize("/dev/timer0", TIMER0); if (ret < 0) { @@ -531,7 +533,7 @@ int esp32_bringup(void) #ifdef CONFIG_RTC_DRIVER /* Instantiate the ESP32 RTC driver */ - ret = esp32_rtc_driverinit(); + ret = esp_rtc_driverinit(); if (ret < 0) { syslog(LOG_ERR, diff --git a/boards/xtensa/esp32/ttgo_t_display_esp32/src/esp32_buttons.c b/boards/xtensa/esp32/ttgo_t_display_esp32/src/esp32_buttons.c index f8cd158c01b23..2d1459f485a24 100644 --- a/boards/xtensa/esp32/ttgo_t_display_esp32/src/esp32_buttons.c +++ b/boards/xtensa/esp32/ttgo_t_display_esp32/src/esp32_buttons.c @@ -37,7 +37,7 @@ #include #include -#include "esp32_gpio.h" +#include "espressif/esp_gpio.h" #include "ttgo_t_display_esp32.h" @@ -58,7 +58,7 @@ uint32_t board_button_initialize(void) { - esp32_configgpio(BUTTON_BOOT, INPUT_FUNCTION_3 | PULLUP); + esp_configgpio(BUTTON_BOOT, INPUT_FUNCTION_3 | PULLUP | CHANGE); return 1; } @@ -79,13 +79,13 @@ uint32_t board_buttons(void) int i = 0; int n = 0; - bool b0 = esp32_gpioread(BUTTON_BOOT); + bool b0 = esp_gpioread(BUTTON_BOOT); for (i = 0; i < 10; i++) { up_mdelay(1); /* TODO */ - bool b1 = esp32_gpioread(BUTTON_BOOT); + bool b1 = esp_gpioread(BUTTON_BOOT); if (b0 == b1) { @@ -131,38 +131,6 @@ uint32_t board_buttons(void) #ifdef CONFIG_ARCH_IRQBUTTONS int board_button_irq(int id, xcpt_t irqhandler, void *arg) { - int ret; - DEBUGASSERT(id == 0); - - int irq = ESP32_PIN2IRQ(BUTTON_BOOT); - - if (NULL != irqhandler) - { - /* Make sure the interrupt is disabled */ - - esp32_gpioirqdisable(irq); - - ret = irq_attach(irq, irqhandler, arg); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: irq_attach() failed: %d\n", ret); - return ret; - } - - gpioinfo("Attach %p\n", irqhandler); - - gpioinfo("Enabling the interrupt\n"); - - /* Configure the interrupt for rising and falling edges */ - - esp32_gpioirqenable(irq, CHANGE); - } - else - { - gpioinfo("Disable the interrupt\n"); - esp32_gpioirqdisable(irq); - } - - return OK; + return esp_gpio_irq(BUTTON_BOOT, irqhandler, arg); } #endif diff --git a/boards/xtensa/esp32/ttgo_t_display_esp32/src/esp32_gpio.c b/boards/xtensa/esp32/ttgo_t_display_esp32/src/esp32_gpio.c index d0c7492f5521e..6dcf5a3fb53d2 100644 --- a/boards/xtensa/esp32/ttgo_t_display_esp32/src/esp32_gpio.c +++ b/boards/xtensa/esp32/ttgo_t_display_esp32/src/esp32_gpio.c @@ -37,7 +37,7 @@ #include #include "ttgo_t_display_esp32.h" -#include "esp32_gpio.h" +#include "espressif/esp_gpio.h" #include "hardware/esp32_gpio_sigmap.h" #if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF) @@ -46,7 +46,7 @@ * Pre-processor Definitions ****************************************************************************/ -#if !defined(CONFIG_ESP32_GPIO_IRQ) && BOARD_NGPIOINT > 0 +#if !defined(CONFIG_ESPRESSIF_GPIO_IRQ) && BOARD_NGPIOINT > 0 # error "NGPIOINT is > 0 and GPIO interrupts aren't enabled" #endif @@ -182,7 +182,7 @@ static int gpout_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(esp32gpio->id < BOARD_NGPIOOUT); gpioinfo("Reading...\n"); - *value = esp32_gpioread(g_gpiooutputs[esp32gpio->id]); + *value = esp_gpioread(g_gpiooutputs[esp32gpio->id]); return OK; } @@ -198,7 +198,7 @@ static int gpout_write(struct gpio_dev_s *dev, bool value) DEBUGASSERT(esp32gpio->id < BOARD_NGPIOOUT); gpioinfo("Writing %d\n", (int)value); - esp32_gpiowrite(g_gpiooutputs[esp32gpio->id], value); + esp_gpiowrite(g_gpiooutputs[esp32gpio->id], value); return OK; } #endif @@ -216,7 +216,7 @@ static int gpin_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(esp32gpio->id < BOARD_NGPIOIN); gpioinfo("Reading... pin %" PRIu32 "\n", g_gpioinputs[esp32gpio->id]); - *value = esp32_gpioread(g_gpioinputs[esp32gpio->id]); + *value = esp_gpioread(g_gpioinputs[esp32gpio->id]); return OK; } #endif @@ -252,7 +252,7 @@ static int gpint_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(esp32gpint->esp32gpio.id < BOARD_NGPIOINT); gpioinfo("Reading int pin...\n"); - *value = esp32_gpioread(g_gpiointinputs[esp32gpint->esp32gpio.id]); + *value = esp_gpioread(g_gpiointinputs[esp32gpint->esp32gpio.id]); return OK; } @@ -265,23 +265,26 @@ static int gpint_attach(struct gpio_dev_s *dev, { struct esp32gpint_dev_s *esp32gpint = (struct esp32gpint_dev_s *)dev; - int irq = ESP32_PIN2IRQ(g_gpiointinputs[esp32gpint->esp32gpio.id]); int ret; gpioinfo("Attaching the callback\n"); /* Make sure the interrupt is disabled */ - esp32_gpioirqdisable(irq); - ret = irq_attach(irq, - esp32gpio_interrupt, - &g_gpint[esp32gpint->esp32gpio.id]); + esp_gpioirqdisable(g_gpiointinputs[esp32gpint->esp32gpio.id]); + + ret = esp_gpio_irq(g_gpiointinputs[esp32gpint->esp32gpio.id], + esp32gpio_interrupt, + &g_gpint[esp32gpint->esp32gpio.id]); if (ret < 0) { - syslog(LOG_ERR, "ERROR: gpint_attach() failed: %d\n", ret); return ret; } + /* Make sure the interrupt is disabled */ + + esp_gpioirqdisable(g_gpiointinputs[esp32gpint->esp32gpio.id]); + gpioinfo("Attach %p\n", callback); esp32gpint->callback = callback; return OK; @@ -295,7 +298,6 @@ static int gpint_enable(struct gpio_dev_s *dev, bool enable) { struct esp32gpint_dev_s *esp32gpint = (struct esp32gpint_dev_s *)dev; - int irq = ESP32_PIN2IRQ(g_gpiointinputs[esp32gpint->esp32gpio.id]); if (enable) { @@ -305,13 +307,13 @@ static int gpint_enable(struct gpio_dev_s *dev, bool enable) /* Configure the interrupt for rising edge */ - esp32_gpioirqenable(irq, RISING); + esp_gpioirqenable(g_gpiointinputs[esp32gpint->esp32gpio.id]); } } else { gpioinfo("Disable the interrupt\n"); - esp32_gpioirqdisable(irq); + esp_gpioirqdisable(g_gpiointinputs[esp32gpint->esp32gpio.id]); } return OK; @@ -343,10 +345,9 @@ int esp32_gpio_init(void) /* Configure the pins that will be used as output */ - esp32_gpio_matrix_out(g_gpiooutputs[i], SIG_GPIO_OUT_IDX, 0, 0); - esp32_configgpio(g_gpiooutputs[i], OUTPUT_FUNCTION_3 | - INPUT_FUNCTION_3); - esp32_gpiowrite(g_gpiooutputs[i], 0); + esp_gpio_matrix_out(g_gpiooutputs[i], SIG_GPIO_OUT_IDX, 0, 0); + esp_configgpio(g_gpiooutputs[i], OUTPUT_FUNCTION_3 | INPUT_FUNCTION_3); + esp_gpiowrite(g_gpiooutputs[i], 0); pincount++; } @@ -364,7 +365,7 @@ int esp32_gpio_init(void) /* Configure the pins that will be used as INPUT */ - esp32_configgpio(g_gpioinputs[i], INPUT_FUNCTION_3); + esp_configgpio(g_gpioinputs[i], INPUT_FUNCTION_3 | PULLDOWN); pincount++; } @@ -382,7 +383,8 @@ int esp32_gpio_init(void) /* Configure the pins that will be used as interrupt input */ - esp32_configgpio(g_gpiointinputs[i], INPUT_FUNCTION_3 | PULLDOWN); + esp_configgpio(g_gpiointinputs[i], + INPUT_FUNCTION_3 | PULLUP | FALLING); pincount++; } diff --git a/boards/xtensa/esp32/ttgo_t_display_esp32/src/esp32_userleds.c b/boards/xtensa/esp32/ttgo_t_display_esp32/src/esp32_userleds.c index f1f62a92f9a03..f1a39ba3db677 100644 --- a/boards/xtensa/esp32/ttgo_t_display_esp32/src/esp32_userleds.c +++ b/boards/xtensa/esp32/ttgo_t_display_esp32/src/esp32_userleds.c @@ -33,7 +33,7 @@ #include #include -#include "esp32_gpio.h" +#include "espressif/esp_gpio.h" #include "ttgo_t_display_esp32.h" /**************************************************************************** @@ -61,7 +61,7 @@ uint32_t board_userled_initialize(void) for (i = 0; i < BOARD_NLEDS; i++) { - esp32_configgpio(g_ledcfg[i], OUTPUT); + esp_configgpio(g_ledcfg[i], OUTPUT); } return BOARD_NLEDS; @@ -75,7 +75,7 @@ void board_userled(int led, bool ledon) { if ((unsigned)led < BOARD_NLEDS) { - esp32_gpiowrite(g_ledcfg[led], ledon); + esp_gpiowrite(g_ledcfg[led], ledon); } } @@ -91,7 +91,6 @@ void board_userled_all(uint32_t ledset) for (i = 0; i < BOARD_NLEDS; i++) { - esp32_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); + esp_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); } } - diff --git a/boards/xtensa/esp32s2/common/include/esp32s2_board_rmt.h b/boards/xtensa/esp32s2/common/include/esp32s2_board_rmt.h index 74ce7b8bb367f..467c94c5b6b18 100644 --- a/boards/xtensa/esp32s2/common/include/esp32s2_board_rmt.h +++ b/boards/xtensa/esp32s2/common/include/esp32s2_board_rmt.h @@ -61,7 +61,6 @@ extern "C" * Initialize the RMT peripheral and register an RX device. * * Input Parameters: - * ch - The RMT's channel that will be used * pin - The pin used for the RX channel * * Returned Value: @@ -69,7 +68,7 @@ extern "C" * ****************************************************************************/ -int board_rmt_rxinitialize(int ch, int pin); +int board_rmt_rxinitialize(int pin); /**************************************************************************** * Name: board_rmt_txinitialize @@ -78,7 +77,6 @@ int board_rmt_rxinitialize(int ch, int pin); * Initialize the RMT peripheral and register an TX device. * * Input Parameters: - * ch - The RMT's channel that will be used * pin - The pin used for the TX channel * * Returned Value: @@ -86,7 +84,7 @@ int board_rmt_rxinitialize(int ch, int pin); * ****************************************************************************/ -int board_rmt_txinitialize(int ch, int pin); +int board_rmt_txinitialize(int pin); #endif /* CONFIG_ESP_RMT */ diff --git a/boards/xtensa/esp32s2/common/scripts/esp32s2_sections.ld b/boards/xtensa/esp32s2/common/scripts/esp32s2_sections.ld index 59b70e6ecb305..5862b2ca5f984 100644 --- a/boards/xtensa/esp32s2/common/scripts/esp32s2_sections.ld +++ b/boards/xtensa/esp32s2/common/scripts/esp32s2_sections.ld @@ -170,6 +170,7 @@ SECTIONS *libarch.a:*clk.*(.text .text.* .literal .literal.*) *libarch.a:*efuse_hal.*(.literal.is_eco0 .text.is_eco0) *libarch.a:*efuse_hal.*(.text .text.* .literal .literal.*) + *libarch.a:*efuse_utility.*(.text .text.* .literal .literal.*) *libarch.a:*esp_clk.*(.text .text.* .literal .literal.*) *libarch.a:*esp_clk_tree.*(.text .text.* .literal .literal.*) *libarch.a:*esp_clk_tree_common.*(.text .text.* .literal .literal.*) @@ -238,11 +239,26 @@ SECTIONS *libarch.a:spi_flash_os_func_noos.*(.literal .literal.* .text .text.*) *libarch.a:spi_flash_os_func_app.*(.literal .literal.* .text .text.*) *libarch.a:flash_brownout_hook.*(.literal .literal.* .text .text.*) - *libarch.a:esp_cache.*(.literal .literal.* .text .text.*) + *libarch.a:esp_cache_utils.*(.literal .literal.* .text .text.*) *libarch.a:cache_utils.*(.literal .literal.* .text .text.*) *libarch.a:memspi_host_driver.*(.literal .literal.* .text .text.*) + *libarch.a:critical_section.*(.literal .literal.* .text .text.*) + *libarch.a:os.*(.literal.nuttx_enter_critical .text.nuttx_enter_critical) + *libarch.a:os.*(.literal.nuttx_exit_critical .text.nuttx_exit_critical) + *libarch.a:esp_irq.*(.literal .literal.* .text .text.*) + *libarch.a:esp_xtensa_intr.*(.literal .literal.* .text .text.*) + *libarch.a:intr_alloc.*(.literal .literal.* .text .text.*) + *libarch.a:xtensa_intr.*(.literal .literal.* .text .text.*) + *libarch.a:*sleep_modes.*(.literal.esp_sleep_sub_mode_force_disable* .text.esp_sleep_sub_mode_force_disable*) + *libarch.a:intr_alloc.*(.literal.esp_intr_get_intno .text.esp_intr_get_intno) + *libarch.a:intr_alloc.*(.literal.esp_intr_get_cpu .text.esp_intr_get_cpu) + *libarch.a:interrupt.*(.literal.intr_handler_get .text.intr_handler_get) + *libarch.a:interrupt.*(.literal.intr_handler_get_arg .text.intr_handler_get_arg) + *libarch.a:interrupt.*(.literal.intr_get_item .text.intr_get_item) + *libarch.a:interrupt.*(.literal.intr_handler_get_arg .text.intr_handler_get_arg) *libc.a:sq_remlast.*(.literal .text .literal.* .text.*) + *libc.a:arch_atomic.*(.text .text.* .literal .literal.*) *libsched.a:irq_dispatch.*(.text .text.* .literal .literal.*) *libsched.a:sched_lock.*(.text .text.* .literal .literal.*) @@ -390,6 +406,7 @@ SECTIONS *libarch.a:*esp_rom_cache_esp32s2_esp32s3.*(.rodata .rodata.*) *libarch.a:*esp_rom_wdt.*(.rodata .rodata.*) *libarch.a:*efuse_hal.*(.rodata .rodata.*) + *libarch.a:*efuse_utility.*(.rodata .rodata.*) *libarch.a:*log.*(.rodata .rodata.*) *libarch.a:*log_noos.*(.rodata .rodata.*) *libarch.a:*cpu_region_protect.*(.rodata .rodata.*) @@ -404,14 +421,23 @@ SECTIONS *libarch.a:spi_flash_os_func_noos.*(.rodata .rodata.*) *libarch.a:spi_flash_os_func_app.*(.rodata .rodata.*) *libarch.a:flash_brownout_hook.*(.rodata .rodata.*) - *libarch.a:esp_cache.*(.rodata .rodata.*) + *libarch.a:esp_cache_utils.*(.rodata .rodata.*) *libarch.a:cache_utils.*(.rodata .rodata.*) *libarch.a:memspi_host_driver.*(.rodata .rodata.*) + *libarch.a:critical_section.*(.rodata .rodata.*) + *libarch.a:os.*(.rodata.g_int_flags_count .rodata.g_int_flags) + *libarch.a:esp_irq.*(.rodata .rodata.*) + *libarch.a:esp_xtensa_intr.*(.rodata .rodata.*) + *libarch.a:intr_alloc.*(.rodata .rodata.*) + *libarch.a:xtensa_intr.*(.rodata .rodata.*) + *libarch.a:*sleep_modes.*(.rodata.esp_sleep_sub_mode_force_disable*) *libsched.a:irq_dispatch.*(.rodata .rodata.*) *libsched.a:sched_lock.*(.rodata .rodata.*) *libsched.a:sched_unlock.*(.rodata .rodata.*) + *libc.a:arch_atomic.*(.rodata .rodata.*) + . = ALIGN(4); _edata = ABSOLUTE(.); _data_end = ABSOLUTE(.); @@ -526,9 +552,7 @@ SECTIONS . = ALIGN(4); _sinit = ABSOLUTE(.); - __init_array_start = ABSOLUTE(.); KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .ctors SORT(.ctors.*))) - __init_array_end = ABSOLUTE(.); _einit = ABSOLUTE(.); /* Addresses of memory regions reserved via SOC_RESERVE_MEMORY_REGION() */ @@ -626,12 +650,14 @@ SECTIONS { *(.rtc.bss) *(.rtc.bss*) + } >rtc_slow_seg .rtc.data : { . = ALIGN(4); _rtc_data_start = ABSOLUTE(.); + *(.rtc.force_slow .rtc.force_slow.*) *(.rtc.data) *(.rtc.data.*) *(.rtc.rodata) diff --git a/boards/xtensa/esp32s2/common/scripts/flat_memory.ld b/boards/xtensa/esp32s2/common/scripts/flat_memory.ld index db611a754de65..13154a589ee8f 100644 --- a/boards/xtensa/esp32s2/common/scripts/flat_memory.ld +++ b/boards/xtensa/esp32s2/common/scripts/flat_memory.ld @@ -36,8 +36,8 @@ #define RAM_IRAM_START 0x40020000 #define RAM_DRAM_START 0x3ffb0000 -#define DATA_RAM_END 0x3ffe0000 /* 2nd stage bootloader iram_loader_seg - * starts at SRAM block 14 (reclaimed +#define DATA_RAM_END 0x3ffde000 /* 2nd stage bootloader iram_loader_seg + * starts at SRAM block 13 (reclaimed * after app boots) */ diff --git a/boards/xtensa/esp32s2/common/scripts/mcuboot_sections.ld b/boards/xtensa/esp32s2/common/scripts/mcuboot_sections.ld index 719cec04fa5e0..78884493a487e 100644 --- a/boards/xtensa/esp32s2/common/scripts/mcuboot_sections.ld +++ b/boards/xtensa/esp32s2/common/scripts/mcuboot_sections.ld @@ -181,6 +181,7 @@ SECTIONS *libarch.a:*mmu_hal.*(.text .text.* .literal .literal.*) *libc.a:sq_remlast.*(.literal .text .literal.* .text.*) + *libc.a:arch_atomic.*(.literal .text .literal.* .text.*) /* align + add 16B for CPU dummy speculative instr. fetch */ @@ -262,6 +263,8 @@ SECTIONS *libarch.a:*mpu_hal.*(.rodata .rodata.*) *libarch.a:*mmu_hal.*(.rodata .rodata.*) + *libc.a:arch_atomic.*(.rodata .rodata.*) + _edata = ABSOLUTE(.); . = ALIGN(4); diff --git a/boards/xtensa/esp32s2/common/src/esp32s2_board_rmt.c b/boards/xtensa/esp32s2/common/src/esp32s2_board_rmt.c index 2ee824292a442..5b06382a57913 100644 --- a/boards/xtensa/esp32s2/common/src/esp32s2_board_rmt.c +++ b/boards/xtensa/esp32s2/common/src/esp32s2_board_rmt.c @@ -79,7 +79,6 @@ * Initialize the RMT peripheral and register an RX device. * * Input Parameters: - * ch - The RMT's channel that will be used * pin - The pin used for the RX channel * * Returned Value: @@ -87,11 +86,17 @@ * ****************************************************************************/ -int board_rmt_rxinitialize(int ch, int pin) +int board_rmt_rxinitialize(int pin) { int ret; + struct rmt_dev_s *rmt; - struct rmt_dev_s *rmt = esp_rmt_rx_init(ch, pin); + rmt = esp_rmt_rx_init(pin); + if (rmt == NULL) + { + rmterr("ERROR: esp_rmt_rx_init failed\n"); + return -ENODEV; + } ret = rmtchar_register(rmt); if (ret < 0) @@ -110,7 +115,6 @@ int board_rmt_rxinitialize(int ch, int pin) * Initialize the RMT peripheral and register an TX device. * * Input Parameters: - * ch - The RMT's channel that will be used * pin - The pin used for the TX channel * * Returned Value: @@ -118,7 +122,7 @@ int board_rmt_rxinitialize(int ch, int pin) * ****************************************************************************/ -int board_rmt_txinitialize(int ch, int pin) +int board_rmt_txinitialize(int pin) { int ret; struct rmt_dev_s *rmt; @@ -126,7 +130,7 @@ int board_rmt_txinitialize(int ch, int pin) struct ws2812_dev_s *led; #endif - rmt = esp_rmt_tx_init(ch, pin); + rmt = esp_rmt_tx_init(pin); if (rmt == NULL) { rmterr("ERROR: esp_rmt_tx_init failed\n"); diff --git a/boards/xtensa/esp32s2/common/src/esp32s2_board_spi.c b/boards/xtensa/esp32s2/common/src/esp32s2_board_spi.c index ed1292768fa86..4867cab762802 100644 --- a/boards/xtensa/esp32s2/common/src/esp32s2_board_spi.c +++ b/boards/xtensa/esp32s2/common/src/esp32s2_board_spi.c @@ -32,7 +32,7 @@ #include -#include "esp32s2_gpio.h" +#include "espressif/esp_gpio.h" /**************************************************************************** * Private Functions @@ -76,7 +76,7 @@ int esp32s2_spi2_cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) * data bits are data or a command. */ - esp32s2_gpiowrite(CONFIG_ESP32S2_SPI2_MISOPIN, !cmd); + esp_gpiowrite(CONFIG_ESP32S2_SPI2_MISOPIN, !cmd); return OK; } @@ -123,7 +123,7 @@ int esp32s2_spi3_cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) * data bits are data or a command. */ - esp32s2_gpiowrite(CONFIG_ESP32S2_SPI3_MISOPIN, !cmd); + esp_gpiowrite(CONFIG_ESP32S2_SPI3_MISOPIN, !cmd); return OK; } diff --git a/boards/xtensa/esp32s2/common/src/esp32s2_board_spiflash.c b/boards/xtensa/esp32s2/common/src/esp32s2_board_spiflash.c index bc8b505587d84..fef13ab3e6195 100644 --- a/boards/xtensa/esp32s2/common/src/esp32s2_board_spiflash.c +++ b/boards/xtensa/esp32s2/common/src/esp32s2_board_spiflash.c @@ -114,8 +114,9 @@ static int init_ota_partitions(void) { struct mtd_dev_s *mtd; int ret = OK; + int i; - for (int i = 0; i < nitems(g_ota_partition_table); ++i) + for (i = 0; i < nitems(g_ota_partition_table); ++i) { const struct partition_s *part = &g_ota_partition_table[i]; mtd = esp_spiflash_alloc_mtdpart(part->firstblock, part->blocksize); @@ -428,12 +429,6 @@ int board_spiflash_init(void) { int ret = OK; - ret = esp_spiflash_init(); - if (ret < 0) - { - return ret; - } - #ifdef CONFIG_ESPRESSIF_HAVE_OTA_PARTITION ret = init_ota_partitions(); if (ret < 0) diff --git a/boards/xtensa/esp32s2/common/src/esp32s2_board_wdt.c b/boards/xtensa/esp32s2/common/src/esp32s2_board_wdt.c index f008e234aa931..9372694366c13 100644 --- a/boards/xtensa/esp32s2/common/src/esp32s2_board_wdt.c +++ b/boards/xtensa/esp32s2/common/src/esp32s2_board_wdt.c @@ -31,7 +31,6 @@ #include "esp32s2_board_wdt.h" #include "esp32s2_wdt_lowerhalf.h" -#include "esp32s2_wdt.h" /**************************************************************************** * Pre-processor Definitions diff --git a/boards/xtensa/esp32s2/common/src/esp32s2_ili9341.c b/boards/xtensa/esp32s2/common/src/esp32s2_ili9341.c index 59b16328e3fbd..2f3e5cc388460 100644 --- a/boards/xtensa/esp32s2/common/src/esp32s2_ili9341.c +++ b/boards/xtensa/esp32s2/common/src/esp32s2_ili9341.c @@ -40,7 +40,7 @@ #include -#include "esp32s2_gpio.h" +#include "espressif/esp_gpio.h" #include "esp32s2_spi.h" #include "hardware/esp32s2_gpio_sigmap.h" @@ -371,21 +371,21 @@ int board_lcd_initialize(void) /* Initialize non-SPI GPIOs */ - esp32s2_configgpio(GPIO_LCD_DC, OUTPUT_FUNCTION_3); - esp32s2_gpio_matrix_out(GPIO_LCD_DC, SIG_GPIO_OUT_IDX, 0, 0); + esp_configgpio(GPIO_LCD_DC, OUTPUT_FUNCTION_3); + esp_gpio_matrix_out(GPIO_LCD_DC, SIG_GPIO_OUT_IDX, 0, 0); - esp32s2_configgpio(GPIO_LCD_RST, INPUT_FUNCTION_3); - esp32s2_gpio_matrix_out(GPIO_LCD_RST, SIG_GPIO_OUT_IDX, 0, 0); + esp_configgpio(GPIO_LCD_RST, INPUT_FUNCTION_3); + esp_gpio_matrix_out(GPIO_LCD_RST, SIG_GPIO_OUT_IDX, 0, 0); - esp32s2_configgpio(GPIO_LCD_BCKL, OUTPUT_FUNCTION_3); - esp32s2_gpio_matrix_out(GPIO_LCD_BCKL, SIG_GPIO_OUT_IDX, 0, 0); + esp_configgpio(GPIO_LCD_BCKL, OUTPUT_FUNCTION_3); + esp_gpio_matrix_out(GPIO_LCD_BCKL, SIG_GPIO_OUT_IDX, 0, 0); /* Reset ILI9341 */ up_mdelay(10); - esp32s2_gpiowrite(GPIO_LCD_RST, false); + esp_gpiowrite(GPIO_LCD_RST, false); up_mdelay(10); - esp32s2_gpiowrite(GPIO_LCD_RST, true); + esp_gpiowrite(GPIO_LCD_RST, true); up_mdelay(50); /* Configure SPI */ diff --git a/boards/xtensa/esp32s2/common/src/esp32s2_st7789.c b/boards/xtensa/esp32s2/common/src/esp32s2_st7789.c index 803955ed67c52..7159b79fb84d1 100644 --- a/boards/xtensa/esp32s2/common/src/esp32s2_st7789.c +++ b/boards/xtensa/esp32s2/common/src/esp32s2_st7789.c @@ -40,7 +40,7 @@ #include #include "esp32s2_spi.h" -#include "esp32s2_gpio.h" +#include "espressif/esp_gpio.h" /**************************************************************************** * Pre-processor Definitions @@ -86,21 +86,21 @@ int board_lcd_initialize(void) /* SPI RX is not used. Same pin is used as LCD Data/Command control */ - esp32s2_configgpio(GPIO_LCD_DC, OUTPUT); - esp32s2_gpiowrite(GPIO_LCD_DC, true); + esp_configgpio(GPIO_LCD_DC, OUTPUT); + esp_gpiowrite(GPIO_LCD_DC, true); /* Pull LCD_RESET high */ - esp32s2_configgpio(GPIO_LCD_RST, OUTPUT); - esp32s2_gpiowrite(GPIO_LCD_RST, false); + esp_configgpio(GPIO_LCD_RST, OUTPUT); + esp_gpiowrite(GPIO_LCD_RST, false); up_mdelay(1); - esp32s2_gpiowrite(GPIO_LCD_RST, true); + esp_gpiowrite(GPIO_LCD_RST, true); up_mdelay(10); /* Set full brightness */ - esp32s2_configgpio(GPIO_LCD_BCKL, OUTPUT); - esp32s2_gpiowrite(GPIO_LCD_BCKL, true); + esp_configgpio(GPIO_LCD_BCKL, OUTPUT); + esp_gpiowrite(GPIO_LCD_BCKL, true); lcdinfo("LCD successfully initialized"); diff --git a/boards/xtensa/esp32s2/esp32s2-kaluga-1/configs/audio/defconfig b/boards/xtensa/esp32s2/esp32s2-kaluga-1/configs/audio/defconfig index 878454eebff05..093d58e7edd7e 100644 --- a/boards/xtensa/esp32s2/esp32s2-kaluga-1/configs/audio/defconfig +++ b/boards/xtensa/esp32s2/esp32s2-kaluga-1/configs/audio/defconfig @@ -17,6 +17,9 @@ CONFIG_ARCH_BOARD_ESP32S2_KALUGA_1=y CONFIG_ARCH_CHIP="esp32s2" CONFIG_ARCH_CHIP_ESP32S2=y CONFIG_ARCH_CHIP_ESP32S2WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_AUDIO=y diff --git a/boards/xtensa/esp32s2/esp32s2-kaluga-1/configs/buttons/defconfig b/boards/xtensa/esp32s2/esp32s2-kaluga-1/configs/buttons/defconfig index 27bfff6051f5e..e7175324aa306 100644 --- a/boards/xtensa/esp32s2/esp32s2-kaluga-1/configs/buttons/defconfig +++ b/boards/xtensa/esp32s2/esp32s2-kaluga-1/configs/buttons/defconfig @@ -17,14 +17,17 @@ CONFIG_ARCH_CHIP="esp32s2" CONFIG_ARCH_CHIP_ESP32S2=y CONFIG_ARCH_CHIP_ESP32S2WROVER=y CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y -CONFIG_ESP32S2_GPIO_IRQ=y CONFIG_ESP32S2_TOUCH=y CONFIG_ESP32S2_TOUCH_IRQ=y CONFIG_ESP32S2_UART0=y +CONFIG_ESPRESSIF_GPIO_IRQ=y CONFIG_EXAMPLES_BUTTONS=y CONFIG_FS_PROCFS=y CONFIG_HAVE_CXX=y diff --git a/boards/xtensa/esp32s2/esp32s2-kaluga-1/configs/i2c/defconfig b/boards/xtensa/esp32s2/esp32s2-kaluga-1/configs/i2c/defconfig index b814f66408764..90f498d9c6260 100644 --- a/boards/xtensa/esp32s2/esp32s2-kaluga-1/configs/i2c/defconfig +++ b/boards/xtensa/esp32s2/esp32s2-kaluga-1/configs/i2c/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_BOARD_ESP32S2_KALUGA_1=y CONFIG_ARCH_CHIP="esp32s2" CONFIG_ARCH_CHIP_ESP32S2=y CONFIG_ARCH_CHIP_ESP32S2WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s2/esp32s2-kaluga-1/configs/lvgl_ili9341/defconfig b/boards/xtensa/esp32s2/esp32s2-kaluga-1/configs/lvgl_ili9341/defconfig index 24d84ab7e42ea..f2c96f04839ac 100644 --- a/boards/xtensa/esp32s2/esp32s2-kaluga-1/configs/lvgl_ili9341/defconfig +++ b/boards/xtensa/esp32s2/esp32s2-kaluga-1/configs/lvgl_ili9341/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_BOARD_ESP32S2_KALUGA_1=y CONFIG_ARCH_CHIP="esp32s2" CONFIG_ARCH_CHIP_ESP32S2=y CONFIG_ARCH_CHIP_ESP32S2WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s2/esp32s2-kaluga-1/configs/lvgl_st7789/defconfig b/boards/xtensa/esp32s2/esp32s2-kaluga-1/configs/lvgl_st7789/defconfig index e9cb44af20fa2..579724d5b9018 100644 --- a/boards/xtensa/esp32s2/esp32s2-kaluga-1/configs/lvgl_st7789/defconfig +++ b/boards/xtensa/esp32s2/esp32s2-kaluga-1/configs/lvgl_st7789/defconfig @@ -17,6 +17,9 @@ CONFIG_ARCH_BOARD_ESP32S2_KALUGA_1=y CONFIG_ARCH_CHIP="esp32s2" CONFIG_ARCH_CHIP_ESP32S2=y CONFIG_ARCH_CHIP_ESP32S2WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s2/esp32s2-kaluga-1/configs/nsh/defconfig b/boards/xtensa/esp32s2/esp32s2-kaluga-1/configs/nsh/defconfig index 568c0176a42c2..b425cee3f3398 100644 --- a/boards/xtensa/esp32s2/esp32s2-kaluga-1/configs/nsh/defconfig +++ b/boards/xtensa/esp32s2/esp32s2-kaluga-1/configs/nsh/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32S2_KALUGA_1=y CONFIG_ARCH_CHIP="esp32s2" CONFIG_ARCH_CHIP_ESP32S2=y CONFIG_ARCH_CHIP_ESP32S2WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s2/esp32s2-kaluga-1/configs/nxlooper/defconfig b/boards/xtensa/esp32s2/esp32s2-kaluga-1/configs/nxlooper/defconfig index 17ac1d91ecd16..128b1af6510ad 100644 --- a/boards/xtensa/esp32s2/esp32s2-kaluga-1/configs/nxlooper/defconfig +++ b/boards/xtensa/esp32s2/esp32s2-kaluga-1/configs/nxlooper/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_BOARD_ESP32S2_KALUGA_1=y CONFIG_ARCH_CHIP="esp32s2" CONFIG_ARCH_CHIP_ESP32S2=y CONFIG_ARCH_CHIP_ESP32S2WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_AUDIO=y diff --git a/boards/xtensa/esp32s2/esp32s2-kaluga-1/configs/rtc/defconfig b/boards/xtensa/esp32s2/esp32s2-kaluga-1/configs/rtc/defconfig index 17dae9e97d992..da61c4fddd1af 100644 --- a/boards/xtensa/esp32s2/esp32s2-kaluga-1/configs/rtc/defconfig +++ b/boards/xtensa/esp32s2/esp32s2-kaluga-1/configs/rtc/defconfig @@ -15,11 +15,13 @@ CONFIG_ARCH_BOARD_ESP32S2_KALUGA_1=y CONFIG_ARCH_CHIP="esp32s2" CONFIG_ARCH_CHIP_ESP32S2=y CONFIG_ARCH_CHIP_ESP32S2WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y -CONFIG_ESP32S2_RT_TIMER=y CONFIG_ESP32S2_UART0=y CONFIG_EXAMPLES_ALARM=y CONFIG_FS_PROCFS=y diff --git a/boards/xtensa/esp32s2/esp32s2-kaluga-1/configs/twai/defconfig b/boards/xtensa/esp32s2/esp32s2-kaluga-1/configs/twai/defconfig index d46219bd1237f..5062ef7ae3df0 100644 --- a/boards/xtensa/esp32s2/esp32s2-kaluga-1/configs/twai/defconfig +++ b/boards/xtensa/esp32s2/esp32s2-kaluga-1/configs/twai/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32S2_KALUGA_1=y CONFIG_ARCH_CHIP="esp32s2" CONFIG_ARCH_CHIP_ESP32S2=y CONFIG_ARCH_CHIP_ESP32S2WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s2/esp32s2-kaluga-1/configs/watchdog/defconfig b/boards/xtensa/esp32s2/esp32s2-kaluga-1/configs/watchdog/defconfig index ee7b3b5113452..f017f5dcc48ce 100644 --- a/boards/xtensa/esp32s2/esp32s2-kaluga-1/configs/watchdog/defconfig +++ b/boards/xtensa/esp32s2/esp32s2-kaluga-1/configs/watchdog/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32S2_KALUGA_1=y CONFIG_ARCH_CHIP="esp32s2" CONFIG_ARCH_CHIP_ESP32S2=y CONFIG_ARCH_CHIP_ESP32S2WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s2/esp32s2-kaluga-1/src/esp32s2_bringup.c b/boards/xtensa/esp32s2/esp32s2-kaluga-1/src/esp32s2_bringup.c index 5309e3abe7226..6b003767c8411 100644 --- a/boards/xtensa/esp32s2/esp32s2-kaluga-1/src/esp32s2_bringup.c +++ b/boards/xtensa/esp32s2/esp32s2-kaluga-1/src/esp32s2_bringup.c @@ -39,7 +39,8 @@ #include #include -#include "esp32s2_gpio.h" +#include "espressif/esp_gpio.h" +#include "esp32s2_start.h" #ifdef CONFIG_USERLED # include @@ -61,10 +62,6 @@ # include "espressif/esp_i2s.h" #endif -#ifdef CONFIG_ESP32S2_RT_TIMER -# include "esp32s2_rt_timer.h" -#endif - #ifdef CONFIG_WATCHDOG # include "esp32s2_board_wdt.h" #endif @@ -85,7 +82,11 @@ #endif #ifdef CONFIG_RTC_DRIVER -# include "esp32s2_rtc_lowerhalf.h" +# include "espressif/esp_rtc.h" +#endif + +#ifdef CONFIG_ESPRESSIF_HR_TIMER +# include "espressif/esp_hr_timer.h" #endif #include "esp32s2-kaluga-1.h" @@ -179,6 +180,14 @@ int esp32s2_bringup(void) } #endif +#ifdef CONFIG_ESPRESSIF_HR_TIMER + ret = esp_hr_timer_init(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: esp_hr_timer_init() failed: %d\n", ret); + } +#endif + /* Register the timer drivers */ #ifdef CONFIG_TIMER @@ -229,14 +238,6 @@ int esp32s2_bringup(void) #endif /* CONFIG_TIMER */ -#ifdef CONFIG_ESP32S2_RT_TIMER - ret = esp32s2_rt_timer_init(); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize RT timer: %d\n", ret); - } - -#endif /* Now register one oneshot driver */ #if defined(CONFIG_ONESHOT) && defined(CONFIG_ESP32S2_TIMER0) @@ -302,8 +303,8 @@ int esp32s2_bringup(void) /* Configure ES8311 audio on I2C0 and I2S0 */ - esp32s2_configgpio(SPEAKER_ENABLE_GPIO, OUTPUT); - esp32s2_gpiowrite(SPEAKER_ENABLE_GPIO, true); + esp_configgpio(SPEAKER_ENABLE_GPIO, OUTPUT); + esp_gpiowrite(SPEAKER_ENABLE_GPIO, true); ret = esp32s2_es8311_initialize(ESP32S2_I2C0, ES8311_I2C_ADDR, ES8311_I2C_FREQ); @@ -319,7 +320,7 @@ int esp32s2_bringup(void) #ifdef CONFIG_RTC_DRIVER /* Instantiate the ESP32 RTC driver */ - ret = esp32s2_rtc_driverinit(); + ret = esp_rtc_driverinit(); if (ret < 0) { syslog(LOG_ERR, diff --git a/boards/xtensa/esp32s2/esp32s2-kaluga-1/src/esp32s2_buttons.c b/boards/xtensa/esp32s2/esp32s2-kaluga-1/src/esp32s2_buttons.c index 37b0b7b6fbe67..9769e6c5070ed 100644 --- a/boards/xtensa/esp32s2/esp32s2-kaluga-1/src/esp32s2_buttons.c +++ b/boards/xtensa/esp32s2/esp32s2-kaluga-1/src/esp32s2_buttons.c @@ -39,7 +39,7 @@ #include #include -#include "esp32s2_gpio.h" +#include "espressif/esp_gpio.h" #include "esp32s2_touch.h" #include "esp32s2-kaluga-1.h" @@ -175,7 +175,7 @@ uint32_t board_button_initialize(void) esp32s2_touchsetthreshold(TP_VOLDN_CHANNEL, TOUCHPAD_THRESHOLD); #endif - esp32s2_configgpio(BUTTON_BOOT, INPUT_FUNCTION_3 | PULLUP); + esp_configgpio(BUTTON_BOOT, INPUT_FUNCTION_3 | PULLUP); return NUM_BUTTONS; } @@ -211,13 +211,14 @@ uint32_t board_buttons(void) } else { - b0 = esp32s2_gpioread(button_info.input.gpio); + int i; + b0 = esp_gpioread(button_info.input.gpio); - for (int i = 0; i < 10; i++) + for (i = 0; i < 10; i++) { up_mdelay(1); - b1 = esp32s2_gpioread(button_info.input.gpio); + b1 = esp_gpioread(button_info.input.gpio); if (b0 == b1) { @@ -282,11 +283,11 @@ int board_button_irq(int id, xcpt_t irqhandler, void *arg) esp32s2_touchirqdisable(irq); - esp32s2_touchregisterreleasecb(irqhandler); - ret = irq_attach(irq, irqhandler, arg); + ret = esp32s2_touchirqattach(irq, irqhandler, arg); if (ret < 0) { - syslog(LOG_ERR, "ERROR: irq_attach() failed: %d\n", ret); + syslog(LOG_ERR, "ERROR: esp32_touchirqattach() failed: %d\n", + ret); return ret; } @@ -307,37 +308,7 @@ int board_button_irq(int id, xcpt_t irqhandler, void *arg) else #endif { - int pin = button_info.input.gpio; - int irq = ESP32S2_PIN2IRQ(pin); - - if (NULL != irqhandler) - { - /* Make sure the interrupt is disabled */ - - esp32s2_gpioirqdisable(irq); - - ret = irq_attach(irq, irqhandler, arg); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: irq_attach() failed: %d\n", ret); - return ret; - } - - gpioinfo("Attach %p to pin %d\n", irqhandler, pin); - - gpioinfo("Enabling the interrupt\n"); - - /* Configure the interrupt for rising and falling edges */ - - esp32s2_gpioirqenable(irq, CHANGE); - } - else - { - gpioinfo("Disabled interrupts from pin %d\n", pin); - esp32s2_gpioirqdisable(irq); - } - - return OK; + return esp_gpio_irq(button_info.input.gpio, irqhandler, arg); } } #endif diff --git a/boards/xtensa/esp32s2/esp32s2-kaluga-1/src/esp32s2_gpio.c b/boards/xtensa/esp32s2/esp32s2-kaluga-1/src/esp32s2_gpio.c index da4ffd63db8b4..90191c2099bc4 100644 --- a/boards/xtensa/esp32s2/esp32s2-kaluga-1/src/esp32s2_gpio.c +++ b/boards/xtensa/esp32s2/esp32s2-kaluga-1/src/esp32s2_gpio.c @@ -39,7 +39,7 @@ #include #include "esp32s2-kaluga-1.h" -#include "esp32s2_gpio.h" +#include "espressif/esp_gpio.h" #include "hardware/esp32s2_gpio_sigmap.h" #if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF) @@ -54,15 +54,15 @@ #define GPIO_OUT2 2 #define GPIO_IN1 4 -#if !defined(CONFIG_ESP32S2_GPIO_IRQ) && BOARD_NGPIOINT > 0 +#if !defined(CONFIG_ESPRESSIF_GPIO_IRQ) && BOARD_NGPIOINT > 0 # error "NGPIOINT is > 0 and GPIO interrupts aren't enabled" #endif -/* Interrupt pins. GPIO9 is used as an example, any other inputs could be - * used. +/* Interrupt pins. GPIO0 is used as an example, any other inputs could be + * used. This is the BOOT button. */ -#define GPIO_IRQPIN 9 +#define GPIO_IRQPIN 0 /**************************************************************************** * Private Types @@ -190,7 +190,7 @@ static int gpout_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(esp32s2gpio->id < BOARD_NGPIOOUT); gpioinfo("Reading...\n"); - *value = esp32s2_gpioread(g_gpiooutputs[esp32s2gpio->id]); + *value = esp_gpioread(g_gpiooutputs[esp32s2gpio->id]); return OK; } @@ -218,7 +218,7 @@ static int gpout_write(struct gpio_dev_s *dev, bool value) DEBUGASSERT(esp32s2gpio->id < BOARD_NGPIOOUT); gpioinfo("Writing %d\n", (int)value); - esp32s2_gpiowrite(g_gpiooutputs[esp32s2gpio->id], value); + esp_gpiowrite(g_gpiooutputs[esp32s2gpio->id], value); return OK; } #endif @@ -248,13 +248,13 @@ static int gpin_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(esp32s2gpio->id < BOARD_NGPIOIN); gpioinfo("Reading...\n"); - *value = esp32s2_gpioread(g_gpioinputs[esp32s2gpio->id]); + *value = esp_gpioread(g_gpioinputs[esp32s2gpio->id]); return OK; } #endif /**************************************************************************** - * Name: esp32s2gpio_interrupt + * Name: espgpio_interrupt * * Description: * Digital Input ISR. @@ -299,7 +299,7 @@ static int gpint_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(esp32s2gpint->esp32s2gpio.id < BOARD_NGPIOINT); gpioinfo("Reading int pin...\n"); - *value = esp32s2_gpioread(g_gpiointinputs[esp32s2gpint->esp32s2gpio.id]); + *value = esp_gpioread(g_gpiointinputs[esp32s2gpint->esp32s2gpio.id]); return OK; } @@ -325,23 +325,27 @@ static int gpint_attach(struct gpio_dev_s *dev, { struct esp32s2gpint_dev_s *esp32s2gpint = (struct esp32s2gpint_dev_s *)dev; - int irq = ESP32S2_PIN2IRQ(g_gpiointinputs[esp32s2gpint->esp32s2gpio.id]); int ret; gpioinfo("Attaching the callback\n"); /* Make sure the interrupt is disabled */ - esp32s2_gpioirqdisable(irq); - ret = irq_attach(irq, - esp32s2gpio_interrupt, - &g_gpint[esp32s2gpint->esp32s2gpio.id]); + esp_gpioirqdisable(g_gpiointinputs[esp32s2gpint->esp32s2gpio.id]); + + ret = esp_gpio_irq(g_gpiointinputs[esp32s2gpint->esp32s2gpio.id], + esp32s2gpio_interrupt, + &g_gpint[esp32s2gpint->esp32s2gpio.id]); if (ret < 0) { syslog(LOG_ERR, "ERROR: gpint_attach() failed: %d\n", ret); return ret; } + /* Make sure the interrupt is disabled */ + + esp_gpioirqdisable(g_gpiointinputs[esp32s2gpint->esp32s2gpio.id]); + gpioinfo("Attach %p\n", callback); esp32s2gpint->callback = callback; return OK; @@ -366,7 +370,6 @@ static int gpint_enable(struct gpio_dev_s *dev, bool enable) { struct esp32s2gpint_dev_s *esp32s2gpint = (struct esp32s2gpint_dev_s *)dev; - int irq = ESP32S2_PIN2IRQ(g_gpiointinputs[esp32s2gpint->esp32s2gpio.id]); if (enable) { @@ -376,13 +379,13 @@ static int gpint_enable(struct gpio_dev_s *dev, bool enable) /* Configure the interrupt for rising edge */ - esp32s2_gpioirqenable(irq, RISING); + esp_gpioirqenable(g_gpiointinputs[esp32s2gpint->esp32s2gpio.id]); } } else { gpioinfo("Disable the interrupt\n"); - esp32s2_gpioirqdisable(irq); + esp_gpioirqdisable(g_gpiointinputs[esp32s2gpint->esp32s2gpio.id]); } return OK; @@ -407,9 +410,10 @@ static int gpint_enable(struct gpio_dev_s *dev, bool enable) int esp32s2_gpio_init(void) { int pincount = 0; + int i; #if BOARD_NGPIOOUT > 0 - for (int i = 0; i < BOARD_NGPIOOUT; i++) + for (i = 0; i < BOARD_NGPIOOUT; i++) { /* Setup and register the GPIO pin */ @@ -420,17 +424,16 @@ int esp32s2_gpio_init(void) /* Configure the pins that will be used as output */ - esp32s2_gpio_matrix_out(g_gpiooutputs[i], SIG_GPIO_OUT_IDX, 0, 0); - esp32s2_configgpio(g_gpiooutputs[i], OUTPUT_FUNCTION_1 | - INPUT_FUNCTION_1); - esp32s2_gpiowrite(g_gpiooutputs[i], 0); + esp_gpio_matrix_out(g_gpiooutputs[i], SIG_GPIO_OUT_IDX, 0, 0); + esp_configgpio(g_gpiooutputs[i], OUTPUT_FUNCTION_1 | INPUT_FUNCTION_1); + esp_gpiowrite(g_gpiooutputs[i], 0); pincount++; } #endif #if BOARD_NGPIOIN > 0 - for (int i = 0; i < BOARD_NGPIOIN; i++) + for (i = 0; i < BOARD_NGPIOIN; i++) { /* Setup and register the GPIO pin */ @@ -441,14 +444,14 @@ int esp32s2_gpio_init(void) /* Configure the pins that will be used as interrupt input */ - esp32s2_configgpio(g_gpioinputs[i], INPUT_FUNCTION_1 | PULLDOWN); + esp_configgpio(g_gpioinputs[i], INPUT_FUNCTION_1 | PULLDOWN); pincount++; } #endif #if BOARD_NGPIOINT > 0 - for (int i = 0; i < BOARD_NGPIOINT; i++) + for (i = 0; i < BOARD_NGPIOINT; i++) { /* Setup and register the GPIO pin */ @@ -457,9 +460,12 @@ int esp32s2_gpio_init(void) g_gpint[i].esp32s2gpio.id = i; gpio_pin_register(&g_gpint[i].esp32s2gpio.gpio, pincount); - /* Configure the pins that will be used as interrupt input */ + /* Configure the pins that will be used as interrupt input with + * falling edge. + */ - esp32s2_configgpio(g_gpiointinputs[i], INPUT_FUNCTION_1 | PULLDOWN); + esp_configgpio(g_gpiointinputs[i], + INPUT_FUNCTION_1 | PULLUP | FALLING); pincount++; } diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/adc/defconfig b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/adc/defconfig index 9013015ee2d30..a5c5f0c62b964 100644 --- a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/adc/defconfig +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/adc/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32S2_SAOLA_1=y CONFIG_ARCH_CHIP="esp32s2" CONFIG_ARCH_CHIP_ESP32S2=y CONFIG_ARCH_CHIP_ESP32S2WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/audio/defconfig b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/audio/defconfig index 652f5053c035d..d51049cde67f0 100644 --- a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/audio/defconfig +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/audio/defconfig @@ -18,6 +18,9 @@ CONFIG_ARCH_BOARD_ESP32S2_SAOLA_1=y CONFIG_ARCH_CHIP="esp32s2" CONFIG_ARCH_CHIP_ESP32S2=y CONFIG_ARCH_CHIP_ESP32S2WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_AUDIO=y diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/buttons/defconfig b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/buttons/defconfig index 63db09b06e19e..0db930b57b753 100644 --- a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/buttons/defconfig +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/buttons/defconfig @@ -17,12 +17,15 @@ CONFIG_ARCH_CHIP="esp32s2" CONFIG_ARCH_CHIP_ESP32S2=y CONFIG_ARCH_CHIP_ESP32S2WROVER=y CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y -CONFIG_ESP32S2_GPIO_IRQ=y CONFIG_ESP32S2_UART0=y +CONFIG_ESPRESSIF_GPIO_IRQ=y CONFIG_EXAMPLES_BUTTONS=y CONFIG_FS_PROCFS=y CONFIG_HAVE_CXX=y diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/coremark/defconfig b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/coremark/defconfig index 3029107c80212..262a064279a94 100644 --- a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/coremark/defconfig +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/coremark/defconfig @@ -14,6 +14,9 @@ CONFIG_ARCH_BOARD_ESP32S2_SAOLA_1=y CONFIG_ARCH_CHIP="esp32s2" CONFIG_ARCH_CHIP_ESP32S2=y CONFIG_ARCH_CHIP_ESP32S2WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_SETJMP_H=y CONFIG_ARCH_XTENSA=y CONFIG_BENCHMARK_COREMARK=y diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/crypto/defconfig b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/crypto/defconfig index 4e89cb435d8be..02974336ad2b6 100644 --- a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/crypto/defconfig +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/crypto/defconfig @@ -19,6 +19,9 @@ CONFIG_ARCH_BOARD_ESP32S2_SAOLA_1=y CONFIG_ARCH_CHIP="esp32s2" CONFIG_ARCH_CHIP_ESP32S2=y CONFIG_ARCH_CHIP_ESP32S2WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/cxx/defconfig b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/cxx/defconfig index dd22a902965c3..58ed474928ce4 100644 --- a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/cxx/defconfig +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/cxx/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32S2_SAOLA_1=y CONFIG_ARCH_CHIP="esp32s2" CONFIG_ARCH_CHIP_ESP32S2=y CONFIG_ARCH_CHIP_ESP32S2WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/efuse/defconfig b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/efuse/defconfig index ba66005fe73b8..a6cce0f6153c4 100644 --- a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/efuse/defconfig +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/efuse/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_BOARD_ESP32S2_SAOLA_1=y CONFIG_ARCH_CHIP="esp32s2" CONFIG_ARCH_CHIP_ESP32S2=y CONFIG_ARCH_CHIP_ESP32S2WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/gpio/defconfig b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/gpio/defconfig index cf553cf1d508f..1ae44c5cb31e5 100644 --- a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/gpio/defconfig +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/gpio/defconfig @@ -15,13 +15,16 @@ CONFIG_ARCH_BOARD_ESP32S2_SAOLA_1=y CONFIG_ARCH_CHIP="esp32s2" CONFIG_ARCH_CHIP_ESP32S2=y CONFIG_ARCH_CHIP_ESP32S2WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y CONFIG_DEV_GPIO=y -CONFIG_ESP32S2_GPIO_IRQ=y CONFIG_ESP32S2_UART0=y +CONFIG_ESPRESSIF_GPIO_IRQ=y CONFIG_EXAMPLES_GPIO=y CONFIG_FS_PROCFS=y CONFIG_HAVE_CXX=y diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/i2c/defconfig b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/i2c/defconfig index 6c39cd3eff098..ae6a03b7609d5 100644 --- a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/i2c/defconfig +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/i2c/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32S2_SAOLA_1=y CONFIG_ARCH_CHIP="esp32s2" CONFIG_ARCH_CHIP_ESP32S2=y CONFIG_ARCH_CHIP_ESP32S2WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/i2schar/defconfig b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/i2schar/defconfig index c28c6bb869fd0..ef0cb8029c4cb 100644 --- a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/i2schar/defconfig +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/i2schar/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_BOARD_ESP32S2_SAOLA_1=y CONFIG_ARCH_CHIP="esp32s2" CONFIG_ARCH_CHIP_ESP32S2=y CONFIG_ARCH_CHIP_ESP32S2WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_AUDIO=y diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/mcuboot_nsh/defconfig b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/mcuboot_nsh/defconfig index 38457e3cf9d0b..aefcf129ceecb 100644 --- a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/mcuboot_nsh/defconfig +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/mcuboot_nsh/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32S2_SAOLA_1=y CONFIG_ARCH_CHIP="esp32s2" CONFIG_ARCH_CHIP_ESP32S2=y CONFIG_ARCH_CHIP_ESP32S2WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/mcuboot_update_agent/defconfig b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/mcuboot_update_agent/defconfig index 71e49b4a49066..91aa0e44da01b 100644 --- a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/mcuboot_update_agent/defconfig +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/mcuboot_update_agent/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_BOARD_ESP32S2_SAOLA_1=y CONFIG_ARCH_CHIP="esp32s2" CONFIG_ARCH_CHIP_ESP32S2=y CONFIG_ARCH_CHIP_ESP32S2WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARDCTL_RESET=y @@ -25,7 +28,6 @@ CONFIG_DEFAULT_TASK_STACKSIZE=4096 CONFIG_DRIVERS_IEEE80211=y CONFIG_DRIVERS_WIRELESS=y CONFIG_ESP32S2_APP_FORMAT_MCUBOOT=y -CONFIG_ESP32S2_RT_TIMER_TASK_STACK_SIZE=4096 CONFIG_ESP32S2_UART0=y CONFIG_ESPRESSIF_SPIFLASH=y CONFIG_ESPRESSIF_WIFI=y @@ -71,6 +73,8 @@ CONFIG_PTHREAD_MUTEX_TYPES=y CONFIG_RAM_SIZE=114688 CONFIG_RAM_START=0x20000000 CONFIG_RR_INTERVAL=200 +CONFIG_RTC=y +CONFIG_RTC_DRIVER=y CONFIG_SCHED_LPWORK=y CONFIG_SCHED_WAITPID=y CONFIG_SIG_DEFAULT=y diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/nsh/defconfig b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/nsh/defconfig index 0d247f1ab6d79..59fccc990660c 100644 --- a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/nsh/defconfig +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/nsh/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32S2_SAOLA_1=y CONFIG_ARCH_CHIP="esp32s2" CONFIG_ARCH_CHIP_ESP32S2=y CONFIG_ARCH_CHIP_ESP32S2WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/nxlooper/defconfig b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/nxlooper/defconfig index fe51edb47ce35..f60a050ca2aaa 100644 --- a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/nxlooper/defconfig +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/nxlooper/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_BOARD_ESP32S2_SAOLA_1=y CONFIG_ARCH_CHIP="esp32s2" CONFIG_ARCH_CHIP_ESP32S2=y CONFIG_ARCH_CHIP_ESP32S2WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_AUDIO=y diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/oneshot/defconfig b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/oneshot/defconfig index 7ae604ddb3d0b..5be888763c922 100644 --- a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/oneshot/defconfig +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/oneshot/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32S2_SAOLA_1=y CONFIG_ARCH_CHIP="esp32s2" CONFIG_ARCH_CHIP_ESP32S2=y CONFIG_ARCH_CHIP_ESP32S2WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/ostest/defconfig b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/ostest/defconfig index 0828a56bb803c..77037030c2aae 100644 --- a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/ostest/defconfig +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/ostest/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32S2_SAOLA_1=y CONFIG_ARCH_CHIP="esp32s2" CONFIG_ARCH_CHIP_ESP32S2=y CONFIG_ARCH_CHIP_ESP32S2WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_SETJMP_H=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/pm/defconfig b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/pm/defconfig index 909c1f4146988..b8bf517253fc8 100644 --- a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/pm/defconfig +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/pm/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32S2_SAOLA_1=y CONFIG_ARCH_CHIP="esp32s2" CONFIG_ARCH_CHIP_ESP32S2=y CONFIG_ARCH_CHIP_ESP32S2WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 @@ -39,6 +42,8 @@ CONFIG_PREALLOC_TIMERS=4 CONFIG_RAM_SIZE=114688 CONFIG_RAM_START=0x20000000 CONFIG_RR_INTERVAL=200 +CONFIG_RTC=y +CONFIG_RTC_DRIVER=y CONFIG_SCHED_WAITPID=y CONFIG_SYSLOG_BUFFER=y CONFIG_SYSTEM_NSH=y diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/pwm/defconfig b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/pwm/defconfig index 18028f92e74e0..4a04afcd3d25b 100644 --- a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/pwm/defconfig +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/pwm/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32S2_SAOLA_1=y CONFIG_ARCH_CHIP="esp32s2" CONFIG_ARCH_CHIP_ESP32S2=y CONFIG_ARCH_CHIP_ESP32S2WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/qencoder/defconfig b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/qencoder/defconfig index 03aa1641f87e5..63643da8870b5 100644 --- a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/qencoder/defconfig +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/qencoder/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32S2_SAOLA_1=y CONFIG_ARCH_CHIP="esp32s2" CONFIG_ARCH_CHIP_ESP32S2=y CONFIG_ARCH_CHIP_ESP32S2WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/random/defconfig b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/random/defconfig index f0913c78d2f1c..04102bff59a3e 100644 --- a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/random/defconfig +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/random/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32S2_SAOLA_1=y CONFIG_ARCH_CHIP="esp32s2" CONFIG_ARCH_CHIP_ESP32S2=y CONFIG_ARCH_CHIP_ESP32S2WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/rmt/defconfig b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/rmt/defconfig index 5e6197303d4c4..9b31d333be9d5 100644 --- a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/rmt/defconfig +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/rmt/defconfig @@ -17,6 +17,9 @@ CONFIG_ARCH_BOARD_ESP32S2_SAOLA_1=y CONFIG_ARCH_CHIP="esp32s2" CONFIG_ARCH_CHIP_ESP32S2=y CONFIG_ARCH_CHIP_ESP32S2WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/romfs/defconfig b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/romfs/defconfig index 9fe404f0ad3e6..27caf4e742f26 100644 --- a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/romfs/defconfig +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/romfs/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32S2_SAOLA_1=y CONFIG_ARCH_CHIP="esp32s2" CONFIG_ARCH_CHIP_ESP32S2=y CONFIG_ARCH_CHIP_ESP32S2WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/rtc/defconfig b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/rtc/defconfig index 036636f515aaa..33170aaca4af5 100644 --- a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/rtc/defconfig +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/rtc/defconfig @@ -15,11 +15,13 @@ CONFIG_ARCH_BOARD_ESP32S2_SAOLA_1=y CONFIG_ARCH_CHIP="esp32s2" CONFIG_ARCH_CHIP_ESP32S2=y CONFIG_ARCH_CHIP_ESP32S2WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y -CONFIG_ESP32S2_RT_TIMER=y CONFIG_ESP32S2_UART0=y CONFIG_EXAMPLES_ALARM=y CONFIG_FS_PROCFS=y diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/sdm/defconfig b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/sdm/defconfig index c848a85b9460d..53379492e568f 100644 --- a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/sdm/defconfig +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/sdm/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32S2_SAOLA_1=y CONFIG_ARCH_CHIP="esp32s2" CONFIG_ARCH_CHIP_ESP32S2=y CONFIG_ARCH_CHIP_ESP32S2WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/sdmmc_spi/defconfig b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/sdmmc_spi/defconfig index ff762234a700f..649acf113cda5 100644 --- a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/sdmmc_spi/defconfig +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/sdmmc_spi/defconfig @@ -20,6 +20,9 @@ CONFIG_ARCH_BOARD_ESP32S2_SAOLA_1=y CONFIG_ARCH_CHIP="esp32s2" CONFIG_ARCH_CHIP_ESP32S2=y CONFIG_ARCH_CHIP_ESP32S2WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/sotest/defconfig b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/sotest/defconfig index 507694fece2ad..9710b931084fb 100644 --- a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/sotest/defconfig +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/sotest/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32S2_SAOLA_1=y CONFIG_ARCH_CHIP="esp32s2" CONFIG_ARCH_CHIP_ESP32S2=y CONFIG_ARCH_CHIP_ESP32S2WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARDCTL_OS_SYMTAB=y diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/spi/defconfig b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/spi/defconfig index 98f17046a2e07..6499b27eba25b 100644 --- a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/spi/defconfig +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/spi/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32S2_SAOLA_1=y CONFIG_ARCH_CHIP="esp32s2" CONFIG_ARCH_CHIP_ESP32S2=y CONFIG_ARCH_CHIP_ESP32S2WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/spiflash/defconfig b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/spiflash/defconfig index 98f7b814d8e2f..a097b183c3e10 100644 --- a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/spiflash/defconfig +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/spiflash/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32S2_SAOLA_1=y CONFIG_ARCH_CHIP="esp32s2" CONFIG_ARCH_CHIP_ESP32S2=y CONFIG_ARCH_CHIP_ESP32S2WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/sta_softap/defconfig b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/sta_softap/defconfig index 68cf99a517902..24fe5af68ef29 100644 --- a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/sta_softap/defconfig +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/sta_softap/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_BOARD_ESP32S2_SAOLA_1=y CONFIG_ARCH_CHIP="esp32s2" CONFIG_ARCH_CHIP_ESP32S2=y CONFIG_ARCH_CHIP_ESP32S2WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 @@ -63,6 +66,8 @@ CONFIG_PTHREAD_MUTEX_TYPES=y CONFIG_RAM_SIZE=114688 CONFIG_RAM_START=0x20000000 CONFIG_RR_INTERVAL=200 +CONFIG_RTC=y +CONFIG_RTC_DRIVER=y CONFIG_SCHED_LPWORK=y CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/temperature_sensor/defconfig b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/temperature_sensor/defconfig index b3f5fdfec2424..3d4e33135afde 100644 --- a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/temperature_sensor/defconfig +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/temperature_sensor/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32S2_SAOLA_1=y CONFIG_ARCH_CHIP="esp32s2" CONFIG_ARCH_CHIP_ESP32S2=y CONFIG_ARCH_CHIP_ESP32S2WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 @@ -29,6 +32,7 @@ CONFIG_IDLETHREAD_STACKSIZE=3072 CONFIG_INIT_ENTRYPOINT="nsh_main" CONFIG_INIT_STACKSIZE=3072 CONFIG_INTELHEX_BINARY=y +CONFIG_LIBC_FLOATINGPOINT=y CONFIG_LINE_MAX=64 CONFIG_NSH_ARCHINIT=y CONFIG_NSH_BUILTIN_APPS=y diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/timer/defconfig b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/timer/defconfig index eddb5b9e58cc2..fc0e9e5def756 100644 --- a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/timer/defconfig +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/timer/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32S2_SAOLA_1=y CONFIG_ARCH_CHIP="esp32s2" CONFIG_ARCH_CHIP_ESP32S2=y CONFIG_ARCH_CHIP_ESP32S2WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 @@ -48,5 +51,4 @@ CONFIG_START_YEAR=2011 CONFIG_SYSLOG_BUFFER=y CONFIG_SYSTEM_NSH=y CONFIG_TIMER=y -CONFIG_TIMER_ARCH=y CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/twai/defconfig b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/twai/defconfig index bf94740c58007..2f7693ddcdfc1 100644 --- a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/twai/defconfig +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/twai/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32S2_SAOLA_1=y CONFIG_ARCH_CHIP="esp32s2" CONFIG_ARCH_CHIP_ESP32S2=y CONFIG_ARCH_CHIP_ESP32S2WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/ulp/defconfig b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/ulp/defconfig index 7ad658e528979..8d3220384c3fa 100644 --- a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/ulp/defconfig +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/ulp/defconfig @@ -15,14 +15,17 @@ CONFIG_ARCH_BOARD_ESP32S2_SAOLA_1=y CONFIG_ARCH_CHIP="esp32s2" CONFIG_ARCH_CHIP_ESP32S2=y CONFIG_ARCH_CHIP_ESP32S2WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y CONFIG_DEV_GPIO=y -CONFIG_ESP32S2_GPIO_IRQ=y CONFIG_ESP32S2_UART0=y CONFIG_ESP32S2_ULP_COPROC_RESERVE_MEM=8000 +CONFIG_ESPRESSIF_GPIO_IRQ=y CONFIG_ESPRESSIF_ULP_USE_TEST_BIN=y CONFIG_FS_PROCFS=y CONFIG_HAVE_CXX=y diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/watchdog/defconfig b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/watchdog/defconfig index ba3b53006c4b6..f52204ef75068 100644 --- a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/watchdog/defconfig +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/watchdog/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_ESP32S2_SAOLA_1=y CONFIG_ARCH_CHIP="esp32s2" CONFIG_ARCH_CHIP_ESP32S2=y CONFIG_ARCH_CHIP_ESP32S2WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/wifi/defconfig b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/wifi/defconfig index 042b3149782b1..f74b812e722f5 100644 --- a/boards/xtensa/esp32s2/esp32s2-saola-1/configs/wifi/defconfig +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/configs/wifi/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_BOARD_ESP32S2_SAOLA_1=y CONFIG_ARCH_CHIP="esp32s2" CONFIG_ARCH_CHIP_ESP32S2=y CONFIG_ARCH_CHIP_ESP32S2WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 @@ -59,6 +62,8 @@ CONFIG_PTHREAD_MUTEX_TYPES=y CONFIG_RAM_SIZE=114688 CONFIG_RAM_START=0x20000000 CONFIG_RR_INTERVAL=200 +CONFIG_RTC=y +CONFIG_RTC_DRIVER=y CONFIG_SCHED_LPWORK=y CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_bringup.c b/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_bringup.c index 576850306af16..64e1a00a921a2 100644 --- a/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_bringup.c +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_bringup.c @@ -38,6 +38,9 @@ #include #include +#include "espressif/esp_gpio.h" +#include "esp32s2_start.h" + #ifdef CONFIG_USERLED # include #endif @@ -58,10 +61,6 @@ # include "esp32s2_i2c.h" #endif -#ifdef CONFIG_ESP32S2_RT_TIMER -# include "esp32s2_rt_timer.h" -#endif - #ifdef CONFIG_ESPRESSIF_EFUSE # include "espressif/esp_efuse.h" #endif @@ -89,7 +88,11 @@ #endif #ifdef CONFIG_RTC_DRIVER -# include "esp32s2_rtc_lowerhalf.h" +# include "espressif/esp_rtc.h" +#endif + +#ifdef CONFIG_ESPRESSIF_HR_TIMER +# include "espressif/esp_hr_timer.h" #endif #ifdef CONFIG_ESP_RMT @@ -266,6 +269,14 @@ int esp32s2_bringup(void) # endif #endif +#ifdef CONFIG_ESPRESSIF_HR_TIMER + ret = esp_hr_timer_init(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: esp_hr_timer_init() failed: %d\n", ret); + } +#endif + /* Register the timer drivers */ #ifdef CONFIG_TIMER @@ -316,14 +327,6 @@ int esp32s2_bringup(void) #endif /* CONFIG_TIMER */ -#ifdef CONFIG_ESP32S2_RT_TIMER - ret = esp32s2_rt_timer_init(); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize RT timer: %d\n", ret); - } - -#endif /* Now register one oneshot driver */ #if defined(CONFIG_ONESHOT) && defined(CONFIG_ESP32S2_TIMER0) @@ -437,13 +440,13 @@ int esp32s2_bringup(void) #endif /* CONFIG_ESPRESSIF_I2S || CONFIG_ESPRESSIF_I2S */ #ifdef CONFIG_ESP_RMT - ret = board_rmt_txinitialize(RMT_TXCHANNEL, RMT_OUTPUT_PIN); + ret = board_rmt_txinitialize(RMT_OUTPUT_PIN); if (ret < 0) { syslog(LOG_ERR, "ERROR: board_rmt_txinitialize() failed: %d\n", ret); } - ret = board_rmt_rxinitialize(RMT_RXCHANNEL, RMT_INPUT_PIN); + ret = board_rmt_rxinitialize(RMT_INPUT_PIN); if (ret < 0) { syslog(LOG_ERR, "ERROR: board_rmt_txinitialize() failed: %d\n", ret); @@ -488,7 +491,7 @@ int esp32s2_bringup(void) #ifdef CONFIG_RTC_DRIVER /* Instantiate the ESP32 RTC driver */ - ret = esp32s2_rtc_driverinit(); + ret = esp_rtc_driverinit(); if (ret < 0) { syslog(LOG_ERR, diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_buttons.c b/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_buttons.c index 78ff79a283a7a..983c1e7824245 100644 --- a/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_buttons.c +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_buttons.c @@ -38,7 +38,7 @@ #include #include -#include "esp32s2_gpio.h" +#include "espressif/esp_gpio.h" #include "esp32s2-saola-1.h" @@ -55,11 +55,17 @@ * of all buttons or board_button_irq() may be called to register button * interrupt handlers. * + * Input Parameters: + * None. + * + * Returned Value: + * The number of buttons that were initialized. + * ****************************************************************************/ uint32_t board_button_initialize(void) { - esp32s2_configgpio(BUTTON_BOOT, INPUT_FUNCTION_3 | PULLUP); + esp_configgpio(BUTTON_BOOT, INPUT_FUNCTION_3 | PULLUP | CHANGE); return NUM_BUTTONS; } @@ -80,13 +86,13 @@ uint32_t board_buttons(void) int i = 0; int n = 0; - bool b0 = esp32s2_gpioread(BUTTON_BOOT); + bool b0 = esp_gpioread(BUTTON_BOOT); for (i = 0; i < 10; i++) { up_mdelay(1); /* TODO */ - bool b1 = esp32s2_gpioread(BUTTON_BOOT); + bool b1 = esp_gpioread(BUTTON_BOOT); if (b0 == b1) { @@ -132,38 +138,6 @@ uint32_t board_buttons(void) #ifdef CONFIG_ARCH_IRQBUTTONS int board_button_irq(int id, xcpt_t irqhandler, void *arg) { - int ret; - DEBUGASSERT(id == 0); - - int irq = ESP32S2_PIN2IRQ(BUTTON_BOOT); - - if (NULL != irqhandler) - { - /* Make sure the interrupt is disabled */ - - esp32s2_gpioirqdisable(irq); - - ret = irq_attach(irq, irqhandler, arg); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: irq_attach() failed: %d\n", ret); - return ret; - } - - gpioinfo("Attach %p\n", irqhandler); - - gpioinfo("Enabling the interrupt\n"); - - /* Configure the interrupt for rising and falling edges */ - - esp32s2_gpioirqenable(irq, CHANGE); - } - else - { - gpioinfo("Disable the interrupt\n"); - esp32s2_gpioirqdisable(irq); - } - - return OK; + return esp_gpio_irq(BUTTON_BOOT, irqhandler, arg); } #endif diff --git a/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_gpio.c b/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_gpio.c index 5c39d8d8f2a45..3eb66786c7de5 100644 --- a/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_gpio.c +++ b/boards/xtensa/esp32s2/esp32s2-saola-1/src/esp32s2_gpio.c @@ -39,9 +39,8 @@ #include #include "esp32s2-saola-1.h" -#include "esp32s2_gpio.h" +#include "espressif/esp_gpio.h" #include "hardware/esp32s2_gpio_sigmap.h" - #ifdef CONFIG_ESPRESSIF_DEDICATED_GPIO #include "espressif/esp_dedic_gpio.h" #endif @@ -62,15 +61,15 @@ #define GPIO_OUT2 2 #define GPIO_IN1 4 -#if !defined(CONFIG_ESP32S2_GPIO_IRQ) && BOARD_NGPIOINT > 0 +#if !defined(CONFIG_ESPRESSIF_GPIO_IRQ) && BOARD_NGPIOINT > 0 # error "NGPIOINT is > 0 and GPIO interrupts aren't enabled" #endif -/* Interrupt pins. GPIO9 is used as an example, any other inputs could be - * used. +/* Interrupt pins. GPIO0 is used as an example, any other inputs could be + * used. This is the BOOT button. */ -#define GPIO_IRQPIN 9 +#define GPIO_IRQPIN 0 /* Dedicated GPIO pins. GPIO4 and GPIO5 is used as an example, any other * GPIOs could be used. @@ -314,7 +313,7 @@ static int gpout_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(esp32s2gpio->id < BOARD_NGPIOOUT); gpioinfo("Reading...\n"); - *value = esp32s2_gpioread(g_gpiooutputs[esp32s2gpio->id]); + *value = esp_gpioread(g_gpiooutputs[esp32s2gpio->id]); return OK; } @@ -342,7 +341,7 @@ static int gpout_write(struct gpio_dev_s *dev, bool value) DEBUGASSERT(esp32s2gpio->id < BOARD_NGPIOOUT); gpioinfo("Writing %d\n", (int)value); - esp32s2_gpiowrite(g_gpiooutputs[esp32s2gpio->id], value); + esp_gpiowrite(g_gpiooutputs[esp32s2gpio->id], value); return OK; } #endif @@ -372,13 +371,13 @@ static int gpin_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(esp32s2gpio->id < BOARD_NGPIOIN); gpioinfo("Reading...\n"); - *value = esp32s2_gpioread(g_gpioinputs[esp32s2gpio->id]); + *value = esp_gpioread(g_gpioinputs[esp32s2gpio->id]); return OK; } #endif /**************************************************************************** - * Name: esp32s2gpio_interrupt + * Name: espgpio_interrupt * * Description: * Digital Input ISR. @@ -423,7 +422,7 @@ static int gpint_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(esp32s2gpint->esp32s2gpio.id < BOARD_NGPIOINT); gpioinfo("Reading int pin...\n"); - *value = esp32s2_gpioread(g_gpiointinputs[esp32s2gpint->esp32s2gpio.id]); + *value = esp_gpioread(g_gpiointinputs[esp32s2gpint->esp32s2gpio.id]); return OK; } @@ -449,23 +448,27 @@ static int gpint_attach(struct gpio_dev_s *dev, { struct esp32s2gpint_dev_s *esp32s2gpint = (struct esp32s2gpint_dev_s *)dev; - int irq = ESP32S2_PIN2IRQ(g_gpiointinputs[esp32s2gpint->esp32s2gpio.id]); int ret; gpioinfo("Attaching the callback\n"); /* Make sure the interrupt is disabled */ - esp32s2_gpioirqdisable(irq); - ret = irq_attach(irq, - esp32s2gpio_interrupt, - &g_gpint[esp32s2gpint->esp32s2gpio.id]); + esp_gpioirqdisable(g_gpiointinputs[esp32s2gpint->esp32s2gpio.id]); + + ret = esp_gpio_irq(g_gpiointinputs[esp32s2gpint->esp32s2gpio.id], + esp32s2gpio_interrupt, + &g_gpint[esp32s2gpint->esp32s2gpio.id]); if (ret < 0) { syslog(LOG_ERR, "ERROR: gpint_attach() failed: %d\n", ret); return ret; } + /* Make sure the interrupt is disabled */ + + esp_gpioirqdisable(g_gpiointinputs[esp32s2gpint->esp32s2gpio.id]); + gpioinfo("Attach %p\n", callback); esp32s2gpint->callback = callback; return OK; @@ -490,7 +493,6 @@ static int gpint_enable(struct gpio_dev_s *dev, bool enable) { struct esp32s2gpint_dev_s *esp32s2gpint = (struct esp32s2gpint_dev_s *)dev; - int irq = ESP32S2_PIN2IRQ(g_gpiointinputs[esp32s2gpint->esp32s2gpio.id]); if (enable) { @@ -500,13 +502,13 @@ static int gpint_enable(struct gpio_dev_s *dev, bool enable) /* Configure the interrupt for rising edge */ - esp32s2_gpioirqenable(irq, RISING); + esp_gpioirqenable(g_gpiointinputs[esp32s2gpint->esp32s2gpio.id]); } } else { gpioinfo("Disable the interrupt\n"); - esp32s2_gpioirqdisable(irq); + esp_gpioirqdisable(g_gpiointinputs[esp32s2gpint->esp32s2gpio.id]); } return OK; @@ -531,9 +533,10 @@ static int gpint_enable(struct gpio_dev_s *dev, bool enable) int esp32s2_gpio_init(void) { int pincount = 0; + int i; #if BOARD_NGPIOOUT > 0 - for (int i = 0; i < BOARD_NGPIOOUT; i++) + for (i = 0; i < BOARD_NGPIOOUT; i++) { /* Setup and register the GPIO pin */ @@ -544,17 +547,16 @@ int esp32s2_gpio_init(void) /* Configure the pins that will be used as output */ - esp32s2_gpio_matrix_out(g_gpiooutputs[i], SIG_GPIO_OUT_IDX, 0, 0); - esp32s2_configgpio(g_gpiooutputs[i], OUTPUT_FUNCTION_1 | - INPUT_FUNCTION_1); - esp32s2_gpiowrite(g_gpiooutputs[i], 0); + esp_gpio_matrix_out(g_gpiooutputs[i], SIG_GPIO_OUT_IDX, 0, 0); + esp_configgpio(g_gpiooutputs[i], OUTPUT_FUNCTION_1 | INPUT_FUNCTION_1); + esp_gpiowrite(g_gpiooutputs[i], 0); pincount++; } #endif #if BOARD_NGPIOIN > 0 - for (int i = 0; i < BOARD_NGPIOIN; i++) + for (i = 0; i < BOARD_NGPIOIN; i++) { /* Setup and register the GPIO pin */ @@ -565,14 +567,14 @@ int esp32s2_gpio_init(void) /* Configure the pins that will be used as interrupt input */ - esp32s2_configgpio(g_gpioinputs[i], INPUT_FUNCTION_1 | PULLDOWN); + esp_configgpio(g_gpioinputs[i], INPUT_FUNCTION_1 | PULLDOWN); pincount++; } #endif #if BOARD_NGPIOINT > 0 - for (int i = 0; i < BOARD_NGPIOINT; i++) + for (i = 0; i < BOARD_NGPIOINT; i++) { /* Setup and register the GPIO pin */ @@ -581,9 +583,12 @@ int esp32s2_gpio_init(void) g_gpint[i].esp32s2gpio.id = i; gpio_pin_register(&g_gpint[i].esp32s2gpio.gpio, pincount); - /* Configure the pins that will be used as interrupt input */ + /* Configure the pins that will be used as interrupt input with + * falling edge. + */ - esp32s2_configgpio(g_gpiointinputs[i], INPUT_FUNCTION_1 | PULLDOWN); + esp_configgpio(g_gpiointinputs[i], + INPUT_FUNCTION_1 | PULLUP | FALLING); pincount++; } @@ -596,7 +601,7 @@ int esp32s2_gpio_init(void) #endif #ifdef CONFIG_ESPRESSIF_USE_ULP_RISCV_CORE - for (int i = 0; i < GPIO_RTC_COUNT; i++) + for (i = 0; i < GPIO_RTC_COUNT; i++) { /* Setup and register the GPIO pin */ diff --git a/boards/xtensa/esp32s2/franzininho-wifi/configs/nsh/defconfig b/boards/xtensa/esp32s2/franzininho-wifi/configs/nsh/defconfig index 682065a9926c0..6c1c046385cca 100644 --- a/boards/xtensa/esp32s2/franzininho-wifi/configs/nsh/defconfig +++ b/boards/xtensa/esp32s2/franzininho-wifi/configs/nsh/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_BOARD_FRANZININHO_WIFI=y CONFIG_ARCH_CHIP="esp32s2" CONFIG_ARCH_CHIP_ESP32S2=y CONFIG_ARCH_CHIP_ESP32S2WROVER=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s2/franzininho-wifi/src/esp32s2_bringup.c b/boards/xtensa/esp32s2/franzininho-wifi/src/esp32s2_bringup.c index d00a4d2f5d1e0..01e806992a828 100644 --- a/boards/xtensa/esp32s2/franzininho-wifi/src/esp32s2_bringup.c +++ b/boards/xtensa/esp32s2/franzininho-wifi/src/esp32s2_bringup.c @@ -38,18 +38,20 @@ #include #include +#include "esp32s2_start.h" + #ifdef CONFIG_TIMER # include "esp32s2_tim_lowerhalf.h" #endif -#ifdef CONFIG_ESP32S2_RT_TIMER -# include "esp32s2_rt_timer.h" -#endif - #ifdef CONFIG_WATCHDOG # include "esp32s2_board_wdt.h" #endif +#ifdef CONFIG_ESPRESSIF_HR_TIMER +# include "espressif/esp_hr_timer.h" +#endif + #include "franzininho-wifi.h" /**************************************************************************** @@ -105,6 +107,14 @@ int esp32s2_bringup(void) } #endif +#ifdef CONFIG_ESPRESSIF_HR_TIMER + ret = esp_hr_timer_init(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: esp_hr_timer_init() failed: %d\n", ret); + } +#endif + /* Register the timer drivers */ #ifdef CONFIG_TIMER @@ -155,14 +165,6 @@ int esp32s2_bringup(void) #endif /* CONFIG_TIMER */ -#ifdef CONFIG_ESP32S2_RT_TIMER - ret = esp32s2_rt_timer_init(); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize RT timer: %d\n", ret); - } - -#endif /* Now register one oneshot driver */ #if defined(CONFIG_ONESHOT) && defined(CONFIG_ESP32S2_TIMER0) diff --git a/boards/xtensa/esp32s3/common/Makefile b/boards/xtensa/esp32s3/common/Makefile index 02d2e673ac46d..cf726ef54c54d 100644 --- a/boards/xtensa/esp32s3/common/Makefile +++ b/boards/xtensa/esp32s3/common/Makefile @@ -33,3 +33,4 @@ include $(TOPDIR)/boards/Board.mk ARCHSRCDIR = $(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src BOARDDIR = $(ARCHSRCDIR)$(DELIM)board CFLAGS += ${INCDIR_PREFIX}$(BOARDDIR)$(DELIM)include +CFLAGS += ${INCDIR_PREFIX}"$(ARCHSRCDIR)$(DELIM)common$(DELIM)espressif" diff --git a/boards/xtensa/esp32s3/common/include/esp32s3_board_rmt.h b/boards/xtensa/esp32s3/common/include/esp32s3_board_rmt.h index e92b2e545096a..a4371eff63569 100644 --- a/boards/xtensa/esp32s3/common/include/esp32s3_board_rmt.h +++ b/boards/xtensa/esp32s3/common/include/esp32s3_board_rmt.h @@ -61,7 +61,6 @@ extern "C" * Initialize the RMT peripheral and register an RX device. * * Input Parameters: - * ch - The RMT's channel that will be used * pin - The pin used for the RX channel * * Returned Value: @@ -69,7 +68,7 @@ extern "C" * ****************************************************************************/ -int board_rmt_rxinitialize(int ch, int pin); +int board_rmt_rxinitialize(int pin); /**************************************************************************** * Name: board_rmt_txinitialize @@ -78,7 +77,6 @@ int board_rmt_rxinitialize(int ch, int pin); * Initialize the RMT peripheral and register an TX device. * * Input Parameters: - * ch - The RMT's channel that will be used * pin - The pin used for the TX channel * * Returned Value: @@ -86,7 +84,7 @@ int board_rmt_rxinitialize(int ch, int pin); * ****************************************************************************/ -int board_rmt_txinitialize(int ch, int pin); +int board_rmt_txinitialize(int pin); #endif /* CONFIG_ESP_RMT */ diff --git a/boards/xtensa/esp32s3/common/scripts/esp32s3_sections.ld b/boards/xtensa/esp32s3/common/scripts/esp32s3_sections.ld index 8136c08f6ec3a..e0384d88f4200 100644 --- a/boards/xtensa/esp32s3/common/scripts/esp32s3_sections.ld +++ b/boards/xtensa/esp32s3/common/scripts/esp32s3_sections.ld @@ -167,7 +167,6 @@ SECTIONS *libpp.a:wifi_slp_rx_iram.*(.literal .text .literal.* .text.*) *libarch.a:*esp_loader.*(.literal .text .literal.* .text.*) *libarch.a:esp32s3_cpuindex.*(.literal .text .literal.* .text.*) - *libarch.a:esp32s3_irq.*(.literal .text .literal.* .text.*) *libarch.a:esp32s3_user.*(.literal .text .literal.* .text.*) *libarch.a:esp32s3_spiflash.*(.literal .text .literal.* .text.*) *libarch.a:xtensa_assert.*(.literal .text .literal.* .text.*) @@ -177,6 +176,9 @@ SECTIONS *libarch.a:xtensa_modifyreg32.*(.literal .text .literal.* .text.*) *libarch.a:xtensa_testset.*(.literal .text .literal.* .text.*) *libarch.a:esp_app_desc.*(.literal .text .literal.* .text.*) + *libarch.a:intr_alloc.*(.literal.esp_intr_get_intno .text.esp_intr_get_intno) + *libarch.a:xtensa_intr.*(.literal.xt_get_interrupt_handler .text.xt_get_interrupt_handler) + *libarch.a:xtensa_intr.*(.literal.xt_get_interrupt_handler_arg .text.xt_get_interrupt_handler_arg) *libc.a:sq_remlast.*(.literal .text .literal.* .text.*) @@ -194,6 +196,7 @@ SECTIONS *libsched.a:spinlock.*(.literal .text .literal.* .text.*) *libsched.a:*sched_get_stackinfo.*(.literal .text .literal.* .text.*) *libsched.a:stack_record.*(.literal .text .literal.* .text.*) + *libsched.a:stack_monitor.*(.literal .text .literal.* .text.*) #ifdef CONFIG_ESP32S3_SPEED_UP_ISR *libarch.a:xtensa_switchcontext.*(.literal.up_switch_context .text.up_switch_context) @@ -235,6 +238,7 @@ SECTIONS *libarch.a:*periph_ctrl.*(.text .text.* .literal .literal.*) *libarch.a:*clk.*(.text .text.* .literal .literal.*) *libarch.a:*efuse_hal.*(.literal.is_eco0 .text.is_eco0) + *libarch.a:*efuse_utility.*(.text .text.* .literal .literal.*) *libarch.a:*esp_clk.*(.text .text.* .literal .literal.*) *libarch.a:*esp_clk_tree.*(.text .text.* .literal .literal.*) *libarch.a:*esp_clk_tree_common.*(.text .text.* .literal .literal.*) @@ -307,11 +311,22 @@ SECTIONS *libarch.a:spi_flash_os_func_noos.*(.literal .literal.* .text .text.*) *libarch.a:spi_flash_os_func_app.*(.literal .literal.* .text .text.*) *libarch.a:flash_brownout_hook.*(.literal .literal.* .text .text.*) - *libarch.a:esp_cache.*(.literal .literal.* .text .text.*) + *libarch.a:esp_cache_utils.*(.literal .literal.* .text .text.*) *libarch.a:cache_utils.*(.literal .literal.* .text .text.*) *libarch.a:memspi_host_driver.*(.literal .literal.* .text .text.*) + *libarch.a:critical_section.*(.literal .literal.* .text .text.*) + *libarch.a:os.*(.literal.nuttx_enter_critical .text.nuttx_enter_critical) + *libarch.a:os.*(.literal.nuttx_exit_critical .text.nuttx_exit_critical) + *libarch.a:*sleep_modes.*(.literal.esp_sleep_sub_mode_force_disable* .text.esp_sleep_sub_mode_force_disable*) + *libarch.a:intr_alloc.*(.literal.esp_intr_get_intno .text.esp_intr_get_intno) + *libarch.a:intr_alloc.*(.literal.esp_intr_get_cpu .text.esp_intr_get_cpu) + *libarch.a:interrupt.*(.literal.intr_handler_get .text.intr_handler_get) + *libarch.a:interrupt.*(.literal.intr_handler_get_arg .text.intr_handler_get_arg) + *libarch.a:interrupt.*(.literal.intr_get_item .text.intr_get_item) + *libarch.a:interrupt.*(.literal.intr_handler_get_arg .text.intr_handler_get_arg) *libc.a:*lib_instrument.*(.text .text.* .literal .literal.*) + *libc.a:arch_atomic.*(.text .text.* .literal .literal.*) *(.wifirxiram .wifirxiram.*) *(.wifi0iram .wifi0iram.*) @@ -448,6 +463,7 @@ SECTIONS *libarch.a:*esp_loader.*(.rodata .rodata.*) *libarch.a:esp32s3_spiflash.*(.rodata .rodata.*) *libarch.a:esp_spiflash.*(.rodata .rodata.*) + *libarch.a:*efuse_utility.*(.rodata .rodata.*) *libarch.a:*brownout.*(.rodata .rodata.*) *libarch.a:*cpu.*(.rodata .rodata.*) *libarch.a:*gpio_hal.*(.rodata .rodata.*) @@ -521,9 +537,14 @@ SECTIONS *libarch.a:spi_flash_os_func_noos.*(.rodata .rodata.*) *libarch.a:spi_flash_os_func_app.*(.rodata .rodata.*) *libarch.a:flash_brownout_hook.*(.rodata .rodata.*) - *libarch.a:esp_cache.*(.rodata .rodata.*) + *libarch.a:esp_cache_utils.*(.rodata .rodata.*) *libarch.a:cache_utils.*(.rodata .rodata.*) *libarch.a:memspi_host_driver.*(.rodata .rodata.*) + *libarch.a:critical_section.*(.rodata .rodata.*) + *libarch.a:os.*(.rodata.g_int_flags_count .rodata.g_int_flags) + *libarch.a:*sleep_modes.*(.rodata.esp_sleep_sub_mode_force_disable*) + + *libc.a:arch_atomic.*(.rodata .rodata.*) . = ALIGN(4); _edata = ABSOLUTE(.); @@ -689,9 +710,7 @@ SECTIONS . = ALIGN(4); _sinit = ABSOLUTE(.); - __init_array_start = ABSOLUTE(.); KEEP (*(EXCLUDE_FILE (*crtend.* *crtbegin.*) .ctors SORT(.ctors.*))) - __init_array_end = ABSOLUTE(.); _einit = ABSOLUTE(.); /* Addresses of memory regions reserved via SOC_RESERVE_MEMORY_REGION() */ @@ -803,6 +822,8 @@ SECTIONS .rtc.data : { + . = ALIGN(4); + *(.rtc.force_slow .rtc.force_slow.*) *(.rtc.data) *(.rtc.data.*) *(.rtc.rodata) diff --git a/boards/xtensa/esp32s3/common/scripts/kernel-space.ld b/boards/xtensa/esp32s3/common/scripts/kernel-space.ld index a60287819314b..2c68c27659019 100644 --- a/boards/xtensa/esp32s3/common/scripts/kernel-space.ld +++ b/boards/xtensa/esp32s3/common/scripts/kernel-space.ld @@ -22,6 +22,8 @@ /* Provide these so there is no need for using config files for this */ +#include "esp32s3_aliases.ld" + __uirom_start = ORIGIN(UIROM); __uirom_size = LENGTH(UIROM); __uirom_end = ORIGIN(UIROM) + LENGTH(UIROM); @@ -114,6 +116,9 @@ SECTIONS *libkarch.a:xtensa_interruptcontext.*(.literal .text .literal.* .text.*) *libkarch.a:xtensa_testset.*(.literal .text .literal.* .text.*) *libkarch.a:esp_app_desc.*(.literal .text .literal.* .text.*) + *libkarch.a:intr_alloc.*(.literal.esp_intr_get_intno .text.esp_intr_get_intno) + *libkarch.a:xtensa_intr.*(.literal.xt_get_interrupt_handler .text.xt_get_interrupt_handler) + *libkarch.a:xtensa_intr.*(.literal.xt_get_interrupt_handler_arg .text.xt_get_interrupt_handler_arg) *libkarch.a:esp_spiflash.*(.literal .text .literal.* .text.*) *libkarch.a:esp_flash_api.*(.text .text.* .literal .literal.*) *libkarch.a:esp_flash_spi_init.*(.text .text.* .literal .literal.*) @@ -125,6 +130,7 @@ SECTIONS *libkarch.a:spi_flash_os_func_noos.*(.literal .literal.* .text .text.*) *libkarch.a:spi_flash_os_func_app.*(.literal .literal.* .text .text.*) *libkarch.a:flash_brownout_hook.*(.literal .literal.* .text .text.*) + *libkarch.a:esp_cache_utils.*(.literal .literal.* .text .text.*) *libkarch.a:esp_cache.*(.literal .literal.* .text .text.*) *libkarch.a:cache_utils.*(.literal .literal.* .text .text.*) *libkarch.a:memspi_host_driver.*(.literal .literal.* .text .text.*) @@ -252,6 +258,7 @@ SECTIONS *libsched.a:irq_dispatch.*(.rodata .rodata.*) *libc.a:*lib_instrument.*(.rodata .rodata.*) + *libc.a:arch_atomic.*(.rodata .rodata.*) . = ALIGN(4); _edata = ABSOLUTE(.); diff --git a/boards/xtensa/esp32s3/common/scripts/legacy_sections.ld b/boards/xtensa/esp32s3/common/scripts/legacy_sections.ld index 6665cd6461fb6..cdff5755c48c5 100644 --- a/boards/xtensa/esp32s3/common/scripts/legacy_sections.ld +++ b/boards/xtensa/esp32s3/common/scripts/legacy_sections.ld @@ -79,7 +79,6 @@ SECTIONS *(.iram1 .iram1.*) *libarch.a:esp32s3_cpuindex.*(.literal .text .literal.* .text.*) - *libarch.a:esp32s3_irq.*(.literal .text .literal.* .text.*) *libarch.a:esp32s3_user.*(.literal .text .literal.* .text.*) *libarch.a:esp32s3_spiflash.*(.literal .text .literal.* .text.*) *libarch.a:xtensa_assert.*(.literal .text .literal.* .text.*) @@ -110,6 +109,7 @@ SECTIONS *libsched.a:stack_record.*(.literal .text .literal.* .text.*) *libc.a:*lib_instrument.*(.literal .text .literal.* .text.*) + *libc.a:arch_atomic.*(.literal .text .literal.* .text.*) #ifdef CONFIG_ESP32S3_SPEED_UP_ISR *libarch.a:xtensa_switchcontext.*(.literal.up_switch_context .text.up_switch_context) @@ -263,7 +263,7 @@ SECTIONS *libarch.a:spi_flash_os_func*.*(.rodata .rodata.*) *libarch.a:flash_brownout_hook.*(.rodata .rodata.*) *libarch.a:memspi_host_driver.*(.rodata .rodata.*) - + *libc.a:arch_atomic.*(.rodata .rodata.*) _edata = ABSOLUTE(.); . = ALIGN(4); diff --git a/boards/xtensa/esp32s3/common/scripts/mcuboot_sections.ld b/boards/xtensa/esp32s3/common/scripts/mcuboot_sections.ld index a66814df1831c..0e8f6b914a073 100644 --- a/boards/xtensa/esp32s3/common/scripts/mcuboot_sections.ld +++ b/boards/xtensa/esp32s3/common/scripts/mcuboot_sections.ld @@ -186,7 +186,6 @@ SECTIONS *libarch.a:*esp_loader.*(.text .text.* .literal .literal.*) *libarch.a:esp32s3_cpuindex.*(.literal .text .literal.* .text.*) - *libarch.a:esp32s3_irq.*(.literal .text .literal.* .text.*) *libarch.a:esp32s3_user.*(.literal .text .literal.* .text.*) *libarch.a:esp32s3_spiflash.*(.literal .text .literal.* .text.*) *libarch.a:xtensa_assert.*(.literal .text .literal.* .text.*) @@ -201,6 +200,7 @@ SECTIONS *libarch.a:*mmu_hal.*(.text .text.* .literal .literal.*) *libc.a:sq_remlast.*(.literal .text .literal.* .text.*) + *libc.a:arch_atomic.*(.literal .text .literal.* .text.*) *libdrivers.a:syslog_flush.*(.literal .text .literal.* .text.*) @@ -348,6 +348,8 @@ SECTIONS *libc.a:lib_stackchk.*(.rodata .rodata.*) #endif + *libc.a:arch_atomic.*(.rodata .rodata.*) + _edata = ABSOLUTE(.); . = ALIGN(4); diff --git a/boards/xtensa/esp32s3/common/scripts/protected_memory.ld b/boards/xtensa/esp32s3/common/scripts/protected_memory.ld index 9f8ab016f14c9..67f86f2ad0b55 100644 --- a/boards/xtensa/esp32s3/common/scripts/protected_memory.ld +++ b/boards/xtensa/esp32s3/common/scripts/protected_memory.ld @@ -34,8 +34,6 @@ #include -#include "esp32s3_aliases.ld" - #define SRAM_IRAM_START 0x40370000 #define SRAM_DIRAM_I_START 0x40378000 diff --git a/boards/xtensa/esp32s3/common/src/esp32s3_board_rmt.c b/boards/xtensa/esp32s3/common/src/esp32s3_board_rmt.c index d4449964776e1..6c6bd982d24ef 100644 --- a/boards/xtensa/esp32s3/common/src/esp32s3_board_rmt.c +++ b/boards/xtensa/esp32s3/common/src/esp32s3_board_rmt.c @@ -79,7 +79,6 @@ * Initialize the RMT peripheral and register an RX device. * * Input Parameters: - * ch - The RMT's channel that will be used * pin - The pin used for the RX channel * * Returned Value: @@ -87,11 +86,11 @@ * ****************************************************************************/ -int board_rmt_rxinitialize(int ch, int pin) +int board_rmt_rxinitialize(int pin) { int ret; - struct rmt_dev_s *rmt = esp_rmt_rx_init(ch, pin); + struct rmt_dev_s *rmt = esp_rmt_rx_init(pin); ret = rmtchar_register(rmt); if (ret < 0) @@ -110,7 +109,6 @@ int board_rmt_rxinitialize(int ch, int pin) * Initialize the RMT peripheral and register an TX device. * * Input Parameters: - * ch - The RMT's channel that will be used * pin - The pin used for the TX channel * * Returned Value: @@ -118,7 +116,7 @@ int board_rmt_rxinitialize(int ch, int pin) * ****************************************************************************/ -int board_rmt_txinitialize(int ch, int pin) +int board_rmt_txinitialize(int pin) { int ret; struct rmt_dev_s *rmt; @@ -126,7 +124,7 @@ int board_rmt_txinitialize(int ch, int pin) struct ws2812_dev_s *led; #endif - rmt = esp_rmt_tx_init(ch, pin); + rmt = esp_rmt_tx_init(pin); if (rmt == NULL) { rmterr("ERROR: esp_rmt_tx_init failed\n"); diff --git a/boards/xtensa/esp32s3/common/src/esp32s3_board_spiflash.c b/boards/xtensa/esp32s3/common/src/esp32s3_board_spiflash.c index 6619ff4b8e61c..7072c04720fed 100644 --- a/boards/xtensa/esp32s3/common/src/esp32s3_board_spiflash.c +++ b/boards/xtensa/esp32s3/common/src/esp32s3_board_spiflash.c @@ -124,8 +124,9 @@ static int init_ota_partitions(void) { struct mtd_dev_s *mtd; int ret = OK; + int i; - for (int i = 0; i < nitems(g_ota_partition_table); ++i) + for (i = 0; i < nitems(g_ota_partition_table); ++i) { const struct partition_s *part = &g_ota_partition_table[i]; #if defined(CONFIG_ESP32S3_SPIRAM) || defined(CONFIG_ESP32S3_PARTITION_TABLE) @@ -451,8 +452,6 @@ int board_spiflash_init(void) #if defined(CONFIG_ESP32S3_SPIRAM) || defined(CONFIG_ESP32S3_PARTITION_TABLE) ret = esp32s3_spiflash_init(); -#else - ret = esp_spiflash_init(); #endif if (ret < 0) { diff --git a/boards/xtensa/esp32s3/common/src/esp32s3_board_wdt.c b/boards/xtensa/esp32s3/common/src/esp32s3_board_wdt.c index bc9f9f0defe12..c3b61cf8bf489 100644 --- a/boards/xtensa/esp32s3/common/src/esp32s3_board_wdt.c +++ b/boards/xtensa/esp32s3/common/src/esp32s3_board_wdt.c @@ -31,7 +31,6 @@ #include "esp32s3_board_wdt.h" #include "esp32s3_wdt_lowerhalf.h" -#include "esp32s3_wdt.h" /**************************************************************************** * Pre-processor Definitions @@ -95,4 +94,3 @@ int board_wdt_init(void) return ret; } - diff --git a/boards/xtensa/esp32s3/common/src/esp32s3_lan9250.c b/boards/xtensa/esp32s3/common/src/esp32s3_lan9250.c index 5eeae968f45bb..cc091566fb47a 100644 --- a/boards/xtensa/esp32s3/common/src/esp32s3_lan9250.c +++ b/boards/xtensa/esp32s3/common/src/esp32s3_lan9250.c @@ -40,7 +40,7 @@ #include "xtensa.h" #include "espressif/esp_efuse.h" -#include "esp32s3_gpio.h" +#include "espressif/esp_gpio.h" #ifdef CONFIG_LAN9250_SPI #include "esp32s3_spi.h" #else @@ -109,9 +109,8 @@ static int lan9250_attach(const struct lan9250_lower_s *lower, xcpt_t handler, void *arg) { int ret; - int irq = ESP32S3_PIN2IRQ(LAN9250_IRQ); - ret = irq_attach(irq, handler, arg); + ret = esp_gpio_irq(LAN9250_IRQ, handler, arg); if (ret < 0) { syslog(LOG_ERR, "ERROR: irq_attach() failed: %d\n", ret); @@ -139,11 +138,7 @@ static int lan9250_attach(const struct lan9250_lower_s *lower, static void lan9250_enable(const struct lan9250_lower_s *lower) { - int irq = ESP32S3_PIN2IRQ(LAN9250_IRQ); - - /* Configure the interrupt for rising and falling edges */ - - esp32s3_gpioirqenable(irq, ONLOW); + esp_gpioirqenable(LAN9250_IRQ); ninfo("Enable the interrupt\n"); } @@ -163,10 +158,8 @@ static void lan9250_enable(const struct lan9250_lower_s *lower) static void lan9250_disable(const struct lan9250_lower_s *lower) { - int irq = ESP32S3_PIN2IRQ(LAN9250_IRQ); - ninfo("Disable the interrupt\n"); - esp32s3_gpioirqdisable(irq); + esp_gpioirqdisable(LAN9250_IRQ); } /**************************************************************************** @@ -283,8 +276,11 @@ int esp32s3_lan9250_initialize(int port) { int ret; - esp32s3_configgpio(LAN9250_IRQ, INPUT_FUNCTION_2 | PULLUP); - esp32s3_configgpio(LAN9250_RST, OUTPUT_FUNCTION_2 | PULLUP); + /* Configure the interrupt for rising and falling edges */ + + esp_configgpio(LAN9250_IRQ, INPUT_FUNCTION_2 | PULLUP | ONLOW); + + esp_configgpio(LAN9250_RST, OUTPUT_FUNCTION_2 | PULLUP); #ifdef CONFIG_LAN9250_SPI g_dev = esp32s3_spibus_initialize(port); @@ -331,10 +327,8 @@ int esp32s3_lan9250_initialize(int port) int esp32s3_lan9250_uninitialize(int port) { int ret; - int irq; - irq = ESP32S3_PIN2IRQ(LAN9250_IRQ); - esp32s3_gpioirqdisable(irq); + esp_gpioirqdisable(LAN9250_IRQ); #ifdef CONFIG_LAN9250_SPI ret = esp32s3_spibus_uninitialize((struct spi_dev_s *)g_dev); diff --git a/boards/xtensa/esp32s3/esp32s3-8048S043/configs/gpio/defconfig b/boards/xtensa/esp32s3/esp32s3-8048S043/configs/gpio/defconfig index fe95018e07767..f4be7cdcea3e2 100644 --- a/boards/xtensa/esp32s3/esp32s3-8048S043/configs/gpio/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-8048S043/configs/gpio/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/esp32s3-8048S043/configs/i2c/defconfig b/boards/xtensa/esp32s3/esp32s3-8048S043/configs/i2c/defconfig index 8a94a971ada9c..23c9511d42b10 100644 --- a/boards/xtensa/esp32s3/esp32s3-8048S043/configs/i2c/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-8048S043/configs/i2c/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/esp32s3-8048S043/configs/lcd/defconfig b/boards/xtensa/esp32s3/esp32s3-8048S043/configs/lcd/defconfig index b57872857c65e..a1bced925d540 100644 --- a/boards/xtensa/esp32s3/esp32s3-8048S043/configs/lcd/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-8048S043/configs/lcd/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/esp32s3-8048S043/configs/nsh/defconfig b/boards/xtensa/esp32s3/esp32s3-8048S043/configs/nsh/defconfig index dd7256c048c56..e3cd0c45df2b7 100644 --- a/boards/xtensa/esp32s3/esp32s3-8048S043/configs/nsh/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-8048S043/configs/nsh/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/esp32s3-8048S043/configs/sdmmc/defconfig b/boards/xtensa/esp32s3/esp32s3-8048S043/configs/sdmmc/defconfig index 9e12de69c26c8..3f63d05717eef 100644 --- a/boards/xtensa/esp32s3/esp32s3-8048S043/configs/sdmmc/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-8048S043/configs/sdmmc/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/esp32s3-8048S043/configs/spi/defconfig b/boards/xtensa/esp32s3/esp32s3-8048S043/configs/spi/defconfig index ffad5c7733b6c..1b0259e906e5d 100644 --- a/boards/xtensa/esp32s3/esp32s3-8048S043/configs/spi/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-8048S043/configs/spi/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/esp32s3-8048S043/configs/touchscreen/defconfig b/boards/xtensa/esp32s3/esp32s3-8048S043/configs/touchscreen/defconfig index 165b919651a2b..c98d6c1b63480 100644 --- a/boards/xtensa/esp32s3/esp32s3-8048S043/configs/touchscreen/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-8048S043/configs/touchscreen/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/esp32s3-8048S043/src/esp32s3_board_spi.c b/boards/xtensa/esp32s3/esp32s3-8048S043/src/esp32s3_board_spi.c index c7546c6556f01..61951bd23d850 100644 --- a/boards/xtensa/esp32s3/esp32s3-8048S043/src/esp32s3_board_spi.c +++ b/boards/xtensa/esp32s3/esp32s3-8048S043/src/esp32s3_board_spi.c @@ -32,7 +32,7 @@ #include -#include "esp32s3_gpio.h" +#include "espressif/esp_gpio.h" #include "esp32s3-8048S043.h" /**************************************************************************** diff --git a/boards/xtensa/esp32s3/esp32s3-8048S043/src/esp32s3_board_touchsceen.c b/boards/xtensa/esp32s3/esp32s3-8048S043/src/esp32s3_board_touchsceen.c index 1007cd4cb0967..c186d810db3d9 100644 --- a/boards/xtensa/esp32s3/esp32s3-8048S043/src/esp32s3_board_touchsceen.c +++ b/boards/xtensa/esp32s3/esp32s3-8048S043/src/esp32s3_board_touchsceen.c @@ -36,7 +36,7 @@ #include #include "esp32s3_i2c.h" -#include "esp32s3_gpio.h" +#include "espressif/esp_gpio.h" #include "hardware/esp32s3_gpio_sigmap.h" #include "esp32s3-8048S043.h" diff --git a/boards/xtensa/esp32s3/esp32s3-8048S043/src/esp32s3_bringup.c b/boards/xtensa/esp32s3/esp32s3-8048S043/src/esp32s3_bringup.c index bd96835102cec..e1d4ad28d76ee 100644 --- a/boards/xtensa/esp32s3/esp32s3-8048S043/src/esp32s3_bringup.c +++ b/boards/xtensa/esp32s3/esp32s3-8048S043/src/esp32s3_bringup.c @@ -40,6 +40,9 @@ #include #include +#include "espressif/esp_gpio.h" +#include "esp32s3_start.h" + #ifdef CONFIG_ESP32S3_I2C # include "esp32s3_i2c.h" #endif @@ -49,7 +52,11 @@ #endif #ifdef CONFIG_RTC_DRIVER -# include "esp32s3_rtc_lowerhalf.h" +# include "espressif/esp_rtc.h" +#endif + +#ifdef CONFIG_ESPRESSIF_HR_TIMER +# include "espressif/esp_hr_timer.h" #endif #ifdef CONFIG_ESPRESSIF_EFUSE @@ -109,6 +116,14 @@ int esp32s3_bringup(void) { int ret; +#ifdef CONFIG_ESPRESSIF_HR_TIMER + ret = esp_hr_timer_init(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: esp_hr_timer_init() failed: %d\n", ret); + } +#endif + #if defined(CONFIG_ESP32S3_SPIRAM) && \ defined(CONFIG_ESP32S3_SPIRAM_BANKSWITCH_ENABLE) ret = esp_himem_init(); @@ -195,7 +210,7 @@ int esp32s3_bringup(void) #ifdef CONFIG_RTC_DRIVER /* Instantiate the ESP32-S3 RTC driver */ - ret = esp32s3_rtc_driverinit(); + ret = esp_rtc_driverinit(); if (ret < 0) { syslog(LOG_ERR, diff --git a/boards/xtensa/esp32s3/esp32s3-8048S043/src/esp32s3_buttons.c b/boards/xtensa/esp32s3/esp32s3-8048S043/src/esp32s3_buttons.c index 1bb8d4e82f0cf..581f4c6be8895 100644 --- a/boards/xtensa/esp32s3/esp32s3-8048S043/src/esp32s3_buttons.c +++ b/boards/xtensa/esp32s3/esp32s3-8048S043/src/esp32s3_buttons.c @@ -34,7 +34,7 @@ #include #include -#include "esp32s3_gpio.h" +#include "espressif/esp_gpio.h" #include "hardware/esp32s3_gpio_sigmap.h" #include "esp32s3-8048S043.h" @@ -56,7 +56,7 @@ uint32_t board_button_initialize(void) { - esp32s3_configgpio(BUTTON_BOOT, INPUT_FUNCTION_2 | PULLUP); + esp_configgpio(BUTTON_BOOT, INPUT_FUNCTION_2 | PULLUP | CHANGE); return 1; } @@ -77,13 +77,13 @@ uint32_t board_buttons(void) int i = 0; int n = 0; - bool b0 = esp32s3_gpioread(BUTTON_BOOT); + bool b0 = esp_gpioread(BUTTON_BOOT); for (i = 0; i < 10; i++) { up_mdelay(1); - bool b1 = esp32s3_gpioread(BUTTON_BOOT); + bool b1 = esp_gpioread(BUTTON_BOOT); if (b0 == b1) { @@ -129,38 +129,6 @@ uint32_t board_buttons(void) #ifdef CONFIG_ARCH_IRQBUTTONS int board_button_irq(int id, xcpt_t irqhandler, void *arg) { - int ret; - DEBUGASSERT(id == 0); - - int irq = ESP32S3_PIN2IRQ(BUTTON_BOOT); - - if (irqhandler != NULL) - { - /* Make sure the interrupt is disabled */ - - esp32s3_gpioirqdisable(irq); - - ret = irq_attach(irq, irqhandler, arg); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: irq_attach() failed: %d\n", ret); - return ret; - } - - gpioinfo("Attach %p\n", irqhandler); - - gpioinfo("Enabling the interrupt\n"); - - /* Configure the interrupt for rising and falling edges */ - - esp32s3_gpioirqenable(irq, CHANGE); - } - else - { - gpioinfo("Disable the interrupt\n"); - esp32s3_gpioirqdisable(irq); - } - - return OK; + return esp_gpio_irq(BUTTON_BOOT, irqhandler, arg); } #endif diff --git a/boards/xtensa/esp32s3/esp32s3-8048S043/src/esp32s3_gpio.c b/boards/xtensa/esp32s3/esp32s3-8048S043/src/esp32s3_gpio.c index fcc802bb7c5c8..a430388c2a4bc 100644 --- a/boards/xtensa/esp32s3/esp32s3-8048S043/src/esp32s3_gpio.c +++ b/boards/xtensa/esp32s3/esp32s3-8048S043/src/esp32s3_gpio.c @@ -36,8 +36,8 @@ #include +#include "espressif/esp_gpio.h" #include "esp32s3-8048S043.h" -#include "esp32s3_gpio.h" #include "hardware/esp32s3_gpio_sigmap.h" #ifdef CONFIG_ESPRESSIF_DEDICATED_GPIO @@ -50,7 +50,7 @@ * Pre-processor Definitions ****************************************************************************/ -#if !defined(CONFIG_ESP32S3_GPIO_IRQ) && BOARD_NGPIOINT > 0 +#if !defined(CONFIG_ESPRESSIF_GPIO_IRQ) && BOARD_NGPIOINT > 0 # error "NGPIOINT is > 0 and GPIO interrupts aren't enabled" #endif @@ -66,11 +66,11 @@ #define GPIO_IN1 18 -/* Interrupt pins. GPIO21 is used as an example, any other inputs could be - * used. +/* Interrupt pins. GPIO0 is used as an example, any other inputs could be + * used. This is the BOOT button. */ -#define GPIO_IRQPIN1 21 +#define GPIO_IRQPIN1 0 /* Dedicated GPIO pins. GPIO4 and GPIO5 is used as an example, any other * GPIOs could be used. @@ -221,7 +221,7 @@ static int gpout_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(esp32s3gpio->id < BOARD_NGPIOOUT); gpioinfo("Reading...\n"); - *value = esp32s3_gpioread(g_gpiooutputs[esp32s3gpio->id]); + *value = esp_gpioread(g_gpiooutputs[esp32s3gpio->id]); return OK; } @@ -237,7 +237,7 @@ static int gpout_write(struct gpio_dev_s *dev, bool value) DEBUGASSERT(esp32s3gpio->id < BOARD_NGPIOOUT); gpioinfo("Writing %d\n", (int)value); - esp32s3_gpiowrite(g_gpiooutputs[esp32s3gpio->id], value); + esp_gpiowrite(g_gpiooutputs[esp32s3gpio->id], value); return OK; } #endif @@ -255,7 +255,7 @@ static int gpin_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(esp32s3gpio->id < BOARD_NGPIOIN); gpioinfo("Reading... pin %" PRIu32 "\n", g_gpioinputs[esp32s3gpio->id]); - *value = esp32s3_gpioread(g_gpioinputs[esp32s3gpio->id]); + *value = esp_gpioread(g_gpioinputs[esp32s3gpio->id]); return OK; } #endif @@ -289,7 +289,7 @@ static int gpint_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(esp32s3gpint->esp32s3gpio.id < BOARD_NGPIOINT); gpioinfo("Reading int pin...\n"); - *value = esp32s3_gpioread(g_gpiointinputs[esp32s3gpint->esp32s3gpio.id]); + *value = esp_gpioread(g_gpiointinputs[esp32s3gpint->esp32s3gpio.id]); return OK; } @@ -302,23 +302,27 @@ static int gpint_attach(struct gpio_dev_s *dev, { struct esp32s3gpint_dev_s *esp32s3gpint = (struct esp32s3gpint_dev_s *)dev; - int irq = ESP32S3_PIN2IRQ(g_gpiointinputs[esp32s3gpint->esp32s3gpio.id]); int ret; gpioinfo("Attaching the callback\n"); /* Make sure the interrupt is disabled */ - esp32s3_gpioirqdisable(irq); - ret = irq_attach(irq, - esp32s3gpio_interrupt, - &g_gpint[esp32s3gpint->esp32s3gpio.id]); + esp_gpioirqdisable(g_gpiointinputs[esp32s3gpint->esp32s3gpio.id]); + + ret = esp_gpio_irq(g_gpiointinputs[esp32s3gpint->esp32s3gpio.id], + esp32s3gpio_interrupt, + &g_gpint[esp32s3gpint->esp32s3gpio.id]); if (ret < 0) { syslog(LOG_ERR, "ERROR: gpint_attach() failed: %d\n", ret); return ret; } + /* Make sure the interrupt is disabled */ + + esp_gpioirqdisable(g_gpiointinputs[esp32s3gpint->esp32s3gpio.id]); + gpioinfo("Attach %p\n", callback); esp32s3gpint->callback = callback; return OK; @@ -331,7 +335,6 @@ static int gpint_attach(struct gpio_dev_s *dev, static int gpint_enable(struct gpio_dev_s *dev, bool enable) { struct esp32s3gpint_dev_s *esp32s3gpint = (struct esp32s3gpint_dev_s *)dev; - int irq = ESP32S3_PIN2IRQ(g_gpiointinputs[esp32s3gpint->esp32s3gpio.id]); if (enable) { @@ -341,13 +344,13 @@ static int gpint_enable(struct gpio_dev_s *dev, bool enable) /* Configure the interrupt for rising edge */ - esp32s3_gpioirqenable(irq, RISING); + esp_gpioirqenable(g_gpiointinputs[esp32s3gpint->esp32s3gpio.id]); } } else { gpioinfo("Disable the interrupt\n"); - esp32s3_gpioirqdisable(irq); + esp_gpioirqdisable(g_gpiointinputs[esp32s3gpint->esp32s3gpio.id]); } return OK; @@ -379,10 +382,9 @@ int esp32s3_gpio_init(void) /* Configure the pins that will be used as output */ - esp32s3_gpio_matrix_out(g_gpiooutputs[i], SIG_GPIO_OUT_IDX, 0, 0); - esp32s3_configgpio(g_gpiooutputs[i], OUTPUT_FUNCTION_2 | - INPUT_FUNCTION_2); - esp32s3_gpiowrite(g_gpiooutputs[i], 0); + esp_gpio_matrix_out(g_gpiooutputs[i], SIG_GPIO_OUT_IDX, 0, 0); + esp_configgpio(g_gpiooutputs[i], OUTPUT_FUNCTION_2 | INPUT_FUNCTION_2); + esp_gpiowrite(g_gpiooutputs[i], 0); pincount++; } @@ -400,7 +402,7 @@ int esp32s3_gpio_init(void) /* Configure the pins that will be used as INPUT */ - esp32s3_configgpio(g_gpioinputs[i], INPUT_FUNCTION_2); + esp_configgpio(g_gpioinputs[i], INPUT_FUNCTION_2); pincount++; } @@ -418,8 +420,8 @@ int esp32s3_gpio_init(void) /* Configure the pins that will be used as interrupt input */ - esp32s3_configgpio(g_gpiointinputs[i], INPUT_FUNCTION_2 | PULLDOWN); - + esp_configgpio(g_gpiointinputs[i], + INPUT_FUNCTION_2 | PULLUP | FALLING); pincount++; } #endif diff --git a/boards/xtensa/esp32s3/esp32s3-8048S043/src/esp32s3_lcd.c b/boards/xtensa/esp32s3/esp32s3-8048S043/src/esp32s3_lcd.c index 7c378fd5af8be..634d90dd826e3 100644 --- a/boards/xtensa/esp32s3/esp32s3-8048S043/src/esp32s3_lcd.c +++ b/boards/xtensa/esp32s3/esp32s3-8048S043/src/esp32s3_lcd.c @@ -36,7 +36,7 @@ #include #include -#include "esp32s3_gpio.h" +#include "espressif/esp_gpio.h" #include "esp32s3-8048S043.h" /**************************************************************************** @@ -81,8 +81,8 @@ int board_lcd_initialize(void) { int ret; - esp32s3_configgpio(ESP32S3_DISPLAY_BCKL, OUTPUT); - esp32s3_gpiowrite(ESP32S3_DISPLAY_BCKL, true); + esp_configgpio(ESP32S3_DISPLAY_BCKL, OUTPUT); + esp_gpiowrite(ESP32S3_DISPLAY_BCKL, true); #ifdef CONFIG_VIDEO_FB /* Initialize and register the framebuffer driver */ diff --git a/boards/xtensa/esp32s3/esp32s3-box/configs/buttons/defconfig b/boards/xtensa/esp32s3/esp32s3-box/configs/buttons/defconfig index 3abd32c40a797..13b00fb039957 100644 --- a/boards/xtensa/esp32s3/esp32s3-box/configs/buttons/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-box/configs/buttons/defconfig @@ -19,6 +19,9 @@ CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM2N16R8V=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/esp32s3-box/configs/lvgl-3/defconfig b/boards/xtensa/esp32s3/esp32s3-box/configs/lvgl-3/defconfig index c5cb1f72b563b..76188d6d84bb1 100644 --- a/boards/xtensa/esp32s3/esp32s3-box/configs/lvgl-3/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-box/configs/lvgl-3/defconfig @@ -19,6 +19,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM2N16R8V=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/esp32s3-box/configs/lvgl/defconfig b/boards/xtensa/esp32s3/esp32s3-box/configs/lvgl/defconfig index 6e379e6171782..d02c00a129920 100644 --- a/boards/xtensa/esp32s3/esp32s3-box/configs/lvgl/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-box/configs/lvgl/defconfig @@ -19,6 +19,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM2N16R8V=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/esp32s3-box/configs/nsh/defconfig b/boards/xtensa/esp32s3/esp32s3-box/configs/nsh/defconfig index 54baafa8374c7..4a2b4b3477f18 100644 --- a/boards/xtensa/esp32s3/esp32s3-box/configs/nsh/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-box/configs/nsh/defconfig @@ -17,6 +17,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM2N16R8V=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/esp32s3-box/configs/touchscreen/defconfig b/boards/xtensa/esp32s3/esp32s3-box/configs/touchscreen/defconfig index 476383ea0b2ee..ec00392fe973a 100644 --- a/boards/xtensa/esp32s3/esp32s3-box/configs/touchscreen/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-box/configs/touchscreen/defconfig @@ -17,6 +17,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM2N16R8V=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/esp32s3-box/src/esp32s3_board_lcd_ili9342c.c b/boards/xtensa/esp32s3/esp32s3-box/src/esp32s3_board_lcd_ili9342c.c index feb41a01a3ebd..e5efb424b7642 100644 --- a/boards/xtensa/esp32s3/esp32s3-box/src/esp32s3_board_lcd_ili9342c.c +++ b/boards/xtensa/esp32s3/esp32s3-box/src/esp32s3_board_lcd_ili9342c.c @@ -42,7 +42,7 @@ #include -#include "esp32s3_gpio.h" +#include "espressif/esp_gpio.h" #include "esp32s3_spi.h" #include "hardware/esp32s3_gpio_sigmap.h" @@ -488,21 +488,21 @@ static struct ili9341_lcd_s *esp32s3_initializa_ili9342c(int spi_port) /* Initialize non-SPI GPIOs */ - esp32s3_configgpio(DISPLAY_DC, OUTPUT); - esp32s3_configgpio(DISPLAY_RST, OUTPUT); - esp32s3_configgpio(DISPLAY_BCKL, OUTPUT); + esp_configgpio(DISPLAY_DC, OUTPUT); + esp_configgpio(DISPLAY_RST, OUTPUT); + esp_configgpio(DISPLAY_BCKL, OUTPUT); /* Reset LCD */ nxsched_usleep(10 * 1000); - esp32s3_gpiowrite(DISPLAY_RST, true); + esp_gpiowrite(DISPLAY_RST, true); nxsched_usleep(10 * 1000); - esp32s3_gpiowrite(DISPLAY_RST, false); + esp_gpiowrite(DISPLAY_RST, false); nxsched_usleep(50 * 1000); /* Turn on LCD backlight */ - esp32s3_gpiowrite(DISPLAY_BCKL, true); + esp_gpiowrite(DISPLAY_BCKL, true); g_lcddev.spi_dev = esp32s3_spibus_initialize(spi_port); if (!g_lcddev.spi_dev) @@ -547,7 +547,9 @@ static void ili9342c_configure(struct ili9341_lcd_s *lcd, lcd->sendcmd(lcd, cmd); if (data_bytes) { - for (int i = 0; i < data_bytes; i++) + int i; + + for (i = 0; i < data_bytes; i++) { lcd->sendparam(lcd, data[i]); } @@ -576,6 +578,7 @@ static void ili9342c_configure(struct ili9341_lcd_s *lcd, int board_lcd_initialize(void) { struct ili9341_lcd_s *ili9342c_lcd; + int i; ili9342c_lcd = esp32s3_initializa_ili9342c(DISPLAY_SPI); if (!ili9342c_lcd) @@ -591,7 +594,7 @@ int board_lcd_initialize(void) return -ENODEV; } - for (int i = 0; i < nitems(g_lcd_config); i++) + for (i = 0; i < nitems(g_lcd_config); i++) { ili9342c_configure(ili9342c_lcd, g_lcd_config[i].cmd, diff --git a/boards/xtensa/esp32s3/esp32s3-box/src/esp32s3_board_lcd_st7789.c b/boards/xtensa/esp32s3/esp32s3-box/src/esp32s3_board_lcd_st7789.c index 4326144b78ab6..ec9f82afea54a 100644 --- a/boards/xtensa/esp32s3/esp32s3-box/src/esp32s3_board_lcd_st7789.c +++ b/boards/xtensa/esp32s3/esp32s3-box/src/esp32s3_board_lcd_st7789.c @@ -40,7 +40,7 @@ #include -#include "esp32s3_gpio.h" +#include "espressif/esp_gpio.h" #include "esp32s3_spi.h" #include "hardware/esp32s3_gpio_sigmap.h" @@ -78,20 +78,20 @@ int board_lcd_initialize(void) { /* Initialize non-SPI GPIOs */ - esp32s3_configgpio(DISPLAY_DC, OUTPUT); - esp32s3_configgpio(DISPLAY_RST, OUTPUT); - esp32s3_configgpio(DISPLAY_BCKL, OUTPUT); + esp_configgpio(DISPLAY_DC, OUTPUT); + esp_configgpio(DISPLAY_RST, OUTPUT); + esp_configgpio(DISPLAY_BCKL, OUTPUT); /* Reset LCD */ - esp32s3_gpiowrite(DISPLAY_RST, false); + esp_gpiowrite(DISPLAY_RST, false); nxsched_usleep(10 * 1000); - esp32s3_gpiowrite(DISPLAY_RST, true); + esp_gpiowrite(DISPLAY_RST, true); nxsched_usleep(10 * 1000); /* Turn on LCD backlight */ - esp32s3_gpiowrite(DISPLAY_BCKL, true); + esp_gpiowrite(DISPLAY_BCKL, true); g_spidev = esp32s3_spibus_initialize(DISPLAY_SPI); if (!g_spidev) diff --git a/boards/xtensa/esp32s3/esp32s3-box/src/esp32s3_board_spi.c b/boards/xtensa/esp32s3/esp32s3-box/src/esp32s3_board_spi.c index eaed30b67cffe..2e19bfd7be890 100644 --- a/boards/xtensa/esp32s3/esp32s3-box/src/esp32s3_board_spi.c +++ b/boards/xtensa/esp32s3/esp32s3-box/src/esp32s3_board_spi.c @@ -32,7 +32,7 @@ #include -#include "esp32s3_gpio.h" +#include "espressif/esp_gpio.h" #include "esp32s3-box.h" /**************************************************************************** @@ -72,7 +72,7 @@ int esp32s3_spi2_cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) * data bits are data or a command. */ - esp32s3_gpiowrite(DISPLAY_DC, !cmd); + esp_gpiowrite(DISPLAY_DC, !cmd); return OK; } @@ -114,7 +114,7 @@ int esp32s3_spi3_cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) * data bits are data or a command. */ - esp32s3_gpiowrite(CONFIG_ESP32S3_SPI3_MISOPIN, !cmd); + esp_gpiowrite(CONFIG_ESP32S3_SPI3_MISOPIN, !cmd); return OK; } diff --git a/boards/xtensa/esp32s3/esp32s3-box/src/esp32s3_board_touchsceen_gt911.c b/boards/xtensa/esp32s3/esp32s3-box/src/esp32s3_board_touchsceen_gt911.c index fb4a79c12137e..4383794a38f59 100644 --- a/boards/xtensa/esp32s3/esp32s3-box/src/esp32s3_board_touchsceen_gt911.c +++ b/boards/xtensa/esp32s3/esp32s3-box/src/esp32s3_board_touchsceen_gt911.c @@ -36,7 +36,7 @@ #include #include "esp32s3_i2c.h" -#include "esp32s3_gpio.h" +#include "espressif/esp_gpio.h" #include "hardware/esp32s3_gpio_sigmap.h" #include "esp32s3-box.h" diff --git a/boards/xtensa/esp32s3/esp32s3-box/src/esp32s3_board_touchsceen_tt21100.c b/boards/xtensa/esp32s3/esp32s3-box/src/esp32s3_board_touchsceen_tt21100.c index 86b51a58f4e2e..2f001a1809b45 100644 --- a/boards/xtensa/esp32s3/esp32s3-box/src/esp32s3_board_touchsceen_tt21100.c +++ b/boards/xtensa/esp32s3/esp32s3-box/src/esp32s3_board_touchsceen_tt21100.c @@ -36,7 +36,7 @@ #include #include "esp32s3_i2c.h" -#include "esp32s3_gpio.h" +#include "espressif/esp_gpio.h" #include "hardware/esp32s3_gpio_sigmap.h" #include "esp32s3-box.h" diff --git a/boards/xtensa/esp32s3/esp32s3-box/src/esp32s3_bringup.c b/boards/xtensa/esp32s3/esp32s3-box/src/esp32s3_bringup.c index 3a69d4614aa0a..f873c003c6044 100644 --- a/boards/xtensa/esp32s3/esp32s3-box/src/esp32s3_bringup.c +++ b/boards/xtensa/esp32s3/esp32s3-box/src/esp32s3_bringup.c @@ -38,6 +38,9 @@ #include #include +#include "espressif/esp_gpio.h" +#include "esp32s3_start.h" + #ifdef CONFIG_ESP32S3_TIMER # include "esp32s3_board_tim.h" #endif @@ -54,10 +57,6 @@ # include "esp32s3_wifi_adapter.h" #endif -#ifdef CONFIG_ESP32S3_RT_TIMER -# include "esp32s3_rt_timer.h" -#endif - #ifdef CONFIG_WATCHDOG # include "esp32s3_board_wdt.h" #endif @@ -67,7 +66,11 @@ #endif #ifdef CONFIG_RTC_DRIVER -# include "esp32s3_rtc_lowerhalf.h" +# include "espressif/esp_rtc.h" +#endif + +#ifdef CONFIG_ESPRESSIF_HR_TIMER +# include "espressif/esp_hr_timer.h" #endif #ifdef CONFIG_ESPRESSIF_EFUSE @@ -107,6 +110,14 @@ int esp32s3_bringup(void) { int ret; +#ifdef CONFIG_ESPRESSIF_HR_TIMER + ret = esp_hr_timer_init(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: esp_hr_timer_init() failed: %d\n", ret); + } +#endif + #if defined(CONFIG_ESPRESSIF_EFUSE) ret = esp_efuse_initialize("/dev/efuse"); if (ret < 0) @@ -146,18 +157,10 @@ int esp32s3_bringup(void) } #endif -#ifdef CONFIG_ESP32S3_RT_TIMER - ret = esp32s3_rt_timer_init(); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize RT timer: %d\n", ret); - } -#endif - #ifdef CONFIG_RTC_DRIVER /* Instantiate the ESP32-S3 RTC driver */ - ret = esp32s3_rtc_driverinit(); + ret = esp_rtc_driverinit(); if (ret < 0) { syslog(LOG_ERR, diff --git a/boards/xtensa/esp32s3/esp32s3-box/src/esp32s3_buttons.c b/boards/xtensa/esp32s3/esp32s3-box/src/esp32s3_buttons.c index 6fa0638ea5b00..b7b89564b7271 100644 --- a/boards/xtensa/esp32s3/esp32s3-box/src/esp32s3_buttons.c +++ b/boards/xtensa/esp32s3/esp32s3-box/src/esp32s3_buttons.c @@ -34,7 +34,7 @@ #include #include -#include "esp32s3_gpio.h" +#include "espressif/esp_gpio.h" #include "hardware/esp32s3_gpio_sigmap.h" #include "esp32s3-box.h" @@ -56,7 +56,7 @@ uint32_t board_button_initialize(void) { - esp32s3_configgpio(BUTTON_BOOT, INPUT_FUNCTION_2 | PULLUP); + esp_configgpio(BUTTON_BOOT, INPUT_FUNCTION_2 | PULLUP | CHANGE); return 1; } @@ -77,13 +77,13 @@ uint32_t board_buttons(void) int i = 0; int n = 0; - bool b0 = esp32s3_gpioread(BUTTON_BOOT); + bool b0 = esp_gpioread(BUTTON_BOOT); for (i = 0; i < 10; i++) { up_mdelay(1); - bool b1 = esp32s3_gpioread(BUTTON_BOOT); + bool b1 = esp_gpioread(BUTTON_BOOT); if (b0 == b1) { @@ -129,38 +129,6 @@ uint32_t board_buttons(void) #ifdef CONFIG_ARCH_IRQBUTTONS int board_button_irq(int id, xcpt_t irqhandler, void *arg) { - int ret; - DEBUGASSERT(id == 0); - - int irq = ESP32S3_PIN2IRQ(BUTTON_BOOT); - - if (irqhandler != NULL) - { - /* Make sure the interrupt is disabled */ - - esp32s3_gpioirqdisable(irq); - - ret = irq_attach(irq, irqhandler, arg); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: irq_attach() failed: %d\n", ret); - return ret; - } - - gpioinfo("Attach %p\n", irqhandler); - - gpioinfo("Enabling the interrupt\n"); - - /* Configure the interrupt for rising and falling edges */ - - esp32s3_gpioirqenable(irq, CHANGE); - } - else - { - gpioinfo("Disable the interrupt\n"); - esp32s3_gpioirqdisable(irq); - } - - return OK; + return esp_gpio_irq(BUTTON_BOOT, irqhandler, arg); } #endif diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/adc/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/adc/defconfig index b56766f56c2f7..aa2c203a299b6 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/adc/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/adc/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/audio/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/audio/defconfig index 8c37eb9f9654f..21668047a19d5 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/audio/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/audio/defconfig @@ -19,6 +19,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_AUDIO=y @@ -84,6 +87,8 @@ CONFIG_PTHREAD_MUTEX_TYPES=y CONFIG_RAM_SIZE=114688 CONFIG_RAM_START=0x20000000 CONFIG_RR_INTERVAL=200 +CONFIG_RTC=y +CONFIG_RTC_DRIVER=y CONFIG_SCHED_LPWORK=y CONFIG_SCHED_WAITPID=y CONFIG_SMP=y diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/ble/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/ble/defconfig index 5d408ddd24143..e40302c0e9917 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/ble/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/ble/defconfig @@ -18,6 +18,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARDCTL_RESET=y @@ -28,7 +31,6 @@ CONFIG_DEFAULT_TASK_STACKSIZE=4096 CONFIG_DRIVERS_BLUETOOTH=y CONFIG_DRIVERS_IEEE80211=y CONFIG_DRIVERS_WIRELESS=y -CONFIG_ESP32S3_RT_TIMER_TASK_STACK_SIZE=4096 CONFIG_ESP32S3_UART0=y CONFIG_ESPRESSIF_BLE=y CONFIG_FS_LARGEFILE=y @@ -59,6 +61,8 @@ CONFIG_PTHREAD_MUTEX_TYPES=y CONFIG_RAM_SIZE=114688 CONFIG_RAM_START=0x20000000 CONFIG_RR_INTERVAL=200 +CONFIG_RTC=y +CONFIG_RTC_DRIVER=y CONFIG_SCHED_WAITPID=y CONFIG_SIG_DEFAULT=y CONFIG_SPINLOCK=y diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/blewifi/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/blewifi/defconfig index c1a2453890aae..a0adca64f434e 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/blewifi/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/blewifi/defconfig @@ -18,6 +18,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BLUETOOTH_TXCMD_PRIORITY=120 @@ -31,7 +34,6 @@ CONFIG_DEFAULT_TASK_STACKSIZE=4096 CONFIG_DRIVERS_BLUETOOTH=y CONFIG_DRIVERS_IEEE80211=y CONFIG_DRIVERS_WIRELESS=y -CONFIG_ESP32S3_RT_TIMER_TASK_STACK_SIZE=4096 CONFIG_ESP32S3_UART0=y CONFIG_ESPRESSIF_BLE=y CONFIG_ESPRESSIF_WIFI=y @@ -81,6 +83,8 @@ CONFIG_PTHREAD_MUTEX_TYPES=y CONFIG_RAM_SIZE=114688 CONFIG_RAM_START=0x20000000 CONFIG_RR_INTERVAL=200 +CONFIG_RTC=y +CONFIG_RTC_DRIVER=y CONFIG_SCHED_WAITPID=y CONFIG_SIG_DEFAULT=y CONFIG_SPINLOCK=y diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/buttons/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/buttons/defconfig index 18f0837d4b7e1..bc05cd9a63d48 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/buttons/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/buttons/defconfig @@ -18,6 +18,9 @@ CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/capture/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/capture/defconfig index 2e8940b41b476..8f4d6bfd0de6b 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/capture/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/capture/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/coremark/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/coremark/defconfig index e51c8895bf6eb..d121685bab4ad 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/coremark/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/coremark/defconfig @@ -15,6 +15,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_SETJMP_H=y CONFIG_ARCH_XTENSA=y CONFIG_BENCHMARK_COREMARK=y diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/crypto/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/crypto/defconfig index 080d477a806cc..0917cc9a4a6d1 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/crypto/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/crypto/defconfig @@ -20,6 +20,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/cxx/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/cxx/defconfig index 3a94c4af6a2a3..7f3ffd3179817 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/cxx/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/cxx/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/efuse/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/efuse/defconfig index 1dcb98e46944a..30d2dcd068f3b 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/efuse/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/efuse/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/elf/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/elf/defconfig index ae76c348f991a..9fe081e517ba3 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/elf/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/elf/defconfig @@ -17,6 +17,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_USE_COPY_SECTION=y CONFIG_ARCH_XTENSA=y diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/eth_lan9250/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/eth_lan9250/defconfig index 3bcd7fe75d928..3a5d0032c817f 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/eth_lan9250/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/eth_lan9250/defconfig @@ -20,6 +20,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/fastboot/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/fastboot/defconfig index 06788255d48f4..e8789c32425eb 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/fastboot/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/fastboot/defconfig @@ -17,6 +17,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BCH=y @@ -30,7 +33,6 @@ CONFIG_DRIVERS_IEEE80211=y CONFIG_DRIVERS_WIRELESS=y CONFIG_ESP32S3_OTG=y CONFIG_ESP32S3_OTG_ENDPOINT_NUM=2 -CONFIG_ESP32S3_RT_TIMER_TASK_STACK_SIZE=4096 CONFIG_ESP32S3_SPIFLASH=y CONFIG_ESP32S3_SPIFLASH_SPIFFS=y CONFIG_ESP32S3_UART0=y @@ -76,6 +78,8 @@ CONFIG_PTHREAD_MUTEX_TYPES=y CONFIG_RAM_SIZE=114688 CONFIG_RAM_START=0x20000000 CONFIG_RR_INTERVAL=200 +CONFIG_RTC=y +CONFIG_RTC_DRIVER=y CONFIG_SCHED_CHILD_STATUS=y CONFIG_SCHED_HAVE_PARENT=y CONFIG_SCHED_LPWORK=y diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/fastboot_tcp/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/fastboot_tcp/defconfig index 63f02065f53a0..b24c11c7b5cb9 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/fastboot_tcp/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/fastboot_tcp/defconfig @@ -18,6 +18,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 @@ -25,7 +28,6 @@ CONFIG_BUILTIN=y CONFIG_DEFAULT_TASK_STACKSIZE=4096 CONFIG_DRIVERS_IEEE80211=y CONFIG_DRIVERS_WIRELESS=y -CONFIG_ESP32S3_RT_TIMER_TASK_STACK_SIZE=4096 CONFIG_ESP32S3_SPIFLASH=y CONFIG_ESP32S3_SPIFLASH_SPIFFS=y CONFIG_ESP32S3_UART0=y @@ -69,6 +71,8 @@ CONFIG_PTHREAD_MUTEX_TYPES=y CONFIG_RAM_SIZE=114688 CONFIG_RAM_START=0x20000000 CONFIG_RR_INTERVAL=200 +CONFIG_RTC=y +CONFIG_RTC_DRIVER=y CONFIG_SCHED_CHILD_STATUS=y CONFIG_SCHED_HAVE_PARENT=y CONFIG_SCHED_LPWORK=y diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/gpio/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/gpio/defconfig index ec1408f06b310..8bc58d04f569f 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/gpio/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/gpio/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/i2c/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/i2c/defconfig index 3f5c6e4f5b137..47d7ae031ebb9 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/i2c/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/i2c/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/i2schar/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/i2schar/defconfig index fca1c3d2dc628..7778391160f65 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/i2schar/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/i2schar/defconfig @@ -17,6 +17,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_AUDIO=y diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/knsh/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/knsh/defconfig index be3a96e2c58c8..029795e3e9ce6 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/knsh/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/knsh/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/ksta_softap/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/ksta_softap/defconfig index a56ed4cd6d469..761af027a3e1d 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/ksta_softap/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/ksta_softap/defconfig @@ -18,6 +18,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=4096 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARDCTL_RESET=y @@ -27,7 +30,6 @@ CONFIG_BUILTIN=y CONFIG_DEFAULT_TASK_STACKSIZE=4096 CONFIG_DRIVERS_IEEE80211=y CONFIG_DRIVERS_WIRELESS=y -CONFIG_ESP32S3_RT_TIMER_TASK_STACK_SIZE=4096 CONFIG_ESP32S3_SPIFLASH=y CONFIG_ESP32S3_SPIFLASH_SPIFFS=y CONFIG_ESP32S3_STORAGE_MTD_OFFSET=0x200000 @@ -77,6 +79,8 @@ CONFIG_RAM_SIZE=114688 CONFIG_RAM_START=0x20000000 CONFIG_RAW_BINARY=y CONFIG_RR_INTERVAL=200 +CONFIG_RTC=y +CONFIG_RTC_DRIVER=y CONFIG_SCHED_LPWORK=y CONFIG_SCHED_WAITPID=y CONFIG_SIG_DEFAULT=y diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/mbedtls/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/mbedtls/defconfig index 14751c10a8961..48c228c1e5dac 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/mbedtls/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/mbedtls/defconfig @@ -8,7 +8,6 @@ # CONFIG_ARCH_LEDS is not set # CONFIG_NSH_ARGCAT is not set # CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_DATE is not set CONFIG_ALLOW_BSD_COMPONENTS=y CONFIG_ARCH="xtensa" CONFIG_ARCH_BOARD="esp32s3-devkit" @@ -18,6 +17,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM2N32R8V=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 @@ -29,7 +31,6 @@ CONFIG_DRIVERS_IEEE80211=y CONFIG_DRIVERS_WIRELESS=y CONFIG_ESP32S3_FLASH_MODE_OCT=y CONFIG_ESP32S3_FLASH_SAMPLE_MODE_STR=y -CONFIG_ESP32S3_RT_TIMER_TASK_STACK_SIZE=4096 CONFIG_ESP32S3_SPIFLASH=y CONFIG_ESP32S3_SPIRAM=y CONFIG_ESP32S3_SPIRAM_MODE_OCT=y @@ -85,6 +86,8 @@ CONFIG_PTHREAD_MUTEX_TYPES=y CONFIG_RAM_SIZE=114688 CONFIG_RAM_START=0x20000000 CONFIG_RR_INTERVAL=200 +CONFIG_RTC=y +CONFIG_RTC_DRIVER=y CONFIG_SCHED_LPWORK=y CONFIG_SCHED_WAITPID=y CONFIG_SIG_DEFAULT=y diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/mcuboot_nsh/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/mcuboot_nsh/defconfig index f490e6e5da135..5280806f3bac2 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/mcuboot_nsh/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/mcuboot_nsh/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARDCTL_RESET=y diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/mcuboot_update_agent/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/mcuboot_update_agent/defconfig index 470bbda720edb..36f924e3873d1 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/mcuboot_update_agent/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/mcuboot_update_agent/defconfig @@ -18,6 +18,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARDCTL_RESET=y @@ -27,7 +30,6 @@ CONFIG_DEFAULT_TASK_STACKSIZE=4096 CONFIG_DRIVERS_IEEE80211=y CONFIG_DRIVERS_WIRELESS=y CONFIG_ESP32S3_APP_FORMAT_MCUBOOT=y -CONFIG_ESP32S3_RT_TIMER_TASK_STACK_SIZE=4096 CONFIG_ESP32S3_SPIFLASH=y CONFIG_ESP32S3_SPIFLASH_SPIFFS=y CONFIG_ESP32S3_STORAGE_MTD_OFFSET=0x180000 @@ -76,6 +78,8 @@ CONFIG_PTHREAD_MUTEX_TYPES=y CONFIG_RAM_SIZE=114688 CONFIG_RAM_START=0x20000000 CONFIG_RR_INTERVAL=200 +CONFIG_RTC=y +CONFIG_RTC_DRIVER=y CONFIG_SCHED_LPWORK=y CONFIG_SCHED_WAITPID=y CONFIG_SIG_DEFAULT=y diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/motor/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/motor/defconfig index 6c98973d431b2..202010edc54ff 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/motor/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/motor/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/nsh/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/nsh/defconfig index 7914a260061f2..33a0591324130 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/nsh/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/nsh/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/nxlooper/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/nxlooper/defconfig index 3552dc5d8a5d3..ed5c723355fcc 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/nxlooper/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/nxlooper/defconfig @@ -20,6 +20,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=4096 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_AUDIO=y diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/oneshot/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/oneshot/defconfig index 67279e69abac4..de75191a3ea79 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/oneshot/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/oneshot/defconfig @@ -8,7 +8,6 @@ # CONFIG_ARCH_LEDS is not set # CONFIG_NSH_ARGCAT is not set # CONFIG_NSH_CMDOPT_HEXDUMP is not set -CONFIG_ALARM_ARCH=y CONFIG_ARCH="xtensa" CONFIG_ARCH_BOARD="esp32s3-devkit" CONFIG_ARCH_BOARD_COMMON=y @@ -17,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 @@ -55,5 +57,4 @@ CONFIG_START_YEAR=2011 CONFIG_SYSLOG_BUFFER=y CONFIG_SYSTEM_NSH=y CONFIG_TIMER=y -CONFIG_TIMER_ARCH=y CONFIG_UART0_SERIAL_CONSOLE=y diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/ostest/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/ostest/defconfig index 29e65474b34af..068996aebd77d 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/ostest/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/ostest/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_SETJMP_H=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/pm/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/pm/defconfig index 95611ac34cdcf..4230f6fb2cb89 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/pm/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/pm/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 @@ -44,6 +47,8 @@ CONFIG_PREALLOC_TIMERS=4 CONFIG_RAM_SIZE=114688 CONFIG_RAM_START=0x20000000 CONFIG_RR_INTERVAL=200 +CONFIG_RTC=y +CONFIG_RTC_DRIVER=y CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 CONFIG_START_MONTH=12 diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/psram_octal/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/psram_octal/defconfig index 03817d1bf57a6..c6414d7e7fde0 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/psram_octal/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/psram_octal/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/psram_quad/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/psram_quad/defconfig index b3c44da9936f3..3e9513bd97ed8 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/psram_quad/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/psram_quad/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/psram_usrheap/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/psram_usrheap/defconfig index 8863a99ef80a6..34fd44f797731 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/psram_usrheap/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/psram_usrheap/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N8R2=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/pwm/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/pwm/defconfig index d87be5396a776..d8b57c241d9b9 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/pwm/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/pwm/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/python/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/python/defconfig index e68b2e10ec661..5889128709b12 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/python/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/python/defconfig @@ -8,7 +8,6 @@ # CONFIG_ARCH_LEDS is not set # CONFIG_NSH_ARGCAT is not set # CONFIG_NSH_CMDOPT_HEXDUMP is not set -# CONFIG_NSH_DISABLE_DATE is not set CONFIG_ALLOW_BSD_COMPONENTS=y CONFIG_ARCH="xtensa" CONFIG_ARCH_BOARD="esp32s3-devkit" @@ -18,6 +17,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM2N32R8V=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARDCTL_ROMDISK=y @@ -92,6 +94,8 @@ CONFIG_RAM_START=0x20000000 CONFIG_RMT=y CONFIG_RMTCHAR=y CONFIG_RR_INTERVAL=200 +CONFIG_RTC=y +CONFIG_RTC_DRIVER=y CONFIG_SCHED_BACKTRACE=y CONFIG_SCHED_CPULOAD_SYSCLK=y CONFIG_SCHED_LPWORK=y diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/qemu_debug/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/qemu_debug/defconfig index 0e8a7bc5e084f..d835f2b82cf94 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/qemu_debug/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/qemu_debug/defconfig @@ -18,6 +18,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM2N16R8V=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 @@ -29,8 +32,6 @@ CONFIG_DRIVERS_IEEE80211=y CONFIG_DRIVERS_WIRELESS=y CONFIG_ESP32S3_QEMU_IMAGE=y CONFIG_ESP32S3_RNG=y -CONFIG_ESP32S3_RT_TIMER=y -CONFIG_ESP32S3_RT_TIMER_TASK_STACK_SIZE=4096 CONFIG_ESP32S3_SPIFLASH=y CONFIG_ESP32S3_TIMER0=y CONFIG_ESP32S3_UART0=y @@ -77,6 +78,8 @@ CONFIG_PTHREAD_MUTEX_TYPES=y CONFIG_RAM_SIZE=114688 CONFIG_RAM_START=0x20000000 CONFIG_RR_INTERVAL=200 +CONFIG_RTC=y +CONFIG_RTC_DRIVER=y CONFIG_SCHED_LPWORK=y CONFIG_SCHED_WAITPID=y CONFIG_SIG_DEFAULT=y diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/qemu_openeth/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/qemu_openeth/defconfig index 75b367711cc89..9262b87134a29 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/qemu_openeth/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/qemu_openeth/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/qemu_toywasm/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/qemu_toywasm/defconfig index 2515d54c21af2..4f8291a03e02f 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/qemu_toywasm/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/qemu_toywasm/defconfig @@ -18,6 +18,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM2N16R8V=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 @@ -29,8 +32,6 @@ CONFIG_DRIVERS_IEEE80211=y CONFIG_DRIVERS_WIRELESS=y CONFIG_ESP32S3_QEMU_IMAGE=y CONFIG_ESP32S3_RNG=y -CONFIG_ESP32S3_RT_TIMER=y -CONFIG_ESP32S3_RT_TIMER_TASK_STACK_SIZE=4096 CONFIG_ESP32S3_SPIFLASH=y CONFIG_ESP32S3_TIMER0=y CONFIG_ESP32S3_UART0=y @@ -78,6 +79,8 @@ CONFIG_PTHREAD_MUTEX_TYPES=y CONFIG_RAM_SIZE=114688 CONFIG_RAM_START=0x20000000 CONFIG_RR_INTERVAL=200 +CONFIG_RTC=y +CONFIG_RTC_DRIVER=y CONFIG_SCHED_LPWORK=y CONFIG_SCHED_WAITPID=y CONFIG_SIG_DEFAULT=y diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/qencoder/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/qencoder/defconfig index f2a4fee4387dc..55cd4643110ce 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/qencoder/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/qencoder/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/random/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/random/defconfig index 4e9a422f64b71..563ead80bb886 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/random/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/random/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/rmt/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/rmt/defconfig index 8f4f155b04897..80fbd79aa00b2 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/rmt/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/rmt/defconfig @@ -18,6 +18,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/romfs/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/romfs/defconfig index 580378db6810f..975fb2dab5efe 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/romfs/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/romfs/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/rtc/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/rtc/defconfig index 0181b26d36c84..ca7556c4b3384 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/rtc/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/rtc/defconfig @@ -16,11 +16,13 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 CONFIG_BUILTIN=y -CONFIG_ESP32S3_RT_TIMER=y CONFIG_ESP32S3_UART0=y CONFIG_EXAMPLES_ALARM=y CONFIG_FS_PROCFS=y diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/sdm/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/sdm/defconfig index 43f85e9b6a9ac..0dbc391bafd5a 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/sdm/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/sdm/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/sdmmc/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/sdmmc/defconfig index 67b902f7f0d39..6c7502434e1d6 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/sdmmc/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/sdmmc/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/sdmmc_spi/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/sdmmc_spi/defconfig index e0fad37021ea0..cb4a5ab8a2d0b 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/sdmmc_spi/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/sdmmc_spi/defconfig @@ -19,6 +19,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/smp/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/smp/defconfig index 8f1e1d61bb9e0..2123b0c3024be 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/smp/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/smp/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_SETJMP_H=y CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/sotest/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/sotest/defconfig index 5b0a81c138eea..fbd3e6a5f7f8e 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/sotest/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/sotest/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARDCTL_OS_SYMTAB=y diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/spi/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/spi/defconfig index eb0760e9d1d4d..04d998093f0e9 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/spi/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/spi/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/spiflash/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/spiflash/defconfig index 09e083d6cc2ac..826d981741636 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/spiflash/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/spiflash/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/spislv/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/spislv/defconfig index 55e8fa742e78e..5beeccc3eb3b3 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/spislv/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/spislv/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/sta_softap/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/sta_softap/defconfig index 9f569c0bf7312..506df24ab2641 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/sta_softap/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/sta_softap/defconfig @@ -17,6 +17,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 @@ -65,6 +68,8 @@ CONFIG_PTHREAD_MUTEX_TYPES=y CONFIG_RAM_SIZE=114688 CONFIG_RAM_START=0x20000000 CONFIG_RR_INTERVAL=200 +CONFIG_RTC=y +CONFIG_RTC_DRIVER=y CONFIG_SCHED_LPWORK=y CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/stack/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/stack/defconfig index b2e83d8c90da6..c44494db3c315 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/stack/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/stack/defconfig @@ -17,6 +17,9 @@ CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INSTRUMENT_ALL=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 @@ -40,6 +43,8 @@ CONFIG_PREALLOC_TIMERS=4 CONFIG_RAM_SIZE=114688 CONFIG_RAM_START=0x20000000 CONFIG_RR_INTERVAL=200 +CONFIG_RTC=y +CONFIG_RTC_DRIVER=y CONFIG_SCHED_BACKTRACE=y CONFIG_SCHED_STACK_RECORD=32 CONFIG_SCHED_WAITPID=y diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/temperature_sensor/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/temperature_sensor/defconfig index ec634c9efff67..b6a2777d8cc20 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/temperature_sensor/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/temperature_sensor/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/tickless/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/tickless/defconfig index 58f002e06a1e5..78d1747cdfd47 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/tickless/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/tickless/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/timer/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/timer/defconfig index 514cb22dbc97a..33d4c358cdaa9 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/timer/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/timer/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/toywasm/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/toywasm/defconfig index 39aa61fb5e939..01accd8dca242 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/toywasm/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/toywasm/defconfig @@ -17,6 +17,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM2N32R8V=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 @@ -26,7 +29,6 @@ CONFIG_DRIVERS_IEEE80211=y CONFIG_DRIVERS_WIRELESS=y CONFIG_ESP32S3_FLASH_MODE_OCT=y CONFIG_ESP32S3_FLASH_SAMPLE_MODE_STR=y -CONFIG_ESP32S3_RT_TIMER_TASK_STACK_SIZE=4096 CONFIG_ESP32S3_SPIFLASH=y CONFIG_ESP32S3_SPIRAM=y CONFIG_ESP32S3_SPIRAM_MODE_OCT=y @@ -76,6 +78,8 @@ CONFIG_PTHREAD_MUTEX_TYPES=y CONFIG_RAM_SIZE=114688 CONFIG_RAM_START=0x20000000 CONFIG_RR_INTERVAL=200 +CONFIG_RTC=y +CONFIG_RTC_DRIVER=y CONFIG_SCHED_LPWORK=y CONFIG_SCHED_WAITPID=y CONFIG_SIG_DEFAULT=y diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/twai/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/twai/defconfig index 9e0b5b0e72993..dd16896f8311a 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/twai/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/twai/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/ulp/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/ulp/defconfig index e07815741ea14..d98305e766e49 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/ulp/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/ulp/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/usb_device/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/usb_device/defconfig index 65f7faa6931b6..dafea25637050 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/usb_device/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/usb_device/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/usbnsh/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/usbnsh/defconfig index 5e5f10d0bf6b8..6a365c2164756 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/usbnsh/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/usbnsh/defconfig @@ -17,6 +17,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARDCTL_USBDEVCTRL=y diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/watchdog/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/watchdog/defconfig index f66a96c4e4c3b..c12c8b8800c95 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/watchdog/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/watchdog/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/configs/wifi/defconfig b/boards/xtensa/esp32s3/esp32s3-devkit/configs/wifi/defconfig index 5a4fcc82b2f2d..d1f5b7e317f79 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/configs/wifi/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-devkit/configs/wifi/defconfig @@ -17,6 +17,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 @@ -61,6 +64,8 @@ CONFIG_PTHREAD_MUTEX_TYPES=y CONFIG_RAM_SIZE=114688 CONFIG_RAM_START=0x20000000 CONFIG_RR_INTERVAL=200 +CONFIG_RTC=y +CONFIG_RTC_DRIVER=y CONFIG_SCHED_LPWORK=y CONFIG_SCHED_WAITPID=y CONFIG_START_DAY=6 diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/src/Make.defs b/boards/xtensa/esp32s3/esp32s3-devkit/src/Make.defs index bd84d1cbd03b5..65e5a421f3e41 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/src/Make.defs +++ b/boards/xtensa/esp32s3/esp32s3-devkit/src/Make.defs @@ -56,3 +56,11 @@ endif DEPPATH += --dep-path board VPATH += :board CFLAGS += ${INCDIR_PREFIX}$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)board$(DELIM)board + + +ifeq ($(CONFIG_ESPRESSIF_HR_TIMER),y) + CFLAGS += -I$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)chip$(DELIM)esp-hal-3rdparty$(DELIM)components$(DELIM)esp_timer$(DELIM)include +endif + CFLAGS += -I$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)chip$(DELIM)esp-hal-3rdparty$(DELIM)components$(DELIM)esp_system$(DELIM)include + CFLAGS += -I$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)chip$(DELIM)esp-hal-3rdparty$(DELIM)components$(DELIM)esp_common$(DELIM)include + CFLAGS += -I$(TOPDIR)$(DELIM)arch$(DELIM)$(CONFIG_ARCH)$(DELIM)src$(DELIM)chip$(DELIM)esp-hal-3rdparty$(DELIM)nuttx$(DELIM)esp32s3$(DELIM)include diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_board_spi.c b/boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_board_spi.c index 45298b4ef8e74..e5f893fe7f0fd 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_board_spi.c +++ b/boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_board_spi.c @@ -32,7 +32,7 @@ #include -#include "esp32s3_gpio.h" +#include "espressif/esp_gpio.h" #include "esp32s3-devkit.h" /**************************************************************************** @@ -77,7 +77,7 @@ int esp32s3_spi2_cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) * data bits are data or a command. */ - esp32s3_gpiowrite(GPIO_LCD_DC, !cmd); + esp_gpiowrite(GPIO_LCD_DC, !cmd); return OK; } @@ -124,7 +124,7 @@ int esp32s3_spi3_cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) * data bits are data or a command. */ - esp32s3_gpiowrite(CONFIG_ESP32S3_SPI3_MISOPIN, !cmd); + esp_gpiowrite(CONFIG_ESP32S3_SPI3_MISOPIN, !cmd); return OK; } diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_bringup.c b/boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_bringup.c index 428cf70d29d5e..566ecfd55e453 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_bringup.c +++ b/boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_bringup.c @@ -40,6 +40,9 @@ #include #include +#include "espressif/esp_gpio.h" +#include "esp32s3_start.h" + #ifdef CONFIG_ESP32S3_TIMER # include "esp32s3_board_tim.h" #endif @@ -56,10 +59,6 @@ # include "esp32s3_wifi_adapter.h" #endif -#ifdef CONFIG_ESP32S3_RT_TIMER -# include "esp32s3_rt_timer.h" -#endif - #ifdef CONFIG_ESP32S3_I2C # include "esp32s3_i2c.h" #endif @@ -77,7 +76,11 @@ #endif #ifdef CONFIG_RTC_DRIVER -# include "esp32s3_rtc_lowerhalf.h" +# include "espressif/esp_rtc.h" +#endif + +#ifdef CONFIG_ESPRESSIF_HR_TIMER +# include "espressif/esp_hr_timer.h" #endif #ifdef CONFIG_VIDEO_FB @@ -198,6 +201,14 @@ int esp32s3_bringup(void) } #endif +#ifdef CONFIG_ESPRESSIF_HR_TIMER + ret = esp_hr_timer_init(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: esp_hr_timer_init() failed: %d\n", ret); + } +#endif + #if defined(CONFIG_ESP32S3_SPI) && defined(CONFIG_SPI_DRIVER) #if defined(CONFIG_SPI_SLAVE_DRIVER) && defined(CONFIG_ESP32S3_SPI2) @@ -214,7 +225,7 @@ int esp32s3_bringup(void) if (ret < 0) { syslog(LOG_ERR, "Failed to initialize SPI%d Slave driver: %d\n", - ESP32S3_SPI2, ret); + ESP32S3_SPI3, ret); } #endif @@ -326,22 +337,14 @@ int esp32s3_bringup(void) } #endif -#ifdef CONFIG_ESP32S3_RT_TIMER - ret = esp32s3_rt_timer_init(); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize RT timer: %d\n", ret); - } -#endif - #ifdef CONFIG_ESP_RMT - ret = board_rmt_txinitialize(RMT_TXCHANNEL, RMT_OUTPUT_PIN); + ret = board_rmt_txinitialize(RMT_OUTPUT_PIN); if (ret < 0) { syslog(LOG_ERR, "ERROR: board_rmt_txinitialize() failed: %d\n", ret); } - ret = board_rmt_rxinitialize(RMT_RXCHANNEL, RMT_INPUT_PIN); + ret = board_rmt_rxinitialize(RMT_INPUT_PIN); if (ret < 0) { syslog(LOG_ERR, "ERROR: board_rmt_txinitialize() failed: %d\n", ret); @@ -359,9 +362,9 @@ int esp32s3_bringup(void) #endif #ifdef CONFIG_RTC_DRIVER - /* Instantiate the ESP32-S3 RTC driver */ + /* Instantiate the RTC driver */ - ret = esp32s3_rtc_driverinit(); + ret = esp_rtc_driverinit(); if (ret < 0) { syslog(LOG_ERR, diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_buttons.c b/boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_buttons.c index f3d66cb1b2692..d010ff08a501b 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_buttons.c +++ b/boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_buttons.c @@ -34,7 +34,7 @@ #include #include -#include "esp32s3_gpio.h" +#include "espressif/esp_gpio.h" #include "hardware/esp32s3_gpio_sigmap.h" #include "esp32s3-devkit.h" @@ -56,7 +56,7 @@ uint32_t board_button_initialize(void) { - esp32s3_configgpio(BUTTON_BOOT, INPUT_FUNCTION_2 | PULLUP); + esp_configgpio(BUTTON_BOOT, INPUT_FUNCTION_2 | PULLUP | CHANGE); return 1; } @@ -77,13 +77,13 @@ uint32_t board_buttons(void) int i = 0; int n = 0; - bool b0 = esp32s3_gpioread(BUTTON_BOOT); + bool b0 = esp_gpioread(BUTTON_BOOT); for (i = 0; i < 10; i++) { up_mdelay(1); - bool b1 = esp32s3_gpioread(BUTTON_BOOT); + bool b1 = esp_gpioread(BUTTON_BOOT); if (b0 == b1) { @@ -129,38 +129,6 @@ uint32_t board_buttons(void) #ifdef CONFIG_ARCH_IRQBUTTONS int board_button_irq(int id, xcpt_t irqhandler, void *arg) { - int ret; - DEBUGASSERT(id == 0); - - int irq = ESP32S3_PIN2IRQ(BUTTON_BOOT); - - if (irqhandler != NULL) - { - /* Make sure the interrupt is disabled */ - - esp32s3_gpioirqdisable(irq); - - ret = irq_attach(irq, irqhandler, arg); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: irq_attach() failed: %d\n", ret); - return ret; - } - - gpioinfo("Attach %p\n", irqhandler); - - gpioinfo("Enabling the interrupt\n"); - - /* Configure the interrupt for rising and falling edges */ - - esp32s3_gpioirqenable(irq, CHANGE); - } - else - { - gpioinfo("Disable the interrupt\n"); - esp32s3_gpioirqdisable(irq); - } - - return OK; + return esp_gpio_irq(BUTTON_BOOT, irqhandler, arg); } #endif diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_djoystick.c b/boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_djoystick.c index b85f209dba96b..75627be06e1f7 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_djoystick.c +++ b/boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_djoystick.c @@ -34,7 +34,7 @@ #include #include -#include "esp32s3_gpio.h" +#include "espressif/esp_gpio.h" #include "hardware/esp32s3_gpio_sigmap.h" #include "esp32s3-devkit.h" @@ -143,7 +143,7 @@ static djoy_buttonset_t djoy_sample(const struct djoy_lowerhalf_s *lower) for (i = 0; i < DJOY_NGPIOS; i++) { - bool released = esp32s3_gpioread(g_joygpio[i]); + bool released = esp_gpioread(g_joygpio[i]); if (!released) { ret |= (1 << i); @@ -170,6 +170,7 @@ static void djoy_enable(const struct djoy_lowerhalf_s *lower, irqstate_t flags; djoy_buttonset_t either = press | release; djoy_buttonset_t bit; + uint32_t attr; bool rising; bool falling; int i; @@ -199,15 +200,11 @@ static void djoy_enable(const struct djoy_lowerhalf_s *lower, { int ret; - /* Get the irq associated to each pin */ - - int irq = ESP32S3_PIN2IRQ(g_joygpio[i]); - /* Make sure the interrupt is disabled */ - esp32s3_gpioirqdisable(irq); + esp_gpioirqdisable(g_joygpio[i]); - ret = irq_attach(irq, djoy_interrupt, arg); + ret = esp_gpio_irq(g_joygpio[i], djoy_interrupt, arg); if (ret < 0) { leave_critical_section(flags); @@ -220,6 +217,7 @@ static void djoy_enable(const struct djoy_lowerhalf_s *lower, */ bit = (1 << i); + if ((either & bit) != 0) { /* Active low so a press corresponds to a falling edge and @@ -234,16 +232,20 @@ static void djoy_enable(const struct djoy_lowerhalf_s *lower, if (falling != 0 && rising != 0) { - esp32s3_gpioirqenable(irq, CHANGE); + attr = INPUT_FUNCTION_2 | PULLUP | CHANGE; } else if (falling != 0) { - esp32s3_gpioirqenable(irq, GPIO_INTR_NEGEDGE); + attr = INPUT_FUNCTION_2 | PULLUP | FALLING; } else { - esp32s3_gpioirqenable(irq, RISING); + attr = INPUT_FUNCTION_2 | PULLUP | RISING; } + + esp_configgpio(g_joygpio[i], attr); + + esp_gpioirqenable(g_joygpio[i]); } } } @@ -269,13 +271,9 @@ static void djoy_disable(void) flags = enter_critical_section(); for (i = 0; i < DJOY_NGPIOS; i++) { - /* Get the irq associated to each pin */ - - int irq = ESP32S3_PIN2IRQ(g_joygpio[i]); - /* Disable the interrupt */ - esp32s3_gpioirqdisable(irq); + esp_gpioirqdisable(g_joygpio[i]); } leave_critical_section(flags); @@ -325,7 +323,7 @@ int esp32s3_djoy_initialize(void) for (i = 0; i < DJOY_NGPIOS; i++) { - esp32s3_configgpio(g_joygpio[i], INPUT_FUNCTION_2 | PULLUP); + esp_configgpio(g_joygpio[i], INPUT_FUNCTION_2 | PULLUP); } /* Make sure that all interrupts are disabled */ diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_gpio.c b/boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_gpio.c index df71986036cab..67192b2c3cbe4 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_gpio.c +++ b/boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_gpio.c @@ -37,7 +37,7 @@ #include #include "esp32s3-devkit.h" -#include "esp32s3_gpio.h" +#include "espressif/esp_gpio.h" #include "hardware/esp32s3_gpio_sigmap.h" #ifdef CONFIG_ESPRESSIF_DEDICATED_GPIO @@ -54,7 +54,7 @@ * Pre-processor Definitions ****************************************************************************/ -#if !defined(CONFIG_ESP32S3_GPIO_IRQ) && BOARD_NGPIOINT > 0 +#if !defined(CONFIG_ESPRESSIF_GPIO_IRQ) && BOARD_NGPIOINT > 0 # error "NGPIOINT is > 0 and GPIO interrupts aren't enabled" #endif @@ -70,11 +70,11 @@ #define GPIO_IN1 18 -/* Interrupt pins. GPIO21 is used as an example, any other inputs could be - * used. +/* Interrupt pins. GPIO0 is used as an example, any other inputs could be + * used. This is the BOOT button. */ -#define GPIO_IRQPIN1 21 +#define GPIO_IRQPIN1 0 /* Dedicated GPIO pins. GPIO4 and GPIO5 is used as an example, any other * GPIOs could be used. @@ -257,12 +257,12 @@ static struct esp32s3gpio_dev_s g_gprtc[GPIO_RTC_COUNT]; static int gprtc_read(struct gpio_dev_s *dev, bool *value) { - struct esp32s3gpio_dev_s *espgpio = (struct esp32s3gpio_dev_s *)dev; + struct esp32s3gpio_dev_s *esp32s3gpio = (struct esp32s3gpio_dev_s *)dev; - DEBUGASSERT(espgpio != NULL && value != NULL); + DEBUGASSERT(esp32s3gpio != NULL && value != NULL); gpioinfo("Reading...\n"); - *value = esp32s3_rtcioread(g_gpiortc[espgpio->id]); + *value = esp32s3_rtcioread(g_gpiortc[esp32s3gpio->id]); return OK; } @@ -283,12 +283,12 @@ static int gprtc_read(struct gpio_dev_s *dev, bool *value) static int gprtc_write(struct gpio_dev_s *dev, bool value) { - struct esp32s3gpio_dev_s *espgpio = (struct esp32s3gpio_dev_s *)dev; + struct esp32s3gpio_dev_s *esp32s3gpio = (struct esp32s3gpio_dev_s *)dev; - DEBUGASSERT(espgpio != NULL); + DEBUGASSERT(esp32s3gpio != NULL); gpioinfo("Writing %d\n", (int)value); - esp32s3_rtciowrite(g_gpiortc[espgpio->id], value); + esp32s3_rtciowrite(g_gpiortc[esp32s3gpio->id], value); return OK; } #endif @@ -306,7 +306,7 @@ static int gpout_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(esp32s3gpio->id < BOARD_NGPIOOUT); gpioinfo("Reading...\n"); - *value = esp32s3_gpioread(g_gpiooutputs[esp32s3gpio->id]); + *value = esp_gpioread(g_gpiooutputs[esp32s3gpio->id]); return OK; } @@ -322,7 +322,7 @@ static int gpout_write(struct gpio_dev_s *dev, bool value) DEBUGASSERT(esp32s3gpio->id < BOARD_NGPIOOUT); gpioinfo("Writing %d\n", (int)value); - esp32s3_gpiowrite(g_gpiooutputs[esp32s3gpio->id], value); + esp_gpiowrite(g_gpiooutputs[esp32s3gpio->id], value); return OK; } #endif @@ -340,7 +340,7 @@ static int gpin_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(esp32s3gpio->id < BOARD_NGPIOIN); gpioinfo("Reading... pin %" PRIu32 "\n", g_gpioinputs[esp32s3gpio->id]); - *value = esp32s3_gpioread(g_gpioinputs[esp32s3gpio->id]); + *value = esp_gpioread(g_gpioinputs[esp32s3gpio->id]); return OK; } #endif @@ -374,7 +374,7 @@ static int gpint_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(esp32s3gpint->esp32s3gpio.id < BOARD_NGPIOINT); gpioinfo("Reading int pin...\n"); - *value = esp32s3_gpioread(g_gpiointinputs[esp32s3gpint->esp32s3gpio.id]); + *value = esp_gpioread(g_gpiointinputs[esp32s3gpint->esp32s3gpio.id]); return OK; } @@ -387,23 +387,27 @@ static int gpint_attach(struct gpio_dev_s *dev, { struct esp32s3gpint_dev_s *esp32s3gpint = (struct esp32s3gpint_dev_s *)dev; - int irq = ESP32S3_PIN2IRQ(g_gpiointinputs[esp32s3gpint->esp32s3gpio.id]); int ret; gpioinfo("Attaching the callback\n"); /* Make sure the interrupt is disabled */ - esp32s3_gpioirqdisable(irq); - ret = irq_attach(irq, - esp32s3gpio_interrupt, - &g_gpint[esp32s3gpint->esp32s3gpio.id]); + esp_gpioirqdisable(g_gpiointinputs[esp32s3gpint->esp32s3gpio.id]); + + ret = esp_gpio_irq(g_gpiointinputs[esp32s3gpint->esp32s3gpio.id], + esp32s3gpio_interrupt, + &g_gpint[esp32s3gpint->esp32s3gpio.id]); if (ret < 0) { syslog(LOG_ERR, "ERROR: gpint_attach() failed: %d\n", ret); return ret; } + /* Make sure the interrupt is disabled */ + + esp_gpioirqdisable(g_gpiointinputs[esp32s3gpint->esp32s3gpio.id]); + gpioinfo("Attach %p\n", callback); esp32s3gpint->callback = callback; return OK; @@ -416,7 +420,6 @@ static int gpint_attach(struct gpio_dev_s *dev, static int gpint_enable(struct gpio_dev_s *dev, bool enable) { struct esp32s3gpint_dev_s *esp32s3gpint = (struct esp32s3gpint_dev_s *)dev; - int irq = ESP32S3_PIN2IRQ(g_gpiointinputs[esp32s3gpint->esp32s3gpio.id]); if (enable) { @@ -426,13 +429,13 @@ static int gpint_enable(struct gpio_dev_s *dev, bool enable) /* Configure the interrupt for rising edge */ - esp32s3_gpioirqenable(irq, RISING); + esp_gpioirqenable(g_gpiointinputs[esp32s3gpint->esp32s3gpio.id]); } } else { gpioinfo("Disable the interrupt\n"); - esp32s3_gpioirqdisable(irq); + esp_gpioirqdisable(g_gpiointinputs[esp32s3gpint->esp32s3gpio.id]); } return OK; @@ -464,10 +467,9 @@ int esp32s3_gpio_init(void) /* Configure the pins that will be used as output */ - esp32s3_gpio_matrix_out(g_gpiooutputs[i], SIG_GPIO_OUT_IDX, 0, 0); - esp32s3_configgpio(g_gpiooutputs[i], OUTPUT_FUNCTION_2 | - INPUT_FUNCTION_2); - esp32s3_gpiowrite(g_gpiooutputs[i], 0); + esp_gpio_matrix_out(g_gpiooutputs[i], SIG_GPIO_OUT_IDX, 0, 0); + esp_configgpio(g_gpiooutputs[i], OUTPUT_FUNCTION_2 | INPUT_FUNCTION_2); + esp_gpiowrite(g_gpiooutputs[i], 0); pincount++; } @@ -485,7 +487,7 @@ int esp32s3_gpio_init(void) /* Configure the pins that will be used as INPUT */ - esp32s3_configgpio(g_gpioinputs[i], INPUT_FUNCTION_2); + esp_configgpio(g_gpioinputs[i], INPUT_FUNCTION_2 | PULLDOWN); pincount++; } @@ -503,7 +505,8 @@ int esp32s3_gpio_init(void) /* Configure the pins that will be used as interrupt input */ - esp32s3_configgpio(g_gpiointinputs[i], INPUT_FUNCTION_2 | PULLDOWN); + esp_configgpio(g_gpiointinputs[i], + INPUT_FUNCTION_2 | PULLUP | FALLING); pincount++; } diff --git a/boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_st7735.c b/boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_st7735.c index 0a1f823538e23..3be5a673e61b2 100644 --- a/boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_st7735.c +++ b/boards/xtensa/esp32s3/esp32s3-devkit/src/esp32s3_st7735.c @@ -39,7 +39,7 @@ #include #include "esp32s3_spi.h" -#include "esp32s3_gpio.h" +#include "espressif/esp_gpio.h" #include "esp32s3-devkit.h" /**************************************************************************** @@ -80,15 +80,15 @@ int board_lcd_initialize(void) /* Data/Control PIN */ - esp32s3_configgpio(GPIO_LCD_DC, OUTPUT); - esp32s3_gpiowrite(GPIO_LCD_DC, true); + esp_configgpio(GPIO_LCD_DC, OUTPUT); + esp_gpiowrite(GPIO_LCD_DC, true); /* Reset device */ - esp32s3_configgpio(GPIO_LCD_RST, OUTPUT); - esp32s3_gpiowrite(GPIO_LCD_RST, false); + esp_configgpio(GPIO_LCD_RST, OUTPUT); + esp_gpiowrite(GPIO_LCD_RST, false); nxsched_usleep(10000); - esp32s3_gpiowrite(GPIO_LCD_RST, true); + esp_gpiowrite(GPIO_LCD_RST, true); nxsched_usleep(100000); return OK; diff --git a/boards/xtensa/esp32s3/esp32s3-eye/configs/gpio/defconfig b/boards/xtensa/esp32s3/esp32s3-eye/configs/gpio/defconfig index 39def08c7acea..bbd23859db25c 100644 --- a/boards/xtensa/esp32s3/esp32s3-eye/configs/gpio/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-eye/configs/gpio/defconfig @@ -18,6 +18,9 @@ CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/esp32s3-eye/configs/i2c/defconfig b/boards/xtensa/esp32s3/esp32s3-eye/configs/i2c/defconfig index 2e1b7e9ef60cd..16dd6d3423ab7 100644 --- a/boards/xtensa/esp32s3/esp32s3-eye/configs/i2c/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-eye/configs/i2c/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/esp32s3-eye/configs/lcd/defconfig b/boards/xtensa/esp32s3/esp32s3-eye/configs/lcd/defconfig index 2917af3657d59..7f44e77c9bce3 100644 --- a/boards/xtensa/esp32s3/esp32s3-eye/configs/lcd/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-eye/configs/lcd/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/esp32s3-eye/configs/nsh/defconfig b/boards/xtensa/esp32s3/esp32s3-eye/configs/nsh/defconfig index 909e772a70d03..b15511fd4745a 100644 --- a/boards/xtensa/esp32s3/esp32s3-eye/configs/nsh/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-eye/configs/nsh/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/esp32s3-eye/configs/usbnsh/defconfig b/boards/xtensa/esp32s3/esp32s3-eye/configs/usbnsh/defconfig index 880802ca7c380..366deb3add57e 100644 --- a/boards/xtensa/esp32s3/esp32s3-eye/configs/usbnsh/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-eye/configs/usbnsh/defconfig @@ -17,6 +17,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARDCTL_USBDEVCTRL=y diff --git a/boards/xtensa/esp32s3/esp32s3-eye/configs/wifi/defconfig b/boards/xtensa/esp32s3/esp32s3-eye/configs/wifi/defconfig index 3bf1ab869a2d8..af8890892c3e7 100644 --- a/boards/xtensa/esp32s3/esp32s3-eye/configs/wifi/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-eye/configs/wifi/defconfig @@ -18,6 +18,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 @@ -25,7 +28,6 @@ CONFIG_BUILTIN=y CONFIG_DEFAULT_TASK_STACKSIZE=4096 CONFIG_DRIVERS_IEEE80211=y CONFIG_DRIVERS_WIRELESS=y -CONFIG_ESP32S3_RT_TIMER_TASK_STACK_SIZE=4096 CONFIG_ESP32S3_SPIRAM=y CONFIG_ESP32S3_SPIRAM_MODE_OCT=y CONFIG_ESP32S3_USBSERIAL=y @@ -67,6 +69,8 @@ CONFIG_PTHREAD_MUTEX_TYPES=y CONFIG_RAM_SIZE=114688 CONFIG_RAM_START=0x20000000 CONFIG_RR_INTERVAL=200 +CONFIG_RTC=y +CONFIG_RTC_DRIVER=y CONFIG_SCHED_LPWORK=y CONFIG_SCHED_WAITPID=y CONFIG_SIG_DEFAULT=y diff --git a/boards/xtensa/esp32s3/esp32s3-eye/src/esp32s3_board_lcd.c b/boards/xtensa/esp32s3/esp32s3-eye/src/esp32s3_board_lcd.c index 62e75356a138d..13abb83e47d4b 100644 --- a/boards/xtensa/esp32s3/esp32s3-eye/src/esp32s3_board_lcd.c +++ b/boards/xtensa/esp32s3/esp32s3-eye/src/esp32s3_board_lcd.c @@ -40,7 +40,7 @@ #include -#include "esp32s3_gpio.h" +#include "espressif/esp_gpio.h" #include "esp32s3_spi.h" #include "hardware/esp32s3_gpio_sigmap.h" @@ -78,12 +78,12 @@ int board_lcd_initialize(void) { /* Initialize non-SPI GPIOs */ - esp32s3_configgpio(ESP32S3_EYE_DISPLAY_DC, OUTPUT); - esp32s3_configgpio(ESP32S3_EYE_DISPLAY_BCKL, OUTPUT); + esp_configgpio(ESP32S3_EYE_DISPLAY_DC, OUTPUT); + esp_configgpio(ESP32S3_EYE_DISPLAY_BCKL, OUTPUT); /* Turn on LCD backlight */ - esp32s3_gpiowrite(ESP32S3_EYE_DISPLAY_BCKL, false); + esp_gpiowrite(ESP32S3_EYE_DISPLAY_BCKL, false); g_spidev = esp32s3_spibus_initialize(ESP32S3_EYE_DISPLAY_SPI); if (!g_spidev) diff --git a/boards/xtensa/esp32s3/esp32s3-eye/src/esp32s3_board_spi.c b/boards/xtensa/esp32s3/esp32s3-eye/src/esp32s3_board_spi.c index a56c9b04fa2fb..13b38d8d62424 100644 --- a/boards/xtensa/esp32s3/esp32s3-eye/src/esp32s3_board_spi.c +++ b/boards/xtensa/esp32s3/esp32s3-eye/src/esp32s3_board_spi.c @@ -32,7 +32,7 @@ #include -#include "esp32s3_gpio.h" +#include "espressif/esp_gpio.h" #include "esp32s3-eye.h" /**************************************************************************** @@ -72,7 +72,7 @@ int esp32s3_spi2_cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) * data bits are data or a command. */ - esp32s3_gpiowrite(ESP32S3_EYE_DISPLAY_DC, !cmd); + esp_gpiowrite(ESP32S3_EYE_DISPLAY_DC, !cmd); return OK; } @@ -114,7 +114,7 @@ int esp32s3_spi3_cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) * data bits are data or a command. */ - esp32s3_gpiowrite(CONFIG_ESP32S3_SPI3_MISOPIN, !cmd); + esp_gpiowrite(CONFIG_ESP32S3_SPI3_MISOPIN, !cmd); return OK; } diff --git a/boards/xtensa/esp32s3/esp32s3-eye/src/esp32s3_bringup.c b/boards/xtensa/esp32s3/esp32s3-eye/src/esp32s3_bringup.c index 40119eac62e90..b259d66632a5a 100644 --- a/boards/xtensa/esp32s3/esp32s3-eye/src/esp32s3_bringup.c +++ b/boards/xtensa/esp32s3/esp32s3-eye/src/esp32s3_bringup.c @@ -38,6 +38,9 @@ #include #include +#include "espressif/esp_gpio.h" +#include "esp32s3_start.h" + #ifdef CONFIG_ESP32S3_TIMER # include "esp32s3_board_tim.h" #endif @@ -54,10 +57,6 @@ # include "esp32s3_wifi_adapter.h" #endif -#ifdef CONFIG_ESP32S3_RT_TIMER -# include "esp32s3_rt_timer.h" -#endif - #ifdef CONFIG_ESP32S3_I2C # include "esp32s3_i2c.h" #endif @@ -83,6 +82,10 @@ #include "esp32s3_board_sdmmc.h" #endif +#ifdef CONFIG_ESPRESSIF_HR_TIMER +# include "espressif/esp_hr_timer.h" +#endif + #include "esp32s3-eye.h" /**************************************************************************** @@ -107,6 +110,14 @@ int esp32s3_bringup(void) { int ret; +#ifdef CONFIG_ESPRESSIF_HR_TIMER + ret = esp_hr_timer_init(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: esp_hr_timer_init() failed: %d\n", ret); + } +#endif + #ifdef CONFIG_FS_PROCFS /* Mount the procfs file system */ @@ -138,14 +149,6 @@ int esp32s3_bringup(void) } #endif -#ifdef CONFIG_ESP32S3_RT_TIMER - ret = esp32s3_rt_timer_init(); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize RT timer: %d\n", ret); - } -#endif - #ifdef CONFIG_WATCHDOG /* Configure watchdog timer */ diff --git a/boards/xtensa/esp32s3/esp32s3-eye/src/esp32s3_buttons.c b/boards/xtensa/esp32s3/esp32s3-eye/src/esp32s3_buttons.c index 668c15aabb089..5b869617a9078 100644 --- a/boards/xtensa/esp32s3/esp32s3-eye/src/esp32s3_buttons.c +++ b/boards/xtensa/esp32s3/esp32s3-eye/src/esp32s3_buttons.c @@ -34,7 +34,7 @@ #include #include -#include "esp32s3_gpio.h" +#include "espressif/esp_gpio.h" #include "hardware/esp32s3_gpio_sigmap.h" #include "esp32s3-eye.h" @@ -56,7 +56,7 @@ uint32_t board_button_initialize(void) { - esp32s3_configgpio(BUTTON_BOOT, INPUT_FUNCTION_2 | PULLUP); + esp_configgpio(BUTTON_BOOT, INPUT_FUNCTION_2 | PULLUP | CHANGE); return 1; } @@ -77,13 +77,13 @@ uint32_t board_buttons(void) int i = 0; int n = 0; - bool b0 = esp32s3_gpioread(BUTTON_BOOT); + bool b0 = esp_gpioread(BUTTON_BOOT); for (i = 0; i < 10; i++) { up_mdelay(1); - bool b1 = esp32s3_gpioread(BUTTON_BOOT); + bool b1 = esp_gpioread(BUTTON_BOOT); if (b0 == b1) { @@ -129,38 +129,6 @@ uint32_t board_buttons(void) #ifdef CONFIG_ARCH_IRQBUTTONS int board_button_irq(int id, xcpt_t irqhandler, void *arg) { - int ret; - DEBUGASSERT(id == 0); - - int irq = ESP32S3_PIN2IRQ(BUTTON_BOOT); - - if (irqhandler != NULL) - { - /* Make sure the interrupt is disabled */ - - esp32s3_gpioirqdisable(irq); - - ret = irq_attach(irq, irqhandler, arg); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: irq_attach() failed: %d\n", ret); - return ret; - } - - gpioinfo("Attach %p\n", irqhandler); - - gpioinfo("Enabling the interrupt\n"); - - /* Configure the interrupt for rising and falling edges */ - - esp32s3_gpioirqenable(irq, CHANGE); - } - else - { - gpioinfo("Disable the interrupt\n"); - esp32s3_gpioirqdisable(irq); - } - - return OK; + return esp_gpio_irq(BUTTON_BOOT, irqhandler, arg); } #endif diff --git a/boards/xtensa/esp32s3/esp32s3-eye/src/esp32s3_gpio.c b/boards/xtensa/esp32s3/esp32s3-eye/src/esp32s3_gpio.c index 5518847a7153f..4c78f760c1f85 100644 --- a/boards/xtensa/esp32s3/esp32s3-eye/src/esp32s3_gpio.c +++ b/boards/xtensa/esp32s3/esp32s3-eye/src/esp32s3_gpio.c @@ -37,7 +37,7 @@ #include #include "esp32s3-eye.h" -#include "esp32s3_gpio.h" +#include "espressif/esp_gpio.h" #include "hardware/esp32s3_gpio_sigmap.h" #if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF) @@ -46,7 +46,7 @@ * Pre-processor Definitions ****************************************************************************/ -#if !defined(CONFIG_ESP32S3_GPIO_IRQ) && BOARD_NGPIOINT > 0 +#if !defined(CONFIG_ESPRESSIF_GPIO_IRQ) && BOARD_NGPIOINT > 0 # error "NGPIOINT is > 0 and GPIO interrupts aren't enabled" #endif @@ -60,7 +60,8 @@ #define GPIO_IN1 0 -/* Interrupt pins. GPIO0 can be used as an interrupt. +/* Interrupt pins. GPIO0 is used as an example, any other inputs could be + * used. This is the BOOT button. */ #define GPIO_IRQPIN1 0 @@ -179,7 +180,7 @@ static int gpout_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(esp32s3gpio->id < BOARD_NGPIOOUT); gpioinfo("Reading...\n"); - *value = esp32s3_gpioread(g_gpiooutputs[esp32s3gpio->id]); + *value = esp_gpioread(g_gpiooutputs[esp32s3gpio->id]); return OK; } @@ -195,7 +196,7 @@ static int gpout_write(struct gpio_dev_s *dev, bool value) DEBUGASSERT(esp32s3gpio->id < BOARD_NGPIOOUT); gpioinfo("Writing %d\n", (int)value); - esp32s3_gpiowrite(g_gpiooutputs[esp32s3gpio->id], value); + esp_gpiowrite(g_gpiooutputs[esp32s3gpio->id], value); return OK; } #endif @@ -213,7 +214,7 @@ static int gpin_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(esp32s3gpio->id < BOARD_NGPIOIN); gpioinfo("Reading... pin %" PRIu32 "\n", g_gpioinputs[esp32s3gpio->id]); - *value = esp32s3_gpioread(g_gpioinputs[esp32s3gpio->id]); + *value = esp_gpioread(g_gpioinputs[esp32s3gpio->id]); return OK; } #endif @@ -247,7 +248,7 @@ static int gpint_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(esp32s3gpint->esp32s3gpio.id < BOARD_NGPIOINT); gpioinfo("Reading int pin...\n"); - *value = esp32s3_gpioread(g_gpiointinputs[esp32s3gpint->esp32s3gpio.id]); + *value = esp_gpioread(g_gpiointinputs[esp32s3gpint->esp32s3gpio.id]); return OK; } @@ -260,23 +261,27 @@ static int gpint_attach(struct gpio_dev_s *dev, { struct esp32s3gpint_dev_s *esp32s3gpint = (struct esp32s3gpint_dev_s *)dev; - int irq = ESP32S3_PIN2IRQ(g_gpiointinputs[esp32s3gpint->esp32s3gpio.id]); int ret; gpioinfo("Attaching the callback\n"); /* Make sure the interrupt is disabled */ - esp32s3_gpioirqdisable(irq); - ret = irq_attach(irq, - esp32s3gpio_interrupt, - &g_gpint[esp32s3gpint->esp32s3gpio.id]); + esp_gpioirqdisable(g_gpiointinputs[esp32s3gpint->esp32s3gpio.id]); + + ret = esp_gpio_irq(g_gpiointinputs[esp32s3gpint->esp32s3gpio.id], + esp32s3gpio_interrupt, + &g_gpint[esp32s3gpint->esp32s3gpio.id]); if (ret < 0) { syslog(LOG_ERR, "ERROR: gpint_attach() failed: %d\n", ret); return ret; } + /* Make sure the interrupt is disabled */ + + esp_gpioirqdisable(g_gpiointinputs[esp32s3gpint->esp32s3gpio.id]); + gpioinfo("Attach %p\n", callback); esp32s3gpint->callback = callback; return OK; @@ -289,7 +294,6 @@ static int gpint_attach(struct gpio_dev_s *dev, static int gpint_enable(struct gpio_dev_s *dev, bool enable) { struct esp32s3gpint_dev_s *esp32s3gpint = (struct esp32s3gpint_dev_s *)dev; - int irq = ESP32S3_PIN2IRQ(g_gpiointinputs[esp32s3gpint->esp32s3gpio.id]); if (enable) { @@ -299,13 +303,13 @@ static int gpint_enable(struct gpio_dev_s *dev, bool enable) /* Configure the interrupt for rising edge */ - esp32s3_gpioirqenable(irq, RISING); + esp_gpioirqenable(g_gpiointinputs[esp32s3gpint->esp32s3gpio.id]); } } else { gpioinfo("Disable the interrupt\n"); - esp32s3_gpioirqdisable(irq); + esp_gpioirqdisable(g_gpiointinputs[esp32s3gpint->esp32s3gpio.id]); } return OK; @@ -337,10 +341,9 @@ int esp32s3_gpio_init(void) /* Configure the pins that will be used as output */ - esp32s3_gpio_matrix_out(g_gpiooutputs[i], SIG_GPIO_OUT_IDX, 0, 0); - esp32s3_configgpio(g_gpiooutputs[i], OUTPUT_FUNCTION_2 | - INPUT_FUNCTION_2); - esp32s3_gpiowrite(g_gpiooutputs[i], 0); + esp_gpio_matrix_out(g_gpiooutputs[i], SIG_GPIO_OUT_IDX, 0, 0); + esp_configgpio(g_gpiooutputs[i], OUTPUT_FUNCTION_2 | INPUT_FUNCTION_2); + esp_gpiowrite(g_gpiooutputs[i], 0); pincount++; } @@ -358,7 +361,7 @@ int esp32s3_gpio_init(void) /* Configure the pins that will be used as INPUT */ - esp32s3_configgpio(g_gpioinputs[i], INPUT_FUNCTION_2 | PULLUP); + esp_configgpio(g_gpioinputs[i], INPUT_FUNCTION_2 | PULLUP); pincount++; } @@ -376,7 +379,8 @@ int esp32s3_gpio_init(void) /* Configure the pins that will be used as interrupt input */ - esp32s3_configgpio(g_gpiointinputs[i], INPUT_FUNCTION_2 | PULLUP); + esp_configgpio(g_gpiointinputs[i], + INPUT_FUNCTION_2 | PULLUP | FALLING); pincount++; } diff --git a/boards/xtensa/esp32s3/esp32s3-korvo-2/configs/audio/defconfig b/boards/xtensa/esp32s3/esp32s3-korvo-2/configs/audio/defconfig index 95caab3e8f0e2..2d9fb77d7e682 100644 --- a/boards/xtensa/esp32s3/esp32s3-korvo-2/configs/audio/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-korvo-2/configs/audio/defconfig @@ -21,6 +21,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N16R8=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_AUDIO=y @@ -94,6 +97,8 @@ CONFIG_PTHREAD_MUTEX_TYPES=y CONFIG_RAM_SIZE=114688 CONFIG_RAM_START=0x20000000 CONFIG_RR_INTERVAL=200 +CONFIG_RTC=y +CONFIG_RTC_DRIVER=y CONFIG_SCHED_LPWORK=y CONFIG_SCHED_WAITPID=y CONFIG_SMP=y diff --git a/boards/xtensa/esp32s3/esp32s3-korvo-2/configs/nsh/defconfig b/boards/xtensa/esp32s3/esp32s3-korvo-2/configs/nsh/defconfig index ea8fb02d969fe..0f922d001790c 100644 --- a/boards/xtensa/esp32s3/esp32s3-korvo-2/configs/nsh/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-korvo-2/configs/nsh/defconfig @@ -17,6 +17,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N16R8=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/esp32s3-korvo-2/configs/rtptools/defconfig b/boards/xtensa/esp32s3/esp32s3-korvo-2/configs/rtptools/defconfig index 80c08569d8c07..23df8e5044a3a 100644 --- a/boards/xtensa/esp32s3/esp32s3-korvo-2/configs/rtptools/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-korvo-2/configs/rtptools/defconfig @@ -21,6 +21,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N16R8=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_AUDIO=y @@ -96,6 +99,8 @@ CONFIG_PTHREAD_MUTEX_TYPES=y CONFIG_RAM_SIZE=114688 CONFIG_RAM_START=0x20000000 CONFIG_RR_INTERVAL=200 +CONFIG_RTC=y +CONFIG_RTC_DRIVER=y CONFIG_SCHED_LPWORK=y CONFIG_SCHED_WAITPID=y CONFIG_SMP=y diff --git a/boards/xtensa/esp32s3/esp32s3-korvo-2/configs/sdmmc/defconfig b/boards/xtensa/esp32s3/esp32s3-korvo-2/configs/sdmmc/defconfig index 65e079848ba4c..05f0c31263632 100644 --- a/boards/xtensa/esp32s3/esp32s3-korvo-2/configs/sdmmc/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-korvo-2/configs/sdmmc/defconfig @@ -17,6 +17,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N16R8=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/esp32s3-korvo-2/src/esp32s3_board_spi.c b/boards/xtensa/esp32s3/esp32s3-korvo-2/src/esp32s3_board_spi.c index a7e6f5ab0eb4e..62418599c3de6 100644 --- a/boards/xtensa/esp32s3/esp32s3-korvo-2/src/esp32s3_board_spi.c +++ b/boards/xtensa/esp32s3/esp32s3-korvo-2/src/esp32s3_board_spi.c @@ -32,7 +32,7 @@ #include -#include "esp32s3_gpio.h" +#include "espressif/esp_gpio.h" #include "esp32s3-korvo-2.h" /**************************************************************************** @@ -72,7 +72,7 @@ int esp32s3_spi2_cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) * data bits are data or a command. */ - esp32s3_gpiowrite(GPIO_LCD_DC, !cmd); + esp_gpiowrite(GPIO_LCD_DC, !cmd); return OK; } @@ -114,7 +114,7 @@ int esp32s3_spi3_cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) * data bits are data or a command. */ - esp32s3_gpiowrite(CONFIG_ESP32S3_SPI3_MISOPIN, !cmd); + esp_gpiowrite(CONFIG_ESP32S3_SPI3_MISOPIN, !cmd); return OK; } diff --git a/boards/xtensa/esp32s3/esp32s3-korvo-2/src/esp32s3_bringup.c b/boards/xtensa/esp32s3/esp32s3-korvo-2/src/esp32s3_bringup.c index 4164e13551185..e456ccd9b0a80 100644 --- a/boards/xtensa/esp32s3/esp32s3-korvo-2/src/esp32s3_bringup.c +++ b/boards/xtensa/esp32s3/esp32s3-korvo-2/src/esp32s3_bringup.c @@ -39,7 +39,8 @@ #include #include -#include "esp32s3_gpio.h" +#include "espressif/esp_gpio.h" +#include "esp32s3_start.h" #ifdef CONFIG_ESP32S3_TIMER # include "esp32s3_board_tim.h" @@ -57,10 +58,6 @@ # include "esp32s3_wifi_adapter.h" #endif -#ifdef CONFIG_ESP32S3_RT_TIMER -# include "esp32s3_rt_timer.h" -#endif - #ifdef CONFIG_ESP32S3_I2C # include "esp32s3_i2c.h" #endif @@ -78,7 +75,11 @@ #endif #ifdef CONFIG_RTC_DRIVER -# include "esp32s3_rtc_lowerhalf.h" +# include "espressif/esp_rtc.h" +#endif + +#ifdef CONFIG_ESPRESSIF_HR_TIMER +# include "espressif/esp_hr_timer.h" #endif #ifdef CONFIG_ESPRESSIF_EFUSE @@ -141,6 +142,15 @@ int esp32s3_bringup(void) { int ret = OK; + +#ifdef CONFIG_ESPRESSIF_HR_TIMER + ret = esp_hr_timer_init(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: esp_hr_timer_init() failed: %d\n", ret); + } +#endif + #if (defined(CONFIG_ESPRESSIF_I2S0) && !defined(CONFIG_AUDIO_CS4344) && \ !defined(CONFIG_AUDIO_ES8311)) || defined(CONFIG_ESPRESSIF_I2S1) bool i2s_enable_tx; @@ -241,22 +251,14 @@ int esp32s3_bringup(void) } #endif -#ifdef CONFIG_ESP32S3_RT_TIMER - ret = esp32s3_rt_timer_init(); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize RT timer: %d\n", ret); - } -#endif - #ifdef CONFIG_ESP_RMT - ret = board_rmt_txinitialize(RMT_TXCHANNEL, RMT_OUTPUT_PIN); + ret = board_rmt_txinitialize(RMT_OUTPUT_PIN); if (ret < 0) { syslog(LOG_ERR, "ERROR: board_rmt_txinitialize() failed: %d\n", ret); } - ret = board_rmt_rxinitialize(RMT_RXCHANNEL, RMT_INPUT_PIN); + ret = board_rmt_rxinitialize(RMT_INPUT_PIN); if (ret < 0) { syslog(LOG_ERR, "ERROR: board_rmt_txinitialize() failed: %d\n", ret); @@ -266,7 +268,7 @@ int esp32s3_bringup(void) #ifdef CONFIG_RTC_DRIVER /* Instantiate the ESP32-S3 RTC driver */ - ret = esp32s3_rtc_driverinit(); + ret = esp_rtc_driverinit(); if (ret < 0) { syslog(LOG_ERR, @@ -311,8 +313,8 @@ int esp32s3_bringup(void) /* Configure ES8311 audio on I2C0 and I2S0 */ - esp32s3_configgpio(SPEAKER_ENABLE_GPIO, OUTPUT); - esp32s3_gpiowrite(SPEAKER_ENABLE_GPIO, true); + esp_configgpio(SPEAKER_ENABLE_GPIO, OUTPUT); + esp_gpiowrite(SPEAKER_ENABLE_GPIO, true); i2c = esp32s3_i2cbus_initialize(ESP32S3_I2C0); if (i2c == NULL) diff --git a/boards/xtensa/esp32s3/esp32s3-korvo-2/src/esp32s3_buttons.c b/boards/xtensa/esp32s3/esp32s3-korvo-2/src/esp32s3_buttons.c index 9a411cf96ad4d..1fceb887f2535 100644 --- a/boards/xtensa/esp32s3/esp32s3-korvo-2/src/esp32s3_buttons.c +++ b/boards/xtensa/esp32s3/esp32s3-korvo-2/src/esp32s3_buttons.c @@ -34,7 +34,7 @@ #include #include -#include "esp32s3_gpio.h" +#include "espressif/esp_gpio.h" #include "hardware/esp32s3_gpio_sigmap.h" #include "esp32s3-korvo-2.h" @@ -56,7 +56,7 @@ uint32_t board_button_initialize(void) { - esp32s3_configgpio(BUTTON_BOOT, INPUT_FUNCTION_2 | PULLUP); + esp_configgpio(BUTTON_BOOT, INPUT_FUNCTION_2 | PULLUP | CHANGE); return 1; } @@ -77,13 +77,13 @@ uint32_t board_buttons(void) int i = 0; int n = 0; - bool b0 = esp32s3_gpioread(BUTTON_BOOT); + bool b0 = esp_gpioread(BUTTON_BOOT); for (i = 0; i < 10; i++) { up_mdelay(1); - bool b1 = esp32s3_gpioread(BUTTON_BOOT); + bool b1 = esp_gpioread(BUTTON_BOOT); if (b0 == b1) { @@ -129,38 +129,6 @@ uint32_t board_buttons(void) #ifdef CONFIG_ARCH_IRQBUTTONS int board_button_irq(int id, xcpt_t irqhandler, void *arg) { - int ret; - DEBUGASSERT(id == 0); - - int irq = ESP32S3_PIN2IRQ(BUTTON_BOOT); - - if (irqhandler != NULL) - { - /* Make sure the interrupt is disabled */ - - esp32s3_gpioirqdisable(irq); - - ret = irq_attach(irq, irqhandler, arg); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: irq_attach() failed: %d\n", ret); - return ret; - } - - gpioinfo("Attach %p\n", irqhandler); - - gpioinfo("Enabling the interrupt\n"); - - /* Configure the interrupt for rising and falling edges */ - - esp32s3_gpioirqenable(irq, CHANGE); - } - else - { - gpioinfo("Disable the interrupt\n"); - esp32s3_gpioirqdisable(irq); - } - - return OK; + return esp_gpio_irq(BUTTON_BOOT, irqhandler, arg); } #endif diff --git a/boards/xtensa/esp32s3/esp32s3-lcd-ev/configs/audio/defconfig b/boards/xtensa/esp32s3/esp32s3-lcd-ev/configs/audio/defconfig index 45d15197b6751..5ee3f77b703d8 100644 --- a/boards/xtensa/esp32s3/esp32s3-lcd-ev/configs/audio/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-lcd-ev/configs/audio/defconfig @@ -20,6 +20,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM2N16R8V=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_AUDIO=y @@ -87,6 +90,8 @@ CONFIG_PTHREAD_MUTEX_TYPES=y CONFIG_RAM_SIZE=114688 CONFIG_RAM_START=0x20000000 CONFIG_RR_INTERVAL=200 +CONFIG_RTC=y +CONFIG_RTC_DRIVER=y CONFIG_SCHED_LPWORK=y CONFIG_SCHED_WAITPID=y CONFIG_SMP=y diff --git a/boards/xtensa/esp32s3/esp32s3-lcd-ev/configs/buttons/defconfig b/boards/xtensa/esp32s3/esp32s3-lcd-ev/configs/buttons/defconfig index f4c7ab48ec842..38dbd7e5ad12e 100644 --- a/boards/xtensa/esp32s3/esp32s3-lcd-ev/configs/buttons/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-lcd-ev/configs/buttons/defconfig @@ -18,6 +18,9 @@ CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM2N16R8V=y CONFIG_ARCH_INTERRUPTSTACK=2048 CONFIG_ARCH_IRQBUTTONS=y +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/esp32s3-lcd-ev/configs/lcd/defconfig b/boards/xtensa/esp32s3/esp32s3-lcd-ev/configs/lcd/defconfig index 97473b968362e..95a4f1de23f3f 100644 --- a/boards/xtensa/esp32s3/esp32s3-lcd-ev/configs/lcd/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-lcd-ev/configs/lcd/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM2N16R8V=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/esp32s3-lcd-ev/configs/lvgl/defconfig b/boards/xtensa/esp32s3/esp32s3-lcd-ev/configs/lvgl/defconfig index 488367418e973..2bbc86d2a99a1 100644 --- a/boards/xtensa/esp32s3/esp32s3-lcd-ev/configs/lvgl/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-lcd-ev/configs/lvgl/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM2N16R8V=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/esp32s3-lcd-ev/configs/nsh/defconfig b/boards/xtensa/esp32s3/esp32s3-lcd-ev/configs/nsh/defconfig index 49e7d8d37bc4c..bef08fe21b5a5 100644 --- a/boards/xtensa/esp32s3/esp32s3-lcd-ev/configs/nsh/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-lcd-ev/configs/nsh/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM2N16R8V=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/esp32s3-lcd-ev/configs/ws2812/defconfig b/boards/xtensa/esp32s3/esp32s3-lcd-ev/configs/ws2812/defconfig index d5167dab81313..88c69e36b56b1 100644 --- a/boards/xtensa/esp32s3/esp32s3-lcd-ev/configs/ws2812/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-lcd-ev/configs/ws2812/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM2N16R8V=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/esp32s3-lcd-ev/src/esp32s3_board_spi.c b/boards/xtensa/esp32s3/esp32s3-lcd-ev/src/esp32s3_board_spi.c index 80b70c65e6d30..e5a49396c239a 100644 --- a/boards/xtensa/esp32s3/esp32s3-lcd-ev/src/esp32s3_board_spi.c +++ b/boards/xtensa/esp32s3/esp32s3-lcd-ev/src/esp32s3_board_spi.c @@ -32,7 +32,7 @@ #include -#include "esp32s3_gpio.h" +#include "espressif/esp_gpio.h" #include "esp32s3-lcd-ev.h" /**************************************************************************** @@ -72,7 +72,7 @@ int esp32s3_spi2_cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) * data bits are data or a command. */ - esp32s3_gpiowrite(GPIO_LCD_DC, !cmd); + esp_gpiowrite(GPIO_LCD_DC, !cmd); return OK; } @@ -114,7 +114,7 @@ int esp32s3_spi3_cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) * data bits are data or a command. */ - esp32s3_gpiowrite(CONFIG_ESP32S3_SPI3_MISOPIN, !cmd); + esp_gpiowrite(CONFIG_ESP32S3_SPI3_MISOPIN, !cmd); return OK; } diff --git a/boards/xtensa/esp32s3/esp32s3-lcd-ev/src/esp32s3_bringup.c b/boards/xtensa/esp32s3/esp32s3-lcd-ev/src/esp32s3_bringup.c index 3de427b45c91b..75885397b4f8d 100644 --- a/boards/xtensa/esp32s3/esp32s3-lcd-ev/src/esp32s3_bringup.c +++ b/boards/xtensa/esp32s3/esp32s3-lcd-ev/src/esp32s3_bringup.c @@ -39,7 +39,8 @@ #include #include -#include "esp32s3_gpio.h" +#include "espressif/esp_gpio.h" +#include "esp32s3_start.h" #ifdef CONFIG_ESP32S3_TIMER # include "esp32s3_board_tim.h" @@ -65,10 +66,6 @@ # include "espressif/esp_i2s.h" #endif -#ifdef CONFIG_ESP32S3_RT_TIMER -# include "esp32s3_rt_timer.h" -#endif - #ifdef CONFIG_WATCHDOG # include "esp32s3_board_wdt.h" #endif @@ -78,7 +75,11 @@ #endif #ifdef CONFIG_RTC_DRIVER -# include "esp32s3_rtc_lowerhalf.h" +# include "espressif/esp_rtc.h" +#endif + +#ifdef CONFIG_ESPRESSIF_HR_TIMER +# include "espressif/esp_hr_timer.h" #endif #ifdef CONFIG_ESPRESSIF_EFUSE @@ -112,6 +113,15 @@ int esp32s3_bringup(void) { int ret = OK; + +#ifdef CONFIG_ESPRESSIF_HR_TIMER + ret = esp_hr_timer_init(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: esp_hr_timer_init() failed: %d\n", ret); + } +#endif + #if (defined(CONFIG_ESPRESSIF_I2S0) && !defined(CONFIG_AUDIO_CS4344) && \ !defined(CONFIG_AUDIO_ES8311)) || defined(CONFIG_ESPRESSIF_I2S1) bool i2s_enable_tx; @@ -160,18 +170,10 @@ int esp32s3_bringup(void) } #endif -#ifdef CONFIG_ESP32S3_RT_TIMER - ret = esp32s3_rt_timer_init(); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize RT timer: %d\n", ret); - } -#endif - #ifdef CONFIG_RTC_DRIVER /* Instantiate the ESP32-S3 RTC driver */ - ret = esp32s3_rtc_driverinit(); + ret = esp_rtc_driverinit(); if (ret < 0) { syslog(LOG_ERR, @@ -195,8 +197,8 @@ int esp32s3_bringup(void) /* Configure ES8311 audio on I2C0 and I2S0 */ - esp32s3_configgpio(SPEAKER_ENABLE_GPIO, OUTPUT); - esp32s3_gpiowrite(SPEAKER_ENABLE_GPIO, true); + esp_configgpio(SPEAKER_ENABLE_GPIO, OUTPUT); + esp_gpiowrite(SPEAKER_ENABLE_GPIO, true); i2c = esp32s3_i2cbus_initialize(ESP32S3_I2C0); if (i2c == NULL) diff --git a/boards/xtensa/esp32s3/esp32s3-lcd-ev/src/esp32s3_buttons.c b/boards/xtensa/esp32s3/esp32s3-lcd-ev/src/esp32s3_buttons.c index b65e058e69cb1..a6f3bb49efcd1 100644 --- a/boards/xtensa/esp32s3/esp32s3-lcd-ev/src/esp32s3_buttons.c +++ b/boards/xtensa/esp32s3/esp32s3-lcd-ev/src/esp32s3_buttons.c @@ -34,7 +34,7 @@ #include #include -#include "esp32s3_gpio.h" +#include "espressif/esp_gpio.h" #include "hardware/esp32s3_gpio_sigmap.h" #include "esp32s3-lcd-ev.h" @@ -56,7 +56,7 @@ uint32_t board_button_initialize(void) { - esp32s3_configgpio(BUTTON_BOOT, INPUT_FUNCTION_2 | PULLUP); + esp_configgpio(BUTTON_BOOT, INPUT_FUNCTION_2 | PULLUP | CHANGE); return 1; } @@ -77,13 +77,13 @@ uint32_t board_buttons(void) int i = 0; int n = 0; - bool b0 = esp32s3_gpioread(BUTTON_BOOT); + bool b0 = esp_gpioread(BUTTON_BOOT); for (i = 0; i < 10; i++) { up_mdelay(1); - bool b1 = esp32s3_gpioread(BUTTON_BOOT); + bool b1 = esp_gpioread(BUTTON_BOOT); if (b0 == b1) { @@ -129,38 +129,6 @@ uint32_t board_buttons(void) #ifdef CONFIG_ARCH_IRQBUTTONS int board_button_irq(int id, xcpt_t irqhandler, void *arg) { - int ret; - DEBUGASSERT(id == 0); - - int irq = ESP32S3_PIN2IRQ(BUTTON_BOOT); - - if (irqhandler != NULL) - { - /* Make sure the interrupt is disabled */ - - esp32s3_gpioirqdisable(irq); - - ret = irq_attach(irq, irqhandler, arg); - if (ret < 0) - { - syslog(LOG_ERR, "ERROR: irq_attach() failed: %d\n", ret); - return ret; - } - - gpioinfo("Attach %p\n", irqhandler); - - gpioinfo("Enabling the interrupt\n"); - - /* Configure the interrupt for rising and falling edges */ - - esp32s3_gpioirqenable(irq, CHANGE); - } - else - { - gpioinfo("Disable the interrupt\n"); - esp32s3_gpioirqdisable(irq); - } - - return OK; + return esp_gpio_irq(BUTTON_BOOT, irqhandler, arg); } #endif diff --git a/boards/xtensa/esp32s3/esp32s3-lcd-ev/src/esp32s3_lcd.c b/boards/xtensa/esp32s3/esp32s3-lcd-ev/src/esp32s3_lcd.c index e402dc83ef777..65c6c596dc249 100644 --- a/boards/xtensa/esp32s3/esp32s3-lcd-ev/src/esp32s3_lcd.c +++ b/boards/xtensa/esp32s3/esp32s3-lcd-ev/src/esp32s3_lcd.c @@ -36,7 +36,7 @@ #include #include -#include "esp32s3_gpio.h" +#include "espressif/esp_gpio.h" #include "esp32s3-lcd-ev.h" /**************************************************************************** @@ -614,12 +614,14 @@ static void lcd_initialize_spi(void) static void lcd_configure_display(void) { + int i; + /* Pull-up V-SYNC pin to start configuring LCD */ - esp32s3_configgpio(CONFIG_ESP32S3_LCD_VSYNC_PIN, OUTPUT | PULLUP); - esp32s3_gpiowrite(CONFIG_ESP32S3_LCD_VSYNC_PIN, 1); + esp_configgpio(CONFIG_ESP32S3_LCD_VSYNC_PIN, OUTPUT | PULLUP); + esp_gpiowrite(CONFIG_ESP32S3_LCD_VSYNC_PIN, 1); - for (int i = 0; i < nitems(g_lcd_config); i++) + for (i = 0; i < nitems(g_lcd_config); i++) { send_cmd(g_lcd_config[i].cmd); diff --git a/boards/xtensa/esp32s3/esp32s3-lhcbit/configs/usbnsh/defconfig b/boards/xtensa/esp32s3/esp32s3-lhcbit/configs/usbnsh/defconfig index 2d1e8642cfec7..6f282a57b32e3 100644 --- a/boards/xtensa/esp32s3/esp32s3-lhcbit/configs/usbnsh/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-lhcbit/configs/usbnsh/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N16R8=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARDCTL_USBDEVCTRL=y diff --git a/boards/xtensa/esp32s3/esp32s3-lhcbit/src/esp32s3_bringup.c b/boards/xtensa/esp32s3/esp32s3-lhcbit/src/esp32s3_bringup.c index 521368e447d03..0fde785a2c2ba 100644 --- a/boards/xtensa/esp32s3/esp32s3-lhcbit/src/esp32s3_bringup.c +++ b/boards/xtensa/esp32s3/esp32s3-lhcbit/src/esp32s3_bringup.c @@ -40,6 +40,13 @@ #include #include +#include "espressif/esp_gpio.h" +#include "esp32s3_start.h" + +#ifdef CONFIG_ESPRESSIF_HR_TIMER +# include "espressif/esp_hr_timer.h" +#endif + #include "esp32s3-lhcbit.h" /**************************************************************************** @@ -64,6 +71,14 @@ int esp32s3_bringup(void) { int ret; +#ifdef CONFIG_ESPRESSIF_HR_TIMER + ret = esp_hr_timer_init(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: esp_hr_timer_init() failed: %d\n", ret); + } +#endif + #ifdef CONFIG_FS_PROCFS /* Mount the procfs file system */ diff --git a/boards/xtensa/esp32s3/esp32s3-meadow/configs/nsh/defconfig b/boards/xtensa/esp32s3/esp32s3-meadow/configs/nsh/defconfig index 0d1e09b239fd4..498e2b8d4e2ed 100644 --- a/boards/xtensa/esp32s3/esp32s3-meadow/configs/nsh/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-meadow/configs/nsh/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/esp32s3-meadow/configs/usbnsh/defconfig b/boards/xtensa/esp32s3/esp32s3-meadow/configs/usbnsh/defconfig index 8cde231f3a634..ae45ab07eba34 100644 --- a/boards/xtensa/esp32s3/esp32s3-meadow/configs/usbnsh/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-meadow/configs/usbnsh/defconfig @@ -17,6 +17,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N4=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARDCTL_USBDEVCTRL=y diff --git a/boards/xtensa/esp32s3/esp32s3-meadow/src/esp32s3_bringup.c b/boards/xtensa/esp32s3/esp32s3-meadow/src/esp32s3_bringup.c index 2f6624ff0d02f..885d527deead8 100644 --- a/boards/xtensa/esp32s3/esp32s3-meadow/src/esp32s3_bringup.c +++ b/boards/xtensa/esp32s3/esp32s3-meadow/src/esp32s3_bringup.c @@ -38,14 +38,13 @@ #include #include +#include "espressif/esp_gpio.h" +#include "esp32s3_start.h" + #ifdef CONFIG_ESP32S3_TIMER # include "esp32s3_board_tim.h" #endif -#ifdef CONFIG_ESP32S3_RT_TIMER -# include "esp32s3_rt_timer.h" -#endif - #ifdef CONFIG_WATCHDOG # include "esp32s3_board_wdt.h" #endif @@ -54,6 +53,10 @@ # include #endif +#ifdef CONFIG_ESPRESSIF_HR_TIMER +# include "espressif/esp_hr_timer.h" +#endif + #include "esp32s3-meadow.h" /**************************************************************************** @@ -78,6 +81,14 @@ int esp32s3_bringup(void) { int ret; +#ifdef CONFIG_ESPRESSIF_HR_TIMER + ret = esp_hr_timer_init(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: esp_hr_timer_init() failed: %d\n", ret); + } +#endif + #ifdef CONFIG_FS_PROCFS /* Mount the procfs file system */ @@ -109,14 +120,6 @@ int esp32s3_bringup(void) } #endif -#ifdef CONFIG_ESP32S3_RT_TIMER - ret = esp32s3_rt_timer_init(); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize RT timer: %d\n", ret); - } -#endif - #ifdef CONFIG_WATCHDOG /* Configure watchdog timer */ diff --git a/boards/xtensa/esp32s3/esp32s3-xiao/configs/combo/defconfig b/boards/xtensa/esp32s3/esp32s3-xiao/configs/combo/defconfig index 9ac64ab9cb990..8d4ebbfbaa2ad 100644 --- a/boards/xtensa/esp32s3/esp32s3-xiao/configs/combo/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-xiao/configs/combo/defconfig @@ -17,6 +17,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N8R8=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARDCTL_USBDEVCTRL=y diff --git a/boards/xtensa/esp32s3/esp32s3-xiao/configs/usbnsh/defconfig b/boards/xtensa/esp32s3/esp32s3-xiao/configs/usbnsh/defconfig index 386aed8b4f692..df085f67251ac 100644 --- a/boards/xtensa/esp32s3/esp32s3-xiao/configs/usbnsh/defconfig +++ b/boards/xtensa/esp32s3/esp32s3-xiao/configs/usbnsh/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N8R8=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARDCTL_USBDEVCTRL=y diff --git a/boards/xtensa/esp32s3/esp32s3-xiao/src/esp32s3_autoleds.c b/boards/xtensa/esp32s3/esp32s3-xiao/src/esp32s3_autoleds.c index 9d8be81879968..221d4e13b5b22 100644 --- a/boards/xtensa/esp32s3/esp32s3-xiao/src/esp32s3_autoleds.c +++ b/boards/xtensa/esp32s3/esp32s3-xiao/src/esp32s3_autoleds.c @@ -33,7 +33,7 @@ #include #include -#include "esp32s3_gpio.h" +#include "espressif/esp_gpio.h" #include "esp32s3-xiao.h" #ifdef CONFIG_ARCH_LEDS @@ -79,7 +79,7 @@ void board_autoled_initialize(void) { /* Configure RX and TX LED GPIOs for output */ - esp32s3_configgpio(GPIO_LED1, OUTPUT); + esp_configgpio(GPIO_LED1, OUTPUT); } /**************************************************************************** @@ -106,7 +106,7 @@ void board_autoled_on(int led) /* High illuminates */ - esp32s3_gpiowrite(GPIO_LED1, ledon); + esp_gpiowrite(GPIO_LED1, ledon); } /**************************************************************************** @@ -128,7 +128,7 @@ void board_autoled_off(int led) /* High illuminates */ - esp32s3_gpiowrite(GPIO_LED1, false); + esp_gpiowrite(GPIO_LED1, false); } -#endif /* CONFIG_ARCH_LEDS */ \ No newline at end of file +#endif /* CONFIG_ARCH_LEDS */ diff --git a/boards/xtensa/esp32s3/esp32s3-xiao/src/esp32s3_bringup.c b/boards/xtensa/esp32s3/esp32s3-xiao/src/esp32s3_bringup.c index 0156d9f002683..61097e61142de 100644 --- a/boards/xtensa/esp32s3/esp32s3-xiao/src/esp32s3_bringup.c +++ b/boards/xtensa/esp32s3/esp32s3-xiao/src/esp32s3_bringup.c @@ -40,6 +40,13 @@ #include #include +#include "espressif/esp_gpio.h" +#include "esp32s3_start.h" + +#ifdef CONFIG_ESPRESSIF_HR_TIMER +# include "espressif/esp_hr_timer.h" +#endif + #include "esp32s3-xiao.h" #ifdef CONFIG_USERLED @@ -68,6 +75,14 @@ int esp32s3_bringup(void) { int ret; +#ifdef CONFIG_ESPRESSIF_HR_TIMER + ret = esp_hr_timer_init(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: esp_hr_timer_init() failed: %d\n", ret); + } +#endif + #ifdef CONFIG_FS_PROCFS /* Mount the procfs file system */ diff --git a/boards/xtensa/esp32s3/esp32s3-xiao/src/esp32s3_gpio.c b/boards/xtensa/esp32s3/esp32s3-xiao/src/esp32s3_gpio.c index 982803b2180bb..cdf729648144f 100644 --- a/boards/xtensa/esp32s3/esp32s3-xiao/src/esp32s3_gpio.c +++ b/boards/xtensa/esp32s3/esp32s3-xiao/src/esp32s3_gpio.c @@ -37,7 +37,7 @@ #include #include "esp32s3-xiao.h" -#include "esp32s3_gpio.h" +#include "espressif/esp_gpio.h" #include "hardware/esp32s3_gpio_sigmap.h" #if defined(CONFIG_DEV_GPIO) && !defined(CONFIG_GPIO_LOWER_HALF) @@ -198,7 +198,7 @@ static int gpout_write(struct gpio_dev_s *dev, bool value) DEBUGASSERT(esp32s3gpio->id < BOARD_NGPIOOUT); gpioinfo("Writing %d\n", (int)value); - esp32s3_gpiowrite(g_gpiooutputs[esp32s3gpio->id], value); + esp_gpiowrite(g_gpiooutputs[esp32s3gpio->id], value); return OK; } #endif @@ -340,10 +340,9 @@ int esp32s3_gpio_init(void) /* Configure the pins that will be used as output */ - esp32s3_gpio_matrix_out(g_gpiooutputs[i], SIG_GPIO_OUT_IDX, 0, 0); - esp32s3_configgpio(g_gpiooutputs[i], OUTPUT_FUNCTION_2 | - INPUT_FUNCTION_2); - esp32s3_gpiowrite(g_gpiooutputs[i], 0); + esp_gpio_matrix_out(g_gpiooutputs[i], SIG_GPIO_OUT_IDX, 0, 0); + esp_configgpio(g_gpiooutputs[i], OUTPUT_FUNCTION_2 | INPUT_FUNCTION_2); + esp_gpiowrite(g_gpiooutputs[i], 0); pincount++; } @@ -361,7 +360,7 @@ int esp32s3_gpio_init(void) /* Configure the pins that will be used as INPUT */ - esp32s3_configgpio(g_gpioinputs[i], INPUT_FUNCTION_2); + esp_configgpio(g_gpioinputs[i], INPUT_FUNCTION_2); pincount++; } @@ -379,7 +378,8 @@ int esp32s3_gpio_init(void) /* Configure the pins that will be used as interrupt input */ - esp32s3_configgpio(g_gpiointinputs[i], INPUT_FUNCTION_2 | PULLDOWN); + esp_configgpio(g_gpiointinputs[i], + INPUT_FUNCTION_2 | PULLUP | FALLING); pincount++; } diff --git a/boards/xtensa/esp32s3/esp32s3-xiao/src/esp32s3_userleds.c b/boards/xtensa/esp32s3/esp32s3-xiao/src/esp32s3_userleds.c index 68e2be07e86f0..e3d3c4a56bb78 100644 --- a/boards/xtensa/esp32s3/esp32s3-xiao/src/esp32s3_userleds.c +++ b/boards/xtensa/esp32s3/esp32s3-xiao/src/esp32s3_userleds.c @@ -33,7 +33,7 @@ #include #include -#include "esp32s3_gpio.h" +#include "espressif/esp_gpio.h" #include "esp32s3-xiao.h" /**************************************************************************** @@ -61,7 +61,7 @@ uint32_t board_userled_initialize(void) for (i = 0; i < BOARD_NLEDS; i++) { - esp32s3_configgpio(g_ledcfg[i], OUTPUT); + esp_configgpio(g_ledcfg[i], OUTPUT); } return BOARD_NLEDS; @@ -75,7 +75,7 @@ void board_userled(int led, bool ledon) { if ((unsigned)led < BOARD_NLEDS) { - esp32s3_gpiowrite(g_ledcfg[led], ledon); + esp_gpiowrite(g_ledcfg[led], ledon); } } @@ -88,6 +88,5 @@ void board_userled_all(uint32_t ledset) bool ledon; ledon = ((ledset & BOARD_LED_L_BIT) != 0); - esp32s3_gpiowrite(ledset, ledon); + esp_gpiowrite(ledset, ledon); } - diff --git a/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/configs/camera/defconfig b/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/configs/camera/defconfig index 93c58555b9f4b..8f4f32fbda5d2 100644 --- a/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/configs/camera/defconfig +++ b/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/configs/camera/defconfig @@ -24,6 +24,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N16R8=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/configs/fastboot/defconfig b/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/configs/fastboot/defconfig index ba4a2e11630fd..db3d3e2805506 100644 --- a/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/configs/fastboot/defconfig +++ b/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/configs/fastboot/defconfig @@ -17,6 +17,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N16R8=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BCH=y @@ -30,7 +33,6 @@ CONFIG_DRIVERS_IEEE80211=y CONFIG_DRIVERS_WIRELESS=y CONFIG_ESP32S3_OTG=y CONFIG_ESP32S3_OTG_ENDPOINT_NUM=2 -CONFIG_ESP32S3_RT_TIMER_TASK_STACK_SIZE=4096 CONFIG_ESP32S3_SPIFLASH=y CONFIG_ESP32S3_SPIFLASH_SPIFFS=y CONFIG_ESP32S3_UART0=y @@ -76,6 +78,8 @@ CONFIG_PTHREAD_MUTEX_TYPES=y CONFIG_RAM_SIZE=114688 CONFIG_RAM_START=0x20000000 CONFIG_RR_INTERVAL=200 +CONFIG_RTC=y +CONFIG_RTC_DRIVER=y CONFIG_SCHED_CHILD_STATUS=y CONFIG_SCHED_HAVE_PARENT=y CONFIG_SCHED_LPWORK=y diff --git a/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/configs/fastboot_tcp/defconfig b/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/configs/fastboot_tcp/defconfig index 10c2122fb6ce5..601e4c7d4ceec 100644 --- a/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/configs/fastboot_tcp/defconfig +++ b/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/configs/fastboot_tcp/defconfig @@ -18,6 +18,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N16R8=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 @@ -25,7 +28,6 @@ CONFIG_BUILTIN=y CONFIG_DEFAULT_TASK_STACKSIZE=4096 CONFIG_DRIVERS_IEEE80211=y CONFIG_DRIVERS_WIRELESS=y -CONFIG_ESP32S3_RT_TIMER_TASK_STACK_SIZE=4096 CONFIG_ESP32S3_SPIFLASH=y CONFIG_ESP32S3_SPIFLASH_SPIFFS=y CONFIG_ESP32S3_UART0=y @@ -67,6 +69,8 @@ CONFIG_PTHREAD_MUTEX_TYPES=y CONFIG_RAM_SIZE=114688 CONFIG_RAM_START=0x20000000 CONFIG_RR_INTERVAL=200 +CONFIG_RTC=y +CONFIG_RTC_DRIVER=y CONFIG_SCHED_CHILD_STATUS=y CONFIG_SCHED_HAVE_PARENT=y CONFIG_SCHED_LPWORK=y diff --git a/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/configs/gc0308/defconfig b/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/configs/gc0308/defconfig index 0917384e8bc10..0dc2204353f14 100644 --- a/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/configs/gc0308/defconfig +++ b/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/configs/gc0308/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N16R8=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/configs/gpio/defconfig b/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/configs/gpio/defconfig index 6fa64b7fc6841..2d883c63f6704 100644 --- a/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/configs/gpio/defconfig +++ b/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/configs/gpio/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N16R8=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/configs/lcd/defconfig b/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/configs/lcd/defconfig index dbf50c4259415..edb55c91d8347 100644 --- a/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/configs/lcd/defconfig +++ b/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/configs/lcd/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N16R8=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/configs/lvgl/defconfig b/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/configs/lvgl/defconfig index 8119354fa5eaa..eca401825e720 100644 --- a/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/configs/lvgl/defconfig +++ b/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/configs/lvgl/defconfig @@ -19,6 +19,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N16R8=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/configs/nsh/defconfig b/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/configs/nsh/defconfig index 9f7a61d92759f..0b46e8cf7e0ed 100644 --- a/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/configs/nsh/defconfig +++ b/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/configs/nsh/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N16R8=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/configs/pca9557/defconfig b/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/configs/pca9557/defconfig index 130cc6df2d465..cc5dbe9882a9e 100644 --- a/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/configs/pca9557/defconfig +++ b/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/configs/pca9557/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N16R8=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/configs/psram/defconfig b/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/configs/psram/defconfig index 5e431d4026437..8710dd56af82c 100644 --- a/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/configs/psram/defconfig +++ b/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/configs/psram/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N16R8=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/configs/pwm/defconfig b/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/configs/pwm/defconfig index 7f35a8fa26b32..2423fc888b513 100644 --- a/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/configs/pwm/defconfig +++ b/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/configs/pwm/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N16R8=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/configs/qmi8658/defconfig b/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/configs/qmi8658/defconfig index 80f2e798d7833..54334c4872fb5 100644 --- a/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/configs/qmi8658/defconfig +++ b/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/configs/qmi8658/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N16R8=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/configs/sdmmc/defconfig b/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/configs/sdmmc/defconfig index 1c605f5fbe3c1..909244dd8e0b8 100644 --- a/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/configs/sdmmc/defconfig +++ b/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/configs/sdmmc/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N16R8=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/configs/usb_device/defconfig b/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/configs/usb_device/defconfig index 0b0696ccf2caf..b69fb541a6d3a 100644 --- a/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/configs/usb_device/defconfig +++ b/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/configs/usb_device/defconfig @@ -16,6 +16,9 @@ CONFIG_ARCH_CHIP="esp32s3" CONFIG_ARCH_CHIP_ESP32S3=y CONFIG_ARCH_CHIP_ESP32S3WROOM1N16R8=y CONFIG_ARCH_INTERRUPTSTACK=2048 +CONFIG_ARCH_IRQ_TO_NDX=y +CONFIG_ARCH_MINIMAL_VECTORTABLE_DYNAMIC=y +CONFIG_ARCH_NUSER_INTERRUPTS=2 CONFIG_ARCH_STACKDUMP=y CONFIG_ARCH_XTENSA=y CONFIG_BOARD_LOOPSPERMSEC=16717 diff --git a/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/src/esp32s3_board_lcd.c b/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/src/esp32s3_board_lcd.c index 1c29788c68844..6c26777a72710 100644 --- a/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/src/esp32s3_board_lcd.c +++ b/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/src/esp32s3_board_lcd.c @@ -44,7 +44,7 @@ #include -#include "esp32s3_gpio.h" +#include "espressif/esp_gpio.h" #include "esp32s3_spi.h" #include "hardware/esp32s3_gpio_sigmap.h" diff --git a/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/src/esp32s3_board_spi.c b/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/src/esp32s3_board_spi.c index 3ea1c837e68e9..73c75984bbe13 100644 --- a/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/src/esp32s3_board_spi.c +++ b/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/src/esp32s3_board_spi.c @@ -34,7 +34,7 @@ #include #include -#include "esp32s3_gpio.h" +#include "espressif/esp_gpio.h" #include "esp32s3-szpi.h" /**************************************************************************** @@ -74,7 +74,7 @@ int esp32s3_spi2_cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) * data bits are data or a command. */ - esp32s3_gpiowrite(GPIO_LCD_DC, !cmd); + esp_gpiowrite(GPIO_LCD_DC, !cmd); return OK; } @@ -140,7 +140,7 @@ int esp32s3_spi3_cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd) * data bits are data or a command. */ - esp32s3_gpiowrite(CONFIG_ESP32S3_SPI3_MISOPIN, !cmd); + esp_gpiowrite(CONFIG_ESP32S3_SPI3_MISOPIN, !cmd); return OK; } diff --git a/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/src/esp32s3_bringup.c b/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/src/esp32s3_bringup.c index dfac808cee968..26bbb4641b70d 100644 --- a/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/src/esp32s3_bringup.c +++ b/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/src/esp32s3_bringup.c @@ -41,6 +41,9 @@ #include #include +#include "espressif/esp_gpio.h" +#include "esp32s3_start.h" + #ifdef CONFIG_ESP32S3_TIMER # include "esp32s3_board_tim.h" #endif @@ -57,10 +60,6 @@ # include "esp32s3_wifi_adapter.h" #endif -#ifdef CONFIG_ESP32S3_RT_TIMER -# include "esp32s3_rt_timer.h" -#endif - #ifdef CONFIG_ESP32S3_I2C # include "esp32s3_i2c.h" #endif @@ -74,7 +73,11 @@ #endif #ifdef CONFIG_RTC_DRIVER -# include "esp32s3_rtc_lowerhalf.h" +# include "espressif/esp_rtc.h" +#endif + +#ifdef CONFIG_ESPRESSIF_HR_TIMER +# include "espressif/esp_hr_timer.h" #endif #ifdef CONFIG_VIDEO_FB @@ -161,6 +164,15 @@ int esp32s3_bringup(void) { int ret; + +#ifdef CONFIG_ESPRESSIF_HR_TIMER + ret = esp_hr_timer_init(); + if (ret < 0) + { + syslog(LOG_ERR, "ERROR: esp_hr_timer_init() failed: %d\n", ret); + } +#endif + #if defined(CONFIG_ESPRESSIF_I2S0) || defined(CONFIG_ESPRESSIF_I2S1) bool i2s_enable_tx; bool i2s_enable_rx; @@ -265,14 +277,6 @@ int esp32s3_bringup(void) } #endif -#ifdef CONFIG_ESP32S3_RT_TIMER - ret = esp32s3_rt_timer_init(); - if (ret < 0) - { - syslog(LOG_ERR, "Failed to initialize RT timer: %d\n", ret); - } -#endif - #ifdef CONFIG_ESPRESSIF_TEMP struct esp_temp_sensor_config_t cfg = TEMPERATURE_SENSOR_CONFIG(10, 50); ret = esp_temperature_sensor_initialize(cfg); @@ -286,7 +290,7 @@ int esp32s3_bringup(void) #ifdef CONFIG_RTC_DRIVER /* Instantiate the ESP32-S3 RTC driver */ - ret = esp32s3_rtc_driverinit(); + ret = esp_rtc_driverinit(); if (ret < 0) { syslog(LOG_ERR, diff --git a/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/src/esp32s3_gpio.c b/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/src/esp32s3_gpio.c index 0a346d812e890..551734b985e16 100644 --- a/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/src/esp32s3_gpio.c +++ b/boards/xtensa/esp32s3/lckfb-szpi-esp32s3/src/esp32s3_gpio.c @@ -37,7 +37,7 @@ #include #include "esp32s3-szpi.h" -#include "esp32s3_gpio.h" +#include "espressif/esp_gpio.h" #include "hardware/esp32s3_gpio_sigmap.h" #if defined(CONFIG_DEV_GPIO) @@ -92,7 +92,7 @@ static int gpout_write(struct gpio_dev_s *dev, bool value); static int gpin_read(struct gpio_dev_s *dev, bool *value); #endif -#if defined(CONFIG_ESP32S3_GPIO_IRQ) && BOARD_NGPIOINT > 0 +#if defined(CONFIG_ESPRESSIF_GPIO_IRQ) && BOARD_NGPIOINT > 0 static int gpint_read(struct gpio_dev_s *dev, bool *value); static int gpint_attach(struct gpio_dev_s *dev, pin_interrupt_t callback); @@ -141,7 +141,7 @@ static const uint32_t g_gpioinputs[BOARD_NGPIOIN] = static struct esp32s3gpio_dev_s g_gpin[BOARD_NGPIOIN]; #endif -#if defined(CONFIG_ESP32S3_GPIO_IRQ) && BOARD_NGPIOINT > 0 +#if defined(CONFIG_ESPRESSIF_GPIO_IRQ) && BOARD_NGPIOINT > 0 static const struct gpio_operations_s gpint_ops = { .go_read = gpint_read, @@ -177,7 +177,7 @@ static int gpout_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(esp32s3gpio->id < BOARD_NGPIOOUT); gpioinfo("Reading...\n"); - *value = esp32s3_gpioread(g_gpiooutputs[esp32s3gpio->id]); + *value = esp_gpioread(g_gpiooutputs[esp32s3gpio->id]); return OK; } @@ -193,7 +193,7 @@ static int gpout_write(struct gpio_dev_s *dev, bool value) DEBUGASSERT(esp32s3gpio->id < BOARD_NGPIOOUT); gpioinfo("Writing %d\n", (int)value); - esp32s3_gpiowrite(g_gpiooutputs[esp32s3gpio->id], value); + esp_gpiowrite(g_gpiooutputs[esp32s3gpio->id], value); return OK; } #endif @@ -211,7 +211,7 @@ static int gpin_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(esp32s3gpio->id < BOARD_NGPIOIN); gpioinfo("Reading... pin %" PRIu32 "\n", g_gpioinputs[esp32s3gpio->id]); - *value = esp32s3_gpioread(g_gpioinputs[esp32s3gpio->id]); + *value = esp_gpioread(g_gpioinputs[esp32s3gpio->id]); return OK; } #endif @@ -220,7 +220,7 @@ static int gpin_read(struct gpio_dev_s *dev, bool *value) * Name: esp32s3gpio_interrupt ****************************************************************************/ -#if defined(CONFIG_ESP32S3_GPIO_IRQ) && BOARD_NGPIOINT > 0 +#if defined(CONFIG_ESPRESSIF_GPIO_IRQ) && BOARD_NGPIOINT > 0 static int esp32s3gpio_interrupt(int irq, void *context, void *arg) { struct esp32s3gpint_dev_s *esp32s3gpint = (struct esp32s3gpint_dev_s *)arg; @@ -245,7 +245,7 @@ static int gpint_read(struct gpio_dev_s *dev, bool *value) DEBUGASSERT(esp32s3gpint->esp32s3gpio.id < BOARD_NGPIOINT); gpioinfo("Reading int pin...\n"); - *value = esp32s3_gpioread(g_gpiointinputs[esp32s3gpint->esp32s3gpio.id]); + *value = esp_gpioread(g_gpiointinputs[esp32s3gpint->esp32s3gpio.id]); return OK; } @@ -258,23 +258,27 @@ static int gpint_attach(struct gpio_dev_s *dev, { struct esp32s3gpint_dev_s *esp32s3gpint = (struct esp32s3gpint_dev_s *)dev; - int irq = ESP32S3_PIN2IRQ(g_gpiointinputs[esp32s3gpint->esp32s3gpio.id]); int ret; gpioinfo("Attaching the callback\n"); /* Make sure the interrupt is disabled */ - esp32s3_gpioirqdisable(irq); - ret = irq_attach(irq, - esp32s3gpio_interrupt, - &g_gpint[esp32s3gpint->esp32s3gpio.id]); + esp_gpioirqdisable(g_gpiointinputs[esp32s3gpint->esp32s3gpio.id]); + + ret = esp_gpio_irq(g_gpiointinputs[esp32s3gpint->esp32s3gpio.id], + esp32s3gpio_interrupt, + &g_gpint[esp32s3gpint->esp32s3gpio.id]); if (ret < 0) { syslog(LOG_ERR, "ERROR: gpint_attach() failed: %d\n", ret); return ret; } + /* Make sure the interrupt is disabled */ + + esp_gpioirqdisable(g_gpiointinputs[esp32s3gpint->esp32s3gpio.id]); + gpioinfo("Attach %p\n", callback); esp32s3gpint->callback = callback; return OK; @@ -287,7 +291,6 @@ static int gpint_attach(struct gpio_dev_s *dev, static int gpint_enable(struct gpio_dev_s *dev, bool enable) { struct esp32s3gpint_dev_s *esp32s3gpint = (struct esp32s3gpint_dev_s *)dev; - int irq = ESP32S3_PIN2IRQ(g_gpiointinputs[esp32s3gpint->esp32s3gpio.id]); if (enable) { @@ -297,13 +300,13 @@ static int gpint_enable(struct gpio_dev_s *dev, bool enable) /* Configure the interrupt for rising edge */ - esp32s3_gpioirqenable(irq, RISING); + esp_gpioirqenable(g_gpiointinputs[esp32s3gpint->esp32s3gpio.id]); } } else { gpioinfo("Disable the interrupt\n"); - esp32s3_gpioirqdisable(irq); + esp_gpioirqdisable(g_gpiointinputs[esp32s3gpint->esp32s3gpio.id]); } return OK; @@ -334,10 +337,9 @@ int esp32s3_gpio_init(void) /* Configure the pins that will be used as output */ - esp32s3_gpio_matrix_out(g_gpiooutputs[i], SIG_GPIO_OUT_IDX, 0, 0); - esp32s3_configgpio(g_gpiooutputs[i], OUTPUT_FUNCTION_2 | - INPUT_FUNCTION_2); - esp32s3_gpiowrite(g_gpiooutputs[i], 0); + esp_gpio_matrix_out(g_gpiooutputs[i], SIG_GPIO_OUT_IDX, 0, 0); + esp_configgpio(g_gpiooutputs[i], OUTPUT_FUNCTION_2 | INPUT_FUNCTION_2); + esp_gpiowrite(g_gpiooutputs[i], 0); } #endif @@ -353,11 +355,11 @@ int esp32s3_gpio_init(void) /* Configure the pins that will be used as INPUT */ - esp32s3_configgpio(g_gpioinputs[i], INPUT_FUNCTION_2); + esp_configgpio(g_gpioinputs[i], INPUT_FUNCTION_2 | PULLDOWN); } #endif -#if defined(CONFIG_ESP32S3_GPIO_IRQ) && BOARD_NGPIOINT > 0 +#if defined(CONFIG_ESPRESSIF_GPIO_IRQ) && BOARD_NGPIOINT > 0 for (i = 0; i < BOARD_NGPIOINT; i++) { /* Setup and register the GPIO pin */ @@ -369,7 +371,8 @@ int esp32s3_gpio_init(void) /* Configure the pins that will be used as interrupt input */ - esp32s3_configgpio(g_gpiointinputs[i], INPUT_FUNCTION_2 | PULLDOWN); + esp_configgpio(g_gpiointinputs[i], + INPUT_FUNCTION_2 | PULLDOWN | FALLING); } #endif