From 124b820b3e62b6772b15f81fddd78ca8354819f2 Mon Sep 17 00:00:00 2001 From: p-szafonimateusz Date: Mon, 3 Nov 2025 14:43:07 +0100 Subject: [PATCH] arch/intel64: add CPU affinity support for irq add CPU affinity support for interrupts (up_affinity_irq) Signed-off-by: p-szafonimateusz --- arch/x86_64/src/intel64/intel64_irq.c | 38 +++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/x86_64/src/intel64/intel64_irq.c b/arch/x86_64/src/intel64/intel64_irq.c index 4765290dc194d..885ae0411134c 100644 --- a/arch/x86_64/src/intel64/intel64_irq.c +++ b/arch/x86_64/src/intel64/intel64_irq.c @@ -845,3 +845,41 @@ int up_set_irq_type(int irq, int mode) return 0; } + +/**************************************************************************** + * Name: up_affinity_irq + * + * Description: + * Set an IRQ affinity by software. + * + ****************************************************************************/ + +void up_affinity_irq(int irq, cpu_set_t cpuset) +{ + irqstate_t flags = spin_lock_irqsave(&g_irq_spinlock); + uint32_t data; + int cpu; + + if (irq >= IRQ_MSI_START && irq <= g_msi_now) + { + /* Affinit for MSI is not supported now. + * For x86 this must be done on PCI level as MSI/MSI-X interrupts + * bypass IOAPIC. + */ + + spin_unlock_irqrestore(&g_irq_spinlock, flags); + return; + } + + for (cpu = 0; cpu < CONFIG_NCPUS; cpu++) + { + if (CPU_ISSET(cpu, &cpuset)) + { + data = x86_64_cpu_to_loapic(cpu) << 24; + up_ioapic_write(IOAPIC_REG_TABLE + (irq - IRQ0) * 2 + 1, data); + break; + } + } + + spin_unlock_irqrestore(&g_irq_spinlock, flags); +}