openware-notes.txt

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todo:
- refactor build files
- common top level build file
- make sure all output files end up in project Build directory
- refactor device.h files

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STM32F756ZG
RAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 320K
FLASH (rx)     : ORIGIN = 0x8000000, LENGTH = 1024K

STM32F439ZG
RAM (xrw)      : ORIGIN = 0x20000000, LENGTH = 192K
CCMRAM (rw)    : ORIGIN = 0x10000000, LENGTH = 64K
FLASH (rx)     : ORIGIN = 0x8000000, LENGTH = 1024K

STM32F407ZGT6
RAM (xrw)	: ORIGIN = 0x20000000, LENGTH = 112k
CCMRAM (xrw)	: ORIGIN = 0x10000000, LENGTH = 64k
NVRAM (xrw)	: ORIGIN = 0x40024000, LENGTH = 4K
FLASH (rx)	: ORIGIN = 0x08000000, LENGTH = 1M

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WM8731: I2S_MCLK not needed for Codec Master mode

OpenWare:
main.c:
  RCC_OscInitStruct.PLL.PLLM = 4;
  RCC_OscInitStruct.PLL.PLLN = 168;
  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
  RCC_OscInitStruct.PLL.PLLQ = 7;
  PeriphClkInitStruct.PLLI2S.PLLI2SN = 50;
  PeriphClkInitStruct.PLLI2S.PLLI2SR = 2;

    __HAL_RCC_SPI2_CLK_ENABLE();
    HAL_NVIC_SetPriority(SPI2_IRQn, 5, 0);
    HAL_NVIC_EnableIRQ(SPI2_IRQn);

OwlWare:
#define PLL_M      8
#define PLL_N      336
#define PLL_P      2
#define PLL_Q      7
#define PLLI2S_N   258
#define PLLI2S_R   3

  *        I2S input clock(Hz)                    | 86000000
  *        To achieve the following I2S config:   |
  *         - Master clock output (MCKO): ON      |
  *         - Frame wide                : 16bit   |
  *         - Audio sampling freq (KHz) : 48      |
  *         - Error %                   : 0.0186  |
  *         - Prescaler Odd factor (ODD): 1       |
  *         - Linear prescaler (DIV)    : 3       |

  RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2C2, ENABLE);

  /* Configures the I2S clock source (I2SCLK). */
  /* This function must be called before enabling the I2S APB clock. */
  RCC_I2SCLKConfig(RCC_I2S2CLKSource_PLLI2S);
  RCC_PLLI2SCmd(ENABLE);
  /* Enable the CODEC_I2S peripheral clock */
  RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE);

blocking TransmitReceive seems to work on RX (strange values)

HAL_I2S_Receive_DMA: no callbacks on RX

Transmit: time-outs
TransmitReceive_IT: underrun in TX

DACLRC / ADCLRC / LRCK 48khz
BCLK / SCLK 3.08MHz
ADCDAT / SDI data
DACDAT / SDO flat

Problems fixed by removing __HAL_I2S_ENABLE(&hi2s2) in Codec::reset()

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OwlPedal SRAM memory

OwlWare:
  p.FSMC_AddressSetupTime = 3;
  p.FSMC_AddressHoldTime = 0;
  p.FSMC_DataSetupTime = 6;
  p.FSMC_BusTurnAroundDuration = 1;
  p.FSMC_CLKDivision = 0;
  p.FSMC_DataLatency = 0;
  p.FSMC_AccessMode = FSMC_AccessMode_A;

OpenWare:
  Timing.AddressSetupTime = 3;
  Timing.AddressHoldTime = 1; // > 0, <= 15
  Timing.DataSetupTime = 6;
  Timing.BusTurnAroundDuration = 1;
  Timing.CLKDivision = 2; // > 1, <= 16
  Timing.DataLatency = 2; // > 1, <= 17
  Timing.AccessMode = FSMC_ACCESS_MODE_A;

  /* Set FSMC_NORSRAM device timing parameters */  
  tmpr |= (uint32_t)(Timing->AddressSetupTime                  |\
                    ((Timing->AddressHoldTime) << 4U)          |\
                    ((Timing->DataSetupTime) << 8U)            |\
                    ((Timing->BusTurnAroundDuration) << 16U)   |\
                    (((Timing->CLKDivision)-1U) << 20U)        |\
                    (((Timing->DataLatency)-2U) << 24U)        |\
                    (Timing->AccessMode));


__HAL_RCC_FSMC_CLK_ENABLE():
                                      __IO uint32_t tmpreg = 0x00U; \
                                      SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
                                      /* Delay after an RCC peripheral clock enabling */ \
                                      tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
                                      UNUSED(tmpreg); \

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todo:
/ pass in sample format in PV: 16/24bit, 24bit
  / change audio_bitdepth to audio_format
/ refactor OwlProgram/PatchProgram/SampleBuffer to allow different conversions depending on format
- pass in stack as available heap memory (for CCM / non-F7 platforms)
- check OWL2 sample format and conversion
- owl1 sram
- replace float div with mul in SampleBuffer conversions - check accuracy

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OWL2 80kHz 500mV on AINA

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Bootloader STM32F42x/3x
Bootloader activation Pattern 5:
Boot0(pin) = 1, Boot1(pin) = 0 and BFB2(bit) = 0
Boot0(pin) = 1, Boot1(pin) = 0 and BFB2 (bit) = 1
Boot0(pin) = 0, BFB2(bit) = 1 and both banks don’t contain valid code

BFB2: boot from bank 2

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note:
for all projects, check main.c and stm32xyz_it.c for common blocks, e.g.
SRAM / SDRAM initialisation
I2S / SAI initialisation and interrupts
uart / bus IDLE interrupts
USB stuff

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Alchemist / Wizard Reset loop
presets:
Fascination I to V
Granular Delay
Granular Delay
Granular Delay
FmDronePoly
DroneBox

Granular Delay and DroneBox both cause reset cycle when stored in patch slot 1

flash erase not working? needs unlocking?

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# reset
amidi -p hw:2 -S f07d527df7

# reset to bootloader
amidi -p hw:2 -S f07d527ef7

# erase flash storage sectors
amidi -p "hw:1,0,0" -S f07d52140000000007f7f07d52140000000008f7f07d52140000000009f7f07d52140000000010f7

# flash Wizard firmware
amidi -p hw:2 -s Wizard.syx

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#define VECT_TAB_OFFSET  0x00008000

cd MidiBoot
make PLATFORM=Alchemist CONFIG=Release clean all

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FirmwareSender -in Build/Alchemist.bin -flash `crc32 Build/Alchemist.bin` -save Alchemist.syx
FirmwareSender -in Build/Wizard.bin -flash `crc32 Build/Wizard.bin` -save Wizard.syx

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USB AUDIO + MIDI device descriptor

https://eleccelerator.com/usbdescreqparser/

4ch BioSignals w/o MIDI:

09026400020100803209040000000101000009240100011e0001010c2402010102000700000000092403020101000100090401000001020000090401010101020000072401020001000b24020107042001401f0009058101e00001000007250100000000

Focusrite Scarlett
0902600106010980fa080b00030100200009040000000101200309240100020865000008240a290307000a08240b2801290308112402020101002804000000000e0000060c240314010300022800000011240201010200280200000000120000001224060b01000000000000000000000000000c2403160101000b280000070904010000010220040904010102010220041024010200010100000004000000000e0624020104180705010d9001010825010000020800070581110400040904020000010220050904020101010220051024011600010100000002000000001206240201041807058225c8000108250100000208000904030000010100000924010001090001010904040002010300000724010001410006240201010006240202020c09240301030102010009240302040101010b090502020002000000052501010109058302000200000005250101030904050001ff01100d07058403400008

WireShark
[Expert Info (Error/Malformed): Malformed Packet (Exception occurred)]

https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/how-to-retrieve-information-about-a-usb-device
MS USB hardware verifier

https://www.usb.org/usb2tools
http://www.testusb.com/Ch8ck.html


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enable semihosting:
* remove C_SRC += libnosys_gnu.c in sources.mk
* add `end` symbol to linker
* add in main.c:
int main(void)
 {
   /* USER CODE BEGIN 1 */
   initialise_monitor_handles(); // remove when not semi-hosting

Makefile owl2.mk:
-CPPFLAGS += --specs=nano.specs
+LDLIBS += -lc -lm
+LDLIBS += -lrdimon
+# CPPFLAGS += -specs=rdimon.specs
+LDFLAGS += --specs=nano.specs
-CPPFLAGS += -nostdlib -nostartfiles -fno-builtin -ffreestanding

* use openocd
* enable semi hosting in gdb:
debug: $(ELF)
       @$(GDB) -ex "target extended-remote localhost:3333" -ex "monitor reset hard" -ex "monitor arm semihosting enable" -ex "load" $(ELF)

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To catch reset cycles due to buggy default patches
#define USE_BKPSRAM

in Cube, enable Timers/RTC clock source 

define armex
  printf "EXEC_RETURN (LR):\n",
  info registers $lr
    if ($lr & (0x4 == 0x4))
      printf "Uses MSP 0x%x return.\n", $msp
      set $armex_base = (uint32_t)$msp
    else
      printf "Uses PSP 0x%x return.\n", $psp
      set $armex_base = (uint32_t)$psp
    end

    printf "xPSR            0x%x\n", *($armex_base+28)
    printf "ReturnAddress   0x%x\n", *($armex_base+24)
    printf "LR (R14)        0x%x\n", *($armex_base+20)
    printf "R12             0x%x\n", *($armex_base+16)
    printf "R3              0x%x\n", *($armex_base+12)
    printf "R2              0x%x\n", *($armex_base+8)
    printf "R1              0x%x\n", *($armex_base+4)
    printf "R0              0x%x\n", *($armex_base)
    printf "Return instruction:\n"
    x/i *($armex_base+24)
    printf "LR instruction:\n"
    x/i *($armex_base+20)
end

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Wizard pin compatible devices:
STM32F777ZITx
STM32F767ZITx
STM32F767ZGTx
STM32F756ZGTx
STM32F746ZGTx
STM32F765ZGTx
...

Noctua pin compatible devices:
STM32F427VITx 256k SRAM, 2Mb FLASH, $6.70 @1k
STM32F446VETx 128k SRAM, 512k FLASH, $3.98 @1k

PE12 / pin 43 : 

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Compiling with C++14 support with -std=gnu++14 can cause `operator delete(void*, size_t) undefined` errors.

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