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ACE1802FORTH.asm
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7882 lines (7387 loc) · 369 KB
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;
; r2.5
;
;===================================================================
;
; A CCCC EEEEE
; A A C E
; AAAAA C EEEE
; A A C E
; A A CCCC EEEEE
;
; FFFF I GGG FFFF OO RRRR TTTTT H H
; F I G F O O R R T H H
; FFF I G GGG XX FFF O O RRR T HHHHH
; F I G G F O O R R T H H
; F I GGG F OO R R T H H
;
; 1 8888 00 2222
; 1 8 8 0 0 2
; 1 8888 0 0 22
; 1 8 8 0 0 2
; 1 8888 00 2222
;
;=====================================================================
; FIG-FORTH for the ASSOCIATION OF COMPUTER CHIP EXPERIMENTERS (ACE)
;=====================================================================
;
; THIS PUBLICATION WAS ORIGINALLY MADE AVAILABLE BY THE
; FORTH INTREST GROUP
; P. O. BOX 1105
; SAN CARLOS, CA 94070
; ALL PUBLICATIONS OF THE FORTH INTEREST GROUP ARE PUBLIC DOMAIN.
; THEY MAY BE FURTHER DISTRIBUTED BY INCLUSION OF THIS CREDIT NOTICE.
;
; ORIGINAL IMPLEMENTATION (6502) BY:
; WILLIAM F RAGSDALE
; FORTH INTEREST GROUP
;
; IMPLEMENTAION FOR 1802 BY:
; GARY R. BRADSHAW;
; MODIFIED BY:
; GORDEN FLEMMING
; JIM MCDANIEL
;
; EDITOR :
; WILLIAM F RAGSDALE
; FORTH INTEREST GROUP
;
; ASSEMBLER :
; KEN MANTEI
; CHEMISTRY DEPARTMENT
; CAL STATE COLLEGE
; SAN BERNARDINO, A 92407
;
; Q & EF SOFTWARE UART SERIAL I/O TAKEN FROM CODE BY :
; DAVID S MADOLE [ david@madole.net ]
;
; OTHER MODIFICATIONS BY:
; ANTHONY HILL [ hill.anthony@outlook.com ]
; ASSOCIATION OF COMPUTER CHIP EXPERIMENTERS (ACE)
; - including ACE hardware, ROMable code,
; interrupt driven 1854 and RTC,
; mutlitasking, hex file download, serial screen load,
; & support for Lee Hart's Membership Card Version
;
; OTHER ACKNOWLEDGEMENTS:
; This figFORTH integration has evolved 40 years.
; Other contributions may have been used but accidentally not acknowledged.
; Please contact Anthony Hill to be gratefully added to these acknowledgements
;
;====================================================================
;
; INSTALLATION & BUILD NOTES :
;
; 1) Build using the A18 assembler for the 1802 ( https://www.retrotechnology.com/memship/a18.html )
; 2) Example configuratio build otions for
; - a generice 1802 ELF ( uart_type and timer_type = software )
; - Lee Hart's more recent Membership Card with 7 segment LED displays ( uart_type = software and timer_type = hardware )
; - CDP1854 UART with interrrupt support ( uart_type and timer_type = software or hardware )
; 3) Modify for other 1802 hardware by changing the code at CSEND, getKey, and qTERM
; 4) Full system with all options will fit into a 16K EPROM. Use the existing memory lay options or edit to suit.
; 5) Build option to include a precompiled figFORTH line editor
; 6) Build option to include a precompiled 1802 inline assembler
; 7) Build option to include other example code to control external hardwas ( 8255, 6818, etc)
; 8) Build option to include some example Forth code screens
;
; This file and its documentation are available at https://github.com/anthonylhill/ACE1802FORTH
;
;====================================================================
;
; 1802 Register Allocations For This Version
; R0 <<unused other than cold start PC >>
; R1 ISR PC for task timers and / or UART (for Memebership Card, R1 = 0 disables interrupts to protect software UART)
; R2 Return Stack Pointer
; Grows down left pointing to free location
; R3 PC For I/O And Primitives
; R4 Multitasker
; R5 Multitasker stack for storing previous task state ??
; R6 <<software UART serial code>>
; R7,R8 Temporary Accumulators
; R9 Computation Stack Pointer S0
; Grows upward left pointing at high byte
; RA Forth "I" Register Ip
; RB Forth "W" Register Wp
; RC PC For Inner Interpreter
; RD User Pointer Up
; RE <<software UART serial code>>
; RF <<unused during cold or warm starts>>
;
;
;========================== Useful Constants ===========================
R0 EQU 0 ;
R1 EQU 1 ;
R2 EQU 2 ;
R3 EQU 3 ;
R4 EQU 4 ;
R5 EQU 5 ;
R6 EQU 6 ;
R7 EQU 7 ;
R8 EQU 8 ;
R9 EQU 9 ;
RA EQU 10 ;
RB EQU 11 ;
RC EQU 12 ;
RD EQU 13 ;
RE EQU 14 ;
RF EQU 15 ;
no EQU 0 ;
yes EQU 1 ;
selectable EQU 2 ;
XON EQU $11 ;
XOFF EQU $13 ;
software EQU 1 ;
hardware EQU 2 ;
ram_elf EQU 1 ; Elf with 32K RAM at $0000
rom_ram_elf EQU 2 ; Elf or Membership Card with ROM at $0000 and RAM at $8000
ram_rom_elf EQU 3 ; ELF or Membership Card with ROM at $8000 and RAM at $0000
ace_cpu_card EQU 4 ; ACE CPU card with 16K ROM at $0000 and 48K RAM
custom EQU 5 ; custom memory model
;============= Build Options : *** Edit the Configurations Options Here for Your Needs *** ==============================
memory_model equ ram_elf ; ram_elf / rom_ram_elf / ram_rom_elf / ace_cpu_card / custom
uart_type equ software ; UART implemented in software or hardware ?
timer_type equ hardware ; tic timer implemented in software or hardware ?
extra_hardware equ no ; no / yes = include code for extra hardware support ACE CPU systems
example_screens equ yes ; no / yes = include example Forth source screens at screen XSCREEN
autoload_screen equ selectable ; no / yes / selectable = enable autoload of example screen on startup (selectable assumes an I/O switch)
clock_mhz equ 4 ; CPU clock speed for bit bash uart timing ( 1.8 Mhz or 4 Mhz )
uart_config equ $3E ; CDP1854 control register : Interrupts enabled, 8 data bits , 2 stop bits , even parity , parity enabled
;
editor equ yes ; yes = include line editor code
assembler equ yes ; yes = include assembler code
stackptr_show equ yes ; yes = show top of stack address after the OK prompt
zero_ram equ no ; yes = zero RAM at startup
lbr_at_zero equ no ; yes = insert a LBR START at $0000 (optional for memory maps where code does not start at $0000)
prescaler_value equ $80 ; prescale value for software based task tic timers
;========================== Memory Maps =============================
if memory_model = ram_elf ; simple Elf with 32K RAM at $0000
START_OF_ROM EQU $0000 ; code start
START_OF_RAM EQU $4000 ; start of RAM area - must be on a page bountry
END_OF_RAM EQU $6000 ; end of RAM block - first byte after
FIRSTB EQU END_OF_RAM-$0400 ; start of RAM disk : disk screen #0 is unusable so offset FIRSTB back 1K
LIMITB EQU $7FFF ; end of RAM disk area (CONSTANT variable not currently used)
endi ;
if memory_model = rom_ram_elf ; Elf or Membership Card with ROM at $0000 and RAM at $8000
START_OF_ROM EQU $0000 ; code start
START_OF_RAM EQU $8000 ; start of RAM area - must be on a page bountry
END_OF_RAM EQU $A000 ; end of RAM block - first byte after
FIRSTB EQU END_OF_RAM-$0400 ; start of RAM disk : disk screen #0 is unusable so offset FIRSTB back 1K
LIMITB EQU $FFFF ; end of RAM disk area (CONSTANT variable not currently used)
endi
if memory_model = ram_rom_elf ; ELF or Membership Card with ROM at $8000 and RAM at $0000
START_OF_ROM EQU $8000 ; code start
START_OF_RAM EQU $4000 ; start of RAM area - must be on a page boundry
END_OF_RAM EQU $6000 ; end of RAM block - first byte after
FIRSTB EQU END_OF_RAM - $0400 ; start of RAM disk : disk screen #0 is unusable so offset FIRSTB back 1K
LIMITB EQU $7FFF ; end of RAM disk area (CONSTANT variable not currently used)
endi
if memory_model = ace_cpu_card ; ACE CPU card with 16K ROM at $0000 and 48K RAM
START_OF_ROM EQU $0000 ; code start
START_OF_RAM EQU $4000 ; start of RAM area - must be on a page bountry
END_OF_RAM EQU $FF00 ; end of RAM block - first byte after
FIRSTB EQU END_OF_RAM-$0400 ; start of RAM disk : disk screen #0 is unusable so offset FIRSTB back 1K
LIMITB EQU $FFFF ; end of RAM disk area (CONSTANT variable not currently used)
endi
if memory_model = custom ; custom memory model - edit for user system needs
START_OF_ROM EQU $8000 ; code start
START_OF_RAM EQU $C000 ; start of RAM area - must be on a page boundry
END_OF_RAM EQU $E000 ; end of RAM block - first byte after
FIRSTB EQU END_OF_RAM - $0400 ; start of RAM disk : disk screen #0 is unusable so offset FIRSTB back 1K
LIMITB EQU $FFF0 ; end of RAM disk area (CONSTANT variable not currently used)
endi
if memory_model = -1
START_OF_ROM EQU $xxxx ; code start
START_OF_RAM EQU $yyyy ; start of RAM area - must be on a page boundry
END_OF_RAM EQU $zz00 ; end of RAM block - first byte after
FIRSTB EQU $w000 ; start of RAM disk : disk screen #0 is unusable so offset FIRSTB back 1K
LIMITB EQU $yyyy ; end of RAM disk area (CONSTANT variable not currently used)
endi
;========================== FORTH RAM Layout - change at your own risk =============================
S0_START EQU END_OF_RAM-$0200 ; data stack (grows up) S0
R0_START EQU END_OF_RAM-$0101 ; return stack (grows down) R0
USER_START EQU END_OF_RAM-$0100 ; USER area - 64 variables max UP
TIB_START EQU END_OF_RAM-$0080 ; terminal input buffer TIB
if (uart_type = hardware)
tx_buffer EQU END_OF_RAM-$0400 ; Reserve 256 bytes of RAM for UART rx and tx buffers NOTE : buffers must be on page boundaries
rx_buffer EQU END_OF_RAM-$0300 ;
endi
task1stacks EQU END_OF_RAM-$0780 ; Reserve RAM for seven task stacks - task0stacks0 is the user task - uses default S0 & R0 values
task2stacks EQU END_OF_RAM-$0700 ;
task3stacks EQU END_OF_RAM-$0680 ;
task4stacks EQU END_OF_RAM-$0600 ;
task5stacks EQU END_OF_RAM-$0580 ;
task6stacks EQU END_OF_RAM-$0500 ;
task7stacks EQU END_OF_RAM-$0480 ;
;========================== Power Up Entry Points ======================================================================
if (lbr_at_zero = yes) and (START_OF_ROM <> $0000)
ORG $0000 ; optional LBR START for memory maps where code does not start at $0000 (omit for making ROMS)
DIS ;
DB $00
LBR START
endi
ORG START_OF_ROM ; code start
START: ; entry point on power up when PC = R0
DIS ; disable interrupts / PC = R0 SP = R0
DB $00 ; DIS instruction loads 0 to P and X
if (uart_type = software)
SEQ ; set Q high for software UART
endi
LDI high COLD ; initialize R3 as program counter
PHI R3 ;
LDI low COLD ;
PLO R3 ;
SEP R3 ;
;========================== Cold Start Entry Point ======================================================================
;
; entry point assumes P=3, X=? and resets everything to default state
;
COLD: LDI low (USER_IMAGE_COLD-USER_IMAGE) ; initialize cold start USER data initialization ( currently 22 bytes)
LSKP ; skip warm start entry point
;========================== Warm start Entry Point ======================================================================
;
; entry point assumes P=3, X=? and resets everything except any new dictionary workds
;
WARM: LDI low (USER_IMAGE_WARM-USER_IMAGE) ; initialize warm start USER data initialization ( currently 16 bytes)
PLO RF ; RF.0 = count of bytes to initialize
LDI high USER_BASE ; R7 -> USER area image in ROM
PHI R7 ;
LDI low USER_BASE ;
PLO R7 ;
LDA R7 ; RD , R8 -> USER area pointer store in ROM
PHI RD ;
PHI R8 ;
LDA R7 ;
PLO R8 ;
PLO RD ;
LDI low USER_IMAGE ; R7 -> USER area image in ROM
PLO R7 ;
COPYLOOP: ; Copy intialization data (warm or cold)
LDA R7 ;
STR R8 ;
INC R8 ;
DEC RF ;
GLO RF ;
BNZ COPYLOOP ;
; SNEAKY HACK : R7 content flags if this was a warm or cold start for later STARTUP usage
LDI high NEXT ; RC -> inner interpreter NEXT
PHI RC ;
LDI low NEXT ;
PLO RC ;
LDI low ABRT2 ; RA = Forth "I" or "Instruction" Register -> ABORT + 2 (i.e. NEST is assumed)
PLO RA ;
LDI high ABRT2 ;
PHI RA ;
;
if zero_ram eq 1
LDI high START_OF_RAM ; zero out all RAM - useful for debugging as memory dumps are easier to understand
PHI R2 ;
LDI low START_OF_RAM ;
PLO R2 ;
zrloop: LDI $00 ;
STR R2 ;
INC R2 ;
GLO R2 ;
SMI low R0_START ;
BNZ zrloop ;
GHI R2 ;
SMI high R0_START ;
BNZ zrloop ;
endi
;
LDI high R0_START ; set R2 to return stack address
PHI R2 ;
LDI low R0_START ;
PLO R2 ;
SEX R3 ; interrupts off, PC=3, SP=2
DIS ;
DB $23 ;
GLO R7 ; NOTE : hack to make WARM start work based on where it stopped during copy of initialzed variables
SMI low USER_IMAGE_COLD - 1 ;
BGE warm_init ;
;
cold_init: ;
LDI high (PROM_TABLE_WARM_END-PROM_TABLE) ; warm start tranfer initialized variable table from ROM to RAM
PHI RF ;
LDI low (PROM_TABLE_WARM_END-PROM_TABLE) ;
PLO RF ;
BR start1 ;
warm_init: ;
LDI high (PROM_TABLE_COLD_END-PROM_TABLE) ; warm start tranfer initialized variable table from ROM to RAM
PHI RF ;
LDI low (PROM_TABLE_COLD_END-PROM_TABLE) ;
PLO RF ;
start1: LDI high PROM_TABLE ;
PHI R7 ;
LDI low PROM_TABLE ;
PLO R7 ;
LDI high START_OF_RAM ;
PHI R8 ;
LDI low START_OF_RAM ;
PLO R8 ;
STRT1: LDA R7 ;
STR R8 ;
INC R8 ;
DEC RF ;
GLO RF ;
BNZ STRT1 ;
GHI RF ;
BNZ STRT1 ;
;
if (uart_type = hardware)
LDI high rx_optr+DELTA ; intialize UART Tx and RX buffer pointers
PHI R8 ;
LDI low rx_optr+DELTA ;
PLO R8 ;
LDI $00 ;
STR R8 ;
INC R8 ;
STR R8 ;
INC R8 ;
INC R8 ;
STR R8 ;
INC R8 ;
STR R8 ;
;
INP 5 ; initialize UART
INP 6 ;
LDI uart_config ;
STR R2 ;
OUT 5 ;
DEC R2 ;
INP 5 ; clear UART status and data registers
INP 6 ;
endi
LDI high R0_START ; initialize R2 = ISR -> stack pointer
PHI R2 ;
LDI low R0_START ;
PLO R2 ;
LDI high TASKLIST+DELTA ; setup multi tasking registers R4, R4
PHI R4 ;
LDI low TASKLIST+DELTA ;
PLO R4 ;
LDI high TCB+DELTA ;
PHI R5 ;
LDI low TCB+DELTA+5 ;
PLO R5 ;
if (uart_type = hardware)
;
LDI high ISRentry ; initialize R1 = ISR PC ( for UART and task timers )
PHI R1 ;
LDI low ISRentry ;
PLO R1 ;
LDI $23 ; enable interrupts / PC = R3 SP = R2
STR R2 ;
RET ;
else
LDI $00 ; start with interrupts off and ISR disabled
PHI R1 ;
PLO R1 ;
endi
LBR RP1A ; jump to RP! word - loads the stack pointer and then does a SEP RC into the inner interpreter
;============================================== Legacy fig-FORTH Standard Initializationds Header Area ========================================
ORIGIN equ $ - 8 ; CAUTION : USER variables and some initialization values are hard coded by +ORIGIN from here
; ( <-- in FIG model, space for cold and warm start jumps was here )
DW 1802 ; CPU NUMBER
DW 7 + memory_model ; printed version # will be 7,8,9,or 10 depending on lmemory_model selected
;
USER_IMAGE: ; base of USER area (copied to RAM @ 7F00) - USER variable are relative to the relocated address?
DW FORTH-8+DELTA ; top most word in FORTH vocabulary ( was TASK - 7 ) $407D
DW $0008 ; backspace
USER_BASE: ;
DW USER_START ; USER area UP
DW S0_START ; data stack S0
DW R0_START ; return stack R0
DW TIB_START ; terminal input buffer TIB
DW $001F ; name field width WIDTH
DW $0001 ; warning WARNING
DW $0001 ; caps lock flag CAPS
USER_IMAGE_WARM: ;
DW PROM_TABLE_COLD_END+DELTA ; FENCE
DW PROM_TABLE_COLD_END+DELTA ; DP
DW ASSEM1+DELTA ; VOC-LINK
USER_IMAGE_COLD: ;
;============================================== Preload table of initializtion of variables stored in RAM =====================================================
; Note : this table holds variable with initialized values. It are relocated to RAM during system startup
;
PROM_TABLE: ; <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
DELTA EQU START_OF_RAM - PROM_TABLE ; offset to where intialized variable will be located & initialized from values stored in EPROM
if (extra_hardware = yes) ; Note : this must be on a page boundary when moved to RAM to map 6321's ports via
; OUT 4 instruction
;
PPORT: DB $00, $00, $00, $00 ; 6845 Parrallel Port Bytes 0 - 3 ( relocates to $4000 )
lcd_buffer DB $0,$0,$0,$0,$0,$0,$0,$0 ; Reserve RAM for LCD display drivers
;
endi ;
if (uart_type = hardware) ;
; CDP1854 UART ISR pointers and data buffers - only needs to be 8 bit ptr as buffers are page aligned and exactly a page long
rx_optr: DB $0 ; NOTE : ORDER MATTERS HERE as ISR assumes 5 bytes ordered this way
rx_iptr: DB $0 ;
xonxoff: DB $0 ; set to one to force an initial XON
tx_iptr: DB $0 ;
tx_optr: DB $0 ;
uart_errors: DB $0, $0, $0 ; overrun error , parity error , framing error counters
endi
if (uart_type = software)
qtermflag DB $00 ; flag for indicating keyboard activity - used by ?TERMINAL word
endi
TIMERS: ; task tic timers
DB $00, $00, $00, $00, $00, $00, $00, $00 ; Warning: must all be on same page
prescaler: DB $00 ; tic timer prescaler (must be immediately after TIMERS
if ( ((high prescaler) - (high TIMERS)) <> 0 )
BR cold ; ERROR : off page computed branch detected !!
endi
TASKLIST: ; tasker ( PC= R4 - each task runs when SKP is replaced with SEP R3 - self modifying code)
SEP R3 ; 0
DB low TCB+DELTA+00 ;
SKP ; 1
DB low TCB+DELTA+06 ;
SKP ; 2
DB low TCB+DELTA+12 ;
SKP ; 3
DB low TCB+DELTA+18 ;
SKP ; 4
DB low TCB+DELTA+24 ;
SKP ; 5
DB low TCB+DELTA+30 ;
SKP ; 6
DB low TCB+DELTA+36 ;
TL7: SKP ; 7
DB low TCB+DELTA+42 ;
;
if (timer_type = software) ; fake TIC_timer_update (hard coded branch instructions to get
; around A18 limitation when TASKLIST is above $8000
;
LDI high TL7+DELTA ; R7 -> last task SKP / SEP RC instruction
PHI R7 ;
LDI low TL7+DELTA ;
PLO R7 ;
LDI high prescaler+DELTA ; R8 -> task timer pre-scaler (last entry in task timer block)
PHI R8 ;
LDI low prescaler+DELTA ;
PLO R8 ;
LDN R8 ; update tic timer prescaler value
SMI $01 ;
STR R8 ;
DB $3A, low (TASKLIST+DELTA) ; BNZ don't adjust task tic timers until prescaler hits zero
LDI prescaler_value ; else reset prescaler
STR R8 ;
DEC R8 ; and go update each task's tic timer
check_timers: ;
LDN R8 ; get next timer
DB $32, low (next_timer1+DELTA) ; BZ to relocated address if its not running
SMI $01 ; decrement timer
STR R8 ; save new value
DB $3A, low (next_timer1+DELTA) ; BNZ jump if still not zero
LDI $D3 ; else push $D3 to RAM buffer to activate task as timer has expired
STR R7 ;
next_timer1:
DEC R7 ; back up task list
DEC R7 ;
DEC R8 ; next timer byte
GLO R8 ; check if pointer back past start of table
SMI low TIMERS+DELTA-1 ;
DB $3A, low (check_timers+DELTA) ; BNZ loop back if not at end of buffer
endi
DB $30, low (TASKLIST+DELTA) ; BR Warning : must be on same page
TCB: DW R0_START, S0_START , null_task ; 0 - terminal task
DW task1stacks+$0080, task1stacks, null_task ; 1
DW task2stacks+$0080, task2stacks, null_task ; 2
DW task3stacks+$0080, task3stacks, null_task ; 3
DW task4stacks+$0080, task4stacks, null_task ; 4
DW task5stacks+$0080, task5stacks, null_task ; 5
DW task6stacks+$0080, task6stacks, null_task ; 6
DW task7stacks+$0080, task7stacks, null_task ; 7
LED_BUF_POINTER DB low LED_BUFFER+DELTA ; holds the current digit address being displayed on the six digit display
LED_BUFFER DB "ACE 1802 Forth " ; allocate 20 bytes either blank or a default string
PROM_TABLE_WARM_END
;
; -----------------------------------------------------------------------------
DB $C9,"ASSEMBLE",$D2 ; ASSEMBLER Vocabulary Link - must be located in RAM
DW FORTH_LAST_WORD ; link back into main forth vocabulary tree
ASSEMBLER: DW DUZ1 ; PFA -> DOES
DW VB1 ; VOCABULARY
DW $81A0 ; fake header ( space ) - its LFA is the next word
if assembler = 0 ;
DW FRTH0+DELTA ; link to LATEST address for this vocabulary
else ;
DW ASSEMBLER_LAST_WORD ;
endi ;
ASSEM1: DW ED1+DELTA ; link to previous dictionary $407B
;
; -----------------------------------------------------------------------------
DB $C6,"EDITO",$D2 ; EDITOR Vocabulary Link - must be located in RAM
DW ASSEMBLER-12+DELTA ; NFA of ASSEMBLER
EDITOR: DW DUZ1 ; PFA -> DOES
DW VB1 ; VOCABULARY
DW $81A0 ; fake header ( space ) - its LFA is the next word
if editor = 0 ;
DW FRTH0+DELTA ; link to LATEST address for this vocabulary
else ;
DW EDITOR_LAST_WORD ; link to LATEST address for this vocabulary
endi ;
ED1: DW FRTH1+DELTA ; link to previous dictionary $408D
;
; -----------------------------------------------------------------------------
DB $C5,"FORT",$C8 ; FORTH Vocabulary Link - must be located in RAM
DW EDITOR-9+DELTA ; NFA of EDITOR
FORTH: DW DUZ1 ; PFA -> DOES
DW VB1 ; VOCABULARY
FRTH0: DW $81A0 ; fake header ( space ) - its LFA is the next word
DW FORTH-8+DELTA ; link to LATEST address for this vocabulary
FRTH1: DW $0000 ; link to previous dictionary - 0 means this is the root vocab
PROM_TABLE_COLD_END: ;<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
PAGE
;**********************************************************************************************************************************
;************************** Hardware Customization Section for Console and Timer Starts Here**************************************
;**********************************************************************************************************************************
if ( uart_type = software )
; HOTE : software UART transmits the value in D out via the Q line, receives characters via EF3
; - 1.8MHz = 5.8 2 cycle instructions per bit
; - 4.0MHz = 13.0 2 cycle instructions per bit (add 7 2 cycle or 4 NOP + 1 2 cycle)
;=================================================================
;
; KEY : software UART via Q and EF
;`
;=================================================================
;
getKEY: GLO R1 ; are interrupts disabled (i.e. console input in process) ?
BZ key_ints_off ; go wait for the next character if so
B3 activate_console ; otherwise is an incoming character detected?
LBR tsk_repeat ; keep multi-tasking if not
;
activate_console: ; serial input activity detected so activate console input
SEX R3 ; disable interrupts
DIS ;
db $23 ; PC = 3, SP = 2
LDI $00 ; flag interrupts as off for console input by destroying the ISR entry address held in R1
PLO R1 ;
INC R9 ; ignore the incoming character as we were likely too slow to rx it correctly
INC R9 ;
STR R9 ;
INC R9 ;
LDI $0D ; save a CR on the stack instead and send that back
STR R9 ;
DEC R9 ;
LBR TASKER ; done
;
key_ints_off: ;
BN3 $ ; wait for start bit
LDI $00 ; nop - one byte that also sets D=0 and being empty means
; ... that no bits will shift out the first 7 times through the loops below
LDI $00 ; nop (first time through will set a bit to shift in. When it shifts out,
; ... 8 bits have been sent).
spc: SMI $0 ; set DF (first time through will set a bit to shift in. When it shifts out,
; ... 8 bits have been sent).
mark: SHRC ; shift next serial bit in to rx byte ( DF = 0 if we jump directly here.
; ... DF = 1 if we are falling throught from the SHRC instruction above)
BDF kdone ; if a bit pops out of D when shifted it means we have shifted 8 times
;
if clock_mhz = 4 ;
NOP ; 1.5 additional instruction ( 6 usec per nop )
NOP ; 3.0
NOP ; 4.5
NOP ; 6.0
SEP R3 ; 2 cycle NOP
endi ;
SEP R3 ; nop (as P = 3 already )
SEP R3 ; nop
BN3 spc ; jump if next serial bit a zero
BR mark ; otherwise it's a one
kdone: ;
INC R9 ; save received character
INC R9 ;
INC R9 ;
STR R9 ;
SMI $0D ; was it a CR ?
BNZ kd1 ;
GHI R1 ; is there a valid ISR address in R1.1 ?
BZ kd1 ; don't reenable interrupts if not - assume ints disabled via the DI word
;
LDI low ISR ; re=enable interrupts if CR and they are not user disabled
PLO R1
SEX R3 ; enable interrupts
RET ;
db $23 ; PC = 3, SP = 2
kd1: ;
DEC R9 ;
LDI $00 ;
STR R9 ;
LBR TASKER ; done
;=================================================================
;
; EMIT : software UART via Q and EF
;
;=================================================================
; software UART the value in D out on the Q line
; - 1.8MHz = 5.8 2 cycle instructions per bit
; - 4.0MHz = 13.0 2 cycle instructions per bit (add 7 2 cycle or 4 NOP + 1 2 cycle)
;----------------------------------------------------------------------
;
CSEND: DW $+2 ;
INC R9 ; pop tx char from computation stack
LDN R9 ;
DEC R9 ; and cleanup computation stack
DEC R9 ;
DEC R9 ;
;
SEX R3 ; disable interrupts for now but don't flag them as being off for console input
DIS ;
db $23 ;
REQ ; send start bit
if clock_mhz = 4
NOP ; 1.5 additional instruction ( 6 usec per nop )
NOP ; 3.0
NOP ; 4.5
NOP ; 8.0
REQ ; 9.5
endi
SHRC ; check first data bit by shifting into DF
PHI RE ; RE.1 = remaining bits to be sent
;
LDI 4 ; bit count = 4
PLO RE ; RE.0 = bit counter
BDF SEQ1 ; jump if next data bit is a 1
;
REQ1: REQ ; data bit was a zero so reset Q
;
if clock_mhz = 4
NOP ; 1.5 additional instruction ( 6 usec per nop )
NOP ; 3.0
NOP ; 4.5
NOP ; 8.0
REQ ; 8.0
endi
GHI RE ; D = remaining data bits
SHRC ; move next bit into DF
BDF SEQ2 ; jump if it's a 1
REQ2: SHRC ; data bit was a zero
PHI RE ; RE.1 = remainging data bits
REQ ; data bit was a zero so reset Q
if clock_mhz = 4
NOP ; 1.5 additional instruction ( 6 usec per nop )
NOP ; 3.0
NOP ; 4.5
NOP ; 8.0
REQ ; 9.5
endi
;
REQ ; 2 cycle "nop" in place of BR at end of EQ2
;
OLOOP: ;
DEC RE ; decrement bit count
GLO RE ; check if we are all done
BZ STOP ; exit if so
BNF REQ1 ; else go process next bit
;
SEQ1: SEQ ; data bit was a one so set Q
;
if clock_mhz = 4
NOP ; 1.5 additional instruction ( 6 usec per nop )
NOP ; 3.0
NOP ; 4.5
NOP ; 8.0
SEQ ; 8.0
endi
GHI RE ; RE.1 = remainging data bits
SHRC ; move next bit into DF
BNF REQ2 ; jump if it's a 0
SEQ2: SHRC ; data bit was a zero
PHI RE ; RE.1 = remainging data bits
SEQ ; data bit was a zero so rest Q
if clock_mhz = 4
NOP ; 1.5 additional instruction ( 6 usec per nop )
NOP ; 3.0
NOP ; 4.5
NOP ; 8.0
SEQ ; 8.0
endi
BR OLOOP ; go process next bit (also a 2 cycle "nop")
;
STOP: SEQ ; all done so set line to idle state
GHI R1 ; is there a valid ISR address in R1.1 ?
BZ no_int_enable ; don't reenable interrupts if user disabled is DI word
GLO R1 ; are interrupts off for console input?
BZ no_int_enable ; don't turn them back on if so
SEX R3 ; re-enable interupts
RET ;
DB $23 ;
no_int_enable:
LBR TASKER ; done
;=================================================================
;
; ?TERMINAL : software UART via Q and EF
;
;=================================================================
qTERM: ;
INC R9 ; prep data stack pointer
INC R9 ;
LDI $00 ;1
STR R9 ;
INC R9 ;
LDI high qtermflag ; else point R7 to the ?TERMINAL flag
PHI R7 ;
LDI low qtermflag ;
PLO R7 ;
LDN R7 ; get ?TERMINAL flag
BZ qT1 ;
LDI $01 ;
qT1: STR R9 ; save # of chars on stack ( 0 = false = not data )
DEC R9 ;
LDI $00 ; clear the flag
STR R7 ;
LBR TASKER ; all done if buffer not empty
else
;=================================================================
;
; KEY : CDP1854 UART Version with interrupt support
;
;=================================================================
XOFF_LIMIT EQU $80 ; characters in rx buffer when XOFF sent
XON_LIMIT EQU $F0 ; free space in rx buffer when XON sent
getKEY: SEX R8 ;
LDI high rx_optr+DELTA ; R8 -> rx output pointer
PHI R8 ;
LDI low rx_optr+DELTA ;
PLO R8 ;
LDI high rx_iptr+DELTA ; R7 -> rx insert pointer
PHI R7 ;
LDI low rx_iptr+DELTA ;
PLO R7 ;
LDN R7 ;
SM ; if rx_iptr = rx_optr then rx buffer is empty
LBZ tsk_repeat ; nothing ready - reset the I/O routine to run on next outer interpreter pass (assume no XON needed)
;
INC R9 ; pull next rx char from buffer to computation stack
INC R9 ;
LDI $00 ; high byte = 0
STR R9 ;
INC R9 ;
LDI high rx_buffer ; R7 -> rx buffer
PHI R7 ;
LDN R8 ; get optr advance and wrap
ADI $01 ;
PLO R7 ; R7 -> next rx buffer space
STR R8 ; save new value of optr
LDN R7 ; read from rx buffer <- R7 (optr) and advance pointer
STR R9 ; save on data stack
;
LDI $00 ; destroy the char in the buffer to make sure we are not getting repeats from there during this debug process
STR R7 ;
;
GHI RD ; is virtual caps lock enabled in USER variable CAPS?
PHI R7 ;
GLO RD ;
ADI low capslock + 1 ; low byte only
PLO R7 ;
LDN R7 ;
BNZ filter_char ;
LDN R9 ; check for SI (shift in) to enable caps lock / filtering
SMI $0F ;
BNZ accept_char ;
;
filter_char: ;
LDN R9 ; check for control characters
SMI $1F ;
BGE not_ctrl ;
LDN R9 ; accept a carriage return
SMI $0D ;
BZ accept_char ;
LDN R9 ; accept a backspare
SMI $08 ;
BZ accept_char ;
LDN R9 ;
SMI $0E ; process SO (shift out) to disable caps lock / CTRL filters
BNZ not_SO ;
LDI $00 ;
STR R7 ;
BR ignore_char ;
not_SO: LDN R9 ;
SMI $0F ; process SI (shift in) to enable caps lock / CTRL filer
BNZ ignore_char ;
LDI $01 ;
STR R7 ;
ignore_char: ;
DEC R9 ;
DEC R9 ;
DEC R9 ;
LBR tsk_repeat ; reset the I/O routine to run on next outer interpreter pass
;
not_ctrl: ;
LDN R9 ;
ANI $80 ; mask for 7 bit ASCII only
BNZ ignore_char ;
; LDN R9 ; Caps Lock emulation
; SMI $61 ;
; BL accept_char ; is this a lower case character?
; LDN R9 ;
; SMI $7B ;
; BGE accept_char ;
; LDN R9 ; convert to upper case if so
; ANI $DF ;
; STR R9 ;
accept_char: ;
DEC R9 ;
LDI $00 ;
STR R9 ;
; check space left in input buffer
LDA R8 ; load D with optr and set R8 -> iptr
SM ; check rx buffer space D = optr - iptr = free space
SMI XON_LIMIT ; $D0 ; $F0 ? ; check if there is more than 208 bytes free in the buffer
LBNF TASKER ; done if not - no need to check for if an XON is needed yet
;
LDI high xonxoff+DELTA ; otherwise check if we need to send an XON : rx buffer has enough space to re-enable receiving data
PHI R8 ;
LDI low xonxoff+DELTA ;
PLO R8 ;
LDN R8 ; XON already sent?
LBZ TASKER ; skip out if so
;
SEX R8 ;
LDI high tx_iptr+DELTA ; R8 -> tx buffer insert pointer
PHI R8 ;
LDI low tx_iptr+DELTA ;
PLO R8 ;
LDI high tx_buffer ; R7 -> tx buffer previous character location
PHI R7 ;
LDA R8 ; R8 moves to -> tx_optr via LDA - order matters
ADI $01 ; advance tx_iptr and wrap if necessary
PLO R7 ;
SM ; check if about to overrun tx buffer?
LBZ TASKER ; don't try to send an XON if tx buffer is full
;
LDI XON ;
STR R7 ; store XON char in tx buffer
DEC R8 ; update tx_iptr after saving tx character in buffer (i.e. ISR safe)
GLO R7 ;
STR R8 ;
;
LDI high xonxoff+DELTA ; clear xoff flag (Warning : is this interrupt safe ?)
PHI R8 ;
LDI low xonxoff+DELTA ;
PLO R8 ;
LDI $00 ;
STR R8 ;
;
SEX R2 ; check if UART currently transmitting and start if not
DEC R2 ;
INP 5 ;
ANI $C0 ;
SMI $C0 ; THRE * TSRE both set = UART not transmitting
BNZ tx_active2 ;
;
LDI uart_config ; toggle TR off
STR R2 ;
OUT 5 ;
DEC R2 ;
LDI uart_config+$80 ; set TR bit in UART control register
STR R2 ;
OUT 5 ;
SKP ;
tx_active2: ;
INC R2 ;
LBR TASKER ; done
;=================================================================
;
; EMIT : CDP1854 UART Version with interrupt support
;
;=================================================================
CSEND: DW $+2 ;
SEX R8 ;
LDI high tx_iptr+DELTA ; R8 -> tx buffer insert pointer
PHI R8 ;
LDI low tx_iptr+DELTA ;
PLO R8 ;
LDI high tx_buffer ; R7 -> tx buffer previous character location
PHI R7 ;
LDA R8 ; R8 moves to -> tx_optr via LDA - order matters
ADI $01 ; advance tx_iptr and wrap if necessary
PLO R7 ;
SM ; check if about to overrun tx buffer?
LBZ tsk_repeat ; busy outer interpreter loop until ISR moves the tx_optr
;
INC R9 ; pop tx char from computation stack
LDN R9 ;
DEC R9 ; and cleanup computation stack
DEC R9 ;
DEC R9 ;
STR R7 ; store char in tx buffer
DEC R8 ; update tx_iptr after saving tx character in buffer (i.e. ISR safe)
GLO R7 ;
STR R8 ;
;
SEX R2 ; check if UART currently transmitting and start if not