SDHC_CLK_FREQ definition relationship to final SDHC clock freq is unclear from comments

[JordanAceto]

The comments here make reference to using this definition to control the SDHC clock frequency, but it is not super clear what the final frequency will be without a lot of datahsheet digging.

msdk/Libraries/SDHC/Include/sdhc_lib.h

Lines 39 to 47 in ef6c81d

	#ifndef SDHC_CLK_FREQ
	/**
	* @brief SDHC target clock frequency.
	* @details Max freq. is limited by GCR register to be @ref SystemCoreClock / 2 or @ref SystemCoreClock / 4.
	* This field is used as a target for the SDHC peripheral's internal clock divider.
	* R/W reliability issues can sometimes be eliminated by reducing the clock frequency, which is a good first step for troubleshooting.
	*/
	#define SDHC_CLK_FREQ 40000000
	#endif

For example, on the MAX32650 we are using, the SDHC clock is fed from 120MHz / 2, and an integer divider is calculated based on the value of SDHC_CLK_FREQ. You can set SDHC_CLK_FREQ to any integer you want, but the actual clock frequency will only be taken from a set of a few integer divisions of 60MHz.

Ex:

• Define SDHC_CLK_FREQ as 30'000'001
• sdhc_input_clk_freq / (2 * SDHC_CLK_FREQ) -> 0
• So the actual SDHC clock freq is 60MHz, pretty far off if you thought you were getting 30MHz

I'm not sure what the best move is. I don't think you can document every possible combo. But it could be more clear that there are really only a small handful of meaningful values of SDHC_CLK_FREQ for a given processor.