diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad9088.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad9088.yaml new file mode 100644 index 00000000000000..b69a6ca03857b8 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad9088.yaml @@ -0,0 +1,249 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/adi,ad9088.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices AD9088 Mixed Signal Front End (MxFE) + +maintainers: + - Michael Hennerich + +description: | + Bindings for the Analog Devices AD9088 and compatible MxFE devices. + +properties: + compatible: + enum: + - adi,ad9084 + - adi,ad9088 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: dev_clk + description: Device clock name + + '#clock-cells': + const: 0 + + clock-output-names: + maxItems: 1 + + adi,spi-3wire-enable: + type: boolean + description: Enable 3-wire SPI mode. + + adi,device-profile-fw-name: + $ref: /schemas/types.yaml#/definitions/string + description: Name of the device profile firmware file. + + adi,rx-real-channel-en: + type: boolean + description: Enable real RX channel mode (complex if not present). + + adi,tx-real-channel-en: + type: boolean + description: Enable real TX channel mode (complex if not present). + + adi,side-b-use-seperate-tpl-en: + type: boolean + description: Use separate TPL for side B. + + adi,hsci-auto-linkup-mode-en: + type: boolean + description: Enable HSCI auto linkup mode. + + adi,hsci-disable-after-boot-en: + type: boolean + description: Disable HSCI after initial configuration. + + adi,multidevice-instance-count: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Number of multidevice instances. + + adi,trigger-sync-en: + type: boolean + description: Enable trigger synchronization. + + adi,standalone-enable: + type: boolean + description: Enable standalone mode. + + adi,nyquist-zone: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2] + description: Nyquist zone (1 or 2). + + adi,jtx0-logical-lane-mapping: + minItems: 12 + maxItems: 12 + items: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Logical lane mapping for JTX0. + + adi,jtx1-logical-lane-mapping: + minItems: 12 + maxItems: 12 + items: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Logical lane mapping for JTX1. + + adi,jrx0-physical-lane-mapping: + minItems: 12 + maxItems: 12 + items: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Physical lane mapping for JRX0. + + adi,jrx1-physical-lane-mapping: + minItems: 12 + maxItems: 12 + items: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Physical lane mapping for JRX1. + + adi,jtx-ser-amplitude: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Serializer amplitude setting. + + adi,jtx-ser-pre-emphasis: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Serializer pre-emphasis setting. + + adi,jtx-ser-post-emphasis: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Serializer post-emphasis setting. + + adi,subclass: + $ref: /schemas/types.yaml#/definitions/uint32 + description: JESD subclass setting. + + adi,gpio-hop-profile: + minItems: 1 + maxItems: 5 + items: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + GPIO indices for frequency hopping profile selection. + Supports up to 5 GPIOs for profile control. Missing values + are filled with -1 (ADI_APOLLO_GPIO_HOP_IDX_NONE). + + adi,gpio-hop-block: + minItems: 1 + maxItems: 4 + items: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + GPIO indices for frequency hopping block selection. + Supports up to 4 GPIOs for block control. Missing values + are filled with -1 (ADI_APOLLO_GPIO_HOP_IDX_NONE). + + adi,gpio-hop-side: + maxItems: 1 + items: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + GPIO index for frequency hopping side selection. + Supports 1 GPIO for side control. Missing value is + filled with -1 (ADI_APOLLO_GPIO_HOP_IDX_NONE). + + adi,gpio-hop-slice: + minItems: 1 + maxItems: 5 + items: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + GPIO indices for frequency hopping slice selection. + Supports up to 5 GPIOs for slice control. Missing values + are filled with -1 (ADI_APOLLO_GPIO_HOP_IDX_NONE). + + adi,gpio-hop-terminal: + minItems: 1 + maxItems: 4 + items: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + GPIO indices for frequency hopping terminal selection. + Supports up to 4 GPIOs for terminal control. Missing values + are filled with -1 (ADI_APOLLO_GPIO_HOP_IDX_NONE). + + adi,gpio-sniffer-a-export: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + GPIO pin number for FFT sniffer side A done signal export. + Used to export FFT done status to external GPIO pin. + Defaults to 17 if not specified. + + adi,gpio-sniffer-b-export: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + GPIO pin number for FFT sniffer side B done signal export. + Used to export FFT done status to external GPIO pin. + Defaults to 18 if not specified. + +required: + - compatible + - adi,device-profile-fw-name + +additionalProperties: false + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + - $ref: /schemas/jesd204/jesd204-device-props.yaml# + +examples: + - | + #include + + spi { + #address-cells = <1>; + #size-cells = <0>; + + trx0_ad9084: ad9084@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "adi,ad9084"; + reg = <0>; + spi-max-frequency = <5000000>; + + /* Clocks */ + clocks = <&adf4382 0>; + clock-names = "dev_clk"; + dev_clk-clock-scales = <1 10>; + + clock-output-names = "rx_sampl_clk", "tx_sampl_clk"; + #clock-cells = <1>; + + adi,axi-hsci-connected = <&axi_hsci>; + + adi,hsci-auto-linkup-mode-en; + adi,hsci-disable-after-boot-en; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-top-device = <0>; /* This is the TOP device */ + jesd204-ignore-errors; + + jesd204-link-ids = ; + + jesd204-inputs = + <&axi_ad9084_core_rx 0 FRAMER_LINK_A0_RX>, + <&axi_ad9084_core_tx 0 DEFRAMER_LINK_A0_TX>; + + reset-gpios = <&axi_gpio 62 0>; + adi,device-profile-fw-name = "DEVICE_PROFILE_NAME"; + + /* GPIO frequency hopping configuration (optional) */ + adi,gpio-hop-profile = <19 20 21 22 23>; + adi,gpio-hop-block = <15 16 17 18>; + + /* FFT sniffer GPIO exports (optional) */ + adi,gpio-sniffer-a-export = <17>; + adi,gpio-sniffer-b-export = <18>; + }; + }; diff --git a/Documentation/devicetree/bindings/iio/frequency/adi,adf4382.yaml b/Documentation/devicetree/bindings/iio/frequency/adi,adf4382.yaml new file mode 100644 index 00000000000000..5d9a91ffb3cbad --- /dev/null +++ b/Documentation/devicetree/bindings/iio/frequency/adi,adf4382.yaml @@ -0,0 +1,141 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/frequency/adi,adf4382.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ADF4382 Microwave Wideband Synthesizer with Integrated VCO + +maintainers: + - Antoniu Miclaus + - Ciprian Hegbeli + +description: The ADF4382 is a high performance, ultralow jitter, Frac-N PLL with + integrated VCO ideally suited for LO generation for 5G applications + or data converter clock applications. + + https://www.analog.com/en/products/adf4382a.html + +properties: + compatible: + enum: + - adi,adf4382 + - adi,adf4382a + + reg: + maxItems: 1 + + spi-max-frequency: + maximum: 75000000 + + clocks: + description: Clock to provide CLKIN reference clock signal. + maxItems: 1 + + clock-names: + description: + External clock that provides reference input frequency. + items: + - const: ref_clk + + '#clock-cells': + const: 0 + + clock-output-names: + maxItems: 1 + + adi,charge-pump-microamp: + description: + The charge pump current that the external loop filter was designed for. + If this property is not specified, then the charge pump current is set to the + default 11100uA. The valid values are listed below. However, if the set value is + not supported, the driver will look for the closest valid charge pump current. + anyOf: + - enum: [790, 990, 1190, 1380, 1590, 1980, 2390, 2790, 3180, 3970, 4770, 5570, 6330, 7910, 9510, 11100] + + adi,ref-divider: + description: + Input divider of the reference frequency, cannot be lower then 1 or + higher then 63. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - minimum: 1 + - maximum: 63 + - default: 1 + maxItems: 1 + + adi,ref-doubler-enable: + description: + Enables the doubling of the reference clock. + type: boolean + maxItems: 1 + + adi,bleed-word: + description: + A small programmable constant charge pump current, known as bleed current, + can be used to optimize the phase noise and fractional spurious signals + in fractional mode. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - minimum: 0 + - maximum: 4095 + - default: 0 + maxItems: 1 + + adi,power-up-frequency: + description: + PLL tunes to the set frequency on probe or defaults to 2,305 GHz. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint64 + - minimum: 687500000 + - maximum: 22000000000 + - default: 2305000000 + maxItems: 1 + + adi,output-power-value: + description: + The output power amplitude level which will be applied for both channels + at startup. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - minimum: 0 + - maximum: 15 + - default: 11 + maxItems: 1 + + adi,spi-3wire-enable: + description: + Uses SPI in 3 wire mode, by default is uses 4 wire mode. + type: boolean + maxItems: 1 + + adi,cmos-3v3: + description: + Sets the SPI logic to 3.3V, by defautl it uses 1,8V. + type: boolean + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + frequency@0 { + compatible = "adi,adf4382"; + reg = <0>; + spi-max-frequency = <1000000>; + clocks = <&adf4382_clkin>; + clock-names = "ref_clk"; + adi,charge-pump-current = <15>; + adi,ref-divider = <1>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/jesd204/jesd204-device-props.yaml b/Documentation/devicetree/bindings/jesd204/jesd204-device-props.yaml new file mode 100644 index 00000000000000..6a429ab957c9a7 --- /dev/null +++ b/Documentation/devicetree/bindings/jesd204/jesd204-device-props.yaml @@ -0,0 +1,160 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/jesd204/jesd204-device-props.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: JESD204 Device Node properties. + +maintainers: + - Michael Hennerich + +description: | + Bindings for JESD204 framework devices and topologies. + +properties: + jesd204-device: + type: boolean + description: Indicates this node is a JESD204 device. + + jesd204-top-device: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Marks this node as a JESD204 top-level device and provides a topology ID. + + jesd204-link-ids: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 32 + description: Array of link IDs for the top-level JESD204 device. + + jesd204-ignore-errors: + type: boolean + description: Ignore errors for all links in this device. + + jesd204-sysref-provider: + type: boolean + description: Marks this device as a SYSREF provider for the topology. + + jesd204-secondary-sysref-provider: + type: boolean + description: Marks this device as a secondary SYSREF provider for the topology. + + jesd204-stop-states: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 32 + description: Array of FSM state IDs where the device should stop. + + jesd204-inputs: + description: | + List of phandles with arguments describing input connections to other JESD204 devices. + Each entry must have at least 2 arguments: topology ID and link ID. + $ref: /schemas/types.yaml#/definitions/phandle-array + + "#jesd204-cells": + description: Number of cells in each jesd204-inputs phandle. + const: 2 + + jesd204-device-id: + description: JESD204 device ID (DID) + $ref: /schemas/types.yaml#/definitions/uint32 + + jesd204-bank-id: + description: JESD204 bank ID (BID) + $ref: /schemas/types.yaml#/definitions/uint32 + + jesd204-lanes-per-device: + description: Number of lanes per device (L) + $ref: /schemas/types.yaml#/definitions/uint32 + + jesd204-converters-per-device: + description: Number of converters per device (M) + $ref: /schemas/types.yaml#/definitions/uint32 + + jesd204-octets-per-frame: + description: Number of octets per frame (F) + $ref: /schemas/types.yaml#/definitions/uint32 + + jesd204-frames-per-multiframe: + description: Number of frames per multiframe (K) + $ref: /schemas/types.yaml#/definitions/uint32 + + jesd204-num-multiblocks-in-emb: + description: Number of multiblocks in extended multiblock (E) + $ref: /schemas/types.yaml#/definitions/uint32 + + jesd204-bits-per-sample: + description: Number of bits per sample (N') or (NP) + $ref: /schemas/types.yaml#/definitions/uint32 + + jesd204-converter-resolution: + description: Converter resolution in bits (N) + $ref: /schemas/types.yaml#/definitions/uint32 + + jesd204-scrambling: + description: Enable or disable scrambling (SCR) + $ref: /schemas/types.yaml#/definitions/uint32 + + jesd204-encoding: + description: JESD204 encoding type + $ref: /schemas/types.yaml#/definitions/uint32 + + jesd204-high-density: + description: High-density mode (HD) + $ref: /schemas/types.yaml#/definitions/uint32 + + jesd204-version: + description: JESD204 version (JESDV) + $ref: /schemas/types.yaml#/definitions/uint32 + + jesd204-subclass: + description: JESD204 subclass (SC) + $ref: /schemas/types.yaml#/definitions/uint32 + + jesd204-control-words-per-frame-clk: + description: Number of control words per frame clock (CF) + $ref: /schemas/types.yaml#/definitions/uint32 + + jesd204-control-bits-per-sample: + description: Number of control bits per sample (CS) + $ref: /schemas/types.yaml#/definitions/uint32 + + jesd204-samples-per-converter-per-frame: + description: Number of samples per converter per frame (S) + $ref: /schemas/types.yaml#/definitions/uint32 + + jesd204-dac-adj-resolution-steps: + description: DAC adjustment resolution steps (ADJCNT) + $ref: /schemas/types.yaml#/definitions/uint32 + + jesd204-dac-adj-direction: + description: DAC adjustment direction (ADJDIR) + $ref: /schemas/types.yaml#/definitions/uint32 + + jesd204-dac-phase-adjust: + description: DAC phase adjustment (PHADJ) + $ref: /schemas/types.yaml#/definitions/uint32 + +required: + - jesd204-device + +additionalProperties: true + +examples: + - | + jesd204_top { + compatible = "vendor,jesd204-top"; + jesd204-device; + jesd204-top-device = <0>; + jesd204-link-ids = <0 1>; + jesd204-ignore-errors; + jesd204-sysref-provider; + }; + + jesd204_dev { + compatible = "vendor,jesd204-dev"; + jesd204-device; + jesd204-inputs = <&jesd204_top 0 1>; + #jesd204-cells = <2>; + }; +... diff --git a/arch/arm64/boot/dts/xilinx/versal-vck190-reva-ad9084-204C-M4-L4-NP16-20p0-4x4.dts b/arch/arm64/boot/dts/xilinx/versal-vck190-reva-ad9084-204C-M4-L4-NP16-20p0-4x4.dts new file mode 100644 index 00000000000000..d0e89f53ff5bdf --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/versal-vck190-reva-ad9084-204C-M4-L4-NP16-20p0-4x4.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Analog Devices AD9084 RevC + * https://wiki.analog.com/resources/tools-software/linux-drivers/iio-mxfe/ad9084 + * https://wiki.analog.com/resources/eval/user-guides/ad9084_fmca_ebz/ad9084_fmca_ebz_hdl + * + * hdl_project: + * board_revision: + * + * Copyright (C) 2025 Analog Devices Inc. + */ + +#define DEVICE_PROFILE_NAME "204C_M4_L4_NP16_20p0_4x4.bin" + + +#define HMC7044_PLL2_FREQ (2500000000) // 2.5 GHz (2150...3200 MHz range) +#define AION_VCO_FREQ_HZ (2500000000) // 2.5 GHz (2375...2625 MHz range) + +#define SYSREF_CLK_MHz (9765625) + +#define WITH_AION 1 + +#include "versal-vck190-reva-ad9084.dts" diff --git a/arch/arm64/boot/dts/xilinx/versal-vck190-reva-ad9084.dts b/arch/arm64/boot/dts/xilinx/versal-vck190-reva-ad9084.dts new file mode 100644 index 00000000000000..bca6d0e7593419 --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/versal-vck190-reva-ad9084.dts @@ -0,0 +1,743 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Analog Devices AD9084-EBZ + * + * hdl_project: + * board_revision: <> + * + * Copyright (C) 2025 Analog Devices Inc. + */ +/dts-v1/; + +#include "versal-vck190-rev1.1.dts" +#include +#include +#include + +#define WITH_AXI_AION_TRIG 0 +#define WITH_FSRC 0 + +#define fmc_spi spi0 + +#ifndef DEVICE_PROFILE_NAME +#define DEVICE_PROFILE_NAME "204C_M4_L4_NP16_20p0_4x4.bin" +#endif + +#ifndef HMC7044_PLL2_FREQ +#define HMC7044_PLL2_FREQ (2500000000) // 2.5 GHz (2150...3200 MHz range) +#endif + +#define HSCI_SPEED 800 + +/* RX path */ +#define AD9084_RX_LANERATE_KHZ 20625000 +#define AD9084_RX_LINK_CLK 312500000 + +/* TX path */ +#define AD9084_TX_LANERATE_KHZ 20625000 +#define AD9084_TX_LINK_CLK 312500000 + +#if WITH_AION +#ifndef SYSREF_CLK_MHz +#define SYSREF_CLK_MHz (9765625) +#endif +#ifndef AION_VCO_FREQ_HZ +#define AION_VCO_FREQ_HZ (2500000000) // 2.5 GHz (2375...2625 MHz range) +#endif +#define JESD_SUBCLASS 1 +#else +#define JESD_SUBCLASS 0 +#endif /* WITH_AION */ + +/ { + clocks { + clkin_125: clock@0 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_125"; + }; + + ref_clk { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <33333333>; + clock-output-names = "ref_clk"; + }; + }; +}; + +&cpu_opp_table { + opp00 { + opp-hz = /bits/ 64 <1399999988>; + }; +}; + +&gic { + num_cpus = <2>; + num_interrupts = <96>; +}; + +&lpd_dma_chan0 { + status = "okay"; +}; + +&lpd_dma_chan1 { + status = "okay"; +}; + +&lpd_dma_chan2 { + status = "okay"; +}; + +&lpd_dma_chan3 { + status = "okay"; +}; + +&lpd_dma_chan4 { + status = "okay"; +}; + +&lpd_dma_chan5 { + status = "okay"; +}; + +&lpd_dma_chan6 { + status = "okay"; +}; + +&lpd_dma_chan7 { + status = "okay"; +}; + +&cci { + status = "okay"; +}; + +&smmu { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&qspi { + is-dual = <1>; + num-cs = <1>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + status = "okay"; +}; + +&sdhci1 { + clock-frequency = <199999985>; + status = "okay"; +}; + +&serial0 { + cts-override ; + device_type = "serial"; + port-number = <0>; +}; + +&spi0 { + is-decoded-cs = <0>; + num-cs = <3>; + status = "okay"; +}; + +&spi1 { + is-decoded-cs = <0>; + num-cs = <3>; + status = "okay"; +}; + +&ttc0 { + status = "okay"; +}; + +&gem0 { + local-mac-address = [00 0a 35 ad 90 81]; +}; + +&i2c1 { + eeprom@50 { + compatible = "at24,24c02"; + reg = <0x50>; + }; + ltc2977@5c { + compatible = "lltc,ltc2977"; + reg = <0x5C>; + }; + ltm4681_c23@4f { + compatible = "lltc,ltm4680"; + reg = <0x4F>; + }; + ltm4681_c01@4e { + compatible = "lltc,ltm4680"; + reg = <0x4E>; + }; +}; + +/ { + model = "Analog Devices AD9084-FMCA-EBZ (Rev. B0) @Xilinx/vck190"; + + chosen { + bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait"; + stdout-path = "serial0:115200"; + }; + + fpga_axi: fpga-axi@0 { + interrupt-parent = <&gic>; + compatible = "simple-bus"; + #address-cells = <0x1>; + #size-cells = <0x1>; + ranges = <0 0 0 0xffffffff>; + + clocks { + rx_fixed_linerate: clock@1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = ; + clock-output-names = "rx_lane_clk"; + }; + + tx_fixed_linerate: clock@2 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = ; + clock-output-names = "tx_lane_clk"; + }; + + rx_fixed_link_clk: clock@3 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = ; + clock-output-names = "rx_link_clk"; + }; + + tx_fixed_link_clk: clock@4 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = ; + clock-output-names = "tx_link_clk"; + }; + }; + + axi_gpio: gpio@a4000000 { + #gpio-cells = <2>; + #interrupt-cells = <2>; + clock-names = "s_axi_aclk"; + clocks = <&versal_clk PMC_PL0_REF>; + compatible = "xlnx,axi-gpio-2.0", "xlnx,xps-gpio-1.00.a"; + gpio-controller; + interrupt-controller; + interrupt-names = "ip2intc_irpt"; + interrupt-parent = <&gic>; + interrupts = <0 84 4>; + reg = <0xa4000000 0x1000>; + xlnx,all-inputs = <0x0>; + xlnx,all-inputs-2 = <0x0>; + xlnx,all-outputs = <0x0>; + xlnx,all-outputs-2 = <0x0>; + xlnx,dout-default = <0x00000000>; + xlnx,dout-default-2 = <0x00000000>; + xlnx,gpio-width = <0x20>; + xlnx,gpio2-width = <0x20>; + xlnx,interrupt-present = <0x1>; + xlnx,is-dual = <0x1>; + xlnx,tri-default = <0xFFFFFFFF>; + xlnx,tri-default-2 = <0xFFFFFFFF>; + }; + + rx_dma: dma@bc420000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0xbc420000 0x10000>; + #dma-cells = <1>; + #clock-cells = <0>; + interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&versal_clk PMC_PL1_REF>; + + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <2>; + adi,destination-bus-type = <0>; + }; + }; + }; + + tx_dma: dma@bc430000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0xbc430000 0x10000>; + #dma-cells = <1>; + #clock-cells = <0>; + interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&versal_clk PMC_PL1_REF>; + + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <0>; + adi,destination-bus-type = <2>; + }; + }; + }; + + axi_data_offload_tx: axi-data-offload-0@bc440000 { + compatible = "adi,axi-data-offload-1.0.a"; + reg = <0xbc440000 0x10000>; + }; + + axi_data_offload_rx: axi-data-offload-1@bc450000 { + compatible = "adi,axi-data-offload-1.0.a"; + reg = <0xbc450000 0x10000>; + }; + + hsci_clkgen: axi-clkgen@a4ad0000 { + compatible = "adi,axi-clkgen-2.00.a"; + reg = <0xa4ad0000 0x10000>; + #clock-cells = <0>; + clocks = <&versal_clk PMC_PL0_REF>, <&versal_clk PMC_PL0_REF>; + clock-names = "s_axi_aclk", "clkin1"; + clock-output-names = "hsci_clkgen"; + }; + + axi_hsci: axi_hsci@bc500000 { + compatible = "adi,axi-hsci-1.0.a"; + reg = <0xbc500000 0x40000>; + clocks = <&hsci_clkgen>; + clock-names = "pclk"; + + adi,hsci-interface-speed-mhz = ; + }; + +#if WITH_AXI_AION_TRIG + axi_aion_trig: axi_aion_trig@7c600000 { + compatible = "adi,axi-aion-trig-1.0.a"; + reg = <0x7c600000 0x1000>; + clocks = <&hmc7044 8>; + clock-names = "device_clk"; + + jesd204-device; + #jesd204-cells = <2>; + + io-channels = <&adf4030 8>; + io-channel-names = "bsync"; + }; +#endif /* WITH_AXI_AION_TRIG */ + + axi_ad9084_core_rx: axi-ad9084-rx-hpc@a4a10000 { + compatible = "adi,axi-ad9081-rx-1.0"; + reg = <0xa4a10000 0x8000>; + dmas = <&rx_dma 0>; + dma-names = "rx"; + spibus-connected = <&trx0_ad9084>; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_rx_jesd 0 FRAMER_LINK_A0_RX>; + }; + + axi_ad9084_core_tx: axi-ad9084-tx-hpc@a4b10000 { + compatible = "adi,axi-ad9081-tx-1.0"; + reg = <0xa4b10000 0x4000>; + dmas = <&tx_dma 0>; + dma-names = "tx"; + clocks = <&trx0_ad9084 1>; + clock-names = "sampl_clk"; + spibus-connected = <&trx0_ad9084>; + adi,axi-pl-fifo-enable; + adi,axi-data-offload-connected = <&axi_data_offload_tx>; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_tx_jesd 0 DEFRAMER_LINK_A0_TX>; + }; + + axi_ad9084_rx_jesd: axi-jesd204-rx@a4a90000 { + compatible = "adi,axi-jesd204-rx-1.0"; + reg = <0xa4a90000 0x1000>; + + interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&versal_clk PMC_PL0_REF>, <&hmc7044 9>, <&rx_fixed_link_clk>, <&rx_fixed_linerate>; + clock-names = "s_axi_aclk", "device_clk", "link_clk", "lane_clk"; + + #clock-cells = <0>; + clock-output-names = "jesd_rx_lane_clk"; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&hmc7044 0 FRAMER_LINK_A0_RX>; + + reset-done-gpios = <&axi_gpio 32 0>; + pll-datapath-reset-gpios = <&axi_gpio 36 0>; + datapath-reset-gpios = <&axi_gpio 38 0>; + }; + + axi_ad9084_tx_jesd: axi-jesd204-tx@a4b90000 { + compatible = "adi,axi-jesd204-tx-1.0"; + reg = <0xa4b90000 0x1000>; + + interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&versal_clk PMC_PL0_REF>, <&hmc7044 8>, <&tx_fixed_link_clk>, <&tx_fixed_linerate>; + clock-names = "s_axi_aclk", "device_clk", "link_clk", "lane_clk"; + + #clock-cells = <0>; + clock-output-names = "jesd_tx_lane_clk"; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&hmc7044 0 DEFRAMER_LINK_A0_TX>; + reset-done-gpios = <&axi_gpio 33 0>; + pll-datapath-reset-gpios = <&axi_gpio 37 0>; + datapath-reset-gpios = <&axi_gpio 39 0>; + }; + + axi_sysid_0: axi-sysid-0@a5000000 { + compatible = "adi,axi-sysid-1.00.a"; + reg = <0xa5000000 0x10000>; + }; + + axi_spi_2: spi@a4a80000 { + #address-cells = <1>; + #size-cells = <0>; + bits-per-word = <8>; + compatible = "xlnx,axi-quad-spi-3.2", "xlnx,xps-spi-2.00.a"; + fifo-size = <16>; + interrupt-names = "ip2intc_irpt"; + interrupt-parent = <&gic>; + interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>; + num-cs = <0x8>; + reg = <0xa4a80000 0x1000>; + xlnx,num-ss-bits = <0x8>; + xlnx,spi-mode = <0>; + }; + +#if WITH_FSRC + axi_fsrc_sequencer: axi-fsrc-sequencer@a4540000 { + compatible = "adi,axi-fsrc-sequencer"; + reg = <0xa4540000 0x10000>; + + trig-gpios = <&axi_gpio 26 GPIO_ACTIVE_HIGH>; // 58-32 offset + fsrc-topology = <&axi_fsrc_tx &axi_fsrc_rx>; + #io-channel-cells = <1>; + }; + + axi_fsrc_tx: axi-fsrc-sequencer@a4510000 { + reg = <0xa4510000 0x10000>; + adi,fsrc_tx; + }; + + axi_fsrc_rx: axi-fsrc-sequencer@a4500000 { + reg = <0xa4500000 0x10000>; + adi,fsrc_rx; + }; +#endif /* WITH_FSRC */ + }; +}; + + +#include +#include + +&spi0 { + status = "okay"; + + adf4382: adf4382@0 { + #clock-cells = <1>; + compatible = "adi,adf4382"; + reg = <0>; + spi-max-frequency = <5000000>; + adi,spi-3wire-enable; + clocks = <&clkin_125>; + clock-names = "ref_clk"; + clock-output-names = "adf4382_out_clk"; + adi,power-up-frequency = /bits/ 64 <20000000000>; + label = "adf4382"; + #io-channel-cells = <1>; + }; + + hmc7044: hmc7044@1 { + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + compatible = "adi,hmc7044"; + reg = <1>; + spi-max-frequency = <1000000>; + + clocks = <&clkin_125>; + clock-names = "clkin0"; + + jesd204-device; + #jesd204-cells = <2>; +#if WITH_AION + jesd204-inputs = + <&adf4030 0 FRAMER_LINK_A0_RX>, + <&adf4030 0 DEFRAMER_LINK_A0_TX>; +#endif /* WITH_AION */ + + adi,pll1-clkin-frequencies = <125000000 125000000 125000000 125000000>; + adi,vcxo-frequency = <125000000>; + + adi,pll1-loop-bandwidth-hz = <200>; + + adi,pll2-output-frequency = ; + + adi,pll1-ref-prio-ctrl = <0xE1>; /* prefer CLKIN1 -> CLKIN0 -> CLKIN2 -> CLKIN3 */ + adi,pll1-ref-autorevert-enable; + + adi,sysref-timer-divider = <1024>; + adi,pulse-generator-mode = ; + + adi,clkin0-buffer-mode = <0x07>; + adi,clkin1-buffer-mode = <0x07>; + adi,oscin-buffer-mode = <0x5>; + + adi,gpi-controls = <0x00 0x00 0x00 0x00>; + adi,gpo-controls = <0x37 0x33 0x00 0x00>; + + clock-output-names = + "hmc7044_out0", "hmc7044_out1", "hmc7044_out2", + "hmc7044_out3", "hmc7044_out4", "hmc7044_out5", + "hmc7044_out6", "hmc7044_out7", "hmc7044_out8", + "hmc7044_out9", "hmc7044_out10", "hmc7044_out11", + "hmc7044_out12", "hmc7044_out13"; + + hmc7044_c1: channel@1 { + reg = <1>; + adi,extended-name = "ADF4030_REFIN"; + adi,divider = <20>; // 125 + adi,driver-mode = ; // LVDS + }; + + hmc7044_c3: channel@3 { + reg = <3>; + adi,extended-name = "ADF4030_BSYNC0"; + adi,divider = <256>; // 9.765 + adi,driver-mode = ; // change to LVPECL + }; + + hmc7044_c8: channel@8 { + reg = <8>; + adi,extended-name = "CORE_CLK_TX"; + adi,divider = <8>; + adi,driver-mode = ; // LVDS + }; + + hmc7044_c9: channel@9 { + reg = <9>; + adi,extended-name = "CORE_CLK_RX"; + adi,divider = <8>; + adi,driver-mode = ; // LVDS + }; + + hmc7044_c10: channel@10 { + reg = <10>; + adi,extended-name = "FPGA_REFCLK"; + adi,divider = <8>; + adi,driver-mode = ; // LVDS + }; + + hmc7044_c11: channel@11 { + reg = <11>; + adi,extended-name = "CORE_CLK_RX_B"; + adi,divider = <8>; + adi,driver-mode = ; // LVDS + }; + + hmc7044_c12: channel@12 { + reg = <12>; + adi,extended-name = "CORE_CLK_TX_B"; + adi,divider = <8>; + adi,driver-mode = ; // LVDS + }; + }; + +#if WITH_AION + adf4030: adf4030@2 { + #clock-cells = <1>; + compatible = "adi,adf4030"; + reg = <2>; + + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + spi-max-frequency = <1000000>; + adi,spi-3wire-enable; + clocks = <&hmc7044 1>; + clock-names = "refin"; + clock-output-names = "adf4030_bsync_0", "adf4030_bsync_1", + "adf4030_bsync_2", "adf4030_bsync_3", "adf4030_bsync_4", + "adf4030_bsync_5", "adf4030_bsync_6", "adf4030_bsync_7", + "adf4030_bsync_8", "adf4030_bsync_9"; + label = "adf4030"; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-sysref-provider; + +#if WITH_AXI_AION_TRIG + jesd204-inputs = + <&axi_aion_trig 0 FRAMER_LINK_A0_RX>, + <&axi_aion_trig 0 DEFRAMER_LINK_A0_TX>; +#endif /* WITH_AXI_AION_TRIG */ + + adi,jesd204-max-sysref-frequency-hz = <2000000>; + + adi,vco-frequency-hz = ; /* 2.5 GHz */ + adi,bsync-frequency-hz = ; + adi,bsync-autoalign-reference-channel = <0>; /* LTC6952_OUT_6 */ + adi,bsync-autoalign-iteration-count = <6>; + adi,bsync-secondary-frequency-hz = <12500000>; /* 12.5 MHz */ + + channel@0 { + /* hmc output */ + reg = <0>; + adi,extended-name = "ADF4030_SCLKOUT3"; + auto-align-on-sync-en; + adi,rcm = <1>; + adi,link-rx-en; + adi,float-rx-en; + }; + channel@1 { + /* Output debug loopback */ + reg = <1>; + adi,extended-name = "BSYNC1_DEBUG"; + //auto-align-on-sync-en; + adi,input-output-reconfig-en; + adi,rcm = <62>; // LVDS + adi,link-rx-en; + adi,float-rx-en; + adi,output-en; + }; + channel@2 { + /* Input debug loopback */ + reg = <2>; + adi,extended-name = "BSYNC2_DEBUG"; + //auto-align-on-sync-en; + adi,input-output-reconfig-en; + adi,rcm = <62>; + adi,link-rx-en; + adi,float-rx-en; + }; + channel@5 { + /* apollo input */ + reg = <5>; + adi,extended-name = "APOLLO_SYSREF"; + auto-align-on-sync-en; + adi,output-en; + adi,input-output-reconfig-en; + adi,rcm = <1>; + adi,link-rx-en; + adi,float-rx-en; + }; + channel@8 { + /* fpga sysref_in_p/n input */ + reg = <8>; + adi,extended-name = "SYSREF_IN_F"; + auto-align-on-sync-en; + adi,output-en; + adi,link-rx-en; + adi,float-rx-en; + adi,input-output-reconfig-en; + }; + channel@9 { + /* Unused, connects to nothing */ + reg = <9>; + adi,extended-name = "SYSREF_OUT_FMC"; + adi,output-en; + //auto-align-on-sync-en; + adi,input-output-reconfig-en; + adi,rcm = <62>; + }; + }; +#endif /* WITH_AION */ +}; + +&axi_spi_2 { + trx0_ad9084: ad9084@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "adi,ad9084"; + reg = <0>; + spi-max-frequency = <13000000>; + + /* Clocks */ + clocks = <&adf4382 0>; + clock-names = "dev_clk"; + dev_clk-clock-scales = <1 10>; + + clock-output-names = "rx_sampl_clk", "tx_sampl_clk"; + #clock-cells = <1>; + + + /* FFT sniffer GPIO exports and corresponding interrupts */ + // interrupt-names = "fft_done_A", "fft_done_B"; + // interrupt-parent = <&axi_gpio>; + // interrupts = <2 1 3 1>; + //adi,gpio-sniffer-a-export = <17>; + //adi,gpio-sniffer-b-export = <18>; + + adi,axi-hsci-connected = <&axi_hsci>; + + adi,hsci-auto-linkup-mode-en; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-top-device = <0>; /* This is the TOP device */ + jesd204-ignore-errors; + jesd204-link-ids = ; + + jesd204-inputs = + <&axi_ad9084_core_rx 0 FRAMER_LINK_A0_RX>, + <&axi_ad9084_core_tx 0 DEFRAMER_LINK_A0_TX>; + + reset-gpios = <&axi_gpio 30 0>; + //adi,gpio-exports = /bits/ 8 <15 16 17 18 19 20 21 22 23>; // + +#if WITH_AION +#if WITH_FSRC + io-channels = <&adf4030 5>, <&adf4382 0>, <&axi_fsrc_sequencer 0>; + io-channel-names = "bsync", "clk", "fsrc"; +#else + io-channels = <&adf4030 5>, <&adf4382 0>; + io-channel-names = "bsync", "clk"; +#endif /* WITH_FSRC */ +#else +#if WITH_FSRC + io-channels = <&axi_fsrc_sequencer 0>; + io-channel-names = "fsrc"; +#endif +#endif /* WITH_AION */ + + adi,device-profile-fw-name = DEVICE_PROFILE_NAME; + + adi,jrx0-physical-lane-mapping = <5 1 3 7 11 11 11 11 11 11 11 11>; + adi,jtx0-logical-lane-mapping = <11 11 11 1 11 11 11 11 2 3 11 0>; + + adi,jrx1-physical-lane-mapping = <1 7 10 3 5 8 9 11 11 11 11 11>; + adi,jtx1-logical-lane-mapping = <11 5 1 0 11 2 11 3 4 7 11 6>; + + adi,subclass = ; + + adi,invalid-en; + + // adi,cddc-bmem-sample-delay-en; + // adi,fddc-bmem-sample-delay-en; + + /* GPIO frequency hopping configuration (optional) */ + //adi,gpio-hop-profile = <19 20 21 22 23>; + //adi,gpio-hop-block = <15 16 17 18>; + }; +}; diff --git a/arch/arm64/boot/dts/xilinx/versal-vpk180-reva-ad9084-204C-M4-L1-NP16-20p0-16x4.dts b/arch/arm64/boot/dts/xilinx/versal-vpk180-reva-ad9084-204C-M4-L1-NP16-20p0-16x4.dts new file mode 100644 index 00000000000000..5d0f6238d5998f --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/versal-vpk180-reva-ad9084-204C-M4-L1-NP16-20p0-16x4.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Analog Devices AD9084 RevC + * https://wiki.analog.com/resources/tools-software/linux-drivers/iio-mxfe/ad9084 + * https://wiki.analog.com/resources/eval/user-guides/ad9084_fmca_ebz/ad9084_fmca_ebz_hdl + * + * hdl_project: + * board_revision: + * + * Copyright (C) 2025 Analog Devices Inc. + */ + +#define DEVICE_PROFILE_NAME "204C_M4_L1_NP16_20p0_16x4.bin" + +#include "versal-vpk180-reva-ad9084.dts" diff --git a/arch/arm64/boot/dts/xilinx/versal-vpk180-reva-ad9084.dts b/arch/arm64/boot/dts/xilinx/versal-vpk180-reva-ad9084.dts new file mode 100644 index 00000000000000..343628f3157e3a --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/versal-vpk180-reva-ad9084.dts @@ -0,0 +1,700 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Analog Devices AD9084-EBZ + * + * hdl_project: + * board_revision: <> + * + * Copyright (C) 2026 Analog Devices Inc. + */ +/dts-v1/; + +#include "versal-vpk180-revA.dts" +#include +#include +#include + +#define WITH_AION 1 +#define WITH_AXI_AION_TRIG 0 + +#define fmc_spi spi0 + +#ifndef DEVICE_PROFILE_NAME +#define DEVICE_PROFILE_NAME "204C_M4_L4_NP16_20p0_4x4.bin" +#endif + +/* RX path */ +#define AD9084_RX_LANERATE_KHZ 20625000 +#define AD9084_RX_LINK_CLK 312500000 + +/* TX path */ +#define AD9084_TX_LANERATE_KHZ 20625000 +#define AD9084_TX_LINK_CLK 312500000 + +#ifndef SYSREF_CLK_MHz +#define SYSREF_CLK_MHz (9765625) +#endif + +#if WITH_AION +#define JESD_SUBCLASS 1 +#else +#define JESD_SUBCLASS 0 +#endif /* WITH_AION */ + +/ { + clocks { + clkin_125: clock@0 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_125"; + }; + }; +}; + +&gic { + num_cpus = <2>; + num_interrupts = <96>; +}; + +&lpd_dma_chan0 { + status = "okay"; +}; + +&lpd_dma_chan1 { + status = "okay"; +}; + +&lpd_dma_chan2 { + status = "okay"; +}; + +&lpd_dma_chan3 { + status = "okay"; +}; + +&lpd_dma_chan4 { + status = "okay"; +}; + +&lpd_dma_chan5 { + status = "okay"; +}; + +&lpd_dma_chan6 { + status = "okay"; +}; + +&lpd_dma_chan7 { + status = "okay"; +}; + +&cci { + status = "okay"; +}; + +&smmu { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&qspi { + is-dual = <1>; + num-cs = <1>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + status = "okay"; +}; + +&sdhci1 { + clock-frequency = <199999985>; + status = "okay"; +}; + +// &sysmon { +// #address-cells = <1>; +// #size-cells = <0>; +// xlnx,numchannels = /bits/8 <0>; +// }; + +&serial0 { + cts-override ; + device_type = "serial"; + port-number = <0>; +}; + +&spi0 { + is-decoded-cs = <0>; + num-cs = <3>; + status = "okay"; +}; + +&spi1 { + is-decoded-cs = <0>; + num-cs = <3>; + status = "okay"; +}; + +&ttc0 { + status = "okay"; +}; + +&ref { + clock-frequency = <33333333>; +}; + +&gem0 { + local-mac-address = [00 0a 35 ad 90 81]; +}; + +&i2c1 { + eeprom@50 { + compatible = "at24,24c02"; + reg = <0x50>; + }; + ltc2977@5c { + compatible = "lltc,ltc2977"; + reg = <0x5C>; + }; + ltm4681_c23@4f { + compatible = "lltc,ltm4680"; + reg = <0x4F>; + }; + ltm4681_c01@4e { + compatible = "lltc,ltm4680"; + reg = <0x4E>; + }; +}; + +/ { + model = "Analog Devices AD9084-FMCA-EBZ (Rev. B0) @Xilinx/vpk180"; + + chosen { + bootargs = "console=ttyAMA0 earlycon=pl011,mmio32,0xFF000000,115200n8 clk_ignore_unused root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait"; + stdout-path = "serial0:115200"; + }; + + fpga_axi: fpga-axi@0 { + interrupt-parent = <&gic>; + compatible = "simple-bus"; + #address-cells = <0x1>; + #size-cells = <0x1>; + ranges = <0 0 0 0xffffffff>; + + clocks { + rx_fixed_linerate: clock@1 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = ; + clock-output-names = "rx_lane_clk"; + }; + + tx_fixed_linerate: clock@2 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = ; + clock-output-names = "tx_lane_clk"; + }; + + rx_fixed_link_clk: clock@3 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = ; + clock-output-names = "rx_link_clk"; + }; + + tx_fixed_link_clk: clock@4 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = ; + clock-output-names = "tx_link_clk"; + }; +}; + + axi_gpio: gpio@a4000000 { + #gpio-cells = <2>; + #interrupt-cells = <2>; + clock-names = "s_axi_aclk"; + clocks = <&versal_clk PMC_PL0_REF>; + compatible = "xlnx,axi-gpio-2.0", "xlnx,xps-gpio-1.00.a"; + gpio-controller; + interrupt-controller; + interrupt-names = "ip2intc_irpt"; + interrupt-parent = <&gic>; + interrupts = <0 84 4>; + reg = <0xa4000000 0x1000>; + xlnx,all-inputs = <0x0>; + xlnx,all-inputs-2 = <0x0>; + xlnx,all-outputs = <0x0>; + xlnx,all-outputs-2 = <0x0>; + xlnx,dout-default = <0x00000000>; + xlnx,dout-default-2 = <0x00000000>; + xlnx,gpio-width = <0x20>; + xlnx,gpio2-width = <0x20>; + xlnx,interrupt-present = <0x1>; + xlnx,is-dual = <0x1>; + xlnx,tri-default = <0xFFFFFFFF>; + xlnx,tri-default-2 = <0xFFFFFFFF>; + }; + + rx_dma: dma@bc420000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0xbc420000 0x10000>; + #dma-cells = <1>; + #clock-cells = <0>; + interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&versal_clk PMC_PL1_REF>; + + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <2>; + adi,destination-bus-type = <0>; + }; + }; + }; + + tx_dma: dma@bc430000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0xbc430000 0x10000>; + #dma-cells = <1>; + #clock-cells = <0>; + interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&versal_clk PMC_PL1_REF>; + + adi,channels { + #size-cells = <0>; + #address-cells = <1>; + + dma-channel@0 { + reg = <0>; + adi,source-bus-type = <0>; + adi,destination-bus-type = <2>; + }; + }; + }; + + axi_data_offload_tx: axi-data-offload-0@bc440000 { + compatible = "adi,axi-data-offload-1.0.a"; + reg = <0xbc440000 0x10000>; + }; + + axi_data_offload_rx: axi-data-offload-1@bc450000 { + compatible = "adi,axi-data-offload-1.0.a"; + reg = <0xbc450000 0x10000>; + }; + + hsci_clkgen: axi-clkgen@a4ad0000 { + compatible = "adi,axi-clkgen-2.00.a"; + reg = <0xa4ad0000 0x10000>; + #clock-cells = <0>; + clocks = <&versal_clk PMC_PL0_REF>, <&versal_clk PMC_PL0_REF>; + clock-names = "s_axi_aclk", "clkin1"; + clock-output-names = "hsci_clkgen"; + }; + + axi_hsci: axi_hsci@bc500000 { + compatible = "adi,axi-hsci-1.0.a"; + reg = <0xbc500000 0x40000>; + clocks = <&hsci_clkgen>; + clock-names = "pclk"; + + adi,hsci-interface-speed-mhz = <800>; + }; + +#if WITH_AXI_AION_TRIG + axi_aion_trig: axi_aion_trig@bc600000 { + compatible = "adi,axi-aion-trig-1.0.a"; + reg = <0xbc600000 0x1000>; + clocks = <&hmc7044 8>; + clock-names = "device_clk"; + + jesd204-device; + #jesd204-cells = <2>; + + io-channels = <&adf4030 8>; + io-channel-names = "bsync"; + }; +#endif /* WITH_AXI_AION_TRIG */ + + axi_ad9084_core_rx: axi-ad9084-rx-hpc@a4a10000 { + compatible = "adi,axi-ad9081-rx-1.0"; + reg = <0xa4a10000 0x8000>; + dmas = <&rx_dma 0>; + dma-names = "rx"; + spibus-connected = <&trx0_ad9084>; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_rx_jesd 0 FRAMER_LINK_A0_RX>; + }; + + axi_ad9084_core_tx: axi-ad9084-tx-hpc@a4b10000 { + compatible = "adi,axi-ad9081-tx-1.0"; + reg = <0xa4b10000 0x4000>; + dmas = <&tx_dma 0>; + dma-names = "tx"; + clocks = <&trx0_ad9084 1>; + clock-names = "sampl_clk"; + spibus-connected = <&trx0_ad9084>; + adi,axi-pl-fifo-enable; + adi,axi-data-offload-connected = <&axi_data_offload_tx>; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_tx_jesd 0 DEFRAMER_LINK_A0_TX>; + }; + + axi_ad9084_rx_jesd: axi-jesd204-rx@a4a90000 { + compatible = "adi,axi-jesd204-rx-1.0"; + reg = <0xa4a90000 0x1000>; + + interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&versal_clk PMC_PL0_REF>, <&hmc7044 9>, <&rx_fixed_link_clk>, <&rx_fixed_linerate>; + clock-names = "s_axi_aclk", "device_clk", "link_clk", "lane_clk"; + + #clock-cells = <0>; + clock-output-names = "jesd_rx_lane_clk"; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&hmc7044 0 FRAMER_LINK_A0_RX>; + + reset-done-gpios = <&axi_gpio 32 0>; + pll-datapath-reset-gpios = <&axi_gpio 36 0>; + datapath-reset-gpios = <&axi_gpio 38 0>; + }; + + axi_ad9084_tx_jesd: axi-jesd204-tx@a4b90000 { + compatible = "adi,axi-jesd204-tx-1.0"; + reg = <0xa4b90000 0x1000>; + + interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&versal_clk PMC_PL0_REF>, <&hmc7044 8>, <&tx_fixed_link_clk>, <&tx_fixed_linerate>; + clock-names = "s_axi_aclk", "device_clk", "link_clk", "lane_clk"; + + #clock-cells = <0>; + clock-output-names = "jesd_tx_lane_clk"; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&hmc7044 0 DEFRAMER_LINK_A0_TX>; + + reset-done-gpios = <&axi_gpio 33 0>; + pll-datapath-reset-gpios = <&axi_gpio 37 0>; + datapath-reset-gpios = <&axi_gpio 39 0>; + }; + + axi_sysid_0: axi-sysid-0@a5000000 { + compatible = "adi,axi-sysid-1.00.a"; + reg = <0xa5000000 0x10000>; + }; + + axi_spi_2: spi@a4a80000 { + #address-cells = <1>; + #size-cells = <0>; + bits-per-word = <8>; + compatible = "xlnx,axi-quad-spi-3.2", "xlnx,xps-spi-2.00.a"; + fifo-size = <16>; + interrupt-names = "ip2intc_irpt"; + interrupt-parent = <&gic>; + interrupts = <0 93 IRQ_TYPE_LEVEL_HIGH>; + num-cs = <0x8>; + reg = <0xa4a80000 0x1000>; + xlnx,num-ss-bits = <0x8>; + xlnx,spi-mode = <0>; + }; + }; +}; + + +#include +#include + +&spi0 { + status = "okay"; + + hmc7044: hmc7044@1 { + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + compatible = "adi,hmc7044"; + reg = <1>; + spi-max-frequency = <1000000>; + + jesd204-device; + #jesd204-cells = <2>; +#if WITH_AION + jesd204-inputs = + <&adf4030 0 FRAMER_LINK_A0_RX>, + <&adf4030 0 DEFRAMER_LINK_A0_TX>; +#endif /* WITH_AION */ + // jesd204-sysref-provider; + + //adi,clkin1-vco-in-enable; + + clocks = <&clkin_125>; + clock-names = "clkin0"; + + adi,jesd204-max-sysref-frequency-hz = <2000000>; + + adi,pll1-clkin-frequencies = <125000000 125000000 125000000 125000000>; + adi,vcxo-frequency = <125000000>; + + adi,pll1-loop-bandwidth-hz = <200>; + + adi,pll2-output-frequency = <2500000000>; + + adi,pll1-ref-prio-ctrl = <0xE1>; /* prefer CLKIN1 -> CLKIN0 -> CLKIN2 -> CLKIN3 */ + adi,pll1-ref-autorevert-enable; + + adi,sysref-timer-divider = <1024>; + adi,pulse-generator-mode = ; + + adi,clkin0-buffer-mode = <0x07>; + adi,clkin1-buffer-mode = <0x07>; + adi,oscin-buffer-mode = <0x5>; + + adi,gpi-controls = <0x00 0x00 0x00 0x00>; + adi,gpo-controls = <0x37 0x33 0x00 0x00>; + + clock-output-names = + "hmc7044_out0", "hmc7044_out1", "hmc7044_out2", + "hmc7044_out3", "hmc7044_out4", "hmc7044_out5", + "hmc7044_out6", "hmc7044_out7", "hmc7044_out8", + "hmc7044_out9", "hmc7044_out10", "hmc7044_out11", + "hmc7044_out12", "hmc7044_out13"; + + hmc7044_c1: channel@1 { + reg = <1>; + adi,extended-name = "ADF4030_REFIN"; + adi,divider = <20>; // 125 + adi,driver-mode = ; // LVDS + }; + + hmc7044_c3: channel@3 { + reg = <3>; + adi,extended-name = "ADF4030_BSYNC0"; + adi,divider = <256>; // 9.765 + adi,driver-mode = ; // change to LVPECL + }; + + hmc7044_c8: channel@8 { + reg = <8>; + adi,extended-name = "CORE_CLK_TX"; + adi,divider = <8>; + adi,driver-mode = ; // LVDS + }; + + hmc7044_c9: channel@9 { + reg = <9>; + adi,extended-name = "CORE_CLK_RX"; + adi,divider = <8>; + adi,driver-mode = ; // LVDS + }; + + hmc7044_c10: channel@10 { + reg = <10>; + adi,extended-name = "FPGA_REFCLK"; + adi,divider = <8>; + adi,driver-mode = ; // LVDS + }; + + hmc7044_c11: channel@11 { + reg = <11>; + adi,extended-name = "CORE_CLK_RX_B"; + adi,divider = <8>; + adi,driver-mode = ; // LVDS + }; + + hmc7044_c12: channel@12 { + reg = <12>; + adi,extended-name = "CORE_CLK_TX_B"; + adi,divider = <8>; + adi,driver-mode = ; // LVDS + }; + }; + +#if WITH_AION + adf4030: adf4030@2 { + #clock-cells = <1>; + compatible = "adi,adf4030"; + reg = <2>; + + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + spi-max-frequency = <1000000>; + adi,spi-3wire-enable; + clocks = <&hmc7044 1>; + clock-names = "refin"; + clock-output-names = "adf4030_bsync_0", "adf4030_bsync_1", + "adf4030_bsync_2", "adf4030_bsync_3", "adf4030_bsync_4", + "adf4030_bsync_5", "adf4030_bsync_6", "adf4030_bsync_7", + "adf4030_bsync_8", "adf4030_bsync_9"; + label = "adf4030"; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-sysref-provider; + +#if WITH_AXI_AION_TRIG + jesd204-inputs = + <&axi_aion_trig 0 FRAMER_LINK_A0_RX>, + <&axi_aion_trig 0 DEFRAMER_LINK_A0_TX>; +#endif /* WITH_AXI_AION_TRIG */ + + adi,jesd204-max-sysref-frequency-hz = <2000000>; + + adi,vco-frequency-hz = <2500000000>; /* 2.5 GHz */ + adi,bsync-frequency-hz = ; + adi,bsync-autoalign-reference-channel = <0>; /* LTC6952_OUT_6 */ + adi,bsync-autoalign-iteration-count = <6>; + adi,bsync-secondary-frequency-hz = <12500000>; /* 12.5 MHz */ + + channel@0 { + /* hmc output */ + reg = <0>; + adi,extended-name = "ADF4030_SCLKOUT3"; + auto-align-on-sync-en; + adi,rcm = <1>; + adi,link-rx-en; + adi,float-rx-en; + }; + channel@1 { + /* Output debug loopback */ + reg = <1>; + adi,extended-name = "BSYNC1_DEBUG"; + // auto-align-on-sync-en; + adi,input-output-reconfig-en; + adi,rcm = <62>; // LVDS + adi,link-rx-en; + adi,float-rx-en; + adi,output-en; + }; + channel@2 { + /* Input debug loopback */ + reg = <2>; + adi,extended-name = "BSYNC2_DEBUG"; + // auto-align-on-sync-en; + adi,input-output-reconfig-en; + adi,rcm = <62>; + adi,link-rx-en; + adi,float-rx-en; + }; + channel@5 { + /* apollo input */ + reg = <5>; + adi,extended-name = "APOLLO_SYSREF"; + auto-align-on-sync-en; + adi,output-en; + adi,input-output-reconfig-en; + adi,rcm = <1>; + adi,link-rx-en; + adi,float-rx-en; + }; + channel@8 { + /* fpga sysref_in_p/n input */ + reg = <8>; + adi,extended-name = "SYSREF_IN_F"; + auto-align-on-sync-en; + adi,output-en; + adi,link-rx-en; + adi,float-rx-en; + adi,input-output-reconfig-en; + }; + channel@9 { + /* Unused, connects to nothing */ + reg = <9>; + adi,extended-name = "SYSREF_OUT_FMC"; + adi,output-en; + // auto-align-on-sync-en; + adi,input-output-reconfig-en; + adi,rcm = <62>; + }; + }; +#endif /* WITH_AION */ + + adf4382: adf4382@0 { + #clock-cells = <1>; + compatible = "adi,adf4382"; + reg = <0>; + spi-max-frequency = <5000000>; + adi,spi-3wire-enable; + clocks = <&clkin_125>; + clock-names = "ref_clk"; + clock-output-names = "adf4382_out_clk"; + adi,power-up-frequency = /bits/ 64 <20000000000>; + label = "adf4382"; + #io-channel-cells = <1>; + }; +}; + +&axi_spi_2 { + trx0_ad9084: ad9084@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "adi,ad9084"; + reg = <0>; + spi-max-frequency = <13000000>; + + /* Clocks */ + clocks = <&adf4382 0>; + clock-names = "dev_clk"; + dev_clk-clock-scales = <1 10>; + + clock-output-names = "rx_sampl_clk", "tx_sampl_clk"; + #clock-cells = <1>; + + adi,axi-hsci-connected = <&axi_hsci>; + // adi,hsci-rx-clk-invert-en; + // adi,hsci-rx-clk-adj = <8>; + // //adi,hsci-tx-clk-invert-en; + // adi,hsci-tx-clk-adj = <9>; + + adi,hsci-auto-linkup-mode-en; + // adi,hsci-disable-after-boot-en; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-top-device = <0>; /* This is the TOP device */ + jesd204-ignore-errors; + jesd204-link-ids = ; + + jesd204-inputs = + <&axi_ad9084_core_rx 0 FRAMER_LINK_A0_RX>, + <&axi_ad9084_core_tx 0 DEFRAMER_LINK_A0_TX>; + reset-gpios = <&axi_gpio 30 0>; + adi,gpio-exports = /bits/ 8 <15 16 17 18 19 20 21 22 23>; // + +#if WITH_AION + io-channels = <&adf4030 5>, <&adf4382 0>; + io-channel-names = "bsync", "clk"; +#endif /* WITH_AION */ + + adi,device-profile-fw-name = DEVICE_PROFILE_NAME; + + adi,jrx0-physical-lane-mapping = <5 1 3 7 11 11 11 11 11 11 11 11>; + adi,jtx0-logical-lane-mapping = <11 11 11 1 11 11 11 11 2 3 11 0>; + + adi,jrx1-physical-lane-mapping = <1 7 10 3 11 11 11 11 11 11 11 11>; + adi,jtx1-logical-lane-mapping = <11 11 1 0 11 2 11 3 11 11 11 11>; + + adi,jtx-ser-amplitude = <0>; + adi,jtx-ser-pre-emphasis = <2>; + adi,jtx-ser-post-emphasis = <1>; + + adi,subclass = ; + + adi,invalid-en; + }; +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/xilinx/vu11p-ad9084-vpx-nyx.dtso b/arch/arm64/boot/dts/xilinx/vu11p-ad9084-vpx-nyx.dtso new file mode 100644 index 00000000000000..b6002e8f2ebf3b --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/vu11p-ad9084-vpx-nyx.dtso @@ -0,0 +1,428 @@ +/dts-v1/; +/plugin/; + +#include "vu11p-ad9084-vpx-revb.dtso" + +&rfpc_one_bit_adc_dac { + status = "okay"; + label = "nyx_controls"; + + out-gpios = <&axi_gpio_1 33 0>, <&axi_gpio_1 34 0>, + <&axi_gpio_1 35 0>, <&axi_gpio_1 36 0>, + <&axi_gpio_1 37 0>, <&axi_gpio_1 38 0>, + <&axi_gpio_1 39 0>, <&axi_gpio_1 40 0>, + <&axi_gpio_1 41 0>, <&axi_gpio_1 42 0>, + <&axi_gpio_1 43 0>, <&axi_gpio_1 44 0>, + <&axi_gpio_1 45 0>, <&axi_gpio_1 46 0>, + <&axi_gpio_1 47 0>, <&axi_gpio_1 48 0>, + <&axi_gpio_1 49 0>, <&axi_gpio_1 50 0>, + <&axi_gpio_1 51 0>, <&axi_gpio_1 52 0>, + <&axi_gpio_1 53 0>, <&axi_gpio_1 54 0>, + <&axi_gpio_1 55 0>, <&axi_gpio_1 56 0>, + <&axi_gpio_1 57 0>, <&axi_gpio_1 58 0>, + <&axi_gpio_1 59 0>, <&axi_gpio_1 60 0>, + <&axi_gpio_1 61 0>, <&axi_gpio_1 62 0>, + <&axi_gpio_1 63 0>, <&axi_gpio_2 0 0>, + <&axi_gpio_2 1 0>, <&axi_gpio_2 2 0>, + <&axi_gpio_2 3 0>, <&axi_gpio_2 4 0>, + <&axi_gpio_2 5 0>, <&axi_gpio_2 6 0>, + <&axi_gpio_2 7 0>, <&axi_gpio_2 8 0>, + <&axi_gpio_2 9 0>, <&axi_gpio_2 10 0>, + <&axi_gpio_2 11 0>, <&axi_gpio_2 12 0>, + <&axi_gpio_2 13 0>, <&axi_gpio_2 14 0>, + <&axi_gpio_2 15 0>, <&axi_gpio_2 16 0>, + <&axi_gpio_2 17 0>, <&axi_gpio_2 18 0>, + <&axi_gpio_2 19 0>, <&axi_gpio_2 20 0>, + <&axi_gpio_2 21 0>, <&axi_gpio_2 22 0>, + <&axi_gpio_2 23 0>, <&axi_gpio_2 24 0>, + <&axi_gpio_2 25 0>, <&axi_gpio_2 26 0>, + <&axi_gpio_2 27 0>, <&axi_gpio_2 28 0>, + <&axi_gpio_2 29 0>, <&axi_gpio_2 30 0>, + <&axi_gpio_2 31 0>, <&axi_gpio_2 32 0>, + <&axi_gpio_2 33 0>, <&axi_gpio_2 34 0>, + <&axi_gpio_2 35 0>, <&axi_gpio_2 36 0>, + <&axi_gpio_2 37 0>, <&axi_gpio_2 38 0>, + <&axi_gpio_2 39 0>, <&axi_gpio_2 40 0>, + <&axi_gpio_2 41 0>, <&axi_gpio_2 42 0>, + <&axi_gpio_2 43 0>, <&axi_gpio_2 44 0>; + + channel@0 { + reg = <0>; + label = "tx3_filter_ctrl_0"; //axi_gpio_1 33 + }; + + channel@1 { + reg = <1>; + label = "tx3_filter_ctrl_1"; //axi_gpio_1 34 + }; + + channel@2 { + reg = <2>; + label = "tx2_filter_ctrl_0"; //axi_gpio_1 35 + }; + + channel@3 { + reg = <3>; + label = "tx2_filter_ctrl_1"; //axi_gpio_1 36 + }; + + channel@4 { + reg = <4>; + label = "tx1_filter_ctrl_0"; //axi_gpio_1 37 + }; + + channel@5 { + reg = <5>; + label = "tx1_filter_ctrl_1"; //axi_gpio_1 38 + }; + + channel@6 { + reg = <6>; + label = "tx0_filter_ctrl_0"; //axi_gpio_1 39 + }; + + channel@7 { + reg = <7>; + label = "tx0_filter_ctrl_1"; //axi_gpio_1 40 + }; + + channel@8 { + reg = <8>; + label = "rx3_filter_ctrl_0"; //axi_gpio_1 41 + }; + + channel@9 { + reg = <9>; + label = "rx3_filter_ctrl_1"; //axi_gpio_1 42 + }; + + channel@10 { + reg = <10>; + label = "rx2_filter_ctrl_0"; //axi_gpio_1 43 + }; + + channel@11 { + reg = <11>; + label = "rx2_filter_ctrl_1"; //axi_gpio_1 44 + }; + + channel@12 { + reg = <12>; + label = "rx1_filter_ctrl_0"; //axi_gpio_1 45 + }; + + channel@13 { + reg = <13>; + label = "rx1_filter_ctrl_1"; //axi_gpio_1 46 + }; + + channel@14 { + reg = <14>; + label = "rx0_filter_ctrl_0"; //axi_gpio_1 47 + }; + + channel@15 { + reg = <15>; + label = "rx0_filter_ctrl_1"; //axi_gpio_1 48 + }; + + channel@16 { + reg = <16>; + label = "tx0_dsa_0"; //axi_gpio_1 49 + }; + + channel@17 { + reg = <17>; + label = "tx0_dsa_1"; //axi_gpio_1 50 + }; + + channel@18 { + reg = <18>; + label = "tx0_dsa_2"; //axi_gpio_1 51 + }; + + channel@19 { + reg = <19>; + label = "tx0_dsa_3"; //axi_gpio_1 52 + }; + + channel@20 { + reg = <20>; + label = "tx0_dsa_4"; //axi_gpio_1 53 + }; + + channel@21 { + reg = <21>; + label = "tx0_dsa_5"; //axi_gpio_1 54 + }; + + channel@22 { + reg = <22>; + label = "tx1_dsa_0"; //axi_gpio_1 55 + }; + + channel@23 { + reg = <23>; + label = "tx1_dsa_1"; //axi_gpio_1 56 + }; + + channel@24 { + reg = <24>; + label = "tx1_dsa_2"; //axi_gpio_1 57 + }; + + channel@25 { + reg = <25>; + label = "tx1_dsa_3"; //axi_gpio_1 58 + }; + + channel@26 { + reg = <26>; + label = "tx1_dsa_4"; //axi_gpio_1 59 + }; + + channel@27 { + reg = <27>; + label = "tx1_dsa_5"; //axi_gpio_1 60 + }; + + channel@28 { + reg = <28>; + label = "tx2_dsa_0"; //axi_gpio_1 61 + }; + + channel@29 { + reg = <29>; + label = "tx2_dsa_1"; //axi_gpio_1 62 + }; + + channel@30 { + reg = <30>; + label = "tx2_dsa_2"; //axi_gpio_1 63 + }; + + channel@31 { + reg = <31>; + label = "tx2_dsa_3"; //axi_gpio_2 0 + }; + + channel@32 { + reg = <32>; + label = "tx2_dsa_4"; //axi_gpio_2 1 + }; + + channel@33 { + reg = <33>; + label = "tx2_dsa_5"; //axi_gpio_2 2 + }; + + channel@34 { + reg = <34>; + label = "tx3_dsa_0"; //axi_gpio_2 3 + }; + + channel@35 { + reg = <35>; + label = "tx3_dsa_1"; //axi_gpio_2 4 + }; + + channel@36 { + reg = <36>; + label = "tx3_dsa_2"; //axi_gpio_2 5 + }; + + channel@37 { + reg = <37>; + label = "tx3_dsa_3"; //axi_gpio_2 6 + }; + + channel@38 { + reg = <38>; + label = "tx3_dsa_4"; //axi_gpio_2 7 + }; + + channel@39 { + reg = <39>; + label = "tx3_dsa_5"; //axi_gpio_2 8 + }; + + channel@40 { + reg = <40>; + label = "rx0_dsa_0"; //axi_gpio_2 9 + }; + + channel@41 { + reg = <41>; + label = "rx0_dsa_1"; //axi_gpio_2 10 + }; + + channel@42 { + reg = <42>; + label = "rx0_dsa_2"; //axi_gpio_2 11 + }; + + channel@43 { + reg = <43>; + label = "rx0_dsa_3"; //axi_gpio_2 12 + }; + + channel@44 { + reg = <44>; + label = "rx0_dsa_4"; //axi_gpio_2 13 + }; + + channel@45 { + reg = <45>; + label = "rx0_dsa_5"; //axi_gpio_2 14 + }; + + channel@46 { + reg = <46>; + label = "rx1_dsa_0"; //axi_gpio_2 15 + }; + + channel@47 { + reg = <47>; + label = "rx1_dsa_1"; //axi_gpio_2 16 + }; + + channel@48 { + reg = <48>; + label = "rx1_dsa_2"; //axi_gpio_2 17 + }; + + channel@49 { + reg = <49>; + label = "rx1_dsa_3"; //axi_gpio_2 18 + }; + + channel@50 { + reg = <50>; + label = "rx1_dsa_4"; //axi_gpio_2 19 + }; + + channel@51 { + reg = <51>; + label = "rx1_dsa_5"; //axi_gpio_2 20 + }; + + channel@52 { + reg = <52>; + label = "rx2_dsa_0"; //axi_gpio_2 21 + }; + + channel@53 { + reg = <53>; + label = "rx2_dsa_1"; //axi_gpio_2 22 + }; + + channel@54 { + reg = <54>; + label = "rx2_dsa_2"; //axi_gpio_2 23 + }; + + channel@55 { + reg = <55>; + label = "rx2_dsa_3"; //axi_gpio_2 24 + }; + + channel@56 { + reg = <56>; + label = "rx2_dsa_4"; //axi_gpio_2 25 + }; + + channel@57 { + reg = <57>; + label = "rx2_dsa_5"; //axi_gpio_2 26 + }; + + channel@58 { + reg = <58>; + label = "rx3_dsa_0"; //axi_gpio_2 27 + }; + + channel@59 { + reg = <59>; + label = "rx3_dsa_1"; //axi_gpio_2 28 + }; + + channel@60 { + reg = <60>; + label = "rx3_dsa_2"; //axi_gpio_2 29 + }; + + channel@61 { + reg = <61>; + label = "rx3_dsa_3"; //axi_gpio_2 30 + }; + + channel@62 { + reg = <62>; + label = "rx3_dsa_4"; //axi_gpio_2 31 + }; + + channel@63 { + reg = <63>; + label = "rx3_dsa_5"; //axi_gpio_2 32 + }; + + channel@64 { + reg = <64>; + label = "tx_enable_0"; //axi_gpio_2 33 + }; + + channel@65 { + reg = <65>; + label = "tx_enable_1"; //axi_gpio_2 34 + }; + + channel@66 { + reg = <66>; + label = "tx_enable_2"; //axi_gpio_2 35 + }; + + channel@67 { + reg = <67>; + label = "tx_enable_3"; //axi_gpio_2 36 + }; + + channel@68 { + reg = <68>; + label = "rx_enable_0"; //axi_gpio_2 37 + }; + + channel@69 { + reg = <69>; + label = "rx_enable_1"; //axi_gpio_2 38 + }; + + channel@70 { + reg = <70>; + label = "rx_enable_2"; //axi_gpio_2 39 + }; + + channel@71 { + reg = <71>; + label = "rx_enable_3"; //axi_gpio_2 40 + }; + + channel@72 { + reg = <72>; + label = "rx_amp_bypass_1"; //axi_gpio_2 41 + }; + + channel@73 { + reg = <73>; + label = "rx_amp_bypass_2"; //axi_gpio_2 42 + }; + + channel@74 { + reg = <74>; + label = "rx_amp_bypass_3"; //axi_gpio_2 43 + }; + + channel@75 { + reg = <75>; + label = "rx_amp_bypass_4"; //axi_gpio_2 44 + }; +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/xilinx/vu11p-ad9084-vpx-reva-204C_M4_L8_NP16_8p0_4x2.dtso b/arch/arm64/boot/dts/xilinx/vu11p-ad9084-vpx-reva-204C_M4_L8_NP16_8p0_4x2.dtso new file mode 100644 index 00000000000000..fb7ab38f68b772 --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/vu11p-ad9084-vpx-reva-204C_M4_L8_NP16_8p0_4x2.dtso @@ -0,0 +1,684 @@ +/dts-v1/; +/plugin/; + +#include +#include + +#ifndef DEVICE_PROFILE_NAME +#define DEVICE_PROFILE_NAME "204C_M4_L8_NP16_8p0_4x2.bin" +#endif + +#ifndef OUT_CLK_SELECT +#define OUT_CLK_SELECT XCVR_PROGDIV_CLK +#endif + +#ifndef ASYNM_A_B_MODE +#define ASYNM_A_B_MODE 1 +#endif + +#ifndef HSCI_ENABLE +#define HSCI_ENABLE 0 +#endif + +#ifndef VU11_FIRMWARE_NAME +#define VU11_FIRMWARE_NAME "vu11p.bin" +#endif + +&vu11p_fpga_region { + #address-cells = <2>; + #size-cells = <2>; + + firmware-name = VU11_FIRMWARE_NAME; + + mig_clkout1: clock@0 { + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "vu11p_mig_1"; + compatible = "fixed-clock"; + }; + + clkin_125: clock@1 { + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "clkin_ref"; + compatible = "fixed-clock"; + }; + + clkin_62p5: clock@2 { + #clock-cells = <0>; + clock-frequency = <62500000>; + clock-output-names = "clkin_div2_ref"; + compatible = "fixed-clock"; + }; + + axi_intc_0: interrupt-controller@88160000 { + #interrupt-cells = <2>; + clock-names = "mig_clkout1"; + clocks = <&mig_clkout1>; + compatible = "xlnx,axi-intc-4.1", "xlnx,xps-intc-1.00.a"; + interrupt-controller; + interrupt-names = "irq"; + interrupt-parent = <&gic>; + interrupts = <0 104 4>; + reg = <0x0 0x88160000 0x0 0x1000>; + xlnx,kind-of-intr = <0xffe0385>; + xlnx,num-intr-inputs = <17>; + }; + + adf4382_spi: spi@88000000 { + bits-per-word = <8>; + compatible = "xlnx,axi-quad-spi-3.2", "xlnx,xps-spi-2.00.a"; + fifo-size = <16>; + interrupt-names = "ip2intc_irpt"; + interrupt-parent = <&axi_intc_0>; + interrupts = <8 0>; + num-cs = <0x1>; + reg = <0x0 0x88000000 0x0 0x1000>; + xlnx,num-ss-bits = <0x1>; + xlnx,spi-mode = <0>; + + #address-cells = <1>; + #size-cells = <0>; + adf4382: adf4382@0 { + #clock-cells = <1>; + compatible = "adi,adf4382"; + reg = <0>; + spi-max-frequency = <1000000>; + clocks = <&clkin_62p5>; + clock-names = "ref_clk"; + adi,ref-doubler-enable; + clock-output-names = "adf4382_out_clk"; + adi,power-up-frequency = /bits/ 64 <8000000000>; + }; + }; + + ltc6952_spi: spi@881a0000 { + bits-per-word = <8>; + compatible = "xlnx,axi-quad-spi-3.2", "xlnx,xps-spi-2.00.a"; + fifo-size = <16>; + interrupt-names = "ip2intc_irpt"; + interrupt-parent = <&axi_intc_0>; + interrupts = <9 0>; + num-cs = <2>; + reg = <0x0 0x881A0000 0x0 0x1000>; + xlnx,num-ss-bits = <0x2>; + xlnx,spi-mode = <0>; + + #address-cells = <1>; + #size-cells = <0>; + + ltc6952: ltc6952@0 { + compatible = "adi,ltc6952"; + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <10000000>; + label = "ltc6952"; + + clocks = <&clkin_125> , <<c6948>; + clock-names = "clkin", "vcoin"; + vcoin-clock-scales = <1 10>; + + adi,vco-frequency-hz = <2500000000>; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-sysref-provider; + + clock-output-names = "ltc6952_0_out0", "ltc6952_0_out1", + "ltc6952_0_out2", "ltc6952_0_out3", "ltc6952_0_out4", + "ltc6952_0_out5", "ltc6952_0_out6", "ltc6952_0_out7", + "ltc6952_0_out8", "ltc6952_0_out9", "ltc6952_0_out10"; + + #clock-cells = <1>; + + adi,pulse-generator-mode = <2>; /* Four Pulses */ + + // channel@1 { + // reg = <1>; + // adi,extended-name = "Aurora RF GTH"; + // adi,divider = <6>; + // adi,digital-delay = <0>; + // adi,analog-delay = <0>; + // }; + // channel@2 { + // reg = <2>; + // adi,extended-name = "Apollo PLL REF CLK"; + // adi,divider = <6>; + // adi,digital-delay = <0>; + // adi,analog-delay = <0>; + // adi,sysref-mode = <0>; + // adi,jesd204-sysref-chan; + // }; + channel@3 { + reg = <3>; + adi,extended-name = "Apollo SYSREF"; + adi,divider = <768>; + adi,digital-delay = <0>; + adi,analog-delay = <0>; + adi,sysref-mode = <0>; + adi,jesd204-sysref-chan; + }; + channel@4 { + reg = <4>; + adi,extended-name = "VUP JESD SYSREF"; + adi,divider = <768>; + adi,digital-delay = <0>; + adi,analog-delay = <0>; + adi,sysref-mode = <0>; + adi,jesd204-sysref-chan; + }; + channel@5 { + reg = <5>; + adi,extended-name = "VUP Core CLK"; + adi,divider = <20>; + adi,digital-delay = <0>; + adi,analog-delay = <0>; + }; + channel@6 { + reg = <6>; + adi,extended-name = "JESD REF CLK 1"; + adi,divider = <10>; + adi,digital-delay = <0>; + adi,analog-delay = <0>; + }; + channel@7 { + reg = <7>; + adi,extended-name = "JESD REF CLK 2"; + adi,divider = <10>; + adi,digital-delay = <0>; + adi,analog-delay = <0>; + }; + // channel@8 { + // reg = <8>; + // adi,extended-name = "REF CLL RFPC"; + // adi,divider = <6>; + // adi,digital-delay = <0>; + // adi,analog-delay = <0>; + // }; + // channel@9 { + // reg = <9>; + // adi,extended-name = "SYNC RFPC"; + // adi,divider = <6>; + // adi,digital-delay = <0>; + // adi,analog-delay = <0>; + // }; + // channel@10 { + // reg = <10>; + // adi,extended-name = "Auroro RF GTY"; + // adi,divider = <6>; + // adi,digital-delay = <0>; + // adi,analog-delay = <0>; + // }; + }; + + ltc6948: ltc6948@1 { + #clock-cells = <0>; + compatible = "adi,ltc6948"; + reg = <1>; + spi-max-frequency = <5000000>; + clocks = <&clkin_125>; + clock-names = "clkin"; + clock-output-names = "ltc6948_out_clk"; + clock-scales = <1 10>; + }; + }; + + axi_gpio_0: gpio@88120000 { + #gpio-cells = <2>; + clock-frequency = <100000000>; + clock-names = "s_axi_aclk"; + clocks = <&mig_clkout1>; + compatible = "xlnx,axi-gpio-2.0", "xlnx,xps-gpio-1.00.a"; + gpio-controller ; + reg = <0x0 0x88120000 0x0 0x10000>; + xlnx,all-inputs = <0x0>; + xlnx,all-inputs-2 = <0x0>; + xlnx,all-outputs = <0x0>; + xlnx,all-outputs-2 = <0x0>; + xlnx,dout-default = <0x00000000>; + xlnx,dout-default-2 = <0x00000000>; + xlnx,gpio-width = <0x20>; + xlnx,gpio2-width = <0x20>; + xlnx,interrupt-present = <0x0>; + xlnx,is-dual = <0x1>; + xlnx,tri-default = <0xFFFFFFFF>; + xlnx,tri-default-2 = <0xFFFFFFFF>; + }; + + axi_gpio_1: gpio@88130000 { + #gpio-cells = <2>; + clock-frequency = <100000000>; + clock-names = "s_axi_aclk"; + clocks = <&mig_clkout1>; + compatible = "xlnx,axi-gpio-2.0", "xlnx,xps-gpio-1.00.a"; + gpio-controller ; + reg = <0x0 0x88130000 0x0 0x10000>; + xlnx,all-inputs = <0x0>; + xlnx,all-inputs-2 = <0x0>; + xlnx,all-outputs = <0x0>; + xlnx,all-outputs-2 = <0x0>; + xlnx,dout-default = <0x00000000>; + xlnx,dout-default-2 = <0x00000000>; + xlnx,gpio-width = <0x20>; + xlnx,gpio2-width = <0x20>; + xlnx,interrupt-present = <0x0>; + xlnx,is-dual = <0x1>; + xlnx,tri-default = <0xFFFFFFFF>; + xlnx,tri-default-2 = <0xFFFFFFFF>; + }; + + axi_gpio_2: gpio@88140000 { + #gpio-cells = <2>; + clock-frequency = <100000000>; + clock-names = "s_axi_aclk"; + clocks = <&mig_clkout1>; + compatible = "xlnx,axi-gpio-2.0", "xlnx,xps-gpio-1.00.a"; + gpio-controller; + reg = <0x0 0x88140000 0x0 0x10000>; + xlnx,all-inputs = <0x0>; + xlnx,all-inputs-2 = <0x0>; + xlnx,all-outputs = <0x0>; + xlnx,all-outputs-2 = <0x0>; + xlnx,dout-default = <0x00000000>; + xlnx,dout-default-2 = <0x00000000>; + xlnx,gpio-width = <0x20>; + xlnx,gpio2-width = <0x13>; + xlnx,interrupt-present = <0x0>; + xlnx,is-dual = <0x1>; + xlnx,tri-default = <0xFFFFFFFF>; + xlnx,tri-default-2 = <0xFFFFFFFF>; + }; + + axi_iic_main: i2c@88150000 { + clock-frequency = <100000000>; + clocks = <&mig_clkout1>; + compatible = "xlnx,axi-iic-2.1", "xlnx,xps-iic-2.00.a"; + interrupt-names = "iic2intc_irpt"; + interrupt-parent = <&axi_intc_0>; + interrupts = <1 2>; + reg = <0x0 0x88150000 0x0 0x10000>; + }; + + axi_sysid_0: axi_sysid@42000000 { + compatible = "adi,axi-sysid-1.00.a"; + reg = <0x0 0x88170000 0x0 0x1000>; + }; + + rx_dma: dma@88090000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x0 0x88090000 0x0 0x10000>; + #dma-cells = <1>; + #clock-cells = <0>; + interrupt-parent = <&axi_intc_0>; + interrupts = <3 2>; + clocks = <&mig_clkout1>; + memory-region = <&vu11p_ddr_dma>; + }; + + tx_dma: dma@880f0000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x0 0x880F0000 0x0 0x10000>; + #dma-cells = <1>; + #clock-cells = <0>; + interrupt-parent = <&axi_intc_0>; + interrupts = <4 2>; + clocks = <&mig_clkout1>; + memory-region = <&vu11p_ddr_dma>; + }; + + axi_data_offload_rx: data_offload_rx@88020000 { + compatible = "adi,axi-data-offload-1.0.a"; + reg = <0x0 0x88020000 0x0 0x10000>; + }; + + axi_data_offload_tx: data_offload_tx@88050000 { + compatible = "adi,axi-data-offload-1.0.a"; + reg = <0x0 0x88050000 0x0 0x10000>; + }; + + axi_ad9084_adxcvr_rx: axi-adxcvr-rx@880b0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "adi,axi-adxcvr-1.0"; + reg = <0x0 0x880B0000 0x0 0x1000>; + + clocks = <<c6952 7>; /* div40 is controlled by axi_ad9084_rx_jesd */ + clock-names = "conv"; + + #clock-cells = <1>; + clock-output-names = "rx_gt_clk", "rx_out_clk"; + + adi,sys-clk-select = ; + adi,out-clk-select = ; + adi,use-lpm-enable; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <<c6952 0 FRAMER_LINK_A0_RX>; + }; + + axi_ad9084_adxcvr_tx: axi-adxcvr-tx@88110000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "adi,axi-adxcvr-1.0"; + reg = <0x0 0x88110000 0x0 0x1000>; + + clocks = <<c6952 7>; /* div40 is controlled by axi_ad9084_tx_jesd */ + clock-names = "conv"; + + #clock-cells = <1>; + clock-output-names = "tx_gt_clk", "tx_out_clk"; + + adi,sys-clk-select = ; + adi,out-clk-select = ; /* XCVR_PROGDIV_CLK */ + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <<c6952 0 DEFRAMER_LINK_A0_TX>; + }; + + axi_ad9084_rx_jesd: axi-jesd204-rx@880a0000 { + compatible = "adi,axi-jesd204-rx-1.0"; + reg = <0x0 0x880a0000 0x0 0x1000>; + interrupt-parent = <&axi_intc_0>; + interrupts = <5 2>; + + clocks = <&mig_clkout1>, <&axi_ad9084_adxcvr_rx 1>, <<c6952 5>, <&axi_ad9084_adxcvr_rx 0>; + clock-names = "s_axi_aclk", "link_clk", "device_clk", "lane_clk"; + + #clock-cells = <0>; + clock-output-names = "jesd_rx_lane_clk"; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_adxcvr_rx 0 FRAMER_LINK_A0_RX>; + }; + + axi_ad9084_tx_jesd: axi-jesd204-tx@88100000 { + compatible = "adi,axi-jesd204-tx-1.0"; + reg = <0x0 0x88100000 0x0 0x1000>; + + interrupt-parent = <&axi_intc_0>; + interrupts = <6 2>; + + clocks = <&mig_clkout1>, <&axi_ad9084_adxcvr_tx 1>, <<c6952 5>, <&axi_ad9084_adxcvr_tx 0>; + clock-names = "s_axi_aclk", "link_clk", "device_clk", "lane_clk"; + + #clock-cells = <0>; + clock-output-names = "jesd_tx_lane_clk"; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_adxcvr_tx 0 DEFRAMER_LINK_A0_TX>; + }; + + apollo_spi: spi@88030000 { + bits-per-word = <8>; + compatible = "xlnx,axi-quad-spi-3.2", "xlnx,xps-spi-2.00.a"; + fifo-size = <16>; + interrupt-names = "ip2intc_irpt"; + interrupt-parent = <&axi_intc_0>; + interrupts = <7 0>; + num-cs = <1>; + reg = <0x0 0x88030000 0x0 0x1000>; + xlnx,num-ss-bits = <0x1>; + xlnx,spi-mode = <0>; + + #address-cells = <1>; + #size-cells = <0>; + + trx0_ad9084: ad9084@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "adi,ad9084"; + reg = <0>; + spi-max-frequency = <5000000>; + + /* Clocks */ + clocks = <&adf4382 0>; + clock-names = "dev_clk"; + dev_clk-clock-scales = <1 10>; + + clock-output-names = "rx_sampl_clk", "tx_sampl_clk"; + #clock-cells = <1>; + + // interrupt-names = "fft_done_A", "fft_done_B"; + // interrupt-parent = <&axi_gpio>; + // interrupts = <17 1 18 1>; + +#if HSCI_ENABLE + adi,axi-hsci-connected = <&axi_hsci>; + adi,hsci-auto-linkup-mode-en; + adi,hsci-disable-after-boot-en; +#endif + + jesd204-device; + #jesd204-cells = <2>; + jesd204-top-device = <0>; /* This is the TOP device */ + jesd204-ignore-errors; + +#ifdef ASYNM_A_B_MODE + jesd204-link-ids = ; + + jesd204-inputs = + <&axi_ad9084_core_rx 0 FRAMER_LINK_A0_RX>, + <&axi_ad9084_rx_jesd_b 0 FRAMER_LINK_B0_RX>, + <&axi_ad9084_core_tx 0 DEFRAMER_LINK_A0_TX>, + <&axi_ad9084_core_tx_b 0 DEFRAMER_LINK_B0_TX>; + + adi,side-b-use-seperate-tpl-en; +#else + jesd204-link-ids = ; + + jesd204-inputs = + <&axi_ad9084_core_rx 0 FRAMER_LINK_A0_RX>, + <&axi_ad9084_core_tx 0 DEFRAMER_LINK_A0_TX>; +#endif + + reset-gpios = <&axi_gpio_2 0x31 0>; + adi,device-profile-fw-name = DEVICE_PROFILE_NAME; + + adi,jrx0-physical-lane-mapping = <11 4 6 10 9 8 7 2 0 3 5 1>; + adi,jtx0-logical-lane-mapping = < 8 6 10 11 9 4 7 2 5 0 3 1>; + adi,jrx1-physical-lane-mapping = <3 1 5 0 7 2 8 6 4 9 10 11>; + adi,jtx1-logical-lane-mapping = <0 2 1 4 3 5 6 10 7 11 8 9>; + + //adi,standalone-enable; + }; + + }; + + axi_ad9084_core_rx: axi-ad9084-rx-hpc@881b0000 { + compatible = "adi,axi-ad9081-rx-1.0"; + reg = <0x0 0x881B0000 0x0 0x1000>; + dmas = <&rx_dma 0>; + dma-names = "rx"; + spibus-connected = <&trx0_ad9084>; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_rx_jesd 0 FRAMER_LINK_A0_RX>; + }; + + axi_ad9084_core_tx: axi-ad9084-tx-hpc@881d0000 { + compatible = "adi,axi-ad9081-tx-1.0"; + reg = <0x0 0x881D0000 0x0 0x1000>; + dmas = <&tx_dma 0>; + dma-names = "tx"; + clocks = <&trx0_ad9084 1>; + clock-names = "sampl_clk"; + spibus-connected = <&trx0_ad9084>; + adi,axi-pl-fifo-enable; + adi,axi-data-offload-connected = <&axi_data_offload_tx>; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_tx_jesd 0 DEFRAMER_LINK_A0_TX>; + }; + +#if HSCI_ENABLE + hsci_clkgen: axi-clkgen@881F0000 { + compatible = "adi,axi-clkgen-2.00.a"; + reg = <0x0 0x881F0000 0x0 0x1000>; + #clock-cells = <0>; + clocks = <&mig_clkout1>, <&mig_clkout1>; + clock-names = "s_axi_aclk", "clkin1"; + clock-output-names = "hsci_clkgen"; + }; + + axi_hsci: axi_hsci@88200000 { + compatible = "adi,axi-hsci-1.0.a"; + reg = <0x0 0x88200000 0x0 0x40000>; + clocks = <&hsci_clkgen>; + clock-names = "pclk"; + adi,hsci-interface-speed-mhz = <800>; + }; +#endif + +#ifdef ASYNM_A_B_MODE + rx_dma_b: dma@88060000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x0 0x88060000 0x0 0x10000>; + #dma-cells = <1>; + #clock-cells = <0>; + interrupt-parent = <&axi_intc_0>; + interrupts = <10 2>; + clocks = <&mig_clkout1>; + memory-region = <&vu11p_ddr_dma>; + }; + + tx_dma_b: dma@880c0000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x0 0x880C0000 0x0 0x10000>; + #dma-cells = <1>; + #clock-cells = <0>; + interrupt-parent = <&axi_intc_0>; + interrupts = <11 2>; + clocks = <&mig_clkout1>; + memory-region = <&vu11p_ddr_dma>; + + }; + + axi_ad9084_core_rx_b: axi-ad9084b-rx-b@881c0000 { + compatible = "adi,axi-adc-tpl-so-10.0.a"; + reg = <0x0 0x881C0000 0x0 0x10000>; + dmas = <&rx_dma_b 0>; + dma-names = "rx"; + clocks = <&trx0_ad9084 0>; /* FIXME */ + clock-names = "sampl_clk"; + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_rx_jesd_b 0 FRAMER_LINK_B0_RX>; + }; + + axi_ad9084_core_tx_b: axi-ad9084-tx-b@881e0000 { + compatible = "adi,axi-ad9081-tx-1.0"; + reg = <0x0 0x881E0000 0x0 0x10000>; + dmas = <&tx_dma_b 0>; + dma-names = "tx"; + clocks = <&trx0_ad9084 1>; /* FIXME */ + clock-names = "sampl_clk"; + adi,axi-pl-fifo-enable; + adi,axi-data-offload-connected = <&axi_data_offload_tx_b>; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_tx_jesd_b 0 DEFRAMER_LINK_B0_TX>; + }; + + axi_ad9084_rx_jesd_b: axi-jesd204-rx-b@88070000 { + compatible = "adi,axi-jesd204-rx-1.0"; + reg = <0x0 0x88070000 0x0 0x10000>; + + interrupt-parent = <&axi_intc_0>; + interrupts = <12 2>; + + clocks = <&mig_clkout1>, <&axi_ad9084_adxcvr_rx_b 1>, <<c6952 5>, <&axi_ad9084_adxcvr_rx_b 0>; + clock-names = "s_axi_aclk", "link_clk", "device_clk", "lane_clk"; + + #clock-cells = <0>; + clock-output-names = "jesd_rx_lane_clk_b"; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_adxcvr_rx_b 0 FRAMER_LINK_B0_RX>; + }; + + axi_ad9084_tx_jesd_b: axi-jesd204-tx-b@880d0000 { + compatible = "adi,axi-jesd204-tx-1.0"; + reg = <0x0 0x880D0000 0x0 0x10000>; + + interrupt-parent = <&axi_intc_0>; + interrupts = <13 2>; + + clocks = <&mig_clkout1>, <&axi_ad9084_adxcvr_tx_b 1>, <<c6952 5>, <&axi_ad9084_adxcvr_tx_b 0>; + clock-names = "s_axi_aclk", "link_clk", "device_clk", "lane_clk"; + + #clock-cells = <0>; + clock-output-names = "jesd_tx_lane_clk_b"; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_adxcvr_tx_b 0 DEFRAMER_LINK_B0_TX>; + }; + + axi_ad9084_adxcvr_rx_b: axi-adxcvr-rx-b@88080000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "adi,axi-adxcvr-1.0"; + reg = <0x0 0x88080000 0x0 0x10000>; + + clocks = <<c6952 6>; /* div40 is controlled by axi_ad9084_rx_jesd */ + clock-names = "conv"; + + #clock-cells = <1>; + clock-output-names = "rx_gt_clk_b", "rx_out_clk_b"; + + adi,sys-clk-select = ; + adi,out-clk-select = ; + adi,use-lpm-enable; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <<c6952 0 FRAMER_LINK_B0_RX>; + }; + + axi_ad9084_adxcvr_tx_b: axi-adxcvr-tx-b@880e0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "adi,axi-adxcvr-1.0"; + reg = <0x0 0x880E0000 0x0 0x10000>; + + clocks = <<c6952 6>; /* div40 is controlled by axi_ad9084_tx_jesd */ + clock-names = "conv"; + + #clock-cells = <1>; + clock-output-names = "tx_gt_clk_b", "tx_out_clk_b"; + + adi,sys-clk-select = ; + adi,out-clk-select = ; /* XCVR_PROGDIV_CLK */ + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <<c6952 0 DEFRAMER_LINK_B0_TX>; + }; + + axi_data_offload_rx_b: data_offload_rx_b@88010000 { + compatible = "adi,axi-data-offload-1.0.a"; + reg = <0x0 0x88010000 0x0 0x10000>; + }; + + axi_data_offload_tx_b: data_offload_tx_b@88040000 { + compatible = "adi,axi-data-offload-1.0.a"; + reg = <0x0 0x88040000 0x0 0x10000>; + }; +#endif /* ASYNM_A_B_MODE */ + + rfpc_one_bit_adc_dac: one-bit-adc-dac@0 { + compatible = "adi,one-bit-adc-dac"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/xilinx/vu11p-ad9084-vpx-reva.dtso b/arch/arm64/boot/dts/xilinx/vu11p-ad9084-vpx-reva.dtso new file mode 100644 index 00000000000000..ba1ecf72003f2e --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/vu11p-ad9084-vpx-reva.dtso @@ -0,0 +1,685 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +/plugin/; + +#include +#include + +#ifndef DEVICE_PROFILE_NAME +#define DEVICE_PROFILE_NAME "204C_M4_L8_NP16_2p5_4x2.bin" +#endif + +#ifndef OUT_CLK_SELECT +#define OUT_CLK_SELECT XCVR_PROGDIV_CLK +#endif + +#ifndef ASYNM_A_B_MODE +#define ASYNM_A_B_MODE 1 +#endif + +#ifndef HSCI_ENABLE +#define HSCI_ENABLE 0 +#endif + +#ifndef VU11_FIRMWARE_NAME +#define VU11_FIRMWARE_NAME "vu11p.bin" +#endif + +&vu11p_fpga_region { + #address-cells = <2>; + #size-cells = <2>; + + firmware-name = VU11_FIRMWARE_NAME; + + mig_clkout1: clock@0 { + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "vu11p_mig_1"; + compatible = "fixed-clock"; + }; + + clkin_125: clock@1 { + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "clkin_ref"; + compatible = "fixed-clock"; + }; + + clkin_62p5: clock@2 { + #clock-cells = <0>; + clock-frequency = <62500000>; + clock-output-names = "clkin_div2_ref"; + compatible = "fixed-clock"; + }; + + axi_intc_0: interrupt-controller@88160000 { + #interrupt-cells = <2>; + clock-names = "mig_clkout1"; + clocks = <&mig_clkout1>; + compatible = "xlnx,axi-intc-4.1", "xlnx,xps-intc-1.00.a"; + interrupt-controller; + interrupt-names = "irq"; + interrupt-parent = <&gic>; + interrupts = <0 104 4>; + reg = <0x0 0x88160000 0x0 0x1000>; + xlnx,kind-of-intr = <0xffe0385>; + xlnx,num-intr-inputs = <17>; + }; + + adf4382_spi: spi@88000000 { + bits-per-word = <8>; + compatible = "xlnx,axi-quad-spi-3.2", "xlnx,xps-spi-2.00.a"; + fifo-size = <16>; + interrupt-names = "ip2intc_irpt"; + interrupt-parent = <&axi_intc_0>; + interrupts = <8 0>; + num-cs = <0x1>; + reg = <0x0 0x88000000 0x0 0x1000>; + xlnx,num-ss-bits = <0x1>; + xlnx,spi-mode = <0>; + + #address-cells = <1>; + #size-cells = <0>; + adf4382: adf4382@0 { + #clock-cells = <1>; + compatible = "adi,adf4382"; + reg = <0>; + spi-max-frequency = <1000000>; + clocks = <&clkin_62p5>; + clock-names = "ref_clk"; + adi,ref-doubler-enable; + clock-output-names = "adf4382_out_clk"; + adi,power-up-frequency = /bits/ 64 <20000000000>; + }; + }; + + ltc6952_spi: spi@881a0000 { + bits-per-word = <8>; + compatible = "xlnx,axi-quad-spi-3.2", "xlnx,xps-spi-2.00.a"; + fifo-size = <16>; + interrupt-names = "ip2intc_irpt"; + interrupt-parent = <&axi_intc_0>; + interrupts = <9 0>; + num-cs = <2>; + reg = <0x0 0x881A0000 0x0 0x1000>; + xlnx,num-ss-bits = <0x2>; + xlnx,spi-mode = <0>; + + #address-cells = <1>; + #size-cells = <0>; + + ltc6952: ltc6952@0 { + compatible = "adi,ltc6952"; + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <10000000>; + label = "ltc6952"; + + clocks = <&clkin_125> , <<c6948>; + clock-names = "clkin", "vcoin"; + vcoin-clock-scales = <1 10>; + + adi,vco-frequency-hz = <2500000000>; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-sysref-provider; + + clock-output-names = "ltc6952_0_out0", "ltc6952_0_out1", + "ltc6952_0_out2", "ltc6952_0_out3", "ltc6952_0_out4", + "ltc6952_0_out5", "ltc6952_0_out6", "ltc6952_0_out7", + "ltc6952_0_out8", "ltc6952_0_out9", "ltc6952_0_out10"; + + #clock-cells = <1>; + + adi,pulse-generator-mode = <2>; /* Four Pulses */ + + // channel@1 { + // reg = <1>; + // adi,extended-name = "Aurora RF GTH"; + // adi,divider = <6>; + // adi,digital-delay = <0>; + // adi,analog-delay = <0>; + // }; + // channel@2 { + // reg = <2>; + // adi,extended-name = "Apollo PLL REF CLK"; + // adi,divider = <6>; + // adi,digital-delay = <0>; + // adi,analog-delay = <0>; + // adi,sysref-mode = <0>; + // adi,jesd204-sysref-chan; + // }; + channel@3 { + reg = <3>; + adi,extended-name = "Apollo SYSREF"; + adi,divider = <768>; + adi,digital-delay = <0>; + adi,analog-delay = <0>; + adi,sysref-mode = <0>; + adi,jesd204-sysref-chan; + }; + channel@4 { + reg = <4>; + adi,extended-name = "VUP JESD SYSREF"; + adi,divider = <768>; + adi,digital-delay = <0>; + adi,analog-delay = <0>; + adi,sysref-mode = <0>; + adi,jesd204-sysref-chan; + }; + channel@5 { + reg = <5>; + adi,extended-name = "VUP Core CLK"; + adi,divider = <8>; + adi,digital-delay = <0>; + adi,analog-delay = <0>; + }; + channel@6 { + reg = <6>; + adi,extended-name = "JESD REF CLK 1"; + adi,divider = <4>; + adi,digital-delay = <0>; + adi,analog-delay = <0>; + }; + channel@7 { + reg = <7>; + adi,extended-name = "JESD REF CLK 2"; + adi,divider = <4>; + adi,digital-delay = <0>; + adi,analog-delay = <0>; + }; + // channel@8 { + // reg = <8>; + // adi,extended-name = "REF CLL RFPC"; + // adi,divider = <6>; + // adi,digital-delay = <0>; + // adi,analog-delay = <0>; + // }; + // channel@9 { + // reg = <9>; + // adi,extended-name = "SYNC RFPC"; + // adi,divider = <6>; + // adi,digital-delay = <0>; + // adi,analog-delay = <0>; + // }; + // channel@10 { + // reg = <10>; + // adi,extended-name = "Auroro RF GTY"; + // adi,divider = <6>; + // adi,digital-delay = <0>; + // adi,analog-delay = <0>; + // }; + }; + + ltc6948: ltc6948@1 { + #clock-cells = <0>; + compatible = "adi,ltc6948"; + reg = <1>; + spi-max-frequency = <5000000>; + clocks = <&clkin_125>; + clock-names = "clkin"; + clock-output-names = "ltc6948_out_clk"; + clock-scales = <1 10>; + }; + }; + + axi_gpio_0: gpio@88120000 { + #gpio-cells = <2>; + clock-frequency = <100000000>; + clock-names = "s_axi_aclk"; + clocks = <&mig_clkout1>; + compatible = "xlnx,axi-gpio-2.0", "xlnx,xps-gpio-1.00.a"; + gpio-controller ; + reg = <0x0 0x88120000 0x0 0x10000>; + xlnx,all-inputs = <0x0>; + xlnx,all-inputs-2 = <0x0>; + xlnx,all-outputs = <0x0>; + xlnx,all-outputs-2 = <0x0>; + xlnx,dout-default = <0x00000000>; + xlnx,dout-default-2 = <0x00000000>; + xlnx,gpio-width = <0x20>; + xlnx,gpio2-width = <0x20>; + xlnx,interrupt-present = <0x0>; + xlnx,is-dual = <0x1>; + xlnx,tri-default = <0xFFFFFFFF>; + xlnx,tri-default-2 = <0xFFFFFFFF>; + }; + + axi_gpio_1: gpio@88130000 { + #gpio-cells = <2>; + clock-frequency = <100000000>; + clock-names = "s_axi_aclk"; + clocks = <&mig_clkout1>; + compatible = "xlnx,axi-gpio-2.0", "xlnx,xps-gpio-1.00.a"; + gpio-controller ; + reg = <0x0 0x88130000 0x0 0x10000>; + xlnx,all-inputs = <0x0>; + xlnx,all-inputs-2 = <0x0>; + xlnx,all-outputs = <0x0>; + xlnx,all-outputs-2 = <0x0>; + xlnx,dout-default = <0x00000000>; + xlnx,dout-default-2 = <0x00000000>; + xlnx,gpio-width = <0x20>; + xlnx,gpio2-width = <0x20>; + xlnx,interrupt-present = <0x0>; + xlnx,is-dual = <0x1>; + xlnx,tri-default = <0xFFFFFFFF>; + xlnx,tri-default-2 = <0xFFFFFFFF>; + }; + + axi_gpio_2: gpio@88140000 { + #gpio-cells = <2>; + clock-frequency = <100000000>; + clock-names = "s_axi_aclk"; + clocks = <&mig_clkout1>; + compatible = "xlnx,axi-gpio-2.0", "xlnx,xps-gpio-1.00.a"; + gpio-controller; + reg = <0x0 0x88140000 0x0 0x10000>; + xlnx,all-inputs = <0x0>; + xlnx,all-inputs-2 = <0x0>; + xlnx,all-outputs = <0x0>; + xlnx,all-outputs-2 = <0x0>; + xlnx,dout-default = <0x00000000>; + xlnx,dout-default-2 = <0x00000000>; + xlnx,gpio-width = <0x20>; + xlnx,gpio2-width = <0x13>; + xlnx,interrupt-present = <0x0>; + xlnx,is-dual = <0x1>; + xlnx,tri-default = <0xFFFFFFFF>; + xlnx,tri-default-2 = <0xFFFFFFFF>; + }; + + axi_iic_main: i2c@88150000 { + clock-frequency = <100000000>; + clocks = <&mig_clkout1>; + compatible = "xlnx,axi-iic-2.1", "xlnx,xps-iic-2.00.a"; + interrupt-names = "iic2intc_irpt"; + interrupt-parent = <&axi_intc_0>; + interrupts = <1 2>; + reg = <0x0 0x88150000 0x0 0x10000>; + }; + + axi_sysid_0: axi_sysid@42000000 { + compatible = "adi,axi-sysid-1.00.a"; + reg = <0x0 0x88170000 0x0 0x1000>; + }; + + rx_dma: dma@88090000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x0 0x88090000 0x0 0x10000>; + #dma-cells = <1>; + #clock-cells = <0>; + interrupt-parent = <&axi_intc_0>; + interrupts = <3 2>; + clocks = <&mig_clkout1>; + memory-region = <&vu11p_ddr_dma>; + }; + + tx_dma: dma@880f0000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x0 0x880F0000 0x0 0x10000>; + #dma-cells = <1>; + #clock-cells = <0>; + interrupt-parent = <&axi_intc_0>; + interrupts = <4 2>; + clocks = <&mig_clkout1>; + memory-region = <&vu11p_ddr_dma>; + }; + + axi_data_offload_rx: data_offload_rx@88020000 { + compatible = "adi,axi-data-offload-1.0.a"; + reg = <0x0 0x88020000 0x0 0x10000>; + }; + + axi_data_offload_tx: data_offload_tx@88050000 { + compatible = "adi,axi-data-offload-1.0.a"; + reg = <0x0 0x88050000 0x0 0x10000>; + }; + + axi_ad9084_adxcvr_rx: axi-adxcvr-rx@880b0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "adi,axi-adxcvr-1.0"; + reg = <0x0 0x880B0000 0x0 0x1000>; + + clocks = <<c6952 7>; /* div40 is controlled by axi_ad9084_rx_jesd */ + clock-names = "conv"; + + #clock-cells = <1>; + clock-output-names = "rx_gt_clk", "rx_out_clk"; + + adi,sys-clk-select = ; + adi,out-clk-select = ; + adi,use-lpm-enable; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <<c6952 0 FRAMER_LINK_A0_RX>; + }; + + axi_ad9084_adxcvr_tx: axi-adxcvr-tx@88110000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "adi,axi-adxcvr-1.0"; + reg = <0x0 0x88110000 0x0 0x1000>; + + clocks = <<c6952 7>; /* div40 is controlled by axi_ad9084_tx_jesd */ + clock-names = "conv"; + + #clock-cells = <1>; + clock-output-names = "tx_gt_clk", "tx_out_clk"; + + adi,sys-clk-select = ; + adi,out-clk-select = ; /* XCVR_PROGDIV_CLK */ + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <<c6952 0 DEFRAMER_LINK_A0_TX>; + }; + + axi_ad9084_rx_jesd: axi-jesd204-rx@880a0000 { + compatible = "adi,axi-jesd204-rx-1.0"; + reg = <0x0 0x880a0000 0x0 0x1000>; + interrupt-parent = <&axi_intc_0>; + interrupts = <5 2>; + + clocks = <&mig_clkout1>, <&axi_ad9084_adxcvr_rx 1>, <<c6952 5>, <&axi_ad9084_adxcvr_rx 0>; + clock-names = "s_axi_aclk", "link_clk", "device_clk", "lane_clk"; + + #clock-cells = <0>; + clock-output-names = "jesd_rx_lane_clk"; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_adxcvr_rx 0 FRAMER_LINK_A0_RX>; + }; + + axi_ad9084_tx_jesd: axi-jesd204-tx@88100000 { + compatible = "adi,axi-jesd204-tx-1.0"; + reg = <0x0 0x88100000 0x0 0x1000>; + + interrupt-parent = <&axi_intc_0>; + interrupts = <6 2>; + + clocks = <&mig_clkout1>, <&axi_ad9084_adxcvr_tx 1>, <<c6952 5>, <&axi_ad9084_adxcvr_tx 0>; + clock-names = "s_axi_aclk", "link_clk", "device_clk", "lane_clk"; + + #clock-cells = <0>; + clock-output-names = "jesd_tx_lane_clk"; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_adxcvr_tx 0 DEFRAMER_LINK_A0_TX>; + }; + + apollo_spi: spi@88030000 { + bits-per-word = <8>; + compatible = "xlnx,axi-quad-spi-3.2", "xlnx,xps-spi-2.00.a"; + fifo-size = <16>; + interrupt-names = "ip2intc_irpt"; + interrupt-parent = <&axi_intc_0>; + interrupts = <7 0>; + num-cs = <1>; + reg = <0x0 0x88030000 0x0 0x1000>; + xlnx,num-ss-bits = <0x1>; + xlnx,spi-mode = <0>; + + #address-cells = <1>; + #size-cells = <0>; + + trx0_ad9084: ad9084@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "adi,ad9084"; + reg = <0>; + spi-max-frequency = <5000000>; + + /* Clocks */ + clocks = <&adf4382 0>; + clock-names = "dev_clk"; + dev_clk-clock-scales = <1 10>; + + clock-output-names = "rx_sampl_clk", "tx_sampl_clk"; + #clock-cells = <1>; + + // interrupt-names = "fft_done_A", "fft_done_B"; + // interrupt-parent = <&axi_gpio>; + // interrupts = <17 1 18 1>; + +#if HSCI_ENABLE + adi,axi-hsci-connected = <&axi_hsci>; + adi,hsci-auto-linkup-mode-en; + adi,hsci-disable-after-boot-en; +#endif + + jesd204-device; + #jesd204-cells = <2>; + jesd204-top-device = <0>; /* This is the TOP device */ + jesd204-ignore-errors; + +#ifdef ASYNM_A_B_MODE + jesd204-link-ids = ; + + jesd204-inputs = + <&axi_ad9084_core_rx 0 FRAMER_LINK_A0_RX>, + <&axi_ad9084_rx_jesd_b 0 FRAMER_LINK_B0_RX>, + <&axi_ad9084_core_tx 0 DEFRAMER_LINK_A0_TX>, + <&axi_ad9084_core_tx_b 0 DEFRAMER_LINK_B0_TX>; + + adi,side-b-use-seperate-tpl-en; +#else + jesd204-link-ids = ; + + jesd204-inputs = + <&axi_ad9084_core_rx 0 FRAMER_LINK_A0_RX>, + <&axi_ad9084_core_tx 0 DEFRAMER_LINK_A0_TX>; +#endif + + reset-gpios = <&axi_gpio_2 0x31 0>; + adi,device-profile-fw-name = DEVICE_PROFILE_NAME; + + adi,jrx0-physical-lane-mapping = <11 4 6 10 9 8 7 2 0 3 5 1>; + adi,jtx0-logical-lane-mapping = < 8 6 10 11 9 4 7 2 5 0 3 1>; + adi,jrx1-physical-lane-mapping = <3 1 5 0 7 2 8 6 4 9 10 11>; + adi,jtx1-logical-lane-mapping = <0 2 1 4 3 5 6 10 7 11 8 9>; + + //adi,standalone-enable; + }; + + }; + + axi_ad9084_core_rx: axi-ad9084-rx-hpc@881b0000 { + compatible = "adi,axi-ad9081-rx-1.0"; + reg = <0x0 0x881B0000 0x0 0x1000>; + dmas = <&rx_dma 0>; + dma-names = "rx"; + spibus-connected = <&trx0_ad9084>; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_rx_jesd 0 FRAMER_LINK_A0_RX>; + }; + + axi_ad9084_core_tx: axi-ad9084-tx-hpc@881d0000 { + compatible = "adi,axi-ad9081-tx-1.0"; + reg = <0x0 0x881D0000 0x0 0x1000>; + dmas = <&tx_dma 0>; + dma-names = "tx"; + clocks = <&trx0_ad9084 1>; + clock-names = "sampl_clk"; + spibus-connected = <&trx0_ad9084>; + adi,axi-pl-fifo-enable; + adi,axi-data-offload-connected = <&axi_data_offload_tx>; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_tx_jesd 0 DEFRAMER_LINK_A0_TX>; + }; + +#if HSCI_ENABLE + hsci_clkgen: axi-clkgen@881F0000 { + compatible = "adi,axi-clkgen-2.00.a"; + reg = <0x0 0x881F0000 0x0 0x1000>; + #clock-cells = <0>; + clocks = <&mig_clkout1>, <&mig_clkout1>; + clock-names = "s_axi_aclk", "clkin1"; + clock-output-names = "hsci_clkgen"; + }; + + axi_hsci: axi_hsci@88200000 { + compatible = "adi,axi-hsci-1.0.a"; + reg = <0x0 0x88200000 0x0 0x40000>; + clocks = <&hsci_clkgen>; + clock-names = "pclk"; + adi,hsci-interface-speed-mhz = <800>; + }; +#endif + +#ifdef ASYNM_A_B_MODE + rx_dma_b: dma@88060000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x0 0x88060000 0x0 0x10000>; + #dma-cells = <1>; + #clock-cells = <0>; + interrupt-parent = <&axi_intc_0>; + interrupts = <10 2>; + clocks = <&mig_clkout1>; + memory-region = <&vu11p_ddr_dma>; + }; + + tx_dma_b: dma@880c0000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x0 0x880C0000 0x0 0x10000>; + #dma-cells = <1>; + #clock-cells = <0>; + interrupt-parent = <&axi_intc_0>; + interrupts = <11 2>; + clocks = <&mig_clkout1>; + memory-region = <&vu11p_ddr_dma>; + + }; + + axi_ad9084_core_rx_b: axi-ad9084b-rx-b@881c0000 { + compatible = "adi,axi-adc-tpl-so-10.0.a"; + reg = <0x0 0x881C0000 0x0 0x10000>; + dmas = <&rx_dma_b 0>; + dma-names = "rx"; + clocks = <&trx0_ad9084 0>; /* FIXME */ + clock-names = "sampl_clk"; + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_rx_jesd_b 0 FRAMER_LINK_B0_RX>; + }; + + axi_ad9084_core_tx_b: axi-ad9084-tx-b@881e0000 { + compatible = "adi,axi-ad9081-tx-1.0"; + reg = <0x0 0x881E0000 0x0 0x10000>; + dmas = <&tx_dma_b 0>; + dma-names = "tx"; + clocks = <&trx0_ad9084 1>; /* FIXME */ + clock-names = "sampl_clk"; + adi,axi-pl-fifo-enable; + adi,axi-data-offload-connected = <&axi_data_offload_tx_b>; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_tx_jesd_b 0 DEFRAMER_LINK_B0_TX>; + }; + + axi_ad9084_rx_jesd_b: axi-jesd204-rx-b@88070000 { + compatible = "adi,axi-jesd204-rx-1.0"; + reg = <0x0 0x88070000 0x0 0x10000>; + + interrupt-parent = <&axi_intc_0>; + interrupts = <12 2>; + + clocks = <&mig_clkout1>, <&axi_ad9084_adxcvr_rx_b 1>, <<c6952 5>, <&axi_ad9084_adxcvr_rx_b 0>; + clock-names = "s_axi_aclk", "link_clk", "device_clk", "lane_clk"; + + #clock-cells = <0>; + clock-output-names = "jesd_rx_lane_clk_b"; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_adxcvr_rx_b 0 FRAMER_LINK_B0_RX>; + }; + + axi_ad9084_tx_jesd_b: axi-jesd204-tx-b@880d0000 { + compatible = "adi,axi-jesd204-tx-1.0"; + reg = <0x0 0x880D0000 0x0 0x10000>; + + interrupt-parent = <&axi_intc_0>; + interrupts = <13 2>; + + clocks = <&mig_clkout1>, <&axi_ad9084_adxcvr_tx_b 1>, <<c6952 5>, <&axi_ad9084_adxcvr_tx_b 0>; + clock-names = "s_axi_aclk", "link_clk", "device_clk", "lane_clk"; + + #clock-cells = <0>; + clock-output-names = "jesd_tx_lane_clk_b"; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_adxcvr_tx_b 0 DEFRAMER_LINK_B0_TX>; + }; + + axi_ad9084_adxcvr_rx_b: axi-adxcvr-rx-b@88080000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "adi,axi-adxcvr-1.0"; + reg = <0x0 0x88080000 0x0 0x10000>; + + clocks = <<c6952 6>; /* div40 is controlled by axi_ad9084_rx_jesd */ + clock-names = "conv"; + + #clock-cells = <1>; + clock-output-names = "rx_gt_clk_b", "rx_out_clk_b"; + + adi,sys-clk-select = ; + adi,out-clk-select = ; + adi,use-lpm-enable; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <<c6952 0 FRAMER_LINK_B0_RX>; + }; + + axi_ad9084_adxcvr_tx_b: axi-adxcvr-tx-b@880e0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "adi,axi-adxcvr-1.0"; + reg = <0x0 0x880E0000 0x0 0x10000>; + + clocks = <<c6952 6>; /* div40 is controlled by axi_ad9084_tx_jesd */ + clock-names = "conv"; + + #clock-cells = <1>; + clock-output-names = "tx_gt_clk_b", "tx_out_clk_b"; + + adi,sys-clk-select = ; + adi,out-clk-select = ; /* XCVR_PROGDIV_CLK */ + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <<c6952 0 DEFRAMER_LINK_B0_TX>; + }; + + axi_data_offload_rx_b: data_offload_rx_b@88010000 { + compatible = "adi,axi-data-offload-1.0.a"; + reg = <0x0 0x88010000 0x0 0x10000>; + }; + + axi_data_offload_tx_b: data_offload_tx_b@88040000 { + compatible = "adi,axi-data-offload-1.0.a"; + reg = <0x0 0x88040000 0x0 0x10000>; + }; +#endif /* ASYNM_A_B_MODE */ + + rfpc_one_bit_adc_dac: one-bit-adc-dac@0 { + compatible = "adi,one-bit-adc-dac"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/xilinx/vu11p-ad9084-vpx-revb-204C_M4_L4_NP16_8p0_2x2.dtso b/arch/arm64/boot/dts/xilinx/vu11p-ad9084-vpx-revb-204C_M4_L4_NP16_8p0_2x2.dtso new file mode 100644 index 00000000000000..8f34577298fed0 --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/vu11p-ad9084-vpx-revb-204C_M4_L4_NP16_8p0_2x2.dtso @@ -0,0 +1,728 @@ +/dts-v1/; +/plugin/; + +#include +#include + +// Parameters for AD9084 device profile +#define DEVICE_PROFILE_NAME "id01_uc47_ffsom_8G.bin" + +#define OUT_CLK_SELECT XCVR_PROGDIV_CLK + +#define ASYNM_A_B_MODE 1 + +#define HSCI_ENABLE 0 + +#define WITH_AION 0 + +#define VU11_FIRMWARE_NAME "vu11p.bin" + +#define JESD_SUBCLASS 0 + +&vu11p_fpga_region { + #address-cells = <2>; + #size-cells = <2>; + + firmware-name = VU11_FIRMWARE_NAME; + + mig_clkout1: clock@0 { + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "vu11p_mig_1"; + compatible = "fixed-clock"; + }; + + clkin_125: clock@1 { + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "clkin_ref"; + compatible = "fixed-clock"; + }; + + clkin_8000: clock@2 { + #clock-cells = <0>; + clock-frequency = <8000000000>; + clock-output-names = "apollo_sample_clock"; + compatible = "fixed-clock"; + }; + + clkin_250: clock@3 { + #clock-cells = <0>; + clock-frequency = <250000000>; + clock-output-names = "clkin_mul2_ref"; + compatible = "fixed-clock"; + }; + + axi_intc_0: interrupt-controller@88160000 { + #interrupt-cells = <2>; + clock-names = "mig_clkout1"; + clocks = <&mig_clkout1>; + compatible = "xlnx,axi-intc-4.1", "xlnx,xps-intc-1.00.a"; + interrupt-controller; + interrupt-names = "irq"; + interrupt-parent = <&gic>; + interrupts = <0 104 4>; + reg = <0x0 0x88160000 0x0 0x1000>; + xlnx,kind-of-intr = <0xffe0385>; + xlnx,num-intr-inputs = <19>; + }; + + ltc6952_spi: spi@881a0000 { + bits-per-word = <8>; + compatible = "xlnx,axi-quad-spi-3.2", "xlnx,xps-spi-2.00.a"; + fifo-size = <16>; + interrupt-names = "ip2intc_irpt"; + interrupt-parent = <&axi_intc_0>; + interrupts = <9 0>; + num-cs = <2>; + reg = <0x0 0x881A0000 0x0 0x1000>; + xlnx,num-ss-bits = <0x2>; + xlnx,spi-mode = <0>; + + #address-cells = <1>; + #size-cells = <0>; + + ltc6952: ltc6952@0 { + compatible = "adi,ltc6952"; + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <10000000>; + label = "ltc6952"; + + clocks = <&clkin_125> , <<c6948>; + clock-names = "clkin", "vcoin"; + vcoin-clock-scales = <1 10>; + + adi,vco-frequency-hz = <2500000000>; + + jesd204-device; + #jesd204-cells = <2>; +#if WITH_AION + jesd204-inputs = + <&adf4030 0 FRAMER_LINK_A0_RX>, + <&adf4030 0 DEFRAMER_LINK_A0_TX>; +#else + jesd204-sysref-provider; +#endif /* WITH_AION */ + + clock-output-names = "ltc6952_0_out0", "ltc6952_0_out1", + "ltc6952_0_out2", "ltc6952_0_out3", "ltc6952_0_out4", + "ltc6952_0_out5", "ltc6952_0_out6", "ltc6952_0_out7", + "ltc6952_0_out8", "ltc6952_0_out9", "ltc6952_0_out10"; + + #clock-cells = <1>; + + adi,pulse-generator-mode = <2>; /* Four Pulses */ +#if WITH_AION + channel@0 { + reg = <0>; + adi,extended-name = "ADF4030_BSYNC0"; + adi,divider = <256>; + adi,digital-delay = <0>; + adi,analog-delay = <0>; + }; +#endif /* WITH_AION */ + channel@3 { + reg = <3>; + adi,extended-name = "VUP Core CLK"; // adsy1100_AD9084_RX_device_clk + adi,divider = <10>; + adi,digital-delay = <0>; + adi,analog-delay = <0>; + }; +#ifndef WITH_AION + channel@4 { + reg = <4>; + adi,extended-name = "VUP JESD SYSREF"; + adi,divider = <1280>; + adi,digital-delay = <0>; + adi,analog-delay = <0>; + adi,sysref-mode = <0>; + adi,jesd204-sysref-chan; + }; + channel@5 { + reg = <5>; + adi,extended-name = "Apollo SYSREF"; + adi,divider = <1280>; + adi,digital-delay = <0>; + adi,analog-delay = <0>; + adi,sysref-mode = <0>; + adi,jesd204-sysref-chan; + }; +#endif /* !WITH_AION */ + channel@6 { + reg = <6>; + adi,extended-name = "JESD REF CLK 1"; // adsy1100_AD9084_RX_ref_clk + adi,divider = <10>; + adi,digital-delay = <0>; + adi,analog-delay = <0>; + }; + channel@7 { + reg = <7>; + adi,extended-name = "JESD REF CLK 2"; // adsy1100_AD9084_RX_ref_clk + adi,divider = <10>; + adi,digital-delay = <0>; + adi,analog-delay = <0>; + }; + }; + + ltc6948: ltc6948@1 { + #clock-cells = <0>; + compatible = "adi,ltc6948"; + reg = <1>; + spi-max-frequency = <5000000>; + clocks = <&clkin_125>; + clock-names = "clkin"; + clock-output-names = "ltc6948_out_clk"; + clock-scales = <1 10>; + }; + }; + +#if WITH_AION + adf4030_spi: spi@88260000 { + bits-per-word = <8>; + compatible = "xlnx,axi-quad-spi-3.2", "xlnx,xps-spi-2.00.a"; + fifo-size = <16>; + interrupt-names = "ip2intc_irpt"; + interrupt-parent = <&axi_intc_0>; + interrupts = <18 0>; + num-cs = <1>; + reg = <0x0 0x88260000 0x0 0x1000>; + xlnx,num-ss-bits = <0x2>; + xlnx,spi-mode = <0>; + + #address-cells = <1>; + #size-cells = <0>; + + adf4030: adf4030@0 { + #clock-cells = <1>; + compatible = "adi,adf4030"; + reg = <0>; + + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + spi-max-frequency = <1000000>; + adi,spi-3wire-enable; + + clocks = <&clkin_250>; + clock-names = "refin"; + clock-output-names = "adf4030_bsync_0", "adf4030_bsync_1", + "adf4030_bsync_2", "adf4030_bsync_3", "adf4030_bsync_4", + "adf4030_bsync_5", "adf4030_bsync_6", "adf4030_bsync_7", + "adf4030_bsync_8", "adf4030_bsync_9"; + label = "adf4030"; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-sysref-provider; + + adi,vco-frequency-hz = <2500000000>; /* 2.5 GHz */ + adi,bsync-frequency-hz = <9765625>; + adi,bsync-autoalign-reference-channel = <0>; + adi,bsync-autoalign-iteration-count = <6>; + adi,bsync-secondary-frequency-hz = <9765625>; + + channel@0 { + reg = <0>; + adi,extended-name = "ADF4030_BSYNC0"; + auto-align-on-sync-en; + adi,rcm = <62>; // LVDS + adi,link-rx-en; + adi,float-rx-en; + }; + channel@1 { + reg = <1>; + adi,extended-name = "BSYNC1_APOLLO_SYSREF"; + auto-align-on-sync-en; + adi,output-en; + adi,input-output-reconfig-en; + adi,rcm = <62>; // LVDS + adi,link-rx-en; + adi,float-rx-en; + }; + channel@2 { + reg = <2>; + adi,extended-name = "BSYNC2_JESD_SYSREF"; + auto-align-on-sync-en; + adi,output-en; + adi,input-output-reconfig-en; + adi,rcm = <62>; + adi,link-rx-en; + adi,float-rx-en; + }; + channel@9 { + reg = <9>; + adi,extended-name = "ADF4030_BSYNC9"; + adi,output-en; + auto-align-on-sync-en; + adi,input-output-reconfig-en; + adi,rcm = <62>; + }; + }; + }; +#endif /* WITH_AION */ + + + axi_gpio_0: gpio@88120000 { + #gpio-cells = <2>; + clock-frequency = <100000000>; + clock-names = "s_axi_aclk"; + clocks = <&mig_clkout1>; + compatible = "xlnx,axi-gpio-2.0", "xlnx,xps-gpio-1.00.a"; + gpio-controller ; + reg = <0x0 0x88120000 0x0 0x10000>; + xlnx,all-inputs = <0x0>; + xlnx,all-inputs-2 = <0x0>; + xlnx,all-outputs = <0x0>; + xlnx,all-outputs-2 = <0x0>; + xlnx,dout-default = <0x00000000>; + xlnx,dout-default-2 = <0x00000000>; + xlnx,gpio-width = <0x20>; + xlnx,gpio2-width = <0x20>; + xlnx,interrupt-present = <0x0>; + xlnx,is-dual = <0x1>; + xlnx,tri-default = <0xFFFFFFFF>; + xlnx,tri-default-2 = <0xFFFFFFFF>; + }; + + axi_gpio_1: gpio@88130000 { + #gpio-cells = <2>; + clock-frequency = <100000000>; + clock-names = "s_axi_aclk"; + clocks = <&mig_clkout1>; + compatible = "xlnx,axi-gpio-2.0", "xlnx,xps-gpio-1.00.a"; + gpio-controller ; + reg = <0x0 0x88130000 0x0 0x10000>; + xlnx,all-inputs = <0x0>; + xlnx,all-inputs-2 = <0x0>; + xlnx,all-outputs = <0x0>; + xlnx,all-outputs-2 = <0x0>; + xlnx,dout-default = <0x00000000>; + xlnx,dout-default-2 = <0x00000000>; + xlnx,gpio-width = <0x20>; + xlnx,gpio2-width = <0x20>; + xlnx,interrupt-present = <0x0>; + xlnx,is-dual = <0x1>; + xlnx,tri-default = <0xFFFFFFFF>; + xlnx,tri-default-2 = <0xFFFFFFFF>; + }; + + axi_gpio_2: gpio@88140000 { + #gpio-cells = <2>; + clock-frequency = <100000000>; + clock-names = "s_axi_aclk"; + clocks = <&mig_clkout1>; + compatible = "xlnx,axi-gpio-2.0", "xlnx,xps-gpio-1.00.a"; + gpio-controller; + reg = <0x0 0x88140000 0x0 0x10000>; + xlnx,all-inputs = <0x0>; + xlnx,all-inputs-2 = <0x0>; + xlnx,all-outputs = <0x0>; + xlnx,all-outputs-2 = <0x0>; + xlnx,dout-default = <0x00000000>; + xlnx,dout-default-2 = <0x00000000>; + xlnx,gpio-width = <0x20>; + xlnx,gpio2-width = <0x13>; + xlnx,interrupt-present = <0x0>; + xlnx,is-dual = <0x1>; + xlnx,tri-default = <0xFFFFFFFF>; + xlnx,tri-default-2 = <0xFFFFFFFF>; + }; + + axi_iic_main: i2c@88150000 { + clock-frequency = <100000000>; + clocks = <&mig_clkout1>; + compatible = "xlnx,axi-iic-2.1", "xlnx,xps-iic-2.00.a"; + interrupt-names = "iic2intc_irpt"; + interrupt-parent = <&axi_intc_0>; + interrupts = <1 2>; + reg = <0x0 0x88150000 0x0 0x10000>; + }; + + axi_sysid_0: axi_sysid@42000000 { + compatible = "adi,axi-sysid-1.00.a"; + reg = <0x0 0x88170000 0x0 0x1000>; + }; + + rx_dma: dma@88090000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x0 0x88090000 0x0 0x10000>; + #dma-cells = <1>; + #clock-cells = <0>; + interrupt-parent = <&axi_intc_0>; + interrupts = <3 2>; + clocks = <&mig_clkout1>; + memory-region = <&vu11p_ddr_dma>; + }; + + tx_dma: dma@880f0000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x0 0x880F0000 0x0 0x10000>; + #dma-cells = <1>; + #clock-cells = <0>; + interrupt-parent = <&axi_intc_0>; + interrupts = <4 2>; + clocks = <&mig_clkout1>; + memory-region = <&vu11p_ddr_dma>; + }; + + axi_data_offload_rx: data_offload_rx@88020000 { + compatible = "adi,axi-data-offload-1.0.a"; + reg = <0x0 0x88020000 0x0 0x10000>; + }; + + axi_data_offload_tx: data_offload_tx@88050000 { + compatible = "adi,axi-data-offload-1.0.a"; + reg = <0x0 0x88050000 0x0 0x10000>; + }; + + axi_ad9084_adxcvr_rx: axi-adxcvr-rx@880b0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "adi,axi-adxcvr-1.0"; + reg = <0x0 0x880B0000 0x0 0x1000>; + + clocks = <<c6952 7>; /* div40 is controlled by axi_ad9084_rx_jesd */ + clock-names = "conv"; + + #clock-cells = <1>; + clock-output-names = "rx_gt_clk", "rx_out_clk"; + + adi,sys-clk-select = ; + adi,out-clk-select = ; + adi,use-lpm-enable; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <<c6952 0 FRAMER_LINK_A0_RX>; + }; + + axi_ad9084_adxcvr_tx: axi-adxcvr-tx@88110000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "adi,axi-adxcvr-1.0"; + reg = <0x0 0x88110000 0x0 0x1000>; + + clocks = <<c6952 7>; /* div40 is controlled by axi_ad9084_tx_jesd */ + clock-names = "conv"; + + #clock-cells = <1>; + clock-output-names = "tx_gt_clk", "tx_out_clk"; + + adi,sys-clk-select = ; + adi,out-clk-select = ; /* XCVR_PROGDIV_CLK */ + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <<c6952 0 DEFRAMER_LINK_A0_TX>; + }; + + axi_ad9084_rx_jesd: axi-jesd204-rx@880a0000 { + compatible = "adi,axi-jesd204-rx-1.0"; + reg = <0x0 0x880a0000 0x0 0x1000>; + interrupt-parent = <&axi_intc_0>; + interrupts = <5 2>; + + clocks = <&mig_clkout1>, <&axi_ad9084_adxcvr_rx 1>, <<c6952 3>, <&axi_ad9084_adxcvr_rx 0>; + clock-names = "s_axi_aclk", "link_clk", "device_clk", "lane_clk"; + + #clock-cells = <0>; + clock-output-names = "jesd_rx_lane_clk"; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_adxcvr_rx 0 FRAMER_LINK_A0_RX>; + }; + + axi_ad9084_tx_jesd: axi-jesd204-tx@88100000 { + compatible = "adi,axi-jesd204-tx-1.0"; + reg = <0x0 0x88100000 0x0 0x1000>; + + interrupt-parent = <&axi_intc_0>; + interrupts = <6 2>; + + clocks = <&mig_clkout1>, <&axi_ad9084_adxcvr_tx 1>, <<c6952 3>, <&axi_ad9084_adxcvr_tx 0>; + clock-names = "s_axi_aclk", "link_clk", "device_clk", "lane_clk"; + + #clock-cells = <0>; + clock-output-names = "jesd_tx_lane_clk"; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_adxcvr_tx 0 DEFRAMER_LINK_A0_TX>; + }; + + apollo_spi: spi@88030000 { + bits-per-word = <8>; + compatible = "xlnx,axi-quad-spi-3.2", "xlnx,xps-spi-2.00.a"; + fifo-size = <16>; + interrupt-names = "ip2intc_irpt"; + interrupt-parent = <&axi_intc_0>; + interrupts = <7 0>; + num-cs = <1>; + reg = <0x0 0x88030000 0x0 0x1000>; + xlnx,num-ss-bits = <0x1>; + xlnx,spi-mode = <0>; + + #address-cells = <1>; + #size-cells = <0>; + + trx0_ad9084: ad9084@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "adi,ad9084"; + reg = <0>; + spi-max-frequency = <5000000>; + + /* Clocks */ + clocks = <&clkin_8000 0>; + clock-names = "dev_clk"; + dev_clk-clock-scales = <1 10>; + + clock-output-names = "rx_sampl_clk", "tx_sampl_clk"; + #clock-cells = <1>; + +#if HSCI_ENABLE + adi,axi-hsci-connected = <&axi_hsci>; + adi,hsci-auto-linkup-mode-en; + adi,hsci-disable-after-boot-en; +#endif + + jesd204-device; + #jesd204-cells = <2>; + jesd204-top-device = <0>; /* This is the TOP device */ + jesd204-ignore-errors; + +#ifdef ASYNM_A_B_MODE + jesd204-link-ids = ; + + jesd204-inputs = + <&axi_ad9084_core_rx 0 FRAMER_LINK_A0_RX>, + <&axi_ad9084_rx_jesd_b 0 FRAMER_LINK_B0_RX>, + <&axi_ad9084_core_tx 0 DEFRAMER_LINK_A0_TX>, + <&axi_ad9084_core_tx_b 0 DEFRAMER_LINK_B0_TX>; + + adi,side-b-use-seperate-tpl-en; +#else + jesd204-link-ids = ; + + jesd204-inputs = + <&axi_ad9084_core_rx 0 FRAMER_LINK_A0_RX>, + <&axi_ad9084_core_tx 0 DEFRAMER_LINK_A0_TX>; +#endif + + reset-gpios = <&axi_gpio_2 0x31 0>; + adi,device-profile-fw-name = DEVICE_PROFILE_NAME; + + adi,jrx0-physical-lane-mapping = <11 4 6 10 9 8 7 2 0 3 5 1>; + adi,jtx0-logical-lane-mapping = < 8 6 10 11 9 4 7 2 5 0 3 1>; + adi,jrx1-physical-lane-mapping = <3 1 5 0 7 2 8 6 4 9 10 11>; + adi,jtx1-logical-lane-mapping = <0 2 1 4 3 5 6 10 7 11 8 9>; + + adi,subclass = ; + +#if WITH_AION + io-channels = <&adf4030 1>, <&adf4382 0>; + io-channel-names = "bsync", "clk"; +#endif /* WITH_AION */ + + //adi,standalone-enable; + }; + + }; + + axi_ad9084_core_rx: axi-ad9084-rx-hpc@881b0000 { + compatible = "adi,axi-ad9081-rx-1.0"; + reg = <0x0 0x881B0000 0x0 0x1000>; + dmas = <&rx_dma 0>; + dma-names = "rx"; + spibus-connected = <&trx0_ad9084>; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_rx_jesd 0 FRAMER_LINK_A0_RX>; + }; + + axi_ad9084_core_tx: axi-ad9084-tx-hpc@881d0000 { + compatible = "adi,axi-ad9081-tx-1.0"; + reg = <0x0 0x881D0000 0x0 0x1000>; + dmas = <&tx_dma 0>; + dma-names = "tx"; + clocks = <&trx0_ad9084 1>; + clock-names = "sampl_clk"; + spibus-connected = <&trx0_ad9084>; + adi,axi-pl-fifo-enable; + adi,axi-data-offload-connected = <&axi_data_offload_tx>; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_tx_jesd 0 DEFRAMER_LINK_A0_TX>; + }; + +#if HSCI_ENABLE + hsci_clkgen: axi-clkgen@881F0000 { + compatible = "adi,axi-clkgen-2.00.a"; + reg = <0x0 0x881F0000 0x0 0x1000>; + #clock-cells = <0>; + clocks = <&mig_clkout1>, <&mig_clkout1>; + clock-names = "s_axi_aclk", "clkin1"; + clock-output-names = "hsci_clkgen"; + }; + + axi_hsci: axi_hsci@88200000 { + compatible = "adi,axi-hsci-1.0.a"; + reg = <0x0 0x88200000 0x0 0x40000>; + clocks = <&hsci_clkgen>; + clock-names = "pclk"; + adi,hsci-interface-speed-mhz = <800>; + }; +#endif + +#ifdef ASYNM_A_B_MODE + rx_dma_b: dma@88060000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x0 0x88060000 0x0 0x10000>; + #dma-cells = <1>; + #clock-cells = <0>; + interrupt-parent = <&axi_intc_0>; + interrupts = <10 2>; + clocks = <&mig_clkout1>; + memory-region = <&vu11p_ddr_dma>; + }; + + tx_dma_b: dma@880c0000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x0 0x880C0000 0x0 0x10000>; + #dma-cells = <1>; + #clock-cells = <0>; + interrupt-parent = <&axi_intc_0>; + interrupts = <11 2>; + clocks = <&mig_clkout1>; + memory-region = <&vu11p_ddr_dma>; + + }; + + axi_ad9084_core_rx_b: axi-ad9084b-rx-b@881c0000 { + compatible = "adi,axi-adc-tpl-so-10.0.a"; + reg = <0x0 0x881C0000 0x0 0x10000>; + dmas = <&rx_dma_b 0>; + dma-names = "rx"; + clocks = <&trx0_ad9084 0>; /* FIXME */ + clock-names = "sampl_clk"; + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_rx_jesd_b 0 FRAMER_LINK_B0_RX>; + }; + + axi_ad9084_core_tx_b: axi-ad9084-tx-b@881e0000 { + compatible = "adi,axi-ad9081-tx-1.0"; + reg = <0x0 0x881E0000 0x0 0x10000>; + dmas = <&tx_dma_b 0>; + dma-names = "tx"; + clocks = <&trx0_ad9084 1>; /* FIXME */ + clock-names = "sampl_clk"; + adi,axi-pl-fifo-enable; + adi,axi-data-offload-connected = <&axi_data_offload_tx_b>; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_tx_jesd_b 0 DEFRAMER_LINK_B0_TX>; + }; + + axi_ad9084_rx_jesd_b: axi-jesd204-rx-b@88070000 { + compatible = "adi,axi-jesd204-rx-1.0"; + reg = <0x0 0x88070000 0x0 0x10000>; + + interrupt-parent = <&axi_intc_0>; + interrupts = <12 2>; + + clocks = <&mig_clkout1>, <&axi_ad9084_adxcvr_rx_b 1>, <<c6952 3>, <&axi_ad9084_adxcvr_rx_b 0>; + clock-names = "s_axi_aclk", "link_clk", "device_clk", "lane_clk"; + + #clock-cells = <0>; + clock-output-names = "jesd_rx_lane_clk_b"; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_adxcvr_rx_b 0 FRAMER_LINK_B0_RX>; + }; + + axi_ad9084_tx_jesd_b: axi-jesd204-tx-b@880d0000 { + compatible = "adi,axi-jesd204-tx-1.0"; + reg = <0x0 0x880D0000 0x0 0x10000>; + + interrupt-parent = <&axi_intc_0>; + interrupts = <13 2>; + + clocks = <&mig_clkout1>, <&axi_ad9084_adxcvr_tx_b 1>, <<c6952 3>, <&axi_ad9084_adxcvr_tx_b 0>; + clock-names = "s_axi_aclk", "link_clk", "device_clk", "lane_clk"; + + #clock-cells = <0>; + clock-output-names = "jesd_tx_lane_clk_b"; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_adxcvr_tx_b 0 DEFRAMER_LINK_B0_TX>; + }; + + axi_ad9084_adxcvr_rx_b: axi-adxcvr-rx-b@88080000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "adi,axi-adxcvr-1.0"; + reg = <0x0 0x88080000 0x0 0x10000>; + + clocks = <<c6952 6>; /* div40 is controlled by axi_ad9084_rx_jesd */ + clock-names = "conv"; + + #clock-cells = <1>; + clock-output-names = "rx_gt_clk_b", "rx_out_clk_b"; + + adi,sys-clk-select = ; + adi,out-clk-select = ; + adi,use-lpm-enable; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <<c6952 0 FRAMER_LINK_B0_RX>; + }; + + axi_ad9084_adxcvr_tx_b: axi-adxcvr-tx-b@880e0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "adi,axi-adxcvr-1.0"; + reg = <0x0 0x880E0000 0x0 0x10000>; + + clocks = <<c6952 6>; /* div40 is controlled by axi_ad9084_tx_jesd */ + clock-names = "conv"; + + #clock-cells = <1>; + clock-output-names = "tx_gt_clk_b", "tx_out_clk_b"; + + adi,sys-clk-select = ; + adi,out-clk-select = ; /* XCVR_PROGDIV_CLK */ + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <<c6952 0 DEFRAMER_LINK_B0_TX>; + }; + + axi_data_offload_rx_b: data_offload_rx_b@88010000 { + compatible = "adi,axi-data-offload-1.0.a"; + reg = <0x0 0x88010000 0x0 0x10000>; + }; + + axi_data_offload_tx_b: data_offload_tx_b@88040000 { + compatible = "adi,axi-data-offload-1.0.a"; + reg = <0x0 0x88040000 0x0 0x10000>; + }; +#endif /* ASYNM_A_B_MODE */ + + rfpc_one_bit_adc_dac: one-bit-adc-dac@0 { + compatible = "adi,one-bit-adc-dac"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/xilinx/vu11p-ad9084-vpx-revb-204C_M4_L8_NP16_8p0_4x2.dtso b/arch/arm64/boot/dts/xilinx/vu11p-ad9084-vpx-revb-204C_M4_L8_NP16_8p0_4x2.dtso new file mode 100644 index 00000000000000..079cce29a1eb42 --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/vu11p-ad9084-vpx-revb-204C_M4_L8_NP16_8p0_4x2.dtso @@ -0,0 +1,807 @@ +/dts-v1/; +/plugin/; + +#include +#include + +#ifndef DEVICE_PROFILE_NAME +#define DEVICE_PROFILE_NAME "204C_M4_L8_NP16_8p0_4x2.bin" +#endif + +#ifndef OUT_CLK_SELECT +#define OUT_CLK_SELECT XCVR_PROGDIV_CLK +#endif + +#ifndef ASYNM_A_B_MODE +#define ASYNM_A_B_MODE 1 +#endif + +#ifndef HSCI_ENABLE +#define HSCI_ENABLE 1 +#endif + +#ifndef VU11_FIRMWARE_NAME +#define VU11_FIRMWARE_NAME "vu11p.bin" +#endif + +#ifdef WITH_AION +#define JESD_SUBCLASS 1 +#else +#define JESD_SUBCLASS 0 +#endif + +&vu11p_fpga_region { + #address-cells = <2>; + #size-cells = <2>; + + firmware-name = VU11_FIRMWARE_NAME; + + mig_clkout1: clock@0 { + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "vu11p_mig_1"; + compatible = "fixed-clock"; + }; + + clkin_125: clock@1 { + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "clkin_ref"; + compatible = "fixed-clock"; + }; + + clkin_62p5: clock@2 { + #clock-cells = <0>; + clock-frequency = <62500000>; + clock-output-names = "clkin_div2_ref"; + compatible = "fixed-clock"; + }; + + clkin_250: clock@3 { + #clock-cells = <0>; + clock-frequency = <250000000>; + clock-output-names = "clkin_mul2_ref"; + compatible = "fixed-clock"; + }; + + axi_intc_0: interrupt-controller@88160000 { + #interrupt-cells = <2>; + clock-names = "mig_clkout1"; + clocks = <&mig_clkout1>; + compatible = "xlnx,axi-intc-4.1", "xlnx,xps-intc-1.00.a"; + interrupt-controller; + interrupt-names = "irq"; + interrupt-parent = <&gic>; + interrupts = <0 104 4>; + reg = <0x0 0x88160000 0x0 0x1000>; + xlnx,kind-of-intr = <0xffe0385>; + xlnx,num-intr-inputs = <19>; + }; + + adf4382_spi: spi@88000000 { + bits-per-word = <8>; + compatible = "xlnx,axi-quad-spi-3.2", "xlnx,xps-spi-2.00.a"; + fifo-size = <16>; + interrupt-names = "ip2intc_irpt"; + interrupt-parent = <&axi_intc_0>; + interrupts = <8 0>; + num-cs = <0x1>; + reg = <0x0 0x88000000 0x0 0x1000>; + xlnx,num-ss-bits = <0x1>; + xlnx,spi-mode = <0>; + + #address-cells = <1>; + #size-cells = <0>; + adf4382: adf4382@0 { + #clock-cells = <1>; + compatible = "adi,adf4382"; + reg = <0>; + spi-max-frequency = <1000000>; + clocks = <&clkin_62p5>; + clock-names = "ref_clk"; + adi,ref-doubler-enable; + clock-output-names = "adf4382_out_clk"; + adi,power-up-frequency = /bits/ 64 <8000000000>; + }; + }; + + ltc6952_spi: spi@881a0000 { + bits-per-word = <8>; + compatible = "xlnx,axi-quad-spi-3.2", "xlnx,xps-spi-2.00.a"; + fifo-size = <16>; + interrupt-names = "ip2intc_irpt"; + interrupt-parent = <&axi_intc_0>; + interrupts = <9 0>; + num-cs = <2>; + reg = <0x0 0x881A0000 0x0 0x1000>; + xlnx,num-ss-bits = <0x2>; + xlnx,spi-mode = <0>; + + #address-cells = <1>; + #size-cells = <0>; + + ltc6952: ltc6952@0 { + compatible = "adi,ltc6952"; + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <10000000>; + label = "ltc6952"; + + clocks = <&clkin_125> , <<c6948>; + clock-names = "clkin", "vcoin"; + vcoin-clock-scales = <1 10>; + + adi,vco-frequency-hz = <2500000000>; + + jesd204-device; + #jesd204-cells = <2>; +#if WITH_AION + jesd204-inputs = + <&adf4030 0 FRAMER_LINK_A0_RX>, + <&adf4030 0 DEFRAMER_LINK_A0_TX>; +#else + jesd204-sysref-provider; +#endif /* WITH_AION */ + + clock-output-names = "ltc6952_0_out0", "ltc6952_0_out1", + "ltc6952_0_out2", "ltc6952_0_out3", "ltc6952_0_out4", + "ltc6952_0_out5", "ltc6952_0_out6", "ltc6952_0_out7", + "ltc6952_0_out8", "ltc6952_0_out9", "ltc6952_0_out10"; + + #clock-cells = <1>; + + adi,pulse-generator-mode = <2>; /* Four Pulses */ +#if WITH_AION + channel@0 { + reg = <0>; + adi,extended-name = "ADF4030_BSYNC0"; + adi,divider = <256>; + adi,digital-delay = <0>; + adi,analog-delay = <0>; + }; +#endif /* WITH_AION */ + // channel@1 { + // reg = <1>; + // adi,extended-name = "Aurora RF GTH"; + // adi,divider = <6>; + // adi,digital-delay = <0>; + // adi,analog-delay = <0>; + // }; + // channel@2 { + // reg = <2>; + // adi,extended-name = "Apollo PLL REF CLK"; + // adi,divider = <6>; + // adi,digital-delay = <0>; + // adi,analog-delay = <0>; + // adi,sysref-mode = <0>; + // adi,jesd204-sysref-chan; + // }; + channel@3 { + reg = <3>; + adi,extended-name = "VUP Core CLK"; + adi,divider = <20>; + adi,digital-delay = <0>; + adi,analog-delay = <0>; + }; +#ifndef WITH_AION + channel@4 { + reg = <4>; + adi,extended-name = "VUP JESD SYSREF"; + adi,divider = <768>; + adi,digital-delay = <0>; + adi,analog-delay = <0>; + adi,sysref-mode = <0>; + adi,jesd204-sysref-chan; + }; + channel@5 { + reg = <5>; + adi,extended-name = "Apollo SYSREF"; + adi,divider = <768>; + adi,digital-delay = <0>; + adi,analog-delay = <0>; + adi,sysref-mode = <0>; + adi,jesd204-sysref-chan; + }; +#endif /* !WITH_AION */ + channel@6 { + reg = <6>; + adi,extended-name = "JESD REF CLK 1"; + adi,divider = <10>; + adi,digital-delay = <0>; + adi,analog-delay = <0>; + }; + channel@7 { + reg = <7>; + adi,extended-name = "JESD REF CLK 2"; + adi,divider = <10>; + adi,digital-delay = <0>; + adi,analog-delay = <0>; + }; + // channel@8 { + // reg = <8>; + // adi,extended-name = "REF CLL RFPC"; + // adi,divider = <6>; + // adi,digital-delay = <0>; + // adi,analog-delay = <0>; + // }; + // channel@9 { + // reg = <9>; + // adi,extended-name = "SYNC RFPC"; + // adi,divider = <6>; + // adi,digital-delay = <0>; + // adi,analog-delay = <0>; + // }; + // channel@10 { + // reg = <10>; + // adi,extended-name = "Auroro RF GTY"; + // adi,divider = <6>; + // adi,digital-delay = <0>; + // adi,analog-delay = <0>; + // }; + }; + + ltc6948: ltc6948@1 { + #clock-cells = <0>; + compatible = "adi,ltc6948"; + reg = <1>; + spi-max-frequency = <5000000>; + clocks = <&clkin_125>; + clock-names = "clkin"; + clock-output-names = "ltc6948_out_clk"; + clock-scales = <1 10>; + }; + }; + +#if WITH_AION + adf4030_spi: spi@88260000 { + bits-per-word = <8>; + compatible = "xlnx,axi-quad-spi-3.2", "xlnx,xps-spi-2.00.a"; + fifo-size = <16>; + interrupt-names = "ip2intc_irpt"; + interrupt-parent = <&axi_intc_0>; + interrupts = <18 0>; + num-cs = <1>; + reg = <0x0 0x88260000 0x0 0x1000>; + xlnx,num-ss-bits = <0x2>; + xlnx,spi-mode = <0>; + + #address-cells = <1>; + #size-cells = <0>; + + adf4030: adf4030@0 { + #clock-cells = <1>; + compatible = "adi,adf4030"; + reg = <0>; + + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + spi-max-frequency = <1000000>; + adi,spi-3wire-enable; + + clocks = <&clkin_250>; + clock-names = "refin"; + clock-output-names = "adf4030_bsync_0", "adf4030_bsync_1", + "adf4030_bsync_2", "adf4030_bsync_3", "adf4030_bsync_4", + "adf4030_bsync_5", "adf4030_bsync_6", "adf4030_bsync_7", + "adf4030_bsync_8", "adf4030_bsync_9"; + label = "adf4030"; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-sysref-provider; + + adi,vco-frequency-hz = <2500000000>; /* 2.5 GHz */ + adi,bsync-frequency-hz = <9765625>; + adi,bsync-autoalign-reference-channel = <0>; + adi,bsync-autoalign-iteration-count = <6>; + adi,bsync-secondary-frequency-hz = <9765625>; + + channel@0 { + reg = <0>; + adi,extended-name = "ADF4030_BSYNC0"; + auto-align-on-sync-en; + adi,rcm = <62>; // LVDS + adi,link-rx-en; + adi,float-rx-en; + }; + channel@1 { + reg = <1>; + adi,extended-name = "BSYNC1_APOLLO_SYSREF"; + auto-align-on-sync-en; + adi,output-en; + adi,input-output-reconfig-en; + adi,rcm = <62>; // LVDS + adi,link-rx-en; + adi,float-rx-en; + }; + channel@2 { + reg = <2>; + adi,extended-name = "BSYNC2_JESD_SYSREF"; + auto-align-on-sync-en; + adi,output-en; + adi,input-output-reconfig-en; + adi,rcm = <62>; + adi,link-rx-en; + adi,float-rx-en; + }; + channel@9 { + reg = <9>; + adi,extended-name = "ADF4030_BSYNC9"; + adi,output-en; + auto-align-on-sync-en; + adi,input-output-reconfig-en; + adi,rcm = <62>; + }; + }; + }; +#endif /* WITH_AION */ + + + axi_gpio_0: gpio@88120000 { + #gpio-cells = <2>; + clock-frequency = <100000000>; + clock-names = "s_axi_aclk"; + clocks = <&mig_clkout1>; + compatible = "xlnx,axi-gpio-2.0", "xlnx,xps-gpio-1.00.a"; + gpio-controller ; + reg = <0x0 0x88120000 0x0 0x10000>; + xlnx,all-inputs = <0x0>; + xlnx,all-inputs-2 = <0x0>; + xlnx,all-outputs = <0x0>; + xlnx,all-outputs-2 = <0x0>; + xlnx,dout-default = <0x00000000>; + xlnx,dout-default-2 = <0x00000000>; + xlnx,gpio-width = <0x20>; + xlnx,gpio2-width = <0x20>; + xlnx,interrupt-present = <0x0>; + xlnx,is-dual = <0x1>; + xlnx,tri-default = <0xFFFFFFFF>; + xlnx,tri-default-2 = <0xFFFFFFFF>; + }; + + axi_gpio_1: gpio@88130000 { + #gpio-cells = <2>; + clock-frequency = <100000000>; + clock-names = "s_axi_aclk"; + clocks = <&mig_clkout1>; + compatible = "xlnx,axi-gpio-2.0", "xlnx,xps-gpio-1.00.a"; + gpio-controller ; + reg = <0x0 0x88130000 0x0 0x10000>; + xlnx,all-inputs = <0x0>; + xlnx,all-inputs-2 = <0x0>; + xlnx,all-outputs = <0x0>; + xlnx,all-outputs-2 = <0x0>; + xlnx,dout-default = <0x00000000>; + xlnx,dout-default-2 = <0x00000000>; + xlnx,gpio-width = <0x20>; + xlnx,gpio2-width = <0x20>; + xlnx,interrupt-present = <0x0>; + xlnx,is-dual = <0x1>; + xlnx,tri-default = <0xFFFFFFFF>; + xlnx,tri-default-2 = <0xFFFFFFFF>; + }; + + axi_gpio_2: gpio@88140000 { + #gpio-cells = <2>; + clock-frequency = <100000000>; + clock-names = "s_axi_aclk"; + clocks = <&mig_clkout1>; + compatible = "xlnx,axi-gpio-2.0", "xlnx,xps-gpio-1.00.a"; + gpio-controller; + reg = <0x0 0x88140000 0x0 0x10000>; + xlnx,all-inputs = <0x0>; + xlnx,all-inputs-2 = <0x0>; + xlnx,all-outputs = <0x0>; + xlnx,all-outputs-2 = <0x0>; + xlnx,dout-default = <0x00000000>; + xlnx,dout-default-2 = <0x00000000>; + xlnx,gpio-width = <0x20>; + xlnx,gpio2-width = <0x13>; + xlnx,interrupt-present = <0x0>; + xlnx,is-dual = <0x1>; + xlnx,tri-default = <0xFFFFFFFF>; + xlnx,tri-default-2 = <0xFFFFFFFF>; + }; + + axi_iic_main: i2c@88150000 { + clock-frequency = <100000000>; + clocks = <&mig_clkout1>; + compatible = "xlnx,axi-iic-2.1", "xlnx,xps-iic-2.00.a"; + interrupt-names = "iic2intc_irpt"; + interrupt-parent = <&axi_intc_0>; + interrupts = <1 2>; + reg = <0x0 0x88150000 0x0 0x10000>; + }; + + axi_sysid_0: axi_sysid@42000000 { + compatible = "adi,axi-sysid-1.00.a"; + reg = <0x0 0x88170000 0x0 0x1000>; + }; + + rx_dma: dma@88090000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x0 0x88090000 0x0 0x10000>; + #dma-cells = <1>; + #clock-cells = <0>; + interrupt-parent = <&axi_intc_0>; + interrupts = <3 2>; + clocks = <&mig_clkout1>; + memory-region = <&vu11p_ddr_dma>; + }; + + tx_dma: dma@880f0000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x0 0x880F0000 0x0 0x10000>; + #dma-cells = <1>; + #clock-cells = <0>; + interrupt-parent = <&axi_intc_0>; + interrupts = <4 2>; + clocks = <&mig_clkout1>; + memory-region = <&vu11p_ddr_dma>; + }; + + axi_data_offload_rx: data_offload_rx@88020000 { + compatible = "adi,axi-data-offload-1.0.a"; + reg = <0x0 0x88020000 0x0 0x10000>; + }; + + axi_data_offload_tx: data_offload_tx@88050000 { + compatible = "adi,axi-data-offload-1.0.a"; + reg = <0x0 0x88050000 0x0 0x10000>; + }; + + axi_ad9084_adxcvr_rx: axi-adxcvr-rx@880b0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "adi,axi-adxcvr-1.0"; + reg = <0x0 0x880B0000 0x0 0x1000>; + + clocks = <<c6952 7>; /* div40 is controlled by axi_ad9084_rx_jesd */ + clock-names = "conv"; + + #clock-cells = <1>; + clock-output-names = "rx_gt_clk", "rx_out_clk"; + + adi,sys-clk-select = ; + adi,out-clk-select = ; + adi,use-lpm-enable; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <<c6952 0 FRAMER_LINK_A0_RX>; + }; + + axi_ad9084_adxcvr_tx: axi-adxcvr-tx@88110000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "adi,axi-adxcvr-1.0"; + reg = <0x0 0x88110000 0x0 0x1000>; + + clocks = <<c6952 7>; /* div40 is controlled by axi_ad9084_tx_jesd */ + clock-names = "conv"; + + #clock-cells = <1>; + clock-output-names = "tx_gt_clk", "tx_out_clk"; + + adi,sys-clk-select = ; + adi,out-clk-select = ; /* XCVR_PROGDIV_CLK */ + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <<c6952 0 DEFRAMER_LINK_A0_TX>; + }; + + axi_ad9084_rx_jesd: axi-jesd204-rx@880a0000 { + compatible = "adi,axi-jesd204-rx-1.0"; + reg = <0x0 0x880a0000 0x0 0x1000>; + interrupt-parent = <&axi_intc_0>; + interrupts = <5 2>; + + clocks = <&mig_clkout1>, <&axi_ad9084_adxcvr_rx 1>, <<c6952 3>, <&axi_ad9084_adxcvr_rx 0>; + clock-names = "s_axi_aclk", "link_clk", "device_clk", "lane_clk"; + + #clock-cells = <0>; + clock-output-names = "jesd_rx_lane_clk"; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_adxcvr_rx 0 FRAMER_LINK_A0_RX>; + }; + + axi_ad9084_tx_jesd: axi-jesd204-tx@88100000 { + compatible = "adi,axi-jesd204-tx-1.0"; + reg = <0x0 0x88100000 0x0 0x1000>; + + interrupt-parent = <&axi_intc_0>; + interrupts = <6 2>; + + clocks = <&mig_clkout1>, <&axi_ad9084_adxcvr_tx 1>, <<c6952 3>, <&axi_ad9084_adxcvr_tx 0>; + clock-names = "s_axi_aclk", "link_clk", "device_clk", "lane_clk"; + + #clock-cells = <0>; + clock-output-names = "jesd_tx_lane_clk"; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_adxcvr_tx 0 DEFRAMER_LINK_A0_TX>; + }; + + apollo_spi: spi@88030000 { + bits-per-word = <8>; + compatible = "xlnx,axi-quad-spi-3.2", "xlnx,xps-spi-2.00.a"; + fifo-size = <16>; + interrupt-names = "ip2intc_irpt"; + interrupt-parent = <&axi_intc_0>; + interrupts = <7 0>; + num-cs = <1>; + reg = <0x0 0x88030000 0x0 0x1000>; + xlnx,num-ss-bits = <0x1>; + xlnx,spi-mode = <0>; + + #address-cells = <1>; + #size-cells = <0>; + + trx0_ad9084: ad9084@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "adi,ad9084"; + reg = <0>; + spi-max-frequency = <5000000>; + + /* Clocks */ + clocks = <&adf4382 0>; + clock-names = "dev_clk"; + dev_clk-clock-scales = <1 10>; + + clock-output-names = "rx_sampl_clk", "tx_sampl_clk"; + #clock-cells = <1>; + + // interrupt-names = "fft_done_A", "fft_done_B"; + // interrupt-parent = <&axi_gpio>; + // interrupts = <17 1 18 1>; + +#if HSCI_ENABLE + adi,axi-hsci-connected = <&axi_hsci>; + adi,hsci-auto-linkup-mode-en; + adi,hsci-disable-after-boot-en; +#endif + + jesd204-device; + #jesd204-cells = <2>; + jesd204-top-device = <0>; /* This is the TOP device */ + jesd204-ignore-errors; + +#ifdef ASYNM_A_B_MODE + jesd204-link-ids = ; + + jesd204-inputs = + <&axi_ad9084_core_rx 0 FRAMER_LINK_A0_RX>, + <&axi_ad9084_rx_jesd_b 0 FRAMER_LINK_B0_RX>, + <&axi_ad9084_core_tx 0 DEFRAMER_LINK_A0_TX>, + <&axi_ad9084_core_tx_b 0 DEFRAMER_LINK_B0_TX>; + + adi,side-b-use-seperate-tpl-en; +#else + jesd204-link-ids = ; + + jesd204-inputs = + <&axi_ad9084_core_rx 0 FRAMER_LINK_A0_RX>, + <&axi_ad9084_core_tx 0 DEFRAMER_LINK_A0_TX>; +#endif + + reset-gpios = <&axi_gpio_2 0x31 0>; + adi,device-profile-fw-name = DEVICE_PROFILE_NAME; + + adi,jrx0-physical-lane-mapping = <11 4 6 10 9 8 7 2 0 3 5 1>; + adi,jtx0-logical-lane-mapping = < 8 6 10 11 9 4 7 2 5 0 3 1>; + adi,jrx1-physical-lane-mapping = <3 1 5 0 7 2 8 6 4 9 10 11>; + adi,jtx1-logical-lane-mapping = <0 2 1 4 3 5 6 10 7 11 8 9>; + + adi,subclass = ; + +#if WITH_AION + io-channels = <&adf4030 1>, <&adf4382 0>; + io-channel-names = "bsync", "clk"; +#endif /* WITH_AION */ + + //adi,standalone-enable; + }; + + }; + + axi_ad9084_core_rx: axi-ad9084-rx-hpc@881b0000 { + compatible = "adi,axi-ad9081-rx-1.0"; + reg = <0x0 0x881B0000 0x0 0x1000>; + dmas = <&rx_dma 0>; + dma-names = "rx"; + spibus-connected = <&trx0_ad9084>; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_rx_jesd 0 FRAMER_LINK_A0_RX>; + }; + + axi_ad9084_core_tx: axi-ad9084-tx-hpc@881d0000 { + compatible = "adi,axi-ad9081-tx-1.0"; + reg = <0x0 0x881D0000 0x0 0x1000>; + dmas = <&tx_dma 0>; + dma-names = "tx"; + clocks = <&trx0_ad9084 1>; + clock-names = "sampl_clk"; + spibus-connected = <&trx0_ad9084>; + adi,axi-pl-fifo-enable; + adi,axi-data-offload-connected = <&axi_data_offload_tx>; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_tx_jesd 0 DEFRAMER_LINK_A0_TX>; + }; + +#if HSCI_ENABLE + hsci_clkgen: axi-clkgen@881F0000 { + compatible = "adi,axi-clkgen-2.00.a"; + reg = <0x0 0x881F0000 0x0 0x1000>; + #clock-cells = <0>; + clocks = <&mig_clkout1>, <&mig_clkout1>; + clock-names = "s_axi_aclk", "clkin1"; + clock-output-names = "hsci_clkgen"; + }; + + axi_hsci: axi_hsci@88200000 { + compatible = "adi,axi-hsci-1.0.a"; + reg = <0x0 0x88200000 0x0 0x40000>; + clocks = <&hsci_clkgen>; + clock-names = "pclk"; + adi,hsci-interface-speed-mhz = <800>; + }; +#endif + +#ifdef ASYNM_A_B_MODE + rx_dma_b: dma@88060000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x0 0x88060000 0x0 0x10000>; + #dma-cells = <1>; + #clock-cells = <0>; + interrupt-parent = <&axi_intc_0>; + interrupts = <10 2>; + clocks = <&mig_clkout1>; + memory-region = <&vu11p_ddr_dma>; + }; + + tx_dma_b: dma@880c0000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x0 0x880C0000 0x0 0x10000>; + #dma-cells = <1>; + #clock-cells = <0>; + interrupt-parent = <&axi_intc_0>; + interrupts = <11 2>; + clocks = <&mig_clkout1>; + memory-region = <&vu11p_ddr_dma>; + + }; + + axi_ad9084_core_rx_b: axi-ad9084b-rx-b@881c0000 { + compatible = "adi,axi-adc-tpl-so-10.0.a"; + reg = <0x0 0x881C0000 0x0 0x10000>; + dmas = <&rx_dma_b 0>; + dma-names = "rx"; + clocks = <&trx0_ad9084 0>; /* FIXME */ + clock-names = "sampl_clk"; + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_rx_jesd_b 0 FRAMER_LINK_B0_RX>; + }; + + axi_ad9084_core_tx_b: axi-ad9084-tx-b@881e0000 { + compatible = "adi,axi-ad9081-tx-1.0"; + reg = <0x0 0x881E0000 0x0 0x10000>; + dmas = <&tx_dma_b 0>; + dma-names = "tx"; + clocks = <&trx0_ad9084 1>; /* FIXME */ + clock-names = "sampl_clk"; + adi,axi-pl-fifo-enable; + adi,axi-data-offload-connected = <&axi_data_offload_tx_b>; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_tx_jesd_b 0 DEFRAMER_LINK_B0_TX>; + }; + + axi_ad9084_rx_jesd_b: axi-jesd204-rx-b@88070000 { + compatible = "adi,axi-jesd204-rx-1.0"; + reg = <0x0 0x88070000 0x0 0x10000>; + + interrupt-parent = <&axi_intc_0>; + interrupts = <12 2>; + + clocks = <&mig_clkout1>, <&axi_ad9084_adxcvr_rx_b 1>, <<c6952 3>, <&axi_ad9084_adxcvr_rx_b 0>; + clock-names = "s_axi_aclk", "link_clk", "device_clk", "lane_clk"; + + #clock-cells = <0>; + clock-output-names = "jesd_rx_lane_clk_b"; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_adxcvr_rx_b 0 FRAMER_LINK_B0_RX>; + }; + + axi_ad9084_tx_jesd_b: axi-jesd204-tx-b@880d0000 { + compatible = "adi,axi-jesd204-tx-1.0"; + reg = <0x0 0x880D0000 0x0 0x10000>; + + interrupt-parent = <&axi_intc_0>; + interrupts = <13 2>; + + clocks = <&mig_clkout1>, <&axi_ad9084_adxcvr_tx_b 1>, <<c6952 3>, <&axi_ad9084_adxcvr_tx_b 0>; + clock-names = "s_axi_aclk", "link_clk", "device_clk", "lane_clk"; + + #clock-cells = <0>; + clock-output-names = "jesd_tx_lane_clk_b"; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_adxcvr_tx_b 0 DEFRAMER_LINK_B0_TX>; + }; + + axi_ad9084_adxcvr_rx_b: axi-adxcvr-rx-b@88080000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "adi,axi-adxcvr-1.0"; + reg = <0x0 0x88080000 0x0 0x10000>; + + clocks = <<c6952 6>; /* div40 is controlled by axi_ad9084_rx_jesd */ + clock-names = "conv"; + + #clock-cells = <1>; + clock-output-names = "rx_gt_clk_b", "rx_out_clk_b"; + + adi,sys-clk-select = ; + adi,out-clk-select = ; + adi,use-lpm-enable; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <<c6952 0 FRAMER_LINK_B0_RX>; + }; + + axi_ad9084_adxcvr_tx_b: axi-adxcvr-tx-b@880e0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "adi,axi-adxcvr-1.0"; + reg = <0x0 0x880E0000 0x0 0x10000>; + + clocks = <<c6952 6>; /* div40 is controlled by axi_ad9084_tx_jesd */ + clock-names = "conv"; + + #clock-cells = <1>; + clock-output-names = "tx_gt_clk_b", "tx_out_clk_b"; + + adi,sys-clk-select = ; + adi,out-clk-select = ; /* XCVR_PROGDIV_CLK */ + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <<c6952 0 DEFRAMER_LINK_B0_TX>; + }; + + axi_data_offload_rx_b: data_offload_rx_b@88010000 { + compatible = "adi,axi-data-offload-1.0.a"; + reg = <0x0 0x88010000 0x0 0x10000>; + }; + + axi_data_offload_tx_b: data_offload_tx_b@88040000 { + compatible = "adi,axi-data-offload-1.0.a"; + reg = <0x0 0x88040000 0x0 0x10000>; + }; +#endif /* ASYNM_A_B_MODE */ + + rfpc_one_bit_adc_dac: one-bit-adc-dac@0 { + compatible = "adi,one-bit-adc-dac"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; +}; \ No newline at end of file diff --git a/arch/arm64/boot/dts/xilinx/vu11p-ad9084-vpx-revb.dtso b/arch/arm64/boot/dts/xilinx/vu11p-ad9084-vpx-revb.dtso new file mode 100644 index 00000000000000..bb0e11f47cd9b1 --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/vu11p-ad9084-vpx-revb.dtso @@ -0,0 +1,769 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; +/plugin/; + +#include +#include + +#ifndef DEVICE_PROFILE_NAME +#define DEVICE_PROFILE_NAME "204C_M4_L8_NP16_2p5_4x2.bin" +#endif + +#ifndef OUT_CLK_SELECT +#define OUT_CLK_SELECT XCVR_PROGDIV_CLK +#endif + +#ifndef ASYNM_A_B_MODE +#define ASYNM_A_B_MODE 1 +#endif + +#ifndef HSCI_ENABLE +#define HSCI_ENABLE 1 +#endif + +#ifndef WITH_AION +#define WITH_AION 1 +#endif + +#ifndef VU11_FIRMWARE_NAME +#define VU11_FIRMWARE_NAME "vu11p.bin" +#endif + +#ifdef WITH_AION +#define JESD_SUBCLASS 1 +#else +#define JESD_SUBCLASS 0 +#endif + +&vu11p_fpga_region { + #address-cells = <2>; + #size-cells = <2>; + + firmware-name = VU11_FIRMWARE_NAME; + + mig_clkout1: clock@0 { + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "vu11p_mig_1"; + compatible = "fixed-clock"; + }; + + clkin_125: clock@1 { + #clock-cells = <0>; + clock-frequency = <125000000>; + clock-output-names = "clkin_ref"; + compatible = "fixed-clock"; + }; + + clkin_62p5: clock@2 { + #clock-cells = <0>; + clock-frequency = <62500000>; + clock-output-names = "clkin_div2_ref"; + compatible = "fixed-clock"; + }; + + clkin_250: clock@3 { + #clock-cells = <0>; + clock-frequency = <250000000>; + clock-output-names = "clkin_mul2_ref"; + compatible = "fixed-clock"; + }; + + axi_intc_0: interrupt-controller@88160000 { + #interrupt-cells = <2>; + clock-names = "mig_clkout1"; + clocks = <&mig_clkout1>; + compatible = "xlnx,axi-intc-4.1", "xlnx,xps-intc-1.00.a"; + interrupt-controller; + interrupt-names = "irq"; + interrupt-parent = <&gic>; + interrupts = <0 104 4>; + reg = <0x0 0x88160000 0x0 0x1000>; + xlnx,kind-of-intr = <0xffe0385>; + xlnx,num-intr-inputs = <19>; + }; + + adf4382_spi: spi@88000000 { + bits-per-word = <8>; + compatible = "xlnx,axi-quad-spi-3.2", "xlnx,xps-spi-2.00.a"; + fifo-size = <16>; + interrupt-names = "ip2intc_irpt"; + interrupt-parent = <&axi_intc_0>; + interrupts = <8 0>; + num-cs = <0x1>; + reg = <0x0 0x88000000 0x0 0x1000>; + xlnx,num-ss-bits = <0x1>; + xlnx,spi-mode = <0>; + + #address-cells = <1>; + #size-cells = <0>; + adf4382: adf4382@0 { + #clock-cells = <1>; + compatible = "adi,adf4382"; + reg = <0>; + spi-max-frequency = <1000000>; + clocks = <&clkin_62p5>; + clock-names = "ref_clk"; + adi,ref-doubler-enable; + clock-output-names = "adf4382_out_clk"; + adi,power-up-frequency = /bits/ 64 <20000000000>; + }; + }; + + ltc6952_spi: spi@881a0000 { + bits-per-word = <8>; + compatible = "xlnx,axi-quad-spi-3.2", "xlnx,xps-spi-2.00.a"; + fifo-size = <16>; + interrupt-names = "ip2intc_irpt"; + interrupt-parent = <&axi_intc_0>; + interrupts = <9 0>; + num-cs = <2>; + reg = <0x0 0x881A0000 0x0 0x1000>; + xlnx,num-ss-bits = <0x2>; + xlnx,spi-mode = <0>; + + #address-cells = <1>; + #size-cells = <0>; + + ltc6952: ltc6952@0 { + compatible = "adi,ltc6952"; + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <10000000>; + label = "ltc6952"; + + clocks = <&clkin_125> , <<c6948>; + clock-names = "clkin", "vcoin"; + vcoin-clock-scales = <1 10>; + + adi,vco-frequency-hz = <2500000000>; + + jesd204-device; + #jesd204-cells = <2>; +#if WITH_AION + jesd204-inputs = + <&adf4030 0 FRAMER_LINK_A0_RX>, + <&adf4030 0 DEFRAMER_LINK_A0_TX>; +#else + jesd204-sysref-provider; +#endif /* WITH_AION */ + + clock-output-names = "ltc6952_0_out0", "ltc6952_0_out1", + "ltc6952_0_out2", "ltc6952_0_out3", "ltc6952_0_out4", + "ltc6952_0_out5", "ltc6952_0_out6", "ltc6952_0_out7", + "ltc6952_0_out8", "ltc6952_0_out9", "ltc6952_0_out10"; + + #clock-cells = <1>; + + adi,pulse-generator-mode = <2>; /* Four Pulses */ +#if WITH_AION + channel@0 { + reg = <0>; + adi,extended-name = "ADF4030_BSYNC0"; + adi,divider = <256>; + adi,digital-delay = <0>; + adi,analog-delay = <0>; + }; +#endif /* WITH_AION */ + channel@3 { + reg = <3>; + adi,extended-name = "VUP Core CLK"; + adi,divider = <8>; + adi,digital-delay = <0>; + adi,analog-delay = <0>; + }; +#ifndef WITH_AION + channel@4 { + reg = <4>; + adi,extended-name = "VUP JESD SYSREF"; + adi,divider = <768>; + adi,digital-delay = <0>; + adi,analog-delay = <0>; + adi,sysref-mode = <0>; + adi,jesd204-sysref-chan; + }; + channel@5 { + reg = <5>; + adi,extended-name = "Apollo SYSREF"; + adi,divider = <768>; + adi,digital-delay = <0>; + adi,analog-delay = <0>; + adi,sysref-mode = <0>; + adi,jesd204-sysref-chan; + }; +#endif /* !WITH_AION */ + channel@6 { + reg = <6>; + adi,extended-name = "JESD REF CLK 1"; + adi,divider = <4>; + adi,digital-delay = <0>; + adi,analog-delay = <0>; + }; + channel@7 { + reg = <7>; + adi,extended-name = "JESD REF CLK 2"; + adi,divider = <4>; + adi,digital-delay = <0>; + adi,analog-delay = <0>; + }; + }; + + ltc6948: ltc6948@1 { + #clock-cells = <0>; + compatible = "adi,ltc6948"; + reg = <1>; + spi-max-frequency = <5000000>; + clocks = <&clkin_125>; + clock-names = "clkin"; + clock-output-names = "ltc6948_out_clk"; + clock-scales = <1 10>; + }; + }; + +#if WITH_AION + adf4030_spi: spi@88260000 { + bits-per-word = <8>; + compatible = "xlnx,axi-quad-spi-3.2", "xlnx,xps-spi-2.00.a"; + fifo-size = <16>; + interrupt-names = "ip2intc_irpt"; + interrupt-parent = <&axi_intc_0>; + interrupts = <18 0>; + num-cs = <1>; + reg = <0x0 0x88260000 0x0 0x1000>; + xlnx,num-ss-bits = <0x2>; + xlnx,spi-mode = <0>; + + #address-cells = <1>; + #size-cells = <0>; + + adf4030: adf4030@0 { + #clock-cells = <1>; + compatible = "adi,adf4030"; + reg = <0>; + + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + spi-max-frequency = <1000000>; + adi,spi-3wire-enable; + + clocks = <&clkin_250>; + clock-names = "refin"; + clock-output-names = "adf4030_bsync_0", "adf4030_bsync_1", + "adf4030_bsync_2", "adf4030_bsync_3", "adf4030_bsync_4", + "adf4030_bsync_5", "adf4030_bsync_6", "adf4030_bsync_7", + "adf4030_bsync_8", "adf4030_bsync_9"; + label = "adf4030"; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-sysref-provider; + + adi,vco-frequency-hz = <2500000000>; /* 2.5 GHz */ + adi,bsync-frequency-hz = <9765625>; + adi,bsync-autoalign-reference-channel = <0>; + adi,bsync-autoalign-iteration-count = <6>; + adi,bsync-secondary-frequency-hz = <9765625>; + + channel@0 { + reg = <0>; + adi,extended-name = "ADF4030_BSYNC0"; + auto-align-on-sync-en; + adi,rcm = <62>; // LVDS + adi,link-rx-en; + adi,float-rx-en; + }; + channel@1 { + reg = <1>; + adi,extended-name = "BSYNC1_APOLLO_SYSREF"; + auto-align-on-sync-en; + adi,output-en; + adi,input-output-reconfig-en; + adi,rcm = <62>; // LVDS + adi,link-rx-en; + adi,float-rx-en; + }; + channel@2 { + reg = <2>; + adi,extended-name = "BSYNC2_JESD_SYSREF"; + auto-align-on-sync-en; + adi,output-en; + adi,input-output-reconfig-en; + adi,rcm = <62>; + adi,link-rx-en; + adi,float-rx-en; + }; + channel@9 { + reg = <9>; + adi,extended-name = "ADF4030_BSYNC9"; + adi,output-en; + auto-align-on-sync-en; + adi,input-output-reconfig-en; + adi,rcm = <62>; + }; + }; + }; +#endif /* WITH_AION */ + + + axi_gpio_0: gpio@88120000 { + #gpio-cells = <2>; + clock-frequency = <100000000>; + clock-names = "s_axi_aclk"; + clocks = <&mig_clkout1>; + compatible = "xlnx,axi-gpio-2.0", "xlnx,xps-gpio-1.00.a"; + gpio-controller ; + reg = <0x0 0x88120000 0x0 0x10000>; + xlnx,all-inputs = <0x0>; + xlnx,all-inputs-2 = <0x0>; + xlnx,all-outputs = <0x0>; + xlnx,all-outputs-2 = <0x0>; + xlnx,dout-default = <0x00000000>; + xlnx,dout-default-2 = <0x00000000>; + xlnx,gpio-width = <0x20>; + xlnx,gpio2-width = <0x20>; + xlnx,interrupt-present = <0x0>; + xlnx,is-dual = <0x1>; + xlnx,tri-default = <0xFFFFFFFF>; + xlnx,tri-default-2 = <0xFFFFFFFF>; + }; + + axi_gpio_1: gpio@88130000 { + #gpio-cells = <2>; + clock-frequency = <100000000>; + clock-names = "s_axi_aclk"; + clocks = <&mig_clkout1>; + compatible = "xlnx,axi-gpio-2.0", "xlnx,xps-gpio-1.00.a"; + gpio-controller ; + reg = <0x0 0x88130000 0x0 0x10000>; + xlnx,all-inputs = <0x0>; + xlnx,all-inputs-2 = <0x0>; + xlnx,all-outputs = <0x0>; + xlnx,all-outputs-2 = <0x0>; + xlnx,dout-default = <0x00000000>; + xlnx,dout-default-2 = <0x00000000>; + xlnx,gpio-width = <0x20>; + xlnx,gpio2-width = <0x20>; + xlnx,interrupt-present = <0x0>; + xlnx,is-dual = <0x1>; + xlnx,tri-default = <0xFFFFFFFF>; + xlnx,tri-default-2 = <0xFFFFFFFF>; + }; + + axi_gpio_2: gpio@88140000 { + #gpio-cells = <2>; + clock-frequency = <100000000>; + clock-names = "s_axi_aclk"; + clocks = <&mig_clkout1>; + compatible = "xlnx,axi-gpio-2.0", "xlnx,xps-gpio-1.00.a"; + gpio-controller; + reg = <0x0 0x88140000 0x0 0x10000>; + xlnx,all-inputs = <0x0>; + xlnx,all-inputs-2 = <0x0>; + xlnx,all-outputs = <0x0>; + xlnx,all-outputs-2 = <0x0>; + xlnx,dout-default = <0x00000000>; + xlnx,dout-default-2 = <0x00000000>; + xlnx,gpio-width = <0x20>; + xlnx,gpio2-width = <0x13>; + xlnx,interrupt-present = <0x0>; + xlnx,is-dual = <0x1>; + xlnx,tri-default = <0xFFFFFFFF>; + xlnx,tri-default-2 = <0xFFFFFFFF>; + }; + + axi_iic_main: i2c@88150000 { + clock-frequency = <100000000>; + clocks = <&mig_clkout1>; + compatible = "xlnx,axi-iic-2.1", "xlnx,xps-iic-2.00.a"; + interrupt-names = "iic2intc_irpt"; + interrupt-parent = <&axi_intc_0>; + interrupts = <1 2>; + reg = <0x0 0x88150000 0x0 0x10000>; + }; + + axi_sysid_0: axi_sysid@42000000 { + compatible = "adi,axi-sysid-1.00.a"; + reg = <0x0 0x88170000 0x0 0x1000>; + }; + + rx_dma: dma@88090000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x0 0x88090000 0x0 0x10000>; + #dma-cells = <1>; + #clock-cells = <0>; + interrupt-parent = <&axi_intc_0>; + interrupts = <3 2>; + clocks = <&mig_clkout1>; + memory-region = <&vu11p_ddr_dma>; + }; + + tx_dma: dma@880f0000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x0 0x880F0000 0x0 0x10000>; + #dma-cells = <1>; + #clock-cells = <0>; + interrupt-parent = <&axi_intc_0>; + interrupts = <4 2>; + clocks = <&mig_clkout1>; + memory-region = <&vu11p_ddr_dma>; + }; + + axi_data_offload_rx: data_offload_rx@88020000 { + compatible = "adi,axi-data-offload-1.0.a"; + reg = <0x0 0x88020000 0x0 0x10000>; + }; + + axi_data_offload_tx: data_offload_tx@88050000 { + compatible = "adi,axi-data-offload-1.0.a"; + reg = <0x0 0x88050000 0x0 0x10000>; + }; + + axi_ad9084_adxcvr_rx: axi-adxcvr-rx@880b0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "adi,axi-adxcvr-1.0"; + reg = <0x0 0x880B0000 0x0 0x1000>; + + clocks = <<c6952 7>; /* div40 is controlled by axi_ad9084_rx_jesd */ + clock-names = "conv"; + + #clock-cells = <1>; + clock-output-names = "rx_gt_clk", "rx_out_clk"; + + adi,sys-clk-select = ; + adi,out-clk-select = ; + adi,use-lpm-enable; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <<c6952 0 FRAMER_LINK_A0_RX>; + }; + + axi_ad9084_adxcvr_tx: axi-adxcvr-tx@88110000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "adi,axi-adxcvr-1.0"; + reg = <0x0 0x88110000 0x0 0x1000>; + + clocks = <<c6952 7>; /* div40 is controlled by axi_ad9084_tx_jesd */ + clock-names = "conv"; + + #clock-cells = <1>; + clock-output-names = "tx_gt_clk", "tx_out_clk"; + + adi,sys-clk-select = ; + adi,out-clk-select = ; /* XCVR_PROGDIV_CLK */ + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <<c6952 0 DEFRAMER_LINK_A0_TX>; + }; + + axi_ad9084_rx_jesd: axi-jesd204-rx@880a0000 { + compatible = "adi,axi-jesd204-rx-1.0"; + reg = <0x0 0x880a0000 0x0 0x1000>; + interrupt-parent = <&axi_intc_0>; + interrupts = <5 2>; + + clocks = <&mig_clkout1>, <&axi_ad9084_adxcvr_rx 1>, <<c6952 3>, <&axi_ad9084_adxcvr_rx 0>; + clock-names = "s_axi_aclk", "link_clk", "device_clk", "lane_clk"; + + #clock-cells = <0>; + clock-output-names = "jesd_rx_lane_clk"; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_adxcvr_rx 0 FRAMER_LINK_A0_RX>; + }; + + axi_ad9084_tx_jesd: axi-jesd204-tx@88100000 { + compatible = "adi,axi-jesd204-tx-1.0"; + reg = <0x0 0x88100000 0x0 0x1000>; + + interrupt-parent = <&axi_intc_0>; + interrupts = <6 2>; + + clocks = <&mig_clkout1>, <&axi_ad9084_adxcvr_tx 1>, <<c6952 3>, <&axi_ad9084_adxcvr_tx 0>; + clock-names = "s_axi_aclk", "link_clk", "device_clk", "lane_clk"; + + #clock-cells = <0>; + clock-output-names = "jesd_tx_lane_clk"; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_adxcvr_tx 0 DEFRAMER_LINK_A0_TX>; + }; + + apollo_spi: spi@88030000 { + bits-per-word = <8>; + compatible = "xlnx,axi-quad-spi-3.2", "xlnx,xps-spi-2.00.a"; + fifo-size = <16>; + interrupt-names = "ip2intc_irpt"; + interrupt-parent = <&axi_intc_0>; + interrupts = <7 0>; + num-cs = <1>; + reg = <0x0 0x88030000 0x0 0x1000>; + xlnx,num-ss-bits = <0x1>; + xlnx,spi-mode = <0>; + + #address-cells = <1>; + #size-cells = <0>; + + trx0_ad9084: ad9084@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "adi,ad9084"; + reg = <0>; + spi-max-frequency = <5000000>; + + /* Clocks */ + clocks = <&adf4382 0>; + clock-names = "dev_clk"; + dev_clk-clock-scales = <1 10>; + + clock-output-names = "rx_sampl_clk", "tx_sampl_clk"; + #clock-cells = <1>; + +#if HSCI_ENABLE + adi,axi-hsci-connected = <&axi_hsci>; + adi,hsci-auto-linkup-mode-en; + adi,hsci-disable-after-boot-en; +#endif + + jesd204-device; + #jesd204-cells = <2>; + jesd204-top-device = <0>; /* This is the TOP device */ + jesd204-ignore-errors; + +#ifdef ASYNM_A_B_MODE + jesd204-link-ids = ; + + jesd204-inputs = + <&axi_ad9084_core_rx 0 FRAMER_LINK_A0_RX>, + <&axi_ad9084_rx_jesd_b 0 FRAMER_LINK_B0_RX>, + <&axi_ad9084_core_tx 0 DEFRAMER_LINK_A0_TX>, + <&axi_ad9084_core_tx_b 0 DEFRAMER_LINK_B0_TX>; + + adi,side-b-use-seperate-tpl-en; +#else + jesd204-link-ids = ; + + jesd204-inputs = + <&axi_ad9084_core_rx 0 FRAMER_LINK_A0_RX>, + <&axi_ad9084_core_tx 0 DEFRAMER_LINK_A0_TX>; +#endif + + reset-gpios = <&axi_gpio_2 0x31 0>; + adi,device-profile-fw-name = DEVICE_PROFILE_NAME; + + adi,jrx0-physical-lane-mapping = <11 4 6 10 9 8 7 2 0 3 5 1>; + adi,jtx0-logical-lane-mapping = < 8 6 10 11 9 4 7 2 5 0 3 1>; + adi,jrx1-physical-lane-mapping = <3 1 5 0 7 2 8 6 4 9 10 11>; + adi,jtx1-logical-lane-mapping = <0 2 1 4 3 5 6 10 7 11 8 9>; + + adi,subclass = ; + +#if WITH_AION + io-channels = <&adf4030 1>, <&adf4382 0>; + io-channel-names = "bsync", "clk"; +#endif /* WITH_AION */ + }; + + }; + + axi_ad9084_core_rx: axi-ad9084-rx-hpc@881b0000 { + compatible = "adi,axi-ad9081-rx-1.0"; + reg = <0x0 0x881B0000 0x0 0x1000>; + dmas = <&rx_dma 0>; + dma-names = "rx"; + spibus-connected = <&trx0_ad9084>; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_rx_jesd 0 FRAMER_LINK_A0_RX>; + }; + + axi_ad9084_core_tx: axi-ad9084-tx-hpc@881d0000 { + compatible = "adi,axi-ad9081-tx-1.0"; + reg = <0x0 0x881D0000 0x0 0x1000>; + dmas = <&tx_dma 0>; + dma-names = "tx"; + clocks = <&trx0_ad9084 1>; + clock-names = "sampl_clk"; + spibus-connected = <&trx0_ad9084>; + adi,axi-pl-fifo-enable; + adi,axi-data-offload-connected = <&axi_data_offload_tx>; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_tx_jesd 0 DEFRAMER_LINK_A0_TX>; + }; + +#if HSCI_ENABLE + hsci_clkgen: axi-clkgen@881F0000 { + compatible = "adi,axi-clkgen-2.00.a"; + reg = <0x0 0x881F0000 0x0 0x1000>; + #clock-cells = <0>; + clocks = <&mig_clkout1>, <&mig_clkout1>; + clock-names = "s_axi_aclk", "clkin1"; + clock-output-names = "hsci_clkgen"; + }; + + axi_hsci: axi_hsci@88200000 { + compatible = "adi,axi-hsci-1.0.a"; + reg = <0x0 0x88200000 0x0 0x40000>; + clocks = <&hsci_clkgen>; + clock-names = "pclk"; + adi,hsci-interface-speed-mhz = <800>; + }; +#endif + +#ifdef ASYNM_A_B_MODE + rx_dma_b: dma@88060000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x0 0x88060000 0x0 0x10000>; + #dma-cells = <1>; + #clock-cells = <0>; + interrupt-parent = <&axi_intc_0>; + interrupts = <10 2>; + clocks = <&mig_clkout1>; + memory-region = <&vu11p_ddr_dma>; + }; + + tx_dma_b: dma@880c0000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x0 0x880C0000 0x0 0x10000>; + #dma-cells = <1>; + #clock-cells = <0>; + interrupt-parent = <&axi_intc_0>; + interrupts = <11 2>; + clocks = <&mig_clkout1>; + memory-region = <&vu11p_ddr_dma>; + + }; + + axi_ad9084_core_rx_b: axi-ad9084b-rx-b@881c0000 { + compatible = "adi,axi-adc-tpl-so-10.0.a"; + reg = <0x0 0x881C0000 0x0 0x10000>; + dmas = <&rx_dma_b 0>; + dma-names = "rx"; + clocks = <&trx0_ad9084 0>; /* FIXME */ + clock-names = "sampl_clk"; + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_rx_jesd_b 0 FRAMER_LINK_B0_RX>; + }; + + axi_ad9084_core_tx_b: axi-ad9084-tx-b@881e0000 { + compatible = "adi,axi-ad9081-tx-1.0"; + reg = <0x0 0x881E0000 0x0 0x10000>; + dmas = <&tx_dma_b 0>; + dma-names = "tx"; + clocks = <&trx0_ad9084 1>; /* FIXME */ + clock-names = "sampl_clk"; + adi,axi-pl-fifo-enable; + adi,axi-data-offload-connected = <&axi_data_offload_tx_b>; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_tx_jesd_b 0 DEFRAMER_LINK_B0_TX>; + }; + + axi_ad9084_rx_jesd_b: axi-jesd204-rx-b@88070000 { + compatible = "adi,axi-jesd204-rx-1.0"; + reg = <0x0 0x88070000 0x0 0x10000>; + + interrupt-parent = <&axi_intc_0>; + interrupts = <12 2>; + + clocks = <&mig_clkout1>, <&axi_ad9084_adxcvr_rx_b 1>, <<c6952 3>, <&axi_ad9084_adxcvr_rx_b 0>; + clock-names = "s_axi_aclk", "link_clk", "device_clk", "lane_clk"; + + #clock-cells = <0>; + clock-output-names = "jesd_rx_lane_clk_b"; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_adxcvr_rx_b 0 FRAMER_LINK_B0_RX>; + }; + + axi_ad9084_tx_jesd_b: axi-jesd204-tx-b@880d0000 { + compatible = "adi,axi-jesd204-tx-1.0"; + reg = <0x0 0x880D0000 0x0 0x10000>; + + interrupt-parent = <&axi_intc_0>; + interrupts = <13 2>; + + clocks = <&mig_clkout1>, <&axi_ad9084_adxcvr_tx_b 1>, <<c6952 3>, <&axi_ad9084_adxcvr_tx_b 0>; + clock-names = "s_axi_aclk", "link_clk", "device_clk", "lane_clk"; + + #clock-cells = <0>; + clock-output-names = "jesd_tx_lane_clk_b"; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_adxcvr_tx_b 0 DEFRAMER_LINK_B0_TX>; + }; + + axi_ad9084_adxcvr_rx_b: axi-adxcvr-rx-b@88080000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "adi,axi-adxcvr-1.0"; + reg = <0x0 0x88080000 0x0 0x10000>; + + clocks = <<c6952 6>; /* div40 is controlled by axi_ad9084_rx_jesd */ + clock-names = "conv"; + + #clock-cells = <1>; + clock-output-names = "rx_gt_clk_b", "rx_out_clk_b"; + + adi,sys-clk-select = ; + adi,out-clk-select = ; + adi,use-lpm-enable; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <<c6952 0 FRAMER_LINK_B0_RX>; + }; + + axi_ad9084_adxcvr_tx_b: axi-adxcvr-tx-b@880e0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "adi,axi-adxcvr-1.0"; + reg = <0x0 0x880E0000 0x0 0x10000>; + + clocks = <<c6952 6>; /* div40 is controlled by axi_ad9084_tx_jesd */ + clock-names = "conv"; + + #clock-cells = <1>; + clock-output-names = "tx_gt_clk_b", "tx_out_clk_b"; + + adi,sys-clk-select = ; + adi,out-clk-select = ; /* XCVR_PROGDIV_CLK */ + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <<c6952 0 DEFRAMER_LINK_B0_TX>; + }; + + axi_data_offload_rx_b: data_offload_rx_b@88010000 { + compatible = "adi,axi-data-offload-1.0.a"; + reg = <0x0 0x88010000 0x0 0x10000>; + }; + + axi_data_offload_tx_b: data_offload_tx_b@88040000 { + compatible = "adi,axi-data-offload-1.0.a"; + reg = <0x0 0x88040000 0x0 0x10000>; + }; +#endif /* ASYNM_A_B_MODE */ + + rfpc_one_bit_adc_dac: one-bit-adc-dac@0 { + compatible = "adi,one-bit-adc-dac"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-ad9084-vpx.dts b/arch/arm64/boot/dts/xilinx/zynqmp-ad9084-vpx.dts new file mode 100644 index 00000000000000..d0f144b0884967 --- /dev/null +++ b/arch/arm64/boot/dts/xilinx/zynqmp-ad9084-vpx.dts @@ -0,0 +1,377 @@ +// SPDX-License-Identifier: GPL-2.0 +/dts-v1/; + +#include "zynqmp.dtsi" +#include "zynqmp-clk-ccf.dtsi" +#include +#include + +#include +#include + +/ { + + model = "ADSY1100 ZU4EG/VU11P Rev.A"; + + chosen { + bootargs = "earlycon console=ttyPS0,115200 clk_ignore_unused root=/dev/mmcblk0p2 ro rootwait"; + stdout-path = "serial0:115200n8"; + }; + + aliases { + ethernet0 = &gem0; + i2c0 = &i2c0; + i2c1 = &i2c1; + i2c2 = &axi_iic_adm1266; + i2c3 = &axi_iic_ipcm1; + i2c4 = &axi_iic_ltc2977; + serial0 = &uart0; + serial1 = &uart1; + spi0 = &qspi; + spi1 = &spi0; + spi2 = &spi1; + }; + + psgtr_ref0: ext_clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + vu11p_fpga_mgr: fpga-mgr@93000000 { + compatible = "adi,fpga-16-selectmap"; + reg = <0x0 0x93000000 0x0 0x10000>; + prog-gpios = <&gpio 116 GPIO_ACTIVE_LOW>; //38 + init-gpios = <&gpio 114 GPIO_ACTIVE_LOW>;//36 + done-gpios = <&gpio 115 GPIO_ACTIVE_HIGH>;//37 + csi-gpios = <&gpio 121 GPIO_ACTIVE_LOW>;//43 + rdwr-gpios = <&gpio 117 GPIO_ACTIVE_LOW>;//39 + }; + + vu11p_fpga_region: fpga-vu11p { + #address-cells = <2>; + #size-cells = <2>; + + compatible = "fpga-region"; + fpga-mgr = <&vu11p_fpga_mgr>; + ranges = <0x0 0x80000000 0x0 0x80000000 0x0 0x10000000>; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x0 0x0 0x7ff00000>; + }; + + memory_vu11p@1 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x7ff0000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + vu11p_ddr_dma: vu11p_dma_mem_region@80000000 { + compatible = "restricted-dma-pool"; + reg = <0x0 0x80000000 0x0 0x7ff0000>; + }; + }; +}; + +/ { + amba_pl: amba_pl@0 { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges ; + axi_chip2chip: axi_chip2chip@80000000 { + clock-names = "aurora_init_clk", "axi_c2c_phy_clk", "s_aclk"; + clocks = <&zynqmp_clk 71>, <&misc_clk_0>, <&zynqmp_clk 71>; + compatible = "xlnx,axi-chip2chip-5.0"; + reg = <0x0 0x80000000 0x0 0x10000000>; + xlnx,aurora-width = <0x80>; + xlnx,axi-addr-width = <0x20>; + xlnx,axi-brst-width = <0x2>; + xlnx,axi-bus-type = <0x0>; + xlnx,axi-data-width = <0x80>; + xlnx,axi-id-width = <0x1>; + xlnx,axi-len-width = <0x8>; + xlnx,axi-lite-addr-width = <0x20>; + xlnx,axi-lite-data-width = <0x20>; + xlnx,axi-lite-prot-width = <0x2>; + xlnx,axi-lite-resp-width = <0x2>; + xlnx,axi-lite-stb-width = <0x4>; + xlnx,axi-resp-width = <0x2>; + xlnx,axi-size-width = <0x3>; + xlnx,axi-stb-width = <0x10>; + xlnx,axi-wuser-width = <0x1>; + xlnx,common-clk = <0x0>; + xlnx,disable-clk-shift = <0x0>; + xlnx,disable-deskew = <0x0>; + xlnx,ecc-enable = <0x1>; + xlnx,en-aur-gtm-exdes = "false"; + xlnx,en-axi-link-hndlr = <0x0>; + xlnx,en-legacy-mode = <0x0>; + xlnx,include-axilite = <0x0>; + xlnx,interface-mode = <0x1>; + xlnx,interface-type = <0x2>; + xlnx,interrupt-width = <0x4>; + xlnx,master-fpga = <0x1>; + xlnx,num-of-io = <0x14>; + xlnx,selectio-phy-clk = <0x64>; + xlnx,simulation = <0x0>; + xlnx,support-narrowburst = "axi_c2c"; + xlnx,use-diff-clk = <0x0>; + xlnx,use-diff-io = <0x0>; + }; + misc_clk_0: misc_clk_0 { + #clock-cells = <0>; + clock-frequency = <195312500>; + compatible = "fixed-clock"; + }; + axi_iic_adm1266: i2c@91000000 { + #address-cells = <1>; + #size-cells = <0>; + clock-names = "s_axi_aclk"; + clocks = <&zynqmp_clk 71>; + compatible = "xlnx,axi-iic-2.1", "xlnx,xps-iic-2.00.a"; + interrupt-names = "iic2intc_irpt"; + interrupt-parent = <&gic>; + interrupts = <0 95 4>; + reg = <0x0 0x91000000 0x0 0x1000>; + }; + axi_iic_ipcm1: i2c@92000000 { + #address-cells = <1>; + #size-cells = <0>; + clock-names = "s_axi_aclk"; + clocks = <&zynqmp_clk 71>; + compatible = "xlnx,axi-iic-2.1", "xlnx,xps-iic-2.00.a"; + interrupt-names = "iic2intc_irpt"; + interrupt-parent = <&gic>; + interrupts = <0 94 4>; + reg = <0x0 0x92000000 0x0 0x1000>; + }; + axi_iic_ltc2977: i2c@90000000 { + #address-cells = <1>; + #size-cells = <0>; + clock-names = "s_axi_aclk"; + clocks = <&zynqmp_clk 71>; + compatible = "xlnx,axi-iic-2.1", "xlnx,xps-iic-2.00.a"; + interrupt-names = "iic2intc_irpt"; + interrupt-parent = <&gic>; + interrupts = <0 96 4>; + reg = <0x0 0x90000000 0x0 0x1000>; + }; + axi_selmap: axi_selmap@93000000 { + clock-names = "s_axi_aclk"; + clocks = <&zynqmp_clk 71>; + compatible = "xlnx,axi-selmap-1.0"; + reg = <0x0 0x93000000 0x0 0x10000>; + }; + }; +}; + +//TODO:PCW +&gic { + num_cpus = <2>; + num_interrupts = <96>; +}; +&lpd_dma_chan1 { + status = "okay"; +}; +&lpd_dma_chan2 { + status = "okay"; +}; +&lpd_dma_chan3 { + status = "okay"; +}; +&lpd_dma_chan4 { + status = "okay"; +}; +&lpd_dma_chan5 { + status = "okay"; +}; +&lpd_dma_chan6 { + status = "okay"; +}; +&lpd_dma_chan7 { + status = "okay"; +}; +&lpd_dma_chan8 { + status = "okay"; +}; +&xilinx_ams { + status = "okay"; +}; +&cci { + status = "okay"; +}; +&gem0 { + phy-mode = "sgmii"; + status = "okay"; + xlnx,ptp-enet-clock = <0x0>; +}; +&fpd_dma_chan1 { + status = "okay"; +}; +&fpd_dma_chan2 { + status = "okay"; +}; +&fpd_dma_chan3 { + status = "okay"; +}; +&fpd_dma_chan4 { + status = "okay"; +}; +&fpd_dma_chan5 { + status = "okay"; +}; +&fpd_dma_chan6 { + status = "okay"; +}; +&fpd_dma_chan7 { + status = "okay"; +}; +&fpd_dma_chan8 { + status = "okay"; +}; +&gpio { + emio-gpio-width = <32>; + gpio-mask-high = <0x0>; + gpio-mask-low = <0x5600>; + status = "okay"; +}; +&gpu { + status = "okay"; + xlnx,tz-nonsecure = <0x1>; +}; +&i2c0 { + status = "okay"; +}; +&i2c1 { + status = "okay"; +}; +&qspi { + is-dual = <1>; + num-cs = <2>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + status = "okay"; +}; +&rtc { + status = "okay"; +}; +&sdhci1 { + clock-frequency = <199998001>; + status = "okay"; + xlnx,mio-bank = <0x1>; +}; +&psgtr { + status = "okay"; +}; +&spi0 { + is-decoded-cs = <0>; + num-cs = <1>; + status = "okay"; +}; +&spi1 { + is-decoded-cs = <0>; + num-cs = <1>; + status = "okay"; +}; +&uart0 { + cts-override ; + device_type = "serial"; + port-number = <0>; + status = "okay"; + u-boot,dm-pre-reloc ; +}; +&uart1 { + cts-override ; + device_type = "serial"; + port-number = <1>; + status = "okay"; + u-boot,dm-pre-reloc ; +}; +&pinctrl0 { + i2c1-default { + /delete-node/ conf ; + /delete-node/ mux ; + }; + i2c1-gpio { + /delete-node/ conf ; + /delete-node/ mux ; + }; +}; +&ams_ps { + status = "okay"; +}; +&ams_pl { + status = "okay"; +}; + +&axi_selmap { + status = "disabled"; +}; + +&psgtr { + status = "okay"; + clocks = <&psgtr_ref0>; + clock-names = "ref0"; +}; + +&gem0 { + phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; + phy-handle = <&phy1>; + phy-mode = "sgmii"; + is-internal-pcspma; + mdio { + #address-cells = <1>; + #size-cells = <0>; + phy1: ethernet-phy@1 { + reg = <1>; + device_type = "ethernet-phy"; + reset-gpios = <&gpio 82 GPIO_ACTIVE_LOW>; + reset-assert-us = <20000>; + reset-deassert-us = <500>; + }; + }; +}; + +&sdhci1 { + disable-wp; + no-1-8-v; +}; + +&qspi { + status = "okay"; + is-dual = <1>; + num-cs = <1>; + primary_flash: qspi@0 { + #address-cells = <1>; + #size-cells = <1>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <4>; + compatible = "n25q512a", "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <50000000>; + + partition@qspi-fsbl-uboot { + label = "qspi-fsbl-uboot"; + reg = <0x0 0x2000000>; /* 32M */ + }; + partition@qspi-uboot-env { + label = "qspi-uboot-env"; + reg = <0x2000000 0x20000>; /* 128k */ + }; + partition@qspi-nvmfs { + label = "qspi-nvmfs"; + reg = <0x2020000 0xE0000>; /* 1M */ + }; + partition@qspi-linux { + label = "qspi-linux"; + reg = <0x2100000 0x5E00000>; /* 94M */ + }; + }; +}; diff --git a/arch/arm64/configs/adi_versal_apollo_defconfig b/arch/arm64/configs/adi_versal_apollo_defconfig new file mode 100644 index 00000000000000..7711c6afcab660 --- /dev/null +++ b/arch/arm64/configs/adi_versal_apollo_defconfig @@ -0,0 +1,404 @@ +CONFIG_KERNEL_ALL_ADI_DRIVERS=y +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_AUDIT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=16 +CONFIG_CGROUPS=y +CONFIG_NAMESPACES=y +CONFIG_USER_NS=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_EMBEDDED=y +CONFIG_PROFILING=y +CONFIG_ARCH_ZYNQMP=y +CONFIG_ARM64_VA_BITS_48=y +CONFIG_NR_CPUS=4 +CONFIG_KEXEC=y +CONFIG_CRASH_DUMP=y +CONFIG_COMPAT=y +CONFIG_ARMV8_DEPRECATED=y +CONFIG_SWP_EMULATION=y +CONFIG_CP15_BARRIER_EMULATION=y +CONFIG_SETEND_EMULATION=y +CONFIG_CPU_IDLE=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y +CONFIG_CPUFREQ_DT=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_MODULE_FORCE_UNLOAD=y +CONFIG_SLAB=y +# CONFIG_COMPAT_BRK is not set +CONFIG_MEMORY_HOTPLUG=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=32768 +CONFIG_TRANSPARENT_HUGEPAGE=y +CONFIG_TRANSPARENT_HUGEPAGE_MADVISE=y +CONFIG_CMA=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM_USER=y +CONFIG_NET_KEY=y +CONFIG_NET_KEY_MIGRATE=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_SYN_COOKIES=y +CONFIG_NETWORK_SECMARK=y +CONFIG_NETFILTER=y +CONFIG_NETFILTER_NETLINK_LOG=y +CONFIG_NF_CONNTRACK=y +CONFIG_NF_CONNTRACK_FTP=y +CONFIG_NF_CONNTRACK_SNMP=y +CONFIG_NF_CONNTRACK_TFTP=y +CONFIG_NF_CT_NETLINK=y +CONFIG_NETFILTER_XT_MARK=y +CONFIG_NETFILTER_XT_CONNMARK=y +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=y +CONFIG_NETFILTER_XT_TARGET_LOG=y +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=y +CONFIG_NETFILTER_XT_MATCH_MAC=y +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_IP_NF_IPTABLES=y +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_TARGET_REJECT=y +CONFIG_IP_NF_MANGLE=y +CONFIG_IP6_NF_IPTABLES=y +CONFIG_IP6_NF_FILTER=y +CONFIG_IP6_NF_TARGET_REJECT=y +CONFIG_IP6_NF_MANGLE=y +CONFIG_BRIDGE_NF_EBTABLES=y +CONFIG_BRIDGE_EBT_T_FILTER=y +CONFIG_BRIDGE_EBT_T_NAT=y +CONFIG_BRIDGE_EBT_MARK_T=y +CONFIG_NET_PKTGEN=y +CONFIG_CAN=y +CONFIG_BT=y +CONFIG_BT_RFCOMM=y +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=y +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=y +CONFIG_BT_LEDS=y +CONFIG_BT_HCIBTUSB=y +CONFIG_BT_HCIBTSDIO=y +CONFIG_BT_HCIUART=y +CONFIG_BT_HCIUART_BCSP=y +CONFIG_BT_HCIUART_ATH3K=y +CONFIG_BT_HCIUART_LL=y +CONFIG_BT_HCIUART_3WIRE=y +CONFIG_BT_HCIUART_INTEL=y +CONFIG_BT_HCIUART_QCA=y +CONFIG_BT_HCIBCM203X=y +CONFIG_BT_HCIBPA10X=y +CONFIG_BT_HCIBFUSB=y +CONFIG_BT_HCIVHCI=y +CONFIG_BT_MRVL=y +CONFIG_BT_MRVL_SDIO=y +CONFIG_BT_ATH3K=y +CONFIG_CFG80211=y +CONFIG_NL80211_TESTMODE=y +CONFIG_CFG80211_CERTIFICATION_ONUS=y +CONFIG_CFG80211_REG_CELLULAR_HINTS=y +CONFIG_CFG80211_REG_RELAX_NO_IR=y +CONFIG_CFG80211_WEXT=y +CONFIG_MAC80211=y +CONFIG_MAC80211_LEDS=y +CONFIG_MAC80211_MESSAGE_TRACING=y +CONFIG_MAC80211_DEBUG_MENU=y +CONFIG_RFKILL=y +CONFIG_RFKILL_INPUT=y +CONFIG_RFKILL_GPIO=y +CONFIG_NET_9P=y +CONFIG_PCI=y +# CONFIG_VGA_ARB is not set +CONFIG_PCIE_XILINX_NWL=y +CONFIG_PCIE_XILINX=y +CONFIG_PCIE_XDMA_PL=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_EXTRA_FIRMWARE="app_signed_encrypted_B/flash_image_0x01030000.bin app_signed_encrypted_B/flash_image_0x02000000.bin app_signed_encrypted_B/flash_image_0x20000000.bin app_signed_encrypted_B/flash_image_0x21000000.bin app_signed_encrypted_prod_B/flash_image_0x01030000.bin app_signed_encrypted_prod_B/flash_image_0x02000000.bin app_signed_encrypted_prod_B/flash_image_0x20000000.bin app_signed_encrypted_prod_B/flash_image_0x21000000.bin 204C_M4_L4_NP16_20p0_4x4.bin 204C_M4_L1_NP16_20p0_16x4.bin" +CONFIG_EXTRA_FIRMWARE_DIR="./firmware" +CONFIG_CONNECTOR=y +CONFIG_ZYNQMP_FIRMWARE_DEBUG=y +CONFIG_MTD=y +CONFIG_MTD_TESTS=m +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_OOPS=y +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_DATAFLASH=y +CONFIG_MTD_RAW_NAND=y +CONFIG_MTD_NAND_ARASAN=y +CONFIG_MTD_SPI_NOR=y +# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set +CONFIG_MTD_UBI=y +CONFIG_OF_OVERLAY=y +CONFIG_OF_CONFIGFS=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=65536 +CONFIG_ADI_AXI_HSCI=y +CONFIG_SRAM=y +CONFIG_XILINX_SDFEC=y +CONFIG_XILINX_AIE=y +CONFIG_EEPROM_AT24=y +CONFIG_EEPROM_AT25=y +CONFIG_TI_ST=y +CONFIG_BLK_DEV_SD=y +CONFIG_ATA=y +CONFIG_SATA_AHCI_PLATFORM=y +CONFIG_AHCI_CEVA=y +# CONFIG_ATA_SFF is not set +CONFIG_NETDEVICES=y +CONFIG_TUN=y +CONFIG_MACB=y +CONFIG_XILINX_EMACLITE=y +CONFIG_XILINX_AXI_EMAC=y +CONFIG_AMD_PHY=y +CONFIG_BROADCOM_PHY=y +CONFIG_BCM7XXX_PHY=y +CONFIG_BCM87XX_PHY=y +CONFIG_CICADA_PHY=y +CONFIG_DAVICOM_PHY=y +CONFIG_ICPLUS_PHY=y +CONFIG_LXT_PHY=y +CONFIG_LSI_ET1011C_PHY=y +CONFIG_MARVELL_PHY=y +CONFIG_MICREL_PHY=y +CONFIG_MICROSEMI_PHY=y +CONFIG_NATIONAL_PHY=y +CONFIG_AT803X_PHY=y +CONFIG_QSEMI_PHY=y +CONFIG_REALTEK_PHY=y +CONFIG_SMSC_PHY=y +CONFIG_STE10XP=y +CONFIG_DP83848_PHY=y +CONFIG_DP83867_PHY=y +CONFIG_VITESSE_PHY=y +CONFIG_XILINX_PHY=y +CONFIG_XILINX_GMII2RGMII=y +CONFIG_CAN_XILINXCAN=y +CONFIG_WL18XX=y +CONFIG_WLCORE_SPI=y +CONFIG_WLCORE_SDIO=y +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_MOUSE is not set +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_AMBA_PL010=y +CONFIG_SERIAL_AMBA_PL010_CONSOLE=y +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_SERIAL_MAX310X=y +CONFIG_SERIAL_UARTLITE=y +CONFIG_SERIAL_UARTLITE_CONSOLE=y +CONFIG_SERIAL_XILINX_PS_UART=y +CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y +CONFIG_SERIAL_DEV_BUS=y +# CONFIG_HW_RANDOM is not set +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX_PCA9541=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_I2C_CADENCE=y +CONFIG_I2C_XILINX=y +CONFIG_SPI_CADENCE=y +CONFIG_SPI_CADENCE_QUADSPI=y +CONFIG_SPI_XILINX=y +CONFIG_SPI_ZYNQMP_GQSPI=y +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_XILINX=y +CONFIG_GPIO_ZYNQ=y +CONFIG_GPIO_PCA953X=y +CONFIG_GPIO_TPS65086=y +CONFIG_SENSORS_IIO_HWMON=y +CONFIG_WATCHDOG=y +CONFIG_XILINX_WATCHDOG=y +CONFIG_CADENCE_WATCHDOG=y +CONFIG_MFD_TPS65086=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_GPIO=y +CONFIG_REGULATOR_TPS65086=y +CONFIG_VIDEO_XILINX=y +CONFIG_VIDEO_XILINX_CSI2RXSS=y +CONFIG_VIDEO_XILINX_AXI4S_SWITCH=y +CONFIG_VIDEO_XILINX_CFA=y +CONFIG_VIDEO_XILINX_CRESAMPLE=y +CONFIG_VIDEO_XILINX_DEMOSAIC=y +CONFIG_VIDEO_XILINX_GAMMA=y +CONFIG_VIDEO_XILINX_HLS=y +CONFIG_VIDEO_XILINX_REMAPPER=y +CONFIG_VIDEO_XILINX_RGB2YUV=y +CONFIG_VIDEO_XILINX_SCALER=y +CONFIG_VIDEO_XILINX_MULTISCALER=y +CONFIG_VIDEO_XILINX_SDIRXSS=y +CONFIG_VIDEO_XILINX_SWITCH=y +CONFIG_VIDEO_XILINX_TPG=y +CONFIG_VIDEO_XILINX_VPSS_CSC=y +CONFIG_VIDEO_XILINX_VPSS_SCALER=y +CONFIG_VIDEO_XILINX_DPRXSS=y +CONFIG_VIDEO_XILINX_SCD=y +CONFIG_VIDEO_XILINX_M2M=y +CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM=y +CONFIG_DRM_XLNX=y +CONFIG_DRM_XLNX_BRIDGE=y +CONFIG_DRM_XLNX_BRIDGE_DEBUG_FS=y +CONFIG_DRM_XLNX_DPTX=y +CONFIG_DRM_XLNX_DSI=y +CONFIG_DRM_XLNX_MIXER=y +CONFIG_DRM_XLNX_PL_DISP=y +CONFIG_DRM_XLNX_SDI=y +CONFIG_DRM_XLNX_BRIDGE_CSC=y +CONFIG_DRM_XLNX_BRIDGE_SCALER=y +CONFIG_FB_XILINX=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_SND_DRIVERS is not set +# CONFIG_SND_PCI is not set +CONFIG_SND_SOC_XILINX_DP=y +CONFIG_SND_SOC_XILINX_SDI=y +CONFIG_SND_SOC_XILINX_I2S=y +CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER=y +CONFIG_SND_SOC_XILINX_SPDIF=y +CONFIG_SND_SOC_XILINX_PL_SND_CARD=y +CONFIG_USB_OTG_FSM=y +CONFIG_USB_ETH=m +CONFIG_USB_ETH_EEM=y +CONFIG_USB_MASS_STORAGE=m +CONFIG_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_OF_ARASAN=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_ONESHOT=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_BACKLIGHT=y +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_LEDS_TRIGGER_GPIO=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_LEDS_TRIGGER_TRANSIENT=y +CONFIG_LEDS_TRIGGER_CAMERA=y +CONFIG_EDAC=y +CONFIG_EDAC_SYNOPSYS=y +CONFIG_EDAC_ZYNQMP_OCM=y +CONFIG_EDAC_XILINX_DDR=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_ZYNQMP=y +CONFIG_DMADEVICES=y +CONFIG_AXI_DMAC=y +CONFIG_XILINX_DMA=y +CONFIG_XILINX_ZYNQMP_DMA=y +CONFIG_DMATEST=y +CONFIG_XILINX_FCLK=y +CONFIG_COMMON_CLK_SI570=y +CONFIG_COMMON_CLK_SI5324=y +CONFIG_COMMON_CLK_AXI_CLKGEN=y +CONFIG_XILINX_VCU=m +CONFIG_COMMON_CLK_XLNX_CLKWZRD=y +# CONFIG_ARM_ARCH_TIMER_EVTSTREAM is not set +# CONFIG_FSL_ERRATUM_A008585 is not set +CONFIG_REMOTEPROC=y +CONFIG_ZYNQMP_R5_REMOTEPROC=m +CONFIG_AD9088=y +CONFIG_AD9088_REV_B0=y +CONFIG_INA2XX_ADC=y +CONFIG_XILINX_AMS=y +CONFIG_VERSAL_SYSMON=y +# CONFIG_AD916X_AMP is not set +# CONFIG_CF_AXI_DDS_AD9162 is not set +CONFIG_ADF4382=y +CONFIG_XILINX_INTC=y +CONFIG_ARM_CCI_PMU=y +# CONFIG_ARM_PMU is not set +CONFIG_RAS=y +CONFIG_NVMEM_ZYNQMP=y +CONFIG_FPGA=y +CONFIG_XILINX_AFI_FPGA=y +CONFIG_XILINX_PR_DECOUPLER=y +CONFIG_FPGA_REGION=y +CONFIG_OF_FPGA_REGION=y +CONFIG_FPGA_MGR_ZYNQMP_FPGA=y +CONFIG_FPGA_MGR_VERSAL_FPGA=y +CONFIG_EXT3_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_BTRFS_FS=y +CONFIG_EXPORTFS_BLOCK_OPS=y +CONFIG_QUOTA=y +CONFIG_QFMT_V2=y +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=y +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_HUGETLBFS=y +CONFIG_ECRYPT_FS=y +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_SUMMARY=y +CONFIG_JFFS2_FS_XATTR=y +CONFIG_JFFS2_COMPRESSION_OPTIONS=y +CONFIG_JFFS2_LZO=y +CONFIG_JFFS2_RUBIN=y +CONFIG_UBIFS_FS=y +CONFIG_CRAMFS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_NFS_V4_1=y +CONFIG_NFS_V4_2=y +CONFIG_ROOT_NFS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set +CONFIG_CRYPTO_CRCT10DIF=y +CONFIG_CRYPTO_USER_API_SKCIPHER=y +CONFIG_CRYPTO_CHACHA20_NEON=y +CONFIG_CRYPTO_GHASH_ARM64_CE=y +CONFIG_CRYPTO_SHA1_ARM64_CE=y +CONFIG_CRYPTO_SHA2_ARM64_CE=y +CONFIG_CRYPTO_SHA512_ARM64_CE=y +CONFIG_CRYPTO_SHA3_ARM64=y +CONFIG_CRYPTO_SM3_ARM64_CE=y +CONFIG_CRYPTO_AES_ARM64_CE_BLK=y +CONFIG_CRYPTO_AES_ARM64_BS=y +CONFIG_CRYPTO_SM4_ARM64_CE=y +CONFIG_CRYPTO_AES_ARM64_CE_CCM=y +CONFIG_CRYPTO_DEV_XILINX_RSA=y +CONFIG_CRYPTO_DEV_ZYNQMP_AES=y +# CONFIG_XZ_DEC_X86 is not set +# CONFIG_XZ_DEC_POWERPC is not set +# CONFIG_XZ_DEC_IA64 is not set +# CONFIG_XZ_DEC_ARM is not set +# CONFIG_XZ_DEC_ARMTHUMB is not set +# CONFIG_XZ_DEC_SPARC is not set +CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=256 +CONFIG_PRINTK_TIME=y +# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_FS=y +# CONFIG_SCHED_DEBUG is not set +# CONFIG_FTRACE is not set +# CONFIG_STRICT_DEVMEM is not set diff --git a/arch/arm64/configs/adi_zynqmp_adsy1100_defconfig b/arch/arm64/configs/adi_zynqmp_adsy1100_defconfig new file mode 100644 index 00000000000000..192830c46d75b7 --- /dev/null +++ b/arch/arm64/configs/adi_zynqmp_adsy1100_defconfig @@ -0,0 +1,380 @@ +CONFIG_KERNEL_ALL_ADI_DRIVERS=y +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_AUDIT=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=16 +CONFIG_CGROUPS=y +CONFIG_NAMESPACES=y +CONFIG_USER_NS=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_EMBEDDED=y +CONFIG_PROFILING=y +CONFIG_ARCH_ZYNQMP=y +CONFIG_NR_CPUS=8 +CONFIG_COMPAT=y +CONFIG_ARMV8_DEPRECATED=y +CONFIG_SWP_EMULATION=y +CONFIG_CP15_BARRIER_EMULATION=y +CONFIG_SETEND_EMULATION=y +# CONFIG_DMI is not set +CONFIG_CPU_IDLE=y +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y +CONFIG_CPUFREQ_DT=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_SLAB=y +# CONFIG_COMPAT_BRK is not set +CONFIG_DEFAULT_MMAP_MIN_ADDR=32768 +CONFIG_TRANSPARENT_HUGEPAGE=y +CONFIG_TRANSPARENT_HUGEPAGE_MADVISE=y +CONFIG_CMA=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM_USER=y +CONFIG_NET_KEY=y +CONFIG_NET_KEY_MIGRATE=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_SYN_COOKIES=y +CONFIG_NETWORK_SECMARK=y +CONFIG_NETFILTER=y +CONFIG_NETFILTER_NETLINK_LOG=y +CONFIG_NF_CONNTRACK=m +CONFIG_NF_CT_NETLINK=m +CONFIG_NETFILTER_XT_MARK=y +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=y +CONFIG_NETFILTER_XT_TARGET_LOG=y +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=y +CONFIG_NETFILTER_XT_MATCH_MAC=y +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_IP_NF_IPTABLES=y +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_TARGET_REJECT=y +CONFIG_IP_NF_MANGLE=y +CONFIG_IP6_NF_IPTABLES=y +CONFIG_IP6_NF_FILTER=y +CONFIG_IP6_NF_TARGET_REJECT=y +CONFIG_IP6_NF_MANGLE=y +CONFIG_BRIDGE_NF_EBTABLES=y +CONFIG_BRIDGE_EBT_T_FILTER=y +CONFIG_BRIDGE_EBT_T_NAT=y +CONFIG_BRIDGE_EBT_MARK_T=y +CONFIG_NET_PKTGEN=y +CONFIG_CAN=y +CONFIG_BT=y +CONFIG_BT_RFCOMM=y +CONFIG_BT_RFCOMM_TTY=y +CONFIG_BT_BNEP=y +CONFIG_BT_BNEP_MC_FILTER=y +CONFIG_BT_BNEP_PROTO_FILTER=y +CONFIG_BT_HIDP=y +CONFIG_BT_LEDS=y +CONFIG_BT_HCIBTUSB=y +CONFIG_BT_HCIBTSDIO=y +CONFIG_BT_HCIUART=y +CONFIG_BT_HCIUART_BCSP=y +CONFIG_BT_HCIUART_ATH3K=y +CONFIG_BT_HCIUART_LL=y +CONFIG_BT_HCIUART_3WIRE=y +CONFIG_BT_HCIUART_INTEL=y +CONFIG_BT_HCIUART_QCA=y +CONFIG_BT_HCIBCM203X=y +CONFIG_BT_HCIBPA10X=y +CONFIG_BT_HCIBFUSB=y +CONFIG_BT_HCIVHCI=y +CONFIG_BT_MRVL=y +CONFIG_BT_MRVL_SDIO=y +CONFIG_BT_ATH3K=y +CONFIG_CFG80211=y +CONFIG_NL80211_TESTMODE=y +CONFIG_CFG80211_CERTIFICATION_ONUS=y +CONFIG_CFG80211_REG_CELLULAR_HINTS=y +CONFIG_CFG80211_REG_RELAX_NO_IR=y +CONFIG_CFG80211_WEXT=y +CONFIG_MAC80211=y +CONFIG_MAC80211_LEDS=y +CONFIG_MAC80211_MESSAGE_TRACING=y +CONFIG_MAC80211_DEBUG_MENU=y +CONFIG_RFKILL=y4 +CONFIG_RFKILL_INPUT=y +CONFIG_RFKILL_GPIO=y +CONFIG_NET_9P=y +CONFIG_PCI=y +# CONFIG_VGA_ARB is not set +CONFIG_PCIE_XILINX_NWL=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_EXTRA_FIRMWARE="app_signed_encrypted_B/flash_image_0x01030000.bin app_signed_encrypted_B/flash_image_0x02000000.bin app_signed_encrypted_B/flash_image_0x20000000.bin app_signed_encrypted_B/flash_image_0x21000000.bin app_signed_encrypted_prod_B/flash_image_0x01030000.bin app_signed_encrypted_prod_B/flash_image_0x02000000.bin app_signed_encrypted_prod_B/flash_image_0x20000000.bin app_signed_encrypted_prod_B/flash_image_0x21000000.bin 204C_M4_L8_NP16_2p5_4x2.bin 204C_M4_L8_NP16_8p0_4x2.bin" +CONFIG_EXTRA_FIRMWARE_DIR="./firmware" +CONFIG_CONNECTOR=y +CONFIG_MTD=y +CONFIG_MTD_TESTS=m +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_OOPS=y +CONFIG_MTD_CFI=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_DATAFLASH=y +CONFIG_MTD_RAW_NAND=y +CONFIG_MTD_NAND_ARASAN=y +CONFIG_MTD_NAND_ECC_SW_BCH=y +CONFIG_MTD_SPI_NOR=y +# CONFIG_MTD_SPI_NOR_USE_4K_SECTORS is not set +CONFIG_MTD_UBI=y +CONFIG_OF_OVERLAY=y +CONFIG_OF_CONFIGFS=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=65536 +CONFIG_ADI_AXI_HSCI=y +CONFIG_XILINX_SDFEC=y +CONFIG_EEPROM_AT24=y +CONFIG_EEPROM_AT25=y +CONFIG_TI_ST=y +CONFIG_MATHWORKS_IP_CORE=y +CONFIG_MWIPCORE=y +CONFIG_MWIPCORE_DMA_STREAMING=y +CONFIG_MWIPCORE_IIO_STREAMING=y +CONFIG_MWIPCORE_IIO_MM=y +CONFIG_MWIPCORE_IIO_SHAREDMEM=y +CONFIG_MATHWORKS_GENERIC_OF=y +# CONFIG_MATHWORKS_GENERIC_PCI is not set +CONFIG_BLK_DEV_SD=y +CONFIG_ATA=y +CONFIG_SATA_AHCI_PLATFORM=y +CONFIG_AHCI_CEVA=y +# CONFIG_ATA_SFF is not set +CONFIG_NETDEVICES=y +CONFIG_TUN=y +CONFIG_MACB=y +CONFIG_XILINX_EMACLITE=y +CONFIG_XILINX_AXI_EMAC=y +CONFIG_AMD_PHY=y +CONFIG_BROADCOM_PHY=y +CONFIG_BCM7XXX_PHY=y +CONFIG_BCM87XX_PHY=y +CONFIG_CICADA_PHY=y +CONFIG_DAVICOM_PHY=y +CONFIG_ICPLUS_PHY=y +CONFIG_LXT_PHY=y +CONFIG_LSI_ET1011C_PHY=y +CONFIG_MARVELL_PHY=y +CONFIG_MICREL_PHY=y +CONFIG_NATIONAL_PHY=y +CONFIG_AT803X_PHY=y +CONFIG_QSEMI_PHY=y +CONFIG_REALTEK_PHY=y +CONFIG_SMSC_PHY=y +CONFIG_STE10XP=y +CONFIG_DP83867_PHY=y +CONFIG_VITESSE_PHY=y +CONFIG_XILINX_GMII2RGMII=y +CONFIG_CAN_XILINXCAN=y +CONFIG_WL18XX=y +CONFIG_WLCORE_SPI=y +CONFIG_WLCORE_SDIO=y +CONFIG_INPUT_EVDEV=y +CONFIG_KEYBOARD_GPIO_POLLED=y +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_MAX310X=y +CONFIG_SERIAL_UARTLITE=y +CONFIG_SERIAL_UARTLITE_CONSOLE=y +CONFIG_SERIAL_XILINX_PS_UART=y +CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y +CONFIG_SERIAL_DEV_BUS=y +# CONFIG_HW_RANDOM is not set +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX_GPMUX=y +CONFIG_I2C_MUX_PCA9541=y +CONFIG_I2C_MUX_PCA954x=y +CONFIG_I2C_CADENCE=y +CONFIG_I2C_XILINX=y +CONFIG_SPI_CADENCE=y +CONFIG_SPI_XILINX=y +CONFIG_SPI_ZYNQMP_GQSPI=y +CONFIG_PINCTRL=y +CONFIG_GPIO_SYSFS=y +CONFIG_GPIO_XILINX=y +CONFIG_GPIO_ZYNQ=y +CONFIG_GPIO_PCA953X=y +CONFIG_GPIO_TPS65086=y +CONFIG_SENSORS_IIO_HWMON=y +CONFIG_SENSORS_JC42=y +CONFIG_SENSORS_LM87=y +CONFIG_SENSORS_LM90=y +CONFIG_SENSORS_MAX20751=y +CONFIG_SENSORS_INA2XX=y +CONFIG_WATCHDOG=y +CONFIG_XILINX_WATCHDOG=y +CONFIG_CADENCE_WATCHDOG=y +CONFIG_MFD_TPS65086=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_REGULATOR_GPIO=y +CONFIG_REGULATOR_TPS65086=y +CONFIG_VIDEO_XILINX=y +CONFIG_VIDEO_XILINX_CSI2RXSS=y +CONFIG_VIDEO_XILINX_AXI4S_SWITCH=y +CONFIG_VIDEO_XILINX_CFA=y +CONFIG_VIDEO_XILINX_CRESAMPLE=y +CONFIG_VIDEO_XILINX_DEMOSAIC=y +CONFIG_VIDEO_XILINX_GAMMA=y +CONFIG_VIDEO_XILINX_HLS=y +CONFIG_VIDEO_XILINX_REMAPPER=y +CONFIG_VIDEO_XILINX_RGB2YUV=y +CONFIG_VIDEO_XILINX_SCALER=y +CONFIG_VIDEO_XILINX_MULTISCALER=y +CONFIG_VIDEO_XILINX_SDIRXSS=y +CONFIG_VIDEO_XILINX_SWITCH=y +CONFIG_VIDEO_XILINX_TPG=y +CONFIG_VIDEO_XILINX_VPSS_CSC=y +CONFIG_VIDEO_XILINX_VPSS_SCALER=y +CONFIG_VIDEO_XILINX_SCD=y +CONFIG_VIDEO_XILINX_M2M=y +CONFIG_DRM_ZYNQMP_DPSUB=y +CONFIG_DRM_XLNX=y +CONFIG_DRM_XLNX_BRIDGE=y +CONFIG_DRM_XLNX_BRIDGE_DEBUG_FS=y +CONFIG_DRM_XLNX_DSI=y +CONFIG_DRM_XLNX_MIXER=y +CONFIG_DRM_XLNX_PL_DISP=y +CONFIG_DRM_XLNX_SDI=y +CONFIG_DRM_XLNX_BRIDGE_CSC=y +CONFIG_DRM_XLNX_BRIDGE_SCALER=y +CONFIG_DRM_XLNX_BRIDGE_VTC=y +CONFIG_FB_XILINX=y +CONFIG_FRAMEBUFFER_CONSOLE=y +# CONFIG_SND_DRIVERS is not set +# CONFIG_SND_PCI is not set +CONFIG_SND_SOC_XILINX_DP=y +CONFIG_SND_SOC_XILINX_SDI=y +CONFIG_SND_SOC_XILINX_I2S=y +CONFIG_SND_SOC_XILINX_AUDIO_FORMATTER=y +CONFIG_SND_SOC_XILINX_SPDIF=y +CONFIG_SND_SOC_XILINX_PL_SND_CARD=y +CONFIG_USB_OTG_FSM=y +CONFIG_USB_DWC3_ULPI=y +CONFIG_TYPEC_TPS6598X=y +CONFIG_MMC=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PLTFM=y +CONFIG_MMC_SDHCI_OF_ARASAN=y +CONFIG_LEDS_BRIGHTNESS_HW_CHANGED=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_ONESHOT=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_BACKLIGHT=y +CONFIG_LEDS_TRIGGER_CPU=y +CONFIG_LEDS_TRIGGER_GPIO=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_LEDS_TRIGGER_TRANSIENT=y +CONFIG_LEDS_TRIGGER_CAMERA=y +CONFIG_EDAC=y +CONFIG_EDAC_SYNOPSYS=y +CONFIG_EDAC_ZYNQMP_OCM=y +CONFIG_RTC_CLASS=y +CONFIG_RTC_DRV_ZYNQMP=y +CONFIG_DMADEVICES=y +CONFIG_AXI_DMAC=y +CONFIG_XILINX_ZYNQMP_DMA=y +CONFIG_DMATEST=y +CONFIG_UIO=y +CONFIG_UIO_PDRV_GENIRQ=m +CONFIG_UIO_DMEM_GENIRQ=m +CONFIG_UIO_XILINX_APM=y +CONFIG_XILINX_FCLK=y +CONFIG_COMMON_CLK_SI5341=y +CONFIG_COMMON_CLK_SI514=y +CONFIG_COMMON_CLK_SI570=y +CONFIG_COMMON_CLK_SI5324=y +CONFIG_COMMON_CLK_AXI_CLKGEN=y +CONFIG_XILINX_VCU=m +CONFIG_COMMON_CLK_XLNX_CLKWZRD=y +CONFIG_ARM_SMMU=y +CONFIG_REMOTEPROC=y +CONFIG_ZYNQMP_R5_REMOTEPROC=m +CONFIG_AD9088=y +CONFIG_AD9088_REV_B0=y +CONFIG_XILINX_AMS=y +# CONFIG_CF_AXI_DDS_AD9162 is not set +CONFIG_ADF4382=y +CONFIG_LTC6948=y +CONFIG_XILINX_INTC=y +CONFIG_IRQCHIP_XILINX_INTC_MODULE_SUPPORT_EXPERIMENTAL=y +CONFIG_PHY_XILINX_ZYNQMP=y +CONFIG_RAS=y +CONFIG_NVMEM_ZYNQMP=y +CONFIG_FPGA=y +CONFIG_FPGA_MGR_DEBUG_FS=y +CONFIG_FPGA_MGR_XILINX_SELECTMAP=y +CONFIG_XILINX_AFI_FPGA=y +CONFIG_FPGA_BRIDGE=y +CONFIG_XILINX_PR_DECOUPLER=y +CONFIG_FPGA_REGION=y +CONFIG_OF_FPGA_REGION=y +CONFIG_FPGA_MGR_ZYNQMP_FPGA=y +CONFIG_MUX_GPIO=y +CONFIG_EXT2_FS=y +CONFIG_EXT3_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_BTRFS_FS=y +CONFIG_QUOTA=y +CONFIG_QFMT_V2=y +CONFIG_AUTOFS4_FS=y +CONFIG_FUSE_FS=y +CONFIG_OVERLAY_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_HUGETLBFS=y +CONFIG_ECRYPT_FS=y +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_SUMMARY=y +CONFIG_JFFS2_FS_XATTR=y +CONFIG_JFFS2_COMPRESSION_OPTIONS=y +CONFIG_JFFS2_LZO=y +CONFIG_JFFS2_RUBIN=y +CONFIG_CRAMFS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_NFS_V4_1=y +CONFIG_NFS_V4_2=y +CONFIG_ROOT_NFS=y +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set +CONFIG_CRYPTO_CRCT10DIF=y +CONFIG_CRYPTO_USER_API_SKCIPHER=y +CONFIG_CRYPTO_DEV_XILINX_RSA=y +CONFIG_CRYPTO_DEV_ZYNQMP_AES=y +CONFIG_DMA_RESTRICTED_POOL=y +CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_MBYTES=256 +CONFIG_PRINTK_TIME=y +CONFIG_MAGIC_SYSRQ=y +# CONFIG_SCHED_DEBUG is not set +# CONFIG_FTRACE is not set diff --git a/arch/microblaze/boot/dts/vcu118_ad9082_204c_txmode_36_rxmode_28_lr_16_706Gbps.dts b/arch/microblaze/boot/dts/vcu118_ad9082_204c_txmode_36_rxmode_28_lr_16_706Gbps.dts new file mode 100644 index 00000000000000..9334784bc4f15f --- /dev/null +++ b/arch/microblaze/boot/dts/vcu118_ad9082_204c_txmode_36_rxmode_28_lr_16_706Gbps.dts @@ -0,0 +1,397 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Analog Devices AD9082-FMC-EBZ + * https://wiki.analog.com/resources/tools-software/linux-drivers/iio-mxfe/ad9081 + * https://wiki.analog.com/resources/eval/user-guides/ad9081_fmca_ebz/ad9081_fmca_ebz_hdl + * + * hdl_project: + * board_revision: <> + * + * Copyright (C) 2022 Analog Devices Inc. + */ + +#include "vcu118_ad9081.dts" +#include + +#define HMC7044_FPGA_XCVR_CLKDIV 16 +#define HMC7044_FPGA_LINK_CLKDIV_TX 16 +#define HMC7044_FPGA_LINK_CLKDIV_RX 16 +#define HMC7044_SYSREF_CLKDIV 256 + +/* TX path */ +#define AD9081_DAC_FREQUENCY 10800000000 +#define AD9081_TX_MAIN_INTERPOLATION 2 +#define AD9081_TX_CHAN_INTERPOLATION 1 +#define AD9081_TX_MAIN_NCO_SHIFT 0 +#define AD9081_TX_CHAN_NCO_SHIFT 0 + +#define AD9081_GAIN 1024 + +#define AD9081_TX_JESD_MODE 36 +#define AD9081_TX_JESD_SUBCLASS 1 +#define AD9081_TX_JESD_VERSION 2 +#define AD9081_TX_JESD_M 2 +#define AD9081_TX_JESD_F 3 +#define AD9081_TX_JESD_K 256 +#define AD9081_TX_JESD_N 12 +#define AD9081_TX_JESD_NP 12 +#define AD9081_TX_JESD_CS 0 +#define AD9081_TX_JESD_L 8 +#define AD9081_TX_JESD_S 8 +#define AD9081_TX_JESD_HD 1 + +#define AD9081_JRX_TPL_PHASE_ADJUST 15 + +/* RX path */ +#define AD9081_ADC_FREQUENCY 5400000000 +#define AD9081_RX_MAIN_DECIMATION 1 +#define AD9081_RX_CHAN_DECIMATION 1 +#define AD9081_RX_MAIN_NCO_SHIFT 0 +#define AD9081_RX_CHAN_NCO_SHIFT 0 + +#define AD9081_RX_JESD_MODE 28 +#define AD9081_RX_JESD_SUBCLASS 1 +#define AD9081_RX_JESD_VERSION 2 +#define AD9081_RX_JESD_M 2 +#define AD9081_RX_JESD_F 3 +#define AD9081_RX_JESD_K 256 +#define AD9081_RX_JESD_N 12 +#define AD9081_RX_JESD_NP 12 +#define AD9081_RX_JESD_CS 0 +#define AD9081_RX_JESD_L 8 +#define AD9081_RX_JESD_S 8 +#define AD9081_RX_JESD_HD 0 + +&amba_pl { + axi_spi3: spi@44aa0000 { + #address-cells = <1>; + #size-cells = <0>; + bits-per-word = <8>; + compatible = "xlnx,axi-quad-spi-3.2", "xlnx,xps-spi-2.00.a"; + fifo-size = <16>; + interrupt-names = "ip2intc_irpt"; + interrupt-parent = <&axi_intc>; + interrupts = <7 0>; + num-cs = <0x8>; + reg = <0x44aa0000 0x1000>; + xlnx,num-ss-bits = <0x8>; + xlnx,spi-mode = <0>; + }; +}; + +&axi_ad9081_adxcvr_rx { + adi,sys-clk-select = ; + adi,out-clk-select = ; +}; + +&axi_ad9081_adxcvr_tx { + adi,sys-clk-select = ; + adi,out-clk-select = ; +}; + +&axi_ad9081_core_tx { + compatible = "adi,axi-ad9081-tx-1.0-real"; + sampl_clk-clock-scales = <1 10>; +}; + +&hmc7044 { + + adi,pll2-output-frequency = <2700000000>; /* 3037500000*/ + adi,pll1-clkin-frequencies = <0 125000000 0 0>; + + di,pll1-ref-prio-ctrl = <0xE1>; /* prefer CLKIN1 -> CLKIN0 -> CLKIN2 -> CLKIN3 */ + adi,pll1-ref-autorevert-enable; + adi,clkin0-buffer-mode = <0>; + + /delete-property/ adi,pfd1-maximum-limit-frequency-hz; + /delete-property/ jesd204-sysref-provider; + /delete-property/ adi,jesd204-max-sysref-frequency-hz; + adi,hmc-two-level-tree-sync-en; + adi,sync-through-pll2-force-r2-eq-1; + + adi,pfd1-maximum-limit-frequency-hz = <7000000>; /* 7 MHz */ + + hmc7044_c2: channel@2 { + reg = <2>; + adi,extended-name = "DEV_REFCLK"; + adi,divider = <8>; // 600 + adi,driver-mode = ; // LVDS + }; + + hmc7044_c3: channel@3 { + reg = <3>; + adi,extended-name = "DEV_SYSREF"; + adi,divider = ; // + adi,driver-mode = ; // LVDS + adi,jesd204-sysref-chan; + //adi,startup-mode-dynamic-enable; + }; + + hmc7044_c6: channel@6 { + reg = <6>; + adi,extended-name = "CORE_CLK_TX"; + adi,divider = ; // 375 + adi,driver-mode = ; // LVDS + }; + + hmc7044_c8: channel@8 { + reg = <8>; + adi,extended-name = "CORE_CLK_RX"; + adi,divider = ; // 375 + adi,driver-mode = ; // LVDS + }; + + hmc7044_c12: channel@12 { + reg = <12>; + adi,extended-name = "FPGA_REFCLK"; + adi,divider = ; // 375 + adi,driver-mode = ; // LVDS + }; + + hmc7044_c13: channel@13 { + reg = <13>; + adi,extended-name = "FPGA_SYSREF"; + adi,divider = ; // + adi,driver-mode = ; // LVDS + adi,jesd204-sysref-chan; + }; +}; + +&trx0_ad9081 { + compatible = "adi,ad9082"; + + rx_sampl_clk-clock-scales = <1 10>; + tx_sampl_clk-clock-scales = <1 10>; + + jesd204-stop-states = ; + + adi,sysref-ac-coupling-enable; + + /delete-node/ adi,tx-dacs; + /delete-node/ adi,rx-adcs; + + adi,tx-dacs { + #size-cells = <0>; + #address-cells = <1>; + adi,dac-frequency-hz = /bits/ 64 ; + + adi,main-data-paths { + #address-cells = <1>; + #size-cells = <0>; + adi,interpolation = ; + trx0_ad9081_dac0: dac@0 { + reg = <0>; + adi,crossbar-select = <&trx0_ad9081_tx_fddc_chan0>; + adi,nco-frequency-shift-hz = /bits/ 64 ; /* 100 MHz */ + }; + trx0_ad9081_dac1: dac@1 { + reg = <1>; + adi,crossbar-select = <&trx0_ad9081_tx_fddc_chan1>; + adi,nco-frequency-shift-hz = /bits/ 64 ; /* 100 MHz */ + }; + }; + + adi,channelizer-paths { + #address-cells = <1>; + #size-cells = <0>; + adi,interpolation = ; + trx0_ad9081_tx_fddc_chan0: channel@0 { + reg = <0>; + adi,gain = ; /* value * 10^(gain_dB/20) */ + adi,nco-frequency-shift-hz = /bits/ 64 ; + }; + trx0_ad9081_tx_fddc_chan1: channel@1 { + reg = <1>; + adi,gain = ; /* value * 10^(gain_dB/20) */ + adi,nco-frequency-shift-hz = /bits/ 64 ; + }; + }; + + adi,jesd-links { + #size-cells = <0>; + #address-cells = <1>; + trx0_ad9081_tx_jesd_l0: link@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + adi,tpl-phase-adjust = ; + adi,logical-lane-mapping = /bits/ 8 <0 2 7 6 1 5 4 3>; + adi,link-mode = ; /* JESD Quick Configuration Mode */ + adi,subclass = ; /* JESD SUBCLASS 0,1,2 */ + adi,version = ; /* JESD VERSION 0=204A,1=204B,2=204C */ + adi,dual-link = <0>; /* JESD Dual Link Mode */ + adi,converters-per-device = ; /* JESD M */ + adi,octets-per-frame = ; /* JESD F */ + adi,frames-per-multiframe = ; /* JESD K */ + adi,converter-resolution = ; /* JESD N */ + adi,bits-per-sample = ; /* JESD NP' */ + adi,control-bits-per-sample = ; /* JESD CS */ + adi,lanes-per-device = ; /* JESD L */ + adi,samples-per-converter-per-frame = ; /* JESD S */ + adi,high-density = ; /* JESD HD */ + + adi,tpl-phase-adjust = <0x3>; + }; + }; + }; + + adi,rx-adcs { + #size-cells = <0>; + #address-cells = <1>; + adi,adc-frequency-hz = /bits/ 64 ; + adi,nyquist-zone = ; + adi,main-data-paths { + #address-cells = <1>; + #size-cells = <0>; + trx0_ad9081_adc0: adc@0 { + reg = <0>; + adi,decimation = ; + adi,nco-frequency-shift-hz = /bits/ 64 ; + adi,nco-mixer-mode = ; + //adi,crossbar-select = <&trx0_ad9081_rx_fddc_chan0>, <&trx0_ad9081_rx_fddc_chan2>; /* Static for now */ + }; + trx0_ad9081_adc1: adc@1 { + reg = <1>; + adi,decimation = ; + adi,nco-frequency-shift-hz = /bits/ 64 ; + adi,nco-mixer-mode = ; + //adi,crossbar-select = <&trx0_ad9081_rx_fddc_chan0>, <&trx0_ad9081_rx_fddc_chan2>; /* Static for now */ + }; + }; + adi,channelizer-paths { + #address-cells = <1>; + #size-cells = <0>; + trx0_ad9081_rx_fddc_chan0: channel@0 { + reg = <0>; + adi,decimation = ; + adi,gain = ; /* value * 10^(gain_dB/20) */ + adi,nco-frequency-shift-hz = /bits/ 64 ; + }; + trx0_ad9081_rx_fddc_chan1: channel@1 { + reg = <1>; + adi,decimation = ; + adi,gain = ; /* value * 10^(gain_dB/20) */ + adi,nco-frequency-shift-hz = /bits/ 64 ; + }; + }; + adi,jesd-links { + #size-cells = <0>; + #address-cells = <1>; + trx0_ad9081_rx_jesd_l0: link@0 { + reg = <0>; + adi,converter-select = + <&trx0_ad9081_rx_fddc_chan0 FDDC_I>, <&trx0_ad9081_rx_fddc_chan0 FDDC_Q>; + + adi,logical-lane-mapping = /bits/ 8 <2 0 7 6 5 4 3 1>; + adi,link-mode = ; /* JESD Quick Configuration Mode */ + adi,subclass = ; /* JESD SUBCLASS 0,1,2 */ + adi,version = ; /* JESD VERSION 0=204A,1=204B,2=204C */ + adi,dual-link = <0>; /* JESD Dual Link Mode */ + adi,device-id = <3>; + adi,converters-per-device = ; /* JESD M */ + adi,octets-per-frame = ; /* JESD F */ + adi,frames-per-multiframe = ; /* JESD K */ + adi,converter-resolution = ; /* JESD N */ + adi,bits-per-sample = ; /* JESD NP' */ + adi,control-bits-per-sample = ; /* JESD CS */ + adi,lanes-per-device = ; /* JESD L */ + adi,samples-per-converter-per-frame = ; /* JESD S */ + adi,high-density = ; /* JESD HD */ + }; + }; + }; + + +}; + +#if 0 +&axi_spi3 { + hmc7044_ext_synchrona: hmc7044-ext@0 { + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + compatible = "adi,hmc7044"; + reg = <0>; + spi-max-frequency = <100000>; + + adi,vcxo-frequency = <100000000>; + + adi,clkin0-buffer-mode = ; + adi,clkin1-buffer-mode = ; + adi,clkin2-buffer-mode = ; + adi,clkin3-buffer-mode = ; + adi,oscin-buffer-mode = <0x15>; + + adi,pll1-clkin-frequencies = + <40000000 40000000 40000000 40000000>; + + /* CLKIN0 -> CLKIN1 -> CLKIN2 -> CLKIN3 */ + adi,pll1-ref-prio-ctrl = <0xE4>; + adi,pll1-ref-autorevert-enable; + adi,pll1-loop-bandwidth-hz = <200>; + adi,pfd1-maximum-limit-frequency-hz = <3840000>; + + adi,pll2-output-frequency = <3000000000>; + + adi,pulse-generator-mode = ; + adi,sync-pin-mode = ; + + adi,gpi-controls = <0x00 0x00 0x00 0x00>; + adi,gpo-controls = <0x1f 0x2b 0x00 0x00>; + + /* JESD204-FSM */ + jesd204-device; + #jesd204-cells = <2>; + jesd204-sysref-provider; + adi,hmc-two-level-tree-sync-en; + adi,jesd204-max-sysref-frequency-hz = <2000000>; + + clock-output-names = + "hmc7044_e_out0", "hmc7044_e_out1", + "hmc7044_e_out2", "hmc7044_e_out3", + "hmc7044_e_out4", "hmc7044_e_out5", + "hmc7044_e_out6_RFSYNC_A", "hmc7044_e_out7_REFCLK_A", + "hmc7044_e_out8","hmc7044_e_out9", + "hmc7044_e_out10_REFCLK_B", "hmc7044_e_out11_RFSYNC_B", + "hmc7044_e_out12", "hmc7044_e_out13"; + + hmc7044_ext_c6: channel@6 { + reg = <6>; + adi,extended-name = "RFSYNC_A"; + adi,divider = <1024>; /* set by the jesd204-fsm */ + adi,driver-mode = ; + adi,driver-impedance-mode = + ; + adi,startup-mode-dynamic-enable; + adi,high-performance-mode-disable; + adi,force-mute-enable; + }; + + hmc7044_ext_c7: channel@7 { + reg = <7>; + adi,extended-name = "REFCLK_A"; + adi,divider = <6>; + adi,driver-mode = ; + }; + + hmc7044_ext_c10: channel@10 { + reg = <10>; + adi,extended-name = "REFCLK_B"; + adi,divider = <6>; + adi,driver-mode = ; + }; + + hmc7044_ext_c11: channel@11 { + reg = <11>; + adi,extended-name = "RFSYNC_B"; + adi,divider = <1024>; /* set by the jesd204-fsm */ + adi,driver-mode = ; + adi,driver-impedance-mode = + ; + adi,startup-mode-dynamic-enable; + adi,high-performance-mode-disable; + adi,force-mute-enable; + }; + }; +}; +#endif \ No newline at end of file diff --git a/arch/microblaze/boot/dts/vcu118_ad9084.dts b/arch/microblaze/boot/dts/vcu118_ad9084.dts new file mode 100644 index 00000000000000..a82e91c258c32b --- /dev/null +++ b/arch/microblaze/boot/dts/vcu118_ad9084.dts @@ -0,0 +1,814 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Analog Devices AD9084-FMC-EBZ + * https://wiki.analog.com/resources/tools-software/linux-drivers/iio-mxfe/ad9084 + * https://wiki.analog.com/resources/eval/user-guides/ad9084_fmca_ebz/ad9084_fmca_ebz_hdl + * + * hdl_project: + * board_revision: <> + * + * Copyright (C) 2025 Analog Devices Inc. + */ +/dts-v1/; + +#include "vcu118.dtsi" +#include +#include +#include + +#define fmc_i2c fmcp_hspc_iic +#define fmc_spi axi_spi + +#ifndef DEVICE_PROFILE_NAME +#define DEVICE_PROFILE_NAME "204C_M4_L8_NP16_20p0_4x4.bin" +#endif + +#ifndef OUT_CLK_SELECT +#define OUT_CLK_SELECT XCVR_PROGDIV_CLK +#endif + +#ifndef SYS_CLK_SELECT +#define SYS_CLK_SELECT XCVR_QPLL +#endif + +#ifndef HMC7044_PLL2_FREQ +#define HMC7044_PLL2_FREQ (2500000000) // 2.5 GHz (2150...3200 MHz range) +#endif + +#if WITH_AION +#ifndef SYSREF_CLK_MHz +#define SYSREF_CLK_MHz (10000000) +#endif +#ifndef AION_VCO_FREQ_HZ +#define AION_VCO_FREQ_HZ (2500000000) // 2.5 GHz (2375...2625 MHz range) +#endif +#define JESD_SUBCLASS 1 +#else +#define JESD_SUBCLASS 0 +#endif + + +/ { + model = "Analog Devices AD9084-FMCA-EBZ @Xilinx/vcu118"; + + clocks { + clkin_125: clock@0 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "clkin_125"; + }; + }; + + axi-jesd204-rx@0 { + compatible = "adi,iio-fake-platform-device"; + adi,faked-dev = <&axi_ad9084_rx_jesd>; + adi,attribute-names = + "status", "encoder", "lane0_info", "lane1_info", + "lane2_info", "lane3_info", "lane4_info", + "lane5_info", "lane6_info", "lane7_info", + "lane8_info", "lane9_info", "lane10_info", + "lane11_info", "lane12_info", "lane13_info", + "lane14_info", "lane15_info"; + label = "axi-jesd204-rx"; + }; + + axi-jesd204-tx@1 { + compatible = "adi,iio-fake-platform-device"; + adi,faked-dev = <&axi_ad9084_tx_jesd>; + adi,attribute-names = "status", "encoder"; + label = "axi-jesd204-tx"; + }; + + axi-adxcvr-rx@2 { + compatible = "adi,iio-fake-platform-device"; + adi,faked-dev = <&axi_ad9084_adxcvr_rx>; + adi,attribute-names = + "eyescan_info", "prbs_status", "prbs_counter_reset", + "prescale", "enable", "prbs_error_counters", "reg_access", + "prbs_select", "eye_data_available", "eye_data_partial"; + label = "axi-adxcvr-rx"; + }; + + axi-adxcvr-tx@4 { + compatible = "adi,iio-fake-platform-device"; + adi,faked-dev = <&axi_ad9084_adxcvr_tx>; + adi,attribute-names = "prbs_select", "prbs_error_inject", "reg_access"; + label = "axi-adxcvr-tx"; + }; +#if ASYNM_A_B_MODE + axi-jesd204-rx-b@0 { + compatible = "adi,iio-fake-platform-device"; + adi,faked-dev = <&axi_ad9084_rx_jesd_b>; + adi,attribute-names = + "status", "encoder", "lane0_info", "lane1_info", + "lane2_info", "lane3_info", "lane4_info", + "lane5_info", "lane6_info", "lane7_info", + "lane8_info", "lane9_info", "lane10_info", + "lane11_info", "lane12_info", "lane13_info", + "lane14_info", "lane15_info"; + label = "axi-jesd204-rx-b"; + }; + + axi-jesd204-tx-b@1 { + compatible = "adi,iio-fake-platform-device"; + adi,faked-dev = <&axi_ad9084_tx_jesd_b>; + adi,attribute-names = "status", "encoder"; + label = "axi-jesd204-tx-b"; + }; + + axi-adxcvr-rx-b@2 { + compatible = "adi,iio-fake-platform-device"; + adi,faked-dev = <&axi_ad9084_adxcvr_rx_b>; + adi,attribute-names = + "eyescan_info", "prbs_status", "prbs_counter_reset", + "prescale", "enable", "prbs_error_counters", "reg_access", + "prbs_select", "eye_data_available", "eye_data_partial"; + label = "axi-adxcvr-rx-b"; + }; + + axi-adxcvr-tx-b@4 { + compatible = "adi,iio-fake-platform-device"; + adi,faked-dev = <&axi_ad9084_adxcvr_tx_b>; + adi,attribute-names = "prbs_select", "prbs_error_inject", "reg_access"; + label = "axi-adxcvr-tx-b"; + }; + +#endif + +}; + +&axi_intc { + xlnx,kind-of-intr = <0xffff0410>; + xlnx,num-intr-inputs = <0x17>; +}; + +&axi_ethernet { + local-mac-address = [00 0a 35 00 90 84]; +}; + +&axi_iic_main { + compatible = "xlnx,axi-iic-2.1", "xlnx,xps-iic-2.10.a"; /* Needed otherwise the HWMON devices would fail */ +}; + +&fmc_i2c { + eeprom@50 { + compatible = "at24,24c02"; + reg = <0x50>; + }; + // ltc2977@5c { + // compatible = "lltc,ltc2977"; + // reg = <0x5C>; + // }; + // ltm4681_c23@4f { + // compatible = "lltc,ltm4680"; + // reg = <0x4F>; + // }; + // ltm4681_c01@4e { + // compatible = "lltc,ltm4680"; + // reg = <0x4E>; + // }; +}; + +&amba_pl { + rx_dma: dma@7c420000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x7c420000 0x10000>; + #dma-cells = <1>; + #clock-cells = <0>; + interrupt-parent = <&axi_intc>; + interrupts = <12 2>; + + clocks = <&clk_bus_0>; + }; + + tx_dma: dma@7c430000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x7c430000 0x10000>; + #dma-cells = <1>; + #clock-cells = <0>; + interrupt-parent = <&axi_intc>; + interrupts = <13 2>; + clocks = <&clk_bus_0>; + + }; + + axi_ad9084_core_rx: axi-ad9084-rx-hpc@44a10000 { + compatible = "adi,axi-ad9081-rx-1.0"; + reg = <0x44a10000 0x8000>; + dmas = <&rx_dma 0>; + dma-names = "rx"; + spibus-connected = <&trx0_ad9084>; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_rx_jesd 0 FRAMER_LINK_A0_RX>; + }; + + axi_ad9084_core_tx: axi-ad9084-tx-hpc@44b10000 { + compatible = "adi,axi-ad9081-tx-1.0"; + reg = <0x44b10000 0x4000>; + dmas = <&tx_dma 0>; + dma-names = "tx"; + clocks = <&trx0_ad9084 1>; + clock-names = "sampl_clk"; + spibus-connected = <&trx0_ad9084>; + adi,axi-pl-fifo-enable; + adi,axi-data-offload-connected = <&axi_data_offload_tx>; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_tx_jesd 0 DEFRAMER_LINK_A0_TX>; + }; + + axi_ad9084_rx_jesd: axi-jesd204-rx@44a90000 { + compatible = "adi,axi-jesd204-rx-1.0"; + reg = <0x44a90000 0x4000>; + interrupt-parent = <&axi_intc>; + interrupts = <14 2>; + + clocks = <&clk_bus_0>, <&axi_ad9084_adxcvr_rx 1>, <&hmc7044 8>, <&axi_ad9084_adxcvr_rx 0>; + clock-names = "s_axi_aclk", "link_clk", "device_clk", "lane_clk"; + + #clock-cells = <0>; + clock-output-names = "jesd_rx_lane_clk"; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_adxcvr_rx 0 FRAMER_LINK_A0_RX>; + }; + + axi_ad9084_tx_jesd: axi-jesd204-tx@44b90000 { + compatible = "adi,axi-jesd204-tx-1.0"; + reg = <0x44b90000 0x4000>; + + interrupt-parent = <&axi_intc>; + interrupts = <15 2>; + + clocks = <&clk_bus_0>, <&axi_ad9084_adxcvr_tx 1>, <&hmc7044 9>, <&axi_ad9084_adxcvr_tx 0>; + clock-names = "s_axi_aclk", "link_clk", "device_clk", "lane_clk"; + + #clock-cells = <0>; + clock-output-names = "jesd_tx_lane_clk"; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_adxcvr_tx 0 DEFRAMER_LINK_A0_TX>; + }; + + axi_ad9084_adxcvr_rx: axi-adxcvr-rx@44a60000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "adi,axi-adxcvr-1.0"; + reg = <0x44a60000 0x1000>; + + clocks = <&hmc7044 10>; /* div40 is controlled by axi_ad9084_rx_jesd */ + clock-names = "conv"; + + #clock-cells = <1>; + clock-output-names = "rx_gt_clk", "rx_out_clk"; + + adi,sys-clk-select = ; + adi,out-clk-select = ; + adi,use-lpm-enable; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&hmc7044 0 FRAMER_LINK_A0_RX>; + }; + + axi_ad9084_adxcvr_tx: axi-adxcvr-tx@44b60000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "adi,axi-adxcvr-1.0"; + reg = <0x44b60000 0x1000>; + + clocks = <&hmc7044 10>; /* div40 is controlled by axi_ad9084_tx_jesd */ + clock-names = "conv"; + + #clock-cells = <1>; + clock-output-names = "tx_gt_clk", "tx_out_clk"; + + adi,sys-clk-select = ; + adi,out-clk-select = ; /* XCVR_PROGDIV_CLK */ + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&hmc7044 0 DEFRAMER_LINK_A0_TX>; + }; + + axi_sysid_0: axi-sysid-0@45000000 { + compatible = "adi,axi-sysid-1.00.a"; + reg = <0x45000000 0x10000>; + }; + + axi_data_offload_rx: data_offload_rx@7c450000 { + compatible = "adi,axi-data-offload-1.0.a"; + reg = <0x7c450000 0x10000>; + }; + + axi_data_offload_tx: data_offload_tx@7c440000 { + compatible = "adi,axi-data-offload-1.0.a"; + reg = <0x7c440000 0x10000>; + }; + + hsci_clkgen: axi-clkgen@44ad0000 { + compatible = "adi,axi-clkgen-2.00.a"; + reg = <0x44ad0000 0x10000>; + #clock-cells = <0>; + clocks = <&clk_bus_0>, <&clk_bus_0>; + clock-names = "s_axi_aclk", "clkin1"; + clock-output-names = "hsci_clkgen"; + }; + + axi_hsci: axi_hsci@7c500000 { + compatible = "adi,axi-hsci-1.0.a"; + reg = <0x7c500000 0x40000>; + clocks = <&hsci_clkgen>; + clock-names = "pclk"; + + adi,hsci-interface-speed-mhz = <800>; + }; + +#if WITH_AXI_AION_TRIG + axi_aion_trig: axi_aion_trig@7c600000 { + compatible = "adi,axi-aion-trig-1.0.a"; + reg = <0x7c600000 0x1000>; + clocks = <&hmc7044 8>; + clock-names = "device_clk"; + + jesd204-device; + #jesd204-cells = <2>; + + io-channels = <&adf4030 8>; + io-channel-names = "bsync"; + }; +#endif /* WITH_AXI_AION_TRIG */ + + axi_spi_2: spi@44A80000 { + #address-cells = <1>; + #size-cells = <0>; + bits-per-word = <8>; + compatible = "xlnx,axi-quad-spi-3.2", "xlnx,xps-spi-2.00.a"; + fifo-size = <16>; + interrupt-names = "ip2intc_irpt"; + interrupt-parent = <&axi_intc>; + interrupts = <16 0>; + num-cs = <0x8>; + reg = <0x44A80000 0x1000>; + xlnx,num-ss-bits = <0x8>; + xlnx,spi-mode = <0>; + }; + +#if ASYNM_A_B_MODE + rx_dma_b: dma@7c470000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x7c470000 0x10000>; + #dma-cells = <1>; + #clock-cells = <0>; + interrupt-parent = <&axi_intc>; + interrupts = <5 2>; + + clocks = <&clk_bus_0>; + }; + + tx_dma_b: dma@7c480000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x7c480000 0x10000>; + #dma-cells = <1>; + #clock-cells = <0>; + interrupt-parent = <&axi_intc>; + interrupts = <6 2>; + clocks = <&clk_bus_0>; + + }; + + axi_ad9084_core_rx_b: axi-ad9084b-rx-b@44ab0000 { + compatible = "adi,axi-adc-tpl-so-10.0.a"; + reg = <0x44ab0000 0x8000>; + dmas = <&rx_dma_b 0>; + dma-names = "rx"; + clocks = <&trx0_ad9084 0>; /* FIXME */ + clock-names = "sampl_clk"; + // jesd204-device; + // #jesd204-cells = <2>; + // jesd204-inputs = <&axi_ad9084_rx_jesd_b 0 FRAMER_LINK_B0_RX>; + }; + + axi_ad9084_core_tx_b: axi-ad9084-tx-b@44bb0000 { + compatible = "adi,axi-ad9081-tx-1.0"; + reg = <0x44bb0000 0x4000>; + dmas = <&tx_dma_b 0>; + dma-names = "tx"; + clocks = <&trx0_ad9084 1>; /* FIXME */ + clock-names = "sampl_clk"; + adi,axi-pl-fifo-enable; + adi,axi-data-offload-connected = <&axi_data_offload_tx_b>; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_tx_jesd_b 0 DEFRAMER_LINK_B0_TX>; + }; + + axi_ad9084_rx_jesd_b: axi-jesd204-rx-b@44ac0000 { + compatible = "adi,axi-jesd204-rx-1.0"; + reg = <0x44ac0000 0x4000>; + interrupt-parent = <&axi_intc>; + interrupts = <7 2>; + + clocks = <&clk_bus_0>, <&axi_ad9084_adxcvr_rx_b 1>, <&hmc7044 11>, <&axi_ad9084_adxcvr_rx_b 0>; + clock-names = "s_axi_aclk", "link_clk", "device_clk", "lane_clk"; + + #clock-cells = <0>; + clock-output-names = "jesd_rx_lane_clk_b"; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_adxcvr_rx_b 0 FRAMER_LINK_B0_RX>; + }; + + axi_ad9084_tx_jesd_b: axi-jesd204-tx-b@44bc0000 { + compatible = "adi,axi-jesd204-tx-1.0"; + reg = <0x44bc0000 0x4000>; + + interrupt-parent = <&axi_intc>; + interrupts = <8 2>; + + clocks = <&clk_bus_0>, <&axi_ad9084_adxcvr_tx_b 1>, <&hmc7044 12>, <&axi_ad9084_adxcvr_tx_b 0>; + clock-names = "s_axi_aclk", "link_clk", "device_clk", "lane_clk"; + + #clock-cells = <0>; + clock-output-names = "jesd_tx_lane_clk_b"; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_adxcvr_tx_b 0 DEFRAMER_LINK_B0_TX>; + }; + + axi_ad9084_adxcvr_rx_b: axi-adxcvr-rx-b@44aa0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "adi,axi-adxcvr-1.0"; + reg = <0x44aa0000 0x1000>; + + clocks = <&hmc7044 10>; /* div40 is controlled by axi_ad9084_rx_jesd */ + clock-names = "conv"; + + #clock-cells = <1>; + clock-output-names = "rx_gt_clk_b", "rx_out_clk_b"; + + adi,sys-clk-select = ; + adi,out-clk-select = ; + adi,use-lpm-enable; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&hmc7044 0 FRAMER_LINK_B0_RX>; + }; + + axi_ad9084_adxcvr_tx_b: axi-adxcvr-tx-b@44ba0000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "adi,axi-adxcvr-1.0"; + reg = <0x44ba0000 0x1000>; + + clocks = <&hmc7044 10>; /* div40 is controlled by axi_ad9084_tx_jesd */ + clock-names = "conv"; + + #clock-cells = <1>; + clock-output-names = "tx_gt_clk_b", "tx_out_clk_b"; + + adi,sys-clk-select = ; + adi,out-clk-select = ; /* XCVR_PROGDIV_CLK */ + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&hmc7044 0 DEFRAMER_LINK_B0_TX>; + }; + + axi_data_offload_rx_b: data_offload_rx_b@7c4a0000 { + compatible = "adi,axi-data-offload-1.0.a"; + reg = <0x7c4a0000 0x10000>; + }; + + axi_data_offload_tx_b: data_offload_tx_b@7c490000 { + compatible = "adi,axi-data-offload-1.0.a"; + reg = <0x7c490000 0x10000>; + }; +#endif /* ASYNM_A_B_MODE */ +}; + + + +&fmc_spi { + adf4382: adf4382@0 { + #clock-cells = <1>; + compatible = "adi,adf4382"; + reg = <0>; + spi-max-frequency = <1000000>; + adi,spi-3wire-enable; + clocks = <&clkin_125>; + clock-names = "ref_clk"; + clock-output-names = "adf4382_out_clk"; + //adi,power-up-frequency = /bits/ 64 <20000000000>; + label = "adf4382"; + #io-channel-cells = <1>; + }; + + hmc7044: hmc7044@1 { + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + compatible = "adi,hmc7044"; + reg = <1>; + spi-max-frequency = <1000000>; + + jesd204-device; + #jesd204-cells = <2>; + + //adi,clkin1-vco-in-enable; +#if WITH_AION + jesd204-inputs = + <&adf4030 0 FRAMER_LINK_A0_RX>, + <&adf4030 0 DEFRAMER_LINK_A0_TX>; +#endif /* WITH_AION */ + clocks = <&clkin_125>; + clock-names = "clkin0"; + + adi,pll1-clkin-frequencies = <125000000 125000000 125000000 125000000>; + adi,vcxo-frequency = <125000000>; + + adi,pll1-loop-bandwidth-hz = <200>; + + adi,pll2-output-frequency = ; + + adi,pll1-ref-prio-ctrl = <0xE1>; /* prefer CLKIN1 -> CLKIN0 -> CLKIN2 -> CLKIN3 */ + adi,pll1-ref-autorevert-enable; + + adi,sysref-timer-divider = <1024>; + adi,pulse-generator-mode = ; + + adi,clkin0-buffer-mode = <0x07>; + adi,clkin1-buffer-mode = <0x07>; + adi,oscin-buffer-mode = <0x5>; + + adi,gpi-controls = <0x00 0x00 0x00 0x00>; + adi,gpo-controls = <0x37 0x33 0x00 0x00>; + + clock-output-names = + "hmc7044_out0", "hmc7044_out1", "hmc7044_out2", + "hmc7044_out3", "hmc7044_out4", "hmc7044_out5", + "hmc7044_out6", "hmc7044_out7", "hmc7044_out8", + "hmc7044_out9", "hmc7044_out10", "hmc7044_out11", + "hmc7044_out12", "hmc7044_out13"; + + hmc7044_c1: channel@1 { + reg = <1>; + adi,extended-name = "ADF4030_REFIN"; + adi,divider = <20>; // 125 + adi,driver-mode = ; // LVDS + }; + + hmc7044_c3: channel@3 { + reg = <3>; + adi,extended-name = "ADF4030_BSYNC0"; + adi,divider = <512>; // 9.765 + adi,driver-mode = ; // change to LVPECL + adi,jesd204-sysref-chan; + }; + + hmc7044_c8: channel@8 { + reg = <8>; + adi,extended-name = "CORE_CLK_TX"; + adi,divider = <8>; + adi,driver-mode = ; // LVDS + }; + + hmc7044_c9: channel@9 { + reg = <9>; + adi,extended-name = "CORE_CLK_RX"; + adi,divider = <8>; + adi,driver-mode = ; // LVDS + }; + + hmc7044_c10: channel@10 { + reg = <10>; + adi,extended-name = "FPGA_REFCLK"; + adi,divider = <8>; + adi,driver-mode = ; // LVDS + }; + + hmc7044_c11: channel@11 { + reg = <11>; + adi,extended-name = "CORE_CLK_RX_B"; + adi,divider = <8>; + adi,driver-mode = ; // LVDS + }; + + hmc7044_c12: channel@12 { + reg = <12>; + adi,extended-name = "CORE_CLK_TX_B"; + adi,divider = <8>; + adi,driver-mode = ; // LVDS + }; + }; + +#if WITH_AION + adf4030: adf4030@4 { + #clock-cells = <1>; + compatible = "adi,adf4030"; + reg = <4>; + + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + spi-max-frequency = <1000000>; + adi,spi-3wire-enable; + + clocks = <&hmc7044 1>; + clock-names = "refin"; + clock-output-names = "adf4030_bsync_0", "adf4030_bsync_1", + "adf4030_bsync_2", "adf4030_bsync_3", "adf4030_bsync_4", + "adf4030_bsync_5", "adf4030_bsync_6", "adf4030_bsync_7", + "adf4030_bsync_8", "adf4030_bsync_9"; + label = "adf4030"; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-sysref-provider; + +#if WITH_AXI_AION_TRIG + jesd204-inputs = + <&axi_aion_trig 0 FRAMER_LINK_A0_RX>, + <&axi_aion_trig 0 DEFRAMER_LINK_A0_TX>; +#endif /* WITH_AXI_AION_TRIG */ + + adi,vco-frequency-hz = ; /* 2.5 GHz */ + adi,bsync-frequency-hz = ; + adi,bsync-autoalign-reference-channel = <0>; + adi,bsync-autoalign-iteration-count = <6>; + adi,bsync-secondary-frequency-hz = ; /* 12.5 MHz */ + + channel@0 { + /* hmc output */ + reg = <0>; + adi,extended-name = "ADF4030_SCLKOUT3"; + auto-align-on-sync-en; + adi,rcm = <1>; + adi,link-rx-en; + adi,float-rx-en; + }; + adf4030_bsync1_debug_p18: channel@1 { + /* Output debug loopback */ + reg = <1>; + adi,extended-name = "BSYNC1_DEBUG_P18"; + //auto-align-on-sync-en; + adi,input-output-reconfig-en; + adi,rcm = <62>; // LVDS + adi,link-rx-en; + adi,float-rx-en; + adi,output-en; + }; + adf4030_bsync2_debug_p19: channel@2 { + /* Input debug loopback */ + reg = <2>; + adi,extended-name = "BSYNC2_DEBUG_P19"; + //auto-align-on-sync-en; + adi,input-output-reconfig-en; + adi,rcm = <62>; + adi,link-rx-en; + adi,float-rx-en; + }; + channel@3 { + /* Input debug loopback */ + reg = <3>; + adi,extended-name = "BSYNC3_TP54_TP55"; + adi,input-output-reconfig-en; + adi,rcm = <62>; + adi,link-rx-en; + adi,float-rx-en; + }; + channel@4 { + /* Input debug loopback */ + reg = <4>; + adi,extended-name = "BSYNC4_TP56_TP57"; + adi,input-output-reconfig-en; + adi,rcm = <62>; + adi,link-rx-en; + adi,float-rx-en; + }; + + channel@5 { + /* apollo input */ + reg = <5>; + adi,extended-name = "APOLLO_SYSREF"; + auto-align-on-sync-en; + adi,output-en; + adi,input-output-reconfig-en; + adi,rcm = <1>; + adi,link-rx-en; + adi,float-rx-en; + }; + channel@6 { + /* Input debug loopback */ + reg = <6>; + adi,extended-name = "BSYNC4_TP48_TP49"; + adi,input-output-reconfig-en; + adi,rcm = <62>; + adi,link-rx-en; + adi,float-rx-en; + }; + + channel@8 { + /* fpga sysref_in_p/n input */ + reg = <8>; + adi,extended-name = "SYSREF_IN_F"; + auto-align-on-sync-en; + adi,output-en; + adi,link-rx-en; + adi,float-rx-en; + adi,input-output-reconfig-en; + }; + channel@9 { + /* Unused, connects to nothing */ + reg = <9>; + adi,extended-name = "SYSREF_OUT_FMC"; + adi,output-en; + auto-align-on-sync-en; + adi,input-output-reconfig-en; + adi,rcm = <62>; + }; + }; +#endif /* WITH_AION */ +}; + +&axi_spi_2 { + trx0_ad9084: ad9084@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "adi,ad9084"; + reg = <0>; + spi-max-frequency = <5000000>; + + /* Clocks */ + clocks = <&adf4382 0>; + clock-names = "dev_clk"; + dev_clk-clock-scales = <1 10>; + + clock-output-names = "rx_sampl_clk", "tx_sampl_clk"; + #clock-cells = <1>; + + adi,axi-hsci-connected = <&axi_hsci>; + adi,hsci-auto-linkup-mode-en; + //adi,hsci-disable-after-boot-en; + + interrupt-names = "fft_done_A", "fft_done_B"; + interrupt-parent = <&axi_gpio>; + interrupts = <34 1 35 1>; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-top-device = <0>; /* This is the TOP device */ + jesd204-ignore-errors; +#if ASYNM_A_B_MODE + jesd204-link-ids = ; + + jesd204-inputs = + <&axi_ad9084_core_rx 0 FRAMER_LINK_A0_RX>, + <&axi_ad9084_rx_jesd_b 0 FRAMER_LINK_B0_RX>, + <&axi_ad9084_core_tx 0 DEFRAMER_LINK_A0_TX>, + <&axi_ad9084_core_tx_b 0 DEFRAMER_LINK_B0_TX>; + + adi,side-b-use-seperate-tpl-en; +#else + jesd204-link-ids = ; + + jesd204-inputs = + <&axi_ad9084_core_rx 0 FRAMER_LINK_A0_RX>, + <&axi_ad9084_core_tx 0 DEFRAMER_LINK_A0_TX>; +#endif + + adi,jrx0-physical-lane-mapping = <10 8 9 11 5 1 3 7 4 6 2 0>; + adi,jtx0-logical-lane-mapping = <11 2 3 5 10 1 9 0 6 7 8 4>; + adi,jrx1-physical-lane-mapping = <4 6 2 0 1 7 10 3 5 8 9 11>; + adi,jtx1-logical-lane-mapping = <3 9 5 4 2 6 1 7 8 11 0 10>; + + adi,subclass = ; + + reset-gpios = <&axi_gpio 62 0>; + adi,device-profile-fw-name = DEVICE_PROFILE_NAME; + +#if WITH_AXI_AION_TRIG + trig-req-gpios = <&axi_gpio 48 GPIO_ACTIVE_HIGH>; + adi,trigger-sync-en; +#endif /* WITH_AXI_AION_TRIG */ + +#if WITH_AION + io-channels = <&adf4030 5>, <&adf4382 0>; + io-channel-names = "bsync", "clk"; +#endif /* WITH_AION */ + + adi,nyquist-zone = <1>; /* 1 - 1st Nyquist zone, 2 - 2nd Nyquist zone */ + }; +}; diff --git a/arch/microblaze/boot/dts/vcu118_ad9084_204C_M4_L8_NP12_16p2_6x1.dts b/arch/microblaze/boot/dts/vcu118_ad9084_204C_M4_L8_NP12_16p2_6x1.dts new file mode 100644 index 00000000000000..a076651ab32d09 --- /dev/null +++ b/arch/microblaze/boot/dts/vcu118_ad9084_204C_M4_L8_NP12_16p2_6x1.dts @@ -0,0 +1,102 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Analog Devices AD9084 RevC + * https://wiki.analog.com/resources/tools-software/linux-drivers/iio-mxfe/ad9084 + * https://wiki.analog.com/resources/eval/user-guides/ad9084_fmca_ebz/ad9084_fmca_ebz_hdl + * + * hdl_project: + * board_revision: + * + * Copyright (C) 2025 Analog Devices Inc. + */ + +#define DEVICE_PROFILE_NAME "204C_M4_L8_NP12_16p2_6x1.bin" + +//#define DEVICE_PROFILE_NAME "204C_M4_L8_NP12_10p8_4x1.bin" + +#include + +#define HMC7044_PLL2_FREQ (3375000000) // !!! (2150...3200 MHz range) +//#define HMC7044_PLL2_FREQ (2700000000) // (2150...3200 MHz range) +#define AION_VCO_FREQ_HZ (2531250000) // 2.53125 GHz (2375...2625 MHz range) + +/* + * OUT_CLK_SELECT options: + * XCVR_OUTCLK_PCS + * XCVR_OUTCLK_PMA + * XCVR_REFCLK + * XCVR_REFCLK_DIV2 + * XCVR_PROGDIV_CLK (GTHE3, GTHE4, GTYE4 only) +*/ + +#define OUT_CLK_SELECT XCVR_PROGDIV_CLK + +/* + * SYS_CLK_SELECT options: + * XCVR_CPLL (CPLL: GTHE3, GTHE4, GTYE4, GTXE2) + * XCVR_QPLL1 (QPLL1: GTHE3, GTHE4, GTYE4) + * XCVR_QPLL (QPLL0: GTHE3, GTHE4, GTYE4, GTXE2) + */ + +#define SYS_CLK_SELECT XCVR_QPLL1 + +#define SYSREF_CLK_MHz (AION_VCO_FREQ_HZ / 1000) + +#define WITH_AION 1 +#define WITH_AXI_AION_TRIG 1 +#define ASYNM_A_B_MODE 0 + +#include "vcu118_ad9084.dts" + +/ { + model = "Analog Devices AD9084-FMCA-EBZ @Xilinx/vcu118 204C_M4_L8_NP12_16p2_6x1"; +}; + +&hmc7044_c1 { + adi,divider = <40>; /* 32 for 2700 MHz, 40 for 3375 MHz */ +}; + +&hmc7044_c10 { + adi,divider = <10>; +}; + +&hmc7044_c3 { + adi,divider = <1280>; /* 1024 for 2700 MHz, 1280 for 3375 MHz */ + /delete-property/ adi,jesd204-sysref-chan; +}; + +&trx0_ad9084 { + adi,dformat-ddc-dither-en; + jesd204-stop-states = ; +}; + +&hmc7044 { + adi,pll1-clkin-frequencies = <125000000 0 0 0>; + adi,pll1-ref-prio-ctrl = <0xE1>; /* prefer CLKIN1 -> CLKIN0 -> CLKIN2 -> CLKIN3 */ + adi,clkin1-buffer-mode = <0>; + + adi,ignore-vco-limits; + adi,sync-through-pll2-force-r2-eq-1; + adi,hmc-two-level-tree-sync-en; + + hmc7044_c4: channel@4 { + reg = <4>; + adi,extended-name = "to_ext_trig"; + adi,divider = <1280>; /* 1024 for 2700 MHz, 1280 for 3375 MHz */ + adi,driver-mode = ; // LVDS + //adi,startup-mode-dynamic-enable; + }; +}; + +&adf4030 { + adi,bsync-autoalign-reference-channel = <2>; +}; + +&adf4030_bsync1_debug_p18 { + auto-align-on-sync-en; +}; + +&adf4030_bsync2_debug_p19 { + adi,rcm = <1>; + adi,ac-coupled-en; +}; \ No newline at end of file diff --git a/arch/microblaze/boot/dts/vcu118_ad9084_204C_M4_L8_NP16_20p0_4x2_CLL.dts b/arch/microblaze/boot/dts/vcu118_ad9084_204C_M4_L8_NP16_20p0_4x2_CLL.dts new file mode 100644 index 00000000000000..0c91b4d4939636 --- /dev/null +++ b/arch/microblaze/boot/dts/vcu118_ad9084_204C_M4_L8_NP16_20p0_4x2_CLL.dts @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Analog Devices AD9084 RevC + * https://wiki.analog.com/resources/tools-software/linux-drivers/iio-mxfe/ad9084 + * https://wiki.analog.com/resources/eval/user-guides/ad9084_fmca_ebz/ad9084_fmca_ebz_hdl + * + * hdl_project: + * board_revision: + * + * Copyright (C) 2025 Analog Devices Inc. + */ + +#define DEVICE_PROFILE_NAME "204C_M4_L8_NP16_20p0_4x2.bin" + +#include + +#define HMC7044_PLL2_FREQ (2500000000) // 2.5 GHz (2150...3200 MHz range) +#define AION_VCO_FREQ_HZ (2500000000) // 2.5 GHz (2375...2625 MHz range) + +/* + * OUT_CLK_SELECT options: + * XCVR_OUTCLK_PCS + * XCVR_OUTCLK_PMA + * XCVR_REFCLK + * XCVR_REFCLK_DIV2 + * XCVR_PROGDIV_CLK (GTHE3, GTHE4, GTYE4 only) +*/ +#define OUT_CLK_SELECT XCVR_PROGDIV_CLK + +/* + * SYS_CLK_SELECT options: + * XCVR_CPLL (CPLL: GTHE3, GTHE4, GTYE4, GTXE2) + * XCVR_QPLL1 (QPLL1: GTHE3, GTHE4, GTYE4) + * XCVR_QPLL (QPLL0: GTHE3, GTHE4, GTYE4, GTXE2) + */ +#define SYS_CLK_SELECT XCVR_QPLL + +#define SYSREF_CLK_MHz (9765625) + +#define WITH_AION 1 +#define WITH_AXI_AION_TRIG 0 +#define ASYNM_A_B_MODE 0 + +#include "vcu118_ad9084.dts" diff --git a/arch/microblaze/boot/dts/vcu118_ad9084_204C_M4_L8_NP16_20p0_4x4.dts b/arch/microblaze/boot/dts/vcu118_ad9084_204C_M4_L8_NP16_20p0_4x4.dts new file mode 100644 index 00000000000000..274695bf5124e5 --- /dev/null +++ b/arch/microblaze/boot/dts/vcu118_ad9084_204C_M4_L8_NP16_20p0_4x4.dts @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Analog Devices AD9084 RevC + * https://wiki.analog.com/resources/tools-software/linux-drivers/iio-mxfe/ad9084 + * https://wiki.analog.com/resources/eval/user-guides/ad9084_fmca_ebz/ad9084_fmca_ebz_hdl + * + * hdl_project: + * board_revision: + * + * Copyright (C) 2025 Analog Devices Inc. + */ + +#define DEVICE_PROFILE_NAME "204C_M4_L8_NP16_20p0_4x4.bin" + + +#define HMC7044_PLL2_FREQ (2500000000) // 2.5 GHz (2150...3200 MHz range) +#define AION_VCO_FREQ_HZ (2500000000) // 2.5 GHz (2375...2625 MHz range) + +/* + * OUT_CLK_SELECT options: + * XCVR_OUTCLK_PCS + * XCVR_OUTCLK_PMA + * XCVR_REFCLK + * XCVR_REFCLK_DIV2 + * XCVR_PROGDIV_CLK (GTHE3, GTHE4, GTYE4 only) +*/ +#define OUT_CLK_SELECT XCVR_PROGDIV_CLK + +/* + * SYS_CLK_SELECT options: + * XCVR_CPLL (CPLL: GTHE3, GTHE4, GTYE4, GTXE2) + * XCVR_QPLL1 (QPLL1: GTHE3, GTHE4, GTYE4) + * XCVR_QPLL (QPLL0: GTHE3, GTHE4, GTYE4, GTXE2) + */ +#define SYS_CLK_SELECT XCVR_QPLL + +#define SYSREF_CLK_MHz (10000000) + +#define WITH_AION 1 +#define WITH_AXI_AION_TRIG 0 +#define ASYNM_A_B_MODE 1 + +#include "vcu118_ad9084.dts" + diff --git a/arch/microblaze/boot/dts/vcu118_quad_ad9084_26p4_revB.dts b/arch/microblaze/boot/dts/vcu118_quad_ad9084_26p4_revB.dts new file mode 100644 index 00000000000000..3573d75e9377ae --- /dev/null +++ b/arch/microblaze/boot/dts/vcu118_quad_ad9084_26p4_revB.dts @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Analog Devices Quad-AD9084 RevB + * https://wiki.analog.com/resources/tools-software/linux-drivers/iio-mxfe/ad9084 + * https://wiki.analog.com/resources/eval/user-guides/ad9084_fmca_ebz/ad9084_fmca_ebz_hdl + * + * hdl_project: + * board_revision: + * + * Copyright (C) 2024 Analog Devices Inc. + */ + +#define DEVICE_PROFILE_NAME "id01_uc43.bin" + +#define MHz 1000000 + +#define FREQ_J1_MHz (400 * MHz) +#define TX_CORE_CLK_MHz (400 * MHz) +#define RX_CORE_CLK_MHz (400 * MHz) +#define FPGA_REFCLK_CLK_MHz (400 * MHz) + +#define SYSREF_CLK_MHz (2 * 6250000) + +#include "vcu118_quad_ad9084_revB.dts" diff --git a/arch/microblaze/boot/dts/vcu118_quad_ad9084_26p4_revB_ext.dts b/arch/microblaze/boot/dts/vcu118_quad_ad9084_26p4_revB_ext.dts new file mode 100644 index 00000000000000..1ad3273a384f44 --- /dev/null +++ b/arch/microblaze/boot/dts/vcu118_quad_ad9084_26p4_revB_ext.dts @@ -0,0 +1,138 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Analog Devices Quad-AD9084 RevB + * https://wiki.analog.com/resources/tools-software/linux-drivers/iio-mxfe/ad9084 + * https://wiki.analog.com/resources/eval/user-guides/ad9084_fmca_ebz/ad9084_fmca_ebz_hdl + * + * hdl_project: + * board_revision: + * + * Copyright (C) 2024 Analog Devices Inc. + */ + +#define DEVICE_PROFILE_NAME "id01_uc43.bin" + +#define MHz 1000000 + +#define FREQ_J1_MHz (400 * MHz) +#define TX_CORE_CLK_MHz (400 * MHz) +#define RX_CORE_CLK_MHz (400 * MHz) +#define FPGA_REFCLK_CLK_MHz (400 * MHz) + +#define SYSREF_CLK_MHz (2 * 6250000) + +#include "vcu118_quad_ad9084_revB.dts" + +&axi_spi_2 { + + /delete-node/ adf4030; + + adf4030: adf4030@4 { + #clock-cells = <1>; + compatible = "adi,adf4030"; + reg = <4>; + + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + + spi-max-frequency = <1000000>; + clocks = <<c6952 5>; + clock-names = "refin"; + clock-output-names = "adf4030_bsync_0", "adf4030_bsync_1", + "adf4030_bsync_2", "adf4030_bsync_3", "adf4030_bsync_4", + "adf4030_bsync_5", "adf4030_bsync_6", "adf4030_bsync_7", + "adf4030_bsync_8", "adf4030_bsync_9"; + label = "adf4030"; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-sysref-provider; + + adi,vco-frequency-hz = <2500000000>; /* 2.5 GHz */ + adi,bsync-frequency-hz = ; + adi,bsync-autoalign-reference-channel = <9>; /* J46_J47_UFL */ + adi,bsync-autoalign-iteration-count = <6>; + adi,bsync-secondary-frequency-hz = <12500000>; /* 12.5 MHz */ + + channel@0 { + reg = <0>; + adi,extended-name = "APOLLO_SYSREF_0"; + adi,output-en; + adi,input-output-reconfig-en; + auto-align-on-sync-en; + adi,rcm = <1>; + adi,link-rx-en; + adi,float-rx-en; + }; + channel@1 { + reg = <1>; + adi,extended-name = "APOLLO_SYSREF_1"; + adi,output-en; + adi,input-output-reconfig-en; + auto-align-on-sync-en; + adi,rcm = <1>; + adi,link-rx-en; + adi,float-rx-en; + }; + channel@2 { + reg = <2>; + adi,extended-name = "APOLLO_SYSREF_2"; + adi,output-en; + adi,input-output-reconfig-en; + auto-align-on-sync-en; + adi,rcm = <1>; + adi,link-rx-en; + adi,float-rx-en; + }; + channel@3 { + reg = <3>; + adi,extended-name = "APOLLO_SYSREF_3"; + adi,output-en; + adi,input-output-reconfig-en; + auto-align-on-sync-en; + adi,rcm = <1>; + adi,link-rx-en; + adi,float-rx-en; + }; + channel@4 { + reg = <4>; + adi,extended-name = "FPGA_SYSREF_0"; /* RES rotate option for J40/J41 U.FL output */ + adi,output-en; + adi,input-output-reconfig-en; + auto-align-on-sync-en; + adi,rcm = <62>; + adi,link-rx-en; + adi,float-rx-en; + }; + // channel@5 { + // reg = <5>; + // adi,extended-name = "FPGA_SYSREF_1"; /* RES rotate option for J42/J43 U.FL output */ + // adi,output-en; + // adi,input-output-reconfig-en; + // adi,rcm = <62>; + // }; + channel@6 { + reg = <6>; + adi,extended-name = "LTC6953_OUT_6"; + adi,link-rx-en; + adi,float-rx-en; + }; + /* BSYNC7 unused */ + channel@8 { + reg = <8>; + adi,extended-name = "LTC6952_OUT_8"; + adi,link-rx-en; + adi,float-rx-en; + }; + channel@9 { + reg = <9>; + adi,extended-name = "J46_J47_UFL"; + //adi,output-en; + adi,input-output-reconfig-en; + auto-align-on-sync-en; + adi,rcm = <62>; + }; + }; +}; \ No newline at end of file diff --git a/arch/microblaze/boot/dts/vcu118_quad_ad9084_revB.dts b/arch/microblaze/boot/dts/vcu118_quad_ad9084_revB.dts new file mode 100644 index 00000000000000..cbf478352d2134 --- /dev/null +++ b/arch/microblaze/boot/dts/vcu118_quad_ad9084_revB.dts @@ -0,0 +1,1340 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Analog Devices Quad-AD9084 RevB + * https://wiki.analog.com/resources/tools-software/linux-drivers/iio-mxfe/ad9084 + * https://wiki.analog.com/resources/eval/user-guides/ad9084_fmca_ebz/ad9084_fmca_ebz_hdl + * + * hdl_project: + * board_revision: + * + * Copyright (C) 2024-2025 Analog Devices Inc. + */ + +/dts-v1/; + +#include "vcu118.dtsi" +#include +#include +#include + +#define fmc_i2c fmcp_hspc_iic +#define fmc_spi axi_spi + +#ifndef DEVICE_PROFILE_NAME +#define DEVICE_PROFILE_NAME "id01_uc42.bin" +#endif + +//#define HSCI_FIXED_TIMING_PAR 1 +#define HSCI_SPEED 800 + +#define min(X, Y) ((X) < (Y) ? (X) : (Y)) + +#define MHz 1000000 + +#ifndef FREQ_J1_MHz +#define FREQ_J1_MHz (400 * MHz) +#endif + +#ifndef TX_CORE_CLK_MHz +#define TX_CORE_CLK_MHz (200 * MHz) +#endif + +#ifndef RX_CORE_CLK_MHz +#define RX_CORE_CLK_MHz (200 * MHz) +#endif + +#ifndef FPGA_REFCLK_CLK_MHz +#define FPGA_REFCLK_CLK_MHz (200 * MHz) +#endif + +#ifndef SYSREF_CLK_MHz +#define SYSREF_CLK_MHz (6250000) +#endif + +#ifndef ADF4382_FREQ_Hz +#define ADF4382_FREQ_Hz (12800000000) /* 12.8 GHz */ +#endif + +#define ONCHIP_PLL_LOW_FREQ (400 * MHz) +#define EXT_VCO_FREQ (2000 * MHz) + +#define ADF4382_DIVIDER 1 +#define ADF4382_DIG_DELAY 14 +#define ADF4382_ANA_DELAY 0 + +#define APOLLO_SYSREF_DIVIDER (FREQ_J1_MHz / SYSREF_CLK_MHz) +#define APOLLO_SYSREF_DIG_DELAY 14 +#define APOLLO_SYSREF_ANA_DELAY 0 +#define APOLLO_SYSREF_MODE 0 + +#define LTC6853_FOLLOWER_IN_DIG_DELAY 0 +#define LTC6853_FOLLOWER_IN_ANA_DELAY 0 + +#define LTC6853_FOLLOWER_EZS_SRQ_DIVIDER APOLLO_SYSREF_DIVIDER +#define LTC6853_FOLLOWER_EZS_SRQ_DIG_DELAY 14 +#define LTC6853_FOLLOWER_EZS_SRQ_ANA_DELAY 0 + +#define FPGA_REFCLK_DIVIDER (EXT_VCO_FREQ / FPGA_REFCLK_CLK_MHz) +#define FPGA_REFCLK_DIG_DELAY 0 +#define FPGA_REFCLK_ANA_DELAY 0 + +#define FPGA_CORE_CLK_TX_DIVIDER (EXT_VCO_FREQ / TX_CORE_CLK_MHz) +#define FPGA_CORE_CLK_TX_DIG_DELAY 0 +#define FPGA_CORE_CLK_TX_ANA_DELAY 0 + +#define FPGA_CORE_CLK_RX_DIVIDER (EXT_VCO_FREQ / RX_CORE_CLK_MHz) +#define FPGA_CORE_CLK_RX_DIG_DELAY 0 +#define FPGA_CORE_CLK_RX_ANA_DELAY 0 + +#define APOLLO_LOWFREQ_DIVIDER (FREQ_J1_MHz / ONCHIP_PLL_LOW_FREQ) +#define APOLLO_LOWFREQ_DIG_DELAY 0 +#define APOLLO_LOWFREQ_ANA_DELAY 0 + +#undef APOLLO_LOWFREQ_PATH_ENABLED + +#define LTC6953_AION_BSYNC_6_DIVIDER (FREQ_J1_MHz / SYSREF_CLK_MHz) +#define LTC6953_AION_BSYNC_6_DIG_DELAY 14 +#define LTC6953_AION_BSYNC_6_ANA_DELAY 0 + +#define J50_J51_DIVIDER (FREQ_J1_MHz / SYSREF_CLK_MHz) +#define J50_J51_DIG_DELAY 14 +#define J50_J51_ANA_DELAY 0 + +#define LTC6952_REF_IN_DIVIDER 4 +#define LTC6952_REF_IN_DIG_DELAY 0 +#define LTC6952_REF_IN_ANA_DELAY 0 + +#define LTC6852_EZS_SRQ_IN_DIVIDER (FREQ_J1_MHz / SYSREF_CLK_MHz) +#define LTC6852_EZS_SRQ_IN_DIG_DELAY 14 +#define LTC6852_EZS_SRQ_IN_ANA_DELAY 0 + +#define ADF4351_REF_IN_DIVIDER 20 + +/* LTC6952 */ +#define J48_J49_DIVIDER (EXT_VCO_FREQ / SYSREF_CLK_MHz) +#define J48_J49_DIG_DELAY 0 +#define J48_J49_ANA_DELAY 0 + +#define ADF4030_REF_IN_DIVIDER 200 +#define ADF4030_REF_IN_DIG_DELAY 0 +#define ADF4030_REF_IN_ANA_DELAY 0 + +#define ADF4030_BSYNC_8_DIVIDER (EXT_VCO_FREQ / SYSREF_CLK_MHz) +#define ADF4030_BSYNC_8_DIG_DELAY 0 +#define ADF4030_BSYNC_8_ANA_DELAY 0 + + +/ { + model = "Analog Devices Quad-AD9084 Rev.B FMC @Xilinx/vcu118"; + + clocks { + clkin_j1: clock@0 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = ; + clock-output-names = "clkin_j1"; + }; + }; + + vref: regulator-vref { + compatible = "regulator-fixed"; + regulator-name = "vref-ad5592"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + calibration-board-control@0 { + compatible = "adi,one-bit-adc-dac"; + out-gpios = <&axi_gpio_2 33 0>, <&axi_gpio_2 32 0>, <&axi_gpio_2 34 0>, <&axi_gpio_2 35 0>; + + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0>; + label = "5045_V1"; + }; + + channel@1 { + reg = <1>; + label = "5045_V2"; + }; + + channel@2 { + reg = <2>; + label = "CTRL_IND"; + }; + + channel@3 { + reg = <3>; + label = "CTRL_RX_COMBINED"; + }; + }; + + axi-jesd204-rx@0 { + compatible = "adi,iio-fake-platform-device"; + adi,faked-dev = <&axi_ad9084_rx_jesd>; + adi,attribute-names = + "status", "encoder", "lane0_info", "lane1_info", + "lane2_info", "lane3_info", "lane4_info", + "lane5_info", "lane6_info", "lane7_info", + "lane8_info", "lane9_info", "lane10_info", + "lane11_info", "lane12_info", "lane13_info", + "lane14_info", "lane15_info"; + label = "axi-jesd204-rx"; + }; + + axi-jesd204-rx@1 { + compatible = "adi,iio-fake-platform-device"; + adi,faked-dev = <&axi_ad9084_tx_jesd>; + adi,attribute-names = "status", "encoder"; + label = "axi-jesd204-tx"; + }; + + axi-adxcvr-rx@2 { + compatible = "adi,iio-fake-platform-device"; + adi,faked-dev = <&axi_ad9084_adxcvr_rx>; + adi,attribute-names = + "eyescan_info", "prbs_status", "prbs_counter_reset", + "prescale", "enable", "prbs_error_counters", "reg_access", + "eye_data_available", "eye_data_partial", "prbs_select"; + label = "axi-adxcvr-rx"; + }; + + axi-adxcvr-tx@4 { + compatible = "adi,iio-fake-platform-device"; + adi,faked-dev = <&axi_ad9084_adxcvr_tx>; + adi,attribute-names = "prbs_select", "prbs_error_inject", "reg_access"; + label = "axi-adxcvr-tx"; + }; + + gpio-board-control@0 { + compatible = "adi,one-bit-adc-dac"; + out-gpios = <&axi_gpio_2 30 1>; + in-gpios = <&axi_gpio_2 36 0>, <&axi_gpio_2 37 0>, <&axi_gpio_2 38 0>, <&axi_gpio_2 39 0>, + <&axi_gpio_2 40 0>, <&axi_gpio_2 41 0>, <&axi_gpio_2 42 0>, <&axi_gpio_2 43 0>, + <&axi_gpio_2 44 0>; + label = "gpio-ctrl"; + + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0>; + label = "12v_PG"; + }; + channel@1 { + reg = <1>; + label = "Vdd_0.8v_PG"; + }; + channel@2 { + reg = <2>; + label = "Vdda_1.0v_PG"; + }; + channel@3 { + reg = <3>; + label = "Vddd_1.8v_PG"; + }; + channel@4 { + reg = <4>; + label = "Vdda_1.8v_PG"; + }; + channel@5 { + reg = <5>; + label = "Vneg_1.0v_PG"; + }; + channel@6 { + reg = <6>; + label = "Artemis_5.0v_PG"; + }; + channel@7 { + reg = <7>; + label = "Artemis_Status"; + }; + channel@8 { + reg = <8>; + label = "Clk_Status"; + }; + channel@9 { + reg = <9>; + label = "admv8913_cs_n"; + }; + }; + + adrf5730_0 { + compatible = "adi,hmc425a"; + ctrl-gpios = <&trx0_ad9084 0 GPIO_ACTIVE_LOW>, + <&trx0_ad9084 1 GPIO_ACTIVE_LOW>, + <&trx0_ad9084 2 GPIO_ACTIVE_LOW>, + <&trx0_ad9084 3 GPIO_ACTIVE_LOW>, + <&trx0_ad9084 4 GPIO_ACTIVE_LOW>, + <&trx0_ad9084 5 GPIO_ACTIVE_LOW>; + label = "dsa0"; + }; + + adrf5730_1 { + compatible = "adi,hmc425a"; + ctrl-gpios = <&trx1_ad9084 0 GPIO_ACTIVE_LOW>, + <&trx1_ad9084 1 GPIO_ACTIVE_LOW>, + <&trx1_ad9084 2 GPIO_ACTIVE_LOW>, + <&trx1_ad9084 3 GPIO_ACTIVE_LOW>, + <&trx1_ad9084 4 GPIO_ACTIVE_LOW>, + <&trx1_ad9084 5 GPIO_ACTIVE_LOW>; + label = "dsa1"; + }; + + adrf5730_2 { + compatible = "adi,hmc425a"; + ctrl-gpios = <&trx2_ad9084 0 GPIO_ACTIVE_LOW>, + <&trx2_ad9084 1 GPIO_ACTIVE_LOW>, + <&trx2_ad9084 2 GPIO_ACTIVE_LOW>, + <&trx2_ad9084 3 GPIO_ACTIVE_LOW>, + <&trx2_ad9084 4 GPIO_ACTIVE_LOW>, + <&trx2_ad9084 5 GPIO_ACTIVE_LOW>; + label = "dsa2"; + }; + + adrf5730_3 { + compatible = "adi,hmc425a"; + ctrl-gpios = <&trx3_ad9084 0 GPIO_ACTIVE_LOW>, + <&trx3_ad9084 1 GPIO_ACTIVE_LOW>, + <&trx3_ad9084 2 GPIO_ACTIVE_LOW>, + <&trx3_ad9084 3 GPIO_ACTIVE_LOW>, + <&trx3_ad9084 4 GPIO_ACTIVE_LOW>, + <&trx3_ad9084 5 GPIO_ACTIVE_LOW>; + label = "dsa3"; + }; + + mux_lpf0: mux-controller0 { + compatible = "gpio-mux"; + #mux-control-cells = <0>; + + mux-gpios = <&axi_gpio_2 26 0>, <&axi_gpio_2 27 0>, <&axi_gpio_2 28 0>, <&axi_gpio_2 29 0>; + }; + + mux_hpf0: mux-controller1 { + compatible = "gpio-mux"; + #mux-control-cells = <0>; + + mux-gpios = <&axi_gpio_2 22 0>, <&axi_gpio_2 23 0>, <&axi_gpio_2 24 0>, <&axi_gpio_2 25 0>; + }; + + lpf_mux: mux-lpf { + compatible = "adi,gen_mux"; + mux-controls = <&mux_lpf0>; + mux-state-names = + "0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12", "13", "14", "15"; + label = "lpf-ctrl"; + mux-default-state = "11"; + }; + + hpf_mux: mux-hpf { + compatible = "adi,gen_mux"; + mux-controls = <&mux_hpf0>; + mux-state-names = + "0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12", "13", "14", "15"; + label = "hpf-ctrl"; + mux-default-state = "13"; + }; + +}; + + +&axi_intc { + xlnx,kind-of-intr = <0xffff04f0>; + xlnx,num-intr-inputs = <17>; +}; + +&axi_ethernet { + local-mac-address = [00 0a 35 00 90 84]; +}; + +&axi_iic_main { + compatible = "xlnx,axi-iic-2.1", "xlnx,xps-iic-2.00.a"; /* Needed otherwise the HWMON devices would fail */ +}; + +&fmc_i2c { + eeprom@50 { + compatible = "at24,24c02"; + reg = <0x50>; + }; + /* West */ + ltc2977_w@5f { + compatible = "lltc,ltc2977"; + reg = <0x5F>; + }; + /* East */ + ltc2977_e@60 { + compatible = "lltc,ltc2977"; + reg = <0x60>; + }; +}; + +&amba_pl { + rx_dma: dma@7c420000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x7c420000 0x10000>; + #dma-cells = <1>; + #clock-cells = <0>; + interrupt-parent = <&axi_intc>; + interrupts = <12 2>; + + clocks = <&clk_bus_0>; + }; + + tx_dma: dma@7c430000 { + compatible = "adi,axi-dmac-1.00.a"; + reg = <0x7c430000 0x10000>; + #dma-cells = <1>; + #clock-cells = <0>; + interrupt-parent = <&axi_intc>; + interrupts = <13 2>; + clocks = <&clk_bus_0>; + + }; + + axi_ad9084_core_rx: axi-ad9084-rx-hpc@44a10000 { + compatible = "adi,axi-ad9081-rx-1.0"; + reg = <0x44a10000 0x8000>; + dmas = <&rx_dma 0>; + dma-names = "rx"; + spibus-connected = <&trx0_ad9084>; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_rx_jesd 0 FRAMER_LINK_B0_RX>; + }; + + axi_ad9084_core_tx: axi-ad9084-tx-hpc@44b10000 { + compatible = "adi,axi-ad9081-tx-1.0"; + reg = <0x44b10000 0x4000>; + dmas = <&tx_dma 0>; + dma-names = "tx"; + clocks = <&trx0_ad9084 1>; + clock-names = "sampl_clk"; + spibus-connected = <&trx0_ad9084>; + adi,axi-pl-fifo-enable; + adi,axi-data-offload-connected = <&axi_data_offload_tx>; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_tx_jesd 0 DEFRAMER_LINK_B0_TX>; + }; + + axi_ad9084_rx_jesd: axi-jesd204-rx@44a90000 { + compatible = "adi,axi-jesd204-rx-1.0"; + reg = <0x44a90000 0x4000>; + interrupt-parent = <&axi_intc>; + interrupts = <14 2>; + + clocks = <&clk_bus_0>, <&axi_ad9084_adxcvr_rx 1>, <<c6952 4>, <&axi_ad9084_adxcvr_rx 0>; + clock-names = "s_axi_aclk", "link_clk", "device_clk", "lane_clk"; + + #clock-cells = <0>; + clock-output-names = "jesd_rx_lane_clk"; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_adxcvr_rx 0 FRAMER_LINK_B0_RX>; + + adi,lanes-disable-mask = <0x0F00>; + }; + + axi_ad9084_tx_jesd: axi-jesd204-tx@44b90000 { + compatible = "adi,axi-jesd204-tx-1.0"; + reg = <0x44b90000 0x4000>; + + interrupt-parent = <&axi_intc>; + interrupts = <15 2>; + + clocks = <&clk_bus_0>, <&axi_ad9084_adxcvr_tx 1>, <<c6952 3>, <&axi_ad9084_adxcvr_tx 0>; + clock-names = "s_axi_aclk", "link_clk", "device_clk", "lane_clk"; + + #clock-cells = <0>; + clock-output-names = "jesd_tx_lane_clk"; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <&axi_ad9084_adxcvr_tx 0 DEFRAMER_LINK_B0_TX>; + }; + + axi_ad9084_adxcvr_rx: axi-adxcvr-rx@44a60000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "adi,axi-adxcvr-1.0"; + reg = <0x44a60000 0x1000>; + + clocks = <<c6952 2>; /* div40 is controlled by axi_ad9084_rx_jesd */ + clock-names = "conv"; + + #clock-cells = <1>; + clock-output-names = "rx_gt_clk", "rx_out_clk"; + + adi,sys-clk-select = ; + adi,out-clk-select = ; + adi,use-lpm-enable; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <<c6953 0 FRAMER_LINK_B0_RX>; + }; + + axi_ad9084_adxcvr_tx: axi-adxcvr-tx@44b60000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "adi,axi-adxcvr-1.0"; + reg = <0x44b60000 0x1000>; + + clocks = <<c6952 2>; /* div40 is controlled by axi_ad9084_tx_jesd */ + clock-names = "conv"; + + #clock-cells = <1>; + clock-output-names = "tx_gt_clk", "tx_out_clk"; + + adi,sys-clk-select = ; + adi,out-clk-select = ; /* XCVR_PROGDIV_CLK */ + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = <<c6953 0 DEFRAMER_LINK_B0_TX>; + }; + + axi_sysid_0: axi-sysid-0@45000000 { + compatible = "adi,axi-sysid-1.00.a"; + reg = <0x45000000 0x10000>; + }; + + axi_data_offload_rx: data_offload_rx@7c450000 { + compatible = "adi,axi-data-offload-1.0.a"; + reg = <0x7c450000 0x10000>; + }; + + axi_data_offload_tx: data_offload_tx@7c440000 { + compatible = "adi,axi-data-offload-1.0.a"; + reg = <0x7c440000 0x10000>; + }; + + axi_spi_2: spi@44A80000 { + #address-cells = <1>; + #size-cells = <0>; + bits-per-word = <8>; + compatible = "xlnx,axi-quad-spi-3.2", "xlnx,xps-spi-2.00.a"; + fifo-size = <16>; + interrupt-names = "ip2intc_irpt"; + interrupt-parent = <&axi_intc>; + interrupts = <7 0>; + num-cs = <0x8>; + reg = <0x44A80000 0x1000>; + xlnx,num-ss-bits = <0x8>; + xlnx,spi-mode = <0>; + }; + + axi_spi3: spi@44B80000 { + #address-cells = <1>; + #size-cells = <0>; + bits-per-word = <8>; + compatible = "xlnx,xps-spi-2.00.a"; + fifo-size = <16>; + interrupt-parent = <&axi_intc>; + interrupts = <16 0>; + num-cs = <0x8>; + reg = <0x44B80000 0x10000>; + xlnx,num-ss-bits = <0x8>; + xlnx,spi-mode = <0>; + }; + + axi_gpio_2: gpio@7c470000 { + #gpio-cells = <2>; + #interrupt-cells = <2>; + clock-frequency = <100000000>; + clock-names = "s_axi_aclk"; + clocks = <&clk_bus_0>; + compatible = "xlnx,axi-gpio-2.0", "xlnx,xps-gpio-1.00.a"; + gpio-controller; + interrupt-controller; + interrupt-names = "ip2intc_irpt"; + interrupt-parent = <&axi_intc>; + interrupts = <8 2>; + reg = <0x7c470000 0x1000>; + xlnx,all-inputs = <0x0>; + xlnx,all-inputs-2 = <0x0>; + xlnx,all-outputs = <0x0>; + xlnx,all-outputs-2 = <0x0>; + xlnx,dout-default = <0x00000000>; + xlnx,dout-default-2 = <0x00000000>; + xlnx,gpio-width = <0x20>; + xlnx,gpio2-width = <0x20>; + xlnx,interrupt-present = <0x1>; + xlnx,is-dual = <0x1>; + xlnx,tri-default = <0xFFFFFFFF>; + xlnx,tri-default-2 = <0xFFFFFFFF>; + + artemis-en-hog { /* FIXME: add regulator suport for ADF4382 */ + gpio-hog; + gpios = <31 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "ARTMIS_5V_EN"; + }; + }; + + hsci_clkgen: axi-clkgen@44ad0000 { + compatible = "adi,axi-clkgen-2.00.a"; + reg = <0x44ad0000 0x10000>; + #clock-cells = <0>; + clocks = <&clk_bus_0>, <&clk_bus_0>; + clock-names = "s_axi_aclk", "clkin1"; + clock-output-names = "hsci_clkgen"; + }; + + axi_hsci_0: axi_hsci_0@7c500000 { + compatible = "adi,axi-hsci-1.0.a"; + reg = <0x7c500000 0x40000>; + clocks = <&hsci_clkgen>; + clock-names = "pclk"; + + adi,hsci-interface-speed-mhz = ; + }; + + axi_hsci_1: axi_hsci_1@7c600000 { + compatible = "adi,axi-hsci-1.0.a"; + reg = <0x7c600000 0x40000>; + clocks = <&hsci_clkgen>; + clock-names = "pclk"; + + adi,hsci-interface-speed-mhz = ; + }; + + axi_hsci_2: axi_hsci_2@7c700000 { + compatible = "adi,axi-hsci-1.0.a"; + reg = <0x7c700000 0x40000>; + clocks = <&hsci_clkgen>; + clock-names = "pclk"; + + adi,hsci-interface-speed-mhz = ; + }; + + axi_hsci_3: axi_hsci_3@7c800000 { + compatible = "adi,axi-hsci-1.0.a"; + reg = <0x7c800000 0x40000>; + clocks = <&hsci_clkgen>; + clock-names = "pclk"; + + adi,hsci-interface-speed-mhz = ; + }; + + axi_aion_trig: axi_aion_trig@7c900000 { + compatible = "adi,axi-aion-trig-1.0.a"; + reg = <0x7c900000 0x1000>; + clocks = <<c6952 4>; + clock-names = "device_clk"; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = + <&adf4030 0 FRAMER_LINK_B0_RX>, + <&adf4030 0 DEFRAMER_LINK_B0_TX>; + + io-channels = <&adf4030 4>; + io-channel-names = "bsync"; + }; +}; + +#include + +&axi_spi3 { + adc_ad5592r: ad5592r@0 { + #size-cells = <0>; + #address-cells = <1>; + compatible = "adi,ad5592r"; + reg = <0>; + + spi-max-frequency = <390000>; /* 390 kHz */ + spi-cpol; + + vref-supply = <&vref>; /* optional */ + + channel@0 { + reg = <0>; + adi,mode = ; + }; + channel@1 { + reg = <1>; + adi,mode = ; + }; + channel@5 { + reg = <5>; + adi,mode = ; + }; + channel@7 { + reg = <7>; + adi,mode = ; + }; + }; +}; + +&axi_spi_2 { + + ltc6953: ltc6953@7 { + compatible = "adi,ltc6953"; + reg = <7>; + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <10000000>; + label = "ltc6953"; + + clocks = <&clkin_j1>; + clock-names = "clkin"; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = + <<c6952 0 FRAMER_LINK_B0_RX>, + <<c6952 0 DEFRAMER_LINK_B0_TX>; + + clock-output-names = "ltc6953_out0", "ltc6953_out1", + "ltc6953_out2", "ltc6953_out3", "ltc6953_out4", + "ltc6953_out5", "ltc6953_out6", "ltc6953_out7", + "ltc6953_out8", "ltc6953_out9", "ltc6953_out10"; + + #clock-cells = <1>; + + adi,pulse-generator-mode = <2>; /* Four Pulses */ + adi,controller-srqmd-en-during-sync-en; + + channel@0 { + reg = <0>; + adi,extended-name = "ADF4382_0_REFCLK"; + adi,divider = ; + adi,digital-delay = ; + adi,analog-delay = ; + //adi,sync-disable; + }; + channel@1 { + reg = <1>; + adi,extended-name = "ADF4382_3_REFCLK"; + adi,divider = ; + adi,digital-delay = ; + adi,analog-delay = ; + //adi,sync-disable; + }; + channel@2 { + reg = <2>; + adi,extended-name = "ADF4382_2_REFCLK"; + adi,divider = ; + adi,digital-delay = ; + adi,analog-delay = ; + //adi,sync-disable; + }; + channel@3 { + reg = <3>; + adi,extended-name = "ADF4382_1_REFCLK"; + adi,divider = ; + adi,digital-delay = ; + adi,analog-delay = ; + //adi,sync-disable; + }; +#ifdef APOLLO_LOWFREQ_PATH_ENABLED + channel@4 { + reg = <4>; + adi,extended-name = "APOLLO_1_LOWFREQ"; + adi,divider = ; + adi,digital-delay = ; + adi,analog-delay = ; + }; + channel@5 { + reg = <5>; + adi,extended-name = "APOLLO_0_LOWFREQ"; + adi,divider = ; + adi,digital-delay = ; + adi,analog-delay = ; + }; + channel@6 { + reg = <6>; + adi,extended-name = "APOLLO_2_LOWFREQ"; + adi,divider = ; + adi,digital-delay = ; + adi,analog-delay = ; + }; + channel@7 { + reg = <7>; + adi,extended-name = "APOLLO_3_LOWFREQ"; + adi,divider = ; + adi,digital-delay = ; + adi,analog-delay = ; + }; +#else /* APOLLO_LOWFREQ_PATH_ENABLED */ + channel@6 { + reg = <6>; + adi,extended-name = "AION_BSYNC_6"; + adi,divider = ; + adi,digital-delay = ; + adi,analog-delay = ; + }; + channel@7 { + reg = <7>; + adi,extended-name = "J50_J51_UFL_Output"; + adi,divider = ; + adi,digital-delay = ; + adi,analog-delay = ; + }; +#endif + channel@8 { + reg = <8>; + adi,extended-name = "LTC6952_REF_IN"; + adi,divider = ; + adi,digital-delay = ; + adi,analog-delay = ; + //adi,sync-disable; + }; + channel@9 { + reg = <9>; + adi,extended-name = "LTC6852_EZS_SRQ_IN"; + adi,divider = ; + adi,digital-delay = ; + adi,analog-delay = ; + adi,sysref-mode = <2>; /* Request Pass-Through */ + }; + channel@10 { + reg = <10>; + adi,extended-name = "ADF4351_REF_IN"; + adi,divider = ; + adi,digital-delay = <14>; + adi,analog-delay = <0>; + //adi,sync-disable; + }; + }; + + adf4382_0: adf4382@0 { + #clock-cells = <1>; + compatible = "adi,adf4382"; + reg = <0>; + spi-max-frequency = <1000000>; + adi,output-power-value = <4>; + adi,power-up-frequency = /bits/ 64 ; + adi,cmos-3v3; + clocks = <<c6953 0>; + clock-names = "ref_clk"; + clock-output-names = "adf4382_0_out_clk"; + label = "adf4382_0"; + #io-channel-cells = <1>; + }; + + adf4382_1: adf4382@1 { + #clock-cells = <1>; + compatible = "adi,adf4382"; + reg = <1>; + spi-max-frequency = <1000000>; + adi,output-power-value = <5>; + adi,power-up-frequency = /bits/ 64 ; + adi,cmos-3v3; + clocks = <<c6953 3>; + clock-names = "ref_clk"; + clock-output-names = "adf4382_1_out_clk"; + label = "adf4382_1"; + #io-channel-cells = <1>; + }; + + adf4382_2: adf4382@2 { + #clock-cells = <1>; + compatible = "adi,adf4382"; + reg = <2>; + spi-max-frequency = <1000000>; + adi,output-power-value = <5>; + adi,power-up-frequency = /bits/ 64 ; + adi,cmos-3v3; + clocks = <<c6953 2>; + clock-names = "ref_clk"; + clock-output-names = "adf4382_2_out_clk"; + label = "adf4382_2"; + #io-channel-cells = <1>; + }; + + adf4382_3: adf4382@3 { + #clock-cells = <1>; + compatible = "adi,adf4382"; + reg = <3>; + spi-max-frequency = <1000000>; + adi,output-power-value = <4>; + adi,power-up-frequency = /bits/ 64 ; + adi,cmos-3v3; + clocks = <<c6953 1>; + clock-names = "ref_clk"; + clock-output-names = "adf4382_3_out_clk"; + label = "adf4382_3"; + #io-channel-cells = <1>; + }; + + adf4351: adf4351@5 { + compatible = "adi,adf4351"; + reg = <5>; + + spi-max-frequency = <10000000>; + #clock-cells = <1>; + clocks = <<c6953 10>; + clock-names = "clkin"; + label = "adf4351"; + + adi,channel-spacing = <1000000>; + adi,power-up-frequency = ; /* 2 GHz */ + adi,phase-detector-polarity-positive-enable; + adi,lock-detect-function-integer-n-enable; + adi,charge-pump-current = <1>; + adi,output-power = <3>; + adi,mute-till-lock-enable; + adi,muxout-select = <6>; + }; + + ltc6952: ltc6952@6 { + compatible = "adi,ltc6952"; + reg = <6>; + #address-cells = <1>; + #size-cells = <0>; + spi-max-frequency = <10000000>; + label = "ltc6952"; + + clocks = <<c6953 8> , <&adf4351 0>; + clock-names = "clkin", "vcoin"; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-inputs = + <&axi_aion_trig 0 FRAMER_LINK_B0_RX>, + <&axi_aion_trig 0 DEFRAMER_LINK_B0_TX>; + + + clock-output-names = "ltc6952_out0", "ltc6952_out1", + "ltc6952_out2", "ltc6952_out3", "ltc6952_out4", + "ltc6952_out5", "ltc6952_out6", "ltc6952_out7", + "ltc6952_out8", "ltc6952_out9", "ltc6952_out10"; + + #clock-cells = <1>; + + adi,vco-frequency-hz = ; /* 2 GHz */ + adi,pulse-generator-mode = <2>; /* Four Pulses */ + adi,sync-via-ezs-srq-enable; + + channel@2 { + reg = <2>; + adi,extended-name = "FPGA_REFCLK"; + adi,divider = ; + adi,digital-delay = ; + adi,analog-delay = ; + //adi,sync-disable; + }; + channel@3 { + reg = <3>; + adi,extended-name = "FPGA_CORE_CLK_TX"; + adi,divider = ; + adi,digital-delay = ; + adi,analog-delay = ; + }; + channel@4 { + reg = <4>; + adi,extended-name = "FPGA_CORE_CLK_RX"; + adi,divider = ; + adi,digital-delay = ; + adi,analog-delay = ; + }; + + channel@5 { + reg = <5>; + adi,extended-name = "ADF4030_REF_IN"; + adi,divider = ; + adi,digital-delay = ; + adi,analog-delay = ; + }; + channel@6 { + reg = <6>; + adi,extended-name = "ADF4030_BSYNC_8"; + adi,divider = ; + adi,digital-delay = ; + adi,analog-delay = ; + }; + channel@7 { + reg = <7>; + adi,extended-name = "J48_J49_UFL_Output"; + adi,divider = ; + adi,digital-delay = ; + adi,analog-delay = ; + }; + }; + + adf4030: adf4030@4 { + #clock-cells = <1>; + compatible = "adi,adf4030"; + reg = <4>; + + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + + spi-max-frequency = <1000000>; + clocks = <<c6952 5>; + clock-names = "refin"; + clock-output-names = "adf4030_bsync_0", "adf4030_bsync_1", + "adf4030_bsync_2", "adf4030_bsync_3", "adf4030_bsync_4", + "adf4030_bsync_5", "adf4030_bsync_6", "adf4030_bsync_7", + "adf4030_bsync_8", "adf4030_bsync_9"; + label = "adf4030"; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-sysref-provider; + + adi,vco-frequency-hz = <2500000000>; /* 2.5 GHz */ + adi,bsync-frequency-hz = ; + adi,bsync-autoalign-reference-channel = <8>; /* LTC6952_OUT_6 */ + adi,bsync-autoalign-iteration-count = <6>; + adi,bsync-secondary-frequency-hz = <12500000>; /* 12.5 MHz */ + + channel@0 { + reg = <0>; + adi,extended-name = "APOLLO_SYSREF_0"; + adi,output-en; + adi,input-output-reconfig-en; + auto-align-on-sync-en; + adi,rcm = <1>; + adi,link-rx-en; + adi,float-rx-en; + }; + channel@1 { + reg = <1>; + adi,extended-name = "APOLLO_SYSREF_1"; + adi,output-en; + adi,input-output-reconfig-en; + auto-align-on-sync-en; + adi,rcm = <1>; + adi,link-rx-en; + adi,float-rx-en; + }; + channel@2 { + reg = <2>; + adi,extended-name = "APOLLO_SYSREF_2"; + adi,output-en; + adi,input-output-reconfig-en; + auto-align-on-sync-en; + adi,rcm = <1>; + adi,link-rx-en; + adi,float-rx-en; + }; + channel@3 { + reg = <3>; + adi,extended-name = "APOLLO_SYSREF_3"; + adi,output-en; + adi,input-output-reconfig-en; + auto-align-on-sync-en; + adi,rcm = <1>; + adi,link-rx-en; + adi,float-rx-en; + }; + channel@4 { + reg = <4>; + adi,extended-name = "FPGA_SYSREF_0"; /* RES rotate option for J40/J41 U.FL output */ + adi,output-en; + adi,input-output-reconfig-en; + auto-align-on-sync-en; + adi,rcm = <62>; + adi,link-rx-en; + adi,float-rx-en; + }; + // channel@5 { + // reg = <5>; + // adi,extended-name = "FPGA_SYSREF_1"; /* RES rotate option for J42/J43 U.FL output */ + // adi,output-en; + // adi,input-output-reconfig-en; + // adi,rcm = <62>; + // }; + channel@6 { + reg = <6>; + adi,extended-name = "LTC6953_OUT_6"; + adi,link-rx-en; + adi,float-rx-en; + }; + /* BSYNC7 unused */ + channel@8 { + reg = <8>; + adi,extended-name = "LTC6952_OUT_8"; + adi,link-rx-en; + adi,float-rx-en; + }; + channel@9 { + reg = <9>; + adi,extended-name = "J46_J47_UFL"; + adi,output-en; + adi,input-output-reconfig-en; + auto-align-on-sync-en; + adi,rcm = <62>; + }; + }; +}; + +&fmc_spi { + trx0_ad9084: ad9084@0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "adi,ad9084"; + reg = <0>; + spi-max-frequency = <5000000>; + label = "axi-ad9084-rx0"; + + gpio-controller; + #gpio-cells = <2>; + adi,gpio-exports = /bits/ 8 <7 10 11 12 13 14>; /* DSA Control GPIOS */ + + adi,axi-hsci-connected = <&axi_hsci_0>; +#ifdef HSCI_FIXED_TIMING_PAR + //adi,hsci-rx-clk-invert-en; + adi,hsci-rx-clk-adj = <7>; + adi,hsci-tx-clk-invert-en; + adi,hsci-tx-clk-adj = <7>; +#endif + adi,nyquist-zone = <2>; + adi,subclass = <1>; + + adi,hsci-auto-linkup-mode-en; + //adi,hsci-disable-after-boot-en; + + adi,jtx0-logical-lane-mapping = <11 0 11 11 11 11 11 1 11 11 11 11>; + adi,jtx1-logical-lane-mapping = <11 0 11 11 11 11 11 1 11 11 11 11>; + + adi,jrx0-physical-lane-mapping = <11 7 0 0 0 0 0 0 0 0 0 0>; + adi,jrx1-physical-lane-mapping = <11 7 0 0 0 0 0 0 0 0 0 0>; + + adi,jtx-ser-amplitude = <0>; + adi,jtx-ser-pre-emphasis = <2>; + adi,jtx-ser-post-emphasis = <1>; + + adi,clock-align-delay-adjust-gpio-num = /bits/ 8 <29 0>; + adi,clock-align-delay-strobe-gpio-num = /bits/ 8 <30 0>; + + /* Clocks */ + clocks = <&adf4382_0 0>; + clock-names = "dev_clk"; + dev_clk-clock-scales = <1 10>; + + clock-output-names = "rx0_sampl_clk", "tx0_sampl_clk"; + #clock-cells = <1>; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-top-device = <0>; /* This is the TOP device */ + jesd204-ignore-errors; + + + jesd204-link-ids = ; + + jesd204-inputs = + <&trx1_ad9084 0 FRAMER_LINK_A0_RX>, + <&trx1_ad9084 0 FRAMER_LINK_B0_RX>, + <&trx1_ad9084 0 DEFRAMER_LINK_A0_TX>, + <&trx1_ad9084 0 DEFRAMER_LINK_B0_TX>; + + reset-gpios = <&axi_gpio_2 0 0>; + trig-req-gpios = <&axi_gpio 32 0>; + adi,trigger-sync-en; + + adi,device-profile-fw-name = DEVICE_PROFILE_NAME; + + adi,multidevice-instance-count = <4>; + + io-channels = <&adf4030 0>, <&adf4382_0 0>; + io-channel-names = "bsync", "clk"; + + adi,aion-background-serial-alignment-en; + }; + + trx1_ad9084: axi-ad9084-rx1@1 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "adi,ad9084"; + reg = <1>; + spi-max-frequency = <5000000>; + label = "axi-ad9084-rx1"; + + gpio-controller; + #gpio-cells = <2>; + adi,gpio-exports = /bits/ 8 <7 10 11 12 13 14>; /* DSA Control GPIOS */ + + adi,axi-hsci-connected = <&axi_hsci_1>; +#ifdef HSCI_FIXED_TIMING_PAR + //adi,hsci-rx-clk-invert-en; + adi,hsci-rx-clk-adj = <6>; + adi,hsci-tx-clk-invert-en; + adi,hsci-tx-clk-adj = <6>; +#endif + adi,nyquist-zone = <2>; + adi,subclass = <1>; + + adi,hsci-auto-linkup-mode-en; + //adi,hsci-disable-after-boot-en; + + adi,jtx0-logical-lane-mapping = <11 0 11 11 11 11 11 1 11 11 11 11>; + adi,jtx1-logical-lane-mapping = <11 0 11 11 11 11 11 1 11 11 11 11>; + + adi,jrx0-physical-lane-mapping = <11 7 0 0 0 0 0 0 0 0 0 0>; + adi,jrx1-physical-lane-mapping = <11 7 0 0 0 0 0 0 0 0 0 0>; + + adi,jtx-ser-amplitude = <0>; + adi,jtx-ser-pre-emphasis = <2>; + adi,jtx-ser-post-emphasis = <1>; + + adi,clock-align-delay-adjust-gpio-num = /bits/ 8 <29 0>; + adi,clock-align-delay-strobe-gpio-num = /bits/ 8 <30 0>; + + /* Clocks */ + clocks = <&adf4382_1 0>; + clock-names = "dev_clk"; + dev_clk-clock-scales = <1 10>; + + clock-output-names = "rx1_sampl_clk", "tx1_sampl_clk"; + #clock-cells = <1>; + + jesd204-device; + #jesd204-cells = <2>; + + jesd204-inputs = + <&trx2_ad9084 0 FRAMER_LINK_A0_RX>, + <&trx2_ad9084 0 FRAMER_LINK_B0_RX>, + <&trx2_ad9084 0 DEFRAMER_LINK_A0_TX>, + <&trx2_ad9084 0 DEFRAMER_LINK_B0_TX>; + + reset-gpios = <&axi_gpio_2 1 0>; + + adi,device-profile-fw-name = DEVICE_PROFILE_NAME; + adi,trigger-sync-en; + + io-channels = <&adf4030 1>, <&adf4382_1 0>; + io-channel-names = "bsync", "clk"; + }; + + trx2_ad9084: axi-ad9084-rx2@2 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "adi,ad9084"; + reg = <2>; + spi-max-frequency = <5000000>; + label = "axi-ad9084-rx2"; + + gpio-controller; + #gpio-cells = <2>; + adi,gpio-exports = /bits/ 8 <7 10 11 12 13 14>; /* DSA Control GPIOS */ + + adi,axi-hsci-connected = <&axi_hsci_2>; +#ifdef HSCI_FIXED_TIMING_PAR + //adi,hsci-rx-clk-invert-en; + adi,hsci-rx-clk-adj = <7>; + adi,hsci-tx-clk-invert-en; + adi,hsci-tx-clk-adj = <6>; +#endif + adi,nyquist-zone = <2>; + adi,subclass = <1>; + + adi,hsci-auto-linkup-mode-en; + //adi,hsci-disable-after-boot-en; + + adi,jtx0-logical-lane-mapping = <11 0 11 11 11 11 11 1 11 11 11 11>; + adi,jtx1-logical-lane-mapping = <11 0 11 11 11 11 11 1 11 11 11 11>; + + adi,jrx0-physical-lane-mapping = <11 7 0 0 0 0 0 0 0 0 0 0>; + adi,jrx1-physical-lane-mapping = <11 7 0 0 0 0 0 0 0 0 0 0>; + + adi,jtx-ser-amplitude = <0>; + adi,jtx-ser-pre-emphasis = <2>; + adi,jtx-ser-post-emphasis = <1>; + + adi,clock-align-delay-adjust-gpio-num = /bits/ 8 <29 0>; + adi,clock-align-delay-strobe-gpio-num = /bits/ 8 <30 0>; + + /* Clocks */ + clocks = <&adf4382_2 0>; + clock-names = "dev_clk"; + dev_clk-clock-scales = <1 10>; + + clock-output-names = "rx2_sampl_clk", "tx2_sampl_clk"; + #clock-cells = <1>; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-ignore-errors; + + jesd204-inputs = + <&trx3_ad9084 0 FRAMER_LINK_A0_RX>, + <&trx3_ad9084 0 FRAMER_LINK_B0_RX>, + <&trx3_ad9084 0 DEFRAMER_LINK_A0_TX>, + <&trx3_ad9084 0 DEFRAMER_LINK_B0_TX>; + + reset-gpios = <&axi_gpio_2 2 0>; + + adi,device-profile-fw-name = DEVICE_PROFILE_NAME; + adi,trigger-sync-en; + io-channels = <&adf4030 2>, <&adf4382_2 0>; + io-channel-names = "bsync", "clk"; + }; + + trx3_ad9084: axi-ad9084-rx3@3 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "adi,ad9084"; + reg = <3>; + spi-max-frequency = <5000000>; + label = "axi-ad9084-rx3"; + + gpio-controller; + #gpio-cells = <2>; + adi,gpio-exports = /bits/ 8 <7 10 11 12 13 14>; /* DSA Control GPIOS */ + + adi,axi-hsci-connected = <&axi_hsci_3>; +#ifdef HSCI_FIXED_TIMING_PAR + //adi,hsci-rx-clk-invert-en; + adi,hsci-rx-clk-adj = <7>; + adi,hsci-tx-clk-invert-en; + adi,hsci-tx-clk-adj = <6>; +#endif + adi,nyquist-zone = <2>; + adi,subclass = <1>; + + adi,hsci-auto-linkup-mode-en; + //adi,hsci-disable-after-boot-en; + + adi,jtx0-logical-lane-mapping = <11 0 11 11 11 11 11 1 11 11 11 11>; + adi,jtx1-logical-lane-mapping = <11 0 11 11 11 11 11 1 11 11 11 11>; + + adi,jrx0-physical-lane-mapping = <11 7 0 0 0 0 0 0 0 0 0 0>; + adi,jrx1-physical-lane-mapping = <11 7 0 0 0 0 0 0 0 0 0 0>; + + adi,jtx-ser-amplitude = <0>; + adi,jtx-ser-pre-emphasis = <2>; + adi,jtx-ser-post-emphasis = <1>; + + adi,clock-align-delay-adjust-gpio-num = /bits/ 8 <29 0>; + adi,clock-align-delay-strobe-gpio-num = /bits/ 8 <30 0>; + + /* Clocks */ + clocks = <&adf4382_3 0>; + clock-names = "dev_clk"; + dev_clk-clock-scales = <1 10>; + + clock-output-names = "rx3_sampl_clk", "tx3_sampl_clk"; + #clock-cells = <1>; + + jesd204-device; + #jesd204-cells = <2>; + + jesd204-inputs = + <&axi_ad9084_core_rx 0 FRAMER_LINK_B0_RX>, + <&axi_ad9084_core_tx 0 DEFRAMER_LINK_B0_TX>; + + reset-gpios = <&axi_gpio_2 3 0>; + + adi,device-profile-fw-name = DEVICE_PROFILE_NAME; + adi,trigger-sync-en; + + io-channels = <&adf4030 3>, <&adf4382_3 0>; + io-channel-names = "bsync", "clk"; + }; +}; diff --git a/arch/microblaze/boot/dts/vcu118_quad_ad9084_revB_ext.dts b/arch/microblaze/boot/dts/vcu118_quad_ad9084_revB_ext.dts new file mode 100644 index 00000000000000..ecb74b2c660b92 --- /dev/null +++ b/arch/microblaze/boot/dts/vcu118_quad_ad9084_revB_ext.dts @@ -0,0 +1,127 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Analog Devices Quad-AD9084 RevB + * https://wiki.analog.com/resources/tools-software/linux-drivers/iio-mxfe/ad9084 + * https://wiki.analog.com/resources/eval/user-guides/ad9084_fmca_ebz/ad9084_fmca_ebz_hdl + * + * hdl_project: + * board_revision: + * + * Copyright (C) 2024 Analog Devices Inc. + */ + +#include "vcu118_quad_ad9084_revB.dts" + +&axi_spi_2 { + + /delete-node/ adf4030; + + adf4030: adf4030@4 { + #clock-cells = <1>; + compatible = "adi,adf4030"; + reg = <4>; + + #address-cells = <1>; + #size-cells = <0>; + #io-channel-cells = <1>; + + + spi-max-frequency = <1000000>; + clocks = <<c6952 5>; + clock-names = "refin"; + clock-output-names = "adf4030_bsync_0", "adf4030_bsync_1", + "adf4030_bsync_2", "adf4030_bsync_3", "adf4030_bsync_4", + "adf4030_bsync_5", "adf4030_bsync_6", "adf4030_bsync_7", + "adf4030_bsync_8", "adf4030_bsync_9"; + label = "adf4030"; + + jesd204-device; + #jesd204-cells = <2>; + jesd204-sysref-provider; + + adi,vco-frequency-hz = <2500000000>; /* 2.5 GHz */ + adi,bsync-frequency-hz = ; + adi,bsync-autoalign-reference-channel = <9>; /* J46_J47_UFL */ + adi,bsync-autoalign-iteration-count = <6>; + adi,bsync-secondary-frequency-hz = <12500000>; /* 12.5 MHz */ + + channel@0 { + reg = <0>; + adi,extended-name = "APOLLO_SYSREF_0"; + adi,output-en; + adi,input-output-reconfig-en; + auto-align-on-sync-en; + adi,rcm = <1>; + adi,link-rx-en; + adi,float-rx-en; + }; + channel@1 { + reg = <1>; + adi,extended-name = "APOLLO_SYSREF_1"; + adi,output-en; + adi,input-output-reconfig-en; + auto-align-on-sync-en; + adi,rcm = <1>; + adi,link-rx-en; + adi,float-rx-en; + }; + channel@2 { + reg = <2>; + adi,extended-name = "APOLLO_SYSREF_2"; + adi,output-en; + adi,input-output-reconfig-en; + auto-align-on-sync-en; + adi,rcm = <1>; + adi,link-rx-en; + adi,float-rx-en; + }; + channel@3 { + reg = <3>; + adi,extended-name = "APOLLO_SYSREF_3"; + adi,output-en; + adi,input-output-reconfig-en; + auto-align-on-sync-en; + adi,rcm = <1>; + adi,link-rx-en; + adi,float-rx-en; + }; + channel@4 { + reg = <4>; + adi,extended-name = "FPGA_SYSREF_0"; /* RES rotate option for J40/J41 U.FL output */ + adi,output-en; + adi,input-output-reconfig-en; + auto-align-on-sync-en; + adi,rcm = <62>; + adi,link-rx-en; + adi,float-rx-en; + }; + // channel@5 { + // reg = <5>; + // adi,extended-name = "FPGA_SYSREF_1"; /* RES rotate option for J42/J43 U.FL output */ + // adi,output-en; + // adi,input-output-reconfig-en; + // adi,rcm = <62>; + // }; + channel@6 { + reg = <6>; + adi,extended-name = "LTC6953_OUT_6"; + adi,link-rx-en; + adi,float-rx-en; + }; + /* BSYNC7 unused */ + channel@8 { + reg = <8>; + adi,extended-name = "LTC6952_OUT_8"; + adi,link-rx-en; + adi,float-rx-en; + }; + channel@9 { + reg = <9>; + adi,extended-name = "J46_J47_UFL"; + //adi,output-en; + adi,input-output-reconfig-en; + auto-align-on-sync-en; + adi,rcm = <62>; + }; + }; +}; \ No newline at end of file diff --git a/arch/microblaze/configs/adi_mb_apollo_defconfig b/arch/microblaze/configs/adi_mb_apollo_defconfig new file mode 100644 index 00000000000000..6a2ccdc98d0bb6 --- /dev/null +++ b/arch/microblaze/configs/adi_mb_apollo_defconfig @@ -0,0 +1,224 @@ +CONFIG_SYSVIPC=y +CONFIG_POSIX_MQUEUE=y +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=15 +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="rootfs.cpio.gz" +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_KERNEL_BASE_ADDR=0x80000000 +CONFIG_XILINX_MICROBLAZE0_USE_MSR_INSTR=1 +CONFIG_XILINX_MICROBLAZE0_USE_PCMP_INSTR=1 +CONFIG_XILINX_MICROBLAZE0_USE_BARREL=1 +CONFIG_XILINX_MICROBLAZE0_USE_DIV=1 +CONFIG_XILINX_MICROBLAZE0_USE_HW_MUL=2 +CONFIG_HZ_100=y +CONFIG_ADVANCED_OPTIONS=y +CONFIG_HIGHMEM=y +CONFIG_LOWMEM_SIZE_BOOL=y +CONFIG_KERNEL_START_BOOL=y +CONFIG_KERNEL_START=0x80000000 +CONFIG_TASK_SIZE_BOOL=y +# CONFIG_SECCOMP is not set +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_PARTITION_ADVANCED=y +# CONFIG_EFI_PARTITION is not set +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +CONFIG_BINFMT_MISC=y +# CONFIG_COMPACTION is not set +CONFIG_CMA=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_XFRM_USER=y +CONFIG_NET_KEY=y +CONFIG_NET_KEY_MIGRATE=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +CONFIG_SYN_COOKIES=y +CONFIG_NETWORK_SECMARK=y +CONFIG_NETFILTER=y +CONFIG_NETFILTER_NETLINK_LOG=y +CONFIG_NF_CONNTRACK=m +CONFIG_NF_CT_NETLINK=m +CONFIG_NETFILTER_XT_MARK=y +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=y +CONFIG_NETFILTER_XT_TARGET_LOG=y +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=y +CONFIG_NETFILTER_XT_MATCH_MAC=y +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_IP_NF_IPTABLES=y +CONFIG_IP_NF_FILTER=y +CONFIG_IP_NF_TARGET_REJECT=y +CONFIG_IP_NF_MANGLE=y +CONFIG_IP6_NF_IPTABLES=y +CONFIG_IP6_NF_FILTER=y +CONFIG_IP6_NF_TARGET_REJECT=y +CONFIG_IP6_NF_MANGLE=y +CONFIG_BRIDGE_NF_EBTABLES=y +CONFIG_BRIDGE_EBT_T_FILTER=y +CONFIG_BRIDGE_EBT_T_NAT=y +CONFIG_BRIDGE_EBT_MARK_T=y +CONFIG_BRIDGE=y +CONFIG_NET_DSA=y +CONFIG_PCI=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_EXTRA_FIRMWARE="app_signed_encrypted_B/flash_image_0x01030000.bin app_signed_encrypted_B/flash_image_0x02000000.bin app_signed_encrypted_B/flash_image_0x20000000.bin app_signed_encrypted_B/flash_image_0x21000000.bin app_signed_encrypted_prod_B/flash_image_0x01030000.bin app_signed_encrypted_prod_B/flash_image_0x02000000.bin app_signed_encrypted_prod_B/flash_image_0x20000000.bin app_signed_encrypted_prod_B/flash_image_0x21000000.bin id01_uc42.bin id01_uc43.bin 204C_M4_L8_NP12_16p2_6x1.bin 204C_M4_L8_NP16_20p0_4x4.bin 204C_M4_L8_NP16_20p0_4x2.bin" +CONFIG_EXTRA_FIRMWARE_DIR="./firmware" +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_CFI=y +CONFIG_MTD_JEDECPROBE=y +CONFIG_MTD_CFI_ADV_OPTIONS=y +CONFIG_MTD_CFI_INTELEXT=y +CONFIG_MTD_CFI_AMDSTD=y +CONFIG_MTD_CFI_STAA=y +CONFIG_MTD_RAM=y +CONFIG_MTD_COMPLEX_MAPPINGS=y +CONFIG_MTD_PHYSMAP=y +CONFIG_MTD_PHYSMAP_OF=y +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_SIZE=16384 +CONFIG_AD525X_DPOT=y +CONFIG_AD525X_DPOT_I2C=y +CONFIG_AD525X_DPOT_SPI=y +CONFIG_ADI_AXI_DATA_OFFLOAD=y +CONFIG_ADI_AXI_HSCI=y +CONFIG_XLNX_LCD=y +CONFIG_EEPROM_AT24=y +CONFIG_NETDEVICES=y +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_SAMSUNG is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +CONFIG_XILINX_AXI_EMAC=y +CONFIG_MARVELL_PHY=y +CONFIG_DP83867_PHY=y +CONFIG_XILINX_PHY=y +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_UARTLITE=y +CONFIG_SERIAL_UARTLITE_CONSOLE=y +# CONFIG_HW_RANDOM is not set +CONFIG_XILINX_HWICAP=y +CONFIG_I2C=y +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX=y +CONFIG_I2C_MUX_PCA954x=y +# CONFIG_I2C_HELPER_AUTO is not set +CONFIG_I2C_XILINX=y +CONFIG_SPI=y +CONFIG_SPI_XCOMM=y +CONFIG_SPI_AD9250FMC=y +CONFIG_SPI_XILINX=y +CONFIG_SPI_SPIDEV=y +CONFIG_GPIO_XILINX=y +CONFIG_GPIO_PCA953X=y +CONFIG_GPIO_PCA953X_IRQ=y +CONFIG_POWER_RESET=y +CONFIG_POWER_RESET_GPIO_RESTART=y +# CONFIG_HWMON is not set +CONFIG_WATCHDOG=y +CONFIG_XILINX_WATCHDOG=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +# CONFIG_USB_SUPPORT is not set +CONFIG_DMADEVICES=y +CONFIG_AXI_DMAC=y +CONFIG_XILINX_DMA=y +CONFIG_STAGING=y +CONFIG_COMMON_CLK_SI570=y +CONFIG_COMMON_CLK_SI5324=y +CONFIG_COMMON_CLK_AXI_CLKGEN=y +CONFIG_IIO=y +CONFIG_IIO_KFIFO_BUF=y +CONFIG_AD7291=y +CONFIG_ADM1177=y +CONFIG_AD9467=y +CONFIG_AD9081=y +CONFIG_AD9083=y +CONFIG_AD9088=y +CONFIG_AD9208=y +CONFIG_AD9361=y +CONFIG_AD9371=y +CONFIG_ADRV9009=y +CONFIG_ADRV9025=y +CONFIG_AD6676=y +CONFIG_AD9680=y +CONFIG_ADMC=y +CONFIG_AXI_FMCADC5_SYNC=y +CONFIG_ONE_BIT_ADC_DAC=y +CONFIG_AD8366=y +CONFIG_HMC425=y +CONFIG_AD5446=y +CONFIG_AD5592R=y +CONFIG_AD5593R=y +CONFIG_AD9523=y +CONFIG_AD9528=y +CONFIG_AD9548=y +CONFIG_AD9517=y +CONFIG_HMC7044=y +CONFIG_LTC6952=y +CONFIG_ADF4030=y +CONFIG_CF_AXI_DDS=y +CONFIG_CF_AXI_DDS_AD9122=y +CONFIG_CF_AXI_DDS_AD9144=y +CONFIG_ADF4350=y +CONFIG_ADF4371=y +CONFIG_ADF4382=y +CONFIG_ADF5355=y +CONFIG_AXI_ADXCVR=y +CONFIG_AXI_JESD204B=y +CONFIG_AXI_JESD204_TX=y +CONFIG_AXI_JESD204_RX=y +CONFIG_ADI_IIO_FAKEDEV=y +CONFIG_AXI_AION_TRIG=y +CONFIG_IIO_GEN_MUX=y +CONFIG_JESD204=y +CONFIG_NVMEM_AXI_SYSID=y +CONFIG_MUX_GPIO=y +CONFIG_EXT2_FS=y +CONFIG_EXT2_FS_XATTR=y +CONFIG_EXT2_FS_POSIX_ACL=y +CONFIG_EXT2_FS_SECURITY=y +CONFIG_EXT3_FS=y +CONFIG_EXT3_FS_POSIX_ACL=y +CONFIG_EXT3_FS_SECURITY=y +# CONFIG_DNOTIFY is not set +CONFIG_TMPFS=y +CONFIG_JFFS2_FS=y +CONFIG_JFFS2_SUMMARY=y +CONFIG_CRAMFS=y +CONFIG_ROMFS_FS=y +CONFIG_NFS_FS=y +CONFIG_CIFS=y +CONFIG_ENCRYPTED_KEYS=y +CONFIG_CRYPTO_AUTHENC=y +CONFIG_CRC_CCITT=y +CONFIG_DMA_CMA=y +CONFIG_CMA_SIZE_PERCENTAGE=25 +CONFIG_CMA_SIZE_SEL_PERCENTAGE=y +CONFIG_PRINTK_TIME=y +CONFIG_STACKTRACE_BUILD_ID=y +CONFIG_DEBUG_FS=y diff --git a/arch/microblaze/configs/adi_mb_defconfig b/arch/microblaze/configs/adi_mb_defconfig index eb2a1d979d85e4..c4aba83034421a 100644 --- a/arch/microblaze/configs/adi_mb_defconfig +++ b/arch/microblaze/configs/adi_mb_defconfig @@ -109,9 +109,7 @@ CONFIG_NETDEVICES=y # CONFIG_NET_VENDOR_STMICRO is not set # CONFIG_NET_VENDOR_VIA is not set # CONFIG_NET_VENDOR_WIZNET is not set -CONFIG_XILINX_EMACLITE=y CONFIG_XILINX_AXI_EMAC=y -CONFIG_XILINX_LL_TEMAC=y CONFIG_MARVELL_PHY=y CONFIG_DP83867_PHY=y CONFIG_XILINX_PHY=y diff --git a/drivers/clk/Kconfig.adi b/drivers/clk/Kconfig.adi index e6ca2ebf5efdce..e1e353a7c2e5b6 100644 --- a/drivers/clk/Kconfig.adi +++ b/drivers/clk/Kconfig.adi @@ -6,3 +6,4 @@ config CLK_ALL_ADI_DRIVERS imply COMMON_CLK_AD9545 imply COMMON_CLK_AD9545_I2C imply COMMON_CLK_AD9545_SPI + imply COMMON_CLK_LTC6948 diff --git a/drivers/clk/adi/Kconfig b/drivers/clk/adi/Kconfig index 768b8227f3363b..57e6bece84cb92 100644 --- a/drivers/clk/adi/Kconfig +++ b/drivers/clk/adi/Kconfig @@ -26,4 +26,16 @@ config COMMON_CLK_AD9545_SPI Quad Input, 10-Output, Dual DPLL/IEEE 1588, 1 pps Synchronizer and Jitter Cleaner via SPI +config COMMON_CLK_LTC6948 + tristate "Analog Devices LTC6948/LTC6947 Fractional-N Synthesizer with Integrated VCO" + depends on SPI + depends on COMMON_CLK + help + Say yes here to build support for Analog Devices LTC6948/LTC6947 + Fractional-N Synthesizer with Integrated VCO. + The driver provides direct access via sysfs. + + To compile this driver as a module, choose M here: the + module will be called ltc6948. + endmenu diff --git a/drivers/clk/adi/Makefile b/drivers/clk/adi/Makefile index 7ba1fded3013c3..409f83e88e0ba0 100644 --- a/drivers/clk/adi/Makefile +++ b/drivers/clk/adi/Makefile @@ -7,3 +7,4 @@ obj-$(CONFIG_COMMON_CLK_AD9545) += clk-ad9545.o obj-$(CONFIG_COMMON_CLK_AD9545_I2C) += clk-ad9545-i2c.o obj-$(CONFIG_COMMON_CLK_AD9545_SPI) += clk-ad9545-spi.o +obj-$(CONFIG_COMMON_CLK_LTC6948) += ltc6948.o diff --git a/drivers/clk/adi/ltc6948.c b/drivers/clk/adi/ltc6948.c new file mode 100644 index 00000000000000..c421ba7e82749b --- /dev/null +++ b/drivers/clk/adi/ltc6948.c @@ -0,0 +1,806 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Analog Devices ltc6948 SPI Fractional-N Synthesizer with Integrated VCO + * + * Copyright 2024 Analog Devices Inc. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +/* Register map defines */ +/* REG 0x0 */ +#define LTC6948_MSK_UNLOCK BIT(5) +#define LTC6948_MSK_ALCHI BIT(4) +#define LTC6948_MSK_ALCLO BIT(3) +#define LTC6948_MSK_LOCK BIT(2) +#define LTC6948_MSK_THI BIT(1) +#define LTC6948_MSK_TLO BIT(0) + +/* REG 0x1 */ +#define LTC6948_MSK_X GENMASK(5, 0) + +/* REG 0x2 */ +#define LTC6948_MSK_PDALL BIT(7) +#define LTC6948_MSK_PDPLL BIT(6) +#define LTC6948_MSK_PDVCO BIT(5) +#define LTC6948_MSK_PDOUT BIT(4) +#define LTC6948_MSK_PDFN BIT(3) +#define LTC6948_MSK_MTCAL BIT(2) +#define LTC6948_MSK_OMUTE BIT(1) +#define LTC6948_MSK_POR BIT(0) + +/* REG 0x3 */ +#define LTC6948_MSK_ALCEN BIT(7) +#define LTC6948_MSK_ALCMON BIT(6) +#define LTC6948_MSK_ALCCAL BIT(5) +#define LTC6948_MSK_ALCULOK BIT(4) +#define LTC6948_MSK_AUTOCAL BIT(3) +#define LTC6948_MSK_AUTORST BIT(2) +#define LTC6948_MSK_DITHEN BIT(1) +#define LTC6948_MSK_INTN BIT(0) + +/* REG 0x4 */ +#define LTC6948_MSK_BD GENMASK(7, 4) +#define LTC6948_MSK_CPLE BIT(3) +#define LTC6948_MSK_LDOEN BIT(2) +#define LTC6948_MSK_LDOV GENMASK(1, 0) + +/* REG 0x6 .. 0x7 */ +#define LTC6948_MSK_RD GENMASK(7, 3) +#define LTC6948_MSK_ND_98 GENMASK(1, 0) + +/* REG 0x8 .. 0xA */ +#define LTC6948_MSK_NUM_1712 GENMASK(5, 0) +#define LTC6948_MSK_NUM_114 GENMASK(7, 0) +#define LTC6948_MSK_NUM_03 GENMASK(7, 4) +#define LTC6948_MSK_RSTFN BIT(1) +#define LTC6948_MSK_CAL BIT(0) + +/* REG 0xB */ +#define LTC6948_MSK_BST BIT(7) +#define LTC6948_MSK_FILT GENMASK(6, 5) +#define LTC6948_MSK_RFO GENMASK(4, 3) +#define LTC6948_MSK_OD GENMASK(2, 0) + +/* REG 0xC */ +#define LTC6948_MSK_LKWIN GENMASK(7, 5) +#define LTC6948_MSK_LKCT GENMASK(4, 3) +#define LTC6948_MSK_CP GENMASK(2, 0) + +/* REG 0xD */ +#define LTC6948_MSK_CPCHI BIT(7) +#define LTC6948_MSK_CPCLO BIT(6) +#define LTC6948_MSK_CPMID BIT(5) +#define LTC6948_MSK_CPINV BIT(4) +#define LTC6948_MSK_CPWIDE BIT(3) +#define LTC6948_MSK_CPRST BIT(2) +#define LTC6948_MSK_CPUP BIT(1) +#define LTC6948_MSK_CPDN BIT(0) + +/* REG 0xE */ +#define LTC6948_MSK_REV GENMASK(7, 4) +#define LTC6948_MSK_PART GENMASK(3, 0) + +#define LTC6948_BREG(x) (st->buf[LTC6948_REG(x)]) + +/* Registers address macro */ +#define LTC6948_REG(x) (x) +#define LTC6948_REG_HW(x) ((x) << 1) +#define LTC6948_MODULUS BIT(18) + +#define LTC6948_1_MAXFREQ 3740000000ULL //!< LTC6948-1 upper freq limit +#define LTC6948_2_MAXFREQ 4910000000ULL //!< LTC6948-2 upper freq limit +#define LTC6948_3_MAXFREQ 5790000000ULL //!< LTC6948-3 upper freq limit +#define LTC6948_4_MAXFREQ 6390000000ULL //!< LTC6948-4 upper freq limit + +#define LTC6948_1_MINFREQ 2240000000ULL //!< LTC6948-1 lower freq limit +#define LTC6948_2_MINFREQ 3080000000ULL //!< LTC6948-2 lower freq limit +#define LTC6948_3_MINFREQ 3840000000ULL //!< LTC6948-3 lower freq limit +#define LTC6948_4_MINFREQ 4200000000ULL //!< LTC6948-4 lower freq limit + +#define LTC6948_1_FCALMAXFREQ 1000000 //!< LTC6948-1 cal-max freq limit +#define LTC6948_2_FCALMAXFREQ 1330000 //!< LTC6948-2 cal-max freq limit +#define LTC6948_3_FCALMAXFREQ 1700000 //!< LTC6948-3 cal-max freq limit +#define LTC6948_4_FCALMAXFREQ 1800000 //!< LTC6948-3 cal-max freq limit + +#define LTC6948_MIN_REF_FREQ 10000000 //!< LTC6948 lower reference frequency limit +#define LTC6948_MAX_REF_FREQ 425000000 //!< LTC6948 upper reference frequency limit + +#define MAX_FPFD_INTEGER 100000000UL +#define MAX_FPFD_FRACT 76100000UL + +#define MAX_INT_INTEGER 1023 +#define MAX_INT_FRACT 1019 +#define MIN_INT_INTEGER 32 +#define MIN_INT_FRACT 35 + +static const struct regmap_config ltc6948_regmap_config = { + .reg_bits = 8, + .val_bits = 8, + .read_flag_mask = BIT(0), +}; + +struct child_clk { + struct clk_hw hw; + struct ltc6948_state *st; + bool enabled; + struct clock_scale scale; +}; + +#define to_clk_priv(_hw) container_of(_hw, struct child_clk, hw) + +struct ltc6948_state { + struct spi_device *spi; + struct regmap *regmap; + struct clk *clkin; + unsigned long clkin_freq; + + unsigned long long max_vco_freq; + unsigned long long min_vco_freq; + unsigned long max_fcal_freq; + + u8 part_id, rev; + + u8 reg_1_default; + u8 reg_3_default; + u8 reg_4_default; + u8 reg_b_default; + u8 reg_c_default; + u8 reg_d_default; + + u8 buf[15] __aligned(IIO_DMA_MINALIGN); +}; + +static unsigned int ltc6948_fref_valid(u32 fref) +{ + if (fref < LTC6948_MIN_REF_FREQ || fref > LTC6948_MAX_REF_FREQ) + return -EINVAL; + + return 0; +}; + +static unsigned int ltc6948_filt(u32 fref) +{ + if (fref < 20000000) + return 3; + else if (fref > 50000000) + return 0; + else + return 1; +}; + +static int ltc6948_get_b_and_bd(unsigned int b, unsigned int *bd, unsigned int *b_value) +{ + switch (b) { + case 0 ... 8: + *bd = 0; + *b_value = 8; + break; + case 9 ... 12: + *bd = 1; + *b_value = 12; + break; + case 13 ... 16: + *bd = 2; + *b_value = 16; + break; + case 17 ... 24: + *bd = 3; + *b_value = 24; + break; + case 25 ... 32: + *bd = 4; + *b_value = 32; + break; + case 33 ... 48: + *bd = 5; + *b_value = 48; + break; + case 49 ... 64: + *bd = 6; + *b_value = 64; + break; + case 65 ... 96: + *bd = 7; + *b_value = 96; + break; + case 97 ... 128: + *bd = 8; + *b_value = 128; + break; + case 129 ... 192: + *bd = 9; + *b_value = 192; + break; + case 193 ... 256: + *bd = 10; + *b_value = 256; + break; + case 257 ... 384: + *bd = 11; + *b_value = 384; + break; + default: + return -EINVAL; + } + + return 0; +} + +static unsigned int ltc6948_lkwin_fract(unsigned int fvco, bool cple) +{ + if (cple) { + if (fvco >= 2970000000UL) + return 0; + else if (fvco >= 2000000000UL) + return 1; + else if (fvco >= 1390000000UL) + return 2; + else if (fvco >= 941000000UL) + return 3; + else if (fvco >= 646000000UL) + return 4; + else if (fvco >= 431000000UL) + return 5; + else if (fvco >= 294000000UL) + return 6; + else + return 7; + } else { + if (fvco >= 1350000000UL) + return 0; + else if (fvco >= 919000000UL) + return 1; + else if (fvco >= 632000000UL) + return 2; + else if (fvco >= 428000000UL) + return 3; + else if (fvco >= 294000000UL) + return 4; + else if (fvco >= 196000000UL) + return 5; + else if (fvco >= 134000000UL) + return 6; + else + return 7; + } +} + +static unsigned int ltc6948_lkwin_integer(unsigned int fpfd) +{ + if (fpfd > 6800000) + return 0; + else if (fpfd > 4700000) + return 1; + else if (fpfd > 3200000) + return 2; + else if (fpfd > 2200000) + return 3; + else if (fpfd > 1500000) + return 4; + else if (fpfd > 1000000) + return 5; + else if (fpfd > 660000) + return 6; + else + return 7; +} + +static void ltc6948_get_ldov_ldoen(unsigned int fpfd, unsigned int *ldov, bool *ldoen) +{ + if (fpfd <= 34300000UL) { + *ldov = 0; + *ldoen = true; + } else if (fpfd <= 45900000UL) { + *ldov = 1; + *ldoen = true; + } else if (fpfd <= 56100000UL) { + *ldov = 2; + *ldoen = true; + } else if (fpfd <= 66300000UL) { + *ldov = 3; + *ldoen = true; + } else { + *ldov = 0; + *ldoen = false; + } +} + +static unsigned int ltc6948_compute_cp(unsigned int icp) +{ + unsigned int cp; + + if (icp < 1400) + cp = 0; + else if (icp < 2000) + cp = 1; + else if (icp < 2800) + cp = 2; + else if (icp < 4000) + cp = 3; + else if (icp < 5600) + cp = 4; + else if (icp < 8000) + cp = 5; + else if (icp < 11200) + cp = 6; + else + cp = 7; // Default value + + return cp; +} + +static int ltc6948_set_freq(struct ltc6948_state *st, unsigned long parent_rate, + unsigned long long freq, unsigned long long *round_rate) +{ + u64 vco_freq, integer; + u32 b_min, bd_val, b_value, ldov, lkwin, odiv, rdiv, fpfd, fract; + int ret; + bool ldoen; + + ret = ltc6948_fref_valid(parent_rate); + if (ret < 0) { + dev_err(&st->spi->dev, "Fref frequency out of range %lu Hz\n", parent_rate); + return ret; + } + + odiv = DIV_ROUND_UP_ULL(st->min_vco_freq, freq); + vco_freq = freq * odiv; + + if (vco_freq < st->min_vco_freq || vco_freq > st->max_vco_freq) { + dev_err(&st->spi->dev, "VCO frequency out of range %llu Hz\n", vco_freq); + return -EINVAL; + } + + rdiv = DIV_ROUND_UP(parent_rate, MAX_FPFD_INTEGER); /* Assume integer mode for now */ + fpfd = parent_rate / rdiv; + + integer = vco_freq; + fract = do_div(integer, fpfd); + if (fract) { + rdiv = DIV_ROUND_UP(parent_rate, MAX_FPFD_FRACT); /* Fract mode max fpfd = 76.1 MHz */ + fpfd = parent_rate / rdiv; + + integer = vco_freq; + fract = do_div(integer, fpfd); + fract = DIV_ROUND_CLOSEST_ULL(fract * LTC6948_MODULUS, fpfd); + if (fract > LTC6948_MODULUS) { + dev_err(&st->spi->dev, "Fract-N %u modulus out of range\n", fract); + return -EINVAL; + } + } + + if (fract == 0) { + if (integer > MAX_INT_INTEGER || integer < MIN_INT_INTEGER) { + dev_err(&st->spi->dev, "N-Divider %llu out of range for integer mode\n", integer); + return -EINVAL; + } + st->buf[LTC6948_REG(0x3)] = st->reg_3_default | LTC6948_MSK_INTN; + lkwin = ltc6948_lkwin_integer(fpfd); + } else { + if (integer > MAX_INT_FRACT || integer < MIN_INT_FRACT) { + dev_err(&st->spi->dev, "N-Divider %llu out of range for fractional mode\n", integer); + return -EINVAL; + } + st->buf[LTC6948_REG(0x3)] = st->reg_3_default; + lkwin = ltc6948_lkwin_fract(vco_freq, !!(st->reg_4_default & LTC6948_MSK_CPLE)); + } + + if (round_rate) { + u64 val; + + val = ((integer * LTC6948_MODULUS) + fract) * fpfd; + do_div(val, LTC6948_MODULUS * odiv); + + *round_rate = val; + + return 0; + } + + b_min = DIV_ROUND_UP(fpfd, st->max_fcal_freq); + ret = ltc6948_get_b_and_bd(b_min, &bd_val, &b_value); + if (ret < 0) { + dev_err(&st->spi->dev, "B value out of range\n"); + return ret; + } + + ltc6948_get_ldov_ldoen(fpfd, &ldov, &ldoen); + st->buf[LTC6948_REG(0x4)] = FIELD_PREP(LTC6948_MSK_BD, bd_val) | + FIELD_PREP(LTC6948_MSK_LDOV, ldov) | + FIELD_PREP(LTC6948_MSK_LDOEN, ldoen) | + st->reg_4_default; + + st->buf[LTC6948_REG(0x5)] = 0x11 /* default SEED */; + st->buf[LTC6948_REG(0x6)] = FIELD_PREP(LTC6948_MSK_ND_98, integer >> 8) | (rdiv << 3); + st->buf[LTC6948_REG(0x7)] = integer & 0xFF; + st->buf[LTC6948_REG(0x8)] = FIELD_PREP(LTC6948_MSK_NUM_1712, fract >> 12); + st->buf[LTC6948_REG(0x9)] = FIELD_PREP(LTC6948_MSK_NUM_114, fract >> 4); + st->buf[LTC6948_REG(0xA)] = FIELD_PREP(LTC6948_MSK_NUM_03, fract); + + st->buf[LTC6948_REG(0xB)] = st->reg_b_default | + FIELD_PREP(LTC6948_MSK_FILT, ltc6948_filt(parent_rate)) | + FIELD_PREP(LTC6948_MSK_OD, odiv); + + st->buf[LTC6948_REG(0xC)] = st->reg_c_default | + FIELD_PREP(LTC6948_MSK_LKWIN, lkwin); + + ret = regmap_raw_write(st->regmap, LTC6948_REG_HW(0x3), &st->buf[LTC6948_REG(0x3)], 10); + if (ret < 0) + return ret; + + dev_dbg(&st->spi->dev, + "odiv %d rdiv %d fpfd %d integer %llu fract %d lkwin %d ldov %d ldoen %d\n", + odiv, rdiv, fpfd, integer, fract, lkwin, ldov, ldoen); + + return 0; +} + +static int ltc6948_pll_fract_n_get_rate(struct ltc6948_state *st, unsigned long parent_rate, u64 *freq) +{ + unsigned long long val = 0; + u32 o_div, fpfd, ref_div; + u64 integer, fract; + int ret; + + ret = regmap_raw_read(st->regmap, LTC6948_REG_HW(0x6), &st->buf[LTC6948_REG(0x6)], 6); + if (ret < 0) + return ret; + + o_div = FIELD_GET(LTC6948_MSK_OD, LTC6948_BREG(0xB)); + ref_div = FIELD_GET(LTC6948_MSK_RD, LTC6948_BREG(0x6)); + integer = (FIELD_GET(LTC6948_MSK_ND_98, LTC6948_BREG(0x6)) << 8) | + LTC6948_BREG(0x7); + fract = (FIELD_GET(LTC6948_MSK_NUM_1712, LTC6948_BREG(0x8)) << 12) | + LTC6948_BREG(0x9) << 4 | + (FIELD_GET(LTC6948_MSK_NUM_03, LTC6948_BREG(0xA))); + + if (!ref_div || !o_div) + return -EINVAL; + + fpfd = st->clkin_freq / ref_div; + + val = ((integer * LTC6948_MODULUS) + fract) * fpfd; + do_div(val, LTC6948_MODULUS * o_div); + + *freq = val; + + dev_dbg(&st->spi->dev, "o_div %d ref_div %d integer %llu fract %llu fpfd %d freq %llu\n", + o_div, ref_div, integer, fract, fpfd, *freq); + + return 0; +} + +static long ltc6948_clock_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + unsigned long long scaled_rate; + int ret; + + scaled_rate = from_ccf_scaled(rate, &to_clk_priv(hw)->scale); + ret = ltc6948_set_freq(to_clk_priv(hw)->st, *parent_rate, scaled_rate, &scaled_rate); + if (ret < 0) + return ret; + + return to_ccf_scaled(scaled_rate, &to_clk_priv(hw)->scale); +} + +static unsigned long ltc6948_clock_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + unsigned long long rate; + + ltc6948_pll_fract_n_get_rate(to_clk_priv(hw)->st, parent_rate, &rate); + + return to_ccf_scaled(rate, &to_clk_priv(hw)->scale); +} + +static int ltc6948_clock_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + return ltc6948_set_freq(to_clk_priv(hw)->st, parent_rate, + from_ccf_scaled(rate, &to_clk_priv(hw)->scale), NULL); +} + +static int ltc6948_clock_enable(struct clk_hw *hw) +{ + struct ltc6948_state *st = to_clk_priv(hw)->st; + int ret; + + ret = regmap_clear_bits(st->regmap, LTC6948_REG_HW(0x2), LTC6948_MSK_OMUTE); + if (!ret) + to_clk_priv(hw)->enabled = true; + + return ret; +} + +void ltc6948_clock_disable(struct clk_hw *hw) +{ + struct ltc6948_state *st = to_clk_priv(hw)->st; + int ret; + + ret = regmap_set_bits(st->regmap, LTC6948_REG_HW(0x2), LTC6948_MSK_OMUTE); + if (!ret) + to_clk_priv(hw)->enabled = false; +} + +static int ltc6948_clk_is_enabled(struct clk_hw *hw) +{ + return to_clk_priv(hw)->enabled; +} + +#ifdef CONFIG_DEBUG_FS +#include + +static int ltc6948_debugfs_show(struct seq_file *s, void *p) +{ + struct ltc6948_state *st = s->private; + u32 status; + int ret; + + ret = regmap_read(st->regmap, LTC6948_REG_HW(0), &status); + if (ret < 0) + return ret; + + seq_printf(s, "LTC6948-%u Rev.%u Status: PLL %s%s%s%s%s\n", st->part_id, st->rev, + (status & LTC6948_MSK_LOCK) ? " Locked" : "Unlocked", + (status & LTC6948_MSK_ALCHI) ? " ALC too high" : "", + (status & LTC6948_MSK_ALCLO) ? " ALC too low" : "", + (status & LTC6948_MSK_THI) ? " CP too high" : "", + (status & LTC6948_MSK_TLO) ? " CP too low" : ""); + + return 0; +} +DEFINE_SHOW_ATTRIBUTE(ltc6948_debugfs); + +static void ltc6948_debug_init(struct clk_hw *hw, struct dentry *dentry) +{ + debugfs_create_file("status", 0444, dentry, to_clk_priv(hw)->st, <c6948_debugfs_fops); +} +#else +#define ltc6948_debug_init NULL +#endif + +static const struct clk_ops ltc6948_clock_ops = { + .set_rate = ltc6948_clock_set_rate, + .recalc_rate = ltc6948_clock_recalc_rate, + .round_rate = ltc6948_clock_round_rate, + .enable = ltc6948_clock_enable, + .disable = ltc6948_clock_disable, + .is_enabled = ltc6948_clk_is_enabled, + .debug_init = ltc6948_debug_init, +}; + +static void ltc6948_of_clk_del_provider(void *data) +{ + struct device *dev = data; + + of_clk_del_provider(dev->of_node); +} + +static int ltc6948_clk_register(struct ltc6948_state *st) +{ + struct child_clk *clk_priv; + struct clk_init_data init; + const char *parent_name; + const char *clk_name; + struct clk *clk_out; + struct spi_device *spi = st->spi; + int ret; + + if (!IS_ENABLED(CONFIG_OF)) + return 0; + + clk_priv = devm_kzalloc(&spi->dev, sizeof(*clk_priv), GFP_KERNEL); + if (!clk_priv) + return -ENOMEM; + + /* struct child_clk assignments */ + clk_priv->hw.init = &init; + clk_priv->st = st; + clk_name = spi->dev.of_node->name; + of_property_read_string(spi->dev.of_node, "clock-output-names", + &clk_name); + + ret = of_clk_get_scale(spi->dev.of_node, + NULL, &clk_priv->scale); + if (ret < 0) { + clk_priv->scale.mult = 1; + clk_priv->scale.div = 10; + } + + init.name = clk_name; + init.ops = <c6948_clock_ops; + init.flags = 0; + parent_name = __clk_get_name(st->clkin); + init.parent_names = &parent_name; + init.num_parents = 1; + clk_out = devm_clk_register(&spi->dev, &clk_priv->hw); + if (IS_ERR(clk_out)) + return PTR_ERR(clk_out); + + ret = of_clk_add_provider(spi->dev.of_node, + of_clk_src_simple_get, clk_out); + if (ret) + return ret; + + return devm_add_action_or_reset(&spi->dev, + ltc6948_of_clk_del_provider, &spi->dev); +} + +static int ltc6948_parse_dt(struct ltc6948_state *st) +{ + u32 val; + + if (device_property_read_bool(&st->spi->dev, "adi,ref-boost-enable")) + st->reg_b_default |= LTC6948_MSK_BST; + + val = 3; /* default to max */ + device_property_read_u32(&st->spi->dev, "adi,output-power", &val); + st->reg_b_default |= FIELD_PREP(LTC6948_MSK_RFO, val); + + val = 1; /* 32 */ + device_property_read_u32(&st->spi->dev, "adi,lock-count", &val); + st->reg_c_default = FIELD_PREP(LTC6948_MSK_LKCT, val); + + val = 5600; + device_property_read_u32(&st->spi->dev, "adi,charge-pump-current-uA", &val); + st->reg_c_default |= FIELD_PREP(LTC6948_MSK_CP, ltc6948_compute_cp(val)); + + st->reg_3_default = LTC6948_MSK_ALCEN | LTC6948_MSK_ALCMON | + LTC6948_MSK_ALCCAL | LTC6948_MSK_AUTOCAL | + LTC6948_MSK_AUTORST; + + if (device_property_read_bool(&st->spi->dev, "adi,dither-enable")) + st->reg_3_default |= LTC6948_MSK_DITHEN; + + val = 0; /* disabled */ + device_property_read_u32(&st->spi->dev, "adi,status-output-or-mask", &val); + st->reg_1_default = FIELD_PREP(LTC6948_MSK_X, val); + + st->reg_4_default = LTC6948_MSK_CPLE; + if (device_property_read_bool(&st->spi->dev, "adi,cp-linearizer-disable")) + st->reg_4_default = 0; + + if (device_property_read_bool(&st->spi->dev, "adi,cp-extended-pulse-width-enable")) + st->reg_d_default |= LTC6948_MSK_CPWIDE; + + if (device_property_read_bool(&st->spi->dev, "adi,cp-phase-invert-enable")) + st->reg_d_default |= LTC6948_MSK_CPINV; + + return 0; +} + +static int ltc6948_probe(struct spi_device *spi) +{ + struct ltc6948_state *st; + struct regmap *regmap; + int ret; + u32 val; + + regmap = devm_regmap_init_spi(spi, <c6948_regmap_config); + if (IS_ERR(regmap)) { + dev_err(&spi->dev, "Error initializing spi regmap: %ld\n", + PTR_ERR(regmap)); + return PTR_ERR(regmap); + } + + st = devm_kzalloc(&spi->dev, sizeof(*st), GFP_KERNEL); + if (!st) + return -ENOMEM; + + spi_set_drvdata(spi, st); + st->spi = spi; + st->regmap = regmap; + + ret = ltc6948_parse_dt(st); + if (ret < 0) + return ret; + + st->clkin = devm_clk_get_enabled(&spi->dev, "clkin"); + if (IS_ERR(st->clkin)) + return PTR_ERR(st->clkin); + + st->clkin_freq = clk_get_rate(st->clkin); + + /* Force Power-On-Reset */ + regmap_write(st->regmap, LTC6948_REG_HW(0x2), LTC6948_MSK_POR | + LTC6948_MSK_OMUTE | LTC6948_MSK_MTCAL); + fsleep(10); + regmap_write(st->regmap, LTC6948_REG_HW(0x2), LTC6948_MSK_OMUTE | + LTC6948_MSK_MTCAL); + + regmap_read(st->regmap, LTC6948_REG_HW(0xE), &val); + + st->part_id = FIELD_GET(LTC6948_MSK_PART, val); + st->rev = FIELD_GET(LTC6948_MSK_REV, val); + + switch (st->part_id) { + case 1: + st->max_vco_freq = LTC6948_1_MAXFREQ; + st->min_vco_freq = LTC6948_1_MINFREQ; + st->max_fcal_freq = LTC6948_1_FCALMAXFREQ; + break; + case 2: + st->max_vco_freq = LTC6948_2_MAXFREQ; + st->min_vco_freq = LTC6948_2_MINFREQ; + st->max_fcal_freq = LTC6948_2_FCALMAXFREQ; + break; + case 3: + st->max_vco_freq = LTC6948_3_MAXFREQ; + st->min_vco_freq = LTC6948_3_MINFREQ; + st->max_fcal_freq = LTC6948_3_FCALMAXFREQ; + break; + case 4: + st->max_vco_freq = LTC6948_4_MAXFREQ; + st->min_vco_freq = LTC6948_4_MINFREQ; + st->max_fcal_freq = LTC6948_4_FCALMAXFREQ; + break; + default: + dev_err(&spi->dev, "Invalid part id\n"); + return -EINVAL; + } + + ret = regmap_write(st->regmap, LTC6948_REG_HW(0x1), st->reg_1_default); + if (ret < 0) + return ret; + + ret = regmap_write(st->regmap, LTC6948_REG_HW(0xD), st->reg_d_default); + if (ret < 0) + return ret; + + ret = ltc6948_clk_register(st); + if (ret < 0) + return ret; + + dev_info(&spi->dev, "LTC6948-%u Rev.%u successfully initialized\n", st->part_id, st->rev); + + return ret; +} + +static const struct spi_device_id ltc6948_id_table[] = { + { "ltc6948", 0 }, + { "ltc6948-1", 1 }, + { "ltc6948-2", 2 }, + { "ltc6948-3", 3 }, + { "ltc6948-4", 4 }, + {} +}; +MODULE_DEVICE_TABLE(spi, ltc6948_id_table); + +static const struct of_device_id ltc6948_of_match[] = { + { .compatible = "adi,ltc6948" }, + { .compatible = "adi,ltc6948-1" }, + { .compatible = "adi,ltc6948-2" }, + { .compatible = "adi,ltc6948-3" }, + { .compatible = "adi,ltc6948-4" }, + { }, +}; +MODULE_DEVICE_TABLE(of, ltc6948_of_match); + +static struct spi_driver ltc6948_driver = { + .driver = { + .name = "ltc6948", + .of_match_table = ltc6948_of_match, + }, + .probe = ltc6948_probe, + .id_table = ltc6948_id_table, +}; +module_spi_driver(ltc6948_driver); + +MODULE_AUTHOR("Michael Hennerich "); +MODULE_DESCRIPTION("Analog Devices LTC6948 Synthesizer"); +MODULE_LICENSE("GPL"); diff --git a/drivers/dma/dma-axi-dmac.c b/drivers/dma/dma-axi-dmac.c index 0eb8029797ddcf..c479b7e3a8bc5d 100644 --- a/drivers/dma/dma-axi-dmac.c +++ b/drivers/dma/dma-axi-dmac.c @@ -135,6 +135,8 @@ struct axi_dmac_desc { struct virt_dma_desc vdesc; struct axi_dmac_chan *chan; + struct work_struct sched_work; + bool cyclic; bool have_partial_xfer; @@ -532,6 +534,26 @@ static void axi_dmac_issue_pending(struct dma_chan *c) spin_unlock_irqrestore(&chan->vchan.lock, flags); } +static void axi_dmac_free_desc(struct axi_dmac_desc *desc) +{ + struct axi_dmac *dmac = chan_to_axi_dmac(desc->chan); + struct device *dev = dmac->dma_dev.dev; + struct axi_dmac_hw_desc *hw = desc->sg[0].hw; + dma_addr_t hw_phys = desc->sg[0].hw_phys; + + dma_free_coherent(dev, PAGE_ALIGN(desc->num_sgs * sizeof(*hw)), + hw, hw_phys); + kfree(desc); +} + +static void axi_dmac_free_desc_schedule_work(struct work_struct *work) +{ + struct axi_dmac_desc *desc = container_of(work, + struct axi_dmac_desc, + sched_work); + axi_dmac_free_desc(desc); +} + static struct axi_dmac_desc * axi_dmac_alloc_desc(struct axi_dmac_chan *chan, unsigned int num_sgs) { @@ -569,19 +591,12 @@ axi_dmac_alloc_desc(struct axi_dmac_chan *chan, unsigned int num_sgs) /* The last hardware descriptor will trigger an interrupt */ desc->sg[num_sgs - 1].hw->flags = AXI_DMAC_HW_FLAG_LAST | AXI_DMAC_HW_FLAG_IRQ; - return desc; -} + /* Initialize a workqueue to schedule work to be performed outside of + * interrupt context, which allows other operations to be run in a + * process context, making it safe to execute.*/ + INIT_WORK(&desc->sched_work, axi_dmac_free_desc_schedule_work); -static void axi_dmac_free_desc(struct axi_dmac_desc *desc) -{ - struct axi_dmac *dmac = chan_to_axi_dmac(desc->chan); - struct device *dev = dmac->dma_dev.dev; - struct axi_dmac_hw_desc *hw = desc->sg[0].hw; - dma_addr_t hw_phys = desc->sg[0].hw_phys; - - dma_free_coherent(dev, PAGE_ALIGN(desc->num_sgs * sizeof(*hw)), - hw, hw_phys); - kfree(desc); + return desc; } static struct axi_dmac_sg *axi_dmac_fill_linear_sg(struct axi_dmac_chan *chan, @@ -842,7 +857,10 @@ static void axi_dmac_free_chan_resources(struct dma_chan *c) static void axi_dmac_desc_free(struct virt_dma_desc *vdesc) { - axi_dmac_free_desc(to_axi_dmac_desc(vdesc)); + struct axi_dmac_desc *desc = to_axi_dmac_desc(vdesc); + + /* vunmap() must be performed outside of interrupt context */ + schedule_work(&desc->sched_work); } static bool axi_dmac_regmap_rdwr(struct device *dev, unsigned int reg) diff --git a/drivers/fpga/xilinx-selectmap.c b/drivers/fpga/xilinx-selectmap.c index 2cd87e7e913ff7..933fd0cdca4121 100644 --- a/drivers/fpga/xilinx-selectmap.c +++ b/drivers/fpga/xilinx-selectmap.c @@ -17,9 +17,22 @@ #include #include +#define IP_DATA_REG 0x18 + +enum xilinx_selectmap_device_ids { + ID_XC7S_SELMAP, + ID_XC7A_SELMAP, + ID_XC7K_SELMAP, + ID_XC7V_SELMAP, + ID_ADI_8_SELMAP, + ID_ADI_16_SELMAP, + ID_ADI_32_SELMAP, +}; + struct xilinx_selectmap_conf { struct xilinx_fpga_core core; void __iomem *base; + enum xilinx_selectmap_device_ids id; }; #define to_xilinx_selectmap_conf(obj) \ @@ -30,9 +43,27 @@ static int xilinx_selectmap_write(struct xilinx_fpga_core *core, { struct xilinx_selectmap_conf *conf = to_xilinx_selectmap_conf(core); size_t i; - - for (i = 0; i < count; ++i) - writeb(buf[i], conf->base); + const u16 *buf16 = (u16 *)buf; + const u32 *buf32 = (u32 *)buf; + + switch (conf->id) { + case ID_ADI_8_SELMAP: + for (i = 0; i < count; ++i) + writeb(buf[i], conf->base + IP_DATA_REG); + break; + case ID_ADI_16_SELMAP: + for (i = 0; i < (count/2)+1; ++i) + writew(cpu_to_be16(buf16[i]), conf->base + IP_DATA_REG); + break; + case ID_ADI_32_SELMAP: + for (i = 0; i < (count/4)+1; ++i) + writel(cpu_to_be32(buf32[i]), conf->base + IP_DATA_REG); + break; + default: + for (i = 0; i < count; ++i) + writeb(buf[i], conf->base); + break; + } return 0; } @@ -49,6 +80,7 @@ static int xilinx_selectmap_probe(struct platform_device *pdev) conf->core.dev = &pdev->dev; conf->core.write = xilinx_selectmap_write; + conf->id = (enum xilinx_selectmap_device_ids)device_get_match_data(&pdev->dev); base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); if (IS_ERR(base)) @@ -72,10 +104,13 @@ static int xilinx_selectmap_probe(struct platform_device *pdev) } static const struct of_device_id xlnx_selectmap_of_match[] = { - { .compatible = "xlnx,fpga-xc7s-selectmap", }, // Spartan-7 - { .compatible = "xlnx,fpga-xc7a-selectmap", }, // Artix-7 - { .compatible = "xlnx,fpga-xc7k-selectmap", }, // Kintex-7 - { .compatible = "xlnx,fpga-xc7v-selectmap", }, // Virtex-7 + { .compatible = "xlnx,fpga-xc7s-selectmap", .data = (void *)ID_XC7S_SELMAP, }, // Spartan-7 + { .compatible = "xlnx,fpga-xc7a-selectmap", .data = (void *)ID_XC7A_SELMAP, }, // Artix-7 + { .compatible = "xlnx,fpga-xc7k-selectmap", .data = (void *)ID_XC7K_SELMAP, }, // Kintex-7 + { .compatible = "xlnx,fpga-xc7v-selectmap", .data = (void *)ID_XC7V_SELMAP, }, // Virtex-7 + { .compatible = "adi,fpga-8-selectmap", .data = (void *)ID_ADI_8_SELMAP, }, // ADI 8bit version + { .compatible = "adi,fpga-16-selectmap", .data = (void *)ID_ADI_16_SELMAP, }, // ADI 16bit version + { .compatible = "adi,fpga-32-selectmap", .data = (void *)ID_ADI_32_SELMAP, }, // ADI 32bit version {}, }; MODULE_DEVICE_TABLE(of, xlnx_selectmap_of_match); diff --git a/drivers/iio/Kconfig b/drivers/iio/Kconfig index 2f3397cc41a90e..fdda8879b87814 100644 --- a/drivers/iio/Kconfig +++ b/drivers/iio/Kconfig @@ -116,5 +116,6 @@ source "drivers/iio/pressure/Kconfig" source "drivers/iio/proximity/Kconfig" source "drivers/iio/resolver/Kconfig" source "drivers/iio/temperature/Kconfig" +source "drivers/iio/trx-rf/Kconfig" endif # IIO diff --git a/drivers/iio/Kconfig.adi b/drivers/iio/Kconfig.adi index d34388a1c2c580..04db5435ac0825 100644 --- a/drivers/iio/Kconfig.adi +++ b/drivers/iio/Kconfig.adi @@ -217,3 +217,7 @@ config IIO_ALL_ADI_DRIVERS imply AD7091R8 imply AD9739A imply MAX22007 + imply ADF4382 + imply AXI_AION_TRIG + imply AD9088 + diff --git a/drivers/iio/Makefile b/drivers/iio/Makefile index 6d9f49723e70f4..7b9583761e974c 100644 --- a/drivers/iio/Makefile +++ b/drivers/iio/Makefile @@ -50,4 +50,5 @@ obj-y += resolver/ obj-y += temperature/ obj-y += test/ obj-y += trigger/ +obj-y += trx-rf/ diff --git a/drivers/iio/adc/ad_adc.c b/drivers/iio/adc/ad_adc.c index a2b03e7b091766..4da9c2055a6443 100644 --- a/drivers/iio/adc/ad_adc.c +++ b/drivers/iio/adc/ad_adc.c @@ -37,14 +37,38 @@ #include #include + +#define ADI_REG_CONFIG 0x000C +#define ADI_IQCORRECTION_DISABLE (1 << 0) +#define ADI_DCFILTER_DISABLE (1 << 1) +#define ADI_DATAFORMAT_DISABLE (1 << 2) +#define ADI_USERPORTS_DISABLE (1 << 3) +#define ADI_MODE_1R1T (1 << 4) +#define ADI_DELAY_CONTROL_DISABLE (1 << 5) +#define ADI_CMOS_OR_LVDS_N (1 << 7) +#define ADI_PPS_RECEIVER_ENABLE (1 << 8) +#define ADI_SCALECORRECTION_ONLY (1 << 9) +#define ADI_EXT_SYNC (1 << 12) + /* ADC Common */ #define ADI_REG_RSTN 0x0040 #define ADI_RSTN (1 << 0) +#define ADI_REG_CNTRL 0x0044 +#define ADI_SYNC (1 << 3) + +#define ADI_REG_CNTRL_2 0x0048 +#define ADI_EXT_SYNC_ARM (1 << 1) +#define ADI_EXT_SYNC_DISARM (1 << 2) +#define ADI_MANUAL_SYNC_REQUEST (1 << 8) + #define ADI_REG_STATUS 0x005C #define ADI_REG_DMA_STATUS 0x0088 #define ADI_REG_USR_CNTRL_1 0x00A0 +#define ADI_REG_SYNC_STATUS 0x0068 +#define ADI_ADC_SYNC_STATUS (1 << 0) + /* ADC Channel */ #define ADI_REG_CHAN_CNTRL(c) (0x0400 + (c) * 0x40) #define ADI_IQCOR_ENB (1 << 9) @@ -101,6 +125,7 @@ struct axiadc_state { unsigned int adc_calibbias[2]; unsigned int adc_calibscale[2][2]; bool calibrate; + bool ext_sync_avail; }; #define CN0363_CHANNEL(_address, _type, _ch, _mod, _rb) { \ @@ -611,13 +636,104 @@ static int adc_reg_access(struct iio_dev *indio_dev, return 0; } +static const char * const axiadc_sync_ctrls[] = { + "arm", "disarm", "trigger_manual", +}; + +static ssize_t axiadc_sync_start_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t len) +{ + struct iio_dev *indio_dev = dev_to_iio_dev(dev); + struct axiadc_state *st = iio_priv(indio_dev); + int ret; + + ret = sysfs_match_string(axiadc_sync_ctrls, buf); + if (ret < 0) + return ret; + + mutex_lock(&st->lock); + if (st->ext_sync_avail) { + switch (ret) { + case 0: + axiadc_write(st, ADI_REG_CNTRL_2, ADI_EXT_SYNC_ARM); + break; + case 1: + axiadc_write(st, ADI_REG_CNTRL_2, ADI_EXT_SYNC_DISARM); + break; + case 2: + axiadc_write(st, ADI_REG_CNTRL_2, ADI_MANUAL_SYNC_REQUEST); + break; + default: + ret = -EINVAL; + } + } else if (ret == 0) { + u32 reg; + + reg = axiadc_read(st, ADI_REG_CNTRL); + axiadc_write(st, ADI_REG_CNTRL, reg | ADI_SYNC); + } + mutex_unlock(&st->lock); + + return ret < 0 ? ret : len; +} + +static ssize_t axiadc_sync_start_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct iio_dev *indio_dev = dev_to_iio_dev(dev); + struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); + struct axiadc_state *st = iio_priv(indio_dev); + u32 reg; + + switch ((u32)this_attr->address) { + case 0: + reg = axiadc_read(st, ADI_REG_SYNC_STATUS); + + return sprintf(buf, "%s\n", reg & ADI_ADC_SYNC_STATUS ? + axiadc_sync_ctrls[0] : axiadc_sync_ctrls[1]); + case 1: + if (st->ext_sync_avail) + return sprintf(buf, "arm disarm trigger_manual\n"); + else + return sprintf(buf, "arm\n"); + default: + return -EINVAL; + } + + return -EINVAL; +} + +static IIO_DEVICE_ATTR(sync_start_enable, 0644, + axiadc_sync_start_show, + axiadc_sync_start_store, + 0); + +static IIO_DEVICE_ATTR(sync_start_enable_available, 0444, + axiadc_sync_start_show, + NULL, + 1); + +static struct attribute *axiadc_attributes[] = { + &iio_dev_attr_sync_start_enable.dev_attr.attr, + &iio_dev_attr_sync_start_enable_available.dev_attr.attr, + NULL, +}; + +static const struct attribute_group axiadc_attribute_group = { + .attrs = axiadc_attributes, +}; + static const struct iio_info adc_info = { .read_raw = axiadc_read_raw, .write_raw = axiadc_write_raw, .debugfs_reg_access = &adc_reg_access, .update_scan_mode = axiadc_update_scan_mode, + .attrs = &axiadc_attribute_group, }; + static const struct of_device_id adc_of_match[] = { { .compatible = "adi,cn0363-adc-1.00.a", .data = &cn0363_chip_info }, { .compatible = "adi,axi-ad9371-obs-1.0", @@ -703,6 +819,7 @@ static int adc_probe(struct platform_device *pdev) struct axiadc_state *st; struct resource *mem; int ret; + u32 config; id = of_match_node(adc_of_match, pdev->dev.of_node); if (!id) @@ -747,6 +864,9 @@ static int adc_probe(struct platform_device *pdev) axiadc_write(st, ADI_REG_RSTN, 0); axiadc_write(st, ADI_REG_RSTN, ADI_RSTN); + config = axiadc_read(st, ADI_REG_CONFIG); + st->ext_sync_avail = !!(config & ADI_EXT_SYNC); + if (info->has_frontend) { st->frontend = devm_iio_hw_consumer_alloc(&pdev->dev); if (IS_ERR(st->frontend)) diff --git a/drivers/iio/frequency/Kconfig b/drivers/iio/frequency/Kconfig index 3a3d56e027eedd..4331425067c645 100644 --- a/drivers/iio/frequency/Kconfig +++ b/drivers/iio/frequency/Kconfig @@ -227,6 +227,16 @@ config ADF4377 To compile this driver as a module, choose M here: the module will be called adf4377. +config ADF4382 + tristate "Analog Devices ADF4382 Microwave Wideband Synthesizer" + depends on SPI && COMMON_CLK + help + Say yes here to build support for Analog Devices ADF4382 Microwave + Wideband Synthesizer. + + To compile this driver as a module, choose M here: the + module will be called adf4382. + config ADF5355 tristate "Analog Devices ADF5355/ADF4355 Wideband Synthesizers" depends on SPI diff --git a/drivers/iio/frequency/Makefile b/drivers/iio/frequency/Makefile index 19f8db351554e4..82d1181988cec6 100644 --- a/drivers/iio/frequency/Makefile +++ b/drivers/iio/frequency/Makefile @@ -16,6 +16,7 @@ obj-$(CONFIG_ADF4360) += adf4360.o obj-$(CONFIG_ADF4371) += adf4371.o obj-$(CONFIG_ADF4377) += adf4377.o obj-$(CONFIG_ADMFM2000) += admfm2000.o +obj-$(CONFIG_ADF4382) += adf4382.o obj-$(CONFIG_ADMV1013) += admv1013.o obj-$(CONFIG_ADMV1014) += admv1014.o obj-$(CONFIG_ADMV4420) += admv4420.o diff --git a/drivers/iio/frequency/adf4030.c b/drivers/iio/frequency/adf4030.c index a8d46320a5e69e..3d8659142a4794 100644 --- a/drivers/iio/frequency/adf4030.c +++ b/drivers/iio/frequency/adf4030.c @@ -47,13 +47,20 @@ #define ADF4030_AVGEXP_MSK GENMASK(3, 0) #define ADF4030_TDC_ARM_M_MSK BIT(7) +/* REG 0x17 */ +#define ADF4030_NDEL_ADJ_MSK BIT(7) +#define ADF4030_STOP_FSM_MSK BIT(6) +#define ADF4030_ADEL_MSK GENMASK(5, 0) + /* REG 0x35 */ #define ADF4030_ALIGN_THOLD_MSK GENMASK(5, 0) +#define ADF4030_BSYNC_CAL_ON_1_0_MSK GENMASK(7, 6) /* REG 0x37 */ #define ADF4030_EN_ITER_MSK BIT(0) #define ADF4030_EN_CYCS_RED_MSK BIT(1) #define ADF4030_EN_SERIAL_ALIGN_MSK BIT(2) +#define ADF4030_EN_BKGND_ALGN_MSK BIT(3) #define ADF4030_ALIGN_CYCLES_MSK GENMASK(7, 5) /* REG 0x3C */ @@ -99,6 +106,7 @@ #define ADF4030_EN_ADC_MSK BIT(0) #define ADF4030_EN_ADC_CLK_MSK BIT(1) #define ADF4030_EN_ADC_CNV_MSK BIT(2) +#define ADF4030_RST_TDC_ERR_MSK BIT(7) /* REG 0x72 */ #define ADF4030_START_CNV BIT(0) @@ -136,7 +144,7 @@ #define ADI_ADF4030_VCO_FREQ_MIN 2375000000U #define ADI_ADF4030_VCO_FREQ_MAX 2625000000U #define ADI_ADF4030_BSYNC_FREQ_MIN 650000U -#define ADI_ADF4030_BSYNC_FREQ_MAX 250000000U +#define ADI_ADF4030_BSYNC_FREQ_MAX 200000000U #define ADI_ADF4030_R_DIV_MIN 1U #define ADI_ADF4030_R_DIV_MAX 31U #define ADI_ADF4030_N_DIV_MIN 8U @@ -210,6 +218,8 @@ struct adf4030_state { bool adc_enabled; bool spi_3wire_en; bool cmos_3v3_en; + bool bsync_autoalign_en; + u32 bsync_autoalign_mask; u8 vals[3] __aligned(IIO_DMA_MINALIGN); }; @@ -276,7 +286,7 @@ static int adf4030_compute_odiv(u32 vco_freq, u64 bsync_out_freq_uhz, u32 *odiv) if (rem) return -EINVAL; - if (*odiv > ADI_ADF4030_O_DIV_MAX) + if (*odiv < ADI_ADF4030_O_DIV_MIN || *odiv > ADI_ADF4030_O_DIV_MAX) return -EINVAL; return 0; @@ -394,6 +404,17 @@ static int adf4030_tdc_measure(struct adf4030_state *st, u32 channel, if (ret) return ret; + /* Reset TDC error monitor before starting measurement */ + ret = regmap_set_bits(st->regmap, ADF4030_REG(0x61), + ADF4030_RST_TDC_ERR_MSK); + if (ret) + return ret; + + ret = regmap_clear_bits(st->regmap, ADF4030_REG(0x61), + ADF4030_RST_TDC_ERR_MSK); + if (ret) + return ret; + ret = regmap_write(st->regmap, ADF4030_REG(0x10), FIELD_PREP(ADF4030_TDC_TARGET_MSK, channel)); if (ret) @@ -535,7 +556,7 @@ static int adf4030_auto_align_delay(const struct adf4030_state *st, u32 channel, static int adf4030_auto_align_iteration_set(struct adf4030_state *st, u8 iter_number) { - if (iter_number > ADI_ADF4030_ALIGN_CYCLES_MAX_COUNT) + if (iter_number < 1 || iter_number > ADI_ADF4030_ALIGN_CYCLES_MAX_COUNT) return -EINVAL; return regmap_update_bits(st->regmap, ADF4030_REG(0x37), @@ -590,7 +611,7 @@ static int adf4030_auto_align_single_channel(const struct adf4030_state *st, return ret; dev_dbg(&st->spi->dev, "Auto-aligning channel %d to channel %d (try %u)\n", - channel, source_channel, retry - 3); + channel, source_channel, 4 - retry); /* Wait for FSM to complete */ ret = regmap_read_poll_timeout(st->regmap, ADF4030_REG(0x8F), @@ -648,11 +669,81 @@ static int adf4030_core_die_temp_get(struct adf4030_state *st, int *die_temp) if (ret) return ret; - *die_temp = sign_extend32((st->vals[1] << 8) | st->vals[0], 8); + /* Temperature is sign-magnitude: 0x92 = magnitude, 0x93 bit 0 = sign */ + *die_temp = st->vals[0]; + if (st->vals[1] & BIT(0)) + *die_temp = -*die_temp; return 0; } +static int adf4030_set_background_serial_alignment(struct adf4030_state *st, bool enable, u32 channel_flags) +{ + u32 tmp; + int ret; + + if (!channel_flags) { + dev_err(&st->spi->dev, "No channels selected for background alignment\n"); + return -EINVAL; + } + + + ret = regmap_read(st->regmap, ADF4030_REG(0x37), &tmp); + if (ret) + return ret; + + /* If enabled : Disable Background alignment */ + if (tmp & ADF4030_EN_BKGND_ALGN_MSK) { + ret = regmap_update_bits(st->regmap, ADF4030_REG(0x17), ADF4030_STOP_FSM_MSK, 0xFF); + if (ret) + return ret; + + ret = regmap_update_bits(st->regmap, ADF4030_REG(0x37), ADF4030_EN_BKGND_ALGN_MSK, 0x0); + if (ret) + return ret; + + st->bsync_autoalign_en = false; + + ret = regmap_update_bits(st->regmap, ADF4030_REG(0x17), ADF4030_STOP_FSM_MSK, 0x0); + if (ret) + return ret; + + } + + if (!enable) + return 0; + + ret = adf4030_core_die_temp_get(st, &tmp); /* Enable ADC, ignore temp */ + if (ret) + return ret; + + ret = regmap_update_bits(st->regmap, ADF4030_REG(0x11), + ADF4030_MANUAL_MODE_MSK | ADF4030_EN_ALIGN_MSK, + FIELD_PREP(ADF4030_MANUAL_MODE_MSK, 0) | + FIELD_PREP(ADF4030_EN_ALIGN_MSK, 1)); + if (ret) + return ret; + + ret = regmap_update_bits(st->regmap, ADF4030_REG(0x35), ADF4030_BSYNC_CAL_ON_1_0_MSK, + FIELD_PREP(ADF4030_BSYNC_CAL_ON_1_0_MSK, channel_flags & 0x3)); + if (ret) + return ret; + + /* Write ADF4030_BSYNC_CAL_ON_9_2 */ + ret = regmap_write(st->regmap, ADF4030_REG(0x36), (channel_flags >> 2)); + if (ret) + return ret; + + ret = regmap_update_bits(st->regmap, ADF4030_REG(0x37), + ADF4030_EN_SERIAL_ALIGN_MSK | ADF4030_EN_BKGND_ALGN_MSK, 0xFF); + if (ret) + return ret; + + st->bsync_autoalign_en = true; + + return regmap_write(st->regmap, ADF4030_REG(0x10), 0xFF); +} + enum { BSYNC_OUT_EN, BSYNC_REF_CHAN, @@ -661,6 +752,7 @@ enum { BSYNC_ALIGN_THRESH_EN, BSYNC_ALIGN_ITER, BSYNC_DUTY_CYCLE, + BSYNC_ALIGN_BG_EN, }; static ssize_t adf4030_ext_info_read(struct iio_dev *indio_dev, @@ -694,6 +786,8 @@ static ssize_t adf4030_ext_info_read(struct iio_dev *indio_dev, rem = do_div(tdc_result, MICRO); return sysfs_emit(buf, "%u.%06u\n", (u32)tdc_result, rem); + case BSYNC_ALIGN_BG_EN: + return sysfs_emit(buf, "%u\n", st->bsync_autoalign_en); default: return -EOPNOTSUPP; } @@ -758,6 +852,15 @@ static ssize_t adf4030_ext_info_write(struct iio_dev *indio_dev, st->bsync_autoalign_iter = readin; return len; + case BSYNC_ALIGN_BG_EN: + if (readin < 0 || readin > 1) + return -EINVAL; + ret = adf4030_set_background_serial_alignment(st, readin, st->bsync_autoalign_mask); + if (ret) + return ret; + + st->bsync_autoalign_ref_chan = readin; + return len; default: return -EOPNOTSUPP; } @@ -806,6 +909,13 @@ static struct iio_chan_spec_ext_info adf4030_ext_info[] = { .shared = IIO_SEPARATE, .private = BSYNC_DUTY_CYCLE, }, + { + .name = "background_serial_alignment_en", + .read = adf4030_ext_info_read, + .write = adf4030_ext_info_write, + .shared = IIO_SHARED_BY_TYPE, + .private = BSYNC_ALIGN_BG_EN, + }, {}, }; @@ -898,9 +1008,9 @@ static int adf4030_reg_access(struct iio_dev *indio_dev, unsigned int reg, return regmap_write(st->regmap, reg, writeval); } -static const int adf4030_avg_range[] = {64, 128, 256, 512, 1024, 2048, 4096, - 8192, 16384, 32768, 65536, 131072, - 262144, 524288, 1048576, 2097152}; +static const int adf4030_avg_range[] = {512, 1024, 2048, 4096, 8192, 16384, + 32768, 65536, 131072, 262144, 524288, + 1048576, 2097152}; static int adf4030_read_avail(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, @@ -1511,7 +1621,7 @@ static int adf4030_probe(struct spi_device *spi) { struct iio_dev *indio_dev; struct adf4030_state *st; - int ret; + int ret, i; indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); if (!indio_dev) @@ -1543,6 +1653,10 @@ static int adf4030_probe(struct spi_device *spi) if (st->refin) st->ref_freq = clk_get_rate(st->refin); + for (i = 0; i < st->num_channels; i++) + if (st->channels[i].align_on_sync_en) + st->bsync_autoalign_mask |= BIT(st->channels[i].num); + indio_dev->name = "adf4030"; indio_dev->info = &adf4030_iio_info; indio_dev->modes = INDIO_DIRECT_MODE; diff --git a/drivers/iio/frequency/adf4350.c b/drivers/iio/frequency/adf4350.c index 04bf1504e080a9..39062822176f2e 100644 --- a/drivers/iio/frequency/adf4350.c +++ b/drivers/iio/frequency/adf4350.c @@ -221,7 +221,13 @@ static int adf4350_set_freq(struct adf4350_state *st, unsigned long long freq) st->regs[ADF4350_REG2] &= ~ADF4350_REG2_10BIT_R_CNT(0x3FF); st->regs[ADF4350_REG2] |= ADF4350_REG2_10BIT_R_CNT(r_cnt); - + if (st->r0_fract) { + st->regs[ADF4350_REG2] &= ~ADF4350_REG2_LDF_INT_N; + st->regs[ADF4350_REG3] &= ~ADF4351_REG3_ANTI_BACKLASH_3ns_EN; + } else { + st->regs[ADF4350_REG2] |= ADF4350_REG2_LDF_INT_N; + st->regs[ADF4350_REG3] |= ADF4351_REG3_ANTI_BACKLASH_3ns_EN; + } st->regs[ADF4350_REG4] &= ~(ADF4350_REG4_RF_DIV_SEL(0x7) | ADF4350_REG4_8BIT_BAND_SEL_CLKDIV(0xFF)); st->regs[ADF4350_REG4] |= ADF4350_REG4_RF_DIV_SEL(st->r4_rf_div_sel) | @@ -424,12 +430,20 @@ static int adf4350_clk_is_enabled(struct clk_hw *hw) return (st->regs[ADF4350_REG2] & ADF4350_REG2_POWER_DOWN_EN); } +static long adf4350_clk_round_rate(struct clk_hw *hw, + unsigned long rate, + unsigned long *parent_rate) +{ + return rate; +} + static const struct clk_ops adf4350_clk_ops = { .recalc_rate = adf4350_clk_recalc_rate, .set_rate = adf4350_clk_set_rate, .prepare = adf4350_clk_prepare, .unprepare = adf4350_clk_unprepare, .is_enabled = adf4350_clk_is_enabled, + .round_rate = adf4350_clk_round_rate, }; static int adf4350_clk_register(struct adf4350_state *st) diff --git a/drivers/iio/frequency/adf4382.c b/drivers/iio/frequency/adf4382.c new file mode 100644 index 00000000000000..01d25aa67d54f7 --- /dev/null +++ b/drivers/iio/frequency/adf4382.c @@ -0,0 +1,2225 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * ADF4382 Microwave Wideband Synthesizer with Integrated VCO + * + * Copyright 2022-2024 Analog Devices Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* ADF4382 REG0000 Map */ +#define ADF4382_SOFT_RESET_R_MSK BIT(7) +#define ADF4382_LSB_FIRST_R_MSK BIT(6) +#define ADF4382_ADDRESS_ASC_R_MSK BIT(5) +#define ADF4382_SDO_ACTIVE_R_MSK BIT(4) +#define ADF4382_SDO_ACTIVE_MSK BIT(3) +#define ADF4382_ADDRESS_ASC_MSK BIT(2) +#define ADF4382_LSB_FIRST_MSK BIT(1) +#define ADF4382_SOFT_RESET_MSK BIT(0) + +/* ADF4382_REG0 */ +#define ADF4382_ADDR_ASC_MSK BIT(2) +#define ADF4382_ADDR_ASC_R_MSK BIT(5) +#define ADF4382_SDO_ACT_MSK BIT(3) +#define ADF4382_SDO_ACT_R_MSK BIT(4) +#define ADF4382_RESET_CMD 0x81 + +/* ADF4382 REG0000 Bit Definition */ +#define ADF4382_SDO_ACTIVE_SPI_3W 0x0 +#define ADF4382_SDO_ACTIVE_SPI_4W 0x1 + +#define ADF4382_ADDR_ASC_AUTO_DECR 0x0 +#define ADF4382_ADDR_ASC_AUTO_INCR 0x1 + +#define ADF4382_LSB_FIRST_MSB 0x0 +#define ADF4382_LSB_FIRST_LSB 0x1 + +#define ADF4382_SOFT_RESET_N_OP 0x0 +#define ADF4382_SOFT_RESET_EN 0x1 + +/* ADF4382 REG0001 Map */ +#define ADF4382_SINGLE_INSTR_MSK BIT(7) +#define ADF4382_MASTER_RB_CTRL_MSK BIT(5) + +/* ADF4382 REG0001 Bit Definition */ +#define ADF4382_SPI_STREAM_EN 0x0 +#define ADF4382_SPI_STREAM_DIS 0x1 + +#define ADF4382_RB_SLAVE_REG 0x0 +#define ADF4382_RB_MASTER_REG 0x1 + +/* ADF4382 REG0003 Bit Definition */ +#define ADF4382_CHIP_TYPE 0x06 + +/* ADF4382 REG0004 Bit Definition */ +#define ADF4382_PRODUCT_ID_LSB 0x0005 + +/* ADF4382 REG0005 Bit Definition */ +#define ADF4382_PRODUCT_ID_MSB 0x0005 + +/* ADF4382 REG000A Map */ +#define ADF4382_SCRATCHPAD_MSK GENMASK(7, 0) + +/* ADF4382 REG000C Bit Definition */ +#define ADF4382_VENDOR_ID_LSB 0x56 + +/* ADF4382 REG000D Bit Definition */ +#define ADF4382_VENDOR_ID_MSB 0x04 + +/* ADF4382 REG000F Bit Definition */ +#define ADF4382_M_S_TRANSF_BIT_MSK BIT(0) + +/* ADF4382 REG0010 Map*/ +#define ADF4382_N_INT_LSB_MSK GENMASK(7, 0) + +/* ADF4382 REG0011 Map*/ +#define ADF4382_CLKOUT_DIV_MSK GENMASK(7, 5) +#define ADF4382_INV_CLK_OUT_MSK BIT(4) +#define ADF4382_N_INT_MSB_MSK GENMASK(3, 0) + +/* ADF4382 REG0015 Map */ +#define ADF4382_M_VCO_BAND_LSB_MSK BIT(7) +#define ADF4382_M_VCO_CORE_MSK BIT(6) +#define ADF4382_BIAS_DEC_MODE_MSK GENMASK(5, 3) +#define ADF4382_INT_MODE_MSK BIT(2) +#define ADF4382_PFD_POL_MSK BIT(1) +#define ADF4382_FRAC1WORD_MSB BIT(0) + +/* ADF4382 REG0016 Map */ +#define ADF4382_M_VCO_BAND_MSB_MSK GENMASK(7, 0) + +/* ADF4382 REG001D Map */ +#define ADF4382_BLEED_I_LSB_MSK GENMASK(7, 0) + +/* ADF4382 REG001E Map */ +#define ADF4382_EN_PHASE_RESYNC_MSK BIT(7) +#define ADF4382_EN_REF_RST_MSK BIT(6) +#define ADF4382_TIMED_SYNC_MSK BIT(5) +#define ADF4382_BLEED_I_MSB_MSK GENMASK(4, 0) + +/* ADF4382 REG001F Map */ +#define ADF4382_SW_SYNC_MSK BIT(7) +#define ADF4382_SPARE_1F_MSK BIT(6) +#define ADF4382_BLEED_POL_MSK BIT(5) +#define ADF4382_EN_BLEED_MSK BIT(4) +#define ADF4382_CP_I_MSK GENMASK(3, 0) + +/* ADF4382 REG0020 Map */ +#define ADF4382_EN_AUTOCAL_MSK BIT(7) +#define ADF4382_EN_RDBLR_MSK BIT(6) +#define ADF4382_R_DIV_MSK GENMASK(5, 0) + +/* ADF4382 REG0021 Map */ +#define ADF4382_PHASE_WORD_LSB_MSK GENMASK(7, 0) + +/* ADF4382 REG0022 Map */ +#define ADF4382_PHASE_WORD_MID_MSK GENMASK(7, 0) + +/* ADF4382 REG0023 Map */ +#define ADF4382_PHASE_WORD_MSB_MSK GENMASK(7, 0) + +/* ADF4382 REG0024 Map */ +#define ADF4382_SPARE_24_MSK GENMASK(7, 5) +#define ADF4382_DCLK_DIV_SEL_MSK BIT(4) +#define ADF4382_DNCLK_DIV1_MSK GENMASK(3, 2) +#define ADF4382_DCLK_DIV1_MSK GENMASK(1, 0) + +/* ADF4382 REG0025 Map */ +#define ADF4382_RESYNC_WAIT_LSB_MSK GENMASK(7, 0) + +/* ADF4382 REG0026 Map */ +#define ADF4382_RESYNC_WAIT_MSB_MSK GENMASK(7, 0) + +/* ADF4382 REG0027 Map */ +#define ADF4382_CAL_BLEED_FINE_MIN_MSK GENMASK(7, 4) +#define ADF4382_BLEED_ADJ_SCALE_MSK GENMASK(3, 0) + +/* ADF4382 REG0028 Map */ +#define ADF4382_PH_RESYNC_RB_SEL_MSK BIT(7) +#define ADF4382_LSB_P1_MSK BIT(6) +#define ADF4382_VAR_MOD_EN_MSK BIT(5) +#define ADF4382_DITHER1_SCALE_MSK GENMASK(4, 2) +#define ADF4382_EN_DITHER2_MSK BIT(1) +#define ADF4382_EN_DITHER1_MSK BIT(0) + +/* ADF4382 REG0029 Map */ +#define ADF4382_CLK2_OPWR_MSK GENMASK(7, 4) +#define ADF4382_CLK1_OPWR_MSK GENMASK(3, 0) + +/* ADF4382 REG002A Map */ +#define ADF4382_FN_DBL_MSK BIT(7) +#define ADF4382_PD_NDIV_TL_MSK BIT(6) +#define ADF4382_CLKOUT_BST_MSK BIT(5) +#define ADF4382_PD_SYNC_MSK BIT(4) +#define ADF4382_PD_CLK_MSK BIT(3) +#define ADF4382_PD_RDET_MSK BIT(2) +#define ADF4382_PD_ADC_MSK BIT(1) +#define ADF4382_PD_CALGEN_MSK BIT(0) + +/* ADF4382 REG002B Map */ +#define ADF4382_PD_ALL_MSK BIT(7) +#define ADF4382_PD_RDIV_TL_MSK BIT(6) +#define ADF4382_PD_NDIV_MSK BIT(5) +#define ADF4382_PD_VCO_MSK BIT(4) +#define ADF4382_PD_LD_MSK BIT(3) +#define ADF4382_PD_PFDCP_MSK BIT(2) +#define ADF4382_PD_CLKOUT1_MSK BIT(1) +#define ADF4382_PD_CLKOUT2_MSK BIT(0) + +/* ADF4382 REG002C Map */ +#define ADF4382_LDWIN_PW_MSK GENMASK(7, 5) +#define ADF4382_LD_COUNT_OPWR_MSK GENMASK(4, 0) + +/* ADF4382 REG002D Map */ +#define ADF4382_EN_DNCLK_MSK BIT(7) +#define ADF4382_EN_DRCLK_MSK BIT(6) +#define ADF4382_EN_LOL_MSK BIT(5) +#define ADF4382_EN_LDWIN_MSK BIT(4) +#define ADF4382_PDET_POL_MSK BIT(3) +#define ADF4382_RST_LD_MSK BIT(2) +#define ADF4382_LD_O_CTRL_MSK GENMASK(1, 0) + +/* ADF4382 REG002E Map */ +#define ADF4382_MUXOUT_MSK GENMASK(7, 4) +#define ADF4382_ABPW_WD_MSK BIT(3) +#define ADF4382_EN_CPTEST_MSK BIT(2) +#define ADF4382_CP_DOWN_MSK BIT(1) +#define ADF4382_CP_UP_MSK BIT(0) + +/* ADF4382 REG002F Map*/ +#define ADF4382_BST_REF_MSK BIT(7) +#define ADF4382_FILT_REF_MSK BIT(6) +#define ADF4382_RDBLR_DC_MSK GENMASK(5, 0) + +/* ADF4382 REG0030 Map */ +#define ADF4382_MUTE_NCLK_MSK BIT(7) +#define ADF4382_MUTE_RCLK_MSK BIT(6) +#define ADF4382_REF_SEL_MSK BIT(5) +#define ADF4382_INV_RDBLR_MSK BIT(4) +#define ADF4382_RDBLR_DEL_SEL_MSK GENMASK(3, 0) + +/* ADF4382 REG0031 Map */ +#define ADF4382_SYNC_DEL_MSK GENMASK(7, 5) +#define ADF4382_RST_SYS_MSK BIT(4) +#define ADF4382_EN_ADC_CLK_MSK BIT(3) +#define ADF4382_EN_VCAL_MSK BIT(2) +#define ADF4382_CAL_CT_SEL_MSK BIT(1) +#define ADF4382_DCLK_MODE_MSK BIT(0) + +/* ADF4382 REG0032 Map */ +#define ADF4382_SPARE_32_MSK BIT(7) +#define ADF4382_BLEED_ADJ_CAL_MSK BIT(6) +#define ADF4382_DEL_MODE_MSK BIT(5) +#define ADF4382_EN_AUTO_ALIGN_MSK BIT(4) +#define ADF4382_PHASE_ADJ_POL_MSK BIT(3) +#define ADF4382_EFM3_MODE_MSK GENMASK(2, 0) + +/* ADF4382 REG0033 Map */ +#define ADF4382_PHASE_ADJUST_MSK GENMASK(7, 0) + +/* ADF4382 REG0034 Map */ +#define ADF4382_PHASE_ADJ_MSK BIT(7) +#define ADF4382_DRCLK_DEL_MSK GENMASK(6, 4) +#define ADF4382_DNCLK_DEL_MSK GENMASK(3, 1) +#define ADF4382_RST_CNTR_MSK BIT(0) + +/* ADF4382 REG0035 Map */ +#define ADF4382_SPARE_35_MSK GENMASK(7, 6) +#define ADF4382_M_VCO_BIAS_MSK GENMASK(5, 0) + +/* ADF4382 REG0036 Map */ +#define ADF4382_CLKODIV_DB_MSK BIT(7) +#define ADF4382_DCLK_DIV_DB_MSK BIT(6) +#define ADF4382_SPARE_36_MSK GENMASK(5, 2) +#define ADF4382_EN_LUT_GEN_MSK BIT(1) +#define ADF4382_EN_LUT_CAL_MSK BIT(0) + +/* ADF4382 REG0037 Map */ +#define ADF4382_CAL_COUNT_TO_MSK GENMASK(7, 0) + +/* ADF4382 REG0038 Map */ +#define ADF4382_CAL_VTUNE_TO_LSB_MSK GENMASK(7, 0) + +/* ADF4382 REG0039 Map */ +#define ADF4382_O_VCO_DB_MSK BIT(7) +#define ADF4382_CAL_VTUNE_TO_MSB_MSK GENMASK(6, 0) + +/* ADF4382 REG003A Map */ +#define ADF4382_CAL_VCO_TO_LSB_MSK GENMASK(7, 0) + +/* ADF4382 REG003B Map */ +#define ADF4382_DEL_CTRL_DB_MSK BIT(7) +#define ADF4382_CAL_VCO_TO_MSB_MSK GENMASK(6, 0) + +/* ADF4382 REG003C Map */ +#define ADF4382_CNTR_DIV_WORD_MSK GENMASK(7, 0) + +/* ADF4382 REG003D Map */ +#define ADF4382_SPARE_3D_MSK BIT(7) +#define ADF4382_SYNC_SP_DB_MSK BIT(6) +#define ADF4382_CMOS_OV_MSK BIT(5) +#define ADF4382_READ_MODE_MSK BIT(4) +#define ADF4382_CNTR_DIV_WORD_MSB_MSK GENMASK(3, 0) + +/* ADF4382 REG003E Map */ +#define ADF4382_ADC_CLK_DIV_MSK GENMASK(7, 0) + +/* ADF4382 REG003F Map */ +#define ADF4382_EN_ADC_CNV_MSK BIT(7) +#define ADF4382_EN_ADC_VTEST_MSK BIT(6) +#define ADF4382_ADC_VTEST_SEL_MSK BIT(5) +#define ADF4382_ADC_MUX_SEL_MSK BIT(4) +#define ADF4382_ADC_F_CONV_MSK BIT(3) +#define ADF4382_ADC_C_CONV_MSK BIT(2) +#define ADF4382_EN_ADC_MSK BIT(1) +#define ADF4382_SPARE_3F_MSK BIT(0) + +/* ADF4382 REG0040 Map */ +#define ADF4382_EXT_DIV_DEC_SEL_MSK BIT(7) +#define ADF4382_ADC_CLK_TEST_SEL_MSK BIT(6) +#define ADF4382_MUTE_CLKOUT2_MSK GENMASK(5, 3) +#define ADF4382_MUTE_CLKOUT1_MSK GENMASK(2, 0) + +/* ADF4382 REG0041 Map */ +#define ADF4382_EXT_DIV_MSK GENMASK(7, 5) +#define ADF4382_EN_VCO_CAP_TEST_MSK BIT(4) +#define ADF4382_EN_CALGEN_CAP_TEST_MSK BIT(3) +#define ADF4382_EN_CP_CAP_TEST_MSK BIT(2) +#define ADF4382_CAP_TEST_STATE_MSK BIT(1) +#define ADF4382_TRANS_LOOP_SEL_MSK BIT(0) + +/* ADF4382 REG0042 Map */ +#define ADF4382_NDIV_PWRUP_TIMEOUT_MSK GENMASK(7, 0) + +/* ADF4382 REG0043 Map */ +#define ADF4382_CAL_BLEED_FINE_MAX_MSK GENMASK(7, 0) + +/* ADF4382 REG0044 Map */ +#define ADF4382_VCAL_ZERO_MSK BIT(7) +#define ADF4382_VPTAT_CALGEN_MSK GENMASK(6, 0) + +/* ADF4382 REG0045 Map */ +#define ADF4382_SPARE_45_MSK BIT(7) +#define ADF4382_VCTAT_CALGEN_MSK GENMASK(6, 0) + +/* ADF4382 REG0046 Map */ +#define ADF4382_NVMDIN_MSK GENMASK(7, 0) + +/* ADF4382 REG0047 Map */ +#define ADF4382_SPARE_47_MSK BIT(7) +#define ADF4382_NVMADDR_MSK GENMASK(6, 3) +#define ADF4382_NVMBIT_SEL GENMASK(2, 0) + +/* ADF4382 REG0048 Map */ +#define ADF4382_TRIM_LATCH_MSK BIT(7) +#define ADF4382_NVMTEST_MSK BIT(6) +#define ADF4382_NVMPROG_MSK BIT(5) +#define ADF4382_NVMRD_MSK BIT(4) +#define ADF4382_NVMSTART_MSK BIT(3) +#define ADF4382_NVMON_MSK BIT(2) +#define ADF4382_MARGIN_MSK GENMASK(1, 0) + +/* ADF4382 REG0049 Map */ +#define ADF4382_NVMDOUT_MSK GENMASK(7, 0) + +/* ADF4382 REG004A Map */ +#define ADF4382_SCAN_MODE_CODE_MSK GENMASK(7, 0) + +/* ADF4382 REG004B Map */ +#define ADF4382_TEMP_OFFSET_MSK GENMASK(7, 0) + +/* ADF4382 REG004C Map */ +#define ADF4382_SPARE_4C_MSK GENMASK(7, 6) +#define ADF4382_TEMP_SLOPE_MSK GENMASK(5, 0) + +/* ADF4382 REG004D Map */ +#define ADF4382_VCO_FSM_TEST_MUX_MSK GENMASK(7, 5) +#define ADF4382_SPARE_4D_MSK GENMASK(4, 3) +#define ADF4382_O_VCO_BIAS_MSK BIT(2) +#define ADF4382_O_VCO_BAND_MSK BIT(1) +#define ADF4382_O_VCO_CORE_MSK BIT(0) + +/* ADF4382 REG004E Map */ +#define ADF4382_EN_TWO_PASS_CALL_MSK BIT(4) +#define ADF4382_TWO_PASS_BAND_START_MSK GENMASK(3, 0) + +/* ADF4382 REG004F Map */ +#define ADF4382_LUT_SCALE_MSK GENMASK(7, 0) + +/* ADF4382 REG0050 Map */ +#define ADF4382_SPARE0_MSK GENMASK(7, 0) + +/* ADF4382 REG0051 Map */ +#define ADF4382_SPARE1_MSK GENMASK(7, 0) + +/* ADF4382 REG0052 Map */ +#define ADF4382_SYNC_REF_SPARE_MSK GENMASK(7, 4) +#define ADF4382_SYNC_MON_DEL_MSK GENMASK(3, 0) + +/* ADF4382 REG0053 Map */ +#define ADF4382_PD_SYNC_MON_MSK BIT(6) +#define ADF4382_SYNC_SEL_MSK BIT(5) +#define ADF4382_RST_SYNC_MON_MSK BIT(4) +#define ADF4382_SYNC_SH_DEL_MSK GENMASK(3, 0) + +/* ADF4382 REG0054 Map */ +#define ADF4382_ADC_ST_CNV_MSK BIT(0) + +/* ADF4382 REG0058 Map */ +#define ADF4382_PLL_LOCK_MSK BIT(0) + +#define ADF4382_MOD2WORD_LSB_MSK GENMASK(7, 0) +#define ADF4382_MOD2WORD_MID_MSK GENMASK(15, 8) +#define ADF4382_MOD2WORD_MSB_MSK GENMASK(23, 16) + +#define ADF4382_FRAC1WORD_LSB_MSK GENMASK(7, 0) +#define ADF4382_FRAC1WORD_MID_MSK GENMASK(15, 8) +#define ADF4382_FRAC1WORD_MSB_MSK GENMASK(23, 16) +#define ADF4382_FRAC1WORD_MS_BIT_MSK BIT(24) + +#define ADF4382_FRAC2WORD_LSB_MSK GENMASK(7, 0) +#define ADF4382_FRAC2WORD_MID_MSK GENMASK(15, 8) +#define ADF4382_FRAC2WORD_MSB_MSK GENMASK(23, 16) + +#define ADF4382_DEL_CNT_LSB_MSK GENMASK(7, 0) +#define ADF4382_DEL_CNT_MSB_MSK GENMASK(15, 8) + +#define ADF4382_DEL_CNT_FINE_MSK GENMASK(8, 0) +#define ADF4382_DEL_CNT_COARSE_MSK GENMASK(12, 9) +#define ADF4382_DEL_CNT_BLEED_POL_MSK BIT(15) + +/* ADF4382 REG0058 Map */ +#define ADF4382_ADC_BUSY BIT(2) + +#define ADF4382_REF_MIN 10000000ULL // 10MHz +#define ADF4382_REF_MAX 4500000000ULL // 4.5GHz +#define ADF4382_VCO_FREQ_MIN 11000000000ULL // 11GHz +#define ADF4382_VCO_FREQ_MAX 22000000000ULL // 22GHz +#define ADF4382A_VCO_FREQ_MIN 11500000000ULL // 11.5GHz +#define ADF4382A_VCO_FREQ_MAX 21000000000ULL // 21GHz +#define ADF4382_PFD_FREQ_MAX 625000000ULL // 625MHz +#define ADF4382_PFD_FREQ_FRAC_MAX 250000000ULL // 250MHz +#define ADF4382_PFD_FREQ_MIN 5400000ULL // 5.4MHz +#define ADF4382_MOD1WORD 0x2000000ULL // 2^25 +#define ADF4382_MOD2WORD_MAX 0xFFFFFFU // 2^24 - 1 +#define ADF4382_PHASE_RESYNC_MOD2WORD_MAX 0x1FFFFU // 2^17 - 1 +#define ADF4382_CHANNEL_SPACING_MAX 78125U +#define ADF4382_DCLK_DIV1_0_MAX 160000000ULL // 160MHz +#define ADF4382_DCLK_DIV1_1_MAX 320000000ULL // 320MHz +#define ADF4382_OUT_PWR_MAX 15 +#define ADF4382_CLKOUT_DIV_REG_VAL_MAX 4 +#define ADF4382A_CLKOUT_DIV_REG_VAL_MAX 2 + +#define ADF4382_CP_I_DEFAULT 15 +#define ADF4382_OPOWER_DEFAULT 11 +#define ADF4382_REF_DIV_DEFAULT 1 +#define ADF4382_RFOUT_DEFAULT 2875000000ULL // 2.875GHz +#define ADF4382_SCRATCHPAD_VAL 0xA5 + +#define ADF4382_PHASE_BLEED_CNST_MUL 511 +#define ADF4382_PHASE_BLEED_CNST_DIV 250 +#define ADF4382_VCO_CAL_CNT 202 +#define ADF4382_VCO_CAL_VTUNE 124 +#define ADF4382_VCO_CAL_ALC 250 + +#define FS_PER_NS MICRO +#define NS_PER_MS MICRO +#define MS_PER_NS MICRO +#define NS_PER_FS MICRO +#define PS_PER_NS 1000 +#define UA_PER_A 1000000 + +#define PERIOD_IN_DEG 360 +#define PERIOD_IN_DEG_MS 360000 + +#define ADF4382_CHIP_VER_U2 4 +#define ADF4382_CHIP_VER_U4 7 +#define ADF4382_CHIP_VER_U5_A 11 +#define ADF4382_CHIP_VER_U5_B 12 +#define ADF4382_CHIP_VER_U5_C 13 +#define ADF4382_CHIP_VER_U5_D 18 + +// #ifdef CONFIG_64BIT +// #define ADF4382_CLK_SCALE 1 +// #else +#define ADF4382_CLK_SCALE 10ULL +// #endif + +enum { + ADF4382_FREQ, + ADF4382_EN_AUTO_ALIGN, + ADF4382_BLEED_POL, + ADF4382_COARSE_CURRENT, + ADF4382_FINE_CURRENT, +}; + +enum { + ADF4382, + ADF4382A, +}; + +struct adf4382_state { + struct spi_device *spi; + struct regmap *regmap; + struct clk *clkin; + struct clk *clkout; + struct clk_hw clk_hw; + /* Protect against concurrent accesses to the device and data content */ + struct mutex lock; + struct notifier_block nb; + unsigned int ref_freq_hz; + u8 cp_i; + u8 opwr_a; + u64 freq; + bool spi_3wire_en; + bool ref_doubler_en; + bool auto_align_en; + u8 ref_div; + u8 clkout_div_reg_val_max; + u16 bleed_word; + int phase; + bool cmos_3v3; + u64 vco_max; + u64 vco_min; +}; + +#define to_adf4382_state(_hw) container_of(_hw, struct adf4382_state, clk_hw) + +/* Charge pump current values expressed in uA */ +static const int adf4382_ci_ua[] = { + 790, 990, 1190, 1380, 1590, 1980, 2390, 2790, 3180, 3970, 4770, 5570, + 6330, 7910, 9510, 11100 +}; + +static const struct reg_sequence adf4382_u2_reg_default[] = { + {0x000A, 0x0A}, + {0x0200, 0x00}, + {0x0201, 0x00}, + {0x0202, 0x00}, + {0x0203, 0x00}, + {0x0054, 0x00}, + {0x0053, 0x45}, + {0x0052, 0x00}, + {0x0051, 0x00}, + {0x0050, 0x00}, + {0x004F, 0x08}, + {0x004E, 0x06}, + {0x004D, 0x04}, + {0x004C, 0x2B}, + {0x004B, 0x5D}, + {0x004A, 0x00}, + {0x0048, 0x00}, + {0x0047, 0x00}, + {0x0046, 0x00}, + {0x0045, 0x06}, + {0x0044, 0x1B}, + {0x0043, 0xB8}, + {0x0042, 0x01}, + {0x0041, 0x00}, + {0x0040, 0x00}, + {0x003F, 0x82}, + {0x003E, 0x27}, + {0x003C, 0x00}, + {0x003B, 0x00}, + {0x003A, 0xFA}, + {0x0039, 0x00}, + {0x0038, 0x7C}, + {0x0037, 0xCA}, + {0x0036, 0xC0}, + {0x0035, 0x3F}, + {0x0034, 0x36}, + {0x0033, 0x00}, + {0x0032, 0x40}, + {0x0031, 0x63}, + {0x0030, 0x0F}, + {0x002F, 0x3F}, + {0x002E, 0x00}, + {0x002D, 0xF1}, + {0x002C, 0x0C}, + {0x002B, 0x01}, + {0x002A, 0x30}, + {0x0029, 0x09}, + {0x0028, 0x00}, + {0x0027, 0xF0}, + {0x0026, 0x00}, + {0x0025, 0x01}, + {0x0024, 0x01}, + {0x0023, 0x00}, + {0x0022, 0x00}, + {0x0021, 0x00}, + {0x001E, 0x20}, + {0x001D, 0x00}, + {0x001C, 0x00}, + {0x001B, 0x00}, + {0x001A, 0x00}, + {0x0019, 0x00}, + {0x0018, 0x00}, + {0x0017, 0x00}, + {0x0016, 0x00}, + {0x0015, 0x06}, + {0x0014, 0x00}, + {0x0013, 0x00}, + {0x0012, 0x00}, + {0x0011, 0x00}, + {0x0010, 0x50} +}; + +static const struct reg_sequence adf4382_u4_reg_default[] = { + {0x000A, 0xA5}, + {0x0200, 0x00}, + {0x0201, 0x00}, + {0x0202, 0x00}, + {0x0203, 0x00}, + {0x0100, 0x25}, + {0x0101, 0x3F}, + {0x0102, 0x3F}, + {0x0103, 0x3F}, + {0x0104, 0x3F}, + {0x0105, 0x3F}, + {0x0106, 0x3F}, + {0x0107, 0x3F}, + {0x0108, 0x3F}, + // {0x0109, 0x25}, // workaournd for AD9084-EVAL + {0x010A, 0x25}, + {0x010B, 0x3F}, + {0x010C, 0x3F}, + {0x010D, 0x3F}, + {0x010E, 0x3F}, + {0x010F, 0x3F}, + {0x0110, 0x3F}, + {0x0111, 0x3F}, + {0x0054, 0x00}, + {0x0053, 0x45}, + {0x0052, 0x00}, + {0x0051, 0x00}, + {0x0050, 0x00}, + {0x004F, 0x08}, + {0x004E, 0x06}, + {0x004D, 0x04}, // workaournd for AD9084-EVAL + {0x004C, 0x2B}, + {0x004B, 0x5D}, + {0x004A, 0x00}, + {0x0048, 0x00}, + {0x0047, 0x00}, + {0x0046, 0x00}, + {0x0045, 0x62}, + {0x0044, 0x3F}, + {0x0043, 0xB8}, + {0x0042, 0x01}, + {0x0041, 0x00}, + {0x0040, 0x00}, + {0x003F, 0x82}, + {0x003E, 0x4E}, + {0x003C, 0x00}, + {0x003B, 0x00}, + {0x003A, 0xFA}, + {0x0039, 0x00}, + {0x0038, 0x71}, + {0x0037, 0x82}, + {0x0036, 0xC0}, + {0x0035, 0x25}, // workaournd for AD9084-EVAL + {0x0034, 0x36}, + {0x0033, 0x00}, + {0x0032, 0x40}, + {0x0031, 0x6B}, + {0x0030, 0x0F}, + {0x002F, 0x3F}, + {0x002E, 0x00}, + {0x002D, 0xF1}, + {0x002C, 0x0E}, + {0x002B, 0x01}, + {0x002A, 0x30}, + {0x0029, 0x09}, + {0x0028, 0x00}, + {0x0027, 0xF0}, + {0x0026, 0x00}, + {0x0025, 0x01}, + {0x0024, 0x01}, + {0x0023, 0x00}, + {0x0022, 0x00}, + {0x0021, 0x00}, + {0x001E, 0x20}, + {0x001D, 0x00}, + {0x001C, 0x00}, + {0x001B, 0x00}, + {0x001A, 0x00}, + {0x0019, 0x00}, + {0x0018, 0x00}, + {0x0017, 0x00}, + {0x0016, 0x00}, + {0x0015, 0x06}, + {0x0014, 0x00}, + {0x0013, 0x00}, + {0x0012, 0x00}, + {0x0011, 0x00}, + {0x0010, 0x50}, +}; + +static const struct reg_sequence adf4382_u5_reg_default[] = { + { 0x00A, 0xA5 }, + { 0x200, 0x00 }, + { 0x201, 0x00 }, + { 0x202, 0x00 }, + { 0x203, 0x00 }, + { 0x100, 0x25 }, + { 0x101, 0x3F }, + { 0x102, 0x3F }, + { 0x103, 0x3F }, + { 0x104, 0x3F }, + { 0x105, 0x3F }, + { 0x106, 0x3F }, + { 0x107, 0x3F }, + { 0x108, 0x3F }, + // { 0x109, 0x25 }, // workaournd for AD9084-EVAL + { 0x10A, 0x25 }, + { 0x10B, 0x3F }, + { 0x10C, 0x3F }, + { 0x10D, 0x3F }, + { 0x10E, 0x3F }, + { 0x10F, 0x3F }, + { 0x110, 0x3F }, + { 0x111, 0x3F }, + { 0x054, 0x00 }, + { 0x053, 0x45 }, + { 0x052, 0x00 }, + { 0x051, 0x00 }, + { 0x050, 0x00 }, + { 0x04F, 0x08 }, + { 0x04E, 0x06 }, + { 0x04D, 0x04 }, // workaournd for AD9084-EVAL + { 0x04C, 0x2B }, + { 0x04B, 0x5D }, + { 0x04A, 0x00 }, + { 0x048, 0x00 }, + { 0x047, 0x00 }, + { 0x046, 0x00 }, + { 0x045, 0x52 }, + { 0x044, 0x2E }, + { 0x043, 0xB8 }, + { 0x042, 0x01 }, + { 0x041, 0x00 }, + { 0x040, 0x00 }, + { 0x03F, 0x82 }, + { 0x03E, 0x4E }, + { 0x03C, 0x00 }, + { 0x03B, 0x00 }, + { 0x03A, 0xFA }, + { 0x039, 0x00 }, + { 0x038, 0x7C }, + { 0x037, 0xCA }, + { 0x036, 0xC0 }, + { 0x035, 0x25 }, // workaournd for AD9084-EVAL + { 0x034, 0x36 }, + { 0x033, 0x00 }, + { 0x032, 0x40 }, + { 0x031, 0x63 }, + { 0x030, 0x0F }, + { 0x02F, 0x3F }, + { 0x02E, 0x00 }, + { 0x02D, 0xF1 }, + { 0x02C, 0x0E }, + { 0x02B, 0x01 }, + { 0x02A, 0x30 }, + { 0x029, 0x09 }, + { 0x028, 0x00 }, + { 0x027, 0xF0 }, + { 0x026, 0x00 }, + { 0x025, 0x01 }, + { 0x024, 0x01 }, + { 0x023, 0x00 }, + { 0x022, 0x00 }, + { 0x021, 0x00 }, + { 0x01E, 0x20 }, + { 0x01D, 0x00 }, + { 0x01C, 0x00 }, + { 0x01B, 0x00 }, + { 0x01A, 0x00 }, + { 0x019, 0x00 }, + { 0x018, 0x00 }, + { 0x017, 0x00 }, + { 0x016, 0x00 }, + { 0x015, 0x06 }, + { 0x014, 0x00 }, + { 0x013, 0x00 }, + { 0x012, 0x00 }, + { 0x011, 0x00 }, + { 0x010, 0x50 } +}; + +static const struct regmap_config adf4382_regmap_config = { + .reg_bits = 16, + .val_bits = 8, + .read_flag_mask = BIT(7), +}; + +static int adf4382_pfd_compute(struct adf4382_state *st, u64 *pfd_freq_hz) +{ + u64 tmp; + + tmp = DIV_ROUND_CLOSEST(st->ref_freq_hz, st->ref_div); + if (st->ref_doubler_en) + tmp *= 2; + + if (tmp < ADF4382_PFD_FREQ_MIN || tmp > ADF4382_PFD_FREQ_MAX) + return -EINVAL; + + *pfd_freq_hz = tmp; + + return 0; +} + +static int adf4382_frac2_compute(struct adf4382_state *st, u64 res, + unsigned int pfd_freq_hz, u32 *frac2_word, + u32 *mod2_word) +{ + u32 channel_spacing; + int en_phase_resync; + u32 chsp_freq; + u32 mod2_tmp; + u32 mod2_max; + u32 mod2_wd; + u32 gcd_var; + + channel_spacing = 1; + mod2_wd = 1; + + en_phase_resync = regmap_test_bits(st->regmap, 0x1E, + ADF4382_EN_PHASE_RESYNC_MSK); + if (en_phase_resync < 0) + return en_phase_resync; + + if (en_phase_resync) + mod2_max = ADF4382_PHASE_RESYNC_MOD2WORD_MAX; + else + mod2_max = ADF4382_MOD2WORD_MAX; + + do { + chsp_freq = channel_spacing * ADF4382_MOD1WORD; + gcd_var = gcd(chsp_freq, pfd_freq_hz); + mod2_tmp = DIV_ROUND_UP(pfd_freq_hz, gcd_var); + + if (mod2_tmp > mod2_max) { + channel_spacing *= 5; + } else { + mod2_wd = mod2_tmp; + break; + } + + } while (channel_spacing < ADF4382_CHANNEL_SPACING_MAX); + + if (!en_phase_resync) + mod2_wd *= DIV_ROUND_DOWN_ULL(mod2_max, mod2_wd); + + *frac2_word = DIV_ROUND_CLOSEST_ULL(res * mod2_wd, pfd_freq_hz); + *mod2_word = mod2_wd; + + return 0; +} + +static int adf4382_pll_fract_n_compute(struct adf4382_state *st, unsigned int pfd_freq_hz, + u16 *n_int, u32 *frac1_word, u32 *frac2_word, + u32 *mod2_word) +{ + u64 rem; + u64 res; + + *n_int = div64_u64_rem(st->freq, pfd_freq_hz, &rem); + + res = rem * ADF4382_MOD1WORD; + *frac1_word = (u32)div64_u64_rem(res, pfd_freq_hz, &rem); + + *frac2_word = 0; + *mod2_word = 0; + + if (pfd_freq_hz > ADF4382_PFD_FREQ_FRAC_MAX) { + dev_warn(&st->spi->dev, "PFD frequency exceeds 250MHz."); + dev_warn(&st->spi->dev, "Only integer mode available."); + } + + if (rem > 0) + return adf4382_frac2_compute(st, rem, pfd_freq_hz, frac2_word, + mod2_word); + + return 0; +} + +static int _adf4382_set_freq(struct adf4382_state *st) +{ + u32 frac2_word = 0; + u32 mod2_word = 0; + u64 pfd_freq_hz; + u32 frac1_word; + u8 clkout_div; + u32 read_val; + u8 dclk_div1; + u8 int_mode; + u8 en_bleed; + u8 ldwin_pw = 0; + u16 n_int; + u8 div1; + u64 tmp; + u64 vco = 0; + int ret; + u8 var; + + ret = adf4382_pfd_compute(st, &pfd_freq_hz); + if (ret) { + dev_err(&st->spi->dev, "PFD frequency is out of range.\n"); + return ret; + } + + for (clkout_div = 0; clkout_div <= st->clkout_div_reg_val_max; clkout_div++) { + tmp = (1 << clkout_div) * st->freq; + if (tmp < st->vco_min || tmp > st->vco_max) + continue; + + vco = tmp; + break; + } + + if (vco == 0) { + dev_err(&st->spi->dev, "Output frequency is out of range.\n"); + ret = -EINVAL; + return ret; + } + + ret = adf4382_pll_fract_n_compute(st, pfd_freq_hz, &n_int, &frac1_word, + &frac2_word, &mod2_word); + if (ret) + return ret; + + if (frac1_word || frac2_word) { + int_mode = 0; + en_bleed = 1; + + if (pfd_freq_hz <= (40 * HZ_PER_MHZ)) { + ldwin_pw = 7; + } else if (pfd_freq_hz <= (50 * HZ_PER_MHZ)) { + ldwin_pw = 6; + } else if (pfd_freq_hz <= (100 * HZ_PER_MHZ)) { + ldwin_pw = 5; + } else if (pfd_freq_hz <= (200 * HZ_PER_MHZ)) { + ldwin_pw = 4; + } else if (pfd_freq_hz <= (250 * HZ_PER_MHZ)) { + if (st->freq >= (5000U * HZ_PER_MHZ) && + st->freq < (6400U * HZ_PER_MHZ)) { + ldwin_pw = 3; + } else { + ldwin_pw = 2; + } + } + } else { + int_mode = 1; + en_bleed = 0; + + tmp = DIV_ROUND_UP_ULL(pfd_freq_hz, UA_PER_A); + tmp *= adf4382_ci_ua[st->cp_i]; + tmp = DIV_ROUND_UP_ULL(st->bleed_word, tmp); + if (tmp <= 85) + ldwin_pw = 0; + else + ldwin_pw = 1; + } + + dev_info(&st->spi->dev, + "VCO=%llu PFD=%llu RFout_div=%u N=%u FRAC1=%u FRAC2=%u MOD2=%u\n", + vco, pfd_freq_hz, 1 << clkout_div, n_int, + frac1_word, frac2_word, mod2_word); + + ret = regmap_update_bits(st->regmap, 0x28, ADF4382_VAR_MOD_EN_MSK, + frac2_word != 0 ? 0xff : 0); + if (ret) + return ret; + + ret = regmap_update_bits(st->regmap, 0x30, ADF4382_MUTE_NCLK_MSK, 0xff); + if (ret) + return ret; + + ret = regmap_update_bits(st->regmap, 0x15, ADF4382_INT_MODE_MSK, + FIELD_PREP(ADF4382_INT_MODE_MSK, int_mode)); + if (ret) + return ret; + + ret = regmap_update_bits(st->regmap, 0x30, ADF4382_MUTE_NCLK_MSK, 0); + if (ret) + return ret; + + ret = regmap_write(st->regmap, 0x1D, + FIELD_GET(ADF4382_BLEED_I_LSB_MSK, st->bleed_word)); + if (ret) + return ret; + + var = (st->bleed_word >> 8) & ADF4382_BLEED_I_MSB_MSK; + ret = regmap_update_bits(st->regmap, 0x1E, ADF4382_BLEED_I_MSB_MSK, var); + if (ret) + return ret; + ret = regmap_update_bits(st->regmap, 0x1F, ADF4382_EN_BLEED_MSK, + FIELD_PREP(ADF4382_EN_BLEED_MSK, en_bleed)); + if (ret) + return ret; + + ret = regmap_write(st->regmap, 0x1A, + FIELD_GET(ADF4382_MOD2WORD_LSB_MSK, mod2_word)); + if (ret) + return ret; + + ret = regmap_write(st->regmap, 0x1B, + FIELD_GET(ADF4382_MOD2WORD_MID_MSK, mod2_word)); + if (ret) + return ret; + + ret = regmap_write(st->regmap, 0x1C, + FIELD_GET(ADF4382_MOD2WORD_MSB_MSK, mod2_word)); + if (ret) + return ret; + + ret = regmap_write(st->regmap, 0x12, + FIELD_GET(ADF4382_FRAC1WORD_LSB_MSK, frac1_word)); + if (ret) + return ret; + + ret = regmap_write(st->regmap, 0x13, + FIELD_GET(ADF4382_FRAC1WORD_MID_MSK, frac1_word)); + if (ret) + return ret; + + ret = regmap_write(st->regmap, 0x14, + FIELD_GET(ADF4382_FRAC1WORD_MSB_MSK, frac1_word)); + if (ret) + return ret; + + ret = regmap_update_bits(st->regmap, 0x15, ADF4382_FRAC1WORD_MSB, + FIELD_GET(ADF4382_FRAC1WORD_MS_BIT_MSK, frac1_word)); + if (ret) + return ret; + + ret = regmap_write(st->regmap, 0x17, + FIELD_GET(ADF4382_FRAC2WORD_LSB_MSK, frac2_word)); + if (ret) + return ret; + + ret = regmap_write(st->regmap, 0x18, + FIELD_GET(ADF4382_FRAC2WORD_MID_MSK, frac2_word)); + if (ret) + return ret; + + ret = regmap_write(st->regmap, 0x19, + FIELD_GET(ADF4382_FRAC2WORD_MSB_MSK, frac2_word)); + if (ret) + return ret; + + dclk_div1 = 2; + div1 = 8; + if (pfd_freq_hz <= ADF4382_DCLK_DIV1_0_MAX) { + dclk_div1 = 0; + div1 = 1; + } else if (pfd_freq_hz <= ADF4382_DCLK_DIV1_1_MAX) { + dclk_div1 = 1; + div1 = 2; + } + + ret = regmap_update_bits(st->regmap, 0x24, ADF4382_DCLK_DIV1_MSK, + FIELD_PREP(ADF4382_DCLK_DIV1_MSK, dclk_div1)); + if (ret) + return ret; + + ret = regmap_update_bits(st->regmap, 0x31, ADF4382_DCLK_MODE_MSK, + pfd_freq_hz > (11 * HZ_PER_MHZ) ? 0xff : 0); + if (ret) + return ret; + + ret = regmap_update_bits(st->regmap, 0x31, ADF4382_CAL_CT_SEL_MSK, 0xff); + if (ret) + return ret; + + ret = regmap_write(st->regmap, 0x38, ADF4382_VCO_CAL_VTUNE); + if (ret) + return ret; + + ret = regmap_write(st->regmap, 0x3a, ADF4382_VCO_CAL_ALC); + if (ret) + return ret; + + ret = regmap_write(st->regmap, 0x37, ADF4382_VCO_CAL_CNT); + if (ret) + return ret; + + var = DIV_ROUND_UP(div_u64(pfd_freq_hz, div1 * 400000) - 2, 4); + var = clamp_t(u8, var, 0U, 255U); + ret = regmap_write(st->regmap, 0x3e, var); + if (ret) + return ret; + + ret = regmap_update_bits(st->regmap, 0x2c, ADF4382_LD_COUNT_OPWR_MSK, + 10); + if (ret) + return ret; + + ret = regmap_update_bits(st->regmap, 0x2c, ADF4382_LDWIN_PW_MSK, + FIELD_PREP(ADF4382_LDWIN_PW_MSK, ldwin_pw)); + if (ret) + return ret; + + ret = regmap_update_bits(st->regmap, 0x11, ADF4382_CLKOUT_DIV_MSK, + FIELD_PREP(ADF4382_CLKOUT_DIV_MSK, clkout_div)); + if (ret) + return ret; + + var = (n_int >> 8) & ADF4382_N_INT_MSB_MSK; + ret = regmap_update_bits(st->regmap, 0x11, ADF4382_N_INT_MSB_MSK, var); + if (ret) + return ret; + + ret = regmap_write(st->regmap, 0x10, + FIELD_PREP(ADF4382_N_INT_LSB_MSK, n_int)); + if (ret) + return ret; + + mdelay(1); + + ret = regmap_read(st->regmap, 0x58, &read_val); + if (ret) + return ret; + + if (!FIELD_GET(ADF4382_PLL_LOCK_MSK, read_val)) { + dev_err(&st->spi->dev, "PLL is not locked.\n"); + return -EINVAL; + } + + dev_info(&st->spi->dev, "PLL %s, REF %s\n", + read_val & BIT(0) ? "Locked" : "Unlocked", + read_val & BIT(3) ? "OK" : "Error"); + + return 0; +} + +static int adf4382_set_freq(struct adf4382_state *st) +{ + int ret; + + mutex_lock(&st->lock); + ret = _adf4382_set_freq(st); + mutex_unlock(&st->lock); + + return ret; +} + +static int adf4382_get_freq(struct adf4382_state *st, u64 *val) +{ + unsigned int tmp; + u32 frac1 = 0; + u32 frac2 = 0; + u32 mod2 = 0; + u64 freq; + u64 pfd; + u16 n; + int ret; + + ret = adf4382_pfd_compute(st, &pfd); + if (ret) + return ret; + + ret = regmap_read(st->regmap, 0x11, &tmp); + if (ret) + return ret; + + n = FIELD_PREP(ADF4382_N_INT_MSB_MSK, tmp); + n = n << 8; + + ret = regmap_read(st->regmap, 0x10, &tmp); + if (ret) + return ret; + n |= FIELD_PREP(ADF4382_N_INT_LSB_MSK, tmp); + + ret = regmap_read(st->regmap, 0x15, &tmp); + if (ret) + return ret; + frac1 |= FIELD_PREP(ADF4382_FRAC1WORD_MS_BIT_MSK, tmp); + + ret = regmap_read(st->regmap, 0x14, &tmp); + if (ret) + return ret; + frac1 |= FIELD_PREP(ADF4382_FRAC1WORD_MSB_MSK, tmp); + + ret = regmap_read(st->regmap, 0x13, &tmp); + if (ret) + return ret; + frac1 |= FIELD_PREP(ADF4382_FRAC1WORD_MID_MSK, tmp); + + ret = regmap_read(st->regmap, 0x12, &tmp); + if (ret) + return ret; + frac1 |= FIELD_PREP(ADF4382_FRAC1WORD_LSB_MSK, tmp); + + ret = regmap_read(st->regmap, 0x19, &tmp); + if (ret) + return ret; + frac2 |= FIELD_PREP(ADF4382_FRAC2WORD_MSB_MSK, tmp); + + ret = regmap_read(st->regmap, 0x18, &tmp); + if (ret) + return ret; + frac2 |= FIELD_PREP(ADF4382_FRAC2WORD_MID_MSK, tmp); + + ret = regmap_read(st->regmap, 0x17, &tmp); + if (ret) + return ret; + frac2 |= FIELD_PREP(ADF4382_FRAC2WORD_LSB_MSK, tmp); + + ret = regmap_read(st->regmap, 0x1c, &tmp); + if (ret) + return ret; + mod2 |= FIELD_PREP(ADF4382_MOD2WORD_MSB_MSK, tmp); + + ret = regmap_read(st->regmap, 0x1b, &tmp); + if (ret) + return ret; + mod2 |= FIELD_PREP(ADF4382_MOD2WORD_MID_MSK, tmp); + + ret = regmap_read(st->regmap, 0x1a, &tmp); + if (ret) + return ret; + mod2 |= FIELD_PREP(ADF4382_MOD2WORD_LSB_MSK, tmp); + + if (mod2 == 0) + mod2 = 1; + + freq = frac2 * pfd; + freq = div_u64(freq, mod2); + freq = freq + (frac1 * pfd); + freq = div_u64(freq, ADF4382_MOD1WORD); + freq = freq + (n * pfd); + + *val = freq; + return 0; +} + +static int adf4382_set_phase_adjust(struct adf4382_state *st, u32 phase_fs) +{ + u8 phase_reg_value; + u64 phase_deg_fs; + u64 phase_deg_ns; + u64 phase_deg_ms; + u64 phase_bleed; + u64 phase_value; + u64 pfd_freq_hz; + u64 phase_ci; + int ret; + + ret = regmap_update_bits(st->regmap, 0x1E, ADF4382_EN_PHASE_RESYNC_MSK, + 0xff); + if (ret) + return ret; + + ret = regmap_update_bits(st->regmap, 0x1F, ADF4382_EN_BLEED_MSK, 0xff); + if (ret) + return ret; + + ret = regmap_update_bits(st->regmap, 0x32, ADF4382_DEL_MODE_MSK, 0x0); + if (ret) + return ret; + + ret = adf4382_pfd_compute(st, &pfd_freq_hz); + if (ret) { + dev_err(&st->spi->dev, "PFD frequency is out of range.\n"); + return ret; + } + + // Determine the phase adjustment in degrees relative the output freq. + phase_deg_fs = phase_fs * st->freq; + phase_deg_ns = div_u64(phase_deg_fs, FS_PER_NS); + phase_deg_ns = PERIOD_IN_DEG * phase_deg_ns; + phase_deg_ms = div_u64(phase_deg_ns, NS_PER_MS); + + if (phase_deg_ms > PERIOD_IN_DEG_MS) { + dev_err(&st->spi->dev, "Phase adjustment is out of range.\n"); + return -EINVAL; + } + + /* + * The charge pump current will also need to be taken in to account + * as well as the Bleed constant + */ + phase_ci = phase_deg_ms * adf4382_ci_ua[st->cp_i]; + phase_bleed = phase_ci * ADF4382_PHASE_BLEED_CNST_MUL; + phase_bleed = div_u64(phase_bleed, ADF4382_PHASE_BLEED_CNST_DIV); + + // Computation of the register value for the phase adjust + phase_value = phase_bleed * pfd_freq_hz; + phase_value = div64_u64(phase_value, st->freq); + phase_value = div_u64(phase_value, PERIOD_IN_DEG); + phase_value = DIV_ROUND_CLOSEST_ULL(phase_value, MILLI); + + if (phase_value == 0 && phase_fs != 0) { + dev_warn(&st->spi->dev, + "Phase %u fs too small to represent at Icp %u uA.\n", + phase_fs, adf4382_ci_ua[st->cp_i]); + phase_value = 1u; + } + + if (phase_value > U8_MAX) { + dev_warn(&st->spi->dev, + "Phase adjust register clamped to 255 (computed %llu).\n", + phase_value); + phase_value = U8_MAX; + } + + phase_reg_value = (u8)phase_value; + + ret = regmap_write(st->regmap, 0x33, phase_reg_value); + if (ret) + return ret; + + if (st->auto_align_en) + return regmap_update_bits(st->regmap, 0x32, + ADF4382_EN_AUTO_ALIGN_MSK, 0xff); + + ret = regmap_update_bits(st->regmap, 0x32, ADF4382_EN_AUTO_ALIGN_MSK, 0x0); + if (ret) + return ret; + + return regmap_update_bits(st->regmap, 0x34, ADF4382_PHASE_ADJ_MSK, 0xff); +} + +static int adf4382_get_phase_adjust(struct adf4382_state *st, u32 *val) +{ + unsigned int tmp; + u8 phase_reg_value; + u64 phase_value; + u64 pfd_freq_hz; + int ret; + + ret = regmap_read(st->regmap, 0x33, &tmp); + if (ret) + return ret; + + phase_reg_value = tmp; + + ret = adf4382_pfd_compute(st, &pfd_freq_hz); + if (ret) { + dev_err(&st->spi->dev, "PFD frequency is out of range.\n"); + return ret; + } + + phase_value = phase_reg_value * PERIOD_IN_DEG; + phase_value = phase_value * st->freq; + phase_value = div64_u64(phase_value, pfd_freq_hz); + + phase_value = phase_value * ADF4382_PHASE_BLEED_CNST_DIV; + phase_value = phase_value * MS_PER_NS; + phase_value = div_u64(phase_value, ADF4382_PHASE_BLEED_CNST_MUL); + phase_value = phase_value * MILLI; + phase_value = div_u64(phase_value, adf4382_ci_ua[st->cp_i]); + + phase_value = phase_value * NS_PER_FS; + phase_value = div_u64(phase_value, PERIOD_IN_DEG); + phase_value = div64_u64(phase_value, st->freq); + + *val = (u32)phase_value; + + return 0; +} + +static int adf4382_set_phase_pol(struct adf4382_state *st, bool ph_pol) +{ + return regmap_update_bits(st->regmap, 0x32, ADF4382_PHASE_ADJ_POL_MSK, + FIELD_PREP(ADF4382_PHASE_ADJ_POL_MSK, ph_pol)); +} + +static int adf4382_get_phase_pol(struct adf4382_state *st, bool *ph_pol) +{ + unsigned int tmp; + int ret; + + ret = regmap_read(st->regmap, 0x32, &tmp); + if (ret) + return ret; + + *ph_pol = FIELD_GET(ADF4382_PHASE_ADJ_POL_MSK, tmp); + + return 0; +} + +static int adf4382_set_out_power(struct adf4382_state *st, int ch, int pwr) +{ + if (pwr > ADF4382_OUT_PWR_MAX) + pwr = ADF4382_OUT_PWR_MAX; + + if (!ch) { + return regmap_update_bits(st->regmap, 0x29, ADF4382_CLK1_OPWR_MSK, + FIELD_PREP(ADF4382_CLK1_OPWR_MSK, pwr)); + } + + return regmap_update_bits(st->regmap, 0x29, ADF4382_CLK2_OPWR_MSK, + FIELD_PREP(ADF4382_CLK2_OPWR_MSK, pwr)); + +}; + +static int adf4382_get_out_power(struct adf4382_state *st, int ch, int *pwr) +{ + unsigned int tmp; + int ret; + + ret = regmap_read(st->regmap, 0x29, &tmp); + if (ret) + return ret; + + if (!ch) + *pwr = FIELD_GET(ADF4382_CLK1_OPWR_MSK, tmp); + else + *pwr = FIELD_GET(ADF4382_CLK2_OPWR_MSK, tmp); + + return 0; +} + +static int adf4382_set_en_chan(struct adf4382_state *st, int ch, int en) +{ + if (!ch) { + return regmap_update_bits(st->regmap, 0x2B, + ADF4382_PD_CLKOUT1_MSK, + FIELD_PREP(ADF4382_PD_CLKOUT1_MSK, !en)); + } + + return regmap_update_bits(st->regmap, 0x2B, ADF4382_PD_CLKOUT2_MSK, + FIELD_PREP(ADF4382_PD_CLKOUT2_MSK, !en)); +} + +static int adf4382_get_en_chan(struct adf4382_state *st, int ch, int *en) +{ + int enable; + + if (!ch) + enable = regmap_test_bits(st->regmap, 0x2B, + ADF4382_PD_CLKOUT1_MSK); + else + enable = regmap_test_bits(st->regmap, 0x2B, + ADF4382_PD_CLKOUT2_MSK); + if (enable < 0) + return enable; + + *en = !enable; + return 0; +} + +static ssize_t adf4382_write(struct iio_dev *indio_dev, uintptr_t private, + const struct iio_chan_spec *chan, const char *buf, + size_t len) +{ + struct adf4382_state *st = iio_priv(indio_dev); + unsigned long long val; + int ret; + + ret = kstrtoull(buf, 10, &val); + if (ret) + return ret; + + switch ((u32)private) { + case ADF4382_FREQ: + st->freq = val; + ret = adf4382_set_freq(st); + break; + case ADF4382_EN_AUTO_ALIGN: + st->auto_align_en = !!val; + ret = adf4382_set_phase_adjust(st, 0); + break; + default: + return -EINVAL; + } + + return ret ? ret : len; +} + +static ssize_t adf4382_read(struct iio_dev *indio_dev, uintptr_t private, + const struct iio_chan_spec *chan, char *buf) +{ + struct adf4382_state *st = iio_priv(indio_dev); + unsigned int val = 0; + u64 val_u64 = 0; + int ret; + + switch ((u32)private) { + case ADF4382_FREQ: + ret = adf4382_get_freq(st, &val_u64); + if (ret) + return ret; + return sysfs_emit(buf, "%llu\n", val_u64); + case ADF4382_EN_AUTO_ALIGN: + ret = regmap_read(st->regmap, 0x32, &val); + if (ret) + return ret; + return sysfs_emit(buf, "%lu\n", + FIELD_GET(ADF4382_EN_AUTO_ALIGN_MSK, val)); + case ADF4382_BLEED_POL: + case ADF4382_COARSE_CURRENT: + case ADF4382_FINE_CURRENT: { + u16 del_cnt = 0; + unsigned int tmp; + + ret = regmap_read(st->regmap, 0x64, &tmp); + if (ret) + return ret; + del_cnt |= FIELD_PREP(ADF4382_DEL_CNT_LSB_MSK, tmp); + + ret = regmap_read(st->regmap, 0x65, &tmp); + if (ret) + return ret; + del_cnt |= FIELD_PREP(ADF4382_DEL_CNT_MSB_MSK, tmp); + + switch ((u32)private) { + case ADF4382_BLEED_POL: + val = FIELD_GET(ADF4382_DEL_CNT_BLEED_POL_MSK, del_cnt); + break; + case ADF4382_COARSE_CURRENT: + val = FIELD_GET(ADF4382_DEL_CNT_COARSE_MSK, del_cnt); + break; + case ADF4382_FINE_CURRENT: + val = FIELD_GET(ADF4382_DEL_CNT_FINE_MSK, del_cnt); + break; + } + return sysfs_emit(buf, "%u\n", val); + } + default: + return -EINVAL; + } +} + +#define _ADF4382_EXT_INFO(_name, _shared, _ident) { \ + .name = _name, \ + .read = adf4382_read, \ + .write = adf4382_write, \ + .private = _ident, \ + .shared = _shared, \ +} + +static const struct iio_chan_spec_ext_info adf4382_ext_info[] = { + /* + * Usually we use IIO_CHAN_INFO_FREQUENCY, but there are + * values > 2^32 in order to support the entire frequency range + * in Hz. + */ + _ADF4382_EXT_INFO("frequency", IIO_SHARED_BY_TYPE, ADF4382_FREQ), + _ADF4382_EXT_INFO("en_auto_align", IIO_SHARED_BY_TYPE, ADF4382_EN_AUTO_ALIGN), + _ADF4382_EXT_INFO("bleed_pol", IIO_SHARED_BY_TYPE, ADF4382_BLEED_POL), + _ADF4382_EXT_INFO("coarse_current", IIO_SHARED_BY_TYPE, ADF4382_COARSE_CURRENT), + _ADF4382_EXT_INFO("fine_current", IIO_SHARED_BY_TYPE, ADF4382_FINE_CURRENT), + { }, +}; + +static int adf4382_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int *val, + int *val2, + long mask) +{ + struct adf4382_state *st = iio_priv(indio_dev); + bool pol; + u32 tmp; + int ret; + + switch (mask) { + case IIO_CHAN_INFO_HARDWAREGAIN: + ret = adf4382_get_out_power(st, chan->channel, val); + if (ret) + return ret; + return IIO_VAL_INT; + case IIO_CHAN_INFO_ENABLE: + ret = adf4382_get_en_chan(st, chan->channel, val); + if (ret) + return ret; + return IIO_VAL_INT; + case IIO_CHAN_INFO_PHASE: + ret = adf4382_get_phase_adjust(st, &tmp); + if (ret) + return ret; + *val = tmp; + + ret = adf4382_get_phase_pol(st, &pol); + if (ret) + return ret; + + if (pol) + *val *= -1; + + return IIO_VAL_INT; + case IIO_CHAN_INFO_PROCESSED: + ret = regmap_write(st->regmap, 0x54, 0x0); + if (ret) + return ret; + + ret = regmap_update_bits(st->regmap, 0x31, ADF4382_EN_ADC_CLK_MSK, ADF4382_EN_ADC_CLK_MSK); + if (ret) + return ret; + + ret = regmap_write(st->regmap, 0x54, ADF4382_ADC_ST_CNV_MSK); + if (ret) + return ret; + + ret = regmap_read_poll_timeout(st->regmap, 0x58, + tmp, !(tmp & ADF4382_ADC_BUSY), + 500, 10000); + if (ret) + return ret; + + ret = regmap_read(st->regmap, 0x5b, &tmp); + if (ret) + return ret; + + *val = tmp * 1000; + + ret = regmap_read(st->regmap, 0x5c, &tmp); + if (ret) + return ret; + + if (tmp & 0x1) + *val = -*val; + + ret = regmap_update_bits(st->regmap, 0x31, ADF4382_EN_ADC_CLK_MSK, 0); + if (ret) + return ret; + + return IIO_VAL_INT; + default: + return -EINVAL; + } +} + +static int adf4382_write_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int val, + int val2, + long mask) +{ + struct adf4382_state *st = iio_priv(indio_dev); + int ret; + + switch (mask) { + case IIO_CHAN_INFO_HARDWAREGAIN: + return adf4382_set_out_power(st, chan->channel, val); + case IIO_CHAN_INFO_ENABLE: + return adf4382_set_en_chan(st, chan->channel, val); + case IIO_CHAN_INFO_PHASE: + st->phase = val; + + if (val < 0) + ret = adf4382_set_phase_pol(st, true); + else + ret = adf4382_set_phase_pol(st, false); + if (ret) + return ret; + + return adf4382_set_phase_adjust(st, abs(val)); + default: + return -EINVAL; + } +} + +static int adf4382_reg_access(struct iio_dev *indio_dev, + unsigned int reg, + unsigned int write_val, + unsigned int *read_val) +{ + struct adf4382_state *st = iio_priv(indio_dev); + + if (read_val) + return regmap_read(st->regmap, reg, read_val); + + return regmap_write(st->regmap, reg, write_val); +} + +static const struct iio_info adf4382_info = { + .read_raw = &adf4382_read_raw, + .write_raw = &adf4382_write_raw, + .debugfs_reg_access = &adf4382_reg_access, +}; + +static const struct iio_chan_spec adf4382_channels[] = { + { + .type = IIO_ALTVOLTAGE, + .info_mask_separate = BIT(IIO_CHAN_INFO_ENABLE) | + BIT(IIO_CHAN_INFO_HARDWAREGAIN), + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_PHASE), + .indexed = 1, + .output = 1, + .channel = 0, + .ext_info = adf4382_ext_info, + }, + { + .type = IIO_ALTVOLTAGE, + .info_mask_separate = BIT(IIO_CHAN_INFO_ENABLE) | + BIT(IIO_CHAN_INFO_HARDWAREGAIN), + .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_PHASE), + .indexed = 1, + .output = 1, + .channel = 1, + .ext_info = adf4382_ext_info, + }, + { + .type = IIO_TEMP, + .indexed = 1, + .channel = 0, + .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), + }, +}; + +#ifdef CONFIG_DEBUG_FS +static int adf4382_show_del_cnt_raw(void *arg, u64 *val) +{ + struct iio_dev *indio_dev = arg; + struct adf4382_state *st = iio_priv(indio_dev); + unsigned int tmp; + u16 del_cnt = 0; + int ret; + + ret = regmap_read(st->regmap, 0x64, &tmp); + if (ret) + return ret; + del_cnt |= FIELD_PREP(ADF4382_DEL_CNT_LSB_MSK, tmp); + + ret = regmap_read(st->regmap, 0x65, &tmp); + if (ret) + return ret; + del_cnt |= FIELD_PREP(ADF4382_DEL_CNT_MSB_MSK, tmp); + + *val = del_cnt; + + return 0; +} +DEFINE_DEBUGFS_ATTRIBUTE(adf4382_del_cnt_raw_fops, + adf4382_show_del_cnt_raw, NULL, "%llu\n"); + +static int adf4382_show_bleed_pol(void *arg, u64 *val) +{ + struct iio_dev *indio_dev = arg; + struct adf4382_state *st = iio_priv(indio_dev); + unsigned int tmp; + u16 del_cnt = 0; + u8 bleed_pol = 0; + int ret; + + ret = regmap_read(st->regmap, 0x64, &tmp); + if (ret) + return ret; + del_cnt |= FIELD_PREP(ADF4382_DEL_CNT_LSB_MSK, tmp); + + ret = regmap_read(st->regmap, 0x65, &tmp); + if (ret) + return ret; + del_cnt |= FIELD_PREP(ADF4382_DEL_CNT_MSB_MSK, tmp); + + bleed_pol = FIELD_GET(ADF4382_DEL_CNT_BLEED_POL_MSK, del_cnt); + + *val = bleed_pol; + + return 0; +} +DEFINE_DEBUGFS_ATTRIBUTE(adf4382_bleed_pol_fops, + adf4382_show_bleed_pol, NULL, "%llu\n"); + +static int adf4382_show_fine_current(void *arg, u64 *val) +{ + struct iio_dev *indio_dev = arg; + struct adf4382_state *st = iio_priv(indio_dev); + u8 fine_current = 0; + unsigned int tmp; + u16 del_cnt = 0; + int ret; + + ret = regmap_read(st->regmap, 0x64, &tmp); + if (ret) + return ret; + del_cnt |= FIELD_PREP(ADF4382_DEL_CNT_LSB_MSK, tmp); + + ret = regmap_read(st->regmap, 0x65, &tmp); + if (ret) + return ret; + del_cnt |= FIELD_PREP(ADF4382_DEL_CNT_MSB_MSK, tmp); + + fine_current = FIELD_GET(ADF4382_DEL_CNT_FINE_MSK, del_cnt); + + *val = fine_current; + + return 0; +} +DEFINE_DEBUGFS_ATTRIBUTE(adf4382_fine_current_fops, + adf4382_show_fine_current, NULL, "%llu\n"); + +static int adf4382_show_coarse_current(void *arg, u64 *val) +{ + struct iio_dev *indio_dev = arg; + struct adf4382_state *st = iio_priv(indio_dev); + u8 coarse_current = 0; + unsigned int tmp; + u16 del_cnt = 0; + int ret; + + ret = regmap_read(st->regmap, 0x64, &tmp); + if (ret) + return ret; + del_cnt |= FIELD_PREP(ADF4382_DEL_CNT_LSB_MSK, tmp); + + ret = regmap_read(st->regmap, 0x65, &tmp); + if (ret) + return ret; + del_cnt |= FIELD_PREP(ADF4382_DEL_CNT_MSB_MSK, tmp); + + coarse_current = FIELD_GET(ADF4382_DEL_CNT_COARSE_MSK, del_cnt); + + *val = coarse_current; + + return 0; +} +DEFINE_DEBUGFS_ATTRIBUTE(adf4382_coarse_current_fops, + adf4382_show_coarse_current, NULL, "%llu\n"); + + +static int adf4382_show_lock_status(void *arg, u64 *val) +{ + struct iio_dev *indio_dev = arg; + struct adf4382_state *st = iio_priv(indio_dev); + u8 lock = 0; + unsigned int tmp; + int ret; + + ret = regmap_read(st->regmap, 0x58, &tmp); + if (ret) + return ret; + + lock = FIELD_GET(ADF4382_PLL_LOCK_MSK, tmp); + + *val = lock; + + return 0; +} +DEFINE_DEBUGFS_ATTRIBUTE(adf4382_show_lock_status_fops, + adf4382_show_lock_status, NULL, "%llu\n"); + +static void adf4382_debugfs_init(struct iio_dev *indio_dev) +{ + struct dentry *d = iio_get_debugfs_dentry(indio_dev); + + debugfs_create_file_unsafe("del_cnt_raw", 0400, d, + indio_dev, &adf4382_del_cnt_raw_fops); + + debugfs_create_file_unsafe("bleed_pol", 0400, d, + indio_dev, &adf4382_bleed_pol_fops); + + debugfs_create_file_unsafe("fine_current", 0400, d, + indio_dev, &adf4382_fine_current_fops); + + debugfs_create_file_unsafe("coarse_current", 0400, d, + indio_dev, &adf4382_coarse_current_fops); + + debugfs_create_file_unsafe("lock_status", 0400, d, + indio_dev, &adf4382_show_lock_status_fops); +} +#else +static void adf4382_debugfs_init(struct iio_dev *indio_dev) +{ +} +#endif + +static int adf4382_parse_device(struct adf4382_state *st) +{ + u32 tmp; + int ret; + int i; + + ret = device_property_read_u64(&st->spi->dev, "adi,power-up-frequency", + &st->freq); + if (ret) + st->freq = ADF4382_RFOUT_DEFAULT; + + ret = device_property_read_u32(&st->spi->dev, "adi,bleed-word", + &tmp); + if (ret) + st->bleed_word = 0; + else + st->bleed_word = (u16)tmp; + + ret = device_property_read_u32(&st->spi->dev, "adi,charge-pump-microamp", + &tmp); + if (ret) { + st->cp_i = ADF4382_CP_I_DEFAULT; + } else { + i = find_closest(tmp, adf4382_ci_ua, ARRAY_SIZE(adf4382_ci_ua)); + st->cp_i = (u8)i; + } + + ret = device_property_read_u32(&st->spi->dev, "adi,output-power-value", + &tmp); + if (ret) + st->opwr_a = ADF4382_OPOWER_DEFAULT; + else + st->opwr_a = clamp_t(u8, tmp, 0, 15); + + ret = device_property_read_u32(&st->spi->dev, "adi,ref-divider", + &tmp); + if (ret || !tmp) + st->ref_div = ADF4382_REF_DIV_DEFAULT; + else + st->ref_div = (u8)tmp; + + st->spi_3wire_en = device_property_read_bool(&st->spi->dev, + "adi,spi-3wire-enable"); + st->ref_doubler_en = device_property_read_bool(&st->spi->dev, + "adi,ref-doubler-enable"); + st->cmos_3v3 = device_property_read_bool(&st->spi->dev, "adi,cmos-3v3"); + + st->clkin = devm_clk_get_enabled(&st->spi->dev, "ref_clk"); + + return PTR_ERR_OR_ZERO(st->clkin); +} + +static int adf4382_scratchpad_check(struct adf4382_state *st) +{ + unsigned int val; + int ret; + + ret = regmap_write(st->regmap, 0x0A, ADF4382_SCRATCHPAD_VAL); + if (ret) + return ret; + + ret = regmap_read(st->regmap, 0x0A, &val); + if (ret) + return ret; + + if (val != ADF4382_SCRATCHPAD_VAL) + return dev_err_probe(&st->spi->dev, -EINVAL, + "Scratch pad test failed please check SPI connection"); + + return 0; +} + +static int adf4382_set_defaults(struct adf4382_state *st) +{ + unsigned int val; + int ret; + + ret = regmap_read(st->regmap, 0x67, &val); + if (ret) + return ret; + + switch (val) { + case ADF4382_CHIP_VER_U2: + return regmap_multi_reg_write(st->regmap, adf4382_u2_reg_default, + ARRAY_SIZE(adf4382_u2_reg_default)); + case ADF4382_CHIP_VER_U4: + return regmap_multi_reg_write(st->regmap, adf4382_u4_reg_default, + ARRAY_SIZE(adf4382_u4_reg_default)); + case ADF4382_CHIP_VER_U5_A: + case ADF4382_CHIP_VER_U5_B: + case ADF4382_CHIP_VER_U5_C: + case ADF4382_CHIP_VER_U5_D: + return regmap_multi_reg_write(st->regmap, adf4382_u5_reg_default, + ARRAY_SIZE(adf4382_u5_reg_default)); + default: + dev_err(&st->spi->dev, "Unknown chip version.\n"); + return -EINVAL; + } +} + +static int adf4382_init(struct adf4382_state *st) +{ + int ret; + bool en = true; + + ret = regmap_write(st->regmap, 0x00, ADF4382_RESET_CMD); + if (ret) + return ret; + + if (st->spi->mode & SPI_3WIRE || st->spi_3wire_en) + en = false; + + ret = regmap_write(st->regmap, 0x00, + FIELD_PREP(ADF4382_SDO_ACT_MSK, en) | + FIELD_PREP(ADF4382_SDO_ACT_R_MSK, en)); + if (ret) + return ret; + + ret = regmap_write(st->regmap, 0x3D, + FIELD_PREP(ADF4382_CMOS_OV_MSK, st->cmos_3v3)); + if (ret) + return ret; + + ret = adf4382_scratchpad_check(st); + if (ret) + return ret; + + ret = regmap_write(st->regmap, 0x20, + FIELD_PREP(ADF4382_EN_RDBLR_MSK, st->ref_doubler_en) | + FIELD_PREP(ADF4382_R_DIV_MSK, st->ref_div)); + if (ret) + return ret; + + ret = regmap_write(st->regmap, 0x1f, st->cp_i); + if (ret) + return ret; + + st->ref_freq_hz = clk_get_rate(st->clkin); + + ret = adf4382_set_defaults(st); + if (ret) + return ret; + + ret = regmap_update_bits(st->regmap, 0x20, ADF4382_EN_AUTOCAL_MSK, + ADF4382_EN_AUTOCAL_MSK); + if (ret) + return ret; + + ret = adf4382_set_out_power(st, 0, st->opwr_a); + if (ret) + return ret; + + ret = adf4382_set_out_power(st, 1, st->opwr_a); + if (ret) + return ret; + + return _adf4382_set_freq(st); +} + +static int adf4382_freq_change(struct notifier_block *nb, unsigned long action, + void *data) +{ + struct adf4382_state *st = container_of(nb, struct adf4382_state, nb); + int ret; + + if (action == POST_RATE_CHANGE) { + mutex_lock(&st->lock); + ret = notifier_from_errno(adf4382_init(st)); + mutex_unlock(&st->lock); + return ret; + } + + return NOTIFY_OK; +} + +static int adf4382_clock_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct adf4382_state *st = to_adf4382_state(hw); + + st->ref_freq_hz = parent_rate; + st->freq = rate * ADF4382_CLK_SCALE; + + return adf4382_set_freq(st); +} + +static void adf4382_clk_notifier_unreg(void *data) +{ + struct adf4382_state *st = data; + + clk_notifier_unregister(st->clkin, &st->nb); +} + +static unsigned long adf4382_clock_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct adf4382_state *st = to_adf4382_state(hw); + u64 freq = 0; + unsigned long rate; + + adf4382_get_freq(st, &freq); + rate = DIV_ROUND_CLOSEST_ULL(freq, ADF4382_CLK_SCALE); + + return rate; +} + +static int adf4382_clock_enable(struct clk_hw *hw) +{ + struct adf4382_state *st = to_adf4382_state(hw); + + return regmap_update_bits(st->regmap, 0x2B, + ADF4382_PD_CLKOUT1_MSK | ADF4382_PD_CLKOUT2_MSK, + 0x00); +} + +static void adf4382_clock_disable(struct clk_hw *hw) +{ + struct adf4382_state *st = to_adf4382_state(hw); + + regmap_update_bits(st->regmap, 0x2B, + ADF4382_PD_CLKOUT1_MSK | ADF4382_PD_CLKOUT2_MSK, + 0xff); +} + +static long adf4382_clock_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + struct adf4382_state *st = to_adf4382_state(hw); + u64 freq = rate * ADF4382_CLK_SCALE; + u8 div_rate; + u64 tmp; + + for (div_rate = 0; div_rate <= st->clkout_div_reg_val_max; div_rate++) { + tmp = (1 << div_rate) * freq; + if (tmp >= st->vco_min) + break; + } + div_rate = clamp_t(u8, div_rate, 0U, st->clkout_div_reg_val_max); + freq = clamp_t(u64, tmp, st->vco_min, st->vco_max); + freq = div_u64(freq, 1 << div_rate); + + rate = DIV_ROUND_CLOSEST_ULL(freq, ADF4382_CLK_SCALE); + return rate; +} + +static const struct clk_ops adf4382_clock_ops = { + .set_rate = adf4382_clock_set_rate, + .recalc_rate = adf4382_clock_recalc_rate, + .round_rate = adf4382_clock_round_rate, + .enable = adf4382_clock_enable, + .disable = adf4382_clock_disable, +}; + +static int adf4382_setup_clk(struct adf4382_state *st) +{ + struct device *dev = &st->spi->dev; + struct clk_init_data init; + struct clk *clk; + const char *parent_name; + + if (!device_property_present(dev, "#clock-cells")) + return 0; + + if (device_property_read_string(dev, "clock-output-names", &init.name)) { + init.name = devm_kasprintf(dev, GFP_KERNEL, "%s-clk", + fwnode_get_name(dev_fwnode(dev))); + if (!init.name) + return -ENOMEM; + } + + parent_name = of_clk_get_parent_name(dev->of_node, 0); + if (!parent_name) + return -EINVAL; + + init.ops = &adf4382_clock_ops; + init.parent_names = (parent_name ? &parent_name : NULL); + init.num_parents = (parent_name ? 1 : 0); + + st->clk_hw.init = &init; + clk = devm_clk_register(dev, &st->clk_hw); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + st->clkout = clk; + + return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, clk); +} + +static int adf4382_probe(struct spi_device *spi) +{ + struct iio_dev *indio_dev; + struct regmap *regmap; + struct adf4382_state *st; + int ret; + + indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); + if (!indio_dev) + return -ENOMEM; + + regmap = devm_regmap_init_spi(spi, &adf4382_regmap_config); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + st = iio_priv(indio_dev); + + indio_dev->info = &adf4382_info; + indio_dev->name = "adf4382"; + + st->regmap = regmap; + st->spi = spi; + st->phase = 0; + + st->vco_max = ADF4382_VCO_FREQ_MAX; + st->vco_min = ADF4382_VCO_FREQ_MIN; + st->clkout_div_reg_val_max = ADF4382_CLKOUT_DIV_REG_VAL_MAX; + if (spi_get_device_id(spi)->driver_data == ADF4382A) { + indio_dev->name = "adf4382a"; + st->vco_max = ADF4382A_VCO_FREQ_MAX; + st->vco_min = ADF4382A_VCO_FREQ_MIN; + st->clkout_div_reg_val_max = ADF4382A_CLKOUT_DIV_REG_VAL_MAX; + } + + mutex_init(&st->lock); + + ret = adf4382_parse_device(st); + if (ret) + return ret; + + st->nb.notifier_call = adf4382_freq_change; + ret = clk_notifier_register(st->clkin, &st->nb); + if (ret) + return ret; + + ret = devm_add_action_or_reset(&spi->dev, adf4382_clk_notifier_unreg, st); + if (ret) + return ret; + + ret = adf4382_init(st); + if (ret) + return dev_err_probe(&spi->dev, ret, "adf4382 init failed\n"); + + ret = adf4382_setup_clk(st); + if (ret) + return ret; + + //if (!st->clkout) { + indio_dev->channels = adf4382_channels; + indio_dev->num_channels = ARRAY_SIZE(adf4382_channels); + //} + + ret = devm_iio_device_register(&spi->dev, indio_dev); + if (ret) + return ret; + + if (IS_ENABLED(CONFIG_DEBUG_FS)) + adf4382_debugfs_init(indio_dev); + + return 0; +} + +static const struct spi_device_id adf4382_id[] = { + { "adf4382", ADF4382 }, + { "adf4382a", ADF4382A }, + {}, +}; +MODULE_DEVICE_TABLE(spi, adf4382_id); + +static const struct of_device_id adf4382_of_match[] = { + { .compatible = "adi,adf4382" }, + { .compatible = "adi,adf4382a" }, + {}, +}; +MODULE_DEVICE_TABLE(of, adf4382_of_match); + +static struct spi_driver adf4382_driver = { + .driver = { + .name = "adf4382", + .of_match_table = adf4382_of_match, + }, + .probe = adf4382_probe, + .id_table = adf4382_id, +}; +module_spi_driver(adf4382_driver); + +MODULE_AUTHOR("Antoniu Miclaus "); +MODULE_AUTHOR("Ciprian Hegbeli "); +MODULE_DESCRIPTION("Analog Devices ADF4382"); +MODULE_LICENSE("GPL"); diff --git a/drivers/iio/frequency/ltc6952.c b/drivers/iio/frequency/ltc6952.c index c468db75d08c7f..b7ed3e59ae1f07 100644 --- a/drivers/iio/frequency/ltc6952.c +++ b/drivers/iio/frequency/ltc6952.c @@ -15,6 +15,7 @@ #include #include +#include #include #include @@ -209,6 +210,7 @@ struct ltc6952_state { u32 vco_freq; bool follower; bool is_controller; + bool controller_srqmd_en_during_sync; bool filtv_enable; u32 cp_current; u32 sysct; @@ -220,7 +222,8 @@ struct ltc6952_state { struct clk *clks[LTC6952_NUM_CHAN]; struct clk_onecell_data clk_data; struct jesd204_dev *jdev; - struct clk *clkin; + struct clk *clkin; /* LTC6953: CLK_IN, LTC6952: REF_IN */ + struct clk *vcoin; }; #define to_output(_hw) container_of(_hw, struct ltc6952_output, hw) @@ -673,6 +676,10 @@ static int ltc6952_setup(struct iio_dev *indio_dev) r *= 2; } + dev_dbg(&st->spi->dev, + "VCO: %luMHz, PFD: %luMHz, REF: %luMHz, N: %lu, R: %lu\n", + vco_freq, pfd_freq, ref_freq, n, r); + /* Program the dividers */ ret |= ltc6952_write_mask(indio_dev, LTC6952_REG(0x06), LTC6952_RD_HIGH_MSK, @@ -681,6 +688,9 @@ static int ltc6952_setup(struct iio_dev *indio_dev) ret |= ltc6952_write(indio_dev, LTC6952_REG(0x08), LTC6952_ND_HIGH(n >> 8)); ret |= ltc6952_write(indio_dev, LTC6952_REG(0x09), LTC6952_ND_LOW(n)); + + ret |= ltc6952_write_mask(indio_dev, LTC6952_REG(0x0B), + LTC6952_CPMID_MSK, LTC6952_CPMID(0)); if (ret < 0) goto err_unlock; @@ -806,6 +816,8 @@ static int ltc6952_parse_dt(struct device *dev, st->follower = of_property_read_bool(np, "adi,follower-mode-enable"); st->is_controller = !of_property_read_bool(np, "adi,sync-via-ezs-srq-enable"); + st->controller_srqmd_en_during_sync = of_property_read_bool(np, + "adi,controller-srqmd-en-during-sync-en"); st->filtv_enable = of_property_read_bool(np, "adi,input-buffer-filt-enable"); @@ -934,7 +946,9 @@ static int ltc6952_jesd204_clks_sync1(struct jesd204_dev *jdev, return ret; ret = ltc6952_write_mask(indio_dev, LTC6952_REG(0x0B), - LTC6952_SRQMD_MSK, LTC6952_SRQMD(0)); + LTC6952_SRQMD_MSK, + LTC6952_SRQMD(st->controller_srqmd_en_during_sync ? + st->is_controller : 0)); if (ret) return ret; @@ -1030,6 +1044,10 @@ static int ltc6952_probe(struct spi_device *spi) if (IS_ERR(st->clkin)) return dev_err_probe(&spi->dev, PTR_ERR(st->clkin), "failed to get clkin\n"); + st->vcoin = devm_clk_get_optional(&spi->dev, "vcoin"); + if (IS_ERR(st->vcoin)) + return dev_err_probe(&spi->dev, PTR_ERR(st->vcoin), "failed to get vcoin\n"); + st->jdev = devm_jesd204_dev_register(&spi->dev, <c6952_jesd204_data); if (IS_ERR(st->jdev)) return PTR_ERR(st->jdev); @@ -1062,6 +1080,28 @@ static int ltc6952_probe(struct spi_device *spi) return ret; } + if (st->vcoin) { + struct clock_scale devclk_clkscale; + + ret = of_clk_get_scale(spi->dev.of_node, "vcoin", &devclk_clkscale); + if (ret < 0) { + devclk_clkscale.mult = 1; + devclk_clkscale.div = 1; + } + + ret = clk_set_rate_scaled(st->vcoin, st->vco_freq, &devclk_clkscale); + if (ret < 0) + return ret; + + ret = clk_prepare_enable(st->vcoin); + if (ret < 0) + return ret; + + ret = devm_add_action_or_reset(&spi->dev, ltc6952_clk_disable_unprepare, st->vcoin); + if (ret) + return ret; + } + indio_dev->dev.parent = &spi->dev; indio_dev->name = spi->dev.of_node->name; indio_dev->info = <c6952_iio_info; diff --git a/drivers/iio/jesd204/axi_jesd204_rx.c b/drivers/iio/jesd204/axi_jesd204_rx.c index 1f156096935f08..5477e5130f38f8 100644 --- a/drivers/iio/jesd204/axi_jesd204_rx.c +++ b/drivers/iio/jesd204/axi_jesd204_rx.c @@ -384,13 +384,24 @@ static int __axi_jesd204_rx_laneinfo_64b66b_read(struct axi_jesd204_rx *jesd, { int ret = pos; u8 extend_multiblock; + u32 octets_per_multiframe, lane_latency; extend_multiblock = JESD204_EMB_STATE_GET(lane_status); + octets_per_multiframe = readl_relaxed(jesd->base + JESD204_RX_REG_LINK_CONF0); + octets_per_multiframe &= 0xffff; + octets_per_multiframe += 1; + ret += scnprintf(buf + ret, PAGE_SIZE - ret, "State of Extended multiblock alignment:%s\n", axi_jesd204_rx_emb_state_label[extend_multiblock]); + lane_latency = readl_relaxed(jesd->base + JESD204_RX_REG_LANE_LATENCY(lane)); + ret += scnprintf(buf + ret, PAGE_SIZE - ret, + "Lane Latency: %u (min/max 64/%u)", + lane_latency, + octets_per_multiframe); + return ret; } diff --git a/drivers/iio/logic/Kconfig b/drivers/iio/logic/Kconfig index c2ed9e70d01621..79403c184f265e 100644 --- a/drivers/iio/logic/Kconfig +++ b/drivers/iio/logic/Kconfig @@ -12,3 +12,8 @@ config M2K_LOGIC_ANALYZER ADALM-2000 (M2k) platform. endmenu + +config AXI_AION_TRIG + tristate "AXI AION Trigger support" + help + Support for the AXI AION Trigger module HDL IP Core. diff --git a/drivers/iio/logic/Makefile b/drivers/iio/logic/Makefile index 47bbe888543d99..e9558ec2997a4f 100644 --- a/drivers/iio/logic/Makefile +++ b/drivers/iio/logic/Makefile @@ -1,3 +1,5 @@ obj-$(CONFIG_M2K_LOGIC_ANALYZER) += m2k-logic-analyzer.o obj-$(CONFIG_M2K_LOGIC_ANALYZER) += m2k-fabric.o obj-$(CONFIG_M2K_LOGIC_ANALYZER) += m2k-trigger-ad.o +obj-$(CONFIG_AXI_AION_TRIG) += axi-aion-trig.o + diff --git a/drivers/iio/logic/axi-aion-trig.c b/drivers/iio/logic/axi-aion-trig.c new file mode 100644 index 00000000000000..6fdb06a321db69 --- /dev/null +++ b/drivers/iio/logic/axi-aion-trig.c @@ -0,0 +1,823 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Driver for AXI-AION-TRIG IP core. + * + * Copyright 2026 Analog Devices Inc. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define AXI_AION_IIO_DRIVER_NAME "axi_aion_trig" + +/* Register addresses */ + +#define AION_IDENTIFICATION_REG 0x000C +#define AION_CONTROL_REG 0x0010 +#define AION_DEBUG_REG 0x0014 +#define AION_MANUAL_TRIGGER 0x0018 +#define AION_TRIG_CH0_PHASE_REG 0x001C +#define AION_TRIG_CH1_PHASE_REG 0x0020 +#define AION_TRIG_CH2_PHASE_REG 0x0024 +#define AION_TRIG_CH3_PHASE_REG 0x0028 +#define AION_TRIG_CH4_PHASE_REG 0x002C +#define AION_TRIG_CH5_PHASE_REG 0x0030 +#define AION_TRIG_CH6_PHASE_REG 0x0034 +#define AION_TRIG_CH7_PHASE_REG 0x0038 + +/* Register bit masks */ +#define AION_CONTROL_ENABLE_MISALIGN_CHECK BIT(14) +#define AION_CONTROL_DEBUG_TRIG BIT(13) +#define AION_CONTROL_ENABLE_DEBUG_TRIG BIT(12) +#define AION_CONTROL_TRIG_SELECT BIT(11) +#define AION_CONTROL_SW_RESET BIT(10) +#define AION_CONTROL_TRIG_CHANNEL_ENABLE_MASK GENMASK(9, 2) +#define AION_CONTROL_DISABLE_INTERNAL_BSYNC_MASK BIT(1) +#define AION_CONTROL_BSYNC_DIRECTION_MASK BIT(0) + +#define AION_DEBUG_BSYNC_STATE_MASK GENMASK(26, 24) +#define AION_DEBUG_BSYNC_CAPTURED_MASK BIT(23) +#define AION_DEBUG_BSYNC_ALIGNMENT_ERROR_MASK BIT(22) +#define AION_DEBUG_BSYNC_RATIO_MASK GENMASK(21, 6) +#define AION_DEBUG_BSYNC_DELAY_MASK GENMASK(5, 1) +#define AION_DEBUG_BSYNC_READY_MASK BIT(0) + +#define AION_TRIG_CH_STATE_MASK GENMASK(18, 16) +#define AION_TRIG_CH_PHASE_MASK GENMASK(15, 0) + +static const char *const axi_aion_trig_states[] = { + "idle", "trig_edge", "phase_read", "trig_adjust", + "UNDEF", "UNDEF", "UNDEF", "UNDEF", +}; + +static const char *const axi_aion_bsync_states[] = { + "idle", "bsync_edge", "calib", "bsync_gen", + "bsync_alignment_error", "UNDEF", "UNDEF", "UNDEF", +}; + +struct axi_aion_state { + struct regmap *regmap; + /* + * lock to protect against concurrent accesses of the HW and device + * global variables. + */ + struct mutex lock; + struct clk *dev_clk; + struct jesd204_dev *jdev; + struct iio_channel *iio_adf4030; + u32 trigX_phase[8]; +}; + +struct axi_aion_state *st_global; + +enum { + BSYNC_OUT_EN, + BSYNC_INT_EN, + STATUS, + FREQUENCY, + TRIGGER_SELECT_GPIO_EN, + MANUAL_TRIGGER, +}; + +static ssize_t axi_aion_ext_info_read(struct iio_dev *indio_dev, uintptr_t private, + const struct iio_chan_spec *chan, char *buf) +{ + struct axi_aion_state *st = iio_priv(indio_dev); + unsigned int regval, regval2; + unsigned long dev_clk; + int ret; + + guard(mutex)(&st->lock); + + switch (private) { + case BSYNC_OUT_EN: + ret = regmap_read(st->regmap, AION_CONTROL_REG, ®val); + if (ret) + return ret; + + return sysfs_emit(buf, "%u\n", !(regval & AION_CONTROL_BSYNC_DIRECTION_MASK)); + case BSYNC_INT_EN: + ret = regmap_read(st->regmap, AION_CONTROL_REG, ®val); + if (ret) + return ret; + + return sysfs_emit(buf, "%u\n", + !(regval & AION_CONTROL_DISABLE_INTERNAL_BSYNC_MASK)); + case STATUS: + ret = regmap_read(st->regmap, AION_DEBUG_REG, ®val); + if (ret) + return ret; + + ret = regmap_read(st->regmap, chan->address, ®val2); + if (ret) + return ret; + + return sysfs_emit(buf, + "trig_state=%s bsync_state=%s bsync_captured=%u bsync_alignment_error=%u bsync_ratio=%u bsync_delay=%u bsync_ready=%u\n", + axi_aion_trig_states[(regval2 & AION_TRIG_CH_STATE_MASK) >> 16], + axi_aion_bsync_states[(regval & AION_DEBUG_BSYNC_STATE_MASK) >> 24], + !!(regval & AION_DEBUG_BSYNC_CAPTURED_MASK), + !!(regval & AION_DEBUG_BSYNC_ALIGNMENT_ERROR_MASK), + (u32)((regval & AION_DEBUG_BSYNC_RATIO_MASK) >> 6), + (u32)((regval & AION_DEBUG_BSYNC_DELAY_MASK) >> 1), + !!(regval & AION_DEBUG_BSYNC_READY_MASK)); + case FREQUENCY: + ret = regmap_read(st->regmap, AION_DEBUG_REG, ®val); + if (ret) + return ret; + + dev_clk = clk_get_rate(st->dev_clk); + if (!dev_clk) + return -EINVAL; + + return sysfs_emit(buf, "%lu\n", + dev_clk / ((regval & AION_DEBUG_BSYNC_RATIO_MASK) >> 6) * 2); + + case TRIGGER_SELECT_GPIO_EN: + ret = regmap_read(st->regmap, AION_CONTROL_REG, ®val); + if (ret) + return ret; + + return sysfs_emit(buf, "%u\n", !!(regval & AION_CONTROL_TRIG_SELECT)); + case MANUAL_TRIGGER: + ret = regmap_read(st->regmap, AION_MANUAL_TRIGGER, ®val); + if (ret) + return ret; + + return sysfs_emit(buf, "%u\n", regval); /* Self clears should always be 0 */ + default: + return -EINVAL; + }; +} + +static ssize_t axi_aion_ext_info_write(struct iio_dev *indio_dev, uintptr_t private, + const struct iio_chan_spec *chan, const char *buf, + size_t len) +{ + struct axi_aion_state *st = iio_priv(indio_dev); + bool readin; + int ret = 0; + + ret = kstrtobool(buf, &readin); + if (ret) + return ret; + + guard(mutex)(&st->lock); + + switch (private) { + case BSYNC_OUT_EN: + if (readin) + ret = regmap_clear_bits(st->regmap, AION_CONTROL_REG, + AION_CONTROL_BSYNC_DIRECTION_MASK); + else + ret = regmap_set_bits(st->regmap, AION_CONTROL_REG, + AION_CONTROL_BSYNC_DIRECTION_MASK); + + if (ret) + return ret; + + return len; + case BSYNC_INT_EN: + if (readin) + ret = regmap_clear_bits(st->regmap, AION_CONTROL_REG, + AION_CONTROL_DISABLE_INTERNAL_BSYNC_MASK); + else + ret = regmap_set_bits(st->regmap, AION_CONTROL_REG, + AION_CONTROL_DISABLE_INTERNAL_BSYNC_MASK); + if (ret) + return ret; + + return len; + case MANUAL_TRIGGER: + if (readin) { + ret = regmap_write(st->regmap, AION_MANUAL_TRIGGER, 1); + if (ret) + return ret; + } + + return len; + case TRIGGER_SELECT_GPIO_EN: + if (readin) + ret = regmap_set_bits(st->regmap, AION_CONTROL_REG, + AION_CONTROL_TRIG_SELECT); + else + ret = regmap_clear_bits(st->regmap, AION_CONTROL_REG, + AION_CONTROL_TRIG_SELECT); + if (ret) + return ret; + + return len; + default: + return -ENOTSUPP; + } + + return len; +} + +static struct iio_chan_spec_ext_info axi_aion_ext_info[] = { + { + .name = "output_enable", + .read = axi_aion_ext_info_read, + .write = axi_aion_ext_info_write, + .shared = IIO_SHARED_BY_TYPE, + .private = BSYNC_OUT_EN, + }, + { + .name = "internal_bsync_enable", + .read = axi_aion_ext_info_read, + .write = axi_aion_ext_info_write, + .shared = IIO_SHARED_BY_TYPE, + .private = BSYNC_INT_EN, + }, + { + .name = "status", + .read = axi_aion_ext_info_read, + .write = axi_aion_ext_info_write, + .shared = IIO_SEPARATE, + .private = STATUS, + }, + { + .name = "frequency", + .read = axi_aion_ext_info_read, + .write = axi_aion_ext_info_write, + .shared = IIO_SHARED_BY_TYPE, + .private = FREQUENCY, + }, + { + .name = "trigger_select_gpio_enable", + .read = axi_aion_ext_info_read, + .write = axi_aion_ext_info_write, + .shared = IIO_SHARED_BY_TYPE, + .private = TRIGGER_SELECT_GPIO_EN, + }, + { + .name = "trigger_now", + .read = axi_aion_ext_info_read, + .write = axi_aion_ext_info_write, + .shared = IIO_SHARED_BY_TYPE, + .private = MANUAL_TRIGGER, + }, + {} +}; + +static int axi_aion_iio_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, + int *val, int *val2, long mask) +{ + struct axi_aion_state *st = iio_priv(indio_dev); + unsigned int regval; + int ret; + + switch (mask) { + case IIO_CHAN_INFO_PHASE: + ret = regmap_read(st->regmap, chan->address, ®val); + if (ret) + return ret; + *val = regval & 0xFFFF; + return IIO_VAL_INT; + case IIO_CHAN_INFO_ENABLE: + ret = regmap_read(st->regmap, AION_CONTROL_REG, ®val); + if (ret) + return ret; + *val = !!(regval & BIT(chan->channel + 2)); + return IIO_VAL_INT; + default: + return -EINVAL; + } +} + +static int axi_aion_iio_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, + int val, int val2, long mask) +{ + struct axi_aion_state *st = iio_priv(indio_dev); + + switch (mask) { + case IIO_CHAN_INFO_PHASE: + if (val > 0xFFFF || val < 0) + return -EINVAL; + st->trigX_phase[chan->channel] = val; + return regmap_write(st->regmap, chan->address, val); + case IIO_CHAN_INFO_ENABLE: + return regmap_update_bits(st->regmap, AION_CONTROL_REG, BIT(chan->channel + 2), + val ? BIT(chan->channel + 2) : 0); + default: + return -EINVAL; + } +} + +static int axi_aion_reg_access(struct iio_dev *indio_dev, unsigned int reg, unsigned int writeval, + unsigned int *readval) +{ + struct axi_aion_state *st = iio_priv(indio_dev); + + guard(mutex)(&st->lock); + + if (readval) + return regmap_read(st->regmap, reg, readval); + + return regmap_write(st->regmap, reg, writeval); +} + +static const struct iio_info axi_aion_iio_info = { + .read_raw = axi_aion_iio_read_raw, + .write_raw = axi_aion_iio_write_raw, + .debugfs_reg_access = &axi_aion_reg_access, +}; + +static const struct iio_chan_spec axi_aion_iio_channels[] = { + { + .type = IIO_VOLTAGE, + .indexed = 1, + .channel = 0, + .address = AION_TRIG_CH0_PHASE_REG, + .info_mask_separate = BIT(IIO_CHAN_INFO_PHASE) | BIT(IIO_CHAN_INFO_ENABLE), + .ext_info = axi_aion_ext_info, + }, + { + .type = IIO_VOLTAGE, + .indexed = 1, + .channel = 1, + .address = AION_TRIG_CH1_PHASE_REG, + .info_mask_separate = BIT(IIO_CHAN_INFO_PHASE) | BIT(IIO_CHAN_INFO_ENABLE), + .ext_info = axi_aion_ext_info, + }, + { + .type = IIO_VOLTAGE, + .indexed = 1, + .channel = 2, + .address = AION_TRIG_CH2_PHASE_REG, + .info_mask_separate = BIT(IIO_CHAN_INFO_PHASE) | BIT(IIO_CHAN_INFO_ENABLE), + .ext_info = axi_aion_ext_info, + }, + { + .type = IIO_VOLTAGE, + .indexed = 1, + .channel = 3, + .address = AION_TRIG_CH3_PHASE_REG, + .info_mask_separate = BIT(IIO_CHAN_INFO_PHASE) | BIT(IIO_CHAN_INFO_ENABLE), + .ext_info = axi_aion_ext_info, + }, + { + .type = IIO_VOLTAGE, + .indexed = 1, + .channel = 4, + .address = AION_TRIG_CH4_PHASE_REG, + .info_mask_separate = BIT(IIO_CHAN_INFO_PHASE) | BIT(IIO_CHAN_INFO_ENABLE), + .ext_info = axi_aion_ext_info, + }, + { + .type = IIO_VOLTAGE, + .indexed = 1, + .channel = 5, + .address = AION_TRIG_CH5_PHASE_REG, + .info_mask_separate = BIT(IIO_CHAN_INFO_PHASE) | BIT(IIO_CHAN_INFO_ENABLE), + .ext_info = axi_aion_ext_info, + }, + { + .type = IIO_VOLTAGE, + .indexed = 1, + .channel = 6, + .address = AION_TRIG_CH6_PHASE_REG, + .info_mask_separate = BIT(IIO_CHAN_INFO_PHASE) | BIT(IIO_CHAN_INFO_ENABLE), + .ext_info = axi_aion_ext_info, + }, + { + .type = IIO_VOLTAGE, + .indexed = 1, + .channel = 7, + .address = AION_TRIG_CH7_PHASE_REG, + .info_mask_separate = BIT(IIO_CHAN_INFO_PHASE) | BIT(IIO_CHAN_INFO_ENABLE), + .ext_info = axi_aion_ext_info, + }, +}; + +void axi_aion_trig_manual_trigger(void) +{ + regmap_write(st_global->regmap, AION_MANUAL_TRIGGER, 1); +} +EXPORT_SYMBOL_GPL(axi_aion_trig_manual_trigger); + +static int axi_aion_enable_debug_trig_set(void *arg, const u64 val) +{ + struct iio_dev *indio_dev = arg; + struct axi_aion_state *st = iio_priv(indio_dev); + + guard(mutex)(&st->lock); + + if (val) + return regmap_set_bits(st->regmap, AION_CONTROL_REG, + AION_CONTROL_ENABLE_DEBUG_TRIG); + + return regmap_clear_bits(st->regmap, AION_CONTROL_REG, + AION_CONTROL_ENABLE_DEBUG_TRIG); +} + +static int axi_aion_enable_debug_trig_get(void *arg, u64 *val) +{ + struct iio_dev *indio_dev = arg; + struct axi_aion_state *st = iio_priv(indio_dev); + int ret; + u32 regval; + + guard(mutex)(&st->lock); + + ret = regmap_read(st->regmap, AION_CONTROL_REG, ®val); + + *val = !!(regval & AION_CONTROL_ENABLE_DEBUG_TRIG); + + return ret; +} +DEFINE_DEBUGFS_ATTRIBUTE(axi_aion_enable_debug_trig_fops, + axi_aion_enable_debug_trig_get, + axi_aion_enable_debug_trig_set, "%llu\n"); + +static int axi_aion_debug_trig_set(void *arg, const u64 val) +{ + struct iio_dev *indio_dev = arg; + struct axi_aion_state *st = iio_priv(indio_dev); + + guard(mutex)(&st->lock); + + if (val) + return regmap_set_bits(st->regmap, AION_CONTROL_REG, + AION_CONTROL_DEBUG_TRIG); + + return regmap_clear_bits(st->regmap, AION_CONTROL_REG, AION_CONTROL_DEBUG_TRIG); +} + +static int axi_aion_debug_trig_get(void *arg, u64 *val) +{ + struct iio_dev *indio_dev = arg; + struct axi_aion_state *st = iio_priv(indio_dev); + int ret; + u32 regval; + + guard(mutex)(&st->lock); + + ret = regmap_read(st->regmap, AION_CONTROL_REG, ®val); + + *val = !!(regval & AION_CONTROL_DEBUG_TRIG); + + return ret; +} +DEFINE_DEBUGFS_ATTRIBUTE(axi_aion_debug_trig_fops, + axi_aion_debug_trig_get, + axi_aion_debug_trig_set, "%llu\n"); + +static int axi_aion_iio_write_channel_ext_info(struct iio_channel *chan, + const char *ext_name, long long val) +{ + ssize_t size; + char str[16]; + + snprintf(str, sizeof(str), "%lld\n", val); + + size = iio_write_channel_ext_info(chan, ext_name, str, sizeof(str)); + if (size != sizeof(str)) + return -EINVAL; + + return 0; +} + +static int axi_aion_jesd204_link_supported(struct jesd204_dev *jdev, + enum jesd204_state_op_reason reason, + struct jesd204_link *lnk) +{ + struct device *dev = jesd204_dev_to_device(jdev); + + if (reason != JESD204_STATE_OP_REASON_INIT) + return JESD204_STATE_CHANGE_DONE; + + dev_dbg(dev, "%s:%d reason %s\n", __func__, __LINE__, + jesd204_state_op_reason_str(reason)); + + return JESD204_STATE_CHANGE_DONE; +} + +static int axi_aion_jesd204_opt_setup_stage1(struct jesd204_dev *jdev, + enum jesd204_state_op_reason reason) +{ + u32 debug_msk = AION_DEBUG_BSYNC_READY_MASK | AION_DEBUG_BSYNC_CAPTURED_MASK; + struct device *dev = jesd204_dev_to_device(jdev); + struct iio_dev *indio_dev = dev_get_drvdata(dev); + struct axi_aion_state *st = iio_priv(indio_dev); + int ret, i; + u32 regval; + s64 adf4030_phase; + int val, val2; + + if (reason != JESD204_STATE_OP_REASON_INIT) + return JESD204_STATE_CHANGE_DONE; + + dev_dbg(dev, "%s:%d reason %s\n", __func__, __LINE__, + jesd204_state_op_reason_str(reason)); + + if (IS_ERR_OR_NULL(st->iio_adf4030)) + return JESD204_STATE_CHANGE_DONE; + + ret = regmap_write(st->regmap, AION_CONTROL_REG, + AION_CONTROL_SW_RESET | AION_CONTROL_BSYNC_DIRECTION_MASK); + if (ret) { + dev_err(dev, "Failed to reset BSYNC\n"); + goto out; + } + + ret = axi_aion_iio_write_channel_ext_info(st->iio_adf4030, "output_enable", 1); + if (ret) { + dev_err(dev, "Failed to enable BSYNC output\n"); + goto out; + } + ret = iio_write_channel_attribute(st->iio_adf4030, 0, 0, IIO_CHAN_INFO_PHASE); + if (ret) { + dev_err(dev, "Failed to set phase\n"); + goto out; + } + + ret = regmap_write(st->regmap, AION_CONTROL_REG, + AION_CONTROL_SW_RESET | AION_CONTROL_BSYNC_DIRECTION_MASK); + if (ret) { + dev_err(dev, "Failed to reset BSYNC\n"); + goto out; + } + + ret = regmap_read_poll_timeout(st->regmap, AION_DEBUG_REG, + regval, (regval & debug_msk) == debug_msk, 100, 10000); + if (ret) { + dev_err(dev, "BSYNC not ready %u\n", __LINE__); + goto out; + } + + ret = regmap_set_bits(st->regmap, AION_CONTROL_REG, + AION_CONTROL_DISABLE_INTERNAL_BSYNC_MASK); + if (ret) { + dev_err(dev, "Failed to disable internal BSYNC\n"); + goto out; + } + + ret = axi_aion_iio_write_channel_ext_info(st->iio_adf4030, "output_enable", 0); + if (ret) { + dev_err(dev, "Failed to enable BSYNC output\n"); + goto out; + } + + ret = regmap_clear_bits(st->regmap, AION_CONTROL_REG, + AION_CONTROL_DISABLE_INTERNAL_BSYNC_MASK); + if (ret) { + dev_err(dev, "Failed to enable internal BSYNC\n"); + goto out; + } + + ret = regmap_clear_bits(st->regmap, AION_CONTROL_REG, + AION_CONTROL_BSYNC_DIRECTION_MASK); + if (ret) { + dev_err(dev, "Failed to set BSYNC direction\n"); + goto out; + } + + ret = regmap_read_poll_timeout(st->regmap, AION_DEBUG_REG, + regval, (regval & AION_DEBUG_BSYNC_READY_MASK), + 100, 10000); + if (ret) { + dev_err(dev, "BSYNC not ready %u\n", __LINE__); + goto out; + } + + ret = iio_read_channel_attribute(st->iio_adf4030, &val, &val2, IIO_CHAN_INFO_PHASE); + if (ret != IIO_VAL_INT_64) { + dev_err(dev, "Failed to read phase (ret=%d)\n", ret); + goto out; + } + + adf4030_phase = (s64)((((u64)val2) << 32) | (u32)val); + + dev_info(dev, "FPGA BSYNC ToF measured phase: %lld fs\n", adf4030_phase); + + ret = regmap_set_bits(st->regmap, AION_CONTROL_REG, + AION_CONTROL_DISABLE_INTERNAL_BSYNC_MASK); + if (ret) { + dev_err(dev, "Failed to disable internal BSYNC\n"); + goto out; + } + + ret = regmap_set_bits(st->regmap, AION_CONTROL_REG, + AION_CONTROL_BSYNC_DIRECTION_MASK); + if (ret) { + dev_err(dev, "Failed to set BSYNC direction\n"); + goto out; + } + + ret = axi_aion_iio_write_channel_ext_info(st->iio_adf4030, "output_enable", 1); + if (ret) { + dev_err(dev, "Failed to enable BSYNC output\n"); + goto out; + } + + ret = regmap_read_poll_timeout(st->regmap, AION_DEBUG_REG, + regval, (regval & debug_msk) == debug_msk, 100, 10000); + if (ret) { + dev_err(dev, "BSYNC not ready\n"); + goto out; + } + + val = lower_32_bits(-1 * adf4030_phase); + val2 = upper_32_bits(-1 * adf4030_phase); + + ret = iio_write_channel_attribute(st->iio_adf4030, val, val2, IIO_CHAN_INFO_PHASE); + if (ret) { + dev_err(dev, "Failed to set phase (ret=%d)\n", ret); + goto out; + } + + ret = regmap_clear_bits(st->regmap, AION_CONTROL_REG, + AION_CONTROL_DISABLE_INTERNAL_BSYNC_MASK); + if (ret) { + dev_err(dev, "Failed to disable internal BSYNC\n"); + goto out; + } + + ret = regmap_set_bits(st->regmap, AION_CONTROL_REG, AION_CONTROL_TRIG_CHANNEL_ENABLE_MASK); + if (ret) { + dev_err(dev, "Failed to enable trigger channels\n"); + return ret; + } + + ret = regmap_set_bits(st->regmap, AION_CONTROL_REG, AION_CONTROL_TRIG_SELECT); + if (ret) { + dev_err(dev, "Failed to select trigger channel\n"); + return ret; + } + + for (i = 0; i < ARRAY_SIZE(st->trigX_phase); i++) { + ret = regmap_write(st->regmap, AION_TRIG_CH0_PHASE_REG + (i * 4), + st->trigX_phase[i]); + if (ret) + return ret; + } + + return JESD204_STATE_CHANGE_DONE; +out: + /* + * At this point we try put the HW in a sane way but there's no point in + * checking for errors. + */ + regmap_set_bits(st->regmap, AION_CONTROL_REG, + AION_CONTROL_BSYNC_DIRECTION_MASK); + + regmap_clear_bits(st->regmap, AION_CONTROL_REG, + AION_CONTROL_DISABLE_INTERNAL_BSYNC_MASK); + + axi_aion_iio_write_channel_ext_info(st->iio_adf4030, "output_enable", 1); + + return ret; +} + +static const struct jesd204_dev_data axi_aion_jesd204_data = { + .state_ops = { + [JESD204_OP_LINK_SUPPORTED] = { + .per_link = axi_aion_jesd204_link_supported, + }, + + [JESD204_OP_OPT_SETUP_STAGE1] = { + .per_device = axi_aion_jesd204_opt_setup_stage1, + .mode = JESD204_STATE_OP_MODE_PER_DEVICE, + }, + }, +}; + +static const struct regmap_config axi_aion_regmap_config = { + .val_bits = 32, + .reg_bits = 32, + .reg_stride = 4, + .max_register = 0x1000, +}; + +static int axi_aion_iio_probe(struct platform_device *pdev) +{ + struct iio_dev *indio_dev; + struct axi_aion_state *st; + void __iomem *base; + const unsigned int *expected_ver; + u32 ver; + int ret; + + indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*st)); + if (!indio_dev) + return -ENOMEM; + + st = iio_priv(indio_dev); + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + st->regmap = devm_regmap_init_mmio(&pdev->dev, base, &axi_aion_regmap_config); + if (IS_ERR(st->regmap)) + return PTR_ERR(st->regmap); + + st->dev_clk = devm_clk_get_enabled(&pdev->dev, "device_clk"); + if (IS_ERR(st->dev_clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(st->dev_clk), "failed to get clock\n"); + + st->jdev = devm_jesd204_dev_register(&pdev->dev, &axi_aion_jesd204_data); + if (IS_ERR(st->jdev)) + return dev_err_probe(&pdev->dev, PTR_ERR(st->jdev), + "failed to register JESD204 device\n"); + + st->iio_adf4030 = devm_fwnode_iio_channel_get_by_name(&pdev->dev, + dev_fwnode(&pdev->dev), "bsync"); + + if (IS_ERR(st->iio_adf4030) && PTR_ERR(st->iio_adf4030) != -ENOENT) + return dev_err_probe(&pdev->dev, PTR_ERR(st->iio_adf4030), + "bsync: error getting channel\n"); + + dev_set_drvdata(&pdev->dev, indio_dev); + + ret = devm_mutex_init(&pdev->dev, &st->lock); + if (ret) + return ret; + + indio_dev->name = AXI_AION_IIO_DRIVER_NAME; + indio_dev->info = &axi_aion_iio_info; + indio_dev->modes = INDIO_DIRECT_MODE; + indio_dev->channels = axi_aion_iio_channels; + indio_dev->num_channels = ARRAY_SIZE(axi_aion_iio_channels); + + expected_ver = device_get_match_data(&pdev->dev); + if (!expected_ver) + return -ENODEV; + + ret = regmap_set_bits(st->regmap, AION_CONTROL_REG, AION_CONTROL_SW_RESET); + if (ret) + return ret; + + ret = regmap_read(st->regmap, ADI_AXI_REG_VERSION, &ver); + if (ret) + return ret; + + if (*expected_ver > ver) { + dev_err(&pdev->dev, + "IP core version is too old. Expected %d.%.2d.%c, Reported %d.%.2d.%c\n", + ADI_AXI_PCORE_VER_MAJOR(*expected_ver), + ADI_AXI_PCORE_VER_MINOR(*expected_ver), + ADI_AXI_PCORE_VER_PATCH(*expected_ver), ADI_AXI_PCORE_VER_MAJOR(ver), + ADI_AXI_PCORE_VER_MINOR(ver), ADI_AXI_PCORE_VER_PATCH(ver)); + return -ENODEV; + } + + ret = devm_iio_device_register(&pdev->dev, indio_dev); + if (ret) + return ret; + + st_global = st; + + debugfs_create_file_unsafe("enable_debug_trig", 0600, + iio_get_debugfs_dentry(indio_dev), indio_dev, + &axi_aion_enable_debug_trig_fops); + + debugfs_create_file_unsafe("debug_trig", 0600, + iio_get_debugfs_dentry(indio_dev), indio_dev, + &axi_aion_debug_trig_fops); + + ret = devm_jesd204_fsm_start(&pdev->dev, st->jdev, JESD204_LINKS_ALL); + if (ret) + return dev_err_probe(&pdev->dev, ret, + "Failed to start JESD204 FSM\n"); + + dev_info(&pdev->dev, "AXI AION IP core (%d.%.2d.%c) probed\n", ADI_AXI_PCORE_VER_MAJOR(ver), + ADI_AXI_PCORE_VER_MINOR(ver), ADI_AXI_PCORE_VER_PATCH(ver)); + + return 0; +} + +static unsigned int axi_aion_1_0_a_info = ADI_AXI_PCORE_VER(1, 0, 'a'); + +static const struct of_device_id axi_aion_iio_of_match[] = { + { .compatible = "adi,axi-aion-trig-1.0.a", + .data = &axi_aion_1_0_a_info }, + {} +}; +MODULE_DEVICE_TABLE(of, axi_aion_iio_of_match); + +static struct platform_driver axi_aion_iio_driver = { + .driver = { + .name = AXI_AION_IIO_DRIVER_NAME, + .of_match_table = axi_aion_iio_of_match, + }, + .probe = axi_aion_iio_probe, +}; +module_platform_driver(axi_aion_iio_driver); + +MODULE_AUTHOR("Michael Hennerich "); +MODULE_DESCRIPTION("AXI AION IIO Platform Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/iio/trx-rf/Kconfig b/drivers/iio/trx-rf/Kconfig new file mode 100644 index 00000000000000..63c91750d60ff1 --- /dev/null +++ b/drivers/iio/trx-rf/Kconfig @@ -0,0 +1,17 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# RF Transceivers and Advanced Mixed Signal Frontends drivers +# +menu "RF Transceivers and Advanced Mixed Signal Frontends" + +config AD9088 + tristate "Analog Devices AD9088 and similar Mixed Signal Front End (MxFE)" + depends on SPI + select CF_AXI_ADC + select ADI_AXI_HSCI + help + Say yes here to build support for Analog Devices: + AD9088, AD9084 mixed signal front end (MxFE). + Provides direct access via sysfs. + +endmenu diff --git a/drivers/iio/trx-rf/Makefile b/drivers/iio/trx-rf/Makefile new file mode 100644 index 00000000000000..1d3f5373d42aee --- /dev/null +++ b/drivers/iio/trx-rf/Makefile @@ -0,0 +1,7 @@ +# SPDX-License-Identifier: GPL-2.0-only +# +# Makefile for TRX-RF IIO drivers +# +# When adding new entries keep the list in alphabetical order + +obj-$(CONFIG_AD9088) += ad9088/ diff --git a/drivers/iio/trx-rf/ad9088/CAL_DATA_README.md b/drivers/iio/trx-rf/ad9088/CAL_DATA_README.md new file mode 100644 index 00000000000000..fd42c7ebe6c9ef --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/CAL_DATA_README.md @@ -0,0 +1,317 @@ +# AD9088 Calibration Data Save/Restore + +## Overview + +The AD9088 driver provides a comprehensive calibration data management system that allows you to save and restore calibration data across power cycles. This is useful for: + +- Reducing boot time by skipping calibration +- Maintaining consistent performance across reboots +- Factory calibration persistence +- Backup and restore of device calibration + +## File Format + +The calibration data is stored in a binary format with the following structure: + +### Header (64 bytes) +- **Magic** (4 bytes): 0x41443930 ("AD90") - File identification +- **Version** (4 bytes): Format version (currently 1) +- **Chip ID** (4 bytes): Device chip ID (0x9084 or 0x9088) +- **Device Config** (4 bytes): 8T8R vs 4T4R configuration +- **Section Offsets** (16 bytes): Offsets to each calibration section +- **Section Sizes** (16 bytes): Size of each calibration section +- **Reserved** (16 bytes): For future use + +### Calibration Sections + +1. **ADC Calibration Data** + - Sequential mode data for all ADCs + - Random mode data for all ADCs + - Each ADC has its own calibration data with embedded CRC + +2. **DAC Calibration Data** + - Calibration data for all DACs + - Each DAC has its own calibration data with embedded CRC + +3. **SERDES RX Calibration Data** + - Calibration data for all SERDES RX 12-packs + - Each SERDES has its own calibration data with embedded CRC + +4. **SERDES TX Calibration Data** + - Calibration data for all SERDES TX 12-packs + - Each SERDES has its own calibration data with embedded CRC + +### Footer +- **CRC32** (4 bytes): Checksum of entire file (excluding CRC itself) + +## Usage + +### Sysfs Interface + +The calibration data is accessible via a sysfs bin attribute: + +``` +/sys/bus/spi/devices/spi0.0/iio:device0/calibration_data +``` + +### Saving Calibration Data + +After the device has been initialized and calibrated, save the calibration data: + +```bash +# Read calibration data from device and save to file +cat /sys/bus/spi/devices/spi0.0/iio:device0/calibration_data > /lib/firmware/ad9088_cal.bin + +# Verify the file was created +ls -lh /lib/firmware/ad9088_cal.bin +``` + +The save operation will: +1. Read all ADC calibration data (sequential and random modes) +2. Read all DAC calibration data +3. Read all SERDES RX calibration data +4. Read all SERDES TX calibration data +5. Build a binary file with header and CRC32 +6. Return the complete calibration image + +Typical calibration data size: +- **4T4R**: ~50-100 KB +- **8T8R**: ~100-200 KB + +### Restoring Calibration Data + +To restore calibration data from a previously saved file: + +```bash +# Write calibration data back to device +cat /lib/firmware/ad9088_cal.bin > /sys/bus/spi/devices/spi0.0/iio:device0/calibration_data +``` + +The restore operation will: +1. Validate magic number and file format version +2. Verify chip ID matches current device +3. Verify device configuration (4T4R/8T8R) matches +4. Validate CRC32 of entire file +5. Restore ADC calibration data +6. Restore DAC calibration data +7. Restore SERDES RX calibration data +8. Restore SERDES TX calibration data + +### Complete Workflow + +Here's the recommended workflow for using automatic calibration restore: + +#### First Boot (Capture Calibration) + +1. **Boot without calibration restore** (don't add device tree property yet): + ```bash + # Device boots and performs full calibration (takes longer) + ``` + +2. **Save calibration data**: + ```bash + cat /sys/bus/spi/devices/spi0.0/iio:device0/calibration_data > /lib/firmware/ad9088_cal.bin + ``` + +3. **Verify the saved data**: + ```bash + ls -lh /lib/firmware/ad9088_cal.bin + # Should show file size (typically 50-200KB depending on configuration) + ``` + +4. **Test restore** (optional but recommended): + ```bash + # Write the calibration data back to verify it works + cat /lib/firmware/ad9088_cal.bin > /sys/bus/spi/devices/spi0.0/iio:device0/calibration_data + # Check dmesg for "Calibration data restored successfully" + ``` + +5. **Update device tree** to enable automatic restore: + ```dts + adi,device-calibration-data-name = "ad9088_cal.bin"; + ``` + +6. **Rebuild and deploy** device tree + +#### Subsequent Boots + +On subsequent boots, the driver will: +- Automatically load `/lib/firmware/ad9088_cal.bin` +- Restore calibration data to hardware +- Skip time-consuming calibration procedures +- Boot faster while maintaining performance + +### Automatic Restore on Boot (Alternative Methods) + +If you don't want to use device tree integration, you can use a systemd service or init script: + +#### Systemd Service + +Create `/etc/systemd/system/ad9088-cal-restore.service`: + +```ini +[Unit] +Description=Restore AD9088 Calibration Data +After=multi-user.target +Requires=multi-user.target + +[Service] +Type=oneshot +ExecStart=/bin/sh -c 'if [ -f /lib/firmware/ad9088_cal.bin ]; then cat /lib/firmware/ad9088_cal.bin > /sys/bus/spi/devices/spi0.0/iio:device0/calibration_data; fi' +RemainAfterExit=true + +[Install] +WantedBy=multi-user.target +``` + +Enable the service: + +```bash +systemctl enable ad9088-cal-restore.service +systemctl start ad9088-cal-restore.service +``` + +#### Init Script + +Add to your init script (e.g., `/etc/rc.local`): + +```bash +# Restore AD9088 calibration data if available +if [ -f /lib/firmware/ad9088_cal.bin ]; then + cat /lib/firmware/ad9088_cal.bin > /sys/bus/spi/devices/spi0.0/iio:device0/calibration_data +fi +``` + +## Error Handling + +### Save Errors + +If saving fails, check: +- Device is properly initialized +- Initial calibration has completed +- Sufficient memory is available + +### Restore Errors + +Common errors and solutions: + +| Error | Cause | Solution | +|-------|-------|----------| +| Invalid magic | Wrong file format | Use file saved by this driver | +| Version mismatch | Incompatible format version | Re-save calibration data with current driver | +| Chip ID mismatch | File from different device | Use calibration data from same chip type | +| Config mismatch | 4T4R vs 8T8R mismatch | Use calibration data from same device config | +| CRC error | File corruption | Re-save calibration data | +| Size mismatch | Truncated file | Check file was completely written | + +## Best Practices + +1. **Save After Initial Calibration**: Save calibration data immediately after successful initial calibration + +2. **Verify Saved Data**: Always verify the saved file can be restored before relying on it: + ```bash + # Save + cat /sys/bus/spi/devices/spi0.0/iio:device0/calibration_data > /tmp/test_cal.bin + + # Restore and verify no errors + cat /tmp/test_cal.bin > /sys/bus/spi/devices/spi0.0/iio:device0/calibration_data + ``` + +3. **Keep Backups**: Maintain multiple calibration backups: + ```bash + # Timestamped backup + cat /sys/bus/spi/devices/spi0.0/iio:device0/calibration_data > \ + /lib/firmware/ad9088_cal_$(date +%Y%m%d_%H%M%S).bin + ``` + +4. **Temperature Considerations**: Calibration data is temperature-dependent. Consider: + - Saving calibration at operating temperature + - Re-calibrating if temperature changes significantly + - Maintaining separate calibration files for different temperature ranges + +5. **Version Control**: Track calibration data with device information: + ```bash + # Create metadata file + echo "Chip ID: $(dmesg | grep AD9088 | grep 'Chip ID')" > /lib/firmware/ad9088_cal.txt + echo "Date: $(date)" >> /lib/firmware/ad9088_cal.txt + echo "Temperature: $(cat /sys/class/hwmon/hwmon0/temp1_input)" >> /lib/firmware/ad9088_cal.txt + ``` + +## Integration with Device Tree + +The calibration restore can be integrated with device initialization to automatically load calibration data during driver probe. This eliminates the need for manual systemd services or init scripts. + +### Automatic Calibration Load at Boot + +Add the calibration firmware property to your device tree: + +```dts +&spi0 { + ad9088@0 { + compatible = "adi,ad9088"; + reg = <0>; + spi-max-frequency = <10000000>; + + /* Automatically load calibration data from firmware at boot */ + adi,device-calibration-data-name = "ad9088_cal.bin"; + }; +}; +``` + +When this property is present, the driver will: +1. Request the firmware file from `/lib/firmware/` during probe +2. Validate the calibration data (magic, version, chip ID, CRC) +3. Restore the calibration data to hardware +4. Continue with normal device initialization + +If the property is not present, the driver will skip calibration restore and perform normal initialization with full calibration. + +**Important Notes:** +- The calibration file must be placed in `/lib/firmware/` before boot +- If the file is missing or invalid, driver probe will fail +- This happens automatically after firmware load but before any other hardware configuration +- The calibration data must match the device (same chip ID and 4T4R/8T8R configuration) + +## Debugging + +Enable debug output: + +```bash +# Enable driver debug messages +echo 8 > /proc/sys/kernel/printk +echo 'file ad9088_cal.c +p' > /sys/kernel/debug/dynamic_debug/control + +# Check kernel messages +dmesg | grep -i "calibration\|ad9088" +``` + +Example successful save output: +``` +ad9088 spi0.0: Saving calibration data... +ad9088 spi0.0: Reading ADC calibration data... +ad9088 spi0.0: Reading DAC calibration data... +ad9088 spi0.0: Reading SERDES RX calibration data... +ad9088 spi0.0: Reading SERDES TX calibration data... +ad9088 spi0.0: Calibration data saved: 102400 bytes (ADC: 51200, DAC: 25600, SERDES RX: 12800, SERDES TX: 12800) +``` + +Example successful restore output: +``` +ad9088 spi0.0: Restoring calibration data... +ad9088 spi0.0: Restoring ADC calibration data... +ad9088 spi0.0: Restoring DAC calibration data... +ad9088 spi0.0: Restoring SERDES RX calibration data... +ad9088 spi0.0: Restoring SERDES TX calibration data... +ad9088 spi0.0: Calibration data restored successfully +``` + +## File Format Changes + +If the file format needs to be updated in the future, the version field in the header will be incremented. The driver will reject files with unsupported versions to prevent corruption. + +## Security Considerations + +- The calibration_data sysfs attribute has 0600 permissions (root read/write only) +- Calibration data is device-specific and cannot be shared between different chip instances +- CRC32 validation ensures data integrity +- No sensitive information is stored in calibration data diff --git a/drivers/iio/trx-rf/ad9088/Makefile b/drivers/iio/trx-rf/ad9088/Makefile new file mode 100644 index 00000000000000..e5981fd046f3cb --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/Makefile @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: GPL-2.0 + +ad9088_drv-y = ad9088.o +ad9088_drv-y += ad9088_dt.o ad9088_fft.o ad9088_jesd204_fsm.o ad9088_mcs.o ad9088_ffh.o ad9088_bmem.o ad9088_cal.o +ad9088_drv-$(CONFIG_DEBUG_FS) += ad9088_debugfs.o +ad9088_drv-y += public/src/adi_apollo_adc.o +ad9088_drv-y += public/src/adi_apollo_dac.o +ad9088_drv-y += public/src/adi_apollo_fddc.o +ad9088_drv-y += public/src/adi_apollo_trigts.o +ad9088_drv-y += public/src/adi_apollo_hal_regio_hsci.o +ad9088_drv-y += public/src/adi_apollo_serdes.o +ad9088_drv-y += public/src/adi_apollo_rx.o +ad9088_drv-y += public/src/adi_apollo_arm.o +ad9088_drv-y += public/src/adi_apollo_jrx.o +ad9088_drv-y += public/src/adi_apollo_txen.o +ad9088_drv-y += public/src/adi_apollo_mailbox.o +ad9088_drv-y += public/src/adi_apollo_gpio.o +ad9088_drv-y += public/src/adi_apollo_cddc.o +ad9088_drv-y += public/src/adi_apollo_fsrc.o +ad9088_drv-y += public/src/adi_apollo_hal_regio_spi.o +ad9088_drv-y += public/src/adi_apollo_cfg.o +ad9088_drv-y += public/src/adi_apollo_dformat.o +ad9088_drv-y += public/src/adi_apollo_jtx.o +ad9088_drv-y += public/src/adi_apollo_hal.o +ad9088_drv-y += public/src/adi_apollo_mailbox_handler.o +ad9088_drv-y += public/src/adi_apollo_clk_mcs.o +ad9088_drv-y += public/src/adi_apollo_cfir.o +ad9088_drv-y += public/src/adi_apollo_fnco.o +ad9088_drv-y += public/src/adi_apollo_rxen.o +ad9088_drv-y += public/src/adi_apollo_bmem.o +ad9088_drv-y += public/src/adi_apollo_txmisc.o +ad9088_drv-y += public/src/adi_apollo_tmode.o +ad9088_drv-y += public/src/adi_apollo_reconfig.o +ad9088_drv-y += public/src/adi_apollo_device.o +ad9088_drv-y += public/src/adi_apollo_cduc.o +ad9088_drv-y += public/src/adi_apollo_txmux.o +ad9088_drv-y += public/src/adi_apollo_rxmux.o +ad9088_drv-y += public/src/adi_apollo_pfilt.o +ad9088_drv-y += public/src/adi_apollo_invsinc.o +ad9088_drv-y += public/src/adi_apollo_rxmisc.o +ad9088_drv-y += public/src/adi_apollo_sniffer.o +ad9088_drv-y += public/src/adi_apollo_sysclk_cond.o +ad9088_drv-y += public/src/adi_apollo_smon.o +ad9088_drv-y += public/src/adi_apollo_fduc.o +ad9088_drv-y += public/src/adi_apollo_tx.o +ad9088_drv-y += public/src/adi_apollo_cnco.o +ad9088_drv-y += private/src/adi_apollo_private_sysclk_cond.o +ad9088_drv-y += public/src/adi_apollo_mcs_cal.o +ad9088_drv-y += adi_utils/src/adi_utils.o +ad9088_drv-y += private/src/adi_apollo_private_bmem.o +ad9088_drv-y += private/src/adi_apollo_private_device.o +ad9088_drv-y += public/src/adi_apollo_gpio_hop.o +ad9088_drv-y += public/src/adi_apollo_loopback.o +ad9088_drv-y += public/src/adi_apollo_lb0.o +ad9088_drv-y += public/src/adi_apollo_utils.o +ad9088_drv-y += private/src/adi_apollo_private_blk_sel.o +ad9088_drv-y += public/src/adi_apollo_startup.o + +obj-$(CONFIG_AD9088) += ad9088_drv.o + +ccflags-y += -I$(src)/public/inc/ \ + -I$(src)/private/inc/ \ + -I$(src)/adi_inc/ \ + -I$(src)/adi_utils/inc/ + +ccflags-y += -DB0 -I$(src)/private/inc/bitfields/b0/ diff --git a/drivers/iio/trx-rf/ad9088/ad9088.c b/drivers/iio/trx-rf/ad9088/ad9088.c new file mode 100644 index 00000000000000..892557966d92d0 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/ad9088.c @@ -0,0 +1,5248 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Driver for AD9088 and similar mixed signal front end (MxFE®) + * + * Copyright 2022 Analog Devices Inc. + */ + +#include "linux/device.h" +#include "linux/fwnode.h" +#include "linux/property.h" +#include "linux/slab.h" +#include + +#include "ad9088.h" + +#define INDIRECT_REG_TEST_ADDR (0x60366045) +#define ARM_REG_TEST_BASE_ADDR (0x20000000U) + +static const u8 lanes_all[] = { + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, + 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 +}; + +int adi_ad9088_calc_nco_ftw(struct ad9088_phy *phy, u64 freq, s64 nco_shift, u32 div, + u32 bits, u64 *ftw, u64 *frac_a, u64 *frac_b) +{ + bool neg = false; + int ret; + u64 f_clamp = freq; + + if (!freq || !bits || bits > 48 || !ftw || !frac_a || !frac_b || !div) + return -EINVAL; + + do_div(f_clamp, div); + + dev_dbg(&phy->spi->dev, "%s: freq=%llu, nco_shift=%lld, bits=%u\n", + __func__, f_clamp, nco_shift, bits); + + nco_shift = clamp_t(int64_t, nco_shift, -(f_clamp >> 1), f_clamp >> 1); + + if (nco_shift < 0) { + nco_shift = -nco_shift; + neg = true; + } + + ret = adi_api_utils_ratio_decomposition(nco_shift * div, freq, bits, ftw, frac_a, frac_b); + if (ret) { + dev_err(&phy->spi->dev, "Error in ratio decomposition: (%d)\n", ret); + return ret; + } + + if (bits == 32 && !phy->cnco_dual_modulus_mode_en) { + *frac_a = 0; + *frac_b = 1; + } else if ((bits == 48) && !phy->fnco_dual_modulus_mode_en) { + *frac_a = 0; + *frac_b = 1; + } else if ((bits == 48) && phy->fnco_dual_modulus_mode_en) { + /* frac_a and fact_b are 24-bit registers */ + while (*frac_a >= (1 << 24) || *frac_b >= (1 << 24)) { + *frac_a >>= 1; + *frac_b >>= 1; + }; + }; + + if (neg) + *ftw = (1ULL << bits) - *ftw; + + dev_dbg(&phy->spi->dev, "%s: ftw=%llx, frac_a=%llu, frac_b=%llu\n", + __func__, *ftw, *frac_a, *frac_b); + + return API_CMS_ERROR_OK; +} + +static int adi_ad9088_calc_nco_freq(struct ad9088_phy *phy, u64 freq, u64 ftw, u32 a, u32 b, + u32 bits, s64 *nco_shift) +{ + u64 hi, lo, mod; + bool neg = false; + + dev_dbg(&phy->spi->dev, "%s: freq=%llu, ftw=%llu, a=%u, b=%u, bits=%u\n", + __func__, freq, ftw, a, b, bits); + + if (!b) + b = 1; + + if (!freq || !bits || (bits > 48) || (a > b)) + return -EINVAL; + + mod = (1ULL << bits); + + if (ftw > (mod >> 1)) { + ftw = mod - ftw; + neg = true; + } + + adi_api_utils_mult_128(freq, (ftw * 100ULL) + ((100 * a) / b), &hi, &lo); + adi_api_utils_add_128(hi, lo, 0, (mod * 100) >> 1, &hi, &lo); + adi_api_utils_div_128(hi, lo, 0, (mod * 100), &hi, nco_shift); + + if (neg) + *nco_shift *= -1; + + return API_CMS_ERROR_OK; +} + +const char *const ad9088_fsm_links_to_str[] = { + [DEFRAMER_LINK_A0_TX] = "JESD TX (JRX Deframer Link A0)", + [DEFRAMER_LINK_A1_TX] = "JESD TX (JRX Deframer Link A1)", + [DEFRAMER_LINK_B0_TX] = "JESD TX (JRX Deframer Link B0)", + [DEFRAMER_LINK_B1_TX] = "JESD TX (JRX Deframer Link B1)", + [FRAMER_LINK_A0_RX] = "JESD RX (JTX Framer Link A0)", + [FRAMER_LINK_A1_RX] = "JESD RX (JTX Framer Link A1)", + [FRAMER_LINK_B0_RX] = "JESD RX (JTX Framer Link B0)", + [FRAMER_LINK_B1_RX] = "JESD RX (JTX Framer Link B1)", +}; + +u8 ad9088_to_link(u8 linkid) +{ + u8 lut[8] = { + ADI_APOLLO_LINK_A0, ADI_APOLLO_LINK_A1, /* DEFRAMER */ + ADI_APOLLO_LINK_B0, ADI_APOLLO_LINK_B1, + ADI_APOLLO_LINK_A0, ADI_APOLLO_LINK_A1, /* FRAMER */ + ADI_APOLLO_LINK_B0, ADI_APOLLO_LINK_B1 + }; + + return lut[linkid]; +} + +static int32_t ad9088_log_write(void *user_data, int32_t log_type, const char *message, + va_list argp) +{ + struct axiadc_converter *conv = user_data; + char logMessage[160]; + + if (log_type == ADI_CMS_LOG_SPI) + return 0; + + vsnprintf(logMessage, sizeof(logMessage), message, argp); + + switch (log_type) { + case ADI_CMS_LOG_NONE: + break; + case ADI_CMS_LOG_MSG: + dev_info(&conv->spi->dev, "%s", logMessage); + break; + case ADI_CMS_LOG_WARN: + dev_warn(&conv->spi->dev, "%s", logMessage); + break; + case ADI_CMS_LOG_ERR: + dev_err(&conv->spi->dev, "%s", logMessage); + break; + case ADI_CMS_LOG_SPI: + dev_dbg(&conv->spi->dev, "%s", logMessage); + break; + case ADI_CMS_LOG_API: + dev_dbg(&conv->spi->dev, "%s", logMessage); + break; + case ADI_CMS_LOG_ALL: + pr_notice("%s", logMessage); + break; + } + + return 0; +} + +/** + * @brief Get a human-readable string for a CMS error code + * @param error_code The error code to look up + * @return Pointer to a constant string describing the error + */ +static const char *adi_cms_error_to_string(int error_code) +{ + switch (error_code) { + case API_CMS_ERROR_OK: + return "No Error"; + case API_CMS_ERROR_ERROR: + return "General Error"; + case API_CMS_ERROR_NULL_PARAM: + return "Null parameter"; + case API_CMS_ERROR_OVERFLOW: + return "General overflow"; + case API_CMS_ERROR_DIV_BY_ZERO: + return "Divide by zero"; + case API_CMS_ERROR_FEAT_LOCKOUT: + return "Device feature is locked out"; + case API_CMS_ERROR_SPI_SDO: + return "Wrong value assigned to the SDO in device structure"; + case API_CMS_ERROR_INVALID_HANDLE_PTR: + return "Device handler pointer is invalid"; + case API_CMS_ERROR_INVALID_XFER_PTR: + return "Invalid pointer to the SPI write or read function assigned"; + case API_CMS_ERROR_INVALID_DELAYUS_PTR: + return "Invalid pointer to the delay_us function assigned"; + case API_CMS_ERROR_INVALID_PARAM: + return "Invalid parameter passed"; + case API_CMS_ERROR_INVALID_RESET_CTRL_PTR: + return "Invalid pointer to the reset control function assigned"; + case API_CMS_ERROR_NOT_SUPPORTED: + return "Not supported"; + case API_CMS_ERROR_INVALID_MASK_SELECT: + return "Invalid bitmask select parameter passed"; + case API_CMS_ERROR_IN_REF_STATUS: + return "The Input Reference Signal is not available"; + case API_CMS_ERROR_VCO_OUT_OF_RANGE: + return "The VCO is out of range"; + case API_CMS_ERROR_PLL_NOT_LOCKED: + return "PLL is not locked"; + case API_CMS_ERROR_DLL_NOT_LOCKED: + return "DLL is not locked"; + case API_CMS_ERROR_MODE_NOT_IN_TABLE: + return "JESD Mode not in table"; + case API_CMS_ERROR_CLK_CKT: + return "Clock circuit error"; + case API_CMS_ERROR_FTW_LOAD_ACK: + return "FTW acknowledge not received"; + case API_CMS_ERROR_NCO_NOT_ENABLED: + return "The NCO is not enabled"; + case API_CMS_ERROR_INIT_SEQ_FAIL: + return "Initialization sequence failed"; + case API_CMS_ERROR_TEST_FAILED: + return "Test failed"; + case API_CMS_ERROR_SPI_XFER: + return "SPI transfer error"; + case API_CMS_ERROR_TX_EN_PIN_CTRL: + return "TX enable function error"; + case API_CMS_ERROR_RESET_PIN_CTRL: + return "HW reset function error"; + case API_CMS_ERROR_EVENT_HNDL: + return "Event handling error"; + case API_CMS_ERROR_HW_OPEN: + return "HW open function error"; + case API_CMS_ERROR_HW_CLOSE: + return "HW close function error"; + case API_CMS_ERROR_LOG_OPEN: + return "Log open error"; + case API_CMS_ERROR_LOG_WRITE: + return "Log write error"; + case API_CMS_ERROR_LOG_CLOSE: + return "Log close error"; + case API_CMS_ERROR_DELAY_US: + return "Delay error"; + case API_CMS_ERROR_HSCI_LINK_UP: + return "HSCI Linkup error"; + case API_CMS_ERROR_SPI_REGIO_XFER: + return "Register transaction error spi"; + case API_CMS_ERROR_HSCI_REGIO_XFER: + return "Register transaction error hsci"; + case API_CMS_ERROR_OPERATION_TIMEOUT: + return "Operation timeout"; + case API_CMS_ERROR_LINK_DOWN: + return "JESD links down"; + case API_CMS_ERROR_FILE_OPEN: + return "File open error"; + case API_CMS_ERROR_SERDES_CAL_ERROR: + return "SERDES cal error"; + case API_CMS_ERROR_SERDES_CAL_TIMEOUT: + return "SERDES cal timeout"; + case API_CMS_ERROR_PLATFORM_READ: + return "Platform (e.g. FPGA) read error"; + case API_CMS_ERROR_PLATFORM_WRITE: + return "Platform (e.g. FPGA) write error"; + case API_CMS_ERROR_FILE_READ: + return "File read error"; + case API_CMS_ERROR_FILE_WRITE: + return "File write error"; + case API_CMS_ERROR_FILE_OPERATION: + return "General file error (e.g. seek)"; + case API_CMS_ERROR_PLATFORM_IMAGE_LOAD: + return "Error loading platform FPGA image"; + case API_CMS_ERROR_NOT_IMPLEMENTED: + return "Feature not currently implemented"; + case API_CMS_ERROR_STRUCT_UNPOPULATED: + return "Struct not populated"; + case API_CMS_ERROR_PROTOCOL_OP_NOT_SUPPORTED: + return "Protocol not supported for operation"; + case API_CMS_ERROR_INVALID_CLK_OR_REF_PARAM: + return "Invalid clock or reference parameter"; + case API_CMS_ERROR_MEM_ALLOC: + return "Memory allocation error"; + case API_CMS_ERROR_MMAP: + return "Memory mapping error"; + case API_CMS_ERROR_DEV_MEM_OPEN: + return "Device memory open error"; + case API_CMS_ERROR_I2C_ERROR: + return "I2C General Error"; + case API_CMS_ERROR_I2C_WRITE: + return "I2C Write Operation Failed"; + case API_CMS_ERROR_I2C_READ: + return "I2C Read Operation Failed"; + case API_CMS_ERROR_I2C_BUSY: + return "I2C controller or device is busy"; + case API_CMS_ERROR_PMOD_NVM_LOCK: + return "A fault occurred while accessing the Power Module's NVM"; + case API_CMS_ERROR_EC_RAM_LOCK_ERROR: + return "EC ram-lock error"; + case API_CMS_ERROR_PROFILE_CRC: + return "Profile CRC invalid"; + case API_CMS_ERROR_MAILBOX_RESP_STATUS: + return "Mailbox Command Response Status Error"; + case API_CMS_ERROR_MCS_CAL_CONFIG_ERROR: + return "MCS Cal Configuration related error"; + case API_CMS_ERROR_MCS_INIT_CAL_ERROR: + return "MCS Init Cal related error"; + case API_CMS_ERROR_MCS_TRACK_CAL_ERROR: + return "MCS Tracking Cal related error"; + case API_CMS_ERROR_MCS_CAL_TIMEOUT: + return "MCS Cal run or status check response timed out error"; + case API_CMS_ERROR_ADC_INIT_CAL_ERROR: + return "ADC Init Cal related error"; + case API_CMS_ERROR_ADC_TRACK_CAL_ERROR: + return "ADC Tracking Cal related error"; + case API_CMS_ERROR_ADC_CAL_TIMEOUT: + return "ADC Cal run or status check response timed out error"; + case API_CMS_ERROR_BAD_STATE: + return "Device is not in appropriate state to perform operation"; + case API_CMS_ERROR_STARTUP_FW_RDY_FOR_PROFILE_ERROR: + return "FW did not reach ready for profile config state"; + case API_CMS_ERROR_STARTUP_FW_MAILBOX_RDY_ERROR: + return "FW did not reach mailbox ready state"; + case API_CMS_ERROR_PLATFORM_CAPTURE_INVALID_CONFIG: + return "Invalid platform capture configuration"; + default: + return "Unknown error code"; + } +} + +/** + * @brief Convert CMS API error code to Linux errno value + * @param api_error The CMS API error code + * @return Corresponding Linux errno value (positive) + * @note Returns the absolute value suitable for setting errno or returning -errno + */ +static int adi_cms_error_to_errno(int api_error) +{ + /* Success case */ + if (api_error == API_CMS_ERROR_OK) + return 0; + + switch (api_error) { + /* Invalid parameter errors -> EINVAL */ + case API_CMS_ERROR_NULL_PARAM: + case API_CMS_ERROR_INVALID_PARAM: + case API_CMS_ERROR_INVALID_MASK_SELECT: + case API_CMS_ERROR_INVALID_CLK_OR_REF_PARAM: + case API_CMS_ERROR_PLATFORM_CAPTURE_INVALID_CONFIG: + return -EINVAL; + + /* Invalid pointer/handle errors -> EINVAL */ + case API_CMS_ERROR_INVALID_HANDLE_PTR: + case API_CMS_ERROR_INVALID_XFER_PTR: + case API_CMS_ERROR_INVALID_DELAYUS_PTR: + case API_CMS_ERROR_INVALID_RESET_CTRL_PTR: + return -EINVAL; + + /* Memory errors -> ENOMEM or EFAULT */ + case API_CMS_ERROR_MEM_ALLOC: + return -ENOMEM; + case API_CMS_ERROR_MMAP: + case API_CMS_ERROR_DEV_MEM_OPEN: + return -EFAULT; + + /* Overflow errors -> EOVERFLOW */ + case API_CMS_ERROR_OVERFLOW: + return -EOVERFLOW; + + /* Divide by zero -> EDOM (domain error) */ + case API_CMS_ERROR_DIV_BY_ZERO: + return -EDOM; + + /* Not supported -> ENOTSUP or EOPNOTSUPP */ + case API_CMS_ERROR_NOT_SUPPORTED: + case API_CMS_ERROR_NOT_IMPLEMENTED: + case API_CMS_ERROR_PROTOCOL_OP_NOT_SUPPORTED: + return -EOPNOTSUPP; + + /* Device busy/locked -> EBUSY */ + case API_CMS_ERROR_FEAT_LOCKOUT: + case API_CMS_ERROR_I2C_BUSY: + case API_CMS_ERROR_EC_RAM_LOCK_ERROR: + case API_CMS_ERROR_PMOD_NVM_LOCK: + return -EBUSY; + + /* Timeout errors -> ETIMEDOUT */ + case API_CMS_ERROR_OPERATION_TIMEOUT: + case API_CMS_ERROR_SERDES_CAL_TIMEOUT: + case API_CMS_ERROR_MCS_CAL_TIMEOUT: + case API_CMS_ERROR_ADC_CAL_TIMEOUT: + return -ETIMEDOUT; + + /* File operation errors -> appropriate file errno */ + case API_CMS_ERROR_FILE_OPEN: + return -ENOENT; + + /* Hardware errors -> EIO */ + case API_CMS_ERROR_TX_EN_PIN_CTRL: + case API_CMS_ERROR_RESET_PIN_CTRL: + case API_CMS_ERROR_HW_OPEN: + case API_CMS_ERROR_HW_CLOSE: + case API_CMS_ERROR_PLATFORM_READ: + case API_CMS_ERROR_PLATFORM_WRITE: + case API_CMS_ERROR_PLATFORM_IMAGE_LOAD: + return -EIO; + + /* Communication/link errors -> ECOMM or ENOTCONN */ + case API_CMS_ERROR_HSCI_LINK_UP: + case API_CMS_ERROR_HSCI_REGIO_XFER: + case API_CMS_ERROR_LINK_DOWN: + return -ENOTCONN; + + /* Hardware not ready errors -> EAGAIN */ + case API_CMS_ERROR_IN_REF_STATUS: + case API_CMS_ERROR_VCO_OUT_OF_RANGE: + case API_CMS_ERROR_PLL_NOT_LOCKED: + case API_CMS_ERROR_DLL_NOT_LOCKED: + case API_CMS_ERROR_FTW_LOAD_ACK: + case API_CMS_ERROR_NCO_NOT_ENABLED: + return -EAGAIN; + + /* State/sequencing errors -> EILSEQ */ + case API_CMS_ERROR_INIT_SEQ_FAIL: + case API_CMS_ERROR_BAD_STATE: + case API_CMS_ERROR_STARTUP_FW_RDY_FOR_PROFILE_ERROR: + case API_CMS_ERROR_STARTUP_FW_MAILBOX_RDY_ERROR: + return -EILSEQ; + + /* Data integrity errors -> EBADMSG */ + case API_CMS_ERROR_PROFILE_CRC: + case API_CMS_ERROR_MAILBOX_RESP_STATUS: + return -EBADMSG; + + /* Lookup/table errors -> ENOENT */ + case API_CMS_ERROR_MODE_NOT_IN_TABLE: + return -ENOENT; + + /* Missing/unpopulated data -> ENODATA */ + case API_CMS_ERROR_STRUCT_UNPOPULATED: + return -ENODATA; + + default: + return -EIO; + } +} + +/** + * ad9088_check_apollo_error - Check and handle Apollo API return value + * @dev: Device context for error reporting + * @ret: Return value from Apollo API call + * @api_name: Name of the API for error reporting + * + * Returns: 0 on success, negative Linux error code on failure + */ +int ad9088_check_apollo_error(struct device *dev, int ret, const char *api_name) +{ + if (ret != API_CMS_ERROR_OK) { + dev_err(dev, "Apollo API call %s failed with error: %s (%d)\n", + api_name, adi_cms_error_to_string(ret), ret); + return adi_cms_error_to_errno(ret); + } + + return 0; +} + +static int ad9088_udelay(void *user_data, unsigned int us) +{ + fsleep(us); + return 0; +} + +static int ad9088_spi_xfer(void *dev_obj, uint8_t *wbuf, uint8_t *rbuf, + uint32_t len) +{ + struct axiadc_converter *conv = dev_obj; + int ret; + + struct spi_transfer t = { + .tx_buf = wbuf, + .rx_buf = rbuf, + .len = len & 0xFFFF, + }; + + ret = spi_sync_transfer(conv->spi, &t, 1); + + return ret; +} + +static int ad9088_spi_read(void *dev_obj, const uint8_t tx_data[], + u8 rx_data[], uint32_t num_tx_rx_bytes, + adi_apollo_hal_txn_config_t *txn_config) +{ + struct axiadc_converter *conv = dev_obj; + int ret; + + struct spi_transfer t = { + .tx_buf = tx_data, + .rx_buf = rx_data, + .len = num_tx_rx_bytes, + }; + + ret = spi_sync_transfer(conv->spi, &t, 1); + + return ret; +} + +static int ad9088_spi_write(void *dev_obj, const uint8_t tx_data[], + u32 num_tx_bytes, adi_apollo_hal_txn_config_t *txn_config) +{ + struct axiadc_converter *conv = dev_obj; + int ret; + + struct spi_transfer t = { + .tx_buf = tx_data, + .rx_buf = NULL, + .len = num_tx_bytes, + }; + + ret = spi_sync_transfer(conv->spi, &t, 1); + + return ret; +} + +static int ad9088_reset_pin_ctrl(void *user_data, u8 enable) +{ + struct axiadc_converter *conv = user_data; + + return gpiod_direction_output(conv->reset_gpio, enable); +} + +void ad9088_print_link_phase(struct ad9088_phy *phy, + struct jesd204_link *lnk) +{ + adi_apollo_device_t *device = &phy->ad9088; + u8 id = ad9088_to_link(lnk->link_id); + u16 jrx_phase_diff; + + adi_apollo_jrx_phase_diff_get(device, id, &jrx_phase_diff); + dev_info(&phy->spi->dev, "%s Phase Difference %d\n", + ad9088_fsm_links_to_str[lnk->link_id], jrx_phase_diff); +} + +void ad9088_print_sysref_phase(struct ad9088_phy *phy) +{ + adi_apollo_device_t *device = &phy->ad9088; + u32 sysref_phase; + int i; + + for (i = 0; i < 5; i++) { + adi_apollo_clk_mcs_sysref_phase_get(device, &sysref_phase); + dev_info(&phy->spi->dev, "SYSREF_PHASE = %d (TRY%d)\n", + sign_extend32(sysref_phase, 9), i); + } +} + +static void ad9088_remove_swnode(void *swnode) +{ + fwnode_remove_software_node(swnode); +} + +/* + * The child label is derived from the parent one. If there is none, don't set any child + * one either. + */ +int devm_ad9088_set_child_label(struct ad9088_phy *phy, struct iio_dev *child, const char *suffix) +{ + const char *parent_label = NULL, *child_label; + struct property_entry properties[2] = { }; + struct device *dev = &phy->spi->dev; + struct fwnode_handle *swnode; + int ret; + + device_property_read_string(dev, "label", &parent_label); + if (!parent_label) + return 0; + + /* Strip common "axi-ad9084-" or "axi-ad9088-" prefix */ + if (!strncmp(parent_label, "axi-ad9084-", 11) || !strncmp(parent_label, "axi-ad9088-", 11)) + parent_label += 11; + + child_label = devm_kasprintf(dev, GFP_KERNEL, "%s-%s", parent_label, suffix); + if (!child_label) + return -ENOMEM; + + properties[0] = PROPERTY_ENTRY_STRING("label", child_label); + + swnode = fwnode_create_software_node(properties, NULL); + if (IS_ERR(swnode)) + return PTR_ERR(swnode); + + ret = devm_add_action_or_reset(dev, ad9088_remove_swnode, swnode); + if (ret) + return ret; + + device_set_node(&child->dev, swnode); + + return 0; +} + +static int ad9088_reg_access(struct iio_dev *indio_dev, unsigned int reg, + unsigned int writeval, unsigned int *readval) +{ + struct axiadc_converter *conv = iio_device_get_drvdata(indio_dev); + struct ad9088_phy *phy = conv->phy; + u8 val; + int ret; + + guard(mutex)(&phy->lock); + + if (!readval) + return adi_apollo_hal_reg_set(&phy->ad9088, reg, writeval); + + ret = adi_apollo_hal_reg_get(&phy->ad9088, reg, &val); + if (ret < 0) + return ret; + + *readval = val; + + return 0; +} + +/** + * ad9088_iiochan_to_fddc_cddc_from_profile - Map IIO channel to FDDC/CDDC/ADC/DAC using profile + * @phy: Pointer to the ad9088_phy structure + * @chan: IIO channel specification + * @fddc_num: Output - FDDC number (0-7 per side) + * @fddc_mask: Output - FDDC bitmask (ADI_APOLLO_FNCO_Ax or ADI_APOLLO_FNCO_Bx) + * @cddc_num: Output - CDDC number (0-3 per side for 8T8R, 0-1 for 4T4R) + * @cddc_mask: Output - CDDC bitmask (ADI_APOLLO_CNCO_Ax or ADI_APOLLO_CNCO_Bx) + * @adcdac_num: Output - ADC/DAC number (0-3 per side) + * @adcdac_mask: Output - ADC/DAC bitmask (ADI_APOLLO_ADC_Ax or ADI_APOLLO_DAC_Ax) + * @side: Output - Chip side (0=A, 1=B) + * + * This function derives the FDDC, CDDC, and ADC/DAC mapping from the profile's + * mux configuration rather than using hardcoded values. + * + * For RX path: + * - MUX3 (sample_xbar_sel[]) in JTX config maps each virtual converter (IIO channel) + * to its FDDC source (RX0-RX7). The enum value encodes: RXn_BAND_x_DATA_[I|Q] + * - MUX2 (mux2_fddc_input_sel[]) maps CDDC to FDDC + * - MUX0 (mux0_out_adc_sel[]) maps ADC to crossbar output (CDDC) + * + * For TX path: + * - MUX3 (sample_xbar_sel[]) in JRX config maps virtual converters to FDUCs + * - fduc_cduc_summer[] maps FDUCs to CDUCs + * - MUX0 (mux0_sel[]) maps CDUC output to DAC + * + * MUX3 sample_xbar_sel encoding for RX (adi_apollo_jesd_frm_sample_xbar_select_e): + * Value = RXn * 4 + BAND * 2 + (Q ? 1 : 0) + * FDDC = Value / 2 (strips I/Q bit) + * + * MUX2 (mux2_fddc_input_sel) 8T8R encoding (3-bit value): + * For entry[i] controlling FDDC[i] and FDDC[i+4]: + * - 0: C0->F[i], C2->F[i+4] - 1: C2->F[i], C0->F[i+4] + * - 2: C0->F[i], C0->F[i+4] - 3: C2->F[i], C2->F[i+4] + * - 4: C1->F[i], C3->F[i+4] - 5: C3->F[i], C1->F[i+4] + * - 6: C1->F[i], C1->F[i+4] - 7: C3->F[i], C3->F[i+4] + */ +static void ad9088_iiochan_to_fddc_cddc_from_profile(struct ad9088_phy *phy, + const struct iio_chan_spec *chan, u8 *fddc_num, + u32 *fddc_mask, u8 *cddc_num, u32 *cddc_mask, + u8 *adcdac_num, u32 *adcdac_mask, u8 *side) +{ + /* FDDC masks indexed by FDDC number (0-7) and side */ + static const u32 fddc_masks[ADI_APOLLO_NUM_SIDES][8] = { + { ADI_APOLLO_FDDC_A0, ADI_APOLLO_FDDC_A1, ADI_APOLLO_FDDC_A2, ADI_APOLLO_FDDC_A3, + ADI_APOLLO_FDDC_A4, ADI_APOLLO_FDDC_A5, ADI_APOLLO_FDDC_A6, ADI_APOLLO_FDDC_A7 }, + { ADI_APOLLO_FDDC_B0, ADI_APOLLO_FDDC_B1, ADI_APOLLO_FDDC_B2, ADI_APOLLO_FDDC_B3, + ADI_APOLLO_FDDC_B4, ADI_APOLLO_FDDC_B5, ADI_APOLLO_FDDC_B6, ADI_APOLLO_FDDC_B7 }, + }; + /* CDDC masks indexed by CDDC number (0-3) and side */ + static const u32 cddc_masks_all[ADI_APOLLO_NUM_SIDES][4] = { + { ADI_APOLLO_CNCO_A0, ADI_APOLLO_CNCO_A1, + ADI_APOLLO_CNCO_A2, ADI_APOLLO_CNCO_A3 }, + { ADI_APOLLO_CNCO_B0, ADI_APOLLO_CNCO_B1, + ADI_APOLLO_CNCO_B2, ADI_APOLLO_CNCO_B3 }, + }; + /* ADC masks indexed by ADC number (0-3) and side */ + static const u32 adc_masks[ADI_APOLLO_NUM_SIDES][4] = { + { ADI_APOLLO_ADC_A0, ADI_APOLLO_ADC_A1, + ADI_APOLLO_ADC_A2, ADI_APOLLO_ADC_A3 }, + { ADI_APOLLO_ADC_B0, ADI_APOLLO_ADC_B1, + ADI_APOLLO_ADC_B2, ADI_APOLLO_ADC_B3 }, + }; + /* DAC masks indexed by DAC number (0-3) and side */ + static const u32 dac_masks[ADI_APOLLO_NUM_SIDES][4] = { + { ADI_APOLLO_DAC_A0, ADI_APOLLO_DAC_A1, + ADI_APOLLO_DAC_A2, ADI_APOLLO_DAC_A3 }, + { ADI_APOLLO_DAC_B0, ADI_APOLLO_DAC_B1, + ADI_APOLLO_DAC_B2, ADI_APOLLO_DAC_B3 }, + }; + bool is_8t8r = phy->profile.profile_cfg.is_8t8r; + u8 local_side; + u8 local_fddc_num; + u8 local_cddc_num; + u8 local_adcdac_num; + + if (chan->output) { + /* TX path: Use JRX sample_xbar_sel and fduc_cduc_summer */ + const adi_apollo_jesd_rx_link_cfg_t *jrx_link; + const adi_apollo_txpath_misc_t *tx_mux; + u8 xbar_sel; + u8 fduc_bit; + int i, num_cducs; + int xbar_idx; + int m_side_a; + + /* + * For TX, IIO channel maps to virtual converter index. + * chan->address is the raw virtual converter index (M index). + * The sample_xbar_sel tells us which FDUC this converter uses. + * + * xbar_sel encoding: TXn_BAND_x_DATA_[I|Q] + * Value = TXn * 4 + BAND * 2 + (Q ? 1 : 0) + * FDUC_num = Value / 4 (for TX0-TX7) + */ + m_side_a = phy->profile.jrx[ADI_APOLLO_SIDE_IDX_A].rx_link_cfg[0].m_minus1 + 1; + xbar_idx = chan->address; /* Virtual converter index */ + + if (xbar_idx < m_side_a) { + local_side = ADI_APOLLO_SIDE_IDX_A; + jrx_link = &phy->profile.jrx[ADI_APOLLO_SIDE_IDX_A].rx_link_cfg[0]; + } else { + /* Channel is on side B */ + local_side = ADI_APOLLO_SIDE_IDX_B; + jrx_link = &phy->profile.jrx[ADI_APOLLO_SIDE_IDX_B].rx_link_cfg[0]; + xbar_idx -= m_side_a; + } + + if (xbar_idx >= ADI_APOLLO_JESD_MAX_SAMPLE_XBAR_IDXS) { + dev_err(&phy->spi->dev, + "ERROR: TX xbar_idx %d out of range", xbar_idx); + return; + } + + xbar_sel = jrx_link->sample_xbar_sel[xbar_idx]; + + dev_dbg(&phy->spi->dev, + "TX chan %d addr %lu: m_side_a=%d xbar_idx=%d xbar_sel=%d", + chan->channel, chan->address, m_side_a, xbar_idx, xbar_sel); + + /* + * Extract FDUC number from xbar_sel. + * xbar_sel encoding: TXn_BAND_x_DATA_[I|Q] + * Value = TXn * 4 + BAND * 2 + (Q ? 1 : 0) + * FDUC = xbar_sel / 2 (strips I/Q bit, keeps TXn and BAND) + * BAND_0 -> even FDUC, BAND_1 -> odd FDUC + */ + if (xbar_sel <= 31) + local_fddc_num = xbar_sel / 2; + else + local_fddc_num = 0; + + /* Now find which CDUC this FDUC feeds using fduc_cduc_summer */ + tx_mux = &phy->profile.tx_path[local_side].tx_mux_summer_xbar; + fduc_bit = 1 << local_fddc_num; + local_cddc_num = 0; + num_cducs = is_8t8r ? 4 : ADI_APOLLO_CDDCS_PER_SIDE; + + for (i = 0; i < num_cducs; i++) { + if (tx_mux->fduc_cduc_summer[i] & fduc_bit) { + local_cddc_num = i; + break; + } + } + + /* + * Determine DAC from mux0_sel. + * mux0_sel[cddc_num] tells us which DAC this CDUC output goes to. + * For 4T4R: mux0_sel values 0-1 map to DAC0-DAC1 + * For 8T8R: mux0_sel values 0-3 map to DAC0-DAC3 + */ + local_adcdac_num = tx_mux->mux0_sel[local_cddc_num] & 0x03; + } else { + /* RX path: Use JTX sample_xbar_sel and mux2_fddc_input_sel */ + const adi_apollo_jesd_tx_link_cfg_t *jtx_link; + const adi_apollo_rxpath_misc_t *rx_mux; + adi_apollo_jesd_frm_conv_xbar_select_e xbar_sel; + adi_apollo_rx_mux2_sel_e mux2_sel; + u8 fddc_idx; + bool is_upper_fddc; + int xbar_idx; + int m_side_a; + + /* + * For RX, IIO channel maps to virtual converter index. + * chan->address is the raw virtual converter index (M index). + * The sample_xbar_sel tells us which FDDC this converter uses. + */ + m_side_a = phy->profile.jtx[ADI_APOLLO_SIDE_IDX_A].tx_link_cfg[0].m_minus1 + 1; + xbar_idx = chan->address; /* Virtual converter index */ + + if (xbar_idx < m_side_a) { + local_side = ADI_APOLLO_SIDE_IDX_A; + jtx_link = &phy->profile.jtx[ADI_APOLLO_SIDE_IDX_A].tx_link_cfg[0]; + } else { + /* Channel is on side B */ + local_side = ADI_APOLLO_SIDE_IDX_B; + jtx_link = &phy->profile.jtx[ADI_APOLLO_SIDE_IDX_B].tx_link_cfg[0]; + xbar_idx -= m_side_a; + } + + if (xbar_idx >= ADI_APOLLO_JESD_MAX_CONV_XBAR_IDXS) { + dev_err(&phy->spi->dev, + "ERROR: RX xbar_idx %d out of range", xbar_idx); + return; + } + + xbar_sel = jtx_link->conv_xbar_sel[xbar_idx]; + + dev_dbg(&phy->spi->dev, + "RX chan %d addr %lu: m_side_a=%d xbar_idx=%d xbar_sel=%d", + chan->channel, chan->address, m_side_a, xbar_idx, xbar_sel); + + /* + * Extract FDDC number from xbar_sel. + * xbar_sel encoding: RXn_BAND_x_DATA_[I|Q] + * Value = RXn * 4 + BAND * 2 + (Q ? 1 : 0) + * FDDC = xbar_sel / 2 (strips I/Q bit, keeps RXn and BAND) + * BAND_0 -> even FDDC, BAND_1 -> odd FDDC + * Values 32+ are ORX paths, handle separately if needed. + */ + if (xbar_sel <= ADI_APOLLO_JESD_FRM_CONVXBAR_VCONV_15) + local_fddc_num = xbar_sel / 2; + else + local_fddc_num = 0; /* Default for ORX or invalid */ + + /* Now determine CDDC from mux2_fddc_input_sel */ + rx_mux = &phy->profile.rx_path[local_side].rx_mux_splitter_xbar; + + if (is_8t8r) { + /* FDDC 0-3 are "lower", FDDC 4-7 are "upper" */ + is_upper_fddc = (local_fddc_num >= 4); + fddc_idx = is_upper_fddc ? (local_fddc_num - 4) : local_fddc_num; + } else { + is_upper_fddc = false; + fddc_idx = local_fddc_num; + } + + if (fddc_idx >= ADI_APOLLO_RX_MUX2_NUM) { + dev_err(&phy->spi->dev, + "ERROR: fddc_idx %d >= ADI_APOLLO_RX_MUX2_NUM", fddc_idx); + return; + } + + mux2_sel = rx_mux->mux2_fddc_input_sel[fddc_idx]; + + /* Decode mux2_sel to determine CDDC */ + if (is_8t8r) { + if (!is_upper_fddc) { + /* Lower FDDC (0-3) */ + switch (mux2_sel & 0x07) { + case 0: case 2: + local_cddc_num = 0; + break; + case 1: case 3: + local_cddc_num = 2; + break; + case 4: case 6: + local_cddc_num = 1; + break; + case 5: case 7: + local_cddc_num = 3; + break; + default: + local_cddc_num = 0; + break; + } + } else { + /* Upper FDDC (4-7) */ + switch (mux2_sel & 0x07) { + case 0: case 3: + local_cddc_num = 2; + break; + case 1: case 2: + local_cddc_num = 0; + break; + case 4: case 7: + local_cddc_num = 3; + break; + case 5: case 6: + local_cddc_num = 1; + break; + default: + local_cddc_num = 0; + break; + } + } + } else { + /* 4T4R: mux2_sel 0-3 = CDDC0, 4-7 = CDDC1 */ + local_cddc_num = (mux2_sel >= 4) ? 1 : 0; + } + + /* + * Determine ADC from mux0_out_adc_sel. + * mux0_out_adc_sel[cddc_num] tells us which ADC feeds this CDDC. + * For 4T4R: Values 0,1 select between ADC0 and ADC1 + * For 8T8R: Values 0-3 select ADC0-ADC3 + * + * 4T4R encoding (adi_apollo_rx_mux0_sel_e): + * CB_OUT_0: 0=ADC0, 1=ADC1 + * CB_OUT_1: 0=ADC1, 1=ADC0 + * 8T8R encoding: + * 0=ADC0, 1=ADC2, 2=ADC1, 3=ADC3 + */ + if (is_8t8r) { + /* 8T8R: mux0_out_adc_sel directly gives ADC with swapped bit encoding */ + static const u8 mux0_to_adc_8t8r[] = {0, 2, 1, 3}; + u8 mux0_val = rx_mux->mux0_out_adc_sel[local_cddc_num] & 0x03; + + local_adcdac_num = mux0_to_adc_8t8r[mux0_val]; + } else { + /* 4T4R: CB_OUT_0 and CB_OUT_1 have opposite default mappings */ + u8 mux0_val = rx_mux->mux0_out_adc_sel[local_cddc_num] & 0x01; + + if (local_cddc_num == 0) + local_adcdac_num = mux0_val; /* 0=ADC0, 1=ADC1 */ + else + local_adcdac_num = mux0_val ? 0 : 1; /* 0=ADC1, 1=ADC0 */ + } + } + + *side = local_side; + *fddc_num = local_fddc_num; + *fddc_mask = fddc_masks[local_side][local_fddc_num]; + *cddc_num = local_cddc_num; + *cddc_mask = cddc_masks_all[local_side][local_cddc_num]; + *adcdac_num = local_adcdac_num; + if (chan->output) + *adcdac_mask = dac_masks[local_side][local_adcdac_num]; + else + *adcdac_mask = adc_masks[local_side][local_adcdac_num]; + + dev_dbg(&phy->spi->dev, + "%s_voltage%d(addr=%lu): Side-%c fddc=%d(0x%04X) cddc=%d(0x%02X) %s=%d(0x%02X) (%s, mux-based)", + chan->output ? "out" : "in", chan->channel, chan->address, local_side ? 'B' : 'A', + *fddc_num, *fddc_mask, *cddc_num, *cddc_mask, + chan->output ? "dac" : "adc", *adcdac_num, *adcdac_mask, + is_8t8r ? "8T8R" : "4T4R"); + +} + +/** + * ad9088_get_chan_map - Get pre-computed channel mapping for an IIO channel + * @phy: Pointer to the ad9088_phy structure + * @chan: IIO channel specification + * + * Returns pointer to the pre-computed channel mapping structure. + * The channel maps are populated during ad9088_label_writer() which is + * called from ad9088_setup_chip_info_tbl() at probe time. + */ +const struct ad9088_chan_map *ad9088_get_chan_map(struct ad9088_phy *phy, + const struct iio_chan_spec *chan) +{ + if (chan->address >= MAX_NUM_CHANNELIZER) + return NULL; + + if (chan->output) + return &phy->tx_chan_map[chan->address]; + + return &phy->rx_chan_map[chan->address]; +} + +static void ad9088_iiochan_to_cfir(struct ad9088_phy *phy, + const struct iio_chan_spec *chan, + adi_apollo_terminal_e *terminal, + adi_apollo_cfir_sel_e *cfir_sel, + adi_apollo_cfir_dp_sel *dp_sel) +{ + const struct ad9088_chan_map *map = ad9088_get_chan_map(phy, chan); + + if (!map) { + dev_err(&phy->spi->dev, "Invalid channel address %lu", chan->address); + return; + } + + if (chan->output) + *terminal = ADI_APOLLO_TX; + else + *terminal = ADI_APOLLO_RX; + + switch (map->fddc_mask) { + case ADI_APOLLO_FDDC_A0: + *cfir_sel = ADI_APOLLO_CFIR_A0; + *dp_sel = ADI_APOLLO_CFIR_DP_0; + break; + case ADI_APOLLO_FDDC_A1: + *cfir_sel = ADI_APOLLO_CFIR_A0; + *dp_sel = ADI_APOLLO_CFIR_DP_1; + break; + case ADI_APOLLO_FDDC_A2: + *cfir_sel = ADI_APOLLO_CFIR_A1; + *dp_sel = ADI_APOLLO_CFIR_DP_0; + break; + case ADI_APOLLO_FDDC_A3: + *cfir_sel = ADI_APOLLO_CFIR_A1; + *dp_sel = ADI_APOLLO_CFIR_DP_1; + break; + case ADI_APOLLO_FDDC_B0: + *cfir_sel = ADI_APOLLO_CFIR_B0; + *dp_sel = ADI_APOLLO_CFIR_DP_0; + break; + case ADI_APOLLO_FDDC_B1: + *cfir_sel = ADI_APOLLO_CFIR_B0; + *dp_sel = ADI_APOLLO_CFIR_DP_1; + break; + case ADI_APOLLO_FDDC_B2: + *cfir_sel = ADI_APOLLO_CFIR_B1; + *dp_sel = ADI_APOLLO_CFIR_DP_0; + break; + case ADI_APOLLO_FDDC_B3: + *cfir_sel = ADI_APOLLO_CFIR_B1; + *dp_sel = ADI_APOLLO_CFIR_DP_1; + break; + default: + dev_err(&phy->spi->dev, "Unhandled FDDC number 0x%X\n", map->fddc_mask); + } + + dev_dbg(&phy->spi->dev, + "%s_voltage%d: Side-%c fddc_mask=%X terminal=%s, cfir_sel=%u dp_sel=%u\n", + chan->output ? "out" : "in", chan->channel, map->side ? 'B' : 'A', + map->fddc_mask, *terminal ? "TX" : "RX", *cfir_sel, *dp_sel); +} + +#define AD9088_MAX_CLK_NAME 79 + +static char *ad9088_clk_set_dev_name(struct ad9088_phy *phy, char *dest, + const char *name) +{ + size_t len = 0; + + if (!name) + return NULL; + + if (*name == '-') + len = strscpy(dest, dev_name(&phy->spi->dev), + AD9088_MAX_CLK_NAME); + else + *dest = '\0'; + + return strncat(dest, name, AD9088_MAX_CLK_NAME - len); +} + +static unsigned long ad9088_bb_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct ad9088_clock *clk_priv = to_clk_priv(hw); + + return clk_priv->rate; +} + +static int ad9088_bb_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct ad9088_clock *clk_priv = to_clk_priv(hw); + + clk_priv->rate = rate; + + return 0; +} + +static long ad9088_bb_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + struct ad9088_clock *clk_priv = to_clk_priv(hw); + + dev_dbg(&clk_priv->spi->dev, "%s: Rate %lu Hz", __func__, rate); + + return rate; +} + +static int ad9088_bb_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + return 0; +} + +static const struct clk_ops bb_clk_ops = { + .round_rate = ad9088_bb_round_rate, + .determine_rate = ad9088_bb_determine_rate, + .set_rate = ad9088_bb_set_rate, + .recalc_rate = ad9088_bb_recalc_rate, +}; + +static int ad9088_clk_register(struct ad9088_phy *phy, const char *name, + const char *parent_name, + const char *parent_name2, unsigned long flags, + u32 source) +{ + struct ad9088_clock *clk_priv = &phy->clk_priv[source]; + struct clk_init_data init; + struct clk *clk; + char c_name[AD9088_MAX_CLK_NAME + 1], + p_name[2][AD9088_MAX_CLK_NAME + 1]; + const char *_parent_name[2]; + + /* struct ad9088_clock assignments */ + clk_priv->source = source; + clk_priv->hw.init = &init; + clk_priv->spi = phy->spi; + clk_priv->phy = phy; + + _parent_name[0] = ad9088_clk_set_dev_name(phy, p_name[0], parent_name); + _parent_name[1] = ad9088_clk_set_dev_name(phy, p_name[1], parent_name2); + + init.name = ad9088_clk_set_dev_name(phy, c_name, name); + init.flags = flags; + init.parent_names = &_parent_name[0]; + init.num_parents = _parent_name[1] ? 2 : _parent_name[0] ? 1 : 0; + + switch (source) { + case RX_SAMPL_CLK: + case RX_SAMPL_CLK_LINK2: + init.ops = &bb_clk_ops; + break; + case TX_SAMPL_CLK: + init.ops = &bb_clk_ops; + break; + default: + return -EINVAL; + } + + of_clk_get_scale(phy->spi->dev.of_node, &name[1], + &phy->clkscale[source]); + + clk = devm_clk_register(&phy->spi->dev, &clk_priv->hw); + phy->clks[source] = clk; + + return 0; +} + +static irqreturn_t ad9088_event_handler(struct axiadc_converter *conv, + unsigned int chn) +{ + u64 event = IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, chn, + IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING); + s64 timestamp = iio_get_time_ns(conv->indio_dev); + + if (conv->indio_dev) + iio_push_event(conv->indio_dev, event, timestamp); + + return IRQ_HANDLED; +} + +static irqreturn_t ad9088_fdA_handler(int irq, void *private) +{ + return ad9088_event_handler(private, 0); +} + +static irqreturn_t ad9088_fdB_handler(int irq, void *private) +{ + return ad9088_event_handler(private, 1); +} + +static int ad9088_testmode_read(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan) +{ + struct axiadc_converter *conv = iio_device_get_drvdata(indio_dev); + + return conv->testmode[chan->channel]; +} + +static int ad9088_testmode_write(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + unsigned int item) +{ + struct axiadc_converter *conv = iio_device_get_drvdata(indio_dev); + struct ad9088_phy *phy = conv->phy; + const struct ad9088_chan_map *map = ad9088_get_chan_map(phy, chan); + adi_apollo_rx_tmode_res_e res; + int ret = 0; + + if (!map) + return -EINVAL; + + guard(mutex)(&phy->lock); + + switch (phy->profile.rx_path[map->side].rx_dformat[0].res) { + case ADI_APOLLO_RX_DFORMAT_RES_16B: + res = ADI_APOLLO_RX_TMODE_RES_16B; + break; + case ADI_APOLLO_RX_DFORMAT_RES_15B: + res = ADI_APOLLO_RX_TMODE_RES_15B; + break; + case ADI_APOLLO_RX_DFORMAT_RES_14B: + res = ADI_APOLLO_RX_TMODE_RES_14B; + break; + case ADI_APOLLO_RX_DFORMAT_RES_13B: + res = ADI_APOLLO_RX_TMODE_RES_13B; + break; + case ADI_APOLLO_RX_DFORMAT_RES_12B: + res = ADI_APOLLO_RX_TMODE_RES_12B; + break; + default: + dev_warn(&phy->spi->dev, "Unsupported tmode resolution %d\n", + phy->profile.rx_path[map->side].rx_dformat[0].res); + res = ADI_APOLLO_RX_TMODE_RES_12B; + } + + ret = adi_apollo_tmode_config_set(&phy->ad9088, + map->side ? ADI_APOLLO_LINK_B0 : ADI_APOLLO_LINK_A0, + item ? 0xFF : 0, item, res); + + if (!ret) + conv->testmode[chan->channel] = item; + + return ret; +} + +static const char *const ad9088_adc_testmodes[] = { + [ADI_APOLLO_TMODE_TYPE_SEL_NORM] = "off", + [ADI_APOLLO_TMODE_TYPE_SEL_MIDSCALE] = "midscale_short", + [ADI_APOLLO_TMODE_TYPE_SEL_POS_FS] = "pos_fullscale", + [ADI_APOLLO_TMODE_TYPE_SEL_NEG_FS] = "neg_fullscale", + [ADI_APOLLO_TMODE_TYPE_SEL_ACB] = "checkerboard", + [ADI_APOLLO_TMODE_TYPE_SEL_PN9] = "pn9", + [ADI_APOLLO_TMODE_TYPE_SEL_PN23] = "pn23", + [ADI_APOLLO_TMODE_TYPE_SEL_WT] = "one_zero_toggle", + [ADI_APOLLO_TMODE_TYPE_SEL_USR] = "user", + [ADI_APOLLO_TMODE_TYPE_SEL_PN7] = "pn7", + [ADI_APOLLO_TMODE_TYPE_SEL_PN15] = "pn15", + [ADI_APOLLO_TMODE_TYPE_SEL_PN31] = "pn31", + [ADI_APOLLO_TMODE_TYPE_SEL_RAMP] = "ramp", + [12] = "", + [13] = "", + [14] = "", +}; + +static const struct iio_enum ad9088_testmode_enum = { + .items = ad9088_adc_testmodes, + .num_items = ARRAY_SIZE(ad9088_adc_testmodes), + .set = ad9088_testmode_write, + .get = ad9088_testmode_read, +}; + +static int ad9088_iio_val_to_str(char *buf, u32 max, int val) +{ + int vals[2]; + + vals[0] = val; + vals[1] = max; + + return iio_format_value(buf, IIO_VAL_FRACTIONAL, 2, vals); +} + +static int ad9088_iio_str_to_val(const char *str, int min, int max, int *val) +{ + int ret, integer, fract; + + ret = iio_str_to_fixpoint(str, 100000, &integer, &fract); + + *val = DIV_ROUND_CLOSEST(max * (integer * 1000 + DIV_ROUND_CLOSEST(fract, 1000)), 1000); + *val = clamp(*val, min, max); + + return ret; +} + +static int ad9088_nyquist_zone_read(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan) +{ + struct axiadc_converter *conv = iio_device_get_drvdata(indio_dev); + struct ad9088_phy *phy = conv->phy; + const struct ad9088_chan_map *map = ad9088_get_chan_map(phy, chan); + u32 nz; + int ret; + + if (!map) + return -EINVAL; + + guard(mutex)(&phy->lock); + + ret = adi_apollo_adc_nyquist_zone_get(&phy->ad9088, map->adcdac_mask, &nz); + if (ret < 0) { + dev_err(&phy->spi->dev, "Error reading nyquist zone: %d\n", ret); + return -EFAULT; + } + + if (nz != 1 && nz != 2) { + dev_err(&phy->spi->dev, "Invalid nyquist zone value: %d\n", nz); + return -EINVAL; + } + + return nz - 1; +} + +static int ad9088_nyquist_zone_write(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + unsigned int item) +{ + struct axiadc_converter *conv = iio_device_get_drvdata(indio_dev); + struct ad9088_phy *phy = conv->phy; + const struct ad9088_chan_map *map = ad9088_get_chan_map(phy, chan); + + if (!map) + return -EINVAL; + + guard(mutex)(&phy->lock); + + return adi_apollo_adc_nyquist_zone_set(&phy->ad9088, map->adcdac_mask, item + 1); +} + +static const char *const ad9088_adc_nyquist_zones[] = { + [0] = "odd", + [1] = "even", +}; + +static const struct iio_enum ad9088_nyquist_zone_enum = { + .items = ad9088_adc_nyquist_zones, + .num_items = ARRAY_SIZE(ad9088_adc_nyquist_zones), + .set = ad9088_nyquist_zone_write, + .get = ad9088_nyquist_zone_read, +}; + +static int ad9088_sampling_mode_read(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan) +{ + struct axiadc_converter *conv = iio_device_get_drvdata(indio_dev); + struct ad9088_phy *phy = conv->phy; + const struct ad9088_chan_map *map = ad9088_get_chan_map(phy, chan); + adi_apollo_mailbox_resp_get_adc_slice_modes_t slice_modes; + u8 adc_idx; + int ret; + + if (!map) + return -EINVAL; + + /* Calculate ADC index: A0-A3 = 0-3, B0-B3 = 4-7 */ + adc_idx = map->side * ADI_APOLLO_ADC_PER_SIDE_NUM + map->adcdac_num; + + guard(mutex)(&phy->lock); + + ret = adi_apollo_mailbox_get_adc_slice_modes(&phy->ad9088, &slice_modes); + if (ret < 0) { + dev_err(&phy->spi->dev, "Error getting ADC slice modes: %d\n", ret); + return -EFAULT; + } + + if (slice_modes.adc_slice_mode[adc_idx] == ADI_APOLLO_ADC_MODE_DISABLED) { + dev_err(&phy->spi->dev, "ADC%c%d is disabled\n", + map->side ? 'B' : 'A', map->adcdac_num); + return -ENODEV; + } + + return slice_modes.adc_slice_mode[adc_idx]; +} + +static int ad9088_sampling_mode_write(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + unsigned int item) +{ + struct axiadc_converter *conv = iio_device_get_drvdata(indio_dev); + struct ad9088_phy *phy = conv->phy; + const struct ad9088_chan_map *map = ad9088_get_chan_map(phy, chan); + adi_apollo_mailbox_resp_get_adc_slice_modes_t slice_modes; + u8 adc_idx; + int ret; + + if (!map) + return -EINVAL; + + /* Calculate ADC index: A0-A3 = 0-3, B0-B3 = 4-7 */ + adc_idx = map->side * ADI_APOLLO_ADC_PER_SIDE_NUM + map->adcdac_num; + + guard(mutex)(&phy->lock); + + /* Check if already in the requested mode */ + ret = adi_apollo_mailbox_get_adc_slice_modes(&phy->ad9088, &slice_modes); + if (ret < 0) { + dev_err(&phy->spi->dev, "Error getting ADC slice modes: %d\n", ret); + return -EFAULT; + } + + if (slice_modes.adc_slice_mode[adc_idx] == item) + return 0; /* Already in requested mode */ + + /* Execute mode switch sequence */ + ret = adi_apollo_adc_mode_switch_prepare(&phy->ad9088, map->adcdac_mask); + if (ret < 0) { + dev_err(&phy->spi->dev, "Mode switch prepare failed: %d\n", ret); + return ret; + } + + ret = adi_apollo_adc_mode_switch_execute(&phy->ad9088, map->adcdac_mask, + ADI_APOLLO_ADC_MODE_SWITCH_BY_COMMAND); + if (ret < 0) { + dev_err(&phy->spi->dev, "Mode switch execute failed: %d\n", ret); + return ret; + } + + ret = adi_apollo_adc_mode_switch_restore(&phy->ad9088, map->adcdac_mask, 1); + if (ret < 0) { + dev_err(&phy->spi->dev, "Mode switch restore failed: %d\n", ret); + return ret; + } + + return 0; +} + +static const char *const ad9088_adc_sampling_modes[] = { + [ADI_APOLLO_ADC_MODE_RANDOM] = "random", + [ADI_APOLLO_ADC_MODE_SEQUENTIAL] = "sequential", +}; + +static const struct iio_enum ad9088_sampling_mode_enum = { + .items = ad9088_adc_sampling_modes, + .num_items = ARRAY_SIZE(ad9088_adc_sampling_modes), + .set = ad9088_sampling_mode_write, + .get = ad9088_sampling_mode_read, +}; + +/** + * Get optional channel. + * Returns 0 on success and if channel doesn't exist, or error code otherwise. + * In special, if the driver hasn't been probed yet, will return -EPROBE_DEFER. + */ +static int ad9088_iio_get_optional_channel(struct ad9088_phy *phy, struct iio_channel **chan, + const char *channel_name) +{ + long ptr_err; + + *chan = devm_fwnode_iio_channel_get_by_name(&phy->spi->dev, dev_fwnode(&phy->spi->dev), + channel_name); + ptr_err = PTR_ERR(*chan); + if (IS_ERR(*chan)) { + *chan = NULL; + if (ptr_err != -ENOENT && ptr_err != -ENODEV) + return dev_err_probe(&phy->spi->dev, ptr_err, "%s: error getting channel\n", + channel_name); + } + + return 0; +} + +static ssize_t ad9088_ext_info_read(struct iio_dev *indio_dev, + uintptr_t private, + const struct iio_chan_spec *chan, char *buf) +{ + struct axiadc_converter *conv = iio_device_get_drvdata(indio_dev); + struct ad9088_phy *phy = conv->phy; + const struct ad9088_chan_map *map = ad9088_get_chan_map(phy, chan); + long long val; + u64 range, f; + u8 enable; + int ret = -EINVAL; + u32 cddc_dcm; + adi_apollo_invsinc_inspect_t invsinc_inspect; + adi_apollo_terminal_e terminal; + adi_apollo_cfir_sel_e cfir_sel; + adi_apollo_cfir_dp_sel dp_sel; + + if (!map) + return -EINVAL; + + guard(mutex)(&phy->lock); + + switch (private) { + case CDDC_NCO_FREQ: + if (chan->output) { + f = phy->profile.dac_cfg[map->side].dac_sampling_rate_Hz; + ret = adi_ad9088_calc_nco_freq(phy, f, phy->profile.tx_path[map->side].tx_cduc[map->cddc_num].nco[0].nco_phase_inc, + phy->profile.tx_path[map->side].tx_cduc[map->cddc_num].nco[0].nco_phase_inc_frac_a, + phy->profile.tx_path[map->side].tx_cduc[map->cddc_num].nco[0].nco_phase_inc_frac_b, 32, &val); + } else { + f = phy->profile.adc_cfg[map->side].adc_sampling_rate_Hz; + ret = adi_ad9088_calc_nco_freq(phy, f, phy->profile.rx_path[map->side].rx_cddc[map->cddc_num].nco[0].nco_phase_inc, + phy->profile.rx_path[map->side].rx_cddc[map->cddc_num].nco[0].nco_phase_inc_frac_a, + phy->profile.rx_path[map->side].rx_cddc[map->cddc_num].nco[0].nco_phase_inc_frac_b, 32, &val); + } + return sysfs_emit(buf, "%lld\n", val); + case FDDC_NCO_FREQ: + if (chan->output) { + u32 cddc_dcm; + + adi_apollo_cduc_interp_bf_to_val(&phy->ad9088, phy->profile.tx_path[map->side].tx_cduc[map->cddc_num].drc_ratio, &cddc_dcm); + f = phy->profile.dac_cfg[map->side].dac_sampling_rate_Hz; + do_div(f, cddc_dcm); + + ret = adi_ad9088_calc_nco_freq(phy, f, + phy->profile.tx_path[map->side].tx_fduc[map->fddc_num].nco[0].nco_phase_inc, + phy->profile.tx_path[map->side].tx_fduc[map->fddc_num].nco[0].nco_phase_inc_frac_a, + phy->profile.tx_path[map->side].tx_fduc[map->fddc_num].nco[0].nco_phase_inc_frac_b, + 48, &val); + } else { + u32 cddc_dcm; + + adi_apollo_cddc_dcm_bf_to_val(&phy->ad9088, phy->profile.rx_path[map->side].rx_cddc[map->cddc_num].drc_ratio, &cddc_dcm); + f = phy->profile.adc_cfg[map->side].adc_sampling_rate_Hz; + do_div(f, cddc_dcm); + ret = adi_ad9088_calc_nco_freq(phy, f, + phy->profile.rx_path[map->side].rx_fddc[map->fddc_num].nco[0].nco_phase_inc, + phy->profile.rx_path[map->side].rx_fddc[map->fddc_num].nco[0].nco_phase_inc_frac_a, + phy->profile.rx_path[map->side].rx_fddc[map->fddc_num].nco[0].nco_phase_inc_frac_b, + 48, &val); + } + return sysfs_emit(buf, "%lld\n", val); + case CDDC_NCO_FREQ_AVAIL: + if (chan->output) + range = DIV_ROUND_CLOSEST_ULL(phy->profile.dac_cfg[map->side].dac_sampling_rate_Hz, 2); + else + range = DIV_ROUND_CLOSEST_ULL(phy->profile.adc_cfg[map->side].adc_sampling_rate_Hz, 2); + + return sysfs_emit(buf, "[%lld 1 %lld]\n", -1 * range, range); + case FDDC_NCO_FREQ_AVAIL: + if (chan->output) { + adi_apollo_cduc_interp_bf_to_val(&phy->ad9088, phy->profile.tx_path[map->side].tx_cduc[map->cddc_num].drc_ratio, &cddc_dcm); + f = phy->profile.dac_cfg[map->side].dac_sampling_rate_Hz; + + } else { + adi_apollo_cddc_dcm_bf_to_val(&phy->ad9088, phy->profile.rx_path[map->side].rx_cddc[map->cddc_num].drc_ratio, &cddc_dcm); + f = phy->profile.adc_cfg[map->side].adc_sampling_rate_Hz; + } + + range = DIV_ROUND_CLOSEST_ULL(f, cddc_dcm * 2); + return sysfs_emit(buf, "[%lld 1 %lld]\n", -1 * range, range); + case CDDC_NCO_PHASE: + val = phy->cnco_phase[chan->output][map->side][map->cddc_num]; + return sysfs_emit(buf, "%lld\n", val); + case FDDC_NCO_PHASE: + val = phy->fnco_phase[chan->output][map->side][map->fddc_num]; + return sysfs_emit(buf, "%lld\n", val); + case CDDC_TB1_6DB_GAIN: + ret = adi_apollo_cddc_gain_enable_get(&phy->ad9088, map->cddc_mask, + ADI_APOLLO_CDDC_GAIN_TB1, &enable); + if (ret) + return ret; + return sysfs_emit(buf, "%u\n", !!enable); + case CDDC_HB1_6DB_GAIN: + ret = adi_apollo_cddc_gain_enable_get(&phy->ad9088, map->cddc_mask, + ADI_APOLLO_CDDC_GAIN_HB1, &enable); + if (ret) + return ret; + return sysfs_emit(buf, "%u\n", !!enable); + case FDDC_6DB_GAIN: + ret = adi_apollo_fddc_gain_enable_get(&phy->ad9088, map->fddc_mask, &enable); + if (ret) + return ret; + return sysfs_emit(buf, "%u\n", !!enable); + case CDDC_TEST_TONE_EN: + val = phy->cnco_test_tone_en[chan->output][map->side][map->cddc_num]; + return sysfs_emit(buf, "%lld\n", val); + case FDDC_TEST_TONE_EN: + val = phy->fnco_test_tone_en[chan->output][map->side][map->fddc_num]; + return sysfs_emit(buf, "%lld\n", val); + case CDDC_TEST_TONE_OFFSET: + val = phy->cnco_test_tone_offset[chan->output][map->side][map->cddc_num]; + return ad9088_iio_val_to_str(buf, chan->output ? 0x1FFF : 0x7FF, val); + case FDDC_TEST_TONE_OFFSET: + val = phy->fnco_test_tone_offset[chan->output][map->side][map->fddc_num]; + return ad9088_iio_val_to_str(buf, chan->output ? 0x7FFF : 0x1FFF, val); + case TRX_CONVERTER_RATE: + if (chan->output) + val = phy->profile.dac_cfg[map->side].dac_sampling_rate_Hz; + else + val = phy->profile.adc_cfg[map->side].adc_sampling_rate_Hz; + return sysfs_emit(buf, "%lld\n", val); + case DAC_INVSINC_EN: + ret = adi_apollo_invsinc_inspect(&phy->ad9088, + ADI_APOLLO_CDUC_IDX2B(map->side, map->cddc_num), + &invsinc_inspect); + if (ret) + return ret; + return sysfs_emit(buf, "%u\n", !!invsinc_inspect.invsinc_en); + case CFIR_PROFILE_SEL: + ad9088_iiochan_to_cfir(phy, chan, &terminal, &cfir_sel, &dp_sel); + return sysfs_emit(buf, "%u\n", phy->cfir_profile[terminal][cfir_sel][dp_sel]); + case CFIR_ENABLE: + ad9088_iiochan_to_cfir(phy, chan, &terminal, &cfir_sel, &dp_sel); + return sysfs_emit(buf, "%u\n", phy->cfir_enable[terminal][cfir_sel][dp_sel]); + case BMEM_CDDC_DELAY: + return sysfs_emit(buf, "%u\n", phy->cddc_sample_delay[map->side][map->cddc_num]); + case BMEM_FDDC_DELAY: + return sysfs_emit(buf, "%u\n", phy->fddc_sample_delay[map->side][map->cddc_num]); + default: + return -EINVAL; + } +} + +static ssize_t ad9088_ext_info_write(struct iio_dev *indio_dev, + uintptr_t private, + const struct iio_chan_spec *chan, + const char *buf, size_t len) +{ + struct axiadc_converter *conv = iio_device_get_drvdata(indio_dev); + struct ad9088_phy *phy = conv->phy; + const struct ad9088_chan_map *map = ad9088_get_chan_map(phy, chan); + long long readin, fnco_phase; + bool enable; + int ret, readin_32; + s32 val32, tmp; + u32 cddc_dcm; + s64 val64; + u64 ftw, f, frac_a, frac_b; + adi_apollo_terminal_e terminal; + adi_apollo_cfir_sel_e cfir_sel; + adi_apollo_cfir_dp_sel dp_sel; + adi_apollo_fine_nco_main_pgm_t config = {}; + + if (!map) + return -EINVAL; + + guard(mutex)(&phy->lock); + + switch (private) { + case CDDC_NCO_FREQ: + ret = kstrtoll(buf, 10, &readin); + if (ret) + return ret; + + if (chan->output) + f = phy->profile.dac_cfg[map->side].dac_sampling_rate_Hz; + else + f = phy->profile.adc_cfg[map->side].adc_sampling_rate_Hz; + + ret = adi_ad9088_calc_nco_ftw(phy, f, readin, 1, 32, &ftw, &frac_a, &frac_b); + if (ret) + return ret; + + ret = adi_apollo_cnco_ftw_set(&phy->ad9088, + chan->output ? ADI_APOLLO_TX : ADI_APOLLO_RX, + map->cddc_mask, 0, 1, ftw); + if (ret) + return ret; + + ret = adi_apollo_cnco_mod_set(&phy->ad9088, + chan->output ? ADI_APOLLO_TX : ADI_APOLLO_RX, + map->cddc_mask, frac_a, frac_b); + if (ret) + return ret; + + if (chan->output) { + struct adi_apollo_txpath *tx = &phy->profile.tx_path[map->side]; + + tx->tx_cduc[map->cddc_num].nco[0].nco_phase_inc = ftw; + tx->tx_cduc[map->cddc_num].nco[0].nco_phase_inc_frac_a = frac_a; + tx->tx_cduc[map->cddc_num].nco[0].nco_phase_inc_frac_b = frac_b; + } else { + struct adi_apollo_rxpath *rx = &phy->profile.rx_path[map->side]; + + rx->rx_cddc[map->cddc_num].nco[0].nco_phase_inc = ftw; + rx->rx_cddc[map->cddc_num].nco[0].nco_phase_inc_frac_a = frac_a; + rx->rx_cddc[map->cddc_num].nco[0].nco_phase_inc_frac_b = frac_b; + } + + return len; + case FDDC_NCO_FREQ: + ret = kstrtoll(buf, 10, &readin); + if (ret) + return ret; + + if (chan->output) { + struct adi_apollo_txpath *tx = &phy->profile.tx_path[map->side]; + + adi_apollo_cduc_interp_bf_to_val(&phy->ad9088, + tx->tx_cduc[map->cddc_num].drc_ratio, + &cddc_dcm); + f = phy->profile.dac_cfg[map->side].dac_sampling_rate_Hz; + } else { + struct adi_apollo_rxpath *rx = &phy->profile.rx_path[map->side]; + + adi_apollo_cddc_dcm_bf_to_val(&phy->ad9088, + rx->rx_cddc[map->cddc_num].drc_ratio, + &cddc_dcm); + f = phy->profile.adc_cfg[map->side].adc_sampling_rate_Hz; + } + + ret = adi_ad9088_calc_nco_ftw(phy, f, readin, cddc_dcm, 48, &ftw, &frac_a, &frac_b); + if (ret) + return ret; + + fnco_phase = phy->fnco_phase[chan->output][map->side][map->fddc_num]; + config.main_phase_inc = ftw; + config.main_phase_offset = div_s64(fnco_phase * 14073748835533, 18000LL); + config.drc_phase_inc_frac_a = frac_a; + config.drc_phase_inc_frac_b = frac_b; + + ret = adi_apollo_fnco_main_pgm(&phy->ad9088, chan->output ? + ADI_APOLLO_TX : ADI_APOLLO_RX, + map->fddc_mask, &config); + if (ret) + return ret; + + if (chan->output) { + struct adi_apollo_txpath *tx = &phy->profile.tx_path[map->side]; + + tx->tx_fduc[map->fddc_num].nco[0].nco_phase_inc = ftw; + tx->tx_fduc[map->fddc_num].nco[0].nco_phase_inc_frac_a = frac_a; + tx->tx_fduc[map->fddc_num].nco[0].nco_phase_inc_frac_b = frac_b; + } else { + struct adi_apollo_rxpath *rx = &phy->profile.rx_path[map->side]; + + rx->rx_fddc[map->fddc_num].nco[0].nco_phase_inc = ftw; + rx->rx_fddc[map->fddc_num].nco[0].nco_phase_inc_frac_a = frac_a; + rx->rx_fddc[map->fddc_num].nco[0].nco_phase_inc_frac_b = frac_b; + } + + return len; + case CDDC_NCO_PHASE: + ret = kstrtoll(buf, 10, &readin); + if (ret) + return ret; + + readin = clamp(readin, -180000, 180000); + val32 = div_s64(readin * S32_MAX, 180000LL); + + ret = adi_apollo_cnco_pow_set(&phy->ad9088, + chan->output ? ADI_APOLLO_TX : ADI_APOLLO_RX, + map->cddc_mask, 0, 1, val32); + if (ret) + return ret; + + phy->cnco_phase[chan->output][map->side][map->cddc_num] = readin; + return len; + case FDDC_NCO_PHASE: + ret = kstrtoll(buf, 10, &readin); + if (ret) + return ret; + + readin = clamp(readin, -180000, 180000); + val64 = div_s64(readin * 14073748835533, 18000LL); + + ret = adi_apollo_fnco_main_phase_offset_set(&phy->ad9088, + chan->output ? + ADI_APOLLO_TX : ADI_APOLLO_RX, + map->fddc_mask, val64); + if (ret) + return ret; + + phy->fnco_phase[chan->output][map->side][map->fddc_num] = readin; + return len; + case CDDC_TB1_6DB_GAIN: + ret = kstrtobool(buf, &enable); + if (ret) + return ret; + ret = adi_apollo_cddc_gain_enable_set(&phy->ad9088, map->cddc_mask, + ADI_APOLLO_CDDC_GAIN_TB1, enable); + if (ret) + return ret; + + return len; + case CDDC_HB1_6DB_GAIN: + ret = kstrtobool(buf, &enable); + if (ret) + return ret; + ret = adi_apollo_cddc_gain_enable_set(&phy->ad9088, map->cddc_mask, + ADI_APOLLO_CDDC_GAIN_HB1, enable); + if (ret) + return ret; + + return len; + case FDDC_6DB_GAIN: + ret = kstrtobool(buf, &enable); + if (ret) + return ret; + + ret = adi_apollo_fddc_gain_enable_set(&phy->ad9088, map->fddc_mask, enable); + if (ret) + return ret; + + return len; + case CDDC_TEST_TONE_EN: + ret = kstrtobool(buf, &enable); + if (ret) + return ret; + + if (chan->output) { + struct adi_apollo_txpath *tx = &phy->profile.tx_path[map->side]; + + tmp = tx->tx_cduc[map->cddc_num].nco[0].nco_if_mode; + } else { + struct adi_apollo_rxpath *rx = &phy->profile.rx_path[map->side]; + + tmp = rx->rx_cddc[map->cddc_num].nco[0].nco_if_mode; + } + + ret = adi_apollo_cnco_mode_set(&phy->ad9088, chan->output ? + ADI_APOLLO_TX : ADI_APOLLO_RX, + map->cddc_mask, + enable ? ADI_APOLLO_MXR_TEST_MODE : tmp); + if (ret) + return ret; + + phy->cnco_test_tone_en[chan->output][map->side][map->cddc_num] = enable; + return len; + case FDDC_TEST_TONE_EN: + ret = kstrtobool(buf, &enable); + if (ret) + return ret; + + if (chan->output) { + struct adi_apollo_txpath *tx = &phy->profile.tx_path[map->side]; + + tmp = tx->tx_fduc[map->fddc_num].nco[0].nco_if_mode; + } else { + struct adi_apollo_rxpath *rx = &phy->profile.rx_path[map->side]; + + tmp = rx->rx_fddc[map->fddc_num].nco[0].nco_if_mode; + } + + ret = adi_apollo_fnco_mode_set(&phy->ad9088, chan->output ? + ADI_APOLLO_TX : ADI_APOLLO_RX, + map->fddc_mask, + enable ? ADI_APOLLO_MXR_TEST_MODE : tmp); + if (ret) + return ret; + + phy->fnco_test_tone_en[chan->output][map->side][map->fddc_num] = enable; + return len; + case CDDC_TEST_TONE_OFFSET: + ret = ad9088_iio_str_to_val(buf, 0, chan->output ? 0x1FFF : 0x7FF, &readin_32); + if (ret) + return ret; + + ret = adi_apollo_cnco_test_mode_val_set(&phy->ad9088, chan->output ? + ADI_APOLLO_TX : ADI_APOLLO_RX, + map->cddc_mask, readin_32); + if (ret) + return ret; + + phy->cnco_test_tone_offset[chan->output][map->side][map->cddc_num] = readin_32; + + return len; + case FDDC_TEST_TONE_OFFSET: + ret = ad9088_iio_str_to_val(buf, 0, chan->output ? 0x7FFF : 0x1FFF, &readin_32); + if (ret) + return ret; + + ret = adi_apollo_fnco_test_mode_val_set(&phy->ad9088, chan->output ? + ADI_APOLLO_TX : ADI_APOLLO_RX, + map->fddc_mask, readin_32); + if (ret) + return ret; + + phy->fnco_test_tone_offset[chan->output][map->side][map->fddc_num] = readin_32; + return len; + case DAC_INVSINC_EN: + ret = kstrtobool(buf, &enable); + if (ret) + return ret; + + ret = adi_apollo_tx_inv_sinc_configure(&phy->ad9088, map->side, map->cddc_num, + enable); + if (ret) + return ret; + return len; + case CFIR_PROFILE_SEL: + ret = kstrtoll(buf, 10, &readin); + if (ret) + return ret; + + ad9088_iiochan_to_cfir(phy, chan, &terminal, &cfir_sel, &dp_sel); + adi_apollo_cfir_profile_sel(&phy->ad9088, terminal, cfir_sel, dp_sel, readin); + phy->cfir_profile[terminal][cfir_sel][dp_sel] = readin; + return len; + case CFIR_ENABLE: + ret = kstrtobool(buf, &enable); + if (ret) + return ret; + ad9088_iiochan_to_cfir(phy, chan, &terminal, &cfir_sel, &dp_sel); + ret = adi_apollo_cfir_mode_enable_set(&phy->ad9088, terminal, cfir_sel, enable); + if (ret < 0) + return ret; + phy->cfir_enable[terminal][cfir_sel][dp_sel] = enable; + return len; + case BMEM_CDDC_DELAY: + if (!phy->cddc_sample_delay_en) { + dev_err(&phy->spi->dev, "adi,cddc-bmem-sample-delay-en is not set in the device tree\n"); + return -ENOTSUPP; + } + + ret = kstrtoll(buf, 10, &readin); + if (ret) + return ret; + readin = clamp_t(long long, readin, 0, 4095); + + ret = adi_apollo_bmem_cddc_delay_sample_set(&phy->ad9088, map->cddc_mask, readin); + ret = ad9088_check_apollo_error(&phy->spi->dev, ret, + "adi_apollo_bmem_cddc_delay_sample_set"); + if (ret) + return ret; + + phy->cddc_sample_delay[map->side][map->cddc_num] = readin; + return len; + case BMEM_FDDC_DELAY: + if (!phy->fddc_sample_delay_en) { + dev_err(&phy->spi->dev, "adi,fddc-bmem-sample-delay-en is not set in the device tree\n"); + return -ENOTSUPP; + } + + ret = kstrtoll(buf, 10, &readin); + if (ret) + return ret; + + readin = clamp_t(long long, readin, 0, 255); + + ret = adi_apollo_bmem_fddc_delay_sample_set(&phy->ad9088, map->fddc_mask, readin); + ret = ad9088_check_apollo_error(&phy->spi->dev, ret, + "adi_apollo_bmem_fddc_delay_sample_set"); + if (ret) + return ret; + + phy->fddc_sample_delay[map->side][map->fddc_num] = readin; + return len; + default: + return -EINVAL; + } +} + +static int ad9088_device_loopback0(struct ad9088_phy *phy, + adi_apollo_sides_e side) +{ + adi_apollo_side_select_e sides = side ? ADI_APOLLO_SIDE_B : ADI_APOLLO_SIDE_A; + adi_apollo_adc_select_e select_adc = side ? ADI_APOLLO_ADC_B_ALL : ADI_APOLLO_ADC_A_ALL; + u16 xbar[ADI_APOLLO_ADC_PER_SIDE_NUM / 2] = {ADI_APOLLO_ADC_0, ADI_APOLLO_ADC_1}; + adi_apollo_device_t *device = &phy->ad9088; + int err = API_CMS_ERROR_OK; + + err = adi_apollo_loopback_lb0_read_ptr_rst_set(device, select_adc, 2); + if (err != API_CMS_ERROR_OK) { + dev_err(&phy->spi->dev, "Error in adi_apollo_loopback_lb0_read_ptr_rst_set %d\n", + err); + return err; + } + + err = adi_apollo_loopback_lb0_write_ptr_rst_set(device, sides, 2); + if (err != API_CMS_ERROR_OK) { + dev_err(&phy->spi->dev, "Error in adi_apollo_loopback_lb0_write_ptr_rst_set %d\n", + err); + return err; + } + + err = adi_apollo_loopback_lb0_tx_xbar_set(device, sides, xbar, 2); + if (err != API_CMS_ERROR_OK) { + dev_err(&phy->spi->dev, "Error in adi_apollo_loopback_lb0_tx_xbar_set: %d\n", + err); + return err; + } + + err = adi_apollo_loopback_lb0_rx_enable_set(device, sides, 1); + if (err != API_CMS_ERROR_OK) { + dev_err(&phy->spi->dev, "Error in adi_apollo_loopback_lb0_rx_enable_set %d\n", + err); + return err; + } + + err = adi_apollo_loopback_lb0_tx_enable_set(device, select_adc, 1); + if (err != API_CMS_ERROR_OK) { + dev_err(&phy->spi->dev, "Error in adi_apollo_loopback_lb0_tx_enable_set %d\n", + err); + return err; + } + + phy->loopback_mode[side] = ADI_APOLLO_LOOPBACK_0; + return 0; +} + +static u16 ad9088_lb1_cduc_mask_get(adi_apollo_device_t *device, + adi_apollo_sides_e side) +{ + if (side == ADI_APOLLO_SIDE_IDX_B) { + if (device->dev_info.is_8t8r) + return ADI_APOLLO_CDUC_B0 | ADI_APOLLO_CDUC_B1 | + ADI_APOLLO_CDUC_B2 | ADI_APOLLO_CDUC_B3; + + return ADI_APOLLO_CDUC_B0 | ADI_APOLLO_CDUC_B1; + } + + if (device->dev_info.is_8t8r) + return ADI_APOLLO_CDUC_A0 | ADI_APOLLO_CDUC_A1 | + ADI_APOLLO_CDUC_A2 | ADI_APOLLO_CDUC_A3; + + return ADI_APOLLO_CDUC_A0 | ADI_APOLLO_CDUC_A1; +} + +static int ad9088_device_loopback1(struct ad9088_phy *phy, + adi_apollo_sides_e side) +{ + adi_apollo_side_select_e sides = side ? ADI_APOLLO_SIDE_B : ADI_APOLLO_SIDE_A; + adi_apollo_device_t *device = &phy->ad9088; + u16 lb1_cducs = ad9088_lb1_cduc_mask_get(device, side); + int err; + + err = adi_apollo_loopback_lb1_enable_set(device, sides, 1); + if (err) + return err; + + err = adi_apollo_loopback_lb1_cduc_enable_set(device, lb1_cducs, 1); + if (err) + return err; + + err = adi_apollo_loopback_lb1_blend_set(device, lb1_cducs, phy->lb1_blend[side]); + if (err) + return err; + + phy->loopback_mode[side] = ADI_APOLLO_LOOPBACK_1; + + return 0; +} + +static u16 ad9088_lb2_fduc_mask_get(adi_apollo_device_t *device, + adi_apollo_sides_e side) +{ + if (side == ADI_APOLLO_SIDE_IDX_B) { + if (device->dev_info.is_8t8r) + return ADI_APOLLO_FDUC_B_ALL; + return ADI_APOLLO_FDUC_B_ALL_4T4R; + } + + if (device->dev_info.is_8t8r) + return ADI_APOLLO_FDUC_A_ALL; + + return ADI_APOLLO_FDUC_A_ALL_4T4R; +} + +static int ad9088_device_loopback2(struct ad9088_phy *phy, + adi_apollo_sides_e side) +{ + adi_apollo_side_select_e sides = side ? ADI_APOLLO_SIDE_B : ADI_APOLLO_SIDE_A; + adi_apollo_device_t *device = &phy->ad9088; + u16 lb2_fducs = ad9088_lb2_fduc_mask_get(device, side); + int err; + + err = adi_apollo_loopback_lb2_enable_set(device, sides, 1); + if (err != API_CMS_ERROR_OK) + return err; + + err = adi_apollo_loopback_lb2_fduc_enable_set(device, lb2_fducs, 1); + if (err != API_CMS_ERROR_OK) + return err; + + phy->loopback_mode[side] = ADI_APOLLO_LOOPBACK_2; + + return 0; +} + +static int ad9088_device_loopback3(struct ad9088_phy *phy, + adi_apollo_sides_e side) +{ + adi_apollo_side_select_e sides = side ? ADI_APOLLO_SIDE_B : ADI_APOLLO_SIDE_A; + adi_apollo_device_t *device = &phy->ad9088; + int err; + + err = adi_apollo_loopback_jesd_enable_set(device, sides, 1); + if (err != API_CMS_ERROR_OK) + return err; + + phy->loopback_mode[side] = ADI_APOLLO_LOOPBACK_3; + + return err; +} + +static int ad9088_device_loopback_disable(struct ad9088_phy *phy, + adi_apollo_sides_e side) +{ + adi_apollo_adc_select_e select_adc = side ? ADI_APOLLO_ADC_B_ALL : ADI_APOLLO_ADC_A_ALL; + adi_apollo_side_select_e sides = side ? ADI_APOLLO_SIDE_B : ADI_APOLLO_SIDE_A; + adi_apollo_device_t *device = &phy->ad9088; + u16 lb1_cducs = ad9088_lb1_cduc_mask_get(device, side); + u16 lb2_fducs = ad9088_lb2_fduc_mask_get(device, side); + struct device *dev = &phy->spi->dev; + int err; + + switch (phy->loopback_mode[side]) { + case ADI_APOLLO_LOOPBACK_0: + err = adi_apollo_loopback_lb0_tx_enable_set(device, select_adc, 0); + if (err != API_CMS_ERROR_OK) { + dev_err(dev, "Error in adi_apollo_loopback_lb0_tx_enable_set %d\n", err); + return err; + } + + err = adi_apollo_loopback_lb0_rx_enable_set(device, sides, 0); + if (err != API_CMS_ERROR_OK) { + dev_err(dev, "Error in adi_apollo_loopback_lb0_rx_enable_set %d\n", err); + return err; + } + break; + case ADI_APOLLO_LOOPBACK_1: + err = adi_apollo_loopback_lb1_cduc_enable_set(device, lb1_cducs, 0); + if (err != API_CMS_ERROR_OK) { + dev_err(dev, "Error adi_apollo_loopback_lb1_cduc_enable_set %d\n", err); + return err; + } + + err = adi_apollo_loopback_lb1_enable_set(device, sides, 0); + if (err != API_CMS_ERROR_OK) { + dev_err(dev, "Error in adi_apollo_loopback_lb1_enable_set %d\n", err); + return err; + } + + err = adi_apollo_loopback_lb1_blend_set(device, lb1_cducs, + ADI_APOLLO_LB1_BLEND_DISABLE); + if (err != API_CMS_ERROR_OK) { + dev_err(dev, "Error adi_apollo_loopback_lb1_blend_set %d\n", err); + return err; + } + break; + case ADI_APOLLO_LOOPBACK_2: + err = adi_apollo_loopback_lb2_enable_set(device, sides, 0); + if (err != API_CMS_ERROR_OK) { + dev_err(dev, "Error in adi_apollo_loopback_lb2_enable_set %d\n", err); + return err; + } + + err = adi_apollo_loopback_lb2_fduc_enable_set(device, lb2_fducs, 0); + if (err != API_CMS_ERROR_OK) { + dev_err(dev, "Error in adi_apollo_loopback_lb2_fduc_enable_set %d\n", err); + return err; + } + break; + case ADI_APOLLO_LOOPBACK_3: + err = adi_apollo_loopback_jesd_enable_set(device, sides, 0); + if (err != API_CMS_ERROR_OK) { + dev_err(dev, "Error in adi_apollo_loopback_jesd_enable_set %d\n", err); + return err; + } + break; + } + + phy->loopback_mode[side] = ADI_APOLLO_LOOPBACK_NONE; + return 0; +} + +static int ad9088_assert_fs(struct ad9088_phy *phy, u8 side) +{ + u64 dac_fs = phy->profile.dac_cfg[side].dac_sampling_rate_Hz; + u64 adc_fs = phy->profile.adc_cfg[side].adc_sampling_rate_Hz; + + if (dac_fs != adc_fs) + return -EINVAL; + + return 0; +} + +static int ad9088_loopback_mode_read(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan) +{ + struct axiadc_converter *conv = iio_device_get_drvdata(indio_dev); + struct ad9088_phy *phy = conv->phy; + const struct ad9088_chan_map *map = ad9088_get_chan_map(phy, chan); + + if (!map) + return -EINVAL; + + return phy->loopback_mode[map->side]; +} + +static int ad9088_loopback_mode_write(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + unsigned int item) +{ + struct axiadc_converter *conv = iio_device_get_drvdata(indio_dev); + struct ad9088_phy *phy = conv->phy; + const struct ad9088_chan_map *map = ad9088_get_chan_map(phy, chan); + int ret = 0; + + if (!map) + return -EINVAL; + + guard(mutex)(&phy->lock); + + ad9088_device_loopback_disable(phy, map->side); + switch (item) { + case ADI_APOLLO_LOOPBACK_NONE: + break; + case ADI_APOLLO_LOOPBACK_0: + ret = ad9088_assert_fs(phy, map->side); + if (ret) + return ret; + ret = ad9088_device_loopback0(phy, map->side); + break; + case ADI_APOLLO_LOOPBACK_1: + ret = ad9088_device_loopback1(phy, map->side); + break; + case ADI_APOLLO_LOOPBACK_2: + ret = ad9088_device_loopback2(phy, map->side); + break; + case ADI_APOLLO_LOOPBACK_3: + ret = ad9088_device_loopback3(phy, map->side); + break; + default: + ret = -EINVAL; + } + + if (ret) + return ret; + + ret = adi_apollo_clk_mcs_dyn_sync_sequence_run(&phy->ad9088); + + return ret; +} + +static const char *const ad9088_loopback_modes[] = { + [ADI_APOLLO_LOOPBACK_NONE] = "off", + [ADI_APOLLO_LOOPBACK_0] = "loopback0", + [ADI_APOLLO_LOOPBACK_1] = "loopback1", + [ADI_APOLLO_LOOPBACK_2] = "loopback2", + [ADI_APOLLO_LOOPBACK_3] = "loopback3_jesd", +}; + +static const struct iio_enum ad9088_loopback_modes_enum = { + .items = ad9088_loopback_modes, + .num_items = ARRAY_SIZE(ad9088_loopback_modes), + .set = ad9088_loopback_mode_write, + .get = ad9088_loopback_mode_read, +}; + +static int ad9088_cnco_mixer_mode_read(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan) +{ + struct axiadc_converter *conv = iio_device_get_drvdata(indio_dev); + struct ad9088_phy *phy = conv->phy; + const struct ad9088_chan_map *map = ad9088_get_chan_map(phy, chan); + int ret, inst; + u8 mode; + + if (!map) + return -EINVAL; + + if (chan->output) + inst = calc_tx_cnco_base(map->cddc_num); + else + inst = calc_rx_cnco_base(map->cddc_num); + + ret = adi_apollo_hal_bf_get(&phy->ad9088, BF_DRC_IF_MODE_TXRX_COARSE_NCO_INFO(inst), + &mode, 1); + if (ret) + return ret; + + return mode & 0x3; +} + +static int ad9088_cnco_mixer_mode_write(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, unsigned int item) +{ + struct axiadc_converter *conv = iio_device_get_drvdata(indio_dev); + struct ad9088_phy *phy = conv->phy; + const struct ad9088_chan_map *map = ad9088_get_chan_map(phy, chan); + + if (!map) + return -EINVAL; + + guard(mutex)(&phy->lock); + + return adi_apollo_cnco_mode_set(&phy->ad9088, chan->output ? ADI_APOLLO_TX : ADI_APOLLO_RX, + map->cddc_mask, item); +} + +static int ad9088_fnco_mixer_mode_read(struct iio_dev *indio_dev, const struct iio_chan_spec *chan) +{ + struct axiadc_converter *conv = iio_device_get_drvdata(indio_dev); + struct ad9088_phy *phy = conv->phy; + const struct ad9088_chan_map *map = ad9088_get_chan_map(phy, chan); + int ret, inst; + u8 mode; + + if (!map) + return -EINVAL; + + if (chan->output) + inst = calc_tx_fnco_base(map->fddc_num); + else + inst = calc_rx_fnco_base(map->fddc_num); + + ret = adi_apollo_hal_bf_get(&phy->ad9088, BF_DRC_IF_MODE_TXRX_FINE_NCO_INFO(inst), + &mode, 1); + if (ret) + return ret; + + return mode & 0x3; +} + +static int ad9088_fnco_mixer_mode_write(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, unsigned int item) +{ + struct axiadc_converter *conv = iio_device_get_drvdata(indio_dev); + struct ad9088_phy *phy = conv->phy; + const struct ad9088_chan_map *map = ad9088_get_chan_map(phy, chan); + + if (!map) + return -EINVAL; + + guard(mutex)(&phy->lock); + + return adi_apollo_fnco_mode_set(&phy->ad9088, chan->output ? ADI_APOLLO_TX : ADI_APOLLO_RX, + map->fddc_mask, item); +} + +static const char *const ad9088_mixer_modes[] = { + [ADI_APOLLO_MXR_VAR_IF_MODE] = "var_IF", + [ADI_APOLLO_MXR_ZERO_IF_MODE] = "zero_IF", + [ADI_APOLLO_MXR_FS_BY_4_MODE] = "fs/4_IF", + [ADI_APOLLO_MXR_TEST_MODE] = "test_tone", +}; + +static const struct iio_enum ad9088_cnco_mixer_modes_enum = { + .items = ad9088_mixer_modes, + .num_items = ARRAY_SIZE(ad9088_mixer_modes), + .set = ad9088_cnco_mixer_mode_write, + .get = ad9088_cnco_mixer_mode_read, +}; + +static const struct iio_enum ad9088_fnco_mixer_modes_enum = { + .items = ad9088_mixer_modes, + .num_items = ARRAY_SIZE(ad9088_mixer_modes), + .set = ad9088_fnco_mixer_mode_write, + .get = ad9088_fnco_mixer_mode_read, +}; + +static struct iio_chan_spec_ext_info rxadc_ext_info[] = { + IIO_ENUM("main_nco_mixer_mode", IIO_SEPARATE, &ad9088_cnco_mixer_modes_enum), + IIO_ENUM_AVAILABLE("main_nco_mixer_mode", IIO_SHARED_BY_TYPE, + &ad9088_cnco_mixer_modes_enum), + IIO_ENUM("channel_nco_mixer_mode", IIO_SEPARATE, &ad9088_fnco_mixer_modes_enum), + IIO_ENUM_AVAILABLE("channel_nco_mixer_mode", IIO_SHARED_BY_TYPE, + &ad9088_fnco_mixer_modes_enum), + IIO_ENUM("test_mode", IIO_SEPARATE, &ad9088_testmode_enum), + IIO_ENUM_AVAILABLE("test_mode", IIO_SHARED_BY_TYPE, &ad9088_testmode_enum), + IIO_ENUM("loopback", IIO_SEPARATE, &ad9088_loopback_modes_enum), + IIO_ENUM_AVAILABLE("loopback", IIO_SHARED_BY_TYPE, &ad9088_loopback_modes_enum), + IIO_ENUM("nyquist_zone", IIO_SEPARATE, &ad9088_nyquist_zone_enum), + IIO_ENUM_AVAILABLE("nyquist_zone", IIO_SHARED_BY_TYPE, &ad9088_nyquist_zone_enum), + IIO_ENUM("sampling_mode", IIO_SEPARATE, &ad9088_sampling_mode_enum), + IIO_ENUM_AVAILABLE("sampling_mode", IIO_SHARED_BY_TYPE, &ad9088_sampling_mode_enum), + { + .name = "main_nco_frequency", + .read = ad9088_ext_info_read, + .write = ad9088_ext_info_write, + .shared = IIO_SEPARATE, + .private = CDDC_NCO_FREQ, + }, + { + .name = "main_nco_frequency_available", + .read = ad9088_ext_info_read, + .write = ad9088_ext_info_write, + .shared = IIO_SHARED_BY_TYPE, + .private = CDDC_NCO_FREQ_AVAIL, + }, + { + .name = "channel_nco_frequency", + .read = ad9088_ext_info_read, + .write = ad9088_ext_info_write, + .shared = IIO_SEPARATE, + .private = FDDC_NCO_FREQ, + }, + { + .name = "channel_nco_frequency_available", + .read = ad9088_ext_info_read, + .write = ad9088_ext_info_write, + .shared = IIO_SHARED_BY_TYPE, + .private = FDDC_NCO_FREQ_AVAIL, + }, + { + .name = "main_nco_phase", + .read = ad9088_ext_info_read, + .write = ad9088_ext_info_write, + .shared = IIO_SEPARATE, + .private = CDDC_NCO_PHASE, + }, + { + .name = "channel_nco_phase", + .read = ad9088_ext_info_read, + .write = ad9088_ext_info_write, + .shared = IIO_SEPARATE, + .private = FDDC_NCO_PHASE, + }, + { + .name = "main_nco_test_tone_scale", + .read = ad9088_ext_info_read, + .write = ad9088_ext_info_write, + .shared = IIO_SEPARATE, + .private = CDDC_TEST_TONE_OFFSET, + }, + { + .name = "channel_nco_test_tone_scale", + .read = ad9088_ext_info_read, + .write = ad9088_ext_info_write, + .shared = IIO_SEPARATE, + .private = FDDC_TEST_TONE_OFFSET, + }, + { + .name = "main_tb1_6db_digital_gain_en", + .read = ad9088_ext_info_read, + .write = ad9088_ext_info_write, + .shared = IIO_SEPARATE, + .private = CDDC_TB1_6DB_GAIN, + }, + { + .name = "main_hb1_6db_digital_gain_en", + .read = ad9088_ext_info_read, + .write = ad9088_ext_info_write, + .shared = IIO_SEPARATE, + .private = CDDC_HB1_6DB_GAIN, + }, + { + .name = "channel_6db_digital_gain_en", + .read = ad9088_ext_info_read, + .write = ad9088_ext_info_write, + .shared = IIO_SEPARATE, + .private = FDDC_6DB_GAIN, + }, + { + .name = "adc_frequency", + .read = ad9088_ext_info_read, + .shared = IIO_SHARED_BY_TYPE, + .private = TRX_CONVERTER_RATE, + }, + { + .name = "cfir_en", + .read = ad9088_ext_info_read, + .write = ad9088_ext_info_write, + .shared = IIO_SEPARATE, + .private = CFIR_ENABLE, + }, + { + .name = "cfir_profile_sel", + .read = ad9088_ext_info_read, + .write = ad9088_ext_info_write, + .shared = IIO_SEPARATE, + .private = CFIR_PROFILE_SEL, + }, + { + .name = "ffh_fnco_index", + .read = ad9088_ext_info_read_ffh, + .write = ad9088_ext_info_write_ffh, + .shared = IIO_SEPARATE, + .private = FFH_FNCO_INDEX, + }, + { + .name = "ffh_fnco_frequency", + .read = ad9088_ext_info_read_ffh, + .write = ad9088_ext_info_write_ffh, + .shared = IIO_SEPARATE, + .private = FFH_FNCO_FREQUENCY, + }, + { + .name = "ffh_fnco_select", + .read = ad9088_ext_info_read_ffh, + .write = ad9088_ext_info_write_ffh, + .shared = IIO_SEPARATE, + .private = FFH_FNCO_SELECT, + }, + { + .name = "ffh_fnco_mode", + .read = ad9088_ext_info_read_ffh, + .write = ad9088_ext_info_write_ffh, + .shared = IIO_SEPARATE, + .private = FFH_FNCO_MODE, + }, + { + .name = "ffh_cnco_index", + .read = ad9088_ext_info_read_ffh, + .write = ad9088_ext_info_write_ffh, + .shared = IIO_SEPARATE, + .private = FFH_CNCO_INDEX, + }, + { + .name = "ffh_cnco_frequency", + .read = ad9088_ext_info_read_ffh, + .write = ad9088_ext_info_write_ffh, + .shared = IIO_SEPARATE, + .private = FFH_CNCO_FREQUENCY, + }, + { + .name = "ffh_cnco_select", + .read = ad9088_ext_info_read_ffh, + .write = ad9088_ext_info_write_ffh, + .shared = IIO_SEPARATE, + .private = FFH_CNCO_SELECT, + }, + { + .name = "ffh_cnco_mode", + .read = ad9088_ext_info_read_ffh, + .write = ad9088_ext_info_write_ffh, + .shared = IIO_SEPARATE, + .private = FFH_CNCO_MODE, + }, + { + .name = "main_bmem_sample_delay", + .read = ad9088_ext_info_read, + .write = ad9088_ext_info_write, + .shared = IIO_SEPARATE, + .private = BMEM_CDDC_DELAY, + }, + { + .name = "channel_bmem_sample_delay", + .read = ad9088_ext_info_read, + .write = ad9088_ext_info_write, + .shared = IIO_SEPARATE, + .private = BMEM_FDDC_DELAY, + }, + { }, +}; + +static struct iio_chan_spec_ext_info txdac_ext_info[] = { + IIO_ENUM("main_nco_mixer_mode", IIO_SEPARATE, &ad9088_cnco_mixer_modes_enum), + IIO_ENUM_AVAILABLE("main_nco_mixer_mode", IIO_SHARED_BY_TYPE, + &ad9088_cnco_mixer_modes_enum), + IIO_ENUM("channel_nco_mixer_mode", IIO_SEPARATE, &ad9088_fnco_mixer_modes_enum), + IIO_ENUM_AVAILABLE("channel_nco_mixer_mode", IIO_SHARED_BY_TYPE, + &ad9088_fnco_mixer_modes_enum), + { + .name = "main_nco_frequency", + .read = ad9088_ext_info_read, + .write = ad9088_ext_info_write, + .shared = IIO_SEPARATE, + .private = CDDC_NCO_FREQ, + }, + { + .name = "main_nco_frequency_available", + .read = ad9088_ext_info_read, + .write = ad9088_ext_info_write, + .shared = IIO_SHARED_BY_TYPE, + .private = CDDC_NCO_FREQ_AVAIL, + }, + { + .name = "channel_nco_frequency", + .read = ad9088_ext_info_read, + .write = ad9088_ext_info_write, + .shared = IIO_SEPARATE, + .private = FDDC_NCO_FREQ, + }, + { + .name = "channel_nco_frequency_available", + .read = ad9088_ext_info_read, + .write = ad9088_ext_info_write, + .shared = IIO_SHARED_BY_TYPE, + .private = FDDC_NCO_FREQ_AVAIL, + }, + { + .name = "main_nco_phase", + .read = ad9088_ext_info_read, + .write = ad9088_ext_info_write, + .shared = IIO_SEPARATE, + .private = CDDC_NCO_PHASE, + }, + { + .name = "channel_nco_phase", + .read = ad9088_ext_info_read, + .write = ad9088_ext_info_write, + .shared = IIO_SEPARATE, + .private = FDDC_NCO_PHASE, + }, + { + .name = "main_nco_test_tone_en", + .read = ad9088_ext_info_read, + .write = ad9088_ext_info_write, + .shared = IIO_SEPARATE, + .private = CDDC_TEST_TONE_EN, + }, + { + .name = "channel_nco_test_tone_en", + .read = ad9088_ext_info_read, + .write = ad9088_ext_info_write, + .shared = IIO_SEPARATE, + .private = FDDC_TEST_TONE_EN, + }, + { + .name = "main_nco_test_tone_scale", + .read = ad9088_ext_info_read, + .write = ad9088_ext_info_write, + .shared = IIO_SEPARATE, + .private = CDDC_TEST_TONE_OFFSET, + }, + { + .name = "channel_nco_test_tone_scale", + .read = ad9088_ext_info_read, + .write = ad9088_ext_info_write, + .shared = IIO_SEPARATE, + .private = FDDC_TEST_TONE_OFFSET, + }, + { + .name = "dac_frequency", + .read = ad9088_ext_info_read, + .shared = IIO_SHARED_BY_TYPE, + .private = TRX_CONVERTER_RATE, + }, + { + .name = "invsinc_en", + .read = ad9088_ext_info_read, + .write = ad9088_ext_info_write, + .shared = IIO_SEPARATE, + .private = DAC_INVSINC_EN, + }, + { + .name = "cfir_en", + .read = ad9088_ext_info_read, + .write = ad9088_ext_info_write, + .shared = IIO_SEPARATE, + .private = CFIR_ENABLE, + }, + { + .name = "cfir_profile_sel", + .read = ad9088_ext_info_read, + .write = ad9088_ext_info_write, + .shared = IIO_SEPARATE, + .private = CFIR_PROFILE_SEL, + }, + { + .name = "ffh_fnco_index", + .read = ad9088_ext_info_read_ffh, + .write = ad9088_ext_info_write_ffh, + .shared = IIO_SEPARATE, + .private = FFH_FNCO_INDEX, + }, + { + .name = "ffh_fnco_frequency", + .read = ad9088_ext_info_read_ffh, + .write = ad9088_ext_info_write_ffh, + .shared = IIO_SEPARATE, + .private = FFH_FNCO_FREQUENCY, + }, + { + .name = "ffh_fnco_select", + .read = ad9088_ext_info_read_ffh, + .write = ad9088_ext_info_write_ffh, + .shared = IIO_SEPARATE, + .private = FFH_FNCO_SELECT, + }, + { + .name = "ffh_fnco_mode", + .read = ad9088_ext_info_read_ffh, + .write = ad9088_ext_info_write_ffh, + .shared = IIO_SEPARATE, + .private = FFH_FNCO_MODE, + }, + { + .name = "ffh_cnco_index", + .read = ad9088_ext_info_read_ffh, + .write = ad9088_ext_info_write_ffh, + .shared = IIO_SEPARATE, + .private = FFH_CNCO_INDEX, + }, + { + .name = "ffh_cnco_frequency", + .read = ad9088_ext_info_read_ffh, + .write = ad9088_ext_info_write_ffh, + .shared = IIO_SEPARATE, + .private = FFH_CNCO_FREQUENCY, + }, + { + .name = "ffh_cnco_select", + .read = ad9088_ext_info_read_ffh, + .write = ad9088_ext_info_write_ffh, + .shared = IIO_SEPARATE, + .private = FFH_CNCO_SELECT, + }, + { + .name = "ffh_cnco_mode", + .read = ad9088_ext_info_read_ffh, + .write = ad9088_ext_info_write_ffh, + .shared = IIO_SEPARATE, + .private = FFH_CNCO_MODE, + }, + { }, +}; + +static int ad9088_set_sample_rate(struct axiadc_converter *conv, + unsigned int sample_rate) +{ + return -ENOTSUPP; +} + +int ad9088_jesd_tx_link_status_print(struct ad9088_phy *phy, + struct jesd204_link *lnk, int retry) +{ + int ret; + u16 stat; + + do { + ret = adi_apollo_jtx_link_status_get(&phy->ad9088, + ad9088_to_link(lnk->link_id), &stat); + + if (ret) + return -EFAULT; + + if (lnk->jesd_version == JESD204_VERSION_C) { + if ((stat & 0x60) == 0x60) + ret = 0; + else + ret = -EIO; + + if (ret == 0 || retry == 0) + dev_info(&phy->spi->dev, + "%s Link%d 204C PLL %s, PHASE %s, MODE %s\n", + ad9088_fsm_links_to_str[lnk->link_id], + lnk->link_id, + stat & BIT(5) ? "locked" : "unlocked", + stat & BIT(6) ? "established" : "lost", + stat & BIT(7) ? "invalid" : "valid"); + else + msleep(20); + } else { + if ((stat & 0xF0) == 0x70) + ret = 0; + else + ret = -EIO; + + if (ret == 0 || retry == 0) + dev_info(&phy->spi->dev, + "%s Link%d 204B SYNC %s, PLL %s, PHASE %s, MODE %s, STAT 0x%X\n", + ad9088_fsm_links_to_str[lnk->link_id], + lnk->link_id, + stat & BIT(4) ? "deasserted" : "asserted", + stat & BIT(5) ? "locked" : "unlocked", + stat & BIT(6) ? "established" : "lost", + stat & BIT(7) ? "invalid" : "valid", + stat); + else + msleep(20); + } + } while (ret && retry--); + + return ret; +} + +static const char *const ad9088_jrx_204c_states[] = { + "Reset", "Undef", "Sync header alignment done", + "Extended multiblock sync complete", + "Extended multiblock alignment complete", + "Undef", "Link is good", "Undef", +}; + +int ad9088_status_show(struct seq_file *file, void *offset) +{ + struct axiadc_converter *conv = spi_get_drvdata(file->private); + struct ad9088_phy *phy = conv->phy; + adi_apollo_device_t *device = &phy->ad9088; + adi_apollo_jesd_rx_inspect_t jrx_status; + adi_apollo_jesd_tx_inspect_t jtx_status; + u16 links_to_inspect[] = { + ADI_APOLLO_LINK_A0, ADI_APOLLO_LINK_A1, + ADI_APOLLO_LINK_B0, ADI_APOLLO_LINK_B1 + }; + const char * const links_to_inspect_str[] = { "A0", "A1", "B0", "B1" }; + int l, i, ret; + u16 stat, l_stat; + + for (l = 0; l < ARRAY_SIZE(links_to_inspect); l++) { + ret = adi_apollo_jrx_link_inspect(device, links_to_inspect[l], &jrx_status); + ret = ad9088_check_apollo_error(&phy->spi->dev, ret, "adi_apollo_jrx_link_inspect"); + if (ret) + return ret; + + if (!jrx_status.np_minus1) + continue; + + seq_printf(file, "JRX ADI_APOLLO_LINK_%s: JESD204%c Subclass=%c L=%d M=%d F=%d S=%d Np=%d CS=%d link_en=%-8s\n", + links_to_inspect_str[l], + jrx_status.ver == ADI_APOLLO_JESD_204C ? 'C' : 'B', + jrx_status.subclass ? '1' : '0', + jrx_status.l_minus1 + 1, + jrx_status.m_minus1 + 1, + jrx_status.f_minus1 + 1, + jrx_status.s_minus1 + 1, + jrx_status.np_minus1 + 1, + jrx_status.cs, + jrx_status.link_en ? "Enabled" : "Disabled"); + + ret = adi_apollo_jrx_link_status_get(&phy->ad9088, links_to_inspect[l], &stat); + if (ret) + return -EFAULT; + + if (jrx_status.ver == ADI_APOLLO_JESD_204C) { + for (i = 0; i < ADI_APOLLO_JESD_MAX_LANES_PER_SIDE; i++) { + adi_apollo_jrx_j204c_lane_status_get(&phy->ad9088, + links_to_inspect[l], i, + &l_stat); + seq_printf(file, " Lane%d status: %s\n", i, + ad9088_jrx_204c_states[l_stat & 0x7]); + } + } else { + for (i = 0; i < ADI_APOLLO_JESD_MAX_LANES_PER_SIDE; i++) { + adi_apollo_jrx_j204b_lane_status_get(&phy->ad9088, + links_to_inspect[l], i, + &l_stat); + seq_printf(file, " Lane%d status: %s 0x%X\n", i, + (l_stat & 0x3C) == 0x38 ? + "Link Ready" : "Link NOT Ready", + l_stat); + } + } + + seq_printf(file, " User status: %s, SYSREF Phase: %s\n", + (stat & 0x20) ? "Ready" : "Fail", + (stat & 0x40) ? "Locked" : "Unlocked"); + } + + for (l = 0; l < ARRAY_SIZE(links_to_inspect); l++) { + ret = adi_apollo_jtx_link_inspect(device, links_to_inspect[l], &jtx_status); + ret = ad9088_check_apollo_error(&phy->spi->dev, ret, "adi_apollo_jtx_link_inspect"); + if (ret) + return ret; + + if (!jtx_status.np_minus1) + continue; + + seq_printf(file, "JTX ADI_APOLLO_LINK_%s: JESD204%c Subclass=%c L=%d M=%d F=%d S=%d Np=%d CS=%d link_en=%-8s\n", + links_to_inspect_str[l], + jtx_status.ver == ADI_APOLLO_JESD_204C ? 'C' : 'B', + jtx_status.subclass ? '1' : '0', + jtx_status.l_minus1 + 1, + jtx_status.m_minus1 + 1, + jtx_status.f_minus1 + 1, + jtx_status.s_minus1 + 1, + jtx_status.np_minus1 + 1, + jtx_status.cs, + jtx_status.link_en ? "Enabled" : "Disabled"); + + ret = adi_apollo_jtx_link_status_get(&phy->ad9088, links_to_inspect[l], &stat); + if (ret) + return -EFAULT; + + if (jtx_status.ver == ADI_APOLLO_JESD_204C) + seq_printf(file, + " PLL %s, PHASE %s, MODE %s\n", + stat & BIT(5) ? "locked" : "unlocked", + stat & BIT(6) ? "established" : "lost", + stat & BIT(7) ? "invalid" : "valid"); + else + seq_printf(file, + " SYNC %s, PLL %s, PHASE %s, MODE %s\n", + stat & BIT(4) ? "deasserted" : "asserted", + stat & BIT(5) ? "locked" : "unlocked", + stat & BIT(6) ? "established" : "lost", + stat & BIT(7) ? "invalid" : "valid"); + } + + return 0; +} + +int ad9088_jesd_rx_link_status_print(struct ad9088_phy *phy, + struct jesd204_link *lnk, int retry) +{ + int ret, i, err; + u16 stat, l_stat, mask; + u8 id = ad9088_to_link(lnk->link_id); + + do { + ret = adi_apollo_jrx_link_status_get(&phy->ad9088, id, &stat); + if (ret) + return -EFAULT; + + if (lnk->jesd_version == JESD204_VERSION_C) { + if (phy->profile.jrx[(lnk->link_id / 2) & 1].common_link_cfg.subclass) + mask = 0x60; /* Subclass 1*/ + else + mask = 0x20; /* Ignore SYSREF Phase */ + + if ((stat & mask) == mask) + ret = 0; + else + ret = -EIO; + + if (ret == 0 || retry == 0) { + for (i = 0; i < lnk->num_lanes; i++) { + u8 phys_lane = phy->profile.jrx[(lnk->link_id / 2) & 1].rx_link_cfg[(lnk->link_id % 2) & 1].lane_xbar[i]; + + err = adi_apollo_jrx_j204c_lane_status_get(&phy->ad9088, id, + phys_lane, + &l_stat); + if (err) + return -EFAULT; + if ((l_stat & 0x7) == 0x6) + dev_info(&phy->spi->dev, "%s Link%d 204C Lane-%d@%d status: %s\n", + ad9088_fsm_links_to_str[lnk->link_id], + lnk->link_id, i, phys_lane, + ad9088_jrx_204c_states[l_stat & 0x7]); + else + dev_err(&phy->spi->dev, "%s Link%d 204C Lane-%d@%d status: %s\n", + ad9088_fsm_links_to_str[lnk->link_id], + lnk->link_id, i, phys_lane, + ad9088_jrx_204c_states[l_stat & 0x7]); + } + + dev_info(&phy->spi->dev, + "%s Link%d 204C User status: %s, SYSREF Phase: %s\n", + ad9088_fsm_links_to_str[lnk->link_id], lnk->link_id, + (stat & 0x20) ? "Ready" : "Fail", + (stat & 0x40) ? "Locked" : "Unlocked"); + } else { + msleep(20); + } + } else { + if (phy->profile.jrx[(lnk->link_id / 2) & 1].common_link_cfg.subclass) + mask = 0x60; /* Subclass 1*/ + else + mask = 0x20; /* Ignore SYSREF Phase */ + + if ((stat & mask) == mask) + ret = 0; + else + ret = -EIO; + + if (ret == 0 || retry == 0) { + for (i = 0; i < lnk->num_lanes; i++) { + u8 phys_lane = phy->profile.jrx[(lnk->link_id / 2) & 1].rx_link_cfg[(lnk->link_id % 2) & 1].lane_xbar[i]; + + err = adi_apollo_jrx_j204b_lane_status_get(&phy->ad9088, + id, phys_lane, + &l_stat); + if (err) + return -EFAULT; + + if ((l_stat & 0x3C) == 0x38) + dev_info(&phy->spi->dev, "%s Link%d 204B Lane-%d@%d status: Link is good (0x%X)\n", + ad9088_fsm_links_to_str[lnk->link_id], + lnk->link_id, i, phys_lane, l_stat); + else + dev_err(&phy->spi->dev, "%s Link%d 204B Lane-%d@%d status: 0x%X Frame Sync:%s SYNC:%s DATA:%s Checksum:%s\n", + ad9088_fsm_links_to_str[lnk->link_id], + lnk->link_id, i, phys_lane, l_stat & 0x3C, + l_stat & BIT(2) ? "Lost" : "Found", + l_stat & BIT(3) ? "Ok" : "Fail", + l_stat & BIT(4) ? "Ready" : "Fail", + l_stat & BIT(5) ? "Good" : "Bad"); + } + + dev_info(&phy->spi->dev, + "%s Link%d 204B User status: %s, SYSREF Phase: %s\n", + ad9088_fsm_links_to_str[lnk->link_id], lnk->link_id, + (stat & 0x20) ? "Ready" : "Fail", + (stat & 0x40) ? "Locked" : "Unlocked"); + } else { + msleep(20); + } + } + } while (ret && retry--); + + return ret; +} + +static int ad9088_read_raw(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, int *val, + int *val2, long info) +{ + struct axiadc_converter *conv = iio_device_get_drvdata(indio_dev); + struct ad9088_phy *phy = conv->phy; + const struct ad9088_chan_map *map = ad9088_get_chan_map(phy, chan); + adi_apollo_device_tmu_data_t tmu_data; + u8 dir; + u64 freq; + int ret; + + if (!map) + return -EINVAL; + + guard(mutex)(&phy->lock); + + switch (info) { + case IIO_CHAN_INFO_SAMP_FREQ: + dir = chan->output ? TX_SAMPL_CLK : RX_SAMPL_CLK; + + if (!phy->clks[dir]) + return -ENODEV; + + freq = clk_get_rate_scaled(phy->clks[dir], &phy->clkscale[dir]); + + *val = lower_32_bits(freq); + *val2 = upper_32_bits(freq); + return IIO_VAL_INT_64; + case IIO_CHAN_INFO_ENABLE: + if (chan->output) + *val = !!(phy->tx_en_mask & map->adcdac_mask); + else + *val = !!(phy->rx_en_mask & map->adcdac_mask); + + return IIO_VAL_INT; + case IIO_CHAN_INFO_PROCESSED: + if (!phy->is_initialized) + return -EBUSY; + + ret = adi_apollo_device_tmu_get(&phy->ad9088, &tmu_data); + if (ret) + return -EFAULT; + + *val = tmu_data.temp_degrees_celsius_avg * 1000; + return IIO_VAL_INT; + } + return -EINVAL; +} + +static int ad9088_write_raw(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, int val, int val2, + long info) +{ + struct axiadc_converter *conv = iio_device_get_drvdata(indio_dev); + struct ad9088_phy *phy = conv->phy; + const struct ad9088_chan_map *map = ad9088_get_chan_map(phy, chan); + int ret; + + guard(mutex)(&phy->lock); + + switch (info) { + case IIO_CHAN_INFO_SAMP_FREQ: + if (!conv->clk) + return -ENODEV; + + if (chan->extend_name) + return -ENODEV; + + if (conv->sample_rate_read_only) + return -EPERM; + + return ad9088_set_sample_rate(conv, val); + + case IIO_CHAN_INFO_ENABLE: + + if (!map) + return -EINVAL; + + if (chan->output) { + adi_apollo_txen_pwrup_ctrl_t txen_config = { + .sm_clk_rate = ADI_APOLLO_PUC_CLK_RATE_FS_DIV_32, + .sm_en = 0, + .spi_txen = !!val, + .spi_txen_en = !!val + }; + + /* Enable Tx blocks - enable/disable via spi */ + ret = adi_apollo_txen_pwrup_ctrl_set(&phy->ad9088, map->adcdac_mask, + &txen_config); + if (ret) { + dev_err(&phy->spi->dev, "Error activating Tx blocks(%d)\n", ret); + return ret; + } + + if (val) + phy->tx_en_mask |= map->adcdac_mask; + else + phy->tx_en_mask &= ~map->adcdac_mask; + + } else { + adi_apollo_rxen_pwrup_ctrl_t rxen_config = { + .sm_clk_rate = ADI_APOLLO_PUC_CLK_RATE_FS_DIV_32, + .sm_en = 0, + .spi_rxen = !!val, + .spi_rxen_en = !!val + }; + + /* Enable Rx blocks - enable/disable via spi */ + ret = adi_apollo_rxen_pwrup_ctrl_set(&phy->ad9088, map->adcdac_mask, + &rxen_config); + if (ret) { + dev_err(&phy->spi->dev, "Error activating Rx blocks (%d)\n", ret); + return ret; + } + if (val) + phy->rx_en_mask |= map->adcdac_mask; + else + phy->rx_en_mask &= ~map->adcdac_mask; + } + break; + default: + return -EINVAL; + } + + return 0; +} + +static int ad9088_read_label(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, char *label) +{ + struct axiadc_converter *conv = iio_device_get_drvdata(indio_dev); + struct ad9088_phy *phy = conv->phy; + + return sysfs_emit(label, "%s\n", chan->output ? phy->tx_labels[chan->channel] : + phy->rx_labels[chan->channel]); +} + +static ssize_t ad9088_phy_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t len) +{ + struct iio_dev *indio_dev = dev_to_iio_dev(dev); + struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); + struct axiadc_converter *conv = iio_device_get_drvdata(indio_dev); + struct ad9088_phy *phy = conv->phy; + adi_apollo_device_t *device = &phy->ad9088; + adi_apollo_side_select_e side; + unsigned long res; + adi_apollo_sides_e side_index; + bool bres; + bool enable; + int ret = 0; + u16 addr = (u32)this_attr->address & 0xFF; + + guard(mutex)(&phy->lock); + + switch (addr) { + case AD9088_LOOPBACK1_BLEND_SIDE_A: + case AD9088_LOOPBACK1_BLEND_SIDE_B: + side = addr == AD9088_LOOPBACK1_BLEND_SIDE_B ? + ADI_APOLLO_SIDE_B : ADI_APOLLO_SIDE_A; + side_index = side == ADI_APOLLO_SIDE_A ? 0 : 1; + ret = kstrtoul(buf, 0, &res); + if (ret) + return ret; + if (res == 0x2 || res > 0x3) + return -EINVAL; + + phy->lb1_blend[side_index] = res; + if (phy->loopback_mode[side_index] == ADI_APOLLO_LOOPBACK_1) { + u16 lb1_cducs = ad9088_lb1_cduc_mask_get(device, side_index); + + ret = adi_apollo_loopback_lb1_blend_set(device, lb1_cducs, + phy->lb1_blend[side_index]); + if (ret) + return ret; + } + return len; + case AD9088_JESD204_FSM_RESUME: + if (!phy->jdev) + return -ENOTSUPP; + + ret = jesd204_fsm_resume(phy->jdev, JESD204_LINKS_ALL); + if (ret) + return ret; + + return len; + case AD9088_JESD204_FSM_CTRL: + if (!phy->jdev) + return -ENOTSUPP; + + ret = kstrtobool(buf, &enable); + if (ret) + return ret; + + if (enable) { + jesd204_fsm_stop(phy->jdev, JESD204_LINKS_ALL); + jesd204_fsm_clear_errors(phy->jdev, JESD204_LINKS_ALL); + ret = jesd204_fsm_start(phy->jdev, JESD204_LINKS_ALL); + if (ret) + return ret; + } else { + jesd204_fsm_stop(phy->jdev, JESD204_LINKS_ALL); + jesd204_fsm_clear_errors(phy->jdev, JESD204_LINKS_ALL); + } + + return len; + case AD9088_MCS_BG_TRACK_CAL_FREEZE: + ret = kstrtobool(buf, &bres); + if (ret < 0) + return ret; + + if (!phy->mcs_cal_bg_tracking_run) { + dev_err(&phy->spi->dev, "MCS BG Tracking Cal not running.\n"); + return -EFAULT; + } + + if (bres) { + ret = adi_apollo_mcs_cal_bg_tracking_freeze(device); + ret = ad9088_check_apollo_error(dev, ret, + "adi_apollo_mcs_cal_bg_tracking_freeze"); + } else { + ret = adi_apollo_mcs_cal_bg_tracking_unfreeze(device); + ret = ad9088_check_apollo_error(dev, ret, + "adi_apollo_mcs_cal_bg_tracking_unfreeze"); + } + if (ret) + return ret; + + phy->mcs_cal_bg_tracking_freeze = bres; + return len; + default: + return -EINVAL; + } +} + +static ssize_t ad9088_phy_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct iio_dev *indio_dev = dev_to_iio_dev(dev); + struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); + struct axiadc_converter *conv = iio_device_get_drvdata(indio_dev); + struct ad9088_phy *phy = conv->phy; + struct jesd204_dev *jdev = phy->jdev; + struct jesd204_link *links[4]; + int i, err, num_links; + bool paused; + int ret = 0; + + guard(mutex)(&phy->lock); + + switch ((u32)this_attr->address & 0xFF) { + case AD9088_LOOPBACK1_BLEND_SIDE_A: + return sysfs_emit(buf, "%x\n", phy->lb1_blend[0]); + case AD9088_LOOPBACK1_BLEND_SIDE_B: + return sysfs_emit(buf, "%x\n", phy->lb1_blend[1]); + case AD9088_JESD204_FSM_ERROR: + if (!phy->jdev) + return -ENOTSUPP; + + num_links = jesd204_get_active_links_num(jdev); + if (num_links < 0) + return num_links; + + ret = jesd204_get_links_data(jdev, links, num_links); + if (ret) + return ret; + + err = 0; + for (i = 0; i < num_links; i++) { + if (links[i]->error) { + err = links[i]->error; + break; + } + } + + return sysfs_emit(buf, "%d\n", err); + case AD9088_JESD204_FSM_PAUSED: + if (!phy->jdev) + return -ENOTSUPP; + + num_links = jesd204_get_active_links_num(jdev); + if (num_links < 0) + return num_links; + + ret = jesd204_get_links_data(jdev, links, num_links); + if (ret) + return ret; + /* + * Take the slowest link; if there are N links and one is + * paused, all are paused. Not sure if this can happen yet, + * but best design it like this here. + */ + paused = false; + for (i = 0; i < num_links; i++) { + if (jesd204_link_get_paused(links[i])) { + paused = true; + break; + } + } + return sysfs_emit(buf, "%d\n", paused); + case AD9088_JESD204_FSM_STATE: + if (!phy->jdev) + return -ENOTSUPP; + + num_links = jesd204_get_active_links_num(jdev); + if (num_links < 0) + return num_links; + + ret = jesd204_get_links_data(jdev, links, num_links); + if (ret) + return ret; + /* + * just get the first link state; we're assuming that all 3 + * are in sync and that AD9088_JESD204_FSM_PAUSED + * was called before + */ + return sysfs_emit(buf, "%s\n", jesd204_link_get_state_str(links[0])); + case AD9088_JESD204_FSM_CTRL: + if (!phy->jdev) + return -ENOTSUPP; + + return sysfs_emit(buf, "%d\n", phy->is_initialized); + case AD9088_MCS_BG_TRACK_CAL_FREEZE: + return sysfs_emit(buf, "%d\n", phy->mcs_cal_bg_tracking_freeze); + default: + return -EINVAL; + } +} + +static IIO_DEVICE_ATTR(loopback1_blend_side_a, 0644, + ad9088_phy_show, + ad9088_phy_store, + AD9088_LOOPBACK1_BLEND_SIDE_A); + +static IIO_DEVICE_ATTR(loopback1_blend_side_b, 0644, + ad9088_phy_show, + ad9088_phy_store, + AD9088_LOOPBACK1_BLEND_SIDE_B); + +static IIO_CONST_ATTR(loopback1_blend_available, "0 1 3"); + +static IIO_DEVICE_ATTR(jesd204_fsm_error, 0444, + ad9088_phy_show, + NULL, + AD9088_JESD204_FSM_ERROR); + +static IIO_DEVICE_ATTR(jesd204_fsm_paused, 0444, + ad9088_phy_show, + NULL, + AD9088_JESD204_FSM_PAUSED); + +static IIO_DEVICE_ATTR(jesd204_fsm_state, 0444, + ad9088_phy_show, + NULL, + AD9088_JESD204_FSM_STATE); + +static IIO_DEVICE_ATTR(jesd204_fsm_resume, 0200, + NULL, + ad9088_phy_store, + AD9088_JESD204_FSM_RESUME); + +static IIO_DEVICE_ATTR(jesd204_fsm_ctrl, 0644, + ad9088_phy_show, + ad9088_phy_store, + AD9088_JESD204_FSM_CTRL); + +static IIO_DEVICE_ATTR(mcs_bg_tacking_cal_freeze, 0644, + ad9088_phy_show, + ad9088_phy_store, + AD9088_MCS_BG_TRACK_CAL_FREEZE); + +/** + * ad9088_phy_attributes - Array of sysfs attributes for the AD9088 PHY driver + * + * This array contains the sysfs attributes that are exposed by the AD9088 PHY + * driver. These attributes allow user-space applications to interact with and + * configure various aspects of the AD9088 device. + * + * Attributes: + * - loopback1_blend_side_a: Controls the blend setting for loopback1 on side A. + * - loopback1_blend_side_b: Controls the blend setting for loopback1 on side B. + * - loopback1_blend_available: Indicates the available blend settings for loopback1. + * - jesd204_fsm_error: Reports the error status of the JESD204 finite state machine. + * - jesd204_fsm_state: Reports the current state of the JESD204 finite state machine. + * - jesd204_fsm_paused: Indicates whether the JESD204 finite state machine is paused. + * - jesd204_fsm_resume: Controls the resume operation of the JESD204 finite state machine. + * - jesd204_fsm_ctrl: Provides control over the JESD204 finite state machine. + * - mcs_bg_tacking_cal_freeze: Freezes the background tracking calibration for MCS. + */ + +static struct attribute *ad9088_phy_attributes[] = { + &iio_dev_attr_loopback1_blend_side_a.dev_attr.attr, + &iio_dev_attr_loopback1_blend_side_b.dev_attr.attr, + &iio_const_attr_loopback1_blend_available.dev_attr.attr, + &iio_dev_attr_jesd204_fsm_error.dev_attr.attr, + &iio_dev_attr_jesd204_fsm_state.dev_attr.attr, + &iio_dev_attr_jesd204_fsm_paused.dev_attr.attr, + &iio_dev_attr_jesd204_fsm_resume.dev_attr.attr, + &iio_dev_attr_jesd204_fsm_ctrl.dev_attr.attr, + &iio_dev_attr_mcs_bg_tacking_cal_freeze.dev_attr.attr, + NULL, +}; + +static const struct attribute_group ad9088_phy_attribute_group = { + .attrs = ad9088_phy_attributes, +}; + +static int ad9088_request_fd_irqs(struct axiadc_converter *conv) +{ + struct device *dev = &conv->spi->dev; + struct gpio_desc *gpio; + + gpio = devm_gpiod_get(dev, "fastdetect-a", GPIOD_IN); + if (!IS_ERR(gpio)) { + int ret, irq = gpiod_to_irq(gpio); + + if (irq < 0) + return irq; + + ret = devm_request_threaded_irq(dev, + irq, NULL, ad9088_fdA_handler, + IRQF_TRIGGER_RISING | IRQF_ONESHOT, + "fastdetect-a", conv); + if (ret < 0) + return ret; + } + + gpio = devm_gpiod_get(dev, "fastdetect-b", GPIOD_IN); + if (!IS_ERR(gpio)) { + int ret, irq = gpiod_to_irq(gpio); + + if (irq < 0) + return irq; + + ret = devm_request_threaded_irq(dev, + irq, NULL, ad9088_fdB_handler, + IRQF_TRIGGER_RISING | IRQF_ONESHOT, + "fastdetect-b", conv); + if (ret < 0) + return ret; + } + + return 0; +} + +static int ad9088_post_setup(struct iio_dev *indio_dev) +{ + struct axiadc_state *st = iio_priv(indio_dev); + struct axiadc_converter *conv = iio_device_get_drvdata(indio_dev); + int i; + + for (i = 0; i < conv->chip_info->num_channels; i++) { + axiadc_write(st, ADI_REG_CHAN_CNTRL_2(i), + (i & 1) ? 0x00004000 : 0x40000000); + axiadc_write(st, ADI_REG_CHAN_CNTRL(i), + ADI_FORMAT_SIGNEXT | ADI_FORMAT_ENABLE | + ADI_IQCOR_ENB | ADI_ENABLE); + } + + return 0; +} + +static const char *const pfir_filter_modes[] = { + "disabled", "real_n4", "real_n2", "undef", + "matrix", "undef", "complex_half", "real_n" +}; + +static const char *const pfir_selects[] = { + "pfilt_a0", "pfilt_a1", "pfilt_b0", "pfilt_b1", "pfilt_all", "pfilt_mask" +}; + +static const char *const pfir_filter_banks[] = { + "bank_0", "bank_1", "bank_2", "bank_3", "bank_all", "bank_mask" +}; + +static const char *const terminals[] = { + "rx", "tx" +}; + +static const char *const pfilt_profile_selection_mode[] = { + "direct_regmap", "direct_gpio", "direct_gpio1", "trig_regmap", "trig_gpio", "trig_gpio1" +}; + +static u32 ad9088_pfir_gain_enc(int val) +{ + switch (val) { + case 0: + return ADI_APOLLO_PFILT_GAIN_ZERO_DB; + case 6: + return ADI_APOLLO_PFILT_GAIN_POS_6_DB; + case 12: + return ADI_APOLLO_PFILT_GAIN_POS_12_DB; + case 18: + return ADI_APOLLO_PFILT_GAIN_POS_18_DB; + case 24: + return ADI_APOLLO_PFILT_GAIN_POS_24_DB; + default: + return ADI_APOLLO_PFILT_GAIN_ZERO_DB; + } +}; + +/** + * ad9088_parse_pfilt - Parse the configuration data for the PFIR filter + * @phy: Pointer to the AD9088 PHY structure + * @data: Pointer to the configuration data + * @size: Size of the configuration data + * + * This function parses the configuration data for the PFIR (Programmable + * Finite Impulse Response) filter of the AD9088 device. The configuration + * data is expected to be in a specific format, which is documented below. + * + * Format of the configuration data: + * - Each line represents a parameter or setting for the PFIR filter. + * - Lines starting with '#' are considered comments and are ignored. + * - The format for each parameter is as follows: + * - mode: + * - Sets the mode for the PFIR filter. The and values + * should be one of the predefined filter modes: "disabled", + * "real_n4", "real_n2", "undef", "matrix", "undef", "complex_half", + * "real_n". + * - gain: + * - Sets the gain values for the PFIR filter. The , , , + * and values should be integers representing the gain in dB. + * - scalar_gain: + * - Sets the scalar gain values for the PFIR filter. The , , + * , and values should be integers representing the scalar + * gain. + * - dest: + * - Sets the destination for the PFIR filter. The value + * should be either "rx" or "tx". The value should be one + * of the predefined filter selects: "pfilt_a0", "pfilt_a1", + * "pfilt_b0", "pfilt_b1", "pfilt_all", "pfilt_mask". The + * value should be one of the predefined filter banks: "bank_0", + * "bank_1", "bank_2", "bank_3", "bank_all", "bank_mask". + * - hc_delay: + * - Sets the high cut delay value for the PFIR filter. The + * value should be an unsigned 8-bit integer. + * - mode_switch_en: + * - Sets the mode switch enable value for the PFIR filter. The + * should be either 0 or 1. + * - mode_switch_add_en: + * - Sets the mode switch add enable value for the PFIR filter. The + * should be either 0 or 1. + * - real_data_mode_en: + * - Sets the real data mode enable value for the PFIR filter. The + * should be either 0 or 1. + * - quad_mode_en: + * - Sets the quad mode enable value for the PFIR filter. The + * should be either 0 or 1. + * - selection_mode: + * - Sets the profile selection mode for the PFIR filter. The + * value should be one of the predefined profile selection modes: + * "direct_regmap", "direct_gpio", "direct_gpio1", "trig_regmap", + * "trig_gpio", "trig_gpio1". + * - + * - Sets the coefficient values for the PFIR filter. The value + * should be an integer representing the coefficient value. + * + * Return: 0 on success, negative error code on failure + */ +static int ad9088_parse_pfilt(struct ad9088_phy *phy, + char *data, u32 size) +{ + struct device *dev = &phy->spi->dev; + char *line; + int i = 0, ret, j; + char *ptr = data; + u16 pfilt_coeffs[ADI_APOLLO_PFILT_COEFF_NUM]; + u32 val; + s32 sval; + + adi_apollo_terminal_e terminal; + adi_apollo_pfilt_bank_sel_e bank_sel; + adi_apollo_pfilt_sel_e pfilt_sel; + adi_apollo_pfilt_profile_sel_mode_e selection_mode; + + adi_apollo_pfilt_mode_pgm_t pfilt_mode_pgm = { 0 }; + adi_apollo_pfilt_gain_dly_pgm_t gain_dly_pgm = { + /* Gain can be +/-24dB in 6dB steps. */ + .pfir_iy_gain = ADI_APOLLO_PFILT_GAIN_ZERO_DB, + /* + * code = 64*scalarGain-1. 1/64 <= scalarGain <= 1. (code 6'h0 1/64(-36dB), + * 6'h1 1/32(-30dB), 6'h3f 1(0dB)) + */ + .pfir_iy_scalar_gain = 0x3f, + /* Gain can be +/-24dB in 6dB steps */ + .pfir_qx_gain = ADI_APOLLO_PFILT_GAIN_ZERO_DB, + /* + * code = 64*scalarGain-1. 1/64 <= scalarGain <= 1. (code 6'h0 1/64(-36dB), + * 6'h1 1/32(-30dB), 6'h3f 1(0dB)) + */ + .pfir_qx_scalar_gain = 0x3f, + }; + u8 read_mask = 0; + + while ((line = strsep(&ptr, "\n"))) { + if (line >= data + size) + break; + + if (line[0] == '#') + continue; + + if (~read_mask & BIT(0)) { + char imode[16], qmode[16]; + + ret = sscanf(line, "mode: %15s %15s", + imode, qmode); + + if (ret == 2) + pfilt_mode_pgm.pfir_q_mode[0] = sysfs_match_string(pfir_filter_modes, + qmode); + + if (ret == 1 || ret == 2) { + pfilt_mode_pgm.pfir_i_mode[0] = sysfs_match_string(pfir_filter_modes, + imode); + read_mask |= BIT(0); + continue; + } + } + + if (~read_mask & BIT(1)) { + int ix = 0, iy = 0, qx = 0, qy = 0; + + ret = sscanf(line, "gain: %d %d %d %d", + &ix, &iy, &qx, &qy); + + if (ret == 4) { + gain_dly_pgm.pfir_ix_gain = ad9088_pfir_gain_enc(ix); + gain_dly_pgm.pfir_iy_gain = ad9088_pfir_gain_enc(iy); + gain_dly_pgm.pfir_qx_gain = ad9088_pfir_gain_enc(qx); + gain_dly_pgm.pfir_qy_gain = ad9088_pfir_gain_enc(qy); + + read_mask |= BIT(1); + continue; + } + } + + if (~read_mask & BIT(4)) { + ret = sscanf(line, "scalar_gain: %hhu %hhu %hhu %hhu", + &gain_dly_pgm.pfir_ix_scalar_gain, + &gain_dly_pgm.pfir_iy_scalar_gain, + &gain_dly_pgm.pfir_qx_scalar_gain, + &gain_dly_pgm.pfir_qy_scalar_gain); + + if (ret == 4) { + read_mask |= BIT(4); + continue; + } + } + + if (~read_mask & BIT(2)) { + char t[4], p[16], b[16]; + u32 mask; + + ret = sscanf(line, "dest: %3s %15s %15s", t, p, b); + + if (ret == 3) { + ret = sysfs_match_string(terminals, t); + if (ret < 0) + goto out; + terminal = ret ? ADI_APOLLO_TX : ADI_APOLLO_RX; + + ret = sysfs_match_string(pfir_selects, p); + if (ret < 0) + goto out; + pfilt_sel = 1 << ret; + if (ret == 4) + pfilt_sel = ADI_APOLLO_PFILT_ALL; + if (ret == 5) { + ret = sscanf(line, "pfilt_mask%u", &mask); + if (ret != 1) + goto out; + pfilt_sel = mask; + } + + ret = sysfs_match_string(pfir_filter_banks, b); + if (ret < 0) + goto out; + bank_sel = 1 << ret; + if (ret == 4) + bank_sel = ADI_APOLLO_PFILT_BANK_ALL; + if (ret == 5) { + ret = sscanf(line, "bank_mask%u", &mask); + if (ret != 1) + goto out; + bank_sel = mask; + } + + read_mask |= BIT(2); + continue; + } + } + + if (~read_mask & BIT(3)) { + ret = sscanf(line, "hc_delay: %hhu", &gain_dly_pgm.hc_delay); + if (ret == 1) { + read_mask |= BIT(3); + continue; + } + } + + if (~read_mask & BIT(5)) { + ret = sscanf(line, "mode_switch_en: %u", &val); + if (ret == 1) { + pfilt_mode_pgm.mode_switch = val ? ADI_APOLLO_PFILT_ENABLE_3DB_AVG_MOD_SW : ADI_APOLLO_PFILT_DISABLE_3DB_AVG_MOD_SW; + read_mask |= BIT(5); + continue; + } + } + + if (~read_mask & BIT(6)) { + ret = sscanf(line, "mode_switch_add_en: %u", &val); + if (ret == 1) { + pfilt_mode_pgm.add_sub_sel = val ? ADI_APOLLO_PFILT_ADD_FOR_MOD_SW : ADI_APOLLO_PFILT_SUB_FOR_MOD_SW; + read_mask |= BIT(6); + continue; + } + } + + if (~read_mask & BIT(7)) { + ret = sscanf(line, "real_data_mode_en: %u", &val); + if (ret == 1) { + pfilt_mode_pgm.data = val ? ADI_APOLLO_PFILT_REAL_DATA : ADI_APOLLO_PFILT_COMPLEX_DATA; + read_mask |= BIT(7); + continue; + } + } + + if (~read_mask & BIT(8)) { + ret = sscanf(line, "quad_mode_en: %u", &val); + if (ret == 1) { + pfilt_mode_pgm.dq_mode = val ? ADI_APOLLO_PFILT_QUAD_MODE : ADI_APOLLO_PFILT_DUAL_MODE; + read_mask |= BIT(8); + continue; + } + } + + if (~read_mask & BIT(9)) { + char m[16]; + + ret = sscanf(line, "selection_mode: %s", m); + if (ret == 1) { + ret = sysfs_match_string(pfilt_profile_selection_mode, m); + if (ret < 0) + goto out; + + selection_mode = ret; + read_mask |= BIT(9); + continue; + } + } + + ret = sscanf(line, "%i", &sval); + if (ret == 1) { + if (i >= ADI_APOLLO_PFILT_COEFF_NUM) + return -EINVAL; + + pfilt_coeffs[i++] = (u16)sval; + continue; + } + } + + dev_dbg(dev, "terminal: %s\n", terminals[terminal]); + dev_dbg(dev, "pfilt_sel: MASK 0x%X\n", pfilt_sel); + dev_dbg(dev, "bank_sel: MASK 0x%x\n", bank_sel); + + dev_dbg(dev, "pfilt_mode_pgm.pfir_i_mode: %s\n", + pfir_filter_modes[pfilt_mode_pgm.pfir_i_mode[0]]); + dev_dbg(dev, "pfilt_mode_pgm.pfir_q_mode: %s\n", + pfir_filter_modes[pfilt_mode_pgm.pfir_q_mode[0]]); + dev_dbg(dev, "pfilt_mode_pgm.mode_switch: %d\n", pfilt_mode_pgm.mode_switch); + dev_dbg(dev, "pfilt_mode_pgm.add_sub_sel: %d\n", pfilt_mode_pgm.add_sub_sel); + dev_dbg(dev, "pfilt_mode_pgm.data: %d\n", pfilt_mode_pgm.data); + dev_dbg(dev, "pfilt_mode_pgm.dq_mode: %d\n", pfilt_mode_pgm.dq_mode); + + ret = adi_apollo_pfilt_mode_pgm(&phy->ad9088, terminal, pfilt_sel, &pfilt_mode_pgm); + if (ret < 0) + goto out1; + + dev_dbg(dev, "gain_dly_pgm.pfir_ix_gain: %d\n", gain_dly_pgm.pfir_ix_gain); + dev_dbg(dev, "gain_dly_pgm.pfir_iy_gain: %d\n", gain_dly_pgm.pfir_iy_gain); + dev_dbg(dev, "gain_dly_pgm.pfir_qx_gain: %d\n", gain_dly_pgm.pfir_qx_gain); + dev_dbg(dev, "gain_dly_pgm.pfir_qy_gain: %d\n", gain_dly_pgm.pfir_qy_gain); + dev_dbg(dev, "gain_dly_pgm.pfir_ix_scalar_gain: %u\n", gain_dly_pgm.pfir_ix_scalar_gain); + dev_dbg(dev, "gain_dly_pgm.pfir_iy_scalar_gain: %u\n", gain_dly_pgm.pfir_iy_scalar_gain); + dev_dbg(dev, "gain_dly_pgm.pfir_qx_scalar_gain: %u\n", gain_dly_pgm.pfir_qx_scalar_gain); + dev_dbg(dev, "gain_dly_pgm.pfir_qy_scalar_gain: %u\n", gain_dly_pgm.pfir_qy_scalar_gain); + dev_dbg(dev, "gain_dly_pgm.hc_delay: %u\n", gain_dly_pgm.hc_delay); + dev_dbg(dev, "selection_mode: %u\n", selection_mode); + + ret = adi_apollo_pfilt_gain_dly_pgm(&phy->ad9088, terminal, pfilt_sel, bank_sel, + &gain_dly_pgm); + if (ret < 0) + goto out1; + + if (read_mask & BIT(9)) { + ret = adi_apollo_pfilt_profile_sel_mode_set(&phy->ad9088, terminal, pfilt_sel, + selection_mode); + if (ret < 0) + goto out1; + } + + for (j = 0; j < i; j++) + dev_dbg(dev, "0x%X\n", pfilt_coeffs[j]); + + ret = adi_apollo_pfilt_coeff_pgm(&phy->ad9088, terminal, pfilt_sel, bank_sel, + pfilt_coeffs, i); + if (ret < 0) + goto out1; + ret = adi_apollo_pfilt_coeff_transfer(&phy->ad9088, terminal, pfilt_sel, bank_sel); + if (ret < 0) + goto out1; + +out1: + if (ret != API_CMS_ERROR_OK) + dev_err(&phy->spi->dev, "Programming filter failed (%d)", ret); + + return size; + +out: + dev_err(dev, "malformed pFir filter file detected\n"); + + return -EINVAL; +} + +static ssize_t +ad9088_pfilt_bin_write(struct file *filp, struct kobject *kobj, + struct bin_attribute *bin_attr, + char *buf, loff_t off, size_t count) +{ + struct iio_dev *indio_dev = dev_to_iio_dev(kobj_to_dev(kobj)); + struct axiadc_converter *conv = iio_device_get_drvdata(indio_dev); + struct ad9088_phy *phy = conv->phy; + + guard(mutex)(&phy->lock); + + return ad9088_parse_pfilt(phy, buf, count); +} + +/* CFIR */ + +static const char *const cfir_selects[] = { + "cfir_none", "cfir_a0", "cfir_a1", "cfir_b0", + "cfir_b1", "cfir_all", "cfir_mask" +}; + +static const char *const cfir_profiles[] = { + "profile_none", "profile_1", "profile_2", "profile_all" +}; + +static const char *const cfir_datapaths[] = { + "datapath_none", "datapath_0", "datapath_1", "datapath_2", + "datapath_3", "datapath_all", "datapath_mask" +}; + +static const char *const cfir_profile_selection_mode[] = { + "direct_regmap", "direct_gpio", "trig_regmap", "trig_gpio" +}; + +static u32 ad9088_cfir_gain_enc(int val) +{ + switch (val) { + case 0: + return ADI_APOLLO_CFIR_GAIN_ZERO_DB; + case 6: + return ADI_APOLLO_CFIR_GAIN_PLUS6_DB; + case 12: + return ADI_APOLLO_CFIR_GAIN_PLUS12_DB; + case -18: + return ADI_APOLLO_CFIR_GAIN_MINUS18_DB; + case -12: + return ADI_APOLLO_CFIR_GAIN_MINUS12_DB; + case -6: + return ADI_APOLLO_CFIR_GAIN_MINUS6_DB; + default: + return ADI_APOLLO_CFIR_GAIN_ZERO_DB; + } +}; + +/** + * ad9088_parse_cfilt - Parse the CFIR filter configuration from a string + * @phy: Pointer to the ad9088_phy structure + * @data: Pointer to the string containing the CFIR filter configuration + * @size: Size of the string + * + * This function parses the CFIR filter configuration from a string and updates + * the ad9088_phy structure accordingly. The string should have the following + * format: + * + * dest: + * gain: + * complex_scalar: + * bypass: + * sparse_filt_en: + * 32taps_en: <32taps_en_value> + * coeff_transfer: + * enable: + * selection_mode: + * + * + * ... + * + * + * Each line in the string represents a specific configuration parameter. + * The "dest" line specifies the destination terminal, CFIR select, CFIR profile, + * and CFIR datapath. The "gain" line specifies the gain value. The "complex_scalar" + * line specifies the complex scalar values. The "bypass" line specifies the bypass + * value. The "sparse_filt_en" line specifies the sparse filter enable value. + * The "32taps_en" line specifies the 32 taps enable value. The "coeff_transfer" + * line specifies the coefficient transfer value. The "enable" line specifies the + * enable value and enable profile value. The "selection_mode" line specifies the + * selection mode value. The and lines specify the + * CFIR coefficient values. + * + * Return: 0 on success, negative error code on failure + */ +static int ad9088_parse_cfilt(struct ad9088_phy *phy, + char *data, u32 size) +{ + struct device *dev = &phy->spi->dev; + char *line; + int i = 0, ret, j; + char *ptr = data; + u16 cfir_coeff_i[ADI_APOLLO_CFIR_COEFF_NUM]; + u16 cfir_coeff_q[ADI_APOLLO_CFIR_COEFF_NUM]; + u32 val, enable; + s32 sval_i, sval_q, enable_profile, selection_mode, gain = 0; + adi_apollo_terminal_e terminal; + adi_apollo_cfir_sel_e cfir_sel; + adi_apollo_cfir_dp_sel dp_sel; + adi_apollo_cfir_profile_sel_e profile_sel; + adi_apollo_cfir_pgm_t cfir_pgm = { 0 }; + u16 scalar_i, scalar_q; + u8 read_mask = 0; + + while ((line = strsep(&ptr, "\n"))) { + if (line >= data + size) + break; + + if (line[0] == '#') /* skip comments */ + continue; + + if (~read_mask & BIT(0)) { + char t[4], s[16], p[16], d[21]; + u32 mask; + /* dest: rx cfir_a0 profile_1 datapath_0 */ + ret = sscanf(line, "dest: %3s %15s %15s %20s", t, s, p, d); + if (ret == 4) { + ret = sysfs_match_string(terminals, t); + if (ret < 0) { + dev_err(dev, "dest read:%s %s %s %s", t, s, p, d); + goto out; + } + terminal = ret ? ADI_APOLLO_TX : ADI_APOLLO_RX; + + ret = sysfs_match_string(cfir_selects, s); + + if (ret < 0) + goto out; + + switch (ret) { + case 0: + cfir_sel = ADI_APOLLO_CFIR_NONE; + break; + case 1: + cfir_sel = ADI_APOLLO_CFIR_A0; + break; + case 2: + cfir_sel = ADI_APOLLO_CFIR_A1; + break; + case 3: + cfir_sel = ADI_APOLLO_CFIR_B0; + break; + case 4: + cfir_sel = ADI_APOLLO_CFIR_B1; + break; + case 5: + cfir_sel = ADI_APOLLO_CFIR_ALL; + break; + case 6: + ret = sscanf(s, "cfir_mask%u", &mask); + if (ret != 1) + goto out; + cfir_sel = mask; + break; + default: + goto out; + } + + ret = sysfs_match_string(cfir_profiles, p); + if (ret < 0) { + dev_err(dev, "dest read:%s %s %s %s", t, s, p, d); + goto out; + } + switch (ret) { + case 0: + profile_sel = ADI_APOLLO_CFIR_PROFILE_NONE; + break; + case 1: + profile_sel = ADI_APOLLO_CFIR_PROFILE_0; + break; + case 2: + profile_sel = ADI_APOLLO_CFIR_PROFILE_1; + break; + case 3: + profile_sel = ADI_APOLLO_CFIR_PROFILE_ALL; + break; + default: + goto out; + } + + ret = sysfs_match_string(cfir_datapaths, d); + if (ret < 0) { + dev_err(dev, "dest read:%s %s %s %s", t, s, p, d); + goto out; + } + switch (ret) { + case 0: + dp_sel = ADI_APOLLO_CFIR_DP_NONE; + break; + case 1: + dp_sel = ADI_APOLLO_CFIR_DP_0; + break; + case 2: + dp_sel = ADI_APOLLO_CFIR_DP_1; + break; + case 3: + dp_sel = ADI_APOLLO_CFIR_DP_2; + break; + case 4: + dp_sel = ADI_APOLLO_CFIR_DP_3; + break; + case 5: + dp_sel = ADI_APOLLO_CFIR_DP_ALL; + break; + case 6: + ret = sscanf(d, "datapath_mask%u", &mask); + if (ret != 1) + goto out; + dp_sel = mask; + break; + default: + goto out; + } + + read_mask |= BIT(0); + continue; + } + } + + if (~read_mask & BIT(1)) { + ret = sscanf(line, "gain: %d", &val); + if (ret == 1) { + gain = ad9088_cfir_gain_enc(val); + read_mask |= BIT(1); + continue; + } + } + + if (~read_mask & BIT(2)) { + ret = sscanf(line, "complex_scalar: %i %i", &sval_i, &sval_q); + if (ret == 2) { + scalar_i = sval_i; + scalar_q = sval_q; + read_mask |= BIT(2); + continue; + } + } + + if (~read_mask & BIT(3)) { + ret = sscanf(line, "bypass: %hhu", &cfir_pgm.cfir_bypass); + if (ret == 1) { + read_mask |= BIT(3); + continue; + } + } + if (~read_mask & BIT(4)) { + ret = sscanf(line, "sparse_filt_en: %hhu", &cfir_pgm.cfir_sparse_filt_en); + if (ret == 1) { + read_mask |= BIT(4); + continue; + } + } + if (~read_mask & BIT(5)) { + ret = sscanf(line, "32taps_en: %hhu", &cfir_pgm.cfir_32taps_en); + if (ret == 1) { + read_mask |= BIT(5); + continue; + } + } + if (~read_mask & BIT(6)) { + ret = sscanf(line, "coeff_transfer: %hhu", &cfir_pgm.cfir_coeff_transfer); + if (ret == 1) { + read_mask |= BIT(6); + continue; + } + } + if (~read_mask & BIT(6)) { + char p[16]; + + ret = sscanf(line, "enable: %u %s", &enable, p); + if (ret == 2) { + enable_profile = sysfs_match_string(cfir_profiles, p); + if (enable_profile < 0) + goto out; + read_mask |= BIT(6); + continue; + } + } + if (~read_mask & BIT(7)) { + char m[16]; + + ret = sscanf(line, "selection_mode: %s", m); + if (ret == 1) { + ret = sysfs_match_string(cfir_profile_selection_mode, m); + if (ret < 0) + goto out; + + selection_mode = ret; + read_mask |= BIT(7); + continue; + } + } + + ret = sscanf(line, "%i %i", &sval_i, &sval_q); + if (ret == 2) { + if (i >= ADI_APOLLO_CFIR_COEFF_NUM) + return -EINVAL; + + cfir_coeff_i[i] = (u16)sval_i; + cfir_coeff_q[i++] = (u16)sval_q; + continue; + } + } + + if (read_mask & BIT(0)) { + dev_dbg(dev, "terminal: %s\n", terminals[terminal]); + dev_dbg(dev, "cfir_sel: MASK 0x%X\n", cfir_sel); + dev_dbg(dev, "profile_sel: %s\n", cfir_profiles[profile_sel]); + dev_dbg(dev, "dp_sel: MASK 0x%x\n", dp_sel); + } else { + dev_err(dev, "dest: not found\n"); + goto out; + } + + for (j = 0; j < i; j++) + dev_dbg(dev, "0x%X\t0x%X\n", cfir_coeff_i[j], cfir_coeff_q[j]); + + ret = adi_apollo_cfir_coeff_pgm(&phy->ad9088, terminal, cfir_sel, profile_sel, dp_sel, + cfir_coeff_i, cfir_coeff_q, i); + if (ret < 0) + goto out1; + + if (read_mask & BIT(2)) { + dev_dbg(dev, "scalar_i: %d scalar_q: %d\n", scalar_i, scalar_q); + ret = adi_apollo_cfir_scalar_pgm(&phy->ad9088, terminal, cfir_sel, profile_sel, + dp_sel, scalar_i, scalar_q); + if (ret < 0) + goto out1; + } + + if (read_mask & BIT(1)) { + dev_dbg(dev, "gain: %d\n", gain); + ret = adi_apollo_cfir_gain_pgm(&phy->ad9088, terminal, cfir_sel, profile_sel, + dp_sel, gain); + if (ret < 0) + goto out1; + } + + if (read_mask & BIT(7)) { + dev_dbg(dev, "selection_mode: %d\n", selection_mode); + ret = adi_apollo_cfir_profile_sel_mode_set(&phy->ad9088, terminal, cfir_sel, + selection_mode); + if (ret < 0) + goto out1; + } + + ret = adi_apollo_cfir_pgm(&phy->ad9088, terminal, cfir_sel, &cfir_pgm); + if (ret < 0) + goto out1; + + /* This seems to be required */ + ret = adi_apollo_clk_mcs_dyn_sync_sequence_run(&phy->ad9088); + if (ret < 0) + goto out1; + + if (read_mask & BIT(6)) { + u32 j; + + dev_dbg(dev, "enable: %u enable_profile: %u\n", enable, enable_profile); + adi_apollo_cfir_profile_sel(&phy->ad9088, terminal, cfir_sel, dp_sel, + enable_profile); + if (ret < 0) + goto out1; + ret = adi_apollo_cfir_mode_enable_set(&phy->ad9088, terminal, cfir_sel, enable); + if (ret < 0) + goto out1; + + for (i = 0; i < 4; i++) { + if (!(cfir_sel & BIT(i))) + continue; + for (j = 0; j < 4; j++) { + if (!(dp_sel & BIT(j))) + continue; + phy->cfir_profile[terminal][BIT(i)][BIT(j)] = enable_profile; + phy->cfir_enable[terminal][BIT(i)][BIT(j)] = enable; + } + } + } + +out1: + if (ret != API_CMS_ERROR_OK) + dev_err(&phy->spi->dev, "Programming filter failed (%d)", ret); + + return size; + +out: + dev_err(dev, "malformed CFir filter file detected\n"); + + return -EINVAL; +} + +static ssize_t ad9088_cfir_bin_write(struct file *filp, struct kobject *kobj, + struct bin_attribute *bin_attr, + char *buf, loff_t off, size_t count) +{ + struct iio_dev *indio_dev = dev_to_iio_dev(kobj_to_dev(kobj)); + struct axiadc_converter *conv = iio_device_get_drvdata(indio_dev); + struct ad9088_phy *phy = conv->phy; + + guard(mutex)(&phy->lock); + + return ad9088_parse_cfilt(phy, buf, count); +} + +static int ad9088_post_iio_register(struct iio_dev *indio_dev) +{ + struct axiadc_converter *conv = iio_device_get_drvdata(indio_dev); + struct ad9088_phy *phy = conv->phy; + int ret; + + /* Register debugfs entries */ + ad9088_debugfs_register(indio_dev); + + sysfs_bin_attr_init(&phy->pfilt); + phy->pfilt.attr.name = "pfilt_config"; + phy->pfilt.attr.mode = 0200; + phy->pfilt.write = ad9088_pfilt_bin_write; + phy->pfilt.size = 4096; + + ret = device_create_bin_file(&indio_dev->dev, &phy->pfilt); + if (ret) + return ret; + + sysfs_bin_attr_init(&phy->cfir); + phy->cfir.attr.name = "cfir_config"; + phy->cfir.attr.mode = 0200; + phy->cfir.write = ad9088_cfir_bin_write; + phy->cfir.size = 4096; + + ret = device_create_bin_file(&indio_dev->dev, &phy->cfir); + if (ret) + return ret; + + sysfs_bin_attr_init(&phy->cal_data); + phy->cal_data.attr.name = "calibration_data"; + phy->cal_data.attr.mode = 0600; /* Read and write */ + phy->cal_data.read = ad9088_cal_data_read; + phy->cal_data.write = ad9088_cal_data_write; + phy->cal_data.size = 0; /* Dynamic size */ + + return device_create_bin_file(&indio_dev->dev, &phy->cal_data); +} + +static char *ad9088_label_writer(struct ad9088_phy *phy, const struct iio_chan_spec *chan) +{ + u8 adcdac_num, cddc_num, fddc_num, side; + u32 adcdac_mask, cddc_mask, fddc_mask; + + ad9088_iiochan_to_fddc_cddc_from_profile(phy, chan, &fddc_num, &fddc_mask, &cddc_num, + &cddc_mask, &adcdac_num, &adcdac_mask, &side); + + if (chan->output) { + phy->tx_chan_map[chan->address].fddc_num = fddc_num; + phy->tx_chan_map[chan->address].cddc_num = cddc_num; + phy->tx_chan_map[chan->address].adcdac_num = adcdac_num; + phy->tx_chan_map[chan->address].cddc_mask = cddc_mask; + phy->tx_chan_map[chan->address].fddc_mask = fddc_mask; + phy->tx_chan_map[chan->address].adcdac_mask = adcdac_mask; + phy->tx_chan_map[chan->address].side = side; + + snprintf(phy->tx_chan_labels[chan->channel], sizeof(phy->tx_chan_labels[0]), + "Side-%c:FDUC%u->CDUC%u->DAC%u", side ? 'B' : 'A', fddc_num, cddc_num, + adcdac_num); + + return phy->tx_chan_labels[chan->channel]; + } + + phy->rx_chan_map[chan->address].fddc_num = fddc_num; + phy->rx_chan_map[chan->address].cddc_num = cddc_num; + phy->rx_chan_map[chan->address].adcdac_num = adcdac_num; + phy->rx_chan_map[chan->address].cddc_mask = cddc_mask; + phy->rx_chan_map[chan->address].fddc_mask = fddc_mask; + phy->rx_chan_map[chan->address].adcdac_mask = adcdac_mask; + phy->rx_chan_map[chan->address].side = side; + + snprintf(phy->rx_chan_labels[chan->channel], sizeof(phy->rx_chan_labels[0]), + "Side-%c:FDDC%u->CDDC%u->ADC%u", side ? 'B' : 'A', fddc_num, cddc_num, adcdac_num); + + return phy->rx_chan_labels[chan->channel]; +} + +static int ad9088_setup_chip_info_tbl(struct ad9088_phy *phy, + bool complex_rx, bool complex_tx, bool buffer_capable) +{ + struct device *dev = &phy->spi->dev; + int i, c, m, s, l, total_rx_channels; + + for (m = 0, s = 0; s < ADI_APOLLO_NUM_SIDES; s++) + for (l = 0; l < ADI_APOLLO_JESD_LINKS; l++) + if (phy->profile.jtx[s].tx_link_cfg[l].link_in_use) + m += phy->profile.jtx[s].tx_link_cfg[l].m_minus1 + 1; + + total_rx_channels = m * phy->multidevice_instance_count; + + if (total_rx_channels > MAX_NUM_REMAP_CHANNELS) + return dev_err_probe(dev, -EINVAL, "Too many RX channels (%d > %d)\n", + total_rx_channels, MAX_NUM_REMAP_CHANNELS); + + phy->rx_labels = devm_kcalloc(dev, total_rx_channels, + sizeof(*phy->rx_labels), GFP_KERNEL); + if (!phy->rx_labels) + return -ENOMEM; + + for (c = 0, i = 0; i < total_rx_channels; i++, c++) { + s8 remap_idx = phy->rx_iio_to_phy_remap[i]; + int scan_idx; + + phy->chip_info.channel[c].type = IIO_VOLTAGE; + phy->chip_info.channel[c].output = 0; + phy->chip_info.channel[c].indexed = 1; + phy->chip_info.channel[c].modified = complex_rx ? 1 : 0; + phy->chip_info.channel[c].channel = complex_rx ? i / 2 : i; + phy->chip_info.channel[c].channel2 = + (i & 1) ? IIO_MOD_Q : IIO_MOD_I; + + /* + * Apply IIO-to-PHY remapping to scan_index for lane swap compensation. + * When remap is configured, the scan_index (DMA buffer position) is + * remapped so that the IIO channel's data buffer matches the physical + * channel that its control attributes operate on. + */ + if (remap_idx >= 0 && remap_idx < total_rx_channels) + scan_idx = remap_idx; + else + scan_idx = i; + + phy->chip_info.channel[c].scan_index = buffer_capable ? scan_idx : -1; + + if (phy->side_b_use_own_tpl_en && + (i >= ((phy->profile.jtx[0].tx_link_cfg[0].m_minus1 + 1) * + phy->multidevice_instance_count))) + phy->chip_info.channel[c].scan_index = -1; + + phy->chip_info.channel[c].address = i; + phy->chip_info.channel[c].info_mask_shared_by_type = + BIT(IIO_CHAN_INFO_SAMP_FREQ); + + phy->chip_info.channel[c].scan_type.realbits = + phy->profile.jtx[0].tx_link_cfg[0].n_minus1 + 1; + phy->chip_info.channel[c].scan_type.storagebits = + (phy->profile.jtx[0].tx_link_cfg[0].np_minus1 + 1 > 8) ? 16 : 8; + phy->chip_info.channel[c].scan_type.sign = 's'; + + if (i < m) { + phy->chip_info.channel[c].ext_info = rxadc_ext_info; + phy->chip_info.channel[c].info_mask_separate = + BIT(IIO_CHAN_INFO_ENABLE); + phy->rx_labels[phy->chip_info.channel[c].channel] = + ad9088_label_writer(phy, &phy->chip_info.channel[c]); + } else { + phy->rx_labels[phy->chip_info.channel[c].channel] = "buffer_only"; + } + } + + for (m = 0, s = 0; s < ADI_APOLLO_NUM_SIDES; s++) + for (l = 0; l < ADI_APOLLO_JESD_LINKS; l++) + if (phy->profile.jrx[s].rx_link_cfg[l].link_in_use) + m += phy->profile.jrx[s].rx_link_cfg[l].m_minus1 + 1; + + phy->tx_labels = devm_kcalloc(&phy->spi->dev, m, + sizeof(*phy->tx_labels), GFP_KERNEL); + if (!phy->tx_labels) + return -ENOMEM; + + for (i = 0; i < m; i++, c++) { + phy->chip_info.channel[c].type = IIO_VOLTAGE; + phy->chip_info.channel[c].output = 1; + phy->chip_info.channel[c].indexed = 1; + phy->chip_info.channel[c].modified = complex_tx ? 1 : 0; + phy->chip_info.channel[c].channel = complex_tx ? i / 2 : i; + phy->chip_info.channel[c].channel2 = + (i & 1) ? IIO_MOD_Q : IIO_MOD_I; + phy->chip_info.channel[c].scan_index = -1; + phy->chip_info.channel[c].address = i; + phy->chip_info.channel[c].info_mask_shared_by_type = + BIT(IIO_CHAN_INFO_SAMP_FREQ); + + phy->chip_info.channel[c].info_mask_separate = + BIT(IIO_CHAN_INFO_ENABLE); + + phy->chip_info.channel[c].ext_info = txdac_ext_info; + phy->tx_labels[phy->chip_info.channel[c].channel] = + ad9088_label_writer(phy, &phy->chip_info.channel[c]); + } + + phy->chip_info.channel[c].type = IIO_TEMP; + phy->chip_info.channel[c].indexed = 1; + phy->chip_info.channel[c].info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED); + phy->chip_info.channel[c].scan_index = -1; + phy->chip_info.channel[c].ext_info = NULL; + c++; + + phy->chip_info.num_channels = c; + phy->chip_info.name = "AD9088"; + phy->chip_info.max_rate = 28000000UL; /* kHZ and not used */ + + return 0; +} + +static const struct iio_info ad9088_iio_info = { + .read_raw = &ad9088_read_raw, + .write_raw = &ad9088_write_raw, + .read_label = &ad9088_read_label, + .debugfs_reg_access = &ad9088_reg_access, + .attrs = &ad9088_phy_attribute_group, +}; + +static int ad9088_register_iiodev(struct axiadc_converter *conv) +{ + struct iio_dev *indio_dev; + struct spi_device *spi = conv->spi; + struct ad9088_phy *phy = conv->phy; + int ret; + + indio_dev = devm_iio_device_alloc(&spi->dev, 0); + if (!indio_dev) + return -ENOMEM; + + iio_device_set_drvdata(indio_dev, conv); + + indio_dev->name = spi_get_device_id(spi)->name; + indio_dev->info = &ad9088_iio_info; + indio_dev->modes = INDIO_DIRECT_MODE; + indio_dev->channels = phy->chip_info.channel; + indio_dev->num_channels = phy->chip_info.num_channels; + + ret = iio_device_register(indio_dev); + if (ret) + return ret; + + ad9088_post_iio_register(indio_dev); + + conv->indio_dev = indio_dev; + + return 0; +} + +static int ad9088_version_info(struct ad9088_phy *phy) +{ + adi_apollo_mailbox_resp_get_fw_version_t fw_ver; + adi_apollo_mailbox_cmd_ping_t ping_cmd; + adi_apollo_mailbox_resp_ping_t ping_resp; + adi_apollo_device_t *device = &phy->ad9088; + int ret; + u16 maj, min, rc; + + ret = adi_apollo_device_api_revision_get(device, &maj, &min, &rc); + if (ret) { + dev_err(&phy->spi->dev, "API revision get error (%d)\n", ret); + return ret; + } + + dev_info(&phy->spi->dev, "API ver: %d.%d.%d\n", maj, min, rc); + + ret = adi_apollo_mailbox_ready_check(device); + if (ret) { + dev_err(&phy->spi->dev, "Mailbox Ready error (%d)\n", ret); + if (ret != APOLLO_CPU_SYSTEM_AHB_COMMON_INVALID_ERROR) + return ret; + } + + ping_cmd.echo_data = 0x00000000; /* Ping core 1 (echo_data < 0x10000000, increment by 1) */ + ret = adi_apollo_mailbox_ping(device, &ping_cmd, &ping_resp); + if (ret) { + dev_err(&phy->spi->dev, "Mailbox ping error (%d)\n", ret); + return ret; + } + + dev_info(&phy->spi->dev, "Ping (core 1) cmd/res: 0x%08x/0x%08x\n", + ping_cmd.echo_data, ping_resp.echo_data); + + ping_cmd.echo_data = 0x12345678; /* Ping core 0 (echo_data >= 0x10000000, increment by 2) */ + ret = adi_apollo_mailbox_ping(device, &ping_cmd, &ping_resp); + if (ret) { + dev_err(&phy->spi->dev, "Mailbox ping error (%d)\n", ret); + return ret; + } + + dev_info(&phy->spi->dev, "Ping (core 0) cmd/res: 0x%08x/0x%08x\n", + ping_cmd.echo_data, ping_resp.echo_data); + + ret = adi_apollo_mailbox_get_fw_version(device, &fw_ver); + if (ret) { + dev_err(&phy->spi->dev, "Mailbox fw error (%d)\n", ret); + return ret; + } + + dev_info(&phy->spi->dev, "FW ver: %d.%d.%d\n", fw_ver.major, fw_ver.minor, fw_ver.patch); + + return ret; +} + +int ad9088_inspect_jrx_link_all(struct ad9088_phy *phy) +{ + int err; + adi_apollo_device_t *device = &phy->ad9088; + adi_apollo_jesd_rx_inspect_t jrx_status; + u16 links_to_inspect[] = { + ADI_APOLLO_LINK_A0, ADI_APOLLO_LINK_A1, + ADI_APOLLO_LINK_B0, ADI_APOLLO_LINK_B1 + }; + const char * const links_to_inspect_str[] = { "A0", "A1", "B0", "B1" }; + int i, l; + u8 phys_lane; + + phy->jrx_lanes_used = 0; + + for (l = 0; l < ARRAY_SIZE(links_to_inspect); l++) { + err = adi_apollo_jrx_link_inspect(device, links_to_inspect[l], &jrx_status); + err = ad9088_check_apollo_error(&phy->spi->dev, err, "adi_apollo_jrx_link_inspect"); + if (err) + return err; + + dev_info(&phy->spi->dev, "JRX ADI_APOLLO_LINK_%s: L=%2d M=%2d F=%2d S=%2d Np=%2d CS=%2d link_en= %-8s\n", + links_to_inspect_str[l], + jrx_status.l_minus1 + 1, + jrx_status.m_minus1 + 1, + jrx_status.f_minus1 + 1, + jrx_status.s_minus1 + 1, + jrx_status.np_minus1 + 1, + jrx_status.cs, + jrx_status.link_en ? "Enabled" : "Disabled"); + + if (jrx_status.link_en) + for (i = 0; i < jrx_status.l_minus1 + 1; i++) { + phys_lane = phy->profile.jrx[(l / 2) & 1].rx_link_cfg[(l % 2) & 1].lane_xbar[i]; + phy->jrx_lanes[phy->jrx_lanes_used++] = phys_lane + (((l / 2) & 1) * 12); + } + } + + return API_CMS_ERROR_OK; +} + +int ad9088_inspect_jtx_link_all(struct ad9088_phy *phy) +{ + int err; + adi_apollo_device_t *device = &phy->ad9088; + adi_apollo_jesd_tx_inspect_t jtx_status; + u16 links_to_inspect[] = { + ADI_APOLLO_LINK_A0, ADI_APOLLO_LINK_A1, + ADI_APOLLO_LINK_B0, ADI_APOLLO_LINK_B1 + }; + const char * const links_to_inspect_str[] = { "A0", "A1", "B0", "B1" }; + int l; + + for (l = 0; l < ARRAY_SIZE(links_to_inspect); l++) { + err = adi_apollo_jtx_link_inspect(device, links_to_inspect[l], &jtx_status); + err = ad9088_check_apollo_error(&phy->spi->dev, err, "adi_apollo_jtx_link_inspect"); + if (err) + return err; + + dev_info(&phy->spi->dev, "JTX ADI_APOLLO_LINK_%s: L=%2d M=%2d F=%2d S=%2d Np=%2d CS=%2d link_en= %-8s\n", + links_to_inspect_str[l], + jtx_status.l_minus1 + 1, + jtx_status.m_minus1 + 1, + jtx_status.f_minus1 + 1, + jtx_status.s_minus1 + 1, + jtx_status.np_minus1 + 1, + jtx_status.cs, + jtx_status.link_en ? "Enabled" : "Disabled"); + } + + return API_CMS_ERROR_OK; +} + +static int ad9088_setup(struct ad9088_phy *phy) +{ + adi_apollo_bmem_delay_sample_t config = { + .sample_size = 0, + .ramclk_ph_dis = 1, + .sample_delay = 0, + .parity_check_en = 1, + }; + adi_apollo_top_t *profile = &phy->profile; + struct spi_device *spi = phy->spi; + adi_apollo_device_t *device = &phy->ad9088; + u64 sample_rate; + int ret; + + ret = adi_apollo_adc_mode_switch_enable_set(device, 1); + ret = ad9088_check_apollo_error(&spi->dev, ret, "adi_apollo_adc_mode_switch_enable_set"); + if (ret) + return ret; + + ret = adi_apollo_startup_execute(device, profile, ADI_APOLLO_STARTUP_SEQ_DEFAULT); + ret = ad9088_check_apollo_error(&spi->dev, ret, "adi_apollo_startup_execute"); + if (ret) + return dev_err_probe(&spi->dev, ret, + "Failed to execute startup sequence\n"); + + /* Display API and Firmware revision */ + ret = ad9088_version_info(phy); + if (ret) + return dev_err_probe(&spi->dev, ret, + "Error displaying version info. This may indicate device clock is incorrect\n"); + + ret = adi_apollo_device_chip_id_get(&phy->ad9088, &phy->chip_id); + if (ret < 0) + return dev_err_probe(&spi->dev, ret, "chip_id failed\n"); + + /* Load calibration data from firmware if specified in device tree */ + ret = ad9088_cal_load_from_firmware(phy); + if (ret) + return dev_err_probe(&spi->dev, ret, + "Failed to load calibration data from firmware\n"); + + if (phy->cddc_sample_delay_en) { + ret = adi_apollo_bmem_cddc_delay_sample_config(device, ADI_APOLLO_BMEM_ALL, + &config); + ret = ad9088_check_apollo_error(&spi->dev, ret, + "adi_apollo_bmem_cddc_delay_sample_config"); + if (ret) + return ret; + } + + if (phy->fddc_sample_delay_en) { + ret = adi_apollo_bmem_fddc_delay_sample_config(device, ADI_APOLLO_BMEM_ALL, + &config); + ret = ad9088_check_apollo_error(&spi->dev, ret, + "adi_apollo_bmem_fddc_delay_sample_config"); + if (ret) + return ret; + } + + if (phy->sniffer_en) { + ret = adi_apollo_sniffer_enable_set(device, ADI_APOLLO_SIDE_ALL, ADI_APOLLO_ENABLE); + ret = ad9088_check_apollo_error(&spi->dev, ret, + "adi_apollo_sniffer_enable_set"); + if (ret) + return dev_err_probe(&spi->dev, ret, "Failed to enable sniffer\n"); + } + + sample_rate = DIV_ROUND_CLOSEST_ULL(phy->profile.dac_cfg[0].dac_sampling_rate_Hz, + phy->profile.jrx[0].rx_link_cfg[0].link_total_ratio); + clk_set_rate_scaled(phy->clks[TX_SAMPL_CLK], sample_rate, + &phy->clkscale[TX_SAMPL_CLK]); + + sample_rate = DIV_ROUND_CLOSEST_ULL(phy->profile.adc_cfg[0].adc_sampling_rate_Hz, + phy->profile.jtx[0].tx_link_cfg[0].link_total_ratio); + clk_set_rate_scaled(phy->clks[RX_SAMPL_CLK], sample_rate, + &phy->clkscale[RX_SAMPL_CLK]); + + return 0; +} + +int ad9088_iio_write_channel_ext_info(struct ad9088_phy *phy, struct iio_channel *chan, + const char *ext_name, long long val) +{ + ssize_t size; + char str[16]; + + snprintf(str, sizeof(str), "%lld\n", val); + + size = iio_write_channel_ext_info(chan, ext_name, str, sizeof(str)); + if (size != sizeof(str)) { + dev_err(&phy->spi->dev, "%s: Failed to write channel ext info\n", __func__); + return -EINVAL; + } + + return 0; +} + +int ad9088_iio_read_channel_ext_info(struct ad9088_phy *phy, struct iio_channel *chan, + const char *ext_name, long long *val) +{ + ssize_t size; + int ret; + + char *str __free(kfree) = kzalloc(PAGE_SIZE, GFP_KERNEL); + if (!str) + return -ENOMEM; + + size = iio_read_channel_ext_info(chan, ext_name, str); + if (size < 0) { + dev_err(&phy->spi->dev, "%s: Failed to read channel ext info\n", __func__); + return size; + } + + ret = kstrtoll(str, 10, val); + if (ret) { + dev_err(&phy->spi->dev, "%s: Failed to parse value\n", __func__); + return ret; + } + + return 0; +} + +static int ad9088_reg_test(adi_apollo_device_t *device) +{ + s32 err; + u32 i, data32; + u8 data8, stat; + adi_apollo_hal_protocol_e protocol; + const u32 direct_addr[] = { 0x4700000a, 0x4700000a, 0x47000200, 0x47000200 }; + const u8 direct_data[] = { 0x55, 0xaa, 0xcc, 0x33 }; + u32 indirect_addr[] = { + INDIRECT_REG_TEST_ADDR + 0, INDIRECT_REG_TEST_ADDR + 1, + INDIRECT_REG_TEST_ADDR + 2, INDIRECT_REG_TEST_ADDR + 3 + }; /* indirect register address */ + const u8 indirect_data[] = { 0x12, 0x34, 0x56, 0x78 }; + + u32 arm_addr[] = { + ARM_REG_TEST_BASE_ADDR + 0, ARM_REG_TEST_BASE_ADDR + 4, + ARM_REG_TEST_BASE_ADDR + 8, ARM_REG_TEST_BASE_ADDR + 12 + }; /* ARM core1 register addresses */ + const u32 arm_data[] = { 0x55aa55aa, 0xdeadbeef, 0xbeefdead, 0xaa55aa55 }; + + adi_apollo_hal_active_protocol_get(device, &protocol); + + /* Direct register SPI scratch loop rd/wr test */ + stat = 0; + for (i = 0; i < ARRAY_SIZE(direct_addr); i++) { + if ((protocol == ADI_APOLLO_HAL_PROTOCOL_HSCI) && (direct_addr[i] <= 0x4700000Fu)) + continue; + + err = adi_apollo_hal_reg_set(device, direct_addr[i], direct_data[i]); + if (err != API_CMS_ERROR_OK) + return err; + + err = adi_apollo_hal_reg_get(device, direct_addr[i], &data8); + if (err != API_CMS_ERROR_OK) + return err; + + if (data8 != direct_data[i]) { + pr_err("data8 0x%X != direct_data[i] 0x%X\n", data8, direct_data[i]); + stat = 1; + } + } + + pr_err("Test direct register %s\n", (stat == 0) ? "Passed" : "*** FAILED ***"); + if (stat != 0) + return API_CMS_ERROR_ERROR; + + /* Indirect register SPI loop rd/wr test */ + stat = 0; + for (i = 0; i < ARRAY_SIZE(indirect_addr); i++) { + err = adi_apollo_hal_reg_set(device, indirect_addr[i], indirect_data[i]); + if (err != API_CMS_ERROR_OK) + return err; + + err = adi_apollo_hal_reg_get(device, indirect_addr[i], &data8); + if (err != API_CMS_ERROR_OK) + return err; + + if (data8 != indirect_data[i]) { + pr_err("Test indirect register 0x%X - 0x%X\n", data8, indirect_data[i]); + stat = 1; + } + } + + pr_err("Test indirect register %s\n", (stat == 0) ? "Passed" : "*** FAILED ***"); + if (stat != 0) + return API_CMS_ERROR_ERROR; + + /* 32-bit ARM mem rd/wr test */ + stat = 0; + for (i = 0; i < ARRAY_SIZE(arm_addr); i++) { + err = adi_apollo_hal_reg32_set(device, arm_addr[i], arm_data[i]); + if (err != API_CMS_ERROR_OK) + return err; + + err = adi_apollo_hal_reg32_get(device, arm_addr[i], &data32); + if (err != API_CMS_ERROR_OK) + return err; + + if (data32 != arm_data[i]) { + pr_err("Test ARM memory 0x%X - 0x%X\n", data32, arm_data[i]); + stat = 1; + } else { + stat = 0; + } + } + + pr_err("Test ARM memory %s\n", (stat == 0) ? "Passed" : "*** FAILED ***"); + if (stat != 0) + return API_CMS_ERROR_ERROR; + + return API_CMS_ERROR_OK; +} + +static int ad9088_hsci_manual_linkup(void *user_data, uint8_t enable, uint16_t link_up_signal_bits) +{ + struct axiadc_converter *conv = user_data; + struct ad9088_phy *phy = conv->phy; + + dev_dbg(&phy->spi->dev, "%s:%d\n", __func__, __LINE__); + + return axi_hsci_manual_linkup(phy->hsci, enable, link_up_signal_bits); +} + +static int ad9088_hsci_auto_linkup(void *user_data, uint8_t enable, uint8_t hscim_mosi_clk_inv, + uint8_t hscim_miso_clk_inv) +{ + struct axiadc_converter *conv = user_data; + struct ad9088_phy *phy = conv->phy; + + dev_dbg(&phy->spi->dev, "%s:%d\n", __func__, __LINE__); + + return axi_hsci_auto_linkup(phy->hsci, enable, hscim_mosi_clk_inv, hscim_miso_clk_inv); +} + +static int ad9088_hsci_alink_tbl_get(void *user_data, uint16_t *hscim_alink_table) +{ + struct axiadc_converter *conv = user_data; + struct ad9088_phy *phy = conv->phy; + + dev_dbg(&phy->spi->dev, "%s:%d\n", __func__, __LINE__); + + return axi_hsci_alink_tbl_get(phy->hsci, hscim_alink_table); +} + +static int ad9088_hsci_read(void *user_data, const u8 *tx_data, u8 *rx_data, u32 num_tx_rx_bytes, + adi_apollo_hal_txn_config_t *txn_config) +{ + struct axiadc_converter *conv = user_data; + struct ad9088_phy *phy = conv->phy; + int ret; + + dev_dbg(&phy->spi->dev, "%s:%d\n", __func__, __LINE__); + + ret = axi_hsci_readm(phy->hsci, tx_data, rx_data, num_tx_rx_bytes, + txn_config->addr_len, txn_config->data_len, txn_config->stream_len); + + return ret; +} + +static int ad9088_hsci_write(void *user_data, const u8 *tx_data, u32 num_tx_bytes, + adi_apollo_hal_txn_config_t *txn_config) +{ + struct axiadc_converter *conv = user_data; + struct ad9088_phy *phy = conv->phy; + int ret; + + dev_dbg(&phy->spi->dev, "%s:%d\n", __func__, __LINE__); + + ret = axi_hsci_writem(phy->hsci, tx_data, num_tx_bytes, + txn_config->addr_len, txn_config->data_len, txn_config->stream_len); + + return ret; +} + +static int ad9088_input_gpio(struct gpio_chip *chip, unsigned int offset) +{ + struct ad9088_phy *phy = gpiochip_get_data(chip); + + guard(mutex)(&phy->lock); + + return adi_apollo_gpio_cmos_gpio_mode_set(&phy->ad9088, phy->gpios_exported[offset], + ADI_APOLLO_GPIO_DIR_INPUT); +} + +static int ad9088_output_gpio(struct gpio_chip *chip, + unsigned int offset, int value) +{ + struct ad9088_phy *phy = gpiochip_get_data(chip); + int ret; + + guard(mutex)(&phy->lock); + + ret = adi_apollo_gpio_cmos_output_set(&phy->ad9088, phy->gpios_exported[offset], value); + if (ret < 0) + return ret; + + return adi_apollo_gpio_cmos_gpio_mode_set(&phy->ad9088, phy->gpios_exported[offset], + ADI_APOLLO_GPIO_DIR_OUTPUT); +} + +static int ad9088_get_gpio(struct gpio_chip *chip, unsigned int offset) +{ + struct ad9088_phy *phy = gpiochip_get_data(chip); + u8 val; + int ret; + + guard(mutex)(&phy->lock); + + ret = adi_apollo_gpio_cmos_input_get(&phy->ad9088, phy->gpios_exported[offset], &val); + if (ret < 0) + return ret; + + return !!val; +} + +static void ad9088_set_gpio(struct gpio_chip *chip, unsigned int offset, int value) +{ + struct ad9088_phy *phy = gpiochip_get_data(chip); + + guard(mutex)(&phy->lock); + + adi_apollo_gpio_cmos_output_set(&phy->ad9088, phy->gpios_exported[offset], value); +} + +static int ad9088_gpio_setup(struct ad9088_phy *phy) +{ + int ret, len; + + len = device_property_count_u8(&phy->spi->dev, "adi,gpio-exports"); + if (len < 0 || len > ARRAY_SIZE(phy->gpios_exported)) + return -EINVAL; + + ret = device_property_read_u8_array(&phy->spi->dev, "adi,gpio-exports", + phy->gpios_exported, len); + if (ret < 0) + return ret; + + phy->gpiochip.label = "ad9088"; + phy->gpiochip.base = -1; + phy->gpiochip.ngpio = len; + phy->gpiochip.parent = &phy->spi->dev; + phy->gpiochip.can_sleep = true; + phy->gpiochip.direction_input = ad9088_input_gpio; + phy->gpiochip.direction_output = ad9088_output_gpio; + phy->gpiochip.get = ad9088_get_gpio; + phy->gpiochip.set = ad9088_set_gpio; + + return devm_gpiochip_add_data(&phy->spi->dev, &phy->gpiochip, phy); +} + +static int ad9088_fw_provider_close(adi_apollo_fw_provider_t *obj, adi_apollo_startup_fw_id_e fw_id) +{ + struct ad9088_phy *phy = (struct ad9088_phy *)obj->tag; + + release_firmware(phy->fw); + + return 0; +} + +static int ad9088_fw_provider_get(adi_apollo_fw_provider_t *obj, + adi_apollo_startup_fw_id_e fw_id, + u8 **byte_arr, uint32_t *bytes_read) +{ + struct ad9088_phy *phy = (struct ad9088_phy *)obj->tag; + struct device *dev = &phy->spi->dev; + int ret; + + static const char *fw_file[ADI_APOLLO_FW_ID_MAX] = { + "APOLLO_FW_CPU0_B.bin", + "APOLLO_FW_CPU1_B.bin", + + "app_signed_encrypted_B/flash_image_0x01030000.bin", + "app_signed_encrypted_B/flash_image_0x20000000.bin", + "app_signed_encrypted_B/flash_image_0x02000000.bin", + "app_signed_encrypted_B/flash_image_0x21000000.bin", + + "app_signed_encrypted_prod_B/flash_image_0x01030000.bin", + "app_signed_encrypted_prod_B/flash_image_0x20000000.bin", + "app_signed_encrypted_prod_B/flash_image_0x02000000.bin", + "app_signed_encrypted_prod_B/flash_image_0x21000000.bin" + }; + + ret = request_firmware(&phy->fw, fw_file[fw_id], dev); + if (ret) { + dev_err(dev, "request_firmware() failed with %d\n", ret); + return ret; + } + + *byte_arr = (u8 *)phy->fw->data; + *bytes_read = phy->fw->size; + + return 0; +} + +static int ad9088_probe(struct spi_device *spi) +{ + struct clock_scale devclk_clkscale; + struct ad9088_jesd204_priv *priv; + struct axiadc_converter *conv; + struct jesd204_dev *jdev; + struct gpio_desc *reset; + struct ad9088_phy *phy; + u16 api_rev[3]; + int ret; + + jdev = devm_jesd204_dev_register(&spi->dev, &jesd204_ad9088_init); + if (IS_ERR(jdev)) + return PTR_ERR(jdev); + if (!jdev) + return dev_err_probe(&spi->dev, -ENODEV, "Failed to register jesd204-fsm device"); + + conv = devm_kzalloc(&spi->dev, sizeof(*conv), GFP_KERNEL); + if (!conv) + return -ENOMEM; + + phy = devm_kzalloc(&spi->dev, sizeof(*phy), GFP_KERNEL); + if (!phy) + return -ENOMEM; + + phy->hsci = devm_axi_hsci_get_optional(&spi->dev); + if (IS_ERR(phy->hsci)) + return PTR_ERR(phy->hsci); + + conv->adc_clkscale.mult = 1; + conv->adc_clkscale.div = 1; + + spi_set_drvdata(spi, conv); + conv->spi = spi; + conv->phy = phy; + phy->spi = spi; + phy->jdev = jdev; + priv = jesd204_dev_priv(jdev); + priv->phy = phy; + + phy->dev_clk = devm_clk_get(&conv->spi->dev, "dev_clk"); + if (IS_ERR(phy->dev_clk)) + return PTR_ERR(phy->dev_clk); + + conv->reset_gpio = devm_gpiod_get_optional(&spi->dev, "reset", GPIOD_OUT_HIGH); + if (IS_ERR(conv->reset_gpio)) + return PTR_ERR(conv->reset_gpio); + + phy->rx1_en_gpio = devm_gpiod_get_optional(&spi->dev, "rx1-enable", GPIOD_OUT_LOW); + if (IS_ERR(phy->rx1_en_gpio)) + return PTR_ERR(phy->rx1_en_gpio); + + phy->rx2_en_gpio = devm_gpiod_get_optional(&spi->dev, "rx2-enable", GPIOD_OUT_LOW); + if (IS_ERR(phy->rx2_en_gpio)) + return PTR_ERR(phy->rx2_en_gpio); + + phy->tx1_en_gpio = devm_gpiod_get_optional(&spi->dev, "tx1-enable", GPIOD_OUT_LOW); + if (IS_ERR(phy->tx1_en_gpio)) + return PTR_ERR(phy->tx1_en_gpio); + + phy->tx2_en_gpio = devm_gpiod_get_optional(&spi->dev, "tx2-enable", GPIOD_OUT_LOW); + if (IS_ERR(phy->tx2_en_gpio)) + return PTR_ERR(phy->tx2_en_gpio); + + phy->triq_req_gpio = devm_gpiod_get_optional(&spi->dev, "trig-req", GPIOD_OUT_LOW); + if (IS_ERR(phy->triq_req_gpio)) + return PTR_ERR(phy->triq_req_gpio); + + reset = devm_gpiod_get_optional(&spi->dev, "versal-transceiver-reset", GPIOD_OUT_HIGH); + if (IS_ERR(reset)) + return PTR_ERR(reset); + + ret = ad9088_iio_get_optional_channel(phy, &phy->iio_adf4030, "bsync"); + if (ret) + return ret; + + ret = ad9088_iio_get_optional_channel(phy, &phy->iio_adf4382, "clk"); + if (ret) + return ret; + + ret = devm_mutex_init(&spi->dev, &phy->lock); + if (ret) + return ret; + + ret = ad9088_parse_dt(phy); + if (ret < 0) + return dev_err_probe(&spi->dev, ret, "Parsing devicetree failed\n"); + + ret = devm_regulator_get_enable(&spi->dev, "vdd"); + if (ret) + return dev_err_probe(&spi->dev, ret, + "failed to get the vdd supply regulator\n"); + + of_clk_get_scale(spi->dev.of_node, "dev_clk", &devclk_clkscale); + + clk_set_rate_scaled(phy->dev_clk, + phy->profile.clk_cfg.dev_clk_freq_Hz, + &devclk_clkscale); + + ret = clk_prepare_enable(phy->dev_clk); + if (ret) + return ret; + + phy->ad9088.hal_info.spi0_desc.spi_config.sdo = (spi->mode & SPI_3WIRE || phy->spi_3wire_en) ? + ADI_APOLLO_DEVICE_SPI_SDIO : + ADI_APOLLO_DEVICE_SPI_SDO; + phy->ad9088.hal_info.spi0_desc.spi_config.msb = (spi->mode & SPI_LSB_FIRST) ? + ADI_APOLLO_DEVICE_SPI_MSB_LAST : + ADI_APOLLO_DEVICE_SPI_MSB_FIRST; + phy->ad9088.hal_info.spi0_desc.spi_config.addr_inc = ADI_APOLLO_DEVICE_SPI_ADDR_INC_AUTO; + + phy->ad9088.hal_info.spi0_desc.is_used = 1; + phy->ad9088.hal_info.spi0_desc.dev_obj = conv; + phy->ad9088.hal_info.user_data = conv; + phy->ad9088.hal_info.delay_us = ad9088_udelay; + phy->ad9088.hal_info.spi0_desc.read = ad9088_spi_read; + phy->ad9088.hal_info.spi0_desc.write = ad9088_spi_write; + phy->ad9088.hal_info.spi0_desc.xfer = ad9088_spi_xfer; + phy->ad9088.hal_info.reset_pin_ctrl = ad9088_reset_pin_ctrl; + phy->ad9088.hal_info.log_write = ad9088_log_write; + + phy->fw_provider.desc = "Linux Firmware Provider"; + phy->fw_provider.tag = phy; + + phy->ad9088.startup_info.get = ad9088_fw_provider_get; + phy->ad9088.startup_info.close = ad9088_fw_provider_close; + phy->ad9088.startup_info.open = NULL; + phy->ad9088.startup_info.fw_provider = &phy->fw_provider; + + if (phy->hsci) { + phy->ad9088.hal_info.hsci_desc.is_used = 1; + phy->ad9088.hal_info.hsci_desc.dev_obj = conv; + phy->ad9088.hal_info.hsci_desc.hsci_config.auto_linkup_en = phy->hsci_use_auto_linkup_mode; + phy->ad9088.hal_info.hsci_desc.hsci_config.addr_inc = ADI_APOLLO_DEVICE_HSCI_ADDR_INC_AUTO; + phy->ad9088.hal_info.hsci_desc.manual_linkup = &ad9088_hsci_manual_linkup; + phy->ad9088.hal_info.hsci_desc.auto_linkup = &ad9088_hsci_auto_linkup; + phy->ad9088.hal_info.hsci_desc.alink_tbl_get = &ad9088_hsci_alink_tbl_get; + phy->ad9088.hal_info.hsci_desc.read = &ad9088_hsci_read; + phy->ad9088.hal_info.hsci_desc.write = &ad9088_hsci_write; + phy->ad9088.hal_info.hsci_desc.poll_read = NULL; + phy->ad9088.hal_info.hsci_desc.buff = phy->hsci_buf; + phy->ad9088.hal_info.hsci_desc.buff_len = sizeof(phy->hsci_buf); + } + + ret = adi_apollo_device_hw_open(&phy->ad9088, + conv->reset_gpio ? ADI_APOLLO_HARD_RESET_AND_INIT : + ADI_APOLLO_SOFT_RESET_AND_INIT); + if (ret < 0) + return dev_err_probe(&spi->dev, ret, "reset/init failed\n"); + + ret = adi_apollo_hal_active_protocol_set(&phy->ad9088, ADI_APOLLO_HAL_PROTOCOL_SPI0); + if (ret < 0) + return dev_err_probe(&spi->dev, ret, "SPI active protocol set failed\n"); + + ret = adi_apollo_hal_rmw_enable_set(&phy->ad9088, ADI_APOLLO_HAL_PROTOCOL_SPI0, 0); + if (ret < 0) + return dev_err_probe(&spi->dev, ret, "SPI rmw enable failed\n"); + + if (phy->hsci) { + ret = adi_apollo_hal_rmw_enable_set(&phy->ad9088, ADI_APOLLO_HAL_PROTOCOL_HSCI, 0); + if (ret < 0) + return dev_err_probe(&spi->dev, ret, "HSCI rmw enable failed\n"); + + ret = adi_apollo_hal_active_protocol_set(&phy->ad9088, + ADI_APOLLO_HAL_PROTOCOL_HSCI); + if (ret < 0) + return dev_err_probe(&spi->dev, ret, "HSCI active protocol set failed\n"); + } + + ad9088_clk_register(phy, "-rx_sampl_clk", + __clk_get_name(phy->dev_clk), NULL, + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED, + RX_SAMPL_CLK); + + ad9088_clk_register(phy, "-tx_sampl_clk", + __clk_get_name(phy->dev_clk), NULL, + CLK_GET_RATE_NOCACHE | CLK_IGNORE_UNUSED, + TX_SAMPL_CLK); + + phy->clk_data.clks = phy->clks; + phy->clk_data.clk_num = NUM_AD9088_CLKS; + + ret = of_clk_add_provider(spi->dev.of_node, of_clk_src_onecell_get, + &phy->clk_data); + + phy->loopback_mode[0] = ADI_APOLLO_LOOPBACK_NONE; + phy->loopback_mode[1] = ADI_APOLLO_LOOPBACK_NONE; + phy->lb1_blend[0] = 0; + phy->lb1_blend[1] = 0; + + switch (spi_get_device_id(spi)->driver_data & CHIPID_MASK) { + case CHIPID_AD9084: + case CHIPID_AD9088: + ret = ad9088_reg_test(&phy->ad9088); + if (ret) + break; + + ret = ad9088_setup(phy); + if (ret) { + ad9088_reg_test(&phy->ad9088); + goto out_clk_del_provider; + } + + conv->id = phy->chip_id.prod_id; + conv->chip_info = &phy->chip_info; + ret = ad9088_setup_chip_info_tbl(phy, phy->complex_rx, phy->complex_tx, + jesd204_dev_is_top(jdev)); + if (ret) + goto out_clk_del_provider; + break; + default: + return dev_err_probe(&spi->dev, -ENODEV, "Unrecognized CHIP_ID 0x%X\n", conv->id); + } + + conv->clk = phy->clks[RX_SAMPL_CLK]; + conv->reg_access = ad9088_reg_access; + conv->write_raw = ad9088_write_raw; + conv->read_raw = ad9088_read_raw; + conv->read_label = ad9088_read_label; + + conv->post_setup = ad9088_post_setup; + conv->post_iio_register = ad9088_post_iio_register; + + conv->attrs = &ad9088_phy_attribute_group; + + if (phy->standalone || !jesd204_dev_is_top(jdev)) { + ret = ad9088_register_iiodev(conv); + if (ret) + goto out_clk_del_provider; + } + + ret = ad9088_request_fd_irqs(conv); + if (ret < 0) + dev_warn(&spi->dev, + "Failed to request FastDetect IRQs (%d)", ret); + + adi_apollo_device_api_revision_get(&phy->ad9088, &api_rev[0], + &api_rev[1], &api_rev[2]); + + dev_info(&spi->dev, "AD%X Rev. %u Grade %u (API %u.%u.%u) probed\n", + phy->chip_id.prod_id, phy->chip_id.dev_revision, + phy->chip_id.prod_grade, api_rev[0], api_rev[1], api_rev[2]); + + if (reset) { + ad9088_udelay(NULL, 100000); + gpiod_set_value_cansleep(reset, 0); + } + + ret = ad9088_bmem_probe(phy); + if (ret) + return ret; + + if (phy->sniffer_en) { + ret = ad9088_fft_sniffer_probe(phy, ADI_APOLLO_SIDE_A); + if (ret) + goto out_clk_del_provider; + + ret = ad9088_fft_sniffer_probe(phy, ADI_APOLLO_SIDE_B); + if (ret) + goto out_clk_del_provider; + } + + ret = ad9088_ffh_probe(phy); + if (ret) + return ret; + + ret = ad9088_gpio_setup(phy); + if (ret) + return ret; + + ret = jesd204_fsm_start(jdev, JESD204_LINKS_ALL); + if (ret) + goto out_clk_del_provider; + + return 0; + +out_clk_del_provider: + of_clk_del_provider(spi->dev.of_node); + + return ret; +} + +static void ad9088_remove(struct spi_device *spi) +{ + struct axiadc_converter *conv = spi_get_drvdata(spi); + struct ad9088_phy *phy = conv->phy; + + cancel_delayed_work_sync(&phy->dwork); + + if (phy->standalone || !jesd204_dev_is_top(phy->jdev)) + iio_device_unregister(conv->indio_dev); + + clk_disable_unprepare(phy->dev_clk); + of_clk_del_provider(spi->dev.of_node); + adi_apollo_hal_hw_close(&phy->ad9088); +} + +static const struct spi_device_id ad9088_id[] = { + { "ad9084", CHIPID_AD9084 }, + { "ad9088", CHIPID_AD9088 }, + {} +}; +MODULE_DEVICE_TABLE(spi, ad9088_id); + +static const struct of_device_id ad9088_of_match[] = { + { .compatible = "adi,ad9084" }, + { .compatible = "adi,ad9088" }, + {}, +}; +MODULE_DEVICE_TABLE(of, ad9088_of_match); + +static struct spi_driver ad9088_driver = { + .driver = { + .name = "ad9088", + .of_match_table = of_match_ptr(ad9088_of_match), + }, + .probe = ad9088_probe, + .remove = ad9088_remove, + .id_table = ad9088_id, +}; +module_spi_driver(ad9088_driver); + +MODULE_AUTHOR("Michael Hennerich "); +MODULE_DESCRIPTION("Analog Devices AD9088 MxFE"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/iio/trx-rf/ad9088/ad9088.h b/drivers/iio/trx-rf/ad9088/ad9088.h new file mode 100644 index 00000000000000..c933f816007765 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/ad9088.h @@ -0,0 +1,436 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Driver for AD9088 and similar mixed signal front end (MxFE®) + * + * Copyright 2026 Analog Devices Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include + +#define JESD204_OF_PREFIX "adi," +#include +#include +#include "adi_apollo_bf_serdes_txdig_phy_core1p2.h" +#include "adi_apollo_bf_serdes_rxdig_phy_core1p3.h" +#include "public/inc/adi_apollo.h" +#include "adi_apollo_bf_custom.h" +#include "adi_apollo_adc.h" +#include "adi_apollo_hal.h" +#include "adi_apollo_mailbox.h" +#include "adi_apollo_loopback.h" +#include "adi_apollo_utils.h" + +#include "adi_apollo_bf_mcs_sync.h" +#include "adi_apollo_bf_txrx_prefsrc_reconf.h" +#include "adi_apollo_bf_master_bias_ctrl.h" +#include "adi_apollo_sniffer.h" +#include "public/src/adi_apollo_nco_local.h" +#include "adi_apollo_bf_txrx_coarse_nco.h" +#include "adi_utils.h" + +#include "adi_utils/inc/adi_utils.h" +#include "public/src/adi_apollo_dformat_local.h" +#include "public/inc/adi_apollo_gpio_hop.h" + +#include "../../adc/cf_axi_adc.h" + +#include +#include "../../../misc/adi-axi-hsci.h" + +#define CHIPID_AD9084 0x9084 +#define CHIPID_AD9088 0x9088 + +#define CHIPID_MASK 0xFFFF +#define FW_TRANSFER_CHUNK_SIZE (16 * 1024) + +#define MAX_NUM_MAIN_DATAPATHS ADI_APOLLO_CNCO_NUM +#define MAX_NUM_CHANNELIZER ADI_APOLLO_FNCO_NUM +#define MAX_NUM_RX_NCO_CHAN_REGS 16 +#define MAX_NUM_TX_NCO_CHAN_REGS 31 + +#define NUM_RXTX 2 + +enum { + ADI_APOLLO_LOOPBACK_NONE, + ADI_APOLLO_LOOPBACK_0, + ADI_APOLLO_LOOPBACK_1, + ADI_APOLLO_LOOPBACK_2, + ADI_APOLLO_LOOPBACK_3, +}; + +enum { + CDDC_NCO_FREQ, + FDDC_NCO_FREQ, + CDDC_NCO_FREQ_AVAIL, + FDDC_NCO_FREQ_AVAIL, + CDDC_NCO_PHASE, + FDDC_NCO_PHASE, + CDDC_HB1_6DB_GAIN, + CDDC_TB1_6DB_GAIN, + FDDC_6DB_GAIN, + CDDC_TEST_TONE_EN, + FDDC_TEST_TONE_EN, + CDDC_TEST_TONE_OFFSET, + FDDC_TEST_TONE_OFFSET, + TRX_CONVERTER_RATE, + TRX_ENABLE, + ADC_CDDC_FFH_TRIG_HOP_EN, + ADC_FFH_GPIO_MODE_SET, + DAC_FFH_GPIO_MODE_SET, + DAC_FFH_FREQ_SET, + DAC_INVSINC_EN, + CFIR_PROFILE_SEL, + CFIR_ENABLE, + FFH_FNCO_INDEX, + FFH_FNCO_FREQUENCY, + FFH_FNCO_SELECT, + FFH_FNCO_MODE, + FFH_CNCO_INDEX, + FFH_CNCO_FREQUENCY, + FFH_CNCO_SELECT, + FFH_CNCO_MODE, + BMEM_CDDC_DELAY, + BMEM_FDDC_DELAY, +}; + +enum ad9088_iio_dev_attr { + AD9088_JESD204_FSM_ERROR, + AD9088_JESD204_FSM_PAUSED, + AD9088_JESD204_FSM_STATE, + AD9088_JESD204_FSM_RESUME, + AD9088_JESD204_FSM_CTRL, + AD9088_MCS_BG_TRACK_CAL_FREEZE, + AD9088_LOOPBACK_MODE_SIDE_A, + AD9088_LOOPBACK_MODE_SIDE_B, + AD9088_LOOPBACK1_BLEND_SIDE_A, + AD9088_LOOPBACK1_BLEND_SIDE_B, +}; + +struct ad9088_jesd204_priv { + struct ad9088_phy *phy; + bool serdes_jrx_cal_run; +}; + +enum ad9088_clocks { + RX_SAMPL_CLK, + TX_SAMPL_CLK, + RX_SAMPL_CLK_LINK2, /* Dual Link */ + NUM_AD9088_CLKS, +}; + +struct ad9088_clock { + struct clk_hw hw; + struct spi_device *spi; + struct ad9088_phy *phy; + unsigned long rate; + enum ad9088_clocks source; +}; + +#define to_clk_priv(_hw) container_of(_hw, struct ad9088_clock, hw) + +struct _ad9088_ffh { + struct { + u8 index[ADI_APOLLO_NUM_SIDES*ADI_APOLLO_FNCO_NUM]; + u64 frequency[ADI_APOLLO_FNCO_PROFILE_NUM]; + u8 select[ADI_APOLLO_NUM_SIDES*ADI_APOLLO_FNCO_NUM]; + bool en[ADI_APOLLO_NUM_SIDES*ADI_APOLLO_FNCO_NUM]; + u8 mode[ADI_APOLLO_FNCO_PROFILE_NUM]; + } fnco; + struct { + u8 index[ADI_APOLLO_NUM_SIDES*ADI_APOLLO_CNCO_NUM]; + u64 frequency[ADI_APOLLO_CNCO_PROFILE_NUM]; + u8 select[ADI_APOLLO_NUM_SIDES*ADI_APOLLO_CNCO_NUM]; + u8 mode[ADI_APOLLO_CNCO_PROFILE_NUM]; + } cnco; +}; + +union ad9088_ffh { + struct { + struct _ad9088_ffh rx; + struct _ad9088_ffh tx; + }; + struct _ad9088_ffh dir[2]; +}; + +struct ad9088_debugfs_entry { + struct iio_dev *indio_dev; + const char *propname; + void *out_value; + u32 val; + s64 delta_t; + u8 size; + u8 cmd; +}; + +/** + * struct ad9088_chan_map - IIO channel to hardware block mapping + * @fddc_num: FDDC number (0-7 per side) + * @fddc_mask: FDDC bitmask (ADI_APOLLO_FDDC_Ax or ADI_APOLLO_FDDC_Bx) + * @cddc_num: CDDC number (0-3 per side for 8T8R, 0-1 for 4T4R) + * @cddc_mask: CDDC bitmask (ADI_APOLLO_CNCO_Ax or ADI_APOLLO_CNCO_Bx) + * @adcdac_num: ADC/DAC number (0-3 per side) + * @adcdac_mask: ADC/DAC bitmask (ADI_APOLLO_ADC_Ax or ADI_APOLLO_DAC_Ax) + * @side: Chip side (0=A, 1=B) + * + * Pre-computed mapping from IIO channel to hardware blocks. + * Derived from profile mux configuration at init time. + */ +struct ad9088_chan_map { + u8 fddc_num; + u32 fddc_mask; + u8 cddc_num; + u32 cddc_mask; + u8 adcdac_num; + u32 adcdac_mask; + u8 side; +}; + +struct ad9088_phy { + struct spi_device *spi; + struct jesd204_dev *jdev; + const struct firmware *fw; + adi_apollo_device_t ad9088; + adi_apollo_top_t profile; + adi_cms_chip_id_t chip_id; + struct axiadc_chip_info chip_info; + struct clk *dev_clk; + struct bin_attribute pfilt; + struct bin_attribute cfir; + struct bin_attribute cal_data; + struct gpio_chip gpiochip; + + struct gpio_desc *rx1_en_gpio; + struct gpio_desc *rx2_en_gpio; + struct gpio_desc *tx1_en_gpio; + struct gpio_desc *tx2_en_gpio; + struct gpio_desc *triq_req_gpio; + struct axi_hsci_state *hsci; + + struct clk *clks[NUM_AD9088_CLKS]; + struct clock_scale clkscale[NUM_AD9088_CLKS]; + struct ad9088_clock clk_priv[NUM_AD9088_CLKS]; + struct clk_onecell_data clk_data; + struct delayed_work dwork; + + /* + * Synchronize access to members of driver state, and ensure atomicity + * of consecutive regmap operations. + */ + struct mutex lock; + + bool is_initialized; + bool standalone; + bool device_profile_firmware_load; + bool side_b_use_own_tpl_en; + bool complex_tx; + bool complex_rx; + bool spi_3wire_en; + bool log_silent; + bool trig_sync_en; + bool mcs_cal_bg_tracking_run; + bool mcs_cal_bg_tracking_freeze; + bool cddc_sample_delay_en; + bool fddc_sample_delay_en; + u32 multidevice_instance_count; + u32 mcs_track_decimation; + + struct ad9088_debugfs_entry debugfs_entry[32]; + u32 ad9088_debugfs_entry_index; + + const char **rx_labels; + const char **tx_labels; + + char rx_chan_labels[MAX_NUM_CHANNELIZER][32]; + char tx_chan_labels[MAX_NUM_CHANNELIZER][32]; + + long long cnco_phase[NUM_RXTX][ADI_APOLLO_NUM_SIDES][MAX_NUM_MAIN_DATAPATHS]; + u16 cnco_test_tone_offset[NUM_RXTX][ADI_APOLLO_NUM_SIDES][MAX_NUM_MAIN_DATAPATHS]; + bool cnco_test_tone_en[NUM_RXTX][ADI_APOLLO_NUM_SIDES][MAX_NUM_MAIN_DATAPATHS]; + + long long fnco_phase[NUM_RXTX][ADI_APOLLO_NUM_SIDES][MAX_NUM_CHANNELIZER]; + u16 fnco_test_tone_offset[NUM_RXTX][ADI_APOLLO_NUM_SIDES][MAX_NUM_CHANNELIZER]; + bool fnco_test_tone_en[NUM_RXTX][ADI_APOLLO_NUM_SIDES][MAX_NUM_CHANNELIZER]; + + u8 cfir_profile[NUM_RXTX][ADI_APOLLO_CFIR_ALL][ADI_APOLLO_CFIR_DP_ALL]; + u8 cfir_enable[NUM_RXTX][ADI_APOLLO_CFIR_ALL][ADI_APOLLO_CFIR_DP_ALL]; + + u32 cddc_sample_delay[NUM_RXTX][MAX_NUM_MAIN_DATAPATHS]; + u32 fddc_sample_delay[NUM_RXTX][MAX_NUM_CHANNELIZER]; + + u32 rx_nyquist_zone; + u8 jrx_lanes[24]; + u8 jtx_lanes[24]; + u8 jrx_lanes_used; + u8 jtx_lanes_used; + + u8 rx_en_mask; + u8 tx_en_mask; + + bool hsci_use_auto_linkup_mode; + bool hsci_disable_after_initial_configuration; + bool aion_background_serial_alignment_en; + bool fnco_dual_modulus_mode_en; + bool cnco_dual_modulus_mode_en; + bool sniffer_en; + bool cal_data_loaded_from_fw; + + struct iio_channel *iio_adf4030; + struct iio_channel *iio_adf4382; + + adi_apollo_fw_provider_t fw_provider; + union ad9088_ffh ffh; + + adi_apollo_gpio_hop_profile_t gpio_hop_profile; + adi_apollo_gpio_hop_block_t gpio_hop_block; + adi_apollo_gpio_hop_side_t gpio_hop_side; + adi_apollo_gpio_hop_slice_t gpio_hop_slice; + adi_apollo_gpio_hop_terminal_t gpio_hop_terminal; + + u8 hsci_buf[ADI_APOLLO_HAL_REGIO_HSCI_STREAM_DEFAULT_SIZE]; + u8 gpios_exported[ADI_APOLLO_NUM_GPIO]; + char dbuf[1024]; + + u8 loopback_mode[ADI_APOLLO_NUM_SIDES]; + u8 lb1_blend[ADI_APOLLO_NUM_SIDES]; + + u8 *nvm_adc_cal; + u8 *adc_cal; + size_t adc_cal_len; + + /* Calibration restore buffer for multi-write accumulation */ + u8 *cal_restore_buf; + size_t cal_restore_size; + size_t cal_restore_received; + + /* Pre-computed IIO channel to hardware block mapping (indexed by chan->address) */ + struct ad9088_chan_map rx_chan_map[MAX_NUM_CHANNELIZER]; + struct ad9088_chan_map tx_chan_map[MAX_NUM_CHANNELIZER]; + + /* + * RX IIO channel scan_index remapping for lane swap compensation. + * When FPGA lane routing causes DMA buffer positions to not match + * the physical channel order, use this array to remap scan_index. + * Value at index i specifies which DMA buffer position IIO channel i + * should read from. A value of -1 means no remapping (identity). + * + * Array size: MAX_NUM_CHANNELIZER * 2 (I/Q) * max multidevice_instance_count (4) + */ +#define MAX_NUM_REMAP_CHANNELS (MAX_NUM_CHANNELIZER * 2 * 4) + s8 rx_iio_to_phy_remap[MAX_NUM_REMAP_CHANNELS]; +}; + +int ad9088_parse_dt(struct ad9088_phy *phy); +int ad9088_fft_sniffer_probe(struct ad9088_phy *phy, adi_apollo_side_select_e side_sel); +int ad9088_check_apollo_error(struct device *dev, int ret, const char *api_name); +void ad9088_print_sysref_phase(struct ad9088_phy *phy); +int ad9088_status_show(struct seq_file *file, void *offset); +int devm_ad9088_set_child_label(struct ad9088_phy *phy, struct iio_dev *child, const char *suffix); +/* JESD204 FSM interface (ad9088_jesd204_fsm.c) */ +extern const struct jesd204_dev_data jesd204_ad9088_init; + +/* Helper functions used by JESD204 FSM (ad9088.c) */ +extern const char *const ad9088_fsm_links_to_str[]; +u8 ad9088_to_link(u8 linkid); +int ad9088_inspect_jrx_link_all(struct ad9088_phy *phy); +int ad9088_inspect_jtx_link_all(struct ad9088_phy *phy); +void ad9088_print_link_phase(struct ad9088_phy *phy, struct jesd204_link *lnk); +int ad9088_jesd_tx_link_status_print(struct ad9088_phy *phy, struct jesd204_link *lnk, int retry); +int ad9088_jesd_rx_link_status_print(struct ad9088_phy *phy, struct jesd204_link *lnk, int retry); +int ad9088_iio_write_channel_ext_info(struct ad9088_phy *phy, struct iio_channel *chan, + const char *ext_name, long long val); +int ad9088_iio_read_channel_ext_info(struct ad9088_phy *phy, struct iio_channel *chan, + const char *ext_name, long long *val); +int ad9088_mcs_init_cal_setup(struct ad9088_phy *phy); +int ad9088_delta_t_measurement_set(struct ad9088_phy *phy, u32 mode); +int ad9088_delta_t_measurement_get(struct ad9088_phy *phy, u32 mode, s64 *apollo_delta_t); +int ad9088_mcs_init_cal_validate(struct ad9088_phy *phy, + adi_apollo_mcs_cal_init_status_t *init_cal_status); +int ad9088_mcs_tracking_cal_setup(struct ad9088_phy *phy, u32 mcs_track_decimation, + u16 initialize_track_cal); +int ad9088_mcs_init_cal_status_print(struct ad9088_phy *phy, char *buf, + adi_apollo_mcs_cal_init_status_t *status); +int ad9088_mcs_track_cal_status_print(struct ad9088_phy *phy, char *buf, + adi_apollo_mcs_cal_status_t *cal_status, + u8 print_full_state); +int ad9088_mcs_tracking_cal_validate(struct ad9088_phy *phy, char *buf, size_t buf_size); +int ad9088_bmem_probe(struct ad9088_phy *phy); +int adi_ad9088_calc_nco_ftw(struct ad9088_phy *phy, u64 freq, s64 nco_shift, u32 div, u32 bits, + u64 *ftw, u64 *frac_a, u64 *frac_b); +const struct ad9088_chan_map *ad9088_get_chan_map(struct ad9088_phy *phy, + const struct iio_chan_spec *chan); +int ad9088_ffh_probe(struct ad9088_phy *phy); +ssize_t ad9088_ext_info_read_ffh(struct iio_dev *indio_dev, uintptr_t private, + const struct iio_chan_spec *chan, char *buf); +ssize_t ad9088_ext_info_write_ffh(struct iio_dev *indio_dev, uintptr_t private, + const struct iio_chan_spec *chan, const char *buf, size_t len); + +/* Calibration data format */ +#define AD9088_CAL_MAGIC 0x41443930 /* "AD90" */ +#define AD9088_CAL_VERSION 2 + +struct ad9088_cal_header { + u32 magic; /* Magic number for validation */ + u32 version; /* File format version */ + u32 chip_id; /* Chip ID (0x9084 or 0x9088) */ + u8 is_8t8r; /* 1 = 8T8R, 0 = 4T4R */ + u8 num_adcs; /* Number of ADCs */ + u8 num_serdes_rx; /* Number of SERDES RX 12-packs */ + u8 num_clk_cond; /* Number of clock conditioning sides */ + u8 reserved[4]; /* Reserved for future use */ + + /* Offsets to each section (from start of file) */ + u32 adc_cal_offset; /* Offset to ADC calibration data */ + u32 serdes_rx_cal_offset; /* Offset to SERDES RX calibration data */ + u32 clk_cond_cal_offset; /* Offset to clock conditioning cal data */ + + /* Sizes of each section */ + u32 adc_cal_size; /* Total size of all ADC cal data */ + u32 serdes_rx_cal_size; /* Total size of all SERDES RX cal data */ + u32 clk_cond_cal_size; /* Total size of all clock conditioning cal data */ + + u32 total_size; /* Total file size including CRC */ + u32 reserved2[4]; /* Reserved for future use */ +} __packed; + +int ad9088_cal_save(struct ad9088_phy *phy, u8 **buf, size_t *len); +int ad9088_cal_restore(struct ad9088_phy *phy, const u8 *buf, size_t len); +int ad9088_cal_load_from_firmware(struct ad9088_phy *phy); +ssize_t ad9088_cal_data_read(struct file *filp, struct kobject *kobj, + struct bin_attribute *bin_attr, + char *buf, loff_t off, size_t count); +ssize_t ad9088_cal_data_write(struct file *filp, struct kobject *kobj, + struct bin_attribute *bin_attr, char *buf, loff_t off, size_t count); + +/* Debugfs interface (ad9088_debugfs.c) */ +#if IS_ENABLED(CONFIG_DEBUG_FS) +void ad9088_debugfs_register(struct iio_dev *indio_dev); +#else +static inline void ad9088_debugfs_register(struct iio_dev *indio_dev) {} +#endif diff --git a/drivers/iio/trx-rf/ad9088/ad9088_bmem.c b/drivers/iio/trx-rf/ad9088/ad9088_bmem.c new file mode 100644 index 00000000000000..4fa438f65da5fd --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/ad9088_bmem.c @@ -0,0 +1,862 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Driver for AD9088 BMEM (Buffer Memory) interface + * + * Copyright 2026 Analog Devices Inc. + */ + +#include "ad9088.h" + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "public/inc/adi_apollo_bmem.h" +#include "public/inc/adi_apollo_bmem_types.h" +#include "adi_apollo_bf_rx_bmem.h" + +#define AD9088_BMEM_SRAM_SIZE_BYTES (128 * 1024) /* 128KB SRAM */ +#define AD9088_BMEM_SRAM_SIZE_WORDS (32 * 1024) /* 32K 32-bit words */ +#define AD9088_BMEM_SAMPLE_SIZE_16BIT (16) +#define AD9088_BMEM_SAMPLE_SIZE_32BIT (32) + +#define TIMEOUT_US 100000 +#define POLL_DELAY_US 10 + +#define MAX_NUM_CHANNELS 8 /* 4 per side for 8T8R */ + +struct ad9088_bmem_state { + struct device *dev; + /* protect device state and shared data */ + struct mutex lock; + struct completion complete; + struct ad9088_phy *phy; + struct delayed_work capture_work; + struct iio_dev *indio_dev; + + u32 bmem_sel; + u32 bmem_loc; + u32 sample_size; + u16 start_addr; + u16 end_addr; + + u32 sample_count; + u32 delay_sample[MAX_NUM_CHANNELS]; + + /* Delay sample and hop configurations per channel */ + adi_apollo_bmem_delay_sample_t delay_sample_config[MAX_NUM_CHANNELS]; + adi_apollo_bmem_delay_hop_t delay_hop_config[MAX_NUM_CHANNELS]; + + adi_apollo_bmem_capture_t capture_config; + + /* Per-channel buffers for captured data */ + __le32 *channel_buffers[MAX_NUM_CHANNELS]; /* One buffer per channel */ + + /* Scan buffer for pushing to IIO */ + u8 scan_data[MAX_NUM_CHANNELS * sizeof(u16)]; + + /* Track which channels are enabled for capture */ + unsigned long active_channels; +}; + +static adi_apollo_bmem_sel_e ad9088_channel_to_bmem(int channel, bool is_8t8r) +{ + /* + * 8T8R: channels 0-3 are Side A (A0-A3), channels 4-7 are Side B (B0-B3) + * 4T4R: channels 0-1 are Side A (A0-A1), channels 2-3 are Side B (B0-B1) + */ + static const adi_apollo_bmem_sel_e bmem_map_8t8r[] = { + ADI_APOLLO_BMEM_A0, ADI_APOLLO_BMEM_A1, + ADI_APOLLO_BMEM_A2, ADI_APOLLO_BMEM_A3, + ADI_APOLLO_BMEM_B0, ADI_APOLLO_BMEM_B1, + ADI_APOLLO_BMEM_B2, ADI_APOLLO_BMEM_B3, + }; + static const adi_apollo_bmem_sel_e bmem_map_4t4r[] = { + ADI_APOLLO_BMEM_A0, ADI_APOLLO_BMEM_A1, + ADI_APOLLO_BMEM_B0, ADI_APOLLO_BMEM_B1, + }; + + if (is_8t8r) { + if (channel >= 0 && channel < ARRAY_SIZE(bmem_map_8t8r)) + return bmem_map_8t8r[channel]; + } else { + if (channel >= 0 && channel < ARRAY_SIZE(bmem_map_4t4r)) + return bmem_map_4t4r[channel]; + } + + return ADI_APOLLO_BMEM_A0; +} + +static u32 calc_bmem_sram_base(int bmem_index) +{ + static u32 bmem_regmap[ADI_APOLLO_BMEM_NUM] = { + 0x60240000, 0x60440000, + 0x60240000, 0x60440000, + 0x60A40000, 0x60C40000, + 0x60A40000, 0x60C40000 + }; + + return bmem_regmap[bmem_index]; +} + +static u32 calc_bmem_hsdin_base(int bmem_index) +{ + static u32 bmem_regmap[ADI_APOLLO_BMEM_NUM] = { + RX_BMEM0_REG_RX_SLICE_0_RX_DIGITAL0, RX_BMEM0_REG_RX_SLICE_1_RX_DIGITAL0, + RX_BMEM0_REG_RX_SLICE_0_RX_DIGITAL0, RX_BMEM0_REG_RX_SLICE_1_RX_DIGITAL0, + RX_BMEM0_REG_RX_SLICE_0_RX_DIGITAL1, RX_BMEM0_REG_RX_SLICE_1_RX_DIGITAL1, + RX_BMEM0_REG_RX_SLICE_0_RX_DIGITAL1, RX_BMEM0_REG_RX_SLICE_1_RX_DIGITAL1 + }; + + return bmem_regmap[bmem_index]; +} + +static int rx_mux1_config(adi_apollo_device_t *device) +{ + int err = API_CMS_ERROR_OK; + + adi_apollo_rx_mux0_sel_e cbout_to_adc_4t4r_a[] = { + ADI_APOLLO_4T4R_CB_OUT_0_FROM_ADC0, + ADI_APOLLO_4T4R_CB_OUT_1_FROM_ADC1 + }; + adi_apollo_rx_mux0_sel_e cbout_to_adc_4t4r_b[] = { + ADI_APOLLO_4T4R_CB_OUT_0_FROM_ADC0, + ADI_APOLLO_4T4R_CB_OUT_1_FROM_ADC1}; + adi_apollo_rx_mux0_sel_e cbout_to_adc_8t8r_a[] = { + ADI_APOLLO_8T8R_CB_OUT_FROM_ADC0, + ADI_APOLLO_8T8R_CB_OUT_FROM_ADC1, + ADI_APOLLO_8T8R_CB_OUT_FROM_ADC2, + ADI_APOLLO_8T8R_CB_OUT_FROM_ADC3 + }; + adi_apollo_rx_mux0_sel_e cbout_to_adc_8t8r_b[] = { + ADI_APOLLO_8T8R_CB_OUT_FROM_ADC0, + ADI_APOLLO_8T8R_CB_OUT_FROM_ADC1, + ADI_APOLLO_8T8R_CB_OUT_FROM_ADC2, + ADI_APOLLO_8T8R_CB_OUT_FROM_ADC3 + }; + + if (device->dev_info.is_8t8r) { + err = adi_apollo_rxmux_xbar1_set(device, ADI_APOLLO_SIDE_A, cbout_to_adc_8t8r_a, + ADI_APOLLO_RX_MUX0_NUM_8T8R); + ADI_CMS_ERROR_RETURN(err); + err = adi_apollo_rxmux_xbar1_set(device, ADI_APOLLO_SIDE_B, cbout_to_adc_8t8r_b, + ADI_APOLLO_RX_MUX0_NUM_8T8R); + ADI_CMS_ERROR_RETURN(err); + } else { + err = adi_apollo_rxmux_xbar1_set(device, ADI_APOLLO_SIDE_A, cbout_to_adc_4t4r_a, + ADI_APOLLO_RX_MUX0_NUM_4T4R); + ADI_CMS_ERROR_RETURN(err); + err = adi_apollo_rxmux_xbar1_set(device, ADI_APOLLO_SIDE_B, cbout_to_adc_4t4r_b, + ADI_APOLLO_RX_MUX0_NUM_4T4R); + ADI_CMS_ERROR_RETURN(err); + } + + return err; +} + +static int ad9088_hsdin_bmem_capture_run(adi_apollo_device_t *device, adi_apollo_blk_sel_t bmems) +{ + int err, regmap_base_addr = 0; + u8 i; + + ADI_CMS_NULL_PTR_CHECK(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_BMEM_BLK_SEL_MASK(bmems); + + for (i = 0; i < ADI_APOLLO_BMEM_NUM; i++) { + if ((bmems & (ADI_APOLLO_BMEM_A0 << i)) > 0) { + regmap_base_addr = calc_bmem_hsdin_base(i); + + err = adi_apollo_hal_bf_set(device, + BF_BMEM_RESET_INFO(regmap_base_addr), 1); + ADI_CMS_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_wait_to_clear(device, + BF_BMEM_RESET_INFO(regmap_base_addr), + TIMEOUT_US, POLL_DELAY_US); + ADI_CMS_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_TRIG_MODE_INFO(regmap_base_addr), 1); + ADI_CMS_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, + BF_TRIG_MODE_SCLR_EN_INFO(regmap_base_addr), 1); + ADI_CMS_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, + BF_FAST_NSLOW_MODE_INFO(regmap_base_addr), 1); + ADI_CMS_ERROR_RETURN(err); + + err = adi_apollo_hal_delay_us(device, 10000); + ADI_CMS_ERROR_RETURN(err); + } + } + + adi_apollo_trigts_trig_now(device, ADI_APOLLO_RX, ADI_APOLLO_SIDE_ALL); + + for (i = 0; i < ADI_APOLLO_BMEM_NUM; i++) { + if ((bmems & (ADI_APOLLO_BMEM_A0 << i)) > 0) { + regmap_base_addr = calc_bmem_hsdin_base(i); + + err = adi_apollo_hal_bf_wait_to_set(device, + BF_FULL_IRQ_INFO(regmap_base_addr), + TIMEOUT_US, POLL_DELAY_US); + ADI_CMS_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, + BF_FAST_NSLOW_MODE_INFO(regmap_base_addr), 0); + ADI_CMS_ERROR_RETURN(err); + + err = adi_apollo_hal_delay_us(device, 10000); + ADI_CMS_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +static int ad9088_bmem_configure_capture(struct ad9088_bmem_state *st) +{ + adi_apollo_device_t *device = &st->phy->ad9088; + int ret; + + /* Configure capture parameters */ + st->capture_config.sample_size = (st->sample_size == 32) ? 1 : 0; + st->capture_config.ramclk_ph_dis = 0; + st->capture_config.st_addr_cpt = st->start_addr; + st->capture_config.end_addr_cpt = st->end_addr; + st->capture_config.parity_check_en = 1; + + /* Configure BMEM capture */ + ret = adi_apollo_bmem_hsdin_capture_config(device, st->bmem_sel, &st->capture_config); + + adi_apollo_clk_mcs_dyn_sync_rxtxlinks_sequence_run(device); + + return ad9088_check_apollo_error(st->dev, ret, "adi_apollo_bmem_hsdin_capture_config"); +} + +static int ad9088_bmem_start_capture(struct ad9088_bmem_state *st) +{ + adi_apollo_device_t *device = &st->phy->ad9088; + int ret; + + /* Start capture operation */ + ret = ad9088_hsdin_bmem_capture_run(device, st->bmem_sel); + return ad9088_check_apollo_error(st->dev, ret, "adi_apollo_bmem_hsdin_capture_run"); +} + +static int ad9088_bmem_read_samples(struct ad9088_bmem_state *st) +{ + adi_apollo_device_t *device = &st->phy->ad9088; + int ret, ch, num_enabled = 0; + u32 i, sample_count, word_count, scan_offset; + u16 *scan_u16; + u32 words_read; + + /* Calculate number of 32-bit words to read */ + word_count = st->end_addr - st->start_addr + 1; + sample_count = st->sample_count; + + dev_dbg(st->dev, "start_addr=%u, end_addr=%u, sample_size=%u sample_count=%u\n", + st->start_addr, st->end_addr, st->sample_size, sample_count); + + /* Step 1: Read from each enabled channel/BMEM into separate buffers */ + for_each_set_bit(ch, &st->active_channels, st->indio_dev->num_channels) { + bool is_8t8r = st->phy->ad9088.dev_info.is_8t8r; + adi_apollo_blk_sel_t bmem = ad9088_channel_to_bmem(ch, is_8t8r); + + dev_dbg(st->dev, "Reading channel %d (BMEM 0x%x)\n", ch, bmem); + num_enabled++; + + words_read = 0; + + do { + u32 reg = calc_bmem_sram_base(ilog2(bmem)) + (words_read * 4); + u32 chunk = min(4096, word_count - words_read); + + ret = adi_apollo_hal_stream_reg32_get(device, reg, + &st->channel_buffers[ch][words_read], + chunk, 0); + ret = ad9088_check_apollo_error(st->dev, ret, + "adi_apollo_bmem_hsdin_capture_get"); + if (ret) { + dev_err(st->dev, "Failed to read channel %d: %d\n", ch, ret); + return ret; + } + + words_read += chunk; + } while (words_read < word_count); + } + + if (!num_enabled) { + dev_err(st->dev, "No channels were successfully read\n"); + return -EIO; + } + + /* Step 2: Demultiplex - build scan records and push to IIO buffer */ + scan_u16 = (u16 *)st->scan_data; + + for (i = 0; i < word_count; i++) { + if (sample_count--) { + scan_offset = 0; + for_each_set_bit(ch, &st->active_channels, st->indio_dev->num_channels) + scan_u16[scan_offset++] = lower_16_bits(st->channel_buffers[ch][i]); + + iio_push_to_buffers(st->indio_dev, st->scan_data); + } + + if (sample_count--) { + scan_offset = 0; + for_each_set_bit(ch, &st->active_channels, st->indio_dev->num_channels) + scan_u16[scan_offset++] = upper_16_bits(st->channel_buffers[ch][i]); + + iio_push_to_buffers(st->indio_dev, st->scan_data); + } + } + + return 0; +} + +static void ad9088_bmem_capture_work_func(struct work_struct *work) +{ + struct ad9088_bmem_state *st = container_of(work, struct ad9088_bmem_state, + capture_work.work); + int ret; + + guard(mutex)(&st->phy->lock); + + ret = ad9088_bmem_read_samples(st); + if (ret) + dev_err(st->dev, "Error reading BMEM samples: %d\n", ret); + + /* Start capture on all selected BMEMs simultaneously */ + ret = ad9088_bmem_start_capture(st); + if (ret) + dev_err(st->dev, "Error starting BMEM capture: %d\n", ret); + + /* Schedule work to read samples after a delay */ + reinit_completion(&st->complete); + queue_delayed_work(system_freezable_wq, &st->capture_work, msecs_to_jiffies(10)); +} + +static int ad9088_bmem_read_raw(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, + int *val, int *val2, long mask) +{ + struct ad9088_bmem_state *st = iio_priv(indio_dev); + bool is_8t8r = st->phy->ad9088.dev_info.is_8t8r; + int side; + int ret = 0; + u64 freq; + + guard(mutex)(&st->phy->lock); + + /* Determine side: 8T8R has 4 channels per side, 4T4R has 2 per side */ + side = is_8t8r ? (chan->channel >= 4) : (chan->channel >= 2); + + switch (mask) { + case IIO_CHAN_INFO_SAMP_FREQ: + freq = st->phy->profile.adc_cfg[side].adc_sampling_rate_Hz; + *val = lower_32_bits(freq); + *val2 = upper_32_bits(freq); + ret = IIO_VAL_INT_64; + return 0; + default: + return -EINVAL; + } +} + +static ssize_t ad9088_bmem_ext_info_read(struct iio_dev *indio_dev, + uintptr_t private, + const struct iio_chan_spec *chan, + char *buf) +{ + struct ad9088_bmem_state *st = iio_priv(indio_dev); + int i, ch = chan->channel; + ssize_t len = 0; + + guard(mutex)(&st->phy->lock); + + switch (private) { + case 0: /* delay_sample - simple set function */ + return sysfs_emit(buf, "%u\n", st->delay_sample[ch]); + case 1: /* delay_sample_config_value - from delay_sample_config structure */ + return sysfs_emit(buf, "%u\n", st->delay_sample_config[ch].sample_delay); + case 2: /* delay_sample_parity_check_en */ + return sysfs_emit(buf, "%u\n", st->delay_sample_config[ch].parity_check_en); + case 3: /* delay_hop_array - 4 values */ + for (i = 0; i < ADI_APOLLO_BMEM_HOP_PROFILES; i++) { + len += sysfs_emit_at(buf, len, "%u%s", + st->delay_hop_config[ch].hop_delay[i], + (i < ADI_APOLLO_BMEM_HOP_PROFILES - 1) ? " " : "\n"); + } + return len; + case 4: /* delay_hop_sel_mode */ + return sysfs_emit(buf, "%u\n", st->delay_hop_config[ch].hop_delay_sel_mode); + case 5: /* delay_hop_trig_sclr_en */ + return sysfs_emit(buf, "%u\n", st->delay_hop_config[ch].trig_mode_sclr_en); + case 6: /* delay_hop_parity_check_en */ + return sysfs_emit(buf, "%u\n", st->delay_hop_config[ch].parity_check_en); + case 7: /* delay_start - write-only, returns 0 on read */ + return sysfs_emit(buf, "0\n"); + default: + return -EINVAL; + } +} + +static ssize_t ad9088_bmem_ext_info_write(struct iio_dev *indio_dev, + uintptr_t private, + const struct iio_chan_spec *chan, + const char *buf, size_t len) +{ + struct ad9088_bmem_state *st = iio_priv(indio_dev); + bool is_8t8r = st->phy->ad9088.dev_info.is_8t8r; + long long readin; + int ret, ch = chan->channel; + u32 bmem_sel = ad9088_channel_to_bmem(ch, is_8t8r); + char *token, *buf_copy; + int count = 0; + + guard(mutex)(&st->phy->lock); + + switch (private) { + case 0: /* delay_sample - simple set function */ + ret = kstrtoll(buf, 10, &readin); + if (ret) + return ret; + + ret = adi_apollo_bmem_hsdin_delay_sample_set(&st->phy->ad9088, bmem_sel, readin); + ret = ad9088_check_apollo_error(st->dev, ret, + "adi_apollo_bmem_hsdin_delay_sample_set"); + if (ret) + return ret; + + st->delay_sample[ch] = readin; + return len; + case 1: /* delay_sample_config_value - updates structure and applies full config */ + ret = kstrtoll(buf, 10, &readin); + if (ret) + return ret; + + st->delay_sample_config[ch].sample_delay = readin; + ret = adi_apollo_bmem_hsdin_delay_sample_config(&st->phy->ad9088, bmem_sel, + &st->delay_sample_config[ch]); + ret = ad9088_check_apollo_error(st->dev, ret, + "adi_apollo_bmem_hsdin_delay_sample_config"); + if (ret) + return ret; + + st->delay_sample[ch] = readin; + return len; + case 2: /* delay_sample_parity_check_en */ + ret = kstrtoll(buf, 10, &readin); + if (ret) + return ret; + + st->delay_sample_config[ch].parity_check_en = readin ? 1 : 0; + ret = adi_apollo_bmem_hsdin_delay_sample_config(&st->phy->ad9088, bmem_sel, + &st->delay_sample_config[ch]); + ret = ad9088_check_apollo_error(st->dev, ret, + "adi_apollo_bmem_hsdin_delay_sample_config"); + if (ret) + return ret; + + return len; + case 3: { + char *ptr; + + /* delay_hop_array - expects exactly 4 space-separated values */ + buf_copy = kstrdup(buf, GFP_KERNEL); + if (!buf_copy) + return -ENOMEM; + + ptr = buf_copy; + /* Parse space-separated list of exactly 4 delay values */ + while ((token = strsep(&ptr, " \n")) && count < ADI_APOLLO_BMEM_HOP_PROFILES) { + u16 val; + + if (*token == '\0') + continue; + + ret = kstrtou16(token, 10, &val); + if (ret) { + kfree(buf_copy); + return ret; + } + + st->delay_hop_config[ch].hop_delay[count++] = val; + } + + kfree(buf_copy); + + if (count != ADI_APOLLO_BMEM_HOP_PROFILES) { + dev_err(st->dev, "delay_hop_array requires exactly 4 values, got %d\n", + count); + return -EINVAL; + } + + /* Apply to hardware */ + ret = adi_apollo_bmem_hsdin_delay_hop_set(&st->phy->ad9088, bmem_sel, + st->delay_hop_config[ch].hop_delay, + ADI_APOLLO_BMEM_HOP_PROFILES); + ret = ad9088_check_apollo_error(st->dev, ret, + "adi_apollo_bmem_hsdin_delay_hop_set"); + if (ret) + return ret; + + return len; + } + case 4: /* delay_hop_sel_mode */ + ret = kstrtoll(buf, 10, &readin); + if (ret) + return ret; + + st->delay_hop_config[ch].hop_delay_sel_mode = readin; + ret = adi_apollo_bmem_hsdin_delay_hop_config(&st->phy->ad9088, bmem_sel, + &st->delay_hop_config[ch]); + ret = ad9088_check_apollo_error(st->dev, ret, + "adi_apollo_bmem_hsdin_delay_hop_config"); + if (ret) + return ret; + + return len; + case 5: /* delay_hop_trig_sclr_en */ + ret = kstrtoll(buf, 10, &readin); + if (ret) + return ret; + + st->delay_hop_config[ch].trig_mode_sclr_en = readin ? 1 : 0; + ret = adi_apollo_bmem_hsdin_delay_hop_config(&st->phy->ad9088, bmem_sel, + &st->delay_hop_config[ch]); + ret = ad9088_check_apollo_error(st->dev, ret, + "adi_apollo_bmem_hsdin_delay_hop_config"); + if (ret) + return ret; + + return len; + case 6: /* delay_hop_parity_check_en */ + ret = kstrtoll(buf, 10, &readin); + if (ret) + return ret; + + st->delay_hop_config[ch].parity_check_en = readin ? 1 : 0; + ret = adi_apollo_bmem_hsdin_delay_hop_config(&st->phy->ad9088, bmem_sel, + &st->delay_hop_config[ch]); + ret = ad9088_check_apollo_error(st->dev, ret, + "adi_apollo_bmem_hsdin_delay_hop_config"); + if (ret) + return ret; + + return len; + case 7: /* delay_start - trigger delay start for this channel's BMEM */ + ret = kstrtoll(buf, 10, &readin); + if (ret) + return ret; + + if (readin) { + ret = adi_apollo_bmem_hsdin_delay_start(&st->phy->ad9088, bmem_sel); + ret = ad9088_check_apollo_error(st->dev, ret, + "adi_apollo_bmem_hsdin_delay_start"); + if (ret) + return ret; + } + return len; + default: + return -EINVAL; + } +} + +static struct iio_chan_spec_ext_info ad9088_bmem_ext_info[] = { + { + .name = "delay_sample", + .read = ad9088_bmem_ext_info_read, + .write = ad9088_bmem_ext_info_write, + .shared = IIO_SEPARATE, + .private = 0, + }, + { + .name = "delay_sample_config_value", + .read = ad9088_bmem_ext_info_read, + .write = ad9088_bmem_ext_info_write, + .shared = IIO_SEPARATE, + .private = 1, + }, + { + .name = "delay_sample_parity_check_en", + .read = ad9088_bmem_ext_info_read, + .write = ad9088_bmem_ext_info_write, + .shared = IIO_SEPARATE, + .private = 2, + }, + { + .name = "delay_hop_array", + .read = ad9088_bmem_ext_info_read, + .write = ad9088_bmem_ext_info_write, + .shared = IIO_SEPARATE, + .private = 3, + }, + { + .name = "delay_hop_sel_mode", + .read = ad9088_bmem_ext_info_read, + .write = ad9088_bmem_ext_info_write, + .shared = IIO_SEPARATE, + .private = 4, + }, + { + .name = "delay_hop_trig_sclr_en", + .read = ad9088_bmem_ext_info_read, + .write = ad9088_bmem_ext_info_write, + .shared = IIO_SEPARATE, + .private = 5, + }, + { + .name = "delay_hop_parity_check_en", + .read = ad9088_bmem_ext_info_read, + .write = ad9088_bmem_ext_info_write, + .shared = IIO_SEPARATE, + .private = 6, + }, + { + .name = "delay_start", + .read = ad9088_bmem_ext_info_read, + .write = ad9088_bmem_ext_info_write, + .shared = IIO_SEPARATE, + .private = 7, + }, + {}, +}; + +/* Channel template for dynamic channel allocation */ +static const struct iio_chan_spec ad9088_bmem_channel_template = { + .type = IIO_VOLTAGE, + .info_mask_separate = BIT(IIO_CHAN_INFO_SAMP_FREQ), + .ext_info = ad9088_bmem_ext_info, + .indexed = 1, + .scan_type = { + .sign = 's', + .realbits = 16, + .storagebits = 16, + .shift = 0, + .endianness = IIO_LE, + }, +}; + +static int ad9088_bmem_debugfs_reg_access(struct iio_dev *indio_dev, + unsigned int reg, unsigned int writeval, + unsigned int *readval) +{ + struct ad9088_bmem_state *st = iio_priv(indio_dev); + struct ad9088_phy *phy = st->phy; + u8 val; + int ret; + + guard(mutex)(&st->phy->lock); + + if (!readval) { + ret = adi_apollo_hal_reg_set(&phy->ad9088, reg, writeval); + return ad9088_check_apollo_error(st->dev, ret, "adi_apollo_hal_reg_set"); + } + + ret = adi_apollo_hal_reg_get(&phy->ad9088, reg, &val); + ret = ad9088_check_apollo_error(st->dev, ret, "adi_apollo_hal_reg_get"); + if (ret) + return ret; + + *readval = val; + return 0; +} + +static const struct iio_info ad9088_bmem_info = { + .read_raw = &ad9088_bmem_read_raw, + .debugfs_reg_access = &ad9088_bmem_debugfs_reg_access, +}; + +static int ad9088_bmem_buffer_postenable(struct iio_dev *indio_dev) +{ + struct ad9088_bmem_state *st = iio_priv(indio_dev); + struct ad9088_phy *phy = st->phy; + bool is_8t8r = phy->ad9088.dev_info.is_8t8r; + adi_apollo_blk_sel_t bmem_mask = 0; + int ret, i; + + guard(mutex)(&st->phy->lock); + + dev_dbg(st->dev, "%s: buffer length: %d\n", __func__, indio_dev->buffer->length); + + st->end_addr = st->start_addr + DIV_ROUND_UP(indio_dev->buffer->length, + 2 * indio_dev->num_channels) - 1; + + st->sample_count = indio_dev->buffer->length / indio_dev->num_channels; + + rx_mux1_config(&phy->ad9088); + + /* Save which channels are active and build BMEM bitmask */ + st->active_channels = *indio_dev->active_scan_mask; + + for_each_set_bit(i, &st->active_channels, indio_dev->num_channels) + bmem_mask |= ad9088_channel_to_bmem(i, is_8t8r); + + dev_dbg(st->dev, "Configuring BMEMs with mask 0x%x\n", bmem_mask); + + /* Store the mask for later use */ + st->bmem_sel = bmem_mask; + + ret = adi_apollo_trigts_bmem_trig_sel_mux_set(&phy->ad9088, ADI_APOLLO_RX, bmem_mask, + ADI_APOLLO_TRIG_SPI); + if (ret) + return ret; + + /* Configure capture parameters for all selected BMEMs */ + ret = ad9088_bmem_configure_capture(st); + if (ret) + return ret; + + /* Start capture on all selected BMEMs simultaneously */ + ret = ad9088_bmem_start_capture(st); + if (ret) + return ret; + + /* Schedule work to read samples after a delay */ + reinit_completion(&st->complete); + queue_delayed_work(system_freezable_wq, &st->capture_work, msecs_to_jiffies(100)); + + return 0; +} + +static int ad9088_bmem_buffer_predisable(struct iio_dev *indio_dev) +{ + struct ad9088_bmem_state *st = iio_priv(indio_dev); + + complete_all(&st->complete); + cancel_delayed_work_sync(&st->capture_work); + + return 0; +} + +static const struct iio_buffer_setup_ops ad9088_bmem_buffer_ops = { + .postenable = ad9088_bmem_buffer_postenable, + .predisable = ad9088_bmem_buffer_predisable, +}; + +static void ad9088_bmem_debugfs_init(struct iio_dev *indio_dev) +{ + struct ad9088_bmem_state *st = iio_priv(indio_dev); + struct dentry *d; + + d = iio_get_debugfs_dentry(indio_dev); + if (!d) + return; + + debugfs_create_u32("bmem_sel", 0644, d, &st->bmem_sel); + debugfs_create_u32("bmem_loc", 0644, d, &st->bmem_loc); + debugfs_create_u16("start_addr", 0644, d, &st->start_addr); + debugfs_create_u16("end_addr", 0644, d, &st->end_addr); + debugfs_create_u32("sample_size", 0644, d, &st->sample_size); +} + +int ad9088_bmem_probe(struct ad9088_phy *phy) +{ + struct iio_dev *indio_dev; + struct ad9088_bmem_state *st; + struct device *dev = &phy->spi->dev; + struct iio_chan_spec *channels; + bool is_8t8r = phy->ad9088.dev_info.is_8t8r; + int num_channels = is_8t8r ? 8 : 4; + int ret, i; + + indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); + if (!indio_dev) + return -ENOMEM; + + st = iio_priv(indio_dev); + st->dev = dev; + st->phy = phy; + st->indio_dev = indio_dev; + + /* Initialize default configuration */ + st->bmem_sel = ADI_APOLLO_BMEM_A0; + st->bmem_loc = ADI_APOLLO_BMEM_HSDIN; + st->sample_size = 16; + st->start_addr = 0; + + /* Initialize delay configurations for each channel */ + for (i = 0; i < num_channels; i++) { + st->delay_sample[i] = 0; + + /* Initialize delay_sample_config */ + st->delay_sample_config[i].sample_size = 0; /* 0: 16-bit */ + st->delay_sample_config[i].ramclk_ph_dis = 0; + st->delay_sample_config[i].sample_delay = 0; + st->delay_sample_config[i].parity_check_en = 1; + + /* Initialize delay_hop_config */ + st->delay_hop_config[i].sample_size = 0; /* 0: 16-bit */ + st->delay_hop_config[i].ramclk_ph_dis = 0; + st->delay_hop_config[i].hop_delay[0] = 0; + st->delay_hop_config[i].hop_delay[1] = 0; + st->delay_hop_config[i].hop_delay[2] = 0; + st->delay_hop_config[i].hop_delay[3] = 0; + st->delay_hop_config[i].hop_delay_sel_mode = 0; /* 0: cycle through profiles */ + st->delay_hop_config[i].trig_mode_sclr_en = 1; + st->delay_hop_config[i].parity_check_en = 1; + } + + ret = devm_mutex_init(dev, &st->lock); + if (ret) + return ret; + + init_completion(&st->complete); + INIT_DELAYED_WORK(&st->capture_work, ad9088_bmem_capture_work_func); + + /* Allocate per-channel buffers for captured samples */ + for (i = 0; i < num_channels; i++) { + st->channel_buffers[i] = devm_kzalloc(dev, AD9088_BMEM_SRAM_SIZE_BYTES, GFP_KERNEL); + if (!st->channel_buffers[i]) + return -ENOMEM; + } + + /* Dynamically allocate channels based on 8T8R/4T4R mode */ + channels = devm_kcalloc(dev, num_channels, sizeof(*channels), GFP_KERNEL); + if (!channels) + return -ENOMEM; + + for (i = 0; i < num_channels; i++) { + channels[i] = ad9088_bmem_channel_template; + channels[i].channel = i; + channels[i].scan_index = i; + } + + indio_dev->info = &ad9088_bmem_info; + indio_dev->modes = INDIO_DIRECT_MODE; + indio_dev->channels = channels; + indio_dev->num_channels = num_channels; + indio_dev->name = "ad9088-bmem"; + + ret = devm_ad9088_set_child_label(phy, indio_dev, "bmem"); + if (ret) + return ret; + + dev_info(dev, "BMEM sniffer: %d channels (%s mode)\n", + num_channels, is_8t8r ? "8T8R" : "4T4R"); + + ret = devm_iio_kfifo_buffer_setup_ext(dev, indio_dev, &ad9088_bmem_buffer_ops, NULL); + if (ret) + return ret; + + ret = devm_iio_device_register(dev, indio_dev); + if (ret) + return ret; + + ad9088_bmem_debugfs_init(indio_dev); + + return 0; +} diff --git a/drivers/iio/trx-rf/ad9088/ad9088_cal.c b/drivers/iio/trx-rf/ad9088/ad9088_cal.c new file mode 100644 index 00000000000000..0edc31c80f1f59 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/ad9088_cal.c @@ -0,0 +1,713 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * AD9088 Calibration Data Save/Restore + * + * Copyright 2025 Analog Devices Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ad9088.h" +#include "../../adc/cf_axi_adc.h" + +/* + * Calibration File Format (Version 2) + * ==================================== + * + * The calibration data is organized as follows: + * + * +------------------------+ + * | Header (64 bytes) | <- Fixed size header with magic, version, metadata + * +------------------------+ + * | ADC Cal Data | <- All ADC channels, both sequential and random modes + * +------------------------+ + * | SERDES RX Cal Data | <- All SERDES RX 12-packs + * +------------------------+ + * | Clock Cond Cal Data | <- Clock conditioning cal for both sides + * +------------------------+ + * | CRC32 (4 bytes) | <- Checksum of entire file excluding this field + * +------------------------+ + * + * Note: Header structure and constants are defined in ad9088.h + */ + +/** + * ad9088_cal_save - Save all calibration data to buffer + * @phy: AD9088 device structure + * @buf: Pointer to receive allocated buffer + * @len: Pointer to receive buffer length + * + * Returns: 0 on success, negative error code on failure + */ +int ad9088_cal_save(struct ad9088_phy *phy, u8 **buf, size_t *len) +{ + struct ad9088_cal_header *hdr; + adi_apollo_device_t *device = &phy->ad9088; + u8 *ptr, *cal_buf; + u32 adc_len_per_mode = 0, adc_len_per_chan, serdes_rx_len, clk_cond_len; + u32 total_size, current_offset; + u32 crc; + int ret, i, mode; + u16 adc_cal_chans; + u8 num_adcs; + u16 serdes_jrx_enabled_mask = 0; + adi_apollo_serdes_bgcal_state_t serdes_state[ADI_APOLLO_NUM_JRX_SERDES_12PACKS]; + adi_apollo_mailbox_resp_update_cal_data_crc_t crc_resp; + + dev_dbg(&phy->spi->dev, "Saving calibration data...\n"); + + /* Determine device configuration */ + adc_cal_chans = device->dev_info.is_8t8r ? ADI_APOLLO_ADC_ALL : ADI_APOLLO_ADC_ALL_4T4R; + num_adcs = device->dev_info.is_8t8r ? 8 : 4; + + /* Query which SERDES JRX packs are enabled */ + ret = adi_apollo_serdes_jrx_bgcal_state_get(device, ADI_APOLLO_TXRX_SERDES_12PACK_ALL, + serdes_state, ADI_APOLLO_NUM_JRX_SERDES_12PACKS); + if (ret) { + dev_err(&phy->spi->dev, "Failed to get SERDES JRX bgcal state: %d\n", ret); + return -EFAULT; + } + + /* Build mask of enabled SERDES packs */ + for (i = 0; i < ADI_APOLLO_NUM_JRX_SERDES_12PACKS; i++) { + if (serdes_state[i].state_valid && + (serdes_state[i].bgcal_state & ADI_APOLLO_SERDES_BGCAL_STATE_ENABLED)) { + serdes_jrx_enabled_mask |= (ADI_APOLLO_TXRX_SERDES_12PACK_A << i); + dev_dbg(&phy->spi->dev, "SERDES JRX Pack %d is enabled (state: 0x%x)\n", + i, serdes_state[i].bgcal_state); + } + } + + if (serdes_jrx_enabled_mask == 0) + dev_dbg(&phy->spi->dev, "No SERDES JRX packs are enabled for bgcal\n"); + else + dev_dbg(&phy->spi->dev, "SERDES JRX enabled mask: 0x%04x\n", serdes_jrx_enabled_mask); + + /* Get calibration data sizes */ + ret = adi_apollo_cfg_adc_cal_data_len_get(device, ADI_APOLLO_ADC_CAL_SEQUENTIAL_MODE, &adc_len_per_chan); + if (ret) { + dev_err(&phy->spi->dev, "Failed to get ADC cal data length: %d\n", ret); + return -EFAULT; + } + + adc_len_per_mode = adc_len_per_chan * num_adcs; /* Total for one mode (seq or random) */ + + ret = adi_apollo_cfg_serdes_rx_cal_data_len_get(device, &serdes_rx_len); + if (ret) { + dev_err(&phy->spi->dev, "Failed to get SERDES RX cal data length: %d\n", ret); + return -EFAULT; + } + + ret = adi_apollo_cfg_clk_cond_cal_data_len_get(device, &clk_cond_len); + if (ret) { + dev_err(&phy->spi->dev, "Failed to get clock conditioning cal data length: %d\n", ret); + return -EFAULT; + } + + /* Calculate total size: + * - Header + * - ADC cal data (2 modes * num_adcs * size_per_adc) + * - SERDES RX cal data (num_serdes_rx * size_per_serdes) + * - Clock conditioning cal data (2 sides * size_per_side) + * - CRC32 + */ + total_size = sizeof(struct ad9088_cal_header) + + (adc_len_per_mode * 2) + /* 2 modes: sequential and random */ + (serdes_rx_len * ADI_APOLLO_NUM_JTX_SERDES_12PACKS) + + (clk_cond_len * ADI_APOLLO_NUM_SIDES) + + sizeof(u32); /* CRC32 */ + + /* Allocate buffer */ + cal_buf = kzalloc(total_size, GFP_KERNEL); + if (!cal_buf) + return -ENOMEM; + + ptr = cal_buf; + + /* Fill header */ + hdr = (struct ad9088_cal_header *)ptr; + hdr->magic = AD9088_CAL_MAGIC; + hdr->version = AD9088_CAL_VERSION; + hdr->chip_id = phy->chip_id.chip_type; + hdr->is_8t8r = device->dev_info.is_8t8r; + hdr->num_adcs = num_adcs; + hdr->num_serdes_rx = ADI_APOLLO_NUM_JTX_SERDES_12PACKS; + hdr->num_clk_cond = ADI_APOLLO_NUM_SIDES; + hdr->total_size = total_size; + + /* Set up section offsets and sizes */ + current_offset = sizeof(struct ad9088_cal_header); + + hdr->adc_cal_offset = current_offset; + hdr->adc_cal_size = adc_len_per_mode * 2; + current_offset += hdr->adc_cal_size; + + hdr->serdes_rx_cal_offset = current_offset; + hdr->serdes_rx_cal_size = serdes_rx_len * ADI_APOLLO_NUM_JTX_SERDES_12PACKS; + current_offset += hdr->serdes_rx_cal_size; + + hdr->clk_cond_cal_offset = current_offset; + hdr->clk_cond_cal_size = clk_cond_len * ADI_APOLLO_NUM_SIDES; + + ptr += sizeof(struct ad9088_cal_header); + + /* Read ADC calibration data (both sequential and random modes) */ + /* Freeze ADC background calibration before reading */ + dev_dbg(&phy->spi->dev, "Freezing ADC background calibration...\n"); + ret = adi_apollo_adc_bgcal_freeze(device, adc_cal_chans); + if (ret) { + dev_err(&phy->spi->dev, "Failed to freeze ADC bgcal: %d\n", ret); + kfree(cal_buf); + return -EFAULT; + } + + /* Freeze SERDES JRX background calibration (only for enabled packs) */ + if (serdes_jrx_enabled_mask) { + dev_dbg(&phy->spi->dev, "Freezing SERDES JRX background calibration (mask: 0x%04x)...\n", + serdes_jrx_enabled_mask); + ret = adi_apollo_serdes_jrx_bgcal_freeze(&phy->ad9088, serdes_jrx_enabled_mask); + if (ret) { + dev_err(&phy->spi->dev, "Failed to freeze SERDES JRX bgcal: %d\n", ret); + adi_apollo_adc_bgcal_unfreeze(device, adc_cal_chans); + kfree(cal_buf); + return -EFAULT; + } + } + + /* Wait for freeze to take effect */ + msleep(5); + + /* Update CRC in firmware before reading data */ + dev_dbg(&phy->spi->dev, "Updating calibration data CRC...\n"); + ret = adi_apollo_mailbox_update_cal_data_crc(device, &crc_resp); + if (ret) { + dev_err(&phy->spi->dev, "Failed to update cal data CRC: %d\n", ret); + /* Unfreeze bgcal before returning */ + adi_apollo_adc_bgcal_unfreeze(device, adc_cal_chans); + if (serdes_jrx_enabled_mask) + adi_apollo_serdes_jrx_bgcal_unfreeze(device, serdes_jrx_enabled_mask); + kfree(cal_buf); + return -EFAULT; + } + dev_dbg(&phy->spi->dev, "CRC update status: %u\n", crc_resp.status); + + /* Read ADC calibration data (both sequential and random modes) */ + dev_dbg(&phy->spi->dev, "Reading ADC calibration data...\n"); + for (mode = 0; mode < 2; mode++) { + for (i = 0; i < ADI_APOLLO_ADC_NUM; i++) { + if (adc_cal_chans & (ADI_APOLLO_ADC_A0 << i)) { + ret = adi_apollo_cfg_adc_cal_data_get(device, + ADI_APOLLO_ADC_A0 << i, mode, ptr, adc_len_per_chan); + if (ret) { + dev_err(&phy->spi->dev, + "Failed to get ADC%d mode%d cal data: %d\n", + i, mode, ret); + /* Unfreeze bgcal before returning */ + adi_apollo_adc_bgcal_unfreeze(device, adc_cal_chans); + if (serdes_jrx_enabled_mask) + adi_apollo_serdes_jrx_bgcal_unfreeze(device, serdes_jrx_enabled_mask); + kfree(cal_buf); + return -EFAULT; + } + ptr += adc_len_per_chan; + } + } + } + + /* Unfreeze ADC background calibration after reading */ + dev_dbg(&phy->spi->dev, "Unfreezing ADC background calibration...\n"); + ret = adi_apollo_adc_bgcal_unfreeze(device, adc_cal_chans); + if (ret) + dev_warn(&phy->spi->dev, "Failed to unfreeze ADC bgcal: %d\n", ret); + + /* Unfreeze SERDES JRX background calibration after reading */ + if (serdes_jrx_enabled_mask) { + dev_dbg(&phy->spi->dev, "Unfreezing SERDES JRX background calibration...\n"); + ret = adi_apollo_serdes_jrx_bgcal_unfreeze(device, serdes_jrx_enabled_mask); + if (ret) + dev_warn(&phy->spi->dev, "Failed to unfreeze SERDES JRX bgcal: %d\n", ret); + } + + /* Read SERDES RX calibration data */ + dev_dbg(&phy->spi->dev, "Reading SERDES RX calibration data...\n"); + for (i = 0; i < ADI_APOLLO_NUM_JTX_SERDES_12PACKS; i++) { + ret = adi_apollo_cfg_serdes_rx_cal_data_get(device, + ADI_APOLLO_TXRX_SERDES_12PACK_A << i, ptr, serdes_rx_len); + if (ret) { + dev_err(&phy->spi->dev, + "Failed to get SERDES RX%d cal data: %d\n", i, ret); + kfree(cal_buf); + return -EFAULT; + } + ptr += serdes_rx_len; + } + + /* Read clock conditioning calibration data */ + dev_dbg(&phy->spi->dev, "Reading clock conditioning calibration data...\n"); + for (i = 0; i < ADI_APOLLO_NUM_SIDES; i++) { + ret = adi_apollo_cfg_clk_cond_cal_data_get(device, + ADI_APOLLO_SIDE_A << i, ptr, clk_cond_len); + if (ret) { + dev_err(&phy->spi->dev, + "Failed to get clock conditioning Side %c cal data: %d\n", + 'A' + i, ret); + kfree(cal_buf); + return -EFAULT; + } + ptr += clk_cond_len; + } + + /* Calculate and append CRC32 of everything except the CRC itself */ + crc = crc32_le(~0, cal_buf, total_size - sizeof(u32)); + crc = ~crc; + memcpy(ptr, &crc, sizeof(u32)); + + dev_info(&phy->spi->dev, + "Calibration data saved: %u bytes (ADC: %u, SERDES RX: %u, Clk Cond: %u)\n", + total_size, hdr->adc_cal_size, hdr->serdes_rx_cal_size, + hdr->clk_cond_cal_size); + + *buf = cal_buf; + *len = total_size; + + return 0; +} + +/** + * ad9088_cal_restore - Restore calibration data from buffer + * @phy: AD9088 device structure + * @buf: Buffer containing calibration data + * @len: Buffer length + * + * Returns: 0 on success, negative error code on failure + */ +int ad9088_cal_restore(struct ad9088_phy *phy, const u8 *buf, size_t len) +{ + struct ad9088_cal_header *hdr; + adi_apollo_device_t *device = &phy->ad9088; + const u8 *ptr; + u32 crc, crc_calc; + u32 adc_len_per_chan, serdes_rx_len, clk_cond_len; + int ret, i, mode; + u16 adc_cal_chans; + u16 serdes_jrx_enabled_mask = 0; + adi_apollo_serdes_bgcal_state_t serdes_state[ADI_APOLLO_NUM_JRX_SERDES_12PACKS]; + + dev_dbg(&phy->spi->dev, "Restoring calibration data...\n"); + + /* Validate minimum size */ + if (len < sizeof(struct ad9088_cal_header) + sizeof(u32)) { + dev_err(&phy->spi->dev, "Calibration buffer too small\n"); + return -EINVAL; + } + + hdr = (struct ad9088_cal_header *)buf; + + /* Validate magic number */ + if (hdr->magic != AD9088_CAL_MAGIC) { + dev_err(&phy->spi->dev, + "Invalid calibration magic: 0x%08x (expected 0x%08x)\n", + hdr->magic, AD9088_CAL_MAGIC); + return -EINVAL; + } + + /* Validate version */ + if (hdr->version != AD9088_CAL_VERSION) { + dev_err(&phy->spi->dev, + "Unsupported calibration version: %u (expected %u)\n", + hdr->version, AD9088_CAL_VERSION); + return -EINVAL; + } + + /* Validate total size */ + if (hdr->total_size != len) { + dev_err(&phy->spi->dev, + "Calibration size mismatch: %u vs %zu\n", + hdr->total_size, len); + return -EINVAL; + } + + /* Validate chip ID */ + if (hdr->chip_id != phy->chip_id.chip_type) { + dev_err(&phy->spi->dev, + "Chip ID mismatch: 0x%04x vs 0x%04x\n", + hdr->chip_id, phy->chip_id.chip_type); + return -EINVAL; + } + + /* Validate device configuration */ + if (hdr->is_8t8r != device->dev_info.is_8t8r) { + dev_err(&phy->spi->dev, + "Device configuration mismatch: %s vs %s\n", + hdr->is_8t8r ? "8T8R" : "4T4R", + device->dev_info.is_8t8r ? "8T8R" : "4T4R"); + return -EINVAL; + } + + /* Verify CRC32 */ + memcpy(&crc, buf + len - sizeof(u32), sizeof(u32)); + crc_calc = crc32_le(~0, buf, len - sizeof(u32)); + crc_calc = ~crc_calc; + + if (crc != crc_calc) { + dev_err(&phy->spi->dev, + "CRC mismatch: 0x%08x vs 0x%08x\n", crc, crc_calc); + return -EINVAL; + } + + /* Determine device configuration */ + adc_cal_chans = device->dev_info.is_8t8r ? ADI_APOLLO_ADC_ALL : ADI_APOLLO_ADC_ALL_4T4R; + + /* Query which SERDES JRX packs are enabled */ + ret = adi_apollo_serdes_jrx_bgcal_state_get(device, ADI_APOLLO_TXRX_SERDES_12PACK_ALL, + serdes_state, ADI_APOLLO_NUM_JRX_SERDES_12PACKS); + if (ret) { + dev_err(&phy->spi->dev, "Failed to get SERDES JRX bgcal state: %d\n", ret); + return -EFAULT; + } + + /* Build mask of enabled SERDES packs */ + for (i = 0; i < ADI_APOLLO_NUM_JRX_SERDES_12PACKS; i++) { + if (serdes_state[i].state_valid && + (serdes_state[i].bgcal_state & ADI_APOLLO_SERDES_BGCAL_STATE_ENABLED)) { + serdes_jrx_enabled_mask |= (ADI_APOLLO_TXRX_SERDES_12PACK_A << i); + dev_dbg(&phy->spi->dev, "SERDES JRX Pack %d is enabled (state: 0x%x)\n", + i, serdes_state[i].bgcal_state); + } + } + + if (serdes_jrx_enabled_mask == 0) + dev_warn(&phy->spi->dev, "No SERDES JRX packs are enabled for bgcal\n"); + else + dev_dbg(&phy->spi->dev, "SERDES JRX enabled mask: 0x%04x\n", serdes_jrx_enabled_mask); + + /* Get expected sizes */ + ret = adi_apollo_cfg_adc_cal_data_len_get(device, ADI_APOLLO_ADC_CAL_SEQUENTIAL_MODE, &adc_len_per_chan); + if (ret) { + dev_err(&phy->spi->dev, "Failed to get ADC cal data length: %d\n", ret); + return -EFAULT; + } + + ret = adi_apollo_cfg_serdes_rx_cal_data_len_get(device, &serdes_rx_len); + if (ret) { + dev_err(&phy->spi->dev, "Failed to get SERDES RX cal data length: %d\n", ret); + return -EFAULT; + } + + ret = adi_apollo_cfg_clk_cond_cal_data_len_get(device, &clk_cond_len); + if (ret) { + dev_err(&phy->spi->dev, "Failed to get clock conditioning cal data length: %d\n", ret); + return -EFAULT; + } + + /* Restore ADC calibration data */ + dev_dbg(&phy->spi->dev, "Restoring ADC calibration data...\n"); + ptr = buf + hdr->adc_cal_offset; + for (mode = 0; mode < 2; mode++) { + for (i = 0; i < ADI_APOLLO_ADC_NUM; i++) { + if (adc_cal_chans & (ADI_APOLLO_ADC_A0 << i)) { + ret = adi_apollo_cfg_adc_cal_data_set(device, + ADI_APOLLO_ADC_A0 << i, mode, (u8 *)ptr, adc_len_per_chan); + if (ret) { + dev_err(&phy->spi->dev, + "Failed to set ADC%d mode%d cal data: %d\n", + i, mode, ret); + return -EFAULT; + } + ptr += adc_len_per_chan; + } + } + } + + /* Restore SERDES RX calibration data */ + dev_dbg(&phy->spi->dev, "Restoring SERDES RX calibration data...\n"); + ptr = buf + hdr->serdes_rx_cal_offset; + for (i = 0; i < ADI_APOLLO_NUM_JTX_SERDES_12PACKS; i++) { + ret = adi_apollo_cfg_serdes_rx_cal_data_set(device, + ADI_APOLLO_TXRX_SERDES_12PACK_A << i, (u8 *)ptr, serdes_rx_len); + if (ret) { + dev_err(&phy->spi->dev, + "Failed to set SERDES RX%d cal data: %d\n", i, ret); + return -EFAULT; + } + ptr += serdes_rx_len; + } + + /* Restore clock conditioning calibration data */ + dev_dbg(&phy->spi->dev, "Restoring clock conditioning calibration data...\n"); + ptr = buf + hdr->clk_cond_cal_offset; + for (i = 0; i < ADI_APOLLO_NUM_SIDES; i++) { + ret = adi_apollo_cfg_clk_cond_cal_data_set(device, + ADI_APOLLO_SIDE_A << i, (u8 *)ptr, clk_cond_len); + if (ret) { + dev_err(&phy->spi->dev, + "Failed to set clock conditioning Side %c cal data: %d\n", + 'A' + i, ret); + return -EFAULT; + } + ptr += clk_cond_len; + } + + dev_dbg(&phy->spi->dev, "Calibration data restored successfully\n"); + + return 0; +} + +/** + * ad9088_cal_load_from_firmware - Load and restore calibration data from firmware file + * @phy: AD9088 PHY device structure + * + * This function reads the calibration firmware filename from the device tree + * property "adi,device-calibration-data-name" and loads the calibration data + * from the firmware directory. If the property is not present, this function + * returns success without doing anything (optional feature). + * + * Returns: 0 on success, negative error code on failure + */ +int ad9088_cal_load_from_firmware(struct ad9088_phy *phy) +{ + struct device *dev = &phy->spi->dev; + struct device_node *node = dev->of_node; + const struct firmware *fw; + const char *name; + int ret; + + phy->cal_data_loaded_from_fw = false; + + /* Check if calibration data firmware name is specified in device tree */ + ret = of_property_read_string(node, "adi,device-calibration-data-name", &name); + if (ret) { + /* Property not present - this is optional, so return success */ + dev_dbg(dev, "No calibration firmware specified in device tree\n"); + return 0; + } + + dev_dbg(dev, "Loading calibration data from firmware: %s\n", name); + + /* Request the firmware file */ + ret = request_firmware(&fw, name, dev); + if (ret) { + dev_err(dev, "Failed to load calibration firmware '%s': %d\n", name, ret); + return ret; + } + + /* Validate firmware size */ + if (fw->size < sizeof(struct ad9088_cal_header)) { + dev_err(dev, "Calibration firmware '%s' too small (%zu bytes)\n", + name, fw->size); + ret = -EINVAL; + goto out_release_fw; + } + + /* Restore calibration data to hardware */ + ret = ad9088_cal_restore(phy, fw->data, fw->size); + if (ret) { + dev_err(dev, "Failed to restore calibration data from firmware: %d\n", ret); + goto out_release_fw; + } + + dev_dbg(dev, "Calibration data loaded and restored successfully from %s\n", name); + + phy->cal_data_loaded_from_fw = true; + +out_release_fw: + release_firmware(fw); + return ret; +} + +/** + * ad9088_cal_data_read - Sysfs bin_attribute read for calibration data + * @filp: File pointer + * @kobj: Kernel object + * @bin_attr: Binary attribute + * @buf: Buffer to read into + * @off: Offset in file + * @count: Number of bytes to read + * + * Returns: Number of bytes read, or negative error code + */ +ssize_t ad9088_cal_data_read(struct file *filp, struct kobject *kobj, + struct bin_attribute *bin_attr, + char *buf, loff_t off, size_t count) +{ + struct iio_dev *indio_dev = dev_to_iio_dev(kobj_to_dev(kobj)); + struct axiadc_converter *conv = iio_device_get_drvdata(indio_dev); + struct ad9088_phy *phy = conv->phy; + u8 *cal_buf = NULL; + size_t cal_len = 0; + ssize_t ret_count; + int ret; + + /* Generate calibration data on first read or if not cached */ + if (off == 0) { + guard(mutex)(&phy->lock); + + /* Free old buffer if exists */ + kfree(phy->nvm_adc_cal); + phy->nvm_adc_cal = NULL; + + /* Save current calibration data */ + ret = ad9088_cal_save(phy, &cal_buf, &cal_len); + if (ret) { + dev_err(&phy->spi->dev, "Failed to save calibration data: %d\n", ret); + return ret; + } + + /* Cache the buffer for subsequent reads */ + phy->nvm_adc_cal = cal_buf; + phy->adc_cal_len = cal_len; + } + + /* Validate offset */ + if (off >= phy->adc_cal_len) + return 0; + + /* Calculate bytes to read */ + ret_count = min_t(size_t, count, phy->adc_cal_len - off); + + /* Copy data to user buffer */ + memcpy(buf, phy->nvm_adc_cal + off, ret_count); + + return ret_count; +} + +/** + * ad9088_cal_data_write - Sysfs bin_attribute write for calibration data + * @filp: File pointer + * @kobj: Kernel object + * @bin_attr: Binary attribute + * @buf: Buffer to write from + * @off: Offset in file + * @count: Number of bytes to write + * + * Handles multi-write operations by accumulating data in a buffer until + * the entire calibration file is received, then restores it. + * + * Returns: Number of bytes written, or negative error code + */ +ssize_t ad9088_cal_data_write(struct file *filp, struct kobject *kobj, + struct bin_attribute *bin_attr, + char *buf, loff_t off, size_t count) +{ + struct iio_dev *indio_dev = dev_to_iio_dev(kobj_to_dev(kobj)); + struct axiadc_converter *conv = iio_device_get_drvdata(indio_dev); + struct ad9088_phy *phy = conv->phy; + struct ad9088_cal_header *hdr; + int ret = 0; + + guard(mutex)(&phy->lock); + + /* First write - read header and allocate buffer */ + if (off == 0) { + /* Free any existing buffer */ + if (phy->cal_restore_buf) { + vfree(phy->cal_restore_buf); + phy->cal_restore_buf = NULL; + phy->cal_restore_size = 0; + phy->cal_restore_received = 0; + } + + /* Need at least header to determine size */ + if (count < sizeof(struct ad9088_cal_header)) { + dev_err(&phy->spi->dev, + "First write too small: %zu bytes (need at least %zu)\n", + count, sizeof(struct ad9088_cal_header)); + return -EINVAL; + } + + /* Read header to get total size */ + hdr = (struct ad9088_cal_header *)buf; + + /* Validate magic */ + if (hdr->magic != AD9088_CAL_MAGIC) { + dev_err(&phy->spi->dev, + "Invalid calibration magic: 0x%08x\n", hdr->magic); + return -EINVAL; + } + + /* Validate version */ + if (hdr->version != AD9088_CAL_VERSION) { + dev_err(&phy->spi->dev, + "Unsupported calibration version: %u\n", hdr->version); + return -EINVAL; + } + + /* Allocate buffer for entire file */ + phy->cal_restore_size = hdr->total_size; + phy->cal_restore_buf = vmalloc(phy->cal_restore_size); + if (!phy->cal_restore_buf) { + dev_err(&phy->spi->dev, + "Failed to allocate %zu bytes for calibration restore\n", + phy->cal_restore_size); + phy->cal_restore_size = 0; + return -ENOMEM; + } + + phy->cal_restore_received = 0; + dev_dbg(&phy->spi->dev, + "Starting calibration restore: %zu bytes expected\n", + phy->cal_restore_size); + } + + /* Verify we have an active restore in progress */ + if (!phy->cal_restore_buf) { + dev_err(&phy->spi->dev, + "No calibration restore in progress (write at offset %lld)\n", off); + return -EINVAL; + } + + /* Verify offset is within bounds */ + if (off + count > phy->cal_restore_size) { + dev_err(&phy->spi->dev, + "Write exceeds calibration size: offset=%lld count=%zu size=%zu\n", + off, count, phy->cal_restore_size); + vfree(phy->cal_restore_buf); + phy->cal_restore_buf = NULL; + phy->cal_restore_size = 0; + phy->cal_restore_received = 0; + return -EINVAL; + } + + /* Copy data into buffer */ + memcpy(phy->cal_restore_buf + off, buf, count); + phy->cal_restore_received = off + count; + + dev_dbg(&phy->spi->dev, + "Calibration write: offset=%lld count=%zu received=%zu/%zu\n", + off, count, phy->cal_restore_received, phy->cal_restore_size); + + /* If we've received all data, restore it */ + if (phy->cal_restore_received >= phy->cal_restore_size) { + dev_dbg(&phy->spi->dev, + "All calibration data received, restoring...\n"); + + ret = ad9088_cal_restore(phy, phy->cal_restore_buf, + phy->cal_restore_size); + if (ret) { + dev_err(&phy->spi->dev, + "Failed to restore calibration data: %d\n", ret); + } else { + dev_info(&phy->spi->dev, + "Calibration data restored successfully\n"); + } + + /* Free buffer */ + vfree(phy->cal_restore_buf); + phy->cal_restore_buf = NULL; + phy->cal_restore_size = 0; + phy->cal_restore_received = 0; + + if (ret) + return ret; + } + + return count; +} diff --git a/drivers/iio/trx-rf/ad9088/ad9088_debugfs.c b/drivers/iio/trx-rf/ad9088/ad9088_debugfs.c new file mode 100644 index 00000000000000..0cffc49743c728 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/ad9088_debugfs.c @@ -0,0 +1,853 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * AD9088 Debugfs Interface + * + * Copyright 2026 Analog Devices Inc. + */ + +#include "ad9088.h" + +enum ad9088_debugfs_cmd { + DBGFS_NONE, + DBGFS_BIST_PRBS_JRX, + DBGFS_BIST_PRBS_JRX_ERR, + DBGFS_BIST_PRBS_JTX, + DBGFS_BIST_JRX_2D_EYE, + DBGFS_DEV_API_INFO, + DBGFS_DEV_UUID_INFO, + DBGFS_DEV_DIE_INFO, + DBGFS_DEV_CHIP_INFO, + DBGFS_DEV_TEMP_INFO, + DBGFS_HSCI_ENABLE, + DBGFS_CLK_PWR_STAT, + DBGFS_GENERIC, + DBGFS_JRX_PHASE_ADJUST_CALC, + DBGFS_JTX_LANE_DRIVE_SWING, + DBGFS_JTX_LANE_PRE_EMPHASIS, + DBGFS_JTX_LANE_POST_EMPHASIS, + /* MCS calibration commands */ + DBGFS_MCS_INIT, + DBGFS_MCS_DT0_MEASUREMENT, + DBGFS_MCS_DT1_MEASUREMENT, + DBGFS_MCS_DT_RESTORE, + DBGFS_MCS_CAL_RUN, + DBGFS_MCS_TRACK_CAL_SETUP, + DBGFS_MCS_FG_TRACK_CAL_RUN, + DBGFS_MCS_BG_TRACK_CAL_RUN, + DBGFS_MCS_TRACK_STATUS, + DBGFS_MCS_INIT_CAL_STATUS, + DBGFS_MCS_TRACK_CAL_VALIDATE, + DBGFS_MCS_TRACK_DECIMATION, +}; + +static const u8 lanes_all[] = { + 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, + 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 +}; + +static u16 ad9088_jrx_serdes_en_mask(struct ad9088_phy *phy) +{ + u16 serdes = ADI_APOLLO_TXRX_SERDES_12PACK_NONE; + + if (phy->profile.jrx[0].common_link_cfg.lane_enables) + serdes |= ADI_APOLLO_TXRX_SERDES_12PACK_A; + if (phy->profile.jrx[1].common_link_cfg.lane_enables) + serdes |= ADI_APOLLO_TXRX_SERDES_12PACK_B; + + return serdes; +} + +static int ad9088_dbg(struct ad9088_phy *phy, int val, int val2, int val3, int val4) +{ +#ifdef DEBUG + adi_apollo_device_t *device = &phy->ad9088; + int ret; + + dev_info(&phy->spi->dev, " MCS - %d 0x%X\n", val, val2); + switch (val) { + case 1: + adi_apollo_jrx_phase_adjust_set(device, val3 ? val3 : + ADI_APOLLO_LINK_A0 | ADI_APOLLO_LINK_B0, val2); + break; + case 2: + adi_apollo_jtx_phase_adjust_set(device, val3 ? val3 : + ADI_APOLLO_LINK_A0 | ADI_APOLLO_LINK_B0, val2); + break; + case 3: + adi_apollo_jtx_link_enable_set(device, + ADI_APOLLO_LINK_A0 | ADI_APOLLO_LINK_B0, val2); + adi_apollo_jrx_link_enable_set(device, + ADI_APOLLO_LINK_A0 | ADI_APOLLO_LINK_B0, val2); + break; + case 4: + /* Datapath reset */ + ret = adi_apollo_serdes_jrx_cal(&phy->ad9088); + ad9088_check_apollo_error(&phy->spi->dev, ret, "adi_apollo_serdes_jrx_cal"); + break; + case 5: + adi_apollo_txmisc_dp_reset(device, ADI_APOLLO_SIDE_ALL, 1); + adi_apollo_txmisc_dp_reset(device, ADI_APOLLO_SIDE_ALL, 0); + break; + case 6: + adi_apollo_clk_mcs_dyn_sync_sequence_run(device); + break; + case 7: + adi_apollo_clk_mcs_oneshot_sync(device); + break; + case 8: + adi_apollo_clk_mcs_dyn_sync_rxtxlinks_sequence_run(device); + break; + case 9: + ad9088_print_sysref_phase(phy); + break; + case 10: + adi_apollo_adc_bgcal_unfreeze(device, device->dev_info.is_8t8r ? + ADI_APOLLO_ADC_ALL : ADI_APOLLO_ADC_ALL_4T4R); + break; + case 11: + adi_apollo_adc_bgcal_freeze(device, device->dev_info.is_8t8r ? + ADI_APOLLO_ADC_ALL : ADI_APOLLO_ADC_ALL_4T4R); + break; + default: + return -EINVAL; + } + + return 0; +#else + return -ENOTSUPP; +#endif +} + +static ssize_t ad9088_debugfs_read(struct file *file, char __user *userbuf, + size_t count, loff_t *ppos) +{ + struct ad9088_debugfs_entry *entry = file->private_data; + struct iio_dev *indio_dev = entry->indio_dev; + struct axiadc_converter *conv = iio_device_get_drvdata(indio_dev); + struct ad9088_phy *phy = conv->phy; + adi_apollo_device_tmu_data_t tmu_data; + adi_apollo_serdes_prbs_checker_status_t prbs_stat[24]; + adi_apollo_hal_protocol_e protocol; + adi_apollo_clk_input_power_status_e pwr_stat_a, pwr_stat_b; + adi_apollo_serdes_jrx_horiz_eye_resp_t horz_resp; + adi_apollo_serdes_jrx_vert_eye_resp_t vert_resp; + u64 val = 0; + ssize_t len = 0; + int ret, i, lane, prbs, duration; + u8 uuid[ADI_APOLLO_UUID_NUM_BYTES]; + u16 api_rev[3]; + u8 die_id; + + if (*ppos) + return 0; + + guard(mutex)(&phy->lock); + + if (entry->out_value) { + switch (entry->size) { + case 1: + val = *(u8 *)entry->out_value; + break; + case 2: + val = *(u16 *)entry->out_value; + break; + case 4: + val = *(u32 *)entry->out_value; + break; + case 5: + val = *(bool *)entry->out_value; + break; + case 8: + val = *(u64 *)entry->out_value; + break; + default: + ret = -EINVAL; + } + + } else if (entry->cmd) { + switch (entry->cmd) { + case DBGFS_BIST_PRBS_JRX_ERR: + ret = adi_apollo_serdes_jrx_prbs_checker_status(&phy->ad9088, + phy->jrx_lanes, prbs_stat, + phy->jrx_lanes_used); + if (ret) { + dev_err(&phy->spi->dev, "adi_apollo_serdes_jrx_prbs_checker_status() failed (%d)", + ret); + break; + } + + for (i = 0; i < phy->jrx_lanes_used; i++) + len += snprintf(phy->dbuf + len, sizeof(phy->dbuf) - len, + "%c: lane-%u %u/%u\n", + phy->jrx_lanes[i] < 12 ? 'A' : 'B', + phy->jrx_lanes[i] > 11 ? + phy->jrx_lanes[i] - 12 : phy->jrx_lanes[i], + prbs_stat[phy->jrx_lanes[i]].err_count, + prbs_stat[phy->jrx_lanes[i]].err_sticky); + break; + case DBGFS_BIST_JRX_2D_EYE: + if (!entry->val) + return -EINVAL; + + lane = (entry->val & 0xFF) - 1; + prbs = (entry->val >> 8) & 0xFF; + duration = (entry->val >> 16) & 0xFFFF; + + entry->val = 0; + + if (phy->profile.jrx[0].common_link_cfg.lane_rate_kHz > 16000000) { + ret = adi_apollo_serdes_jrx_bgcal_freeze(&phy->ad9088, + ad9088_jrx_serdes_en_mask(phy)); + ret = ad9088_check_apollo_error(&phy->spi->dev, ret, + "adi_apollo_serdes_jrx_bgcal_freeze"); + if (ret) + return ret; + } + + ret = adi_apollo_serdes_jrx_horiz_eye_sweep(&phy->ad9088, lane, prbs); + ret = ad9088_check_apollo_error(&phy->spi->dev, ret, + "adi_apollo_serdes_jrx_horiz_eye_sweep"); + if (ret) + return ret; + + msleep(duration); /* FIXME: Don't think this does anything */ + + ret = adi_apollo_serdes_jrx_horiz_eye_sweep_resp_get(&phy->ad9088, lane, + &horz_resp); + ret = ad9088_check_apollo_error(&phy->spi->dev, ret, + "adi_apollo_serdes_jrx_horiz_eye_sweep_resp_get"); + if (ret) + return ret; + + ret = adi_apollo_serdes_jrx_vert_eye_sweep(&phy->ad9088, lane); + ret = ad9088_check_apollo_error(&phy->spi->dev, ret, + "adi_apollo_serdes_jrx_vert_eye_sweep"); + if (ret) + return ret; + + msleep(duration); /* FIXME: Don't think this does anything */ + + ret = adi_apollo_serdes_jrx_vert_eye_sweep_resp_get(&phy->ad9088, lane, + &vert_resp); + ret = ad9088_check_apollo_error(&phy->spi->dev, ret, + "adi_apollo_serdes_jrx_vert_eye_sweep_resp_get"); + if (ret) + return ret; + + if (phy->profile.jrx[0].common_link_cfg.lane_rate_kHz > 16000000) { + ret = adi_apollo_serdes_jrx_bgcal_unfreeze(&phy->ad9088, + ad9088_jrx_serdes_en_mask(phy)); + ret = ad9088_check_apollo_error(&phy->spi->dev, ret, + "adi_apollo_serdes_jrx_bgcal_unfreeze"); + if (ret) + return ret; + } + + len = snprintf(phy->dbuf, sizeof(phy->dbuf), + "# lane %u spo_steps %u rate %u spo_left %u spo_right %u version %u\n", + lane, ADI_APOLLO_SERDES_JRX_VERT_EYE_TEST_RESP_BUF_SIZE / 2, + phy->profile.jrx[lane >= + ADI_APOLLO_JESD_MAX_LANES_PER_SIDE].common_link_cfg.lane_rate_kHz, + horz_resp.spo_left, horz_resp.spo_right, horz_resp.ver); + + for (i = 0; i < ADI_APOLLO_SERDES_JRX_VERT_EYE_TEST_RESP_BUF_SIZE; i += 2) + if (!(vert_resp.eye_heights_at_spo[i] == 127 && + vert_resp.eye_heights_at_spo[i + 1] == -127)) + len += snprintf(phy->dbuf + len, + sizeof(phy->dbuf) - len, + "%d,%d,%d\n", (i / 2) - 16, + vert_resp.eye_heights_at_spo[i] * 4, + vert_resp.eye_heights_at_spo[i + 1] * 4); + + break; + case DBGFS_DEV_TEMP_INFO: + if (!phy->is_initialized) + return -EBUSY; + ret = adi_apollo_device_tmu_get(&phy->ad9088, &tmu_data); + if (ret) + break; + + len = snprintf(phy->dbuf, sizeof(phy->dbuf), + "TMU (deg C): serdes_pll=%d mpu_a=%d mpu_b=%d adc_a=%d clk_a=%d adc_b=%d clk_b=%d clk_c=%d (avg: %d, avg mask: 0x%04x)\n", + tmu_data.temp_degrees_celsius[ADI_APOLLO_DEVICE_TMU_SERDES_PLL], + tmu_data.temp_degrees_celsius[ADI_APOLLO_DEVICE_TMU_MPU_A], + tmu_data.temp_degrees_celsius[ADI_APOLLO_DEVICE_TMU_MPU_B], + tmu_data.temp_degrees_celsius[ADI_APOLLO_DEVICE_TMU_ADC_A], + tmu_data.temp_degrees_celsius[ADI_APOLLO_DEVICE_TMU_CLK_A], + tmu_data.temp_degrees_celsius[ADI_APOLLO_DEVICE_TMU_ADC_B], + tmu_data.temp_degrees_celsius[ADI_APOLLO_DEVICE_TMU_CLK_B], + tmu_data.temp_degrees_celsius[ADI_APOLLO_DEVICE_TMU_CLK_C], + tmu_data.temp_degrees_celsius_avg, + tmu_data.avg_mask); + break; + case DBGFS_DEV_API_INFO: + adi_apollo_device_api_revision_get(&phy->ad9088, + &api_rev[0], &api_rev[1], &api_rev[2]); + + len = snprintf(phy->dbuf, sizeof(phy->dbuf), "%u.%u.%u\n", + api_rev[0], api_rev[1], api_rev[2]); + break; + case DBGFS_DEV_UUID_INFO: + ret = adi_apollo_device_uuid_get(&phy->ad9088, uuid, + ADI_APOLLO_UUID_NUM_BYTES); + if (ret) + break; + + len = 0; + for (i = 0; i < ADI_APOLLO_UUID_NUM_BYTES; i++) + len += snprintf(phy->dbuf + len, sizeof(phy->dbuf) - len, "%02x", + uuid[i]); + + len += snprintf(phy->dbuf + len, sizeof(phy->dbuf) - len, "\n"); + break; + case DBGFS_DEV_DIE_INFO: + ret = adi_apollo_device_die_id_get(&phy->ad9088, &die_id); + if (ret < 0) { + dev_err(&phy->spi->dev, "die_id failed (%d)\n", ret); + break; + } + + len = snprintf(phy->dbuf, sizeof(phy->dbuf), "DieID %u\n", + die_id); + break; + case DBGFS_DEV_CHIP_INFO: + ret = adi_apollo_device_chip_id_get(&phy->ad9088, &phy->chip_id); + if (ret < 0) { + dev_err(&phy->spi->dev, "chip_id failed (%d)\n", ret); + break; + } + + len = snprintf(phy->dbuf, sizeof(phy->dbuf), "AD%X Rev. %u Grade %u\n", + phy->chip_id.prod_id, phy->chip_id.dev_revision, + phy->chip_id.prod_grade); + break; + case DBGFS_CLK_PWR_STAT: + ret = adi_apollo_clk_mcs_input_power_status_get(&phy->ad9088, &pwr_stat_a, + &pwr_stat_b); + if (ret) + break; + len = snprintf(phy->dbuf, sizeof(phy->dbuf), "Clock input power detection A: %s\n", + !pwr_stat_a ? "GOOD" : (pwr_stat_a == ADI_APOLLO_CLK_PWR_UNDERDRIVEN ? "UNDERDRIVEN" : + (pwr_stat_a == ADI_APOLLO_CLK_PWR_OVERDRIVEN ? "OVERDRIVEN" : "UNUSED"))); + len += snprintf(phy->dbuf + len, sizeof(phy->dbuf) - len, "Clock input power detection B: %s\n", + !pwr_stat_b ? "GOOD" : (pwr_stat_b == ADI_APOLLO_CLK_PWR_UNDERDRIVEN ? "UNDERDRIVEN" : + (pwr_stat_b == ADI_APOLLO_CLK_PWR_OVERDRIVEN ? "OVERDRIVEN" : "UNUSED"))); + break; + case DBGFS_HSCI_ENABLE: + if (phy->hsci) { + adi_apollo_hal_active_protocol_get(&phy->ad9088, &protocol); + val = (protocol == ADI_APOLLO_HAL_PROTOCOL_HSCI); + } else { + val = 0; + } + break; + case DBGFS_MCS_DT0_MEASUREMENT: + ret = ad9088_delta_t_measurement_get(phy, 0, &entry->delta_t); + if (!ret) + len = snprintf(phy->dbuf, sizeof(phy->dbuf), "%lld\n", + entry->delta_t); + break; + case DBGFS_MCS_DT1_MEASUREMENT: + ret = ad9088_delta_t_measurement_get(phy, 1, &entry->delta_t); + if (!ret) + len = snprintf(phy->dbuf, sizeof(phy->dbuf), "%lld\n", + entry->delta_t); + break; + case DBGFS_MCS_TRACK_DECIMATION: + val = phy->mcs_track_decimation; + break; + case DBGFS_MCS_BG_TRACK_CAL_RUN: + val = phy->mcs_cal_bg_tracking_run; + break; + case DBGFS_MCS_CAL_RUN: { + adi_apollo_mcs_cal_init_status_t init_cal_status = {{0}}; + + ret = adi_apollo_mcs_cal_init_status_get(&phy->ad9088, &init_cal_status); + ret = ad9088_check_apollo_error(&phy->spi->dev, ret, + "adi_apollo_mcs_cal_init_status_get"); + if (ret) + break; + ret = ad9088_mcs_init_cal_validate(phy, &init_cal_status); + len = snprintf(phy->dbuf, sizeof(phy->dbuf), "%s\n", + ret ? "Failed" : "Passed"); + ret = 0; /* Don't propagate validation failure as read error */ + break; + } + case DBGFS_MCS_INIT_CAL_STATUS: { + adi_apollo_mcs_cal_init_status_t init_cal_status = {{0}}; + + ret = adi_apollo_mcs_cal_init_status_get(&phy->ad9088, &init_cal_status); + ret = ad9088_check_apollo_error(&phy->spi->dev, ret, + "adi_apollo_mcs_cal_init_status_get"); + if (ret) + break; + len = ad9088_mcs_init_cal_status_print(phy, phy->dbuf, &init_cal_status); + break; + } + case DBGFS_MCS_TRACK_STATUS: { + adi_apollo_mcs_cal_status_t tracking_cal_status = {{0}}; + + if (!phy->mcs_cal_bg_tracking_run) { + len = snprintf(phy->dbuf, sizeof(phy->dbuf), + "BG tracking not running\n"); + break; + } + + if (!phy->mcs_cal_bg_tracking_freeze) { + ret = adi_apollo_mcs_cal_bg_tracking_freeze(&phy->ad9088); + ret = ad9088_check_apollo_error(&phy->spi->dev, ret, + "adi_apollo_mcs_cal_bg_tracking_freeze"); + if (ret) + break; + } + + ret = adi_apollo_mcs_cal_tracking_status_get(&phy->ad9088, + &tracking_cal_status); + ret = ad9088_check_apollo_error(&phy->spi->dev, ret, + "adi_apollo_mcs_cal_tracking_status_get"); + if (ret) + break; + + len = ad9088_mcs_track_cal_status_print(phy, phy->dbuf, + &tracking_cal_status, 1); + + if (!phy->mcs_cal_bg_tracking_freeze) { + ret = adi_apollo_mcs_cal_bg_tracking_unfreeze(&phy->ad9088); + ret = ad9088_check_apollo_error(&phy->spi->dev, ret, + "adi_apollo_mcs_cal_bg_tracking_unfreeze"); + } + break; + } + case DBGFS_MCS_TRACK_CAL_VALIDATE: + ret = ad9088_mcs_tracking_cal_validate(phy, phy->dbuf, sizeof(phy->dbuf)); + if (ret > 0) + len = ret; + break; + case DBGFS_MCS_INIT: + case DBGFS_MCS_DT_RESTORE: + case DBGFS_MCS_TRACK_CAL_SETUP: + case DBGFS_MCS_FG_TRACK_CAL_RUN: + /* Write-only attributes, return 0 on read */ + val = 0; + break; + default: + val = entry->val; + } + } else { + return -EFAULT; + } + if (!len) + len = snprintf(phy->dbuf, sizeof(phy->dbuf), "%llu\n", val); + + return simple_read_from_buffer(userbuf, count, ppos, phy->dbuf, len); +} + +static int ad9088_val_to_jtx_prbs(int val) +{ + switch (val) { + case 0: + return 0; + case 7: + return ADI_APOLLO_SERDES_JTX_PRBS7; + case 9: + return ADI_APOLLO_SERDES_JTX_PRBS9; + case 15: + return ADI_APOLLO_SERDES_JTX_PRBS15; + case 31: + return ADI_APOLLO_SERDES_JTX_PRBS31; + default: + return -EINVAL; + } + return -EINVAL; +} + +static int ad9088_val_to_jrx_prbs(int val) +{ + switch (val) { + case 0: + return 0; + case 7: + return ADI_APOLLO_SERDES_JRX_PRBS7; + case 9: + return ADI_APOLLO_SERDES_JRX_PRBS9; + case 15: + return ADI_APOLLO_SERDES_JRX_PRBS15; + case 31: + return ADI_APOLLO_SERDES_JRX_PRBS31; + default: + return -EINVAL; + } + return -EINVAL; +} + +static ssize_t ad9088_debugfs_write(struct file *file, + const char __user *userbuf, size_t count, loff_t *ppos) +{ + struct ad9088_debugfs_entry *entry = file->private_data; + struct iio_dev *indio_dev = entry->indio_dev; + struct axiadc_converter *conv = iio_device_get_drvdata(indio_dev); + struct ad9088_phy *phy = conv->phy; + adi_apollo_serdes_prbs_generator_enable_t prbs_gen; + adi_apollo_serdes_prbs_checker_enable_t prbs_chk; + int val2, val3, val4, ret, side, lane; + s64 val; + u16 phase; + char buf[80]; + + ret = simple_write_to_buffer(buf, sizeof(buf) - 1, ppos, userbuf, count); + if (ret < 0) + return ret; + + buf[ret] = '\0'; + + ret = sscanf(buf, "%lli %i %i %i", &val, &val2, &val3, &val4); + if (ret < 1) + return -EINVAL; + + guard(mutex)(&phy->lock); + + switch (entry->cmd) { + case DBGFS_BIST_PRBS_JRX: + if (ret < 1) + return -EINVAL; + + prbs_chk.enable = !!val; + prbs_chk.auto_mode = 0; + prbs_chk.auto_mode_thres = 4; /* 2^n */ + prbs_chk.prbs_mode = ad9088_val_to_jrx_prbs(val); + + ret = adi_apollo_jrx_link_enable_set(&phy->ad9088, + ADI_APOLLO_LINK_A1 | ADI_APOLLO_LINK_B1, + ADI_APOLLO_DISABLE); + if (ret) { + dev_err(&phy->spi->dev, "Error enabling JRx links %d\n", ret); + return ret; + } + + adi_apollo_serdes_jrx_prbs_checker_enable(&phy->ad9088, phy->jrx_lanes, + phy->jrx_lanes_used, &prbs_chk); + + /* Enable Apollo JRx links */ + ret = adi_apollo_jrx_link_enable_set(&phy->ad9088, + ADI_APOLLO_LINK_A0 | ADI_APOLLO_LINK_B0, + ADI_APOLLO_ENABLE); + if (ret) { + dev_err(&phy->spi->dev, "Error enabling JRx links %d\n", ret); + return ret; + } + + if (prbs_chk.enable) + adi_apollo_serdes_jrx_prbs_clear_error(&phy->ad9088, phy->jrx_lanes, + phy->jrx_lanes_used); + + entry->val = val; + + return count; + case DBGFS_BIST_PRBS_JTX: + if (ret < 1) + return -EINVAL; + + prbs_gen.enable = !!val; + prbs_gen.mode = ad9088_val_to_jtx_prbs(val); + + adi_apollo_serdes_prbs_generator_enable(&phy->ad9088, (u8 *)lanes_all, + ARRAY_SIZE(lanes_all), &prbs_gen); + entry->val = val; + + return count; + case DBGFS_HSCI_ENABLE: + if (ret < 1) + return -EINVAL; + + if (phy->hsci) { + if (val == 1) + val2 = ADI_APOLLO_HAL_PROTOCOL_HSCI; + else + val2 = ADI_APOLLO_HAL_PROTOCOL_SPI0; + ret = adi_apollo_hal_active_protocol_set(&phy->ad9088, val2); + } else { + return -ENODEV; + } + break; + case DBGFS_GENERIC: + if (ret < 1) + return -EINVAL; + + if (__is_defined(DEBUG)) + ret = ad9088_dbg(phy, val, val2, val3, val4); + break; + case DBGFS_BIST_JRX_2D_EYE: + if (ret < 1) + return -EINVAL; + + if (ret < 2) + val2 = 7; /* PRBS7 */ + + if (ret < 3) + val3 = 10; /* 10 ms */ + + if (val > 23) + return -EINVAL; + + lane = val; + + if (lane >= ADI_APOLLO_JESD_MAX_LANES_PER_SIDE) { + side = 1; + lane -= ADI_APOLLO_JESD_MAX_LANES_PER_SIDE; + } else { + side = 0; + } + + if (!(phy->profile.jrx[side].common_link_cfg.lane_enables & (1 << lane))) + return -EINVAL; + + val = val + 1; + + ret = ad9088_val_to_jrx_prbs(val2); + if (ret < 0) + return ret; + + val2 = ret; + /* Time PRBS Lane */ + entry->val = val3 << 16 | (val2 & 0xFF) << 8 | (val & 0xFF); + + return count; + case DBGFS_JRX_PHASE_ADJUST_CALC: + ret = adi_apollo_jrx_phase_adjust_calc(&phy->ad9088, + ADI_APOLLO_LINK_A0 | ADI_APOLLO_LINK_B0, + ADI_APOLLO_JRX_PHASE_ADJ_MARGIN_DEFAULT, + &phase); + if (ret != API_CMS_ERROR_OK) { + dev_err(&phy->spi->dev, + "Error from adi_apollo_jrx_phase_adjust_calc() %d\n", ret); + return ret; + } + entry->val = phase; + return count; + case DBGFS_JTX_LANE_DRIVE_SWING: + if (ret < 3) { + dev_err(&phy->spi->dev, + "Attribute requires 3 arguments \n"); + return -EINVAL; + } + + ret = adi_apollo_jtx_lane_drive_swing_set(&phy->ad9088, val, val2, val3); + if (ret < 0) + return ret; + + dev_info(&phy->spi->dev, + "JTX Lane Drive Swing Set sides: 0x%X lane: %d swing: %d (%d)\n", + (u32)val, val2, val3, ret); + break; + case DBGFS_JTX_LANE_PRE_EMPHASIS: + if (ret < 3) { + dev_err(&phy->spi->dev, "Attribute requires 3 arguments \n"); + return -EINVAL; + } + + ret = adi_apollo_jtx_lane_pre_emphasis_set(&phy->ad9088, val, val2, val3); + if (ret < 0) + return ret; + + dev_info(&phy->spi->dev, "JTX Lane Pre Emphasis Set sides: 0x%X lane: %d emphasis: %d (%d)\n", + (u32)val, val2, val3, ret); + break; + case DBGFS_JTX_LANE_POST_EMPHASIS: + if (ret < 3) { + dev_err(&phy->spi->dev, "Attribute requires 3 arguments \n"); + return -EINVAL; + } + + ret = adi_apollo_jtx_lane_post_emphasis_set(&phy->ad9088, val, val2, val3); + if (ret < 0) + return ret; + + dev_info(&phy->spi->dev, "JTX Lane Post Emphasis Set sides: 0x%X lane: %d emphasis: %d (%d)\n", + (u32)val, val2, val3, ret); + break; + /* MCS calibration commands */ + case DBGFS_MCS_INIT: + if (val) + ret = ad9088_mcs_init_cal_setup(phy); + break; + case DBGFS_MCS_DT0_MEASUREMENT: + if (val) + ret = ad9088_delta_t_measurement_set(phy, 0); + break; + case DBGFS_MCS_DT1_MEASUREMENT: + if (val) + ret = ad9088_delta_t_measurement_set(phy, 1); + break; + case DBGFS_MCS_DT_RESTORE: + if (val) + ret = ad9088_delta_t_measurement_set(phy, 2); + break; + case DBGFS_MCS_CAL_RUN: + if (val) { + ret = adi_apollo_mcs_cal_init_run(&phy->ad9088); + ret = ad9088_check_apollo_error(&phy->spi->dev, ret, + "adi_apollo_mcs_cal_init_run"); + } + break; + case DBGFS_MCS_TRACK_CAL_SETUP: + if (val) + ret = ad9088_mcs_tracking_cal_setup(phy, phy->mcs_track_decimation, 1); + break; + case DBGFS_MCS_TRACK_DECIMATION: + phy->mcs_track_decimation = val; + ret = adi_apollo_mcs_cal_tracking_decimation_set(&phy->ad9088, phy->mcs_track_decimation); + ret = ad9088_check_apollo_error(&phy->spi->dev, ret, "adi_apollo_mcs_cal_tracking_decimation_set"); + break; + case DBGFS_MCS_FG_TRACK_CAL_RUN: + if (val) { + ret = adi_apollo_mcs_cal_fg_tracking_run(&phy->ad9088); + ret = ad9088_check_apollo_error(&phy->spi->dev, ret, + "adi_apollo_mcs_cal_fg_tracking_run"); + } + break; + case DBGFS_MCS_BG_TRACK_CAL_RUN: + if (val) { + ret = adi_apollo_mcs_cal_bg_tracking_run(&phy->ad9088); + ret = ad9088_check_apollo_error(&phy->spi->dev, ret, + "adi_apollo_mcs_cal_bg_tracking_run"); + } else { + ret = adi_apollo_mcs_cal_bg_tracking_abort(&phy->ad9088); + ret = ad9088_check_apollo_error(&phy->spi->dev, ret, + "adi_apollo_mcs_cal_bg_tracking_abort"); + } + if (!ret) + phy->mcs_cal_bg_tracking_run = !!val; + break; + case DBGFS_MCS_TRACK_STATUS: + case DBGFS_MCS_INIT_CAL_STATUS: + /* Read-only attributes */ + return -EINVAL; + default: + break; + } + + if (entry->out_value) { + switch (entry->size) { + case 1: + *(u8 *)entry->out_value = val; + break; + case 2: + *(u16 *)entry->out_value = val; + break; + case 4: + *(u32 *)entry->out_value = val; + break; + case 5: + *(bool *)entry->out_value = val; + break; + case 8: + *(u64 *)entry->out_value = val; + break; + default: + ret = -EINVAL; + } + } + + return count; +} + +static const struct file_operations ad9088_debugfs_reg_fops = { + .open = simple_open, + .read = ad9088_debugfs_read, + .write = ad9088_debugfs_write, +}; + +static void ad9088_add_debugfs_entry(struct ad9088_phy *phy, + struct iio_dev *indio_dev, + const char *propname, unsigned int cmd) +{ + unsigned int i = phy->ad9088_debugfs_entry_index; + + if (WARN_ON(i >= ARRAY_SIZE(phy->debugfs_entry))) + return; + + phy->debugfs_entry[i].indio_dev = indio_dev; + phy->debugfs_entry[i].propname = propname; + phy->debugfs_entry[i].cmd = cmd; + + phy->ad9088_debugfs_entry_index++; +} + +void ad9088_debugfs_register(struct iio_dev *indio_dev) +{ + struct axiadc_converter *conv = iio_device_get_drvdata(indio_dev); + struct ad9088_phy *phy = conv->phy; + int i; + + if (!iio_get_debugfs_dentry(indio_dev)) + return; + + debugfs_create_devm_seqfile(&conv->spi->dev, "status", + iio_get_debugfs_dentry(indio_dev), + ad9088_status_show); + + ad9088_add_debugfs_entry(phy, indio_dev, + "bist_prbs_select_jrx", DBGFS_BIST_PRBS_JRX); + ad9088_add_debugfs_entry(phy, indio_dev, + "bist_prbs_select_jtx", DBGFS_BIST_PRBS_JTX); + ad9088_add_debugfs_entry(phy, indio_dev, + "bist_prbs_error_counters_jrx", DBGFS_BIST_PRBS_JRX_ERR); + ad9088_add_debugfs_entry(phy, indio_dev, + "bist_2d_eyescan_jrx", DBGFS_BIST_JRX_2D_EYE); + ad9088_add_debugfs_entry(phy, indio_dev, + "api_version", DBGFS_DEV_API_INFO); + ad9088_add_debugfs_entry(phy, indio_dev, + "uuid", DBGFS_DEV_UUID_INFO); + ad9088_add_debugfs_entry(phy, indio_dev, + "die_id", DBGFS_DEV_DIE_INFO); + ad9088_add_debugfs_entry(phy, indio_dev, + "chip_version", DBGFS_DEV_CHIP_INFO); + ad9088_add_debugfs_entry(phy, indio_dev, + "clk_pwr_stat", DBGFS_CLK_PWR_STAT); + ad9088_add_debugfs_entry(phy, indio_dev, + "temperature_status", DBGFS_DEV_TEMP_INFO); + ad9088_add_debugfs_entry(phy, indio_dev, + "hsci_enable", DBGFS_HSCI_ENABLE); + ad9088_add_debugfs_entry(phy, indio_dev, + "misc", DBGFS_GENERIC); + ad9088_add_debugfs_entry(phy, indio_dev, + "jrx_phase_adjust_calc", DBGFS_JRX_PHASE_ADJUST_CALC); + ad9088_add_debugfs_entry(phy, indio_dev, + "jtx_lane_drive_swing", DBGFS_JTX_LANE_DRIVE_SWING); + ad9088_add_debugfs_entry(phy, indio_dev, + "jtx_lane_pre_emphasis", DBGFS_JTX_LANE_PRE_EMPHASIS); + ad9088_add_debugfs_entry(phy, indio_dev, + "jtx_lane_post_emphasis", DBGFS_JTX_LANE_POST_EMPHASIS); + + /* MCS calibration entries */ + ad9088_add_debugfs_entry(phy, indio_dev, + "mcs_init", DBGFS_MCS_INIT); + ad9088_add_debugfs_entry(phy, indio_dev, + "mcs_dt0_measurement", DBGFS_MCS_DT0_MEASUREMENT); + ad9088_add_debugfs_entry(phy, indio_dev, + "mcs_dt1_measurement", DBGFS_MCS_DT1_MEASUREMENT); + ad9088_add_debugfs_entry(phy, indio_dev, + "mcs_dt_restore", DBGFS_MCS_DT_RESTORE); + ad9088_add_debugfs_entry(phy, indio_dev, + "mcs_cal_run", DBGFS_MCS_CAL_RUN); + ad9088_add_debugfs_entry(phy, indio_dev, + "mcs_track_cal_setup", DBGFS_MCS_TRACK_CAL_SETUP); + ad9088_add_debugfs_entry(phy, indio_dev, + "mcs_fg_track_cal_run", DBGFS_MCS_FG_TRACK_CAL_RUN); + ad9088_add_debugfs_entry(phy, indio_dev, + "mcs_bg_track_cal_run", DBGFS_MCS_BG_TRACK_CAL_RUN); + ad9088_add_debugfs_entry(phy, indio_dev, + "mcs_track_status", DBGFS_MCS_TRACK_STATUS); + ad9088_add_debugfs_entry(phy, indio_dev, + "mcs_init_cal_status", DBGFS_MCS_INIT_CAL_STATUS); + ad9088_add_debugfs_entry(phy, indio_dev, + "mcs_track_cal_validate", DBGFS_MCS_TRACK_CAL_VALIDATE); + ad9088_add_debugfs_entry(phy, indio_dev, + "mcs_track_decimation", DBGFS_MCS_TRACK_DECIMATION); + + for (i = 0; i < phy->ad9088_debugfs_entry_index; i++) + debugfs_create_file(phy->debugfs_entry[i].propname, 0644, + iio_get_debugfs_dentry(indio_dev), + &phy->debugfs_entry[i], + &ad9088_debugfs_reg_fops); +} diff --git a/drivers/iio/trx-rf/ad9088/ad9088_dt.c b/drivers/iio/trx-rf/ad9088/ad9088_dt.c new file mode 100644 index 00000000000000..aa3d1c94ab90d9 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/ad9088_dt.c @@ -0,0 +1,290 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Driver for AD9088 and similar mixed signal front end (MxFE®) + * + * Copyright 2026 Analog Devices Inc. + */ + +#include "ad9088.h" + +static void ad9088_jrx_lane_set(adi_apollo_jesd_rx_cfg_t *jrx, u8 link, u8 idx) +{ + adi_apollo_jesd_rx_link_cfg_t *link_cfg = &jrx->rx_link_cfg[link]; + + if (!link_cfg->link_in_use || idx > link_cfg->l_minus1) + return; + jrx->common_link_cfg.lane_enables |= (1 << link_cfg->lane_xbar[idx]); +} + +static void ad9088_jtx_lane_set(adi_apollo_jesd_tx_cfg_t *jtx, u8 link, u8 idx) +{ + adi_apollo_jesd_tx_link_cfg_t *link_cfg = &jtx->tx_link_cfg[link]; + + if (!link_cfg->link_in_use || (u32)link_cfg->lane_xbar[idx] > (u32)link_cfg->l_minus1) + return; + jtx->common_link_cfg.lane_enables |= (1 << idx); +} + +static void ad9088_jesd_lane_setup(struct ad9088_phy *phy) +{ + struct device *dev = &phy->spi->dev; + struct device_node *node = dev->of_node; + int ret, i; + u32 lane_xbar[12]; + u32 ser_amplitude = ADI_APOLLO_JESD_DRIVE_SWING_VTT_100; + u32 ser_pre_emphasis = ADI_APOLLO_JESD_PRE_TAP_LEVEL_6_DB; + u32 ser_post_emphasis = ADI_APOLLO_JESD_POST_TAP_LEVEL_3_DB; + + ret = of_property_read_u32_array(node, "adi,jtx0-logical-lane-mapping", + lane_xbar, ARRAY_SIZE(lane_xbar)); + if (!ret) { + dev_dbg(dev, "found adi,jtx0-logical-lane-mapping\n"); + for (i = 0; i < ARRAY_SIZE(lane_xbar); i++) + phy->profile.jtx[0].tx_link_cfg[0].lane_xbar[i] = lane_xbar[i]; + } + + ret = of_property_read_u32_array(node, "adi,jtx1-logical-lane-mapping", + lane_xbar, ARRAY_SIZE(lane_xbar)); + if (!ret) { + dev_dbg(dev, "found adi,jtx1-logical-lane-mapping\n"); + for (i = 0; i < ARRAY_SIZE(lane_xbar); i++) + phy->profile.jtx[1].tx_link_cfg[0].lane_xbar[i] = lane_xbar[i]; + } + + ret = of_property_read_u32_array(node, "adi,jrx0-physical-lane-mapping", + lane_xbar, ARRAY_SIZE(lane_xbar)); + if (!ret) { + dev_dbg(dev, "found adi,jrx0-logical-lane-mapping\n"); + for (i = 0; i < ARRAY_SIZE(lane_xbar); i++) + phy->profile.jrx[0].rx_link_cfg[0].lane_xbar[i] = lane_xbar[i]; + } + + ret = of_property_read_u32_array(node, "adi,jrx1-physical-lane-mapping", + lane_xbar, ARRAY_SIZE(lane_xbar)); + if (!ret) { + dev_dbg(dev, "found adi,jrx1-logical-lane-mapping\n"); + for (i = 0; i < ARRAY_SIZE(lane_xbar); i++) + phy->profile.jrx[1].rx_link_cfg[0].lane_xbar[i] = lane_xbar[i]; + } + + of_property_read_u32(node, "adi,jtx-ser-amplitude", &ser_amplitude); + of_property_read_u32(node, "adi,jtx-ser-pre-emphasis", &ser_pre_emphasis); + of_property_read_u32(node, "adi,jtx-ser-post-emphasis", &ser_post_emphasis); + + phy->profile.jrx[0].common_link_cfg.lane_enables = 0; + phy->profile.jrx[1].common_link_cfg.lane_enables = 0; + phy->profile.jtx[0].common_link_cfg.lane_enables = 0; + phy->profile.jtx[1].common_link_cfg.lane_enables = 0; + + for (i = 0; i < ARRAY_SIZE(lane_xbar); i++) { + phy->profile.jtx[0].serializer_lane[i].ser_amplitude = ser_amplitude; + phy->profile.jtx[0].serializer_lane[i].ser_pre_emphasis = ser_pre_emphasis; + phy->profile.jtx[0].serializer_lane[i].ser_post_emphasis = ser_post_emphasis; + + phy->profile.jtx[1].serializer_lane[i].ser_amplitude = ser_amplitude; + phy->profile.jtx[1].serializer_lane[i].ser_pre_emphasis = ser_pre_emphasis; + phy->profile.jtx[1].serializer_lane[i].ser_post_emphasis = ser_post_emphasis; + + /* JRX */ + ad9088_jrx_lane_set(&phy->profile.jrx[0], 0, i); + ad9088_jrx_lane_set(&phy->profile.jrx[1], 0, i); + /* JRX Link2 */ + ad9088_jrx_lane_set(&phy->profile.jrx[0], 1, i); + ad9088_jrx_lane_set(&phy->profile.jrx[1], 1, i); + /* JTX */ + ad9088_jtx_lane_set(&phy->profile.jtx[0], 0, i); + ad9088_jtx_lane_set(&phy->profile.jtx[1], 0, i); + /* JTX Link2 */ + ad9088_jtx_lane_set(&phy->profile.jtx[0], 1, i); + ad9088_jtx_lane_set(&phy->profile.jtx[1], 1, i); + } +} + +int ad9088_parse_dt(struct ad9088_phy *phy) +{ + struct device *dev = &phy->spi->dev; + struct device_node *node = dev->of_node; + adi_apollo_top_t *p = &phy->profile; + int ret; + u32 val; + const char *name; + bool found; + + phy->spi_3wire_en = of_property_read_bool(node, "adi,spi-3wire-enable"); + + ret = of_property_read_string(node, "adi,device-profile-fw-name", &name); + if (!ret) { + ret = firmware_request_nowarn(&phy->fw, name, dev); + if (ret == -ENOENT) + return dev_err_probe(dev, -EPROBE_DEFER, + "Profile firmware '%s' not available yet, deferring probe\n", + name); + if (ret) + return dev_err_probe(dev, ret, "request_firmware() failed\n"); + + if (sizeof(*p) == phy->fw->size) { + memcpy(p, phy->fw->data, sizeof(*p)); + release_firmware(phy->fw); + phy->device_profile_firmware_load = true; + } else { + release_firmware(phy->fw); + return dev_err_probe(dev, -EINVAL, + "request_firmware() incompatible size %zu != %zu\n", + sizeof(*p), phy->fw->size); + } + } + + /* Check if calibration firmware is available - defer probe if not yet accessible */ + if (!ret) { + ret = of_property_read_string(node, "adi,device-calibration-data-name", &name); + const struct firmware *fw; + + ret = firmware_request_nowarn(&fw, name, dev); + if (ret == -ENOENT) + return dev_err_probe(dev, -EPROBE_DEFER, + "Calibration firmware '%s' not available yet, deferring probe\n", + name); + if (ret) + return dev_err_probe(dev, ret, + "Failed to load calibration firmware '%s': %d\n", + name, ret); + /* + * Firmware is available, release it - will be loaded later in + * ad9088_cal_load_from_firmware() + */ + release_firmware(fw); + } + + phy->complex_rx = !of_property_read_bool(node, "adi,rx-real-channel-en"); + phy->complex_tx = !of_property_read_bool(node, "adi,tx-real-channel-en"); + + if (of_property_read_bool(node, "adi,aion-background-serial-alignment-en")) + phy->aion_background_serial_alignment_en = true; + + phy->side_b_use_own_tpl_en = of_property_read_bool(node, + "adi,side-b-use-seperate-tpl-en"); + + phy->hsci_use_auto_linkup_mode = of_property_read_bool(node, + "adi,hsci-auto-linkup-mode-en"); + + if (of_property_read_bool(node, "adi,hsci-disable-after-boot-en")) + phy->hsci_disable_after_initial_configuration = true; + + phy->multidevice_instance_count = 1; + of_property_read_u32(node, "adi,multidevice-instance-count", + &phy->multidevice_instance_count); + + /* + * MCS tracking calibration TDC decimation rate. A larger value improves + * precision at the expense of longer TDC measurement time. For gapped + * periodic SYSREF, keep below 32768. Default: 1023. + */ + phy->mcs_track_decimation = 1023; + of_property_read_u32(node, "adi,mcs-track-decimation", &phy->mcs_track_decimation); + + phy->trig_sync_en = of_property_read_bool(node, "adi,trigger-sync-en"); + + phy->standalone = of_property_read_bool(node, "adi,standalone-enable"); + + phy->rx_nyquist_zone = 1; + of_property_read_u32(node, "adi,nyquist-zone", &phy->rx_nyquist_zone); + + if (phy->rx_nyquist_zone != 1 && phy->rx_nyquist_zone != 2) + return dev_err_probe(dev, -EINVAL, "Invalid Nyquist zone %u\n", + phy->rx_nyquist_zone); + + phy->fnco_dual_modulus_mode_en = of_property_read_bool(node, + "adi,fnco-dual-modulus-mode-en"); + phy->cnco_dual_modulus_mode_en = of_property_read_bool(node, + "adi,cnco-dual-modulus-mode-en"); + + phy->sniffer_en = !of_property_read_bool(node, "adi,sniffer-disable"); + + phy->cddc_sample_delay_en = of_property_read_bool(node, "adi,cddc-bmem-sample-delay-en"); + phy->fddc_sample_delay_en = of_property_read_bool(node, "adi,fddc-bmem-sample-delay-en"); + + ad9088_jesd_lane_setup(phy); + + /* + * IIO channel scan_index remapping for lane swap compensation. + * When FPGA lane routing causes DMA buffer positions to not match + * the physical channel order, use this array to remap scan_index. + * Value at index i specifies which DMA buffer position IIO channel i + * should read from. A value of -1 means no remapping (identity). + * + * Array covers: channelizers * 2 (I/Q) * multidevice_instance_count (max 4) + * + * Example: If sides are swapped (Side B data in DMA pos 0-3, + * Side A data in DMA pos 4-7): + * adi,rx-iio-to-phy-remap = /bits/ 8 <4 5 6 7 0 1 2 3>; + */ + memset(phy->rx_iio_to_phy_remap, -1, sizeof(phy->rx_iio_to_phy_remap)); + + ret = of_property_read_variable_u8_array(node, "adi,rx-iio-to-phy-remap", + (u8 *)phy->rx_iio_to_phy_remap, + 1, MAX_NUM_REMAP_CHANNELS); + if (ret > 0) + dev_info(dev, "RX IIO-to-PHY channel remap: %d entries\n", ret); + + found = of_property_read_bool(node, "adi,dformat-ddc-dither-en"); + if (found) { + phy->profile.rx_path[0].rx_dformat[0].ddc_dither_en = found; + phy->profile.rx_path[0].rx_dformat[1].ddc_dither_en = found; + phy->profile.rx_path[1].rx_dformat[0].ddc_dither_en = found; + phy->profile.rx_path[1].rx_dformat[1].ddc_dither_en = found; + } + + ret = of_property_read_u32(node, "adi,subclass", &val); + if (!ret) { + phy->profile.jtx[0].common_link_cfg.subclass = val; + phy->profile.jtx[1].common_link_cfg.subclass = val; + phy->profile.jrx[0].common_link_cfg.subclass = val; + phy->profile.jrx[1].common_link_cfg.subclass = val; + } + + if (phy->profile.profile_cfg.profile_version.major != ADI_APOLLO_PROFILE_VERSION_MAJOR || + phy->profile.profile_cfg.profile_version.minor != ADI_APOLLO_PROFILE_VERSION_MINOR) { + dev_err(dev, "Incompatible profile version %u.%u != %u.%u\n", + phy->profile.profile_cfg.profile_version.major, + phy->profile.profile_cfg.profile_version.minor, + ADI_APOLLO_PROFILE_VERSION_MAJOR, + ADI_APOLLO_PROFILE_VERSION_MINOR); + + return -EINVAL; + } + + /* FIXME ! */ + if (phy->profile.profile_cfg.profile_version.patch < 3) { + dev_warn(dev, "Old profile version patch %u, updating to %u\n", + phy->profile.profile_cfg.profile_version.patch, 3); + + phy->profile.profile_cfg.profile_version.patch = 3; + phy->profile.reserved_cfg[4] = phy->profile.reserved_cfg[0]; + phy->profile.reserved_cfg[5] = phy->profile.reserved_cfg[1]; + phy->profile.reserved_cfg[0] = 0; + phy->profile.reserved_cfg[1] = 0; + phy->profile.mcs_cfg.center_sysref.sysref_present = true; + } + + /* ADF4382 clock align GPIO configuration - set defaults */ + p->mcs_cfg.adf4382_cfg.clock_align_delay_adjust_gpio[0] = 16; + p->mcs_cfg.adf4382_cfg.clock_align_delay_adjust_gpio[1] = 0; + p->mcs_cfg.adf4382_cfg.clock_align_delay_strobe_gpio[0] = 15; + p->mcs_cfg.adf4382_cfg.clock_align_delay_strobe_gpio[1] = 0; + + /* Allow device tree to override */ + of_property_read_variable_u8_array(node, "adi,clock-align-delay-adjust-gpio-num", + p->mcs_cfg.adf4382_cfg.clock_align_delay_adjust_gpio, + 1, ADI_APOLLO_NUM_ADF4382_GPIOS); + + of_property_read_variable_u8_array(node, "adi,clock-align-delay-strobe-gpio-num", + p->mcs_cfg.adf4382_cfg.clock_align_delay_strobe_gpio, + 1, ADI_APOLLO_NUM_ADF4382_GPIOS); + + dev_dbg(dev, "Profile CRC32 %u\n", phy->profile.profile_checksum); + phy->profile.profile_checksum = crc32_be(0, (unsigned char const *)p, + sizeof(*p) - sizeof(u32)); + dev_dbg(dev, "Profile CRC32 %u\n", phy->profile.profile_checksum); + + return 0; +} diff --git a/drivers/iio/trx-rf/ad9088/ad9088_ffh.c b/drivers/iio/trx-rf/ad9088/ad9088_ffh.c new file mode 100644 index 00000000000000..5ed972144ec46a --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/ad9088_ffh.c @@ -0,0 +1,441 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Driver for AD9088 and similar mixed signal front end (MxFE®) + * + * Copyright 2025 Analog Devices Inc. + */ +#include +#include +#include +#include "ad9088.h" + +/** + * ad9088_read_gpio_hop_array - Read GPIO hop array from device tree + * @dev: Device pointer + * @propname: Device tree property name + * @array: Output array to fill + * @count: Maximum number of elements to read + * + * Reads GPIO indices from device tree and fills the array. Missing values + * are filled with ADI_APOLLO_GPIO_HOP_IDX_NONE (-1). + * + * Return: Number of GPIOs read, or 0 if property not found + */ +static int ad9088_read_gpio_hop_array(struct device *dev, const char *propname, + s8 *array, size_t count) +{ + u32 tmp[ADI_APOLLO_GPIO_HOP_PROFILE_BIT_NUMBER]; /* max number */ + int ret, i; + + /* Initialize all to NONE (-1) */ + for (i = 0; i < count; i++) + array[i] = ADI_APOLLO_GPIO_HOP_IDX_NONE; + + ret = device_property_count_u32(dev, propname); + if (ret <= 0) + return 0; + + /* Read up to count values */ + ret = device_property_read_u32_array(dev, propname, tmp, + min(ret, (int)count)); + if (ret < 0) + return 0; + + /* Copy to output array */ + for (i = 0; i < ret; i++) + array[i] = tmp[i]; + + return ret; +} + +int ad9088_ffh_probe(struct ad9088_phy *phy) +{ + adi_apollo_fine_nco_hop_t fnco_hop_config; + adi_apollo_coarse_nco_hop_t cnco_hop_config; + struct device *dev = &phy->spi->dev; + int ret, n_gpios; + + fnco_hop_config.nco_trig_hop_sel = ADI_APOLLO_FNCO_TRIG_HOP_FREQ_PHASE; + fnco_hop_config.profile_sel_mode = ADI_APOLLO_NCO_CHAN_SEL_DIRECT_REGMAP; + cnco_hop_config.auto_mode = ADI_APOLLO_NCO_AUTO_HOP_DECR; + cnco_hop_config.profile_sel_mode = ADI_APOLLO_NCO_CHAN_SEL_DIRECT_REGMAP; + + ret = adi_apollo_fnco_hop_pgm(&phy->ad9088, ADI_APOLLO_RX, + ADI_APOLLO_CNCO_ALL, &fnco_hop_config); + if (ret) + return ret; + ret = adi_apollo_fnco_hop_pgm(&phy->ad9088, ADI_APOLLO_TX, + ADI_APOLLO_FNCO_ALL, &fnco_hop_config); + if (ret) + return ret; + ret = adi_apollo_cnco_hop_enable(&phy->ad9088, ADI_APOLLO_RX, + ADI_APOLLO_CNCO_ALL, &cnco_hop_config); + if (ret) + return ret; + ret = adi_apollo_cnco_hop_enable(&phy->ad9088, ADI_APOLLO_TX, + ADI_APOLLO_CNCO_ALL, &cnco_hop_config); + if (ret) + return ret; + + /* Read GPIO hop profile configuration directly into phy structure */ + n_gpios = ad9088_read_gpio_hop_array(dev, "adi,gpio-hop-profile", + (s8 *)phy->gpio_hop_profile.index, + ADI_APOLLO_GPIO_HOP_PROFILE_BIT_NUMBER); + if (n_gpios > 0) { + ret = adi_apollo_gpio_hop_profile_configure(&phy->ad9088, + &phy->gpio_hop_profile); + if (ret) + return dev_err_probe(dev, ret, "Failed to configure GPIO hop profile\n"); + + dev_info(dev, "Configured %d GPIO hop profile bits\n", n_gpios); + } + + /* Read GPIO hop block configuration directly into phy structure */ + n_gpios = ad9088_read_gpio_hop_array(dev, "adi,gpio-hop-block", + (s8 *)phy->gpio_hop_block.index, + ADI_APOLLO_GPIO_HOP_BLOCK_BIT_NUMBER); + if (n_gpios > 0) { + ret = adi_apollo_gpio_hop_block_configure(&phy->ad9088, + &phy->gpio_hop_block); + if (ret) + return dev_err_probe(dev, ret, "Failed to configure GPIO hop block\n"); + + dev_info(dev, "Configured %d GPIO hop block bits\n", n_gpios); + } + + /* Read GPIO hop side configuration directly into phy structure */ + n_gpios = ad9088_read_gpio_hop_array(dev, "adi,gpio-hop-side", + (s8 *)phy->gpio_hop_side.index, + ADI_APOLLO_GPIO_HOP_SIDE_BIT_NUMBER); + if (n_gpios > 0) { + ret = adi_apollo_gpio_hop_side_configure(&phy->ad9088, + &phy->gpio_hop_side); + if (ret) + return dev_err_probe(dev, ret, "Failed to configure GPIO hop side\n"); + + dev_info(dev, "Configured %d GPIO hop side bits\n", n_gpios); + } + + /* Read GPIO hop slice configuration directly into phy structure */ + n_gpios = ad9088_read_gpio_hop_array(dev, "adi,gpio-hop-slice", + (s8 *)phy->gpio_hop_slice.index, + ADI_APOLLO_GPIO_HOP_SLICE_BIT_NUMBER); + if (n_gpios > 0) { + ret = adi_apollo_gpio_hop_slice_configure(&phy->ad9088, + &phy->gpio_hop_slice); + if (ret) + return dev_err_probe(dev, ret, "Failed to configure GPIO hop slice\n"); + + dev_info(dev, "Configured %d GPIO hop slice bits\n", n_gpios); + } + + /* Read GPIO hop terminal configuration directly into phy structure */ + n_gpios = ad9088_read_gpio_hop_array(dev, "adi,gpio-hop-terminal", + (s8 *)phy->gpio_hop_terminal.index, + ADI_APOLLO_GPIO_HOP_TERMINAL_BIT_NUMBER); + if (n_gpios > 0) { + ret = adi_apollo_gpio_hop_terminal_configure(&phy->ad9088, + &phy->gpio_hop_terminal); + if (ret) + return dev_err_probe(dev, ret, "Failed to configure GPIO hop terminal\n"); + + dev_info(dev, "Configured %d GPIO hop terminal bits\n", n_gpios); + } + + /* Cache defaults */ + memset(&phy->ffh, 0, sizeof(union ad9088_ffh)); + for (u8 i = 0; i < ADI_APOLLO_FNCO_PROFILE_NUM; i++) { + for (u8 j = 0; j < 2; j++) + phy->ffh.dir[j].fnco.mode[i] = cnco_hop_config.profile_sel_mode; + } + for (u8 i = 0; i < ADI_APOLLO_CNCO_PROFILE_NUM; i++) { + for (u8 j = 0; j < 2; j++) + phy->ffh.dir[j].cnco.mode[i] = fnco_hop_config.profile_sel_mode; + } + + return ret; +} + +ssize_t ad9088_ext_info_read_ffh(struct iio_dev *indio_dev, uintptr_t private, + const struct iio_chan_spec *chan, char *buf) +{ + struct axiadc_converter *conv = iio_device_get_drvdata(indio_dev); + u8 dir = chan->output ? ADI_APOLLO_TX : ADI_APOLLO_RX; + struct ad9088_phy *phy = conv->phy; + const struct ad9088_chan_map *map = ad9088_get_chan_map(phy, chan); + u8 index; + + if (!map) + return -EINVAL; + + guard(mutex)(&phy->lock); + + switch (private) { + case FFH_FNCO_INDEX: + return sysfs_emit(buf, "%u\n", phy->ffh.dir[dir].fnco.index[map->fddc_num]); + case FFH_FNCO_FREQUENCY: + index = phy->ffh.dir[dir].fnco.index[map->fddc_num]; + if (index >= ADI_APOLLO_FNCO_PROFILE_NUM) + return -EINVAL; + return sysfs_emit(buf, "%llu\n", phy->ffh.dir[dir].fnco.frequency[index]); + case FFH_FNCO_SELECT: + return sysfs_emit(buf, "%u\n", phy->ffh.dir[dir].fnco.select[map->fddc_num] - 1); + case FFH_FNCO_MODE: + return sysfs_emit(buf, "%u\n", phy->ffh.dir[dir].fnco.mode[map->fddc_num]); + case FFH_CNCO_INDEX: + return sysfs_emit(buf, "%u\n", phy->ffh.dir[dir].cnco.index[map->fddc_num]); + case FFH_CNCO_FREQUENCY: + index = phy->ffh.dir[dir].cnco.index[map->cddc_num]; + if (index >= ADI_APOLLO_CNCO_PROFILE_NUM) + return -EINVAL; + return sysfs_emit(buf, "%llu\n", phy->ffh.dir[dir].cnco.frequency[index]); + case FFH_CNCO_SELECT: + return sysfs_emit(buf, "%u\n", phy->ffh.dir[dir].cnco.select[map->cddc_num]); + case FFH_CNCO_MODE: + return sysfs_emit(buf, "%u\n", phy->ffh.dir[dir].cnco.mode[map->cddc_num]); + default: + return -EINVAL; + } +} + +ssize_t ad9088_ext_info_write_ffh(struct iio_dev *indio_dev, uintptr_t private, + const struct iio_chan_spec *chan, + const char *buf, size_t len) +{ + struct axiadc_converter *conv = iio_device_get_drvdata(indio_dev); + u8 dir = chan->output ? ADI_APOLLO_TX : ADI_APOLLO_RX; + struct ad9088_phy *phy = conv->phy; + const struct ad9088_chan_map *map = ad9088_get_chan_map(phy, chan); + u8 fnco_num, cnco_num; + u8 index; + u32 ftw_u32; + u32 cddc_dcm; + u16 fnco_en, cnco_en; + bool hop_enable; + u64 val, ret; + u64 ftw_u64, f, tmp; + + if (!map) + return -EINVAL; + + guard(mutex)(&phy->lock); + + switch (private) { + case FFH_FNCO_INDEX: + if (map->fddc_num > ADI_APOLLO_FNCO_PROFILE_NUM) + return -EINVAL; + + ret = kstrtou64(buf, 10, &val); + if (ret || val >= ADI_APOLLO_FNCO_PROFILE_NUM || val < 0) + return -EINVAL; + + phy->ffh.dir[dir].fnco.index[map->fddc_num] = val; + return len; + case FFH_FNCO_FREQUENCY: + fnco_num = map->fddc_num + map->side * 8; + fnco_en = GENMASK(fnco_num + 1, fnco_num); + + ret = kstrtou64(buf, 10, &val); + if (ret || val < 0) + return -EINVAL; + + index = phy->ffh.dir[dir].fnco.index[map->fddc_num]; + if (index >= ADI_APOLLO_FNCO_PROFILE_NUM) + return -EINVAL; + + /* Needs to be enabled to apply */ + ret = adi_apollo_fnco_hop_enable(&phy->ad9088, dir, fnco_en, true); + if (ret) + return -EFAULT; + if (chan->output) { + adi_apollo_cduc_interp_bf_to_val(&phy->ad9088, phy->profile.tx_path[map->side].tx_cduc[map->cddc_num].drc_ratio, &cddc_dcm); + f = phy->profile.dac_cfg[map->side].dac_sampling_rate_Hz; + } else { + adi_apollo_cddc_dcm_bf_to_val(&phy->ad9088, phy->profile.rx_path[map->side].rx_cddc[map->cddc_num].drc_ratio, &cddc_dcm); + f = phy->profile.adc_cfg[map->side].adc_sampling_rate_Hz; + } + adi_ad9088_calc_nco_ftw(phy, f, val, cddc_dcm, 32, &ftw_u64, &tmp, &tmp); + ftw_u32 = ftw_u64; + ret = adi_apollo_fnco_profile_load(&phy->ad9088, dir, fnco_en, + ADI_APOLLO_NCO_PROFILE_PHASE_INCREMENT, + index, &ftw_u32, 1); + if (ret) + return -EFAULT; + phy->ffh.dir[dir].fnco.frequency[index] = val; + /* Restore state */ + adi_apollo_fnco_hop_enable(&phy->ad9088, dir, fnco_en, + phy->ffh.dir[dir].fnco.en[index]); + if (ret) + return -EFAULT; + return len; + case FFH_FNCO_SELECT: + fnco_num = map->fddc_num + map->side * 8; + fnco_en = GENMASK(fnco_num + 1, fnco_num); + + ret = kstrtou64(buf, 10, &val); + hop_enable = !(val == -1); + if (ret || val >= ADI_APOLLO_FNCO_PROFILE_NUM || val < -1) + return -EINVAL; + + ret = adi_apollo_fnco_hop_enable(&phy->ad9088, dir, fnco_en, + hop_enable); + if (ret) + return -EFAULT; + + phy->ffh.dir[dir].fnco.en[map->fddc_num] = hop_enable; + if (!hop_enable) + return len; + + if (phy->ffh.dir[dir].fnco.mode[map->fddc_num] == ADI_APOLLO_NCO_CHAN_SEL_TRIG_GPIO || + phy->ffh.dir[dir].fnco.mode[map->fddc_num] == ADI_APOLLO_NCO_CHAN_SEL_DIRECT_GPIO) { + u64 gpio, val2; + + ret = adi_apollo_gpio_hop_profile_calc(&phy->ad9088, + &phy->gpio_hop_profile, + val, &gpio, &val2); + if (ret) + return ret; + + dev_info(&conv->spi->dev, "Profile GPIO: mask: %llx value: %llx\n", + gpio, val2); + + ret = adi_apollo_gpio_hop_block_calc(&phy->ad9088, + &phy->gpio_hop_block, + 0, &gpio, &val2); + if (ret) + return ret; + + dev_info(&conv->spi->dev, + "Block GPIO: mask: %llx value: %llx\n", + gpio, val2); + } + + if (phy->ffh.dir[dir].fnco.mode[map->fddc_num] != ADI_APOLLO_NCO_CHAN_SEL_DIRECT_REGMAP && + phy->ffh.dir[dir].fnco.mode[map->fddc_num] != ADI_APOLLO_NCO_CHAN_SEL_TRIG_REGMAP) + return -EINVAL; + + ret = adi_apollo_fnco_active_profile_set(&phy->ad9088, dir, fnco_en, val); + if (ret) + return -EFAULT; + + /* Increment by 1 to use 0 to flag disabled */ + phy->ffh.dir[dir].fnco.select[map->fddc_num] = val + 1; + phy->ffh.dir[dir].fnco.en[map->fddc_num] = hop_enable; + return len; + case FFH_FNCO_MODE: + fnco_num = map->fddc_num + map->side * 8; + fnco_en = GENMASK(fnco_num + 1, fnco_num); + + if (map->fddc_num > ADI_APOLLO_FNCO_PROFILE_NUM) + return -EINVAL; + + ret = kstrtou64(buf, 10, &val); + if (ret || val > ADI_APOLLO_NCO_CHAN_SEL_DIRECT_REGMAP) + return -EINVAL; + + ret = adi_apollo_fnco_profile_sel_mode_set(&phy->ad9088, dir, fnco_en, val); + if (ret) + return -EFAULT; + + phy->ffh.dir[dir].fnco.mode[map->fddc_num] = val; + return len; + case FFH_CNCO_INDEX: + if (map->cddc_num > ADI_APOLLO_CNCO_PROFILE_NUM) + return -EINVAL; + + ret = kstrtou64(buf, 10, &val); + if (ret || val >= ADI_APOLLO_CNCO_PROFILE_NUM || val < 0) + return -EINVAL; + + phy->ffh.dir[dir].cnco.index[map->cddc_num] = val; + return len; + case FFH_CNCO_FREQUENCY: + cnco_num = map->cddc_num + map->side * 4; + cnco_en = BIT(cnco_num); + + ret = kstrtou64(buf, 10, &val); + if (ret || val < 0) + return -EINVAL; + + index = phy->ffh.dir[dir].cnco.index[map->cddc_num]; + if (index >= ADI_APOLLO_CNCO_PROFILE_NUM) + return -EINVAL; + + if (chan->output) + adi_ad9088_calc_nco_ftw(phy, phy->profile.dac_cfg[map->side].dac_sampling_rate_Hz, + val, 1, 32, &ftw_u64, &tmp, &tmp); + else + adi_ad9088_calc_nco_ftw(phy, phy->profile.adc_cfg[map->side].adc_sampling_rate_Hz, + val, 1, 32, &ftw_u64, &tmp, &tmp); + ftw_u32 = ftw_u64; + ret = adi_apollo_cnco_profile_load(&phy->ad9088, dir, cnco_en, + ADI_APOLLO_NCO_PROFILE_PHASE_INCREMENT, + index, &ftw_u32, 1); + if (ret) + return -EFAULT; + + phy->ffh.dir[dir].cnco.frequency[index] = val; + return len; + case FFH_CNCO_SELECT: + cnco_num = map->cddc_num + map->side * 4; + cnco_en = BIT(cnco_num); + + ret = kstrtou64(buf, 10, &val); + if (ret || val >= ADI_APOLLO_CNCO_PROFILE_NUM || val < 0) + return -EINVAL; + + if (phy->ffh.dir[dir].cnco.mode[map->cddc_num] == ADI_APOLLO_NCO_CHAN_SEL_TRIG_GPIO || + phy->ffh.dir[dir].cnco.mode[map->cddc_num] == ADI_APOLLO_NCO_CHAN_SEL_DIRECT_GPIO) { + u64 gpio, val2; + + ret = adi_apollo_gpio_hop_profile_calc(&phy->ad9088, + &phy->gpio_hop_profile, + val, &gpio, &val2); + if (ret) + return ret; + + dev_info(&conv->spi->dev, "Profile GPIO: mask: %llx value: %llx\n", + gpio, val2); + + ret = adi_apollo_gpio_hop_block_calc(&phy->ad9088, + &phy->gpio_hop_block, + 0, &gpio, &val2); + if (ret) + return ret; + + dev_info(&conv->spi->dev, + "Block GPIO: mask: %llx value: %llx\n", + gpio, val2); + } + + if (phy->ffh.dir[dir].cnco.mode[map->cddc_num] != ADI_APOLLO_NCO_CHAN_SEL_DIRECT_REGMAP && + phy->ffh.dir[dir].cnco.mode[map->cddc_num] != ADI_APOLLO_NCO_CHAN_SEL_TRIG_REGMAP) + return -EINVAL; + + ret = adi_apollo_cnco_active_profile_set(&phy->ad9088, dir, cnco_en, val); + if (ret) + return -EFAULT; + + phy->ffh.dir[dir].cnco.select[map->cddc_num] = val; + return len; + case FFH_CNCO_MODE: + cnco_num = map->cddc_num + map->side * 4; + cnco_en = BIT(cnco_num); + + if (map->cddc_num > ADI_APOLLO_CNCO_PROFILE_NUM) + return -EINVAL; + + ret = kstrtou64(buf, 10, &val); + if (ret || val > ADI_APOLLO_NCO_CHAN_SEL_DIRECT_REGMAP) + return -EINVAL; + + ret = adi_apollo_cnco_profile_sel_mode_set(&phy->ad9088, dir, cnco_en, val); + if (ret) + return -EFAULT; + + phy->ffh.dir[dir].cnco.mode[map->cddc_num] = val; + return len; + default: + return -EINVAL; + } +} diff --git a/drivers/iio/trx-rf/ad9088/ad9088_fft.c b/drivers/iio/trx-rf/ad9088/ad9088_fft.c new file mode 100644 index 00000000000000..04747c61c694fd --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/ad9088_fft.c @@ -0,0 +1,777 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Driver for AD9088 and similar mixed signal front end (MxFE®) + * + * Copyright 2026 Analog Devices Inc. + */ + +#include "ad9088.h" + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include "adi_apollo_bf_rx_spectrum_sniffer.h" + +#define AD9088_FFT_SNIFFER_SI_INDEX 0 +#define AD9088_FFT_SNIFFER_I_INDEX 1 +#define AD9088_FFT_SNIFFER_Q_INDEX 2 +#define AD9088_FFT_SNIFFER_MAGN_INDEX 3 +#define AD9088_FFT_SNIFFER_CHAN_MAX 4 + +static const unsigned long ad9088_fft_sniffer_available_scan_masks[] = { + BIT(AD9088_FFT_SNIFFER_SI_INDEX) | BIT(AD9088_FFT_SNIFFER_I_INDEX) | + BIT(AD9088_FFT_SNIFFER_Q_INDEX), + BIT(AD9088_FFT_SNIFFER_SI_INDEX) | BIT(AD9088_FFT_SNIFFER_MAGN_INDEX), + 0x00000000, +}; + +struct ad9088_fft_sniffer_state { + struct device *dev; + struct iio_trigger *trig; + /* lock to protect device state */ + struct mutex lock; + struct completion complete; + struct ad9088_phy *phy; + int irq; + u32 regmap_base; + u32 delay_ms; + u32 mode; + struct delayed_work sync_work; + struct iio_dev *indio_dev; + + u32 side_sel; + u16 adc_select; + adi_apollo_sniffer_param_t sniffer_config; + adi_apollo_sniffer_param_t sniffer_config_hw; + adi_apollo_sniffer_fft_data_t fft_data; + + __le16 buffer[AD9088_FFT_SNIFFER_CHAN_MAX]; + __le16 buffer_hw[AD9088_FFT_SNIFFER_CHAN_MAX] __aligned(IIO_DMA_MINALIGN); +}; + +enum { + AD9088_FTT_MAX_THRESHOLD, + AD9088_FTT_MIN_THRESHOLD, +}; + +static int ad9088_rx_sniffer_populate_default_params(adi_apollo_sniffer_mode_e mode, + adi_apollo_sniffer_param_t *config) +{ + config->init.fft_hold_sel = 1; // 0 - gpio 1 - regmap + config->init.fft_enable_sel = 1; // 0 - gpio 1 - regmap + config->init.real_mode = 1; // 1 real 0 complex + config->init.max_threshold = 255; // Max threshold for max + config->init.min_threshold = 0; // Min threshold for min + config->init.sniffer_enable = 1; // Enable spec sniffer + + config->pgm.sniffer_mode = mode; // see \ref adi_apollo_sniffer_mode_e + config->pgm.sort_enable = 0; // 1 enable 0 disable + config->pgm.continuous_mode = 0; // 1 continuous 0 single + config->pgm.bottom_fft_enable = 0; // 1 enable 0 disable + config->pgm.window_enable = 0; // 1 enable 0 disable + config->pgm.low_power_enable = 0; // 1 enable 0 disable + config->pgm.dither_enable = 0; // 1 enable 0 disable + config->pgm.alpha_factor = 0; // exp. avg. 0 - disable 1-8 - enable + config->pgm.adc = ADI_APOLLO_ADC_0; + + config->read.run_fft_engine_background = 0; + config->read.timeout_us = 1000; + + if (mode > ADI_APOLLO_SNIFFER_INSTANT_MAGNITUDE) { // IQ mode necessities + config->init.real_mode = 0; + config->pgm.sort_enable = 0; + config->pgm.continuous_mode = 0; + config->pgm.alpha_factor = 0; + } + + return API_CMS_ERROR_OK; +} + +static int ad9088_fft_sniffer_request(struct ad9088_fft_sniffer_state *st) +{ + int ret; + + /* Set FFT enable high */ + ret = adi_apollo_sniffer_fft_enable_set(&st->phy->ad9088, st->side_sel, 1); + if (ret) + return ret; + + /* Set FFT hold low to request new data */ + return adi_apollo_sniffer_fft_hold_set(&st->phy->ad9088, st->side_sel, 0); +} + +static int ad9088_fft_sniffer_data_read(struct ad9088_fft_sniffer_state *st, + adi_apollo_sniffer_param_t *config) +{ + adi_apollo_device_t *device = &st->phy->ad9088; + adi_apollo_sniffer_fft_data_t *fft_data = &st->fft_data; + u8 fft_done = 0; + bool iq_mode; + int ret, i, j; + + /* Check if FFT is done */ + ret = adi_apollo_sniffer_fft_done_get(device, st->side_sel, &fft_done); + if (ret) { + dev_err(st->dev, "Failed to get FFT done status: %d\n", ret); + return ret; + } + + if (!fft_done) { + dev_dbg(st->dev, "FFT not done\n"); + return 0; + } + + /* Disable FFT engine if not running in background */ + if (!config->read.run_fft_engine_background) { + ret = adi_apollo_sniffer_fft_enable_set(device, st->side_sel, 0); + if (ret) + dev_err(st->dev, "Failed to disable FFT engine: %d\n", ret); + } + + /* Hold FFT data */ + ret = adi_apollo_sniffer_fft_hold_set(device, st->side_sel, 1); + if (ret) { + dev_err(st->dev, "Failed to hold FFT: %d\n", ret); + return ret; + } + + /* Read FFT data using new API */ + ret = adi_apollo_sniffer_fft_data_get(device, st->side_sel, config, fft_data); + if (ret) { + dev_err(st->dev, "Failed to get FFT data: %d\n", ret); + return ret; + } + + iq_mode = config->pgm.sniffer_mode > ADI_APOLLO_SNIFFER_INSTANT_MAGNITUDE; + + /* Push data to IIO buffer */ + for (i = 0; i < fft_data->valid_data_length; i++) { + j = 0; + + if (st->indio_dev->active_scan_mask[0] & BIT(AD9088_FFT_SNIFFER_SI_INDEX)) + st->buffer[j++] = iq_mode ? i : fft_data->bin_q_data[i]; + + if (st->indio_dev->active_scan_mask[0] & BIT(AD9088_FFT_SNIFFER_I_INDEX)) + st->buffer[j++] = fft_data->mag_i_data[i]; + + if (st->indio_dev->active_scan_mask[0] & BIT(AD9088_FFT_SNIFFER_Q_INDEX)) + st->buffer[j++] = fft_data->bin_q_data[i]; + + if (st->indio_dev->active_scan_mask[0] & BIT(AD9088_FFT_SNIFFER_MAGN_INDEX)) + st->buffer[j++] = fft_data->mag_i_data[i]; + + iio_push_to_buffers(st->indio_dev, st->buffer); + } + + return 0; +} + +static ssize_t ad9088_fft_sniffer_ext_info_read(struct iio_dev *indio_dev, + uintptr_t private, + const struct iio_chan_spec *chan, char *buf) +{ + struct ad9088_fft_sniffer_state *st = iio_priv(indio_dev); + struct ad9088_phy *phy = st->phy; + + guard(mutex)(&phy->lock); + + switch (private) { + case AD9088_FTT_MAX_THRESHOLD: + return sysfs_emit(buf, "%u\n", st->sniffer_config.init.max_threshold); + case AD9088_FTT_MIN_THRESHOLD: + return sysfs_emit(buf, "%u\n", st->sniffer_config.init.min_threshold); + default: + return -EINVAL; + } +} + +static ssize_t ad9088_fft_sniffer_ext_info_write(struct iio_dev *indio_dev, + uintptr_t private, + const struct iio_chan_spec *chan, + const char *buf, size_t len) +{ + struct ad9088_fft_sniffer_state *st = iio_priv(indio_dev); + struct ad9088_phy *phy = st->phy; + long long readin; + int ret; + u8 val; + + ret = kstrtoll(buf, 10, &readin); + if (ret) + return ret; + + val = clamp(readin, 0, 255); + + guard(mutex)(&phy->lock); + + switch (private) { + case AD9088_FTT_MAX_THRESHOLD: + ret = adi_apollo_hal_bf_set(&st->phy->ad9088, + BF_MAX_THRESHOLD_INFO(st->regmap_base), val); + if (ret) + return ret; + + st->sniffer_config.init.max_threshold = val; + return len; + case AD9088_FTT_MIN_THRESHOLD: + ret = adi_apollo_hal_bf_set(&st->phy->ad9088, + BF_MIN_THRESHOLD_INFO(st->regmap_base), val); + if (ret) + return ret; + + st->sniffer_config.init.min_threshold = val; + return len; + default: + return -EINVAL; + } +} + +static const char *const ad9088_fft_sniffer_modes[] = { + [0] = "normal", + [1] = "instant", +}; + +static int ad9088_fft_sniffer_modes_read(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan) +{ + struct ad9088_fft_sniffer_state *st = iio_priv(indio_dev); + + guard(mutex)(&st->phy->lock); + return st->mode; +} + +static int ad9088_fft_sniffer_modes_write(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + unsigned int item) +{ + struct ad9088_fft_sniffer_state *st = iio_priv(indio_dev); + + scoped_guard(mutex, &st->phy->lock) + st->mode = item; + + return 0; +} + +static const char *const ad9088_fft_sniffer_adc_select[] = { + [0] = "adc0", + [1] = "adc1", + [2] = "adc2", + [3] = "adc3", +}; + +static int ad9088_fft_sniffer_adc_select_read(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan) +{ + struct ad9088_fft_sniffer_state *st = iio_priv(indio_dev); + int i; + + guard(mutex)(&st->phy->lock); + + /* Convert bit position to array index (0x1->0, 0x2->1, 0x4->2, 0x8->3) */ + for (i = 0; i < ARRAY_SIZE(ad9088_fft_sniffer_adc_select); i++) { + if (st->adc_select == BIT(i)) + return i; + } + + return -EINVAL; +} + +static int ad9088_fft_sniffer_adc_select_write(struct iio_dev *indio_dev, + const struct iio_chan_spec *chan, + unsigned int item) +{ + struct ad9088_fft_sniffer_state *st = iio_priv(indio_dev); + struct ad9088_phy *phy = st->phy; + bool is_8t8r = phy->ad9088.dev_info.is_8t8r; + int ret; + + /* Validate item range */ + if (item >= ARRAY_SIZE(ad9088_fft_sniffer_adc_select)) + return -EINVAL; + + /* For 4t4r, only ADC0 and ADC1 are valid */ + if (!is_8t8r && item > 1) + return -EINVAL; + + guard(mutex)(&phy->lock); + + /* Convert index to bit position (0->0x1, 1->0x2, 2->0x4, 3->0x8) */ + st->adc_select = BIT(item); + + /* Apply ADC mux setting */ + ret = adi_apollo_sniffer_adc_mux_set(&phy->ad9088, st->side_sel, + st->adc_select); + if (ret) { + dev_err(st->dev, "Failed to set ADC mux: %d\n", ret); + return ret; + } + + return 0; +} + +static ssize_t ad9088_fft_sniffer_adc_select_available(struct iio_dev *indio_dev, + uintptr_t private, + const struct iio_chan_spec *chan, + char *buf) +{ + struct ad9088_fft_sniffer_state *st = iio_priv(indio_dev); + struct ad9088_phy *phy = st->phy; + bool is_8t8r = phy->ad9088.dev_info.is_8t8r; + int i, len = 0; + int max_adc = is_8t8r ? 4 : 2; + + for (i = 0; i < max_adc; i++) + len += sysfs_emit_at(buf, len, "%s ", ad9088_fft_sniffer_adc_select[i]); + + buf[len - 1] = '\n'; + + return len; +} + +static const struct iio_enum ad9088_testmode_enum = { + .items = ad9088_fft_sniffer_modes, + .num_items = ARRAY_SIZE(ad9088_fft_sniffer_modes), + .set = ad9088_fft_sniffer_modes_write, + .get = ad9088_fft_sniffer_modes_read, +}; + +static const struct iio_enum ad9088_adc_select_enum = { + .items = ad9088_fft_sniffer_adc_select, + .num_items = ARRAY_SIZE(ad9088_fft_sniffer_adc_select), + .set = ad9088_fft_sniffer_adc_select_write, + .get = ad9088_fft_sniffer_adc_select_read, +}; + +static struct iio_chan_spec_ext_info ad9088_fft_sniffer_ext_info[] = { + IIO_ENUM("mode", IIO_SHARED_BY_ALL, &ad9088_testmode_enum), + IIO_ENUM_AVAILABLE("mode", IIO_SHARED_BY_ALL, &ad9088_testmode_enum), + IIO_ENUM("adc_select", IIO_SHARED_BY_ALL, &ad9088_adc_select_enum), + { + .name = "adc_select_available", + .read = ad9088_fft_sniffer_adc_select_available, + .shared = IIO_SHARED_BY_ALL, + }, + { + .name = "max_threshold", + .read = ad9088_fft_sniffer_ext_info_read, + .write = ad9088_fft_sniffer_ext_info_write, + .shared = IIO_SHARED_BY_ALL, + .private = AD9088_FTT_MAX_THRESHOLD, + }, + { + .name = "min_threshold", + .read = ad9088_fft_sniffer_ext_info_read, + .write = ad9088_fft_sniffer_ext_info_write, + .shared = IIO_SHARED_BY_ALL, + .private = AD9088_FTT_MIN_THRESHOLD, + }, + {}, +}; + +static const struct iio_chan_spec ad9088_fft_sniffer_channels[] = { + { + .type = IIO_INDEX, + .info_mask_separate = 0, + .channel = 0, + .scan_index = AD9088_FFT_SNIFFER_SI_INDEX, + .scan_type = { + .sign = 'u', + .realbits = 9, + .storagebits = 16, + .shift = 0, + .endianness = IIO_LE, + }, + }, + { + .type = IIO_VOLTAGE, + .info_mask_separate = 0, + .ext_info = ad9088_fft_sniffer_ext_info, + .indexed = 1, + .modified = 1, + .channel = 0, + .channel2 = IIO_MOD_I, + .scan_index = AD9088_FFT_SNIFFER_I_INDEX, + .scan_type = { + .sign = 's', + .realbits = 9, + .storagebits = 16, + .shift = 0, + .endianness = IIO_LE, + }, + }, + { + .type = IIO_VOLTAGE, + .info_mask_separate = 0, + .ext_info = ad9088_fft_sniffer_ext_info, + .indexed = 1, + .modified = 1, + .channel = 0, + .channel2 = IIO_MOD_Q, + .scan_index = AD9088_FFT_SNIFFER_Q_INDEX, + .scan_type = { + .sign = 's', + .realbits = 9, + .storagebits = 16, + .shift = 0, + .endianness = IIO_LE, + }, + }, + { + .type = IIO_MAGN, + .info_mask_separate = 0, + .ext_info = ad9088_fft_sniffer_ext_info, + .indexed = 1, + .channel = 0, + .scan_index = AD9088_FFT_SNIFFER_MAGN_INDEX, + .scan_type = { + .sign = 'u', + .realbits = 9, + .storagebits = 16, + .shift = 0, + .endianness = IIO_LE, + }, + }, +}; + +static int ad9088_fft_sniffer_debugfs_reg_access(struct iio_dev *indio_dev, + unsigned int reg, unsigned int writeval, + unsigned int *readval) +{ + struct ad9088_fft_sniffer_state *st = iio_priv(indio_dev); + struct ad9088_phy *phy = st->phy; + u8 val; + int ret; + + guard(mutex)(&st->phy->lock); + if (!readval) + return adi_apollo_hal_reg_set(&phy->ad9088, reg, writeval); + + ret = adi_apollo_hal_reg_get(&phy->ad9088, reg, &val); + if (ret < 0) + return ret; + + *readval = val; + + return 0; +} + +static int ad9088_fft_sniffer_update_scan_mode(struct iio_dev *indio_dev, + const unsigned long *active_scan_mask) +{ + struct ad9088_fft_sniffer_state *st = iio_priv(indio_dev); + + guard(mutex)(&st->phy->lock); + + memcpy(&st->sniffer_config_hw, &st->sniffer_config, sizeof(st->sniffer_config_hw)); + + if (active_scan_mask[0] & BIT(AD9088_FFT_SNIFFER_MAGN_INDEX)) { + st->sniffer_config_hw.pgm.sniffer_mode = st->mode ? + ADI_APOLLO_SNIFFER_INSTANT_MAGNITUDE : + ADI_APOLLO_SNIFFER_NORMAL_MAGNITUDE; + } else { + st->sniffer_config_hw.pgm.sniffer_mode = st->mode ? + ADI_APOLLO_SNIFFER_INSTANT_IQ : + ADI_APOLLO_SNIFFER_NORMAL_IQ; + st->sniffer_config_hw.init.real_mode = 0; + st->sniffer_config_hw.pgm.sort_enable = 0; + st->sniffer_config_hw.pgm.continuous_mode = 0; + st->sniffer_config_hw.pgm.alpha_factor = 0; + } + + dev_dbg(st->dev, "sniffer_mode %d\n", st->sniffer_config_hw.pgm.sniffer_mode); + + return 0; +} + +static const struct iio_info ad9088_fft_sniffer_info = { + .debugfs_reg_access = &ad9088_fft_sniffer_debugfs_reg_access, + .update_scan_mode = ad9088_fft_sniffer_update_scan_mode, +}; + +static int ad9088_fft_sniffer_buffer_postenable(struct iio_dev *indio_dev) +{ + struct ad9088_fft_sniffer_state *st = iio_priv(indio_dev); + int ret = 0; + u32 blen, dlen; + + dev_dbg(st->dev, "%s:%d\n", __func__, __LINE__); + + blen = indio_dev->buffer->length / indio_dev->num_channels; + dlen = st->sniffer_config_hw.init.real_mode ? (ADI_APOLLO_SNIFFER_FFT_LENGTH / 2) : + ADI_APOLLO_SNIFFER_FFT_LENGTH; + + if (blen != dlen) { + dev_err(st->dev, "Buffer length %d incompatible with current sniffer mode (real/complex) set to %d\n", + blen, dlen); + return -EINVAL; + } + + guard(mutex)(&st->phy->lock); + + ret = adi_apollo_sniffer_init(&st->phy->ad9088, st->side_sel, &st->sniffer_config_hw.init); + if (ret != API_CMS_ERROR_OK) { + dev_err(st->dev, "Error in adi_apollo_sniffer_pgm: %d\n", ret); + return ret; + } + /* Program the sniffer */ + ret = adi_apollo_sniffer_pgm(&st->phy->ad9088, st->side_sel, &st->sniffer_config_hw.pgm); + if (ret != API_CMS_ERROR_OK) { + dev_err(st->dev, "Error in adi_apollo_sniffer_pgm: %d\n", ret); + return ret; + } + + reinit_completion(&st->complete); + queue_delayed_work(system_freezable_wq, &st->sync_work, msecs_to_jiffies(st->delay_ms)); + + return 0; +} + +static int ad9088_fft_sniffer_buffer_predisable(struct iio_dev *indio_dev) +{ + struct ad9088_fft_sniffer_state *st = iio_priv(indio_dev); + int ret; + + dev_dbg(st->dev, "%s:%d\n", __func__, __LINE__); + + complete_all(&st->complete); + cancel_delayed_work_sync(&st->sync_work); + + guard(mutex)(&st->phy->lock); + + ret = adi_apollo_sniffer_enable_set(&st->phy->ad9088, st->side_sel, 0); + if (ret != API_CMS_ERROR_OK) + dev_err(st->dev, "Error in adi_apollo_sniffer_pgm: %d\n", ret); + + return ret; +} + +static const struct iio_buffer_setup_ops ad9088_fft_sniffer_buffer_ops = { + .postenable = ad9088_fft_sniffer_buffer_postenable, + .predisable = ad9088_fft_sniffer_buffer_predisable, +}; + +static irqreturn_t ad9088_fft_sniffer_irq_handler(int irq, void *private) +{ + struct iio_dev *indio_dev = private; + struct ad9088_fft_sniffer_state *st = iio_priv(indio_dev); + + complete_all(&st->complete); + + return IRQ_HANDLED; +} + +static void ad9088_rx_sniffer_debugfs_init(struct iio_dev *indio_dev, + adi_apollo_sniffer_param_t *config) +{ + struct ad9088_fft_sniffer_state *st = iio_priv(indio_dev); + struct dentry *d; + + d = iio_get_debugfs_dentry(indio_dev); + if (!d) + return; + + debugfs_create_u8("fft_hold_sel", 0644, d, &config->init.fft_hold_sel); + debugfs_create_u8("fft_enable_sel", 0644, d, &config->init.fft_enable_sel); + debugfs_create_u8("real_mode", 0644, d, &config->init.real_mode); + debugfs_create_u8("max_threshold", 0644, d, &config->init.max_threshold); + debugfs_create_u8("min_threshold", 0644, d, &config->init.min_threshold); + debugfs_create_u8("sort_enable", 0644, d, &config->pgm.sort_enable); + debugfs_create_u8("continuous_mode", 0644, d, &config->pgm.continuous_mode); + debugfs_create_u8("bottom_fft_enable", 0644, d, &config->pgm.bottom_fft_enable); + debugfs_create_u8("window_enable", 0644, d, &config->pgm.window_enable); + debugfs_create_u8("low_power_enable", 0644, d, &config->pgm.low_power_enable); + debugfs_create_u8("dither_enable", 0644, d, &config->pgm.dither_enable); + debugfs_create_u8("alpha_factor", 0644, d, &config->pgm.alpha_factor); + debugfs_create_u16("adc", 0644, d, &config->pgm.adc); + debugfs_create_u8("run_fft_engine_background", 0644, d, + &config->read.run_fft_engine_background); + debugfs_create_u32("delay_capture_ms", 0644, d, &st->delay_ms); + debugfs_create_u64("adc_sampling_rate_Hz", 0444, d, + &st->phy->profile.adc_cfg[st->side_sel - 1].adc_sampling_rate_Hz); +} + +static void ad9088_fft_sniffer_sync_work_func(struct work_struct *work) +{ + struct ad9088_fft_sniffer_state *st = + container_of(work, struct ad9088_fft_sniffer_state, sync_work.work); + adi_apollo_sniffer_fft_data_t *fft_data = &st->fft_data; + bool iq_mode; + int ret, i, j; + + guard(mutex)(&st->phy->lock); + + if (st->irq) { + /* IRQ-based mode: manually trigger and wait for interrupt */ + ret = ad9088_fft_sniffer_request(st); + if (ret != API_CMS_ERROR_OK) { + dev_err(st->dev, "Error requesting FFT data: %d\n", ret); + goto requeue; + } + + mutex_unlock(&st->phy->lock); + wait_for_completion_interruptible(&st->complete); + reinit_completion(&st->complete); + mutex_lock(&st->phy->lock); + + /* Read data after IRQ */ + ad9088_fft_sniffer_data_read(st, &st->sniffer_config_hw); + } else { + /* Polling mode: use complete data_get API */ + ret = adi_apollo_sniffer_data_get(&st->phy->ad9088, st->side_sel, + &st->sniffer_config_hw, fft_data); + if (ret) { + dev_err(st->dev, "Failed to get FFT data (polling): %d\n", ret); + goto requeue; + } + + if (st->sniffer_config_hw.pgm.sniffer_mode > ADI_APOLLO_SNIFFER_INSTANT_MAGNITUDE) + iq_mode = true; + else + iq_mode = false; + + /* Push data to IIO buffer */ + for (i = 0; i < fft_data->valid_data_length; i++) { + j = 0; + + if (st->indio_dev->active_scan_mask[0] & BIT(AD9088_FFT_SNIFFER_SI_INDEX)) + st->buffer[j++] = iq_mode ? i : fft_data->bin_q_data[i]; + + if (st->indio_dev->active_scan_mask[0] & BIT(AD9088_FFT_SNIFFER_I_INDEX)) + st->buffer[j++] = fft_data->mag_i_data[i]; + + if (st->indio_dev->active_scan_mask[0] & BIT(AD9088_FFT_SNIFFER_Q_INDEX)) + st->buffer[j++] = fft_data->bin_q_data[i]; + + if (st->indio_dev->active_scan_mask[0] & BIT(AD9088_FFT_SNIFFER_MAGN_INDEX)) + st->buffer[j++] = fft_data->mag_i_data[i]; + + iio_push_to_buffers(st->indio_dev, st->buffer); + } + } + +requeue: + queue_delayed_work(system_freezable_wq, &st->sync_work, msecs_to_jiffies(st->delay_ms)); +} + +int ad9088_fft_sniffer_probe(struct ad9088_phy *phy, adi_apollo_side_select_e side_sel) +{ + static adi_apollo_gpio_func_e gpio_func; + struct ad9088_fft_sniffer_state *st; + struct device *dev = &phy->spi->dev; + const char *irq_name, *label; + struct iio_dev *indio_dev; + int ret; + u32 pin; + + indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); + if (!indio_dev) + return -ENOMEM; + + st = iio_priv(indio_dev); + st->dev = dev; + st->phy = phy; + st->indio_dev = indio_dev; + st->delay_ms = 100; + st->mode = 1; /* instant */ + st->adc_select = ADI_APOLLO_ADC_0; /* Default to ADC0 */ + + init_completion(&st->complete); + INIT_DELAYED_WORK(&st->sync_work, ad9088_fft_sniffer_sync_work_func); + + indio_dev->info = &ad9088_fft_sniffer_info; + indio_dev->modes = INDIO_DIRECT_MODE; + indio_dev->channels = ad9088_fft_sniffer_channels; + indio_dev->num_channels = ARRAY_SIZE(ad9088_fft_sniffer_channels); + indio_dev->available_scan_masks = ad9088_fft_sniffer_available_scan_masks; + + switch (side_sel) { + case ADI_APOLLO_SIDE_A: + irq_name = "fft_done_A"; + indio_dev->name = "ad9088-fft-sniffer-A"; + label = "fft-sniffer-A"; + gpio_func = ADI_APOLLO_FUNC_FFT_DONE_A; + st->side_sel = ADI_APOLLO_SNIFFER_A; + st->regmap_base = RX_SPECTRUM_SNIFFER_RX_SLICE_0_RX_DIGITAL0; + /* Read GPIO pin from devicetree */ + ret = device_property_read_u32(dev, "adi,gpio-sniffer-a-export", &pin); + if (ret) + pin = 17; /* Default fallback */ + break; + case ADI_APOLLO_SIDE_B: + irq_name = "fft_done_B"; + indio_dev->name = "ad9088-fft-sniffer-B"; + label = "fft-sniffer-B"; + gpio_func = ADI_APOLLO_FUNC_FFT_DONE_B; + st->side_sel = ADI_APOLLO_SNIFFER_B; + st->regmap_base = RX_SPECTRUM_SNIFFER_RX_SLICE_0_RX_DIGITAL1; + /* Read GPIO pin from devicetree */ + ret = device_property_read_u32(dev, "adi,gpio-sniffer-b-export", &pin); + if (ret) + pin = 18; /* Default fallback */ + break; + default: + return dev_err_probe(&phy->spi->dev, -EINVAL, "Invalid side selection\n"); + } + + ret = devm_ad9088_set_child_label(phy, indio_dev, label); + if (ret) + return ret; + + ret = devm_mutex_init(dev, &st->lock); + if (ret) + return ret; + + st->side_sel = side_sel; + st->irq = fwnode_irq_get_byname(dev_fwnode(dev), irq_name); + + if (st->irq == -EPROBE_DEFER) + return -EPROBE_DEFER; + + if (st->irq < 0) { + /* No IRQ available, use polling mode */ + dev_info(dev, "%s: No IRQ found, using polling mode\n", + indio_dev->name); + st->irq = 0; + } + + /* Set up IIO buffer for both IRQ and polling modes */ + ret = devm_iio_kfifo_buffer_setup_ext(st->dev, indio_dev, + &ad9088_fft_sniffer_buffer_ops, + NULL); + if (ret) + return ret; + + /* Only request IRQ and configure GPIO if IRQ is available */ + if (st->irq > 0) { + ret = devm_request_irq(dev, st->irq, + ad9088_fft_sniffer_irq_handler, 0, + indio_dev->name, indio_dev); + if (ret) + return dev_err_probe(st->dev, ret, + "Failed to request irq\n"); + + adi_apollo_gpio_quick_config_mode_set(&phy->ad9088, 0); + adi_apollo_gpio_cmos_func_mode_set(&phy->ad9088, pin, gpio_func); + } + + ad9088_rx_sniffer_populate_default_params(ADI_APOLLO_SNIFFER_INSTANT_MAGNITUDE, + &st->sniffer_config); + + ret = devm_iio_device_register(dev, indio_dev); + if (ret) + return ret; + + ad9088_rx_sniffer_debugfs_init(indio_dev, &st->sniffer_config); + + return 0; +} diff --git a/drivers/iio/trx-rf/ad9088/ad9088_jesd204_fsm.c b/drivers/iio/trx-rf/ad9088/ad9088_jesd204_fsm.c new file mode 100644 index 00000000000000..b16cad5f2097f1 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/ad9088_jesd204_fsm.c @@ -0,0 +1,1075 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * AD9088 JESD204 FSM support + * + * Copyright 2026 Analog Devices Inc. + */ + +#include "ad9088.h" + +#define AD9088_REG_TX_SLICE_0_TX_DIGITAL0 \ + BF_SYNC_INPUT_COUNT_INFO(TXRX_PREFSRC_RECONF_TX_SLICE_0_TX_DIGITAL0) +#define AD9088_REG_TX_SLICE_1_TX_DIGITAL0 \ + BF_SYNC_INPUT_COUNT_INFO(TXRX_PREFSRC_RECONF_TX_SLICE_1_TX_DIGITAL0) +#define AD9088_REG_TX_SLICE_0_TX_DIGITAL1 \ + BF_SYNC_INPUT_COUNT_INFO(TXRX_PREFSRC_RECONF_TX_SLICE_0_TX_DIGITAL1) +#define AD9088_REG_TX_SLICE_1_TX_DIGITAL1 \ + BF_SYNC_INPUT_COUNT_INFO(TXRX_PREFSRC_RECONF_TX_SLICE_1_TX_DIGITAL1) + +static int ad9088_jesd204_link_init(struct jesd204_dev *jdev, + enum jesd204_state_op_reason reason, + struct jesd204_link *lnk) +{ + struct device *dev = jesd204_dev_to_device(jdev); + struct ad9088_jesd204_priv *priv = jesd204_dev_priv(jdev); + struct ad9088_phy *phy = priv->phy; + adi_apollo_jesd_tx_cfg_t *jtx; + adi_apollo_jesd_rx_cfg_t *jrx; + u8 sideIdx, linkIdx; + unsigned long lane_rate_kbps; + int ret; + + switch (reason) { + case JESD204_STATE_OP_REASON_INIT: + break; + default: + return JESD204_STATE_CHANGE_DONE; + } + + dev_dbg(dev, "%s:%d link_num %u reason %s\n", __func__, __LINE__, + lnk->link_id, jesd204_state_op_reason_str(reason)); + + switch (lnk->link_id) { + case DEFRAMER_LINK_A0_TX: + case DEFRAMER_LINK_A1_TX: + case DEFRAMER_LINK_B0_TX: + case DEFRAMER_LINK_B1_TX: + sideIdx = (lnk->link_id - DEFRAMER_LINK_A0_TX) / 2; + linkIdx = (lnk->link_id - DEFRAMER_LINK_A0_TX) % 2; + + jrx = &phy->profile.jrx[sideIdx]; + + lnk->is_transmit = 1; + lnk->num_lanes = jrx->rx_link_cfg[linkIdx].l_minus1 + 1; + lnk->num_converters = jrx->rx_link_cfg[linkIdx].m_minus1 + 1; + lnk->octets_per_frame = jrx->rx_link_cfg[linkIdx].f_minus1 + 1; + lnk->frames_per_multiframe = jrx->rx_link_cfg[linkIdx].k_minus1 + 1; + lnk->num_of_multiblocks_in_emb = jrx->rx_link_cfg[linkIdx].e_minus1 + 1; + lnk->bits_per_sample = jrx->rx_link_cfg[linkIdx].np_minus1 + 1; + lnk->converter_resolution = jrx->rx_link_cfg[linkIdx].n_minus1 + 1; + if (jrx->common_link_cfg.ver == ADI_APOLLO_JESD_204C) + lnk->jesd_version = JESD204_VERSION_C; + else + lnk->jesd_version = JESD204_VERSION_B; + lnk->subclass = jrx->common_link_cfg.subclass; + lnk->scrambling = jrx->rx_link_cfg[linkIdx].scr; + lnk->high_density = jrx->rx_link_cfg[linkIdx].high_dens; + lnk->ctrl_words_per_frame_clk = 0; + lnk->ctrl_bits_per_sample = jrx->rx_link_cfg[linkIdx].cs; + lnk->samples_per_conv_frame = jrx->rx_link_cfg[linkIdx].s_minus1 + 1; + + lnk->sample_rate = phy->profile.dac_cfg[sideIdx].dac_sampling_rate_Hz; + lnk->sample_rate_div = jrx->rx_link_cfg[linkIdx].link_total_ratio; + priv->serdes_jrx_cal_run = false; + break; + case FRAMER_LINK_A0_RX: + case FRAMER_LINK_A1_RX: + case FRAMER_LINK_B0_RX: + case FRAMER_LINK_B1_RX: + + sideIdx = (lnk->link_id - FRAMER_LINK_A0_RX) / 2; + linkIdx = (lnk->link_id - FRAMER_LINK_A0_RX) % 2; + + jtx = &phy->profile.jtx[sideIdx]; + + lnk->is_transmit = 0; + lnk->num_lanes = jtx->tx_link_cfg[linkIdx].l_minus1 + 1; + lnk->num_converters = jtx->tx_link_cfg[linkIdx].m_minus1 + 1; + lnk->octets_per_frame = jtx->tx_link_cfg[linkIdx].f_minus1 + 1; + lnk->frames_per_multiframe = jtx->tx_link_cfg[linkIdx].k_minus1 + 1; + lnk->num_of_multiblocks_in_emb = jtx->tx_link_cfg[linkIdx].e_minus1 + 1; + lnk->bits_per_sample = jtx->tx_link_cfg[linkIdx].np_minus1 + 1; + lnk->converter_resolution = jtx->tx_link_cfg[linkIdx].n_minus1 + 1; + if (jtx->common_link_cfg.ver == ADI_APOLLO_JESD_204C) + lnk->jesd_version = JESD204_VERSION_C; + else + lnk->jesd_version = JESD204_VERSION_B; + lnk->subclass = jtx->common_link_cfg.subclass; + lnk->scrambling = jtx->tx_link_cfg[linkIdx].scr; + lnk->high_density = jtx->tx_link_cfg[linkIdx].high_dens; + lnk->ctrl_words_per_frame_clk = 0; + lnk->ctrl_bits_per_sample = jtx->tx_link_cfg[linkIdx].cs; + lnk->samples_per_conv_frame = jtx->tx_link_cfg[linkIdx].s_minus1 + 1; + + lnk->sample_rate = phy->profile.adc_cfg[sideIdx].adc_sampling_rate_Hz; + lnk->sample_rate_div = jtx->tx_link_cfg[linkIdx].link_total_ratio; + break; + default: + return -EINVAL; + } + + if (lnk->jesd_version == JESD204_VERSION_C) + lnk->jesd_encoder = JESD204_ENCODER_64B66B; + else + lnk->jesd_encoder = JESD204_ENCODER_8B10B; + + ret = jesd204_link_get_rate_khz(lnk, &lane_rate_kbps); + if (ret) + return ret; + + return JESD204_STATE_CHANGE_DONE; +} + +static int ad9088_jesd204_link_setup(struct jesd204_dev *jdev, + enum jesd204_state_op_reason reason) +{ + struct device *dev = jesd204_dev_to_device(jdev); + struct ad9088_jesd204_priv *priv = jesd204_dev_priv(jdev); + struct ad9088_phy *phy = priv->phy; + adi_apollo_device_t *device = &phy->ad9088; + adi_apollo_rxen_pwrup_ctrl_t rxen_config = { + .sm_clk_rate = ADI_APOLLO_PUC_CLK_RATE_FS_DIV_32, + .sm_en = 0, + .spi_rxen = 1, + .spi_rxen_en = 1 + }; + + adi_apollo_txen_pwrup_ctrl_t txen_config = { + .sm_clk_rate = ADI_APOLLO_PUC_CLK_RATE_FS_DIV_32, + .sm_en = 0, + .spi_txen = 1, + .spi_txen_en = 1 + }; + u32 subclass = 0; + int ret; + + dev_dbg(dev, "%s:%d reason %s\n", __func__, __LINE__, jesd204_state_op_reason_str(reason)); + + if (reason != JESD204_STATE_OP_REASON_INIT) + return JESD204_STATE_CHANGE_DONE; + + /* Enable Apollo JTx links */ + ret = adi_apollo_jtx_link_enable_set(device, ADI_APOLLO_LINK_A0 | ADI_APOLLO_LINK_B0, + ADI_APOLLO_ENABLE); + if (ret) { + dev_err(dev, "Error enabling JTx links %d\n", ret); + return ret; + } + ret = adi_apollo_jtx_link_enable_set(device, ADI_APOLLO_LINK_A1 | ADI_APOLLO_LINK_B1, + ADI_APOLLO_DISABLE); + if (ret) { + dev_err(dev, "Error enabling JTx links %d\n", ret); + return ret; + } + + /* Enable Apollo JRx links */ + ret = adi_apollo_jrx_link_enable_set(device, ADI_APOLLO_LINK_A0 | ADI_APOLLO_LINK_B0, + ADI_APOLLO_ENABLE); + if (ret) { + dev_err(dev, "Error enabling JRx links %d\n", ret); + return ret; + } + ret = adi_apollo_jrx_link_enable_set(device, ADI_APOLLO_LINK_A1 | ADI_APOLLO_LINK_B1, + ADI_APOLLO_DISABLE); + if (ret) { + dev_err(dev, "Error enabling JRx links %d\n", ret); + return ret; + } + + /* Enable Rx blocks - enable/disable via spi */ + ret = adi_apollo_rxen_pwrup_ctrl_set(device, ADI_APOLLO_RXEN_ADC_ALL, &rxen_config); + if (ret) { + dev_err(dev, "Error activating Rx blocks (%d)\n", ret); + return ret; + } + + /* Enable Tx blocks - enable/disable via spi */ + ret = adi_apollo_txen_pwrup_ctrl_set(device, ADI_APOLLO_TXEN_DAC_ALL, &txen_config); + if (ret) { + dev_err(dev, "Error activating Tx blocks(%d)\n", ret); + return ret; + } + + /* Datapath reset */ + adi_apollo_rxmisc_dp_reset(device, ADI_APOLLO_SIDE_ALL, 1); + adi_apollo_txmisc_dp_reset(device, ADI_APOLLO_SIDE_ALL, 1); + adi_apollo_rxmisc_dp_reset(device, ADI_APOLLO_SIDE_ALL, 0); + adi_apollo_txmisc_dp_reset(device, ADI_APOLLO_SIDE_ALL, 0); + + if (phy->profile.jtx->common_link_cfg.subclass || + phy->profile.jrx->common_link_cfg.subclass) + subclass = 1; + + ret = adi_apollo_clk_mcs_subclass_set(&phy->ad9088, subclass); + if (ret) { + dev_err(dev, "Error setting subclass %d\n", ret); + return ret; + } + + /* Enable the MCS SYSREF receiver if subclass 1 */ + ret = adi_apollo_clk_mcs_sysref_en_set(&phy->ad9088, (subclass == 1) ? + ADI_APOLLO_ENABLE : ADI_APOLLO_DISABLE); + if (ret) { + dev_err(dev, "Error setting MCS SYSREF receiver %d\n", ret); + return ret; + } + + ret = adi_apollo_adc_bgcal_freeze(device, device->dev_info.is_8t8r ? + ADI_APOLLO_ADC_ALL : ADI_APOLLO_ADC_ALL_4T4R); + if (ret) { + dev_err(dev, "Error in adi_apollo_adc_bgcal_freeze %d\n", ret); + return ret; + } + + ret = adi_apollo_clk_mcs_dyn_sync_sequence_run(device); + if (ret) { + dev_err(dev, "Error in adi_apollo_clk_mcs_dyn_sync_sequence_run %d\n", ret); + return ret; + } + ret = adi_apollo_clk_mcs_dyn_sync_rxtxlinks_sequence_run(device); + if (ret) { + dev_err(dev, "Error in adi_apollo_clk_mcs_dyn_sync_rxtxlinks_sequence_run %d\n", + ret); + return ret; + } + + return JESD204_STATE_CHANGE_DONE; +} + +static int ad9088_jesd204_setup_stage1(struct jesd204_dev *jdev, + enum jesd204_state_op_reason reason) +{ + struct device *dev = jesd204_dev_to_device(jdev); + struct ad9088_jesd204_priv *priv = jesd204_dev_priv(jdev); + struct ad9088_phy *phy = priv->phy; + adi_apollo_device_t *device = &phy->ad9088; + u32 adc_cal_chans = device->dev_info.is_8t8r ? ADI_APOLLO_ADC_ALL : ADI_APOLLO_ADC_ALL_4T4R; + u32 n_adc = device->dev_info.is_8t8r ? ADI_APOLLO_ADC_ALL : ADI_APOLLO_ADC_ALL_4T4R; + adi_apollo_sysclock_cond_cfg_e cc_cal_cfg; + adi_apollo_init_cal_cfg_e init_cal_cfg; + u16 jrx_phase_adjust; + u8 is_adc_nvm_fused; + int ret; + + if (reason != JESD204_STATE_OP_REASON_INIT) + return JESD204_STATE_CHANGE_DONE; + + phy->rx_en_mask = ADI_APOLLO_RXEN_ADC_ALL; + phy->tx_en_mask = ADI_APOLLO_TXEN_DAC_ALL; + + ret = adi_apollo_adc_nyquist_zone_set(device, n_adc, phy->rx_nyquist_zone); + if (ret) { + dev_err(dev, "Error setting ADC Nyquist zone %d\n", ret); + return ret; + } + + if (phy->cal_data_loaded_from_fw) { + cc_cal_cfg = ADI_APOLLO_SYSCLKCONDITIONING_ENABLED_WARMBOOT_FROM_USER; + dev_info(dev, "Run clock conditioning cal WARMBOOT from USER ...\n"); + } else { + cc_cal_cfg = ADI_APOLLO_SYSCLKCONDITIONING_ENABLED; + dev_info(dev, "Run clock conditioning cal (can take up to %d secs)...\n", + ADI_APOLLO_SYSCLK_COND_CENTER_MAX_TO); + } + + ret = adi_apollo_cfg_clk_cond_cal_cfg_set(device, cc_cal_cfg); + if (ret) { + dev_err(dev, "Error in adi_apollo_cfg_clk_cond_cal_cfg_set %d\n", ret); + return ret; + } + + ret = adi_apollo_sysclk_cond_cal(device); + ret = ad9088_check_apollo_error(dev, ret, "adi_apollo_sysclk_cond_cal"); + if (ret) + return ret; + + /* Inspect the Apollo JRx and JTx link config */ + ret = ad9088_inspect_jrx_link_all(phy); + if (ret) { + dev_err(dev, "Error in ad9088_inspect_jrx_link_all %d\n", ret); + return ret; + } + ret = ad9088_inspect_jtx_link_all(phy); + if (ret) { + dev_err(dev, "Error in ad9088_inspect_jtx_link_all %d\n", ret); + return ret; + } + + ret = adi_apollo_jrx_phase_adjust_calc(device, ADI_APOLLO_LINK_A0 | ADI_APOLLO_LINK_B0, + ADI_APOLLO_JRX_PHASE_ADJ_MARGIN_DEFAULT, + &jrx_phase_adjust); + if (ret) { + dev_err(dev, "Error in adi_apollo_jrx_phase_adjust_calc %d\n", ret); + return ret; + } + + dev_dbg(dev, "JRX Phase Adjust: %d\n", jrx_phase_adjust); + + /* Set the jrx phase adjust */ + ret = adi_apollo_jrx_phase_adjust_set(device, ADI_APOLLO_LINK_A0 | ADI_APOLLO_LINK_B0, + jrx_phase_adjust); + if (ret) { + dev_err(dev, "Error in adi_apollo_jrx_phase_adjust_set %d\n", ret); + return ret; + } + + /* Set the jtx phase adjust */ + ret = adi_apollo_jtx_phase_adjust_set(device, ADI_APOLLO_LINK_A0 | ADI_APOLLO_LINK_B0, 0); + if (ret) { + dev_err(dev, "Error in adi_apollo_jtx_phase_adjust_set %d\n", ret); + return ret; + } + + /* ADC calibration */ + if (!phy->cal_data_loaded_from_fw) { + ret = adi_apollo_hal_bf_get(device, BF_ADC_NVM_CALDATA_FUSED_INFO, + &is_adc_nvm_fused, 1); + if (ret != API_CMS_ERROR_OK) { + dev_err(dev, "Error reading ADC NVM fused info %d\n", ret); + return ret; + } + + if (is_adc_nvm_fused) + init_cal_cfg = ADI_APOLLO_INIT_CAL_ENABLED_WARMBOOT_FROM_NVM; + else + init_cal_cfg = ADI_APOLLO_INIT_CAL_ENABLED; + + dev_info(dev, "Run ADC cal from %s (can take up to 100 secs)...\n", + is_adc_nvm_fused ? "NVM" : "scratch"); + } else { + dev_info(dev, "Run ADC CAL WARMBOOT from USER\n"); + init_cal_cfg = ADI_APOLLO_INIT_CAL_DISABLED_WARMBOOT_FROM_USER; + } + + ret = adi_apollo_adc_init_cal_start(device, adc_cal_chans, init_cal_cfg); + ret = ad9088_check_apollo_error(dev, ret, "adi_apollo_adc_init_cal_start"); + if (ret) + return ret; + + return JESD204_STATE_CHANGE_DONE; +} + +static int ad9088_jesd204_setup_stage2(struct jesd204_dev *jdev, + enum jesd204_state_op_reason reason) +{ + struct device *dev = jesd204_dev_to_device(jdev); + struct ad9088_jesd204_priv *priv = jesd204_dev_priv(jdev); + struct ad9088_phy *phy = priv->phy; + adi_apollo_device_t *device = &phy->ad9088; + int ret; + + if (reason != JESD204_STATE_OP_REASON_INIT) + return JESD204_STATE_CHANGE_DONE; + + ret = adi_apollo_adc_init_cal_complete(device, device->dev_info.is_8t8r ? + ADI_APOLLO_ADC_ALL : ADI_APOLLO_ADC_ALL_4T4R); + ret = ad9088_check_apollo_error(dev, ret, "adi_apollo_adc_init_cal_complete"); + if (ret) + return ret; + + ret = adi_apollo_adc_nyquist_zone_set(device, device->dev_info.is_8t8r ? + ADI_APOLLO_ADC_ALL : ADI_APOLLO_ADC_ALL_4T4R, + phy->rx_nyquist_zone); + if (ret) { + dev_err(dev, "Error setting ADC Nyquist zone %d\n", ret); + return ret; + } + + ret = adi_apollo_clk_mcs_dyn_sync_rxtxlinks_sequence_run(device); + if (ret) { + dev_err(dev, "Error in adi_apollo_clk_mcs_dyn_sync_rxtxlinks_sequence_run %d\n", + ret); + return ret; + } + + if (phy->cddc_sample_delay_en) { + ret = adi_apollo_bmem_cddc_delay_start(device, ADI_APOLLO_BMEM_ALL); + ret = ad9088_check_apollo_error(&phy->spi->dev, ret, + "adi_apollo_bmem_cddc_delay_start"); + if (ret) + return ret; + } + + if (phy->fddc_sample_delay_en) { + ret = adi_apollo_bmem_fddc_delay_start(device, ADI_APOLLO_BMEM_ALL); + ret = ad9088_check_apollo_error(&phy->spi->dev, ret, + "adi_apollo_bmem_fddc_delay_start"); + if (ret) + return ret; + } + + return JESD204_STATE_CHANGE_DONE; +} + +static int ad9088_jesd204_clks_enable(struct jesd204_dev *jdev, + enum jesd204_state_op_reason reason, + struct jesd204_link *lnk) +{ + struct device *dev = jesd204_dev_to_device(jdev); + struct ad9088_jesd204_priv *priv = jesd204_dev_priv(jdev); + struct ad9088_phy *phy = priv->phy; + int ret; + + u16 serdes; + + switch (lnk->link_id) { + case DEFRAMER_LINK_A0_TX: + case DEFRAMER_LINK_A1_TX: + serdes = ADI_APOLLO_TXRX_SERDES_12PACK_A; + break; + case DEFRAMER_LINK_B0_TX: + case DEFRAMER_LINK_B1_TX: + serdes = ADI_APOLLO_TXRX_SERDES_12PACK_B; + break; + default: + serdes = ADI_APOLLO_TXRX_SERDES_12PACK_NONE | ADI_APOLLO_TXRX_SERDES_12PACK_NONE; + break; + } + + dev_dbg(dev, "%s:%d link_num %u reason %s\n", __func__, __LINE__, + lnk->link_id, jesd204_state_op_reason_str(reason)); + + if (lnk->is_transmit && reason == JESD204_STATE_OP_REASON_UNINIT && + phy->profile.jrx[0].common_link_cfg.lane_rate_kHz > 16000000) { + ret = adi_apollo_serdes_jrx_bgcal_freeze(&phy->ad9088, serdes); + ret = ad9088_check_apollo_error(dev, ret, "adi_apollo_serdes_jrx_bgcal_freeze"); + if (ret) + return ret; + + dev_dbg(dev, "%s: SERDES JRx bg cal freeze\n", + ad9088_fsm_links_to_str[lnk->link_id]); + } + + if (lnk->is_transmit && reason == JESD204_STATE_OP_REASON_INIT && + phy->profile.jrx[0].common_link_cfg.lane_rate_kHz > 8000000) { + adi_apollo_init_cal_cfg_e init_cal; + + dev_info(dev, "%s: SERDES JRx cal Rate %u kBps via %s ...\n", + ad9088_fsm_links_to_str[lnk->link_id], + phy->profile.jrx[0].common_link_cfg.lane_rate_kHz, + phy->cal_data_loaded_from_fw ? "WARMBOOT_FROM_USER" : "INIT_CAL"); + + if (phy->cal_data_loaded_from_fw) + init_cal = ADI_APOLLO_INIT_CAL_DISABLED_WARMBOOT_FROM_USER; + else + init_cal = ADI_APOLLO_INIT_CAL_ENABLED; + + ret = adi_apollo_serdes_jrx_init_cal(&phy->ad9088, serdes, init_cal); + ret = ad9088_check_apollo_error(dev, ret, "adi_apollo_serdes_jrx_init_cal"); + if (ret) + return ret; + + if (phy->profile.jrx[0].common_link_cfg.lane_rate_kHz > 16000000) { + ret = adi_apollo_serdes_jrx_bgcal_unfreeze(&phy->ad9088, serdes); + ret = ad9088_check_apollo_error(dev, ret, + "adi_apollo_serdes_jrx_bgcal_unfreeze"); + if (ret) + return ret; + + dev_dbg(dev, "%s: SERDES JRx bg cal unfreeze\n", + ad9088_fsm_links_to_str[lnk->link_id]); + } + } + + if (!lnk->is_transmit) { + ret = adi_apollo_jtx_link_enable_set(&phy->ad9088, ad9088_to_link(lnk->link_id), + reason == JESD204_STATE_OP_REASON_INIT); + ret = ad9088_check_apollo_error(dev, ret, "adi_apollo_jtx_link_enable_set"); + if (ret) + return ret; + } + + return JESD204_STATE_CHANGE_DONE; +} + +static int ad9088_jesd204_link_enable(struct jesd204_dev *jdev, + enum jesd204_state_op_reason reason, + struct jesd204_link *lnk) +{ + struct device *dev = jesd204_dev_to_device(jdev); + struct ad9088_jesd204_priv *priv = jesd204_dev_priv(jdev); + struct ad9088_phy *phy = priv->phy; + int ret; + + dev_dbg(dev, "%s:%d link_num %u reason %s\n", __func__, __LINE__, lnk->link_id, + jesd204_state_op_reason_str(reason)); + + if (lnk->is_transmit) { + /* txfe TX (JRX) link */ + ret = adi_apollo_jrx_link_enable_set(&phy->ad9088, + ad9088_to_link(lnk->link_id), + reason == JESD204_STATE_OP_REASON_INIT); + ret = ad9088_check_apollo_error(dev, ret, "adi_apollo_jrx_link_enable_set"); + if (ret) + return ret; + } + + return JESD204_STATE_CHANGE_DONE; +} + +static int ad9088_jesd204_link_running(struct jesd204_dev *jdev, + enum jesd204_state_op_reason reason, + struct jesd204_link *lnk) +{ + struct device *dev = jesd204_dev_to_device(jdev); + struct ad9088_jesd204_priv *priv = jesd204_dev_priv(jdev); + struct ad9088_phy *phy = priv->phy; + int ret; + + dev_dbg(dev, "%s:%d link_num %u reason %s\n", __func__, __LINE__, + lnk->link_id, jesd204_state_op_reason_str(reason)); + + if (reason != JESD204_STATE_OP_REASON_INIT) { + phy->is_initialized = false; + + return JESD204_STATE_CHANGE_DONE; + } + + if (lnk->is_transmit) { + ad9088_print_link_phase(phy, lnk); + ret = ad9088_jesd_rx_link_status_print(phy, lnk, 3); + if (ret < 0) + return JESD204_STATE_CHANGE_ERROR; + } else { + ret = ad9088_jesd_tx_link_status_print(phy, lnk, 3); + if (ret < 0) + return JESD204_STATE_CHANGE_ERROR; + } + + return JESD204_STATE_CHANGE_DONE; +} + +static int ad9088_jesd204_post_setup_stage1(struct jesd204_dev *jdev, + enum jesd204_state_op_reason reason) +{ + struct device *dev = jesd204_dev_to_device(jdev); + struct ad9088_jesd204_priv *priv = jesd204_dev_priv(jdev); + struct ad9088_phy *phy = priv->phy; + adi_apollo_mcs_cal_init_status_t init_cal_status = {{0}}; + adi_apollo_device_t *device = &phy->ad9088; + s64 apollo_delta_t0 = 0; + s64 apollo_delta_t1 = 0; + s64 adf4030_delta_t0 = 0; + s64 adf4030_delta_t1 = 0; + s64 calc_delay = 0; + u64 bsync_out_period_fs; + u64 path_delay, round_trip_delay = 0; + s64 adf4030_phase; + int val, val2; + int ret, ret2; + + dev_dbg(dev, "%s:%d reason %s\n", __func__, __LINE__, jesd204_state_op_reason_str(reason)); + + if (!phy->iio_adf4030 || !phy->iio_adf4382) { + dev_info(dev, "Skipping MCS calibration\n"); + return JESD204_STATE_CHANGE_DONE; + } + + if (reason != JESD204_STATE_OP_REASON_INIT) { + adi_apollo_mcs_cal_bg_tracking_abort(device); + adi_apollo_mcs_cal_tracking_enable(device, 0); + return JESD204_STATE_CHANGE_DONE; + } + + ret = iio_read_channel_attribute(phy->iio_adf4030, &val, &val2, IIO_CHAN_INFO_FREQUENCY); + if (ret < 0) { + dev_err(dev, "Failed to read adf4030 frequency\n"); + return ret; + } + + bsync_out_period_fs = div_u64(1000000000000000ULL, val); + + dev_dbg(dev, "bsync_out_period_fs %lld\n", bsync_out_period_fs); + + ret = ad9088_iio_write_channel_ext_info(phy, phy->iio_adf4030, "output_enable", 1); + if (ret < 0) { + dev_err(dev, "Failed to enable adf4030 output\n"); + return ret; + } + ret = iio_write_channel_attribute(phy->iio_adf4030, 0, 0, IIO_CHAN_INFO_PHASE); + if (ret < 0) { + dev_err(dev, "Failed to set adf4030 phase\n"); + return ret; + } + + ret = ad9088_mcs_init_cal_setup(phy); + if (ret) { + dev_err(dev, "Failed to setup MCS init cal\n"); + return ret; + } + + ret = ad9088_delta_t_measurement_set(phy, 0); + if (ret) { + dev_err(dev, "Failed to set delta_t measurement 0\n"); + return ret; + } + ret = ad9088_delta_t_measurement_get(phy, 0, &apollo_delta_t0); + if (ret) { + dev_err(dev, "Failed to get delta_t measurement\n"); + return ret; + } + dev_dbg(dev, "apollo_delta_t0 %lld fs\n", apollo_delta_t0); + ret = iio_read_channel_attribute(phy->iio_adf4030, &val, &val2, IIO_CHAN_INFO_PHASE); + if (ret < 0) { + dev_err(dev, "Failed to read adf4030 phase\n"); + return ret; + } + adf4030_delta_t0 = (s64)((((u64)val2) << 32) | (u32)val); + dev_dbg(dev, "adf4030_delta_t0 %lld fs\n", adf4030_delta_t0); + + ret = ad9088_iio_write_channel_ext_info(phy, phy->iio_adf4030, "output_enable", 0); + if (ret < 0) { + dev_err(dev, "Failed to disable adf4030 output\n"); + return ret; + } + ret = ad9088_delta_t_measurement_set(phy, 1); + if (ret) { + dev_err(dev, "Failed to set delta_t measurement 1\n"); + + ret2 = ad9088_delta_t_measurement_set(phy, 2); + if (ret2) { + dev_err(dev, "Failed to set delta_t measurement 2\n"); + return ret2; + } + + ad9088_iio_write_channel_ext_info(phy, phy->iio_adf4030, "output_enable", 1); + + return ret; + } + ret = ad9088_delta_t_measurement_get(phy, 1, &apollo_delta_t1); + if (ret) { + dev_err(dev, "Failed to get delta_t measurement\n"); + + ret2 = ad9088_delta_t_measurement_set(phy, 2); + if (ret2) { + dev_err(dev, "Failed to set delta_t measurement 2\n"); + return ret2; + } + + ad9088_iio_write_channel_ext_info(phy, phy->iio_adf4030, "output_enable", 1); + + return ret; + } + dev_dbg(dev, "apollo_delta_t1 %lld fs\n", apollo_delta_t1); + + ret = iio_read_channel_attribute(phy->iio_adf4030, &val, &val2, IIO_CHAN_INFO_PHASE); + if (ret < 0) { + dev_err(dev, "Failed to read adf4030 phase\n"); + + ret2 = ad9088_delta_t_measurement_set(phy, 2); + if (ret2) { + dev_err(dev, "Failed to set delta_t measurement 2\n"); + return ret2; + } + + ad9088_iio_write_channel_ext_info(phy, phy->iio_adf4030, "output_enable", 1); + + return ret; + } + adf4030_delta_t1 = (s64)((((u64)val2) << 32) | (u32)val); + dev_dbg(dev, "adf4030_delta_t1 %lld fs\n", adf4030_delta_t1); + + ret = ad9088_delta_t_measurement_set(phy, 2); + if (ret) { + dev_err(dev, "Failed to set delta_t measurement 2\n"); + return ret; + } + + calc_delay = (adf4030_delta_t0 - adf4030_delta_t1) - (apollo_delta_t1 - apollo_delta_t0); + dev_dbg(dev, "calc_delay %lld fs\n", calc_delay); + div64_u64_rem(calc_delay + bsync_out_period_fs, bsync_out_period_fs, &round_trip_delay); + dev_dbg(dev, "round_trip_delay %lld fs\n", round_trip_delay); + path_delay = round_trip_delay >> 1; + + dev_info(dev, "Total BSYNC path delay %lld fs\n", path_delay); + + ret = ad9088_iio_write_channel_ext_info(phy, phy->iio_adf4030, "output_enable", 1); + if (ret < 0) { + dev_err(dev, "Failed to enable adf4030 output\n"); + return ret; + } + + val = lower_32_bits(-1 * path_delay); + val2 = upper_32_bits(-1 * path_delay); + + ret = iio_write_channel_attribute(phy->iio_adf4030, val, val2, IIO_CHAN_INFO_PHASE); + if (ret < 0) { + dev_err(dev, "Failed to set adf4030 phase\n"); + return ret; + } + + if (__is_defined(DEBUG)) { + ret = iio_read_channel_attribute(phy->iio_adf4030, &val, &val2, + IIO_CHAN_INFO_PHASE); + if (ret < 0) { + dev_err(dev, "Failed to read adf4030 phase\n"); + return ret; + } + adf4030_phase = (s64)((((u64)val2) << 32) | (u32)val); + dev_info(dev, "adf4030_phase %lld fs\n", adf4030_phase); + } + + ret = adi_apollo_mcs_cal_init_run(device); + ret = ad9088_check_apollo_error(dev, ret, "adi_apollo_mcs_cal_init_run"); + if (ret) + return ret; + + ret = adi_apollo_mcs_cal_init_status_get(device, &init_cal_status); + ret = ad9088_check_apollo_error(dev, ret, "adi_apollo_mcs_cal_init_status_get"); + if (ret) + return ret; + + ret = ad9088_mcs_init_cal_validate(phy, &init_cal_status); + if (ret) { + dev_err(dev, "MCS Initcal Status: Failed\n"); + return ret; + } + + dev_info(dev, "MCS Initcal Status: Passed\n"); + + /* + * MCS Tracking Calibration is only supported in single clock mode. + * Per UG-2300: "MCS Tracking Calibration restricted to Single Clock + * scheme due to HW limitation." + */ + if (device->dev_info.is_dual_clk) { + dev_info(dev, "Dual clock mode: skipping MCS tracking calibration (HW limitation)\n"); + } else { + ret = ad9088_mcs_tracking_cal_setup(phy, phy->mcs_track_decimation, 1); + if (ret) { + dev_err(dev, "Failed to setup MCS tracking cal\n"); + return ret; + } + + ret = ad9088_iio_write_channel_ext_info(phy, phy->iio_adf4382, "en_auto_align", 1); + if (ret < 0) { + dev_err(dev, "Failed to enable adf4382 auto align\n"); + return ret; + } + + ret = iio_write_channel_attribute(phy->iio_adf4382, 125, 0, IIO_CHAN_INFO_PHASE); + if (ret < 0) { + dev_err(dev, "Failed to set adf4382 phase\n"); + return ret; + } + + ret = adi_apollo_mcs_cal_fg_tracking_run(device); + ret = ad9088_check_apollo_error(dev, ret, "adi_apollo_mcs_cal_fg_tracking_run"); + if (ret) + return ret; + + ret = adi_apollo_mcs_cal_bg_tracking_run(device); + ret = ad9088_check_apollo_error(dev, ret, "adi_apollo_mcs_cal_bg_tracking_run"); + if (ret) + return ret; + + phy->mcs_cal_bg_tracking_run = true; + } + + if (__is_defined(DEBUG)) { + ret = adi_apollo_mcs_cal_init_status_get(device, &init_cal_status); + ret = ad9088_check_apollo_error(dev, ret, "adi_apollo_mcs_cal_init_status_get"); + if (ret) + return ret; + ret = ad9088_mcs_init_cal_status_print(phy, phy->dbuf, &init_cal_status); + if (ret <= 0) { + dev_err(dev, "Failed to print MCS init cal status\n"); + return ret; + } + + dev_info(dev, "MCS Initcal Status: %s\n", phy->dbuf); + } + + return JESD204_STATE_CHANGE_DONE; +} + +static int ad9088_jesd204_post_setup_stage2(struct jesd204_dev *jdev, + enum jesd204_state_op_reason reason) +{ + struct device *dev = jesd204_dev_to_device(jdev); + struct ad9088_jesd204_priv *priv = jesd204_dev_priv(jdev); + struct ad9088_phy *phy = priv->phy; + adi_apollo_device_t *device = &phy->ad9088; + int ret; + + dev_dbg(dev, "%s:%d reason %s\n", __func__, __LINE__, jesd204_state_op_reason_str(reason)); + + if (reason != JESD204_STATE_OP_REASON_INIT) { + adi_apollo_clk_mcs_trig_sync_enable(device, 0); + adi_apollo_clk_mcs_trig_reset_disable(device); + + if (!IS_ERR_OR_NULL(phy->iio_adf4030) && jesd204_dev_is_top(jdev) && + phy->aion_background_serial_alignment_en) { + ret = ad9088_iio_write_channel_ext_info(phy, phy->iio_adf4030, + "background_serial_alignment_en", + 0); + if (ret < 0) + dev_err(dev, "Failed to disable adf4030 background_serial_alignment_en\n"); + } + + return JESD204_STATE_CHANGE_DONE; + } + + if (!IS_ERR_OR_NULL(phy->iio_adf4030) && jesd204_dev_is_top(jdev) && + phy->aion_background_serial_alignment_en) { + ret = ad9088_iio_write_channel_ext_info(phy, phy->iio_adf4030, + "background_serial_alignment_en", 1); + if (ret < 0) { + dev_err(dev, "Failed to enable adf4030 background_serial_alignment_en\n"); + return ret; + } + } + + if (phy->trig_sync_en) { + /* Use Trigger pin A0 to sync Rx and Tx */ + ret = adi_apollo_clk_mcs_sync_trig_map(device, ADI_APOLLO_RX_TX_ALL, + ADI_APOLLO_TRIG_PIN_A0); + if (ret) { + dev_err(dev, "Error in adi_apollo_clk_mcs_sync_trig_map %d\n", ret); + return ret; + } + + /* + * Resync the Rx and Tx dig only during trig sync + */ + ret = adi_apollo_clk_mcs_trig_sync_enable(device, 0); + if (ret) { + dev_err(dev, "Error in adi_apollo_clk_mcs_trig_sync_enable %d\n", ret); + return ret; + } + ret = adi_apollo_clk_mcs_trig_reset_disable(device); + if (ret) { + dev_err(dev, "Error in adi_apollo_clk_mcs_trig_reset_disable %d\n", ret); + return ret; + } + + /* + * Set trig_syn to 1. Apollo will wait for a trigger from the FPGA. When + * received, the FSRC will be reset. + * + * trig_sync is not self-clearing + */ + ret = adi_apollo_clk_mcs_trig_sync_enable(device, 0); + if (ret) { + dev_err(dev, "Error in adi_apollo_clk_mcs_trig_sync_enable %d\n", ret); + return ret; + } + ret = adi_apollo_clk_mcs_trig_reset_dsp_enable(device); + if (ret) { + dev_err(dev, "Error in adi_apollo_clk_mcs_trig_reset_dsp_enable %d\n", ret); + return ret; + } + ret = adi_apollo_clk_mcs_trig_sync_enable(device, 1); + if (ret) { + dev_err(dev, "Error in adi_apollo_clk_mcs_trig_sync_enable %d\n", ret); + return ret; + } + } + + return JESD204_STATE_CHANGE_DONE; +} + +static int ad9088_jesd204_post_setup_stage3(struct jesd204_dev *jdev, + enum jesd204_state_op_reason reason) +{ + struct device *dev = jesd204_dev_to_device(jdev); + struct ad9088_jesd204_priv *priv = jesd204_dev_priv(jdev); + struct ad9088_phy *phy = priv->phy; + + if (reason != JESD204_STATE_OP_REASON_INIT) + return JESD204_STATE_CHANGE_DONE; + + dev_dbg(dev, "%s:%d reason %s\n", __func__, __LINE__, jesd204_state_op_reason_str(reason)); + + if (phy->triq_req_gpio && phy->trig_sync_en) { + gpiod_set_value(phy->triq_req_gpio, 1); + udelay(1); + gpiod_set_value(phy->triq_req_gpio, 0); + } + + return JESD204_STATE_CHANGE_DONE; +} + +static int ad9088_jesd204_post_setup_stage4(struct jesd204_dev *jdev, + enum jesd204_state_op_reason reason) +{ + struct device *dev = jesd204_dev_to_device(jdev); + struct ad9088_jesd204_priv *priv = jesd204_dev_priv(jdev); + struct ad9088_phy *phy = priv->phy; + adi_apollo_device_t *device = &phy->ad9088; + u32 period_fs, temp; + int ret; + + if (reason != JESD204_STATE_OP_REASON_INIT) { + phy->is_initialized = false; + return JESD204_STATE_CHANGE_DONE; + } + + dev_dbg(dev, "%s:%d reason %s\n", __func__, __LINE__, jesd204_state_op_reason_str(reason)); + + if (phy->trig_sync_en) { + u16 phase, phase1; + /* + * Wait for the trigger sync to finish. + */ + ret = adi_apollo_hal_bf_wait_to_set(device, + BF_TRIGGER_SYNC_DONE_A0_INFO(MCS_SYNC_MCSTOP0), + 1000000, 100); + if (ret) { + dev_err(dev, "Error in adi_apollo_hal_bf_wait_to_set %d\n", ret); + return ret; + } + ret = adi_apollo_clk_mcs_trig_phase_get(&phy->ad9088, ADI_APOLLO_TRIG_PIN_A0, + &phase, &phase1); + if (ret) { + dev_err(dev, "Error in adi_apollo_clk_mcs_trig_phase_get %d\n", ret); + return ret; + } + + if (phy->profile.clk_cfg.clocking_mode == ADI_APOLLO_CLOCKING_MODE_SDR_DIV_8) + temp = 8; + else + temp = 4; + + period_fs = div64_u64(1000000000000000ULL * temp, + phy->profile.clk_cfg.dev_clk_freq_Hz); + + dev_info(dev, "Trigger Phase %d (ideal %u) period %u fs\n", phase, + phy->profile.mcs_cfg.internal_sysref_prd_digclk_cycles_center / 2, + period_fs); + + /* + * Validate trigger phase is within safe margin. Per UG-2300: + * "The user is recommended to maintain the trigger phase close to + * internal_sysref_prd_digclk_cycles/2. If the trigger is too close + * to the rising edge of the internal SYSREF, the jitter on the + * trigger path may cause the latency varying +/-1 internal SYSREF + * clock cycle." + * + * Use 25%-75% of period as safe range (centered around ideal 50%). + */ + { + u16 period = phy->profile.mcs_cfg.internal_sysref_prd_digclk_cycles_center; + u16 margin_low = period / 4; + u16 margin_high = (period * 3) / 4; + + if (phase < margin_low || phase > margin_high) + dev_warn(dev, + "Trigger phase %u outside safe margin [%u, %u]. Risk of +/-1 SYSREF cycle latency jitter.\n", + phase, margin_low, margin_high); + } + + ret = adi_apollo_clk_mcs_trig_sync_enable(device, 0); + if (ret) { + dev_err(dev, "Error in adi_apollo_clk_mcs_trig_sync_enable %d\n", ret); + return ret; + } + ret = adi_apollo_clk_mcs_trig_reset_disable(device); + if (ret) { + dev_err(dev, "Error in adi_apollo_clk_mcs_trig_reset_disable %d\n", ret); + return ret; + } + + if (__is_defined(DEBUG)) { + /* + * Read the trigger sync count. It will increment by two each time the FPGA + * sysref sequencer is executed. + */ + u8 sync_input_count[4]; + + adi_apollo_hal_bf_get(device, AD9088_REG_TX_SLICE_0_TX_DIGITAL0, + &sync_input_count[0], 1); + adi_apollo_hal_bf_get(device, AD9088_REG_TX_SLICE_1_TX_DIGITAL0, + &sync_input_count[1], 1); + adi_apollo_hal_bf_get(device, AD9088_REG_TX_SLICE_0_TX_DIGITAL1, + &sync_input_count[2], 1); + adi_apollo_hal_bf_get(device, AD9088_REG_TX_SLICE_1_TX_DIGITAL1, + &sync_input_count[3], 1); + + dev_info(&phy->spi->dev, "sync_input_count=%d %d %d %d PHASE %d\n", + sync_input_count[0], sync_input_count[1], + sync_input_count[2], sync_input_count[3], phase); + } + } + + ad9088_print_sysref_phase(phy); + + ret = adi_apollo_adc_bgcal_unfreeze(device, device->dev_info.is_8t8r ? + ADI_APOLLO_ADC_ALL : ADI_APOLLO_ADC_ALL_4T4R); + if (ret) { + dev_err(dev, "Error in adi_apollo_adc_bgcal_unfreeze %d\n", ret); + return ret; + } + + phy->is_initialized = true; + + if (phy->hsci_disable_after_initial_configuration) + adi_apollo_hal_active_protocol_set(&phy->ad9088, ADI_APOLLO_HAL_PROTOCOL_SPI0); + + return JESD204_STATE_CHANGE_DONE; +} + +static int ad9088_jesd204_uninit(struct jesd204_dev *jdev, enum jesd204_state_op_reason reason) +{ + struct device *dev = jesd204_dev_to_device(jdev); + + if (reason != JESD204_STATE_OP_REASON_UNINIT) + return JESD204_STATE_CHANGE_DONE; + + dev_dbg(dev, "%s:%d reason %s\n", __func__, __LINE__, jesd204_state_op_reason_str(reason)); + + return JESD204_STATE_CHANGE_DONE; +} + +const struct jesd204_dev_data jesd204_ad9088_init = { + .state_ops = { + [JESD204_OP_DEVICE_INIT] = { + .per_device = ad9088_jesd204_uninit, + }, + [JESD204_OP_LINK_INIT] = { + .per_link = ad9088_jesd204_link_init, + }, + [JESD204_OP_LINK_SETUP] = { + .per_device = ad9088_jesd204_link_setup, + .mode = JESD204_STATE_OP_MODE_PER_DEVICE, + }, + [JESD204_OP_OPT_SETUP_STAGE1] = { + .per_device = ad9088_jesd204_setup_stage1, + .mode = JESD204_STATE_OP_MODE_PER_DEVICE, + }, + [JESD204_OP_OPT_SETUP_STAGE2] = { + .per_device = ad9088_jesd204_setup_stage2, + .mode = JESD204_STATE_OP_MODE_PER_DEVICE, + }, + [JESD204_OP_CLOCKS_ENABLE] = { + .per_link = ad9088_jesd204_clks_enable, + }, + [JESD204_OP_LINK_ENABLE] = { + .per_link = ad9088_jesd204_link_enable, + .post_state_sysref = true, + }, + [JESD204_OP_LINK_RUNNING] = { + .per_link = ad9088_jesd204_link_running, + }, + [JESD204_OP_OPT_POST_SETUP_STAGE1] = { + .per_device = ad9088_jesd204_post_setup_stage1, + .mode = JESD204_STATE_OP_MODE_PER_DEVICE, + }, + [JESD204_OP_OPT_POST_SETUP_STAGE2] = { + .per_device = ad9088_jesd204_post_setup_stage2, + .mode = JESD204_STATE_OP_MODE_PER_DEVICE, + }, + [JESD204_OP_OPT_POST_SETUP_STAGE3] = { + .per_device = ad9088_jesd204_post_setup_stage3, + .mode = JESD204_STATE_OP_MODE_PER_DEVICE, + }, + [JESD204_OP_OPT_POST_RUNNING_STAGE] = { + .per_device = ad9088_jesd204_post_setup_stage4, + .mode = JESD204_STATE_OP_MODE_PER_DEVICE, + }, + }, + + .max_num_links = 4, + .num_retries = 0, + .sizeof_priv = sizeof(struct ad9088_jesd204_priv), +}; diff --git a/drivers/iio/trx-rf/ad9088/ad9088_mcs.c b/drivers/iio/trx-rf/ad9088/ad9088_mcs.c new file mode 100644 index 00000000000000..77d0755ce5c424 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/ad9088_mcs.c @@ -0,0 +1,492 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * AD9088 MCS (Multi-Chip Synchronization) calibration support + * + * Copyright 2026 Analog Devices Inc. + */ + +#include "ad9088.h" + +int ad9088_mcs_init_cal_setup(struct ad9088_phy *phy) +{ + adi_apollo_device_t *device = &phy->ad9088; + int ret; + + if (!device->dev_info.is_dual_clk) { + ret = adi_apollo_mcs_cal_parameter_set(device, MCS_OFFSET_C_FEMTOSECONDS_INT64, 0); + ret = ad9088_check_apollo_error(&phy->spi->dev, ret, + "adi_apollo_mcs_cal_parameter_set"); + if (ret) + return ret; + } else { + ret = adi_apollo_mcs_cal_parameter_set(device, MCS_OFFSET_A_FEMTOSECONDS_INT64, 0); + ret = ad9088_check_apollo_error(&phy->spi->dev, ret, + "adi_apollo_mcs_cal_parameter_set"); + if (ret) + return ret; + ret = adi_apollo_mcs_cal_parameter_set(device, MCS_OFFSET_B_FEMTOSECONDS_INT64, 0); + ret = ad9088_check_apollo_error(&phy->spi->dev, ret, + "adi_apollo_mcs_cal_parameter_set"); + if (ret) + return ret; + } + + return 0; +} + +int ad9088_mcs_init_cal_status_print(struct ad9088_phy *phy, char *buf, + adi_apollo_mcs_cal_init_status_t *cal_status) +{ + int len = 0; + + len += sprintf(buf + len, "errorCode: %d.\n", cal_status->hdr.errorCode); + len += sprintf(buf + len, "percentComplete: %d.\n", cal_status->hdr.percentComplete); + len += sprintf(buf + len, "performanceMetric: %d.\n", cal_status->hdr.performanceMetric); + len += sprintf(buf + len, "iterCount: %d.\n", cal_status->hdr.iterCount); + len += sprintf(buf + len, "updateCount: %d.\n\n", cal_status->hdr.updateCount); + + len += sprintf(buf + len, "mcsErr: %d.\n\n", cal_status->mcsErr); + + len += sprintf(buf + len, "is_C_Locked: %d.\n", cal_status->data.is_C_Locked); + len += sprintf(buf + len, "is_A_Locked: %d.\n", cal_status->data.is_A_Locked); + len += sprintf(buf + len, "is_B_Locked: %d.\n\n", cal_status->data.is_B_Locked); + + len += sprintf(buf + len, "diff_C_Before_femtoseconds: %lld.\n", + cal_status->data.diff_C_Before_femtoseconds); + len += sprintf(buf + len, "diff_A_Before_femtoseconds: %lld.\n", + cal_status->data.diff_A_Before_femtoseconds); + len += sprintf(buf + len, "diff_B_Before_femtoseconds: %lld.\n", + cal_status->data.diff_B_Before_femtoseconds); + len += sprintf(buf + len, "internal_period_C_femtoseconds: %lld.\n", + cal_status->data.internal_period_C_femtoseconds); + len += sprintf(buf + len, "internal_period_A_femtoseconds: %lld.\n", + cal_status->data.internal_period_A_femtoseconds); + len += sprintf(buf + len, "internal_period_B_femtoseconds: %lld.\n", + cal_status->data.internal_period_B_femtoseconds); + len += sprintf(buf + len, "diff_C_After_femtoseconds: %lld.\n", + cal_status->data.diff_C_After_femtoseconds); + len += sprintf(buf + len, "diff_A_After_femtoseconds: %lld.\n", + cal_status->data.diff_A_After_femtoseconds); + len += sprintf(buf + len, "diff_B_After_femtoseconds: %lld.\n", + cal_status->data.diff_B_After_femtoseconds); + len += sprintf(buf + len, "recommended_offset_C_femtoseconds: %lld.\n", + cal_status->data.recommended_offset_C_femtoseconds); + len += sprintf(buf + len, "recommended_offset_A_femtoseconds: %lld.\n", + cal_status->data.recommended_offset_A_femtoseconds); + len += sprintf(buf + len, "recommended_offset_B_femtoseconds: %lld.\n", + cal_status->data.recommended_offset_B_femtoseconds); + + return len; +} + +int ad9088_delta_t_measurement_set(struct ad9088_phy *phy, u32 mode) +{ + adi_apollo_mailbox_cmd_mcs_bsync_set_config_t bsync_set_config_cmd = {0}; + adi_apollo_mailbox_resp_mcs_bsync_set_config_t bsync_set_config_resp = {0}; + adi_apollo_mailbox_resp_mcs_bsync_go_t bsync_go_resp = {0}; + adi_apollo_device_t *device = &phy->ad9088; + u32 bsync_divider; + int ret; + + if (phy->profile.clk_cfg.clocking_mode == ADI_APOLLO_CLOCKING_MODE_SDR_DIV_8) + bsync_divider = 8 * phy->profile.mcs_cfg.internal_sysref_prd_digclk_cycles_center; + else + bsync_divider = 4 * phy->profile.mcs_cfg.internal_sysref_prd_digclk_cycles_center; + + switch (mode) { + case 0: + bsync_set_config_cmd.func_mode = APOLLO_MCS_BSYNC_ALIGN; + break; + case 1: + bsync_set_config_cmd.func_mode = APOLLO_MCS_BSYNC_OUTPUT_EN; + break; + case 2: + bsync_set_config_cmd.func_mode = APOLLO_MCS_BSYNC_OUTPUT_DIS; + break; + default: + return -EINVAL; + } + + bsync_set_config_cmd.bsync_div = bsync_divider; + + ret = adi_apollo_mailbox_mcs_bsync_set_config(device, &bsync_set_config_cmd, + &bsync_set_config_resp); + ret = ad9088_check_apollo_error(&phy->spi->dev, ret, + "adi_apollo_mailbox_mcs_bsync_set_config"); + if (ret) + return ret; + + if (bsync_set_config_resp.status) + dev_warn(&phy->spi->dev, "bsync_set_config_resp.status: %d.\n", + bsync_set_config_resp.status); + + ret = adi_apollo_mailbox_mcs_bsync_go(device, &bsync_go_resp); + ret = ad9088_check_apollo_error(&phy->spi->dev, ret, "adi_apollo_mailbox_mcs_bsync_go"); + if (ret) + return ret; + + if (bsync_go_resp.status) + dev_warn(&phy->spi->dev, "bsync_go_resp.status: %d.\n", bsync_go_resp.status); + + return 0; +} + +int ad9088_delta_t_measurement_get(struct ad9088_phy *phy, u32 mode, s64 *apollo_delta_t) +{ + adi_apollo_mailbox_resp_mcs_bsync_get_config_t bsync_get_config_resp = {0}; + adi_apollo_device_t *device = &phy->ad9088; + int ret; + + ret = adi_apollo_mailbox_mcs_bsync_get_config(device, &bsync_get_config_resp); + if (ret) + return ret; + + switch (mode) { + case 0: + *apollo_delta_t = bsync_get_config_resp.delta_t0; + break; + case 1: + *apollo_delta_t = bsync_get_config_resp.delta_t1; + break; + default: + return -EINVAL; + } + + dev_dbg(&phy->spi->dev, "bsync_get_config_resp:\n"); + dev_dbg(&phy->spi->dev, "\t status: %d.\n", bsync_get_config_resp.status); + dev_dbg(&phy->spi->dev, "\t func_mode: %d.\n", bsync_get_config_resp.func_mode); + dev_dbg(&phy->spi->dev, "\t bsync_div: %d.\n", bsync_get_config_resp.bsync_div); + dev_dbg(&phy->spi->dev, "\t done_flag: %d.\n", bsync_get_config_resp.done_flag); + dev_dbg(&phy->spi->dev, "\t delta_t0: %lld.\n", bsync_get_config_resp.delta_t0); + dev_dbg(&phy->spi->dev, "\t delta_t1: %lld.\n\n", bsync_get_config_resp.delta_t1); + + return 0; +} + +int ad9088_mcs_init_cal_validate(struct ad9088_phy *phy, + adi_apollo_mcs_cal_init_status_t *cal_status) +{ + int ret = 0; + + adi_apollo_device_t *device = &phy->ad9088; + u64 dev_clk_hz = phy->profile.clk_cfg.dev_clk_freq_Hz; + u32 post_cal_init_sysref_diff_cycles; + u64 int_sysref_align_diff; + bool is_locked; + + /* + * External and Internal Time Difference must be within +/- 0.4 clock cycles. + * In dual clock mode, check both A and B sides; in single clock mode, check center. + */ + if (device->dev_info.is_dual_clk) { + /* Check side A alignment */ + int_sysref_align_diff = abs(cal_status->data.diff_A_After_femtoseconds - + cal_status->data.recommended_offset_A_femtoseconds); + post_cal_init_sysref_diff_cycles = div64_u64(int_sysref_align_diff * dev_clk_hz, + 1000000000000ULL); + if (post_cal_init_sysref_diff_cycles > 400) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, + "Side A: Time difference too large: %u.%02u cycles\n", + post_cal_init_sysref_diff_cycles / 1000, + post_cal_init_sysref_diff_cycles % 1000); + ret = -EFAULT; + goto end; + } + + /* Check side B alignment */ + int_sysref_align_diff = abs(cal_status->data.diff_B_After_femtoseconds - + cal_status->data.recommended_offset_B_femtoseconds); + post_cal_init_sysref_diff_cycles = div64_u64(int_sysref_align_diff * dev_clk_hz, + 1000000000000ULL); + if (post_cal_init_sysref_diff_cycles > 400) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, + "Side B: Time difference too large: %u.%02u cycles\n", + post_cal_init_sysref_diff_cycles / 1000, + post_cal_init_sysref_diff_cycles % 1000); + ret = -EFAULT; + goto end; + } + + /* Check lock status - require at least one side locked */ + is_locked = cal_status->data.is_A_Locked || cal_status->data.is_B_Locked; + if (!is_locked) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, + "MCS Init Cal did not lock SysRefs (A=%d, B=%d).\n", + cal_status->data.is_A_Locked, + cal_status->data.is_B_Locked); + ret = -EFAULT; + goto end; + } + } else { + /* Single clock mode - check center */ + int_sysref_align_diff = abs(cal_status->data.diff_C_After_femtoseconds - + cal_status->data.recommended_offset_C_femtoseconds); + post_cal_init_sysref_diff_cycles = div64_u64(int_sysref_align_diff * dev_clk_hz, + 1000000000000ULL); + if (post_cal_init_sysref_diff_cycles > 400) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, + "Time difference between internal and External SysRefs is too large: %u.%02u\n", + post_cal_init_sysref_diff_cycles / 1000, + post_cal_init_sysref_diff_cycles % 1000); + ret = -EFAULT; + goto end; + } + + /* Check if sysref is locked */ + if (cal_status->data.is_C_Locked != 1) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, + "MCS Init Cal did not lock SysRefs.\n"); + ret = -EFAULT; + goto end; + } + } + + /* Check for Cal errors */ + if (cal_status->hdr.errorCode != 0) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, + "MCS Init Cal Apollo CPU errorCode: 0x%X.\n", + cal_status->hdr.errorCode); + ret = -EFAULT; + goto end; + } + + if (cal_status->mcsErr != 0) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, + "MCS Init Cal MCS errorCode: 0x%X.\n", cal_status->mcsErr); + ret = -EFAULT; + goto end; + } + +end: + adi_apollo_hal_log_write(device, (ret == 0) ? ADI_CMS_LOG_API : ADI_CMS_LOG_ERR, + "MCS Init Cal Validation: %s.\n", ret == 0 ? "Passed" : "Failed!"); + + return ret; +} + +int ad9088_mcs_tracking_cal_setup(struct ad9088_phy *phy, u32 mcs_track_decimation, + u16 initialize_track_cal) +{ + adi_apollo_device_t *device = &phy->ad9088; + int ret; + + /* Set MCS tracking cal decimation for more precise TDC measurements. */ + ret = adi_apollo_mcs_cal_tracking_decimation_set(device, mcs_track_decimation); + ret = ad9088_check_apollo_error(&phy->spi->dev, ret, + "adi_apollo_mcs_cal_tracking_decimation_set"); + if (ret) + return ret; + + /* Optional: Calibration values for setting tracking offset between internal + * and external SYSREF may be customized to align with hardware setup + */ + ret = adi_apollo_mcs_cal_parameter_set(device, MCS_ADF4382_TRACK_TARGET_0_INT32, 0); + ret = ad9088_check_apollo_error(&phy->spi->dev, ret, "adi_apollo_mcs_cal_parameter_set"); + if (ret) + return ret; + + if (device->dev_info.is_dual_clk) { + ret = adi_apollo_mcs_cal_parameter_set(device, MCS_ADF4382_TRACK_TARGET_1_INT32, 0); + ret = ad9088_check_apollo_error(&phy->spi->dev, ret, + "adi_apollo_mcs_cal_parameter_set"); + if (ret) + return ret; + } + + /* Enable MCS Tracking Cal. Tracking decimation needs to be updated before this API call. */ + ret = adi_apollo_mcs_cal_tracking_enable(device, 1); + ret = ad9088_check_apollo_error(&phy->spi->dev, ret, "adi_apollo_mcs_cal_tracking_enable"); + if (ret) + return ret; + + /* Initialize MCS Tracking Cal if not done by device profile or mcs_cal_config struct + * (i.e. cal_config.track_initialize = 1). + */ + if (initialize_track_cal) { + ret = adi_apollo_mcs_cal_tracking_initialize_set(device); + ret = ad9088_check_apollo_error(&phy->spi->dev, ret, + "adi_apollo_mcs_cal_tracking_initialize_set"); + if (ret) + return ret; + } + + return 0; +} + +/** + * ad9088_mcs_tracking_cal_validate - Validate MCS tracking calibration synchronicity + * @phy: AD9088 PHY structure + * @buf: Buffer to write validation results + * @buf_size: Size of the buffer + * + * Compares the ADF4382 bleed current values reported by Apollo's MCS tracking + * calibration with the actual hardware values read from ADF4382. This verifies + * that the tracking calibration is properly synchronized. + * + * Return: Number of bytes written to buf, or negative error code + */ +int ad9088_mcs_tracking_cal_validate(struct ad9088_phy *phy, char *buf, size_t buf_size) +{ + adi_apollo_mcs_cal_status_t tracking_cal_status = { }; + adi_apollo_mcs_private_cal_status_t *mcs_cal_status; + adi_apollo_device_t *device = &phy->ad9088; + struct device *dev = &phy->spi->dev; + long long hw_bleed_pol, hw_coarse_current, hw_fine_current; + u8 fw_bleed_pol, fw_coarse_current; + s16 fw_fine_current; + bool need_unfreeze = false; + int len = 0; + int ret; + + if (!phy->iio_adf4382) { + len = scnprintf(buf, buf_size, "ADF4382 IIO channel not available\n"); + return len; + } + + if (!phy->mcs_cal_bg_tracking_run) { + len = scnprintf(buf, buf_size, "BG tracking not running\n"); + return len; + } + + /* Freeze tracking calibration to get consistent readings */ + if (!phy->mcs_cal_bg_tracking_freeze) { + ret = adi_apollo_mcs_cal_bg_tracking_freeze(device); + ret = ad9088_check_apollo_error(dev, ret, "adi_apollo_mcs_cal_bg_tracking_freeze"); + if (ret) + return ret; + need_unfreeze = true; + } + + /* Get Apollo's tracking calibration status */ + ret = adi_apollo_mcs_cal_tracking_status_get(device, &tracking_cal_status); + ret = ad9088_check_apollo_error(dev, ret, "adi_apollo_mcs_cal_tracking_status_get"); + if (ret) + goto out_unfreeze; + + /* Read ADF4382 hardware values via IIO ext_info */ + ret = ad9088_iio_read_channel_ext_info(phy, phy->iio_adf4382, "bleed_pol", &hw_bleed_pol); + if (ret) + goto out_unfreeze; + + ret = ad9088_iio_read_channel_ext_info(phy, phy->iio_adf4382, "coarse_current", + &hw_coarse_current); + if (ret) + goto out_unfreeze; + + ret = ad9088_iio_read_channel_ext_info(phy, phy->iio_adf4382, "fine_current", + &hw_fine_current); + if (ret) + goto out_unfreeze; + + /* Get firmware-reported values */ + mcs_cal_status = &tracking_cal_status.mcs_tracking_cal_status; + fw_bleed_pol = mcs_cal_status->adf4382_specific_status[0].bleed_pol; + fw_coarse_current = mcs_cal_status->adf4382_specific_status[0].current_coarse_value; + fw_fine_current = mcs_cal_status->adf4382_specific_status[0].current_fine_value; + + /* Compare and report results */ + len = scnprintf(buf, buf_size, + "MCS Tracking Cal Validation:\n" + " ADF4382 HW: bleed_pol=%lld coarse=%lld fine=%lld\n" + " Apollo FW: bleed_pol=%u coarse=%u fine=%d\n" + " Status: %s\n", + hw_bleed_pol, hw_coarse_current, hw_fine_current, + fw_bleed_pol, fw_coarse_current, fw_fine_current, + (hw_bleed_pol == fw_bleed_pol && + hw_coarse_current == fw_coarse_current && + hw_fine_current == fw_fine_current) ? "SYNCHRONIZED" : "MISMATCH"); + + if (hw_bleed_pol != fw_bleed_pol) + dev_warn(dev, "MCS Tracking: bleed_pol mismatch HW=%lld FW=%u\n", + hw_bleed_pol, fw_bleed_pol); + + if (hw_coarse_current != fw_coarse_current) + dev_warn(dev, "MCS Tracking: coarse_current mismatch HW=%lld FW=%u\n", + hw_coarse_current, fw_coarse_current); + + if (hw_fine_current != fw_fine_current) + dev_warn(dev, "MCS Tracking: fine_current mismatch HW=%lld FW=%d\n", + hw_fine_current, fw_fine_current); + +out_unfreeze: + if (need_unfreeze) { + int ret2 = adi_apollo_mcs_cal_bg_tracking_unfreeze(device); + + ret = ad9088_check_apollo_error(dev, ret2, + "adi_apollo_mcs_cal_bg_tracking_unfreeze"); + } + + return ret < 0 ? ret : len; +} + +int ad9088_mcs_track_cal_status_print(struct ad9088_phy *phy, char *buf, + adi_apollo_mcs_cal_status_t *cal_status, + u8 print_full_state) +{ + adi_apollo_mcs_private_cal_status_t *mcs_cal_status = &cal_status->mcs_tracking_cal_status; + int len = 0; + + if (print_full_state == 1) { + len += sprintf(buf + len, "errorCode: %d.\n", cal_status->hdr.errorCode); + len += sprintf(buf + len, "percentComplete: %d.\n", + cal_status->hdr.percentComplete); + len += sprintf(buf + len, "performanceMetric: %d.\n", + cal_status->hdr.performanceMetric); + len += sprintf(buf + len, "iterCount: %d.\n", cal_status->hdr.iterCount); + len += sprintf(buf + len, "updateCount: %d.\n\n", cal_status->hdr.updateCount); + + len += sprintf(buf + len, "foreground_done: %d.\n", + mcs_cal_status->foreground_done); + len += sprintf(buf + len, "track_state[0]: %d.\n", mcs_cal_status->track_state[0]); + len += sprintf(buf + len, "track_state[1]: %d.\n", mcs_cal_status->track_state[1]); + len += sprintf(buf + len, "track_lock[0]: %d.\n", mcs_cal_status->track_lock[0]); + len += sprintf(buf + len, "track_lock[1]: %d.\n", mcs_cal_status->track_lock[1]); + len += sprintf(buf + len, "halt_active: %d.\n\n", mcs_cal_status->halt_active); + len += sprintf(buf + len, "force_background_done[0]: %d.\n", + mcs_cal_status->force_background_done[0]); + len += sprintf(buf + len, "force_background_done[1]: %d.\n", + mcs_cal_status->force_background_done[1]); + len += sprintf(buf + len, "abort_done: %d.\n\n", mcs_cal_status->abort_done); + len += sprintf(buf + len, "adf4382_specific_status[0].bleed_pol: %d.\n", + mcs_cal_status->adf4382_specific_status[0].bleed_pol); + len += sprintf(buf + len, "adf4382_specific_status[0].current_coarse_value: %d.\n", + mcs_cal_status->adf4382_specific_status[0].current_coarse_value); + len += sprintf(buf + len, "adf4382_specific_status[0].current_fine_value: %d.\n", + mcs_cal_status->adf4382_specific_status[0].current_fine_value); + len += sprintf(buf + len, "adf4382_specific_status[0].EOR_POS: %d.\n", + mcs_cal_status->adf4382_specific_status[0].EOR_POS); + len += sprintf(buf + len, "adf4382_specific_status[0].EOR_NEG: %d.\n", + mcs_cal_status->adf4382_specific_status[0].EOR_NEG); + len += sprintf(buf + len, "adf4382_specific_status[0].EOR_Coarse: %d.\n", + mcs_cal_status->adf4382_specific_status[0].EOR_Coarse); + len += sprintf(buf + len, "adf4382_specific_status[1].bleed_pol: %d.\n", + mcs_cal_status->adf4382_specific_status[1].bleed_pol); + len += sprintf(buf + len, "adf4382_specific_status[1].current_coarse_value: %d.\n", + mcs_cal_status->adf4382_specific_status[1].current_coarse_value); + len += sprintf(buf + len, "adf4382_specific_status[1].current_fine_value: %d.\n", + mcs_cal_status->adf4382_specific_status[1].current_fine_value); + len += sprintf(buf + len, "adf4382_specific_status[1].EOR_POS: %d.\n", + mcs_cal_status->adf4382_specific_status[1].EOR_POS); + len += sprintf(buf + len, "adf4382_specific_status[1].EOR_NEG: %d.\n", + mcs_cal_status->adf4382_specific_status[1].EOR_NEG); + len += sprintf(buf + len, "adf4382_specific_status[1].EOR_Coarse: %d.\n", + mcs_cal_status->adf4382_specific_status[1].EOR_Coarse); + + len += sprintf(buf + len, "current_measure[0]: %lld.\n", + mcs_cal_status->current_measure[0]); + len += sprintf(buf + len, "current_measure[1]: %lld.\n", + mcs_cal_status->current_measure[1]); + } else { + len += sprintf(buf + len, "Tracking Cal[0]: --> \t"); + len += sprintf(buf + len, "bleed_pol: %d. \t", + mcs_cal_status->adf4382_specific_status[0].bleed_pol); + len += sprintf(buf + len, "current_coarse: %d. \t", + mcs_cal_status->adf4382_specific_status[0].current_coarse_value); + len += sprintf(buf + len, "current_fine: %d. \t", + mcs_cal_status->adf4382_specific_status[0].current_fine_value); + len += sprintf(buf + len, "current_measure: %lld.\n", + mcs_cal_status->current_measure[0]); + } + + return len; +} diff --git a/drivers/iio/trx-rf/ad9088/adi_inc/adi_cms_api_common.h b/drivers/iio/trx-rf/ad9088/adi_inc/adi_cms_api_common.h new file mode 100644 index 00000000000000..2f328ceb5b58f7 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/adi_inc/adi_cms_api_common.h @@ -0,0 +1,372 @@ +/*! + * \brief Common API definitions header file. + * This file contains all common API definitions. + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_API_COMMON + * @{ + */ +#ifndef __ADI_CMS_API_COMMON_H__ +#define __ADI_CMS_API_COMMON_H__ + +/*============= I N C L U D E S ============*/ +#ifdef __KERNEL__ +#include +#include +#include + +#ifndef UINT64_MAX +#define UINT64_MAX U64_MAX +#endif + +#else +#include +#include +#include +#include +#include +#include +#include +#endif +#include "adi_cms_api_config.h" + +/*============= D E F I N E S ==============*/ + +#ifndef __maybe_unused +#define __maybe_unused __attribute__((__unused__)) +#endif + +/*! + * \brief Enumerate error code + */ +typedef enum { + API_CMS_ERROR_OK = 0, /*!< No Error */ + API_CMS_ERROR_ERROR = -1, /*!< General Error */ + API_CMS_ERROR_NULL_PARAM = -2, /*!< Null parameter */ + API_CMS_ERROR_OVERFLOW = -3, /*!< General overflow */ + API_CMS_ERROR_DIV_BY_ZERO = -4, /*!< Divide by zero */ + API_CMS_ERROR_FEAT_LOCKOUT = -5, /*!< Device feature is locked out */ + API_CMS_ERROR_SPI_SDO = -10, /*!< Wrong value assigned to the SDO in device structure */ + API_CMS_ERROR_INVALID_HANDLE_PTR = -11, /*!< Device handler pointer is invalid */ + API_CMS_ERROR_INVALID_XFER_PTR = -12, /*!< Invalid pointer to the SPI write or read function assigned */ + API_CMS_ERROR_INVALID_DELAYUS_PTR = -13, /*!< Invalid pointer to the delay_us function assigned */ + API_CMS_ERROR_INVALID_PARAM = -14, /*!< Invalid parameter passed */ + API_CMS_ERROR_INVALID_RESET_CTRL_PTR = -15, /*!< Invalid pointer to the reset control function assigned */ + API_CMS_ERROR_NOT_SUPPORTED = -16, /*!< Not supported */ + API_CMS_ERROR_INVALID_MASK_SELECT = -17, /*!< Invalid bitmask select parameter passed */ + API_CMS_ERROR_INVALID_PROFILE_SELECT = -18, /*!< Invalid profile parameter passed */ + API_CMS_ERROR_IN_REF_STATUS = -19, /*!< The Input Reference Signal is not available */ + API_CMS_ERROR_VCO_OUT_OF_RANGE = -20, /*!< The VCO is out of range */ + API_CMS_ERROR_PLL_NOT_LOCKED = -21, /*!< PLL is not locked */ + API_CMS_ERROR_DLL_NOT_LOCKED = -22, /*!< DLL is not locked */ + API_CMS_ERROR_MODE_NOT_IN_TABLE = -23, /*!< JESD Mode not in table */ + API_CMS_ERROR_CLK_CKT = -24, /*!< Clock circuit error */ + API_CMS_ERROR_FTW_LOAD_ACK = -30, /*!< FTW acknowledge not received */ + API_CMS_ERROR_NCO_NOT_ENABLED = -31, /*!< The NCO is not enabled */ + API_CMS_ERROR_INIT_SEQ_FAIL = -40, /*!< Initialization sequence failed */ + API_CMS_ERROR_TEST_FAILED = -50, /*!< Test failed */ + API_CMS_ERROR_SPI_XFER = -60, /*!< SPI transfer error */ + API_CMS_ERROR_TX_EN_PIN_CTRL = -62, /*!< TX enable function error */ + API_CMS_ERROR_RESET_PIN_CTRL = -63, /*!< HW reset function error */ + API_CMS_ERROR_EVENT_HNDL = -64, /*!< Event handling error */ + API_CMS_ERROR_HW_OPEN = -65, /*!< HW open function error */ + API_CMS_ERROR_HW_CLOSE = -66, /*!< HW close function error */ + API_CMS_ERROR_LOG_OPEN = -67, /*!< Log open error */ + API_CMS_ERROR_LOG_WRITE = -68, /*!< Log write error */ + API_CMS_ERROR_LOG_CLOSE = -69, /*!< Log close error */ + API_CMS_ERROR_DELAY_US = -70, /*!< Delay error */ + API_CMS_ERROR_HSCI_LINK_UP = -79, /*!< HSCI Linkup error */ + API_CMS_ERROR_SPI_REGIO_XFER = -80, /*!< Register transaction error spi */ + API_CMS_ERROR_HSCI_REGIO_XFER = -81, /*!< Register transaction error hsci */ + API_CMS_ERROR_OPERATION_TIMEOUT = -82, /*!< Operation timeout */ + API_CMS_ERROR_LINK_DOWN = -83, /*!< JESD links down */ + API_CMS_ERROR_FILE_OPEN = -84, /*!< File open error */ + API_CMS_ERROR_SERDES_CAL_ERROR = -85, /*!< SERDES cal error */ + API_CMS_ERROR_SERDES_CAL_TIMEOUT = -86, /*!< SERDES cal timeout */ + API_CMS_ERROR_PLATFORM_READ = -87, /*!< Platform (e.g. FPGA) read error */ + API_CMS_ERROR_PLATFORM_WRITE = -88, /*!< Platform (e.g. FPGA) write error */ + API_CMS_ERROR_FILE_READ = -89, /*!< File read error */ + API_CMS_ERROR_FILE_WRITE = -90, /*!< File write error */ + API_CMS_ERROR_FILE_OPERATION = -91, /*!< General file error (e.g. seek) */ + API_CMS_ERROR_PLATFORM_IMAGE_LOAD = -92, /*!< Error loading platform FPGA image */ + API_CMS_ERROR_NOT_IMPLEMENTED = -93, /*!< Feature not currently implemented */ + API_CMS_ERROR_STRUCT_UNPOPULATED = -94, /*!< Struct not populated */ + API_CMS_ERROR_PROTOCOL_OP_NOT_SUPPORTED = -95, /*!< Protocol not supported for operation */ + API_CMS_ERROR_INVALID_CLK_OR_REF_PARAM = -96, /*!< Invalid clock or reference parameter */ + API_CMS_ERROR_UNEXPECTED_RESULT = -97, /*!< An unexpected result */ + + API_CMS_ERROR_MEM_ALLOC = -100, /*!< memory allocation error */ + API_CMS_ERROR_MMAP = -101, /*!< memory mapping error */ + API_CMS_ERROR_DEV_MEM_OPEN = -102, /*!< device memory open error */ + + API_CMS_ERROR_I2C_ERROR = -110, /*!< I2C General Error. */ + API_CMS_ERROR_I2C_WRITE = -111, /*!< I2C Write Operation Failed. */ + API_CMS_ERROR_I2C_READ = -112, /*!< I2C Read Operation Failed. */ + API_CMS_ERROR_I2C_BUSY = -113, /*!< I2C controller or device is busy. */ + API_CMS_ERROR_PMOD_NVM_LOCK = -114, /*!< A fault occurred while accessing the Power Module's NVM (Non Volatile Memory). */ + + API_CMS_ERROR_EC_RAM_LOCK_ERROR = -120, /*!< EC ram-lock error */ + API_CMS_ERROR_PROFILE_CRC = -121, /*!< Profile CRC invalid */ + API_CMS_ERROR_MAILBOX_RESP_STATUS = -122, /*!< Mailbox Command Response Status Error */ + + API_CMS_ERROR_MCS_CAL_CONFIG_ERROR = -130, /*!< MCS Cal Configuration related error */ + API_CMS_ERROR_MCS_INIT_CAL_ERROR = -131, /*!< MCS Init Cal related error */ + API_CMS_ERROR_MCS_TRACK_CAL_ERROR = -132, /*!< MCS Tracking Cal related error */ + API_CMS_ERROR_MCS_CAL_TIMEOUT = -133, /*!< MCS Cal run or status check response timed out error */ + API_CMS_ERROR_ADC_INIT_CAL_ERROR = -134, /*!< ADC Init Cal related error */ + API_CMS_ERROR_ADC_TRACK_CAL_ERROR = -135, /*!< ADC Tracking Cal related error */ + API_CMS_ERROR_ADC_CAL_TIMEOUT = -136, /*!< ADC Cal run or status check response timed out error */ + + API_CMS_ERROR_BAD_STATE = -140, /*!< Device is not in appropriate state to perform operation */ + API_CMS_ERROR_VEC_IQ_LEN_MISMATCH = -141, /*!< Complex vector I&Q lengths not equal */ + + API_CMS_ERROR_STARTUP_FW_RDY_FOR_PROFILE_ERROR = -150, /*!< FW did not reach ready for profile config state */ + API_CMS_ERROR_STARTUP_FW_MAILBOX_RDY_ERROR = -151, /*!< FW did not reach mailbox ready state */ + + API_CMS_ERROR_SMON_FRAMER_SOF_NOT_FOUND = -160, /*!< Start of frame not found */ + API_CMS_ERROR_SMON_FRAMER_MIN_SAMPLES_ERROR = -161, /*!< Min samples not available for de-serialization */ + + API_CMS_ERROR_PLATFORM_CAPTURE_INVALID_CONFIG = -200, /*!< Invalid platform capture configuration */ + +} adi_cms_error_e; + +/*! + * \brief Enumerate log source type + */ +typedef enum { + ADI_CMS_LOG_NONE = 0x0000, /*!< all not selected */ + ADI_CMS_LOG_ERR = 0x0001, /*!< error message */ + ADI_CMS_LOG_WARN = 0x0002, /*!< warning message */ + ADI_CMS_LOG_MSG = 0x0004, /*!< tips info message */ + ADI_CMS_LOG_SPI = 0x0010, /*!< spi r/w info message */ + ADI_CMS_LOG_API = 0x0020, /*!< api info message */ + ADI_CMS_LOG_ALL = 0xFFFF /*!< all selected */ +} adi_cms_log_type_e; + +/*! + * \brief ADI Device Identification Data + */ +typedef struct { + uint8_t chip_type; /*!< Chip Type Code */ + uint16_t prod_id; /*!< Product ID Code */ + uint8_t prod_grade; /*!< Product Grade Code */ + uint8_t dev_revision; /*!< Device Revision */ +}adi_cms_chip_id_t; + +/*! + * \brief API register access structure + */ +typedef struct { + uint16_t reg; /*!< Register address */ + uint8_t val; /*!< Register value */ +}adi_cms_reg_data_t; + +/*! + * \brief SPI mode settings + */ +typedef enum { + SPI_NONE = 0, /*!< Keep this for test */ + SPI_SDO = 1, /*!< SDO active, 4-wire only */ + SPI_SDIO = 2, /*!< SDIO active, 3-wire only */ + SPI_CONFIG_MAX = 3 /*!< Keep it last */ +}adi_cms_spi_sdo_config_e; + +/*! + * \brief SPI bit order settings + */ +typedef enum { + SPI_MSB_LAST = 0, /*!< LSB first */ + SPI_MSB_FIRST = 1 /*!< MSB first */ +}adi_cms_spi_msb_config_e; + +/*! + * \brief SPI address increment settings + */ +typedef enum { + SPI_ADDR_DEC_AUTO = 0, /*!< auto decremented */ + SPI_ADDR_INC_AUTO = 1 /*!< auto incremented */ +}adi_cms_spi_addr_inc_e; + +/*! + *\brief driver operation mode + */ +typedef enum +{ + OPEN_DRAIN_MODE = 0, + CMOS_MODE = 1 +}adi_cms_driver_mode_config_e; + +/*! + * \brief Enumerate Impedance Types + */ +typedef enum { + ADI_CMS_NO_INTERNAL_RESISTOR = 0, /*!< disable internal resistor */ + ADI_CMS_INTERNAL_RESISTOR_100_OHM = 1, /*!< internal 100ohm resistor */ + ADI_CMS_INTERNAL_RESISTOR_50_OHM = 2, /*!< internal 50ohm resistor */ + ADI_CMS_INTERNAL_RESISTOR_UNKNOWN = 3 /*!< unknown type */ +}adi_cms_signal_impedance_type_e; + +/*! + * \brief Enumerate Signal Types + */ +typedef enum { + SIGNAL_CMOS = 0, /*!< CMOS signal */ + SIGNAL_LVDS = 1, /*!< LVDS signal */ + SIGNAL_CML = 2, /*!< CML signal */ + SIGNAL_LVPECL = 3, /*!< LVPECL signal */ + SIGNAL_UNKNOWN = 4 /*!< UNKNOW signal */ +}adi_cms_signal_type_e; + +/*! + * \brief Enumerate coupling mode + */ +typedef enum { + COUPLING_AC = 0, /*!< AC coupled signal */ + COUPLING_DC = 1, /*!< DC signal */ + COUPLING_UNKNOWN = 2 /*!< UNKNOWN coupling */ +}adi_cms_signal_coupling_e; + +/*! + * \brief Enumerates JESD LINK Signals + */ +typedef enum { + JESD_LINK_NONE = 0, /*!< JESD link none */ + JESD_LINK_0 = 1, /*!< JESD link 0 */ + JESD_LINK_1 = 2, /*!< JESD link 1 */ + JESD_LINK_ALL = 3 /*!< All JESD links */ +}adi_cms_jesd_link_e; + +/*! + * \brief Enumerates SYNCOUTB Output Signals + */ +typedef enum { + SYNCOUTB_0 = 0x0, /*!< SYNCOUTB 0 */ + SYNCOUTB_1 = 0x1, /*!< SYNCOUTB 1 */ + SYNCOUTB_ALL = 0xFF /*!< ALL SYNCOUTB SIGNALS */ +}adi_cms_jesd_syncoutb_e; + +/*! + * \brief Enumerates SYSREF Synchronization Mode + */ +typedef enum { + SYSREF_NONE = 0, /*!< No SYSREF Support */ + SYSREF_ONESHOT = 1, /*!< ONE-SHOT SYSREF */ + SYSREF_CONT = 2, /*!< Continuous SysRef sync. */ + SYSREF_MON = 3, /*!< SYSREF monitor mode */ + SYSREF_MODE_INVALID = 4 +}adi_cms_jesd_sysref_mode_e; + +/*! + * \brief Enumerates PRBS pattern type + */ +typedef enum { + PRBS_NONE = 0, /*!< PRBS off */ + PRBS7 = 1, /*!< PRBS7 pattern */ + PRBS9 = 2, /*!< PRBS9 pattern */ + PRBS15 = 3, /*!< PRBS15 pattern */ + PRBS23 = 4, /*!< PRBS23 pattern */ + PRBS31 = 5, /*!< PRBS31 pattern */ + PRBS_MAX = 6 /*!< Number of member */ +}adi_cms_jesd_prbs_pattern_e; + +/*! + * \brief Enumerates all available Jesd Subclass Modes + */ +typedef enum { + JESD_SUBCLASS_0 = 0, /*!< JESD SUBCLASS 0 */ + JESD_SUBCLASS_1 = 1, /*!< JESD SUBCLASS 1 */ + JESD_SUBCLASS_INVALID = 2 +}adi_cms_jesd_subclass_e; + +/*! + * \brief Defines JESD Parameters + */ +typedef struct { + uint8_t jesd_l; /*!< No of lanes */ + uint8_t jesd_f; /*!< No of octets in a frame */ + uint8_t jesd_m; /*!< No of converters */ + uint8_t jesd_s; /*!< No of samples */ + uint8_t jesd_hd; /*!< High Density */ + uint16_t jesd_k; /*!< No of frames for a multi-frame */ + uint8_t jesd_n; /*!< Converter resolution */ + uint8_t jesd_np; /*!< Bit packing sample */ + uint8_t jesd_cf; /*!< Parameter CF */ + uint8_t jesd_cs; /*!< Parameter CS */ + uint8_t jesd_did; /*!< Device ID DID */ + uint8_t jesd_bid; /*!< Bank ID. BID */ + uint8_t jesd_lid0; /*!< Lane ID for lane0 */ + uint8_t jesd_subclass; /*!< Subclass */ + uint8_t jesd_scr; /*!< Scramble enable */ + uint8_t jesd_duallink; /*!< Link mode (single/dual) */ + uint8_t jesd_jesdv; /*!< Version (0:204A, 1:204B, 2:204C) */ + uint8_t jesd_mode_id; /*!< JESD mode ID */ + uint8_t jesd_mode_c2r_en; /*!< JESD mode C2R enable */ + uint8_t jesd_mode_s_sel; /*!< JESD mode S value */ + uint8_t jtx_ns; /*!< JTx NS value. ADI, non-jesd standard param */ +}adi_cms_jesd_param_t; + +/*! + * \brief Device transaction config structure + */ +typedef struct { + uint8_t addr_len; /*!< Interface reg address size, in bytes */ + uint8_t data_len; /*!< Interface reg data size, in bytes */ + uint16_t stream_len; /*!< Interface transaction stream length. Number of data words to transfer. */ + uint32_t mask; /*!< Interface reg mask */ +} adi_cms_hal_txn_config_t; + +#ifndef CLIENT_IGNORE + +typedef int32_t(*adi_cms_spi_write_t)(void *user_data, const uint8_t *in_data, uint32_t size_bytes, adi_cms_hal_txn_config_t *txn_config); +typedef int32_t(*adi_cms_spi_read_t)(void *user_data, const uint8_t *in_data, uint8_t *out_data, uint32_t size_bytes, adi_cms_hal_txn_config_t *txn_config); +typedef int32_t(*adi_cms_delay_us_t)(void *user_data, uint32_t us); + +#endif + +#define _ADI_CMS_ERROR_PRINT_ENABLED(err) fprintf(stderr, "TB:ERROR %d in %s(): line %d in file \"%s\"\n", err, __func__, __LINE__, __FILE__) +#define _ADI_CMS_ERROR_PRINT_DISABLED(err) ; + +#ifdef ADI_EN_STDERR +#define ADI_CMS_ERROR_PRINT(err) _ADI_CMS_ERROR_PRINT_ENABLED(err) +#else +#define ADI_CMS_ERROR_PRINT(err) _ADI_CMS_ERROR_PRINT_DISABLED(err) +#endif /*ADI_EN_STDERR*/ + +#define ADI_CMS_ERROR_RETURN(err) \ + { \ + if (err != API_CMS_ERROR_OK) { \ + ADI_CMS_ERROR_PRINT(err); \ + return err; \ + } \ + } + +#define ADI_CMS_ERROR_GOTO(err, label) \ + { \ + if (err != API_CMS_ERROR_OK) { \ + ADI_CMS_ERROR_PRINT(err); \ + goto label; \ + } \ + } + +#define ADI_CMS_CHECK(r, err) {if (r) ADI_CMS_ERROR_RETURN(err);} +#define ADI_CMS_NULL_PTR_CHECK(r) ADI_CMS_CHECK(r == NULL, API_CMS_ERROR_NULL_PARAM) +#define ADI_CMS_MEM_ALLOC_CHECK(r) ADI_CMS_CHECK(r == NULL, API_CMS_ERROR_MEM_ALLOC) +#define ADI_CMS_FILE_OPEN_CHECK(r) ADI_CMS_CHECK(r == NULL, API_CMS_ERROR_FILE_OPEN) +#define ADI_CMS_INVALID_PARAM_CHECK(r) ADI_CMS_CHECK(r, API_CMS_ERROR_INVALID_PARAM) +#define ADI_CMS_MAX_SELECT_CHECK(r, m) ADI_CMS_CHECK((((r) & (~(m)))), API_CMS_ERROR_INVALID_MASK_SELECT) +#define ADI_CMS_SINGLE_SELECT_CHECK(r) ADI_CMS_CHECK(!(r > 0 && (r & (r - 1)) == 0), API_CMS_ERROR_INVALID_MASK_SELECT) +#define ADI_CMS_RANGE_CHECK(r, min, max) ADI_CMS_CHECK(r < min || r > max, API_CMS_ERROR_INVALID_PARAM) + +#define ADI_CMS_MASK_MATCH(value, mask) ((value & mask) == mask) + +#define ADI_CMS_MEM_ALLOC_FREE(r) if (r != NULL) {free(r); r = NULL;} +#define ADI_CMS_FILE_CLOSE(r) if (r != NULL) {fclose(r); r = NULL;} + +#endif /* __ADI_API_COMMON_H__ */ +/*! @} */ \ No newline at end of file diff --git a/drivers/iio/trx-rf/ad9088/adi_inc/adi_cms_api_config.h b/drivers/iio/trx-rf/ad9088/adi_inc/adi_cms_api_config.h new file mode 100644 index 00000000000000..b802c222ade819 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/adi_inc/adi_cms_api_config.h @@ -0,0 +1,23 @@ +/*! + * \brief API configuration header file. + * This file contains API configuration parameters. + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_API_CONFIG + * @{ + */ +#ifndef __ADI_CMS_API_CONFIG_H__ +#define __ADI_CMS_API_CONFIG_H__ + +/*============= D E F I N E S ==============*/ +#define ADI_REPORT_VERBOSE ADI_CMS_LOG_ALL /*!< verbose log report control */ +#define ADI_INVALID_POINTER 0 /*!< invalid pointer address */ + +#endif /* __ADI_API_CONFIG_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/adi_utils/inc/adi_utils.h b/drivers/iio/trx-rf/ad9088/adi_utils/inc/adi_utils.h new file mode 100644 index 00000000000000..065827718bbaae --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/adi_utils/inc/adi_utils.h @@ -0,0 +1,148 @@ +/*! + * \brief ADI utility functions header file. + * + * \version 0.1.x + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup __ADI_UTILS__ + * @{ + */ +#ifndef __ADI_UTILS_H__ +#define __ADI_UTILS_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_cms_api_common.h" + +/*============= D E F I N E S ==============*/ +#define ADI_UTILS_POW2_32 ((uint64_t)1 << 32) +#define ADI_UTILS_POW2_48 ((uint64_t)1 << 48) +#define ADI_UTILS_MAXUINT24 (0xffffff) +#define ADI_UTILS_MAXUINT32 (ADI_UTILS_POW2_32 - 1) +#define ADI_UTILS_MAXUINT48 (ADI_UTILS_POW2_48 - 1) + +#define ADI_UTILS_GET_BYTE(w, p) (uint8_t)(((w) >> (p)) & 0xff) +#define ADI_UTILS_DIV_U64(x, y) ((x) / (y)) +#define ADI_UTILS_BIT(x) ((1) << (x)) +#define ADI_UTILS_ALL (-1) +#define ADI_UTILS_ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) + +#define ADI_UTILS_MAX(a,b) ((a) > (b) ? (a) : (b)) +#define ADI_UTILS_MIN(a,b) ((a) < (b) ? (a) : (b)) + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +int32_t adi_api_utils_gcd(int32_t u, int32_t v); + +uint64_t adi_api_utils_gcd_64(uint64_t u, uint64_t v); + +uint32_t adi_api_utils_lcm(uint32_t p, uint32_t q); + +uint64_t adi_api_utils_lcm_64(uint64_t p, uint64_t q); + +int32_t adi_api_utils_is_power_of_two(uint64_t x); + +void adi_api_utils_mult_64(uint32_t a, uint32_t b, uint32_t *hi, uint32_t *lo); + +/** + * @brief Convert a ratio M/N to (X+A/B)/(2^bit_size) + * + * @param ratio_num Ratio numerator + * @param ratio_den Ratio denominator + * @param bit_size Number of bits + * @param x Decomposition integer component + * @param a Decomposition fractional numerator + * @param b Decomposition fractional denominator + */ +int32_t adi_api_utils_ratio_decomposition(uint64_t ratio_num, uint64_t ratio_den, uint8_t bit_size, uint64_t *x, uint64_t *a, uint64_t *b); + +/** + * @brief Calculate a ratio M/N = (X+A/B)/(2^bit_size) + * + * @param x Composition integer component + * @param a Composition fractional numerator + * @param b Composition fractional denominator + * @param ratio_num Ratio numerator + * @param ratio_den Ratio denominator + * @param bit_size Number of bits + */ +int32_t adi_api_utils_ratio_composition(uint64_t x, uint64_t a, uint64_t b, uint32_t *ratio_num, uint32_t *ratio_den, uint8_t bit_size); + +void adi_api_utils_lshift_128(uint64_t *hi, uint64_t *lo); + +void adi_api_utils_rshift_128(uint64_t *hi, uint64_t *lo); + +void adi_api_utils_mult_128(uint64_t a, uint64_t b, uint64_t *hi, uint64_t *lo); + +void adi_api_utils_div_128(uint64_t a_hi, uint64_t a_lo, uint64_t b_hi, + uint64_t b_lo, uint64_t *hi, uint64_t *lo); + +void adi_api_utils_mod_128(uint64_t ah, uint64_t al, uint64_t div, uint64_t *mod); + +void adi_api_utils_add_128(uint64_t ah, uint64_t al, uint64_t bh, uint64_t bl, + uint64_t *hi, uint64_t *lo); + +void adi_api_utils_subt_128(uint64_t ah, uint64_t al, uint64_t bh,uint64_t bl, + uint64_t *hi,uint64_t *lo); + +uint64_t adi_api_utils_div_floor_u64(uint64_t a, uint64_t b); + +uint64_t adi_api_utils_div_ceil_u64(uint64_t a, uint64_t b); + +uint8_t adi_api_utils_num_selected(uint32_t select_mask); + +uint8_t adi_api_utils_select_lsb_get(uint32_t select_mask); + +/** + * Convert uint64_t to byte array + */ + +/** + * @brief Convert uint64_t to byte array + * + * @param dest Destination array + * @param val Value to convert + */ +void adi_uint64_to_byte_array(uint8_t dest[], const uint64_t val); + +/** + * @brief Convert byte array to uint64_t + * + * @param src Source array + * @param val Converted value + */ +void adi_byte_array_to_uint64(uint8_t src[], uint64_t *val); + +/** + * \brief The decision logic looks for an expected value, i.e. series of consecutive 1’s, within the link table from lower to upper bound indexes. + * If a match is found, calculates the center index from the located series. + * + * + * \param link_table Value to search series of 1's within + * \param expected_val Value to look for, which is a series of 1's + * \param clk_adj_lower_bound Starting bit index for the search + * \param clk_adj_upper_bound Ending bit index for the search + * \param calc_clk_adj Center index of matching bit sequence + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_api_utils_check_consecutive_ones_bounded(uint16_t link_table, uint8_t expected_val, uint8_t clk_adj_lower_bound, uint8_t clk_adj_upper_bound, uint8_t *calc_clk_adj); + + + +#ifdef __cplusplus +} +#endif + +#endif /*__ADI_UTILS_H__*/ + +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/adi_utils/src/adi_utils.c b/drivers/iio/trx-rf/ad9088/adi_utils/src/adi_utils.c new file mode 100644 index 00000000000000..cb386edb7d94c7 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/adi_utils/src/adi_utils.c @@ -0,0 +1,495 @@ +/*! + * \brief API utility helper functions + * + * \version 0.1.x + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_UTILS + * @{ + */ + +/*============= I N C L U D E S ============*/ +#include "adi_utils.h" + +/*============= D E F I N E S ==============*/ +#define LOWER_16(A) (((A) & 0xffff)) +#define UPPER_16(A) (((A) >> 16) & 0xffff) +#define LOWER_32(A) (((A) & (uint32_t) 0xffffffff)) +#define U64MSB (0x8000000000000000ull) + +/*============= C O D E ====================*/ +int32_t adi_api_utils_gcd(int32_t u, int32_t v) +{ + int32_t t; + while (v != 0) { + t = u; + u = v; + v = t % v; + } + return u < 0 ? -u : u; /* abs(u) */ +} + +uint64_t adi_api_utils_gcd_64(uint64_t u, uint64_t v) +{ + uint64_t t; + while (v != 0) { + t = u; + u = v; +#ifdef __KERNEL__ + div64_u64_rem(t, v, &v); +#else + v = t % v; +#endif + } + return u; +} + +uint32_t adi_api_utils_lcm(uint32_t p, uint32_t q) +{ + uint32_t gcd, lcm, i, min_p_q; + + if (p == 0 || q == 0) { + return 0; + } + + min_p_q = (p <= q) ? p : q; + + i = min_p_q; + while (i > 0) { + if (p % i == 0 && q % i == 0) { + gcd = i; + break; + } + i--; + } + + lcm = (p * q) / gcd; + return lcm; +} + + +uint64_t adi_api_utils_lcm_64(uint64_t p, uint64_t q) +{ + uint64_t gcd, lcm, i, min_p_q; +#ifdef __KERNEL__ + uint64_t p_mod_i, q_mod_i; +#endif + min_p_q = (p <= q) ? p : q; + + i = min_p_q; + while (i > 0) { +#ifdef __KERNEL__ + div64_u64_rem(p, i, &p_mod_i); + div64_u64_rem(q, i, &q_mod_i); + + if (p_mod_i == 0 && q_mod_i == 0) { + gcd = i; + break; + } +#else + if (p % i == 0 && q % i == 0) { + gcd = i; + break; + } +#endif + i--; + } + +#ifdef __KERNEL__ + lcm = div64_u64(p * q, gcd); +#else + lcm = (p * q) / gcd; +#endif + return lcm; +} + +int32_t adi_api_utils_is_power_of_two(uint64_t x) +{ + return ((x != 0) && !(x & (x - 1))); +} + +void adi_api_utils_mult_64(uint32_t a, uint32_t b, uint32_t *hi, uint32_t *lo) +{ + uint32_t ah = a >> 16, + al = a & 0xffff, + bh = b >> 16, + bl = b & 0xffff, + rh = ah * bh, + rl = al * bl, + rm1 = ah * bl, + rm2 = al * bh, + rm1h = rm1 >> 16, + rm2h = rm2 >> 16, + rm1l = rm1 & 0xffff, + rm2l = rm2 & 0xffff, + rmh = rm1h + rm2h, + rml = rm1l + rm2l, + c = ((rl >> 16) + rml) >> 16; + rl = rl + (rml << 16); + rh = rh + rmh + c; + *lo = rl; + *hi = rh; +} + +void adi_api_utils_lshift_128(uint64_t *hi, uint64_t *lo) +{ + *hi <<= 1; + if (*lo & U64MSB) + { + *hi |= 1ul; + } + *lo <<= 1; +} + +void adi_api_utils_rshift_128(uint64_t *hi, uint64_t *lo) +{ + *lo >>= 1; + if (*hi & 1u) { + *lo |= U64MSB; + } + *hi >>= 1; +} + +void adi_api_utils_mult_128(uint64_t a, uint64_t b, uint64_t *hi, uint64_t *lo) +{ + uint64_t ah = a >> 32, + al = a & 0xffffffff, + bh = b >> 32, + bl = b & 0xffffffff, + rh = ah * bh, + rl = al * bl, + rm1 = ah * bl, + rm2 = al * bh, + rm1h = rm1 >> 32, + rm2h = rm2 >> 32, + rm1l = rm1 & 0xffffffff, + rm2l = rm2 & 0xffffffff, + rmh = rm1h + rm2h, + rml = rm1l + rm2l, + c = ((rl >> 32) + rml) >> 32; + rl = rl + (rml << 32); + rh = rh + rmh + c; + *lo = rl; + *hi = rh; +} + +void adi_api_utils_div_128(uint64_t a_hi, uint64_t a_lo, uint64_t b_hi, uint64_t b_lo, + uint64_t *hi, uint64_t *lo) +{ + uint64_t remain_lo = a_lo; /* The left-hand side of division, i.e. what is being divided */ + uint64_t remain_hi = a_hi; /* The left-hand side of division, i.e. what is being divided */ + uint64_t part1_lo = b_lo; /* The right-hand side of division */ + uint64_t part1_hi = b_hi; /* The right-hand side of division */ + uint64_t result_lo = 0; + uint64_t result_hi = 0; + uint64_t mask_lo = 1; + uint64_t mask_hi = 0; + + if ((part1_lo == 0) && (part1_hi == 0)) { + /* Do whatever should happen when dividing by zero. */ + return; + } + + /* while(part1_lo < remain_lo) + * Alternative: while(!(part1 & 0x8000)) - For 16-bit, test highest order bit. + * Alternative: while(not_signed(part1)) - Same as above: As long as sign bit is not set in part1. + */ + while (!(part1_hi & U64MSB)) { + adi_api_utils_lshift_128(&part1_hi, &part1_lo); + adi_api_utils_lshift_128(&mask_hi, &mask_lo); + } + + do { + if ((remain_hi > part1_hi) || ((remain_hi == part1_hi) && (remain_lo >= part1_lo))) { + /* remain_lo = remain_lo - part1_lo */ + adi_api_utils_subt_128(remain_hi, remain_lo, part1_hi, part1_lo, &remain_hi, &remain_lo); + /* result = result + mask */ + adi_api_utils_add_128(result_hi, result_lo, mask_hi, mask_lo, &result_hi, &result_lo); + } + adi_api_utils_rshift_128(&part1_hi, &part1_lo); /* part1 = part1 >> 1 */ + adi_api_utils_rshift_128(&mask_hi, &mask_lo); /* mask = mask >> 1 */ + } while ((mask_hi != 0) || (mask_lo != 0)); + + /* result = division result (quotient) */ + /* remain_lo = division remain_loder (modulo) */ + *lo = result_lo; + *hi = result_hi; +} + +void adi_api_utils_mod_128(uint64_t ah, uint64_t al, uint64_t div, uint64_t *mod) +{ + uint64_t result = 0; + uint64_t a; + +#ifdef __KERNEL__ + div64_u64_rem(~0, div, &a); + a += 1; + div64_u64_rem(ah, div, &ah); +#else + a = (~0 % div) + 1; + ah %= div; +#endif + + /*modular multiplication of (2^64*upper) % div*/ + while (ah != 0) { + if ( (ah & 1) == 1) { + result += a; + if(result >= div) { + result -= div; + } + } + a <<= 1; + if(a >= div) { + a -= div; + } + ah >>= 1; + } + + /* add up the 2 results and return the modulus*/ + if (al > div) { + al -= div; + } + +#ifdef __KERNEL__ + div64_u64_rem(al + result, div, mod); +#else + *mod = (al + result) % div; +#endif +} + +void adi_api_utils_add_128(uint64_t ah, uint64_t al, uint64_t bh, uint64_t bl, + uint64_t *hi, uint64_t *lo) +{ + /* r = a + b */ + uint64_t rl, rh; + rl = al + bl; + rh = ah + bh; + + if (rl < al) + { + rh++; + } + + *lo = rl; + *hi = rh; +} + +void adi_api_utils_subt_128(uint64_t ah, uint64_t al, uint64_t bh, uint64_t bl, + uint64_t *hi, uint64_t *lo) +{ + /* r = a - b */ + uint64_t rl, rh; + if (bl <= al) { + rl = al - bl; + rh = ah - bh; + } else { + rl = bl - al - 1; + rl = 0xFFFFFFFFFFFFFFFFll - rl; + ah--; + rh = ah - bh; + } + + *lo = rl; + *hi = rh; +} + +uint8_t adi_api_utils_num_selected(uint32_t select_mask) +{ + int sel_cnt = 0; + while (select_mask) { + sel_cnt += select_mask & 1; + select_mask = select_mask >> 1; + } + return sel_cnt; +} + +uint8_t adi_api_utils_select_lsb_get(uint32_t select_mask) +{ + uint8_t index = 0; + if (select_mask == 0) { + return 255; + } + while ((select_mask & 1) == 0) { + index++; + select_mask = select_mask >> 1; + } + return index; +} + +void adi_uint64_to_byte_array(uint8_t dest[], const uint64_t val) +{ + uint32_t offset = 0; + uint32_t endian_test_val = 0x11223344; + uint8_t is_lit_endian = (*(uint8_t *)&endian_test_val == 0x44); + + /* Little endian */ + if (is_lit_endian) { + dest[offset++] = (uint8_t)(val); + dest[offset++] = (uint8_t)(val >> 8); + dest[offset++] = (uint8_t)(val >> 16); + dest[offset++] = (uint8_t)(val >> 24); + dest[offset++] = (uint8_t)(val >> 32); + dest[offset++] = (uint8_t)(val >> 40); + dest[offset++] = (uint8_t)(val >> 48); + dest[offset++] = (uint8_t)(val >> 56); + } else { + offset = 7; + dest[offset--] = (uint8_t)(val); + dest[offset--] = (uint8_t)(val >> 8); + dest[offset--] = (uint8_t)(val >> 16); + dest[offset--] = (uint8_t)(val >> 24); + dest[offset--] = (uint8_t)(val >> 32); + dest[offset--] = (uint8_t)(val >> 40); + dest[offset--] = (uint8_t)(val >> 48); + dest[offset--] = (uint8_t)(val >> 56); + } +} + +void adi_byte_array_to_uint64(uint8_t src[], uint64_t *val) +{ + uint32_t offset = 0; + uint32_t endian_test_val = 0x11223344; + uint8_t is_lit_endian = (*(uint8_t *)&endian_test_val == 0x44); + + uint8_t *val_ptr = (uint8_t *) val; + + if (is_lit_endian) { + val_ptr[0] = src[offset++]; + val_ptr[1] = src[offset++]; + val_ptr[2] = src[offset++]; + val_ptr[3] = src[offset++]; + val_ptr[4] = src[offset++]; + val_ptr[5] = src[offset++]; + val_ptr[6] = src[offset++]; + val_ptr[7] = src[offset++]; + } else { + offset = 7; + val_ptr[0] = src[offset--]; + val_ptr[1] = src[offset--]; + val_ptr[2] = src[offset--]; + val_ptr[3] = src[offset--]; + val_ptr[4] = src[offset--]; + val_ptr[5] = src[offset--]; + val_ptr[6] = src[offset--]; + val_ptr[7] = src[offset--]; + } +} + +int32_t adi_api_utils_ratio_decomposition(uint64_t ratio_num, uint64_t ratio_den, uint8_t bit_size, uint64_t *x, uint64_t *a, uint64_t *b) { + uint64_t gcd, n, mh, ml, xh, xl; // ratio = m/n + uint64_t y; + + if (ratio_den == 0 || bit_size >= 64 || ratio_num > ratio_den) { + return -1; + } + + gcd = adi_api_utils_gcd_64(ratio_num, ratio_den); + +#ifdef __KERNEL__ + n = div64_u64(ratio_den, gcd); + adi_api_utils_mult_128(div64_u64(ratio_num, gcd),(1ull << bit_size), &mh, &ml); +#else + n = ratio_den/gcd; + adi_api_utils_mult_128(ratio_num/gcd,(1ull << bit_size), &mh, &ml); +#endif + + adi_api_utils_div_128(mh, ml, 0, n, &xh, &xl); + adi_api_utils_mod_128(mh, ml, n, &y); + + if (xh > 0) { + return -1; + } + + gcd = adi_api_utils_gcd_64(y, n); + + *x = xl; +#ifdef __KERNEL__ + *a = div64_u64(y, gcd); + *b = div64_u64(n, gcd); +#else + *a = y / gcd; + *b = n / gcd; +#endif + return 0; +} + +int32_t adi_api_utils_ratio_composition(uint64_t x, uint64_t a, uint64_t b, uint32_t *ratio_num, uint32_t *ratio_den, uint8_t bit_size) +{ + + uint64_t mh, ml, ah, al, xh, xl, gcd; + + if (b == 0 || bit_size >= 64) { + return -1; + } + + adi_api_utils_mult_128(x, b, &mh, &ml); + adi_api_utils_add_128(mh, ml, 0, a, &ah, &al); + while ((al & (0xFFFFFFFFFFFFFFFF >> (64 - bit_size))) != 0ull) { + adi_api_utils_lshift_128(&ah, &al); + b = b << 1; + } + + adi_api_utils_div_128(ah, al, 0, (1ull << bit_size), &xh, &xl); + + if (xh > 0) { + return -1; + } + + gcd = adi_api_utils_gcd_64(xl, b); + +#ifdef __KERNEL__ + *ratio_num = div64_u64(xl, gcd); + *ratio_den = div64_u64(b, gcd); +#else + *ratio_num = xl / gcd; + *ratio_den = b / gcd; +#endif + + return 0; + +} + +uint64_t adi_api_utils_div_floor_u64(uint64_t a, uint64_t b) { + +#ifdef __KERNEL__ + return div64_u64(a, b); +#else + return ((a) / (b)); +#endif +} + +uint64_t adi_api_utils_div_ceil_u64(uint64_t a, uint64_t b) { + +#ifdef __KERNEL__ + return DIV64_U64_ROUND_UP(a, b); +#else + return ((a) / (b)) + ((a) % (b) != 0); +#endif +} + +int32_t adi_api_utils_check_consecutive_ones_bounded(uint16_t link_table, uint8_t expected_val, uint8_t clk_adj_lower_bound, uint8_t clk_adj_upper_bound, uint8_t *calc_clk_adj) +{ + uint16_t link_table_shifted = 0; + uint8_t bit_shift = 0; + uint8_t i = 0; + + for (i = clk_adj_lower_bound; i <= clk_adj_upper_bound; ++i) { + link_table_shifted = (link_table >> bit_shift) & expected_val; + + if (link_table_shifted == expected_val) { + *calc_clk_adj = i; + return API_CMS_ERROR_OK; + } + bit_shift++; + } + return API_CMS_ERROR_ERROR; +} + +/*! @} */ + diff --git a/drivers/iio/trx-rf/ad9088/private/inc/adi_apollo_private_blk_sel.h b/drivers/iio/trx-rf/ad9088/private/inc/adi_apollo_private_blk_sel.h new file mode 100644 index 00000000000000..8fcba3ae80a910 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/adi_apollo_private_blk_sel.h @@ -0,0 +1,44 @@ +/*! + * \brief API private block select header file + * + * \copyright copyright(c) 2024 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_PRIVATE_DEVICE + * @{ + */ +#ifndef __ADI_APOLLO_PRIVATE_BLK_SEL_H__ +#define __ADI_APOLLO_PRIVATE_BLK_SEL_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_common.h" + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef CLIENT_IGNORE + +/** + * \brief Sets the block sel mask for each feature set. Called at open, depends on 4t4r/8t8r. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_private_blk_sel_mask_set(adi_apollo_device_t *device); + +#endif /* CLIENT_IGNORE*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_PRIVATE_BLK_SEL_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/adi_apollo_private_blk_sel_types.h b/drivers/iio/trx-rf/ad9088/private/inc/adi_apollo_private_blk_sel_types.h new file mode 100644 index 00000000000000..1a5422a4788207 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/adi_apollo_private_blk_sel_types.h @@ -0,0 +1,38 @@ +/*! + * \brief API private block select types header file + * + * \copyright copyright(c) 2024 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_PRIVATE_DEVICE + * @{ + */ +#ifndef __ADI_APOLLO_PRIVATE_BLK_SEL_TYPES_H__ +#define __ADI_APOLLO_PRIVATE_BLK_SEL_TYPES_H__ + +/*============= I N C L U D E S ============*/ + +#define ADI_APOLLO_ADC_BLK_SEL_MASK(sel) (sel) = (device->dev_info.blk_sel_mask.adc & (sel)) +#define ADI_APOLLO_BMEM_BLK_SEL_MASK(sel) (sel) = (device->dev_info.blk_sel_mask.bmem & (sel)) +#define ADI_APOLLO_DAC_BLK_SEL_MASK(sel) (sel) = (device->dev_info.blk_sel_mask.dac & (sel)) +#define ADI_APOLLO_CDDC_BLK_SEL_MASK(sel) (sel) = (device->dev_info.blk_sel_mask.cddc & (sel)) +#define ADI_APOLLO_CDUC_BLK_SEL_MASK(sel) (sel) = (device->dev_info.blk_sel_mask.cduc & (sel)) +#define ADI_APOLLO_CFIR_BLK_SEL_MASK(sel) (sel) = (device->dev_info.blk_sel_mask.cfir & (sel)) +#define ADI_APOLLO_CNCO_BLK_SEL_MASK(sel) (sel) = (device->dev_info.blk_sel_mask.cnco & (sel)) +#define ADI_APOLLO_FDDC_BLK_SEL_MASK(sel) (sel) = (device->dev_info.blk_sel_mask.fddc & (sel)) +#define ADI_APOLLO_FDUC_BLK_SEL_MASK(sel) (sel) = (device->dev_info.blk_sel_mask.fduc & (sel)) +#define ADI_APOLLO_FSRC_BLK_SEL_MASK(sel) (sel) = (device->dev_info.blk_sel_mask.fsrc & (sel)) +#define ADI_APOLLO_FNCO_BLK_SEL_MASK(sel) (sel) = (device->dev_info.blk_sel_mask.fnco & (sel)) +#define ADI_APOLLO_INVSINC_BLK_SEL_MASK(sel) (sel) = (device->dev_info.blk_sel_mask.invsinc & (sel)) +#define ADI_APOLLO_PFILT_BLK_SEL_MASK(sel) (sel) = (device->dev_info.blk_sel_mask.pfilt & (sel)) +#define ADI_APOLLO_RXEN_BLK_SEL_MASK(sel) (sel) = (device->dev_info.blk_sel_mask.rxen & (sel)) +#define ADI_APOLLO_TXEN_BLK_SEL_MASK(sel) (sel) = (device->dev_info.blk_sel_mask.txen & (sel)) +#define ADI_APOLLO_SMON_BLK_SEL_MASK(sel) (sel) = (device->dev_info.blk_sel_mask.smon & (sel)) +#define ADI_APOLLO_SNIFFER_BLK_SEL_MASK(sel) (sel) = (device->dev_info.blk_sel_mask.sniffer & (sel)) + +#endif /* __ADI_APOLLO_PRIVATE_BLK_SEL_TYPES_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/adi_apollo_private_bmem.h b/drivers/iio/trx-rf/ad9088/private/inc/adi_apollo_private_bmem.h new file mode 100644 index 00000000000000..48abf10befe6ad --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/adi_apollo_private_bmem.h @@ -0,0 +1,223 @@ +/*! + * \brief BMEM Block definition headers + * + * \copyright copyright(c) 2024 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_BMEM + * @{ + */ +#ifndef __ADI_APOLLO_PRIVATE_BMEM_H__ +#define __ADI_APOLLO_PRIVATE_BMEM_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_bmem_types.h" + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef CLIENT_IGNORE + +/** + * \brief Sets BMEM sample delay + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] bmem_loc Which BMEM location to target \ref adi_apollo_bmem_loc_e + * \param[in] bmems Target BMEM \ref adi_apollo_bmem_sel_e + * \param[in] sample_delay Sample delay + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_private_bmem_delay_sample_set(adi_apollo_device_t *device, adi_apollo_bmem_loc_e bmem_loc, adi_apollo_blk_sel_t bmems, uint16_t sample_delay); + +/** + * \brief Sets BMEM delay for the 4 hopping profiles + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] bmem_loc Which BMEM location to target \ref adi_apollo_bmem_loc_e + * \param[in] bmems Target BMEM \ref adi_apollo_bmem_sel_e + * \param[in] sample_delay Sample delay array - 4 elements + * \param[in] sample_delay_length Sample delay array length (must be 4) + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_private_bmem_delay_hop_set(adi_apollo_device_t *device, adi_apollo_bmem_loc_e bmem_loc, adi_apollo_blk_sel_t bmems, uint16_t sample_delay[], uint32_t sample_delay_length); + +/** + * \brief Configures BMEM to delay + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] bmem_loc Which BMEM location to target \ref adi_apollo_bmem_loc_e + * \param[in] bmems Target BMEM \ref adi_apollo_bmem_sel_e + * \param[in] config BMEM delay config \ref adi_apollo_bmem_delay_sample_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_private_bmem_delay_sample_config(adi_apollo_device_t *device, adi_apollo_bmem_loc_e bmem_loc, adi_apollo_blk_sel_t bmems, adi_apollo_bmem_delay_sample_t *config); + +/** + * \brief Configures BMEM to delay with hopping mode + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] bmem_loc Which BMEM location to target \ref adi_apollo_bmem_loc_e + * \param[in] bmems Target BMEM \ref adi_apollo_bmem_sel_e + * \param[in] config BMEM delay config \ref adi_apollo_bmem_delay_hop_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_private_bmem_delay_hop_config(adi_apollo_device_t *device, adi_apollo_bmem_loc_e bmem_loc, adi_apollo_blk_sel_t bmems, adi_apollo_bmem_delay_hop_t *config); + +/** + * \brief Starts BMEM sample delay + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] bmem_loc Which BMEM location to target \ref adi_apollo_bmem_loc_e + * \param[in] bmems Target BMEM \ref adi_apollo_bmem_sel_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_private_bmem_delay_start(adi_apollo_device_t *device, adi_apollo_bmem_loc_e bmem_loc, adi_apollo_blk_sel_t bmems); + +/** + * \brief Configures BMEM to Capture + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] bmem_loc Which BMEM location to target \ref adi_apollo_bmem_loc_e + * \param[in] bmems Target BMEM \ref adi_apollo_bmem_sel_e + * \param[in] config \ref adi_apollo_bmem_capture_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_private_bmem_capture_config(adi_apollo_device_t *device, adi_apollo_bmem_loc_e bmem_loc, adi_apollo_blk_sel_t bmems, adi_apollo_bmem_capture_t *config); + +/** + * \brief Runs normal BMEM capture + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] bmem_loc Which BMEM location to target \ref adi_apollo_bmem_loc_e + * \param[in] bmems Target BMEM \ref adi_apollo_bmem_sel_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_private_bmem_capture_run(adi_apollo_device_t *device, adi_apollo_bmem_loc_e bmem_loc, adi_apollo_blk_sel_t bmems); + +/** + * \brief Reads Rx BMEM SRAM. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] bmem_loc Which BMEM location to target \ref adi_apollo_bmem_loc_e + * \param[in] bmems Target BMEM \ref adi_apollo_bmem_sel_e + * \param[out] data Data that is read out of each \ref adi_apollo_bmem_sel_e. Each 32-bit word contains two 16-bit samples + * \param[in] length Number of 32-bit words to read. 64K max. + */ +int32_t adi_apollo_private_bmem_capture_get(adi_apollo_device_t *device, adi_apollo_bmem_loc_e bmem_loc, adi_apollo_blk_sel_t bmems, uint32_t data[], uint32_t length); + +/** + * \brief Configures BMEM to AWG + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] bmem_loc Which BMEM location to target \ref adi_apollo_bmem_loc_e + * \param[in] bmems Target BMEM \ref adi_apollo_bmem_sel_e + * \param[in] config \ref adi_apollo_bmem_awg_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_private_bmem_awg_config(adi_apollo_device_t *device, adi_apollo_bmem_loc_e bmem_loc, adi_apollo_blk_sel_t bmems, adi_apollo_bmem_awg_t *config); + +/** + * \brief Starts normal BMEM AWG in loop + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] bmem_loc Which BMEM location to target \ref adi_apollo_bmem_loc_e + * \param[in] bmems Target BMEM \ref adi_apollo_bmem_sel_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_private_bmem_awg_start(adi_apollo_device_t *device, adi_apollo_bmem_loc_e bmem_loc, adi_apollo_blk_sel_t bmems); + +/** + * \brief Stops normal BMEM AWG + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] bmem_loc Which BMEM location to target \ref adi_apollo_bmem_loc_e + * \param[in] bmems Target BMEM \ref adi_apollo_bmem_sel_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_private_bmem_awg_stop(adi_apollo_device_t *device, adi_apollo_bmem_loc_e bmem_loc, adi_apollo_blk_sel_t bmems); + +/** + * \brief Writes Rx BMEM SRAM. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] bmem_loc Which BMEM location to target \ref adi_apollo_bmem_loc_e + * \param[in] bmems Target BMEM \ref adi_apollo_bmem_sel_e + * \param[in] data Array of data to write. Each 32-bit word contains two 16-bit samples + * \param[in] length Number of 32-bit words to write. 64K max. + */ +int32_t adi_apollo_private_bmem_awg_sram_set(adi_apollo_device_t *device, adi_apollo_bmem_loc_e bmem_loc, adi_apollo_blk_sel_t bmems, uint32_t data[], uint32_t length); + +/** + * \brief Configures BMEM to AWG with 16-bit sample data. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] bmem_loc Which BMEM location to target \ref adi_apollo_bmem_loc_e + * \param[in] bmems Target BMEM \ref adi_apollo_bmem_sel_e + * \param[in] data16 Array of 16-bit data samples to play out of bmem awg. + * \param[in] data16_len Length of data array + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_private_bmem_awg_sample_write(adi_apollo_device_t *device, adi_apollo_bmem_loc_e bmem_loc, adi_apollo_blk_sel_t bmems, int16_t data16[], uint32_t data16_len); + +/** + * \brief Configures BMEM to AWG with 16-bit sample data for 8T8R devices + * + * \note + * For 8T8R devices, BMEM instances split the sram memory between ADC pairs (e.g. A0/A2). + * This results in half the number of samples per converter channel. + * + * This function requires a user provided scratch memory. Prevents exceeding local stack limits. + * Apollo APIs don't use dynamic memory allocation. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] bmem_loc Which BMEM location to target \ref adi_apollo_bmem_loc_e + * \param[in] bmems Target BMEM \ref adi_apollo_bmem_sel_e + * \param[in] data16_0 Array of 16-bit data samples to play out of bmem awg for first ADC in pair + * \param[in] data16_1 Array of 16-bit data samples to play out of bmem awg for second ADC in pair + * \param[in] data16_len Length of data16_0 and data16_1 arrays + * \param[in] scratch32 User provided 32-bit scratch array. Used by function to assemble data and write mem. + * \param[in] scratch32_len Length of scratch32 array + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_private_bmem_awg_sample_shared_write(adi_apollo_device_t *device, adi_apollo_bmem_loc_e bmem_loc, adi_apollo_blk_sel_t bmems, + int16_t data16_0[], int16_t data16_1[], uint32_t data16_len, + uint32_t scratch32[], uint32_t scratch32_len); + +#endif /* CLIENT_IGNORE*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_PRIVATE_BMEM_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/adi_apollo_private_device.h b/drivers/iio/trx-rf/ad9088/private/inc/adi_apollo_private_device.h new file mode 100644 index 00000000000000..773867f69d70b3 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/adi_apollo_private_device.h @@ -0,0 +1,67 @@ +/*! + * \brief API private device header file + * + * \copyright copyright(c) 2024 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_PRIVATE_DEVICE + * @{ + */ +#ifndef __ADI_APOLLO_PRIVATE_DEVICE_H__ +#define __ADI_APOLLO_PRIVATE_DEVICE_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_common.h" +#include "adi_apollo_private_device_types.h" + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef CLIENT_IGNORE + +/** + * \brief Configure HSCI Linkup using Manual Mode + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_private_device_hsci_manual_linkup_configure(adi_apollo_device_t *device); + +/** + * \brief Configure HSCI Linkup using Auto Mode + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_private_device_hsci_auto_linkup_configure(adi_apollo_device_t *device); + +/** + * \brief Returns lockout state of a device feature (1 = feature is locked out by device, 0 = feature avail) + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] feat Feature to test for lockout + * + * + * \return Lockout state. 1: Feature is locked out by device variant. 0: Feature is available + */ +uint8_t adi_apollo_private_device_lockout_get(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_private_device_feat_lockout_e feat); + +#endif /* CLIENT_IGNORE*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_PRIVATE_DEVICE_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/adi_apollo_private_device_types.h b/drivers/iio/trx-rf/ad9088/private/inc/adi_apollo_private_device_types.h new file mode 100644 index 00000000000000..37dd3c3a00db10 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/adi_apollo_private_device_types.h @@ -0,0 +1,47 @@ +/*! + * \brief API private device types header file + * + * \copyright copyright(c) 2024 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_PRIVATE_DEVICE + * @{ + */ +#ifndef __ADI_APOLLO_PRIVATE_DEVICE_TYPES_H__ +#define __ADI_APOLLO_PRIVATE_DEVICE_TYPES_H__ + +/*============= I N C L U D E S ============*/ + +/** +* \brief Device feature lockouts +*/ +typedef enum +{ + /* Rx and Tx terminals */ + ADI_APOLLO_EC_CONV_1X1X_LOCK = 0, /*! bit=1 lock out all Rx/Tx 1x-1x (raw data) modes. */ + ADI_APOLLO_EC_CONV_QC_LOCK = 1, /*! bit=1 lock out manual ADC JESD programming. */ + ADI_APOLLO_EC_CONV_LOCK = 2, /*! bit=1 force shut down all ADC channels. */ + ADI_APOLLO_EC_CONV_FFH_LOCK = 3, /*! bit=1 lock out ADC FFH. */ + ADI_APOLLO_EC_NLC_LOCK = 4, /*! bit=1 lock out Rx/Tx NLC. */ + ADI_APOLLO_EC_PFILT_LOCK = 5, /*! bit=1 lock out Rx/Tx PFILT. */ + ADI_APOLLO_EC_CFIR_LOCK = 6, /*! bit=1 lock out Rx/Tx CFIR. */ + ADI_APOLLO_EC_FSRC_LOCK = 7, /*! bit=1 lock out Rx/Tx FSRC. */ + ADI_APOLLO_EC_DYN_CFG_LOCK = 8, /*! bit=1 lock out Rx/Tx dynamic config. */ + ADI_APOLLO_EC_USR_LOCK = 9, /*! bit=1 lock out Rx/Tx USR. */ + ADI_APOLLO_EC_VSR_LOCK = 10, /*! bit=1 lock out Rx/Tx VSR. */ + ADI_APOLLO_EC_CDRC_LT8X_LOCK = 11, /*! bit=1 lock out all CDDC/CDUC ratios < 8x (1x, 2x, 3x, 4x, 6x). */ + + /* Rx terminal */ + ADI_APOLLO_EC_FFT_SPECTURMSNIFFER_LOCK = 12, /*! bit=1 lock out fft spectrum sniffer. */ + + /* Tx terminal */ + ADI_APOLLO_EC_LPBK0_LOCK = 12, /*! bit=1 lock out lpbk mode 0. */ + ADI_APOLLO_EC_LPBK123_LOCK = 13, /*! bit=1 lock out lpbk mode 1, 2, and 3. */ +} adi_apollo_private_device_feat_lockout_e; + +#endif /* __ADI_APOLLO_PRIVATE_DEVICE_TYPES_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/adi_apollo_private_sysclk_cond.h b/drivers/iio/trx-rf/ad9088/private/inc/adi_apollo_private_sysclk_cond.h new file mode 100644 index 00000000000000..8a3f865bf806bf --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/adi_apollo_private_sysclk_cond.h @@ -0,0 +1,41 @@ +/*! + * \brief: Apollo private system clock calibration functions + * + * \copyright copyright(c) 2023 Analog Devices, Inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated Analog Devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_SYSCLK_COND + * @{ + */ +#ifndef __ADI_APOLLO_PRIVATE_SYSCLK_COND_H__ +#define __ADI_APOLLO_PRIVATE_SYSCLK_COND_H__ + +#include "adi_apollo_sysclk_cond_types.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Sets the ADC clock conditioning firmware defaults. + * + * \note Should be called after firmware load and before device profile load. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] clk_cfg Pointer to \ref adi_apollo_clk_cfg_t used to determine CC defaults. + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_private_sysclk_cond_defaults_set(adi_apollo_device_t *device, adi_apollo_clk_cfg_t *clk_cfg); + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_PRIVATE_SYSCLK_COND_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_actrl_east_open.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_actrl_east_open.h new file mode 100644 index 00000000000000..ff4a7ca1ea2fef --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_actrl_east_open.h @@ -0,0 +1,1284 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:19 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_ACTRL_EAST_OPEN_H__ +#define __ADI_APOLLO_BF_ACTRL_EAST_OPEN_H__ + +/*============= D E F I N E S ==============*/ +#define VENUS_ACTRL_EAST_REGMAP_ADC8_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x60262800 +#define VENUS_ACTRL_EAST_REGMAP_ADC8_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x60462800 +#define VENUS_ACTRL_EAST_REGMAP_ADC8_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A62800 +#define VENUS_ACTRL_EAST_REGMAP_ADC8_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C62800 + +#define REG_ACTRL_SCRATCH_BEGIN_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000000) +#define BF_ACTRL_SCRATCH_BEGIN_ACTRL_EAST__OPEN_INFO(inst) ((inst) + 0x00000000), 0x00000800 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0001_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000001) +#define BF_BF_ACE00BAA_INFO(inst) ((inst) + 0x00000001), 0x00000100 +#define BF_BF_F62E7DB9_INFO(inst) ((inst) + 0x00000001), 0x00000101 +#define BF_BF_BF9A2608_INFO(inst) ((inst) + 0x00000001), 0x00000102 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0002_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000002) +#define BF_BF_92E841D6_INFO(inst) ((inst) + 0x00000002), 0x00000100 +#define BF_BF_3D0DBB97_INFO(inst) ((inst) + 0x00000002), 0x00000101 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0003_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000003) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0004_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000004) +#define BF_BF_BEE14B53_INFO(inst) ((inst) + 0x00000004), 0x00000100 +#define BF_BF_5730BA68_INFO(inst) ((inst) + 0x00000004), 0x00000101 +#define BF_BF_539CB8A7_INFO(inst) ((inst) + 0x00000004), 0x00000102 +#define BF_BF_B8B6E31D_INFO(inst) ((inst) + 0x00000004), 0x00000103 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0005_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000005) +#define BF_BF_1322B279_INFO(inst) ((inst) + 0x00000005), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0006_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000006) +#define BF_BF_743CADCA_INFO(inst) ((inst) + 0x00000006), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0007_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000007) +#define BF_BF_03A82045_INFO(inst) ((inst) + 0x00000007), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0008_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000008) +#define BF_BF_38ABEB20_INFO(inst) ((inst) + 0x00000008), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0009_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000009) +#define BF_BF_7CEDBF88_INFO(inst) ((inst) + 0x00000009), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X000A_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000000A) +#define BF_BF_BAB445BD_INFO(inst) ((inst) + 0x0000000A), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X000B_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000000B) +#define BF_BF_A7963CB3_INFO(inst) ((inst) + 0x0000000B), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X000C_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000000C) +#define BF_BF_CFE1765B_INFO(inst) ((inst) + 0x0000000C), 0x00000200 +#define BF_BF_EC6E7162_INFO(inst) ((inst) + 0x0000000C), 0x00000202 +#define BF_BF_2BA5C0FA_INFO(inst) ((inst) + 0x0000000C), 0x00000204 +#define BF_BF_D0E1FA60_INFO(inst) ((inst) + 0x0000000C), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X000D_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000000D) +#define BF_BF_57356264_INFO(inst) ((inst) + 0x0000000D), 0x00000200 +#define BF_BF_288D3CEE_INFO(inst) ((inst) + 0x0000000D), 0x00000202 +#define BF_BF_307A9467_INFO(inst) ((inst) + 0x0000000D), 0x00000204 +#define BF_BF_D8A978DA_INFO(inst) ((inst) + 0x0000000D), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X000E_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000000E) +#define BF_BF_D3D1EB46_INFO(inst) ((inst) + 0x0000000E), 0x00000300 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X000F_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000000F) +#define BF_BF_16A32022_INFO(inst) ((inst) + 0x0000000F), 0x00000200 +#define BF_BF_C9BC413E_INFO(inst) ((inst) + 0x0000000F), 0x00000202 +#define BF_BF_8248D837_INFO(inst) ((inst) + 0x0000000F), 0x00000204 +#define BF_BF_ED5B6FF6_INFO(inst) ((inst) + 0x0000000F), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0010_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000010) +#define BF_BF_5A05B140_INFO(inst) ((inst) + 0x00000010), 0x00000200 +#define BF_BF_0E866118_INFO(inst) ((inst) + 0x00000010), 0x00000202 +#define BF_BF_A825D579_INFO(inst) ((inst) + 0x00000010), 0x00000204 +#define BF_BF_0347B9EA_INFO(inst) ((inst) + 0x00000010), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0011_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000011) +#define BF_BF_37729898_INFO(inst) ((inst) + 0x00000011), 0x00000300 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0012_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000012) +#define BF_BF_59991ED3_INFO(inst) ((inst) + 0x00000012), 0x00000200 +#define BF_BF_90039DED_INFO(inst) ((inst) + 0x00000012), 0x00000202 +#define BF_BF_A0BD92C7_INFO(inst) ((inst) + 0x00000012), 0x00000204 +#define BF_BF_B7372F28_INFO(inst) ((inst) + 0x00000012), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0013_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000013) +#define BF_BF_354A1DB4_INFO(inst) ((inst) + 0x00000013), 0x00000200 +#define BF_BF_ECF1C1DF_INFO(inst) ((inst) + 0x00000013), 0x00000202 +#define BF_BF_9877306D_INFO(inst) ((inst) + 0x00000013), 0x00000204 +#define BF_BF_6DACC9C0_INFO(inst) ((inst) + 0x00000013), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0014_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000014) +#define BF_BF_9FA63423_INFO(inst) ((inst) + 0x00000014), 0x00000300 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0015_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000015) +#define BF_BF_9BF98EFF_INFO(inst) ((inst) + 0x00000015), 0x00000200 +#define BF_BF_B65ED02F_INFO(inst) ((inst) + 0x00000015), 0x00000202 +#define BF_BF_4E171ADD_INFO(inst) ((inst) + 0x00000015), 0x00000204 +#define BF_BF_26E0A67C_INFO(inst) ((inst) + 0x00000015), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0016_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000016) +#define BF_BF_D3BA083C_INFO(inst) ((inst) + 0x00000016), 0x00000200 +#define BF_BF_C0E8E123_INFO(inst) ((inst) + 0x00000016), 0x00000202 +#define BF_BF_0B70C8C8_INFO(inst) ((inst) + 0x00000016), 0x00000204 +#define BF_BF_CAB57CCA_INFO(inst) ((inst) + 0x00000016), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0017_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000017) +#define BF_BF_92522375_INFO(inst) ((inst) + 0x00000017), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0018_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000018) +#define BF_BF_93BD1868_INFO(inst) ((inst) + 0x00000018), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0019_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000019) +#define BF_BF_FFFA6B56_INFO(inst) ((inst) + 0x00000019), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X001A_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000001A) +#define BF_BF_4D8D848C_INFO(inst) ((inst) + 0x0000001A), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X001B_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000001B) +#define BF_BF_B25CABA3_INFO(inst) ((inst) + 0x0000001B), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X001C_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000001C) +#define BF_BF_23232F4E_INFO(inst) ((inst) + 0x0000001C), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X001D_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000001D) +#define BF_BF_D767B532_INFO(inst) ((inst) + 0x0000001D), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X001E_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000001E) +#define BF_BF_1CD7B017_INFO(inst) ((inst) + 0x0000001E), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X001F_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000001F) +#define BF_BF_16E15371_INFO(inst) ((inst) + 0x0000001F), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0020_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000020) +#define BF_BF_41267477_INFO(inst) ((inst) + 0x00000020), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0021_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000021) +#define BF_BF_478F8D2C_INFO(inst) ((inst) + 0x00000021), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0022_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000022) +#define BF_BF_099AE646_INFO(inst) ((inst) + 0x00000022), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0023_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000023) +#define BF_BF_232FA1F1_INFO(inst) ((inst) + 0x00000023), 0x00000400 +#define BF_BF_6CC9581E_INFO(inst) ((inst) + 0x00000023), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0024_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000024) +#define BF_BF_E7B0BAD2_INFO(inst) ((inst) + 0x00000024), 0x00000400 +#define BF_BF_6BE57A35_INFO(inst) ((inst) + 0x00000024), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0025_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000025) +#define BF_BF_3E67A859_INFO(inst) ((inst) + 0x00000025), 0x00000200 +#define BF_BF_367F3FFC_INFO(inst) ((inst) + 0x00000025), 0x00000202 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0026_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000026) +#define BF_BF_1778EDD1_INFO(inst) ((inst) + 0x00000026), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0027_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000027) +#define BF_BF_7DD4FA6D_INFO(inst) ((inst) + 0x00000027), 0x00000200 +#define BF_BF_FD32EB34_INFO(inst) ((inst) + 0x00000027), 0x00000202 +#define BF_BF_3F98E934_INFO(inst) ((inst) + 0x00000027), 0x00000204 +#define BF_BF_AE605C1A_INFO(inst) ((inst) + 0x00000027), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0028_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000028) +#define BF_BF_BD6EDB40_INFO(inst) ((inst) + 0x00000028), 0x00000200 +#define BF_BF_D601DE4D_INFO(inst) ((inst) + 0x00000028), 0x00000202 +#define BF_BF_D57EE75D_INFO(inst) ((inst) + 0x00000028), 0x00000204 +#define BF_BF_9804BF21_INFO(inst) ((inst) + 0x00000028), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0029_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000029) +#define BF_BF_099B2AB5_INFO(inst) ((inst) + 0x00000029), 0x00000300 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X002A_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000002A) +#define BF_BF_C8EB6F3A_INFO(inst) ((inst) + 0x0000002A), 0x00000200 +#define BF_BF_E92E44A4_INFO(inst) ((inst) + 0x0000002A), 0x00000202 +#define BF_BF_132F4A77_INFO(inst) ((inst) + 0x0000002A), 0x00000204 +#define BF_BF_5C9D23E4_INFO(inst) ((inst) + 0x0000002A), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X002B_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000002B) +#define BF_BF_D67CE5B6_INFO(inst) ((inst) + 0x0000002B), 0x00000200 +#define BF_BF_2A35EF2C_INFO(inst) ((inst) + 0x0000002B), 0x00000202 +#define BF_BF_4AD20DF5_INFO(inst) ((inst) + 0x0000002B), 0x00000204 +#define BF_BF_4C32E642_INFO(inst) ((inst) + 0x0000002B), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X002C_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000002C) +#define BF_BF_DB0AFA1A_INFO(inst) ((inst) + 0x0000002C), 0x00000300 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X002D_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000002D) +#define BF_BF_D76B26F4_INFO(inst) ((inst) + 0x0000002D), 0x00000200 +#define BF_BF_48E4F2CA_INFO(inst) ((inst) + 0x0000002D), 0x00000202 +#define BF_BF_CFD1F7FB_INFO(inst) ((inst) + 0x0000002D), 0x00000204 +#define BF_BF_4324395D_INFO(inst) ((inst) + 0x0000002D), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X002E_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000002E) +#define BF_BF_521409C9_INFO(inst) ((inst) + 0x0000002E), 0x00000200 +#define BF_BF_7332F034_INFO(inst) ((inst) + 0x0000002E), 0x00000202 +#define BF_BF_FA0EEF3B_INFO(inst) ((inst) + 0x0000002E), 0x00000204 +#define BF_BF_3C853C06_INFO(inst) ((inst) + 0x0000002E), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X002F_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000002F) +#define BF_BF_6018961B_INFO(inst) ((inst) + 0x0000002F), 0x00000300 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0030_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000030) +#define BF_BF_CCFDED14_INFO(inst) ((inst) + 0x00000030), 0x00000200 +#define BF_BF_10C7489C_INFO(inst) ((inst) + 0x00000030), 0x00000202 +#define BF_BF_9C1ADB8C_INFO(inst) ((inst) + 0x00000030), 0x00000204 +#define BF_BF_C87D10FC_INFO(inst) ((inst) + 0x00000030), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0031_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000031) +#define BF_BF_18172696_INFO(inst) ((inst) + 0x00000031), 0x00000200 +#define BF_BF_2DFC91BB_INFO(inst) ((inst) + 0x00000031), 0x00000202 +#define BF_BF_8EB2FD62_INFO(inst) ((inst) + 0x00000031), 0x00000204 +#define BF_BF_CFFE1EE3_INFO(inst) ((inst) + 0x00000031), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0032_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000032) +#define BF_BF_1666C213_INFO(inst) ((inst) + 0x00000032), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0033_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000033) +#define BF_BF_2CCC2627_INFO(inst) ((inst) + 0x00000033), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0034_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000034) +#define BF_BF_EE79C5DA_INFO(inst) ((inst) + 0x00000034), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0035_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000035) +#define BF_BF_0002493D_INFO(inst) ((inst) + 0x00000035), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0036_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000036) +#define BF_BF_FBEFEBA4_INFO(inst) ((inst) + 0x00000036), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0037_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000037) +#define BF_BF_9C6FAD25_INFO(inst) ((inst) + 0x00000037), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0038_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000038) +#define BF_BF_ACCEBE08_INFO(inst) ((inst) + 0x00000038), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0039_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000039) +#define BF_BF_2A9AA610_INFO(inst) ((inst) + 0x00000039), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X003A_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000003A) +#define BF_BF_44A67BB6_INFO(inst) ((inst) + 0x0000003A), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X003B_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000003B) +#define BF_BF_513CF369_INFO(inst) ((inst) + 0x0000003B), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X003C_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000003C) +#define BF_BF_C4425C14_INFO(inst) ((inst) + 0x0000003C), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X003D_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000003D) +#define BF_BF_F1160BDC_INFO(inst) ((inst) + 0x0000003D), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X003E_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000003E) +#define BF_BF_38FF8611_INFO(inst) ((inst) + 0x0000003E), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X003F_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000003F) +#define BF_BF_0D88F8BD_INFO(inst) ((inst) + 0x0000003F), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0040_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000040) +#define BF_BF_A3AE5F94_INFO(inst) ((inst) + 0x00000040), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0041_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000041) +#define BF_BF_720B66B2_INFO(inst) ((inst) + 0x00000041), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0042_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000042) +#define BF_BF_1DC05849_INFO(inst) ((inst) + 0x00000042), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0043_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000043) +#define BF_BF_F3E48A9F_INFO(inst) ((inst) + 0x00000043), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0044_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000044) +#define BF_BF_9C72BF80_INFO(inst) ((inst) + 0x00000044), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0045_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000045) +#define BF_BF_371BC3D9_INFO(inst) ((inst) + 0x00000045), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0046_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000046) +#define BF_BF_84C7F523_INFO(inst) ((inst) + 0x00000046), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0047_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000047) +#define BF_BF_CDEC9799_INFO(inst) ((inst) + 0x00000047), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0048_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000048) +#define BF_BF_877C054C_INFO(inst) ((inst) + 0x00000048), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0049_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000049) +#define BF_BF_98B439B8_INFO(inst) ((inst) + 0x00000049), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X004A_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000004A) +#define BF_BF_0AF985D6_INFO(inst) ((inst) + 0x0000004A), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X004B_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000004B) +#define BF_BF_7D6985F5_INFO(inst) ((inst) + 0x0000004B), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X004C_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000004C) +#define BF_BF_45667D8B_INFO(inst) ((inst) + 0x0000004C), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X004D_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000004D) +#define BF_BF_7C4891D6_INFO(inst) ((inst) + 0x0000004D), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X004E_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000004E) +#define BF_BF_8A478BE8_INFO(inst) ((inst) + 0x0000004E), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X004F_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000004F) +#define BF_BF_C0757DBA_INFO(inst) ((inst) + 0x0000004F), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0050_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000050) +#define BF_BF_CF2E4B89_INFO(inst) ((inst) + 0x00000050), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0051_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000051) +#define BF_BF_DF0DE648_INFO(inst) ((inst) + 0x00000051), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0052_ADDR(inst) ((inst) + 0x00000052) +#define BF_BF_45A23508_INFO(inst) ((inst) + 0x00000052), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0053_ADDR(inst) ((inst) + 0x00000053) +#define BF_BF_8E333615_INFO(inst) ((inst) + 0x00000053), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0054_ADDR(inst) ((inst) + 0x00000054) +#define BF_BF_A3AE602E_INFO(inst) ((inst) + 0x00000054), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0055_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000055) +#define BF_BF_18C49AB2_INFO(inst) ((inst) + 0x00000055), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0056_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000056) +#define BF_BF_D9D08B8B_INFO(inst) ((inst) + 0x00000056), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0057_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000057) +#define BF_BF_87BA41E5_INFO(inst) ((inst) + 0x00000057), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0058_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000058) +#define BF_BF_30F4026F_INFO(inst) ((inst) + 0x00000058), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0059_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000059) +#define BF_BF_EB780239_INFO(inst) ((inst) + 0x00000059), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X005A_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000005A) +#define BF_BF_6D3A1240_INFO(inst) ((inst) + 0x0000005A), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X005B_ADDR(inst) ((inst) + 0x0000005B) +#define BF_BF_B5FBA87A_INFO(inst) ((inst) + 0x0000005B), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X005C_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000005C) +#define BF_BF_E4DB5572_INFO(inst) ((inst) + 0x0000005C), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X005D_ADDR(inst) ((inst) + 0x0000005D) +#define BF_BF_B944F982_INFO(inst) ((inst) + 0x0000005D), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X005E_ADDR(inst) ((inst) + 0x0000005E) +#define BF_BF_2F992B0E_INFO(inst) ((inst) + 0x0000005E), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X005F_ADDR(inst) ((inst) + 0x0000005F) +#define BF_BF_8A83AEB6_INFO(inst) ((inst) + 0x0000005F), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0060_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000060) +#define BF_BF_FB47E055_INFO(inst) ((inst) + 0x00000060), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0061_ADDR(inst) ((inst) + 0x00000061) +#define BF_BF_57432FC6_INFO(inst) ((inst) + 0x00000061), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0062_ADDR(inst) ((inst) + 0x00000062) +#define BF_BF_56B1DB56_INFO(inst) ((inst) + 0x00000062), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0063_ADDR(inst) ((inst) + 0x00000063) +#define BF_BF_9AA13BCE_INFO(inst) ((inst) + 0x00000063), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0064_ADDR(inst) ((inst) + 0x00000064) +#define BF_BF_2039935D_INFO(inst) ((inst) + 0x00000064), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0065_ADDR(inst) ((inst) + 0x00000065) +#define BF_BF_50F1DE26_INFO(inst) ((inst) + 0x00000065), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0066_ADDR(inst) ((inst) + 0x00000066) +#define BF_BF_CB662E54_INFO(inst) ((inst) + 0x00000066), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0067_ADDR(inst) ((inst) + 0x00000067) +#define BF_BF_0E763A37_INFO(inst) ((inst) + 0x00000067), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0068_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000068) +#define BF_BF_3FEEC273_INFO(inst) ((inst) + 0x00000068), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0069_ADDR(inst) ((inst) + 0x00000069) +#define BF_BF_086A4763_INFO(inst) ((inst) + 0x00000069), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X006A_ADDR(inst) ((inst) + 0x0000006A) +#define BF_BF_19843866_INFO(inst) ((inst) + 0x0000006A), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X006B_ADDR(inst) ((inst) + 0x0000006B) +#define BF_BF_790E7AE7_INFO(inst) ((inst) + 0x0000006B), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X006C_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000006C) +#define BF_BF_69F39416_INFO(inst) ((inst) + 0x0000006C), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X006D_ADDR(inst) ((inst) + 0x0000006D) +#define BF_BF_E48AF3BC_INFO(inst) ((inst) + 0x0000006D), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X006E_ADDR(inst) ((inst) + 0x0000006E) +#define BF_BF_9D8A7056_INFO(inst) ((inst) + 0x0000006E), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X006F_ADDR(inst) ((inst) + 0x0000006F) +#define BF_BF_12864FA1_INFO(inst) ((inst) + 0x0000006F), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0070_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000070) +#define BF_BF_11448D41_INFO(inst) ((inst) + 0x00000070), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0071_ADDR(inst) ((inst) + 0x00000071) +#define BF_BF_517DD066_INFO(inst) ((inst) + 0x00000071), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0072_ADDR(inst) ((inst) + 0x00000072) +#define BF_BF_BC7007B8_INFO(inst) ((inst) + 0x00000072), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0073_ADDR(inst) ((inst) + 0x00000073) +#define BF_BF_EB898B35_INFO(inst) ((inst) + 0x00000073), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0074_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000074) +#define BF_BF_FF956141_INFO(inst) ((inst) + 0x00000074), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0075_ADDR(inst) ((inst) + 0x00000075) +#define BF_BF_D1BA0CCB_INFO(inst) ((inst) + 0x00000075), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0076_ADDR(inst) ((inst) + 0x00000076) +#define BF_BF_02BBD37A_INFO(inst) ((inst) + 0x00000076), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0077_ADDR(inst) ((inst) + 0x00000077) +#define BF_BF_C87FADDB_INFO(inst) ((inst) + 0x00000077), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0078_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000078) +#define BF_BF_C2A6BCD8_INFO(inst) ((inst) + 0x00000078), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0079_ADDR(inst) ((inst) + 0x00000079) +#define BF_BF_D4872F4B_INFO(inst) ((inst) + 0x00000079), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X007A_ADDR(inst) ((inst) + 0x0000007A) +#define BF_BF_073C6954_INFO(inst) ((inst) + 0x0000007A), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X007B_ADDR(inst) ((inst) + 0x0000007B) +#define BF_BF_046EED1C_INFO(inst) ((inst) + 0x0000007B), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X007C_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000007C) +#define BF_BF_647183D2_INFO(inst) ((inst) + 0x0000007C), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X007D_ADDR(inst) ((inst) + 0x0000007D) +#define BF_BF_0D8767CB_INFO(inst) ((inst) + 0x0000007D), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X007E_ADDR(inst) ((inst) + 0x0000007E) +#define BF_BF_5FE84509_INFO(inst) ((inst) + 0x0000007E), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X007F_ADDR(inst) ((inst) + 0x0000007F) +#define BF_BF_E82F5E92_INFO(inst) ((inst) + 0x0000007F), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0080_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000080) +#define BF_BF_6E93EF47_INFO(inst) ((inst) + 0x00000080), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0081_ADDR(inst) ((inst) + 0x00000081) +#define BF_BF_05D9E50D_INFO(inst) ((inst) + 0x00000081), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0082_ADDR(inst) ((inst) + 0x00000082) +#define BF_BF_B1374F67_INFO(inst) ((inst) + 0x00000082), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0083_ADDR(inst) ((inst) + 0x00000083) +#define BF_BF_8BAD84AF_INFO(inst) ((inst) + 0x00000083), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0084_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000084) +#define BF_BF_EEAD6A06_INFO(inst) ((inst) + 0x00000084), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0085_ADDR(inst) ((inst) + 0x00000085) +#define BF_BF_73C53E6A_INFO(inst) ((inst) + 0x00000085), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0086_ADDR(inst) ((inst) + 0x00000086) +#define BF_BF_7274C1EB_INFO(inst) ((inst) + 0x00000086), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0087_ADDR(inst) ((inst) + 0x00000087) +#define BF_BF_CA5D8F53_INFO(inst) ((inst) + 0x00000087), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0088_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000088) +#define BF_BF_09F4E46B_INFO(inst) ((inst) + 0x00000088), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0089_ADDR(inst) ((inst) + 0x00000089) +#define BF_BF_885C1945_INFO(inst) ((inst) + 0x00000089), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X008A_ADDR(inst) ((inst) + 0x0000008A) +#define BF_BF_295F527C_INFO(inst) ((inst) + 0x0000008A), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X008B_ADDR(inst) ((inst) + 0x0000008B) +#define BF_BF_BF04B71C_INFO(inst) ((inst) + 0x0000008B), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X008C_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000008C) +#define BF_BF_99F14377_INFO(inst) ((inst) + 0x0000008C), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X008D_ADDR(inst) ((inst) + 0x0000008D) +#define BF_BF_C74E66B4_INFO(inst) ((inst) + 0x0000008D), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X008E_ADDR(inst) ((inst) + 0x0000008E) +#define BF_BF_3C6340B8_INFO(inst) ((inst) + 0x0000008E), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X008F_ADDR(inst) ((inst) + 0x0000008F) +#define BF_BF_53DD1D84_INFO(inst) ((inst) + 0x0000008F), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0090_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000090) +#define BF_BF_5E73B8BA_INFO(inst) ((inst) + 0x00000090), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0091_ADDR(inst) ((inst) + 0x00000091) +#define BF_BF_B349B5B8_INFO(inst) ((inst) + 0x00000091), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0092_ADDR(inst) ((inst) + 0x00000092) +#define BF_BF_3B4A412D_INFO(inst) ((inst) + 0x00000092), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0093_ADDR(inst) ((inst) + 0x00000093) +#define BF_BF_9FC2C086_INFO(inst) ((inst) + 0x00000093), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0094_ADDR(inst) ((inst) + 0x00000094) +#define BF_BF_F49FF642_INFO(inst) ((inst) + 0x00000094), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0095_ADDR(inst) ((inst) + 0x00000095) +#define BF_BF_7C28B2DB_INFO(inst) ((inst) + 0x00000095), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0096_ADDR(inst) ((inst) + 0x00000096) +#define BF_BF_891C0AF4_INFO(inst) ((inst) + 0x00000096), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0097_ADDR(inst) ((inst) + 0x00000097) +#define BF_BF_85A00C00_INFO(inst) ((inst) + 0x00000097), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0098_ADDR(inst) ((inst) + 0x00000098) +#define BF_BF_9DEA97A3_INFO(inst) ((inst) + 0x00000098), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0099_ADDR(inst) ((inst) + 0x00000099) +#define BF_BF_9179CBDC_INFO(inst) ((inst) + 0x00000099), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X009A_ADDR(inst) ((inst) + 0x0000009A) +#define BF_BF_084AB0D4_INFO(inst) ((inst) + 0x0000009A), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X009B_ADDR(inst) ((inst) + 0x0000009B) +#define BF_BF_CEA90E2F_INFO(inst) ((inst) + 0x0000009B), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X009C_ADDR(inst) ((inst) + 0x0000009C) +#define BF_BF_7C0582C2_INFO(inst) ((inst) + 0x0000009C), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X009D_ADDR(inst) ((inst) + 0x0000009D) +#define BF_BF_510A51D7_INFO(inst) ((inst) + 0x0000009D), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X009E_ADDR(inst) ((inst) + 0x0000009E) +#define BF_BF_61899914_INFO(inst) ((inst) + 0x0000009E), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X009F_ADDR(inst) ((inst) + 0x0000009F) +#define BF_BF_D80BF2DC_INFO(inst) ((inst) + 0x0000009F), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00A0_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x000000A0) +#define BF_BF_6BAA9B30_INFO(inst) ((inst) + 0x000000A0), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00A1_ADDR(inst) ((inst) + 0x000000A1) +#define BF_BF_93D6102A_INFO(inst) ((inst) + 0x000000A1), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00A2_ADDR(inst) ((inst) + 0x000000A2) +#define BF_BF_D075335A_INFO(inst) ((inst) + 0x000000A2), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00A3_ADDR(inst) ((inst) + 0x000000A3) +#define BF_BF_F6E7DE4A_INFO(inst) ((inst) + 0x000000A3), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00A4_ADDR(inst) ((inst) + 0x000000A4) +#define BF_BF_10B50A11_INFO(inst) ((inst) + 0x000000A4), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00A5_ADDR(inst) ((inst) + 0x000000A5) +#define BF_BF_D770280B_INFO(inst) ((inst) + 0x000000A5), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00A6_ADDR(inst) ((inst) + 0x000000A6) +#define BF_BF_2FAD0663_INFO(inst) ((inst) + 0x000000A6), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00A7_ADDR(inst) ((inst) + 0x000000A7) +#define BF_BF_B25984B4_INFO(inst) ((inst) + 0x000000A7), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00A8_ADDR(inst) ((inst) + 0x000000A8) +#define BF_BF_25A22373_INFO(inst) ((inst) + 0x000000A8), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00A9_ADDR(inst) ((inst) + 0x000000A9) +#define BF_BF_E479C47C_INFO(inst) ((inst) + 0x000000A9), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00AA_ADDR(inst) ((inst) + 0x000000AA) +#define BF_BF_4A70DE57_INFO(inst) ((inst) + 0x000000AA), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00AB_ADDR(inst) ((inst) + 0x000000AB) +#define BF_BF_7ED02D3E_INFO(inst) ((inst) + 0x000000AB), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00AC_ADDR(inst) ((inst) + 0x000000AC) +#define BF_BF_12192AC9_INFO(inst) ((inst) + 0x000000AC), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00AD_ADDR(inst) ((inst) + 0x000000AD) +#define BF_BF_CAE99163_INFO(inst) ((inst) + 0x000000AD), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00AE_ADDR(inst) ((inst) + 0x000000AE) +#define BF_BF_81A55DD0_INFO(inst) ((inst) + 0x000000AE), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00AF_ADDR(inst) ((inst) + 0x000000AF) +#define BF_BF_94E6D45F_INFO(inst) ((inst) + 0x000000AF), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00B0_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x000000B0) +#define BF_BF_83058D46_INFO(inst) ((inst) + 0x000000B0), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00B1_ADDR(inst) ((inst) + 0x000000B1) +#define BF_BF_16CE9612_INFO(inst) ((inst) + 0x000000B1), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00B2_ADDR(inst) ((inst) + 0x000000B2) +#define BF_BF_ED0889A8_INFO(inst) ((inst) + 0x000000B2), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00B3_ADDR(inst) ((inst) + 0x000000B3) +#define BF_BF_D367938A_INFO(inst) ((inst) + 0x000000B3), 0x00000100 +#define BF_BF_F7ACF82F_INFO(inst) ((inst) + 0x000000B3), 0x00000201 +#define BF_BF_CF062091_INFO(inst) ((inst) + 0x000000B3), 0x00000103 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00B4_ADDR(inst) ((inst) + 0x000000B4) +#define BF_BF_66506219_INFO(inst) ((inst) + 0x000000B4), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00B5_ADDR(inst) ((inst) + 0x000000B5) +#define BF_BF_4492BDA3_INFO(inst) ((inst) + 0x000000B5), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00B6_ADDR(inst) ((inst) + 0x000000B6) +#define BF_BF_C349D470_INFO(inst) ((inst) + 0x000000B6), 0x00000200 +#define BF_BF_0366BFB5_INFO(inst) ((inst) + 0x000000B6), 0x00000202 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00B7_ADDR(inst) ((inst) + 0x000000B7) +#define BF_BF_AA8AB79E_INFO(inst) ((inst) + 0x000000B7), 0x00000300 +#define BF_BF_1920D4A4_INFO(inst) ((inst) + 0x000000B7), 0x00000303 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00B8_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x000000B8) +#define BF_BF_8248D004_INFO(inst) ((inst) + 0x000000B8), 0x00000400 +#define BF_BF_5BDE2FD9_INFO(inst) ((inst) + 0x000000B8), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00B9_ADDR(inst) ((inst) + 0x000000B9) +#define BF_BF_D7A66B31_INFO(inst) ((inst) + 0x000000B9), 0x00000400 +#define BF_BF_355A9592_INFO(inst) ((inst) + 0x000000B9), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00BA_ADDR(inst) ((inst) + 0x000000BA) +#define BF_BF_5389AB66_INFO(inst) ((inst) + 0x000000BA), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00BB_ADDR(inst) ((inst) + 0x000000BB) +#define BF_BF_C44A20A3_INFO(inst) ((inst) + 0x000000BB), 0x00000300 +#define BF_BF_68BAE7CF_INFO(inst) ((inst) + 0x000000BB), 0x00000203 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00BD_ADDR(inst) ((inst) + 0x000000BD) +#define BF_BF_B7FD43BB_INFO(inst) ((inst) + 0x000000BD), 0x00000400 +#define BF_BF_E555E374_INFO(inst) ((inst) + 0x000000BD), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00BE_ADDR(inst) ((inst) + 0x000000BE) +#define BF_BF_E55709C4_INFO(inst) ((inst) + 0x000000BE), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00BF_ADDR(inst) ((inst) + 0x000000BF) +#define BF_BF_132BA678_INFO(inst) ((inst) + 0x000000BF), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00C0_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x000000C0) +#define BF_BF_1DAD5008_INFO(inst) ((inst) + 0x000000C0), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00C1_ADDR(inst) ((inst) + 0x000000C1) +#define BF_BF_5FD9B2E8_INFO(inst) ((inst) + 0x000000C1), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00C2_ADDR(inst) ((inst) + 0x000000C2) +#define BF_BF_BFB2117E_INFO(inst) ((inst) + 0x000000C2), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00C3_ADDR(inst) ((inst) + 0x000000C3) +#define BF_BF_B1629ECD_INFO(inst) ((inst) + 0x000000C3), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00C4_ADDR(inst) ((inst) + 0x000000C4) +#define BF_BF_6BFD9CFD_INFO(inst) ((inst) + 0x000000C4), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00C5_ADDR(inst) ((inst) + 0x000000C5) +#define BF_BF_D98634B9_INFO(inst) ((inst) + 0x000000C5), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00C6_ADDR(inst) ((inst) + 0x000000C6) +#define BF_BF_F787E919_INFO(inst) ((inst) + 0x000000C6), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00C7_ADDR(inst) ((inst) + 0x000000C7) +#define BF_BF_D1399BEC_INFO(inst) ((inst) + 0x000000C7), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00C8_ADDR(inst) ((inst) + 0x000000C8) +#define BF_BF_909D142E_INFO(inst) ((inst) + 0x000000C8), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00C9_ADDR(inst) ((inst) + 0x000000C9) +#define BF_BF_B31A327B_INFO(inst) ((inst) + 0x000000C9), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00CA_ADDR(inst) ((inst) + 0x000000CA) +#define BF_BF_A3DB5FD3_INFO(inst) ((inst) + 0x000000CA), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00CB_ADDR(inst) ((inst) + 0x000000CB) +#define BF_BF_992EF2F3_INFO(inst) ((inst) + 0x000000CB), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00CC_ADDR(inst) ((inst) + 0x000000CC) +#define BF_BF_2BCD10F0_INFO(inst) ((inst) + 0x000000CC), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00CD_ADDR(inst) ((inst) + 0x000000CD) +#define BF_BF_4443BFD9_INFO(inst) ((inst) + 0x000000CD), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00CE_ADDR(inst) ((inst) + 0x000000CE) +#define BF_BF_B38657ED_INFO(inst) ((inst) + 0x000000CE), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00CF_ADDR(inst) ((inst) + 0x000000CF) +#define BF_BF_1E4FE596_INFO(inst) ((inst) + 0x000000CF), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00D0_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x000000D0) +#define BF_BF_5B6F4662_INFO(inst) ((inst) + 0x000000D0), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00D1_ADDR(inst) ((inst) + 0x000000D1) +#define BF_BF_CBACE33F_INFO(inst) ((inst) + 0x000000D1), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00D2_ADDR(inst) ((inst) + 0x000000D2) +#define BF_BF_2C843ECB_INFO(inst) ((inst) + 0x000000D2), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00D3_ADDR(inst) ((inst) + 0x000000D3) +#define BF_BF_6DFE39E7_INFO(inst) ((inst) + 0x000000D3), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00D4_ADDR(inst) ((inst) + 0x000000D4) +#define BF_BF_478E6CBE_INFO(inst) ((inst) + 0x000000D4), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00D5_ADDR(inst) ((inst) + 0x000000D5) +#define BF_BF_7EC1D051_INFO(inst) ((inst) + 0x000000D5), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00D6_ADDR(inst) ((inst) + 0x000000D6) +#define BF_BF_36C3F722_INFO(inst) ((inst) + 0x000000D6), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00D7_ADDR(inst) ((inst) + 0x000000D7) +#define BF_BF_43D363AE_INFO(inst) ((inst) + 0x000000D7), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00D8_ADDR(inst) ((inst) + 0x000000D8) +#define BF_BF_438D6C2F_INFO(inst) ((inst) + 0x000000D8), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00D9_ADDR(inst) ((inst) + 0x000000D9) +#define BF_BF_F2993362_INFO(inst) ((inst) + 0x000000D9), 0x00000200 +#define BF_BF_B76A0C1C_INFO(inst) ((inst) + 0x000000D9), 0x00000204 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00DA_ADDR(inst) ((inst) + 0x000000DA) +#define BF_BF_246AC3B1_ACTRL_EAST__OPEN_INFO(inst) ((inst) + 0x000000DA), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00DB_ADDR(inst) ((inst) + 0x000000DB) +#define BF_BF_ECECD989_ACTRL_EAST__OPEN_INFO(inst) ((inst) + 0x000000DB), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00DC_ADDR(inst) ((inst) + 0x000000DC) +#define BF_BF_DA32E51D_ACTRL_EAST__OPEN_INFO(inst) ((inst) + 0x000000DC), 0x00000500 +#define BF_BF_CB8D6E7B_ACTRL_EAST__OPEN_INFO(inst) ((inst) + 0x000000DC), 0x00000305 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X00E0_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x000000E0) + +#define REG_REG_0X00E1_ADDR(inst) ((inst) + 0x000000E1) + +#define REG_REG_0X00E3_ADDR(inst) ((inst) + 0x000000E3) + +#define REG_REG_0X00E4_ADDR(inst) ((inst) + 0x000000E4) + +#define REG_REG_0X00E5_ADDR(inst) ((inst) + 0x000000E5) + +#define REG_REG_0X00E6_ADDR(inst) ((inst) + 0x000000E6) + +#define REG_REG_0X00E7_ADDR(inst) ((inst) + 0x000000E7) + +#define REG_REG_0X00E8_ADDR(inst) ((inst) + 0x000000E8) + +#define REG_REG_0X00E9_ADDR(inst) ((inst) + 0x000000E9) + +#define REG_REG_0X00EA_ADDR(inst) ((inst) + 0x000000EA) + +#define REG_REG_0X00EB_ADDR(inst) ((inst) + 0x000000EB) + +#define REG_REG_0X00EC_ADDR(inst) ((inst) + 0x000000EC) + +#define REG_REG_0X00ED_ADDR(inst) ((inst) + 0x000000ED) + +#define REG_REG_0X00EE_ADDR(inst) ((inst) + 0x000000EE) + +#define REG_REG_0X00EF_ADDR(inst) ((inst) + 0x000000EF) + +#define REG_REG_0X00F0_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x000000F0) + +#define REG_REG_0X00F1_ADDR(inst) ((inst) + 0x000000F1) + +#define REG_REG_0X00F2_ADDR(inst) ((inst) + 0x000000F2) + +#define REG_REG_0X00F3_ADDR(inst) ((inst) + 0x000000F3) + +#define REG_REG_0X00F4_ADDR(inst) ((inst) + 0x000000F4) + +#define REG_REG_0X00F5_ADDR(inst) ((inst) + 0x000000F5) + +#define REG_REG_0X00F6_ADDR(inst) ((inst) + 0x000000F6) + +#define REG_REG_0X00F7_ADDR(inst) ((inst) + 0x000000F7) + +#define REG_REG_0X00F8_ADDR(inst) ((inst) + 0x000000F8) + +#define REG_REG_0X00F9_ADDR(inst) ((inst) + 0x000000F9) + +#define REG_REG_0X00FA_ADDR(inst) ((inst) + 0x000000FA) + +#define REG_REG_0X00FB_ADDR(inst) ((inst) + 0x000000FB) + +#define REG_REG_0X00FC_ADDR(inst) ((inst) + 0x000000FC) + +#define REG_REG_0X00FD_ADDR(inst) ((inst) + 0x000000FD) + +#define REG_REG_0X00FE_ADDR(inst) ((inst) + 0x000000FE) + +#define REG_REG_0X00FF_ADDR(inst) ((inst) + 0x000000FF) + +#define REG_REG_0X0100_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000100) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0101_ADDR(inst) ((inst) + 0x00000101) +#define BF_BF_2BD68F04_ACTRL_EAST__OPEN_INFO(inst) ((inst) + 0x00000101), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0102_ADDR(inst) ((inst) + 0x00000102) +#define BF_BF_6F0E76C0_ACTRL_EAST__OPEN_INFO(inst) ((inst) + 0x00000102), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0103_ADDR(inst) ((inst) + 0x00000103) +#define BF_BF_1DECF0B5_ACTRL_EAST__OPEN_INFO(inst) ((inst) + 0x00000103), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0104_ADDR(inst) ((inst) + 0x00000104) +#define BF_BF_C5EBC8EF_ACTRL_EAST__OPEN_INFO(inst) ((inst) + 0x00000104), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0105_ADDR(inst) ((inst) + 0x00000105) +#define BF_BF_C9878C07_ACTRL_EAST__OPEN_INFO(inst) ((inst) + 0x00000105), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0106_ADDR(inst) ((inst) + 0x00000106) +#define BF_BF_A8BAEFD3_ACTRL_EAST__OPEN_INFO(inst) ((inst) + 0x00000106), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_ACTRL_SCRATCH_END_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x000003FF) +#define BF_ACTRL_SCRATCH_END_ACTRL_EAST__OPEN_INFO(inst) ((inst) + 0x000003FF), 0x00000800 + +#endif /* __ADI_APOLLO_BF_ACTRL_EAST_OPEN_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_actrl_slice_broadcast_open.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_actrl_slice_broadcast_open.h new file mode 100644 index 00000000000000..cbb8021deb8ae9 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_actrl_slice_broadcast_open.h @@ -0,0 +1,307 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:19 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_ACTRL_SLICE_BROADCAST_OPEN_H__ +#define __ADI_APOLLO_BF_ACTRL_SLICE_BROADCAST_OPEN_H__ + +/*============= D E F I N E S ==============*/ +#define VENUS_ACTRL_SLICE_BROADCAST_ADC8_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x60260000 +#define VENUS_ACTRL_SLICE_BROADCAST_ADC8_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x60460000 +#define VENUS_ACTRL_SLICE_BROADCAST_ADC8_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A60000 +#define VENUS_ACTRL_SLICE_BROADCAST_ADC8_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C60000 + +#define REG_ACTRL_SCRATCH_BEGIN_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000000) +#define BF_ACTRL_SCRATCH_BEGIN_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000000), 0x00000800 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0001_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000001) +#define BF_BF_5EB08FA9_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000001), 0x00000100 +#define BF_BF_126EB5D8_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000001), 0x00000101 +#define BF_BF_D1919DE4_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000001), 0x00000102 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0002_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000002) +#define BF_BF_A252E209_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000002), 0x00000100 +#define BF_BF_EC0570A1_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000002), 0x00000101 +#define BF_BF_9EC08343_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000002), 0x00000102 +#define BF_BF_DD32CEDB_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000002), 0x00000103 +#define BF_BF_889162C1_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000002), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0003_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000003) +#define BF_BF_A6D3CBFE_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000003), 0x00000101 +#define BF_BF_4018413E_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000003), 0x00000102 +#define BF_BF_2D63C129_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000003), 0x00000103 +#define BF_BF_339349E3_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000003), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0004_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000004) +#define BF_BF_AA4FF39E_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000004), 0x00000100 +#define BF_BF_001B22C8_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000004), 0x00000101 +#define BF_BF_2EAD4958_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000004), 0x00000102 +#define BF_BF_0CD0A002_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000004), 0x00000103 +#define BF_BF_458B15CA_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000004), 0x00000104 +#define BF_BF_99E768C7_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000004), 0x00000105 +#define BF_BF_09247BC9_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000004), 0x00000106 +#define BF_BF_D9B5E6DC_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000004), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0005_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000005) +#define BF_BF_4A1CE9FD_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000005), 0x00000100 +#define BF_BF_2FB6FEB1_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000005), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0006_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000006) +#define BF_BF_B1275EF4_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000006), 0x00000100 +#define BF_BF_2B4D955F_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000006), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0007_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000007) +#define BF_BF_D6F9511E_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000007), 0x00000100 +#define BF_BF_B2A878C7_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000007), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0008_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000008) +#define BF_BF_879E702A_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000008), 0x00000100 +#define BF_BF_EE1E3FD5_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000008), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0009_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000009) +#define BF_BF_9F65E970_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000009), 0x00000100 +#define BF_BF_9C76E371_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000009), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X000A_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000000A) +#define BF_BF_4B2ABE3F_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000000A), 0x00000100 +#define BF_BF_CA3810E7_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000000A), 0x00000101 +#define BF_BF_7BE4DF0B_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000000A), 0x00000102 +#define BF_BF_B950B3D9_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000000A), 0x00000103 +#define BF_BF_03899053_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000000A), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X000B_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000000B) +#define BF_BF_47AD4A09_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000000B), 0x00000400 +#define BF_BF_C278F62B_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000000B), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X000C_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000000C) +#define BF_BF_4AFC5970_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000000C), 0x00000400 +#define BF_BF_DC4BD305_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000000C), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X000D_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000000D) +#define BF_BF_AD50EA09_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000000D), 0x00000400 +#define BF_BF_6B9EF517_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000000D), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X000E_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000000E) +#define BF_BF_31AECD11_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000000E), 0x00000400 +#define BF_BF_7D3754EB_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000000E), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X000F_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000000F) +#define BF_BF_FE1DA073_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000000F), 0x00000400 +#define BF_BF_B5F7486C_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000000F), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0010_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000010) +#define BF_BF_B866A4AB_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000010), 0x00000100 +#define BF_BF_DE6A013F_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000010), 0x00000101 +#define BF_BF_FD8BEC76_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000010), 0x00000102 +#define BF_BF_E582A0EB_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000010), 0x00000103 +#define BF_BF_38088E6C_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000010), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0011_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000011) +#define BF_BF_5587D278_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000011), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0012_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000012) +#define BF_BF_F0273B9A_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000012), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0013_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000013) +#define BF_BF_954D455E_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000013), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0014_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000014) +#define BF_BF_E4A95397_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000014), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0015_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000015) +#define BF_BF_F908A4B7_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000015), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0016_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000016) +#define BF_BF_8DCABC6F_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000016), 0x00000200 +#define BF_BF_46B72E84_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000016), 0x00000202 +#define BF_BF_8AF0C451_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000016), 0x00000204 +#define BF_BF_FF501E2E_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000016), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0017_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000017) +#ifdef USE_PRIVATE_BF +#define BF_BF_77037A43_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000017), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_77037A43_WEB_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000017), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_DC5FC06D_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000017), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_DC5FC06D_WEB_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000017), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_6B686F5F_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000017), 0x00000304 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_6B686F5F_WEB_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000017), 0x00000107 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0018_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000018) +#define BF_BF_FE5D14F7_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000018), 0x00000100 +#define BF_BF_293203CE_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000018), 0x00000101 +#define BF_BF_1F8B49FB_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000018), 0x00000302 +#define BF_BF_BC94FEB9_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000018), 0x00000105 +#define BF_BF_4932BE36_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000018), 0x00000106 +#define BF_BF_15542900_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000018), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0019_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000019) +#define BF_BF_6E624734_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000019), 0x00000100 +#define BF_BF_3451B00C_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000019), 0x00000101 +#define BF_BF_11F6B22B_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000019), 0x00000302 +#define BF_BF_D74C5E45_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000019), 0x00000105 +#define BF_BF_85370402_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000019), 0x00000106 +#define BF_BF_4E3ABDB0_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000019), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X001A_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000001A) +#define BF_BF_DBD9054E_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000001A), 0x00000100 +#define BF_BF_8FEFCFA2_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000001A), 0x00000101 +#define BF_BF_E209801C_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000001A), 0x00000302 +#define BF_BF_22202CD7_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000001A), 0x00000105 +#define BF_BF_3D738581_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000001A), 0x00000106 +#define BF_BF_46D7DA69_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000001A), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X001B_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000001B) +#define BF_BF_6F58C319_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000001B), 0x00000100 +#define BF_BF_D436DB2D_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000001B), 0x00000101 +#define BF_BF_4F00CCC9_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000001B), 0x00000302 +#define BF_BF_87949627_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000001B), 0x00000105 +#define BF_BF_C86E3FED_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000001B), 0x00000106 +#define BF_BF_30A1F19E_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000001B), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X001C_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000001C) +#define BF_BF_A5738686_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000001C), 0x00002400 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X001D_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000001D) + +#define REG_REG_0X001E_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000001E) + +#define REG_REG_0X001F_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000001F) + +#define REG_REG_0X0020_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000020) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0021_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000021) +#define BF_BF_3A967583_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000021), 0x00000200 +#define BF_BF_55B25744_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000021), 0x00000202 +#define BF_BF_6F32B7D5_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000021), 0x00000204 +#define BF_BF_4F85E59F_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000021), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0022_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000022) +#define BF_BF_8B5D9414_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000022), 0x00000200 +#define BF_BF_891B6811_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000022), 0x00000202 +#define BF_BF_ECCF50C4_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000022), 0x00000204 +#define BF_BF_C32291CF_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000022), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0023_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000023) +#define BF_BF_7A13FD19_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000023), 0x00000200 +#define BF_BF_C5D1868C_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000023), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0024_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000024) +#define BF_BF_8701A65A_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000024), 0x00000200 +#define BF_BF_14DF43FB_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000024), 0x00000202 +#define BF_BF_C35798E6_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000024), 0x00000204 +#define BF_BF_455E4600_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000024), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0025_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000025) +#define BF_BF_1AD3C3B4_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000025), 0x00000200 +#define BF_BF_C13F473C_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000025), 0x00000202 +#define BF_BF_D167EABD_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000025), 0x00000204 +#define BF_BF_C8945FBC_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000025), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0026_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000026) +#define BF_BF_2BD68F04_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000026), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0027_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000027) +#define BF_BF_6F0E76C0_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000027), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0028_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000028) +#define BF_BF_1DECF0B5_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000028), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0029_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000029) +#define BF_BF_C5EBC8EF_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000029), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X002A_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000002A) + +#define REG_REG_0X002B_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000002B) + +#define REG_ACTRL_SCRATCH_END_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000003FF) +#define BF_ACTRL_SCRATCH_END_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000003FF), 0x00000800 + +#endif /* __ADI_APOLLO_BF_ACTRL_SLICE_BROADCAST_OPEN_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_actrl_slice_open.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_actrl_slice_open.h new file mode 100644 index 00000000000000..313e843ccc7a60 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_actrl_slice_open.h @@ -0,0 +1,341 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:19 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_ACTRL_SLICE_OPEN_H__ +#define __ADI_APOLLO_BF_ACTRL_SLICE_OPEN_H__ + +/*============= D E F I N E S ==============*/ +#define VENUS_ACTRL_SLICE_REGMAP0_ADC8_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x60260400 +#define VENUS_ACTRL_SLICE_REGMAP1_ADC8_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x60260800 +#define VENUS_ACTRL_SLICE_REGMAP2_ADC8_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x60260C00 +#define VENUS_ACTRL_SLICE_REGMAP3_ADC8_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x60261000 +#define VENUS_ACTRL_SLICE_REGMAP4_ADC8_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x60261400 +#define VENUS_ACTRL_SLICE_REGMAP5_ADC8_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x60261800 +#define VENUS_ACTRL_SLICE_REGMAP6_ADC8_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x60261C00 +#define VENUS_ACTRL_SLICE_REGMAP7_ADC8_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x60262000 +#define VENUS_ACTRL_SLICE_REGMAP0_ADC8_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x60460400 +#define VENUS_ACTRL_SLICE_REGMAP1_ADC8_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x60460800 +#define VENUS_ACTRL_SLICE_REGMAP2_ADC8_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x60460C00 +#define VENUS_ACTRL_SLICE_REGMAP3_ADC8_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x60461000 +#define VENUS_ACTRL_SLICE_REGMAP4_ADC8_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x60461400 +#define VENUS_ACTRL_SLICE_REGMAP5_ADC8_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x60461800 +#define VENUS_ACTRL_SLICE_REGMAP6_ADC8_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x60461C00 +#define VENUS_ACTRL_SLICE_REGMAP7_ADC8_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x60462000 +#define VENUS_ACTRL_SLICE_REGMAP0_ADC8_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A60400 +#define VENUS_ACTRL_SLICE_REGMAP1_ADC8_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A60800 +#define VENUS_ACTRL_SLICE_REGMAP2_ADC8_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A60C00 +#define VENUS_ACTRL_SLICE_REGMAP3_ADC8_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A61000 +#define VENUS_ACTRL_SLICE_REGMAP4_ADC8_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A61400 +#define VENUS_ACTRL_SLICE_REGMAP5_ADC8_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A61800 +#define VENUS_ACTRL_SLICE_REGMAP6_ADC8_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A61C00 +#define VENUS_ACTRL_SLICE_REGMAP7_ADC8_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A62000 +#define VENUS_ACTRL_SLICE_REGMAP0_ADC8_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C60400 +#define VENUS_ACTRL_SLICE_REGMAP1_ADC8_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C60800 +#define VENUS_ACTRL_SLICE_REGMAP2_ADC8_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C60C00 +#define VENUS_ACTRL_SLICE_REGMAP3_ADC8_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C61000 +#define VENUS_ACTRL_SLICE_REGMAP4_ADC8_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C61400 +#define VENUS_ACTRL_SLICE_REGMAP5_ADC8_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C61800 +#define VENUS_ACTRL_SLICE_REGMAP6_ADC8_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C61C00 +#define VENUS_ACTRL_SLICE_REGMAP7_ADC8_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C62000 + +#define REG_ACTRL_SCRATCH_BEGIN_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x00000000) +#define BF_ACTRL_SCRATCH_BEGIN_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000000), 0x00000800 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0001_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x00000001) +#define BF_BF_5EB08FA9_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000001), 0x00000100 +#define BF_BF_126EB5D8_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000001), 0x00000101 +#define BF_BF_D1919DE4_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000001), 0x00000102 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0002_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x00000002) +#define BF_BF_A252E209_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000002), 0x00000100 +#define BF_BF_EC0570A1_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000002), 0x00000101 +#define BF_BF_9EC08343_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000002), 0x00000102 +#define BF_BF_DD32CEDB_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000002), 0x00000103 +#define BF_BF_889162C1_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000002), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0003_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x00000003) +#define BF_BF_A6D3CBFE_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000003), 0x00000101 +#define BF_BF_4018413E_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000003), 0x00000102 +#define BF_BF_2D63C129_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000003), 0x00000103 +#define BF_BF_339349E3_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000003), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0004_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x00000004) +#define BF_BF_AA4FF39E_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000004), 0x00000100 +#define BF_BF_001B22C8_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000004), 0x00000101 +#define BF_BF_2EAD4958_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000004), 0x00000102 +#define BF_BF_0CD0A002_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000004), 0x00000103 +#define BF_BF_458B15CA_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000004), 0x00000104 +#define BF_BF_99E768C7_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000004), 0x00000105 +#define BF_BF_09247BC9_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000004), 0x00000106 +#define BF_BF_D9B5E6DC_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000004), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0005_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x00000005) +#define BF_BF_4A1CE9FD_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000005), 0x00000100 +#define BF_BF_2FB6FEB1_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000005), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0006_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x00000006) +#define BF_BF_B1275EF4_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000006), 0x00000100 +#define BF_BF_2B4D955F_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000006), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0007_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x00000007) +#define BF_BF_D6F9511E_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000007), 0x00000100 +#define BF_BF_B2A878C7_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000007), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0008_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x00000008) +#define BF_BF_879E702A_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000008), 0x00000100 +#define BF_BF_EE1E3FD5_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000008), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0009_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x00000009) +#define BF_BF_9F65E970_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000009), 0x00000100 +#define BF_BF_9C76E371_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000009), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X000A_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x0000000A) +#define BF_BF_4B2ABE3F_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x0000000A), 0x00000100 +#define BF_BF_CA3810E7_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x0000000A), 0x00000101 +#define BF_BF_7BE4DF0B_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x0000000A), 0x00000102 +#define BF_BF_B950B3D9_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x0000000A), 0x00000103 +#define BF_BF_03899053_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x0000000A), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X000B_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x0000000B) +#define BF_BF_47AD4A09_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x0000000B), 0x00000400 +#define BF_BF_C278F62B_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x0000000B), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X000C_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x0000000C) +#define BF_BF_4AFC5970_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x0000000C), 0x00000400 +#define BF_BF_DC4BD305_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x0000000C), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X000D_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x0000000D) +#define BF_BF_AD50EA09_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x0000000D), 0x00000400 +#define BF_BF_6B9EF517_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x0000000D), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X000E_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x0000000E) +#define BF_BF_31AECD11_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x0000000E), 0x00000400 +#define BF_BF_7D3754EB_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x0000000E), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X000F_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x0000000F) +#define BF_BF_FE1DA073_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x0000000F), 0x00000400 +#define BF_BF_B5F7486C_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x0000000F), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0010_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x00000010) +#define BF_BF_B866A4AB_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000010), 0x00000100 +#define BF_BF_DE6A013F_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000010), 0x00000101 +#define BF_BF_FD8BEC76_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000010), 0x00000102 +#define BF_BF_E582A0EB_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000010), 0x00000103 +#define BF_BF_38088E6C_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000010), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0011_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x00000011) +#define BF_BF_5587D278_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000011), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0012_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x00000012) +#define BF_BF_F0273B9A_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000012), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0013_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x00000013) +#define BF_BF_954D455E_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000013), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0014_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x00000014) +#define BF_BF_E4A95397_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000014), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0015_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x00000015) +#define BF_BF_F908A4B7_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000015), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0016_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x00000016) +#define BF_BF_8DCABC6F_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000016), 0x00000200 +#define BF_BF_46B72E84_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000016), 0x00000202 +#define BF_BF_8AF0C451_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000016), 0x00000204 +#define BF_BF_FF501E2E_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000016), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0017_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x00000017) +#ifdef USE_PRIVATE_BF +#define BF_BF_77037A43_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000017), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_77037A43_WEB_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000017), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_DC5FC06D_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000017), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_DC5FC06D_WEB_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000017), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_6B686F5F_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000017), 0x00000304 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_6B686F5F_WEB_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000017), 0x00000107 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0018_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x00000018) +#define BF_BF_FE5D14F7_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000018), 0x00000100 +#define BF_BF_293203CE_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000018), 0x00000101 +#define BF_BF_1F8B49FB_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000018), 0x00000302 +#define BF_BF_BC94FEB9_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000018), 0x00000105 +#define BF_BF_4932BE36_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000018), 0x00000106 +#define BF_BF_15542900_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000018), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0019_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x00000019) +#define BF_BF_6E624734_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000019), 0x00000100 +#define BF_BF_3451B00C_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000019), 0x00000101 +#define BF_BF_11F6B22B_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000019), 0x00000302 +#define BF_BF_D74C5E45_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000019), 0x00000105 +#define BF_BF_85370402_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000019), 0x00000106 +#define BF_BF_4E3ABDB0_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000019), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X001A_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x0000001A) +#define BF_BF_DBD9054E_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x0000001A), 0x00000100 +#define BF_BF_8FEFCFA2_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x0000001A), 0x00000101 +#define BF_BF_E209801C_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x0000001A), 0x00000302 +#define BF_BF_22202CD7_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x0000001A), 0x00000105 +#define BF_BF_3D738581_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x0000001A), 0x00000106 +#define BF_BF_46D7DA69_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x0000001A), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X001B_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x0000001B) +#define BF_BF_6F58C319_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x0000001B), 0x00000100 +#define BF_BF_D436DB2D_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x0000001B), 0x00000101 +#define BF_BF_4F00CCC9_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x0000001B), 0x00000302 +#define BF_BF_87949627_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x0000001B), 0x00000105 +#define BF_BF_C86E3FED_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x0000001B), 0x00000106 +#define BF_BF_30A1F19E_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x0000001B), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X001C_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x0000001C) +#define BF_BF_A5738686_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x0000001C), 0x00002400 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X001D_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x0000001D) + +#define REG_REG_0X001E_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x0000001E) + +#define REG_REG_0X001F_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x0000001F) + +#define REG_REG_0X0020_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x00000020) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0021_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x00000021) +#define BF_BF_3A967583_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000021), 0x00000200 +#define BF_BF_55B25744_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000021), 0x00000202 +#define BF_BF_6F32B7D5_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000021), 0x00000204 +#define BF_BF_4F85E59F_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000021), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0022_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x00000022) +#define BF_BF_8B5D9414_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000022), 0x00000200 +#define BF_BF_891B6811_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000022), 0x00000202 +#define BF_BF_ECCF50C4_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000022), 0x00000204 +#define BF_BF_C32291CF_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000022), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0023_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x00000023) +#define BF_BF_7A13FD19_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000023), 0x00000200 +#define BF_BF_C5D1868C_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000023), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0024_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x00000024) +#define BF_BF_8701A65A_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000024), 0x00000200 +#define BF_BF_14DF43FB_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000024), 0x00000202 +#define BF_BF_C35798E6_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000024), 0x00000204 +#define BF_BF_455E4600_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000024), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0025_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x00000025) +#define BF_BF_1AD3C3B4_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000025), 0x00000200 +#define BF_BF_C13F473C_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000025), 0x00000202 +#define BF_BF_D167EABD_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000025), 0x00000204 +#define BF_BF_C8945FBC_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000025), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0026_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x00000026) +#define BF_BF_2BD68F04_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000026), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0027_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x00000027) +#define BF_BF_6F0E76C0_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000027), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0028_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x00000028) +#define BF_BF_1DECF0B5_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000028), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0029_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x00000029) +#define BF_BF_C5EBC8EF_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000029), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X002A_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x0000002A) +#define BF_BF_C9878C07_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x0000002A), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X002B_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x0000002B) +#define BF_BF_A8BAEFD3_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x0000002B), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_ACTRL_SCRATCH_END_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x000003FF) +#define BF_ACTRL_SCRATCH_END_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x000003FF), 0x00000800 + +#endif /* __ADI_APOLLO_BF_ACTRL_SLICE_OPEN_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_actrl_west_open.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_actrl_west_open.h new file mode 100644 index 00000000000000..7aad339ba02c57 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_actrl_west_open.h @@ -0,0 +1,408 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:19 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_ACTRL_WEST_OPEN_H__ +#define __ADI_APOLLO_BF_ACTRL_WEST_OPEN_H__ + +/*============= D E F I N E S ==============*/ +#define VENUS_ACTRL_WEST_REGMAP_ADC8_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x60262400 +#define VENUS_ACTRL_WEST_REGMAP_ADC8_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x60462400 +#define VENUS_ACTRL_WEST_REGMAP_ADC8_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A62400 +#define VENUS_ACTRL_WEST_REGMAP_ADC8_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C62400 + +#define REG_ACTRL_SCRATCH_BEGIN_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000000) +#define BF_ACTRL_SCRATCH_BEGIN_ACTRL_WEST__OPEN_INFO(inst) ((inst) + 0x00000000), 0x00000800 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0001_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000001) +#define BF_BF_4F891517_INFO(inst) ((inst) + 0x00000001), 0x00000100 +#define BF_BF_CAEB7B6D_INFO(inst) ((inst) + 0x00000001), 0x00000101 +#define BF_BF_B5E15A20_INFO(inst) ((inst) + 0x00000001), 0x00000102 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0002_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000002) +#define BF_BF_80682486_INFO(inst) ((inst) + 0x00000002), 0x00000100 +#define BF_BF_0CEA8917_INFO(inst) ((inst) + 0x00000002), 0x00000101 +#define BF_BF_CAA8A3A9_INFO(inst) ((inst) + 0x00000002), 0x00000102 +#define BF_BF_EF17F471_INFO(inst) ((inst) + 0x00000002), 0x00000103 +#define BF_BF_FB0A16E3_INFO(inst) ((inst) + 0x00000002), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0003_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000003) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0004_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000004) +#define BF_BF_D715BF87_INFO(inst) ((inst) + 0x00000004), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0005_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000005) +#define BF_BF_AF3E1E65_INFO(inst) ((inst) + 0x00000005), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0006_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000006) +#define BF_BF_5050CF8A_INFO(inst) ((inst) + 0x00000006), 0x00000100 +#define BF_BF_F92DEBA5_INFO(inst) ((inst) + 0x00000006), 0x00000101 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0007_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000007) +#define BF_BF_CBBB0A1D_INFO(inst) ((inst) + 0x00000007), 0x00000100 +#define BF_BF_0EC38FEC_INFO(inst) ((inst) + 0x00000007), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0008_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000008) +#define BF_BF_D6319B8F_INFO(inst) ((inst) + 0x00000008), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0009_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000009) +#define BF_BF_C151B9C1_INFO(inst) ((inst) + 0x00000009), 0x00000300 +#define BF_BF_785765B5_INFO(inst) ((inst) + 0x00000009), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X000A_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x0000000A) +#define BF_BF_F0EFD958_INFO(inst) ((inst) + 0x0000000A), 0x00000300 +#define BF_BF_3617B926_INFO(inst) ((inst) + 0x0000000A), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X000B_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x0000000B) +#define BF_BF_0827E611_INFO(inst) ((inst) + 0x0000000B), 0x00000300 +#define BF_BF_92C4A8D5_INFO(inst) ((inst) + 0x0000000B), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X000C_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x0000000C) +#define BF_BF_0CACD55E_INFO(inst) ((inst) + 0x0000000C), 0x00000300 +#define BF_BF_460694AB_INFO(inst) ((inst) + 0x0000000C), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X000D_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x0000000D) +#define BF_BF_585C1963_INFO(inst) ((inst) + 0x0000000D), 0x00000300 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X000E_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x0000000E) +#define BF_BF_16C1981F_INFO(inst) ((inst) + 0x0000000E), 0x00000200 +#define BF_BF_AC531167_INFO(inst) ((inst) + 0x0000000E), 0x00000202 +#define BF_BF_9FC9112E_INFO(inst) ((inst) + 0x0000000E), 0x00000204 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X000F_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x0000000F) +#define BF_BF_3E5198E9_INFO(inst) ((inst) + 0x0000000F), 0x00000300 +#define BF_BF_F7E42D50_INFO(inst) ((inst) + 0x0000000F), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0010_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000010) +#define BF_BF_57DBD614_INFO(inst) ((inst) + 0x00000010), 0x00000200 +#define BF_BF_6FA8186A_INFO(inst) ((inst) + 0x00000010), 0x00000204 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0011_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000011) +#define BF_BF_8BF62269_INFO(inst) ((inst) + 0x00000011), 0x00000500 +#define BF_BF_2BDB14F1_INFO(inst) ((inst) + 0x00000011), 0x00000105 +#define BF_BF_3038DD87_INFO(inst) ((inst) + 0x00000011), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0012_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000012) +#define BF_BF_71FC3AF9_INFO(inst) ((inst) + 0x00000012), 0x00000500 +#define BF_BF_AA7CEFFF_INFO(inst) ((inst) + 0x00000012), 0x00000105 +#define BF_BF_16BCA3C2_INFO(inst) ((inst) + 0x00000012), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0013_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000013) +#define BF_BF_899E4BBF_INFO(inst) ((inst) + 0x00000013), 0x00000300 +#define BF_BF_F3A4F067_INFO(inst) ((inst) + 0x00000013), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0014_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000014) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0015_ACTRL_WEST__OPEN_ADDR(inst, n) ((inst) + 0x00000015 + 1 * (n)) +#define BF_BF_4EB392BF_INFO(inst, n) ((inst) + 0x00000015 + 1 * (n)), 0x00000200 +#define BF_BF_D8B30366_INFO(inst, n) ((inst) + 0x00000015 + 1 * (n)), 0x00000202 +#define BF_BF_20CE60BB_INFO(inst, n) ((inst) + 0x00000015 + 1 * (n)), 0x00000204 +#define BF_BF_9203C058_INFO(inst, n) ((inst) + 0x00000015 + 1 * (n)), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X001D_ACTRL_WEST__OPEN_ADDR(inst, n) ((inst) + 0x0000001D + 1 * (n)) +#define BF_BF_4E03658F_INFO(inst, n) ((inst) + 0x0000001D + 1 * (n)), 0x00000200 +#define BF_BF_B1068A5B_INFO(inst, n) ((inst) + 0x0000001D + 1 * (n)), 0x00000202 +#define BF_BF_75F3304F_INFO(inst, n) ((inst) + 0x0000001D + 1 * (n)), 0x00000204 +#define BF_BF_2C2ED0CC_INFO(inst, n) ((inst) + 0x0000001D + 1 * (n)), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0025_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000025) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0026_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000026) +#define BF_BF_DC640D74_INFO(inst) ((inst) + 0x00000026), 0x00000300 +#define BF_BF_EC909415_INFO(inst) ((inst) + 0x00000026), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0027_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000027) +#define BF_BF_8BC429B9_INFO(inst) ((inst) + 0x00000027), 0x00000300 +#define BF_BF_17B15B87_INFO(inst) ((inst) + 0x00000027), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0028_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000028) +#define BF_BF_5AAF89C8_INFO(inst) ((inst) + 0x00000028), 0x00000300 +#define BF_BF_19109ACE_INFO(inst) ((inst) + 0x00000028), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0029_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000029) +#define BF_BF_8DF4690C_INFO(inst) ((inst) + 0x00000029), 0x00000300 +#define BF_BF_0FC925AE_INFO(inst) ((inst) + 0x00000029), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X002A_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x0000002A) +#define BF_BF_6F3D1EB2_INFO(inst) ((inst) + 0x0000002A), 0x00000300 +#define BF_BF_06BFDD4F_INFO(inst) ((inst) + 0x0000002A), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X002B_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x0000002B) +#define BF_BF_A748C638_INFO(inst) ((inst) + 0x0000002B), 0x00000300 +#define BF_BF_BEA5A3D9_INFO(inst) ((inst) + 0x0000002B), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X002C_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x0000002C) +#define BF_BF_3D67E04C_INFO(inst) ((inst) + 0x0000002C), 0x00000300 +#define BF_BF_53D60460_INFO(inst) ((inst) + 0x0000002C), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X002D_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x0000002D) +#define BF_BF_AF725B34_INFO(inst) ((inst) + 0x0000002D), 0x00000300 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X002E_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x0000002E) +#define BF_BF_3838C9C7_INFO(inst) ((inst) + 0x0000002E), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X002F_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x0000002F) +#define BF_BF_BC7ABCEF_INFO(inst) ((inst) + 0x0000002F), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0030_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000030) +#define BF_BF_5EDCE83D_INFO(inst) ((inst) + 0x00000030), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0031_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000031) +#define BF_BF_12A41045_INFO(inst) ((inst) + 0x00000031), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0032_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000032) +#define BF_BF_818EAAB9_INFO(inst) ((inst) + 0x00000032), 0x00000300 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0033_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000033) +#define BF_BF_D909CB45_INFO(inst) ((inst) + 0x00000033), 0x00000100 +#define BF_BF_9B37C1EE_INFO(inst) ((inst) + 0x00000033), 0x00000201 +#define BF_BF_EAD5C9CD_INFO(inst) ((inst) + 0x00000033), 0x00000103 +#define BF_BF_E751D2E0_INFO(inst) ((inst) + 0x00000033), 0x00000104 +#define BF_BF_85E41FBC_INFO(inst) ((inst) + 0x00000033), 0x00000105 +#define BF_BF_8113DC9C_INFO(inst) ((inst) + 0x00000033), 0x00000106 +#define BF_BF_C3E8EB1D_INFO(inst) ((inst) + 0x00000033), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0034_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000034) +#define BF_BF_6F17ED86_INFO(inst) ((inst) + 0x00000034), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0035_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000035) +#define BF_BF_831942C1_INFO(inst) ((inst) + 0x00000035), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0036_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000036) +#define BF_BF_4B0B8019_INFO(inst) ((inst) + 0x00000036), 0x00000300 +#define BF_BF_D3FA0DFF_INFO(inst) ((inst) + 0x00000036), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0037_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000037) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0038_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000038) +#define BF_BF_F2B9F109_INFO(inst) ((inst) + 0x00000038), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0039_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000039) +#define BF_BF_459ACF5C_INFO(inst) ((inst) + 0x00000039), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X003A_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x0000003A) +#define BF_BF_DA32E51D_ACTRL_WEST__OPEN_INFO(inst) ((inst) + 0x0000003A), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X003B_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x0000003B) +#define BF_BF_ECECD989_ACTRL_WEST__OPEN_INFO(inst) ((inst) + 0x0000003B), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X003C_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x0000003C) +#define BF_BF_246AC3B1_ACTRL_WEST__OPEN_INFO(inst) ((inst) + 0x0000003C), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X003D_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x0000003D) +#define BF_BF_CB8D6E7B_ACTRL_WEST__OPEN_INFO(inst) ((inst) + 0x0000003D), 0x00000300 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X003E_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x0000003E) +#define BF_BF_E71A6D16_INFO(inst) ((inst) + 0x0000003E), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X003F_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x0000003F) +#define BF_BF_5F1C3B7E_INFO(inst) ((inst) + 0x0000003F), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0040_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000040) +#define BF_BF_04557BC8_INFO(inst) ((inst) + 0x00000040), 0x00000300 +#define BF_BF_568AB02F_INFO(inst) ((inst) + 0x00000040), 0x00000303 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0041_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000041) +#define BF_BF_97907FC4_INFO(inst) ((inst) + 0x00000041), 0x00000300 +#define BF_BF_40FAEF21_INFO(inst) ((inst) + 0x00000041), 0x00000303 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0042_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000042) +#define BF_BF_6653AD72_INFO(inst) ((inst) + 0x00000042), 0x00000400 +#define BF_BF_F95A48BC_INFO(inst) ((inst) + 0x00000042), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0043_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000043) +#define BF_BF_85EDE74B_INFO(inst) ((inst) + 0x00000043), 0x00000300 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0044_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000044) + +#define REG_REG_0X0045_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000045) + +#define REG_REG_0X0046_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000046) + +#define REG_REG_0X0047_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000047) + +#define REG_REG_0X0048_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000048) + +#define REG_REG_0X0049_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000049) + +#define REG_REG_0X004A_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x0000004A) + +#define REG_REG_0X004B_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x0000004B) + +#define REG_REG_0X004C_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x0000004C) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X004D_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x0000004D) +#define BF_BF_6D240534_INFO(inst) ((inst) + 0x0000004D), 0x00000200 +#define BF_BF_30B90B4D_INFO(inst) ((inst) + 0x0000004D), 0x00000202 +#define BF_BF_F7942724_INFO(inst) ((inst) + 0x0000004D), 0x00000204 +#define BF_BF_CF92A541_INFO(inst) ((inst) + 0x0000004D), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X004E_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x0000004E) +#define BF_BF_8B25C9FE_INFO(inst) ((inst) + 0x0000004E), 0x00000400 +#define BF_BF_DF7E2BC6_INFO(inst) ((inst) + 0x0000004E), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X004F_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x0000004F) +#define BF_BF_AD94D2D6_INFO(inst) ((inst) + 0x0000004F), 0x00000400 +#define BF_BF_EBDB1917_INFO(inst) ((inst) + 0x0000004F), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0050_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000050) +#define BF_BF_80470963_INFO(inst) ((inst) + 0x00000050), 0x00000400 +#define BF_BF_9BC834E1_INFO(inst) ((inst) + 0x00000050), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0051_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000051) +#define BF_BF_E152813D_INFO(inst) ((inst) + 0x00000051), 0x00000400 +#define BF_BF_EDF345ED_INFO(inst) ((inst) + 0x00000051), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0055_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000055) +#define BF_BF_2BD68F04_ACTRL_WEST__OPEN_INFO(inst) ((inst) + 0x00000055), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0056_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000056) +#define BF_BF_6F0E76C0_ACTRL_WEST__OPEN_INFO(inst) ((inst) + 0x00000056), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0057_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000057) +#define BF_BF_1DECF0B5_ACTRL_WEST__OPEN_INFO(inst) ((inst) + 0x00000057), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0058_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000058) +#define BF_BF_C5EBC8EF_ACTRL_WEST__OPEN_INFO(inst) ((inst) + 0x00000058), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0059_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000059) +#define BF_BF_C9878C07_ACTRL_WEST__OPEN_INFO(inst) ((inst) + 0x00000059), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X005A_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x0000005A) +#define BF_BF_A8BAEFD3_ACTRL_WEST__OPEN_INFO(inst) ((inst) + 0x0000005A), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_ACTRL_SCRATCH_END_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x000003FF) +#define BF_ACTRL_SCRATCH_END_ACTRL_WEST__OPEN_INFO(inst) ((inst) + 0x000003FF), 0x00000800 + +#endif /* __ADI_APOLLO_BF_ACTRL_WEST_OPEN_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_ahb_arm_dap_regs.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_ahb_arm_dap_regs.h new file mode 100644 index 00000000000000..72e5d42fd29f57 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_ahb_arm_dap_regs.h @@ -0,0 +1,33 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:17 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_AHB_ARM_DAP_REGS_H__ +#define __ADI_APOLLO_BF_AHB_ARM_DAP_REGS_H__ + +/*============= D E F I N E S ==============*/ +#define REG_IDCODE_ADDR 0x46810000 +#define BF_ID_CODE_INFO 0x46810000, 0x00002000 + +#define REG_CTRL_STAT_ADDR 0x46810004 +#define BF_ABORT_AHB_ARM_DAP_REGS_INFO 0x46810004, 0x00000100 +#define BF_DEBUG_POWER_UP_REQ_INFO 0x46810004, 0x0000011C +#define BF_DEBUG_POWER_UP_ACK_INFO 0x46810004, 0x0000011D +#define BF_SYSTEM_POWER_UP_REQ_INFO 0x46810004, 0x0000011E +#define BF_SYSTEM_POWER_UP_ACK_INFO 0x46810004, 0x0000011F + +#define REG_SELECT_ADDR 0x46810008 +#define BF_AP_BANKSEL_INFO 0x46810008, 0x00000404 + +#endif /* __ADI_APOLLO_BF_AHB_ARM_DAP_REGS_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_apollo_profile_config.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_apollo_profile_config.h new file mode 100644 index 00000000000000..5cd7cafa714d17 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_apollo_profile_config.h @@ -0,0 +1,128 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:18 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_APOLLO_PROFILE_CONFIG_H__ +#define __ADI_APOLLO_BF_APOLLO_PROFILE_CONFIG_H__ + +/*============= D E F I N E S ==============*/ +#define REG_PROFILE_FCN_SEL_REG_ADDR 0x4C004600 +#define BF_PROFILE_FCN_SEL_INFO 0x4C004600, 0x00000400 +#define BF_FCN_SEL_SPI_GPIO_INFO 0x4C004600, 0x00000104 + +#define REG_FNCO_SLICE_SELECT_REG_ADDR 0x4C004604 +#define BF_RX_FNCO_A_SLICE_SELECT_INFO 0x4C004604, 0x00000800 +#define BF_RX_FNCO_B_SLICE_SELECT_INFO 0x4C004604, 0x00000808 +#define BF_TX_FNCO_A_SLICE_SELECT_INFO 0x4C004604, 0x00000810 +#define BF_TX_FNCO_B_SLICE_SELECT_INFO 0x4C004604, 0x00000818 + +#define REG_CNCO_SLICE_SELECT_REG_ADDR 0x4C004608 +#define BF_RX_CNCO_A_SLICE_SELECT_INFO 0x4C004608, 0x00000400 +#define BF_RX_CNCO_B_SLICE_SELECT_INFO 0x4C004608, 0x00000404 +#define BF_TX_CNCO_A_SLICE_SELECT_INFO 0x4C004608, 0x00000408 +#define BF_TX_CNCO_B_SLICE_SELECT_INFO 0x4C004608, 0x0000040C + +#define REG_CFIR_SLICE_SELECT_REG_ADDR 0x4C00460C +#define BF_RX_CFIR_A_SLICE_SELECT_INFO 0x4C00460C, 0x00000800 +#define BF_RX_CFIR_B_SLICE_SELECT_INFO 0x4C00460C, 0x00000808 +#define BF_TX_CFIR_A_SLICE_SELECT_INFO 0x4C00460C, 0x00000810 +#define BF_TX_CFIR_B_SLICE_SELECT_INFO 0x4C00460C, 0x00000818 + +#define REG_PFILT_SLICE_SELECT_REG_ADDR 0x4C004610 +#define BF_RX_PFILT_A_SLICE_SELECT_INFO 0x4C004610, 0x00000100 +#define BF_RX_PFILT_B_SLICE_SELECT_INFO 0x4C004610, 0x00000101 +#define BF_TX_PFILT_A_SLICE_SELECT_INFO 0x4C004610, 0x00000102 +#define BF_TX_PFILT_B_SLICE_SELECT_INFO 0x4C004610, 0x00000103 + +#define REG_DYN_CONFIG_SLICE_SELECT_REG_ADDR 0x4C004614 +#define BF_RX_DYN_CONFIG_A_SLICE_SELECT_INFO 0x4C004614, 0x00000400 +#define BF_RX_DYN_CONFIG_B_SLICE_SELECT_INFO 0x4C004614, 0x00000404 +#define BF_TX_DYN_CONFIG_A_SLICE_SELECT_INFO 0x4C004614, 0x00000408 +#define BF_TX_DYN_CONFIG_B_SLICE_SELECT_INFO 0x4C004614, 0x0000040C + +#define REG_BMEM_HOP_SLICE_SELECT_REG_ADDR 0x4C004618 +#define BF_RX_BMEM_HOP_A_SLICE_SELECT_INFO 0x4C004618, 0x00000200 +#define BF_RX_BMEM_HOP_B_SLICE_SELECT_INFO 0x4C004618, 0x00000202 + +#define REG_FNCO_PFILT_SLICE_SELECT_REG_ADDR 0x4C00461C +#define BF_RX_FNCO_PFILT_A_SLICE_SELECT_INFO 0x4C00461C, 0x00000800 +#define BF_RX_FNCO_PFILT_B_SLICE_SELECT_INFO 0x4C00461C, 0x00000808 +#define BF_TX_FNCO_PFILT_A_SLICE_SELECT_INFO 0x4C00461C, 0x00000810 +#define BF_TX_FNCO_PFILT_B_SLICE_SELECT_INFO 0x4C00461C, 0x00000818 + +#define REG_FNCO_CFIR_SLICE_SELECT_REG_ADDR 0x4C004620 +#define BF_RX_FNCO_CFIR_A_SLICE_SELECT_INFO 0x4C004620, 0x00000800 +#define BF_RX_FNCO_CFIR_B_SLICE_SELECT_INFO 0x4C004620, 0x00000808 +#define BF_TX_FNCO_CFIR_A_SLICE_SELECT_INFO 0x4C004620, 0x00000810 +#define BF_TX_FNCO_CFIR_B_SLICE_SELECT_INFO 0x4C004620, 0x00000818 + +#define REG_FNCO_CNCO_SLICE_SELECT_REG_ADDR 0x4C004624 +#define BF_RX_FNCO_CNCO_A_SLICE_SELECT_INFO 0x4C004624, 0x00000800 +#define BF_RX_FNCO_CNCO_B_SLICE_SELECT_INFO 0x4C004624, 0x00000808 +#define BF_TX_FNCO_CNCO_A_SLICE_SELECT_INFO 0x4C004624, 0x00000810 +#define BF_TX_FNCO_CNCO_B_SLICE_SELECT_INFO 0x4C004624, 0x00000818 + +#define REG_PFILT_CFIR_SLICE_SELECT_REG_ADDR 0x4C004628 +#define BF_RX_PFILT_CFIR_A_SLICE_SELECT_INFO 0x4C004628, 0x00000800 +#define BF_RX_PFILT_CFIR_B_SLICE_SELECT_INFO 0x4C004628, 0x00000808 +#define BF_TX_PFILT_CFIR_A_SLICE_SELECT_INFO 0x4C004628, 0x00000810 +#define BF_TX_PFILT_CFIR_B_SLICE_SELECT_INFO 0x4C004628, 0x00000818 + +#define REG_CNCO_PFILT_SLICE_SELECT_REG_ADDR 0x4C00462C +#define BF_RX_CNCO_PFILT_A_SLICE_SELECT_INFO 0x4C00462C, 0x00000400 +#define BF_RX_CNCO_PFILT_B_SLICE_SELECT_INFO 0x4C00462C, 0x00000404 +#define BF_TX_CNCO_PFILT_A_SLICE_SELECT_INFO 0x4C00462C, 0x00000408 +#define BF_TX_CNCO_PFILT_B_SLICE_SELECT_INFO 0x4C00462C, 0x0000040C + +#define REG_FNCO_CNCO_PROFILE_MAP_WORD0_ADDR 0x4C004630 + +#define REG_FNCO_CNCO_PROFILE_MAP_WORD1_ADDR 0x4C004634 + +#define REG_FNCO_CNCO_PROFILE_MAP_WORD2_ADDR 0x4C004638 + +#define REG_FNCO_CNCO_PROFILE_MAP_WORD3_ADDR 0x4C00463C + +#define REG_FNCO_PFILT_PROFILE_MAP_WORD0_ADDR 0x4C004640 +#define BF_FNCO_PFILT_PROFILE_MAP_INFO 0x4C004640, 0x00004000 + +#define REG_FNCO_PFILT_PROFILE_MAP_WORD1_ADDR 0x4C004644 + +#define REG_FNCO_CFIR_PROFILE_MAP_WORD0_ADDR 0x4C004648 +#define BF_FNCO_CFIR_PROFILE_MAP_INFO 0x4C004648, 0x00002000 + +#define REG_PFILT_CFIR_PROFILE_MAP_WORD0_ADDR 0x4C00464C +#define BF_PFILT_CFIR_PROFILE_MAP_INFO 0x4C00464C, 0x00000400 + +#define REG_CNCO_PFILT_PROFILE_MAP_WORD0_ADDR 0x4C004650 +#define BF_CNCO_PFILT_PROFILE_MAP_INFO 0x4C004650, 0x00002000 + +#define REG_SPI_GPIO_SELECT_REG_ADDR 0x4C004654 +#define BF_FNCO_SLICE_SELECT_SPI_GPIO_INFO 0x4C004654, 0x00000100 +#define BF_CNCO_SLICE_SELECT_SPI_GPIO_INFO 0x4C004654, 0x00000101 +#define BF_PFILT_SLICE_SELECT_SPI_GPIO_INFO 0x4C004654, 0x00000102 +#define BF_CFIR_SLICE_SELECT_SPI_GPIO_INFO 0x4C004654, 0x00000103 +#define BF_CNCO_PFILT_SLICE_SELECT_SPI_GPIO_INFO 0x4C004654, 0x00000104 +#define BF_PFILT_CFIR_SLICE_SELECT_SPI_GPIO_INFO 0x4C004654, 0x00000105 +#define BF_FNCO_CNCO_SLICE_SELECT_SPI_GPIO_INFO 0x4C004654, 0x00000106 +#define BF_FNCO_CFIR_SLICE_SELECT_SPI_GPIO_INFO 0x4C004654, 0x00000107 +#define BF_DYN_CONFIG_SLICE_SELECT_SPI_GPIO_INFO 0x4C004654, 0x00000108 +#define BF_FNCO_PFILT_SLICE_SELECT_SPI_GPIO_INFO 0x4C004654, 0x00000109 +#define BF_BMEM_HOP_SLICE_SELECT_SPI_GPIO_INFO 0x4C004654, 0x0000010A +#define BF_FNCO_CNCO_PROFILE_MAP_SPI_GPIO_INFO 0x4C004654, 0x0000010B +#define BF_FNCO_PFILT_PROFILE_MAP_SPI_GPIO_INFO 0x4C004654, 0x0000010C +#define BF_FNCO_CFIR_PROFILE_MAP_SPI_GPIO_INFO 0x4C004654, 0x0000010D +#define BF_PFILT_CFIR_PROFILE_MAP_SPI_GPIO_INFO 0x4C004654, 0x0000010E +#define BF_CNCO_PFILT_PROFILE_MAP_SPI_GPIO_INFO 0x4C004654, 0x0000010F + +#endif /* __ADI_APOLLO_BF_APOLLO_PROFILE_CONFIG_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_c2c_mailbox_dst.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_c2c_mailbox_dst.h new file mode 100644 index 00000000000000..47d20ddb3e23ac --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_c2c_mailbox_dst.h @@ -0,0 +1,43 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:17 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_C2C_MAILBOX_DST_H__ +#define __ADI_APOLLO_BF_C2C_MAILBOX_DST_H__ + +/*============= D E F I N E S ==============*/ +#define REG_ARM_CMD_1_C2C_MAILBOX_DST_ADDR 0x41800000 +#define BF_ARM_COMMAND_DST_INFO 0x41800000, 0x00003800 +#define BF_STALL_SRC_AHB_EN_DST_INFO 0x41800000, 0x0000011E +#define BF_ARM_COMMAND_BUSY_C2C_MAILBOX_DST_INFO 0x41800000, 0x0000011F + +#define REG_ARM_CMD_2_C2C_MAILBOX_DST_ADDR 0x41800004 + +#define REG_ARM_STATUS_1_C2C_MAILBOX_DST_ADDR 0x41800008 +#define BF_ARM_STATUS_DST_1_INFO 0x41800008, 0x00002000 + +#define REG_ARM_STATUS_2_C2C_MAILBOX_DST_ADDR 0x4180000C +#define BF_ARM_STATUS_DST_2_INFO 0x4180000C, 0x00001E00 +#define BF_STREAM_PROC_ARM_STATUS_C2C_MAILBOX_DST_INFO 0x4180000C, 0x0000021E + +#define REG_ARM_STATUS_3_C2C_MAILBOX_DST_ADDR 0x41800010 +#define BF_ARM_STATUS_DST_3_INFO 0x41800010, 0x00002000 + +#define REG_ARM_STATUS_4_C2C_MAILBOX_DST_ADDR 0x41800014 +#define BF_ARM_STATUS_DST_4_INFO 0x41800014, 0x00002000 + +#define REG_ARM_GPIO_VAL_C2C_MAILBOX_DST_ADDR 0x41800018 +#define BF_GPIO_VAL_DST_INFO 0x41800018, 0x00001000 + +#endif /* __ADI_APOLLO_BF_C2C_MAILBOX_DST_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_c2c_mailbox_src.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_c2c_mailbox_src.h new file mode 100644 index 00000000000000..af4f27fbe40954 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_c2c_mailbox_src.h @@ -0,0 +1,43 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:17 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_C2C_MAILBOX_SRC_H__ +#define __ADI_APOLLO_BF_C2C_MAILBOX_SRC_H__ + +/*============= D E F I N E S ==============*/ +#define REG_ARM_CMD_1_C2C_MAILBOX_SRC_ADDR 0x41700000 +#define BF_ARM_COMMAND_SRC_INFO 0x41700000, 0x00003800 +#define BF_STALL_SRC_AHB_EN_SRC_INFO 0x41700000, 0x0000011E +#define BF_ARM_COMMAND_BUSY_C2C_MAILBOX_SRC_INFO 0x41700000, 0x0000011F + +#define REG_ARM_CMD_2_C2C_MAILBOX_SRC_ADDR 0x41700004 + +#define REG_ARM_STATUS_1_C2C_MAILBOX_SRC_ADDR 0x41700008 +#define BF_ARM_STATUS_SRC_1_INFO 0x41700008, 0x00002000 + +#define REG_ARM_STATUS_2_C2C_MAILBOX_SRC_ADDR 0x4170000C +#define BF_ARM_STATUS_SRC_2_INFO 0x4170000C, 0x00001E00 +#define BF_STREAM_PROC_ARM_STATUS_C2C_MAILBOX_SRC_INFO 0x4170000C, 0x0000021E + +#define REG_ARM_STATUS_3_C2C_MAILBOX_SRC_ADDR 0x41700010 +#define BF_ARM_STATUS_SRC_3_INFO 0x41700010, 0x00002000 + +#define REG_ARM_STATUS_4_C2C_MAILBOX_SRC_ADDR 0x41700014 +#define BF_ARM_STATUS_SRC_4_INFO 0x41700014, 0x00002000 + +#define REG_ARM_GPIO_VAL_C2C_MAILBOX_SRC_ADDR 0x41700018 +#define BF_GPIO_VAL_SRC_INFO 0x41700018, 0x00001000 + +#endif /* __ADI_APOLLO_BF_C2C_MAILBOX_SRC_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_conv_pow_onoff.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_conv_pow_onoff.h new file mode 100644 index 00000000000000..dd15f122dad1ee --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_conv_pow_onoff.h @@ -0,0 +1,40 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:18 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_CONV_POW_ONOFF_H__ +#define __ADI_APOLLO_BF_CONV_POW_ONOFF_H__ + +/*============= D E F I N E S ==============*/ +#define REG_CONFIG_ADDR(n) (0x4C004000 + 1 * (n)) +#define BF_MUX_SELECT_INFO(n) (0x4C004000 + 1 * (n)), 0x00000500 +#define BF_COUNTER_BYPASS_EN_INFO(n) (0x4C004000 + 1 * (n)), 0x00000105 +#define BF_POWER_EN_MASK_INFO(n) (0x4C004000 + 1 * (n)), 0x00000106 +#define BF_TRIGGER_POLARITY_INVERT_INFO(n) (0x4C004000 + 1 * (n)), 0x00000107 + +#define REG_THRESH_HL_BYTE0_ADDR(n) (0x4C004010 + 3 * (n)) +#define BF_THRESH_HL_INFO(n) (0x4C004010 + 3 * (n)), 0x00001800 + +#define REG_THRESH_HL_BYTE1_ADDR(n) (0x4C004011 + 3 * (n)) + +#define REG_THRESH_HL_BYTE2_ADDR(n) (0x4C004012 + 3 * (n)) + +#define REG_THRESH_LH_BYTE0_ADDR(n) (0x4C004040 + 3 * (n)) +#define BF_THRESH_LH_INFO(n) (0x4C004040 + 3 * (n)), 0x00001800 + +#define REG_THRESH_LH_BYTE1_ADDR(n) (0x4C004041 + 3 * (n)) + +#define REG_THRESH_LH_BYTE2_ADDR(n) (0x4C004042 + 3 * (n)) + +#endif /* __ADI_APOLLO_BF_CONV_POW_ONOFF_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_core.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_core.h new file mode 100644 index 00000000000000..5ec5ea0f58fc5a --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_core.h @@ -0,0 +1,2326 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:17 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_CORE_H__ +#define __ADI_APOLLO_BF_CORE_H__ + +/*============= D E F I N E S ==============*/ +#ifdef USE_PRIVATE_BF +#define REG_SPI_IFACE_CONFIG_A_ADDR 0x47000000 +#define BF_SOFT_RESET_0_INFO 0x47000000, 0x00000100 +#define BF_LSB_FIRST_1_INFO 0x47000000, 0x00000101 +#define BF_ADDR_ASCENSION_2_INFO 0x47000000, 0x00000102 +#define BF_SDO_ACTIVE_3_INFO 0x47000000, 0x00000103 +#define BF_SDO_ACTIVE_4_INFO 0x47000000, 0x00000104 +#define BF_ADDR_ASCENSION_5_INFO 0x47000000, 0x00000105 +#define BF_LSB_FIRST_6_INFO 0x47000000, 0x00000106 +#define BF_SOFT_RESET_7_INFO 0x47000000, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_SPI_IFACE_CONFIG_B_ADDR 0x47000001 +#define BF_SOFT_RESET_001_1_INFO 0x47000001, 0x00000101 +#define BF_SOFT_RESET_001_2_INFO 0x47000001, 0x00000102 +#define BF_SLOW_IFACE_CTL_INFO 0x47000001, 0x00000104 +#define BF_MASTER_SLAVE_READBACK_CTL_INFO 0x47000001, 0x00000105 +#define BF_CSB_STALL_INFO 0x47000001, 0x00000106 +#define BF_SINGLE_INSTRUCTION_INFO 0x47000001, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_DEVICE_CONFIG_ADDR 0x47000002 +#define BF_DEVICE_CONFIG_OP_MODES_INFO 0x47000002, 0x00000200 +#define BF_DEVICE_CONFIG_CUSTOM_OP_MODES_INFO 0x47000002, 0x00000202 +#define BF_DEVICE_CONFIG_STATUS_INFO 0x47000002, 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#define REG_CHIP_TYPE_ADDR 0x47000003 +#define BF_CHIP_TYPE_INFO 0x47000003, 0x00000800 + +#define REG_PRODUCT_ID_0_ADDR 0x47000004 +#define BF_PRODUCT_ID_0_INFO 0x47000004, 0x00000800 + +#define REG_PRODUCT_ID_1_ADDR 0x47000005 +#define BF_PRODUCT_ID_1_INFO 0x47000005, 0x00000800 + +#define REG_CHIP_GRADE_ADDR 0x47000006 +#define BF_CHIP_GRADE_LOWER_NIBBLE_INFO 0x47000006, 0x00000400 +#define BF_CHIP_GRADE_UPPER_NIBBLE_INFO 0x47000006, 0x00000404 + +#ifdef USE_PRIVATE_BF +#define REG_DIE_ID_ADDR 0x47000007 +#define BF_MASK_REVISION_MINOR_INFO 0x47000007, 0x00000400 +#define BF_MASK_REVISION_MAJOR_INFO 0x47000007, 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_OFFSET_POINTER_DEVICE_INDEX_ADDR 0x47000008 +#define BF_PAGE_POINTER_DEVICE_INDEX_VALUE_0_INFO 0x47000008, 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_DEVICE_INDEX_ADDR 0x47000009 +#define BF_PAGE_POINTER_DEVICE_INDEX_VALUE_1_INFO 0x47000009, 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_SCRATCH_PAD_ADDR 0x4700000A +#define BF_SCRATCH_PAD_WORD_INFO 0x4700000A, 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_SPI_REVISION_ADDR 0x4700000B +#define BF_SPI_CONTROLLER_DOC_REVISION_INFO 0x4700000B, 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_VENDOR_ID_0_ADDR 0x4700000C +#define BF_VENDOR_ID_INFO 0x4700000C, 0x00001000 + +#define REG_VENDOR_ID_1_ADDR 0x4700000D + +#ifdef USE_PRIVATE_BF +#define REG_LAMINATE_ID_ADDR 0x4700000E +#define BF_LAMINATE_ID_INFO 0x4700000E, 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TRANSFER_REG_ADDR 0x4700000F +#define BF_MASTER_SLAVE_TRANSFER_BIT_INFO 0x4700000F, 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_SPI_FIFO_MODE_REG_ADDR 0x47000010 +#define BF_SPI_FIFO_MODE_INFO 0x47000010, 0x00000300 +#endif /* USE_PRIVATE_BF */ + +#define REG_FW_REV_RESERVED_ADDR 0x47000011 +#define BF_FW_REV_INFO 0x47000011, 0x00002000 + +#define REG_FW_REV_PATCH_ADDR 0x47000012 + +#define REG_FW_REV_MINOR_ADDR 0x47000013 + +#define REG_FW_REV_MAJOR_ADDR 0x47000014 + +#ifdef USE_PRIVATE_BF +#define REG_SPI1_ENABLE_ADDR 0x47000015 +#define BF_SPI1_EN_INFO 0x47000015, 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#define REG_CLOCK_CONTROL_0_ADDR 0x47000017 +#define BF_UP_RTCLK_DIV_CORE_INFO 0x47000017, 0x00000400 +#define BF_UP_RTCLK_DIV_UPDT_CORE_INFO 0x47000017, 0x00000104 +#ifdef USE_PRIVATE_BF +#define BF_ROSC_BACKUP_CLK_SELECT_INFO 0x47000017, 0x00000105 +#endif /* USE_PRIVATE_BF */ + +#define REG_CLOCK_CONTROL_1_ADDR 0x47000018 +#define BF_ASYNC_CLK_MUX_BYPASS_INFO 0x47000018, 0x00000100 +#ifdef USE_PRIVATE_BF +#define BF_DIG_REF_CLK_DIV_RATIO_INFO 0x47000018, 0x00000302 +#endif /* USE_PRIVATE_BF */ +#define BF_ROSC_CLK_DEBUG_DIV_RATIO_INFO 0x47000018, 0x00000205 + +#ifdef USE_PRIVATE_BF +#define REG_CLOCK_CONTROL_2_ADDR 0x47000019 +#define BF_DIGITAL_CLOCK_POWER_UP_INFO 0x47000019, 0x00000106 +#define BF_USE_DEVICE_CLK_AS_HSDIGCLK_INFO 0x47000019, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#define REG_OTP_CLK_CONTROL_ADDR 0x4700001B +#define BF_OTP_CLK_DIV_RATIO_INFO 0x4700001B, 0x00000600 +#define BF_OTP_CLK_ENABLE_INFO 0x4700001B, 0x00000106 + +#ifdef USE_PRIVATE_BF +#define REG_REFERENCE_CLOCK_CYCLES_ADDR 0x4700001C +#define BF_REFERENCE_CLOCK_CYCLES_CORE_INFO 0x4700001C, 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_TRACE_CLK_GEN_DIV_VAL_ADDR 0x4700001D +#define BF_TRACE_CLK_GEN_DIV_VAL_INFO 0x4700001D, 0x00000700 + +#ifdef USE_PRIVATE_BF +#define REG_AHB_SPI_BRIDGE_ADDR 0x4700001F +#define BF_AHB_SPI_BRIDGE_ENABLE_INFO 0x4700001F, 0x00000100 +#define BF_SPI_ARB_DISABLE_RESP_INFO 0x4700001F, 0x00000105 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARM0_CTL_ADDR 0x47000021 +#define BF_ARM0_M3_RUN_INFO 0x47000021, 0x00000100 +#define BF_ARM0_ERROR_INFO 0x47000021, 0x00000101 +#define BF_ARM0_MEM_HRESP_MASK_INFO 0x47000021, 0x00000103 +#define BF_ARM0_DEBUG_ENABLE_INFO 0x47000021, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARM0_RESET_ADDR 0x47000022 +#define BF_ARM0_FORCE_RESET_INFO 0x47000022, 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARM0_BOOT_ADDR_BYTE0_ADDR 0x47000023 +#define BF_ARM0_BOOT_ADDR_INFO 0x47000023, 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_ARM0_BOOT_ADDR_BYTE1_ADDR 0x47000024 + +#define REG_ARM0_BOOT_ADDR_BYTE2_ADDR 0x47000025 + +#define REG_ARM0_BOOT_ADDR_BYTE3_ADDR 0x47000026 + +#ifdef USE_PRIVATE_BF +#define REG_ARM0_STACK_PTR_BYTE_0_ADDR 0x47000027 +#define BF_ARM0_STACK_PTR_INFO 0x47000027, 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_ARM0_STACK_PTR_BYTE_1_ADDR 0x47000028 + +#define REG_ARM0_STACK_PTR_BYTE_2_ADDR 0x47000029 + +#define REG_ARM0_STACK_PTR_BYTE_3_ADDR 0x4700002A + +#ifdef USE_PRIVATE_BF +#define REG_L1MEM0_ECC_CONTROL_ADDR 0x4700003A +#define BF_L1MEM0_ECC_IRQ_SENSITIVITY_INFO 0x4700003A, 0x00000101 +#define BF_L1MEM0_ECC_MODE_INFO 0x4700003A, 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_L1MEM0_ECC_DATA_READBACK0_ADDR 0x4700003B +#define BF_L1MEM0_ECC_DATA_PARITY_INDEX_INFO 0x4700003B, 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#define REG_L1MEM0_ECC_DATA_READBACK1_ADDR 0x4700003C + +#ifdef USE_PRIVATE_BF +#define REG_L1MEM0_ECC_DATA_READBACK2_ADDR 0x4700003D +#define BF_L1MEM0_ECC_DATA_PARITY_TAG_INFO 0x4700003D, 0x00000D00 +#endif /* USE_PRIVATE_BF */ + +#define REG_L1MEM0_ECC_DATA_READBACK3_ADDR 0x4700003E + +#ifdef USE_PRIVATE_BF +#define REG_L1MEM0_ECC_DATA_READBACK4_ADDR 0x4700003F +#define BF_L1MEM0_ECC_DATA_PARITY_OUT_INFO 0x4700003F, 0x00000700 +#define BF_L1MEM0_ECC_DATA_PARITY_ERROR_INFO 0x4700003F, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_L1MEM0_ECC_DATA_READBACK5_ADDR 0x47000040 +#define BF_L1MEM0_ECC_DATA_PARITY_IN_INFO 0x47000040, 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_L1MEM0_ECC_DATA_READBACK6_ADDR 0x47000041 + +#define REG_L1MEM0_ECC_DATA_READBACK7_ADDR 0x47000042 + +#define REG_L1MEM0_ECC_DATA_READBACK8_ADDR 0x47000043 + +#ifdef USE_PRIVATE_BF +#define REG_L1MEM0_ECC_PROG_READBACK0_ADDR 0x47000044 +#define BF_L1MEM0_ECC_PROG_PARITY_INDEX_INFO 0x47000044, 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#define REG_L1MEM0_ECC_PROG_READBACK1_ADDR 0x47000045 + +#ifdef USE_PRIVATE_BF +#define REG_L1MEM0_ECC_PROG_READBACK2_ADDR 0x47000046 +#define BF_L1MEM0_ECC_PROG_PARITY_TAG_INFO 0x47000046, 0x00000D00 +#endif /* USE_PRIVATE_BF */ + +#define REG_L1MEM0_ECC_PROG_READBACK3_ADDR 0x47000047 + +#ifdef USE_PRIVATE_BF +#define REG_L1MEM0_ECC_PROG_READBACK4_ADDR 0x47000048 +#define BF_L1MEM0_ECC_PROG_PARITY_OUT_INFO 0x47000048, 0x00000700 +#define BF_L1MEM0_ECC_PROG_PARITY_ERROR_INFO 0x47000048, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_L1MEM0_ECC_PROG_READBACK5_ADDR 0x47000049 +#define BF_L1MEM0_ECC_PROG_PARITY_IN_INFO 0x47000049, 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_L1MEM0_ECC_PROG_READBACK6_ADDR 0x4700004A + +#define REG_L1MEM0_ECC_PROG_READBACK7_ADDR 0x4700004B + +#define REG_L1MEM0_ECC_PROG_READBACK8_ADDR 0x4700004C + +#ifdef USE_PRIVATE_BF +#define REG_L1MEM0_SHARED_BANK_DIV_CTRL_ADDR 0x4700004D +#define BF_L1MEM0_SHARED_BANK_DIV_INFO 0x4700004D, 0x00000300 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_SPIDMA0_CTL_ADDR 0x4700004F +#define BF_SPIDMA0_AHB_BUS_SELECT_INFO 0x4700004F, 0x00000100 +#define BF_SPIDMA0_AUTO_INCR_INFO 0x4700004F, 0x00000101 +#define BF_SPIDMA0_BUS_SIZE_INFO 0x4700004F, 0x00000202 +#define BF_SPIDMA0_BUS_RESPONSE_INFO 0x4700004F, 0x00000104 +#define BF_SPIDMA0_BUS_WAITING_INFO 0x4700004F, 0x00000105 +#define BF_SPIDMA0_SYS_CODEB_INFO 0x4700004F, 0x00000106 +#define BF_SPIDMA0_RD_WRB_INFO 0x4700004F, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#define REG_SPIDMA0_ADDR3_ADDR 0x47000050 + +#define REG_SPIDMA0_ADDR2_ADDR 0x47000051 + +#define REG_SPIDMA0_ADDR1_ADDR 0x47000052 + +#ifdef USE_PRIVATE_BF +#define REG_SPIDMA0_ADDR0_ADDR 0x47000053 +#define BF_SPIDMA0_BUS_ADDR_INFO 0x47000053, 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_SPIDMA0_DATA3_ADDR 0x47000054 + +#define REG_SPIDMA0_DATA2_ADDR 0x47000055 + +#define REG_SPIDMA0_DATA1_ADDR 0x47000056 + +#ifdef USE_PRIVATE_BF +#define REG_SPIDMA0_DATA0_ADDR 0x47000057 +#define BF_SPIDMA0_MEM_WRITE_DATA_INFO 0x47000057, 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_SPIDMA1_CTL_ADDR 0x47000059 +#define BF_SPIDMA1_AHB_BUS_SELECT_INFO 0x47000059, 0x00000100 +#define BF_SPIDMA1_AUTO_INCR_INFO 0x47000059, 0x00000101 +#define BF_SPIDMA1_BUS_SIZE_INFO 0x47000059, 0x00000202 +#define BF_SPIDMA1_BUS_RESPONSE_INFO 0x47000059, 0x00000104 +#define BF_SPIDMA1_BUS_WAITING_INFO 0x47000059, 0x00000105 +#define BF_SPIDMA1_SYS_CODEB_INFO 0x47000059, 0x00000106 +#define BF_SPIDMA1_RD_WRB_INFO 0x47000059, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#define REG_SPIDMA1_ADDR3_ADDR 0x4700005A + +#define REG_SPIDMA1_ADDR2_ADDR 0x4700005B + +#define REG_SPIDMA1_ADDR1_ADDR 0x4700005C + +#ifdef USE_PRIVATE_BF +#define REG_SPIDMA1_ADDR0_ADDR 0x4700005D +#define BF_SPIDMA1_BUS_ADDR_INFO 0x4700005D, 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_SPIDMA1_DATA3_ADDR 0x4700005E + +#define REG_SPIDMA1_DATA2_ADDR 0x4700005F + +#define REG_SPIDMA1_DATA1_ADDR 0x47000060 + +#ifdef USE_PRIVATE_BF +#define REG_SPIDMA1_DATA0_ADDR 0x47000061 +#define BF_SPIDMA1_MEM_WRITE_DATA_INFO 0x47000061, 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARM0_SPI0_COMMAND_ADDR 0x47000063 +#define BF_ARM0_SPI0_COMMAND_INFO 0x47000063, 0x00000600 +#define BF_ARM0_SPI0_COMMAND_BUSY_INFO 0x47000063, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARM0_SPI0_EXT_CMD_BYTE_1_ADDR 0x47000064 +#define BF_ARM0_SPI0_EXT_CMD_BYTE_1_INFO 0x47000064, 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARM0_SPI0_EXT_CMD_BYTE_2_ADDR 0x47000065 +#define BF_ARM0_SPI0_EXT_CMD_BYTE_2_INFO 0x47000065, 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARM0_SPI0_EXT_CMD_BYTE_3_ADDR 0x47000066 +#define BF_ARM0_SPI0_EXT_CMD_BYTE_3_INFO 0x47000066, 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARM0_SPI0_EXT_CMD_BYTE_4_ADDR 0x47000067 +#define BF_ARM0_SPI0_EXT_CMD_BYTE_4_INFO 0x47000067, 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARM0_SPI0_CMD_STATUS_0_ADDR 0x4700006B +#define BF_ARM0_SPI0_CMD_STATUS_DWL_INFO 0x4700006B, 0x00004000 +#endif /* USE_PRIVATE_BF */ + +#define REG_ARM0_SPI0_CMD_STATUS_1_ADDR 0x4700006C + +#define REG_ARM0_SPI0_CMD_STATUS_2_ADDR 0x4700006D + +#define REG_ARM0_SPI0_CMD_STATUS_3_ADDR 0x4700006E + +#define REG_ARM0_SPI0_CMD_STATUS_4_ADDR 0x4700006F + +#define REG_ARM0_SPI0_CMD_STATUS_5_ADDR 0x47000070 + +#define REG_ARM0_SPI0_CMD_STATUS_6_ADDR 0x47000071 + +#define REG_ARM0_SPI0_CMD_STATUS_7_ADDR 0x47000072 + +#ifdef USE_PRIVATE_BF +#define REG_ARM0_SPI0_CMD_STATUS_8_ADDR 0x47000073 +#define BF_ARM0_SPI0_CMD_STATUS_DWH_INFO 0x47000073, 0x00004000 +#endif /* USE_PRIVATE_BF */ + +#define REG_ARM0_SPI0_CMD_STATUS_9_ADDR 0x47000074 + +#define REG_ARM0_SPI0_CMD_STATUS_10_ADDR 0x47000075 + +#define REG_ARM0_SPI0_CMD_STATUS_11_ADDR 0x47000076 + +#define REG_ARM0_SPI0_CMD_STATUS_12_ADDR 0x47000077 + +#define REG_ARM0_SPI0_CMD_STATUS_13_ADDR 0x47000078 + +#define REG_ARM0_SPI0_CMD_STATUS_14_ADDR 0x47000079 + +#define REG_ARM0_SPI0_CMD_STATUS_15_ADDR 0x4700007A + +#ifdef USE_PRIVATE_BF +#define REG_ARM0_SPI1_COMMAND_ADDR 0x4700007C +#define BF_ARM0_SPI1_COMMAND_INFO 0x4700007C, 0x00000600 +#define BF_ARM0_SPI1_COMMAND_BUSY_INFO 0x4700007C, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARM0_SPI1_EXT_CMD_BYTE_1_ADDR 0x4700007D +#define BF_ARM0_SPI1_EXT_CMD_BYTE_1_INFO 0x4700007D, 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARM0_SPI1_EXT_CMD_BYTE_2_ADDR 0x4700007E +#define BF_ARM0_SPI1_EXT_CMD_BYTE_2_INFO 0x4700007E, 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARM0_SPI1_EXT_CMD_BYTE_3_ADDR 0x4700007F +#define BF_ARM0_SPI1_EXT_CMD_BYTE_3_INFO 0x4700007F, 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARM0_SPI1_EXT_CMD_BYTE_4_ADDR 0x47000080 +#define BF_ARM0_SPI1_EXT_CMD_BYTE_4_INFO 0x47000080, 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARM0_SPI1_CMD_STATUS_0_ADDR 0x47000084 +#define BF_ARM0_SPI1_CMD_STATUS_DWL_INFO 0x47000084, 0x00004000 +#endif /* USE_PRIVATE_BF */ + +#define REG_ARM0_SPI1_CMD_STATUS_1_ADDR 0x47000085 + +#define REG_ARM0_SPI1_CMD_STATUS_2_ADDR 0x47000086 + +#define REG_ARM0_SPI1_CMD_STATUS_3_ADDR 0x47000087 + +#define REG_ARM0_SPI1_CMD_STATUS_4_ADDR 0x47000088 + +#define REG_ARM0_SPI1_CMD_STATUS_5_ADDR 0x47000089 + +#define REG_ARM0_SPI1_CMD_STATUS_6_ADDR 0x4700008A + +#define REG_ARM0_SPI1_CMD_STATUS_7_ADDR 0x4700008B + +#ifdef USE_PRIVATE_BF +#define REG_ARM0_SPI1_CMD_STATUS_8_ADDR 0x4700008C +#define BF_ARM0_SPI1_CMD_STATUS_DWH_INFO 0x4700008C, 0x00004000 +#endif /* USE_PRIVATE_BF */ + +#define REG_ARM0_SPI1_CMD_STATUS_9_ADDR 0x4700008D + +#define REG_ARM0_SPI1_CMD_STATUS_10_ADDR 0x4700008E + +#define REG_ARM0_SPI1_CMD_STATUS_11_ADDR 0x4700008F + +#define REG_ARM0_SPI1_CMD_STATUS_12_ADDR 0x47000090 + +#define REG_ARM0_SPI1_CMD_STATUS_13_ADDR 0x47000091 + +#define REG_ARM0_SPI1_CMD_STATUS_14_ADDR 0x47000092 + +#define REG_ARM0_SPI1_CMD_STATUS_15_ADDR 0x47000093 + +#ifdef USE_PRIVATE_BF +#define REG_STREAM_CONTROL_ADDR 0x47000095 +#define BF_STREAM_RESET_CORE_INFO 0x47000095, 0x00000100 +#define BF_STREAM_BANK_SELECT_INFO 0x47000095, 0x00000305 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_STREAM_BASE_BYTE0_ADDR 0x47000096 +#define BF_STREAM_BASE_CORE_INFO 0x47000096, 0x00001000 +#endif /* USE_PRIVATE_BF */ + +#define REG_STREAM_BASE_BYTE1_ADDR 0x47000097 + +#ifdef USE_PRIVATE_BF +#define REG_LAST_STREAM_NUM_ADDR 0x47000098 +#define BF_LAST_STREAM_NUM_CORE_INFO 0x47000098, 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_COMPLETED_STREAM_NUMBER_ADDR 0x47000099 +#define BF_COMPLETED_STREAM_NUM_CORE_INFO 0x47000099, 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TX_EN_READBACK_ADDR 0x4700009A +#define BF_TX_ENABLE_READBACK_INFO 0x4700009A, 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_RX_EN_READBACK_ADDR 0x4700009B +#define BF_RX_ENABLE_READBACK_INFO 0x4700009B, 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ORX_EN_READBACK_ADDR 0x4700009C +#define BF_ORX_ENABLE_READBACK_INFO 0x4700009C, 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_PIN_MODE_STREAM_ERROR_TX_RISE_ADDR 0x4700009D +#define BF_TX0_RISE_STREAM_ERROR_INFO 0x4700009D, 0x00000100 +#define BF_TX1_RISE_STREAM_ERROR_INFO 0x4700009D, 0x00000101 +#define BF_TX2_RISE_STREAM_ERROR_INFO 0x4700009D, 0x00000102 +#define BF_TX3_RISE_STREAM_ERROR_INFO 0x4700009D, 0x00000103 +#define BF_TX4_RISE_STREAM_ERROR_INFO 0x4700009D, 0x00000104 +#define BF_TX5_RISE_STREAM_ERROR_INFO 0x4700009D, 0x00000105 +#define BF_TX6_RISE_STREAM_ERROR_INFO 0x4700009D, 0x00000106 +#define BF_TX7_RISE_STREAM_ERROR_INFO 0x4700009D, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_PIN_MODE_STREAM_ERROR_TX_FALL_ADDR 0x4700009F +#define BF_TX0_FALL_STREAM_ERROR_INFO 0x4700009F, 0x00000100 +#define BF_TX1_FALL_STREAM_ERROR_INFO 0x4700009F, 0x00000101 +#define BF_TX2_FALL_STREAM_ERROR_INFO 0x4700009F, 0x00000102 +#define BF_TX3_FALL_STREAM_ERROR_INFO 0x4700009F, 0x00000103 +#define BF_TX4_FALL_STREAM_ERROR_INFO 0x4700009F, 0x00000104 +#define BF_TX5_FALL_STREAM_ERROR_INFO 0x4700009F, 0x00000105 +#define BF_TX6_FALL_STREAM_ERROR_INFO 0x4700009F, 0x00000106 +#define BF_TX7_FALL_STREAM_ERROR_INFO 0x4700009F, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_PIN_MODE_STREAM_ERROR_ORX_RISE_FALL_ADDR 0x470000A1 +#define BF_ORX0_RISE_STREAM_ERROR_INFO 0x470000A1, 0x00000100 +#define BF_ORX1_RISE_STREAM_ERROR_INFO 0x470000A1, 0x00000101 +#define BF_ORX2_RISE_STREAM_ERROR_INFO 0x470000A1, 0x00000102 +#define BF_ORX3_RISE_STREAM_ERROR_INFO 0x470000A1, 0x00000103 +#define BF_ORX0_FALL_STREAM_ERROR_INFO 0x470000A1, 0x00000104 +#define BF_ORX1_FALL_STREAM_ERROR_INFO 0x470000A1, 0x00000105 +#define BF_ORX2_FALL_STREAM_ERROR_INFO 0x470000A1, 0x00000106 +#define BF_ORX3_FALL_STREAM_ERROR_INFO 0x470000A1, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_PIN_MODE_STREAM_ERROR_RX_RISE_ADDR 0x470000A2 +#define BF_RX0_RISE_STREAM_ERROR_INFO 0x470000A2, 0x00000100 +#define BF_RX1_RISE_STREAM_ERROR_INFO 0x470000A2, 0x00000101 +#define BF_RX2_RISE_STREAM_ERROR_INFO 0x470000A2, 0x00000102 +#define BF_RX3_RISE_STREAM_ERROR_INFO 0x470000A2, 0x00000103 +#define BF_RX4_RISE_STREAM_ERROR_INFO 0x470000A2, 0x00000104 +#define BF_RX5_RISE_STREAM_ERROR_INFO 0x470000A2, 0x00000105 +#define BF_RX6_RISE_STREAM_ERROR_INFO 0x470000A2, 0x00000106 +#define BF_RX7_RISE_STREAM_ERROR_INFO 0x470000A2, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_PIN_MODE_STREAM_ERROR_RX_FALL_ADDR 0x470000A4 +#define BF_RX0_FALL_STREAM_ERROR_INFO 0x470000A4, 0x00000100 +#define BF_RX1_FALL_STREAM_ERROR_INFO 0x470000A4, 0x00000101 +#define BF_RX2_FALL_STREAM_ERROR_INFO 0x470000A4, 0x00000102 +#define BF_RX3_FALL_STREAM_ERROR_INFO 0x470000A4, 0x00000103 +#define BF_RX4_FALL_STREAM_ERROR_INFO 0x470000A4, 0x00000104 +#define BF_RX5_FALL_STREAM_ERROR_INFO 0x470000A4, 0x00000105 +#define BF_RX6_FALL_STREAM_ERROR_INFO 0x470000A4, 0x00000106 +#define BF_RX7_FALL_STREAM_ERROR_INFO 0x470000A4, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ORX_LPBK_STREAM_ERROR_ADDR 0x470000A6 +#define BF_LPBK0_FALL_STREAM_ERROR_INFO 0x470000A6, 0x00000100 +#define BF_LPBK0_RISE_STREAM_ERROR_INFO 0x470000A6, 0x00000101 +#define BF_LPBK1_FALL_STREAM_ERROR_INFO 0x470000A6, 0x00000102 +#define BF_LPBK1_RISE_STREAM_ERROR_INFO 0x470000A6, 0x00000103 +#define BF_LPBK2_FALL_STREAM_ERROR_INFO 0x470000A6, 0x00000104 +#define BF_LPBK2_RISE_STREAM_ERROR_INFO 0x470000A6, 0x00000105 +#define BF_LPBK3_FALL_STREAM_ERROR_INFO 0x470000A6, 0x00000106 +#define BF_LPBK3_RISE_STREAM_ERROR_INFO 0x470000A6, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#define REG_STREAM_DFRM_IRQ_MASK_ADDR 0x470000A7 +#define BF_DFRM_IRQ_MASK_INFO 0x470000A7, 0x00000200 +#define BF_NEW_SYSREF_PHASE_IRQ_MASK_INFO 0x470000A7, 0x00000104 + +#ifdef USE_PRIVATE_BF +#define REG_STREAM_SPI_REG_MASK_WRITE_STATUS_ADDR 0x470000A8 +#define BF_SPI_REG_MASK_WRITE_STREAM_STATUS_INFO 0x470000A8, 0x00000100 +#define BF_SPI_REG_MASK_WRITE_STREAM_ERROR_INFO 0x470000A8, 0x00000101 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_STREAM_GPIO_STATUS_ADDR 0x470000A9 +#define BF_STREAM_GPIO0_STATUS_INFO 0x470000A9, 0x00000100 +#define BF_STREAM_GPIO1_STATUS_INFO 0x470000A9, 0x00000101 +#define BF_STREAM_GPIO2_STATUS_INFO 0x470000A9, 0x00000102 +#define BF_STREAM_GPIO3_STATUS_INFO 0x470000A9, 0x00000103 +#define BF_STREAM_GPIO4_STATUS_INFO 0x470000A9, 0x00000104 +#define BF_STREAM_GPIO5_STATUS_INFO 0x470000A9, 0x00000105 +#define BF_STREAM_GPIO6_STATUS_INFO 0x470000A9, 0x00000106 +#define BF_STREAM_GPIO7_STATUS_INFO 0x470000A9, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_STREAM_GPIO_ERROR_ADDR 0x470000AA +#define BF_STREAM_GPIO0_RISE_ERROR_INFO 0x470000AA, 0x00000100 +#define BF_STREAM_GPIO1_RISE_ERROR_INFO 0x470000AA, 0x00000101 +#define BF_STREAM_GPIO2_RISE_ERROR_INFO 0x470000AA, 0x00000102 +#define BF_STREAM_GPIO3_RISE_ERROR_INFO 0x470000AA, 0x00000103 +#define BF_STREAM_GPIO0_FALL_ERROR_INFO 0x470000AA, 0x00000104 +#define BF_STREAM_GPIO1_FALL_ERROR_INFO 0x470000AA, 0x00000105 +#define BF_STREAM_GPIO2_FALL_ERROR_INFO 0x470000AA, 0x00000106 +#define BF_STREAM_GPIO3_FALL_ERROR_INFO 0x470000AA, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_STREAM_GPIO_ERROR1_ADDR 0x470000AB +#define BF_STREAM_GPIO4_RISE_ERROR_INFO 0x470000AB, 0x00000100 +#define BF_STREAM_GPIO5_RISE_ERROR_INFO 0x470000AB, 0x00000101 +#define BF_STREAM_GPIO6_RISE_ERROR_INFO 0x470000AB, 0x00000102 +#define BF_STREAM_GPIO7_RISE_ERROR_INFO 0x470000AB, 0x00000103 +#define BF_STREAM_GPIO4_FALL_ERROR_INFO 0x470000AB, 0x00000104 +#define BF_STREAM_GPIO5_FALL_ERROR_INFO 0x470000AB, 0x00000105 +#define BF_STREAM_GPIO6_FALL_ERROR_INFO 0x470000AB, 0x00000106 +#define BF_STREAM_GPIO7_FALL_ERROR_INFO 0x470000AB, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_STREAM_GPIO_ERROR2_ADDR 0x470000AC +#define BF_STREAM_GPIO8_RISE_ERROR_INFO 0x470000AC, 0x00000100 +#define BF_STREAM_GPIO9_RISE_ERROR_INFO 0x470000AC, 0x00000101 +#define BF_STREAM_GPIO10_RISE_ERROR_INFO 0x470000AC, 0x00000102 +#define BF_STREAM_GPIO11_RISE_ERROR_INFO 0x470000AC, 0x00000103 +#define BF_STREAM_GPIO8_FALL_ERROR_INFO 0x470000AC, 0x00000104 +#define BF_STREAM_GPIO9_FALL_ERROR_INFO 0x470000AC, 0x00000105 +#define BF_STREAM_GPIO10_FALL_ERROR_INFO 0x470000AC, 0x00000106 +#define BF_STREAM_GPIO11_FALL_ERROR_INFO 0x470000AC, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_STREAM_GPIO_ERROR3_ADDR 0x470000AD +#define BF_STREAM_GPIO12_RISE_ERROR_INFO 0x470000AD, 0x00000100 +#define BF_STREAM_GPIO13_RISE_ERROR_INFO 0x470000AD, 0x00000101 +#define BF_STREAM_GPIO14_RISE_ERROR_INFO 0x470000AD, 0x00000102 +#define BF_STREAM_GPIO15_RISE_ERROR_INFO 0x470000AD, 0x00000103 +#define BF_STREAM_GPIO12_FALL_ERROR_INFO 0x470000AD, 0x00000104 +#define BF_STREAM_GPIO13_FALL_ERROR_INFO 0x470000AD, 0x00000105 +#define BF_STREAM_GPIO14_FALL_ERROR_INFO 0x470000AD, 0x00000106 +#define BF_STREAM_GPIO15_FALL_ERROR_INFO 0x470000AD, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_STREAM_GPIO_ERROR4_ADDR 0x470000AE +#define BF_STREAM_GPIO16_RISE_ERROR_INFO 0x470000AE, 0x00000100 +#define BF_STREAM_GPIO17_RISE_ERROR_INFO 0x470000AE, 0x00000101 +#define BF_STREAM_GPIO18_RISE_ERROR_INFO 0x470000AE, 0x00000102 +#define BF_STREAM_GPIO19_RISE_ERROR_INFO 0x470000AE, 0x00000103 +#define BF_STREAM_GPIO16_FALL_ERROR_INFO 0x470000AE, 0x00000104 +#define BF_STREAM_GPIO17_FALL_ERROR_INFO 0x470000AE, 0x00000105 +#define BF_STREAM_GPIO18_FALL_ERROR_INFO 0x470000AE, 0x00000106 +#define BF_STREAM_GPIO19_FALL_ERROR_INFO 0x470000AE, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_STREAM_GPIO_ERROR5_ADDR 0x470000AF +#define BF_STREAM_GPIO20_RISE_ERROR_INFO 0x470000AF, 0x00000100 +#define BF_STREAM_GPIO21_RISE_ERROR_INFO 0x470000AF, 0x00000101 +#define BF_STREAM_GPIO22_RISE_ERROR_INFO 0x470000AF, 0x00000102 +#define BF_STREAM_GPIO23_RISE_ERROR_INFO 0x470000AF, 0x00000103 +#define BF_STREAM_GPIO20_FALL_ERROR_INFO 0x470000AF, 0x00000104 +#define BF_STREAM_GPIO21_FALL_ERROR_INFO 0x470000AF, 0x00000105 +#define BF_STREAM_GPIO22_FALL_ERROR_INFO 0x470000AF, 0x00000106 +#define BF_STREAM_GPIO23_FALL_ERROR_INFO 0x470000AF, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_STREAM_ORX_SWITCH_ERROR_ADDR 0x470000B0 +#define BF_ORX0LOW_TO_ORX1HIGH_STREAM_ERROR_INFO 0x470000B0, 0x00000100 +#define BF_ORX1LOW_TO_ORX0HIGH_STREAM_ERROR_INFO 0x470000B0, 0x00000101 +#define BF_ORX2LOW_TO_ORX3HIGH_STREAM_ERROR_INFO 0x470000B0, 0x00000102 +#define BF_ORX3LOW_TO_ORX2HIGH_STREAM_ERROR_INFO 0x470000B0, 0x00000103 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_STREAM_PROC_READBACK_ADDR_ADDR 0x470000B1 +#define BF_STREAM_PROC_ADDR_CORE_INFO 0x470000B1, 0x00000400 +#define BF_STREAM_PROC_RDEN_CORE_INFO 0x470000B1, 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_STREAM_PROC_READBACK_DATA0_ADDR 0x470000B2 +#define BF_STREAM_PROC_DATA_CORE_INFO 0x470000B2, 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_STREAM_PROC_READBACK_DATA1_ADDR 0x470000B3 + +#define REG_STREAM_PROC_READBACK_DATA2_ADDR 0x470000B4 + +#define REG_STREAM_PROC_READBACK_DATA3_ADDR 0x470000B5 + +#ifdef USE_PRIVATE_BF +#define REG_STREAM_PROC_ERROR_ADDR 0x470000B6 +#define BF_STREAM_ERROR_CORE_INFO 0x470000B6, 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_STREAM_PROC_SPI_RMW_ADDRESS_LSB_ADDR 0x470000B7 +#define BF_SPI_RMW_ADDRESS_INFO 0x470000B7, 0x00000F00 +#endif /* USE_PRIVATE_BF */ + +#define REG_STREAM_PROC_SPI_RMW_ADDRESS_MSB_ADDR 0x470000B8 + +#ifdef USE_PRIVATE_BF +#define REG_STREAM_PROC_SPI_RMW_MASK_ADDR 0x470000B9 +#define BF_SPI_RMW_MASK_INFO 0x470000B9, 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_STREAM_PROC_SPI_RMW_DATA_ADDR 0x470000BA +#define BF_SPI_RMW_DATA_INFO 0x470000BA, 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_STREAM_GPIO_STATUS2_ADDR 0x470000BB +#define BF_STREAM_GPIO8_STATUS_INFO 0x470000BB, 0x00000100 +#define BF_STREAM_GPIO9_STATUS_INFO 0x470000BB, 0x00000101 +#define BF_STREAM_GPIO10_STATUS_INFO 0x470000BB, 0x00000102 +#define BF_STREAM_GPIO11_STATUS_INFO 0x470000BB, 0x00000103 +#define BF_STREAM_GPIO12_STATUS_INFO 0x470000BB, 0x00000104 +#define BF_STREAM_GPIO13_STATUS_INFO 0x470000BB, 0x00000105 +#define BF_STREAM_GPIO14_STATUS_INFO 0x470000BB, 0x00000106 +#define BF_STREAM_GPIO15_STATUS_INFO 0x470000BB, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_STREAM_GPIO_STATUS3_ADDR 0x470000BC +#define BF_STREAM_GPIO16_STATUS_INFO 0x470000BC, 0x00000100 +#define BF_STREAM_GPIO17_STATUS_INFO 0x470000BC, 0x00000101 +#define BF_STREAM_GPIO18_STATUS_INFO 0x470000BC, 0x00000102 +#define BF_STREAM_GPIO19_STATUS_INFO 0x470000BC, 0x00000103 +#define BF_STREAM_GPIO20_STATUS_INFO 0x470000BC, 0x00000104 +#define BF_STREAM_GPIO21_STATUS_INFO 0x470000BC, 0x00000105 +#define BF_STREAM_GPIO22_STATUS_INFO 0x470000BC, 0x00000106 +#define BF_STREAM_GPIO23_STATUS_INFO 0x470000BC, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARM1_CTL_ADDR 0x470000C6 +#define BF_ARM1_M3_RUN_INFO 0x470000C6, 0x00000100 +#define BF_ARM1_ERROR_INFO 0x470000C6, 0x00000101 +#define BF_ARM1_MEM_HRESP_MASK_INFO 0x470000C6, 0x00000103 +#define BF_ARM1_DEBUG_ENABLE_INFO 0x470000C6, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARM1_RESET_ADDR 0x470000C7 +#define BF_ARM1_FORCE_RESET_INFO 0x470000C7, 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARM1_BOOT_ADDR_BYTE0_ADDR 0x470000C8 +#define BF_ARM1_BOOT_ADDR_INFO 0x470000C8, 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_ARM1_BOOT_ADDR_BYTE1_ADDR 0x470000C9 + +#define REG_ARM1_BOOT_ADDR_BYTE2_ADDR 0x470000CA + +#define REG_ARM1_BOOT_ADDR_BYTE3_ADDR 0x470000CB + +#ifdef USE_PRIVATE_BF +#define REG_ARM1_STACK_PTR_BYTE_0_ADDR 0x470000CC +#define BF_ARM1_STACK_PTR_INFO 0x470000CC, 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_ARM1_STACK_PTR_BYTE_1_ADDR 0x470000CD + +#define REG_ARM1_STACK_PTR_BYTE_2_ADDR 0x470000CE + +#define REG_ARM1_STACK_PTR_BYTE_3_ADDR 0x470000CF + +#ifdef USE_PRIVATE_BF +#define REG_L1MEM1_ECC_CONTROL_ADDR 0x470000DF +#define BF_L1MEM1_ECC_IRQ_SENSITIVITY_INFO 0x470000DF, 0x00000101 +#define BF_L1MEM1_ECC_MODE_INFO 0x470000DF, 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_L1MEM1_ECC_DATA_READBACK0_ADDR 0x470000E0 +#define BF_L1MEM1_ECC_DATA_PARITY_INDEX_INFO 0x470000E0, 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#define REG_L1MEM1_ECC_DATA_READBACK1_ADDR 0x470000E1 + +#ifdef USE_PRIVATE_BF +#define REG_L1MEM1_ECC_DATA_READBACK2_ADDR 0x470000E2 +#define BF_L1MEM1_ECC_DATA_PARITY_TAG_INFO 0x470000E2, 0x00000D00 +#endif /* USE_PRIVATE_BF */ + +#define REG_L1MEM1_ECC_DATA_READBACK3_ADDR 0x470000E3 + +#ifdef USE_PRIVATE_BF +#define REG_L1MEM1_ECC_DATA_READBACK4_ADDR 0x470000E4 +#define BF_L1MEM1_ECC_DATA_PARITY_OUT_INFO 0x470000E4, 0x00000700 +#define BF_L1MEM1_ECC_DATA_PARITY_ERROR_INFO 0x470000E4, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_L1MEM1_ECC_DATA_READBACK5_ADDR 0x470000E5 +#define BF_L1MEM1_ECC_DATA_PARITY_IN_INFO 0x470000E5, 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_L1MEM1_ECC_DATA_READBACK6_ADDR 0x470000E6 + +#define REG_L1MEM1_ECC_DATA_READBACK7_ADDR 0x470000E7 + +#define REG_L1MEM1_ECC_DATA_READBACK8_ADDR 0x470000E8 + +#ifdef USE_PRIVATE_BF +#define REG_L1MEM1_ECC_PROG_READBACK0_ADDR 0x470000E9 +#define BF_L1MEM1_ECC_PROG_PARITY_INDEX_INFO 0x470000E9, 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#define REG_L1MEM1_ECC_PROG_READBACK1_ADDR 0x470000EA + +#ifdef USE_PRIVATE_BF +#define REG_L1MEM1_ECC_PROG_READBACK2_ADDR 0x470000EB +#define BF_L1MEM1_ECC_PROG_PARITY_TAG_INFO 0x470000EB, 0x00000D00 +#endif /* USE_PRIVATE_BF */ + +#define REG_L1MEM1_ECC_PROG_READBACK3_ADDR 0x470000EC + +#ifdef USE_PRIVATE_BF +#define REG_L1MEM1_ECC_PROG_READBACK4_ADDR 0x470000ED +#define BF_L1MEM1_ECC_PROG_PARITY_OUT_INFO 0x470000ED, 0x00000700 +#define BF_L1MEM1_ECC_PROG_PARITY_ERROR_INFO 0x470000ED, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_L1MEM1_ECC_PROG_READBACK5_ADDR 0x470000EE +#define BF_L1MEM1_ECC_PROG_PARITY_IN_INFO 0x470000EE, 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_L1MEM1_ECC_PROG_READBACK6_ADDR 0x470000EF + +#define REG_L1MEM1_ECC_PROG_READBACK7_ADDR 0x470000F0 + +#define REG_L1MEM1_ECC_PROG_READBACK8_ADDR 0x470000F1 + +#ifdef USE_PRIVATE_BF +#define REG_L1MEM1_SHARED_BANK_DIV_CTRL_ADDR 0x470000F2 +#define BF_L1MEM1_SHARED_BANK_DIV_INFO 0x470000F2, 0x00000300 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARM1_SPI0_COMMAND_ADDR 0x470000F4 +#define BF_ARM1_SPI0_COMMAND_INFO 0x470000F4, 0x00000600 +#define BF_ARM1_SPI0_COMMAND_BUSY_INFO 0x470000F4, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARM1_SPI0_EXT_CMD_BYTE_1_ADDR 0x470000F5 +#define BF_ARM1_SPI0_EXT_CMD_BYTE_1_INFO 0x470000F5, 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARM1_SPI0_EXT_CMD_BYTE_2_ADDR 0x470000F6 +#define BF_ARM1_SPI0_EXT_CMD_BYTE_2_INFO 0x470000F6, 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARM1_SPI0_EXT_CMD_BYTE_3_ADDR 0x470000F7 +#define BF_ARM1_SPI0_EXT_CMD_BYTE_3_INFO 0x470000F7, 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARM1_SPI0_EXT_CMD_BYTE_4_ADDR 0x470000F8 +#define BF_ARM1_SPI0_EXT_CMD_BYTE_4_INFO 0x470000F8, 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARM1_SPI0_CMD_STATUS_0_ADDR 0x470000FC +#define BF_ARM1_SPI0_CMD_STATUS_DWL_INFO 0x470000FC, 0x00004000 +#endif /* USE_PRIVATE_BF */ + +#define REG_ARM1_SPI0_CMD_STATUS_1_ADDR 0x470000FD + +#define REG_ARM1_SPI0_CMD_STATUS_2_ADDR 0x470000FE + +#define REG_ARM1_SPI0_CMD_STATUS_3_ADDR 0x470000FF + +#define REG_ARM1_SPI0_CMD_STATUS_4_ADDR 0x47000100 + +#define REG_ARM1_SPI0_CMD_STATUS_5_ADDR 0x47000101 + +#define REG_ARM1_SPI0_CMD_STATUS_6_ADDR 0x47000102 + +#define REG_ARM1_SPI0_CMD_STATUS_7_ADDR 0x47000103 + +#ifdef USE_PRIVATE_BF +#define REG_ARM1_SPI0_CMD_STATUS_8_ADDR 0x47000104 +#define BF_ARM1_SPI0_CMD_STATUS_DWH_INFO 0x47000104, 0x00004000 +#endif /* USE_PRIVATE_BF */ + +#define REG_ARM1_SPI0_CMD_STATUS_9_ADDR 0x47000105 + +#define REG_ARM1_SPI0_CMD_STATUS_10_ADDR 0x47000106 + +#define REG_ARM1_SPI0_CMD_STATUS_11_ADDR 0x47000107 + +#define REG_ARM1_SPI0_CMD_STATUS_12_ADDR 0x47000108 + +#define REG_ARM1_SPI0_CMD_STATUS_13_ADDR 0x47000109 + +#define REG_ARM1_SPI0_CMD_STATUS_14_ADDR 0x4700010A + +#define REG_ARM1_SPI0_CMD_STATUS_15_ADDR 0x4700010B + +#ifdef USE_PRIVATE_BF +#define REG_ARM1_SPI1_COMMAND_ADDR 0x4700010D +#define BF_ARM1_SPI1_COMMAND_INFO 0x4700010D, 0x00000600 +#define BF_ARM1_SPI1_COMMAND_BUSY_INFO 0x4700010D, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARM1_SPI1_EXT_CMD_BYTE_1_ADDR 0x4700010E +#define BF_ARM1_SPI1_EXT_CMD_BYTE_1_INFO 0x4700010E, 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARM1_SPI1_EXT_CMD_BYTE_2_ADDR 0x4700010F +#define BF_ARM1_SPI1_EXT_CMD_BYTE_2_INFO 0x4700010F, 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARM1_SPI1_EXT_CMD_BYTE_3_ADDR 0x47000110 +#define BF_ARM1_SPI1_EXT_CMD_BYTE_3_INFO 0x47000110, 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARM1_SPI1_EXT_CMD_BYTE_4_ADDR 0x47000111 +#define BF_ARM1_SPI1_EXT_CMD_BYTE_4_INFO 0x47000111, 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARM1_SPI1_CMD_STATUS_0_ADDR 0x47000115 +#define BF_ARM1_SPI1_CMD_STATUS_DWL_INFO 0x47000115, 0x00004000 +#endif /* USE_PRIVATE_BF */ + +#define REG_ARM1_SPI1_CMD_STATUS_1_ADDR 0x47000116 + +#define REG_ARM1_SPI1_CMD_STATUS_2_ADDR 0x47000117 + +#define REG_ARM1_SPI1_CMD_STATUS_3_ADDR 0x47000118 + +#define REG_ARM1_SPI1_CMD_STATUS_4_ADDR 0x47000119 + +#define REG_ARM1_SPI1_CMD_STATUS_5_ADDR 0x4700011A + +#define REG_ARM1_SPI1_CMD_STATUS_6_ADDR 0x4700011B + +#define REG_ARM1_SPI1_CMD_STATUS_7_ADDR 0x4700011C + +#ifdef USE_PRIVATE_BF +#define REG_ARM1_SPI1_CMD_STATUS_8_ADDR 0x4700011D +#define BF_ARM1_SPI1_CMD_STATUS_DWH_INFO 0x4700011D, 0x00004000 +#endif /* USE_PRIVATE_BF */ + +#define REG_ARM1_SPI1_CMD_STATUS_9_ADDR 0x4700011E + +#define REG_ARM1_SPI1_CMD_STATUS_10_ADDR 0x4700011F + +#define REG_ARM1_SPI1_CMD_STATUS_11_ADDR 0x47000120 + +#define REG_ARM1_SPI1_CMD_STATUS_12_ADDR 0x47000121 + +#define REG_ARM1_SPI1_CMD_STATUS_13_ADDR 0x47000122 + +#define REG_ARM1_SPI1_CMD_STATUS_14_ADDR 0x47000123 + +#define REG_ARM1_SPI1_CMD_STATUS_15_ADDR 0x47000124 + +#define REG_SPI0_BASE_PAGE_ADDRESS_31TO24_ADDR 0x47000126 +#define BF_SPI0_BASE_PAGE_ADDR_31TO24_INFO 0x47000126, 0x00000800 + +#define REG_SPI0_BASE_PAGE_ADDRESS_23TO16_ADDR 0x47000127 +#define BF_SPI0_BASE_PAGE_ADDR_23TO16_INFO 0x47000127, 0x00000800 + +#define REG_SPI0_BASE_PAGE_ADDRESS_15TO8_ADDR 0x47000128 +#define BF_SPI0_BASE_PAGE_ADDR_15TO8_INFO 0x47000128, 0x00000800 + +#define REG_SPI0_BASE_PAGE_ADDRESS_7TO0_ADDR 0x47000129 +#define BF_SPI0_BASE_PAGE_ADDR_7TO0_INFO 0x47000129, 0x00000800 + +#define REG_SPI0_PAGING_CONTROL_ADDR 0x4700012A +#define BF_SPI0_AHB_BRIDGE_32B_PACK_EN_INFO 0x4700012A, 0x00000100 +#define BF_SPI0_PAGING_SPI2AHB_BUSY_INFO 0x4700012A, 0x00000102 + +#define REG_SPI0_WORKING_PAGE_ADDRESS_31TO24_ADDR 0x4700012B +#define BF_SPI0_WORKING_PAGE_ADDR_31TO24_INFO 0x4700012B, 0x00000800 + +#define REG_SPI0_WORKING_PAGE_ADDRESS_23TO16_ADDR 0x4700012C +#define BF_SPI0_WORKING_PAGE_ADDR_23TO16_INFO 0x4700012C, 0x00000800 + +#define REG_SPI0_WORKING_PAGE_ADDRESS_15TO8_ADDR 0x4700012D +#define BF_SPI0_WORKING_PAGE_ADDR_15TO8_INFO 0x4700012D, 0x00000800 + +#define REG_SPI0_WORKING_PAGE_ADDRESS_7TO0_ADDR 0x4700012E +#define BF_SPI0_WORKING_PAGE_ADDR_7TO0_INFO 0x4700012E, 0x00000800 + +#define REG_SPI0_MASK_31TO24_ADDR 0x4700012F +#define BF_SPI0_MASK_31TO24_INFO 0x4700012F, 0x00000800 + +#define REG_SPI0_MASK_23TO16_ADDR 0x47000130 +#define BF_SPI0_MASK_23TO16_INFO 0x47000130, 0x00000800 + +#define REG_SPI0_MASK_15TO8_ADDR 0x47000131 +#define BF_SPI0_MASK_15TO8_INFO 0x47000131, 0x00000800 + +#define REG_SPI0_MASK_7TO0_ADDR 0x47000132 +#define BF_SPI0_MASK_7TO0_INFO 0x47000132, 0x00000800 + +#define REG_SPI1_PAGE_ADDRESS_31TO24_ADDR 0x47000134 +#define BF_SPI1_BASE_PAGE_ADDR_31TO24_INFO 0x47000134, 0x00000800 + +#define REG_SPI1_PAGE_ADDRESS_23TO16_ADDR 0x47000135 +#define BF_SPI1_BASE_PAGE_ADDR_23TO16_INFO 0x47000135, 0x00000800 + +#define REG_SPI1_PAGE_ADDRESS_15TO8_ADDR 0x47000136 +#define BF_SPI1_BASE_PAGE_ADDR_15TO8_INFO 0x47000136, 0x00000800 + +#define REG_SPI1_PAGE_ADDRESS_7TO0_ADDR 0x47000137 +#define BF_SPI1_BASE_PAGE_ADDR_7TO0_INFO 0x47000137, 0x00000800 + +#define REG_SPI1_PAGING_CONTROL_ADDR 0x47000138 +#define BF_SPI1_AHB_BRIDGE_32B_PACK_EN_INFO 0x47000138, 0x00000100 +#define BF_SPI1_CORE_SPI2AHB_BUSY_INFO 0x47000138, 0x00000101 +#define BF_SPI1_PAGING_SPI2AHB_BUSY_INFO 0x47000138, 0x00000102 + +#define REG_SPI1_WORKING_PAGE_ADDRESS_31TO24_ADDR 0x47000139 +#define BF_SPI1_WORKING_PAGE_ADDR_31TO24_INFO 0x47000139, 0x00000800 + +#define REG_SPI1_WORKING_PAGE_ADDRESS_23TO16_ADDR 0x4700013A +#define BF_SPI1_WORKING_PAGE_ADDR_23TO16_INFO 0x4700013A, 0x00000800 + +#define REG_SPI1_WORKING_PAGE_ADDRESS_15TO8_ADDR 0x4700013B +#define BF_SPI1_WORKING_PAGE_ADDR_15TO8_INFO 0x4700013B, 0x00000800 + +#define REG_SPI1_WORKING_PAGE_ADDRESS_7TO0_ADDR 0x4700013C +#define BF_SPI1_WORKING_PAGE_ADDR_7TO0_INFO 0x4700013C, 0x00000800 + +#define REG_SPI1_MASK_31TO24_ADDR 0x4700013D +#define BF_SPI1_MASK_31TO24_INFO 0x4700013D, 0x00000800 + +#define REG_SPI1_MASK_23TO16_ADDR 0x4700013E +#define BF_SPI1_MASK_23TO16_INFO 0x4700013E, 0x00000800 + +#define REG_SPI1_MASK_15TO8_ADDR 0x4700013F +#define BF_SPI1_MASK_15TO8_INFO 0x4700013F, 0x00000800 + +#define REG_SPI1_MASK_7TO0_ADDR 0x47000140 +#define BF_SPI1_MASK_7TO0_INFO 0x47000140, 0x00000800 + +#define REG_DUAL_ARM_SUBSYS_MISC_CONTROL_ADDR 0x47000142 +#define BF_ARM_DAP_MODE_SEL_INFO 0x47000142, 0x00000100 +#define BF_STREAM_PROC_WR_ACC_ARM_MEM_INFO 0x47000142, 0x00000101 + +#ifdef USE_PRIVATE_BF +#define REG_ARM0_SW_INTERRUPT_CONTROL_ADDR 0x47000143 +#define BF_ARM0_FORCE_GP_INTERRUPT_INFO 0x47000143, 0x00000100 +#define BF_ARM0_CALIBRATION_ERROR_INFO 0x47000143, 0x00000102 +#define BF_ARM0_SYSTEM_ERROR_INFO 0x47000143, 0x00000103 +#define BF_ARM0_USE_RX_ENABLE_PIN_FOR_INTERRUPT_INFO 0x47000143, 0x00000104 +#define BF_ARM0_USE_TX_ENABLE_PIN_FOR_INTERRUPT_INFO 0x47000143, 0x00000105 +#define BF_ARM0_USE_ORX_ENABLE_PIN_FOR_INTERRUPT_INFO 0x47000143, 0x00000106 +#define BF_ARM0_USE_ORX_ENABLE_PIN_FOR_LPBK_INTERRUPT_INFO 0x47000143, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARM1_SW_INTERRUPT_CONTROL_ADDR 0x47000144 +#define BF_ARM1_FORCE_GP_INTERRUPT_INFO 0x47000144, 0x00000100 +#define BF_ARM1_CALIBRATION_ERROR_INFO 0x47000144, 0x00000102 +#define BF_ARM1_SYSTEM_ERROR_INFO 0x47000144, 0x00000103 +#define BF_ARM1_USE_RX_ENABLE_PIN_FOR_INTERRUPT_INFO 0x47000144, 0x00000104 +#define BF_ARM1_USE_TX_ENABLE_PIN_FOR_INTERRUPT_INFO 0x47000144, 0x00000105 +#define BF_ARM1_USE_ORX_ENABLE_PIN_FOR_INTERRUPT_INFO 0x47000144, 0x00000106 +#define BF_ARM1_USE_ORX_ENABLE_PIN_FOR_LPBK_INTERRUPT_INFO 0x47000144, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#define REG_GP_INTERRUPT_MASK_PIN_1_BYTE0_ADDR 0x47000146 +#define BF_GP_INTERRUPTS_MASK_LOWER_WORD_PIN1_INFO 0x47000146, 0x00003000 + +#define REG_GP_INTERRUPT_MASK_PIN_1_BYTE1_ADDR 0x47000147 + +#define REG_GP_INTERRUPT_MASK_PIN_1_BYTE2_ADDR 0x47000148 + +#define REG_GP_INTERRUPT_MASK_PIN_1_BYTE3_ADDR 0x47000149 + +#define REG_GP_INTERRUPT_MASK_PIN_1_BYTE4_ADDR 0x4700014A + +#define REG_GP_INTERRUPT_MASK_PIN_1_BYTE5_ADDR 0x4700014B + +#define REG_GP_INTERRUPT_MASK_PIN_1_BYTE6_ADDR 0x4700014C +#define BF_GP_INTERRUPTS_MASK_UPPER_WORD_PIN1_INFO 0x4700014C, 0x00003000 + +#define REG_GP_INTERRUPT_MASK_PIN_1_BYTE7_ADDR 0x4700014D + +#define REG_GP_INTERRUPT_MASK_PIN_1_BYTE8_ADDR 0x4700014E + +#define REG_GP_INTERRUPT_MASK_PIN_1_BYTE9_ADDR 0x4700014F + +#define REG_GP_INTERRUPT_MASK_PIN_1_BYTE10_ADDR 0x47000150 + +#define REG_GP_INTERRUPT_MASK_PIN_1_BYTE11_ADDR 0x47000151 + +#ifdef USE_PRIVATE_BF +#define REG_GP_INTERRUPT_MASK_PIN_0_BYTE0_ADDR 0x47000152 +#define BF_GP_INTERRUPTS_MASK_LOWER_WORD_PIN0_INFO 0x47000152, 0x00003000 +#endif /* USE_PRIVATE_BF */ + +#define REG_GP_INTERRUPT_MASK_PIN_0_BYTE1_ADDR 0x47000153 + +#define REG_GP_INTERRUPT_MASK_PIN_0_BYTE2_ADDR 0x47000154 + +#define REG_GP_INTERRUPT_MASK_PIN_0_BYTE3_ADDR 0x47000155 + +#define REG_GP_INTERRUPT_MASK_PIN_0_BYTE4_ADDR 0x47000156 + +#define REG_GP_INTERRUPT_MASK_PIN_0_BYTE5_ADDR 0x47000157 + +#ifdef USE_PRIVATE_BF +#define REG_GP_INTERRUPT_MASK_PIN_0_BYTE6_ADDR 0x47000158 +#define BF_GP_INTERRUPTS_MASK_UPPER_WORD_PIN0_INFO 0x47000158, 0x00003000 +#endif /* USE_PRIVATE_BF */ + +#define REG_GP_INTERRUPT_MASK_PIN_0_BYTE7_ADDR 0x47000159 + +#define REG_GP_INTERRUPT_MASK_PIN_0_BYTE8_ADDR 0x4700015A + +#define REG_GP_INTERRUPT_MASK_PIN_0_BYTE9_ADDR 0x4700015B + +#define REG_GP_INTERRUPT_MASK_PIN_0_BYTE10_ADDR 0x4700015C + +#define REG_GP_INTERRUPT_MASK_PIN_0_BYTE11_ADDR 0x4700015D + +#ifdef USE_PRIVATE_BF +#define REG_GP_INTERRUPT_STATUS_READ_BYTE0_ADDR 0x4700016A +#define BF_GP_INTERRUPTS_STATUS_LOWER_WORD_INFO 0x4700016A, 0x00003000 +#endif /* USE_PRIVATE_BF */ + +#define REG_GP_INTERRUPT_STATUS_READ_BYTE1_ADDR 0x4700016B + +#define REG_GP_INTERRUPT_STATUS_READ_BYTE2_ADDR 0x4700016C + +#define REG_GP_INTERRUPT_STATUS_READ_BYTE3_ADDR 0x4700016D + +#define REG_GP_INTERRUPT_STATUS_READ_BYTE4_ADDR 0x4700016E + +#define REG_GP_INTERRUPT_STATUS_READ_BYTE5_ADDR 0x4700016F + +#ifdef USE_PRIVATE_BF +#define REG_GP_INTERRUPT_STATUS_READ_BYTE6_ADDR 0x47000170 +#define BF_GP_INTERRUPTS_STATUS_UPPER_WORD_INFO 0x47000170, 0x00003000 +#endif /* USE_PRIVATE_BF */ + +#define REG_GP_INTERRUPT_STATUS_READ_BYTE7_ADDR 0x47000171 + +#define REG_GP_INTERRUPT_STATUS_READ_BYTE8_ADDR 0x47000172 + +#define REG_GP_INTERRUPT_STATUS_READ_BYTE9_ADDR 0x47000173 + +#define REG_GP_INTERRUPT_STATUS_READ_BYTE10_ADDR 0x47000174 + +#define REG_GP_INTERRUPT_STATUS_READ_BYTE11_ADDR 0x47000175 + +#define REG_GP_INTERRUPT_LEVEL_PULSE_B_BYTE0_ADDR 0x47000176 +#define BF_GP_INTERRUPTS_LEVEL_PULSE_B_LOWER_WORD_INFO 0x47000176, 0x00003000 + +#define REG_GP_INTERRUPT_LEVEL_PULSE_B_BYTE1_ADDR 0x47000177 + +#define REG_GP_INTERRUPT_LEVEL_PULSE_B_BYTE2_ADDR 0x47000178 + +#define REG_GP_INTERRUPT_LEVEL_PULSE_B_BYTE3_ADDR 0x47000179 + +#define REG_GP_INTERRUPT_LEVEL_PULSE_B_BYTE4_ADDR 0x4700017A + +#define REG_GP_INTERRUPT_LEVEL_PULSE_B_BYTE5_ADDR 0x4700017B + +#define REG_GP_INTERRUPT_LEVEL_PULSE_B_BYTE6_ADDR 0x4700017C +#define BF_GP_INTERRUPTS_LEVEL_PULSE_B_UPPER_WORD_INFO 0x4700017C, 0x00003000 + +#define REG_GP_INTERRUPT_LEVEL_PULSE_B_BYTE7_ADDR 0x4700017D + +#define REG_GP_INTERRUPT_LEVEL_PULSE_B_BYTE8_ADDR 0x4700017E + +#define REG_GP_INTERRUPT_LEVEL_PULSE_B_BYTE9_ADDR 0x4700017F + +#define REG_GP_INTERRUPT_LEVEL_PULSE_B_BYTE10_ADDR 0x47000180 + +#define REG_GP_INTERRUPT_LEVEL_PULSE_B_BYTE11_ADDR 0x47000181 + +#define REG_SYNCINB0_A_CNTRL_ADDR 0x47000183 +#define BF_SYNCINB0_A_PAD_EN_INFO 0x47000183, 0x00000100 +#define BF_SYNCINB0_A_PN_INVERT_INFO 0x47000183, 0x00000101 +#define BF_SYNCINB0_A_LVDS_SEL_INFO 0x47000183, 0x00000102 +#define BF_SYNCINB0_A_ALT_LVDS_DOUT_EN_INFO 0x47000183, 0x00000103 +#define BF_SYNCINB0_A_SPI_READ_INFO 0x47000183, 0x00000104 +#define BF_SYNCINB0_A_TERM_EN_INFO 0x47000183, 0x00000105 +#define BF_SYNCINB0_A_ALT_DOUT_MUX_SEL_INFO 0x47000183, 0x00000206 + +#define REG_SYNCINB1_A_CNTRL_ADDR 0x47000184 +#define BF_SYNCINB1_A_PAD_EN_INFO 0x47000184, 0x00000100 +#define BF_SYNCINB1_A_PN_INVERT_INFO 0x47000184, 0x00000101 +#define BF_SYNCINB1_A_LVDS_SEL_INFO 0x47000184, 0x00000102 +#define BF_SYNCINB1_A_ALT_LVDS_DOUT_EN_INFO 0x47000184, 0x00000103 +#define BF_SYNCINB1_A_SPI_READ_INFO 0x47000184, 0x00000104 +#define BF_SYNCINB1_A_TERM_EN_INFO 0x47000184, 0x00000105 +#define BF_SYNCINB1_A_ALT_DOUT_MUX_SEL_INFO 0x47000184, 0x00000206 + +#define REG_SYNCINB0_B_CNTRL_ADDR 0x47000185 +#define BF_SYNCINB0_B_PAD_EN_INFO 0x47000185, 0x00000100 +#define BF_SYNCINB0_B_PN_INVERT_INFO 0x47000185, 0x00000101 +#define BF_SYNCINB0_B_LVDS_SEL_INFO 0x47000185, 0x00000102 +#define BF_SYNCINB0_B_ALT_LVDS_DOUT_EN_INFO 0x47000185, 0x00000103 +#define BF_SYNCINB0_B_SPI_READ_INFO 0x47000185, 0x00000104 +#define BF_SYNCINB0_B_TERM_EN_INFO 0x47000185, 0x00000105 +#define BF_SYNCINB0_B_ALT_DOUT_MUX_SEL_INFO 0x47000185, 0x00000206 + +#define REG_SYNCINB1_B_CNTRL_ADDR 0x47000186 +#define BF_SYNCINB1_B_PAD_EN_INFO 0x47000186, 0x00000100 +#define BF_SYNCINB1_B_PN_INVERT_INFO 0x47000186, 0x00000101 +#define BF_SYNCINB1_B_LVDS_SEL_INFO 0x47000186, 0x00000102 +#define BF_SYNCINB1_B_ALT_LVDS_DOUT_EN_INFO 0x47000186, 0x00000103 +#define BF_SYNCINB1_B_SPI_READ_INFO 0x47000186, 0x00000104 +#define BF_SYNCINB1_B_TERM_EN_INFO 0x47000186, 0x00000105 +#define BF_SYNCINB1_B_ALT_DOUT_MUX_SEL_INFO 0x47000186, 0x00000206 + +#define REG_SYNCOUTB0_A_CNTRL_BYTE0_ADDR 0x47000187 +#define BF_SYNCOUTB0_A_PAD_EN_INFO 0x47000187, 0x00000100 +#define BF_SYNCOUTB0_A_PN_INVERT_INFO 0x47000187, 0x00000101 +#define BF_SYNCOUTB0_A_LVDS_SEL_INFO 0x47000187, 0x00000102 +#define BF_SYNCOUTB0_A_ALT_LVDS_DIN_EN_INFO 0x47000187, 0x00000103 +#define BF_SYNCOUTB0_A_ALT_DIN_MUX_SEL_INFO 0x47000187, 0x00000206 + +#define REG_SYNCOUTB0_A_CNTRL_BYTE1_ADDR 0x47000188 +#define BF_SYNCOUTB0_A_GPIO_STAGE_SEL_INFO 0x47000188, 0x00000100 +#define BF_SYNCOUTB0_A_GPIO_DEBUG_SOURCE_SEL_INFO 0x47000188, 0x00000601 + +#define REG_SYNCOUTB1_A_CNTRL_BYTE0_ADDR 0x47000189 +#define BF_SYNCOUTB1_A_PAD_EN_INFO 0x47000189, 0x00000100 +#define BF_SYNCOUTB1_A_PN_INVERT_INFO 0x47000189, 0x00000101 +#define BF_SYNCOUTB1_A_LVDS_SEL_INFO 0x47000189, 0x00000102 +#define BF_SYNCOUTB1_A_ALT_LVDS_DIN_EN_INFO 0x47000189, 0x00000103 +#define BF_SYNCOUTB1_A_ALT_DIN_MUX_SEL_INFO 0x47000189, 0x00000206 + +#define REG_SYNCOUTB1_A_CNTRL_BYTE1_ADDR 0x4700018A +#define BF_SYNCOUTB1_A_GPIO_STAGE_SEL_INFO 0x4700018A, 0x00000100 +#define BF_SYNCOUTB1_A_GPIO_DEBUG_SOURCE_SEL_INFO 0x4700018A, 0x00000601 + +#define REG_SYNCOUTB0_B_CNTRL_BYTE0_ADDR 0x4700018B +#define BF_SYNCOUTB0_B_PAD_EN_INFO 0x4700018B, 0x00000100 +#define BF_SYNCOUTB0_B_PN_INVERT_INFO 0x4700018B, 0x00000101 +#define BF_SYNCOUTB0_B_LVDS_SEL_INFO 0x4700018B, 0x00000102 +#define BF_SYNCOUTB0_B_ALT_LVDS_DIN_EN_INFO 0x4700018B, 0x00000103 +#define BF_SYNCOUTB0_B_ALT_DIN_MUX_SEL_INFO 0x4700018B, 0x00000206 + +#define REG_SYNCOUTB0_B_CNTRL_BYTE1_ADDR 0x4700018C +#define BF_SYNCOUTB0_B_GPIO_STAGE_SEL_INFO 0x4700018C, 0x00000100 +#define BF_SYNCOUTB0_B_GPIO_DEBUG_SOURCE_SEL_INFO 0x4700018C, 0x00000601 + +#define REG_SYNCOUTB1_B_CNTRL_BYTE0_ADDR 0x4700018D +#define BF_SYNCOUTB1_B_PAD_EN_INFO 0x4700018D, 0x00000100 +#define BF_SYNCOUTB1_B_PN_INVERT_INFO 0x4700018D, 0x00000101 +#define BF_SYNCOUTB1_B_LVDS_SEL_INFO 0x4700018D, 0x00000102 +#define BF_SYNCOUTB1_B_ALT_LVDS_DIN_EN_INFO 0x4700018D, 0x00000103 +#define BF_SYNCOUTB1_B_ALT_DIN_MUX_SEL_INFO 0x4700018D, 0x00000206 + +#define REG_SYNCOUTB1_B_CNTRL_BYTE1_ADDR 0x4700018E +#define BF_SYNCOUTB1_B_GPIO_STAGE_SEL_INFO 0x4700018E, 0x00000100 +#define BF_SYNCOUTB1_B_GPIO_DEBUG_SOURCE_SEL_INFO 0x4700018E, 0x00000601 + +#ifdef USE_PRIVATE_BF +#define REG_SCAN_CONFIG_BYTE0_ADDR 0x47000190 +#define BF_SCAN_COMP_EN_INFO 0x47000190, 0x00000100 +#define BF_SCAN_OPCG_EN_INFO 0x47000190, 0x00000101 +#define BF_TEST_ENTRY_PATTERN_INFO 0x47000190, 0x00000502 +#endif /* USE_PRIVATE_BF */ + +#define REG_TEST_MODE_REGISTER_ADDR 0x47000191 +#ifdef USE_PRIVATE_BF +#define BF_TEST_MODE_CONTROL_INFO 0x47000191, 0x00000300 +#endif /* USE_PRIVATE_BF */ +#define BF_TEST_MODE_EN_INFO 0x47000191, 0x00000103 + +#define REG_OPCG_CLK_SEL_REG_ADDR 0x47000192 +#define BF_OPCG_CLK_SELECT_INFO 0x47000192, 0x00000700 + +#ifdef USE_PRIVATE_BF +#define REG_EFUSE_OVERRIDE_0_ADDR 0x4700019A +#define BF_EFUSE_OVERRIDES_LOWER_WORD_INFO 0x4700019A, 0x00003000 +#endif /* USE_PRIVATE_BF */ + +#define REG_EFUSE_OVERRIDE_1_ADDR 0x4700019B + +#define REG_EFUSE_OVERRIDE_2_ADDR 0x4700019C + +#define REG_EFUSE_OVERRIDE_3_ADDR 0x4700019D + +#define REG_EFUSE_OVERRIDE_4_ADDR 0x4700019E + +#define REG_EFUSE_OVERRIDE_5_ADDR 0x4700019F + +#ifdef USE_PRIVATE_BF +#define REG_EFUSE_OVERRIDE_6_ADDR 0x470001A0 +#define BF_EFUSE_OVERRIDES_UPPER_WORD_INFO 0x470001A0, 0x00003000 +#endif /* USE_PRIVATE_BF */ + +#define REG_EFUSE_OVERRIDE_7_ADDR 0x470001A1 + +#define REG_EFUSE_OVERRIDE_8_ADDR 0x470001A2 + +#define REG_EFUSE_OVERRIDE_9_ADDR 0x470001A3 + +#define REG_EFUSE_OVERRIDE_10_ADDR 0x470001A4 + +#define REG_EFUSE_OVERRIDE_11_ADDR 0x470001A5 + +#ifdef USE_PRIVATE_BF +#define REG_EFUSE_OVERRIDE_CTL_ADDR 0x470001A6 +#define BF_EFUSE_OVER_RIDE_ENABLE_INFO 0x470001A6, 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_MONITOR_0_ADDR 0x470001A8 +#define BF_CONTROL_OUT_SEL_INFO 0x470001A8, 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_MONITOR_1_ADDR 0x470001A9 +#define BF_RX_CONTROL_OUT_SEL_INFO 0x470001A9, 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_MONITOR_2_ADDR 0x470001AB +#define BF_CONTROL_OUT_ENABLE_INFO 0x470001AB, 0x00000100 +#define BF_RX_CONTROL_OUT_ENABLE_INFO 0x470001AB, 0x00000101 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_MONITOR_3_ADDR 0x470001AE +#define BF_RX_ORX_ANY_SOURCE_MUX_SEL_10_INFO 0x470001AE, 0x00000300 +#define BF_RX_ORX_ANY_SOURCE_MUX_SEL_32_INFO 0x470001AE, 0x00000303 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_MONITOR_4_ADDR 0x470001AF +#define BF_RX_ORX_ANY_SOURCE_MUX_SEL_54_INFO 0x470001AF, 0x00000300 +#define BF_RX_ORX_ANY_SOURCE_MUX_SEL_76_INFO 0x470001AF, 0x00000303 +#endif /* USE_PRIVATE_BF */ + +#define REG_DRV_STRENGTH_CONTROL_0_ADDR 0x470001B1 +#define BF_REFCLK_CLK_PLL_DRVR_STRENGTH_INFO 0x470001B1, 0x00000200 +#define BF_REFCLK_SERDES_PLL_DRVR_STRENGTH_INFO 0x470001B1, 0x00000206 + +#define REG_SCRATCH_REGS_ADDR(n) (0x47000200 + 1 * (n)) +#define BF_SCRATCH_REG_INFO(n) (0x47000200 + 1 * (n)), 0x00000800 + +#define REG_SP_DBG_GLBL_CTL_ADDR 0x47000300 +#define BF_SP_DBG_GLOBAL_HALT_INFO 0x47000300, 0x00000100 +#define BF_SP_DBG_GLOBAL_RESUME_INFO 0x47000300, 0x00000101 + +#define REG_RX_SP_DBG_TRIG_MASK_ADDR 0x47000301 +#define BF_RX_SP_DBG_TRIG_MASK_INFO 0x47000301, 0x00000800 + +#define REG_TX_SP_DBG_TRIG_MASK_ADDR 0x47000302 +#define BF_TX_SP_DBG_TRIG_MASK_INFO 0x47000302, 0x00000800 + +#define REG_ORX_MAIN_SP_DBG_TRIG_MASK_ADDR 0x47000303 +#define BF_ORX_SP_DBG_TRIG_MASK_INFO 0x47000303, 0x00000200 +#define BF_MAIN_SP_DBG_TRIG_MASK_INFO 0x47000303, 0x00000104 + +#define REG_MAIN_SP_DBG_STATUS_ADDR 0x47000307 +#define BF_MAIN_SP_DBG_STAT_INFO 0x47000307, 0x00000100 + +#define REG_ORX_SP_DBG_STATUS_ADDR 0x47000308 +#define BF_ORX_SLICE_SP_DBG_STAT_INFO 0x47000308, 0x00000200 + +#define REG_RX_SP_DBG_STATUS_ADDR 0x47000309 +#define BF_RX_SLICE_SP_DBG_STAT_INFO 0x47000309, 0x00000800 + +#define REG_TX_SP_DBG_STATUS_ADDR 0x4700030A +#define BF_TX_SLICE_SP_DBG_STAT_INFO 0x4700030A, 0x00000800 + +#define REG_JESD_EVENT_FIFO_STATUS_ADDR 0x4700030B +#define BF_JESD_EVENT_FIFO_WR_FULL_INFO 0x4700030B, 0x00000800 + +#define REG_AHB_ERROR_HMASTER_ADDR 0x4700030C +#define BF_AHB_ERR_HMASTER_INFO 0x4700030C, 0x00000400 + +#define REG_AHB_ERROR_HADDR_BYTE3_ADDR 0x4700030D + +#define REG_AHB_ERROR_HADDR_BYTE2_ADDR 0x4700030E + +#define REG_AHB_ERROR_HADDR_BYTE1_ADDR 0x4700030F + +#define REG_AHB_ERROR_HADDR_BYTE0_ADDR 0x47000310 +#define BF_AHB_ERR_HADDR_INFO 0x47000310, 0x00002000 + +#define REG_AHB_ERROR_TYPE_ADDR 0x47000311 +#define BF_AHB_ERR_HSIZE_INFO 0x47000311, 0x00000300 +#ifdef USE_HW_BF +#define BF_AHB_ERR_HWRITE_INFO 0x47000311, 0x00000103 +#endif /* USE_HW_BF */ + +#define REG_AHB_ERROR_LOCATOR_ADDR 0x47000313 +#define BF_AHB_ERROR_LOCATOR_INFO 0x47000313, 0x00000500 + +#define REG_MASTER_AHB_ERROR_HRESP_MASK_ADDR 0x47000315 +#define BF_AHB_ERROR_HRESP_MASK_ARM0_INFO 0x47000315, 0x00000100 +#define BF_AHB_ERROR_HRESP_MASK_ARM1_INFO 0x47000315, 0x00000101 + +#define REG_MASTER_AHB_ERROR_INTERRUPT_MASK_ADDR 0x47000316 +#define BF_AHB_ERROR_INTERRUPT_MASK_SPI0_INFO 0x47000316, 0x00000100 +#define BF_AHB_ERROR_INTERRUPT_MASK_SPI1_INFO 0x47000316, 0x00000101 +#define BF_AHB_ERROR_INTERRUPT_MASK_ARM0_INFO 0x47000316, 0x00000102 +#define BF_AHB_ERROR_INTERRUPT_MASK_ARM1_INFO 0x47000316, 0x00000103 +#define BF_AHB_ERROR_INTERRUPT_MASK_CORE_STREAM_PROC_INFO 0x47000316, 0x00000104 +#define BF_AHB_ERROR_INTERRUPT_MASK_KFA_STREAM_PROC_INFO 0x47000316, 0x00000105 + +#ifdef USE_PRIVATE_BF +#define REG_STREAM_PROC_GPIO_PIN_MASK_1_ADDR 0x47000317 +#define BF_STREAM_PROC_GPIO_PIN_MASK_INFO 0x47000317, 0x00001800 +#endif /* USE_PRIVATE_BF */ + +#define REG_STREAM_PROC_GPIO_PIN_MASK_2_ADDR 0x47000318 + +#define REG_STREAM_PROC_GPIO_PIN_MASK_3_ADDR 0x47000319 + +#ifdef USE_PRIVATE_BF +#define REG_JESD_CONTROL_CONFIG_ADDR 0x4700031A +#define BF_JESD_CONTROL_TRIGGER_MASK_INFO 0x4700031A, 0x00000100 +#define BF_JESD_CONTROL_TRIGGER_1_MASK_INFO 0x4700031A, 0x00000101 +#define BF_JESD_CONTROL_TRIGGER_2_MASK_INFO 0x4700031A, 0x00000102 +#define BF_JESD_CONTROL_TRIGGER_3_MASK_INFO 0x4700031A, 0x00000103 +#define BF_JESD_CONTROL_TRIGGER_4_MASK_INFO 0x4700031A, 0x00000104 +#define BF_JESD_CONTROL_TRIGGER_5_MASK_INFO 0x4700031A, 0x00000105 +#define BF_JESD_CONTROL_TRIGGER_6_MASK_INFO 0x4700031A, 0x00000106 +#define BF_JESD_CONTROL_TRIGGER_7_MASK_INFO 0x4700031A, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_STREAM_PROC_GP_IRQ_MASK_ADDR 0x4700031B +#define BF_STREAM_PROC_GP_IRQ_MASK_INFO 0x4700031B, 0x00000200 +#endif /* USE_PRIVATE_BF */ + +#define REG_REFCLK_CLKSYNTH_CONTROL_ADDR 0x47000338 +#define BF_CLKPLL_REFPATH_PD_INFO 0x47000338, 0x00000100 +#define BF_CLKPLL_REFCLK_ENABLE_CLKB_INFO 0x47000338, 0x00000101 +#define BF_CLKPLL_INVERT_REFCLK_INFO 0x47000338, 0x00000102 +#define BF_CLKPLL_INVERT_SYNC_PULSE_INFO 0x47000338, 0x00000103 +#define BF_CLKPLL_FORCE_REFCLK_PATH_ON_INFO 0x47000338, 0x00000104 + +#define REG_REFCLK_CLKSYNTH_CONTROL2_ADDR 0x47000339 +#define BF_CLKPLL_DELAY_REFCLK_INFO 0x47000339, 0x00000400 +#define BF_CLKPLL_DELAY_SYNC_PULSE_INFO 0x47000339, 0x00000404 + +#define REG_REFCLK_SERDES_SYNTH_CONTROL_ADDR 0x4700033A +#define BF_SERDES_PLL_REFPATH_PD_INFO 0x4700033A, 0x00000100 +#define BF_SERDES_PLL_REFCLK_ENABLE_CLKB_INFO 0x4700033A, 0x00000101 +#define BF_SERDES_PLL_INVERT_REFCLK_INFO 0x4700033A, 0x00000102 +#define BF_SERDES_PLL_INVERT_SYNC_PULSE_INFO 0x4700033A, 0x00000103 +#define BF_SERDES_PLL_FORCE_REFCLK_PATH_ON_INFO 0x4700033A, 0x00000104 + +#define REG_REFCLK_SERDES_SYNTH_CONTROL2_ADDR 0x4700033B +#define BF_SERDES_PLL_DELAY_REFCLK_INFO 0x4700033B, 0x00000400 +#define BF_SERDES_PLL_DELAY_SYNC_PULSE_INFO 0x4700033B, 0x00000404 + +#define REG_XTRIG_CTL_ADDR 0x470003F0 +#define BF_XTRIG_EN_INFO 0x470003F0, 0x00000100 + +#define REG_XTRIG_MASK1_ADDR(n) (0x470003F1 + 3 * (n)) +#define BF_TRIG_MASK_INFO(n) (0x470003F1 + 3 * (n)), 0x00001500 + +#define REG_XTRIG_MASK2_ADDR(n) (0x470003F2 + 3 * (n)) + +#define REG_XTRIG_MASK3_ADDR(n) (0x470003F3 + 3 * (n)) + +#ifdef USE_PRIVATE_BF +#define REG_STREAM_PROC_DEBUG_REG_ARRAY_ADDR(n) (0x47000523 + 1 * (n)) +#define BF_STREAMPROC_DEBUG_DATA_INFO(n) (0x47000523 + 1 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_STREAM_PROC_ECC_STATUS_ADDR 0x47000543 +#define BF_MAIN_STREAMPROC_ERROR_STATUS_INFO 0x47000543, 0x00000100 +#define BF_MAIN_STREAMPROC_ERROR_CLEAR_INFO 0x47000543, 0x00000101 + +#ifdef USE_PRIVATE_BF +#define REG_DIG_CORE_FABRIC_DUAL_RANGE_CONTROL_ADDR 0x47000544 +#define BF_DIG_CORE_FABRIC_DUAL_RANGE_ENABLE_INFO 0x47000544, 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_DEBUG_KEY_STATUS_ADDR 0x4700054E +#define BF_DEBUG_KEY_UNLOCKED_INFO 0x4700054E, 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#define REG_CMOS_PAD_DS_ADDR 0x47000550 +#define BF_PAD_DS_INFO 0x47000550, 0x00000400 + +#define REG_CMOS_PAD_ST_BYTE0_ADDR 0x47000551 +#define BF_PAD_ST_GPIO_INFO 0x47000551, 0x00002F00 + +#define REG_CMOS_PAD_ST_BYTE1_ADDR 0x47000552 + +#define REG_CMOS_PAD_ST_BYTE2_ADDR 0x47000553 + +#define REG_CMOS_PAD_ST_BYTE3_ADDR 0x47000554 + +#define REG_CMOS_PAD_ST_BYTE4_ADDR 0x47000555 + +#define REG_CMOS_PAD_ST_BYTE5_ADDR 0x47000556 + +#define REG_CMOS_PAD_ST_BYTE6_ADDR 0x47000557 +#define BF_PAD_ST_SCK_INFO 0x47000557, 0x00000100 +#define BF_PAD_ST_SCSB_INFO 0x47000557, 0x00000101 +#define BF_PAD_ST_RESETN_INFO 0x47000557, 0x00000102 +#define BF_PAD_ST_SDIO_INFO 0x47000557, 0x00000103 +#define BF_PAD_ST_SDO_INFO 0x47000557, 0x00000104 + +#define REG_ALT_BOOT_ADDR(n) (0x47000558 + 1 * (n)) +#define BF_ALT_BOOT_INFO(n) (0x47000558 + 1 * (n)), 0x00000800 + +#define REG_RX_A0_PORB_STATUS_ADDR 0x47000582 +#define BF_PORB_RX_A0_VDDA1P0_INFO 0x47000582, 0x00000100 +#define BF_PORB_RX_A0_VDDA1P8_INFO 0x47000582, 0x00000101 +#define BF_PORB_RX_A0_VDDACK1P0_INFO 0x47000582, 0x00000102 +#define BF_PORB_RX_A0_VDDD0P8_INFO 0x47000582, 0x00000103 +#define BF_PORB_RX_A0_VDDD1P0_INFO 0x47000582, 0x00000104 + +#define REG_RX_A1_PORB_STATUS_ADDR 0x47000583 +#define BF_PORB_RX_A1_VDDA1P0_INFO 0x47000583, 0x00000100 +#define BF_PORB_RX_A1_VDDA1P8_INFO 0x47000583, 0x00000101 +#define BF_PORB_RX_A1_VDDACK1P0_INFO 0x47000583, 0x00000102 +#define BF_PORB_RX_A1_VDDD0P8_INFO 0x47000583, 0x00000103 +#define BF_PORB_RX_A1_VDDD1P0_INFO 0x47000583, 0x00000104 + +#define REG_RX_B0_PORB_STATUS_ADDR 0x47000584 +#define BF_PORB_RX_B0_VDDA1P0_INFO 0x47000584, 0x00000100 +#define BF_PORB_RX_B0_VDDA1P8_INFO 0x47000584, 0x00000101 +#define BF_PORB_RX_B0_VDDACK1P0_INFO 0x47000584, 0x00000102 +#define BF_PORB_RX_B0_VDDD0P8_INFO 0x47000584, 0x00000103 +#define BF_PORB_RX_B0_VDDD1P0_INFO 0x47000584, 0x00000104 + +#define REG_RX_B1_PORB_STATUS_ADDR 0x47000585 +#define BF_PORB_RX_B1_VDDA1P0_INFO 0x47000585, 0x00000100 +#define BF_PORB_RX_B1_VDDA1P8_INFO 0x47000585, 0x00000101 +#define BF_PORB_RX_B1_VDDACK1P0_INFO 0x47000585, 0x00000102 +#define BF_PORB_RX_B1_VDDD0P8_INFO 0x47000585, 0x00000103 +#define BF_PORB_RX_B1_VDDD1P0_INFO 0x47000585, 0x00000104 + +#define REG_TX_A0_PORB_STATUS_ADDR 0x47000586 +#define BF_PORB_TX_A0_VDDA1P0_INFO 0x47000586, 0x00000100 +#define BF_PORB_TX_A0_VDDA1P8_INFO 0x47000586, 0x00000101 +#define BF_PORB_TX_A0_VDDC1P0_INFO 0x47000586, 0x00000102 +#define BF_PORB_TX_A0_VDDD1P0_INFO 0x47000586, 0x00000103 +#define BF_PORB_TX_A0_VNEG_INFO 0x47000586, 0x00000104 +#define BF_PORB_TX_A0_VDDA2P5_INFO 0x47000586, 0x00000105 + +#define REG_TX_A1_PORB_STATUS_ADDR 0x47000587 +#define BF_PORB_TX_A1_VDDA1P0_INFO 0x47000587, 0x00000100 +#define BF_PORB_TX_A1_VDDA1P8_INFO 0x47000587, 0x00000101 +#define BF_PORB_TX_A1_VDDC1P0_INFO 0x47000587, 0x00000102 +#define BF_PORB_TX_A1_VDDD1P0_INFO 0x47000587, 0x00000103 +#define BF_PORB_TX_A1_VNEG_INFO 0x47000587, 0x00000104 +#define BF_PORB_TX_A1_VDDA2P5_INFO 0x47000587, 0x00000105 + +#define REG_TX_A2_PORB_STATUS_ADDR 0x47000588 +#define BF_PORB_TX_A2_VDDA1P0_INFO 0x47000588, 0x00000100 +#define BF_PORB_TX_A2_VDDA1P8_INFO 0x47000588, 0x00000101 +#define BF_PORB_TX_A2_VDDC1P0_INFO 0x47000588, 0x00000102 +#define BF_PORB_TX_A2_VDDD1P0_INFO 0x47000588, 0x00000103 +#define BF_PORB_TX_A2_VNEG_INFO 0x47000588, 0x00000104 +#define BF_PORB_TX_A2_VDDA2P5_INFO 0x47000588, 0x00000105 + +#define REG_TX_A3_PORB_STATUS_ADDR 0x47000589 +#define BF_PORB_TX_A3_VDDA1P0_INFO 0x47000589, 0x00000100 +#define BF_PORB_TX_A3_VDDA1P8_INFO 0x47000589, 0x00000101 +#define BF_PORB_TX_A3_VDDC1P0_INFO 0x47000589, 0x00000102 +#define BF_PORB_TX_A3_VDDD1P0_INFO 0x47000589, 0x00000103 +#define BF_PORB_TX_A3_VNEG_INFO 0x47000589, 0x00000104 +#define BF_PORB_TX_A3_VDDA2P5_INFO 0x47000589, 0x00000105 + +#define REG_TX_B0_PORB_STATUS_ADDR 0x4700058A +#define BF_PORB_TX_B0_VDDA1P0_INFO 0x4700058A, 0x00000100 +#define BF_PORB_TX_B0_VDDA1P8_INFO 0x4700058A, 0x00000101 +#define BF_PORB_TX_B0_VDDC1P0_INFO 0x4700058A, 0x00000102 +#define BF_PORB_TX_B0_VDDD1P0_INFO 0x4700058A, 0x00000103 +#define BF_PORB_TX_B0_VNEG_INFO 0x4700058A, 0x00000104 +#define BF_PORB_TX_B0_VDDA2P5_INFO 0x4700058A, 0x00000105 + +#define REG_TX_B1_PORB_STATUS_ADDR 0x4700058B +#define BF_PORB_TX_B1_VDDA1P0_INFO 0x4700058B, 0x00000100 +#define BF_PORB_TX_B1_VDDA1P8_INFO 0x4700058B, 0x00000101 +#define BF_PORB_TX_B1_VDDC1P0_INFO 0x4700058B, 0x00000102 +#define BF_PORB_TX_B1_VDDD1P0_INFO 0x4700058B, 0x00000103 +#define BF_PORB_TX_B1_VNEG_INFO 0x4700058B, 0x00000104 +#define BF_PORB_TX_B1_VDDA2P5_INFO 0x4700058B, 0x00000105 + +#define REG_TX_B2_PORB_STATUS_ADDR 0x4700058C +#define BF_PORB_TX_B2_VDDA1P0_INFO 0x4700058C, 0x00000100 +#define BF_PORB_TX_B2_VDDA1P8_INFO 0x4700058C, 0x00000101 +#define BF_PORB_TX_B2_VDDC1P0_INFO 0x4700058C, 0x00000102 +#define BF_PORB_TX_B2_VDDD1P0_INFO 0x4700058C, 0x00000103 +#define BF_PORB_TX_B2_VNEG_INFO 0x4700058C, 0x00000104 +#define BF_PORB_TX_B2_VDDA2P5_INFO 0x4700058C, 0x00000105 + +#define REG_TX_B3_PORB_STATUS_ADDR 0x4700058D +#define BF_PORB_TX_B3_VDDA1P0_INFO 0x4700058D, 0x00000100 +#define BF_PORB_TX_B3_VDDA1P8_INFO 0x4700058D, 0x00000101 +#define BF_PORB_TX_B3_VDDC1P0_INFO 0x4700058D, 0x00000102 +#define BF_PORB_TX_B3_VDDD1P0_INFO 0x4700058D, 0x00000103 +#define BF_PORB_TX_B3_VNEG_INFO 0x4700058D, 0x00000104 +#define BF_PORB_TX_B3_VDDA2P5_INFO 0x4700058D, 0x00000105 + +#define REG_SERDES_PORB_STATUS_ADDR 0x4700058E +#define BF_PORB_DES_VDDA1P0_INFO 0x4700058E, 0x00000100 +#define BF_PORB_SER_VDDA1P0_INFO 0x4700058E, 0x00000101 +#define BF_PORB_SERDES_CK_VDDA1P0_INFO 0x4700058E, 0x00000102 +#define BF_PORB_SERDES_PLL_VDDA1P0_INFO 0x4700058E, 0x00000103 +#define BF_PORB_SERDES_PLL_VDDA1P8_INFO 0x4700058E, 0x00000104 +#define BF_PORB_SERDES_VDDD0P8_INFO 0x4700058E, 0x00000105 + +#define REG_MCS_MB_CK_PORB_STATUS_ADDR 0x4700058F +#define BF_PORB_CK_VDDA1P0_INFO 0x4700058F, 0x00000100 +#define BF_PORB_MB_A_VDDA1P0_INFO 0x4700058F, 0x00000101 +#define BF_PORB_MB_A_VDDA1P8_INFO 0x4700058F, 0x00000102 +#define BF_PORB_MB_B_VDDA1P0_INFO 0x4700058F, 0x00000103 +#define BF_PORB_MB_B_VDDA1P8_INFO 0x4700058F, 0x00000104 +#define BF_PORB_MCS_VDDD1P0_INFO 0x4700058F, 0x00000105 + +#define REG_RX_A_IRMON_CTRL_ADDR 0x47000590 +#define BF_RX_A_IRMON_CTRL_INFO 0x47000590, 0x00000800 + +#define REG_RX_B_IRMON_CTRL_ADDR 0x47000591 +#define BF_RX_B_IRMON_CTRL_INFO 0x47000591, 0x00000800 + +#define REG_TX_A_IRMON_CTRL_ADDR 0x47000592 +#define BF_TX_A_IRMON_CTRL_INFO 0x47000592, 0x00000800 + +#define REG_TX_B_IRMON_CTRL_ADDR 0x47000593 +#define BF_TX_B_IRMON_CTRL_INFO 0x47000593, 0x00000800 + +#define REG_TRACE_CORE_SELECT_REG_ADDR 0x4700077E +#define BF_TRACE_CORE_SELECT_INFO 0x4700077E, 0x00000100 + +#define REG_XTRIG_DAP_MODE_TRIG_CTL_ADDR 0x47000786 +#define BF_XTRIG_DAP_MODE_TRIG_EN_INFO 0x47000786, 0x00000100 + +#define REG_XTRIG_PROG_COUNT_THRES_ADDR 0x47000787 +#define BF_PROG_FSM_COUNT_THRES_INFO 0x47000787, 0x00000400 +#define BF_PROG_FSM_COUNT_THRES1_INFO 0x47000787, 0x00000404 + +#define REG_XTRIG_PROG_DP_ADDR1_1_ADDR 0x47000788 +#define BF_PROG_DP_ADDR1_INFO 0x47000788, 0x00002000 + +#define REG_XTRIG_PROG_DP_ADDR1_2_ADDR 0x47000789 + +#define REG_XTRIG_PROG_DP_ADDR1_3_ADDR 0x4700078A + +#define REG_XTRIG_PROG_DP_ADDR1_4_ADDR 0x4700078B + +#define REG_XTRIG_PROG_DP_ADDR2_1_ADDR 0x4700078C +#define BF_PROG_DP_ADDR2_INFO 0x4700078C, 0x00002000 + +#define REG_XTRIG_PROG_DP_ADDR2_2_ADDR 0x4700078D + +#define REG_XTRIG_PROG_DP_ADDR2_3_ADDR 0x4700078E + +#define REG_XTRIG_PROG_DP_ADDR2_4_ADDR 0x4700078F + +#define REG_XTRIG_PROG_DP_ADDR3_1_ADDR 0x47000790 +#define BF_PROG_DP_ADDR3_INFO 0x47000790, 0x00002000 + +#define REG_XTRIG_PROG_DP_ADDR3_2_ADDR 0x47000791 + +#define REG_XTRIG_PROG_DP_ADDR3_3_ADDR 0x47000792 + +#define REG_XTRIG_PROG_DP_ADDR3_4_ADDR 0x47000793 + +#define REG_XTRIG_PROG_DP_ADDR4_1_ADDR 0x47000794 +#define BF_PROG_DP_ADDR4_INFO 0x47000794, 0x00002000 + +#define REG_XTRIG_PROG_DP_ADDR4_2_ADDR 0x47000795 + +#define REG_XTRIG_PROG_DP_ADDR4_3_ADDR 0x47000796 + +#define REG_XTRIG_PROG_DP_ADDR4_4_ADDR 0x47000797 + +#define REG_XTRIG_PROG_DP_ADDR5_1_ADDR 0x47000798 +#define BF_PROG_DP_ADDR5_INFO 0x47000798, 0x00002000 + +#define REG_XTRIG_PROG_DP_ADDR5_2_ADDR 0x47000799 + +#define REG_XTRIG_PROG_DP_ADDR5_3_ADDR 0x4700079A + +#define REG_XTRIG_PROG_DP_ADDR5_4_ADDR 0x4700079B + +#define REG_XTRIG_PROG_DP_ADDR6_1_ADDR 0x4700079C +#define BF_PROG_DP_ADDR6_INFO 0x4700079C, 0x00002000 + +#define REG_XTRIG_PROG_DP_ADDR6_2_ADDR 0x4700079D + +#define REG_XTRIG_PROG_DP_ADDR6_3_ADDR 0x4700079E + +#define REG_XTRIG_PROG_DP_ADDR6_4_ADDR 0x4700079F + +#define REG_XTRIG_PROG_DP_ADDR7_1_ADDR 0x470007A0 +#define BF_PROG_DP_ADDR7_INFO 0x470007A0, 0x00002000 + +#define REG_XTRIG_PROG_DP_ADDR7_2_ADDR 0x470007A1 + +#define REG_XTRIG_PROG_DP_ADDR7_3_ADDR 0x470007A2 + +#define REG_XTRIG_PROG_DP_ADDR7_4_ADDR 0x470007A3 + +#define REG_XTRIG_PROG_DP_ADDR8_1_ADDR 0x470007A4 +#define BF_PROG_DP_ADDR8_INFO 0x470007A4, 0x00002000 + +#define REG_XTRIG_PROG_DP_ADDR8_2_ADDR 0x470007A5 + +#define REG_XTRIG_PROG_DP_ADDR8_3_ADDR 0x470007A6 + +#define REG_XTRIG_PROG_DP_ADDR8_4_ADDR 0x470007A7 + +#define REG_XTRIG_PROG_DP_ADDR9_1_ADDR 0x470007A8 +#define BF_PROG_DP_ADDR9_INFO 0x470007A8, 0x00002000 + +#define REG_XTRIG_PROG_DP_ADDR9_2_ADDR 0x470007A9 + +#define REG_XTRIG_PROG_DP_ADDR9_3_ADDR 0x470007AA + +#define REG_XTRIG_PROG_DP_ADDR9_4_ADDR 0x470007AB + +#define REG_XTRIG_PROG_DP_ADDR10_1_ADDR 0x470007AC +#define BF_PROG_DP_ADDR10_INFO 0x470007AC, 0x00002000 + +#define REG_XTRIG_PROG_DP_ADDR10_2_ADDR 0x470007AD + +#define REG_XTRIG_PROG_DP_ADDR10_3_ADDR 0x470007AE + +#define REG_XTRIG_PROG_DP_ADDR10_4_ADDR 0x470007AF + +#define REG_XTRIG_PROG_DP_VAL1_1_ADDR 0x470007B6 +#define BF_PROG_DP_VAL1_INFO 0x470007B6, 0x00002000 + +#define REG_XTRIG_PROG_DP_VAL1_2_ADDR 0x470007B7 + +#define REG_XTRIG_PROG_DP_VAL1_3_ADDR 0x470007B8 + +#define REG_XTRIG_PROG_DP_VAL1_4_ADDR 0x470007B9 + +#define REG_XTRIG_PROG_DP_VAL2_1_ADDR 0x470007BA +#define BF_PROG_DP_VAL2_INFO 0x470007BA, 0x00002000 + +#define REG_XTRIG_PROG_DP_VAL2_2_ADDR 0x470007BB + +#define REG_XTRIG_PROG_DP_VAL2_3_ADDR 0x470007BC + +#define REG_XTRIG_PROG_DP_VAL2_4_ADDR 0x470007BD + +#define REG_XTRIG_PROG_DP_VAL3_1_ADDR 0x470007BE +#define BF_PROG_DP_VAL3_INFO 0x470007BE, 0x00002000 + +#define REG_XTRIG_PROG_DP_VAL3_2_ADDR 0x470007BF + +#define REG_XTRIG_PROG_DP_VAL3_3_ADDR 0x470007C0 + +#define REG_XTRIG_PROG_DP_VAL3_4_ADDR 0x470007C1 + +#define REG_XTRIG_PROG_DP_VAL4_1_ADDR 0x470007C2 +#define BF_PROG_DP_VAL4_INFO 0x470007C2, 0x00002000 + +#define REG_XTRIG_PROG_DP_VAL4_2_ADDR 0x470007C3 + +#define REG_XTRIG_PROG_DP_VAL4_3_ADDR 0x470007C4 + +#define REG_XTRIG_PROG_DP_VAL4_4_ADDR 0x470007C5 + +#define REG_XTRIG_PROG_DP_VAL5_1_ADDR 0x470007C6 +#define BF_PROG_DP_VAL5_INFO 0x470007C6, 0x00002000 + +#define REG_XTRIG_PROG_DP_VAL5_2_ADDR 0x470007C7 + +#define REG_XTRIG_PROG_DP_VAL5_3_ADDR 0x470007C8 + +#define REG_XTRIG_PROG_DP_VAL5_4_ADDR 0x470007C9 + +#define REG_XTRIG_PROG_DP_VAL6_1_ADDR 0x470007CA +#define BF_PROG_DP_VAL6_INFO 0x470007CA, 0x00002000 + +#define REG_XTRIG_PROG_DP_VAL6_2_ADDR 0x470007CB + +#define REG_XTRIG_PROG_DP_VAL6_3_ADDR 0x470007CC + +#define REG_XTRIG_PROG_DP_VAL6_4_ADDR 0x470007CD + +#define REG_XTRIG_PROG_DP_VAL7_1_ADDR 0x470007CE +#define BF_PROG_DP_VAL7_INFO 0x470007CE, 0x00002000 + +#define REG_XTRIG_PROG_DP_VAL7_2_ADDR 0x470007CF + +#define REG_XTRIG_PROG_DP_VAL7_3_ADDR 0x470007D0 + +#define REG_XTRIG_PROG_DP_VAL7_4_ADDR 0x470007D1 + +#define REG_XTRIG_PROG_DP_VAL8_1_ADDR 0x470007D2 +#define BF_PROG_DP_VAL8_INFO 0x470007D2, 0x00002000 + +#define REG_XTRIG_PROG_DP_VAL8_2_ADDR 0x470007D3 + +#define REG_XTRIG_PROG_DP_VAL8_3_ADDR 0x470007D4 + +#define REG_XTRIG_PROG_DP_VAL8_4_ADDR 0x470007D5 + +#define REG_XTRIG_PROG_DP_VAL9_1_ADDR 0x470007D6 +#define BF_PROG_DP_VAL9_INFO 0x470007D6, 0x00002000 + +#define REG_XTRIG_PROG_DP_VAL9_2_ADDR 0x470007D7 + +#define REG_XTRIG_PROG_DP_VAL9_3_ADDR 0x470007D8 + +#define REG_XTRIG_PROG_DP_VAL9_4_ADDR 0x470007D9 + +#define REG_XTRIG_PROG_DP_VAL10_1_ADDR 0x470007DA +#define BF_PROG_DP_VAL10_INFO 0x470007DA, 0x00002000 + +#define REG_XTRIG_PROG_DP_VAL10_2_ADDR 0x470007DB + +#define REG_XTRIG_PROG_DP_VAL10_3_ADDR 0x470007DC + +#define REG_XTRIG_PROG_DP_VAL10_4_ADDR 0x470007DD + +#define REG_XTRIG_PROG_DP1_ADDR1_1_ADDR 0x470007DE +#define BF_PROG_DP1_ADDR1_INFO 0x470007DE, 0x00002000 + +#define REG_XTRIG_PROG_DP1_ADDR1_2_ADDR 0x470007DF + +#define REG_XTRIG_PROG_DP1_ADDR1_3_ADDR 0x470007E0 + +#define REG_XTRIG_PROG_DP1_ADDR1_4_ADDR 0x470007E1 + +#define REG_XTRIG_PROG_DP1_ADDR2_1_ADDR 0x470007E2 +#define BF_PROG_DP1_ADDR2_INFO 0x470007E2, 0x00002000 + +#define REG_XTRIG_PROG_DP1_ADDR2_2_ADDR 0x470007E3 + +#define REG_XTRIG_PROG_DP1_ADDR2_3_ADDR 0x470007E4 + +#define REG_XTRIG_PROG_DP1_ADDR2_4_ADDR 0x470007E5 + +#define REG_XTRIG_PROG_DP1_ADDR3_1_ADDR 0x470007E6 +#define BF_PROG_DP1_ADDR3_INFO 0x470007E6, 0x00002000 + +#define REG_XTRIG_PROG_DP1_ADDR3_2_ADDR 0x470007E7 + +#define REG_XTRIG_PROG_DP1_ADDR3_3_ADDR 0x470007E8 + +#define REG_XTRIG_PROG_DP1_ADDR3_4_ADDR 0x470007E9 + +#define REG_XTRIG_PROG_DP1_ADDR4_1_ADDR 0x470007EA +#define BF_PROG_DP1_ADDR4_INFO 0x470007EA, 0x00002000 + +#define REG_XTRIG_PROG_DP1_ADDR4_2_ADDR 0x470007EB + +#define REG_XTRIG_PROG_DP1_ADDR4_3_ADDR 0x470007EC + +#define REG_XTRIG_PROG_DP1_ADDR4_4_ADDR 0x470007ED + +#define REG_XTRIG_PROG_DP1_ADDR5_1_ADDR 0x470007EE +#define BF_PROG_DP1_ADDR5_INFO 0x470007EE, 0x00002000 + +#define REG_XTRIG_PROG_DP1_ADDR5_2_ADDR 0x470007EF + +#define REG_XTRIG_PROG_DP1_ADDR5_3_ADDR 0x470007F0 + +#define REG_XTRIG_PROG_DP1_ADDR5_4_ADDR 0x470007F1 + +#define REG_XTRIG_PROG_DP1_ADDR6_1_ADDR 0x470007F2 +#define BF_PROG_DP1_ADDR6_INFO 0x470007F2, 0x00002000 + +#define REG_XTRIG_PROG_DP1_ADDR6_2_ADDR 0x470007F3 + +#define REG_XTRIG_PROG_DP1_ADDR6_3_ADDR 0x470007F4 + +#define REG_XTRIG_PROG_DP1_ADDR6_4_ADDR 0x470007F5 + +#define REG_XTRIG_PROG_DP1_ADDR7_1_ADDR 0x470007F6 +#define BF_PROG_DP1_ADDR7_INFO 0x470007F6, 0x00002000 + +#define REG_XTRIG_PROG_DP1_ADDR7_2_ADDR 0x470007F7 + +#define REG_XTRIG_PROG_DP1_ADDR7_3_ADDR 0x470007F8 + +#define REG_XTRIG_PROG_DP1_ADDR7_4_ADDR 0x470007F9 + +#define REG_XTRIG_PROG_DP1_ADDR8_1_ADDR 0x470007FA +#define BF_PROG_DP1_ADDR8_INFO 0x470007FA, 0x00002000 + +#define REG_XTRIG_PROG_DP1_ADDR8_2_ADDR 0x470007FB + +#define REG_XTRIG_PROG_DP1_ADDR8_3_ADDR 0x470007FC + +#define REG_XTRIG_PROG_DP1_ADDR8_4_ADDR 0x470007FD + +#define REG_XTRIG_PROG_DP1_ADDR9_1_ADDR 0x470007FE +#define BF_PROG_DP1_ADDR9_INFO 0x470007FE, 0x00002000 + +#define REG_XTRIG_PROG_DP1_ADDR9_2_ADDR 0x470007FF + +#define REG_XTRIG_PROG_DP1_ADDR9_3_ADDR 0x47000800 + +#define REG_XTRIG_PROG_DP1_ADDR9_4_ADDR 0x47000801 + +#define REG_XTRIG_PROG_DP1_ADDR10_1_ADDR 0x47000802 +#define BF_PROG_DP1_ADDR10_INFO 0x47000802, 0x00002000 + +#define REG_XTRIG_PROG_DP1_ADDR10_2_ADDR 0x47000803 + +#define REG_XTRIG_PROG_DP1_ADDR10_3_ADDR 0x47000804 + +#define REG_XTRIG_PROG_DP1_ADDR10_4_ADDR 0x47000805 + +#define REG_XTRIG_PROG_DP1_VAL1_1_ADDR 0x47000806 +#define BF_PROG_DP1_VAL1_INFO 0x47000806, 0x00002000 + +#define REG_XTRIG_PROG_DP1_VAL1_2_ADDR 0x47000807 + +#define REG_XTRIG_PROG_DP1_VAL1_3_ADDR 0x47000808 + +#define REG_XTRIG_PROG_DP1_VAL1_4_ADDR 0x47000809 + +#define REG_XTRIG_PROG_DP1_VAL2_1_ADDR 0x4700080A +#define BF_PROG_DP1_VAL2_INFO 0x4700080A, 0x00002000 + +#define REG_XTRIG_PROG_DP1_VAL2_2_ADDR 0x4700080B + +#define REG_XTRIG_PROG_DP1_VAL2_3_ADDR 0x4700080C + +#define REG_XTRIG_PROG_DP1_VAL2_4_ADDR 0x4700080D + +#define REG_XTRIG_PROG_DP1_VAL3_1_ADDR 0x4700080E +#define BF_PROG_DP1_VAL3_INFO 0x4700080E, 0x00002000 + +#define REG_XTRIG_PROG_DP1_VAL3_2_ADDR 0x4700080F + +#define REG_XTRIG_PROG_DP1_VAL3_3_ADDR 0x47000810 + +#define REG_XTRIG_PROG_DP1_VAL3_4_ADDR 0x47000811 + +#define REG_XTRIG_PROG_DP1_VAL4_1_ADDR 0x47000812 +#define BF_PROG_DP1_VAL4_INFO 0x47000812, 0x00002000 + +#define REG_XTRIG_PROG_DP1_VAL4_2_ADDR 0x47000813 + +#define REG_XTRIG_PROG_DP1_VAL4_3_ADDR 0x47000814 + +#define REG_XTRIG_PROG_DP1_VAL4_4_ADDR 0x47000815 + +#define REG_XTRIG_PROG_DP1_VAL5_1_ADDR 0x47000816 +#define BF_PROG_DP1_VAL5_INFO 0x47000816, 0x00002000 + +#define REG_XTRIG_PROG_DP1_VAL5_2_ADDR 0x47000817 + +#define REG_XTRIG_PROG_DP1_VAL5_3_ADDR 0x47000818 + +#define REG_XTRIG_PROG_DP1_VAL5_4_ADDR 0x47000819 + +#define REG_XTRIG_PROG_DP1_VAL6_1_ADDR 0x4700081A +#define BF_PROG_DP1_VAL6_INFO 0x4700081A, 0x00002000 + +#define REG_XTRIG_PROG_DP1_VAL6_2_ADDR 0x4700081B + +#define REG_XTRIG_PROG_DP1_VAL6_3_ADDR 0x4700081C + +#define REG_XTRIG_PROG_DP1_VAL6_4_ADDR 0x4700081D + +#define REG_XTRIG_PROG_DP1_VAL7_1_ADDR 0x4700081E +#define BF_PROG_DP1_VAL7_INFO 0x4700081E, 0x00002000 + +#define REG_XTRIG_PROG_DP1_VAL7_2_ADDR 0x4700081F + +#define REG_XTRIG_PROG_DP1_VAL7_3_ADDR 0x47000820 + +#define REG_XTRIG_PROG_DP1_VAL7_4_ADDR 0x47000821 + +#define REG_XTRIG_PROG_DP1_VAL8_1_ADDR 0x47000822 +#define BF_PROG_DP1_VAL8_INFO 0x47000822, 0x00002000 + +#define REG_XTRIG_PROG_DP1_VAL8_2_ADDR 0x47000823 + +#define REG_XTRIG_PROG_DP1_VAL8_3_ADDR 0x47000824 + +#define REG_XTRIG_PROG_DP1_VAL8_4_ADDR 0x47000825 + +#define REG_XTRIG_PROG_DP1_VAL9_1_ADDR 0x47000826 +#define BF_PROG_DP1_VAL9_INFO 0x47000826, 0x00002000 + +#define REG_XTRIG_PROG_DP1_VAL9_2_ADDR 0x47000827 + +#define REG_XTRIG_PROG_DP1_VAL9_3_ADDR 0x47000828 + +#define REG_XTRIG_PROG_DP1_VAL9_4_ADDR 0x47000829 + +#define REG_XTRIG_PROG_DP1_VAL10_1_ADDR 0x4700082A +#define BF_PROG_DP1_VAL10_INFO 0x4700082A, 0x00002000 + +#define REG_XTRIG_PROG_DP1_VAL10_2_ADDR 0x4700082B + +#define REG_XTRIG_PROG_DP1_VAL10_3_ADDR 0x4700082C + +#define REG_XTRIG_PROG_DP1_VAL10_4_ADDR 0x4700082D + +#define REG_RX_DIG_RESET_ADDR 0x4700082F +#define BF_SOFT_RESET_RX_A_INFO 0x4700082F, 0x00000100 +#define BF_SOFT_RESET_RX_B_INFO 0x4700082F, 0x00000101 +#define BF_RX_DP_RESET_A_INFO 0x4700082F, 0x00000102 +#define BF_RX_DP_RESET_B_INFO 0x4700082F, 0x00000103 +#define BF_RX_DIG_REGMAP_RESET_A_INFO 0x4700082F, 0x00000104 +#define BF_RX_DIG_REGMAP_RESET_B_INFO 0x4700082F, 0x00000105 + +#define REG_TX_DIG_RESET_ADDR 0x47000830 +#define BF_SOFT_RESET_TX_A_INFO 0x47000830, 0x00000100 +#define BF_SOFT_RESET_TX_B_INFO 0x47000830, 0x00000101 +#define BF_TX_DP_RESET_A_INFO 0x47000830, 0x00000102 +#define BF_TX_DP_RESET_B_INFO 0x47000830, 0x00000103 +#define BF_TX_DIG_REGMAP_RESET_A_INFO 0x47000830, 0x00000104 +#define BF_TX_DIG_REGMAP_RESET_B_INFO 0x47000830, 0x00000105 + +#define REG_VENUS_IP_RESET_A_ADDR 0x47000831 +#define BF_VENUS_ADC_REG8_A_INFO 0x47000831, 0x00000200 +#define BF_VENUS_ADC_REG32_A_INFO 0x47000831, 0x00000202 +#define BF_VENUS_ADC_DP_RESET_A_INFO 0x47000831, 0x00000404 + +#define REG_VENUS_IP_RESET_B_ADDR 0x47000832 +#define BF_VENUS_ADC_REG8_B_INFO 0x47000832, 0x00000200 +#define BF_VENUS_ADC_REG32_B_INFO 0x47000832, 0x00000202 +#define BF_VENUS_ADC_DP_RESET_B_INFO 0x47000832, 0x00000404 + +#define REG_DAC_IP_RESET_A_ADDR 0x47000833 +#define BF_DAC_RMAP_RESET_A_INFO 0x47000833, 0x00000400 +#define BF_DAC_DP_RESET_A_INFO 0x47000833, 0x00000404 + +#define REG_DAC_IP_RESET_B_ADDR 0x47000834 +#define BF_DAC_RMAP_RESET_B_INFO 0x47000834, 0x00000400 +#define BF_DAC_DP_RESET_B_INFO 0x47000834, 0x00000404 + +#define REG_SERDES_IP_RSTN_ADDR 0x47000835 +#define BF_TXSER_DP_RESET_A_INFO 0x47000835, 0x00000100 +#define BF_TXSER_DP_RESET_B_INFO 0x47000835, 0x00000101 +#define BF_RXDES_DP_RESET_A_INFO 0x47000835, 0x00000102 +#define BF_RXDES_DP_RESET_B_INFO 0x47000835, 0x00000103 +#define BF_SERDES_PLL_REG_RESET_INFO 0x47000835, 0x00000104 + +#define REG_MISC_RESETS_ADDR 0x47000836 +#define BF_SOFT_RESET_REST_INFO 0x47000836, 0x00000100 +#define BF_ANA_CENTER_RESET_INFO 0x47000836, 0x00000101 +#define BF_OSC_CLK_EN_INFO 0x47000836, 0x00000102 + +#define REG_GPIO_MODE_CONTROL_BYTE0_ADDR 0x47000839 +#define BF_GPIO_MODE_EN_INFO 0x47000839, 0x00002F00 + +#define REG_GPIO_MODE_CONTROL_BYTE1_ADDR 0x4700083A + +#define REG_GPIO_MODE_CONTROL_BYTE2_ADDR 0x4700083B + +#define REG_GPIO_MODE_CONTROL_BYTE3_ADDR 0x4700083C + +#define REG_GPIO_MODE_CONTROL_BYTE4_ADDR 0x4700083D + +#define REG_GPIO_MODE_CONTROL_BYTE5_ADDR 0x4700083E + +#define REG_GPIO_MODE_DIR_BYTE0_ADDR 0x4700083F +#define BF_GPIO_MODE_DIR_INFO 0x4700083F, 0x00002F00 + +#define REG_GPIO_MODE_DIR_BYTE1_ADDR 0x47000840 + +#define REG_GPIO_MODE_DIR_BYTE2_ADDR 0x47000841 + +#define REG_GPIO_MODE_DIR_BYTE3_ADDR 0x47000842 + +#define REG_GPIO_MODE_DIR_BYTE4_ADDR 0x47000843 + +#define REG_GPIO_MODE_DIR_BYTE5_ADDR 0x47000844 + +#define REG_GPIO_FROM_MASTER_BYTE0_ADDR 0x47000845 +#define BF_GPIO_FROM_MASTER_INFO 0x47000845, 0x00002F00 + +#define REG_GPIO_FROM_MASTER_BYTE1_ADDR 0x47000846 + +#define REG_GPIO_FROM_MASTER_BYTE2_ADDR 0x47000847 + +#define REG_GPIO_FROM_MASTER_BYTE3_ADDR 0x47000848 + +#define REG_GPIO_FROM_MASTER_BYTE4_ADDR 0x47000849 + +#define REG_GPIO_FROM_MASTER_BYTE5_ADDR 0x4700084A + +#define REG_GPIO_FROM_MASTER_SET_BYTE0_ADDR 0x4700084B +#define BF_GPIO_FROM_SET_INFO 0x4700084B, 0x00002F00 + +#define REG_GPIO_FROM_MASTER_SET_BYTE1_ADDR 0x4700084C + +#define REG_GPIO_FROM_MASTER_SET_BYTE2_ADDR 0x4700084D + +#define REG_GPIO_FROM_MASTER_SET_BYTE3_ADDR 0x4700084E + +#define REG_GPIO_FROM_MASTER_SET_BYTE4_ADDR 0x4700084F + +#define REG_GPIO_FROM_MASTER_SET_BYTE5_ADDR 0x47000850 + +#define REG_GPIO_FROM_MASTER_CLEAR_BYTE0_ADDR 0x47000851 +#define BF_GPIO_FROM_CLEAR_INFO 0x47000851, 0x00002F00 + +#define REG_GPIO_FROM_MASTER_CLEAR_BYTE1_ADDR 0x47000852 + +#define REG_GPIO_FROM_MASTER_CLEAR_BYTE2_ADDR 0x47000853 + +#define REG_GPIO_FROM_MASTER_CLEAR_BYTE3_ADDR 0x47000854 + +#define REG_GPIO_FROM_MASTER_CLEAR_BYTE4_ADDR 0x47000855 + +#define REG_GPIO_FROM_MASTER_CLEAR_BYTE5_ADDR 0x47000856 + +#define REG_GPIO_FROM_MASTER_TOGGLE_BYTE0_ADDR 0x47000857 +#define BF_GPIO_FROM_TOGGLE_INFO 0x47000857, 0x00002F00 + +#define REG_GPIO_FROM_MASTER_TOGGLE_BYTE1_ADDR 0x47000858 + +#define REG_GPIO_FROM_MASTER_TOGGLE_BYTE2_ADDR 0x47000859 + +#define REG_GPIO_FROM_MASTER_TOGGLE_BYTE3_ADDR 0x4700085A + +#define REG_GPIO_FROM_MASTER_TOGGLE_BYTE4_ADDR 0x4700085B + +#define REG_GPIO_FROM_MASTER_TOGGLE_BYTE5_ADDR 0x4700085C + +#define REG_GPIO_SPI_READ_BYTE0_ADDR 0x47000869 +#define BF_GPIO_SPI_READ_INFO 0x47000869, 0x00002F00 + +#define REG_GPIO_SPI_READ_BYTE1_ADDR 0x4700086A + +#define REG_GPIO_SPI_READ_BYTE2_ADDR 0x4700086B + +#define REG_GPIO_SPI_READ_BYTE3_ADDR 0x4700086C + +#define REG_GPIO_SPI_READ_BYTE4_ADDR 0x4700086D + +#define REG_GPIO_SPI_READ_BYTE5_ADDR 0x4700086E + +#define REG_GPIO_SOURCE_CONTROL_ADDR(n) (0x4700086F + 1 * (n)) +#define BF_GPIO_SOURCE_CONTROL_INFO(n) (0x4700086F + 1 * (n)), 0x00000800 + +#define REG_GPIO_STAGE_SEL_BYTE0_ADDR 0x4700089E + +#define REG_GPIO_STAGE_SEL_BYTE1_ADDR 0x4700089F + +#define REG_GPIO_STAGE_SEL_BYTE2_ADDR 0x470008A0 + +#define REG_GPIO_STAGE_SEL_BYTE3_ADDR 0x470008A1 + +#define REG_GPIO_STAGE_SEL_BYTE4_ADDR 0x470008A2 + +#define REG_GPIO_STAGE_SEL_BYTE5_ADDR 0x470008A3 + +#define REG_GPIO_STAGE_SEL_BYTE6_ADDR 0x470008A4 + +#define REG_GPIO_STAGE_SEL_BYTE7_ADDR 0x470008A5 + +#define REG_GPIO_STAGE_SEL_BYTE8_ADDR 0x470008A6 + +#define REG_GPIO_STAGE_SEL_BYTE9_ADDR 0x470008A7 + +#define REG_GPIO_STAGE_SEL_BYTE10_ADDR 0x470008A8 + +#define REG_GPIO_STAGE_SEL_BYTE11_ADDR 0x470008A9 + +#define REG_GPIO_QUICK_CONFIG_ADDR 0x470008AA +#define BF_GPIO_QUICK_CONFIG_INFO 0x470008AA, 0x00000400 + +#define REG_GPIO_PINMUX_REGOUT_BYTE0_ADDR 0x470008AB +#define BF_LNX_SW0_CTL_INFO 0x470008AB, 0x00000200 +#define BF_LNX_SW1_CTL_INFO 0x470008AB, 0x00000202 +#define BF_CLK_DELADJ_INFO 0x470008AB, 0x00000204 +#define BF_CLK_DELSTR_INFO 0x470008AB, 0x00000206 + +#define REG_GPIO_PINMUX_REGOUT_BYTE1_ADDR 0x470008AC +#define BF_FW_IRQ_OUT_INFO 0x470008AC, 0x00000100 +#define BF_CAL_FREEZE_INFO 0x470008AC, 0x00000101 + +#define REG_COMMON_SYNCIN_CTRL_ADDR 0x470008AD +#define BF_COMMON_SYNCIN_LINK0_INFO 0x470008AD, 0x00000100 +#define BF_COMMON_SYNCIN_LINK1_INFO 0x470008AD, 0x00000101 + +#define REG_SERDES_PLL_WR_SETUP_CYCLES_ADDR 0x470008AE +#define BF_SERDES_PLL_ANA_BRIDGE_WR_SETUP_CYCLES_INFO 0x470008AE, 0x00000600 + +#define REG_SERDES_PLL_WR_HOLD_CYCLES_ADDR 0x470008AF +#define BF_SERDES_PLL_ANA_BRIDGE_WR_HOLD_CYCLES_INFO 0x470008AF, 0x00000600 + +#define REG_SERDES_PLL_RD_CYCLES_ADDR 0x470008B0 +#define BF_SERDES_PLL_ANA_BRIDGE_RD_CYCLES_INFO 0x470008B0, 0x00000600 + +#define REG_RTCLK_GEN_WR_SETUP_CYCLES_ADDR 0x470008B1 +#define BF_RTCLK_GEN_ANA_BRIDGE_WR_SETUP_CYCLES_INFO 0x470008B1, 0x00000600 + +#define REG_RTCLK_GEN_WR_HOLD_CYCLES_ADDR 0x470008B2 +#define BF_RTCLK_GEN_ANA_BRIDGE_WR_HOLD_CYCLES_INFO 0x470008B2, 0x00000600 + +#define REG_RTCLK_GEN_RD_CYCLES_ADDR 0x470008B3 +#define BF_RTCLK_GEN_ANA_BRIDGE_RD_CYCLES_INFO 0x470008B3, 0x00000600 + +#define REG_WT_RT_SEL_1024X132_ADDR 0x470008B4 +#define BF_RT_SEL_1024X132_INFO 0x470008B4, 0x00000200 +#define BF_WT_SEL_1024X132_INFO 0x470008B4, 0x00000202 + +#define REG_WT_RT_SEL_1024X39_ADDR 0x470008B5 +#define BF_RT_SEL_1024X39_INFO 0x470008B5, 0x00000200 +#define BF_WT_SEL_1024X39_INFO 0x470008B5, 0x00000202 + +#define REG_WT_RT_SEL_4096X39_ADDR 0x470008B6 +#define BF_RT_SEL_4096X39_INFO 0x470008B6, 0x00000200 +#define BF_WT_SEL_4096X39_INFO 0x470008B6, 0x00000202 + +#define REG_WT_RT_SEL_512X39_ADDR 0x470008B7 +#define BF_RT_SEL_512X39_INFO 0x470008B7, 0x00000200 +#define BF_WT_SEL_512X39_INFO 0x470008B7, 0x00000202 + +#define REG_WT_RT_SEL_64X64_ADDR 0x470008B8 +#define BF_RT_SEL_64X64_INFO 0x470008B8, 0x00000200 +#define BF_WT_SEL_64X64_INFO 0x470008B8, 0x00000202 + +#define REG_WT_RT_SEL_64X10_ADDR 0x470008B9 +#define BF_RT_SEL_64X10_INFO 0x470008B9, 0x00000200 +#define BF_WT_SEL_64X10_INFO 0x470008B9, 0x00000202 + +#define REG_WT_RT_SEL_8192X13_ADDR 0x470008BA +#define BF_RT_SEL_8192X13_INFO 0x470008BA, 0x00000200 +#define BF_WT_SEL_8192X13_INFO 0x470008BA, 0x00000202 + +#define REG_WT_RT_SEL_8192X39_ADDR 0x470008BB +#define BF_RT_SEL_8192X39_INFO 0x470008BB, 0x00000200 +#define BF_WT_SEL_8192X39_INFO 0x470008BB, 0x00000202 + +#define REG_PT_RT_SEL_8192X39_ADDR 0x470008BC +#define BF_ROM_RT_SEL_8192X39_INFO 0x470008BC, 0x00000200 +#define BF_ROM_PT_SEL_8192X39_INFO 0x470008BC, 0x00000202 + +#ifdef USE_PRIVATE_BF +#define REG_ENG_MASK_REVISION_ADDR 0x470008BD +#define BF_ENG_MASK_REVISION_MINOR_INFO 0x470008BD, 0x00000400 +#define BF_ENG_MASK_REVISION_MAJOR_INFO 0x470008BD, 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#define REG_SLICE_STREAM_TO_CORE_STREAM_INTERRUPT_ENABLE_ADDR 0x470008C0 +#define BF_SLICE_TO_CORE_IRQ_ENABLE_INFO 0x470008C0, 0x00000800 + +#define REG_TE_BYPASS_N_MMR_ADDR 0x470008C1 +#define BF_TE_BYPASS_N_MMR_INFO 0x470008C1, 0x00000100 + +#define REG_NVM_BOOT_STATUS_ADDR 0x470008C2 +#define BF_TE_BYPASS_INFO 0x470008C2, 0x00000100 +#define BF_NVM_BOOT_DONE_INFO 0x470008C2, 0x00000101 +#define BF_NVM_ERR_FLAG_TIMEOUT_INFO 0x470008C2, 0x00000102 +#define BF_NVM_ERR_FLAG_BOOT_INFO 0x470008C2, 0x00000103 +#define BF_MC_QUAL_BUSY_INFO 0x470008C2, 0x00000104 +#define BF_TE_FAULT_INFO 0x470008C2, 0x00000105 + +#define REG_EC_RX_BYTE0_ADDR 0x470008C3 +#define BF_EC_RX_INFO 0x470008C3, 0x00002000 + +#define REG_EC_RX_BYTE1_ADDR 0x470008C4 + +#define REG_EC_RX_BYTE2_ADDR 0x470008C5 + +#define REG_EC_RX_BYTE3_ADDR 0x470008C6 + +#define REG_EC_TX_BYTE0_ADDR 0x470008C7 +#define BF_EC_TX_INFO 0x470008C7, 0x00002000 + +#define REG_EC_TX_BYTE1_ADDR 0x470008C8 + +#define REG_EC_TX_BYTE2_ADDR 0x470008C9 + +#define REG_EC_TX_BYTE3_ADDR 0x470008CA + +#define REG_EC_ANA_BYTE0_ADDR 0x470008CB +#define BF_EC_ANA_INFO 0x470008CB, 0x00002000 + +#define REG_EC_ANA_BYTE1_ADDR 0x470008CC + +#define REG_EC_ANA_BYTE2_ADDR 0x470008CD + +#define REG_EC_ANA_BYTE3_ADDR 0x470008CE + +#ifdef USE_PRIVATE_BF +#define REG_DIE_ID_BIT8_OVERRIDE_REG_ADDR 0x470008D0 +#define BF_DIE_ID_BIT8_OVERRIDE_INFO 0x470008D0, 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#define REG_SYSRESETN_DETECT_FLAG_ADDR 0x470008D1 +#define BF_SYSRESETN_DETECT_FLAG_INFO 0x470008D1, 0x00000100 + +#ifdef USE_PRIVATE_BF +#define REG_ACB_REG_BYTE0_ADDR 0x470008D2 +#define BF_TE_SCAN_EN_INFO 0x470008D2, 0x00000100 +#define BF_TE_JTAG_EN_INFO 0x470008D2, 0x00000103 +#define BF_TE_UART_RX_EN_INFO 0x470008D2, 0x00000104 +#define BF_ARM_JTAG_EN_INFO 0x470008D2, 0x00000105 +#define BF_C0_M3_RUN_FINAL_INFO 0x470008D2, 0x00000106 +#define BF_IRAM_ACCESS_EN_INFO 0x470008D2, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ACB_REG_BYTE1_ADDR 0x470008D3 +#define BF_TE_UART_TX_EN_INFO 0x470008D3, 0x00000100 +#define BF_IROM_ACCESS_EN_INFO 0x470008D3, 0x00000104 +#define BF_C1_M3_RUN_FINAL_INFO 0x470008D3, 0x00000106 +#define BF_SYSRESETN_FINAL_INFO 0x470008D3, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ACB_REG_BYTE2_ADDR 0x470008D4 +#define BF_TE_OTP_MASTER_INFO 0x470008D4, 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#endif /* __ADI_APOLLO_BF_CORE_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_custom.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_custom.h new file mode 100644 index 00000000000000..99670d339300ac --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_custom.h @@ -0,0 +1,93 @@ + +/*! + * \brief SPI Register Definition Header File, includes customised bitfield definitions derived from auto-generated headers + * + * \copyright copyright(c) 2018 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_CUSTOM_H__ +#define __ADI_APOLLO_BF_CUSTOM_H__ + +/*=========== I N C L U D E S ============*/ + +#include "adi_apollo_bf_jrx_wrapper.h" +#include "adi_apollo_bf_jtx_dformat.h" +#include "adi_apollo_bf_txrx_cfir_top.h" +#include "adi_apollo_bf_txrx_fine_nco.h" +#include "adi_apollo_bf_core.h" +#include "adi_apollo_bf_apollo_profile_config.h" + +/*============= D E F I N E S ==============*/ + +#define BF_JRX_CORE_PHASE_ADJUST_INFO_LSB(inst, n) REG_JRX_CORE_PHASE_ADJUST0_ADDR(inst, n), 0x00000800 +#define BF_JRX_CORE_PHASE_ADJUST_INFO_MSB(inst, n) REG_JRX_CORE_PHASE_ADJUST1_ADDR(inst, n), 0x00000800 + +#define BF_LINK_TOTAL_INTERP_INFO_LSB(inst, n) REG_GENERAL_JRX_CTRL_5_ADDR(inst, n), 0x00000800 +#define BF_LINK_TOTAL_INTERP_INFO_MSB(inst, n) REG_GENERAL_JRX_CTRL_6_ADDR(inst, n), 0x00000800 + +#define BF_LINK_DUC_INTERP_INFO_LSB(inst, n) REG_GENERAL_JRX_CTRL_8_ADDR(inst, n), 0x00000800 +#define BF_LINK_DUC_INTERP_INFO_MSB(inst, n) REG_GENERAL_JRX_CTRL_9_ADDR(inst, n), 0x00000800 + +#define BF_INVALID_EN_0_INFO(inst) REG_INVALID_EN_ADDR(inst), 0x00000100 +#define BF_INVALID_EN_1_INFO(inst) REG_INVALID_EN_ADDR(inst), 0x00000101 + +#define BF_COEFF_PROFILE_SEL0_INFO(inst) REG_CFIR_PROFILE_ADDR(inst), 0x00000100 +#define BF_COEFF_PROFILE_SEL1_INFO(inst) REG_CFIR_PROFILE_ADDR(inst), 0x00000101 +#define BF_COEFF_PROFILE_SEL2_INFO(inst) REG_CFIR_PROFILE_ADDR(inst), 0x00000102 +#define BF_COEFF_PROFILE_SEL3_INFO(inst) REG_CFIR_PROFILE_ADDR(inst), 0x00000103 + +#define BF_AUTOFLIP_INCDIR_FTW_TXRX_FINE_NCO_INFO(inst) REG_AUTOFLIP_INCDIR_ADDR(inst), 0x00000100 +#define BF_AUTOFLIP_INCDIR_PHOFST_TXRX_FINE_NCO_INFO(inst) REG_AUTOFLIP_INCDIR_ADDR(inst), 0x00000102 + +#define BF_AUTO_INC_DECB_FTW_TXRX_FINE_NCO_INFO(inst) REG_AUTO_INC_DECB_ADDR(inst), 0x00000100 +#define BF_AUTO_INC_DECB_PHOFST_TXRX_FINE_NCO_INFO(inst) REG_AUTO_INC_DECB_ADDR(inst), 0x00000102 +#define BF_HOP_PHASE_INC_INFO(inst) REG_HOP_PHASE_INC0_ADDR(inst), 0x00002000 +#define BF_HOP_PHASE_OFFSET_INFO(inst) REG_HOP_PHASE_OFFSET0_ADDR(inst), 0x00001000 + +#define MEM_CODE_MEMORY_B_0 (0x02000000U) //arm_mem.yda +#define MEM_CODE_MEMORY_A_6 (0x01030000U) //arm_mem.yda +#define MEM_SYS_MEMORY_B_0 (0x21000000U) //arm_mem.yda +#define MEM_SYS_MEMORY_B_MAX (0x21050000U + 0x8000U) //arm_mem.yda +#define BF_CPU_0_PRIMARY BF_SCRATCH_REG_INFO(16) //FW startup code +#define BF_CPU_1_PRIMARY BF_SCRATCH_REG_INFO(17) //FW startup code +#define BF_EC_RAM_LOCK_INFO REG_EC_ANA_BYTE3_ADDR, 0x00000106 +#define BF_EC_RAM_LOCK_MASK (0x40) +#define BF_CONFIG_TRANSFER_DONE REG_ALT_BOOT_ADDR(0), 0x00000100 +#define BF_WAITING_FOR_CONFIG_TRANSFER_STATUS REG_ALT_BOOT_ADDR(0), 0x00000101 +#define BF_BOOT_STALL_STATUS REG_ALT_BOOT_ADDR(0), 0x00000102 +#define BF_BOOT_DONE_STATUS REG_ALT_BOOT_ADDR(0), 0x00000107 +#define BF_BOOT_ERROR REG_ALT_BOOT_ADDR(1), 0x00000800 +#define BF_BOOT_STATUS REG_ALT_BOOT_ADDR(2), 0x00000800 +#define REG_RAM_BOOT_ERROR_PTR (0x020003B4U) +#define BF_RAM_BOOT_CORE0_STATUS (0x47000200U), 0x00000800 +#define BF_RAM_BOOT_CORE1_STATUS (0x47000201U), 0x00000800 + +#define BF_DEVICE_PROFILE_CRC_CHECK_STATUS BF_SCRATCH_REG_INFO(6) + +#define BF_NVMB_TE_BYPASS_INFO (0x4C0023E8U), 0x00000106U +#define BF_TE_BOOT_READY_SET REG_ALT_BOOT_ADDR(23), 0x00000800 +#define REG_SECURE_BOOT_STAGE0 (0x4C006342U) +#define REG_SECURE_BOOT_STAGE1 (0x4C006343U) + +// Enhancements to adi_apollo_bf_apollo_profile_config.h +#define BF_PC_RX_FNCO_SLICE_SELECT_INFO(inst) (0x00000100 + inst) +#define BF_PC_TX_FNCO_SLICE_SELECT_INFO(inst) (0x00000110 + inst) +#define BF_PC_RX_CNCO_SLICE_SELECT_INFO(inst) (0x00000100 + inst) +#define BF_PC_TX_CNCO_SLICE_SELECT_INFO(inst) (0x00000108 + inst) +#define BF_PC_RX_CFIR_SLICE_SELECT_INFO(inst) (0x00000100 + inst) +#define BF_PC_TX_CFIR_SLICE_SELECT_INFO(inst) (0x00000110 + inst) +#define BF_PC_RX_PFILT_SLICE_SELECT_INFO(inst) (0x00000100 + inst) +#define BF_PC_TX_PFILT_SLICE_SELECT_INFO(inst) (0x00000102 + inst) +#define BF_PC_RX_DR_SLICE_SELECT_INFO(inst) (0x00000100 + inst) +#define BF_PC_TX_DR_SLICE_SELECT_INFO(inst) (0x00000108 + inst) +#define BF_PC_BMEM_HOP_SLICE_SELECT_INFO(inst) (0x00000100 + inst) + +#endif /* __ADI_APOLLO_BF_CUSTOM_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_ec.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_ec.h new file mode 100644 index 00000000000000..4fe8981a323812 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_ec.h @@ -0,0 +1,146 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:18 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_EC_H__ +#define __ADI_APOLLO_BF_EC_H__ + +/*============= D E F I N E S ==============*/ +#define REG_CHIPID_0_EC_ADDR 0x4C004200 + +#define REG_CHIPID_1_EC_ADDR 0x4C004201 + +#define REG_CHIPID_2_EC_ADDR 0x4C004202 + +#define REG_CHIPID_3_EC_ADDR 0x4C004203 + +#define REG_CHIPID_4_EC_ADDR 0x4C004204 + +#define REG_CHIPID_5_EC_ADDR 0x4C004205 + +#define REG_CHIPID_6_EC_ADDR 0x4C004206 + +#define REG_CHIPID_7_EC_ADDR 0x4C004207 + +#define REG_CHIPID_8_EC_ADDR 0x4C004208 + +#define REG_CHIPID_9_EC_ADDR 0x4C004209 + +#define REG_CHIPID_10_EC_ADDR 0x4C00420A + +#define REG_CHIPID_11_EC_ADDR 0x4C00420B + +#define REG_CHIPID_12_EC_ADDR 0x4C00420C + +#define REG_CHIPID_13_EC_ADDR 0x4C00420D + +#define REG_CHIPID_14_EC_ADDR 0x4C00420E + +#define REG_CHIPID_15_EC_ADDR 0x4C00420F + +#define REG_GROUPID_0_EC_ADDR 0x4C004210 +#define BF_NVM_GROUPID_INFO 0x4C004210, 0x00002000 + +#define REG_GROUPID_1_EC_ADDR 0x4C004211 + +#define REG_GROUPID_2_EC_ADDR 0x4C004212 + +#define REG_GROUPID_3_EC_ADDR 0x4C004213 + +#ifdef USE_PRIVATE_BF +#define REG_NVM_GENERAL_CTRL0_ADDR 0x4C004214 +#define BF_NVM_GENERAL_CTRL_INFO 0x4C004214, 0x00004000 +#endif /* USE_PRIVATE_BF */ + +#define REG_NVM_GENERAL_CTRL1_ADDR 0x4C004215 + +#define REG_NVM_GENERAL_CTRL2_ADDR 0x4C004216 + +#define REG_NVM_GENERAL_CTRL3_ADDR 0x4C004217 + +#define REG_NVM_GENERAL_CTRL4_ADDR 0x4C004218 + +#define REG_NVM_GENERAL_CTRL5_ADDR 0x4C004219 + +#define REG_NVM_GENERAL_CTRL6_ADDR 0x4C00421A + +#define REG_NVM_GENERAL_CTRL7_ADDR 0x4C00421B + +#ifdef USE_PRIVATE_BF +#define REG_NVM_EC_TORX0_ADDR 0x4C00421C +#define BF_NVM_EC_TORX_INFO 0x4C00421C, 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_NVM_EC_TORX1_ADDR 0x4C00421D + +#define REG_NVM_EC_TORX2_ADDR 0x4C00421E + +#define REG_NVM_EC_TORX3_ADDR 0x4C00421F + +#ifdef USE_PRIVATE_BF +#define REG_NVM_EC_TOTX0_ADDR 0x4C004220 +#define BF_NVM_EC_TOTX_INFO 0x4C004220, 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_NVM_EC_TOTX1_ADDR 0x4C004221 + +#define REG_NVM_EC_TOTX2_ADDR 0x4C004222 + +#define REG_NVM_EC_TOTX3_ADDR 0x4C004223 + +#ifdef USE_PRIVATE_BF +#define REG_NVM_EC_TOANA0_ADDR 0x4C004224 +#define BF_NVM_EC_TOANA_INFO 0x4C004224, 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_NVM_EC_TOANA1_ADDR 0x4C004225 + +#define REG_NVM_EC_TOANA2_ADDR 0x4C004226 + +#define REG_NVM_EC_TOANA3_ADDR 0x4C004227 + +#define REG_NVM_REG0X3_ADDR 0x4C004228 +#define BF_NVM_REG0X3_INFO 0x4C004228, 0x00000800 + +#define REG_NVM_REG0X4_ADDR 0x4C004229 +#define BF_NVM_REG0X4_INFO 0x4C004229, 0x00000800 + +#define REG_NVM_REG0X5_ADDR 0x4C00422A +#define BF_NVM_REG0X5_INFO 0x4C00422A, 0x00000800 + +#define REG_NVM_REG0X6_ADDR 0x4C00422B +#define BF_NVM_REG0X6_INFO 0x4C00422B, 0x00000800 + +#define REG_NVM_REG0XC_ADDR 0x4C00422C +#define BF_NVM_REG0XC_INFO 0x4C00422C, 0x00000800 + +#define REG_NVM_REG0XD_ADDR 0x4C00422D +#define BF_NVM_REG0XD_INFO 0x4C00422D, 0x00000800 + +#define REG_SEQUENTIAL_SN_0_EC_ADDR 0x4C00422E +#define BF_SEQUENTIAL_SN_0_EC_INFO 0x4C00422E, 0x00000800 + +#define REG_SEQUENTIAL_SN_1_EC_ADDR 0x4C00422F +#define BF_SEQUENTIAL_SN_1_EC_INFO 0x4C00422F, 0x00000800 + +#define REG_MAIN_FW_REVID_0_ADDR 0x4C004230 +#define BF_NVM_FW_MAIN_REVID_INFO 0x4C004230, 0x00002000 + +#define REG_MAIN_FW_REVID_1_ADDR 0x4C004231 + +#define REG_MAIN_FW_REVID_2_ADDR 0x4C004232 + +#define REG_MAIN_FW_REVID_3_ADDR 0x4C004233 + +#endif /* __ADI_APOLLO_BF_EC_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_hsci.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_hsci.h new file mode 100644 index 00000000000000..3ef07b1b93868f --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_hsci.h @@ -0,0 +1,139 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:18 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_HSCI_H__ +#define __ADI_APOLLO_BF_HSCI_H__ + +/*============= D E F I N E S ==============*/ +#define REG_MAIN_CTRL_ADDR 0x4C000000 +#define BF_HSCI_EN_INFO 0x4C000000, 0x00000100 +#define BF_HSCI_RX_LINKUP_MODE_INFO 0x4C000000, 0x00000101 +#define BF_HSCI_LPBK_MODE_INFO 0x4C000000, 0x00000102 +#define BF_HSCI_RD_AUTO_INC_DIS_INFO 0x4C000000, 0x00000103 +#define BF_HSCI_WR_AUTO_INC_DIS_INFO 0x4C000000, 0x00000104 +#define BF_HSCI_ERR_IRQ_CLR_INFO 0x4C000000, 0x00000105 +#define BF_HSCI_SOFT_RESET_INFO 0x4C000000, 0x00000106 +#define BF_HSCI_HARD_RESET_INFO 0x4C000000, 0x00000107 + +#define REG_MAIN_CTRL2_ADDR 0x4C000001 +#define BF_HSCI_BURST_MODE_INFO 0x4C000001, 0x00000200 +#define BF_DIS_SEND_ERR_INFO 0x4C000001, 0x00000102 +#define BF_HSCI_AUTO_LINKUP_INFO 0x4C000001, 0x00000103 +#define BF_TXCLK_ADJ_OVERRIDE_INFO 0x4C000001, 0x00000104 +#define BF_LINK_ACITVE_INFO 0x4C000001, 0x00000105 +#define BF_HSCI_READ_IN_PROG_INFO 0x4C000001, 0x00000106 +#define BF_HSCI_WRITE_IN_PROG_INFO 0x4C000001, 0x00000107 + +#define REG_RX_CLK_ADJUST_ADDR 0x4C000002 +#define BF_HSCI_RXCLK_ADJ_INFO 0x4C000002, 0x00000400 +#define BF_HSCI_RXCLK_INV_INFO 0x4C000002, 0x00000104 + +#define REG_TX_CLK_ADJUST_ADDR 0x4C000003 +#define BF_HSCI_TXCLK_ADJ_INFO 0x4C000003, 0x00000400 +#define BF_HSCI_TXCLK_INV_INFO 0x4C000003, 0x00000104 + +#define REG_ERROR_STATUS_ADDR 0x4C000004 +#define BF_UNKNOWN_CMD_INFO 0x4C000004, 0x00000100 +#define BF_BAD_PARITY_DET_INFO 0x4C000004, 0x00000101 +#define BF_ADDR_SIZE_ERR_INFO 0x4C000004, 0x00000102 +#define BF_BYTE_NUM_SIZE_ERR_INFO 0x4C000004, 0x00000103 +#define BF_WR_FIFO_FULL_INFO 0x4C000004, 0x00000104 +#define BF_RD_FIFO_FULL_INFO 0x4C000004, 0x00000105 +#define BF_READY_TO_ERR_INFO 0x4C000004, 0x00000106 +#define BF_HRESP_ERR_INFO 0x4C000004, 0x00000107 + +#define REG_ERROR_FLAG_DIS_ADDR 0x4C000005 +#define BF_UNKNOWN_CMD_DIS_INFO 0x4C000005, 0x00000100 +#define BF_BAD_PARITY_DET_DIS_INFO 0x4C000005, 0x00000101 +#define BF_ADDR_SIZE_ERR_DIS_INFO 0x4C000005, 0x00000102 +#define BF_BYTE_NUM_SIZE_ERR_DIS_INFO 0x4C000005, 0x00000103 +#define BF_WR_FIFO_FULL_DIS_INFO 0x4C000005, 0x00000104 +#define BF_RD_FIFO_FULL_DIS_INFO 0x4C000005, 0x00000105 +#define BF_READY_TO_ERR_DIS_INFO 0x4C000005, 0x00000106 +#define BF_HRESP_ERR_DIS_INFO 0x4C000005, 0x00000107 + +#define REG_HREADY_TO_REG_ADDR 0x4C000006 +#define BF_READY_TIME_OUT_CNT_INFO 0x4C000006, 0x00000200 +#define BF_HSCI_CTRL_RX_EYE_EN_INFO 0x4C000006, 0x00000102 + +#define REG_POS_EYE_DIAG_LB_ADDR 0x4C000007 +#define BF_HSCI_DIG_EYE_POS_INFO 0x4C000007, 0x00001000 + +#define REG_POS_EYE_DIAG_HB_ADDR 0x4C000008 + +#define REG_NEG_EYE_DIAG_LB_ADDR 0x4C000009 +#define BF_HSCI_DIG_EYE_NEG_INFO 0x4C000009, 0x00001000 + +#define REG_NEG_EYE_DIAG_HB_ADDR 0x4C00000A + +#define REG_FSM_STATUS_ADDR 0x4C00000B +#define BF_RXDES_STATE_INFO 0x4C00000B, 0x00000300 +#define BF_TXFIFO_STATE_INFO 0x4C00000B, 0x00000404 + +#define REG_AHB_FSM_STATUS_ADDR 0x4C00000C +#define BF_AHB_BUS_STATE_INFO 0x4C00000C, 0x00000300 +#define BF_AUTO_LINK_FSM_INFO 0x4C00000C, 0x00000404 + +#define REG_AUTO_LINK_TABLE_LO_ADDR 0x4C00000D +#define BF_AUTO_LINK_TABLE_INFO 0x4C00000D, 0x00001000 + +#define REG_AUTO_LINK_TABLE_HI_ADDR 0x4C00000E + +#define REG_AUTO_LINK_CNTR_DEF_ADDR 0x4C00000F +#define BF_ACQ_CNTR_DEF_INFO 0x4C00000F, 0x00000200 +#define BF_LPBK_CNTR_DEF_INFO 0x4C00000F, 0x00000202 +#define BF_LOCK_FRM_CNTR_DEF_INFO 0x4C00000F, 0x00000204 + +#define REG_AUTO_LINK_RXCLK_ADJ_ADDR 0x4C000010 +#define BF_AUTO_RXCLK_ADJ_INFO 0x4C000010, 0x00000400 +#define BF_AUTO_RXCLK_INV_INFO 0x4C000010, 0x00000104 + +#define REG_AUTO_LINK_TXCLK_ADJ_ADDR 0x4C000011 +#define BF_AUTO_TXCLK_ADJ_INFO 0x4C000011, 0x00000400 +#define BF_AUTO_TXCLK_INV_INFO 0x4C000011, 0x00000104 + +#define REG_HSCI_PAD_CTRL_ADDR 0x4C000012 +#define BF_HSCI_CTRL_RX_ONCHIP_TERM_INFO 0x4C000012, 0x00000100 +#define BF_HSCI_CTRL_RX_PD_INFO 0x4C000012, 0x00000101 +#define BF_HSCI_CTRL_TX_LVL_INFO 0x4C000012, 0x00000302 +#define BF_HSCI_CTRL_TX_PD_INFO 0x4C000012, 0x00000105 +#define BF_HSCI_CTRL_FRNT_END_TX_CK_INV_INFO 0x4C000012, 0x00000106 + +#define REG_HSCI_AFE_CTRL_ADDR 0x4C000013 +#define BF_HSCI_TERM_TRIM_INFO 0x4C000013, 0x00000300 +#define BF_HSCI_AC_COUP_ON_INFO 0x4C000013, 0x00000103 +#define BF_HSCI_MB_R_TRIM_INFO 0x4C000013, 0x00000304 +#define BF_HSCI_PD_MB_INFO 0x4C000013, 0x00000107 + +#define REG_HSCI_DFX_CTRL_ADDR 0x4C000014 +#define BF_HSCI_RX_TEST_MODE_INFO 0x4C000014, 0x00000100 +#define BF_HSCI_TX_TEST_MODE_INFO 0x4C000014, 0x00000101 +#define BF_HSCI_TSTMODE_EN_INFO 0x4C000014, 0x00000102 +#define BF_HSCI_CLKTST_OUT_INFO 0x4C000014, 0x00000103 +#define BF_HSCI_DATATST_OUT_INFO 0x4C000014, 0x00000104 +#define BF_HSCI_CLKTST_IN_INFO 0x4C000014, 0x00000105 +#define BF_HSCI_DATATST_IN_INFO 0x4C000014, 0x00000106 +#define BF_HSCI_RX_TEST_LFSR_ACQ_INFO 0x4C000014, 0x00000107 + +#define REG_HSCI_RX_BER_ADDR 0x4C000015 +#define BF_HSCI_RX_BER_CNT_INFO 0x4C000015, 0x00002000 + +#define REG_HSCI_RX_BER2_ADDR 0x4C000016 + +#define REG_HSCI_RX_BER3_ADDR 0x4C000017 + +#define REG_HSCI_RX_BER4_ADDR 0x4C000018 + +#endif /* __ADI_APOLLO_BF_HSCI_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_interrupt_aggregator.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_interrupt_aggregator.h new file mode 100644 index 00000000000000..33e0fab6d48b56 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_interrupt_aggregator.h @@ -0,0 +1,23 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:17 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_INTERRUPT_AGGREGATOR_H__ +#define __ADI_APOLLO_BF_INTERRUPT_AGGREGATOR_H__ + +/*============= D E F I N E S ==============*/ +#define REG_INTERRUPT_MASK_ADDR(n) (0x41200000 + 4 * (n)) +#define BF_MASK_INFO(n) (0x41200000 + 4 * (n)), 0x00000800 + +#endif /* __ADI_APOLLO_BF_INTERRUPT_AGGREGATOR_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_interrupt_transmuter.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_interrupt_transmuter.h new file mode 100644 index 00000000000000..f75296476c0ba1 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_interrupt_transmuter.h @@ -0,0 +1,47 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:17 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_INTERRUPT_TRANSMUTER_H__ +#define __ADI_APOLLO_BF_INTERRUPT_TRANSMUTER_H__ + +/*============= D E F I N E S ==============*/ +#define REG_INTERRUPT_ENABLE_ADDR(n) (0x46800000 + 4 * (n)) +#define BF_INTERRUPT_ENABLE_INFO(n) (0x46800000 + 4 * (n)), 0x00002000 + +#define REG_LEVEL_EDGEB_ADDR(n) (0x46800044 + 4 * (n)) +#define BF_LEVEL_EDGEB_INFO(n) (0x46800044 + 4 * (n)), 0x00002000 + +#define REG_POS_MASK_ADDR(n) (0x46800088 + 4 * (n)) +#define BF_INT_POS_MASK_INFO(n) (0x46800088 + 4 * (n)), 0x00002000 + +#define REG_NEG_MASK_ADDR(n) (0x468000CC + 4 * (n)) +#define BF_INT_NEG_MASK_INFO(n) (0x468000CC + 4 * (n)), 0x00002000 + +#define REG_TRIGGER_ADDR(n) (0x46800110 + 4 * (n)) +#define BF_TRIGGER_INFO(n) (0x46800110 + 4 * (n)), 0x00002000 + +#define REG_STATUS_INTERRUPT_TRANSMUTER_ADDR(n) (0x46800154 + 4 * (n)) +#define BF_INT_STATUS_INFO(n) (0x46800154 + 4 * (n)), 0x00002000 + +#define REG_RAW_STATUS_ADDR(n) (0x46800198 + 4 * (n)) +#define BF_RAW_STATUS_INFO(n) (0x46800198 + 4 * (n)), 0x00002000 + +#define REG_EDGE_STATUS_ADDR(n) (0x468001DC + 4 * (n)) +#define BF_EDGE_STATUS_INFO(n) (0x468001DC + 4 * (n)), 0x00002000 + +#define REG_MASTER_ID_READ_ADDR 0x46800220 +#define BF_MASTER_ID_INFO 0x46800220, 0x00002000 + +#endif /* __ADI_APOLLO_BF_INTERRUPT_TRANSMUTER_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_itm.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_itm.h new file mode 100644 index 00000000000000..c20b1b6b8351b4 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_itm.h @@ -0,0 +1,41 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:17 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_ITM_H__ +#define __ADI_APOLLO_BF_ITM_H__ + +/*============= D E F I N E S ==============*/ +#define REG_PKTZR_STIM_ADDR(n) (0x46300000 + 4 * (n)) +#define BF_PKTZR_FIFOREADY_INFO(n) (0x46300000 + 4 * (n)), 0x00000100 + +#define REG_PKTZR_TER_ADDR 0x46300E00 +#define BF_PKTZR_TEN_INFO 0x46300E00, 0x00002000 + +#define REG_PKTZR_TCSR_ADDR 0x46300E80 +#define BF_PKTZR_ENABLE_INFO 0x46300E80, 0x00000100 +#define BF_PKTZR_SYNC_EN_INFO 0x46300E80, 0x00000102 +#define BF_PKTZR_TRACE_BUSID_INFO 0x46300E80, 0x00000710 +#define BF_PKTZR_BUSY_INFO 0x46300E80, 0x00000117 + +#define REG_PKTZR_SYNC_CTRL_ADDR 0x46300E90 +#define BF_PKTZR_SYNC_COUNT_INFO 0x46300E90, 0x00001400 + +#define REG_PKTZR_INTR_CTRL_ADDR 0x46300EA0 +#define BF_PKTZR_OVFL_INTEN_INFO 0x46300EA0, 0x00000100 + +#define REG_PKTZR_INTR_STAT_ADDR 0x46300EA4 +#define BF_PKTZR_OVFL_INTSTAT_INFO 0x46300EA4, 0x00000100 + +#endif /* __ADI_APOLLO_BF_ITM_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_jrx_core.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_jrx_core.h new file mode 100644 index 00000000000000..f49399a7dbec65 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_jrx_core.h @@ -0,0 +1,123 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:21 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_JRX_CORE_H__ +#define __ADI_APOLLO_BF_JRX_CORE_H__ + +/*============= D E F I N E S ==============*/ +#define JRX_CORE_JRX_TX_DIGITAL0 0x61604000 +#define JRX_CORE_JRX_TX_DIGITAL1 0x61E04000 + +#ifdef USE_PRIVATE_BF +#define REG_JRX_CORE_CONFIG_ADDR(inst) ((inst) + 0x00000000) +#define BF_JRX_LINK_TYPE_INFO(inst) ((inst) + 0x00000000), 0x00000200 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_CORE_CONFIG0_ADDR(inst, n) ((inst) + 0x00000001 + 1 * (n)) +#define BF_JRX_CORE_CHKSUM_DISABLE_INFO(inst, n) ((inst) + 0x00000001 + 1 * (n)), 0x00000100 +#define BF_JRX_CORE_CHKSUM_LSB_ALG_INFO(inst, n) ((inst) + 0x00000001 + 1 * (n)), 0x00000101 +#define BF_JRX_CORE_CLEAR_SYNC_NE_COUNT_INFO(inst, n) ((inst) + 0x00000001 + 1 * (n)), 0x00000102 +#define BF_JRX_CORE_PCLK_ERROR_CLEAR_INFO(inst, n) ((inst) + 0x00000001 + 1 * (n)), 0x00000103 +#define BF_JRX_CORE_SYSREF_FOR_RELINK_INFO(inst, n) ((inst) + 0x00000001 + 1 * (n)), 0x00000104 +#define BF_JRX_CORE_SYSREF_FOR_STARTUP_INFO(inst, n) ((inst) + 0x00000001 + 1 * (n)), 0x00000105 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_CORE_SAMPLE_XBAR_A_ADDR(inst, n) ((inst) + 0x00000010 + 1 * (n)) +#define BF_JRX_CORE_CONV_SEL_LINK0_INFO(inst, n) ((inst) + 0x00000010 + 1 * (n)), 0x00000700 +#define BF_JRX_CORE_CONV_DISABLE_LINK0_INFO(inst, n) ((inst) + 0x00000010 + 1 * (n)), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_CORE_SAMPLE_XBAR_B_ADDR(inst, n) ((inst) + 0x00000090 + 1 * (n)) +#define BF_JRX_CORE_CONV_SEL_LINK1_INFO(inst, n) ((inst) + 0x00000090 + 1 * (n)), 0x00000700 +#define BF_JRX_CORE_CONV_DISABLE_LINK1_INFO(inst, n) ((inst) + 0x00000090 + 1 * (n)), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_CORE_SYNC_N_SEL_ADDR(inst, n) ((inst) + 0x00000110 + 1 * (n)) +#define BF_JRX_CORE_SYNC_N_SEL_INFO(inst, n) ((inst) + 0x00000110 + 1 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_CORE_SYNC_NE_COUNT_ADDR(inst, n) ((inst) + 0x00000112 + 1 * (n)) +#define BF_JRX_CORE_SYNC_NE_COUNT_INFO(inst, n) ((inst) + 0x00000112 + 1 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_CORE_BUF_DEPTH_ADDR(inst, n) ((inst) + 0x00000114 + 1 * (n)) +#define BF_JRX_CORE_BUF_DEPTH_INFO(inst, n) ((inst) + 0x00000114 + 1 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_CORE_PHASE_ADJUST0_ADDR(inst, n) ((inst) + 0x00000116 + 1 * (n)) +#define BF_JRX_CORE_PHASE_ADJUST_INFO(inst, n) ((inst) + 0x00000116 + 1 * (n)), 0x00001000 +#endif /* USE_PRIVATE_BF */ + +#define REG_JRX_CORE_PHASE_ADJUST1_ADDR(inst, n) ((inst) + 0x00000118 + 1 * (n)) + +#ifdef USE_PRIVATE_BF +#define REG_JRX_CORE_LANE_PHASE_DIFF_0_ADDR(inst, n) ((inst) + 0x0000011B + 1 * (n)) +#define BF_JRX_CORE_PHASE_DIFF_INFO(inst, n) ((inst) + 0x0000011B + 1 * (n)), 0x00001000 +#endif /* USE_PRIVATE_BF */ + +#define REG_JRX_CORE_LANE_PHASE_DIFF_1_ADDR(inst, n) ((inst) + 0x0000013C + 1 * (n)) + +#ifdef USE_PRIVATE_BF +#define REG_JRX_TPL_CONFIG0_ADDR(inst, n) ((inst) + 0x0000015C + 1 * (n)) +#define BF_JRX_CORE_CFG_INVALID_INFO(inst, n) ((inst) + 0x0000015C + 1 * (n)), 0x00000100 +#define BF_JRX_CORE_USR_DATA_RDY_INFO(inst, n) ((inst) + 0x0000015C + 1 * (n)), 0x00000101 +#define BF_JRX_CORE_SYSREF_RCVD_INFO(inst, n) ((inst) + 0x0000015C + 1 * (n)), 0x00000102 +#define BF_JRX_CORE_SYSREF_N_SHOT_ENABLE_INFO(inst, n) ((inst) + 0x0000015C + 1 * (n)), 0x00000103 +#define BF_JRX_CORE_SYSREF_N_SHOT_COUNT_INFO(inst, n) ((inst) + 0x0000015C + 1 * (n)), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_TPL_CONFIG1_ADDR(inst, n) ((inst) + 0x0000015E + 1 * (n)) +#define BF_JRX_CORE_SYSREF_PHASE_ERR_INFO(inst, n) ((inst) + 0x0000015E + 1 * (n)), 0x00000100 +#define BF_JRX_CORE_SYSREF_CLR_PHASE_ERR_INFO(inst, n) ((inst) + 0x0000015E + 1 * (n)), 0x00000101 +#define BF_JRX_CORE_SYSREF_IGNORE_WHEN_LINKED_INFO(inst, n) ((inst) + 0x0000015E + 1 * (n)), 0x00000102 +#define BF_JRX_CORE_SYSREF_ENABLE_INFO(inst, n) ((inst) + 0x0000015E + 1 * (n)), 0x00000103 +#define BF_JRX_CORE_SYNC_FORMAT_EN_INFO(inst, n) ((inst) + 0x0000015E + 1 * (n)), 0x00000104 +#define BF_JRX_CORE_BUF_ERROR_INFO(inst, n) ((inst) + 0x0000015E + 1 * (n)), 0x00000106 +#define BF_JRX_TPL_BUF_ERROR_INFO(inst, n) ((inst) + 0x0000015E + 1 * (n)), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_TPL_LANE_BUF_DEPTH_A_ADDR(inst, n) ((inst) + 0x00000160 + 1 * (n)) +#define BF_JRX_TPL_BUF_DEPTH_LINK0_INFO(inst, n) ((inst) + 0x00000160 + 1 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_TPL_LANE_BUF_DEPTH_B_ADDR(inst, n) ((inst) + 0x00000170 + 1 * (n)) +#define BF_JRX_TPL_BUF_DEPTH_LINK1_INFO(inst, n) ((inst) + 0x00000170 + 1 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_CORE_LANE_XBAR_A_ADDR(inst, n) ((inst) + 0x00000180 + 1 * (n)) +#define BF_JRX_CORE_LANE_SEL_LINK0_INFO(inst, n) ((inst) + 0x00000180 + 1 * (n)), 0x00000500 +#define BF_JRX_CORE_PCLK_SLOW_ERROR_LINK0_INFO(inst, n) ((inst) + 0x00000180 + 1 * (n)), 0x00000106 +#define BF_JRX_CORE_PCLK_FAST_ERROR_LINK0_INFO(inst, n) ((inst) + 0x00000180 + 1 * (n)), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_CORE_LANE_XBAR_B_ADDR(inst, n) ((inst) + 0x00000190 + 1 * (n)) +#define BF_JRX_CORE_LANE_SEL_LINK1_INFO(inst, n) ((inst) + 0x00000190 + 1 * (n)), 0x00000500 +#define BF_JRX_CORE_PCLK_SLOW_ERROR_LINK1_INFO(inst, n) ((inst) + 0x00000190 + 1 * (n)), 0x00000106 +#define BF_JRX_CORE_PCLK_FAST_ERROR_LINK1_INFO(inst, n) ((inst) + 0x00000190 + 1 * (n)), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#endif /* __ADI_APOLLO_BF_JRX_CORE_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_jrx_dac_sample_prbs.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_jrx_dac_sample_prbs.h new file mode 100644 index 00000000000000..122909b66805db --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_jrx_dac_sample_prbs.h @@ -0,0 +1,62 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:21 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_JRX_DAC_SAMPLE_PRBS_H__ +#define __ADI_APOLLO_BF_JRX_DAC_SAMPLE_PRBS_H__ + +/*============= D E F I N E S ==============*/ +#define JRX_DAC_SAMPLE_PRBS_JRX_TX_DIGITAL0 0x61620000 +#define JRX_DAC_SAMPLE_PRBS_JRX_TX_DIGITAL1 0x61E20000 + +#define REG_SAMPLE_PRBS_CTRL0_ADDR(inst) ((inst) + 0x00000000) +#define BF_PRBS_MODE_INFO(inst) ((inst) + 0x00000000), 0x00000300 +#define BF_SWAP_ENDIANNESS_INFO(inst) ((inst) + 0x00000000), 0x00000103 +#define BF_PRBS_INV_REAL_INFO(inst) ((inst) + 0x00000000), 0x00000104 +#define BF_PRBS_INV_IMAG_INFO(inst) ((inst) + 0x00000000), 0x00000105 +#define BF_CLR_ERRORS_INFO(inst) ((inst) + 0x00000000), 0x00000106 +#define BF_SAMPLE_PRBS_ENABLE_INFO(inst) ((inst) + 0x00000000), 0x00000107 + +#define REG_SAMPLE_PRBS_CTRL1_ADDR(inst) ((inst) + 0x00000001) +#define BF_UPDATE_ERROR_COUNT_INFO(inst) ((inst) + 0x00000001), 0x00000100 +#define BF_PRBS_ERR_RD_MODE_INFO(inst) ((inst) + 0x00000001), 0x00000101 +#define BF_PRBS_ERR_RD_CHNL_CLR_INFO(inst) ((inst) + 0x00000001), 0x00000102 +#define BF_PRBS_CHNL_SEL_INFO(inst) ((inst) + 0x00000001), 0x00000303 + +#define REG_SAMPLE_PRBS_STATUS0_ADDR(inst) ((inst) + 0x00000002) +#define BF_PRBS_INVALID_DATA_FLAG_I_INFO(inst) ((inst) + 0x00000002), 0x00000100 +#define BF_PRBS_INVALID_DATA_FLAG_Q_INFO(inst) ((inst) + 0x00000002), 0x00000101 +#define BF_PRBS_ERROR_FLAG_I_INFO(inst) ((inst) + 0x00000002), 0x00000102 +#define BF_PRBS_ERROR_FLAG_Q_INFO(inst) ((inst) + 0x00000002), 0x00000103 +#define BF_PRBS_INV_FLAG_REAL_INFO(inst) ((inst) + 0x00000002), 0x00000104 +#define BF_PRBS_INV_FLAG_IMAG_INFO(inst) ((inst) + 0x00000002), 0x00000105 + +#define REG_SAMPLE_PRBS_STATUS1_ADDR(inst) ((inst) + 0x00000003) +#define BF_ERROR_COUNT_I_INFO(inst) ((inst) + 0x00000003), 0x00001800 + +#define REG_SAMPLE_PRBS_STATUS2_ADDR(inst) ((inst) + 0x00000004) + +#define REG_SAMPLE_PRBS_STATUS3_ADDR(inst) ((inst) + 0x00000005) + +#define REG_SAMPLE_PRBS_STATUS4_ADDR(inst) ((inst) + 0x00000006) +#define BF_ERROR_COUNT_Q_INFO(inst) ((inst) + 0x00000006), 0x00001800 + +#define REG_SAMPLE_PRBS_STATUS5_ADDR(inst) ((inst) + 0x00000007) + +#define REG_SAMPLE_PRBS_STATUS6_ADDR(inst) ((inst) + 0x00000008) + +#define REG_SAMPLE_PRBS_DEBUG_ADDR(inst) ((inst) + 0x00000009) +#define BF_PRBS_ERR_RD_CHNL_READBACK_INFO(inst) ((inst) + 0x00000009), 0x00000300 + +#endif /* __ADI_APOLLO_BF_JRX_DAC_SAMPLE_PRBS_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_jrx_dl_204b.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_jrx_dl_204b.h new file mode 100644 index 00000000000000..5c097ba23905e1 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_jrx_dl_204b.h @@ -0,0 +1,203 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:21 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_JRX_DL_204B_H__ +#define __ADI_APOLLO_BF_JRX_DL_204B_H__ + +/*============= D E F I N E S ==============*/ +#define JRX_DL_204B_JRX_TX_DIGITAL0 0x6160C000 +#define JRX_DL_204B_JRX_TX_DIGITAL1 0x61E0C000 + +#ifdef USE_PRIVATE_BF +#define REG_JRX_DL_204B_CONFIG0_ADDR(inst) ((inst) + 0x00000380) +#define BF_JRX_DL_204B_AR_ECNTR_INFO(inst) ((inst) + 0x00000380), 0x00000100 +#define BF_JRX_DL_204B_CGS_SEL_INFO(inst) ((inst) + 0x00000380), 0x00000101 +#define BF_JRX_DL_204B_CHAR_REPL_DIS_INFO(inst) ((inst) + 0x00000380), 0x00000102 +#define BF_JRX_DL_204B_ENA_RAMP_CHECK_INFO(inst) ((inst) + 0x00000380), 0x00000103 +#define BF_JRX_DL_204B_FCHK_N_INFO(inst) ((inst) + 0x00000380), 0x00000104 +#define BF_JRX_DL_204B_FORCESYNCREQ_INFO(inst) ((inst) + 0x00000380), 0x00000105 +#define BF_JRX_DL_204B_ILS_MODE_INFO(inst) ((inst) + 0x00000380), 0x00000106 +#define BF_JRX_DL_204B_QUAL_RDERR_INFO(inst) ((inst) + 0x00000380), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_DL_204B_CONFIG1_ADDR(inst) ((inst) + 0x00000381) +#define BF_JRX_DL_204B_REPDATATEST_INFO(inst) ((inst) + 0x00000381), 0x00000100 +#define BF_JRX_DL_204B_SYNC_ASSERT_MASK_INFO(inst) ((inst) + 0x00000381), 0x00000301 +#define BF_JRX_DL_204B_SYNC_ERR_ENABLE_INFO(inst) ((inst) + 0x00000381), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_DL_204B_IRQ_CLR0_ADDR(inst) ((inst) + 0x00000382) +#define BF_JRX_DL_204B_IRQ_CLR_INFO(inst) ((inst) + 0x00000382), 0x00000900 +#endif /* USE_PRIVATE_BF */ + +#define REG_JRX_DL_204B_IRQ_CLR1_ADDR(inst) ((inst) + 0x00000383) + +#ifdef USE_PRIVATE_BF +#define REG_JRX_DL_204B_ETH_ADDR(inst) ((inst) + 0x00000384) +#define BF_JRX_DL_204B_ETH_INFO(inst) ((inst) + 0x00000384), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_DL_204B_KSYNC_ADDR(inst) ((inst) + 0x00000386) +#define BF_JRX_DL_204B_KSYNC_INFO(inst) ((inst) + 0x00000386), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_DL_204B_LANE_RXCFG_00_ADDR(inst, n) ((inst) + 0x00000390 + 1 * (n)) +#define BF_JRX_DL_204B_L0_RXCFG_0_INFO(inst, n) ((inst) + 0x00000390 + 1 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_DL_204B_LANE_RXCFG_01_ADDR(inst, n) ((inst) + 0x000003A0 + 1 * (n)) +#define BF_JRX_DL_204B_L0_RXCFG_1_INFO(inst, n) ((inst) + 0x000003A0 + 1 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_DL_204B_LANE_RXCFG_02_ADDR(inst, n) ((inst) + 0x000003B0 + 1 * (n)) +#define BF_JRX_DL_204B_L0_RXCFG_2_INFO(inst, n) ((inst) + 0x000003B0 + 1 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_DL_204B_LANE_RXCFG_03_ADDR(inst, n) ((inst) + 0x000003C0 + 1 * (n)) +#define BF_JRX_DL_204B_L0_RXCFG_3_INFO(inst, n) ((inst) + 0x000003C0 + 1 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_DL_204B_LANE_RXCFG_04_ADDR(inst, n) ((inst) + 0x000003D0 + 1 * (n)) +#define BF_JRX_DL_204B_L0_RXCFG_4_INFO(inst, n) ((inst) + 0x000003D0 + 1 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_DL_204B_LANE_RXCFG_05_ADDR(inst, n) ((inst) + 0x000003E0 + 1 * (n)) +#define BF_JRX_DL_204B_L0_RXCFG_5_INFO(inst, n) ((inst) + 0x000003E0 + 1 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_DL_204B_LANE_RXCFG_06_ADDR(inst, n) ((inst) + 0x000003F0 + 1 * (n)) +#define BF_JRX_DL_204B_L0_RXCFG_6_INFO(inst, n) ((inst) + 0x000003F0 + 1 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_DL_204B_LANE_RXCFG_07_ADDR(inst, n) ((inst) + 0x00000400 + 1 * (n)) +#define BF_JRX_DL_204B_L0_RXCFG_7_INFO(inst, n) ((inst) + 0x00000400 + 1 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_DL_204B_LANE_RXCFG_08_ADDR(inst, n) ((inst) + 0x00000410 + 1 * (n)) +#define BF_JRX_DL_204B_L0_RXCFG_8_INFO(inst, n) ((inst) + 0x00000410 + 1 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_DL_204B_LANE_RXCFG_09_ADDR(inst, n) ((inst) + 0x00000420 + 1 * (n)) +#define BF_JRX_DL_204B_L0_RXCFG_9_INFO(inst, n) ((inst) + 0x00000420 + 1 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_DL_204B_LANE_RXCFG_10_ADDR(inst, n) ((inst) + 0x00000430 + 1 * (n)) +#define BF_JRX_DL_204B_L0_RXCFG_10_INFO(inst, n) ((inst) + 0x00000430 + 1 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_DL_204B_LANE_RXCFG_11_ADDR(inst, n) ((inst) + 0x00000440 + 1 * (n)) +#define BF_JRX_DL_204B_L0_RXCFG_11_INFO(inst, n) ((inst) + 0x00000440 + 1 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_DL_204B_LANE_RXCFG_12_ADDR(inst, n) ((inst) + 0x00000450 + 1 * (n)) +#define BF_JRX_DL_204B_L0_RXCFG_12_INFO(inst, n) ((inst) + 0x00000450 + 1 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_DL_204B_LANE_RXCFG_13_ADDR(inst, n) ((inst) + 0x00000460 + 1 * (n)) +#define BF_JRX_DL_204B_L0_RXCFG_13_INFO(inst, n) ((inst) + 0x00000460 + 1 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_DL_204B_LANE_ECNT0_ADDR(inst, n) ((inst) + 0x00000470 + 1 * (n)) +#define BF_JRX_DL_204B_ECNT_ENA_INFO(inst, n) ((inst) + 0x00000470 + 1 * (n)), 0x00000300 +#define BF_JRX_DL_204B_ECNT_RST_INFO(inst, n) ((inst) + 0x00000470 + 1 * (n)), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_DL_204B_LANE_ECNT1_ADDR(inst, n) ((inst) + 0x00000480 + 1 * (n)) +#define BF_JRX_DL_204B_ECNT_TCH_INFO(inst, n) ((inst) + 0x00000480 + 1 * (n)), 0x00000300 +#define BF_JRX_DL_204B_ECNT_TCR_INFO(inst, n) ((inst) + 0x00000480 + 1 * (n)), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_DL_204B_LANE_ERR_STATUS_ADDR(inst, n) ((inst) + 0x00000490 + 1 * (n)) +#define BF_JRX_DL_204B_BDE_INFO(inst, n) ((inst) + 0x00000490 + 1 * (n)), 0x00000100 +#define BF_JRX_DL_204B_CGS_INFO(inst, n) ((inst) + 0x00000490 + 1 * (n)), 0x00000101 +#define BF_JRX_DL_204B_CKS_INFO(inst, n) ((inst) + 0x00000490 + 1 * (n)), 0x00000102 +#define BF_JRX_DL_204B_FS_INFO(inst, n) ((inst) + 0x00000490 + 1 * (n)), 0x00000103 +#define BF_JRX_DL_204B_ILD_INFO(inst, n) ((inst) + 0x00000490 + 1 * (n)), 0x00000104 +#define BF_JRX_DL_204B_ILS_INFO(inst, n) ((inst) + 0x00000490 + 1 * (n)), 0x00000105 +#define BF_JRX_DL_204B_NIT_INFO(inst, n) ((inst) + 0x00000490 + 1 * (n)), 0x00000106 +#define BF_JRX_DL_204B_UEK_INFO(inst, n) ((inst) + 0x00000490 + 1 * (n)), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_DL_204B_LANE_BD_ADDR(inst, n) ((inst) + 0x000004A0 + 1 * (n)) +#define BF_JRX_DL_204B_BD_CNT_INFO(inst, n) ((inst) + 0x000004A0 + 1 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_DL_204B_LANE_UEK_ADDR(inst, n) ((inst) + 0x000004B0 + 1 * (n)) +#define BF_JRX_DL_204B_UEK_CNT_INFO(inst, n) ((inst) + 0x000004B0 + 1 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_DL_204B_LANE_NIT_ADDR(inst, n) ((inst) + 0x000004C0 + 1 * (n)) +#define BF_JRX_DL_204B_NIT_CNT_INFO(inst, n) ((inst) + 0x000004C0 + 1 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_DL_204B_LANE_FCHK_ADDR(inst, n) ((inst) + 0x000004D0 + 1 * (n)) +#define BF_JRX_DL_204B_LL_FCHK_INFO(inst, n) ((inst) + 0x000004D0 + 1 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_DL_204B_LANE_FCMP_ADDR(inst, n) ((inst) + 0x000004E0 + 1 * (n)) +#define BF_JRX_DL_204B_LL_FCMP_INFO(inst, n) ((inst) + 0x000004E0 + 1 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_DL_204B_LANE_LID_ADDR(inst, n) ((inst) + 0x000004F0 + 1 * (n)) +#define BF_JRX_DL_204B_LL_LID_INFO(inst, n) ((inst) + 0x000004F0 + 1 * (n)), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_DL_204B_LANE_STATUS_ADDR(inst, n) ((inst) + 0x00000500 + 1 * (n)) +#define BF_JRX_DL_204B_EOF_EVENT_INFO(inst, n) ((inst) + 0x00000500 + 1 * (n)), 0x00000100 +#define BF_JRX_DL_204B_EOMF_EVENT_INFO(inst, n) ((inst) + 0x00000500 + 1 * (n)), 0x00000101 +#define BF_JRX_DL_204B_FS_LOST_INFO(inst, n) ((inst) + 0x00000500 + 1 * (n)), 0x00000102 +#define BF_JRX_DL_204B_SYNC_N_INFO(inst, n) ((inst) + 0x00000500 + 1 * (n)), 0x00000103 +#define BF_JRX_DL_204B_USER_DATA_INFO(inst, n) ((inst) + 0x00000500 + 1 * (n)), 0x00000104 +#define BF_JRX_DL_204B_VALID_CKSUM_INFO(inst, n) ((inst) + 0x00000500 + 1 * (n)), 0x00000105 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_DL_204B_LANE_IRQ_VEC0_ADDR(inst, n) ((inst) + 0x00000510 + 1 * (n)) +#define BF_JRX_DL_204B_IRQ_VEC_INFO(inst, n) ((inst) + 0x00000510 + 1 * (n)), 0x00000900 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_DL_204B_LANE_IRQ_VEC1_ADDR(inst, n) ((inst) + 0x00000520 + 1 * (n)) +#define BF_JRX_DL_204B_IRQ_INFO(inst, n) ((inst) + 0x00000520 + 1 * (n)), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#endif /* __ADI_APOLLO_BF_JRX_DL_204B_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_jrx_dl_204c.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_jrx_dl_204c.h new file mode 100644 index 00000000000000..1ab0a2e2a4fdb2 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_jrx_dl_204c.h @@ -0,0 +1,98 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:21 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_JRX_DL_204C_H__ +#define __ADI_APOLLO_BF_JRX_DL_204C_H__ + +/*============= D E F I N E S ==============*/ +#define JRX_DL_204C_JRX_TX_DIGITAL0 0x61610000 +#define JRX_DL_204C_JRX_TX_DIGITAL1 0x61E10000 + +#define REG_JRX_DL_204C_CONFIG_ADDR(inst) ((inst) + 0x00000000) +#ifdef USE_PRIVATE_BF +#define BF_JRX_DL_204C_CRC_FEC_REVERSE_CFG_INFO(inst) ((inst) + 0x00000000), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#ifdef USE_PRIVATE_BF +#define BF_JRX_DL_204C_LINK_LOCK_INFO(inst) ((inst) + 0x00000000), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#ifdef USE_PRIVATE_BF +#define BF_JRX_DL_204C_CLR_ERR_CNT_INFO(inst) ((inst) + 0x00000000), 0x00000103 +#endif /* USE_PRIVATE_BF */ +#ifdef USE_PRIVATE_BF +#define BF_JRX_DL_204C_HOLD_ERR_CNT_INFO(inst) ((inst) + 0x00000000), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_JRX_DL_204C_SYNC_WORD_SEL_INFO(inst) ((inst) + 0x00000000), 0x00000206 + +#ifdef USE_PRIVATE_BF +#define REG_JRX_DL_204C_MB_ADDR(inst) ((inst) + 0x00000001) +#define BF_JRX_DL_204C_MB_ERR_CFG_INFO(inst) ((inst) + 0x00000001), 0x00000400 +#define BF_JRX_DL_204C_MB_REQD_CFG_INFO(inst) ((inst) + 0x00000001), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_DL_204C_SH_ERR_ADDR(inst) ((inst) + 0x00000002) +#define BF_JRX_DL_204C_SH_ERR_CFG_INFO(inst) ((inst) + 0x00000002), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_DL_204C_SH_REQD_ADDR(inst) ((inst) + 0x00000003) +#define BF_JRX_DL_204C_SH_REQD_CFG_INFO(inst) ((inst) + 0x00000003), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_DL_204C_EMB_ADDR(inst) ((inst) + 0x00000005) +#define BF_JRX_DL_204C_EMB_ERR_CFG_INFO(inst) ((inst) + 0x00000005), 0x00000300 +#define BF_JRX_DL_204C_EMB_REQD_CFG_INFO(inst) ((inst) + 0x00000005), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_DL_204C_LANE_SKEW0_ADDR(inst, n) ((inst) + 0x00000010 + 1 * (n)) +#define BF_JRX_DL_204C_LANE_SKEW_INFO(inst, n) ((inst) + 0x00000010 + 1 * (n)), 0x00000900 +#endif /* USE_PRIVATE_BF */ + +#define REG_JRX_DL_204C_LANE_SKEW1_ADDR(inst, n) ((inst) + 0x00000020 + 1 * (n)) + +#ifdef USE_PRIVATE_BF +#define REG_JRX_DL_204C_LANE_STATUS_ADDR(inst, n) ((inst) + 0x00000030 + 1 * (n)) +#define BF_JRX_DL_204C_STATE_INFO(inst, n) ((inst) + 0x00000030 + 1 * (n)), 0x00000300 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_DL_204C_LANE_SH_ERR_ADDR(inst, n) ((inst) + 0x00000040 + 1 * (n)) +#define BF_JRX_DL_204C_SH_ERR_CNT_INFO(inst, n) ((inst) + 0x00000040 + 1 * (n)), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_DL_204C_LANE_FEC_ERR_ADDR(inst, n) ((inst) + 0x00000050 + 1 * (n)) +#define BF_JRX_DL_204C_FEC_ERR_CNT_INFO(inst, n) ((inst) + 0x00000050 + 1 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_DL_204C_LANE_FEC_UNC_ERR_ADDR(inst, n) ((inst) + 0x00000060 + 1 * (n)) +#define BF_JRX_DL_204C_FEC_UNCORRECTABLE_ERR_CNT_INFO(inst, n) ((inst) + 0x00000060 + 1 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_DL_204C_LANE_CRC_ERR_ADDR(inst, n) ((inst) + 0x00000070 + 1 * (n)) +#define BF_JRX_DL_204C_CRC_ERR_CNT_INFO(inst, n) ((inst) + 0x00000070 + 1 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_DL_204C_LANE_BLOCK_ERR_ADDR(inst, n) ((inst) + 0x00000080 + 1 * (n)) +#define BF_JRX_DL_204C_MB_ERR_CNT_INFO(inst, n) ((inst) + 0x00000080 + 1 * (n)), 0x00000400 +#define BF_JRX_DL_204C_EMB_ERR_CNT_INFO(inst, n) ((inst) + 0x00000080 + 1 * (n)), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#endif /* __ADI_APOLLO_BF_JRX_DL_204C_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_jrx_jesd_l0.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_jrx_jesd_l0.h new file mode 100644 index 00000000000000..7584b897be90da --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_jrx_jesd_l0.h @@ -0,0 +1,108 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:21 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_JRX_JESD_L0_H__ +#define __ADI_APOLLO_BF_JRX_JESD_L0_H__ + +/*============= D E F I N E S ==============*/ +#define JRX_JESD_L0_JRX_TX_DIGITAL0 0x61608000 +#define JRX_JESD_L0_JRX_TX_DIGITAL1 0x61E08000 + +#ifdef USE_PRIVATE_BF +#define REG_JRX_L0_DID_ADDR(inst, n) ((inst) + 0x00000000 + 1 * (n)) +#define BF_JRX_CORE_DID_CFG_INFO(inst, n) ((inst) + 0x00000000 + 1 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_JRX_L0_RESERVED0_ADDR(inst, n) ((inst) + 0x00000002 + 1 * (n)) + +#ifdef USE_PRIVATE_BF +#define REG_JRX_L0_LID_ADDR(inst, n) ((inst) + 0x00000004 + 1 * (n)) +#define BF_JRX_CORE_LID_CFG_LINK0_INFO(inst, n) ((inst) + 0x00000004 + 1 * (n)), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_L0_LID_1_ADDR(inst, n) ((inst) + 0x00000014 + 1 * (n)) +#define BF_JRX_CORE_LID_CFG_LINK1_INFO(inst, n) ((inst) + 0x00000014 + 1 * (n)), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_L0_DSCR_L_ADDR(inst, n) ((inst) + 0x00000024 + 1 * (n)) +#define BF_JRX_CORE_L_CFG_INFO(inst, n) ((inst) + 0x00000024 + 1 * (n)), 0x00000500 +#define BF_JRX_CORE_DSCR_CFG_INFO(inst, n) ((inst) + 0x00000024 + 1 * (n)), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_L0_F_ADDR(inst, n) ((inst) + 0x00000026 + 1 * (n)) +#define BF_JRX_CORE_F_CFG_INFO(inst, n) ((inst) + 0x00000026 + 1 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_L0_K_ADDR(inst, n) ((inst) + 0x00000028 + 1 * (n)) +#define BF_JRX_CORE_K_CFG_INFO(inst, n) ((inst) + 0x00000028 + 1 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_L0_M_ADDR(inst, n) ((inst) + 0x0000002A + 1 * (n)) +#define BF_JRX_CORE_M_CFG_INFO(inst, n) ((inst) + 0x0000002A + 1 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_L0_CS_N_ADDR(inst, n) ((inst) + 0x0000002C + 1 * (n)) +#define BF_JRX_CORE_N_CFG_INFO(inst, n) ((inst) + 0x0000002C + 1 * (n)), 0x00000500 +#define BF_JRX_CORE_CS_CFG_INFO(inst, n) ((inst) + 0x0000002C + 1 * (n)), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_L0_SUBCLASSV_NP_ADDR(inst, n) ((inst) + 0x0000002E + 1 * (n)) +#define BF_JRX_CORE_NP_CFG_INFO(inst, n) ((inst) + 0x0000002E + 1 * (n)), 0x00000500 +#define BF_JRX_CORE_SUBCLASSV_CFG_INFO(inst, n) ((inst) + 0x0000002E + 1 * (n)), 0x00000305 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_L0_JESDV_S_ADDR(inst, n) ((inst) + 0x00000030 + 1 * (n)) +#define BF_JRX_CORE_S_CFG_INFO(inst, n) ((inst) + 0x00000030 + 1 * (n)), 0x00000500 +#define BF_JRX_CORE_JESDV_CFG_INFO(inst, n) ((inst) + 0x00000030 + 1 * (n)), 0x00000305 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_L0_HD_ADDR(inst, n) ((inst) + 0x00000032 + 1 * (n)) +#define BF_JRX_CORE_HD_CFG_INFO(inst, n) ((inst) + 0x00000032 + 1 * (n)), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#define REG_JRX_L0_RESERVED1_ADDR(inst, n) ((inst) + 0x00000034 + 1 * (n)) + +#define REG_JRX_L0_RESERVED2_ADDR(inst, n) ((inst) + 0x00000036 + 1 * (n)) + +#ifdef USE_PRIVATE_BF +#define REG_JRX_L0_CHKSUM_ADDR(inst, n) ((inst) + 0x00000040 + 1 * (n)) +#define BF_JRX_CORE_CHKSUM_CFG_LINK0_INFO(inst, n) ((inst) + 0x00000040 + 1 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_L0_CHKSUM_1_ADDR(inst, n) ((inst) + 0x00000050 + 1 * (n)) +#define BF_JRX_CORE_CHKSUM_CFG_LINK1_INFO(inst, n) ((inst) + 0x00000050 + 1 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_L0_NS_ADDR(inst, n) ((inst) + 0x00000060 + 1 * (n)) +#define BF_JRX_CORE_NS_CFG_INFO(inst, n) ((inst) + 0x00000060 + 1 * (n)), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_L0_E_ADDR(inst, n) ((inst) + 0x00000062 + 1 * (n)) +#define BF_JRX_CORE_E_CFG_INFO(inst, n) ((inst) + 0x00000062 + 1 * (n)), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#endif /* __ADI_APOLLO_BF_JRX_JESD_L0_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_jrx_phy_ifx.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_jrx_phy_ifx.h new file mode 100644 index 00000000000000..a4157cfd4720e3 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_jrx_phy_ifx.h @@ -0,0 +1,30 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:21 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_JRX_PHY_IFX_H__ +#define __ADI_APOLLO_BF_JRX_PHY_IFX_H__ + +/*============= D E F I N E S ==============*/ +#define JRX_PHY_IFX_JRX_TX_DIGITAL0 0x61614000 +#define JRX_PHY_IFX_JRX_TX_DIGITAL1 0x61E14000 + +#ifdef USE_PRIVATE_BF +#define REG_JRX_PHY_IFX_LANE_PHY_SPLIT_ADDR(inst, n) ((inst) + 0x00000000 + 1 * (n)) +#define BF_JRX_IFX_LOG2_SPLIT_INFO(inst, n) ((inst) + 0x00000000 + 1 * (n)), 0x00000200 +#define BF_JRX_IFX_LANE_SEL_INFO(inst, n) ((inst) + 0x00000000 + 1 * (n)), 0x00000502 +#define BF_JRX_IFX_LANE_INVERSE_INFO(inst, n) ((inst) + 0x00000000 + 1 * (n)), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#endif /* __ADI_APOLLO_BF_JRX_PHY_IFX_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_jrx_private.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_jrx_private.h new file mode 100644 index 00000000000000..c4d3a8d21271b7 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_jrx_private.h @@ -0,0 +1,34 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:21 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_JRX_PRIVATE_H__ +#define __ADI_APOLLO_BF_JRX_PRIVATE_H__ + +/*============= D E F I N E S ==============*/ +#define JRX_PRIVATE_JRX_TX_DIGITAL0 0x6161C000 +#define JRX_PRIVATE_JRX_TX_DIGITAL1 0x61E1C000 + +#ifdef USE_PRIVATE_BF +#define REG_JRX_CORE_0_CONTROL_ADDR(inst) ((inst) + 0x00000000) +#define BF_JRX_CONV_SEL_SPI_EN_INFO(inst) ((inst) + 0x00000000), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TXFE_LOOPBACK_MODE_ADDR(inst) ((inst) + 0x00000001) +#define BF_TXFE_LOOPBACK_MODES_INFO(inst) ((inst) + 0x00000001), 0x00000300 +#define BF_LP_SYNC_CONNECT_EN_INFO(inst) ((inst) + 0x00000001), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#endif /* __ADI_APOLLO_BF_JRX_PRIVATE_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_jrx_prngtop.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_jrx_prngtop.h new file mode 100644 index 00000000000000..7f03c725f63d95 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_jrx_prngtop.h @@ -0,0 +1,46 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:21 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_JRX_PRNGTOP_H__ +#define __ADI_APOLLO_BF_JRX_PRNGTOP_H__ + +/*============= D E F I N E S ==============*/ +#define JRX_PRNGTOP_JRX_TX_DIGITAL0 0x61624000 +#define JRX_PRNGTOP_JRX_TX_DIGITAL1 0x61E24000 + +#ifdef USE_PRIVATE_BF +#define REG_PRNGTOP_CTRL_ADDR(inst) ((inst) + 0x00000000) +#define BF_TX_GLOBAL_BIST_ENABLE_INFO(inst) ((inst) + 0x00000000), 0x00000100 +#define BF_TX_GLOBAL_BIST_MODE_INFO(inst) ((inst) + 0x00000000), 0x00000101 +#define BF_TX_GLOBAL_BIST_FLUSH_LEN_INFO(inst) ((inst) + 0x00000000), 0x00000202 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_PRNGTOP_STATUS_ADDR(inst) ((inst) + 0x00000001) +#define BF_TX_GLOBAL_BIST_CLR_INFO(inst) ((inst) + 0x00000001), 0x00000100 +#define BF_TX_GLOBAL_BIST_RUN_INFO(inst) ((inst) + 0x00000001), 0x00000101 +#define BF_TX_GLOBAL_BIST_DONE_INFO(inst) ((inst) + 0x00000001), 0x00000102 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_BIST_LENGTH_LSB_ADDR(inst) ((inst) + 0x00000002) +#define BF_TX_GLOBAL_BIST_LENGTH_INFO(inst) ((inst) + 0x00000002), 0x00001300 +#endif /* USE_PRIVATE_BF */ + +#define REG_BIST_LENGTH_MID_ADDR(inst) ((inst) + 0x00000003) + +#define REG_BIST_LENGTH_MSB_ADDR(inst) ((inst) + 0x00000004) + +#endif /* __ADI_APOLLO_BF_JRX_PRNGTOP_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_jrx_test.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_jrx_test.h new file mode 100644 index 00000000000000..fcbdc572f41756 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_jrx_test.h @@ -0,0 +1,72 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:21 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_JRX_TEST_H__ +#define __ADI_APOLLO_BF_JRX_TEST_H__ + +/*============= D E F I N E S ==============*/ +#define JRX_TEST_JRX_TX_DIGITAL0 0x61600000 +#define JRX_TEST_JRX_TX_DIGITAL1 0x61E00000 + +#ifdef USE_PRIVATE_BF +#define REG_JRX_TEST_CONFIG0_ADDR(inst) ((inst) + 0x00000000) +#define BF_JRX_TEST_LANE_CLEAR_ERRORS_INFO(inst) ((inst) + 0x00000000), 0x00000100 +#define BF_JRX_TEST_LANE_UPDATE_ERROR_COUNT_INFO(inst) ((inst) + 0x00000000), 0x00000101 +#define BF_JRX_TEST_PRBS_SWAP_ENDIANNESS_INFO(inst) ((inst) + 0x00000000), 0x00000103 +#define BF_JRX_TEST_SAMPLE_UPDATE_ERROR_COUNT_INFO(inst) ((inst) + 0x00000000), 0x00000104 +#define BF_JRX_TEST_SAMPLE_CLEAR_ERRORS_INFO(inst) ((inst) + 0x00000000), 0x00000105 +#define BF_JRX_TEST_SAMPLE_INVALID_DATA_FLAG_INFO(inst) ((inst) + 0x00000000), 0x00000106 +#define BF_JRX_TEST_SAMPLE_ERROR_FLAG_INFO(inst) ((inst) + 0x00000000), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_TEST_SAMPLE_ERROR_COUNT_ADDR(inst) ((inst) + 0x00000001) +#define BF_JRX_TEST_SAMPLE_ERROR_COUNT_INFO(inst) ((inst) + 0x00000001), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_TEST_CONFIG1_ADDR(inst) ((inst) + 0x00000002) +#define BF_JRX_TEST_MODE_INFO(inst) ((inst) + 0x00000002), 0x00000300 +#define BF_JRX_TEST_SOURCE_INFO(inst) ((inst) + 0x00000002), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_TEST_LANE_STATUS_ADDR(inst, n) ((inst) + 0x00000003 + 1 * (n)) +#define BF_JRX_TEST_LANE_INV_INFO(inst, n) ((inst) + 0x00000003 + 1 * (n)), 0x00000105 +#define BF_JRX_TEST_LANE_INVALID_DATA_FLAG_INFO(inst, n) ((inst) + 0x00000003 + 1 * (n)), 0x00000106 +#define BF_JRX_TEST_LANE_ERROR_FLAG_INFO(inst, n) ((inst) + 0x00000003 + 1 * (n)), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_TEST_LANE_ERROR_COUNT0_ADDR(inst, n) ((inst) + 0x00000013 + 1 * (n)) +#define BF_JRX_TEST_LANE_ERROR_COUNT_INFO(inst, n) ((inst) + 0x00000013 + 1 * (n)), 0x00001800 +#endif /* USE_PRIVATE_BF */ + +#define REG_JRX_TEST_LANE_ERROR_COUNT1_ADDR(inst, n) ((inst) + 0x00000023 + 1 * (n)) + +#define REG_JRX_TEST_LANE_ERROR_COUNT2_ADDR(inst, n) ((inst) + 0x00000033 + 1 * (n)) + +#ifdef USE_PRIVATE_BF +#define REG_JRX_TEST_USER_DATA0_ADDR(inst) ((inst) + 0x00000043) +#define BF_JRX_TEST_USER_DATA_INFO(inst) ((inst) + 0x00000043), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_JRX_TEST_USER_DATA1_ADDR(inst) ((inst) + 0x00000044) + +#define REG_JRX_TEST_USER_DATA2_ADDR(inst) ((inst) + 0x00000045) + +#define REG_JRX_TEST_USER_DATA3_ADDR(inst) ((inst) + 0x00000046) + +#endif /* __ADI_APOLLO_BF_JRX_TEST_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_jrx_wrapper.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_jrx_wrapper.h new file mode 100644 index 00000000000000..6b91b6951f8b4b --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_jrx_wrapper.h @@ -0,0 +1,235 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:21 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_JRX_WRAPPER_H__ +#define __ADI_APOLLO_BF_JRX_WRAPPER_H__ + +/*============= D E F I N E S ==============*/ +#define JRX_WRAPPER_JRX_TX_DIGITAL0 0x61618000 +#define JRX_WRAPPER_JRX_TX_DIGITAL1 0x61E18000 + +#define REG_GENERAL_JRX_CTRL_0_ADDR(inst) ((inst) + 0x00000000) +#define BF_LINK_EN_INFO(inst) ((inst) + 0x00000000), 0x00000200 +#define BF_LINK0_SYNCB_COMB_SEL_INFO(inst) ((inst) + 0x00000000), 0x00000204 +#define BF_LINK1_SYNCB_COMB_SEL_INFO(inst) ((inst) + 0x00000000), 0x00000206 + +#define REG_GENERAL_JRX_CTRL_1_ADDR(inst) ((inst) + 0x00000001) +#define BF_LINK_MODE_INFO(inst) ((inst) + 0x00000001), 0x00000200 +#define BF_LINK_SEPARATE_EN_INFO(inst) ((inst) + 0x00000001), 0x00000102 +#define BF_LINK0_SYNCB_COMB_EN_INFO(inst) ((inst) + 0x00000001), 0x00000103 +#define BF_LINK1_SYNCB_COMB_EN_INFO(inst) ((inst) + 0x00000001), 0x00000104 +#ifdef USE_PRIVATE_BF +#define BF_SINGLE_LINK_TM_INFO(inst) ((inst) + 0x00000001), 0x00000105 +#endif /* USE_PRIVATE_BF */ +#define BF_USE_JRXIP_SYNCB_INFO(inst) ((inst) + 0x00000001), 0x00000107 + +#define REG_SYNCB_GEN_0_ADDR(inst, n) ((inst) + 0x00000002 + 1 * (n)) +#define BF_EOF_MASK_INFO(inst, n) ((inst) + 0x00000002 + 1 * (n)), 0x00000100 +#define BF_EOMF_MASK_INFO(inst, n) ((inst) + 0x00000002 + 1 * (n)), 0x00000102 + +#ifdef USE_PRIVATE_BF +#define REG_SYNCB_GEN_1_ADDR(inst, n) ((inst) + 0x00000004 + 1 * (n)) +#define BF_SYNCB_SYNCREQ_DUR_INFO(inst, n) ((inst) + 0x00000004 + 1 * (n)), 0x00000400 +#define BF_SYNCB_ERR_DUR_INFO(inst, n) ((inst) + 0x00000004 + 1 * (n)), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_SYNCB_GEN_3_ADDR(inst, n) ((inst) + 0x00000006 + 1 * (n)) +#define BF_LMFC_PERIOD_INFO(inst, n) ((inst) + 0x00000006 + 1 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JESD_DEBUG_REG_0_ADDR(inst) ((inst) + 0x00000008) +#define BF_JRX_DEBUG_BIT_INFO(inst) ((inst) + 0x00000008), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JESD_DEBUG_REG_1_ADDR(inst, n) ((inst) + 0x00000009 + 1 * (n)) +#define BF_CONV_CLK_DIV_INFO(inst, n) ((inst) + 0x00000009 + 1 * (n)), 0x00001000 +#endif /* USE_PRIVATE_BF */ + +#define REG_JESD_DEBUG_REG_2_ADDR(inst, n) ((inst) + 0x0000000B + 1 * (n)) + +#define REG_JESD_JRX_204BQBD_PA_INT_ENABLE_ADDR(inst, n) ((inst) + 0x0000000D + 1 * (n)) +#define BF_EN_204B_BD_JRX_INT_GAINOFF_INFO(inst, n) ((inst) + 0x0000000D + 1 * (n)), 0x00000100 +#define BF_EN_204B_NIT_JRX_INT_GAINOFF_INFO(inst, n) ((inst) + 0x0000000D + 1 * (n)), 0x00000101 +#define BF_EN_204B_UEK_JRX_INT_GAINOFF_INFO(inst, n) ((inst) + 0x0000000D + 1 * (n)), 0x00000102 + +#define REG_JESD_JRX_204H_PA_INT_ENABLE_ADDR(inst) ((inst) + 0x0000000E) + +#define REG_JESD_LANE_FIFO_INT_ENABLE_ADDR(inst, n) ((inst) + 0x0000000F + 1 * (n)) +#define BF_EN_JRX_LANE_FIFO_EMPTY_INT_GAINOFF_INFO(inst, n) ((inst) + 0x0000000F + 1 * (n)), 0x00000100 +#define BF_EN_JRX_LANE_FIFO_FULL_INT_GAINOFF_INFO(inst, n) ((inst) + 0x0000000F + 1 * (n)), 0x00000101 + +#define REG_FIFO_STATUS_REG_0_ADDR(inst) ((inst) + 0x00000011) +#define BF_LANE_FIFO_FULL_INFO(inst) ((inst) + 0x00000011), 0x00000C00 + +#define REG_FIFO_STATUS_REG_1_ADDR(inst) ((inst) + 0x00000020) + +#define REG_FIFO_STATUS_REG_2_ADDR(inst) ((inst) + 0x00000021) +#define BF_LANE_FIFO_EMPTY_INFO(inst) ((inst) + 0x00000021), 0x00000C00 + +#define REG_FIFO_STATUS_REG_3_ADDR(inst) ((inst) + 0x00000022) + +#ifdef USE_PRIVATE_BF +#define REG_JRX_CLK_DBUG_ADDR(inst) ((inst) + 0x00000023) +#define BF_CONV_CLK_EN_INFO(inst) ((inst) + 0x00000023), 0x00000100 +#define BF_PCLK_EN_INFO(inst) ((inst) + 0x00000023), 0x00000101 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TEST_MUX_0_ADDR(inst) ((inst) + 0x00000024) +#define BF_TMUX_LANE_SEL_INFO(inst) ((inst) + 0x00000024), 0x00000400 +#define BF_LINK_DATA_RDY_IRQ_SEL_INFO(inst) ((inst) + 0x00000024), 0x00000305 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TEST_MUX_1_ADDR(inst) ((inst) + 0x00000025) +#define BF_TMUX_SEL_A0_INFO(inst) ((inst) + 0x00000025), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TEST_MUX_2_ADDR(inst) ((inst) + 0x00000026) +#define BF_TMUX_SEL_A1_INFO(inst) ((inst) + 0x00000026), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#define REG_JRX_204C_IRQ_ADDR(inst, n) ((inst) + 0x00000027 + 1 * (n)) +#define BF_JRX_204C_SH_IRQ_INFO(inst, n) ((inst) + 0x00000027 + 1 * (n)), 0x00000100 +#define BF_JRX_204C_MB_IRQ_INFO(inst, n) ((inst) + 0x00000027 + 1 * (n)), 0x00000101 +#define BF_JRX_204C_EMB_IRQ_INFO(inst, n) ((inst) + 0x00000027 + 1 * (n)), 0x00000102 +#define BF_JRX_204C_CRC_IRQ_INFO(inst, n) ((inst) + 0x00000027 + 1 * (n)), 0x00000103 +#define BF_JRX_204C_SH_IRQ_ENABLE_INFO(inst, n) ((inst) + 0x00000027 + 1 * (n)), 0x00000104 +#define BF_JRX_204C_MB_IRQ_ENABLE_INFO(inst, n) ((inst) + 0x00000027 + 1 * (n)), 0x00000105 +#define BF_JRX_204C_EMB_IRQ_ENABLE_INFO(inst, n) ((inst) + 0x00000027 + 1 * (n)), 0x00000106 +#define BF_JRX_204C_CRC_IRQ_ENABLE_INFO(inst, n) ((inst) + 0x00000027 + 1 * (n)), 0x00000107 + +#define REG_GENERAL_JRX_CTRL_2_ADDR(inst, n) ((inst) + 0x00000029 + 1 * (n)) +#define BF_S_F_SEL_INFO(inst, n) ((inst) + 0x00000029 + 1 * (n)), 0x00000100 +#ifdef USE_PRIVATE_BF +#define BF_DOWN_SCALE_OVERFLOW_INFO(inst, n) ((inst) + 0x00000029 + 1 * (n)), 0x00000101 +#endif /* USE_PRIVATE_BF */ +#define BF_JESD_MODES_NOT_IN_TABLE_INFO(inst, n) ((inst) + 0x00000029 + 1 * (n)), 0x00000102 +#ifdef USE_PRIVATE_BF +#define BF_DOWN_SCALE_RATIO_INFO(inst, n) ((inst) + 0x00000029 + 1 * (n)), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#define REG_GENERAL_JRX_CTRL_3_ADDR(inst, n) ((inst) + 0x0000002B + 1 * (n)) +#define BF_JESD_MODE_INFO(inst, n) ((inst) + 0x0000002B + 1 * (n)), 0x00000800 + +#define REG_GENERAL_JRX_CTRL_5_ADDR(inst, n) ((inst) + 0x0000002E + 1 * (n)) +#define BF_LINK_TOTAL_INTERP_INFO(inst, n) ((inst) + 0x0000002E + 1 * (n)), 0x00001000 + +#define REG_GENERAL_JRX_CTRL_6_ADDR(inst, n) ((inst) + 0x00000030 + 1 * (n)) + +#ifdef USE_PRIVATE_BF +#define REG_GENERAL_JRX_CTRL_7_ADDR(inst, n) ((inst) + 0x00000032 + 1 * (n)) +#define BF_LINK_TOTAL_INTERP_MULTI_INFO(inst, n) ((inst) + 0x00000032 + 1 * (n)), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#define REG_GENERAL_JRX_CTRL_8_ADDR(inst, n) ((inst) + 0x00000034 + 1 * (n)) +#define BF_LINK_DUC_INTERP_INFO(inst, n) ((inst) + 0x00000034 + 1 * (n)), 0x00001000 + +#define REG_GENERAL_JRX_CTRL_9_ADDR(inst, n) ((inst) + 0x00000036 + 1 * (n)) + +#define REG_GENERAL_JRX_CTRL_10_ADDR(inst, n) ((inst) + 0x00000038 + 1 * (n)) +#define BF_NUM_OF_INVALID_SAMPLE_INFO(inst, n) ((inst) + 0x00000038 + 1 * (n)), 0x00000500 +#define BF_INVALID_DATA_EN_INFO(inst, n) ((inst) + 0x00000038 + 1 * (n)), 0x00000107 + +#ifdef USE_PRIVATE_BF +#define REG_JESD_DEBUG_REG_3_ADDR(inst, n) ((inst) + 0x0000003A + 1 * (n)) +#define BF_SPI_CONFIG_EN_INFO(inst, n) ((inst) + 0x0000003A + 1 * (n)), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#define REG_RM_FIFO_IRQ_ADDR(inst, n) ((inst) + 0x0000003C + 1 * (n)) +#define BF_RM_FIFO_EMPTY_IRQ_ENABLE_INFO(inst, n) ((inst) + 0x0000003C + 1 * (n)), 0x00000100 +#define BF_RM_FIFO_FULL_IRQ_ENABLE_INFO(inst, n) ((inst) + 0x0000003C + 1 * (n)), 0x00000101 +#define BF_INVALID_SAMPLE_ERR_IRQ_INFO(inst, n) ((inst) + 0x0000003C + 1 * (n)), 0x00000102 +#define BF_RM_FIFO_EMPTY_IRQ_INFO(inst, n) ((inst) + 0x0000003C + 1 * (n)), 0x00000104 +#define BF_RM_FIFO_FULL_IRQ_INFO(inst, n) ((inst) + 0x0000003C + 1 * (n)), 0x00000105 +#define BF_INVALID_SAMPLE_ERR_IRQ_ENABLE_INFO(inst, n) ((inst) + 0x0000003C + 1 * (n)), 0x00000106 + +#define REG_LANE_FIFO_IRQ_ADDR(inst, n) ((inst) + 0x0000003E + 1 * (n)) +#define BF_JRX_LANE_FIFO_EMPTY_IRQ_ENABLE_INFO(inst, n) ((inst) + 0x0000003E + 1 * (n)), 0x00000100 +#define BF_JRX_LANE_FIFO_FULL_IRQ_ENABLE_INFO(inst, n) ((inst) + 0x0000003E + 1 * (n)), 0x00000101 +#define BF_JRX_LANE_FIFO_EMPTY_IRQ_INFO(inst, n) ((inst) + 0x0000003E + 1 * (n)), 0x00000104 +#define BF_JRX_LANE_FIFO_FULL_IRQ_INFO(inst, n) ((inst) + 0x0000003E + 1 * (n)), 0x00000105 + +#define REG_RM_FIFO_STATUS_ADDR(inst) ((inst) + 0x00000050) +#define BF_RM_FIFO_EMPTY_INFO(inst) ((inst) + 0x00000050), 0x00000200 +#define BF_RM_FIFO_FULL_INFO(inst) ((inst) + 0x00000050), 0x00000202 +#define BF_INVALID_SAMPLE_ERR_INFO(inst) ((inst) + 0x00000050), 0x00000104 + +#define REG_JRX_DATA_RDY_LOST_IRQ_ADDR(inst, n) ((inst) + 0x00000051 + 1 * (n)) +#define BF_DATA_RDY_LOST_IRQ_ENABLE_INFO(inst, n) ((inst) + 0x00000051 + 1 * (n)), 0x00000100 +#define BF_DATA_RDY_LOST_IRQ_INFO(inst, n) ((inst) + 0x00000051 + 1 * (n)), 0x00000104 + +#ifdef USE_PRIVATE_BF +#define REG_DEBUG_CLK_SEL_1_ADDR(inst) ((inst) + 0x00000053) +#define BF_DEBUG_CLK_OUTPUT_SEL0_INFO(inst) ((inst) + 0x00000053), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_DEBUG_CLK_SEL_0_ADDR(inst) ((inst) + 0x00000054) +#define BF_DEBUG_CLK_OUTPUT_SEL1_INFO(inst) ((inst) + 0x00000054), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_RM_FIFO_CTRL_ADDR(inst) ((inst) + 0x00000055) +#define BF_RM_FIFO_RESET_INFO(inst) ((inst) + 0x00000055), 0x00000100 +#define BF_HOLD_INVALID_SAMPLE_ERR_INFO(inst) ((inst) + 0x00000055), 0x00000104 + +#define REG_RM_FIFO_INT_ENABLE_ADDR(inst, n) ((inst) + 0x00000056 + 1 * (n)) +#define BF_EN_RM_FIFO_EMPTY_INT_GAINOFF_INFO(inst, n) ((inst) + 0x00000056 + 1 * (n)), 0x00000100 +#define BF_EN_RM_FIFO_FULL_INT_GAINOFF_INFO(inst, n) ((inst) + 0x00000056 + 1 * (n)), 0x00000101 +#define BF_EN_INVALID_SAMPLE_INT_GAINOFF_INFO(inst, n) ((inst) + 0x00000056 + 1 * (n)), 0x00000104 + +#define REG_DATA_RDY_LOST_INT_ENABLE_ADDR(inst, n) ((inst) + 0x00000058 + 1 * (n)) +#define BF_EN_DATA_RDY_LOST_INT_GAINOFF_INFO(inst, n) ((inst) + 0x00000058 + 1 * (n)), 0x00000100 + +#define REG_JESD_JRX_204C_PA_INT_ENABLE_ADDR(inst, n) ((inst) + 0x0000005A + 1 * (n)) +#define BF_EN_204C_SH_ERR_JRX_INT_GAINOFF_INFO(inst, n) ((inst) + 0x0000005A + 1 * (n)), 0x00000100 +#define BF_EN_204C_MB_ERR_JRX_INT_GAINOFF_INFO(inst, n) ((inst) + 0x0000005A + 1 * (n)), 0x00000101 +#define BF_EN_204C_EMB_ERR_JRX_INT_GAINOFF_INFO(inst, n) ((inst) + 0x0000005A + 1 * (n)), 0x00000102 +#define BF_EN_204C_CRC_ERR_JRX_INT_GAINOFF_INFO(inst, n) ((inst) + 0x0000005A + 1 * (n)), 0x00000103 + +#ifdef USE_PRIVATE_BF +#define REG_GENERAL_JRX_CTRL_11_ADDR(inst) ((inst) + 0x0000005C) +#define BF_CRC_ERR_THRESHOLD_INFO(inst) ((inst) + 0x0000005C), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_GENERAL_JRX_CTRL_12_ADDR(inst) ((inst) + 0x0000005D) +#define BF_LINK0_RAMP_SEL_INFO(inst) ((inst) + 0x0000005D), 0x00000400 + +#define REG_GENERAL_JRX_CTRL_13_ADDR(inst) ((inst) + 0x0000005E) +#define BF_LINK1_RAMP_SEL_INFO(inst) ((inst) + 0x0000005E), 0x00000400 + +#define REG_GENERAL_JRX_CTRL_14_ADDR(inst) ((inst) + 0x0000005F) +#define BF_LINK_RAMP_DECODER_BYPASS_INFO(inst) ((inst) + 0x0000005F), 0x00000200 + +#define REG_GENERAL_JRX_CTRL_15_ADDR(inst, n) ((inst) + 0x00000060 + 1 * (n)) +#define BF_SAMPLE_REPEAT_EN_INFO(inst, n) ((inst) + 0x00000060 + 1 * (n)), 0x00000100 + +#define REG_GENERAL_JRX_CTRL_16_ADDR(inst, n) ((inst) + 0x00000062 + 1 * (n)) +#define BF_SYNCB_STATUS_INFO(inst, n) ((inst) + 0x00000062 + 1 * (n)), 0x00000100 + +#define REG_SERDES_RX_WR_SETUP_CTRL_ADDR(inst) ((inst) + 0x00000064) +#define BF_SERDES_RX_ANA_BRIDGE_WR_SETUP_CYCLES_INFO(inst) ((inst) + 0x00000064), 0x00000600 + +#define REG_SERDES_RX_WR_HOLD_CTRL_ADDR(inst) ((inst) + 0x00000065) +#define BF_SERDES_RX_ANA_BRIDGE_WR_HOLD_CYCLES_INFO(inst) ((inst) + 0x00000065), 0x00000600 + +#define REG_SERDES_RX_RD_CTRL_ADDR(inst) ((inst) + 0x00000066) +#define BF_SERDES_RX_ANA_BRIDGE_RD_CYCLES_INFO(inst) ((inst) + 0x00000066), 0x00000600 + +#endif /* __ADI_APOLLO_BF_JRX_WRAPPER_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_jtx_dformat.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_jtx_dformat.h new file mode 100644 index 00000000000000..00eb7ca7ff55ec --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_jtx_dformat.h @@ -0,0 +1,210 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:21 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_JTX_DFORMAT_H__ +#define __ADI_APOLLO_BF_JTX_DFORMAT_H__ + +/*============= D E F I N E S ==============*/ +#define JTX_DFORMAT_JTX_TOP_RX_DIGITAL0 0x60600000 +#define JTX_DFORMAT_JTX_TOP_RX_DIGITAL1 0x60E00000 + +#define REG_DFORMAT_OUT_FORMAT_SEL0_ADDR(inst) ((inst) + 0x00000000) +#define BF_DFORMAT_SEL_0_INFO(inst) ((inst) + 0x00000000), 0x00000200 +#define BF_DFORMAT_INV_0_INFO(inst) ((inst) + 0x00000000), 0x00000102 + +#define REG_DFORMAT_OUT_FORMAT_SEL1_ADDR(inst) ((inst) + 0x00000001) +#define BF_DFORMAT_SEL_1_INFO(inst) ((inst) + 0x00000001), 0x00000200 +#define BF_DFORMAT_INV_1_INFO(inst) ((inst) + 0x00000001), 0x00000102 + +#define REG_DFORMAT_OUT_RES0_ADDR(inst) ((inst) + 0x00000002) +#define BF_DFORMAT_RES_0_INFO(inst) ((inst) + 0x00000002), 0x00000400 +#define BF_DFORMAT_DDC_DITHER_EN_0_INFO(inst) ((inst) + 0x00000002), 0x00000104 + +#define REG_DFORMAT_OUT_RES1_ADDR(inst) ((inst) + 0x00000003) +#define BF_DFORMAT_RES_1_INFO(inst) ((inst) + 0x00000003), 0x00000400 +#define BF_DFORMAT_DDC_DITHER_EN_1_INFO(inst) ((inst) + 0x00000003), 0x00000104 + +#define REG_LINK_EN_ADDR(inst) ((inst) + 0x00000004) +#define BF_LINK_EN_0_INFO(inst) ((inst) + 0x00000004), 0x00000100 +#define BF_LINK_EN_1_INFO(inst) ((inst) + 0x00000004), 0x00000101 + +#define REG_DFORMAT_TMODE_SEL0_ADDR(inst) ((inst) + 0x00000005) +#define BF_DFORMAT_TMODE_SEL_0_INFO(inst) ((inst) + 0x00000005), 0x00000800 + +#define REG_DFORMAT_TMODE_SEL1_ADDR(inst) ((inst) + 0x00000006) +#define BF_DFORMAT_TMODE_SEL_1_INFO(inst) ((inst) + 0x00000006), 0x00000800 + +#define REG_DFORMAT_OVR_CLR0_ADDR(inst) ((inst) + 0x00000007) +#define BF_DFORMAT_OVR_CLR_0_INFO(inst) ((inst) + 0x00000007), 0x00000800 + +#define REG_DFORMAT_OVR_CLR1_ADDR(inst) ((inst) + 0x00000008) +#define BF_DFORMAT_OVR_CLR_1_INFO(inst) ((inst) + 0x00000008), 0x00000800 + +#define REG_DFORMAT_OVR_STATUS0_ADDR(inst) ((inst) + 0x00000009) +#define BF_DFORMAT_OVR_STATUS_0_INFO(inst) ((inst) + 0x00000009), 0x00000800 + +#define REG_DFORMAT_OVR_STATUS1_ADDR(inst) ((inst) + 0x0000000A) +#define BF_DFORMAT_OVR_STATUS_1_INFO(inst) ((inst) + 0x0000000A), 0x00000800 + +#define REG_LINK0_DDC_DEC0_ADDR(inst) ((inst) + 0x0000000B) +#define BF_LINK_DDC_DEC_0_INFO(inst) ((inst) + 0x0000000B), 0x00000A00 + +#define REG_LINK0_DDC_DEC1_ADDR(inst) ((inst) + 0x0000000C) + +#define REG_LINK1_DDC_DEC0_ADDR(inst) ((inst) + 0x0000000D) +#define BF_LINK_DDC_DEC_1_INFO(inst) ((inst) + 0x0000000D), 0x00000A00 + +#define REG_LINK1_DDC_DEC1_ADDR(inst) ((inst) + 0x0000000E) + +#define REG_CTRL_BIT_0_SEL0_ADDR(inst) ((inst) + 0x0000000F) +#define BF_DFORMAT_CTRL_BIT_0_SEL_0_INFO(inst) ((inst) + 0x0000000F), 0x00000400 + +#define REG_CTRL_BIT_0_SEL1_ADDR(inst) ((inst) + 0x00000010) +#define BF_DFORMAT_CTRL_BIT_0_SEL_1_INFO(inst) ((inst) + 0x00000010), 0x00000400 + +#define REG_CTRL_BIT_1_SEL0_ADDR(inst) ((inst) + 0x00000011) +#define BF_DFORMAT_CTRL_BIT_1_SEL_0_INFO(inst) ((inst) + 0x00000011), 0x00000400 + +#define REG_CTRL_BIT_1_SEL1_ADDR(inst) ((inst) + 0x00000012) +#define BF_DFORMAT_CTRL_BIT_1_SEL_1_INFO(inst) ((inst) + 0x00000012), 0x00000400 + +#define REG_CTRL_BIT_2_SEL0_ADDR(inst) ((inst) + 0x00000013) +#define BF_DFORMAT_CTRL_BIT_2_SEL_0_INFO(inst) ((inst) + 0x00000013), 0x00000400 + +#define REG_CTRL_BIT_2_SEL1_ADDR(inst) ((inst) + 0x00000014) +#define BF_DFORMAT_CTRL_BIT_2_SEL_1_INFO(inst) ((inst) + 0x00000014), 0x00000400 + +#define REG_TMODE_USR_LSB_P0_ADDR(inst, n) ((inst) + 0x0000001D + 1 * (n)) +#define BF_TMODE_USR_PAT0_INFO(inst, n) ((inst) + 0x0000001D + 1 * (n)), 0x00001000 + +#define REG_TMODE_USR_MSB_P0_ADDR(inst, n) ((inst) + 0x0000001F + 1 * (n)) + +#define REG_TMODE_USR_LSB_P1_ADDR(inst, n) ((inst) + 0x00000021 + 1 * (n)) +#define BF_TMODE_USR_PAT1_INFO(inst, n) ((inst) + 0x00000021 + 1 * (n)), 0x00001000 + +#define REG_TMODE_USR_MSB_P1_ADDR(inst, n) ((inst) + 0x00000023 + 1 * (n)) + +#define REG_TMODE_USR_LSB_P2_ADDR(inst, n) ((inst) + 0x00000025 + 1 * (n)) +#define BF_TMODE_USR_PAT2_INFO(inst, n) ((inst) + 0x00000025 + 1 * (n)), 0x00001000 + +#define REG_TMODE_USR_MSB_P2_ADDR(inst, n) ((inst) + 0x00000027 + 1 * (n)) + +#define REG_TMODE_USR_LSB_P3_ADDR(inst, n) ((inst) + 0x00000029 + 1 * (n)) +#define BF_TMODE_USR_PAT3_INFO(inst, n) ((inst) + 0x00000029 + 1 * (n)), 0x00001000 + +#define REG_TMODE_USR_MSB_P3_ADDR(inst, n) ((inst) + 0x0000002B + 1 * (n)) + +#define REG_TMODE_USR_LSB_P4_ADDR(inst, n) ((inst) + 0x0000002D + 1 * (n)) +#define BF_TMODE_USR_PAT4_INFO(inst, n) ((inst) + 0x0000002D + 1 * (n)), 0x00001000 + +#define REG_TMODE_USR_MSB_P4_ADDR(inst, n) ((inst) + 0x0000002F + 1 * (n)) + +#define REG_TMODE_USR_LSB_P5_ADDR(inst, n) ((inst) + 0x00000031 + 1 * (n)) +#define BF_TMODE_USR_PAT5_INFO(inst, n) ((inst) + 0x00000031 + 1 * (n)), 0x00001000 + +#define REG_TMODE_USR_MSB_P5_ADDR(inst, n) ((inst) + 0x00000033 + 1 * (n)) + +#define REG_TMODE_USR_LSB_P6_ADDR(inst, n) ((inst) + 0x00000035 + 1 * (n)) +#define BF_TMODE_USR_PAT6_INFO(inst, n) ((inst) + 0x00000035 + 1 * (n)), 0x00001000 + +#define REG_TMODE_USR_MSB_P6_ADDR(inst, n) ((inst) + 0x00000037 + 1 * (n)) + +#define REG_TMODE_USR_LSB_P7_ADDR(inst, n) ((inst) + 0x00000039 + 1 * (n)) +#define BF_TMODE_USR_PAT7_INFO(inst, n) ((inst) + 0x00000039 + 1 * (n)), 0x00001000 + +#define REG_TMODE_USR_MSB_P7_ADDR(inst, n) ((inst) + 0x0000004B + 1 * (n)) + +#define REG_LINK_TOTAL_DEC0_LSB_ADDR(inst) ((inst) + 0x0000006D) +#define BF_LINK_TOTAL_DEC_0_INFO(inst) ((inst) + 0x0000006D), 0x00000B00 + +#define REG_LINK_TOTAL_DEC0_MSB_ADDR(inst) ((inst) + 0x0000006E) + +#define REG_LINK_TOTAL_DEC1_LSB_ADDR(inst) ((inst) + 0x0000006F) +#define BF_LINK_TOTAL_DEC_1_INFO(inst) ((inst) + 0x0000006F), 0x00000B00 + +#define REG_LINK_TOTAL_DEC1_MSB_ADDR(inst) ((inst) + 0x00000070) + +#define REG_INVALID_EN_ADDR(inst) ((inst) + 0x00000071) +#define BF_INVALID_EN_INFO(inst) ((inst) + 0x00000071), 0x00000200 + +#define REG_FINE_I_SEL_ADDR(inst) ((inst) + 0x00000072) +#define BF_FINE0_ADC_I_SEL_INFO(inst) ((inst) + 0x00000072), 0x00000200 +#define BF_FINE1_ADC_I_SEL_INFO(inst) ((inst) + 0x00000072), 0x00000202 +#define BF_FINE2_ADC_I_SEL_INFO(inst) ((inst) + 0x00000072), 0x00000204 +#define BF_FINE3_ADC_I_SEL_INFO(inst) ((inst) + 0x00000072), 0x00000206 + +#define REG_FINE_I_SEL_8T8R_ADDR(inst) ((inst) + 0x00000073) +#define BF_FINE4_ADC_I_SEL_INFO(inst) ((inst) + 0x00000073), 0x00000200 +#define BF_FINE5_ADC_I_SEL_INFO(inst) ((inst) + 0x00000073), 0x00000202 +#define BF_FINE6_ADC_I_SEL_INFO(inst) ((inst) + 0x00000073), 0x00000204 +#define BF_FINE7_ADC_I_SEL_INFO(inst) ((inst) + 0x00000073), 0x00000206 + +#define REG_FINE_Q_SEL_ADDR(inst) ((inst) + 0x00000074) +#define BF_FINE0_ADC_Q_SEL_INFO(inst) ((inst) + 0x00000074), 0x00000200 +#define BF_FINE1_ADC_Q_SEL_INFO(inst) ((inst) + 0x00000074), 0x00000202 +#define BF_FINE2_ADC_Q_SEL_INFO(inst) ((inst) + 0x00000074), 0x00000204 +#define BF_FINE3_ADC_Q_SEL_INFO(inst) ((inst) + 0x00000074), 0x00000206 + +#define REG_FINE_Q_SEL_8T8R_ADDR(inst) ((inst) + 0x00000075) +#define BF_FINE4_ADC_Q_SEL_INFO(inst) ((inst) + 0x00000075), 0x00000200 +#define BF_FINE5_ADC_Q_SEL_INFO(inst) ((inst) + 0x00000075), 0x00000202 +#define BF_FINE6_ADC_Q_SEL_INFO(inst) ((inst) + 0x00000075), 0x00000204 +#define BF_FINE7_ADC_Q_SEL_INFO(inst) ((inst) + 0x00000075), 0x00000206 + +#define REG_TMODE_CTRL0_LINK0_ADDR(inst) ((inst) + 0x00000076) +#define BF_TMODE_TYPE_SEL_INFO(inst) ((inst) + 0x00000076), 0x00000400 + +#define REG_TMODE_CTRL1_LINK0_ADDR(inst) ((inst) + 0x00000078) +#define BF_TMODE_USR_PAT_SEL_INFO(inst) ((inst) + 0x00000078), 0x00000100 +#define BF_TMODE_FLUSH_INFO(inst) ((inst) + 0x00000078), 0x00000101 +#define BF_TMODE_PN_FORCE_RST_INFO(inst) ((inst) + 0x00000078), 0x00000102 + +#define REG_TMODE_CTRL2_LINK0_ADDR(inst) ((inst) + 0x0000007A) +#define BF_TMODE_RES_INFO(inst) ((inst) + 0x0000007A), 0x00000400 + +#define REG_TMODE_CTRL0_LINK1_ADDR(inst) ((inst) + 0x0000007B) +#define BF_TMODE_TYPE_SEL_LINK1_INFO(inst) ((inst) + 0x0000007B), 0x00000400 + +#define REG_TMODE_CTRL1_LINK1_ADDR(inst) ((inst) + 0x0000007C) +#define BF_TMODE_USR_PAT_SEL_LINK1_INFO(inst) ((inst) + 0x0000007C), 0x00000100 +#define BF_TMODE_FLUSH_LINK1_INFO(inst) ((inst) + 0x0000007C), 0x00000101 +#define BF_TMODE_PN_FORCE_RST_LINK1_INFO(inst) ((inst) + 0x0000007C), 0x00000102 + +#define REG_TMODE_CTRL2_LINK1_ADDR(inst) ((inst) + 0x0000007D) +#define BF_TMODE_RES_LINK1_INFO(inst) ((inst) + 0x0000007D), 0x00000400 + +#define REG_DFORMAT_NEG_FULL_SCALE_CLR0_ADDR(inst) ((inst) + 0x0000007E) +#define BF_DFORMAT_NEG_FULL_SCALE_CLR_0_INFO(inst) ((inst) + 0x0000007E), 0x00000800 + +#define REG_DFORMAT_NEG_FULL_SCALE_CLR1_ADDR(inst) ((inst) + 0x0000007F) +#define BF_DFORMAT_NEG_FULL_SCALE_CLR_1_INFO(inst) ((inst) + 0x0000007F), 0x00000800 + +#define REG_DFORMAT_NEG_FULL_SCALE_STATUS0_ADDR(inst) ((inst) + 0x00000080) +#define BF_DFORMAT_NEG_FULL_SCALE_STATUS_0_INFO(inst) ((inst) + 0x00000080), 0x00000800 + +#define REG_DFORMAT_NEG_FULL_SCALE_STATUS1_ADDR(inst) ((inst) + 0x00000081) +#define BF_DFORMAT_NEG_FULL_SCALE_STATUS_1_INFO(inst) ((inst) + 0x00000081), 0x00000800 + +#define REG_SAMPLE_REPEAT_EN_ADDR(inst) ((inst) + 0x00000082) +#define BF_SAMPLE_REPEAT_EN_0_INFO(inst) ((inst) + 0x00000082), 0x00000100 +#define BF_SAMPLE_REPEAT_EN_1_INFO(inst) ((inst) + 0x00000082), 0x00000101 + +#define REG_STARTUP_FORCE_INVALID_EN_ADDR(inst, n) ((inst) + 0x00000083 + 1 * (n)) +#define BF_STARTUP_FRCE_INVALID_EN_INFO(inst, n) ((inst) + 0x00000083 + 1 * (n)), 0x00000100 + +#define REG_FORCE_INVALID_EN_ADDR(inst, n) ((inst) + 0x00000085 + 1 * (n)) +#define BF_FORCE_INVALID_EN_INFO(inst, n) ((inst) + 0x00000085 + 1 * (n)), 0x00000100 + +#endif /* __ADI_APOLLO_BF_JTX_DFORMAT_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_jtx_dual_link.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_jtx_dual_link.h new file mode 100644 index 00000000000000..c6a8da8060f6cf --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_jtx_dual_link.h @@ -0,0 +1,253 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:21 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_JTX_DUAL_LINK_H__ +#define __ADI_APOLLO_BF_JTX_DUAL_LINK_H__ + +/*============= D E F I N E S ==============*/ +#define JTX_DUAL_LINK_0_JTX_TOP_RX_DIGITAL0 0x60610000 +#define JTX_DUAL_LINK_1_JTX_TOP_RX_DIGITAL0 0x60614000 +#define JTX_DUAL_LINK_0_JTX_TOP_RX_DIGITAL1 0x60E10000 +#define JTX_DUAL_LINK_1_JTX_TOP_RX_DIGITAL1 0x60E14000 + +#define REG_JTX_CORE_1_ADDR(inst) ((inst) + 0x00000011) +#define BF_JTX_CHKSUM_LSB_ALG_INFO(inst) ((inst) + 0x00000011), 0x00000100 +#define BF_JTX_CHKSUM_DISABLE_INFO(inst) ((inst) + 0x00000011), 0x00000101 +#define BF_JTX_LINK_204C_SEL_INFO(inst) ((inst) + 0x00000011), 0x00000204 +#define BF_JTX_SYSREF_FOR_STARTUP_INFO(inst) ((inst) + 0x00000011), 0x00000106 +#define BF_JTX_SYSREF_FOR_RELINK_INFO(inst) ((inst) + 0x00000011), 0x00000107 + +#define REG_JTX_CORE_2_LANE_ADDR(inst, n) ((inst) + 0x00000020 + 1 * (n)) +#define BF_JTX_LANE_ASSIGN_INFO(inst, n) ((inst) + 0x00000020 + 1 * (n)), 0x00000500 +#define BF_JTX_LANE_INV_INFO(inst, n) ((inst) + 0x00000020 + 1 * (n)), 0x00000105 +#define BF_JTX_FORCE_LANE_PD_INFO(inst, n) ((inst) + 0x00000020 + 1 * (n)), 0x00000106 +#define BF_JTX_LANE_PD_INFO(inst, n) ((inst) + 0x00000020 + 1 * (n)), 0x00000107 + +#define REG_JTX_CORE_3_ADDR(inst) ((inst) + 0x00000030) +#define BF_JTX_TEST_GEN_MODE_INFO(inst) ((inst) + 0x00000030), 0x00000400 +#define BF_JTX_TEST_GEN_SEL_INFO(inst) ((inst) + 0x00000030), 0x00000204 +#define BF_JTX_TEST_MIRROR_INFO(inst) ((inst) + 0x00000030), 0x00000106 +#define BF_JTX_TEST_USER_GO_INFO(inst) ((inst) + 0x00000030), 0x00000107 + +#define REG_JTX_CORE_4_ADDR(inst) ((inst) + 0x00000031) + +#define REG_JTX_CORE_5_ADDR(inst) ((inst) + 0x00000032) + +#define REG_JTX_CORE_6_ADDR(inst) ((inst) + 0x00000033) + +#define REG_JTX_CORE_7_ADDR(inst) ((inst) + 0x00000034) + +#define REG_JTX_CORE_8_ADDR(inst) ((inst) + 0x00000035) + +#define REG_JTX_CORE_9_ADDR(inst) ((inst) + 0x00000036) + +#define REG_JTX_CORE_10_ADDR(inst) ((inst) + 0x00000037) + +#define REG_JTX_CORE_11_ADDR(inst) ((inst) + 0x00000038) + +#define REG_JTX_CORE_12_ADDR(inst) ((inst) + 0x00000039) +#define BF_JTX_SYNC_N_SEL_INFO(inst) ((inst) + 0x00000039), 0x00000305 + +#define REG_JTX_CORE_13_ADDR(inst) ((inst) + 0x0000003A) +#define BF_JTX_LINK_EN_INFO(inst) ((inst) + 0x0000003A), 0x00000100 + +#define REG_JTX_CORE_0_CONV_ADDR(inst, n) ((inst) + 0x00000040 + 1 * (n)) +#define BF_JTX_CONV_SEL_INFO(inst, n) ((inst) + 0x00000040 + 1 * (n)), 0x00000700 +#ifdef USE_PRIVATE_BF +#define BF_JTX_CONV_MASK_INFO(inst, n) ((inst) + 0x00000040 + 1 * (n)), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#define REG_JTX_TPL_0_ADDR(inst) ((inst) + 0x00000080) +#define BF_JTX_TPL_ADAPTIVE_LATENCY_INFO(inst) ((inst) + 0x00000080), 0x00000100 +#define BF_JTX_TPL_TEST_ENABLE_INFO(inst) ((inst) + 0x00000080), 0x00000101 +#define BF_JTX_CONV_ASYNCHRONOUS_INFO(inst) ((inst) + 0x00000080), 0x00000102 +#define BF_JTX_NS_CFG_INFO(inst) ((inst) + 0x00000080), 0x00000503 + +#define REG_JTX_TPL_1_ADDR(inst) ((inst) + 0x00000081) +#define BF_JTX_TPL_LATENCY_ADJUST_INFO(inst) ((inst) + 0x00000081), 0x00000800 + +#define REG_JTX_TPL_2_ADDR(inst) ((inst) + 0x00000082) +#define BF_JTX_TPL_PHASE_ADJUST_INFO(inst) ((inst) + 0x00000082), 0x00001000 + +#define REG_JTX_TPL_3_ADDR(inst) ((inst) + 0x00000083) + +#define REG_JTX_TPL_4_ADDR(inst) ((inst) + 0x00000084) +#define BF_JTX_TPL_TEST_NUM_FRAMES_M1_INFO(inst) ((inst) + 0x00000084), 0x00001000 + +#define REG_JTX_TPL_5_ADDR(inst) ((inst) + 0x00000085) + +#define REG_JTX_TPL_6_ADDR(inst) ((inst) + 0x00000086) +#define BF_JTX_TPL_INVALID_CFG_INFO(inst) ((inst) + 0x00000086), 0x00000100 +#define BF_JTX_TPL_SYSREF_RCVD_INFO(inst) ((inst) + 0x00000086), 0x00000101 +#define BF_JTX_TPL_SYSREF_PHASE_ERR_INFO(inst) ((inst) + 0x00000086), 0x00000102 +#define BF_JTX_TPL_SYSREF_MASK_INFO(inst) ((inst) + 0x00000086), 0x00000105 +#define BF_JTX_TPL_SYSREF_CLR_PHASE_ERR_INFO(inst) ((inst) + 0x00000086), 0x00000106 +#define BF_JTX_TPL_SYSREF_IGNORE_WHEN_LINKED_INFO(inst) ((inst) + 0x00000086), 0x00000107 + +#define REG_JTX_TPL_7_ADDR(inst) ((inst) + 0x00000087) +#define BF_JTX_TPL_SYSREF_N_SHOT_COUNT_INFO(inst) ((inst) + 0x00000087), 0x00000400 +#define BF_JTX_TPL_SYSREF_N_SHOT_ENABLE_INFO(inst) ((inst) + 0x00000087), 0x00000104 + +#define REG_JTX_TPL_8_ADDR(inst) ((inst) + 0x00000088) +#define BF_JTX_TPL_LATENCY_ADDED_INFO(inst) ((inst) + 0x00000088), 0x00000800 + +#ifdef USE_PRIVATE_BF +#define REG_JTX_TPL_9_ADDR(inst) ((inst) + 0x00000089) +#define BF_JTX_TPL_BUF_FRAMES_INFO(inst) ((inst) + 0x00000089), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_JTX_L0_0_ADDR(inst) ((inst) + 0x00000090) +#define BF_JTX_DID_CFG_INFO(inst) ((inst) + 0x00000090), 0x00000800 + +#define REG_JTX_L0_1_ADDR(inst) ((inst) + 0x00000091) +#define BF_JTX_BID_CFG_INFO(inst) ((inst) + 0x00000091), 0x00000400 +#define BF_JTX_ADJCNT_CFG_INFO(inst) ((inst) + 0x00000091), 0x00000404 + +#define REG_JTX_L0_2_ADDR(inst) ((inst) + 0x00000092) +#define BF_JTX_PHADJ_CFG_INFO(inst) ((inst) + 0x00000092), 0x00000105 +#define BF_JTX_ADJDIR_CFG_INFO(inst) ((inst) + 0x00000092), 0x00000106 + +#define REG_JTX_L0_3_ADDR(inst) ((inst) + 0x00000093) +#define BF_JTX_L_CFG_INFO(inst) ((inst) + 0x00000093), 0x00000500 +#define BF_JTX_SCR_CFG_INFO(inst) ((inst) + 0x00000093), 0x00000107 + +#define REG_JTX_L0_4_ADDR(inst) ((inst) + 0x00000094) +#define BF_JTX_F_CFG_INFO(inst) ((inst) + 0x00000094), 0x00000800 + +#define REG_JTX_L0_5_ADDR(inst) ((inst) + 0x00000095) +#define BF_JTX_K_CFG_INFO(inst) ((inst) + 0x00000095), 0x00000800 + +#define REG_JTX_L0_6_ADDR(inst) ((inst) + 0x00000096) +#define BF_JTX_M_CFG_INFO(inst) ((inst) + 0x00000096), 0x00000800 + +#define REG_JTX_L0_7_ADDR(inst) ((inst) + 0x00000097) +#define BF_JTX_N_CFG_INFO(inst) ((inst) + 0x00000097), 0x00000500 +#define BF_JTX_CS_CFG_INFO(inst) ((inst) + 0x00000097), 0x00000206 + +#define REG_JTX_L0_8_ADDR(inst) ((inst) + 0x00000098) +#define BF_JTX_NP_CFG_INFO(inst) ((inst) + 0x00000098), 0x00000500 +#define BF_JTX_SUBCLASSV_CFG_INFO(inst) ((inst) + 0x00000098), 0x00000305 + +#define REG_JTX_L0_9_ADDR(inst) ((inst) + 0x00000099) +#define BF_JTX_S_CFG_INFO(inst) ((inst) + 0x00000099), 0x00000500 +#define BF_JTX_JESDV_CFG_INFO(inst) ((inst) + 0x00000099), 0x00000305 + +#define REG_JTX_L0_10_ADDR(inst) ((inst) + 0x0000009A) +#define BF_JTX_HD_CFG_INFO(inst) ((inst) + 0x0000009A), 0x00000107 + +#define REG_JTX_L0_13_LANE_ADDR(inst, n) ((inst) + 0x000000A0 + 1 * (n)) +#define BF_JTX_CHKSUM_CFG_INFO(inst, n) ((inst) + 0x000000A0 + 1 * (n)), 0x00000800 + +#define REG_JTX_L0_14_LANE_ADDR(inst, n) ((inst) + 0x000000B0 + 1 * (n)) +#define BF_JTX_LID_CFG_INFO(inst, n) ((inst) + 0x000000B0 + 1 * (n)), 0x00000500 + +#define REG_JTX_DL_204B_0_ADDR(inst) ((inst) + 0x000000C0) +#define BF_JTX_DL_204B_BYP_ACG_CFG_INFO(inst) ((inst) + 0x000000C0), 0x00000100 +#define BF_JTX_DL_204B_BYP_8B10B_CFG_INFO(inst) ((inst) + 0x000000C0), 0x00000101 +#define BF_JTX_DL_204B_ILAS_TEST_EN_CFG_INFO(inst) ((inst) + 0x000000C0), 0x00000102 +#define BF_JTX_DL_204B_BYP_ILAS_CFG_INFO(inst) ((inst) + 0x000000C0), 0x00000103 +#define BF_JTX_DL_204B_ILAS_DELAY_CFG_INFO(inst) ((inst) + 0x000000C0), 0x00000404 + +#define REG_JTX_DL_204B_1_ADDR(inst) ((inst) + 0x000000C1) +#define BF_JTX_DL_204B_10B_MIRROR_INFO(inst) ((inst) + 0x000000C1), 0x00000100 +#define BF_JTX_DL_204B_DEL_SCR_CFG_INFO(inst) ((inst) + 0x000000C1), 0x00000101 +#define BF_JTX_DL_204B_LSYNC_EN_CFG_INFO(inst) ((inst) + 0x000000C1), 0x00000102 + +#define REG_JTX_DL_204B_2_ADDR(inst) ((inst) + 0x000000C2) +#define BF_JTX_DL_204B_KF_ILAS_CFG_INFO(inst) ((inst) + 0x000000C2), 0x00000800 + +#define REG_JTX_DL_204B_3_ADDR(inst) ((inst) + 0x000000C3) +#define BF_JTX_DL_204B_RJSPAT_EN_CFG_INFO(inst) ((inst) + 0x000000C3), 0x00000100 +#define BF_JTX_DL_204B_RJSPAT_SEL_CFG_INFO(inst) ((inst) + 0x000000C3), 0x00000201 +#define BF_JTX_DL_204B_TPL_TEST_EN_CFG_INFO(inst) ((inst) + 0x000000C3), 0x00000104 +#define BF_JTX_DL_204B_SYNC_N_INFO(inst) ((inst) + 0x000000C3), 0x00000105 +#define BF_JTX_DL_204B_TESTMODE_IGNORE_SYNCN_CFG_INFO(inst) ((inst) + 0x000000C3), 0x00000106 +#define BF_JTX_DL_204B_CLEAR_SYNC_NE_COUNT_INFO(inst) ((inst) + 0x000000C3), 0x00000107 + +#define REG_JTX_DL_204B_4_ADDR(inst) ((inst) + 0x000000C4) +#define BF_JTX_DL_204B_STATE_INFO(inst) ((inst) + 0x000000C4), 0x00000400 +#define BF_JTX_DL_204B_SYNC_N_FORCE_VAL_INFO(inst) ((inst) + 0x000000C4), 0x00000106 +#define BF_JTX_DL_204B_SYNC_N_FORCE_EN_INFO(inst) ((inst) + 0x000000C4), 0x00000107 + +#define REG_JTX_DL_204B_5_ADDR(inst) ((inst) + 0x000000C5) +#define BF_JTX_DL_204B_SYNC_NE_COUNT_INFO(inst) ((inst) + 0x000000C5), 0x00000800 + +#define REG_JTX_DL_204B_6_LANE_ADDR(inst, n) ((inst) + 0x000000C6 + 1 * (n)) +#ifdef USE_PRIVATE_BF +#define BF_JTX_DL_204B_L_EN_CFG_INFO(inst, n) ((inst) + 0x000000C6 + 1 * (n)), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_JTX_DL_204B_PHY_DATA_SEL_CFG_INFO(inst, n) ((inst) + 0x000000C6 + 1 * (n)), 0x00000102 +#define BF_JTX_DL_204B_SCR_DATA_SEL_CFG_INFO(inst, n) ((inst) + 0x000000C6 + 1 * (n)), 0x00000103 +#define BF_JTX_DL_204B_SCR_IN_CTRL_CFG_INFO(inst, n) ((inst) + 0x000000C6 + 1 * (n)), 0x00000104 + +#define REG_JTX_DL_204C_0_ADDR(inst) ((inst) + 0x000000F0) +#define BF_JTX_CRC_FEC_REVERSE_CFG_INFO(inst) ((inst) + 0x000000F0), 0x00000100 +#define BF_JTX_LINK_FEC_ENABLE_INFO(inst) ((inst) + 0x000000F0), 0x00000101 +#define BF_JTX_FORCE_METABITS_INFO(inst) ((inst) + 0x000000F0), 0x00000102 +#define BF_JTX_DL_204C_SYSREF_RCVD_INFO(inst) ((inst) + 0x000000F0), 0x00000103 + +#define REG_JTX_DL_204C_1_ADDR(inst) ((inst) + 0x000000F1) +#define BF_JTX_E_CFG_INFO(inst) ((inst) + 0x000000F1), 0x00000800 + +#define REG_JTX_DL_204C_2_ADDR(inst) ((inst) + 0x000000F2) +#define BF_JTX_BURST_ERROR_INJECT_INFO(inst) ((inst) + 0x000000F2), 0x00000100 +#define BF_JTX_BURST_ERROR_LENGTH_INFO(inst) ((inst) + 0x000000F2), 0x00000404 + +#define REG_JTX_DL_204C_3_ADDR(inst) ((inst) + 0x000000F3) +#define BF_JTX_BURST_ERROR_LOCATION_INFO(inst) ((inst) + 0x000000F3), 0x00000B00 + +#ifdef USE_PRIVATE_BF +#define REG_JTX_DL_204H_0_ADDR(inst) ((inst) + 0x00000100) +#define BF_JTX_DL_204H_ACG_BYP_INFO(inst) ((inst) + 0x00000100), 0x00000100 +#define BF_JTX_DL_204H_BYP_ILAS_CFG_INFO(inst) ((inst) + 0x00000100), 0x00000101 +#define BF_JTX_DL_204H_CLEAR_SYNC_NE_COUNT_INFO(inst) ((inst) + 0x00000100), 0x00000102 +#define BF_JTX_DL_204H_LANE_SYNC_2SIDES_INFO(inst) ((inst) + 0x00000100), 0x00000103 +#define BF_JTX_DL_204H_ILAS_DELAY_CFG_INFO(inst) ((inst) + 0x00000100), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JTX_DL_204H_1_ADDR(inst) ((inst) + 0x00000101) +#define BF_JTX_DL_204H_INTERLEAVE_MODE_INFO(inst) ((inst) + 0x00000101), 0x00000200 +#define BF_JTX_DL_204H_PARITY_BYPASS_INFO(inst) ((inst) + 0x00000101), 0x00000102 +#define BF_JTX_DL_204H_PARITY_MODE_INFO(inst) ((inst) + 0x00000101), 0x00000103 +#define BF_JTX_DL_204H_STATE_INFO(inst) ((inst) + 0x00000101), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JTX_DL_204H_2_ADDR(inst) ((inst) + 0x00000102) +#define BF_JTX_DL_204H_KF_ILAS_CFG_INFO(inst) ((inst) + 0x00000102), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JTX_DL_204H_3_ADDR(inst) ((inst) + 0x00000103) +#define BF_JTX_DL_204H_PARITY_ODD_ENABLE_INFO(inst) ((inst) + 0x00000103), 0x00000100 +#define BF_JTX_DL_204H_SCR_CFG_INFO(inst) ((inst) + 0x00000103), 0x00000101 +#define BF_JTX_DL_204H_SYNC_N_FORCE_EN_INFO(inst) ((inst) + 0x00000103), 0x00000102 +#define BF_JTX_DL_204H_SYNC_N_FORCE_VAL_INFO(inst) ((inst) + 0x00000103), 0x00000103 +#define BF_JTX_DL_204H_TEST_MODE_INFO(inst) ((inst) + 0x00000103), 0x00000204 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JTX_DL_204H_4_ADDR(inst) ((inst) + 0x00000104) +#define BF_JTX_DL_204H_SYNC_NE_COUNT_INFO(inst) ((inst) + 0x00000104), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_JTX_PHY_IFX_0_LANE_ADDR(inst, n) ((inst) + 0x00000110 + 1 * (n)) +#define BF_JTX_BR_LOG2_RATIO_INFO(inst, n) ((inst) + 0x00000110 + 1 * (n)), 0x00000400 +#ifdef USE_PRIVATE_BF +#define BF_JTX_LANE_FIFO_WR_ENTRIES_INFO(inst, n) ((inst) + 0x00000110 + 1 * (n)), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#endif /* __ADI_APOLLO_BF_JTX_DUAL_LINK_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_jtx_qbf_txfe.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_jtx_qbf_txfe.h new file mode 100644 index 00000000000000..2cb8ef46df1506 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_jtx_qbf_txfe.h @@ -0,0 +1,250 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:21 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_JTX_QBF_TXFE_H__ +#define __ADI_APOLLO_BF_JTX_QBF_TXFE_H__ + +/*============= D E F I N E S ==============*/ +#define JTX_QBF_TXFE_0_JTX_TOP_RX_DIGITAL0 0x60618000 +#define JTX_QBF_TXFE_1_JTX_TOP_RX_DIGITAL0 0x6061C000 +#define JTX_QBF_TXFE_0_JTX_TOP_RX_DIGITAL1 0x60E18000 +#define JTX_QBF_TXFE_1_JTX_TOP_RX_DIGITAL1 0x60E1C000 + +#ifdef USE_PRIVATE_BF +#define REG_JTX_C2R_EN_ADDR(inst) ((inst) + 0x00000000) +#define BF_JTX_MODE_C2R_EN_INFO(inst) ((inst) + 0x00000000), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#define REG_PLL_STATUS_ADDR(inst) ((inst) + 0x00000001) +#define BF_JTX_PLL_LOCKED_INFO(inst) ((inst) + 0x00000001), 0x00000107 + +#define REG_JTX_QUICK_CFG_ADDR(inst) ((inst) + 0x00000002) +#define BF_JTX_MODE_INFO(inst) ((inst) + 0x00000002), 0x00000700 + +#define REG_JTX_QUICK_CFG_EN_ADDR(inst) ((inst) + 0x00000003) +#define BF_JTX_QUICK_CONFIG_EN_INFO(inst) ((inst) + 0x00000003), 0x00000100 + +#define REG_JTX_LINK_CTRL1_ADDR(inst) ((inst) + 0x00000004) +#define BF_JTX_LINK_PD_INFO(inst) ((inst) + 0x00000004), 0x00000100 +#ifdef USE_PRIVATE_BF +#define BF_JTX_LINK_STDBY_MODE_INFO(inst) ((inst) + 0x00000004), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#define REG_JTX_SER_CLK_INVERT_ADDR(inst) ((inst) + 0x00000006) +#define BF_JTX_SER_CLK_INVERT_INFO(inst) ((inst) + 0x00000006), 0x00000100 + +#ifdef USE_PRIVATE_BF +#define REG_JTX_PDWN_CTRL_ADDR(inst) ((inst) + 0x00000008) +#define BF_PD_CHIP_INFO(inst) ((inst) + 0x00000008), 0x00000100 +#define BF_STDBY_CHIP_INFO(inst) ((inst) + 0x00000008), 0x00000101 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_SYSREF_DELAY_REG_ADDR(inst) ((inst) + 0x00000009) +#define BF_SYSREF_PULSE_DELAY_CYCLES_INFO(inst) ((inst) + 0x00000009), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_RESET_CTRL_REG_ADDR(inst) ((inst) + 0x0000000A) +#ifdef USE_PRIVATE_BF +#define BF_FORCE_JTX_DIGITAL_RESET_ON_RSTEN_FORCE_EN_INFO(inst) ((inst) + 0x0000000A), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_FORCE_JTX_DIGITAL_RESET_ON_SYSREF_INFO(inst) ((inst) + 0x0000000A), 0x00000104 + +#define REG_SER_PARITY_RESET_EN1_ADDR(inst) ((inst) + 0x0000000B) +#define BF_SER_PARITY_RESET_EN_INFO(inst) ((inst) + 0x0000000B), 0x00001000 + +#define REG_SER_PARITY_RESET_EN2_ADDR(inst) ((inst) + 0x0000000C) + +#ifdef USE_PRIVATE_BF +#define REG_LCM_DIV_FORCE_EN_ADDR(inst) ((inst) + 0x0000000D) +#define BF_LCM_DIV_FORCE_EN_INFO(inst) ((inst) + 0x0000000D), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_LCM_DIV1_ADDR(inst) ((inst) + 0x0000000E) +#define BF_LCM_DIV_INFO(inst) ((inst) + 0x0000000E), 0x00001000 +#endif /* USE_PRIVATE_BF */ + +#define REG_LCM_DIV2_ADDR(inst) ((inst) + 0x0000000F) + +#ifdef USE_PRIVATE_BF +#define REG_FORCE_LINK_RESET_REG_ADDR(inst) ((inst) + 0x00000010) +#define BF_FORCE_LINK_RESET_INFO(inst) ((inst) + 0x00000010), 0x00000100 +#define BF_FORCE_LINK_DIGITAL_RESET_INFO(inst) ((inst) + 0x00000010), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#define REG_QC_MODE_STATUS_ADDR(inst) ((inst) + 0x00000011) +#define BF_JTX_INVALID_MODE_INFO(inst) ((inst) + 0x00000011), 0x00000100 + +#define REG_K_EMB_QC_OVERRIDE_ADDR(inst) ((inst) + 0x00000012) +#define BF_JTX_K_EMB_QC_OVERRIDE_INFO(inst) ((inst) + 0x00000012), 0x00000100 + +#define REG_PHASE_ESTABLISH_STATUS_ADDR(inst) ((inst) + 0x00000013) +#define BF_JTX_PHASE_ESTABLISHED_INFO(inst) ((inst) + 0x00000013), 0x00000100 + +#ifdef USE_PRIVATE_BF +#define REG_PHASE_ESTABLISH_GPIO_ADDR(inst) ((inst) + 0x00000014) +#define BF_JTX_PHASE_ESTABLISHED_GPIO_OUT_INFO(inst) ((inst) + 0x00000014), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CLKGEN_ALIGN_FALL_RST_DEASSERT_ADDR(inst) ((inst) + 0x00000015) +#define BF_CLKGEN_ALIGN_FALL_FOR_RST_DEASSERT_INFO(inst) ((inst) + 0x00000015), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#define REG_PHASE_ESTABLISH_DATA_GATING_ADDR(inst) ((inst) + 0x00000016) +#define BF_JTX_PHASE_ESTABLISHED_DATA_GATING_EN_INFO(inst) ((inst) + 0x00000016), 0x00000100 + +#define REG_PLL_REF_CLK_DIV1_REG_ADDR(inst) ((inst) + 0x00000017) +#define BF_DIVM_LCPLL_RC_RX_INFO(inst) ((inst) + 0x00000017), 0x00000200 + +#ifdef USE_PRIVATE_BF +#define REG_LMFC_CTL_ADDR(inst) ((inst) + 0x00000018) +#define BF_LMFC_OUT_DIV_INFO(inst) ((inst) + 0x00000018), 0x00000300 +#define BF_LMFC_DIV_EDGE_INFO(inst) ((inst) + 0x00000018), 0x00000104 +#define BF_LMFC_OUT_SEL_INFO(inst) ((inst) + 0x00000018), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_DIV_CLK_GEN_ASYNC_MODE_ADDR(inst) ((inst) + 0x00000019) +#define BF_ASYNC_DIV_CLK_REGEN_INFO(inst) ((inst) + 0x00000019), 0x00000300 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ASYNC_CLK_GEN_SYNC_ADDR(inst) ((inst) + 0x0000001A) +#define BF_ASYNC_DIV_CLK_OFFSET_INFO(inst) ((inst) + 0x0000001A), 0x00000400 +#define BF_ASYNC_DIV_CLK_OFFSET_ENABLE_INFO(inst) ((inst) + 0x0000001A), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_SYNC_DELAY_REG_ADDR(inst) ((inst) + 0x0000001B) +#define BF_SYNC_DELAY_COUNT_INFO(inst) ((inst) + 0x0000001B), 0x00000400 +#define BF_SYNC_DELAY_LINK_PCLK_CYCLES_ENABLE_INFO(inst) ((inst) + 0x0000001B), 0x00000106 +#define BF_SYNC_DELAY_ENABLE_INFO(inst) ((inst) + 0x0000001B), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_EXTEND_SYNC_FORCE_REG_ADDR(inst) ((inst) + 0x0000001C) +#define BF_EXTEND_SYNC_FORCE_DURING_RESYNC_INFO(inst) ((inst) + 0x0000001C), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CONV_EN_LINK1_ADDR(inst, n) ((inst) + 0x0000001D + 1 * (n)) +#define BF_CONV_EN_LINK1_INFO(inst, n) ((inst) + 0x0000001D + 1 * (n)), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#define REG_NS_OVERRIDE_ADDR(inst) ((inst) + 0x0000002D) +#define BF_JTX_NS_OVERRIDE_INFO(inst) ((inst) + 0x0000002D), 0x00000100 +#ifdef USE_PRIVATE_BF +#define BF_DDC_NS_OVERRIDE_INFO(inst) ((inst) + 0x0000002D), 0x00000101 +#endif /* USE_PRIVATE_BF */ +#ifdef USE_PRIVATE_BF +#define BF_NS_CONV_NS_OVERRIDE_INFO(inst) ((inst) + 0x0000002D), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_ASYNC_MODE_OVERRIDE_INFO(inst) ((inst) + 0x0000002D), 0x00000103 + +#ifdef USE_PRIVATE_BF +#define REG_NS_CONV_NS_ADDR(inst) ((inst) + 0x0000002E) +#define BF_NS_CONV_NS_REGMAP_INFO(inst) ((inst) + 0x0000002E), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_DDC_NS_ADDR(inst) ((inst) + 0x0000002F) +#define BF_DDC_NS_REGMAP_INFO(inst) ((inst) + 0x0000002F), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JTX_FORCE_SYNC_DELAY_EN_ADDR(inst) ((inst) + 0x00000030) +#define BF_JTX_FORCE_SYNC_DELAY_EN_INFO(inst) ((inst) + 0x00000030), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JTX_FORCE_SYNC_DELAY_COUNT_ADDR(inst) ((inst) + 0x00000031) +#define BF_JTX_FORCE_SYNC_DELAY_COUNT_INFO(inst) ((inst) + 0x00000031), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_RESET_FIRST_CLK_AFTER_RESET_ADDR(inst) ((inst) + 0x00000032) +#define BF_RST_JTX_FIRST_CLK_AFTER_RST_INFO(inst) ((inst) + 0x00000032), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#define REG_SERDES_TX_WR_SETUP_CTRL_ADDR(inst) ((inst) + 0x00000033) +#define BF_SERDES_TX_ANA_BRIDGE_WR_SETUP_CYCLES_INFO(inst) ((inst) + 0x00000033), 0x00000600 + +#define REG_SERDES_TX_WR_HOLD_CTRL_ADDR(inst) ((inst) + 0x00000034) +#define BF_SERDES_TX_ANA_BRIDGE_WR_HOLD_CYCLES_INFO(inst) ((inst) + 0x00000034), 0x00000600 + +#define REG_SERDES_TX_RD_CTRL_ADDR(inst) ((inst) + 0x00000035) +#define BF_SERDES_TX_ANA_BRIDGE_RD_CYCLES_INFO(inst) ((inst) + 0x00000035), 0x00000600 + +#ifdef USE_PRIVATE_BF +#define REG_JTX_NS_READBACK_ADDR(inst) ((inst) + 0x00000036) +#define BF_JTX_NS_READBACK_INFO(inst) ((inst) + 0x00000036), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JTX_M_READBACK_ADDR(inst) ((inst) + 0x00000037) +#define BF_JTX_M_READBACK_INFO(inst) ((inst) + 0x00000037), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JTX_L_READBACK_ADDR(inst) ((inst) + 0x00000038) +#define BF_JTX_L_READBACK_INFO(inst) ((inst) + 0x00000038), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JTX_S_READBACK_ADDR(inst) ((inst) + 0x00000039) +#define BF_JTX_S_READBACK_INFO(inst) ((inst) + 0x00000039), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JTX_F_READBACK_ADDR(inst) ((inst) + 0x0000003A) +#define BF_JTX_F_READBACK_INFO(inst) ((inst) + 0x0000003A), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JTX_NP_READBACK_ADDR(inst) ((inst) + 0x0000003B) +#define BF_JTX_NP_READBACK_INFO(inst) ((inst) + 0x0000003B), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JTX_SPECIAL_CASE_ADDR(inst) ((inst) + 0x0000003C) +#define BF_JTX_SAMPLE_CROSSBAR_EN_INFO(inst) ((inst) + 0x0000003C), 0x00000100 +#define BF_USE_NS_LINK_TOTAL_DEC_INFO(inst) ((inst) + 0x0000003C), 0x00000101 +#define BF_SWITCH_DATA_TO_16_TO_24_INFO(inst) ((inst) + 0x0000003C), 0x00000402 +#define BF_OVERRIDE_DATA_TO_16_TO_24_INFO(inst) ((inst) + 0x0000003C), 0x00000106 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JTX_K_S_BY_NS_READBACK_ADDR(inst) ((inst) + 0x0000003D) +#define BF_JTX_K_S_BY_NS_READBACK_INFO(inst) ((inst) + 0x0000003D), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JTX_ASYNC_READBACK_ADDR(inst) ((inst) + 0x0000003E) +#define BF_JTX_ASYNC_READBACK_INFO(inst) ((inst) + 0x0000003E), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_NS_CONV_NS_READBACK_ADDR(inst) ((inst) + 0x0000003F) +#define BF_NS_CONV_NS_READBACK_INFO(inst) ((inst) + 0x0000003F), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_SYSREF_DELAY_REG_EN_ADDR(inst) ((inst) + 0x00000040) +#define BF_SYSREF_PULSE_DELAY_ENABLE_INFO(inst) ((inst) + 0x00000040), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#endif /* __ADI_APOLLO_BF_JTX_QBF_TXFE_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_linearx_bmem.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_linearx_bmem.h new file mode 100644 index 00000000000000..d19642fc111291 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_linearx_bmem.h @@ -0,0 +1,180 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:19 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_LINEARX_BMEM_H__ +#define __ADI_APOLLO_BF_LINEARX_BMEM_H__ + +/*============= D E F I N E S ==============*/ +#define LINEARX_BMEM_REGMAP_RX_LINEARX_REG8_0_RX_SLICE_0_RX_DIGITAL0 0x60210000 +#define LINEARX_BMEM_REGMAP_RX_LINEARX_REG8_1_RX_SLICE_0_RX_DIGITAL0 0x60218000 +#define LINEARX_BMEM_REGMAP_RX_LINEARX_REG8_0_RX_SLICE_1_RX_DIGITAL0 0x60410000 +#define LINEARX_BMEM_REGMAP_RX_LINEARX_REG8_1_RX_SLICE_1_RX_DIGITAL0 0x60418000 +#define LINEARX_BMEM_REGMAP_RX_LINEARX_REG8_0_RX_SLICE_0_RX_DIGITAL1 0x60A10000 +#define LINEARX_BMEM_REGMAP_RX_LINEARX_REG8_1_RX_SLICE_0_RX_DIGITAL1 0x60A18000 +#define LINEARX_BMEM_REGMAP_RX_LINEARX_REG8_0_RX_SLICE_1_RX_DIGITAL1 0x60C10000 +#define LINEARX_BMEM_REGMAP_RX_LINEARX_REG8_1_RX_SLICE_1_RX_DIGITAL1 0x60C18000 +#define LINEARX_BMEM_REGMAP_TX_LINEARX_REG8_0_TX_SLICE_0_TX_DIGITAL0 0x61210000 +#define LINEARX_BMEM_REGMAP_TX_LINEARX_REG8_1_TX_SLICE_0_TX_DIGITAL0 0x61218000 +#define LINEARX_BMEM_REGMAP_TX_LINEARX_REG8_0_TX_SLICE_1_TX_DIGITAL0 0x61410000 +#define LINEARX_BMEM_REGMAP_TX_LINEARX_REG8_1_TX_SLICE_1_TX_DIGITAL0 0x61418000 +#define LINEARX_BMEM_REGMAP_TX_LINEARX_REG8_0_TX_SLICE_0_TX_DIGITAL1 0x61A10000 +#define LINEARX_BMEM_REGMAP_TX_LINEARX_REG8_1_TX_SLICE_0_TX_DIGITAL1 0x61A18000 +#define LINEARX_BMEM_REGMAP_TX_LINEARX_REG8_0_TX_SLICE_1_TX_DIGITAL1 0x61C10000 +#define LINEARX_BMEM_REGMAP_TX_LINEARX_REG8_1_TX_SLICE_1_TX_DIGITAL1 0x61C18000 + +#define REG_BMEM_CONTROL_1_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000000) +#define BF_BMEM_EN_LINEARX_BMEM_INFO(inst) ((inst) + 0x00000000), 0x00000100 +#define BF_BMEM_START_LINEARX_BMEM_INFO(inst) ((inst) + 0x00000000), 0x00000101 +#define BF_BMEM_MODE_LINEARX_BMEM_INFO(inst) ((inst) + 0x00000000), 0x00000202 +#define BF_BMEM_RESET_LINEARX_BMEM_INFO(inst) ((inst) + 0x00000000), 0x00000104 +#define BF_BMEM_SLEEP_LINEARX_BMEM_INFO(inst) ((inst) + 0x00000000), 0x00000105 +#define BF_BMEM_SHUT_DOWN_LINEARX_BMEM_INFO(inst) ((inst) + 0x00000000), 0x00000106 +#define BF_FAST_NSLOW_MODE_LINEARX_BMEM_INFO(inst) ((inst) + 0x00000000), 0x00000107 + +#define REG_BMEM_CONTROL_2_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000001) +#define BF_TRIG_MODE_LINEARX_BMEM_INFO(inst) ((inst) + 0x00000001), 0x00000100 +#define BF_TRIG_MODE_SCLR_EN_LINEARX_BMEM_INFO(inst) ((inst) + 0x00000001), 0x00000101 +#define BF_PARITY_CHECK_EN_LINEARX_BMEM_INFO(inst) ((inst) + 0x00000001), 0x00000102 +#define BF_SAMPLE_SIZE_LINEARX_BMEM_INFO(inst) ((inst) + 0x00000001), 0x00000103 +#define BF_RAMCLK_PH_DIS_LINEARX_BMEM_INFO(inst) ((inst) + 0x00000001), 0x00000104 +#define BF_BMEM_8T8R_CAP_MASK_LINEARX_BMEM_INFO(inst) ((inst) + 0x00000001), 0x00000205 +#define BF_HOP_DLY_SEL_MODE_LINEARX_BMEM_INFO(inst) ((inst) + 0x00000001), 0x00000107 + +#define REG_SAMPLE_DELAY_0_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000002) +#define BF_SAMPLE_DLY_LINEARX_BMEM_INFO(inst) ((inst) + 0x00000002), 0x00001000 + +#define REG_SAMPLE_DELAY_1_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000003) + +#define REG_HOP_DELAY0_0_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000004) +#define BF_HOP_DELAY0_LINEARX_BMEM_INFO(inst) ((inst) + 0x00000004), 0x00001000 + +#define REG_HOP_DELAY0_1_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000005) + +#define REG_HOP_DELAY1_0_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000006) +#define BF_HOP_DELAY1_LINEARX_BMEM_INFO(inst) ((inst) + 0x00000006), 0x00001000 + +#define REG_HOP_DELAY1_1_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000007) + +#define REG_HOP_DELAY2_0_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000008) +#define BF_HOP_DELAY2_LINEARX_BMEM_INFO(inst) ((inst) + 0x00000008), 0x00001000 + +#define REG_HOP_DELAY2_1_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000009) + +#define REG_HOP_DELAY3_0_LINEARX_BMEM_ADDR(inst) ((inst) + 0x0000000A) +#define BF_HOP_DELAY3_LINEARX_BMEM_INFO(inst) ((inst) + 0x0000000A), 0x00001000 + +#define REG_HOP_DELAY3_1_LINEARX_BMEM_ADDR(inst) ((inst) + 0x0000000B) + +#define REG_ST_ADDR_CPT_0_LINEARX_BMEM_ADDR(inst) ((inst) + 0x0000000C) +#define BF_ST_ADDR_CPT_LINEARX_BMEM_INFO(inst) ((inst) + 0x0000000C), 0x00000F00 + +#define REG_ST_ADDR_CPT_1_LINEARX_BMEM_ADDR(inst) ((inst) + 0x0000000D) + +#define REG_END_ADDR_CPT_0_LINEARX_BMEM_ADDR(inst) ((inst) + 0x0000000E) +#define BF_END_ADDR_CPT_LINEARX_BMEM_INFO(inst) ((inst) + 0x0000000E), 0x00000F00 + +#define REG_END_ADDR_CPT_1_LINEARX_BMEM_ADDR(inst) ((inst) + 0x0000000F) + +#define REG_ST_ADDR_AWG_0_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000010) +#define BF_ST_ADDR_AWG_LINEARX_BMEM_INFO(inst) ((inst) + 0x00000010), 0x00000F00 + +#define REG_ST_ADDR_AWG_1_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000011) + +#define REG_END_ADDR_AWG_0_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000012) +#define BF_END_ADDR_AWG_LINEARX_BMEM_INFO(inst) ((inst) + 0x00000012), 0x00000F00 + +#define REG_END_ADDR_AWG_1_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000013) + +#define REG_ST_CPTR_ON_SMPL_VAL_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000014) +#define BF_ST_CPTR_ON_SMPL_VAL_LINEARX_BMEM_INFO(inst) ((inst) + 0x00000014), 0x00000800 + +#define REG_SMPL_VAL_FOR_CPTR0_0_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000015) +#define BF_SMPL_VAL_FOR_CPTR0_LINEARX_BMEM_INFO(inst) ((inst) + 0x00000015), 0x00002000 + +#define REG_SMPL_VAL_FOR_CPTR0_1_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000016) + +#define REG_SMPL_VAL_FOR_CPTR0_2_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000017) + +#define REG_SMPL_VAL_FOR_CPTR0_3_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000018) + +#define REG_SMPL_VAL_FOR_CPTR1_0_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000019) +#define BF_SMPL_VAL_FOR_CPTR1_LINEARX_BMEM_INFO(inst) ((inst) + 0x00000019), 0x00002000 + +#define REG_SMPL_VAL_FOR_CPTR1_1_LINEARX_BMEM_ADDR(inst) ((inst) + 0x0000001A) + +#define REG_SMPL_VAL_FOR_CPTR1_2_LINEARX_BMEM_ADDR(inst) ((inst) + 0x0000001B) + +#define REG_SMPL_VAL_FOR_CPTR1_3_LINEARX_BMEM_ADDR(inst) ((inst) + 0x0000001C) + +#define REG_SMPL_VAL_FOR_CPTR2_0_LINEARX_BMEM_ADDR(inst) ((inst) + 0x0000001D) +#define BF_SMPL_VAL_FOR_CPTR2_LINEARX_BMEM_INFO(inst) ((inst) + 0x0000001D), 0x00002000 + +#define REG_SMPL_VAL_FOR_CPTR2_1_LINEARX_BMEM_ADDR(inst) ((inst) + 0x0000001E) + +#define REG_SMPL_VAL_FOR_CPTR2_2_LINEARX_BMEM_ADDR(inst) ((inst) + 0x0000001F) + +#define REG_SMPL_VAL_FOR_CPTR2_3_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000020) + +#define REG_SMPL_VAL_FOR_CPTR3_0_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000021) +#define BF_SMPL_VAL_FOR_CPTR3_LINEARX_BMEM_INFO(inst) ((inst) + 0x00000021), 0x00002000 + +#define REG_SMPL_VAL_FOR_CPTR3_1_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000022) + +#define REG_SMPL_VAL_FOR_CPTR3_2_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000023) + +#define REG_SMPL_VAL_FOR_CPTR3_3_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000024) + +#define REG_SMPL_VAL_FOR_CPTR4_0_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000025) +#define BF_SMPL_VAL_FOR_CPTR4_LINEARX_BMEM_INFO(inst) ((inst) + 0x00000025), 0x00002000 + +#define REG_SMPL_VAL_FOR_CPTR4_1_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000026) + +#define REG_SMPL_VAL_FOR_CPTR4_2_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000027) + +#define REG_SMPL_VAL_FOR_CPTR4_3_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000028) + +#define REG_SMPL_VAL_FOR_CPTR5_0_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000029) +#define BF_SMPL_VAL_FOR_CPTR5_LINEARX_BMEM_INFO(inst) ((inst) + 0x00000029), 0x00002000 + +#define REG_SMPL_VAL_FOR_CPTR5_1_LINEARX_BMEM_ADDR(inst) ((inst) + 0x0000002A) + +#define REG_SMPL_VAL_FOR_CPTR5_2_LINEARX_BMEM_ADDR(inst) ((inst) + 0x0000002B) + +#define REG_SMPL_VAL_FOR_CPTR5_3_LINEARX_BMEM_ADDR(inst) ((inst) + 0x0000002C) + +#define REG_SMPL_VAL_FOR_CPTR6_0_LINEARX_BMEM_ADDR(inst) ((inst) + 0x0000002D) +#define BF_SMPL_VAL_FOR_CPTR6_LINEARX_BMEM_INFO(inst) ((inst) + 0x0000002D), 0x00002000 + +#define REG_SMPL_VAL_FOR_CPTR6_1_LINEARX_BMEM_ADDR(inst) ((inst) + 0x0000002E) + +#define REG_SMPL_VAL_FOR_CPTR6_2_LINEARX_BMEM_ADDR(inst) ((inst) + 0x0000002F) + +#define REG_SMPL_VAL_FOR_CPTR6_3_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000030) + +#define REG_SMPL_VAL_FOR_CPTR7_0_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000031) +#define BF_SMPL_VAL_FOR_CPTR7_LINEARX_BMEM_INFO(inst) ((inst) + 0x00000031), 0x00002000 + +#define REG_SMPL_VAL_FOR_CPTR7_1_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000032) + +#define REG_SMPL_VAL_FOR_CPTR7_2_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000033) + +#define REG_SMPL_VAL_FOR_CPTR7_3_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000034) + +#define REG_BMEM_STATUS_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000035) +#define BF_CAPTURE_TRIG_PHASE_LINEARX_BMEM_INFO(inst) ((inst) + 0x00000035), 0x00000600 +#define BF_FULL_IRQ_LINEARX_BMEM_INFO(inst) ((inst) + 0x00000035), 0x00000106 +#define BF_PARITY_ERR_LINEARX_BMEM_INFO(inst) ((inst) + 0x00000035), 0x00000107 + +#endif /* __ADI_APOLLO_BF_LINEARX_BMEM_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_linearx_corr.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_linearx_corr.h new file mode 100644 index 00000000000000..fcfe02c7ee8d18 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_linearx_corr.h @@ -0,0 +1,110 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:19 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_LINEARX_CORR_H__ +#define __ADI_APOLLO_BF_LINEARX_CORR_H__ + +/*============= D E F I N E S ==============*/ +#define LINEARX_CORR_RX_LINEARX_REG32_0_RX_SLICE_0_RX_DIGITAL0 0x60220100 +#define LINEARX_CORR_RX_LINEARX_REG32_1_RX_SLICE_0_RX_DIGITAL0 0x60228100 +#define LINEARX_CORR_RX_LINEARX_REG32_0_RX_SLICE_1_RX_DIGITAL0 0x60420100 +#define LINEARX_CORR_RX_LINEARX_REG32_1_RX_SLICE_1_RX_DIGITAL0 0x60428100 +#define LINEARX_CORR_RX_LINEARX_REG32_0_RX_SLICE_0_RX_DIGITAL1 0x60A20100 +#define LINEARX_CORR_RX_LINEARX_REG32_1_RX_SLICE_0_RX_DIGITAL1 0x60A28100 +#define LINEARX_CORR_RX_LINEARX_REG32_0_RX_SLICE_1_RX_DIGITAL1 0x60C20100 +#define LINEARX_CORR_RX_LINEARX_REG32_1_RX_SLICE_1_RX_DIGITAL1 0x60C28100 +#define LINEARX_CORR_TX_LINEARX_REG32_0_TX_SLICE_0_TX_DIGITAL0 0x61220100 +#define LINEARX_CORR_TX_LINEARX_REG32_1_TX_SLICE_0_TX_DIGITAL0 0x61228100 +#define LINEARX_CORR_TX_LINEARX_REG32_0_TX_SLICE_1_TX_DIGITAL0 0x61420100 +#define LINEARX_CORR_TX_LINEARX_REG32_1_TX_SLICE_1_TX_DIGITAL0 0x61428100 +#define LINEARX_CORR_TX_LINEARX_REG32_0_TX_SLICE_0_TX_DIGITAL1 0x61A20100 +#define LINEARX_CORR_TX_LINEARX_REG32_1_TX_SLICE_0_TX_DIGITAL1 0x61A28100 +#define LINEARX_CORR_TX_LINEARX_REG32_0_TX_SLICE_1_TX_DIGITAL1 0x61C20100 +#define LINEARX_CORR_TX_LINEARX_REG32_1_TX_SLICE_1_TX_DIGITAL1 0x61C28100 + +#define REG_LINEARX_CORR_CONTROL_ADDR(inst) ((inst) + 0x00000000) +#define BF_NO_INTERP_CORRECTION_INFO(inst) ((inst) + 0x00000000), 0x00000100 +#define BF_INTERP_TYPE_EN_INFO(inst) ((inst) + 0x00000000), 0x00000101 +#define BF_HAMMERSTEIN_EN_INFO(inst) ((inst) + 0x00000000), 0x00000102 +#define BF_INTERP_NOM_6B_OUT_LP_INFO(inst) ((inst) + 0x00000000), 0x00000103 +#define BF_INTERP_NOM_6B_OUT_BP_INFO(inst) ((inst) + 0x00000000), 0x00000104 +#define BF_CROSSTERM_EN_INFO(inst) ((inst) + 0x00000000), 0x0000010D +#define BF_CROSSTERM_DELAY_INFO(inst) ((inst) + 0x00000000), 0x00000C10 +#define BF_LINEARX_OVR_OPTION_INFO(inst) ((inst) + 0x00000000), 0x0000021C +#define BF_TAP_ADJUST_INFO(inst) ((inst) + 0x00000000), 0x0000021E + +#define REG_LINEARX_ACAUSAL_TAPS_ADDR(inst) ((inst) + 0x00000004) +#define BF_ACAUSAL_TAPS_INFO(inst) ((inst) + 0x00000004), 0x00000400 +#define BF_DISABLE_ACAUSAL_TAPS_CSRAM_INFO(inst) ((inst) + 0x00000004), 0x00000204 + +#define REG_LINEARX_AMP_THRESH_ADDR(inst) ((inst) + 0x00000008) +#define BF_LINEARX_AMP_THRESH_EN_INFO(inst) ((inst) + 0x00000008), 0x00000100 +#define BF_LINEARX_AMP_THRESH_DITHER_EN_INFO(inst) ((inst) + 0x00000008), 0x00000101 +#define BF_LINEARX_AMP_THRESH_CLK_GATING_EN_INFO(inst) ((inst) + 0x00000008), 0x00000102 +#define BF_LINEARX_AMP_THRESH_FLUSH_PIPELINE_EN_INFO(inst) ((inst) + 0x00000008), 0x00000103 +#define BF_LINEARX_AMP_THRESH_DITHER_SHIFT_INFO(inst) ((inst) + 0x00000008), 0x00000204 + +#define REG_LINEARX_AMP_THRESH2_ADDR(inst) ((inst) + 0x0000000C) +#define BF_CAL_DWELL_TIME_INFO(inst) ((inst) + 0x0000000C), 0x00001000 +#define BF_LINEARX_AMP_THRESH_INFO(inst) ((inst) + 0x0000000C), 0x00000B10 + +#define REG_LINEARX_OFFSET_OVR_ADDR(inst) ((inst) + 0x00000010) +#define BF_LINEARX_OFFSET_OVR_CNT_INFO(inst) ((inst) + 0x00000010), 0x00001000 + +#define REG_LINEARX_OFFSET_MEASUREMENT_ADDR(inst) ((inst) + 0x00000014) +#define BF_LINEARX_OFFSET_MEASUREMENT_INFO(inst) ((inst) + 0x00000014), 0x00000B00 +#define BF_LINEARX_OFFSET_STATUS_IRQ_INFO(inst) ((inst) + 0x00000014), 0x0000010B + +#define REG_LINEARX_OFFSET_START_ADDR(inst) ((inst) + 0x00000018) +#define BF_LINEARX_OFFSET_CAL_START_INFO(inst) ((inst) + 0x00000018), 0x00000100 + +#define REG_LINEARX_OFFSET_CLR_ADDR(inst) ((inst) + 0x0000001C) +#define BF_LINEARX_OFFSET_IRQ_CLEAR_INFO(inst) ((inst) + 0x0000001C), 0x00000100 + +#define REG_LINEARX_OFFSET_CAL_ADDR(inst) ((inst) + 0x00000020) +#define BF_LINEARX_OFFSET_CAL_DEC_RATE_INFO(inst) ((inst) + 0x00000020), 0x00000D00 +#define BF_LINEARX_OFFSET_CAL_SHIFT_EXP_INFO(inst) ((inst) + 0x00000020), 0x0000040D +#define BF_LINEARX_OFFSET_CAL_EN_INFO(inst) ((inst) + 0x00000020), 0x00000111 +#define BF_LINEARX_OFFSET_IRQ_EN_INFO(inst) ((inst) + 0x00000020), 0x00000112 + +#define REG_LINEARX_OFFSET_CORR_COEF_ADDR(inst) ((inst) + 0x00000024) +#define BF_LINEARX_OFFSET_CANCELLATION_COEF_INFO(inst) ((inst) + 0x00000024), 0x00000900 + +#define REG_LINEARX_DEBUG_ADDR(inst) ((inst) + 0x00000028) +#define BF_DEBUG_MODE_HSRAM_CSRAM_EN_INFO(inst) ((inst) + 0x00000028), 0x00000200 +#define BF_DEBUG_MODE_CSRAM_NUM_INFO(inst) ((inst) + 0x00000028), 0x00000202 +#define BF_DEBUG_MODE_POLY_INFO(inst) ((inst) + 0x00000028), 0x00000204 +#define BF_DEBUG_MODE_INFO(inst) ((inst) + 0x00000028), 0x00000306 + +#define REG_LFSR_CONTROLS_ADDR(inst) ((inst) + 0x0000002C) +#define BF_ADDR_GEN_LFSR_EN_INFO(inst) ((inst) + 0x0000002C), 0x00000100 +#define BF_ADDR_GEN_LFSR_RESTART_INFO(inst) ((inst) + 0x0000002C), 0x00000101 +#define BF_DIST_REM_LFSR_EN_INFO(inst) ((inst) + 0x0000002C), 0x00000102 +#define BF_DIST_REM_LFSR_RESTART_INFO(inst) ((inst) + 0x0000002C), 0x00000103 +#define BF_THRESHOLD_LFSR_EN_INFO(inst) ((inst) + 0x0000002C), 0x00000104 +#define BF_THRESHOLD_LFSR_RESTART_INFO(inst) ((inst) + 0x0000002C), 0x00000105 +#define BF_REQUANT_LFSR_EN_INFO(inst) ((inst) + 0x0000002C), 0x00000106 +#define BF_REQUANT_LFSR_RESTART_INFO(inst) ((inst) + 0x0000002C), 0x00000107 + +#define REG_TRANSFER_ADDR(inst) ((inst) + 0x00000030) +#define BF_TRANSFER_OFFSET_CORR_INFO(inst) ((inst) + 0x00000030), 0x00000100 +#define BF_TRANSFER_OFFSET_CORR_IN_INFO(inst) ((inst) + 0x00000030), 0x00000101 +#define BF_READ_SEL_OFFSET_CORR_INFO(inst) ((inst) + 0x00000030), 0x00000104 +#define BF_READ_SEL_OFFSET_CORR_IN_INFO(inst) ((inst) + 0x00000030), 0x00000105 + +#define REG_LINEARX_INPUT_OFFSET_CORR_COEF_ADDR(inst) ((inst) + 0x00000034) +#define BF_LINEARX_OFFSET_CANCELLATION_COEF_IN_INFO(inst) ((inst) + 0x00000034), 0x00001000 + +#endif /* __ADI_APOLLO_BF_LINEARX_CORR_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_linearx_lut_mem_ctrl.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_linearx_lut_mem_ctrl.h new file mode 100644 index 00000000000000..ef7bff9da4b8f0 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_linearx_lut_mem_ctrl.h @@ -0,0 +1,281 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:19 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_LINEARX_LUT_MEM_CTRL_H__ +#define __ADI_APOLLO_BF_LINEARX_LUT_MEM_CTRL_H__ + +/*============= D E F I N E S ==============*/ +#define LINEARX_LUT_MEM_CTRL_RX_LINEARX_REG32_0_RX_SLICE_0_RX_DIGITAL0 0x60220B00 +#define LINEARX_LUT_MEM_CTRL_RX_LINEARX_REG32_1_RX_SLICE_0_RX_DIGITAL0 0x60228B00 +#define LINEARX_LUT_MEM_CTRL_RX_LINEARX_REG32_0_RX_SLICE_1_RX_DIGITAL0 0x60420B00 +#define LINEARX_LUT_MEM_CTRL_RX_LINEARX_REG32_1_RX_SLICE_1_RX_DIGITAL0 0x60428B00 +#define LINEARX_LUT_MEM_CTRL_RX_LINEARX_REG32_0_RX_SLICE_0_RX_DIGITAL1 0x60A20B00 +#define LINEARX_LUT_MEM_CTRL_RX_LINEARX_REG32_1_RX_SLICE_0_RX_DIGITAL1 0x60A28B00 +#define LINEARX_LUT_MEM_CTRL_RX_LINEARX_REG32_0_RX_SLICE_1_RX_DIGITAL1 0x60C20B00 +#define LINEARX_LUT_MEM_CTRL_RX_LINEARX_REG32_1_RX_SLICE_1_RX_DIGITAL1 0x60C28B00 +#define LINEARX_LUT_MEM_CTRL_TX_LINEARX_REG32_0_TX_SLICE_0_TX_DIGITAL0 0x61220B00 +#define LINEARX_LUT_MEM_CTRL_TX_LINEARX_REG32_1_TX_SLICE_0_TX_DIGITAL0 0x61228B00 +#define LINEARX_LUT_MEM_CTRL_TX_LINEARX_REG32_0_TX_SLICE_1_TX_DIGITAL0 0x61420B00 +#define LINEARX_LUT_MEM_CTRL_TX_LINEARX_REG32_1_TX_SLICE_1_TX_DIGITAL0 0x61428B00 +#define LINEARX_LUT_MEM_CTRL_TX_LINEARX_REG32_0_TX_SLICE_0_TX_DIGITAL1 0x61A20B00 +#define LINEARX_LUT_MEM_CTRL_TX_LINEARX_REG32_1_TX_SLICE_0_TX_DIGITAL1 0x61A28B00 +#define LINEARX_LUT_MEM_CTRL_TX_LINEARX_REG32_0_TX_SLICE_1_TX_DIGITAL1 0x61C20B00 +#define LINEARX_LUT_MEM_CTRL_TX_LINEARX_REG32_1_TX_SLICE_1_TX_DIGITAL1 0x61C28B00 + +#define REG_LINEARX_HSRAM_MUX_SEL0_ADDR(inst) ((inst) + 0x00000000) +#define BF_HSRAM_MUX_SEL0_INFO(inst) ((inst) + 0x00000000), 0x00000300 +#define BF_HSRAM_MUX_SEL1_INFO(inst) ((inst) + 0x00000000), 0x00000304 +#define BF_HSRAM_MUX_SEL2_INFO(inst) ((inst) + 0x00000000), 0x00000308 +#define BF_HSRAM_MUX_SEL3_INFO(inst) ((inst) + 0x00000000), 0x0000030C +#define BF_HSRAM_MUX_SEL4_INFO(inst) ((inst) + 0x00000000), 0x00000310 +#define BF_HSRAM_MUX_SEL5_INFO(inst) ((inst) + 0x00000000), 0x00000314 +#define BF_HSRAM_MUX_SEL6_INFO(inst) ((inst) + 0x00000000), 0x00000318 +#define BF_HSRAM_MUX_SEL7_INFO(inst) ((inst) + 0x00000000), 0x0000031C + +#define REG_LINEARX_HSRAM_MUX_SEL1_ADDR(inst) ((inst) + 0x00000004) +#define BF_HSRAM_MUX_SEL8_INFO(inst) ((inst) + 0x00000004), 0x00000300 +#define BF_HSRAM_MUX_SEL9_INFO(inst) ((inst) + 0x00000004), 0x00000304 +#define BF_HSRAM_MUX_SEL10_INFO(inst) ((inst) + 0x00000004), 0x00000308 +#define BF_HSRAM_MUX_SEL11_INFO(inst) ((inst) + 0x00000004), 0x0000030C +#define BF_HSRAM_MUX_SEL12_INFO(inst) ((inst) + 0x00000004), 0x00000310 +#define BF_HSRAM_MUX_SEL13_INFO(inst) ((inst) + 0x00000004), 0x00000314 +#define BF_HSRAM_MUX_SEL14_INFO(inst) ((inst) + 0x00000004), 0x00000318 +#define BF_HSRAM_MUX_SEL15_INFO(inst) ((inst) + 0x00000004), 0x0000031C + +#define REG_LINEARX_HSRAM_MUX_SEL2_ADDR(inst) ((inst) + 0x00000008) +#define BF_UPDATE_HSRAM_MUX_SEL0_INFO(inst) ((inst) + 0x00000008), 0x00000300 +#define BF_UPDATE_HSRAM_MUX_SEL1_INFO(inst) ((inst) + 0x00000008), 0x00000304 + +#define REG_LINEARX_CSRAM_MUX_SEL0_ADDR(inst) ((inst) + 0x00000010) +#define BF_CSRAM_MUX_SEL0_INFO(inst) ((inst) + 0x00000010), 0x00000300 +#define BF_CSRAM_MUX_SEL1_INFO(inst) ((inst) + 0x00000010), 0x00000304 +#define BF_CSRAM_MUX_SEL2_INFO(inst) ((inst) + 0x00000010), 0x00000308 +#define BF_CSRAM_MUX_SEL3_INFO(inst) ((inst) + 0x00000010), 0x0000030C +#define BF_CSRAM_MUX_SEL4_INFO(inst) ((inst) + 0x00000010), 0x00000310 +#define BF_CSRAM_MUX_SEL5_INFO(inst) ((inst) + 0x00000010), 0x00000314 +#define BF_CSRAM_MUX_SEL6_INFO(inst) ((inst) + 0x00000010), 0x00000318 +#define BF_CSRAM_MUX_SEL7_INFO(inst) ((inst) + 0x00000010), 0x0000031C + +#define REG_LINEARX_CSRAM_MUX_SEL1_ADDR(inst) ((inst) + 0x00000014) +#define BF_CSRAM_MUX_SEL8_INFO(inst) ((inst) + 0x00000014), 0x00000300 +#define BF_CSRAM_MUX_SEL9_INFO(inst) ((inst) + 0x00000014), 0x00000304 +#define BF_CSRAM_MUX_SEL10_INFO(inst) ((inst) + 0x00000014), 0x00000308 +#define BF_CSRAM_MUX_SEL11_INFO(inst) ((inst) + 0x00000014), 0x0000030C +#define BF_CSRAM_MUX_SEL12_INFO(inst) ((inst) + 0x00000014), 0x00000310 +#define BF_CSRAM_MUX_SEL13_INFO(inst) ((inst) + 0x00000014), 0x00000314 +#define BF_CSRAM_MUX_SEL14_INFO(inst) ((inst) + 0x00000014), 0x00000318 +#define BF_CSRAM_MUX_SEL15_INFO(inst) ((inst) + 0x00000014), 0x0000031C + +#define REG_LINEARX_CSRAM_MUX_SEL2_ADDR(inst) ((inst) + 0x00000018) +#define BF_UPDATE_CSRAM_MUX_SEL0_INFO(inst) ((inst) + 0x00000018), 0x00000300 +#define BF_UPDATE_CSRAM_MUX_SEL1_INFO(inst) ((inst) + 0x00000018), 0x00000304 + +#define REG_LINEARX_PATH_MUX_SEL0_ADDR(inst) ((inst) + 0x00000020) +#define BF_HSRAM_PATH_MUX_SEL0_INFO(inst) ((inst) + 0x00000020), 0x00000100 +#define BF_HSRAM_PATH_MUX_SEL1_INFO(inst) ((inst) + 0x00000020), 0x00000101 +#define BF_HSRAM_PATH_MUX_SEL2_INFO(inst) ((inst) + 0x00000020), 0x00000102 +#define BF_HSRAM_PATH_MUX_SEL3_INFO(inst) ((inst) + 0x00000020), 0x00000103 +#define BF_HSRAM_PATH_MUX_SEL4_INFO(inst) ((inst) + 0x00000020), 0x00000104 +#define BF_HSRAM_PATH_MUX_SEL5_INFO(inst) ((inst) + 0x00000020), 0x00000105 +#define BF_HSRAM_PATH_MUX_SEL6_INFO(inst) ((inst) + 0x00000020), 0x00000106 +#define BF_HSRAM_PATH_MUX_SEL7_INFO(inst) ((inst) + 0x00000020), 0x00000107 +#define BF_HSRAM_PATH_MUX_SEL8_INFO(inst) ((inst) + 0x00000020), 0x00000108 +#define BF_HSRAM_PATH_MUX_SEL9_INFO(inst) ((inst) + 0x00000020), 0x00000109 +#define BF_HSRAM_PATH_MUX_SEL10_INFO(inst) ((inst) + 0x00000020), 0x0000010A +#define BF_HSRAM_PATH_MUX_SEL11_INFO(inst) ((inst) + 0x00000020), 0x0000010B +#define BF_HSRAM_PATH_MUX_SEL12_INFO(inst) ((inst) + 0x00000020), 0x0000010C +#define BF_HSRAM_PATH_MUX_SEL13_INFO(inst) ((inst) + 0x00000020), 0x0000010D +#define BF_HSRAM_PATH_MUX_SEL14_INFO(inst) ((inst) + 0x00000020), 0x0000010E +#define BF_HSRAM_PATH_MUX_SEL15_INFO(inst) ((inst) + 0x00000020), 0x0000010F + +#define REG_LINEARX_PATH_MUX_SEL1_ADDR(inst) ((inst) + 0x00000024) +#define BF_CSRAM_PATH_MUX_SEL0_INFO(inst) ((inst) + 0x00000024), 0x00000100 +#define BF_CSRAM_PATH_MUX_SEL1_INFO(inst) ((inst) + 0x00000024), 0x00000101 +#define BF_CSRAM_PATH_MUX_SEL2_INFO(inst) ((inst) + 0x00000024), 0x00000102 +#define BF_CSRAM_PATH_MUX_SEL3_INFO(inst) ((inst) + 0x00000024), 0x00000103 +#define BF_CSRAM_PATH_MUX_SEL4_INFO(inst) ((inst) + 0x00000024), 0x00000104 +#define BF_CSRAM_PATH_MUX_SEL5_INFO(inst) ((inst) + 0x00000024), 0x00000105 +#define BF_CSRAM_PATH_MUX_SEL6_INFO(inst) ((inst) + 0x00000024), 0x00000106 +#define BF_CSRAM_PATH_MUX_SEL7_INFO(inst) ((inst) + 0x00000024), 0x00000107 +#define BF_CSRAM_PATH_MUX_SEL8_INFO(inst) ((inst) + 0x00000024), 0x00000108 +#define BF_CSRAM_PATH_MUX_SEL9_INFO(inst) ((inst) + 0x00000024), 0x00000109 +#define BF_CSRAM_PATH_MUX_SEL10_INFO(inst) ((inst) + 0x00000024), 0x0000010A +#define BF_CSRAM_PATH_MUX_SEL11_INFO(inst) ((inst) + 0x00000024), 0x0000010B +#define BF_CSRAM_PATH_MUX_SEL12_INFO(inst) ((inst) + 0x00000024), 0x0000010C +#define BF_CSRAM_PATH_MUX_SEL13_INFO(inst) ((inst) + 0x00000024), 0x0000010D +#define BF_CSRAM_PATH_MUX_SEL14_INFO(inst) ((inst) + 0x00000024), 0x0000010E +#define BF_CSRAM_PATH_MUX_SEL15_INFO(inst) ((inst) + 0x00000024), 0x0000010F + +#define REG_LINEARX_HSRAM_SD_ADDR(inst) ((inst) + 0x00000030) +#define BF_HSRAM_SD_INFO(inst) ((inst) + 0x00000030), 0x00001200 + +#define REG_LINEARX_HSRAM_SLP_ADDR(inst) ((inst) + 0x00000034) +#define BF_HSRAM_SLP_INFO(inst) ((inst) + 0x00000034), 0x00001200 + +#define REG_LINEARX_HSRAM_DSLP_ADDR(inst) ((inst) + 0x00000038) +#define BF_HSRAM_DSLP_INFO(inst) ((inst) + 0x00000038), 0x00001200 + +#define REG_LINEARX_CSRAM_SD0_ADDR(inst) ((inst) + 0x00000040) +#define BF_CSRAM_SD_INST0_INFO(inst) ((inst) + 0x00000040), 0x00001200 + +#define REG_LINEARX_CSRAM_SD1_ADDR(inst) ((inst) + 0x00000044) +#define BF_CSRAM_SD_INST1_INFO(inst) ((inst) + 0x00000044), 0x00001200 + +#define REG_LINEARX_CSRAM_SD2_ADDR(inst) ((inst) + 0x00000048) +#define BF_CSRAM_SD_INST2_INFO(inst) ((inst) + 0x00000048), 0x00001200 + +#define REG_LINEARX_CSRAM_SLP0_ADDR(inst) ((inst) + 0x00000050) +#define BF_CSRAM_SLP_INST0_INFO(inst) ((inst) + 0x00000050), 0x00001200 + +#define REG_LINEARX_CSRAM_SLP1_ADDR(inst) ((inst) + 0x00000054) +#define BF_CSRAM_SLP_INST1_INFO(inst) ((inst) + 0x00000054), 0x00001200 + +#define REG_LINEARX_CSRAM_SLP2_ADDR(inst) ((inst) + 0x00000058) +#define BF_CSRAM_SLP_INST2_INFO(inst) ((inst) + 0x00000058), 0x00001200 + +#define REG_LINEARX_CSRAM_DSLP0_ADDR(inst) ((inst) + 0x00000060) +#define BF_CSRAM_DSLP_INST0_INFO(inst) ((inst) + 0x00000060), 0x00001200 + +#define REG_LINEARX_CSRAM_DSLP1_ADDR(inst) ((inst) + 0x00000064) +#define BF_CSRAM_DSLP_INST1_INFO(inst) ((inst) + 0x00000064), 0x00001200 + +#define REG_LINEARX_CSRAM_DSLP2_ADDR(inst) ((inst) + 0x00000068) +#define BF_CSRAM_DSLP_INST2_INFO(inst) ((inst) + 0x00000068), 0x00001200 + +#define REG_LINEARX_SRAM_PARITY_CFG_ADDR(inst) ((inst) + 0x00000070) +#define BF_HSRAM_EN_PARITY_CHK_INFO(inst) ((inst) + 0x00000070), 0x00000100 +#define BF_CSRAM_EN_PARITY_CHK_INFO(inst) ((inst) + 0x00000070), 0x00000101 +#define BF_HSRAM_EN_PARITY_RB_INFO(inst) ((inst) + 0x00000070), 0x00000102 +#define BF_CSRAM_EN_PARITY_RB_INFO(inst) ((inst) + 0x00000070), 0x00000103 +#define BF_HSRAM_EN_PARITY_ERR_IRQ_INFO(inst) ((inst) + 0x00000070), 0x00000104 +#define BF_CSRAM_EN_PARITY_ERR_IRQ_INFO(inst) ((inst) + 0x00000070), 0x00000105 + +#define REG_LINEARX_SRAM_PARITY_ERR_ADDR(inst) ((inst) + 0x00000074) +#define BF_HSRAM_PARITY_ERR_IRQ_INFO(inst) ((inst) + 0x00000074), 0x00000100 +#define BF_CSRAM_PARITY_ERR_IRQ_INFO(inst) ((inst) + 0x00000074), 0x00000101 + +#define REG_LINEARX_HSRAM_PARITY_ERR0_ADDR(inst) ((inst) + 0x00000080) +#define BF_HSRAM0_PARITY_ERR_INFO(inst) ((inst) + 0x00000080), 0x00000400 +#define BF_HSRAM1_PARITY_ERR_INFO(inst) ((inst) + 0x00000080), 0x00000404 +#define BF_HSRAM2_PARITY_ERR_INFO(inst) ((inst) + 0x00000080), 0x00000408 +#define BF_HSRAM3_PARITY_ERR_INFO(inst) ((inst) + 0x00000080), 0x0000040C +#define BF_HSRAM4_PARITY_ERR_INFO(inst) ((inst) + 0x00000080), 0x00000410 +#define BF_HSRAM5_PARITY_ERR_INFO(inst) ((inst) + 0x00000080), 0x00000414 +#define BF_HSRAM6_PARITY_ERR_INFO(inst) ((inst) + 0x00000080), 0x00000418 +#define BF_HSRAM7_PARITY_ERR_INFO(inst) ((inst) + 0x00000080), 0x0000041C + +#define REG_LINEARX_HSRAM_PARITY_ERR1_ADDR(inst) ((inst) + 0x00000084) +#define BF_HSRAM8_PARITY_ERR_INFO(inst) ((inst) + 0x00000084), 0x00000400 +#define BF_HSRAM9_PARITY_ERR_INFO(inst) ((inst) + 0x00000084), 0x00000404 +#define BF_HSRAM10_PARITY_ERR_INFO(inst) ((inst) + 0x00000084), 0x00000408 +#define BF_HSRAM11_PARITY_ERR_INFO(inst) ((inst) + 0x00000084), 0x0000040C +#define BF_HSRAM12_PARITY_ERR_INFO(inst) ((inst) + 0x00000084), 0x00000410 +#define BF_HSRAM13_PARITY_ERR_INFO(inst) ((inst) + 0x00000084), 0x00000414 +#define BF_HSRAM14_PARITY_ERR_INFO(inst) ((inst) + 0x00000084), 0x00000418 +#define BF_HSRAM15_PARITY_ERR_INFO(inst) ((inst) + 0x00000084), 0x0000041C + +#define REG_LINEARX_HSRAM_PARITY_ERR2_ADDR(inst) ((inst) + 0x00000088) +#define BF_UPDATE_HSRAM0_PARITY_ERR_INFO(inst) ((inst) + 0x00000088), 0x00000400 +#define BF_UPDATE_HSRAM1_PARITY_ERR_INFO(inst) ((inst) + 0x00000088), 0x00000404 + +#define REG_LINEARX_CSRAM_PARITY_ERR0_ADDR(inst) ((inst) + 0x00000090) +#define BF_CSRAM0_INST0_PARITY_ERR_INFO(inst) ((inst) + 0x00000090), 0x00000400 +#define BF_CSRAM1_INST0_PARITY_ERR_INFO(inst) ((inst) + 0x00000090), 0x00000404 +#define BF_CSRAM2_INST0_PARITY_ERR_INFO(inst) ((inst) + 0x00000090), 0x00000408 +#define BF_CSRAM3_INST0_PARITY_ERR_INFO(inst) ((inst) + 0x00000090), 0x0000040C +#define BF_CSRAM4_INST0_PARITY_ERR_INFO(inst) ((inst) + 0x00000090), 0x00000410 +#define BF_CSRAM5_INST0_PARITY_ERR_INFO(inst) ((inst) + 0x00000090), 0x00000414 +#define BF_CSRAM6_INST0_PARITY_ERR_INFO(inst) ((inst) + 0x00000090), 0x00000418 +#define BF_CSRAM7_INST0_PARITY_ERR_INFO(inst) ((inst) + 0x00000090), 0x0000041C + +#define REG_LINEARX_CSRAM_PARITY_ERR1_ADDR(inst) ((inst) + 0x00000094) +#define BF_CSRAM8_INST0_PARITY_ERR_INFO(inst) ((inst) + 0x00000094), 0x00000400 +#define BF_CSRAM9_INST0_PARITY_ERR_INFO(inst) ((inst) + 0x00000094), 0x00000404 +#define BF_CSRAM10_INST0_PARITY_ERR_INFO(inst) ((inst) + 0x00000094), 0x00000408 +#define BF_CSRAM11_INST0_PARITY_ERR_INFO(inst) ((inst) + 0x00000094), 0x0000040C +#define BF_CSRAM12_INST0_PARITY_ERR_INFO(inst) ((inst) + 0x00000094), 0x00000410 +#define BF_CSRAM13_INST0_PARITY_ERR_INFO(inst) ((inst) + 0x00000094), 0x00000414 +#define BF_CSRAM14_INST0_PARITY_ERR_INFO(inst) ((inst) + 0x00000094), 0x00000418 +#define BF_CSRAM15_INST0_PARITY_ERR_INFO(inst) ((inst) + 0x00000094), 0x0000041C + +#define REG_LINEARX_CSRAM_PARITY_ERR2_ADDR(inst) ((inst) + 0x00000098) +#define BF_UPDATE_CSRAM0_INST0_PARITY_ERR_INFO(inst) ((inst) + 0x00000098), 0x00000400 +#define BF_UPDATE_CSRAM1_INST0_PARITY_ERR_INFO(inst) ((inst) + 0x00000098), 0x00000404 + +#define REG_LINEARX_CSRAM_PARITY_ERR3_ADDR(inst) ((inst) + 0x000000A0) +#define BF_CSRAM0_INST1_PARITY_ERR_INFO(inst) ((inst) + 0x000000A0), 0x00000400 +#define BF_CSRAM1_INST1_PARITY_ERR_INFO(inst) ((inst) + 0x000000A0), 0x00000404 +#define BF_CSRAM2_INST1_PARITY_ERR_INFO(inst) ((inst) + 0x000000A0), 0x00000408 +#define BF_CSRAM3_INST1_PARITY_ERR_INFO(inst) ((inst) + 0x000000A0), 0x0000040C +#define BF_CSRAM4_INST1_PARITY_ERR_INFO(inst) ((inst) + 0x000000A0), 0x00000410 +#define BF_CSRAM5_INST1_PARITY_ERR_INFO(inst) ((inst) + 0x000000A0), 0x00000414 +#define BF_CSRAM6_INST1_PARITY_ERR_INFO(inst) ((inst) + 0x000000A0), 0x00000418 +#define BF_CSRAM7_INST1_PARITY_ERR_INFO(inst) ((inst) + 0x000000A0), 0x0000041C + +#define REG_LINEARX_CSRAM_PARITY_ERR4_ADDR(inst) ((inst) + 0x000000A4) +#define BF_CSRAM8_INST1_PARITY_ERR_INFO(inst) ((inst) + 0x000000A4), 0x00000400 +#define BF_CSRAM9_INST1_PARITY_ERR_INFO(inst) ((inst) + 0x000000A4), 0x00000404 +#define BF_CSRAM10_INST1_PARITY_ERR_INFO(inst) ((inst) + 0x000000A4), 0x00000408 +#define BF_CSRAM11_INST1_PARITY_ERR_INFO(inst) ((inst) + 0x000000A4), 0x0000040C +#define BF_CSRAM12_INST1_PARITY_ERR_INFO(inst) ((inst) + 0x000000A4), 0x00000410 +#define BF_CSRAM13_INST1_PARITY_ERR_INFO(inst) ((inst) + 0x000000A4), 0x00000414 +#define BF_CSRAM14_INST1_PARITY_ERR_INFO(inst) ((inst) + 0x000000A4), 0x00000418 +#define BF_CSRAM15_INST1_PARITY_ERR_INFO(inst) ((inst) + 0x000000A4), 0x0000041C + +#define REG_LINEARX_CSRAM_PARITY_ERR5_ADDR(inst) ((inst) + 0x000000A8) +#define BF_UPDATE_CSRAM0_INST1_PARITY_ERR_INFO(inst) ((inst) + 0x000000A8), 0x00000400 +#define BF_UPDATE_CSRAM1_INST1_PARITY_ERR_INFO(inst) ((inst) + 0x000000A8), 0x00000404 + +#define REG_LINEARX_CSRAM_PARITY_ERR6_ADDR(inst) ((inst) + 0x000000B0) +#define BF_CSRAM0_INST2_PARITY_ERR_INFO(inst) ((inst) + 0x000000B0), 0x00000400 +#define BF_CSRAM1_INST2_PARITY_ERR_INFO(inst) ((inst) + 0x000000B0), 0x00000404 +#define BF_CSRAM2_INST2_PARITY_ERR_INFO(inst) ((inst) + 0x000000B0), 0x00000408 +#define BF_CSRAM3_INST2_PARITY_ERR_INFO(inst) ((inst) + 0x000000B0), 0x0000040C +#define BF_CSRAM4_INST2_PARITY_ERR_INFO(inst) ((inst) + 0x000000B0), 0x00000410 +#define BF_CSRAM5_INST2_PARITY_ERR_INFO(inst) ((inst) + 0x000000B0), 0x00000414 +#define BF_CSRAM6_INST2_PARITY_ERR_INFO(inst) ((inst) + 0x000000B0), 0x00000418 +#define BF_CSRAM7_INST2_PARITY_ERR_INFO(inst) ((inst) + 0x000000B0), 0x0000041C + +#define REG_LINEARX_CSRAM_PARITY_ERR7_ADDR(inst) ((inst) + 0x000000B4) +#define BF_CSRAM8_INST2_PARITY_ERR_INFO(inst) ((inst) + 0x000000B4), 0x00000400 +#define BF_CSRAM9_INST2_PARITY_ERR_INFO(inst) ((inst) + 0x000000B4), 0x00000404 +#define BF_CSRAM10_INST2_PARITY_ERR_INFO(inst) ((inst) + 0x000000B4), 0x00000408 +#define BF_CSRAM11_INST2_PARITY_ERR_INFO(inst) ((inst) + 0x000000B4), 0x0000040C +#define BF_CSRAM12_INST2_PARITY_ERR_INFO(inst) ((inst) + 0x000000B4), 0x00000410 +#define BF_CSRAM13_INST2_PARITY_ERR_INFO(inst) ((inst) + 0x000000B4), 0x00000414 +#define BF_CSRAM14_INST2_PARITY_ERR_INFO(inst) ((inst) + 0x000000B4), 0x00000418 +#define BF_CSRAM15_INST2_PARITY_ERR_INFO(inst) ((inst) + 0x000000B4), 0x0000041C + +#define REG_LINEARX_CSRAM_PARITY_ERR8_ADDR(inst) ((inst) + 0x000000B8) +#define BF_UPDATE_CSRAM0_INST2_PARITY_ERR_INFO(inst) ((inst) + 0x000000B8), 0x00000400 +#define BF_UPDATE_CSRAM1_INST2_PARITY_ERR_INFO(inst) ((inst) + 0x000000B8), 0x00000404 + +#define REG_LINEARX_HSRAM_CLK_EN_ADDR(inst) ((inst) + 0x000000C0) +#define BF_HSRAM_CLK_EN_INFO(inst) ((inst) + 0x000000C0), 0x00001200 + +#define REG_LINEARX_CSRAM_CLK_EN0_ADDR(inst) ((inst) + 0x000000C4) +#define BF_CSRAM_CLK_EN_INST0_INFO(inst) ((inst) + 0x000000C4), 0x00001200 + +#define REG_LINEARX_CSRAM_CLK_EN1_ADDR(inst) ((inst) + 0x000000C8) +#define BF_CSRAM_CLK_EN_INST1_INFO(inst) ((inst) + 0x000000C8), 0x00001200 + +#define REG_LINEARX_CSRAM_CLK_EN2_ADDR(inst) ((inst) + 0x000000CC) +#define BF_CSRAM_CLK_EN_INST2_INFO(inst) ((inst) + 0x000000CC), 0x00001200 + +#define REG_LINEARX_RESET_CLK_MUX_ADDR(inst) ((inst) + 0x000000D0) +#define BF_HSRAM_RESET_CLK_MUX_INFO(inst) ((inst) + 0x000000D0), 0x00000100 +#define BF_CSRAM_RESET_CLK_MUX_INFO(inst) ((inst) + 0x000000D0), 0x00000101 + +#endif /* __ADI_APOLLO_BF_LINEARX_LUT_MEM_CTRL_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_linearx_lutp_master.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_linearx_lutp_master.h new file mode 100644 index 00000000000000..5ae7dc9a595189 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_linearx_lutp_master.h @@ -0,0 +1,70 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:19 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_LINEARX_LUTP_MASTER_H__ +#define __ADI_APOLLO_BF_LINEARX_LUTP_MASTER_H__ + +/*============= D E F I N E S ==============*/ +#define LINEARX_LUTP_MASTER_RX_LINEARX_REG32_0_RX_SLICE_0_RX_DIGITAL0 0x60220200 +#define LINEARX_LUTP_MASTER_RX_LINEARX_REG32_1_RX_SLICE_0_RX_DIGITAL0 0x60228200 +#define LINEARX_LUTP_MASTER_RX_LINEARX_REG32_0_RX_SLICE_1_RX_DIGITAL0 0x60420200 +#define LINEARX_LUTP_MASTER_RX_LINEARX_REG32_1_RX_SLICE_1_RX_DIGITAL0 0x60428200 +#define LINEARX_LUTP_MASTER_RX_LINEARX_REG32_0_RX_SLICE_0_RX_DIGITAL1 0x60A20200 +#define LINEARX_LUTP_MASTER_RX_LINEARX_REG32_1_RX_SLICE_0_RX_DIGITAL1 0x60A28200 +#define LINEARX_LUTP_MASTER_RX_LINEARX_REG32_0_RX_SLICE_1_RX_DIGITAL1 0x60C20200 +#define LINEARX_LUTP_MASTER_RX_LINEARX_REG32_1_RX_SLICE_1_RX_DIGITAL1 0x60C28200 +#define LINEARX_LUTP_MASTER_TX_LINEARX_REG32_0_TX_SLICE_0_TX_DIGITAL0 0x61220200 +#define LINEARX_LUTP_MASTER_TX_LINEARX_REG32_1_TX_SLICE_0_TX_DIGITAL0 0x61228200 +#define LINEARX_LUTP_MASTER_TX_LINEARX_REG32_0_TX_SLICE_1_TX_DIGITAL0 0x61420200 +#define LINEARX_LUTP_MASTER_TX_LINEARX_REG32_1_TX_SLICE_1_TX_DIGITAL0 0x61428200 +#define LINEARX_LUTP_MASTER_TX_LINEARX_REG32_0_TX_SLICE_0_TX_DIGITAL1 0x61A20200 +#define LINEARX_LUTP_MASTER_TX_LINEARX_REG32_1_TX_SLICE_0_TX_DIGITAL1 0x61A28200 +#define LINEARX_LUTP_MASTER_TX_LINEARX_REG32_0_TX_SLICE_1_TX_DIGITAL1 0x61C20200 +#define LINEARX_LUTP_MASTER_TX_LINEARX_REG32_1_TX_SLICE_1_TX_DIGITAL1 0x61C28200 + +#define REG_LINEARX_LUTP_MASTER_START_ADDR(inst) ((inst) + 0x00000000) +#define BF_LUTP_MASTER_START_INFO(inst) ((inst) + 0x00000000), 0x00000100 + +#define REG_LINEARX_LUTP_MASTER_HCONFIG_ADDR(inst) ((inst) + 0x00000004) +#define BF_LUTP_MASTER_HSCALE_INFO(inst) ((inst) + 0x00000004), 0x00000300 +#define BF_LUTP_MASTER_POLY_ORDER_INFO(inst) ((inst) + 0x00000004), 0x00000308 +#define BF_LUTP_MASTER_HOUTPUT_BITS_INFO(inst) ((inst) + 0x00000004), 0x00000410 + +#define REG_LINEARX_LUTP_MASTER_CCONFIG_ADDR(inst) ((inst) + 0x00000008) +#define BF_LUTP_MASTER_CENABLE_INFO(inst) ((inst) + 0x00000008), 0x00000100 +#define BF_LUTP_MASTER_CSCALE_INFO(inst) ((inst) + 0x00000008), 0x00000308 +#define BF_LUTP_MASTER_CTAP_CNT_INFO(inst) ((inst) + 0x00000008), 0x00000510 +#define BF_LUTP_MASTER_COUTPUT_BITS_INFO(inst) ((inst) + 0x00000008), 0x00000418 + +#define REG_LINEARX_LUTP_MASTER_HCCONFIG_ADDR(inst) ((inst) + 0x0000000C) +#define BF_LUTP_MASTER_START_OFFSET_INFO(inst) ((inst) + 0x0000000C), 0x00000800 +#define BF_LUTP_MASTER_LUT_SIZE_INFO(inst) ((inst) + 0x0000000C), 0x00000908 + +#define REG_LINEARX_LUTP_MASTER_IRQ_ENABLE_ADDR(inst) ((inst) + 0x00000010) +#define BF_LUTP_MASTER_IRQ_EN_INFO(inst) ((inst) + 0x00000010), 0x00000100 + +#define REG_LINEARX_LUTP_MASTER_DONE_ADDR(inst) ((inst) + 0x00000014) +#define BF_LUTP_MASTER_DONE_INFO(inst) ((inst) + 0x00000014), 0x00000100 + +#define REG_LINEARX_LUTP_MASTER_DONE_CLEAR_ADDR(inst) ((inst) + 0x00000018) +#define BF_LUTP_MASTER_DONE_CLEAR_INFO(inst) ((inst) + 0x00000018), 0x00000100 + +#define REG_LINEARX_LUTP_HCOEFFS_ADDR(inst, n) ((inst) + 0x0000001C + 4 * (n)) +#define BF_LUTP_MASTER_HCOEFFS_INFO(inst, n) ((inst) + 0x0000001C + 4 * (n)), 0x00001000 + +#define REG_LINEARX_LUTP_CCOEFFS_ADDR(inst, n) ((inst) + 0x0000039C + 4 * (n)) +#define BF_LUTP_MASTER_CCOEFFS_INFO(inst, n) ((inst) + 0x0000039C + 4 * (n)), 0x00001000 + +#endif /* __ADI_APOLLO_BF_LINEARX_LUTP_MASTER_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_linearx_lutp_slave.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_linearx_lutp_slave.h new file mode 100644 index 00000000000000..725cc3dfc1afd0 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_linearx_lutp_slave.h @@ -0,0 +1,66 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:19 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_LINEARX_LUTP_SLAVE_H__ +#define __ADI_APOLLO_BF_LINEARX_LUTP_SLAVE_H__ + +/*============= D E F I N E S ==============*/ +#define LINEARX_LUTP_SLAVE_RX_LINEARX_REG32_0_RX_SLICE_0_RX_DIGITAL0 0x60220A00 +#define LINEARX_LUTP_SLAVE_RX_LINEARX_REG32_1_RX_SLICE_0_RX_DIGITAL0 0x60228A00 +#define LINEARX_LUTP_SLAVE_RX_LINEARX_REG32_0_RX_SLICE_1_RX_DIGITAL0 0x60420A00 +#define LINEARX_LUTP_SLAVE_RX_LINEARX_REG32_1_RX_SLICE_1_RX_DIGITAL0 0x60428A00 +#define LINEARX_LUTP_SLAVE_RX_LINEARX_REG32_0_RX_SLICE_0_RX_DIGITAL1 0x60A20A00 +#define LINEARX_LUTP_SLAVE_RX_LINEARX_REG32_1_RX_SLICE_0_RX_DIGITAL1 0x60A28A00 +#define LINEARX_LUTP_SLAVE_RX_LINEARX_REG32_0_RX_SLICE_1_RX_DIGITAL1 0x60C20A00 +#define LINEARX_LUTP_SLAVE_RX_LINEARX_REG32_1_RX_SLICE_1_RX_DIGITAL1 0x60C28A00 +#define LINEARX_LUTP_SLAVE_TX_LINEARX_REG32_0_TX_SLICE_0_TX_DIGITAL0 0x61220A00 +#define LINEARX_LUTP_SLAVE_TX_LINEARX_REG32_1_TX_SLICE_0_TX_DIGITAL0 0x61228A00 +#define LINEARX_LUTP_SLAVE_TX_LINEARX_REG32_0_TX_SLICE_1_TX_DIGITAL0 0x61420A00 +#define LINEARX_LUTP_SLAVE_TX_LINEARX_REG32_1_TX_SLICE_1_TX_DIGITAL0 0x61428A00 +#define LINEARX_LUTP_SLAVE_TX_LINEARX_REG32_0_TX_SLICE_0_TX_DIGITAL1 0x61A20A00 +#define LINEARX_LUTP_SLAVE_TX_LINEARX_REG32_1_TX_SLICE_0_TX_DIGITAL1 0x61A28A00 +#define LINEARX_LUTP_SLAVE_TX_LINEARX_REG32_0_TX_SLICE_1_TX_DIGITAL1 0x61C20A00 +#define LINEARX_LUTP_SLAVE_TX_LINEARX_REG32_1_TX_SLICE_1_TX_DIGITAL1 0x61C28A00 + +#define REG_LINEARX_LUTP_SLAVE_START_ADDR(inst) ((inst) + 0x00000000) +#define BF_LUTP_SLAVE_HSRAM_START_INFO(inst) ((inst) + 0x00000000), 0x00000100 +#define BF_LUTP_SLAVE_CSRAM_START_INFO(inst) ((inst) + 0x00000000), 0x00000101 + +#define REG_LINEARX_LUTP_SLAVE_DONE_ADDR(inst) ((inst) + 0x00000004) +#define BF_LUTP_SLAVE_HSRAM_DONE_INFO(inst) ((inst) + 0x00000004), 0x00000100 +#define BF_LUTP_SLAVE_CSRAM_DONE_INFO(inst) ((inst) + 0x00000004), 0x00000101 + +#define REG_LINEARX_LUTP_SLAVE_START_EN_ADDR(inst) ((inst) + 0x00000008) +#define BF_LUTP_SLAVE_HSRAM_START_FROM_MASTER_EN_INFO(inst) ((inst) + 0x00000008), 0x00000100 +#define BF_LUTP_SLAVE_CSRAM_START_FROM_MASTER_EN_INFO(inst) ((inst) + 0x00000008), 0x00000101 + +#define REG_LINEARX_LUTP_SLAVE_CLK_ENABLE_ADDR(inst) ((inst) + 0x0000000C) +#define BF_LUTP_SLAVE_CLK_EN_INFO(inst) ((inst) + 0x0000000C), 0x00000100 + +#define REG_LINEARX_LUTP_SLAVE_IRQ_ENABLE_ADDR(inst) ((inst) + 0x00000010) +#define BF_LUTP_SLAVE_HSRAM_IRQ_EN_INFO(inst) ((inst) + 0x00000010), 0x00000100 +#define BF_LUTP_SLAVE_CSRAM_IRQ_EN_INFO(inst) ((inst) + 0x00000010), 0x00000101 + +#define REG_LINEARX_LUTP_SLAVE_CONFIG_ADDR(inst) ((inst) + 0x00000020) +#define BF_LUTP_SLAVE_CLK_MUX_WAIT_COUNT_INFO(inst) ((inst) + 0x00000020), 0x00000400 +#define BF_LUTP_SLAVE_PATH_MUX_WAIT_COUNT_INFO(inst) ((inst) + 0x00000020), 0x00000404 + +#define REG_LINEARX_LUTP_SLAVE_FSM_ADDR(inst) ((inst) + 0x00000024) +#define BF_LUTP_SLAVE_HSRAM_FSM_STATE_INFO(inst) ((inst) + 0x00000024), 0x00000400 +#define BF_LUTP_SLAVE_CSRAM_FSM_STATE_INFO(inst) ((inst) + 0x00000024), 0x00000404 +#define BF_LUTP_SLAVE_HSRAM_RESET_FSM_INFO(inst) ((inst) + 0x00000024), 0x00000108 +#define BF_LUTP_SLAVE_CSRAM_RESET_FSM_INFO(inst) ((inst) + 0x00000024), 0x00000109 + +#endif /* __ADI_APOLLO_BF_LINEARX_LUTP_SLAVE_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_linearx_misc.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_linearx_misc.h new file mode 100644 index 00000000000000..7893861d02d3aa --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_linearx_misc.h @@ -0,0 +1,50 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:19 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_LINEARX_MISC_H__ +#define __ADI_APOLLO_BF_LINEARX_MISC_H__ + +/*============= D E F I N E S ==============*/ +#define LINEARX_MISC_RX_LINEARX_REG32_0_RX_SLICE_0_RX_DIGITAL0 0x60220080 +#define LINEARX_MISC_RX_LINEARX_REG32_1_RX_SLICE_0_RX_DIGITAL0 0x60228080 +#define LINEARX_MISC_RX_LINEARX_REG32_0_RX_SLICE_1_RX_DIGITAL0 0x60420080 +#define LINEARX_MISC_RX_LINEARX_REG32_1_RX_SLICE_1_RX_DIGITAL0 0x60428080 +#define LINEARX_MISC_RX_LINEARX_REG32_0_RX_SLICE_0_RX_DIGITAL1 0x60A20080 +#define LINEARX_MISC_RX_LINEARX_REG32_1_RX_SLICE_0_RX_DIGITAL1 0x60A28080 +#define LINEARX_MISC_RX_LINEARX_REG32_0_RX_SLICE_1_RX_DIGITAL1 0x60C20080 +#define LINEARX_MISC_RX_LINEARX_REG32_1_RX_SLICE_1_RX_DIGITAL1 0x60C28080 +#define LINEARX_MISC_TX_LINEARX_REG32_0_TX_SLICE_0_TX_DIGITAL0 0x61220080 +#define LINEARX_MISC_TX_LINEARX_REG32_1_TX_SLICE_0_TX_DIGITAL0 0x61228080 +#define LINEARX_MISC_TX_LINEARX_REG32_0_TX_SLICE_1_TX_DIGITAL0 0x61420080 +#define LINEARX_MISC_TX_LINEARX_REG32_1_TX_SLICE_1_TX_DIGITAL0 0x61428080 +#define LINEARX_MISC_TX_LINEARX_REG32_0_TX_SLICE_0_TX_DIGITAL1 0x61A20080 +#define LINEARX_MISC_TX_LINEARX_REG32_1_TX_SLICE_0_TX_DIGITAL1 0x61A28080 +#define LINEARX_MISC_TX_LINEARX_REG32_0_TX_SLICE_1_TX_DIGITAL1 0x61C20080 +#define LINEARX_MISC_TX_LINEARX_REG32_1_TX_SLICE_1_TX_DIGITAL1 0x61C28080 + +#define REG_BMEM_CTRL_ADDR(inst) ((inst) + 0x00000000) +#define BF_BMEM_ADC1_SEL_INFO(inst) ((inst) + 0x00000000), 0x00000100 +#define BF_NLCA_ACCESS_BMEM_INFO(inst) ((inst) + 0x00000000), 0x00000101 +#define BF_BMEM_FULL_IRQ_EN_INFO(inst) ((inst) + 0x00000000), 0x00000102 +#define BF_BMEM_PARITY_ERR_IRQ_EN_INFO(inst) ((inst) + 0x00000000), 0x00000103 + +#define REG_LINEARX_LUT_UPDATE_IRQ_ADDR(inst) ((inst) + 0x00000004) +#define BF_LUT_UPDATE_DONE_CLEAR_INFO(inst) ((inst) + 0x00000004), 0x00000100 +#define BF_LUT_UPDATE_IRQ_SEL_INFO(inst) ((inst) + 0x00000004), 0x00000101 + +#define REG_LINEARX_DEBUG_CLK_SEL_ADDR(inst) ((inst) + 0x00000008) +#define BF_DEBUG_CLK_SEL_LINEARX_MISC_INFO(inst) ((inst) + 0x00000008), 0x00000300 + +#endif /* __ADI_APOLLO_BF_LINEARX_MISC_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_linearx_nlca.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_linearx_nlca.h new file mode 100644 index 00000000000000..b1fe20c5a28afc --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_linearx_nlca.h @@ -0,0 +1,99 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:19 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_LINEARX_NLCA_H__ +#define __ADI_APOLLO_BF_LINEARX_NLCA_H__ + +/*============= D E F I N E S ==============*/ +#define LINEARX_NLCA_RX_LINEARX_REG32_0_RX_SLICE_0_RX_DIGITAL0 0x60220C00 +#define LINEARX_NLCA_RX_LINEARX_REG32_1_RX_SLICE_0_RX_DIGITAL0 0x60228C00 +#define LINEARX_NLCA_RX_LINEARX_REG32_0_RX_SLICE_1_RX_DIGITAL0 0x60420C00 +#define LINEARX_NLCA_RX_LINEARX_REG32_1_RX_SLICE_1_RX_DIGITAL0 0x60428C00 +#define LINEARX_NLCA_RX_LINEARX_REG32_0_RX_SLICE_0_RX_DIGITAL1 0x60A20C00 +#define LINEARX_NLCA_RX_LINEARX_REG32_1_RX_SLICE_0_RX_DIGITAL1 0x60A28C00 +#define LINEARX_NLCA_RX_LINEARX_REG32_0_RX_SLICE_1_RX_DIGITAL1 0x60C20C00 +#define LINEARX_NLCA_RX_LINEARX_REG32_1_RX_SLICE_1_RX_DIGITAL1 0x60C28C00 +#define LINEARX_NLCA_TX_LINEARX_REG32_0_TX_SLICE_0_TX_DIGITAL0 0x61220C00 +#define LINEARX_NLCA_TX_LINEARX_REG32_1_TX_SLICE_0_TX_DIGITAL0 0x61228C00 +#define LINEARX_NLCA_TX_LINEARX_REG32_0_TX_SLICE_1_TX_DIGITAL0 0x61420C00 +#define LINEARX_NLCA_TX_LINEARX_REG32_1_TX_SLICE_1_TX_DIGITAL0 0x61428C00 +#define LINEARX_NLCA_TX_LINEARX_REG32_0_TX_SLICE_0_TX_DIGITAL1 0x61A20C00 +#define LINEARX_NLCA_TX_LINEARX_REG32_1_TX_SLICE_0_TX_DIGITAL1 0x61A28C00 +#define LINEARX_NLCA_TX_LINEARX_REG32_0_TX_SLICE_1_TX_DIGITAL1 0x61C20C00 +#define LINEARX_NLCA_TX_LINEARX_REG32_1_TX_SLICE_1_TX_DIGITAL1 0x61C28C00 + +#define REG_NLCA_OFFSET_A_ADDR(inst) ((inst) + 0x00000000) +#define BF_NLCA_OFFSET_A_INFO(inst) ((inst) + 0x00000000), 0x00001000 + +#define REG_NLCA_SHIFT_ADDR(inst) ((inst) + 0x00000004) +#define BF_NLCA_SHIFT_ADDR_A_INFO(inst) ((inst) + 0x00000004), 0x00000800 +#define BF_NLCA_SHIFT_SAMP_A_INFO(inst) ((inst) + 0x00000004), 0x00000608 +#define BF_NLCA_SHIFT_SAMP_B_INFO(inst) ((inst) + 0x00000004), 0x0000060E +#define BF_NLCA_SHIFT_SAMP_X_INFO(inst) ((inst) + 0x00000004), 0x00000614 +#define BF_NLCA_SHIFT_SAMP_Y_INFO(inst) ((inst) + 0x00000004), 0x0000061A + +#define REG_NLCA_ADDR_A_B_ADDR(inst) ((inst) + 0x00000008) +#define BF_NLCA_ADDR_A_START_INFO(inst) ((inst) + 0x00000008), 0x00000A00 +#define BF_NLCA_ADDR_B_START_INFO(inst) ((inst) + 0x00000008), 0x00000A0A + +#define REG_NLCA_ADDR_X_Y_ADDR(inst) ((inst) + 0x0000000C) +#define BF_NLCA_ADDR_X_START_INFO(inst) ((inst) + 0x0000000C), 0x00000A00 +#define BF_NLCA_ADDR_Y_START_INFO(inst) ((inst) + 0x0000000C), 0x00000A0A + +#define REG_NLCA_ADDR_R_ADDR(inst) ((inst) + 0x00000010) +#define BF_NLCA_ADDR_R_START_INFO(inst) ((inst) + 0x00000010), 0x00000A00 + +#define REG_NLCA_OP_CODE_ADDR(inst) ((inst) + 0x00000014) +#define BF_NLCA_OP_CODE_INFO(inst) ((inst) + 0x00000014), 0x00000400 + +#define REG_NLCA_OP_START_ADDR(inst) ((inst) + 0x00000018) +#define BF_NLCA_OP_START_INFO(inst) ((inst) + 0x00000018), 0x00000100 + +#define REG_NLCA_OP_DONE_ADDR(inst) ((inst) + 0x0000001C) +#define BF_NLCA_OP_DONE_INFO(inst) ((inst) + 0x0000001C), 0x00000100 +#define BF_FSM_ERROR_FLAG_INFO(inst) ((inst) + 0x0000001C), 0x00000101 + +#define REG_NLCA_IRQ_EN_ADDR(inst) ((inst) + 0x00000020) +#define BF_NLCA_IRQ_EN_INFO(inst) ((inst) + 0x00000020), 0x00000100 + +#define REG_NLCA_OP_ACK_ADDR(inst) ((inst) + 0x00000024) +#define BF_NLCA_OP_ACK_INFO(inst) ((inst) + 0x00000024), 0x00000100 + +#define REG_NLCA_RESET_FSM_ADDR(inst) ((inst) + 0x00000028) +#define BF_NLCA_RESET_FSM_INFO(inst) ((inst) + 0x00000028), 0x00000100 + +#define REG_NLCA_FSM_STATE_ADDR(inst) ((inst) + 0x0000002C) +#define BF_NLCA_FSM_STATE_INFO(inst) ((inst) + 0x0000002C), 0x00000500 + +#define REG_NLCA_MAX_LAG_ADDR(inst) ((inst) + 0x00000030) +#define BF_NLCA_MAX_LAG_INFO(inst) ((inst) + 0x00000030), 0x00000600 + +#define REG_NLCA_FILT_SETTINGS_ADDR(inst) ((inst) + 0x00000034) +#define BF_NLCA_R_ADD_SUB_SHIFT_INFO(inst) ((inst) + 0x00000034), 0x00000100 +#define BF_NLCA_R_MULT_SHIFT_INFO(inst) ((inst) + 0x00000034), 0x00000401 +#define BF_NLCA_Q_IN_SHIFT_INFO(inst) ((inst) + 0x00000034), 0x00000505 +#define BF_NLCA_Q_IN_ROUND_EN_INFO(inst) ((inst) + 0x00000034), 0x0000010A +#define BF_NLCA_R_OUT_ROUND_EN_INFO(inst) ((inst) + 0x00000034), 0x0000010B +#define BF_NLCA_PN_RUN_CNT_INFO(inst) ((inst) + 0x00000034), 0x0000090C +#define BF_NLCA_BLOCK_SIZE_ADJ_INFO(inst) ((inst) + 0x00000034), 0x00000215 + +#define REG_NLCA_FILT_ADDR(inst, n) ((inst) + 0x00000038 + 4 * (n)) +#define BF_NLCA_FILT_COEF_LSB_INFO(inst, n) ((inst) + 0x00000038 + 4 * (n)), 0x00001000 +#define BF_NLCA_FILT_COEF_MSB_INFO(inst, n) ((inst) + 0x00000038 + 4 * (n)), 0x00001010 + +#define REG_NLCA_OUTPUT_Q_ADDR(inst, n) ((inst) + 0x00000138 + 4 * (n)) +#define BF_NLCA_OUTPUT_Q_INFO(inst, n) ((inst) + 0x00000138 + 4 * (n)), 0x00002000 + +#endif /* __ADI_APOLLO_BF_LINEARX_NLCA_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_linearx_rx_config.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_linearx_rx_config.h new file mode 100644 index 00000000000000..402905625c521c --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_linearx_rx_config.h @@ -0,0 +1,36 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:19 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_LINEARX_RX_CONFIG_H__ +#define __ADI_APOLLO_BF_LINEARX_RX_CONFIG_H__ + +/*============= D E F I N E S ==============*/ +#define LINEARX_RX_CONFIG_RX_LINEARX_REG32_0_RX_SLICE_0_RX_DIGITAL0 0x60220000 +#define LINEARX_RX_CONFIG_RX_LINEARX_REG32_1_RX_SLICE_0_RX_DIGITAL0 0x60228000 +#define LINEARX_RX_CONFIG_RX_LINEARX_REG32_0_RX_SLICE_1_RX_DIGITAL0 0x60420000 +#define LINEARX_RX_CONFIG_RX_LINEARX_REG32_1_RX_SLICE_1_RX_DIGITAL0 0x60428000 +#define LINEARX_RX_CONFIG_RX_LINEARX_REG32_0_RX_SLICE_0_RX_DIGITAL1 0x60A20000 +#define LINEARX_RX_CONFIG_RX_LINEARX_REG32_1_RX_SLICE_0_RX_DIGITAL1 0x60A28000 +#define LINEARX_RX_CONFIG_RX_LINEARX_REG32_0_RX_SLICE_1_RX_DIGITAL1 0x60C20000 +#define LINEARX_RX_CONFIG_RX_LINEARX_REG32_1_RX_SLICE_1_RX_DIGITAL1 0x60C28000 + +#define REG_LINEARX_RX_BYPASS_ADDR(inst) ((inst) + 0x00000000) +#define BF_LINEARX_RX_BYPASS_INFO(inst) ((inst) + 0x00000000), 0x00000100 + +#define REG_LINEARX_RX_CTRL_ADDR(inst) ((inst) + 0x00000004) +#define BF_LINEARX_RX_CLK_DIS_INFO(inst) ((inst) + 0x00000004), 0x00000100 +#define BF_LINEARX_RX_LATENCY_CONST_INFO(inst) ((inst) + 0x00000004), 0x00000202 + +#endif /* __ADI_APOLLO_BF_LINEARX_RX_CONFIG_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_linearx_rx_ddc.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_linearx_rx_ddc.h new file mode 100644 index 00000000000000..72c6e8179d4c5f --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_linearx_rx_ddc.h @@ -0,0 +1,70 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:19 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_LINEARX_RX_DDC_H__ +#define __ADI_APOLLO_BF_LINEARX_RX_DDC_H__ + +/*============= D E F I N E S ==============*/ +#define LINEARX_RX_DDC_REGMAP_RX_LINEARX_REG32_0_RX_SLICE_0_RX_DIGITAL0 0x60220F00 +#define LINEARX_RX_DDC_REGMAP_RX_LINEARX_REG32_1_RX_SLICE_0_RX_DIGITAL0 0x60228F00 +#define LINEARX_RX_DDC_REGMAP_RX_LINEARX_REG32_0_RX_SLICE_1_RX_DIGITAL0 0x60420F00 +#define LINEARX_RX_DDC_REGMAP_RX_LINEARX_REG32_1_RX_SLICE_1_RX_DIGITAL0 0x60428F00 +#define LINEARX_RX_DDC_REGMAP_RX_LINEARX_REG32_0_RX_SLICE_0_RX_DIGITAL1 0x60A20F00 +#define LINEARX_RX_DDC_REGMAP_RX_LINEARX_REG32_1_RX_SLICE_0_RX_DIGITAL1 0x60A28F00 +#define LINEARX_RX_DDC_REGMAP_RX_LINEARX_REG32_0_RX_SLICE_1_RX_DIGITAL1 0x60C20F00 +#define LINEARX_RX_DDC_REGMAP_RX_LINEARX_REG32_1_RX_SLICE_1_RX_DIGITAL1 0x60C28F00 + +#define REG_NCO_TUNE_LINEARX_RX_DDC_ADDR(inst) ((inst) + 0x00000000) +#define BF_NCO_FREQ_ADJ_LINEARX_RX_DDC_INFO(inst) ((inst) + 0x00000000), 0x00000F00 +#define BF_NCO_PHASE_ADJ_LINEARX_RX_DDC_INFO(inst) ((inst) + 0x00000000), 0x00000F10 + +#define REG_DDC_DATA_I_ADDR(inst) ((inst) + 0x00000010) +#define BF_CIC_OUT_IDATA_LINEARX_RX_DDC_INFO(inst) ((inst) + 0x00000010), 0x00001900 + +#define REG_DDC_DATA_Q_ADDR(inst) ((inst) + 0x00000014) +#define BF_CIC_OUT_QDATA_LINEARX_RX_DDC_INFO(inst) ((inst) + 0x00000014), 0x00001900 + +#define REG_DDC_MISC_CTRL_LINEARX_RX_DDC_ADDR(inst) ((inst) + 0x00000020) +#define BF_MIXER_DITH_EN_INFO(inst) ((inst) + 0x00000020), 0x00000100 +#define BF_NCO_ADITH_EN_LINEARX_RX_DDC_INFO(inst) ((inst) + 0x00000020), 0x00000101 +#define BF_NCO_PDITH_EN_LINEARX_RX_DDC_INFO(inst) ((inst) + 0x00000020), 0x00000102 +#define BF_MIXER_MODE_LINEARX_RX_DDC_INFO(inst) ((inst) + 0x00000020), 0x00000203 +#define BF_CIC_DEC_RATE_LINEARX_RX_DDC_INFO(inst) ((inst) + 0x00000020), 0x00000805 +#define BF_RESET_FSM_INFO(inst) ((inst) + 0x00000020), 0x0000010D +#define BF_CIC_FSM_STATE_I0_LINEARX_RX_DDC_INFO(inst) ((inst) + 0x00000020), 0x00000410 +#define BF_CIC_FSM_STATE_Q0_LINEARX_RX_DDC_INFO(inst) ((inst) + 0x00000020), 0x00000414 +#define BF_EXP_DEC_RATE_INFO(inst) ((inst) + 0x00000020), 0x00000318 + +#define REG_DDC_CTRL_REG_LINEARX_RX_DDC_ADDR(inst) ((inst) + 0x00000030) +#define BF_RESET_DDC_LINEARX_RX_DDC_INFO(inst) ((inst) + 0x00000030), 0x00000100 +#define BF_EN_CLK_DDC_LINEARX_RX_DDC_INFO(inst) ((inst) + 0x00000030), 0x00000101 +#define BF_NCO_RESET_LINEARX_RX_DDC_INFO(inst) ((inst) + 0x00000030), 0x00000102 +#define BF_NUM_CPT_AVG_INFO(inst) ((inst) + 0x00000030), 0x00000703 + +#define REG_DDC_NCO_EN_LINEARX_RX_DDC_ADDR(inst) ((inst) + 0x00000034) +#define BF_NCO_EN_DDC_LINEARX_RX_DDC_INFO(inst) ((inst) + 0x00000034), 0x00000100 + +#define REG_DDC_START_LINEARX_RX_DDC_ADDR(inst) ((inst) + 0x00000038) +#define BF_START_DDC_LINEARX_RX_DDC_INFO(inst) ((inst) + 0x00000038), 0x00000100 + +#define REG_DDC_IRQ_LINEARX_RX_DDC_ADDR(inst) ((inst) + 0x00000040) +#define BF_CIC_IRQ_RECVD_DDC_LINEARX_RX_DDC_INFO(inst) ((inst) + 0x00000040), 0x00000100 +#define BF_IRQ_STATUS_DDC_LINEARX_RX_DDC_INFO(inst) ((inst) + 0x00000040), 0x00000101 +#define BF_IRQ_DDC_EN_LINEARX_RX_DDC_INFO(inst) ((inst) + 0x00000040), 0x00000102 + +#define REG_DDC_BMEM_CTRL_ADDR(inst) ((inst) + 0x00000044) +#define BF_RX_DDC_BMEM_AWG_MODE_INFO(inst) ((inst) + 0x00000044), 0x00000100 + +#endif /* __ADI_APOLLO_BF_LINEARX_RX_DDC_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_linearx_tx_config.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_linearx_tx_config.h new file mode 100644 index 00000000000000..750302db94e537 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_linearx_tx_config.h @@ -0,0 +1,39 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:21 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_LINEARX_TX_CONFIG_H__ +#define __ADI_APOLLO_BF_LINEARX_TX_CONFIG_H__ + +/*============= D E F I N E S ==============*/ +#define LINEARX_TX_CONFIG_TX_LINEARX_REG32_0_TX_SLICE_0_TX_DIGITAL0 0x61220000 +#define LINEARX_TX_CONFIG_TX_LINEARX_REG32_1_TX_SLICE_0_TX_DIGITAL0 0x61228000 +#define LINEARX_TX_CONFIG_TX_LINEARX_REG32_0_TX_SLICE_1_TX_DIGITAL0 0x61420000 +#define LINEARX_TX_CONFIG_TX_LINEARX_REG32_1_TX_SLICE_1_TX_DIGITAL0 0x61428000 +#define LINEARX_TX_CONFIG_TX_LINEARX_REG32_0_TX_SLICE_0_TX_DIGITAL1 0x61A20000 +#define LINEARX_TX_CONFIG_TX_LINEARX_REG32_1_TX_SLICE_0_TX_DIGITAL1 0x61A28000 +#define LINEARX_TX_CONFIG_TX_LINEARX_REG32_0_TX_SLICE_1_TX_DIGITAL1 0x61C20000 +#define LINEARX_TX_CONFIG_TX_LINEARX_REG32_1_TX_SLICE_1_TX_DIGITAL1 0x61C28000 + +#define REG_LINEARX_TX_BYPASS_ADDR(inst) ((inst) + 0x00000000) +#define BF_LINEARX_TX_BYPASS_INFO(inst) ((inst) + 0x00000000), 0x00000100 + +#define REG_LINEARX_TX_CTRL_ADDR(inst) ((inst) + 0x00000004) +#define BF_LINEARX_TX_CLK_DIS_INFO(inst) ((inst) + 0x00000004), 0x00000100 +#define BF_LINEARX_TX_LATENCY_CONST_INFO(inst) ((inst) + 0x00000004), 0x00000202 + +#define REG_LINEARX_FROM_BMEM_ADDR(inst) ((inst) + 0x0000000C) +#define BF_LINEARX_FROM_BMEM_INFO(inst) ((inst) + 0x0000000C), 0x00000100 + +#endif /* __ADI_APOLLO_BF_LINEARX_TX_CONFIG_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_linearx_tx_ddc.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_linearx_tx_ddc.h new file mode 100644 index 00000000000000..0bffb36956c35b --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_linearx_tx_ddc.h @@ -0,0 +1,68 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:21 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_LINEARX_TX_DDC_H__ +#define __ADI_APOLLO_BF_LINEARX_TX_DDC_H__ + +/*============= D E F I N E S ==============*/ +#define LINEARX_TX_DDC_REGMAP_TX_LINEARX_REG32_0_TX_SLICE_0_TX_DIGITAL0 0x61220F00 +#define LINEARX_TX_DDC_REGMAP_TX_LINEARX_REG32_1_TX_SLICE_0_TX_DIGITAL0 0x61228F00 +#define LINEARX_TX_DDC_REGMAP_TX_LINEARX_REG32_0_TX_SLICE_1_TX_DIGITAL0 0x61420F00 +#define LINEARX_TX_DDC_REGMAP_TX_LINEARX_REG32_1_TX_SLICE_1_TX_DIGITAL0 0x61428F00 +#define LINEARX_TX_DDC_REGMAP_TX_LINEARX_REG32_0_TX_SLICE_0_TX_DIGITAL1 0x61A20F00 +#define LINEARX_TX_DDC_REGMAP_TX_LINEARX_REG32_1_TX_SLICE_0_TX_DIGITAL1 0x61A28F00 +#define LINEARX_TX_DDC_REGMAP_TX_LINEARX_REG32_0_TX_SLICE_1_TX_DIGITAL1 0x61C20F00 +#define LINEARX_TX_DDC_REGMAP_TX_LINEARX_REG32_1_TX_SLICE_1_TX_DIGITAL1 0x61C28F00 + +#define REG_NCO_TUNE_LINEARX_TX_DDC_ADDR(inst, n) ((inst) + 0x00000000 + 4 * (n)) +#define BF_NCO_FREQ_ADJ_LINEARX_TX_DDC_INFO(inst, n) ((inst) + 0x00000000 + 4 * (n)), 0x00000F00 +#define BF_NCO_PHASE_ADJ_LINEARX_TX_DDC_INFO(inst, n) ((inst) + 0x00000000 + 4 * (n)), 0x00000F10 + +#define REG_DDC_DATA_ADDR(inst, n) ((inst) + 0x00000010 + 4 * (n)) +#define BF_CIC_OUT_IDATA_LINEARX_TX_DDC_INFO(inst, n) ((inst) + 0x00000010 + 4 * (n)), 0x00001000 +#define BF_CIC_OUT_QDATA_LINEARX_TX_DDC_INFO(inst, n) ((inst) + 0x00000010 + 4 * (n)), 0x00001010 + +#define REG_DDC_MISC_CTRL_LINEARX_TX_DDC_ADDR(inst, n) ((inst) + 0x00000020 + 4 * (n)) +#define BF_NCO_ADITH_EN_LINEARX_TX_DDC_INFO(inst, n) ((inst) + 0x00000020 + 4 * (n)), 0x00000101 +#define BF_NCO_PDITH_EN_LINEARX_TX_DDC_INFO(inst, n) ((inst) + 0x00000020 + 4 * (n)), 0x00000102 +#define BF_MIXER_MODE_LINEARX_TX_DDC_INFO(inst, n) ((inst) + 0x00000020 + 4 * (n)), 0x00000203 +#define BF_CIC_DEC_RATE_LINEARX_TX_DDC_INFO(inst, n) ((inst) + 0x00000020 + 4 * (n)), 0x00000B05 +#define BF_CIC_FSM_STATE_I0_LINEARX_TX_DDC_INFO(inst, n) ((inst) + 0x00000020 + 4 * (n)), 0x00000410 +#define BF_CIC_FSM_STATE_Q0_LINEARX_TX_DDC_INFO(inst, n) ((inst) + 0x00000020 + 4 * (n)), 0x00000414 + +#define REG_DDC_CTRL_REG_LINEARX_TX_DDC_ADDR(inst) ((inst) + 0x00000030) +#define BF_RESET_DDC_LINEARX_TX_DDC_INFO(inst) ((inst) + 0x00000030), 0x00000200 +#define BF_EN_CLK_DDC_LINEARX_TX_DDC_INFO(inst) ((inst) + 0x00000030), 0x00000202 +#define BF_DDC_INPUT_DATA_SEL_INFO(inst) ((inst) + 0x00000030), 0x00000104 +#define BF_NCO_RESET_LINEARX_TX_DDC_INFO(inst) ((inst) + 0x00000030), 0x00000205 + +#define REG_DDC_NCO_EN_LINEARX_TX_DDC_ADDR(inst) ((inst) + 0x00000034) +#define BF_NCO_EN_DDC_LINEARX_TX_DDC_INFO(inst) ((inst) + 0x00000034), 0x00000200 + +#define REG_DDC_START_LINEARX_TX_DDC_ADDR(inst) ((inst) + 0x00000038) +#define BF_START_DDC_LINEARX_TX_DDC_INFO(inst) ((inst) + 0x00000038), 0x00000200 + +#define REG_NCO_BMEM_CTRL_ADDR(inst) ((inst) + 0x0000003C) +#define BF_TX_NCO_BMEM_EN_INFO(inst) ((inst) + 0x0000003C), 0x00000100 +#define BF_TX_NCO_BMEM_DITH_EN_INFO(inst) ((inst) + 0x0000003C), 0x00000101 +#define BF_TX_NCO_BMEM_SCALE_INFO(inst) ((inst) + 0x0000003C), 0x00000202 +#define BF_TX_NCO_BMEM_8T8R_MASK_INFO(inst) ((inst) + 0x0000003C), 0x00000204 + +#define REG_DDC_IRQ_LINEARX_TX_DDC_ADDR(inst) ((inst) + 0x00000040) +#define BF_CIC_IRQ_RECVD_DDC_LINEARX_TX_DDC_INFO(inst) ((inst) + 0x00000040), 0x00000200 +#define BF_IRQ_STATUS_DDC_LINEARX_TX_DDC_INFO(inst) ((inst) + 0x00000040), 0x00000202 +#define BF_IRQ_DDC_EN_LINEARX_TX_DDC_INFO(inst) ((inst) + 0x00000040), 0x00000204 + +#endif /* __ADI_APOLLO_BF_LINEARX_TX_DDC_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_mailbox.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_mailbox.h new file mode 100644 index 00000000000000..8205f896c155c5 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_mailbox.h @@ -0,0 +1,48 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:17 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_MAILBOX_H__ +#define __ADI_APOLLO_BF_MAILBOX_H__ + +/*============= D E F I N E S ==============*/ +#define CORE_0_SPI0_CMD_MAILBOX 0x41500000 +#define CORE_0_SPI1_CMD_MAILBOX 0x41600000 + +#ifdef USE_PRIVATE_BF +#define REG_ARM_CMD_1_MAILBOX_ADDR(inst) ((inst) + 0x00000000) +#define BF_ARM_COMMAND_OPCODE_INFO(inst) ((inst) + 0x00000000), 0x00000600 +#define BF_ARM_COMMAND_BUSY_MAILBOX_INFO(inst) ((inst) + 0x00000000), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#define REG_ARM_CMD_2_MAILBOX_ADDR(inst) ((inst) + 0x00000004) +#define BF_ARM_COMMAND_PAYLOAD_BYTES_INFO(inst) ((inst) + 0x00000004), 0x00002000 + +#define REG_ARM_STATUS_1_MAILBOX_ADDR(inst) ((inst) + 0x00000008) +#define BF_ARM_STATUS_1_INFO(inst) ((inst) + 0x00000008), 0x00002000 + +#define REG_ARM_STATUS_2_MAILBOX_ADDR(inst) ((inst) + 0x0000000C) +#define BF_ARM_STATUS_2_INFO(inst) ((inst) + 0x0000000C), 0x00001E00 +#define BF_STREAM_PROC_ARM_STATUS_MAILBOX_INFO(inst) ((inst) + 0x0000000C), 0x0000021E + +#define REG_ARM_STATUS_3_MAILBOX_ADDR(inst) ((inst) + 0x00000010) +#define BF_ARM_STATUS_3_INFO(inst) ((inst) + 0x00000010), 0x00002000 + +#define REG_ARM_STATUS_4_MAILBOX_ADDR(inst) ((inst) + 0x00000014) +#define BF_ARM_STATUS_4_INFO(inst) ((inst) + 0x00000014), 0x00002000 + +#define REG_ARM_GPIO_VAL_MAILBOX_ADDR(inst) ((inst) + 0x00000018) +#define BF_GPIO_VAL_INFO(inst) ((inst) + 0x00000018), 0x00001000 + +#endif /* __ADI_APOLLO_BF_MAILBOX_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_master_bias_ctrl.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_master_bias_ctrl.h new file mode 100644 index 00000000000000..946a6accfe63db --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_master_bias_ctrl.h @@ -0,0 +1,521 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:18 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_MASTER_BIAS_CTRL_H__ +#define __ADI_APOLLO_BF_MASTER_BIAS_CTRL_H__ + +/*============= D E F I N E S ==============*/ +#define MBIAS0 0x4C001800 +#define MBIAS1 0x4C001C00 + +#define REG_MBIAS_IGEN_PWRDWN_ADDR(inst) ((inst) + 0x00000100) +#define BF_MBIAS_IGEN_PD_INFO(inst) ((inst) + 0x00000100), 0x00000100 +#define BF_MBIAS_TRIM_COMP_PD_INFO(inst) ((inst) + 0x00000100), 0x00000101 + +#define REG_MBIAS_BG_CTAT_TRIM_ADDR(inst) ((inst) + 0x00000101) +#define BF_MBIAS_BG_CTAT_INFO(inst) ((inst) + 0x00000101), 0x00000400 +#define BF_MBIAS_BG_CTAT_D_INFO(inst) ((inst) + 0x00000101), 0x00000104 +#define BF_MBIAS_BG_CURVE_D_IN_INFO(inst) ((inst) + 0x00000101), 0x00000105 + +#define REG_MBIAS_TRIM_AUTO_ADDR(inst) ((inst) + 0x00000102) +#define BF_MBIAS_TRIM_AUTO_INFO(inst) ((inst) + 0x00000102), 0x00000100 + +#define REG_MBIAS_BG_PTAT_TRIM_ADDR(inst) ((inst) + 0x00000103) +#define BF_MBIAS_BG_PTAT_INFO(inst) ((inst) + 0x00000103), 0x00000600 + +#define REG_MBIAS_BG_LEVEL_TRIM_ADDR(inst) ((inst) + 0x00000104) +#define BF_MBIAS_BG_LEVEL_INFO(inst) ((inst) + 0x00000104), 0x00000800 + +#define REG_MBIAS_IGEN_TRIM_CODE_ADDR(inst) ((inst) + 0x00000105) +#define BF_MBIAS_IGEN_PTATR_INFO(inst) ((inst) + 0x00000105), 0x00000600 + +#define REG_MBIAS_DEGEN_TRIM_CODE_ADDR(inst) ((inst) + 0x00000106) +#define BF_MBIAS_DEGEN_TRIM_CODE_INFO(inst) ((inst) + 0x00000106), 0x00000300 + +#define REG_MBIAS_IGEN_RTRIM_ADDR(inst) ((inst) + 0x00000107) +#define BF_MBIAS_RTRIM_TRIGGER_MANUAL_INFO(inst) ((inst) + 0x00000107), 0x00000100 +#define BF_MBIAS_RTRIM_BYP_TRIGGERDEL_INFO(inst) ((inst) + 0x00000107), 0x00000101 +#define BF_MBIAS_RTRIM_CODE_SELECT_INFO(inst) ((inst) + 0x00000107), 0x00000102 +#define BF_MBIAS_DEGEN_TRIM_CODE_SELECT_INFO(inst) ((inst) + 0x00000107), 0x00000103 +#define BF_MBIAS_RTRIM_RESETB_INFO(inst) ((inst) + 0x00000107), 0x00000104 +#define BF_MBIAS_TRIM_REPEAT_INFO(inst) ((inst) + 0x00000107), 0x00000105 +#define BF_MBIAS_RTRIM_CHOP_CNTL_INFO(inst) ((inst) + 0x00000107), 0x00000206 + +#ifdef USE_PRIVATE_BF +#define REG_MBIAS_IGEN_RTRIM_RB_ADDR(inst) ((inst) + 0x00000108) +#define BF_MBIAS_IGEN_PTATR_CODE_RB_INFO(inst) ((inst) + 0x00000108), 0x00000600 +#define BF_MBIAS_IGEN_PTATR_TRIM_DONE_INFO(inst) ((inst) + 0x00000108), 0x00000106 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_MBIAS_DEGEN_TRIM_RB_ADDR(inst) ((inst) + 0x00000109) +#define BF_MBIAS_DEGEN_TRIM_CODE_RB_INFO(inst) ((inst) + 0x00000109), 0x00000300 +#endif /* USE_PRIVATE_BF */ + +#define REG_MBIAS_IGEN_MISC_ADDR(inst) ((inst) + 0x0000010A) +#define BF_MBIAS_AMUX_SEL_INFO(inst) ((inst) + 0x0000010A), 0x00000400 + +#define REG_MBIAS_IGEN_MISC2_ADDR(inst) ((inst) + 0x0000010B) +#define BF_MBIAS_SPARE_INFO(inst) ((inst) + 0x0000010B), 0x00000800 + +#define REG_MBIAS_EN_CTRL_ADDR(inst) ((inst) + 0x0000010C) +#define BF_MBIAS_DFT_EN_INFO(inst) ((inst) + 0x0000010C), 0x00000100 +#define BF_MBIAS_BANDGAP_VREF_EN_INFO(inst) ((inst) + 0x0000010C), 0x00000104 + +#define REG_MBIAS_BYPASS_RES_CTRL_ADDR(inst) ((inst) + 0x0000010D) +#define BF_MBIAS_BYPASS_BIAS_RES_INFO(inst) ((inst) + 0x0000010D), 0x00000100 +#define BF_MBIAS_BYPASS_ICON_RES_INFO(inst) ((inst) + 0x0000010D), 0x00000204 + +#define REG_MBIAS_CALCLK_CTRL_ADDR(inst) ((inst) + 0x0000010E) +#define BF_MBIAS_CALCLK_EN_INFO(inst) ((inst) + 0x0000010E), 0x00000100 +#define BF_MBIAS_CALCLK_DIV_INFO(inst) ((inst) + 0x0000010E), 0x00000204 + +#define REG_TUNER_CALCLK_CTRL_ADDR(inst) ((inst) + 0x0000010F) +#define BF_TUNER_CALCLK_EN_INFO(inst) ((inst) + 0x0000010F), 0x00000100 +#define BF_TUNER_CALCLK_DIV_INFO(inst) ((inst) + 0x0000010F), 0x00000204 + +#define REG_TUNER_RESET_ADDR(inst) ((inst) + 0x00000110) +#define BF_TUNER_RESET_INFO(inst) ((inst) + 0x00000110), 0x00000100 + +#define REG_ADC_CLK_DIV_CTRL_ADDR(inst) ((inst) + 0x00000122) +#define BF_ADC_CLK_PATH_EN_INFO(inst) ((inst) + 0x00000122), 0x00000100 +#define BF_ADC_DIVBY2_INFO(inst) ((inst) + 0x00000122), 0x00000104 + +#define REG_DAC_CLK_DIV_CTRL_ADDR(inst) ((inst) + 0x00000123) +#define BF_DAC_CLK_PATH_EN_INFO(inst) ((inst) + 0x00000123), 0x00000100 +#define BF_DAC_DIVBY2_INFO(inst) ((inst) + 0x00000123), 0x00000104 + +#define REG_ADC_CLK_INV_ADDR(inst) ((inst) + 0x00000124) +#define BF_ADC_INCLK_INVERT0_INFO(inst) ((inst) + 0x00000124), 0x00000100 +#define BF_ADC_INCLK_INVERT1_INFO(inst) ((inst) + 0x00000124), 0x00000104 + +#define REG_DBG_CLK_CTRL_ADDR(inst) ((inst) + 0x00000125) +#define BF_DEBUG_CLK_EN_INFO(inst) ((inst) + 0x00000125), 0x00000100 +#define BF_DEBUG_CLK_SEL_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x00000125), 0x00000204 + +#define REG_ADC_DBG_CTRL_ADDR(inst) ((inst) + 0x00000126) +#define BF_ADC_DEBUG_EN_INFO(inst) ((inst) + 0x00000126), 0x00000100 +#define BF_ADC_DEBUG_SEL0_INFO(inst) ((inst) + 0x00000126), 0x00000204 +#define BF_ADC_DEBUG_SEL1_INFO(inst) ((inst) + 0x00000126), 0x00000206 + +#define REG_DAC_DBG_CTRL_ADDR(inst) ((inst) + 0x00000127) +#define BF_DAC_DEBUG_EN_INFO(inst) ((inst) + 0x00000127), 0x00000100 +#define BF_DAC_DEBUG_SEL0_INFO(inst) ((inst) + 0x00000127), 0x00000204 +#define BF_DAC_DEBUG_SEL1_INFO(inst) ((inst) + 0x00000127), 0x00000206 + +#define REG_CK_EN_CTRL_ADDR(inst) ((inst) + 0x00000128) +#define BF_EN_CK_TO_ADC_INFO(inst) ((inst) + 0x00000128), 0x00000100 +#define BF_EN_CK_TO_DAC_INFO(inst) ((inst) + 0x00000128), 0x00000101 +#define BF_EN_CK_TO_MCS_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x00000128), 0x00000104 + +#define REG_CK_DEBUG_CTRL_ADDR(inst) ((inst) + 0x00000129) +#define BF_ADC_LATENCY_DEBUG_EN_INFO(inst) ((inst) + 0x00000129), 0x00000100 +#define BF_ADC_SYNC_DEBUG_EN_INFO(inst) ((inst) + 0x00000129), 0x00000101 +#define BF_DAC_LATENCY_DEBUG_EN_INFO(inst) ((inst) + 0x00000129), 0x00000104 +#define BF_DAC_SYNC_DEBUG_EN_INFO(inst) ((inst) + 0x00000129), 0x00000105 + +#define REG_MPU_SEL_ADDR(inst) ((inst) + 0x0000012A) +#define BF_MPU_SELECT_B_INFO(inst) ((inst) + 0x0000012A), 0x00000800 + +#define REG_MPU_CTRL_ADDR(inst) ((inst) + 0x0000012B) +#define BF_MPU_EN_B_INFO(inst) ((inst) + 0x0000012B), 0x00000100 +#define BF_MPU_BUS_PRECHARGE_B_INFO(inst) ((inst) + 0x0000012B), 0x00000404 + +#define REG_MPU_SPARE_ADDR(inst) ((inst) + 0x0000012C) +#define BF_MPU_SPARE_INFO(inst) ((inst) + 0x0000012C), 0x00000800 + +#define REG_TEMPS_MAIN_00_MASTER_BIAS_CTRL_ADDR(inst) ((inst) + 0x00000130) +#define BF_TEMPS_RESET_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x00000130), 0x00000100 +#define BF_TEMPS_START_MEASUREMENT_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x00000130), 0x00000101 +#define BF_TEMPS_MEASUREMENT_READY_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x00000130), 0x00000104 + +#define REG_TEMPS_MAIN_01_MASTER_BIAS_CTRL_ADDR(inst) ((inst) + 0x00000131) + +#define REG_TEMPS_MAIN_02_MASTER_BIAS_CTRL_ADDR(inst) ((inst) + 0x00000132) +#define BF_TEMPS_TEMPERATURE_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x00000132), 0x00000C00 + +#define REG_TEMPS_MAIN_03_MASTER_BIAS_CTRL_ADDR(inst) ((inst) + 0x00000133) +#define BF_TEMPS_OFFSET_ADJ_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x00000133), 0x00000700 + +#define REG_TEMPS_MAIN_04_MASTER_BIAS_CTRL_ADDR(inst) ((inst) + 0x00000134) +#define BF_TEMPS_SLOPE_ADJ_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x00000134), 0x00000800 + +#ifdef USE_PRIVATE_BF +#define REG_TEMPS_PD_RESET_MASTER_BIAS_CTRL_ADDR(inst) ((inst) + 0x00000135) +#define BF_TEMPS_CLK_PD_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x00000135), 0x00000100 +#define BF_TEMPS_STARTUP_PD_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x00000135), 0x00000101 +#define BF_TEMPS_PTAT_PD_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x00000135), 0x00000102 +#define BF_TEMPS_REF_PD_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x00000135), 0x00000103 +#define BF_TEMPS_ADC_PD_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x00000135), 0x00000104 +#define BF_TEMPS_RESET_ADC_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x00000135), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TEMPS_BIAS_PTAT_MASTER_BIAS_CTRL_ADDR(inst) ((inst) + 0x00000136) +#define BF_TEMPS_CURR_PTAT_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x00000136), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TEMPS_BIAS_REF_MASTER_BIAS_CTRL_ADDR(inst) ((inst) + 0x00000137) +#define BF_TEMPS_CURR_REF_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x00000137), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TEMPS_BIAS_IAMP_MASTER_BIAS_CTRL_ADDR(inst) ((inst) + 0x00000138) +#define BF_TEMPS_CURR_IAMP1_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x00000138), 0x00000400 +#define BF_TEMPS_CURR_IAMP2_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x00000138), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TEMPS_BIAS_VCM_MASTER_BIAS_CTRL_ADDR(inst) ((inst) + 0x00000139) +#define BF_TEMPS_CURR_VCM_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x00000139), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TEMPS_BIAS_COMP_MASTER_BIAS_CTRL_ADDR(inst) ((inst) + 0x0000013A) +#define BF_TEMPS_CURR_FLASHO_N_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x0000013A), 0x00000400 +#define BF_TEMPS_CURR_FLASHO_P_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x0000013A), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TEMPS_MUX_IN_MASTER_BIAS_CTRL_ADDR(inst) ((inst) + 0x0000013B) +#define BF_TEMPS_SEL_MUX_VP_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x0000013B), 0x00000300 +#define BF_TEMPS_SEL_MUX_VM_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x0000013B), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TEMPS_MUX_BG_CLK_MASTER_BIAS_CTRL_ADDR(inst) ((inst) + 0x0000013C) +#define BF_TEMPS_SEL_MUX_BG_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x0000013C), 0x00000300 +#define BF_TEMPS_CLK_MUX_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x0000013C), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TEMPS_TEST_CTRL_MASTER_BIAS_CTRL_ADDR(inst) ((inst) + 0x0000013D) +#define BF_TEMPS_TEST_MODE_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x0000013D), 0x00000200 +#define BF_TEMPS_WAIT_TO_MEASURE_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x0000013D), 0x00000302 +#define BF_TEMPS_WAKE_SETTING_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x0000013D), 0x00000305 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TEMPS_TEST_STATE_STEP_MASTER_BIAS_CTRL_ADDR(inst) ((inst) + 0x0000013E) +#define BF_TEMPS_TEST_STATE_ADVANCE_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x0000013E), 0x00000100 +#define BF_TEMPS_TEST_STATE_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x0000013E), 0x00000101 +#define BF_TEMPS_MEASURE_CONTROL_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x0000013E), 0x00000204 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TEMPS_MUX_OBS_CTRL_MASTER_BIAS_CTRL_ADDR(inst) ((inst) + 0x0000013F) +#define BF_TEMPS_MUX_OBS_CTRL_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x0000013F), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TEMPS_MUX_OBS_MASTER_BIAS_CTRL_ADDR(inst) ((inst) + 0x00000140) +#define BF_TEMPS_MUX_OBS_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x00000140), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_TEMPS_TEST_SPARE_00_MASTER_BIAS_CTRL_ADDR(inst) ((inst) + 0x00000141) + +#ifdef USE_PRIVATE_BF +#define REG_TEMPS_TEST_SPARE_01_MASTER_BIAS_CTRL_ADDR(inst) ((inst) + 0x00000142) +#define BF_TEMPS_CTRL_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x00000142), 0x00001000 +#endif /* USE_PRIVATE_BF */ + +#define REG_TEMPS_ADC_AWAKE_ADDR(inst) ((inst) + 0x00000143) +#define BF_TEMPS_ADC_AWAKE_INFO(inst) ((inst) + 0x00000143), 0x00000100 + +#define REG_MB_DAC_GAIN0_LSB_ADDR(inst) ((inst) + 0x00000150) +#define BF_MBIAS_DAC_GAIN0_INFO(inst) ((inst) + 0x00000150), 0x00000A00 + +#define REG_MB_DAC_GAIN0_MSB_ADDR(inst) ((inst) + 0x00000151) + +#define REG_MB_DAC_GAIN1_LSB_ADDR(inst) ((inst) + 0x00000152) +#define BF_MBIAS_DAC_GAIN1_INFO(inst) ((inst) + 0x00000152), 0x00000A00 + +#define REG_MB_DAC_GAIN1_MSB_ADDR(inst) ((inst) + 0x00000153) + +#define REG_MB_DAC_GAIN2_LSB_ADDR(inst) ((inst) + 0x00000154) +#define BF_MBIAS_DAC_GAIN2_INFO(inst) ((inst) + 0x00000154), 0x00000A00 + +#define REG_MB_DAC_GAIN2_MSB_ADDR(inst) ((inst) + 0x00000155) + +#define REG_MB_DAC_GAIN3_LSB_ADDR(inst) ((inst) + 0x00000156) +#define BF_MBIAS_DAC_GAIN3_INFO(inst) ((inst) + 0x00000156), 0x00000A00 + +#define REG_MB_DAC_GAIN3_MSB_ADDR(inst) ((inst) + 0x00000157) + +#define REG_MB_DAC_BLD_GAIN0_LSB_ADDR(inst) ((inst) + 0x00000158) +#define BF_MBIAS_DAC_BLD_GAIN0_INFO(inst) ((inst) + 0x00000158), 0x00000A00 + +#define REG_MB_DAC_BLD_GAIN0_MSB_ADDR(inst) ((inst) + 0x00000159) + +#define REG_MB_DAC_BLD_GAIN1_LSB_ADDR(inst) ((inst) + 0x0000015A) +#define BF_MBIAS_DAC_BLD_GAIN1_INFO(inst) ((inst) + 0x0000015A), 0x00000A00 + +#define REG_MB_DAC_BLD_GAIN1_MSB_ADDR(inst) ((inst) + 0x0000015B) + +#define REG_MB_DAC_BLD_GAIN2_LSB_ADDR(inst) ((inst) + 0x0000015C) +#define BF_MBIAS_DAC_BLD_GAIN2_INFO(inst) ((inst) + 0x0000015C), 0x00000A00 + +#define REG_MB_DAC_BLD_GAIN2_MSB_ADDR(inst) ((inst) + 0x0000015D) + +#define REG_MB_DAC_BLD_GAIN3_LSB_ADDR(inst) ((inst) + 0x0000015E) +#define BF_MBIAS_DAC_BLD_GAIN3_INFO(inst) ((inst) + 0x0000015E), 0x00000A00 + +#define REG_MB_DAC_BLD_GAIN3_MSB_ADDR(inst) ((inst) + 0x0000015F) + +#define REG_DIV_DLYPATH_ADDR(inst) ((inst) + 0x00000160) +#define BF_DIV_EN_DELAY_INFO(inst) ((inst) + 0x00000160), 0x00000100 +#define BF_DIV_PD_TESTPATH_INFO(inst) ((inst) + 0x00000160), 0x00000104 + +#define REG_ADC_DIV_DLYPATH_ADDR(inst) ((inst) + 0x00000161) +#define BF_ADC_DIV_EN_DELAY_INFO(inst) ((inst) + 0x00000161), 0x00000100 +#define BF_ADC_DIV_PD_TESTPATH_INFO(inst) ((inst) + 0x00000161), 0x00000104 + +#define REG_TRIG_CTRL_MASTER_BIAS_CTRL_ADDR(inst) ((inst) + 0x00000162) +#define BF_TRIGGER_ENABLE_INFO(inst) ((inst) + 0x00000162), 0x00000200 +#define BF_TRIGGER_SCHMITT_ENABLE_INFO(inst) ((inst) + 0x00000162), 0x00000104 + +#define REG_PD_DACDIV_CTRL_ADDR(inst) ((inst) + 0x00000163) +#define BF_PD_DAC_DIV_TO_DAC01_INFO(inst) ((inst) + 0x00000163), 0x00000100 +#define BF_PD_DAC_DIV_TO_DAC23_INFO(inst) ((inst) + 0x00000163), 0x00000101 +#define BF_PD_DAC_CORNER_TO_DIV_INFO(inst) ((inst) + 0x00000163), 0x00000104 + +#define REG_CC_CLK_CORN_ADDR(inst) ((inst) + 0x00000165) +#define BF_CC_CLK_CORN_INFO(inst) ((inst) + 0x00000165), 0x00000100 +#define BF_CC_COMP_CORN_INFO(inst) ((inst) + 0x00000165), 0x00000104 + +#define REG_CC_CORN_CFG0_ADDR(inst) ((inst) + 0x00000166) +#define BF_CC_CONFIG_CORN_INFO(inst) ((inst) + 0x00000166), 0x00001000 + +#define REG_CC_CORN_CFG1_ADDR(inst) ((inst) + 0x00000167) + +#define REG_CC_CLK_S_ADDR(inst) ((inst) + 0x00000168) +#define BF_CC_CLK_S_INFO(inst) ((inst) + 0x00000168), 0x00000100 +#define BF_CC_COMP_S_INFO(inst) ((inst) + 0x00000168), 0x00000104 + +#define REG_CC_S_CFG0_ADDR(inst) ((inst) + 0x00000169) +#define BF_CC_CONFIG_S_INFO(inst) ((inst) + 0x00000169), 0x00001000 + +#define REG_CC_S_CFG1_ADDR(inst) ((inst) + 0x0000016A) + +#define REG_CC_CLK_01_ADDR(inst) ((inst) + 0x0000016B) +#define BF_CC_CLK_01_INFO(inst) ((inst) + 0x0000016B), 0x00000100 +#define BF_CC_COMP_01_INFO(inst) ((inst) + 0x0000016B), 0x00000104 + +#define REG_CC_01_CFG0_ADDR(inst) ((inst) + 0x0000016C) +#define BF_CC_CONFIG_01_INFO(inst) ((inst) + 0x0000016C), 0x00001000 + +#define REG_CC_01_CFG1_ADDR(inst) ((inst) + 0x0000016D) + +#define REG_CC_CLK_23_ADDR(inst) ((inst) + 0x0000016E) +#define BF_CC_CLK_23_INFO(inst) ((inst) + 0x0000016E), 0x00000100 +#define BF_CC_COMP_23_INFO(inst) ((inst) + 0x0000016E), 0x00000104 + +#define REG_CC_23_CFG0_ADDR(inst) ((inst) + 0x0000016F) +#define BF_CC_CONFIG_23_INFO(inst) ((inst) + 0x0000016F), 0x00001000 + +#define REG_CC_23_CFG1_ADDR(inst) ((inst) + 0x00000170) + +#define REG_CC_CLK_ADC_ADDR(inst) ((inst) + 0x00000171) +#define BF_CC_CLK_ADC_INFO(inst) ((inst) + 0x00000171), 0x00000100 +#define BF_CC_COMP_ADC_INFO(inst) ((inst) + 0x00000171), 0x00000104 + +#define REG_CC_ADC_CFG0_ADDR(inst) ((inst) + 0x00000172) +#define BF_CC_CONFIG_ADC_INFO(inst) ((inst) + 0x00000172), 0x00001000 + +#define REG_CC_ADC_CFG1_ADDR(inst) ((inst) + 0x00000173) + +#define REG_ADC_LPU_CTRL_ADDR(inst) ((inst) + 0x00000174) +#define BF_DIG_VENUSLPU_CHOP_INFO(inst) ((inst) + 0x00000174), 0x00000100 +#define BF_DIG_VENUSLPU_BUFBYPASS_INFO(inst) ((inst) + 0x00000174), 0x00000101 +#define BF_DIG_VENUSLPU_SEL_INFO(inst) ((inst) + 0x00000174), 0x00000404 + +#define REG_ADC_INV_CTRL0_ADDR(inst) ((inst) + 0x00000175) +#define BF_EN_ADC_INV0_INFO(inst) ((inst) + 0x00000175), 0x00000100 +#define BF_EN_ADC_INV0_XC_INFO(inst) ((inst) + 0x00000175), 0x00000204 + +#define REG_ADC_INV_CTRL1_ADDR(inst) ((inst) + 0x00000176) +#define BF_EN_ADC_INV1_INFO(inst) ((inst) + 0x00000176), 0x00000100 +#define BF_EN_ADC_INV1_XC_INFO(inst) ((inst) + 0x00000176), 0x00000204 + +#define REG_C2B_TL2_CKP_R_PUP_ADDR(inst) ((inst) + 0x00000180) +#define BF_C2B_TL2_CLKP_R_PUP_INFO(inst) ((inst) + 0x00000180), 0x00000500 + +#define REG_C2B_TL2_CKP_R_PDN_ADDR(inst) ((inst) + 0x00000181) +#define BF_C2B_TL2_CLKP_R_PDN_INFO(inst) ((inst) + 0x00000181), 0x00000500 + +#define REG_C2B_TL2_CKN_R_PUP_ADDR(inst) ((inst) + 0x00000182) +#define BF_C2B_TL2_CLKN_R_PUP_INFO(inst) ((inst) + 0x00000182), 0x00000500 + +#define REG_C2B_TL2_CKN_R_PDN_ADDR(inst) ((inst) + 0x00000183) +#define BF_C2B_TL2_CLKN_R_PDN_INFO(inst) ((inst) + 0x00000183), 0x00000500 + +#define REG_C2B_TL2_CKP_C_ADDR(inst) ((inst) + 0x00000184) +#define BF_C2B_TL2_CLKP_C_INFO(inst) ((inst) + 0x00000184), 0x00000500 + +#define REG_C2B_TL2_CKN_C_ADDR(inst) ((inst) + 0x00000185) +#define BF_C2B_TL2_CLKN_C_INFO(inst) ((inst) + 0x00000185), 0x00000500 + +#define REG_C2B_TL2_SYNC_RC_ADDR(inst) ((inst) + 0x00000186) +#define BF_C2B_TL2_SYNC_R_INFO(inst) ((inst) + 0x00000186), 0x00000200 +#define BF_C2B_TL2_SYNC_C_INFO(inst) ((inst) + 0x00000186), 0x00000204 + +#define REG_C2B_TL2_CK_RTERM_ADDR(inst) ((inst) + 0x00000187) +#define BF_C2B_TL2_CLKP_RTERM_PUP_INFO(inst) ((inst) + 0x00000187), 0x00000200 +#define BF_C2B_TL2_CLKP_RTERM_PDN_INFO(inst) ((inst) + 0x00000187), 0x00000202 +#define BF_C2B_TL2_CLKN_RTERM_PUP_INFO(inst) ((inst) + 0x00000187), 0x00000204 +#define BF_C2B_TL2_CLKN_RTERM_PDN_INFO(inst) ((inst) + 0x00000187), 0x00000206 + +#define REG_ADC_TL1_CKP_R_PUP_ADDR(inst) ((inst) + 0x00000188) +#define BF_ADC_TL1_CLKP_R_PUP_INFO(inst) ((inst) + 0x00000188), 0x00000500 + +#define REG_ADC_TL1_CKP_R_PDN_ADDR(inst) ((inst) + 0x00000189) +#define BF_ADC_TL1_CLKP_R_PDN_INFO(inst) ((inst) + 0x00000189), 0x00000500 + +#define REG_ADC_TL1_CKN_R_PUP_ADDR(inst) ((inst) + 0x0000018A) +#define BF_ADC_TL1_CLKN_R_PUP_INFO(inst) ((inst) + 0x0000018A), 0x00000500 + +#define REG_ADC_TL1_CKN_R_PDN_ADDR(inst) ((inst) + 0x0000018B) +#define BF_ADC_TL1_CLKN_R_PDN_INFO(inst) ((inst) + 0x0000018B), 0x00000500 + +#define REG_ADC_TL1_CKP_C_ADDR(inst) ((inst) + 0x0000018C) +#define BF_ADC_TL1_CLKP_C_INFO(inst) ((inst) + 0x0000018C), 0x00000500 + +#define REG_ADC_TL1_CKN_C_ADDR(inst) ((inst) + 0x0000018D) +#define BF_ADC_TL1_CLKN_C_INFO(inst) ((inst) + 0x0000018D), 0x00000500 + +#define REG_ADC_TL1_SYNC_RC_ADDR(inst) ((inst) + 0x0000018E) +#define BF_ADC_TL1_SYNC_R_INFO(inst) ((inst) + 0x0000018E), 0x00000200 +#define BF_ADC_TL1_SYNC_C_INFO(inst) ((inst) + 0x0000018E), 0x00000204 + +#define REG_ADC_TL1_CK_RTERM_ADDR(inst) ((inst) + 0x0000018F) +#define BF_ADC_TL1_CLKP_RTERM_PUP_INFO(inst) ((inst) + 0x0000018F), 0x00000200 +#define BF_ADC_TL1_CLKP_RTERM_PDN_INFO(inst) ((inst) + 0x0000018F), 0x00000202 +#define BF_ADC_TL1_CLKN_RTERM_PUP_INFO(inst) ((inst) + 0x0000018F), 0x00000204 +#define BF_ADC_TL1_CLKN_RTERM_PDN_INFO(inst) ((inst) + 0x0000018F), 0x00000206 + +#define REG_ADC_TL2_CKP_R_PUP_ADDR(inst) ((inst) + 0x00000190) +#define BF_ADC_TL2_CLKP_R_PUP_INFO(inst) ((inst) + 0x00000190), 0x00000500 + +#define REG_ADC_TL2_CKP_R_PDN_ADDR(inst) ((inst) + 0x00000191) +#define BF_ADC_TL2_CLKP_R_PDN_INFO(inst) ((inst) + 0x00000191), 0x00000500 + +#define REG_ADC_TL2_CKN_R_PUP_ADDR(inst) ((inst) + 0x00000192) +#define BF_ADC_TL2_CLKN_R_PUP_INFO(inst) ((inst) + 0x00000192), 0x00000500 + +#define REG_ADC_TL2_CKN_R_PDN_ADDR(inst) ((inst) + 0x00000193) +#define BF_ADC_TL2_CLKN_R_PDN_INFO(inst) ((inst) + 0x00000193), 0x00000500 + +#define REG_ADC_TL2_CKP_C_ADDR(inst) ((inst) + 0x00000194) +#define BF_ADC_TL2_CLKP_C_INFO(inst) ((inst) + 0x00000194), 0x00000500 + +#define REG_ADC_TL2_CKN_C_ADDR(inst) ((inst) + 0x00000195) +#define BF_ADC_TL2_CLKN_C_INFO(inst) ((inst) + 0x00000195), 0x00000500 + +#define REG_ADC_TL2_SYNC_RC_ADDR(inst) ((inst) + 0x00000196) +#define BF_ADC_TL2_SYNC_R_INFO(inst) ((inst) + 0x00000196), 0x00000200 +#define BF_ADC_TL2_SYNC_C_INFO(inst) ((inst) + 0x00000196), 0x00000204 + +#define REG_ADC_TL2_CK_RTERM_ADDR(inst) ((inst) + 0x00000197) +#define BF_ADC_TL2_CLKP_RTERM_PUP_INFO(inst) ((inst) + 0x00000197), 0x00000200 +#define BF_ADC_TL2_CLKP_RTERM_PDN_INFO(inst) ((inst) + 0x00000197), 0x00000202 +#define BF_ADC_TL2_CLKN_RTERM_PUP_INFO(inst) ((inst) + 0x00000197), 0x00000204 +#define BF_ADC_TL2_CLKN_RTERM_PDN_INFO(inst) ((inst) + 0x00000197), 0x00000206 + +#define REG_C2S_CKP_R_PUP_ADDR(inst) ((inst) + 0x00000198) +#define BF_C2S_CLKP_R_PUP_INFO(inst) ((inst) + 0x00000198), 0x00000500 + +#define REG_C2S_CKP_R_PDN_ADDR(inst) ((inst) + 0x00000199) +#define BF_C2S_CLKP_R_PDN_INFO(inst) ((inst) + 0x00000199), 0x00000500 + +#define REG_C2S_CKN_R_PUP_ADDR(inst) ((inst) + 0x0000019A) +#define BF_C2S_CLKN_R_PUP_INFO(inst) ((inst) + 0x0000019A), 0x00000500 + +#define REG_C2S_CKN_R_PDN_ADDR(inst) ((inst) + 0x0000019B) +#define BF_C2S_CLKN_R_PDN_INFO(inst) ((inst) + 0x0000019B), 0x00000500 + +#define REG_C2S_CKP_C_ADDR(inst) ((inst) + 0x0000019C) +#define BF_C2S_CLKP_C_INFO(inst) ((inst) + 0x0000019C), 0x00000500 + +#define REG_C2S_CKN_C_ADDR(inst) ((inst) + 0x0000019D) +#define BF_C2S_CLKN_C_INFO(inst) ((inst) + 0x0000019D), 0x00000500 + +#define REG_C2S_SYNC_RC_ADDR(inst) ((inst) + 0x0000019E) +#define BF_C2S_SYNC_R_INFO(inst) ((inst) + 0x0000019E), 0x00000200 +#define BF_C2S_SYNC_C_INFO(inst) ((inst) + 0x0000019E), 0x00000204 + +#define REG_C2S_CK_RTERM_ADDR(inst) ((inst) + 0x0000019F) +#define BF_C2S_CLKP_RTERM_PUP_INFO(inst) ((inst) + 0x0000019F), 0x00000200 +#define BF_C2S_CLKP_RTERM_PDN_INFO(inst) ((inst) + 0x0000019F), 0x00000202 +#define BF_C2S_CLKN_RTERM_PUP_INFO(inst) ((inst) + 0x0000019F), 0x00000204 +#define BF_C2S_CLKN_RTERM_PDN_INFO(inst) ((inst) + 0x0000019F), 0x00000206 + +#define REG_S01_CKP_R_PUP_ADDR(inst) ((inst) + 0x000001A0) +#define BF_S01_CLKP_R_PUP_INFO(inst) ((inst) + 0x000001A0), 0x00000500 + +#define REG_S01_CKP_R_PDN_ADDR(inst) ((inst) + 0x000001A1) +#define BF_S01_CLKP_R_PDN_INFO(inst) ((inst) + 0x000001A1), 0x00000500 + +#define REG_S01_CKN_R_PUP_ADDR(inst) ((inst) + 0x000001A2) +#define BF_S01_CLKN_R_PUP_INFO(inst) ((inst) + 0x000001A2), 0x00000500 + +#define REG_S01_CKN_R_PDN_ADDR(inst) ((inst) + 0x000001A3) +#define BF_S01_CLKN_R_PDN_INFO(inst) ((inst) + 0x000001A3), 0x00000500 + +#define REG_S01_CKP_C_ADDR(inst) ((inst) + 0x000001A4) +#define BF_S01_CLKP_C_INFO(inst) ((inst) + 0x000001A4), 0x00000500 + +#define REG_S01_CKN_C_ADDR(inst) ((inst) + 0x000001A5) +#define BF_S01_CLKN_C_INFO(inst) ((inst) + 0x000001A5), 0x00000500 + +#define REG_S01_SYNC_RC_ADDR(inst) ((inst) + 0x000001A6) +#define BF_S01_SYNC_R_INFO(inst) ((inst) + 0x000001A6), 0x00000200 +#define BF_S01_SYNC_C_INFO(inst) ((inst) + 0x000001A6), 0x00000204 + +#define REG_S01_CK_RTERM_ADDR(inst) ((inst) + 0x000001A7) +#define BF_S01_CLKP_RTERM_PUP_INFO(inst) ((inst) + 0x000001A7), 0x00000200 +#define BF_S01_CLKP_RTERM_PDN_INFO(inst) ((inst) + 0x000001A7), 0x00000202 +#define BF_S01_CLKN_RTERM_PUP_INFO(inst) ((inst) + 0x000001A7), 0x00000204 +#define BF_S01_CLKN_RTERM_PDN_INFO(inst) ((inst) + 0x000001A7), 0x00000206 + +#define REG_S23_CKP_R_PUP_ADDR(inst) ((inst) + 0x000001A8) +#define BF_S23_CLKP_R_PUP_INFO(inst) ((inst) + 0x000001A8), 0x00000500 + +#define REG_S23_CKP_R_PDN_ADDR(inst) ((inst) + 0x000001A9) +#define BF_S23_CLKP_R_PDN_INFO(inst) ((inst) + 0x000001A9), 0x00000500 + +#define REG_S23_CKN_R_PUP_ADDR(inst) ((inst) + 0x000001AA) +#define BF_S23_CLKN_R_PUP_INFO(inst) ((inst) + 0x000001AA), 0x00000500 + +#define REG_S23_CKN_R_PDN_ADDR(inst) ((inst) + 0x000001AB) +#define BF_S23_CLKN_R_PDN_INFO(inst) ((inst) + 0x000001AB), 0x00000500 + +#define REG_S23_CKP_C_ADDR(inst) ((inst) + 0x000001AC) +#define BF_S23_CLKP_C_INFO(inst) ((inst) + 0x000001AC), 0x00000500 + +#define REG_S23_CKN_C_ADDR(inst) ((inst) + 0x000001AD) +#define BF_S23_CLKN_C_INFO(inst) ((inst) + 0x000001AD), 0x00000500 + +#define REG_S23_SYNC_RC_ADDR(inst) ((inst) + 0x000001AE) +#define BF_S23_SYNC_R_INFO(inst) ((inst) + 0x000001AE), 0x00000200 +#define BF_S23_SYNC_C_INFO(inst) ((inst) + 0x000001AE), 0x00000204 + +#define REG_S23_CK_RTERM_ADDR(inst) ((inst) + 0x000001AF) +#define BF_S23_CLKP_RTERM_PUP_INFO(inst) ((inst) + 0x000001AF), 0x00000200 +#define BF_S23_CLKP_RTERM_PDN_INFO(inst) ((inst) + 0x000001AF), 0x00000202 +#define BF_S23_CLKN_RTERM_PUP_INFO(inst) ((inst) + 0x000001AF), 0x00000204 +#define BF_S23_CLKN_RTERM_PDN_INFO(inst) ((inst) + 0x000001AF), 0x00000206 + +#endif /* __ADI_APOLLO_BF_MASTER_BIAS_CTRL_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_mb_regs.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_mb_regs.h new file mode 100644 index 00000000000000..24ad649a837e91 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_mb_regs.h @@ -0,0 +1,161 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:18 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_MB_REGS_H__ +#define __ADI_APOLLO_BF_MB_REGS_H__ + +/*============= D E F I N E S ==============*/ +#define REG_MCR_ADDR 0x4C006000 +#define BF_E_MDR_CLEAR_INFO 0x4C006000, 0x00000100 +#define BF_H_WR_DISABLE_INFO 0x4C006000, 0x00000101 + +#define REG_IRQ_ENABLE_ADDR 0x4C006004 +#define BF_HREQ_ACK_IRQEN_INFO 0x4C006004, 0x00000100 +#define BF_ERESP_RDY_IRQEN_INFO 0x4C006004, 0x00000101 +#define BF_HREQ_RDY_IRQEN_INFO 0x4C006004, 0x00000102 +#define BF_ERESP_ACK_IRQEN_INFO 0x4C006004, 0x00000103 + +#define REG_E_STATUS_ADDR 0x4C006020 +#define BF_HREQ_ACK_INFO 0x4C006020, 0x00000100 +#define BF_ERESP_RDY_INFO 0x4C006020, 0x00000101 + +#define REG_ERC_ADDR(n) (0x4C006040 + 4 * (n)) +#define BF_ERESP_CODE_INFO(n) (0x4C006040 + 4 * (n)), 0x00002000 + +#define REG_H_STATUS_ADDR 0x4C006120 +#define BF_HREQ_RDY_INFO 0x4C006120, 0x00000100 +#define BF_ERESP_ACK_INFO 0x4C006120, 0x00000101 + +#define REG_HRC_ADDR(n) (0x4C006140 + 4 * (n)) +#define BF_HREQ_CODE_INFO(n) (0x4C006140 + 4 * (n)), 0x00002000 + +#define REG_MDR_ADDR(n) (0x4C006200 + 4 * (n)) +#define BF_MB_DATA_REG_INFO(n) (0x4C006200 + 4 * (n)), 0x00002000 + +#define REG_RSTINFO_ADDR 0x4C006310 +#define BF_SYSRESETREQ_INFO 0x4C006310, 0x00000100 +#define BF_WATCHDOG_INFO 0x4C006310, 0x00000101 +#define BF_LOCKUP_INFO 0x4C006310, 0x00000102 + +#define REG_ROM_ERR_ST_ADDR 0x4C006320 +#define BF_ROM_ERR_INFO 0x4C006320, 0x00000100 + +#define REG_ROM_ERR_ADDR_ADDR 0x4C006324 +#define BF_ROM_ERR_ADDR_INFO 0x4C006324, 0x00002000 + +#define REG_ROM_ERR_DATA_ADDR 0x4C006328 +#define BF_ROM_ERR_DATA_INFO 0x4C006328, 0x00002000 + +#define REG_ROM_ERR_PARITY_ADDR 0x4C00632C +#define BF_ROM_ERR_PARITY_INFO 0x4C00632C, 0x00002000 + +#define REG_SRAM_ERR_ST_ADDR 0x4C006330 +#define BF_SRAM_ERR_INFO 0x4C006330, 0x00000100 + +#define REG_SRAM_ERR_ADDR_ADDR 0x4C006334 +#define BF_SRAM_ERR_ADDR_INFO 0x4C006334, 0x00002000 + +#define REG_SRAM_ERR_DATA_ADDR 0x4C006338 +#define BF_SRAM_ERR_DATA_INFO 0x4C006338, 0x00002000 + +#define REG_SRAM_ERR_PARITY_ADDR 0x4C00633C +#define BF_SRAM_ERR_PARITY_INFO 0x4C00633C, 0x00002000 + +#define REG_BOOT_FLOW0_ADDR 0x4C006340 +#define BF_PLATFORM_INIT_START_INFO 0x4C006340, 0x00000100 +#define BF_IS_SELF_BOOT_INFO 0x4C006340, 0x00000101 +#define BF_LIFECYCLE_INFO 0x4C006340, 0x00000302 +#define BF_CRYPTO_SELFTESTS_START_INFO 0x4C006340, 0x00000105 +#define BF_LOAD_AND_UNWRAP_KEYS_INFO 0x4C006340, 0x00000106 +#define BF_IS_SECURE_BOOT_INFO 0x4C006340, 0x00000107 +#define BF_WARMBOOT_INFO 0x4C006340, 0x00000108 +#define BF_SBS_FAIL_SBH2_PRESENT_INFO 0x4C006340, 0x00000109 +#define BF_ENC_FW_REQUIRED_INFO 0x4C006340, 0x0000010A +#define BF_ENC_FW_PRESENT_INFO 0x4C006340, 0x0000010B +#define BF_APP_RESET_INFO 0x4C006340, 0x0000010C +#define BF_SBS_ADDR1_1ST_ATTEMPT_INFO 0x4C006340, 0x0000010D +#define BF_OPEN_SAMPLE_INFO 0x4C006340, 0x0000010E +#define BF_BOOT_FAILED_INFO 0x4C006340, 0x0000010F +#define BF_SECURE_BOOT_STAGE_0_INFO 0x4C006340, 0x00000810 +#define BF_SECURE_BOOT_STAGE_1_INFO 0x4C006340, 0x00000818 + +#define REG_BOOT_FLOW1_ADDR 0x4C006344 +#define BF_SECURE_BOOT_STAGE_2_INFO 0x4C006344, 0x00000800 +#define BF_ERROR_CODE_0_INFO 0x4C006344, 0x00000C08 +#define BF_ERROR_CODE_1_INFO 0x4C006344, 0x00000C14 + +#define REG_BOOT_AUX_STATE_ADDR 0x4C006348 +#define BF_BOOT_AUX_STATE_INFO 0x4C006348, 0x00002000 + +#define REG_ECC_ERROR_ADDR 0x4C006350 +#define BF_ECC_1BIT_ERR_INFO 0x4C006350, 0x00000100 +#define BF_ECC_2BIT_ERR_INFO 0x4C006350, 0x00000101 +#define BF_ERROR_ADDR_INFO 0x4C006350, 0x00000A10 + +#define REG_BOOT_STATUS_ADDR 0x4C006358 +#define BF_LOCKOUT_INFO 0x4C006358, 0x00000100 +#define BF_CRC_MISMATCH_INFO 0x4C006358, 0x00000101 +#define BF_NVM_RDY_INFO 0x4C006358, 0x00000102 +#ifdef USE_HW_BF +#define BF_HW_FSM_BOOT_ERROR_INFO 0x4C006358, 0x0000010F +#endif /* USE_HW_BF */ +#ifdef USE_HW_BF +#define BF_HW_FSM_STATUS_INFO 0x4C006358, 0x00001010 +#endif /* USE_HW_BF */ + +#define REG_CHIP_EXPORT_SHADOW0_ADDR 0x4C006360 +#define BF_CHIP_EXPORT_SHADOW0_INFO 0x4C006360, 0x00002000 + +#define REG_CHIP_EXPORT_SHADOW1_ADDR 0x4C006364 +#define BF_CHIP_EXPORT_SHADOW1_INFO 0x4C006364, 0x00002000 + +#define REG_CHIP_EXPORT_SHADOW2_ADDR 0x4C006368 +#define BF_CHIP_EXPORT_SHADOW2_INFO 0x4C006368, 0x00002000 + +#define REG_CHIP_EXPORT_SHADOW3_ADDR 0x4C00636C +#define BF_CHIP_EXPORT_SHADOW3_INFO 0x4C00636C, 0x00002000 + +#define REG_CHIP_EXPORT_SHADOW4_ADDR 0x4C006370 +#define BF_CHIP_EXPORT_SHADOW4_INFO 0x4C006370, 0x00002000 + +#define REG_CHIP_EXPORT_SHADOW5_ADDR 0x4C006374 +#define BF_CHIP_EXPORT_SHADOW5_INFO 0x4C006374, 0x00002000 + +#define REG_CHIP_EXPORT_SHADOW6_ADDR 0x4C006378 +#define BF_CHIP_EXPORT_SHADOW6_INFO 0x4C006378, 0x00002000 + +#define REG_CHIP_EXPORT_SHADOW7_ADDR 0x4C00637C +#define BF_CHIP_EXPORT_SHADOW7_INFO 0x4C00637C, 0x00002000 + +#define REG_NO_ECC_SHADOW0_ADDR 0x4C006380 +#define BF_NOECC_SHADOW0_INFO 0x4C006380, 0x00002000 + +#define REG_NO_ECC_SHADOW1_ADDR 0x4C006384 +#define BF_NOECC_SHADOW1_INFO 0x4C006384, 0x00002000 + +#define REG_NO_ECC_SHADOW2_ADDR 0x4C006388 +#define BF_NOECC_SHADOW2_INFO 0x4C006388, 0x00002000 + +#define REG_NO_ECC_SHADOW3_ADDR 0x4C00638C +#define BF_NOECC_SHADOW3_INFO 0x4C00638C, 0x00002000 + +#define REG_LIFECYCLE_STATUS_ADDR 0x4C0063A0 +#define BF_LIFECYCLE_TR_INFO 0x4C0063A0, 0x00000A00 +#define BF_LIFECYCLE_ENCODE_INFO 0x4C0063A0, 0x00000410 + +#define REG_VERSION_ADDR 0x4C0063FC +#define BF_VERSION_INFO 0x4C0063FC, 0x00000800 + +#endif /* __ADI_APOLLO_BF_MB_REGS_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_mcs_c_only.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_mcs_c_only.h new file mode 100644 index 00000000000000..4cd4eeca30a504 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_mcs_c_only.h @@ -0,0 +1,119 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:18 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_MCS_C_ONLY_H__ +#define __ADI_APOLLO_BF_MCS_C_ONLY_H__ + +/*============= D E F I N E S ==============*/ +#define REG_PLL_CTRL0_ADDR 0x4C001500 +#define BF_PLL_REFCLK_EN_INFO 0x4C001500, 0x00000100 +#define BF_PLL_DEVCLK_BYP_BIAS_R_INFO 0x4C001500, 0x00000104 + +#define REG_PLL_CTRL1_ADDR 0x4C001501 +#define BF_CLKPLL_RESET_INFO 0x4C001501, 0x00000100 + +#define REG_PLL_DEVCLK_BUF_TRIM_ADDR 0x4C001502 +#define BF_PLL_DEVCLK_CLKBUF_OFFSET_EN_INFO 0x4C001502, 0x00000100 +#define BF_PLL_DEVCLK_CLKBUF_TRM_VCM_INFO 0x4C001502, 0x00000304 + +#define REG_PLL_DEVCLK_BUF_TERM_ADDR 0x4C001503 +#define BF_PLL_DEVCLK_CLKBUF_TERM_EN_INFO 0x4C001503, 0x00000100 +#define BF_PLL_DEVCLK_CLKBUF_TRM_IBIAS_INFO 0x4C001503, 0x00000204 + +#define REG_DRV_EN_CTRL_ADDR 0x4C001504 +#define BF_EN_DRV_I_A_INFO 0x4C001504, 0x00000100 +#define BF_EN_DRV_I_B_INFO 0x4C001504, 0x00000101 + +#define REG_TRIG_CTRL0_ADDR 0x4C001505 +#define BF_TRIGGER_EN_MCS_C_ONLY_INFO 0x4C001505, 0x00000100 +#define BF_TRIGGER_LEVEL_INFO 0x4C001505, 0x00000104 + +#define REG_CK_TO_MCS_EN_ADDR 0x4C001506 +#define BF_EN_CK_TO_MCS_MCS_C_ONLY_INFO 0x4C001506, 0x00000100 + +#define REG_CC_CLK_CTRL_ADDR 0x4C001507 +#define BF_CC_CLK_C_INFO 0x4C001507, 0x00000100 +#define BF_CC_COMP_C_INFO 0x4C001507, 0x00000104 + +#define REG_CC_CFG0_ADDR 0x4C001508 +#define BF_CC_CONFIG_C_INFO 0x4C001508, 0x00001000 + +#define REG_CC_CFG1_ADDR 0x4C001509 + +#define REG_C2AB_PRE_SYNC_ADDR 0x4C00150A + +#define REG_SEL_ODRV_ADDR 0x4C00150B +#define BF_SEL_ODRV_MUX_INFO 0x4C00150B, 0x00000100 + +#define REG_PLL_TDC_PATH_EN_ADDR 0x4C00150C +#define BF_PLL_DEVCLK_TDC_PATH_EN_INFO 0x4C00150C, 0x00000100 + +#define REG_C2A_TL1_CKP_R_PUP_ADDR 0x4C00150D +#define BF_C2A_TL1_CLKP_R_PUP_INFO 0x4C00150D, 0x00000500 + +#define REG_C2A_TL1_CKP_R_PDN_ADDR 0x4C00150E +#define BF_C2A_TL1_CLKP_R_PDN_INFO 0x4C00150E, 0x00000500 + +#define REG_C2A_TL1_CKN_R_PUP_ADDR 0x4C00150F +#define BF_C2A_TL1_CLKN_R_PUP_INFO 0x4C00150F, 0x00000500 + +#define REG_C2A_TL1_CKN_R_PDN_ADDR 0x4C001510 +#define BF_C2A_TL1_CLKN_R_PDN_INFO 0x4C001510, 0x00000500 + +#define REG_C2A_TL1_CKP_C_ADDR 0x4C001511 +#define BF_C2A_TL1_CLKP_C_INFO 0x4C001511, 0x00000500 + +#define REG_C2A_TL1_CKN_C_ADDR 0x4C001512 +#define BF_C2A_TL1_CLKN_C_INFO 0x4C001512, 0x00000500 + +#define REG_C2A_TL1_SYNC_RC_ADDR 0x4C001513 +#define BF_C2A_TL1_SYNC_R_INFO 0x4C001513, 0x00000200 +#define BF_C2A_TL1_SYNC_C_INFO 0x4C001513, 0x00000204 + +#define REG_C2A_TL1_CK_RTERM_ADDR 0x4C001514 +#define BF_C2A_TL1_CLKP_RTERM_PUP_INFO 0x4C001514, 0x00000200 +#define BF_C2A_TL1_CLKP_RTERM_PDN_INFO 0x4C001514, 0x00000202 +#define BF_C2A_TL1_CLKN_RTERM_PUP_INFO 0x4C001514, 0x00000204 +#define BF_C2A_TL1_CLKN_RTERM_PDN_INFO 0x4C001514, 0x00000206 + +#define REG_C2B_TL1_CKP_R_PUP_ADDR 0x4C001515 +#define BF_C2B_TL1_CLKP_R_PUP_INFO 0x4C001515, 0x00000500 + +#define REG_C2B_TL1_CKP_R_PDN_ADDR 0x4C001516 +#define BF_C2B_TL1_CLKP_R_PDN_INFO 0x4C001516, 0x00000500 + +#define REG_C2B_TL1_CKN_R_PUP_ADDR 0x4C001517 +#define BF_C2B_TL1_CLKN_R_PUP_INFO 0x4C001517, 0x00000500 + +#define REG_C2B_TL1_CKN_R_PDN_ADDR 0x4C001518 +#define BF_C2B_TL1_CLKN_R_PDN_INFO 0x4C001518, 0x00000500 + +#define REG_C2B_TL1_CKP_C_ADDR 0x4C001519 +#define BF_C2B_TL1_CLKP_C_INFO 0x4C001519, 0x00000500 + +#define REG_C2B_TL1_CKN_C_ADDR 0x4C00151A +#define BF_C2B_TL1_CLKN_C_INFO 0x4C00151A, 0x00000500 + +#define REG_C2B_TL1_SYNC_RC_ADDR 0x4C00151B +#define BF_C2B_TL1_SYNC_R_INFO 0x4C00151B, 0x00000200 +#define BF_C2B_TL1_SYNC_C_INFO 0x4C00151B, 0x00000204 + +#define REG_C2B_TL1_CK_RTERM_ADDR 0x4C00151C +#define BF_C2B_TL1_CLKP_RTERM_PUP_INFO 0x4C00151C, 0x00000200 +#define BF_C2B_TL1_CLKP_RTERM_PDN_INFO 0x4C00151C, 0x00000202 +#define BF_C2B_TL1_CLKN_RTERM_PUP_INFO 0x4C00151C, 0x00000204 +#define BF_C2B_TL1_CLKN_RTERM_PDN_INFO 0x4C00151C, 0x00000206 + +#endif /* __ADI_APOLLO_BF_MCS_C_ONLY_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_mcs_sync.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_mcs_sync.h new file mode 100644 index 00000000000000..6470538f8bd19f --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_mcs_sync.h @@ -0,0 +1,152 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:18 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_MCS_SYNC_H__ +#define __ADI_APOLLO_BF_MCS_SYNC_H__ + +/*============= D E F I N E S ==============*/ +#define MCS_SYNC_MCSTOP0 0x4C001410 +#define MCS_SYNC_MCSTOP1 0x4C001810 +#define MCS_SYNC_MCSTOP2 0x4C001C10 + +#define REG_CLOCKING_MODE_ADDR(inst) ((inst) + 0x00000000) +#define BF_MCS_DIVG_EN_INFO(inst) ((inst) + 0x00000000), 0x00000100 +#define BF_CLOCKING_MODE_INFO(inst) ((inst) + 0x00000000), 0x00000204 + +#define REG_SYNC_SYSREF_DELAY_0_ADDR(inst) ((inst) + 0x00000001) +#define BF_SYNC_SYSREF_DELAY_INFO(inst) ((inst) + 0x00000001), 0x00001000 + +#define REG_SYNC_SYSREF_DELAY_1_ADDR(inst) ((inst) + 0x00000002) + +#define REG_SYSREF_COUNT_ADDR(inst) ((inst) + 0x00000003) +#define BF_SYSREF_COUNT_INFO(inst) ((inst) + 0x00000003), 0x00000800 + +#define REG_SYSREF_PHASE0_ADDR(inst) ((inst) + 0x00000004) +#define BF_SYSREF_PHASE_INFO(inst) ((inst) + 0x00000004), 0x00001300 + +#define REG_SYSREF_PHASE1_ADDR(inst) ((inst) + 0x00000005) + +#define REG_SYSREF_PHASE2_ADDR(inst) ((inst) + 0x00000006) + +#define REG_SYSREF_ERR_WINDOW_ADDR(inst) ((inst) + 0x00000007) +#define BF_SYSREF_ERR_WINDOW_INFO(inst) ((inst) + 0x00000007), 0x00000700 +#define BF_SYSREF_WITHIN_ERRWINDOW_INFO(inst) ((inst) + 0x00000007), 0x00000107 + +#define REG_SYNC_MODE_ADDR(inst) ((inst) + 0x00000008) +#define BF_DYN_CFG_SYNC_INFO(inst) ((inst) + 0x00000008), 0x00000100 +#define BF_ONESHOT_SYNC_INFO(inst) ((inst) + 0x00000008), 0x00000101 +#define BF_MANUAL_SYNC_INFO(inst) ((inst) + 0x00000008), 0x00000102 +#define BF_TRIGGER_SYNC_INFO(inst) ((inst) + 0x00000008), 0x00000103 +#define BF_DYN_CFG_SYNC_DONE_INFO(inst) ((inst) + 0x00000008), 0x00000104 +#define BF_ONESHOT_SYNC_DONE_INFO(inst) ((inst) + 0x00000008), 0x00000105 +#define BF_MANUAL_SYNC_DONE_INFO(inst) ((inst) + 0x00000008), 0x00000106 +#define BF_TRIGGER_SYNC_DONE_INFO(inst) ((inst) + 0x00000008), 0x00000107 + +#define REG_SOFT_OFFON_MODE_ADDR(inst) ((inst) + 0x00000009) +#ifdef USE_PRIVATE_BF +#define BF_SOFT_OFFON_MODE_INFO(inst) ((inst) + 0x00000009), 0x00000200 +#endif /* USE_PRIVATE_BF */ +#define BF_TRIGGER_SYNC_MODE_INFO(inst) ((inst) + 0x00000009), 0x00000104 + +#define REG_SYSREF_AVERAGE_ADDR(inst) ((inst) + 0x0000000A) +#define BF_SYSREF_AVERAGE_INFO(inst) ((inst) + 0x0000000A), 0x00000300 + +#define REG_SUBCLASS_SEL_ADDR(inst) ((inst) + 0x0000000B) +#define BF_SUBCLASS_SEL_INFO(inst) ((inst) + 0x0000000B), 0x00000100 + +#ifdef USE_PRIVATE_BF +#define REG_NCO_SYNC_MS_TRIG_ADDR(inst) ((inst) + 0x0000000C) +#define BF_NCO_SYNC_MS_TRIG_INFO(inst) ((inst) + 0x0000000C), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_NCOSYNC_SYSREF_MODE_ADDR(inst) ((inst) + 0x0000000D) +#define BF_NCO_SYNC_SYSREF_MODE_TX_INFO(inst) ((inst) + 0x0000000D), 0x00000200 +#define BF_NCO_SYNC_SYSREF_MODE_RX_INFO(inst) ((inst) + 0x0000000D), 0x00000202 +#define BF_RXNCOSYNC_SYSREF_ONESHOT_INFO(inst) ((inst) + 0x0000000D), 0x00000105 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_NCOSYNC_MS_MODE_ADDR(inst) ((inst) + 0x0000000E) +#define BF_NCO_SYNC_MS_MODE_INFO(inst) ((inst) + 0x0000000E), 0x00000200 +#define BF_NCO_SYNC_MS_TRIG_SOURCE_INFO(inst) ((inst) + 0x0000000E), 0x00000202 +#define BF_NCO_SYNC_MS_EXTRA_LMFC_NUM_INFO(inst) ((inst) + 0x0000000E), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#define REG_MCS_RESET_ADDR(inst) ((inst) + 0x0000000F) +#define BF_SYNCLOGIC_RESET_INFO(inst) ((inst) + 0x0000000F), 0x00000100 +#define BF_MCSTDC_RESET_INFO(inst) ((inst) + 0x0000000F), 0x00000101 +#define BF_MBTRIM_RESET_INFO(inst) ((inst) + 0x0000000F), 0x00000102 + +#define REG_SYNCTRL_FSM_0_ADDR(inst) ((inst) + 0x00000010) +#define BF_SYNCTRL_FSM_INFO(inst) ((inst) + 0x00000010), 0x00001000 + +#define REG_SYNCTRL_FSM_1_ADDR(inst) ((inst) + 0x00000011) + +#define REG_SYNCTRL_MAN_0_ADDR(inst) ((inst) + 0x00000012) +#define BF_SYNCTRL_MAN_INFO(inst) ((inst) + 0x00000012), 0x00001000 + +#define REG_SYNCTRL_MAN_1_ADDR(inst) ((inst) + 0x00000013) + +#define REG_SYNCSTEP_INTERVAL_ADDR(inst) ((inst) + 0x00000014) +#define BF_CYCLES_BF_SYNCSTEP_INFO(inst) ((inst) + 0x00000014), 0x00000400 +#define BF_CYCLES_AF_SYNCSTEP_INFO(inst) ((inst) + 0x00000014), 0x00000404 + +#ifdef USE_PRIVATE_BF +#define REG_SYNC_DEBUG0_ADDR(inst) ((inst) + 0x00000015) +#define BF_AVRG_IN_MONITOR_EN_INFO(inst) ((inst) + 0x00000015), 0x00000100 +#define BF_AVRG_FLOW_EN_INFO(inst) ((inst) + 0x00000015), 0x00000105 +#endif /* USE_PRIVATE_BF */ + +#define REG_SYNC_DEBUG1_ADDR(inst) ((inst) + 0x00000016) +#define BF_SYNC_STATE_INFO(inst) ((inst) + 0x00000016), 0x00000300 +#ifdef USE_PRIVATE_BF +#define BF_SOFT_OFFON_STATE_INFO(inst) ((inst) + 0x00000016), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#define REG_INT_SYSREF_PERIOD_0_ADDR(inst) ((inst) + 0x00000017) +#define BF_INT_SYSREF_PERIOD_INFO(inst) ((inst) + 0x00000017), 0x00001000 + +#define REG_INT_SYSREF_PERIOD_1_ADDR(inst) ((inst) + 0x00000018) + +#define REG_TRIG_PHASE_0_ADDR(inst) ((inst) + 0x00000019) +#define BF_TRIG_PHASE_INFO(inst) ((inst) + 0x00000019), 0x00001000 + +#define REG_TRIG_PHASE_1_ADDR(inst) ((inst) + 0x0000001A) + +#define REG_SYNC_MASK_ADC_ADDR(inst) ((inst) + 0x0000001B) +#define BF_SYNC_MASK_ADC_INFO(inst) ((inst) + 0x0000001B), 0x00000400 + +#define REG_SYNC_MASK_DAC_ADDR(inst) ((inst) + 0x0000001C) +#define BF_SYNC_MASK_DAC_INFO(inst) ((inst) + 0x0000001C), 0x00000800 + +#define REG_SYNC_MASK_AB_ADDR(inst) ((inst) + 0x0000001D) +#define BF_SYNC_MASK_ADC_AB_INFO(inst) ((inst) + 0x0000001D), 0x00000200 +#define BF_SYNC_MASK_DAC_AB_INFO(inst) ((inst) + 0x0000001D), 0x00000404 + +#define REG_MANUAL_ROT_CENTER_ADDR(inst) ((inst) + 0x00000020) +#define BF_MASTERDIV_MANUAL_ROT_INFO(inst) ((inst) + 0x00000020), 0x00000100 + +#define REG_MASTERDIV4_ROT_MAP_ADDR(inst) ((inst) + 0x00000021) +#define BF_MASTERDIV4_ROTMAP_INFO(inst) ((inst) + 0x00000021), 0x00000800 + +#define REG_MASTERDIV8_ROT_MAP_0_ADDR(inst) ((inst) + 0x0000002A) +#define BF_MASTERDIV8_ROTMAP_INFO(inst) ((inst) + 0x0000002A), 0x00001800 + +#define REG_MASTERDIV8_ROT_MAP_1_ADDR(inst) ((inst) + 0x0000002B) + +#define REG_MASTERDIV8_ROT_MAP_2_ADDR(inst) ((inst) + 0x0000002C) + +#endif /* __ADI_APOLLO_BF_MCS_SYNC_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_mcs_tdc.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_mcs_tdc.h new file mode 100644 index 00000000000000..653eb5e547bb69 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_mcs_tdc.h @@ -0,0 +1,225 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:18 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_MCS_TDC_H__ +#define __ADI_APOLLO_BF_MCS_TDC_H__ + +/*============= D E F I N E S ==============*/ +#define MCS_TDC_MCSTOP0 0x4C001480 +#define MCS_TDC_MCSTOP1 0x4C001880 +#define MCS_TDC_MCSTOP2 0x4C001C80 + +#ifdef USE_PRIVATE_BF +#define REG_MCS_EN_CTRL_ADDR(inst) ((inst) + 0x00000000) +#define BF_TDC_EN_INFO(inst) ((inst) + 0x00000000), 0x00000100 +#define BF_DTLL_EN_INFO(inst) ((inst) + 0x00000000), 0x00000104 +#define BF_TDC_DIG_EN_INFO(inst) ((inst) + 0x00000000), 0x00000105 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_MCS_IRQ_CTRL_ADDR(inst) ((inst) + 0x00000001) +#define BF_MCS_SYSREF_IN_FSM_START_INFO(inst) ((inst) + 0x00000001), 0x00000100 +#define BF_MCS_SYSREF_IN_IRQ_RECVD_INFO(inst) ((inst) + 0x00000001), 0x00000101 +#define BF_MCS_MEASURE_DONE_INFO(inst) ((inst) + 0x00000001), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TDC_MUX_CTRL_ADDR(inst) ((inst) + 0x00000002) +#define BF_TDC_A_MUX_SEL_INFO(inst) ((inst) + 0x00000002), 0x00000300 +#define BF_TDC_B_MUX_SEL_INFO(inst) ((inst) + 0x00000002), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TDC_FREQ_CTRL_ADDR(inst) ((inst) + 0x00000003) +#define BF_TDC_FREQ_CTRL_INFO(inst) ((inst) + 0x00000003), 0x00000300 +#define BF_TDC_PN_FREQ_CTRL_MASK_INFO(inst) ((inst) + 0x00000003), 0x00000303 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_DTLL_CLK_CTRL_ADDR(inst) ((inst) + 0x00000004) +#define BF_DTLL_CLK_SEL_INFO(inst) ((inst) + 0x00000004), 0x00000100 +#define BF_DTLL_EDGE_ALIGN_EN_INFO(inst) ((inst) + 0x00000004), 0x00000101 +#define BF_DTLL_GAPPED_TRUE_PERIOD_DETECT_INFO(inst) ((inst) + 0x00000004), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_DTLL_CIC_DECIMATION_RATE_0_ADDR(inst) ((inst) + 0x00000005) +#define BF_DTLL_CIC_DECIMATION_RATE_INFO(inst) ((inst) + 0x00000005), 0x00001000 +#endif /* USE_PRIVATE_BF */ + +#define REG_DTLL_CIC_DECIMATION_RATE_1_ADDR(inst) ((inst) + 0x00000006) + +#ifdef USE_PRIVATE_BF +#define REG_MCS_RD_FSM_1_ADDR(inst) ((inst) + 0x00000007) +#define BF_MCS_SYSREF_IN_FSM_STATE_INFO(inst) ((inst) + 0x00000007), 0x00000400 +#define BF_MCS_SYSREF_OUT_FSM_STATE_INFO(inst) ((inst) + 0x00000007), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_MCS_RD_FSM_3_ADDR(inst) ((inst) + 0x00000008) +#define BF_MCS_DTLL_EDGE_ALIGN_FSM_STATE_INFO(inst) ((inst) + 0x00000008), 0x00000400 +#define BF_MCS_DTLL_EDGE_ALIGN_DONE_INFO(inst) ((inst) + 0x00000008), 0x00000104 +#define BF_MCS_SYSREF_IN_DONE_INFO(inst) ((inst) + 0x00000008), 0x00000106 +#define BF_MCS_SYSREF_OUT_DONE_INFO(inst) ((inst) + 0x00000008), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_MCS_MEAS_TDC_FAST_PERIOD_0_ADDR(inst) ((inst) + 0x00000009) +#define BF_MCS_MEAS_TDC_FAST_PERIOD_INFO(inst) ((inst) + 0x00000009), 0x00003000 +#endif /* USE_PRIVATE_BF */ + +#define REG_MCS_MEAS_TDC_FAST_PERIOD_1_ADDR(inst) ((inst) + 0x0000000A) + +#define REG_MCS_MEAS_TDC_FAST_PERIOD_2_ADDR(inst) ((inst) + 0x0000000B) + +#define REG_MCS_MEAS_TDC_FAST_PERIOD_3_ADDR(inst) ((inst) + 0x0000000C) + +#define REG_MCS_MEAS_TDC_FAST_PERIOD_4_ADDR(inst) ((inst) + 0x0000000D) + +#define REG_MCS_MEAS_TDC_FAST_PERIOD_5_ADDR(inst) ((inst) + 0x0000000E) + +#ifdef USE_PRIVATE_BF +#define REG_MCS_MEAS_TDC_SLOW_PERIOD_0_ADDR(inst) ((inst) + 0x0000000F) +#define BF_MCS_MEAS_TDC_SLOW_PERIOD_INFO(inst) ((inst) + 0x0000000F), 0x00003000 +#endif /* USE_PRIVATE_BF */ + +#define REG_MCS_MEAS_TDC_SLOW_PERIOD_1_ADDR(inst) ((inst) + 0x00000010) + +#define REG_MCS_MEAS_TDC_SLOW_PERIOD_2_ADDR(inst) ((inst) + 0x00000011) + +#define REG_MCS_MEAS_TDC_SLOW_PERIOD_3_ADDR(inst) ((inst) + 0x00000012) + +#define REG_MCS_MEAS_TDC_SLOW_PERIOD_4_ADDR(inst) ((inst) + 0x00000013) + +#define REG_MCS_MEAS_TDC_SLOW_PERIOD_5_ADDR(inst) ((inst) + 0x00000014) + +#ifdef USE_PRIVATE_BF +#define REG_MCS_MEAS_TDC_TIMEDIFF_0_ADDR(inst) ((inst) + 0x00000015) +#define BF_MCS_MEAS_TDC_TIMEDIFF_INFO(inst) ((inst) + 0x00000015), 0x00003000 +#endif /* USE_PRIVATE_BF */ + +#define REG_MCS_MEAS_TDC_TIMEDIFF_1_ADDR(inst) ((inst) + 0x00000016) + +#define REG_MCS_MEAS_TDC_TIMEDIFF_2_ADDR(inst) ((inst) + 0x00000017) + +#define REG_MCS_MEAS_TDC_TIMEDIFF_3_ADDR(inst) ((inst) + 0x00000018) + +#define REG_MCS_MEAS_TDC_TIMEDIFF_4_ADDR(inst) ((inst) + 0x00000019) + +#define REG_MCS_MEAS_TDC_TIMEDIFF_5_ADDR(inst) ((inst) + 0x0000001A) + +#ifdef USE_PRIVATE_BF +#define REG_DTLL_FINE_PH_REMAP_0_ADDR(inst) ((inst) + 0x0000001B) +#define BF_DTLL_FINE_PH_REMAP_INFO(inst) ((inst) + 0x0000001B), 0x00001000 +#endif /* USE_PRIVATE_BF */ + +#define REG_DTLL_FINE_PH_REMAP_1_ADDR(inst) ((inst) + 0x0000001C) + +#define REG_CLK_STABLE_ADDR(inst) ((inst) + 0x0000001D) +#define BF_CLK_STABLE_FLAG_INFO(inst) ((inst) + 0x0000001D), 0x00000100 + +#define REG_SYSREF_SUHD_STATUS_ADDR(inst) ((inst) + 0x00000030) +#define BF_SYSREF_SETUP_STATUS_INFO(inst) ((inst) + 0x00000030), 0x00000400 +#define BF_SYSREF_HOLD_STATUS_INFO(inst) ((inst) + 0x00000030), 0x00000404 + +#define REG_SERDIV_CTRL0_ADDR(inst) ((inst) + 0x00000031) +#define BF_MCS_SERDIV_EN_INFO(inst) ((inst) + 0x00000031), 0x00000100 +#define BF_MCS_SERDIV_MODE_INFO(inst) ((inst) + 0x00000031), 0x00000204 + +#define REG_SERDIV_CTRL1_ADDR(inst) ((inst) + 0x00000032) +#define BF_SER_DIVROT_INFO(inst) ((inst) + 0x00000032), 0x00000100 + +#define REG_CLK_EN_GEN_ADDR(inst) ((inst) + 0x00000033) +#define BF_CLK_REC_EN_INFO(inst) ((inst) + 0x00000033), 0x00000100 +#define BF_MCS_SH_EN_INFO(inst) ((inst) + 0x00000033), 0x00000101 +#define BF_MCS_SYNCSAMPLER_EN_INFO(inst) ((inst) + 0x00000033), 0x00000102 + +#define REG_SYSREF_EN_ALL_ADDR(inst) ((inst) + 0x00000034) +#define BF_SYSREF_EN_INFO(inst) ((inst) + 0x00000034), 0x00000100 +#define BF_SYSREF_LEVEL_INFO(inst) ((inst) + 0x00000034), 0x00000104 + +#define REG_TDC_DIV32_CTRL_ADDR(inst) ((inst) + 0x00000035) +#define BF_TDC_DIV_BYPASS_INFO(inst) ((inst) + 0x00000035), 0x00000100 +#define BF_TDC_DIV_RESETB_INFO(inst) ((inst) + 0x00000035), 0x00000104 + +#define REG_SYSREF_TRIM_OFFSET_ADDR(inst) ((inst) + 0x00000036) +#define BF_SYSREF_OFFSET_INFO(inst) ((inst) + 0x00000036), 0x00000300 +#define BF_SYSREF_TRIM_IBIAS_INFO(inst) ((inst) + 0x00000036), 0x00000204 + +#define REG_SYSREF_CTRL_MISC_ADDR(inst) ((inst) + 0x00000037) +#define BF_SYSREF_GATEOFF_OUTPUT_INFO(inst) ((inst) + 0x00000037), 0x00000100 +#define BF_SYSREF_BYP_BIAS_R_INFO(inst) ((inst) + 0x00000037), 0x00000101 +#define BF_EN_ODRV_TST_INFO(inst) ((inst) + 0x00000037), 0x00000102 + +#define REG_CKMUX_CTRL_ADDR(inst) ((inst) + 0x00000038) +#define BF_EN_CKMUX_INFO(inst) ((inst) + 0x00000038), 0x00000100 +#define BF_EN_CKMUX_XC_INFO(inst) ((inst) + 0x00000038), 0x00000204 + +#define REG_PROG_AMUX_ADDR(inst) ((inst) + 0x00000039) +#define BF_PROG_AMUX_INFO(inst) ((inst) + 0x00000039), 0x00000400 + +#define REG_CLK_PATH_SEL_ADDR(inst) ((inst) + 0x0000003A) +#define BF_CLK_PATH_SEL_INFO(inst) ((inst) + 0x0000003A), 0x00000100 + +#define REG_CKRX_SKEW_TRIM_ADDR(inst) ((inst) + 0x0000003B) +#define BF_CKRX_SKEW_TRIMP_INFO(inst) ((inst) + 0x0000003B), 0x00000400 +#define BF_CKRX_SKEW_TRIMN_INFO(inst) ((inst) + 0x0000003B), 0x00000404 + +#define REG_SH_DETECTOR_ADDR(inst) ((inst) + 0x0000003C) +#define BF_SH_BEFORE_INFO(inst) ((inst) + 0x0000003C), 0x00000200 +#define BF_SH_AFTER_INFO(inst) ((inst) + 0x0000003C), 0x00000204 + +#define REG_SPARE_0_MCS_TDC_ADDR(inst) ((inst) + 0x00000040) +#define BF_SPARE0_INFO(inst) ((inst) + 0x00000040), 0x00000800 + +#define REG_SPARE_1_MCS_TDC_ADDR(inst) ((inst) + 0x00000041) +#define BF_SPARE1_INFO(inst) ((inst) + 0x00000041), 0x00000800 + +#define REG_SPARE_2_MCS_TDC_ADDR(inst) ((inst) + 0x00000042) +#define BF_SPARE2_INFO(inst) ((inst) + 0x00000042), 0x00000800 + +#define REG_SPARE_3_MCS_TDC_ADDR(inst) ((inst) + 0x00000043) +#define BF_SPARE3_INFO(inst) ((inst) + 0x00000043), 0x00000800 + +#define REG_CKRX_SKEW_TRIM_PAD_P_ADDR(inst) ((inst) + 0x00000044) +#define BF_CKRX_SKEW_TRIM_PAD_P_INFO(inst) ((inst) + 0x00000044), 0x00000600 + +#define REG_CKRX_SKEW_TRIM_PAD_N_ADDR(inst) ((inst) + 0x00000045) +#define BF_CKRX_SKEW_TRIM_PAD_N_INFO(inst) ((inst) + 0x00000045), 0x00000600 + +#define REG_CKRX_SKEW_OTRIM_ADDR(inst) ((inst) + 0x00000046) +#define BF_CKRX_SKEW_OTRIMP_INFO(inst) ((inst) + 0x00000046), 0x00000400 +#define BF_CKRX_SKEW_OTRIMN_INFO(inst) ((inst) + 0x00000046), 0x00000404 + +#define REG_MCS_CLK_CTRL_MISC_ADDR(inst) ((inst) + 0x00000047) +#define BF_MCS_CLK_BUFF_EN_INFO(inst) ((inst) + 0x00000047), 0x00000100 +#define BF_MCS_CLK_SERDES_EN_INFO(inst) ((inst) + 0x00000047), 0x00000101 +#define BF_MCS_EN_TDC_DIV4_INFO(inst) ((inst) + 0x00000047), 0x00000104 + +#define REG_ODRV_CTRL_ADDR(inst) ((inst) + 0x00000048) +#define BF_EN_ODRV_PATH_INFO(inst) ((inst) + 0x00000048), 0x00000100 +#define BF_SEL_ODRV_INFO(inst) ((inst) + 0x00000048), 0x00000404 + +#define REG_MCS_LINK_CFG0_ADDR(inst) ((inst) + 0x00000049) +#define BF_MCS_LINK_CONFIG_INFO(inst) ((inst) + 0x00000049), 0x00001000 + +#define REG_LPU_CK_CTRL_ADDR(inst) ((inst) + 0x0000004A) +#define BF_LPU_CK_CHOP_INFO(inst) ((inst) + 0x0000004A), 0x00000100 +#define BF_LPU_CK_BUFBYPASS_INFO(inst) ((inst) + 0x0000004A), 0x00000101 +#define BF_LPU_CK_SEL_INFO(inst) ((inst) + 0x0000004A), 0x00000404 + +#define REG_MCS_LINK_CFG1_ADDR(inst) ((inst) + 0x0000004B) + +#endif /* __ADI_APOLLO_BF_MCS_TDC_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_mem_ctrl.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_mem_ctrl.h new file mode 100644 index 00000000000000..65e302c7c6bf9b --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_mem_ctrl.h @@ -0,0 +1,439 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:18 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_MEM_CTRL_H__ +#define __ADI_APOLLO_BF_MEM_CTRL_H__ + +/*============= D E F I N E S ==============*/ +#define REG_MC_EN_CTRL_ADDR 0x4C002000 +#define BF_MC_CMD_EN_SBPI_INFO 0x4C002000, 0x00000100 +#define BF_MC_CMD_EN_USER_INFO 0x4C002000, 0x00000101 +#define BF_MC_LOAD_QSR_QRR_INFO 0x4C002000, 0x00000104 +#define BF_MC_SEL_RD_MODE_INFO 0x4C002000, 0x00000105 +#define BF_MC_SOFT_RESET_INFO 0x4C002000, 0x00000107 + +#define REG_MC_IDLE_STATUS_ADDR 0x4C002004 +#define BF_MC_CMD_STATUS_IDLE_INFO 0x4C002004, 0x00000100 + +#define REG_MC_SEL_SD_IP_CTRL_ADDR 0x4C002008 +#define BF_MC_CMD_SEL_SD_IP_OHOT_INFO 0x4C002008, 0x00000400 + +#define REG_MC_SEL_SD_IP_STATUS_ADDR 0x4C00200C +#define BF_MC_SEL_SD_IP_OHOT_INFO 0x4C00200C, 0x00000400 +#define BF_MC_CTRL_SEL_SD_IP_INFO 0x4C00200C, 0x00000107 + +#define REG_MC_OP_REQ_ADDR 0x4C002010 +#define BF_MC_OP_OTP_BOOT_REQ_INFO 0x4C002010, 0x00000100 +#define BF_MC_OP_OTP_QUAL_REQ_INFO 0x4C002010, 0x00000101 +#define BF_MC_OP_ABORT_REQ_INFO 0x4C002010, 0x00000107 + +#define REG_MC_OP_ACK_ADDR 0x4C002014 +#define BF_MC_OP_OTP_BOOT_ACK_INFO 0x4C002014, 0x00000100 +#define BF_MC_OP_OTP_QUAL_ACK_INFO 0x4C002014, 0x00000101 +#define BF_MC_OP_ABORT_ACK_INFO 0x4C002014, 0x00000107 + +#define REG_MC_SHF_REQ_ADDR 0x4C002018 +#define BF_MC_CMD_SHF_PDN_REQ_INFO 0x4C002018, 0x00000100 +#define BF_MC_CMD_SHF_RST_REQ_INFO 0x4C002018, 0x00000104 + +#define REG_MC_SHF_ACK_ADDR 0x4C00201C +#define BF_MC_CMD_SHF_PDN_ACK_INFO 0x4C00201C, 0x00000100 +#define BF_MC_CMD_SHF_PDN_RDY_INFO 0x4C00201C, 0x00000101 +#define BF_MC_CMD_SHF_RST_ACK_INFO 0x4C00201C, 0x00000104 +#define BF_MC_CMD_SHF_PWUP_RDY_INFO 0x4C00201C, 0x00000105 + +#define REG_MC_PMC_REQ_ADDR 0x4C002020 +#define BF_MC_CMD_WR_PMC_RQ_REQ_INFO 0x4C002020, 0x00000100 +#define BF_MC_CMD_RD_PMC_RQ_REQ_INFO 0x4C002020, 0x00000101 +#define BF_MC_CMD_WR_PMC_CQ_REQ_INFO 0x4C002020, 0x00000102 +#define BF_MC_CMD_RD_PMC_CQ_REQ_INFO 0x4C002020, 0x00000103 +#define BF_MC_CMD_WR_PMC_CC_REQ_INFO 0x4C002020, 0x00000104 +#define BF_MC_CMD_RD_PMC_CC_REQ_INFO 0x4C002020, 0x00000105 +#define BF_MC_CMD_PMC_OP_REQ_INFO 0x4C002020, 0x00000107 + +#define REG_MC_PMC_ACK_ADDR 0x4C002024 +#define BF_MC_CMD_WR_PMC_RQ_ACK_INFO 0x4C002024, 0x00000100 +#define BF_MC_CMD_RD_PMC_RQ_ACK_INFO 0x4C002024, 0x00000101 +#define BF_MC_CMD_WR_PMC_CQ_ACK_INFO 0x4C002024, 0x00000102 +#define BF_MC_CMD_RD_PMC_CQ_ACK_INFO 0x4C002024, 0x00000103 +#define BF_MC_CMD_WR_PMC_CC_ACK_INFO 0x4C002024, 0x00000104 +#define BF_MC_CMD_RD_PMC_CC_ACK_INFO 0x4C002024, 0x00000105 +#define BF_MC_CMD_PMC_OP_ACK_INFO 0x4C002024, 0x00000107 + +#define REG_MC_PMC_OP_STATUS_ADDR(n) (0x4C002028 + 4 * (n)) +#define BF_MC_CMD_PMC_OP_STATUS_INFO(n) (0x4C002028 + 4 * (n)), 0x00000800 + +#define REG_MC_DAP_REQ_ADDR 0x4C002038 +#define BF_MC_CMD_WR_DAP_RQ_REQ_INFO 0x4C002038, 0x00000100 +#define BF_MC_CMD_RD_DAP_RQ_REQ_INFO 0x4C002038, 0x00000101 +#define BF_MC_CMD_WR_DAP_CQ_REQ_INFO 0x4C002038, 0x00000102 +#define BF_MC_CMD_RD_DAP_CQ_REQ_INFO 0x4C002038, 0x00000103 +#define BF_MC_CMD_WR_DAP_CC_REQ_INFO 0x4C002038, 0x00000104 +#define BF_MC_CMD_RD_DAP_CC_REQ_INFO 0x4C002038, 0x00000105 +#define BF_MC_CMD_WR_DAP_DATA_REQ_INFO 0x4C002038, 0x00000108 +#define BF_MC_CMD_RD_DAP_DATA_REQ_INFO 0x4C002038, 0x00000109 +#define BF_MC_CMD_WR_DAP_ECC_REQ_INFO 0x4C002038, 0x0000010A +#define BF_MC_CMD_RD_DAP_ECC_REQ_INFO 0x4C002038, 0x0000010B +#define BF_MC_CMD_DAP_RP_REQ_INFO 0x4C002038, 0x0000010F + +#define REG_MC_DAP_ACK_ADDR 0x4C00203C +#define BF_MC_CMD_WR_DAP_RQ_ACK_INFO 0x4C00203C, 0x00000100 +#define BF_MC_CMD_RD_DAP_RQ_ACK_INFO 0x4C00203C, 0x00000101 +#define BF_MC_CMD_WR_DAP_CQ_ACK_INFO 0x4C00203C, 0x00000102 +#define BF_MC_CMD_RD_DAP_CQ_ACK_INFO 0x4C00203C, 0x00000103 +#define BF_MC_CMD_WR_DAP_CC_ACK_INFO 0x4C00203C, 0x00000104 +#define BF_MC_CMD_RD_DAP_CC_ACK_INFO 0x4C00203C, 0x00000105 +#define BF_MC_CMD_WR_DAP_DATA_ACK_INFO 0x4C00203C, 0x00000108 +#define BF_MC_CMD_RD_DAP_DATA_ACK_INFO 0x4C00203C, 0x00000109 +#define BF_MC_CMD_WR_DAP_ECC_ACK_INFO 0x4C00203C, 0x0000010A +#define BF_MC_CMD_RD_DAP_ECC_ACK_INFO 0x4C00203C, 0x0000010B +#define BF_MC_CMD_DAP_RP_ACK_INFO 0x4C00203C, 0x0000010F + +#define REG_MC_REDN_ADDR 0x4C002040 +#define BF_MC_CMD_REDN_INFO 0x4C002040, 0x00000200 + +#define REG_MC_ADDR_ADDR 0x4C002044 +#define BF_MC_CMD_ADDR_INFO 0x4C002044, 0x00002000 + +#define REG_MC_PGM_REQ_ADDR 0x4C002048 +#define BF_MC_CMD_PGM_REQ_INFO 0x4C002048, 0x00000100 +#define BF_MC_CMD_PGM_ECC_GEN_INFO 0x4C002048, 0x00000107 + +#define REG_MC_PGM_ACK_ADDR 0x4C00204C +#define BF_MC_CMD_PGM_ACK_INFO 0x4C00204C, 0x00000100 + +#define REG_MC_PGM_BUSY_STATUS_ADDR 0x4C002050 +#define BF_MC_CMD_PGM_BUSY_INFO 0x4C002050, 0x00000100 +#define BF_MC_CMD_PGM_NUMWDS_INFO 0x4C002050, 0x00000304 + +#define REG_MC_PGM_DAP_ADDR_ADDR 0x4C002054 +#define BF_MC_CMD_PGM_DAP_ADDR_INFO 0x4C002054, 0x00001800 + +#define REG_MC_PGM_DAP_DATA_ADDR 0x4C002058 +#define BF_MC_CMD_PGM_DAP_DATA_INFO 0x4C002058, 0x00002000 + +#define REG_MC_PGM_DAP_ECC_ADDR 0x4C00205C +#define BF_MC_CMD_PGM_DAP_ECC_INFO 0x4C00205C, 0x00000800 + +#define REG_MC_PGM_STATUS_ADDR 0x4C002060 +#define BF_MC_CMD_PGM_STATUS_0_INFO 0x4C002060, 0x00000800 +#define BF_MC_CMD_PGM_STATUS_1_INFO 0x4C002060, 0x00000808 +#define BF_MC_CMD_PGM_STATUS_2_INFO 0x4C002060, 0x00000810 +#define BF_MC_CMD_PGM_STATUS_3_INFO 0x4C002060, 0x00000818 + +#define REG_MC_PGM_DAP_DATA_N_ADDR(n) (0x4C002064 + 12 * (n)) +#define BF_MC_CMD_PGM_DAP_DATA_N_INFO(n) (0x4C002064 + 12 * (n)), 0x00002000 + +#define REG_MC_PGM_DAP_ECC_N_ADDR(n) (0x4C002068 + 12 * (n)) +#define BF_MC_CMD_PGM_DAP_ECC_N_INFO(n) (0x4C002068 + 12 * (n)), 0x00000800 + +#define REG_MC_PGM_STATUS_N_ADDR(n) (0x4C00206C + 12 * (n)) +#define BF_MC_CMD_PGM_STATUS_N_0_INFO(n) (0x4C00206C + 12 * (n)), 0x00000800 +#define BF_MC_CMD_PGM_STATUS_N_1_INFO(n) (0x4C00206C + 12 * (n)), 0x00000808 +#define BF_MC_CMD_PGM_STATUS_N_2_INFO(n) (0x4C00206C + 12 * (n)), 0x00000810 +#define BF_MC_CMD_PGM_STATUS_N_3_INFO(n) (0x4C00206C + 12 * (n)), 0x00000818 + +#define REG_MC_OTP_REQ_ADDR 0x4C002094 +#define BF_MC_CMD_OTP_PDN_REQ_INFO 0x4C002094, 0x00000100 +#define BF_MC_CMD_OTP_PWUP_REQ_INFO 0x4C002094, 0x00000101 + +#define REG_MC_OTP_ACK_ADDR 0x4C002098 +#define BF_MC_CMD_OTP_PDN_ACK_INFO 0x4C002098, 0x00000100 +#define BF_MC_CMD_OTP_PWUP_ACK_INFO 0x4C002098, 0x00000101 +#define BF_MC_CMD_OTP_PDN_RDY_INFO 0x4C002098, 0x00000104 + +#define REG_MC_OTP_RD_REQ_ADDR 0x4C00209C +#define BF_MC_CMD_OTP_RD_REQ_INFO 0x4C00209C, 0x00000100 +#define BF_MC_CMD_OTP_BURST_RD_EN_INFO 0x4C00209C, 0x00000107 +#define BF_MC_OTP_RD_ECC_BYPASS_INFO 0x4C00209C, 0x00000110 +#define BF_MC_OTP_RD_ECC_DISABLE_INFO 0x4C00209C, 0x00000111 +#define BF_MC_OTP_RD_ECC_GEN_INFO 0x4C00209C, 0x00000112 +#define BF_MC_OTP_RD_ECC_TEST_INFO 0x4C00209C, 0x00000113 + +#define REG_MC_OTP_RD_ACK_ADDR 0x4C0020A0 +#define BF_MC_CMD_OTP_RD_ACK_INFO 0x4C0020A0, 0x00000100 + +#define REG_MC_OTP_BURST_RD_COUNT_ADDR 0x4C0020A4 +#define BF_MC_CMD_OTP_BURST_RD_COUNT_INFO 0x4C0020A4, 0x00002000 + +#define REG_MC_OTP_RD_WIDTH_CTRL_ADDR 0x4C0020A8 +#define BF_MC_OTP_RD_PULSE_WIDTH_INFO 0x4C0020A8, 0x00000500 +#define BF_MC_OTP_RD_RECOV_WIDTH_INFO 0x4C0020A8, 0x00000508 + +#define REG_MC_OTP_RD_DATA_VALID_ADDR 0x4C0020AC +#define BF_MC_OTP_RD_DATA_VALID_INFO 0x4C0020AC, 0x00000100 + +#define REG_MC_OTP_RD_DATA_ADDR 0x4C0020B0 +#define BF_MC_OTP_RD_DATA_INFO 0x4C0020B0, 0x00002000 + +#define REG_MC_OTP_RD_ECC_ADDR 0x4C0020B4 +#define BF_MC_OTP_RD_ECC_INFO 0x4C0020B4, 0x00000800 +#define BF_MC_OTP_RD_NO_ERR_FLAG_INFO 0x4C0020B4, 0x00000108 +#define BF_MC_OTP_RD_SEC_FLAG_INFO 0x4C0020B4, 0x00000109 +#define BF_MC_OTP_RD_DED_FLAG_INFO 0x4C0020B4, 0x0000010A + +#define REG_MC_OTP_RD_ADDR_STATUS_ADDR 0x4C0020B8 +#define BF_MC_OTP_RD_ADDR_STATUS_INFO 0x4C0020B8, 0x00001800 +#define BF_MC_OTP_RD_SEL_SD_IP_OHOT_INFO 0x4C0020B8, 0x00000418 + +#define REG_MC_OTP_RD_DATA_VALID_N_ADDR(n) (0x4C0020BC + 16 * (n)) +#define BF_MC_OTP_RD_DATA_VALID_N_INFO(n) (0x4C0020BC + 16 * (n)), 0x00000100 + +#define REG_MC_OTP_RD_DATA_N_ADDR(n) (0x4C0020C0 + 16 * (n)) +#define BF_MC_OTP_RD_DATA_N_INFO(n) (0x4C0020C0 + 16 * (n)), 0x00002000 + +#define REG_MC_OTP_RD_ECC_N_ADDR(n) (0x4C0020C4 + 16 * (n)) +#define BF_MC_OTP_RD_ECC_N_INFO(n) (0x4C0020C4 + 16 * (n)), 0x00000800 +#define BF_MC_OTP_RD_NO_ERR_FLAG_N_INFO(n) (0x4C0020C4 + 16 * (n)), 0x00000108 +#define BF_MC_OTP_RD_SEC_FLAG_N_INFO(n) (0x4C0020C4 + 16 * (n)), 0x00000109 +#define BF_MC_OTP_RD_DED_FLAG_N_INFO(n) (0x4C0020C4 + 16 * (n)), 0x0000010A + +#define REG_MC_OTP_RD_ADDR_STATUS_N_ADDR(n) (0x4C0020C8 + 16 * (n)) +#define BF_MC_OTP_RD_ADDR_STATUS_N_INFO(n) (0x4C0020C8 + 16 * (n)), 0x00001800 + +#define REG_MC_ECC_CTRL_ADDR 0x4C0020FC +#define BF_MC_ECC_DISABLE_INFO 0x4C0020FC, 0x00000100 +#define BF_MC_ECC_GEN_INFO 0x4C0020FC, 0x00000101 +#define BF_MC_ECC_TEST_INFO 0x4C0020FC, 0x00000102 + +#define REG_MC_ECC_FLAGS_ADDR 0x4C002100 +#define BF_MC_ECC_NO_ERR_FLAG_INFO 0x4C002100, 0x00000100 +#define BF_MC_ECC_SEC_FLAG_INFO 0x4C002100, 0x00000101 +#define BF_MC_ECC_DED_FLAG_INFO 0x4C002100, 0x00000102 + +#define REG_MC_ECC_INPUT_DATA_ADDR 0x4C002104 +#define BF_MC_ECC_REGMAP_DATA_INFO 0x4C002104, 0x00002000 + +#define REG_MC_ECC_INPUT_ECC_ADDR 0x4C002108 +#define BF_MC_ECC_REGMAP_ECC_INFO 0x4C002108, 0x00000800 + +#define REG_MC_ECC_OUTPUT_DATA_ADDR 0x4C00210C +#define BF_MC_ECC_CORRECTED_DATA_INFO 0x4C00210C, 0x00002000 + +#define REG_MC_ECC_OUTPUT_ECC_ADDR 0x4C002110 +#define BF_MC_ECC_CORRECTED_ECC_INFO 0x4C002110, 0x00000800 + +#define REG_MC_CRC_CTRL_ADDR 0x4C002114 +#define BF_MC_CRC_ENABLE_INFO 0x4C002114, 0x00000100 +#define BF_MC_CRC_RESTART_INFO 0x4C002114, 0x00000101 +#define BF_MC_CRC_ERR_COND_SEL_INFO 0x4C002114, 0x00000102 + +#define REG_MC_CRC_NUM_READS_ADDR 0x4C002118 +#define BF_MC_CRC_NUM_READS_INFO 0x4C002118, 0x00002000 + +#define REG_MC_CRC_CHECKSUM_ADDR 0x4C00211C +#define BF_MC_CRC_CHECKSUM_INFO 0x4C00211C, 0x00002000 + +#define REG_MC_CRC_FLAGS_ADDR 0x4C002120 +#define BF_MC_CRC_NO_ERR_FLAG_INFO 0x4C002120, 0x00000100 +#define BF_MC_CRC_SEC_FLAG_INFO 0x4C002120, 0x00000101 +#define BF_MC_CRC_DED_FLAG_INFO 0x4C002120, 0x00000102 + +#define REG_MC_CRC_ERR_ADDR_ADDR 0x4C002124 +#define BF_MC_CRC_ERR_ADDR_INFO 0x4C002124, 0x00001800 +#define BF_MC_CRC_ERR_SEL_SD_IP_OHOT_INFO 0x4C002124, 0x00000418 + +#define REG_MC_SBPI_PMC_CQ_ADDR 0x4C002130 +#define BF_MC_SBPI_PMC_CQ_REGS_0_INFO 0x4C002130, 0x00000800 +#define BF_MC_SBPI_PMC_CQ_REGS_1_INFO 0x4C002130, 0x00000808 + +#define REG_MC_SBPI_PMC_RQ0_ADDR 0x4C002134 +#define BF_MC_SBPI_PMC_RQ_REGS_0_INFO 0x4C002134, 0x00000800 +#define BF_MC_SBPI_PMC_RQ_REGS_1_INFO 0x4C002134, 0x00000808 +#define BF_MC_SBPI_PMC_RQ_REGS_2_INFO 0x4C002134, 0x00000810 +#define BF_MC_SBPI_PMC_RQ_REGS_3_INFO 0x4C002134, 0x00000818 + +#define REG_MC_SBPI_PMC_RQ1_ADDR 0x4C002138 +#define BF_MC_SBPI_PMC_RQ_REGS_4_INFO 0x4C002138, 0x00000800 +#define BF_MC_SBPI_PMC_RQ_REGS_5_INFO 0x4C002138, 0x00000808 +#define BF_MC_SBPI_PMC_RQ_REGS_6_INFO 0x4C002138, 0x00000810 +#define BF_MC_SBPI_PMC_RQ_REGS_7_INFO 0x4C002138, 0x00000818 + +#define REG_MC_SBPI_PMC_RQ2_ADDR 0x4C00213C +#define BF_MC_SBPI_PMC_RQ_REGS_8_INFO 0x4C00213C, 0x00000800 +#define BF_MC_SBPI_PMC_RQ_REGS_9_INFO 0x4C00213C, 0x00000808 +#define BF_MC_SBPI_PMC_RQ_REGS_10_INFO 0x4C00213C, 0x00000810 +#define BF_MC_SBPI_PMC_RQ_REGS_11_INFO 0x4C00213C, 0x00000818 + +#define REG_MC_SBPI_PMC_CC_ADDR 0x4C002140 +#define BF_MC_SBPI_PMC_CC_REGS_0_INFO 0x4C002140, 0x00000800 + +#define REG_MC_SBPI_DAP_CQ_ADDR 0x4C002144 +#define BF_MC_SBPI_DAP_CQ_REGS_0_INFO 0x4C002144, 0x00000800 +#define BF_MC_SBPI_DAP_CQ_REGS_1_INFO 0x4C002144, 0x00000808 + +#define REG_MC_SBPI_DAP_RQ0_ADDR 0x4C002148 +#define BF_MC_SBPI_DAP_RQ_REGS_0_INFO 0x4C002148, 0x00000800 +#define BF_MC_SBPI_DAP_RQ_REGS_1_INFO 0x4C002148, 0x00000808 +#define BF_MC_SBPI_DAP_RQ_REGS_2_INFO 0x4C002148, 0x00000810 +#define BF_MC_SBPI_DAP_RQ_REGS_3_INFO 0x4C002148, 0x00000818 + +#define REG_MC_SBPI_DAP_RQ1_ADDR 0x4C00214C +#define BF_MC_SBPI_DAP_RQ_REGS_4_INFO 0x4C00214C, 0x00000800 +#define BF_MC_SBPI_DAP_RQ_REGS_5_INFO 0x4C00214C, 0x00000808 +#define BF_MC_SBPI_DAP_RQ_REGS_6_INFO 0x4C00214C, 0x00000810 +#define BF_MC_SBPI_DAP_RQ_REGS_7_INFO 0x4C00214C, 0x00000818 + +#define REG_MC_SBPI_DAP_RQ2_ADDR 0x4C002150 +#define BF_MC_SBPI_DAP_RQ_REGS_8_INFO 0x4C002150, 0x00000800 +#define BF_MC_SBPI_DAP_RQ_REGS_9_INFO 0x4C002150, 0x00000808 +#define BF_MC_SBPI_DAP_RQ_REGS_10_INFO 0x4C002150, 0x00000810 +#define BF_MC_SBPI_DAP_RQ_REGS_11_INFO 0x4C002150, 0x00000818 + +#define REG_MC_SBPI_DAP_CC_ADDR 0x4C002154 +#define BF_MC_SBPI_DAP_CC_REGS_0_INFO 0x4C002154, 0x00000800 + +#define REG_MC_SBPI_DAP_DATA_ADDR 0x4C002158 +#define BF_MC_SBPI_DAP_DATA_REGS_0_INFO 0x4C002158, 0x00000800 +#define BF_MC_SBPI_DAP_DATA_REGS_1_INFO 0x4C002158, 0x00000808 +#define BF_MC_SBPI_DAP_DATA_REGS_2_INFO 0x4C002158, 0x00000810 +#define BF_MC_SBPI_DAP_DATA_REGS_3_INFO 0x4C002158, 0x00000818 + +#define REG_MC_SBPI_DAP_ECC_ADDR 0x4C00215C +#define BF_MC_SBPI_DAP_ECC_REGS_0_INFO 0x4C00215C, 0x00000800 + +#define REG_MC_SBPI_DAP_DATA_N_ADDR(n) (0x4C002160 + 8 * (n)) +#define BF_MC_SBPI_DAP_DATA_REGS_N_0_INFO(n) (0x4C002160 + 8 * (n)), 0x00000800 +#define BF_MC_SBPI_DAP_DATA_REGS_N_1_INFO(n) (0x4C002160 + 8 * (n)), 0x00000808 +#define BF_MC_SBPI_DAP_DATA_REGS_N_2_INFO(n) (0x4C002160 + 8 * (n)), 0x00000810 +#define BF_MC_SBPI_DAP_DATA_REGS_N_3_INFO(n) (0x4C002160 + 8 * (n)), 0x00000818 + +#define REG_MC_SBPI_DAP_ECC_N_ADDR(n) (0x4C002164 + 8 * (n)) +#define BF_MC_SBPI_DAP_ECC_REGS_N_0_INFO(n) (0x4C002164 + 8 * (n)), 0x00000800 + +#define REG_MC_SBPI_RD_REGS0_ADDR(n) (0x4C002180 + 16 * (n)) +#define BF_MC_SBPI_RD_REGS_0_INFO(n) (0x4C002180 + 16 * (n)), 0x00000800 +#define BF_MC_SBPI_RD_REGS_1_INFO(n) (0x4C002180 + 16 * (n)), 0x00000808 +#define BF_MC_SBPI_RD_REGS_2_INFO(n) (0x4C002180 + 16 * (n)), 0x00000810 +#define BF_MC_SBPI_RD_REGS_3_INFO(n) (0x4C002180 + 16 * (n)), 0x00000818 + +#define REG_MC_SBPI_RD_REGS1_ADDR(n) (0x4C002184 + 16 * (n)) +#define BF_MC_SBPI_RD_REGS_4_INFO(n) (0x4C002184 + 16 * (n)), 0x00000800 +#define BF_MC_SBPI_RD_REGS_5_INFO(n) (0x4C002184 + 16 * (n)), 0x00000808 +#define BF_MC_SBPI_RD_REGS_6_INFO(n) (0x4C002184 + 16 * (n)), 0x00000810 +#define BF_MC_SBPI_RD_REGS_7_INFO(n) (0x4C002184 + 16 * (n)), 0x00000818 + +#define REG_MC_SBPI_RD_REGS2_ADDR(n) (0x4C002188 + 16 * (n)) +#define BF_MC_SBPI_RD_REGS_8_INFO(n) (0x4C002188 + 16 * (n)), 0x00000800 +#define BF_MC_SBPI_RD_REGS_9_INFO(n) (0x4C002188 + 16 * (n)), 0x00000808 +#define BF_MC_SBPI_RD_REGS_10_INFO(n) (0x4C002188 + 16 * (n)), 0x00000810 +#define BF_MC_SBPI_RD_REGS_11_INFO(n) (0x4C002188 + 16 * (n)), 0x00000818 + +#define REG_MC_SBPI_RD_REGS3_ADDR(n) (0x4C00218C + 16 * (n)) +#define BF_MC_SBPI_RD_REGS_12_INFO(n) (0x4C00218C + 16 * (n)), 0x00000800 +#define BF_MC_SBPI_RD_REGS_13_INFO(n) (0x4C00218C + 16 * (n)), 0x00000808 +#define BF_MC_SBPI_RD_REGS_14_INFO(n) (0x4C00218C + 16 * (n)), 0x00000810 +#define BF_MC_SBPI_RD_REGS_15_INFO(n) (0x4C00218C + 16 * (n)), 0x00000818 + +#define REG_SD_SHF_CTRL_ADDR 0x4C002200 +#define BF_SD_SHF_OVERRIDE_INFO 0x4C002200, 0x00000100 +#define BF_SD_SHF_SEL_SD_IP_OHOT_INFO 0x4C002200, 0x00000408 + +#define REG_SD_SHF_SBPI_CTRL_ADDR 0x4C002204 +#define BF_SD_SHF_SBPI_CKE_INFO 0x4C002204, 0x00000100 +#define BF_SD_SHF_SBPI_CS_INFO 0x4C002204, 0x00000101 +#define BF_SD_SHF_SBPI_SP_INFO 0x4C002204, 0x00000102 +#define BF_SD_SHF_SBPI_CLOCK_PULSE_INFO 0x4C002204, 0x00000104 +#define BF_SD_SHF_SBPI_SOFT_RESET_INFO 0x4C002204, 0x00000107 + +#define REG_SD_SHF_SBPI_MOSI_ADDR 0x4C002208 +#define BF_SD_SHF_SBPI_MOSI_INFO 0x4C002208, 0x00000800 + +#define REG_SD_SHF_SBPI_MISO_ADDR(n) (0x4C00220C + 8 * (n)) +#define BF_SD_SHF_SBPI_MISO_INFO(n) (0x4C00220C + 8 * (n)), 0x00000800 + +#define REG_SD_SHF_SBPI_STATUS_ADDR(n) (0x4C002210 + 8 * (n)) +#define BF_SD_SHF_SBPI_FLAG_INFO(n) (0x4C002210 + 8 * (n)), 0x00000100 + +#define REG_SD_SHF_USER_CTRL_ADDR 0x4C00222C +#define BF_SD_SHF_USER_CK_INFO 0x4C00222C, 0x00000100 +#define BF_SD_SHF_USER_SEL_INFO 0x4C00222C, 0x00000101 +#define BF_SD_SHF_USER_PD_INFO 0x4C00222C, 0x00000102 +#define BF_SD_SHF_USER_DCTRL_INFO 0x4C00222C, 0x00000103 + +#define REG_SD_SHF_USER_ADDR_ADDR 0x4C002230 +#define BF_SD_SHF_USER_ADDR_INFO 0x4C002230, 0x00001800 + +#define REG_MC_BOOT_CTRL_STATUS_ADDR 0x4C002234 +#define BF_MC_BOOT_REDN_INFO 0x4C002234, 0x00000200 +#define BF_MC_BOOT_ECCDIS_INFO 0x4C002234, 0x00000102 +#define BF_MC_FUSED_PGM_LOCK_INFO 0x4C002234, 0x00000106 +#define BF_MC_FUSED_QUAL_EN_INFO 0x4C002234, 0x00000107 + +#define REG_MC_OP_FSM_STATUS_ADDR 0x4C002238 +#define BF_MC_OP_FSM_BUSY_INFO 0x4C002238, 0x00000100 +#define BF_MC_OP_OTP_RD_READY_INFO 0x4C002238, 0x00000101 +#define BF_MC_OP_ABORTED_FLAG_INFO 0x4C002238, 0x00000103 +#define BF_MC_OP_FSM_STATE_INFO 0x4C002238, 0x00000408 +#define BF_MC_OP_FSM_STATUS_INFO 0x4C002238, 0x0000090C + +#define REG_MC_CMD_FSM_STATUS_ADDR 0x4C00223C +#define BF_MC_CMD_STATUS_FSM_STATE_INFO 0x4C00223C, 0x00000800 +#define BF_MC_CMD_PMC_OP_INVALID_INFO 0x4C00223C, 0x00000108 + +#define REG_MC_IF_FSM_STATUS_ADDR(n) (0x4C002240 + 4 * (n)) +#define BF_MC_SBPI_STATUS_FSM_STATE_INFO(n) (0x4C002240 + 4 * (n)), 0x00000400 +#define BF_MC_USER_STATUS_FSM_STATE_INFO(n) (0x4C002240 + 4 * (n)), 0x00000408 + +#define REG_SD_SHF_Q_ADDR(n) (0x4C002260 + 24 * (n)) +#define BF_SD_SHF_Q_INFO(n) (0x4C002260 + 24 * (n)), 0x00002000 + +#define REG_SD_SHF_QP_ADDR(n) (0x4C002264 + 24 * (n)) +#define BF_SD_SHF_QP_INFO(n) (0x4C002264 + 24 * (n)), 0x00000800 + +#define REG_SD_SHF_QSR_ADDR(n) (0x4C002268 + 24 * (n)) +#define BF_SD_SHF_QSR_INFO(n) (0x4C002268 + 24 * (n)), 0x00002000 + +#define REG_SD_SHF_QSRP_ADDR(n) (0x4C00226C + 24 * (n)) +#define BF_SD_SHF_QSRP_INFO(n) (0x4C00226C + 24 * (n)), 0x00000800 + +#define REG_SD_SHF_QRR_ADDR(n) (0x4C002270 + 24 * (n)) +#define BF_SD_SHF_QRR_INFO(n) (0x4C002270 + 24 * (n)), 0x00002000 + +#define REG_SD_SHF_QRRP_ADDR(n) (0x4C002274 + 24 * (n)) +#define BF_SD_SHF_QRRP_INFO(n) (0x4C002274 + 24 * (n)), 0x00000800 + +#define REG_SD_IPS_STATUS_ADDR(n) (0x4C0022C4 + 8 * (n)) +#define BF_SD_IPS_SHUTD_INFO(n) (0x4C0022C4 + 8 * (n)), 0x00000100 +#define BF_SD_IPS_VRREN_INFO(n) (0x4C0022C4 + 8 * (n)), 0x00000101 +#define BF_SD_IPS_VQQEN_INFO(n) (0x4C0022C4 + 8 * (n)), 0x00000102 +#define BF_SD_IPS_VPPEN_INFO(n) (0x4C0022C4 + 8 * (n)), 0x00000103 + +#define REG_SD_IPS_MRR_ADDR(n) (0x4C0022C8 + 8 * (n)) +#define BF_SD_IPS_MRR_INFO(n) (0x4C0022C8 + 8 * (n)), 0x00002000 + +#define REG_SD_NVM_MR_ADDR(n) (0x4C0022E4 + 24 * (n)) +#define BF_SD_NVM_MR_INFO(n) (0x4C0022E4 + 24 * (n)), 0x00002000 + +#define REG_SD_NVM_ADDR_ADDR(n) (0x4C0022E8 + 24 * (n)) +#define BF_SD_NVM_A_INFO(n) (0x4C0022E8 + 24 * (n)), 0x00001800 + +#define REG_SD_NVM_Q_ADDR(n) (0x4C0022EC + 24 * (n)) +#define BF_SD_NVM_Q_INFO(n) (0x4C0022EC + 24 * (n)), 0x00002000 + +#define REG_SD_NVM_QP_ADDR(n) (0x4C0022F0 + 24 * (n)) +#define BF_SD_NVM_QP_INFO(n) (0x4C0022F0 + 24 * (n)), 0x00000800 + +#define REG_SD_NVM_NQ_ADDR(n) (0x4C0022F4 + 24 * (n)) +#define BF_SD_NVM_NQ_INFO(n) (0x4C0022F4 + 24 * (n)), 0x00002000 + +#define REG_SD_NVM_NQP_ADDR(n) (0x4C0022F8 + 24 * (n)) +#define BF_SD_NVM_NQP_INFO(n) (0x4C0022F8 + 24 * (n)), 0x00000800 + +#define REG_MC_REGMAP_CTRL_ADDR 0x4C0023F0 +#define BF_MC_REGMAP_SOFT_RESET_INFO 0x4C0023F0, 0x00000100 +#define BF_MC_REGMAP_REQ_CLR_N_INFO 0x4C0023F0, 0x00000101 + +#endif /* __ADI_APOLLO_BF_MEM_CTRL_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_pll_mem_map.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_pll_mem_map.h new file mode 100644 index 00000000000000..69121b5f6d54ed --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_pll_mem_map.h @@ -0,0 +1,1074 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:18 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_PLL_MEM_MAP_H__ +#define __ADI_APOLLO_BF_PLL_MEM_MAP_H__ + +/*============= D E F I N E S ==============*/ +#define SERDES_PLL 0x4C003000 +#define CKPLL 0x4C001700 + +#ifdef USE_PRIVATE_BF +#define REG_SYNTH_RESETB_ADDR(inst) ((inst) + 0x00000000) +#define BF_VCO_CAL_LOGIC_RESETB_INFO(inst) ((inst) + 0x00000000), 0x00000100 +#define BF_VCO_TC_CAL_RESETB_INFO(inst) ((inst) + 0x00000000), 0x00000101 +#define BF_LO_SYNC_RESETB_INFO(inst) ((inst) + 0x00000000), 0x00000102 +#define BF_MCS_RESETB_INFO(inst) ((inst) + 0x00000000), 0x00000103 +#define BF_LOCK_DETECT_RESETB_INFO(inst) ((inst) + 0x00000000), 0x00000104 +#define BF_SDM_RESETB_INFO(inst) ((inst) + 0x00000000), 0x00000105 +#define BF_AB_COUNTER_RESETB_INFO(inst) ((inst) + 0x00000000), 0x00000106 +#define BF_REF_CLK_DIVIDER_RESETB_INFO(inst) ((inst) + 0x00000000), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_MISC_PD_ADDR(inst) ((inst) + 0x00000001) +#define BF_VCO_LDO_PD_INFO(inst) ((inst) + 0x00000001), 0x00000100 +#define BF_VCOTC_DAC_PD_INFO(inst) ((inst) + 0x00000001), 0x00000101 +#define BF_PRESCALER_PD_INFO(inst) ((inst) + 0x00000001), 0x00000102 +#define BF_PFD_RESETB_INFO(inst) ((inst) + 0x00000001), 0x00000103 +#define BF_REF_CLK_DIVIDER_PD_INFO(inst) ((inst) + 0x00000001), 0x00000104 +#define BF_CP_LEVELDET_PD_INFO(inst) ((inst) + 0x00000001), 0x00000105 +#define BF_SDM_PD_INFO(inst) ((inst) + 0x00000001), 0x00000106 +#define BF_SYNTH_PD_INFO(inst) ((inst) + 0x00000001), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_MISC_PD_KILLS_ADDR(inst) ((inst) + 0x00000002) +#define BF_KILLRDIV_TEMPS_INFO(inst) ((inst) + 0x00000002), 0x00000100 +#define BF_VCOBUF_TO_PS_PD_INFO(inst) ((inst) + 0x00000002), 0x00000101 +#define BF_CP_OPAMP_PD_INFO(inst) ((inst) + 0x00000002), 0x00000102 +#define BF_CLKOUT_BUF_PD_INFO(inst) ((inst) + 0x00000002), 0x00000103 +#define BF_CP_RESETB_INFO(inst) ((inst) + 0x00000002), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_LOGEN_CLKGEN_LOSYNC_PD_ADDR(inst) ((inst) + 0x00000003) +#define BF_CLKGEN_SERDES_OUTBUF_PD_INFO(inst) ((inst) + 0x00000003), 0x00000100 +#define BF_RF_EXTLO_OUT_PD_INFO(inst) ((inst) + 0x00000003), 0x00000101 +#define BF_LOGEN_PD_INFO(inst) ((inst) + 0x00000003), 0x00000104 +#define BF_RF_EXTLO_IN_PD_INFO(inst) ((inst) + 0x00000003), 0x00000105 +#define BF_LO_SYNC_SAMPLER_FLOPS_PD_INFO(inst) ((inst) + 0x00000003), 0x00000106 +#define BF_LO_SYNC_SAMPLER_LO_INPUT_BUF_PD_INFO(inst) ((inst) + 0x00000003), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_DIVIDER_INT_BYTE0_ADDR(inst) ((inst) + 0x00000004) +#define BF_SDM_INT_INFO(inst) ((inst) + 0x00000004), 0x00000B00 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_DIVIDER_INT_BYTE1_ADDR(inst) ((inst) + 0x00000005) +#define BF_READ_EFFECT_FTW_INFO(inst) ((inst) + 0x00000005), 0x00000103 +#define BF_FB_CLOCK_ADV_INFO(inst) ((inst) + 0x00000005), 0x00000204 +#define BF_BYP_LOAD_DELAY_INFO(inst) ((inst) + 0x00000005), 0x00000106 +#define BF_SDM_BYP_INFO(inst) ((inst) + 0x00000005), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_DIVIDER_FRAC_BYTE0_ADDR(inst) ((inst) + 0x00000006) +#define BF_SDM_FRAC_INFO(inst) ((inst) + 0x00000006), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_DIVIDER_FRAC_BYTE1_ADDR(inst) ((inst) + 0x00000007) + +#define REG_DIVIDER_FRAC_BYTE2_ADDR(inst) ((inst) + 0x00000008) + +#define REG_DIVIDER_FRAC_BYTE3_ADDR(inst) ((inst) + 0x00000009) + +#ifdef USE_PRIVATE_BF +#define REG_CHARGE_PUMP_CONFIG0_ADDR(inst) ((inst) + 0x0000000A) +#define BF_CP_I_INFO(inst) ((inst) + 0x0000000A), 0x00000500 +#define BF_VT_FORCE_INFO(inst) ((inst) + 0x0000000A), 0x00000106 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_PFD_CTL0_ADDR(inst) ((inst) + 0x0000000B) +#define BF_PFD_CLOCK_EDGE_INFO(inst) ((inst) + 0x0000000B), 0x00000100 +#define BF_PFD_FORCEUPDN_INFO(inst) ((inst) + 0x0000000B), 0x00000204 +#define BF_PFD_KILLUPDN_INFO(inst) ((inst) + 0x0000000B), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_PFD_CTL1_ADDR(inst) ((inst) + 0x0000000C) +#define BF_PFD_DELAY_INFO(inst) ((inst) + 0x0000000C), 0x00000200 +#define BF_PFD_DISABLE_ASYM_INFO(inst) ((inst) + 0x0000000C), 0x00000102 +#define BF_PFD_SLIPDN_INFO(inst) ((inst) + 0x0000000C), 0x00000104 +#define BF_PFD_SLIPUP_INFO(inst) ((inst) + 0x0000000C), 0x00000105 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CP_CAL_CTL0_ADDR(inst) ((inst) + 0x0000000D) +#define BF_CP_CAL_INIT_INFO(inst) ((inst) + 0x0000000D), 0x00000100 +#define BF_CP_CAL_EN_INFO(inst) ((inst) + 0x0000000D), 0x00000101 +#define BF_CP_TEST_INFO(inst) ((inst) + 0x0000000D), 0x00000202 +#define BF_CP_CAL_CLK_DIVIDE_INFO(inst) ((inst) + 0x0000000D), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CP_CAL_CTL1_ADDR(inst) ((inst) + 0x0000000E) +#define BF_CP_F_CAL_BITS_INFO(inst) ((inst) + 0x0000000E), 0x00000600 +#define BF_CP_F_CAL_INFO(inst) ((inst) + 0x0000000E), 0x00000106 +#define BF_CP_CAL_VALID_INFO(inst) ((inst) + 0x0000000E), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CP_LVL_DET_TC_ADDR(inst) ((inst) + 0x0000000F) +#define BF_CP_VLEVEL_LOW_TC_INFO(inst) ((inst) + 0x0000000F), 0x00000400 +#define BF_CP_VLEVEL_HIGH_TC_INFO(inst) ((inst) + 0x0000000F), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CP_LVL_DET_TC2_ADDR(inst) ((inst) + 0x00000010) +#define BF_CP_VLEVEL_HIGH_FLAG_INFO(inst) ((inst) + 0x00000010), 0x00000400 +#define BF_CP_VLEVEL_LOW_FLAG_INFO(inst) ((inst) + 0x00000010), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CP_LVL_DET_CTL_STAT_ADDR(inst) ((inst) + 0x00000011) +#define BF_CP_AUXADC_HYST_TC_INFO(inst) ((inst) + 0x00000011), 0x00000200 +#define BF_CP_AUXADC_HYST_ON_TC_INFO(inst) ((inst) + 0x00000011), 0x00000102 +#define BF_CP_SEL_ADC_TC_INFO(inst) ((inst) + 0x00000011), 0x00000103 +#define BF_CP_OVERRANGE_LOW_TC_INFO(inst) ((inst) + 0x00000011), 0x00000104 +#define BF_CP_OVERRANGE_HIGH_TC_INFO(inst) ((inst) + 0x00000011), 0x00000105 +#define BF_CP_OVERRANGE_HIGH_FLAG_INFO(inst) ((inst) + 0x00000011), 0x00000106 +#define BF_CP_OVERRANGE_LOW_FLAG_INFO(inst) ((inst) + 0x00000011), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_LF_C2_ADDR(inst) ((inst) + 0x00000012) +#define BF_LF_C2_INFO(inst) ((inst) + 0x00000012), 0x00000600 +#define BF_LF_BYPASS_C2_INFO(inst) ((inst) + 0x00000012), 0x00000106 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_LF_C1_ADDR(inst) ((inst) + 0x00000013) +#define BF_LF_C1_INFO(inst) ((inst) + 0x00000013), 0x00000600 +#define BF_LF_BYPASS_C1_INFO(inst) ((inst) + 0x00000013), 0x00000106 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_LF_R1_ADDR(inst) ((inst) + 0x00000014) +#define BF_LF_R1_INFO(inst) ((inst) + 0x00000014), 0x00000600 +#define BF_LF_BYPASS_R1_INFO(inst) ((inst) + 0x00000014), 0x00000106 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_LF_C3_ADDR(inst) ((inst) + 0x00000015) +#define BF_LF_C3_INFO(inst) ((inst) + 0x00000015), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_LF_R3_ADDR(inst) ((inst) + 0x00000016) +#define BF_LF_R3_INFO(inst) ((inst) + 0x00000016), 0x00000600 +#define BF_LF_BYPASS_R3_INFO(inst) ((inst) + 0x00000016), 0x00000106 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_VCO_ALC_FREQ_CAL_BYTE0_ADDR(inst) ((inst) + 0x00000017) +#define BF_VCO_CAL_INIT_INFO(inst) ((inst) + 0x00000017), 0x00000100 +#define BF_VCO_CAL_BUSY_INFO(inst) ((inst) + 0x00000017), 0x00000101 +#define BF_VCO_COMP_OUT_INFO(inst) ((inst) + 0x00000017), 0x00000102 +#define BF_VCO_FINE_CAL_EN_INFO(inst) ((inst) + 0x00000017), 0x00000103 +#define BF_VCO_CAL_ALC_WAIT_INFO(inst) ((inst) + 0x00000017), 0x00000304 +#define BF_VCO_COARSE_CAL_EN_INFO(inst) ((inst) + 0x00000017), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_VCO_ALC_FREQ_CAL_BYTE1_ADDR(inst) ((inst) + 0x00000018) +#define BF_VCO_CAL_ALC_CLK_DIV_INFO(inst) ((inst) + 0x00000018), 0x00000300 +#define BF_VCO_CAL_ALC_INIT_WAIT_INFO(inst) ((inst) + 0x00000018), 0x00000203 +#define BF_VCO_CAL_INIT_DEL_INFO(inst) ((inst) + 0x00000018), 0x00000305 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_VCO_ALC_FREQ_CAL_BYTE2_ADDR(inst) ((inst) + 0x00000019) +#define BF_VCO_INIT_ALC_VALUE_INFO(inst) ((inst) + 0x00000019), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_F_ALC_BYTE0_ADDR(inst) ((inst) + 0x0000001A) +#define BF_VCO_F_ALC_INFO(inst) ((inst) + 0x0000001A), 0x00000B00 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_F_ALC_BYTE1_ADDR(inst) ((inst) + 0x0000001B) +#define BF_ALC_COMP_CLK_F_VAL_INFO(inst) ((inst) + 0x0000001B), 0x00000104 +#define BF_FORCE_ALC_COMP_CLK_INFO(inst) ((inst) + 0x0000001B), 0x00000105 +#define BF_VCO_ALC_CAL_EN_INFO(inst) ((inst) + 0x0000001B), 0x00000106 +#define BF_VCO_F_ALC_EN_INFO(inst) ((inst) + 0x0000001B), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_VCO_F_COARSE_BAND_BYTE0_ADDR(inst) ((inst) + 0x0000001C) +#define BF_VCO_F_COARSE_BAND_INFO(inst) ((inst) + 0x0000001C), 0x00000900 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_VCO_F_COARSE_BAND_BYTE1_ADDR(inst) ((inst) + 0x0000001D) +#define BF_VCO_F_COARSE_BAND_EN_INFO(inst) ((inst) + 0x0000001D), 0x00000101 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_VCO_F_FINE_BAND_ADDR(inst) ((inst) + 0x0000001E) +#define BF_VCO_F_FINE_BAND_INFO(inst) ((inst) + 0x0000001E), 0x00000600 +#define BF_VCO_F_FINE_BAND_EN_INFO(inst) ((inst) + 0x0000001E), 0x00000106 +#define BF_VCO_F_FINE_BAND_INDEX_EN_INFO(inst) ((inst) + 0x0000001E), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_VCO_TC_BYTE1_ADDR(inst) ((inst) + 0x0000001F) +#define BF_VCO_VAR_TC_INFO(inst) ((inst) + 0x0000001F), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_VCO_TC_BYTE2_ADDR(inst) ((inst) + 0x00000020) +#define BF_VCO_TC_TRACKING_EN_INFO(inst) ((inst) + 0x00000020), 0x00000100 +#define BF_TC_FLAG_STEP_EN_INFO(inst) ((inst) + 0x00000020), 0x00000101 +#define BF_VCO_TC_WAIT_INFO(inst) ((inst) + 0x00000020), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_VCO_TC_BYTE3_ADDR(inst) ((inst) + 0x00000021) +#define BF_TC_OV_STEP_INFO(inst) ((inst) + 0x00000021), 0x00000400 +#define BF_TC_FLAG_STEP_INFO(inst) ((inst) + 0x00000021), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_MCS_CONTROL_ADDR(inst) ((inst) + 0x00000022) +#define BF_MCS_ENABLE_INFO(inst) ((inst) + 0x00000022), 0x00000100 +#define BF_MCS_CLKGEN_SYNC_ENABLE_INFO(inst) ((inst) + 0x00000022), 0x00000101 +#define BF_MCS_SDM_SYNC_ENABLE_INFO(inst) ((inst) + 0x00000022), 0x00000102 +#define BF_MCS_DEVICE_CLK_DIVIDER_SYNC_ENABLE_INFO(inst) ((inst) + 0x00000022), 0x00000103 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_MCS_CONTROL_2_ADDR(inst) ((inst) + 0x00000023) +#define BF_MCS_PULSE_DELAY_INFO(inst) ((inst) + 0x00000023), 0x00000300 +#define BF_MCS_WAIT_COUNT_INFO(inst) ((inst) + 0x00000023), 0x00000203 +#define BF_RETIME_SEL_PSYNCDIV_INFO(inst) ((inst) + 0x00000023), 0x00000105 +#define BF_SEL_PSYNCDIV_FE_INFO(inst) ((inst) + 0x00000023), 0x00000106 +#define BF_INV_SYSREF_INFO(inst) ((inst) + 0x00000023), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_MCS_CONTROL_3_ADDR(inst) ((inst) + 0x00000024) +#define BF_INTERNAL_SYSREF_EN_INFO(inst) ((inst) + 0x00000024), 0x00000100 +#define BF_GCNT_SYSREF_EN_INFO(inst) ((inst) + 0x00000024), 0x00000101 +#define BF_REFCLK_MCSRST_ON_RE_INFO(inst) ((inst) + 0x00000024), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_MCS_STATUS_ADDR(inst) ((inst) + 0x00000025) +#define BF_MCS_SPI_STATUS_INFO(inst) ((inst) + 0x00000025), 0x00000300 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_LOCKDET_CONFIG_ADDR(inst) ((inst) + 0x00000026) +#define BF_LOCKDET_MODE_INFO(inst) ((inst) + 0x00000026), 0x00000200 +#define BF_LOCKDET_CNT_INFO(inst) ((inst) + 0x00000026), 0x00000202 +#define BF_FORCE_LOCK_INFO(inst) ((inst) + 0x00000026), 0x00000104 +#define BF_SYN_LOCK_INFO(inst) ((inst) + 0x00000026), 0x00000105 +#define BF_LOCK_WINDOW_SIZE_INFO(inst) ((inst) + 0x00000026), 0x00000106 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_LOCKDET_CONFIG2_ADDR(inst) ((inst) + 0x00000027) +#define BF_FAST_UNLOCK_EN_INFO(inst) ((inst) + 0x00000027), 0x00000100 +#define BF_UNLOCK_TIMEOUT_EN_INFO(inst) ((inst) + 0x00000027), 0x00000101 +#define BF_FAST_UNLOCK_THR_INFO(inst) ((inst) + 0x00000027), 0x00000204 +#define BF_UNLOCK_TIMEOUT_VAL_INFO(inst) ((inst) + 0x00000027), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_PSCTL0_ADDR(inst) ((inst) + 0x00000028) +#define BF_PSEN_INFO(inst) ((inst) + 0x00000028), 0x00000100 +#define BF_CALTYP_INFO(inst) ((inst) + 0x00000028), 0x00000301 +#define BF_CALPER_INFO(inst) ((inst) + 0x00000028), 0x00000304 +#define BF_ABORT_PLL_MEM_MAP_INFO(inst) ((inst) + 0x00000028), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_PSCTL1_ADDR(inst) ((inst) + 0x00000029) +#define BF_CTSTEP_INFO(inst) ((inst) + 0x00000029), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_PSCTL2_ADDR(inst) ((inst) + 0x0000002A) +#define BF_CSTEP_INFO(inst) ((inst) + 0x0000002A), 0x00000C00 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_PSCTL3_ADDR(inst) ((inst) + 0x0000002B) +#define BF_QTHR_INFO(inst) ((inst) + 0x0000002B), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_PSCTL4_ADDR(inst) ((inst) + 0x0000002C) +#define BF_ICALWAIT_INFO(inst) ((inst) + 0x0000002C), 0x00000200 +#define BF_TSZERO_INFO(inst) ((inst) + 0x0000002C), 0x00000103 +#define BF_TSPRSC_INFO(inst) ((inst) + 0x0000002C), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_PSCTL5_ADDR(inst) ((inst) + 0x0000002D) +#define BF_LG_DIV_INFO(inst) ((inst) + 0x0000002D), 0x00000A00 +#endif /* USE_PRIVATE_BF */ + +#define REG_PSCTL6_ADDR(inst) ((inst) + 0x0000002E) + +#ifdef USE_PRIVATE_BF +#define REG_PSCTL7_ADDR(inst) ((inst) + 0x0000002F) +#define BF_READ_GCNT_INFO(inst) ((inst) + 0x0000002F), 0x00000100 +#define BF_FDOVDM_INFO(inst) ((inst) + 0x0000002F), 0x00000104 +#define BF_INV_LO_I_INFO(inst) ((inst) + 0x0000002F), 0x00000106 +#define BF_INV_LO_Q_INFO(inst) ((inst) + 0x0000002F), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_PSSTAT_ADDR(inst) ((inst) + 0x00000030) +#define BF_PSBUSY_INFO(inst) ((inst) + 0x00000030), 0x00000100 +#define BF_MPEND_INFO(inst) ((inst) + 0x00000030), 0x00000101 +#define BF_CPEND_INFO(inst) ((inst) + 0x00000030), 0x00000102 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_PHADJ0_ADDR(inst) ((inst) + 0x00000031) +#define BF_PHADJ_INFO(inst) ((inst) + 0x00000031), 0x00001700 +#endif /* USE_PRIVATE_BF */ + +#define REG_PHADJ1_ADDR(inst) ((inst) + 0x00000032) + +#define REG_PHADJ2_ADDR(inst) ((inst) + 0x00000033) + +#ifdef USE_PRIVATE_BF +#define REG_FDOVD0_ADDR(inst) ((inst) + 0x00000034) +#define BF_FDOVD_INFO(inst) ((inst) + 0x00000034), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_FDOVD1_ADDR(inst) ((inst) + 0x00000035) + +#define REG_FDOVD2_ADDR(inst) ((inst) + 0x00000036) + +#define REG_FDOVD3_ADDR(inst) ((inst) + 0x00000037) + +#ifdef USE_PRIVATE_BF +#define REG_WPA0_ADDR(inst) ((inst) + 0x00000038) +#define BF_WPA_INFO(inst) ((inst) + 0x00000038), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_WPA1_ADDR(inst) ((inst) + 0x00000039) + +#define REG_WPA2_ADDR(inst) ((inst) + 0x0000003A) + +#define REG_WPA3_ADDR(inst) ((inst) + 0x0000003B) + +#ifdef USE_PRIVATE_BF +#define REG_POAI0_ADDR(inst) ((inst) + 0x0000003C) +#define BF_POAI_INFO(inst) ((inst) + 0x0000003C), 0x00001400 +#endif /* USE_PRIVATE_BF */ + +#define REG_POAI1_ADDR(inst) ((inst) + 0x0000003D) + +#define REG_POAI2_ADDR(inst) ((inst) + 0x0000003E) + +#ifdef USE_PRIVATE_BF +#define REG_POAQ0_ADDR(inst) ((inst) + 0x0000003F) +#define BF_POAQ_INFO(inst) ((inst) + 0x0000003F), 0x00001400 +#endif /* USE_PRIVATE_BF */ + +#define REG_POAQ1_ADDR(inst) ((inst) + 0x00000040) + +#define REG_POAQ2_ADDR(inst) ((inst) + 0x00000041) + +#ifdef USE_PRIVATE_BF +#define REG_PHDIFF0_ADDR(inst) ((inst) + 0x00000042) +#define BF_PHDIFF_INFO(inst) ((inst) + 0x00000042), 0x00001700 +#endif /* USE_PRIVATE_BF */ + +#define REG_PHDIFF1_ADDR(inst) ((inst) + 0x00000043) + +#define REG_PHDIFF2_ADDR(inst) ((inst) + 0x00000044) + +#ifdef USE_PRIVATE_BF +#define REG_GCNT0_ADDR(inst) ((inst) + 0x00000045) +#define BF_GCNT_INFO(inst) ((inst) + 0x00000045), 0x00004000 +#endif /* USE_PRIVATE_BF */ + +#define REG_GCNT1_ADDR(inst) ((inst) + 0x00000046) + +#define REG_GCNT2_ADDR(inst) ((inst) + 0x00000047) + +#define REG_GCNT3_ADDR(inst) ((inst) + 0x00000048) + +#define REG_GCNT4_ADDR(inst) ((inst) + 0x00000049) + +#define REG_GCNT5_ADDR(inst) ((inst) + 0x0000004A) + +#define REG_GCNT6_ADDR(inst) ((inst) + 0x0000004B) + +#define REG_GCNT7_ADDR(inst) ((inst) + 0x0000004C) + +#ifdef USE_PRIVATE_BF +#define REG_GCNT_SYSREF0_ADDR(inst) ((inst) + 0x0000004D) +#define BF_GCNT_SYSREF_INFO(inst) ((inst) + 0x0000004D), 0x00004000 +#endif /* USE_PRIVATE_BF */ + +#define REG_GCNT_SYSREF1_ADDR(inst) ((inst) + 0x0000004E) + +#define REG_GCNT_SYSREF2_ADDR(inst) ((inst) + 0x0000004F) + +#define REG_GCNT_SYSREF3_ADDR(inst) ((inst) + 0x00000050) + +#define REG_GCNT_SYSREF4_ADDR(inst) ((inst) + 0x00000051) + +#define REG_GCNT_SYSREF5_ADDR(inst) ((inst) + 0x00000052) + +#define REG_GCNT_SYSREF6_ADDR(inst) ((inst) + 0x00000053) + +#define REG_GCNT_SYSREF7_ADDR(inst) ((inst) + 0x00000054) + +#ifdef USE_PRIVATE_BF +#define REG_MOD0_0_ADDR(inst) ((inst) + 0x00000055) +#define BF_MOD0_INFO(inst) ((inst) + 0x00000055), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_MOD0_1_ADDR(inst) ((inst) + 0x00000056) + +#define REG_MOD0_2_ADDR(inst) ((inst) + 0x00000057) + +#define REG_MOD0_3_ADDR(inst) ((inst) + 0x00000058) + +#ifdef USE_PRIVATE_BF +#define REG_MOD1_0_ADDR(inst) ((inst) + 0x00000059) +#define BF_MOD1_INFO(inst) ((inst) + 0x00000059), 0x00001700 +#endif /* USE_PRIVATE_BF */ + +#define REG_MOD1_1_ADDR(inst) ((inst) + 0x0000005A) + +#define REG_MOD1_2_ADDR(inst) ((inst) + 0x0000005B) + +#ifdef USE_PRIVATE_BF +#define REG_MOD2_0_ADDR(inst) ((inst) + 0x0000005C) +#define BF_MOD2_INFO(inst) ((inst) + 0x0000005C), 0x00001700 +#endif /* USE_PRIVATE_BF */ + +#define REG_MOD2_1_ADDR(inst) ((inst) + 0x0000005D) + +#define REG_MOD2_2_ADDR(inst) ((inst) + 0x0000005E) + +#ifdef USE_PRIVATE_BF +#define REG_DTAPS0_ADDR(inst) ((inst) + 0x0000005F) +#define BF_DTAPS_B0_INFO(inst) ((inst) + 0x0000005F), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_DTAPS1_ADDR(inst) ((inst) + 0x00000060) +#define BF_DTAPS_B1_INFO(inst) ((inst) + 0x00000060), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_DTAPS2_ADDR(inst) ((inst) + 0x00000061) +#define BF_DTAPS_B2_INFO(inst) ((inst) + 0x00000061), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_DTAPS3_ADDR(inst) ((inst) + 0x00000062) +#define BF_DTAPS_B3_INFO(inst) ((inst) + 0x00000062), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_SDA_ADDR(inst) ((inst) + 0x00000063) +#define BF_SDA_INFO(inst) ((inst) + 0x00000063), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_SDM_DITH_ADDR(inst) ((inst) + 0x00000064) +#define BF_NUM_DITHER_BITS_INFO(inst) ((inst) + 0x00000064), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TCCTL_ADDR(inst) ((inst) + 0x00000065) +#define BF_TCFORCEN_INFO(inst) ((inst) + 0x00000065), 0x00000100 +#define BF_TCUPDINIT_INFO(inst) ((inst) + 0x00000065), 0x00000101 +#define BF_TCPOL_INFO(inst) ((inst) + 0x00000065), 0x00000102 +#define BF_TCFORCE_INFO(inst) ((inst) + 0x00000065), 0x00000103 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TCIDAC_0_ADDR(inst) ((inst) + 0x00000066) +#define BF_TCIDAC_INFO(inst) ((inst) + 0x00000066), 0x00000C00 +#endif /* USE_PRIVATE_BF */ + +#define REG_TCIDAC_1_ADDR(inst) ((inst) + 0x00000067) + +#ifdef USE_PRIVATE_BF +#define REG_LOGEN_CTL0_ADDR(inst) ((inst) + 0x00000068) +#define BF_LODIV_THERMCODE_INFO(inst) ((inst) + 0x00000068), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_LOGEN_CTL1_ADDR(inst) ((inst) + 0x00000069) +#define BF_LOOUTDIV_THERMCODE_INFO(inst) ((inst) + 0x00000069), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_LOGEN_CTL2_ADDR(inst) ((inst) + 0x0000006A) +#define BF_LOOUTDIV_LEAF_THERMCODE_INFO(inst) ((inst) + 0x0000006A), 0x00000200 +#define BF_LOOUTDIV_LEAF_FUND_INFO(inst) ((inst) + 0x0000006A), 0x00000103 +#define BF_XLOIN_BAND_INFO(inst) ((inst) + 0x0000006A), 0x00000304 +#define BF_XLOIN_SPARE_INFO(inst) ((inst) + 0x0000006A), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_LOGEN_CTL3_ADDR(inst) ((inst) + 0x0000006B) +#define BF_LODIV_KILLCLK_INFO(inst) ((inst) + 0x0000006B), 0x00000100 +#define BF_LOOUTDIV_KILLCLK_INFO(inst) ((inst) + 0x0000006B), 0x00000101 +#define BF_LODIV_RB_INFO(inst) ((inst) + 0x0000006B), 0x00000104 +#define BF_LOOUTDIV_RB_INFO(inst) ((inst) + 0x0000006B), 0x00000105 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_LOGEN_CTL4_ADDR(inst) ((inst) + 0x0000006C) +#define BF_XLOIN_FUND_INV_INFO(inst) ((inst) + 0x0000006C), 0x00000100 +#define BF_LODIV_FUND_INFO(inst) ((inst) + 0x0000006C), 0x00000101 +#define BF_LOOUTDIV_FUND_INFO(inst) ((inst) + 0x0000006C), 0x00000102 +#define BF_SEL_VCO_OR_EXTLO_INFO(inst) ((inst) + 0x0000006C), 0x00000104 +#define BF_SEL_TX_LO_INFO(inst) ((inst) + 0x0000006C), 0x00000105 +#define BF_SEL_RX_LO_INFO(inst) ((inst) + 0x0000006C), 0x00000106 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_LOGEN_CTL5_ADDR(inst) ((inst) + 0x0000006D) +#define BF_LO_PHSYNC_LEAF_FUND_INFO(inst) ((inst) + 0x0000006D), 0x00000100 +#define BF_LO_PHSYNC_LEAF_THERMCODE_INFO(inst) ((inst) + 0x0000006D), 0x00000202 +#define BF_LO_PHSYNC_LEAF_KILLCLK_INFO(inst) ((inst) + 0x0000006D), 0x00000104 +#define BF_LO_PHSYNC_LEAF_RB_INFO(inst) ((inst) + 0x0000006D), 0x00000105 +#define BF_LO_PHSYNC_QUAD2_KILLCLK_INFO(inst) ((inst) + 0x0000006D), 0x00000106 +#define BF_LO_PHSYNC_QUAD2_RB_INFO(inst) ((inst) + 0x0000006D), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_LOGEN_CTL6_ADDR(inst) ((inst) + 0x0000006E) +#define BF_LOGEN_SPARES_INFO(inst) ((inst) + 0x0000006E), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CLKGEN_DIGCORE_1_ADDR(inst) ((inst) + 0x0000006F) +#define BF_DIGCORE_DIV1_EN_INFO(inst) ((inst) + 0x0000006F), 0x00000100 +#define BF_DIGCORE_DIV3_EN_INFO(inst) ((inst) + 0x0000006F), 0x00000101 +#define BF_CLKGEN_SYNCCLK_OUTPUT_EN_INFO(inst) ((inst) + 0x0000006F), 0x00000102 +#define BF_DIGCORE_DIV3_KILLCLK_INFO(inst) ((inst) + 0x0000006F), 0x00000104 +#define BF_DIGCORE_SAMPLE_KILLCLK_INFO(inst) ((inst) + 0x0000006F), 0x00000105 +#define BF_DIGCORE_INTERFACE_KILLCLK_INFO(inst) ((inst) + 0x0000006F), 0x00000106 +#define BF_DIGCORE_DIV_RSTB_INFO(inst) ((inst) + 0x0000006F), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CLKGEN_DIGCORE_2_ADDR(inst) ((inst) + 0x00000070) +#define BF_DIGCORE_INTDIV_BINCODE_INFO(inst) ((inst) + 0x00000070), 0x00000400 +#define BF_DIGCORE_CLKDIV_THERMCODE_INFO(inst) ((inst) + 0x00000070), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CLKGEN_DIGCORE_3_ADDR(inst) ((inst) + 0x00000071) +#define BF_CLKGEN_SPARES_INFO(inst) ((inst) + 0x00000071), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CLKGEN_ROOT_DIV_ADDR(inst) ((inst) + 0x00000072) +#define BF_ROOT_CLKDIV_RB_INFO(inst) ((inst) + 0x00000072), 0x00000100 +#define BF_ROOT_CLKDIV_KILLCLK_INFO(inst) ((inst) + 0x00000072), 0x00000103 +#define BF_ROOT_CLKDIV_FUND_INFO(inst) ((inst) + 0x00000072), 0x00000104 +#define BF_ROOT_CLKDIV_DIV2_INFO(inst) ((inst) + 0x00000072), 0x00000105 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TEST_CLKDIV_ADDR(inst) ((inst) + 0x00000073) +#define BF_TEST_CLKDIV_RSTB_INFO(inst) ((inst) + 0x00000073), 0x00000100 +#define BF_TEST_CLKDIV_SAMPLE_KILLCLK_INFO(inst) ((inst) + 0x00000073), 0x00000101 +#define BF_TEST_CLKDIV_DIV1_EN_INFO(inst) ((inst) + 0x00000073), 0x00000102 +#define BF_TEST_CLKDIV_THERMCODE_INFO(inst) ((inst) + 0x00000073), 0x00000204 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REF_CLK_BYTE0_ADDR(inst) ((inst) + 0x00000074) +#define BF_REF_CLK_DIVIDE_RATIO_INFO(inst) ((inst) + 0x00000074), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_MOD_VCO_CAL_CTL_ADDR(inst) ((inst) + 0x00000075) +#define BF_VCOCAL_MAXCNTBAND_EN_INFO(inst) ((inst) + 0x00000075), 0x00000100 +#define BF_ENDVCOCAL_MAXCNT_EN_INFO(inst) ((inst) + 0x00000075), 0x00000101 +#define BF_FREQ_CAL_SINGLE_INFO(inst) ((inst) + 0x00000075), 0x00000102 +#define BF_FCAL_SINGLE_UPD_BANDS_INFO(inst) ((inst) + 0x00000075), 0x00000103 +#define BF_VCOCAL_TIMEDBANDUPD_EN_INFO(inst) ((inst) + 0x00000075), 0x00000104 +#define BF_FREQ_CAL_CNT_RDSEL_INFO(inst) ((inst) + 0x00000075), 0x00000106 +#define BF_FORCE_VCO_INIT_ALC_VALUE_INFO(inst) ((inst) + 0x00000075), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_QUICK_FREQ_CAL_CTL_ADDR(inst) ((inst) + 0x00000076) +#define BF_QUICK_FREQ_CAL_THRESHOLD_INFO(inst) ((inst) + 0x00000076), 0x00000700 +#define BF_QUICK_FREQ_CAL_EN_INFO(inst) ((inst) + 0x00000076), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FREQ_CAL_MAX_CNT0_ADDR(inst) ((inst) + 0x00000077) +#define BF_FREQ_CAL_MAX_CNT_INFO(inst) ((inst) + 0x00000077), 0x00001800 +#endif /* USE_PRIVATE_BF */ + +#define REG_FREQ_CAL_MAX_CNT1_ADDR(inst) ((inst) + 0x00000078) + +#define REG_FREQ_CAL_MAX_CNT2_ADDR(inst) ((inst) + 0x00000079) + +#ifdef USE_PRIVATE_BF +#define REG_FINE_CAP_DNL_OFFSET_ADDR(inst) ((inst) + 0x0000007A) +#define BF_DNL_OFFSET_INFO(inst) ((inst) + 0x0000007A), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FREQ_CALCNT_RDBCK0_ADDR(inst) ((inst) + 0x0000007B) +#define BF_FREQ_CALCNT_RDBCK_INFO(inst) ((inst) + 0x0000007B), 0x00001800 +#endif /* USE_PRIVATE_BF */ + +#define REG_FREQ_CALCNT_RDBCK1_ADDR(inst) ((inst) + 0x0000007C) + +#define REG_FREQ_CALCNT_RDBCK2_ADDR(inst) ((inst) + 0x0000007D) + +#ifdef USE_PRIVATE_BF +#define REG_FINE_CAP_DNL_0_ADDR(inst) ((inst) + 0x0000007E) +#define BF_DNL_0_INFO(inst) ((inst) + 0x0000007E), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FINE_CAP_DNL_1_ADDR(inst) ((inst) + 0x0000007F) +#define BF_DNL_1_INFO(inst) ((inst) + 0x0000007F), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FINE_CAP_DNL_2_ADDR(inst) ((inst) + 0x00000080) +#define BF_DNL_2_INFO(inst) ((inst) + 0x00000080), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FINE_CAP_DNL_3_ADDR(inst) ((inst) + 0x00000081) +#define BF_DNL_3_INFO(inst) ((inst) + 0x00000081), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FINE_CAP_DNL_4_ADDR(inst) ((inst) + 0x00000082) +#define BF_DNL_4_INFO(inst) ((inst) + 0x00000082), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FINE_CAP_DNL_5_ADDR(inst) ((inst) + 0x00000083) +#define BF_DNL_5_INFO(inst) ((inst) + 0x00000083), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FINE_CAP_DNL_6_ADDR(inst) ((inst) + 0x00000084) +#define BF_DNL_6_INFO(inst) ((inst) + 0x00000084), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FINE_CAP_DNL_7_ADDR(inst) ((inst) + 0x00000085) +#define BF_DNL_7_INFO(inst) ((inst) + 0x00000085), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FINE_CAP_DNL_8_ADDR(inst) ((inst) + 0x00000086) +#define BF_DNL_8_INFO(inst) ((inst) + 0x00000086), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CP_CTL0_ADDR(inst) ((inst) + 0x00000087) +#define BF_CP_EN_INFO(inst) ((inst) + 0x00000087), 0x00000100 +#define BF_CP_BLEED_DN_EN_INFO(inst) ((inst) + 0x00000087), 0x00000102 +#define BF_CP_BLEED_UP_EN_INFO(inst) ((inst) + 0x00000087), 0x00000103 +#define BF_CP_BW_INFO(inst) ((inst) + 0x00000087), 0x00000204 +#define BF_CP_GAINBITS_INFO(inst) ((inst) + 0x00000087), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CP_CTL1_ADDR(inst) ((inst) + 0x00000088) +#define BF_CP_IBLEED_INFO(inst) ((inst) + 0x00000088), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CP_CTL2_ADDR(inst) ((inst) + 0x00000089) +#define BF_AUXADC_HYST_ON_FLAG_INFO(inst) ((inst) + 0x00000089), 0x00000100 +#define BF_SEL_ADC_FLAG_INFO(inst) ((inst) + 0x00000089), 0x00000102 +#define BF_CP_FORCE_VDD_OVER_2_INFO(inst) ((inst) + 0x00000089), 0x00000103 +#define BF_AUXADC_HYST_FLAG_INFO(inst) ((inst) + 0x00000089), 0x00000204 +#define BF_CP_BYPASS_FILTER_INFO(inst) ((inst) + 0x00000089), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_MISC_KILL_SIGNALS_ADDR(inst) ((inst) + 0x0000008A) +#define BF_PFD_KILL_UPDNTOLD_INFO(inst) ((inst) + 0x0000008A), 0x00000100 +#define BF_KILLRDIVTODIG_INFO(inst) ((inst) + 0x0000008A), 0x00000102 +#define BF_KILLRDIVTOLD_INFO(inst) ((inst) + 0x0000008A), 0x00000103 +#define BF_KILLNDIVTOLD_INFO(inst) ((inst) + 0x0000008A), 0x00000104 +#define BF_NDIV_PS_KILLCLK_TUNEDIV4_INFO(inst) ((inst) + 0x0000008A), 0x00000105 +#define BF_KILLRDIV_VCOCAL_INFO(inst) ((inst) + 0x0000008A), 0x00000106 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_NEW_LOCK_DETECT0_ADDR(inst) ((inst) + 0x0000008B) +#define BF_LD_RSTB_INFO(inst) ((inst) + 0x0000008B), 0x00000100 +#define BF_LD_EN_INFO(inst) ((inst) + 0x0000008B), 0x00000102 +#define BF_LD_LOL_EN_INFO(inst) ((inst) + 0x0000008B), 0x00000103 +#define BF_LD_BYPASS_DIVBY32_INFO(inst) ((inst) + 0x0000008B), 0x00000104 +#define BF_LD_LOL_LDP_INFO(inst) ((inst) + 0x0000008B), 0x00000305 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_NEW_LOCK_DETECT1_ADDR(inst) ((inst) + 0x0000008C) +#define BF_LD_LOL_HYST_EN_INFO(inst) ((inst) + 0x0000008C), 0x00000100 +#define BF_LD_PD_INFO(inst) ((inst) + 0x0000008C), 0x00000101 +#define BF_LD_LOL_DEAD_CLK_INFO(inst) ((inst) + 0x0000008C), 0x00000102 +#define BF_LD_LOL_HYST_INFO(inst) ((inst) + 0x0000008C), 0x00000103 +#define BF_LD_COUNT_INFO(inst) ((inst) + 0x0000008C), 0x00000204 +#define BF_LD_LOCKED_INFO(inst) ((inst) + 0x0000008C), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_PRESCALER_CTL_ADDR(inst) ((inst) + 0x0000008D) +#define BF_NDIV_PS_EN_TUNEDIV4_INFO(inst) ((inst) + 0x0000008D), 0x00000100 +#define BF_NDIV_PS_RB_INFO(inst) ((inst) + 0x0000008D), 0x00000101 +#define BF_KILL_VCO_TO_NDIV_PS_INFO(inst) ((inst) + 0x0000008D), 0x00000102 +#define BF_NDIV_PS_DLYSEL_INFO(inst) ((inst) + 0x0000008D), 0x00000103 +#define BF_NDIV_PS_SPARES_INFO(inst) ((inst) + 0x0000008D), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_PFD_CHARGEPUMP_SPARES_ADDR(inst) ((inst) + 0x0000008E) +#define BF_PFDCP_SPARES_INFO(inst) ((inst) + 0x0000008E), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_VCO_LDO_0_ADDR(inst) ((inst) + 0x0000008F) +#define BF_LDO_THERM_SDN_THR_INFO(inst) ((inst) + 0x0000008F), 0x00000200 +#define BF_VCO_LDO_ILIM_THR_INFO(inst) ((inst) + 0x0000008F), 0x00000202 +#define BF_LDO_OVERVOLT_THR_INFO(inst) ((inst) + 0x0000008F), 0x00000204 +#define BF_LDO_OVERRIDE_INFO(inst) ((inst) + 0x0000008F), 0x00000106 +#define BF_VCO_LDO_BYPASS_INFO(inst) ((inst) + 0x0000008F), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_VCO_LDO_1_ADDR(inst) ((inst) + 0x00000090) +#define BF_LDO_VOUT_ADJ_INFO(inst) ((inst) + 0x00000090), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_VCO_LDO_2_ADDR(inst) ((inst) + 0x00000091) +#define BF_LDO_VREF_FILT_INFO(inst) ((inst) + 0x00000091), 0x00000200 +#define BF_LDO_COMPENS_ADJ_INFO(inst) ((inst) + 0x00000091), 0x00000202 +#define BF_LDO_LOAD_RES_ADJ_INFO(inst) ((inst) + 0x00000091), 0x00000104 +#define BF_LDO_COMPAR_TEST_INFO(inst) ((inst) + 0x00000091), 0x00000305 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_VCO_LDO_3_ADDR(inst) ((inst) + 0x00000092) +#define BF_LDO_SPARE_INFO(inst) ((inst) + 0x00000092), 0x00000400 +#define BF_LDO_ENVPTAT_INFO(inst) ((inst) + 0x00000092), 0x00000104 +#define BF_LDO_VPTATCTRL_INFO(inst) ((inst) + 0x00000092), 0x00000205 +#define BF_VCO_LDO_OUTPUT_PD_INFO(inst) ((inst) + 0x00000092), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_VCO_LDO_4_ADDR(inst) ((inst) + 0x00000093) +#define BF_LDO_CORE_BIAS_ADJ_INFO(inst) ((inst) + 0x00000093), 0x00000400 +#define BF_LDO_CLEAR_STATUS_INFO(inst) ((inst) + 0x00000093), 0x00000104 +#define BF_LDO_ILOAD_ADJ_INFO(inst) ((inst) + 0x00000093), 0x00000105 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_VCO_LDO_STAT_ADDR(inst) ((inst) + 0x00000094) +#define BF_LDO_OVERVOLT_INFO(inst) ((inst) + 0x00000094), 0x00000100 +#define BF_LDO_CURLIM_INFO(inst) ((inst) + 0x00000094), 0x00000101 +#define BF_LDO_THERMSDN_INFO(inst) ((inst) + 0x00000094), 0x00000102 +#define BF_LDO_POWERGOOD_INFO(inst) ((inst) + 0x00000094), 0x00000103 +#define BF_LDO_NOREF_INFO(inst) ((inst) + 0x00000094), 0x00000104 +#define BF_LDO_UVL_INFO(inst) ((inst) + 0x00000094), 0x00000105 +#define BF_LDO_LOWOUTPUT_INFO(inst) ((inst) + 0x00000094), 0x00000106 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_VCO_CTL0_ADDR(inst) ((inst) + 0x00000095) +#define BF_VCO_SEL_INFO(inst) ((inst) + 0x00000095), 0x00000200 +#define BF_VCOLCR_PD_INFO(inst) ((inst) + 0x00000095), 0x00000102 +#define BF_VCOLCR_BYPASS_BIAS_RES_INFO(inst) ((inst) + 0x00000095), 0x00000103 +#define BF_VCO_VPULL_SEL_INFO(inst) ((inst) + 0x00000095), 0x00000305 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_VCO_CTL1_ADDR(inst) ((inst) + 0x00000096) +#define BF_VCO_VAR_INFO(inst) ((inst) + 0x00000096), 0x00000400 +#define BF_VCOPKDET_CM_SEL_INFO(inst) ((inst) + 0x00000096), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_VCO_CTL2_ADDR(inst) ((inst) + 0x00000097) +#define BF_VCOPKDET_VREF_SEL_INFO(inst) ((inst) + 0x00000097), 0x00000400 +#define BF_VCOPKDET_BYP_RES_DET_INFO(inst) ((inst) + 0x00000097), 0x00000105 +#define BF_VCO_BIAS_TEST_INFO(inst) ((inst) + 0x00000097), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_VCO_CTL3_ADDR(inst) ((inst) + 0x00000098) +#define BF_VCO_LBCORE_CONFIG_INFO(inst) ((inst) + 0x00000098), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_VCO_PD0_ADDR(inst) ((inst) + 0x00000099) +#define BF_VCO_PD_INFO(inst) ((inst) + 0x00000099), 0x00000600 +#define BF_VCO_PD_OVERRIDE_INFO(inst) ((inst) + 0x00000099), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_VCO_PD1_ADDR(inst) ((inst) + 0x0000009A) +#define BF_VCOBUF_PD_INFO(inst) ((inst) + 0x0000009A), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_VCO_PD2_ADDR(inst) ((inst) + 0x0000009B) +#define BF_VCOPKDET_PD_INFO(inst) ((inst) + 0x0000009B), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_VCO_PD3_ADDR(inst) ((inst) + 0x0000009C) +#define BF_VCOPKDET_CMP_PD_INFO(inst) ((inst) + 0x0000009C), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TCIDAC_REG0_ADDR(inst) ((inst) + 0x0000009D) +#define BF_VCOTC_DAC_RST_INFO(inst) ((inst) + 0x0000009D), 0x00000100 +#define BF_VCOTC_I2V_DEGEN_BYP_INFO(inst) ((inst) + 0x0000009D), 0x00000102 +#define BF_VCOTC_I2V_PD_INFO(inst) ((inst) + 0x0000009D), 0x00000103 +#define BF_VCOTC_DAC_SCALE_INFO(inst) ((inst) + 0x0000009D), 0x00000204 +#define BF_VCOTC_I2V_FILT1_BYP_INFO(inst) ((inst) + 0x0000009D), 0x00000106 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TCIDAC_REG1_ADDR(inst) ((inst) + 0x0000009E) +#define BF_VCOTC_I2V_FILT1_INFO(inst) ((inst) + 0x0000009E), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TCIDAC_REG2_ADDR(inst) ((inst) + 0x0000009F) +#define BF_VCOTC_I2V_FILT2_INFO(inst) ((inst) + 0x0000009F), 0x00000300 +#define BF_VCOTC_I2V_FILT2_BYP_INFO(inst) ((inst) + 0x0000009F), 0x00000104 +#define BF_VCOTC_TEST_INFO(inst) ((inst) + 0x0000009F), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TCIDAC_REG3_ADDR(inst) ((inst) + 0x000000A0) +#define BF_VCOTC_I2V_MIR_INFO(inst) ((inst) + 0x000000A0), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TCIDAC_REG4_ADDR(inst) ((inst) + 0x000000A1) +#define BF_VCOTC_I2V_DIODE_INFO(inst) ((inst) + 0x000000A1), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_VCO_CTL_SPARES_0_ADDR(inst) ((inst) + 0x000000A2) +#define BF_VCO_STAT_SPARE_INFO(inst) ((inst) + 0x000000A2), 0x00001000 +#endif /* USE_PRIVATE_BF */ + +#define REG_VCO_CTL_SPARES_1_ADDR(inst) ((inst) + 0x000000A3) + +#ifdef USE_PRIVATE_BF +#define REG_VCO_STAT_SPARES_0_ADDR(inst) ((inst) + 0x000000A4) +#define BF_VCO_CTL_SPARE_INFO(inst) ((inst) + 0x000000A4), 0x00001000 +#endif /* USE_PRIVATE_BF */ + +#define REG_VCO_STAT_SPARES_1_ADDR(inst) ((inst) + 0x000000A5) + +#ifdef USE_PRIVATE_BF +#define REG_BLEED_RAMP_CTL_ADDR(inst) ((inst) + 0x000000A6) +#define BF_BLEED_RAMP_EN_INFO(inst) ((inst) + 0x000000A6), 0x00000100 +#define BF_BLEED_RAMP_INIT_INFO(inst) ((inst) + 0x000000A6), 0x00000101 +#define BF_BLEED_RAMP_DONE_INFO(inst) ((inst) + 0x000000A6), 0x00000104 +#define BF_CP_BLEED_UP_EN_RAMPED_INFO(inst) ((inst) + 0x000000A6), 0x00000106 +#define BF_CP_BLEED_DN_EN_RAMPED_INFO(inst) ((inst) + 0x000000A6), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_BLEED_RAMP_CFG_ADDR(inst) ((inst) + 0x000000A7) +#define BF_BLEED_RAMP_STEP_INFO(inst) ((inst) + 0x000000A7), 0x00000400 +#define BF_BLEED_RAMP_TIME_STEP_INFO(inst) ((inst) + 0x000000A7), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_BLEED_RAMP_STAT_ADDR(inst) ((inst) + 0x000000A8) +#define BF_CP_IBLEED_RAMPED_INFO(inst) ((inst) + 0x000000A8), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_VCO_BAND_DEBUG_COARSE_0_ADDR(inst) ((inst) + 0x000000A9) +#define BF_VCO_BAND2_COARSE_INFO(inst) ((inst) + 0x000000A9), 0x00000900 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_VCO_BAND_DEBUG_COARSE_1_ADDR(inst) ((inst) + 0x000000AA) +#define BF_VCO_BAND_COARSE_SEL_INFO(inst) ((inst) + 0x000000AA), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_VCO_BAND_DEBUG_FINE_ADDR(inst) ((inst) + 0x000000AB) +#define BF_VCO_BAND2_FINE_INFO(inst) ((inst) + 0x000000AB), 0x00000600 +#define BF_VCO_BAND_FINE_SEL_INFO(inst) ((inst) + 0x000000AB), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TESTMUX_ADDR(inst) ((inst) + 0x000000AC) +#define BF_TESTMUX_SEL_INFO(inst) ((inst) + 0x000000AC), 0x00000500 +#define BF_TESTMUX_PD_INFO(inst) ((inst) + 0x000000AC), 0x00000106 +#define BF_TESTMUX_RB_INFO(inst) ((inst) + 0x000000AC), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_SERDES_TEMP_LOOP_CTL_ADDR(inst) ((inst) + 0x000000AD) +#define BF_TC2_CURR_GM_INFO(inst) ((inst) + 0x000000AD), 0x00000300 +#define BF_TC2_GM_PD_INFO(inst) ((inst) + 0x000000AD), 0x00000104 +#define BF_TC2_GM_NORMAL_INFO(inst) ((inst) + 0x000000AD), 0x00000105 +#define BF_TC2_CAL_INFO(inst) ((inst) + 0x000000AD), 0x00000106 +#define BF_TC2_OVERRIDE_INFO(inst) ((inst) + 0x000000AD), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_SERDES_OUTPUT_DIVIDER_CTL_ADDR(inst) ((inst) + 0x000000AE) +#define BF_SERDES_PLL_ODIV_KILLCLK_INFO(inst) ((inst) + 0x000000AE), 0x00000100 +#define BF_SERDES_PLL_ODIV_RB_INFO(inst) ((inst) + 0x000000AE), 0x00000101 +#define BF_SERDES_PLL_ODIV_INFO(inst) ((inst) + 0x000000AE), 0x00000602 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_VCO_SHUNT_LDO_CTL_0_ADDR(inst) ((inst) + 0x000000AF) +#define BF_SLDO1P0_UVP_DET_THR_INFO(inst) ((inst) + 0x000000AF), 0x00000200 +#define BF_SLDO1P0_UVP_COMP_TST_INFO(inst) ((inst) + 0x000000AF), 0x00000102 +#define BF_SLDO1P0_BYP_INFO(inst) ((inst) + 0x000000AF), 0x00000103 +#define BF_SLDO1P0_SPARE_INFO(inst) ((inst) + 0x000000AF), 0x00000304 +#define BF_SLDO1P0_OVP_COMP_TST_INFO(inst) ((inst) + 0x000000AF), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_VCO_SHUNT_LDO_CTL_1_ADDR(inst) ((inst) + 0x000000B0) +#define BF_SLDO1P0_OVP_DIS_INFO(inst) ((inst) + 0x000000B0), 0x00000100 +#define BF_SLDO1P0_COMPENS_ADJ_INFO(inst) ((inst) + 0x000000B0), 0x00000101 +#define BF_SLDO1P0_PD_INFO(inst) ((inst) + 0x000000B0), 0x00000102 +#define BF_SLDO1P0_RAMP_INFO(inst) ((inst) + 0x000000B0), 0x00000103 +#define BF_SLDO1P0_OVP_DET_THR_INFO(inst) ((inst) + 0x000000B0), 0x00000204 +#define BF_SLDO1P0_VOUT_ADJ_INFO(inst) ((inst) + 0x000000B0), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_VCO_SHUNT_LDO_STAT_ADDR(inst) ((inst) + 0x000000B1) +#define BF_SLDO1P0_OVFLAG_INFO(inst) ((inst) + 0x000000B1), 0x00000100 +#define BF_SLDO1P0_UVFLAG_INFO(inst) ((inst) + 0x000000B1), 0x00000101 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_SDM_SHUNT_LDO_CTL0_ADDR(inst) ((inst) + 0x000000B2) +#define BF_SLDO0P8_PD_INFO(inst) ((inst) + 0x000000B2), 0x00000100 +#define BF_SLDO0P8_BYP_INFO(inst) ((inst) + 0x000000B2), 0x00000101 +#define BF_SLDO0P8_VOUT_ADJ_INFO(inst) ((inst) + 0x000000B2), 0x00000202 +#define BF_SLDO0P8_COMPENS_ADJ_INFO(inst) ((inst) + 0x000000B2), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_SDM_SHUNT_LDO_CTL1_ADDR(inst) ((inst) + 0x000000B3) +#define BF_SLDO0P8_SPARE_INFO(inst) ((inst) + 0x000000B3), 0x00000300 +#define BF_PORB_0P8_INFO(inst) ((inst) + 0x000000B3), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#define REG_TEMPS_MAIN_00_PLL_MEM_MAP_ADDR(inst) ((inst) + 0x000000B4) +#define BF_TEMPS_RESET_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000B4), 0x00000100 +#define BF_TEMPS_START_MEASUREMENT_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000B4), 0x00000101 +#define BF_TEMPS_MEASUREMENT_READY_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000B4), 0x00000104 +#define BF_TEMPS_AWAKE_INFO(inst) ((inst) + 0x000000B4), 0x00000107 + +#define REG_TEMPS_MAIN_01_PLL_MEM_MAP_ADDR(inst) ((inst) + 0x000000B5) + +#define REG_TEMPS_MAIN_02_PLL_MEM_MAP_ADDR(inst) ((inst) + 0x000000B6) +#define BF_TEMPS_TEMPERATURE_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000B6), 0x00000C00 + +#define REG_TEMPS_MAIN_03_PLL_MEM_MAP_ADDR(inst) ((inst) + 0x000000B7) +#define BF_TEMPS_OFFSET_ADJ_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000B7), 0x00000700 + +#define REG_TEMPS_MAIN_04_PLL_MEM_MAP_ADDR(inst) ((inst) + 0x000000B8) +#define BF_TEMPS_SLOPE_ADJ_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000B8), 0x00000800 + +#define REG_TEMPS_PD_RESET_PLL_MEM_MAP_ADDR(inst) ((inst) + 0x000000B9) +#define BF_TEMPS_CLK_PD_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000B9), 0x00000100 +#define BF_TEMPS_STARTUP_PD_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000B9), 0x00000101 +#define BF_TEMPS_PTAT_PD_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000B9), 0x00000102 +#define BF_TEMPS_REF_PD_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000B9), 0x00000103 +#define BF_TEMPS_ADC_PD_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000B9), 0x00000104 +#define BF_TEMPS_RESET_ADC_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000B9), 0x00000107 + +#define REG_TEMPS_PD_OVERRIDE_ADDR(inst) ((inst) + 0x000000BA) + +#define REG_TEMPS_PD_OVERRIDE_SELECT_ADDR(inst) ((inst) + 0x000000BB) + +#define REG_TEMPS_BIAS_PTAT_PLL_MEM_MAP_ADDR(inst) ((inst) + 0x000000BC) +#define BF_TEMPS_CURR_PTAT_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000BC), 0x00000600 + +#define REG_TEMPS_BIAS_REF_PLL_MEM_MAP_ADDR(inst) ((inst) + 0x000000BD) +#define BF_TEMPS_CURR_REF_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000BD), 0x00000600 + +#define REG_TEMPS_BIAS_IAMP_PLL_MEM_MAP_ADDR(inst) ((inst) + 0x000000BE) +#define BF_TEMPS_CURR_IAMP1_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000BE), 0x00000400 +#define BF_TEMPS_CURR_IAMP2_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000BE), 0x00000404 + +#define REG_TEMPS_BIAS_VCM_PLL_MEM_MAP_ADDR(inst) ((inst) + 0x000000BF) +#define BF_TEMPS_CURR_VCM_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000BF), 0x00000400 + +#define REG_TEMPS_BIAS_COMP_PLL_MEM_MAP_ADDR(inst) ((inst) + 0x000000C0) +#define BF_TEMPS_CURR_FLASHO_N_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000C0), 0x00000400 +#define BF_TEMPS_CURR_FLASHO_P_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000C0), 0x00000404 + +#define REG_TEMPS_MUX_IN_PLL_MEM_MAP_ADDR(inst) ((inst) + 0x000000C1) +#define BF_TEMPS_SEL_MUX_VP_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000C1), 0x00000300 +#define BF_TEMPS_SEL_MUX_VM_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000C1), 0x00000304 + +#define REG_TEMPS_MUX_BG_CLK_PLL_MEM_MAP_ADDR(inst) ((inst) + 0x000000C2) +#define BF_TEMPS_SEL_MUX_BG_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000C2), 0x00000300 +#define BF_TEMPS_CLK_MUX_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000C2), 0x00000104 + +#define REG_TEMPS_TEST_CTRL_PLL_MEM_MAP_ADDR(inst) ((inst) + 0x000000C3) +#define BF_TEMPS_TEST_MODE_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000C3), 0x00000200 +#define BF_TEMPS_WAIT_TO_MEASURE_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000C3), 0x00000302 +#define BF_TEMPS_WAKE_SETTING_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000C3), 0x00000305 + +#define REG_TEMPS_TEST_STATE_STEP_PLL_MEM_MAP_ADDR(inst) ((inst) + 0x000000C4) +#define BF_TEMPS_TEST_STATE_ADVANCE_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000C4), 0x00000100 +#define BF_TEMPS_TEST_STATE_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000C4), 0x00000101 +#define BF_TEMPS_MEASURE_CONTROL_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000C4), 0x00000204 + +#define REG_TEMPS_MUX_OBS_CTRL_PLL_MEM_MAP_ADDR(inst) ((inst) + 0x000000C5) +#define BF_TEMPS_MUX_OBS_CTRL_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000C5), 0x00000800 + +#define REG_TEMPS_MUX_OBS_PLL_MEM_MAP_ADDR(inst) ((inst) + 0x000000C6) +#define BF_TEMPS_MUX_OBS_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000C6), 0x00000800 + +#define REG_TEMPS_TEST_SPARE_00_PLL_MEM_MAP_ADDR(inst) ((inst) + 0x000000C7) + +#define REG_TEMPS_TEST_SPARE_01_PLL_MEM_MAP_ADDR(inst) ((inst) + 0x000000C8) +#define BF_TEMPS_CTRL_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000C8), 0x00001000 + +#endif /* __ADI_APOLLO_BF_PLL_MEM_MAP_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_raptor_open.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_raptor_open.h new file mode 100644 index 00000000000000..6f3d1c37eda152 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_raptor_open.h @@ -0,0 +1,984 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 1/19/2023 11:54:08 PM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_RAPTOR_OPEN_H__ +#define __ADI_APOLLO_BF_RAPTOR_OPEN_H__ + +/*============= D E F I N E S ==============*/ +#define TX_DAC8_ANALOG0_TX_SLICE_0_TX_DIGITAL0 0x61238000 +#define TX_DAC8_ANALOG1_TX_SLICE_0_TX_DIGITAL0 0x61239000 +#define TX_DAC8_ANALOG0_TX_SLICE_1_TX_DIGITAL0 0x61438000 +#define TX_DAC8_ANALOG1_TX_SLICE_1_TX_DIGITAL0 0x61439000 +#define TX_DAC8_ANALOG0_TX_SLICE_0_TX_DIGITAL1 0x61A38000 +#define TX_DAC8_ANALOG1_TX_SLICE_0_TX_DIGITAL1 0x61A39000 +#define TX_DAC8_ANALOG0_TX_SLICE_1_TX_DIGITAL1 0x61C38000 +#define TX_DAC8_ANALOG1_TX_SLICE_1_TX_DIGITAL1 0x61C39000 + +#define REG_RESET_ADDR(inst) ((inst) + 0x00000000) +#define BF_RESET_INFO(inst) ((inst) + 0x00000000), 0x00000100 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0006_ADDR(inst) ((inst) + 0x00000006) +#define BF_BF_E669B158_INFO(inst) ((inst) + 0x00000006), 0x00000200 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0007_ADDR(inst) ((inst) + 0x00000007) +#define BF_BF_12FBD550_INFO(inst) ((inst) + 0x00000007), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0008_ADDR(inst) ((inst) + 0x00000008) +#define BF_BF_70AC9ED8_INFO(inst) ((inst) + 0x00000008), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0009_ADDR(inst) ((inst) + 0x00000009) +#define BF_BF_DEBBC5DE_INFO(inst) ((inst) + 0x00000009), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0001_ADDR(inst) ((inst) + 0x00000001) +#define BF_BF_8E4B8D89_INFO(inst) ((inst) + 0x00000001), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0002_ADDR(inst) ((inst) + 0x00000002) +#define BF_BF_6C1FE910_INFO(inst) ((inst) + 0x00000002), 0x00000100 +#define BF_BF_3009C337_INFO(inst) ((inst) + 0x00000002), 0x00000101 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0003_ADDR(inst) ((inst) + 0x00000003) +#define BF_BF_F43A30FA_INFO(inst) ((inst) + 0x00000003), 0x00000100 +#define BF_BF_E3BB5782_INFO(inst) ((inst) + 0x00000003), 0x00000101 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0004_ADDR(inst) ((inst) + 0x00000004) +#define BF_BF_54F0F733_INFO(inst) ((inst) + 0x00000004), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0005_ADDR(inst) ((inst) + 0x00000005) +#define BF_BF_37B572D1_INFO(inst) ((inst) + 0x00000005), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0010_ADDR(inst) ((inst) + 0x00000010) +#define BF_BF_A9676458_INFO(inst) ((inst) + 0x00000010), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0011_ADDR(inst) ((inst) + 0x00000011) +#define BF_BF_34D62158_INFO(inst) ((inst) + 0x00000011), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0012_ADDR(inst) ((inst) + 0x00000012) +#define BF_BF_A4844B60_INFO(inst) ((inst) + 0x00000012), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0013_ADDR(inst) ((inst) + 0x00000013) +#define BF_BF_BF19D3C6_INFO(inst) ((inst) + 0x00000013), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0014_ADDR(inst) ((inst) + 0x00000014) +#define BF_BF_9764175F_INFO(inst) ((inst) + 0x00000014), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0015_ADDR(inst) ((inst) + 0x00000015) +#define BF_BF_A67FEBFA_INFO(inst) ((inst) + 0x00000015), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0020_ADDR(inst) ((inst) + 0x00000020) +#define BF_BF_FF66C215_INFO(inst) ((inst) + 0x00000020), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0021_ADDR(inst) ((inst) + 0x00000021) +#define BF_BF_FE8C79E6_INFO(inst) ((inst) + 0x00000021), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0022_ADDR(inst) ((inst) + 0x00000022) +#define BF_BF_9299CD42_INFO(inst) ((inst) + 0x00000022), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0023_ADDR(inst) ((inst) + 0x00000023) +#define BF_BF_EEA1BC08_INFO(inst) ((inst) + 0x00000023), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0024_ADDR(inst) ((inst) + 0x00000024) +#define BF_BF_E47277B0_INFO(inst) ((inst) + 0x00000024), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0025_ADDR(inst) ((inst) + 0x00000025) +#define BF_BF_004A312A_INFO(inst) ((inst) + 0x00000025), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0026_ADDR(inst) ((inst) + 0x00000026) +#define BF_BF_A49E63BD_INFO(inst) ((inst) + 0x00000026), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0027_ADDR(inst) ((inst) + 0x00000027) +#define BF_BF_3E0E832A_INFO(inst) ((inst) + 0x00000027), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0028_ADDR(inst) ((inst) + 0x00000028) +#define BF_BF_FB43FE05_INFO(inst) ((inst) + 0x00000028), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0029_ADDR(inst) ((inst) + 0x00000029) +#define BF_BF_62631345_INFO(inst) ((inst) + 0x00000029), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X002A_ADDR(inst) ((inst) + 0x0000002A) +#define BF_BF_49E3F5B7_INFO(inst) ((inst) + 0x0000002A), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0030_ADDR(inst) ((inst) + 0x00000030) +#define BF_BF_E29D72B0_INFO(inst) ((inst) + 0x00000030), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0031_ADDR(inst) ((inst) + 0x00000031) +#define BF_BF_1CD7C11D_INFO(inst) ((inst) + 0x00000031), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0032_ADDR(inst) ((inst) + 0x00000032) +#define BF_BF_F09B49FE_INFO(inst) ((inst) + 0x00000032), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0033_ADDR(inst) ((inst) + 0x00000033) +#define BF_BF_9DE01DA6_INFO(inst) ((inst) + 0x00000033), 0x00000200 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0034_ADDR(inst) ((inst) + 0x00000034) +#define BF_BF_E28CCBC8_INFO(inst) ((inst) + 0x00000034), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0035_ADDR(inst) ((inst) + 0x00000035) +#define BF_BF_13CA4698_INFO(inst) ((inst) + 0x00000035), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0036_ADDR(inst) ((inst) + 0x00000036) +#define BF_BF_8337FBA4_INFO(inst) ((inst) + 0x00000036), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0037_ADDR(inst) ((inst) + 0x00000037) +#define BF_BF_1218FF47_INFO(inst) ((inst) + 0x00000037), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0038_ADDR(inst) ((inst) + 0x00000038) +#define BF_BF_864D7A88_INFO(inst) ((inst) + 0x00000038), 0x00001800 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0X0039_ADDR(inst) ((inst) + 0x00000039) + +#define REG_REG_0X0X003A_ADDR(inst) ((inst) + 0x0000003A) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X003B_ADDR(inst) ((inst) + 0x0000003B) +#define BF_BF_A166D4E4_INFO(inst) ((inst) + 0x0000003B), 0x00000200 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X003C_ADDR(inst) ((inst) + 0x0000003C) +#define BF_BF_CFF45E5F_INFO(inst) ((inst) + 0x0000003C), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X003D_ADDR(inst) ((inst) + 0x0000003D) +#define BF_BF_14871C83_INFO(inst) ((inst) + 0x0000003D), 0x00000200 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X003E_ADDR(inst) ((inst) + 0x0000003E) +#define BF_BF_B2A308D2_INFO(inst) ((inst) + 0x0000003E), 0x00000900 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0X003F_ADDR(inst) ((inst) + 0x0000003F) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0040_ADDR(inst) ((inst) + 0x00000040) +#define BF_BF_91D580BF_INFO(inst) ((inst) + 0x00000040), 0x00000900 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0X0041_ADDR(inst) ((inst) + 0x00000041) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0042_ADDR(inst) ((inst) + 0x00000042) +#define BF_BF_BD3C6EF3_INFO(inst) ((inst) + 0x00000042), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0043_ADDR(inst) ((inst) + 0x00000043) +#define BF_BF_5041F10E_INFO(inst) ((inst) + 0x00000043), 0x00001000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0X0044_ADDR(inst) ((inst) + 0x00000044) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0045_ADDR(inst) ((inst) + 0x00000045) +#define BF_BF_2355940D_INFO(inst) ((inst) + 0x00000045), 0x00000900 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0X0046_ADDR(inst) ((inst) + 0x00000046) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0047_ADDR(inst) ((inst) + 0x00000047) +#define BF_BF_86486D14_INFO(inst) ((inst) + 0x00000047), 0x00000900 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0X0048_ADDR(inst) ((inst) + 0x00000048) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0049_ADDR(inst) ((inst) + 0x00000049) +#define BF_BF_0773BE32_INFO(inst) ((inst) + 0x00000049), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X004A_ADDR(inst) ((inst) + 0x0000004A) +#define BF_BF_C72109A6_INFO(inst) ((inst) + 0x0000004A), 0x00001000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0X004B_ADDR(inst) ((inst) + 0x0000004B) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0401_ADDR(inst) ((inst) + 0x00000401) +#define BF_BF_92273DEB_INFO(inst) ((inst) + 0x00000401), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0402_ADDR(inst) ((inst) + 0x00000402) +#define BF_BF_53912B4F_INFO(inst) ((inst) + 0x00000402), 0x00000100 +#define BF_BF_E503F98B_INFO(inst) ((inst) + 0x00000402), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0403_ADDR(inst) ((inst) + 0x00000403) +#define BF_BF_E5F48D37_INFO(inst) ((inst) + 0x00000403), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0404_ADDR(inst) ((inst) + 0x00000404) +#define BF_BF_F82D59BA_INFO(inst) ((inst) + 0x00000404), 0x00000100 +#define BF_BF_7D079DC7_INFO(inst) ((inst) + 0x00000404), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0405_ADDR(inst) ((inst) + 0x00000405) +#define BF_BF_170AF5B0_INFO(inst) ((inst) + 0x00000405), 0x00000400 +#define BF_BF_B5BCDFD7_INFO(inst) ((inst) + 0x00000405), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0406_ADDR(inst) ((inst) + 0x00000406) +#define BF_BF_F4B8FCC4_INFO(inst) ((inst) + 0x00000406), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0407_ADDR(inst) ((inst) + 0x00000407) +#define BF_BF_F61A2AB5_INFO(inst) ((inst) + 0x00000407), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0408_ADDR(inst) ((inst) + 0x00000408) +#define BF_BF_1FF30FBF_INFO(inst) ((inst) + 0x00000408), 0x00000300 +#define BF_BF_A2B5B411_INFO(inst) ((inst) + 0x00000408), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0409_ADDR(inst) ((inst) + 0x00000409) +#define BF_BF_0EC59E93_INFO(inst) ((inst) + 0x00000409), 0x00000100 +#define BF_BF_913938EC_INFO(inst) ((inst) + 0x00000409), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X040A_ADDR(inst) ((inst) + 0x0000040A) +#define BF_BF_C9C4D490_INFO(inst) ((inst) + 0x0000040A), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X040B_ADDR(inst) ((inst) + 0x0000040B) +#define BF_BF_AFA76E56_INFO(inst) ((inst) + 0x0000040B), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0410_ADDR(inst) ((inst) + 0x00000410) +#define BF_BF_ED0EEF0E_INFO(inst) ((inst) + 0x00000410), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0411_ADDR(inst) ((inst) + 0x00000411) +#define BF_BF_9731CE7A_INFO(inst) ((inst) + 0x00000411), 0x00000100 +#define BF_BF_CBE62FD3_INFO(inst) ((inst) + 0x00000411), 0x00000101 +#define BF_BF_1143176A_INFO(inst) ((inst) + 0x00000411), 0x00000102 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0412_ADDR(inst) ((inst) + 0x00000412) +#define BF_BF_6AB3151A_INFO(inst) ((inst) + 0x00000412), 0x00000100 +#define BF_BF_A766B2F4_INFO(inst) ((inst) + 0x00000412), 0x00000101 +#define BF_BF_03932366_INFO(inst) ((inst) + 0x00000412), 0x00000102 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0413_ADDR(inst) ((inst) + 0x00000413) +#define BF_BF_66D7BA0A_INFO(inst) ((inst) + 0x00000413), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0414_ADDR(inst) ((inst) + 0x00000414) +#define BF_BF_05D638E6_INFO(inst) ((inst) + 0x00000414), 0x00000200 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0415_ADDR(inst) ((inst) + 0x00000415) +#define BF_BF_27BE3895_INFO(inst) ((inst) + 0x00000415), 0x00000200 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0416_ADDR(inst) ((inst) + 0x00000416) +#define BF_BF_2D922C60_INFO(inst) ((inst) + 0x00000416), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0417_ADDR(inst) ((inst) + 0x00000417) +#define BF_BF_5D0FC6EA_INFO(inst) ((inst) + 0x00000417), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0418_ADDR(inst) ((inst) + 0x00000418) +#define BF_BF_6DAB8DBD_INFO(inst) ((inst) + 0x00000418), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0419_ADDR(inst) ((inst) + 0x00000419) +#define BF_BF_D449DC69_INFO(inst) ((inst) + 0x00000419), 0x00000100 +#define BF_BF_FE62B479_INFO(inst) ((inst) + 0x00000419), 0x00000101 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X041A_ADDR(inst) ((inst) + 0x0000041A) +#define BF_BF_36FAD932_INFO(inst) ((inst) + 0x0000041A), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X041B_ADDR(inst) ((inst) + 0x0000041B) +#define BF_BF_80FDFF24_INFO(inst) ((inst) + 0x0000041B), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X041C_ADDR(inst) ((inst) + 0x0000041C) +#define BF_BF_7DC9BE35_INFO(inst) ((inst) + 0x0000041C), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X041D_ADDR(inst) ((inst) + 0x0000041D) +#define BF_BF_E7AC27B9_INFO(inst) ((inst) + 0x0000041D), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X041E_ADDR(inst) ((inst) + 0x0000041E) +#define BF_BF_4B22B334_INFO(inst) ((inst) + 0x0000041E), 0x00000200 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X041F_ADDR(inst) ((inst) + 0x0000041F) +#define BF_BF_9AE1E07A_INFO(inst) ((inst) + 0x0000041F), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0420_ADDR(inst) ((inst) + 0x00000420) +#define BF_BF_9556CFB9_INFO(inst) ((inst) + 0x00000420), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0421_ADDR(inst) ((inst) + 0x00000421) +#define BF_BF_0B06318A_INFO(inst) ((inst) + 0x00000421), 0x00000200 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0422_ADDR(inst) ((inst) + 0x00000422) +#define BF_BF_8A3CC1CE_INFO(inst) ((inst) + 0x00000422), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0423_ADDR(inst) ((inst) + 0x00000423) +#define BF_BF_0F97527D_INFO(inst) ((inst) + 0x00000423), 0x00000200 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0424_ADDR(inst) ((inst) + 0x00000424) +#define BF_BF_A3EA2614_INFO(inst) ((inst) + 0x00000424), 0x00000200 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0425_ADDR(inst) ((inst) + 0x00000425) +#define BF_BF_8035E27C_INFO(inst) ((inst) + 0x00000425), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0426_ADDR(inst) ((inst) + 0x00000426) +#define BF_BF_8008264B_INFO(inst) ((inst) + 0x00000426), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0427_ADDR(inst) ((inst) + 0x00000427) +#define BF_BF_0DE117D5_INFO(inst) ((inst) + 0x00000427), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0428_ADDR(inst) ((inst) + 0x00000428) +#define BF_BF_618A2DC8_INFO(inst) ((inst) + 0x00000428), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0429_ADDR(inst) ((inst) + 0x00000429) +#define BF_BF_A06D9CCD_INFO(inst) ((inst) + 0x00000429), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X042A_ADDR(inst) ((inst) + 0x0000042A) +#define BF_BF_18A52BE4_INFO(inst) ((inst) + 0x0000042A), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X042B_ADDR(inst) ((inst) + 0x0000042B) +#define BF_BF_C6446F22_INFO(inst) ((inst) + 0x0000042B), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X042C_ADDR(inst) ((inst) + 0x0000042C) +#define BF_BF_6CB70161_INFO(inst) ((inst) + 0x0000042C), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0450_ADDR(inst) ((inst) + 0x00000450) +#define BF_BF_BBD5ECD0_INFO(inst) ((inst) + 0x00000450), 0x00000100 +#define BF_BF_2F404EBF_INFO(inst) ((inst) + 0x00000450), 0x00000101 +#define BF_BF_7ECCDB5B_INFO(inst) ((inst) + 0x00000450), 0x00000102 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0800_ADDR(inst) ((inst) + 0x00000800) +#define BF_BF_6ED4125A_INFO(inst) ((inst) + 0x00000800), 0x00000300 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0801_ADDR(inst) ((inst) + 0x00000801) +#define BF_BF_B1AD16A3_INFO(inst) ((inst) + 0x00000801), 0x00000300 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0802_ADDR(inst) ((inst) + 0x00000802) +#define BF_BF_E7AAA3BF_INFO(inst) ((inst) + 0x00000802), 0x00000300 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0803_ADDR(inst) ((inst) + 0x00000803) +#define BF_BF_2FEF6326_INFO(inst) ((inst) + 0x00000803), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0804_ADDR(inst) ((inst) + 0x00000804) +#define BF_BF_B98C5ECC_INFO(inst) ((inst) + 0x00000804), 0x00000300 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0805_ADDR(inst) ((inst) + 0x00000805) +#define BF_BF_90325EF2_INFO(inst) ((inst) + 0x00000805), 0x00000300 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0806_ADDR(inst) ((inst) + 0x00000806) +#define BF_BF_0FE4E00B_INFO(inst) ((inst) + 0x00000806), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0807_ADDR(inst) ((inst) + 0x00000807) +#define BF_BF_FD01EA7D_INFO(inst) ((inst) + 0x00000807), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#define REG_BIAS_MODE_ADDR(inst) ((inst) + 0x00000808) +#define BF_BIAS_MODE_INFO(inst) ((inst) + 0x00000808), 0x00000100 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0809_ADDR(inst) ((inst) + 0x00000809) +#define BF_BF_E1937169_INFO(inst) ((inst) + 0x00000809), 0x00000100 +#define BF_BF_A7F8EA12_INFO(inst) ((inst) + 0x00000809), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X080A_ADDR(inst) ((inst) + 0x0000080A) +#define BF_BF_2C819551_INFO(inst) ((inst) + 0x0000080A), 0x00000400 +#define BF_BF_CF4506AF_INFO(inst) ((inst) + 0x0000080A), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X080B_ADDR(inst) ((inst) + 0x0000080B) +#define BF_BF_36D31A61_INFO(inst) ((inst) + 0x0000080B), 0x00000100 +#define BF_BF_48C25CC5_INFO(inst) ((inst) + 0x0000080B), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X080C_ADDR(inst) ((inst) + 0x0000080C) +#define BF_BF_C6671F96_INFO(inst) ((inst) + 0x0000080C), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X080D_ADDR(inst) ((inst) + 0x0000080D) +#define BF_BF_D150F5FB_INFO(inst) ((inst) + 0x0000080D), 0x00000100 +#define BF_BF_56B53ABF_INFO(inst) ((inst) + 0x0000080D), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X080E_ADDR(inst) ((inst) + 0x0000080E) +#define BF_BF_D8A97B37_INFO(inst) ((inst) + 0x0000080E), 0x00000400 +#define BF_BF_D70E1980_INFO(inst) ((inst) + 0x0000080E), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X080F_ADDR(inst) ((inst) + 0x0000080F) +#define BF_BF_125A913C_INFO(inst) ((inst) + 0x0000080F), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0810_ADDR(inst) ((inst) + 0x00000810) +#define BF_BF_F5D19006_INFO(inst) ((inst) + 0x00000810), 0x00000100 +#define BF_BF_C95EC6D7_INFO(inst) ((inst) + 0x00000810), 0x00000101 +#define BF_BF_EA68C9A3_INFO(inst) ((inst) + 0x00000810), 0x00000102 +#define BF_BF_7928739B_INFO(inst) ((inst) + 0x00000810), 0x00000103 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0811_ADDR(inst) ((inst) + 0x00000811) +#define BF_BF_61AC19DA_INFO(inst) ((inst) + 0x00000811), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0812_ADDR(inst) ((inst) + 0x00000812) +#define BF_BF_62A4A556_INFO(inst) ((inst) + 0x00000812), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0813_ADDR(inst) ((inst) + 0x00000813) +#define BF_BF_37CE76E1_INFO(inst) ((inst) + 0x00000813), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0814_ADDR(inst) ((inst) + 0x00000814) +#define BF_BF_38404F4D_INFO(inst) ((inst) + 0x00000814), 0x00000400 +#define BF_BF_DA2DCD9F_INFO(inst) ((inst) + 0x00000814), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0815_ADDR(inst) ((inst) + 0x00000815) +#define BF_BF_0E55E9C9_INFO(inst) ((inst) + 0x00000815), 0x00000400 +#define BF_BF_6DA49B8E_INFO(inst) ((inst) + 0x00000815), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0816_ADDR(inst) ((inst) + 0x00000816) +#define BF_BF_57DC81A4_INFO(inst) ((inst) + 0x00000816), 0x00000400 +#define BF_BF_E055177F_INFO(inst) ((inst) + 0x00000816), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0817_ADDR(inst) ((inst) + 0x00000817) +#define BF_BF_870215FD_INFO(inst) ((inst) + 0x00000817), 0x00000400 +#define BF_BF_21FFC997_INFO(inst) ((inst) + 0x00000817), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0818_ADDR(inst) ((inst) + 0x00000818) +#define BF_BF_CB2E7639_INFO(inst) ((inst) + 0x00000818), 0x00000400 +#define BF_BF_425B695E_INFO(inst) ((inst) + 0x00000818), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0819_ADDR(inst) ((inst) + 0x00000819) +#define BF_BF_3807D07C_INFO(inst) ((inst) + 0x00000819), 0x00000400 +#define BF_BF_9AD0FA1E_INFO(inst) ((inst) + 0x00000819), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X081A_ADDR(inst) ((inst) + 0x0000081A) +#define BF_BF_F81B06A8_INFO(inst) ((inst) + 0x0000081A), 0x00000400 +#define BF_BF_35397572_INFO(inst) ((inst) + 0x0000081A), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X081B_ADDR(inst) ((inst) + 0x0000081B) +#define BF_BF_337F98A3_INFO(inst) ((inst) + 0x0000081B), 0x00000400 +#define BF_BF_C50D3018_INFO(inst) ((inst) + 0x0000081B), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X081C_ADDR(inst) ((inst) + 0x0000081C) +#define BF_BF_3EB8AFDA_INFO(inst) ((inst) + 0x0000081C), 0x00000400 +#define BF_BF_9108630F_INFO(inst) ((inst) + 0x0000081C), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0820_ADDR(inst) ((inst) + 0x00000820) +#define BF_BF_1F7436A4_INFO(inst) ((inst) + 0x00000820), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0821_ADDR(inst) ((inst) + 0x00000821) +#define BF_BF_7066C156_INFO(inst) ((inst) + 0x00000821), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0822_ADDR(inst) ((inst) + 0x00000822) +#define BF_BF_B1262357_INFO(inst) ((inst) + 0x00000822), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0823_ADDR(inst) ((inst) + 0x00000823) +#define BF_BF_50873D5A_INFO(inst) ((inst) + 0x00000823), 0x00000300 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0824_ADDR(inst) ((inst) + 0x00000824) +#define BF_BF_11498B75_INFO(inst) ((inst) + 0x00000824), 0x00000300 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0825_ADDR(inst) ((inst) + 0x00000825) +#define BF_BF_EE5FD1DB_INFO(inst) ((inst) + 0x00000825), 0x00000200 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0826_ADDR(inst) ((inst) + 0x00000826) +#define BF_BF_8EA05E7D_INFO(inst) ((inst) + 0x00000826), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0827_ADDR(inst) ((inst) + 0x00000827) +#define BF_BF_349B9412_INFO(inst) ((inst) + 0x00000827), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0828_ADDR(inst) ((inst) + 0x00000828) +#define BF_BF_5398A0B3_INFO(inst) ((inst) + 0x00000828), 0x00000300 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0829_ADDR(inst) ((inst) + 0x00000829) +#define BF_BF_709E6C26_INFO(inst) ((inst) + 0x00000829), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X082A_ADDR(inst) ((inst) + 0x0000082A) +#define BF_BF_6E917302_INFO(inst) ((inst) + 0x0000082A), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X082B_ADDR(inst) ((inst) + 0x0000082B) +#define BF_BF_62F2FF0D_INFO(inst) ((inst) + 0x0000082B), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X082C_ADDR(inst) ((inst) + 0x0000082C) +#define BF_BF_80D632ED_INFO(inst) ((inst) + 0x0000082C), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X082D_ADDR(inst) ((inst) + 0x0000082D) +#define BF_BF_2DC98F97_INFO(inst) ((inst) + 0x0000082D), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X082E_ADDR(inst) ((inst) + 0x0000082E) +#define BF_BF_27A681CF_INFO(inst) ((inst) + 0x0000082E), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X082F_ADDR(inst) ((inst) + 0x0000082F) +#define BF_BF_431EC858_INFO(inst) ((inst) + 0x0000082F), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0830_ADDR(inst) ((inst) + 0x00000830) +#define BF_BF_36E0AE84_INFO(inst) ((inst) + 0x00000830), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0831_ADDR(inst) ((inst) + 0x00000831) +#define BF_BF_D3AF6A04_INFO(inst) ((inst) + 0x00000831), 0x00000200 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0832_ADDR(inst) ((inst) + 0x00000832) +#define BF_BF_9A27FC53_INFO(inst) ((inst) + 0x00000832), 0x00000300 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0833_ADDR(inst) ((inst) + 0x00000833) +#define BF_BF_6AC65B90_INFO(inst) ((inst) + 0x00000833), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0834_ADDR(inst) ((inst) + 0x00000834) +#define BF_BF_822DED62_INFO(inst) ((inst) + 0x00000834), 0x00000300 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0835_ADDR(inst) ((inst) + 0x00000835) +#define BF_BF_417051D7_INFO(inst) ((inst) + 0x00000835), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0836_ADDR(inst) ((inst) + 0x00000836) +#define BF_BF_6FBB6357_INFO(inst) ((inst) + 0x00000836), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0837_ADDR(inst) ((inst) + 0x00000837) +#define BF_BF_80816734_INFO(inst) ((inst) + 0x00000837), 0x00000900 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0X0838_ADDR(inst) ((inst) + 0x00000838) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0839_ADDR(inst) ((inst) + 0x00000839) +#define BF_BF_F0BFE47D_INFO(inst) ((inst) + 0x00000839), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X083A_ADDR(inst) ((inst) + 0x0000083A) +#define BF_BF_548EA9EF_INFO(inst) ((inst) + 0x0000083A), 0x00000900 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0X083B_ADDR(inst) ((inst) + 0x0000083B) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X083C_ADDR(inst) ((inst) + 0x0000083C) +#define BF_BF_F93542A0_INFO(inst) ((inst) + 0x0000083C), 0x00000900 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0X083D_ADDR(inst) ((inst) + 0x0000083D) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X083E_ADDR(inst) ((inst) + 0x0000083E) +#define BF_BF_2CF5B5ED_INFO(inst) ((inst) + 0x0000083E), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X083F_ADDR(inst) ((inst) + 0x0000083F) +#define BF_BF_9F33742D_INFO(inst) ((inst) + 0x0000083F), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0840_ADDR(inst) ((inst) + 0x00000840) +#define BF_BF_1EA21983_INFO(inst) ((inst) + 0x00000840), 0x00000900 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0X0841_ADDR(inst) ((inst) + 0x00000841) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0842_ADDR(inst) ((inst) + 0x00000842) +#define BF_BF_6F85B04C_INFO(inst) ((inst) + 0x00000842), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0843_ADDR(inst) ((inst) + 0x00000843) +#define BF_BF_0AB24C19_INFO(inst) ((inst) + 0x00000843), 0x00000300 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0844_ADDR(inst) ((inst) + 0x00000844) +#define BF_BF_498BCAC3_INFO(inst) ((inst) + 0x00000844), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0845_ADDR(inst) ((inst) + 0x00000845) +#define BF_BF_07FF1574_INFO(inst) ((inst) + 0x00000845), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0846_ADDR(inst) ((inst) + 0x00000846) +#define BF_BF_BAC34A7D_INFO(inst) ((inst) + 0x00000846), 0x00000300 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0847_ADDR(inst) ((inst) + 0x00000847) +#define BF_BF_B825EFCD_INFO(inst) ((inst) + 0x00000847), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0848_ADDR(inst) ((inst) + 0x00000848) +#define BF_BF_C0056CA4_INFO(inst) ((inst) + 0x00000848), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0849_ADDR(inst) ((inst) + 0x00000849) +#define BF_BF_6C096A02_INFO(inst) ((inst) + 0x00000849), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X084A_ADDR(inst) ((inst) + 0x0000084A) +#define BF_BF_E0CBD4FB_INFO(inst) ((inst) + 0x0000084A), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X084B_ADDR(inst) ((inst) + 0x0000084B) +#define BF_BF_57CDC2DA_INFO(inst) ((inst) + 0x0000084B), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X084C_ADDR(inst) ((inst) + 0x0000084C) +#define BF_BF_BDD6BA21_INFO(inst) ((inst) + 0x0000084C), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X084D_ADDR(inst) ((inst) + 0x0000084D) +#define BF_BF_26F117D3_INFO(inst) ((inst) + 0x0000084D), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X084E_ADDR(inst) ((inst) + 0x0000084E) +#define BF_BF_BFB99502_INFO(inst) ((inst) + 0x0000084E), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X084F_ADDR(inst) ((inst) + 0x0000084F) +#define BF_BF_B0891CF7_INFO(inst) ((inst) + 0x0000084F), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0850_ADDR(inst) ((inst) + 0x00000850) +#define BF_BF_96145DD8_INFO(inst) ((inst) + 0x00000850), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0851_ADDR(inst) ((inst) + 0x00000851) +#define BF_BF_080BD1E5_INFO(inst) ((inst) + 0x00000851), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0852_ADDR(inst) ((inst) + 0x00000852) +#define BF_BF_C4ECC4FE_INFO(inst) ((inst) + 0x00000852), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0853_ADDR(inst) ((inst) + 0x00000853) +#define BF_BF_EE9D43DE_INFO(inst) ((inst) + 0x00000853), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0860_ADDR(inst) ((inst) + 0x00000860) +#define BF_BF_4AF75CD3_INFO(inst) ((inst) + 0x00000860), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0861_ADDR(inst) ((inst) + 0x00000861) +#define BF_BF_13E1B658_INFO(inst) ((inst) + 0x00000861), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0862_ADDR(inst) ((inst) + 0x00000862) +#define BF_BF_C9A41BAF_INFO(inst) ((inst) + 0x00000862), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0863_ADDR(inst) ((inst) + 0x00000863) +#define BF_BF_4B4BE0FB_INFO(inst) ((inst) + 0x00000863), 0x00000200 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0864_ADDR(inst) ((inst) + 0x00000864) +#define BF_BF_5DFB7F34_INFO(inst) ((inst) + 0x00000864), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0865_ADDR(inst) ((inst) + 0x00000865) +#define BF_BF_BEF691C4_INFO(inst) ((inst) + 0x00000865), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0870_ADDR(inst) ((inst) + 0x00000870) +#define BF_BF_08C91334_INFO(inst) ((inst) + 0x00000870), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0871_ADDR(inst) ((inst) + 0x00000871) +#define BF_BF_286AACF2_INFO(inst) ((inst) + 0x00000871), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#define REG_DC_DAC_ENABLE_ADDR(inst) ((inst) + 0x00000880) +#define BF_DC_DAC_ENABLE_INFO(inst) ((inst) + 0x00000880), 0x00000100 + +#define REG_DC_DAC_DATA0_ADDR(inst) ((inst) + 0x00000881) +#define BF_DC_DAC_DATA_INFO(inst) ((inst) + 0x00000881), 0x00000D00 + +#define REG_DC_DAC_DATA1_ADDR(inst) ((inst) + 0x00000882) + +#define REG_DC_DAC_LATCH_P_ADDR(inst) ((inst) + 0x00000883) +#define BF_DC_DAC_LATCH_P_INFO(inst) ((inst) + 0x00000883), 0x00000100 + +#define REG_DC_DAC_LATCH_N_ADDR(inst) ((inst) + 0x00000884) +#define BF_DC_DAC_LATCH_N_INFO(inst) ((inst) + 0x00000884), 0x00000100 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0890_ADDR(inst) ((inst) + 0x00000890) +#define BF_BF_4A5DBE9A_INFO(inst) ((inst) + 0x00000890), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0891_ADDR(inst) ((inst) + 0x00000891) +#define BF_BF_2B6942FC_INFO(inst) ((inst) + 0x00000891), 0x00000100 +#define BF_BF_1DA8B768_INFO(inst) ((inst) + 0x00000891), 0x00000101 +#define BF_BF_0B37568F_INFO(inst) ((inst) + 0x00000891), 0x00000102 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0892_ADDR(inst) ((inst) + 0x00000892) +#define BF_BF_56C723B1_INFO(inst) ((inst) + 0x00000892), 0x00000100 +#define BF_BF_0A1A0871_INFO(inst) ((inst) + 0x00000892), 0x00000101 +#define BF_BF_5362CEC4_INFO(inst) ((inst) + 0x00000892), 0x00000102 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0893_ADDR(inst) ((inst) + 0x00000893) +#define BF_BF_AA48D3AB_INFO(inst) ((inst) + 0x00000893), 0x00000100 +#define BF_BF_FA0D1E07_INFO(inst) ((inst) + 0x00000893), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#endif /* __ADI_APOLLO_BF_RAPTOR_OPEN_H__ */ +/*! @} */ \ No newline at end of file diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_rc_tuner_analog.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_rc_tuner_analog.h new file mode 100644 index 00000000000000..3c05fe42b9cfed --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_rc_tuner_analog.h @@ -0,0 +1,59 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:18 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_RC_TUNER_ANALOG_H__ +#define __ADI_APOLLO_BF_RC_TUNER_ANALOG_H__ + +/*============= D E F I N E S ==============*/ +#define RC_TUNER0 0x4C001B00 +#define RC_TUNER1 0x4C001F00 + +#define REG_RC_TUNER_CTRL_ADDR(inst) ((inst) + 0x00000000) +#define BF_RXADC_PD_INFO(inst) ((inst) + 0x00000000), 0x00000100 +#define BF_RXADC_RCAL_START_INFO(inst) ((inst) + 0x00000000), 0x00000101 +#define BF_RXADC_CCAL_START_INFO(inst) ((inst) + 0x00000000), 0x00000102 +#define BF_RXADC_PD_REF_INFO(inst) ((inst) + 0x00000000), 0x00000103 + +#define REG_RC_TUNER_CAP_MSB_ADDR(inst) ((inst) + 0x00000001) + +#define REG_RC_TUNER_CAP_LSB_ADDR(inst) ((inst) + 0x00000002) +#define BF_RXADC_CAP_SCALE_CONST_INFO(inst) ((inst) + 0x00000002), 0x00000C00 + +#define REG_RC_TUNER_CAP_SCALE_MSB_ADDR(inst) ((inst) + 0x00000003) + +#define REG_RC_TUNER_CAP_SCALE_LSB_ADDR(inst) ((inst) + 0x00000004) +#define BF_RXADC_G_SCALE_CONST_INFO(inst) ((inst) + 0x00000004), 0x00000C00 + +#define REG_RC_TUNER_MEAS1_LSB_ADDR(inst) ((inst) + 0x00000005) +#define BF_RXADC_G_MEASURED_1_INFO(inst) ((inst) + 0x00000005), 0x00000C00 + +#define REG_RC_TUNER_MEAS1_MSB_ADDR(inst) ((inst) + 0x00000006) + +#define REG_RC_TUNER_MEAS2_MSB_ADDR(inst) ((inst) + 0x00000007) + +#define REG_RC_TUNER_MEAS2_LSB_ADDR(inst) ((inst) + 0x00000008) +#define BF_RXADC_G_MEASURED_2_INFO(inst) ((inst) + 0x00000008), 0x00000C00 + +#define REG_RC_TUNER_COUNT_N1_MSB_ADDR(inst) ((inst) + 0x00000009) + +#define REG_RC_TUNER_COUNT_N1_LSB_ADDR(inst) ((inst) + 0x0000000A) +#define BF_RXADC_N1_COUNT_INFO(inst) ((inst) + 0x0000000A), 0x00000B00 + +#define REG_RC_TUNER_COUNT_N2_MSB_ADDR(inst) ((inst) + 0x0000000B) + +#define REG_RC_TUNER_COUNT_N2_LSB_ADDR(inst) ((inst) + 0x0000000C) +#define BF_RXADC_N2_COUNT_INFO(inst) ((inst) + 0x0000000C), 0x00000B00 + +#endif /* __ADI_APOLLO_BF_RC_TUNER_ANALOG_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_rsa.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_rsa.h new file mode 100644 index 00000000000000..ab920444608f72 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_rsa.h @@ -0,0 +1,839 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:18 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_RSA_H__ +#define __ADI_APOLLO_BF_RSA_H__ + +/*============= D E F I N E S ==============*/ +#ifdef USE_PRIVATE_BF +#define REG_EC_DAC_SPI_0_ADDR 0x4C004400 +#define BF_NVM_EC_TOTX_SPI_INFO 0x4C004400, 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_EC_DAC_SPI_1_ADDR 0x4C004401 + +#define REG_EC_DAC_SPI_2_ADDR 0x4C004402 + +#define REG_EC_DAC_SPI_3_ADDR 0x4C004403 + +#ifdef USE_PRIVATE_BF +#define REG_EC_DAC_REAL_0_ADDR 0x4C004404 +#define BF_NVM_EC_TOTX_REAL_INFO 0x4C004404, 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_EC_DAC_REAL_1_ADDR 0x4C004405 + +#define REG_EC_DAC_REAL_2_ADDR 0x4C004406 + +#define REG_EC_DAC_REAL_3_ADDR 0x4C004407 + +#ifdef USE_PRIVATE_BF +#define REG_EC_ADC_SPI_0_ADDR 0x4C004408 +#define BF_NVM_EC_TORX_SPI_INFO 0x4C004408, 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_EC_ADC_SPI_1_ADDR 0x4C004409 + +#define REG_EC_ADC_SPI_2_ADDR 0x4C00440A + +#define REG_EC_ADC_SPI_3_ADDR 0x4C00440B + +#ifdef USE_PRIVATE_BF +#define REG_EC_ADC_REAL_0_ADDR 0x4C00440C +#define BF_NVM_EC_TORX_REAL_INFO 0x4C00440C, 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_EC_ADC_REAL_1_ADDR 0x4C00440D + +#define REG_EC_ADC_REAL_2_ADDR 0x4C00440E + +#define REG_EC_ADC_REAL_3_ADDR 0x4C00440F + +#ifdef USE_PRIVATE_BF +#define REG_EC_ANA_SPI_0_ADDR 0x4C004410 +#define BF_NVM_EC_TOANA_SPI_INFO 0x4C004410, 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_EC_ANA_SPI_1_ADDR 0x4C004411 + +#define REG_EC_ANA_SPI_2_ADDR 0x4C004412 + +#define REG_EC_ANA_SPI_3_ADDR 0x4C004413 + +#ifdef USE_PRIVATE_BF +#define REG_EC_ANA_REAL_0_ADDR 0x4C004414 +#define BF_NVM_EC_TOANA_REAL_INFO 0x4C004414, 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_EC_ANA_REAL_1_ADDR 0x4C004415 + +#define REG_EC_ANA_REAL_2_ADDR 0x4C004416 + +#define REG_EC_ANA_REAL_3_ADDR 0x4C004417 + +#ifdef USE_PRIVATE_BF +#define REG_EC_GENERAL_0_ADDR 0x4C004418 +#define BF_EC_GENERAL_REAL_INFO 0x4C004418, 0x00004000 +#endif /* USE_PRIVATE_BF */ + +#define REG_EC_GENERAL_1_ADDR 0x4C004419 + +#define REG_EC_GENERAL_2_ADDR 0x4C00441A + +#define REG_EC_GENERAL_3_ADDR 0x4C00441B + +#define REG_EC_GENERAL_4_ADDR 0x4C00441C + +#define REG_EC_GENERAL_5_ADDR 0x4C00441D + +#define REG_EC_GENERAL_6_ADDR 0x4C00441E + +#define REG_EC_GENERAL_7_ADDR 0x4C00441F + +#define REG_RSA_CTRL_ADDR 0x4C004420 +#define BF_RSA_DECRYPT_EN_INFO 0x4C004420, 0x00000100 +#define BF_RSA_CLK_EN_INFO 0x4C004420, 0x00000101 +#define BF_RSA_DECRYPT_DONE_INFO 0x4C004420, 0x00000103 +#define BF_RSA_CHIP_UNLOCK_INFO 0x4C004420, 0x00000104 +#define BF_RSA_GROUP_UNLOCK_INFO 0x4C004420, 0x00000105 +#define BF_RSA_DECRYPT_CRC_FAIL_INFO 0x4C004420, 0x00000106 +#define BF_RSA_DECRYPT_ZERO_FAIL_INFO 0x4C004420, 0x00000107 + +#define REG_RSA_IN_M_0_ADDR 0x4C004421 + +#define REG_RSA_IN_M_1_ADDR 0x4C004422 + +#define REG_RSA_IN_M_2_ADDR 0x4C004423 + +#define REG_RSA_IN_M_3_ADDR 0x4C004424 + +#define REG_RSA_IN_M_4_ADDR 0x4C004425 + +#define REG_RSA_IN_M_5_ADDR 0x4C004426 + +#define REG_RSA_IN_M_6_ADDR 0x4C004427 + +#define REG_RSA_IN_M_7_ADDR 0x4C004428 + +#define REG_RSA_IN_M_8_ADDR 0x4C004429 + +#define REG_RSA_IN_M_9_ADDR 0x4C00442A + +#define REG_RSA_IN_M_10_ADDR 0x4C00442B + +#define REG_RSA_IN_M_11_ADDR 0x4C00442C + +#define REG_RSA_IN_M_12_ADDR 0x4C00442D + +#define REG_RSA_IN_M_13_ADDR 0x4C00442E + +#define REG_RSA_IN_M_14_ADDR 0x4C00442F + +#define REG_RSA_IN_M_15_ADDR 0x4C004430 + +#define REG_RSA_IN_M_16_ADDR 0x4C004431 + +#define REG_RSA_IN_M_17_ADDR 0x4C004432 + +#define REG_RSA_IN_M_18_ADDR 0x4C004433 + +#define REG_RSA_IN_M_19_ADDR 0x4C004434 + +#define REG_RSA_IN_M_20_ADDR 0x4C004435 + +#define REG_RSA_IN_M_21_ADDR 0x4C004436 + +#define REG_RSA_IN_M_22_ADDR 0x4C004437 + +#define REG_RSA_IN_M_23_ADDR 0x4C004438 + +#define REG_RSA_IN_M_24_ADDR 0x4C004439 + +#define REG_RSA_IN_M_25_ADDR 0x4C00443A + +#define REG_RSA_IN_M_26_ADDR 0x4C00443B + +#define REG_RSA_IN_M_27_ADDR 0x4C00443C + +#define REG_RSA_IN_M_28_ADDR 0x4C00443D + +#define REG_RSA_IN_M_29_ADDR 0x4C00443E + +#define REG_RSA_IN_M_30_ADDR 0x4C00443F + +#define REG_RSA_IN_M_31_ADDR 0x4C004440 + +#define REG_RSA_IN_M_32_ADDR 0x4C004441 + +#define REG_RSA_IN_M_33_ADDR 0x4C004442 + +#define REG_RSA_IN_M_34_ADDR 0x4C004443 + +#define REG_RSA_IN_M_35_ADDR 0x4C004444 + +#define REG_RSA_IN_M_36_ADDR 0x4C004445 + +#define REG_RSA_IN_M_37_ADDR 0x4C004446 + +#define REG_RSA_IN_M_38_ADDR 0x4C004447 + +#define REG_RSA_IN_M_39_ADDR 0x4C004448 + +#define REG_RSA_IN_M_40_ADDR 0x4C004449 + +#define REG_RSA_IN_M_41_ADDR 0x4C00444A + +#define REG_RSA_IN_M_42_ADDR 0x4C00444B + +#define REG_RSA_IN_M_43_ADDR 0x4C00444C + +#define REG_RSA_IN_M_44_ADDR 0x4C00444D + +#define REG_RSA_IN_M_45_ADDR 0x4C00444E + +#define REG_RSA_IN_M_46_ADDR 0x4C00444F + +#define REG_RSA_IN_M_47_ADDR 0x4C004450 + +#define REG_RSA_IN_M_48_ADDR 0x4C004451 + +#define REG_RSA_IN_M_49_ADDR 0x4C004452 + +#define REG_RSA_IN_M_50_ADDR 0x4C004453 + +#define REG_RSA_IN_M_51_ADDR 0x4C004454 + +#define REG_RSA_IN_M_52_ADDR 0x4C004455 + +#define REG_RSA_IN_M_53_ADDR 0x4C004456 + +#define REG_RSA_IN_M_54_ADDR 0x4C004457 + +#define REG_RSA_IN_M_55_ADDR 0x4C004458 + +#define REG_RSA_IN_M_56_ADDR 0x4C004459 + +#define REG_RSA_IN_M_57_ADDR 0x4C00445A + +#define REG_RSA_IN_M_58_ADDR 0x4C00445B + +#define REG_RSA_IN_M_59_ADDR 0x4C00445C + +#define REG_RSA_IN_M_60_ADDR 0x4C00445D + +#define REG_RSA_IN_M_61_ADDR 0x4C00445E + +#define REG_RSA_IN_M_62_ADDR 0x4C00445F + +#define REG_RSA_IN_M_63_ADDR 0x4C004460 + +#define REG_RSA_IN_M_64_ADDR 0x4C004461 + +#define REG_RSA_IN_M_65_ADDR 0x4C004462 + +#define REG_RSA_IN_M_66_ADDR 0x4C004463 + +#define REG_RSA_IN_M_67_ADDR 0x4C004464 + +#define REG_RSA_IN_M_68_ADDR 0x4C004465 + +#define REG_RSA_IN_M_69_ADDR 0x4C004466 + +#define REG_RSA_IN_M_70_ADDR 0x4C004467 + +#define REG_RSA_IN_M_71_ADDR 0x4C004468 + +#define REG_RSA_IN_M_72_ADDR 0x4C004469 + +#define REG_RSA_IN_M_73_ADDR 0x4C00446A + +#define REG_RSA_IN_M_74_ADDR 0x4C00446B + +#define REG_RSA_IN_M_75_ADDR 0x4C00446C + +#define REG_RSA_IN_M_76_ADDR 0x4C00446D + +#define REG_RSA_IN_M_77_ADDR 0x4C00446E + +#define REG_RSA_IN_M_78_ADDR 0x4C00446F + +#define REG_RSA_IN_M_79_ADDR 0x4C004470 + +#define REG_RSA_IN_M_80_ADDR 0x4C004471 + +#define REG_RSA_IN_M_81_ADDR 0x4C004472 + +#define REG_RSA_IN_M_82_ADDR 0x4C004473 + +#define REG_RSA_IN_M_83_ADDR 0x4C004474 + +#define REG_RSA_IN_M_84_ADDR 0x4C004475 + +#define REG_RSA_IN_M_85_ADDR 0x4C004476 + +#define REG_RSA_IN_M_86_ADDR 0x4C004477 + +#define REG_RSA_IN_M_87_ADDR 0x4C004478 + +#define REG_RSA_IN_M_88_ADDR 0x4C004479 + +#define REG_RSA_IN_M_89_ADDR 0x4C00447A + +#define REG_RSA_IN_M_90_ADDR 0x4C00447B + +#define REG_RSA_IN_M_91_ADDR 0x4C00447C + +#define REG_RSA_IN_M_92_ADDR 0x4C00447D + +#define REG_RSA_IN_M_93_ADDR 0x4C00447E + +#define REG_RSA_IN_M_94_ADDR 0x4C00447F + +#define REG_RSA_IN_M_95_ADDR 0x4C004480 + +#define REG_RSA_IN_M_96_ADDR 0x4C004481 + +#define REG_RSA_IN_M_97_ADDR 0x4C004482 + +#define REG_RSA_IN_M_98_ADDR 0x4C004483 + +#define REG_RSA_IN_M_99_ADDR 0x4C004484 + +#define REG_RSA_IN_M_100_ADDR 0x4C004485 + +#define REG_RSA_IN_M_101_ADDR 0x4C004486 + +#define REG_RSA_IN_M_102_ADDR 0x4C004487 + +#define REG_RSA_IN_M_103_ADDR 0x4C004488 + +#define REG_RSA_IN_M_104_ADDR 0x4C004489 + +#define REG_RSA_IN_M_105_ADDR 0x4C00448A + +#define REG_RSA_IN_M_106_ADDR 0x4C00448B + +#define REG_RSA_IN_M_107_ADDR 0x4C00448C + +#define REG_RSA_IN_M_108_ADDR 0x4C00448D + +#define REG_RSA_IN_M_109_ADDR 0x4C00448E + +#define REG_RSA_IN_M_110_ADDR 0x4C00448F + +#define REG_RSA_IN_M_111_ADDR 0x4C004490 + +#define REG_RSA_IN_M_112_ADDR 0x4C004491 + +#define REG_RSA_IN_M_113_ADDR 0x4C004492 + +#define REG_RSA_IN_M_114_ADDR 0x4C004493 + +#define REG_RSA_IN_M_115_ADDR 0x4C004494 + +#define REG_RSA_IN_M_116_ADDR 0x4C004495 + +#define REG_RSA_IN_M_117_ADDR 0x4C004496 + +#define REG_RSA_IN_M_118_ADDR 0x4C004497 + +#define REG_RSA_IN_M_119_ADDR 0x4C004498 + +#define REG_RSA_IN_M_120_ADDR 0x4C004499 + +#define REG_RSA_IN_M_121_ADDR 0x4C00449A + +#define REG_RSA_IN_M_122_ADDR 0x4C00449B + +#define REG_RSA_IN_M_123_ADDR 0x4C00449C + +#define REG_RSA_IN_M_124_ADDR 0x4C00449D + +#define REG_RSA_IN_M_125_ADDR 0x4C00449E + +#define REG_RSA_IN_M_126_ADDR 0x4C00449F + +#define REG_RSA_IN_M_127_ADDR 0x4C0044A0 + +#define REG_RSA_IN_M_128_ADDR 0x4C0044A1 + +#define REG_RSA_IN_M_129_ADDR 0x4C0044A2 + +#define REG_RSA_IN_M_130_ADDR 0x4C0044A3 + +#define REG_RSA_IN_M_131_ADDR 0x4C0044A4 + +#define REG_RSA_IN_M_132_ADDR 0x4C0044A5 + +#define REG_RSA_IN_M_133_ADDR 0x4C0044A6 + +#define REG_RSA_IN_M_134_ADDR 0x4C0044A7 + +#define REG_RSA_IN_M_135_ADDR 0x4C0044A8 + +#define REG_RSA_IN_M_136_ADDR 0x4C0044A9 + +#define REG_RSA_IN_M_137_ADDR 0x4C0044AA + +#define REG_RSA_IN_M_138_ADDR 0x4C0044AB + +#define REG_RSA_IN_M_139_ADDR 0x4C0044AC + +#define REG_RSA_IN_M_140_ADDR 0x4C0044AD + +#define REG_RSA_IN_M_141_ADDR 0x4C0044AE + +#define REG_RSA_IN_M_142_ADDR 0x4C0044AF + +#define REG_RSA_IN_M_143_ADDR 0x4C0044B0 + +#define REG_RSA_IN_M_144_ADDR 0x4C0044B1 + +#define REG_RSA_IN_M_145_ADDR 0x4C0044B2 + +#define REG_RSA_IN_M_146_ADDR 0x4C0044B3 + +#define REG_RSA_IN_M_147_ADDR 0x4C0044B4 + +#define REG_RSA_IN_M_148_ADDR 0x4C0044B5 + +#define REG_RSA_IN_M_149_ADDR 0x4C0044B6 + +#define REG_RSA_IN_M_150_ADDR 0x4C0044B7 + +#define REG_RSA_IN_M_151_ADDR 0x4C0044B8 + +#define REG_RSA_IN_M_152_ADDR 0x4C0044B9 + +#define REG_RSA_IN_M_153_ADDR 0x4C0044BA + +#define REG_RSA_IN_M_154_ADDR 0x4C0044BB + +#define REG_RSA_IN_M_155_ADDR 0x4C0044BC + +#define REG_RSA_IN_M_156_ADDR 0x4C0044BD + +#define REG_RSA_IN_M_157_ADDR 0x4C0044BE + +#define REG_RSA_IN_M_158_ADDR 0x4C0044BF + +#define REG_RSA_IN_M_159_ADDR 0x4C0044C0 + +#define REG_RSA_IN_M_160_ADDR 0x4C0044C1 + +#define REG_RSA_IN_M_161_ADDR 0x4C0044C2 + +#define REG_RSA_IN_M_162_ADDR 0x4C0044C3 + +#define REG_RSA_IN_M_163_ADDR 0x4C0044C4 + +#define REG_RSA_IN_M_164_ADDR 0x4C0044C5 + +#define REG_RSA_IN_M_165_ADDR 0x4C0044C6 + +#define REG_RSA_IN_M_166_ADDR 0x4C0044C7 + +#define REG_RSA_IN_M_167_ADDR 0x4C0044C8 + +#define REG_RSA_IN_M_168_ADDR 0x4C0044C9 + +#define REG_RSA_IN_M_169_ADDR 0x4C0044CA + +#define REG_RSA_IN_M_170_ADDR 0x4C0044CB + +#define REG_RSA_IN_M_171_ADDR 0x4C0044CC + +#define REG_RSA_IN_M_172_ADDR 0x4C0044CD + +#define REG_RSA_IN_M_173_ADDR 0x4C0044CE + +#define REG_RSA_IN_M_174_ADDR 0x4C0044CF + +#define REG_RSA_IN_M_175_ADDR 0x4C0044D0 + +#define REG_RSA_IN_M_176_ADDR 0x4C0044D1 + +#define REG_RSA_IN_M_177_ADDR 0x4C0044D2 + +#define REG_RSA_IN_M_178_ADDR 0x4C0044D3 + +#define REG_RSA_IN_M_179_ADDR 0x4C0044D4 + +#define REG_RSA_IN_M_180_ADDR 0x4C0044D5 + +#define REG_RSA_IN_M_181_ADDR 0x4C0044D6 + +#define REG_RSA_IN_M_182_ADDR 0x4C0044D7 + +#define REG_RSA_IN_M_183_ADDR 0x4C0044D8 + +#define REG_RSA_IN_M_184_ADDR 0x4C0044D9 + +#define REG_RSA_IN_M_185_ADDR 0x4C0044DA + +#define REG_RSA_IN_M_186_ADDR 0x4C0044DB + +#define REG_RSA_IN_M_187_ADDR 0x4C0044DC + +#define REG_RSA_IN_M_188_ADDR 0x4C0044DD + +#define REG_RSA_IN_M_189_ADDR 0x4C0044DE + +#define REG_RSA_IN_M_190_ADDR 0x4C0044DF + +#define REG_RSA_IN_M_191_ADDR 0x4C0044E0 + +#define REG_RSA_IN_M_192_ADDR 0x4C0044E1 + +#define REG_RSA_IN_M_193_ADDR 0x4C0044E2 + +#define REG_RSA_IN_M_194_ADDR 0x4C0044E3 + +#define REG_RSA_IN_M_195_ADDR 0x4C0044E4 + +#define REG_RSA_IN_M_196_ADDR 0x4C0044E5 + +#define REG_RSA_IN_M_197_ADDR 0x4C0044E6 + +#define REG_RSA_IN_M_198_ADDR 0x4C0044E7 + +#define REG_RSA_IN_M_199_ADDR 0x4C0044E8 + +#define REG_RSA_IN_M_200_ADDR 0x4C0044E9 + +#define REG_RSA_IN_M_201_ADDR 0x4C0044EA + +#define REG_RSA_IN_M_202_ADDR 0x4C0044EB + +#define REG_RSA_IN_M_203_ADDR 0x4C0044EC + +#define REG_RSA_IN_M_204_ADDR 0x4C0044ED + +#define REG_RSA_IN_M_205_ADDR 0x4C0044EE + +#define REG_RSA_IN_M_206_ADDR 0x4C0044EF + +#define REG_RSA_IN_M_207_ADDR 0x4C0044F0 + +#define REG_RSA_IN_M_208_ADDR 0x4C0044F1 + +#define REG_RSA_IN_M_209_ADDR 0x4C0044F2 + +#define REG_RSA_IN_M_210_ADDR 0x4C0044F3 + +#define REG_RSA_IN_M_211_ADDR 0x4C0044F4 + +#define REG_RSA_IN_M_212_ADDR 0x4C0044F5 + +#define REG_RSA_IN_M_213_ADDR 0x4C0044F6 + +#define REG_RSA_IN_M_214_ADDR 0x4C0044F7 + +#define REG_RSA_IN_M_215_ADDR 0x4C0044F8 + +#define REG_RSA_IN_M_216_ADDR 0x4C0044F9 + +#define REG_RSA_IN_M_217_ADDR 0x4C0044FA + +#define REG_RSA_IN_M_218_ADDR 0x4C0044FB + +#define REG_RSA_IN_M_219_ADDR 0x4C0044FC + +#define REG_RSA_IN_M_220_ADDR 0x4C0044FD + +#define REG_RSA_IN_M_221_ADDR 0x4C0044FE + +#define REG_RSA_IN_M_222_ADDR 0x4C0044FF + +#define REG_RSA_IN_M_223_ADDR 0x4C004500 + +#define REG_RSA_IN_M_224_ADDR 0x4C004501 + +#define REG_RSA_IN_M_225_ADDR 0x4C004502 + +#define REG_RSA_IN_M_226_ADDR 0x4C004503 + +#define REG_RSA_IN_M_227_ADDR 0x4C004504 + +#define REG_RSA_IN_M_228_ADDR 0x4C004505 + +#define REG_RSA_IN_M_229_ADDR 0x4C004506 + +#define REG_RSA_IN_M_230_ADDR 0x4C004507 + +#define REG_RSA_IN_M_231_ADDR 0x4C004508 + +#define REG_RSA_IN_M_232_ADDR 0x4C004509 + +#define REG_RSA_IN_M_233_ADDR 0x4C00450A + +#define REG_RSA_IN_M_234_ADDR 0x4C00450B + +#define REG_RSA_IN_M_235_ADDR 0x4C00450C + +#define REG_RSA_IN_M_236_ADDR 0x4C00450D + +#define REG_RSA_IN_M_237_ADDR 0x4C00450E + +#define REG_RSA_IN_M_238_ADDR 0x4C00450F + +#define REG_RSA_IN_M_239_ADDR 0x4C004510 + +#define REG_RSA_IN_M_240_ADDR 0x4C004511 + +#define REG_RSA_IN_M_241_ADDR 0x4C004512 + +#define REG_RSA_IN_M_242_ADDR 0x4C004513 + +#define REG_RSA_IN_M_243_ADDR 0x4C004514 + +#define REG_RSA_IN_M_244_ADDR 0x4C004515 + +#define REG_RSA_IN_M_245_ADDR 0x4C004516 + +#define REG_RSA_IN_M_246_ADDR 0x4C004517 + +#define REG_RSA_IN_M_247_ADDR 0x4C004518 + +#define REG_RSA_IN_M_248_ADDR 0x4C004519 + +#define REG_RSA_IN_M_249_ADDR 0x4C00451A + +#define REG_RSA_IN_M_250_ADDR 0x4C00451B + +#define REG_RSA_IN_M_251_ADDR 0x4C00451C + +#define REG_RSA_IN_M_252_ADDR 0x4C00451D + +#define REG_RSA_IN_M_253_ADDR 0x4C00451E + +#define REG_RSA_IN_M_254_ADDR 0x4C00451F + +#define REG_RSA_IN_M_255_ADDR 0x4C004520 + +#define REG_CHIPID_0_RSA_ADDR 0x4C004521 + +#define REG_CHIPID_1_RSA_ADDR 0x4C004522 + +#define REG_CHIPID_2_RSA_ADDR 0x4C004523 + +#define REG_CHIPID_3_RSA_ADDR 0x4C004524 + +#define REG_CHIPID_4_RSA_ADDR 0x4C004525 + +#define REG_CHIPID_5_RSA_ADDR 0x4C004526 + +#define REG_CHIPID_6_RSA_ADDR 0x4C004527 + +#define REG_CHIPID_7_RSA_ADDR 0x4C004528 + +#define REG_CHIPID_8_RSA_ADDR 0x4C004529 + +#define REG_CHIPID_9_RSA_ADDR 0x4C00452A + +#define REG_CHIPID_10_RSA_ADDR 0x4C00452B + +#define REG_CHIPID_11_RSA_ADDR 0x4C00452C + +#define REG_CHIPID_12_RSA_ADDR 0x4C00452D + +#define REG_CHIPID_13_RSA_ADDR 0x4C00452E + +#define REG_CHIPID_14_RSA_ADDR 0x4C00452F + +#define REG_CHIPID_15_RSA_ADDR 0x4C004530 + +#define REG_GROUPID_0_RSA_ADDR 0x4C004531 +#define BF_GROUPID_INFO 0x4C004531, 0x00002000 + +#define REG_GROUPID_1_RSA_ADDR 0x4C004532 + +#define REG_GROUPID_2_RSA_ADDR 0x4C004533 + +#define REG_GROUPID_3_RSA_ADDR 0x4C004534 + +#define REG_DUT_REG_REV_ADDR 0x4C004535 +#define BF_DUT_REG_REV_INFO 0x4C004535, 0x00000800 + +#define REG_ATE_ID_ADDR 0x4C004536 +#define BF_ATE_ID_INFO 0x4C004536, 0x00000800 + +#define REG_HIB_INFO_0_ADDR 0x4C004537 +#define BF_HIB_INFO_0_INFO 0x4C004537, 0x00000800 + +#define REG_HIB_INFO_1_ADDR 0x4C004538 +#define BF_HIB_INFO_1_INFO 0x4C004538, 0x00000800 + +#define REG_FUSE_INFO_ADDR 0x4C004539 +#define BF_FUSE_INFO_INFO 0x4C004539, 0x00000800 + +#define REG_PROGRAM_REV_0_ADDR 0x4C00453A +#define BF_PROGRAM_REV_0_INFO 0x4C00453A, 0x00000800 + +#define REG_PROGRAM_REV_1_ADDR 0x4C00453B +#define BF_PROGRAM_REV_1_INFO 0x4C00453B, 0x00000800 + +#define REG_DATE_0_ADDR 0x4C00453C +#define BF_DATE_0_INFO 0x4C00453C, 0x00000800 + +#define REG_DATE_1_ADDR 0x4C00453D +#define BF_DATE_1_INFO 0x4C00453D, 0x00000800 + +#define REG_SEQUENTIAL_SN_0_RSA_ADDR 0x4C00453E +#define BF_SEQUENTIAL_SN_0_RSA_INFO 0x4C00453E, 0x00000800 + +#define REG_SEQUENTIAL_SN_1_RSA_ADDR 0x4C00453F +#define BF_SEQUENTIAL_SN_1_RSA_INFO 0x4C00453F, 0x00000800 + +#define REG_FPGA_PROGRAM_ID_ADDR 0x4C004540 +#define BF_FPGA_PROGRAM_ID_INFO 0x4C004540, 0x00000800 + +#define REG_FUSE_PASSED_ADDR 0x4C004541 +#define BF_FUSE_PASSED_INFO 0x4C004541, 0x00000800 + +#define REG_SPARE_0_RSA_ADDR 0x4C004542 +#define BF_SPARE_0_INFO 0x4C004542, 0x00000800 + +#define REG_SPARE_1_RSA_ADDR 0x4C004543 +#define BF_SPARE_1_INFO 0x4C004543, 0x00000800 + +#define REG_SPARE_2_RSA_ADDR 0x4C004544 +#define BF_SPARE_2_INFO 0x4C004544, 0x00000800 + +#define REG_SPARE_3_RSA_ADDR 0x4C004545 +#define BF_SPARE_3_INFO 0x4C004545, 0x00000800 + +#define REG_SPARE_4_ADDR 0x4C004546 +#define BF_SPARE_4_INFO 0x4C004546, 0x00000800 + +#define REG_SPARE_5_ADDR 0x4C004547 +#define BF_SPARE_5_INFO 0x4C004547, 0x00000800 + +#define REG_SPARE_6_ADDR 0x4C004548 +#define BF_SPARE_6_INFO 0x4C004548, 0x00000800 + +#define REG_SPARE_7_ADDR 0x4C004549 +#define BF_SPARE_7_INFO 0x4C004549, 0x00000800 + +#define REG_SPARE_8_ADDR 0x4C00454A +#define BF_SPARE_8_INFO 0x4C00454A, 0x00000800 + +#define REG_SPARE_9_ADDR 0x4C00454B +#define BF_SPARE_9_INFO 0x4C00454B, 0x00000800 + +#define REG_SPARE_10_ADDR 0x4C00454C +#define BF_SPARE_10_INFO 0x4C00454C, 0x00000800 + +#define REG_SPARE_11_ADDR 0x4C00454D +#define BF_SPARE_11_INFO 0x4C00454D, 0x00000800 + +#define REG_SPARE_12_ADDR 0x4C00454E +#define BF_SPARE_12_INFO 0x4C00454E, 0x00000800 + +#define REG_SPARE_13_ADDR 0x4C00454F +#define BF_SPARE_13_INFO 0x4C00454F, 0x00000800 + +#define REG_SPARE_14_ADDR 0x4C004550 +#define BF_SPARE_14_INFO 0x4C004550, 0x00000800 + +#define REG_RESERVED_0_ADDR 0x4C004551 +#define BF_RESERVED_0_INFO 0x4C004551, 0x00000800 + +#define REG_RESERVED_1_ADDR 0x4C004552 +#define BF_RESERVED_1_INFO 0x4C004552, 0x00000800 + +#define REG_RESERVED_2_ADDR 0x4C004553 +#define BF_RESERVED_2_INFO 0x4C004553, 0x00000800 + +#define REG_RESERVED_3_ADDR 0x4C004554 +#define BF_RESERVED_3_INFO 0x4C004554, 0x00000800 + +#define REG_RESERVED_4_ADDR 0x4C004555 +#define BF_RESERVED_4_INFO 0x4C004555, 0x00000800 + +#define REG_RESERVED_5_ADDR 0x4C004556 +#define BF_RESERVED_5_INFO 0x4C004556, 0x00000800 + +#define REG_FW_REV_CTRL_0_L_ADDR 0x4C004557 +#define BF_FW_REV_CTRL_0_INFO 0x4C004557, 0x00001800 + +#define REG_FW_REV_CTRL_0_M_ADDR 0x4C004558 + +#define REG_FW_REV_CTRL_0_H_ADDR 0x4C004559 + +#define REG_FW_REV_CTRL_1_L_ADDR 0x4C00455A +#define BF_FW_REV_CTRL_1_INFO 0x4C00455A, 0x00001800 + +#define REG_FW_REV_CTRL_1_M_ADDR 0x4C00455B + +#define REG_FW_REV_CTRL_1_H_ADDR 0x4C00455C + +#define REG_FW_REV_CTRL_2_L_ADDR 0x4C00455D +#define BF_FW_REV_CTRL_2_INFO 0x4C00455D, 0x00001800 + +#define REG_FW_REV_CTRL_2_M_ADDR 0x4C00455E + +#define REG_FW_REV_CTRL_2_H_ADDR 0x4C00455F + +#define REG_FW_REV_CTRL_3_L_ADDR 0x4C004560 +#define BF_FW_REV_CTRL_3_INFO 0x4C004560, 0x00001800 + +#define REG_FW_REV_CTRL_3_M_ADDR 0x4C004561 + +#define REG_FW_REV_CTRL_3_H_ADDR 0x4C004562 + +#define REG_FW_REV_CTRL_4_L_ADDR 0x4C004563 +#define BF_FW_REV_CTRL_4_INFO 0x4C004563, 0x00001800 + +#define REG_FW_REV_CTRL_4_M_ADDR 0x4C004564 + +#define REG_FW_REV_CTRL_4_H_ADDR 0x4C004565 + +#define REG_FW_REV_CTRL_5_L_ADDR 0x4C004566 +#define BF_FW_REV_CTRL_5_INFO 0x4C004566, 0x00001800 + +#define REG_FW_REV_CTRL_5_M_ADDR 0x4C004567 + +#define REG_FW_REV_CTRL_5_H_ADDR 0x4C004568 + +#define REG_FW_REV_CTRL_6_L_ADDR 0x4C004569 +#define BF_FW_REV_CTRL_6_INFO 0x4C004569, 0x00001800 + +#define REG_FW_REV_CTRL_6_M_ADDR 0x4C00456A + +#define REG_FW_REV_CTRL_6_H_ADDR 0x4C00456B + +#define REG_FW_REV_CTRL_7_L_ADDR 0x4C00456C +#define BF_FW_REV_CTRL_7_INFO 0x4C00456C, 0x00001800 + +#define REG_FW_REV_CTRL_7_M_ADDR 0x4C00456D + +#define REG_FW_REV_CTRL_7_H_ADDR 0x4C00456E + +#define REG_FW_REV_CTRL_8_L_ADDR 0x4C00456F +#define BF_FW_REV_CTRL_8_INFO 0x4C00456F, 0x00001800 + +#define REG_FW_REV_CTRL_8_M_ADDR 0x4C004570 + +#define REG_FW_REV_CTRL_8_H_ADDR 0x4C004571 + +#define REG_FW_REV_CTRL_9_L_ADDR 0x4C004572 +#define BF_FW_REV_CTRL_9_INFO 0x4C004572, 0x00001800 + +#define REG_FW_REV_CTRL_9_M_ADDR 0x4C004573 + +#define REG_FW_REV_CTRL_9_H_ADDR 0x4C004574 + +#endif /* __ADI_APOLLO_BF_RSA_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_rtclk_gen.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_rtclk_gen.h new file mode 100644 index 00000000000000..f2a7d3b8211e00 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_rtclk_gen.h @@ -0,0 +1,118 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:18 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_RTCLK_GEN_H__ +#define __ADI_APOLLO_BF_RTCLK_GEN_H__ + +/*============= D E F I N E S ==============*/ +#define REG_DUAL_CLK_MODE_ADDR 0x4C001010 +#define BF_SINGLE_DUAL_CLK_SEL_INFO 0x4C001010, 0x00000100 + +#define REG_RTCLKGEN_RX_ADDR 0x4C001011 +#define BF_RTCLKGEN_MODE_RX_A_INFO 0x4C001011, 0x00000300 +#define BF_RTCLKGEN_MODE_RX_B_INFO 0x4C001011, 0x00000304 + +#define REG_RTCLKGEN_TX_ADDR 0x4C001012 +#define BF_RTCLKGEN_MODE_TX_A_INFO 0x4C001012, 0x00000300 +#define BF_RTCLKGEN_MODE_TX_B_INFO 0x4C001012, 0x00000304 + +#define REG_RTCLKGEN_PD_ADDR 0x4C001013 +#define BF_RTCLKGEN_PD_INFO 0x4C001013, 0x00000400 + +#define REG_DIGRTCLK_OFFINSYNC_ADDR 0x4C001014 +#define BF_GATEOFFCLK_INSYNC_INFO 0x4C001014, 0x00000400 + +#define REG_SDS_REFCLK_DIV_RATIO_ADDR 0x4C001015 +#define BF_SERDES_PLL_REFCLK_DIV_INFO 0x4C001015, 0x00000500 +#define BF_SERDES_PLL_REFCLK_DIV_UPDT_INFO 0x4C001015, 0x00000107 + +#define REG_UP_RTCLK_DIV_RATIO_ADDR 0x4C001017 +#define BF_UP_RTCLK_DIV_RTCLK_GEN_INFO 0x4C001017, 0x00000400 +#define BF_UP_RTCLK_DIV_UPDT_RTCLK_GEN_INFO 0x4C001017, 0x00000107 + +#define REG_CLK_PD_DEBUG_ADDR 0x4C001018 +#define BF_UP_RTCLK_EN_INFO 0x4C001018, 0x00000100 +#define BF_UP_RTCLK_CFG_SEL_INFO 0x4C001018, 0x00000103 +#define BF_SERDES_PLL_REFCLK_EN_INFO 0x4C001018, 0x00000104 + +#define REG_FORCE_ATSPD_CLK_EN_ADDR 0x4C001019 +#define BF_FORCE_ATSPD_CLK_EN_INFO 0x4C001019, 0x00000100 + +#define REG_CLK_SEL_CTRL_ADDR 0x4C00101A +#define BF_FREERUN_CLK_SEL_INFO 0x4C00101A, 0x00000200 +#define BF_ATSPD_CLK_AB_SEL_INFO 0x4C00101A, 0x00000104 + +#define REG_ATSPD_CLK_CTRL_ADDR 0x4C00101B +#define BF_ATSPD_CLK_C_DIV_INFO 0x4C00101B, 0x00000400 +#define BF_ATSPD_CLK_AB_DIV_INFO 0x4C00101B, 0x00000404 + +#define REG_DIVP_PH_MAP_RX_ADDR 0x4C00101C +#define BF_DIVGMODE2_DIV2_PHMAP_INFO 0x4C00101C, 0x00000100 +#define BF_DIVGMODE3_DIV2_PHMAP_INFO 0x4C00101C, 0x00000101 +#define BF_DIVGMODE2_DIV4_PHMAP_INFO 0x4C00101C, 0x00000204 + +#define REG_SYNC_MASK_RTCLK_ADDR 0x4C001020 +#define BF_SYNC_MASK_RTCLK_INFO 0x4C001020, 0x00000800 + +#define REG_SYNC_MASK_ADCFIFO_ADDR 0x4C001021 +#define BF_SYNC_MASK_ADCFIFO_INFO 0x4C001021, 0x00000400 + +#define REG_SYNC_MASK_DACFIFO_ADDR 0x4C001022 +#define BF_SYNC_MASK_DACFIFO_INFO 0x4C001022, 0x00000800 + +#define REG_SYNC_MASK_RXTX_ADDR 0x4C001023 +#define BF_SYNC_MASK_RXTX_INFO 0x4C001023, 0x00000400 + +#define REG_SYNC_MASK_RXTXLINK_ADDR 0x4C001024 +#define BF_SYNC_MASK_RXTXLINK_INFO 0x4C001024, 0x00000800 + +#define REG_SYNC_MASK_LPBKFIFO_ADDR 0x4C001025 +#define BF_SYNC_MASK_LPBKFIFO_INFO 0x4C001025, 0x00000200 + +#define REG_XBTI_RESET_ADDR 0x4C00102F +#define BF_XBTI_CLK_EN_INFO 0x4C00102F, 0x00000100 +#define BF_XBTI_RESET_INFO 0x4C00102F, 0x00000104 + +#define REG_XBTI_CLK_CTRL_ADDR 0x4C001030 +#define BF_XBTI_CLK_DIV_UPDT_INFO 0x4C001030, 0x00000100 +#define BF_XBTI_CLK_DIV_INFO 0x4C001030, 0x00000204 + +#define REG_XBTI_CTRL0_ADDR 0x4C001031 +#define BF_XBTI_CTRL_INFO 0x4C001031, 0x00002000 + +#define REG_XBTI_CTRL1_ADDR 0x4C001032 + +#define REG_XBTI_CTRL2_ADDR 0x4C001033 + +#define REG_XBTI_CTRL3_ADDR 0x4C001034 + +#define REG_XBTI_STATE0_ADDR 0x4C001035 +#define BF_XBTI_STATUS_INFO 0x4C001035, 0x00004000 + +#define REG_XBTI_STATE1_ADDR 0x4C001036 + +#define REG_XBTI_STATE2_ADDR 0x4C001037 + +#define REG_XBTI_STATE3_ADDR 0x4C001038 + +#define REG_XBTI_STATE4_ADDR 0x4C001039 + +#define REG_XBTI_STATE5_ADDR 0x4C00103A + +#define REG_XBTI_STATE6_ADDR 0x4C00103B + +#define REG_XBTI_STATE7_ADDR 0x4C00103C + +#endif /* __ADI_APOLLO_BF_RTCLK_GEN_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_rx_bmem.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_rx_bmem.h new file mode 100644 index 00000000000000..22e7fbec56586e --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_rx_bmem.h @@ -0,0 +1,168 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:19 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_RX_BMEM_H__ +#define __ADI_APOLLO_BF_RX_BMEM_H__ + +/*============= D E F I N E S ==============*/ +#define RX_BMEM0_REG_RX_SLICE_0_RX_DIGITAL0 0x60204000 +#define RX_BMEM0_REG_RX_SLICE_1_RX_DIGITAL0 0x60404000 +#define RX_BMEM0_REG_RX_SLICE_0_RX_DIGITAL1 0x60A04000 +#define RX_BMEM0_REG_RX_SLICE_1_RX_DIGITAL1 0x60C04000 + +#define REG_BMEM_CONTROL_1_RX_BMEM_ADDR(inst) ((inst) + 0x00000000) +#define BF_BMEM_EN_RX_BMEM_INFO(inst) ((inst) + 0x00000000), 0x00000100 +#define BF_BMEM_START_RX_BMEM_INFO(inst) ((inst) + 0x00000000), 0x00000101 +#define BF_BMEM_MODE_RX_BMEM_INFO(inst) ((inst) + 0x00000000), 0x00000202 +#define BF_BMEM_RESET_RX_BMEM_INFO(inst) ((inst) + 0x00000000), 0x00000104 +#define BF_BMEM_SLEEP_RX_BMEM_INFO(inst) ((inst) + 0x00000000), 0x00000105 +#define BF_BMEM_SHUT_DOWN_RX_BMEM_INFO(inst) ((inst) + 0x00000000), 0x00000106 +#define BF_FAST_NSLOW_MODE_RX_BMEM_INFO(inst) ((inst) + 0x00000000), 0x00000107 + +#define REG_BMEM_CONTROL_2_RX_BMEM_ADDR(inst) ((inst) + 0x00000001) +#define BF_TRIG_MODE_RX_BMEM_INFO(inst) ((inst) + 0x00000001), 0x00000100 +#define BF_TRIG_MODE_SCLR_EN_RX_BMEM_INFO(inst) ((inst) + 0x00000001), 0x00000101 +#define BF_PARITY_CHECK_EN_RX_BMEM_INFO(inst) ((inst) + 0x00000001), 0x00000102 +#define BF_SAMPLE_SIZE_RX_BMEM_INFO(inst) ((inst) + 0x00000001), 0x00000103 +#define BF_RAMCLK_PH_DIS_RX_BMEM_INFO(inst) ((inst) + 0x00000001), 0x00000104 +#define BF_BMEM_8T8R_CAP_MASK_RX_BMEM_INFO(inst) ((inst) + 0x00000001), 0x00000205 +#define BF_HOP_DLY_SEL_MODE_RX_BMEM_INFO(inst) ((inst) + 0x00000001), 0x00000107 + +#define REG_SAMPLE_DELAY_0_RX_BMEM_ADDR(inst) ((inst) + 0x00000002) +#define BF_SAMPLE_DLY_RX_BMEM_INFO(inst) ((inst) + 0x00000002), 0x00001000 + +#define REG_SAMPLE_DELAY_1_RX_BMEM_ADDR(inst) ((inst) + 0x00000003) + +#define REG_HOP_DELAY0_0_RX_BMEM_ADDR(inst) ((inst) + 0x00000004) +#define BF_HOP_DELAY0_RX_BMEM_INFO(inst) ((inst) + 0x00000004), 0x00001000 + +#define REG_HOP_DELAY0_1_RX_BMEM_ADDR(inst) ((inst) + 0x00000005) + +#define REG_HOP_DELAY1_0_RX_BMEM_ADDR(inst) ((inst) + 0x00000006) +#define BF_HOP_DELAY1_RX_BMEM_INFO(inst) ((inst) + 0x00000006), 0x00001000 + +#define REG_HOP_DELAY1_1_RX_BMEM_ADDR(inst) ((inst) + 0x00000007) + +#define REG_HOP_DELAY2_0_RX_BMEM_ADDR(inst) ((inst) + 0x00000008) +#define BF_HOP_DELAY2_RX_BMEM_INFO(inst) ((inst) + 0x00000008), 0x00001000 + +#define REG_HOP_DELAY2_1_RX_BMEM_ADDR(inst) ((inst) + 0x00000009) + +#define REG_HOP_DELAY3_0_RX_BMEM_ADDR(inst) ((inst) + 0x0000000A) +#define BF_HOP_DELAY3_RX_BMEM_INFO(inst) ((inst) + 0x0000000A), 0x00001000 + +#define REG_HOP_DELAY3_1_RX_BMEM_ADDR(inst) ((inst) + 0x0000000B) + +#define REG_ST_ADDR_CPT_0_RX_BMEM_ADDR(inst) ((inst) + 0x0000000C) +#define BF_ST_ADDR_CPT_RX_BMEM_INFO(inst) ((inst) + 0x0000000C), 0x00000F00 + +#define REG_ST_ADDR_CPT_1_RX_BMEM_ADDR(inst) ((inst) + 0x0000000D) + +#define REG_END_ADDR_CPT_0_RX_BMEM_ADDR(inst) ((inst) + 0x0000000E) +#define BF_END_ADDR_CPT_RX_BMEM_INFO(inst) ((inst) + 0x0000000E), 0x00000F00 + +#define REG_END_ADDR_CPT_1_RX_BMEM_ADDR(inst) ((inst) + 0x0000000F) + +#define REG_ST_ADDR_AWG_0_RX_BMEM_ADDR(inst) ((inst) + 0x00000010) +#define BF_ST_ADDR_AWG_RX_BMEM_INFO(inst) ((inst) + 0x00000010), 0x00000F00 + +#define REG_ST_ADDR_AWG_1_RX_BMEM_ADDR(inst) ((inst) + 0x00000011) + +#define REG_END_ADDR_AWG_0_RX_BMEM_ADDR(inst) ((inst) + 0x00000012) +#define BF_END_ADDR_AWG_RX_BMEM_INFO(inst) ((inst) + 0x00000012), 0x00000F00 + +#define REG_END_ADDR_AWG_1_RX_BMEM_ADDR(inst) ((inst) + 0x00000013) + +#define REG_ST_CPTR_ON_SMPL_VAL_RX_BMEM_ADDR(inst) ((inst) + 0x00000014) +#define BF_ST_CPTR_ON_SMPL_VAL_RX_BMEM_INFO(inst) ((inst) + 0x00000014), 0x00000800 + +#define REG_SMPL_VAL_FOR_CPTR0_0_RX_BMEM_ADDR(inst) ((inst) + 0x00000015) +#define BF_SMPL_VAL_FOR_CPTR0_RX_BMEM_INFO(inst) ((inst) + 0x00000015), 0x00002000 + +#define REG_SMPL_VAL_FOR_CPTR0_1_RX_BMEM_ADDR(inst) ((inst) + 0x00000016) + +#define REG_SMPL_VAL_FOR_CPTR0_2_RX_BMEM_ADDR(inst) ((inst) + 0x00000017) + +#define REG_SMPL_VAL_FOR_CPTR0_3_RX_BMEM_ADDR(inst) ((inst) + 0x00000018) + +#define REG_SMPL_VAL_FOR_CPTR1_0_RX_BMEM_ADDR(inst) ((inst) + 0x00000019) +#define BF_SMPL_VAL_FOR_CPTR1_RX_BMEM_INFO(inst) ((inst) + 0x00000019), 0x00002000 + +#define REG_SMPL_VAL_FOR_CPTR1_1_RX_BMEM_ADDR(inst) ((inst) + 0x0000001A) + +#define REG_SMPL_VAL_FOR_CPTR1_2_RX_BMEM_ADDR(inst) ((inst) + 0x0000001B) + +#define REG_SMPL_VAL_FOR_CPTR1_3_RX_BMEM_ADDR(inst) ((inst) + 0x0000001C) + +#define REG_SMPL_VAL_FOR_CPTR2_0_RX_BMEM_ADDR(inst) ((inst) + 0x0000001D) +#define BF_SMPL_VAL_FOR_CPTR2_RX_BMEM_INFO(inst) ((inst) + 0x0000001D), 0x00002000 + +#define REG_SMPL_VAL_FOR_CPTR2_1_RX_BMEM_ADDR(inst) ((inst) + 0x0000001E) + +#define REG_SMPL_VAL_FOR_CPTR2_2_RX_BMEM_ADDR(inst) ((inst) + 0x0000001F) + +#define REG_SMPL_VAL_FOR_CPTR2_3_RX_BMEM_ADDR(inst) ((inst) + 0x00000020) + +#define REG_SMPL_VAL_FOR_CPTR3_0_RX_BMEM_ADDR(inst) ((inst) + 0x00000021) +#define BF_SMPL_VAL_FOR_CPTR3_RX_BMEM_INFO(inst) ((inst) + 0x00000021), 0x00002000 + +#define REG_SMPL_VAL_FOR_CPTR3_1_RX_BMEM_ADDR(inst) ((inst) + 0x00000022) + +#define REG_SMPL_VAL_FOR_CPTR3_2_RX_BMEM_ADDR(inst) ((inst) + 0x00000023) + +#define REG_SMPL_VAL_FOR_CPTR3_3_RX_BMEM_ADDR(inst) ((inst) + 0x00000024) + +#define REG_SMPL_VAL_FOR_CPTR4_0_RX_BMEM_ADDR(inst) ((inst) + 0x00000025) +#define BF_SMPL_VAL_FOR_CPTR4_RX_BMEM_INFO(inst) ((inst) + 0x00000025), 0x00002000 + +#define REG_SMPL_VAL_FOR_CPTR4_1_RX_BMEM_ADDR(inst) ((inst) + 0x00000026) + +#define REG_SMPL_VAL_FOR_CPTR4_2_RX_BMEM_ADDR(inst) ((inst) + 0x00000027) + +#define REG_SMPL_VAL_FOR_CPTR4_3_RX_BMEM_ADDR(inst) ((inst) + 0x00000028) + +#define REG_SMPL_VAL_FOR_CPTR5_0_RX_BMEM_ADDR(inst) ((inst) + 0x00000029) +#define BF_SMPL_VAL_FOR_CPTR5_RX_BMEM_INFO(inst) ((inst) + 0x00000029), 0x00002000 + +#define REG_SMPL_VAL_FOR_CPTR5_1_RX_BMEM_ADDR(inst) ((inst) + 0x0000002A) + +#define REG_SMPL_VAL_FOR_CPTR5_2_RX_BMEM_ADDR(inst) ((inst) + 0x0000002B) + +#define REG_SMPL_VAL_FOR_CPTR5_3_RX_BMEM_ADDR(inst) ((inst) + 0x0000002C) + +#define REG_SMPL_VAL_FOR_CPTR6_0_RX_BMEM_ADDR(inst) ((inst) + 0x0000002D) +#define BF_SMPL_VAL_FOR_CPTR6_RX_BMEM_INFO(inst) ((inst) + 0x0000002D), 0x00002000 + +#define REG_SMPL_VAL_FOR_CPTR6_1_RX_BMEM_ADDR(inst) ((inst) + 0x0000002E) + +#define REG_SMPL_VAL_FOR_CPTR6_2_RX_BMEM_ADDR(inst) ((inst) + 0x0000002F) + +#define REG_SMPL_VAL_FOR_CPTR6_3_RX_BMEM_ADDR(inst) ((inst) + 0x00000030) + +#define REG_SMPL_VAL_FOR_CPTR7_0_RX_BMEM_ADDR(inst) ((inst) + 0x00000031) +#define BF_SMPL_VAL_FOR_CPTR7_RX_BMEM_INFO(inst) ((inst) + 0x00000031), 0x00002000 + +#define REG_SMPL_VAL_FOR_CPTR7_1_RX_BMEM_ADDR(inst) ((inst) + 0x00000032) + +#define REG_SMPL_VAL_FOR_CPTR7_2_RX_BMEM_ADDR(inst) ((inst) + 0x00000033) + +#define REG_SMPL_VAL_FOR_CPTR7_3_RX_BMEM_ADDR(inst) ((inst) + 0x00000034) + +#define REG_BMEM_STATUS_RX_BMEM_ADDR(inst) ((inst) + 0x00000035) +#define BF_CAPTURE_TRIG_PHASE_RX_BMEM_INFO(inst) ((inst) + 0x00000035), 0x00000600 +#define BF_FULL_IRQ_RX_BMEM_INFO(inst) ((inst) + 0x00000035), 0x00000106 +#define BF_PARITY_ERR_RX_BMEM_INFO(inst) ((inst) + 0x00000035), 0x00000107 + +#endif /* __ADI_APOLLO_BF_RX_BMEM_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_rx_cddc.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_rx_cddc.h new file mode 100644 index 00000000000000..8c82f8c49bac6a --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_rx_cddc.h @@ -0,0 +1,139 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:20 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_RX_CDDC_H__ +#define __ADI_APOLLO_BF_RX_CDDC_H__ + +/*============= D E F I N E S ==============*/ +#define RX_CDDC_RX_SLICE_0_RX_DIGITAL0 0x60373000 +#define RX_CDDC_RX_SLICE_1_RX_DIGITAL0 0x60573000 +#define RX_CDDC_RX_SLICE_0_RX_DIGITAL1 0x60B73000 +#define RX_CDDC_RX_SLICE_1_RX_DIGITAL1 0x60D73000 + +#define REG_COARSE_DEC_CTRL_ADDR(inst) ((inst) + 0x00000000) +#define BF_COARSE_DDC_DEC_SEL_INFO(inst) ((inst) + 0x00000000), 0x00000400 +#define BF_FINE_BYPASS_INFO(inst) ((inst) + 0x00000000), 0x00000106 +#define BF_LINK_NUM_RX_CDDC_INFO(inst) ((inst) + 0x00000000), 0x00000107 + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_BASE_OFFSET_ADDR(inst) ((inst) + 0x00000001) +#define BF_DDC_BASE_OFFSET_RX_CDDC_INFO(inst) ((inst) + 0x00000001), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_CLK_OFFSET_WR_EN_ADDR(inst) ((inst) + 0x00000002) +#define BF_CLK_OFFSET_WR_EN_RX_CDDC_INFO(inst) ((inst) + 0x00000002), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#define REG_COARSE_FILT_DEL_CTRL_ADDR(inst) ((inst) + 0x00000003) +#define BF_HB1_DEL_RX_CDDC_INFO(inst) ((inst) + 0x00000003), 0x00000100 +#define BF_HB2_DEL_RX_CDDC_INFO(inst) ((inst) + 0x00000003), 0x00000101 +#define BF_TB1_DEL_INFO(inst) ((inst) + 0x00000003), 0x00000202 + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_CLK_DEBUG_ADDR(inst) ((inst) + 0x00000004) +#define BF_DEBUG_CDDC_CLKOFF_N_INFO(inst) ((inst) + 0x00000004), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_I_HB1_OFFSET_PH0_ADDR(inst) ((inst) + 0x00000005) +#define BF_COARSE_I_HB1_OFFSET_PH0_INFO(inst) ((inst) + 0x00000005), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_I_HB1_OFFSET_PH1_ADDR(inst) ((inst) + 0x00000006) +#define BF_COARSE_I_HB1_OFFSET_PH1_INFO(inst) ((inst) + 0x00000006), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_Q_HB1_OFFSET_PH0_ADDR(inst) ((inst) + 0x00000007) +#define BF_COARSE_Q_HB1_OFFSET_PH0_INFO(inst) ((inst) + 0x00000007), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_Q_HB1_OFFSET_PH1_ADDR(inst) ((inst) + 0x00000008) +#define BF_COARSE_Q_HB1_OFFSET_PH1_INFO(inst) ((inst) + 0x00000008), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_I_HB2_OFFSET_PH0_ADDR(inst) ((inst) + 0x00000009) +#define BF_COARSE_I_HB2_OFFSET_PH0_INFO(inst) ((inst) + 0x00000009), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_I_HB2_OFFSET_PH1_ADDR(inst) ((inst) + 0x0000000A) +#define BF_COARSE_I_HB2_OFFSET_PH1_INFO(inst) ((inst) + 0x0000000A), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_Q_HB2_OFFSET_PH0_ADDR(inst) ((inst) + 0x0000000B) +#define BF_COARSE_Q_HB2_OFFSET_PH0_INFO(inst) ((inst) + 0x0000000B), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_Q_HB2_OFFSET_PH1_ADDR(inst) ((inst) + 0x0000000C) +#define BF_COARSE_Q_HB2_OFFSET_PH1_INFO(inst) ((inst) + 0x0000000C), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_I_TB1_OFFSET_PH0_ADDR(inst) ((inst) + 0x0000000D) +#define BF_COARSE_I_TB1_OFFSET_PH0_INFO(inst) ((inst) + 0x0000000D), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_I_TB1_OFFSET_PH1_ADDR(inst) ((inst) + 0x0000000E) +#define BF_COARSE_I_TB1_OFFSET_PH1_INFO(inst) ((inst) + 0x0000000E), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_Q_TB1_OFFSET_PH0_ADDR(inst) ((inst) + 0x0000000F) +#define BF_COARSE_Q_TB1_OFFSET_PH0_INFO(inst) ((inst) + 0x0000000F), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_Q_TB1_OFFSET_PH1_ADDR(inst) ((inst) + 0x00000010) +#define BF_COARSE_Q_TB1_OFFSET_PH1_INFO(inst) ((inst) + 0x00000010), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_I_FILT_IN_OFFSET_ADDR(inst) ((inst) + 0x00000013) +#define BF_COARSE_I_FILT_IN_OFFSET_INFO(inst) ((inst) + 0x00000013), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_Q_FILT_IN_OFFSET_ADDR(inst) ((inst) + 0x00000014) +#define BF_COARSE_Q_FILT_IN_OFFSET_INFO(inst) ((inst) + 0x00000014), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_I_FILT_OUT_OFFSET_ADDR(inst) ((inst) + 0x00000015) +#define BF_COARSE_I_FILT_OUT_OFFSET_INFO(inst) ((inst) + 0x00000015), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_Q_FILT_OUT_OFFSET_ADDR(inst) ((inst) + 0x00000016) +#define BF_COARSE_Q_FILT_OUT_OFFSET_INFO(inst) ((inst) + 0x00000016), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_FILTER_GAIN_EN_RX_CDDC_ADDR(inst) ((inst) + 0x00000017) +#define BF_HB1_GAIN_EN_RX_CDDC_INFO(inst) ((inst) + 0x00000017), 0x00000100 +#define BF_TB1_GAIN_EN_INFO(inst) ((inst) + 0x00000017), 0x00000101 + +#ifdef USE_PRIVATE_BF +#define REG_GPIO_EN_RX_CDDC_ADDR(inst) ((inst) + 0x00000018) +#define BF_GPIO_DEC_SEL_RX_CDDC_INFO(inst) ((inst) + 0x00000018), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#endif /* __ADI_APOLLO_BF_RX_CDDC_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_rx_datin.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_rx_datin.h new file mode 100644 index 00000000000000..6ca532e8a7f2eb --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_rx_datin.h @@ -0,0 +1,70 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:19 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_RX_DATIN_H__ +#define __ADI_APOLLO_BF_RX_DATIN_H__ + +/*============= D E F I N E S ==============*/ +#define RX_DATIN_RX_SLICE_0_RX_DIGITAL0 0x60209000 +#define RX_DATIN_RX_SLICE_1_RX_DIGITAL0 0x60409000 +#define RX_DATIN_RX_SLICE_0_RX_DIGITAL1 0x60A09000 +#define RX_DATIN_RX_SLICE_1_RX_DIGITAL1 0x60C09000 + +#define REG_DFIFO_CTRL_RX_DATIN_ADDR(inst) ((inst) + 0x00000000) +#define BF_DFIFO_EN_RX_DATIN_INFO(inst) ((inst) + 0x00000000), 0x00000100 +#define BF_RXFIFO_WRCLK_INVERT_INFO(inst) ((inst) + 0x00000000), 0x00000101 +#define BF_DAC_FIFO_FORCEON_CTRL_RX_DATIN_INFO(inst) ((inst) + 0x00000000), 0x00000404 + +#define REG_LAT_CTRL_RX_DATIN_ADDR(inst) ((inst) + 0x00000001) +#define BF_LAT_PGM_MODE_RX_DATIN_INFO(inst) ((inst) + 0x00000001), 0x00000200 +#define BF_WR_RD_OFFSET_RX_DATIN_INFO(inst) ((inst) + 0x00000001), 0x00000302 + +#define REG_LAT_SPI_CTRL_RX_DATIN_ADDR(inst) ((inst) + 0x00000002) +#define BF_LAT_RD_SPI_RX_DATIN_INFO(inst) ((inst) + 0x00000002), 0x00000300 +#define BF_LAT_WR_SPI_RX_DATIN_INFO(inst) ((inst) + 0x00000002), 0x00000403 + +#ifdef USE_PRIVATE_BF +#define REG_SYNCCNT_STRB_RX_DATIN_ADDR(inst) ((inst) + 0x00000003) +#define BF_RDSYNCCNT_WRSTRB_RX_DATIN_INFO(inst) ((inst) + 0x00000003), 0x00000300 +#define BF_WRSYNCCNT_RDSTRB_RX_DATIN_INFO(inst) ((inst) + 0x00000003), 0x00000403 +#endif /* USE_PRIVATE_BF */ + +#define REG_LAT_REAL_RX_DATIN_ADDR(inst) ((inst) + 0x00000004) +#define BF_LAT_RD_REAL_RX_DATIN_INFO(inst) ((inst) + 0x00000004), 0x00000300 +#define BF_LAT_WR_REAL_RX_DATIN_INFO(inst) ((inst) + 0x00000004), 0x00000403 + +#define REG_SYNC_STATE_RX_DATIN_ADDR(inst) ((inst) + 0x00000005) +#define BF_RDSYNC_STATE_RX_DATIN_INFO(inst) ((inst) + 0x00000005), 0x00000200 +#define BF_WRSYNC_STATE_RX_DATIN_INFO(inst) ((inst) + 0x00000005), 0x00000202 + +#define REG_DEBUG_CTRL_ADDR(inst) ((inst) + 0x00000006) +#define BF_DBG_EN_RX_DATIN_INFO(inst) ((inst) + 0x00000006), 0x00000100 +#define BF_DBG_OUT_INFO(inst) ((inst) + 0x00000006), 0x00000101 +#define BF_DBG_OUT_DEC2_INFO(inst) ((inst) + 0x00000006), 0x00000102 + +#define REG_ADC_MUX_SEL_ADDR(inst) ((inst) + 0x00000007) +#define BF_ADC_0_MUX_SEL_INFO(inst) ((inst) + 0x00000007), 0x00000200 +#define BF_ADC_1_MUX_SEL_INFO(inst) ((inst) + 0x00000007), 0x00000202 + +#define REG_ADC_WR_SETUP_CTRL_ADDR(inst) ((inst) + 0x00000008) +#define BF_ADC_ANA_BRIDGE_WR_SETUP_CYCLES_INFO(inst) ((inst) + 0x00000008), 0x00000600 + +#define REG_ADC_WR_HOLD_CTRL_ADDR(inst) ((inst) + 0x00000009) +#define BF_ADC_ANA_BRIDGE_WR_HOLD_CYCLES_INFO(inst) ((inst) + 0x00000009), 0x00000600 + +#define REG_ADC_RD_CTRL_ADDR(inst) ((inst) + 0x0000000A) +#define BF_ADC_ANA_BRIDGE_RD_CYCLES_INFO(inst) ((inst) + 0x0000000A), 0x00000600 + +#endif /* __ADI_APOLLO_BF_RX_DATIN_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_rx_eng.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_rx_eng.h new file mode 100644 index 00000000000000..afe1a67072215b --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_rx_eng.h @@ -0,0 +1,65 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:19 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_RX_ENG_H__ +#define __ADI_APOLLO_BF_RX_ENG_H__ + +/*============= D E F I N E S ==============*/ +#define RX_ENG_RX_DIGITAL0 0x60010000 +#define RX_ENG_RX_DIGITAL1 0x60810000 + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_DDC_BIST_OP_ADDR(inst, n) ((inst) + 0x00000000 + 1 * (n)) +#define BF_COARSE_DDC_BIST_EN_INFO(inst, n) ((inst) + 0x00000000 + 1 * (n)), 0x00000100 +#define BF_COARSE_DDC_BIST_INIT_INFO(inst, n) ((inst) + 0x00000000 + 1 * (n)), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_DDC_BIST_CRC_LO_ADDR(inst, n) ((inst) + 0x00000004 + 1 * (n)) +#define BF_COARSE_DDC_BIST_CRC_LO_INFO(inst, n) ((inst) + 0x00000004 + 1 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_DDC_BIST_CRC_HI_ADDR(inst, n) ((inst) + 0x00000008 + 1 * (n)) +#define BF_COARSE_DDC_BIST_CRC_HI_INFO(inst, n) ((inst) + 0x00000008 + 1 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_DDC_BIST_EN_STATUS_ADDR(inst, n) ((inst) + 0x0000000C + 1 * (n)) +#define BF_COARSE_DDC_BIST_EN_STATUS_INFO(inst, n) ((inst) + 0x0000000C + 1 * (n)), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FINE_DDC_BIST_OP_ADDR(inst, n) ((inst) + 0x00000010 + 1 * (n)) +#define BF_FINE_DDC_BIST_EN_INFO(inst, n) ((inst) + 0x00000010 + 1 * (n)), 0x00000103 +#define BF_FINE_DDC_BIST_INIT_INFO(inst, n) ((inst) + 0x00000010 + 1 * (n)), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FINE_DDC_BIST_CRC_LO_ADDR(inst, n) ((inst) + 0x00000018 + 1 * (n)) +#define BF_FINE_DDC_BIST_CRC_LO_INFO(inst, n) ((inst) + 0x00000018 + 1 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FINE_DDC_BIST_CRC_HI_ADDR(inst, n) ((inst) + 0x00000020 + 1 * (n)) +#define BF_FINE_DDC_BIST_CRC_HI_INFO(inst, n) ((inst) + 0x00000020 + 1 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FINE_DDC_BIST_EN_STATUS_ADDR(inst, n) ((inst) + 0x00000028 + 1 * (n)) +#define BF_FINE_DDC_BIST_EN_STATUS_INFO(inst, n) ((inst) + 0x00000028 + 1 * (n)), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#endif /* __ADI_APOLLO_BF_RX_ENG_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_rx_fine_ddc.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_rx_fine_ddc.h new file mode 100644 index 00000000000000..0a972385d58cd8 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_rx_fine_ddc.h @@ -0,0 +1,140 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:20 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_RX_FINE_DDC_H__ +#define __ADI_APOLLO_BF_RX_FINE_DDC_H__ + +/*============= D E F I N E S ==============*/ +#define RX_FINE_DDC0_RX_SLICE_0_RX_DIGITAL0 0x60360000 +#define RX_FINE_DDC1_RX_SLICE_0_RX_DIGITAL0 0x60361000 +#define RX_FINE_DDC0_RX_SLICE_1_RX_DIGITAL0 0x60560000 +#define RX_FINE_DDC1_RX_SLICE_1_RX_DIGITAL0 0x60561000 +#define RX_FINE_DDC0_RX_SLICE_0_RX_DIGITAL1 0x60B60000 +#define RX_FINE_DDC1_RX_SLICE_0_RX_DIGITAL1 0x60B61000 +#define RX_FINE_DDC0_RX_SLICE_1_RX_DIGITAL1 0x60D60000 +#define RX_FINE_DDC1_RX_SLICE_1_RX_DIGITAL1 0x60D61000 + +#define REG_FINE_DEC_CTRL_ADDR(inst) ((inst) + 0x00000000) +#define BF_FINE_DDC_DEC_SEL_INFO(inst) ((inst) + 0x00000000), 0x00000400 +#define BF_LINK_NUM_RX_FINE_DDC_INFO(inst) ((inst) + 0x00000000), 0x00000106 + +#define REG_FINE_FILT_DEL_CTRL_ADDR(inst) ((inst) + 0x00000001) +#define BF_HB1_DEL_RX_FINE_DDC_INFO(inst) ((inst) + 0x00000001), 0x00000100 +#define BF_HB2_DEL_RX_FINE_DDC_INFO(inst) ((inst) + 0x00000001), 0x00000101 +#define BF_HB3_DEL_INFO(inst) ((inst) + 0x00000001), 0x00000102 +#define BF_HB4_DEL_INFO(inst) ((inst) + 0x00000001), 0x00000103 +#define BF_HB5_DEL_INFO(inst) ((inst) + 0x00000001), 0x00000104 +#define BF_HB6_DEL_INFO(inst) ((inst) + 0x00000001), 0x00000105 + +#ifdef USE_PRIVATE_BF +#define REG_FINE_BASE_OFFSET_RX_FINE_DDC_ADDR(inst) ((inst) + 0x00000002) +#define BF_DDC_BASE_OFFSET_RX_FINE_DDC_INFO(inst) ((inst) + 0x00000002), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FINE_CLK_OFFSET_WR_EN_ADDR(inst) ((inst) + 0x00000003) +#define BF_CLK_OFFSET_WR_EN_RX_FINE_DDC_INFO(inst) ((inst) + 0x00000003), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#define REG_FINE_CLK_DEBUG_ADDR(inst) ((inst) + 0x00000004) +#define BF_DEBUG_FDDC_CLKOFF_N_INFO(inst) ((inst) + 0x00000004), 0x00000800 + +#ifdef USE_PRIVATE_BF +#define REG_FINE_I_FILT_OUT_OFFSET_ADDR(inst) ((inst) + 0x00000007) +#define BF_FINE_I_FILT_OUT_OFFSET_INFO(inst) ((inst) + 0x00000007), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FINE_Q_FILT_OUT_OFFSET_ADDR(inst) ((inst) + 0x00000008) +#define BF_FINE_Q_FILT_OUT_OFFSET_INFO(inst) ((inst) + 0x00000008), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FINE_I_FILT_IN_OFFSET_ADDR(inst) ((inst) + 0x00000009) +#define BF_FINE_I_FILT_IN_OFFSET_INFO(inst) ((inst) + 0x00000009), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FINE_Q_FILT_IN_OFFSET_ADDR(inst) ((inst) + 0x0000000A) +#define BF_FINE_Q_FILT_IN_OFFSET_INFO(inst) ((inst) + 0x0000000A), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FINE_I_HB1_OFFSET_ADDR(inst) ((inst) + 0x0000000B) +#define BF_FINE_I_HB1_OFFSET_INFO(inst) ((inst) + 0x0000000B), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FINE_Q_HB1_OFFSET_ADDR(inst) ((inst) + 0x0000000C) +#define BF_FINE_Q_HB1_OFFSET_INFO(inst) ((inst) + 0x0000000C), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FINE_I_HB2_OFFSET_ADDR(inst) ((inst) + 0x0000000D) +#define BF_FINE_I_HB2_OFFSET_INFO(inst) ((inst) + 0x0000000D), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FINE_Q_HB2_OFFSET_ADDR(inst) ((inst) + 0x0000000E) +#define BF_FINE_Q_HB2_OFFSET_INFO(inst) ((inst) + 0x0000000E), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FINE_I_HB3_OFFSET_ADDR(inst) ((inst) + 0x0000000F) +#define BF_FINE_I_HB3_OFFSET_INFO(inst) ((inst) + 0x0000000F), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FINE_Q_HB3_OFFSET_ADDR(inst) ((inst) + 0x00000010) +#define BF_FINE_Q_HB3_OFFSET_INFO(inst) ((inst) + 0x00000010), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FINE_I_HB4_OFFSET_ADDR(inst) ((inst) + 0x00000011) +#define BF_FINE_I_HB4_OFFSET_INFO(inst) ((inst) + 0x00000011), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FINE_Q_HB4_OFFSET_ADDR(inst) ((inst) + 0x00000012) +#define BF_FINE_Q_HB4_OFFSET_INFO(inst) ((inst) + 0x00000012), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FINE_I_HB5_OFFSET_ADDR(inst) ((inst) + 0x00000013) +#define BF_FINE_I_HB5_OFFSET_INFO(inst) ((inst) + 0x00000013), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FINE_Q_HB5_OFFSET_ADDR(inst) ((inst) + 0x00000014) +#define BF_FINE_Q_HB5_OFFSET_INFO(inst) ((inst) + 0x00000014), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FINE_I_HB6_OFFSET_ADDR(inst) ((inst) + 0x00000015) +#define BF_FINE_I_HB6_OFFSET_INFO(inst) ((inst) + 0x00000015), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FINE_Q_HB6_OFFSET_ADDR(inst) ((inst) + 0x00000016) +#define BF_FINE_Q_HB6_OFFSET_INFO(inst) ((inst) + 0x00000016), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_FILTER_GAIN_EN_RX_FINE_DDC_ADDR(inst) ((inst) + 0x00000017) +#define BF_HB1_GAIN_EN_RX_FINE_DDC_INFO(inst) ((inst) + 0x00000017), 0x00000100 + +#define REG_GPIO_EN_RX_FINE_DDC_ADDR(inst) ((inst) + 0x00000018) +#define BF_GPIO_DEC_SEL_RX_FINE_DDC_INFO(inst) ((inst) + 0x00000018), 0x00000100 + +#endif /* __ADI_APOLLO_BF_RX_FINE_DDC_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_rx_loopback.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_rx_loopback.h new file mode 100644 index 00000000000000..ee8a8d6dc74246 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_rx_loopback.h @@ -0,0 +1,40 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:19 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_RX_LOOPBACK_H__ +#define __ADI_APOLLO_BF_RX_LOOPBACK_H__ + +/*============= D E F I N E S ==============*/ +#define RX_LOOPBACK_RX_SLICE_0_RX_DIGITAL0 0x60200000 +#define RX_LOOPBACK_RX_SLICE_1_RX_DIGITAL0 0x60400000 +#define RX_LOOPBACK_RX_SLICE_0_RX_DIGITAL1 0x60A00000 +#define RX_LOOPBACK_RX_SLICE_1_RX_DIGITAL1 0x60C00000 + +#define REG_WRPTR_SYNC_RSTVAL_ADDR(inst) ((inst) + 0x00000000) +#define BF_WRPTR_SYNC_RSTVAL_INFO(inst) ((inst) + 0x00000000), 0x00000200 + +#define REG_ADC_DATA_OVR_STATUS_ADDR(inst) ((inst) + 0x00000001) +#define BF_ADC_DATA_OVR_STATUS_INFO(inst) ((inst) + 0x00000001), 0x00000400 + +#define REG_ADC_DATA_OVR_CLR_ADDR(inst) ((inst) + 0x00000002) +#define BF_ADC_DATA_OVR_CLEAR_INFO(inst) ((inst) + 0x00000002), 0x00000400 + +#define REG_LPBK_WR_EN_ADDR(inst) ((inst) + 0x00000003) +#define BF_LPBK_WR_EN_INFO(inst) ((inst) + 0x00000003), 0x00000100 + +#define REG_DBG_DATA_OFF_EN_ADDR(inst) ((inst) + 0x00000004) +#define BF_DBG_DATA_OFF_EN_INFO(inst) ((inst) + 0x00000004), 0x00000100 + +#endif /* __ADI_APOLLO_BF_RX_LOOPBACK_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_rx_misc.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_rx_misc.h new file mode 100644 index 00000000000000..fb6a1f2d6098ba --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_rx_misc.h @@ -0,0 +1,139 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:19 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_RX_MISC_H__ +#define __ADI_APOLLO_BF_RX_MISC_H__ + +/*============= D E F I N E S ==============*/ +#define RX_MISC_RX_DIGITAL0 0x60000000 +#define RX_MISC_RX_DIGITAL1 0x60800000 + +#define REG_LOW_SAMP_RX_MISC_ADDR(inst) ((inst) + 0x0000001A) +#define BF_LOW_SAMP_RX_MISC_INFO(inst) ((inst) + 0x0000001A), 0x00000100 + +#define REG_DATAPATH_CTRL_ADDR(inst) ((inst) + 0x0000001B) +#ifdef USE_PRIVATE_BF +#define BF_RXEN_CDDC_INFO(inst) ((inst) + 0x0000001B), 0x00000200 +#endif /* USE_PRIVATE_BF */ +#ifdef USE_PRIVATE_BF +#define BF_RXEN_FDDC_INFO(inst) ((inst) + 0x0000001B), 0x00000402 +#endif /* USE_PRIVATE_BF */ +#define BF_DATAPATH_CLK_EN_INFO(inst) ((inst) + 0x0000001B), 0x00000206 + +#define REG_CB_SEL0_ADDR(inst) ((inst) + 0x0000001C) +#define BF_CB_SEL_F0_INFO(inst) ((inst) + 0x0000001C), 0x00000300 +#define BF_CB_SEL_F1_INFO(inst) ((inst) + 0x0000001C), 0x00000303 + +#define REG_CB_SEL1_ADDR(inst) ((inst) + 0x0000001D) +#define BF_CB_SEL_F2_INFO(inst) ((inst) + 0x0000001D), 0x00000300 +#define BF_CB_SEL_F3_INFO(inst) ((inst) + 0x0000001D), 0x00000303 + +#ifdef USE_PRIVATE_BF +#define REG_HSDIN_DBG_CNT_EN_ADDR(inst) ((inst) + 0x0000033D) +#define BF_HSDIN_DBG_CNT_EN_INFO(inst) ((inst) + 0x0000033D), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_LINX_DBG_CNT_EN_RX_MISC_ADDR(inst) ((inst) + 0x0000033E) +#define BF_LINX_DBG_CNT_EN_INFO(inst) ((inst) + 0x0000033E), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_PFILT_DBG_CNT_EN_ADDR(inst) ((inst) + 0x0000033F) +#define BF_PFILT_DBG_CNT_EN_INFO(inst) ((inst) + 0x0000033F), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CDDC0_DBG_CNT_EN_ADDR(inst) ((inst) + 0x00000340) +#define BF_CDDC0_DBG_CNT_EN_INFO(inst) ((inst) + 0x00000340), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CDDC1_DBG_CNT_EN_ADDR(inst) ((inst) + 0x00000341) +#define BF_CDDC1_DBG_CNT_EN_INFO(inst) ((inst) + 0x00000341), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FDDC_DBG_CNT_EN_ADDR(inst) ((inst) + 0x00000342) +#define BF_FDDC_DBG_CNT_EN_INFO(inst) ((inst) + 0x00000342), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CFIR_DBG_CNT_EN_ADDR(inst) ((inst) + 0x00000343) +#define BF_CFIR_DBG_CNT_EN_INFO(inst) ((inst) + 0x00000343), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JTX_DBG_CNT_EN_ADDR(inst) ((inst) + 0x00000344) +#define BF_JTX_DBG_CNT_EN_INFO(inst) ((inst) + 0x00000344), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_HSDIN_DBG_MUX_SEL_ADDR(inst) ((inst) + 0x00000345) +#define BF_HSDIN_DBG_MUX_SEL_INFO(inst) ((inst) + 0x00000345), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_LINX_DBG_MUX_SEL_ADDR(inst) ((inst) + 0x00000346) +#define BF_LINX_DBG_MUX_SEL_INFO(inst) ((inst) + 0x00000346), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_PFILT_DBG_MUX_SEL_ADDR(inst) ((inst) + 0x00000347) +#define BF_PFILT_DBG_MUX_SEL_INFO(inst) ((inst) + 0x00000347), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CDDC0_DBG_MUX_SEL_ADDR(inst) ((inst) + 0x00000348) +#define BF_CDDC0_DBG_MUX_SEL_INFO(inst) ((inst) + 0x00000348), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CDDC1_DBG_MUX_SEL_ADDR(inst) ((inst) + 0x00000349) +#define BF_CDDC1_DBG_MUX_SEL_INFO(inst) ((inst) + 0x00000349), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FDDC_DBG_MUX_SEL_ADDR(inst) ((inst) + 0x0000034A) +#define BF_FDDC_DBG_MUX_SEL_INFO(inst) ((inst) + 0x0000034A), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CFIR_DBG_MUX_SEL_ADDR(inst) ((inst) + 0x0000034B) +#define BF_CFIR_DBG_MUX_SEL_INFO(inst) ((inst) + 0x0000034B), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JTX_DBG_MUX_SEL_ADDR(inst) ((inst) + 0x0000034C) +#define BF_JTX_DBG_MUX_SEL_INFO(inst) ((inst) + 0x0000034C), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ADC_BIST_CTRL_STATUS_ADDR(inst, n) ((inst) + 0x00000400 + 2 * (n)) +#define BF_ADC_BIST_ENABLE_INFO(inst, n) ((inst) + 0x00000400 + 2 * (n)), 0x00000100 +#define BF_ADC_BIST_START_INFO(inst, n) ((inst) + 0x00000400 + 2 * (n)), 0x00000101 +#define BF_ADC_BIST_MODE_SEL_INFO(inst, n) ((inst) + 0x00000400 + 2 * (n)), 0x00000102 +#define BF_ADC_BIST_INVERT_INFO(inst, n) ((inst) + 0x00000400 + 2 * (n)), 0x00000103 +#define BF_ADC_BIST_PASS_INFO(inst, n) ((inst) + 0x00000400 + 2 * (n)), 0x00000104 +#define BF_ADC_BIST_FAIL_INFO(inst, n) ((inst) + 0x00000400 + 2 * (n)), 0x00000105 +#define BF_ADC_BIST_DONE_INFO(inst, n) ((inst) + 0x00000400 + 2 * (n)), 0x00000106 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ADC_BIST_ERRORS_ADDR(inst, n) ((inst) + 0x00000401 + 2 * (n)) +#define BF_ADC_BIST_ERRORS_INFO(inst, n) ((inst) + 0x00000401 + 2 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#endif /* __ADI_APOLLO_BF_RX_MISC_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_rx_smon.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_rx_smon.h new file mode 100644 index 00000000000000..b41538621661bb --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_rx_smon.h @@ -0,0 +1,73 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:19 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_RX_SMON_H__ +#define __ADI_APOLLO_BF_RX_SMON_H__ + +/*============= D E F I N E S ==============*/ +#define RX_SMON0_RX_SLICE_0_RX_DIGITAL0 0x60207000 +#define RX_SMON1_RX_SLICE_0_RX_DIGITAL0 0x60208000 +#define RX_SMON0_RX_SLICE_1_RX_DIGITAL0 0x60407000 +#define RX_SMON1_RX_SLICE_1_RX_DIGITAL0 0x60408000 +#define RX_SMON0_RX_SLICE_0_RX_DIGITAL1 0x60A07000 +#define RX_SMON1_RX_SLICE_0_RX_DIGITAL1 0x60A08000 +#define RX_SMON0_RX_SLICE_1_RX_DIGITAL1 0x60C07000 +#define RX_SMON1_RX_SLICE_1_RX_DIGITAL1 0x60C08000 + +#define REG_SMON_CLK_EN_ADDR(inst) ((inst) + 0x00000000) +#define BF_SMON_SFRAMER_MODE_EN_INFO(inst) ((inst) + 0x00000000), 0x00000201 + +#define REG_SMON_STATUS_FCNT_ADDR(inst) ((inst) + 0x00000001) +#define BF_SMON_STATUS_FCNT_INFO(inst) ((inst) + 0x00000001), 0x00000800 + +#define REG_SMON_PERIOD0_ADDR(inst) ((inst) + 0x00000002) +#define BF_SMON_PERIOD_INFO(inst) ((inst) + 0x00000002), 0x00002000 + +#define REG_SMON_PERIOD1_ADDR(inst) ((inst) + 0x00000003) + +#define REG_SMON_PERIOD2_ADDR(inst) ((inst) + 0x00000004) + +#define REG_SMON_PERIOD3_ADDR(inst) ((inst) + 0x00000005) + +#define REG_SMON_STATUS_CTRL_ADDR(inst) ((inst) + 0x00000006) +#define BF_SMON_STATUS_UPDATE_INFO(inst) ((inst) + 0x00000006), 0x00000100 +#define BF_SMON_STATUS_RDSEL_INFO(inst) ((inst) + 0x00000006), 0x00000301 +#define BF_SMON_PEAK_EN_INFO(inst) ((inst) + 0x00000006), 0x00000104 +#define BF_SMON_JLINK_SEL_INFO(inst) ((inst) + 0x00000006), 0x00000105 +#define BF_SMON_GPIO_EN_INFO(inst) ((inst) + 0x00000006), 0x00000106 + +#define REG_SMON_FRAMER_ADDR(inst) ((inst) + 0x00000007) +#define BF_SMON_SFRAMER_EN_INFO(inst) ((inst) + 0x00000007), 0x00000100 +#define BF_SMON_SFRAMER_MODE_INFO(inst) ((inst) + 0x00000007), 0x00000101 +#define BF_SMON_SFRAMER_INSEL_INFO(inst) ((inst) + 0x00000007), 0x00000602 + +#define REG_SMON_SYNC_CTRL_ADDR(inst) ((inst) + 0x00000008) +#define BF_SMON_SYNC_EN_INFO(inst) ((inst) + 0x00000008), 0x00000100 +#define BF_SMON_SYNC_NEXT_INFO(inst) ((inst) + 0x00000008), 0x00000101 + +#define REG_SMON_STATUS_ADDR(inst, n) ((inst) + 0x00000009 + 1 * (n)) +#define BF_SMON_STATUS_INFO(inst, n) ((inst) + 0x00000009 + 1 * (n)), 0x00000800 + +#define REG_SMON_THRESH_LOW0_ADDR(inst) ((inst) + 0x0000000C) +#define BF_SMON_THRESH_LOW_INFO(inst) ((inst) + 0x0000000C), 0x00000B00 + +#define REG_SMON_THRESH_LOW1_ADDR(inst) ((inst) + 0x0000000D) + +#define REG_SMON_THRESH_HIGH0_ADDR(inst) ((inst) + 0x0000000E) +#define BF_SMON_THRESH_HIGH_INFO(inst) ((inst) + 0x0000000E), 0x00000B00 + +#define REG_SMON_THRESH_HIGH1_ADDR(inst) ((inst) + 0x0000000F) + +#endif /* __ADI_APOLLO_BF_RX_SMON_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_rx_spectrum_sniffer.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_rx_spectrum_sniffer.h new file mode 100644 index 00000000000000..1b4b853c7f4fa5 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_rx_spectrum_sniffer.h @@ -0,0 +1,90 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:19 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_RX_SPECTRUM_SNIFFER_H__ +#define __ADI_APOLLO_BF_RX_SPECTRUM_SNIFFER_H__ + +/*============= D E F I N E S ==============*/ +#define RX_SPECTRUM_SNIFFER_RX_SLICE_0_RX_DIGITAL0 0x60205000 +#define RX_SPECTRUM_SNIFFER_RX_SLICE_1_RX_DIGITAL0 0x60405000 +#define RX_SPECTRUM_SNIFFER_RX_SLICE_0_RX_DIGITAL1 0x60A05000 +#define RX_SPECTRUM_SNIFFER_RX_SLICE_1_RX_DIGITAL1 0x60C05000 + +#define REG_SPECTRUM_SNIFFER_CONTROL_1_ADDR(inst) ((inst) + 0x00000000) +#define BF_SPECTRUM_SNIFFER_EN_INFO(inst) ((inst) + 0x00000000), 0x00000100 +#define BF_FFT_ENABLE_INFO(inst) ((inst) + 0x00000000), 0x00000101 +#define BF_SORT_EN_INFO(inst) ((inst) + 0x00000000), 0x00000102 +#define BF_MAGNITUDE_IQ_N_INFO(inst) ((inst) + 0x00000000), 0x00000103 +#define BF_FORCE_SORT_STORE_INFO(inst) ((inst) + 0x00000000), 0x00000104 +#define BF_FFT_HOLD_INFO(inst) ((inst) + 0x00000000), 0x00000105 +#define BF_FFT_ENABLE_SEL_INFO(inst) ((inst) + 0x00000000), 0x00000106 +#define BF_FFT_HOLD_SEL_INFO(inst) ((inst) + 0x00000000), 0x00000107 + +#define REG_SPECTRUM_SNIFFER_CONTROL_2_ADDR(inst) ((inst) + 0x00000001) +#define BF_REAL_MODE_INFO(inst) ((inst) + 0x00000001), 0x00000100 +#define BF_CONTINUOUS_MODE_INFO(inst) ((inst) + 0x00000001), 0x00000101 +#define BF_BOTTOM_FFT_ENABLE_INFO(inst) ((inst) + 0x00000001), 0x00000102 +#define BF_WINDOW_ENABLE_INFO(inst) ((inst) + 0x00000001), 0x00000103 +#define BF_LOW_POWER_INFO(inst) ((inst) + 0x00000001), 0x00000104 +#define BF_DITHER_ENABLE_INFO(inst) ((inst) + 0x00000001), 0x00000105 + +#define REG_ALPHA_FACTOR_ADDR(inst) ((inst) + 0x00000002) +#define BF_ALPHA_FACTOR_INFO(inst) ((inst) + 0x00000002), 0x00000400 + +#define REG_MAX_THRESHOLD_ADDR(inst) ((inst) + 0x00000003) +#define BF_MAX_THRESHOLD_INFO(inst) ((inst) + 0x00000003), 0x00000800 + +#define REG_MIN_THRESHOLD_ADDR(inst) ((inst) + 0x00000004) +#define BF_MIN_THRESHOLD_INFO(inst) ((inst) + 0x00000004), 0x00000800 + +#define REG_SPECTRUM_SNIFFER_STATUS_ADDR(inst) ((inst) + 0x00000005) +#define BF_FFT_DONE_INFO(inst) ((inst) + 0x00000005), 0x00000100 +#define BF_DBG_MAG_OVERFLOW_INFO(inst) ((inst) + 0x00000005), 0x00000101 + +#define REG_MAGNITUDE_I_0_ADDR(inst, n) ((inst) + 0x00000006 + 4 * (n)) +#define BF_MAGNITUDE_I_INFO(inst, n) ((inst) + 0x00000006 + 4 * (n)), 0x00000900 + +#define REG_MAGNITUDE_I_1_ADDR(inst, n) ((inst) + 0x00000007 + 4 * (n)) + +#define REG_BIN_NUMBER_Q_0_ADDR(inst, n) ((inst) + 0x00000008 + 4 * (n)) +#define BF_BIN_NUMBER_Q_INFO(inst, n) ((inst) + 0x00000008 + 4 * (n)), 0x00000900 + +#define REG_BIN_NUMBER_Q_1_ADDR(inst, n) ((inst) + 0x00000009 + 4 * (n)) + +#define REG_MAX_THRESHOLD_BIN_ADDR(inst, n) ((inst) + 0x00000806 + 1 * (n)) +#define BF_MAX_THRESHOLD_BIN_INFO(inst, n) ((inst) + 0x00000806 + 1 * (n)), 0x00000800 + +#define REG_MIN_THRESHOLD_BIN_ADDR(inst, n) ((inst) + 0x00000846 + 1 * (n)) +#define BF_MIN_THRESHOLD_BIN_INFO(inst, n) ((inst) + 0x00000846 + 1 * (n)), 0x00000800 + +#ifdef USE_PRIVATE_BF +#define REG_BIST_CTRL_ADDR(inst) ((inst) + 0x00000886) +#define BF_BIST_EN_RX_SPECTRUM_SNIFFER_INFO(inst) ((inst) + 0x00000886), 0x00000100 +#define BF_BIST_INIT_INFO(inst) ((inst) + 0x00000886), 0x00000101 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_BIST_CRC_LSB_ADDR(inst) ((inst) + 0x00000887) +#define BF_BIST_CRC_INFO(inst) ((inst) + 0x00000887), 0x00001000 +#endif /* USE_PRIVATE_BF */ + +#define REG_BIST_CRC_MSB_ADDR(inst) ((inst) + 0x00000888) + +#ifdef USE_PRIVATE_BF +#define REG_BIST_STATUS_ADDR(inst) ((inst) + 0x00000889) +#define BF_BIST_EN_STATUS_INFO(inst) ((inst) + 0x00000889), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#endif /* __ADI_APOLLO_BF_RX_SPECTRUM_SNIFFER_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_semaphore.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_semaphore.h new file mode 100644 index 00000000000000..cde57ac17ba7a3 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_semaphore.h @@ -0,0 +1,120 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:17 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_SEMAPHORE_H__ +#define __ADI_APOLLO_BF_SEMAPHORE_H__ + +/*============= D E F I N E S ==============*/ +#define SEMAPHORE0 0x46500000 +#define SEMAPHORE1 0x46510000 +#define SEMAPHORE2 0x46520000 +#define SEMAPHORE3 0x46530000 +#define SEMAPHORE4 0x46540000 +#define SEMAPHORE5 0x46550000 +#define SEMAPHORE6 0x46560000 +#define SEMAPHORE7 0x46570000 +#define SEMAPHORE8 0x46580000 +#define SEMAPHORE9 0x46590000 +#define SEMAPHORE10 0x465A0000 +#define SEMAPHORE11 0x465B0000 +#define SEMAPHORE12 0x465C0000 +#define SEMAPHORE13 0x465D0000 +#define SEMAPHORE14 0x465E0000 +#define SEMAPHORE15 0x465F0000 +#define SEMAPHORE16 0x46600000 +#define SEMAPHORE17 0x46610000 +#define SEMAPHORE18 0x46620000 +#define SEMAPHORE19 0x46630000 +#define SEMAPHORE20 0x46640000 +#define SEMAPHORE21 0x46650000 +#define SEMAPHORE22 0x46660000 +#define SEMAPHORE23 0x46670000 +#define SEMAPHORE24 0x46680000 +#define SEMAPHORE25 0x46690000 +#define SEMAPHORE26 0x466A0000 +#define SEMAPHORE27 0x466B0000 +#define SEMAPHORE28 0x466C0000 +#define SEMAPHORE29 0x466D0000 +#define SEMAPHORE30 0x466E0000 +#define SEMAPHORE31 0x466F0000 +#define RX_SEMAPHORE0_RX_SLICE_0_RX_DIGITAL0 0x6037D000 +#define RX_SEMAPHORE1_RX_SLICE_0_RX_DIGITAL0 0x6037D100 +#define RX_SEMAPHORE2_RX_SLICE_0_RX_DIGITAL0 0x6037D200 +#define RX_SEMAPHORE3_RX_SLICE_0_RX_DIGITAL0 0x6037D300 +#define RX_SEMAPHORE4_RX_SLICE_0_RX_DIGITAL0 0x6037D400 +#define RX_SEMAPHORE5_RX_SLICE_0_RX_DIGITAL0 0x6037D500 +#define RX_SEMAPHORE6_RX_SLICE_0_RX_DIGITAL0 0x6037D600 +#define RX_SEMAPHORE7_RX_SLICE_0_RX_DIGITAL0 0x6037D700 +#define RX_SEMAPHORE0_RX_SLICE_1_RX_DIGITAL0 0x6057D000 +#define RX_SEMAPHORE1_RX_SLICE_1_RX_DIGITAL0 0x6057D100 +#define RX_SEMAPHORE2_RX_SLICE_1_RX_DIGITAL0 0x6057D200 +#define RX_SEMAPHORE3_RX_SLICE_1_RX_DIGITAL0 0x6057D300 +#define RX_SEMAPHORE4_RX_SLICE_1_RX_DIGITAL0 0x6057D400 +#define RX_SEMAPHORE5_RX_SLICE_1_RX_DIGITAL0 0x6057D500 +#define RX_SEMAPHORE6_RX_SLICE_1_RX_DIGITAL0 0x6057D600 +#define RX_SEMAPHORE7_RX_SLICE_1_RX_DIGITAL0 0x6057D700 +#define RX_SEMAPHORE0_RX_SLICE_0_RX_DIGITAL1 0x60B7D000 +#define RX_SEMAPHORE1_RX_SLICE_0_RX_DIGITAL1 0x60B7D100 +#define RX_SEMAPHORE2_RX_SLICE_0_RX_DIGITAL1 0x60B7D200 +#define RX_SEMAPHORE3_RX_SLICE_0_RX_DIGITAL1 0x60B7D300 +#define RX_SEMAPHORE4_RX_SLICE_0_RX_DIGITAL1 0x60B7D400 +#define RX_SEMAPHORE5_RX_SLICE_0_RX_DIGITAL1 0x60B7D500 +#define RX_SEMAPHORE6_RX_SLICE_0_RX_DIGITAL1 0x60B7D600 +#define RX_SEMAPHORE7_RX_SLICE_0_RX_DIGITAL1 0x60B7D700 +#define RX_SEMAPHORE0_RX_SLICE_1_RX_DIGITAL1 0x60D7D000 +#define RX_SEMAPHORE1_RX_SLICE_1_RX_DIGITAL1 0x60D7D100 +#define RX_SEMAPHORE2_RX_SLICE_1_RX_DIGITAL1 0x60D7D200 +#define RX_SEMAPHORE3_RX_SLICE_1_RX_DIGITAL1 0x60D7D300 +#define RX_SEMAPHORE4_RX_SLICE_1_RX_DIGITAL1 0x60D7D400 +#define RX_SEMAPHORE5_RX_SLICE_1_RX_DIGITAL1 0x60D7D500 +#define RX_SEMAPHORE6_RX_SLICE_1_RX_DIGITAL1 0x60D7D600 +#define RX_SEMAPHORE7_RX_SLICE_1_RX_DIGITAL1 0x60D7D700 +#define TX_SEMAPHORE0_TX_SLICE_0_TX_DIGITAL0 0x6133E000 +#define TX_SEMAPHORE1_TX_SLICE_0_TX_DIGITAL0 0x6133E100 +#define TX_SEMAPHORE2_TX_SLICE_0_TX_DIGITAL0 0x6133E200 +#define TX_SEMAPHORE3_TX_SLICE_0_TX_DIGITAL0 0x6133E300 +#define TX_SEMAPHORE4_TX_SLICE_0_TX_DIGITAL0 0x6133E400 +#define TX_SEMAPHORE5_TX_SLICE_0_TX_DIGITAL0 0x6133E500 +#define TX_SEMAPHORE6_TX_SLICE_0_TX_DIGITAL0 0x6133E600 +#define TX_SEMAPHORE7_TX_SLICE_0_TX_DIGITAL0 0x6133E700 +#define TX_SEMAPHORE0_TX_SLICE_1_TX_DIGITAL0 0x6153E000 +#define TX_SEMAPHORE1_TX_SLICE_1_TX_DIGITAL0 0x6153E100 +#define TX_SEMAPHORE2_TX_SLICE_1_TX_DIGITAL0 0x6153E200 +#define TX_SEMAPHORE3_TX_SLICE_1_TX_DIGITAL0 0x6153E300 +#define TX_SEMAPHORE4_TX_SLICE_1_TX_DIGITAL0 0x6153E400 +#define TX_SEMAPHORE5_TX_SLICE_1_TX_DIGITAL0 0x6153E500 +#define TX_SEMAPHORE6_TX_SLICE_1_TX_DIGITAL0 0x6153E600 +#define TX_SEMAPHORE7_TX_SLICE_1_TX_DIGITAL0 0x6153E700 +#define TX_SEMAPHORE0_TX_SLICE_0_TX_DIGITAL1 0x61B3E000 +#define TX_SEMAPHORE1_TX_SLICE_0_TX_DIGITAL1 0x61B3E100 +#define TX_SEMAPHORE2_TX_SLICE_0_TX_DIGITAL1 0x61B3E200 +#define TX_SEMAPHORE3_TX_SLICE_0_TX_DIGITAL1 0x61B3E300 +#define TX_SEMAPHORE4_TX_SLICE_0_TX_DIGITAL1 0x61B3E400 +#define TX_SEMAPHORE5_TX_SLICE_0_TX_DIGITAL1 0x61B3E500 +#define TX_SEMAPHORE6_TX_SLICE_0_TX_DIGITAL1 0x61B3E600 +#define TX_SEMAPHORE7_TX_SLICE_0_TX_DIGITAL1 0x61B3E700 +#define TX_SEMAPHORE0_TX_SLICE_1_TX_DIGITAL1 0x61D3E000 +#define TX_SEMAPHORE1_TX_SLICE_1_TX_DIGITAL1 0x61D3E100 +#define TX_SEMAPHORE2_TX_SLICE_1_TX_DIGITAL1 0x61D3E200 +#define TX_SEMAPHORE3_TX_SLICE_1_TX_DIGITAL1 0x61D3E300 +#define TX_SEMAPHORE4_TX_SLICE_1_TX_DIGITAL1 0x61D3E400 +#define TX_SEMAPHORE5_TX_SLICE_1_TX_DIGITAL1 0x61D3E500 +#define TX_SEMAPHORE6_TX_SLICE_1_TX_DIGITAL1 0x61D3E600 +#define TX_SEMAPHORE7_TX_SLICE_1_TX_DIGITAL1 0x61D3E700 + +#define REG_SEMAPHORE_ADDR(inst) ((inst) + 0x00000000) +#define BF_SEMAPHORE_INFO(inst) ((inst) + 0x00000000), 0x00002000 + +#endif /* __ADI_APOLLO_BF_SEMAPHORE_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_serdes_rxdig_12pack_core1p3.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_serdes_rxdig_12pack_core1p3.h new file mode 100644 index 00000000000000..9e24b124a61809 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_serdes_rxdig_12pack_core1p3.h @@ -0,0 +1,156 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:22 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_SERDES_RXDIG_12PACK_CORE1P3_H__ +#define __ADI_APOLLO_BF_SERDES_RXDIG_12PACK_CORE1P3_H__ + +/*============= D E F I N E S ==============*/ +#define DESER_PHY_TOP_12PACK_SERDES_RX_JRX_TX_DIGITAL0 0x61638000 +#define DESER_PHY_TOP_12PACK_SERDES_RX_JRX_TX_DIGITAL1 0x61E38000 + +#define REG_RXDES_12PACK_PD0_ADDR(inst) ((inst) + 0x00000000) +#define BF_RXDES_PD_CH_INFO(inst) ((inst) + 0x00000000), 0x00000C00 + +#define REG_RXDES_12PACK_PD1_ADDR(inst) ((inst) + 0x00000001) +#define BF_RXDES_PD_CLK_RCVR_INFO(inst) ((inst) + 0x00000001), 0x00000104 +#define BF_RXDES_PD_BIASDIST_INFO(inst) ((inst) + 0x00000001), 0x00000105 + +#define REG_RXDES_12PACK_TEST_CLK_CTL_ADDR(inst) ((inst) + 0x00000002) +#define BF_RXDES_TEST_CLK_SEL_INFO(inst) ((inst) + 0x00000002), 0x00000400 +#define BF_RXDES_TEST_CLK_EN_INFO(inst) ((inst) + 0x00000002), 0x00000104 +#define BF_RXDES_EN_DESER_TESTV_OUT_INFO(inst) ((inst) + 0x00000002), 0x00000105 +#define BF_RXDES_TEST_MUX_BANK_SEL_INFO(inst) ((inst) + 0x00000002), 0x00000106 + +#define REG_RXDES_12PACK_BIAS_CTL0_ADDR(inst) ((inst) + 0x00000003) +#define BF_CTRL_IBIAS_TFR_INFO(inst) ((inst) + 0x00000003), 0x00000300 +#define BF_CTRL_IBIAS_FIX_INFO(inst) ((inst) + 0x00000003), 0x00000304 + +#define REG_RXDES_12PACK_BIAS_CTL1_ADDR(inst) ((inst) + 0x00000004) +#define BF_CTRL_IBIAS_PTAT_INFO(inst) ((inst) + 0x00000004), 0x00000300 + +#define REG_RXDES_12PACK_RATE_CTL_ADDR(inst) ((inst) + 0x00000005) +#define BF_RXDES_QHFRATE_INFO(inst) ((inst) + 0x00000005), 0x00000200 +#define BF_RXDES_PARDATAMODE_INFO(inst) ((inst) + 0x00000005), 0x00000202 +#define BF_RXDES_DIVRATE_INFO(inst) ((inst) + 0x00000005), 0x00000304 + +#define REG_RXDES_12PACK_ERRBITS_ADDR(inst) ((inst) + 0x00000006) +#define BF_RXDES_EN_ERRBITS_INFO(inst) ((inst) + 0x00000006), 0x00000100 + +#define REG_RXDES_12PACK_SPARE_CTL_ADDR(inst) ((inst) + 0x00000007) +#define BF_SPARE_CTL_SERDES_RXDIG_12PACK__CORE1P3_INFO(inst) ((inst) + 0x00000007), 0x00000800 + +#define REG_RXDES_12PACK_SPARE_STA_ADDR(inst) ((inst) + 0x00000008) +#define BF_SPARE_STA_INFO(inst) ((inst) + 0x00000008), 0x00000800 + +#define REG_RXDES_12PACK_VARDCO_CTL_ADDR(inst) ((inst) + 0x00000010) +#define BF_RXDES_VARDCO_DIVN_INFO(inst) ((inst) + 0x00000010), 0x00000300 +#define BF_RXDES_VARDCO_EN_INFO(inst) ((inst) + 0x00000010), 0x00000103 + +#define REG_RXDES_12PACK_UC_CTL0_ADDR(inst) ((inst) + 0x00000011) +#define BF_RXDES_UC_EN_INFO(inst) ((inst) + 0x00000011), 0x00000100 +#define BF_RXDES_UC_RUN_INFO(inst) ((inst) + 0x00000011), 0x00000101 +#define BF_RXDES_UC_STEP_INFO(inst) ((inst) + 0x00000011), 0x00000102 +#define BF_RXDES_UC_BREAKPOINT_EN_INFO(inst) ((inst) + 0x00000011), 0x00000103 +#define BF_RXDES_UC_MEM_OVERRIDE_INFO(inst) ((inst) + 0x00000011), 0x00000104 +#define BF_RXDES_UC_SPI_OVERRIDE_INFO(inst) ((inst) + 0x00000011), 0x00000105 + +#define REG_RXDES_12PACK_UC_CTL1_ADDR(inst) ((inst) + 0x00000012) +#define BF_RXDES_UC_STACK_START_ADDR_INFO(inst) ((inst) + 0x00000012), 0x00000C00 + +#define REG_RXDES_12PACK_UC_CTL2_ADDR(inst) ((inst) + 0x00000013) + +#define REG_RXDES_12PACK_UC_CTL3_ADDR(inst) ((inst) + 0x00000014) +#define BF_RXDES_UC_BREAKPOINT_ADDR_INFO(inst) ((inst) + 0x00000014), 0x00000C00 + +#define REG_RXDES_12PACK_UC_CTL4_ADDR(inst) ((inst) + 0x00000015) + +#define REG_RXDES_12PACK_UC_CTL5_ADDR(inst) ((inst) + 0x00000016) +#define BF_RXDES_UC_PC_PTR_INFO(inst) ((inst) + 0x00000016), 0x00000C00 + +#define REG_RXDES_12PACK_UC_CTL6_ADDR(inst) ((inst) + 0x00000017) + +#define REG_RXDES_12PACK_PHY_UC_CTL0_ADDR(inst) ((inst) + 0x00000020) +#define BF_RXDES_LMS_EN_INFO(inst) ((inst) + 0x00000020), 0x00000C00 + +#define REG_RXDES_12PACK_PHY_UC_CTL1_ADDR(inst) ((inst) + 0x00000021) + +#define REG_RXDES_12PACK_PHY_UC_CTL2_ADDR(inst) ((inst) + 0x00000022) +#define BF_RXDES_LMS_DONE_INFO(inst) ((inst) + 0x00000022), 0x00000C00 + +#define REG_RXDES_12PACK_PHY_UC_CTL3_ADDR(inst) ((inst) + 0x00000023) + +#define REG_RXDES_12PACK_PHY_UC_CTL4_ADDR(inst) ((inst) + 0x00000024) +#define BF_RXDES_LMS_FREEZE_INFO(inst) ((inst) + 0x00000024), 0x00000C00 + +#define REG_RXDES_12PACK_PHY_UC_CTL5_ADDR(inst) ((inst) + 0x00000025) + +#define REG_RXDES_12PACK_PHY_UC_CTL6_ADDR(inst) ((inst) + 0x00000026) +#define BF_RXDES_LMS_STEP_INFO(inst) ((inst) + 0x00000026), 0x00000C00 + +#define REG_RXDES_12PACK_PHY_UC_CTL7_ADDR(inst) ((inst) + 0x00000027) + +#define REG_RXDES_12PACK_PHY_INTERRUPT_CTL0_ADDR(inst) ((inst) + 0x00000028) +#define BF_RXDES_LANE_INTERRUPT_MASK_INFO(inst) ((inst) + 0x00000028), 0x00000C00 + +#define REG_RXDES_12PACK_PHY_INTERRUPT_CTL1_ADDR(inst) ((inst) + 0x00000029) + +#define REG_RXDES_12PACK_PHY_INTERRUPT_CTL2_ADDR(inst) ((inst) + 0x0000002A) +#define BF_RXDES_LANE_INTERRUPT_INVERT_INFO(inst) ((inst) + 0x0000002A), 0x00000C00 + +#define REG_RXDES_12PACK_PHY_INTERRUPT_CTL3_ADDR(inst) ((inst) + 0x0000002B) + +#define REG_RXDES_12PACK_PHY_INTERRUPT_CTL4_ADDR(inst) ((inst) + 0x0000002C) +#define BF_RXDES_GLOBAL_INTERRUPT_AND_OR_INFO(inst) ((inst) + 0x0000002C), 0x00000100 +#define BF_RXDES_GLOBAL_INTERRUPT_INVERT_INFO(inst) ((inst) + 0x0000002C), 0x00000101 +#define BF_RXDES_LOCAL_INTERRUPT_MASK_INFO(inst) ((inst) + 0x0000002C), 0x00000104 +#define BF_RXDES_LOCAL_INTERRUPT_INVERT_INFO(inst) ((inst) + 0x0000002C), 0x00000105 + +#define REG_RXDES_12PACK_PHY_USR_CTL0_ADDR(inst) ((inst) + 0x00000030) +#define BF_RXDES_USR_CTL0_INFO(inst) ((inst) + 0x00000030), 0x00000800 + +#define REG_RXDES_12PACK_PHY_USR_CTL1_ADDR(inst) ((inst) + 0x00000031) +#define BF_RXDES_USR_CTL1_INFO(inst) ((inst) + 0x00000031), 0x00000800 + +#define REG_RXDES_12PACK_PHY_USR_CTL2_ADDR(inst) ((inst) + 0x00000032) +#define BF_RXDES_USR_CTL2_INFO(inst) ((inst) + 0x00000032), 0x00000800 + +#define REG_RXDES_12PACK_PHY_USR_CTL3_ADDR(inst) ((inst) + 0x00000033) +#define BF_RXDES_USR_CTL3_INFO(inst) ((inst) + 0x00000033), 0x00000800 + +#define REG_RXDES_12PACK_PHY_USR_CTL4_ADDR(inst) ((inst) + 0x00000034) +#define BF_RXDES_USR_CTL4_INFO(inst) ((inst) + 0x00000034), 0x00000800 + +#define REG_RXDES_12PACK_PHY_USR_CTL5_ADDR(inst) ((inst) + 0x00000035) +#define BF_RXDES_USR_CTL5_INFO(inst) ((inst) + 0x00000035), 0x00000800 + +#define REG_RXDES_12PACK_PHY_USR_CTL6_ADDR(inst) ((inst) + 0x00000036) +#define BF_RXDES_USR_CTL6_INFO(inst) ((inst) + 0x00000036), 0x00000800 + +#define REG_RXDES_12PACK_PHY_USR_CTL7_ADDR(inst) ((inst) + 0x00000037) +#define BF_RXDES_USR_CTL7_INFO(inst) ((inst) + 0x00000037), 0x00000800 + +#define REG_RXDES_12PACK_PHY_USR_CTL8_ADDR(inst) ((inst) + 0x00000038) +#define BF_RXDES_USR_CTL8_INFO(inst) ((inst) + 0x00000038), 0x00000800 + +#define REG_RXDES_12PACK_PHY_USR_CTL9_ADDR(inst) ((inst) + 0x00000039) +#define BF_RXDES_USR_STA0_INFO(inst) ((inst) + 0x00000039), 0x00000800 + +#define REG_RXDES_12PACK_PHY_USR_CTL10_ADDR(inst) ((inst) + 0x0000003A) +#define BF_RXDES_USR_STA1_INFO(inst) ((inst) + 0x0000003A), 0x00000800 + +#define REG_RXDES_12PACK_REVID_ADDR(inst) ((inst) + 0x000000FF) +#define BF_RXDES_12PACK_REVID_INFO(inst) ((inst) + 0x000000FF), 0x00000800 + +#endif /* __ADI_APOLLO_BF_SERDES_RXDIG_12PACK_CORE1P3_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_serdes_rxdig_phy_core1p2.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_serdes_rxdig_phy_core1p2.h new file mode 100644 index 00000000000000..bce70b52ab92da --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_serdes_rxdig_phy_core1p2.h @@ -0,0 +1,740 @@ +/*! + * \brief SPI Register Definition Header File, automatically generated by + * /nobackup/jbirnie/yoda_bb_workdir/yoda2h_v1.3.6 v1.3.6 at 4/21/2021 7:18:46 PM. + * + * \copyright copyright(c) 2018 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_SERDES_RXDIG_PHY_CORE1P2_H__ +#define __ADI_APOLLO_BF_SERDES_RXDIG_PHY_CORE1P2_H__ + +/*============= D E F I N E S ==============*/ +#define DESER_PHY0_SERDES_RX_JRX_TX_DIGITAL0 0x61630000 +#define DESER_PHY1_SERDES_RX_JRX_TX_DIGITAL0 0x61630800 +#define DESER_PHY2_SERDES_RX_JRX_TX_DIGITAL0 0x61631000 +#define DESER_PHY3_SERDES_RX_JRX_TX_DIGITAL0 0x61631800 +#define DESER_PHY4_SERDES_RX_JRX_TX_DIGITAL0 0x61632000 +#define DESER_PHY5_SERDES_RX_JRX_TX_DIGITAL0 0x61632800 +#define DESER_PHY6_SERDES_RX_JRX_TX_DIGITAL0 0x61633000 +#define DESER_PHY7_SERDES_RX_JRX_TX_DIGITAL0 0x61633800 +#define DESER_PHY8_SERDES_RX_JRX_TX_DIGITAL0 0x61634000 +#define DESER_PHY9_SERDES_RX_JRX_TX_DIGITAL0 0x61634800 +#define DESER_PHY10_SERDES_RX_JRX_TX_DIGITAL0 0x61635000 +#define DESER_PHY11_SERDES_RX_JRX_TX_DIGITAL0 0x61635800 +#define DESER_PHY_ALL_SERDES_RX_JRX_TX_DIGITAL0 0x61636000 +#define DESER_PHY0_SERDES_RX_JRX_TX_DIGITAL1 0x61E30000 +#define DESER_PHY1_SERDES_RX_JRX_TX_DIGITAL1 0x61E30800 +#define DESER_PHY2_SERDES_RX_JRX_TX_DIGITAL1 0x61E31000 +#define DESER_PHY3_SERDES_RX_JRX_TX_DIGITAL1 0x61E31800 +#define DESER_PHY4_SERDES_RX_JRX_TX_DIGITAL1 0x61E32000 +#define DESER_PHY5_SERDES_RX_JRX_TX_DIGITAL1 0x61E32800 +#define DESER_PHY6_SERDES_RX_JRX_TX_DIGITAL1 0x61E33000 +#define DESER_PHY7_SERDES_RX_JRX_TX_DIGITAL1 0x61E33800 +#define DESER_PHY8_SERDES_RX_JRX_TX_DIGITAL1 0x61E34000 +#define DESER_PHY9_SERDES_RX_JRX_TX_DIGITAL1 0x61E34800 +#define DESER_PHY10_SERDES_RX_JRX_TX_DIGITAL1 0x61E35000 +#define DESER_PHY11_SERDES_RX_JRX_TX_DIGITAL1 0x61E35800 +#define DESER_PHY_ALL_SERDES_RX_JRX_TX_DIGITAL1 0x61E36000 + +#define REG_SPI_INTFCONFA_ADDR(inst) ((inst) + 0x00000000) +#define BF_SOFTRESET_INFO(inst) ((inst) + 0x00000000), 0x00000100 + +#define REG_CAL_EN_ADDR(inst) ((inst) + 0x00000001) +#define BF_RFPLL_LOCKED_INFO(inst) ((inst) + 0x00000001), 0x00000100 +#define BF_AUTOCAL_EN_INFO(inst) ((inst) + 0x00000001), 0x00000104 + +#define REG_PD_REG_0_ADDR(inst) ((inst) + 0x00000002) +#define BF_CK_DIS_CKGATES_INFO(inst) ((inst) + 0x00000002), 0x00000100 +#define BF_RXDES_PD_MBIAS_INFO(inst) ((inst) + 0x00000002), 0x00000101 +#define BF_PD_CDR_D_DES_RC_INFO(inst) ((inst) + 0x00000002), 0x00000102 +#define BF_PD_CTLE_DES_RC_INFO(inst) ((inst) + 0x00000002), 0x00000103 +#define BF_CK_PD_PI_INFO(inst) ((inst) + 0x00000002), 0x00000104 +#define BF_CK_PD_PI_DUTYDAC_INFO(inst) ((inst) + 0x00000002), 0x00000105 + +#define REG_PD_REG_1_ADDR(inst) ((inst) + 0x00000003) +#define BF_AFE_PD_CAL_INFO(inst) ((inst) + 0x00000003), 0x00000100 +#define BF_AFE_PD_VCM_INFO(inst) ((inst) + 0x00000003), 0x00000101 +#define BF_CTLE_PD_ODAC_INFO(inst) ((inst) + 0x00000003), 0x00000102 + +#define REG_MBIAS_CTL_ADDR(inst) ((inst) + 0x00000004) +#define BF_RXDES_CTRL_MBIAS_INFO(inst) ((inst) + 0x00000004), 0x00000800 + +#define REG_CAL_ADDR(inst) ((inst) + 0x00000007) +#define BF_PHASESTATE_CAL_EN_INFO(inst) ((inst) + 0x00000007), 0x00000100 +#define BF_PHASESTATE_INFO(inst) ((inst) + 0x00000007), 0x00000104 + +#define REG_LF_DLL_ADDR(inst) ((inst) + 0x00000008) +#define BF_DLLSLEW_INFO(inst) ((inst) + 0x00000008), 0x00000200 + +#define REG_LF_DESER_ADDR(inst) ((inst) + 0x00000009) +#define BF_SYNC_DESER8TO32_INFO(inst) ((inst) + 0x00000009), 0x00000100 +#define BF_CLKDIV8_INV_DESER8TO32_INFO(inst) ((inst) + 0x00000009), 0x00000101 +#define BF_CLKDIV32_INV_DESER8TO32_INFO(inst) ((inst) + 0x00000009), 0x00000102 +#define BF_PHI_TEST_EN_INFO(inst) ((inst) + 0x00000009), 0x00000103 + +#define REG_PAR_DATA_CTL_ADDR(inst) ((inst) + 0x0000000A) +#define BF_PAR_DATA_INV_INFO(inst) ((inst) + 0x0000000A), 0x00000100 +#define BF_PAR_CLK_EDGE_INFO(inst) ((inst) + 0x0000000A), 0x00000101 + +#define REG_LF_PHI_RS0_ADDR(inst) ((inst) + 0x0000000B) +#define BF_LF_PHI_DES_RS_INFO(inst) ((inst) + 0x0000000B), 0x00000E00 + +#define REG_LF_PHI_RS1_ADDR(inst) ((inst) + 0x0000000C) + +#define REG_TEST_ADDR(inst) ((inst) + 0x0000000E) +#define BF_RXDES_AMUX_SEL_INFO(inst) ((inst) + 0x0000000E), 0x00000500 + +#define REG_JTAG_ADDR(inst) ((inst) + 0x0000000F) +#define BF_JTAG_DBG_CLK_INFO(inst) ((inst) + 0x0000000F), 0x00000200 +#define BF_JTAG_DBG_INIT_D_INFO(inst) ((inst) + 0x0000000F), 0x00000202 + +#define REG_CK_CTL0_ADDR(inst) ((inst) + 0x00000010) +#define BF_CK_IBSEL_INFO(inst) ((inst) + 0x00000010), 0x00000100 +#define BF_CK_QBSEL_INFO(inst) ((inst) + 0x00000010), 0x00000101 +#define BF_CK_PI_COMSENSEEN_INFO(inst) ((inst) + 0x00000010), 0x00000102 +#define BF_CK_ENSLEWMEAS_INFO(inst) ((inst) + 0x00000010), 0x00000103 +#define BF_CK_PI_DUTYDAC_MAG_INFO(inst) ((inst) + 0x00000010), 0x00000204 +#define BF_CK_PI_DUTYDAC_SGN_INFO(inst) ((inst) + 0x00000010), 0x00000106 + +#define REG_CK_CTL1_ADDR(inst) ((inst) + 0x00000011) +#define BF_CK_PI_PHI_INFO(inst) ((inst) + 0x00000011), 0x00000700 +#define BF_CK_PI_PHI_CLK_INV_INFO(inst) ((inst) + 0x00000011), 0x00000107 + +#define REG_CK_CTL2_ADDR(inst) ((inst) + 0x00000012) +#define BF_CK_PI_SLEWFS_INFO(inst) ((inst) + 0x00000012), 0x00000500 +#define BF_CK_PI_SLEWFS_FORCE_INFO(inst) ((inst) + 0x00000012), 0x00000105 +#define BF_CK_PI_SLEWFS_CAL_FBEN_FORCE_INFO(inst) ((inst) + 0x00000012), 0x00000106 + +#define REG_CK_CTL3_ADDR(inst) ((inst) + 0x00000013) +#define BF_CK_PI_FBEN_INFO(inst) ((inst) + 0x00000013), 0x00000400 +#define BF_CK_PI_SLEW_DFLIP_INFO(inst) ((inst) + 0x00000013), 0x00000104 +#define BF_CK_SLEWRATE_CKFLIP_INFO(inst) ((inst) + 0x00000013), 0x00000105 + +#define REG_CK_CTL4_ADDR(inst) ((inst) + 0x00000014) +#define BF_CK_SPO_ISTROBE_INFO(inst) ((inst) + 0x00000014), 0x00000100 +#define BF_CK_SPO_QSTROBE_INFO(inst) ((inst) + 0x00000014), 0x00000101 +#define BF_CK_SPO_UP_DN_INFO(inst) ((inst) + 0x00000014), 0x00000102 + +#define REG_CK_CTL5_ADDR(inst) ((inst) + 0x00000015) +#define BF_CK_PI_CAL_INIT_INFO(inst) ((inst) + 0x00000015), 0x00000100 +#define BF_CK_PI_COUNT_TOTAL_INFO(inst) ((inst) + 0x00000015), 0x00000301 +#define BF_CK_PI_COUNT_THR_DIFF_INFO(inst) ((inst) + 0x00000015), 0x00000404 + +#define REG_CK_CTL6_ADDR(inst) ((inst) + 0x00000016) +#define BF_CK_PI_DUTY_SEL_INFO(inst) ((inst) + 0x00000016), 0x00000300 +#define BF_CK_PI_REG_READ_INFO(inst) ((inst) + 0x00000016), 0x00000203 +#define BF_CK_PI_ROCLK_INFO(inst) ((inst) + 0x00000016), 0x00000105 +#define BF_CK_PI_ROCLK_BYPASS_INFO(inst) ((inst) + 0x00000016), 0x00000106 +#define BF_CK_PI_MEAS_INIT_INFO(inst) ((inst) + 0x00000016), 0x00000107 + +#define REG_CK_CTL7_ADDR(inst) ((inst) + 0x00000017) +#define BF_CK_PI_SLEWFS_OUT_INFO(inst) ((inst) + 0x00000017), 0x00000500 +#define BF_CK_PI_MEASIOUT_INFO(inst) ((inst) + 0x00000017), 0x00000105 +#define BF_CK_PI_MEASQOUT_INFO(inst) ((inst) + 0x00000017), 0x00000106 + +#define REG_CK_CTL8_ADDR(inst) ((inst) + 0x00000018) +#define BF_CK_PI_CAL_STATE_INFO(inst) ((inst) + 0x00000018), 0x00000400 +#define BF_CK_PI_CAL_DONE_INFO(inst) ((inst) + 0x00000018), 0x00000104 +#define BF_CK_PI_CAL_INPROGRESS_INFO(inst) ((inst) + 0x00000018), 0x00000105 +#define BF_CK_PI_MEAS_DONE_INFO(inst) ((inst) + 0x00000018), 0x00000106 +#define BF_CK_PI_MEAS_INPROGRESS_INFO(inst) ((inst) + 0x00000018), 0x00000107 + +#define REG_CK_CTL9_ADDR(inst) ((inst) + 0x00000019) +#define BF_CK_PI_COUNT_OUT_INFO(inst) ((inst) + 0x00000019), 0x00001000 + +#define REG_CK_CTL10_ADDR(inst) ((inst) + 0x0000001A) + +#define REG_CTLE_CTL0_ADDR(inst) ((inst) + 0x00000020) +#define BF_CTLE_STROBE_INFO(inst) ((inst) + 0x00000020), 0x00000100 +#define BF_AFE_CAL_STROBE_INFO(inst) ((inst) + 0x00000020), 0x00000101 +#define BF_AFE_CAL_STEP_INFO(inst) ((inst) + 0x00000020), 0x00000102 +#define BF_AFE_CAL_INIT_INFO(inst) ((inst) + 0x00000020), 0x00000104 +#define BF_FORCE_AFE_CAL_INFO(inst) ((inst) + 0x00000020), 0x00000105 +#define BF_FORCE_CTLE_REG_INFO(inst) ((inst) + 0x00000020), 0x00000106 +#define BF_CTLE_REG_OVERRIDE_INFO(inst) ((inst) + 0x00000020), 0x00000107 + +#define REG_CTLE_CTL1_ADDR(inst) ((inst) + 0x00000021) +#define BF_AFE_STATE_INFO(inst) ((inst) + 0x00000021), 0x00000500 +#define BF_AFE_CAL_DONE_INFO(inst) ((inst) + 0x00000021), 0x00000105 +#define BF_AFE_CAL_OUT_INFO(inst) ((inst) + 0x00000021), 0x00000106 + +#define REG_CTLE_CTL2_ADDR(inst) ((inst) + 0x00000022) +#define BF_CTLE_REG_DROPOUT_INFO(inst) ((inst) + 0x00000022), 0x00000500 +#define BF_CTLE_REG_CM_ADJUST_INFO(inst) ((inst) + 0x00000022), 0x00000305 + +#define REG_CTLE_CTL3_ADDR(inst) ((inst) + 0x00000023) +#define BF_CTLE_S1_GM_INFO(inst) ((inst) + 0x00000023), 0x00000500 + +#define REG_CTLE_CTL4_ADDR(inst) ((inst) + 0x00000024) +#define BF_CTLE_S1_LD_INFO(inst) ((inst) + 0x00000024), 0x00000400 +#define BF_CTLE_SQUELCH_INFO(inst) ((inst) + 0x00000024), 0x00000104 + +#define REG_CTLE_CTL5_ADDR(inst) ((inst) + 0x00000025) +#define BF_CTLE_S2_GM_INFO(inst) ((inst) + 0x00000025), 0x00000400 +#define BF_CTLE_S2_LD_INFO(inst) ((inst) + 0x00000025), 0x00000404 + +#define REG_CTLE_CTL6_ADDR(inst) ((inst) + 0x00000026) +#define BF_CTLE_S1_RP_INFO(inst) ((inst) + 0x00000026), 0x00000300 +#define BF_CTLE_S2_RP_INFO(inst) ((inst) + 0x00000026), 0x00000304 + +#define REG_CTLE_CTL7_ADDR(inst) ((inst) + 0x00000027) +#define BF_CTLE_PGA_LD_INFO(inst) ((inst) + 0x00000027), 0x00000800 + +#define REG_CTLE_CTL8_ADDR(inst) ((inst) + 0x00000028) +#define BF_CTLE_PGA_GM_INFO(inst) ((inst) + 0x00000028), 0x00001000 + +#define REG_CTLE_CTL9_ADDR(inst) ((inst) + 0x00000029) + +#define REG_CTLE_CTL10_ADDR(inst) ((inst) + 0x0000002A) +#define BF_CTLE_RSHUNT_EN_INFO(inst) ((inst) + 0x0000002A), 0x00000200 +#define BF_CTLE_RSHUNT_5K_EN_INFO(inst) ((inst) + 0x0000002A), 0x00000102 +#define BF_CTLE_RSER_EN_INFO(inst) ((inst) + 0x0000002A), 0x00000103 +#define BF_CTLE_REG_OVERRIDE_AMP_INFO(inst) ((inst) + 0x0000002A), 0x00000104 + +#define REG_CTLE_CTL11_ADDR(inst) ((inst) + 0x0000002B) +#define BF_CTLE_CSER_INFO(inst) ((inst) + 0x0000002B), 0x00000F00 + +#define REG_CTLE_CTL12_ADDR(inst) ((inst) + 0x0000002C) + +#define REG_CTLE_CTL13_ADDR(inst) ((inst) + 0x0000002D) +#define BF_CTLE_B_CTLE_ODAC_INFO(inst) ((inst) + 0x0000002D), 0x00000500 + +#define REG_CTLE_CTL14_ADDR(inst) ((inst) + 0x0000002E) +#define BF_CTLE_B_AFE_ODAC_INFO(inst) ((inst) + 0x0000002E), 0x00000500 + +#define REG_CTLE_CTL15_ADDR(inst) ((inst) + 0x0000002F) +#define BF_AFE_PROG_DLY_INFO(inst) ((inst) + 0x0000002F), 0x00000200 +#define BF_AFE_PROG_DROPOUT_MIN_INFO(inst) ((inst) + 0x0000002F), 0x00000202 +#define BF_AFE_PROG_DROPOUT_MAX_INFO(inst) ((inst) + 0x0000002F), 0x00000204 + +#define REG_CTLE_CTL16_ADDR(inst) ((inst) + 0x00000030) +#define BF_CTLE_REG_DROPOUT_SM_INFO(inst) ((inst) + 0x00000030), 0x00000500 + +#define REG_CTLE_CTL17_ADDR(inst) ((inst) + 0x00000031) +#define BF_CTLE_B_AFE_ODAC_SM_INFO(inst) ((inst) + 0x00000031), 0x00000500 + +#define REG_RAM_CTL0_ADDR(inst) ((inst) + 0x00000032) +#define BF_RAM_CEN_INFO(inst) ((inst) + 0x00000032), 0x00000104 +#define BF_RAM_WEN_INFO(inst) ((inst) + 0x00000032), 0x00000105 +#define BF_RAM_BYPASS_INFO(inst) ((inst) + 0x00000032), 0x00000106 + +#define REG_RAM_CTL1_ADDR(inst) ((inst) + 0x00000033) +#define BF_RAM_ADDR_INFO(inst) ((inst) + 0x00000033), 0x00000C00 + +#define REG_RAM_CTL2_ADDR(inst) ((inst) + 0x00000034) +#define BF_RAM_WDATA_INFO(inst) ((inst) + 0x00000034), 0x00001000 + +#define REG_RAM_CTL3_ADDR(inst) ((inst) + 0x00000035) + +#define REG_RAM_CTL4_ADDR(inst) ((inst) + 0x00000036) +#define BF_RAM_RDATA_INFO(inst) ((inst) + 0x00000036), 0x00001000 + +#define REG_RAM_CTL5_ADDR(inst) ((inst) + 0x00000037) + +#define REG_LMS_CTL0_ADDR(inst) ((inst) + 0x00000038) +#define BF_LMS_RESET_INFO(inst) ((inst) + 0x00000038), 0x00000100 +#define BF_LMS_BREAKPT_EN_INFO(inst) ((inst) + 0x00000038), 0x00000101 +#define BF_BOOTLOAD_EN_INFO(inst) ((inst) + 0x00000038), 0x00000104 +#define BF_BOOTLOAD_START_INFO(inst) ((inst) + 0x00000038), 0x00000105 + +#define REG_LMS_CTL1_ADDR(inst) ((inst) + 0x00000039) +#define BF_BOOTLOAD_ON_INFO(inst) ((inst) + 0x00000039), 0x00000104 +#define BF_BOOTLOAD_DONE_INFO(inst) ((inst) + 0x00000039), 0x00000105 + +#define REG_LMS_CTL2_ADDR(inst) ((inst) + 0x0000003A) +#define BF_LMS_NUM_ITER_INFO(inst) ((inst) + 0x0000003A), 0x00000800 + +#define REG_LMS_CTL3_ADDR(inst) ((inst) + 0x0000003B) +#define BF_LMS_FLASH_MSK_PRE_INFO(inst) ((inst) + 0x0000003B), 0x00000800 + +#define REG_LMS_CTL4_ADDR(inst) ((inst) + 0x0000003C) +#define BF_LMS_FLASH_MSK_POST_INFO(inst) ((inst) + 0x0000003C), 0x00000800 + +#define REG_LMS_CTL5_ADDR(inst) ((inst) + 0x0000003D) +#define BF_LMS_UPP_THRESH_INFO(inst) ((inst) + 0x0000003D), 0x00001000 + +#define REG_LMS_CTL6_ADDR(inst) ((inst) + 0x0000003E) + +#define REG_LMS_CTL7_ADDR(inst) ((inst) + 0x0000003F) +#define BF_LMS_BREAKPT_INFO(inst) ((inst) + 0x0000003F), 0x00000B00 + +#define REG_LMS_CTL8_ADDR(inst) ((inst) + 0x00000040) + +#define REG_LMS_CTL9_ADDR(inst) ((inst) + 0x00000041) +#define BF_LMS_CTL_FLAG_INFO(inst) ((inst) + 0x00000041), 0x00000800 + +#define REG_LMS_CTL10_ADDR(inst) ((inst) + 0x00000042) +#define BF_LMS_INNER_UP_STA_INFO(inst) ((inst) + 0x00000042), 0x00000700 + +#define REG_LMS_CTL11_ADDR(inst) ((inst) + 0x00000043) +#define BF_LMS_OUTER_UP_STA_INFO(inst) ((inst) + 0x00000043), 0x00000700 + +#define REG_LMS_CTL12_ADDR(inst) ((inst) + 0x00000044) +#define BF_LMS_INNER_DN_STA_INFO(inst) ((inst) + 0x00000044), 0x00000700 + +#define REG_LMS_CTL13_ADDR(inst) ((inst) + 0x00000045) +#define BF_LMS_OUTER_DN_STA_INFO(inst) ((inst) + 0x00000045), 0x00000700 + +#define REG_LMS_CTL14_ADDR(inst) ((inst) + 0x00000046) +#define BF_LMS_B2_STA_INFO(inst) ((inst) + 0x00000046), 0x00000600 + +#define REG_LMS_CTL15_ADDR(inst) ((inst) + 0x00000047) +#define BF_LMS_B3_STA_INFO(inst) ((inst) + 0x00000047), 0x00000600 + +#define REG_LMS_CTL16_ADDR(inst) ((inst) + 0x00000048) +#define BF_LMS_B4_STA_INFO(inst) ((inst) + 0x00000048), 0x00000500 + +#define REG_LMS_CTL17_ADDR(inst) ((inst) + 0x00000049) +#define BF_LMS_B5_STA_INFO(inst) ((inst) + 0x00000049), 0x00000500 + +#define REG_LMS_CTL18_ADDR(inst) ((inst) + 0x0000004A) +#define BF_LMS_B6_STA_INFO(inst) ((inst) + 0x0000004A), 0x00000500 + +#define REG_LMS_CTL19_ADDR(inst) ((inst) + 0x0000004B) +#define BF_LMS_DONE_INFO(inst) ((inst) + 0x0000004B), 0x00000800 + +#define REG_CTL_SPARE0_ADDR(inst) ((inst) + 0x00000050) +#define BF_CTL_SPARE0_INFO(inst) ((inst) + 0x00000050), 0x00000800 + +#define REG_CTL_SPARE1_ADDR(inst) ((inst) + 0x00000051) +#define BF_CTL_SPARE1_INFO(inst) ((inst) + 0x00000051), 0x00000800 + +#define REG_CTL_SPARE2_ADDR(inst) ((inst) + 0x00000052) +#define BF_CTL_SPARE2_INFO(inst) ((inst) + 0x00000052), 0x00000800 + +#define REG_CTL_SPARE3_ADDR(inst) ((inst) + 0x00000053) +#define BF_CTL_SPARE3_INFO(inst) ((inst) + 0x00000053), 0x00000800 + +#define REG_STATUS_SPARE0_ADDR(inst) ((inst) + 0x00000054) +#define BF_STATUS_SPARE0_INFO(inst) ((inst) + 0x00000054), 0x00000800 + +#define REG_STATUS_SPARE1_ADDR(inst) ((inst) + 0x00000055) +#define BF_STATUS_SPARE1_INFO(inst) ((inst) + 0x00000055), 0x00000800 + +#define REG_VARDCO_CTL_0_ADDR(inst) ((inst) + 0x00000058) +#define BF_VARDCO_LFSR_VALUE_INFO(inst) ((inst) + 0x00000058), 0x00000500 +#define BF_VARDCO_LFSR_BYPASS_INFO(inst) ((inst) + 0x00000058), 0x00000105 +#define BF_VARDCO_EN_INFO(inst) ((inst) + 0x00000058), 0x00000106 + +#define REG_VARDCO_CTL_1_ADDR(inst) ((inst) + 0x00000059) +#define BF_VARDCO_DIVN_INFO(inst) ((inst) + 0x00000059), 0x00000300 +#define BF_VARDCO_DIVM_INFO(inst) ((inst) + 0x00000059), 0x00000304 + +#define REG_PRBS_DEBUG_CTL0_ADDR(inst) ((inst) + 0x00000070) +#define BF_PRBS_RCV_EN_INFO(inst) ((inst) + 0x00000070), 0x00000100 +#define BF_PRBS_RCV_DATAREC_EN_INFO(inst) ((inst) + 0x00000070), 0x00000101 +#define BF_PRBS_RCV_DATAREC_MODE_INFO(inst) ((inst) + 0x00000070), 0x00000202 +#define BF_PRBS_RCV_DATAREC_CLR_INFO(inst) ((inst) + 0x00000070), 0x00000104 +#define BF_PRBS_RCV_AUTO_MODE_INFO(inst) ((inst) + 0x00000070), 0x00000105 + +#define REG_PRBS_DEBUG_CTL1_ADDR(inst) ((inst) + 0x00000071) +#define BF_PRBS_RCV_AUTO_MODE_THRESH_INFO(inst) ((inst) + 0x00000071), 0x00000600 + +#define REG_PRBS_DEBUG_STA0_ADDR(inst) ((inst) + 0x00000072) +#define BF_PRBS_RCV_ERR_INFO(inst) ((inst) + 0x00000072), 0x00000100 +#define BF_PRBS_RCV_ERR_STICKY_INFO(inst) ((inst) + 0x00000072), 0x00000101 +#define BF_PRBS_RCV_AUTO_MODE_DONE_INFO(inst) ((inst) + 0x00000072), 0x00000104 + +#define REG_PRBS_DEBUG_STA1_ADDR(inst) ((inst) + 0x00000073) +#define BF_PRBS_RCV_ERR_CNT_INFO(inst) ((inst) + 0x00000073), 0x00002000 + +#define REG_PRBS_DEBUG_STA2_ADDR(inst) ((inst) + 0x00000074) + +#define REG_PRBS_DEBUG_STA3_ADDR(inst) ((inst) + 0x00000075) + +#define REG_PRBS_DEBUG_STA4_ADDR(inst) ((inst) + 0x00000076) + +#define REG_DAT_DEBUG_CTL0_ADDR(inst) ((inst) + 0x00000077) +#define BF_CAPTURE_SAMPLE_INFO(inst) ((inst) + 0x00000077), 0x00000100 +#define BF_DMX_OUT_CLK_GATE_INFO(inst) ((inst) + 0x00000077), 0x00000101 + +#define REG_DAT_DEBUG_SAMPLE0_ADDR(inst) ((inst) + 0x00000078) +#define BF_SAMPLE_LATCHED_DATA_INFO(inst) ((inst) + 0x00000078), 0x00002000 + +#define REG_DAT_DEBUG_SAMPLE1_ADDR(inst) ((inst) + 0x00000079) + +#define REG_DAT_DEBUG_SAMPLE2_ADDR(inst) ((inst) + 0x0000007A) + +#define REG_DAT_DEBUG_SAMPLE3_ADDR(inst) ((inst) + 0x0000007B) + +#define REG_DAT_DEBUG_SAMPLE4_ADDR(inst) ((inst) + 0x0000007C) +#define BF_SAMPLE_LATCHED_ERR_INFO(inst) ((inst) + 0x0000007C), 0x00002000 + +#define REG_DAT_DEBUG_SAMPLE5_ADDR(inst) ((inst) + 0x0000007D) + +#define REG_DAT_DEBUG_SAMPLE6_ADDR(inst) ((inst) + 0x0000007E) + +#define REG_DAT_DEBUG_SAMPLE7_ADDR(inst) ((inst) + 0x0000007F) + +#define REG_CAL_CTL0_ADDR(inst) ((inst) + 0x00000080) +#define BF_CAL_ACC_EN_INFO(inst) ((inst) + 0x00000080), 0x00000101 +#define BF_CAL_ACC_TIMEOUT_EN_INFO(inst) ((inst) + 0x00000080), 0x00000102 +#define BF_CAL_ACC_INTERRUPT_EN_INFO(inst) ((inst) + 0x00000080), 0x00000103 +#define BF_CAL_ACC_EIN_SRC_INFO(inst) ((inst) + 0x00000080), 0x00000204 + +#define REG_CAL_CTL1_ADDR(inst) ((inst) + 0x00000081) +#define BF_CAL_DSHIFT0_INFO(inst) ((inst) + 0x00000081), 0x00000300 +#define BF_CAL_FUNC0_INFO(inst) ((inst) + 0x00000081), 0x00000304 + +#define REG_CAL_CTL2_ADDR(inst) ((inst) + 0x00000082) +#define BF_CAL_DSHIFT1_INFO(inst) ((inst) + 0x00000082), 0x00000300 +#define BF_CAL_FUNC1_INFO(inst) ((inst) + 0x00000082), 0x00000304 + +#define REG_CAL_CTL3_ADDR(inst) ((inst) + 0x00000083) +#define BF_CAL_DSHIFT2_INFO(inst) ((inst) + 0x00000083), 0x00000300 +#define BF_CAL_FUNC2_INFO(inst) ((inst) + 0x00000083), 0x00000304 + +#define REG_CAL_CTL4_ADDR(inst) ((inst) + 0x00000084) +#define BF_CAL_DSHIFT3_INFO(inst) ((inst) + 0x00000084), 0x00000300 +#define BF_CAL_FUNC3_INFO(inst) ((inst) + 0x00000084), 0x00000304 + +#define REG_CAL_CTL5_ADDR(inst) ((inst) + 0x00000085) +#define BF_CAL_MASK0_INFO(inst) ((inst) + 0x00000085), 0x00000800 + +#define REG_CAL_CTL6_ADDR(inst) ((inst) + 0x00000086) +#define BF_CAL_MASK1_INFO(inst) ((inst) + 0x00000086), 0x00000800 + +#define REG_CAL_CTL7_ADDR(inst) ((inst) + 0x00000087) +#define BF_CAL_MASK2_INFO(inst) ((inst) + 0x00000087), 0x00000800 + +#define REG_CAL_CTL8_ADDR(inst) ((inst) + 0x00000088) +#define BF_CAL_MASK3_INFO(inst) ((inst) + 0x00000088), 0x00000800 + +#define REG_CAL_CTL9_ADDR(inst) ((inst) + 0x00000089) +#define BF_CAL_QUAD0_INFO(inst) ((inst) + 0x00000089), 0x00000400 +#define BF_CAL_QUAD1_INFO(inst) ((inst) + 0x00000089), 0x00000404 + +#define REG_CAL_CTL10_ADDR(inst) ((inst) + 0x0000008A) +#define BF_CAL_QUAD2_INFO(inst) ((inst) + 0x0000008A), 0x00000400 +#define BF_CAL_QUAD3_INFO(inst) ((inst) + 0x0000008A), 0x00000404 + +#define REG_CAL_CTL11_ADDR(inst) ((inst) + 0x0000008B) +#define BF_CAL_COUNT_LIMIT_INFO(inst) ((inst) + 0x0000008B), 0x00001000 + +#define REG_CAL_CTL12_ADDR(inst) ((inst) + 0x0000008C) + +#define REG_CAL_CTL13_ADDR(inst) ((inst) + 0x0000008D) +#define BF_CAL_TIMEOUT_CNT_INFO(inst) ((inst) + 0x0000008D), 0x00001000 + +#define REG_CAL_CTL14_ADDR(inst) ((inst) + 0x0000008E) + +#define REG_CAL_CTL15_ADDR(inst) ((inst) + 0x0000008F) +#define BF_CAL_ACC_DONE_ALL_STA_INFO(inst) ((inst) + 0x0000008F), 0x00000100 +#define BF_CAL_ACC_TIMEOUT_STA_INFO(inst) ((inst) + 0x0000008F), 0x00000101 +#define BF_CAL_ACC_INTERRUPT_INFO(inst) ((inst) + 0x0000008F), 0x00000102 + +#define REG_CAL_CTL16_ADDR(inst) ((inst) + 0x00000090) +#define BF_CAL_ACC_STA0_INFO(inst) ((inst) + 0x00000090), 0x00001000 + +#define REG_CAL_CTL17_ADDR(inst) ((inst) + 0x00000091) + +#define REG_CAL_CTL18_ADDR(inst) ((inst) + 0x00000092) +#define BF_CAL_ACC_STA1_INFO(inst) ((inst) + 0x00000092), 0x00001000 + +#define REG_CAL_CTL19_ADDR(inst) ((inst) + 0x00000093) + +#define REG_CAL_CTL20_ADDR(inst) ((inst) + 0x00000094) +#define BF_CAL_ACC_STA2_INFO(inst) ((inst) + 0x00000094), 0x00001000 + +#define REG_CAL_CTL21_ADDR(inst) ((inst) + 0x00000095) + +#define REG_CAL_CTL22_ADDR(inst) ((inst) + 0x00000096) +#define BF_CAL_ACC_STA3_INFO(inst) ((inst) + 0x00000096), 0x00001000 + +#define REG_CAL_CTL23_ADDR(inst) ((inst) + 0x00000097) + +#define REG_CAL_CTL24_ADDR(inst) ((inst) + 0x00000098) +#define BF_CAL_CNT_STA0_INFO(inst) ((inst) + 0x00000098), 0x00001000 + +#define REG_CAL_CTL25_ADDR(inst) ((inst) + 0x00000099) + +#define REG_CAL_CTL26_ADDR(inst) ((inst) + 0x0000009A) +#define BF_CAL_CNT_STA1_INFO(inst) ((inst) + 0x0000009A), 0x00001000 + +#define REG_CAL_CTL27_ADDR(inst) ((inst) + 0x0000009B) + +#define REG_CAL_CTL28_ADDR(inst) ((inst) + 0x0000009C) +#define BF_CAL_CNT_STA2_INFO(inst) ((inst) + 0x0000009C), 0x00001000 + +#define REG_CAL_CTL29_ADDR(inst) ((inst) + 0x0000009D) + +#define REG_CAL_CTL30_ADDR(inst) ((inst) + 0x0000009E) +#define BF_CAL_CNT_STA3_INFO(inst) ((inst) + 0x0000009E), 0x00001000 + +#define REG_CAL_CTL31_ADDR(inst) ((inst) + 0x0000009F) + +#define REG_CAL_CTL32_ADDR(inst) ((inst) + 0x000000A0) +#define BF_CAL_LCNT_STA_INFO(inst) ((inst) + 0x000000A0), 0x00001000 + +#define REG_CAL_CTL33_ADDR(inst) ((inst) + 0x000000A1) + +#define REG_DCMEASURE_CTL0_ADDR(inst) ((inst) + 0x000000A8) +#define BF_DCMEASURE_CAL_EN_INFO(inst) ((inst) + 0x000000A8), 0x00000100 +#define BF_DCMEASURE_LD_INFO(inst) ((inst) + 0x000000A8), 0x00000101 +#define BF_DCMEASURE_HOLD_INFO(inst) ((inst) + 0x000000A8), 0x00000102 +#define BF_DCMEASURE_POL_INFO(inst) ((inst) + 0x000000A8), 0x00000103 +#define BF_DCD_DAC_DC_CNT_RDBK_HOLD_RC_INFO(inst) ((inst) + 0x000000A8), 0x00000104 + +#define REG_DCMEASURE_CTL1_ADDR(inst) ((inst) + 0x000000A9) +#define BF_DCMEASURE_CTLE_B_CTLE_ODAC_INFO(inst) ((inst) + 0x000000A9), 0x00000500 + +#define REG_DCD_DAC_DCUP_CNT_RDBK_0_ADDR(inst) ((inst) + 0x000000AA) +#define BF_DCD_DAC_DCUP_CNT_RDBK_RS_INFO(inst) ((inst) + 0x000000AA), 0x00000B00 + +#define REG_DCD_DAC_DCUP_CNT_RDBK_1_ADDR(inst) ((inst) + 0x000000AB) + +#define REG_DCD_DAC_DCDN_CNT_RDBK_0_ADDR(inst) ((inst) + 0x000000AC) +#define BF_DCD_DAC_DCDN_CNT_RDBK_RS_INFO(inst) ((inst) + 0x000000AC), 0x00000B00 + +#define REG_DCD_DAC_DCDN_CNT_RDBK_1_ADDR(inst) ((inst) + 0x000000AD) + +#define REG_DCD_DAC_HYSTERESIS_ADDR(inst) ((inst) + 0x000000AE) +#define BF_DCD_DAC_HYSTERESIS_CODE_RC_INFO(inst) ((inst) + 0x000000AE), 0x00000800 + +#define REG_EYEMON_CTL0_ADDR(inst) ((inst) + 0x000000B0) +#define BF_EYEMON_EN_INFO(inst) ((inst) + 0x000000B0), 0x00000100 +#define BF_EYEMON_START_INFO(inst) ((inst) + 0x000000B0), 0x00000101 +#define BF_EYEMON_MEAS_EN_INFO(inst) ((inst) + 0x000000B0), 0x00000104 + +#define REG_EYEMON_CTL1_ADDR(inst) ((inst) + 0x000000B1) +#define BF_EYEMON_THRESH_INFO(inst) ((inst) + 0x000000B1), 0x00000800 + +#define REG_EYEMON_STATUS0_ADDR(inst) ((inst) + 0x000000B2) +#define BF_EYEMON_STATE_INFO(inst) ((inst) + 0x000000B2), 0x00000600 + +#define REG_EYEMON_STATUS1_ADDR(inst) ((inst) + 0x000000B3) +#define BF_EYEMON_SPOI_CNT_INFO(inst) ((inst) + 0x000000B3), 0x00000500 + +#define REG_EYEMON_STATUS2_ADDR(inst) ((inst) + 0x000000B4) +#define BF_EYEMON_SPOQ_CNT_INFO(inst) ((inst) + 0x000000B4), 0x00000500 + +#define REG_EYEMON_STATUS3_ADDR(inst) ((inst) + 0x000000B5) +#define BF_EYEMON_SPOG_MEAS_INFO(inst) ((inst) + 0x000000B5), 0x00001000 + +#define REG_EYEMON_STATUS4_ADDR(inst) ((inst) + 0x000000B6) + +#define REG_EYEMON_STATUS5_ADDR(inst) ((inst) + 0x000000B7) +#define BF_EYEMON_SPOI_MEAS_INFO(inst) ((inst) + 0x000000B7), 0x00001000 + +#define REG_EYEMON_STATUS6_ADDR(inst) ((inst) + 0x000000B8) + +#define REG_EYEMON_STATUS7_ADDR(inst) ((inst) + 0x000000B9) +#define BF_EYEMON_SPOQ_MEAS_INFO(inst) ((inst) + 0x000000B9), 0x00001000 + +#define REG_EYEMON_STATUS8_ADDR(inst) ((inst) + 0x000000BA) + +#define REG_DFE_CTL0_ADDR(inst) ((inst) + 0x000000C0) +#define BF_S0_PD_IFB2_INFO(inst) ((inst) + 0x000000C0), 0x00000100 +#define BF_S0_PD_IFB3_INFO(inst) ((inst) + 0x000000C0), 0x00000101 +#define BF_S1_PD_IFB2_INFO(inst) ((inst) + 0x000000C0), 0x00000102 +#define BF_S1_PD_IFB3_INFO(inst) ((inst) + 0x000000C0), 0x00000103 + +#define REG_DFE_CTL1_ADDR(inst) ((inst) + 0x000000C1) +#define BF_FORCE_E_S0F0_INFO(inst) ((inst) + 0x000000C1), 0x00000400 +#define BF_FORCE_E_S0F1_INFO(inst) ((inst) + 0x000000C1), 0x00000404 + +#define REG_DFE_CTL2_ADDR(inst) ((inst) + 0x000000C2) +#define BF_FORCE_E_S1F0_INFO(inst) ((inst) + 0x000000C2), 0x00000400 +#define BF_FORCE_E_S1F1_INFO(inst) ((inst) + 0x000000C2), 0x00000404 + +#define REG_DFE_CTL3_ADDR(inst) ((inst) + 0x000000C3) +#define BF_S0_B_FB2_INFO(inst) ((inst) + 0x000000C3), 0x00000600 + +#define REG_DFE_CTL4_ADDR(inst) ((inst) + 0x000000C4) +#define BF_S0_B_FB3_INFO(inst) ((inst) + 0x000000C4), 0x00000600 + +#define REG_DFE_CTL5_ADDR(inst) ((inst) + 0x000000C5) +#define BF_S1_B_FB2_INFO(inst) ((inst) + 0x000000C5), 0x00000600 + +#define REG_DFE_CTL6_ADDR(inst) ((inst) + 0x000000C6) +#define BF_S1_B_FB3_INFO(inst) ((inst) + 0x000000C6), 0x00000600 + +#define REG_DFE_CTL7_ADDR(inst) ((inst) + 0x000000C7) +#define BF_DFE_CM_GMSW_INFO(inst) ((inst) + 0x000000C7), 0x00000500 +#define BF_DFE_CM_GMSW_OVRD_INFO(inst) ((inst) + 0x000000C7), 0x00000105 +#define BF_DFE_GMSW_CAP_DEL_INFO(inst) ((inst) + 0x000000C7), 0x00000106 + +#define REG_DFE_CTL8_ADDR(inst) ((inst) + 0x000000C8) +#define BF_S0_USESKEW_INFO(inst) ((inst) + 0x000000C8), 0x00000600 + +#define REG_DFE_CTL9_ADDR(inst) ((inst) + 0x000000C9) +#define BF_S1_USESKEW_INFO(inst) ((inst) + 0x000000C9), 0x00000600 + +#define REG_DFE_CTL10_ADDR(inst) ((inst) + 0x000000CA) +#define BF_S0_B_THRB1_INFO(inst) ((inst) + 0x000000CA), 0x00000700 + +#define REG_DFE_CTL11_ADDR(inst) ((inst) + 0x000000CB) +#define BF_S0_B_THRC20_INFO(inst) ((inst) + 0x000000CB), 0x00000700 + +#define REG_DFE_CTL12_ADDR(inst) ((inst) + 0x000000CC) +#define BF_S0_B_THRC21_INFO(inst) ((inst) + 0x000000CC), 0x00000700 + +#define REG_DFE_CTL13_ADDR(inst) ((inst) + 0x000000CD) +#define BF_S1_B_THRB1_INFO(inst) ((inst) + 0x000000CD), 0x00000700 + +#define REG_DFE_CTL14_ADDR(inst) ((inst) + 0x000000CE) +#define BF_S1_B_THRC20_INFO(inst) ((inst) + 0x000000CE), 0x00000700 + +#define REG_DFE_CTL15_ADDR(inst) ((inst) + 0x000000CF) +#define BF_S1_B_THRC21_INFO(inst) ((inst) + 0x000000CF), 0x00000700 + +#define REG_DFE_CTL16_ADDR(inst) ((inst) + 0x000000D0) +#define BF_S0_GM_SWITCH_OFF_VIP_INFO(inst) ((inst) + 0x000000D0), 0x00000500 + +#define REG_DFE_CTL17_ADDR(inst) ((inst) + 0x000000D1) +#define BF_S0_GM_SWITCH_OFF_VIN_INFO(inst) ((inst) + 0x000000D1), 0x00000500 + +#define REG_DFE_CTL18_ADDR(inst) ((inst) + 0x000000D2) +#define BF_S0_PD_CLKGEN_INFO(inst) ((inst) + 0x000000D2), 0x00000100 +#define BF_S0_PD_DAC_THR_INFO(inst) ((inst) + 0x000000D2), 0x00000303 +#define BF_S0_MUX_EN_OVRD_INFO(inst) ((inst) + 0x000000D2), 0x00000206 + +#define REG_DFE_CTL19_ADDR(inst) ((inst) + 0x000000D3) +#define BF_S0_PD_DAC_OFF_INFO(inst) ((inst) + 0x000000D3), 0x00000800 + +#define REG_DFE_CTL20_ADDR(inst) ((inst) + 0x000000D4) +#define BF_S0_B_F0I0_INFO(inst) ((inst) + 0x000000D4), 0x00000500 + +#define REG_DFE_CTL21_ADDR(inst) ((inst) + 0x000000D5) +#define BF_S0_B_F0I1_INFO(inst) ((inst) + 0x000000D5), 0x00000500 + +#define REG_DFE_CTL22_ADDR(inst) ((inst) + 0x000000D6) +#define BF_S0_B_F0I2_INFO(inst) ((inst) + 0x000000D6), 0x00000500 + +#define REG_DFE_CTL23_ADDR(inst) ((inst) + 0x000000D7) +#define BF_S0_B_F0I3_INFO(inst) ((inst) + 0x000000D7), 0x00000500 + +#define REG_DFE_CTL24_ADDR(inst) ((inst) + 0x000000D8) +#define BF_S0_B_F1I0_INFO(inst) ((inst) + 0x000000D8), 0x00000500 + +#define REG_DFE_CTL25_ADDR(inst) ((inst) + 0x000000D9) +#define BF_S0_B_F1I1_INFO(inst) ((inst) + 0x000000D9), 0x00000500 + +#define REG_DFE_CTL26_ADDR(inst) ((inst) + 0x000000DA) +#define BF_S0_B_F1I2_INFO(inst) ((inst) + 0x000000DA), 0x00000500 + +#define REG_DFE_CTL27_ADDR(inst) ((inst) + 0x000000DB) +#define BF_S0_B_F1I3_INFO(inst) ((inst) + 0x000000DB), 0x00000500 + +#define REG_DFE_CTL28_ADDR(inst) ((inst) + 0x000000DC) +#define BF_S0_PD_COMP_F0_INFO(inst) ((inst) + 0x000000DC), 0x00000400 +#define BF_S0_PD_COMP_F1_INFO(inst) ((inst) + 0x000000DC), 0x00000404 + +#define REG_DFE_CTL28X_ADDR(inst) ((inst) + 0x000000DD) +#define BF_S0_USE_COMP23_DATA_INFO(inst) ((inst) + 0x000000DD), 0x00000100 + +#define REG_DFE_CTL29_ADDR(inst) ((inst) + 0x000000E0) +#define BF_S1_GM_SWITCH_OFF_VIP_INFO(inst) ((inst) + 0x000000E0), 0x00000500 + +#define REG_DFE_CTL30_ADDR(inst) ((inst) + 0x000000E1) +#define BF_S1_GM_SWITCH_OFF_VIN_INFO(inst) ((inst) + 0x000000E1), 0x00000500 + +#define REG_DFE_CTL31_ADDR(inst) ((inst) + 0x000000E2) +#define BF_S1_PD_CLKGEN_INFO(inst) ((inst) + 0x000000E2), 0x00000100 +#define BF_S1_PD_DAC_THR_INFO(inst) ((inst) + 0x000000E2), 0x00000303 +#define BF_S1_MUX_EN_OVRD_INFO(inst) ((inst) + 0x000000E2), 0x00000206 + +#define REG_DFE_CTL32_ADDR(inst) ((inst) + 0x000000E3) +#define BF_S1_PD_DAC_OFF_INFO(inst) ((inst) + 0x000000E3), 0x00000800 + +#define REG_DFE_CTL33_ADDR(inst) ((inst) + 0x000000E4) +#define BF_S1_B_F0I0_INFO(inst) ((inst) + 0x000000E4), 0x00000500 + +#define REG_DFE_CTL34_ADDR(inst) ((inst) + 0x000000E5) +#define BF_S1_B_F0I1_INFO(inst) ((inst) + 0x000000E5), 0x00000500 + +#define REG_DFE_CTL35_ADDR(inst) ((inst) + 0x000000E6) +#define BF_S1_B_F0I2_INFO(inst) ((inst) + 0x000000E6), 0x00000500 + +#define REG_DFE_CTL36_ADDR(inst) ((inst) + 0x000000E7) +#define BF_S1_B_F0I3_INFO(inst) ((inst) + 0x000000E7), 0x00000500 + +#define REG_DFE_CTL37_ADDR(inst) ((inst) + 0x000000E8) +#define BF_S1_B_F1I0_INFO(inst) ((inst) + 0x000000E8), 0x00000500 + +#define REG_DFE_CTL38_ADDR(inst) ((inst) + 0x000000E9) +#define BF_S1_B_F1I1_INFO(inst) ((inst) + 0x000000E9), 0x00000500 + +#define REG_DFE_CTL39_ADDR(inst) ((inst) + 0x000000EA) +#define BF_S1_B_F1I2_INFO(inst) ((inst) + 0x000000EA), 0x00000500 + +#define REG_DFE_CTL40_ADDR(inst) ((inst) + 0x000000EB) +#define BF_S1_B_F1I3_INFO(inst) ((inst) + 0x000000EB), 0x00000500 + +#define REG_DFE_CTL41_ADDR(inst) ((inst) + 0x000000EC) +#define BF_S1_PD_COMP_F0_INFO(inst) ((inst) + 0x000000EC), 0x00000400 +#define BF_S1_PD_COMP_F1_INFO(inst) ((inst) + 0x000000EC), 0x00000404 + +#define REG_DFE_CTL41X_ADDR(inst) ((inst) + 0x000000ED) +#define BF_S1_USE_COMP23_DATA_INFO(inst) ((inst) + 0x000000ED), 0x00000100 + +#define REG_DFE_CTL42_ADDR(inst) ((inst) + 0x000000EE) +#define BF_DFE_FB_SUM_INFO(inst) ((inst) + 0x000000EE), 0x00000500 +#define BF_DFE_FB_SUM_OVRD_INFO(inst) ((inst) + 0x000000EE), 0x00000105 + +#define REG_DFE_CTL43_ADDR(inst) ((inst) + 0x000000EF) +#define BF_S0_B_FB4_INFO(inst) ((inst) + 0x000000EF), 0x00000500 +#define BF_S0_PD_FB456_INFO(inst) ((inst) + 0x000000EF), 0x00000107 + +#define REG_DFE_CTL44_ADDR(inst) ((inst) + 0x000000F0) +#define BF_S0_B_FB5_INFO(inst) ((inst) + 0x000000F0), 0x00000500 + +#define REG_DFE_CTL44X_ADDR(inst) ((inst) + 0x000000F1) +#define BF_S0_B_FB6_INFO(inst) ((inst) + 0x000000F1), 0x00000500 + +#define REG_DFE_CTL45_ADDR(inst) ((inst) + 0x000000F2) +#define BF_S1_B_FB4_INFO(inst) ((inst) + 0x000000F2), 0x00000500 +#define BF_S1_PD_FB456_INFO(inst) ((inst) + 0x000000F2), 0x00000107 + +#define REG_DFE_CTL46_ADDR(inst) ((inst) + 0x000000F3) +#define BF_S1_B_FB5_INFO(inst) ((inst) + 0x000000F3), 0x00000500 + +#define REG_DFE_CTL46X_ADDR(inst) ((inst) + 0x000000F4) +#define BF_S1_B_FB6_INFO(inst) ((inst) + 0x000000F4), 0x00000500 + +#define REG_DFE_CTL47_ADDR(inst) ((inst) + 0x000000F5) +#define BF_DFE_STROBE_INFO(inst) ((inst) + 0x000000F5), 0x00000100 + +#define REG_DFE_CTL48_ADDR(inst) ((inst) + 0x000000F6) +#define BF_RSELU_INFO(inst) ((inst) + 0x000000F6), 0x00000300 +#define BF_RSELU_BYPASS_INFO(inst) ((inst) + 0x000000F6), 0x00000103 + +#define REG_DFE_CTL49_ADDR(inst) ((inst) + 0x000000F7) +#define BF_CLKGEN_PD_VAL_SEL_INFO(inst) ((inst) + 0x000000F7), 0x00000200 +#define BF_PD_VCM_INFO(inst) ((inst) + 0x000000F7), 0x00000102 + +#define REG_DFE_CTL50_ADDR(inst) ((inst) + 0x000000F8) +#define BF_S1_DMX_SWP_DIV2_INFO(inst) ((inst) + 0x000000F8), 0x00000100 + +#define REG_DFE_CTL51_ADDR(inst) ((inst) + 0x000000F9) +#define BF_RHO_INFO(inst) ((inst) + 0x000000F9), 0x00000800 + +#define REG_DFE_CTL52_ADDR(inst) ((inst) + 0x000000FA) +#define BF_EN_FLASH_SRC_DES_RC_INFO(inst) ((inst) + 0x000000FA), 0x00000400 +#define BF_EN_FLASH_MASK_DES_RC_INFO(inst) ((inst) + 0x000000FA), 0x00000404 + +#define REG_DFE_CTL53_ADDR(inst) ((inst) + 0x000000FB) +#define BF_PROG_NMAK_REFDAC_INFO(inst) ((inst) + 0x000000FB), 0x00000200 +#define BF_PROG_NMAK_PDAC_INFO(inst) ((inst) + 0x000000FB), 0x00000202 + +#define REG_DFE_CTL54_ADDR(inst) ((inst) + 0x000000FC) +#define BF_S0_PD_GMSW_INFO(inst) ((inst) + 0x000000FC), 0x00000100 +#define BF_S0_SHORT_GMSW_INFO(inst) ((inst) + 0x000000FC), 0x00000101 +#define BF_S1_PD_GMSW_INFO(inst) ((inst) + 0x000000FC), 0x00000102 +#define BF_S1_SHORT_GMSW_INFO(inst) ((inst) + 0x000000FC), 0x00000103 + +#define REG_DIG_REVID_ADDR(inst) ((inst) + 0x000000FE) +#define BF_RX_DIG_REVID_INFO(inst) ((inst) + 0x000000FE), 0x00000800 + +#define REG_ANA_REVID_ADDR(inst) ((inst) + 0x000000FF) +#define BF_RX_ANA_REVID_INFO(inst) ((inst) + 0x000000FF), 0x00000800 + +#endif /* __ADI_APOLLO_BF_SERDES_RXDIG_PHY_CORE1P2_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_serdes_rxdig_phy_core1p3.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_serdes_rxdig_phy_core1p3.h new file mode 100644 index 00000000000000..ced485da2dfe79 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_serdes_rxdig_phy_core1p3.h @@ -0,0 +1,805 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:21 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_SERDES_RXDIG_PHY_CORE1P3_H__ +#define __ADI_APOLLO_BF_SERDES_RXDIG_PHY_CORE1P3_H__ + +/*============= D E F I N E S ==============*/ +#define DESER_PHY0_SERDES_RX_JRX_TX_DIGITAL0 0x61630000 +#define DESER_PHY1_SERDES_RX_JRX_TX_DIGITAL0 0x61630800 +#define DESER_PHY2_SERDES_RX_JRX_TX_DIGITAL0 0x61631000 +#define DESER_PHY3_SERDES_RX_JRX_TX_DIGITAL0 0x61631800 +#define DESER_PHY4_SERDES_RX_JRX_TX_DIGITAL0 0x61632000 +#define DESER_PHY5_SERDES_RX_JRX_TX_DIGITAL0 0x61632800 +#define DESER_PHY6_SERDES_RX_JRX_TX_DIGITAL0 0x61633000 +#define DESER_PHY7_SERDES_RX_JRX_TX_DIGITAL0 0x61633800 +#define DESER_PHY8_SERDES_RX_JRX_TX_DIGITAL0 0x61634000 +#define DESER_PHY9_SERDES_RX_JRX_TX_DIGITAL0 0x61634800 +#define DESER_PHY10_SERDES_RX_JRX_TX_DIGITAL0 0x61635000 +#define DESER_PHY11_SERDES_RX_JRX_TX_DIGITAL0 0x61635800 +#define DESER_PHY_ALL_SERDES_RX_JRX_TX_DIGITAL0 0x61636000 +#define DESER_PHY0_SERDES_RX_JRX_TX_DIGITAL1 0x61E30000 +#define DESER_PHY1_SERDES_RX_JRX_TX_DIGITAL1 0x61E30800 +#define DESER_PHY2_SERDES_RX_JRX_TX_DIGITAL1 0x61E31000 +#define DESER_PHY3_SERDES_RX_JRX_TX_DIGITAL1 0x61E31800 +#define DESER_PHY4_SERDES_RX_JRX_TX_DIGITAL1 0x61E32000 +#define DESER_PHY5_SERDES_RX_JRX_TX_DIGITAL1 0x61E32800 +#define DESER_PHY6_SERDES_RX_JRX_TX_DIGITAL1 0x61E33000 +#define DESER_PHY7_SERDES_RX_JRX_TX_DIGITAL1 0x61E33800 +#define DESER_PHY8_SERDES_RX_JRX_TX_DIGITAL1 0x61E34000 +#define DESER_PHY9_SERDES_RX_JRX_TX_DIGITAL1 0x61E34800 +#define DESER_PHY10_SERDES_RX_JRX_TX_DIGITAL1 0x61E35000 +#define DESER_PHY11_SERDES_RX_JRX_TX_DIGITAL1 0x61E35800 +#define DESER_PHY_ALL_SERDES_RX_JRX_TX_DIGITAL1 0x61E36000 + +#define REG_SPI_INTFCONFA_ADDR(inst) ((inst) + 0x00000000) +#define BF_SOFTRESET_INFO(inst) ((inst) + 0x00000000), 0x00000100 + +#define REG_CAL_EN_ADDR(inst) ((inst) + 0x00000001) +#define BF_RFPLL_LOCKED_INFO(inst) ((inst) + 0x00000001), 0x00000100 +#define BF_AUTOCAL_EN_INFO(inst) ((inst) + 0x00000001), 0x00000104 + +#define REG_PD_REG_0_ADDR(inst) ((inst) + 0x00000002) +#define BF_CK_DIS_CKGATES_INFO(inst) ((inst) + 0x00000002), 0x00000100 +#define BF_RXDES_PD_MBIAS_INFO(inst) ((inst) + 0x00000002), 0x00000101 +#define BF_PD_CDR_D_DES_RC_INFO(inst) ((inst) + 0x00000002), 0x00000102 +#define BF_PD_CTLE_DES_RC_INFO(inst) ((inst) + 0x00000002), 0x00000103 +#define BF_CK_PD_PI_INFO(inst) ((inst) + 0x00000002), 0x00000104 +#define BF_CK_PD_PI_DUTYDAC_INFO(inst) ((inst) + 0x00000002), 0x00000105 + +#define REG_PD_REG_1_ADDR(inst) ((inst) + 0x00000003) +#define BF_AFE_PD_CAL_INFO(inst) ((inst) + 0x00000003), 0x00000100 +#define BF_AFE_PD_VCM_INFO(inst) ((inst) + 0x00000003), 0x00000101 +#define BF_CTLE_PD_ODAC_INFO(inst) ((inst) + 0x00000003), 0x00000102 + +#define REG_MBIAS_CTL_ADDR(inst) ((inst) + 0x00000004) +#define BF_RXDES_CTRL_MBIAS_INFO(inst) ((inst) + 0x00000004), 0x00000800 + +#define REG_CAL_ADDR(inst) ((inst) + 0x00000007) +#define BF_PHASESTATE_CAL_EN_INFO(inst) ((inst) + 0x00000007), 0x00000100 +#define BF_PHASESTATE_INFO(inst) ((inst) + 0x00000007), 0x00000104 + +#define REG_LF_DLL_ADDR(inst) ((inst) + 0x00000008) +#define BF_DLLSLEW_INFO(inst) ((inst) + 0x00000008), 0x00000200 +#define BF_DLLSLEW_PREDIV_INFO(inst) ((inst) + 0x00000008), 0x00000204 +#define BF_DLLSLEW_HALFDIV_INFO(inst) ((inst) + 0x00000008), 0x00000206 + +#define REG_LF_DESER_ADDR(inst) ((inst) + 0x00000009) +#define BF_SYNC_DESER8TO32_INFO(inst) ((inst) + 0x00000009), 0x00000100 +#define BF_CLKDIV8_INV_DESER8TO32_INFO(inst) ((inst) + 0x00000009), 0x00000101 +#define BF_CLKDIV32_INV_DESER8TO32_INFO(inst) ((inst) + 0x00000009), 0x00000102 +#define BF_PHI_TEST_EN_INFO(inst) ((inst) + 0x00000009), 0x00000103 + +#define REG_PAR_DATA_CTL_ADDR(inst) ((inst) + 0x0000000A) +#define BF_PAR_DATA_INV_INFO(inst) ((inst) + 0x0000000A), 0x00000100 +#define BF_PAR_CLK_EDGE_INFO(inst) ((inst) + 0x0000000A), 0x00000101 + +#define REG_LF_PHI_RS0_ADDR(inst) ((inst) + 0x0000000B) +#define BF_LF_PHI_DES_RS_INFO(inst) ((inst) + 0x0000000B), 0x00000E00 + +#define REG_LF_PHI_RS1_ADDR(inst) ((inst) + 0x0000000C) + +#define REG_TEST_ADDR(inst) ((inst) + 0x0000000E) +#define BF_RXDES_AMUX_SEL_INFO(inst) ((inst) + 0x0000000E), 0x00000500 + +#define REG_JTAG_ADDR(inst) ((inst) + 0x0000000F) +#define BF_JTAG_DBG_CLK_INFO(inst) ((inst) + 0x0000000F), 0x00000200 +#define BF_JTAG_DBG_INIT_D_INFO(inst) ((inst) + 0x0000000F), 0x00000202 + +#define REG_CK_CTL0_ADDR(inst) ((inst) + 0x00000010) +#define BF_CK_IBSEL_INFO(inst) ((inst) + 0x00000010), 0x00000100 +#define BF_CK_QBSEL_INFO(inst) ((inst) + 0x00000010), 0x00000101 +#define BF_CK_PI_COMSENSEEN_INFO(inst) ((inst) + 0x00000010), 0x00000102 +#define BF_CK_ENSLEWMEAS_INFO(inst) ((inst) + 0x00000010), 0x00000103 +#define BF_CK_PI_DUTYDAC_MAG_INFO(inst) ((inst) + 0x00000010), 0x00000204 +#define BF_CK_PI_DUTYDAC_SGN_INFO(inst) ((inst) + 0x00000010), 0x00000106 + +#define REG_CK_CTL1_ADDR(inst) ((inst) + 0x00000011) +#define BF_CK_PI_PHI_INFO(inst) ((inst) + 0x00000011), 0x00000700 +#define BF_CK_PI_PHI_CLK_INV_INFO(inst) ((inst) + 0x00000011), 0x00000107 + +#define REG_CK_CTL2_ADDR(inst) ((inst) + 0x00000012) +#define BF_CK_PI_SLEWFS_INFO(inst) ((inst) + 0x00000012), 0x00000500 +#define BF_CK_PI_SLEWFS_FORCE_INFO(inst) ((inst) + 0x00000012), 0x00000105 +#define BF_CK_PI_SLEWFS_CAL_FBEN_FORCE_INFO(inst) ((inst) + 0x00000012), 0x00000106 + +#define REG_CK_CTL3_ADDR(inst) ((inst) + 0x00000013) +#define BF_CK_PI_FBEN_INFO(inst) ((inst) + 0x00000013), 0x00000400 +#define BF_CK_PI_SLEW_DFLIP_INFO(inst) ((inst) + 0x00000013), 0x00000104 +#define BF_CK_SLEWRATE_CKFLIP_INFO(inst) ((inst) + 0x00000013), 0x00000105 + +#define REG_CK_CTL4_ADDR(inst) ((inst) + 0x00000014) +#define BF_CK_SPO_ISTROBE_INFO(inst) ((inst) + 0x00000014), 0x00000100 +#define BF_CK_SPO_QSTROBE_INFO(inst) ((inst) + 0x00000014), 0x00000101 +#define BF_CK_SPO_UP_DN_INFO(inst) ((inst) + 0x00000014), 0x00000102 + +#define REG_CK_CTL5_ADDR(inst) ((inst) + 0x00000015) +#define BF_CK_PI_CAL_INIT_INFO(inst) ((inst) + 0x00000015), 0x00000100 +#define BF_CK_PI_COUNT_TOTAL_INFO(inst) ((inst) + 0x00000015), 0x00000301 +#define BF_CK_PI_COUNT_THR_DIFF_INFO(inst) ((inst) + 0x00000015), 0x00000404 + +#define REG_CK_CTL6_ADDR(inst) ((inst) + 0x00000016) +#define BF_CK_PI_DUTY_SEL_INFO(inst) ((inst) + 0x00000016), 0x00000300 +#define BF_CK_PI_REG_READ_INFO(inst) ((inst) + 0x00000016), 0x00000203 +#define BF_CK_PI_ROCLK_INFO(inst) ((inst) + 0x00000016), 0x00000105 +#define BF_CK_PI_ROCLK_BYPASS_INFO(inst) ((inst) + 0x00000016), 0x00000106 +#define BF_CK_PI_MEAS_INIT_INFO(inst) ((inst) + 0x00000016), 0x00000107 + +#define REG_CK_CTL7_ADDR(inst) ((inst) + 0x00000017) +#define BF_CK_PI_SLEWFS_OUT_INFO(inst) ((inst) + 0x00000017), 0x00000500 +#define BF_CK_PI_MEASIOUT_INFO(inst) ((inst) + 0x00000017), 0x00000105 +#define BF_CK_PI_MEASQOUT_INFO(inst) ((inst) + 0x00000017), 0x00000106 + +#define REG_CK_CTL8_ADDR(inst) ((inst) + 0x00000018) +#define BF_CK_PI_CAL_STATE_INFO(inst) ((inst) + 0x00000018), 0x00000400 +#define BF_CK_PI_CAL_DONE_INFO(inst) ((inst) + 0x00000018), 0x00000104 +#define BF_CK_PI_CAL_INPROGRESS_INFO(inst) ((inst) + 0x00000018), 0x00000105 +#define BF_CK_PI_MEAS_DONE_INFO(inst) ((inst) + 0x00000018), 0x00000106 +#define BF_CK_PI_MEAS_INPROGRESS_INFO(inst) ((inst) + 0x00000018), 0x00000107 + +#define REG_CK_CTL9_ADDR(inst) ((inst) + 0x00000019) +#define BF_CK_PI_COUNT_OUT_INFO(inst) ((inst) + 0x00000019), 0x00001000 + +#define REG_CK_CTL10_ADDR(inst) ((inst) + 0x0000001A) + +#define REG_CTLE_CTL0_ADDR(inst) ((inst) + 0x00000020) +#define BF_CTLE_STROBE_INFO(inst) ((inst) + 0x00000020), 0x00000100 +#define BF_AFE_CAL_STROBE_INFO(inst) ((inst) + 0x00000020), 0x00000101 +#define BF_AFE_CAL_STEP_INFO(inst) ((inst) + 0x00000020), 0x00000102 +#define BF_AFE_CAL_INIT_INFO(inst) ((inst) + 0x00000020), 0x00000104 +#define BF_FORCE_AFE_CAL_INFO(inst) ((inst) + 0x00000020), 0x00000105 +#define BF_FORCE_CTLE_REG_INFO(inst) ((inst) + 0x00000020), 0x00000106 +#define BF_CTLE_REG_OVERRIDE_INFO(inst) ((inst) + 0x00000020), 0x00000107 + +#define REG_CTLE_CTL1_ADDR(inst) ((inst) + 0x00000021) +#define BF_AFE_STATE_INFO(inst) ((inst) + 0x00000021), 0x00000500 +#define BF_AFE_CAL_DONE_INFO(inst) ((inst) + 0x00000021), 0x00000105 +#define BF_AFE_CAL_OUT_INFO(inst) ((inst) + 0x00000021), 0x00000106 + +#define REG_CTLE_CTL2_ADDR(inst) ((inst) + 0x00000022) +#define BF_CTLE_REG_DROPOUT_INFO(inst) ((inst) + 0x00000022), 0x00000500 +#define BF_CTLE_REG_CM_ADJUST_INFO(inst) ((inst) + 0x00000022), 0x00000305 + +#define REG_CTLE_CTL3_ADDR(inst) ((inst) + 0x00000023) +#define BF_CTLE_S1_GM_INFO(inst) ((inst) + 0x00000023), 0x00000500 + +#define REG_CTLE_CTL4_ADDR(inst) ((inst) + 0x00000024) +#define BF_CTLE_S1_LD_INFO(inst) ((inst) + 0x00000024), 0x00000400 +#define BF_CTLE_SQUELCH_INFO(inst) ((inst) + 0x00000024), 0x00000104 + +#define REG_CTLE_CTL5_ADDR(inst) ((inst) + 0x00000025) +#define BF_CTLE_S2_GM_INFO(inst) ((inst) + 0x00000025), 0x00000400 +#define BF_CTLE_S2_LD_INFO(inst) ((inst) + 0x00000025), 0x00000404 + +#define REG_CTLE_CTL6_ADDR(inst) ((inst) + 0x00000026) +#define BF_CTLE_S1_RP_INFO(inst) ((inst) + 0x00000026), 0x00000300 +#define BF_CTLE_S2_RP_INFO(inst) ((inst) + 0x00000026), 0x00000304 + +#define REG_CTLE_CTL7_ADDR(inst) ((inst) + 0x00000027) +#define BF_CTLE_PGA_LD_INFO(inst) ((inst) + 0x00000027), 0x00000800 + +#define REG_CTLE_CTL8_ADDR(inst) ((inst) + 0x00000028) +#define BF_CTLE_PGA_GM_INFO(inst) ((inst) + 0x00000028), 0x00001000 + +#define REG_CTLE_CTL9_ADDR(inst) ((inst) + 0x00000029) + +#define REG_CTLE_CTL10_ADDR(inst) ((inst) + 0x0000002A) +#define BF_CTLE_RSHUNT_EN_INFO(inst) ((inst) + 0x0000002A), 0x00000200 +#define BF_CTLE_RSHUNT_5K_EN_INFO(inst) ((inst) + 0x0000002A), 0x00000102 +#define BF_CTLE_RSER_EN_INFO(inst) ((inst) + 0x0000002A), 0x00000103 +#define BF_CTLE_REG_OVERRIDE_AMP_INFO(inst) ((inst) + 0x0000002A), 0x00000104 + +#define REG_CTLE_CTL11_ADDR(inst) ((inst) + 0x0000002B) +#define BF_CTLE_CSER_INFO(inst) ((inst) + 0x0000002B), 0x00000F00 + +#define REG_CTLE_CTL12_ADDR(inst) ((inst) + 0x0000002C) + +#define REG_CTLE_CTL13_ADDR(inst) ((inst) + 0x0000002D) +#define BF_CTLE_B_CTLE_ODAC_INFO(inst) ((inst) + 0x0000002D), 0x00000500 + +#define REG_CTLE_CTL14_ADDR(inst) ((inst) + 0x0000002E) +#define BF_CTLE_B_AFE_ODAC_INFO(inst) ((inst) + 0x0000002E), 0x00000500 + +#define REG_CTLE_CTL15_ADDR(inst) ((inst) + 0x0000002F) +#define BF_AFE_PROG_DLY_INFO(inst) ((inst) + 0x0000002F), 0x00000200 +#define BF_AFE_PROG_DROPOUT_MIN_INFO(inst) ((inst) + 0x0000002F), 0x00000202 +#define BF_AFE_PROG_DROPOUT_MAX_INFO(inst) ((inst) + 0x0000002F), 0x00000204 + +#define REG_CTLE_CTL16_ADDR(inst) ((inst) + 0x00000030) +#define BF_CTLE_REG_DROPOUT_SM_INFO(inst) ((inst) + 0x00000030), 0x00000500 + +#define REG_CTLE_CTL17_ADDR(inst) ((inst) + 0x00000031) +#define BF_CTLE_B_AFE_ODAC_SM_INFO(inst) ((inst) + 0x00000031), 0x00000500 + +#define REG_RAM_CTL0_ADDR(inst) ((inst) + 0x00000032) +#define BF_RAM_CEN_INFO(inst) ((inst) + 0x00000032), 0x00000104 +#define BF_RAM_WEN_INFO(inst) ((inst) + 0x00000032), 0x00000105 +#define BF_RAM_BYPASS_INFO(inst) ((inst) + 0x00000032), 0x00000106 + +#define REG_RAM_CTL1_ADDR(inst) ((inst) + 0x00000033) +#define BF_RAM_ADDR_INFO(inst) ((inst) + 0x00000033), 0x00000C00 + +#define REG_RAM_CTL2_ADDR(inst) ((inst) + 0x00000034) +#define BF_RAM_WDATA_INFO(inst) ((inst) + 0x00000034), 0x00001000 + +#define REG_RAM_CTL3_ADDR(inst) ((inst) + 0x00000035) + +#define REG_RAM_CTL4_ADDR(inst) ((inst) + 0x00000036) +#define BF_RAM_RDATA_INFO(inst) ((inst) + 0x00000036), 0x00001000 + +#define REG_RAM_CTL5_ADDR(inst) ((inst) + 0x00000037) + +#define REG_LMS_CTL0_ADDR(inst) ((inst) + 0x00000038) +#define BF_LMS_RESET_INFO(inst) ((inst) + 0x00000038), 0x00000100 +#define BF_LMS_BREAKPT_EN_INFO(inst) ((inst) + 0x00000038), 0x00000101 +#define BF_BOOTLOAD_EN_INFO(inst) ((inst) + 0x00000038), 0x00000104 +#define BF_BOOTLOAD_START_INFO(inst) ((inst) + 0x00000038), 0x00000105 + +#define REG_LMS_CTL1_ADDR(inst) ((inst) + 0x00000039) +#define BF_BOOTLOAD_ON_INFO(inst) ((inst) + 0x00000039), 0x00000104 +#define BF_BOOTLOAD_DONE_INFO(inst) ((inst) + 0x00000039), 0x00000105 + +#define REG_LMS_CTL2_ADDR(inst) ((inst) + 0x0000003A) +#define BF_LMS_NUM_ITER_INFO(inst) ((inst) + 0x0000003A), 0x00000800 + +#define REG_LMS_CTL3_ADDR(inst) ((inst) + 0x0000003B) +#define BF_LMS_FLASH_MSK_PRE_INFO(inst) ((inst) + 0x0000003B), 0x00000800 + +#define REG_LMS_CTL4_ADDR(inst) ((inst) + 0x0000003C) +#define BF_LMS_FLASH_MSK_POST_INFO(inst) ((inst) + 0x0000003C), 0x00000800 + +#define REG_LMS_CTL5_ADDR(inst) ((inst) + 0x0000003D) +#define BF_LMS_UPP_THRESH_INFO(inst) ((inst) + 0x0000003D), 0x00001000 + +#define REG_LMS_CTL6_ADDR(inst) ((inst) + 0x0000003E) + +#define REG_LMS_CTL7_ADDR(inst) ((inst) + 0x0000003F) +#define BF_LMS_BREAKPT_INFO(inst) ((inst) + 0x0000003F), 0x00000B00 + +#define REG_LMS_CTL8_ADDR(inst) ((inst) + 0x00000040) + +#define REG_LMS_CTL9_ADDR(inst) ((inst) + 0x00000041) +#define BF_LMS_CTL_FLAG_INFO(inst) ((inst) + 0x00000041), 0x00000800 + +#define REG_LMS_CTL10_ADDR(inst) ((inst) + 0x00000042) +#define BF_LMS_INNER_UP_STA_INFO(inst) ((inst) + 0x00000042), 0x00000700 + +#define REG_LMS_CTL11_ADDR(inst) ((inst) + 0x00000043) +#define BF_LMS_OUTER_UP_STA_INFO(inst) ((inst) + 0x00000043), 0x00000700 + +#define REG_LMS_CTL12_ADDR(inst) ((inst) + 0x00000044) +#define BF_LMS_INNER_DN_STA_INFO(inst) ((inst) + 0x00000044), 0x00000700 + +#define REG_LMS_CTL13_ADDR(inst) ((inst) + 0x00000045) +#define BF_LMS_OUTER_DN_STA_INFO(inst) ((inst) + 0x00000045), 0x00000700 + +#define REG_LMS_CTL14_ADDR(inst) ((inst) + 0x00000046) +#define BF_LMS_B2_STA_INFO(inst) ((inst) + 0x00000046), 0x00000600 + +#define REG_LMS_CTL15_ADDR(inst) ((inst) + 0x00000047) +#define BF_LMS_B3_STA_INFO(inst) ((inst) + 0x00000047), 0x00000600 + +#define REG_LMS_CTL16_ADDR(inst) ((inst) + 0x00000048) +#define BF_LMS_B4_STA_INFO(inst) ((inst) + 0x00000048), 0x00000500 + +#define REG_LMS_CTL17_ADDR(inst) ((inst) + 0x00000049) +#define BF_LMS_B5_STA_INFO(inst) ((inst) + 0x00000049), 0x00000500 + +#define REG_LMS_CTL18_ADDR(inst) ((inst) + 0x0000004A) +#define BF_LMS_B6_STA_INFO(inst) ((inst) + 0x0000004A), 0x00000500 + +#define REG_LMS_CTL19_ADDR(inst) ((inst) + 0x0000004B) +#define BF_LMS_DONE_INFO(inst) ((inst) + 0x0000004B), 0x00000800 + +#define REG_CTL_SPARE0_ADDR(inst) ((inst) + 0x00000050) +#define BF_CTL_SPARE0_INFO(inst) ((inst) + 0x00000050), 0x00000800 + +#define REG_CTL_SPARE1_ADDR(inst) ((inst) + 0x00000051) +#define BF_CTL_SPARE1_INFO(inst) ((inst) + 0x00000051), 0x00000800 + +#define REG_CTL_SPARE2_ADDR(inst) ((inst) + 0x00000052) +#define BF_CTL_SPARE2_INFO(inst) ((inst) + 0x00000052), 0x00000800 + +#define REG_CTL_SPARE3_ADDR(inst) ((inst) + 0x00000053) +#define BF_CTL_SPARE3_INFO(inst) ((inst) + 0x00000053), 0x00000800 + +#define REG_STATUS_SPARE0_ADDR(inst) ((inst) + 0x00000054) +#define BF_STATUS_SPARE0_INFO(inst) ((inst) + 0x00000054), 0x00000800 + +#define REG_STATUS_SPARE1_ADDR(inst) ((inst) + 0x00000055) +#define BF_STATUS_SPARE1_INFO(inst) ((inst) + 0x00000055), 0x00000800 + +#define REG_VARDCO_CTL_0_ADDR(inst) ((inst) + 0x00000058) +#define BF_VARDCO_LFSR_VALUE_INFO(inst) ((inst) + 0x00000058), 0x00000500 +#define BF_VARDCO_LFSR_BYPASS_INFO(inst) ((inst) + 0x00000058), 0x00000105 +#define BF_VARDCO_EN_INFO(inst) ((inst) + 0x00000058), 0x00000106 + +#define REG_VARDCO_CTL_1_ADDR(inst) ((inst) + 0x00000059) +#define BF_VARDCO_DIVN_INFO(inst) ((inst) + 0x00000059), 0x00000300 +#define BF_VARDCO_DIVM_INFO(inst) ((inst) + 0x00000059), 0x00000304 + +#define REG_USR_RETIMER_CTL_ADDR(inst) ((inst) + 0x00000060) +#define BF_USR_PD_INFO(inst) ((inst) + 0x00000060), 0x00000100 +#define BF_USR_SLICE0_PD_INFO(inst) ((inst) + 0x00000060), 0x00000101 +#define BF_USR_SLICE1_PD_INFO(inst) ((inst) + 0x00000060), 0x00000102 +#define BF_USR_SEL_INFO(inst) ((inst) + 0x00000060), 0x00000103 +#define BF_USR_PI_DELAY_CAL_INIT_INFO(inst) ((inst) + 0x00000060), 0x00000104 +#define BF_USR_PI_DELAY_CAL_ITER_INFO(inst) ((inst) + 0x00000060), 0x00000205 + +#define REG_USR_CTLE_CTL0_ADDR(inst) ((inst) + 0x00000061) +#define BF_USR_GM_BOOST_EN_INFO(inst) ((inst) + 0x00000061), 0x00000100 +#define BF_USR_RESETB_TIA_COMP_ODACS_INFO(inst) ((inst) + 0x00000061), 0x00000101 +#define BF_USR_TIA_RSHORT_COMP_INFO(inst) ((inst) + 0x00000061), 0x00000102 +#define BF_USR_EN_TIA_AMUX_INFO(inst) ((inst) + 0x00000061), 0x00000103 +#define BF_USR_TIA_PD_COMP_INFO(inst) ((inst) + 0x00000061), 0x00000104 + +#define REG_USR_CTLE_CTL1_ADDR(inst) ((inst) + 0x00000062) +#define BF_USR_TIA_ODAC_INFO(inst) ((inst) + 0x00000062), 0x00000600 +#define BF_USR_TIA_ODAC_STROBE_INFO(inst) ((inst) + 0x00000062), 0x00000106 + +#define REG_USR_CTLE_CTL2_ADDR(inst) ((inst) + 0x00000063) +#define BF_USR_TIACOMP_ODAC_INFO(inst) ((inst) + 0x00000063), 0x00000600 +#define BF_USR_TIACOMP_ODAC_STROBE_INFO(inst) ((inst) + 0x00000063), 0x00000106 + +#define REG_USR_PI_CTL0_ADDR(inst) ((inst) + 0x00000064) +#define BF_USR_PI_SLEWFS_OFFSET_INFO(inst) ((inst) + 0x00000064), 0x00000500 +#define BF_USR_PI_ENMEAS_INFO(inst) ((inst) + 0x00000064), 0x00000105 +#define BF_USR_PI_SEL90_135_INFO(inst) ((inst) + 0x00000064), 0x00000106 +#define BF_USR_SLEWMEAS_JESD_SRC_INFO(inst) ((inst) + 0x00000064), 0x00000107 + +#define REG_USR_PI_CTL1_ADDR(inst) ((inst) + 0x00000065) +#define BF_USR_PI_PH45_INFO(inst) ((inst) + 0x00000065), 0x00000600 +#define BF_USR_PI_PH45_OVRD_INFO(inst) ((inst) + 0x00000065), 0x00000106 + +#define REG_USR_PI_CTL2_ADDR(inst) ((inst) + 0x00000066) +#define BF_USR_PI_PH45_OUT_INFO(inst) ((inst) + 0x00000066), 0x00000600 +#define BF_CK_USR_CAL_INPROGRESS_INFO(inst) ((inst) + 0x00000066), 0x00000106 +#define BF_CK_USR_CAL_DONE_INFO(inst) ((inst) + 0x00000066), 0x00000107 + +#define REG_USR_PI_CTL3_ADDR(inst) ((inst) + 0x00000067) +#define BF_USR_PI_PH135_INFO(inst) ((inst) + 0x00000067), 0x00000600 + +#define REG_USR_TIA_CAL_CTL0_ADDR(inst) ((inst) + 0x00000068) +#define BF_TIA_CAL_INIT_INFO(inst) ((inst) + 0x00000068), 0x00000100 +#define BF_TIA_DCMEASURE_INIT_INFO(inst) ((inst) + 0x00000068), 0x00000101 +#define BF_TIA_COMPCAL_BYP_INFO(inst) ((inst) + 0x00000068), 0x00000102 +#define BF_TIA_LA_OFFSET_BYP_INFO(inst) ((inst) + 0x00000068), 0x00000103 +#define BF_TIA_COMPCAL_POL_INFO(inst) ((inst) + 0x00000068), 0x00000104 +#define BF_TIA_LA_OFFSET_POL_INFO(inst) ((inst) + 0x00000068), 0x00000105 +#define BF_TIA_CAL_BYPASS_INFO(inst) ((inst) + 0x00000068), 0x00000106 + +#define REG_USR_TIA_CAL_STA0_ADDR(inst) ((inst) + 0x00000069) +#define BF_TIA_LIMAMP_CAL_STATE_INFO(inst) ((inst) + 0x00000069), 0x00000400 +#define BF_TIA_LIMAMP_CAL_DONE_INFO(inst) ((inst) + 0x00000069), 0x00000104 + +#define REG_USR_TIA_CAL_STA1_ADDR(inst) ((inst) + 0x0000006A) +#define BF_TIA_LIMAMP_CAL_STA_INFO(inst) ((inst) + 0x0000006A), 0x00000700 + +#define REG_USR_AMUX_CTL_ADDR(inst) ((inst) + 0x0000006B) +#define BF_RXDES_AMUX_USR_SEL_INFO(inst) ((inst) + 0x0000006B), 0x00000800 + +#define REG_USR_SPARE_CTL_ADDR(inst) ((inst) + 0x0000006C) +#define BF_USR_SPARE_INFO(inst) ((inst) + 0x0000006C), 0x00000800 + +#define REG_PRBS_DEBUG_CTL0_ADDR(inst) ((inst) + 0x00000070) +#define BF_PRBS_RCV_EN_INFO(inst) ((inst) + 0x00000070), 0x00000100 +#define BF_PRBS_RCV_DATAREC_EN_INFO(inst) ((inst) + 0x00000070), 0x00000101 +#define BF_PRBS_RCV_DATAREC_MODE_INFO(inst) ((inst) + 0x00000070), 0x00000202 +#define BF_PRBS_RCV_DATAREC_CLR_INFO(inst) ((inst) + 0x00000070), 0x00000104 +#define BF_PRBS_RCV_AUTO_MODE_INFO(inst) ((inst) + 0x00000070), 0x00000105 + +#define REG_PRBS_DEBUG_CTL1_ADDR(inst) ((inst) + 0x00000071) +#define BF_PRBS_RCV_AUTO_MODE_THRESH_INFO(inst) ((inst) + 0x00000071), 0x00000600 + +#define REG_PRBS_DEBUG_STA0_ADDR(inst) ((inst) + 0x00000072) +#define BF_PRBS_RCV_ERR_INFO(inst) ((inst) + 0x00000072), 0x00000100 +#define BF_PRBS_RCV_ERR_STICKY_INFO(inst) ((inst) + 0x00000072), 0x00000101 +#define BF_PRBS_RCV_AUTO_MODE_DONE_INFO(inst) ((inst) + 0x00000072), 0x00000104 + +#define REG_PRBS_DEBUG_STA1_ADDR(inst) ((inst) + 0x00000073) +#define BF_PRBS_RCV_ERR_CNT_INFO(inst) ((inst) + 0x00000073), 0x00002000 + +#define REG_PRBS_DEBUG_STA2_ADDR(inst) ((inst) + 0x00000074) + +#define REG_PRBS_DEBUG_STA3_ADDR(inst) ((inst) + 0x00000075) + +#define REG_PRBS_DEBUG_STA4_ADDR(inst) ((inst) + 0x00000076) + +#define REG_DAT_DEBUG_CTL0_ADDR(inst) ((inst) + 0x00000077) +#define BF_CAPTURE_SAMPLE_INFO(inst) ((inst) + 0x00000077), 0x00000100 +#define BF_DMX_OUT_CLK_GATE_INFO(inst) ((inst) + 0x00000077), 0x00000101 + +#define REG_DAT_DEBUG_SAMPLE0_ADDR(inst) ((inst) + 0x00000078) +#define BF_SAMPLE_LATCHED_DATA_INFO(inst) ((inst) + 0x00000078), 0x00002000 + +#define REG_DAT_DEBUG_SAMPLE1_ADDR(inst) ((inst) + 0x00000079) + +#define REG_DAT_DEBUG_SAMPLE2_ADDR(inst) ((inst) + 0x0000007A) + +#define REG_DAT_DEBUG_SAMPLE3_ADDR(inst) ((inst) + 0x0000007B) + +#define REG_DAT_DEBUG_SAMPLE4_ADDR(inst) ((inst) + 0x0000007C) +#define BF_SAMPLE_LATCHED_ERR_INFO(inst) ((inst) + 0x0000007C), 0x00002000 + +#define REG_DAT_DEBUG_SAMPLE5_ADDR(inst) ((inst) + 0x0000007D) + +#define REG_DAT_DEBUG_SAMPLE6_ADDR(inst) ((inst) + 0x0000007E) + +#define REG_DAT_DEBUG_SAMPLE7_ADDR(inst) ((inst) + 0x0000007F) + +#define REG_CAL_CTL0_ADDR(inst) ((inst) + 0x00000080) +#define BF_CAL_ACC_EN_INFO(inst) ((inst) + 0x00000080), 0x00000101 +#define BF_CAL_ACC_TIMEOUT_EN_INFO(inst) ((inst) + 0x00000080), 0x00000102 +#define BF_CAL_ACC_INTERRUPT_EN_INFO(inst) ((inst) + 0x00000080), 0x00000103 +#define BF_CAL_ACC_EIN_SRC_INFO(inst) ((inst) + 0x00000080), 0x00000204 + +#define REG_CAL_CTL1_ADDR(inst) ((inst) + 0x00000081) +#define BF_CAL_DSHIFT0_INFO(inst) ((inst) + 0x00000081), 0x00000300 +#define BF_CAL_FUNC0_INFO(inst) ((inst) + 0x00000081), 0x00000304 + +#define REG_CAL_CTL2_ADDR(inst) ((inst) + 0x00000082) +#define BF_CAL_DSHIFT1_INFO(inst) ((inst) + 0x00000082), 0x00000300 +#define BF_CAL_FUNC1_INFO(inst) ((inst) + 0x00000082), 0x00000304 + +#define REG_CAL_CTL3_ADDR(inst) ((inst) + 0x00000083) +#define BF_CAL_DSHIFT2_INFO(inst) ((inst) + 0x00000083), 0x00000300 +#define BF_CAL_FUNC2_INFO(inst) ((inst) + 0x00000083), 0x00000304 + +#define REG_CAL_CTL4_ADDR(inst) ((inst) + 0x00000084) +#define BF_CAL_DSHIFT3_INFO(inst) ((inst) + 0x00000084), 0x00000300 +#define BF_CAL_FUNC3_INFO(inst) ((inst) + 0x00000084), 0x00000304 + +#define REG_CAL_CTL5_ADDR(inst) ((inst) + 0x00000085) +#define BF_CAL_MASK0_INFO(inst) ((inst) + 0x00000085), 0x00000800 + +#define REG_CAL_CTL6_ADDR(inst) ((inst) + 0x00000086) +#define BF_CAL_MASK1_INFO(inst) ((inst) + 0x00000086), 0x00000800 + +#define REG_CAL_CTL7_ADDR(inst) ((inst) + 0x00000087) +#define BF_CAL_MASK2_INFO(inst) ((inst) + 0x00000087), 0x00000800 + +#define REG_CAL_CTL8_ADDR(inst) ((inst) + 0x00000088) +#define BF_CAL_MASK3_INFO(inst) ((inst) + 0x00000088), 0x00000800 + +#define REG_CAL_CTL9_ADDR(inst) ((inst) + 0x00000089) +#define BF_CAL_QUAD0_INFO(inst) ((inst) + 0x00000089), 0x00000400 +#define BF_CAL_QUAD1_INFO(inst) ((inst) + 0x00000089), 0x00000404 + +#define REG_CAL_CTL10_ADDR(inst) ((inst) + 0x0000008A) +#define BF_CAL_QUAD2_INFO(inst) ((inst) + 0x0000008A), 0x00000400 +#define BF_CAL_QUAD3_INFO(inst) ((inst) + 0x0000008A), 0x00000404 + +#define REG_CAL_CTL11_ADDR(inst) ((inst) + 0x0000008B) +#define BF_CAL_COUNT_LIMIT_INFO(inst) ((inst) + 0x0000008B), 0x00001000 + +#define REG_CAL_CTL12_ADDR(inst) ((inst) + 0x0000008C) + +#define REG_CAL_CTL13_ADDR(inst) ((inst) + 0x0000008D) +#define BF_CAL_TIMEOUT_CNT_INFO(inst) ((inst) + 0x0000008D), 0x00001000 + +#define REG_CAL_CTL14_ADDR(inst) ((inst) + 0x0000008E) + +#define REG_CAL_CTL15_ADDR(inst) ((inst) + 0x0000008F) +#define BF_CAL_ACC_DONE_ALL_STA_INFO(inst) ((inst) + 0x0000008F), 0x00000100 +#define BF_CAL_ACC_TIMEOUT_STA_INFO(inst) ((inst) + 0x0000008F), 0x00000101 +#define BF_CAL_ACC_INTERRUPT_INFO(inst) ((inst) + 0x0000008F), 0x00000102 + +#define REG_CAL_CTL16_ADDR(inst) ((inst) + 0x00000090) +#define BF_CAL_ACC_STA0_INFO(inst) ((inst) + 0x00000090), 0x00001000 + +#define REG_CAL_CTL17_ADDR(inst) ((inst) + 0x00000091) + +#define REG_CAL_CTL18_ADDR(inst) ((inst) + 0x00000092) +#define BF_CAL_ACC_STA1_INFO(inst) ((inst) + 0x00000092), 0x00001000 + +#define REG_CAL_CTL19_ADDR(inst) ((inst) + 0x00000093) + +#define REG_CAL_CTL20_ADDR(inst) ((inst) + 0x00000094) +#define BF_CAL_ACC_STA2_INFO(inst) ((inst) + 0x00000094), 0x00001000 + +#define REG_CAL_CTL21_ADDR(inst) ((inst) + 0x00000095) + +#define REG_CAL_CTL22_ADDR(inst) ((inst) + 0x00000096) +#define BF_CAL_ACC_STA3_INFO(inst) ((inst) + 0x00000096), 0x00001000 + +#define REG_CAL_CTL23_ADDR(inst) ((inst) + 0x00000097) + +#define REG_CAL_CTL24_ADDR(inst) ((inst) + 0x00000098) +#define BF_CAL_CNT_STA0_INFO(inst) ((inst) + 0x00000098), 0x00001000 + +#define REG_CAL_CTL25_ADDR(inst) ((inst) + 0x00000099) + +#define REG_CAL_CTL26_ADDR(inst) ((inst) + 0x0000009A) +#define BF_CAL_CNT_STA1_INFO(inst) ((inst) + 0x0000009A), 0x00001000 + +#define REG_CAL_CTL27_ADDR(inst) ((inst) + 0x0000009B) + +#define REG_CAL_CTL28_ADDR(inst) ((inst) + 0x0000009C) +#define BF_CAL_CNT_STA2_INFO(inst) ((inst) + 0x0000009C), 0x00001000 + +#define REG_CAL_CTL29_ADDR(inst) ((inst) + 0x0000009D) + +#define REG_CAL_CTL30_ADDR(inst) ((inst) + 0x0000009E) +#define BF_CAL_CNT_STA3_INFO(inst) ((inst) + 0x0000009E), 0x00001000 + +#define REG_CAL_CTL31_ADDR(inst) ((inst) + 0x0000009F) + +#define REG_CAL_CTL32_ADDR(inst) ((inst) + 0x000000A0) +#define BF_CAL_LCNT_STA_INFO(inst) ((inst) + 0x000000A0), 0x00001000 + +#define REG_CAL_CTL33_ADDR(inst) ((inst) + 0x000000A1) + +#define REG_DCMEASURE_CTL0_ADDR(inst) ((inst) + 0x000000A8) +#define BF_DCMEASURE_CAL_EN_INFO(inst) ((inst) + 0x000000A8), 0x00000100 +#define BF_DCMEASURE_LD_INFO(inst) ((inst) + 0x000000A8), 0x00000101 +#define BF_DCMEASURE_HOLD_INFO(inst) ((inst) + 0x000000A8), 0x00000102 +#define BF_DCMEASURE_POL_INFO(inst) ((inst) + 0x000000A8), 0x00000103 +#define BF_DCD_DAC_DC_CNT_RDBK_HOLD_RC_INFO(inst) ((inst) + 0x000000A8), 0x00000104 + +#define REG_DCMEASURE_CTL1_ADDR(inst) ((inst) + 0x000000A9) +#define BF_DCMEASURE_CTLE_B_CTLE_ODAC_INFO(inst) ((inst) + 0x000000A9), 0x00000500 + +#define REG_DCD_DAC_DCUP_CNT_RDBK_0_ADDR(inst) ((inst) + 0x000000AA) +#define BF_DCD_DAC_DCUP_CNT_RDBK_RS_INFO(inst) ((inst) + 0x000000AA), 0x00000B00 + +#define REG_DCD_DAC_DCUP_CNT_RDBK_1_ADDR(inst) ((inst) + 0x000000AB) + +#define REG_DCD_DAC_DCDN_CNT_RDBK_0_ADDR(inst) ((inst) + 0x000000AC) +#define BF_DCD_DAC_DCDN_CNT_RDBK_RS_INFO(inst) ((inst) + 0x000000AC), 0x00000B00 + +#define REG_DCD_DAC_DCDN_CNT_RDBK_1_ADDR(inst) ((inst) + 0x000000AD) + +#define REG_DCD_DAC_HYSTERESIS_ADDR(inst) ((inst) + 0x000000AE) +#define BF_DCD_DAC_HYSTERESIS_CODE_RC_INFO(inst) ((inst) + 0x000000AE), 0x00000800 + +#define REG_EYEMON_CTL0_ADDR(inst) ((inst) + 0x000000B0) +#define BF_EYEMON_EN_INFO(inst) ((inst) + 0x000000B0), 0x00000100 +#define BF_EYEMON_START_INFO(inst) ((inst) + 0x000000B0), 0x00000101 +#define BF_EYEMON_MEAS_EN_INFO(inst) ((inst) + 0x000000B0), 0x00000104 + +#define REG_EYEMON_CTL1_ADDR(inst) ((inst) + 0x000000B1) +#define BF_EYEMON_THRESH_INFO(inst) ((inst) + 0x000000B1), 0x00000800 + +#define REG_EYEMON_STATUS0_ADDR(inst) ((inst) + 0x000000B2) +#define BF_EYEMON_STATE_INFO(inst) ((inst) + 0x000000B2), 0x00000600 + +#define REG_EYEMON_STATUS1_ADDR(inst) ((inst) + 0x000000B3) +#define BF_EYEMON_SPOI_CNT_INFO(inst) ((inst) + 0x000000B3), 0x00000500 + +#define REG_EYEMON_STATUS2_ADDR(inst) ((inst) + 0x000000B4) +#define BF_EYEMON_SPOQ_CNT_INFO(inst) ((inst) + 0x000000B4), 0x00000500 + +#define REG_EYEMON_STATUS3_ADDR(inst) ((inst) + 0x000000B5) +#define BF_EYEMON_SPOG_MEAS_INFO(inst) ((inst) + 0x000000B5), 0x00001000 + +#define REG_EYEMON_STATUS4_ADDR(inst) ((inst) + 0x000000B6) + +#define REG_EYEMON_STATUS5_ADDR(inst) ((inst) + 0x000000B7) +#define BF_EYEMON_SPOI_MEAS_INFO(inst) ((inst) + 0x000000B7), 0x00001000 + +#define REG_EYEMON_STATUS6_ADDR(inst) ((inst) + 0x000000B8) + +#define REG_EYEMON_STATUS7_ADDR(inst) ((inst) + 0x000000B9) +#define BF_EYEMON_SPOQ_MEAS_INFO(inst) ((inst) + 0x000000B9), 0x00001000 + +#define REG_EYEMON_STATUS8_ADDR(inst) ((inst) + 0x000000BA) + +#define REG_DFE_CTL0_ADDR(inst) ((inst) + 0x000000C0) +#define BF_S0_PD_IFB2_INFO(inst) ((inst) + 0x000000C0), 0x00000100 +#define BF_S0_PD_IFB3_INFO(inst) ((inst) + 0x000000C0), 0x00000101 +#define BF_S1_PD_IFB2_INFO(inst) ((inst) + 0x000000C0), 0x00000102 +#define BF_S1_PD_IFB3_INFO(inst) ((inst) + 0x000000C0), 0x00000103 + +#define REG_DFE_CTL1_ADDR(inst) ((inst) + 0x000000C1) +#define BF_FORCE_E_S0F0_INFO(inst) ((inst) + 0x000000C1), 0x00000400 +#define BF_FORCE_E_S0F1_INFO(inst) ((inst) + 0x000000C1), 0x00000404 + +#define REG_DFE_CTL2_ADDR(inst) ((inst) + 0x000000C2) +#define BF_FORCE_E_S1F0_INFO(inst) ((inst) + 0x000000C2), 0x00000400 +#define BF_FORCE_E_S1F1_INFO(inst) ((inst) + 0x000000C2), 0x00000404 + +#define REG_DFE_CTL3_ADDR(inst) ((inst) + 0x000000C3) +#define BF_S0_B_FB2_INFO(inst) ((inst) + 0x000000C3), 0x00000600 + +#define REG_DFE_CTL4_ADDR(inst) ((inst) + 0x000000C4) +#define BF_S0_B_FB3_INFO(inst) ((inst) + 0x000000C4), 0x00000600 + +#define REG_DFE_CTL5_ADDR(inst) ((inst) + 0x000000C5) +#define BF_S1_B_FB2_INFO(inst) ((inst) + 0x000000C5), 0x00000600 + +#define REG_DFE_CTL6_ADDR(inst) ((inst) + 0x000000C6) +#define BF_S1_B_FB3_INFO(inst) ((inst) + 0x000000C6), 0x00000600 + +#define REG_DFE_CTL7_ADDR(inst) ((inst) + 0x000000C7) +#define BF_DFE_CM_GMSW_INFO(inst) ((inst) + 0x000000C7), 0x00000500 +#define BF_DFE_CM_GMSW_OVRD_INFO(inst) ((inst) + 0x000000C7), 0x00000105 +#define BF_DFE_GMSW_CAP_DEL_INFO(inst) ((inst) + 0x000000C7), 0x00000106 + +#define REG_DFE_CTL8_ADDR(inst) ((inst) + 0x000000C8) +#define BF_S0_USESKEW_INFO(inst) ((inst) + 0x000000C8), 0x00000600 + +#define REG_DFE_CTL9_ADDR(inst) ((inst) + 0x000000C9) +#define BF_S1_USESKEW_INFO(inst) ((inst) + 0x000000C9), 0x00000600 + +#define REG_DFE_CTL10_ADDR(inst) ((inst) + 0x000000CA) +#define BF_S0_B_THRB1_INFO(inst) ((inst) + 0x000000CA), 0x00000700 + +#define REG_DFE_CTL11_ADDR(inst) ((inst) + 0x000000CB) +#define BF_S0_B_THRC20_INFO(inst) ((inst) + 0x000000CB), 0x00000700 + +#define REG_DFE_CTL12_ADDR(inst) ((inst) + 0x000000CC) +#define BF_S0_B_THRC21_INFO(inst) ((inst) + 0x000000CC), 0x00000700 + +#define REG_DFE_CTL13_ADDR(inst) ((inst) + 0x000000CD) +#define BF_S1_B_THRB1_INFO(inst) ((inst) + 0x000000CD), 0x00000700 + +#define REG_DFE_CTL14_ADDR(inst) ((inst) + 0x000000CE) +#define BF_S1_B_THRC20_INFO(inst) ((inst) + 0x000000CE), 0x00000700 + +#define REG_DFE_CTL15_ADDR(inst) ((inst) + 0x000000CF) +#define BF_S1_B_THRC21_INFO(inst) ((inst) + 0x000000CF), 0x00000700 + +#define REG_DFE_CTL16_ADDR(inst) ((inst) + 0x000000D0) +#define BF_S0_GM_SWITCH_OFF_VIP_INFO(inst) ((inst) + 0x000000D0), 0x00000500 + +#define REG_DFE_CTL17_ADDR(inst) ((inst) + 0x000000D1) +#define BF_S0_GM_SWITCH_OFF_VIN_INFO(inst) ((inst) + 0x000000D1), 0x00000500 + +#define REG_DFE_CTL18_ADDR(inst) ((inst) + 0x000000D2) +#define BF_S0_PD_CLKGEN_INFO(inst) ((inst) + 0x000000D2), 0x00000100 +#define BF_S0_PD_DAC_THR_INFO(inst) ((inst) + 0x000000D2), 0x00000303 +#define BF_S0_MUX_EN_OVRD_INFO(inst) ((inst) + 0x000000D2), 0x00000206 + +#define REG_DFE_CTL19_ADDR(inst) ((inst) + 0x000000D3) +#define BF_S0_PD_DAC_OFF_INFO(inst) ((inst) + 0x000000D3), 0x00000800 + +#define REG_DFE_CTL20_ADDR(inst) ((inst) + 0x000000D4) +#define BF_S0_B_F0I0_INFO(inst) ((inst) + 0x000000D4), 0x00000500 + +#define REG_DFE_CTL21_ADDR(inst) ((inst) + 0x000000D5) +#define BF_S0_B_F0I1_INFO(inst) ((inst) + 0x000000D5), 0x00000500 + +#define REG_DFE_CTL22_ADDR(inst) ((inst) + 0x000000D6) +#define BF_S0_B_F0I2_INFO(inst) ((inst) + 0x000000D6), 0x00000500 + +#define REG_DFE_CTL23_ADDR(inst) ((inst) + 0x000000D7) +#define BF_S0_B_F0I3_INFO(inst) ((inst) + 0x000000D7), 0x00000500 + +#define REG_DFE_CTL24_ADDR(inst) ((inst) + 0x000000D8) +#define BF_S0_B_F1I0_INFO(inst) ((inst) + 0x000000D8), 0x00000500 + +#define REG_DFE_CTL25_ADDR(inst) ((inst) + 0x000000D9) +#define BF_S0_B_F1I1_INFO(inst) ((inst) + 0x000000D9), 0x00000500 + +#define REG_DFE_CTL26_ADDR(inst) ((inst) + 0x000000DA) +#define BF_S0_B_F1I2_INFO(inst) ((inst) + 0x000000DA), 0x00000500 + +#define REG_DFE_CTL27_ADDR(inst) ((inst) + 0x000000DB) +#define BF_S0_B_F1I3_INFO(inst) ((inst) + 0x000000DB), 0x00000500 + +#define REG_DFE_CTL28_ADDR(inst) ((inst) + 0x000000DC) +#define BF_S0_PD_COMP_F0_INFO(inst) ((inst) + 0x000000DC), 0x00000400 +#define BF_S0_PD_COMP_F1_INFO(inst) ((inst) + 0x000000DC), 0x00000404 + +#define REG_DFE_CTL28X_ADDR(inst) ((inst) + 0x000000DD) +#define BF_S0_USE_COMP23_DATA_INFO(inst) ((inst) + 0x000000DD), 0x00000100 + +#define REG_DFE_CTL29_ADDR(inst) ((inst) + 0x000000E0) +#define BF_S1_GM_SWITCH_OFF_VIP_INFO(inst) ((inst) + 0x000000E0), 0x00000500 + +#define REG_DFE_CTL30_ADDR(inst) ((inst) + 0x000000E1) +#define BF_S1_GM_SWITCH_OFF_VIN_INFO(inst) ((inst) + 0x000000E1), 0x00000500 + +#define REG_DFE_CTL31_ADDR(inst) ((inst) + 0x000000E2) +#define BF_S1_PD_CLKGEN_INFO(inst) ((inst) + 0x000000E2), 0x00000100 +#define BF_S1_PD_DAC_THR_INFO(inst) ((inst) + 0x000000E2), 0x00000303 +#define BF_S1_MUX_EN_OVRD_INFO(inst) ((inst) + 0x000000E2), 0x00000206 + +#define REG_DFE_CTL32_ADDR(inst) ((inst) + 0x000000E3) +#define BF_S1_PD_DAC_OFF_INFO(inst) ((inst) + 0x000000E3), 0x00000800 + +#define REG_DFE_CTL33_ADDR(inst) ((inst) + 0x000000E4) +#define BF_S1_B_F0I0_INFO(inst) ((inst) + 0x000000E4), 0x00000500 + +#define REG_DFE_CTL34_ADDR(inst) ((inst) + 0x000000E5) +#define BF_S1_B_F0I1_INFO(inst) ((inst) + 0x000000E5), 0x00000500 + +#define REG_DFE_CTL35_ADDR(inst) ((inst) + 0x000000E6) +#define BF_S1_B_F0I2_INFO(inst) ((inst) + 0x000000E6), 0x00000500 + +#define REG_DFE_CTL36_ADDR(inst) ((inst) + 0x000000E7) +#define BF_S1_B_F0I3_INFO(inst) ((inst) + 0x000000E7), 0x00000500 + +#define REG_DFE_CTL37_ADDR(inst) ((inst) + 0x000000E8) +#define BF_S1_B_F1I0_INFO(inst) ((inst) + 0x000000E8), 0x00000500 + +#define REG_DFE_CTL38_ADDR(inst) ((inst) + 0x000000E9) +#define BF_S1_B_F1I1_INFO(inst) ((inst) + 0x000000E9), 0x00000500 + +#define REG_DFE_CTL39_ADDR(inst) ((inst) + 0x000000EA) +#define BF_S1_B_F1I2_INFO(inst) ((inst) + 0x000000EA), 0x00000500 + +#define REG_DFE_CTL40_ADDR(inst) ((inst) + 0x000000EB) +#define BF_S1_B_F1I3_INFO(inst) ((inst) + 0x000000EB), 0x00000500 + +#define REG_DFE_CTL41_ADDR(inst) ((inst) + 0x000000EC) +#define BF_S1_PD_COMP_F0_INFO(inst) ((inst) + 0x000000EC), 0x00000400 +#define BF_S1_PD_COMP_F1_INFO(inst) ((inst) + 0x000000EC), 0x00000404 + +#define REG_DFE_CTL41X_ADDR(inst) ((inst) + 0x000000ED) +#define BF_S1_USE_COMP23_DATA_INFO(inst) ((inst) + 0x000000ED), 0x00000100 + +#define REG_DFE_CTL42_ADDR(inst) ((inst) + 0x000000EE) +#define BF_DFE_FB_SUM_INFO(inst) ((inst) + 0x000000EE), 0x00000500 +#define BF_DFE_FB_SUM_OVRD_INFO(inst) ((inst) + 0x000000EE), 0x00000105 + +#define REG_DFE_CTL43_ADDR(inst) ((inst) + 0x000000EF) +#define BF_S0_B_FB4_INFO(inst) ((inst) + 0x000000EF), 0x00000500 +#define BF_S0_PD_FB456_INFO(inst) ((inst) + 0x000000EF), 0x00000107 + +#define REG_DFE_CTL44_ADDR(inst) ((inst) + 0x000000F0) +#define BF_S0_B_FB5_INFO(inst) ((inst) + 0x000000F0), 0x00000500 + +#define REG_DFE_CTL44X_ADDR(inst) ((inst) + 0x000000F1) +#define BF_S0_B_FB6_INFO(inst) ((inst) + 0x000000F1), 0x00000500 + +#define REG_DFE_CTL45_ADDR(inst) ((inst) + 0x000000F2) +#define BF_S1_B_FB4_INFO(inst) ((inst) + 0x000000F2), 0x00000500 +#define BF_S1_PD_FB456_INFO(inst) ((inst) + 0x000000F2), 0x00000107 + +#define REG_DFE_CTL46_ADDR(inst) ((inst) + 0x000000F3) +#define BF_S1_B_FB5_INFO(inst) ((inst) + 0x000000F3), 0x00000500 + +#define REG_DFE_CTL46X_ADDR(inst) ((inst) + 0x000000F4) +#define BF_S1_B_FB6_INFO(inst) ((inst) + 0x000000F4), 0x00000500 + +#define REG_DFE_CTL47_ADDR(inst) ((inst) + 0x000000F5) +#define BF_DFE_STROBE_INFO(inst) ((inst) + 0x000000F5), 0x00000100 + +#define REG_DFE_CTL48_ADDR(inst) ((inst) + 0x000000F6) +#define BF_RSELU_INFO(inst) ((inst) + 0x000000F6), 0x00000300 +#define BF_RSELU_BYPASS_INFO(inst) ((inst) + 0x000000F6), 0x00000103 + +#define REG_DFE_CTL49_ADDR(inst) ((inst) + 0x000000F7) +#define BF_CLKGEN_PD_VAL_SEL_INFO(inst) ((inst) + 0x000000F7), 0x00000200 +#define BF_PD_VCM_INFO(inst) ((inst) + 0x000000F7), 0x00000102 + +#define REG_DFE_CTL50_ADDR(inst) ((inst) + 0x000000F8) +#define BF_S1_DMX_SWP_DIV2_INFO(inst) ((inst) + 0x000000F8), 0x00000100 + +#define REG_DFE_CTL51_ADDR(inst) ((inst) + 0x000000F9) +#define BF_RHO_INFO(inst) ((inst) + 0x000000F9), 0x00000800 + +#define REG_DFE_CTL52_ADDR(inst) ((inst) + 0x000000FA) +#define BF_EN_FLASH_SRC_DES_RC_INFO(inst) ((inst) + 0x000000FA), 0x00000400 +#define BF_EN_FLASH_MASK_DES_RC_INFO(inst) ((inst) + 0x000000FA), 0x00000404 + +#define REG_DFE_CTL53_ADDR(inst) ((inst) + 0x000000FB) +#define BF_PROG_NMAK_REFDAC_INFO(inst) ((inst) + 0x000000FB), 0x00000200 +#define BF_PROG_NMAK_PDAC_INFO(inst) ((inst) + 0x000000FB), 0x00000202 + +#define REG_DFE_CTL54_ADDR(inst) ((inst) + 0x000000FC) +#define BF_S0_PD_GMSW_INFO(inst) ((inst) + 0x000000FC), 0x00000100 +#define BF_S0_SHORT_GMSW_INFO(inst) ((inst) + 0x000000FC), 0x00000101 +#define BF_S1_PD_GMSW_INFO(inst) ((inst) + 0x000000FC), 0x00000102 +#define BF_S1_SHORT_GMSW_INFO(inst) ((inst) + 0x000000FC), 0x00000103 + +#define REG_DIG_REVID_ADDR(inst) ((inst) + 0x000000FE) +#define BF_RX_DIG_REVID_INFO(inst) ((inst) + 0x000000FE), 0x00000800 + +#define REG_ANA_REVID_ADDR(inst) ((inst) + 0x000000FF) +#define BF_RX_ANA_REVID_INFO(inst) ((inst) + 0x000000FF), 0x00000800 + +#endif /* __ADI_APOLLO_BF_SERDES_RXDIG_PHY_CORE1P3_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_serdes_txdig_12pack_apollo_core1p0.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_serdes_txdig_12pack_apollo_core1p0.h new file mode 100644 index 00000000000000..0982a1eea74f28 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_serdes_txdig_12pack_apollo_core1p0.h @@ -0,0 +1,136 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:21 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_SERDES_TXDIG_12PACK_APOLLO_CORE1P0_H__ +#define __ADI_APOLLO_BF_SERDES_TXDIG_12PACK_APOLLO_CORE1P0_H__ + +/*============= D E F I N E S ==============*/ +#define SER_PHY_TOP_12PACK_SERDES_TX_JTX_TOP_RX_DIGITAL0 0x60628000 +#define SER_PHY_TOP_12PACK_SERDES_TX_JTX_TOP_RX_DIGITAL1 0x60E28000 + +#define REG_TXSER_12PACK_CLK_CTL0_ADDR(inst) ((inst) + 0x00000000) +#define BF_SER_CLK_DIV_INFO(inst) ((inst) + 0x00000000), 0x00000200 + +#define REG_TXSER_12PACK_PD_ADDR(inst) ((inst) + 0x00000001) +#define BF_SER_CLK_PD_INFO(inst) ((inst) + 0x00000001), 0x00000100 +#define BF_DES_CLK_PD_INFO(inst) ((inst) + 0x00000001), 0x00000101 +#define BF_SERDES_CLK_PD_INFO(inst) ((inst) + 0x00000001), 0x00000102 + +#define REG_TXSER_12PACK_CLK_PD_ADDR(inst) ((inst) + 0x00000002) +#define BF_TXSER_PD_CLK_RX_INFO(inst) ((inst) + 0x00000002), 0x00000100 + +#define REG_TXSER_12PACK_CLK_CTL1_ADDR(inst) ((inst) + 0x00000003) +#define BF_TEST_CLK_OUTPUT_PD_INFO(inst) ((inst) + 0x00000003), 0x00000104 +#define BF_TEST_CLK_RECEIVER_PD_INFO(inst) ((inst) + 0x00000003), 0x00000105 +#define BF_SEL_EXT_REF_CLK_INFO(inst) ((inst) + 0x00000003), 0x00000106 +#define BF_SER_CLK_DIV_RESETB_INFO(inst) ((inst) + 0x00000003), 0x00000107 + +#define REG_TXSER_12PACK_JTAG_CTL0_ADDR(inst) ((inst) + 0x00000004) +#define BF_TXSER_JTAG_DATA_INV_INFO(inst) ((inst) + 0x00000004), 0x00000C00 + +#define REG_TXSER_12PACK_JTAG_CTL1_ADDR(inst) ((inst) + 0x00000005) + +#define REG_TXSER_12PACK_TEST_CTL_ADDR(inst) ((inst) + 0x00000006) +#define BF_TXSER_EN_SER_TESTV_OUT_INFO(inst) ((inst) + 0x00000006), 0x00000100 + +#define REG_TXSER_12PACK_TEST_CTL2_ADDR(inst) ((inst) + 0x00000007) +#define BF_TEST_CLK_SEL_INFO(inst) ((inst) + 0x00000007), 0x00000300 + +#define REG_TXSER_12PACK_PLL_REF_CTL_ADDR(inst) ((inst) + 0x00000008) +#define BF_PLL_REF_CLK_INFO(inst) ((inst) + 0x00000008), 0x00000800 + +#define REG_TXSER_12PACK_TERM_CAL_CTL0_ADDR(inst) ((inst) + 0x00000010) +#define BF_TERM_CAL_RPOLY_CODE_INFO(inst) ((inst) + 0x00000010), 0x00000600 +#define BF_TERM_CAL_EN_INFO(inst) ((inst) + 0x00000010), 0x00000106 +#define BF_OFFSET32_EN_INFO(inst) ((inst) + 0x00000010), 0x00000107 + +#define REG_TXSER_12PACK_TERM_CAL_CTL1_ADDR(inst) ((inst) + 0x00000011) +#define BF_TERM_CAL_RO_DELAY_INFO(inst) ((inst) + 0x00000011), 0x00000300 +#define BF_TERM_CAL_RO_DIVN_INFO(inst) ((inst) + 0x00000011), 0x00000304 +#define BF_TERM_CAL_RO_FORCE_EN_INFO(inst) ((inst) + 0x00000011), 0x00000107 + +#define REG_TXSER_12PACK_COMP_CTL0_ADDR(inst) ((inst) + 0x00000012) +#define BF_COMP_OUT_INV_INFO(inst) ((inst) + 0x00000012), 0x00000100 +#define BF_COMP_CLK_INV_INFO(inst) ((inst) + 0x00000012), 0x00000101 +#define BF_COMP_SWAP_FORCE_CAL_INFO(inst) ((inst) + 0x00000012), 0x00000102 +#define BF_COMP_CTL_FORCE_INFO(inst) ((inst) + 0x00000012), 0x00000103 + +#define REG_TXSER_12PACK_COMP_CTL1_ADDR(inst) ((inst) + 0x00000013) +#define BF_COMP_CODE_FORCE_INFO(inst) ((inst) + 0x00000013), 0x00000600 + +#define REG_TXSER_12PACK_COMP_CTL2_ADDR(inst) ((inst) + 0x00000014) +#define BF_COMP_0_EN_FORCE_INFO(inst) ((inst) + 0x00000014), 0x00000100 +#define BF_COMP_1_EN_FORCE_INFO(inst) ((inst) + 0x00000014), 0x00000101 +#define BF_COMP_EN_FORCE_INFO(inst) ((inst) + 0x00000014), 0x00000102 +#define BF_COMP_SWAP_FORCE_INFO(inst) ((inst) + 0x00000014), 0x00000103 +#define BF_COMP_CLK_FORCE_INFO(inst) ((inst) + 0x00000014), 0x00000104 + +#define REG_TXSER_12PACK_COMP_STA0_ADDR(inst) ((inst) + 0x00000015) +#define BF_TERM_OFFSET_STA_INFO(inst) ((inst) + 0x00000015), 0x00000400 +#define BF_TERM_CAL_DONE_INFO(inst) ((inst) + 0x00000015), 0x00000104 +#define BF_COMP_OUT_STA_INFO(inst) ((inst) + 0x00000015), 0x00000105 + +#define REG_TXSER_12PACK_COMP_STA1_ADDR(inst) ((inst) + 0x00000016) +#define BF_COMP0A_CODE_STA_INFO(inst) ((inst) + 0x00000016), 0x00000600 + +#define REG_TXSER_12PACK_COMP_STA2_ADDR(inst) ((inst) + 0x00000017) +#define BF_COMP0B_CODE_STA_INFO(inst) ((inst) + 0x00000017), 0x00000600 + +#define REG_TXSER_12PACK_COMP_STA3_ADDR(inst) ((inst) + 0x00000018) +#define BF_COMP1A_CODE_STA_INFO(inst) ((inst) + 0x00000018), 0x00000600 + +#define REG_TXSER_12PACK_COMP_STA4_ADDR(inst) ((inst) + 0x00000019) +#define BF_COMP1B_CODE_STA_INFO(inst) ((inst) + 0x00000019), 0x00000600 + +#define REG_TXSER_12PACK_USR0_ADDR(inst) ((inst) + 0x00000020) +#define BF_TXSER_USR_CTL0_INFO(inst) ((inst) + 0x00000020), 0x00000800 + +#define REG_TXSER_12PACK_USR1_ADDR(inst) ((inst) + 0x00000021) +#define BF_TXSER_USR_CTL1_INFO(inst) ((inst) + 0x00000021), 0x00000800 + +#define REG_TXSER_12PACK_USR2_ADDR(inst) ((inst) + 0x00000022) +#define BF_TXSER_USR_CTL2_INFO(inst) ((inst) + 0x00000022), 0x00000800 + +#define REG_TXSER_12PACK_USR3_ADDR(inst) ((inst) + 0x00000023) +#define BF_TXSER_USR_CTL3_INFO(inst) ((inst) + 0x00000023), 0x00000800 + +#define REG_TXSER_12PACK_USR4_ADDR(inst) ((inst) + 0x00000024) +#define BF_TXSER_USR_CTL4_INFO(inst) ((inst) + 0x00000024), 0x00000800 + +#define REG_TXSER_12PACK_USR5_ADDR(inst) ((inst) + 0x00000025) +#define BF_TXSER_USR_CTL5_INFO(inst) ((inst) + 0x00000025), 0x00000800 + +#define REG_TXSER_12PACK_USR6_ADDR(inst) ((inst) + 0x00000026) +#define BF_TXSER_USR_CTL6_INFO(inst) ((inst) + 0x00000026), 0x00000800 + +#define REG_TXSER_12PACK_USR7_ADDR(inst) ((inst) + 0x00000027) +#define BF_TXSER_USR_CTL7_INFO(inst) ((inst) + 0x00000027), 0x00000800 + +#define REG_TXSER_12PACK_USR8_ADDR(inst) ((inst) + 0x00000028) +#define BF_TXSER_USR_CTL8_INFO(inst) ((inst) + 0x00000028), 0x00000800 + +#define REG_TXSER_12PACK_USR9_ADDR(inst) ((inst) + 0x00000029) +#define BF_TXSER_USR_STA0_INFO(inst) ((inst) + 0x00000029), 0x00000800 + +#define REG_TXSER_12PACK_USR10_ADDR(inst) ((inst) + 0x0000002A) +#define BF_TXSER_USR_STA1_INFO(inst) ((inst) + 0x0000002A), 0x00000800 + +#define REG_TXSER_12PACK_SPARE_ADDR(inst) ((inst) + 0x00000030) +#define BF_SPARE_CTL_SERDES_TXDIG_12PACK_APOLLO__CORE1P0_INFO(inst) ((inst) + 0x00000030), 0x00000800 + +#define REG_TXSER_12PACK_REVID_ADDR(inst) ((inst) + 0x000000FF) +#define BF_TXSER_12PACK_REVID_INFO(inst) ((inst) + 0x000000FF), 0x00000800 + +#endif /* __ADI_APOLLO_BF_SERDES_TXDIG_12PACK_APOLLO_CORE1P0_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_serdes_txdig_dcc_core1p3.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_serdes_txdig_dcc_core1p3.h new file mode 100644 index 00000000000000..b1032566db292d --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_serdes_txdig_dcc_core1p3.h @@ -0,0 +1,85 @@ +/*! + * \brief SPI Register Definition Header File, automatically generated by + * /nobackup/jbirnie/yoda_bb_workdir/yoda2h_v1.3.6 v1.3.6 at 4/21/2021 7:18:45 PM. + * + * \copyright copyright(c) 2018 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_SERDES_TXDIG_DCC_CORE1P3_H__ +#define __ADI_APOLLO_BF_SERDES_TXDIG_DCC_CORE1P3_H__ + +/*============= D E F I N E S ==============*/ +#define SER_PHY_TOP_12PACK_SERDES_TX_JTX_TOP_RX_DIGITAL0 0x60628000 +#define SER_PHY_TOP_12PACK_SERDES_TX_JTX_TOP_RX_DIGITAL1 0x60E28000 + +#define REG_TXSER_12PACK_CLK_CTL_ADDR(inst) ((inst) + 0x00000000) +#define BF_TXSER_TX_PATH_CLK_DIV_INFO(inst) ((inst) + 0x00000000), 0x00000200 + +#define REG_TXSER_12PACK_PD_ADDR(inst) ((inst) + 0x00000001) +#define BF_TXSER_PD_SER_CLK_INFO(inst) ((inst) + 0x00000001), 0x00000100 +#define BF_TXSER_PD_DES_CLK_INFO(inst) ((inst) + 0x00000001), 0x00000101 + +#define REG_TXSER_12PACK_CLK_PD_ADDR(inst) ((inst) + 0x00000002) +#define BF_TXSER_PD_CLK_RX_INFO(inst) ((inst) + 0x00000002), 0x00000100 + +#define REG_TXSER_12PACK_OFFSET_CTL_ADDR(inst) ((inst) + 0x00000003) +#define BF_DRV_RPOLY_CODE_INFO(inst) ((inst) + 0x00000003), 0x00000600 +#define BF_DRV_SLICE_OFFSET_EN_INFO(inst) ((inst) + 0x00000003), 0x00000106 +#define BF_OFFSET32_EN_INFO(inst) ((inst) + 0x00000003), 0x00000107 + +#define REG_TXSER_12PACK_JTAG_CTL0_ADDR(inst) ((inst) + 0x00000004) +#define BF_TXSER_JTAG_DATA_INV_INFO(inst) ((inst) + 0x00000004), 0x00000C00 + +#define REG_TXSER_12PACK_JTAG_CTL1_ADDR(inst) ((inst) + 0x00000005) + +#define REG_TXSER_12PACK_TEST_CTL_ADDR(inst) ((inst) + 0x00000006) +#define BF_TXSER_EN_SER_TESTV_OUT_INFO(inst) ((inst) + 0x00000006), 0x00000100 + +#define REG_TXSER_12PACK_SPARE_ADDR(inst) ((inst) + 0x00000007) +#define BF_SPARE_CTL_SERDES_TXDIG_DCC__CORE1P3_INFO(inst) ((inst) + 0x00000007), 0x00000800 + +#define REG_TXSER_12PACK_USR0_ADDR(inst) ((inst) + 0x00000010) +#define BF_TXSER_USR_CTL0_INFO(inst) ((inst) + 0x00000010), 0x00000800 + +#define REG_TXSER_12PACK_USR1_ADDR(inst) ((inst) + 0x00000011) +#define BF_TXSER_USR_CTL1_INFO(inst) ((inst) + 0x00000011), 0x00000800 + +#define REG_TXSER_12PACK_USR2_ADDR(inst) ((inst) + 0x00000012) +#define BF_TXSER_USR_CTL2_INFO(inst) ((inst) + 0x00000012), 0x00000800 + +#define REG_TXSER_12PACK_USR3_ADDR(inst) ((inst) + 0x00000013) +#define BF_TXSER_USR_CTL3_INFO(inst) ((inst) + 0x00000013), 0x00000800 + +#define REG_TXSER_12PACK_USR4_ADDR(inst) ((inst) + 0x00000014) +#define BF_TXSER_USR_CTL4_INFO(inst) ((inst) + 0x00000014), 0x00000800 + +#define REG_TXSER_12PACK_USR5_ADDR(inst) ((inst) + 0x00000015) +#define BF_TXSER_USR_CTL5_INFO(inst) ((inst) + 0x00000015), 0x00000800 + +#define REG_TXSER_12PACK_USR6_ADDR(inst) ((inst) + 0x00000016) +#define BF_TXSER_USR_CTL6_INFO(inst) ((inst) + 0x00000016), 0x00000800 + +#define REG_TXSER_12PACK_USR7_ADDR(inst) ((inst) + 0x00000017) +#define BF_TXSER_USR_CTL7_INFO(inst) ((inst) + 0x00000017), 0x00000800 + +#define REG_TXSER_12PACK_USR8_ADDR(inst) ((inst) + 0x00000018) +#define BF_TXSER_USR_CTL8_INFO(inst) ((inst) + 0x00000018), 0x00000800 + +#define REG_TXSER_12PACK_USR9_ADDR(inst) ((inst) + 0x00000019) +#define BF_TXSER_USR_STA0_INFO(inst) ((inst) + 0x00000019), 0x00000800 + +#define REG_TXSER_12PACK_USR10_ADDR(inst) ((inst) + 0x0000001A) +#define BF_TXSER_USR_STA1_INFO(inst) ((inst) + 0x0000001A), 0x00000800 + +#define REG_TXSER_12PACK_REVID_ADDR(inst) ((inst) + 0x000000FF) +#define BF_TXSER_12PACK_REVID_INFO(inst) ((inst) + 0x000000FF), 0x00000800 + +#endif /* __ADI_APOLLO_BF_SERDES_TXDIG_DCC_CORE1P3_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_serdes_txdig_phy_core1p2.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_serdes_txdig_phy_core1p2.h new file mode 100644 index 00000000000000..6077bcda1ad2ba --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_serdes_txdig_phy_core1p2.h @@ -0,0 +1,184 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:21 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_SERDES_TXDIG_PHY_CORE1P2_H__ +#define __ADI_APOLLO_BF_SERDES_TXDIG_PHY_CORE1P2_H__ + +/*============= D E F I N E S ==============*/ +#define SER_PHY0_SERDES_TX_JTX_TOP_RX_DIGITAL0 0x60620000 +#define SER_PHY1_SERDES_TX_JTX_TOP_RX_DIGITAL0 0x60620800 +#define SER_PHY2_SERDES_TX_JTX_TOP_RX_DIGITAL0 0x60621000 +#define SER_PHY3_SERDES_TX_JTX_TOP_RX_DIGITAL0 0x60621800 +#define SER_PHY4_SERDES_TX_JTX_TOP_RX_DIGITAL0 0x60622000 +#define SER_PHY5_SERDES_TX_JTX_TOP_RX_DIGITAL0 0x60622800 +#define SER_PHY6_SERDES_TX_JTX_TOP_RX_DIGITAL0 0x60623000 +#define SER_PHY7_SERDES_TX_JTX_TOP_RX_DIGITAL0 0x60623800 +#define SER_PHY8_SERDES_TX_JTX_TOP_RX_DIGITAL0 0x60624000 +#define SER_PHY9_SERDES_TX_JTX_TOP_RX_DIGITAL0 0x60624800 +#define SER_PHY10_SERDES_TX_JTX_TOP_RX_DIGITAL0 0x60625000 +#define SER_PHY11_SERDES_TX_JTX_TOP_RX_DIGITAL0 0x60625800 +#define SER_PHY_ALL_SERDES_TX_JTX_TOP_RX_DIGITAL0 0x60626000 +#define SER_PHY0_SERDES_TX_JTX_TOP_RX_DIGITAL1 0x60E20000 +#define SER_PHY1_SERDES_TX_JTX_TOP_RX_DIGITAL1 0x60E20800 +#define SER_PHY2_SERDES_TX_JTX_TOP_RX_DIGITAL1 0x60E21000 +#define SER_PHY3_SERDES_TX_JTX_TOP_RX_DIGITAL1 0x60E21800 +#define SER_PHY4_SERDES_TX_JTX_TOP_RX_DIGITAL1 0x60E22000 +#define SER_PHY5_SERDES_TX_JTX_TOP_RX_DIGITAL1 0x60E22800 +#define SER_PHY6_SERDES_TX_JTX_TOP_RX_DIGITAL1 0x60E23000 +#define SER_PHY7_SERDES_TX_JTX_TOP_RX_DIGITAL1 0x60E23800 +#define SER_PHY8_SERDES_TX_JTX_TOP_RX_DIGITAL1 0x60E24000 +#define SER_PHY9_SERDES_TX_JTX_TOP_RX_DIGITAL1 0x60E24800 +#define SER_PHY10_SERDES_TX_JTX_TOP_RX_DIGITAL1 0x60E25000 +#define SER_PHY11_SERDES_TX_JTX_TOP_RX_DIGITAL1 0x60E25800 +#define SER_PHY_ALL_SERDES_TX_JTX_TOP_RX_DIGITAL1 0x60E26000 + +#define REG_PWR_DN_ADDR(inst) ((inst) + 0x00000000) +#define BF_PD_SER_INFO(inst) ((inst) + 0x00000000), 0x00000100 + +#define REG_SER_EN_ADDR(inst) ((inst) + 0x00000001) +#define BF_SER_EN_RC_INFO(inst) ((inst) + 0x00000001), 0x00000100 + +#define REG_JTX_SWING_ADDR(inst) ((inst) + 0x00000002) +#define BF_DRVSWING_SER_RC_INFO(inst) ((inst) + 0x00000002), 0x00000300 +#define BF_DRVPOSTEM_SER_RC_INFO(inst) ((inst) + 0x00000002), 0x00000304 + +#define REG_PRE_TAP_LEVEL_ADDR(inst) ((inst) + 0x00000003) +#define BF_DRVPREEM_SER_RC_INFO(inst) ((inst) + 0x00000003), 0x00000800 + +#define REG_GEN_CTL1_ADDR(inst) ((inst) + 0x00000004) +#define BF_RSTB_SER_INFO(inst) ((inst) + 0x00000004), 0x00000100 +#define BF_EN_DRVSLICEOFFSET_SER_RC_INFO(inst) ((inst) + 0x00000004), 0x00000101 +#define BF_DATA_PN_SWAP_CORR_INFO(inst) ((inst) + 0x00000004), 0x00000102 +#define BF_OUTPUTDATAINVERT_SER_RC_INFO(inst) ((inst) + 0x00000004), 0x00000103 +#define BF_PARDATAMODE_SER_RC_INFO(inst) ((inst) + 0x00000004), 0x00000204 +#define BF_LFPATHEN_SER_RC_INFO(inst) ((inst) + 0x00000004), 0x00000106 + +#define REG_PARITY_ERROR_ADDR(inst) ((inst) + 0x00000005) +#define BF_PARITY_ERROR_SER_INFO(inst) ((inst) + 0x00000005), 0x00000100 + +#define REG_PARITY_RST_N_ADDR(inst) ((inst) + 0x00000006) +#define BF_SER_PARITY_RST_N_INFO(inst) ((inst) + 0x00000006), 0x00000100 + +#define REG_CLOCK_CTL_ADDR(inst) ((inst) + 0x00000007) +#define BF_CLKOFFSET_SER_RC_INFO(inst) ((inst) + 0x00000007), 0x00000300 +#define BF_EN_FBCK_SER_RC_INFO(inst) ((inst) + 0x00000007), 0x00000104 +#define BF_FBCKINV_SER_RC_INFO(inst) ((inst) + 0x00000007), 0x00000105 +#define BF_CK66B_INV_SER_RC_INFO(inst) ((inst) + 0x00000007), 0x00000106 + +#define REG_DATA_GEN_CTL_ADDR(inst) ((inst) + 0x00000008) +#define BF_DATA_GEN_MODE_INFO(inst) ((inst) + 0x00000008), 0x00000400 +#define BF_DATA_GEN_EN_INFO(inst) ((inst) + 0x00000008), 0x00000104 + +#define REG_POLY_CODE_ADDR(inst) ((inst) + 0x0000000C) +#define BF_DRVPOLYCODE_SER_RC_INFO(inst) ((inst) + 0x0000000C), 0x00000600 + +#define REG_SYNCA_CTRL_ADDR(inst) ((inst) + 0x0000000D) +#define BF_SYNCA_RX_MODE_RC_INFO(inst) ((inst) + 0x0000000D), 0x00000100 +#define BF_SYNCA_RX_ONCHIP_TERM_RC_INFO(inst) ((inst) + 0x0000000D), 0x00000101 +#define BF_SYNCA_RX_PN_INV_RC_INFO(inst) ((inst) + 0x0000000D), 0x00000102 +#define BF_PD_SYNCA_RX_RC_INFO(inst) ((inst) + 0x0000000D), 0x00000103 + +#define REG_SYNCB_CTRL_ADDR(inst) ((inst) + 0x0000000E) +#define BF_SYNCB_RX_MODE_RC_INFO(inst) ((inst) + 0x0000000E), 0x00000100 +#define BF_SYNCB_RX_ONCHIP_TERM_RC_INFO(inst) ((inst) + 0x0000000E), 0x00000101 +#define BF_SYNCB_RX_PN_INV_RC_INFO(inst) ((inst) + 0x0000000E), 0x00000102 +#define BF_PD_SYNCB_RX_RC_INFO(inst) ((inst) + 0x0000000E), 0x00000103 + +#define REG_JTX_CTRL_ADDR(inst) ((inst) + 0x0000000F) +#define BF_JTAG_EN_SER_TESTMODE_RC_INFO(inst) ((inst) + 0x0000000F), 0x00000100 + +#define REG_DATA_FIR_ADDR(inst) ((inst) + 0x00000010) +#define BF_DATAFIREN_INFO(inst) ((inst) + 0x00000010), 0x00000800 + +#define REG_MAIN_TAP_EN1_ADDR(inst) ((inst) + 0x00000011) +#define BF_MAINTAPEN_INFO(inst) ((inst) + 0x00000011), 0x00001000 + +#define REG_MAIN_TAP_EN2_ADDR(inst) ((inst) + 0x00000012) + +#define REG_MAIN_TAP_MUX1_ADDR(inst) ((inst) + 0x00000013) +#define BF_MAINTAPMUX_INFO(inst) ((inst) + 0x00000013), 0x00001000 + +#define REG_MAIN_TAP_MUX2_ADDR(inst) ((inst) + 0x00000014) + +#define REG_POST_TAP_EN1_ADDR(inst) ((inst) + 0x00000015) +#define BF_POSTTAPEN_INFO(inst) ((inst) + 0x00000015), 0x00000C00 + +#define REG_POST_TAP_EN2_ADDR(inst) ((inst) + 0x00000016) + +#define REG_POST_TAP_MUX1_ADDR(inst) ((inst) + 0x00000017) +#define BF_POSTTAPMUX_INFO(inst) ((inst) + 0x00000017), 0x00000C00 + +#define REG_POST_TAP_MUX2_ADDR(inst) ((inst) + 0x00000018) + +#define REG_PRE_TAP_EN_ADDR(inst) ((inst) + 0x00000019) +#define BF_PRETAPEN_INFO(inst) ((inst) + 0x00000019), 0x00000800 + +#define REG_PRE_TAP_MUX_ADDR(inst) ((inst) + 0x0000001A) +#define BF_PRETAPMUX_INFO(inst) ((inst) + 0x0000001A), 0x00000800 + +#define REG_GEN_CTL2_ADDR(inst) ((inst) + 0x00000020) +#define BF_TAPCTRL_INFO(inst) ((inst) + 0x00000020), 0x00000100 +#define BF_CLKDIV160_EN_INFO(inst) ((inst) + 0x00000020), 0x00000101 +#define BF_CLKDIV8_INV_INFO(inst) ((inst) + 0x00000020), 0x00000102 +#define BF_FIFO_START_ADDR_INFO(inst) ((inst) + 0x00000020), 0x00000304 + +#define REG_SLICE_OFFSET_STA_ADDR(inst) ((inst) + 0x00000021) +#define BF_DRVSLICEENOFFSET_INFO(inst) ((inst) + 0x00000021), 0x00000400 + +#define REG_GEN_CTL3_ADDR(inst) ((inst) + 0x00000023) +#define BF_CLKDIV8_MUX_OUT_INFO(inst) ((inst) + 0x00000023), 0x00000100 + +#define REG_TAP_ERROR_ADDR(inst) ((inst) + 0x00000024) +#define BF_TAPERROR_INFO(inst) ((inst) + 0x00000024), 0x00000100 + +#define REG_SLICE_OFFSET_CTL_ADDR(inst) ((inst) + 0x00000025) +#define BF_SLICEOFFSET_OFFSET_INFO(inst) ((inst) + 0x00000025), 0x00000400 + +#define REG_DATA_FIR_STA_ADDR(inst) ((inst) + 0x00000030) +#define BF_DATAFIREN_STA_INFO(inst) ((inst) + 0x00000030), 0x00000800 + +#define REG_MAIN_TAP_EN_STA1_ADDR(inst) ((inst) + 0x00000031) +#define BF_MAINTAPEN_STA_INFO(inst) ((inst) + 0x00000031), 0x00001000 + +#define REG_MAIN_TAP_EN_STA2_ADDR(inst) ((inst) + 0x00000032) + +#define REG_MAIN_TAP_GEN_STA1_ADDR(inst) ((inst) + 0x00000033) +#define BF_MAINTAPMUX_STA_INFO(inst) ((inst) + 0x00000033), 0x00001000 + +#define REG_MAIN_TAP_GEN_STA2_ADDR(inst) ((inst) + 0x00000034) + +#define REG_POST_TAP_EN_STA1_ADDR(inst) ((inst) + 0x00000035) +#define BF_POSTTAPEN_STA_INFO(inst) ((inst) + 0x00000035), 0x00000C00 + +#define REG_POST_TAP_EN_STA2_ADDR(inst) ((inst) + 0x00000036) + +#define REG_POST_TAP_GEN_STA1_ADDR(inst) ((inst) + 0x00000037) +#define BF_POSTTAPMUX_STA_INFO(inst) ((inst) + 0x00000037), 0x00000C00 + +#define REG_POST_TAP_GEN_STA2_ADDR(inst) ((inst) + 0x00000038) + +#define REG_PRE_TAP_EN_STA_ADDR(inst) ((inst) + 0x00000039) +#define BF_PRETAPEN_STA_INFO(inst) ((inst) + 0x00000039), 0x00000800 + +#define REG_PRE_TAP_GEN_STA2_ADDR(inst) ((inst) + 0x0000003A) +#define BF_PRETAPMUX_STA_INFO(inst) ((inst) + 0x0000003A), 0x00000800 + +#define REG_TX_DIG_REVID_ADDR(inst) ((inst) + 0x0000003E) +#define BF_TX_DIG_REVID_INFO(inst) ((inst) + 0x0000003E), 0x00000800 + +#define REG_TX_REVID_ADDR(inst) ((inst) + 0x0000003F) +#define BF_TX_REVID_INFO(inst) ((inst) + 0x0000003F), 0x00000800 + +#endif /* __ADI_APOLLO_BF_SERDES_TXDIG_PHY_CORE1P2_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_snooper.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_snooper.h new file mode 100644 index 00000000000000..0d3328dbbf6478 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_snooper.h @@ -0,0 +1,61 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:17 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_SNOOPER_H__ +#define __ADI_APOLLO_BF_SNOOPER_H__ + +/*============= D E F I N E S ==============*/ +#define REG_SNOOPER_CTRL_ADDR 0x46700000 +#define BF_SNOOPER_ENABLE_SPI0_DIRECT_WR_INFO 0x46700000, 0x00000100 +#define BF_SNOOPER_ENABLE_SPI0_DIRECT_RD_INFO 0x46700000, 0x00000101 +#define BF_SNOOPER_ENABLE_SPI0_PAGED_WR_INFO 0x46700000, 0x00000102 +#define BF_SNOOPER_ENABLE_SPI0_INDIRECT_WR_INFO 0x46700000, 0x00000103 +#define BF_SNOOPER_ENABLE_SPI0_INDIRECT_RD_INFO 0x46700000, 0x00000104 +#define BF_SNOOPER_ENABLE_SPI1_DIRECT_WR_INFO 0x46700000, 0x00000105 +#define BF_SNOOPER_ENABLE_SPI1_DIRECT_RD_INFO 0x46700000, 0x00000106 +#define BF_SNOOPER_ENABLE_SPI1_PAGED_WR_INFO 0x46700000, 0x00000107 +#define BF_SNOOPER_ENABLE_SPI1_INDIRECT_WR_INFO 0x46700000, 0x00000108 +#define BF_SNOOPER_ENABLE_SPI1_INDIRECT_RD_INFO 0x46700000, 0x00000109 +#define BF_SNOOPER_ADDR_DISABLE_INFO 0x46700000, 0x00000810 +#define BF_SNOOPER_ENABLE_INFO 0x46700000, 0x00000119 + +#define REG_SNOOPER_INTERRUPT_EN_ADDR 0x46700004 +#define BF_SNOOPER_STAT_INTR_EN_INFO 0x46700004, 0x00000100 +#define BF_SNOOPER_OVR_INTR_EN_INFO 0x46700004, 0x00000101 + +#define REG_SNOOPER_REGION_START_ADDR(n) (0x46700008 + 4 * (n)) +#define BF_SNOOPER_REGION_START_INFO(n) (0x46700008 + 4 * (n)), 0x00002000 + +#define REG_SNOOPER_REGION_STOP_ADDR(n) (0x4670002C + 4 * (n)) +#define BF_SNOOPER_REGION_STOP_INFO(n) (0x4670002C + 4 * (n)), 0x00002000 + +#define REG_SNOOPED_ADDR_ADDR 0x4670004C +#define BF_ADDRESS_SNOOPED_INFO 0x4670004C, 0x00002000 + +#define REG_SNOOPED_DATA_ADDR 0x46700050 +#define BF_DATA_SNOOPED_INFO 0x46700050, 0x00002000 + +#define REG_SNOOPED_CTRL_ADDR 0x46700054 +#define BF_DIR_SNOOPED_INFO 0x46700054, 0x00000100 +#define BF_MASTER_ID_SNOOPED_INFO 0x46700054, 0x00000301 +#define BF_SIZE_SNOOPED_INFO 0x46700054, 0x00000204 +#define BF_CTRL_REG_REDUNDANT_BIT_FIELDS_INFO 0x46700054, 0x00001A06 + +#define REG_SNOOPER_STATUS_ADDR 0x4670005C +#define BF_SNOOPER_EMPTY_INFO 0x4670005C, 0x00000100 +#define BF_SNOOPER_FULL_INFO 0x4670005C, 0x00000101 +#define BF_SNOOPER_OVERFLOW_INFO 0x4670005C, 0x00000102 + +#endif /* __ADI_APOLLO_BF_SNOOPER_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_spi_master.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_spi_master.h new file mode 100644 index 00000000000000..922787905a6c52 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_spi_master.h @@ -0,0 +1,139 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:17 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_SPI_MASTER_H__ +#define __ADI_APOLLO_BF_SPI_MASTER_H__ + +/*============= D E F I N E S ==============*/ +#ifdef USE_PRIVATE_BF +#define REG_STAT_SPI_MASTER_ADDR 0x46200000 +#define BF_IRQ_INFO 0x46200000, 0x00000100 +#define BF_XFRDONE_INFO 0x46200000, 0x00000101 +#define BF_TXEMPTY_INFO 0x46200000, 0x00000102 +#define BF_TXDONE_INFO 0x46200000, 0x00000103 +#define BF_TXUNDR_INFO 0x46200000, 0x00000104 +#define BF_TXIRQ_INFO 0x46200000, 0x00000105 +#define BF_RXIRQ_INFO 0x46200000, 0x00000106 +#define BF_RXOVR_INFO 0x46200000, 0x00000107 +#define BF_CS_INFO 0x46200000, 0x0000010B +#define BF_CSERR_INFO 0x46200000, 0x0000010C +#define BF_CSFALL_INFO 0x46200000, 0x0000010D +#define BF_CSRISE_INFO 0x46200000, 0x0000010E +#define BF_RDY_INFO 0x46200000, 0x0000010F +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_RX_ADDR 0x46200004 +#define BF_RX_BYTE1_INFO 0x46200004, 0x00000800 +#define BF_RX_BYTE2_INFO 0x46200004, 0x00000808 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TX_ADDR 0x46200008 +#define BF_TX_BYTE1_INFO 0x46200008, 0x00000800 +#define BF_TX_BYTE2_INFO 0x46200008, 0x00000808 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_DIV_ADDR 0x4620000C +#define BF_DIV_VALUE_INFO 0x4620000C, 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CTL_SPI_MASTER_ADDR 0x46200010 +#define BF_SPIEN_INFO 0x46200010, 0x00000100 +#define BF_MASEN_INFO 0x46200010, 0x00000101 +#define BF_CPHA_INFO 0x46200010, 0x00000102 +#define BF_CPOL_INFO 0x46200010, 0x00000103 +#define BF_WOM_INFO 0x46200010, 0x00000104 +#define BF_LSB_INFO 0x46200010, 0x00000105 +#define BF_TIM_INFO 0x46200010, 0x00000106 +#define BF_ZEN_INFO 0x46200010, 0x00000107 +#define BF_RXOF_INFO 0x46200010, 0x00000108 +#define BF_OEN_INFO 0x46200010, 0x00000109 +#define BF_LOOPBACK_INFO 0x46200010, 0x0000010A +#define BF_CON_INFO 0x46200010, 0x0000010B +#define BF_RFLUSH_INFO 0x46200010, 0x0000010C +#define BF_TFLUSH_INFO 0x46200010, 0x0000010D +#define BF_CSRST_INFO 0x46200010, 0x0000010E +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_IEN_ADDR 0x46200014 +#define BF_IRQMODE_INFO 0x46200014, 0x00000300 +#define BF_CS_INTEN_INFO 0x46200014, 0x00000108 +#define BF_TXUNDR_INTEN_INFO 0x46200014, 0x00000109 +#define BF_RXOVR_INTEN_INFO 0x46200014, 0x0000010A +#define BF_RDY_INTEN_INFO 0x46200014, 0x0000010B +#define BF_TXDONE_INTEN_INFO 0x46200014, 0x0000010C +#define BF_XFRDONE_INTEN_INFO 0x46200014, 0x0000010D +#define BF_TXEMPTY_INTEN_INFO 0x46200014, 0x0000010E +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CNT_ADDR 0x46200018 +#define BF_CNT_VALUE_INFO 0x46200018, 0x00000E00 +#define BF_FRAMECONT_INFO 0x46200018, 0x0000010F +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_DMA_ADDR 0x4620001C +#define BF_EN_SPI_MASTER_INFO 0x4620001C, 0x00000100 +#define BF_TXEN_INFO 0x4620001C, 0x00000101 +#define BF_RXEN_INFO 0x4620001C, 0x00000102 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FIFO_STAT_ADDR 0x46200020 +#define BF_TX_INFO 0x46200020, 0x00000400 +#define BF_RX_INFO 0x46200020, 0x00000408 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_RD_CTL_ADDR 0x46200024 +#define BF_CMDEN_INFO 0x46200024, 0x00000100 +#define BF_OVERLAP_INFO 0x46200024, 0x00000101 +#define BF_TXBYTES_INFO 0x46200024, 0x00000402 +#define BF_THREEPIN_INFO 0x46200024, 0x00000108 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FLOW_CTL_ADDR 0x46200028 +#define BF_MODE_SPI_MASTER_INFO 0x46200028, 0x00000200 +#define BF_RDYPOL_INFO 0x46200028, 0x00000104 +#define BF_RDBURSTSZ_INFO 0x46200028, 0x00000A06 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_WAIT_TMR_ADDR 0x4620002C +#define BF_WAIT_VALUE_INFO 0x4620002C, 0x00001000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CS_CTL_ADDR 0x46200030 +#define BF_SEL_INFO 0x46200030, 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CS_OVERRIDE_ADDR 0x46200034 +#define BF_CTL_INFO 0x46200034, 0x00000200 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_XFR_CNT_ADDR 0x46200038 +#define BF_BYTES_INFO 0x46200038, 0x00000E00 +#endif /* USE_PRIVATE_BF */ + +#endif /* __ADI_APOLLO_BF_SPI_MASTER_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_spi_pm_key.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_spi_pm_key.h new file mode 100644 index 00000000000000..e16c3de21da688 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_spi_pm_key.h @@ -0,0 +1,26 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:17 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_SPI_PM_KEY_H__ +#define __ADI_APOLLO_BF_SPI_PM_KEY_H__ + +/*============= D E F I N E S ==============*/ +#define CORE_0_SPI_PM_KEY 0x41100000 +#define DEBUG_KEY_REGS 0x46810100 + +#define REG_KEY_ADDR_ADDR(inst) ((inst) + 0x00000000) +#define BF_PMEM_KEY_INFO(inst) ((inst) + 0x00000000), 0x00002000 + +#endif /* __ADI_APOLLO_BF_SPI_PM_KEY_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_streamproc.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_streamproc.h new file mode 100644 index 00000000000000..1d4773a48b30ed --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_streamproc.h @@ -0,0 +1,197 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:17 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_STREAMPROC_H__ +#define __ADI_APOLLO_BF_STREAMPROC_H__ + +/*============= D E F I N E S ==============*/ +#define MAIN_STREAM_PROC 0x46B00000 +#define RX_STREAM_PROC_RX_SLICE_0_RX_DIGITAL0 0x6037B000 +#define RX_STREAM_PROC_RX_SLICE_1_RX_DIGITAL0 0x6057B000 +#define RX_STREAM_PROC_RX_SLICE_0_RX_DIGITAL1 0x60B7B000 +#define RX_STREAM_PROC_RX_SLICE_1_RX_DIGITAL1 0x60D7B000 +#define TX_STREAM_PROC_TX_SLICE_0_TX_DIGITAL0 0x6133C000 +#define TX_STREAM_PROC_TX_SLICE_1_TX_DIGITAL0 0x6153C000 +#define TX_STREAM_PROC_TX_SLICE_0_TX_DIGITAL1 0x61B3C000 +#define TX_STREAM_PROC_TX_SLICE_1_TX_DIGITAL1 0x61D3C000 + +#define REG_SP_TRIGGER_STREAM_ADDR(inst) ((inst) + 0x00000000) +#define BF_STREAM_NUMBER_INFO(inst) ((inst) + 0x00000000), 0x00000800 +#define BF_TRIGGER_STREAM_INFO(inst) ((inst) + 0x00000000), 0x0000011E +#define BF_STREAM_ERROR_STREAMPROC_INFO(inst) ((inst) + 0x00000000), 0x0000011F + +#define REG_SP_DBG_CTL_ADDR(inst) ((inst) + 0x00000004) +#define BF_DBG_EN_STREAMPROC_INFO(inst) ((inst) + 0x00000004), 0x00000100 +#define BF_DBG_MODE_INFO(inst) ((inst) + 0x00000004), 0x00000201 +#define BF_DBG_TRIG_MODE_INFO(inst) ((inst) + 0x00000004), 0x00000304 +#define BF_DBG_IRQ_MASK_INFO(inst) ((inst) + 0x00000004), 0x00000108 +#define BF_DBG_RDBK_MODE_INFO(inst) ((inst) + 0x00000004), 0x00000109 +#define BF_DBG_HALT_RESUME_MASK_INFO(inst) ((inst) + 0x00000004), 0x0000010C + +#define REG_SP_DBG_HALT_CTL_ADDR(inst) ((inst) + 0x00000008) +#define BF_STREAM_HALT_INFO(inst) ((inst) + 0x00000008), 0x00000100 +#define BF_STREAM_RESUME_INFO(inst) ((inst) + 0x00000008), 0x00000101 + +#define REG_SP_DBG_RDBK_CTL_ADDR(inst) ((inst) + 0x0000000C) +#define BF_DBG_RDBK_STICKY_INFO(inst) ((inst) + 0x0000000C), 0x00000100 + +#define REG_SP_BKPT_PC_VAL_ADDR(inst) ((inst) + 0x00000010) +#define BF_BKPT_PC_VAL_INFO(inst) ((inst) + 0x00000010), 0x00001000 + +#define REG_SP_ERRORED_STREAM_NUM_ADDR(inst) ((inst) + 0x00000014) +#define BF_ERRORED_STREAM_NUMBER_INFO(inst) ((inst) + 0x00000014), 0x00000800 + +#define REG_SP_RDBK_BKPT_PC_ADDR(inst) ((inst) + 0x00000018) +#define BF_RDBK_BKPT_PC_INFO(inst) ((inst) + 0x00000018), 0x00001000 + +#define REG_SP_RDBK_CURR_PC_ADDR(inst) ((inst) + 0x0000001C) +#define BF_RDBK_CURR_PC_INFO(inst) ((inst) + 0x0000001C), 0x00001000 + +#define REG_SP_RDBK_INSTR1_INSTR2_ADDR(inst) ((inst) + 0x00000020) +#define BF_RDBK_INSTR1_INFO(inst) ((inst) + 0x00000020), 0x00000800 +#define BF_RDBK_INSTR2_INFO(inst) ((inst) + 0x00000020), 0x00000808 +#define BF_RDBK_DUAL_ISSUE_INFO(inst) ((inst) + 0x00000020), 0x00000110 + +#define REG_SP_RDBK_ERROR_VAL_ADDR(inst) ((inst) + 0x00000024) +#define BF_RDBK_ERROR_VAL_INFO(inst) ((inst) + 0x00000024), 0x00000A00 + +#define REG_SP_RDBK_R0_ADDR(inst) ((inst) + 0x00000028) +#define BF_RDBK_R0_INFO(inst) ((inst) + 0x00000028), 0x00002000 + +#define REG_SP_RDBK_R1_ADDR(inst) ((inst) + 0x0000002C) +#define BF_RDBK_R1_INFO(inst) ((inst) + 0x0000002C), 0x00002000 + +#define REG_SP_RDBK_R2_ADDR(inst) ((inst) + 0x00000030) +#define BF_RDBK_R2_INFO(inst) ((inst) + 0x00000030), 0x00002000 + +#define REG_SP_RDBK_R3_ADDR(inst) ((inst) + 0x00000034) +#define BF_RDBK_R3_INFO(inst) ((inst) + 0x00000034), 0x00002000 + +#define REG_SP_RDBK_R4_ADDR(inst) ((inst) + 0x00000038) +#define BF_RDBK_R4_INFO(inst) ((inst) + 0x00000038), 0x00002000 + +#define REG_SP_RDBK_R5_ADDR(inst) ((inst) + 0x0000003C) +#define BF_RDBK_R5_INFO(inst) ((inst) + 0x0000003C), 0x00002000 + +#define REG_SP_RDBK_R6_ADDR(inst) ((inst) + 0x00000040) +#define BF_RDBK_R6_INFO(inst) ((inst) + 0x00000040), 0x00002000 + +#define REG_SP_RDBK_R7_ADDR(inst) ((inst) + 0x00000044) +#define BF_RDBK_R7_INFO(inst) ((inst) + 0x00000044), 0x00002000 + +#define REG_SP_RDBK_RSEG_ADDR(inst) ((inst) + 0x00000048) +#define BF_RDBK_RSEG_INFO(inst) ((inst) + 0x00000048), 0x00001000 + +#define REG_SP_RDBK_TIMEOUT_COUNT_ADDR(inst) ((inst) + 0x0000004C) +#define BF_TIMEOUT_TIMER_COUNT_INFO(inst) ((inst) + 0x0000004C), 0x00001000 + +#define REG_SP_RDBK_LAST_EXECUTED_STREAM_ADDR(inst) ((inst) + 0x00000050) +#define BF_RDBK_LAST_EXECUTED_STREAM_INFO(inst) ((inst) + 0x00000050), 0x00000800 + +#define REG_SP_AHB_CTL_ADDR(inst) ((inst) + 0x00000054) +#define BF_HRESP_MASK_INFO(inst) ((inst) + 0x00000054), 0x00000100 +#define BF_POSTED_HRESP_MASK_INFO(inst) ((inst) + 0x00000054), 0x00000101 + +#define REG_SP_DCACHE_RD_DATA1_ADDR(inst) ((inst) + 0x00000058) +#define BF_RDBK_DCACHE_RD_DATA1_INFO(inst) ((inst) + 0x00000058), 0x00002000 + +#define REG_SP_DCACHE_RD_DATA2_ADDR(inst) ((inst) + 0x0000005C) +#define BF_RDBK_DCACHE_RD_DATA2_INFO(inst) ((inst) + 0x0000005C), 0x00001000 + +#define REG_SP_PREV_CURR_PC_N_RD_DATA2_ADDR(inst, n) ((inst) + 0x00000060 + 4 * (n)) +#define BF_PREV_CURR_PC_INFO(inst, n) ((inst) + 0x00000060 + 4 * (n)), 0x00001000 +#define BF_PREV_DCACHE_RD_DATA2_INFO(inst, n) ((inst) + 0x00000060 + 4 * (n)), 0x00001010 + +#define REG_SP_PREV_DCACHE_RD_DATA1_ADDR(inst, n) ((inst) + 0x00000070 + 4 * (n)) +#define BF_PREV_DCACHE_RD_DATA1_INFO(inst, n) ((inst) + 0x00000070 + 4 * (n)), 0x00002000 + +#define REG_SP_PREV_INSTR1_INSTR2_ADDR(inst, n) ((inst) + 0x00000080 + 4 * (n)) +#define BF_PREV_INSTR1_INFO(inst, n) ((inst) + 0x00000080 + 4 * (n)), 0x00000800 +#define BF_PREV_INSTR2_INFO(inst, n) ((inst) + 0x00000080 + 4 * (n)), 0x00000808 +#define BF_PREV_DUAL_ISSUE_INFO(inst, n) ((inst) + 0x00000080 + 4 * (n)), 0x00000110 + +#define REG_SP_PREV_R0_ADDR(inst, n) ((inst) + 0x00000090 + 4 * (n)) +#define BF_PREV_R0_INFO(inst, n) ((inst) + 0x00000090 + 4 * (n)), 0x00002000 + +#define REG_SP_PREV_R1_ADDR(inst, n) ((inst) + 0x000000A0 + 4 * (n)) +#define BF_PREV_R1_INFO(inst, n) ((inst) + 0x000000A0 + 4 * (n)), 0x00002000 + +#define REG_SP_PREV_R2_ADDR(inst, n) ((inst) + 0x000000B0 + 4 * (n)) +#define BF_PREV_R2_INFO(inst, n) ((inst) + 0x000000B0 + 4 * (n)), 0x00002000 + +#define REG_SP_PREV_R3_ADDR(inst, n) ((inst) + 0x000000C0 + 4 * (n)) +#define BF_PREV_R3_INFO(inst, n) ((inst) + 0x000000C0 + 4 * (n)), 0x00002000 + +#define REG_SP_PREV_R4_ADDR(inst, n) ((inst) + 0x000000D0 + 4 * (n)) +#define BF_PREV_R4_INFO(inst, n) ((inst) + 0x000000D0 + 4 * (n)), 0x00002000 + +#define REG_SP_PREV_R5_ADDR(inst, n) ((inst) + 0x000000E0 + 4 * (n)) +#define BF_PREV_R5_INFO(inst, n) ((inst) + 0x000000E0 + 4 * (n)), 0x00002000 + +#define REG_SP_PREV_R6_ADDR(inst, n) ((inst) + 0x000000F0 + 4 * (n)) +#define BF_PREV_R6_INFO(inst, n) ((inst) + 0x000000F0 + 4 * (n)), 0x00002000 + +#define REG_SP_PREV_R7_ADDR(inst, n) ((inst) + 0x00000100 + 4 * (n)) +#define BF_PREV_R7_INFO(inst, n) ((inst) + 0x00000100 + 4 * (n)), 0x00002000 + +#define REG_SP_PREV_RSEG_N_TIMEOUT_VAL_ADDR(inst, n) ((inst) + 0x00000110 + 4 * (n)) +#define BF_PREV_RSEG_INFO(inst, n) ((inst) + 0x00000110 + 4 * (n)), 0x00001000 +#define BF_PREV_TIMEOUT_TIMER_COUNT_INFO(inst, n) ((inst) + 0x00000110 + 4 * (n)), 0x00001010 + +#define REG_SP_TIMER_EVENT_STATUS_ADDR(inst) ((inst) + 0x00000120) +#define BF_EXTERNAL_TIMER_STATUS_INFO(inst) ((inst) + 0x00000120), 0x00000800 +#define BF_FIFO_EVENTS_PENDING_INFO(inst) ((inst) + 0x00000120), 0x00000808 + +#define REG_SP_AHB_FETCH_ADDR_ADDR(inst) ((inst) + 0x00000124) +#define BF_AHB_FETCH_ADDR_INFO(inst) ((inst) + 0x00000124), 0x00002000 + +#define REG_SP_REGBUS_ADDR_ADDR(inst) ((inst) + 0x00000128) +#define BF_REGBUS_ADDR_INFO(inst) ((inst) + 0x00000128), 0x00002000 + +#define REG_SP_REGBUS_SIZE_ADDR(inst) ((inst) + 0x0000012C) +#define BF_REGBUS_SIZE_INFO(inst) ((inst) + 0x0000012C), 0x00000100 + +#define REG_SP_PREV_TIMER_EVENT_STATUS_ADDR(inst, n) ((inst) + 0x00000130 + 4 * (n)) +#define BF_PREV_EXTERNAL_TIMER_STATUS_INFO(inst, n) ((inst) + 0x00000130 + 4 * (n)), 0x00000800 +#define BF_PREV_FIFO_EVENTS_PENDING_INFO(inst, n) ((inst) + 0x00000130 + 4 * (n)), 0x00000808 + +#define REG_SP_PREV_AHB_FETCH_ADDR_ADDR(inst, n) ((inst) + 0x00000140 + 4 * (n)) +#define BF_PREV_AHB_FETCH_ADDR_INFO(inst, n) ((inst) + 0x00000140 + 4 * (n)), 0x00002000 + +#define REG_SP_PREV_REGBUS_ADDR_ADDR(inst, n) ((inst) + 0x00000150 + 4 * (n)) +#define BF_PREV_REGBUS_ADDR_INFO(inst, n) ((inst) + 0x00000150 + 4 * (n)), 0x00002000 + +#define REG_SP_PREV_REGBUS_SIZE_ADDR(inst, n) ((inst) + 0x00000160 + 4 * (n)) +#define BF_PREV_REGBUS_SIZE_INFO(inst, n) ((inst) + 0x00000160 + 4 * (n)), 0x00000100 + +#define REG_SP_EVENT_MISS_ADDR(inst) ((inst) + 0x00000170) +#define BF_EVENT_MISS_IRQ_MASK_INFO(inst) ((inst) + 0x00000170), 0x00000100 + +#define REG_SP_EVENT_MISS_STATUS0_ADDR(inst) ((inst) + 0x00000174) +#define BF_EVENT_MISS0_INFO(inst) ((inst) + 0x00000174), 0x00002000 + +#define REG_SP_EVENT_MISS_STATUS1_ADDR(inst) ((inst) + 0x00000178) +#define BF_EVENT_MISS1_INFO(inst) ((inst) + 0x00000178), 0x00002000 + +#define REG_SP_EVENT_MISS_STATUS2_ADDR(inst) ((inst) + 0x0000017C) +#define BF_EVENT_MISS2_INFO(inst) ((inst) + 0x0000017C), 0x00002000 + +#define REG_SP_EVENT_MISS_STATUS3_ADDR(inst) ((inst) + 0x00000180) +#define BF_EVENT_MISS3_INFO(inst) ((inst) + 0x00000180), 0x00002000 + +#define REG_SP_CALL_FUNC_TRACE_ADDR(inst) ((inst) + 0x00000184) +#define BF_CALL_FUNC_TRACE_INFO(inst) ((inst) + 0x00000184), 0x00000100 + +#endif /* __ADI_APOLLO_BF_STREAMPROC_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_streamproc_channel.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_streamproc_channel.h new file mode 100644 index 00000000000000..6d0304645003d6 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_streamproc_channel.h @@ -0,0 +1,77 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:21 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_STREAMPROC_CHANNEL_H__ +#define __ADI_APOLLO_BF_STREAMPROC_CHANNEL_H__ + +/*============= D E F I N E S ==============*/ +#define RX_STREAM_PROC_CHANNEL_RX_SLICE_0_RX_DIGITAL0 0x6037C000 +#define RX_STREAM_PROC_CHANNEL_RX_SLICE_1_RX_DIGITAL0 0x6057C000 +#define RX_STREAM_PROC_CHANNEL_RX_SLICE_0_RX_DIGITAL1 0x60B7C000 +#define RX_STREAM_PROC_CHANNEL_RX_SLICE_1_RX_DIGITAL1 0x60D7C000 +#define TX_STREAM_PROC_CHANNEL_TX_SLICE_0_TX_DIGITAL0 0x6133D000 +#define TX_STREAM_PROC_CHANNEL_TX_SLICE_1_TX_DIGITAL0 0x6153D000 +#define TX_STREAM_PROC_CHANNEL_TX_SLICE_0_TX_DIGITAL1 0x61B3D000 +#define TX_STREAM_PROC_CHANNEL_TX_SLICE_1_TX_DIGITAL1 0x61D3D000 + +#ifdef USE_PRIVATE_BF +#define REG_STREAM_CONFIG_0_ADDR(inst) ((inst) + 0x00000000) +#define BF_STREAM_ECC_ERROR_CLEAR_INFO(inst) ((inst) + 0x00000000), 0x00000100 +#define BF_CH_RISE_STREAM_ERROR_INFO(inst) ((inst) + 0x00000000), 0x00000104 +#define BF_STREAM_ECC_ERROR_SENSITIVITY_INFO(inst) ((inst) + 0x00000000), 0x00000108 +#define BF_STREAM_PROC_ADDR_STREAMPROC_CHANNEL_INFO(inst) ((inst) + 0x00000000), 0x0000040C +#define BF_STREAM_RESET_STREAMPROC_CHANNEL_INFO(inst) ((inst) + 0x00000000), 0x00000110 +#define BF_RUN_STREAM_NUM_INFO(inst) ((inst) + 0x00000000), 0x00000818 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_STREAM_CONFIG_1_ADDR(inst) ((inst) + 0x00000004) +#define BF_STREAM_BASE_STREAMPROC_CHANNEL_INFO(inst) ((inst) + 0x00000004), 0x00001000 +#define BF_LAST_STREAM_NUM_STREAMPROC_CHANNEL_INFO(inst) ((inst) + 0x00000004), 0x00000810 +#define BF_MASK_CH_RISE_STREAM_TO_CORE_INFO(inst) ((inst) + 0x00000004), 0x00000118 +#define BF_STREAM_PROC_RDEN_STREAMPROC_CHANNEL_INFO(inst) ((inst) + 0x00000004), 0x0000011C +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_STREAM_CONFIG_2_ADDR(inst) ((inst) + 0x00000008) +#define BF_COMPLETED_STREAM_NUM_STREAMPROC_CHANNEL_INFO(inst) ((inst) + 0x00000008), 0x00000800 +#define BF_CH_FALL_STREAM_ERROR_INFO(inst) ((inst) + 0x00000008), 0x00000108 +#define BF_STREAM_ECC_ENABLE_INFO(inst) ((inst) + 0x00000008), 0x0000010C +#define BF_STREAM_ECC_ERROR_INFO(inst) ((inst) + 0x00000008), 0x00000110 +#define BF_CH_ENABLE_READBACK_INFO(inst) ((inst) + 0x00000008), 0x00000114 +#define BF_MASK_CH_FALL_STREAM_TO_CORE_INFO(inst) ((inst) + 0x00000008), 0x00000118 +#define BF_STREAM_ERROR_STREAMPROC_CHANNEL_INFO(inst) ((inst) + 0x00000008), 0x0000011C +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_STREAM_CONFIG_3_ADDR(inst) ((inst) + 0x0000000C) +#define BF_STREAM_ECC_ERROR_TAG_INFO(inst) ((inst) + 0x0000000C), 0x00000C00 +#define BF_MASK_CH_ANT_RISE_STREAM_TO_CORE_INFO(inst) ((inst) + 0x0000000C), 0x0000010C +#define BF_MASK_CH_ANT_FALL_STREAM_TO_CORE_INFO(inst) ((inst) + 0x0000000C), 0x00000110 +#define BF_CH_ENABLE_PIN_INVERT_INFO(inst) ((inst) + 0x0000000C), 0x00000114 +#define BF_CH_ANT_ENABLE_PIN_INVERT_INFO(inst) ((inst) + 0x0000000C), 0x00000118 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_STREAM_PROC_READBACK_DATA_ADDR(inst) ((inst) + 0x00000010) +#define BF_STREAM_PROC_DATA_STREAMPROC_CHANNEL_INFO(inst) ((inst) + 0x00000010), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_STREAM_PROC_SCRATCH_ADDR(inst, n) ((inst) + 0x00000014 + 4 * (n)) +#define BF_STREAM_SCRATCH_INFO(inst, n) ((inst) + 0x00000014 + 4 * (n)), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#endif /* __ADI_APOLLO_BF_STREAMPROC_CHANNEL_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_telemetry.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_telemetry.h new file mode 100644 index 00000000000000..999e55fe037cfb --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_telemetry.h @@ -0,0 +1,110 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:17 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_TELEMETRY_H__ +#define __ADI_APOLLO_BF_TELEMETRY_H__ + +/*============= D E F I N E S ==============*/ +#define REG_TELEMETRY_CTRL_ADDR 0x46400000 +#define BF_TELEMETRY_MODES_INFO 0x46400000, 0x00000200 +#define BF_TELEMETRY_ENABLE_INFO 0x46400000, 0x00000108 + +#define REG_TELEMETRY_SOURCE_FILTER0_ADDR 0x46400004 +#define BF_TELEMETRY_RX_FILTER_INFO 0x46400004, 0x00000800 + +#define REG_TELEMETRY_SOURCE_FILTER1_ADDR 0x46400008 +#define BF_TELEMETRY_TX_FILTER_INFO 0x46400008, 0x00000800 + +#define REG_TELEMETRY_SOURCE_FILTER2_ADDR 0x4640000C +#define BF_TELEMETRY_ORX_FILTER_INFO 0x4640000C, 0x00000200 + +#define REG_TELEMETRY_SOURCE_FILTER3_ADDR 0x46400010 +#define BF_TELEMETRY_RESTOFALL_FILTER_INFO 0x46400010, 0x00000500 +#define BF_TELEMETRY_INVALID_DATA_FILTER_INFO 0x46400010, 0x00000105 +#define BF_TELEMETRY_KFA_MPU_START_FILTER_INFO 0x46400010, 0x00000806 +#define BF_TELEMETRY_KFA_MPU_DONE_FILTER_INFO 0x46400010, 0x0000080E +#define BF_TELEMETRY_KFA_STREAM_FILTER_INFO 0x46400010, 0x00000116 + +#define REG_TELEMETRY_EVENT_FILTER0_ADDR 0x46400014 +#define BF_TELEMETRY_RX_EVENT_FILTER_INFO 0x46400014, 0x00000300 + +#define REG_TELEMETRY_EVENT_FILTER1_ADDR 0x46400018 +#define BF_TELEMETRY_TX_EVENT_FILTER_INFO 0x46400018, 0x00000300 + +#define REG_TELEMETRY_EVENT_FILTER2_ADDR 0x4640001C +#define BF_TELEMETRY_ORX_EVENT_FILTER_INFO 0x4640001C, 0x00000300 + +#define REG_TELEMETRY_EVENT_FILTER3_ADDR 0x46400020 +#define BF_TELEMETRY_CORE_EVENT_FILTER_INFO 0x46400020, 0x00000800 + +#define REG_TELEMETRY_TS_MASK_ADDR 0x46400024 +#define BF_TELEMETRY_TS_MASK_BITS_INFO 0x46400024, 0x00000300 + +#define REG_TELEMETRY_CORE0_WRDATA_ADDR 0x46400028 +#define BF_TELEMETRY_CORE0_WRDATA_INFO 0x46400028, 0x00002000 + +#define REG_TELEMETRY_CORE1_WRDATA_ADDR 0x4640002C +#define BF_TELEMETRY_CORE1_WRDATA_INFO 0x4640002C, 0x00002000 + +#define REG_TELEMETRY_STREAMPROC_WRDATA_ADDR 0x46400030 +#define BF_TELEMETRY_STREAMPROC_WRDATA_INFO 0x46400030, 0x00002000 + +#define REG_TELEMETRY_CORE0_WRDATA_WO_TS_ADDR 0x46400034 +#define BF_TELEMETRY_CORE0_WRDATA_WO_TS_INFO 0x46400034, 0x00002000 + +#define REG_TELEMETRY_CORE1_WRDATA_WO_TS_ADDR 0x46400038 +#define BF_TELEMETRY_CORE1_WRDATA_WO_TS_INFO 0x46400038, 0x00002000 + +#define REG_TELEMETRY_STREAMPROC_WRDATA_WO_TS_ADDR 0x4640003C +#define BF_TELEMETRY_STREAMPROC_WRDATA_WO_TS_INFO 0x4640003C, 0x00002000 + +#define REG_TELEMETRY_STREAM_OVERFLOW_STATUS_WO_SEQFIFO_REG_ADDR 0x46400040 +#define BF_TELEMETRY_STREAM_OVR_BITS_WITH_NO_SEQFIFO_OVR_INFO 0x46400040, 0x00001300 + +#define REG_TELEMETRY_PROC_WR_OVERFLOW_STATUS_WO_SEQFIFO_REG_ADDR 0x46400044 +#define BF_TELEMETRY_PROC_WR_OVR_BITS_WITH_NO_SEQFIFO_OVR_INFO 0x46400044, 0x00000600 + +#define REG_TELEMETRY_KFA_OVERFLOW_STATUS_WO_SEQFIFO_REG_ADDR 0x46400048 +#define BF_TELEMETRY_KFA_OVR_BITS_WITH_NO_SEQFIFO_OVR_INFO 0x46400048, 0x00000900 + +#define REG_TELEMETRY_STREAM_OVERFLOW_STATUS_WITH_SEQFIFO_REG_ADDR 0x4640004C +#define BF_TELEMETRY_STREAM_OVR_BITS_WITH_SEQFIFO_OVR_INFO 0x4640004C, 0x00001300 + +#define REG_TELEMETRY_PROC_WR_OVERFLOW_STATUS_WITH_SEQFIFO_REG_ADDR 0x46400050 +#define BF_TELEMETRY_PROC_WR_OVR_BITS_WITH_SEQFIFO_OVR_INFO 0x46400050, 0x00000600 + +#define REG_TELEMETRY_KFA_OVERFLOW_STATUS_WITH_SEQFIFO_REG_ADDR 0x46400054 +#define BF_TELEMETRY_KFA_OVR_BITS_WITH_SEQFIFO_OVR_INFO 0x46400054, 0x00000900 + +#define REG_TELEMETRY_OVERFLOW_INTERRUPT_ENABLE_ADDR 0x46400058 +#define BF_TELEMETRY_INTR_ENABLE_BITS_INFO 0x46400058, 0x00000300 +#define BF_TELEMETRY_INTR_ENABLE_FOR_SEQFIFO_BIT_INFO 0x46400058, 0x00000303 + +#define REG_TELEMETRY_MEM_FIFO_INTR_EN_ADDR 0x4640005C +#define BF_TELEMETRY_MEM_OV_INTR_EN_INFO 0x4640005C, 0x00000100 +#define BF_TELEMETRY_MEM_FIFO_WATERMARK_INTR_EN_INFO 0x4640005C, 0x00000101 + +#define REG_TELEMETRY_MEM_FIFO_WATERMARK_ADDR 0x46400060 +#define BF_TELEMETRY_MEM_FIFO_WATERMARK_INFO 0x46400060, 0x00000E00 + +#define REG_TELEMETRY_MEM_FIFO_STATUS_ADDR 0x46400064 +#define BF_TELEMETRY_MEM_FIFO_EMPTY_INFO 0x46400064, 0x00000100 +#define BF_TELEMETRY_MEM_FIFO_OVERFLOW_INFO 0x46400064, 0x00000101 +#define BF_TELEMETRY_MEM_FIFO_COUNT_INFO 0x46400064, 0x00000E02 + +#define REG_TELEMETRY_MEM_DIRECT_ACCESS_ADDR 0x46400068 +#define BF_TELEMETRY_MEM_DIRECT_ACCESS_INFO 0x46400068, 0x00000100 + +#endif /* __ADI_APOLLO_BF_TELEMETRY_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_timer.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_timer.h new file mode 100644 index 00000000000000..5c14d435209017 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_timer.h @@ -0,0 +1,63 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:17 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_TIMER_H__ +#define __ADI_APOLLO_BF_TIMER_H__ + +/*============= D E F I N E S ==============*/ +#define CORE_0_TIMER0 0x40000000 +#define CORE_0_TIMER1 0x40010000 +#define CORE_0_TIMER2 0x40020000 +#define CORE_0_TIMER3 0x40030000 +#define CORE_0_TIMER4 0x40040000 +#define CORE_0_TIMER5 0x40050000 +#define CORE_0_TIMER6 0x40060000 +#define CORE_0_TIMER7 0x40070000 +#define CORE_0_TIMER8 0x40080000 +#define CORE_0_TIMER9 0x40090000 +#define CORE_0_TIMER10 0x400A0000 +#define CORE_0_TIMER11 0x400B0000 +#define CORE_0_TIMER12 0x400C0000 +#define CORE_0_TIMER13 0x400D0000 +#define CORE_0_TIMER14 0x400E0000 +#define CORE_0_TIMER15 0x400F0000 + +#define REG_LOAD_ADDR(inst) ((inst) + 0x00000000) +#define BF_LOAD_VAL_INFO(inst) ((inst) + 0x00000000), 0x00002000 + +#define REG_VALS_ADDR(inst) ((inst) + 0x00000004) +#define BF_TIMER_READ_VAL_INFO(inst) ((inst) + 0x00000004), 0x00002000 + +#define REG_CON_ADDR(inst) ((inst) + 0x00000008) +#define BF_PRESCALE_INFO(inst) ((inst) + 0x00000008), 0x00000200 +#define BF_UP_INFO(inst) ((inst) + 0x00000008), 0x00000102 +#define BF_MODE_TIMER_INFO(inst) ((inst) + 0x00000008), 0x00000103 +#define BF_ENABLE_INFO(inst) ((inst) + 0x00000008), 0x00000104 +#define BF_CLKSEL_INFO(inst) ((inst) + 0x00000008), 0x00000205 +#define BF_RLD_INFO(inst) ((inst) + 0x00000008), 0x00000107 +#define BF_EVENT_SEL_INFO(inst) ((inst) + 0x00000008), 0x00000408 +#define BF_EVENT_EN_INFO(inst) ((inst) + 0x00000008), 0x0000010C + +#define REG_CLRI_ADDR(inst) ((inst) + 0x0000000C) +#define BF_CLEAR_TIMER_VAL_INFO(inst) ((inst) + 0x0000000C), 0x00000100 +#define BF_CLEAR_TIMEOUT_INTERRUPT_INFO(inst) ((inst) + 0x0000000C), 0x00000101 + +#define REG_CAPTURE_ADDR(inst) ((inst) + 0x00000010) +#define BF_TIMER_CAPTURE_VAL_INFO(inst) ((inst) + 0x00000010), 0x00002000 + +#define REG_STATUS_TIMER_ADDR(inst) ((inst) + 0x00000014) +#define BF_TIMEOUT_INFO(inst) ((inst) + 0x00000014), 0x00000100 + +#endif /* __ADI_APOLLO_BF_TIMER_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_tx_bist.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_tx_bist.h new file mode 100644 index 00000000000000..48cf32e253d139 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_tx_bist.h @@ -0,0 +1,39 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:21 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_TX_BIST_H__ +#define __ADI_APOLLO_BF_TX_BIST_H__ + +/*============= D E F I N E S ==============*/ +#define TX_BIST0_TX_SLICE_0_TX_DIGITAL0 0x61206000 +#define TX_BIST1_TX_SLICE_0_TX_DIGITAL0 0x61207000 +#define TX_BIST0_TX_SLICE_1_TX_DIGITAL0 0x61406000 +#define TX_BIST1_TX_SLICE_1_TX_DIGITAL0 0x61407000 +#define TX_BIST0_TX_SLICE_0_TX_DIGITAL1 0x61A06000 +#define TX_BIST1_TX_SLICE_0_TX_DIGITAL1 0x61A07000 +#define TX_BIST0_TX_SLICE_1_TX_DIGITAL1 0x61C06000 +#define TX_BIST1_TX_SLICE_1_TX_DIGITAL1 0x61C07000 + +#ifdef USE_PRIVATE_BF +#define REG_BIST_CFG_ADDR(inst) ((inst) + 0x00000000) +#define BF_BIST_EN_TX_BIST_INFO(inst) ((inst) + 0x00000000), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_BIST_SIGNA0_ADDR(inst) ((inst) + 0x00000023) +#define BF_BIST_STATUS_INFO(inst) ((inst) + 0x00000023), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#endif /* __ADI_APOLLO_BF_TX_BIST_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_tx_bist_test.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_tx_bist_test.h new file mode 100644 index 00000000000000..73b09a4309b031 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_tx_bist_test.h @@ -0,0 +1,125 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:21 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_TX_BIST_TEST_H__ +#define __ADI_APOLLO_BF_TX_BIST_TEST_H__ + +/*============= D E F I N E S ==============*/ +#define TX_BIST_TEST_HSDOUT0_TX_SLICE_0_TX_DIGITAL0 0x6120C000 +#define TX_BIST_TEST_HSDOUT1_TX_SLICE_0_TX_DIGITAL0 0x6120C040 +#define TX_BIST_TEST_LINEARX_TX_SLICE_0_TX_DIGITAL0 0x6120C080 +#define TX_BIST_TEST_FDUC_TX_SLICE_0_TX_DIGITAL0 0x6130C000 +#define TX_BIST_TEST_FSRC_CFIR_TX_SLICE_0_TX_DIGITAL0 0x6130C040 +#define TX_BIST_TEST_CDUC_TX_SLICE_0_TX_DIGITAL0 0x6133B000 +#define TX_BIST_TEST_PFILT_TX_SLICE_0_TX_DIGITAL0 0x6133B040 +#define TX_BIST_TEST_HSDOUT0_TX_SLICE_1_TX_DIGITAL0 0x6140C000 +#define TX_BIST_TEST_HSDOUT1_TX_SLICE_1_TX_DIGITAL0 0x6140C040 +#define TX_BIST_TEST_LINEARX_TX_SLICE_1_TX_DIGITAL0 0x6140C080 +#define TX_BIST_TEST_FDUC_TX_SLICE_1_TX_DIGITAL0 0x6150C000 +#define TX_BIST_TEST_FSRC_CFIR_TX_SLICE_1_TX_DIGITAL0 0x6150C040 +#define TX_BIST_TEST_CDUC_TX_SLICE_1_TX_DIGITAL0 0x6153B000 +#define TX_BIST_TEST_PFILT_TX_SLICE_1_TX_DIGITAL0 0x6153B040 +#define TX_BIST_TEST_HSDOUT0_TX_SLICE_0_TX_DIGITAL1 0x61A0C000 +#define TX_BIST_TEST_HSDOUT1_TX_SLICE_0_TX_DIGITAL1 0x61A0C040 +#define TX_BIST_TEST_LINEARX_TX_SLICE_0_TX_DIGITAL1 0x61A0C080 +#define TX_BIST_TEST_FDUC_TX_SLICE_0_TX_DIGITAL1 0x61B0C000 +#define TX_BIST_TEST_FSRC_CFIR_TX_SLICE_0_TX_DIGITAL1 0x61B0C040 +#define TX_BIST_TEST_CDUC_TX_SLICE_0_TX_DIGITAL1 0x61B3B000 +#define TX_BIST_TEST_PFILT_TX_SLICE_0_TX_DIGITAL1 0x61B3B040 +#define TX_BIST_TEST_HSDOUT0_TX_SLICE_1_TX_DIGITAL1 0x61C0C000 +#define TX_BIST_TEST_HSDOUT1_TX_SLICE_1_TX_DIGITAL1 0x61C0C040 +#define TX_BIST_TEST_LINEARX_TX_SLICE_1_TX_DIGITAL1 0x61C0C080 +#define TX_BIST_TEST_FDUC_TX_SLICE_1_TX_DIGITAL1 0x61D0C000 +#define TX_BIST_TEST_FSRC_CFIR_TX_SLICE_1_TX_DIGITAL1 0x61D0C040 +#define TX_BIST_TEST_CDUC_TX_SLICE_1_TX_DIGITAL1 0x61D3B000 +#define TX_BIST_TEST_PFILT_TX_SLICE_1_TX_DIGITAL1 0x61D3B040 + +#define REG_TX_BIST_CTRL_ADDR(inst) ((inst) + 0x00000000) +#ifdef USE_PRIVATE_BF +#define BF_TX_BIST_ENABLE_INFO(inst) ((inst) + 0x00000000), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#ifdef USE_PRIVATE_BF +#define BF_TX_BIST_FLUSH_LEN_INFO(inst) ((inst) + 0x00000000), 0x00000201 +#endif /* USE_PRIVATE_BF */ +#ifdef USE_PRIVATE_BF +#define BF_TX_BIST_ZERO_NOT_SENSITIVE_INFO(inst) ((inst) + 0x00000000), 0x00000103 +#endif /* USE_PRIVATE_BF */ +#ifdef USE_PRIVATE_BF +#define BF_TX_BIST_DAC_START_INFO(inst) ((inst) + 0x00000000), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_TX_BIST_HOLD_NCO_INFO(inst) ((inst) + 0x00000000), 0x00000105 + +#ifdef USE_PRIVATE_BF +#define REG_TX_BIST_STATUS_ADDR(inst) ((inst) + 0x00000001) +#define BF_TX_BIST_CLR_INFO(inst) ((inst) + 0x00000001), 0x00000100 +#define BF_TX_BIST_RUN_INFO(inst) ((inst) + 0x00000001), 0x00000101 +#define BF_TX_BIST_DONE_INFO(inst) ((inst) + 0x00000001), 0x00000102 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TX_BIST_LEN_LSB_ADDR(inst) ((inst) + 0x00000002) +#define BF_TX_BIST_LENGTH_INFO(inst) ((inst) + 0x00000002), 0x00001300 +#endif /* USE_PRIVATE_BF */ + +#define REG_TX_BIST_LEN_MID_ADDR(inst) ((inst) + 0x00000003) + +#define REG_TX_BIST_LEN_MSB_ADDR(inst) ((inst) + 0x00000004) + +#ifdef USE_PRIVATE_BF +#define REG_TX_BIST_READ_CTRL_ADDR(inst) ((inst) + 0x00000005) +#define BF_TX_BIST_SIGN_RD_MODE_INFO(inst) ((inst) + 0x00000005), 0x00000100 +#define BF_TX_BIST_SIGN_RD_SEL_INFO(inst) ((inst) + 0x00000005), 0x00000501 +#define BF_TX_BIST_SIGN_RD_CLR_INFO(inst) ((inst) + 0x00000005), 0x00000106 +#define BF_TX_BIST_SIGN_RD_EN_INFO(inst) ((inst) + 0x00000005), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TX_BIST_SIGN_LSB_ADDR(inst) ((inst) + 0x00000006) +#define BF_TX_BIST_SIGNATURE_INFO(inst) ((inst) + 0x00000006), 0x00001800 +#endif /* USE_PRIVATE_BF */ + +#define REG_TX_BIST_SIGN_MID_ADDR(inst) ((inst) + 0x00000007) + +#define REG_TX_BIST_SIGN_MSB_ADDR(inst) ((inst) + 0x00000008) + +#ifdef USE_PRIVATE_BF +#define REG_TX_BIST_GLOBAL_STATUS_ADDR(inst) ((inst) + 0x00000009) +#define BF_TX_G_BIST_ENABLE_INFO(inst) ((inst) + 0x00000009), 0x00000100 +#define BF_TX_G_BIST_MODE_INFO(inst) ((inst) + 0x00000009), 0x00000101 +#define BF_TX_G_BIST_CLR_INFO(inst) ((inst) + 0x00000009), 0x00000102 +#define BF_TX_G_BIST_RUN_INFO(inst) ((inst) + 0x00000009), 0x00000103 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TX_BIST_LB0_CTRL_ADDR(inst, n) ((inst) + 0x0000000A + 1 * (n)) +#define BF_TX_LPBK_ADC_BIST_MODE_SEL_INFO(inst, n) ((inst) + 0x0000000A + 1 * (n)), 0x00000100 +#define BF_TX_LPBK_ADC_BIST_INVERT_INFO(inst, n) ((inst) + 0x0000000A + 1 * (n)), 0x00000101 +#define BF_TX_LPBK_ADC_BIST_ENABLE_INFO(inst, n) ((inst) + 0x0000000A + 1 * (n)), 0x00000102 +#define BF_TX_LPBK_ADC_BIST_START_INFO(inst, n) ((inst) + 0x0000000A + 1 * (n)), 0x00000103 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TX_BIST_LB0_STATUS_ADDR(inst, n) ((inst) + 0x0000000E + 1 * (n)) +#define BF_TX_LPBK_ADC_BIST_DONE_INFO(inst, n) ((inst) + 0x0000000E + 1 * (n)), 0x00000100 +#define BF_TX_LPBK_ADC_BIST_PASS_INFO(inst, n) ((inst) + 0x0000000E + 1 * (n)), 0x00000101 +#define BF_TX_LPBK_ADC_BIST_FAIL_INFO(inst, n) ((inst) + 0x0000000E + 1 * (n)), 0x00000102 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TX_BIST_LB0_ERROR_ADDR(inst, n) ((inst) + 0x00000012 + 1 * (n)) +#define BF_TX_LPBK_ADC_BIST_ERRORS_INFO(inst, n) ((inst) + 0x00000012 + 1 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#endif /* __ADI_APOLLO_BF_TX_BIST_TEST_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_tx_cduc.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_tx_cduc.h new file mode 100644 index 00000000000000..0d42513247331e --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_tx_cduc.h @@ -0,0 +1,80 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:21 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_TX_CDUC_H__ +#define __ADI_APOLLO_BF_TX_CDUC_H__ + +/*============= D E F I N E S ==============*/ +#define TX_CDUC_TX_SLICE_0_TX_DIGITAL0 0x61330000 +#define TX_CDUC_TX_SLICE_1_TX_DIGITAL0 0x61530000 +#define TX_CDUC_TX_SLICE_0_TX_DIGITAL1 0x61B30000 +#define TX_CDUC_TX_SLICE_1_TX_DIGITAL1 0x61D30000 + +#define REG_CDUC_DP_CFG0_ADDR(inst) ((inst) + 0x000001D0) +#define BF_POST_INTERP_INFO(inst) ((inst) + 0x000001D0), 0x00000400 + +#ifdef USE_PRIVATE_BF +#define REG_CDUC_DP_CFG1_ADDR(inst) ((inst) + 0x000001D1) +#define BF_CHB1_INT_TIME_DLY_INFO(inst) ((inst) + 0x000001D1), 0x00000100 +#define BF_CHB2_INT_TIME_DLY_INFO(inst) ((inst) + 0x000001D1), 0x00000101 +#define BF_CHB3_INT_TIME_DLY_INFO(inst) ((inst) + 0x000001D1), 0x00000102 +#define BF_CTB1_INT_TIME_DLY_INFO(inst) ((inst) + 0x000001D1), 0x00000203 +#endif /* USE_PRIVATE_BF */ + +#define REG_CDUC_TEST_MUX_ADDR(inst) ((inst) + 0x000001D2) +#define BF_TEST_MUX_INFO(inst) ((inst) + 0x000001D2), 0x00000400 + +#define REG_CDUC_IRQ_EN0_ADDR(inst) ((inst) + 0x000001D3) +#define BF_CDUC_IRQ_EN0_INFO(inst) ((inst) + 0x000001D3), 0x00000A00 + +#define REG_CDUC_IRQ_EN1_ADDR(inst) ((inst) + 0x000001D4) + +#define REG_CDUC_IRQ_EN2_ADDR(inst) ((inst) + 0x000001D5) +#define BF_CDUC_IRQ_EN1_INFO(inst) ((inst) + 0x000001D5), 0x00000A00 + +#define REG_CDUC_IRQ_EN3_ADDR(inst) ((inst) + 0x000001D6) + +#define REG_CDUC_IRQ_STATUS0_ADDR(inst) ((inst) + 0x000001D7) +#define BF_CHB1_I_OVR_STATUS0_INFO(inst) ((inst) + 0x000001D7), 0x00000100 +#define BF_CHB1_Q_OVR_STATUS0_INFO(inst) ((inst) + 0x000001D7), 0x00000101 +#define BF_CHB2_I_OVR_STATUS0_INFO(inst) ((inst) + 0x000001D7), 0x00000102 +#define BF_CHB2_Q_OVR_STATUS0_INFO(inst) ((inst) + 0x000001D7), 0x00000103 +#define BF_CHB3_I_OVR_STATUS0_INFO(inst) ((inst) + 0x000001D7), 0x00000104 +#define BF_CHB3_Q_OVR_STATUS0_INFO(inst) ((inst) + 0x000001D7), 0x00000105 +#define BF_CTB1_I_OVR_STATUS0_INFO(inst) ((inst) + 0x000001D7), 0x00000106 +#define BF_CTB1_Q_OVR_STATUS0_INFO(inst) ((inst) + 0x000001D7), 0x00000107 + +#define REG_CDUC_IRQ_STATUS1_ADDR(inst) ((inst) + 0x000001D8) +#define BF_CNCO_I_OVR_STATUS0_INFO(inst) ((inst) + 0x000001D8), 0x00000100 +#define BF_CNCO_Q_OVR_STATUS0_INFO(inst) ((inst) + 0x000001D8), 0x00000101 + +#define REG_CDUC_IRQ_STATUS2_ADDR(inst) ((inst) + 0x000001D9) +#define BF_CHB1_I_OVR_STATUS1_INFO(inst) ((inst) + 0x000001D9), 0x00000100 +#define BF_CHB1_Q_OVR_STATUS1_INFO(inst) ((inst) + 0x000001D9), 0x00000101 +#define BF_CHB2_I_OVR_STATUS1_INFO(inst) ((inst) + 0x000001D9), 0x00000102 +#define BF_CHB2_Q_OVR_STATUS1_INFO(inst) ((inst) + 0x000001D9), 0x00000103 +#define BF_CHB3_I_OVR_STATUS1_INFO(inst) ((inst) + 0x000001D9), 0x00000104 +#define BF_CHB3_Q_OVR_STATUS1_INFO(inst) ((inst) + 0x000001D9), 0x00000105 +#define BF_CTB1_I_OVR_STATUS1_INFO(inst) ((inst) + 0x000001D9), 0x00000106 +#define BF_CTB1_Q_OVR_STATUS1_INFO(inst) ((inst) + 0x000001D9), 0x00000107 + +#define REG_CDUC_IRQ_STATUS3_ADDR(inst) ((inst) + 0x000001DA) +#define BF_CNCO_I_OVR_STATUS1_INFO(inst) ((inst) + 0x000001DA), 0x00000100 +#define BF_CNCO_Q_OVR_STATUS1_INFO(inst) ((inst) + 0x000001DA), 0x00000101 + +#define REG_CDUC_IRQ_CLR_ADDR(inst) ((inst) + 0x000001DB) +#define BF_CDUC_IRQ_CLR_INFO(inst) ((inst) + 0x000001DB), 0x00000100 + +#endif /* __ADI_APOLLO_BF_TX_CDUC_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_tx_eng.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_tx_eng.h new file mode 100644 index 00000000000000..aea91b6099e45e --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_tx_eng.h @@ -0,0 +1,107 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:21 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_TX_ENG_H__ +#define __ADI_APOLLO_BF_TX_ENG_H__ + +/*============= D E F I N E S ==============*/ +#define TX_ENG_TX_TOP_TX_DIGITAL0 0x61010000 +#define TX_ENG_TX_TOP_TX_DIGITAL1 0x61810000 + +#ifdef USE_PRIVATE_BF +#define REG_FHB1_CLK_DEBUG0_ADDR(inst) ((inst) + 0x00000000) +#define BF_FHB1_FORCE_ON_INFO(inst) ((inst) + 0x00000000), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FHB1_CLK_DEBUG1_ADDR(inst) ((inst) + 0x00000001) +#define BF_FHB1_FORCE_OFF_INFO(inst) ((inst) + 0x00000001), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FHB2_CLK_DEBUG0_ADDR(inst) ((inst) + 0x00000002) +#define BF_FHB2_FORCE_ON_INFO(inst) ((inst) + 0x00000002), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FHB2_CLK_DEBUG1_ADDR(inst) ((inst) + 0x00000003) +#define BF_FHB2_FORCE_OFF_INFO(inst) ((inst) + 0x00000003), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FHB3_CLK_DEBUG0_ADDR(inst) ((inst) + 0x00000004) +#define BF_FHB3_FORCE_ON_INFO(inst) ((inst) + 0x00000004), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FHB3_CLK_DEBUG1_ADDR(inst) ((inst) + 0x00000005) +#define BF_FHB3_FORCE_OFF_INFO(inst) ((inst) + 0x00000005), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FHB4_CLK_DEBUG0_ADDR(inst) ((inst) + 0x00000006) +#define BF_FHB4_FORCE_ON_INFO(inst) ((inst) + 0x00000006), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FHB4_CLK_DEBUG1_ADDR(inst) ((inst) + 0x00000007) +#define BF_FHB4_FORCE_OFF_INFO(inst) ((inst) + 0x00000007), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FHB5_CLK_DEBUG0_ADDR(inst) ((inst) + 0x00000008) +#define BF_FHB5_FORCE_ON_INFO(inst) ((inst) + 0x00000008), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FHB5_CLK_DEBUG1_ADDR(inst) ((inst) + 0x00000009) +#define BF_FHB5_FORCE_OFF_INFO(inst) ((inst) + 0x00000009), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FHB6_CLK_DEBUG0_ADDR(inst) ((inst) + 0x0000000A) +#define BF_FHB6_FORCE_ON_INFO(inst) ((inst) + 0x0000000A), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FHB6_CLK_DEBUG1_ADDR(inst) ((inst) + 0x0000000B) +#define BF_FHB6_FORCE_OFF_INFO(inst) ((inst) + 0x0000000B), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CHB1_CLK_DEBUG_ADDR(inst) ((inst) + 0x0000000C) +#define BF_FORCE_CHB1_ON_INFO(inst) ((inst) + 0x0000000C), 0x00000400 +#define BF_FORCE_CHB1_OFF_INFO(inst) ((inst) + 0x0000000C), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CTB1_CLK_DEBUG_ADDR(inst) ((inst) + 0x0000000D) +#define BF_FORCE_CTB1_ON_INFO(inst) ((inst) + 0x0000000D), 0x00000400 +#define BF_FORCE_CTB1_OFF_INFO(inst) ((inst) + 0x0000000D), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CHB2_CLK_DEBUG_ADDR(inst) ((inst) + 0x0000000E) +#define BF_FORCE_CHB2_ON_INFO(inst) ((inst) + 0x0000000E), 0x00000400 +#define BF_FORCE_CHB2_OFF_INFO(inst) ((inst) + 0x0000000E), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CHB3_CLK_DEBUG_ADDR(inst) ((inst) + 0x0000000F) +#define BF_FORCE_CHB3_ON_INFO(inst) ((inst) + 0x0000000F), 0x00000400 +#define BF_FORCE_CHB3_OFF_INFO(inst) ((inst) + 0x0000000F), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#endif /* __ADI_APOLLO_BF_TX_ENG_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_tx_fduc.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_tx_fduc.h new file mode 100644 index 00000000000000..231eb99f3dec8f --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_tx_fduc.h @@ -0,0 +1,49 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:21 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_TX_FDUC_H__ +#define __ADI_APOLLO_BF_TX_FDUC_H__ + +/*============= D E F I N E S ==============*/ +#define TX_FDUC0_TX_SLICE_0_TX_DIGITAL0 0x61300000 +#define TX_FDUC1_TX_SLICE_0_TX_DIGITAL0 0x61301000 +#define TX_FDUC0_TX_SLICE_1_TX_DIGITAL0 0x61500000 +#define TX_FDUC1_TX_SLICE_1_TX_DIGITAL0 0x61501000 +#define TX_FDUC0_TX_SLICE_0_TX_DIGITAL1 0x61B00000 +#define TX_FDUC1_TX_SLICE_0_TX_DIGITAL1 0x61B01000 +#define TX_FDUC0_TX_SLICE_1_TX_DIGITAL1 0x61D00000 +#define TX_FDUC1_TX_SLICE_1_TX_DIGITAL1 0x61D01000 + +#define REG_FDUC_INTERP_ADDR(inst) ((inst) + 0x00000000) +#define BF_FDUC_INTERP_INFO(inst) ((inst) + 0x00000000), 0x00000700 + +#define REG_SUB_DATAPATH_CFG_ADDR(inst) ((inst) + 0x00000002) +#define BF_SUB_DP_GAIN_EN_INFO(inst) ((inst) + 0x00000002), 0x00000100 +#define BF_FDUC_INTERP_GPIO_EN_INFO(inst) ((inst) + 0x00000002), 0x00000101 + +#define REG_SUBDP_GAIN0_ADDR(inst) ((inst) + 0x00000003) +#define BF_SUBDP_GAIN_INFO(inst) ((inst) + 0x00000003), 0x00000C00 + +#define REG_SUBDP_GAIN1_ADDR(inst) ((inst) + 0x00000004) + +#define REG_INT_TIME_DELAY_ADDR(inst) ((inst) + 0x00000006) +#define BF_INT_TIME_DELAY_HB1_INFO(inst) ((inst) + 0x00000006), 0x00000100 +#define BF_INT_TIME_DELAY_HB2_INFO(inst) ((inst) + 0x00000006), 0x00000101 +#define BF_INT_TIME_DELAY_HB3_INFO(inst) ((inst) + 0x00000006), 0x00000102 +#define BF_INT_TIME_DELAY_HB4_INFO(inst) ((inst) + 0x00000006), 0x00000103 +#define BF_INT_TIME_DELAY_HB5_INFO(inst) ((inst) + 0x00000006), 0x00000104 +#define BF_INT_TIME_DELAY_HB6_INFO(inst) ((inst) + 0x00000006), 0x00000105 + +#endif /* __ADI_APOLLO_BF_TX_FDUC_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_tx_hsdout.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_tx_hsdout.h new file mode 100644 index 00000000000000..b22d09fe23ab74 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_tx_hsdout.h @@ -0,0 +1,85 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:21 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_TX_HSDOUT_H__ +#define __ADI_APOLLO_BF_TX_HSDOUT_H__ + +/*============= D E F I N E S ==============*/ +#define TX_HSDOUT0_TX_SLICE_0_TX_DIGITAL0 0x61204000 +#define TX_HSDOUT1_TX_SLICE_0_TX_DIGITAL0 0x61205000 +#define TX_HSDOUT0_TX_SLICE_1_TX_DIGITAL0 0x61404000 +#define TX_HSDOUT1_TX_SLICE_1_TX_DIGITAL0 0x61405000 +#define TX_HSDOUT0_TX_SLICE_0_TX_DIGITAL1 0x61A04000 +#define TX_HSDOUT1_TX_SLICE_0_TX_DIGITAL1 0x61A05000 +#define TX_HSDOUT0_TX_SLICE_1_TX_DIGITAL1 0x61C04000 +#define TX_HSDOUT1_TX_SLICE_1_TX_DIGITAL1 0x61C05000 + +#define REG_DAC_REG_WR_SETUP_CYCLES_ADDR(inst) ((inst) + 0x00000000) +#define BF_DAC_ANA_BRIDGE_WR_SETUP_CYCLES_INFO(inst) ((inst) + 0x00000000), 0x00000600 + +#define REG_DAC_REG_WR_HOLD_CYCLES_ADDR(inst) ((inst) + 0x00000001) +#define BF_DAC_ANA_BRIDGE_WR_HOLD_CYCLES_INFO(inst) ((inst) + 0x00000001), 0x00000600 + +#define REG_DAC_REG_RD_CYCLES_ADDR(inst) ((inst) + 0x00000002) +#define BF_DAC_ANA_BRIDGE_RD_CYCLES_INFO(inst) ((inst) + 0x00000002), 0x00000600 + +#define REG_DFIFO_CTRL_TX_HSDOUT_ADDR(inst) ((inst) + 0x00000050) +#define BF_DFIFO_EN_TX_HSDOUT_INFO(inst) ((inst) + 0x00000050), 0x00000100 +#define BF_DAC_FIFO_FORCEON_CTRL_TX_HSDOUT_INFO(inst) ((inst) + 0x00000050), 0x00000404 + +#define REG_LAT_CTRL_TX_HSDOUT_ADDR(inst) ((inst) + 0x00000051) +#define BF_LAT_PGM_MODE_TX_HSDOUT_INFO(inst) ((inst) + 0x00000051), 0x00000200 +#define BF_WR_RD_OFFSET_TX_HSDOUT_INFO(inst) ((inst) + 0x00000051), 0x00000304 + +#define REG_LAT_SPI_CTRL_TX_HSDOUT_ADDR(inst) ((inst) + 0x00000052) +#define BF_LAT_WR_SPI_TX_HSDOUT_INFO(inst) ((inst) + 0x00000052), 0x00000300 +#define BF_LAT_RD_SPI_TX_HSDOUT_INFO(inst) ((inst) + 0x00000052), 0x00000404 + +#define REG_SYNCCNT_STRB_TX_HSDOUT_ADDR(inst) ((inst) + 0x00000053) +#define BF_WRSYNCCNT_RDSTRB_TX_HSDOUT_INFO(inst) ((inst) + 0x00000053), 0x00000300 +#define BF_RDSYNCCNT_WRSTRB_TX_HSDOUT_INFO(inst) ((inst) + 0x00000053), 0x00000404 + +#define REG_LAT_REAL_TX_HSDOUT_ADDR(inst) ((inst) + 0x00000054) +#define BF_LAT_WR_REAL_TX_HSDOUT_INFO(inst) ((inst) + 0x00000054), 0x00000300 +#define BF_LAT_RD_REAL_TX_HSDOUT_INFO(inst) ((inst) + 0x00000054), 0x00000404 + +#define REG_SYNC_STATE_TX_HSDOUT_ADDR(inst) ((inst) + 0x00000055) +#define BF_WRSYNC_STATE_TX_HSDOUT_INFO(inst) ((inst) + 0x00000055), 0x00000200 +#define BF_RDSYNC_STATE_TX_HSDOUT_INFO(inst) ((inst) + 0x00000055), 0x00000204 + +#define REG_DATA_INVERSION_ADDR(inst) ((inst) + 0x00000056) +#define BF_DAC_DATA_INVERSION_EN_INFO(inst) ((inst) + 0x00000056), 0x00000100 + +#define REG_INVSINC_CFG_ADDR(inst) ((inst) + 0x000001D0) +#define BF_INVSINC_EN_INFO(inst) ((inst) + 0x000001D0), 0x00000100 + +#define REG_INVSINC_CLK_GATING_ADDR(inst) ((inst) + 0x000001D1) +#define BF_INVSINC_CLK_EN_INFO(inst) ((inst) + 0x000001D1), 0x00000100 + +#define REG_PIPEDLY_CFG_ADDR(inst) ((inst) + 0x000001D2) +#define BF_PIPEDLY_EN_INFO(inst) ((inst) + 0x000001D2), 0x00000100 + +#define REG_PIPEDLY_CLK_GATING_ADDR(inst) ((inst) + 0x000001D3) +#define BF_PIPEDLY_CLK_EN_INFO(inst) ((inst) + 0x000001D3), 0x00000100 + +#ifdef USE_PRIVATE_BF +#define REG_TEST_MUX_LVDS_ADDR(inst) ((inst) + 0x000001D4) +#define BF_TEST_SEL_LVDS_INFO(inst) ((inst) + 0x000001D4), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#define REG_TEST_MUX_CMOS_ADDR(inst) ((inst) + 0x000001D5) +#define BF_TEST_SEL_CMOS_INFO(inst) ((inst) + 0x000001D5), 0x00000500 + +#endif /* __ADI_APOLLO_BF_TX_HSDOUT_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_tx_loopback.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_tx_loopback.h new file mode 100644 index 00000000000000..74fed4068896ac --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_tx_loopback.h @@ -0,0 +1,40 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:21 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_TX_LOOPBACK_H__ +#define __ADI_APOLLO_BF_TX_LOOPBACK_H__ + +/*============= D E F I N E S ==============*/ +#define TX_LOOPBACK0_TX_SLICE_0_TX_DIGITAL0 0x61200000 +#define TX_LOOPBACK1_TX_SLICE_0_TX_DIGITAL0 0x61201000 +#define TX_LOOPBACK0_TX_SLICE_1_TX_DIGITAL0 0x61400000 +#define TX_LOOPBACK1_TX_SLICE_1_TX_DIGITAL0 0x61401000 +#define TX_LOOPBACK0_TX_SLICE_0_TX_DIGITAL1 0x61A00000 +#define TX_LOOPBACK1_TX_SLICE_0_TX_DIGITAL1 0x61A01000 +#define TX_LOOPBACK0_TX_SLICE_1_TX_DIGITAL1 0x61C00000 +#define TX_LOOPBACK1_TX_SLICE_1_TX_DIGITAL1 0x61C01000 + +#define REG_LB0_CFG_ADDR(inst) ((inst) + 0x00000000) +#define BF_LB0_EN_INFO(inst) ((inst) + 0x00000000), 0x00000100 + +#define REG_LB0_RDPTR_CTRL_ADDR(inst) ((inst) + 0x00000001) +#define BF_LB0_RDPTR_SYNC_RSTVAL_INFO(inst) ((inst) + 0x00000001), 0x00000200 + +#ifdef USE_PRIVATE_BF +#define REG_LB0_STATUS_ADDR(inst) ((inst) + 0x00000023) +#define BF_LB_STATUS_INFO(inst) ((inst) + 0x00000023), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#endif /* __ADI_APOLLO_BF_TX_LOOPBACK_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_tx_misc.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_tx_misc.h new file mode 100644 index 00000000000000..e825bce329820b --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_tx_misc.h @@ -0,0 +1,262 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:21 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_TX_MISC_H__ +#define __ADI_APOLLO_BF_TX_MISC_H__ + +/*============= D E F I N E S ==============*/ +#define TX_MISC_TX_TOP_TX_DIGITAL0 0x61000000 +#define TX_MISC_TX_TOP_TX_DIGITAL1 0x61800000 + +#define REG_DP_CFG_ADDR(inst) ((inst) + 0x00000000) +#define BF_MODSW0_INFO(inst) ((inst) + 0x00000000), 0x00000300 +#define BF_MODSW1_INFO(inst) ((inst) + 0x00000000), 0x00000303 +#define BF_DIS_SCALE_INFO(inst) ((inst) + 0x00000000), 0x00000206 + +#ifdef USE_PRIVATE_BF +#define REG_HS_XBAR_CTRL_ADDR(inst) ((inst) + 0x00000001) +#define BF_HS_XBAR_CTRL_INFO(inst) ((inst) + 0x00000001), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_FDUC_ENABLES00_ADDR(inst) ((inst) + 0x00000002) +#define BF_FDUC_ENABLES00_INFO(inst) ((inst) + 0x00000002), 0x00000800 + +#define REG_FDUC_ENABLES01_ADDR(inst) ((inst) + 0x00000003) +#define BF_FDUC_ENABLES01_INFO(inst) ((inst) + 0x00000003), 0x00000800 + +#define REG_FDUC_ENABLES10_ADDR(inst) ((inst) + 0x00000004) +#define BF_FDUC_ENABLES10_INFO(inst) ((inst) + 0x00000004), 0x00000800 + +#define REG_FDUC_ENABLES11_ADDR(inst) ((inst) + 0x00000005) +#define BF_FDUC_ENABLES11_INFO(inst) ((inst) + 0x00000005), 0x00000800 + +#define REG_LOW_SAMP_TX_MISC_ADDR(inst) ((inst) + 0x00000007) +#define BF_LOW_SAMP_TX_MISC_INFO(inst) ((inst) + 0x00000007), 0x00000100 + +#define REG_SL0_FDUC0_HB_IRQ_EN0_ADDR(inst) ((inst) + 0x00000008) +#define BF_EN_SL0_FDUC0_HB1_I_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x00000008), 0x00000100 +#define BF_EN_SL0_FDUC0_HB2_I_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x00000008), 0x00000101 +#define BF_EN_SL0_FDUC0_HB3_I_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x00000008), 0x00000102 +#define BF_EN_SL0_FDUC0_HB4_I_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x00000008), 0x00000103 +#define BF_EN_SL0_FDUC0_HB5_I_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x00000008), 0x00000104 +#define BF_EN_SL0_FDUC0_HB6_I_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x00000008), 0x00000105 + +#define REG_SL0_FDUC0_HB_IRQ_EN1_ADDR(inst) ((inst) + 0x00000009) +#define BF_EN_SL0_FDUC0_HB1_Q_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x00000009), 0x00000100 +#define BF_EN_SL0_FDUC0_HB2_Q_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x00000009), 0x00000101 +#define BF_EN_SL0_FDUC0_HB3_Q_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x00000009), 0x00000102 +#define BF_EN_SL0_FDUC0_HB4_Q_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x00000009), 0x00000103 +#define BF_EN_SL0_FDUC0_HB5_Q_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x00000009), 0x00000104 +#define BF_EN_SL0_FDUC0_HB6_Q_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x00000009), 0x00000105 + +#define REG_SL0_FDUC1_IRQ_ADDR(inst) ((inst) + 0x0000000A) +#define BF_EN_SL0_FDUC1_HB1_I_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x0000000A), 0x00000100 +#define BF_EN_SL0_FDUC1_HB2_I_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x0000000A), 0x00000101 +#define BF_EN_SL0_FDUC1_HB3_I_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x0000000A), 0x00000102 +#define BF_EN_SL0_FDUC1_HB4_I_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x0000000A), 0x00000103 +#define BF_EN_SL0_FDUC1_HB5_I_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x0000000A), 0x00000104 +#define BF_EN_SL0_FDUC1_HB6_I_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x0000000A), 0x00000105 + +#define REG_SL0_FDUC1_HB_IRQ_EN1_ADDR(inst) ((inst) + 0x0000000B) +#define BF_EN_SL0_FDUC1_HB1_Q_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x0000000B), 0x00000100 +#define BF_EN_SL0_FDUC1_HB2_Q_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x0000000B), 0x00000101 +#define BF_EN_SL0_FDUC1_HB3_Q_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x0000000B), 0x00000102 +#define BF_EN_SL0_FDUC1_HB4_Q_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x0000000B), 0x00000103 +#define BF_EN_SL0_FDUC1_HB5_Q_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x0000000B), 0x00000104 +#define BF_EN_SL0_FDUC1_HB6_Q_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x0000000B), 0x00000105 + +#define REG_SL0_FNCO_IRQ_EN_ADDR(inst) ((inst) + 0x0000000C) +#define BF_EN_SL0_FDUC0_FNCO_OVR_I_IRQ0_INFO(inst) ((inst) + 0x0000000C), 0x00000100 +#define BF_EN_SL0_FDUC0_FNCO_OVR_I_IRQ1_INFO(inst) ((inst) + 0x0000000C), 0x00000101 +#define BF_EN_SL0_FDUC0_FNCO_OVR_Q_IRQ0_INFO(inst) ((inst) + 0x0000000C), 0x00000102 +#define BF_EN_SL0_FDUC0_FNCO_OVR_Q_IRQ1_INFO(inst) ((inst) + 0x0000000C), 0x00000103 +#define BF_EN_SL0_FDUC1_FNCO_OVR_I_IRQ0_INFO(inst) ((inst) + 0x0000000C), 0x00000104 +#define BF_EN_SL0_FDUC1_FNCO_OVR_I_IRQ1_INFO(inst) ((inst) + 0x0000000C), 0x00000105 +#define BF_EN_SL0_FDUC1_FNCO_OVR_Q_IRQ0_INFO(inst) ((inst) + 0x0000000C), 0x00000106 +#define BF_EN_SL0_FDUC1_FNCO_OVR_Q_IRQ1_INFO(inst) ((inst) + 0x0000000C), 0x00000107 + +#define REG_SL1_FDUC0_HB_IRQ_EN0_ADDR(inst) ((inst) + 0x0000000D) +#define BF_EN_SL1_FDUC0_HB1_I_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x0000000D), 0x00000100 +#define BF_EN_SL1_FDUC0_HB2_I_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x0000000D), 0x00000101 +#define BF_EN_SL1_FDUC0_HB3_I_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x0000000D), 0x00000102 +#define BF_EN_SL1_FDUC0_HB4_I_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x0000000D), 0x00000103 +#define BF_EN_SL1_FDUC0_HB5_I_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x0000000D), 0x00000104 +#define BF_EN_SL1_FDUC0_HB6_I_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x0000000D), 0x00000105 + +#define REG_SL1_FDUC0_HB_IRQ_EN1_ADDR(inst) ((inst) + 0x0000000E) +#define BF_EN_SL1_FDUC0_HB1_Q_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x0000000E), 0x00000100 +#define BF_EN_SL1_FDUC0_HB2_Q_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x0000000E), 0x00000101 +#define BF_EN_SL1_FDUC0_HB3_Q_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x0000000E), 0x00000102 +#define BF_EN_SL1_FDUC0_HB4_Q_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x0000000E), 0x00000103 +#define BF_EN_SL1_FDUC0_HB5_Q_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x0000000E), 0x00000104 +#define BF_EN_SL1_FDUC0_HB6_Q_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x0000000E), 0x00000105 + +#define REG_SL1_FDUC1_IRQ_ADDR(inst) ((inst) + 0x0000000F) +#define BF_EN_SL1_FDUC1_HB1_I_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x0000000F), 0x00000100 +#define BF_EN_SL1_FDUC1_HB2_I_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x0000000F), 0x00000101 +#define BF_EN_SL1_FDUC1_HB3_I_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x0000000F), 0x00000102 +#define BF_EN_SL1_FDUC1_HB4_I_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x0000000F), 0x00000103 +#define BF_EN_SL1_FDUC1_HB5_I_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x0000000F), 0x00000104 +#define BF_EN_SL1_FDUC1_HB6_I_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x0000000F), 0x00000105 + +#define REG_SL1_FDUC1_HB_IRQ_EN1_ADDR(inst) ((inst) + 0x00000010) +#define BF_EN_SL1_FDUC1_HB1_Q_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x00000010), 0x00000100 +#define BF_EN_SL1_FDUC1_HB2_Q_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x00000010), 0x00000101 +#define BF_EN_SL1_FDUC1_HB3_Q_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x00000010), 0x00000102 +#define BF_EN_SL1_FDUC1_HB4_Q_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x00000010), 0x00000103 +#define BF_EN_SL1_FDUC1_HB5_Q_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x00000010), 0x00000104 +#define BF_EN_SL1_FDUC1_HB6_Q_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x00000010), 0x00000105 + +#define REG_SL1_FNCO_IRQ_EN_ADDR(inst) ((inst) + 0x00000011) +#define BF_EN_SL1_FDUC0_FNCO_OVR_I_IRQ0_INFO(inst) ((inst) + 0x00000011), 0x00000100 +#define BF_EN_SL1_FDUC0_FNCO_OVR_I_IRQ1_INFO(inst) ((inst) + 0x00000011), 0x00000101 +#define BF_EN_SL1_FDUC0_FNCO_OVR_Q_IRQ0_INFO(inst) ((inst) + 0x00000011), 0x00000102 +#define BF_EN_SL1_FDUC0_FNCO_OVR_Q_IRQ1_INFO(inst) ((inst) + 0x00000011), 0x00000103 +#define BF_EN_SL1_FDUC1_FNCO_OVR_I_IRQ0_INFO(inst) ((inst) + 0x00000011), 0x00000104 +#define BF_EN_SL1_FDUC1_FNCO_OVR_I_IRQ1_INFO(inst) ((inst) + 0x00000011), 0x00000105 +#define BF_EN_SL1_FDUC1_FNCO_OVR_Q_IRQ0_INFO(inst) ((inst) + 0x00000011), 0x00000106 +#define BF_EN_SL1_FDUC1_FNCO_OVR_Q_IRQ1_INFO(inst) ((inst) + 0x00000011), 0x00000107 + +#define REG_SL0_FDUC0_HB_OVERFLOW0_ADDR(inst) ((inst) + 0x00000012) +#define BF_IRQ_SL0_FDUC0_HB1_I_OVER_FLOW_INFO(inst) ((inst) + 0x00000012), 0x00000100 +#define BF_IRQ_SL0_FDUC0_HB2_I_OVER_FLOW_INFO(inst) ((inst) + 0x00000012), 0x00000101 +#define BF_IRQ_SL0_FDUC0_HB3_I_OVER_FLOW_INFO(inst) ((inst) + 0x00000012), 0x00000102 +#define BF_IRQ_SL0_FDUC0_HB4_I_OVER_FLOW_INFO(inst) ((inst) + 0x00000012), 0x00000103 +#define BF_IRQ_SL0_FDUC0_HB5_I_OVER_FLOW_INFO(inst) ((inst) + 0x00000012), 0x00000104 +#define BF_IRQ_SL0_FDUC0_HB6_I_OVER_FLOW_INFO(inst) ((inst) + 0x00000012), 0x00000105 +#define BF_IRQ_FDUC_OVER_FLOW_ALL_INFO(inst) ((inst) + 0x00000012), 0x00000106 + +#define REG_SL0_FDUC0_HB_OVERFLOW1_ADDR(inst) ((inst) + 0x00000013) +#define BF_IRQ_SL0_FDUC0_HB1_Q_OVER_FLOW_INFO(inst) ((inst) + 0x00000013), 0x00000100 +#define BF_IRQ_SL0_FDUC0_HB2_Q_OVER_FLOW_INFO(inst) ((inst) + 0x00000013), 0x00000101 +#define BF_IRQ_SL0_FDUC0_HB3_Q_OVER_FLOW_INFO(inst) ((inst) + 0x00000013), 0x00000102 +#define BF_IRQ_SL0_FDUC0_HB4_Q_OVER_FLOW_INFO(inst) ((inst) + 0x00000013), 0x00000103 +#define BF_IRQ_SL0_FDUC0_HB5_Q_OVER_FLOW_INFO(inst) ((inst) + 0x00000013), 0x00000104 +#define BF_IRQ_SL0_FDUC0_HB6_Q_OVER_FLOW_INFO(inst) ((inst) + 0x00000013), 0x00000105 + +#define REG_SL0_FDUC1_HB_OVERFLOW0_ADDR(inst) ((inst) + 0x00000014) +#define BF_IRQ_SL0_FDUC1_HB1_I_OVER_FLOW_INFO(inst) ((inst) + 0x00000014), 0x00000100 +#define BF_IRQ_SL0_FDUC1_HB2_I_OVER_FLOW_INFO(inst) ((inst) + 0x00000014), 0x00000101 +#define BF_IRQ_SL0_FDUC1_HB3_I_OVER_FLOW_INFO(inst) ((inst) + 0x00000014), 0x00000102 +#define BF_IRQ_SL0_FDUC1_HB4_I_OVER_FLOW_INFO(inst) ((inst) + 0x00000014), 0x00000103 +#define BF_IRQ_SL0_FDUC1_HB5_I_OVER_FLOW_INFO(inst) ((inst) + 0x00000014), 0x00000104 +#define BF_IRQ_SL0_FDUC1_HB6_I_OVER_FLOW_INFO(inst) ((inst) + 0x00000014), 0x00000105 + +#define REG_SL0_FDUC1_HB_OVERFLOW1_ADDR(inst) ((inst) + 0x00000015) +#define BF_IRQ_SL0_FDUC1_HB1_Q_OVER_FLOW_INFO(inst) ((inst) + 0x00000015), 0x00000100 +#define BF_IRQ_SL0_FDUC1_HB2_Q_OVER_FLOW_INFO(inst) ((inst) + 0x00000015), 0x00000101 +#define BF_IRQ_SL0_FDUC1_HB3_Q_OVER_FLOW_INFO(inst) ((inst) + 0x00000015), 0x00000102 +#define BF_IRQ_SL0_FDUC1_HB4_Q_OVER_FLOW_INFO(inst) ((inst) + 0x00000015), 0x00000103 +#define BF_IRQ_SL0_FDUC1_HB5_Q_OVER_FLOW_INFO(inst) ((inst) + 0x00000015), 0x00000104 +#define BF_IRQ_SL0_FDUC1_HB6_Q_OVER_FLOW_INFO(inst) ((inst) + 0x00000015), 0x00000105 + +#define REG_SL0_FNCO_OVERFLOW_ADDR(inst) ((inst) + 0x00000016) +#define BF_IRQ_SL0_FDUC0_FNCO_I_OVER_FLOW0_INFO(inst) ((inst) + 0x00000016), 0x00000100 +#define BF_IRQ_SL0_FDUC0_FNCO_I_OVER_FLOW1_INFO(inst) ((inst) + 0x00000016), 0x00000101 +#define BF_IRQ_SL0_FDUC0_FNCO_Q_OVER_FLOW0_INFO(inst) ((inst) + 0x00000016), 0x00000102 +#define BF_IRQ_SL0_FDUC0_FNCO_Q_OVER_FLOW1_INFO(inst) ((inst) + 0x00000016), 0x00000103 +#define BF_IRQ_SL0_FDUC1_FNCO_I_OVER_FLOW0_INFO(inst) ((inst) + 0x00000016), 0x00000104 +#define BF_IRQ_SL0_FDUC1_FNCO_I_OVER_FLOW1_INFO(inst) ((inst) + 0x00000016), 0x00000105 +#define BF_IRQ_SL0_FDUC1_FNCO_Q_OVER_FLOW0_INFO(inst) ((inst) + 0x00000016), 0x00000106 +#define BF_IRQ_SL0_FDUC1_FNCO_Q_OVER_FLOW1_INFO(inst) ((inst) + 0x00000016), 0x00000107 + +#define REG_SL1_FDUC0_HB_OVERFLOW0_ADDR(inst) ((inst) + 0x00000017) +#define BF_IRQ_SL1_FDUC0_HB1_I_OVER_FLOW_INFO(inst) ((inst) + 0x00000017), 0x00000100 +#define BF_IRQ_SL1_FDUC0_HB2_I_OVER_FLOW_INFO(inst) ((inst) + 0x00000017), 0x00000101 +#define BF_IRQ_SL1_FDUC0_HB3_I_OVER_FLOW_INFO(inst) ((inst) + 0x00000017), 0x00000102 +#define BF_IRQ_SL1_FDUC0_HB4_I_OVER_FLOW_INFO(inst) ((inst) + 0x00000017), 0x00000103 +#define BF_IRQ_SL1_FDUC0_HB5_I_OVER_FLOW_INFO(inst) ((inst) + 0x00000017), 0x00000104 +#define BF_IRQ_SL1_FDUC0_HB6_I_OVER_FLOW_INFO(inst) ((inst) + 0x00000017), 0x00000105 + +#define REG_SL1_FDUC0_HB_OVERFLOW1_ADDR(inst) ((inst) + 0x00000018) +#define BF_IRQ_SL1_FDUC0_HB1_Q_OVER_FLOW_INFO(inst) ((inst) + 0x00000018), 0x00000100 +#define BF_IRQ_SL1_FDUC0_HB2_Q_OVER_FLOW_INFO(inst) ((inst) + 0x00000018), 0x00000101 +#define BF_IRQ_SL1_FDUC0_HB3_Q_OVER_FLOW_INFO(inst) ((inst) + 0x00000018), 0x00000102 +#define BF_IRQ_SL1_FDUC0_HB4_Q_OVER_FLOW_INFO(inst) ((inst) + 0x00000018), 0x00000103 +#define BF_IRQ_SL1_FDUC0_HB5_Q_OVER_FLOW_INFO(inst) ((inst) + 0x00000018), 0x00000104 +#define BF_IRQ_SL1_FDUC0_HB6_Q_OVER_FLOW_INFO(inst) ((inst) + 0x00000018), 0x00000105 + +#define REG_SL1_FDUC1_HB_OVERFLOW0_ADDR(inst) ((inst) + 0x00000019) +#define BF_IRQ_SL1_FDUC1_HB1_I_OVER_FLOW_INFO(inst) ((inst) + 0x00000019), 0x00000100 +#define BF_IRQ_SL1_FDUC1_HB2_I_OVER_FLOW_INFO(inst) ((inst) + 0x00000019), 0x00000101 +#define BF_IRQ_SL1_FDUC1_HB3_I_OVER_FLOW_INFO(inst) ((inst) + 0x00000019), 0x00000102 +#define BF_IRQ_SL1_FDUC1_HB4_I_OVER_FLOW_INFO(inst) ((inst) + 0x00000019), 0x00000103 +#define BF_IRQ_SL1_FDUC1_HB5_I_OVER_FLOW_INFO(inst) ((inst) + 0x00000019), 0x00000104 +#define BF_IRQ_SL1_FDUC1_HB6_I_OVER_FLOW_INFO(inst) ((inst) + 0x00000019), 0x00000105 + +#define REG_SL1_FDUC1_HB_OVERFLOW1_ADDR(inst) ((inst) + 0x0000001A) +#define BF_IRQ_SL1_FDUC1_HB1_Q_OVER_FLOW_INFO(inst) ((inst) + 0x0000001A), 0x00000100 +#define BF_IRQ_SL1_FDUC1_HB2_Q_OVER_FLOW_INFO(inst) ((inst) + 0x0000001A), 0x00000101 +#define BF_IRQ_SL1_FDUC1_HB3_Q_OVER_FLOW_INFO(inst) ((inst) + 0x0000001A), 0x00000102 +#define BF_IRQ_SL1_FDUC1_HB4_Q_OVER_FLOW_INFO(inst) ((inst) + 0x0000001A), 0x00000103 +#define BF_IRQ_SL1_FDUC1_HB5_Q_OVER_FLOW_INFO(inst) ((inst) + 0x0000001A), 0x00000104 +#define BF_IRQ_SL1_FDUC1_HB6_Q_OVER_FLOW_INFO(inst) ((inst) + 0x0000001A), 0x00000105 + +#define REG_SL1_FNCO_OVERFLOW_ADDR(inst) ((inst) + 0x0000001B) +#define BF_IRQ_SL1_FDUC0_FNCO_I_OVER_FLOW0_INFO(inst) ((inst) + 0x0000001B), 0x00000100 +#define BF_IRQ_SL1_FDUC0_FNCO_I_OVER_FLOW1_INFO(inst) ((inst) + 0x0000001B), 0x00000101 +#define BF_IRQ_SL1_FDUC0_FNCO_Q_OVER_FLOW0_INFO(inst) ((inst) + 0x0000001B), 0x00000102 +#define BF_IRQ_SL1_FDUC0_FNCO_Q_OVER_FLOW1_INFO(inst) ((inst) + 0x0000001B), 0x00000103 +#define BF_IRQ_SL1_FDUC1_FNCO_I_OVER_FLOW0_INFO(inst) ((inst) + 0x0000001B), 0x00000104 +#define BF_IRQ_SL1_FDUC1_FNCO_I_OVER_FLOW1_INFO(inst) ((inst) + 0x0000001B), 0x00000105 +#define BF_IRQ_SL1_FDUC1_FNCO_Q_OVER_FLOW0_INFO(inst) ((inst) + 0x0000001B), 0x00000106 +#define BF_IRQ_SL1_FDUC1_FNCO_Q_OVER_FLOW1_INFO(inst) ((inst) + 0x0000001B), 0x00000107 + +#define REG_CDUC_DAC_ENABLES_ADDR(inst) ((inst) + 0x0000001C) +#define BF_CDUC_DAC_ENABLES0_INFO(inst) ((inst) + 0x0000001C), 0x00000200 +#define BF_CDUC_DAC_ENABLES1_INFO(inst) ((inst) + 0x0000001C), 0x00000202 +#define BF_CDUC_DAC_ENABLES2_INFO(inst) ((inst) + 0x0000001C), 0x00000204 +#define BF_CDUC_DAC_ENABLES3_INFO(inst) ((inst) + 0x0000001C), 0x00000206 + +#define REG_DUC_EN_CFG_ADDR(inst) ((inst) + 0x0000001D) +#define BF_CDUC_EN_INFO(inst) ((inst) + 0x0000001D), 0x00000400 +#define BF_CDUC_SPI_EN_INFO(inst) ((inst) + 0x0000001D), 0x00000106 +#define BF_FDUC_SPI_EN_INFO(inst) ((inst) + 0x0000001D), 0x00000107 + +#define REG_FDUC_EN_SPI_ADDR(inst) ((inst) + 0x0000001E) +#define BF_FDUC_EN_INFO(inst) ((inst) + 0x0000001E), 0x00000800 + +#define REG_FDUC_TEST_MUX_ADDR(inst) ((inst) + 0x0000001F) +#define BF_FDUC_TEST_MUX_INFO(inst) ((inst) + 0x0000001F), 0x00000600 + +#define REG_CFIR_DATA_CTRL_ADDR(inst) ((inst) + 0x00000020) +#define BF_CFIR1_SAME_AS_CFIR0_EN_INFO(inst) ((inst) + 0x00000020), 0x00000100 + +#ifdef USE_PRIVATE_BF +#define REG_LNX_DBG_MUX_SEL_ADDR(inst) ((inst) + 0x00000021) +#define BF_LNX_DBG_MUX_SEL_INFO(inst) ((inst) + 0x00000021), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CFIR_FSRC_DBG_CNT_EN_ADDR(inst) ((inst) + 0x00000022) +#define BF_CFIR_FSRC_DBG_CNT_EN_INFO(inst) ((inst) + 0x00000022), 0x00001000 +#endif /* USE_PRIVATE_BF */ + +#define REG_CFIR_FSRC_DBG_CNT_EN1_ADDR(inst) ((inst) + 0x00000023) + +#ifdef USE_PRIVATE_BF +#define REG_CFIR_FSRC_DBG_MUX_SEL_ADDR(inst) ((inst) + 0x00000024) +#define BF_CFIR_FSRC_DBG_MUX_SEL_INFO(inst) ((inst) + 0x00000024), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_LINX_DBG_CNT_EN_TX_MISC_ADDR(inst) ((inst) + 0x0000033E) +#define BF_LNX_DBG_CNT_EN_INFO(inst) ((inst) + 0x0000033E), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_PROCESS_MON_SEL_ADDR(inst) ((inst) + 0x0000033F) +#define BF_PROCESS_MON_SEL_INFO(inst) ((inst) + 0x0000033F), 0x00000800 + +#endif /* __ADI_APOLLO_BF_TX_MISC_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_tx_pa.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_tx_pa.h new file mode 100644 index 00000000000000..443e11c2c10d24 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_tx_pa.h @@ -0,0 +1,70 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:21 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_TX_PA_H__ +#define __ADI_APOLLO_BF_TX_PA_H__ + +/*============= D E F I N E S ==============*/ +#define TX_PA0_TX_SLICE_0_TX_DIGITAL0 0x61336000 +#define TX_PA1_TX_SLICE_0_TX_DIGITAL0 0x61337000 +#define TX_PA0_TX_SLICE_1_TX_DIGITAL0 0x61536000 +#define TX_PA1_TX_SLICE_1_TX_DIGITAL0 0x61537000 +#define TX_PA0_TX_SLICE_0_TX_DIGITAL1 0x61B36000 +#define TX_PA1_TX_SLICE_0_TX_DIGITAL1 0x61B37000 +#define TX_PA0_TX_SLICE_1_TX_DIGITAL1 0x61D36000 +#define TX_PA1_TX_SLICE_1_TX_DIGITAL1 0x61D37000 + +#define REG_LONG_PA_THRES_LSB_ADDR(inst) ((inst) + 0x00000024) +#define BF_PWR_THRESHOLD_LONG_INFO(inst) ((inst) + 0x00000024), 0x00000D00 + +#define REG_LONG_PA_THRES_MSB_ADDR(inst) ((inst) + 0x00000025) + +#define REG_LONG_PA_AVG_ADDR(inst) ((inst) + 0x00000026) +#define BF_AVG_LONG_WIN_INFO(inst) ((inst) + 0x00000026), 0x00000400 + +#define REG_SHORT_PA_AVG_ADDR(inst) ((inst) + 0x00000027) +#define BF_AVG_SHORT_WIN_INFO(inst) ((inst) + 0x00000027), 0x00000200 + +#define REG_SHORT_PA_THRES_LSB_ADDR(inst) ((inst) + 0x00000028) +#define BF_PWR_THRESHOLD_SHORT_INFO(inst) ((inst) + 0x00000028), 0x00000D00 + +#define REG_SHORT_PA_THRES_MSB_ADDR(inst) ((inst) + 0x00000029) + +#define REG_LONG_PA_POWER_LSB_ADDR(inst) ((inst) + 0x00000030) +#define BF_CALCULATED_PWR_AVG_LONG_INFO(inst) ((inst) + 0x00000030), 0x00000D00 + +#define REG_LONG_PA_POWER_MSB_ADDR(inst) ((inst) + 0x00000031) + +#define REG_SHORT_PA_POWER_LSB_ADDR(inst) ((inst) + 0x00000032) +#define BF_CALCULATED_PWR_AVG_SHORT_INFO(inst) ((inst) + 0x00000032), 0x00000D00 + +#define REG_SHORT_PA_POWER_MSB_ADDR(inst) ((inst) + 0x00000033) + +#define REG_PA_PWR_AVG_CTRL_ADDR(inst) ((inst) + 0x00000034) +#define BF_LONG_PAC_ENABLE_INFO(inst) ((inst) + 0x00000034), 0x00000101 +#define BF_SHORT_PAC_ENABLE_INFO(inst) ((inst) + 0x00000034), 0x00000102 +#define BF_PA_AVG_ERR_INFO(inst) ((inst) + 0x00000034), 0x00000103 +#define BF_PA_PWR_AVG_ERR_CLEAR_INFO(inst) ((inst) + 0x00000034), 0x00000104 +#define BF_PA_CLK_ENA_INFO(inst) ((inst) + 0x00000034), 0x00000107 + +#define REG_PA_PWR_AVG_IRQ_ADDR(inst) ((inst) + 0x00000035) +#define BF_PA_AVG_ERR_IRQ_INFO(inst) ((inst) + 0x00000035), 0x00000100 +#define BF_PA_AVG_ERR_IRQ_EN_INFO(inst) ((inst) + 0x00000035), 0x00000101 +#define BF_LONG_WIN_DONE_IRQ_INFO(inst) ((inst) + 0x00000035), 0x00000102 +#define BF_LONG_WIN_DONE_IRQ_EN_INFO(inst) ((inst) + 0x00000035), 0x00000103 +#define BF_SHORT_WIN_DONE_IRQ_INFO(inst) ((inst) + 0x00000035), 0x00000104 +#define BF_SHORT_WIN_DONE_IRQ_EN_INFO(inst) ((inst) + 0x00000035), 0x00000105 + +#endif /* __ADI_APOLLO_BF_TX_PA_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_tx_paprot.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_tx_paprot.h new file mode 100644 index 00000000000000..a300b6dd4fb474 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_tx_paprot.h @@ -0,0 +1,144 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:21 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_TX_PAPROT_H__ +#define __ADI_APOLLO_BF_TX_PAPROT_H__ + +/*============= D E F I N E S ==============*/ +#define TX_PAPROT0_TX_SLICE_0_TX_DIGITAL0 0x61202000 +#define TX_PAPROT1_TX_SLICE_0_TX_DIGITAL0 0x61203000 +#define TX_PAPROT0_TX_SLICE_1_TX_DIGITAL0 0x61402000 +#define TX_PAPROT1_TX_SLICE_1_TX_DIGITAL0 0x61403000 +#define TX_PAPROT0_TX_SLICE_0_TX_DIGITAL1 0x61A02000 +#define TX_PAPROT1_TX_SLICE_0_TX_DIGITAL1 0x61A03000 +#define TX_PAPROT0_TX_SLICE_1_TX_DIGITAL1 0x61C02000 +#define TX_PAPROT1_TX_SLICE_1_TX_DIGITAL1 0x61C03000 + +#define REG_ALARM_CNTRL0_ADDR(inst) ((inst) + 0x00000000) +#define BF_JESD_ERR_EN_INFO(inst) ((inst) + 0x00000000), 0x00000100 +#ifdef USE_PRIVATE_BF +#define BF_CLK_STABILITY_CHECK_BYPASS_INFO(inst) ((inst) + 0x00000000), 0x00000101 +#endif /* USE_PRIVATE_BF */ +#define BF_AUTO_DYN_RECONF_EN_INFO(inst) ((inst) + 0x00000000), 0x00000102 +#ifdef USE_PRIVATE_BF +#define BF_RESET_DYN_SYNC_SM_INFO(inst) ((inst) + 0x00000000), 0x00000103 +#endif /* USE_PRIVATE_BF */ +#define BF_AVG_PWR_ERR_EN_INFO(inst) ((inst) + 0x00000000), 0x00000104 +#define BF_SRL_ERR_EN_INFO(inst) ((inst) + 0x00000000), 0x00000105 +#define BF_RAMPDWN_TO_PAPIN_EN_INFO(inst) ((inst) + 0x00000000), 0x00000106 +#ifdef USE_PRIVATE_BF +#define BF_RESET_ALARM_INFO(inst) ((inst) + 0x00000000), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#define REG_ALARM_CNTRL1_ADDR(inst) ((inst) + 0x00000001) +#define BF_DATA_READY_SEL_RAMP_INFO(inst) ((inst) + 0x00000001), 0x00000100 +#define BF_FORCE_ZERO_FLUSH_EN_INFO(inst) ((inst) + 0x00000001), 0x00000101 +#define BF_FORCE_ZERO_FLUSH_SPI_INFO(inst) ((inst) + 0x00000001), 0x00000102 +#define BF_JESD_ERR_SEL_RAMP_INFO(inst) ((inst) + 0x00000001), 0x00000103 +#define BF_DP_ZERO_FLUSH_SEL_INFO(inst) ((inst) + 0x00000001), 0x00000204 +#define BF_DATA_READY_AUTO_CONFIG_EN_INFO(inst) ((inst) + 0x00000001), 0x00000106 +#define BF_JESD_ERR_AUTO_CONFIG_EN_INFO(inst) ((inst) + 0x00000001), 0x00000107 + +#define REG_PASM_CTRL0_ADDR(inst) ((inst) + 0x00000002) +#define BF_SKIP_RAMP_DWN_INFO(inst) ((inst) + 0x00000002), 0x00000100 +#define BF_RAMP_DWN_TIMER_EN_INFO(inst) ((inst) + 0x00000002), 0x00000101 +#define BF_RAMP_UP_TIMER_EN_INFO(inst) ((inst) + 0x00000002), 0x00000102 +#define BF_ENABLE_PAPROTSM_INFO(inst) ((inst) + 0x00000002), 0x00000103 +#define BF_SKIP_RAMP_UP_INFO(inst) ((inst) + 0x00000002), 0x00000104 +#define BF_HOLD_SAMPLE_EN_INFO(inst) ((inst) + 0x00000002), 0x00000105 +#define BF_RESET_RAMP_GAIN_INFO(inst) ((inst) + 0x00000002), 0x00000106 +#define BF_DRIVE_SM_BY_DIG_EN_INFO(inst) ((inst) + 0x00000002), 0x00000107 + +#define REG_PASM_CTRL1_ADDR(inst) ((inst) + 0x00000003) +#define BF_WAIT_CLK_MAXCNT_INFO(inst) ((inst) + 0x00000003), 0x00000800 + +#define REG_HOLD_TIMER_COUNT_ADDR(inst) ((inst) + 0x00000004) +#define BF_HOLD_TIMER_COUNT_INFO(inst) ((inst) + 0x00000004), 0x00000800 + +#define REG_RAMP_DWN_TIMER_VAL_LSB_ADDR(inst) ((inst) + 0x00000007) +#define BF_RAMP_DWN_TIMER_VAL_INFO(inst) ((inst) + 0x00000007), 0x00001000 + +#define REG_RAMP_DWN_TIMER_VAL_MSB_ADDR(inst) ((inst) + 0x00000008) + +#define REG_RAMP_UP_TIMER_VAL_LSB_ADDR(inst) ((inst) + 0x00000009) +#define BF_RAMP_UP_TIMER_VAL_INFO(inst) ((inst) + 0x00000009), 0x00001000 + +#define REG_RAMP_UP_TIMER_VAL_MSB_ADDR(inst) ((inst) + 0x0000000A) + +#define REG_SM_STATUS_ADDR(inst) ((inst) + 0x0000000B) +#define BF_MAIN_SM_CURRENT_INFO(inst) ((inst) + 0x0000000B), 0x00000500 +#define BF_CLOCKS_SM_CURRENT_INFO(inst) ((inst) + 0x0000000B), 0x00000305 + +#define REG_MANUAL_CTRL_ADDR(inst) ((inst) + 0x00000021) +#define BF_FORCE_RAMP_DWN_INFO(inst) ((inst) + 0x00000021), 0x00000100 +#define BF_FORCE_RAMP_DWN_EN_INFO(inst) ((inst) + 0x00000021), 0x00000101 +#define BF_FORCE_RAMP_UP_INFO(inst) ((inst) + 0x00000021), 0x00000102 +#define BF_FORCE_RAMP_UP_EN_INFO(inst) ((inst) + 0x00000021), 0x00000103 +#define BF_FORCE_RAMPS_DYN_RECFIG_EN_INFO(inst) ((inst) + 0x00000021), 0x00000104 +#define BF_ZERO_DETECT_EN_INFO(inst) ((inst) + 0x00000021), 0x00000105 + +#define REG_GAIN_INC_STEP_ADDR(inst) ((inst) + 0x00000022) +#define BF_GAIN_INC_STEP_INFO(inst) ((inst) + 0x00000022), 0x00000800 + +#define REG_GAIN_DEC_STEP_ADDR(inst) ((inst) + 0x0000002A) +#define BF_GAIN_DEC_STEP_INFO(inst) ((inst) + 0x0000002A), 0x00000800 + +#define REG_GAIN_VALUE_ADDR(inst) ((inst) + 0x00000032) +#define BF_GAIN_MAX_VAL_INFO(inst) ((inst) + 0x00000032), 0x00000800 + +#define REG_RAMP_CNTRL_ADDR(inst) ((inst) + 0x00000033) +#define BF_ENABLE_GAIN_INFO(inst) ((inst) + 0x00000033), 0x00000101 +#define BF_ENABLE_RAMP_INFO(inst) ((inst) + 0x00000033), 0x00000102 + +#define REG_ZIF_RAMP_CTRL_ADDR(inst) ((inst) + 0x00000034) +#define BF_TRIG_RAMPDWN_IQ_TOGETHER_EN_INFO(inst) ((inst) + 0x00000034), 0x00000100 +#define BF_TRIG_RAMPDWN_EXT_EN_INFO(inst) ((inst) + 0x00000034), 0x00000101 +#define BF_TRIG_RAMPUP_IQ_TOGETHER_EN_INFO(inst) ((inst) + 0x00000034), 0x00000102 +#define BF_TRIG_RAMPUP_EXT_EN_INFO(inst) ((inst) + 0x00000034), 0x00000103 + +#define REG_SLEW_RATE_CTRL_ADDR(inst) ((inst) + 0x00000040) +#define BF_SR_CALCULATION_EN_INFO(inst) ((inst) + 0x00000040), 0x00000100 +#define BF_SR_ERR_SELF_CLR_EN_INFO(inst) ((inst) + 0x00000040), 0x00000101 +#define BF_SR_PATH_SEL_INFO(inst) ((inst) + 0x00000040), 0x00000502 +#define BF_SR_MANUAL_CLR_INFO(inst) ((inst) + 0x00000040), 0x00000107 + +#define REG_SR_THRESHOLD0_ADDR(inst) ((inst) + 0x00000041) +#define BF_SR_THRESHOLD_INFO(inst) ((inst) + 0x00000041), 0x00001100 + +#define REG_SR_THRESHOLD1_ADDR(inst) ((inst) + 0x00000042) + +#define REG_SR_THRESHOLD2_ADDR(inst) ((inst) + 0x00000043) + +#define REG_SR_CALCULATED_DATA_LSB_ADDR(inst) ((inst) + 0x00000044) +#define BF_SR_CALCULATED_INFO(inst) ((inst) + 0x00000044), 0x00001100 + +#define REG_SR_CALCULATED_DATA_ISB_ADDR(inst) ((inst) + 0x00000045) + +#define REG_SR_CALCULATED_DATA_MSB_ADDR(inst) ((inst) + 0x00000046) +#define BF_SR_DETECTED_ERR_INFO(inst) ((inst) + 0x00000046), 0x00000107 + +#define REG_PAPROT_IRQ_ENABLE_ADDR(inst) ((inst) + 0x00000060) +#define BF_SLEW_RATE_ERR_IRQ_EN_INFO(inst) ((inst) + 0x00000060), 0x00000101 + +#define REG_PAPROT_IRQ_STATUS_ADDR(inst) ((inst) + 0x00000061) +#define BF_SLEW_RATE_ERR_IRQ_INFO(inst) ((inst) + 0x00000061), 0x00000101 + +#define REG_FORCE_CLKS_ADDR(inst) ((inst) + 0x00000080) +#ifdef USE_PRIVATE_BF +#define BF_SR_CLK_EN_INFO(inst) ((inst) + 0x00000080), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_GAIN_CLK_EN_INFO(inst) ((inst) + 0x00000080), 0x00000101 + +#endif /* __ADI_APOLLO_BF_TX_PAPROT_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_txen_power_ctrl.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_txen_power_ctrl.h new file mode 100644 index 00000000000000..19ecc154161a86 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_txen_power_ctrl.h @@ -0,0 +1,85 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:20 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_TXEN_POWER_CTRL_H__ +#define __ADI_APOLLO_BF_TXEN_POWER_CTRL_H__ + +/*============= D E F I N E S ==============*/ +#define RXEN_POWER_CTRL0_RX_SLICE_0_RX_DIGITAL0 0x6036F000 +#define RXEN_POWER_CTRL1_RX_SLICE_0_RX_DIGITAL0 0x60370000 +#define RXEN_POWER_CTRL0_RX_SLICE_1_RX_DIGITAL0 0x6056F000 +#define RXEN_POWER_CTRL1_RX_SLICE_1_RX_DIGITAL0 0x60570000 +#define RXEN_POWER_CTRL0_RX_SLICE_0_RX_DIGITAL1 0x60B6F000 +#define RXEN_POWER_CTRL1_RX_SLICE_0_RX_DIGITAL1 0x60B70000 +#define RXEN_POWER_CTRL0_RX_SLICE_1_RX_DIGITAL1 0x60D6F000 +#define RXEN_POWER_CTRL1_RX_SLICE_1_RX_DIGITAL1 0x60D70000 +#define TXEN_POWER_CTRL0_TX_SLICE_0_TX_DIGITAL0 0x61208000 +#define TXEN_POWER_CTRL1_TX_SLICE_0_TX_DIGITAL0 0x61209000 +#define TXEN_POWER_CTRL0_TX_SLICE_1_TX_DIGITAL0 0x61408000 +#define TXEN_POWER_CTRL1_TX_SLICE_1_TX_DIGITAL0 0x61409000 +#define TXEN_POWER_CTRL0_TX_SLICE_0_TX_DIGITAL1 0x61A08000 +#define TXEN_POWER_CTRL1_TX_SLICE_0_TX_DIGITAL1 0x61A09000 +#define TXEN_POWER_CTRL0_TX_SLICE_1_TX_DIGITAL1 0x61C08000 +#define TXEN_POWER_CTRL1_TX_SLICE_1_TX_DIGITAL1 0x61C09000 + +#define REG_TXEN_PWR_CRTL_ADDR(inst) ((inst) + 0x00000000) +#define BF_SM_EN_INFO(inst) ((inst) + 0x00000000), 0x00000100 +#define BF_SPI_TXEN_ENA_INFO(inst) ((inst) + 0x00000000), 0x00000101 +#define BF_SPI_TXEN_INFO(inst) ((inst) + 0x00000000), 0x00000102 +#define BF_SEL_CNT_RATE_INFO(inst) ((inst) + 0x00000000), 0x00000103 + +#define REG_TXEN_DAC_EDGES_ADDR(inst) ((inst) + 0x00000001) +#define BF_DAC_RISE_INFO(inst) ((inst) + 0x00000001), 0x00000200 +#define BF_DAC_FALL_INFO(inst) ((inst) + 0x00000001), 0x00000202 + +#define REG_TXEN_DIG_EDGES_ADDR(inst) ((inst) + 0x00000002) +#define BF_DIG_RISE_INFO(inst) ((inst) + 0x00000002), 0x00000200 +#define BF_DIG_FALL_INFO(inst) ((inst) + 0x00000002), 0x00000202 + +#define REG_TXEN_PA_EDGES_ADDR(inst) ((inst) + 0x00000003) +#define BF_PA_RISE_INFO(inst) ((inst) + 0x00000003), 0x00000200 +#define BF_PA_FALL_INFO(inst) ((inst) + 0x00000003), 0x00000202 + +#define REG_MAX_A_ADDR(inst) ((inst) + 0x00000004) +#define BF_COUNT_MAXA_INFO(inst) ((inst) + 0x00000004), 0x00000800 + +#define REG_MAX_B_ADDR(inst) ((inst) + 0x00000005) +#define BF_COUNT_MAXB_INFO(inst) ((inst) + 0x00000005), 0x00000800 + +#define REG_MAX_C_ADDR(inst) ((inst) + 0x00000006) +#define BF_COUNT_MAXC_INFO(inst) ((inst) + 0x00000006), 0x00000800 + +#define REG_MAX_D_ADDR(inst) ((inst) + 0x00000007) +#define BF_COUNT_MAXD_INFO(inst) ((inst) + 0x00000007), 0x00000800 + +#define REG_MAX_E_ADDR(inst) ((inst) + 0x00000008) +#define BF_COUNT_MAXE_INFO(inst) ((inst) + 0x00000008), 0x00000800 + +#define REG_MAX_F_ADDR(inst) ((inst) + 0x00000009) +#define BF_COUNT_MAXF_INFO(inst) ((inst) + 0x00000009), 0x00000800 + +#define REG_COUNTER_READ_ADDR(inst) ((inst) + 0x0000000A) +#define BF_COUNT_INFO(inst) ((inst) + 0x0000000A), 0x00000800 + +#define REG_STATES_READ_ADDR(inst) ((inst) + 0x0000000B) +#define BF_STATES_INFO(inst) ((inst) + 0x0000000B), 0x00000800 + +#define REG_TXEN_SEL_ADDR(inst) ((inst) + 0x00000010) +#define BF_TXEN_SEL0_INFO(inst) ((inst) + 0x00000010), 0x00000200 +#define BF_TXEN_SEL1_INFO(inst) ((inst) + 0x00000010), 0x00000202 +#define BF_TXEN_SEL2_INFO(inst) ((inst) + 0x00000010), 0x00000204 +#define BF_TXEN_SEL3_INFO(inst) ((inst) + 0x00000010), 0x00000206 + +#endif /* __ADI_APOLLO_BF_TXEN_POWER_CTRL_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_txrx_cfir_coeff.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_txrx_cfir_coeff.h new file mode 100644 index 00000000000000..41e7811b853895 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_txrx_cfir_coeff.h @@ -0,0 +1,133 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:20 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_TXRX_CFIR_COEFF_H__ +#define __ADI_APOLLO_BF_TXRX_CFIR_COEFF_H__ + +/*============= D E F I N E S ==============*/ +#define RX_CFIR_COEFF_RX_SLICE_0_RX_DIGITAL0 0x60365000 +#define RX_CFIR_COEFF_RX_SLICE_1_RX_DIGITAL0 0x60565000 +#define RX_CFIR_COEFF_RX_SLICE_0_RX_DIGITAL1 0x60B65000 +#define RX_CFIR_COEFF_RX_SLICE_1_RX_DIGITAL1 0x60D65000 +#define TX_CFIR_COEFF_TX_SLICE_0_TX_DIGITAL0 0x61305000 +#define TX_CFIR_COEFF_TX_SLICE_1_TX_DIGITAL0 0x61505000 +#define TX_CFIR_COEFF_TX_SLICE_0_TX_DIGITAL1 0x61B05000 +#define TX_CFIR_COEFF_TX_SLICE_1_TX_DIGITAL1 0x61D05000 + +#define REG_I_COEFF_0_LSB_1_ADDR(inst, n) ((inst) + 0x00000000 + 2 * (n)) +#define BF_I_COEFF_0_1_INFO(inst, n) ((inst) + 0x00000000 + 2 * (n)), 0x00001000 + +#define REG_I_COEFF_0_MSB_1_ADDR(inst, n) ((inst) + 0x00000001 + 2 * (n)) + +#define REG_Q_COEFF_0_LSB_1_ADDR(inst, n) ((inst) + 0x00000020 + 2 * (n)) +#define BF_Q_COEFF_0_1_INFO(inst, n) ((inst) + 0x00000020 + 2 * (n)), 0x00001000 + +#define REG_Q_COEFF_0_MSB_1_ADDR(inst, n) ((inst) + 0x00000021 + 2 * (n)) + +#define REG_I_COEFF_1_LSB_1_ADDR(inst, n) ((inst) + 0x00000040 + 2 * (n)) +#define BF_I_COEFF_1_1_INFO(inst, n) ((inst) + 0x00000040 + 2 * (n)), 0x00001000 + +#define REG_I_COEFF_1_MSB_1_ADDR(inst, n) ((inst) + 0x00000041 + 2 * (n)) + +#define REG_Q_COEFF_1_LSB_1_ADDR(inst, n) ((inst) + 0x00000060 + 2 * (n)) +#define BF_Q_COEFF_1_1_INFO(inst, n) ((inst) + 0x00000060 + 2 * (n)), 0x00001000 + +#define REG_Q_COEFF_1_MSB_1_ADDR(inst, n) ((inst) + 0x00000061 + 2 * (n)) + +#define REG_I_COEFF_2_LSB_1_ADDR(inst, n) ((inst) + 0x00000080 + 2 * (n)) +#define BF_I_COEFF_2_1_INFO(inst, n) ((inst) + 0x00000080 + 2 * (n)), 0x00001000 + +#define REG_I_COEFF_2_MSB_1_ADDR(inst, n) ((inst) + 0x00000081 + 2 * (n)) + +#define REG_Q_COEFF_2_LSB_1_ADDR(inst, n) ((inst) + 0x000000A0 + 2 * (n)) +#define BF_Q_COEFF_2_1_INFO(inst, n) ((inst) + 0x000000A0 + 2 * (n)), 0x00001000 + +#define REG_Q_COEFF_2_MSB_1_ADDR(inst, n) ((inst) + 0x000000A1 + 2 * (n)) + +#define REG_I_COEFF_3_LSB_1_ADDR(inst, n) ((inst) + 0x000000C0 + 2 * (n)) +#define BF_I_COEFF_3_1_INFO(inst, n) ((inst) + 0x000000C0 + 2 * (n)), 0x00001000 + +#define REG_I_COEFF_3_MSB_1_ADDR(inst, n) ((inst) + 0x000000C1 + 2 * (n)) + +#define REG_Q_COEFF_3_LSB_1_ADDR(inst, n) ((inst) + 0x000000E0 + 2 * (n)) +#define BF_Q_COEFF_3_1_INFO(inst, n) ((inst) + 0x000000E0 + 2 * (n)), 0x00001000 + +#define REG_Q_COEFF_3_MSB_1_ADDR(inst, n) ((inst) + 0x000000E1 + 2 * (n)) + +#define REG_I_COEFF_0_LSB_2_ADDR(inst, n) ((inst) + 0x00000100 + 2 * (n)) +#define BF_I_COEFF_0_2_INFO(inst, n) ((inst) + 0x00000100 + 2 * (n)), 0x00001000 + +#define REG_I_COEFF_0_MSB_2_ADDR(inst, n) ((inst) + 0x00000101 + 2 * (n)) + +#define REG_Q_COEFF_0_LSB_2_ADDR(inst, n) ((inst) + 0x00000120 + 2 * (n)) +#define BF_Q_COEFF_0_2_INFO(inst, n) ((inst) + 0x00000120 + 2 * (n)), 0x00001000 + +#define REG_Q_COEFF_0_MSB_2_ADDR(inst, n) ((inst) + 0x00000121 + 2 * (n)) + +#define REG_I_COEFF_1_LSB_2_ADDR(inst, n) ((inst) + 0x00000140 + 2 * (n)) +#define BF_I_COEFF_1_2_INFO(inst, n) ((inst) + 0x00000140 + 2 * (n)), 0x00001000 + +#define REG_I_COEFF_1_MSB_2_ADDR(inst, n) ((inst) + 0x00000141 + 2 * (n)) + +#define REG_Q_COEFF_1_LSB_2_ADDR(inst, n) ((inst) + 0x00000160 + 2 * (n)) +#define BF_Q_COEFF_1_2_INFO(inst, n) ((inst) + 0x00000160 + 2 * (n)), 0x00001000 + +#define REG_Q_COEFF_1_MSB_2_ADDR(inst, n) ((inst) + 0x00000161 + 2 * (n)) + +#define REG_I_COEFF_2_LSB_2_ADDR(inst, n) ((inst) + 0x00000180 + 2 * (n)) +#define BF_I_COEFF_2_2_INFO(inst, n) ((inst) + 0x00000180 + 2 * (n)), 0x00001000 + +#define REG_I_COEFF_2_MSB_2_ADDR(inst, n) ((inst) + 0x00000181 + 2 * (n)) + +#define REG_Q_COEFF_2_LSB_2_ADDR(inst, n) ((inst) + 0x000001A0 + 2 * (n)) +#define BF_Q_COEFF_2_2_INFO(inst, n) ((inst) + 0x000001A0 + 2 * (n)), 0x00001000 + +#define REG_Q_COEFF_2_MSB_2_ADDR(inst, n) ((inst) + 0x000001A1 + 2 * (n)) + +#define REG_I_COEFF_3_LSB_2_ADDR(inst, n) ((inst) + 0x000001C0 + 2 * (n)) +#define BF_I_COEFF_3_2_INFO(inst, n) ((inst) + 0x000001C0 + 2 * (n)), 0x00001000 + +#define REG_I_COEFF_3_MSB_2_ADDR(inst, n) ((inst) + 0x000001C1 + 2 * (n)) + +#define REG_Q_COEFF_3_LSB_2_ADDR(inst, n) ((inst) + 0x000001E0 + 2 * (n)) +#define BF_Q_COEFF_3_2_INFO(inst, n) ((inst) + 0x000001E0 + 2 * (n)), 0x00001000 + +#define REG_Q_COEFF_3_MSB_2_ADDR(inst, n) ((inst) + 0x000001E1 + 2 * (n)) + +#define REG_COEFF_SEL_0_1_ADDR(inst, n) ((inst) + 0x00000201 + 1 * (n)) +#define BF_COEFF_SEL_0_1_INFO(inst, n) ((inst) + 0x00000201 + 1 * (n)), 0x00000600 + +#define REG_COEFF_SEL_1_1_ADDR(inst, n) ((inst) + 0x00000211 + 1 * (n)) +#define BF_COEFF_SEL_1_1_INFO(inst, n) ((inst) + 0x00000211 + 1 * (n)), 0x00000600 + +#define REG_COEFF_SEL_2_1_ADDR(inst, n) ((inst) + 0x00000221 + 1 * (n)) +#define BF_COEFF_SEL_2_1_INFO(inst, n) ((inst) + 0x00000221 + 1 * (n)), 0x00000600 + +#define REG_COEFF_SEL_3_1_ADDR(inst, n) ((inst) + 0x00000231 + 1 * (n)) +#define BF_COEFF_SEL_3_1_INFO(inst, n) ((inst) + 0x00000231 + 1 * (n)), 0x00000600 + +#define REG_COEFF_SEL_0_2_ADDR(inst, n) ((inst) + 0x00000241 + 1 * (n)) +#define BF_COEFF_SEL_0_2_INFO(inst, n) ((inst) + 0x00000241 + 1 * (n)), 0x00000600 + +#define REG_COEFF_SEL_1_2_ADDR(inst, n) ((inst) + 0x00000251 + 1 * (n)) +#define BF_COEFF_SEL_1_2_INFO(inst, n) ((inst) + 0x00000251 + 1 * (n)), 0x00000600 + +#define REG_COEFF_SEL_2_2_ADDR(inst, n) ((inst) + 0x00000261 + 1 * (n)) +#define BF_COEFF_SEL_2_2_INFO(inst, n) ((inst) + 0x00000261 + 1 * (n)), 0x00000600 + +#define REG_COEFF_SEL_3_2_ADDR(inst, n) ((inst) + 0x00000271 + 1 * (n)) +#define BF_COEFF_SEL_3_2_INFO(inst, n) ((inst) + 0x00000271 + 1 * (n)), 0x00000600 + +#endif /* __ADI_APOLLO_BF_TXRX_CFIR_COEFF_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_txrx_cfir_top.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_txrx_cfir_top.h new file mode 100644 index 00000000000000..d6c29ca413a82d --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_txrx_cfir_top.h @@ -0,0 +1,164 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:20 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_TXRX_CFIR_TOP_H__ +#define __ADI_APOLLO_BF_TXRX_CFIR_TOP_H__ + +/*============= D E F I N E S ==============*/ +#define RX_CFIR_TOP_RX_SLICE_0_RX_DIGITAL0 0x60364000 +#define RX_CFIR_TOP_RX_SLICE_1_RX_DIGITAL0 0x60564000 +#define RX_CFIR_TOP_RX_SLICE_0_RX_DIGITAL1 0x60B64000 +#define RX_CFIR_TOP_RX_SLICE_1_RX_DIGITAL1 0x60D64000 +#define TX_CFIR_TOP_TX_SLICE_0_TX_DIGITAL0 0x61304000 +#define TX_CFIR_TOP_TX_SLICE_1_TX_DIGITAL0 0x61504000 +#define TX_CFIR_TOP_TX_SLICE_0_TX_DIGITAL1 0x61B04000 +#define TX_CFIR_TOP_TX_SLICE_1_TX_DIGITAL1 0x61D04000 + +#define REG_CFIR_MODE_ADDR(inst) ((inst) + 0x00000000) +#define BF_CFIR_BYPASS_INFO(inst) ((inst) + 0x00000000), 0x00000100 + +#define REG_CFIR_CFG_ADDR(inst) ((inst) + 0x00000001) +#define BF_CFIR_SPARSE_FILT_EN_INFO(inst) ((inst) + 0x00000001), 0x00000100 +#define BF_CFIR_32TAPS_EN_INFO(inst) ((inst) + 0x00000001), 0x00000101 + +#define REG_CFIR_PROFILE_ADDR(inst) ((inst) + 0x00000002) +#define BF_COEFF_PROFILE_SEL_INFO(inst) ((inst) + 0x00000002), 0x00000400 +#define BF_GPIO_PROFILE_EN_INFO(inst) ((inst) + 0x00000002), 0x00000104 + +#define REG_CFIR_TRIGGER_ADDR(inst) ((inst) + 0x00000003) +#define BF_TRIGGER_EN_TXRX_CFIR_TOP_INFO(inst) ((inst) + 0x00000003), 0x00000100 +#define BF_COEFF_TRANSFER_INFO(inst) ((inst) + 0x00000003), 0x00000101 + +#define REG_CFIR_GAIN0_1_ADDR(inst) ((inst) + 0x00000010) +#define BF_CFIR_GAIN0_1_INFO(inst) ((inst) + 0x00000010), 0x00000300 + +#define REG_CFIR_GAIN1_1_ADDR(inst) ((inst) + 0x00000011) +#define BF_CFIR_GAIN1_1_INFO(inst) ((inst) + 0x00000011), 0x00000300 + +#define REG_CFIR_GAIN2_1_ADDR(inst) ((inst) + 0x00000012) +#define BF_CFIR_GAIN2_1_INFO(inst) ((inst) + 0x00000012), 0x00000300 + +#define REG_CFIR_GAIN3_1_ADDR(inst) ((inst) + 0x00000013) +#define BF_CFIR_GAIN3_1_INFO(inst) ((inst) + 0x00000013), 0x00000300 + +#define REG_CFIR_GAIN0_2_ADDR(inst) ((inst) + 0x00000014) +#define BF_CFIR_GAIN0_2_INFO(inst) ((inst) + 0x00000014), 0x00000300 + +#define REG_CFIR_GAIN1_2_ADDR(inst) ((inst) + 0x00000015) +#define BF_CFIR_GAIN1_2_INFO(inst) ((inst) + 0x00000015), 0x00000300 + +#define REG_CFIR_GAIN2_2_ADDR(inst) ((inst) + 0x00000016) +#define BF_CFIR_GAIN2_2_INFO(inst) ((inst) + 0x00000016), 0x00000300 + +#define REG_CFIR_GAIN3_2_ADDR(inst) ((inst) + 0x00000017) +#define BF_CFIR_GAIN3_2_INFO(inst) ((inst) + 0x00000017), 0x00000300 + +#ifdef USE_PRIVATE_BF +#define REG_CFIR_BIST_CTRL_ADDR(inst) ((inst) + 0x00000018) +#define BF_CFIR_BIST_EN_INFO(inst) ((inst) + 0x00000018), 0x00000100 +#define BF_CFIR_BIST_INIT_INFO(inst) ((inst) + 0x00000018), 0x00000101 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CFIR_BIST_CRC_LSB_ADDR(inst) ((inst) + 0x00000019) +#define BF_CFIR_BIST_CRC_INFO(inst) ((inst) + 0x00000019), 0x00001000 +#endif /* USE_PRIVATE_BF */ + +#define REG_CFIR_BIST_CRC_MSB_ADDR(inst) ((inst) + 0x0000001A) + +#define REG_I_COMP_SCAL_LSB_1_ADDR(inst, n) ((inst) + 0x00000020 + 2 * (n)) +#define BF_I_COMPLEX_SCALAR_1_INFO(inst, n) ((inst) + 0x00000020 + 2 * (n)), 0x00001000 + +#define REG_I_COMP_SCAL_MSB_1_ADDR(inst, n) ((inst) + 0x00000021 + 2 * (n)) + +#define REG_Q_COMP_SCAL_LSB_1_ADDR(inst, n) ((inst) + 0x00000028 + 2 * (n)) +#define BF_Q_COMPLEX_SCALAR_1_INFO(inst, n) ((inst) + 0x00000028 + 2 * (n)), 0x00001000 + +#define REG_Q_COMP_SCAL_MSB_1_ADDR(inst, n) ((inst) + 0x00000029 + 2 * (n)) + +#define REG_I_COMP_SCAL_LSB_2_ADDR(inst, n) ((inst) + 0x00000030 + 2 * (n)) +#define BF_I_COMPLEX_SCALAR_2_INFO(inst, n) ((inst) + 0x00000030 + 2 * (n)), 0x00001000 + +#define REG_I_COMP_SCAL_MSB_2_ADDR(inst, n) ((inst) + 0x00000031 + 2 * (n)) + +#define REG_Q_COMP_SCAL_LSB_2_ADDR(inst, n) ((inst) + 0x00000038 + 2 * (n)) +#define BF_Q_COMPLEX_SCALAR_2_INFO(inst, n) ((inst) + 0x00000038 + 2 * (n)), 0x00001000 + +#define REG_Q_COMP_SCAL_MSB_2_ADDR(inst, n) ((inst) + 0x00000039 + 2 * (n)) + +#define REG_DPATH0_MEM_SEL_1_ADDR(inst) ((inst) + 0x00000040) +#define BF_DPATH0_MEM_SEL0_1_INFO(inst) ((inst) + 0x00000040), 0x00000200 +#define BF_DPATH0_MEM_SEL1_1_INFO(inst) ((inst) + 0x00000040), 0x00000202 +#define BF_DPATH0_MEM_SEL2_1_INFO(inst) ((inst) + 0x00000040), 0x00000204 + +#define REG_DPATH1_MEM_SEL_1_ADDR(inst) ((inst) + 0x00000041) +#define BF_DPATH1_MEM_SEL0_1_INFO(inst) ((inst) + 0x00000041), 0x00000200 +#define BF_DPATH1_MEM_SEL1_1_INFO(inst) ((inst) + 0x00000041), 0x00000202 +#define BF_DPATH1_MEM_SEL2_1_INFO(inst) ((inst) + 0x00000041), 0x00000204 + +#define REG_DPATH2_MEM_SEL_1_ADDR(inst) ((inst) + 0x00000042) +#define BF_DPATH2_MEM_SEL0_1_INFO(inst) ((inst) + 0x00000042), 0x00000200 +#define BF_DPATH2_MEM_SEL1_1_INFO(inst) ((inst) + 0x00000042), 0x00000202 +#define BF_DPATH2_MEM_SEL2_1_INFO(inst) ((inst) + 0x00000042), 0x00000204 + +#define REG_DPATH3_MEM_SEL_1_ADDR(inst) ((inst) + 0x00000043) +#define BF_DPATH3_MEM_SEL0_1_INFO(inst) ((inst) + 0x00000043), 0x00000200 +#define BF_DPATH3_MEM_SEL1_1_INFO(inst) ((inst) + 0x00000043), 0x00000202 +#define BF_DPATH3_MEM_SEL2_1_INFO(inst) ((inst) + 0x00000043), 0x00000204 + +#define REG_DPATH0_MEM_SEL_2_ADDR(inst) ((inst) + 0x00000044) +#define BF_DPATH0_MEM_SEL0_2_INFO(inst) ((inst) + 0x00000044), 0x00000200 +#define BF_DPATH0_MEM_SEL1_2_INFO(inst) ((inst) + 0x00000044), 0x00000202 +#define BF_DPATH0_MEM_SEL2_2_INFO(inst) ((inst) + 0x00000044), 0x00000204 + +#define REG_DPATH1_MEM_SEL_2_ADDR(inst) ((inst) + 0x00000045) +#define BF_DPATH1_MEM_SEL0_2_INFO(inst) ((inst) + 0x00000045), 0x00000200 +#define BF_DPATH1_MEM_SEL1_2_INFO(inst) ((inst) + 0x00000045), 0x00000202 +#define BF_DPATH1_MEM_SEL2_2_INFO(inst) ((inst) + 0x00000045), 0x00000204 + +#define REG_DPATH2_MEM_SEL_2_ADDR(inst) ((inst) + 0x00000046) +#define BF_DPATH2_MEM_SEL0_2_INFO(inst) ((inst) + 0x00000046), 0x00000200 +#define BF_DPATH2_MEM_SEL1_2_INFO(inst) ((inst) + 0x00000046), 0x00000202 +#define BF_DPATH2_MEM_SEL2_2_INFO(inst) ((inst) + 0x00000046), 0x00000204 + +#define REG_DPATH3_MEM_SEL_2_ADDR(inst) ((inst) + 0x00000047) +#define BF_DPATH3_MEM_SEL0_2_INFO(inst) ((inst) + 0x00000047), 0x00000200 +#define BF_DPATH3_MEM_SEL1_2_INFO(inst) ((inst) + 0x00000047), 0x00000202 +#define BF_DPATH3_MEM_SEL2_2_INFO(inst) ((inst) + 0x00000047), 0x00000204 + +#ifdef USE_PRIVATE_BF +#define REG_CFIR_CLK_OFFSET_WR_EN_ADDR(inst) ((inst) + 0x00000048) +#define BF_CLK_OFFSET_WR_EN_TXRX_CFIR_TOP_INFO(inst) ((inst) + 0x00000048), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CFIR_ENGCLK_PH0_OFFSET_ADDR(inst, n) ((inst) + 0x00000049 + 1 * (n)) +#define BF_ENGCLK_PH0_OFFSET_INFO(inst, n) ((inst) + 0x00000049 + 1 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CFIR_ENGCLK_PH4_OFFSET_ADDR(inst, n) ((inst) + 0x0000004D + 1 * (n)) +#define BF_ENGCLK_PH4_OFFSET_INFO(inst, n) ((inst) + 0x0000004D + 1 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_CFIR_IRQ_ENABLE_ADDR(inst) ((inst) + 0x00000051) +#define BF_IRQ_ENABLE_I_TXRX_CFIR_TOP_INFO(inst) ((inst) + 0x00000051), 0x00000100 +#define BF_IRQ_ENABLE_Q_TXRX_CFIR_TOP_INFO(inst) ((inst) + 0x00000051), 0x00000101 + +#define REG_CFIR_IRQ_STATUS_ADDR(inst) ((inst) + 0x00000052) +#define BF_IRQ_STATUS_I_TXRX_CFIR_TOP_INFO(inst) ((inst) + 0x00000052), 0x00000100 +#define BF_IRQ_STATUS_Q_TXRX_CFIR_TOP_INFO(inst) ((inst) + 0x00000052), 0x00000101 + +#endif /* __ADI_APOLLO_BF_TXRX_CFIR_TOP_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_txrx_coarse_nco.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_txrx_coarse_nco.h new file mode 100644 index 00000000000000..89d26f93805db7 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_txrx_coarse_nco.h @@ -0,0 +1,288 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:20 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_TXRX_COARSE_NCO_H__ +#define __ADI_APOLLO_BF_TXRX_COARSE_NCO_H__ + +/*============= D E F I N E S ==============*/ +#define RX_COARSE_NCO0_RX_SLICE_0_RX_DIGITAL0 0x60376000 +#define RX_COARSE_NCO1_RX_SLICE_0_RX_DIGITAL0 0x60377000 +#define RX_COARSE_NCO0_RX_SLICE_1_RX_DIGITAL0 0x60576000 +#define RX_COARSE_NCO1_RX_SLICE_1_RX_DIGITAL0 0x60577000 +#define RX_COARSE_NCO0_RX_SLICE_0_RX_DIGITAL1 0x60B76000 +#define RX_COARSE_NCO1_RX_SLICE_0_RX_DIGITAL1 0x60B77000 +#define RX_COARSE_NCO0_RX_SLICE_1_RX_DIGITAL1 0x60D76000 +#define RX_COARSE_NCO1_RX_SLICE_1_RX_DIGITAL1 0x60D77000 +#define TX_COARSE_NCO0_TX_SLICE_0_TX_DIGITAL0 0x61334000 +#define TX_COARSE_NCO1_TX_SLICE_0_TX_DIGITAL0 0x61335000 +#define TX_COARSE_NCO0_TX_SLICE_1_TX_DIGITAL0 0x61534000 +#define TX_COARSE_NCO1_TX_SLICE_1_TX_DIGITAL0 0x61535000 +#define TX_COARSE_NCO0_TX_SLICE_0_TX_DIGITAL1 0x61B34000 +#define TX_COARSE_NCO1_TX_SLICE_0_TX_DIGITAL1 0x61B35000 +#define TX_COARSE_NCO0_TX_SLICE_1_TX_DIGITAL1 0x61D34000 +#define TX_COARSE_NCO1_TX_SLICE_1_TX_DIGITAL1 0x61D35000 + +#define REG_CNCO_PSW0_ADDR(inst) ((inst) + 0x00000000) +#define BF_DRC_PSW_INFO(inst) ((inst) + 0x00000000), 0x00003000 + +#define REG_CNCO_PSW1_ADDR(inst) ((inst) + 0x00000001) + +#define REG_CNCO_PSW2_ADDR(inst) ((inst) + 0x00000002) + +#define REG_CNCO_PSW3_ADDR(inst) ((inst) + 0x00000003) + +#define REG_CNCO_PSW4_ADDR(inst) ((inst) + 0x00000004) + +#define REG_CNCO_PSW5_ADDR(inst) ((inst) + 0x00000005) + +#define REG_DRC_DITHER_TXRX_COARSE_NCO_ADDR(inst) ((inst) + 0x00000006) +#define BF_DRC_AMP_DITHER_EN_INFO(inst) ((inst) + 0x00000006), 0x00000100 +#define BF_DRC_PHASE_DITHER_EN_INFO(inst) ((inst) + 0x00000006), 0x00000101 + +#define REG_TRIG_HOP_CTRL_ADDR(inst) ((inst) + 0x0000000F) +#define BF_AUTOFLIP_INCDIR_TXRX_COARSE_NCO_INFO(inst) ((inst) + 0x0000000F), 0x00000100 +#define BF_AUTO_INC_DECB_TXRX_COARSE_NCO_INFO(inst) ((inst) + 0x0000000F), 0x00000101 +#define BF_HOP_CTRL_INIT_TXRX_COARSE_NCO_INFO(inst) ((inst) + 0x0000000F), 0x00000102 +#define BF_NEXT_HOP_NUMBER_WR_EN_INFO(inst) ((inst) + 0x0000000F), 0x00000103 + +#define REG_TRIG_HOP_STATUS_ADDR(inst) ((inst) + 0x00000010) +#define BF_CHDIR_INT_STATUS_TXRX_COARSE_NCO_INFO(inst) ((inst) + 0x00000010), 0x00000100 +#define BF_HOP_INT_STATUS_TXRX_COARSE_NCO_INFO(inst) ((inst) + 0x00000010), 0x00000101 +#define BF_PROFILE_INT_OUT_INFO(inst) ((inst) + 0x00000010), 0x00000102 +#define BF_NEXT_HOP_PNDSTAT_INFO(inst) ((inst) + 0x00000010), 0x00000103 +#define BF_TRIG_HOP_PROFILE_CHANGE_INFO(inst) ((inst) + 0x00000010), 0x00000104 + +#define REG_TRIG_HOP_INT_CTRL_ADDR(inst) ((inst) + 0x00000011) +#define BF_HOP_INT_CLR_TXRX_COARSE_NCO_INFO(inst) ((inst) + 0x00000011), 0x00000100 +#define BF_HOP_INT_MASK_TXRX_COARSE_NCO_INFO(inst) ((inst) + 0x00000011), 0x00000101 + +#define REG_HOP_HIGHLIM_ADDR(inst) ((inst) + 0x00000012) +#define BF_HOP_HIGHLIM_INFO(inst) ((inst) + 0x00000012), 0x00000400 + +#define REG_HOP_LOWLIM_ADDR(inst) ((inst) + 0x00000013) +#define BF_HOP_LOWLIM_INFO(inst) ((inst) + 0x00000013), 0x00000400 + +#define REG_HOP_INT_NUM_ADDR(inst) ((inst) + 0x00000014) +#define BF_HOP_INT_NUM_INFO(inst) ((inst) + 0x00000014), 0x00000400 + +#define REG_NEXT_HOP_NUMBER_ADDR(inst) ((inst) + 0x00000015) +#define BF_NEXT_HOP_NUMBER_INFO(inst) ((inst) + 0x00000015), 0x00000400 + +#define REG_PROFILE_SEL_MODE_TXRX_COARSE_NCO_ADDR(inst) ((inst) + 0x00000016) +#define BF_PROFILE_SEL_MODE_TXRX_COARSE_NCO_INFO(inst) ((inst) + 0x00000016), 0x00000200 + +#define REG_DRC_NCO_CHAN_SEL_CTRL_ADDR(inst) ((inst) + 0x00000017) +#define BF_DRC_NCO_CHAN_SEL_MODE_INFO(inst) ((inst) + 0x00000017), 0x00000400 +#define BF_DRC_NCO_REGMAP_CHAN_SEL_INFO(inst) ((inst) + 0x00000017), 0x00000404 + +#define REG_DRC_PROFILE_UPDATE_CTRL_ADDR(inst) ((inst) + 0x00000018) +#define BF_DRC_PROFILE_UPDATE_INDEX_INFO(inst) ((inst) + 0x00000018), 0x00000400 + +#define REG_PST_LOAD_CTRL_ADDR(inst) ((inst) + 0x0000001E) +#define BF_PST_LOAD_ENABLE_INFO(inst) ((inst) + 0x0000001E), 0x00000100 + +#define REG_PST_LOAD_VALUE0_ADDR(inst) ((inst) + 0x0000001F) +#define BF_PST_LOAD_VALUE_INFO(inst) ((inst) + 0x0000001F), 0x00003000 + +#define REG_PST_LOAD_VALUE1_ADDR(inst) ((inst) + 0x00000020) + +#define REG_PST_LOAD_VALUE2_ADDR(inst) ((inst) + 0x00000021) + +#define REG_PST_LOAD_VALUE3_ADDR(inst) ((inst) + 0x00000022) + +#define REG_PST_LOAD_VALUE4_ADDR(inst) ((inst) + 0x00000023) + +#define REG_PST_LOAD_VALUE5_ADDR(inst) ((inst) + 0x00000024) + +#define REG_PST_LOAD_STATUS_ADDR(inst) ((inst) + 0x00000025) +#define BF_PST_LOAD_STATUS_INFO(inst) ((inst) + 0x00000025), 0x00000100 + +#define REG_MXR_TEST_MODE_VALUE0_ADDR(inst) ((inst) + 0x00000026) +#define BF_MIXER_TEST_MODE_VAL_TXRX_COARSE_NCO_INFO(inst) ((inst) + 0x00000026), 0x00000E00 + +#define REG_MXR_TEST_MODE_VALUE1_ADDR(inst) ((inst) + 0x00000027) + +#define REG_FREQ_COHRNCE_CTRL_ADDR(inst) ((inst) + 0x00000028) +#define BF_FREQ_COHRNCE_TXRX_COARSE_NCO_INFO(inst) ((inst) + 0x00000028), 0x00000200 + +#define REG_COARSE_DRC_IF_ADDR(inst) ((inst) + 0x00000029) +#define BF_DRC_IF_MODE_TXRX_COARSE_NCO_INFO(inst) ((inst) + 0x00000029), 0x00000200 + +#define REG_COARSE_DRC_MIXER_CTRL_ADDR(inst) ((inst) + 0x0000002A) +#define BF_DRC_MIXER_SEL_INFO(inst) ((inst) + 0x0000002A), 0x00000100 +#define BF_CMPLX_MXR_SCALE_EN_INFO(inst) ((inst) + 0x0000002A), 0x00000101 + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_MXR_CLK_OFFSET_I0_ADDR(inst) ((inst) + 0x0000002C) +#define BF_COARSE_MXR_CLK_OFFSET_I0_INFO(inst) ((inst) + 0x0000002C), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_MXR_CLK_OFFSET_I1_ADDR(inst) ((inst) + 0x0000002D) +#define BF_COARSE_MXR_CLK_OFFSET_I1_INFO(inst) ((inst) + 0x0000002D), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_MXR_CLK_OFFSET_I2_ADDR(inst) ((inst) + 0x0000002E) +#define BF_COARSE_MXR_CLK_OFFSET_I2_INFO(inst) ((inst) + 0x0000002E), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_MXR_CLK_OFFSET_I3_ADDR(inst) ((inst) + 0x0000002F) +#define BF_COARSE_MXR_CLK_OFFSET_I3_INFO(inst) ((inst) + 0x0000002F), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_MXR_CLK_OFFSET_Q0_ADDR(inst) ((inst) + 0x00000030) +#define BF_COARSE_MXR_CLK_OFFSET_Q0_INFO(inst) ((inst) + 0x00000030), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_MXR_CLK_OFFSET_Q1_ADDR(inst) ((inst) + 0x00000031) +#define BF_COARSE_MXR_CLK_OFFSET_Q1_INFO(inst) ((inst) + 0x00000031), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_MXR_CLK_OFFSET_Q2_ADDR(inst) ((inst) + 0x00000032) +#define BF_COARSE_MXR_CLK_OFFSET_Q2_INFO(inst) ((inst) + 0x00000032), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_MXR_CLK_OFFSET_Q3_ADDR(inst) ((inst) + 0x00000033) +#define BF_COARSE_MXR_CLK_OFFSET_Q3_INFO(inst) ((inst) + 0x00000033), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_DRC_CLK_BASE_OFFSET_ADDR(inst) ((inst) + 0x00000034) +#define BF_COARSE_DRC_BASE_OFFSET_INFO(inst) ((inst) + 0x00000034), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#define REG_COARSE_DRC_CTRL_ADDR(inst) ((inst) + 0x00000035) +#define BF_COARSE_DRC_EN_INFO(inst) ((inst) + 0x00000035), 0x00000100 +#ifdef USE_PRIVATE_BF +#define BF_COARSE_CLK_OFFSET_WR_EN_INFO(inst) ((inst) + 0x00000035), 0x00000101 +#endif /* USE_PRIVATE_BF */ +#define BF_DEBUG_CDRC_CLKOFF_N_INFO(inst) ((inst) + 0x00000035), 0x00000102 + +#define REG_TRIG_HOP_ACTIVE_PROFILE_ADDR(inst) ((inst) + 0x00000036) +#define BF_TRIG_HOP_ACTIVE_PROFILE_INFO(inst) ((inst) + 0x00000036), 0x00000400 + +#define REG_PCT_RST_CTRL_TXRX_COARSE_NCO_ADDR(inst) ((inst) + 0x00000038) +#define BF_TS_RST_MODE_TXRX_COARSE_NCO_INFO(inst) ((inst) + 0x00000038), 0x00000100 +#define BF_SPI_TS_RST_TXRX_COARSE_NCO_INFO(inst) ((inst) + 0x00000038), 0x00000103 + +#define REG_PCT_RST_STATUS_TXRX_COARSE_NCO_ADDR(inst) ((inst) + 0x00000039) +#define BF_RST_DONE_TXRX_COARSE_NCO_INFO(inst) ((inst) + 0x00000039), 0x00000100 +#define BF_RST_DONE_CLR_TXRX_COARSE_NCO_INFO(inst) ((inst) + 0x00000039), 0x00000101 + +#define REG_PCT_RD_EN_TXRX_COARSE_NCO_ADDR(inst) ((inst) + 0x0000003A) +#define BF_TIMESTAMP_READ_EN_TXRX_COARSE_NCO_INFO(inst) ((inst) + 0x0000003A), 0x00000100 + +#define REG_PCT_STATUS0_TXRX_COARSE_NCO_ADDR(inst) ((inst) + 0x0000003B) +#define BF_TIMESTAMP_STATUS_TXRX_COARSE_NCO_INFO(inst) ((inst) + 0x0000003B), 0x00004000 + +#define REG_PCT_STATUS1_TXRX_COARSE_NCO_ADDR(inst) ((inst) + 0x0000003C) + +#define REG_PCT_STATUS2_TXRX_COARSE_NCO_ADDR(inst) ((inst) + 0x0000003D) + +#define REG_PCT_STATUS3_TXRX_COARSE_NCO_ADDR(inst) ((inst) + 0x0000003E) + +#define REG_PCT_STATUS4_TXRX_COARSE_NCO_ADDR(inst) ((inst) + 0x0000003F) + +#define REG_PCT_STATUS5_TXRX_COARSE_NCO_ADDR(inst) ((inst) + 0x00000040) + +#define REG_PCT_STATUS6_TXRX_COARSE_NCO_ADDR(inst) ((inst) + 0x00000041) + +#define REG_PCT_STATUS7_TXRX_COARSE_NCO_ADDR(inst) ((inst) + 0x00000042) + +#ifdef USE_PRIVATE_BF +#define REG_MOD_NCO_CTRL_TXRX_COARSE_NCO_ADDR(inst) ((inst) + 0x00000043) +#define BF_MOD_NCO_PHASE_ERROR_LOAD_ENABLE_TXRX_COARSE_NCO_INFO(inst) ((inst) + 0x00000043), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_MOD_NCO_LOAD_STATUS_ADDR(inst) ((inst) + 0x00000044) +#define BF_MOD_NCO_PHASE_ERROR_LOAD_STATUS_TXRX_COARSE_NCO_INFO(inst) ((inst) + 0x00000044), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#define REG_DRC_PHASE_INC_FRAC_A0_TXRX_COARSE_NCO_ADDR(inst) ((inst) + 0x00000045) +#define BF_DRC_PHASE_INC_FRAC_A_INFO(inst) ((inst) + 0x00000045), 0x00002000 + +#define REG_DRC_PHASE_INC_FRAC_A1_TXRX_COARSE_NCO_ADDR(inst) ((inst) + 0x00000046) + +#define REG_DRC_PHASE_INC_FRAC_A2_TXRX_COARSE_NCO_ADDR(inst) ((inst) + 0x00000047) + +#define REG_DRC_PHASE_INC_FRAC_A3_TXRX_COARSE_NCO_ADDR(inst) ((inst) + 0x00000048) + +#define REG_DRC_PHASE_INC_FRAC_B0_TXRX_COARSE_NCO_ADDR(inst) ((inst) + 0x00000049) +#define BF_DRC_PHASE_INC_FRAC_B_INFO(inst) ((inst) + 0x00000049), 0x00002000 + +#define REG_DRC_PHASE_INC_FRAC_B1_TXRX_COARSE_NCO_ADDR(inst) ((inst) + 0x0000004A) + +#define REG_DRC_PHASE_INC_FRAC_B2_TXRX_COARSE_NCO_ADDR(inst) ((inst) + 0x0000004B) + +#define REG_DRC_PHASE_INC_FRAC_B3_TXRX_COARSE_NCO_ADDR(inst) ((inst) + 0x0000004C) + +#ifdef USE_PRIVATE_BF +#define REG_MOD_NCO_LOAD_VALUE0_ADDR(inst) ((inst) + 0x0000004D) +#define BF_MOD_NCO_PHASE_ERROR_LOAD_VALUE_INFO(inst) ((inst) + 0x0000004D), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_MOD_NCO_LOAD_VALUE1_ADDR(inst) ((inst) + 0x0000004E) + +#define REG_MOD_NCO_LOAD_VALUE2_ADDR(inst) ((inst) + 0x0000004F) + +#define REG_MOD_NCO_LOAD_VALUE3_ADDR(inst) ((inst) + 0x00000050) + +#define REG_DRC_PHASE_INC0_ADDR(inst) ((inst) + 0x00000051) +#define BF_DRC_PHASE_INC_INFO(inst) ((inst) + 0x00000051), 0x00002000 + +#define REG_DRC_PHASE_INC1_ADDR(inst) ((inst) + 0x00000052) + +#define REG_DRC_PHASE_INC2_ADDR(inst) ((inst) + 0x00000053) + +#define REG_DRC_PHASE_INC3_ADDR(inst) ((inst) + 0x00000054) + +#define REG_DRC_PHASE_OFFSET0_ADDR(inst) ((inst) + 0x00000055) +#define BF_DRC_PHASE_OFFSET_INFO(inst) ((inst) + 0x00000055), 0x00002000 + +#define REG_DRC_PHASE_OFFSET1_ADDR(inst) ((inst) + 0x00000056) + +#define REG_DRC_PHASE_OFFSET2_ADDR(inst) ((inst) + 0x00000057) + +#define REG_DRC_PHASE_OFFSET3_ADDR(inst) ((inst) + 0x00000058) + +#define REG_DRC_ACTIVE_PHASE_INC0_TXRX_COARSE_NCO_ADDR(inst) ((inst) + 0x00000059) +#define BF_DRC_ACTIVE_PHASE_INC_INFO(inst) ((inst) + 0x00000059), 0x00002000 + +#define REG_DRC_ACTIVE_PHASE_INC1_TXRX_COARSE_NCO_ADDR(inst) ((inst) + 0x0000005A) + +#define REG_DRC_ACTIVE_PHASE_INC2_TXRX_COARSE_NCO_ADDR(inst) ((inst) + 0x0000005B) + +#define REG_DRC_ACTIVE_PHASE_INC3_TXRX_COARSE_NCO_ADDR(inst) ((inst) + 0x0000005C) + +#define REG_DRC_ACTIVE_PHASE_OFFSET0_TXRX_COARSE_NCO_ADDR(inst) ((inst) + 0x0000005D) +#define BF_DRC_ACTIVE_PHASE_OFFSET_INFO(inst) ((inst) + 0x0000005D), 0x00002000 + +#define REG_DRC_ACTIVE_PHASE_OFFSET1_TXRX_COARSE_NCO_ADDR(inst) ((inst) + 0x0000005E) + +#define REG_DRC_ACTIVE_PHASE_OFFSET2_TXRX_COARSE_NCO_ADDR(inst) ((inst) + 0x0000005F) + +#define REG_DRC_ACTIVE_PHASE_OFFSET3_TXRX_COARSE_NCO_ADDR(inst) ((inst) + 0x00000060) + +#define REG_DRC_MOD_NCO_PROFILE_UPDATE_ADDR(inst) ((inst) + 0x00000061) +#define BF_DRC_MOD_NCO_PROFILE_UPDATE_INFO(inst) ((inst) + 0x00000061), 0x00000100 + +#endif /* __ADI_APOLLO_BF_TXRX_COARSE_NCO_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_txrx_enable.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_txrx_enable.h new file mode 100644 index 00000000000000..02ca8c3a25252e --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_txrx_enable.h @@ -0,0 +1,73 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:19 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_TXRX_ENABLE_H__ +#define __ADI_APOLLO_BF_TXRX_ENABLE_H__ + +/*============= D E F I N E S ==============*/ +#define TXRX_ENABLE_RX_DIGITAL0 0x60020000 +#define TXRX_ENABLE_RX_DIGITAL1 0x60820000 +#define TXRX_ENABLE_TX_SLICE_0_TX_DIGITAL0 0x6120A000 +#define TXRX_ENABLE_TX_SLICE_1_TX_DIGITAL0 0x6140A000 +#define TXRX_ENABLE_TX_SLICE_0_TX_DIGITAL1 0x61A0A000 +#define TXRX_ENABLE_TX_SLICE_1_TX_DIGITAL1 0x61C0A000 + +#define REG_TXRX_ENABLE_CTRL_ADDR(inst, n) ((inst) + 0x00000000 + 15 * (n)) +#define BF_ENABLE_POL_INFO(inst, n) ((inst) + 0x00000000 + 15 * (n)), 0x00000100 +#define BF_ENABLE_SPI_INFO(inst, n) ((inst) + 0x00000000 + 15 * (n)), 0x00000101 +#define BF_ENABLE_SPIEN_INFO(inst, n) ((inst) + 0x00000000 + 15 * (n)), 0x00000102 + +#define REG_SLICE_SEL_ADDR(inst, n) ((inst) + 0x00000001 + 15 * (n)) +#define BF_SLICE_SEL_INFO(inst, n) ((inst) + 0x00000001 + 15 * (n)), 0x00000400 + +#define REG_LINX_SEL_ADDR(inst, n) ((inst) + 0x00000002 + 15 * (n)) +#define BF_LINX_SEL_INFO(inst, n) ((inst) + 0x00000002 + 15 * (n)), 0x00000400 + +#define REG_PFILT_SEL_ADDR(inst, n) ((inst) + 0x00000003 + 15 * (n)) +#define BF_PFILT_SEL_INFO(inst, n) ((inst) + 0x00000003 + 15 * (n)), 0x00000200 + +#define REG_CDUC_CDDC_SEL_ADDR(inst, n) ((inst) + 0x00000004 + 15 * (n)) +#define BF_CDUC_CDDC_SEL_INFO(inst, n) ((inst) + 0x00000004 + 15 * (n)), 0x00000400 + +#define REG_FDUC_FDDC_SEL_ADDR(inst, n) ((inst) + 0x00000005 + 15 * (n)) +#define BF_FDUC_FDDC_SEL_INFO(inst, n) ((inst) + 0x00000005 + 15 * (n)), 0x00000800 + +#define REG_CFIR_SEL_ADDR(inst, n) ((inst) + 0x00000006 + 15 * (n)) +#define BF_CFIR_SEL_INFO(inst, n) ((inst) + 0x00000006 + 15 * (n)), 0x00000200 + +#define REG_FSRC_SEL_ADDR(inst, n) ((inst) + 0x00000007 + 15 * (n)) +#define BF_FSRC_SEL_INFO(inst, n) ((inst) + 0x00000007 + 15 * (n)), 0x00000200 + +#define REG_JRX_JTX_LINK_SEL_ADDR(inst, n) ((inst) + 0x00000008 + 15 * (n)) +#define BF_JRX_JTX_LINK_SEL_INFO(inst, n) ((inst) + 0x00000008 + 15 * (n)), 0x00000200 + +#define REG_JRX_JTX_PHY_SEL0_ADDR(inst, n) ((inst) + 0x00000009 + 15 * (n)) +#define BF_JRX_JTX_PHY_SEL_INFO(inst, n) ((inst) + 0x00000009 + 15 * (n)), 0x00000C00 + +#define REG_JRX_JTX_PHY_SEL1_ADDR(inst, n) ((inst) + 0x0000000A + 15 * (n)) + +#define REG_MODSW_SEL_ADDR(inst, n) ((inst) + 0x0000000B + 15 * (n)) +#define BF_MODSW_SEL_INFO(inst, n) ((inst) + 0x0000000B + 15 * (n)), 0x00000100 + +#define REG_INVSINC_SEL_ADDR(inst, n) ((inst) + 0x0000000C + 15 * (n)) +#define BF_INVSINC_SEL_INFO(inst, n) ((inst) + 0x0000000C + 15 * (n)), 0x00000400 + +#define REG_GAIN_SEL_ADDR(inst, n) ((inst) + 0x0000000D + 15 * (n)) +#define BF_GAIN_SEL_INFO(inst, n) ((inst) + 0x0000000D + 15 * (n)), 0x00000400 + +#define REG_SRD_SEL_ADDR(inst, n) ((inst) + 0x0000000E + 15 * (n)) +#define BF_SRD_SEL_INFO(inst, n) ((inst) + 0x0000000E + 15 * (n)), 0x00000400 + +#endif /* __ADI_APOLLO_BF_TXRX_ENABLE_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_txrx_fine_nco.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_txrx_fine_nco.h new file mode 100644 index 00000000000000..8365f581b273f6 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_txrx_fine_nco.h @@ -0,0 +1,666 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:20 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_TXRX_FINE_NCO_H__ +#define __ADI_APOLLO_BF_TXRX_FINE_NCO_H__ + +/*============= D E F I N E S ==============*/ +#define RX_FINE_NCO0_RX_SLICE_0_RX_DIGITAL0 0x6036A000 +#define RX_FINE_NCO1_RX_SLICE_0_RX_DIGITAL0 0x6036B000 +#define RX_FINE_NCO2_RX_SLICE_0_RX_DIGITAL0 0x6036C000 +#define RX_FINE_NCO3_RX_SLICE_0_RX_DIGITAL0 0x6036D000 +#define RX_FINE_NCO0_RX_SLICE_1_RX_DIGITAL0 0x6056A000 +#define RX_FINE_NCO1_RX_SLICE_1_RX_DIGITAL0 0x6056B000 +#define RX_FINE_NCO2_RX_SLICE_1_RX_DIGITAL0 0x6056C000 +#define RX_FINE_NCO3_RX_SLICE_1_RX_DIGITAL0 0x6056D000 +#define RX_FINE_NCO0_RX_SLICE_0_RX_DIGITAL1 0x60B6A000 +#define RX_FINE_NCO1_RX_SLICE_0_RX_DIGITAL1 0x60B6B000 +#define RX_FINE_NCO2_RX_SLICE_0_RX_DIGITAL1 0x60B6C000 +#define RX_FINE_NCO3_RX_SLICE_0_RX_DIGITAL1 0x60B6D000 +#define RX_FINE_NCO0_RX_SLICE_1_RX_DIGITAL1 0x60D6A000 +#define RX_FINE_NCO1_RX_SLICE_1_RX_DIGITAL1 0x60D6B000 +#define RX_FINE_NCO2_RX_SLICE_1_RX_DIGITAL1 0x60D6C000 +#define RX_FINE_NCO3_RX_SLICE_1_RX_DIGITAL1 0x60D6D000 +#define TX_FINE_NCO0_TX_SLICE_0_TX_DIGITAL0 0x61308000 +#define TX_FINE_NCO1_TX_SLICE_0_TX_DIGITAL0 0x61309000 +#define TX_FINE_NCO2_TX_SLICE_0_TX_DIGITAL0 0x6130A000 +#define TX_FINE_NCO3_TX_SLICE_0_TX_DIGITAL0 0x6130B000 +#define TX_FINE_NCO0_TX_SLICE_1_TX_DIGITAL0 0x61508000 +#define TX_FINE_NCO1_TX_SLICE_1_TX_DIGITAL0 0x61509000 +#define TX_FINE_NCO2_TX_SLICE_1_TX_DIGITAL0 0x6150A000 +#define TX_FINE_NCO3_TX_SLICE_1_TX_DIGITAL0 0x6150B000 +#define TX_FINE_NCO0_TX_SLICE_0_TX_DIGITAL1 0x61B08000 +#define TX_FINE_NCO1_TX_SLICE_0_TX_DIGITAL1 0x61B09000 +#define TX_FINE_NCO2_TX_SLICE_0_TX_DIGITAL1 0x61B0A000 +#define TX_FINE_NCO3_TX_SLICE_0_TX_DIGITAL1 0x61B0B000 +#define TX_FINE_NCO0_TX_SLICE_1_TX_DIGITAL1 0x61D08000 +#define TX_FINE_NCO1_TX_SLICE_1_TX_DIGITAL1 0x61D09000 +#define TX_FINE_NCO2_TX_SLICE_1_TX_DIGITAL1 0x61D0A000 +#define TX_FINE_NCO3_TX_SLICE_1_TX_DIGITAL1 0x61D0B000 + +#define REG_FINE_NCO_CLK_CTRL_ADDR(inst) ((inst) + 0x00000000) +#define BF_FINE_DRC_EN0_INFO(inst) ((inst) + 0x00000000), 0x00000100 +#ifdef USE_PRIVATE_BF +#define BF_CLK_OFFSET_WR_EN_TXRX_FINE_NCO_INFO(inst) ((inst) + 0x00000000), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_DEBUG_FDRC_CLKOFF_N_INFO(inst) ((inst) + 0x00000000), 0x00000103 + +#ifdef USE_PRIVATE_BF +#define REG_FINE_BASE_OFFSET_TXRX_FINE_NCO_ADDR(inst) ((inst) + 0x00000001) +#define BF_DRC_BASE_OFFSET_INFO(inst) ((inst) + 0x00000001), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FINE_I_MXR_OFFSET_ADDR(inst) ((inst) + 0x00000002) +#define BF_FINE_I_MXR_OFFSET_INFO(inst) ((inst) + 0x00000002), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FINE_Q_MXR_OFFSET_ADDR(inst) ((inst) + 0x00000003) +#define BF_FINE_Q_MXR_OFFSET_INFO(inst) ((inst) + 0x00000003), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_FINE_MXR_CTRL_ADDR(inst) ((inst) + 0x00000004) +#define BF_DRC_IF_MODE_TXRX_FINE_NCO_INFO(inst) ((inst) + 0x00000004), 0x00000200 +#define BF_DRC_MXR_SEL_INFO(inst) ((inst) + 0x00000004), 0x00000102 +#define BF_CMPLX_MXR_MULT_SCALE_EN_INFO(inst) ((inst) + 0x00000004), 0x00000103 + +#ifdef USE_PRIVATE_BF +#define REG_ARAMP_INC_DEC_PROFNUM_ADDR(inst) ((inst) + 0x00000005) +#define BF_ARAMP_INC_PROFNUM_INFO(inst) ((inst) + 0x00000005), 0x00000400 +#define BF_ARAMP_DEC_PROFNUM_INFO(inst) ((inst) + 0x00000005), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FRAMP_ARAMP_DIR_ADDR(inst) ((inst) + 0x00000006) +#define BF_FRAMP_DIR_INFO(inst) ((inst) + 0x00000006), 0x00000100 +#define BF_FRAMP_DIR_AUTOFLIP_INFO(inst) ((inst) + 0x00000006), 0x00000101 +#define BF_ARAMP_DIR_INFO(inst) ((inst) + 0x00000006), 0x00000102 +#define BF_ARAMP_DIR_AUTOFLIP_INFO(inst) ((inst) + 0x00000006), 0x00000103 +#define BF_SYMM_ARAMP_INFO(inst) ((inst) + 0x00000006), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FRAMP_INC_PROFNUM_ADDR(inst) ((inst) + 0x00000007) +#define BF_FRAMP_INC_PROFNUM_INFO(inst) ((inst) + 0x00000007), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FRAMP_DEC_PROFNUM_ADDR(inst) ((inst) + 0x00000008) +#define BF_FRAMP_DEC_PROFNUM_INFO(inst) ((inst) + 0x00000008), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARAMP_SCALE_EN_ADDR(inst) ((inst) + 0x00000015) +#define BF_ARAMP_SCALE_EN_INFO(inst) ((inst) + 0x00000015), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARAMP_UPDTRATE0_ADDR(inst) ((inst) + 0x00000016) +#define BF_ARAMP_UPDTRATE0_INFO(inst) ((inst) + 0x00000016), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARAMP_UPDTRATE1_ADDR(inst) ((inst) + 0x00000017) +#define BF_ARAMP_UPDTRATE1_INFO(inst) ((inst) + 0x00000017), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_AUTOFLIP_INCDIR_ADDR(inst) ((inst) + 0x00000018) +#define BF_AUTOFLIP_INCDIR_TXRX_FINE_NCO_INFO(inst) ((inst) + 0x00000018), 0x00000600 + +#define REG_AUTO_INC_DECB_ADDR(inst) ((inst) + 0x00000019) +#define BF_AUTO_INC_DECB_TXRX_FINE_NCO_INFO(inst) ((inst) + 0x00000019), 0x00000600 + +#define REG_CHDIR_INT_STATUS_ADDR(inst) ((inst) + 0x0000001A) +#define BF_CHDIR_INT_STATUS_TXRX_FINE_NCO_INFO(inst) ((inst) + 0x0000001A), 0x00000600 + +#define REG_DRC_ACTIVE_PHASE_INC0_TXRX_FINE_NCO_ADDR(inst) ((inst) + 0x0000001B) +#define BF_DRC0_ACTIVE_PHASE_INC_INFO(inst) ((inst) + 0x0000001B), 0x00003000 + +#define REG_DRC_ACTIVE_PHASE_INC1_TXRX_FINE_NCO_ADDR(inst) ((inst) + 0x0000001C) + +#define REG_DRC_ACTIVE_PHASE_INC2_TXRX_FINE_NCO_ADDR(inst) ((inst) + 0x0000001D) + +#define REG_DRC_ACTIVE_PHASE_INC3_TXRX_FINE_NCO_ADDR(inst) ((inst) + 0x0000001E) + +#define REG_DRC_ACTIVE_PHASE_INC4_ADDR(inst) ((inst) + 0x0000001F) + +#define REG_DRC_ACTIVE_PHASE_INC5_ADDR(inst) ((inst) + 0x00000020) + +#define REG_DRC_ACTIVE_PHASE_OFFSET0_TXRX_FINE_NCO_ADDR(inst) ((inst) + 0x00000021) +#define BF_DRC0_ACTIVE_PHASE_OFFSET_INFO(inst) ((inst) + 0x00000021), 0x00003000 + +#define REG_DRC_ACTIVE_PHASE_OFFSET1_TXRX_FINE_NCO_ADDR(inst) ((inst) + 0x00000022) + +#define REG_DRC_ACTIVE_PHASE_OFFSET2_TXRX_FINE_NCO_ADDR(inst) ((inst) + 0x00000023) + +#define REG_DRC_ACTIVE_PHASE_OFFSET3_TXRX_FINE_NCO_ADDR(inst) ((inst) + 0x00000024) + +#define REG_DRC_ACTIVE_PHASE_OFFSET4_ADDR(inst) ((inst) + 0x00000025) + +#define REG_DRC_ACTIVE_PHASE_OFFSET5_ADDR(inst) ((inst) + 0x00000026) + +#define REG_DRC_DITHER_TXRX_FINE_NCO_ADDR(inst) ((inst) + 0x00000027) +#define BF_DRC0_AMP_DITHER_EN_INFO(inst) ((inst) + 0x00000027), 0x00000100 +#define BF_DRC0_PHASE_DITHER_EN_INFO(inst) ((inst) + 0x00000027), 0x00000101 + +#define REG_DRC_PHASE_INC_FRAC_A0_TXRX_FINE_NCO_ADDR(inst) ((inst) + 0x00000028) +#define BF_DRC0_PHASE_INC_FRAC_A_INFO(inst) ((inst) + 0x00000028), 0x00003000 + +#define REG_DRC_PHASE_INC_FRAC_A1_TXRX_FINE_NCO_ADDR(inst) ((inst) + 0x00000029) + +#define REG_DRC_PHASE_INC_FRAC_A2_TXRX_FINE_NCO_ADDR(inst) ((inst) + 0x0000002A) + +#define REG_DRC_PHASE_INC_FRAC_A3_TXRX_FINE_NCO_ADDR(inst) ((inst) + 0x0000002B) + +#define REG_DRC_PHASE_INC_FRAC_A4_ADDR(inst) ((inst) + 0x0000002C) + +#define REG_DRC_PHASE_INC_FRAC_A5_ADDR(inst) ((inst) + 0x0000002D) + +#define REG_DRC_PHASE_INC_FRAC_B0_TXRX_FINE_NCO_ADDR(inst) ((inst) + 0x0000002E) +#define BF_DRC0_PHASE_INC_FRAC_B_INFO(inst) ((inst) + 0x0000002E), 0x00003000 + +#define REG_DRC_PHASE_INC_FRAC_B1_TXRX_FINE_NCO_ADDR(inst) ((inst) + 0x0000002F) + +#define REG_DRC_PHASE_INC_FRAC_B2_TXRX_FINE_NCO_ADDR(inst) ((inst) + 0x00000030) + +#define REG_DRC_PHASE_INC_FRAC_B3_TXRX_FINE_NCO_ADDR(inst) ((inst) + 0x00000031) + +#define REG_DRC_PHASE_INC_FRAC_B4_ADDR(inst) ((inst) + 0x00000032) + +#define REG_DRC_PHASE_INC_FRAC_B5_ADDR(inst) ((inst) + 0x00000033) + +#define REG_DUTY_CYCLE0_ADDR(inst) ((inst) + 0x00000034) +#define BF_DUTY_CYCLE0_INFO(inst) ((inst) + 0x00000034), 0x00000800 + +#define REG_DUTY_CYCLE1_ADDR(inst) ((inst) + 0x00000035) +#define BF_DUTY_CYCLE1_INFO(inst) ((inst) + 0x00000035), 0x00000800 + +#define REG_NCO_COHRENCE_CTRL_ADDR(inst) ((inst) + 0x00000036) +#define BF_FREQ_COHRNCE_TXRX_FINE_NCO_INFO(inst) ((inst) + 0x00000036), 0x00000200 +#ifdef USE_PRIVATE_BF +#define BF_FJMP_COHRNCE_INFO(inst) ((inst) + 0x00000036), 0x00000202 +#endif /* USE_PRIVATE_BF */ +#ifdef USE_PRIVATE_BF +#define BF_FSTOP_COHRNCE_INFO(inst) ((inst) + 0x00000036), 0x00000204 +#endif /* USE_PRIVATE_BF */ +#define BF_NCORST_COHRNCE_INFO(inst) ((inst) + 0x00000036), 0x00000106 + +#define REG_INTERRUPT_OUT_ADDR(inst) ((inst) + 0x00000037) +#define BF_INTERRUPT_OUT_INFO(inst) ((inst) + 0x00000037), 0x00000100 +#ifdef USE_PRIVATE_BF +#define BF_FRMP_ERR_INTRPT_INFO(inst) ((inst) + 0x00000037), 0x00000101 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FRAMP_ERR_INTRP_CLR_ADDR(inst) ((inst) + 0x00000038) +#define BF_FRMP_ERR_INTRPT_CLR_INFO(inst) ((inst) + 0x00000038), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#define REG_GPIO_HOP_ADDR(inst) ((inst) + 0x00000039) +#define BF_GPIO_ALL_HOP_INFO(inst) ((inst) + 0x00000039), 0x00000100 +#define BF_TXRX_GPIOSHARE_INFO(inst) ((inst) + 0x00000039), 0x00000101 + +#ifdef USE_PRIVATE_BF +#define REG_HOP_AMP0_ADDR(inst) ((inst) + 0x0000003A) +#define BF_HOP_AMP0_INFO(inst) ((inst) + 0x0000003A), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_HOP_AMP1_ADDR(inst) ((inst) + 0x0000003B) +#define BF_HOP_AMP1_INFO(inst) ((inst) + 0x0000003B), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_HOP_AMP_INCR0_ADDR(inst) ((inst) + 0x0000003C) +#define BF_HOP_AMP_INCR0_INFO(inst) ((inst) + 0x0000003C), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_HOP_AMP_INCR1_ADDR(inst) ((inst) + 0x0000003D) +#define BF_HOP_AMP_INCR1_INFO(inst) ((inst) + 0x0000003D), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_HOP_CTRL_ADDR(inst) ((inst) + 0x0000003E) +#define BF_HOP_MODE_EN_INFO(inst) ((inst) + 0x0000003E), 0x00000100 +#define BF_HOP_MODE_INFO(inst) ((inst) + 0x0000003E), 0x00000301 +#define BF_HOP_CTRL_INIT_TXRX_FINE_NCO_INFO(inst) ((inst) + 0x0000003E), 0x00000104 + +#ifdef USE_PRIVATE_BF +#define REG_HOP_FDECR0_ADDR(inst) ((inst) + 0x0000003F) +#define BF_HOP_FDECR0_INFO(inst) ((inst) + 0x0000003F), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_HOP_FDECR1_ADDR(inst) ((inst) + 0x00000040) +#define BF_HOP_FDECR1_INFO(inst) ((inst) + 0x00000040), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_HOP_FDECR2_ADDR(inst) ((inst) + 0x00000041) +#define BF_HOP_FDECR2_INFO(inst) ((inst) + 0x00000041), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_HOP_FDECR3_ADDR(inst) ((inst) + 0x00000042) +#define BF_HOP_FDECR3_INFO(inst) ((inst) + 0x00000042), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_HOP_FINCR0_ADDR(inst) ((inst) + 0x00000043) +#define BF_HOP_FINCR0_INFO(inst) ((inst) + 0x00000043), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_HOP_FINCR1_ADDR(inst) ((inst) + 0x00000044) +#define BF_HOP_FINCR1_INFO(inst) ((inst) + 0x00000044), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_HOP_FINCR2_ADDR(inst) ((inst) + 0x00000045) +#define BF_HOP_FINCR2_INFO(inst) ((inst) + 0x00000045), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_HOP_FINCR3_ADDR(inst) ((inst) + 0x00000046) +#define BF_HOP_FINCR3_INFO(inst) ((inst) + 0x00000046), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_HOP_HIGHLIMIT_PR0_ADDR(inst) ((inst) + 0x00000047) +#define BF_HOP_HIGHLIMIT_PR0_INFO(inst) ((inst) + 0x00000047), 0x00000600 + +#ifdef USE_PRIVATE_BF +#define REG_HOP_HIGHLIMIT_PR1_ADDR(inst) ((inst) + 0x00000048) +#define BF_HOP_HIGHLIMIT_PR1_INFO(inst) ((inst) + 0x00000048), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#define REG_HOP_HIGHLIMIT_PR2_ADDR(inst) ((inst) + 0x00000049) +#define BF_HOP_HIGHLIMIT_PR2_INFO(inst) ((inst) + 0x00000049), 0x00000600 + +#ifdef USE_PRIVATE_BF +#define REG_HOP_HIGHLIMIT_PR3_ADDR(inst) ((inst) + 0x0000004A) +#define BF_HOP_HIGHLIMIT_PR3_INFO(inst) ((inst) + 0x0000004A), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_HOP_HIGHLIMIT_PR4_ADDR(inst) ((inst) + 0x0000004B) +#define BF_HOP_HIGHLIMIT_PR4_INFO(inst) ((inst) + 0x0000004B), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_HOP_HIGHLIMIT_PR5_ADDR(inst) ((inst) + 0x0000004C) +#define BF_HOP_HIGHLIMIT_PR5_INFO(inst) ((inst) + 0x0000004C), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#define REG_HOP_INTRPT_PR0_ADDR(inst) ((inst) + 0x0000004D) +#define BF_HOP_INT_NUM0_INFO(inst) ((inst) + 0x0000004D), 0x00000600 +#define BF_HOP_INT_MASK_TXRX_FINE_NCO_INFO(inst) ((inst) + 0x0000004D), 0x00000606 +#define BF_HOP_INT_CLR_TXRX_FINE_NCO_INFO(inst) ((inst) + 0x0000004D), 0x00000607 + +#ifdef USE_PRIVATE_BF +#define REG_HOP_INTRPT_PR1_ADDR(inst) ((inst) + 0x0000004E) +#define BF_HOP_INT_NUM1_INFO(inst) ((inst) + 0x0000004E), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#define REG_HOP_INTRPT_PR2_ADDR(inst) ((inst) + 0x0000004F) +#define BF_HOP_INT_NUM2_INFO(inst) ((inst) + 0x0000004F), 0x00000600 + +#ifdef USE_PRIVATE_BF +#define REG_HOP_INTRPT_PR3_ADDR(inst) ((inst) + 0x00000050) +#define BF_HOP_INT_NUM3_INFO(inst) ((inst) + 0x00000050), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_HOP_INTRPT_PR4_ADDR(inst) ((inst) + 0x00000051) +#define BF_HOP_INT_NUM4_INFO(inst) ((inst) + 0x00000051), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_HOP_INTRPT_PR5_ADDR(inst) ((inst) + 0x00000052) +#define BF_HOP_INT_NUM5_INFO(inst) ((inst) + 0x00000052), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#define REG_HOP_INT_STATUS_ADDR(inst) ((inst) + 0x00000053) +#define BF_HOP_INT_STATUS_TXRX_FINE_NCO_INFO(inst) ((inst) + 0x00000053), 0x00000600 + +#ifdef USE_PRIVATE_BF +#define REG_HOP_JMP_HIGH0_ADDR(inst) ((inst) + 0x00000054) +#define BF_HOP_JMP_HIGH0_INFO(inst) ((inst) + 0x00000054), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_HOP_JMP_HIGH1_ADDR(inst) ((inst) + 0x00000055) +#define BF_HOP_JMP_HIGH1_INFO(inst) ((inst) + 0x00000055), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_HOP_JMP_HIGH2_ADDR(inst) ((inst) + 0x00000056) +#define BF_HOP_JMP_HIGH2_INFO(inst) ((inst) + 0x00000056), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_HOP_JMP_HIGH3_ADDR(inst) ((inst) + 0x00000057) +#define BF_HOP_JMP_HIGH3_INFO(inst) ((inst) + 0x00000057), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_HOP_JMP_LOW0_ADDR(inst) ((inst) + 0x00000058) +#define BF_HOP_JMP_LOW0_INFO(inst) ((inst) + 0x00000058), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_HOP_JMP_LOW1_ADDR(inst) ((inst) + 0x00000059) +#define BF_HOP_JMP_LOW1_INFO(inst) ((inst) + 0x00000059), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_HOP_JMP_LOW2_ADDR(inst) ((inst) + 0x0000005A) +#define BF_HOP_JMP_LOW2_INFO(inst) ((inst) + 0x0000005A), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_HOP_JMP_LOW3_ADDR(inst) ((inst) + 0x0000005B) +#define BF_HOP_JMP_LOW3_INFO(inst) ((inst) + 0x0000005B), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_HOP_LOWLIMIT_PR0_ADDR(inst) ((inst) + 0x0000005C) +#define BF_HOP_LOWLIMIT_PR0_INFO(inst) ((inst) + 0x0000005C), 0x00000600 + +#ifdef USE_PRIVATE_BF +#define REG_HOP_LOWLIMIT_PR1_ADDR(inst) ((inst) + 0x0000005D) +#define BF_HOP_LOWLIMIT_PR1_INFO(inst) ((inst) + 0x0000005D), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#define REG_HOP_LOWLIMIT_PR2_ADDR(inst) ((inst) + 0x0000005E) +#define BF_HOP_LOWLIMIT_PR2_INFO(inst) ((inst) + 0x0000005E), 0x00000600 + +#ifdef USE_PRIVATE_BF +#define REG_HOP_LOWLIMIT_PR3_ADDR(inst) ((inst) + 0x0000005F) +#define BF_HOP_LOWLIMIT_PR3_INFO(inst) ((inst) + 0x0000005F), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_HOP_LOWLIMIT_PR4_ADDR(inst) ((inst) + 0x00000060) +#define BF_HOP_LOWLIMIT_PR4_INFO(inst) ((inst) + 0x00000060), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_HOP_LOWLIMIT_PR5_ADDR(inst) ((inst) + 0x00000061) +#define BF_HOP_LOWLIMIT_PR5_INFO(inst) ((inst) + 0x00000061), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#define REG_HOP_PHASE_INC0_ADDR(inst) ((inst) + 0x00000062) +#define BF_HOP_PHASE_INC0_INFO(inst) ((inst) + 0x00000062), 0x00000800 + +#define REG_HOP_PHASE_INC1_ADDR(inst) ((inst) + 0x00000063) +#define BF_HOP_PHASE_INC1_INFO(inst) ((inst) + 0x00000063), 0x00000800 + +#define REG_HOP_PHASE_INC2_ADDR(inst) ((inst) + 0x00000064) +#define BF_HOP_PHASE_INC2_INFO(inst) ((inst) + 0x00000064), 0x00000800 + +#define REG_HOP_PHASE_INC3_ADDR(inst) ((inst) + 0x00000065) +#define BF_HOP_PHASE_INC3_INFO(inst) ((inst) + 0x00000065), 0x00000800 + +#define REG_HOP_PHASE_OFFSET0_ADDR(inst) ((inst) + 0x00000066) +#define BF_HOP_PHASE_OFFSET0_INFO(inst) ((inst) + 0x00000066), 0x00000800 + +#define REG_HOP_PHASE_OFFSET1_ADDR(inst) ((inst) + 0x00000067) +#define BF_HOP_PHASE_OFFSET1_INFO(inst) ((inst) + 0x00000067), 0x00000800 + +#define REG_HOP_PROFILE_PAGE_ADDR(inst) ((inst) + 0x00000068) +#define BF_HOP_PROFILE_PAGE_INFO(inst) ((inst) + 0x00000068), 0x00000600 + +#ifdef USE_PRIVATE_BF +#define REG_HOP_STOP_FREQ0_ADDR(inst) ((inst) + 0x00000069) +#define BF_HOP_STOP_FREQ0_INFO(inst) ((inst) + 0x00000069), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_HOP_STOP_FREQ1_ADDR(inst) ((inst) + 0x0000006A) +#define BF_HOP_STOP_FREQ1_INFO(inst) ((inst) + 0x0000006A), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_HOP_STOP_FREQ2_ADDR(inst) ((inst) + 0x0000006B) +#define BF_HOP_STOP_FREQ2_INFO(inst) ((inst) + 0x0000006B), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_HOP_STOP_FREQ3_ADDR(inst) ((inst) + 0x0000006C) +#define BF_HOP_STOP_FREQ3_INFO(inst) ((inst) + 0x0000006C), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_HOP_TIME0_ADDR(inst) ((inst) + 0x0000006D) +#define BF_HOP_TIME0_INFO(inst) ((inst) + 0x0000006D), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_HOP_TIME1_ADDR(inst) ((inst) + 0x0000006E) +#define BF_HOP_TIME1_INFO(inst) ((inst) + 0x0000006E), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_MAIN_NCO_CTRL_ADDR(inst) ((inst) + 0x0000006F) +#define BF_MAIN2_NCO_SEL_INFO(inst) ((inst) + 0x0000006F), 0x00000100 +#define BF_MAIN_NCO_SYNC_UPDT_EN_INFO(inst) ((inst) + 0x0000006F), 0x00000101 +#define BF_MAIN_NCO_SYNC_UPDT_INFO(inst) ((inst) + 0x0000006F), 0x00000102 + +#define REG_MAIN2_PHASE_INC0_ADDR(inst) ((inst) + 0x00000070) +#define BF_MAIN2_PHASE_INC_INFO(inst) ((inst) + 0x00000070), 0x00003000 + +#define REG_MAIN2_PHASE_INC1_ADDR(inst) ((inst) + 0x00000071) + +#define REG_MAIN2_PHASE_INC2_ADDR(inst) ((inst) + 0x00000072) + +#define REG_MAIN2_PHASE_INC3_ADDR(inst) ((inst) + 0x00000073) + +#define REG_MAIN2_PHASE_INC4_ADDR(inst) ((inst) + 0x00000074) + +#define REG_MAIN2_PHASE_INC5_ADDR(inst) ((inst) + 0x00000075) + +#define REG_MAIN2_PHASE_OFFSET0_ADDR(inst) ((inst) + 0x00000076) +#define BF_MAIN2_PHASE_OFFSET_INFO(inst) ((inst) + 0x00000076), 0x00003000 + +#define REG_MAIN2_PHASE_OFFSET1_ADDR(inst) ((inst) + 0x00000077) + +#define REG_MAIN2_PHASE_OFFSET2_ADDR(inst) ((inst) + 0x00000078) + +#define REG_MAIN2_PHASE_OFFSET3_ADDR(inst) ((inst) + 0x00000079) + +#define REG_MAIN2_PHASE_OFFSET4_ADDR(inst) ((inst) + 0x0000007A) + +#define REG_MAIN2_PHASE_OFFSET5_ADDR(inst) ((inst) + 0x0000007B) + +#ifdef USE_PRIVATE_BF +#define REG_MAIN_AMP0_ADDR(inst) ((inst) + 0x0000007C) +#define BF_MAIN_AMP0_INFO(inst) ((inst) + 0x0000007C), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_MAIN_AMP1_ADDR(inst) ((inst) + 0x0000007D) +#define BF_MAIN_AMP1_INFO(inst) ((inst) + 0x0000007D), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_MAIN_PHASE_INC0_ADDR(inst) ((inst) + 0x0000007E) +#define BF_MAIN_PHASE_INC_INFO(inst) ((inst) + 0x0000007E), 0x00003000 + +#define REG_MAIN_PHASE_INC1_ADDR(inst) ((inst) + 0x0000007F) + +#define REG_MAIN_PHASE_INC2_ADDR(inst) ((inst) + 0x00000080) + +#define REG_MAIN_PHASE_INC3_ADDR(inst) ((inst) + 0x00000081) + +#define REG_MAIN_PHASE_INC4_ADDR(inst) ((inst) + 0x00000082) + +#define REG_MAIN_PHASE_INC5_ADDR(inst) ((inst) + 0x00000083) + +#define REG_MAIN_PHASE_OFFSET0_ADDR(inst) ((inst) + 0x00000084) +#define BF_MAIN_PHASE_OFFSET_INFO(inst) ((inst) + 0x00000084), 0x00003000 + +#define REG_MAIN_PHASE_OFFSET1_ADDR(inst) ((inst) + 0x00000085) + +#define REG_MAIN_PHASE_OFFSET2_ADDR(inst) ((inst) + 0x00000086) + +#define REG_MAIN_PHASE_OFFSET3_ADDR(inst) ((inst) + 0x00000087) + +#define REG_MAIN_PHASE_OFFSET4_ADDR(inst) ((inst) + 0x00000088) + +#define REG_MAIN_PHASE_OFFSET5_ADDR(inst) ((inst) + 0x00000089) + +#ifdef USE_PRIVATE_BF +#define REG_MOD_NCO_LOAD_CTRL_ADDR(inst) ((inst) + 0x0000008A) +#define BF_MOD_NCO_PHASE_ERROR_LOAD_ENABLE_TXRX_FINE_NCO_INFO(inst) ((inst) + 0x0000008A), 0x00000100 +#define BF_MOD_NCO_PHASE_ERROR_LOAD_STATUS_TXRX_FINE_NCO_INFO(inst) ((inst) + 0x0000008A), 0x00000101 +#endif /* USE_PRIVATE_BF */ + +#define REG_MOD_NCO_CTRL_TXRX_FINE_NCO_ADDR(inst) ((inst) + 0x0000008B) +#define BF_MOD_PARAM_SCH_INFO(inst) ((inst) + 0x0000008B), 0x00000200 +#define BF_USE_FRC_AB_INFO(inst) ((inst) + 0x0000008B), 0x00000102 + +#define REG_NEXT_HOP_NUMBER_PR0_ADDR(inst) ((inst) + 0x0000008C) +#define BF_NEXT_HOP_NUMBER_PR0_INFO(inst) ((inst) + 0x0000008C), 0x00000600 + +#ifdef USE_PRIVATE_BF +#define REG_NEXT_HOP_NUMBER_PR1_ADDR(inst) ((inst) + 0x0000008D) +#define BF_NEXT_HOP_NUMBER_PR1_INFO(inst) ((inst) + 0x0000008D), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#define REG_NEXT_HOP_NUMBER_PR2_ADDR(inst) ((inst) + 0x0000008E) +#define BF_NEXT_HOP_NUMBER_PR2_INFO(inst) ((inst) + 0x0000008E), 0x00000600 + +#ifdef USE_PRIVATE_BF +#define REG_NEXT_HOP_NUMBER_PR3_ADDR(inst) ((inst) + 0x0000008F) +#define BF_NEXT_HOP_NUMBER_PR3_INFO(inst) ((inst) + 0x0000008F), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_NEXT_HOP_NUMBER_PR4_ADDR(inst) ((inst) + 0x00000090) +#define BF_NEXT_HOP_NUMBER_PR4_INFO(inst) ((inst) + 0x00000090), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_NEXT_HOP_NUMBER_PR5_ADDR(inst) ((inst) + 0x00000091) +#define BF_NEXT_HOP_NUMBER_PR5_INFO(inst) ((inst) + 0x00000091), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#define REG_PROFILE_GRP_COUNTER_VAL_PR0_ADDR(inst) ((inst) + 0x00000092) +#define BF_PROFILE_GRP_COUNTER_VAL_INFO(inst) ((inst) + 0x00000092), 0x00002400 + +#define REG_PROFILE_GRP_COUNTER_VAL_PR1_ADDR(inst) ((inst) + 0x00000093) + +#define REG_PROFILE_GRP_COUNTER_VAL_PR2_ADDR(inst) ((inst) + 0x00000094) + +#define REG_PROFILE_GRP_COUNTER_VAL_PR3_ADDR(inst) ((inst) + 0x00000095) + +#define REG_PROFILE_GRP_COUNTER_VAL_PR4_ADDR(inst) ((inst) + 0x00000096) + +#define REG_PROFILE_GRP_COUNTER_VAL_PR5_ADDR(inst) ((inst) + 0x00000097) + +#define REG_PROFILE_SEL_MODE_TXRX_FINE_NCO_ADDR(inst) ((inst) + 0x00000098) +#define BF_PROFILE_SEL_MODE_TXRX_FINE_NCO_INFO(inst) ((inst) + 0x00000098), 0x00000400 + +#define REG_REGMAP_HOPPROF_ADDR(inst) ((inst) + 0x00000099) +#define BF_REGMAP_HOPPROF_INFO(inst) ((inst) + 0x00000099), 0x00000600 + +#define REG_SAW_POSNEG_SEL_ADDR(inst) ((inst) + 0x0000009A) +#define BF_SAW_POSNEG_SEL_INFO(inst) ((inst) + 0x0000009A), 0x00000100 + +#define REG_SQW_HIGH0_ADDR(inst) ((inst) + 0x0000009C) +#define BF_SQW_HIGH0_INFO(inst) ((inst) + 0x0000009C), 0x00000800 + +#define REG_SQW_HIGH1_ADDR(inst) ((inst) + 0x0000009D) +#define BF_SQW_HIGH1_INFO(inst) ((inst) + 0x0000009D), 0x00000800 + +#define REG_SQW_LOW0_ADDR(inst) ((inst) + 0x0000009E) +#define BF_SQW_LOW0_INFO(inst) ((inst) + 0x0000009E), 0x00000800 + +#define REG_SQW_LOW1_ADDR(inst) ((inst) + 0x0000009F) +#define BF_SQW_LOW1_INFO(inst) ((inst) + 0x0000009F), 0x00000800 + +#define REG_TRIG_HOP_SEL0_ADDR(inst) ((inst) + 0x000000A0) +#define BF_TRIG_HOP_SEL0_INFO(inst) ((inst) + 0x000000A0), 0x00000600 + +#ifdef USE_PRIVATE_BF +#define REG_TRIG_HOP_SEL1_ADDR(inst) ((inst) + 0x000000A1) +#define BF_TRIG_HOP_SEL1_INFO(inst) ((inst) + 0x000000A1), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TRIG_HOP_SEL2_ADDR(inst) ((inst) + 0x000000A2) +#define BF_TRIG_HOP_SEL2_INFO(inst) ((inst) + 0x000000A2), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TRIG_HOP_SEL3_ADDR(inst) ((inst) + 0x000000A3) +#define BF_TRIG_HOP_SEL3_INFO(inst) ((inst) + 0x000000A3), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TRIG_HOP_SEL4_ADDR(inst) ((inst) + 0x000000A4) +#define BF_TRIG_HOP_SEL4_INFO(inst) ((inst) + 0x000000A4), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TRIG_HOP_SEL5_ADDR(inst) ((inst) + 0x000000A5) +#define BF_TRIG_HOP_SEL5_INFO(inst) ((inst) + 0x000000A5), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_WAVE_OFFSET0_ADDR(inst) ((inst) + 0x000000A6) +#define BF_WAVE_OFFSET0_INFO(inst) ((inst) + 0x000000A6), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_WAVE_OFFSET1_ADDR(inst) ((inst) + 0x000000A7) +#define BF_WAVE_OFFSET1_INFO(inst) ((inst) + 0x000000A7), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_WAVE_SEL_ADDR(inst) ((inst) + 0x000000A8) +#define BF_WAVE_SEL_INFO(inst) ((inst) + 0x000000A8), 0x00000200 + +#define REG_PCT_RST_CTRL_TXRX_FINE_NCO_ADDR(inst) ((inst) + 0x000000A9) +#define BF_TS_RST_MODE_TXRX_FINE_NCO_INFO(inst) ((inst) + 0x000000A9), 0x00000100 +#define BF_SPI_TS_RST_TXRX_FINE_NCO_INFO(inst) ((inst) + 0x000000A9), 0x00000101 + +#define REG_PCT_RST_STATUS_TXRX_FINE_NCO_ADDR(inst) ((inst) + 0x000000AA) +#define BF_RST_DONE_TXRX_FINE_NCO_INFO(inst) ((inst) + 0x000000AA), 0x00000100 +#define BF_RST_DONE_CLR_TXRX_FINE_NCO_INFO(inst) ((inst) + 0x000000AA), 0x00000101 + +#define REG_PCT_RD_EN_TXRX_FINE_NCO_ADDR(inst) ((inst) + 0x000000AB) +#define BF_TIMESTAMP_READ_EN_TXRX_FINE_NCO_INFO(inst) ((inst) + 0x000000AB), 0x00000100 + +#define REG_PCT_STATUS0_TXRX_FINE_NCO_ADDR(inst) ((inst) + 0x000000AC) +#define BF_TIMESTAMP_STATUS_TXRX_FINE_NCO_INFO(inst) ((inst) + 0x000000AC), 0x00004000 + +#define REG_PCT_STATUS1_TXRX_FINE_NCO_ADDR(inst) ((inst) + 0x000000AD) + +#define REG_PCT_STATUS2_TXRX_FINE_NCO_ADDR(inst) ((inst) + 0x000000AE) + +#define REG_PCT_STATUS3_TXRX_FINE_NCO_ADDR(inst) ((inst) + 0x000000AF) + +#define REG_PCT_STATUS4_TXRX_FINE_NCO_ADDR(inst) ((inst) + 0x000000B0) + +#define REG_PCT_STATUS5_TXRX_FINE_NCO_ADDR(inst) ((inst) + 0x000000B1) + +#define REG_PCT_STATUS6_TXRX_FINE_NCO_ADDR(inst) ((inst) + 0x000000B2) + +#define REG_PCT_STATUS7_TXRX_FINE_NCO_ADDR(inst) ((inst) + 0x000000B3) + +#define REG_MXR_TEST_MODE_VAL0_ADDR(inst) ((inst) + 0x000000B4) +#define BF_MIXER_TEST_MODE_VAL_TXRX_FINE_NCO_INFO(inst) ((inst) + 0x000000B4), 0x00001000 + +#define REG_MXR_TEST_MODE_VAL1_ADDR(inst) ((inst) + 0x000000B5) + +#endif /* __ADI_APOLLO_BF_TXRX_FINE_NCO_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_txrx_fsrc.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_txrx_fsrc.h new file mode 100644 index 00000000000000..20983a4f028ba3 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_txrx_fsrc.h @@ -0,0 +1,234 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:20 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_TXRX_FSRC_H__ +#define __ADI_APOLLO_BF_TXRX_FSRC_H__ + +/*============= D E F I N E S ==============*/ +#define RX_FSRC_RX_SLICE_0_RX_DIGITAL0 0x60366000 +#define RX_FSRC_RX_SLICE_1_RX_DIGITAL0 0x60566000 +#define RX_FSRC_RX_SLICE_0_RX_DIGITAL1 0x60B66000 +#define RX_FSRC_RX_SLICE_1_RX_DIGITAL1 0x60D66000 +#define TX_FSRC_TX_SLICE_0_TX_DIGITAL0 0x61306000 +#define TX_FSRC_TX_SLICE_1_TX_DIGITAL0 0x61506000 +#define TX_FSRC_TX_SLICE_0_TX_DIGITAL1 0x61B06000 +#define TX_FSRC_TX_SLICE_1_TX_DIGITAL1 0x61D06000 + +#define REG_FSRC_RATE_INT_0_ADDR(inst) ((inst) + 0x00000001) +#define BF_FSRC_RATE_INT_INFO(inst) ((inst) + 0x00000001), 0x00003000 + +#define REG_FSRC_RATE_INT_1_ADDR(inst) ((inst) + 0x00000002) + +#define REG_FSRC_RATE_INT_2_ADDR(inst) ((inst) + 0x00000003) + +#define REG_FSRC_RATE_INT_3_ADDR(inst) ((inst) + 0x00000004) + +#define REG_FSRC_RATE_INT_4_ADDR(inst) ((inst) + 0x00000005) + +#define REG_FSRC_RATE_INT_5_ADDR(inst) ((inst) + 0x00000006) + +#define REG_FSRC_RATE_FRAC_A_0_ADDR(inst) ((inst) + 0x00000007) +#define BF_FSRC_RATE_FRAC_A_INFO(inst) ((inst) + 0x00000007), 0x00003000 + +#define REG_FSRC_RATE_FRAC_A_1_ADDR(inst) ((inst) + 0x00000008) + +#define REG_FSRC_RATE_FRAC_A_2_ADDR(inst) ((inst) + 0x00000009) + +#define REG_FSRC_RATE_FRAC_A_3_ADDR(inst) ((inst) + 0x0000000A) + +#define REG_FSRC_RATE_FRAC_A_4_ADDR(inst) ((inst) + 0x0000000B) + +#define REG_FSRC_RATE_FRAC_A_5_ADDR(inst) ((inst) + 0x0000000C) + +#define REG_FSRC_RATE_FRAC_B_0_ADDR(inst) ((inst) + 0x0000000D) +#define BF_FSRC_RATE_FRAC_B_INFO(inst) ((inst) + 0x0000000D), 0x00003000 + +#define REG_FSRC_RATE_FRAC_B_1_ADDR(inst) ((inst) + 0x0000000E) + +#define REG_FSRC_RATE_FRAC_B_2_ADDR(inst) ((inst) + 0x0000000F) + +#define REG_FSRC_RATE_FRAC_B_3_ADDR(inst) ((inst) + 0x00000010) + +#define REG_FSRC_RATE_FRAC_B_4_ADDR(inst) ((inst) + 0x00000011) + +#define REG_FSRC_RATE_FRAC_B_5_ADDR(inst) ((inst) + 0x00000012) + +#define REG_SAMPLE_FRAC_DELAY_0_ADDR(inst) ((inst) + 0x00000013) +#define BF_SAMPLE_FRAC_DELAY_INFO(inst) ((inst) + 0x00000013), 0x00001000 + +#define REG_SAMPLE_FRAC_DELAY_1_ADDR(inst) ((inst) + 0x00000014) + +#ifdef USE_PRIVATE_BF +#define REG_FSRC_ROUND_WORD_0_ADDR(inst) ((inst) + 0x00000015) +#define BF_FSRC_ROUND_WORD_INFO(inst) ((inst) + 0x00000015), 0x00001800 +#endif /* USE_PRIVATE_BF */ + +#define REG_FSRC_ROUND_WORD_1_ADDR(inst) ((inst) + 0x00000016) + +#define REG_FSRC_ROUND_WORD_2_ADDR(inst) ((inst) + 0x00000017) + +#ifdef USE_PRIVATE_BF +#define REG_SAMPLE_FRAC_DELAY_CTRL_ADDR(inst) ((inst) + 0x00000018) +#define BF_FRAC_DELAY_SAMPLE_SHIFT_FIX_INFO(inst) ((inst) + 0x00000018), 0x00000100 +#define BF_SAMPLE_FRAC_DELAY_LOAD_INFO(inst) ((inst) + 0x00000018), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#define REG_GAIN_REDUCTION_0_ADDR(inst) ((inst) + 0x00000019) +#define BF_GAIN_REDUCTION_INFO(inst) ((inst) + 0x00000019), 0x00000C00 + +#define REG_GAIN_REDUCTION_1_ADDR(inst) ((inst) + 0x0000001A) + +#define REG_PTR_SYNCRSTVAL_CTRL_ADDR(inst) ((inst) + 0x0000001B) +#define BF_PTR_SYNCRSTVAL_INFO(inst) ((inst) + 0x0000001B), 0x00000600 +#define BF_PTR_SYNCRSTVAL_REGMAP_OVERWRITE_INFO(inst) ((inst) + 0x0000001B), 0x00000107 + +#define REG_FSRC_CTRL_ADDR(inst) ((inst) + 0x0000001C) +#define BF_FSRC_EN0_INFO(inst) ((inst) + 0x0000001C), 0x00000100 +#define BF_FSRC_EN1_INFO(inst) ((inst) + 0x0000001C), 0x00000101 +#define BF_FSRC_BYPASS_INFO(inst) ((inst) + 0x0000001C), 0x00000102 +#define BF_FSRC_4T4R_SPLIT_INFO(inst) ((inst) + 0x0000001C), 0x00000103 +#define BF_FSRC_DITHER_EN_INFO(inst) ((inst) + 0x0000001C), 0x00000105 +#define BF_FSRC_DATA_MULT_DITHER_EN_INFO(inst) ((inst) + 0x0000001C), 0x00000106 +#ifdef USE_PRIVATE_BF +#define BF_FSRC_1X_MODE_INFO(inst) ((inst) + 0x0000001C), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CLOCK_GATE_EN_GEN_OFFSET_ADDR(inst) ((inst) + 0x0000001D) +#define BF_FIXED_CLK_GATE_EN_GEN_OFFSET_INFO(inst) ((inst) + 0x0000001D), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CLOCK_GATE_GEN_CTRL_ADDR(inst) ((inst) + 0x0000001E) +#define BF_CLKGATE_GEN_WAIT_FOR_SYNC_INFO(inst) ((inst) + 0x0000001E), 0x00000100 +#define BF_CLKGATE_GEN_RESET_INFO(inst) ((inst) + 0x0000001E), 0x00000101 +#endif /* USE_PRIVATE_BF */ + +#define REG_FSRC_IRQ_EN_ADDR(inst) ((inst) + 0x0000001F) +#define BF_EN_FSRC_CH0_OVR_I_IRQ_INFO(inst) ((inst) + 0x0000001F), 0x00000100 +#define BF_EN_FSRC_CH0_OVR_Q_IRQ_INFO(inst) ((inst) + 0x0000001F), 0x00000101 +#define BF_EN_FSRC_CH1_OVR_I_IRQ_INFO(inst) ((inst) + 0x0000001F), 0x00000102 +#define BF_EN_FSRC_CH1_OVR_Q_IRQ_INFO(inst) ((inst) + 0x0000001F), 0x00000103 + +#define REG_FSRC_OVERFLOW_ADDR(inst) ((inst) + 0x00000020) +#define BF_IRQ_CH0_FSRC_I_OVER_FLOW_INFO(inst) ((inst) + 0x00000020), 0x00000100 +#define BF_IRQ_CH0_FSRC_Q_OVER_FLOW_INFO(inst) ((inst) + 0x00000020), 0x00000101 +#define BF_IRQ_CH1_FSRC_I_OVER_FLOW_INFO(inst) ((inst) + 0x00000020), 0x00000102 +#define BF_IRQ_CH1_FSRC_Q_OVER_FLOW_INFO(inst) ((inst) + 0x00000020), 0x00000103 +#define BF_IRQ_FSRC_OVER_FLOW_ALL_INFO(inst) ((inst) + 0x00000020), 0x00000104 + +#ifdef USE_PRIVATE_BF +#define REG_FSRC_BASE_OFFSET_ADDR(inst) ((inst) + 0x00000021) +#define BF_FSRC_BASE_OFFSET_INFO(inst) ((inst) + 0x00000021), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FSRC_CLK_OFFSET_WR_EN_ADDR(inst) ((inst) + 0x00000022) +#define BF_FSRC_CLK_GEN_PHASE_OFFSET_WR_EN_INFO(inst) ((inst) + 0x00000022), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FSRC_CLK_DEBUG_ADDR(inst) ((inst) + 0x00000023) +#define BF_DEBUG_FSRC_CLKOFF_EN_INFO(inst) ((inst) + 0x00000023), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FSRC_I_IN_OFFSET_PH0_ADDR(inst) ((inst) + 0x00000024) +#define BF_FSRC_I_IN_OFFSET_PH0_INFO(inst) ((inst) + 0x00000024), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FSRC_I_IN_OFFSET_PH1_ADDR(inst) ((inst) + 0x00000025) +#define BF_FSRC_I_IN_OFFSET_PH1_INFO(inst) ((inst) + 0x00000025), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FSRC_I_OUT_OFFSET_PH0_ADDR(inst) ((inst) + 0x00000026) +#define BF_FSRC_I_OUT_OFFSET_PH0_INFO(inst) ((inst) + 0x00000026), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FSRC_I_OUT_OFFSET_PH1_ADDR(inst) ((inst) + 0x00000027) +#define BF_FSRC_I_OUT_OFFSET_PH1_INFO(inst) ((inst) + 0x00000027), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FSRC_Q_IN_OFFSET_PH0_ADDR(inst) ((inst) + 0x00000028) +#define BF_FSRC_Q_IN_OFFSET_PH0_INFO(inst) ((inst) + 0x00000028), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FSRC_Q_IN_OFFSET_PH1_ADDR(inst) ((inst) + 0x00000029) +#define BF_FSRC_Q_IN_OFFSET_PH1_INFO(inst) ((inst) + 0x00000029), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FSRC_Q_OUT_OFFSET_PH0_ADDR(inst) ((inst) + 0x0000002A) +#define BF_FSRC_Q_OUT_OFFSET_PH0_INFO(inst) ((inst) + 0x0000002A), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FSRC_Q_OUT_OFFSET_PH1_ADDR(inst) ((inst) + 0x0000002B) +#define BF_FSRC_Q_OUT_OFFSET_PH1_INFO(inst) ((inst) + 0x0000002B), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TX_FSRC_MUX_CTRL_ADDR(inst) ((inst) + 0x0000002C) +#define BF_FSRC_IN_MUX_SEL_INFO(inst) ((inst) + 0x0000002C), 0x00000200 +#define BF_FSRC_OUT_MUX_SEL_INFO(inst) ((inst) + 0x0000002C), 0x00000202 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FSRC_Q_FILT_CTRL_ADDR(inst) ((inst) + 0x0000002D) +#define BF_FSRC_Q_FILT_FIFO_SYNC_CTRL_INFO(inst) ((inst) + 0x0000002D), 0x00000200 +#define BF_FSRC_Q_FILT_ROOT_CLK_CTRL_INFO(inst) ((inst) + 0x0000002D), 0x00000102 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FSRC_GATED_CLK_VALID_ADDR(inst) ((inst) + 0x0000002E) +#define BF_GATED_CLK_VALID_INFO(inst) ((inst) + 0x0000002E), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#define REG_FSRC_BIST_CTRL_ADDR(inst) ((inst) + 0x00000030) +#define BF_FSRC_BIST_EN_INFO(inst) ((inst) + 0x00000030), 0x00000100 +#ifdef USE_PRIVATE_BF +#define BF_FSRC_BIST_INIT_INFO(inst) ((inst) + 0x00000030), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FSRC_BIST_EN_STATUS_ADDR(inst) ((inst) + 0x00000031) +#define BF_FSRC_BIST_EN_STATUS_INFO(inst) ((inst) + 0x00000031), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FSRC_BIST_CRC_LO_ADDR(inst) ((inst) + 0x00000032) +#define BF_FSRC_BIST_CRC_INFO(inst) ((inst) + 0x00000032), 0x00001000 +#endif /* USE_PRIVATE_BF */ + +#define REG_FSRC_BIST_CRC_HI_ADDR(inst) ((inst) + 0x00000033) + +#define REG_FSRC_NS_SEL_CTRL_ADDR(inst) ((inst) + 0x00000034) +#ifdef USE_PRIVATE_BF +#define BF_FSRC_NS_SEL_INFO(inst) ((inst) + 0x00000034), 0x00000200 +#endif /* USE_PRIVATE_BF */ +#define BF_FSRC_NS_SEL_OVERWRITE_INFO(inst) ((inst) + 0x00000034), 0x00000104 + +#ifdef USE_PRIVATE_BF +#define REG_FSRC_NS_READ_ADDR(inst) ((inst) + 0x00000035) +#define BF_FSRC_NS_RS_INFO(inst) ((inst) + 0x00000035), 0x00000300 +#define BF_FSRC_NS_SPLIT_INVALID_INFO(inst) ((inst) + 0x00000035), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#endif /* __ADI_APOLLO_BF_TXRX_FSRC_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_txrx_pfilt_coeff.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_txrx_pfilt_coeff.h new file mode 100644 index 00000000000000..b8b547a7e12321 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_txrx_pfilt_coeff.h @@ -0,0 +1,47 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:21 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_TXRX_PFILT_COEFF_H__ +#define __ADI_APOLLO_BF_TXRX_PFILT_COEFF_H__ + +/*============= D E F I N E S ==============*/ +#define RX_PFILT_COEFF0_RX_SLICE_0_RX_DIGITAL0 0x60378000 +#define RX_PFILT_COEFF1_RX_SLICE_0_RX_DIGITAL0 0x60379000 +#define RX_PFILT_COEFF0_RX_SLICE_1_RX_DIGITAL0 0x60578000 +#define RX_PFILT_COEFF1_RX_SLICE_1_RX_DIGITAL0 0x60579000 +#define RX_PFILT_COEFF0_RX_SLICE_0_RX_DIGITAL1 0x60B78000 +#define RX_PFILT_COEFF1_RX_SLICE_0_RX_DIGITAL1 0x60B79000 +#define RX_PFILT_COEFF0_RX_SLICE_1_RX_DIGITAL1 0x60D78000 +#define RX_PFILT_COEFF1_RX_SLICE_1_RX_DIGITAL1 0x60D79000 +#define TX_PFILT_COEFF0_TX_SLICE_0_TX_DIGITAL0 0x61338000 +#define TX_PFILT_COEFF1_TX_SLICE_0_TX_DIGITAL0 0x61339000 +#define TX_PFILT_COEFF0_TX_SLICE_1_TX_DIGITAL0 0x61538000 +#define TX_PFILT_COEFF1_TX_SLICE_1_TX_DIGITAL0 0x61539000 +#define TX_PFILT_COEFF0_TX_SLICE_0_TX_DIGITAL1 0x61B38000 +#define TX_PFILT_COEFF1_TX_SLICE_0_TX_DIGITAL1 0x61B39000 +#define TX_PFILT_COEFF0_TX_SLICE_1_TX_DIGITAL1 0x61D38000 +#define TX_PFILT_COEFF1_TX_SLICE_1_TX_DIGITAL1 0x61D39000 + +#define REG_COEFF_0_LSB_ADDR(inst, n) ((inst) + 0x00000000 + 2 * (n)) +#define BF_COEFF_0_INFO(inst, n) ((inst) + 0x00000000 + 2 * (n)), 0x00001000 + +#define REG_COEFF_0_MSB_ADDR(inst, n) ((inst) + 0x00000001 + 2 * (n)) + +#define REG_COEFF_1_LSB_ADDR(inst, n) ((inst) + 0x00000040 + 2 * (n)) +#define BF_COEFF_1_INFO(inst, n) ((inst) + 0x00000040 + 2 * (n)), 0x00001000 + +#define REG_COEFF_1_MSB_ADDR(inst, n) ((inst) + 0x00000041 + 2 * (n)) + +#endif /* __ADI_APOLLO_BF_TXRX_PFILT_COEFF_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_txrx_pfilt_top.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_txrx_pfilt_top.h new file mode 100644 index 00000000000000..2d092235eb4126 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_txrx_pfilt_top.h @@ -0,0 +1,128 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:21 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_TXRX_PFILT_TOP_H__ +#define __ADI_APOLLO_BF_TXRX_PFILT_TOP_H__ + +/*============= D E F I N E S ==============*/ +#define RX_PFILT_TOP_RX_SLICE_0_RX_DIGITAL0 0x6037A000 +#define RX_PFILT_TOP_RX_SLICE_1_RX_DIGITAL0 0x6057A000 +#define RX_PFILT_TOP_RX_SLICE_0_RX_DIGITAL1 0x60B7A000 +#define RX_PFILT_TOP_RX_SLICE_1_RX_DIGITAL1 0x60D7A000 +#define TX_PFILT_TOP_TX_SLICE_0_TX_DIGITAL0 0x6133A000 +#define TX_PFILT_TOP_TX_SLICE_1_TX_DIGITAL0 0x6153A000 +#define TX_PFILT_TOP_TX_SLICE_0_TX_DIGITAL1 0x61B3A000 +#define TX_PFILT_TOP_TX_SLICE_1_TX_DIGITAL1 0x61D3A000 + +#define REG_PFIR_MODE_ADDR(inst, n) ((inst) + 0x0000000C + 1 * (n)) +#define BF_PFIR_I_MODE_INFO(inst, n) ((inst) + 0x0000000C + 1 * (n)), 0x00000400 +#define BF_PFIR_Q_MODE_INFO(inst, n) ((inst) + 0x0000000C + 1 * (n)), 0x00000404 + +#ifdef USE_PRIVATE_BF +#define REG_LEGACY_PFIR_I_GAIN_ADDR(inst, n) ((inst) + 0x0000000E + 1 * (n)) +#define BF_LEGACY_PFIR_IX_GAIN_INFO(inst, n) ((inst) + 0x0000000E + 1 * (n)), 0x00000300 +#define BF_LEGACY_PFIR_IY_GAIN_INFO(inst, n) ((inst) + 0x0000000E + 1 * (n)), 0x00000303 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_LEGACY_PFIR_Q_GAIN_ADDR(inst, n) ((inst) + 0x00000010 + 1 * (n)) +#define BF_LEGACY_PFIR_QX_GAIN_INFO(inst, n) ((inst) + 0x00000010 + 1 * (n)), 0x00000300 +#define BF_LEGACY_PFIR_QY_GAIN_INFO(inst, n) ((inst) + 0x00000010 + 1 * (n)), 0x00000303 +#endif /* USE_PRIVATE_BF */ + +#define REG_PFIR_BIST_CTRL_ADDR(inst, n) ((inst) + 0x00000012 + 1 * (n)) +#ifdef USE_PRIVATE_BF +#define BF_PFIR_BIST_EN_INFO(inst, n) ((inst) + 0x00000012 + 1 * (n)), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#ifdef USE_PRIVATE_BF +#define BF_PFIR_BIST_INIT_INFO(inst, n) ((inst) + 0x00000012 + 1 * (n)), 0x00000101 +#endif /* USE_PRIVATE_BF */ +#ifdef USE_PRIVATE_BF +#define BF_PFIR_BIST_EN_STATUS_INFO(inst, n) ((inst) + 0x00000012 + 1 * (n)), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#ifdef USE_PRIVATE_BF +#define BF_DITHER_DIS_INFO(inst, n) ((inst) + 0x00000012 + 1 * (n)), 0x00000103 +#endif /* USE_PRIVATE_BF */ +#define BF_OUTPUT_DITHER_EN_INFO(inst, n) ((inst) + 0x00000012 + 1 * (n)), 0x00000104 + +#ifdef USE_PRIVATE_BF +#define REG_DELAY_SETTING_ADDR(inst, n) ((inst) + 0x00000014 + 1 * (n)) +#define BF_DELAY_SETTING_INFO(inst, n) ((inst) + 0x00000014 + 1 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_PFIR_COEFF_TRANSFER_ADDR(inst, n) ((inst) + 0x00000016 + 1 * (n)) +#define BF_PFIR_COEFF_TRANSFER_INFO(inst, n) ((inst) + 0x00000016 + 1 * (n)), 0x00000100 + +#ifdef USE_PRIVATE_BF +#define REG_PFIR_BIST_CRC_LSB_ADDR(inst, n) ((inst) + 0x00000018 + 1 * (n)) +#define BF_PFIR_BIST_CRC_INFO(inst, n) ((inst) + 0x00000018 + 1 * (n)), 0x00001000 +#endif /* USE_PRIVATE_BF */ + +#define REG_PFIR_BIST_CRC_MSB_ADDR(inst, n) ((inst) + 0x0000001A + 1 * (n)) + +#define REG_HC_PROG_DELAY_ADDR(inst, n) ((inst) + 0x0000001C + 1 * (n)) +#define BF_HC_PROG_DELAY_INFO(inst, n) ((inst) + 0x0000001C + 1 * (n)), 0x00000700 + +#define REG_MODE_AND_DATA_TYPE_SEL_ADDR(inst) ((inst) + 0x00000024) +#define BF_QUAD_MODE_INFO(inst) ((inst) + 0x00000024), 0x00000100 +#define BF_REAL_DATA_INFO(inst) ((inst) + 0x00000024), 0x00000101 +#define BF_MODE_SWITCH_INFO(inst) ((inst) + 0x00000024), 0x00000102 +#define BF_ADD_SUB_SEL_INFO(inst) ((inst) + 0x00000024), 0x00000103 + +#define REG_PFILT_TRIGGER_EN_ADDR(inst) ((inst) + 0x00000025) +#define BF_PFILT_TRIGGER_EN_INFO(inst) ((inst) + 0x00000025), 0x00000100 + +#define REG_PFILT_CONTROL_ADDR(inst) ((inst) + 0x00000026) +#define BF_EQ_GPIO_EN_INFO(inst) ((inst) + 0x00000026), 0x00000100 +#define BF_GPIO_CONFIG1_INFO(inst) ((inst) + 0x00000026), 0x00000101 +#define BF_DISABLE_ORX_INFO(inst) ((inst) + 0x00000026), 0x00000402 + +#define REG_RD_COEFF_PAGE_SEL_ADDR(inst, n) ((inst) + 0x00000027 + 1 * (n)) +#define BF_RD_COEFF_PAGE_SEL_INFO(inst, n) ((inst) + 0x00000027 + 1 * (n)), 0x00000200 + +#ifdef USE_PRIVATE_BF +#define REG_EIGER_MODE_ADDR(inst) ((inst) + 0x00000029) +#define BF_EIGER_MODE_INFO(inst) ((inst) + 0x00000029), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_PFIR_I_GAIN_ADDR(inst, n) ((inst) + 0x00000030 + 1 * (n)) +#define BF_PFIR_IX_GAIN_INFO(inst, n) ((inst) + 0x00000030 + 1 * (n)), 0x00000400 +#define BF_PFIR_IY_GAIN_INFO(inst, n) ((inst) + 0x00000030 + 1 * (n)), 0x00000404 + +#define REG_PFIR_Q_GAIN_ADDR(inst, n) ((inst) + 0x00000048 + 1 * (n)) +#define BF_PFIR_QX_GAIN_INFO(inst, n) ((inst) + 0x00000048 + 1 * (n)), 0x00000400 +#define BF_PFIR_QY_GAIN_INFO(inst, n) ((inst) + 0x00000048 + 1 * (n)), 0x00000404 + +#define REG_PFIR_IX_SCALAR_GAIN_ADDR(inst, n) ((inst) + 0x00000060 + 1 * (n)) +#define BF_PFIR_IX_SCALAR_GAIN_INFO(inst, n) ((inst) + 0x00000060 + 1 * (n)), 0x00000600 + +#define REG_PFIR_IY_SCALAR_GAIN_ADDR(inst, n) ((inst) + 0x00000078 + 1 * (n)) +#define BF_PFIR_IY_SCALAR_GAIN_INFO(inst, n) ((inst) + 0x00000078 + 1 * (n)), 0x00000600 + +#define REG_PFIR_QX_SCALAR_GAIN_ADDR(inst, n) ((inst) + 0x00000090 + 1 * (n)) +#define BF_PFIR_QX_SCALAR_GAIN_INFO(inst, n) ((inst) + 0x00000090 + 1 * (n)), 0x00000600 + +#define REG_PFIR_QY_SCALAR_GAIN_ADDR(inst, n) ((inst) + 0x00000108 + 1 * (n)) +#define BF_PFIR_QY_SCALAR_GAIN_INFO(inst, n) ((inst) + 0x00000108 + 1 * (n)), 0x00000600 + +#define REG_PFILT_IRQ_ENABLE_ADDR(inst) ((inst) + 0x00000110) +#define BF_IRQ_ENABLE_I_TXRX_PFILT_TOP_INFO(inst) ((inst) + 0x00000110), 0x00000100 +#define BF_IRQ_ENABLE_Q_TXRX_PFILT_TOP_INFO(inst) ((inst) + 0x00000110), 0x00000101 + +#define REG_PFILT_IRQ_STATUS_ADDR(inst) ((inst) + 0x00000111) +#define BF_IRQ_STATUS_I_TXRX_PFILT_TOP_INFO(inst) ((inst) + 0x00000111), 0x00000100 +#define BF_IRQ_STATUS_Q_TXRX_PFILT_TOP_INFO(inst) ((inst) + 0x00000111), 0x00000101 + +#endif /* __ADI_APOLLO_BF_TXRX_PFILT_TOP_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_txrx_postfsrc_reconf.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_txrx_postfsrc_reconf.h new file mode 100644 index 00000000000000..9e70bc0928352e --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_txrx_postfsrc_reconf.h @@ -0,0 +1,59 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:20 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_TXRX_POSTFSRC_RECONF_H__ +#define __ADI_APOLLO_BF_TXRX_POSTFSRC_RECONF_H__ + +/*============= D E F I N E S ==============*/ +#define TXRX_POSTFSRC_RECONF_RX_SLICE_0_RX_DIGITAL0 0x6036E000 +#define TXRX_POSTFSRC_RECONF_RX_SLICE_1_RX_DIGITAL0 0x6056E000 +#define TXRX_POSTFSRC_RECONF_RX_SLICE_0_RX_DIGITAL1 0x60B6E000 +#define TXRX_POSTFSRC_RECONF_RX_SLICE_1_RX_DIGITAL1 0x60D6E000 +#define TXRX_POSTFSRC_RECONF_TX_SLICE_0_TX_DIGITAL0 0x6130D000 +#define TXRX_POSTFSRC_RECONF_TX_SLICE_1_TX_DIGITAL0 0x6150D000 +#define TXRX_POSTFSRC_RECONF_TX_SLICE_0_TX_DIGITAL1 0x61B0D000 +#define TXRX_POSTFSRC_RECONF_TX_SLICE_1_TX_DIGITAL1 0x61D0D000 + +#define REG_POSTFSRC_RECONF_LCM0_ADDR(inst) ((inst) + 0x000002EB) +#define BF_POSTFSRC_LCM_INFO(inst) ((inst) + 0x000002EB), 0x00001000 + +#define REG_POSTFSRC_RECONF_LCM1_ADDR(inst) ((inst) + 0x000002EC) + +#ifdef USE_PRIVATE_BF +#define REG_POSTFSRC_SM_STATE_ADDR(inst) ((inst) + 0x000002F3) +#define BF_POSTFSRC_SM_STATE_INFO(inst) ((inst) + 0x000002F3), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#define REG_RECONFIG_RAMP_WIDTH_TXRX_POSTFSRC_RECONF_ADDR(inst) ((inst) + 0x000002F4) +#define BF_RECONFIG_RAMP_WIDTH_TXRX_POSTFSRC_RECONF_INFO(inst) ((inst) + 0x000002F4), 0x00000500 + +#define REG_RECONFIG_ERROR_STATUS_ADDR(inst) ((inst) + 0x000002F5) +#define BF_TIME_ERROR_STATUS_TXRX_POSTFSRC_RECONF_INFO(inst) ((inst) + 0x000002F5), 0x00000100 + +#define REG_POSTFSRC_NEWCLK_DLY_ADDR(inst) ((inst) + 0x000002F6) +#define BF_NEWCLK_DLY_TXRX_POSTFSRC_RECONF_INFO(inst) ((inst) + 0x000002F6), 0x00000500 + +#define REG_POSTFSRC_RECONFIG_DONE_ADDR(inst) ((inst) + 0x000002F7) +#define BF_RECONFIG_DONE_INFO(inst) ((inst) + 0x000002F7), 0x00000100 + +#ifdef USE_PRIVATE_BF +#define REG_POSTFSRC_FORCE_NEWCLK_ADDR(inst) ((inst) + 0x000002F8) +#define BF_FORCE_NEWCLK_TXRX_POSTFSRC_RECONF_INFO(inst) ((inst) + 0x000002F8), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#define REG_EXTRA_RECONFIG_DLY_ADDR(inst) ((inst) + 0x000002F9) +#define BF_EXTRA_RECONFIG_DLY_INFO(inst) ((inst) + 0x000002F9), 0x00000400 + +#endif /* __ADI_APOLLO_BF_TXRX_POSTFSRC_RECONF_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_txrx_prefsrc_reconf.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_txrx_prefsrc_reconf.h new file mode 100644 index 00000000000000..4180244206cc39 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_txrx_prefsrc_reconf.h @@ -0,0 +1,91 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:19 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_TXRX_PREFSRC_RECONF_H__ +#define __ADI_APOLLO_BF_TXRX_PREFSRC_RECONF_H__ + +/*============= D E F I N E S ==============*/ +#define TXRX_PREFSRC_RECONF_RX_SLICE_0_RX_DIGITAL0 0x6020A000 +#define TXRX_PREFSRC_RECONF_RX_SLICE_1_RX_DIGITAL0 0x6040A000 +#define TXRX_PREFSRC_RECONF_RX_SLICE_0_RX_DIGITAL1 0x60A0A000 +#define TXRX_PREFSRC_RECONF_RX_SLICE_1_RX_DIGITAL1 0x60C0A000 +#define TXRX_PREFSRC_RECONF_TX_SLICE_0_TX_DIGITAL0 0x6120B000 +#define TXRX_PREFSRC_RECONF_TX_SLICE_1_TX_DIGITAL0 0x6140B000 +#define TXRX_PREFSRC_RECONF_TX_SLICE_0_TX_DIGITAL1 0x61A0B000 +#define TXRX_PREFSRC_RECONF_TX_SLICE_1_TX_DIGITAL1 0x61C0B000 + +#define REG_PREFSRC_RECONF_SYNC_CTRL_ADDR(inst) ((inst) + 0x000002E8) +#ifdef USE_PRIVATE_BF +#define BF_FORCE_TS_SYNC_INFO(inst) ((inst) + 0x000002E8), 0x00000101 +#endif /* USE_PRIVATE_BF */ +#define BF_NONRESYNC_SYSREF_EN_INFO(inst) ((inst) + 0x000002E8), 0x00000102 +#define BF_TRIG_RECONF_MODE_INFO(inst) ((inst) + 0x000002E8), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_FORCE_SYNC_EN_INFO(inst) ((inst) + 0x000002E8), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#define REG_PREFSRC_RECONF_CTRL_ADDR(inst) ((inst) + 0x000002E9) +#define BF_CNCO_RESET_EN_INFO(inst) ((inst) + 0x000002E9), 0x00000101 +#define BF_TIMESTAMP_RESET_EN_INFO(inst) ((inst) + 0x000002E9), 0x00000102 +#define BF_RESYNC_EN_INFO(inst) ((inst) + 0x000002E9), 0x00000103 +#define BF_TZERO_COHERENCE_EN_INFO(inst) ((inst) + 0x000002E9), 0x00000104 +#define BF_FNCO_RESET_EN_INFO(inst) ((inst) + 0x000002E9), 0x00000105 + +#define REG_PREFSRC_RECONF_LCM0_ADDR(inst) ((inst) + 0x000002EA) +#define BF_PREFSRC_LCM_INFO(inst) ((inst) + 0x000002EA), 0x00000900 + +#define REG_PREFSRC_RECONF_LCM1_ADDR(inst) ((inst) + 0x000002EB) + +#define REG_PREFSRC_RECONF_ERROR_STATUS_ADDR(inst) ((inst) + 0x000002F1) +#ifdef USE_PRIVATE_BF +#define BF_RECONFIG_ERROR_STATUS_INFO(inst) ((inst) + 0x000002F1), 0x00000400 +#endif /* USE_PRIVATE_BF */ +#define BF_TIME_ERROR_STATUS_TXRX_PREFSRC_RECONF_INFO(inst) ((inst) + 0x000002F1), 0x00000105 + +#ifdef USE_PRIVATE_BF +#define REG_PREFSRC_SM_STATE_ADDR(inst) ((inst) + 0x000002F2) +#define BF_PREFSRC_SM_STATE_INFO(inst) ((inst) + 0x000002F2), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_PREFSRC_TRIG_INP_CNT_ADDR(inst) ((inst) + 0x000002F4) +#define BF_TRIG_INPUT_COUNT_INFO(inst) ((inst) + 0x000002F4), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_PREFSRC_SYNC_INP_CNT_ADDR(inst) ((inst) + 0x000002F5) +#define BF_SYNC_INPUT_COUNT_INFO(inst) ((inst) + 0x000002F5), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#define REG_PREFSRC_RECONF_RESET_STATUS_ADDR(inst) ((inst) + 0x000002F6) +#define BF_TIMESTAMP_RESET_DONE_INFO(inst) ((inst) + 0x000002F6), 0x00000100 +#define BF_CNCO_RESET_DONE_INFO(inst) ((inst) + 0x000002F6), 0x00000101 +#define BF_FNCO_RESET_DONE_INFO(inst) ((inst) + 0x000002F6), 0x00000102 + +#define REG_RECONFIG_FLUSH_COUNT_ADDR(inst) ((inst) + 0x000002F7) +#define BF_RECONFIG_FLUSH_COUNT_INFO(inst) ((inst) + 0x000002F7), 0x00000500 + +#define REG_RECONFIG_RAMP_WIDTH_TXRX_PREFSRC_RECONF_ADDR(inst) ((inst) + 0x000002F8) +#define BF_RECONFIG_RAMP_WIDTH_TXRX_PREFSRC_RECONF_INFO(inst) ((inst) + 0x000002F8), 0x00000500 + +#define REG_PREFSRC_RECONF_NEWCLK_DLY_ADDR(inst) ((inst) + 0x000002F9) +#define BF_NEWCLK_DLY_TXRX_PREFSRC_RECONF_INFO(inst) ((inst) + 0x000002F9), 0x00000500 + +#ifdef USE_PRIVATE_BF +#define REG_PREFSRC_FORCE_NEWCLK_ADDR(inst) ((inst) + 0x000002FA) +#define BF_FORCE_NEWCLK_TXRX_PREFSRC_RECONF_INFO(inst) ((inst) + 0x000002FA), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#endif /* __ADI_APOLLO_BF_TXRX_PREFSRC_RECONF_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_txrx_streamproc_config.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_txrx_streamproc_config.h new file mode 100644 index 00000000000000..c21bcfb93de8aa --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_txrx_streamproc_config.h @@ -0,0 +1,34 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:19 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_TXRX_STREAMPROC_CONFIG_H__ +#define __ADI_APOLLO_BF_TXRX_STREAMPROC_CONFIG_H__ + +/*============= D E F I N E S ==============*/ +#define RX_STREAMPROC_CONFIG_RX_DIGITAL0 0x60022000 +#define RX_STREAMPROC_CONFIG_RX_DIGITAL1 0x60822000 +#define TX_STREAMPROC_CONFIG_TX_TOP_TX_DIGITAL0 0x61021000 +#define TX_STREAMPROC_CONFIG_TX_TOP_TX_DIGITAL1 0x61821000 + +#define REG_STREAMPROC_1US_COUNT_ADDR(inst) ((inst) + 0x00000000) +#define BF_REFERENCE_CLOCK_CYCLES_TXRX_STREAMPROC_CONFIG_INFO(inst) ((inst) + 0x00000000), 0x00000800 + +#define REG_STREAMPROC_REG_RD_DELAY_ADDR(inst) ((inst) + 0x00000001) +#define BF_STREAMPROC_REG_RD_DELAY_INFO(inst) ((inst) + 0x00000001), 0x00000400 + +#define REG_STREAMPROC_EVENT_TRIG_MASK_ADDR(inst) ((inst) + 0x00000002) +#define BF_STREAMPROC_EVENT_TRIG_MASK_INFO(inst) ((inst) + 0x00000002), 0x00000800 + +#endif /* __ADI_APOLLO_BF_TXRX_STREAMPROC_CONFIG_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_txrx_trigger_ts.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_txrx_trigger_ts.h new file mode 100644 index 00000000000000..c3ac28cd12a94a --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_txrx_trigger_ts.h @@ -0,0 +1,149 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:19 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_TXRX_TRIGGER_TS_H__ +#define __ADI_APOLLO_BF_TXRX_TRIGGER_TS_H__ + +/*============= D E F I N E S ==============*/ +#define TXRX_TRIGGER_TS_RX_DIGITAL0 0x60021000 +#define TXRX_TRIGGER_TS_RX_DIGITAL1 0x60821000 +#define TXRX_TRIGGER_TS_TX_TOP_TX_DIGITAL0 0x61020000 +#define TXRX_TRIGGER_TS_TX_TOP_TX_DIGITAL1 0x61820000 + +#define REG_COUNT0_REG0_ADDR(inst) ((inst) + 0x00000000) +#define BF_COUNT0_REG0_INFO(inst) ((inst) + 0x00000000), 0x00000800 + +#define REG_COUNT0_REG1_ADDR(inst) ((inst) + 0x00000001) +#define BF_COUNT0_REG1_INFO(inst) ((inst) + 0x00000001), 0x00000800 + +#define REG_COUNT1_REG0_ADDR(inst) ((inst) + 0x00000002) +#define BF_COUNT1_REG0_INFO(inst) ((inst) + 0x00000002), 0x00000800 + +#define REG_COUNT1_REG1_ADDR(inst) ((inst) + 0x00000003) +#define BF_COUNT1_REG1_INFO(inst) ((inst) + 0x00000003), 0x00000800 + +#define REG_TS_RST_STATUS_ADDR(inst) ((inst) + 0x0000001E) +#define BF_RST_DONE_TXRX_TRIGGER_TS_INFO(inst) ((inst) + 0x0000001E), 0x00000100 +#define BF_RST_DONE_CLR_TXRX_TRIGGER_TS_INFO(inst) ((inst) + 0x0000001E), 0x00000101 + +#define REG_TS_RST_ADDR(inst) ((inst) + 0x0000001F) +#define BF_TS_RST_MODE_TXRX_TRIGGER_TS_INFO(inst) ((inst) + 0x0000001F), 0x00000100 +#define BF_SPI_TS_RST_TXRX_TRIGGER_TS_INFO(inst) ((inst) + 0x0000001F), 0x00000102 + +#define REG_TS_RD_EN_ADDR(inst) ((inst) + 0x00000020) +#define BF_TIMESTAMP_READ_EN_TXRX_TRIGGER_TS_INFO(inst) ((inst) + 0x00000020), 0x00000100 + +#define REG_TS_STATUS0_ADDR(inst) ((inst) + 0x00000021) +#define BF_TIMESTAMP_STATUS_TXRX_TRIGGER_TS_INFO(inst) ((inst) + 0x00000021), 0x00004000 + +#define REG_TS_STATUS1_ADDR(inst) ((inst) + 0x00000022) + +#define REG_TS_STATUS2_ADDR(inst) ((inst) + 0x00000023) + +#define REG_TS_STATUS3_ADDR(inst) ((inst) + 0x00000024) + +#define REG_TS_STATUS4_ADDR(inst) ((inst) + 0x00000025) + +#define REG_TS_STATUS5_ADDR(inst) ((inst) + 0x00000026) + +#define REG_TS_STATUS6_ADDR(inst) ((inst) + 0x00000027) + +#define REG_TS_STATUS7_ADDR(inst) ((inst) + 0x00000028) + +#define REG_TRIG_OFFSET0_ADDR(inst, n) ((inst) + 0x00000035 + 1 * (n)) +#define BF_TRIG_OFFSET0_INFO(inst, n) ((inst) + 0x00000035 + 1 * (n)), 0x00004000 + +#define REG_TRIG_OFFSET1_ADDR(inst, n) ((inst) + 0x00000055 + 1 * (n)) + +#define REG_TRIG_OFFSET2_ADDR(inst, n) ((inst) + 0x00000075 + 1 * (n)) + +#define REG_TRIG_OFFSET3_ADDR(inst, n) ((inst) + 0x00000095 + 1 * (n)) + +#define REG_TRIG_OFFSET4_ADDR(inst, n) ((inst) + 0x000000B5 + 1 * (n)) + +#define REG_TRIG_OFFSET5_ADDR(inst, n) ((inst) + 0x000000D5 + 1 * (n)) + +#define REG_TRIG_OFFSET6_ADDR(inst, n) ((inst) + 0x000000F5 + 1 * (n)) + +#define REG_TRIG_OFFSET7_ADDR(inst, n) ((inst) + 0x00000115 + 1 * (n)) + +#define REG_TRIG_PERIOD0_ADDR(inst, n) ((inst) + 0x00000135 + 1 * (n)) +#define BF_TRIG_PERIOD0_INFO(inst, n) ((inst) + 0x00000135 + 1 * (n)), 0x00004000 + +#define REG_TRIG_PERIOD1_ADDR(inst, n) ((inst) + 0x00000155 + 1 * (n)) + +#define REG_TRIG_PERIOD2_ADDR(inst, n) ((inst) + 0x00000175 + 1 * (n)) + +#define REG_TRIG_PERIOD3_ADDR(inst, n) ((inst) + 0x00000195 + 1 * (n)) + +#define REG_TRIG_PERIOD4_ADDR(inst, n) ((inst) + 0x000001B5 + 1 * (n)) + +#define REG_TRIG_PERIOD5_ADDR(inst, n) ((inst) + 0x000001D5 + 1 * (n)) + +#define REG_TRIG_PERIOD6_ADDR(inst, n) ((inst) + 0x000001F5 + 1 * (n)) + +#define REG_TRIG_PERIOD7_ADDR(inst, n) ((inst) + 0x00000215 + 1 * (n)) + +#define REG_TRIG_GPIO_PERIOD0_ADDR(inst, n) ((inst) + 0x00000235 + 1 * (n)) +#define BF_TRIG_GPIO_PERIOD0_INFO(inst, n) ((inst) + 0x00000235 + 1 * (n)), 0x00001000 + +#define REG_TRIG_GPIO_PERIOD1_ADDR(inst, n) ((inst) + 0x00000255 + 1 * (n)) + +#define REG_TRIG_SEL_MUX_BMEM_ADDR(inst, n) ((inst) + 0x00000275 + 1 * (n)) +#define BF_TRIG_SEL_MUX_BMEM_INFO(inst, n) ((inst) + 0x00000275 + 1 * (n)), 0x00000300 + +#define REG_SPI_TRIG_ADDR(inst) ((inst) + 0x00000277) +#define BF_SPI_TRIG_INFO(inst) ((inst) + 0x00000277), 0x00000100 + +#define REG_TM_SEL0_ADDR(inst) ((inst) + 0x00000278) +#define BF_TM_SEL0_INFO(inst) ((inst) + 0x00000278), 0x00000500 + +#define REG_TM_SEL1_ADDR(inst) ((inst) + 0x00000298) +#define BF_TM_SEL1_INFO(inst) ((inst) + 0x00000298), 0x00000500 + +#define REG_TRIG_SEL_MUX_CDRC0_ADDR(inst, n) ((inst) + 0x000002B8 + 1 * (n)) +#define BF_TRIG_SEL_MUX_CDRC0_INFO(inst, n) ((inst) + 0x000002B8 + 1 * (n)), 0x00000300 + +#define REG_TRIG_SEL_MUX_CDRC1_ADDR(inst, n) ((inst) + 0x000002BA + 1 * (n)) +#define BF_TRIG_SEL_MUX_CDRC1_INFO(inst, n) ((inst) + 0x000002BA + 1 * (n)), 0x00000300 + +#define REG_TRIG_SEL_MUX_FDRC0_ADDR(inst, n) ((inst) + 0x000002BC + 1 * (n)) +#define BF_TRIG_SEL_MUX_FDRC0_INFO(inst, n) ((inst) + 0x000002BC + 1 * (n)), 0x00000300 + +#define REG_TRIG_SEL_MUX_FDRC1_ADDR(inst, n) ((inst) + 0x000002C0 + 1 * (n)) +#define BF_TRIG_SEL_MUX_FDRC1_INFO(inst, n) ((inst) + 0x000002C0 + 1 * (n)), 0x00000300 + +#define REG_TRIG_SEL_MUX_LINEARX_ADDR(inst) ((inst) + 0x000002C4) +#define BF_TRIG_SEL_MUX_LINEARX_INFO(inst) ((inst) + 0x000002C4), 0x00000300 + +#define REG_TRIG_CTRL_TXRX_TRIGGER_TS_ADDR(inst, n) ((inst) + 0x000002C7 + 1 * (n)) +#define BF_MUTE_TRIG_INFO(inst, n) ((inst) + 0x000002C7 + 1 * (n)), 0x00000100 +#define BF_TRIG_EN_INFO(inst, n) ((inst) + 0x000002C7 + 1 * (n)), 0x00000101 +#define BF_TRIG_MASK_COUNT_INFO(inst, n) ((inst) + 0x000002C7 + 1 * (n)), 0x00000202 +#define BF_TRIG_SEL_INFO(inst, n) ((inst) + 0x000002C7 + 1 * (n)), 0x00000204 + +#define REG_TRIG_SEL_MUX_RECONFIG_ADDR(inst) ((inst) + 0x000002E7) +#define BF_TRIG_SEL_MUX_RECONFIG_INFO(inst) ((inst) + 0x000002E7), 0x00000300 + +#define REG_TRIG_SEL_MUX_PFILT0_ADDR(inst) ((inst) + 0x000002F7) +#define BF_TRIG_SEL_MUX_PFILT0_INFO(inst) ((inst) + 0x000002F7), 0x00000300 + +#define REG_TRIG_SEL_MUX_PFILT1_ADDR(inst) ((inst) + 0x000002F8) +#define BF_TRIG_SEL_MUX_PFILT1_INFO(inst) ((inst) + 0x000002F8), 0x00000300 + +#define REG_TRIG_SEL_MUX_CFIR_ADDR(inst, n) ((inst) + 0x000002F9 + 1 * (n)) +#define BF_TRIG_SEL_MUX_CFIR_INFO(inst, n) ((inst) + 0x000002F9 + 1 * (n)), 0x00000300 + +#endif /* __ADI_APOLLO_BF_TXRX_TRIGGER_TS_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_uart.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_uart.h new file mode 100644 index 00000000000000..3996f4f77e0fcc --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_uart.h @@ -0,0 +1,156 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:17 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_UART_H__ +#define __ADI_APOLLO_BF_UART_H__ + +/*============= D E F I N E S ==============*/ +#ifdef USE_PRIVATE_BF +#define REG_REVID_ADDR 0x46100000 +#define BF_REV_INFO 0x46100000, 0x00000400 +#define BF_MAJOR_INFO 0x46100000, 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#define REG_CTL_UART_ADDR 0x46100004 +#define BF_EN_UART_INFO 0x46100004, 0x00000100 +#define BF_LOOP_EN_INFO 0x46100004, 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_RESVD2_INFO 0x46100004, 0x00000102 +#endif /* USE_PRIVATE_BF */ +#ifdef USE_PRIVATE_BF +#define BF_RESVD3_INFO 0x46100004, 0x00000103 +#endif /* USE_PRIVATE_BF */ +#define BF_MOD_INFO 0x46100004, 0x00000204 +#ifdef USE_PRIVATE_BF +#define BF_RESVD6_INFO 0x46100004, 0x00000106 +#endif /* USE_PRIVATE_BF */ +#ifdef USE_PRIVATE_BF +#define BF_RESVD7_INFO 0x46100004, 0x00000107 +#endif /* USE_PRIVATE_BF */ +#define BF_WLS_INFO 0x46100004, 0x00000208 +#ifdef USE_PRIVATE_BF +#define BF_RESVD10_INFO 0x46100004, 0x0000010A +#endif /* USE_PRIVATE_BF */ +#ifdef USE_PRIVATE_BF +#define BF_RESVD11_INFO 0x46100004, 0x0000010B +#endif /* USE_PRIVATE_BF */ +#define BF_STB_INFO 0x46100004, 0x0000010C +#define BF_STBH_INFO 0x46100004, 0x0000010D +#define BF_PEN_INFO 0x46100004, 0x0000010E +#define BF_EPS_INFO 0x46100004, 0x0000010F +#define BF_STP_INFO 0x46100004, 0x00000110 +#define BF_FPE_INFO 0x46100004, 0x00000111 +#define BF_FFE_INFO 0x46100004, 0x00000112 +#define BF_SB_INFO 0x46100004, 0x00000113 +#ifdef USE_PRIVATE_BF +#define BF_RESVD20_INFO 0x46100004, 0x00000114 +#endif /* USE_PRIVATE_BF */ +#ifdef USE_PRIVATE_BF +#define BF_RESVD21_INFO 0x46100004, 0x00000115 +#endif /* USE_PRIVATE_BF */ +#define BF_FCPOL_INFO 0x46100004, 0x00000116 +#define BF_RPOLC_INFO 0x46100004, 0x00000117 +#define BF_TPOLC_INFO 0x46100004, 0x00000118 +#define BF_MRTS_INFO 0x46100004, 0x00000119 +#define BF_XOFF_INFO 0x46100004, 0x0000011A +#define BF_ARTS_INFO 0x46100004, 0x0000011B +#define BF_ACTS_INFO 0x46100004, 0x0000011C +#define BF_RFIT_INFO 0x46100004, 0x0000011D +#define BF_RFRT_INFO 0x46100004, 0x0000011E +#ifdef USE_PRIVATE_BF +#define BF_RESVD31_INFO 0x46100004, 0x0000011F +#endif /* USE_PRIVATE_BF */ + +#define REG_STAT_UART_ADDR 0x46100008 +#define BF_DR_INFO 0x46100008, 0x00000100 +#define BF_OE_INFO 0x46100008, 0x00000101 +#define BF_PE_INFO 0x46100008, 0x00000102 +#define BF_FE_INFO 0x46100008, 0x00000103 +#define BF_BI_INFO 0x46100008, 0x00000104 +#define BF_THRE_INFO 0x46100008, 0x00000105 +#define BF_TEMT_INFO 0x46100008, 0x00000107 +#define BF_TFI_INFO 0x46100008, 0x00000108 +#define BF_ASTKY_INFO 0x46100008, 0x00000109 +#define BF_ADDR_INFO 0x46100008, 0x0000010A +#define BF_RO_INFO 0x46100008, 0x0000010B +#define BF_SCTS_INFO 0x46100008, 0x0000010C +#define BF_CTS_INFO 0x46100008, 0x00000110 +#define BF_RFCS_INFO 0x46100008, 0x00000111 + +#define REG_SCR_ADDR 0x4610000C +#define BF_VALUE_SCR_INFO 0x4610000C, 0x00000800 + +#define REG_CLK_ADDR 0x46100010 +#define BF_DIV_INFO 0x46100010, 0x00001F00 +#define BF_EDBO_INFO 0x46100010, 0x0000011F + +#define REG_IMSK_ADDR 0x46100014 +#define BF_ERBFI_INFO 0x46100014, 0x00000100 +#define BF_ETBEI_INFO 0x46100014, 0x00000101 +#define BF_ELSI_INFO 0x46100014, 0x00000102 +#define BF_EDSSI_INFO 0x46100014, 0x00000103 +#define BF_EDTPTI_INFO 0x46100014, 0x00000104 +#define BF_ETFI_INFO 0x46100014, 0x00000105 +#define BF_ERFCI_INFO 0x46100014, 0x00000106 +#define BF_EAWI_INFO 0x46100014, 0x00000107 +#define BF_ERXS_INFO 0x46100014, 0x00000108 +#define BF_ETXS_INFO 0x46100014, 0x00000109 + +#define REG_IMSK_SET_ADDR 0x46100018 +#define BF_ERBFI_SET_INFO 0x46100018, 0x00000100 +#define BF_ETBEI_SET_INFO 0x46100018, 0x00000101 +#define BF_ELSI_SET_INFO 0x46100018, 0x00000102 +#define BF_EDSSI_SET_INFO 0x46100018, 0x00000103 +#define BF_EDTPTI_SET_INFO 0x46100018, 0x00000104 +#define BF_ETFI_SET_INFO 0x46100018, 0x00000105 +#define BF_ERFCI_SET_INFO 0x46100018, 0x00000106 +#define BF_EAWI_SET_INFO 0x46100018, 0x00000107 +#define BF_ERXS_SET_INFO 0x46100018, 0x00000108 +#define BF_ETXS_SET_INFO 0x46100018, 0x00000109 + +#define REG_IMSK_CLR_ADDR 0x4610001C +#define BF_ERBFI_CLR_INFO 0x4610001C, 0x00000100 +#define BF_ETBEI_CLR_INFO 0x4610001C, 0x00000101 +#define BF_ELSI_CLR_INFO 0x4610001C, 0x00000102 +#define BF_EDSSI_CLR_INFO 0x4610001C, 0x00000103 +#define BF_EDTPTI_CLR_INFO 0x4610001C, 0x00000104 +#define BF_ETFI_CLR_INFO 0x4610001C, 0x00000105 +#define BF_ERFCI_CLR_INFO 0x4610001C, 0x00000106 +#define BF_EAWI_CLR_INFO 0x4610001C, 0x00000107 +#define BF_ERXS_CLR_INFO 0x4610001C, 0x00000108 +#define BF_ETXS_CLR_INFO 0x4610001C, 0x00000109 + +#define REG_RBR_ADDR 0x46100020 +#define BF_VALUE_RBR_INFO 0x46100020, 0x00000800 + +#define REG_THR_ADDR 0x46100024 +#define BF_VALUE_THR_INFO 0x46100024, 0x00000800 + +#define REG_TAIP_ADDR 0x46100028 +#define BF_VALUE_TAIP_INFO 0x46100028, 0x00000800 + +#define REG_TSR_ADDR 0x4610002C +#define BF_VALUE_TSR_INFO 0x4610002C, 0x00000B00 + +#define REG_RSR_ADDR 0x46100030 +#define BF_VALUE_RSR_INFO 0x46100030, 0x00000A00 + +#define REG_TXCNT_ADDR 0x46100034 +#define BF_VALUE_TXCNT_INFO 0x46100034, 0x00001F00 + +#define REG_RXCNT_ADDR 0x46100038 +#define BF_VALUE_RXCNT_INFO 0x46100038, 0x00001F00 + +#endif /* __ADI_APOLLO_BF_UART_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_uartfifo.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_uartfifo.h new file mode 100644 index 00000000000000..49cabf7456bd89 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_uartfifo.h @@ -0,0 +1,35 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:17 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_UARTFIFO_H__ +#define __ADI_APOLLO_BF_UARTFIFO_H__ + +/*============= D E F I N E S ==============*/ +#define REG_UARTFIFO_DATA_ADDR 0x46000000 +#define BF_FIFODATA_INFO 0x46000000, 0x00000800 + +#define REG_UARTFIFO_STATUS_ADDR 0x46000004 +#define BF_FIFO_UNDERFLOW_INFO 0x46000004, 0x00000100 +#define BF_FIFO_HALF_FULL_INFO 0x46000004, 0x00000101 +#define BF_FIFO_ALMOST_FULL_INFO 0x46000004, 0x00000102 +#define BF_FIFO_FULL_INFO 0x46000004, 0x00000103 + +#define REG_UARTFIFO_INTR_EN_ADDR 0x46000008 +#define BF_FIFOINTREN_INFO 0x46000008, 0x00000400 + +#define REG_UARTFIFO_OCCUPANCY_STATUS_ADDR 0x4600000C +#define BF_FIFO_OCCUPANCY_STATUS_INFO 0x4600000C, 0x00000900 + +#endif /* __ADI_APOLLO_BF_UARTFIFO_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_venus_dcal_open.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_venus_dcal_open.h new file mode 100644 index 00000000000000..98c0e21336fc3b --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_venus_dcal_open.h @@ -0,0 +1,370 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:19 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_VENUS_DCAL_OPEN_H__ +#define __ADI_APOLLO_BF_VENUS_DCAL_OPEN_H__ + +/*============= D E F I N E S ==============*/ +#define VENUS_DCAL_REGMAP_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x60280000 +#define VENUS_DCAL_REGMAP_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x60480000 +#define VENUS_DCAL_REGMAP_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A80000 +#define VENUS_DCAL_REGMAP_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C80000 + +#define REG_DCAL_SCRATCH_BEGIN_ADDR(inst) ((inst) + 0x00000000) +#define BF_DCAL_SCRATCH_BEGIN_INFO(inst) ((inst) + 0x00000000), 0x00002000 + +#define REG_REG_0X0004_VENUS_DCAL__OPEN_ADDR(inst) ((inst) + 0x00000004) +#ifdef USE_PRIVATE_BF +#define BF_BF_65905AEB_INFO(inst) ((inst) + 0x00000004), 0x00000800 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_65905AEB_WEB_INFO(inst) ((inst) + 0x00000004), 0x00000108 +#ifdef USE_PRIVATE_BF +#define BF_BF_153627F9_INFO(inst) ((inst) + 0x00000004), 0x00000810 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_153627F9_WEB_INFO(inst) ((inst) + 0x00000004), 0x00000118 + +#define REG_REG_0X0008_VENUS_DCAL__OPEN_ADDR(inst) ((inst) + 0x00000008) +#ifdef USE_PRIVATE_BF +#define BF_BF_1D1898C8_INFO(inst) ((inst) + 0x00000008), 0x00000800 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_1D1898C8_WEB_INFO(inst) ((inst) + 0x00000008), 0x00000108 +#ifdef USE_PRIVATE_BF +#define BF_BF_D8B905EC_INFO(inst) ((inst) + 0x00000008), 0x00000810 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_D8B905EC_WEB_INFO(inst) ((inst) + 0x00000008), 0x00000118 + +#define REG_CUST_CONV_CTRL_ADDR(inst, n) ((inst) + 0x0000000C + 4 * (n)) +#define BF_TPAT_MODE_SEL_INFO(inst, n) ((inst) + 0x0000000C + 4 * (n)), 0x00000410 +#define BF_TPAT_INVERT_INFO(inst, n) ((inst) + 0x0000000C + 4 * (n)), 0x00000115 +#define BF_TPAT_RESTART_INFO(inst, n) ((inst) + 0x0000000C + 4 * (n)), 0x00000117 + +#define REG_CUST_USR_PAT_ADDR(inst, n) ((inst) + 0x0000002C + 4 * (n)) +#define BF_TPAT_USR_PAT_INFO(inst, n) ((inst) + 0x0000002C + 4 * (n)), 0x00001000 + +#define REG_REG_0X003C_VENUS_DCAL__OPEN_ADDR(inst, n) ((inst) + 0x0000003C + 4 * (n)) +#ifdef USE_PRIVATE_BF +#define BF_BF_F3500F69_INFO(inst, n) ((inst) + 0x0000003C + 4 * (n)), 0x00000210 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_F3500F69_WEB_INFO(inst, n) ((inst) + 0x0000003C + 4 * (n)), 0x00000112 +#ifdef USE_PRIVATE_BF +#define BF_BF_FE706944_INFO(inst, n) ((inst) + 0x0000003C + 4 * (n)), 0x00000116 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_FE706944_WEB_INFO(inst, n) ((inst) + 0x0000003C + 4 * (n)), 0x00000117 + +#define REG_REG_0X005C_VENUS_DCAL__OPEN_ADDR(inst) ((inst) + 0x0000005C) +#ifdef USE_PRIVATE_BF +#define BF_BF_C3ED7542_INFO(inst) ((inst) + 0x0000005C), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_C3ED7542_WEB_INFO(inst) ((inst) + 0x0000005C), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_6FF193DE_INFO(inst) ((inst) + 0x0000005C), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_6FF193DE_WEB_INFO(inst) ((inst) + 0x0000005C), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_952F97F2_INFO(inst) ((inst) + 0x0000005C), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_952F97F2_WEB_INFO(inst) ((inst) + 0x0000005C), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_A1FA7FB8_INFO(inst) ((inst) + 0x0000005C), 0x00000106 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_A1FA7FB8_WEB_INFO(inst) ((inst) + 0x0000005C), 0x00000107 +#ifdef USE_PRIVATE_BF +#define BF_BF_C8C93406_INFO(inst) ((inst) + 0x0000005C), 0x00000108 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_C8C93406_WEB_INFO(inst) ((inst) + 0x0000005C), 0x00000109 +#ifdef USE_PRIVATE_BF +#define BF_BF_2F45D307_INFO(inst) ((inst) + 0x0000005C), 0x0000010A +#endif /* USE_PRIVATE_BF */ +#define BF_BF_2F45D307_WEB_INFO(inst) ((inst) + 0x0000005C), 0x0000010B +#ifdef USE_PRIVATE_BF +#define BF_BF_066FBC7D_INFO(inst) ((inst) + 0x0000005C), 0x0000010C +#endif /* USE_PRIVATE_BF */ +#define BF_BF_066FBC7D_WEB_INFO(inst) ((inst) + 0x0000005C), 0x0000010D +#ifdef USE_PRIVATE_BF +#define BF_BF_F9C55881_INFO(inst) ((inst) + 0x0000005C), 0x0000010E +#endif /* USE_PRIVATE_BF */ +#define BF_BF_F9C55881_WEB_INFO(inst) ((inst) + 0x0000005C), 0x0000010F +#ifdef USE_PRIVATE_BF +#define BF_BF_AE88D120_INFO(inst) ((inst) + 0x0000005C), 0x0000011E +#endif /* USE_PRIVATE_BF */ +#define BF_BF_AE88D120_WEB_INFO(inst) ((inst) + 0x0000005C), 0x0000011F + +#define REG_REG_0X0060_VENUS_DCAL__OPEN_ADDR(inst) ((inst) + 0x00000060) +#ifdef USE_PRIVATE_BF +#define BF_BF_C0C064C6_INFO(inst) ((inst) + 0x00000060), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_C0C064C6_WEB_INFO(inst) ((inst) + 0x00000060), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_186A7DF7_INFO(inst) ((inst) + 0x00000060), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_186A7DF7_WEB_INFO(inst) ((inst) + 0x00000060), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_00791309_INFO(inst) ((inst) + 0x00000060), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_00791309_WEB_INFO(inst) ((inst) + 0x00000060), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_27A5E948_INFO(inst) ((inst) + 0x00000060), 0x00000106 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_27A5E948_WEB_INFO(inst) ((inst) + 0x00000060), 0x00000107 +#ifdef USE_PRIVATE_BF +#define BF_BF_D79258B3_INFO(inst) ((inst) + 0x00000060), 0x00000108 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_D79258B3_WEB_INFO(inst) ((inst) + 0x00000060), 0x00000109 +#ifdef USE_PRIVATE_BF +#define BF_BF_E8110471_INFO(inst) ((inst) + 0x00000060), 0x0000010A +#endif /* USE_PRIVATE_BF */ +#define BF_BF_E8110471_WEB_INFO(inst) ((inst) + 0x00000060), 0x0000010B +#ifdef USE_PRIVATE_BF +#define BF_BF_2C9ED7B9_INFO(inst) ((inst) + 0x00000060), 0x0000010C +#endif /* USE_PRIVATE_BF */ +#define BF_BF_2C9ED7B9_WEB_INFO(inst) ((inst) + 0x00000060), 0x0000010D +#ifdef USE_PRIVATE_BF +#define BF_BF_E61D6D80_INFO(inst) ((inst) + 0x00000060), 0x0000010E +#endif /* USE_PRIVATE_BF */ +#define BF_BF_E61D6D80_WEB_INFO(inst) ((inst) + 0x00000060), 0x0000010F +#ifdef USE_PRIVATE_BF +#define BF_BF_6D8FDD12_INFO(inst) ((inst) + 0x00000060), 0x0000011E +#endif /* USE_PRIVATE_BF */ +#define BF_BF_6D8FDD12_WEB_INFO(inst) ((inst) + 0x00000060), 0x0000011F + +#define REG_REG_0X0068_VENUS_DCAL__OPEN_ADDR(inst) ((inst) + 0x00000068) +#ifdef USE_PRIVATE_BF +#define BF_BF_799FD906_INFO(inst) ((inst) + 0x00000068), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_799FD906_WEB_INFO(inst) ((inst) + 0x00000068), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_AEC1FBD9_INFO(inst) ((inst) + 0x00000068), 0x00000804 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_AEC1FBD9_WEB_INFO(inst) ((inst) + 0x00000068), 0x0000010C +#ifdef USE_PRIVATE_BF +#define BF_BF_8AE41084_INFO(inst) ((inst) + 0x00000068), 0x0000080D +#endif /* USE_PRIVATE_BF */ +#define BF_BF_8AE41084_WEB_INFO(inst) ((inst) + 0x00000068), 0x00000115 +#ifdef USE_PRIVATE_BF +#define BF_BF_B9811EB3_INFO(inst) ((inst) + 0x00000068), 0x00000816 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_B9811EB3_WEB_INFO(inst) ((inst) + 0x00000068), 0x0000011E + +#define REG_REG_0X006C_VENUS_DCAL__OPEN_ADDR(inst) ((inst) + 0x0000006C) +#ifdef USE_PRIVATE_BF +#define BF_BF_B76A3C34_INFO(inst) ((inst) + 0x0000006C), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_B76A3C34_WEB_INFO(inst) ((inst) + 0x0000006C), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_133FECF5_INFO(inst) ((inst) + 0x0000006C), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_133FECF5_WEB_INFO(inst) ((inst) + 0x0000006C), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_4DC5BF86_INFO(inst) ((inst) + 0x0000006C), 0x00000804 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_4DC5BF86_WEB_INFO(inst) ((inst) + 0x0000006C), 0x0000010C +#ifdef USE_PRIVATE_BF +#define BF_BF_23F81451_INFO(inst) ((inst) + 0x0000006C), 0x0000080D +#endif /* USE_PRIVATE_BF */ +#define BF_BF_23F81451_WEB_INFO(inst) ((inst) + 0x0000006C), 0x00000115 +#ifdef USE_PRIVATE_BF +#define BF_BF_A403BA02_INFO(inst) ((inst) + 0x0000006C), 0x00000816 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_A403BA02_WEB_INFO(inst) ((inst) + 0x0000006C), 0x0000011E + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0070_VENUS_DCAL__OPEN_ADDR(inst) ((inst) + 0x00000070) +#define BF_BF_69891E46_INFO(inst) ((inst) + 0x00000070), 0x00000800 +#define BF_BF_CC510E0C_INFO(inst) ((inst) + 0x00000070), 0x00000808 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0074_VENUS_DCAL__OPEN_ADDR(inst) ((inst) + 0x00000074) +#define BF_BF_F5C7267F_INFO(inst) ((inst) + 0x00000074), 0x00000408 +#define BF_BF_42F4D459_INFO(inst) ((inst) + 0x00000074), 0x0000010D +#define BF_BF_0E519C6B_INFO(inst) ((inst) + 0x00000074), 0x0000010E +#define BF_BF_1D4E994A_INFO(inst) ((inst) + 0x00000074), 0x0000010F +#define BF_BF_D243CEBC_INFO(inst) ((inst) + 0x00000074), 0x00000418 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0078_VENUS_DCAL__OPEN_ADDR(inst) ((inst) + 0x00000078) +#define BF_BF_FDEC5891_INFO(inst) ((inst) + 0x00000078), 0x00000408 +#define BF_BF_9812E42B_INFO(inst) ((inst) + 0x00000078), 0x0000010D +#define BF_BF_00877BB4_INFO(inst) ((inst) + 0x00000078), 0x0000010E +#define BF_BF_D8AD3486_INFO(inst) ((inst) + 0x00000078), 0x0000010F +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X007C_VENUS_DCAL__OPEN_ADDR(inst) ((inst) + 0x0000007C) +#ifdef USE_PRIVATE_BF +#define BF_BF_B0EEA13E_INFO(inst) ((inst) + 0x0000007C), 0x00000300 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_B0EEA13E_WEB_INFO(inst) ((inst) + 0x0000007C), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_125BD416_INFO(inst) ((inst) + 0x0000007C), 0x00000304 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_125BD416_WEB_INFO(inst) ((inst) + 0x0000007C), 0x00000107 +#ifdef USE_PRIVATE_BF +#define BF_BF_FAFF7B1A_INFO(inst) ((inst) + 0x0000007C), 0x00000308 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_FAFF7B1A_WEB_INFO(inst) ((inst) + 0x0000007C), 0x0000010B +#ifdef USE_PRIVATE_BF +#define BF_BF_F3337F4F_INFO(inst) ((inst) + 0x0000007C), 0x0000030C +#endif /* USE_PRIVATE_BF */ +#define BF_BF_F3337F4F_WEB_INFO(inst) ((inst) + 0x0000007C), 0x0000010F +#ifdef USE_PRIVATE_BF +#define BF_BF_DA710C92_INFO(inst) ((inst) + 0x0000007C), 0x00000310 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_DA710C92_WEB_INFO(inst) ((inst) + 0x0000007C), 0x00000113 +#ifdef USE_PRIVATE_BF +#define BF_BF_D36F4FAA_INFO(inst) ((inst) + 0x0000007C), 0x00000314 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_D36F4FAA_WEB_INFO(inst) ((inst) + 0x0000007C), 0x00000117 +#ifdef USE_PRIVATE_BF +#define BF_BF_140A522B_INFO(inst) ((inst) + 0x0000007C), 0x00000318 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_140A522B_WEB_INFO(inst) ((inst) + 0x0000007C), 0x0000011B +#ifdef USE_PRIVATE_BF +#define BF_BF_A3EC1B9D_INFO(inst) ((inst) + 0x0000007C), 0x0000031C +#endif /* USE_PRIVATE_BF */ +#define BF_BF_A3EC1B9D_WEB_INFO(inst) ((inst) + 0x0000007C), 0x0000011F + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0080_VENUS_DCAL__OPEN_ADDR(inst) ((inst) + 0x00000080) +#define BF_BF_FBEE0B3C_INFO(inst) ((inst) + 0x00000080), 0x00000800 +#define BF_BF_E0086C88_INFO(inst) ((inst) + 0x00000080), 0x00000808 +#define BF_BF_B04EAF9B_INFO(inst) ((inst) + 0x00000080), 0x00000810 +#define BF_BF_C62F9DD2_INFO(inst) ((inst) + 0x00000080), 0x00000818 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0084_VENUS_DCAL__OPEN_ADDR(inst) ((inst) + 0x00000084) +#define BF_BF_7A860592_INFO(inst) ((inst) + 0x00000084), 0x00000800 +#define BF_BF_4EC5642D_INFO(inst) ((inst) + 0x00000084), 0x00000810 +#define BF_BF_BFAE9EFF_INFO(inst) ((inst) + 0x00000084), 0x00000818 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0088_VENUS_DCAL__OPEN_ADDR(inst) ((inst) + 0x00000088) +#ifdef USE_PRIVATE_BF +#define BF_BF_353CD723_INFO(inst) ((inst) + 0x00000088), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_353CD723_WEB_INFO(inst) ((inst) + 0x00000088), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_B214D2A2_INFO(inst) ((inst) + 0x00000088), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_B214D2A2_WEB_INFO(inst) ((inst) + 0x00000088), 0x00000103 + +#define REG_REG_0X008C_VENUS_DCAL__OPEN_ADDR(inst) ((inst) + 0x0000008C) +#ifdef USE_PRIVATE_BF +#define BF_BF_6877F9DB_INFO(inst) ((inst) + 0x0000008C), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_6877F9DB_WEB_INFO(inst) ((inst) + 0x0000008C), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_F13E8147_INFO(inst) ((inst) + 0x0000008C), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_F13E8147_WEB_INFO(inst) ((inst) + 0x0000008C), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_724868B0_INFO(inst) ((inst) + 0x0000008C), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_724868B0_WEB_INFO(inst) ((inst) + 0x0000008C), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_7005A3C2_INFO(inst) ((inst) + 0x0000008C), 0x00000106 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_7005A3C2_WEB_INFO(inst) ((inst) + 0x0000008C), 0x00000107 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0090_VENUS_DCAL__OPEN_ADDR(inst, n) ((inst) + 0x00000090 + 4 * (n)) +#define BF_BF_E4D1D250_INFO(inst, n) ((inst) + 0x00000090 + 4 * (n)), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00A0_VENUS_DCAL__OPEN_ADDR(inst, n) ((inst) + 0x000000A0 + 4 * (n)) +#define BF_BF_0ADCCC43_INFO(inst, n) ((inst) + 0x000000A0 + 4 * (n)), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00B0_VENUS_DCAL__OPEN_ADDR(inst, n) ((inst) + 0x000000B0 + 4 * (n)) +#define BF_BF_85081AEA_INFO(inst, n) ((inst) + 0x000000B0 + 4 * (n)), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00C0_VENUS_DCAL__OPEN_ADDR(inst, n) ((inst) + 0x000000C0 + 4 * (n)) +#define BF_BF_CAADE6EB_INFO(inst, n) ((inst) + 0x000000C0 + 4 * (n)), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00D0_VENUS_DCAL__OPEN_ADDR(inst, n) ((inst) + 0x000000D0 + 4 * (n)) +#define BF_BF_A9E91F37_INFO(inst, n) ((inst) + 0x000000D0 + 4 * (n)), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00E0_VENUS_DCAL__OPEN_ADDR(inst, n) ((inst) + 0x000000E0 + 4 * (n)) +#define BF_BF_902169B2_INFO(inst, n) ((inst) + 0x000000E0 + 4 * (n)), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00F0_VENUS_DCAL__OPEN_ADDR(inst, n) ((inst) + 0x000000F0 + 4 * (n)) +#define BF_BF_DC00DB1E_INFO(inst, n) ((inst) + 0x000000F0 + 4 * (n)), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0100_VENUS_DCAL__OPEN_ADDR(inst, n) ((inst) + 0x00000100 + 4 * (n)) +#define BF_BF_ECD9C66D_INFO(inst, n) ((inst) + 0x00000100 + 4 * (n)), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0110_ADDR(inst, n) ((inst) + 0x00000110 + 4 * (n)) +#define BF_BF_472B2E6F_INFO(inst, n) ((inst) + 0x00000110 + 4 * (n)), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0588_VENUS_DCAL__OPEN_ADDR(inst, n) ((inst) + 0x00000588 + 4 * (n)) +#define BF_BF_965DC444_INFO(inst, n) ((inst) + 0x00000588 + 4 * (n)), 0x00000300 +#define BF_BF_3C848DBF_INFO(inst, n) ((inst) + 0x00000588 + 4 * (n)), 0x00000103 +#define BF_BF_DDBE019C_INFO(inst, n) ((inst) + 0x00000588 + 4 * (n)), 0x00000304 +#define BF_BF_97D3C301_INFO(inst, n) ((inst) + 0x00000588 + 4 * (n)), 0x00000107 +#define BF_BF_44D750FF_INFO(inst, n) ((inst) + 0x00000588 + 4 * (n)), 0x00000308 +#define BF_BF_DF2C7815_INFO(inst, n) ((inst) + 0x00000588 + 4 * (n)), 0x0000010B +#define BF_BF_F0197C39_INFO(inst, n) ((inst) + 0x00000588 + 4 * (n)), 0x0000030C +#define BF_BF_6DDF402C_INFO(inst, n) ((inst) + 0x00000588 + 4 * (n)), 0x0000010F +#define BF_BF_A668FCF5_INFO(inst, n) ((inst) + 0x00000588 + 4 * (n)), 0x00000310 +#define BF_BF_49F2951C_INFO(inst, n) ((inst) + 0x00000588 + 4 * (n)), 0x00000113 +#define BF_BF_08731E8D_INFO(inst, n) ((inst) + 0x00000588 + 4 * (n)), 0x00000314 +#define BF_BF_002240B3_INFO(inst, n) ((inst) + 0x00000588 + 4 * (n)), 0x00000117 +#define BF_BF_30FD0FFB_INFO(inst, n) ((inst) + 0x00000588 + 4 * (n)), 0x00000318 +#define BF_BF_45F810DF_INFO(inst, n) ((inst) + 0x00000588 + 4 * (n)), 0x0000011B +#define BF_BF_340F1D9F_INFO(inst, n) ((inst) + 0x00000588 + 4 * (n)), 0x0000031C +#define BF_BF_2153268E_INFO(inst, n) ((inst) + 0x00000588 + 4 * (n)), 0x0000011F +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X07FC_ADDR(inst) ((inst) + 0x000007FC) +#define BF_BF_6155D3A1_INFO(inst) ((inst) + 0x000007FC), 0x00000300 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0800_ADDR(inst, n) ((inst) + 0x00000800 + 4 * (n)) +#define BF_BF_51CC7466_INFO(inst, n) ((inst) + 0x00000800 + 4 * (n)), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0814_ADDR(inst) ((inst) + 0x00000814) +#define BF_BF_B8021B85_INFO(inst) ((inst) + 0x00000814), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0818_ADDR(inst) ((inst) + 0x00000818) +#define BF_BF_69C7D5DE_INFO(inst) ((inst) + 0x00000818), 0x00000200 +#endif /* USE_PRIVATE_BF */ + +#define REG_DCAL_SCRATCH_END_ADDR(inst) ((inst) + 0x00001FFC) +#define BF_DCAL_SCRATCH_END_INFO(inst) ((inst) + 0x00001FFC), 0x00002000 + +#endif /* __ADI_APOLLO_BF_VENUS_DCAL_OPEN_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_venus_fcal_broadcast_open.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_venus_fcal_broadcast_open.h new file mode 100644 index 00000000000000..6aa93877b0c688 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_venus_fcal_broadcast_open.h @@ -0,0 +1,469 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:20 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_VENUS_FCAL_BROADCAST_OPEN_H__ +#define __ADI_APOLLO_BF_VENUS_FCAL_BROADCAST_OPEN_H__ + +/*============= D E F I N E S ==============*/ +#define VENUS_FCAL_BROADCAST_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x60286800 +#define VENUS_FCAL_BROADCAST_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x60486800 +#define VENUS_FCAL_BROADCAST_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A86800 +#define VENUS_FCAL_BROADCAST_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C86800 + +#define REG_FCAL_SCRATCH_BEGIN_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000000) +#define BF_FCAL_SCRATCH_BEGIN_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000000), 0x00002000 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0004_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000004) +#define BF_BF_70D31378_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000004), 0x00000500 +#define BF_BF_AE9D973E_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000004), 0x00000107 +#define BF_BF_E3872070_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000004), 0x00000408 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0008_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000008) +#define BF_BF_95E42D3D_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000008), 0x00001508 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0010_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000010) +#ifdef USE_PRIVATE_BF +#define BF_BF_9811EAE1_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000010), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_9811EAE1_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000010), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_27E0F6ED_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000010), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_27E0F6ED_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000010), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_1ADEB97E_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000010), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_1ADEB97E_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000010), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_0F77D67B_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000010), 0x00000106 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_0F77D67B_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000010), 0x00000107 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0014_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000014) +#define BF_BF_FD5AEA08_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000014), 0x00000800 +#define BF_BF_226FC1E7_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000014), 0x00000808 +#define BF_BF_78F9304A_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000014), 0x00000810 +#define BF_BF_364A15DC_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000014), 0x00000818 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0018_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000018) + +#define REG_REG_0X0038_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000038) + +#define REG_REG_0X0058_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000058) + +#define REG_REG_0X0088_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000088) + +#define REG_REG_0X00B8_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000000B8) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0118_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst, n) ((inst) + 0x00000118 + 4 * (n)) +#define BF_BF_4148A6B6_VENUS_FCAL__BROADCAST_OPEN_INFO(inst, n) ((inst) + 0x00000118 + 4 * (n)), 0x00001508 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0120_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst, n) ((inst) + 0x00000120 + 4 * (n)) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0128_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst, n) ((inst) + 0x00000128 + 4 * (n)) +#define BF_BF_398889CE_VENUS_FCAL__BROADCAST_OPEN_INFO(inst, n) ((inst) + 0x00000128 + 4 * (n)), 0x00001508 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0130_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst, n) ((inst) + 0x00000130 + 4 * (n)) + +#define REG_REG_0X0144_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000144) + +#define REG_REG_0X0184_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000184) +#ifdef USE_PRIVATE_BF +#define BF_BF_C5135C52_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_C5135C52_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_39861C20_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_39861C20_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_7CB8B9B0_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_7CB8B9B0_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_B0D333EE_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000106 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_B0D333EE_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000107 +#ifdef USE_PRIVATE_BF +#define BF_BF_D4A3F5FF_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000108 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_D4A3F5FF_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000109 +#ifdef USE_PRIVATE_BF +#define BF_BF_EC817610_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000184), 0x0000010C +#endif /* USE_PRIVATE_BF */ +#define BF_BF_EC817610_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000184), 0x0000010D +#ifdef USE_PRIVATE_BF +#define BF_BF_FB5A9FD4_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000184), 0x0000010E +#endif /* USE_PRIVATE_BF */ +#define BF_BF_FB5A9FD4_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000184), 0x0000010F +#ifdef USE_PRIVATE_BF +#define BF_BF_7FA84C3E_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000110 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_7FA84C3E_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000111 +#ifdef USE_PRIVATE_BF +#define BF_BF_08328F9C_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000112 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_08328F9C_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000113 +#ifdef USE_PRIVATE_BF +#define BF_BF_938A3AC2_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000114 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_938A3AC2_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000115 + +#define REG_REG_0X0188_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000188) +#ifdef USE_PRIVATE_BF +#define BF_BF_A217FBDF_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000188), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_A217FBDF_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000188), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_CE0AFDEA_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000188), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_CE0AFDEA_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000188), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_96EB681F_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000188), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_96EB681F_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000188), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_46B6F335_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000188), 0x00000106 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_46B6F335_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000188), 0x00000107 +#ifdef USE_PRIVATE_BF +#define BF_BF_87DFCBB4_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000188), 0x00000108 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_87DFCBB4_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000188), 0x00000109 +#ifdef USE_PRIVATE_BF +#define BF_BF_8E62455B_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000188), 0x0000010A +#endif /* USE_PRIVATE_BF */ +#define BF_BF_8E62455B_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000188), 0x0000010B + +#define REG_REG_0X018C_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000018C) +#ifdef USE_PRIVATE_BF +#define BF_BF_C99662C6_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000018C), 0x00000200 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_C99662C6_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000018C), 0x00000102 +#ifdef USE_PRIVATE_BF +#define BF_BF_69F16890_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000018C), 0x00000203 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_69F16890_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000018C), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_13059625_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000018C), 0x00000106 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_13059625_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000018C), 0x00000107 + +#define REG_REG_0X0190_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000190) +#ifdef USE_PRIVATE_BF +#define BF_BF_D38298F0_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000190), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_D38298F0_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000190), 0x00000101 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0194_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000194) +#define BF_BF_419A5D0E_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000194), 0x00000800 +#define BF_BF_100E7AD9_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000194), 0x00000808 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0198_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000198) +#define BF_BF_3473A519_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000198), 0x00000300 +#define BF_BF_4643E55A_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000198), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X019C_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000019C) +#ifdef USE_PRIVATE_BF +#define BF_BF_A63FA2F8_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000019C), 0x00000300 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_A63FA2F8_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000019C), 0x00000103 + +#define REG_REG_0X01A0_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000001A0) +#ifdef USE_PRIVATE_BF +#define BF_BF_D327F78A_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001A0), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_D327F78A_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001A0), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_C07E65B3_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001A0), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_C07E65B3_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001A0), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_3F783369_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001A0), 0x00000508 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_3F783369_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001A0), 0x0000010D + +#define REG_REG_0X01A4_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000001A4) +#ifdef USE_PRIVATE_BF +#define BF_BF_9658CC5F_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001A4), 0x00000300 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_9658CC5F_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001A4), 0x00000103 + +#define REG_REG_0X01A8_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000001A8) +#ifdef USE_PRIVATE_BF +#define BF_BF_DC2E8285_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001A8), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_DC2E8285_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001A8), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_268FD896_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001A8), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_268FD896_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001A8), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_6B6E8283_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001A8), 0x00000508 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_6B6E8283_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001A8), 0x0000010D + +#define REG_REG_0X01AC_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000001AC) +#ifdef USE_PRIVATE_BF +#define BF_BF_6BCE4EAB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001AC), 0x00000300 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_6BCE4EAB_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001AC), 0x00000103 + +#define REG_REG_0X01B0_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000001B0) +#ifdef USE_PRIVATE_BF +#define BF_BF_4F961F18_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001B0), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_4F961F18_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001B0), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_6680B429_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001B0), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_6680B429_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001B0), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_8E0203E1_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001B0), 0x00000508 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_8E0203E1_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001B0), 0x0000010D + +#define REG_REG_0X01B4_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000001B4) +#ifdef USE_PRIVATE_BF +#define BF_BF_612FDDCF_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001B4), 0x00000300 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_612FDDCF_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001B4), 0x00000103 + +#define REG_REG_0X01B8_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000001B8) +#ifdef USE_PRIVATE_BF +#define BF_BF_1DA2547C_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001B8), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_1DA2547C_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001B8), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_E430F192_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001B8), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_E430F192_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001B8), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_27B8F94C_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001B8), 0x00000508 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_27B8F94C_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001B8), 0x0000010D + +#define REG_REG_0X01C4_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000001C4) +#ifdef USE_PRIVATE_BF +#define BF_BF_F32C451E_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001C4), 0x00000300 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_F32C451E_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001C4), 0x00000103 + +#define REG_REG_0X01C8_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000001C8) +#ifdef USE_PRIVATE_BF +#define BF_BF_D6AABA16_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001C8), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_D6AABA16_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001C8), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_B00F6B93_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001C8), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_B00F6B93_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001C8), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_F1137625_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001C8), 0x00000508 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_F1137625_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001C8), 0x0000010D + +#define REG_REG_0X01CC_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000001CC) + +#define REG_REG_0X01D0_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000001D0) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X01D4_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000001D4) +#define BF_BF_34BC2DC7_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001D4), 0x00000100 +#define BF_BF_23CEB507_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001D4), 0x00000101 +#define BF_BF_9018E84F_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001D4), 0x00000102 +#define BF_BF_153FC4E0_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001D4), 0x00000103 +#define BF_BF_FD479377_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001D4), 0x00000104 +#define BF_BF_819337B6_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001D4), 0x00000105 +#define BF_BF_F4A1EDA4_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001D4), 0x00000107 +#define BF_BF_8528D94D_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001D4), 0x00000108 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X01D8_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000001D8) +#define BF_BF_C0BCC740_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001D8), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X01DC_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000001DC) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X01E0_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000001E0) +#define BF_BF_BBD1A61F_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001E0), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X01E4_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000001E4) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X01E8_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000001E8) +#define BF_BF_CFA1A74A_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001E8), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X01EC_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000001EC) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X01F0_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000001F0) +#define BF_BF_9CDC1423_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001F0), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X01F4_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000001F4) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X01F8_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000001F8) +#define BF_BF_8D590883_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001F8), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X01FC_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000001FC) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0200_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000200) +#define BF_BF_08B4682B_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000200), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0204_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000204) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0210_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000210) +#define BF_BF_3372594F_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000210), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0214_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000214) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0218_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000218) +#define BF_BF_80AA4B94_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000218), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X021C_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000021C) + +#define REG_REG_0X0220_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst, n) ((inst) + 0x00000220 + 4 * (n)) + +#define REG_REG_0X0244_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst, n) ((inst) + 0x00000244 + 4 * (n)) + +#define REG_REG_0X0268_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst, n) ((inst) + 0x00000268 + 4 * (n)) + +#define REG_REG_0X028C_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst, n) ((inst) + 0x0000028C + 4 * (n)) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X02B0_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000002B0) +#define BF_BF_83E000B8_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000002B0), 0x00001500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X02B4_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000002B4) +#define BF_BF_BA00FBEA_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000002B4), 0x00001500 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X02B8_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000002B8) + +#define REG_REG_0X02BC_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000002BC) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X02C0_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000002C0) +#define BF_BF_CEE2B5CB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000002C0), 0x00000100 +#define BF_BF_8A88506E_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000002C0), 0x00000102 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X02D0_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000002D0) +#define BF_BF_B10B6B72_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000002D0), 0x00000100 +#define BF_BF_1173FB44_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000002D0), 0x00000304 +#define BF_BF_6E44740D_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000002D0), 0x00000107 +#define BF_BF_21D0FDD2_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000002D0), 0x00000508 +#define BF_BF_0ADDB6F6_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000002D0), 0x00000510 +#define BF_BF_DB09B423_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000002D0), 0x00000818 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X02D4_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000002D4) + +#define REG_REG_0X0300_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst, n) ((inst) + 0x00000300 + 4 * (n)) + +#define REG_REG_0X0380_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000380) + +#define REG_REG_0X0384_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000384) + +#define REG_REG_0X0388_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000388) + +#define REG_REG_0X0390_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000390) + +#define REG_REG_0X0394_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst, n) ((inst) + 0x00000394 + 4 * (n)) + +#define REG_REG_0X03B8_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000003B8) +#ifdef USE_PRIVATE_BF +#define BF_BF_AB9D1A93_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000003B8), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_AB9D1A93_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000003B8), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_8B2DD03F_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000003B8), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_8B2DD03F_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000003B8), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_DF4C1F1C_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000003B8), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_DF4C1F1C_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000003B8), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_5A94F853_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000003B8), 0x00000106 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_5A94F853_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000003B8), 0x00000107 +#ifdef USE_PRIVATE_BF +#define BF_BF_DFDF6717_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000003B8), 0x00000108 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_DFDF6717_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000003B8), 0x00000109 +#ifdef USE_PRIVATE_BF +#define BF_BF_2A106DB9_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000003B8), 0x0000010C +#endif /* USE_PRIVATE_BF */ +#define BF_BF_2A106DB9_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000003B8), 0x0000010D +#ifdef USE_PRIVATE_BF +#define BF_BF_C8DCAF93_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000003B8), 0x0000090E +#endif /* USE_PRIVATE_BF */ +#define BF_BF_C8DCAF93_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000003B8), 0x00000117 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X03BC_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000003BC) +#define BF_BF_DDBBD610_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000003BC), 0x00000100 +#define BF_BF_5EC297FF_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000003BC), 0x00000101 +#define BF_BF_80C6E8BE_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000003BC), 0x00000102 +#define BF_BF_61262D7E_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000003BC), 0x00000103 +#define BF_BF_9A5D4E20_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000003BC), 0x00000104 +#define BF_BF_927D900E_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000003BC), 0x00000105 +#define BF_BF_DABE39F7_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000003BC), 0x00000106 +#define BF_BF_2B113489_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000003BC), 0x00000107 +#define BF_BF_D88809F8_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000003BC), 0x00000108 +#define BF_BF_66A4D584_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000003BC), 0x00000109 +#define BF_BF_55FD00E6_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000003BC), 0x0000010A +#define BF_BF_214F12BE_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000003BC), 0x0000010B +#define BF_BF_85CB74CC_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000003BC), 0x0000010C +#define BF_BF_BA3DEBCE_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000003BC), 0x0000010D +#define BF_BF_F541A0E2_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000003BC), 0x00000110 +#define BF_BF_AF396B85_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000003BC), 0x00000111 +#endif /* USE_PRIVATE_BF */ + +#define REG_FCAL_SCRATCH_END_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000007FC) +#define BF_FCAL_SCRATCH_END_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000007FC), 0x00002000 + +#endif /* __ADI_APOLLO_BF_VENUS_FCAL_BROADCAST_OPEN_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_venus_fcal_open.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_venus_fcal_open.h new file mode 100644 index 00000000000000..7e756b6ece4e7f --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_venus_fcal_open.h @@ -0,0 +1,581 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:20 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_VENUS_FCAL_OPEN_H__ +#define __ADI_APOLLO_BF_VENUS_FCAL_OPEN_H__ + +/*============= D E F I N E S ==============*/ +#define VENUS_FCAL_REGMAP0_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x60287000 +#define VENUS_FCAL_REGMAP1_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x60287800 +#define VENUS_FCAL_REGMAP2_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x60288000 +#define VENUS_FCAL_REGMAP3_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x60288800 +#define VENUS_FCAL_REGMAP4_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x60289000 +#define VENUS_FCAL_REGMAP5_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x60289800 +#define VENUS_FCAL_REGMAP6_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x6028A000 +#define VENUS_FCAL_REGMAP7_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x6028A800 +#define VENUS_FCAL_REGMAP0_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x60487000 +#define VENUS_FCAL_REGMAP1_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x60487800 +#define VENUS_FCAL_REGMAP2_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x60488000 +#define VENUS_FCAL_REGMAP3_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x60488800 +#define VENUS_FCAL_REGMAP4_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x60489000 +#define VENUS_FCAL_REGMAP5_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x60489800 +#define VENUS_FCAL_REGMAP6_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x6048A000 +#define VENUS_FCAL_REGMAP7_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x6048A800 +#define VENUS_FCAL_REGMAP0_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A87000 +#define VENUS_FCAL_REGMAP1_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A87800 +#define VENUS_FCAL_REGMAP2_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A88000 +#define VENUS_FCAL_REGMAP3_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A88800 +#define VENUS_FCAL_REGMAP4_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A89000 +#define VENUS_FCAL_REGMAP5_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A89800 +#define VENUS_FCAL_REGMAP6_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A8A000 +#define VENUS_FCAL_REGMAP7_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A8A800 +#define VENUS_FCAL_REGMAP0_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C87000 +#define VENUS_FCAL_REGMAP1_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C87800 +#define VENUS_FCAL_REGMAP2_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C88000 +#define VENUS_FCAL_REGMAP3_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C88800 +#define VENUS_FCAL_REGMAP4_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C89000 +#define VENUS_FCAL_REGMAP5_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C89800 +#define VENUS_FCAL_REGMAP6_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C8A000 +#define VENUS_FCAL_REGMAP7_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C8A800 + +#define REG_FCAL_SCRATCH_BEGIN_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x00000000) +#define BF_FCAL_SCRATCH_BEGIN_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000000), 0x00002000 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0004_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x00000004) +#define BF_BF_70D31378_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000004), 0x00000500 +#define BF_BF_AE9D973E_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000004), 0x00000107 +#define BF_BF_E3872070_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000004), 0x00000408 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0008_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x00000008) +#define BF_BF_95E42D3D_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000008), 0x00001508 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0010_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x00000010) +#ifdef USE_PRIVATE_BF +#define BF_BF_9811EAE1_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000010), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_9811EAE1_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000010), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_27E0F6ED_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000010), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_27E0F6ED_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000010), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_1ADEB97E_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000010), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_1ADEB97E_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000010), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_0F77D67B_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000010), 0x00000106 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_0F77D67B_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000010), 0x00000107 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0014_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x00000014) +#define BF_BF_FD5AEA08_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000014), 0x00000800 +#define BF_BF_226FC1E7_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000014), 0x00000808 +#define BF_BF_78F9304A_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000014), 0x00000810 +#define BF_BF_364A15DC_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000014), 0x00000818 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0018_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x00000018) +#define BF_BF_B263A595_INFO(inst) ((inst) + 0x00000018), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0038_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x00000038) +#define BF_BF_32EF326F_INFO(inst) ((inst) + 0x00000038), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0058_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x00000058) +#define BF_BF_4CA57706_INFO(inst) ((inst) + 0x00000058), 0x00004000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0088_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x00000088) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00B8_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000000B8) +#define BF_BF_2CF16EA5_INFO(inst) ((inst) + 0x000000B8), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0118_VENUS_FCAL__OPEN_ADDR(inst, n) ((inst) + 0x00000118 + 4 * (n)) +#define BF_BF_4148A6B6_VENUS_FCAL__OPEN_INFO(inst, n) ((inst) + 0x00000118 + 4 * (n)), 0x00001508 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0120_VENUS_FCAL__OPEN_ADDR(inst, n) ((inst) + 0x00000120 + 4 * (n)) +#define BF_BF_960D50F4_INFO(inst, n) ((inst) + 0x00000120 + 4 * (n)), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0128_VENUS_FCAL__OPEN_ADDR(inst, n) ((inst) + 0x00000128 + 4 * (n)) +#define BF_BF_398889CE_VENUS_FCAL__OPEN_INFO(inst, n) ((inst) + 0x00000128 + 4 * (n)), 0x00001508 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0130_VENUS_FCAL__OPEN_ADDR(inst, n) ((inst) + 0x00000130 + 4 * (n)) +#define BF_BF_67C0DF75_INFO(inst, n) ((inst) + 0x00000130 + 4 * (n)), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0144_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x00000144) +#define BF_BF_82A6F3DA_INFO(inst) ((inst) + 0x00000144), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0184_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x00000184) +#ifdef USE_PRIVATE_BF +#define BF_BF_C5135C52_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_C5135C52_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_39861C20_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_39861C20_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_7CB8B9B0_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_7CB8B9B0_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_B0D333EE_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000106 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_B0D333EE_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000107 +#ifdef USE_PRIVATE_BF +#define BF_BF_D4A3F5FF_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000108 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_D4A3F5FF_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000109 +#ifdef USE_PRIVATE_BF +#define BF_BF_EC817610_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000184), 0x0000010C +#endif /* USE_PRIVATE_BF */ +#define BF_BF_EC817610_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000184), 0x0000010D +#ifdef USE_PRIVATE_BF +#define BF_BF_FB5A9FD4_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000184), 0x0000010E +#endif /* USE_PRIVATE_BF */ +#define BF_BF_FB5A9FD4_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000184), 0x0000010F +#ifdef USE_PRIVATE_BF +#define BF_BF_7FA84C3E_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000110 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_7FA84C3E_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000111 +#ifdef USE_PRIVATE_BF +#define BF_BF_08328F9C_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000112 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_08328F9C_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000113 +#ifdef USE_PRIVATE_BF +#define BF_BF_938A3AC2_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000114 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_938A3AC2_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000115 + +#define REG_REG_0X0188_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x00000188) +#ifdef USE_PRIVATE_BF +#define BF_BF_A217FBDF_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000188), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_A217FBDF_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000188), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_CE0AFDEA_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000188), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_CE0AFDEA_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000188), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_96EB681F_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000188), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_96EB681F_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000188), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_46B6F335_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000188), 0x00000106 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_46B6F335_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000188), 0x00000107 +#ifdef USE_PRIVATE_BF +#define BF_BF_87DFCBB4_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000188), 0x00000108 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_87DFCBB4_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000188), 0x00000109 +#ifdef USE_PRIVATE_BF +#define BF_BF_8E62455B_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000188), 0x0000010A +#endif /* USE_PRIVATE_BF */ +#define BF_BF_8E62455B_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000188), 0x0000010B + +#define REG_REG_0X018C_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x0000018C) +#ifdef USE_PRIVATE_BF +#define BF_BF_C99662C6_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x0000018C), 0x00000200 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_C99662C6_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x0000018C), 0x00000102 +#ifdef USE_PRIVATE_BF +#define BF_BF_69F16890_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x0000018C), 0x00000203 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_69F16890_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x0000018C), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_13059625_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x0000018C), 0x00000106 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_13059625_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x0000018C), 0x00000107 + +#define REG_REG_0X0190_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x00000190) +#ifdef USE_PRIVATE_BF +#define BF_BF_D38298F0_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000190), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_D38298F0_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000190), 0x00000101 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0194_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x00000194) +#define BF_BF_419A5D0E_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000194), 0x00000800 +#define BF_BF_100E7AD9_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000194), 0x00000808 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0198_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x00000198) +#define BF_BF_3473A519_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000198), 0x00000300 +#define BF_BF_4643E55A_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000198), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X019C_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x0000019C) +#ifdef USE_PRIVATE_BF +#define BF_BF_A63FA2F8_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x0000019C), 0x00000300 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_A63FA2F8_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x0000019C), 0x00000103 + +#define REG_REG_0X01A0_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000001A0) +#ifdef USE_PRIVATE_BF +#define BF_BF_D327F78A_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001A0), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_D327F78A_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001A0), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_C07E65B3_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001A0), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_C07E65B3_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001A0), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_3F783369_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001A0), 0x00000508 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_3F783369_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001A0), 0x0000010D + +#define REG_REG_0X01A4_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000001A4) +#ifdef USE_PRIVATE_BF +#define BF_BF_9658CC5F_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001A4), 0x00000300 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_9658CC5F_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001A4), 0x00000103 + +#define REG_REG_0X01A8_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000001A8) +#ifdef USE_PRIVATE_BF +#define BF_BF_DC2E8285_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001A8), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_DC2E8285_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001A8), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_268FD896_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001A8), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_268FD896_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001A8), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_6B6E8283_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001A8), 0x00000508 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_6B6E8283_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001A8), 0x0000010D + +#define REG_REG_0X01AC_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000001AC) +#ifdef USE_PRIVATE_BF +#define BF_BF_6BCE4EAB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001AC), 0x00000300 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_6BCE4EAB_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001AC), 0x00000103 + +#define REG_REG_0X01B0_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000001B0) +#ifdef USE_PRIVATE_BF +#define BF_BF_4F961F18_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001B0), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_4F961F18_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001B0), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_6680B429_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001B0), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_6680B429_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001B0), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_8E0203E1_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001B0), 0x00000508 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_8E0203E1_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001B0), 0x0000010D + +#define REG_REG_0X01B4_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000001B4) +#ifdef USE_PRIVATE_BF +#define BF_BF_612FDDCF_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001B4), 0x00000300 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_612FDDCF_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001B4), 0x00000103 + +#define REG_REG_0X01B8_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000001B8) +#ifdef USE_PRIVATE_BF +#define BF_BF_1DA2547C_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001B8), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_1DA2547C_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001B8), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_E430F192_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001B8), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_E430F192_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001B8), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_27B8F94C_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001B8), 0x00000508 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_27B8F94C_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001B8), 0x0000010D + +#define REG_REG_0X01C4_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000001C4) +#ifdef USE_PRIVATE_BF +#define BF_BF_F32C451E_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001C4), 0x00000300 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_F32C451E_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001C4), 0x00000103 + +#define REG_REG_0X01C8_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000001C8) +#ifdef USE_PRIVATE_BF +#define BF_BF_D6AABA16_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001C8), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_D6AABA16_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001C8), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_B00F6B93_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001C8), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_B00F6B93_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001C8), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_F1137625_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001C8), 0x00000508 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_F1137625_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001C8), 0x0000010D + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X01CC_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000001CC) +#define BF_BF_F1E4CA3F_INFO(inst) ((inst) + 0x000001CC), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X01D0_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000001D0) +#define BF_BF_565759C1_INFO(inst) ((inst) + 0x000001D0), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X01D4_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000001D4) +#define BF_BF_34BC2DC7_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001D4), 0x00000100 +#define BF_BF_23CEB507_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001D4), 0x00000101 +#define BF_BF_9018E84F_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001D4), 0x00000102 +#define BF_BF_153FC4E0_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001D4), 0x00000103 +#define BF_BF_FD479377_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001D4), 0x00000104 +#define BF_BF_819337B6_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001D4), 0x00000105 +#define BF_BF_F4A1EDA4_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001D4), 0x00000107 +#define BF_BF_8528D94D_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001D4), 0x00000108 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X01D8_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000001D8) +#define BF_BF_C0BCC740_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001D8), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X01DC_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000001DC) +#define BF_BF_91C8B049_INFO(inst) ((inst) + 0x000001DC), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X01E0_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000001E0) +#define BF_BF_BBD1A61F_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001E0), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X01E4_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000001E4) +#define BF_BF_83226F2E_INFO(inst) ((inst) + 0x000001E4), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X01E8_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000001E8) +#define BF_BF_CFA1A74A_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001E8), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X01EC_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000001EC) +#define BF_BF_D1BBB026_INFO(inst) ((inst) + 0x000001EC), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X01F0_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000001F0) +#define BF_BF_9CDC1423_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001F0), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X01F4_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000001F4) +#define BF_BF_AA42E05E_INFO(inst) ((inst) + 0x000001F4), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X01F8_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000001F8) +#define BF_BF_8D590883_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001F8), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X01FC_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000001FC) +#define BF_BF_6451CED1_INFO(inst) ((inst) + 0x000001FC), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0200_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x00000200) +#define BF_BF_08B4682B_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000200), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0204_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x00000204) +#define BF_BF_D4420C10_INFO(inst) ((inst) + 0x00000204), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0210_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x00000210) +#define BF_BF_3372594F_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000210), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0214_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x00000214) +#define BF_BF_C3E7B4D2_INFO(inst) ((inst) + 0x00000214), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0218_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x00000218) +#define BF_BF_80AA4B94_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000218), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X021C_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x0000021C) +#define BF_BF_03298689_INFO(inst) ((inst) + 0x0000021C), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0220_VENUS_FCAL__OPEN_ADDR(inst, n) ((inst) + 0x00000220 + 4 * (n)) +#define BF_BF_D7A38C69_INFO(inst, n) ((inst) + 0x00000220 + 4 * (n)), 0x00004000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0244_VENUS_FCAL__OPEN_ADDR(inst, n) ((inst) + 0x00000244 + 4 * (n)) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0268_VENUS_FCAL__OPEN_ADDR(inst, n) ((inst) + 0x00000268 + 4 * (n)) +#define BF_BF_452FAE76_INFO(inst, n) ((inst) + 0x00000268 + 4 * (n)), 0x00004000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X028C_VENUS_FCAL__OPEN_ADDR(inst, n) ((inst) + 0x0000028C + 4 * (n)) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X02B0_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000002B0) +#define BF_BF_83E000B8_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000002B0), 0x00001500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X02B4_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000002B4) +#define BF_BF_BA00FBEA_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000002B4), 0x00001500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X02B8_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000002B8) +#define BF_BF_9E455DE0_INFO(inst) ((inst) + 0x000002B8), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X02BC_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000002BC) +#define BF_BF_AEF29814_INFO(inst) ((inst) + 0x000002BC), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X02C0_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000002C0) +#define BF_BF_CEE2B5CB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000002C0), 0x00000100 +#define BF_BF_8A88506E_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000002C0), 0x00000102 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X02D0_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000002D0) +#define BF_BF_B10B6B72_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000002D0), 0x00000100 +#define BF_BF_1173FB44_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000002D0), 0x00000304 +#define BF_BF_6E44740D_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000002D0), 0x00000107 +#define BF_BF_21D0FDD2_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000002D0), 0x00000508 +#define BF_BF_0ADDB6F6_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000002D0), 0x00000510 +#define BF_BF_DB09B423_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000002D0), 0x00000818 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X02D4_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000002D4) +#define BF_BF_38C26EA2_INFO(inst) ((inst) + 0x000002D4), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0300_VENUS_FCAL__OPEN_ADDR(inst, n) ((inst) + 0x00000300 + 4 * (n)) +#define BF_BF_3039D2A8_INFO(inst, n) ((inst) + 0x00000300 + 4 * (n)), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0380_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x00000380) +#define BF_BF_1055F572_INFO(inst) ((inst) + 0x00000380), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0384_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x00000384) +#define BF_BF_55714486_INFO(inst) ((inst) + 0x00000384), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0388_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x00000388) +#define BF_BF_15F3DBF8_INFO(inst) ((inst) + 0x00000388), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0390_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x00000390) +#define BF_BF_E92C8CBD_INFO(inst) ((inst) + 0x00000390), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0394_VENUS_FCAL__OPEN_ADDR(inst, n) ((inst) + 0x00000394 + 4 * (n)) +#define BF_BF_0692F660_INFO(inst, n) ((inst) + 0x00000394 + 4 * (n)), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X03B8_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000003B8) +#ifdef USE_PRIVATE_BF +#define BF_BF_AB9D1A93_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000003B8), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_AB9D1A93_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000003B8), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_8B2DD03F_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000003B8), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_8B2DD03F_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000003B8), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_DF4C1F1C_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000003B8), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_DF4C1F1C_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000003B8), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_5A94F853_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000003B8), 0x00000106 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_5A94F853_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000003B8), 0x00000107 +#ifdef USE_PRIVATE_BF +#define BF_BF_DFDF6717_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000003B8), 0x00000108 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_DFDF6717_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000003B8), 0x00000109 +#ifdef USE_PRIVATE_BF +#define BF_BF_2A106DB9_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000003B8), 0x0000010C +#endif /* USE_PRIVATE_BF */ +#define BF_BF_2A106DB9_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000003B8), 0x0000010D +#ifdef USE_PRIVATE_BF +#define BF_BF_C8DCAF93_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000003B8), 0x0000090E +#endif /* USE_PRIVATE_BF */ +#define BF_BF_C8DCAF93_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000003B8), 0x00000117 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X03BC_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000003BC) +#define BF_BF_DDBBD610_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000003BC), 0x00000100 +#define BF_BF_5EC297FF_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000003BC), 0x00000101 +#define BF_BF_80C6E8BE_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000003BC), 0x00000102 +#define BF_BF_61262D7E_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000003BC), 0x00000103 +#define BF_BF_9A5D4E20_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000003BC), 0x00000104 +#define BF_BF_927D900E_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000003BC), 0x00000105 +#define BF_BF_DABE39F7_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000003BC), 0x00000106 +#define BF_BF_2B113489_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000003BC), 0x00000107 +#define BF_BF_D88809F8_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000003BC), 0x00000108 +#define BF_BF_66A4D584_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000003BC), 0x00000109 +#define BF_BF_55FD00E6_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000003BC), 0x0000010A +#define BF_BF_214F12BE_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000003BC), 0x0000010B +#define BF_BF_85CB74CC_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000003BC), 0x0000010C +#define BF_BF_BA3DEBCE_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000003BC), 0x0000010D +#define BF_BF_F541A0E2_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000003BC), 0x00000110 +#define BF_BF_AF396B85_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000003BC), 0x00000111 +#endif /* USE_PRIVATE_BF */ + +#define REG_FCAL_SCRATCH_END_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000007FC) +#define BF_FCAL_SCRATCH_END_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000007FC), 0x00002000 + +#endif /* __ADI_APOLLO_BF_VENUS_FCAL_OPEN_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_venus_ical_broadcast_open.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_venus_ical_broadcast_open.h new file mode 100644 index 00000000000000..6304d5fe2accb0 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_venus_ical_broadcast_open.h @@ -0,0 +1,78 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:20 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_VENUS_ICAL_BROADCAST_OPEN_H__ +#define __ADI_APOLLO_BF_VENUS_ICAL_BROADCAST_OPEN_H__ + +/*============= D E F I N E S ==============*/ +#define VENUS_ICAL_BROADCAST_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x6028B000 +#define VENUS_ICAL_BROADCAST_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x6048B000 +#define VENUS_ICAL_BROADCAST_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A8B000 +#define VENUS_ICAL_BROADCAST_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C8B000 + +#define REG_ICAL_SCRATCH_BEGIN_VENUS_ICAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000000) +#define BF_ICAL_SCRATCH_BEGIN_VENUS_ICAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000000), 0x00002000 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0004_VENUS_ICAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000004) +#define BF_BF_BD620D06_VENUS_ICAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000004), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0008_VENUS_ICAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000008) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X000C_VENUS_ICAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000000C) +#define BF_BF_7CB52A3F_VENUS_ICAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000000C), 0x00000300 +#define BF_BF_D296E6CA_VENUS_ICAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000000C), 0x00000304 +#define BF_BF_4C2C6025_VENUS_ICAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000000C), 0x00000308 +#define BF_BF_3880FAE8_VENUS_ICAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000000C), 0x0000030C +#define BF_BF_A0453F15_VENUS_ICAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000000C), 0x00000310 +#define BF_BF_69400B27_VENUS_ICAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000000C), 0x00000314 +#define BF_BF_8C1CBE2A_VENUS_ICAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000000C), 0x00000318 +#define BF_BF_24FE7242_VENUS_ICAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000000C), 0x0000031C +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0010_VENUS_ICAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000010) +#define BF_BF_B5BD3244_VENUS_ICAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000010), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0014_VENUS_ICAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000014) +#define BF_BF_7636BB0C_VENUS_ICAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000014), 0x00001200 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0018_VENUS_ICAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000018) + +#define REG_REG_0X001C_VENUS_ICAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000001C) + +#define REG_REG_0X0020_VENUS_ICAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000020) + +#define REG_REG_0X0024_VENUS_ICAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000024) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0028_VENUS_ICAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000028) +#define BF_BF_1EC9BB81_VENUS_ICAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000028), 0x00001500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X002C_VENUS_ICAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000002C) +#define BF_BF_2F42F9D5_VENUS_ICAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000002C), 0x00001500 +#endif /* USE_PRIVATE_BF */ + +#define REG_ICAL_SCRATCH_END_VENUS_ICAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000007FC) +#define BF_ICAL_SCRATCH_END_VENUS_ICAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000007FC), 0x00002000 + +#endif /* __ADI_APOLLO_BF_VENUS_ICAL_BROADCAST_OPEN_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_venus_ical_open.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_venus_ical_open.h new file mode 100644 index 00000000000000..5d4985f73b75e7 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_venus_ical_open.h @@ -0,0 +1,124 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:20 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_VENUS_ICAL_OPEN_H__ +#define __ADI_APOLLO_BF_VENUS_ICAL_OPEN_H__ + +/*============= D E F I N E S ==============*/ +#define VENUS_ICAL_REGMAP0_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x6028B800 +#define VENUS_ICAL_REGMAP1_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x6028C000 +#define VENUS_ICAL_REGMAP2_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x6028C800 +#define VENUS_ICAL_REGMAP3_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x6028D000 +#define VENUS_ICAL_REGMAP4_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x6028D800 +#define VENUS_ICAL_REGMAP5_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x6028E000 +#define VENUS_ICAL_REGMAP6_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x6028E800 +#define VENUS_ICAL_REGMAP7_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x6028F000 +#define VENUS_ICAL_REGMAP0_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x6048B800 +#define VENUS_ICAL_REGMAP1_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x6048C000 +#define VENUS_ICAL_REGMAP2_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x6048C800 +#define VENUS_ICAL_REGMAP3_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x6048D000 +#define VENUS_ICAL_REGMAP4_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x6048D800 +#define VENUS_ICAL_REGMAP5_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x6048E000 +#define VENUS_ICAL_REGMAP6_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x6048E800 +#define VENUS_ICAL_REGMAP7_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x6048F000 +#define VENUS_ICAL_REGMAP0_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A8B800 +#define VENUS_ICAL_REGMAP1_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A8C000 +#define VENUS_ICAL_REGMAP2_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A8C800 +#define VENUS_ICAL_REGMAP3_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A8D000 +#define VENUS_ICAL_REGMAP4_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A8D800 +#define VENUS_ICAL_REGMAP5_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A8E000 +#define VENUS_ICAL_REGMAP6_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A8E800 +#define VENUS_ICAL_REGMAP7_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A8F000 +#define VENUS_ICAL_REGMAP0_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C8B800 +#define VENUS_ICAL_REGMAP1_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C8C000 +#define VENUS_ICAL_REGMAP2_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C8C800 +#define VENUS_ICAL_REGMAP3_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C8D000 +#define VENUS_ICAL_REGMAP4_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C8D800 +#define VENUS_ICAL_REGMAP5_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C8E000 +#define VENUS_ICAL_REGMAP6_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C8E800 +#define VENUS_ICAL_REGMAP7_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C8F000 + +#define REG_ICAL_SCRATCH_BEGIN_VENUS_ICAL__OPEN_ADDR(inst) ((inst) + 0x00000000) +#define BF_ICAL_SCRATCH_BEGIN_VENUS_ICAL__OPEN_INFO(inst) ((inst) + 0x00000000), 0x00002000 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0004_VENUS_ICAL__OPEN_ADDR(inst) ((inst) + 0x00000004) +#define BF_BF_BD620D06_VENUS_ICAL__OPEN_INFO(inst) ((inst) + 0x00000004), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0008_VENUS_ICAL__OPEN_ADDR(inst) ((inst) + 0x00000008) +#define BF_BF_A527D04B_INFO(inst) ((inst) + 0x00000008), 0x00000100 +#define BF_BF_3DAB5E7F_INFO(inst) ((inst) + 0x00000008), 0x00000101 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X000C_VENUS_ICAL__OPEN_ADDR(inst) ((inst) + 0x0000000C) +#define BF_BF_7CB52A3F_VENUS_ICAL__OPEN_INFO(inst) ((inst) + 0x0000000C), 0x00000300 +#define BF_BF_D296E6CA_VENUS_ICAL__OPEN_INFO(inst) ((inst) + 0x0000000C), 0x00000304 +#define BF_BF_4C2C6025_VENUS_ICAL__OPEN_INFO(inst) ((inst) + 0x0000000C), 0x00000308 +#define BF_BF_3880FAE8_VENUS_ICAL__OPEN_INFO(inst) ((inst) + 0x0000000C), 0x0000030C +#define BF_BF_A0453F15_VENUS_ICAL__OPEN_INFO(inst) ((inst) + 0x0000000C), 0x00000310 +#define BF_BF_69400B27_VENUS_ICAL__OPEN_INFO(inst) ((inst) + 0x0000000C), 0x00000314 +#define BF_BF_8C1CBE2A_VENUS_ICAL__OPEN_INFO(inst) ((inst) + 0x0000000C), 0x00000318 +#define BF_BF_24FE7242_VENUS_ICAL__OPEN_INFO(inst) ((inst) + 0x0000000C), 0x0000031C +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0010_VENUS_ICAL__OPEN_ADDR(inst) ((inst) + 0x00000010) +#define BF_BF_B5BD3244_VENUS_ICAL__OPEN_INFO(inst) ((inst) + 0x00000010), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0014_VENUS_ICAL__OPEN_ADDR(inst) ((inst) + 0x00000014) +#define BF_BF_7636BB0C_VENUS_ICAL__OPEN_INFO(inst) ((inst) + 0x00000014), 0x00001200 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0018_VENUS_ICAL__OPEN_ADDR(inst) ((inst) + 0x00000018) +#define BF_BF_07A65CC1_INFO(inst) ((inst) + 0x00000018), 0x00001200 +#define BF_BF_602BD5EC_INFO(inst) ((inst) + 0x00000018), 0x0000011F +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X001C_VENUS_ICAL__OPEN_ADDR(inst) ((inst) + 0x0000001C) +#define BF_BF_373F82E3_INFO(inst) ((inst) + 0x0000001C), 0x00001200 +#define BF_BF_BCE07784_INFO(inst) ((inst) + 0x0000001C), 0x0000011F +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0020_VENUS_ICAL__OPEN_ADDR(inst) ((inst) + 0x00000020) +#define BF_BF_0F0069B9_INFO(inst) ((inst) + 0x00000020), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0024_VENUS_ICAL__OPEN_ADDR(inst) ((inst) + 0x00000024) +#define BF_BF_ABC3056F_INFO(inst) ((inst) + 0x00000024), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0028_VENUS_ICAL__OPEN_ADDR(inst) ((inst) + 0x00000028) +#define BF_BF_1EC9BB81_VENUS_ICAL__OPEN_INFO(inst) ((inst) + 0x00000028), 0x00001500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X002C_VENUS_ICAL__OPEN_ADDR(inst) ((inst) + 0x0000002C) +#define BF_BF_2F42F9D5_VENUS_ICAL__OPEN_INFO(inst) ((inst) + 0x0000002C), 0x00001500 +#endif /* USE_PRIVATE_BF */ + +#define REG_ICAL_SCRATCH_END_VENUS_ICAL__OPEN_ADDR(inst) ((inst) + 0x000007FC) +#define BF_ICAL_SCRATCH_END_VENUS_ICAL__OPEN_INFO(inst) ((inst) + 0x000007FC), 0x00002000 + +#endif /* __ADI_APOLLO_BF_VENUS_ICAL_OPEN_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_venus_scal_broadcast_open.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_venus_scal_broadcast_open.h new file mode 100644 index 00000000000000..3cef3bb0ae04d7 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_venus_scal_broadcast_open.h @@ -0,0 +1,899 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:20 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_VENUS_SCAL_BROADCAST_OPEN_H__ +#define __ADI_APOLLO_BF_VENUS_SCAL_BROADCAST_OPEN_H__ + +/*============= D E F I N E S ==============*/ +#define VENUS_SCAL_BROADCAST_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x60282000 +#define VENUS_SCAL_BROADCAST_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x60482000 +#define VENUS_SCAL_BROADCAST_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A82000 +#define VENUS_SCAL_BROADCAST_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C82000 + +#define REG_SCAL_SCRATCH_BEGIN_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000000) +#define BF_SCAL_SCRATCH_BEGIN_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000000), 0x00002000 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0004_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst, n) ((inst) + 0x00000004 + 4 * (n)) +#define BF_BF_507BA89F_VENUS_SCAL__BROADCAST_OPEN_INFO(inst, n) ((inst) + 0x00000004 + 4 * (n)), 0x00001108 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X001C_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst, n) ((inst) + 0x0000001C + 4 * (n)) +#define BF_BF_A4C77B32_VENUS_SCAL__BROADCAST_OPEN_INFO(inst, n) ((inst) + 0x0000001C + 4 * (n)), 0x00001308 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0034_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst, n) ((inst) + 0x00000034 + 4 * (n)) + +#define REG_REG_0X004C_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst, n) ((inst) + 0x0000004C + 4 * (n)) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0084_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst, n) ((inst) + 0x00000084 + 4 * (n)) +#define BF_BF_28B73B48_VENUS_SCAL__BROADCAST_OPEN_INFO(inst, n) ((inst) + 0x00000084 + 4 * (n)), 0x00001508 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0134_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst, n) ((inst) + 0x00000134 + 4 * (n)) + +#define REG_REG_0X0158_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst, n) ((inst) + 0x00000158 + 4 * (n)) + +#define REG_REG_0X017C_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst, n) ((inst) + 0x0000017C + 4 * (n)) + +#define REG_REG_0X01A0_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst, n) ((inst) + 0x000001A0 + 4 * (n)) + +#define REG_REG_0X01E4_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst, n) ((inst) + 0x000001E4 + 4 * (n)) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0204_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst, n) ((inst) + 0x00000204 + 4 * (n)) +#define BF_BF_92C0547B_VENUS_SCAL__BROADCAST_OPEN_INFO(inst, n) ((inst) + 0x00000204 + 4 * (n)), 0x00001508 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X020C_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000020C) + +#define REG_REG_0X022C_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000022C) + +#define REG_REG_0X024C_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000024C) + +#define REG_REG_0X0400_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000400) + +#define REG_REG_0X0404_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000404) + +#define REG_REG_0X0408_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000408) + +#define REG_REG_0X040C_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000040C) +#ifdef USE_PRIVATE_BF +#define BF_BF_4D25EF5C_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000040C), 0x00000200 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_4D25EF5C_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000040C), 0x00000102 +#ifdef USE_PRIVATE_BF +#define BF_BF_48F55CE0_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000040C), 0x00000203 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_48F55CE0_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000040C), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_38DA1C3D_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000040C), 0x00000206 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_38DA1C3D_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000040C), 0x00000108 + +#define REG_REG_0X0410_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000410) + +#define REG_REG_0X0414_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000414) + +#define REG_REG_0X0418_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000418) + +#define REG_REG_0X041C_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000041C) + +#define REG_REG_0X0420_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000420) + +#define REG_REG_0X0424_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000424) + +#define REG_REG_0X0428_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000428) +#ifdef USE_PRIVATE_BF +#define BF_BF_BAD86450_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000428), 0x00000600 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_BAD86450_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000428), 0x00000106 +#ifdef USE_PRIVATE_BF +#define BF_BF_0D9CF522_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000428), 0x00000607 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_0D9CF522_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000428), 0x0000010D + +#define REG_REG_0X042C_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000042C) + +#define REG_REG_0X0430_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000430) + +#define REG_REG_0X0434_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000434) + +#define REG_REG_0X0438_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000438) + +#define REG_REG_0X043C_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000043C) + +#define REG_REG_0X0440_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000440) + +#define REG_REG_0X0444_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000444) + +#define REG_REG_0X0448_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000448) + +#define REG_REG_0X044C_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000044C) + +#define REG_REG_0X0450_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000450) + +#define REG_REG_0X0454_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000454) + +#define REG_REG_0X0458_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000458) + +#define REG_REG_0X045C_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000045C) + +#define REG_REG_0X0460_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000460) + +#define REG_REG_0X0464_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000464) + +#define REG_REG_0X0468_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000468) + +#define REG_REG_0X046C_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000046C) +#ifdef USE_PRIVATE_BF +#define BF_BF_04FC627D_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000046C), 0x00000800 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_04FC627D_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000046C), 0x00000108 + +#define REG_REG_0X0470_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000470) +#ifdef USE_PRIVATE_BF +#define BF_BF_89FA30CF_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000470), 0x00000400 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_89FA30CF_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000470), 0x00000104 +#ifdef USE_PRIVATE_BF +#define BF_BF_83063494_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000470), 0x00000405 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_83063494_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000470), 0x00000109 +#ifdef USE_PRIVATE_BF +#define BF_BF_6073B2AA_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000470), 0x0000040A +#endif /* USE_PRIVATE_BF */ +#define BF_BF_6073B2AA_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000470), 0x0000010E +#ifdef USE_PRIVATE_BF +#define BF_BF_56C106E1_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000470), 0x0000040F +#endif /* USE_PRIVATE_BF */ +#define BF_BF_56C106E1_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000470), 0x00000113 +#ifdef USE_PRIVATE_BF +#define BF_BF_34407588_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000470), 0x00000414 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_34407588_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000470), 0x00000118 + +#define REG_REG_0X0474_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000474) +#ifdef USE_PRIVATE_BF +#define BF_BF_DAD827A3_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000474), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_DAD827A3_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000474), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_7BA7C73B_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000474), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_7BA7C73B_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000474), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_DBA82E9D_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000474), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_DBA82E9D_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000474), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_3098C59C_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000474), 0x00000106 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_3098C59C_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000474), 0x00000107 + +#define REG_REG_0X0478_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000478) +#ifdef USE_PRIVATE_BF +#define BF_BF_45F7874C_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000478), 0x00000400 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_45F7874C_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000478), 0x00000104 +#ifdef USE_PRIVATE_BF +#define BF_BF_32F08E3A_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000478), 0x00000405 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_32F08E3A_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000478), 0x00000109 +#ifdef USE_PRIVATE_BF +#define BF_BF_D797E7BF_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000478), 0x0000040A +#endif /* USE_PRIVATE_BF */ +#define BF_BF_D797E7BF_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000478), 0x0000010E + +#define REG_REG_0X047C_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000047C) +#ifdef USE_PRIVATE_BF +#define BF_BF_A432F804_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000047C), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_A432F804_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000047C), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_59DA3AA0_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000047C), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_59DA3AA0_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000047C), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_48B52FAE_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000047C), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_48B52FAE_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000047C), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_CEDBB6EE_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000047C), 0x00000106 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_CEDBB6EE_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000047C), 0x00000107 + +#define REG_REG_0X0480_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000480) +#ifdef USE_PRIVATE_BF +#define BF_BF_821BF1CA_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000480), 0x00000300 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_821BF1CA_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000480), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_27DD70A9_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000480), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_27DD70A9_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000480), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_AD4714AD_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000480), 0x00000206 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_AD4714AD_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000480), 0x00000108 + +#define REG_REG_0X0484_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000484) +#ifdef USE_PRIVATE_BF +#define BF_BF_5CA2D2B4_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000484), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_5CA2D2B4_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000484), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_CC0429E4_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000484), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_CC0429E4_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000484), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_67599BD7_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000484), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_67599BD7_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000484), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_B9D7C00F_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000484), 0x00000106 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_B9D7C00F_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000484), 0x00000107 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0488_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000488) +#define BF_BF_EC9E82E8_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000488), 0x00000800 +#define BF_BF_0818209E_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000488), 0x00000808 +#define BF_BF_B416D230_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000488), 0x00000810 +#define BF_BF_EACE3FE4_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000488), 0x00000818 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X048C_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000048C) +#ifdef USE_PRIVATE_BF +#define BF_BF_ED7193DA_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_ED7193DA_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_9F9E1975_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_9F9E1975_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_25552B6D_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_25552B6D_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_5E7E18C6_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000106 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_5E7E18C6_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000107 +#ifdef USE_PRIVATE_BF +#define BF_BF_F4D789F1_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000108 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_F4D789F1_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000109 +#ifdef USE_PRIVATE_BF +#define BF_BF_E1F9065C_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000048C), 0x0000010A +#endif /* USE_PRIVATE_BF */ +#define BF_BF_E1F9065C_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000048C), 0x0000010B +#ifdef USE_PRIVATE_BF +#define BF_BF_5B7943BD_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000048C), 0x0000010C +#endif /* USE_PRIVATE_BF */ +#define BF_BF_5B7943BD_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000048C), 0x0000010D +#ifdef USE_PRIVATE_BF +#define BF_BF_684D9C7E_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000048C), 0x0000010E +#endif /* USE_PRIVATE_BF */ +#define BF_BF_684D9C7E_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000048C), 0x0000010F +#ifdef USE_PRIVATE_BF +#define BF_BF_B483B9CE_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000112 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_B483B9CE_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000113 +#ifdef USE_PRIVATE_BF +#define BF_BF_C967ACFB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000114 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_C967ACFB_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000115 +#ifdef USE_PRIVATE_BF +#define BF_BF_9580F3CE_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000116 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_9580F3CE_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000117 +#ifdef USE_PRIVATE_BF +#define BF_BF_5B4B40B3_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000118 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_5B4B40B3_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000119 +#ifdef USE_PRIVATE_BF +#define BF_BF_6A3A083B_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000048C), 0x0000011A +#endif /* USE_PRIVATE_BF */ +#define BF_BF_6A3A083B_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000048C), 0x0000011B +#ifdef USE_PRIVATE_BF +#define BF_BF_D5CAD3F6_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000048C), 0x0000021C +#endif /* USE_PRIVATE_BF */ +#define BF_BF_D5CAD3F6_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000048C), 0x0000011E + +#define REG_REG_0X0490_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000490) +#ifdef USE_PRIVATE_BF +#define BF_BF_37ABA1A8_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000490), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_37ABA1A8_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000490), 0x00000101 + +#define REG_REG_0X0494_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000494) +#ifdef USE_PRIVATE_BF +#define BF_BF_4A6EADD0_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000494), 0x00000500 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_4A6EADD0_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000494), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_13A16383_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000494), 0x00000306 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_13A16383_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000494), 0x00000109 +#ifdef USE_PRIVATE_BF +#define BF_BF_C3BD2E36_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000494), 0x0000040A +#endif /* USE_PRIVATE_BF */ +#define BF_BF_C3BD2E36_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000494), 0x0000010E +#ifdef USE_PRIVATE_BF +#define BF_BF_49DD6537_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000494), 0x0000030F +#endif /* USE_PRIVATE_BF */ +#define BF_BF_49DD6537_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000494), 0x00000112 +#ifdef USE_PRIVATE_BF +#define BF_BF_FC7B85A0_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000494), 0x00000113 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_FC7B85A0_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000494), 0x00000114 +#ifdef USE_PRIVATE_BF +#define BF_BF_A946AEFC_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000494), 0x00000115 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_A946AEFC_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000494), 0x00000116 + +#define REG_REG_0X0498_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000498) +#ifdef USE_PRIVATE_BF +#define BF_BF_A0BA0FAB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000498), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_A0BA0FAB_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000498), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_1A41BF89_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000498), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_1A41BF89_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000498), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_73E79897_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000498), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_73E79897_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000498), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_54B73BD8_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000498), 0x00000106 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_54B73BD8_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000498), 0x00000107 +#ifdef USE_PRIVATE_BF +#define BF_BF_B0654939_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000498), 0x00000108 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_B0654939_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000498), 0x00000109 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X049C_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000049C) +#define BF_BF_0B8DA998_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000049C), 0x00000500 +#define BF_BF_40FAAB06_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000049C), 0x00000107 +#define BF_BF_9D6BE1C4_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000049C), 0x00000408 +#define BF_BF_72EE83E6_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000049C), 0x0000020D +#define BF_BF_6751217C_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000049C), 0x00000410 +#define BF_BF_0ABC4A65_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000049C), 0x00000418 +#define BF_BF_7465262C_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000049C), 0x0000031D +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X04A0_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000004A0) +#ifdef USE_PRIVATE_BF +#define BF_BF_D9F03C0D_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004A0), 0x00001000 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_D9F03C0D_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004A0), 0x00000110 + +#define REG_REG_0X04A4_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000004A4) +#ifdef USE_PRIVATE_BF +#define BF_BF_C5EB3B6B_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004A4), 0x00000C00 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_C5EB3B6B_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004A4), 0x0000010C +#ifdef USE_PRIVATE_BF +#define BF_BF_E123593E_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004A4), 0x0000080D +#endif /* USE_PRIVATE_BF */ +#define BF_BF_E123593E_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004A4), 0x00000115 +#ifdef USE_PRIVATE_BF +#define BF_BF_393452C1_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004A4), 0x00000416 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_393452C1_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004A4), 0x0000011A + +#define REG_REG_0X04A8_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000004A8) +#ifdef USE_PRIVATE_BF +#define BF_BF_762E9A1B_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004A8), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_762E9A1B_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004A8), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_EFCC4262_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004A8), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_EFCC4262_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004A8), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_5E9A28EB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004A8), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_5E9A28EB_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004A8), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_1BCD2E5C_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004A8), 0x00000106 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_1BCD2E5C_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004A8), 0x00000107 + +#define REG_REG_0X04AC_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000004AC) +#ifdef USE_PRIVATE_BF +#define BF_BF_2D4E0C9F_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004AC), 0x00000300 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_2D4E0C9F_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004AC), 0x00000103 + +#define REG_REG_0X04B0_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000004B0) +#ifdef USE_PRIVATE_BF +#define BF_BF_C0973401_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004B0), 0x00000300 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_C0973401_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004B0), 0x00000103 + +#define REG_REG_0X04B4_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000004B4) +#ifdef USE_PRIVATE_BF +#define BF_BF_D04D53CC_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004B4), 0x00000300 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_D04D53CC_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004B4), 0x00000103 + +#define REG_REG_0X04B8_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000004B8) +#ifdef USE_PRIVATE_BF +#define BF_BF_1CC10689_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004B8), 0x00000300 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_1CC10689_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004B8), 0x00000103 + +#define REG_REG_0X04BC_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000004BC) +#ifdef USE_PRIVATE_BF +#define BF_BF_28BB343D_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004BC), 0x00000300 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_28BB343D_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004BC), 0x00000103 + +#define REG_REG_0X04C0_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000004C0) +#ifdef USE_PRIVATE_BF +#define BF_BF_56104F9F_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004C0), 0x00000500 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_56104F9F_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004C0), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_15ACCE3B_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004C0), 0x00000506 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_15ACCE3B_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004C0), 0x0000010B +#ifdef USE_PRIVATE_BF +#define BF_BF_7A15F80D_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004C0), 0x0000050C +#endif /* USE_PRIVATE_BF */ +#define BF_BF_7A15F80D_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004C0), 0x00000111 +#ifdef USE_PRIVATE_BF +#define BF_BF_99D1F504_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004C0), 0x00000512 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_99D1F504_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004C0), 0x00000117 +#ifdef USE_PRIVATE_BF +#define BF_BF_71632961_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004C0), 0x00000518 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_71632961_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004C0), 0x0000011D + +#define REG_REG_0X04C4_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000004C4) +#ifdef USE_PRIVATE_BF +#define BF_BF_C515FC1B_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004C4), 0x0000010A +#endif /* USE_PRIVATE_BF */ +#define BF_BF_C515FC1B_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004C4), 0x0000010B +#ifdef USE_PRIVATE_BF +#define BF_BF_BF9D4E01_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004C4), 0x0000010C +#endif /* USE_PRIVATE_BF */ +#define BF_BF_BF9D4E01_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004C4), 0x0000010D +#ifdef USE_PRIVATE_BF +#define BF_BF_17A918A1_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004C4), 0x0000010E +#endif /* USE_PRIVATE_BF */ +#define BF_BF_17A918A1_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004C4), 0x0000010F +#ifdef USE_PRIVATE_BF +#define BF_BF_F585D73C_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004C4), 0x00000110 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_F585D73C_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004C4), 0x00000111 +#ifdef USE_PRIVATE_BF +#define BF_BF_60D96D7E_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004C4), 0x00000112 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_60D96D7E_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004C4), 0x00000113 + +#define REG_REG_0X04C8_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000004C8) +#ifdef USE_PRIVATE_BF +#define BF_BF_6E6DD6A6_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004C8), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_6E6DD6A6_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004C8), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_75358B68_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004C8), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_75358B68_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004C8), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_7260E949_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004C8), 0x00000108 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_7260E949_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004C8), 0x00000109 +#ifdef USE_PRIVATE_BF +#define BF_BF_7DDCFB88_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004C8), 0x0000050A +#endif /* USE_PRIVATE_BF */ +#define BF_BF_7DDCFB88_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004C8), 0x0000010F +#ifdef USE_PRIVATE_BF +#define BF_BF_815F65AE_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004C8), 0x00000110 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_815F65AE_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004C8), 0x00000111 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X04CC_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000004CC) +#define BF_BF_92EE659F_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000100 +#define BF_BF_9CE5B3DD_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000101 +#define BF_BF_997ED7A2_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000102 +#define BF_BF_8773591D_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000103 +#define BF_BF_2B51C820_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000104 +#define BF_BF_33785069_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000105 +#define BF_BF_43B42B61_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000106 +#define BF_BF_990DB6C3_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000107 +#define BF_BF_8AE80AAE_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000108 +#define BF_BF_ECF1FE4C_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000109 +#define BF_BF_3B9FA7CD_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004CC), 0x0000010A +#define BF_BF_F3ABEC40_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004CC), 0x0000010B +#define BF_BF_4459CB53_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004CC), 0x0000010C +#define BF_BF_9626B1AE_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004CC), 0x0000010D +#define BF_BF_F071661E_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004CC), 0x0000010E +#define BF_BF_C9385D2A_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004CC), 0x0000010F +#define BF_BF_905990E8_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000110 +#define BF_BF_ECC16671_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000111 +#define BF_BF_2D25984B_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000112 +#define BF_BF_90FE67B3_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000113 +#define BF_BF_46178217_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000114 +#define BF_BF_DA03E966_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000115 +#define BF_BF_9B05C98F_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000116 +#define BF_BF_D274852B_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000117 +#define BF_BF_54915CD0_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000118 +#define BF_BF_FE0CAE4C_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000119 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X04D4_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000004D4) +#ifdef USE_PRIVATE_BF +#define BF_BF_C53B812B_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004D4), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_C53B812B_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004D4), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_EB0FA4A2_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004D4), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_EB0FA4A2_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004D4), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_97354A59_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004D4), 0x00000404 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_97354A59_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004D4), 0x00000108 +#ifdef USE_PRIVATE_BF +#define BF_BF_CB643805_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004D4), 0x00000409 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_CB643805_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004D4), 0x0000010D +#ifdef USE_PRIVATE_BF +#define BF_BF_D2561460_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004D4), 0x0000010E +#endif /* USE_PRIVATE_BF */ +#define BF_BF_D2561460_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004D4), 0x0000010F + +#define REG_REG_0X04DC_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000004DC) + +#define REG_REG_0X04E0_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000004E0) +#ifdef USE_PRIVATE_BF +#define BF_BF_3F7D6943_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004E0), 0x00000200 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_3F7D6943_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004E0), 0x00000102 +#ifdef USE_PRIVATE_BF +#define BF_BF_1A6F84CA_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004E0), 0x00000203 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_1A6F84CA_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004E0), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_ADA50B94_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004E0), 0x00000206 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_ADA50B94_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004E0), 0x00000108 +#ifdef USE_PRIVATE_BF +#define BF_BF_77976C72_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004E0), 0x00000209 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_77976C72_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004E0), 0x0000010B +#ifdef USE_PRIVATE_BF +#define BF_BF_07F52F79_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004E0), 0x0000020C +#endif /* USE_PRIVATE_BF */ +#define BF_BF_07F52F79_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004E0), 0x0000010E + +#define REG_REG_0X04E4_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000004E4) +#ifdef USE_PRIVATE_BF +#define BF_BF_0DD44427_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004E4), 0x00000400 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_0DD44427_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004E4), 0x00000104 +#ifdef USE_PRIVATE_BF +#define BF_BF_BF879925_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004E4), 0x00000405 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_BF879925_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004E4), 0x00000109 +#ifdef USE_PRIVATE_BF +#define BF_BF_1476FFA8_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004E4), 0x0000040A +#endif /* USE_PRIVATE_BF */ +#define BF_BF_1476FFA8_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004E4), 0x0000010E +#ifdef USE_PRIVATE_BF +#define BF_BF_001C94C5_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004E4), 0x0000040F +#endif /* USE_PRIVATE_BF */ +#define BF_BF_001C94C5_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004E4), 0x00000113 +#ifdef USE_PRIVATE_BF +#define BF_BF_B3E34C3B_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004E4), 0x00000414 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_B3E34C3B_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004E4), 0x00000118 +#ifdef USE_PRIVATE_BF +#define BF_BF_92ECC13C_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004E4), 0x00000119 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_92ECC13C_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004E4), 0x0000011A + +#define REG_REG_0X04E8_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000004E8) +#ifdef USE_PRIVATE_BF +#define BF_BF_B5424714_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004E8), 0x00000300 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_B5424714_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004E8), 0x00000103 + +#define REG_REG_0X04EC_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000004EC) +#ifdef USE_PRIVATE_BF +#define BF_BF_3EBE01A9_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004EC), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_3EBE01A9_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004EC), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_B2862FC4_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004EC), 0x00000D04 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_B2862FC4_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004EC), 0x00000111 +#ifdef USE_PRIVATE_BF +#define BF_BF_3DB03CBF_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004EC), 0x00000D12 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_3DB03CBF_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004EC), 0x0000011F + +#define REG_REG_0X04F0_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000004F0) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X04F4_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000004F4) +#define BF_BF_4188D5E1_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004F4), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X04F8_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000004F8) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X04FC_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000004FC) +#define BF_BF_2F9A8F1A_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004FC), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0500_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000500) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0504_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000504) +#define BF_BF_4FA1F584_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000504), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0508_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000508) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X050C_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000050C) +#define BF_BF_0B81DFC5_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000050C), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0510_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000510) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0514_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000514) +#define BF_BF_A4A947A9_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000514), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0518_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000518) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X051C_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000051C) +#define BF_BF_D1D80148_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000051C), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0520_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000520) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0524_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000524) +#define BF_BF_708AD7DF_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000524), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0528_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000528) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X052C_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000052C) +#define BF_BF_75851DAC_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000052C), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0530_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000530) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0534_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000534) +#define BF_BF_C3ED8B31_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000534), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0538_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000538) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X053C_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000053C) +#define BF_BF_7855ACBB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000053C), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0540_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000540) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0544_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000544) +#define BF_BF_4B3AFE05_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000544), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0548_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000548) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X054C_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000054C) +#define BF_BF_CF9F3639_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000054C), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0550_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000550) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0554_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000554) +#define BF_BF_D392D19B_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000554), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0558_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000558) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X055C_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000055C) +#define BF_BF_AB82BE1F_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000055C), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0560_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000560) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0564_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000564) +#define BF_BF_4EE09902_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000564), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0568_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000568) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X056C_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000056C) +#define BF_BF_ACDFF011_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000056C), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0570_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000570) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0574_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000574) +#define BF_BF_1E874AC1_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000574), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0578_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000578) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X057C_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000057C) +#define BF_BF_A5CB372A_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000057C), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0580_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000580) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0584_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000584) +#define BF_BF_3EE65425_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000584), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0588_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000588) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X058C_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000058C) +#define BF_BF_6434B1F4_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000058C), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0590_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000590) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0594_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000594) +#define BF_BF_962412FE_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000594), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0598_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000598) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X059C_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000059C) +#define BF_BF_23FA173C_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000059C), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X05A0_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000005A0) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X05A4_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000005A4) +#define BF_BF_2CF7CF41_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000005A4), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X05A8_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000005A8) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X05AC_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000005AC) +#define BF_BF_249EE9F7_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000005AC), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X05B0_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000005B0) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X05B4_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000005B4) +#define BF_BF_503461ED_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000005B4), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X05B8_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000005B8) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X05BC_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000005BC) +#define BF_BF_29476181_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000005BC), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X05C0_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000005C0) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X05C4_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000005C4) +#define BF_BF_B9E86EFE_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000005C4), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X05C8_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000005C8) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X05CC_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000005CC) +#define BF_BF_3925C0DE_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000005CC), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X05D0_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000005D0) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X05D4_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000005D4) +#define BF_BF_94B7FB06_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000005D4), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X05D8_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000005D8) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X05DC_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000005DC) +#define BF_BF_BC512F04_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000005DC), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X05E0_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000005E0) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X05E4_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000005E4) +#define BF_BF_D0EFDFC6_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000005E4), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X05E8_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000005E8) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X05EC_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000005EC) +#define BF_BF_42723B74_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000005EC), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X05F0_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000005F0) + +#define REG_REG_0X0600_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000600) +#ifdef USE_PRIVATE_BF +#define BF_BF_466C700F_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000600), 0x00000300 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_466C700F_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000600), 0x00000103 + +#define REG_REG_0X0604_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000604) +#ifdef USE_PRIVATE_BF +#define BF_BF_ED93AE22_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000604), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_ED93AE22_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000604), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_242F3948_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000604), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_242F3948_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000604), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_151077EC_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000604), 0x00000504 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_151077EC_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000604), 0x00000109 + +#define REG_REG_0X0608_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000608) +#ifdef USE_PRIVATE_BF +#define BF_BF_45ACACF6_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000608), 0x00000300 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_45ACACF6_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000608), 0x00000103 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X060C_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000060C) +#define BF_BF_A226534A_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000060C), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_SCAL_SCRATCH_END_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000007FC) +#define BF_SCAL_SCRATCH_END_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000007FC), 0x00002000 + +#endif /* __ADI_APOLLO_BF_VENUS_SCAL_BROADCAST_OPEN_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_venus_scal_open.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_venus_scal_open.h new file mode 100644 index 00000000000000..402b3839a3ea81 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_venus_scal_open.h @@ -0,0 +1,1113 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:20 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_VENUS_SCAL_OPEN_H__ +#define __ADI_APOLLO_BF_VENUS_SCAL_OPEN_H__ + +/*============= D E F I N E S ==============*/ +#define VENUS_SCAL_REGMAP0_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x60282800 +#define VENUS_SCAL_REGMAP1_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x60283000 +#define VENUS_SCAL_REGMAP2_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x60283800 +#define VENUS_SCAL_REGMAP3_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x60284000 +#define VENUS_SCAL_REGMAP4_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x60284800 +#define VENUS_SCAL_REGMAP5_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x60285000 +#define VENUS_SCAL_REGMAP6_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x60285800 +#define VENUS_SCAL_REGMAP7_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x60286000 +#define VENUS_SCAL_REGMAP0_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x60482800 +#define VENUS_SCAL_REGMAP1_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x60483000 +#define VENUS_SCAL_REGMAP2_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x60483800 +#define VENUS_SCAL_REGMAP3_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x60484000 +#define VENUS_SCAL_REGMAP4_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x60484800 +#define VENUS_SCAL_REGMAP5_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x60485000 +#define VENUS_SCAL_REGMAP6_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x60485800 +#define VENUS_SCAL_REGMAP7_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x60486000 +#define VENUS_SCAL_REGMAP0_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A82800 +#define VENUS_SCAL_REGMAP1_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A83000 +#define VENUS_SCAL_REGMAP2_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A83800 +#define VENUS_SCAL_REGMAP3_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A84000 +#define VENUS_SCAL_REGMAP4_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A84800 +#define VENUS_SCAL_REGMAP5_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A85000 +#define VENUS_SCAL_REGMAP6_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A85800 +#define VENUS_SCAL_REGMAP7_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A86000 +#define VENUS_SCAL_REGMAP0_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C82800 +#define VENUS_SCAL_REGMAP1_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C83000 +#define VENUS_SCAL_REGMAP2_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C83800 +#define VENUS_SCAL_REGMAP3_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C84000 +#define VENUS_SCAL_REGMAP4_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C84800 +#define VENUS_SCAL_REGMAP5_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C85000 +#define VENUS_SCAL_REGMAP6_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C85800 +#define VENUS_SCAL_REGMAP7_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C86000 + +#define REG_SCAL_SCRATCH_BEGIN_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000000) +#define BF_SCAL_SCRATCH_BEGIN_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000000), 0x00002000 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0004_VENUS_SCAL__OPEN_ADDR(inst, n) ((inst) + 0x00000004 + 4 * (n)) +#define BF_BF_507BA89F_VENUS_SCAL__OPEN_INFO(inst, n) ((inst) + 0x00000004 + 4 * (n)), 0x00001108 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X001C_VENUS_SCAL__OPEN_ADDR(inst, n) ((inst) + 0x0000001C + 4 * (n)) +#define BF_BF_A4C77B32_VENUS_SCAL__OPEN_INFO(inst, n) ((inst) + 0x0000001C + 4 * (n)), 0x00001308 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0034_VENUS_SCAL__OPEN_ADDR(inst, n) ((inst) + 0x00000034 + 4 * (n)) +#define BF_BF_4C11EC69_INFO(inst, n) ((inst) + 0x00000034 + 4 * (n)), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X004C_VENUS_SCAL__OPEN_ADDR(inst, n) ((inst) + 0x0000004C + 4 * (n)) +#define BF_BF_4520F3B2_INFO(inst, n) ((inst) + 0x0000004C + 4 * (n)), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0084_VENUS_SCAL__OPEN_ADDR(inst, n) ((inst) + 0x00000084 + 4 * (n)) +#define BF_BF_28B73B48_VENUS_SCAL__OPEN_INFO(inst, n) ((inst) + 0x00000084 + 4 * (n)), 0x00001508 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0134_VENUS_SCAL__OPEN_ADDR(inst, n) ((inst) + 0x00000134 + 4 * (n)) +#define BF_BF_9165E1BF_INFO(inst, n) ((inst) + 0x00000134 + 4 * (n)), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0158_VENUS_SCAL__OPEN_ADDR(inst, n) ((inst) + 0x00000158 + 4 * (n)) +#define BF_BF_60B7FE5A_INFO(inst, n) ((inst) + 0x00000158 + 4 * (n)), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X017C_VENUS_SCAL__OPEN_ADDR(inst, n) ((inst) + 0x0000017C + 4 * (n)) +#define BF_BF_E957A710_INFO(inst, n) ((inst) + 0x0000017C + 4 * (n)), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X01A0_VENUS_SCAL__OPEN_ADDR(inst, n) ((inst) + 0x000001A0 + 4 * (n)) +#define BF_BF_E2EF3B98_INFO(inst, n) ((inst) + 0x000001A0 + 4 * (n)), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X01E4_VENUS_SCAL__OPEN_ADDR(inst, n) ((inst) + 0x000001E4 + 4 * (n)) +#define BF_BF_BA0DA821_INFO(inst, n) ((inst) + 0x000001E4 + 4 * (n)), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0204_VENUS_SCAL__OPEN_ADDR(inst, n) ((inst) + 0x00000204 + 4 * (n)) +#define BF_BF_92C0547B_VENUS_SCAL__OPEN_INFO(inst, n) ((inst) + 0x00000204 + 4 * (n)), 0x00001508 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X020C_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x0000020C) +#define BF_BF_D3211CFA_INFO(inst) ((inst) + 0x0000020C), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X022C_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x0000022C) +#define BF_BF_C96B1B9D_INFO(inst) ((inst) + 0x0000022C), 0x00004000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X024C_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x0000024C) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0400_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000400) +#define BF_BF_21E3283D_INFO(inst) ((inst) + 0x00000400), 0x00004000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0404_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000404) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0408_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000408) +#define BF_BF_4BD87248_INFO(inst) ((inst) + 0x00000408), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X040C_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x0000040C) +#ifdef USE_PRIVATE_BF +#define BF_BF_4D25EF5C_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000040C), 0x00000200 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_4D25EF5C_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000040C), 0x00000102 +#ifdef USE_PRIVATE_BF +#define BF_BF_48F55CE0_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000040C), 0x00000203 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_48F55CE0_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000040C), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_38DA1C3D_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000040C), 0x00000206 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_38DA1C3D_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000040C), 0x00000108 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0410_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000410) +#define BF_BF_96BCC18D_INFO(inst) ((inst) + 0x00000410), 0x00004000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0414_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000414) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0418_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000418) +#define BF_BF_CC931EEA_INFO(inst) ((inst) + 0x00000418), 0x00004000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X041C_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x0000041C) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0420_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000420) +#define BF_BF_66BBAEBB_INFO(inst) ((inst) + 0x00000420), 0x00004000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0424_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000424) + +#define REG_REG_0X0428_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000428) +#ifdef USE_PRIVATE_BF +#define BF_BF_BAD86450_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000428), 0x00000600 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_BAD86450_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000428), 0x00000106 +#ifdef USE_PRIVATE_BF +#define BF_BF_0D9CF522_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000428), 0x00000607 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_0D9CF522_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000428), 0x0000010D + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X042C_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x0000042C) +#define BF_BF_B62785DB_INFO(inst) ((inst) + 0x0000042C), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0430_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000430) +#define BF_BF_733BBA6A_INFO(inst) ((inst) + 0x00000430), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0434_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000434) +#define BF_BF_47486732_INFO(inst) ((inst) + 0x00000434), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0438_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000438) +#define BF_BF_454B21FC_INFO(inst) ((inst) + 0x00000438), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X043C_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x0000043C) +#define BF_BF_3BB2B179_INFO(inst) ((inst) + 0x0000043C), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0440_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000440) +#define BF_BF_0D3C03A5_INFO(inst) ((inst) + 0x00000440), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0444_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000444) +#define BF_BF_53142F7C_INFO(inst) ((inst) + 0x00000444), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0448_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000448) +#define BF_BF_FF13351A_INFO(inst) ((inst) + 0x00000448), 0x00004000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X044C_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x0000044C) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0450_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000450) +#define BF_BF_246FD1C9_INFO(inst) ((inst) + 0x00000450), 0x00004000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0454_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000454) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0458_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000458) +#define BF_BF_AC57581C_INFO(inst) ((inst) + 0x00000458), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X045C_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x0000045C) +#define BF_BF_F6B2636C_INFO(inst) ((inst) + 0x0000045C), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0460_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000460) +#define BF_BF_5D22C096_INFO(inst) ((inst) + 0x00000460), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0464_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000464) +#define BF_BF_83558BC6_INFO(inst) ((inst) + 0x00000464), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0468_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000468) +#define BF_BF_D4C5F783_INFO(inst) ((inst) + 0x00000468), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X046C_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x0000046C) +#ifdef USE_PRIVATE_BF +#define BF_BF_04FC627D_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000046C), 0x00000800 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_04FC627D_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000046C), 0x00000108 + +#define REG_REG_0X0470_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000470) +#ifdef USE_PRIVATE_BF +#define BF_BF_89FA30CF_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000470), 0x00000400 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_89FA30CF_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000470), 0x00000104 +#ifdef USE_PRIVATE_BF +#define BF_BF_83063494_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000470), 0x00000405 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_83063494_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000470), 0x00000109 +#ifdef USE_PRIVATE_BF +#define BF_BF_6073B2AA_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000470), 0x0000040A +#endif /* USE_PRIVATE_BF */ +#define BF_BF_6073B2AA_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000470), 0x0000010E +#ifdef USE_PRIVATE_BF +#define BF_BF_56C106E1_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000470), 0x0000040F +#endif /* USE_PRIVATE_BF */ +#define BF_BF_56C106E1_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000470), 0x00000113 +#ifdef USE_PRIVATE_BF +#define BF_BF_34407588_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000470), 0x00000414 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_34407588_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000470), 0x00000118 + +#define REG_REG_0X0474_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000474) +#ifdef USE_PRIVATE_BF +#define BF_BF_DAD827A3_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000474), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_DAD827A3_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000474), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_7BA7C73B_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000474), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_7BA7C73B_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000474), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_DBA82E9D_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000474), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_DBA82E9D_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000474), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_3098C59C_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000474), 0x00000106 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_3098C59C_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000474), 0x00000107 + +#define REG_REG_0X0478_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000478) +#ifdef USE_PRIVATE_BF +#define BF_BF_45F7874C_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000478), 0x00000400 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_45F7874C_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000478), 0x00000104 +#ifdef USE_PRIVATE_BF +#define BF_BF_32F08E3A_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000478), 0x00000405 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_32F08E3A_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000478), 0x00000109 +#ifdef USE_PRIVATE_BF +#define BF_BF_D797E7BF_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000478), 0x0000040A +#endif /* USE_PRIVATE_BF */ +#define BF_BF_D797E7BF_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000478), 0x0000010E + +#define REG_REG_0X047C_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x0000047C) +#ifdef USE_PRIVATE_BF +#define BF_BF_A432F804_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000047C), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_A432F804_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000047C), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_59DA3AA0_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000047C), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_59DA3AA0_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000047C), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_48B52FAE_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000047C), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_48B52FAE_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000047C), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_CEDBB6EE_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000047C), 0x00000106 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_CEDBB6EE_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000047C), 0x00000107 + +#define REG_REG_0X0480_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000480) +#ifdef USE_PRIVATE_BF +#define BF_BF_821BF1CA_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000480), 0x00000300 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_821BF1CA_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000480), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_27DD70A9_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000480), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_27DD70A9_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000480), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_AD4714AD_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000480), 0x00000206 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_AD4714AD_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000480), 0x00000108 + +#define REG_REG_0X0484_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000484) +#ifdef USE_PRIVATE_BF +#define BF_BF_5CA2D2B4_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000484), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_5CA2D2B4_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000484), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_CC0429E4_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000484), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_CC0429E4_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000484), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_67599BD7_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000484), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_67599BD7_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000484), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_B9D7C00F_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000484), 0x00000106 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_B9D7C00F_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000484), 0x00000107 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0488_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000488) +#define BF_BF_EC9E82E8_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000488), 0x00000800 +#define BF_BF_0818209E_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000488), 0x00000808 +#define BF_BF_B416D230_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000488), 0x00000810 +#define BF_BF_EACE3FE4_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000488), 0x00000818 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X048C_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x0000048C) +#ifdef USE_PRIVATE_BF +#define BF_BF_ED7193DA_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_ED7193DA_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_9F9E1975_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_9F9E1975_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_25552B6D_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_25552B6D_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_5E7E18C6_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000106 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_5E7E18C6_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000107 +#ifdef USE_PRIVATE_BF +#define BF_BF_F4D789F1_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000108 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_F4D789F1_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000109 +#ifdef USE_PRIVATE_BF +#define BF_BF_E1F9065C_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000048C), 0x0000010A +#endif /* USE_PRIVATE_BF */ +#define BF_BF_E1F9065C_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000048C), 0x0000010B +#ifdef USE_PRIVATE_BF +#define BF_BF_5B7943BD_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000048C), 0x0000010C +#endif /* USE_PRIVATE_BF */ +#define BF_BF_5B7943BD_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000048C), 0x0000010D +#ifdef USE_PRIVATE_BF +#define BF_BF_684D9C7E_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000048C), 0x0000010E +#endif /* USE_PRIVATE_BF */ +#define BF_BF_684D9C7E_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000048C), 0x0000010F +#ifdef USE_PRIVATE_BF +#define BF_BF_B483B9CE_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000112 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_B483B9CE_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000113 +#ifdef USE_PRIVATE_BF +#define BF_BF_C967ACFB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000114 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_C967ACFB_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000115 +#ifdef USE_PRIVATE_BF +#define BF_BF_9580F3CE_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000116 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_9580F3CE_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000117 +#ifdef USE_PRIVATE_BF +#define BF_BF_5B4B40B3_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000118 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_5B4B40B3_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000119 +#ifdef USE_PRIVATE_BF +#define BF_BF_6A3A083B_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000048C), 0x0000011A +#endif /* USE_PRIVATE_BF */ +#define BF_BF_6A3A083B_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000048C), 0x0000011B +#ifdef USE_PRIVATE_BF +#define BF_BF_D5CAD3F6_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000048C), 0x0000021C +#endif /* USE_PRIVATE_BF */ +#define BF_BF_D5CAD3F6_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000048C), 0x0000011E + +#define REG_REG_0X0490_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000490) +#ifdef USE_PRIVATE_BF +#define BF_BF_37ABA1A8_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000490), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_37ABA1A8_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000490), 0x00000101 + +#define REG_REG_0X0494_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000494) +#ifdef USE_PRIVATE_BF +#define BF_BF_4A6EADD0_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000494), 0x00000500 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_4A6EADD0_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000494), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_13A16383_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000494), 0x00000306 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_13A16383_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000494), 0x00000109 +#ifdef USE_PRIVATE_BF +#define BF_BF_C3BD2E36_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000494), 0x0000040A +#endif /* USE_PRIVATE_BF */ +#define BF_BF_C3BD2E36_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000494), 0x0000010E +#ifdef USE_PRIVATE_BF +#define BF_BF_49DD6537_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000494), 0x0000030F +#endif /* USE_PRIVATE_BF */ +#define BF_BF_49DD6537_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000494), 0x00000112 +#ifdef USE_PRIVATE_BF +#define BF_BF_FC7B85A0_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000494), 0x00000113 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_FC7B85A0_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000494), 0x00000114 +#ifdef USE_PRIVATE_BF +#define BF_BF_A946AEFC_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000494), 0x00000115 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_A946AEFC_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000494), 0x00000116 + +#define REG_REG_0X0498_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000498) +#ifdef USE_PRIVATE_BF +#define BF_BF_A0BA0FAB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000498), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_A0BA0FAB_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000498), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_1A41BF89_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000498), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_1A41BF89_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000498), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_73E79897_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000498), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_73E79897_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000498), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_54B73BD8_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000498), 0x00000106 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_54B73BD8_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000498), 0x00000107 +#ifdef USE_PRIVATE_BF +#define BF_BF_B0654939_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000498), 0x00000108 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_B0654939_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000498), 0x00000109 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X049C_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x0000049C) +#define BF_BF_0B8DA998_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000049C), 0x00000500 +#define BF_BF_40FAAB06_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000049C), 0x00000107 +#define BF_BF_9D6BE1C4_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000049C), 0x00000408 +#define BF_BF_72EE83E6_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000049C), 0x0000020D +#define BF_BF_6751217C_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000049C), 0x00000410 +#define BF_BF_0ABC4A65_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000049C), 0x00000418 +#define BF_BF_7465262C_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000049C), 0x0000031D +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X04A0_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000004A0) +#ifdef USE_PRIVATE_BF +#define BF_BF_D9F03C0D_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004A0), 0x00001000 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_D9F03C0D_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004A0), 0x00000110 + +#define REG_REG_0X04A4_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000004A4) +#ifdef USE_PRIVATE_BF +#define BF_BF_C5EB3B6B_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004A4), 0x00000C00 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_C5EB3B6B_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004A4), 0x0000010C +#ifdef USE_PRIVATE_BF +#define BF_BF_E123593E_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004A4), 0x0000080D +#endif /* USE_PRIVATE_BF */ +#define BF_BF_E123593E_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004A4), 0x00000115 +#ifdef USE_PRIVATE_BF +#define BF_BF_393452C1_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004A4), 0x00000416 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_393452C1_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004A4), 0x0000011A + +#define REG_REG_0X04A8_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000004A8) +#ifdef USE_PRIVATE_BF +#define BF_BF_762E9A1B_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004A8), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_762E9A1B_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004A8), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_EFCC4262_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004A8), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_EFCC4262_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004A8), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_5E9A28EB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004A8), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_5E9A28EB_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004A8), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_1BCD2E5C_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004A8), 0x00000106 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_1BCD2E5C_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004A8), 0x00000107 + +#define REG_REG_0X04AC_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000004AC) +#ifdef USE_PRIVATE_BF +#define BF_BF_2D4E0C9F_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004AC), 0x00000300 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_2D4E0C9F_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004AC), 0x00000103 + +#define REG_REG_0X04B0_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000004B0) +#ifdef USE_PRIVATE_BF +#define BF_BF_C0973401_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004B0), 0x00000300 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_C0973401_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004B0), 0x00000103 + +#define REG_REG_0X04B4_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000004B4) +#ifdef USE_PRIVATE_BF +#define BF_BF_D04D53CC_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004B4), 0x00000300 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_D04D53CC_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004B4), 0x00000103 + +#define REG_REG_0X04B8_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000004B8) +#ifdef USE_PRIVATE_BF +#define BF_BF_1CC10689_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004B8), 0x00000300 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_1CC10689_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004B8), 0x00000103 + +#define REG_REG_0X04BC_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000004BC) +#ifdef USE_PRIVATE_BF +#define BF_BF_28BB343D_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004BC), 0x00000300 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_28BB343D_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004BC), 0x00000103 + +#define REG_REG_0X04C0_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000004C0) +#ifdef USE_PRIVATE_BF +#define BF_BF_56104F9F_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004C0), 0x00000500 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_56104F9F_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004C0), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_15ACCE3B_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004C0), 0x00000506 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_15ACCE3B_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004C0), 0x0000010B +#ifdef USE_PRIVATE_BF +#define BF_BF_7A15F80D_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004C0), 0x0000050C +#endif /* USE_PRIVATE_BF */ +#define BF_BF_7A15F80D_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004C0), 0x00000111 +#ifdef USE_PRIVATE_BF +#define BF_BF_99D1F504_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004C0), 0x00000512 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_99D1F504_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004C0), 0x00000117 +#ifdef USE_PRIVATE_BF +#define BF_BF_71632961_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004C0), 0x00000518 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_71632961_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004C0), 0x0000011D + +#define REG_REG_0X04C4_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000004C4) +#ifdef USE_PRIVATE_BF +#define BF_BF_C515FC1B_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004C4), 0x0000010A +#endif /* USE_PRIVATE_BF */ +#define BF_BF_C515FC1B_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004C4), 0x0000010B +#ifdef USE_PRIVATE_BF +#define BF_BF_BF9D4E01_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004C4), 0x0000010C +#endif /* USE_PRIVATE_BF */ +#define BF_BF_BF9D4E01_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004C4), 0x0000010D +#ifdef USE_PRIVATE_BF +#define BF_BF_17A918A1_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004C4), 0x0000010E +#endif /* USE_PRIVATE_BF */ +#define BF_BF_17A918A1_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004C4), 0x0000010F +#ifdef USE_PRIVATE_BF +#define BF_BF_F585D73C_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004C4), 0x00000110 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_F585D73C_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004C4), 0x00000111 +#ifdef USE_PRIVATE_BF +#define BF_BF_60D96D7E_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004C4), 0x00000112 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_60D96D7E_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004C4), 0x00000113 + +#define REG_REG_0X04C8_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000004C8) +#ifdef USE_PRIVATE_BF +#define BF_BF_6E6DD6A6_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004C8), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_6E6DD6A6_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004C8), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_75358B68_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004C8), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_75358B68_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004C8), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_7260E949_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004C8), 0x00000108 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_7260E949_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004C8), 0x00000109 +#ifdef USE_PRIVATE_BF +#define BF_BF_7DDCFB88_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004C8), 0x0000050A +#endif /* USE_PRIVATE_BF */ +#define BF_BF_7DDCFB88_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004C8), 0x0000010F +#ifdef USE_PRIVATE_BF +#define BF_BF_815F65AE_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004C8), 0x00000110 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_815F65AE_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004C8), 0x00000111 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X04CC_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000004CC) +#define BF_BF_92EE659F_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000100 +#define BF_BF_9CE5B3DD_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000101 +#define BF_BF_997ED7A2_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000102 +#define BF_BF_8773591D_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000103 +#define BF_BF_2B51C820_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000104 +#define BF_BF_33785069_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000105 +#define BF_BF_43B42B61_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000106 +#define BF_BF_990DB6C3_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000107 +#define BF_BF_8AE80AAE_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000108 +#define BF_BF_ECF1FE4C_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000109 +#define BF_BF_3B9FA7CD_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004CC), 0x0000010A +#define BF_BF_F3ABEC40_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004CC), 0x0000010B +#define BF_BF_4459CB53_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004CC), 0x0000010C +#define BF_BF_9626B1AE_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004CC), 0x0000010D +#define BF_BF_F071661E_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004CC), 0x0000010E +#define BF_BF_C9385D2A_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004CC), 0x0000010F +#define BF_BF_905990E8_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000110 +#define BF_BF_ECC16671_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000111 +#define BF_BF_2D25984B_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000112 +#define BF_BF_90FE67B3_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000113 +#define BF_BF_46178217_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000114 +#define BF_BF_DA03E966_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000115 +#define BF_BF_9B05C98F_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000116 +#define BF_BF_D274852B_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000117 +#define BF_BF_54915CD0_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000118 +#define BF_BF_FE0CAE4C_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000119 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X04D4_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000004D4) +#ifdef USE_PRIVATE_BF +#define BF_BF_C53B812B_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004D4), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_C53B812B_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004D4), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_EB0FA4A2_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004D4), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_EB0FA4A2_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004D4), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_97354A59_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004D4), 0x00000404 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_97354A59_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004D4), 0x00000108 +#ifdef USE_PRIVATE_BF +#define BF_BF_CB643805_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004D4), 0x00000409 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_CB643805_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004D4), 0x0000010D +#ifdef USE_PRIVATE_BF +#define BF_BF_D2561460_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004D4), 0x0000010E +#endif /* USE_PRIVATE_BF */ +#define BF_BF_D2561460_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004D4), 0x0000010F + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X04DC_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000004DC) +#define BF_BF_0F880F25_INFO(inst) ((inst) + 0x000004DC), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X04E0_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000004E0) +#ifdef USE_PRIVATE_BF +#define BF_BF_3F7D6943_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004E0), 0x00000200 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_3F7D6943_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004E0), 0x00000102 +#ifdef USE_PRIVATE_BF +#define BF_BF_1A6F84CA_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004E0), 0x00000203 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_1A6F84CA_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004E0), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_ADA50B94_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004E0), 0x00000206 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_ADA50B94_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004E0), 0x00000108 +#ifdef USE_PRIVATE_BF +#define BF_BF_77976C72_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004E0), 0x00000209 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_77976C72_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004E0), 0x0000010B +#ifdef USE_PRIVATE_BF +#define BF_BF_07F52F79_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004E0), 0x0000020C +#endif /* USE_PRIVATE_BF */ +#define BF_BF_07F52F79_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004E0), 0x0000010E + +#define REG_REG_0X04E4_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000004E4) +#ifdef USE_PRIVATE_BF +#define BF_BF_0DD44427_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004E4), 0x00000400 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_0DD44427_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004E4), 0x00000104 +#ifdef USE_PRIVATE_BF +#define BF_BF_BF879925_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004E4), 0x00000405 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_BF879925_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004E4), 0x00000109 +#ifdef USE_PRIVATE_BF +#define BF_BF_1476FFA8_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004E4), 0x0000040A +#endif /* USE_PRIVATE_BF */ +#define BF_BF_1476FFA8_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004E4), 0x0000010E +#ifdef USE_PRIVATE_BF +#define BF_BF_001C94C5_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004E4), 0x0000040F +#endif /* USE_PRIVATE_BF */ +#define BF_BF_001C94C5_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004E4), 0x00000113 +#ifdef USE_PRIVATE_BF +#define BF_BF_B3E34C3B_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004E4), 0x00000414 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_B3E34C3B_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004E4), 0x00000118 +#ifdef USE_PRIVATE_BF +#define BF_BF_92ECC13C_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004E4), 0x00000119 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_92ECC13C_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004E4), 0x0000011A + +#define REG_REG_0X04E8_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000004E8) +#ifdef USE_PRIVATE_BF +#define BF_BF_B5424714_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004E8), 0x00000300 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_B5424714_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004E8), 0x00000103 + +#define REG_REG_0X04EC_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000004EC) +#ifdef USE_PRIVATE_BF +#define BF_BF_3EBE01A9_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004EC), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_3EBE01A9_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004EC), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_B2862FC4_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004EC), 0x00000D04 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_B2862FC4_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004EC), 0x00000111 +#ifdef USE_PRIVATE_BF +#define BF_BF_3DB03CBF_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004EC), 0x00000D12 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_3DB03CBF_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004EC), 0x0000011F + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X04F0_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000004F0) +#define BF_BF_00A846A3_INFO(inst) ((inst) + 0x000004F0), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X04F4_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000004F4) +#define BF_BF_4188D5E1_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004F4), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X04F8_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000004F8) +#define BF_BF_2FC68603_INFO(inst) ((inst) + 0x000004F8), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X04FC_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000004FC) +#define BF_BF_2F9A8F1A_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004FC), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0500_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000500) +#define BF_BF_6E25F661_INFO(inst) ((inst) + 0x00000500), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0504_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000504) +#define BF_BF_4FA1F584_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000504), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0508_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000508) +#define BF_BF_82793082_INFO(inst) ((inst) + 0x00000508), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X050C_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x0000050C) +#define BF_BF_0B81DFC5_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000050C), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0510_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000510) +#define BF_BF_784B0F75_INFO(inst) ((inst) + 0x00000510), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0514_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000514) +#define BF_BF_A4A947A9_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000514), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0518_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000518) +#define BF_BF_58ECDFC2_INFO(inst) ((inst) + 0x00000518), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X051C_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x0000051C) +#define BF_BF_D1D80148_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000051C), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0520_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000520) +#define BF_BF_D1607095_INFO(inst) ((inst) + 0x00000520), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0524_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000524) +#define BF_BF_708AD7DF_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000524), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0528_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000528) +#define BF_BF_DFE4D7DD_INFO(inst) ((inst) + 0x00000528), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X052C_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x0000052C) +#define BF_BF_75851DAC_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000052C), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0530_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000530) +#define BF_BF_AA64DED9_INFO(inst) ((inst) + 0x00000530), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0534_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000534) +#define BF_BF_C3ED8B31_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000534), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0538_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000538) +#define BF_BF_B4B5A6C1_INFO(inst) ((inst) + 0x00000538), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X053C_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x0000053C) +#define BF_BF_7855ACBB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000053C), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0540_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000540) +#define BF_BF_29A47F0D_INFO(inst) ((inst) + 0x00000540), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0544_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000544) +#define BF_BF_4B3AFE05_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000544), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0548_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000548) +#define BF_BF_C47668E5_INFO(inst) ((inst) + 0x00000548), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X054C_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x0000054C) +#define BF_BF_CF9F3639_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000054C), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0550_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000550) +#define BF_BF_82E004D1_INFO(inst) ((inst) + 0x00000550), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0554_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000554) +#define BF_BF_D392D19B_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000554), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0558_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000558) +#define BF_BF_3AD01442_INFO(inst) ((inst) + 0x00000558), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X055C_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x0000055C) +#define BF_BF_AB82BE1F_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000055C), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0560_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000560) +#define BF_BF_1AFAA34A_INFO(inst) ((inst) + 0x00000560), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0564_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000564) +#define BF_BF_4EE09902_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000564), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0568_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000568) +#define BF_BF_5D9EC428_INFO(inst) ((inst) + 0x00000568), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X056C_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x0000056C) +#define BF_BF_ACDFF011_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000056C), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0570_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000570) +#define BF_BF_37EBFAB1_INFO(inst) ((inst) + 0x00000570), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0574_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000574) +#define BF_BF_1E874AC1_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000574), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0578_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000578) +#define BF_BF_AB02A333_INFO(inst) ((inst) + 0x00000578), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X057C_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x0000057C) +#define BF_BF_A5CB372A_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000057C), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0580_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000580) +#define BF_BF_A0DDEC2F_INFO(inst) ((inst) + 0x00000580), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0584_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000584) +#define BF_BF_3EE65425_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000584), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0588_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000588) +#define BF_BF_21335A8D_INFO(inst) ((inst) + 0x00000588), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X058C_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x0000058C) +#define BF_BF_6434B1F4_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000058C), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0590_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000590) +#define BF_BF_4D12CF33_INFO(inst) ((inst) + 0x00000590), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0594_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000594) +#define BF_BF_962412FE_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000594), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0598_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000598) +#define BF_BF_5BB1C70F_INFO(inst) ((inst) + 0x00000598), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X059C_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x0000059C) +#define BF_BF_23FA173C_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000059C), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X05A0_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000005A0) +#define BF_BF_9512FD04_INFO(inst) ((inst) + 0x000005A0), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X05A4_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000005A4) +#define BF_BF_2CF7CF41_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000005A4), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X05A8_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000005A8) +#define BF_BF_4963956F_INFO(inst) ((inst) + 0x000005A8), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X05AC_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000005AC) +#define BF_BF_249EE9F7_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000005AC), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X05B0_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000005B0) +#define BF_BF_AD599480_INFO(inst) ((inst) + 0x000005B0), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X05B4_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000005B4) +#define BF_BF_503461ED_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000005B4), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X05B8_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000005B8) +#define BF_BF_D89B2244_INFO(inst) ((inst) + 0x000005B8), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X05BC_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000005BC) +#define BF_BF_29476181_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000005BC), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X05C0_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000005C0) +#define BF_BF_744E1013_INFO(inst) ((inst) + 0x000005C0), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X05C4_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000005C4) +#define BF_BF_B9E86EFE_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000005C4), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X05C8_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000005C8) +#define BF_BF_8FAABBBA_INFO(inst) ((inst) + 0x000005C8), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X05CC_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000005CC) +#define BF_BF_3925C0DE_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000005CC), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X05D0_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000005D0) +#define BF_BF_15410123_INFO(inst) ((inst) + 0x000005D0), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X05D4_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000005D4) +#define BF_BF_94B7FB06_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000005D4), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X05D8_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000005D8) +#define BF_BF_DEAED8DB_INFO(inst) ((inst) + 0x000005D8), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X05DC_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000005DC) +#define BF_BF_BC512F04_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000005DC), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X05E0_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000005E0) +#define BF_BF_ADC1F655_INFO(inst) ((inst) + 0x000005E0), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X05E4_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000005E4) +#define BF_BF_D0EFDFC6_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000005E4), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X05E8_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000005E8) +#define BF_BF_D14D7EB7_INFO(inst) ((inst) + 0x000005E8), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X05EC_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000005EC) +#define BF_BF_42723B74_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000005EC), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X05F0_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000005F0) +#define BF_BF_BAC0A92F_INFO(inst) ((inst) + 0x000005F0), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0600_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000600) +#ifdef USE_PRIVATE_BF +#define BF_BF_466C700F_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000600), 0x00000300 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_466C700F_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000600), 0x00000103 + +#define REG_REG_0X0604_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000604) +#ifdef USE_PRIVATE_BF +#define BF_BF_ED93AE22_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000604), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_ED93AE22_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000604), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_242F3948_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000604), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_242F3948_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000604), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_151077EC_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000604), 0x00000504 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_151077EC_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000604), 0x00000109 + +#define REG_REG_0X0608_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000608) +#ifdef USE_PRIVATE_BF +#define BF_BF_45ACACF6_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000608), 0x00000300 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_45ACACF6_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000608), 0x00000103 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X060C_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x0000060C) +#define BF_BF_A226534A_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000060C), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_SCAL_SCRATCH_END_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000007FC) +#define BF_SCAL_SCRATCH_END_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000007FC), 0x00002000 + +#endif /* __ADI_APOLLO_BF_VENUS_SCAL_OPEN_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_watchdog_timer.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_watchdog_timer.h new file mode 100644 index 00000000000000..8de25ecfff337c --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/a0/adi_apollo_bf_watchdog_timer.h @@ -0,0 +1,30 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:17 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_WATCHDOG_TIMER_H__ +#define __ADI_APOLLO_BF_WATCHDOG_TIMER_H__ + +/*============= D E F I N E S ==============*/ +#define REG_WD_LOAD_ADDR 0x41000000 +#define BF_WD_LOAD_VAL_INFO 0x41000000, 0x00002000 + +#define REG_WD_CON_ADDR 0x41000004 +#define BF_WD_ENABLE_INFO 0x41000004, 0x00000100 +#define BF_WD_RESTART_INFO 0x41000004, 0x00000101 + +#define REG_WD_VAL_ADDR 0x41000008 +#define BF_WD_VAL_INFO 0x41000008, 0x00002000 + +#endif /* __ADI_APOLLO_BF_WATCHDOG_TIMER_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_actrl_east_open.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_actrl_east_open.h new file mode 100644 index 00000000000000..ff4a7ca1ea2fef --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_actrl_east_open.h @@ -0,0 +1,1284 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:19 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_ACTRL_EAST_OPEN_H__ +#define __ADI_APOLLO_BF_ACTRL_EAST_OPEN_H__ + +/*============= D E F I N E S ==============*/ +#define VENUS_ACTRL_EAST_REGMAP_ADC8_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x60262800 +#define VENUS_ACTRL_EAST_REGMAP_ADC8_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x60462800 +#define VENUS_ACTRL_EAST_REGMAP_ADC8_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A62800 +#define VENUS_ACTRL_EAST_REGMAP_ADC8_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C62800 + +#define REG_ACTRL_SCRATCH_BEGIN_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000000) +#define BF_ACTRL_SCRATCH_BEGIN_ACTRL_EAST__OPEN_INFO(inst) ((inst) + 0x00000000), 0x00000800 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0001_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000001) +#define BF_BF_ACE00BAA_INFO(inst) ((inst) + 0x00000001), 0x00000100 +#define BF_BF_F62E7DB9_INFO(inst) ((inst) + 0x00000001), 0x00000101 +#define BF_BF_BF9A2608_INFO(inst) ((inst) + 0x00000001), 0x00000102 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0002_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000002) +#define BF_BF_92E841D6_INFO(inst) ((inst) + 0x00000002), 0x00000100 +#define BF_BF_3D0DBB97_INFO(inst) ((inst) + 0x00000002), 0x00000101 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0003_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000003) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0004_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000004) +#define BF_BF_BEE14B53_INFO(inst) ((inst) + 0x00000004), 0x00000100 +#define BF_BF_5730BA68_INFO(inst) ((inst) + 0x00000004), 0x00000101 +#define BF_BF_539CB8A7_INFO(inst) ((inst) + 0x00000004), 0x00000102 +#define BF_BF_B8B6E31D_INFO(inst) ((inst) + 0x00000004), 0x00000103 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0005_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000005) +#define BF_BF_1322B279_INFO(inst) ((inst) + 0x00000005), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0006_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000006) +#define BF_BF_743CADCA_INFO(inst) ((inst) + 0x00000006), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0007_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000007) +#define BF_BF_03A82045_INFO(inst) ((inst) + 0x00000007), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0008_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000008) +#define BF_BF_38ABEB20_INFO(inst) ((inst) + 0x00000008), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0009_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000009) +#define BF_BF_7CEDBF88_INFO(inst) ((inst) + 0x00000009), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X000A_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000000A) +#define BF_BF_BAB445BD_INFO(inst) ((inst) + 0x0000000A), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X000B_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000000B) +#define BF_BF_A7963CB3_INFO(inst) ((inst) + 0x0000000B), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X000C_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000000C) +#define BF_BF_CFE1765B_INFO(inst) ((inst) + 0x0000000C), 0x00000200 +#define BF_BF_EC6E7162_INFO(inst) ((inst) + 0x0000000C), 0x00000202 +#define BF_BF_2BA5C0FA_INFO(inst) ((inst) + 0x0000000C), 0x00000204 +#define BF_BF_D0E1FA60_INFO(inst) ((inst) + 0x0000000C), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X000D_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000000D) +#define BF_BF_57356264_INFO(inst) ((inst) + 0x0000000D), 0x00000200 +#define BF_BF_288D3CEE_INFO(inst) ((inst) + 0x0000000D), 0x00000202 +#define BF_BF_307A9467_INFO(inst) ((inst) + 0x0000000D), 0x00000204 +#define BF_BF_D8A978DA_INFO(inst) ((inst) + 0x0000000D), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X000E_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000000E) +#define BF_BF_D3D1EB46_INFO(inst) ((inst) + 0x0000000E), 0x00000300 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X000F_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000000F) +#define BF_BF_16A32022_INFO(inst) ((inst) + 0x0000000F), 0x00000200 +#define BF_BF_C9BC413E_INFO(inst) ((inst) + 0x0000000F), 0x00000202 +#define BF_BF_8248D837_INFO(inst) ((inst) + 0x0000000F), 0x00000204 +#define BF_BF_ED5B6FF6_INFO(inst) ((inst) + 0x0000000F), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0010_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000010) +#define BF_BF_5A05B140_INFO(inst) ((inst) + 0x00000010), 0x00000200 +#define BF_BF_0E866118_INFO(inst) ((inst) + 0x00000010), 0x00000202 +#define BF_BF_A825D579_INFO(inst) ((inst) + 0x00000010), 0x00000204 +#define BF_BF_0347B9EA_INFO(inst) ((inst) + 0x00000010), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0011_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000011) +#define BF_BF_37729898_INFO(inst) ((inst) + 0x00000011), 0x00000300 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0012_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000012) +#define BF_BF_59991ED3_INFO(inst) ((inst) + 0x00000012), 0x00000200 +#define BF_BF_90039DED_INFO(inst) ((inst) + 0x00000012), 0x00000202 +#define BF_BF_A0BD92C7_INFO(inst) ((inst) + 0x00000012), 0x00000204 +#define BF_BF_B7372F28_INFO(inst) ((inst) + 0x00000012), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0013_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000013) +#define BF_BF_354A1DB4_INFO(inst) ((inst) + 0x00000013), 0x00000200 +#define BF_BF_ECF1C1DF_INFO(inst) ((inst) + 0x00000013), 0x00000202 +#define BF_BF_9877306D_INFO(inst) ((inst) + 0x00000013), 0x00000204 +#define BF_BF_6DACC9C0_INFO(inst) ((inst) + 0x00000013), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0014_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000014) +#define BF_BF_9FA63423_INFO(inst) ((inst) + 0x00000014), 0x00000300 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0015_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000015) +#define BF_BF_9BF98EFF_INFO(inst) ((inst) + 0x00000015), 0x00000200 +#define BF_BF_B65ED02F_INFO(inst) ((inst) + 0x00000015), 0x00000202 +#define BF_BF_4E171ADD_INFO(inst) ((inst) + 0x00000015), 0x00000204 +#define BF_BF_26E0A67C_INFO(inst) ((inst) + 0x00000015), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0016_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000016) +#define BF_BF_D3BA083C_INFO(inst) ((inst) + 0x00000016), 0x00000200 +#define BF_BF_C0E8E123_INFO(inst) ((inst) + 0x00000016), 0x00000202 +#define BF_BF_0B70C8C8_INFO(inst) ((inst) + 0x00000016), 0x00000204 +#define BF_BF_CAB57CCA_INFO(inst) ((inst) + 0x00000016), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0017_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000017) +#define BF_BF_92522375_INFO(inst) ((inst) + 0x00000017), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0018_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000018) +#define BF_BF_93BD1868_INFO(inst) ((inst) + 0x00000018), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0019_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000019) +#define BF_BF_FFFA6B56_INFO(inst) ((inst) + 0x00000019), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X001A_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000001A) +#define BF_BF_4D8D848C_INFO(inst) ((inst) + 0x0000001A), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X001B_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000001B) +#define BF_BF_B25CABA3_INFO(inst) ((inst) + 0x0000001B), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X001C_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000001C) +#define BF_BF_23232F4E_INFO(inst) ((inst) + 0x0000001C), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X001D_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000001D) +#define BF_BF_D767B532_INFO(inst) ((inst) + 0x0000001D), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X001E_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000001E) +#define BF_BF_1CD7B017_INFO(inst) ((inst) + 0x0000001E), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X001F_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000001F) +#define BF_BF_16E15371_INFO(inst) ((inst) + 0x0000001F), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0020_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000020) +#define BF_BF_41267477_INFO(inst) ((inst) + 0x00000020), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0021_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000021) +#define BF_BF_478F8D2C_INFO(inst) ((inst) + 0x00000021), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0022_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000022) +#define BF_BF_099AE646_INFO(inst) ((inst) + 0x00000022), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0023_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000023) +#define BF_BF_232FA1F1_INFO(inst) ((inst) + 0x00000023), 0x00000400 +#define BF_BF_6CC9581E_INFO(inst) ((inst) + 0x00000023), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0024_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000024) +#define BF_BF_E7B0BAD2_INFO(inst) ((inst) + 0x00000024), 0x00000400 +#define BF_BF_6BE57A35_INFO(inst) ((inst) + 0x00000024), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0025_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000025) +#define BF_BF_3E67A859_INFO(inst) ((inst) + 0x00000025), 0x00000200 +#define BF_BF_367F3FFC_INFO(inst) ((inst) + 0x00000025), 0x00000202 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0026_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000026) +#define BF_BF_1778EDD1_INFO(inst) ((inst) + 0x00000026), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0027_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000027) +#define BF_BF_7DD4FA6D_INFO(inst) ((inst) + 0x00000027), 0x00000200 +#define BF_BF_FD32EB34_INFO(inst) ((inst) + 0x00000027), 0x00000202 +#define BF_BF_3F98E934_INFO(inst) ((inst) + 0x00000027), 0x00000204 +#define BF_BF_AE605C1A_INFO(inst) ((inst) + 0x00000027), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0028_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000028) +#define BF_BF_BD6EDB40_INFO(inst) ((inst) + 0x00000028), 0x00000200 +#define BF_BF_D601DE4D_INFO(inst) ((inst) + 0x00000028), 0x00000202 +#define BF_BF_D57EE75D_INFO(inst) ((inst) + 0x00000028), 0x00000204 +#define BF_BF_9804BF21_INFO(inst) ((inst) + 0x00000028), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0029_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000029) +#define BF_BF_099B2AB5_INFO(inst) ((inst) + 0x00000029), 0x00000300 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X002A_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000002A) +#define BF_BF_C8EB6F3A_INFO(inst) ((inst) + 0x0000002A), 0x00000200 +#define BF_BF_E92E44A4_INFO(inst) ((inst) + 0x0000002A), 0x00000202 +#define BF_BF_132F4A77_INFO(inst) ((inst) + 0x0000002A), 0x00000204 +#define BF_BF_5C9D23E4_INFO(inst) ((inst) + 0x0000002A), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X002B_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000002B) +#define BF_BF_D67CE5B6_INFO(inst) ((inst) + 0x0000002B), 0x00000200 +#define BF_BF_2A35EF2C_INFO(inst) ((inst) + 0x0000002B), 0x00000202 +#define BF_BF_4AD20DF5_INFO(inst) ((inst) + 0x0000002B), 0x00000204 +#define BF_BF_4C32E642_INFO(inst) ((inst) + 0x0000002B), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X002C_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000002C) +#define BF_BF_DB0AFA1A_INFO(inst) ((inst) + 0x0000002C), 0x00000300 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X002D_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000002D) +#define BF_BF_D76B26F4_INFO(inst) ((inst) + 0x0000002D), 0x00000200 +#define BF_BF_48E4F2CA_INFO(inst) ((inst) + 0x0000002D), 0x00000202 +#define BF_BF_CFD1F7FB_INFO(inst) ((inst) + 0x0000002D), 0x00000204 +#define BF_BF_4324395D_INFO(inst) ((inst) + 0x0000002D), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X002E_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000002E) +#define BF_BF_521409C9_INFO(inst) ((inst) + 0x0000002E), 0x00000200 +#define BF_BF_7332F034_INFO(inst) ((inst) + 0x0000002E), 0x00000202 +#define BF_BF_FA0EEF3B_INFO(inst) ((inst) + 0x0000002E), 0x00000204 +#define BF_BF_3C853C06_INFO(inst) ((inst) + 0x0000002E), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X002F_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000002F) +#define BF_BF_6018961B_INFO(inst) ((inst) + 0x0000002F), 0x00000300 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0030_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000030) +#define BF_BF_CCFDED14_INFO(inst) ((inst) + 0x00000030), 0x00000200 +#define BF_BF_10C7489C_INFO(inst) ((inst) + 0x00000030), 0x00000202 +#define BF_BF_9C1ADB8C_INFO(inst) ((inst) + 0x00000030), 0x00000204 +#define BF_BF_C87D10FC_INFO(inst) ((inst) + 0x00000030), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0031_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000031) +#define BF_BF_18172696_INFO(inst) ((inst) + 0x00000031), 0x00000200 +#define BF_BF_2DFC91BB_INFO(inst) ((inst) + 0x00000031), 0x00000202 +#define BF_BF_8EB2FD62_INFO(inst) ((inst) + 0x00000031), 0x00000204 +#define BF_BF_CFFE1EE3_INFO(inst) ((inst) + 0x00000031), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0032_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000032) +#define BF_BF_1666C213_INFO(inst) ((inst) + 0x00000032), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0033_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000033) +#define BF_BF_2CCC2627_INFO(inst) ((inst) + 0x00000033), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0034_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000034) +#define BF_BF_EE79C5DA_INFO(inst) ((inst) + 0x00000034), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0035_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000035) +#define BF_BF_0002493D_INFO(inst) ((inst) + 0x00000035), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0036_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000036) +#define BF_BF_FBEFEBA4_INFO(inst) ((inst) + 0x00000036), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0037_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000037) +#define BF_BF_9C6FAD25_INFO(inst) ((inst) + 0x00000037), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0038_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000038) +#define BF_BF_ACCEBE08_INFO(inst) ((inst) + 0x00000038), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0039_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000039) +#define BF_BF_2A9AA610_INFO(inst) ((inst) + 0x00000039), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X003A_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000003A) +#define BF_BF_44A67BB6_INFO(inst) ((inst) + 0x0000003A), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X003B_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000003B) +#define BF_BF_513CF369_INFO(inst) ((inst) + 0x0000003B), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X003C_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000003C) +#define BF_BF_C4425C14_INFO(inst) ((inst) + 0x0000003C), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X003D_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000003D) +#define BF_BF_F1160BDC_INFO(inst) ((inst) + 0x0000003D), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X003E_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000003E) +#define BF_BF_38FF8611_INFO(inst) ((inst) + 0x0000003E), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X003F_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000003F) +#define BF_BF_0D88F8BD_INFO(inst) ((inst) + 0x0000003F), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0040_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000040) +#define BF_BF_A3AE5F94_INFO(inst) ((inst) + 0x00000040), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0041_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000041) +#define BF_BF_720B66B2_INFO(inst) ((inst) + 0x00000041), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0042_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000042) +#define BF_BF_1DC05849_INFO(inst) ((inst) + 0x00000042), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0043_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000043) +#define BF_BF_F3E48A9F_INFO(inst) ((inst) + 0x00000043), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0044_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000044) +#define BF_BF_9C72BF80_INFO(inst) ((inst) + 0x00000044), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0045_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000045) +#define BF_BF_371BC3D9_INFO(inst) ((inst) + 0x00000045), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0046_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000046) +#define BF_BF_84C7F523_INFO(inst) ((inst) + 0x00000046), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0047_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000047) +#define BF_BF_CDEC9799_INFO(inst) ((inst) + 0x00000047), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0048_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000048) +#define BF_BF_877C054C_INFO(inst) ((inst) + 0x00000048), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0049_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000049) +#define BF_BF_98B439B8_INFO(inst) ((inst) + 0x00000049), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X004A_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000004A) +#define BF_BF_0AF985D6_INFO(inst) ((inst) + 0x0000004A), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X004B_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000004B) +#define BF_BF_7D6985F5_INFO(inst) ((inst) + 0x0000004B), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X004C_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000004C) +#define BF_BF_45667D8B_INFO(inst) ((inst) + 0x0000004C), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X004D_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000004D) +#define BF_BF_7C4891D6_INFO(inst) ((inst) + 0x0000004D), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X004E_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000004E) +#define BF_BF_8A478BE8_INFO(inst) ((inst) + 0x0000004E), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X004F_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000004F) +#define BF_BF_C0757DBA_INFO(inst) ((inst) + 0x0000004F), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0050_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000050) +#define BF_BF_CF2E4B89_INFO(inst) ((inst) + 0x00000050), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0051_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000051) +#define BF_BF_DF0DE648_INFO(inst) ((inst) + 0x00000051), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0052_ADDR(inst) ((inst) + 0x00000052) +#define BF_BF_45A23508_INFO(inst) ((inst) + 0x00000052), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0053_ADDR(inst) ((inst) + 0x00000053) +#define BF_BF_8E333615_INFO(inst) ((inst) + 0x00000053), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0054_ADDR(inst) ((inst) + 0x00000054) +#define BF_BF_A3AE602E_INFO(inst) ((inst) + 0x00000054), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0055_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000055) +#define BF_BF_18C49AB2_INFO(inst) ((inst) + 0x00000055), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0056_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000056) +#define BF_BF_D9D08B8B_INFO(inst) ((inst) + 0x00000056), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0057_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000057) +#define BF_BF_87BA41E5_INFO(inst) ((inst) + 0x00000057), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0058_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000058) +#define BF_BF_30F4026F_INFO(inst) ((inst) + 0x00000058), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0059_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000059) +#define BF_BF_EB780239_INFO(inst) ((inst) + 0x00000059), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X005A_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000005A) +#define BF_BF_6D3A1240_INFO(inst) ((inst) + 0x0000005A), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X005B_ADDR(inst) ((inst) + 0x0000005B) +#define BF_BF_B5FBA87A_INFO(inst) ((inst) + 0x0000005B), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X005C_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000005C) +#define BF_BF_E4DB5572_INFO(inst) ((inst) + 0x0000005C), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X005D_ADDR(inst) ((inst) + 0x0000005D) +#define BF_BF_B944F982_INFO(inst) ((inst) + 0x0000005D), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X005E_ADDR(inst) ((inst) + 0x0000005E) +#define BF_BF_2F992B0E_INFO(inst) ((inst) + 0x0000005E), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X005F_ADDR(inst) ((inst) + 0x0000005F) +#define BF_BF_8A83AEB6_INFO(inst) ((inst) + 0x0000005F), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0060_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000060) +#define BF_BF_FB47E055_INFO(inst) ((inst) + 0x00000060), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0061_ADDR(inst) ((inst) + 0x00000061) +#define BF_BF_57432FC6_INFO(inst) ((inst) + 0x00000061), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0062_ADDR(inst) ((inst) + 0x00000062) +#define BF_BF_56B1DB56_INFO(inst) ((inst) + 0x00000062), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0063_ADDR(inst) ((inst) + 0x00000063) +#define BF_BF_9AA13BCE_INFO(inst) ((inst) + 0x00000063), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0064_ADDR(inst) ((inst) + 0x00000064) +#define BF_BF_2039935D_INFO(inst) ((inst) + 0x00000064), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0065_ADDR(inst) ((inst) + 0x00000065) +#define BF_BF_50F1DE26_INFO(inst) ((inst) + 0x00000065), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0066_ADDR(inst) ((inst) + 0x00000066) +#define BF_BF_CB662E54_INFO(inst) ((inst) + 0x00000066), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0067_ADDR(inst) ((inst) + 0x00000067) +#define BF_BF_0E763A37_INFO(inst) ((inst) + 0x00000067), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0068_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000068) +#define BF_BF_3FEEC273_INFO(inst) ((inst) + 0x00000068), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0069_ADDR(inst) ((inst) + 0x00000069) +#define BF_BF_086A4763_INFO(inst) ((inst) + 0x00000069), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X006A_ADDR(inst) ((inst) + 0x0000006A) +#define BF_BF_19843866_INFO(inst) ((inst) + 0x0000006A), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X006B_ADDR(inst) ((inst) + 0x0000006B) +#define BF_BF_790E7AE7_INFO(inst) ((inst) + 0x0000006B), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X006C_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000006C) +#define BF_BF_69F39416_INFO(inst) ((inst) + 0x0000006C), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X006D_ADDR(inst) ((inst) + 0x0000006D) +#define BF_BF_E48AF3BC_INFO(inst) ((inst) + 0x0000006D), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X006E_ADDR(inst) ((inst) + 0x0000006E) +#define BF_BF_9D8A7056_INFO(inst) ((inst) + 0x0000006E), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X006F_ADDR(inst) ((inst) + 0x0000006F) +#define BF_BF_12864FA1_INFO(inst) ((inst) + 0x0000006F), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0070_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000070) +#define BF_BF_11448D41_INFO(inst) ((inst) + 0x00000070), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0071_ADDR(inst) ((inst) + 0x00000071) +#define BF_BF_517DD066_INFO(inst) ((inst) + 0x00000071), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0072_ADDR(inst) ((inst) + 0x00000072) +#define BF_BF_BC7007B8_INFO(inst) ((inst) + 0x00000072), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0073_ADDR(inst) ((inst) + 0x00000073) +#define BF_BF_EB898B35_INFO(inst) ((inst) + 0x00000073), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0074_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000074) +#define BF_BF_FF956141_INFO(inst) ((inst) + 0x00000074), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0075_ADDR(inst) ((inst) + 0x00000075) +#define BF_BF_D1BA0CCB_INFO(inst) ((inst) + 0x00000075), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0076_ADDR(inst) ((inst) + 0x00000076) +#define BF_BF_02BBD37A_INFO(inst) ((inst) + 0x00000076), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0077_ADDR(inst) ((inst) + 0x00000077) +#define BF_BF_C87FADDB_INFO(inst) ((inst) + 0x00000077), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0078_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000078) +#define BF_BF_C2A6BCD8_INFO(inst) ((inst) + 0x00000078), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0079_ADDR(inst) ((inst) + 0x00000079) +#define BF_BF_D4872F4B_INFO(inst) ((inst) + 0x00000079), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X007A_ADDR(inst) ((inst) + 0x0000007A) +#define BF_BF_073C6954_INFO(inst) ((inst) + 0x0000007A), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X007B_ADDR(inst) ((inst) + 0x0000007B) +#define BF_BF_046EED1C_INFO(inst) ((inst) + 0x0000007B), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X007C_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000007C) +#define BF_BF_647183D2_INFO(inst) ((inst) + 0x0000007C), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X007D_ADDR(inst) ((inst) + 0x0000007D) +#define BF_BF_0D8767CB_INFO(inst) ((inst) + 0x0000007D), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X007E_ADDR(inst) ((inst) + 0x0000007E) +#define BF_BF_5FE84509_INFO(inst) ((inst) + 0x0000007E), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X007F_ADDR(inst) ((inst) + 0x0000007F) +#define BF_BF_E82F5E92_INFO(inst) ((inst) + 0x0000007F), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0080_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000080) +#define BF_BF_6E93EF47_INFO(inst) ((inst) + 0x00000080), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0081_ADDR(inst) ((inst) + 0x00000081) +#define BF_BF_05D9E50D_INFO(inst) ((inst) + 0x00000081), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0082_ADDR(inst) ((inst) + 0x00000082) +#define BF_BF_B1374F67_INFO(inst) ((inst) + 0x00000082), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0083_ADDR(inst) ((inst) + 0x00000083) +#define BF_BF_8BAD84AF_INFO(inst) ((inst) + 0x00000083), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0084_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000084) +#define BF_BF_EEAD6A06_INFO(inst) ((inst) + 0x00000084), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0085_ADDR(inst) ((inst) + 0x00000085) +#define BF_BF_73C53E6A_INFO(inst) ((inst) + 0x00000085), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0086_ADDR(inst) ((inst) + 0x00000086) +#define BF_BF_7274C1EB_INFO(inst) ((inst) + 0x00000086), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0087_ADDR(inst) ((inst) + 0x00000087) +#define BF_BF_CA5D8F53_INFO(inst) ((inst) + 0x00000087), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0088_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000088) +#define BF_BF_09F4E46B_INFO(inst) ((inst) + 0x00000088), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0089_ADDR(inst) ((inst) + 0x00000089) +#define BF_BF_885C1945_INFO(inst) ((inst) + 0x00000089), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X008A_ADDR(inst) ((inst) + 0x0000008A) +#define BF_BF_295F527C_INFO(inst) ((inst) + 0x0000008A), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X008B_ADDR(inst) ((inst) + 0x0000008B) +#define BF_BF_BF04B71C_INFO(inst) ((inst) + 0x0000008B), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X008C_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x0000008C) +#define BF_BF_99F14377_INFO(inst) ((inst) + 0x0000008C), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X008D_ADDR(inst) ((inst) + 0x0000008D) +#define BF_BF_C74E66B4_INFO(inst) ((inst) + 0x0000008D), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X008E_ADDR(inst) ((inst) + 0x0000008E) +#define BF_BF_3C6340B8_INFO(inst) ((inst) + 0x0000008E), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X008F_ADDR(inst) ((inst) + 0x0000008F) +#define BF_BF_53DD1D84_INFO(inst) ((inst) + 0x0000008F), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0090_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000090) +#define BF_BF_5E73B8BA_INFO(inst) ((inst) + 0x00000090), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0091_ADDR(inst) ((inst) + 0x00000091) +#define BF_BF_B349B5B8_INFO(inst) ((inst) + 0x00000091), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0092_ADDR(inst) ((inst) + 0x00000092) +#define BF_BF_3B4A412D_INFO(inst) ((inst) + 0x00000092), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0093_ADDR(inst) ((inst) + 0x00000093) +#define BF_BF_9FC2C086_INFO(inst) ((inst) + 0x00000093), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0094_ADDR(inst) ((inst) + 0x00000094) +#define BF_BF_F49FF642_INFO(inst) ((inst) + 0x00000094), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0095_ADDR(inst) ((inst) + 0x00000095) +#define BF_BF_7C28B2DB_INFO(inst) ((inst) + 0x00000095), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0096_ADDR(inst) ((inst) + 0x00000096) +#define BF_BF_891C0AF4_INFO(inst) ((inst) + 0x00000096), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0097_ADDR(inst) ((inst) + 0x00000097) +#define BF_BF_85A00C00_INFO(inst) ((inst) + 0x00000097), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0098_ADDR(inst) ((inst) + 0x00000098) +#define BF_BF_9DEA97A3_INFO(inst) ((inst) + 0x00000098), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0099_ADDR(inst) ((inst) + 0x00000099) +#define BF_BF_9179CBDC_INFO(inst) ((inst) + 0x00000099), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X009A_ADDR(inst) ((inst) + 0x0000009A) +#define BF_BF_084AB0D4_INFO(inst) ((inst) + 0x0000009A), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X009B_ADDR(inst) ((inst) + 0x0000009B) +#define BF_BF_CEA90E2F_INFO(inst) ((inst) + 0x0000009B), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X009C_ADDR(inst) ((inst) + 0x0000009C) +#define BF_BF_7C0582C2_INFO(inst) ((inst) + 0x0000009C), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X009D_ADDR(inst) ((inst) + 0x0000009D) +#define BF_BF_510A51D7_INFO(inst) ((inst) + 0x0000009D), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X009E_ADDR(inst) ((inst) + 0x0000009E) +#define BF_BF_61899914_INFO(inst) ((inst) + 0x0000009E), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X009F_ADDR(inst) ((inst) + 0x0000009F) +#define BF_BF_D80BF2DC_INFO(inst) ((inst) + 0x0000009F), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00A0_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x000000A0) +#define BF_BF_6BAA9B30_INFO(inst) ((inst) + 0x000000A0), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00A1_ADDR(inst) ((inst) + 0x000000A1) +#define BF_BF_93D6102A_INFO(inst) ((inst) + 0x000000A1), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00A2_ADDR(inst) ((inst) + 0x000000A2) +#define BF_BF_D075335A_INFO(inst) ((inst) + 0x000000A2), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00A3_ADDR(inst) ((inst) + 0x000000A3) +#define BF_BF_F6E7DE4A_INFO(inst) ((inst) + 0x000000A3), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00A4_ADDR(inst) ((inst) + 0x000000A4) +#define BF_BF_10B50A11_INFO(inst) ((inst) + 0x000000A4), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00A5_ADDR(inst) ((inst) + 0x000000A5) +#define BF_BF_D770280B_INFO(inst) ((inst) + 0x000000A5), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00A6_ADDR(inst) ((inst) + 0x000000A6) +#define BF_BF_2FAD0663_INFO(inst) ((inst) + 0x000000A6), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00A7_ADDR(inst) ((inst) + 0x000000A7) +#define BF_BF_B25984B4_INFO(inst) ((inst) + 0x000000A7), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00A8_ADDR(inst) ((inst) + 0x000000A8) +#define BF_BF_25A22373_INFO(inst) ((inst) + 0x000000A8), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00A9_ADDR(inst) ((inst) + 0x000000A9) +#define BF_BF_E479C47C_INFO(inst) ((inst) + 0x000000A9), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00AA_ADDR(inst) ((inst) + 0x000000AA) +#define BF_BF_4A70DE57_INFO(inst) ((inst) + 0x000000AA), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00AB_ADDR(inst) ((inst) + 0x000000AB) +#define BF_BF_7ED02D3E_INFO(inst) ((inst) + 0x000000AB), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00AC_ADDR(inst) ((inst) + 0x000000AC) +#define BF_BF_12192AC9_INFO(inst) ((inst) + 0x000000AC), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00AD_ADDR(inst) ((inst) + 0x000000AD) +#define BF_BF_CAE99163_INFO(inst) ((inst) + 0x000000AD), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00AE_ADDR(inst) ((inst) + 0x000000AE) +#define BF_BF_81A55DD0_INFO(inst) ((inst) + 0x000000AE), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00AF_ADDR(inst) ((inst) + 0x000000AF) +#define BF_BF_94E6D45F_INFO(inst) ((inst) + 0x000000AF), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00B0_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x000000B0) +#define BF_BF_83058D46_INFO(inst) ((inst) + 0x000000B0), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00B1_ADDR(inst) ((inst) + 0x000000B1) +#define BF_BF_16CE9612_INFO(inst) ((inst) + 0x000000B1), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00B2_ADDR(inst) ((inst) + 0x000000B2) +#define BF_BF_ED0889A8_INFO(inst) ((inst) + 0x000000B2), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00B3_ADDR(inst) ((inst) + 0x000000B3) +#define BF_BF_D367938A_INFO(inst) ((inst) + 0x000000B3), 0x00000100 +#define BF_BF_F7ACF82F_INFO(inst) ((inst) + 0x000000B3), 0x00000201 +#define BF_BF_CF062091_INFO(inst) ((inst) + 0x000000B3), 0x00000103 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00B4_ADDR(inst) ((inst) + 0x000000B4) +#define BF_BF_66506219_INFO(inst) ((inst) + 0x000000B4), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00B5_ADDR(inst) ((inst) + 0x000000B5) +#define BF_BF_4492BDA3_INFO(inst) ((inst) + 0x000000B5), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00B6_ADDR(inst) ((inst) + 0x000000B6) +#define BF_BF_C349D470_INFO(inst) ((inst) + 0x000000B6), 0x00000200 +#define BF_BF_0366BFB5_INFO(inst) ((inst) + 0x000000B6), 0x00000202 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00B7_ADDR(inst) ((inst) + 0x000000B7) +#define BF_BF_AA8AB79E_INFO(inst) ((inst) + 0x000000B7), 0x00000300 +#define BF_BF_1920D4A4_INFO(inst) ((inst) + 0x000000B7), 0x00000303 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00B8_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x000000B8) +#define BF_BF_8248D004_INFO(inst) ((inst) + 0x000000B8), 0x00000400 +#define BF_BF_5BDE2FD9_INFO(inst) ((inst) + 0x000000B8), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00B9_ADDR(inst) ((inst) + 0x000000B9) +#define BF_BF_D7A66B31_INFO(inst) ((inst) + 0x000000B9), 0x00000400 +#define BF_BF_355A9592_INFO(inst) ((inst) + 0x000000B9), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00BA_ADDR(inst) ((inst) + 0x000000BA) +#define BF_BF_5389AB66_INFO(inst) ((inst) + 0x000000BA), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00BB_ADDR(inst) ((inst) + 0x000000BB) +#define BF_BF_C44A20A3_INFO(inst) ((inst) + 0x000000BB), 0x00000300 +#define BF_BF_68BAE7CF_INFO(inst) ((inst) + 0x000000BB), 0x00000203 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00BD_ADDR(inst) ((inst) + 0x000000BD) +#define BF_BF_B7FD43BB_INFO(inst) ((inst) + 0x000000BD), 0x00000400 +#define BF_BF_E555E374_INFO(inst) ((inst) + 0x000000BD), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00BE_ADDR(inst) ((inst) + 0x000000BE) +#define BF_BF_E55709C4_INFO(inst) ((inst) + 0x000000BE), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00BF_ADDR(inst) ((inst) + 0x000000BF) +#define BF_BF_132BA678_INFO(inst) ((inst) + 0x000000BF), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00C0_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x000000C0) +#define BF_BF_1DAD5008_INFO(inst) ((inst) + 0x000000C0), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00C1_ADDR(inst) ((inst) + 0x000000C1) +#define BF_BF_5FD9B2E8_INFO(inst) ((inst) + 0x000000C1), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00C2_ADDR(inst) ((inst) + 0x000000C2) +#define BF_BF_BFB2117E_INFO(inst) ((inst) + 0x000000C2), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00C3_ADDR(inst) ((inst) + 0x000000C3) +#define BF_BF_B1629ECD_INFO(inst) ((inst) + 0x000000C3), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00C4_ADDR(inst) ((inst) + 0x000000C4) +#define BF_BF_6BFD9CFD_INFO(inst) ((inst) + 0x000000C4), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00C5_ADDR(inst) ((inst) + 0x000000C5) +#define BF_BF_D98634B9_INFO(inst) ((inst) + 0x000000C5), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00C6_ADDR(inst) ((inst) + 0x000000C6) +#define BF_BF_F787E919_INFO(inst) ((inst) + 0x000000C6), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00C7_ADDR(inst) ((inst) + 0x000000C7) +#define BF_BF_D1399BEC_INFO(inst) ((inst) + 0x000000C7), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00C8_ADDR(inst) ((inst) + 0x000000C8) +#define BF_BF_909D142E_INFO(inst) ((inst) + 0x000000C8), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00C9_ADDR(inst) ((inst) + 0x000000C9) +#define BF_BF_B31A327B_INFO(inst) ((inst) + 0x000000C9), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00CA_ADDR(inst) ((inst) + 0x000000CA) +#define BF_BF_A3DB5FD3_INFO(inst) ((inst) + 0x000000CA), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00CB_ADDR(inst) ((inst) + 0x000000CB) +#define BF_BF_992EF2F3_INFO(inst) ((inst) + 0x000000CB), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00CC_ADDR(inst) ((inst) + 0x000000CC) +#define BF_BF_2BCD10F0_INFO(inst) ((inst) + 0x000000CC), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00CD_ADDR(inst) ((inst) + 0x000000CD) +#define BF_BF_4443BFD9_INFO(inst) ((inst) + 0x000000CD), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00CE_ADDR(inst) ((inst) + 0x000000CE) +#define BF_BF_B38657ED_INFO(inst) ((inst) + 0x000000CE), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00CF_ADDR(inst) ((inst) + 0x000000CF) +#define BF_BF_1E4FE596_INFO(inst) ((inst) + 0x000000CF), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00D0_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x000000D0) +#define BF_BF_5B6F4662_INFO(inst) ((inst) + 0x000000D0), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00D1_ADDR(inst) ((inst) + 0x000000D1) +#define BF_BF_CBACE33F_INFO(inst) ((inst) + 0x000000D1), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00D2_ADDR(inst) ((inst) + 0x000000D2) +#define BF_BF_2C843ECB_INFO(inst) ((inst) + 0x000000D2), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00D3_ADDR(inst) ((inst) + 0x000000D3) +#define BF_BF_6DFE39E7_INFO(inst) ((inst) + 0x000000D3), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00D4_ADDR(inst) ((inst) + 0x000000D4) +#define BF_BF_478E6CBE_INFO(inst) ((inst) + 0x000000D4), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00D5_ADDR(inst) ((inst) + 0x000000D5) +#define BF_BF_7EC1D051_INFO(inst) ((inst) + 0x000000D5), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00D6_ADDR(inst) ((inst) + 0x000000D6) +#define BF_BF_36C3F722_INFO(inst) ((inst) + 0x000000D6), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00D7_ADDR(inst) ((inst) + 0x000000D7) +#define BF_BF_43D363AE_INFO(inst) ((inst) + 0x000000D7), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00D8_ADDR(inst) ((inst) + 0x000000D8) +#define BF_BF_438D6C2F_INFO(inst) ((inst) + 0x000000D8), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00D9_ADDR(inst) ((inst) + 0x000000D9) +#define BF_BF_F2993362_INFO(inst) ((inst) + 0x000000D9), 0x00000200 +#define BF_BF_B76A0C1C_INFO(inst) ((inst) + 0x000000D9), 0x00000204 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00DA_ADDR(inst) ((inst) + 0x000000DA) +#define BF_BF_246AC3B1_ACTRL_EAST__OPEN_INFO(inst) ((inst) + 0x000000DA), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00DB_ADDR(inst) ((inst) + 0x000000DB) +#define BF_BF_ECECD989_ACTRL_EAST__OPEN_INFO(inst) ((inst) + 0x000000DB), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00DC_ADDR(inst) ((inst) + 0x000000DC) +#define BF_BF_DA32E51D_ACTRL_EAST__OPEN_INFO(inst) ((inst) + 0x000000DC), 0x00000500 +#define BF_BF_CB8D6E7B_ACTRL_EAST__OPEN_INFO(inst) ((inst) + 0x000000DC), 0x00000305 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X00E0_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x000000E0) + +#define REG_REG_0X00E1_ADDR(inst) ((inst) + 0x000000E1) + +#define REG_REG_0X00E3_ADDR(inst) ((inst) + 0x000000E3) + +#define REG_REG_0X00E4_ADDR(inst) ((inst) + 0x000000E4) + +#define REG_REG_0X00E5_ADDR(inst) ((inst) + 0x000000E5) + +#define REG_REG_0X00E6_ADDR(inst) ((inst) + 0x000000E6) + +#define REG_REG_0X00E7_ADDR(inst) ((inst) + 0x000000E7) + +#define REG_REG_0X00E8_ADDR(inst) ((inst) + 0x000000E8) + +#define REG_REG_0X00E9_ADDR(inst) ((inst) + 0x000000E9) + +#define REG_REG_0X00EA_ADDR(inst) ((inst) + 0x000000EA) + +#define REG_REG_0X00EB_ADDR(inst) ((inst) + 0x000000EB) + +#define REG_REG_0X00EC_ADDR(inst) ((inst) + 0x000000EC) + +#define REG_REG_0X00ED_ADDR(inst) ((inst) + 0x000000ED) + +#define REG_REG_0X00EE_ADDR(inst) ((inst) + 0x000000EE) + +#define REG_REG_0X00EF_ADDR(inst) ((inst) + 0x000000EF) + +#define REG_REG_0X00F0_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x000000F0) + +#define REG_REG_0X00F1_ADDR(inst) ((inst) + 0x000000F1) + +#define REG_REG_0X00F2_ADDR(inst) ((inst) + 0x000000F2) + +#define REG_REG_0X00F3_ADDR(inst) ((inst) + 0x000000F3) + +#define REG_REG_0X00F4_ADDR(inst) ((inst) + 0x000000F4) + +#define REG_REG_0X00F5_ADDR(inst) ((inst) + 0x000000F5) + +#define REG_REG_0X00F6_ADDR(inst) ((inst) + 0x000000F6) + +#define REG_REG_0X00F7_ADDR(inst) ((inst) + 0x000000F7) + +#define REG_REG_0X00F8_ADDR(inst) ((inst) + 0x000000F8) + +#define REG_REG_0X00F9_ADDR(inst) ((inst) + 0x000000F9) + +#define REG_REG_0X00FA_ADDR(inst) ((inst) + 0x000000FA) + +#define REG_REG_0X00FB_ADDR(inst) ((inst) + 0x000000FB) + +#define REG_REG_0X00FC_ADDR(inst) ((inst) + 0x000000FC) + +#define REG_REG_0X00FD_ADDR(inst) ((inst) + 0x000000FD) + +#define REG_REG_0X00FE_ADDR(inst) ((inst) + 0x000000FE) + +#define REG_REG_0X00FF_ADDR(inst) ((inst) + 0x000000FF) + +#define REG_REG_0X0100_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x00000100) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0101_ADDR(inst) ((inst) + 0x00000101) +#define BF_BF_2BD68F04_ACTRL_EAST__OPEN_INFO(inst) ((inst) + 0x00000101), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0102_ADDR(inst) ((inst) + 0x00000102) +#define BF_BF_6F0E76C0_ACTRL_EAST__OPEN_INFO(inst) ((inst) + 0x00000102), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0103_ADDR(inst) ((inst) + 0x00000103) +#define BF_BF_1DECF0B5_ACTRL_EAST__OPEN_INFO(inst) ((inst) + 0x00000103), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0104_ADDR(inst) ((inst) + 0x00000104) +#define BF_BF_C5EBC8EF_ACTRL_EAST__OPEN_INFO(inst) ((inst) + 0x00000104), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0105_ADDR(inst) ((inst) + 0x00000105) +#define BF_BF_C9878C07_ACTRL_EAST__OPEN_INFO(inst) ((inst) + 0x00000105), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0106_ADDR(inst) ((inst) + 0x00000106) +#define BF_BF_A8BAEFD3_ACTRL_EAST__OPEN_INFO(inst) ((inst) + 0x00000106), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_ACTRL_SCRATCH_END_ACTRL_EAST__OPEN_ADDR(inst) ((inst) + 0x000003FF) +#define BF_ACTRL_SCRATCH_END_ACTRL_EAST__OPEN_INFO(inst) ((inst) + 0x000003FF), 0x00000800 + +#endif /* __ADI_APOLLO_BF_ACTRL_EAST_OPEN_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_actrl_slice_broadcast_open.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_actrl_slice_broadcast_open.h new file mode 100644 index 00000000000000..cbb8021deb8ae9 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_actrl_slice_broadcast_open.h @@ -0,0 +1,307 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:19 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_ACTRL_SLICE_BROADCAST_OPEN_H__ +#define __ADI_APOLLO_BF_ACTRL_SLICE_BROADCAST_OPEN_H__ + +/*============= D E F I N E S ==============*/ +#define VENUS_ACTRL_SLICE_BROADCAST_ADC8_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x60260000 +#define VENUS_ACTRL_SLICE_BROADCAST_ADC8_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x60460000 +#define VENUS_ACTRL_SLICE_BROADCAST_ADC8_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A60000 +#define VENUS_ACTRL_SLICE_BROADCAST_ADC8_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C60000 + +#define REG_ACTRL_SCRATCH_BEGIN_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000000) +#define BF_ACTRL_SCRATCH_BEGIN_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000000), 0x00000800 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0001_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000001) +#define BF_BF_5EB08FA9_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000001), 0x00000100 +#define BF_BF_126EB5D8_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000001), 0x00000101 +#define BF_BF_D1919DE4_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000001), 0x00000102 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0002_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000002) +#define BF_BF_A252E209_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000002), 0x00000100 +#define BF_BF_EC0570A1_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000002), 0x00000101 +#define BF_BF_9EC08343_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000002), 0x00000102 +#define BF_BF_DD32CEDB_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000002), 0x00000103 +#define BF_BF_889162C1_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000002), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0003_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000003) +#define BF_BF_A6D3CBFE_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000003), 0x00000101 +#define BF_BF_4018413E_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000003), 0x00000102 +#define BF_BF_2D63C129_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000003), 0x00000103 +#define BF_BF_339349E3_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000003), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0004_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000004) +#define BF_BF_AA4FF39E_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000004), 0x00000100 +#define BF_BF_001B22C8_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000004), 0x00000101 +#define BF_BF_2EAD4958_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000004), 0x00000102 +#define BF_BF_0CD0A002_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000004), 0x00000103 +#define BF_BF_458B15CA_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000004), 0x00000104 +#define BF_BF_99E768C7_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000004), 0x00000105 +#define BF_BF_09247BC9_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000004), 0x00000106 +#define BF_BF_D9B5E6DC_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000004), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0005_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000005) +#define BF_BF_4A1CE9FD_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000005), 0x00000100 +#define BF_BF_2FB6FEB1_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000005), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0006_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000006) +#define BF_BF_B1275EF4_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000006), 0x00000100 +#define BF_BF_2B4D955F_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000006), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0007_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000007) +#define BF_BF_D6F9511E_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000007), 0x00000100 +#define BF_BF_B2A878C7_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000007), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0008_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000008) +#define BF_BF_879E702A_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000008), 0x00000100 +#define BF_BF_EE1E3FD5_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000008), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0009_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000009) +#define BF_BF_9F65E970_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000009), 0x00000100 +#define BF_BF_9C76E371_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000009), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X000A_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000000A) +#define BF_BF_4B2ABE3F_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000000A), 0x00000100 +#define BF_BF_CA3810E7_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000000A), 0x00000101 +#define BF_BF_7BE4DF0B_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000000A), 0x00000102 +#define BF_BF_B950B3D9_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000000A), 0x00000103 +#define BF_BF_03899053_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000000A), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X000B_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000000B) +#define BF_BF_47AD4A09_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000000B), 0x00000400 +#define BF_BF_C278F62B_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000000B), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X000C_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000000C) +#define BF_BF_4AFC5970_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000000C), 0x00000400 +#define BF_BF_DC4BD305_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000000C), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X000D_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000000D) +#define BF_BF_AD50EA09_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000000D), 0x00000400 +#define BF_BF_6B9EF517_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000000D), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X000E_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000000E) +#define BF_BF_31AECD11_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000000E), 0x00000400 +#define BF_BF_7D3754EB_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000000E), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X000F_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000000F) +#define BF_BF_FE1DA073_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000000F), 0x00000400 +#define BF_BF_B5F7486C_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000000F), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0010_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000010) +#define BF_BF_B866A4AB_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000010), 0x00000100 +#define BF_BF_DE6A013F_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000010), 0x00000101 +#define BF_BF_FD8BEC76_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000010), 0x00000102 +#define BF_BF_E582A0EB_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000010), 0x00000103 +#define BF_BF_38088E6C_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000010), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0011_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000011) +#define BF_BF_5587D278_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000011), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0012_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000012) +#define BF_BF_F0273B9A_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000012), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0013_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000013) +#define BF_BF_954D455E_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000013), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0014_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000014) +#define BF_BF_E4A95397_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000014), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0015_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000015) +#define BF_BF_F908A4B7_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000015), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0016_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000016) +#define BF_BF_8DCABC6F_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000016), 0x00000200 +#define BF_BF_46B72E84_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000016), 0x00000202 +#define BF_BF_8AF0C451_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000016), 0x00000204 +#define BF_BF_FF501E2E_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000016), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0017_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000017) +#ifdef USE_PRIVATE_BF +#define BF_BF_77037A43_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000017), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_77037A43_WEB_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000017), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_DC5FC06D_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000017), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_DC5FC06D_WEB_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000017), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_6B686F5F_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000017), 0x00000304 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_6B686F5F_WEB_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000017), 0x00000107 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0018_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000018) +#define BF_BF_FE5D14F7_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000018), 0x00000100 +#define BF_BF_293203CE_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000018), 0x00000101 +#define BF_BF_1F8B49FB_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000018), 0x00000302 +#define BF_BF_BC94FEB9_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000018), 0x00000105 +#define BF_BF_4932BE36_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000018), 0x00000106 +#define BF_BF_15542900_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000018), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0019_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000019) +#define BF_BF_6E624734_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000019), 0x00000100 +#define BF_BF_3451B00C_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000019), 0x00000101 +#define BF_BF_11F6B22B_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000019), 0x00000302 +#define BF_BF_D74C5E45_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000019), 0x00000105 +#define BF_BF_85370402_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000019), 0x00000106 +#define BF_BF_4E3ABDB0_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000019), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X001A_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000001A) +#define BF_BF_DBD9054E_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000001A), 0x00000100 +#define BF_BF_8FEFCFA2_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000001A), 0x00000101 +#define BF_BF_E209801C_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000001A), 0x00000302 +#define BF_BF_22202CD7_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000001A), 0x00000105 +#define BF_BF_3D738581_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000001A), 0x00000106 +#define BF_BF_46D7DA69_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000001A), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X001B_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000001B) +#define BF_BF_6F58C319_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000001B), 0x00000100 +#define BF_BF_D436DB2D_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000001B), 0x00000101 +#define BF_BF_4F00CCC9_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000001B), 0x00000302 +#define BF_BF_87949627_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000001B), 0x00000105 +#define BF_BF_C86E3FED_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000001B), 0x00000106 +#define BF_BF_30A1F19E_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000001B), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X001C_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000001C) +#define BF_BF_A5738686_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000001C), 0x00002400 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X001D_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000001D) + +#define REG_REG_0X001E_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000001E) + +#define REG_REG_0X001F_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000001F) + +#define REG_REG_0X0020_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000020) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0021_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000021) +#define BF_BF_3A967583_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000021), 0x00000200 +#define BF_BF_55B25744_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000021), 0x00000202 +#define BF_BF_6F32B7D5_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000021), 0x00000204 +#define BF_BF_4F85E59F_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000021), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0022_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000022) +#define BF_BF_8B5D9414_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000022), 0x00000200 +#define BF_BF_891B6811_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000022), 0x00000202 +#define BF_BF_ECCF50C4_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000022), 0x00000204 +#define BF_BF_C32291CF_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000022), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0023_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000023) +#define BF_BF_7A13FD19_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000023), 0x00000200 +#define BF_BF_C5D1868C_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000023), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0024_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000024) +#define BF_BF_8701A65A_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000024), 0x00000200 +#define BF_BF_14DF43FB_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000024), 0x00000202 +#define BF_BF_C35798E6_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000024), 0x00000204 +#define BF_BF_455E4600_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000024), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0025_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000025) +#define BF_BF_1AD3C3B4_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000025), 0x00000200 +#define BF_BF_C13F473C_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000025), 0x00000202 +#define BF_BF_D167EABD_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000025), 0x00000204 +#define BF_BF_C8945FBC_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000025), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0026_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000026) +#define BF_BF_2BD68F04_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000026), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0027_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000027) +#define BF_BF_6F0E76C0_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000027), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0028_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000028) +#define BF_BF_1DECF0B5_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000028), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0029_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000029) +#define BF_BF_C5EBC8EF_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000029), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X002A_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000002A) + +#define REG_REG_0X002B_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000002B) + +#define REG_ACTRL_SCRATCH_END_ACTRL_SLICE__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000003FF) +#define BF_ACTRL_SCRATCH_END_ACTRL_SLICE__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000003FF), 0x00000800 + +#endif /* __ADI_APOLLO_BF_ACTRL_SLICE_BROADCAST_OPEN_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_actrl_slice_open.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_actrl_slice_open.h new file mode 100644 index 00000000000000..313e843ccc7a60 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_actrl_slice_open.h @@ -0,0 +1,341 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:19 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_ACTRL_SLICE_OPEN_H__ +#define __ADI_APOLLO_BF_ACTRL_SLICE_OPEN_H__ + +/*============= D E F I N E S ==============*/ +#define VENUS_ACTRL_SLICE_REGMAP0_ADC8_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x60260400 +#define VENUS_ACTRL_SLICE_REGMAP1_ADC8_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x60260800 +#define VENUS_ACTRL_SLICE_REGMAP2_ADC8_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x60260C00 +#define VENUS_ACTRL_SLICE_REGMAP3_ADC8_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x60261000 +#define VENUS_ACTRL_SLICE_REGMAP4_ADC8_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x60261400 +#define VENUS_ACTRL_SLICE_REGMAP5_ADC8_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x60261800 +#define VENUS_ACTRL_SLICE_REGMAP6_ADC8_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x60261C00 +#define VENUS_ACTRL_SLICE_REGMAP7_ADC8_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x60262000 +#define VENUS_ACTRL_SLICE_REGMAP0_ADC8_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x60460400 +#define VENUS_ACTRL_SLICE_REGMAP1_ADC8_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x60460800 +#define VENUS_ACTRL_SLICE_REGMAP2_ADC8_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x60460C00 +#define VENUS_ACTRL_SLICE_REGMAP3_ADC8_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x60461000 +#define VENUS_ACTRL_SLICE_REGMAP4_ADC8_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x60461400 +#define VENUS_ACTRL_SLICE_REGMAP5_ADC8_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x60461800 +#define VENUS_ACTRL_SLICE_REGMAP6_ADC8_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x60461C00 +#define VENUS_ACTRL_SLICE_REGMAP7_ADC8_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x60462000 +#define VENUS_ACTRL_SLICE_REGMAP0_ADC8_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A60400 +#define VENUS_ACTRL_SLICE_REGMAP1_ADC8_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A60800 +#define VENUS_ACTRL_SLICE_REGMAP2_ADC8_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A60C00 +#define VENUS_ACTRL_SLICE_REGMAP3_ADC8_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A61000 +#define VENUS_ACTRL_SLICE_REGMAP4_ADC8_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A61400 +#define VENUS_ACTRL_SLICE_REGMAP5_ADC8_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A61800 +#define VENUS_ACTRL_SLICE_REGMAP6_ADC8_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A61C00 +#define VENUS_ACTRL_SLICE_REGMAP7_ADC8_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A62000 +#define VENUS_ACTRL_SLICE_REGMAP0_ADC8_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C60400 +#define VENUS_ACTRL_SLICE_REGMAP1_ADC8_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C60800 +#define VENUS_ACTRL_SLICE_REGMAP2_ADC8_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C60C00 +#define VENUS_ACTRL_SLICE_REGMAP3_ADC8_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C61000 +#define VENUS_ACTRL_SLICE_REGMAP4_ADC8_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C61400 +#define VENUS_ACTRL_SLICE_REGMAP5_ADC8_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C61800 +#define VENUS_ACTRL_SLICE_REGMAP6_ADC8_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C61C00 +#define VENUS_ACTRL_SLICE_REGMAP7_ADC8_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C62000 + +#define REG_ACTRL_SCRATCH_BEGIN_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x00000000) +#define BF_ACTRL_SCRATCH_BEGIN_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000000), 0x00000800 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0001_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x00000001) +#define BF_BF_5EB08FA9_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000001), 0x00000100 +#define BF_BF_126EB5D8_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000001), 0x00000101 +#define BF_BF_D1919DE4_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000001), 0x00000102 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0002_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x00000002) +#define BF_BF_A252E209_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000002), 0x00000100 +#define BF_BF_EC0570A1_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000002), 0x00000101 +#define BF_BF_9EC08343_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000002), 0x00000102 +#define BF_BF_DD32CEDB_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000002), 0x00000103 +#define BF_BF_889162C1_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000002), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0003_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x00000003) +#define BF_BF_A6D3CBFE_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000003), 0x00000101 +#define BF_BF_4018413E_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000003), 0x00000102 +#define BF_BF_2D63C129_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000003), 0x00000103 +#define BF_BF_339349E3_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000003), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0004_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x00000004) +#define BF_BF_AA4FF39E_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000004), 0x00000100 +#define BF_BF_001B22C8_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000004), 0x00000101 +#define BF_BF_2EAD4958_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000004), 0x00000102 +#define BF_BF_0CD0A002_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000004), 0x00000103 +#define BF_BF_458B15CA_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000004), 0x00000104 +#define BF_BF_99E768C7_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000004), 0x00000105 +#define BF_BF_09247BC9_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000004), 0x00000106 +#define BF_BF_D9B5E6DC_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000004), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0005_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x00000005) +#define BF_BF_4A1CE9FD_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000005), 0x00000100 +#define BF_BF_2FB6FEB1_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000005), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0006_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x00000006) +#define BF_BF_B1275EF4_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000006), 0x00000100 +#define BF_BF_2B4D955F_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000006), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0007_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x00000007) +#define BF_BF_D6F9511E_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000007), 0x00000100 +#define BF_BF_B2A878C7_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000007), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0008_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x00000008) +#define BF_BF_879E702A_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000008), 0x00000100 +#define BF_BF_EE1E3FD5_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000008), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0009_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x00000009) +#define BF_BF_9F65E970_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000009), 0x00000100 +#define BF_BF_9C76E371_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000009), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X000A_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x0000000A) +#define BF_BF_4B2ABE3F_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x0000000A), 0x00000100 +#define BF_BF_CA3810E7_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x0000000A), 0x00000101 +#define BF_BF_7BE4DF0B_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x0000000A), 0x00000102 +#define BF_BF_B950B3D9_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x0000000A), 0x00000103 +#define BF_BF_03899053_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x0000000A), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X000B_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x0000000B) +#define BF_BF_47AD4A09_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x0000000B), 0x00000400 +#define BF_BF_C278F62B_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x0000000B), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X000C_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x0000000C) +#define BF_BF_4AFC5970_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x0000000C), 0x00000400 +#define BF_BF_DC4BD305_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x0000000C), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X000D_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x0000000D) +#define BF_BF_AD50EA09_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x0000000D), 0x00000400 +#define BF_BF_6B9EF517_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x0000000D), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X000E_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x0000000E) +#define BF_BF_31AECD11_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x0000000E), 0x00000400 +#define BF_BF_7D3754EB_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x0000000E), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X000F_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x0000000F) +#define BF_BF_FE1DA073_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x0000000F), 0x00000400 +#define BF_BF_B5F7486C_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x0000000F), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0010_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x00000010) +#define BF_BF_B866A4AB_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000010), 0x00000100 +#define BF_BF_DE6A013F_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000010), 0x00000101 +#define BF_BF_FD8BEC76_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000010), 0x00000102 +#define BF_BF_E582A0EB_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000010), 0x00000103 +#define BF_BF_38088E6C_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000010), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0011_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x00000011) +#define BF_BF_5587D278_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000011), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0012_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x00000012) +#define BF_BF_F0273B9A_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000012), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0013_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x00000013) +#define BF_BF_954D455E_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000013), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0014_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x00000014) +#define BF_BF_E4A95397_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000014), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0015_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x00000015) +#define BF_BF_F908A4B7_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000015), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0016_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x00000016) +#define BF_BF_8DCABC6F_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000016), 0x00000200 +#define BF_BF_46B72E84_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000016), 0x00000202 +#define BF_BF_8AF0C451_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000016), 0x00000204 +#define BF_BF_FF501E2E_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000016), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0017_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x00000017) +#ifdef USE_PRIVATE_BF +#define BF_BF_77037A43_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000017), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_77037A43_WEB_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000017), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_DC5FC06D_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000017), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_DC5FC06D_WEB_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000017), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_6B686F5F_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000017), 0x00000304 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_6B686F5F_WEB_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000017), 0x00000107 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0018_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x00000018) +#define BF_BF_FE5D14F7_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000018), 0x00000100 +#define BF_BF_293203CE_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000018), 0x00000101 +#define BF_BF_1F8B49FB_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000018), 0x00000302 +#define BF_BF_BC94FEB9_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000018), 0x00000105 +#define BF_BF_4932BE36_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000018), 0x00000106 +#define BF_BF_15542900_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000018), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0019_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x00000019) +#define BF_BF_6E624734_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000019), 0x00000100 +#define BF_BF_3451B00C_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000019), 0x00000101 +#define BF_BF_11F6B22B_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000019), 0x00000302 +#define BF_BF_D74C5E45_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000019), 0x00000105 +#define BF_BF_85370402_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000019), 0x00000106 +#define BF_BF_4E3ABDB0_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000019), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X001A_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x0000001A) +#define BF_BF_DBD9054E_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x0000001A), 0x00000100 +#define BF_BF_8FEFCFA2_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x0000001A), 0x00000101 +#define BF_BF_E209801C_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x0000001A), 0x00000302 +#define BF_BF_22202CD7_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x0000001A), 0x00000105 +#define BF_BF_3D738581_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x0000001A), 0x00000106 +#define BF_BF_46D7DA69_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x0000001A), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X001B_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x0000001B) +#define BF_BF_6F58C319_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x0000001B), 0x00000100 +#define BF_BF_D436DB2D_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x0000001B), 0x00000101 +#define BF_BF_4F00CCC9_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x0000001B), 0x00000302 +#define BF_BF_87949627_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x0000001B), 0x00000105 +#define BF_BF_C86E3FED_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x0000001B), 0x00000106 +#define BF_BF_30A1F19E_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x0000001B), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X001C_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x0000001C) +#define BF_BF_A5738686_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x0000001C), 0x00002400 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X001D_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x0000001D) + +#define REG_REG_0X001E_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x0000001E) + +#define REG_REG_0X001F_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x0000001F) + +#define REG_REG_0X0020_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x00000020) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0021_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x00000021) +#define BF_BF_3A967583_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000021), 0x00000200 +#define BF_BF_55B25744_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000021), 0x00000202 +#define BF_BF_6F32B7D5_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000021), 0x00000204 +#define BF_BF_4F85E59F_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000021), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0022_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x00000022) +#define BF_BF_8B5D9414_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000022), 0x00000200 +#define BF_BF_891B6811_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000022), 0x00000202 +#define BF_BF_ECCF50C4_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000022), 0x00000204 +#define BF_BF_C32291CF_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000022), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0023_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x00000023) +#define BF_BF_7A13FD19_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000023), 0x00000200 +#define BF_BF_C5D1868C_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000023), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0024_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x00000024) +#define BF_BF_8701A65A_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000024), 0x00000200 +#define BF_BF_14DF43FB_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000024), 0x00000202 +#define BF_BF_C35798E6_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000024), 0x00000204 +#define BF_BF_455E4600_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000024), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0025_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x00000025) +#define BF_BF_1AD3C3B4_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000025), 0x00000200 +#define BF_BF_C13F473C_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000025), 0x00000202 +#define BF_BF_D167EABD_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000025), 0x00000204 +#define BF_BF_C8945FBC_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000025), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0026_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x00000026) +#define BF_BF_2BD68F04_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000026), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0027_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x00000027) +#define BF_BF_6F0E76C0_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000027), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0028_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x00000028) +#define BF_BF_1DECF0B5_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000028), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0029_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x00000029) +#define BF_BF_C5EBC8EF_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x00000029), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X002A_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x0000002A) +#define BF_BF_C9878C07_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x0000002A), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X002B_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x0000002B) +#define BF_BF_A8BAEFD3_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x0000002B), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_ACTRL_SCRATCH_END_ACTRL_SLICE__OPEN_ADDR(inst) ((inst) + 0x000003FF) +#define BF_ACTRL_SCRATCH_END_ACTRL_SLICE__OPEN_INFO(inst) ((inst) + 0x000003FF), 0x00000800 + +#endif /* __ADI_APOLLO_BF_ACTRL_SLICE_OPEN_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_actrl_west_open.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_actrl_west_open.h new file mode 100644 index 00000000000000..7aad339ba02c57 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_actrl_west_open.h @@ -0,0 +1,408 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:19 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_ACTRL_WEST_OPEN_H__ +#define __ADI_APOLLO_BF_ACTRL_WEST_OPEN_H__ + +/*============= D E F I N E S ==============*/ +#define VENUS_ACTRL_WEST_REGMAP_ADC8_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x60262400 +#define VENUS_ACTRL_WEST_REGMAP_ADC8_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x60462400 +#define VENUS_ACTRL_WEST_REGMAP_ADC8_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A62400 +#define VENUS_ACTRL_WEST_REGMAP_ADC8_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C62400 + +#define REG_ACTRL_SCRATCH_BEGIN_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000000) +#define BF_ACTRL_SCRATCH_BEGIN_ACTRL_WEST__OPEN_INFO(inst) ((inst) + 0x00000000), 0x00000800 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0001_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000001) +#define BF_BF_4F891517_INFO(inst) ((inst) + 0x00000001), 0x00000100 +#define BF_BF_CAEB7B6D_INFO(inst) ((inst) + 0x00000001), 0x00000101 +#define BF_BF_B5E15A20_INFO(inst) ((inst) + 0x00000001), 0x00000102 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0002_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000002) +#define BF_BF_80682486_INFO(inst) ((inst) + 0x00000002), 0x00000100 +#define BF_BF_0CEA8917_INFO(inst) ((inst) + 0x00000002), 0x00000101 +#define BF_BF_CAA8A3A9_INFO(inst) ((inst) + 0x00000002), 0x00000102 +#define BF_BF_EF17F471_INFO(inst) ((inst) + 0x00000002), 0x00000103 +#define BF_BF_FB0A16E3_INFO(inst) ((inst) + 0x00000002), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0003_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000003) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0004_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000004) +#define BF_BF_D715BF87_INFO(inst) ((inst) + 0x00000004), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0005_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000005) +#define BF_BF_AF3E1E65_INFO(inst) ((inst) + 0x00000005), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0006_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000006) +#define BF_BF_5050CF8A_INFO(inst) ((inst) + 0x00000006), 0x00000100 +#define BF_BF_F92DEBA5_INFO(inst) ((inst) + 0x00000006), 0x00000101 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0007_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000007) +#define BF_BF_CBBB0A1D_INFO(inst) ((inst) + 0x00000007), 0x00000100 +#define BF_BF_0EC38FEC_INFO(inst) ((inst) + 0x00000007), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0008_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000008) +#define BF_BF_D6319B8F_INFO(inst) ((inst) + 0x00000008), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0009_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000009) +#define BF_BF_C151B9C1_INFO(inst) ((inst) + 0x00000009), 0x00000300 +#define BF_BF_785765B5_INFO(inst) ((inst) + 0x00000009), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X000A_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x0000000A) +#define BF_BF_F0EFD958_INFO(inst) ((inst) + 0x0000000A), 0x00000300 +#define BF_BF_3617B926_INFO(inst) ((inst) + 0x0000000A), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X000B_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x0000000B) +#define BF_BF_0827E611_INFO(inst) ((inst) + 0x0000000B), 0x00000300 +#define BF_BF_92C4A8D5_INFO(inst) ((inst) + 0x0000000B), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X000C_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x0000000C) +#define BF_BF_0CACD55E_INFO(inst) ((inst) + 0x0000000C), 0x00000300 +#define BF_BF_460694AB_INFO(inst) ((inst) + 0x0000000C), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X000D_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x0000000D) +#define BF_BF_585C1963_INFO(inst) ((inst) + 0x0000000D), 0x00000300 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X000E_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x0000000E) +#define BF_BF_16C1981F_INFO(inst) ((inst) + 0x0000000E), 0x00000200 +#define BF_BF_AC531167_INFO(inst) ((inst) + 0x0000000E), 0x00000202 +#define BF_BF_9FC9112E_INFO(inst) ((inst) + 0x0000000E), 0x00000204 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X000F_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x0000000F) +#define BF_BF_3E5198E9_INFO(inst) ((inst) + 0x0000000F), 0x00000300 +#define BF_BF_F7E42D50_INFO(inst) ((inst) + 0x0000000F), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0010_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000010) +#define BF_BF_57DBD614_INFO(inst) ((inst) + 0x00000010), 0x00000200 +#define BF_BF_6FA8186A_INFO(inst) ((inst) + 0x00000010), 0x00000204 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0011_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000011) +#define BF_BF_8BF62269_INFO(inst) ((inst) + 0x00000011), 0x00000500 +#define BF_BF_2BDB14F1_INFO(inst) ((inst) + 0x00000011), 0x00000105 +#define BF_BF_3038DD87_INFO(inst) ((inst) + 0x00000011), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0012_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000012) +#define BF_BF_71FC3AF9_INFO(inst) ((inst) + 0x00000012), 0x00000500 +#define BF_BF_AA7CEFFF_INFO(inst) ((inst) + 0x00000012), 0x00000105 +#define BF_BF_16BCA3C2_INFO(inst) ((inst) + 0x00000012), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0013_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000013) +#define BF_BF_899E4BBF_INFO(inst) ((inst) + 0x00000013), 0x00000300 +#define BF_BF_F3A4F067_INFO(inst) ((inst) + 0x00000013), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0014_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000014) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0015_ACTRL_WEST__OPEN_ADDR(inst, n) ((inst) + 0x00000015 + 1 * (n)) +#define BF_BF_4EB392BF_INFO(inst, n) ((inst) + 0x00000015 + 1 * (n)), 0x00000200 +#define BF_BF_D8B30366_INFO(inst, n) ((inst) + 0x00000015 + 1 * (n)), 0x00000202 +#define BF_BF_20CE60BB_INFO(inst, n) ((inst) + 0x00000015 + 1 * (n)), 0x00000204 +#define BF_BF_9203C058_INFO(inst, n) ((inst) + 0x00000015 + 1 * (n)), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X001D_ACTRL_WEST__OPEN_ADDR(inst, n) ((inst) + 0x0000001D + 1 * (n)) +#define BF_BF_4E03658F_INFO(inst, n) ((inst) + 0x0000001D + 1 * (n)), 0x00000200 +#define BF_BF_B1068A5B_INFO(inst, n) ((inst) + 0x0000001D + 1 * (n)), 0x00000202 +#define BF_BF_75F3304F_INFO(inst, n) ((inst) + 0x0000001D + 1 * (n)), 0x00000204 +#define BF_BF_2C2ED0CC_INFO(inst, n) ((inst) + 0x0000001D + 1 * (n)), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0025_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000025) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0026_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000026) +#define BF_BF_DC640D74_INFO(inst) ((inst) + 0x00000026), 0x00000300 +#define BF_BF_EC909415_INFO(inst) ((inst) + 0x00000026), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0027_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000027) +#define BF_BF_8BC429B9_INFO(inst) ((inst) + 0x00000027), 0x00000300 +#define BF_BF_17B15B87_INFO(inst) ((inst) + 0x00000027), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0028_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000028) +#define BF_BF_5AAF89C8_INFO(inst) ((inst) + 0x00000028), 0x00000300 +#define BF_BF_19109ACE_INFO(inst) ((inst) + 0x00000028), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0029_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000029) +#define BF_BF_8DF4690C_INFO(inst) ((inst) + 0x00000029), 0x00000300 +#define BF_BF_0FC925AE_INFO(inst) ((inst) + 0x00000029), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X002A_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x0000002A) +#define BF_BF_6F3D1EB2_INFO(inst) ((inst) + 0x0000002A), 0x00000300 +#define BF_BF_06BFDD4F_INFO(inst) ((inst) + 0x0000002A), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X002B_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x0000002B) +#define BF_BF_A748C638_INFO(inst) ((inst) + 0x0000002B), 0x00000300 +#define BF_BF_BEA5A3D9_INFO(inst) ((inst) + 0x0000002B), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X002C_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x0000002C) +#define BF_BF_3D67E04C_INFO(inst) ((inst) + 0x0000002C), 0x00000300 +#define BF_BF_53D60460_INFO(inst) ((inst) + 0x0000002C), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X002D_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x0000002D) +#define BF_BF_AF725B34_INFO(inst) ((inst) + 0x0000002D), 0x00000300 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X002E_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x0000002E) +#define BF_BF_3838C9C7_INFO(inst) ((inst) + 0x0000002E), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X002F_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x0000002F) +#define BF_BF_BC7ABCEF_INFO(inst) ((inst) + 0x0000002F), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0030_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000030) +#define BF_BF_5EDCE83D_INFO(inst) ((inst) + 0x00000030), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0031_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000031) +#define BF_BF_12A41045_INFO(inst) ((inst) + 0x00000031), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0032_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000032) +#define BF_BF_818EAAB9_INFO(inst) ((inst) + 0x00000032), 0x00000300 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0033_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000033) +#define BF_BF_D909CB45_INFO(inst) ((inst) + 0x00000033), 0x00000100 +#define BF_BF_9B37C1EE_INFO(inst) ((inst) + 0x00000033), 0x00000201 +#define BF_BF_EAD5C9CD_INFO(inst) ((inst) + 0x00000033), 0x00000103 +#define BF_BF_E751D2E0_INFO(inst) ((inst) + 0x00000033), 0x00000104 +#define BF_BF_85E41FBC_INFO(inst) ((inst) + 0x00000033), 0x00000105 +#define BF_BF_8113DC9C_INFO(inst) ((inst) + 0x00000033), 0x00000106 +#define BF_BF_C3E8EB1D_INFO(inst) ((inst) + 0x00000033), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0034_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000034) +#define BF_BF_6F17ED86_INFO(inst) ((inst) + 0x00000034), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0035_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000035) +#define BF_BF_831942C1_INFO(inst) ((inst) + 0x00000035), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0036_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000036) +#define BF_BF_4B0B8019_INFO(inst) ((inst) + 0x00000036), 0x00000300 +#define BF_BF_D3FA0DFF_INFO(inst) ((inst) + 0x00000036), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0037_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000037) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0038_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000038) +#define BF_BF_F2B9F109_INFO(inst) ((inst) + 0x00000038), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0039_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000039) +#define BF_BF_459ACF5C_INFO(inst) ((inst) + 0x00000039), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X003A_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x0000003A) +#define BF_BF_DA32E51D_ACTRL_WEST__OPEN_INFO(inst) ((inst) + 0x0000003A), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X003B_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x0000003B) +#define BF_BF_ECECD989_ACTRL_WEST__OPEN_INFO(inst) ((inst) + 0x0000003B), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X003C_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x0000003C) +#define BF_BF_246AC3B1_ACTRL_WEST__OPEN_INFO(inst) ((inst) + 0x0000003C), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X003D_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x0000003D) +#define BF_BF_CB8D6E7B_ACTRL_WEST__OPEN_INFO(inst) ((inst) + 0x0000003D), 0x00000300 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X003E_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x0000003E) +#define BF_BF_E71A6D16_INFO(inst) ((inst) + 0x0000003E), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X003F_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x0000003F) +#define BF_BF_5F1C3B7E_INFO(inst) ((inst) + 0x0000003F), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0040_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000040) +#define BF_BF_04557BC8_INFO(inst) ((inst) + 0x00000040), 0x00000300 +#define BF_BF_568AB02F_INFO(inst) ((inst) + 0x00000040), 0x00000303 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0041_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000041) +#define BF_BF_97907FC4_INFO(inst) ((inst) + 0x00000041), 0x00000300 +#define BF_BF_40FAEF21_INFO(inst) ((inst) + 0x00000041), 0x00000303 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0042_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000042) +#define BF_BF_6653AD72_INFO(inst) ((inst) + 0x00000042), 0x00000400 +#define BF_BF_F95A48BC_INFO(inst) ((inst) + 0x00000042), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0043_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000043) +#define BF_BF_85EDE74B_INFO(inst) ((inst) + 0x00000043), 0x00000300 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0044_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000044) + +#define REG_REG_0X0045_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000045) + +#define REG_REG_0X0046_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000046) + +#define REG_REG_0X0047_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000047) + +#define REG_REG_0X0048_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000048) + +#define REG_REG_0X0049_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000049) + +#define REG_REG_0X004A_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x0000004A) + +#define REG_REG_0X004B_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x0000004B) + +#define REG_REG_0X004C_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x0000004C) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X004D_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x0000004D) +#define BF_BF_6D240534_INFO(inst) ((inst) + 0x0000004D), 0x00000200 +#define BF_BF_30B90B4D_INFO(inst) ((inst) + 0x0000004D), 0x00000202 +#define BF_BF_F7942724_INFO(inst) ((inst) + 0x0000004D), 0x00000204 +#define BF_BF_CF92A541_INFO(inst) ((inst) + 0x0000004D), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X004E_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x0000004E) +#define BF_BF_8B25C9FE_INFO(inst) ((inst) + 0x0000004E), 0x00000400 +#define BF_BF_DF7E2BC6_INFO(inst) ((inst) + 0x0000004E), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X004F_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x0000004F) +#define BF_BF_AD94D2D6_INFO(inst) ((inst) + 0x0000004F), 0x00000400 +#define BF_BF_EBDB1917_INFO(inst) ((inst) + 0x0000004F), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0050_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000050) +#define BF_BF_80470963_INFO(inst) ((inst) + 0x00000050), 0x00000400 +#define BF_BF_9BC834E1_INFO(inst) ((inst) + 0x00000050), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0051_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000051) +#define BF_BF_E152813D_INFO(inst) ((inst) + 0x00000051), 0x00000400 +#define BF_BF_EDF345ED_INFO(inst) ((inst) + 0x00000051), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0055_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000055) +#define BF_BF_2BD68F04_ACTRL_WEST__OPEN_INFO(inst) ((inst) + 0x00000055), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0056_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000056) +#define BF_BF_6F0E76C0_ACTRL_WEST__OPEN_INFO(inst) ((inst) + 0x00000056), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0057_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000057) +#define BF_BF_1DECF0B5_ACTRL_WEST__OPEN_INFO(inst) ((inst) + 0x00000057), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0058_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000058) +#define BF_BF_C5EBC8EF_ACTRL_WEST__OPEN_INFO(inst) ((inst) + 0x00000058), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0059_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x00000059) +#define BF_BF_C9878C07_ACTRL_WEST__OPEN_INFO(inst) ((inst) + 0x00000059), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X005A_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x0000005A) +#define BF_BF_A8BAEFD3_ACTRL_WEST__OPEN_INFO(inst) ((inst) + 0x0000005A), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_ACTRL_SCRATCH_END_ACTRL_WEST__OPEN_ADDR(inst) ((inst) + 0x000003FF) +#define BF_ACTRL_SCRATCH_END_ACTRL_WEST__OPEN_INFO(inst) ((inst) + 0x000003FF), 0x00000800 + +#endif /* __ADI_APOLLO_BF_ACTRL_WEST_OPEN_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_ahb_arm_dap_regs.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_ahb_arm_dap_regs.h new file mode 100644 index 00000000000000..3b783502438b55 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_ahb_arm_dap_regs.h @@ -0,0 +1,33 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:17 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_AHB_ARM_DAP_REGS_H__ +#define __ADI_APOLLO_BF_AHB_ARM_DAP_REGS_H__ + +/*============= D E F I N E S ==============*/ +#define REG_IDCODE_ADDR 0x46810000 +#define BF_ID_CODE_INFO 0x46810000, 0x00002000 + +#define REG_CTRL_STAT_ADDR 0x46810004 +#define BF_ABORT_AHB_ARM_DAP_REGS_INFO 0x46810004, 0x00000100 +#define BF_DEBUG_POWER_UP_REQ_INFO 0x46810004, 0x0000011C +#define BF_DEBUG_POWER_UP_ACK_INFO 0x46810004, 0x0000011D +#define BF_SYSTEM_POWER_UP_REQ_INFO 0x46810004, 0x0000011E +#define BF_SYSTEM_POWER_UP_ACK_INFO 0x46810004, 0x0000011F + +#define REG_SELECT_ADDR 0x46810008 +#define BF_AP_BANKSEL_INFO 0x46810008, 0x00000404 + +#endif /* __ADI_APOLLO_BF_AHB_ARM_DAP_REGS_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_apollo_profile_config.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_apollo_profile_config.h new file mode 100644 index 00000000000000..e6037418118ac7 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_apollo_profile_config.h @@ -0,0 +1,135 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:21 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_APOLLO_PROFILE_CONFIG_H__ +#define __ADI_APOLLO_BF_APOLLO_PROFILE_CONFIG_H__ + +/*============= D E F I N E S ==============*/ +#define REG_PROFILE_FCN_SEL_REG_ADDR 0x4C004600 +#define BF_PROFILE_FCN_SEL_INFO 0x4C004600, 0x00000400 +#define BF_FCN_SEL_SPI_GPIO_INFO 0x4C004600, 0x00000104 + +#define REG_FNCO_SLICE_SELECT_REG_ADDR 0x4C004604 +#define BF_RX_FNCO_A_SLICE_SELECT_INFO 0x4C004604, 0x00000800 +#define BF_RX_FNCO_B_SLICE_SELECT_INFO 0x4C004604, 0x00000808 +#define BF_TX_FNCO_A_SLICE_SELECT_INFO 0x4C004604, 0x00000810 +#define BF_TX_FNCO_B_SLICE_SELECT_INFO 0x4C004604, 0x00000818 + +#define REG_CNCO_SLICE_SELECT_REG_ADDR 0x4C004608 +#define BF_RX_CNCO_A_SLICE_SELECT_INFO 0x4C004608, 0x00000400 +#define BF_RX_CNCO_B_SLICE_SELECT_INFO 0x4C004608, 0x00000404 +#define BF_TX_CNCO_A_SLICE_SELECT_INFO 0x4C004608, 0x00000408 +#define BF_TX_CNCO_B_SLICE_SELECT_INFO 0x4C004608, 0x0000040C + +#define REG_CFIR_SLICE_SELECT_REG_ADDR 0x4C00460C +#define BF_RX_CFIR_A_SLICE_SELECT_INFO 0x4C00460C, 0x00000800 +#define BF_RX_CFIR_B_SLICE_SELECT_INFO 0x4C00460C, 0x00000808 +#define BF_TX_CFIR_A_SLICE_SELECT_INFO 0x4C00460C, 0x00000810 +#define BF_TX_CFIR_B_SLICE_SELECT_INFO 0x4C00460C, 0x00000818 + +#define REG_PFILT_SLICE_SELECT_REG_ADDR 0x4C004610 +#define BF_RX_PFILT_A_SLICE_SELECT_INFO 0x4C004610, 0x00000100 +#define BF_RX_PFILT_B_SLICE_SELECT_INFO 0x4C004610, 0x00000101 +#define BF_TX_PFILT_A_SLICE_SELECT_INFO 0x4C004610, 0x00000102 +#define BF_TX_PFILT_B_SLICE_SELECT_INFO 0x4C004610, 0x00000103 + +#define REG_DYN_CONFIG_SLICE_SELECT_REG_ADDR 0x4C004614 +#define BF_RX_DYN_CONFIG_A_SLICE_SELECT_INFO 0x4C004614, 0x00000400 +#define BF_RX_DYN_CONFIG_B_SLICE_SELECT_INFO 0x4C004614, 0x00000404 +#define BF_TX_DYN_CONFIG_A_SLICE_SELECT_INFO 0x4C004614, 0x00000408 +#define BF_TX_DYN_CONFIG_B_SLICE_SELECT_INFO 0x4C004614, 0x0000040C + +#define REG_BMEM_HOP_SLICE_SELECT_REG_ADDR 0x4C004618 +#define BF_RX_BMEM_HOP_A_SLICE_SELECT_INFO 0x4C004618, 0x00000200 +#define BF_RX_BMEM_HOP_B_SLICE_SELECT_INFO 0x4C004618, 0x00000202 + +#define REG_FNCO_PFILT_SLICE_SELECT_REG_ADDR 0x4C00461C +#define BF_RX_FNCO_PFILT_A_SLICE_SELECT_INFO 0x4C00461C, 0x00000800 +#define BF_RX_FNCO_PFILT_B_SLICE_SELECT_INFO 0x4C00461C, 0x00000808 +#define BF_TX_FNCO_PFILT_A_SLICE_SELECT_INFO 0x4C00461C, 0x00000810 +#define BF_TX_FNCO_PFILT_B_SLICE_SELECT_INFO 0x4C00461C, 0x00000818 + +#define REG_FNCO_CFIR_SLICE_SELECT_REG_ADDR 0x4C004620 +#define BF_RX_FNCO_CFIR_A_SLICE_SELECT_INFO 0x4C004620, 0x00000800 +#define BF_RX_FNCO_CFIR_B_SLICE_SELECT_INFO 0x4C004620, 0x00000808 +#define BF_TX_FNCO_CFIR_A_SLICE_SELECT_INFO 0x4C004620, 0x00000810 +#define BF_TX_FNCO_CFIR_B_SLICE_SELECT_INFO 0x4C004620, 0x00000818 + +#define REG_FNCO_CNCO_SLICE_SELECT_REG_ADDR 0x4C004624 +#define BF_RX_FNCO_CNCO_A_SLICE_SELECT_INFO 0x4C004624, 0x00000800 +#define BF_RX_FNCO_CNCO_B_SLICE_SELECT_INFO 0x4C004624, 0x00000808 +#define BF_TX_FNCO_CNCO_A_SLICE_SELECT_INFO 0x4C004624, 0x00000810 +#define BF_TX_FNCO_CNCO_B_SLICE_SELECT_INFO 0x4C004624, 0x00000818 + +#define REG_PFILT_CFIR_SLICE_SELECT_REG_ADDR 0x4C004628 +#define BF_RX_PFILT_CFIR_A_SLICE_SELECT_INFO 0x4C004628, 0x00000800 +#define BF_RX_PFILT_CFIR_B_SLICE_SELECT_INFO 0x4C004628, 0x00000808 +#define BF_TX_PFILT_CFIR_A_SLICE_SELECT_INFO 0x4C004628, 0x00000810 +#define BF_TX_PFILT_CFIR_B_SLICE_SELECT_INFO 0x4C004628, 0x00000818 + +#define REG_CNCO_PFILT_SLICE_SELECT_REG_ADDR 0x4C00462C +#define BF_RX_CNCO_PFILT_A_SLICE_SELECT_INFO 0x4C00462C, 0x00000400 +#define BF_RX_CNCO_PFILT_B_SLICE_SELECT_INFO 0x4C00462C, 0x00000404 +#define BF_TX_CNCO_PFILT_A_SLICE_SELECT_INFO 0x4C00462C, 0x00000408 +#define BF_TX_CNCO_PFILT_B_SLICE_SELECT_INFO 0x4C00462C, 0x0000040C + +#define REG_COARSE_DYN_CONFIG_SLICE_SELECT_REG_ADDR 0x4C004630 +#define BF_RX_COARSE_DYN_CONFIG_A_SLICE_SELECT_INFO 0x4C004630, 0x00000200 +#define BF_RX_COARSE_DYN_CONFIG_B_SLICE_SELECT_INFO 0x4C004630, 0x00000202 +#define BF_TX_COARSE_DYN_CONFIG_A_SLICE_SELECT_INFO 0x4C004630, 0x00000204 +#define BF_TX_COARSE_DYN_CONFIG_B_SLICE_SELECT_INFO 0x4C004630, 0x00000206 + +#define REG_FNCO_CNCO_PROFILE_MAP_WORD0_ADDR 0x4C004634 + +#define REG_FNCO_CNCO_PROFILE_MAP_WORD1_ADDR 0x4C004638 + +#define REG_FNCO_CNCO_PROFILE_MAP_WORD2_ADDR 0x4C00463C + +#define REG_FNCO_CNCO_PROFILE_MAP_WORD3_ADDR 0x4C004640 + +#define REG_FNCO_PFILT_PROFILE_MAP_WORD0_ADDR 0x4C004644 +#define BF_FNCO_PFILT_PROFILE_MAP_INFO 0x4C004644, 0x00004000 + +#define REG_FNCO_PFILT_PROFILE_MAP_WORD1_ADDR 0x4C004648 + +#define REG_FNCO_CFIR_PROFILE_MAP_WORD0_ADDR 0x4C00464C +#define BF_FNCO_CFIR_PROFILE_MAP_INFO 0x4C00464C, 0x00002000 + +#define REG_PFILT_CFIR_PROFILE_MAP_WORD0_ADDR 0x4C004650 +#define BF_PFILT_CFIR_PROFILE_MAP_INFO 0x4C004650, 0x00000400 + +#define REG_CNCO_PFILT_PROFILE_MAP_WORD0_ADDR 0x4C004654 +#define BF_CNCO_PFILT_PROFILE_MAP_INFO 0x4C004654, 0x00002000 + +#define REG_SPI_GPIO_SELECT_REG_ADDR 0x4C004658 +#define BF_FNCO_SLICE_SELECT_SPI_GPIO_INFO 0x4C004658, 0x00000100 +#define BF_CNCO_SLICE_SELECT_SPI_GPIO_INFO 0x4C004658, 0x00000101 +#define BF_PFILT_SLICE_SELECT_SPI_GPIO_INFO 0x4C004658, 0x00000102 +#define BF_CFIR_SLICE_SELECT_SPI_GPIO_INFO 0x4C004658, 0x00000103 +#define BF_CNCO_PFILT_SLICE_SELECT_SPI_GPIO_INFO 0x4C004658, 0x00000104 +#define BF_PFILT_CFIR_SLICE_SELECT_SPI_GPIO_INFO 0x4C004658, 0x00000105 +#define BF_FNCO_CNCO_SLICE_SELECT_SPI_GPIO_INFO 0x4C004658, 0x00000106 +#define BF_FNCO_CFIR_SLICE_SELECT_SPI_GPIO_INFO 0x4C004658, 0x00000107 +#define BF_DYN_CONFIG_SLICE_SELECT_SPI_GPIO_INFO 0x4C004658, 0x00000108 +#define BF_FNCO_PFILT_SLICE_SELECT_SPI_GPIO_INFO 0x4C004658, 0x00000109 +#define BF_BMEM_HOP_SLICE_SELECT_SPI_GPIO_INFO 0x4C004658, 0x0000010A +#define BF_COARSE_DYN_CONFIG_SLICE_SELECT_SPI_GPIO_INFO 0x4C004658, 0x0000010B +#define BF_FNCO_CNCO_PROFILE_MAP_SPI_GPIO_INFO 0x4C004658, 0x0000010D +#define BF_FNCO_PFILT_PROFILE_MAP_SPI_GPIO_INFO 0x4C004658, 0x0000010E +#define BF_FNCO_CFIR_PROFILE_MAP_SPI_GPIO_INFO 0x4C004658, 0x0000010F +#define BF_PFILT_CFIR_PROFILE_MAP_SPI_GPIO_INFO 0x4C004658, 0x00000110 +#define BF_CNCO_PFILT_PROFILE_MAP_SPI_GPIO_INFO 0x4C004658, 0x00000111 + +#endif /* __ADI_APOLLO_BF_APOLLO_PROFILE_CONFIG_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_c2c_mailbox_dst.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_c2c_mailbox_dst.h new file mode 100644 index 00000000000000..6338a6ef59d443 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_c2c_mailbox_dst.h @@ -0,0 +1,43 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:17 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_C2C_MAILBOX_DST_H__ +#define __ADI_APOLLO_BF_C2C_MAILBOX_DST_H__ + +/*============= D E F I N E S ==============*/ +#define REG_ARM_CMD_1_C2C_MAILBOX_DST_ADDR 0x41800000 +#define BF_ARM_COMMAND_DST_INFO 0x41800000, 0x00003800 +#define BF_STALL_SRC_AHB_EN_DST_INFO 0x41800000, 0x0000011E +#define BF_ARM_COMMAND_BUSY_C2C_MAILBOX_DST_INFO 0x41800000, 0x0000011F + +#define REG_ARM_CMD_2_C2C_MAILBOX_DST_ADDR 0x41800004 + +#define REG_ARM_STATUS_1_C2C_MAILBOX_DST_ADDR 0x41800008 +#define BF_ARM_STATUS_DST_1_INFO 0x41800008, 0x00002000 + +#define REG_ARM_STATUS_2_C2C_MAILBOX_DST_ADDR 0x4180000C +#define BF_ARM_STATUS_DST_2_INFO 0x4180000C, 0x00001E00 +#define BF_STREAM_PROC_ARM_STATUS_C2C_MAILBOX_DST_INFO 0x4180000C, 0x0000021E + +#define REG_ARM_STATUS_3_C2C_MAILBOX_DST_ADDR 0x41800010 +#define BF_ARM_STATUS_DST_3_INFO 0x41800010, 0x00002000 + +#define REG_ARM_STATUS_4_C2C_MAILBOX_DST_ADDR 0x41800014 +#define BF_ARM_STATUS_DST_4_INFO 0x41800014, 0x00002000 + +#define REG_ARM_GPIO_VAL_C2C_MAILBOX_DST_ADDR 0x41800018 +#define BF_GPIO_VAL_DST_INFO 0x41800018, 0x00001000 + +#endif /* __ADI_APOLLO_BF_C2C_MAILBOX_DST_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_c2c_mailbox_src.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_c2c_mailbox_src.h new file mode 100644 index 00000000000000..544abe643a38e6 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_c2c_mailbox_src.h @@ -0,0 +1,43 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:17 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_C2C_MAILBOX_SRC_H__ +#define __ADI_APOLLO_BF_C2C_MAILBOX_SRC_H__ + +/*============= D E F I N E S ==============*/ +#define REG_ARM_CMD_1_C2C_MAILBOX_SRC_ADDR 0x41700000 +#define BF_ARM_COMMAND_SRC_INFO 0x41700000, 0x00003800 +#define BF_STALL_SRC_AHB_EN_SRC_INFO 0x41700000, 0x0000011E +#define BF_ARM_COMMAND_BUSY_C2C_MAILBOX_SRC_INFO 0x41700000, 0x0000011F + +#define REG_ARM_CMD_2_C2C_MAILBOX_SRC_ADDR 0x41700004 + +#define REG_ARM_STATUS_1_C2C_MAILBOX_SRC_ADDR 0x41700008 +#define BF_ARM_STATUS_SRC_1_INFO 0x41700008, 0x00002000 + +#define REG_ARM_STATUS_2_C2C_MAILBOX_SRC_ADDR 0x4170000C +#define BF_ARM_STATUS_SRC_2_INFO 0x4170000C, 0x00001E00 +#define BF_STREAM_PROC_ARM_STATUS_C2C_MAILBOX_SRC_INFO 0x4170000C, 0x0000021E + +#define REG_ARM_STATUS_3_C2C_MAILBOX_SRC_ADDR 0x41700010 +#define BF_ARM_STATUS_SRC_3_INFO 0x41700010, 0x00002000 + +#define REG_ARM_STATUS_4_C2C_MAILBOX_SRC_ADDR 0x41700014 +#define BF_ARM_STATUS_SRC_4_INFO 0x41700014, 0x00002000 + +#define REG_ARM_GPIO_VAL_C2C_MAILBOX_SRC_ADDR 0x41700018 +#define BF_GPIO_VAL_SRC_INFO 0x41700018, 0x00001000 + +#endif /* __ADI_APOLLO_BF_C2C_MAILBOX_SRC_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_cc_ss_ctrl.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_cc_ss_ctrl.h new file mode 100644 index 00000000000000..5aabc7afca7802 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_cc_ss_ctrl.h @@ -0,0 +1,115 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:20 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_CC_SS_CTRL_H__ +#define __ADI_APOLLO_BF_CC_SS_CTRL_H__ + +/*============= D E F I N E S ==============*/ +#define CC_SS_CTRL0_MCS_CC_SS0 0x4C001A00 +#define CC_SS_CTRL1_MCS_CC_SS0 0x4C001A20 +#define CC_SS_CTRL2_MCS_CC_SS0 0x4C001A40 +#define CC_SS_CTRL3_MCS_CC_SS0 0x4C001A60 +#define CC_SS_CTRL4_MCS_CC_SS0 0x4C001A80 +#define CC_SS_CTRL5_MCS_CC_SS0 0x4C001AA0 +#define CC_SS_CTRL6_MCS_CC_SS0 0x4C001AC0 +#define CC_SS_CTRL7_MCS_CC_SS0 0x4C001AE0 +#define CC_SS_CTRL0_MCS_CC_SS1 0x4C001E00 +#define CC_SS_CTRL1_MCS_CC_SS1 0x4C001E20 +#define CC_SS_CTRL2_MCS_CC_SS1 0x4C001E40 +#define CC_SS_CTRL3_MCS_CC_SS1 0x4C001E60 +#define CC_SS_CTRL4_MCS_CC_SS1 0x4C001E80 +#define CC_SS_CTRL5_MCS_CC_SS1 0x4C001EA0 +#define CC_SS_CTRL6_MCS_CC_SS1 0x4C001EC0 +#define CC_SS_CTRL7_MCS_CC_SS1 0x4C001EE0 + +#define REG_BUF_CTRL_ADDR(inst) ((inst) + 0x00000000) +#define BF_BUF_PUPB_INFO(inst) ((inst) + 0x00000000), 0x00000100 +#define BF_BUF_PDN_INFO(inst) ((inst) + 0x00000000), 0x00000101 +#define BF_BUF_SWITCH_EN_INFO(inst) ((inst) + 0x00000000), 0x00000102 +#define BF_BUF_VIN_INFO(inst) ((inst) + 0x00000000), 0x00000103 + +#define REG_CDAC_N_PDN_ADDR(inst) ((inst) + 0x00000001) +#define BF_CDAC_N_DRIFT_PUD_INFO(inst) ((inst) + 0x00000001), 0x00000400 + +#define REG_CDAC_N_PUPB_ADDR(inst) ((inst) + 0x00000002) +#define BF_CDAC_N_DRIFT_PUUB_INFO(inst) ((inst) + 0x00000002), 0x00000400 + +#define REG_CDAC_P_PDN_ADDR(inst) ((inst) + 0x00000003) +#define BF_CDAC_P_DRIFT_PUD_INFO(inst) ((inst) + 0x00000003), 0x00000400 + +#define REG_CDAC_P_PUPB_ADDR(inst) ((inst) + 0x00000004) +#define BF_CDAC_P_DRIFT_PUUB_INFO(inst) ((inst) + 0x00000004), 0x00000400 + +#define REG_RDAC_N_PDN0_ADDR(inst) ((inst) + 0x00000005) +#define BF_RDAC_N_DRIFT_PUD_INFO(inst) ((inst) + 0x00000005), 0x00001000 + +#define REG_RDAC_N_PDN1_ADDR(inst) ((inst) + 0x00000006) + +#define REG_RDAC_N_PDN2_ADDR(inst) ((inst) + 0x00000007) + +#define REG_RDAC_N_PDN3_ADDR(inst) ((inst) + 0x00000008) + +#define REG_RDAC_N_PUPB0_ADDR(inst) ((inst) + 0x00000009) +#define BF_RDAC_N_DRIFT_PUUB_INFO(inst) ((inst) + 0x00000009), 0x00001000 + +#define REG_RDAC_N_PUPB1_ADDR(inst) ((inst) + 0x0000000A) + +#define REG_RDAC_N_PUPB2_ADDR(inst) ((inst) + 0x0000000B) + +#define REG_RDAC_N_PUPB3_ADDR(inst) ((inst) + 0x0000000C) + +#define REG_RDAC_P_PDN0_ADDR(inst) ((inst) + 0x0000000D) +#define BF_RDAC_P_DRIFT_PUD_INFO(inst) ((inst) + 0x0000000D), 0x00001000 + +#define REG_RDAC_P_PDN1_ADDR(inst) ((inst) + 0x0000000E) + +#define REG_RDAC_P_PDN2_ADDR(inst) ((inst) + 0x0000000F) + +#define REG_RDAC_P_PDN3_ADDR(inst) ((inst) + 0x00000010) + +#define REG_RDAC_P_PUPB0_ADDR(inst) ((inst) + 0x00000011) +#define BF_RDAC_P_DRIFT_PUUB_INFO(inst) ((inst) + 0x00000011), 0x00001000 + +#define REG_RDAC_P_PUPB1_ADDR(inst) ((inst) + 0x00000012) + +#define REG_RDAC_P_PUPB2_ADDR(inst) ((inst) + 0x00000013) + +#define REG_RDAC_P_PUPB3_ADDR(inst) ((inst) + 0x00000014) + +#define REG_TNEN_CDAC_ADDR(inst) ((inst) + 0x00000015) +#define BF_TNEN_CDAC_INFO(inst) ((inst) + 0x00000015), 0x00000400 + +#define REG_TPEN_CDAC_ADDR(inst) ((inst) + 0x00000016) +#define BF_TPEN_CDAC_INFO(inst) ((inst) + 0x00000016), 0x00000400 + +#define REG_TNEN_RDAC0_ADDR(inst) ((inst) + 0x00000017) +#define BF_TNEN_RDAC_INFO(inst) ((inst) + 0x00000017), 0x00001000 + +#define REG_TNEN_RDAC1_ADDR(inst) ((inst) + 0x00000018) + +#define REG_TNEN_RDAC2_ADDR(inst) ((inst) + 0x00000019) + +#define REG_TNEN_RDAC3_ADDR(inst) ((inst) + 0x0000001A) + +#define REG_TPEN_RDAC0_ADDR(inst) ((inst) + 0x0000001B) +#define BF_TPEN_RDAC_INFO(inst) ((inst) + 0x0000001B), 0x00001000 + +#define REG_TPEN_RDAC1_ADDR(inst) ((inst) + 0x0000001C) + +#define REG_TPEN_RDAC2_ADDR(inst) ((inst) + 0x0000001D) + +#define REG_TPEN_RDAC3_ADDR(inst) ((inst) + 0x0000001E) + +#endif /* __ADI_APOLLO_BF_CC_SS_CTRL_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_conv_pow_onoff.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_conv_pow_onoff.h new file mode 100644 index 00000000000000..a6ebb38beea012 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_conv_pow_onoff.h @@ -0,0 +1,40 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:21 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_CONV_POW_ONOFF_H__ +#define __ADI_APOLLO_BF_CONV_POW_ONOFF_H__ + +/*============= D E F I N E S ==============*/ +#define REG_CONFIG_ADDR(n) (0x4C004000 + 1 * (n)) +#define BF_MUX_SELECT_INFO(n) (0x4C004000 + 1 * (n)), 0x00000500 +#define BF_COUNTER_BYPASS_EN_INFO(n) (0x4C004000 + 1 * (n)), 0x00000105 +#define BF_POWER_EN_MASK_INFO(n) (0x4C004000 + 1 * (n)), 0x00000106 +#define BF_TRIGGER_POLARITY_INVERT_INFO(n) (0x4C004000 + 1 * (n)), 0x00000107 + +#define REG_THRESH_HL_BYTE0_ADDR(n) (0x4C004010 + 3 * (n)) +#define BF_THRESH_HL_INFO(n) (0x4C004010 + 3 * (n)), 0x00001800 + +#define REG_THRESH_HL_BYTE1_ADDR(n) (0x4C004011 + 3 * (n)) + +#define REG_THRESH_HL_BYTE2_ADDR(n) (0x4C004012 + 3 * (n)) + +#define REG_THRESH_LH_BYTE0_ADDR(n) (0x4C004040 + 3 * (n)) +#define BF_THRESH_LH_INFO(n) (0x4C004040 + 3 * (n)), 0x00001800 + +#define REG_THRESH_LH_BYTE1_ADDR(n) (0x4C004041 + 3 * (n)) + +#define REG_THRESH_LH_BYTE2_ADDR(n) (0x4C004042 + 3 * (n)) + +#endif /* __ADI_APOLLO_BF_CONV_POW_ONOFF_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_core.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_core.h new file mode 100644 index 00000000000000..ba133b3d09b086 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_core.h @@ -0,0 +1,2361 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:17 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_CORE_H__ +#define __ADI_APOLLO_BF_CORE_H__ + +/*============= D E F I N E S ==============*/ +#ifdef USE_PRIVATE_BF +#define REG_SPI_IFACE_CONFIG_A_ADDR 0x47000000 +#define BF_SOFT_RESET_0_INFO 0x47000000, 0x00000100 +#define BF_LSB_FIRST_1_INFO 0x47000000, 0x00000101 +#define BF_ADDR_ASCENSION_2_INFO 0x47000000, 0x00000102 +#define BF_SDO_ACTIVE_3_INFO 0x47000000, 0x00000103 +#define BF_SDO_ACTIVE_4_INFO 0x47000000, 0x00000104 +#define BF_ADDR_ASCENSION_5_INFO 0x47000000, 0x00000105 +#define BF_LSB_FIRST_6_INFO 0x47000000, 0x00000106 +#define BF_SOFT_RESET_7_INFO 0x47000000, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_SPI_IFACE_CONFIG_B_ADDR 0x47000001 +#define BF_SOFT_RESET_001_1_INFO 0x47000001, 0x00000101 +#define BF_SOFT_RESET_001_2_INFO 0x47000001, 0x00000102 +#define BF_SLOW_IFACE_CTL_INFO 0x47000001, 0x00000104 +#define BF_MASTER_SLAVE_READBACK_CTL_INFO 0x47000001, 0x00000105 +#define BF_CSB_STALL_INFO 0x47000001, 0x00000106 +#define BF_SINGLE_INSTRUCTION_INFO 0x47000001, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_DEVICE_CONFIG_ADDR 0x47000002 +#define BF_DEVICE_CONFIG_OP_MODES_INFO 0x47000002, 0x00000200 +#define BF_DEVICE_CONFIG_CUSTOM_OP_MODES_INFO 0x47000002, 0x00000202 +#define BF_DEVICE_CONFIG_STATUS_INFO 0x47000002, 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#define REG_CHIP_TYPE_ADDR 0x47000003 +#define BF_CHIP_TYPE_INFO 0x47000003, 0x00000800 + +#define REG_PRODUCT_ID_0_ADDR 0x47000004 +#define BF_PRODUCT_ID_0_INFO 0x47000004, 0x00000800 + +#define REG_PRODUCT_ID_1_ADDR 0x47000005 +#define BF_PRODUCT_ID_1_INFO 0x47000005, 0x00000800 + +#define REG_CHIP_GRADE_ADDR 0x47000006 +#define BF_CHIP_GRADE_LOWER_NIBBLE_INFO 0x47000006, 0x00000400 +#define BF_CHIP_GRADE_UPPER_NIBBLE_INFO 0x47000006, 0x00000404 + +#ifdef USE_PRIVATE_BF +#define REG_DIE_ID_ADDR 0x47000007 +#define BF_MASK_REVISION_MINOR_INFO 0x47000007, 0x00000400 +#define BF_MASK_REVISION_MAJOR_INFO 0x47000007, 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_OFFSET_POINTER_DEVICE_INDEX_ADDR 0x47000008 +#define BF_PAGE_POINTER_DEVICE_INDEX_VALUE_0_INFO 0x47000008, 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_DEVICE_INDEX_ADDR 0x47000009 +#define BF_PAGE_POINTER_DEVICE_INDEX_VALUE_1_INFO 0x47000009, 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_SCRATCH_PAD_ADDR 0x4700000A +#define BF_SCRATCH_PAD_WORD_INFO 0x4700000A, 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_SPI_REVISION_ADDR 0x4700000B +#define BF_SPI_CONTROLLER_DOC_REVISION_INFO 0x4700000B, 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_VENDOR_ID_0_ADDR 0x4700000C +#define BF_VENDOR_ID_INFO 0x4700000C, 0x00001000 + +#define REG_VENDOR_ID_1_ADDR 0x4700000D + +#ifdef USE_PRIVATE_BF +#define REG_LAMINATE_ID_ADDR 0x4700000E +#define BF_LAMINATE_ID_INFO 0x4700000E, 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TRANSFER_REG_ADDR 0x4700000F +#define BF_MASTER_SLAVE_TRANSFER_BIT_INFO 0x4700000F, 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_SPI_FIFO_MODE_REG_ADDR 0x47000010 +#define BF_SPI_FIFO_MODE_INFO 0x47000010, 0x00000300 +#endif /* USE_PRIVATE_BF */ + +#define REG_FW_REV_RESERVED_ADDR 0x47000011 +#define BF_FW_REV_INFO 0x47000011, 0x00002000 + +#define REG_FW_REV_PATCH_ADDR 0x47000012 + +#define REG_FW_REV_MINOR_ADDR 0x47000013 + +#define REG_FW_REV_MAJOR_ADDR 0x47000014 + +#ifdef USE_PRIVATE_BF +#define REG_SPI1_ENABLE_ADDR 0x47000015 +#define BF_SPI1_EN_INFO 0x47000015, 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#define REG_CLOCK_CONTROL_0_ADDR 0x47000017 +#define BF_UP_RTCLK_DIV_CORE_INFO 0x47000017, 0x00000400 +#define BF_UP_RTCLK_DIV_UPDT_CORE_INFO 0x47000017, 0x00000104 +#ifdef USE_PRIVATE_BF +#define BF_ROSC_BACKUP_CLK_SELECT_INFO 0x47000017, 0x00000105 +#endif /* USE_PRIVATE_BF */ + +#define REG_CLOCK_CONTROL_1_ADDR 0x47000018 +#define BF_ASYNC_CLK_MUX_BYPASS_INFO 0x47000018, 0x00000100 +#ifdef USE_PRIVATE_BF +#define BF_DIG_REF_CLK_DIV_RATIO_INFO 0x47000018, 0x00000302 +#endif /* USE_PRIVATE_BF */ +#define BF_ROSC_CLK_DEBUG_DIV_RATIO_INFO 0x47000018, 0x00000205 + +#ifdef USE_PRIVATE_BF +#define REG_CLOCK_CONTROL_2_ADDR 0x47000019 +#define BF_DISABLE_HSDIGCLK_GATING_INFO 0x47000019, 0x00000105 +#define BF_DIGITAL_CLOCK_POWER_UP_INFO 0x47000019, 0x00000106 +#define BF_USE_DEVICE_CLK_AS_HSDIGCLK_INFO 0x47000019, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#define REG_OTP_CLK_CONTROL_ADDR 0x4700001B +#define BF_OTP_CLK_DIV_RATIO_INFO 0x4700001B, 0x00000600 +#define BF_OTP_CLK_ENABLE_INFO 0x4700001B, 0x00000106 + +#ifdef USE_PRIVATE_BF +#define REG_REFERENCE_CLOCK_CYCLES_ADDR 0x4700001C +#define BF_REFERENCE_CLOCK_CYCLES_CORE_INFO 0x4700001C, 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_TRACE_CLK_GEN_DIV_VAL_ADDR 0x4700001D +#define BF_TRACE_CLK_GEN_DIV_VAL_INFO 0x4700001D, 0x00000700 + +#ifdef USE_PRIVATE_BF +#define REG_AHB_SPI_BRIDGE_ADDR 0x4700001F +#define BF_AHB_SPI_BRIDGE_ENABLE_INFO 0x4700001F, 0x00000100 +#define BF_SPI_ARB_DISABLE_RESP_INFO 0x4700001F, 0x00000105 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARM0_CTL_ADDR 0x47000021 +#define BF_ARM0_M3_RUN_INFO 0x47000021, 0x00000100 +#define BF_ARM0_ERROR_INFO 0x47000021, 0x00000101 +#define BF_ARM0_MEM_HRESP_MASK_INFO 0x47000021, 0x00000103 +#define BF_ARM0_DEBUG_ENABLE_INFO 0x47000021, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARM0_RESET_ADDR 0x47000022 +#define BF_ARM0_FORCE_RESET_INFO 0x47000022, 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARM0_BOOT_ADDR_BYTE0_ADDR 0x47000023 +#define BF_ARM0_BOOT_ADDR_INFO 0x47000023, 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_ARM0_BOOT_ADDR_BYTE1_ADDR 0x47000024 + +#define REG_ARM0_BOOT_ADDR_BYTE2_ADDR 0x47000025 + +#define REG_ARM0_BOOT_ADDR_BYTE3_ADDR 0x47000026 + +#ifdef USE_PRIVATE_BF +#define REG_ARM0_STACK_PTR_BYTE_0_ADDR 0x47000027 +#define BF_ARM0_STACK_PTR_INFO 0x47000027, 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_ARM0_STACK_PTR_BYTE_1_ADDR 0x47000028 + +#define REG_ARM0_STACK_PTR_BYTE_2_ADDR 0x47000029 + +#define REG_ARM0_STACK_PTR_BYTE_3_ADDR 0x4700002A + +#ifdef USE_PRIVATE_BF +#define REG_L1MEM0_ECC_CONTROL_ADDR 0x4700003A +#define BF_L1MEM0_ECC_IRQ_SENSITIVITY_INFO 0x4700003A, 0x00000101 +#define BF_L1MEM0_ECC_MODE_INFO 0x4700003A, 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_L1MEM0_ECC_DATA_READBACK0_ADDR 0x4700003B +#define BF_L1MEM0_ECC_DATA_PARITY_INDEX_INFO 0x4700003B, 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#define REG_L1MEM0_ECC_DATA_READBACK1_ADDR 0x4700003C + +#ifdef USE_PRIVATE_BF +#define REG_L1MEM0_ECC_DATA_READBACK2_ADDR 0x4700003D +#define BF_L1MEM0_ECC_DATA_PARITY_TAG_INFO 0x4700003D, 0x00000D00 +#endif /* USE_PRIVATE_BF */ + +#define REG_L1MEM0_ECC_DATA_READBACK3_ADDR 0x4700003E + +#ifdef USE_PRIVATE_BF +#define REG_L1MEM0_ECC_DATA_READBACK4_ADDR 0x4700003F +#define BF_L1MEM0_ECC_DATA_PARITY_OUT_INFO 0x4700003F, 0x00000700 +#define BF_L1MEM0_ECC_DATA_PARITY_ERROR_INFO 0x4700003F, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_L1MEM0_ECC_DATA_READBACK5_ADDR 0x47000040 +#define BF_L1MEM0_ECC_DATA_PARITY_IN_INFO 0x47000040, 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_L1MEM0_ECC_DATA_READBACK6_ADDR 0x47000041 + +#define REG_L1MEM0_ECC_DATA_READBACK7_ADDR 0x47000042 + +#define REG_L1MEM0_ECC_DATA_READBACK8_ADDR 0x47000043 + +#ifdef USE_PRIVATE_BF +#define REG_L1MEM0_ECC_PROG_READBACK0_ADDR 0x47000044 +#define BF_L1MEM0_ECC_PROG_PARITY_INDEX_INFO 0x47000044, 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#define REG_L1MEM0_ECC_PROG_READBACK1_ADDR 0x47000045 + +#ifdef USE_PRIVATE_BF +#define REG_L1MEM0_ECC_PROG_READBACK2_ADDR 0x47000046 +#define BF_L1MEM0_ECC_PROG_PARITY_TAG_INFO 0x47000046, 0x00000D00 +#endif /* USE_PRIVATE_BF */ + +#define REG_L1MEM0_ECC_PROG_READBACK3_ADDR 0x47000047 + +#ifdef USE_PRIVATE_BF +#define REG_L1MEM0_ECC_PROG_READBACK4_ADDR 0x47000048 +#define BF_L1MEM0_ECC_PROG_PARITY_OUT_INFO 0x47000048, 0x00000700 +#define BF_L1MEM0_ECC_PROG_PARITY_ERROR_INFO 0x47000048, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_L1MEM0_ECC_PROG_READBACK5_ADDR 0x47000049 +#define BF_L1MEM0_ECC_PROG_PARITY_IN_INFO 0x47000049, 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_L1MEM0_ECC_PROG_READBACK6_ADDR 0x4700004A + +#define REG_L1MEM0_ECC_PROG_READBACK7_ADDR 0x4700004B + +#define REG_L1MEM0_ECC_PROG_READBACK8_ADDR 0x4700004C + +#ifdef USE_PRIVATE_BF +#define REG_L1MEM0_SHARED_BANK_DIV_CTRL_ADDR 0x4700004D +#define BF_L1MEM0_SHARED_BANK_DIV_INFO 0x4700004D, 0x00000300 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_SPIDMA0_CTL_ADDR 0x4700004F +#define BF_SPIDMA0_AHB_BUS_SELECT_INFO 0x4700004F, 0x00000100 +#define BF_SPIDMA0_AUTO_INCR_INFO 0x4700004F, 0x00000101 +#define BF_SPIDMA0_BUS_SIZE_INFO 0x4700004F, 0x00000202 +#define BF_SPIDMA0_BUS_RESPONSE_INFO 0x4700004F, 0x00000104 +#define BF_SPIDMA0_BUS_WAITING_INFO 0x4700004F, 0x00000105 +#define BF_SPIDMA0_SYS_CODEB_INFO 0x4700004F, 0x00000106 +#define BF_SPIDMA0_RD_WRB_INFO 0x4700004F, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#define REG_SPIDMA0_ADDR3_ADDR 0x47000050 + +#define REG_SPIDMA0_ADDR2_ADDR 0x47000051 + +#define REG_SPIDMA0_ADDR1_ADDR 0x47000052 + +#ifdef USE_PRIVATE_BF +#define REG_SPIDMA0_ADDR0_ADDR 0x47000053 +#define BF_SPIDMA0_BUS_ADDR_INFO 0x47000053, 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_SPIDMA0_DATA3_ADDR 0x47000054 + +#define REG_SPIDMA0_DATA2_ADDR 0x47000055 + +#define REG_SPIDMA0_DATA1_ADDR 0x47000056 + +#ifdef USE_PRIVATE_BF +#define REG_SPIDMA0_DATA0_ADDR 0x47000057 +#define BF_SPIDMA0_MEM_WRITE_DATA_INFO 0x47000057, 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_SPIDMA1_CTL_ADDR 0x47000059 +#define BF_SPIDMA1_AHB_BUS_SELECT_INFO 0x47000059, 0x00000100 +#define BF_SPIDMA1_AUTO_INCR_INFO 0x47000059, 0x00000101 +#define BF_SPIDMA1_BUS_SIZE_INFO 0x47000059, 0x00000202 +#define BF_SPIDMA1_BUS_RESPONSE_INFO 0x47000059, 0x00000104 +#define BF_SPIDMA1_BUS_WAITING_INFO 0x47000059, 0x00000105 +#define BF_SPIDMA1_SYS_CODEB_INFO 0x47000059, 0x00000106 +#define BF_SPIDMA1_RD_WRB_INFO 0x47000059, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#define REG_SPIDMA1_ADDR3_ADDR 0x4700005A + +#define REG_SPIDMA1_ADDR2_ADDR 0x4700005B + +#define REG_SPIDMA1_ADDR1_ADDR 0x4700005C + +#ifdef USE_PRIVATE_BF +#define REG_SPIDMA1_ADDR0_ADDR 0x4700005D +#define BF_SPIDMA1_BUS_ADDR_INFO 0x4700005D, 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_SPIDMA1_DATA3_ADDR 0x4700005E + +#define REG_SPIDMA1_DATA2_ADDR 0x4700005F + +#define REG_SPIDMA1_DATA1_ADDR 0x47000060 + +#ifdef USE_PRIVATE_BF +#define REG_SPIDMA1_DATA0_ADDR 0x47000061 +#define BF_SPIDMA1_MEM_WRITE_DATA_INFO 0x47000061, 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARM0_SPI0_COMMAND_ADDR 0x47000063 +#define BF_ARM0_SPI0_COMMAND_INFO 0x47000063, 0x00000600 +#define BF_ARM0_SPI0_COMMAND_BUSY_INFO 0x47000063, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARM0_SPI0_EXT_CMD_BYTE_1_ADDR 0x47000064 +#define BF_ARM0_SPI0_EXT_CMD_BYTE_1_INFO 0x47000064, 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARM0_SPI0_EXT_CMD_BYTE_2_ADDR 0x47000065 +#define BF_ARM0_SPI0_EXT_CMD_BYTE_2_INFO 0x47000065, 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARM0_SPI0_EXT_CMD_BYTE_3_ADDR 0x47000066 +#define BF_ARM0_SPI0_EXT_CMD_BYTE_3_INFO 0x47000066, 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARM0_SPI0_EXT_CMD_BYTE_4_ADDR 0x47000067 +#define BF_ARM0_SPI0_EXT_CMD_BYTE_4_INFO 0x47000067, 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARM0_SPI0_CMD_STATUS_0_ADDR 0x4700006B +#define BF_ARM0_SPI0_CMD_STATUS_DWL_INFO 0x4700006B, 0x00004000 +#endif /* USE_PRIVATE_BF */ + +#define REG_ARM0_SPI0_CMD_STATUS_1_ADDR 0x4700006C + +#define REG_ARM0_SPI0_CMD_STATUS_2_ADDR 0x4700006D + +#define REG_ARM0_SPI0_CMD_STATUS_3_ADDR 0x4700006E + +#define REG_ARM0_SPI0_CMD_STATUS_4_ADDR 0x4700006F + +#define REG_ARM0_SPI0_CMD_STATUS_5_ADDR 0x47000070 + +#define REG_ARM0_SPI0_CMD_STATUS_6_ADDR 0x47000071 + +#define REG_ARM0_SPI0_CMD_STATUS_7_ADDR 0x47000072 + +#ifdef USE_PRIVATE_BF +#define REG_ARM0_SPI0_CMD_STATUS_8_ADDR 0x47000073 +#define BF_ARM0_SPI0_CMD_STATUS_DWH_INFO 0x47000073, 0x00004000 +#endif /* USE_PRIVATE_BF */ + +#define REG_ARM0_SPI0_CMD_STATUS_9_ADDR 0x47000074 + +#define REG_ARM0_SPI0_CMD_STATUS_10_ADDR 0x47000075 + +#define REG_ARM0_SPI0_CMD_STATUS_11_ADDR 0x47000076 + +#define REG_ARM0_SPI0_CMD_STATUS_12_ADDR 0x47000077 + +#define REG_ARM0_SPI0_CMD_STATUS_13_ADDR 0x47000078 + +#define REG_ARM0_SPI0_CMD_STATUS_14_ADDR 0x47000079 + +#define REG_ARM0_SPI0_CMD_STATUS_15_ADDR 0x4700007A + +#ifdef USE_PRIVATE_BF +#define REG_ARM0_SPI1_COMMAND_ADDR 0x4700007C +#define BF_ARM0_SPI1_COMMAND_INFO 0x4700007C, 0x00000600 +#define BF_ARM0_SPI1_COMMAND_BUSY_INFO 0x4700007C, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARM0_SPI1_EXT_CMD_BYTE_1_ADDR 0x4700007D +#define BF_ARM0_SPI1_EXT_CMD_BYTE_1_INFO 0x4700007D, 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARM0_SPI1_EXT_CMD_BYTE_2_ADDR 0x4700007E +#define BF_ARM0_SPI1_EXT_CMD_BYTE_2_INFO 0x4700007E, 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARM0_SPI1_EXT_CMD_BYTE_3_ADDR 0x4700007F +#define BF_ARM0_SPI1_EXT_CMD_BYTE_3_INFO 0x4700007F, 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARM0_SPI1_EXT_CMD_BYTE_4_ADDR 0x47000080 +#define BF_ARM0_SPI1_EXT_CMD_BYTE_4_INFO 0x47000080, 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARM0_SPI1_CMD_STATUS_0_ADDR 0x47000084 +#define BF_ARM0_SPI1_CMD_STATUS_DWL_INFO 0x47000084, 0x00004000 +#endif /* USE_PRIVATE_BF */ + +#define REG_ARM0_SPI1_CMD_STATUS_1_ADDR 0x47000085 + +#define REG_ARM0_SPI1_CMD_STATUS_2_ADDR 0x47000086 + +#define REG_ARM0_SPI1_CMD_STATUS_3_ADDR 0x47000087 + +#define REG_ARM0_SPI1_CMD_STATUS_4_ADDR 0x47000088 + +#define REG_ARM0_SPI1_CMD_STATUS_5_ADDR 0x47000089 + +#define REG_ARM0_SPI1_CMD_STATUS_6_ADDR 0x4700008A + +#define REG_ARM0_SPI1_CMD_STATUS_7_ADDR 0x4700008B + +#ifdef USE_PRIVATE_BF +#define REG_ARM0_SPI1_CMD_STATUS_8_ADDR 0x4700008C +#define BF_ARM0_SPI1_CMD_STATUS_DWH_INFO 0x4700008C, 0x00004000 +#endif /* USE_PRIVATE_BF */ + +#define REG_ARM0_SPI1_CMD_STATUS_9_ADDR 0x4700008D + +#define REG_ARM0_SPI1_CMD_STATUS_10_ADDR 0x4700008E + +#define REG_ARM0_SPI1_CMD_STATUS_11_ADDR 0x4700008F + +#define REG_ARM0_SPI1_CMD_STATUS_12_ADDR 0x47000090 + +#define REG_ARM0_SPI1_CMD_STATUS_13_ADDR 0x47000091 + +#define REG_ARM0_SPI1_CMD_STATUS_14_ADDR 0x47000092 + +#define REG_ARM0_SPI1_CMD_STATUS_15_ADDR 0x47000093 + +#ifdef USE_PRIVATE_BF +#define REG_STREAM_CONTROL_ADDR 0x47000095 +#define BF_STREAM_RESET_CORE_INFO 0x47000095, 0x00000100 +#define BF_STREAM_BANK_SELECT_INFO 0x47000095, 0x00000305 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_STREAM_BASE_BYTE0_ADDR 0x47000096 +#define BF_STREAM_BASE_CORE_INFO 0x47000096, 0x00001000 +#endif /* USE_PRIVATE_BF */ + +#define REG_STREAM_BASE_BYTE1_ADDR 0x47000097 + +#ifdef USE_PRIVATE_BF +#define REG_LAST_STREAM_NUM_ADDR 0x47000098 +#define BF_LAST_STREAM_NUM_CORE_INFO 0x47000098, 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_COMPLETED_STREAM_NUMBER_ADDR 0x47000099 +#define BF_COMPLETED_STREAM_NUM_CORE_INFO 0x47000099, 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TX_EN_READBACK_ADDR 0x4700009A +#define BF_TX_ENABLE_READBACK_INFO 0x4700009A, 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_RX_EN_READBACK_ADDR 0x4700009B +#define BF_RX_ENABLE_READBACK_INFO 0x4700009B, 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ORX_EN_READBACK_ADDR 0x4700009C +#define BF_ORX_ENABLE_READBACK_INFO 0x4700009C, 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_PIN_MODE_STREAM_ERROR_TX_RISE_ADDR 0x4700009D +#define BF_TX0_RISE_STREAM_ERROR_INFO 0x4700009D, 0x00000100 +#define BF_TX1_RISE_STREAM_ERROR_INFO 0x4700009D, 0x00000101 +#define BF_TX2_RISE_STREAM_ERROR_INFO 0x4700009D, 0x00000102 +#define BF_TX3_RISE_STREAM_ERROR_INFO 0x4700009D, 0x00000103 +#define BF_TX4_RISE_STREAM_ERROR_INFO 0x4700009D, 0x00000104 +#define BF_TX5_RISE_STREAM_ERROR_INFO 0x4700009D, 0x00000105 +#define BF_TX6_RISE_STREAM_ERROR_INFO 0x4700009D, 0x00000106 +#define BF_TX7_RISE_STREAM_ERROR_INFO 0x4700009D, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_PIN_MODE_STREAM_ERROR_TX_FALL_ADDR 0x4700009F +#define BF_TX0_FALL_STREAM_ERROR_INFO 0x4700009F, 0x00000100 +#define BF_TX1_FALL_STREAM_ERROR_INFO 0x4700009F, 0x00000101 +#define BF_TX2_FALL_STREAM_ERROR_INFO 0x4700009F, 0x00000102 +#define BF_TX3_FALL_STREAM_ERROR_INFO 0x4700009F, 0x00000103 +#define BF_TX4_FALL_STREAM_ERROR_INFO 0x4700009F, 0x00000104 +#define BF_TX5_FALL_STREAM_ERROR_INFO 0x4700009F, 0x00000105 +#define BF_TX6_FALL_STREAM_ERROR_INFO 0x4700009F, 0x00000106 +#define BF_TX7_FALL_STREAM_ERROR_INFO 0x4700009F, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_PIN_MODE_STREAM_ERROR_ORX_RISE_FALL_ADDR 0x470000A1 +#define BF_ORX0_RISE_STREAM_ERROR_INFO 0x470000A1, 0x00000100 +#define BF_ORX1_RISE_STREAM_ERROR_INFO 0x470000A1, 0x00000101 +#define BF_ORX2_RISE_STREAM_ERROR_INFO 0x470000A1, 0x00000102 +#define BF_ORX3_RISE_STREAM_ERROR_INFO 0x470000A1, 0x00000103 +#define BF_ORX0_FALL_STREAM_ERROR_INFO 0x470000A1, 0x00000104 +#define BF_ORX1_FALL_STREAM_ERROR_INFO 0x470000A1, 0x00000105 +#define BF_ORX2_FALL_STREAM_ERROR_INFO 0x470000A1, 0x00000106 +#define BF_ORX3_FALL_STREAM_ERROR_INFO 0x470000A1, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_PIN_MODE_STREAM_ERROR_RX_RISE_ADDR 0x470000A2 +#define BF_RX0_RISE_STREAM_ERROR_INFO 0x470000A2, 0x00000100 +#define BF_RX1_RISE_STREAM_ERROR_INFO 0x470000A2, 0x00000101 +#define BF_RX2_RISE_STREAM_ERROR_INFO 0x470000A2, 0x00000102 +#define BF_RX3_RISE_STREAM_ERROR_INFO 0x470000A2, 0x00000103 +#define BF_RX4_RISE_STREAM_ERROR_INFO 0x470000A2, 0x00000104 +#define BF_RX5_RISE_STREAM_ERROR_INFO 0x470000A2, 0x00000105 +#define BF_RX6_RISE_STREAM_ERROR_INFO 0x470000A2, 0x00000106 +#define BF_RX7_RISE_STREAM_ERROR_INFO 0x470000A2, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_PIN_MODE_STREAM_ERROR_RX_FALL_ADDR 0x470000A4 +#define BF_RX0_FALL_STREAM_ERROR_INFO 0x470000A4, 0x00000100 +#define BF_RX1_FALL_STREAM_ERROR_INFO 0x470000A4, 0x00000101 +#define BF_RX2_FALL_STREAM_ERROR_INFO 0x470000A4, 0x00000102 +#define BF_RX3_FALL_STREAM_ERROR_INFO 0x470000A4, 0x00000103 +#define BF_RX4_FALL_STREAM_ERROR_INFO 0x470000A4, 0x00000104 +#define BF_RX5_FALL_STREAM_ERROR_INFO 0x470000A4, 0x00000105 +#define BF_RX6_FALL_STREAM_ERROR_INFO 0x470000A4, 0x00000106 +#define BF_RX7_FALL_STREAM_ERROR_INFO 0x470000A4, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ORX_LPBK_STREAM_ERROR_ADDR 0x470000A6 +#define BF_LPBK0_FALL_STREAM_ERROR_INFO 0x470000A6, 0x00000100 +#define BF_LPBK0_RISE_STREAM_ERROR_INFO 0x470000A6, 0x00000101 +#define BF_LPBK1_FALL_STREAM_ERROR_INFO 0x470000A6, 0x00000102 +#define BF_LPBK1_RISE_STREAM_ERROR_INFO 0x470000A6, 0x00000103 +#define BF_LPBK2_FALL_STREAM_ERROR_INFO 0x470000A6, 0x00000104 +#define BF_LPBK2_RISE_STREAM_ERROR_INFO 0x470000A6, 0x00000105 +#define BF_LPBK3_FALL_STREAM_ERROR_INFO 0x470000A6, 0x00000106 +#define BF_LPBK3_RISE_STREAM_ERROR_INFO 0x470000A6, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#define REG_STREAM_DFRM_IRQ_MASK_ADDR 0x470000A7 +#define BF_DFRM_IRQ_MASK_INFO 0x470000A7, 0x00000200 +#define BF_NEW_SYSREF_PHASE_IRQ_MASK_INFO 0x470000A7, 0x00000104 + +#ifdef USE_PRIVATE_BF +#define REG_STREAM_SPI_REG_MASK_WRITE_STATUS_ADDR 0x470000A8 +#define BF_SPI_REG_MASK_WRITE_STREAM_STATUS_INFO 0x470000A8, 0x00000100 +#define BF_SPI_REG_MASK_WRITE_STREAM_ERROR_INFO 0x470000A8, 0x00000101 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_STREAM_GPIO_STATUS_ADDR 0x470000A9 +#define BF_STREAM_GPIO0_STATUS_INFO 0x470000A9, 0x00000100 +#define BF_STREAM_GPIO1_STATUS_INFO 0x470000A9, 0x00000101 +#define BF_STREAM_GPIO2_STATUS_INFO 0x470000A9, 0x00000102 +#define BF_STREAM_GPIO3_STATUS_INFO 0x470000A9, 0x00000103 +#define BF_STREAM_GPIO4_STATUS_INFO 0x470000A9, 0x00000104 +#define BF_STREAM_GPIO5_STATUS_INFO 0x470000A9, 0x00000105 +#define BF_STREAM_GPIO6_STATUS_INFO 0x470000A9, 0x00000106 +#define BF_STREAM_GPIO7_STATUS_INFO 0x470000A9, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_STREAM_GPIO_ERROR_ADDR 0x470000AA +#define BF_STREAM_GPIO0_RISE_ERROR_INFO 0x470000AA, 0x00000100 +#define BF_STREAM_GPIO1_RISE_ERROR_INFO 0x470000AA, 0x00000101 +#define BF_STREAM_GPIO2_RISE_ERROR_INFO 0x470000AA, 0x00000102 +#define BF_STREAM_GPIO3_RISE_ERROR_INFO 0x470000AA, 0x00000103 +#define BF_STREAM_GPIO0_FALL_ERROR_INFO 0x470000AA, 0x00000104 +#define BF_STREAM_GPIO1_FALL_ERROR_INFO 0x470000AA, 0x00000105 +#define BF_STREAM_GPIO2_FALL_ERROR_INFO 0x470000AA, 0x00000106 +#define BF_STREAM_GPIO3_FALL_ERROR_INFO 0x470000AA, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_STREAM_GPIO_ERROR1_ADDR 0x470000AB +#define BF_STREAM_GPIO4_RISE_ERROR_INFO 0x470000AB, 0x00000100 +#define BF_STREAM_GPIO5_RISE_ERROR_INFO 0x470000AB, 0x00000101 +#define BF_STREAM_GPIO6_RISE_ERROR_INFO 0x470000AB, 0x00000102 +#define BF_STREAM_GPIO7_RISE_ERROR_INFO 0x470000AB, 0x00000103 +#define BF_STREAM_GPIO4_FALL_ERROR_INFO 0x470000AB, 0x00000104 +#define BF_STREAM_GPIO5_FALL_ERROR_INFO 0x470000AB, 0x00000105 +#define BF_STREAM_GPIO6_FALL_ERROR_INFO 0x470000AB, 0x00000106 +#define BF_STREAM_GPIO7_FALL_ERROR_INFO 0x470000AB, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_STREAM_GPIO_ERROR2_ADDR 0x470000AC +#define BF_STREAM_GPIO8_RISE_ERROR_INFO 0x470000AC, 0x00000100 +#define BF_STREAM_GPIO9_RISE_ERROR_INFO 0x470000AC, 0x00000101 +#define BF_STREAM_GPIO10_RISE_ERROR_INFO 0x470000AC, 0x00000102 +#define BF_STREAM_GPIO11_RISE_ERROR_INFO 0x470000AC, 0x00000103 +#define BF_STREAM_GPIO8_FALL_ERROR_INFO 0x470000AC, 0x00000104 +#define BF_STREAM_GPIO9_FALL_ERROR_INFO 0x470000AC, 0x00000105 +#define BF_STREAM_GPIO10_FALL_ERROR_INFO 0x470000AC, 0x00000106 +#define BF_STREAM_GPIO11_FALL_ERROR_INFO 0x470000AC, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_STREAM_GPIO_ERROR3_ADDR 0x470000AD +#define BF_STREAM_GPIO12_RISE_ERROR_INFO 0x470000AD, 0x00000100 +#define BF_STREAM_GPIO13_RISE_ERROR_INFO 0x470000AD, 0x00000101 +#define BF_STREAM_GPIO14_RISE_ERROR_INFO 0x470000AD, 0x00000102 +#define BF_STREAM_GPIO15_RISE_ERROR_INFO 0x470000AD, 0x00000103 +#define BF_STREAM_GPIO12_FALL_ERROR_INFO 0x470000AD, 0x00000104 +#define BF_STREAM_GPIO13_FALL_ERROR_INFO 0x470000AD, 0x00000105 +#define BF_STREAM_GPIO14_FALL_ERROR_INFO 0x470000AD, 0x00000106 +#define BF_STREAM_GPIO15_FALL_ERROR_INFO 0x470000AD, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_STREAM_GPIO_ERROR4_ADDR 0x470000AE +#define BF_STREAM_GPIO16_RISE_ERROR_INFO 0x470000AE, 0x00000100 +#define BF_STREAM_GPIO17_RISE_ERROR_INFO 0x470000AE, 0x00000101 +#define BF_STREAM_GPIO18_RISE_ERROR_INFO 0x470000AE, 0x00000102 +#define BF_STREAM_GPIO19_RISE_ERROR_INFO 0x470000AE, 0x00000103 +#define BF_STREAM_GPIO16_FALL_ERROR_INFO 0x470000AE, 0x00000104 +#define BF_STREAM_GPIO17_FALL_ERROR_INFO 0x470000AE, 0x00000105 +#define BF_STREAM_GPIO18_FALL_ERROR_INFO 0x470000AE, 0x00000106 +#define BF_STREAM_GPIO19_FALL_ERROR_INFO 0x470000AE, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_STREAM_GPIO_ERROR5_ADDR 0x470000AF +#define BF_STREAM_GPIO20_RISE_ERROR_INFO 0x470000AF, 0x00000100 +#define BF_STREAM_GPIO21_RISE_ERROR_INFO 0x470000AF, 0x00000101 +#define BF_STREAM_GPIO22_RISE_ERROR_INFO 0x470000AF, 0x00000102 +#define BF_STREAM_GPIO23_RISE_ERROR_INFO 0x470000AF, 0x00000103 +#define BF_STREAM_GPIO20_FALL_ERROR_INFO 0x470000AF, 0x00000104 +#define BF_STREAM_GPIO21_FALL_ERROR_INFO 0x470000AF, 0x00000105 +#define BF_STREAM_GPIO22_FALL_ERROR_INFO 0x470000AF, 0x00000106 +#define BF_STREAM_GPIO23_FALL_ERROR_INFO 0x470000AF, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_STREAM_ORX_SWITCH_ERROR_ADDR 0x470000B0 +#define BF_ORX0LOW_TO_ORX1HIGH_STREAM_ERROR_INFO 0x470000B0, 0x00000100 +#define BF_ORX1LOW_TO_ORX0HIGH_STREAM_ERROR_INFO 0x470000B0, 0x00000101 +#define BF_ORX2LOW_TO_ORX3HIGH_STREAM_ERROR_INFO 0x470000B0, 0x00000102 +#define BF_ORX3LOW_TO_ORX2HIGH_STREAM_ERROR_INFO 0x470000B0, 0x00000103 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_STREAM_PROC_READBACK_ADDR_ADDR 0x470000B1 +#define BF_STREAM_PROC_ADDR_CORE_INFO 0x470000B1, 0x00000400 +#define BF_STREAM_PROC_RDEN_CORE_INFO 0x470000B1, 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_STREAM_PROC_READBACK_DATA0_ADDR 0x470000B2 +#define BF_STREAM_PROC_DATA_CORE_INFO 0x470000B2, 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_STREAM_PROC_READBACK_DATA1_ADDR 0x470000B3 + +#define REG_STREAM_PROC_READBACK_DATA2_ADDR 0x470000B4 + +#define REG_STREAM_PROC_READBACK_DATA3_ADDR 0x470000B5 + +#ifdef USE_PRIVATE_BF +#define REG_STREAM_PROC_ERROR_ADDR 0x470000B6 +#define BF_STREAM_ERROR_CORE_INFO 0x470000B6, 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_STREAM_PROC_SPI_RMW_ADDRESS_LSB_ADDR 0x470000B7 +#define BF_SPI_RMW_ADDRESS_INFO 0x470000B7, 0x00000F00 +#endif /* USE_PRIVATE_BF */ + +#define REG_STREAM_PROC_SPI_RMW_ADDRESS_MSB_ADDR 0x470000B8 + +#ifdef USE_PRIVATE_BF +#define REG_STREAM_PROC_SPI_RMW_MASK_ADDR 0x470000B9 +#define BF_SPI_RMW_MASK_INFO 0x470000B9, 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_STREAM_PROC_SPI_RMW_DATA_ADDR 0x470000BA +#define BF_SPI_RMW_DATA_INFO 0x470000BA, 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_STREAM_GPIO_STATUS2_ADDR 0x470000BB +#define BF_STREAM_GPIO8_STATUS_INFO 0x470000BB, 0x00000100 +#define BF_STREAM_GPIO9_STATUS_INFO 0x470000BB, 0x00000101 +#define BF_STREAM_GPIO10_STATUS_INFO 0x470000BB, 0x00000102 +#define BF_STREAM_GPIO11_STATUS_INFO 0x470000BB, 0x00000103 +#define BF_STREAM_GPIO12_STATUS_INFO 0x470000BB, 0x00000104 +#define BF_STREAM_GPIO13_STATUS_INFO 0x470000BB, 0x00000105 +#define BF_STREAM_GPIO14_STATUS_INFO 0x470000BB, 0x00000106 +#define BF_STREAM_GPIO15_STATUS_INFO 0x470000BB, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_STREAM_GPIO_STATUS3_ADDR 0x470000BC +#define BF_STREAM_GPIO16_STATUS_INFO 0x470000BC, 0x00000100 +#define BF_STREAM_GPIO17_STATUS_INFO 0x470000BC, 0x00000101 +#define BF_STREAM_GPIO18_STATUS_INFO 0x470000BC, 0x00000102 +#define BF_STREAM_GPIO19_STATUS_INFO 0x470000BC, 0x00000103 +#define BF_STREAM_GPIO20_STATUS_INFO 0x470000BC, 0x00000104 +#define BF_STREAM_GPIO21_STATUS_INFO 0x470000BC, 0x00000105 +#define BF_STREAM_GPIO22_STATUS_INFO 0x470000BC, 0x00000106 +#define BF_STREAM_GPIO23_STATUS_INFO 0x470000BC, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARM1_CTL_ADDR 0x470000C6 +#define BF_ARM1_M3_RUN_INFO 0x470000C6, 0x00000100 +#define BF_ARM1_ERROR_INFO 0x470000C6, 0x00000101 +#define BF_ARM1_MEM_HRESP_MASK_INFO 0x470000C6, 0x00000103 +#define BF_ARM1_DEBUG_ENABLE_INFO 0x470000C6, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARM1_RESET_ADDR 0x470000C7 +#define BF_ARM1_FORCE_RESET_INFO 0x470000C7, 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARM1_BOOT_ADDR_BYTE0_ADDR 0x470000C8 +#define BF_ARM1_BOOT_ADDR_INFO 0x470000C8, 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_ARM1_BOOT_ADDR_BYTE1_ADDR 0x470000C9 + +#define REG_ARM1_BOOT_ADDR_BYTE2_ADDR 0x470000CA + +#define REG_ARM1_BOOT_ADDR_BYTE3_ADDR 0x470000CB + +#ifdef USE_PRIVATE_BF +#define REG_ARM1_STACK_PTR_BYTE_0_ADDR 0x470000CC +#define BF_ARM1_STACK_PTR_INFO 0x470000CC, 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_ARM1_STACK_PTR_BYTE_1_ADDR 0x470000CD + +#define REG_ARM1_STACK_PTR_BYTE_2_ADDR 0x470000CE + +#define REG_ARM1_STACK_PTR_BYTE_3_ADDR 0x470000CF + +#ifdef USE_PRIVATE_BF +#define REG_L1MEM1_ECC_CONTROL_ADDR 0x470000DF +#define BF_L1MEM1_ECC_IRQ_SENSITIVITY_INFO 0x470000DF, 0x00000101 +#define BF_L1MEM1_ECC_MODE_INFO 0x470000DF, 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_L1MEM1_ECC_DATA_READBACK0_ADDR 0x470000E0 +#define BF_L1MEM1_ECC_DATA_PARITY_INDEX_INFO 0x470000E0, 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#define REG_L1MEM1_ECC_DATA_READBACK1_ADDR 0x470000E1 + +#ifdef USE_PRIVATE_BF +#define REG_L1MEM1_ECC_DATA_READBACK2_ADDR 0x470000E2 +#define BF_L1MEM1_ECC_DATA_PARITY_TAG_INFO 0x470000E2, 0x00000D00 +#endif /* USE_PRIVATE_BF */ + +#define REG_L1MEM1_ECC_DATA_READBACK3_ADDR 0x470000E3 + +#ifdef USE_PRIVATE_BF +#define REG_L1MEM1_ECC_DATA_READBACK4_ADDR 0x470000E4 +#define BF_L1MEM1_ECC_DATA_PARITY_OUT_INFO 0x470000E4, 0x00000700 +#define BF_L1MEM1_ECC_DATA_PARITY_ERROR_INFO 0x470000E4, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_L1MEM1_ECC_DATA_READBACK5_ADDR 0x470000E5 +#define BF_L1MEM1_ECC_DATA_PARITY_IN_INFO 0x470000E5, 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_L1MEM1_ECC_DATA_READBACK6_ADDR 0x470000E6 + +#define REG_L1MEM1_ECC_DATA_READBACK7_ADDR 0x470000E7 + +#define REG_L1MEM1_ECC_DATA_READBACK8_ADDR 0x470000E8 + +#ifdef USE_PRIVATE_BF +#define REG_L1MEM1_ECC_PROG_READBACK0_ADDR 0x470000E9 +#define BF_L1MEM1_ECC_PROG_PARITY_INDEX_INFO 0x470000E9, 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#define REG_L1MEM1_ECC_PROG_READBACK1_ADDR 0x470000EA + +#ifdef USE_PRIVATE_BF +#define REG_L1MEM1_ECC_PROG_READBACK2_ADDR 0x470000EB +#define BF_L1MEM1_ECC_PROG_PARITY_TAG_INFO 0x470000EB, 0x00000D00 +#endif /* USE_PRIVATE_BF */ + +#define REG_L1MEM1_ECC_PROG_READBACK3_ADDR 0x470000EC + +#ifdef USE_PRIVATE_BF +#define REG_L1MEM1_ECC_PROG_READBACK4_ADDR 0x470000ED +#define BF_L1MEM1_ECC_PROG_PARITY_OUT_INFO 0x470000ED, 0x00000700 +#define BF_L1MEM1_ECC_PROG_PARITY_ERROR_INFO 0x470000ED, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_L1MEM1_ECC_PROG_READBACK5_ADDR 0x470000EE +#define BF_L1MEM1_ECC_PROG_PARITY_IN_INFO 0x470000EE, 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_L1MEM1_ECC_PROG_READBACK6_ADDR 0x470000EF + +#define REG_L1MEM1_ECC_PROG_READBACK7_ADDR 0x470000F0 + +#define REG_L1MEM1_ECC_PROG_READBACK8_ADDR 0x470000F1 + +#ifdef USE_PRIVATE_BF +#define REG_L1MEM1_SHARED_BANK_DIV_CTRL_ADDR 0x470000F2 +#define BF_L1MEM1_SHARED_BANK_DIV_INFO 0x470000F2, 0x00000300 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARM1_SPI0_COMMAND_ADDR 0x470000F4 +#define BF_ARM1_SPI0_COMMAND_INFO 0x470000F4, 0x00000600 +#define BF_ARM1_SPI0_COMMAND_BUSY_INFO 0x470000F4, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARM1_SPI0_EXT_CMD_BYTE_1_ADDR 0x470000F5 +#define BF_ARM1_SPI0_EXT_CMD_BYTE_1_INFO 0x470000F5, 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARM1_SPI0_EXT_CMD_BYTE_2_ADDR 0x470000F6 +#define BF_ARM1_SPI0_EXT_CMD_BYTE_2_INFO 0x470000F6, 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARM1_SPI0_EXT_CMD_BYTE_3_ADDR 0x470000F7 +#define BF_ARM1_SPI0_EXT_CMD_BYTE_3_INFO 0x470000F7, 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARM1_SPI0_EXT_CMD_BYTE_4_ADDR 0x470000F8 +#define BF_ARM1_SPI0_EXT_CMD_BYTE_4_INFO 0x470000F8, 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARM1_SPI0_CMD_STATUS_0_ADDR 0x470000FC +#define BF_ARM1_SPI0_CMD_STATUS_DWL_INFO 0x470000FC, 0x00004000 +#endif /* USE_PRIVATE_BF */ + +#define REG_ARM1_SPI0_CMD_STATUS_1_ADDR 0x470000FD + +#define REG_ARM1_SPI0_CMD_STATUS_2_ADDR 0x470000FE + +#define REG_ARM1_SPI0_CMD_STATUS_3_ADDR 0x470000FF + +#define REG_ARM1_SPI0_CMD_STATUS_4_ADDR 0x47000100 + +#define REG_ARM1_SPI0_CMD_STATUS_5_ADDR 0x47000101 + +#define REG_ARM1_SPI0_CMD_STATUS_6_ADDR 0x47000102 + +#define REG_ARM1_SPI0_CMD_STATUS_7_ADDR 0x47000103 + +#ifdef USE_PRIVATE_BF +#define REG_ARM1_SPI0_CMD_STATUS_8_ADDR 0x47000104 +#define BF_ARM1_SPI0_CMD_STATUS_DWH_INFO 0x47000104, 0x00004000 +#endif /* USE_PRIVATE_BF */ + +#define REG_ARM1_SPI0_CMD_STATUS_9_ADDR 0x47000105 + +#define REG_ARM1_SPI0_CMD_STATUS_10_ADDR 0x47000106 + +#define REG_ARM1_SPI0_CMD_STATUS_11_ADDR 0x47000107 + +#define REG_ARM1_SPI0_CMD_STATUS_12_ADDR 0x47000108 + +#define REG_ARM1_SPI0_CMD_STATUS_13_ADDR 0x47000109 + +#define REG_ARM1_SPI0_CMD_STATUS_14_ADDR 0x4700010A + +#define REG_ARM1_SPI0_CMD_STATUS_15_ADDR 0x4700010B + +#ifdef USE_PRIVATE_BF +#define REG_ARM1_SPI1_COMMAND_ADDR 0x4700010D +#define BF_ARM1_SPI1_COMMAND_INFO 0x4700010D, 0x00000600 +#define BF_ARM1_SPI1_COMMAND_BUSY_INFO 0x4700010D, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARM1_SPI1_EXT_CMD_BYTE_1_ADDR 0x4700010E +#define BF_ARM1_SPI1_EXT_CMD_BYTE_1_INFO 0x4700010E, 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARM1_SPI1_EXT_CMD_BYTE_2_ADDR 0x4700010F +#define BF_ARM1_SPI1_EXT_CMD_BYTE_2_INFO 0x4700010F, 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARM1_SPI1_EXT_CMD_BYTE_3_ADDR 0x47000110 +#define BF_ARM1_SPI1_EXT_CMD_BYTE_3_INFO 0x47000110, 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARM1_SPI1_EXT_CMD_BYTE_4_ADDR 0x47000111 +#define BF_ARM1_SPI1_EXT_CMD_BYTE_4_INFO 0x47000111, 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARM1_SPI1_CMD_STATUS_0_ADDR 0x47000115 +#define BF_ARM1_SPI1_CMD_STATUS_DWL_INFO 0x47000115, 0x00004000 +#endif /* USE_PRIVATE_BF */ + +#define REG_ARM1_SPI1_CMD_STATUS_1_ADDR 0x47000116 + +#define REG_ARM1_SPI1_CMD_STATUS_2_ADDR 0x47000117 + +#define REG_ARM1_SPI1_CMD_STATUS_3_ADDR 0x47000118 + +#define REG_ARM1_SPI1_CMD_STATUS_4_ADDR 0x47000119 + +#define REG_ARM1_SPI1_CMD_STATUS_5_ADDR 0x4700011A + +#define REG_ARM1_SPI1_CMD_STATUS_6_ADDR 0x4700011B + +#define REG_ARM1_SPI1_CMD_STATUS_7_ADDR 0x4700011C + +#ifdef USE_PRIVATE_BF +#define REG_ARM1_SPI1_CMD_STATUS_8_ADDR 0x4700011D +#define BF_ARM1_SPI1_CMD_STATUS_DWH_INFO 0x4700011D, 0x00004000 +#endif /* USE_PRIVATE_BF */ + +#define REG_ARM1_SPI1_CMD_STATUS_9_ADDR 0x4700011E + +#define REG_ARM1_SPI1_CMD_STATUS_10_ADDR 0x4700011F + +#define REG_ARM1_SPI1_CMD_STATUS_11_ADDR 0x47000120 + +#define REG_ARM1_SPI1_CMD_STATUS_12_ADDR 0x47000121 + +#define REG_ARM1_SPI1_CMD_STATUS_13_ADDR 0x47000122 + +#define REG_ARM1_SPI1_CMD_STATUS_14_ADDR 0x47000123 + +#define REG_ARM1_SPI1_CMD_STATUS_15_ADDR 0x47000124 + +#define REG_SPI0_BASE_PAGE_ADDRESS_31TO24_ADDR 0x47000126 +#define BF_SPI0_BASE_PAGE_ADDR_31TO24_INFO 0x47000126, 0x00000800 + +#define REG_SPI0_BASE_PAGE_ADDRESS_23TO16_ADDR 0x47000127 +#define BF_SPI0_BASE_PAGE_ADDR_23TO16_INFO 0x47000127, 0x00000800 + +#define REG_SPI0_BASE_PAGE_ADDRESS_15TO8_ADDR 0x47000128 +#define BF_SPI0_BASE_PAGE_ADDR_15TO8_INFO 0x47000128, 0x00000800 + +#define REG_SPI0_BASE_PAGE_ADDRESS_7TO0_ADDR 0x47000129 +#define BF_SPI0_BASE_PAGE_ADDR_7TO0_INFO 0x47000129, 0x00000800 + +#define REG_SPI0_PAGING_CONTROL_ADDR 0x4700012A +#define BF_SPI0_AHB_BRIDGE_32B_PACK_EN_INFO 0x4700012A, 0x00000100 +#define BF_SPI0_PAGING_SPI2AHB_BUSY_INFO 0x4700012A, 0x00000102 + +#define REG_SPI0_WORKING_PAGE_ADDRESS_31TO24_ADDR 0x4700012B +#define BF_SPI0_WORKING_PAGE_ADDR_31TO24_INFO 0x4700012B, 0x00000800 + +#define REG_SPI0_WORKING_PAGE_ADDRESS_23TO16_ADDR 0x4700012C +#define BF_SPI0_WORKING_PAGE_ADDR_23TO16_INFO 0x4700012C, 0x00000800 + +#define REG_SPI0_WORKING_PAGE_ADDRESS_15TO8_ADDR 0x4700012D +#define BF_SPI0_WORKING_PAGE_ADDR_15TO8_INFO 0x4700012D, 0x00000800 + +#define REG_SPI0_WORKING_PAGE_ADDRESS_7TO0_ADDR 0x4700012E +#define BF_SPI0_WORKING_PAGE_ADDR_7TO0_INFO 0x4700012E, 0x00000800 + +#define REG_SPI0_MASK_31TO24_ADDR 0x4700012F +#define BF_SPI0_MASK_31TO24_INFO 0x4700012F, 0x00000800 + +#define REG_SPI0_MASK_23TO16_ADDR 0x47000130 +#define BF_SPI0_MASK_23TO16_INFO 0x47000130, 0x00000800 + +#define REG_SPI0_MASK_15TO8_ADDR 0x47000131 +#define BF_SPI0_MASK_15TO8_INFO 0x47000131, 0x00000800 + +#define REG_SPI0_MASK_7TO0_ADDR 0x47000132 +#define BF_SPI0_MASK_7TO0_INFO 0x47000132, 0x00000800 + +#define REG_SPI1_PAGE_ADDRESS_31TO24_ADDR 0x47000134 +#define BF_SPI1_BASE_PAGE_ADDR_31TO24_INFO 0x47000134, 0x00000800 + +#define REG_SPI1_PAGE_ADDRESS_23TO16_ADDR 0x47000135 +#define BF_SPI1_BASE_PAGE_ADDR_23TO16_INFO 0x47000135, 0x00000800 + +#define REG_SPI1_PAGE_ADDRESS_15TO8_ADDR 0x47000136 +#define BF_SPI1_BASE_PAGE_ADDR_15TO8_INFO 0x47000136, 0x00000800 + +#define REG_SPI1_PAGE_ADDRESS_7TO0_ADDR 0x47000137 +#define BF_SPI1_BASE_PAGE_ADDR_7TO0_INFO 0x47000137, 0x00000800 + +#define REG_SPI1_PAGING_CONTROL_ADDR 0x47000138 +#define BF_SPI1_AHB_BRIDGE_32B_PACK_EN_INFO 0x47000138, 0x00000100 +#define BF_SPI1_CORE_SPI2AHB_BUSY_INFO 0x47000138, 0x00000101 +#define BF_SPI1_PAGING_SPI2AHB_BUSY_INFO 0x47000138, 0x00000102 + +#define REG_SPI1_WORKING_PAGE_ADDRESS_31TO24_ADDR 0x47000139 +#define BF_SPI1_WORKING_PAGE_ADDR_31TO24_INFO 0x47000139, 0x00000800 + +#define REG_SPI1_WORKING_PAGE_ADDRESS_23TO16_ADDR 0x4700013A +#define BF_SPI1_WORKING_PAGE_ADDR_23TO16_INFO 0x4700013A, 0x00000800 + +#define REG_SPI1_WORKING_PAGE_ADDRESS_15TO8_ADDR 0x4700013B +#define BF_SPI1_WORKING_PAGE_ADDR_15TO8_INFO 0x4700013B, 0x00000800 + +#define REG_SPI1_WORKING_PAGE_ADDRESS_7TO0_ADDR 0x4700013C +#define BF_SPI1_WORKING_PAGE_ADDR_7TO0_INFO 0x4700013C, 0x00000800 + +#define REG_SPI1_MASK_31TO24_ADDR 0x4700013D +#define BF_SPI1_MASK_31TO24_INFO 0x4700013D, 0x00000800 + +#define REG_SPI1_MASK_23TO16_ADDR 0x4700013E +#define BF_SPI1_MASK_23TO16_INFO 0x4700013E, 0x00000800 + +#define REG_SPI1_MASK_15TO8_ADDR 0x4700013F +#define BF_SPI1_MASK_15TO8_INFO 0x4700013F, 0x00000800 + +#define REG_SPI1_MASK_7TO0_ADDR 0x47000140 +#define BF_SPI1_MASK_7TO0_INFO 0x47000140, 0x00000800 + +#define REG_DUAL_ARM_SUBSYS_MISC_CONTROL_ADDR 0x47000142 +#define BF_ARM_DAP_MODE_SEL_INFO 0x47000142, 0x00000100 +#define BF_STREAM_PROC_WR_ACC_ARM_MEM_INFO 0x47000142, 0x00000101 + +#ifdef USE_PRIVATE_BF +#define REG_ARM0_SW_INTERRUPT_CONTROL_ADDR 0x47000143 +#define BF_ARM0_FORCE_GP_INTERRUPT_INFO 0x47000143, 0x00000100 +#define BF_ARM0_CALIBRATION_ERROR_INFO 0x47000143, 0x00000102 +#define BF_ARM0_SYSTEM_ERROR_INFO 0x47000143, 0x00000103 +#define BF_ARM0_USE_RX_ENABLE_PIN_FOR_INTERRUPT_INFO 0x47000143, 0x00000104 +#define BF_ARM0_USE_TX_ENABLE_PIN_FOR_INTERRUPT_INFO 0x47000143, 0x00000105 +#define BF_ARM0_USE_ORX_ENABLE_PIN_FOR_INTERRUPT_INFO 0x47000143, 0x00000106 +#define BF_ARM0_USE_ORX_ENABLE_PIN_FOR_LPBK_INTERRUPT_INFO 0x47000143, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARM1_SW_INTERRUPT_CONTROL_ADDR 0x47000144 +#define BF_ARM1_FORCE_GP_INTERRUPT_INFO 0x47000144, 0x00000100 +#define BF_ARM1_CALIBRATION_ERROR_INFO 0x47000144, 0x00000102 +#define BF_ARM1_SYSTEM_ERROR_INFO 0x47000144, 0x00000103 +#define BF_ARM1_USE_RX_ENABLE_PIN_FOR_INTERRUPT_INFO 0x47000144, 0x00000104 +#define BF_ARM1_USE_TX_ENABLE_PIN_FOR_INTERRUPT_INFO 0x47000144, 0x00000105 +#define BF_ARM1_USE_ORX_ENABLE_PIN_FOR_INTERRUPT_INFO 0x47000144, 0x00000106 +#define BF_ARM1_USE_ORX_ENABLE_PIN_FOR_LPBK_INTERRUPT_INFO 0x47000144, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#define REG_ZCD_SEL_CTRL_ADDR 0x47000145 +#define BF_ZCD_SEL_TAP1_CORE_INFO 0x47000145, 0x00000300 +#define BF_ZCD_SEL_TAP2_CORE_INFO 0x47000145, 0x00000303 + +#define REG_GP_INTERRUPT_MASK_PIN_1_BYTE0_ADDR 0x47000146 +#define BF_GP_INTERRUPTS_MASK_LOWER_WORD_PIN1_INFO 0x47000146, 0x00003000 + +#define REG_GP_INTERRUPT_MASK_PIN_1_BYTE1_ADDR 0x47000147 + +#define REG_GP_INTERRUPT_MASK_PIN_1_BYTE2_ADDR 0x47000148 + +#define REG_GP_INTERRUPT_MASK_PIN_1_BYTE3_ADDR 0x47000149 + +#define REG_GP_INTERRUPT_MASK_PIN_1_BYTE4_ADDR 0x4700014A + +#define REG_GP_INTERRUPT_MASK_PIN_1_BYTE5_ADDR 0x4700014B + +#define REG_GP_INTERRUPT_MASK_PIN_1_BYTE6_ADDR 0x4700014C +#define BF_GP_INTERRUPTS_MASK_UPPER_WORD_PIN1_INFO 0x4700014C, 0x00003000 + +#define REG_GP_INTERRUPT_MASK_PIN_1_BYTE7_ADDR 0x4700014D + +#define REG_GP_INTERRUPT_MASK_PIN_1_BYTE8_ADDR 0x4700014E + +#define REG_GP_INTERRUPT_MASK_PIN_1_BYTE9_ADDR 0x4700014F + +#define REG_GP_INTERRUPT_MASK_PIN_1_BYTE10_ADDR 0x47000150 + +#define REG_GP_INTERRUPT_MASK_PIN_1_BYTE11_ADDR 0x47000151 + +#ifdef USE_PRIVATE_BF +#define REG_GP_INTERRUPT_MASK_PIN_0_BYTE0_ADDR 0x47000152 +#define BF_GP_INTERRUPTS_MASK_LOWER_WORD_PIN0_INFO 0x47000152, 0x00003000 +#endif /* USE_PRIVATE_BF */ + +#define REG_GP_INTERRUPT_MASK_PIN_0_BYTE1_ADDR 0x47000153 + +#define REG_GP_INTERRUPT_MASK_PIN_0_BYTE2_ADDR 0x47000154 + +#define REG_GP_INTERRUPT_MASK_PIN_0_BYTE3_ADDR 0x47000155 + +#define REG_GP_INTERRUPT_MASK_PIN_0_BYTE4_ADDR 0x47000156 + +#define REG_GP_INTERRUPT_MASK_PIN_0_BYTE5_ADDR 0x47000157 + +#ifdef USE_PRIVATE_BF +#define REG_GP_INTERRUPT_MASK_PIN_0_BYTE6_ADDR 0x47000158 +#define BF_GP_INTERRUPTS_MASK_UPPER_WORD_PIN0_INFO 0x47000158, 0x00003000 +#endif /* USE_PRIVATE_BF */ + +#define REG_GP_INTERRUPT_MASK_PIN_0_BYTE7_ADDR 0x47000159 + +#define REG_GP_INTERRUPT_MASK_PIN_0_BYTE8_ADDR 0x4700015A + +#define REG_GP_INTERRUPT_MASK_PIN_0_BYTE9_ADDR 0x4700015B + +#define REG_GP_INTERRUPT_MASK_PIN_0_BYTE10_ADDR 0x4700015C + +#define REG_GP_INTERRUPT_MASK_PIN_0_BYTE11_ADDR 0x4700015D + +#ifdef USE_PRIVATE_BF +#define REG_GP_INTERRUPT_STATUS_READ_BYTE0_ADDR 0x4700016A +#define BF_GP_INTERRUPTS_STATUS_LOWER_WORD_INFO 0x4700016A, 0x00003000 +#endif /* USE_PRIVATE_BF */ + +#define REG_GP_INTERRUPT_STATUS_READ_BYTE1_ADDR 0x4700016B + +#define REG_GP_INTERRUPT_STATUS_READ_BYTE2_ADDR 0x4700016C + +#define REG_GP_INTERRUPT_STATUS_READ_BYTE3_ADDR 0x4700016D + +#define REG_GP_INTERRUPT_STATUS_READ_BYTE4_ADDR 0x4700016E + +#define REG_GP_INTERRUPT_STATUS_READ_BYTE5_ADDR 0x4700016F + +#ifdef USE_PRIVATE_BF +#define REG_GP_INTERRUPT_STATUS_READ_BYTE6_ADDR 0x47000170 +#define BF_GP_INTERRUPTS_STATUS_UPPER_WORD_INFO 0x47000170, 0x00003000 +#endif /* USE_PRIVATE_BF */ + +#define REG_GP_INTERRUPT_STATUS_READ_BYTE7_ADDR 0x47000171 + +#define REG_GP_INTERRUPT_STATUS_READ_BYTE8_ADDR 0x47000172 + +#define REG_GP_INTERRUPT_STATUS_READ_BYTE9_ADDR 0x47000173 + +#define REG_GP_INTERRUPT_STATUS_READ_BYTE10_ADDR 0x47000174 + +#define REG_GP_INTERRUPT_STATUS_READ_BYTE11_ADDR 0x47000175 + +#define REG_GP_INTERRUPT_LEVEL_PULSE_B_BYTE0_ADDR 0x47000176 +#define BF_GP_INTERRUPTS_LEVEL_PULSE_B_LOWER_WORD_INFO 0x47000176, 0x00003000 + +#define REG_GP_INTERRUPT_LEVEL_PULSE_B_BYTE1_ADDR 0x47000177 + +#define REG_GP_INTERRUPT_LEVEL_PULSE_B_BYTE2_ADDR 0x47000178 + +#define REG_GP_INTERRUPT_LEVEL_PULSE_B_BYTE3_ADDR 0x47000179 + +#define REG_GP_INTERRUPT_LEVEL_PULSE_B_BYTE4_ADDR 0x4700017A + +#define REG_GP_INTERRUPT_LEVEL_PULSE_B_BYTE5_ADDR 0x4700017B + +#define REG_GP_INTERRUPT_LEVEL_PULSE_B_BYTE6_ADDR 0x4700017C +#define BF_GP_INTERRUPTS_LEVEL_PULSE_B_UPPER_WORD_INFO 0x4700017C, 0x00003000 + +#define REG_GP_INTERRUPT_LEVEL_PULSE_B_BYTE7_ADDR 0x4700017D + +#define REG_GP_INTERRUPT_LEVEL_PULSE_B_BYTE8_ADDR 0x4700017E + +#define REG_GP_INTERRUPT_LEVEL_PULSE_B_BYTE9_ADDR 0x4700017F + +#define REG_GP_INTERRUPT_LEVEL_PULSE_B_BYTE10_ADDR 0x47000180 + +#define REG_GP_INTERRUPT_LEVEL_PULSE_B_BYTE11_ADDR 0x47000181 + +#define REG_SYNCINB0_A_CNTRL_ADDR 0x47000183 +#define BF_SYNCINB0_A_PAD_EN_INFO 0x47000183, 0x00000100 +#define BF_SYNCINB0_A_PN_INVERT_INFO 0x47000183, 0x00000101 +#define BF_SYNCINB0_A_LVDS_SEL_INFO 0x47000183, 0x00000102 +#define BF_SYNCINB0_A_ALT_LVDS_DOUT_EN_INFO 0x47000183, 0x00000103 +#define BF_SYNCINB0_A_SPI_READ_INFO 0x47000183, 0x00000104 +#define BF_SYNCINB0_A_TERM_EN_INFO 0x47000183, 0x00000105 +#define BF_SYNCINB0_A_ALT_DOUT_MUX_SEL_INFO 0x47000183, 0x00000206 + +#define REG_SYNCINB1_A_CNTRL_ADDR 0x47000184 +#define BF_SYNCINB1_A_PAD_EN_INFO 0x47000184, 0x00000100 +#define BF_SYNCINB1_A_PN_INVERT_INFO 0x47000184, 0x00000101 +#define BF_SYNCINB1_A_LVDS_SEL_INFO 0x47000184, 0x00000102 +#define BF_SYNCINB1_A_ALT_LVDS_DOUT_EN_INFO 0x47000184, 0x00000103 +#define BF_SYNCINB1_A_SPI_READ_INFO 0x47000184, 0x00000104 +#define BF_SYNCINB1_A_TERM_EN_INFO 0x47000184, 0x00000105 +#define BF_SYNCINB1_A_ALT_DOUT_MUX_SEL_INFO 0x47000184, 0x00000206 + +#define REG_SYNCINB0_B_CNTRL_ADDR 0x47000185 +#define BF_SYNCINB0_B_PAD_EN_INFO 0x47000185, 0x00000100 +#define BF_SYNCINB0_B_PN_INVERT_INFO 0x47000185, 0x00000101 +#define BF_SYNCINB0_B_LVDS_SEL_INFO 0x47000185, 0x00000102 +#define BF_SYNCINB0_B_ALT_LVDS_DOUT_EN_INFO 0x47000185, 0x00000103 +#define BF_SYNCINB0_B_SPI_READ_INFO 0x47000185, 0x00000104 +#define BF_SYNCINB0_B_TERM_EN_INFO 0x47000185, 0x00000105 +#define BF_SYNCINB0_B_ALT_DOUT_MUX_SEL_INFO 0x47000185, 0x00000206 + +#define REG_SYNCINB1_B_CNTRL_ADDR 0x47000186 +#define BF_SYNCINB1_B_PAD_EN_INFO 0x47000186, 0x00000100 +#define BF_SYNCINB1_B_PN_INVERT_INFO 0x47000186, 0x00000101 +#define BF_SYNCINB1_B_LVDS_SEL_INFO 0x47000186, 0x00000102 +#define BF_SYNCINB1_B_ALT_LVDS_DOUT_EN_INFO 0x47000186, 0x00000103 +#define BF_SYNCINB1_B_SPI_READ_INFO 0x47000186, 0x00000104 +#define BF_SYNCINB1_B_TERM_EN_INFO 0x47000186, 0x00000105 +#define BF_SYNCINB1_B_ALT_DOUT_MUX_SEL_INFO 0x47000186, 0x00000206 + +#define REG_SYNCOUTB0_A_CNTRL_BYTE0_ADDR 0x47000187 +#define BF_SYNCOUTB0_A_PAD_EN_INFO 0x47000187, 0x00000100 +#define BF_SYNCOUTB0_A_PN_INVERT_INFO 0x47000187, 0x00000101 +#define BF_SYNCOUTB0_A_LVDS_SEL_INFO 0x47000187, 0x00000102 +#define BF_SYNCOUTB0_A_ALT_LVDS_DIN_EN_INFO 0x47000187, 0x00000103 +#define BF_SYNCOUTB0_A_ALT_DIN_MUX_SEL_INFO 0x47000187, 0x00000206 + +#define REG_SYNCOUTB0_A_CNTRL_BYTE1_ADDR 0x47000188 +#define BF_SYNCOUTB0_A_GPIO_STAGE_SEL_INFO 0x47000188, 0x00000100 +#define BF_SYNCOUTB0_A_GPIO_DEBUG_SOURCE_SEL_INFO 0x47000188, 0x00000601 + +#define REG_SYNCOUTB1_A_CNTRL_BYTE0_ADDR 0x47000189 +#define BF_SYNCOUTB1_A_PAD_EN_INFO 0x47000189, 0x00000100 +#define BF_SYNCOUTB1_A_PN_INVERT_INFO 0x47000189, 0x00000101 +#define BF_SYNCOUTB1_A_LVDS_SEL_INFO 0x47000189, 0x00000102 +#define BF_SYNCOUTB1_A_ALT_LVDS_DIN_EN_INFO 0x47000189, 0x00000103 +#define BF_SYNCOUTB1_A_ALT_DIN_MUX_SEL_INFO 0x47000189, 0x00000206 + +#define REG_SYNCOUTB1_A_CNTRL_BYTE1_ADDR 0x4700018A +#define BF_SYNCOUTB1_A_GPIO_STAGE_SEL_INFO 0x4700018A, 0x00000100 +#define BF_SYNCOUTB1_A_GPIO_DEBUG_SOURCE_SEL_INFO 0x4700018A, 0x00000601 + +#define REG_SYNCOUTB0_B_CNTRL_BYTE0_ADDR 0x4700018B +#define BF_SYNCOUTB0_B_PAD_EN_INFO 0x4700018B, 0x00000100 +#define BF_SYNCOUTB0_B_PN_INVERT_INFO 0x4700018B, 0x00000101 +#define BF_SYNCOUTB0_B_LVDS_SEL_INFO 0x4700018B, 0x00000102 +#define BF_SYNCOUTB0_B_ALT_LVDS_DIN_EN_INFO 0x4700018B, 0x00000103 +#define BF_SYNCOUTB0_B_ALT_DIN_MUX_SEL_INFO 0x4700018B, 0x00000206 + +#define REG_SYNCOUTB0_B_CNTRL_BYTE1_ADDR 0x4700018C +#define BF_SYNCOUTB0_B_GPIO_STAGE_SEL_INFO 0x4700018C, 0x00000100 +#define BF_SYNCOUTB0_B_GPIO_DEBUG_SOURCE_SEL_INFO 0x4700018C, 0x00000601 + +#define REG_SYNCOUTB1_B_CNTRL_BYTE0_ADDR 0x4700018D +#define BF_SYNCOUTB1_B_PAD_EN_INFO 0x4700018D, 0x00000100 +#define BF_SYNCOUTB1_B_PN_INVERT_INFO 0x4700018D, 0x00000101 +#define BF_SYNCOUTB1_B_LVDS_SEL_INFO 0x4700018D, 0x00000102 +#define BF_SYNCOUTB1_B_ALT_LVDS_DIN_EN_INFO 0x4700018D, 0x00000103 +#define BF_SYNCOUTB1_B_ALT_DIN_MUX_SEL_INFO 0x4700018D, 0x00000206 + +#define REG_SYNCOUTB1_B_CNTRL_BYTE1_ADDR 0x4700018E +#define BF_SYNCOUTB1_B_GPIO_STAGE_SEL_INFO 0x4700018E, 0x00000100 +#define BF_SYNCOUTB1_B_GPIO_DEBUG_SOURCE_SEL_INFO 0x4700018E, 0x00000601 + +#ifdef USE_PRIVATE_BF +#define REG_SCAN_CONFIG_BYTE0_ADDR 0x47000190 +#define BF_SCAN_COMP_EN_INFO 0x47000190, 0x00000100 +#define BF_SCAN_OPCG_EN_INFO 0x47000190, 0x00000101 +#define BF_TEST_ENTRY_PATTERN_INFO 0x47000190, 0x00000502 +#endif /* USE_PRIVATE_BF */ + +#define REG_TEST_MODE_REGISTER_ADDR 0x47000191 +#ifdef USE_PRIVATE_BF +#define BF_TEST_MODE_CONTROL_INFO 0x47000191, 0x00000300 +#endif /* USE_PRIVATE_BF */ +#define BF_TEST_MODE_EN_INFO 0x47000191, 0x00000103 + +#define REG_OPCG_CLK_SEL_REG_ADDR 0x47000192 +#define BF_OPCG_CLK_SELECT_INFO 0x47000192, 0x00000700 + +#define REG_MBIST_MODE_EN_ADDR 0x47000193 +#define BF_MBIST_MODE_EN_INFO 0x47000193, 0x00000100 + +#ifdef USE_PRIVATE_BF +#define REG_EFUSE_OVERRIDE_0_ADDR 0x4700019A +#define BF_EFUSE_OVERRIDES_LOWER_WORD_INFO 0x4700019A, 0x00003000 +#endif /* USE_PRIVATE_BF */ + +#define REG_EFUSE_OVERRIDE_1_ADDR 0x4700019B + +#define REG_EFUSE_OVERRIDE_2_ADDR 0x4700019C + +#define REG_EFUSE_OVERRIDE_3_ADDR 0x4700019D + +#define REG_EFUSE_OVERRIDE_4_ADDR 0x4700019E + +#define REG_EFUSE_OVERRIDE_5_ADDR 0x4700019F + +#ifdef USE_PRIVATE_BF +#define REG_EFUSE_OVERRIDE_6_ADDR 0x470001A0 +#define BF_EFUSE_OVERRIDES_UPPER_WORD_INFO 0x470001A0, 0x00003000 +#endif /* USE_PRIVATE_BF */ + +#define REG_EFUSE_OVERRIDE_7_ADDR 0x470001A1 + +#define REG_EFUSE_OVERRIDE_8_ADDR 0x470001A2 + +#define REG_EFUSE_OVERRIDE_9_ADDR 0x470001A3 + +#define REG_EFUSE_OVERRIDE_10_ADDR 0x470001A4 + +#define REG_EFUSE_OVERRIDE_11_ADDR 0x470001A5 + +#ifdef USE_PRIVATE_BF +#define REG_EFUSE_OVERRIDE_CTL_ADDR 0x470001A6 +#define BF_EFUSE_OVER_RIDE_ENABLE_INFO 0x470001A6, 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_MONITOR_0_ADDR 0x470001A8 +#define BF_CONTROL_OUT_SEL_INFO 0x470001A8, 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_MONITOR_1_ADDR 0x470001A9 +#define BF_RX_CONTROL_OUT_SEL_INFO 0x470001A9, 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_MONITOR_2_ADDR 0x470001AB +#define BF_CONTROL_OUT_ENABLE_INFO 0x470001AB, 0x00000100 +#define BF_RX_CONTROL_OUT_ENABLE_INFO 0x470001AB, 0x00000101 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_MONITOR_3_ADDR 0x470001AE +#define BF_RX_ORX_ANY_SOURCE_MUX_SEL_10_INFO 0x470001AE, 0x00000300 +#define BF_RX_ORX_ANY_SOURCE_MUX_SEL_32_INFO 0x470001AE, 0x00000303 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_MONITOR_4_ADDR 0x470001AF +#define BF_RX_ORX_ANY_SOURCE_MUX_SEL_54_INFO 0x470001AF, 0x00000300 +#define BF_RX_ORX_ANY_SOURCE_MUX_SEL_76_INFO 0x470001AF, 0x00000303 +#endif /* USE_PRIVATE_BF */ + +#define REG_DRV_STRENGTH_CONTROL_0_ADDR 0x470001B1 +#define BF_REFCLK_CLK_PLL_DRVR_STRENGTH_INFO 0x470001B1, 0x00000200 +#define BF_REFCLK_SERDES_PLL_DRVR_STRENGTH_INFO 0x470001B1, 0x00000206 + +#define REG_SCRATCH_REGS_ADDR(n) (0x47000200 + 1 * (n)) +#define BF_SCRATCH_REG_INFO(n) (0x47000200 + 1 * (n)), 0x00000800 + +#define REG_SP_DBG_GLBL_CTL_ADDR 0x47000300 +#define BF_SP_DBG_GLOBAL_HALT_INFO 0x47000300, 0x00000100 +#define BF_SP_DBG_GLOBAL_RESUME_INFO 0x47000300, 0x00000101 + +#define REG_RX_SP_DBG_TRIG_MASK_ADDR 0x47000301 +#define BF_RX_SP_DBG_TRIG_MASK_INFO 0x47000301, 0x00000800 + +#define REG_TX_SP_DBG_TRIG_MASK_ADDR 0x47000302 +#define BF_TX_SP_DBG_TRIG_MASK_INFO 0x47000302, 0x00000800 + +#define REG_ORX_MAIN_SP_DBG_TRIG_MASK_ADDR 0x47000303 +#define BF_ORX_SP_DBG_TRIG_MASK_INFO 0x47000303, 0x00000200 +#define BF_MAIN_SP_DBG_TRIG_MASK_INFO 0x47000303, 0x00000104 + +#define REG_MAIN_SP_DBG_STATUS_ADDR 0x47000307 +#define BF_MAIN_SP_DBG_STAT_INFO 0x47000307, 0x00000100 + +#define REG_ORX_SP_DBG_STATUS_ADDR 0x47000308 +#define BF_ORX_SLICE_SP_DBG_STAT_INFO 0x47000308, 0x00000200 + +#define REG_RX_SP_DBG_STATUS_ADDR 0x47000309 +#define BF_RX_SLICE_SP_DBG_STAT_INFO 0x47000309, 0x00000800 + +#define REG_TX_SP_DBG_STATUS_ADDR 0x4700030A +#define BF_TX_SLICE_SP_DBG_STAT_INFO 0x4700030A, 0x00000800 + +#define REG_JESD_EVENT_FIFO_STATUS_ADDR 0x4700030B +#define BF_JESD_EVENT_FIFO_WR_FULL_INFO 0x4700030B, 0x00000800 + +#define REG_AHB_ERROR_HMASTER_ADDR 0x4700030C +#define BF_AHB_ERR_HMASTER_INFO 0x4700030C, 0x00000400 + +#define REG_AHB_ERROR_HADDR_BYTE3_ADDR 0x4700030D + +#define REG_AHB_ERROR_HADDR_BYTE2_ADDR 0x4700030E + +#define REG_AHB_ERROR_HADDR_BYTE1_ADDR 0x4700030F + +#define REG_AHB_ERROR_HADDR_BYTE0_ADDR 0x47000310 +#define BF_AHB_ERR_HADDR_INFO 0x47000310, 0x00002000 + +#define REG_AHB_ERROR_TYPE_ADDR 0x47000311 +#define BF_AHB_ERR_HSIZE_INFO 0x47000311, 0x00000300 +#ifdef USE_HW_BF +#define BF_AHB_ERR_HWRITE_INFO 0x47000311, 0x00000103 +#endif /* USE_HW_BF */ + +#define REG_AHB_ERROR_LOCATOR_ADDR 0x47000313 +#define BF_AHB_ERROR_LOCATOR_INFO 0x47000313, 0x00000500 + +#define REG_MASTER_AHB_ERROR_HRESP_MASK_ADDR 0x47000315 +#define BF_AHB_ERROR_HRESP_MASK_ARM0_INFO 0x47000315, 0x00000100 +#define BF_AHB_ERROR_HRESP_MASK_ARM1_INFO 0x47000315, 0x00000101 + +#define REG_MASTER_AHB_ERROR_INTERRUPT_MASK_ADDR 0x47000316 +#define BF_AHB_ERROR_INTERRUPT_MASK_SPI0_INFO 0x47000316, 0x00000100 +#define BF_AHB_ERROR_INTERRUPT_MASK_SPI1_INFO 0x47000316, 0x00000101 +#define BF_AHB_ERROR_INTERRUPT_MASK_ARM0_INFO 0x47000316, 0x00000102 +#define BF_AHB_ERROR_INTERRUPT_MASK_ARM1_INFO 0x47000316, 0x00000103 +#define BF_AHB_ERROR_INTERRUPT_MASK_CORE_STREAM_PROC_INFO 0x47000316, 0x00000104 +#define BF_AHB_ERROR_INTERRUPT_MASK_KFA_STREAM_PROC_INFO 0x47000316, 0x00000105 + +#ifdef USE_PRIVATE_BF +#define REG_STREAM_PROC_GPIO_PIN_MASK_1_ADDR 0x47000317 +#define BF_STREAM_PROC_GPIO_PIN_MASK_INFO 0x47000317, 0x00001800 +#endif /* USE_PRIVATE_BF */ + +#define REG_STREAM_PROC_GPIO_PIN_MASK_2_ADDR 0x47000318 + +#define REG_STREAM_PROC_GPIO_PIN_MASK_3_ADDR 0x47000319 + +#ifdef USE_PRIVATE_BF +#define REG_JESD_CONTROL_CONFIG_ADDR 0x4700031A +#define BF_JESD_CONTROL_TRIGGER_MASK_INFO 0x4700031A, 0x00000100 +#define BF_JESD_CONTROL_TRIGGER_1_MASK_INFO 0x4700031A, 0x00000101 +#define BF_JESD_CONTROL_TRIGGER_2_MASK_INFO 0x4700031A, 0x00000102 +#define BF_JESD_CONTROL_TRIGGER_3_MASK_INFO 0x4700031A, 0x00000103 +#define BF_JESD_CONTROL_TRIGGER_4_MASK_INFO 0x4700031A, 0x00000104 +#define BF_JESD_CONTROL_TRIGGER_5_MASK_INFO 0x4700031A, 0x00000105 +#define BF_JESD_CONTROL_TRIGGER_6_MASK_INFO 0x4700031A, 0x00000106 +#define BF_JESD_CONTROL_TRIGGER_7_MASK_INFO 0x4700031A, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_STREAM_PROC_GP_IRQ_MASK_ADDR 0x4700031B +#define BF_STREAM_PROC_GP_IRQ_MASK_INFO 0x4700031B, 0x00000200 +#endif /* USE_PRIVATE_BF */ + +#define REG_REFCLK_CLKSYNTH_CONTROL_ADDR 0x47000338 +#define BF_CLKPLL_REFPATH_PD_INFO 0x47000338, 0x00000100 +#define BF_CLKPLL_REFCLK_ENABLE_CLKB_INFO 0x47000338, 0x00000101 +#define BF_CLKPLL_INVERT_REFCLK_INFO 0x47000338, 0x00000102 +#define BF_CLKPLL_INVERT_SYNC_PULSE_INFO 0x47000338, 0x00000103 +#define BF_CLKPLL_FORCE_REFCLK_PATH_ON_INFO 0x47000338, 0x00000104 + +#define REG_REFCLK_CLKSYNTH_CONTROL2_ADDR 0x47000339 +#define BF_CLKPLL_DELAY_REFCLK_INFO 0x47000339, 0x00000400 +#define BF_CLKPLL_DELAY_SYNC_PULSE_INFO 0x47000339, 0x00000404 + +#define REG_REFCLK_SERDES_SYNTH_CONTROL_ADDR 0x4700033A +#define BF_SERDES_PLL_REFPATH_PD_INFO 0x4700033A, 0x00000100 +#define BF_SERDES_PLL_REFCLK_ENABLE_CLKB_INFO 0x4700033A, 0x00000101 +#define BF_SERDES_PLL_INVERT_REFCLK_INFO 0x4700033A, 0x00000102 +#define BF_SERDES_PLL_INVERT_SYNC_PULSE_INFO 0x4700033A, 0x00000103 +#define BF_SERDES_PLL_FORCE_REFCLK_PATH_ON_INFO 0x4700033A, 0x00000104 + +#define REG_REFCLK_SERDES_SYNTH_CONTROL2_ADDR 0x4700033B +#define BF_SERDES_PLL_DELAY_REFCLK_INFO 0x4700033B, 0x00000400 +#define BF_SERDES_PLL_DELAY_SYNC_PULSE_INFO 0x4700033B, 0x00000404 + +#define REG_XTRIG_CTL_ADDR 0x470003F0 +#define BF_XTRIG_EN_INFO 0x470003F0, 0x00000100 + +#define REG_XTRIG_MASK1_ADDR(n) (0x470003F1 + 3 * (n)) +#define BF_TRIG_MASK_INFO(n) (0x470003F1 + 3 * (n)), 0x00001500 + +#define REG_XTRIG_MASK2_ADDR(n) (0x470003F2 + 3 * (n)) + +#define REG_XTRIG_MASK3_ADDR(n) (0x470003F3 + 3 * (n)) + +#ifdef USE_PRIVATE_BF +#define REG_STREAM_PROC_DEBUG_REG_ARRAY_ADDR(n) (0x47000523 + 1 * (n)) +#define BF_STREAMPROC_DEBUG_DATA_INFO(n) (0x47000523 + 1 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_STREAM_PROC_ECC_STATUS_ADDR 0x47000543 +#define BF_MAIN_STREAMPROC_ERROR_STATUS_INFO 0x47000543, 0x00000100 +#define BF_MAIN_STREAMPROC_ERROR_CLEAR_INFO 0x47000543, 0x00000101 + +#ifdef USE_PRIVATE_BF +#define REG_DIG_CORE_FABRIC_DUAL_RANGE_CONTROL_ADDR 0x47000544 +#define BF_DIG_CORE_FABRIC_DUAL_RANGE_ENABLE_INFO 0x47000544, 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_DEBUG_KEY_STATUS_ADDR 0x4700054E +#define BF_DEBUG_KEY_UNLOCKED_INFO 0x4700054E, 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#define REG_CMOS_PAD_DS_ADDR 0x47000550 +#define BF_PAD_DS_INFO 0x47000550, 0x00000400 + +#define REG_CMOS_PAD_ST_BYTE0_ADDR 0x47000551 +#define BF_PAD_ST_GPIO_INFO 0x47000551, 0x00003300 + +#define REG_CMOS_PAD_ST_BYTE1_ADDR 0x47000552 + +#define REG_CMOS_PAD_ST_BYTE2_ADDR 0x47000553 + +#define REG_CMOS_PAD_ST_BYTE3_ADDR 0x47000554 + +#define REG_CMOS_PAD_ST_BYTE4_ADDR 0x47000555 + +#define REG_CMOS_PAD_ST_BYTE5_ADDR 0x47000556 + +#define REG_CMOS_PAD_ST_BYTE6_ADDR 0x47000557 +#define BF_PAD_ST_SCK_INFO 0x47000557, 0x00000103 +#define BF_PAD_ST_SCSB_INFO 0x47000557, 0x00000104 +#define BF_PAD_ST_RESETN_INFO 0x47000557, 0x00000105 +#define BF_PAD_ST_SDIO_INFO 0x47000557, 0x00000106 +#define BF_PAD_ST_SDO_INFO 0x47000557, 0x00000107 + +#define REG_ALT_BOOT_ADDR(n) (0x47000558 + 1 * (n)) +#define BF_ALT_BOOT_INFO(n) (0x47000558 + 1 * (n)), 0x00000800 + +#define REG_RX_A0_PORB_STATUS_ADDR 0x47000582 +#define BF_PORB_RX_A0_VDDA1P0_INFO 0x47000582, 0x00000100 +#define BF_PORB_RX_A0_VDDA1P8_INFO 0x47000582, 0x00000101 +#define BF_PORB_RX_A0_VDDACK1P0_INFO 0x47000582, 0x00000102 +#define BF_PORB_RX_A0_VDDD0P8_INFO 0x47000582, 0x00000103 +#define BF_PORB_RX_A0_VDDD1P0_INFO 0x47000582, 0x00000104 + +#define REG_RX_A1_PORB_STATUS_ADDR 0x47000583 +#define BF_PORB_RX_A1_VDDA1P0_INFO 0x47000583, 0x00000100 +#define BF_PORB_RX_A1_VDDA1P8_INFO 0x47000583, 0x00000101 +#define BF_PORB_RX_A1_VDDACK1P0_INFO 0x47000583, 0x00000102 +#define BF_PORB_RX_A1_VDDD0P8_INFO 0x47000583, 0x00000103 +#define BF_PORB_RX_A1_VDDD1P0_INFO 0x47000583, 0x00000104 + +#define REG_RX_B0_PORB_STATUS_ADDR 0x47000584 +#define BF_PORB_RX_B0_VDDA1P0_INFO 0x47000584, 0x00000100 +#define BF_PORB_RX_B0_VDDA1P8_INFO 0x47000584, 0x00000101 +#define BF_PORB_RX_B0_VDDACK1P0_INFO 0x47000584, 0x00000102 +#define BF_PORB_RX_B0_VDDD0P8_INFO 0x47000584, 0x00000103 +#define BF_PORB_RX_B0_VDDD1P0_INFO 0x47000584, 0x00000104 + +#define REG_RX_B1_PORB_STATUS_ADDR 0x47000585 +#define BF_PORB_RX_B1_VDDA1P0_INFO 0x47000585, 0x00000100 +#define BF_PORB_RX_B1_VDDA1P8_INFO 0x47000585, 0x00000101 +#define BF_PORB_RX_B1_VDDACK1P0_INFO 0x47000585, 0x00000102 +#define BF_PORB_RX_B1_VDDD0P8_INFO 0x47000585, 0x00000103 +#define BF_PORB_RX_B1_VDDD1P0_INFO 0x47000585, 0x00000104 + +#define REG_TX_A0_PORB_STATUS_ADDR 0x47000586 +#define BF_PORB_TX_A0_VDDA1P0_INFO 0x47000586, 0x00000100 +#define BF_PORB_TX_A0_VDDA1P8_INFO 0x47000586, 0x00000101 +#define BF_PORB_TX_A0_VDDC1P0_INFO 0x47000586, 0x00000102 +#define BF_PORB_TX_A0_VDDD1P0_INFO 0x47000586, 0x00000103 +#define BF_PORB_TX_A0_VNEG_INFO 0x47000586, 0x00000104 +#define BF_PORB_TX_A0_VDDA2P5_INFO 0x47000586, 0x00000105 + +#define REG_TX_A1_PORB_STATUS_ADDR 0x47000587 +#define BF_PORB_TX_A1_VDDA1P0_INFO 0x47000587, 0x00000100 +#define BF_PORB_TX_A1_VDDA1P8_INFO 0x47000587, 0x00000101 +#define BF_PORB_TX_A1_VDDC1P0_INFO 0x47000587, 0x00000102 +#define BF_PORB_TX_A1_VDDD1P0_INFO 0x47000587, 0x00000103 +#define BF_PORB_TX_A1_VNEG_INFO 0x47000587, 0x00000104 +#define BF_PORB_TX_A1_VDDA2P5_INFO 0x47000587, 0x00000105 + +#define REG_TX_A2_PORB_STATUS_ADDR 0x47000588 +#define BF_PORB_TX_A2_VDDA1P0_INFO 0x47000588, 0x00000100 +#define BF_PORB_TX_A2_VDDA1P8_INFO 0x47000588, 0x00000101 +#define BF_PORB_TX_A2_VDDC1P0_INFO 0x47000588, 0x00000102 +#define BF_PORB_TX_A2_VDDD1P0_INFO 0x47000588, 0x00000103 +#define BF_PORB_TX_A2_VNEG_INFO 0x47000588, 0x00000104 +#define BF_PORB_TX_A2_VDDA2P5_INFO 0x47000588, 0x00000105 + +#define REG_TX_A3_PORB_STATUS_ADDR 0x47000589 +#define BF_PORB_TX_A3_VDDA1P0_INFO 0x47000589, 0x00000100 +#define BF_PORB_TX_A3_VDDA1P8_INFO 0x47000589, 0x00000101 +#define BF_PORB_TX_A3_VDDC1P0_INFO 0x47000589, 0x00000102 +#define BF_PORB_TX_A3_VDDD1P0_INFO 0x47000589, 0x00000103 +#define BF_PORB_TX_A3_VNEG_INFO 0x47000589, 0x00000104 +#define BF_PORB_TX_A3_VDDA2P5_INFO 0x47000589, 0x00000105 + +#define REG_TX_B0_PORB_STATUS_ADDR 0x4700058A +#define BF_PORB_TX_B0_VDDA1P0_INFO 0x4700058A, 0x00000100 +#define BF_PORB_TX_B0_VDDA1P8_INFO 0x4700058A, 0x00000101 +#define BF_PORB_TX_B0_VDDC1P0_INFO 0x4700058A, 0x00000102 +#define BF_PORB_TX_B0_VDDD1P0_INFO 0x4700058A, 0x00000103 +#define BF_PORB_TX_B0_VNEG_INFO 0x4700058A, 0x00000104 +#define BF_PORB_TX_B0_VDDA2P5_INFO 0x4700058A, 0x00000105 + +#define REG_TX_B1_PORB_STATUS_ADDR 0x4700058B +#define BF_PORB_TX_B1_VDDA1P0_INFO 0x4700058B, 0x00000100 +#define BF_PORB_TX_B1_VDDA1P8_INFO 0x4700058B, 0x00000101 +#define BF_PORB_TX_B1_VDDC1P0_INFO 0x4700058B, 0x00000102 +#define BF_PORB_TX_B1_VDDD1P0_INFO 0x4700058B, 0x00000103 +#define BF_PORB_TX_B1_VNEG_INFO 0x4700058B, 0x00000104 +#define BF_PORB_TX_B1_VDDA2P5_INFO 0x4700058B, 0x00000105 + +#define REG_TX_B2_PORB_STATUS_ADDR 0x4700058C +#define BF_PORB_TX_B2_VDDA1P0_INFO 0x4700058C, 0x00000100 +#define BF_PORB_TX_B2_VDDA1P8_INFO 0x4700058C, 0x00000101 +#define BF_PORB_TX_B2_VDDC1P0_INFO 0x4700058C, 0x00000102 +#define BF_PORB_TX_B2_VDDD1P0_INFO 0x4700058C, 0x00000103 +#define BF_PORB_TX_B2_VNEG_INFO 0x4700058C, 0x00000104 +#define BF_PORB_TX_B2_VDDA2P5_INFO 0x4700058C, 0x00000105 + +#define REG_TX_B3_PORB_STATUS_ADDR 0x4700058D +#define BF_PORB_TX_B3_VDDA1P0_INFO 0x4700058D, 0x00000100 +#define BF_PORB_TX_B3_VDDA1P8_INFO 0x4700058D, 0x00000101 +#define BF_PORB_TX_B3_VDDC1P0_INFO 0x4700058D, 0x00000102 +#define BF_PORB_TX_B3_VDDD1P0_INFO 0x4700058D, 0x00000103 +#define BF_PORB_TX_B3_VNEG_INFO 0x4700058D, 0x00000104 +#define BF_PORB_TX_B3_VDDA2P5_INFO 0x4700058D, 0x00000105 + +#define REG_SERDES_PORB_STATUS_ADDR 0x4700058E +#define BF_PORB_DES_VDDA1P0_INFO 0x4700058E, 0x00000100 +#define BF_PORB_SER_VDDA1P0_INFO 0x4700058E, 0x00000101 +#define BF_PORB_SERDES_CK_VDDA1P0_INFO 0x4700058E, 0x00000102 +#define BF_PORB_SERDES_PLL_VDDA1P0_INFO 0x4700058E, 0x00000103 +#define BF_PORB_SERDES_PLL_VDDA1P8_INFO 0x4700058E, 0x00000104 +#define BF_PORB_SERDES_VDDD0P8_INFO 0x4700058E, 0x00000105 + +#define REG_MCS_MB_CK_PORB_STATUS_ADDR 0x4700058F +#define BF_PORB_CK_VDDA1P0_INFO 0x4700058F, 0x00000100 +#define BF_PORB_MB_A_VDDA1P0_INFO 0x4700058F, 0x00000101 +#define BF_PORB_MB_A_VDDA1P8_INFO 0x4700058F, 0x00000102 +#define BF_PORB_MB_B_VDDA1P0_INFO 0x4700058F, 0x00000103 +#define BF_PORB_MB_B_VDDA1P8_INFO 0x4700058F, 0x00000104 +#define BF_PORB_MCS_VDDD1P0_INFO 0x4700058F, 0x00000105 + +#define REG_RX_A_IRMON_CTRL_ADDR 0x47000590 +#define BF_RX_A_IRMON_CTRL_INFO 0x47000590, 0x00000800 + +#define REG_RX_B_IRMON_CTRL_ADDR 0x47000591 +#define BF_RX_B_IRMON_CTRL_INFO 0x47000591, 0x00000800 + +#define REG_TX_A_IRMON_CTRL_ADDR 0x47000592 +#define BF_TX_A_IRMON_CTRL_INFO 0x47000592, 0x00000800 + +#define REG_TX_B_IRMON_CTRL_ADDR 0x47000593 +#define BF_TX_B_IRMON_CTRL_INFO 0x47000593, 0x00000800 + +#define REG_TRACE_CORE_SELECT_REG_ADDR 0x4700077E +#define BF_TRACE_CORE_SELECT_INFO 0x4700077E, 0x00000100 + +#define REG_XTRIG_DAP_MODE_TRIG_CTL_ADDR 0x47000786 +#define BF_XTRIG_DAP_MODE_TRIG_EN_INFO 0x47000786, 0x00000100 + +#define REG_XTRIG_PROG_COUNT_THRES_ADDR 0x47000787 +#define BF_PROG_FSM_COUNT_THRES_INFO 0x47000787, 0x00000400 +#define BF_PROG_FSM_COUNT_THRES1_INFO 0x47000787, 0x00000404 + +#define REG_XTRIG_PROG_DP_ADDR1_1_ADDR 0x47000788 +#define BF_PROG_DP_ADDR1_INFO 0x47000788, 0x00002000 + +#define REG_XTRIG_PROG_DP_ADDR1_2_ADDR 0x47000789 + +#define REG_XTRIG_PROG_DP_ADDR1_3_ADDR 0x4700078A + +#define REG_XTRIG_PROG_DP_ADDR1_4_ADDR 0x4700078B + +#define REG_XTRIG_PROG_DP_ADDR2_1_ADDR 0x4700078C +#define BF_PROG_DP_ADDR2_INFO 0x4700078C, 0x00002000 + +#define REG_XTRIG_PROG_DP_ADDR2_2_ADDR 0x4700078D + +#define REG_XTRIG_PROG_DP_ADDR2_3_ADDR 0x4700078E + +#define REG_XTRIG_PROG_DP_ADDR2_4_ADDR 0x4700078F + +#define REG_XTRIG_PROG_DP_ADDR3_1_ADDR 0x47000790 +#define BF_PROG_DP_ADDR3_INFO 0x47000790, 0x00002000 + +#define REG_XTRIG_PROG_DP_ADDR3_2_ADDR 0x47000791 + +#define REG_XTRIG_PROG_DP_ADDR3_3_ADDR 0x47000792 + +#define REG_XTRIG_PROG_DP_ADDR3_4_ADDR 0x47000793 + +#define REG_XTRIG_PROG_DP_ADDR4_1_ADDR 0x47000794 +#define BF_PROG_DP_ADDR4_INFO 0x47000794, 0x00002000 + +#define REG_XTRIG_PROG_DP_ADDR4_2_ADDR 0x47000795 + +#define REG_XTRIG_PROG_DP_ADDR4_3_ADDR 0x47000796 + +#define REG_XTRIG_PROG_DP_ADDR4_4_ADDR 0x47000797 + +#define REG_XTRIG_PROG_DP_ADDR5_1_ADDR 0x47000798 +#define BF_PROG_DP_ADDR5_INFO 0x47000798, 0x00002000 + +#define REG_XTRIG_PROG_DP_ADDR5_2_ADDR 0x47000799 + +#define REG_XTRIG_PROG_DP_ADDR5_3_ADDR 0x4700079A + +#define REG_XTRIG_PROG_DP_ADDR5_4_ADDR 0x4700079B + +#define REG_XTRIG_PROG_DP_ADDR6_1_ADDR 0x4700079C +#define BF_PROG_DP_ADDR6_INFO 0x4700079C, 0x00002000 + +#define REG_XTRIG_PROG_DP_ADDR6_2_ADDR 0x4700079D + +#define REG_XTRIG_PROG_DP_ADDR6_3_ADDR 0x4700079E + +#define REG_XTRIG_PROG_DP_ADDR6_4_ADDR 0x4700079F + +#define REG_XTRIG_PROG_DP_ADDR7_1_ADDR 0x470007A0 +#define BF_PROG_DP_ADDR7_INFO 0x470007A0, 0x00002000 + +#define REG_XTRIG_PROG_DP_ADDR7_2_ADDR 0x470007A1 + +#define REG_XTRIG_PROG_DP_ADDR7_3_ADDR 0x470007A2 + +#define REG_XTRIG_PROG_DP_ADDR7_4_ADDR 0x470007A3 + +#define REG_XTRIG_PROG_DP_ADDR8_1_ADDR 0x470007A4 +#define BF_PROG_DP_ADDR8_INFO 0x470007A4, 0x00002000 + +#define REG_XTRIG_PROG_DP_ADDR8_2_ADDR 0x470007A5 + +#define REG_XTRIG_PROG_DP_ADDR8_3_ADDR 0x470007A6 + +#define REG_XTRIG_PROG_DP_ADDR8_4_ADDR 0x470007A7 + +#define REG_XTRIG_PROG_DP_ADDR9_1_ADDR 0x470007A8 +#define BF_PROG_DP_ADDR9_INFO 0x470007A8, 0x00002000 + +#define REG_XTRIG_PROG_DP_ADDR9_2_ADDR 0x470007A9 + +#define REG_XTRIG_PROG_DP_ADDR9_3_ADDR 0x470007AA + +#define REG_XTRIG_PROG_DP_ADDR9_4_ADDR 0x470007AB + +#define REG_XTRIG_PROG_DP_ADDR10_1_ADDR 0x470007AC +#define BF_PROG_DP_ADDR10_INFO 0x470007AC, 0x00002000 + +#define REG_XTRIG_PROG_DP_ADDR10_2_ADDR 0x470007AD + +#define REG_XTRIG_PROG_DP_ADDR10_3_ADDR 0x470007AE + +#define REG_XTRIG_PROG_DP_ADDR10_4_ADDR 0x470007AF + +#define REG_XTRIG_PROG_DP_VAL1_1_ADDR 0x470007B6 +#define BF_PROG_DP_VAL1_INFO 0x470007B6, 0x00002000 + +#define REG_XTRIG_PROG_DP_VAL1_2_ADDR 0x470007B7 + +#define REG_XTRIG_PROG_DP_VAL1_3_ADDR 0x470007B8 + +#define REG_XTRIG_PROG_DP_VAL1_4_ADDR 0x470007B9 + +#define REG_XTRIG_PROG_DP_VAL2_1_ADDR 0x470007BA +#define BF_PROG_DP_VAL2_INFO 0x470007BA, 0x00002000 + +#define REG_XTRIG_PROG_DP_VAL2_2_ADDR 0x470007BB + +#define REG_XTRIG_PROG_DP_VAL2_3_ADDR 0x470007BC + +#define REG_XTRIG_PROG_DP_VAL2_4_ADDR 0x470007BD + +#define REG_XTRIG_PROG_DP_VAL3_1_ADDR 0x470007BE +#define BF_PROG_DP_VAL3_INFO 0x470007BE, 0x00002000 + +#define REG_XTRIG_PROG_DP_VAL3_2_ADDR 0x470007BF + +#define REG_XTRIG_PROG_DP_VAL3_3_ADDR 0x470007C0 + +#define REG_XTRIG_PROG_DP_VAL3_4_ADDR 0x470007C1 + +#define REG_XTRIG_PROG_DP_VAL4_1_ADDR 0x470007C2 +#define BF_PROG_DP_VAL4_INFO 0x470007C2, 0x00002000 + +#define REG_XTRIG_PROG_DP_VAL4_2_ADDR 0x470007C3 + +#define REG_XTRIG_PROG_DP_VAL4_3_ADDR 0x470007C4 + +#define REG_XTRIG_PROG_DP_VAL4_4_ADDR 0x470007C5 + +#define REG_XTRIG_PROG_DP_VAL5_1_ADDR 0x470007C6 +#define BF_PROG_DP_VAL5_INFO 0x470007C6, 0x00002000 + +#define REG_XTRIG_PROG_DP_VAL5_2_ADDR 0x470007C7 + +#define REG_XTRIG_PROG_DP_VAL5_3_ADDR 0x470007C8 + +#define REG_XTRIG_PROG_DP_VAL5_4_ADDR 0x470007C9 + +#define REG_XTRIG_PROG_DP_VAL6_1_ADDR 0x470007CA +#define BF_PROG_DP_VAL6_INFO 0x470007CA, 0x00002000 + +#define REG_XTRIG_PROG_DP_VAL6_2_ADDR 0x470007CB + +#define REG_XTRIG_PROG_DP_VAL6_3_ADDR 0x470007CC + +#define REG_XTRIG_PROG_DP_VAL6_4_ADDR 0x470007CD + +#define REG_XTRIG_PROG_DP_VAL7_1_ADDR 0x470007CE +#define BF_PROG_DP_VAL7_INFO 0x470007CE, 0x00002000 + +#define REG_XTRIG_PROG_DP_VAL7_2_ADDR 0x470007CF + +#define REG_XTRIG_PROG_DP_VAL7_3_ADDR 0x470007D0 + +#define REG_XTRIG_PROG_DP_VAL7_4_ADDR 0x470007D1 + +#define REG_XTRIG_PROG_DP_VAL8_1_ADDR 0x470007D2 +#define BF_PROG_DP_VAL8_INFO 0x470007D2, 0x00002000 + +#define REG_XTRIG_PROG_DP_VAL8_2_ADDR 0x470007D3 + +#define REG_XTRIG_PROG_DP_VAL8_3_ADDR 0x470007D4 + +#define REG_XTRIG_PROG_DP_VAL8_4_ADDR 0x470007D5 + +#define REG_XTRIG_PROG_DP_VAL9_1_ADDR 0x470007D6 +#define BF_PROG_DP_VAL9_INFO 0x470007D6, 0x00002000 + +#define REG_XTRIG_PROG_DP_VAL9_2_ADDR 0x470007D7 + +#define REG_XTRIG_PROG_DP_VAL9_3_ADDR 0x470007D8 + +#define REG_XTRIG_PROG_DP_VAL9_4_ADDR 0x470007D9 + +#define REG_XTRIG_PROG_DP_VAL10_1_ADDR 0x470007DA +#define BF_PROG_DP_VAL10_INFO 0x470007DA, 0x00002000 + +#define REG_XTRIG_PROG_DP_VAL10_2_ADDR 0x470007DB + +#define REG_XTRIG_PROG_DP_VAL10_3_ADDR 0x470007DC + +#define REG_XTRIG_PROG_DP_VAL10_4_ADDR 0x470007DD + +#define REG_XTRIG_PROG_DP1_ADDR1_1_ADDR 0x470007DE +#define BF_PROG_DP1_ADDR1_INFO 0x470007DE, 0x00002000 + +#define REG_XTRIG_PROG_DP1_ADDR1_2_ADDR 0x470007DF + +#define REG_XTRIG_PROG_DP1_ADDR1_3_ADDR 0x470007E0 + +#define REG_XTRIG_PROG_DP1_ADDR1_4_ADDR 0x470007E1 + +#define REG_XTRIG_PROG_DP1_ADDR2_1_ADDR 0x470007E2 +#define BF_PROG_DP1_ADDR2_INFO 0x470007E2, 0x00002000 + +#define REG_XTRIG_PROG_DP1_ADDR2_2_ADDR 0x470007E3 + +#define REG_XTRIG_PROG_DP1_ADDR2_3_ADDR 0x470007E4 + +#define REG_XTRIG_PROG_DP1_ADDR2_4_ADDR 0x470007E5 + +#define REG_XTRIG_PROG_DP1_ADDR3_1_ADDR 0x470007E6 +#define BF_PROG_DP1_ADDR3_INFO 0x470007E6, 0x00002000 + +#define REG_XTRIG_PROG_DP1_ADDR3_2_ADDR 0x470007E7 + +#define REG_XTRIG_PROG_DP1_ADDR3_3_ADDR 0x470007E8 + +#define REG_XTRIG_PROG_DP1_ADDR3_4_ADDR 0x470007E9 + +#define REG_XTRIG_PROG_DP1_ADDR4_1_ADDR 0x470007EA +#define BF_PROG_DP1_ADDR4_INFO 0x470007EA, 0x00002000 + +#define REG_XTRIG_PROG_DP1_ADDR4_2_ADDR 0x470007EB + +#define REG_XTRIG_PROG_DP1_ADDR4_3_ADDR 0x470007EC + +#define REG_XTRIG_PROG_DP1_ADDR4_4_ADDR 0x470007ED + +#define REG_XTRIG_PROG_DP1_ADDR5_1_ADDR 0x470007EE +#define BF_PROG_DP1_ADDR5_INFO 0x470007EE, 0x00002000 + +#define REG_XTRIG_PROG_DP1_ADDR5_2_ADDR 0x470007EF + +#define REG_XTRIG_PROG_DP1_ADDR5_3_ADDR 0x470007F0 + +#define REG_XTRIG_PROG_DP1_ADDR5_4_ADDR 0x470007F1 + +#define REG_XTRIG_PROG_DP1_ADDR6_1_ADDR 0x470007F2 +#define BF_PROG_DP1_ADDR6_INFO 0x470007F2, 0x00002000 + +#define REG_XTRIG_PROG_DP1_ADDR6_2_ADDR 0x470007F3 + +#define REG_XTRIG_PROG_DP1_ADDR6_3_ADDR 0x470007F4 + +#define REG_XTRIG_PROG_DP1_ADDR6_4_ADDR 0x470007F5 + +#define REG_XTRIG_PROG_DP1_ADDR7_1_ADDR 0x470007F6 +#define BF_PROG_DP1_ADDR7_INFO 0x470007F6, 0x00002000 + +#define REG_XTRIG_PROG_DP1_ADDR7_2_ADDR 0x470007F7 + +#define REG_XTRIG_PROG_DP1_ADDR7_3_ADDR 0x470007F8 + +#define REG_XTRIG_PROG_DP1_ADDR7_4_ADDR 0x470007F9 + +#define REG_XTRIG_PROG_DP1_ADDR8_1_ADDR 0x470007FA +#define BF_PROG_DP1_ADDR8_INFO 0x470007FA, 0x00002000 + +#define REG_XTRIG_PROG_DP1_ADDR8_2_ADDR 0x470007FB + +#define REG_XTRIG_PROG_DP1_ADDR8_3_ADDR 0x470007FC + +#define REG_XTRIG_PROG_DP1_ADDR8_4_ADDR 0x470007FD + +#define REG_XTRIG_PROG_DP1_ADDR9_1_ADDR 0x470007FE +#define BF_PROG_DP1_ADDR9_INFO 0x470007FE, 0x00002000 + +#define REG_XTRIG_PROG_DP1_ADDR9_2_ADDR 0x470007FF + +#define REG_XTRIG_PROG_DP1_ADDR9_3_ADDR 0x47000800 + +#define REG_XTRIG_PROG_DP1_ADDR9_4_ADDR 0x47000801 + +#define REG_XTRIG_PROG_DP1_ADDR10_1_ADDR 0x47000802 +#define BF_PROG_DP1_ADDR10_INFO 0x47000802, 0x00002000 + +#define REG_XTRIG_PROG_DP1_ADDR10_2_ADDR 0x47000803 + +#define REG_XTRIG_PROG_DP1_ADDR10_3_ADDR 0x47000804 + +#define REG_XTRIG_PROG_DP1_ADDR10_4_ADDR 0x47000805 + +#define REG_XTRIG_PROG_DP1_VAL1_1_ADDR 0x47000806 +#define BF_PROG_DP1_VAL1_INFO 0x47000806, 0x00002000 + +#define REG_XTRIG_PROG_DP1_VAL1_2_ADDR 0x47000807 + +#define REG_XTRIG_PROG_DP1_VAL1_3_ADDR 0x47000808 + +#define REG_XTRIG_PROG_DP1_VAL1_4_ADDR 0x47000809 + +#define REG_XTRIG_PROG_DP1_VAL2_1_ADDR 0x4700080A +#define BF_PROG_DP1_VAL2_INFO 0x4700080A, 0x00002000 + +#define REG_XTRIG_PROG_DP1_VAL2_2_ADDR 0x4700080B + +#define REG_XTRIG_PROG_DP1_VAL2_3_ADDR 0x4700080C + +#define REG_XTRIG_PROG_DP1_VAL2_4_ADDR 0x4700080D + +#define REG_XTRIG_PROG_DP1_VAL3_1_ADDR 0x4700080E +#define BF_PROG_DP1_VAL3_INFO 0x4700080E, 0x00002000 + +#define REG_XTRIG_PROG_DP1_VAL3_2_ADDR 0x4700080F + +#define REG_XTRIG_PROG_DP1_VAL3_3_ADDR 0x47000810 + +#define REG_XTRIG_PROG_DP1_VAL3_4_ADDR 0x47000811 + +#define REG_XTRIG_PROG_DP1_VAL4_1_ADDR 0x47000812 +#define BF_PROG_DP1_VAL4_INFO 0x47000812, 0x00002000 + +#define REG_XTRIG_PROG_DP1_VAL4_2_ADDR 0x47000813 + +#define REG_XTRIG_PROG_DP1_VAL4_3_ADDR 0x47000814 + +#define REG_XTRIG_PROG_DP1_VAL4_4_ADDR 0x47000815 + +#define REG_XTRIG_PROG_DP1_VAL5_1_ADDR 0x47000816 +#define BF_PROG_DP1_VAL5_INFO 0x47000816, 0x00002000 + +#define REG_XTRIG_PROG_DP1_VAL5_2_ADDR 0x47000817 + +#define REG_XTRIG_PROG_DP1_VAL5_3_ADDR 0x47000818 + +#define REG_XTRIG_PROG_DP1_VAL5_4_ADDR 0x47000819 + +#define REG_XTRIG_PROG_DP1_VAL6_1_ADDR 0x4700081A +#define BF_PROG_DP1_VAL6_INFO 0x4700081A, 0x00002000 + +#define REG_XTRIG_PROG_DP1_VAL6_2_ADDR 0x4700081B + +#define REG_XTRIG_PROG_DP1_VAL6_3_ADDR 0x4700081C + +#define REG_XTRIG_PROG_DP1_VAL6_4_ADDR 0x4700081D + +#define REG_XTRIG_PROG_DP1_VAL7_1_ADDR 0x4700081E +#define BF_PROG_DP1_VAL7_INFO 0x4700081E, 0x00002000 + +#define REG_XTRIG_PROG_DP1_VAL7_2_ADDR 0x4700081F + +#define REG_XTRIG_PROG_DP1_VAL7_3_ADDR 0x47000820 + +#define REG_XTRIG_PROG_DP1_VAL7_4_ADDR 0x47000821 + +#define REG_XTRIG_PROG_DP1_VAL8_1_ADDR 0x47000822 +#define BF_PROG_DP1_VAL8_INFO 0x47000822, 0x00002000 + +#define REG_XTRIG_PROG_DP1_VAL8_2_ADDR 0x47000823 + +#define REG_XTRIG_PROG_DP1_VAL8_3_ADDR 0x47000824 + +#define REG_XTRIG_PROG_DP1_VAL8_4_ADDR 0x47000825 + +#define REG_XTRIG_PROG_DP1_VAL9_1_ADDR 0x47000826 +#define BF_PROG_DP1_VAL9_INFO 0x47000826, 0x00002000 + +#define REG_XTRIG_PROG_DP1_VAL9_2_ADDR 0x47000827 + +#define REG_XTRIG_PROG_DP1_VAL9_3_ADDR 0x47000828 + +#define REG_XTRIG_PROG_DP1_VAL9_4_ADDR 0x47000829 + +#define REG_XTRIG_PROG_DP1_VAL10_1_ADDR 0x4700082A +#define BF_PROG_DP1_VAL10_INFO 0x4700082A, 0x00002000 + +#define REG_XTRIG_PROG_DP1_VAL10_2_ADDR 0x4700082B + +#define REG_XTRIG_PROG_DP1_VAL10_3_ADDR 0x4700082C + +#define REG_XTRIG_PROG_DP1_VAL10_4_ADDR 0x4700082D + +#define REG_RX_DIG_RESET_ADDR 0x4700082F +#define BF_SOFT_RESET_RX_A_INFO 0x4700082F, 0x00000100 +#define BF_SOFT_RESET_RX_B_INFO 0x4700082F, 0x00000101 +#define BF_RX_DP_RESET_A_INFO 0x4700082F, 0x00000102 +#define BF_RX_DP_RESET_B_INFO 0x4700082F, 0x00000103 +#define BF_RX_DIG_REGMAP_RESET_A_INFO 0x4700082F, 0x00000104 +#define BF_RX_DIG_REGMAP_RESET_B_INFO 0x4700082F, 0x00000105 + +#define REG_TX_DIG_RESET_ADDR 0x47000830 +#define BF_SOFT_RESET_TX_A_INFO 0x47000830, 0x00000100 +#define BF_SOFT_RESET_TX_B_INFO 0x47000830, 0x00000101 +#define BF_TX_DP_RESET_A_INFO 0x47000830, 0x00000102 +#define BF_TX_DP_RESET_B_INFO 0x47000830, 0x00000103 +#define BF_TX_DIG_REGMAP_RESET_A_INFO 0x47000830, 0x00000104 +#define BF_TX_DIG_REGMAP_RESET_B_INFO 0x47000830, 0x00000105 + +#define REG_VENUS_IP_RESET_A_ADDR 0x47000831 +#define BF_VENUS_ADC_REG8_A_INFO 0x47000831, 0x00000200 +#define BF_VENUS_ADC_REG32_A_INFO 0x47000831, 0x00000202 +#define BF_VENUS_ADC_DP_RESET_A_INFO 0x47000831, 0x00000404 + +#define REG_VENUS_IP_RESET_B_ADDR 0x47000832 +#define BF_VENUS_ADC_REG8_B_INFO 0x47000832, 0x00000200 +#define BF_VENUS_ADC_REG32_B_INFO 0x47000832, 0x00000202 +#define BF_VENUS_ADC_DP_RESET_B_INFO 0x47000832, 0x00000404 + +#define REG_DAC_IP_RESET_A_ADDR 0x47000833 +#define BF_DAC_RMAP_RESET_A_INFO 0x47000833, 0x00000400 +#define BF_DAC_DP_RESET_A_INFO 0x47000833, 0x00000404 + +#define REG_DAC_IP_RESET_B_ADDR 0x47000834 +#define BF_DAC_RMAP_RESET_B_INFO 0x47000834, 0x00000400 +#define BF_DAC_DP_RESET_B_INFO 0x47000834, 0x00000404 + +#define REG_SERDES_IP_RSTN_ADDR 0x47000835 +#define BF_TXSER_DP_RESET_A_INFO 0x47000835, 0x00000100 +#define BF_TXSER_DP_RESET_B_INFO 0x47000835, 0x00000101 +#define BF_RXDES_DP_RESET_A_INFO 0x47000835, 0x00000102 +#define BF_RXDES_DP_RESET_B_INFO 0x47000835, 0x00000103 +#define BF_SERDES_PLL_REG_RESET_INFO 0x47000835, 0x00000104 + +#define REG_MISC_RESETS_ADDR 0x47000836 +#define BF_SOFT_RESET_REST_INFO 0x47000836, 0x00000100 +#define BF_ANA_CENTER_RESET_INFO 0x47000836, 0x00000101 +#define BF_OSC_CLK_EN_INFO 0x47000836, 0x00000102 + +#define REG_GPIO_MODE_CONTROL_BYTE0_ADDR 0x47000839 +#define BF_GPIO_MODE_EN_INFO 0x47000839, 0x00003300 + +#define REG_GPIO_MODE_CONTROL_BYTE1_ADDR 0x4700083A + +#define REG_GPIO_MODE_CONTROL_BYTE2_ADDR 0x4700083B + +#define REG_GPIO_MODE_CONTROL_BYTE3_ADDR 0x4700083C + +#define REG_GPIO_MODE_CONTROL_BYTE4_ADDR 0x4700083D + +#define REG_GPIO_MODE_CONTROL_BYTE5_ADDR 0x4700083E + +#define REG_GPIO_MODE_CONTROL_BYTE6_ADDR 0x4700083F + +#define REG_GPIO_MODE_DIR_BYTE0_ADDR 0x47000840 +#define BF_GPIO_MODE_DIR_INFO 0x47000840, 0x00003300 + +#define REG_GPIO_MODE_DIR_BYTE1_ADDR 0x47000841 + +#define REG_GPIO_MODE_DIR_BYTE2_ADDR 0x47000842 + +#define REG_GPIO_MODE_DIR_BYTE3_ADDR 0x47000843 + +#define REG_GPIO_MODE_DIR_BYTE4_ADDR 0x47000844 + +#define REG_GPIO_MODE_DIR_BYTE5_ADDR 0x47000845 + +#define REG_GPIO_MODE_DIR_BYTE6_ADDR 0x47000846 + +#define REG_GPIO_FROM_MASTER_BYTE0_ADDR 0x47000847 +#define BF_GPIO_FROM_MASTER_INFO 0x47000847, 0x00003300 + +#define REG_GPIO_FROM_MASTER_BYTE1_ADDR 0x47000848 + +#define REG_GPIO_FROM_MASTER_BYTE2_ADDR 0x47000849 + +#define REG_GPIO_FROM_MASTER_BYTE3_ADDR 0x4700084A + +#define REG_GPIO_FROM_MASTER_BYTE4_ADDR 0x4700084B + +#define REG_GPIO_FROM_MASTER_BYTE5_ADDR 0x4700084C + +#define REG_GPIO_FROM_MASTER_BYTE6_ADDR 0x4700084D + +#define REG_GPIO_FROM_MASTER_SET_BYTE0_ADDR 0x4700084E +#define BF_GPIO_FROM_SET_INFO 0x4700084E, 0x00003300 + +#define REG_GPIO_FROM_MASTER_SET_BYTE1_ADDR 0x4700084F + +#define REG_GPIO_FROM_MASTER_SET_BYTE2_ADDR 0x47000850 + +#define REG_GPIO_FROM_MASTER_SET_BYTE3_ADDR 0x47000851 + +#define REG_GPIO_FROM_MASTER_SET_BYTE4_ADDR 0x47000852 + +#define REG_GPIO_FROM_MASTER_SET_BYTE5_ADDR 0x47000853 + +#define REG_GPIO_FROM_MASTER_SET_BYTE6_ADDR 0x47000854 + +#define REG_GPIO_FROM_MASTER_CLEAR_BYTE0_ADDR 0x47000855 +#define BF_GPIO_FROM_CLEAR_INFO 0x47000855, 0x00003300 + +#define REG_GPIO_FROM_MASTER_CLEAR_BYTE1_ADDR 0x47000856 + +#define REG_GPIO_FROM_MASTER_CLEAR_BYTE2_ADDR 0x47000857 + +#define REG_GPIO_FROM_MASTER_CLEAR_BYTE3_ADDR 0x47000858 + +#define REG_GPIO_FROM_MASTER_CLEAR_BYTE4_ADDR 0x47000859 + +#define REG_GPIO_FROM_MASTER_CLEAR_BYTE5_ADDR 0x4700085A + +#define REG_GPIO_FROM_MASTER_CLEAR_BYTE6_ADDR 0x4700085B + +#define REG_GPIO_FROM_MASTER_TOGGLE_BYTE0_ADDR 0x4700085C +#define BF_GPIO_FROM_TOGGLE_INFO 0x4700085C, 0x00003300 + +#define REG_GPIO_FROM_MASTER_TOGGLE_BYTE1_ADDR 0x4700085D + +#define REG_GPIO_FROM_MASTER_TOGGLE_BYTE2_ADDR 0x4700085E + +#define REG_GPIO_FROM_MASTER_TOGGLE_BYTE3_ADDR 0x4700085F + +#define REG_GPIO_FROM_MASTER_TOGGLE_BYTE4_ADDR 0x47000860 + +#define REG_GPIO_FROM_MASTER_TOGGLE_BYTE5_ADDR 0x47000861 + +#define REG_GPIO_FROM_MASTER_TOGGLE_BYTE6_ADDR 0x47000862 + +#define REG_GPIO_SPI_READ_BYTE0_ADDR 0x47000869 +#define BF_GPIO_SPI_READ_INFO 0x47000869, 0x00003300 + +#define REG_GPIO_SPI_READ_BYTE1_ADDR 0x4700086A + +#define REG_GPIO_SPI_READ_BYTE2_ADDR 0x4700086B + +#define REG_GPIO_SPI_READ_BYTE3_ADDR 0x4700086C + +#define REG_GPIO_SPI_READ_BYTE4_ADDR 0x4700086D + +#define REG_GPIO_SPI_READ_BYTE5_ADDR 0x4700086E + +#define REG_GPIO_SPI_READ_BYTE6_ADDR 0x4700086F + +#define REG_GPIO_SOURCE_CONTROL_ADDR(n) (0x47000870 + 1 * (n)) +#define BF_GPIO_SOURCE_CONTROL_INFO(n) (0x47000870 + 1 * (n)), 0x00000800 + +#define REG_GPIO_STAGE_SEL_BYTE0_ADDR 0x470008A3 + +#define REG_GPIO_STAGE_SEL_BYTE1_ADDR 0x470008A4 + +#define REG_GPIO_STAGE_SEL_BYTE2_ADDR 0x470008A5 + +#define REG_GPIO_STAGE_SEL_BYTE3_ADDR 0x470008A6 + +#define REG_GPIO_STAGE_SEL_BYTE4_ADDR 0x470008A7 + +#define REG_GPIO_STAGE_SEL_BYTE5_ADDR 0x470008A8 + +#define REG_GPIO_STAGE_SEL_BYTE6_ADDR 0x470008A9 + +#define REG_GPIO_STAGE_SEL_BYTE7_ADDR 0x470008AA + +#define REG_GPIO_STAGE_SEL_BYTE8_ADDR 0x470008AB + +#define REG_GPIO_STAGE_SEL_BYTE9_ADDR 0x470008AC + +#define REG_GPIO_STAGE_SEL_BYTE10_ADDR 0x470008AD + +#define REG_GPIO_STAGE_SEL_BYTE11_ADDR 0x470008AE + +#define REG_GPIO_STAGE_SEL_BYTE12_ADDR 0x470008AF + +#define REG_GPIO_QUICK_CONFIG_ADDR 0x470008B0 +#define BF_GPIO_QUICK_CONFIG_INFO 0x470008B0, 0x00000400 + +#define REG_GPIO_PINMUX_REGOUT_BYTE0_ADDR 0x470008B1 +#define BF_LNX_SW0_CTL_INFO 0x470008B1, 0x00000200 +#define BF_LNX_SW1_CTL_INFO 0x470008B1, 0x00000202 +#define BF_CLK_DELADJ_INFO 0x470008B1, 0x00000204 +#define BF_CLK_DELSTR_INFO 0x470008B1, 0x00000206 + +#define REG_GPIO_PINMUX_REGOUT_BYTE1_ADDR 0x470008B2 +#define BF_FW_IRQ_OUT_INFO 0x470008B2, 0x00000100 +#define BF_CAL_FREEZE_INFO 0x470008B2, 0x00000101 +#define BF_FW_TMU_ALARM_INFO 0x470008B2, 0x00000102 + +#define REG_COMMON_SYNCIN_CTRL_ADDR 0x470008B3 +#define BF_COMMON_SYNCIN_LINK0_INFO 0x470008B3, 0x00000100 +#define BF_COMMON_SYNCIN_LINK1_INFO 0x470008B3, 0x00000101 + +#define REG_SERDES_PLL_WR_SETUP_CYCLES_ADDR 0x470008B4 +#define BF_SERDES_PLL_ANA_BRIDGE_WR_SETUP_CYCLES_INFO 0x470008B4, 0x00000600 + +#define REG_SERDES_PLL_WR_HOLD_CYCLES_ADDR 0x470008B5 +#define BF_SERDES_PLL_ANA_BRIDGE_WR_HOLD_CYCLES_INFO 0x470008B5, 0x00000600 + +#define REG_SERDES_PLL_RD_CYCLES_ADDR 0x470008B6 +#define BF_SERDES_PLL_ANA_BRIDGE_RD_CYCLES_INFO 0x470008B6, 0x00000600 + +#define REG_RTCLK_GEN_WR_SETUP_CYCLES_ADDR 0x470008B7 +#define BF_RTCLK_GEN_ANA_BRIDGE_WR_SETUP_CYCLES_INFO 0x470008B7, 0x00000600 + +#define REG_RTCLK_GEN_WR_HOLD_CYCLES_ADDR 0x470008B8 +#define BF_RTCLK_GEN_ANA_BRIDGE_WR_HOLD_CYCLES_INFO 0x470008B8, 0x00000600 + +#define REG_RTCLK_GEN_RD_CYCLES_ADDR 0x470008B9 +#define BF_RTCLK_GEN_ANA_BRIDGE_RD_CYCLES_INFO 0x470008B9, 0x00000600 + +#define REG_WT_RT_SEL_1024X132_ADDR 0x470008BA +#define BF_RT_SEL_1024X132_INFO 0x470008BA, 0x00000200 +#define BF_WT_SEL_1024X132_INFO 0x470008BA, 0x00000202 + +#define REG_WT_RT_SEL_1024X39_ADDR 0x470008BB +#define BF_RT_SEL_1024X39_INFO 0x470008BB, 0x00000200 +#define BF_WT_SEL_1024X39_INFO 0x470008BB, 0x00000202 + +#define REG_WT_RT_SEL_4096X39_ADDR 0x470008BC +#define BF_RT_SEL_4096X39_INFO 0x470008BC, 0x00000200 +#define BF_WT_SEL_4096X39_INFO 0x470008BC, 0x00000202 + +#define REG_WT_RT_SEL_512X39_ADDR 0x470008BD +#define BF_RT_SEL_512X39_INFO 0x470008BD, 0x00000200 +#define BF_WT_SEL_512X39_INFO 0x470008BD, 0x00000202 + +#define REG_WT_RT_SEL_64X64_ADDR 0x470008BE +#define BF_RT_SEL_64X64_INFO 0x470008BE, 0x00000200 +#define BF_WT_SEL_64X64_INFO 0x470008BE, 0x00000202 + +#define REG_WT_RT_SEL_64X10_ADDR 0x470008BF +#define BF_RT_SEL_64X10_INFO 0x470008BF, 0x00000200 +#define BF_WT_SEL_64X10_INFO 0x470008BF, 0x00000202 + +#define REG_WT_RT_SEL_8192X13_ADDR 0x470008C0 +#define BF_RT_SEL_8192X13_INFO 0x470008C0, 0x00000200 +#define BF_WT_SEL_8192X13_INFO 0x470008C0, 0x00000202 + +#define REG_WT_RT_SEL_8192X39_ADDR 0x470008C1 +#define BF_RT_SEL_8192X39_INFO 0x470008C1, 0x00000200 +#define BF_WT_SEL_8192X39_INFO 0x470008C1, 0x00000202 + +#define REG_PT_RT_SEL_8192X39_ADDR 0x470008C2 +#define BF_ROM_RT_SEL_8192X39_INFO 0x470008C2, 0x00000200 +#define BF_ROM_PT_SEL_8192X39_INFO 0x470008C2, 0x00000202 + +#define REG_WT_RT_SEL_8X132_ADDR 0x470008C3 +#define BF_RT_SEL_8X132_INFO 0x470008C3, 0x00000200 +#define BF_WT_SEL_8X132_INFO 0x470008C3, 0x00000202 + +#ifdef USE_PRIVATE_BF +#define REG_ENG_MASK_REVISION_ADDR 0x470008C4 +#define BF_ENG_MASK_REVISION_MINOR_INFO 0x470008C4, 0x00000400 +#define BF_ENG_MASK_REVISION_MAJOR_INFO 0x470008C4, 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#define REG_SLICE_STREAM_TO_CORE_STREAM_INTERRUPT_ENABLE_ADDR 0x470008C5 +#define BF_SLICE_TO_CORE_IRQ_ENABLE_INFO 0x470008C5, 0x00000800 + +#define REG_TE_BYPASS_N_MMR_ADDR 0x470008C6 +#define BF_TE_BYPASS_N_MMR_INFO 0x470008C6, 0x00000100 + +#define REG_NVM_BOOT_STATUS_ADDR 0x470008C7 +#define BF_TE_BYPASS_INFO 0x470008C7, 0x00000100 +#define BF_NVM_BOOT_DONE_INFO 0x470008C7, 0x00000101 +#define BF_NVM_ERR_FLAG_TIMEOUT_INFO 0x470008C7, 0x00000102 +#define BF_NVM_ERR_FLAG_BOOT_INFO 0x470008C7, 0x00000103 +#define BF_MC_QUAL_BUSY_INFO 0x470008C7, 0x00000104 +#define BF_TE_FAULT_INFO 0x470008C7, 0x00000105 + +#define REG_EC_RX_BYTE0_ADDR 0x470008C8 +#define BF_EC_RX_INFO 0x470008C8, 0x00002000 + +#define REG_EC_RX_BYTE1_ADDR 0x470008C9 + +#define REG_EC_RX_BYTE2_ADDR 0x470008CA + +#define REG_EC_RX_BYTE3_ADDR 0x470008CB + +#define REG_EC_TX_BYTE0_ADDR 0x470008CC +#define BF_EC_TX_INFO 0x470008CC, 0x00002000 + +#define REG_EC_TX_BYTE1_ADDR 0x470008CD + +#define REG_EC_TX_BYTE2_ADDR 0x470008CE + +#define REG_EC_TX_BYTE3_ADDR 0x470008CF + +#define REG_EC_ANA_BYTE0_ADDR 0x470008D0 +#define BF_EC_ANA_INFO 0x470008D0, 0x00002000 + +#define REG_EC_ANA_BYTE1_ADDR 0x470008D1 + +#define REG_EC_ANA_BYTE2_ADDR 0x470008D2 + +#define REG_EC_ANA_BYTE3_ADDR 0x470008D3 + +#ifdef USE_PRIVATE_BF +#define REG_DIE_ID_BIT8_OVERRIDE_REG_ADDR 0x470008D5 +#define BF_DIE_ID_BIT8_OVERRIDE_INFO 0x470008D5, 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#define REG_SYSRESETN_DETECT_FLAG_ADDR 0x470008D6 +#define BF_SYSRESETN_DETECT_FLAG_INFO 0x470008D6, 0x00000100 + +#ifdef USE_PRIVATE_BF +#define REG_ACB_REG_BYTE0_ADDR 0x470008D7 +#define BF_TE_SCAN_EN_INFO 0x470008D7, 0x00000100 +#define BF_TE_JTAG_EN_INFO 0x470008D7, 0x00000103 +#define BF_TE_UART_RX_EN_INFO 0x470008D7, 0x00000104 +#define BF_ARM_JTAG_EN_INFO 0x470008D7, 0x00000105 +#define BF_C0_M3_RUN_FINAL_INFO 0x470008D7, 0x00000106 +#define BF_IRAM_ACCESS_EN_INFO 0x470008D7, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ACB_REG_BYTE1_ADDR 0x470008D8 +#define BF_TE_UART_TX_EN_INFO 0x470008D8, 0x00000100 +#define BF_IROM_ACCESS_EN_INFO 0x470008D8, 0x00000104 +#define BF_C1_M3_RUN_FINAL_INFO 0x470008D8, 0x00000106 +#define BF_SYSRESETN_FINAL_INFO 0x470008D8, 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ACB_REG_BYTE2_ADDR 0x470008D9 +#define BF_TE_OTP_MASTER_INFO 0x470008D9, 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#define REG_RX_REG_GATING_ADDR 0x470008DA +#define BF_RX_REGMAP_CLOCK_GATE_INFO 0x470008DA, 0x00000600 + +#define REG_TX_REG_GATING_ADDR 0x470008DB +#define BF_TX_REGMAP_CLOCK_GATE2_INFO 0x470008DB, 0x00000600 + +#endif /* __ADI_APOLLO_BF_CORE_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_custom.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_custom.h new file mode 100644 index 00000000000000..32424be0b7ddc2 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_custom.h @@ -0,0 +1,116 @@ + +/*! + * \brief SPI Register Definition Header File, includes customised bitfield definitions derived from auto-generated headers + * + * \copyright copyright(c) 2018 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_CUSTOM_H__ +#define __ADI_APOLLO_BF_CUSTOM_H__ + +/*=========== I N C L U D E S ============*/ + +#include "adi_apollo_bf_jrx_wrapper.h" +#include "adi_apollo_bf_jtx_dformat.h" +#include "adi_apollo_bf_txrx_cfir_top.h" +#include "adi_apollo_bf_txrx_fine_nco.h" +#include "adi_apollo_bf_core.h" +#include "adi_apollo_bf_interrupt_transmuter.h" +#include "adi_apollo_bf_apollo_profile_config.h" + + +/*============= D E F I N E S ==============*/ + +#define BF_JRX_CORE_PHASE_ADJUST_INFO_LSB(inst, n) REG_JRX_CORE_PHASE_ADJUST0_ADDR(inst, n), 0x00000800 +#define BF_JRX_CORE_PHASE_ADJUST_INFO_MSB(inst, n) REG_JRX_CORE_PHASE_ADJUST1_ADDR(inst, n), 0x00000800 + +#define BF_LINK_TOTAL_INTERP_INFO_LSB(inst, n) REG_GENERAL_JRX_CTRL_5_ADDR(inst, n), 0x00000800 +#define BF_LINK_TOTAL_INTERP_INFO_MSB(inst, n) REG_GENERAL_JRX_CTRL_6_ADDR(inst, n), 0x00000800 + +#define BF_LINK_DUC_INTERP_INFO_LSB(inst, n) REG_GENERAL_JRX_CTRL_8_ADDR(inst, n), 0x00000800 +#define BF_LINK_DUC_INTERP_INFO_MSB(inst, n) REG_GENERAL_JRX_CTRL_9_ADDR(inst, n), 0x00000800 + +#define BF_INVALID_EN_0_INFO(inst) REG_INVALID_EN_ADDR(inst), 0x00000100 +#define BF_INVALID_EN_1_INFO(inst) REG_INVALID_EN_ADDR(inst), 0x00000101 + +#define BF_COEFF_PROFILE_SEL0_INFO(inst) REG_CFIR_PROFILE_ADDR(inst), 0x00000100 +#define BF_COEFF_PROFILE_SEL1_INFO(inst) REG_CFIR_PROFILE_ADDR(inst), 0x00000101 +#define BF_COEFF_PROFILE_SEL2_INFO(inst) REG_CFIR_PROFILE_ADDR(inst), 0x00000102 +#define BF_COEFF_PROFILE_SEL3_INFO(inst) REG_CFIR_PROFILE_ADDR(inst), 0x00000103 + +#define BF_AUTOFLIP_INCDIR_FTW_TXRX_FINE_NCO_INFO(inst) REG_AUTOFLIP_INCDIR_ADDR(inst), 0x00000100 +#define BF_AUTOFLIP_INCDIR_PHOFST_TXRX_FINE_NCO_INFO(inst) REG_AUTOFLIP_INCDIR_ADDR(inst), 0x00000102 + +#define BF_AUTO_INC_DECB_FTW_TXRX_FINE_NCO_INFO(inst) REG_AUTO_INC_DECB_ADDR(inst), 0x00000100 +#define BF_AUTO_INC_DECB_PHOFST_TXRX_FINE_NCO_INFO(inst) REG_AUTO_INC_DECB_ADDR(inst), 0x00000102 +#define BF_HOP_PHASE_INC_INFO(inst) REG_HOP_PHASE_INC0_ADDR(inst), 0x00002000 +#define BF_HOP_PHASE_OFFSET_INFO(inst) REG_HOP_PHASE_OFFSET0_ADDR(inst), 0x00001000 + +#define MEM_CODE_MEMORY_B_0 (0x02000000U) //arm_mem.yda +#define MEM_CODE_MEMORY_A_6 (0x01030000U) //arm_mem.yda +#define MEM_SYS_MEMORY_B_0 (0x21000000U) //arm_mem.yda +#define MEM_SYS_MEMORY_B_MAX (0x21050000U + 0x8000U) //arm_mem.yda +#define BF_CPU_0_PRIMARY BF_SCRATCH_REG_INFO(16) //FW startup code +#define BF_CPU_1_PRIMARY BF_SCRATCH_REG_INFO(17) //FW startup code +#define BF_EC_RAM_LOCK_INFO REG_EC_ANA_BYTE3_ADDR, 0x00000106 +#define BF_EC_RAM_LOCK_MASK (0x40) +#define BF_CONFIG_TRANSFER_DONE REG_ALT_BOOT_ADDR(0), 0x00000100 +#define BF_WAITING_FOR_CONFIG_TRANSFER_STATUS REG_ALT_BOOT_ADDR(0), 0x00000101 +#define BF_BOOT_STALL_STATUS REG_ALT_BOOT_ADDR(0), 0x00000102 +#define BF_BOOT_DONE_STATUS REG_ALT_BOOT_ADDR(0), 0x00000107 +#define BF_BOOT_ERROR REG_ALT_BOOT_ADDR(1), 0x00000800 +#define BF_BOOT_STATUS REG_ALT_BOOT_ADDR(2), 0x00000800 +#define REG_RAM_BOOT_ERROR_PTR (0x21000424U) +#define BF_RAM_BOOT_CORE0_STATUS (0x47000200U), 0x00000800 +#define BF_RAM_BOOT_CORE1_STATUS (0x47000201U), 0x00000800 + +#define BF_DEVICE_PROFILE_CRC_CHECK_STATUS BF_SCRATCH_REG_INFO(6) + +#define BF_NVMB_TE_BYPASS_INFO (0x4C0023E8U), 0x00000106U +#define BF_TE_BOOT_READY_SET REG_ALT_BOOT_ADDR(23), 0x00000800 +#define REG_SECURE_BOOT_STAGE0 (0x4C006342U) +#define REG_SECURE_BOOT_STAGE1 (0x4C006343U) + +#define BF_FW_IRQ_OUT_SOURCE_INFO REG_SCRATCH_REGS_ADDR(0x90), 0x00001800 + +#define REG_ADC_SLICE_MODE_SWITCH_ENABLE_ADDR REG_SCRATCH_REGS_ADDR(0xBD) +#define REG_ADC_SLICE_MODE_SWITCH_CHANNEL_MASK_ADDR REG_SCRATCH_REGS_ADDR(0xBC) +#define REG_ADC_SLICE_MODE_SWITCH_TRIGGER_ADDR REG_TRIGGER_ADDR(14) + +// NVM CAL Data Fuse Status Register and BitFields +#define REG_NVM_CALDATA_FUSED_ADDR REG_SCRATCH_REGS_ADDR(0xA2) +#define BF_ADC_NVM_CALDATA_FUSED_INFO REG_NVM_CALDATA_FUSED_ADDR, 0x00000100 +#define BF_DAC_NVM_CALDATA_FUSED_INFO REG_NVM_CALDATA_FUSED_ADDR, 0x00000101 +#define BF_SERDES_JRX_NVM_CALDATA_FUSED_INFO REG_NVM_CALDATA_FUSED_ADDR, 0x00000102 +#define BF_SERDES_JTX_NVM_CALDATA_FUSED_INFO REG_NVM_CALDATA_FUSED_ADDR, 0x00000103 + +// Enhancements to adi_apollo_bf_apollo_profile_config.h +#define BF_PC_RX_FNCO_SLICE_SELECT_INFO(inst) (0x00000100 + inst) +#define BF_PC_TX_FNCO_SLICE_SELECT_INFO(inst) (0x00000110 + inst) +#define BF_PC_RX_CNCO_SLICE_SELECT_INFO(inst) (0x00000100 + inst) +#define BF_PC_TX_CNCO_SLICE_SELECT_INFO(inst) (0x00000108 + inst) +#define BF_PC_RX_CFIR_SLICE_SELECT_INFO(inst) (0x00000100 + inst) +#define BF_PC_TX_CFIR_SLICE_SELECT_INFO(inst) (0x00000110 + inst) +#define BF_PC_RX_PFILT_SLICE_SELECT_INFO(inst) (0x00000100 + inst) +#define BF_PC_TX_PFILT_SLICE_SELECT_INFO(inst) (0x00000102 + inst) +#define BF_PC_RX_DR_SLICE_SELECT_INFO(inst) (0x00000100 + inst) +#define BF_PC_TX_DR_SLICE_SELECT_INFO(inst) (0x00000108 + inst) +#define BF_PC_BMEM_HOP_SLICE_SELECT_INFO(inst) (0x00000100 + inst) + +// Individual datapath control for LB1/LB2 +#define BF_LB1_EN0_INFO(inst) ((inst) + 0x00000025), 0x00000100 +#define BF_LB2_EN0_INFO(inst) ((inst) + 0x00000027), 0x00000100 + +// Apollo Part Variant +#define REG_PART_VARIANT_SW_MXFE_ADDR REG_SCRATCH_REGS_ADDR(201) +#define REG_PART_VARIANT_SW_TRIM_ADDR REG_SCRATCH_REGS_ADDR(202) + +#endif /* __ADI_APOLLO_BF_CUSTOM_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_ec.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_ec.h new file mode 100644 index 00000000000000..7558294d1fb9c9 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_ec.h @@ -0,0 +1,146 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:21 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_EC_H__ +#define __ADI_APOLLO_BF_EC_H__ + +/*============= D E F I N E S ==============*/ +#define REG_CHIPID_0_EC_ADDR 0x4C004200 + +#define REG_CHIPID_1_EC_ADDR 0x4C004201 + +#define REG_CHIPID_2_EC_ADDR 0x4C004202 + +#define REG_CHIPID_3_EC_ADDR 0x4C004203 + +#define REG_CHIPID_4_EC_ADDR 0x4C004204 + +#define REG_CHIPID_5_EC_ADDR 0x4C004205 + +#define REG_CHIPID_6_EC_ADDR 0x4C004206 + +#define REG_CHIPID_7_EC_ADDR 0x4C004207 + +#define REG_CHIPID_8_EC_ADDR 0x4C004208 + +#define REG_CHIPID_9_EC_ADDR 0x4C004209 + +#define REG_CHIPID_10_EC_ADDR 0x4C00420A + +#define REG_CHIPID_11_EC_ADDR 0x4C00420B + +#define REG_CHIPID_12_EC_ADDR 0x4C00420C + +#define REG_CHIPID_13_EC_ADDR 0x4C00420D + +#define REG_CHIPID_14_EC_ADDR 0x4C00420E + +#define REG_CHIPID_15_EC_ADDR 0x4C00420F + +#define REG_GROUPID_0_EC_ADDR 0x4C004210 +#define BF_NVM_GROUPID_INFO 0x4C004210, 0x00002000 + +#define REG_GROUPID_1_EC_ADDR 0x4C004211 + +#define REG_GROUPID_2_EC_ADDR 0x4C004212 + +#define REG_GROUPID_3_EC_ADDR 0x4C004213 + +#ifdef USE_PRIVATE_BF +#define REG_NVM_GENERAL_CTRL0_ADDR 0x4C004214 +#define BF_NVM_GENERAL_CTRL_INFO 0x4C004214, 0x00004000 +#endif /* USE_PRIVATE_BF */ + +#define REG_NVM_GENERAL_CTRL1_ADDR 0x4C004215 + +#define REG_NVM_GENERAL_CTRL2_ADDR 0x4C004216 + +#define REG_NVM_GENERAL_CTRL3_ADDR 0x4C004217 + +#define REG_NVM_GENERAL_CTRL4_ADDR 0x4C004218 + +#define REG_NVM_GENERAL_CTRL5_ADDR 0x4C004219 + +#define REG_NVM_GENERAL_CTRL6_ADDR 0x4C00421A + +#define REG_NVM_GENERAL_CTRL7_ADDR 0x4C00421B + +#ifdef USE_PRIVATE_BF +#define REG_NVM_EC_TORX0_ADDR 0x4C00421C +#define BF_NVM_EC_TORX_INFO 0x4C00421C, 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_NVM_EC_TORX1_ADDR 0x4C00421D + +#define REG_NVM_EC_TORX2_ADDR 0x4C00421E + +#define REG_NVM_EC_TORX3_ADDR 0x4C00421F + +#ifdef USE_PRIVATE_BF +#define REG_NVM_EC_TOTX0_ADDR 0x4C004220 +#define BF_NVM_EC_TOTX_INFO 0x4C004220, 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_NVM_EC_TOTX1_ADDR 0x4C004221 + +#define REG_NVM_EC_TOTX2_ADDR 0x4C004222 + +#define REG_NVM_EC_TOTX3_ADDR 0x4C004223 + +#ifdef USE_PRIVATE_BF +#define REG_NVM_EC_TOANA0_ADDR 0x4C004224 +#define BF_NVM_EC_TOANA_INFO 0x4C004224, 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_NVM_EC_TOANA1_ADDR 0x4C004225 + +#define REG_NVM_EC_TOANA2_ADDR 0x4C004226 + +#define REG_NVM_EC_TOANA3_ADDR 0x4C004227 + +#define REG_NVM_REG0X3_ADDR 0x4C004228 +#define BF_NVM_REG0X3_INFO 0x4C004228, 0x00000800 + +#define REG_NVM_REG0X4_ADDR 0x4C004229 +#define BF_NVM_REG0X4_INFO 0x4C004229, 0x00000800 + +#define REG_NVM_REG0X5_ADDR 0x4C00422A +#define BF_NVM_REG0X5_INFO 0x4C00422A, 0x00000800 + +#define REG_NVM_REG0X6_ADDR 0x4C00422B +#define BF_NVM_REG0X6_INFO 0x4C00422B, 0x00000800 + +#define REG_NVM_REG0XC_ADDR 0x4C00422C +#define BF_NVM_REG0XC_INFO 0x4C00422C, 0x00000800 + +#define REG_NVM_REG0XD_ADDR 0x4C00422D +#define BF_NVM_REG0XD_INFO 0x4C00422D, 0x00000800 + +#define REG_SEQUENTIAL_SN_0_EC_ADDR 0x4C00422E +#define BF_SEQUENTIAL_SN_0_EC_INFO 0x4C00422E, 0x00000800 + +#define REG_SEQUENTIAL_SN_1_EC_ADDR 0x4C00422F +#define BF_SEQUENTIAL_SN_1_EC_INFO 0x4C00422F, 0x00000800 + +#define REG_MAIN_FW_REVID_0_ADDR 0x4C004230 +#define BF_NVM_FW_MAIN_REVID_INFO 0x4C004230, 0x00002000 + +#define REG_MAIN_FW_REVID_1_ADDR 0x4C004231 + +#define REG_MAIN_FW_REVID_2_ADDR 0x4C004232 + +#define REG_MAIN_FW_REVID_3_ADDR 0x4C004233 + +#endif /* __ADI_APOLLO_BF_EC_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_hsci.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_hsci.h new file mode 100644 index 00000000000000..a8e9d1894473b6 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_hsci.h @@ -0,0 +1,143 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:19 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_HSCI_H__ +#define __ADI_APOLLO_BF_HSCI_H__ + +/*============= D E F I N E S ==============*/ +#define REG_MAIN_CTRL_ADDR 0x4C000000 +#define BF_HSCI_EN_INFO 0x4C000000, 0x00000100 +#define BF_HSCI_RX_LINKUP_MODE_INFO 0x4C000000, 0x00000101 +#define BF_HSCI_LPBK_MODE_INFO 0x4C000000, 0x00000102 +#define BF_HSCI_RD_AUTO_INC_DIS_INFO 0x4C000000, 0x00000103 +#define BF_HSCI_WR_AUTO_INC_DIS_INFO 0x4C000000, 0x00000104 +#define BF_HSCI_ERR_IRQ_CLR_INFO 0x4C000000, 0x00000105 +#define BF_HSCI_SOFT_RESET_INFO 0x4C000000, 0x00000106 +#define BF_HSCI_HARD_RESET_INFO 0x4C000000, 0x00000107 + +#define REG_MAIN_CTRL2_ADDR 0x4C000001 +#define BF_HSCI_BURST_MODE_INFO 0x4C000001, 0x00000200 +#define BF_DIS_SEND_ERR_INFO 0x4C000001, 0x00000102 +#define BF_HSCI_AUTO_LINKUP_INFO 0x4C000001, 0x00000103 +#define BF_TXCLK_ADJ_OVERRIDE_INFO 0x4C000001, 0x00000104 +#define BF_LINK_ACTIVE_INFO 0x4C000001, 0x00000105 +#define BF_HSCI_READ_IN_PROG_INFO 0x4C000001, 0x00000106 +#define BF_HSCI_WRITE_IN_PROG_INFO 0x4C000001, 0x00000107 + +#define REG_RX_CLK_ADJUST_ADDR 0x4C000002 +#define BF_HSCI_RXCLK_ADJ_INFO 0x4C000002, 0x00000400 +#define BF_HSCI_RXCLK_INV_INFO 0x4C000002, 0x00000104 + +#define REG_TX_CLK_ADJUST_ADDR 0x4C000003 +#define BF_HSCI_TXCLK_ADJ_INFO 0x4C000003, 0x00000400 +#define BF_HSCI_TXCLK_INV_INFO 0x4C000003, 0x00000104 + +#define REG_ERROR_STATUS_ADDR 0x4C000004 +#define BF_UNKNOWN_CMD_INFO 0x4C000004, 0x00000100 +#define BF_BAD_PARITY_DET_INFO 0x4C000004, 0x00000101 +#define BF_ADDR_SIZE_ERR_INFO 0x4C000004, 0x00000102 +#define BF_BYTE_NUM_SIZE_ERR_INFO 0x4C000004, 0x00000103 +#define BF_WR_FIFO_FULL_INFO 0x4C000004, 0x00000104 +#define BF_RD_FIFO_FULL_INFO 0x4C000004, 0x00000105 +#define BF_READY_TO_ERR_INFO 0x4C000004, 0x00000106 +#define BF_HRESP_ERR_INFO 0x4C000004, 0x00000107 + +#define REG_ERROR_FLAG_DIS_ADDR 0x4C000005 +#define BF_UNKNOWN_CMD_DIS_INFO 0x4C000005, 0x00000100 +#define BF_BAD_PARITY_DET_DIS_INFO 0x4C000005, 0x00000101 +#define BF_ADDR_SIZE_ERR_DIS_INFO 0x4C000005, 0x00000102 +#define BF_BYTE_NUM_SIZE_ERR_DIS_INFO 0x4C000005, 0x00000103 +#define BF_WR_FIFO_FULL_DIS_INFO 0x4C000005, 0x00000104 +#define BF_RD_FIFO_FULL_DIS_INFO 0x4C000005, 0x00000105 +#define BF_READY_TO_ERR_DIS_INFO 0x4C000005, 0x00000106 +#define BF_HRESP_ERR_DIS_INFO 0x4C000005, 0x00000107 + +#define REG_HREADY_TO_REG_ADDR 0x4C000006 +#define BF_READY_TIME_OUT_CNT_INFO 0x4C000006, 0x00000200 +#define BF_HSCI_CTRL_RX_EYE_EN_INFO 0x4C000006, 0x00000102 + +#define REG_POS_EYE_DIAG_LB_ADDR 0x4C000007 +#define BF_HSCI_DIG_EYE_POS_INFO 0x4C000007, 0x00001000 + +#define REG_POS_EYE_DIAG_HB_ADDR 0x4C000008 + +#define REG_NEG_EYE_DIAG_LB_ADDR 0x4C000009 +#define BF_HSCI_DIG_EYE_NEG_INFO 0x4C000009, 0x00001000 + +#define REG_NEG_EYE_DIAG_HB_ADDR 0x4C00000A + +#define REG_FSM_STATUS_ADDR 0x4C00000B +#define BF_RXDES_STATE_INFO 0x4C00000B, 0x00000300 +#define BF_TXFIFO_STATE_INFO 0x4C00000B, 0x00000404 + +#define REG_AHB_FSM_STATUS_ADDR 0x4C00000C +#define BF_AHB_BUS_STATE_INFO 0x4C00000C, 0x00000300 +#define BF_AUTO_LINK_FSM_INFO 0x4C00000C, 0x00000404 + +#define REG_AUTO_LINK_TABLE_LO_ADDR 0x4C00000D +#define BF_AUTO_LINK_TABLE_INFO 0x4C00000D, 0x00001000 + +#define REG_AUTO_LINK_TABLE_HI_ADDR 0x4C00000E + +#define REG_AUTO_LINK_CNTR_DEF_ADDR 0x4C00000F +#define BF_ACQ_CNTR_DEF_INFO 0x4C00000F, 0x00000200 +#define BF_LPBK_CNTR_DEF_INFO 0x4C00000F, 0x00000202 +#define BF_LOCK_FRM_CNTR_DEF_INFO 0x4C00000F, 0x00000204 + +#define REG_AUTO_LINK_RXCLK_ADJ_ADDR 0x4C000010 +#define BF_AUTO_RXCLK_ADJ_INFO 0x4C000010, 0x00000400 +#define BF_AUTO_RXCLK_INV_INFO 0x4C000010, 0x00000104 + +#define REG_AUTO_LINK_TXCLK_ADJ_ADDR 0x4C000011 +#define BF_AUTO_TXCLK_ADJ_INFO 0x4C000011, 0x00000400 +#define BF_AUTO_TXCLK_INV_INFO 0x4C000011, 0x00000104 + +#define REG_HSCI_PAD_CTRL_ADDR 0x4C000012 +#define BF_HSCI_CTRL_RX_ONCHIP_TERM_INFO 0x4C000012, 0x00000100 +#define BF_HSCI_CTRL_RX_PD_INFO 0x4C000012, 0x00000101 +#define BF_HSCI_CTRL_TX_LVL_INFO 0x4C000012, 0x00000302 +#define BF_HSCI_CTRL_TX_PD_INFO 0x4C000012, 0x00000105 +#define BF_HSCI_CTRL_FRNT_END_TX_CK_INV_INFO 0x4C000012, 0x00000106 +#define BF_HSCI_VER_B_NA_INFO 0x4C000012, 0x00000107 + +#define REG_HSCI_AFE_CTRL_ADDR 0x4C000013 +#define BF_HSCI_TERM_TRIM_INFO 0x4C000013, 0x00000300 +#define BF_HSCI_AC_COUP_ON_INFO 0x4C000013, 0x00000103 +#define BF_HSCI_MB_R_TRIM_INFO 0x4C000013, 0x00000304 +#define BF_HSCI_PD_MB_INFO 0x4C000013, 0x00000107 + +#define REG_HSCI_DFX_CTRL_ADDR 0x4C000014 +#define BF_HSCI_RX_TEST_MODE_INFO 0x4C000014, 0x00000100 +#define BF_HSCI_TX_TEST_MODE_INFO 0x4C000014, 0x00000101 +#define BF_HSCI_TSTMODE_EN_INFO 0x4C000014, 0x00000102 +#define BF_HSCI_CLKTST_OUT_INFO 0x4C000014, 0x00000103 +#define BF_HSCI_DATATST_OUT_INFO 0x4C000014, 0x00000104 +#define BF_HSCI_CLKTST_IN_INFO 0x4C000014, 0x00000105 +#define BF_HSCI_DATATST_IN_INFO 0x4C000014, 0x00000106 +#define BF_HSCI_RX_TEST_LFSR_ACQ_INFO 0x4C000014, 0x00000107 + +#define REG_HSCI_RX_BER_ADDR 0x4C000015 +#define BF_HSCI_RX_BER_CNT_INFO 0x4C000015, 0x00002000 + +#define REG_HSCI_RX_BER2_ADDR 0x4C000016 + +#define REG_HSCI_RX_BER3_ADDR 0x4C000017 + +#define REG_HSCI_RX_BER4_ADDR 0x4C000018 + +#define REG_HSCI_ERR_INFO_ADDR 0x4C000019 +#define BF_HSCI_LINK_ERR_INFO_INFO 0x4C000019, 0x00000800 + +#endif /* __ADI_APOLLO_BF_HSCI_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_interrupt_aggregator.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_interrupt_aggregator.h new file mode 100644 index 00000000000000..dcaab1d4c2852b --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_interrupt_aggregator.h @@ -0,0 +1,23 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:17 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_INTERRUPT_AGGREGATOR_H__ +#define __ADI_APOLLO_BF_INTERRUPT_AGGREGATOR_H__ + +/*============= D E F I N E S ==============*/ +#define REG_INTERRUPT_MASK_ADDR(n) (0x41200000 + 4 * (n)) +#define BF_MASK_INFO(n) (0x41200000 + 4 * (n)), 0x00000800 + +#endif /* __ADI_APOLLO_BF_INTERRUPT_AGGREGATOR_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_interrupt_transmuter.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_interrupt_transmuter.h new file mode 100644 index 00000000000000..a7c5ef62378487 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_interrupt_transmuter.h @@ -0,0 +1,47 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:17 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_INTERRUPT_TRANSMUTER_H__ +#define __ADI_APOLLO_BF_INTERRUPT_TRANSMUTER_H__ + +/*============= D E F I N E S ==============*/ +#define REG_INTERRUPT_ENABLE_ADDR(n) (0x46800000 + 4 * (n)) +#define BF_INTERRUPT_ENABLE_INFO(n) (0x46800000 + 4 * (n)), 0x00002000 + +#define REG_LEVEL_EDGEB_ADDR(n) (0x46800044 + 4 * (n)) +#define BF_LEVEL_EDGEB_INFO(n) (0x46800044 + 4 * (n)), 0x00002000 + +#define REG_POS_MASK_ADDR(n) (0x46800088 + 4 * (n)) +#define BF_INT_POS_MASK_INFO(n) (0x46800088 + 4 * (n)), 0x00002000 + +#define REG_NEG_MASK_ADDR(n) (0x468000CC + 4 * (n)) +#define BF_INT_NEG_MASK_INFO(n) (0x468000CC + 4 * (n)), 0x00002000 + +#define REG_TRIGGER_ADDR(n) (0x46800110 + 4 * (n)) +#define BF_TRIGGER_INFO(n) (0x46800110 + 4 * (n)), 0x00002000 + +#define REG_STATUS_INTERRUPT_TRANSMUTER_ADDR(n) (0x46800154 + 4 * (n)) +#define BF_INT_STATUS_INFO(n) (0x46800154 + 4 * (n)), 0x00002000 + +#define REG_RAW_STATUS_ADDR(n) (0x46800198 + 4 * (n)) +#define BF_RAW_STATUS_INFO(n) (0x46800198 + 4 * (n)), 0x00002000 + +#define REG_EDGE_STATUS_ADDR(n) (0x468001DC + 4 * (n)) +#define BF_EDGE_STATUS_INFO(n) (0x468001DC + 4 * (n)), 0x00002000 + +#define REG_MASTER_ID_READ_ADDR 0x46800220 +#define BF_MASTER_ID_INFO 0x46800220, 0x00002000 + +#endif /* __ADI_APOLLO_BF_INTERRUPT_TRANSMUTER_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_itm.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_itm.h new file mode 100644 index 00000000000000..ff10c6e300a05e --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_itm.h @@ -0,0 +1,41 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:17 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_ITM_H__ +#define __ADI_APOLLO_BF_ITM_H__ + +/*============= D E F I N E S ==============*/ +#define REG_PKTZR_STIM_ADDR(n) (0x46300000 + 4 * (n)) +#define BF_PKTZR_FIFOREADY_INFO(n) (0x46300000 + 4 * (n)), 0x00000100 + +#define REG_PKTZR_TER_ADDR 0x46300E00 +#define BF_PKTZR_TEN_INFO 0x46300E00, 0x00002000 + +#define REG_PKTZR_TCSR_ADDR 0x46300E80 +#define BF_PKTZR_ENABLE_INFO 0x46300E80, 0x00000100 +#define BF_PKTZR_SYNC_EN_INFO 0x46300E80, 0x00000102 +#define BF_PKTZR_TRACE_BUSID_INFO 0x46300E80, 0x00000710 +#define BF_PKTZR_BUSY_INFO 0x46300E80, 0x00000117 + +#define REG_PKTZR_SYNC_CTRL_ADDR 0x46300E90 +#define BF_PKTZR_SYNC_COUNT_INFO 0x46300E90, 0x00001400 + +#define REG_PKTZR_INTR_CTRL_ADDR 0x46300EA0 +#define BF_PKTZR_OVFL_INTEN_INFO 0x46300EA0, 0x00000100 + +#define REG_PKTZR_INTR_STAT_ADDR 0x46300EA4 +#define BF_PKTZR_OVFL_INTSTAT_INFO 0x46300EA4, 0x00000100 + +#endif /* __ADI_APOLLO_BF_ITM_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_jrx_core.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_jrx_core.h new file mode 100644 index 00000000000000..0e658977bb2d4f --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_jrx_core.h @@ -0,0 +1,135 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:25 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_JRX_CORE_H__ +#define __ADI_APOLLO_BF_JRX_CORE_H__ + +/*============= D E F I N E S ==============*/ +#define JRX_CORE_JRX_TX_DIGITAL0 0x61604000 +#define JRX_CORE_JRX_TX_DIGITAL1 0x61E04000 + +#define REG_JRX_CORE_CONFIG_ADDR(inst) ((inst) + 0x00000000) +#define BF_JRX_LINK_TYPE_INFO(inst) ((inst) + 0x00000000), 0x00000200 + +#ifdef USE_PRIVATE_BF +#define REG_JRX_CORE_CONFIG0_ADDR(inst, n) ((inst) + 0x00000001 + 1 * (n)) +#define BF_JRX_CORE_CHKSUM_DISABLE_INFO(inst, n) ((inst) + 0x00000001 + 1 * (n)), 0x00000100 +#define BF_JRX_CORE_CHKSUM_LSB_ALG_INFO(inst, n) ((inst) + 0x00000001 + 1 * (n)), 0x00000101 +#define BF_JRX_CORE_CLEAR_SYNC_NE_COUNT_INFO(inst, n) ((inst) + 0x00000001 + 1 * (n)), 0x00000102 +#define BF_JRX_CORE_PCLK_ERROR_CLEAR_INFO(inst, n) ((inst) + 0x00000001 + 1 * (n)), 0x00000103 +#define BF_JRX_CORE_SYSREF_FOR_RELINK_INFO(inst, n) ((inst) + 0x00000001 + 1 * (n)), 0x00000104 +#define BF_JRX_CORE_SYSREF_FOR_STARTUP_INFO(inst, n) ((inst) + 0x00000001 + 1 * (n)), 0x00000105 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_CORE_SAMPLE_XBAR_A_ADDR(inst, n) ((inst) + 0x00000010 + 1 * (n)) +#define BF_JRX_CORE_CONV_SEL_LINK0_INFO(inst, n) ((inst) + 0x00000010 + 1 * (n)), 0x00000700 +#define BF_JRX_CORE_CONV_DISABLE_LINK0_INFO(inst, n) ((inst) + 0x00000010 + 1 * (n)), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_CORE_SAMPLE_XBAR_B_ADDR(inst, n) ((inst) + 0x00000090 + 1 * (n)) +#define BF_JRX_CORE_CONV_SEL_LINK1_INFO(inst, n) ((inst) + 0x00000090 + 1 * (n)), 0x00000700 +#define BF_JRX_CORE_CONV_DISABLE_LINK1_INFO(inst, n) ((inst) + 0x00000090 + 1 * (n)), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_CORE_SYNC_N_SEL_ADDR(inst, n) ((inst) + 0x00000110 + 1 * (n)) +#define BF_JRX_CORE_SYNC_N_SEL_INFO(inst, n) ((inst) + 0x00000110 + 1 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_CORE_SYNC_NE_COUNT_ADDR(inst, n) ((inst) + 0x00000112 + 1 * (n)) +#define BF_JRX_CORE_SYNC_NE_COUNT_INFO(inst, n) ((inst) + 0x00000112 + 1 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_CORE_BUF_DEPTH_ADDR(inst, n) ((inst) + 0x00000114 + 1 * (n)) +#define BF_JRX_CORE_BUF_DEPTH_INFO(inst, n) ((inst) + 0x00000114 + 1 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_JRX_CORE_PHASE_ADJUST0_ADDR(inst, n) ((inst) + 0x00000116 + 1 * (n)) +#define BF_JRX_CORE_PHASE_ADJUST_INFO(inst, n) ((inst) + 0x00000116 + 1 * (n)), 0x00001000 + +#define REG_JRX_CORE_PHASE_ADJUST1_ADDR(inst, n) ((inst) + 0x00000118 + 1 * (n)) + +#define REG_JRX_CORE_LANE_PHASE_DIFF_0_ADDR(inst, n) ((inst) + 0x0000011B + 1 * (n)) +#define BF_JRX_CORE_PHASE_DIFF_INFO(inst, n) ((inst) + 0x0000011B + 1 * (n)), 0x00001000 + +#define REG_JRX_CORE_LANE_PHASE_DIFF_1_ADDR(inst, n) ((inst) + 0x0000013C + 1 * (n)) + +#define REG_JRX_TPL_CONFIG0_ADDR(inst, n) ((inst) + 0x0000015C + 1 * (n)) +#ifdef USE_PRIVATE_BF +#define BF_JRX_CORE_CFG_INVALID_INFO(inst, n) ((inst) + 0x0000015C + 1 * (n)), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_JRX_CORE_USR_DATA_RDY_INFO(inst, n) ((inst) + 0x0000015C + 1 * (n)), 0x00000101 +#define BF_JRX_CORE_SYSREF_RCVD_INFO(inst, n) ((inst) + 0x0000015C + 1 * (n)), 0x00000102 +#ifdef USE_PRIVATE_BF +#define BF_JRX_CORE_SYSREF_N_SHOT_ENABLE_INFO(inst, n) ((inst) + 0x0000015C + 1 * (n)), 0x00000103 +#endif /* USE_PRIVATE_BF */ +#ifdef USE_PRIVATE_BF +#define BF_JRX_CORE_SYSREF_N_SHOT_COUNT_INFO(inst, n) ((inst) + 0x0000015C + 1 * (n)), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#define REG_JRX_TPL_CONFIG1_ADDR(inst, n) ((inst) + 0x0000015E + 1 * (n)) +#ifdef USE_PRIVATE_BF +#define BF_JRX_CORE_SYSREF_PHASE_ERR_INFO(inst, n) ((inst) + 0x0000015E + 1 * (n)), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#ifdef USE_PRIVATE_BF +#define BF_JRX_CORE_SYSREF_CLR_PHASE_ERR_INFO(inst, n) ((inst) + 0x0000015E + 1 * (n)), 0x00000101 +#endif /* USE_PRIVATE_BF */ +#ifdef USE_PRIVATE_BF +#define BF_JRX_CORE_SYSREF_IGNORE_WHEN_LINKED_INFO(inst, n) ((inst) + 0x0000015E + 1 * (n)), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#ifdef USE_PRIVATE_BF +#define BF_JRX_CORE_SYSREF_ENABLE_INFO(inst, n) ((inst) + 0x0000015E + 1 * (n)), 0x00000103 +#endif /* USE_PRIVATE_BF */ +#ifdef USE_PRIVATE_BF +#define BF_JRX_CORE_SYNC_FORMAT_EN_INFO(inst, n) ((inst) + 0x0000015E + 1 * (n)), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#ifdef USE_PRIVATE_BF +#define BF_JRX_CORE_BUF_ERROR_INFO(inst, n) ((inst) + 0x0000015E + 1 * (n)), 0x00000106 +#endif /* USE_PRIVATE_BF */ +#define BF_JRX_TPL_BUF_ERROR_INFO(inst, n) ((inst) + 0x0000015E + 1 * (n)), 0x00000107 + +#ifdef USE_PRIVATE_BF +#define REG_JRX_TPL_LANE_BUF_DEPTH_A_ADDR(inst, n) ((inst) + 0x00000160 + 1 * (n)) +#define BF_JRX_TPL_BUF_DEPTH_LINK0_INFO(inst, n) ((inst) + 0x00000160 + 1 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_TPL_LANE_BUF_DEPTH_B_ADDR(inst, n) ((inst) + 0x00000170 + 1 * (n)) +#define BF_JRX_TPL_BUF_DEPTH_LINK1_INFO(inst, n) ((inst) + 0x00000170 + 1 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_JRX_CORE_LANE_XBAR_A_ADDR(inst, n) ((inst) + 0x00000180 + 1 * (n)) +#define BF_JRX_CORE_LANE_SEL_LINK0_INFO(inst, n) ((inst) + 0x00000180 + 1 * (n)), 0x00000500 +#ifdef USE_PRIVATE_BF +#define BF_JRX_CORE_PCLK_SLOW_ERROR_LINK0_INFO(inst, n) ((inst) + 0x00000180 + 1 * (n)), 0x00000106 +#endif /* USE_PRIVATE_BF */ +#ifdef USE_PRIVATE_BF +#define BF_JRX_CORE_PCLK_FAST_ERROR_LINK0_INFO(inst, n) ((inst) + 0x00000180 + 1 * (n)), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#define REG_JRX_CORE_LANE_XBAR_B_ADDR(inst, n) ((inst) + 0x00000190 + 1 * (n)) +#define BF_JRX_CORE_LANE_SEL_LINK1_INFO(inst, n) ((inst) + 0x00000190 + 1 * (n)), 0x00000500 +#ifdef USE_PRIVATE_BF +#define BF_JRX_CORE_PCLK_SLOW_ERROR_LINK1_INFO(inst, n) ((inst) + 0x00000190 + 1 * (n)), 0x00000106 +#endif /* USE_PRIVATE_BF */ +#ifdef USE_PRIVATE_BF +#define BF_JRX_CORE_PCLK_FAST_ERROR_LINK1_INFO(inst, n) ((inst) + 0x00000190 + 1 * (n)), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#endif /* __ADI_APOLLO_BF_JRX_CORE_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_jrx_dac_sample_prbs.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_jrx_dac_sample_prbs.h new file mode 100644 index 00000000000000..12cd9f4e5d085b --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_jrx_dac_sample_prbs.h @@ -0,0 +1,102 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:25 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_JRX_DAC_SAMPLE_PRBS_H__ +#define __ADI_APOLLO_BF_JRX_DAC_SAMPLE_PRBS_H__ + +/*============= D E F I N E S ==============*/ +#define JRX_DAC_SAMPLE_PRBS_JRX_TX_DIGITAL0 0x61620000 +#define JRX_DAC_SAMPLE_PRBS_JRX_TX_DIGITAL1 0x61E20000 + +#define REG_SAMPLE_PRBS_CTRL0_ADDR(inst) ((inst) + 0x00000000) +#define BF_PRBS_MODE_INFO(inst) ((inst) + 0x00000000), 0x00000300 +#define BF_SWAP_ENDIANNESS_INFO(inst) ((inst) + 0x00000000), 0x00000103 +#define BF_PRBS_INV_REAL_INFO(inst) ((inst) + 0x00000000), 0x00000104 +#define BF_PRBS_INV_IMAG_INFO(inst) ((inst) + 0x00000000), 0x00000105 +#define BF_CLR_ERRORS_INFO(inst) ((inst) + 0x00000000), 0x00000106 +#define BF_SAMPLE_PRBS_ENABLE_INFO(inst) ((inst) + 0x00000000), 0x00000107 + +#define REG_SAMPLE_PRBS_CTRL1_ADDR(inst) ((inst) + 0x00000001) +#define BF_UPDATE_ERROR_COUNT_INFO(inst) ((inst) + 0x00000001), 0x00000100 +#define BF_PRBS_ERR_RD_MODE_INFO(inst) ((inst) + 0x00000001), 0x00000101 +#define BF_PRBS_ERR_RD_CHNL_CLR_INFO(inst) ((inst) + 0x00000001), 0x00000102 +#define BF_PRBS_CHNL_SEL_INFO(inst) ((inst) + 0x00000001), 0x00000303 + +#define REG_SAMPLE_PRBS_STATUS0_ADDR(inst) ((inst) + 0x00000002) +#define BF_PRBS_INVALID_DATA_FLAG_I_INFO(inst) ((inst) + 0x00000002), 0x00000100 +#define BF_PRBS_INVALID_DATA_FLAG_Q_INFO(inst) ((inst) + 0x00000002), 0x00000101 +#define BF_PRBS_ERROR_FLAG_I_INFO(inst) ((inst) + 0x00000002), 0x00000102 +#define BF_PRBS_ERROR_FLAG_Q_INFO(inst) ((inst) + 0x00000002), 0x00000103 +#define BF_PRBS_INV_FLAG_REAL_INFO(inst) ((inst) + 0x00000002), 0x00000104 +#define BF_PRBS_INV_FLAG_IMAG_INFO(inst) ((inst) + 0x00000002), 0x00000105 + +#define REG_SAMPLE_PRBS_STATUS1_ADDR(inst) ((inst) + 0x00000003) +#define BF_ERROR_COUNT_I_INFO(inst) ((inst) + 0x00000003), 0x00001800 + +#define REG_SAMPLE_PRBS_STATUS2_ADDR(inst) ((inst) + 0x00000004) + +#define REG_SAMPLE_PRBS_STATUS3_ADDR(inst) ((inst) + 0x00000005) + +#define REG_SAMPLE_PRBS_STATUS4_ADDR(inst) ((inst) + 0x00000006) +#define BF_ERROR_COUNT_Q_INFO(inst) ((inst) + 0x00000006), 0x00001800 + +#define REG_SAMPLE_PRBS_STATUS5_ADDR(inst) ((inst) + 0x00000007) + +#define REG_SAMPLE_PRBS_STATUS6_ADDR(inst) ((inst) + 0x00000008) + +#define REG_SAMPLE_PRBS_DEBUG_ADDR(inst) ((inst) + 0x00000009) +#define BF_PRBS_ERR_RD_CHNL_READBACK_INFO(inst) ((inst) + 0x00000009), 0x00000300 + +#define REG_TMODE_USR_LSB_P0_JRX_DAC_SAMPLE_PRBS_ADDR(inst, n) ((inst) + 0x0000000A + 1 * (n)) +#define BF_TMODE_USR_PAT0_JRX_DAC_SAMPLE_PRBS_INFO(inst, n) ((inst) + 0x0000000A + 1 * (n)), 0x00001000 + +#define REG_TMODE_USR_MSB_P0_JRX_DAC_SAMPLE_PRBS_ADDR(inst, n) ((inst) + 0x0000000C + 1 * (n)) + +#define REG_TMODE_USR_LSB_P1_JRX_DAC_SAMPLE_PRBS_ADDR(inst, n) ((inst) + 0x0000000E + 1 * (n)) +#define BF_TMODE_USR_PAT1_JRX_DAC_SAMPLE_PRBS_INFO(inst, n) ((inst) + 0x0000000E + 1 * (n)), 0x00001000 + +#define REG_TMODE_USR_MSB_P1_JRX_DAC_SAMPLE_PRBS_ADDR(inst, n) ((inst) + 0x00000010 + 1 * (n)) + +#define REG_TMODE_USR_LSB_P2_JRX_DAC_SAMPLE_PRBS_ADDR(inst, n) ((inst) + 0x00000012 + 1 * (n)) +#define BF_TMODE_USR_PAT2_JRX_DAC_SAMPLE_PRBS_INFO(inst, n) ((inst) + 0x00000012 + 1 * (n)), 0x00001000 + +#define REG_TMODE_USR_MSB_P2_JRX_DAC_SAMPLE_PRBS_ADDR(inst, n) ((inst) + 0x00000014 + 1 * (n)) + +#define REG_TMODE_USR_LSB_P3_JRX_DAC_SAMPLE_PRBS_ADDR(inst, n) ((inst) + 0x00000016 + 1 * (n)) +#define BF_TMODE_USR_PAT3_JRX_DAC_SAMPLE_PRBS_INFO(inst, n) ((inst) + 0x00000016 + 1 * (n)), 0x00001000 + +#define REG_TMODE_USR_MSB_P3_JRX_DAC_SAMPLE_PRBS_ADDR(inst, n) ((inst) + 0x00000018 + 1 * (n)) + +#define REG_TMODE_USR_LSB_P4_JRX_DAC_SAMPLE_PRBS_ADDR(inst, n) ((inst) + 0x0000001A + 1 * (n)) +#define BF_TMODE_USR_PAT4_JRX_DAC_SAMPLE_PRBS_INFO(inst, n) ((inst) + 0x0000001A + 1 * (n)), 0x00001000 + +#define REG_TMODE_USR_MSB_P4_JRX_DAC_SAMPLE_PRBS_ADDR(inst, n) ((inst) + 0x0000001C + 1 * (n)) + +#define REG_TMODE_USR_LSB_P5_JRX_DAC_SAMPLE_PRBS_ADDR(inst, n) ((inst) + 0x0000001E + 1 * (n)) +#define BF_TMODE_USR_PAT5_JRX_DAC_SAMPLE_PRBS_INFO(inst, n) ((inst) + 0x0000001E + 1 * (n)), 0x00001000 + +#define REG_TMODE_USR_MSB_P5_JRX_DAC_SAMPLE_PRBS_ADDR(inst, n) ((inst) + 0x00000020 + 1 * (n)) + +#define REG_TMODE_USR_LSB_P6_JRX_DAC_SAMPLE_PRBS_ADDR(inst, n) ((inst) + 0x00000022 + 1 * (n)) +#define BF_TMODE_USR_PAT6_JRX_DAC_SAMPLE_PRBS_INFO(inst, n) ((inst) + 0x00000022 + 1 * (n)), 0x00001000 + +#define REG_TMODE_USR_MSB_P6_JRX_DAC_SAMPLE_PRBS_ADDR(inst, n) ((inst) + 0x00000024 + 1 * (n)) + +#define REG_TMODE_USR_LSB_P7_JRX_DAC_SAMPLE_PRBS_ADDR(inst, n) ((inst) + 0x00000026 + 1 * (n)) +#define BF_TMODE_USR_PAT7_JRX_DAC_SAMPLE_PRBS_INFO(inst, n) ((inst) + 0x00000026 + 1 * (n)), 0x00001000 + +#define REG_TMODE_USR_MSB_P7_JRX_DAC_SAMPLE_PRBS_ADDR(inst, n) ((inst) + 0x00000028 + 1 * (n)) + +#endif /* __ADI_APOLLO_BF_JRX_DAC_SAMPLE_PRBS_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_jrx_dl_204b.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_jrx_dl_204b.h new file mode 100644 index 00000000000000..1477258ca1c0bf --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_jrx_dl_204b.h @@ -0,0 +1,165 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:25 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_JRX_DL_204B_H__ +#define __ADI_APOLLO_BF_JRX_DL_204B_H__ + +/*============= D E F I N E S ==============*/ +#define JRX_DL_204B_JRX_TX_DIGITAL0 0x6160C000 +#define JRX_DL_204B_JRX_TX_DIGITAL1 0x61E0C000 + +#define REG_JRX_DL_204B_CONFIG0_ADDR(inst) ((inst) + 0x00000380) +#ifdef USE_PRIVATE_BF +#define BF_JRX_DL_204B_AR_ECNTR_INFO(inst) ((inst) + 0x00000380), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#ifdef USE_PRIVATE_BF +#define BF_JRX_DL_204B_CGS_SEL_INFO(inst) ((inst) + 0x00000380), 0x00000101 +#endif /* USE_PRIVATE_BF */ +#define BF_JRX_DL_204B_CHAR_REPL_DIS_INFO(inst) ((inst) + 0x00000380), 0x00000102 +#ifdef USE_PRIVATE_BF +#define BF_JRX_DL_204B_ENA_RAMP_CHECK_INFO(inst) ((inst) + 0x00000380), 0x00000103 +#endif /* USE_PRIVATE_BF */ +#define BF_JRX_DL_204B_FCHK_N_INFO(inst) ((inst) + 0x00000380), 0x00000104 +#define BF_JRX_DL_204B_FORCESYNCREQ_INFO(inst) ((inst) + 0x00000380), 0x00000105 +#define BF_JRX_DL_204B_ILS_MODE_INFO(inst) ((inst) + 0x00000380), 0x00000106 +#ifdef USE_PRIVATE_BF +#define BF_JRX_DL_204B_QUAL_RDERR_INFO(inst) ((inst) + 0x00000380), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_DL_204B_CONFIG1_ADDR(inst) ((inst) + 0x00000381) +#define BF_JRX_DL_204B_REPDATATEST_INFO(inst) ((inst) + 0x00000381), 0x00000100 +#define BF_JRX_DL_204B_SYNC_ASSERT_MASK_INFO(inst) ((inst) + 0x00000381), 0x00000301 +#define BF_JRX_DL_204B_SYNC_ERR_ENABLE_INFO(inst) ((inst) + 0x00000381), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_DL_204B_IRQ_CLR0_ADDR(inst) ((inst) + 0x00000382) +#define BF_JRX_DL_204B_IRQ_CLR_INFO(inst) ((inst) + 0x00000382), 0x00000900 +#endif /* USE_PRIVATE_BF */ + +#define REG_JRX_DL_204B_IRQ_CLR1_ADDR(inst) ((inst) + 0x00000383) + +#define REG_JRX_DL_204B_ETH_ADDR(inst) ((inst) + 0x00000384) +#define BF_JRX_DL_204B_ETH_INFO(inst) ((inst) + 0x00000384), 0x00000800 + +#define REG_JRX_DL_204B_KSYNC_ADDR(inst) ((inst) + 0x00000386) +#define BF_JRX_DL_204B_KSYNC_INFO(inst) ((inst) + 0x00000386), 0x00000800 + +#define REG_JRX_DL_204B_LANE_RXCFG_00_ADDR(inst, n) ((inst) + 0x00000390 + 1 * (n)) +#define BF_JRX_DL_204B_L0_RXCFG_0_INFO(inst, n) ((inst) + 0x00000390 + 1 * (n)), 0x00000800 + +#define REG_JRX_DL_204B_LANE_RXCFG_01_ADDR(inst, n) ((inst) + 0x000003A0 + 1 * (n)) +#define BF_JRX_DL_204B_L0_RXCFG_1_INFO(inst, n) ((inst) + 0x000003A0 + 1 * (n)), 0x00000800 + +#define REG_JRX_DL_204B_LANE_RXCFG_02_ADDR(inst, n) ((inst) + 0x000003B0 + 1 * (n)) +#define BF_JRX_DL_204B_L0_RXCFG_2_INFO(inst, n) ((inst) + 0x000003B0 + 1 * (n)), 0x00000800 + +#define REG_JRX_DL_204B_LANE_RXCFG_03_ADDR(inst, n) ((inst) + 0x000003C0 + 1 * (n)) +#define BF_JRX_DL_204B_L0_RXCFG_3_INFO(inst, n) ((inst) + 0x000003C0 + 1 * (n)), 0x00000800 + +#define REG_JRX_DL_204B_LANE_RXCFG_04_ADDR(inst, n) ((inst) + 0x000003D0 + 1 * (n)) +#define BF_JRX_DL_204B_L0_RXCFG_4_INFO(inst, n) ((inst) + 0x000003D0 + 1 * (n)), 0x00000800 + +#define REG_JRX_DL_204B_LANE_RXCFG_05_ADDR(inst, n) ((inst) + 0x000003E0 + 1 * (n)) +#define BF_JRX_DL_204B_L0_RXCFG_5_INFO(inst, n) ((inst) + 0x000003E0 + 1 * (n)), 0x00000800 + +#define REG_JRX_DL_204B_LANE_RXCFG_06_ADDR(inst, n) ((inst) + 0x000003F0 + 1 * (n)) +#define BF_JRX_DL_204B_L0_RXCFG_6_INFO(inst, n) ((inst) + 0x000003F0 + 1 * (n)), 0x00000800 + +#define REG_JRX_DL_204B_LANE_RXCFG_07_ADDR(inst, n) ((inst) + 0x00000400 + 1 * (n)) +#define BF_JRX_DL_204B_L0_RXCFG_7_INFO(inst, n) ((inst) + 0x00000400 + 1 * (n)), 0x00000800 + +#define REG_JRX_DL_204B_LANE_RXCFG_08_ADDR(inst, n) ((inst) + 0x00000410 + 1 * (n)) +#define BF_JRX_DL_204B_L0_RXCFG_8_INFO(inst, n) ((inst) + 0x00000410 + 1 * (n)), 0x00000800 + +#define REG_JRX_DL_204B_LANE_RXCFG_09_ADDR(inst, n) ((inst) + 0x00000420 + 1 * (n)) +#define BF_JRX_DL_204B_L0_RXCFG_9_INFO(inst, n) ((inst) + 0x00000420 + 1 * (n)), 0x00000800 + +#define REG_JRX_DL_204B_LANE_RXCFG_10_ADDR(inst, n) ((inst) + 0x00000430 + 1 * (n)) +#define BF_JRX_DL_204B_L0_RXCFG_10_INFO(inst, n) ((inst) + 0x00000430 + 1 * (n)), 0x00000800 + +#define REG_JRX_DL_204B_LANE_RXCFG_11_ADDR(inst, n) ((inst) + 0x00000440 + 1 * (n)) +#define BF_JRX_DL_204B_L0_RXCFG_11_INFO(inst, n) ((inst) + 0x00000440 + 1 * (n)), 0x00000800 + +#define REG_JRX_DL_204B_LANE_RXCFG_12_ADDR(inst, n) ((inst) + 0x00000450 + 1 * (n)) +#define BF_JRX_DL_204B_L0_RXCFG_12_INFO(inst, n) ((inst) + 0x00000450 + 1 * (n)), 0x00000800 + +#define REG_JRX_DL_204B_LANE_RXCFG_13_ADDR(inst, n) ((inst) + 0x00000460 + 1 * (n)) +#define BF_JRX_DL_204B_L0_RXCFG_13_INFO(inst, n) ((inst) + 0x00000460 + 1 * (n)), 0x00000800 + +#define REG_JRX_DL_204B_LANE_ECNT0_ADDR(inst, n) ((inst) + 0x00000470 + 1 * (n)) +#define BF_JRX_DL_204B_ECNT_ENA_INFO(inst, n) ((inst) + 0x00000470 + 1 * (n)), 0x00000300 +#ifdef USE_PRIVATE_BF +#define BF_JRX_DL_204B_ECNT_RST_INFO(inst, n) ((inst) + 0x00000470 + 1 * (n)), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#define REG_JRX_DL_204B_LANE_ECNT1_ADDR(inst, n) ((inst) + 0x00000480 + 1 * (n)) +#ifdef USE_PRIVATE_BF +#define BF_JRX_DL_204B_ECNT_TCH_INFO(inst, n) ((inst) + 0x00000480 + 1 * (n)), 0x00000300 +#endif /* USE_PRIVATE_BF */ +#define BF_JRX_DL_204B_ECNT_TCR_INFO(inst, n) ((inst) + 0x00000480 + 1 * (n)), 0x00000304 + +#define REG_JRX_DL_204B_LANE_ERR_STATUS_ADDR(inst, n) ((inst) + 0x00000490 + 1 * (n)) +#define BF_JRX_DL_204B_BDE_INFO(inst, n) ((inst) + 0x00000490 + 1 * (n)), 0x00000100 +#define BF_JRX_DL_204B_CGS_INFO(inst, n) ((inst) + 0x00000490 + 1 * (n)), 0x00000101 +#define BF_JRX_DL_204B_CKS_INFO(inst, n) ((inst) + 0x00000490 + 1 * (n)), 0x00000102 +#define BF_JRX_DL_204B_FS_INFO(inst, n) ((inst) + 0x00000490 + 1 * (n)), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_JRX_DL_204B_ILD_INFO(inst, n) ((inst) + 0x00000490 + 1 * (n)), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_JRX_DL_204B_ILS_INFO(inst, n) ((inst) + 0x00000490 + 1 * (n)), 0x00000105 +#define BF_JRX_DL_204B_NIT_INFO(inst, n) ((inst) + 0x00000490 + 1 * (n)), 0x00000106 +#define BF_JRX_DL_204B_UEK_INFO(inst, n) ((inst) + 0x00000490 + 1 * (n)), 0x00000107 + +#define REG_JRX_DL_204B_LANE_BD_ADDR(inst, n) ((inst) + 0x000004A0 + 1 * (n)) +#define BF_JRX_DL_204B_BD_CNT_INFO(inst, n) ((inst) + 0x000004A0 + 1 * (n)), 0x00000800 + +#define REG_JRX_DL_204B_LANE_UEK_ADDR(inst, n) ((inst) + 0x000004B0 + 1 * (n)) +#define BF_JRX_DL_204B_UEK_CNT_INFO(inst, n) ((inst) + 0x000004B0 + 1 * (n)), 0x00000800 + +#define REG_JRX_DL_204B_LANE_NIT_ADDR(inst, n) ((inst) + 0x000004C0 + 1 * (n)) +#define BF_JRX_DL_204B_NIT_CNT_INFO(inst, n) ((inst) + 0x000004C0 + 1 * (n)), 0x00000800 + +#define REG_JRX_DL_204B_LANE_FCHK_ADDR(inst, n) ((inst) + 0x000004D0 + 1 * (n)) +#define BF_JRX_DL_204B_LL_FCHK_INFO(inst, n) ((inst) + 0x000004D0 + 1 * (n)), 0x00000800 + +#define REG_JRX_DL_204B_LANE_FCMP_ADDR(inst, n) ((inst) + 0x000004E0 + 1 * (n)) +#define BF_JRX_DL_204B_LL_FCMP_INFO(inst, n) ((inst) + 0x000004E0 + 1 * (n)), 0x00000800 + +#define REG_JRX_DL_204B_LANE_LID_ADDR(inst, n) ((inst) + 0x000004F0 + 1 * (n)) +#define BF_JRX_DL_204B_LL_LID_INFO(inst, n) ((inst) + 0x000004F0 + 1 * (n)), 0x00000500 + +#define REG_JRX_DL_204B_LANE_STATUS_ADDR(inst, n) ((inst) + 0x00000500 + 1 * (n)) +#ifdef USE_PRIVATE_BF +#define BF_JRX_DL_204B_EOF_EVENT_INFO(inst, n) ((inst) + 0x00000500 + 1 * (n)), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#ifdef USE_PRIVATE_BF +#define BF_JRX_DL_204B_EOMF_EVENT_INFO(inst, n) ((inst) + 0x00000500 + 1 * (n)), 0x00000101 +#endif /* USE_PRIVATE_BF */ +#ifdef USE_PRIVATE_BF +#define BF_JRX_DL_204B_FS_LOST_INFO(inst, n) ((inst) + 0x00000500 + 1 * (n)), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_JRX_DL_204B_SYNC_N_INFO(inst, n) ((inst) + 0x00000500 + 1 * (n)), 0x00000103 +#define BF_JRX_DL_204B_USER_DATA_INFO(inst, n) ((inst) + 0x00000500 + 1 * (n)), 0x00000104 +#define BF_JRX_DL_204B_VALID_CKSUM_INFO(inst, n) ((inst) + 0x00000500 + 1 * (n)), 0x00000105 + +#define REG_JRX_DL_204B_LANE_IRQ_VEC0_ADDR(inst, n) ((inst) + 0x00000510 + 1 * (n)) +#define BF_JRX_DL_204B_IRQ_VEC_INFO(inst, n) ((inst) + 0x00000510 + 1 * (n)), 0x00000900 + +#define REG_JRX_DL_204B_LANE_IRQ_VEC1_ADDR(inst, n) ((inst) + 0x00000520 + 1 * (n)) +#define BF_JRX_DL_204B_IRQ_INFO(inst, n) ((inst) + 0x00000520 + 1 * (n)), 0x00000107 + +#endif /* __ADI_APOLLO_BF_JRX_DL_204B_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_jrx_dl_204c.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_jrx_dl_204c.h new file mode 100644 index 00000000000000..18b0644dc2e849 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_jrx_dl_204c.h @@ -0,0 +1,80 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:25 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_JRX_DL_204C_H__ +#define __ADI_APOLLO_BF_JRX_DL_204C_H__ + +/*============= D E F I N E S ==============*/ +#define JRX_DL_204C_JRX_TX_DIGITAL0 0x61610000 +#define JRX_DL_204C_JRX_TX_DIGITAL1 0x61E10000 + +#define REG_JRX_DL_204C_CONFIG_ADDR(inst) ((inst) + 0x00000000) +#ifdef USE_PRIVATE_BF +#define BF_JRX_DL_204C_CRC_FEC_REVERSE_CFG_INFO(inst) ((inst) + 0x00000000), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#ifdef USE_PRIVATE_BF +#define BF_JRX_DL_204C_LINK_LOCK_INFO(inst) ((inst) + 0x00000000), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_JRX_DL_204C_CLR_ERR_CNT_INFO(inst) ((inst) + 0x00000000), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_JRX_DL_204C_HOLD_ERR_CNT_INFO(inst) ((inst) + 0x00000000), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_JRX_DL_204C_SYNC_WORD_SEL_INFO(inst) ((inst) + 0x00000000), 0x00000206 + +#define REG_JRX_DL_204C_MB_ADDR(inst) ((inst) + 0x00000001) +#define BF_JRX_DL_204C_MB_ERR_CFG_INFO(inst) ((inst) + 0x00000001), 0x00000400 +#define BF_JRX_DL_204C_MB_REQD_CFG_INFO(inst) ((inst) + 0x00000001), 0x00000404 + +#define REG_JRX_DL_204C_SH_ERR_ADDR(inst) ((inst) + 0x00000002) +#define BF_JRX_DL_204C_SH_ERR_CFG_INFO(inst) ((inst) + 0x00000002), 0x00000600 + +#define REG_JRX_DL_204C_SH_REQD_ADDR(inst) ((inst) + 0x00000003) +#define BF_JRX_DL_204C_SH_REQD_CFG_INFO(inst) ((inst) + 0x00000003), 0x00000600 + +#define REG_JRX_DL_204C_EMB_ADDR(inst) ((inst) + 0x00000005) +#define BF_JRX_DL_204C_EMB_ERR_CFG_INFO(inst) ((inst) + 0x00000005), 0x00000300 +#define BF_JRX_DL_204C_EMB_REQD_CFG_INFO(inst) ((inst) + 0x00000005), 0x00000404 + +#ifdef USE_PRIVATE_BF +#define REG_JRX_DL_204C_LANE_SKEW0_ADDR(inst, n) ((inst) + 0x00000010 + 1 * (n)) +#define BF_JRX_DL_204C_LANE_SKEW_INFO(inst, n) ((inst) + 0x00000010 + 1 * (n)), 0x00000900 +#endif /* USE_PRIVATE_BF */ + +#define REG_JRX_DL_204C_LANE_SKEW1_ADDR(inst, n) ((inst) + 0x00000020 + 1 * (n)) + +#define REG_JRX_DL_204C_LANE_STATUS_ADDR(inst, n) ((inst) + 0x00000030 + 1 * (n)) +#define BF_JRX_DL_204C_STATE_INFO(inst, n) ((inst) + 0x00000030 + 1 * (n)), 0x00000300 + +#define REG_JRX_DL_204C_LANE_SH_ERR_ADDR(inst, n) ((inst) + 0x00000040 + 1 * (n)) +#define BF_JRX_DL_204C_SH_ERR_CNT_INFO(inst, n) ((inst) + 0x00000040 + 1 * (n)), 0x00000600 + +#ifdef USE_PRIVATE_BF +#define REG_JRX_DL_204C_LANE_FEC_ERR_ADDR(inst, n) ((inst) + 0x00000050 + 1 * (n)) +#define BF_JRX_DL_204C_FEC_ERR_CNT_INFO(inst, n) ((inst) + 0x00000050 + 1 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_DL_204C_LANE_FEC_UNC_ERR_ADDR(inst, n) ((inst) + 0x00000060 + 1 * (n)) +#define BF_JRX_DL_204C_FEC_UNCORRECTABLE_ERR_CNT_INFO(inst, n) ((inst) + 0x00000060 + 1 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_JRX_DL_204C_LANE_CRC_ERR_ADDR(inst, n) ((inst) + 0x00000070 + 1 * (n)) +#define BF_JRX_DL_204C_CRC_ERR_CNT_INFO(inst, n) ((inst) + 0x00000070 + 1 * (n)), 0x00000800 + +#define REG_JRX_DL_204C_LANE_BLOCK_ERR_ADDR(inst, n) ((inst) + 0x00000080 + 1 * (n)) +#define BF_JRX_DL_204C_MB_ERR_CNT_INFO(inst, n) ((inst) + 0x00000080 + 1 * (n)), 0x00000400 +#define BF_JRX_DL_204C_EMB_ERR_CNT_INFO(inst, n) ((inst) + 0x00000080 + 1 * (n)), 0x00000404 + +#endif /* __ADI_APOLLO_BF_JRX_DL_204C_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_jrx_jesd_l0.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_jrx_jesd_l0.h new file mode 100644 index 00000000000000..a8a9b809f92600 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_jrx_jesd_l0.h @@ -0,0 +1,78 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:25 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_JRX_JESD_L0_H__ +#define __ADI_APOLLO_BF_JRX_JESD_L0_H__ + +/*============= D E F I N E S ==============*/ +#define JRX_JESD_L0_JRX_TX_DIGITAL0 0x61608000 +#define JRX_JESD_L0_JRX_TX_DIGITAL1 0x61E08000 + +#define REG_JRX_L0_DID_ADDR(inst, n) ((inst) + 0x00000000 + 1 * (n)) +#define BF_JRX_CORE_DID_CFG_INFO(inst, n) ((inst) + 0x00000000 + 1 * (n)), 0x00000800 + +#define REG_JRX_L0_RESERVED0_ADDR(inst, n) ((inst) + 0x00000002 + 1 * (n)) + +#define REG_JRX_L0_LID_ADDR(inst, n) ((inst) + 0x00000004 + 1 * (n)) +#define BF_JRX_CORE_LID_CFG_LINK0_INFO(inst, n) ((inst) + 0x00000004 + 1 * (n)), 0x00000500 + +#define REG_JRX_L0_LID_1_ADDR(inst, n) ((inst) + 0x00000014 + 1 * (n)) +#define BF_JRX_CORE_LID_CFG_LINK1_INFO(inst, n) ((inst) + 0x00000014 + 1 * (n)), 0x00000500 + +#define REG_JRX_L0_DSCR_L_ADDR(inst, n) ((inst) + 0x00000024 + 1 * (n)) +#define BF_JRX_CORE_L_CFG_INFO(inst, n) ((inst) + 0x00000024 + 1 * (n)), 0x00000500 +#define BF_JRX_CORE_DSCR_CFG_INFO(inst, n) ((inst) + 0x00000024 + 1 * (n)), 0x00000107 + +#define REG_JRX_L0_F_ADDR(inst, n) ((inst) + 0x00000026 + 1 * (n)) +#define BF_JRX_CORE_F_CFG_INFO(inst, n) ((inst) + 0x00000026 + 1 * (n)), 0x00000800 + +#define REG_JRX_L0_K_ADDR(inst, n) ((inst) + 0x00000028 + 1 * (n)) +#define BF_JRX_CORE_K_CFG_INFO(inst, n) ((inst) + 0x00000028 + 1 * (n)), 0x00000800 + +#define REG_JRX_L0_M_ADDR(inst, n) ((inst) + 0x0000002A + 1 * (n)) +#define BF_JRX_CORE_M_CFG_INFO(inst, n) ((inst) + 0x0000002A + 1 * (n)), 0x00000800 + +#define REG_JRX_L0_CS_N_ADDR(inst, n) ((inst) + 0x0000002C + 1 * (n)) +#define BF_JRX_CORE_N_CFG_INFO(inst, n) ((inst) + 0x0000002C + 1 * (n)), 0x00000500 +#define BF_JRX_CORE_CS_CFG_INFO(inst, n) ((inst) + 0x0000002C + 1 * (n)), 0x00000206 + +#define REG_JRX_L0_SUBCLASSV_NP_ADDR(inst, n) ((inst) + 0x0000002E + 1 * (n)) +#define BF_JRX_CORE_NP_CFG_INFO(inst, n) ((inst) + 0x0000002E + 1 * (n)), 0x00000500 +#define BF_JRX_CORE_SUBCLASSV_CFG_INFO(inst, n) ((inst) + 0x0000002E + 1 * (n)), 0x00000305 + +#define REG_JRX_L0_JESDV_S_ADDR(inst, n) ((inst) + 0x00000030 + 1 * (n)) +#define BF_JRX_CORE_S_CFG_INFO(inst, n) ((inst) + 0x00000030 + 1 * (n)), 0x00000500 +#define BF_JRX_CORE_JESDV_CFG_INFO(inst, n) ((inst) + 0x00000030 + 1 * (n)), 0x00000305 + +#define REG_JRX_L0_HD_ADDR(inst, n) ((inst) + 0x00000032 + 1 * (n)) +#define BF_JRX_CORE_HD_CFG_INFO(inst, n) ((inst) + 0x00000032 + 1 * (n)), 0x00000107 + +#define REG_JRX_L0_RESERVED1_ADDR(inst, n) ((inst) + 0x00000034 + 1 * (n)) + +#define REG_JRX_L0_RESERVED2_ADDR(inst, n) ((inst) + 0x00000036 + 1 * (n)) + +#define REG_JRX_L0_CHKSUM_ADDR(inst, n) ((inst) + 0x00000040 + 1 * (n)) +#define BF_JRX_CORE_CHKSUM_CFG_LINK0_INFO(inst, n) ((inst) + 0x00000040 + 1 * (n)), 0x00000800 + +#define REG_JRX_L0_CHKSUM_1_ADDR(inst, n) ((inst) + 0x00000050 + 1 * (n)) +#define BF_JRX_CORE_CHKSUM_CFG_LINK1_INFO(inst, n) ((inst) + 0x00000050 + 1 * (n)), 0x00000800 + +#define REG_JRX_L0_NS_ADDR(inst, n) ((inst) + 0x00000060 + 1 * (n)) +#define BF_JRX_CORE_NS_CFG_INFO(inst, n) ((inst) + 0x00000060 + 1 * (n)), 0x00000500 + +#define REG_JRX_L0_E_ADDR(inst, n) ((inst) + 0x00000062 + 1 * (n)) +#define BF_JRX_CORE_E_CFG_INFO(inst, n) ((inst) + 0x00000062 + 1 * (n)), 0x00000500 + +#endif /* __ADI_APOLLO_BF_JRX_JESD_L0_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_jrx_phy_ifx.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_jrx_phy_ifx.h new file mode 100644 index 00000000000000..9dfb775a31ebe6 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_jrx_phy_ifx.h @@ -0,0 +1,30 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:25 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_JRX_PHY_IFX_H__ +#define __ADI_APOLLO_BF_JRX_PHY_IFX_H__ + +/*============= D E F I N E S ==============*/ +#define JRX_PHY_IFX_JRX_TX_DIGITAL0 0x61614000 +#define JRX_PHY_IFX_JRX_TX_DIGITAL1 0x61E14000 + +#ifdef USE_PRIVATE_BF +#define REG_JRX_PHY_IFX_LANE_PHY_SPLIT_ADDR(inst, n) ((inst) + 0x00000000 + 1 * (n)) +#define BF_JRX_IFX_LOG2_SPLIT_INFO(inst, n) ((inst) + 0x00000000 + 1 * (n)), 0x00000200 +#define BF_JRX_IFX_LANE_SEL_INFO(inst, n) ((inst) + 0x00000000 + 1 * (n)), 0x00000502 +#define BF_JRX_IFX_LANE_INVERSE_INFO(inst, n) ((inst) + 0x00000000 + 1 * (n)), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#endif /* __ADI_APOLLO_BF_JRX_PHY_IFX_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_jrx_private.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_jrx_private.h new file mode 100644 index 00000000000000..aac9836743de32 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_jrx_private.h @@ -0,0 +1,34 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:25 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_JRX_PRIVATE_H__ +#define __ADI_APOLLO_BF_JRX_PRIVATE_H__ + +/*============= D E F I N E S ==============*/ +#define JRX_PRIVATE_JRX_TX_DIGITAL0 0x6161C000 +#define JRX_PRIVATE_JRX_TX_DIGITAL1 0x61E1C000 + +#ifdef USE_PRIVATE_BF +#define REG_JRX_CORE_0_CONTROL_ADDR(inst) ((inst) + 0x00000000) +#define BF_JRX_CONV_SEL_SPI_EN_INFO(inst) ((inst) + 0x00000000), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TXFE_LOOPBACK_MODE_ADDR(inst) ((inst) + 0x00000001) +#define BF_TXFE_LOOPBACK_MODES_INFO(inst) ((inst) + 0x00000001), 0x00000300 +#define BF_LP_SYNC_CONNECT_EN_INFO(inst) ((inst) + 0x00000001), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#endif /* __ADI_APOLLO_BF_JRX_PRIVATE_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_jrx_prngtop.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_jrx_prngtop.h new file mode 100644 index 00000000000000..0d0272908e046d --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_jrx_prngtop.h @@ -0,0 +1,51 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:25 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_JRX_PRNGTOP_H__ +#define __ADI_APOLLO_BF_JRX_PRNGTOP_H__ + +/*============= D E F I N E S ==============*/ +#define JRX_PRNGTOP_JRX_TX_DIGITAL0 0x61624000 +#define JRX_PRNGTOP_JRX_TX_DIGITAL1 0x61E24000 + +#define REG_PRNGTOP_CTRL_ADDR(inst) ((inst) + 0x00000000) +#ifdef USE_PRIVATE_BF +#define BF_TX_GLOBAL_BIST_ENABLE_INFO(inst) ((inst) + 0x00000000), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_TX_GLOBAL_BIST_START_INFO(inst) ((inst) + 0x00000000), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_TX_GLOBAL_BIST_MODE_INFO(inst) ((inst) + 0x00000000), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#ifdef USE_PRIVATE_BF +#define BF_TX_GLOBAL_BIST_FLUSH_LEN_INFO(inst) ((inst) + 0x00000000), 0x00000203 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_PRNGTOP_STATUS_ADDR(inst) ((inst) + 0x00000001) +#define BF_TX_GLOBAL_BIST_CLR_INFO(inst) ((inst) + 0x00000001), 0x00000100 +#define BF_TX_GLOBAL_BIST_RUN_INFO(inst) ((inst) + 0x00000001), 0x00000101 +#define BF_TX_GLOBAL_BIST_DONE_INFO(inst) ((inst) + 0x00000001), 0x00000102 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_BIST_LENGTH_LSB_ADDR(inst) ((inst) + 0x00000002) +#define BF_TX_GLOBAL_BIST_LENGTH_INFO(inst) ((inst) + 0x00000002), 0x00001300 +#endif /* USE_PRIVATE_BF */ + +#define REG_BIST_LENGTH_MID_ADDR(inst) ((inst) + 0x00000003) + +#define REG_BIST_LENGTH_MSB_ADDR(inst) ((inst) + 0x00000004) + +#endif /* __ADI_APOLLO_BF_JRX_PRNGTOP_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_jrx_test.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_jrx_test.h new file mode 100644 index 00000000000000..82ced26cf96f99 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_jrx_test.h @@ -0,0 +1,72 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:25 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_JRX_TEST_H__ +#define __ADI_APOLLO_BF_JRX_TEST_H__ + +/*============= D E F I N E S ==============*/ +#define JRX_TEST_JRX_TX_DIGITAL0 0x61600000 +#define JRX_TEST_JRX_TX_DIGITAL1 0x61E00000 + +#ifdef USE_PRIVATE_BF +#define REG_JRX_TEST_CONFIG0_ADDR(inst) ((inst) + 0x00000000) +#define BF_JRX_TEST_LANE_CLEAR_ERRORS_INFO(inst) ((inst) + 0x00000000), 0x00000100 +#define BF_JRX_TEST_LANE_UPDATE_ERROR_COUNT_INFO(inst) ((inst) + 0x00000000), 0x00000101 +#define BF_JRX_TEST_PRBS_SWAP_ENDIANNESS_INFO(inst) ((inst) + 0x00000000), 0x00000103 +#define BF_JRX_TEST_SAMPLE_UPDATE_ERROR_COUNT_INFO(inst) ((inst) + 0x00000000), 0x00000104 +#define BF_JRX_TEST_SAMPLE_CLEAR_ERRORS_INFO(inst) ((inst) + 0x00000000), 0x00000105 +#define BF_JRX_TEST_SAMPLE_INVALID_DATA_FLAG_INFO(inst) ((inst) + 0x00000000), 0x00000106 +#define BF_JRX_TEST_SAMPLE_ERROR_FLAG_INFO(inst) ((inst) + 0x00000000), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_TEST_SAMPLE_ERROR_COUNT_ADDR(inst) ((inst) + 0x00000001) +#define BF_JRX_TEST_SAMPLE_ERROR_COUNT_INFO(inst) ((inst) + 0x00000001), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_TEST_CONFIG1_ADDR(inst) ((inst) + 0x00000002) +#define BF_JRX_TEST_MODE_INFO(inst) ((inst) + 0x00000002), 0x00000300 +#define BF_JRX_TEST_SOURCE_INFO(inst) ((inst) + 0x00000002), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_TEST_LANE_STATUS_ADDR(inst, n) ((inst) + 0x00000003 + 1 * (n)) +#define BF_JRX_TEST_LANE_INV_INFO(inst, n) ((inst) + 0x00000003 + 1 * (n)), 0x00000105 +#define BF_JRX_TEST_LANE_INVALID_DATA_FLAG_INFO(inst, n) ((inst) + 0x00000003 + 1 * (n)), 0x00000106 +#define BF_JRX_TEST_LANE_ERROR_FLAG_INFO(inst, n) ((inst) + 0x00000003 + 1 * (n)), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JRX_TEST_LANE_ERROR_COUNT0_ADDR(inst, n) ((inst) + 0x00000013 + 1 * (n)) +#define BF_JRX_TEST_LANE_ERROR_COUNT_INFO(inst, n) ((inst) + 0x00000013 + 1 * (n)), 0x00001800 +#endif /* USE_PRIVATE_BF */ + +#define REG_JRX_TEST_LANE_ERROR_COUNT1_ADDR(inst, n) ((inst) + 0x00000023 + 1 * (n)) + +#define REG_JRX_TEST_LANE_ERROR_COUNT2_ADDR(inst, n) ((inst) + 0x00000033 + 1 * (n)) + +#ifdef USE_PRIVATE_BF +#define REG_JRX_TEST_USER_DATA0_ADDR(inst) ((inst) + 0x00000043) +#define BF_JRX_TEST_USER_DATA_INFO(inst) ((inst) + 0x00000043), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_JRX_TEST_USER_DATA1_ADDR(inst) ((inst) + 0x00000044) + +#define REG_JRX_TEST_USER_DATA2_ADDR(inst) ((inst) + 0x00000045) + +#define REG_JRX_TEST_USER_DATA3_ADDR(inst) ((inst) + 0x00000046) + +#endif /* __ADI_APOLLO_BF_JRX_TEST_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_jrx_wrapper.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_jrx_wrapper.h new file mode 100644 index 00000000000000..341bf6d9cba45a --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_jrx_wrapper.h @@ -0,0 +1,289 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:25 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_JRX_WRAPPER_H__ +#define __ADI_APOLLO_BF_JRX_WRAPPER_H__ + +/*============= D E F I N E S ==============*/ +#define JRX_WRAPPER_JRX_TX_DIGITAL0 0x61618000 +#define JRX_WRAPPER_JRX_TX_DIGITAL1 0x61E18000 + +#define REG_GENERAL_JRX_CTRL_0_ADDR(inst) ((inst) + 0x00000000) +#define BF_LINK_EN_INFO(inst) ((inst) + 0x00000000), 0x00000200 +#define BF_LINK0_SYNCB_COMB_SEL_INFO(inst) ((inst) + 0x00000000), 0x00000204 +#define BF_LINK1_SYNCB_COMB_SEL_INFO(inst) ((inst) + 0x00000000), 0x00000206 + +#define REG_GENERAL_JRX_CTRL_1_ADDR(inst) ((inst) + 0x00000001) +#define BF_LINK_MODE_INFO(inst) ((inst) + 0x00000001), 0x00000200 +#define BF_LINK_SEPARATE_EN_INFO(inst) ((inst) + 0x00000001), 0x00000102 +#define BF_LINK0_SYNCB_COMB_EN_INFO(inst) ((inst) + 0x00000001), 0x00000103 +#define BF_LINK1_SYNCB_COMB_EN_INFO(inst) ((inst) + 0x00000001), 0x00000104 +#ifdef USE_PRIVATE_BF +#define BF_SINGLE_LINK_TM_INFO(inst) ((inst) + 0x00000001), 0x00000105 +#endif /* USE_PRIVATE_BF */ +#define BF_USE_JRXIP_SYNCB_INFO(inst) ((inst) + 0x00000001), 0x00000107 + +#ifdef USE_PRIVATE_BF +#define REG_SYNCB_GEN_0_ADDR(inst, n) ((inst) + 0x00000002 + 1 * (n)) +#define BF_EOF_MASK_INFO(inst, n) ((inst) + 0x00000002 + 1 * (n)), 0x00000100 +#define BF_EOMF_MASK_INFO(inst, n) ((inst) + 0x00000002 + 1 * (n)), 0x00000102 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_SYNCB_GEN_1_ADDR(inst, n) ((inst) + 0x00000004 + 1 * (n)) +#define BF_SYNCB_SYNCREQ_DUR_INFO(inst, n) ((inst) + 0x00000004 + 1 * (n)), 0x00000400 +#define BF_SYNCB_ERR_DUR_INFO(inst, n) ((inst) + 0x00000004 + 1 * (n)), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_SYNCB_GEN_3_ADDR(inst, n) ((inst) + 0x00000006 + 1 * (n)) +#define BF_LMFC_PERIOD_INFO(inst, n) ((inst) + 0x00000006 + 1 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JESD_DEBUG_REG_0_ADDR(inst) ((inst) + 0x00000008) +#define BF_JRX_DEBUG_BIT_INFO(inst) ((inst) + 0x00000008), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JESD_DEBUG_REG_1_ADDR(inst, n) ((inst) + 0x00000009 + 1 * (n)) +#define BF_CONV_CLK_DIV_INFO(inst, n) ((inst) + 0x00000009 + 1 * (n)), 0x00001000 +#endif /* USE_PRIVATE_BF */ + +#define REG_JESD_DEBUG_REG_2_ADDR(inst, n) ((inst) + 0x0000000B + 1 * (n)) + +#define REG_JESD_JRX_204BQBD_PA_INT_ENABLE_ADDR(inst, n) ((inst) + 0x0000000D + 1 * (n)) +#define BF_EN_204B_BD_JRX_INT_GAINOFF_INFO(inst, n) ((inst) + 0x0000000D + 1 * (n)), 0x00000100 +#define BF_EN_204B_NIT_JRX_INT_GAINOFF_INFO(inst, n) ((inst) + 0x0000000D + 1 * (n)), 0x00000101 +#define BF_EN_204B_UEK_JRX_INT_GAINOFF_INFO(inst, n) ((inst) + 0x0000000D + 1 * (n)), 0x00000102 + +#define REG_JESD_JRX_204H_PA_INT_ENABLE_ADDR(inst) ((inst) + 0x0000000E) + +#define REG_JESD_LANE_FIFO_INT_ENABLE_ADDR(inst, n) ((inst) + 0x0000000F + 1 * (n)) +#define BF_EN_JRX_LANE_FIFO_EMPTY_INT_GAINOFF_INFO(inst, n) ((inst) + 0x0000000F + 1 * (n)), 0x00000100 +#define BF_EN_JRX_LANE_FIFO_FULL_INT_GAINOFF_INFO(inst, n) ((inst) + 0x0000000F + 1 * (n)), 0x00000101 + +#define REG_FIFO_STATUS_REG_0_ADDR(inst) ((inst) + 0x00000011) +#define BF_LANE_FIFO_FULL_INFO(inst) ((inst) + 0x00000011), 0x00000C00 + +#define REG_FIFO_STATUS_REG_1_ADDR(inst) ((inst) + 0x00000020) + +#define REG_FIFO_STATUS_REG_2_ADDR(inst) ((inst) + 0x00000021) +#define BF_LANE_FIFO_EMPTY_INFO(inst) ((inst) + 0x00000021), 0x00000C00 + +#define REG_FIFO_STATUS_REG_3_ADDR(inst) ((inst) + 0x00000022) + +#ifdef USE_PRIVATE_BF +#define REG_JRX_CLK_DBUG_ADDR(inst) ((inst) + 0x00000023) +#define BF_CONV_CLK_EN_INFO(inst) ((inst) + 0x00000023), 0x00000100 +#define BF_PCLK_EN_INFO(inst) ((inst) + 0x00000023), 0x00000101 +#endif /* USE_PRIVATE_BF */ + +#define REG_TEST_MUX_0_ADDR(inst) ((inst) + 0x00000024) +#define BF_TMUX_LANE_SEL_INFO(inst) ((inst) + 0x00000024), 0x00000400 +#ifdef USE_PRIVATE_BF +#define BF_LINK_DATA_RDY_IRQ_SEL_INFO(inst) ((inst) + 0x00000024), 0x00000305 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TEST_MUX_1_ADDR(inst) ((inst) + 0x00000025) +#define BF_TMUX_SEL_A0_INFO(inst) ((inst) + 0x00000025), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TEST_MUX_2_ADDR(inst) ((inst) + 0x00000026) +#define BF_TMUX_SEL_A1_INFO(inst) ((inst) + 0x00000026), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#define REG_JRX_204C_IRQ_ADDR(inst, n) ((inst) + 0x00000027 + 1 * (n)) +#define BF_JRX_204C_SH_IRQ_INFO(inst, n) ((inst) + 0x00000027 + 1 * (n)), 0x00000100 +#define BF_JRX_204C_MB_IRQ_INFO(inst, n) ((inst) + 0x00000027 + 1 * (n)), 0x00000101 +#define BF_JRX_204C_EMB_IRQ_INFO(inst, n) ((inst) + 0x00000027 + 1 * (n)), 0x00000102 +#define BF_JRX_204C_CRC_IRQ_INFO(inst, n) ((inst) + 0x00000027 + 1 * (n)), 0x00000103 +#define BF_JRX_204C_SH_IRQ_ENABLE_INFO(inst, n) ((inst) + 0x00000027 + 1 * (n)), 0x00000104 +#define BF_JRX_204C_MB_IRQ_ENABLE_INFO(inst, n) ((inst) + 0x00000027 + 1 * (n)), 0x00000105 +#define BF_JRX_204C_EMB_IRQ_ENABLE_INFO(inst, n) ((inst) + 0x00000027 + 1 * (n)), 0x00000106 +#define BF_JRX_204C_CRC_IRQ_ENABLE_INFO(inst, n) ((inst) + 0x00000027 + 1 * (n)), 0x00000107 + +#define REG_GENERAL_JRX_CTRL_2_ADDR(inst, n) ((inst) + 0x00000029 + 1 * (n)) +#ifdef USE_PRIVATE_BF +#define BF_S_F_SEL_INFO(inst, n) ((inst) + 0x00000029 + 1 * (n)), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#ifdef USE_PRIVATE_BF +#define BF_DOWN_SCALE_OVERFLOW_INFO(inst, n) ((inst) + 0x00000029 + 1 * (n)), 0x00000101 +#endif /* USE_PRIVATE_BF */ +#define BF_JESD_MODES_NOT_IN_TABLE_INFO(inst, n) ((inst) + 0x00000029 + 1 * (n)), 0x00000102 +#ifdef USE_PRIVATE_BF +#define BF_DOWN_SCALE_RATIO_INFO(inst, n) ((inst) + 0x00000029 + 1 * (n)), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#define REG_GENERAL_JRX_CTRL_3_ADDR(inst, n) ((inst) + 0x0000002B + 1 * (n)) +#define BF_JESD_MODE_INFO(inst, n) ((inst) + 0x0000002B + 1 * (n)), 0x00000800 + +#define REG_GENERAL_JRX_CTRL_5_ADDR(inst, n) ((inst) + 0x0000002E + 1 * (n)) +#define BF_LINK_TOTAL_INTERP_INFO(inst, n) ((inst) + 0x0000002E + 1 * (n)), 0x00001000 + +#define REG_GENERAL_JRX_CTRL_6_ADDR(inst, n) ((inst) + 0x00000030 + 1 * (n)) + +#ifdef USE_PRIVATE_BF +#define REG_GENERAL_JRX_CTRL_7_ADDR(inst, n) ((inst) + 0x00000032 + 1 * (n)) +#define BF_LINK_TOTAL_INTERP_MULTI_INFO(inst, n) ((inst) + 0x00000032 + 1 * (n)), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#define REG_GENERAL_JRX_CTRL_8_ADDR(inst, n) ((inst) + 0x00000034 + 1 * (n)) +#define BF_LINK_DUC_INTERP_INFO(inst, n) ((inst) + 0x00000034 + 1 * (n)), 0x00001000 + +#define REG_GENERAL_JRX_CTRL_9_ADDR(inst, n) ((inst) + 0x00000036 + 1 * (n)) + +#define REG_GENERAL_JRX_CTRL_10_ADDR(inst, n) ((inst) + 0x00000038 + 1 * (n)) +#define BF_NUM_OF_INVALID_SAMPLE_INFO(inst, n) ((inst) + 0x00000038 + 1 * (n)), 0x00000500 +#define BF_INVALID_DATA_EN_INFO(inst, n) ((inst) + 0x00000038 + 1 * (n)), 0x00000107 + +#ifdef USE_PRIVATE_BF +#define REG_JESD_DEBUG_REG_3_ADDR(inst, n) ((inst) + 0x0000003A + 1 * (n)) +#define BF_SPI_CONFIG_EN_INFO(inst, n) ((inst) + 0x0000003A + 1 * (n)), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#define REG_RM_FIFO_IRQ_ADDR(inst, n) ((inst) + 0x0000003C + 1 * (n)) +#define BF_RM_FIFO_EMPTY_IRQ_ENABLE_INFO(inst, n) ((inst) + 0x0000003C + 1 * (n)), 0x00000100 +#define BF_RM_FIFO_FULL_IRQ_ENABLE_INFO(inst, n) ((inst) + 0x0000003C + 1 * (n)), 0x00000101 +#define BF_INVALID_SAMPLE_ERR_IRQ_INFO(inst, n) ((inst) + 0x0000003C + 1 * (n)), 0x00000102 +#define BF_RM_FIFO_EMPTY_IRQ_INFO(inst, n) ((inst) + 0x0000003C + 1 * (n)), 0x00000104 +#define BF_RM_FIFO_FULL_IRQ_INFO(inst, n) ((inst) + 0x0000003C + 1 * (n)), 0x00000105 +#define BF_INVALID_SAMPLE_ERR_IRQ_ENABLE_INFO(inst, n) ((inst) + 0x0000003C + 1 * (n)), 0x00000106 + +#define REG_LANE_FIFO_IRQ_ADDR(inst, n) ((inst) + 0x0000003E + 1 * (n)) +#define BF_JRX_LANE_FIFO_EMPTY_IRQ_ENABLE_INFO(inst, n) ((inst) + 0x0000003E + 1 * (n)), 0x00000100 +#define BF_JRX_LANE_FIFO_FULL_IRQ_ENABLE_INFO(inst, n) ((inst) + 0x0000003E + 1 * (n)), 0x00000101 +#define BF_JRX_LANE_FIFO_EMPTY_IRQ_INFO(inst, n) ((inst) + 0x0000003E + 1 * (n)), 0x00000104 +#define BF_JRX_LANE_FIFO_FULL_IRQ_INFO(inst, n) ((inst) + 0x0000003E + 1 * (n)), 0x00000105 + +#define REG_RM_FIFO_STATUS_ADDR(inst) ((inst) + 0x00000050) +#define BF_RM_FIFO_EMPTY_INFO(inst) ((inst) + 0x00000050), 0x00000200 +#define BF_RM_FIFO_FULL_INFO(inst) ((inst) + 0x00000050), 0x00000202 +#define BF_INVALID_SAMPLE_ERR_INFO(inst) ((inst) + 0x00000050), 0x00000104 + +#define REG_JRX_DATA_RDY_LOST_IRQ_ADDR(inst, n) ((inst) + 0x00000051 + 1 * (n)) +#define BF_DATA_RDY_LOST_IRQ_ENABLE_INFO(inst, n) ((inst) + 0x00000051 + 1 * (n)), 0x00000100 +#define BF_DATA_RDY_LOST_IRQ_INFO(inst, n) ((inst) + 0x00000051 + 1 * (n)), 0x00000104 + +#define REG_DEBUG_CLK_SEL_1_ADDR(inst) ((inst) + 0x00000053) +#define BF_DEBUG_CLK_OUTPUT_SEL0_INFO(inst) ((inst) + 0x00000053), 0x00000800 + +#define REG_DEBUG_CLK_SEL_0_ADDR(inst) ((inst) + 0x00000054) +#define BF_DEBUG_CLK_OUTPUT_SEL1_INFO(inst) ((inst) + 0x00000054), 0x00000800 + +#define REG_RM_FIFO_CTRL_ADDR(inst) ((inst) + 0x00000055) +#ifdef USE_PRIVATE_BF +#define BF_RM_FIFO_RESET_INFO(inst) ((inst) + 0x00000055), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_HOLD_INVALID_SAMPLE_ERR_INFO(inst) ((inst) + 0x00000055), 0x00000104 + +#define REG_RM_FIFO_INT_ENABLE_ADDR(inst, n) ((inst) + 0x00000056 + 1 * (n)) +#define BF_EN_RM_FIFO_EMPTY_INT_GAINOFF_INFO(inst, n) ((inst) + 0x00000056 + 1 * (n)), 0x00000100 +#define BF_EN_RM_FIFO_FULL_INT_GAINOFF_INFO(inst, n) ((inst) + 0x00000056 + 1 * (n)), 0x00000101 +#define BF_EN_INVALID_SAMPLE_INT_GAINOFF_INFO(inst, n) ((inst) + 0x00000056 + 1 * (n)), 0x00000104 + +#define REG_DATA_RDY_LOST_INT_ENABLE_ADDR(inst, n) ((inst) + 0x00000058 + 1 * (n)) +#define BF_EN_DATA_RDY_LOST_INT_GAINOFF_INFO(inst, n) ((inst) + 0x00000058 + 1 * (n)), 0x00000100 + +#define REG_JESD_JRX_204C_PA_INT_ENABLE_ADDR(inst, n) ((inst) + 0x0000005A + 1 * (n)) +#define BF_EN_204C_SH_ERR_JRX_INT_GAINOFF_INFO(inst, n) ((inst) + 0x0000005A + 1 * (n)), 0x00000100 +#define BF_EN_204C_MB_ERR_JRX_INT_GAINOFF_INFO(inst, n) ((inst) + 0x0000005A + 1 * (n)), 0x00000101 +#define BF_EN_204C_EMB_ERR_JRX_INT_GAINOFF_INFO(inst, n) ((inst) + 0x0000005A + 1 * (n)), 0x00000102 +#define BF_EN_204C_CRC_ERR_JRX_INT_GAINOFF_INFO(inst, n) ((inst) + 0x0000005A + 1 * (n)), 0x00000103 + +#ifdef USE_PRIVATE_BF +#define REG_GENERAL_JRX_CTRL_11_ADDR(inst) ((inst) + 0x0000005C) +#define BF_CRC_ERR_THRESHOLD_INFO(inst) ((inst) + 0x0000005C), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_GENERAL_JRX_CTRL_12_ADDR(inst) ((inst) + 0x0000005D) +#define BF_LINK0_RAMP_SEL_INFO(inst) ((inst) + 0x0000005D), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_GENERAL_JRX_CTRL_13_ADDR(inst) ((inst) + 0x0000005E) +#define BF_LINK1_RAMP_SEL_INFO(inst) ((inst) + 0x0000005E), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_GENERAL_JRX_CTRL_14_ADDR(inst) ((inst) + 0x0000005F) +#define BF_LINK_RAMP_DECODER_BYPASS_INFO(inst) ((inst) + 0x0000005F), 0x00000200 +#endif /* USE_PRIVATE_BF */ + +#define REG_GENERAL_JRX_CTRL_15_ADDR(inst, n) ((inst) + 0x00000060 + 1 * (n)) +#define BF_SAMPLE_REPEAT_EN_INFO(inst, n) ((inst) + 0x00000060 + 1 * (n)), 0x00000100 + +#define REG_GENERAL_JRX_CTRL_16_ADDR(inst, n) ((inst) + 0x00000062 + 1 * (n)) +#define BF_SYNCB_STATUS_INFO(inst, n) ((inst) + 0x00000062 + 1 * (n)), 0x00000100 + +#define REG_SERDES_RX_WR_SETUP_CTRL_ADDR(inst) ((inst) + 0x00000064) +#define BF_SERDES_RX_ANA_BRIDGE_WR_SETUP_CYCLES_INFO(inst) ((inst) + 0x00000064), 0x00000600 + +#define REG_SERDES_RX_WR_HOLD_CTRL_ADDR(inst) ((inst) + 0x00000065) +#define BF_SERDES_RX_ANA_BRIDGE_WR_HOLD_CYCLES_INFO(inst) ((inst) + 0x00000065), 0x00000600 + +#define REG_SERDES_RX_RD_CTRL_ADDR(inst) ((inst) + 0x00000066) +#define BF_SERDES_RX_ANA_BRIDGE_RD_CYCLES_INFO(inst) ((inst) + 0x00000066), 0x00000600 + +#ifdef USE_PRIVATE_BF +#define REG_SYSREF_DELAY_REG_EN_JRX_WRAPPER_ADDR(inst, n) ((inst) + 0x00000067 + 1 * (n)) +#define BF_SYSREF_PULSE_DELAY_ENABLE_JRX_WRAPPER_INFO(inst, n) ((inst) + 0x00000067 + 1 * (n)), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_SYSREF_DELAY_REG_JRX_WRAPPER_ADDR(inst, n) ((inst) + 0x00000069 + 1 * (n)) +#define BF_SYSREF_PULSE_DELAY_CYCLES_JRX_WRAPPER_INFO(inst, n) ((inst) + 0x00000069 + 1 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_ATHENA_M_ADDR(inst, n) ((inst) + 0x0000006B + 1 * (n)) +#define BF_JRX_MPARAM_RMFIFO_INFO(inst, n) ((inst) + 0x0000006B + 1 * (n)), 0x00000400 + +#define REG_ATHENA_NS_ADDR(inst, n) ((inst) + 0x0000006D + 1 * (n)) +#define BF_JRX_NS_RMFIFO_INFO(inst, n) ((inst) + 0x0000006D + 1 * (n)), 0x00000500 + +#define REG_ATHENA_CTRL_ADDR(inst) ((inst) + 0x00000070) +#define BF_ATHENA_ENABLE_INFO(inst) ((inst) + 0x00000070), 0x00000100 + +#define REG_RB_M_PARAM_ADDR(inst, n) ((inst) + 0x00000071 + 1 * (n)) +#define BF_READBACK_JRX_M_PARAM_INFO(inst, n) ((inst) + 0x00000071 + 1 * (n)), 0x00000400 + +#define REG_RB_L_PARAM_ADDR(inst, n) ((inst) + 0x00000073 + 1 * (n)) +#define BF_READBACK_JRX_L_PARAM_INFO(inst, n) ((inst) + 0x00000073 + 1 * (n)), 0x00000500 + +#define REG_RB_E_PARAM_ADDR(inst, n) ((inst) + 0x00000075 + 1 * (n)) +#define BF_READBACK_JRX_E_PARAM_INFO(inst, n) ((inst) + 0x00000075 + 1 * (n)), 0x00000500 + +#define REG_RB_S_PARAM_ADDR(inst, n) ((inst) + 0x00000077 + 1 * (n)) +#define BF_READBACK_JRX_S_PARAM_INFO(inst, n) ((inst) + 0x00000077 + 1 * (n)), 0x00000400 + +#define REG_RB_F_PARAM_ADDR(inst, n) ((inst) + 0x00000079 + 1 * (n)) +#define BF_READBACK_JRX_F_PARAM_INFO(inst, n) ((inst) + 0x00000079 + 1 * (n)), 0x00000500 + +#define REG_RB_K_PARAM_ADDR(inst, n) ((inst) + 0x0000007B + 1 * (n)) +#define BF_READBACK_JRX_K_PARAM_INFO(inst, n) ((inst) + 0x0000007B + 1 * (n)), 0x00000800 + +#define REG_RB_N_PARAM_ADDR(inst, n) ((inst) + 0x0000007D + 1 * (n)) +#define BF_READBACK_JRX_N_PARAM_INFO(inst, n) ((inst) + 0x0000007D + 1 * (n)), 0x00000400 + +#define REG_RB_NP_PARAM_ADDR(inst, n) ((inst) + 0x0000007F + 1 * (n)) +#define BF_READBACK_JRX_NP_PARAM_INFO(inst, n) ((inst) + 0x0000007F + 1 * (n)), 0x00000400 + +#define REG_RB_NS_PARAM_ADDR(inst, n) ((inst) + 0x00000081 + 1 * (n)) +#define BF_READBACK_JRX_NS_PARAM_INFO(inst, n) ((inst) + 0x00000081 + 1 * (n)), 0x00000500 + +#endif /* __ADI_APOLLO_BF_JRX_WRAPPER_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_jtx_dformat.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_jtx_dformat.h new file mode 100644 index 00000000000000..b03f0abd02cf4f --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_jtx_dformat.h @@ -0,0 +1,222 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:23 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_JTX_DFORMAT_H__ +#define __ADI_APOLLO_BF_JTX_DFORMAT_H__ + +/*============= D E F I N E S ==============*/ +#define JTX_DFORMAT_JTX_TOP_RX_DIGITAL0 0x60600000 +#define JTX_DFORMAT_JTX_TOP_RX_DIGITAL1 0x60E00000 + +#define REG_DFORMAT_OUT_FORMAT_SEL0_ADDR(inst) ((inst) + 0x00000000) +#define BF_DFORMAT_SEL_0_INFO(inst) ((inst) + 0x00000000), 0x00000200 +#define BF_DFORMAT_INV_0_INFO(inst) ((inst) + 0x00000000), 0x00000102 + +#define REG_DFORMAT_OUT_FORMAT_SEL1_ADDR(inst) ((inst) + 0x00000001) +#define BF_DFORMAT_SEL_1_INFO(inst) ((inst) + 0x00000001), 0x00000200 +#define BF_DFORMAT_INV_1_INFO(inst) ((inst) + 0x00000001), 0x00000102 + +#define REG_DFORMAT_OUT_RES0_ADDR(inst) ((inst) + 0x00000002) +#define BF_DFORMAT_RES_0_INFO(inst) ((inst) + 0x00000002), 0x00000400 +#define BF_DFORMAT_DDC_DITHER_EN_0_INFO(inst) ((inst) + 0x00000002), 0x00000104 + +#define REG_DFORMAT_OUT_RES1_ADDR(inst) ((inst) + 0x00000003) +#define BF_DFORMAT_RES_1_INFO(inst) ((inst) + 0x00000003), 0x00000400 +#define BF_DFORMAT_DDC_DITHER_EN_1_INFO(inst) ((inst) + 0x00000003), 0x00000104 + +#define REG_LINK_EN_ADDR(inst) ((inst) + 0x00000004) +#define BF_LINK_EN_0_INFO(inst) ((inst) + 0x00000004), 0x00000100 +#define BF_LINK_EN_1_INFO(inst) ((inst) + 0x00000004), 0x00000101 + +#define REG_DFORMAT_TMODE_SEL0_ADDR(inst) ((inst) + 0x00000005) +#define BF_DFORMAT_TMODE_SEL_0_INFO(inst) ((inst) + 0x00000005), 0x00000800 + +#define REG_DFORMAT_TMODE_SEL1_ADDR(inst) ((inst) + 0x00000006) +#define BF_DFORMAT_TMODE_SEL_1_INFO(inst) ((inst) + 0x00000006), 0x00000800 + +#define REG_DFORMAT_OVR_CLR0_ADDR(inst) ((inst) + 0x00000007) +#define BF_DFORMAT_OVR_CLR_0_INFO(inst) ((inst) + 0x00000007), 0x00000800 + +#define REG_DFORMAT_OVR_CLR1_ADDR(inst) ((inst) + 0x00000008) +#define BF_DFORMAT_OVR_CLR_1_INFO(inst) ((inst) + 0x00000008), 0x00000800 + +#define REG_DFORMAT_OVR_STATUS0_ADDR(inst) ((inst) + 0x00000009) +#define BF_DFORMAT_OVR_STATUS_0_INFO(inst) ((inst) + 0x00000009), 0x00000800 + +#define REG_DFORMAT_OVR_STATUS1_ADDR(inst) ((inst) + 0x0000000A) +#define BF_DFORMAT_OVR_STATUS_1_INFO(inst) ((inst) + 0x0000000A), 0x00000800 + +#define REG_LINK0_DDC_DEC0_ADDR(inst) ((inst) + 0x0000000B) +#define BF_LINK_DDC_DEC_0_INFO(inst) ((inst) + 0x0000000B), 0x00000A00 + +#define REG_LINK0_DDC_DEC1_ADDR(inst) ((inst) + 0x0000000C) + +#define REG_LINK1_DDC_DEC0_ADDR(inst) ((inst) + 0x0000000D) +#define BF_LINK_DDC_DEC_1_INFO(inst) ((inst) + 0x0000000D), 0x00000A00 + +#define REG_LINK1_DDC_DEC1_ADDR(inst) ((inst) + 0x0000000E) + +#define REG_CTRL_BIT_0_SEL0_ADDR(inst) ((inst) + 0x0000000F) +#define BF_DFORMAT_CTRL_BIT_0_SEL_0_INFO(inst) ((inst) + 0x0000000F), 0x00000400 + +#define REG_CTRL_BIT_0_SEL1_ADDR(inst) ((inst) + 0x00000010) +#define BF_DFORMAT_CTRL_BIT_0_SEL_1_INFO(inst) ((inst) + 0x00000010), 0x00000400 + +#define REG_CTRL_BIT_1_SEL0_ADDR(inst) ((inst) + 0x00000011) +#define BF_DFORMAT_CTRL_BIT_1_SEL_0_INFO(inst) ((inst) + 0x00000011), 0x00000400 + +#define REG_CTRL_BIT_1_SEL1_ADDR(inst) ((inst) + 0x00000012) +#define BF_DFORMAT_CTRL_BIT_1_SEL_1_INFO(inst) ((inst) + 0x00000012), 0x00000400 + +#define REG_CTRL_BIT_2_SEL0_ADDR(inst) ((inst) + 0x00000013) +#define BF_DFORMAT_CTRL_BIT_2_SEL_0_INFO(inst) ((inst) + 0x00000013), 0x00000400 + +#define REG_CTRL_BIT_2_SEL1_ADDR(inst) ((inst) + 0x00000014) +#define BF_DFORMAT_CTRL_BIT_2_SEL_1_INFO(inst) ((inst) + 0x00000014), 0x00000400 + +#define REG_TMODE_USR_LSB_P0_JTX_DFORMAT_ADDR(inst, n) ((inst) + 0x0000001D + 1 * (n)) +#define BF_TMODE_USR_PAT0_JTX_DFORMAT_INFO(inst, n) ((inst) + 0x0000001D + 1 * (n)), 0x00001000 + +#define REG_TMODE_USR_MSB_P0_JTX_DFORMAT_ADDR(inst, n) ((inst) + 0x0000001F + 1 * (n)) + +#define REG_TMODE_USR_LSB_P1_JTX_DFORMAT_ADDR(inst, n) ((inst) + 0x00000021 + 1 * (n)) +#define BF_TMODE_USR_PAT1_JTX_DFORMAT_INFO(inst, n) ((inst) + 0x00000021 + 1 * (n)), 0x00001000 + +#define REG_TMODE_USR_MSB_P1_JTX_DFORMAT_ADDR(inst, n) ((inst) + 0x00000023 + 1 * (n)) + +#define REG_TMODE_USR_LSB_P2_JTX_DFORMAT_ADDR(inst, n) ((inst) + 0x00000025 + 1 * (n)) +#define BF_TMODE_USR_PAT2_JTX_DFORMAT_INFO(inst, n) ((inst) + 0x00000025 + 1 * (n)), 0x00001000 + +#define REG_TMODE_USR_MSB_P2_JTX_DFORMAT_ADDR(inst, n) ((inst) + 0x00000027 + 1 * (n)) + +#define REG_TMODE_USR_LSB_P3_JTX_DFORMAT_ADDR(inst, n) ((inst) + 0x00000029 + 1 * (n)) +#define BF_TMODE_USR_PAT3_JTX_DFORMAT_INFO(inst, n) ((inst) + 0x00000029 + 1 * (n)), 0x00001000 + +#define REG_TMODE_USR_MSB_P3_JTX_DFORMAT_ADDR(inst, n) ((inst) + 0x0000002B + 1 * (n)) + +#define REG_TMODE_USR_LSB_P4_JTX_DFORMAT_ADDR(inst, n) ((inst) + 0x0000002D + 1 * (n)) +#define BF_TMODE_USR_PAT4_JTX_DFORMAT_INFO(inst, n) ((inst) + 0x0000002D + 1 * (n)), 0x00001000 + +#define REG_TMODE_USR_MSB_P4_JTX_DFORMAT_ADDR(inst, n) ((inst) + 0x0000002F + 1 * (n)) + +#define REG_TMODE_USR_LSB_P5_JTX_DFORMAT_ADDR(inst, n) ((inst) + 0x00000031 + 1 * (n)) +#define BF_TMODE_USR_PAT5_JTX_DFORMAT_INFO(inst, n) ((inst) + 0x00000031 + 1 * (n)), 0x00001000 + +#define REG_TMODE_USR_MSB_P5_JTX_DFORMAT_ADDR(inst, n) ((inst) + 0x00000033 + 1 * (n)) + +#define REG_TMODE_USR_LSB_P6_JTX_DFORMAT_ADDR(inst, n) ((inst) + 0x00000035 + 1 * (n)) +#define BF_TMODE_USR_PAT6_JTX_DFORMAT_INFO(inst, n) ((inst) + 0x00000035 + 1 * (n)), 0x00001000 + +#define REG_TMODE_USR_MSB_P6_JTX_DFORMAT_ADDR(inst, n) ((inst) + 0x00000037 + 1 * (n)) + +#define REG_TMODE_USR_LSB_P7_JTX_DFORMAT_ADDR(inst, n) ((inst) + 0x00000039 + 1 * (n)) +#define BF_TMODE_USR_PAT7_JTX_DFORMAT_INFO(inst, n) ((inst) + 0x00000039 + 1 * (n)), 0x00001000 + +#define REG_TMODE_USR_MSB_P7_JTX_DFORMAT_ADDR(inst, n) ((inst) + 0x0000004B + 1 * (n)) + +#define REG_LINK_TOTAL_DEC0_LSB_ADDR(inst) ((inst) + 0x0000006D) +#define BF_LINK_TOTAL_DEC_0_INFO(inst) ((inst) + 0x0000006D), 0x00000B00 + +#define REG_LINK_TOTAL_DEC0_MSB_ADDR(inst) ((inst) + 0x0000006E) + +#define REG_LINK_TOTAL_DEC1_LSB_ADDR(inst) ((inst) + 0x0000006F) +#define BF_LINK_TOTAL_DEC_1_INFO(inst) ((inst) + 0x0000006F), 0x00000B00 + +#define REG_LINK_TOTAL_DEC1_MSB_ADDR(inst) ((inst) + 0x00000070) + +#define REG_INVALID_EN_ADDR(inst) ((inst) + 0x00000071) +#define BF_INVALID_EN_INFO(inst) ((inst) + 0x00000071), 0x00000200 + +#define REG_FINE_I_SEL_ADDR(inst) ((inst) + 0x00000072) +#define BF_FINE0_ADC_I_SEL_INFO(inst) ((inst) + 0x00000072), 0x00000200 +#define BF_FINE1_ADC_I_SEL_INFO(inst) ((inst) + 0x00000072), 0x00000202 +#define BF_FINE2_ADC_I_SEL_INFO(inst) ((inst) + 0x00000072), 0x00000204 +#define BF_FINE3_ADC_I_SEL_INFO(inst) ((inst) + 0x00000072), 0x00000206 + +#define REG_FINE_I_SEL_8T8R_ADDR(inst) ((inst) + 0x00000073) +#define BF_FINE4_ADC_I_SEL_INFO(inst) ((inst) + 0x00000073), 0x00000200 +#define BF_FINE5_ADC_I_SEL_INFO(inst) ((inst) + 0x00000073), 0x00000202 +#define BF_FINE6_ADC_I_SEL_INFO(inst) ((inst) + 0x00000073), 0x00000204 +#define BF_FINE7_ADC_I_SEL_INFO(inst) ((inst) + 0x00000073), 0x00000206 + +#define REG_FINE_Q_SEL_ADDR(inst) ((inst) + 0x00000074) +#define BF_FINE0_ADC_Q_SEL_INFO(inst) ((inst) + 0x00000074), 0x00000200 +#define BF_FINE1_ADC_Q_SEL_INFO(inst) ((inst) + 0x00000074), 0x00000202 +#define BF_FINE2_ADC_Q_SEL_INFO(inst) ((inst) + 0x00000074), 0x00000204 +#define BF_FINE3_ADC_Q_SEL_INFO(inst) ((inst) + 0x00000074), 0x00000206 + +#define REG_FINE_Q_SEL_8T8R_ADDR(inst) ((inst) + 0x00000075) +#define BF_FINE4_ADC_Q_SEL_INFO(inst) ((inst) + 0x00000075), 0x00000200 +#define BF_FINE5_ADC_Q_SEL_INFO(inst) ((inst) + 0x00000075), 0x00000202 +#define BF_FINE6_ADC_Q_SEL_INFO(inst) ((inst) + 0x00000075), 0x00000204 +#define BF_FINE7_ADC_Q_SEL_INFO(inst) ((inst) + 0x00000075), 0x00000206 + +#define REG_TMODE_CTRL0_LINK0_ADDR(inst) ((inst) + 0x00000076) +#define BF_TMODE_TYPE_SEL_INFO(inst) ((inst) + 0x00000076), 0x00000400 + +#define REG_TMODE_CTRL1_LINK0_ADDR(inst) ((inst) + 0x00000078) +#define BF_TMODE_USR_PAT_SEL_INFO(inst) ((inst) + 0x00000078), 0x00000100 +#define BF_TMODE_FLUSH_INFO(inst) ((inst) + 0x00000078), 0x00000101 +#define BF_TMODE_PN_FORCE_RST_INFO(inst) ((inst) + 0x00000078), 0x00000102 + +#define REG_TMODE_CTRL2_LINK0_ADDR(inst) ((inst) + 0x0000007A) +#define BF_TMODE_RES_INFO(inst) ((inst) + 0x0000007A), 0x00000400 + +#define REG_TMODE_CTRL0_LINK1_ADDR(inst) ((inst) + 0x0000007B) +#define BF_TMODE_TYPE_SEL_LINK1_INFO(inst) ((inst) + 0x0000007B), 0x00000400 + +#define REG_TMODE_CTRL1_LINK1_ADDR(inst) ((inst) + 0x0000007C) +#define BF_TMODE_USR_PAT_SEL_LINK1_INFO(inst) ((inst) + 0x0000007C), 0x00000100 +#define BF_TMODE_FLUSH_LINK1_INFO(inst) ((inst) + 0x0000007C), 0x00000101 +#define BF_TMODE_PN_FORCE_RST_LINK1_INFO(inst) ((inst) + 0x0000007C), 0x00000102 + +#define REG_TMODE_CTRL2_LINK1_ADDR(inst) ((inst) + 0x0000007D) +#define BF_TMODE_RES_LINK1_INFO(inst) ((inst) + 0x0000007D), 0x00000400 + +#define REG_DFORMAT_NEG_FULL_SCALE_CLR0_ADDR(inst) ((inst) + 0x0000007E) +#define BF_DFORMAT_NEG_FULL_SCALE_CLR_0_INFO(inst) ((inst) + 0x0000007E), 0x00000800 + +#define REG_DFORMAT_NEG_FULL_SCALE_CLR1_ADDR(inst) ((inst) + 0x0000007F) +#define BF_DFORMAT_NEG_FULL_SCALE_CLR_1_INFO(inst) ((inst) + 0x0000007F), 0x00000800 + +#define REG_DFORMAT_NEG_FULL_SCALE_STATUS0_ADDR(inst) ((inst) + 0x00000080) +#define BF_DFORMAT_NEG_FULL_SCALE_STATUS_0_INFO(inst) ((inst) + 0x00000080), 0x00000800 + +#define REG_DFORMAT_NEG_FULL_SCALE_STATUS1_ADDR(inst) ((inst) + 0x00000081) +#define BF_DFORMAT_NEG_FULL_SCALE_STATUS_1_INFO(inst) ((inst) + 0x00000081), 0x00000800 + +#define REG_SAMPLE_REPEAT_EN_ADDR(inst) ((inst) + 0x00000082) +#define BF_SAMPLE_REPEAT_EN_0_INFO(inst) ((inst) + 0x00000082), 0x00000100 +#define BF_SAMPLE_REPEAT_EN_1_INFO(inst) ((inst) + 0x00000082), 0x00000101 + +#define REG_STARTUP_FORCE_INVALID_EN_ADDR(inst, n) ((inst) + 0x00000083 + 1 * (n)) +#define BF_STARTUP_FRCE_INVALID_EN_INFO(inst, n) ((inst) + 0x00000083 + 1 * (n)), 0x00000100 + +#define REG_FORCE_INVALID_EN_ADDR(inst, n) ((inst) + 0x00000085 + 1 * (n)) +#define BF_FORCE_INVALID_EN_INFO(inst, n) ((inst) + 0x00000085 + 1 * (n)), 0x00000100 + +#define REG_DFORMAT_OVR_CLR_8T8R_0_ADDR(inst) ((inst) + 0x00000087) +#define BF_DFORMAT_OVR_CLR_8T8R_0_INFO(inst) ((inst) + 0x00000087), 0x00000800 + +#define REG_DFORMAT_OVR_CLR_8T8R_1_ADDR(inst) ((inst) + 0x00000088) +#define BF_DFORMAT_OVR_CLR_8T8R_1_INFO(inst) ((inst) + 0x00000088), 0x00000800 + +#define REG_DFORMAT_OVR_STATUS_8T8R_0_ADDR(inst) ((inst) + 0x00000089) +#define BF_DFORMAT_OVR_STATUS_8T8R_0_INFO(inst) ((inst) + 0x00000089), 0x00000800 + +#define REG_DFORMAT_OVR_STATUS_8T8R_1_ADDR(inst) ((inst) + 0x0000008A) +#define BF_DFORMAT_OVR_STATUS_8T8R_1_INFO(inst) ((inst) + 0x0000008A), 0x00000800 + +#endif /* __ADI_APOLLO_BF_JTX_DFORMAT_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_jtx_dual_link.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_jtx_dual_link.h new file mode 100644 index 00000000000000..fd2b7501286abd --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_jtx_dual_link.h @@ -0,0 +1,279 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:23 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_JTX_DUAL_LINK_H__ +#define __ADI_APOLLO_BF_JTX_DUAL_LINK_H__ + +/*============= D E F I N E S ==============*/ +#define JTX_DUAL_LINK_0_JTX_TOP_RX_DIGITAL0 0x60610000 +#define JTX_DUAL_LINK_1_JTX_TOP_RX_DIGITAL0 0x60614000 +#define JTX_DUAL_LINK_0_JTX_TOP_RX_DIGITAL1 0x60E10000 +#define JTX_DUAL_LINK_1_JTX_TOP_RX_DIGITAL1 0x60E14000 + +#define REG_JTX_CORE_1_ADDR(inst) ((inst) + 0x00000011) +#define BF_JTX_CHKSUM_LSB_ALG_INFO(inst) ((inst) + 0x00000011), 0x00000100 +#define BF_JTX_CHKSUM_DISABLE_INFO(inst) ((inst) + 0x00000011), 0x00000101 +#define BF_JTX_LINK_204C_SEL_INFO(inst) ((inst) + 0x00000011), 0x00000204 +#define BF_JTX_SYSREF_FOR_STARTUP_INFO(inst) ((inst) + 0x00000011), 0x00000106 +#ifdef USE_PRIVATE_BF +#define BF_JTX_SYSREF_FOR_RELINK_INFO(inst) ((inst) + 0x00000011), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#define REG_JTX_CORE_2_LANE_ADDR(inst, n) ((inst) + 0x00000020 + 1 * (n)) +#define BF_JTX_LANE_ASSIGN_INFO(inst, n) ((inst) + 0x00000020 + 1 * (n)), 0x00000500 +#define BF_JTX_LANE_INV_INFO(inst, n) ((inst) + 0x00000020 + 1 * (n)), 0x00000105 +#define BF_JTX_FORCE_LANE_PD_INFO(inst, n) ((inst) + 0x00000020 + 1 * (n)), 0x00000106 +#define BF_JTX_LANE_PD_STATUS_INFO(inst, n) ((inst) + 0x00000020 + 1 * (n)), 0x00000107 + +#define REG_JTX_CORE_3_ADDR(inst) ((inst) + 0x00000030) +#define BF_JTX_TEST_GEN_MODE_INFO(inst) ((inst) + 0x00000030), 0x00000400 +#define BF_JTX_TEST_GEN_SEL_INFO(inst) ((inst) + 0x00000030), 0x00000204 +#define BF_JTX_TEST_MIRROR_INFO(inst) ((inst) + 0x00000030), 0x00000106 +#define BF_JTX_TEST_USER_GO_INFO(inst) ((inst) + 0x00000030), 0x00000107 + +#define REG_JTX_CORE_4_ADDR(inst) ((inst) + 0x00000031) + +#define REG_JTX_CORE_5_ADDR(inst) ((inst) + 0x00000032) + +#define REG_JTX_CORE_6_ADDR(inst) ((inst) + 0x00000033) + +#define REG_JTX_CORE_7_ADDR(inst) ((inst) + 0x00000034) + +#define REG_JTX_CORE_8_ADDR(inst) ((inst) + 0x00000035) + +#define REG_JTX_CORE_9_ADDR(inst) ((inst) + 0x00000036) + +#define REG_JTX_CORE_10_ADDR(inst) ((inst) + 0x00000037) + +#define REG_JTX_CORE_11_ADDR(inst) ((inst) + 0x00000038) + +#define REG_JTX_CORE_12_ADDR(inst) ((inst) + 0x00000039) +#define BF_JTX_SYNC_N_SEL_INFO(inst) ((inst) + 0x00000039), 0x00000305 + +#define REG_JTX_CORE_13_ADDR(inst) ((inst) + 0x0000003A) +#define BF_JTX_LINK_EN_INFO(inst) ((inst) + 0x0000003A), 0x00000100 + +#define REG_JTX_CORE_0_CONV_ADDR(inst, n) ((inst) + 0x00000040 + 1 * (n)) +#define BF_JTX_CONV_SEL_INFO(inst, n) ((inst) + 0x00000040 + 1 * (n)), 0x00000600 +#ifdef USE_PRIVATE_BF +#define BF_JTX_CONV_MASK_INFO(inst, n) ((inst) + 0x00000040 + 1 * (n)), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#define REG_JTX_TPL_0_ADDR(inst) ((inst) + 0x00000080) +#ifdef USE_PRIVATE_BF +#define BF_JTX_TPL_ADAPTIVE_LATENCY_INFO(inst) ((inst) + 0x00000080), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_JTX_TPL_TEST_ENABLE_INFO(inst) ((inst) + 0x00000080), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_JTX_CONV_ASYNCHRONOUS_INFO(inst) ((inst) + 0x00000080), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_JTX_NS_CFG_INFO(inst) ((inst) + 0x00000080), 0x00000503 + +#ifdef USE_PRIVATE_BF +#define REG_JTX_TPL_1_ADDR(inst) ((inst) + 0x00000081) +#define BF_JTX_TPL_LATENCY_ADJUST_INFO(inst) ((inst) + 0x00000081), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_JTX_TPL_2_ADDR(inst) ((inst) + 0x00000082) +#define BF_JTX_TPL_PHASE_ADJUST_INFO(inst) ((inst) + 0x00000082), 0x00001000 + +#define REG_JTX_TPL_3_ADDR(inst) ((inst) + 0x00000083) + +#define REG_JTX_TPL_4_ADDR(inst) ((inst) + 0x00000084) +#define BF_JTX_TPL_TEST_NUM_FRAMES_M1_INFO(inst) ((inst) + 0x00000084), 0x00001000 + +#define REG_JTX_TPL_5_ADDR(inst) ((inst) + 0x00000085) + +#define REG_JTX_TPL_6_ADDR(inst) ((inst) + 0x00000086) +#define BF_JTX_TPL_INVALID_CFG_INFO(inst) ((inst) + 0x00000086), 0x00000100 +#define BF_JTX_TPL_SYSREF_RCVD_INFO(inst) ((inst) + 0x00000086), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_JTX_TPL_SYSREF_PHASE_ERR_INFO(inst) ((inst) + 0x00000086), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#ifdef USE_PRIVATE_BF +#define BF_JTX_TPL_SYSREF_MASK_INFO(inst) ((inst) + 0x00000086), 0x00000105 +#endif /* USE_PRIVATE_BF */ +#ifdef USE_PRIVATE_BF +#define BF_JTX_TPL_SYSREF_CLR_PHASE_ERR_INFO(inst) ((inst) + 0x00000086), 0x00000106 +#endif /* USE_PRIVATE_BF */ +#ifdef USE_PRIVATE_BF +#define BF_JTX_TPL_SYSREF_IGNORE_WHEN_LINKED_INFO(inst) ((inst) + 0x00000086), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JTX_TPL_7_ADDR(inst) ((inst) + 0x00000087) +#define BF_JTX_TPL_SYSREF_N_SHOT_COUNT_INFO(inst) ((inst) + 0x00000087), 0x00000400 +#define BF_JTX_TPL_SYSREF_N_SHOT_ENABLE_INFO(inst) ((inst) + 0x00000087), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JTX_TPL_8_ADDR(inst) ((inst) + 0x00000088) +#define BF_JTX_TPL_LATENCY_ADDED_INFO(inst) ((inst) + 0x00000088), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JTX_TPL_9_ADDR(inst) ((inst) + 0x00000089) +#define BF_JTX_TPL_BUF_FRAMES_INFO(inst) ((inst) + 0x00000089), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_JTX_L0_0_ADDR(inst) ((inst) + 0x00000090) +#define BF_JTX_DID_CFG_INFO(inst) ((inst) + 0x00000090), 0x00000800 + +#define REG_JTX_L0_1_ADDR(inst) ((inst) + 0x00000091) +#define BF_JTX_BID_CFG_INFO(inst) ((inst) + 0x00000091), 0x00000400 +#define BF_JTX_ADJCNT_CFG_INFO(inst) ((inst) + 0x00000091), 0x00000404 + +#define REG_JTX_L0_2_ADDR(inst) ((inst) + 0x00000092) +#define BF_JTX_PHADJ_CFG_INFO(inst) ((inst) + 0x00000092), 0x00000105 +#define BF_JTX_ADJDIR_CFG_INFO(inst) ((inst) + 0x00000092), 0x00000106 + +#define REG_JTX_L0_3_ADDR(inst) ((inst) + 0x00000093) +#define BF_JTX_L_CFG_INFO(inst) ((inst) + 0x00000093), 0x00000500 +#define BF_JTX_SCR_CFG_INFO(inst) ((inst) + 0x00000093), 0x00000107 + +#define REG_JTX_L0_4_ADDR(inst) ((inst) + 0x00000094) +#define BF_JTX_F_CFG_INFO(inst) ((inst) + 0x00000094), 0x00000800 + +#define REG_JTX_L0_5_ADDR(inst) ((inst) + 0x00000095) +#define BF_JTX_K_CFG_INFO(inst) ((inst) + 0x00000095), 0x00000800 + +#define REG_JTX_L0_6_ADDR(inst) ((inst) + 0x00000096) +#define BF_JTX_M_CFG_INFO(inst) ((inst) + 0x00000096), 0x00000800 + +#define REG_JTX_L0_7_ADDR(inst) ((inst) + 0x00000097) +#define BF_JTX_N_CFG_INFO(inst) ((inst) + 0x00000097), 0x00000500 +#define BF_JTX_CS_CFG_INFO(inst) ((inst) + 0x00000097), 0x00000206 + +#define REG_JTX_L0_8_ADDR(inst) ((inst) + 0x00000098) +#define BF_JTX_NP_CFG_INFO(inst) ((inst) + 0x00000098), 0x00000500 +#define BF_JTX_SUBCLASSV_CFG_INFO(inst) ((inst) + 0x00000098), 0x00000305 + +#define REG_JTX_L0_9_ADDR(inst) ((inst) + 0x00000099) +#define BF_JTX_S_CFG_INFO(inst) ((inst) + 0x00000099), 0x00000500 +#define BF_JTX_JESDV_CFG_INFO(inst) ((inst) + 0x00000099), 0x00000305 + +#define REG_JTX_L0_10_ADDR(inst) ((inst) + 0x0000009A) +#define BF_JTX_HD_CFG_INFO(inst) ((inst) + 0x0000009A), 0x00000107 + +#define REG_JTX_L0_13_LANE_ADDR(inst, n) ((inst) + 0x000000A0 + 1 * (n)) +#define BF_JTX_CHKSUM_CFG_INFO(inst, n) ((inst) + 0x000000A0 + 1 * (n)), 0x00000800 + +#define REG_JTX_L0_14_LANE_ADDR(inst, n) ((inst) + 0x000000B0 + 1 * (n)) +#define BF_JTX_LID_CFG_INFO(inst, n) ((inst) + 0x000000B0 + 1 * (n)), 0x00000500 + +#define REG_JTX_DL_204B_0_ADDR(inst) ((inst) + 0x000000C0) +#define BF_JTX_DL_204B_BYP_ACG_CFG_INFO(inst) ((inst) + 0x000000C0), 0x00000100 +#define BF_JTX_DL_204B_BYP_8B10B_CFG_INFO(inst) ((inst) + 0x000000C0), 0x00000101 +#define BF_JTX_DL_204B_ILAS_TEST_EN_CFG_INFO(inst) ((inst) + 0x000000C0), 0x00000102 +#define BF_JTX_DL_204B_BYP_ILAS_CFG_INFO(inst) ((inst) + 0x000000C0), 0x00000103 +#define BF_JTX_DL_204B_ILAS_DELAY_CFG_INFO(inst) ((inst) + 0x000000C0), 0x00000404 + +#define REG_JTX_DL_204B_1_ADDR(inst) ((inst) + 0x000000C1) +#define BF_JTX_DL_204B_10B_MIRROR_INFO(inst) ((inst) + 0x000000C1), 0x00000100 +#define BF_JTX_DL_204B_DEL_SCR_CFG_INFO(inst) ((inst) + 0x000000C1), 0x00000101 +#define BF_JTX_DL_204B_LSYNC_EN_CFG_INFO(inst) ((inst) + 0x000000C1), 0x00000102 + +#define REG_JTX_DL_204B_2_ADDR(inst) ((inst) + 0x000000C2) +#define BF_JTX_DL_204B_KF_ILAS_CFG_INFO(inst) ((inst) + 0x000000C2), 0x00000800 + +#define REG_JTX_DL_204B_3_ADDR(inst) ((inst) + 0x000000C3) +#define BF_JTX_DL_204B_RJSPAT_EN_CFG_INFO(inst) ((inst) + 0x000000C3), 0x00000100 +#define BF_JTX_DL_204B_RJSPAT_SEL_CFG_INFO(inst) ((inst) + 0x000000C3), 0x00000201 +#ifdef USE_PRIVATE_BF +#define BF_JTX_DL_204B_TPL_TEST_EN_CFG_INFO(inst) ((inst) + 0x000000C3), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_JTX_DL_204B_SYNC_N_INFO(inst) ((inst) + 0x000000C3), 0x00000105 +#define BF_JTX_DL_204B_TESTMODE_IGNORE_SYNCN_CFG_INFO(inst) ((inst) + 0x000000C3), 0x00000106 +#define BF_JTX_DL_204B_CLEAR_SYNC_NE_COUNT_INFO(inst) ((inst) + 0x000000C3), 0x00000107 + +#define REG_JTX_DL_204B_4_ADDR(inst) ((inst) + 0x000000C4) +#define BF_JTX_DL_204B_STATE_INFO(inst) ((inst) + 0x000000C4), 0x00000400 +#define BF_JTX_DL_204B_SYNC_N_FORCE_VAL_INFO(inst) ((inst) + 0x000000C4), 0x00000106 +#define BF_JTX_DL_204B_SYNC_N_FORCE_EN_INFO(inst) ((inst) + 0x000000C4), 0x00000107 + +#define REG_JTX_DL_204B_5_ADDR(inst) ((inst) + 0x000000C5) +#define BF_JTX_DL_204B_SYNC_NE_COUNT_INFO(inst) ((inst) + 0x000000C5), 0x00000800 + +#define REG_JTX_DL_204B_6_LANE_ADDR(inst, n) ((inst) + 0x000000C6 + 1 * (n)) +#ifdef USE_PRIVATE_BF +#define BF_JTX_DL_204B_L_EN_CFG_INFO(inst, n) ((inst) + 0x000000C6 + 1 * (n)), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_JTX_DL_204B_PHY_DATA_SEL_CFG_INFO(inst, n) ((inst) + 0x000000C6 + 1 * (n)), 0x00000102 +#define BF_JTX_DL_204B_SCR_DATA_SEL_CFG_INFO(inst, n) ((inst) + 0x000000C6 + 1 * (n)), 0x00000103 +#define BF_JTX_DL_204B_SCR_IN_CTRL_CFG_INFO(inst, n) ((inst) + 0x000000C6 + 1 * (n)), 0x00000104 + +#define REG_JTX_DL_204C_0_ADDR(inst) ((inst) + 0x000000F0) +#define BF_JTX_CRC_FEC_REVERSE_CFG_INFO(inst) ((inst) + 0x000000F0), 0x00000100 +#define BF_JTX_LINK_FEC_ENABLE_INFO(inst) ((inst) + 0x000000F0), 0x00000101 +#define BF_JTX_FORCE_METABITS_INFO(inst) ((inst) + 0x000000F0), 0x00000102 +#define BF_JTX_DL_204C_SYSREF_RCVD_INFO(inst) ((inst) + 0x000000F0), 0x00000103 + +#define REG_JTX_DL_204C_1_ADDR(inst) ((inst) + 0x000000F1) +#define BF_JTX_E_CFG_INFO(inst) ((inst) + 0x000000F1), 0x00000500 + +#ifdef USE_PRIVATE_BF +#define REG_JTX_DL_204C_2_ADDR(inst) ((inst) + 0x000000F2) +#define BF_JTX_BURST_ERROR_INJECT_INFO(inst) ((inst) + 0x000000F2), 0x00000100 +#define BF_JTX_BURST_ERROR_LENGTH_INFO(inst) ((inst) + 0x000000F2), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JTX_DL_204C_3_ADDR(inst) ((inst) + 0x000000F3) +#define BF_JTX_BURST_ERROR_LOCATION_INFO(inst) ((inst) + 0x000000F3), 0x00000B00 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JTX_DL_204H_0_ADDR(inst) ((inst) + 0x00000100) +#define BF_JTX_DL_204H_ACG_BYP_INFO(inst) ((inst) + 0x00000100), 0x00000100 +#define BF_JTX_DL_204H_BYP_ILAS_CFG_INFO(inst) ((inst) + 0x00000100), 0x00000101 +#define BF_JTX_DL_204H_CLEAR_SYNC_NE_COUNT_INFO(inst) ((inst) + 0x00000100), 0x00000102 +#define BF_JTX_DL_204H_LANE_SYNC_2SIDES_INFO(inst) ((inst) + 0x00000100), 0x00000103 +#define BF_JTX_DL_204H_ILAS_DELAY_CFG_INFO(inst) ((inst) + 0x00000100), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JTX_DL_204H_1_ADDR(inst) ((inst) + 0x00000101) +#define BF_JTX_DL_204H_INTERLEAVE_MODE_INFO(inst) ((inst) + 0x00000101), 0x00000200 +#define BF_JTX_DL_204H_PARITY_BYPASS_INFO(inst) ((inst) + 0x00000101), 0x00000102 +#define BF_JTX_DL_204H_PARITY_MODE_INFO(inst) ((inst) + 0x00000101), 0x00000103 +#define BF_JTX_DL_204H_STATE_INFO(inst) ((inst) + 0x00000101), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JTX_DL_204H_2_ADDR(inst) ((inst) + 0x00000102) +#define BF_JTX_DL_204H_KF_ILAS_CFG_INFO(inst) ((inst) + 0x00000102), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JTX_DL_204H_3_ADDR(inst) ((inst) + 0x00000103) +#define BF_JTX_DL_204H_PARITY_ODD_ENABLE_INFO(inst) ((inst) + 0x00000103), 0x00000100 +#define BF_JTX_DL_204H_SCR_CFG_INFO(inst) ((inst) + 0x00000103), 0x00000101 +#define BF_JTX_DL_204H_SYNC_N_FORCE_EN_INFO(inst) ((inst) + 0x00000103), 0x00000102 +#define BF_JTX_DL_204H_SYNC_N_FORCE_VAL_INFO(inst) ((inst) + 0x00000103), 0x00000103 +#define BF_JTX_DL_204H_TEST_MODE_INFO(inst) ((inst) + 0x00000103), 0x00000204 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JTX_DL_204H_4_ADDR(inst) ((inst) + 0x00000104) +#define BF_JTX_DL_204H_SYNC_NE_COUNT_INFO(inst) ((inst) + 0x00000104), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_JTX_PHY_IFX_0_LANE_ADDR(inst, n) ((inst) + 0x00000110 + 1 * (n)) +#define BF_JTX_BR_LOG2_RATIO_INFO(inst, n) ((inst) + 0x00000110 + 1 * (n)), 0x00000400 +#ifdef USE_PRIVATE_BF +#define BF_JTX_LANE_FIFO_WR_ENTRIES_INFO(inst, n) ((inst) + 0x00000110 + 1 * (n)), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#endif /* __ADI_APOLLO_BF_JTX_DUAL_LINK_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_jtx_qbf_txfe.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_jtx_qbf_txfe.h new file mode 100644 index 00000000000000..c52e06f7ce20b3 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_jtx_qbf_txfe.h @@ -0,0 +1,263 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:23 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_JTX_QBF_TXFE_H__ +#define __ADI_APOLLO_BF_JTX_QBF_TXFE_H__ + +/*============= D E F I N E S ==============*/ +#define JTX_QBF_TXFE_0_JTX_TOP_RX_DIGITAL0 0x60618000 +#define JTX_QBF_TXFE_1_JTX_TOP_RX_DIGITAL0 0x6061C000 +#define JTX_QBF_TXFE_0_JTX_TOP_RX_DIGITAL1 0x60E18000 +#define JTX_QBF_TXFE_1_JTX_TOP_RX_DIGITAL1 0x60E1C000 + +#define REG_PLL_STATUS_ADDR(inst) ((inst) + 0x00000001) +#define BF_JTX_PLL_LOCKED_INFO(inst) ((inst) + 0x00000001), 0x00000107 + +#define REG_JTX_QUICK_CFG_ADDR(inst) ((inst) + 0x00000002) +#define BF_JTX_MODE_INFO(inst) ((inst) + 0x00000002), 0x00000700 + +#define REG_JTX_QUICK_CFG_EN_ADDR(inst) ((inst) + 0x00000003) +#define BF_JTX_QUICK_CONFIG_EN_INFO(inst) ((inst) + 0x00000003), 0x00000100 + +#define REG_JTX_LINK_CTRL1_ADDR(inst) ((inst) + 0x00000004) + +#define REG_JTX_SER_CLK_INVERT_ADDR(inst) ((inst) + 0x00000006) +#define BF_JTX_SER_CLK_INVERT_INFO(inst) ((inst) + 0x00000006), 0x00000100 + +#define REG_JTX_PDWN_CTRL_ADDR(inst) ((inst) + 0x00000008) + +#ifdef USE_PRIVATE_BF +#define REG_SYSREF_DELAY_REG_JTX_QBF_TXFE_ADDR(inst) ((inst) + 0x00000009) +#define BF_SYSREF_PULSE_DELAY_CYCLES_JTX_QBF_TXFE_INFO(inst) ((inst) + 0x00000009), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_RESET_CTRL_REG_ADDR(inst) ((inst) + 0x0000000A) +#define BF_FORCE_JTX_DIGITAL_RESET_ON_RSTEN_FORCE_EN_INFO(inst) ((inst) + 0x0000000A), 0x00000100 +#define BF_PD_SERDES_INFO(inst) ((inst) + 0x0000000A), 0x00000101 +#define BF_FORCE_JTX_DIGITAL_RESET_ON_SYSREF_INFO(inst) ((inst) + 0x0000000A), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#define REG_SER_PARITY_RESET_EN1_ADDR(inst) ((inst) + 0x0000000B) +#define BF_SER_PARITY_RESET_EN_INFO(inst) ((inst) + 0x0000000B), 0x00000C00 + +#define REG_SER_PARITY_RESET_EN2_ADDR(inst) ((inst) + 0x0000000C) + +#ifdef USE_PRIVATE_BF +#define REG_LCM_DIV_FORCE_EN_ADDR(inst) ((inst) + 0x0000000D) +#define BF_LCM_DIV_FORCE_EN_INFO(inst) ((inst) + 0x0000000D), 0x00000100 +#define BF_LCM_OVERRIDE_INFO(inst) ((inst) + 0x0000000D), 0x00000101 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_LCM_DIV1_ADDR(inst) ((inst) + 0x0000000E) +#define BF_LCM_DIV_INFO(inst) ((inst) + 0x0000000E), 0x00000E00 +#endif /* USE_PRIVATE_BF */ + +#define REG_LCM_DIV2_ADDR(inst) ((inst) + 0x0000000F) + +#ifdef USE_PRIVATE_BF +#define REG_FORCE_LINK_RESET_REG_ADDR(inst) ((inst) + 0x00000010) +#define BF_FORCE_LINK_RESET_INFO(inst) ((inst) + 0x00000010), 0x00000100 +#define BF_FORCE_LINK_DIGITAL_RESET_INFO(inst) ((inst) + 0x00000010), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#define REG_QC_MODE_STATUS_ADDR(inst) ((inst) + 0x00000011) +#define BF_JTX_INVALID_MODE_INFO(inst) ((inst) + 0x00000011), 0x00000100 + +#define REG_K_EMB_QC_OVERRIDE_ADDR(inst) ((inst) + 0x00000012) +#define BF_JTX_K_EMB_QC_OVERRIDE_INFO(inst) ((inst) + 0x00000012), 0x00000100 + +#define REG_PHASE_ESTABLISH_STATUS_ADDR(inst) ((inst) + 0x00000013) +#define BF_JTX_PHASE_ESTABLISHED_INFO(inst) ((inst) + 0x00000013), 0x00000100 + +#ifdef USE_PRIVATE_BF +#define REG_PHASE_ESTABLISH_GPIO_ADDR(inst) ((inst) + 0x00000014) +#define BF_JTX_PHASE_ESTABLISHED_GPIO_OUT_INFO(inst) ((inst) + 0x00000014), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CLKGEN_ALIGN_FALL_RST_DEASSERT_ADDR(inst) ((inst) + 0x00000015) +#define BF_CLKGEN_ALIGN_FALL_FOR_RST_DEASSERT_INFO(inst) ((inst) + 0x00000015), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#define REG_PHASE_ESTABLISH_DATA_GATING_ADDR(inst) ((inst) + 0x00000016) +#define BF_JTX_PHASE_ESTABLISHED_DATA_GATING_EN_INFO(inst) ((inst) + 0x00000016), 0x00000100 + +#define REG_PLL_REF_CLK_DIV1_REG_ADDR(inst) ((inst) + 0x00000017) +#define BF_DIVM_LCPLL_RC_RX_INFO(inst) ((inst) + 0x00000017), 0x00000200 + +#ifdef USE_PRIVATE_BF +#define REG_LMFC_CTL_ADDR(inst) ((inst) + 0x00000018) +#define BF_LMFC_OUT_DIV_INFO(inst) ((inst) + 0x00000018), 0x00000300 +#define BF_LMFC_DIV_EDGE_INFO(inst) ((inst) + 0x00000018), 0x00000104 +#define BF_LMFC_OUT_SEL_INFO(inst) ((inst) + 0x00000018), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#define REG_DIV_CLK_GEN_ASYNC_MODE_ADDR(inst) ((inst) + 0x00000019) + +#ifdef USE_PRIVATE_BF +#define REG_SYNC_DELAY_REG_ADDR(inst) ((inst) + 0x0000001B) +#define BF_SYNC_DELAY_COUNT_INFO(inst) ((inst) + 0x0000001B), 0x00000400 +#define BF_SYNC_DELAY_LINK_PCLK_CYCLES_ENABLE_INFO(inst) ((inst) + 0x0000001B), 0x00000106 +#define BF_SYNC_DELAY_ENABLE_INFO(inst) ((inst) + 0x0000001B), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_EXTEND_SYNC_FORCE_REG_ADDR(inst) ((inst) + 0x0000001C) +#define BF_EXTEND_SYNC_FORCE_DURING_RESYNC_INFO(inst) ((inst) + 0x0000001C), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#define REG_NS_OVERRIDE_ADDR(inst) ((inst) + 0x0000002D) +#define BF_JTX_NS_OVERRIDE_INFO(inst) ((inst) + 0x0000002D), 0x00000100 +#ifdef USE_PRIVATE_BF +#define BF_DDC_NS_OVERRIDE_INFO(inst) ((inst) + 0x0000002D), 0x00000101 +#endif /* USE_PRIVATE_BF */ +#ifdef USE_PRIVATE_BF +#define BF_NS_CONV_NS_OVERRIDE_INFO(inst) ((inst) + 0x0000002D), 0x00000102 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_NS_CONV_NS_ADDR(inst) ((inst) + 0x0000002E) +#define BF_NS_CONV_NS_REGMAP_INFO(inst) ((inst) + 0x0000002E), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_DDC_NS_ADDR(inst) ((inst) + 0x0000002F) +#define BF_DDC_NS_REGMAP_INFO(inst) ((inst) + 0x0000002F), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JTX_FORCE_SYNC_DELAY_EN_ADDR(inst) ((inst) + 0x00000030) +#define BF_JTX_FORCE_SYNC_DELAY_EN_INFO(inst) ((inst) + 0x00000030), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JTX_FORCE_SYNC_DELAY_COUNT_ADDR(inst) ((inst) + 0x00000031) +#define BF_JTX_FORCE_SYNC_DELAY_COUNT_INFO(inst) ((inst) + 0x00000031), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_RESET_FIRST_CLK_AFTER_RESET_ADDR(inst) ((inst) + 0x00000032) + +#define REG_SERDES_TX_WR_SETUP_CTRL_ADDR(inst) ((inst) + 0x00000033) +#define BF_SERDES_TX_ANA_BRIDGE_WR_SETUP_CYCLES_INFO(inst) ((inst) + 0x00000033), 0x00000600 + +#define REG_SERDES_TX_WR_HOLD_CTRL_ADDR(inst) ((inst) + 0x00000034) +#define BF_SERDES_TX_ANA_BRIDGE_WR_HOLD_CYCLES_INFO(inst) ((inst) + 0x00000034), 0x00000600 + +#define REG_SERDES_TX_RD_CTRL_ADDR(inst) ((inst) + 0x00000035) +#define BF_SERDES_TX_ANA_BRIDGE_RD_CYCLES_INFO(inst) ((inst) + 0x00000035), 0x00000600 + +#ifdef USE_PRIVATE_BF +#define REG_JTX_NS_READBACK_ADDR(inst) ((inst) + 0x00000036) +#define BF_JTX_NS_READBACK_INFO(inst) ((inst) + 0x00000036), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JTX_M_READBACK_ADDR(inst) ((inst) + 0x00000037) +#define BF_JTX_M_READBACK_INFO(inst) ((inst) + 0x00000037), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JTX_L_READBACK_ADDR(inst) ((inst) + 0x00000038) +#define BF_JTX_L_READBACK_INFO(inst) ((inst) + 0x00000038), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JTX_S_READBACK_ADDR(inst) ((inst) + 0x00000039) +#define BF_JTX_S_READBACK_INFO(inst) ((inst) + 0x00000039), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JTX_F_READBACK_ADDR(inst) ((inst) + 0x0000003A) +#define BF_JTX_F_READBACK_INFO(inst) ((inst) + 0x0000003A), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JTX_NP_READBACK_ADDR(inst) ((inst) + 0x0000003B) +#define BF_JTX_NP_READBACK_INFO(inst) ((inst) + 0x0000003B), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JTX_SPECIAL_CASE_ADDR(inst) ((inst) + 0x0000003C) +#define BF_JTX_SAMPLE_CROSSBAR_EN_INFO(inst) ((inst) + 0x0000003C), 0x00000100 +#define BF_USE_NS_LINK_TOTAL_DEC_INFO(inst) ((inst) + 0x0000003C), 0x00000101 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JTX_K_S_BY_NS_READBACK_ADDR(inst) ((inst) + 0x0000003D) +#define BF_JTX_K_S_BY_NS_READBACK_INFO(inst) ((inst) + 0x0000003D), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JTX_ASYNC_READBACK_ADDR(inst) ((inst) + 0x0000003E) +#define BF_JTX_ASYNC_READBACK_INFO(inst) ((inst) + 0x0000003E), 0x00000100 +#define BF_CLK_ASYNC_READBACK_INFO(inst) ((inst) + 0x0000003E), 0x00000101 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_NS_CONV_NS_READBACK_ADDR(inst) ((inst) + 0x0000003F) +#define BF_NS_CONV_NS_READBACK_INFO(inst) ((inst) + 0x0000003F), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_SYSREF_DELAY_REG_EN_JTX_QBF_TXFE_ADDR(inst) ((inst) + 0x00000040) +#define BF_SYSREF_PULSE_DELAY_ENABLE_JTX_QBF_TXFE_INFO(inst) ((inst) + 0x00000040), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JTX_C2R_EN_ADDR(inst) ((inst) + 0x00000041) +#define BF_JTX_MODE_C2R_EN_INFO(inst) ((inst) + 0x00000041), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JTX_CLK_DLY_START_ADDR(inst) ((inst) + 0x00000042) +#define BF_NEWCLK_DLY_JTX_QBF_TXFE_INFO(inst) ((inst) + 0x00000042), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JTX_CLK_RESTART_CTRL_ADDR(inst) ((inst) + 0x00000043) +#define BF_FORCE_SYNC_INFO(inst) ((inst) + 0x00000043), 0x00000100 +#define BF_FORCE_NEWCLK_JTX_QBF_TXFE_INFO(inst) ((inst) + 0x00000043), 0x00000101 +#define BF_REGMAP_RESYNC_EN_INFO(inst) ((inst) + 0x00000043), 0x00000102 +#define BF_ALLOW_IFX_CLK_RESTART_INFO(inst) ((inst) + 0x00000043), 0x00000103 +#define BF_ALLOW_PCLK_RESTART_INFO(inst) ((inst) + 0x00000043), 0x00000104 +#define BF_ALLOW_CONV_CLK_RESTART_INFO(inst) ((inst) + 0x00000043), 0x00000105 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JTX_CLK_CTL_FSM_STATE_ADDR(inst) ((inst) + 0x00000044) +#define BF_CTRL_FSM_STATE_INFO(inst) ((inst) + 0x00000044), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#define REG_ASYNC_CTRL_ADDR(inst) ((inst) + 0x00000046) +#ifdef USE_PRIVATE_BF +#define BF_ASYNC_MODE_OVERRIDE_INFO(inst) ((inst) + 0x00000046), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_JTX_LINK_204C_CLK_GATE_DIS_INFO(inst) ((inst) + 0x00000046), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_CLK_ASYNC_INFO(inst) ((inst) + 0x00000046), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#ifdef USE_PRIVATE_BF +#define BF_CLK_ASYNC_OVERRIDE_INFO(inst) ((inst) + 0x00000046), 0x00000103 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_DDC_TYPE_ADDR(inst) ((inst) + 0x00000049) +#define BF_DDC_TYPE_INFO(inst) ((inst) + 0x00000049), 0x00000200 +#define BF_DDC_TYPE_OVERRIDE_INFO(inst) ((inst) + 0x00000049), 0x00000102 +#endif /* USE_PRIVATE_BF */ + +#endif /* __ADI_APOLLO_BF_JTX_QBF_TXFE_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_linearx_bmem.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_linearx_bmem.h new file mode 100644 index 00000000000000..d19642fc111291 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_linearx_bmem.h @@ -0,0 +1,180 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:19 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_LINEARX_BMEM_H__ +#define __ADI_APOLLO_BF_LINEARX_BMEM_H__ + +/*============= D E F I N E S ==============*/ +#define LINEARX_BMEM_REGMAP_RX_LINEARX_REG8_0_RX_SLICE_0_RX_DIGITAL0 0x60210000 +#define LINEARX_BMEM_REGMAP_RX_LINEARX_REG8_1_RX_SLICE_0_RX_DIGITAL0 0x60218000 +#define LINEARX_BMEM_REGMAP_RX_LINEARX_REG8_0_RX_SLICE_1_RX_DIGITAL0 0x60410000 +#define LINEARX_BMEM_REGMAP_RX_LINEARX_REG8_1_RX_SLICE_1_RX_DIGITAL0 0x60418000 +#define LINEARX_BMEM_REGMAP_RX_LINEARX_REG8_0_RX_SLICE_0_RX_DIGITAL1 0x60A10000 +#define LINEARX_BMEM_REGMAP_RX_LINEARX_REG8_1_RX_SLICE_0_RX_DIGITAL1 0x60A18000 +#define LINEARX_BMEM_REGMAP_RX_LINEARX_REG8_0_RX_SLICE_1_RX_DIGITAL1 0x60C10000 +#define LINEARX_BMEM_REGMAP_RX_LINEARX_REG8_1_RX_SLICE_1_RX_DIGITAL1 0x60C18000 +#define LINEARX_BMEM_REGMAP_TX_LINEARX_REG8_0_TX_SLICE_0_TX_DIGITAL0 0x61210000 +#define LINEARX_BMEM_REGMAP_TX_LINEARX_REG8_1_TX_SLICE_0_TX_DIGITAL0 0x61218000 +#define LINEARX_BMEM_REGMAP_TX_LINEARX_REG8_0_TX_SLICE_1_TX_DIGITAL0 0x61410000 +#define LINEARX_BMEM_REGMAP_TX_LINEARX_REG8_1_TX_SLICE_1_TX_DIGITAL0 0x61418000 +#define LINEARX_BMEM_REGMAP_TX_LINEARX_REG8_0_TX_SLICE_0_TX_DIGITAL1 0x61A10000 +#define LINEARX_BMEM_REGMAP_TX_LINEARX_REG8_1_TX_SLICE_0_TX_DIGITAL1 0x61A18000 +#define LINEARX_BMEM_REGMAP_TX_LINEARX_REG8_0_TX_SLICE_1_TX_DIGITAL1 0x61C10000 +#define LINEARX_BMEM_REGMAP_TX_LINEARX_REG8_1_TX_SLICE_1_TX_DIGITAL1 0x61C18000 + +#define REG_BMEM_CONTROL_1_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000000) +#define BF_BMEM_EN_LINEARX_BMEM_INFO(inst) ((inst) + 0x00000000), 0x00000100 +#define BF_BMEM_START_LINEARX_BMEM_INFO(inst) ((inst) + 0x00000000), 0x00000101 +#define BF_BMEM_MODE_LINEARX_BMEM_INFO(inst) ((inst) + 0x00000000), 0x00000202 +#define BF_BMEM_RESET_LINEARX_BMEM_INFO(inst) ((inst) + 0x00000000), 0x00000104 +#define BF_BMEM_SLEEP_LINEARX_BMEM_INFO(inst) ((inst) + 0x00000000), 0x00000105 +#define BF_BMEM_SHUT_DOWN_LINEARX_BMEM_INFO(inst) ((inst) + 0x00000000), 0x00000106 +#define BF_FAST_NSLOW_MODE_LINEARX_BMEM_INFO(inst) ((inst) + 0x00000000), 0x00000107 + +#define REG_BMEM_CONTROL_2_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000001) +#define BF_TRIG_MODE_LINEARX_BMEM_INFO(inst) ((inst) + 0x00000001), 0x00000100 +#define BF_TRIG_MODE_SCLR_EN_LINEARX_BMEM_INFO(inst) ((inst) + 0x00000001), 0x00000101 +#define BF_PARITY_CHECK_EN_LINEARX_BMEM_INFO(inst) ((inst) + 0x00000001), 0x00000102 +#define BF_SAMPLE_SIZE_LINEARX_BMEM_INFO(inst) ((inst) + 0x00000001), 0x00000103 +#define BF_RAMCLK_PH_DIS_LINEARX_BMEM_INFO(inst) ((inst) + 0x00000001), 0x00000104 +#define BF_BMEM_8T8R_CAP_MASK_LINEARX_BMEM_INFO(inst) ((inst) + 0x00000001), 0x00000205 +#define BF_HOP_DLY_SEL_MODE_LINEARX_BMEM_INFO(inst) ((inst) + 0x00000001), 0x00000107 + +#define REG_SAMPLE_DELAY_0_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000002) +#define BF_SAMPLE_DLY_LINEARX_BMEM_INFO(inst) ((inst) + 0x00000002), 0x00001000 + +#define REG_SAMPLE_DELAY_1_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000003) + +#define REG_HOP_DELAY0_0_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000004) +#define BF_HOP_DELAY0_LINEARX_BMEM_INFO(inst) ((inst) + 0x00000004), 0x00001000 + +#define REG_HOP_DELAY0_1_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000005) + +#define REG_HOP_DELAY1_0_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000006) +#define BF_HOP_DELAY1_LINEARX_BMEM_INFO(inst) ((inst) + 0x00000006), 0x00001000 + +#define REG_HOP_DELAY1_1_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000007) + +#define REG_HOP_DELAY2_0_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000008) +#define BF_HOP_DELAY2_LINEARX_BMEM_INFO(inst) ((inst) + 0x00000008), 0x00001000 + +#define REG_HOP_DELAY2_1_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000009) + +#define REG_HOP_DELAY3_0_LINEARX_BMEM_ADDR(inst) ((inst) + 0x0000000A) +#define BF_HOP_DELAY3_LINEARX_BMEM_INFO(inst) ((inst) + 0x0000000A), 0x00001000 + +#define REG_HOP_DELAY3_1_LINEARX_BMEM_ADDR(inst) ((inst) + 0x0000000B) + +#define REG_ST_ADDR_CPT_0_LINEARX_BMEM_ADDR(inst) ((inst) + 0x0000000C) +#define BF_ST_ADDR_CPT_LINEARX_BMEM_INFO(inst) ((inst) + 0x0000000C), 0x00000F00 + +#define REG_ST_ADDR_CPT_1_LINEARX_BMEM_ADDR(inst) ((inst) + 0x0000000D) + +#define REG_END_ADDR_CPT_0_LINEARX_BMEM_ADDR(inst) ((inst) + 0x0000000E) +#define BF_END_ADDR_CPT_LINEARX_BMEM_INFO(inst) ((inst) + 0x0000000E), 0x00000F00 + +#define REG_END_ADDR_CPT_1_LINEARX_BMEM_ADDR(inst) ((inst) + 0x0000000F) + +#define REG_ST_ADDR_AWG_0_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000010) +#define BF_ST_ADDR_AWG_LINEARX_BMEM_INFO(inst) ((inst) + 0x00000010), 0x00000F00 + +#define REG_ST_ADDR_AWG_1_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000011) + +#define REG_END_ADDR_AWG_0_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000012) +#define BF_END_ADDR_AWG_LINEARX_BMEM_INFO(inst) ((inst) + 0x00000012), 0x00000F00 + +#define REG_END_ADDR_AWG_1_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000013) + +#define REG_ST_CPTR_ON_SMPL_VAL_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000014) +#define BF_ST_CPTR_ON_SMPL_VAL_LINEARX_BMEM_INFO(inst) ((inst) + 0x00000014), 0x00000800 + +#define REG_SMPL_VAL_FOR_CPTR0_0_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000015) +#define BF_SMPL_VAL_FOR_CPTR0_LINEARX_BMEM_INFO(inst) ((inst) + 0x00000015), 0x00002000 + +#define REG_SMPL_VAL_FOR_CPTR0_1_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000016) + +#define REG_SMPL_VAL_FOR_CPTR0_2_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000017) + +#define REG_SMPL_VAL_FOR_CPTR0_3_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000018) + +#define REG_SMPL_VAL_FOR_CPTR1_0_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000019) +#define BF_SMPL_VAL_FOR_CPTR1_LINEARX_BMEM_INFO(inst) ((inst) + 0x00000019), 0x00002000 + +#define REG_SMPL_VAL_FOR_CPTR1_1_LINEARX_BMEM_ADDR(inst) ((inst) + 0x0000001A) + +#define REG_SMPL_VAL_FOR_CPTR1_2_LINEARX_BMEM_ADDR(inst) ((inst) + 0x0000001B) + +#define REG_SMPL_VAL_FOR_CPTR1_3_LINEARX_BMEM_ADDR(inst) ((inst) + 0x0000001C) + +#define REG_SMPL_VAL_FOR_CPTR2_0_LINEARX_BMEM_ADDR(inst) ((inst) + 0x0000001D) +#define BF_SMPL_VAL_FOR_CPTR2_LINEARX_BMEM_INFO(inst) ((inst) + 0x0000001D), 0x00002000 + +#define REG_SMPL_VAL_FOR_CPTR2_1_LINEARX_BMEM_ADDR(inst) ((inst) + 0x0000001E) + +#define REG_SMPL_VAL_FOR_CPTR2_2_LINEARX_BMEM_ADDR(inst) ((inst) + 0x0000001F) + +#define REG_SMPL_VAL_FOR_CPTR2_3_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000020) + +#define REG_SMPL_VAL_FOR_CPTR3_0_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000021) +#define BF_SMPL_VAL_FOR_CPTR3_LINEARX_BMEM_INFO(inst) ((inst) + 0x00000021), 0x00002000 + +#define REG_SMPL_VAL_FOR_CPTR3_1_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000022) + +#define REG_SMPL_VAL_FOR_CPTR3_2_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000023) + +#define REG_SMPL_VAL_FOR_CPTR3_3_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000024) + +#define REG_SMPL_VAL_FOR_CPTR4_0_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000025) +#define BF_SMPL_VAL_FOR_CPTR4_LINEARX_BMEM_INFO(inst) ((inst) + 0x00000025), 0x00002000 + +#define REG_SMPL_VAL_FOR_CPTR4_1_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000026) + +#define REG_SMPL_VAL_FOR_CPTR4_2_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000027) + +#define REG_SMPL_VAL_FOR_CPTR4_3_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000028) + +#define REG_SMPL_VAL_FOR_CPTR5_0_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000029) +#define BF_SMPL_VAL_FOR_CPTR5_LINEARX_BMEM_INFO(inst) ((inst) + 0x00000029), 0x00002000 + +#define REG_SMPL_VAL_FOR_CPTR5_1_LINEARX_BMEM_ADDR(inst) ((inst) + 0x0000002A) + +#define REG_SMPL_VAL_FOR_CPTR5_2_LINEARX_BMEM_ADDR(inst) ((inst) + 0x0000002B) + +#define REG_SMPL_VAL_FOR_CPTR5_3_LINEARX_BMEM_ADDR(inst) ((inst) + 0x0000002C) + +#define REG_SMPL_VAL_FOR_CPTR6_0_LINEARX_BMEM_ADDR(inst) ((inst) + 0x0000002D) +#define BF_SMPL_VAL_FOR_CPTR6_LINEARX_BMEM_INFO(inst) ((inst) + 0x0000002D), 0x00002000 + +#define REG_SMPL_VAL_FOR_CPTR6_1_LINEARX_BMEM_ADDR(inst) ((inst) + 0x0000002E) + +#define REG_SMPL_VAL_FOR_CPTR6_2_LINEARX_BMEM_ADDR(inst) ((inst) + 0x0000002F) + +#define REG_SMPL_VAL_FOR_CPTR6_3_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000030) + +#define REG_SMPL_VAL_FOR_CPTR7_0_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000031) +#define BF_SMPL_VAL_FOR_CPTR7_LINEARX_BMEM_INFO(inst) ((inst) + 0x00000031), 0x00002000 + +#define REG_SMPL_VAL_FOR_CPTR7_1_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000032) + +#define REG_SMPL_VAL_FOR_CPTR7_2_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000033) + +#define REG_SMPL_VAL_FOR_CPTR7_3_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000034) + +#define REG_BMEM_STATUS_LINEARX_BMEM_ADDR(inst) ((inst) + 0x00000035) +#define BF_CAPTURE_TRIG_PHASE_LINEARX_BMEM_INFO(inst) ((inst) + 0x00000035), 0x00000600 +#define BF_FULL_IRQ_LINEARX_BMEM_INFO(inst) ((inst) + 0x00000035), 0x00000106 +#define BF_PARITY_ERR_LINEARX_BMEM_INFO(inst) ((inst) + 0x00000035), 0x00000107 + +#endif /* __ADI_APOLLO_BF_LINEARX_BMEM_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_linearx_corr.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_linearx_corr.h new file mode 100644 index 00000000000000..fcfe02c7ee8d18 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_linearx_corr.h @@ -0,0 +1,110 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:19 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_LINEARX_CORR_H__ +#define __ADI_APOLLO_BF_LINEARX_CORR_H__ + +/*============= D E F I N E S ==============*/ +#define LINEARX_CORR_RX_LINEARX_REG32_0_RX_SLICE_0_RX_DIGITAL0 0x60220100 +#define LINEARX_CORR_RX_LINEARX_REG32_1_RX_SLICE_0_RX_DIGITAL0 0x60228100 +#define LINEARX_CORR_RX_LINEARX_REG32_0_RX_SLICE_1_RX_DIGITAL0 0x60420100 +#define LINEARX_CORR_RX_LINEARX_REG32_1_RX_SLICE_1_RX_DIGITAL0 0x60428100 +#define LINEARX_CORR_RX_LINEARX_REG32_0_RX_SLICE_0_RX_DIGITAL1 0x60A20100 +#define LINEARX_CORR_RX_LINEARX_REG32_1_RX_SLICE_0_RX_DIGITAL1 0x60A28100 +#define LINEARX_CORR_RX_LINEARX_REG32_0_RX_SLICE_1_RX_DIGITAL1 0x60C20100 +#define LINEARX_CORR_RX_LINEARX_REG32_1_RX_SLICE_1_RX_DIGITAL1 0x60C28100 +#define LINEARX_CORR_TX_LINEARX_REG32_0_TX_SLICE_0_TX_DIGITAL0 0x61220100 +#define LINEARX_CORR_TX_LINEARX_REG32_1_TX_SLICE_0_TX_DIGITAL0 0x61228100 +#define LINEARX_CORR_TX_LINEARX_REG32_0_TX_SLICE_1_TX_DIGITAL0 0x61420100 +#define LINEARX_CORR_TX_LINEARX_REG32_1_TX_SLICE_1_TX_DIGITAL0 0x61428100 +#define LINEARX_CORR_TX_LINEARX_REG32_0_TX_SLICE_0_TX_DIGITAL1 0x61A20100 +#define LINEARX_CORR_TX_LINEARX_REG32_1_TX_SLICE_0_TX_DIGITAL1 0x61A28100 +#define LINEARX_CORR_TX_LINEARX_REG32_0_TX_SLICE_1_TX_DIGITAL1 0x61C20100 +#define LINEARX_CORR_TX_LINEARX_REG32_1_TX_SLICE_1_TX_DIGITAL1 0x61C28100 + +#define REG_LINEARX_CORR_CONTROL_ADDR(inst) ((inst) + 0x00000000) +#define BF_NO_INTERP_CORRECTION_INFO(inst) ((inst) + 0x00000000), 0x00000100 +#define BF_INTERP_TYPE_EN_INFO(inst) ((inst) + 0x00000000), 0x00000101 +#define BF_HAMMERSTEIN_EN_INFO(inst) ((inst) + 0x00000000), 0x00000102 +#define BF_INTERP_NOM_6B_OUT_LP_INFO(inst) ((inst) + 0x00000000), 0x00000103 +#define BF_INTERP_NOM_6B_OUT_BP_INFO(inst) ((inst) + 0x00000000), 0x00000104 +#define BF_CROSSTERM_EN_INFO(inst) ((inst) + 0x00000000), 0x0000010D +#define BF_CROSSTERM_DELAY_INFO(inst) ((inst) + 0x00000000), 0x00000C10 +#define BF_LINEARX_OVR_OPTION_INFO(inst) ((inst) + 0x00000000), 0x0000021C +#define BF_TAP_ADJUST_INFO(inst) ((inst) + 0x00000000), 0x0000021E + +#define REG_LINEARX_ACAUSAL_TAPS_ADDR(inst) ((inst) + 0x00000004) +#define BF_ACAUSAL_TAPS_INFO(inst) ((inst) + 0x00000004), 0x00000400 +#define BF_DISABLE_ACAUSAL_TAPS_CSRAM_INFO(inst) ((inst) + 0x00000004), 0x00000204 + +#define REG_LINEARX_AMP_THRESH_ADDR(inst) ((inst) + 0x00000008) +#define BF_LINEARX_AMP_THRESH_EN_INFO(inst) ((inst) + 0x00000008), 0x00000100 +#define BF_LINEARX_AMP_THRESH_DITHER_EN_INFO(inst) ((inst) + 0x00000008), 0x00000101 +#define BF_LINEARX_AMP_THRESH_CLK_GATING_EN_INFO(inst) ((inst) + 0x00000008), 0x00000102 +#define BF_LINEARX_AMP_THRESH_FLUSH_PIPELINE_EN_INFO(inst) ((inst) + 0x00000008), 0x00000103 +#define BF_LINEARX_AMP_THRESH_DITHER_SHIFT_INFO(inst) ((inst) + 0x00000008), 0x00000204 + +#define REG_LINEARX_AMP_THRESH2_ADDR(inst) ((inst) + 0x0000000C) +#define BF_CAL_DWELL_TIME_INFO(inst) ((inst) + 0x0000000C), 0x00001000 +#define BF_LINEARX_AMP_THRESH_INFO(inst) ((inst) + 0x0000000C), 0x00000B10 + +#define REG_LINEARX_OFFSET_OVR_ADDR(inst) ((inst) + 0x00000010) +#define BF_LINEARX_OFFSET_OVR_CNT_INFO(inst) ((inst) + 0x00000010), 0x00001000 + +#define REG_LINEARX_OFFSET_MEASUREMENT_ADDR(inst) ((inst) + 0x00000014) +#define BF_LINEARX_OFFSET_MEASUREMENT_INFO(inst) ((inst) + 0x00000014), 0x00000B00 +#define BF_LINEARX_OFFSET_STATUS_IRQ_INFO(inst) ((inst) + 0x00000014), 0x0000010B + +#define REG_LINEARX_OFFSET_START_ADDR(inst) ((inst) + 0x00000018) +#define BF_LINEARX_OFFSET_CAL_START_INFO(inst) ((inst) + 0x00000018), 0x00000100 + +#define REG_LINEARX_OFFSET_CLR_ADDR(inst) ((inst) + 0x0000001C) +#define BF_LINEARX_OFFSET_IRQ_CLEAR_INFO(inst) ((inst) + 0x0000001C), 0x00000100 + +#define REG_LINEARX_OFFSET_CAL_ADDR(inst) ((inst) + 0x00000020) +#define BF_LINEARX_OFFSET_CAL_DEC_RATE_INFO(inst) ((inst) + 0x00000020), 0x00000D00 +#define BF_LINEARX_OFFSET_CAL_SHIFT_EXP_INFO(inst) ((inst) + 0x00000020), 0x0000040D +#define BF_LINEARX_OFFSET_CAL_EN_INFO(inst) ((inst) + 0x00000020), 0x00000111 +#define BF_LINEARX_OFFSET_IRQ_EN_INFO(inst) ((inst) + 0x00000020), 0x00000112 + +#define REG_LINEARX_OFFSET_CORR_COEF_ADDR(inst) ((inst) + 0x00000024) +#define BF_LINEARX_OFFSET_CANCELLATION_COEF_INFO(inst) ((inst) + 0x00000024), 0x00000900 + +#define REG_LINEARX_DEBUG_ADDR(inst) ((inst) + 0x00000028) +#define BF_DEBUG_MODE_HSRAM_CSRAM_EN_INFO(inst) ((inst) + 0x00000028), 0x00000200 +#define BF_DEBUG_MODE_CSRAM_NUM_INFO(inst) ((inst) + 0x00000028), 0x00000202 +#define BF_DEBUG_MODE_POLY_INFO(inst) ((inst) + 0x00000028), 0x00000204 +#define BF_DEBUG_MODE_INFO(inst) ((inst) + 0x00000028), 0x00000306 + +#define REG_LFSR_CONTROLS_ADDR(inst) ((inst) + 0x0000002C) +#define BF_ADDR_GEN_LFSR_EN_INFO(inst) ((inst) + 0x0000002C), 0x00000100 +#define BF_ADDR_GEN_LFSR_RESTART_INFO(inst) ((inst) + 0x0000002C), 0x00000101 +#define BF_DIST_REM_LFSR_EN_INFO(inst) ((inst) + 0x0000002C), 0x00000102 +#define BF_DIST_REM_LFSR_RESTART_INFO(inst) ((inst) + 0x0000002C), 0x00000103 +#define BF_THRESHOLD_LFSR_EN_INFO(inst) ((inst) + 0x0000002C), 0x00000104 +#define BF_THRESHOLD_LFSR_RESTART_INFO(inst) ((inst) + 0x0000002C), 0x00000105 +#define BF_REQUANT_LFSR_EN_INFO(inst) ((inst) + 0x0000002C), 0x00000106 +#define BF_REQUANT_LFSR_RESTART_INFO(inst) ((inst) + 0x0000002C), 0x00000107 + +#define REG_TRANSFER_ADDR(inst) ((inst) + 0x00000030) +#define BF_TRANSFER_OFFSET_CORR_INFO(inst) ((inst) + 0x00000030), 0x00000100 +#define BF_TRANSFER_OFFSET_CORR_IN_INFO(inst) ((inst) + 0x00000030), 0x00000101 +#define BF_READ_SEL_OFFSET_CORR_INFO(inst) ((inst) + 0x00000030), 0x00000104 +#define BF_READ_SEL_OFFSET_CORR_IN_INFO(inst) ((inst) + 0x00000030), 0x00000105 + +#define REG_LINEARX_INPUT_OFFSET_CORR_COEF_ADDR(inst) ((inst) + 0x00000034) +#define BF_LINEARX_OFFSET_CANCELLATION_COEF_IN_INFO(inst) ((inst) + 0x00000034), 0x00001000 + +#endif /* __ADI_APOLLO_BF_LINEARX_CORR_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_linearx_lut_mem_ctrl.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_linearx_lut_mem_ctrl.h new file mode 100644 index 00000000000000..ef7bff9da4b8f0 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_linearx_lut_mem_ctrl.h @@ -0,0 +1,281 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:19 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_LINEARX_LUT_MEM_CTRL_H__ +#define __ADI_APOLLO_BF_LINEARX_LUT_MEM_CTRL_H__ + +/*============= D E F I N E S ==============*/ +#define LINEARX_LUT_MEM_CTRL_RX_LINEARX_REG32_0_RX_SLICE_0_RX_DIGITAL0 0x60220B00 +#define LINEARX_LUT_MEM_CTRL_RX_LINEARX_REG32_1_RX_SLICE_0_RX_DIGITAL0 0x60228B00 +#define LINEARX_LUT_MEM_CTRL_RX_LINEARX_REG32_0_RX_SLICE_1_RX_DIGITAL0 0x60420B00 +#define LINEARX_LUT_MEM_CTRL_RX_LINEARX_REG32_1_RX_SLICE_1_RX_DIGITAL0 0x60428B00 +#define LINEARX_LUT_MEM_CTRL_RX_LINEARX_REG32_0_RX_SLICE_0_RX_DIGITAL1 0x60A20B00 +#define LINEARX_LUT_MEM_CTRL_RX_LINEARX_REG32_1_RX_SLICE_0_RX_DIGITAL1 0x60A28B00 +#define LINEARX_LUT_MEM_CTRL_RX_LINEARX_REG32_0_RX_SLICE_1_RX_DIGITAL1 0x60C20B00 +#define LINEARX_LUT_MEM_CTRL_RX_LINEARX_REG32_1_RX_SLICE_1_RX_DIGITAL1 0x60C28B00 +#define LINEARX_LUT_MEM_CTRL_TX_LINEARX_REG32_0_TX_SLICE_0_TX_DIGITAL0 0x61220B00 +#define LINEARX_LUT_MEM_CTRL_TX_LINEARX_REG32_1_TX_SLICE_0_TX_DIGITAL0 0x61228B00 +#define LINEARX_LUT_MEM_CTRL_TX_LINEARX_REG32_0_TX_SLICE_1_TX_DIGITAL0 0x61420B00 +#define LINEARX_LUT_MEM_CTRL_TX_LINEARX_REG32_1_TX_SLICE_1_TX_DIGITAL0 0x61428B00 +#define LINEARX_LUT_MEM_CTRL_TX_LINEARX_REG32_0_TX_SLICE_0_TX_DIGITAL1 0x61A20B00 +#define LINEARX_LUT_MEM_CTRL_TX_LINEARX_REG32_1_TX_SLICE_0_TX_DIGITAL1 0x61A28B00 +#define LINEARX_LUT_MEM_CTRL_TX_LINEARX_REG32_0_TX_SLICE_1_TX_DIGITAL1 0x61C20B00 +#define LINEARX_LUT_MEM_CTRL_TX_LINEARX_REG32_1_TX_SLICE_1_TX_DIGITAL1 0x61C28B00 + +#define REG_LINEARX_HSRAM_MUX_SEL0_ADDR(inst) ((inst) + 0x00000000) +#define BF_HSRAM_MUX_SEL0_INFO(inst) ((inst) + 0x00000000), 0x00000300 +#define BF_HSRAM_MUX_SEL1_INFO(inst) ((inst) + 0x00000000), 0x00000304 +#define BF_HSRAM_MUX_SEL2_INFO(inst) ((inst) + 0x00000000), 0x00000308 +#define BF_HSRAM_MUX_SEL3_INFO(inst) ((inst) + 0x00000000), 0x0000030C +#define BF_HSRAM_MUX_SEL4_INFO(inst) ((inst) + 0x00000000), 0x00000310 +#define BF_HSRAM_MUX_SEL5_INFO(inst) ((inst) + 0x00000000), 0x00000314 +#define BF_HSRAM_MUX_SEL6_INFO(inst) ((inst) + 0x00000000), 0x00000318 +#define BF_HSRAM_MUX_SEL7_INFO(inst) ((inst) + 0x00000000), 0x0000031C + +#define REG_LINEARX_HSRAM_MUX_SEL1_ADDR(inst) ((inst) + 0x00000004) +#define BF_HSRAM_MUX_SEL8_INFO(inst) ((inst) + 0x00000004), 0x00000300 +#define BF_HSRAM_MUX_SEL9_INFO(inst) ((inst) + 0x00000004), 0x00000304 +#define BF_HSRAM_MUX_SEL10_INFO(inst) ((inst) + 0x00000004), 0x00000308 +#define BF_HSRAM_MUX_SEL11_INFO(inst) ((inst) + 0x00000004), 0x0000030C +#define BF_HSRAM_MUX_SEL12_INFO(inst) ((inst) + 0x00000004), 0x00000310 +#define BF_HSRAM_MUX_SEL13_INFO(inst) ((inst) + 0x00000004), 0x00000314 +#define BF_HSRAM_MUX_SEL14_INFO(inst) ((inst) + 0x00000004), 0x00000318 +#define BF_HSRAM_MUX_SEL15_INFO(inst) ((inst) + 0x00000004), 0x0000031C + +#define REG_LINEARX_HSRAM_MUX_SEL2_ADDR(inst) ((inst) + 0x00000008) +#define BF_UPDATE_HSRAM_MUX_SEL0_INFO(inst) ((inst) + 0x00000008), 0x00000300 +#define BF_UPDATE_HSRAM_MUX_SEL1_INFO(inst) ((inst) + 0x00000008), 0x00000304 + +#define REG_LINEARX_CSRAM_MUX_SEL0_ADDR(inst) ((inst) + 0x00000010) +#define BF_CSRAM_MUX_SEL0_INFO(inst) ((inst) + 0x00000010), 0x00000300 +#define BF_CSRAM_MUX_SEL1_INFO(inst) ((inst) + 0x00000010), 0x00000304 +#define BF_CSRAM_MUX_SEL2_INFO(inst) ((inst) + 0x00000010), 0x00000308 +#define BF_CSRAM_MUX_SEL3_INFO(inst) ((inst) + 0x00000010), 0x0000030C +#define BF_CSRAM_MUX_SEL4_INFO(inst) ((inst) + 0x00000010), 0x00000310 +#define BF_CSRAM_MUX_SEL5_INFO(inst) ((inst) + 0x00000010), 0x00000314 +#define BF_CSRAM_MUX_SEL6_INFO(inst) ((inst) + 0x00000010), 0x00000318 +#define BF_CSRAM_MUX_SEL7_INFO(inst) ((inst) + 0x00000010), 0x0000031C + +#define REG_LINEARX_CSRAM_MUX_SEL1_ADDR(inst) ((inst) + 0x00000014) +#define BF_CSRAM_MUX_SEL8_INFO(inst) ((inst) + 0x00000014), 0x00000300 +#define BF_CSRAM_MUX_SEL9_INFO(inst) ((inst) + 0x00000014), 0x00000304 +#define BF_CSRAM_MUX_SEL10_INFO(inst) ((inst) + 0x00000014), 0x00000308 +#define BF_CSRAM_MUX_SEL11_INFO(inst) ((inst) + 0x00000014), 0x0000030C +#define BF_CSRAM_MUX_SEL12_INFO(inst) ((inst) + 0x00000014), 0x00000310 +#define BF_CSRAM_MUX_SEL13_INFO(inst) ((inst) + 0x00000014), 0x00000314 +#define BF_CSRAM_MUX_SEL14_INFO(inst) ((inst) + 0x00000014), 0x00000318 +#define BF_CSRAM_MUX_SEL15_INFO(inst) ((inst) + 0x00000014), 0x0000031C + +#define REG_LINEARX_CSRAM_MUX_SEL2_ADDR(inst) ((inst) + 0x00000018) +#define BF_UPDATE_CSRAM_MUX_SEL0_INFO(inst) ((inst) + 0x00000018), 0x00000300 +#define BF_UPDATE_CSRAM_MUX_SEL1_INFO(inst) ((inst) + 0x00000018), 0x00000304 + +#define REG_LINEARX_PATH_MUX_SEL0_ADDR(inst) ((inst) + 0x00000020) +#define BF_HSRAM_PATH_MUX_SEL0_INFO(inst) ((inst) + 0x00000020), 0x00000100 +#define BF_HSRAM_PATH_MUX_SEL1_INFO(inst) ((inst) + 0x00000020), 0x00000101 +#define BF_HSRAM_PATH_MUX_SEL2_INFO(inst) ((inst) + 0x00000020), 0x00000102 +#define BF_HSRAM_PATH_MUX_SEL3_INFO(inst) ((inst) + 0x00000020), 0x00000103 +#define BF_HSRAM_PATH_MUX_SEL4_INFO(inst) ((inst) + 0x00000020), 0x00000104 +#define BF_HSRAM_PATH_MUX_SEL5_INFO(inst) ((inst) + 0x00000020), 0x00000105 +#define BF_HSRAM_PATH_MUX_SEL6_INFO(inst) ((inst) + 0x00000020), 0x00000106 +#define BF_HSRAM_PATH_MUX_SEL7_INFO(inst) ((inst) + 0x00000020), 0x00000107 +#define BF_HSRAM_PATH_MUX_SEL8_INFO(inst) ((inst) + 0x00000020), 0x00000108 +#define BF_HSRAM_PATH_MUX_SEL9_INFO(inst) ((inst) + 0x00000020), 0x00000109 +#define BF_HSRAM_PATH_MUX_SEL10_INFO(inst) ((inst) + 0x00000020), 0x0000010A +#define BF_HSRAM_PATH_MUX_SEL11_INFO(inst) ((inst) + 0x00000020), 0x0000010B +#define BF_HSRAM_PATH_MUX_SEL12_INFO(inst) ((inst) + 0x00000020), 0x0000010C +#define BF_HSRAM_PATH_MUX_SEL13_INFO(inst) ((inst) + 0x00000020), 0x0000010D +#define BF_HSRAM_PATH_MUX_SEL14_INFO(inst) ((inst) + 0x00000020), 0x0000010E +#define BF_HSRAM_PATH_MUX_SEL15_INFO(inst) ((inst) + 0x00000020), 0x0000010F + +#define REG_LINEARX_PATH_MUX_SEL1_ADDR(inst) ((inst) + 0x00000024) +#define BF_CSRAM_PATH_MUX_SEL0_INFO(inst) ((inst) + 0x00000024), 0x00000100 +#define BF_CSRAM_PATH_MUX_SEL1_INFO(inst) ((inst) + 0x00000024), 0x00000101 +#define BF_CSRAM_PATH_MUX_SEL2_INFO(inst) ((inst) + 0x00000024), 0x00000102 +#define BF_CSRAM_PATH_MUX_SEL3_INFO(inst) ((inst) + 0x00000024), 0x00000103 +#define BF_CSRAM_PATH_MUX_SEL4_INFO(inst) ((inst) + 0x00000024), 0x00000104 +#define BF_CSRAM_PATH_MUX_SEL5_INFO(inst) ((inst) + 0x00000024), 0x00000105 +#define BF_CSRAM_PATH_MUX_SEL6_INFO(inst) ((inst) + 0x00000024), 0x00000106 +#define BF_CSRAM_PATH_MUX_SEL7_INFO(inst) ((inst) + 0x00000024), 0x00000107 +#define BF_CSRAM_PATH_MUX_SEL8_INFO(inst) ((inst) + 0x00000024), 0x00000108 +#define BF_CSRAM_PATH_MUX_SEL9_INFO(inst) ((inst) + 0x00000024), 0x00000109 +#define BF_CSRAM_PATH_MUX_SEL10_INFO(inst) ((inst) + 0x00000024), 0x0000010A +#define BF_CSRAM_PATH_MUX_SEL11_INFO(inst) ((inst) + 0x00000024), 0x0000010B +#define BF_CSRAM_PATH_MUX_SEL12_INFO(inst) ((inst) + 0x00000024), 0x0000010C +#define BF_CSRAM_PATH_MUX_SEL13_INFO(inst) ((inst) + 0x00000024), 0x0000010D +#define BF_CSRAM_PATH_MUX_SEL14_INFO(inst) ((inst) + 0x00000024), 0x0000010E +#define BF_CSRAM_PATH_MUX_SEL15_INFO(inst) ((inst) + 0x00000024), 0x0000010F + +#define REG_LINEARX_HSRAM_SD_ADDR(inst) ((inst) + 0x00000030) +#define BF_HSRAM_SD_INFO(inst) ((inst) + 0x00000030), 0x00001200 + +#define REG_LINEARX_HSRAM_SLP_ADDR(inst) ((inst) + 0x00000034) +#define BF_HSRAM_SLP_INFO(inst) ((inst) + 0x00000034), 0x00001200 + +#define REG_LINEARX_HSRAM_DSLP_ADDR(inst) ((inst) + 0x00000038) +#define BF_HSRAM_DSLP_INFO(inst) ((inst) + 0x00000038), 0x00001200 + +#define REG_LINEARX_CSRAM_SD0_ADDR(inst) ((inst) + 0x00000040) +#define BF_CSRAM_SD_INST0_INFO(inst) ((inst) + 0x00000040), 0x00001200 + +#define REG_LINEARX_CSRAM_SD1_ADDR(inst) ((inst) + 0x00000044) +#define BF_CSRAM_SD_INST1_INFO(inst) ((inst) + 0x00000044), 0x00001200 + +#define REG_LINEARX_CSRAM_SD2_ADDR(inst) ((inst) + 0x00000048) +#define BF_CSRAM_SD_INST2_INFO(inst) ((inst) + 0x00000048), 0x00001200 + +#define REG_LINEARX_CSRAM_SLP0_ADDR(inst) ((inst) + 0x00000050) +#define BF_CSRAM_SLP_INST0_INFO(inst) ((inst) + 0x00000050), 0x00001200 + +#define REG_LINEARX_CSRAM_SLP1_ADDR(inst) ((inst) + 0x00000054) +#define BF_CSRAM_SLP_INST1_INFO(inst) ((inst) + 0x00000054), 0x00001200 + +#define REG_LINEARX_CSRAM_SLP2_ADDR(inst) ((inst) + 0x00000058) +#define BF_CSRAM_SLP_INST2_INFO(inst) ((inst) + 0x00000058), 0x00001200 + +#define REG_LINEARX_CSRAM_DSLP0_ADDR(inst) ((inst) + 0x00000060) +#define BF_CSRAM_DSLP_INST0_INFO(inst) ((inst) + 0x00000060), 0x00001200 + +#define REG_LINEARX_CSRAM_DSLP1_ADDR(inst) ((inst) + 0x00000064) +#define BF_CSRAM_DSLP_INST1_INFO(inst) ((inst) + 0x00000064), 0x00001200 + +#define REG_LINEARX_CSRAM_DSLP2_ADDR(inst) ((inst) + 0x00000068) +#define BF_CSRAM_DSLP_INST2_INFO(inst) ((inst) + 0x00000068), 0x00001200 + +#define REG_LINEARX_SRAM_PARITY_CFG_ADDR(inst) ((inst) + 0x00000070) +#define BF_HSRAM_EN_PARITY_CHK_INFO(inst) ((inst) + 0x00000070), 0x00000100 +#define BF_CSRAM_EN_PARITY_CHK_INFO(inst) ((inst) + 0x00000070), 0x00000101 +#define BF_HSRAM_EN_PARITY_RB_INFO(inst) ((inst) + 0x00000070), 0x00000102 +#define BF_CSRAM_EN_PARITY_RB_INFO(inst) ((inst) + 0x00000070), 0x00000103 +#define BF_HSRAM_EN_PARITY_ERR_IRQ_INFO(inst) ((inst) + 0x00000070), 0x00000104 +#define BF_CSRAM_EN_PARITY_ERR_IRQ_INFO(inst) ((inst) + 0x00000070), 0x00000105 + +#define REG_LINEARX_SRAM_PARITY_ERR_ADDR(inst) ((inst) + 0x00000074) +#define BF_HSRAM_PARITY_ERR_IRQ_INFO(inst) ((inst) + 0x00000074), 0x00000100 +#define BF_CSRAM_PARITY_ERR_IRQ_INFO(inst) ((inst) + 0x00000074), 0x00000101 + +#define REG_LINEARX_HSRAM_PARITY_ERR0_ADDR(inst) ((inst) + 0x00000080) +#define BF_HSRAM0_PARITY_ERR_INFO(inst) ((inst) + 0x00000080), 0x00000400 +#define BF_HSRAM1_PARITY_ERR_INFO(inst) ((inst) + 0x00000080), 0x00000404 +#define BF_HSRAM2_PARITY_ERR_INFO(inst) ((inst) + 0x00000080), 0x00000408 +#define BF_HSRAM3_PARITY_ERR_INFO(inst) ((inst) + 0x00000080), 0x0000040C +#define BF_HSRAM4_PARITY_ERR_INFO(inst) ((inst) + 0x00000080), 0x00000410 +#define BF_HSRAM5_PARITY_ERR_INFO(inst) ((inst) + 0x00000080), 0x00000414 +#define BF_HSRAM6_PARITY_ERR_INFO(inst) ((inst) + 0x00000080), 0x00000418 +#define BF_HSRAM7_PARITY_ERR_INFO(inst) ((inst) + 0x00000080), 0x0000041C + +#define REG_LINEARX_HSRAM_PARITY_ERR1_ADDR(inst) ((inst) + 0x00000084) +#define BF_HSRAM8_PARITY_ERR_INFO(inst) ((inst) + 0x00000084), 0x00000400 +#define BF_HSRAM9_PARITY_ERR_INFO(inst) ((inst) + 0x00000084), 0x00000404 +#define BF_HSRAM10_PARITY_ERR_INFO(inst) ((inst) + 0x00000084), 0x00000408 +#define BF_HSRAM11_PARITY_ERR_INFO(inst) ((inst) + 0x00000084), 0x0000040C +#define BF_HSRAM12_PARITY_ERR_INFO(inst) ((inst) + 0x00000084), 0x00000410 +#define BF_HSRAM13_PARITY_ERR_INFO(inst) ((inst) + 0x00000084), 0x00000414 +#define BF_HSRAM14_PARITY_ERR_INFO(inst) ((inst) + 0x00000084), 0x00000418 +#define BF_HSRAM15_PARITY_ERR_INFO(inst) ((inst) + 0x00000084), 0x0000041C + +#define REG_LINEARX_HSRAM_PARITY_ERR2_ADDR(inst) ((inst) + 0x00000088) +#define BF_UPDATE_HSRAM0_PARITY_ERR_INFO(inst) ((inst) + 0x00000088), 0x00000400 +#define BF_UPDATE_HSRAM1_PARITY_ERR_INFO(inst) ((inst) + 0x00000088), 0x00000404 + +#define REG_LINEARX_CSRAM_PARITY_ERR0_ADDR(inst) ((inst) + 0x00000090) +#define BF_CSRAM0_INST0_PARITY_ERR_INFO(inst) ((inst) + 0x00000090), 0x00000400 +#define BF_CSRAM1_INST0_PARITY_ERR_INFO(inst) ((inst) + 0x00000090), 0x00000404 +#define BF_CSRAM2_INST0_PARITY_ERR_INFO(inst) ((inst) + 0x00000090), 0x00000408 +#define BF_CSRAM3_INST0_PARITY_ERR_INFO(inst) ((inst) + 0x00000090), 0x0000040C +#define BF_CSRAM4_INST0_PARITY_ERR_INFO(inst) ((inst) + 0x00000090), 0x00000410 +#define BF_CSRAM5_INST0_PARITY_ERR_INFO(inst) ((inst) + 0x00000090), 0x00000414 +#define BF_CSRAM6_INST0_PARITY_ERR_INFO(inst) ((inst) + 0x00000090), 0x00000418 +#define BF_CSRAM7_INST0_PARITY_ERR_INFO(inst) ((inst) + 0x00000090), 0x0000041C + +#define REG_LINEARX_CSRAM_PARITY_ERR1_ADDR(inst) ((inst) + 0x00000094) +#define BF_CSRAM8_INST0_PARITY_ERR_INFO(inst) ((inst) + 0x00000094), 0x00000400 +#define BF_CSRAM9_INST0_PARITY_ERR_INFO(inst) ((inst) + 0x00000094), 0x00000404 +#define BF_CSRAM10_INST0_PARITY_ERR_INFO(inst) ((inst) + 0x00000094), 0x00000408 +#define BF_CSRAM11_INST0_PARITY_ERR_INFO(inst) ((inst) + 0x00000094), 0x0000040C +#define BF_CSRAM12_INST0_PARITY_ERR_INFO(inst) ((inst) + 0x00000094), 0x00000410 +#define BF_CSRAM13_INST0_PARITY_ERR_INFO(inst) ((inst) + 0x00000094), 0x00000414 +#define BF_CSRAM14_INST0_PARITY_ERR_INFO(inst) ((inst) + 0x00000094), 0x00000418 +#define BF_CSRAM15_INST0_PARITY_ERR_INFO(inst) ((inst) + 0x00000094), 0x0000041C + +#define REG_LINEARX_CSRAM_PARITY_ERR2_ADDR(inst) ((inst) + 0x00000098) +#define BF_UPDATE_CSRAM0_INST0_PARITY_ERR_INFO(inst) ((inst) + 0x00000098), 0x00000400 +#define BF_UPDATE_CSRAM1_INST0_PARITY_ERR_INFO(inst) ((inst) + 0x00000098), 0x00000404 + +#define REG_LINEARX_CSRAM_PARITY_ERR3_ADDR(inst) ((inst) + 0x000000A0) +#define BF_CSRAM0_INST1_PARITY_ERR_INFO(inst) ((inst) + 0x000000A0), 0x00000400 +#define BF_CSRAM1_INST1_PARITY_ERR_INFO(inst) ((inst) + 0x000000A0), 0x00000404 +#define BF_CSRAM2_INST1_PARITY_ERR_INFO(inst) ((inst) + 0x000000A0), 0x00000408 +#define BF_CSRAM3_INST1_PARITY_ERR_INFO(inst) ((inst) + 0x000000A0), 0x0000040C +#define BF_CSRAM4_INST1_PARITY_ERR_INFO(inst) ((inst) + 0x000000A0), 0x00000410 +#define BF_CSRAM5_INST1_PARITY_ERR_INFO(inst) ((inst) + 0x000000A0), 0x00000414 +#define BF_CSRAM6_INST1_PARITY_ERR_INFO(inst) ((inst) + 0x000000A0), 0x00000418 +#define BF_CSRAM7_INST1_PARITY_ERR_INFO(inst) ((inst) + 0x000000A0), 0x0000041C + +#define REG_LINEARX_CSRAM_PARITY_ERR4_ADDR(inst) ((inst) + 0x000000A4) +#define BF_CSRAM8_INST1_PARITY_ERR_INFO(inst) ((inst) + 0x000000A4), 0x00000400 +#define BF_CSRAM9_INST1_PARITY_ERR_INFO(inst) ((inst) + 0x000000A4), 0x00000404 +#define BF_CSRAM10_INST1_PARITY_ERR_INFO(inst) ((inst) + 0x000000A4), 0x00000408 +#define BF_CSRAM11_INST1_PARITY_ERR_INFO(inst) ((inst) + 0x000000A4), 0x0000040C +#define BF_CSRAM12_INST1_PARITY_ERR_INFO(inst) ((inst) + 0x000000A4), 0x00000410 +#define BF_CSRAM13_INST1_PARITY_ERR_INFO(inst) ((inst) + 0x000000A4), 0x00000414 +#define BF_CSRAM14_INST1_PARITY_ERR_INFO(inst) ((inst) + 0x000000A4), 0x00000418 +#define BF_CSRAM15_INST1_PARITY_ERR_INFO(inst) ((inst) + 0x000000A4), 0x0000041C + +#define REG_LINEARX_CSRAM_PARITY_ERR5_ADDR(inst) ((inst) + 0x000000A8) +#define BF_UPDATE_CSRAM0_INST1_PARITY_ERR_INFO(inst) ((inst) + 0x000000A8), 0x00000400 +#define BF_UPDATE_CSRAM1_INST1_PARITY_ERR_INFO(inst) ((inst) + 0x000000A8), 0x00000404 + +#define REG_LINEARX_CSRAM_PARITY_ERR6_ADDR(inst) ((inst) + 0x000000B0) +#define BF_CSRAM0_INST2_PARITY_ERR_INFO(inst) ((inst) + 0x000000B0), 0x00000400 +#define BF_CSRAM1_INST2_PARITY_ERR_INFO(inst) ((inst) + 0x000000B0), 0x00000404 +#define BF_CSRAM2_INST2_PARITY_ERR_INFO(inst) ((inst) + 0x000000B0), 0x00000408 +#define BF_CSRAM3_INST2_PARITY_ERR_INFO(inst) ((inst) + 0x000000B0), 0x0000040C +#define BF_CSRAM4_INST2_PARITY_ERR_INFO(inst) ((inst) + 0x000000B0), 0x00000410 +#define BF_CSRAM5_INST2_PARITY_ERR_INFO(inst) ((inst) + 0x000000B0), 0x00000414 +#define BF_CSRAM6_INST2_PARITY_ERR_INFO(inst) ((inst) + 0x000000B0), 0x00000418 +#define BF_CSRAM7_INST2_PARITY_ERR_INFO(inst) ((inst) + 0x000000B0), 0x0000041C + +#define REG_LINEARX_CSRAM_PARITY_ERR7_ADDR(inst) ((inst) + 0x000000B4) +#define BF_CSRAM8_INST2_PARITY_ERR_INFO(inst) ((inst) + 0x000000B4), 0x00000400 +#define BF_CSRAM9_INST2_PARITY_ERR_INFO(inst) ((inst) + 0x000000B4), 0x00000404 +#define BF_CSRAM10_INST2_PARITY_ERR_INFO(inst) ((inst) + 0x000000B4), 0x00000408 +#define BF_CSRAM11_INST2_PARITY_ERR_INFO(inst) ((inst) + 0x000000B4), 0x0000040C +#define BF_CSRAM12_INST2_PARITY_ERR_INFO(inst) ((inst) + 0x000000B4), 0x00000410 +#define BF_CSRAM13_INST2_PARITY_ERR_INFO(inst) ((inst) + 0x000000B4), 0x00000414 +#define BF_CSRAM14_INST2_PARITY_ERR_INFO(inst) ((inst) + 0x000000B4), 0x00000418 +#define BF_CSRAM15_INST2_PARITY_ERR_INFO(inst) ((inst) + 0x000000B4), 0x0000041C + +#define REG_LINEARX_CSRAM_PARITY_ERR8_ADDR(inst) ((inst) + 0x000000B8) +#define BF_UPDATE_CSRAM0_INST2_PARITY_ERR_INFO(inst) ((inst) + 0x000000B8), 0x00000400 +#define BF_UPDATE_CSRAM1_INST2_PARITY_ERR_INFO(inst) ((inst) + 0x000000B8), 0x00000404 + +#define REG_LINEARX_HSRAM_CLK_EN_ADDR(inst) ((inst) + 0x000000C0) +#define BF_HSRAM_CLK_EN_INFO(inst) ((inst) + 0x000000C0), 0x00001200 + +#define REG_LINEARX_CSRAM_CLK_EN0_ADDR(inst) ((inst) + 0x000000C4) +#define BF_CSRAM_CLK_EN_INST0_INFO(inst) ((inst) + 0x000000C4), 0x00001200 + +#define REG_LINEARX_CSRAM_CLK_EN1_ADDR(inst) ((inst) + 0x000000C8) +#define BF_CSRAM_CLK_EN_INST1_INFO(inst) ((inst) + 0x000000C8), 0x00001200 + +#define REG_LINEARX_CSRAM_CLK_EN2_ADDR(inst) ((inst) + 0x000000CC) +#define BF_CSRAM_CLK_EN_INST2_INFO(inst) ((inst) + 0x000000CC), 0x00001200 + +#define REG_LINEARX_RESET_CLK_MUX_ADDR(inst) ((inst) + 0x000000D0) +#define BF_HSRAM_RESET_CLK_MUX_INFO(inst) ((inst) + 0x000000D0), 0x00000100 +#define BF_CSRAM_RESET_CLK_MUX_INFO(inst) ((inst) + 0x000000D0), 0x00000101 + +#endif /* __ADI_APOLLO_BF_LINEARX_LUT_MEM_CTRL_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_linearx_lutp_master.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_linearx_lutp_master.h new file mode 100644 index 00000000000000..5ae7dc9a595189 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_linearx_lutp_master.h @@ -0,0 +1,70 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:19 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_LINEARX_LUTP_MASTER_H__ +#define __ADI_APOLLO_BF_LINEARX_LUTP_MASTER_H__ + +/*============= D E F I N E S ==============*/ +#define LINEARX_LUTP_MASTER_RX_LINEARX_REG32_0_RX_SLICE_0_RX_DIGITAL0 0x60220200 +#define LINEARX_LUTP_MASTER_RX_LINEARX_REG32_1_RX_SLICE_0_RX_DIGITAL0 0x60228200 +#define LINEARX_LUTP_MASTER_RX_LINEARX_REG32_0_RX_SLICE_1_RX_DIGITAL0 0x60420200 +#define LINEARX_LUTP_MASTER_RX_LINEARX_REG32_1_RX_SLICE_1_RX_DIGITAL0 0x60428200 +#define LINEARX_LUTP_MASTER_RX_LINEARX_REG32_0_RX_SLICE_0_RX_DIGITAL1 0x60A20200 +#define LINEARX_LUTP_MASTER_RX_LINEARX_REG32_1_RX_SLICE_0_RX_DIGITAL1 0x60A28200 +#define LINEARX_LUTP_MASTER_RX_LINEARX_REG32_0_RX_SLICE_1_RX_DIGITAL1 0x60C20200 +#define LINEARX_LUTP_MASTER_RX_LINEARX_REG32_1_RX_SLICE_1_RX_DIGITAL1 0x60C28200 +#define LINEARX_LUTP_MASTER_TX_LINEARX_REG32_0_TX_SLICE_0_TX_DIGITAL0 0x61220200 +#define LINEARX_LUTP_MASTER_TX_LINEARX_REG32_1_TX_SLICE_0_TX_DIGITAL0 0x61228200 +#define LINEARX_LUTP_MASTER_TX_LINEARX_REG32_0_TX_SLICE_1_TX_DIGITAL0 0x61420200 +#define LINEARX_LUTP_MASTER_TX_LINEARX_REG32_1_TX_SLICE_1_TX_DIGITAL0 0x61428200 +#define LINEARX_LUTP_MASTER_TX_LINEARX_REG32_0_TX_SLICE_0_TX_DIGITAL1 0x61A20200 +#define LINEARX_LUTP_MASTER_TX_LINEARX_REG32_1_TX_SLICE_0_TX_DIGITAL1 0x61A28200 +#define LINEARX_LUTP_MASTER_TX_LINEARX_REG32_0_TX_SLICE_1_TX_DIGITAL1 0x61C20200 +#define LINEARX_LUTP_MASTER_TX_LINEARX_REG32_1_TX_SLICE_1_TX_DIGITAL1 0x61C28200 + +#define REG_LINEARX_LUTP_MASTER_START_ADDR(inst) ((inst) + 0x00000000) +#define BF_LUTP_MASTER_START_INFO(inst) ((inst) + 0x00000000), 0x00000100 + +#define REG_LINEARX_LUTP_MASTER_HCONFIG_ADDR(inst) ((inst) + 0x00000004) +#define BF_LUTP_MASTER_HSCALE_INFO(inst) ((inst) + 0x00000004), 0x00000300 +#define BF_LUTP_MASTER_POLY_ORDER_INFO(inst) ((inst) + 0x00000004), 0x00000308 +#define BF_LUTP_MASTER_HOUTPUT_BITS_INFO(inst) ((inst) + 0x00000004), 0x00000410 + +#define REG_LINEARX_LUTP_MASTER_CCONFIG_ADDR(inst) ((inst) + 0x00000008) +#define BF_LUTP_MASTER_CENABLE_INFO(inst) ((inst) + 0x00000008), 0x00000100 +#define BF_LUTP_MASTER_CSCALE_INFO(inst) ((inst) + 0x00000008), 0x00000308 +#define BF_LUTP_MASTER_CTAP_CNT_INFO(inst) ((inst) + 0x00000008), 0x00000510 +#define BF_LUTP_MASTER_COUTPUT_BITS_INFO(inst) ((inst) + 0x00000008), 0x00000418 + +#define REG_LINEARX_LUTP_MASTER_HCCONFIG_ADDR(inst) ((inst) + 0x0000000C) +#define BF_LUTP_MASTER_START_OFFSET_INFO(inst) ((inst) + 0x0000000C), 0x00000800 +#define BF_LUTP_MASTER_LUT_SIZE_INFO(inst) ((inst) + 0x0000000C), 0x00000908 + +#define REG_LINEARX_LUTP_MASTER_IRQ_ENABLE_ADDR(inst) ((inst) + 0x00000010) +#define BF_LUTP_MASTER_IRQ_EN_INFO(inst) ((inst) + 0x00000010), 0x00000100 + +#define REG_LINEARX_LUTP_MASTER_DONE_ADDR(inst) ((inst) + 0x00000014) +#define BF_LUTP_MASTER_DONE_INFO(inst) ((inst) + 0x00000014), 0x00000100 + +#define REG_LINEARX_LUTP_MASTER_DONE_CLEAR_ADDR(inst) ((inst) + 0x00000018) +#define BF_LUTP_MASTER_DONE_CLEAR_INFO(inst) ((inst) + 0x00000018), 0x00000100 + +#define REG_LINEARX_LUTP_HCOEFFS_ADDR(inst, n) ((inst) + 0x0000001C + 4 * (n)) +#define BF_LUTP_MASTER_HCOEFFS_INFO(inst, n) ((inst) + 0x0000001C + 4 * (n)), 0x00001000 + +#define REG_LINEARX_LUTP_CCOEFFS_ADDR(inst, n) ((inst) + 0x0000039C + 4 * (n)) +#define BF_LUTP_MASTER_CCOEFFS_INFO(inst, n) ((inst) + 0x0000039C + 4 * (n)), 0x00001000 + +#endif /* __ADI_APOLLO_BF_LINEARX_LUTP_MASTER_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_linearx_lutp_slave.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_linearx_lutp_slave.h new file mode 100644 index 00000000000000..725cc3dfc1afd0 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_linearx_lutp_slave.h @@ -0,0 +1,66 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:19 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_LINEARX_LUTP_SLAVE_H__ +#define __ADI_APOLLO_BF_LINEARX_LUTP_SLAVE_H__ + +/*============= D E F I N E S ==============*/ +#define LINEARX_LUTP_SLAVE_RX_LINEARX_REG32_0_RX_SLICE_0_RX_DIGITAL0 0x60220A00 +#define LINEARX_LUTP_SLAVE_RX_LINEARX_REG32_1_RX_SLICE_0_RX_DIGITAL0 0x60228A00 +#define LINEARX_LUTP_SLAVE_RX_LINEARX_REG32_0_RX_SLICE_1_RX_DIGITAL0 0x60420A00 +#define LINEARX_LUTP_SLAVE_RX_LINEARX_REG32_1_RX_SLICE_1_RX_DIGITAL0 0x60428A00 +#define LINEARX_LUTP_SLAVE_RX_LINEARX_REG32_0_RX_SLICE_0_RX_DIGITAL1 0x60A20A00 +#define LINEARX_LUTP_SLAVE_RX_LINEARX_REG32_1_RX_SLICE_0_RX_DIGITAL1 0x60A28A00 +#define LINEARX_LUTP_SLAVE_RX_LINEARX_REG32_0_RX_SLICE_1_RX_DIGITAL1 0x60C20A00 +#define LINEARX_LUTP_SLAVE_RX_LINEARX_REG32_1_RX_SLICE_1_RX_DIGITAL1 0x60C28A00 +#define LINEARX_LUTP_SLAVE_TX_LINEARX_REG32_0_TX_SLICE_0_TX_DIGITAL0 0x61220A00 +#define LINEARX_LUTP_SLAVE_TX_LINEARX_REG32_1_TX_SLICE_0_TX_DIGITAL0 0x61228A00 +#define LINEARX_LUTP_SLAVE_TX_LINEARX_REG32_0_TX_SLICE_1_TX_DIGITAL0 0x61420A00 +#define LINEARX_LUTP_SLAVE_TX_LINEARX_REG32_1_TX_SLICE_1_TX_DIGITAL0 0x61428A00 +#define LINEARX_LUTP_SLAVE_TX_LINEARX_REG32_0_TX_SLICE_0_TX_DIGITAL1 0x61A20A00 +#define LINEARX_LUTP_SLAVE_TX_LINEARX_REG32_1_TX_SLICE_0_TX_DIGITAL1 0x61A28A00 +#define LINEARX_LUTP_SLAVE_TX_LINEARX_REG32_0_TX_SLICE_1_TX_DIGITAL1 0x61C20A00 +#define LINEARX_LUTP_SLAVE_TX_LINEARX_REG32_1_TX_SLICE_1_TX_DIGITAL1 0x61C28A00 + +#define REG_LINEARX_LUTP_SLAVE_START_ADDR(inst) ((inst) + 0x00000000) +#define BF_LUTP_SLAVE_HSRAM_START_INFO(inst) ((inst) + 0x00000000), 0x00000100 +#define BF_LUTP_SLAVE_CSRAM_START_INFO(inst) ((inst) + 0x00000000), 0x00000101 + +#define REG_LINEARX_LUTP_SLAVE_DONE_ADDR(inst) ((inst) + 0x00000004) +#define BF_LUTP_SLAVE_HSRAM_DONE_INFO(inst) ((inst) + 0x00000004), 0x00000100 +#define BF_LUTP_SLAVE_CSRAM_DONE_INFO(inst) ((inst) + 0x00000004), 0x00000101 + +#define REG_LINEARX_LUTP_SLAVE_START_EN_ADDR(inst) ((inst) + 0x00000008) +#define BF_LUTP_SLAVE_HSRAM_START_FROM_MASTER_EN_INFO(inst) ((inst) + 0x00000008), 0x00000100 +#define BF_LUTP_SLAVE_CSRAM_START_FROM_MASTER_EN_INFO(inst) ((inst) + 0x00000008), 0x00000101 + +#define REG_LINEARX_LUTP_SLAVE_CLK_ENABLE_ADDR(inst) ((inst) + 0x0000000C) +#define BF_LUTP_SLAVE_CLK_EN_INFO(inst) ((inst) + 0x0000000C), 0x00000100 + +#define REG_LINEARX_LUTP_SLAVE_IRQ_ENABLE_ADDR(inst) ((inst) + 0x00000010) +#define BF_LUTP_SLAVE_HSRAM_IRQ_EN_INFO(inst) ((inst) + 0x00000010), 0x00000100 +#define BF_LUTP_SLAVE_CSRAM_IRQ_EN_INFO(inst) ((inst) + 0x00000010), 0x00000101 + +#define REG_LINEARX_LUTP_SLAVE_CONFIG_ADDR(inst) ((inst) + 0x00000020) +#define BF_LUTP_SLAVE_CLK_MUX_WAIT_COUNT_INFO(inst) ((inst) + 0x00000020), 0x00000400 +#define BF_LUTP_SLAVE_PATH_MUX_WAIT_COUNT_INFO(inst) ((inst) + 0x00000020), 0x00000404 + +#define REG_LINEARX_LUTP_SLAVE_FSM_ADDR(inst) ((inst) + 0x00000024) +#define BF_LUTP_SLAVE_HSRAM_FSM_STATE_INFO(inst) ((inst) + 0x00000024), 0x00000400 +#define BF_LUTP_SLAVE_CSRAM_FSM_STATE_INFO(inst) ((inst) + 0x00000024), 0x00000404 +#define BF_LUTP_SLAVE_HSRAM_RESET_FSM_INFO(inst) ((inst) + 0x00000024), 0x00000108 +#define BF_LUTP_SLAVE_CSRAM_RESET_FSM_INFO(inst) ((inst) + 0x00000024), 0x00000109 + +#endif /* __ADI_APOLLO_BF_LINEARX_LUTP_SLAVE_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_linearx_misc.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_linearx_misc.h new file mode 100644 index 00000000000000..7893861d02d3aa --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_linearx_misc.h @@ -0,0 +1,50 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:19 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_LINEARX_MISC_H__ +#define __ADI_APOLLO_BF_LINEARX_MISC_H__ + +/*============= D E F I N E S ==============*/ +#define LINEARX_MISC_RX_LINEARX_REG32_0_RX_SLICE_0_RX_DIGITAL0 0x60220080 +#define LINEARX_MISC_RX_LINEARX_REG32_1_RX_SLICE_0_RX_DIGITAL0 0x60228080 +#define LINEARX_MISC_RX_LINEARX_REG32_0_RX_SLICE_1_RX_DIGITAL0 0x60420080 +#define LINEARX_MISC_RX_LINEARX_REG32_1_RX_SLICE_1_RX_DIGITAL0 0x60428080 +#define LINEARX_MISC_RX_LINEARX_REG32_0_RX_SLICE_0_RX_DIGITAL1 0x60A20080 +#define LINEARX_MISC_RX_LINEARX_REG32_1_RX_SLICE_0_RX_DIGITAL1 0x60A28080 +#define LINEARX_MISC_RX_LINEARX_REG32_0_RX_SLICE_1_RX_DIGITAL1 0x60C20080 +#define LINEARX_MISC_RX_LINEARX_REG32_1_RX_SLICE_1_RX_DIGITAL1 0x60C28080 +#define LINEARX_MISC_TX_LINEARX_REG32_0_TX_SLICE_0_TX_DIGITAL0 0x61220080 +#define LINEARX_MISC_TX_LINEARX_REG32_1_TX_SLICE_0_TX_DIGITAL0 0x61228080 +#define LINEARX_MISC_TX_LINEARX_REG32_0_TX_SLICE_1_TX_DIGITAL0 0x61420080 +#define LINEARX_MISC_TX_LINEARX_REG32_1_TX_SLICE_1_TX_DIGITAL0 0x61428080 +#define LINEARX_MISC_TX_LINEARX_REG32_0_TX_SLICE_0_TX_DIGITAL1 0x61A20080 +#define LINEARX_MISC_TX_LINEARX_REG32_1_TX_SLICE_0_TX_DIGITAL1 0x61A28080 +#define LINEARX_MISC_TX_LINEARX_REG32_0_TX_SLICE_1_TX_DIGITAL1 0x61C20080 +#define LINEARX_MISC_TX_LINEARX_REG32_1_TX_SLICE_1_TX_DIGITAL1 0x61C28080 + +#define REG_BMEM_CTRL_ADDR(inst) ((inst) + 0x00000000) +#define BF_BMEM_ADC1_SEL_INFO(inst) ((inst) + 0x00000000), 0x00000100 +#define BF_NLCA_ACCESS_BMEM_INFO(inst) ((inst) + 0x00000000), 0x00000101 +#define BF_BMEM_FULL_IRQ_EN_INFO(inst) ((inst) + 0x00000000), 0x00000102 +#define BF_BMEM_PARITY_ERR_IRQ_EN_INFO(inst) ((inst) + 0x00000000), 0x00000103 + +#define REG_LINEARX_LUT_UPDATE_IRQ_ADDR(inst) ((inst) + 0x00000004) +#define BF_LUT_UPDATE_DONE_CLEAR_INFO(inst) ((inst) + 0x00000004), 0x00000100 +#define BF_LUT_UPDATE_IRQ_SEL_INFO(inst) ((inst) + 0x00000004), 0x00000101 + +#define REG_LINEARX_DEBUG_CLK_SEL_ADDR(inst) ((inst) + 0x00000008) +#define BF_DEBUG_CLK_SEL_LINEARX_MISC_INFO(inst) ((inst) + 0x00000008), 0x00000300 + +#endif /* __ADI_APOLLO_BF_LINEARX_MISC_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_linearx_nlca.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_linearx_nlca.h new file mode 100644 index 00000000000000..b1fe20c5a28afc --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_linearx_nlca.h @@ -0,0 +1,99 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:19 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_LINEARX_NLCA_H__ +#define __ADI_APOLLO_BF_LINEARX_NLCA_H__ + +/*============= D E F I N E S ==============*/ +#define LINEARX_NLCA_RX_LINEARX_REG32_0_RX_SLICE_0_RX_DIGITAL0 0x60220C00 +#define LINEARX_NLCA_RX_LINEARX_REG32_1_RX_SLICE_0_RX_DIGITAL0 0x60228C00 +#define LINEARX_NLCA_RX_LINEARX_REG32_0_RX_SLICE_1_RX_DIGITAL0 0x60420C00 +#define LINEARX_NLCA_RX_LINEARX_REG32_1_RX_SLICE_1_RX_DIGITAL0 0x60428C00 +#define LINEARX_NLCA_RX_LINEARX_REG32_0_RX_SLICE_0_RX_DIGITAL1 0x60A20C00 +#define LINEARX_NLCA_RX_LINEARX_REG32_1_RX_SLICE_0_RX_DIGITAL1 0x60A28C00 +#define LINEARX_NLCA_RX_LINEARX_REG32_0_RX_SLICE_1_RX_DIGITAL1 0x60C20C00 +#define LINEARX_NLCA_RX_LINEARX_REG32_1_RX_SLICE_1_RX_DIGITAL1 0x60C28C00 +#define LINEARX_NLCA_TX_LINEARX_REG32_0_TX_SLICE_0_TX_DIGITAL0 0x61220C00 +#define LINEARX_NLCA_TX_LINEARX_REG32_1_TX_SLICE_0_TX_DIGITAL0 0x61228C00 +#define LINEARX_NLCA_TX_LINEARX_REG32_0_TX_SLICE_1_TX_DIGITAL0 0x61420C00 +#define LINEARX_NLCA_TX_LINEARX_REG32_1_TX_SLICE_1_TX_DIGITAL0 0x61428C00 +#define LINEARX_NLCA_TX_LINEARX_REG32_0_TX_SLICE_0_TX_DIGITAL1 0x61A20C00 +#define LINEARX_NLCA_TX_LINEARX_REG32_1_TX_SLICE_0_TX_DIGITAL1 0x61A28C00 +#define LINEARX_NLCA_TX_LINEARX_REG32_0_TX_SLICE_1_TX_DIGITAL1 0x61C20C00 +#define LINEARX_NLCA_TX_LINEARX_REG32_1_TX_SLICE_1_TX_DIGITAL1 0x61C28C00 + +#define REG_NLCA_OFFSET_A_ADDR(inst) ((inst) + 0x00000000) +#define BF_NLCA_OFFSET_A_INFO(inst) ((inst) + 0x00000000), 0x00001000 + +#define REG_NLCA_SHIFT_ADDR(inst) ((inst) + 0x00000004) +#define BF_NLCA_SHIFT_ADDR_A_INFO(inst) ((inst) + 0x00000004), 0x00000800 +#define BF_NLCA_SHIFT_SAMP_A_INFO(inst) ((inst) + 0x00000004), 0x00000608 +#define BF_NLCA_SHIFT_SAMP_B_INFO(inst) ((inst) + 0x00000004), 0x0000060E +#define BF_NLCA_SHIFT_SAMP_X_INFO(inst) ((inst) + 0x00000004), 0x00000614 +#define BF_NLCA_SHIFT_SAMP_Y_INFO(inst) ((inst) + 0x00000004), 0x0000061A + +#define REG_NLCA_ADDR_A_B_ADDR(inst) ((inst) + 0x00000008) +#define BF_NLCA_ADDR_A_START_INFO(inst) ((inst) + 0x00000008), 0x00000A00 +#define BF_NLCA_ADDR_B_START_INFO(inst) ((inst) + 0x00000008), 0x00000A0A + +#define REG_NLCA_ADDR_X_Y_ADDR(inst) ((inst) + 0x0000000C) +#define BF_NLCA_ADDR_X_START_INFO(inst) ((inst) + 0x0000000C), 0x00000A00 +#define BF_NLCA_ADDR_Y_START_INFO(inst) ((inst) + 0x0000000C), 0x00000A0A + +#define REG_NLCA_ADDR_R_ADDR(inst) ((inst) + 0x00000010) +#define BF_NLCA_ADDR_R_START_INFO(inst) ((inst) + 0x00000010), 0x00000A00 + +#define REG_NLCA_OP_CODE_ADDR(inst) ((inst) + 0x00000014) +#define BF_NLCA_OP_CODE_INFO(inst) ((inst) + 0x00000014), 0x00000400 + +#define REG_NLCA_OP_START_ADDR(inst) ((inst) + 0x00000018) +#define BF_NLCA_OP_START_INFO(inst) ((inst) + 0x00000018), 0x00000100 + +#define REG_NLCA_OP_DONE_ADDR(inst) ((inst) + 0x0000001C) +#define BF_NLCA_OP_DONE_INFO(inst) ((inst) + 0x0000001C), 0x00000100 +#define BF_FSM_ERROR_FLAG_INFO(inst) ((inst) + 0x0000001C), 0x00000101 + +#define REG_NLCA_IRQ_EN_ADDR(inst) ((inst) + 0x00000020) +#define BF_NLCA_IRQ_EN_INFO(inst) ((inst) + 0x00000020), 0x00000100 + +#define REG_NLCA_OP_ACK_ADDR(inst) ((inst) + 0x00000024) +#define BF_NLCA_OP_ACK_INFO(inst) ((inst) + 0x00000024), 0x00000100 + +#define REG_NLCA_RESET_FSM_ADDR(inst) ((inst) + 0x00000028) +#define BF_NLCA_RESET_FSM_INFO(inst) ((inst) + 0x00000028), 0x00000100 + +#define REG_NLCA_FSM_STATE_ADDR(inst) ((inst) + 0x0000002C) +#define BF_NLCA_FSM_STATE_INFO(inst) ((inst) + 0x0000002C), 0x00000500 + +#define REG_NLCA_MAX_LAG_ADDR(inst) ((inst) + 0x00000030) +#define BF_NLCA_MAX_LAG_INFO(inst) ((inst) + 0x00000030), 0x00000600 + +#define REG_NLCA_FILT_SETTINGS_ADDR(inst) ((inst) + 0x00000034) +#define BF_NLCA_R_ADD_SUB_SHIFT_INFO(inst) ((inst) + 0x00000034), 0x00000100 +#define BF_NLCA_R_MULT_SHIFT_INFO(inst) ((inst) + 0x00000034), 0x00000401 +#define BF_NLCA_Q_IN_SHIFT_INFO(inst) ((inst) + 0x00000034), 0x00000505 +#define BF_NLCA_Q_IN_ROUND_EN_INFO(inst) ((inst) + 0x00000034), 0x0000010A +#define BF_NLCA_R_OUT_ROUND_EN_INFO(inst) ((inst) + 0x00000034), 0x0000010B +#define BF_NLCA_PN_RUN_CNT_INFO(inst) ((inst) + 0x00000034), 0x0000090C +#define BF_NLCA_BLOCK_SIZE_ADJ_INFO(inst) ((inst) + 0x00000034), 0x00000215 + +#define REG_NLCA_FILT_ADDR(inst, n) ((inst) + 0x00000038 + 4 * (n)) +#define BF_NLCA_FILT_COEF_LSB_INFO(inst, n) ((inst) + 0x00000038 + 4 * (n)), 0x00001000 +#define BF_NLCA_FILT_COEF_MSB_INFO(inst, n) ((inst) + 0x00000038 + 4 * (n)), 0x00001010 + +#define REG_NLCA_OUTPUT_Q_ADDR(inst, n) ((inst) + 0x00000138 + 4 * (n)) +#define BF_NLCA_OUTPUT_Q_INFO(inst, n) ((inst) + 0x00000138 + 4 * (n)), 0x00002000 + +#endif /* __ADI_APOLLO_BF_LINEARX_NLCA_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_linearx_rx_config.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_linearx_rx_config.h new file mode 100644 index 00000000000000..402905625c521c --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_linearx_rx_config.h @@ -0,0 +1,36 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:19 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_LINEARX_RX_CONFIG_H__ +#define __ADI_APOLLO_BF_LINEARX_RX_CONFIG_H__ + +/*============= D E F I N E S ==============*/ +#define LINEARX_RX_CONFIG_RX_LINEARX_REG32_0_RX_SLICE_0_RX_DIGITAL0 0x60220000 +#define LINEARX_RX_CONFIG_RX_LINEARX_REG32_1_RX_SLICE_0_RX_DIGITAL0 0x60228000 +#define LINEARX_RX_CONFIG_RX_LINEARX_REG32_0_RX_SLICE_1_RX_DIGITAL0 0x60420000 +#define LINEARX_RX_CONFIG_RX_LINEARX_REG32_1_RX_SLICE_1_RX_DIGITAL0 0x60428000 +#define LINEARX_RX_CONFIG_RX_LINEARX_REG32_0_RX_SLICE_0_RX_DIGITAL1 0x60A20000 +#define LINEARX_RX_CONFIG_RX_LINEARX_REG32_1_RX_SLICE_0_RX_DIGITAL1 0x60A28000 +#define LINEARX_RX_CONFIG_RX_LINEARX_REG32_0_RX_SLICE_1_RX_DIGITAL1 0x60C20000 +#define LINEARX_RX_CONFIG_RX_LINEARX_REG32_1_RX_SLICE_1_RX_DIGITAL1 0x60C28000 + +#define REG_LINEARX_RX_BYPASS_ADDR(inst) ((inst) + 0x00000000) +#define BF_LINEARX_RX_BYPASS_INFO(inst) ((inst) + 0x00000000), 0x00000100 + +#define REG_LINEARX_RX_CTRL_ADDR(inst) ((inst) + 0x00000004) +#define BF_LINEARX_RX_CLK_DIS_INFO(inst) ((inst) + 0x00000004), 0x00000100 +#define BF_LINEARX_RX_LATENCY_CONST_INFO(inst) ((inst) + 0x00000004), 0x00000202 + +#endif /* __ADI_APOLLO_BF_LINEARX_RX_CONFIG_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_linearx_rx_ddc.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_linearx_rx_ddc.h new file mode 100644 index 00000000000000..72c6e8179d4c5f --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_linearx_rx_ddc.h @@ -0,0 +1,70 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:19 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_LINEARX_RX_DDC_H__ +#define __ADI_APOLLO_BF_LINEARX_RX_DDC_H__ + +/*============= D E F I N E S ==============*/ +#define LINEARX_RX_DDC_REGMAP_RX_LINEARX_REG32_0_RX_SLICE_0_RX_DIGITAL0 0x60220F00 +#define LINEARX_RX_DDC_REGMAP_RX_LINEARX_REG32_1_RX_SLICE_0_RX_DIGITAL0 0x60228F00 +#define LINEARX_RX_DDC_REGMAP_RX_LINEARX_REG32_0_RX_SLICE_1_RX_DIGITAL0 0x60420F00 +#define LINEARX_RX_DDC_REGMAP_RX_LINEARX_REG32_1_RX_SLICE_1_RX_DIGITAL0 0x60428F00 +#define LINEARX_RX_DDC_REGMAP_RX_LINEARX_REG32_0_RX_SLICE_0_RX_DIGITAL1 0x60A20F00 +#define LINEARX_RX_DDC_REGMAP_RX_LINEARX_REG32_1_RX_SLICE_0_RX_DIGITAL1 0x60A28F00 +#define LINEARX_RX_DDC_REGMAP_RX_LINEARX_REG32_0_RX_SLICE_1_RX_DIGITAL1 0x60C20F00 +#define LINEARX_RX_DDC_REGMAP_RX_LINEARX_REG32_1_RX_SLICE_1_RX_DIGITAL1 0x60C28F00 + +#define REG_NCO_TUNE_LINEARX_RX_DDC_ADDR(inst) ((inst) + 0x00000000) +#define BF_NCO_FREQ_ADJ_LINEARX_RX_DDC_INFO(inst) ((inst) + 0x00000000), 0x00000F00 +#define BF_NCO_PHASE_ADJ_LINEARX_RX_DDC_INFO(inst) ((inst) + 0x00000000), 0x00000F10 + +#define REG_DDC_DATA_I_ADDR(inst) ((inst) + 0x00000010) +#define BF_CIC_OUT_IDATA_LINEARX_RX_DDC_INFO(inst) ((inst) + 0x00000010), 0x00001900 + +#define REG_DDC_DATA_Q_ADDR(inst) ((inst) + 0x00000014) +#define BF_CIC_OUT_QDATA_LINEARX_RX_DDC_INFO(inst) ((inst) + 0x00000014), 0x00001900 + +#define REG_DDC_MISC_CTRL_LINEARX_RX_DDC_ADDR(inst) ((inst) + 0x00000020) +#define BF_MIXER_DITH_EN_INFO(inst) ((inst) + 0x00000020), 0x00000100 +#define BF_NCO_ADITH_EN_LINEARX_RX_DDC_INFO(inst) ((inst) + 0x00000020), 0x00000101 +#define BF_NCO_PDITH_EN_LINEARX_RX_DDC_INFO(inst) ((inst) + 0x00000020), 0x00000102 +#define BF_MIXER_MODE_LINEARX_RX_DDC_INFO(inst) ((inst) + 0x00000020), 0x00000203 +#define BF_CIC_DEC_RATE_LINEARX_RX_DDC_INFO(inst) ((inst) + 0x00000020), 0x00000805 +#define BF_RESET_FSM_INFO(inst) ((inst) + 0x00000020), 0x0000010D +#define BF_CIC_FSM_STATE_I0_LINEARX_RX_DDC_INFO(inst) ((inst) + 0x00000020), 0x00000410 +#define BF_CIC_FSM_STATE_Q0_LINEARX_RX_DDC_INFO(inst) ((inst) + 0x00000020), 0x00000414 +#define BF_EXP_DEC_RATE_INFO(inst) ((inst) + 0x00000020), 0x00000318 + +#define REG_DDC_CTRL_REG_LINEARX_RX_DDC_ADDR(inst) ((inst) + 0x00000030) +#define BF_RESET_DDC_LINEARX_RX_DDC_INFO(inst) ((inst) + 0x00000030), 0x00000100 +#define BF_EN_CLK_DDC_LINEARX_RX_DDC_INFO(inst) ((inst) + 0x00000030), 0x00000101 +#define BF_NCO_RESET_LINEARX_RX_DDC_INFO(inst) ((inst) + 0x00000030), 0x00000102 +#define BF_NUM_CPT_AVG_INFO(inst) ((inst) + 0x00000030), 0x00000703 + +#define REG_DDC_NCO_EN_LINEARX_RX_DDC_ADDR(inst) ((inst) + 0x00000034) +#define BF_NCO_EN_DDC_LINEARX_RX_DDC_INFO(inst) ((inst) + 0x00000034), 0x00000100 + +#define REG_DDC_START_LINEARX_RX_DDC_ADDR(inst) ((inst) + 0x00000038) +#define BF_START_DDC_LINEARX_RX_DDC_INFO(inst) ((inst) + 0x00000038), 0x00000100 + +#define REG_DDC_IRQ_LINEARX_RX_DDC_ADDR(inst) ((inst) + 0x00000040) +#define BF_CIC_IRQ_RECVD_DDC_LINEARX_RX_DDC_INFO(inst) ((inst) + 0x00000040), 0x00000100 +#define BF_IRQ_STATUS_DDC_LINEARX_RX_DDC_INFO(inst) ((inst) + 0x00000040), 0x00000101 +#define BF_IRQ_DDC_EN_LINEARX_RX_DDC_INFO(inst) ((inst) + 0x00000040), 0x00000102 + +#define REG_DDC_BMEM_CTRL_ADDR(inst) ((inst) + 0x00000044) +#define BF_RX_DDC_BMEM_AWG_MODE_INFO(inst) ((inst) + 0x00000044), 0x00000100 + +#endif /* __ADI_APOLLO_BF_LINEARX_RX_DDC_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_linearx_tx_config.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_linearx_tx_config.h new file mode 100644 index 00000000000000..750302db94e537 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_linearx_tx_config.h @@ -0,0 +1,39 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:21 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_LINEARX_TX_CONFIG_H__ +#define __ADI_APOLLO_BF_LINEARX_TX_CONFIG_H__ + +/*============= D E F I N E S ==============*/ +#define LINEARX_TX_CONFIG_TX_LINEARX_REG32_0_TX_SLICE_0_TX_DIGITAL0 0x61220000 +#define LINEARX_TX_CONFIG_TX_LINEARX_REG32_1_TX_SLICE_0_TX_DIGITAL0 0x61228000 +#define LINEARX_TX_CONFIG_TX_LINEARX_REG32_0_TX_SLICE_1_TX_DIGITAL0 0x61420000 +#define LINEARX_TX_CONFIG_TX_LINEARX_REG32_1_TX_SLICE_1_TX_DIGITAL0 0x61428000 +#define LINEARX_TX_CONFIG_TX_LINEARX_REG32_0_TX_SLICE_0_TX_DIGITAL1 0x61A20000 +#define LINEARX_TX_CONFIG_TX_LINEARX_REG32_1_TX_SLICE_0_TX_DIGITAL1 0x61A28000 +#define LINEARX_TX_CONFIG_TX_LINEARX_REG32_0_TX_SLICE_1_TX_DIGITAL1 0x61C20000 +#define LINEARX_TX_CONFIG_TX_LINEARX_REG32_1_TX_SLICE_1_TX_DIGITAL1 0x61C28000 + +#define REG_LINEARX_TX_BYPASS_ADDR(inst) ((inst) + 0x00000000) +#define BF_LINEARX_TX_BYPASS_INFO(inst) ((inst) + 0x00000000), 0x00000100 + +#define REG_LINEARX_TX_CTRL_ADDR(inst) ((inst) + 0x00000004) +#define BF_LINEARX_TX_CLK_DIS_INFO(inst) ((inst) + 0x00000004), 0x00000100 +#define BF_LINEARX_TX_LATENCY_CONST_INFO(inst) ((inst) + 0x00000004), 0x00000202 + +#define REG_LINEARX_FROM_BMEM_ADDR(inst) ((inst) + 0x0000000C) +#define BF_LINEARX_FROM_BMEM_INFO(inst) ((inst) + 0x0000000C), 0x00000100 + +#endif /* __ADI_APOLLO_BF_LINEARX_TX_CONFIG_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_linearx_tx_ddc.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_linearx_tx_ddc.h new file mode 100644 index 00000000000000..0bffb36956c35b --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_linearx_tx_ddc.h @@ -0,0 +1,68 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:21 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_LINEARX_TX_DDC_H__ +#define __ADI_APOLLO_BF_LINEARX_TX_DDC_H__ + +/*============= D E F I N E S ==============*/ +#define LINEARX_TX_DDC_REGMAP_TX_LINEARX_REG32_0_TX_SLICE_0_TX_DIGITAL0 0x61220F00 +#define LINEARX_TX_DDC_REGMAP_TX_LINEARX_REG32_1_TX_SLICE_0_TX_DIGITAL0 0x61228F00 +#define LINEARX_TX_DDC_REGMAP_TX_LINEARX_REG32_0_TX_SLICE_1_TX_DIGITAL0 0x61420F00 +#define LINEARX_TX_DDC_REGMAP_TX_LINEARX_REG32_1_TX_SLICE_1_TX_DIGITAL0 0x61428F00 +#define LINEARX_TX_DDC_REGMAP_TX_LINEARX_REG32_0_TX_SLICE_0_TX_DIGITAL1 0x61A20F00 +#define LINEARX_TX_DDC_REGMAP_TX_LINEARX_REG32_1_TX_SLICE_0_TX_DIGITAL1 0x61A28F00 +#define LINEARX_TX_DDC_REGMAP_TX_LINEARX_REG32_0_TX_SLICE_1_TX_DIGITAL1 0x61C20F00 +#define LINEARX_TX_DDC_REGMAP_TX_LINEARX_REG32_1_TX_SLICE_1_TX_DIGITAL1 0x61C28F00 + +#define REG_NCO_TUNE_LINEARX_TX_DDC_ADDR(inst, n) ((inst) + 0x00000000 + 4 * (n)) +#define BF_NCO_FREQ_ADJ_LINEARX_TX_DDC_INFO(inst, n) ((inst) + 0x00000000 + 4 * (n)), 0x00000F00 +#define BF_NCO_PHASE_ADJ_LINEARX_TX_DDC_INFO(inst, n) ((inst) + 0x00000000 + 4 * (n)), 0x00000F10 + +#define REG_DDC_DATA_ADDR(inst, n) ((inst) + 0x00000010 + 4 * (n)) +#define BF_CIC_OUT_IDATA_LINEARX_TX_DDC_INFO(inst, n) ((inst) + 0x00000010 + 4 * (n)), 0x00001000 +#define BF_CIC_OUT_QDATA_LINEARX_TX_DDC_INFO(inst, n) ((inst) + 0x00000010 + 4 * (n)), 0x00001010 + +#define REG_DDC_MISC_CTRL_LINEARX_TX_DDC_ADDR(inst, n) ((inst) + 0x00000020 + 4 * (n)) +#define BF_NCO_ADITH_EN_LINEARX_TX_DDC_INFO(inst, n) ((inst) + 0x00000020 + 4 * (n)), 0x00000101 +#define BF_NCO_PDITH_EN_LINEARX_TX_DDC_INFO(inst, n) ((inst) + 0x00000020 + 4 * (n)), 0x00000102 +#define BF_MIXER_MODE_LINEARX_TX_DDC_INFO(inst, n) ((inst) + 0x00000020 + 4 * (n)), 0x00000203 +#define BF_CIC_DEC_RATE_LINEARX_TX_DDC_INFO(inst, n) ((inst) + 0x00000020 + 4 * (n)), 0x00000B05 +#define BF_CIC_FSM_STATE_I0_LINEARX_TX_DDC_INFO(inst, n) ((inst) + 0x00000020 + 4 * (n)), 0x00000410 +#define BF_CIC_FSM_STATE_Q0_LINEARX_TX_DDC_INFO(inst, n) ((inst) + 0x00000020 + 4 * (n)), 0x00000414 + +#define REG_DDC_CTRL_REG_LINEARX_TX_DDC_ADDR(inst) ((inst) + 0x00000030) +#define BF_RESET_DDC_LINEARX_TX_DDC_INFO(inst) ((inst) + 0x00000030), 0x00000200 +#define BF_EN_CLK_DDC_LINEARX_TX_DDC_INFO(inst) ((inst) + 0x00000030), 0x00000202 +#define BF_DDC_INPUT_DATA_SEL_INFO(inst) ((inst) + 0x00000030), 0x00000104 +#define BF_NCO_RESET_LINEARX_TX_DDC_INFO(inst) ((inst) + 0x00000030), 0x00000205 + +#define REG_DDC_NCO_EN_LINEARX_TX_DDC_ADDR(inst) ((inst) + 0x00000034) +#define BF_NCO_EN_DDC_LINEARX_TX_DDC_INFO(inst) ((inst) + 0x00000034), 0x00000200 + +#define REG_DDC_START_LINEARX_TX_DDC_ADDR(inst) ((inst) + 0x00000038) +#define BF_START_DDC_LINEARX_TX_DDC_INFO(inst) ((inst) + 0x00000038), 0x00000200 + +#define REG_NCO_BMEM_CTRL_ADDR(inst) ((inst) + 0x0000003C) +#define BF_TX_NCO_BMEM_EN_INFO(inst) ((inst) + 0x0000003C), 0x00000100 +#define BF_TX_NCO_BMEM_DITH_EN_INFO(inst) ((inst) + 0x0000003C), 0x00000101 +#define BF_TX_NCO_BMEM_SCALE_INFO(inst) ((inst) + 0x0000003C), 0x00000202 +#define BF_TX_NCO_BMEM_8T8R_MASK_INFO(inst) ((inst) + 0x0000003C), 0x00000204 + +#define REG_DDC_IRQ_LINEARX_TX_DDC_ADDR(inst) ((inst) + 0x00000040) +#define BF_CIC_IRQ_RECVD_DDC_LINEARX_TX_DDC_INFO(inst) ((inst) + 0x00000040), 0x00000200 +#define BF_IRQ_STATUS_DDC_LINEARX_TX_DDC_INFO(inst) ((inst) + 0x00000040), 0x00000202 +#define BF_IRQ_DDC_EN_LINEARX_TX_DDC_INFO(inst) ((inst) + 0x00000040), 0x00000204 + +#endif /* __ADI_APOLLO_BF_LINEARX_TX_DDC_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_mailbox.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_mailbox.h new file mode 100644 index 00000000000000..b359069d8e93b2 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_mailbox.h @@ -0,0 +1,48 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:17 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_MAILBOX_H__ +#define __ADI_APOLLO_BF_MAILBOX_H__ + +/*============= D E F I N E S ==============*/ +#define CORE_0_SPI0_CMD_MAILBOX 0x41500000 +#define CORE_0_SPI1_CMD_MAILBOX 0x41600000 + +#ifdef USE_PRIVATE_BF +#define REG_ARM_CMD_1_MAILBOX_ADDR(inst) ((inst) + 0x00000000) +#define BF_ARM_COMMAND_OPCODE_INFO(inst) ((inst) + 0x00000000), 0x00000600 +#define BF_ARM_COMMAND_BUSY_MAILBOX_INFO(inst) ((inst) + 0x00000000), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#define REG_ARM_CMD_2_MAILBOX_ADDR(inst) ((inst) + 0x00000004) +#define BF_ARM_COMMAND_PAYLOAD_BYTES_INFO(inst) ((inst) + 0x00000004), 0x00002000 + +#define REG_ARM_STATUS_1_MAILBOX_ADDR(inst) ((inst) + 0x00000008) +#define BF_ARM_STATUS_1_INFO(inst) ((inst) + 0x00000008), 0x00002000 + +#define REG_ARM_STATUS_2_MAILBOX_ADDR(inst) ((inst) + 0x0000000C) +#define BF_ARM_STATUS_2_INFO(inst) ((inst) + 0x0000000C), 0x00001E00 +#define BF_STREAM_PROC_ARM_STATUS_MAILBOX_INFO(inst) ((inst) + 0x0000000C), 0x0000021E + +#define REG_ARM_STATUS_3_MAILBOX_ADDR(inst) ((inst) + 0x00000010) +#define BF_ARM_STATUS_3_INFO(inst) ((inst) + 0x00000010), 0x00002000 + +#define REG_ARM_STATUS_4_MAILBOX_ADDR(inst) ((inst) + 0x00000014) +#define BF_ARM_STATUS_4_INFO(inst) ((inst) + 0x00000014), 0x00002000 + +#define REG_ARM_GPIO_VAL_MAILBOX_ADDR(inst) ((inst) + 0x00000018) +#define BF_GPIO_VAL_INFO(inst) ((inst) + 0x00000018), 0x00001000 + +#endif /* __ADI_APOLLO_BF_MAILBOX_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_master_bias_ctrl.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_master_bias_ctrl.h new file mode 100644 index 00000000000000..9b5146d9d7380c --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_master_bias_ctrl.h @@ -0,0 +1,704 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:20 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_MASTER_BIAS_CTRL_H__ +#define __ADI_APOLLO_BF_MASTER_BIAS_CTRL_H__ + +/*============= D E F I N E S ==============*/ +#define MBIAS0 0x4C001800 +#define MBIAS1 0x4C001C00 + +#define REG_MBIAS_IGEN_PWRDWN_ADDR(inst) ((inst) + 0x00000100) +#define BF_MBIAS_IGEN_PD_INFO(inst) ((inst) + 0x00000100), 0x00000100 +#define BF_MBIAS_TRIM_COMP_PD_INFO(inst) ((inst) + 0x00000100), 0x00000101 +#define BF_MBIAS_TRIM_COMP_PD_RD_INFO(inst) ((inst) + 0x00000100), 0x00000104 + +#define REG_MBIAS_BG_CTAT_TRIM_ADDR(inst) ((inst) + 0x00000101) +#define BF_MBIAS_BG_CTAT_INFO(inst) ((inst) + 0x00000101), 0x00000400 +#define BF_MBIAS_BG_CTAT_D_INFO(inst) ((inst) + 0x00000101), 0x00000104 +#define BF_MBIAS_BG_CURVE_D_IN_INFO(inst) ((inst) + 0x00000101), 0x00000105 + +#define REG_MBIAS_TRIM_AUTO_ADDR(inst) ((inst) + 0x00000102) +#define BF_MBIAS_TRIM_AUTO_INFO(inst) ((inst) + 0x00000102), 0x00000100 + +#define REG_MBIAS_BG_PTAT_TRIM_ADDR(inst) ((inst) + 0x00000103) +#define BF_MBIAS_BG_PTAT_INFO(inst) ((inst) + 0x00000103), 0x00000600 + +#define REG_MBIAS_BG_LEVEL_TRIM_ADDR(inst) ((inst) + 0x00000104) +#define BF_MBIAS_BG_LEVEL_INFO(inst) ((inst) + 0x00000104), 0x00000800 + +#define REG_MBIAS_IGEN_TRIM_CODE_ADDR(inst) ((inst) + 0x00000105) +#define BF_MBIAS_IGEN_PTATR_INFO(inst) ((inst) + 0x00000105), 0x00000600 + +#define REG_MBIAS_DEGEN_TRIM_CODE_ADDR(inst) ((inst) + 0x00000106) +#define BF_MBIAS_DEGEN_TRIM_CODE_INFO(inst) ((inst) + 0x00000106), 0x00000300 + +#define REG_MBIAS_IGEN_RTRIM_ADDR(inst) ((inst) + 0x00000107) +#define BF_MBIAS_RTRIM_TRIGGER_MANUAL_INFO(inst) ((inst) + 0x00000107), 0x00000100 +#define BF_MBIAS_RTRIM_BYP_TRIGGERDEL_INFO(inst) ((inst) + 0x00000107), 0x00000101 +#define BF_MBIAS_RTRIM_CODE_SELECT_INFO(inst) ((inst) + 0x00000107), 0x00000102 +#define BF_MBIAS_DEGEN_TRIM_CODE_SELECT_INFO(inst) ((inst) + 0x00000107), 0x00000103 +#define BF_MBIAS_RTRIM_RESETB_INFO(inst) ((inst) + 0x00000107), 0x00000104 +#define BF_MBIAS_TRIM_REPEAT_INFO(inst) ((inst) + 0x00000107), 0x00000105 +#define BF_MBIAS_RTRIM_CHOP_CNTL_INFO(inst) ((inst) + 0x00000107), 0x00000206 + +#ifdef USE_PRIVATE_BF +#define REG_MBIAS_IGEN_RTRIM_RB_ADDR(inst) ((inst) + 0x00000108) +#define BF_MBIAS_IGEN_PTATR_CODE_RB_INFO(inst) ((inst) + 0x00000108), 0x00000600 +#define BF_MBIAS_IGEN_PTATR_TRIM_DONE_INFO(inst) ((inst) + 0x00000108), 0x00000106 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_MBIAS_DEGEN_TRIM_RB_ADDR(inst) ((inst) + 0x00000109) +#define BF_MBIAS_DEGEN_TRIM_CODE_RB_INFO(inst) ((inst) + 0x00000109), 0x00000300 +#endif /* USE_PRIVATE_BF */ + +#define REG_MBIAS_IGEN_MISC_ADDR(inst) ((inst) + 0x0000010A) +#define BF_MBIAS_AMUX_SEL_INFO(inst) ((inst) + 0x0000010A), 0x00000400 + +#define REG_MBIAS_IGEN_MISC2_ADDR(inst) ((inst) + 0x0000010B) +#define BF_MBIAS_SPARE_INFO(inst) ((inst) + 0x0000010B), 0x00000800 + +#define REG_MBIAS_EN_CTRL_ADDR(inst) ((inst) + 0x0000010C) +#define BF_MBIAS_DFT_EN_INFO(inst) ((inst) + 0x0000010C), 0x00000100 +#define BF_MBIAS_BANDGAP_VREF_EN_INFO(inst) ((inst) + 0x0000010C), 0x00000104 + +#define REG_MBIAS_BYPASS_RES_CTRL_ADDR(inst) ((inst) + 0x0000010D) +#define BF_MBIAS_BYPASS_BIAS_RES_INFO(inst) ((inst) + 0x0000010D), 0x00000100 +#define BF_MBIAS_BYPASS_ICON_RES_INFO(inst) ((inst) + 0x0000010D), 0x00000204 + +#define REG_MBIAS_CALCLK_CTRL_ADDR(inst) ((inst) + 0x0000010E) +#define BF_MBIAS_CALCLK_EN_INFO(inst) ((inst) + 0x0000010E), 0x00000100 +#define BF_MBIAS_CALCLK_SEL_INFO(inst) ((inst) + 0x0000010E), 0x00000101 +#define BF_MBIAS_CALCLK_DIV_INFO(inst) ((inst) + 0x0000010E), 0x00000204 + +#define REG_TUNER_CALCLK_CTRL_ADDR(inst) ((inst) + 0x0000010F) +#define BF_TUNER_CALCLK_EN_INFO(inst) ((inst) + 0x0000010F), 0x00000100 +#define BF_TUNER_CALCLK_DIV_INFO(inst) ((inst) + 0x0000010F), 0x00000204 + +#define REG_TUNER_RESET_ADDR(inst) ((inst) + 0x00000110) +#define BF_TUNER_RESET_INFO(inst) ((inst) + 0x00000110), 0x00000100 + +#define REG_ADC_CLK_DIV_CTRL_ADDR(inst) ((inst) + 0x00000122) +#define BF_ADC_CLK_PATH_EN_INFO(inst) ((inst) + 0x00000122), 0x00000100 +#define BF_ADC_DIVBY2_INFO(inst) ((inst) + 0x00000122), 0x00000104 + +#define REG_DAC_CLK_DIV_CTRL_ADDR(inst) ((inst) + 0x00000123) +#define BF_DAC_CLK_PATH_EN_INFO(inst) ((inst) + 0x00000123), 0x00000100 +#define BF_DAC_DIVBY2_INFO(inst) ((inst) + 0x00000123), 0x00000104 + +#define REG_ADC_CLK_INV_ADDR(inst) ((inst) + 0x00000124) +#define BF_ADC_INCLK_INVERT0_INFO(inst) ((inst) + 0x00000124), 0x00000100 +#define BF_ADC_INCLK_INVERT1_INFO(inst) ((inst) + 0x00000124), 0x00000104 + +#define REG_DBG_CLK_CTRL_ADDR(inst) ((inst) + 0x00000125) +#define BF_DEBUG_CLK_EN_INFO(inst) ((inst) + 0x00000125), 0x00000100 +#define BF_DEBUG_CLK_SEL_INFO(inst) ((inst) + 0x00000125), 0x00000204 + +#define REG_ADC_DBG_CTRL_ADDR(inst) ((inst) + 0x00000126) +#define BF_ADC_DEBUG_EN_INFO(inst) ((inst) + 0x00000126), 0x00000100 +#define BF_ADC_DEBUG_SEL0_INFO(inst) ((inst) + 0x00000126), 0x00000204 +#define BF_ADC_DEBUG_SEL1_INFO(inst) ((inst) + 0x00000126), 0x00000206 + +#define REG_DAC_DBG_CTRL_ADDR(inst) ((inst) + 0x00000127) +#define BF_DAC_DEBUG_EN_INFO(inst) ((inst) + 0x00000127), 0x00000100 +#define BF_DAC_DEBUG_SEL0_INFO(inst) ((inst) + 0x00000127), 0x00000204 +#define BF_DAC_DEBUG_SEL1_INFO(inst) ((inst) + 0x00000127), 0x00000206 + +#define REG_CK_EN_CTRL_ADDR(inst) ((inst) + 0x00000128) +#define BF_EN_CK_TO_ADC_INFO(inst) ((inst) + 0x00000128), 0x00000100 +#define BF_EN_CK_TO_DAC_INFO(inst) ((inst) + 0x00000128), 0x00000101 +#define BF_EN_CK_TO_MCS_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x00000128), 0x00000104 + +#define REG_CK_DEBUG_CTRL_ADDR(inst) ((inst) + 0x00000129) +#define BF_ADC_LATENCY_DEBUG_EN_INFO(inst) ((inst) + 0x00000129), 0x00000100 +#define BF_ADC_SYNC_DEBUG_EN_INFO(inst) ((inst) + 0x00000129), 0x00000101 +#define BF_DAC_LATENCY_DEBUG_EN_INFO(inst) ((inst) + 0x00000129), 0x00000104 +#define BF_DAC_SYNC_DEBUG_EN_INFO(inst) ((inst) + 0x00000129), 0x00000105 + +#define REG_MPU_SEL_ADDR(inst) ((inst) + 0x0000012A) +#define BF_MPU_SELECT_B_INFO(inst) ((inst) + 0x0000012A), 0x00000800 + +#define REG_MPU_CTRL_ADDR(inst) ((inst) + 0x0000012B) +#define BF_MPU_EN_B_INFO(inst) ((inst) + 0x0000012B), 0x00000100 +#define BF_MPU_BUS_PRECHARGE_B_INFO(inst) ((inst) + 0x0000012B), 0x00000404 + +#define REG_MPU_SPARE_ADDR(inst) ((inst) + 0x0000012C) +#define BF_MPU_SPARE_INFO(inst) ((inst) + 0x0000012C), 0x00000800 + +#define REG_TEMPS_MAIN_00_MASTER_BIAS_CTRL_ADDR(inst) ((inst) + 0x00000130) +#define BF_TEMPS_RESET_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x00000130), 0x00000100 +#define BF_TEMPS_START_MEASUREMENT_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x00000130), 0x00000101 +#define BF_TEMPS_MEASUREMENT_READY_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x00000130), 0x00000104 + +#define REG_TEMPS_MAIN_01_MASTER_BIAS_CTRL_ADDR(inst) ((inst) + 0x00000131) + +#define REG_TEMPS_MAIN_02_MASTER_BIAS_CTRL_ADDR(inst) ((inst) + 0x00000132) +#define BF_TEMPS_TEMPERATURE_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x00000132), 0x00000C00 + +#define REG_TEMPS_MAIN_03_MASTER_BIAS_CTRL_ADDR(inst) ((inst) + 0x00000133) +#define BF_TEMPS_OFFSET_ADJ_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x00000133), 0x00000700 + +#define REG_TEMPS_MAIN_04_MASTER_BIAS_CTRL_ADDR(inst) ((inst) + 0x00000134) +#define BF_TEMPS_SLOPE_ADJ_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x00000134), 0x00000800 + +#ifdef USE_PRIVATE_BF +#define REG_TEMPS_PD_RESET_MASTER_BIAS_CTRL_ADDR(inst) ((inst) + 0x00000135) +#define BF_TEMPS_CLK_PD_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x00000135), 0x00000100 +#define BF_TEMPS_STARTUP_PD_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x00000135), 0x00000101 +#define BF_TEMPS_PTAT_PD_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x00000135), 0x00000102 +#define BF_TEMPS_REF_PD_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x00000135), 0x00000103 +#define BF_TEMPS_ADC_PD_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x00000135), 0x00000104 +#define BF_TEMPS_RESET_ADC_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x00000135), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TEMPS_BIAS_PTAT_MASTER_BIAS_CTRL_ADDR(inst) ((inst) + 0x00000136) +#define BF_TEMPS_CURR_PTAT_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x00000136), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TEMPS_BIAS_REF_MASTER_BIAS_CTRL_ADDR(inst) ((inst) + 0x00000137) +#define BF_TEMPS_CURR_REF_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x00000137), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TEMPS_BIAS_IAMP_MASTER_BIAS_CTRL_ADDR(inst) ((inst) + 0x00000138) +#define BF_TEMPS_CURR_IAMP1_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x00000138), 0x00000400 +#define BF_TEMPS_CURR_IAMP2_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x00000138), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TEMPS_BIAS_VCM_MASTER_BIAS_CTRL_ADDR(inst) ((inst) + 0x00000139) +#define BF_TEMPS_CURR_VCM_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x00000139), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TEMPS_BIAS_COMP_MASTER_BIAS_CTRL_ADDR(inst) ((inst) + 0x0000013A) +#define BF_TEMPS_CURR_FLASHO_N_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x0000013A), 0x00000400 +#define BF_TEMPS_CURR_FLASHO_P_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x0000013A), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TEMPS_MUX_IN_MASTER_BIAS_CTRL_ADDR(inst) ((inst) + 0x0000013B) +#define BF_TEMPS_SEL_MUX_VP_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x0000013B), 0x00000300 +#define BF_TEMPS_SEL_MUX_VM_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x0000013B), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TEMPS_MUX_BG_CLK_MASTER_BIAS_CTRL_ADDR(inst) ((inst) + 0x0000013C) +#define BF_TEMPS_SEL_MUX_BG_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x0000013C), 0x00000300 +#define BF_TEMPS_CLK_MUX_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x0000013C), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TEMPS_TEST_CTRL_MASTER_BIAS_CTRL_ADDR(inst) ((inst) + 0x0000013D) +#define BF_TEMPS_TEST_MODE_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x0000013D), 0x00000200 +#define BF_TEMPS_WAIT_TO_MEASURE_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x0000013D), 0x00000302 +#define BF_TEMPS_WAKE_SETTING_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x0000013D), 0x00000305 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TEMPS_TEST_STATE_STEP_MASTER_BIAS_CTRL_ADDR(inst) ((inst) + 0x0000013E) +#define BF_TEMPS_TEST_STATE_ADVANCE_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x0000013E), 0x00000100 +#define BF_TEMPS_TEST_STATE_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x0000013E), 0x00000101 +#define BF_TEMPS_MEASURE_CONTROL_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x0000013E), 0x00000204 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TEMPS_MUX_OBS_CTRL_MASTER_BIAS_CTRL_ADDR(inst) ((inst) + 0x0000013F) +#define BF_TEMPS_MUX_OBS_CTRL_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x0000013F), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TEMPS_MUX_OBS_MASTER_BIAS_CTRL_ADDR(inst) ((inst) + 0x00000140) +#define BF_TEMPS_MUX_OBS_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x00000140), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_TEMPS_TEST_SPARE_00_MASTER_BIAS_CTRL_ADDR(inst) ((inst) + 0x00000141) + +#ifdef USE_PRIVATE_BF +#define REG_TEMPS_TEST_SPARE_01_MASTER_BIAS_CTRL_ADDR(inst) ((inst) + 0x00000142) +#define BF_TEMPS_CTRL_MASTER_BIAS_CTRL_INFO(inst) ((inst) + 0x00000142), 0x00001000 +#endif /* USE_PRIVATE_BF */ + +#define REG_TEMPS_ADC_AWAKE_ADDR(inst) ((inst) + 0x00000143) +#define BF_TEMPS_ADC_AWAKE_INFO(inst) ((inst) + 0x00000143), 0x00000100 + +#define REG_MB_DAC_GAIN0_LSB_ADDR(inst) ((inst) + 0x00000150) +#define BF_MBIAS_DAC_GAIN0_INFO(inst) ((inst) + 0x00000150), 0x00000A00 + +#define REG_MB_DAC_GAIN0_MSB_ADDR(inst) ((inst) + 0x00000151) + +#define REG_MB_DAC_GAIN1_LSB_ADDR(inst) ((inst) + 0x00000152) +#define BF_MBIAS_DAC_GAIN1_INFO(inst) ((inst) + 0x00000152), 0x00000A00 + +#define REG_MB_DAC_GAIN1_MSB_ADDR(inst) ((inst) + 0x00000153) + +#define REG_MB_DAC_GAIN2_LSB_ADDR(inst) ((inst) + 0x00000154) +#define BF_MBIAS_DAC_GAIN2_INFO(inst) ((inst) + 0x00000154), 0x00000A00 + +#define REG_MB_DAC_GAIN2_MSB_ADDR(inst) ((inst) + 0x00000155) + +#define REG_MB_DAC_GAIN3_LSB_ADDR(inst) ((inst) + 0x00000156) +#define BF_MBIAS_DAC_GAIN3_INFO(inst) ((inst) + 0x00000156), 0x00000A00 + +#define REG_MB_DAC_GAIN3_MSB_ADDR(inst) ((inst) + 0x00000157) + +#define REG_MB_DAC_BLD_GAIN0_LSB_ADDR(inst) ((inst) + 0x00000158) +#define BF_MBIAS_DAC_BLD_GAIN0_INFO(inst) ((inst) + 0x00000158), 0x00000A00 + +#define REG_MB_DAC_BLD_GAIN0_MSB_ADDR(inst) ((inst) + 0x00000159) + +#define REG_MB_DAC_BLD_GAIN1_LSB_ADDR(inst) ((inst) + 0x0000015A) +#define BF_MBIAS_DAC_BLD_GAIN1_INFO(inst) ((inst) + 0x0000015A), 0x00000A00 + +#define REG_MB_DAC_BLD_GAIN1_MSB_ADDR(inst) ((inst) + 0x0000015B) + +#define REG_MB_DAC_BLD_GAIN2_LSB_ADDR(inst) ((inst) + 0x0000015C) +#define BF_MBIAS_DAC_BLD_GAIN2_INFO(inst) ((inst) + 0x0000015C), 0x00000A00 + +#define REG_MB_DAC_BLD_GAIN2_MSB_ADDR(inst) ((inst) + 0x0000015D) + +#define REG_MB_DAC_BLD_GAIN3_LSB_ADDR(inst) ((inst) + 0x0000015E) +#define BF_MBIAS_DAC_BLD_GAIN3_INFO(inst) ((inst) + 0x0000015E), 0x00000A00 + +#define REG_MB_DAC_BLD_GAIN3_MSB_ADDR(inst) ((inst) + 0x0000015F) + +#define REG_DIV_DLYPATH_ADDR(inst) ((inst) + 0x00000160) +#define BF_DIV_EN_DELAY_INFO(inst) ((inst) + 0x00000160), 0x00000100 +#define BF_DIV_PD_TESTPATH_INFO(inst) ((inst) + 0x00000160), 0x00000104 + +#define REG_ADC_DIV_DLYPATH_ADDR(inst) ((inst) + 0x00000161) +#define BF_ADC_DIV_EN_DELAY_INFO(inst) ((inst) + 0x00000161), 0x00000100 +#define BF_ADC_DIV_PD_TESTPATH_INFO(inst) ((inst) + 0x00000161), 0x00000104 + +#define REG_TRIG_CTRL_MASTER_BIAS_CTRL_ADDR(inst) ((inst) + 0x00000162) +#define BF_TRIGGER_ENABLE_INFO(inst) ((inst) + 0x00000162), 0x00000200 +#define BF_TRIGGER_SCHMITT_ENABLE_INFO(inst) ((inst) + 0x00000162), 0x00000104 + +#define REG_PD_DACDIV_CTRL_ADDR(inst) ((inst) + 0x00000163) +#define BF_PD_DAC_DIV_TO_DAC01_INFO(inst) ((inst) + 0x00000163), 0x00000100 +#define BF_PD_DAC_DIV_TO_DAC23_INFO(inst) ((inst) + 0x00000163), 0x00000101 +#define BF_PD_DAC_CORNER_TO_DIV_INFO(inst) ((inst) + 0x00000163), 0x00000104 + +#define REG_CC_CLK_CORN_ADDR(inst) ((inst) + 0x00000165) +#define BF_CC_CLK_CORN_INFO(inst) ((inst) + 0x00000165), 0x00000100 +#define BF_CC_COMP_CORN_INFO(inst) ((inst) + 0x00000165), 0x00000104 + +#define REG_CC_CORN_CFG0_ADDR(inst) ((inst) + 0x00000166) +#define BF_CC_CONFIG_CORN_INFO(inst) ((inst) + 0x00000166), 0x00001000 + +#define REG_CC_CORN_CFG1_ADDR(inst) ((inst) + 0x00000167) + +#define REG_CC_CLK_S_ADDR(inst) ((inst) + 0x00000168) +#define BF_CC_CLK_S_INFO(inst) ((inst) + 0x00000168), 0x00000100 +#define BF_CC_COMP_S_INFO(inst) ((inst) + 0x00000168), 0x00000104 + +#define REG_CC_S_CFG0_ADDR(inst) ((inst) + 0x00000169) +#define BF_CC_CONFIG_S_INFO(inst) ((inst) + 0x00000169), 0x00001000 + +#define REG_CC_S_CFG1_ADDR(inst) ((inst) + 0x0000016A) + +#define REG_CC_CLK_01_ADDR(inst) ((inst) + 0x0000016B) +#define BF_CC_CLK_01_INFO(inst) ((inst) + 0x0000016B), 0x00000100 +#define BF_CC_COMP_01_INFO(inst) ((inst) + 0x0000016B), 0x00000104 + +#define REG_CC_01_CFG0_ADDR(inst) ((inst) + 0x0000016C) +#define BF_CC_CONFIG_01_INFO(inst) ((inst) + 0x0000016C), 0x00001000 + +#define REG_CC_01_CFG1_ADDR(inst) ((inst) + 0x0000016D) + +#define REG_CC_CLK_23_ADDR(inst) ((inst) + 0x0000016E) +#define BF_CC_CLK_23_INFO(inst) ((inst) + 0x0000016E), 0x00000100 +#define BF_CC_COMP_23_INFO(inst) ((inst) + 0x0000016E), 0x00000104 + +#define REG_CC_23_CFG0_ADDR(inst) ((inst) + 0x0000016F) +#define BF_CC_CONFIG_23_INFO(inst) ((inst) + 0x0000016F), 0x00001000 + +#define REG_CC_23_CFG1_ADDR(inst) ((inst) + 0x00000170) + +#define REG_CC_CLK_ADC_ADDR(inst) ((inst) + 0x00000171) +#define BF_CC_CLK_ADC_INFO(inst) ((inst) + 0x00000171), 0x00000100 +#define BF_CC_COMP_ADC_INFO(inst) ((inst) + 0x00000171), 0x00000104 +#define BF_CC_COMP_ADC1_INFO(inst) ((inst) + 0x00000171), 0x00000105 + +#define REG_CC_ADC_CFG0_ADDR(inst) ((inst) + 0x00000172) +#define BF_CC_CONFIG_ADC_INFO(inst) ((inst) + 0x00000172), 0x00001000 + +#define REG_CC_ADC_CFG1_ADDR(inst) ((inst) + 0x00000173) + +#define REG_ADC_LPU_CTRL_ADDR(inst) ((inst) + 0x00000174) +#define BF_DIG_VENUSLPU_CHOP_INFO(inst) ((inst) + 0x00000174), 0x00000100 +#define BF_DIG_VENUSLPU_BUFBYPASS_INFO(inst) ((inst) + 0x00000174), 0x00000101 +#define BF_DIG_VENUSLPU_SEL_INFO(inst) ((inst) + 0x00000174), 0x00000404 + +#define REG_ADC_INV_CTRL0_ADDR(inst) ((inst) + 0x00000175) +#define BF_EN_ADC_INV0_INFO(inst) ((inst) + 0x00000175), 0x00000100 +#define BF_EN_ADC_INV0_XC_INFO(inst) ((inst) + 0x00000175), 0x00000204 + +#define REG_ADC_INV_CTRL1_ADDR(inst) ((inst) + 0x00000176) +#define BF_EN_ADC_INV1_INFO(inst) ((inst) + 0x00000176), 0x00000100 +#define BF_EN_ADC_INV1_XC_INFO(inst) ((inst) + 0x00000176), 0x00000204 + +#define REG_EN_CK_CC_AMUX_CTRL_ADDR(inst) ((inst) + 0x00000177) +#define BF_EN_CK_CC_AMUX_CORNER_INFO(inst) ((inst) + 0x00000177), 0x00000100 +#define BF_EN_CK_CC_AMUX_ADC0_INFO(inst) ((inst) + 0x00000177), 0x00000101 +#define BF_EN_CK_CC_AMUX_ADC1_INFO(inst) ((inst) + 0x00000177), 0x00000102 +#define BF_EN_CK_CC_AMUX_DAC_INFO(inst) ((inst) + 0x00000177), 0x00000104 +#define BF_EN_CK_CC_AMUX_DAC01_INFO(inst) ((inst) + 0x00000177), 0x00000105 +#define BF_EN_CK_CC_AMUX_DAC23_INFO(inst) ((inst) + 0x00000177), 0x00000106 + +#define REG_DAC_CK_PATH_EN_CTRL_ADDR(inst) ((inst) + 0x00000178) +#define BF_DAC_CLK_PATH_EN01_INFO(inst) ((inst) + 0x00000178), 0x00000100 +#define BF_DAC_CLK_PATH_EN23_INFO(inst) ((inst) + 0x00000178), 0x00000101 + +#define REG_DIG_DAC01_TMU_ADDR(inst) ((inst) + 0x00000179) +#define BF_DIG_DAC01_TMU_LPU_BUFBYPASS_INFO(inst) ((inst) + 0x00000179), 0x00000100 +#define BF_DIG_DAC01_TMU_LPU_CHOP_INFO(inst) ((inst) + 0x00000179), 0x00000101 +#define BF_DIG_DAC01_TMU_LPU_SEL_INFO(inst) ((inst) + 0x00000179), 0x00000404 + +#define REG_DIG_DAC23_TMU_ADDR(inst) ((inst) + 0x0000017A) +#define BF_DIG_DAC23_TMU_LPU_BUFBYPASS_INFO(inst) ((inst) + 0x0000017A), 0x00000100 +#define BF_DIG_DAC23_TMU_LPU_CHOP_INFO(inst) ((inst) + 0x0000017A), 0x00000101 +#define BF_DIG_DAC23_TMU_LPU_SEL_INFO(inst) ((inst) + 0x0000017A), 0x00000404 + +#define REG_CC_SKEW_DET0_ADDR(inst) ((inst) + 0x0000017B) +#define BF_CC_ADC_DET_DUTY_SET_ADC0_INFO(inst) ((inst) + 0x0000017B), 0x00000300 +#define BF_CC_ADC_DET_DUTY_SET_ADC1_INFO(inst) ((inst) + 0x0000017B), 0x00000304 + +#define REG_CC_SKEW_DET1_ADDR(inst) ((inst) + 0x0000017C) +#define BF_CC_SKEW_DET_TRIM_DAC01_INFO(inst) ((inst) + 0x0000017C), 0x00000400 +#define BF_CC_SKEW_DET_TRIM_DAC23_INFO(inst) ((inst) + 0x0000017C), 0x00000404 + +#define REG_CC_SKEW_DET2_ADDR(inst) ((inst) + 0x0000017D) +#define BF_CC_SKEW_DET_TRIM_CORNER_INFO(inst) ((inst) + 0x0000017D), 0x00000400 +#define BF_CC_SKEW_DET_TRIM_DACC2S_INFO(inst) ((inst) + 0x0000017D), 0x00000404 + +#define REG_CC_SKEW_DET3_ADDR(inst) ((inst) + 0x0000017E) +#define BF_CC_SKEW_DET_TRIM_ADC_INFO(inst) ((inst) + 0x0000017E), 0x00000400 + +#define REG_C2B_TL2_CKP_R_PUP_ADDR(inst) ((inst) + 0x00000180) +#define BF_C2B_TL2_CLKP_R_PUP_INFO(inst) ((inst) + 0x00000180), 0x00000500 + +#define REG_C2B_TL2_CKP_R_PDN_ADDR(inst) ((inst) + 0x00000181) +#define BF_C2B_TL2_CLKP_R_PDN_INFO(inst) ((inst) + 0x00000181), 0x00000500 + +#define REG_C2B_TL2_CKN_R_PUP_ADDR(inst) ((inst) + 0x00000182) +#define BF_C2B_TL2_CLKN_R_PUP_INFO(inst) ((inst) + 0x00000182), 0x00000500 + +#define REG_C2B_TL2_CKN_R_PDN_ADDR(inst) ((inst) + 0x00000183) +#define BF_C2B_TL2_CLKN_R_PDN_INFO(inst) ((inst) + 0x00000183), 0x00000500 + +#define REG_C2B_TL2_CKP_C_ADDR(inst) ((inst) + 0x00000184) +#define BF_C2B_TL2_CLKP_C_INFO(inst) ((inst) + 0x00000184), 0x00000500 + +#define REG_C2B_TL2_CKN_C_ADDR(inst) ((inst) + 0x00000185) +#define BF_C2B_TL2_CLKN_C_INFO(inst) ((inst) + 0x00000185), 0x00000500 + +#define REG_C2B_TL2_SYNC_RC_ADDR(inst) ((inst) + 0x00000186) +#define BF_C2B_TL2_SYNC_R_INFO(inst) ((inst) + 0x00000186), 0x00000200 +#define BF_C2B_TL2_SYNC_C_INFO(inst) ((inst) + 0x00000186), 0x00000204 + +#define REG_C2B_TL2_CK_RTERM_ADDR(inst) ((inst) + 0x00000187) +#define BF_C2B_TL2_CLKP_RTERM_PUP_INFO(inst) ((inst) + 0x00000187), 0x00000200 +#define BF_C2B_TL2_CLKP_RTERM_PDN_INFO(inst) ((inst) + 0x00000187), 0x00000202 +#define BF_C2B_TL2_CLKN_RTERM_PUP_INFO(inst) ((inst) + 0x00000187), 0x00000204 +#define BF_C2B_TL2_CLKN_RTERM_PDN_INFO(inst) ((inst) + 0x00000187), 0x00000206 + +#define REG_ADC_TL1_CKP_R_PUP_ADDR(inst) ((inst) + 0x00000188) +#define BF_ADC_TL1_CLKP_R_PUP_INFO(inst) ((inst) + 0x00000188), 0x00000500 + +#define REG_ADC_TL1_CKP_R_PDN_ADDR(inst) ((inst) + 0x00000189) +#define BF_ADC_TL1_CLKP_R_PDN_INFO(inst) ((inst) + 0x00000189), 0x00000500 + +#define REG_ADC_TL1_CKN_R_PUP_ADDR(inst) ((inst) + 0x0000018A) +#define BF_ADC_TL1_CLKN_R_PUP_INFO(inst) ((inst) + 0x0000018A), 0x00000500 + +#define REG_ADC_TL1_CKN_R_PDN_ADDR(inst) ((inst) + 0x0000018B) +#define BF_ADC_TL1_CLKN_R_PDN_INFO(inst) ((inst) + 0x0000018B), 0x00000500 + +#define REG_ADC_TL1_CKP_C_ADDR(inst) ((inst) + 0x0000018C) +#define BF_ADC_TL1_CLKP_C_INFO(inst) ((inst) + 0x0000018C), 0x00000500 + +#define REG_ADC_TL1_CKN_C_ADDR(inst) ((inst) + 0x0000018D) +#define BF_ADC_TL1_CLKN_C_INFO(inst) ((inst) + 0x0000018D), 0x00000500 + +#define REG_ADC_TL1_SYNC_RC_ADDR(inst) ((inst) + 0x0000018E) +#define BF_ADC_TL1_SYNC_R_INFO(inst) ((inst) + 0x0000018E), 0x00000200 +#define BF_ADC_TL1_SYNC_C_INFO(inst) ((inst) + 0x0000018E), 0x00000204 + +#define REG_ADC_TL1_CK_RTERM_ADDR(inst) ((inst) + 0x0000018F) +#define BF_ADC_TL1_CLKP_RTERM_PUP_INFO(inst) ((inst) + 0x0000018F), 0x00000200 +#define BF_ADC_TL1_CLKP_RTERM_PDN_INFO(inst) ((inst) + 0x0000018F), 0x00000202 +#define BF_ADC_TL1_CLKN_RTERM_PUP_INFO(inst) ((inst) + 0x0000018F), 0x00000204 +#define BF_ADC_TL1_CLKN_RTERM_PDN_INFO(inst) ((inst) + 0x0000018F), 0x00000206 + +#define REG_ADC_TL2_CKP_R_PUP_ADDR(inst) ((inst) + 0x00000190) +#define BF_ADC_TL2_CLKP_R_PUP_INFO(inst) ((inst) + 0x00000190), 0x00000500 + +#define REG_ADC_TL2_CKP_R_PDN_ADDR(inst) ((inst) + 0x00000191) +#define BF_ADC_TL2_CLKP_R_PDN_INFO(inst) ((inst) + 0x00000191), 0x00000500 + +#define REG_ADC_TL2_CKN_R_PUP_ADDR(inst) ((inst) + 0x00000192) +#define BF_ADC_TL2_CLKN_R_PUP_INFO(inst) ((inst) + 0x00000192), 0x00000500 + +#define REG_ADC_TL2_CKN_R_PDN_ADDR(inst) ((inst) + 0x00000193) +#define BF_ADC_TL2_CLKN_R_PDN_INFO(inst) ((inst) + 0x00000193), 0x00000500 + +#define REG_ADC_TL2_CKP_C_ADDR(inst) ((inst) + 0x00000194) +#define BF_ADC_TL2_CLKP_C_INFO(inst) ((inst) + 0x00000194), 0x00000500 + +#define REG_ADC_TL2_CKN_C_ADDR(inst) ((inst) + 0x00000195) +#define BF_ADC_TL2_CLKN_C_INFO(inst) ((inst) + 0x00000195), 0x00000500 + +#define REG_ADC_TL2_SYNC_RC_ADDR(inst) ((inst) + 0x00000196) +#define BF_ADC_TL2_SYNC_R_INFO(inst) ((inst) + 0x00000196), 0x00000200 +#define BF_ADC_TL2_SYNC_C_INFO(inst) ((inst) + 0x00000196), 0x00000204 + +#define REG_ADC_TL2_CK_RTERM_ADDR(inst) ((inst) + 0x00000197) +#define BF_ADC_TL2_CLKP_RTERM_PUP_INFO(inst) ((inst) + 0x00000197), 0x00000200 +#define BF_ADC_TL2_CLKP_RTERM_PDN_INFO(inst) ((inst) + 0x00000197), 0x00000202 +#define BF_ADC_TL2_CLKN_RTERM_PUP_INFO(inst) ((inst) + 0x00000197), 0x00000204 +#define BF_ADC_TL2_CLKN_RTERM_PDN_INFO(inst) ((inst) + 0x00000197), 0x00000206 + +#define REG_C2S_CKP_R_PUP_ADDR(inst) ((inst) + 0x00000198) +#define BF_C2S_CLKP_R_PUP_INFO(inst) ((inst) + 0x00000198), 0x00000500 + +#define REG_C2S_CKP_R_PDN_ADDR(inst) ((inst) + 0x00000199) +#define BF_C2S_CLKP_R_PDN_INFO(inst) ((inst) + 0x00000199), 0x00000500 + +#define REG_C2S_CKN_R_PUP_ADDR(inst) ((inst) + 0x0000019A) +#define BF_C2S_CLKN_R_PUP_INFO(inst) ((inst) + 0x0000019A), 0x00000500 + +#define REG_C2S_CKN_R_PDN_ADDR(inst) ((inst) + 0x0000019B) +#define BF_C2S_CLKN_R_PDN_INFO(inst) ((inst) + 0x0000019B), 0x00000500 + +#define REG_C2S_CKP_C_ADDR(inst) ((inst) + 0x0000019C) +#define BF_C2S_CLKP_C_INFO(inst) ((inst) + 0x0000019C), 0x00000500 + +#define REG_C2S_CKN_C_ADDR(inst) ((inst) + 0x0000019D) +#define BF_C2S_CLKN_C_INFO(inst) ((inst) + 0x0000019D), 0x00000500 + +#define REG_C2S_SYNC_RC_ADDR(inst) ((inst) + 0x0000019E) +#define BF_C2S_SYNC_R_INFO(inst) ((inst) + 0x0000019E), 0x00000200 +#define BF_C2S_SYNC_C_INFO(inst) ((inst) + 0x0000019E), 0x00000204 + +#define REG_C2S_CK_RTERM_ADDR(inst) ((inst) + 0x0000019F) +#define BF_C2S_CLKP_RTERM_PUP_INFO(inst) ((inst) + 0x0000019F), 0x00000200 +#define BF_C2S_CLKP_RTERM_PDN_INFO(inst) ((inst) + 0x0000019F), 0x00000202 +#define BF_C2S_CLKN_RTERM_PUP_INFO(inst) ((inst) + 0x0000019F), 0x00000204 +#define BF_C2S_CLKN_RTERM_PDN_INFO(inst) ((inst) + 0x0000019F), 0x00000206 + +#define REG_S01_CKP_R_PUP_ADDR(inst) ((inst) + 0x000001A0) +#define BF_S01_CLKP_R_PUP_INFO(inst) ((inst) + 0x000001A0), 0x00000500 + +#define REG_S01_CKP_R_PDN_ADDR(inst) ((inst) + 0x000001A1) +#define BF_S01_CLKP_R_PDN_INFO(inst) ((inst) + 0x000001A1), 0x00000500 + +#define REG_S01_CKN_R_PUP_ADDR(inst) ((inst) + 0x000001A2) +#define BF_S01_CLKN_R_PUP_INFO(inst) ((inst) + 0x000001A2), 0x00000500 + +#define REG_S01_CKN_R_PDN_ADDR(inst) ((inst) + 0x000001A3) +#define BF_S01_CLKN_R_PDN_INFO(inst) ((inst) + 0x000001A3), 0x00000500 + +#define REG_S01_CKP_C_ADDR(inst) ((inst) + 0x000001A4) +#define BF_S01_CLKP_C_INFO(inst) ((inst) + 0x000001A4), 0x00000500 + +#define REG_S01_CKN_C_ADDR(inst) ((inst) + 0x000001A5) +#define BF_S01_CLKN_C_INFO(inst) ((inst) + 0x000001A5), 0x00000500 + +#define REG_S01_SYNC_RC_ADDR(inst) ((inst) + 0x000001A6) +#define BF_S01_SYNC_R_INFO(inst) ((inst) + 0x000001A6), 0x00000200 +#define BF_S01_SYNC_C_INFO(inst) ((inst) + 0x000001A6), 0x00000204 + +#define REG_S01_CK_RTERM_ADDR(inst) ((inst) + 0x000001A7) +#define BF_S01_CLKP_RTERM_PUP_INFO(inst) ((inst) + 0x000001A7), 0x00000200 +#define BF_S01_CLKP_RTERM_PDN_INFO(inst) ((inst) + 0x000001A7), 0x00000202 +#define BF_S01_CLKN_RTERM_PUP_INFO(inst) ((inst) + 0x000001A7), 0x00000204 +#define BF_S01_CLKN_RTERM_PDN_INFO(inst) ((inst) + 0x000001A7), 0x00000206 + +#define REG_S23_CKP_R_PUP_ADDR(inst) ((inst) + 0x000001A8) +#define BF_S23_CLKP_R_PUP_INFO(inst) ((inst) + 0x000001A8), 0x00000500 + +#define REG_S23_CKP_R_PDN_ADDR(inst) ((inst) + 0x000001A9) +#define BF_S23_CLKP_R_PDN_INFO(inst) ((inst) + 0x000001A9), 0x00000500 + +#define REG_S23_CKN_R_PUP_ADDR(inst) ((inst) + 0x000001AA) +#define BF_S23_CLKN_R_PUP_INFO(inst) ((inst) + 0x000001AA), 0x00000500 + +#define REG_S23_CKN_R_PDN_ADDR(inst) ((inst) + 0x000001AB) +#define BF_S23_CLKN_R_PDN_INFO(inst) ((inst) + 0x000001AB), 0x00000500 + +#define REG_S23_CKP_C_ADDR(inst) ((inst) + 0x000001AC) +#define BF_S23_CLKP_C_INFO(inst) ((inst) + 0x000001AC), 0x00000500 + +#define REG_S23_CKN_C_ADDR(inst) ((inst) + 0x000001AD) +#define BF_S23_CLKN_C_INFO(inst) ((inst) + 0x000001AD), 0x00000500 + +#define REG_S23_SYNC_RC_ADDR(inst) ((inst) + 0x000001AE) +#define BF_S23_SYNC_R_INFO(inst) ((inst) + 0x000001AE), 0x00000200 +#define BF_S23_SYNC_C_INFO(inst) ((inst) + 0x000001AE), 0x00000204 + +#define REG_S23_CK_RTERM_ADDR(inst) ((inst) + 0x000001AF) +#define BF_S23_CLKP_RTERM_PUP_INFO(inst) ((inst) + 0x000001AF), 0x00000200 +#define BF_S23_CLKP_RTERM_PDN_INFO(inst) ((inst) + 0x000001AF), 0x00000202 +#define BF_S23_CLKN_RTERM_PUP_INFO(inst) ((inst) + 0x000001AF), 0x00000204 +#define BF_S23_CLKN_RTERM_PDN_INFO(inst) ((inst) + 0x000001AF), 0x00000206 + +#define REG_CCSS_CLK_CTRL_ADDR(inst) ((inst) + 0x000001B0) +#define BF_CCSS_CLK_EN_INFO(inst) ((inst) + 0x000001B0), 0x00000100 +#define BF_CCSS_FSM_PRN_RESET_INFO(inst) ((inst) + 0x000001B0), 0x00000101 +#define BF_CCSS_CLK_DIV_INFO(inst) ((inst) + 0x000001B0), 0x00000204 + +#define REG_CCSS_RST_CTRL_ADDR(inst) ((inst) + 0x000001B1) +#define BF_CCSS_FSM_RESET_INFO(inst) ((inst) + 0x000001B1), 0x00000100 +#define BF_CCSS_REGMAP_RESET_INFO(inst) ((inst) + 0x000001B1), 0x00000101 +#define BF_CCSS_SPI_RDEN_INFO(inst) ((inst) + 0x000001B1), 0x00000102 +#define BF_CCSS_SPI_WREN_INFO(inst) ((inst) + 0x000001B1), 0x00000103 +#define BF_CCSS_FSM_STATE_INFO(inst) ((inst) + 0x000001B1), 0x00000404 + +#define REG_CCSS_ACT_SEL_ADDR(inst) ((inst) + 0x000001B2) +#define BF_CCSS_FSM_ACT_SEL_INFO(inst) ((inst) + 0x000001B2), 0x00000300 +#define BF_CCSS_FSM_RCDAC_PN_SEL_INFO(inst) ((inst) + 0x000001B2), 0x00000204 +#define BF_CCSS_FSM_UPDN_SEL_INFO(inst) ((inst) + 0x000001B2), 0x00000107 + +#define REG_CCSS_SWIT_TIME_ADDR(inst) ((inst) + 0x000001B3) +#define BF_CCSS_FSM_SWITCH_TIME_INFO(inst) ((inst) + 0x000001B3), 0x00000800 + +#define REG_CCSS_FSM_CTRL_ADDR(inst) ((inst) + 0x000001B4) +#define BF_CCSS_FSM_START_INFO(inst) ((inst) + 0x000001B4), 0x00000100 +#define BF_CCSS_FSM_INIT_INFO(inst) ((inst) + 0x000001B4), 0x00000101 +#define BF_CCSS_FSM_PULL_UP_DONE_INFO(inst) ((inst) + 0x000001B4), 0x00000104 +#define BF_CCSS_FSM_PULL_DN_DONE_INFO(inst) ((inst) + 0x000001B4), 0x00000105 +#define BF_CCSS_FSM_BOUNDARY_HIT_INFO(inst) ((inst) + 0x000001B4), 0x00000106 +#define BF_CCSS_FSM_INIT_DONE_INFO(inst) ((inst) + 0x000001B4), 0x00000107 + +#define REG_CCSS_REGCLK_DIV_ADDR(inst) ((inst) + 0x000001B5) +#define BF_CCSS_FSM_REGCLK_DIV_INFO(inst) ((inst) + 0x000001B5), 0x00000800 + +#define REG_C2C_CC_ACT_NEW_RTERM_ADDR(inst) ((inst) + 0x000001BA) +#define BF_C2C_CC_ACT_NEW_CLKP_RTERM_PUP_INFO(inst) ((inst) + 0x000001BA), 0x00000200 +#define BF_C2C_CC_ACT_NEW_CLKP_RTERM_PDN_INFO(inst) ((inst) + 0x000001BA), 0x00000202 +#define BF_C2C_CC_ACT_NEW_CLKN_RTERM_PUP_INFO(inst) ((inst) + 0x000001BA), 0x00000204 +#define BF_C2C_CC_ACT_NEW_CLKN_RTERM_PDN_INFO(inst) ((inst) + 0x000001BA), 0x00000206 + +#define REG_C2C_CC_ACT_NEW_CLKP_RPUP_ADDR(inst) ((inst) + 0x000001BB) +#define BF_C2C_CC_ACT_NEW_CLKP_R_PUP_INFO(inst) ((inst) + 0x000001BB), 0x00000500 + +#define REG_C2C_CC_ACT_NEW_CLKP_RPDN_ADDR(inst) ((inst) + 0x000001BC) +#define BF_C2C_CC_ACT_NEW_CLKP_R_PDN_INFO(inst) ((inst) + 0x000001BC), 0x00000500 + +#define REG_C2C_CC_ACT_NEW_CLKP_C_ADDR(inst) ((inst) + 0x000001BD) +#define BF_C2C_CC_ACT_NEW_CLKP_C_INFO(inst) ((inst) + 0x000001BD), 0x00000500 + +#define REG_C2C_CC_ACT_NEW_CLKN_RPUP_ADDR(inst) ((inst) + 0x000001BE) +#define BF_C2C_CC_ACT_NEW_CLKN_R_PUP_INFO(inst) ((inst) + 0x000001BE), 0x00000500 + +#define REG_C2C_CC_ACT_NEW_CLKN_RPDN_ADDR(inst) ((inst) + 0x000001BF) +#define BF_C2C_CC_ACT_NEW_CLKN_R_PDN_INFO(inst) ((inst) + 0x000001BF), 0x00000500 + +#define REG_C2C_CC_ACT_NEW_CLKN_C_ADDR(inst) ((inst) + 0x000001C0) +#define BF_C2C_CC_ACT_NEW_CLKN_C_INFO(inst) ((inst) + 0x000001C0), 0x00000500 + +#define REG_C2C_CC_ACT_NEW_SYNC_ADDR(inst) ((inst) + 0x000001C1) +#define BF_C2C_CC_ACT_NEW_SYNC_R_INFO(inst) ((inst) + 0x000001C1), 0x00000200 +#define BF_C2C_CC_ACT_NEW_SYNC_C_INFO(inst) ((inst) + 0x000001C1), 0x00000204 + +#define REG_C2A_CC_ACT_NEW_RTERM_ADDR(inst) ((inst) + 0x000001C2) +#define BF_C2A_CC_ACT_NEW_CLKP_RTERM_PUP_INFO(inst) ((inst) + 0x000001C2), 0x00000200 +#define BF_C2A_CC_ACT_NEW_CLKP_RTERM_PDN_INFO(inst) ((inst) + 0x000001C2), 0x00000202 +#define BF_C2A_CC_ACT_NEW_CLKN_RTERM_PUP_INFO(inst) ((inst) + 0x000001C2), 0x00000204 +#define BF_C2A_CC_ACT_NEW_CLKN_RTERM_PDN_INFO(inst) ((inst) + 0x000001C2), 0x00000206 + +#define REG_C2A_CC_ACT_NEW_CLKP_RPUP_ADDR(inst) ((inst) + 0x000001C3) +#define BF_C2A_CC_ACT_NEW_CLKP_R_PUP_INFO(inst) ((inst) + 0x000001C3), 0x00000500 + +#define REG_C2A_CC_ACT_NEW_CLKP_RPDN_ADDR(inst) ((inst) + 0x000001C4) +#define BF_C2A_CC_ACT_NEW_CLKP_R_PDN_INFO(inst) ((inst) + 0x000001C4), 0x00000500 + +#define REG_C2A_CC_ACT_NEW_CLKP_C_ADDR(inst) ((inst) + 0x000001C5) +#define BF_C2A_CC_ACT_NEW_CLKP_C_INFO(inst) ((inst) + 0x000001C5), 0x00000500 + +#define REG_C2A_CC_ACT_NEW_CLKN_RPUP_ADDR(inst) ((inst) + 0x000001C6) +#define BF_C2A_CC_ACT_NEW_CLKN_R_PUP_INFO(inst) ((inst) + 0x000001C6), 0x00000500 + +#define REG_C2A_CC_ACT_NEW_CLKN_RPDN_ADDR(inst) ((inst) + 0x000001C7) +#define BF_C2A_CC_ACT_NEW_CLKN_R_PDN_INFO(inst) ((inst) + 0x000001C7), 0x00000500 + +#define REG_C2A_CC_ACT_NEW_CLKN_C_ADDR(inst) ((inst) + 0x000001C8) +#define BF_C2A_CC_ACT_NEW_CLKN_C_INFO(inst) ((inst) + 0x000001C8), 0x00000500 + +#define REG_C2A_CC_ACT_NEW_SYNC_ADDR(inst) ((inst) + 0x000001C9) +#define BF_C2A_CC_ACT_NEW_SYNC_R_INFO(inst) ((inst) + 0x000001C9), 0x00000200 +#define BF_C2A_CC_ACT_NEW_SYNC_C_INFO(inst) ((inst) + 0x000001C9), 0x00000204 + +#define REG_C2S_CC_ACT_NEW_RTERM_ADDR(inst) ((inst) + 0x000001CA) +#define BF_C2S_CC_ACT_NEW_CLKP_RTERM_PUP_INFO(inst) ((inst) + 0x000001CA), 0x00000200 +#define BF_C2S_CC_ACT_NEW_CLKP_RTERM_PDN_INFO(inst) ((inst) + 0x000001CA), 0x00000202 +#define BF_C2S_CC_ACT_NEW_CLKN_RTERM_PUP_INFO(inst) ((inst) + 0x000001CA), 0x00000204 +#define BF_C2S_CC_ACT_NEW_CLKN_RTERM_PDN_INFO(inst) ((inst) + 0x000001CA), 0x00000206 + +#define REG_C2S_CC_ACT_NEW_CLKP_RPUP_ADDR(inst) ((inst) + 0x000001CB) +#define BF_C2S_CC_ACT_NEW_CLKP_R_PUP_INFO(inst) ((inst) + 0x000001CB), 0x00000500 + +#define REG_C2S_CC_ACT_NEW_CLKP_RPDN_ADDR(inst) ((inst) + 0x000001CC) +#define BF_C2S_CC_ACT_NEW_CLKP_R_PDN_INFO(inst) ((inst) + 0x000001CC), 0x00000500 + +#define REG_C2S_CC_ACT_NEW_CLKP_C_ADDR(inst) ((inst) + 0x000001CD) +#define BF_C2S_CC_ACT_NEW_CLKP_C_INFO(inst) ((inst) + 0x000001CD), 0x00000500 + +#define REG_C2S_CC_ACT_NEW_CLKN_RPUP_ADDR(inst) ((inst) + 0x000001CE) +#define BF_C2S_CC_ACT_NEW_CLKN_R_PUP_INFO(inst) ((inst) + 0x000001CE), 0x00000500 + +#define REG_C2S_CC_ACT_NEW_CLKN_RPDN_ADDR(inst) ((inst) + 0x000001CF) +#define BF_C2S_CC_ACT_NEW_CLKN_R_PDN_INFO(inst) ((inst) + 0x000001CF), 0x00000500 + +#define REG_C2S_CC_ACT_NEW_CLKN_C_ADDR(inst) ((inst) + 0x000001D0) +#define BF_C2S_CC_ACT_NEW_CLKN_C_INFO(inst) ((inst) + 0x000001D0), 0x00000500 + +#define REG_C2S_CC_ACT_NEW_SYNC_ADDR(inst) ((inst) + 0x000001D1) +#define BF_C2S_CC_ACT_NEW_SYNC_R_INFO(inst) ((inst) + 0x000001D1), 0x00000200 +#define BF_C2S_CC_ACT_NEW_SYNC_C_INFO(inst) ((inst) + 0x000001D1), 0x00000204 + +#define REG_DACSENSE_01_CTRL0_ADDR(inst) ((inst) + 0x000001D2) +#define BF_DACSENSE_REF_LVL_LO_01_INFO(inst) ((inst) + 0x000001D2), 0x00000200 +#define BF_DACSENSE_REF_LVL_HI_01_INFO(inst) ((inst) + 0x000001D2), 0x00000202 +#define BF_DACSENSE_DACVOLT_SEL_01_INFO(inst) ((inst) + 0x000001D2), 0x00000204 +#define BF_DACSENSE_DAC_SEL_SPARE_01_INFO(inst) ((inst) + 0x000001D2), 0x00000206 + +#define REG_DACSENSE_01_CTRL1_ADDR(inst) ((inst) + 0x000001D3) +#define BF_DACSENSE_REF_SEL_01_INFO(inst) ((inst) + 0x000001D3), 0x00000100 +#define BF_DACSENSE_DAC_SEL_01_INFO(inst) ((inst) + 0x000001D3), 0x00000101 +#define BF_DACSENSE_EN_01_INFO(inst) ((inst) + 0x000001D3), 0x00000104 +#define BF_DACSENSE_AMUX_EN_01_INFO(inst) ((inst) + 0x000001D3), 0x00000105 +#define BF_DACSENSE_COMPCLK_01_INFO(inst) ((inst) + 0x000001D3), 0x00000106 +#define BF_DACSENSE_COMP_VALUE_01_INFO(inst) ((inst) + 0x000001D3), 0x00000107 + +#define REG_DACSENSE_23_CTRL0_ADDR(inst) ((inst) + 0x000001D4) +#define BF_DACSENSE_REF_LVL_LO_23_INFO(inst) ((inst) + 0x000001D4), 0x00000200 +#define BF_DACSENSE_REF_LVL_HI_23_INFO(inst) ((inst) + 0x000001D4), 0x00000202 +#define BF_DACSENSE_DACVOLT_SEL_23_INFO(inst) ((inst) + 0x000001D4), 0x00000204 +#define BF_DACSENSE_DAC_SEL_SPARE_23_INFO(inst) ((inst) + 0x000001D4), 0x00000206 + +#define REG_DACSENSE_23_CTRL1_ADDR(inst) ((inst) + 0x000001D5) +#define BF_DACSENSE_REF_SEL_23_INFO(inst) ((inst) + 0x000001D5), 0x00000100 +#define BF_DACSENSE_DAC_SEL_23_INFO(inst) ((inst) + 0x000001D5), 0x00000101 +#define BF_DACSENSE_EN_23_INFO(inst) ((inst) + 0x000001D5), 0x00000104 +#define BF_DACSENSE_AMUX_EN_23_INFO(inst) ((inst) + 0x000001D5), 0x00000105 +#define BF_DACSENSE_COMPCLK_23_INFO(inst) ((inst) + 0x000001D5), 0x00000106 +#define BF_DACSENSE_COMP_VALUE_23_INFO(inst) ((inst) + 0x000001D5), 0x00000107 + +#endif /* __ADI_APOLLO_BF_MASTER_BIAS_CTRL_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_mb_regs.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_mb_regs.h new file mode 100644 index 00000000000000..67c4f066e05106 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_mb_regs.h @@ -0,0 +1,161 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:21 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_MB_REGS_H__ +#define __ADI_APOLLO_BF_MB_REGS_H__ + +/*============= D E F I N E S ==============*/ +#define REG_MCR_ADDR 0x4C006000 +#define BF_E_MDR_CLEAR_INFO 0x4C006000, 0x00000100 +#define BF_H_WR_DISABLE_INFO 0x4C006000, 0x00000101 + +#define REG_IRQ_ENABLE_ADDR 0x4C006004 +#define BF_HREQ_ACK_IRQEN_INFO 0x4C006004, 0x00000100 +#define BF_ERESP_RDY_IRQEN_INFO 0x4C006004, 0x00000101 +#define BF_HREQ_RDY_IRQEN_INFO 0x4C006004, 0x00000102 +#define BF_ERESP_ACK_IRQEN_INFO 0x4C006004, 0x00000103 + +#define REG_E_STATUS_ADDR 0x4C006020 +#define BF_HREQ_ACK_INFO 0x4C006020, 0x00000100 +#define BF_ERESP_RDY_INFO 0x4C006020, 0x00000101 + +#define REG_ERC_ADDR(n) (0x4C006040 + 4 * (n)) +#define BF_ERESP_CODE_INFO(n) (0x4C006040 + 4 * (n)), 0x00002000 + +#define REG_H_STATUS_ADDR 0x4C006120 +#define BF_HREQ_RDY_INFO 0x4C006120, 0x00000100 +#define BF_ERESP_ACK_INFO 0x4C006120, 0x00000101 + +#define REG_HRC_ADDR(n) (0x4C006140 + 4 * (n)) +#define BF_HREQ_CODE_INFO(n) (0x4C006140 + 4 * (n)), 0x00002000 + +#define REG_MDR_ADDR(n) (0x4C006200 + 4 * (n)) +#define BF_MB_DATA_REG_INFO(n) (0x4C006200 + 4 * (n)), 0x00002000 + +#define REG_RSTINFO_ADDR 0x4C006310 +#define BF_SYSRESETREQ_INFO 0x4C006310, 0x00000100 +#define BF_WATCHDOG_INFO 0x4C006310, 0x00000101 +#define BF_LOCKUP_INFO 0x4C006310, 0x00000102 + +#define REG_ROM_ERR_ST_ADDR 0x4C006320 +#define BF_ROM_ERR_INFO 0x4C006320, 0x00000100 + +#define REG_ROM_ERR_ADDR_ADDR 0x4C006324 +#define BF_ROM_ERR_ADDR_INFO 0x4C006324, 0x00002000 + +#define REG_ROM_ERR_DATA_ADDR 0x4C006328 +#define BF_ROM_ERR_DATA_INFO 0x4C006328, 0x00002000 + +#define REG_ROM_ERR_PARITY_ADDR 0x4C00632C +#define BF_ROM_ERR_PARITY_INFO 0x4C00632C, 0x00002000 + +#define REG_SRAM_ERR_ST_ADDR 0x4C006330 +#define BF_SRAM_ERR_INFO 0x4C006330, 0x00000100 + +#define REG_SRAM_ERR_ADDR_ADDR 0x4C006334 +#define BF_SRAM_ERR_ADDR_INFO 0x4C006334, 0x00002000 + +#define REG_SRAM_ERR_DATA_ADDR 0x4C006338 +#define BF_SRAM_ERR_DATA_INFO 0x4C006338, 0x00002000 + +#define REG_SRAM_ERR_PARITY_ADDR 0x4C00633C +#define BF_SRAM_ERR_PARITY_INFO 0x4C00633C, 0x00002000 + +#define REG_BOOT_FLOW0_ADDR 0x4C006340 +#define BF_PLATFORM_INIT_START_INFO 0x4C006340, 0x00000100 +#define BF_IS_SELF_BOOT_INFO 0x4C006340, 0x00000101 +#define BF_LIFECYCLE_INFO 0x4C006340, 0x00000302 +#define BF_CRYPTO_SELFTESTS_START_INFO 0x4C006340, 0x00000105 +#define BF_LOAD_AND_UNWRAP_KEYS_INFO 0x4C006340, 0x00000106 +#define BF_IS_SECURE_BOOT_INFO 0x4C006340, 0x00000107 +#define BF_WARMBOOT_INFO 0x4C006340, 0x00000108 +#define BF_SBS_FAIL_SBH2_PRESENT_INFO 0x4C006340, 0x00000109 +#define BF_ENC_FW_REQUIRED_INFO 0x4C006340, 0x0000010A +#define BF_ENC_FW_PRESENT_INFO 0x4C006340, 0x0000010B +#define BF_APP_RESET_INFO 0x4C006340, 0x0000010C +#define BF_SBS_ADDR1_1ST_ATTEMPT_INFO 0x4C006340, 0x0000010D +#define BF_OPEN_SAMPLE_INFO 0x4C006340, 0x0000010E +#define BF_BOOT_FAILED_INFO 0x4C006340, 0x0000010F +#define BF_SECURE_BOOT_STAGE_0_INFO 0x4C006340, 0x00000810 +#define BF_SECURE_BOOT_STAGE_1_INFO 0x4C006340, 0x00000818 + +#define REG_BOOT_FLOW1_ADDR 0x4C006344 +#define BF_SECURE_BOOT_STAGE_2_INFO 0x4C006344, 0x00000800 +#define BF_ERROR_CODE_0_INFO 0x4C006344, 0x00000C08 +#define BF_ERROR_CODE_1_INFO 0x4C006344, 0x00000C14 + +#define REG_BOOT_AUX_STATE_ADDR 0x4C006348 +#define BF_BOOT_AUX_STATE_INFO 0x4C006348, 0x00002000 + +#define REG_ECC_ERROR_ADDR 0x4C006350 +#define BF_ECC_1BIT_ERR_INFO 0x4C006350, 0x00000100 +#define BF_ECC_2BIT_ERR_INFO 0x4C006350, 0x00000101 +#define BF_ERROR_ADDR_INFO 0x4C006350, 0x00000A10 + +#define REG_BOOT_STATUS_ADDR 0x4C006358 +#define BF_LOCKOUT_INFO 0x4C006358, 0x00000100 +#define BF_CRC_MISMATCH_INFO 0x4C006358, 0x00000101 +#define BF_NVM_RDY_INFO 0x4C006358, 0x00000102 +#ifdef USE_HW_BF +#define BF_HW_FSM_BOOT_ERROR_INFO 0x4C006358, 0x0000010F +#endif /* USE_HW_BF */ +#ifdef USE_HW_BF +#define BF_HW_FSM_STATUS_INFO 0x4C006358, 0x00001010 +#endif /* USE_HW_BF */ + +#define REG_CHIP_EXPORT_SHADOW0_ADDR 0x4C006360 +#define BF_CHIP_EXPORT_SHADOW0_INFO 0x4C006360, 0x00002000 + +#define REG_CHIP_EXPORT_SHADOW1_ADDR 0x4C006364 +#define BF_CHIP_EXPORT_SHADOW1_INFO 0x4C006364, 0x00002000 + +#define REG_CHIP_EXPORT_SHADOW2_ADDR 0x4C006368 +#define BF_CHIP_EXPORT_SHADOW2_INFO 0x4C006368, 0x00002000 + +#define REG_CHIP_EXPORT_SHADOW3_ADDR 0x4C00636C +#define BF_CHIP_EXPORT_SHADOW3_INFO 0x4C00636C, 0x00002000 + +#define REG_CHIP_EXPORT_SHADOW4_ADDR 0x4C006370 +#define BF_CHIP_EXPORT_SHADOW4_INFO 0x4C006370, 0x00002000 + +#define REG_CHIP_EXPORT_SHADOW5_ADDR 0x4C006374 +#define BF_CHIP_EXPORT_SHADOW5_INFO 0x4C006374, 0x00002000 + +#define REG_CHIP_EXPORT_SHADOW6_ADDR 0x4C006378 +#define BF_CHIP_EXPORT_SHADOW6_INFO 0x4C006378, 0x00002000 + +#define REG_CHIP_EXPORT_SHADOW7_ADDR 0x4C00637C +#define BF_CHIP_EXPORT_SHADOW7_INFO 0x4C00637C, 0x00002000 + +#define REG_NO_ECC_SHADOW0_ADDR 0x4C006380 +#define BF_NOECC_SHADOW0_INFO 0x4C006380, 0x00002000 + +#define REG_NO_ECC_SHADOW1_ADDR 0x4C006384 +#define BF_NOECC_SHADOW1_INFO 0x4C006384, 0x00002000 + +#define REG_NO_ECC_SHADOW2_ADDR 0x4C006388 +#define BF_NOECC_SHADOW2_INFO 0x4C006388, 0x00002000 + +#define REG_NO_ECC_SHADOW3_ADDR 0x4C00638C +#define BF_NOECC_SHADOW3_INFO 0x4C00638C, 0x00002000 + +#define REG_LIFECYCLE_STATUS_ADDR 0x4C0063A0 +#define BF_LIFECYCLE_TR_INFO 0x4C0063A0, 0x00000A00 +#define BF_LIFECYCLE_ENCODE_INFO 0x4C0063A0, 0x00000410 + +#define REG_VERSION_ADDR 0x4C0063FC +#define BF_VERSION_INFO 0x4C0063FC, 0x00000800 + +#endif /* __ADI_APOLLO_BF_MB_REGS_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_mcs_c_only.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_mcs_c_only.h new file mode 100644 index 00000000000000..e74e6aa1249623 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_mcs_c_only.h @@ -0,0 +1,123 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:19 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_MCS_C_ONLY_H__ +#define __ADI_APOLLO_BF_MCS_C_ONLY_H__ + +/*============= D E F I N E S ==============*/ +#define REG_PLL_CTRL0_ADDR 0x4C001500 +#define BF_PLL_REFCLK_EN_INFO 0x4C001500, 0x00000100 +#define BF_PLL_DEVCLK_BYP_BIAS_R_INFO 0x4C001500, 0x00000104 + +#define REG_PLL_CTRL1_ADDR 0x4C001501 +#define BF_CLKPLL_RESET_INFO 0x4C001501, 0x00000100 + +#define REG_PLL_DEVCLK_BUF_TRIM_ADDR 0x4C001502 +#define BF_PLL_DEVCLK_CLKBUF_OFFSET_EN_INFO 0x4C001502, 0x00000100 +#define BF_PLL_DEVCLK_CLKBUF_TRM_VCM_INFO 0x4C001502, 0x00000304 + +#define REG_PLL_DEVCLK_BUF_TERM_ADDR 0x4C001503 +#define BF_PLL_DEVCLK_CLKBUF_TERM_EN_INFO 0x4C001503, 0x00000100 +#define BF_PLL_DEVCLK_CLKBUF_TRM_IBIAS_INFO 0x4C001503, 0x00000204 + +#define REG_DRV_EN_CTRL_ADDR 0x4C001504 +#define BF_EN_DRV_I_A_INFO 0x4C001504, 0x00000100 +#define BF_EN_DRV_I_B_INFO 0x4C001504, 0x00000101 + +#define REG_TRIG_CTRL0_ADDR 0x4C001505 +#define BF_TRIGGER_EN_MCS_C_ONLY_INFO 0x4C001505, 0x00000100 +#define BF_TRIGGER_LEVEL_INFO 0x4C001505, 0x00000104 + +#define REG_CK_TO_MCS_EN_ADDR 0x4C001506 +#define BF_EN_CK_TO_MCS_MCS_C_ONLY_INFO 0x4C001506, 0x00000100 + +#define REG_CC_CLK_CTRL_ADDR 0x4C001507 +#define BF_CC_CLK_C_INFO 0x4C001507, 0x00000100 +#define BF_CC_COMP_C_INFO 0x4C001507, 0x00000104 + +#define REG_CC_CFG0_ADDR 0x4C001508 +#define BF_CC_CONFIG_C_INFO 0x4C001508, 0x00001000 + +#define REG_CC_CFG1_ADDR 0x4C001509 + +#define REG_C2AB_PRE_SYNC_ADDR 0x4C00150A + +#define REG_SEL_ODRV_ADDR 0x4C00150B +#define BF_SEL_ODRV_MUX_INFO 0x4C00150B, 0x00000100 + +#define REG_PLL_TDC_PATH_EN_ADDR 0x4C00150C +#define BF_PLL_DEVCLK_TDC_PATH_EN_INFO 0x4C00150C, 0x00000100 + +#define REG_C2A_TL1_CKP_R_PUP_ADDR 0x4C00150D +#define BF_C2A_TL1_CLKP_R_PUP_INFO 0x4C00150D, 0x00000500 + +#define REG_C2A_TL1_CKP_R_PDN_ADDR 0x4C00150E +#define BF_C2A_TL1_CLKP_R_PDN_INFO 0x4C00150E, 0x00000500 + +#define REG_C2A_TL1_CKN_R_PUP_ADDR 0x4C00150F +#define BF_C2A_TL1_CLKN_R_PUP_INFO 0x4C00150F, 0x00000500 + +#define REG_C2A_TL1_CKN_R_PDN_ADDR 0x4C001510 +#define BF_C2A_TL1_CLKN_R_PDN_INFO 0x4C001510, 0x00000500 + +#define REG_C2A_TL1_CKP_C_ADDR 0x4C001511 +#define BF_C2A_TL1_CLKP_C_INFO 0x4C001511, 0x00000500 + +#define REG_C2A_TL1_CKN_C_ADDR 0x4C001512 +#define BF_C2A_TL1_CLKN_C_INFO 0x4C001512, 0x00000500 + +#define REG_C2A_TL1_SYNC_RC_ADDR 0x4C001513 +#define BF_C2A_TL1_SYNC_R_INFO 0x4C001513, 0x00000200 +#define BF_C2A_TL1_SYNC_C_INFO 0x4C001513, 0x00000204 + +#define REG_C2A_TL1_CK_RTERM_ADDR 0x4C001514 +#define BF_C2A_TL1_CLKP_RTERM_PUP_INFO 0x4C001514, 0x00000200 +#define BF_C2A_TL1_CLKP_RTERM_PDN_INFO 0x4C001514, 0x00000202 +#define BF_C2A_TL1_CLKN_RTERM_PUP_INFO 0x4C001514, 0x00000204 +#define BF_C2A_TL1_CLKN_RTERM_PDN_INFO 0x4C001514, 0x00000206 + +#define REG_C2B_TL1_CKP_R_PUP_ADDR 0x4C001515 +#define BF_C2B_TL1_CLKP_R_PUP_INFO 0x4C001515, 0x00000500 + +#define REG_C2B_TL1_CKP_R_PDN_ADDR 0x4C001516 +#define BF_C2B_TL1_CLKP_R_PDN_INFO 0x4C001516, 0x00000500 + +#define REG_C2B_TL1_CKN_R_PUP_ADDR 0x4C001517 +#define BF_C2B_TL1_CLKN_R_PUP_INFO 0x4C001517, 0x00000500 + +#define REG_C2B_TL1_CKN_R_PDN_ADDR 0x4C001518 +#define BF_C2B_TL1_CLKN_R_PDN_INFO 0x4C001518, 0x00000500 + +#define REG_C2B_TL1_CKP_C_ADDR 0x4C001519 +#define BF_C2B_TL1_CLKP_C_INFO 0x4C001519, 0x00000500 + +#define REG_C2B_TL1_CKN_C_ADDR 0x4C00151A +#define BF_C2B_TL1_CLKN_C_INFO 0x4C00151A, 0x00000500 + +#define REG_C2B_TL1_SYNC_RC_ADDR 0x4C00151B +#define BF_C2B_TL1_SYNC_R_INFO 0x4C00151B, 0x00000200 +#define BF_C2B_TL1_SYNC_C_INFO 0x4C00151B, 0x00000204 + +#define REG_C2B_TL1_CK_RTERM_ADDR 0x4C00151C +#define BF_C2B_TL1_CLKP_RTERM_PUP_INFO 0x4C00151C, 0x00000200 +#define BF_C2B_TL1_CLKP_RTERM_PDN_INFO 0x4C00151C, 0x00000202 +#define BF_C2B_TL1_CLKN_RTERM_PUP_INFO 0x4C00151C, 0x00000204 +#define BF_C2B_TL1_CLKN_RTERM_PDN_INFO 0x4C00151C, 0x00000206 + +#define REG_CC_SKEW_DET_ADDR 0x4C00151D +#define BF_EN_CK_CC_AMUX_CENTER_INFO 0x4C00151D, 0x00000100 +#define BF_CC_SKEW_DET_TRIM_CENTER_INFO 0x4C00151D, 0x00000404 + +#endif /* __ADI_APOLLO_BF_MCS_C_ONLY_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_mcs_sync.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_mcs_sync.h new file mode 100644 index 00000000000000..e2740e2f480611 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_mcs_sync.h @@ -0,0 +1,190 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:19 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_MCS_SYNC_H__ +#define __ADI_APOLLO_BF_MCS_SYNC_H__ + +/*============= D E F I N E S ==============*/ +#define MCS_SYNC_MCSTOP0 0x4C001410 +#define MCS_SYNC_MCSTOP1 0x4C001810 +#define MCS_SYNC_MCSTOP2 0x4C001C10 + +#define REG_CLOCKING_MODE_ADDR(inst) ((inst) + 0x00000000) +#define BF_MCS_DIVG_EN_INFO(inst) ((inst) + 0x00000000), 0x00000100 +#define BF_CLOCKING_MODE_INFO(inst) ((inst) + 0x00000000), 0x00000204 + +#define REG_SYNC_SYSREF_DELAY_0_ADDR(inst) ((inst) + 0x00000001) +#define BF_SYNC_SYSREF_DELAY_INFO(inst) ((inst) + 0x00000001), 0x00001000 + +#define REG_SYNC_SYSREF_DELAY_1_ADDR(inst) ((inst) + 0x00000002) + +#define REG_SYSREF_COUNT_ADDR(inst) ((inst) + 0x00000003) +#define BF_SYSREF_COUNT_INFO(inst) ((inst) + 0x00000003), 0x00000800 + +#define REG_SYSREF_PHASE0_ADDR(inst) ((inst) + 0x00000004) +#define BF_SYSREF_PHASE_INFO(inst) ((inst) + 0x00000004), 0x00001300 + +#define REG_SYSREF_PHASE1_ADDR(inst) ((inst) + 0x00000005) + +#define REG_SYSREF_PHASE2_ADDR(inst) ((inst) + 0x00000006) + +#define REG_SYSREF_ERR_WINDOW_ADDR(inst) ((inst) + 0x00000007) +#define BF_SYSREF_ERR_WINDOW_INFO(inst) ((inst) + 0x00000007), 0x00000700 +#define BF_SYSREF_WITHIN_ERRWINDOW_INFO(inst) ((inst) + 0x00000007), 0x00000107 + +#define REG_SYNC_MODE_ADDR(inst) ((inst) + 0x00000008) +#define BF_DYN_CFG_SYNC_INFO(inst) ((inst) + 0x00000008), 0x00000100 +#define BF_ONESHOT_SYNC_INFO(inst) ((inst) + 0x00000008), 0x00000101 +#define BF_MANUAL_SYNC_INFO(inst) ((inst) + 0x00000008), 0x00000102 +#define BF_TRIGGER_SYNC_INFO(inst) ((inst) + 0x00000008), 0x00000103 +#define BF_DYN_CFG_SYNC_DONE_INFO(inst) ((inst) + 0x00000008), 0x00000104 +#define BF_ONESHOT_SYNC_DONE_INFO(inst) ((inst) + 0x00000008), 0x00000105 +#define BF_MANUAL_SYNC_DONE_INFO(inst) ((inst) + 0x00000008), 0x00000106 + +#define REG_TRIG_MODE_CTRL_ADDR(inst) ((inst) + 0x00000009) +#ifdef USE_PRIVATE_BF +#define BF_SOFT_OFFON_MODE_INFO(inst) ((inst) + 0x00000009), 0x00000200 +#endif /* USE_PRIVATE_BF */ +#define BF_TRIGGER_SYNC_MODE_INFO(inst) ((inst) + 0x00000009), 0x00000104 + +#define REG_SYSREF_AVERAGE_ADDR(inst) ((inst) + 0x0000000A) +#define BF_SYSREF_AVERAGE_INFO(inst) ((inst) + 0x0000000A), 0x00000300 + +#define REG_SUBCLASS_SEL_ADDR(inst) ((inst) + 0x0000000B) +#define BF_SUBCLASS_SEL_INFO(inst) ((inst) + 0x0000000B), 0x00000100 + +#ifdef USE_PRIVATE_BF +#define REG_NCO_SYNC_MS_TRIG_ADDR(inst) ((inst) + 0x0000000C) +#define BF_NCO_SYNC_MS_TRIG_INFO(inst) ((inst) + 0x0000000C), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_NCOSYNC_SYSREF_MODE_ADDR(inst) ((inst) + 0x0000000D) +#define BF_NCO_SYNC_SYSREF_MODE_TX_INFO(inst) ((inst) + 0x0000000D), 0x00000200 +#define BF_NCO_SYNC_SYSREF_MODE_RX_INFO(inst) ((inst) + 0x0000000D), 0x00000202 +#define BF_RXNCOSYNC_SYSREF_ONESHOT_INFO(inst) ((inst) + 0x0000000D), 0x00000105 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_NCOSYNC_MS_MODE_ADDR(inst) ((inst) + 0x0000000E) +#define BF_NCO_SYNC_MS_MODE_INFO(inst) ((inst) + 0x0000000E), 0x00000200 +#define BF_NCO_SYNC_MS_TRIG_SOURCE_INFO(inst) ((inst) + 0x0000000E), 0x00000202 +#define BF_NCO_SYNC_MS_EXTRA_LMFC_NUM_INFO(inst) ((inst) + 0x0000000E), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#define REG_MCS_RESET_ADDR(inst) ((inst) + 0x0000000F) +#define BF_SYNCLOGIC_RESET_INFO(inst) ((inst) + 0x0000000F), 0x00000100 +#define BF_MCSTDC_RESET_INFO(inst) ((inst) + 0x0000000F), 0x00000101 +#define BF_MBTRIM_RESET_INFO(inst) ((inst) + 0x0000000F), 0x00000102 + +#define REG_SYNCTRL_FSM_0_ADDR(inst) ((inst) + 0x00000010) +#define BF_SYNCTRL_FSM_INFO(inst) ((inst) + 0x00000010), 0x00001000 + +#define REG_SYNCTRL_FSM_1_ADDR(inst) ((inst) + 0x00000011) + +#define REG_SYNCTRL_MAN_0_ADDR(inst) ((inst) + 0x00000012) +#define BF_SYNCTRL_MAN_INFO(inst) ((inst) + 0x00000012), 0x00001000 + +#define REG_SYNCTRL_MAN_1_ADDR(inst) ((inst) + 0x00000013) + +#define REG_SYNCSTEP_INTERVAL_ADDR(inst) ((inst) + 0x00000014) +#define BF_CYCLES_BF_SYNCSTEP_INFO(inst) ((inst) + 0x00000014), 0x00000400 +#define BF_CYCLES_AF_SYNCSTEP_INFO(inst) ((inst) + 0x00000014), 0x00000404 + +#ifdef USE_PRIVATE_BF +#define REG_SYNC_DEBUG0_ADDR(inst) ((inst) + 0x00000015) +#define BF_AVRG_IN_MONITOR_EN_INFO(inst) ((inst) + 0x00000015), 0x00000100 +#define BF_AVRG_FLOW_EN_INFO(inst) ((inst) + 0x00000015), 0x00000105 +#endif /* USE_PRIVATE_BF */ + +#define REG_SYNC_DEBUG1_ADDR(inst) ((inst) + 0x00000016) +#define BF_SYNC_STATE_INFO(inst) ((inst) + 0x00000016), 0x00000300 +#ifdef USE_PRIVATE_BF +#define BF_SOFT_OFFON_STATE_INFO(inst) ((inst) + 0x00000016), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#define REG_INT_SYSREF_PERIOD_0_ADDR(inst) ((inst) + 0x00000017) +#define BF_INT_SYSREF_PERIOD_INFO(inst) ((inst) + 0x00000017), 0x00001000 + +#define REG_INT_SYSREF_PERIOD_1_ADDR(inst) ((inst) + 0x00000018) + +#define REG_TRIG_PHASE_A0_LSB_ADDR(inst) ((inst) + 0x00000019) +#define BF_TRIG_PHASE_A0_INFO(inst) ((inst) + 0x00000019), 0x00001000 + +#define REG_TRIG_PHASE_A0_MSB_ADDR(inst) ((inst) + 0x0000001A) + +#define REG_SYNC_MASK_ADC_ADDR(inst) ((inst) + 0x0000001B) +#define BF_SYNC_MASK_ADC_INFO(inst) ((inst) + 0x0000001B), 0x00000400 + +#define REG_SYNC_MASK_DAC_ADDR(inst) ((inst) + 0x0000001C) +#define BF_SYNC_MASK_DAC_INFO(inst) ((inst) + 0x0000001C), 0x00000800 + +#define REG_SYNC_MASK_AB_ADDR(inst) ((inst) + 0x0000001D) +#define BF_SYNC_MASK_ADC_AB_INFO(inst) ((inst) + 0x0000001D), 0x00000200 +#define BF_SYNC_MASK_DAC_AB_INFO(inst) ((inst) + 0x0000001D), 0x00000404 + +#define REG_TRIG_SYNC_DONE_FLAG_ADDR(inst) ((inst) + 0x0000001E) +#define BF_TRIGGER_SYNC_DONE_A0_INFO(inst) ((inst) + 0x0000001E), 0x00000100 +#define BF_TRIGGER_SYNC_DONE_A1_INFO(inst) ((inst) + 0x0000001E), 0x00000101 +#define BF_TRIGGER_SYNC_DONE_B0_INFO(inst) ((inst) + 0x0000001E), 0x00000102 +#define BF_TRIGGER_SYNC_DONE_B1_INFO(inst) ((inst) + 0x0000001E), 0x00000103 +#define BF_TRIGGER_PHASE_KOW_IND_A0_INFO(inst) ((inst) + 0x0000001E), 0x00000104 +#define BF_TRIGGER_PHASE_KOW_IND_A1_INFO(inst) ((inst) + 0x0000001E), 0x00000105 +#define BF_TRIGGER_PHASE_KOW_IND_B0_INFO(inst) ((inst) + 0x0000001E), 0x00000106 +#define BF_TRIGGER_PHASE_KOW_IND_B1_INFO(inst) ((inst) + 0x0000001E), 0x00000107 + +#define REG_MCS_C_TRIG_PIN_SEL_ADDR(inst) ((inst) + 0x0000001F) +#define BF_MCS_C_TRIG_SEL_RX_A_INFO(inst) ((inst) + 0x0000001F), 0x00000200 +#define BF_MCS_C_TRIG_SEL_RX_B_INFO(inst) ((inst) + 0x0000001F), 0x00000202 +#define BF_MCS_C_TRIG_SEL_TX_A_INFO(inst) ((inst) + 0x0000001F), 0x00000204 +#define BF_MCS_C_TRIG_SEL_TX_B_INFO(inst) ((inst) + 0x0000001F), 0x00000206 + +#define REG_MANUAL_ROT_CENTER_ADDR(inst) ((inst) + 0x00000020) +#define BF_MASTERDIV_MANUAL_ROT_INFO(inst) ((inst) + 0x00000020), 0x00000100 + +#define REG_MASTERDIV4_ROT_MAP_ADDR(inst) ((inst) + 0x00000021) +#define BF_MASTERDIV4_ROTMAP_INFO(inst) ((inst) + 0x00000021), 0x00000800 + +#define REG_TRIG_PHASE_A1_LSB_ADDR(inst) ((inst) + 0x00000022) +#define BF_TRIG_PHASE_A1_INFO(inst) ((inst) + 0x00000022), 0x00001000 + +#define REG_TRIG_PHASE_A1_MSB_ADDR(inst) ((inst) + 0x00000023) + +#define REG_TRIG_PHASE_B0_LSB_ADDR(inst) ((inst) + 0x00000024) +#define BF_TRIG_PHASE_B0_INFO(inst) ((inst) + 0x00000024), 0x00001000 + +#define REG_TRIG_PHASE_B0_MSB_ADDR(inst) ((inst) + 0x00000025) + +#define REG_TRIG_PHASE_B1_LSB_ADDR(inst) ((inst) + 0x00000026) +#define BF_TRIG_PHASE_B1_INFO(inst) ((inst) + 0x00000026), 0x00001000 + +#define REG_TRIG_PHASE_B1_MSB_ADDR(inst) ((inst) + 0x00000027) + +#define REG_MASTERDIV8_ROT_MAP_0_ADDR(inst) ((inst) + 0x0000002A) +#define BF_MASTERDIV8_ROTMAP_INFO(inst) ((inst) + 0x0000002A), 0x00001800 + +#define REG_MASTERDIV8_ROT_MAP_1_ADDR(inst) ((inst) + 0x0000002B) + +#define REG_MASTERDIV8_ROT_MAP_2_ADDR(inst) ((inst) + 0x0000002C) + +#define REG_MCS_AB_TRIG_PIN_SEL_ADDR(inst) ((inst) + 0x0000002D) +#define BF_MCS_AB_TRIG_SEL_RX_INFO(inst) ((inst) + 0x0000002D), 0x00000200 +#define BF_MCS_AB_TRIG_SEL_TX_INFO(inst) ((inst) + 0x0000002D), 0x00000202 + +#define REG_TRIG_CTRL_FOR_CONV_ADDR(inst) ((inst) + 0x0000002E) +#define BF_TRIG_SEL_CONV_INFO(inst) ((inst) + 0x0000002E), 0x00000200 +#define BF_TRIG_EN_FOR_CONV_INFO(inst) ((inst) + 0x0000002E), 0x00000104 + +#endif /* __ADI_APOLLO_BF_MCS_SYNC_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_mcs_tdc.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_mcs_tdc.h new file mode 100644 index 00000000000000..14c092e7c0b3b6 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_mcs_tdc.h @@ -0,0 +1,258 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:19 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_MCS_TDC_H__ +#define __ADI_APOLLO_BF_MCS_TDC_H__ + +/*============= D E F I N E S ==============*/ +#define MCS_TDC_MCSTOP0 0x4C001480 +#define MCS_TDC_MCSTOP1 0x4C001880 +#define MCS_TDC_MCSTOP2 0x4C001C80 + +#ifdef USE_PRIVATE_BF +#define REG_MCS_EN_CTRL_ADDR(inst) ((inst) + 0x00000000) +#define BF_TDC_EN_INFO(inst) ((inst) + 0x00000000), 0x00000100 +#define BF_DTLL_EN_INFO(inst) ((inst) + 0x00000000), 0x00000104 +#define BF_TDC_DIG_EN_INFO(inst) ((inst) + 0x00000000), 0x00000105 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_MCS_IRQ_CTRL_ADDR(inst) ((inst) + 0x00000001) +#define BF_MCS_SYSREF_IN_FSM_START_INFO(inst) ((inst) + 0x00000001), 0x00000100 +#define BF_MCS_SYSREF_IN_IRQ_RECVD_INFO(inst) ((inst) + 0x00000001), 0x00000101 +#define BF_MCS_MEASURE_DONE_INFO(inst) ((inst) + 0x00000001), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TDC_MUX_CTRL_ADDR(inst) ((inst) + 0x00000002) +#define BF_TDC_A_MUX_SEL_INFO(inst) ((inst) + 0x00000002), 0x00000300 +#define BF_TDC_B_MUX_SEL_INFO(inst) ((inst) + 0x00000002), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TDC_FREQ_CTRL_ADDR(inst) ((inst) + 0x00000003) +#define BF_TDC_FREQ_CTRL_INFO(inst) ((inst) + 0x00000003), 0x00000300 +#define BF_TDC_PN_FREQ_CTRL_MASK_INFO(inst) ((inst) + 0x00000003), 0x00000303 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_DTLL_CLK_CTRL_ADDR(inst) ((inst) + 0x00000004) +#define BF_DTLL_CLK_SEL_INFO(inst) ((inst) + 0x00000004), 0x00000100 +#define BF_DTLL_EDGE_ALIGN_EN_INFO(inst) ((inst) + 0x00000004), 0x00000101 +#define BF_DTLL_GAPPED_TRUE_PERIOD_DETECT_INFO(inst) ((inst) + 0x00000004), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_DTLL_CIC_DECIMATION_RATE_0_ADDR(inst) ((inst) + 0x00000005) +#define BF_DTLL_CIC_DECIMATION_RATE_INFO(inst) ((inst) + 0x00000005), 0x00001000 +#endif /* USE_PRIVATE_BF */ + +#define REG_DTLL_CIC_DECIMATION_RATE_1_ADDR(inst) ((inst) + 0x00000006) + +#ifdef USE_PRIVATE_BF +#define REG_MCS_RD_FSM_1_ADDR(inst) ((inst) + 0x00000007) +#define BF_MCS_SYSREF_IN_FSM_STATE_INFO(inst) ((inst) + 0x00000007), 0x00000400 +#define BF_MCS_SYSREF_OUT_FSM_STATE_INFO(inst) ((inst) + 0x00000007), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_MCS_RD_FSM_3_ADDR(inst) ((inst) + 0x00000008) +#define BF_MCS_DTLL_EDGE_ALIGN_FSM_STATE_INFO(inst) ((inst) + 0x00000008), 0x00000400 +#define BF_MCS_DTLL_EDGE_ALIGN_DONE_INFO(inst) ((inst) + 0x00000008), 0x00000104 +#define BF_MCS_SYSREF_IN_DONE_INFO(inst) ((inst) + 0x00000008), 0x00000106 +#define BF_MCS_SYSREF_OUT_DONE_INFO(inst) ((inst) + 0x00000008), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_MCS_MEAS_TDC_FAST_PERIOD_0_ADDR(inst) ((inst) + 0x00000009) +#define BF_MCS_MEAS_TDC_FAST_PERIOD_INFO(inst) ((inst) + 0x00000009), 0x00003000 +#endif /* USE_PRIVATE_BF */ + +#define REG_MCS_MEAS_TDC_FAST_PERIOD_1_ADDR(inst) ((inst) + 0x0000000A) + +#define REG_MCS_MEAS_TDC_FAST_PERIOD_2_ADDR(inst) ((inst) + 0x0000000B) + +#define REG_MCS_MEAS_TDC_FAST_PERIOD_3_ADDR(inst) ((inst) + 0x0000000C) + +#define REG_MCS_MEAS_TDC_FAST_PERIOD_4_ADDR(inst) ((inst) + 0x0000000D) + +#define REG_MCS_MEAS_TDC_FAST_PERIOD_5_ADDR(inst) ((inst) + 0x0000000E) + +#ifdef USE_PRIVATE_BF +#define REG_MCS_MEAS_TDC_SLOW_PERIOD_0_ADDR(inst) ((inst) + 0x0000000F) +#define BF_MCS_MEAS_TDC_SLOW_PERIOD_INFO(inst) ((inst) + 0x0000000F), 0x00003000 +#endif /* USE_PRIVATE_BF */ + +#define REG_MCS_MEAS_TDC_SLOW_PERIOD_1_ADDR(inst) ((inst) + 0x00000010) + +#define REG_MCS_MEAS_TDC_SLOW_PERIOD_2_ADDR(inst) ((inst) + 0x00000011) + +#define REG_MCS_MEAS_TDC_SLOW_PERIOD_3_ADDR(inst) ((inst) + 0x00000012) + +#define REG_MCS_MEAS_TDC_SLOW_PERIOD_4_ADDR(inst) ((inst) + 0x00000013) + +#define REG_MCS_MEAS_TDC_SLOW_PERIOD_5_ADDR(inst) ((inst) + 0x00000014) + +#ifdef USE_PRIVATE_BF +#define REG_MCS_MEAS_TDC_TIMEDIFF_0_ADDR(inst) ((inst) + 0x00000015) +#define BF_MCS_MEAS_TDC_TIMEDIFF_INFO(inst) ((inst) + 0x00000015), 0x00003000 +#endif /* USE_PRIVATE_BF */ + +#define REG_MCS_MEAS_TDC_TIMEDIFF_1_ADDR(inst) ((inst) + 0x00000016) + +#define REG_MCS_MEAS_TDC_TIMEDIFF_2_ADDR(inst) ((inst) + 0x00000017) + +#define REG_MCS_MEAS_TDC_TIMEDIFF_3_ADDR(inst) ((inst) + 0x00000018) + +#define REG_MCS_MEAS_TDC_TIMEDIFF_4_ADDR(inst) ((inst) + 0x00000019) + +#define REG_MCS_MEAS_TDC_TIMEDIFF_5_ADDR(inst) ((inst) + 0x0000001A) + +#ifdef USE_PRIVATE_BF +#define REG_DTLL_FINE_PH_REMAP_0_ADDR(inst) ((inst) + 0x0000001B) +#define BF_DTLL_FINE_PH_REMAP_INFO(inst) ((inst) + 0x0000001B), 0x00001000 +#endif /* USE_PRIVATE_BF */ + +#define REG_DTLL_FINE_PH_REMAP_1_ADDR(inst) ((inst) + 0x0000001C) + +#define REG_CLK_STABLE_ADDR(inst) ((inst) + 0x0000001D) +#define BF_CLK_STABLE_FLAG_INFO(inst) ((inst) + 0x0000001D), 0x00000100 + +#define REG_CK_CKR_PD_CTRL_ADDR(inst) ((inst) + 0x0000001E) +#define BF_CK_CKR_PD_COMP_CK_INFO(inst) ((inst) + 0x0000001E), 0x00000100 +#define BF_CK_CKR_PD_ENB_INFO(inst) ((inst) + 0x0000001E), 0x00000101 +#define BF_CK_CKR_PD_TRIM_INFO(inst) ((inst) + 0x0000001E), 0x00000204 + +#define REG_CK_CKR_STATUS_ADDR(inst) ((inst) + 0x0000001F) +#define BF_CK_CKR_PD_STATUS_RX_INFO(inst) ((inst) + 0x0000001F), 0x00000100 +#define BF_CK_CKR_PD_STATUS_SCR_INFO(inst) ((inst) + 0x0000001F), 0x00000104 + +#define REG_SYSREF_RX_RTERM_ADDR(inst) ((inst) + 0x00000020) +#define BF_SYSREF_RX_RTERM_PD_INFO(inst) ((inst) + 0x00000020), 0x00000100 +#define BF_SYSREF_RX_RTERM_INFO(inst) ((inst) + 0x00000020), 0x00000304 + +#define REG_SYSREF_RX_CTRL_MISC_ADDR(inst) ((inst) + 0x00000021) +#define BF_SYSREF_RX_LOW_DEG_INFO(inst) ((inst) + 0x00000021), 0x00000100 +#define BF_SYSREF_RX_LOW_VCM_INFO(inst) ((inst) + 0x00000021), 0x00000101 +#define BF_SYSREF_RX_PROT_EN_INFO(inst) ((inst) + 0x00000021), 0x00000202 +#define BF_SYSREF_RX_TX_DATA_INVERT_INFO(inst) ((inst) + 0x00000021), 0x00000104 + +#define REG_SYSREF_DELAY0_ADDR(inst) ((inst) + 0x00000022) +#define BF_SYSREF_DELAY_CTRL_INFO(inst) ((inst) + 0x00000022), 0x00000D00 + +#define REG_SYSREF_DELAY1_ADDR(inst) ((inst) + 0x00000023) + +#define REG_SYSREF_EARLY_DELAY_ADDR(inst) ((inst) + 0x00000024) +#define BF_SYSREF_EARLY_DELAY_CTRL_INFO(inst) ((inst) + 0x00000024), 0x00000200 + +#define REG_SYSREF_SUHD_STATUS_ADDR(inst) ((inst) + 0x00000030) +#define BF_SYSREF_SETUP_STATUS_INFO(inst) ((inst) + 0x00000030), 0x00000400 +#define BF_SYSREF_HOLD_STATUS_INFO(inst) ((inst) + 0x00000030), 0x00000404 + +#define REG_SERDIV_CTRL0_ADDR(inst) ((inst) + 0x00000031) +#define BF_MCS_SERDIV_EN_INFO(inst) ((inst) + 0x00000031), 0x00000100 +#define BF_MCS_SERDIV_MODE_INFO(inst) ((inst) + 0x00000031), 0x00000204 + +#define REG_SERDIV_CTRL1_ADDR(inst) ((inst) + 0x00000032) +#define BF_SER_DIVROT_INFO(inst) ((inst) + 0x00000032), 0x00000100 + +#define REG_CLK_EN_GEN_ADDR(inst) ((inst) + 0x00000033) +#define BF_CLK_REC_EN_INFO(inst) ((inst) + 0x00000033), 0x00000100 +#define BF_MCS_SH_EN_INFO(inst) ((inst) + 0x00000033), 0x00000101 +#define BF_MCS_SYNCSAMPLER_EN_INFO(inst) ((inst) + 0x00000033), 0x00000102 + +#define REG_SYSREF_EN_ALL_ADDR(inst) ((inst) + 0x00000034) +#define BF_SYSREF_EN_INFO(inst) ((inst) + 0x00000034), 0x00000100 +#define BF_SYSREF_LEVEL_INFO(inst) ((inst) + 0x00000034), 0x00000104 + +#define REG_TDC_DIV32_CTRL_ADDR(inst) ((inst) + 0x00000035) +#define BF_TDC_DIV_BYPASS_INFO(inst) ((inst) + 0x00000035), 0x00000100 +#define BF_TDC_DIV_RESETB_INFO(inst) ((inst) + 0x00000035), 0x00000104 + +#define REG_SYSREF_TRIM_OFFSET_ADDR(inst) ((inst) + 0x00000036) +#define BF_SYSREF_OFFSET_INFO(inst) ((inst) + 0x00000036), 0x00000300 +#define BF_SYSREF_TRIM_IBIAS_INFO(inst) ((inst) + 0x00000036), 0x00000204 + +#define REG_SYSREF_CTRL_MISC_ADDR(inst) ((inst) + 0x00000037) +#define BF_SYSREF_GATEOFF_OUTPUT_INFO(inst) ((inst) + 0x00000037), 0x00000100 +#define BF_SYSREF_BYP_BIAS_R_INFO(inst) ((inst) + 0x00000037), 0x00000101 +#define BF_EN_ODRV_TST_INFO(inst) ((inst) + 0x00000037), 0x00000102 + +#define REG_CKMUX_CTRL_ADDR(inst) ((inst) + 0x00000038) +#define BF_EN_CKMUX_INFO(inst) ((inst) + 0x00000038), 0x00000100 +#define BF_EN_CKMUX_XC_INFO(inst) ((inst) + 0x00000038), 0x00000204 + +#define REG_PROG_AMUX_ADDR(inst) ((inst) + 0x00000039) +#define BF_PROG_AMUX_INFO(inst) ((inst) + 0x00000039), 0x00000400 + +#define REG_CLK_PATH_SEL_ADDR(inst) ((inst) + 0x0000003A) +#define BF_CLK_PATH_SEL_INFO(inst) ((inst) + 0x0000003A), 0x00000100 + +#define REG_CKRX_SKEW_TRIM_ADDR(inst) ((inst) + 0x0000003B) +#define BF_CKRX_SKEW_TRIMP_INFO(inst) ((inst) + 0x0000003B), 0x00000400 +#define BF_CKRX_SKEW_TRIMN_INFO(inst) ((inst) + 0x0000003B), 0x00000404 + +#define REG_SH_DETECTOR_ADDR(inst) ((inst) + 0x0000003C) +#define BF_SH_BEFORE_INFO(inst) ((inst) + 0x0000003C), 0x00000200 +#define BF_SH_AFTER_INFO(inst) ((inst) + 0x0000003C), 0x00000204 + +#define REG_RDBK_SPARE_0_ADDR(inst) ((inst) + 0x0000003E) +#define BF_RDBK_SPARE0_INFO(inst) ((inst) + 0x0000003E), 0x00000800 + +#define REG_RDBK_SPARE_1_ADDR(inst) ((inst) + 0x0000003F) +#define BF_RDBK_SPARE1_INFO(inst) ((inst) + 0x0000003F), 0x00000800 + +#define REG_SPARE_0_MCS_TDC_ADDR(inst) ((inst) + 0x00000040) +#define BF_SPARE0_INFO(inst) ((inst) + 0x00000040), 0x00000800 + +#define REG_SPARE_1_MCS_TDC_ADDR(inst) ((inst) + 0x00000041) +#define BF_SPARE1_INFO(inst) ((inst) + 0x00000041), 0x00000800 + +#define REG_SPARE_2_MCS_TDC_ADDR(inst) ((inst) + 0x00000042) +#define BF_SPARE2_INFO(inst) ((inst) + 0x00000042), 0x00000800 + +#define REG_SPARE_3_MCS_TDC_ADDR(inst) ((inst) + 0x00000043) +#define BF_SPARE3_INFO(inst) ((inst) + 0x00000043), 0x00000800 + +#define REG_CKRX_SKEW_TRIM_PAD_P_ADDR(inst) ((inst) + 0x00000044) +#define BF_CKRX_SKEW_TRIM_PAD_P_INFO(inst) ((inst) + 0x00000044), 0x00000600 + +#define REG_CKRX_SKEW_TRIM_PAD_N_ADDR(inst) ((inst) + 0x00000045) +#define BF_CKRX_SKEW_TRIM_PAD_N_INFO(inst) ((inst) + 0x00000045), 0x00000600 + +#define REG_CKRX_SKEW_OTRIM_ADDR(inst) ((inst) + 0x00000046) +#define BF_CKRX_SKEW_OTRIMP_INFO(inst) ((inst) + 0x00000046), 0x00000400 +#define BF_CKRX_SKEW_OTRIMN_INFO(inst) ((inst) + 0x00000046), 0x00000404 + +#define REG_MCS_CLK_CTRL_MISC_ADDR(inst) ((inst) + 0x00000047) +#define BF_MCS_CLK_BUFF_EN_INFO(inst) ((inst) + 0x00000047), 0x00000100 +#define BF_MCS_CLK_SERDES_EN_INFO(inst) ((inst) + 0x00000047), 0x00000101 +#define BF_MCS_EN_TDC_DIV4_INFO(inst) ((inst) + 0x00000047), 0x00000104 + +#define REG_ODRV_CTRL_ADDR(inst) ((inst) + 0x00000048) +#define BF_EN_ODRV_PATH_INFO(inst) ((inst) + 0x00000048), 0x00000100 +#define BF_SEL_ODRV_INFO(inst) ((inst) + 0x00000048), 0x00000404 + +#define REG_MCS_LINK_CFG0_ADDR(inst) ((inst) + 0x00000049) +#define BF_MCS_LINK_CONFIG_INFO(inst) ((inst) + 0x00000049), 0x00001000 + +#define REG_LPU_CK_CTRL_ADDR(inst) ((inst) + 0x0000004A) +#define BF_LPU_CK_CHOP_INFO(inst) ((inst) + 0x0000004A), 0x00000100 +#define BF_LPU_CK_BUFBYPASS_INFO(inst) ((inst) + 0x0000004A), 0x00000101 +#define BF_LPU_CK_SEL_INFO(inst) ((inst) + 0x0000004A), 0x00000404 + +#define REG_MCS_LINK_CFG1_ADDR(inst) ((inst) + 0x0000004B) + +#endif /* __ADI_APOLLO_BF_MCS_TDC_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_mem_ctrl.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_mem_ctrl.h new file mode 100644 index 00000000000000..f38b1624d48171 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_mem_ctrl.h @@ -0,0 +1,439 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:20 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_MEM_CTRL_H__ +#define __ADI_APOLLO_BF_MEM_CTRL_H__ + +/*============= D E F I N E S ==============*/ +#define REG_MC_EN_CTRL_ADDR 0x4C002000 +#define BF_MC_CMD_EN_SBPI_INFO 0x4C002000, 0x00000100 +#define BF_MC_CMD_EN_USER_INFO 0x4C002000, 0x00000101 +#define BF_MC_LOAD_QSR_QRR_INFO 0x4C002000, 0x00000104 +#define BF_MC_SEL_RD_MODE_INFO 0x4C002000, 0x00000105 +#define BF_MC_SOFT_RESET_INFO 0x4C002000, 0x00000107 + +#define REG_MC_IDLE_STATUS_ADDR 0x4C002004 +#define BF_MC_CMD_STATUS_IDLE_INFO 0x4C002004, 0x00000100 + +#define REG_MC_SEL_SD_IP_CTRL_ADDR 0x4C002008 +#define BF_MC_CMD_SEL_SD_IP_OHOT_INFO 0x4C002008, 0x00000400 + +#define REG_MC_SEL_SD_IP_STATUS_ADDR 0x4C00200C +#define BF_MC_SEL_SD_IP_OHOT_INFO 0x4C00200C, 0x00000400 +#define BF_MC_CTRL_SEL_SD_IP_INFO 0x4C00200C, 0x00000107 + +#define REG_MC_OP_REQ_ADDR 0x4C002010 +#define BF_MC_OP_OTP_BOOT_REQ_INFO 0x4C002010, 0x00000100 +#define BF_MC_OP_OTP_QUAL_REQ_INFO 0x4C002010, 0x00000101 +#define BF_MC_OP_ABORT_REQ_INFO 0x4C002010, 0x00000107 + +#define REG_MC_OP_ACK_ADDR 0x4C002014 +#define BF_MC_OP_OTP_BOOT_ACK_INFO 0x4C002014, 0x00000100 +#define BF_MC_OP_OTP_QUAL_ACK_INFO 0x4C002014, 0x00000101 +#define BF_MC_OP_ABORT_ACK_INFO 0x4C002014, 0x00000107 + +#define REG_MC_SHF_REQ_ADDR 0x4C002018 +#define BF_MC_CMD_SHF_PDN_REQ_INFO 0x4C002018, 0x00000100 +#define BF_MC_CMD_SHF_RST_REQ_INFO 0x4C002018, 0x00000104 + +#define REG_MC_SHF_ACK_ADDR 0x4C00201C +#define BF_MC_CMD_SHF_PDN_ACK_INFO 0x4C00201C, 0x00000100 +#define BF_MC_CMD_SHF_PDN_RDY_INFO 0x4C00201C, 0x00000101 +#define BF_MC_CMD_SHF_RST_ACK_INFO 0x4C00201C, 0x00000104 +#define BF_MC_CMD_SHF_PWUP_RDY_INFO 0x4C00201C, 0x00000105 + +#define REG_MC_PMC_REQ_ADDR 0x4C002020 +#define BF_MC_CMD_WR_PMC_RQ_REQ_INFO 0x4C002020, 0x00000100 +#define BF_MC_CMD_RD_PMC_RQ_REQ_INFO 0x4C002020, 0x00000101 +#define BF_MC_CMD_WR_PMC_CQ_REQ_INFO 0x4C002020, 0x00000102 +#define BF_MC_CMD_RD_PMC_CQ_REQ_INFO 0x4C002020, 0x00000103 +#define BF_MC_CMD_WR_PMC_CC_REQ_INFO 0x4C002020, 0x00000104 +#define BF_MC_CMD_RD_PMC_CC_REQ_INFO 0x4C002020, 0x00000105 +#define BF_MC_CMD_PMC_OP_REQ_INFO 0x4C002020, 0x00000107 + +#define REG_MC_PMC_ACK_ADDR 0x4C002024 +#define BF_MC_CMD_WR_PMC_RQ_ACK_INFO 0x4C002024, 0x00000100 +#define BF_MC_CMD_RD_PMC_RQ_ACK_INFO 0x4C002024, 0x00000101 +#define BF_MC_CMD_WR_PMC_CQ_ACK_INFO 0x4C002024, 0x00000102 +#define BF_MC_CMD_RD_PMC_CQ_ACK_INFO 0x4C002024, 0x00000103 +#define BF_MC_CMD_WR_PMC_CC_ACK_INFO 0x4C002024, 0x00000104 +#define BF_MC_CMD_RD_PMC_CC_ACK_INFO 0x4C002024, 0x00000105 +#define BF_MC_CMD_PMC_OP_ACK_INFO 0x4C002024, 0x00000107 + +#define REG_MC_PMC_OP_STATUS_ADDR(n) (0x4C002028 + 4 * (n)) +#define BF_MC_CMD_PMC_OP_STATUS_INFO(n) (0x4C002028 + 4 * (n)), 0x00000800 + +#define REG_MC_DAP_REQ_ADDR 0x4C002038 +#define BF_MC_CMD_WR_DAP_RQ_REQ_INFO 0x4C002038, 0x00000100 +#define BF_MC_CMD_RD_DAP_RQ_REQ_INFO 0x4C002038, 0x00000101 +#define BF_MC_CMD_WR_DAP_CQ_REQ_INFO 0x4C002038, 0x00000102 +#define BF_MC_CMD_RD_DAP_CQ_REQ_INFO 0x4C002038, 0x00000103 +#define BF_MC_CMD_WR_DAP_CC_REQ_INFO 0x4C002038, 0x00000104 +#define BF_MC_CMD_RD_DAP_CC_REQ_INFO 0x4C002038, 0x00000105 +#define BF_MC_CMD_WR_DAP_DATA_REQ_INFO 0x4C002038, 0x00000108 +#define BF_MC_CMD_RD_DAP_DATA_REQ_INFO 0x4C002038, 0x00000109 +#define BF_MC_CMD_WR_DAP_ECC_REQ_INFO 0x4C002038, 0x0000010A +#define BF_MC_CMD_RD_DAP_ECC_REQ_INFO 0x4C002038, 0x0000010B +#define BF_MC_CMD_DAP_RP_REQ_INFO 0x4C002038, 0x0000010F + +#define REG_MC_DAP_ACK_ADDR 0x4C00203C +#define BF_MC_CMD_WR_DAP_RQ_ACK_INFO 0x4C00203C, 0x00000100 +#define BF_MC_CMD_RD_DAP_RQ_ACK_INFO 0x4C00203C, 0x00000101 +#define BF_MC_CMD_WR_DAP_CQ_ACK_INFO 0x4C00203C, 0x00000102 +#define BF_MC_CMD_RD_DAP_CQ_ACK_INFO 0x4C00203C, 0x00000103 +#define BF_MC_CMD_WR_DAP_CC_ACK_INFO 0x4C00203C, 0x00000104 +#define BF_MC_CMD_RD_DAP_CC_ACK_INFO 0x4C00203C, 0x00000105 +#define BF_MC_CMD_WR_DAP_DATA_ACK_INFO 0x4C00203C, 0x00000108 +#define BF_MC_CMD_RD_DAP_DATA_ACK_INFO 0x4C00203C, 0x00000109 +#define BF_MC_CMD_WR_DAP_ECC_ACK_INFO 0x4C00203C, 0x0000010A +#define BF_MC_CMD_RD_DAP_ECC_ACK_INFO 0x4C00203C, 0x0000010B +#define BF_MC_CMD_DAP_RP_ACK_INFO 0x4C00203C, 0x0000010F + +#define REG_MC_REDN_ADDR 0x4C002040 +#define BF_MC_CMD_REDN_INFO 0x4C002040, 0x00000200 + +#define REG_MC_ADDR_ADDR 0x4C002044 +#define BF_MC_CMD_ADDR_INFO 0x4C002044, 0x00002000 + +#define REG_MC_PGM_REQ_ADDR 0x4C002048 +#define BF_MC_CMD_PGM_REQ_INFO 0x4C002048, 0x00000100 +#define BF_MC_CMD_PGM_ECC_GEN_INFO 0x4C002048, 0x00000107 + +#define REG_MC_PGM_ACK_ADDR 0x4C00204C +#define BF_MC_CMD_PGM_ACK_INFO 0x4C00204C, 0x00000100 + +#define REG_MC_PGM_BUSY_STATUS_ADDR 0x4C002050 +#define BF_MC_CMD_PGM_BUSY_INFO 0x4C002050, 0x00000100 +#define BF_MC_CMD_PGM_NUMWDS_INFO 0x4C002050, 0x00000304 + +#define REG_MC_PGM_DAP_ADDR_ADDR 0x4C002054 +#define BF_MC_CMD_PGM_DAP_ADDR_INFO 0x4C002054, 0x00001800 + +#define REG_MC_PGM_DAP_DATA_ADDR 0x4C002058 +#define BF_MC_CMD_PGM_DAP_DATA_INFO 0x4C002058, 0x00002000 + +#define REG_MC_PGM_DAP_ECC_ADDR 0x4C00205C +#define BF_MC_CMD_PGM_DAP_ECC_INFO 0x4C00205C, 0x00000800 + +#define REG_MC_PGM_STATUS_ADDR 0x4C002060 +#define BF_MC_CMD_PGM_STATUS_0_INFO 0x4C002060, 0x00000800 +#define BF_MC_CMD_PGM_STATUS_1_INFO 0x4C002060, 0x00000808 +#define BF_MC_CMD_PGM_STATUS_2_INFO 0x4C002060, 0x00000810 +#define BF_MC_CMD_PGM_STATUS_3_INFO 0x4C002060, 0x00000818 + +#define REG_MC_PGM_DAP_DATA_N_ADDR(n) (0x4C002064 + 12 * (n)) +#define BF_MC_CMD_PGM_DAP_DATA_N_INFO(n) (0x4C002064 + 12 * (n)), 0x00002000 + +#define REG_MC_PGM_DAP_ECC_N_ADDR(n) (0x4C002068 + 12 * (n)) +#define BF_MC_CMD_PGM_DAP_ECC_N_INFO(n) (0x4C002068 + 12 * (n)), 0x00000800 + +#define REG_MC_PGM_STATUS_N_ADDR(n) (0x4C00206C + 12 * (n)) +#define BF_MC_CMD_PGM_STATUS_N_0_INFO(n) (0x4C00206C + 12 * (n)), 0x00000800 +#define BF_MC_CMD_PGM_STATUS_N_1_INFO(n) (0x4C00206C + 12 * (n)), 0x00000808 +#define BF_MC_CMD_PGM_STATUS_N_2_INFO(n) (0x4C00206C + 12 * (n)), 0x00000810 +#define BF_MC_CMD_PGM_STATUS_N_3_INFO(n) (0x4C00206C + 12 * (n)), 0x00000818 + +#define REG_MC_OTP_REQ_ADDR 0x4C002094 +#define BF_MC_CMD_OTP_PDN_REQ_INFO 0x4C002094, 0x00000100 +#define BF_MC_CMD_OTP_PWUP_REQ_INFO 0x4C002094, 0x00000101 + +#define REG_MC_OTP_ACK_ADDR 0x4C002098 +#define BF_MC_CMD_OTP_PDN_ACK_INFO 0x4C002098, 0x00000100 +#define BF_MC_CMD_OTP_PWUP_ACK_INFO 0x4C002098, 0x00000101 +#define BF_MC_CMD_OTP_PDN_RDY_INFO 0x4C002098, 0x00000104 + +#define REG_MC_OTP_RD_REQ_ADDR 0x4C00209C +#define BF_MC_CMD_OTP_RD_REQ_INFO 0x4C00209C, 0x00000100 +#define BF_MC_CMD_OTP_BURST_RD_EN_INFO 0x4C00209C, 0x00000107 +#define BF_MC_OTP_RD_ECC_BYPASS_INFO 0x4C00209C, 0x00000110 +#define BF_MC_OTP_RD_ECC_DISABLE_INFO 0x4C00209C, 0x00000111 +#define BF_MC_OTP_RD_ECC_GEN_INFO 0x4C00209C, 0x00000112 +#define BF_MC_OTP_RD_ECC_TEST_INFO 0x4C00209C, 0x00000113 + +#define REG_MC_OTP_RD_ACK_ADDR 0x4C0020A0 +#define BF_MC_CMD_OTP_RD_ACK_INFO 0x4C0020A0, 0x00000100 + +#define REG_MC_OTP_BURST_RD_COUNT_ADDR 0x4C0020A4 +#define BF_MC_CMD_OTP_BURST_RD_COUNT_INFO 0x4C0020A4, 0x00002000 + +#define REG_MC_OTP_RD_WIDTH_CTRL_ADDR 0x4C0020A8 +#define BF_MC_OTP_RD_PULSE_WIDTH_INFO 0x4C0020A8, 0x00000500 +#define BF_MC_OTP_RD_RECOV_WIDTH_INFO 0x4C0020A8, 0x00000508 + +#define REG_MC_OTP_RD_DATA_VALID_ADDR 0x4C0020AC +#define BF_MC_OTP_RD_DATA_VALID_INFO 0x4C0020AC, 0x00000100 + +#define REG_MC_OTP_RD_DATA_ADDR 0x4C0020B0 +#define BF_MC_OTP_RD_DATA_INFO 0x4C0020B0, 0x00002000 + +#define REG_MC_OTP_RD_ECC_ADDR 0x4C0020B4 +#define BF_MC_OTP_RD_ECC_INFO 0x4C0020B4, 0x00000800 +#define BF_MC_OTP_RD_NO_ERR_FLAG_INFO 0x4C0020B4, 0x00000108 +#define BF_MC_OTP_RD_SEC_FLAG_INFO 0x4C0020B4, 0x00000109 +#define BF_MC_OTP_RD_DED_FLAG_INFO 0x4C0020B4, 0x0000010A + +#define REG_MC_OTP_RD_ADDR_STATUS_ADDR 0x4C0020B8 +#define BF_MC_OTP_RD_ADDR_STATUS_INFO 0x4C0020B8, 0x00001800 +#define BF_MC_OTP_RD_SEL_SD_IP_OHOT_INFO 0x4C0020B8, 0x00000418 + +#define REG_MC_OTP_RD_DATA_VALID_N_ADDR(n) (0x4C0020BC + 16 * (n)) +#define BF_MC_OTP_RD_DATA_VALID_N_INFO(n) (0x4C0020BC + 16 * (n)), 0x00000100 + +#define REG_MC_OTP_RD_DATA_N_ADDR(n) (0x4C0020C0 + 16 * (n)) +#define BF_MC_OTP_RD_DATA_N_INFO(n) (0x4C0020C0 + 16 * (n)), 0x00002000 + +#define REG_MC_OTP_RD_ECC_N_ADDR(n) (0x4C0020C4 + 16 * (n)) +#define BF_MC_OTP_RD_ECC_N_INFO(n) (0x4C0020C4 + 16 * (n)), 0x00000800 +#define BF_MC_OTP_RD_NO_ERR_FLAG_N_INFO(n) (0x4C0020C4 + 16 * (n)), 0x00000108 +#define BF_MC_OTP_RD_SEC_FLAG_N_INFO(n) (0x4C0020C4 + 16 * (n)), 0x00000109 +#define BF_MC_OTP_RD_DED_FLAG_N_INFO(n) (0x4C0020C4 + 16 * (n)), 0x0000010A + +#define REG_MC_OTP_RD_ADDR_STATUS_N_ADDR(n) (0x4C0020C8 + 16 * (n)) +#define BF_MC_OTP_RD_ADDR_STATUS_N_INFO(n) (0x4C0020C8 + 16 * (n)), 0x00001800 + +#define REG_MC_ECC_CTRL_ADDR 0x4C0020FC +#define BF_MC_ECC_DISABLE_INFO 0x4C0020FC, 0x00000100 +#define BF_MC_ECC_GEN_INFO 0x4C0020FC, 0x00000101 +#define BF_MC_ECC_TEST_INFO 0x4C0020FC, 0x00000102 + +#define REG_MC_ECC_FLAGS_ADDR 0x4C002100 +#define BF_MC_ECC_NO_ERR_FLAG_INFO 0x4C002100, 0x00000100 +#define BF_MC_ECC_SEC_FLAG_INFO 0x4C002100, 0x00000101 +#define BF_MC_ECC_DED_FLAG_INFO 0x4C002100, 0x00000102 + +#define REG_MC_ECC_INPUT_DATA_ADDR 0x4C002104 +#define BF_MC_ECC_REGMAP_DATA_INFO 0x4C002104, 0x00002000 + +#define REG_MC_ECC_INPUT_ECC_ADDR 0x4C002108 +#define BF_MC_ECC_REGMAP_ECC_INFO 0x4C002108, 0x00000800 + +#define REG_MC_ECC_OUTPUT_DATA_ADDR 0x4C00210C +#define BF_MC_ECC_CORRECTED_DATA_INFO 0x4C00210C, 0x00002000 + +#define REG_MC_ECC_OUTPUT_ECC_ADDR 0x4C002110 +#define BF_MC_ECC_CORRECTED_ECC_INFO 0x4C002110, 0x00000800 + +#define REG_MC_CRC_CTRL_ADDR 0x4C002114 +#define BF_MC_CRC_ENABLE_INFO 0x4C002114, 0x00000100 +#define BF_MC_CRC_RESTART_INFO 0x4C002114, 0x00000101 +#define BF_MC_CRC_ERR_COND_SEL_INFO 0x4C002114, 0x00000102 + +#define REG_MC_CRC_NUM_READS_ADDR 0x4C002118 +#define BF_MC_CRC_NUM_READS_INFO 0x4C002118, 0x00002000 + +#define REG_MC_CRC_CHECKSUM_ADDR 0x4C00211C +#define BF_MC_CRC_CHECKSUM_INFO 0x4C00211C, 0x00002000 + +#define REG_MC_CRC_FLAGS_ADDR 0x4C002120 +#define BF_MC_CRC_NO_ERR_FLAG_INFO 0x4C002120, 0x00000100 +#define BF_MC_CRC_SEC_FLAG_INFO 0x4C002120, 0x00000101 +#define BF_MC_CRC_DED_FLAG_INFO 0x4C002120, 0x00000102 + +#define REG_MC_CRC_ERR_ADDR_ADDR 0x4C002124 +#define BF_MC_CRC_ERR_ADDR_INFO 0x4C002124, 0x00001800 +#define BF_MC_CRC_ERR_SEL_SD_IP_OHOT_INFO 0x4C002124, 0x00000418 + +#define REG_MC_SBPI_PMC_CQ_ADDR 0x4C002130 +#define BF_MC_SBPI_PMC_CQ_REGS_0_INFO 0x4C002130, 0x00000800 +#define BF_MC_SBPI_PMC_CQ_REGS_1_INFO 0x4C002130, 0x00000808 + +#define REG_MC_SBPI_PMC_RQ0_ADDR 0x4C002134 +#define BF_MC_SBPI_PMC_RQ_REGS_0_INFO 0x4C002134, 0x00000800 +#define BF_MC_SBPI_PMC_RQ_REGS_1_INFO 0x4C002134, 0x00000808 +#define BF_MC_SBPI_PMC_RQ_REGS_2_INFO 0x4C002134, 0x00000810 +#define BF_MC_SBPI_PMC_RQ_REGS_3_INFO 0x4C002134, 0x00000818 + +#define REG_MC_SBPI_PMC_RQ1_ADDR 0x4C002138 +#define BF_MC_SBPI_PMC_RQ_REGS_4_INFO 0x4C002138, 0x00000800 +#define BF_MC_SBPI_PMC_RQ_REGS_5_INFO 0x4C002138, 0x00000808 +#define BF_MC_SBPI_PMC_RQ_REGS_6_INFO 0x4C002138, 0x00000810 +#define BF_MC_SBPI_PMC_RQ_REGS_7_INFO 0x4C002138, 0x00000818 + +#define REG_MC_SBPI_PMC_RQ2_ADDR 0x4C00213C +#define BF_MC_SBPI_PMC_RQ_REGS_8_INFO 0x4C00213C, 0x00000800 +#define BF_MC_SBPI_PMC_RQ_REGS_9_INFO 0x4C00213C, 0x00000808 +#define BF_MC_SBPI_PMC_RQ_REGS_10_INFO 0x4C00213C, 0x00000810 +#define BF_MC_SBPI_PMC_RQ_REGS_11_INFO 0x4C00213C, 0x00000818 + +#define REG_MC_SBPI_PMC_CC_ADDR 0x4C002140 +#define BF_MC_SBPI_PMC_CC_REGS_0_INFO 0x4C002140, 0x00000800 + +#define REG_MC_SBPI_DAP_CQ_ADDR 0x4C002144 +#define BF_MC_SBPI_DAP_CQ_REGS_0_INFO 0x4C002144, 0x00000800 +#define BF_MC_SBPI_DAP_CQ_REGS_1_INFO 0x4C002144, 0x00000808 + +#define REG_MC_SBPI_DAP_RQ0_ADDR 0x4C002148 +#define BF_MC_SBPI_DAP_RQ_REGS_0_INFO 0x4C002148, 0x00000800 +#define BF_MC_SBPI_DAP_RQ_REGS_1_INFO 0x4C002148, 0x00000808 +#define BF_MC_SBPI_DAP_RQ_REGS_2_INFO 0x4C002148, 0x00000810 +#define BF_MC_SBPI_DAP_RQ_REGS_3_INFO 0x4C002148, 0x00000818 + +#define REG_MC_SBPI_DAP_RQ1_ADDR 0x4C00214C +#define BF_MC_SBPI_DAP_RQ_REGS_4_INFO 0x4C00214C, 0x00000800 +#define BF_MC_SBPI_DAP_RQ_REGS_5_INFO 0x4C00214C, 0x00000808 +#define BF_MC_SBPI_DAP_RQ_REGS_6_INFO 0x4C00214C, 0x00000810 +#define BF_MC_SBPI_DAP_RQ_REGS_7_INFO 0x4C00214C, 0x00000818 + +#define REG_MC_SBPI_DAP_RQ2_ADDR 0x4C002150 +#define BF_MC_SBPI_DAP_RQ_REGS_8_INFO 0x4C002150, 0x00000800 +#define BF_MC_SBPI_DAP_RQ_REGS_9_INFO 0x4C002150, 0x00000808 +#define BF_MC_SBPI_DAP_RQ_REGS_10_INFO 0x4C002150, 0x00000810 +#define BF_MC_SBPI_DAP_RQ_REGS_11_INFO 0x4C002150, 0x00000818 + +#define REG_MC_SBPI_DAP_CC_ADDR 0x4C002154 +#define BF_MC_SBPI_DAP_CC_REGS_0_INFO 0x4C002154, 0x00000800 + +#define REG_MC_SBPI_DAP_DATA_ADDR 0x4C002158 +#define BF_MC_SBPI_DAP_DATA_REGS_0_INFO 0x4C002158, 0x00000800 +#define BF_MC_SBPI_DAP_DATA_REGS_1_INFO 0x4C002158, 0x00000808 +#define BF_MC_SBPI_DAP_DATA_REGS_2_INFO 0x4C002158, 0x00000810 +#define BF_MC_SBPI_DAP_DATA_REGS_3_INFO 0x4C002158, 0x00000818 + +#define REG_MC_SBPI_DAP_ECC_ADDR 0x4C00215C +#define BF_MC_SBPI_DAP_ECC_REGS_0_INFO 0x4C00215C, 0x00000800 + +#define REG_MC_SBPI_DAP_DATA_N_ADDR(n) (0x4C002160 + 8 * (n)) +#define BF_MC_SBPI_DAP_DATA_REGS_N_0_INFO(n) (0x4C002160 + 8 * (n)), 0x00000800 +#define BF_MC_SBPI_DAP_DATA_REGS_N_1_INFO(n) (0x4C002160 + 8 * (n)), 0x00000808 +#define BF_MC_SBPI_DAP_DATA_REGS_N_2_INFO(n) (0x4C002160 + 8 * (n)), 0x00000810 +#define BF_MC_SBPI_DAP_DATA_REGS_N_3_INFO(n) (0x4C002160 + 8 * (n)), 0x00000818 + +#define REG_MC_SBPI_DAP_ECC_N_ADDR(n) (0x4C002164 + 8 * (n)) +#define BF_MC_SBPI_DAP_ECC_REGS_N_0_INFO(n) (0x4C002164 + 8 * (n)), 0x00000800 + +#define REG_MC_SBPI_RD_REGS0_ADDR(n) (0x4C002180 + 16 * (n)) +#define BF_MC_SBPI_RD_REGS_0_INFO(n) (0x4C002180 + 16 * (n)), 0x00000800 +#define BF_MC_SBPI_RD_REGS_1_INFO(n) (0x4C002180 + 16 * (n)), 0x00000808 +#define BF_MC_SBPI_RD_REGS_2_INFO(n) (0x4C002180 + 16 * (n)), 0x00000810 +#define BF_MC_SBPI_RD_REGS_3_INFO(n) (0x4C002180 + 16 * (n)), 0x00000818 + +#define REG_MC_SBPI_RD_REGS1_ADDR(n) (0x4C002184 + 16 * (n)) +#define BF_MC_SBPI_RD_REGS_4_INFO(n) (0x4C002184 + 16 * (n)), 0x00000800 +#define BF_MC_SBPI_RD_REGS_5_INFO(n) (0x4C002184 + 16 * (n)), 0x00000808 +#define BF_MC_SBPI_RD_REGS_6_INFO(n) (0x4C002184 + 16 * (n)), 0x00000810 +#define BF_MC_SBPI_RD_REGS_7_INFO(n) (0x4C002184 + 16 * (n)), 0x00000818 + +#define REG_MC_SBPI_RD_REGS2_ADDR(n) (0x4C002188 + 16 * (n)) +#define BF_MC_SBPI_RD_REGS_8_INFO(n) (0x4C002188 + 16 * (n)), 0x00000800 +#define BF_MC_SBPI_RD_REGS_9_INFO(n) (0x4C002188 + 16 * (n)), 0x00000808 +#define BF_MC_SBPI_RD_REGS_10_INFO(n) (0x4C002188 + 16 * (n)), 0x00000810 +#define BF_MC_SBPI_RD_REGS_11_INFO(n) (0x4C002188 + 16 * (n)), 0x00000818 + +#define REG_MC_SBPI_RD_REGS3_ADDR(n) (0x4C00218C + 16 * (n)) +#define BF_MC_SBPI_RD_REGS_12_INFO(n) (0x4C00218C + 16 * (n)), 0x00000800 +#define BF_MC_SBPI_RD_REGS_13_INFO(n) (0x4C00218C + 16 * (n)), 0x00000808 +#define BF_MC_SBPI_RD_REGS_14_INFO(n) (0x4C00218C + 16 * (n)), 0x00000810 +#define BF_MC_SBPI_RD_REGS_15_INFO(n) (0x4C00218C + 16 * (n)), 0x00000818 + +#define REG_SD_SHF_CTRL_ADDR 0x4C002200 +#define BF_SD_SHF_OVERRIDE_INFO 0x4C002200, 0x00000100 +#define BF_SD_SHF_SEL_SD_IP_OHOT_INFO 0x4C002200, 0x00000408 + +#define REG_SD_SHF_SBPI_CTRL_ADDR 0x4C002204 +#define BF_SD_SHF_SBPI_CKE_INFO 0x4C002204, 0x00000100 +#define BF_SD_SHF_SBPI_CS_INFO 0x4C002204, 0x00000101 +#define BF_SD_SHF_SBPI_SP_INFO 0x4C002204, 0x00000102 +#define BF_SD_SHF_SBPI_CLOCK_PULSE_INFO 0x4C002204, 0x00000104 +#define BF_SD_SHF_SBPI_SOFT_RESET_INFO 0x4C002204, 0x00000107 + +#define REG_SD_SHF_SBPI_MOSI_ADDR 0x4C002208 +#define BF_SD_SHF_SBPI_MOSI_INFO 0x4C002208, 0x00000800 + +#define REG_SD_SHF_SBPI_MISO_ADDR(n) (0x4C00220C + 8 * (n)) +#define BF_SD_SHF_SBPI_MISO_INFO(n) (0x4C00220C + 8 * (n)), 0x00000800 + +#define REG_SD_SHF_SBPI_STATUS_ADDR(n) (0x4C002210 + 8 * (n)) +#define BF_SD_SHF_SBPI_FLAG_INFO(n) (0x4C002210 + 8 * (n)), 0x00000100 + +#define REG_SD_SHF_USER_CTRL_ADDR 0x4C00222C +#define BF_SD_SHF_USER_CK_INFO 0x4C00222C, 0x00000100 +#define BF_SD_SHF_USER_SEL_INFO 0x4C00222C, 0x00000101 +#define BF_SD_SHF_USER_PD_INFO 0x4C00222C, 0x00000102 +#define BF_SD_SHF_USER_DCTRL_INFO 0x4C00222C, 0x00000103 + +#define REG_SD_SHF_USER_ADDR_ADDR 0x4C002230 +#define BF_SD_SHF_USER_ADDR_INFO 0x4C002230, 0x00001800 + +#define REG_MC_BOOT_CTRL_STATUS_ADDR 0x4C002234 +#define BF_MC_BOOT_REDN_INFO 0x4C002234, 0x00000200 +#define BF_MC_BOOT_ECCDIS_INFO 0x4C002234, 0x00000102 +#define BF_MC_FUSED_PGM_LOCK_INFO 0x4C002234, 0x00000106 +#define BF_MC_FUSED_QUAL_EN_INFO 0x4C002234, 0x00000107 + +#define REG_MC_OP_FSM_STATUS_ADDR 0x4C002238 +#define BF_MC_OP_FSM_BUSY_INFO 0x4C002238, 0x00000100 +#define BF_MC_OP_OTP_RD_READY_INFO 0x4C002238, 0x00000101 +#define BF_MC_OP_ABORTED_FLAG_INFO 0x4C002238, 0x00000103 +#define BF_MC_OP_FSM_STATE_INFO 0x4C002238, 0x00000408 +#define BF_MC_OP_FSM_STATUS_INFO 0x4C002238, 0x0000090C + +#define REG_MC_CMD_FSM_STATUS_ADDR 0x4C00223C +#define BF_MC_CMD_STATUS_FSM_STATE_INFO 0x4C00223C, 0x00000800 +#define BF_MC_CMD_PMC_OP_INVALID_INFO 0x4C00223C, 0x00000108 + +#define REG_MC_IF_FSM_STATUS_ADDR(n) (0x4C002240 + 4 * (n)) +#define BF_MC_SBPI_STATUS_FSM_STATE_INFO(n) (0x4C002240 + 4 * (n)), 0x00000400 +#define BF_MC_USER_STATUS_FSM_STATE_INFO(n) (0x4C002240 + 4 * (n)), 0x00000408 + +#define REG_SD_SHF_Q_ADDR(n) (0x4C002260 + 24 * (n)) +#define BF_SD_SHF_Q_INFO(n) (0x4C002260 + 24 * (n)), 0x00002000 + +#define REG_SD_SHF_QP_ADDR(n) (0x4C002264 + 24 * (n)) +#define BF_SD_SHF_QP_INFO(n) (0x4C002264 + 24 * (n)), 0x00000800 + +#define REG_SD_SHF_QSR_ADDR(n) (0x4C002268 + 24 * (n)) +#define BF_SD_SHF_QSR_INFO(n) (0x4C002268 + 24 * (n)), 0x00002000 + +#define REG_SD_SHF_QSRP_ADDR(n) (0x4C00226C + 24 * (n)) +#define BF_SD_SHF_QSRP_INFO(n) (0x4C00226C + 24 * (n)), 0x00000800 + +#define REG_SD_SHF_QRR_ADDR(n) (0x4C002270 + 24 * (n)) +#define BF_SD_SHF_QRR_INFO(n) (0x4C002270 + 24 * (n)), 0x00002000 + +#define REG_SD_SHF_QRRP_ADDR(n) (0x4C002274 + 24 * (n)) +#define BF_SD_SHF_QRRP_INFO(n) (0x4C002274 + 24 * (n)), 0x00000800 + +#define REG_SD_IPS_STATUS_ADDR(n) (0x4C0022C4 + 8 * (n)) +#define BF_SD_IPS_SHUTD_INFO(n) (0x4C0022C4 + 8 * (n)), 0x00000100 +#define BF_SD_IPS_VRREN_INFO(n) (0x4C0022C4 + 8 * (n)), 0x00000101 +#define BF_SD_IPS_VQQEN_INFO(n) (0x4C0022C4 + 8 * (n)), 0x00000102 +#define BF_SD_IPS_VPPEN_INFO(n) (0x4C0022C4 + 8 * (n)), 0x00000103 + +#define REG_SD_IPS_MRR_ADDR(n) (0x4C0022C8 + 8 * (n)) +#define BF_SD_IPS_MRR_INFO(n) (0x4C0022C8 + 8 * (n)), 0x00002000 + +#define REG_SD_NVM_MR_ADDR(n) (0x4C0022E4 + 24 * (n)) +#define BF_SD_NVM_MR_INFO(n) (0x4C0022E4 + 24 * (n)), 0x00002000 + +#define REG_SD_NVM_ADDR_ADDR(n) (0x4C0022E8 + 24 * (n)) +#define BF_SD_NVM_A_INFO(n) (0x4C0022E8 + 24 * (n)), 0x00001800 + +#define REG_SD_NVM_Q_ADDR(n) (0x4C0022EC + 24 * (n)) +#define BF_SD_NVM_Q_INFO(n) (0x4C0022EC + 24 * (n)), 0x00002000 + +#define REG_SD_NVM_QP_ADDR(n) (0x4C0022F0 + 24 * (n)) +#define BF_SD_NVM_QP_INFO(n) (0x4C0022F0 + 24 * (n)), 0x00000800 + +#define REG_SD_NVM_NQ_ADDR(n) (0x4C0022F4 + 24 * (n)) +#define BF_SD_NVM_NQ_INFO(n) (0x4C0022F4 + 24 * (n)), 0x00002000 + +#define REG_SD_NVM_NQP_ADDR(n) (0x4C0022F8 + 24 * (n)) +#define BF_SD_NVM_NQP_INFO(n) (0x4C0022F8 + 24 * (n)), 0x00000800 + +#define REG_MC_REGMAP_CTRL_ADDR 0x4C0023F0 +#define BF_MC_REGMAP_SOFT_RESET_INFO 0x4C0023F0, 0x00000100 +#define BF_MC_REGMAP_REQ_CLR_N_INFO 0x4C0023F0, 0x00000101 + +#endif /* __ADI_APOLLO_BF_MEM_CTRL_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_pll_mem_map.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_pll_mem_map.h new file mode 100644 index 00000000000000..f27f2b48fa5a49 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_pll_mem_map.h @@ -0,0 +1,1074 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:19 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_PLL_MEM_MAP_H__ +#define __ADI_APOLLO_BF_PLL_MEM_MAP_H__ + +/*============= D E F I N E S ==============*/ +#define SERDES_PLL 0x4C003000 +#define CKPLL 0x4C001700 + +#ifdef USE_PRIVATE_BF +#define REG_SYNTH_RESETB_ADDR(inst) ((inst) + 0x00000000) +#define BF_VCO_CAL_LOGIC_RESETB_INFO(inst) ((inst) + 0x00000000), 0x00000100 +#define BF_VCO_TC_CAL_RESETB_INFO(inst) ((inst) + 0x00000000), 0x00000101 +#define BF_LO_SYNC_RESETB_INFO(inst) ((inst) + 0x00000000), 0x00000102 +#define BF_MCS_RESETB_INFO(inst) ((inst) + 0x00000000), 0x00000103 +#define BF_LOCK_DETECT_RESETB_INFO(inst) ((inst) + 0x00000000), 0x00000104 +#define BF_SDM_RESETB_INFO(inst) ((inst) + 0x00000000), 0x00000105 +#define BF_AB_COUNTER_RESETB_INFO(inst) ((inst) + 0x00000000), 0x00000106 +#define BF_REF_CLK_DIVIDER_RESETB_INFO(inst) ((inst) + 0x00000000), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_MISC_PD_ADDR(inst) ((inst) + 0x00000001) +#define BF_VCO_LDO_PD_INFO(inst) ((inst) + 0x00000001), 0x00000100 +#define BF_VCOTC_DAC_PD_INFO(inst) ((inst) + 0x00000001), 0x00000101 +#define BF_PRESCALER_PD_INFO(inst) ((inst) + 0x00000001), 0x00000102 +#define BF_PFD_RESETB_INFO(inst) ((inst) + 0x00000001), 0x00000103 +#define BF_REF_CLK_DIVIDER_PD_INFO(inst) ((inst) + 0x00000001), 0x00000104 +#define BF_CP_LEVELDET_PD_INFO(inst) ((inst) + 0x00000001), 0x00000105 +#define BF_SDM_PD_INFO(inst) ((inst) + 0x00000001), 0x00000106 +#define BF_SYNTH_PD_INFO(inst) ((inst) + 0x00000001), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_MISC_PD_KILLS_ADDR(inst) ((inst) + 0x00000002) +#define BF_KILLRDIV_TEMPS_INFO(inst) ((inst) + 0x00000002), 0x00000100 +#define BF_VCOBUF_TO_PS_PD_INFO(inst) ((inst) + 0x00000002), 0x00000101 +#define BF_CP_OPAMP_PD_INFO(inst) ((inst) + 0x00000002), 0x00000102 +#define BF_CLKOUT_BUF_PD_INFO(inst) ((inst) + 0x00000002), 0x00000103 +#define BF_CP_RESETB_INFO(inst) ((inst) + 0x00000002), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_LOGEN_CLKGEN_LOSYNC_PD_ADDR(inst) ((inst) + 0x00000003) +#define BF_CLKGEN_SERDES_OUTBUF_PD_INFO(inst) ((inst) + 0x00000003), 0x00000100 +#define BF_RF_EXTLO_OUT_PD_INFO(inst) ((inst) + 0x00000003), 0x00000101 +#define BF_LOGEN_PD_INFO(inst) ((inst) + 0x00000003), 0x00000104 +#define BF_RF_EXTLO_IN_PD_INFO(inst) ((inst) + 0x00000003), 0x00000105 +#define BF_LO_SYNC_SAMPLER_FLOPS_PD_INFO(inst) ((inst) + 0x00000003), 0x00000106 +#define BF_LO_SYNC_SAMPLER_LO_INPUT_BUF_PD_INFO(inst) ((inst) + 0x00000003), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_DIVIDER_INT_BYTE0_ADDR(inst) ((inst) + 0x00000004) +#define BF_SDM_INT_INFO(inst) ((inst) + 0x00000004), 0x00000B00 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_DIVIDER_INT_BYTE1_ADDR(inst) ((inst) + 0x00000005) +#define BF_READ_EFFECT_FTW_INFO(inst) ((inst) + 0x00000005), 0x00000103 +#define BF_FB_CLOCK_ADV_INFO(inst) ((inst) + 0x00000005), 0x00000204 +#define BF_BYP_LOAD_DELAY_INFO(inst) ((inst) + 0x00000005), 0x00000106 +#define BF_SDM_BYP_INFO(inst) ((inst) + 0x00000005), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_DIVIDER_FRAC_BYTE0_ADDR(inst) ((inst) + 0x00000006) +#define BF_SDM_FRAC_INFO(inst) ((inst) + 0x00000006), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_DIVIDER_FRAC_BYTE1_ADDR(inst) ((inst) + 0x00000007) + +#define REG_DIVIDER_FRAC_BYTE2_ADDR(inst) ((inst) + 0x00000008) + +#define REG_DIVIDER_FRAC_BYTE3_ADDR(inst) ((inst) + 0x00000009) + +#ifdef USE_PRIVATE_BF +#define REG_CHARGE_PUMP_CONFIG0_ADDR(inst) ((inst) + 0x0000000A) +#define BF_CP_I_INFO(inst) ((inst) + 0x0000000A), 0x00000500 +#define BF_VT_FORCE_INFO(inst) ((inst) + 0x0000000A), 0x00000106 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_PFD_CTL0_ADDR(inst) ((inst) + 0x0000000B) +#define BF_PFD_CLOCK_EDGE_INFO(inst) ((inst) + 0x0000000B), 0x00000100 +#define BF_PFD_FORCEUPDN_INFO(inst) ((inst) + 0x0000000B), 0x00000204 +#define BF_PFD_KILLUPDN_INFO(inst) ((inst) + 0x0000000B), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_PFD_CTL1_ADDR(inst) ((inst) + 0x0000000C) +#define BF_PFD_DELAY_INFO(inst) ((inst) + 0x0000000C), 0x00000200 +#define BF_PFD_DISABLE_ASYM_INFO(inst) ((inst) + 0x0000000C), 0x00000102 +#define BF_PFD_SLIPDN_INFO(inst) ((inst) + 0x0000000C), 0x00000104 +#define BF_PFD_SLIPUP_INFO(inst) ((inst) + 0x0000000C), 0x00000105 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CP_CAL_CTL0_ADDR(inst) ((inst) + 0x0000000D) +#define BF_CP_CAL_INIT_INFO(inst) ((inst) + 0x0000000D), 0x00000100 +#define BF_CP_CAL_EN_INFO(inst) ((inst) + 0x0000000D), 0x00000101 +#define BF_CP_TEST_INFO(inst) ((inst) + 0x0000000D), 0x00000202 +#define BF_CP_CAL_CLK_DIVIDE_INFO(inst) ((inst) + 0x0000000D), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CP_CAL_CTL1_ADDR(inst) ((inst) + 0x0000000E) +#define BF_CP_F_CAL_BITS_INFO(inst) ((inst) + 0x0000000E), 0x00000600 +#define BF_CP_F_CAL_INFO(inst) ((inst) + 0x0000000E), 0x00000106 +#define BF_CP_CAL_VALID_INFO(inst) ((inst) + 0x0000000E), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CP_LVL_DET_TC_ADDR(inst) ((inst) + 0x0000000F) +#define BF_CP_VLEVEL_LOW_TC_INFO(inst) ((inst) + 0x0000000F), 0x00000400 +#define BF_CP_VLEVEL_HIGH_TC_INFO(inst) ((inst) + 0x0000000F), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CP_LVL_DET_TC2_ADDR(inst) ((inst) + 0x00000010) +#define BF_CP_VLEVEL_HIGH_FLAG_INFO(inst) ((inst) + 0x00000010), 0x00000400 +#define BF_CP_VLEVEL_LOW_FLAG_INFO(inst) ((inst) + 0x00000010), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CP_LVL_DET_CTL_STAT_ADDR(inst) ((inst) + 0x00000011) +#define BF_CP_AUXADC_HYST_TC_INFO(inst) ((inst) + 0x00000011), 0x00000200 +#define BF_CP_AUXADC_HYST_ON_TC_INFO(inst) ((inst) + 0x00000011), 0x00000102 +#define BF_CP_SEL_ADC_TC_INFO(inst) ((inst) + 0x00000011), 0x00000103 +#define BF_CP_OVERRANGE_LOW_TC_INFO(inst) ((inst) + 0x00000011), 0x00000104 +#define BF_CP_OVERRANGE_HIGH_TC_INFO(inst) ((inst) + 0x00000011), 0x00000105 +#define BF_CP_OVERRANGE_HIGH_FLAG_INFO(inst) ((inst) + 0x00000011), 0x00000106 +#define BF_CP_OVERRANGE_LOW_FLAG_INFO(inst) ((inst) + 0x00000011), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_LF_C2_ADDR(inst) ((inst) + 0x00000012) +#define BF_LF_C2_INFO(inst) ((inst) + 0x00000012), 0x00000600 +#define BF_LF_BYPASS_C2_INFO(inst) ((inst) + 0x00000012), 0x00000106 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_LF_C1_ADDR(inst) ((inst) + 0x00000013) +#define BF_LF_C1_INFO(inst) ((inst) + 0x00000013), 0x00000600 +#define BF_LF_BYPASS_C1_INFO(inst) ((inst) + 0x00000013), 0x00000106 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_LF_R1_ADDR(inst) ((inst) + 0x00000014) +#define BF_LF_R1_INFO(inst) ((inst) + 0x00000014), 0x00000600 +#define BF_LF_BYPASS_R1_INFO(inst) ((inst) + 0x00000014), 0x00000106 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_LF_C3_ADDR(inst) ((inst) + 0x00000015) +#define BF_LF_C3_INFO(inst) ((inst) + 0x00000015), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_LF_R3_ADDR(inst) ((inst) + 0x00000016) +#define BF_LF_R3_INFO(inst) ((inst) + 0x00000016), 0x00000600 +#define BF_LF_BYPASS_R3_INFO(inst) ((inst) + 0x00000016), 0x00000106 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_VCO_ALC_FREQ_CAL_BYTE0_ADDR(inst) ((inst) + 0x00000017) +#define BF_VCO_CAL_INIT_INFO(inst) ((inst) + 0x00000017), 0x00000100 +#define BF_VCO_CAL_BUSY_INFO(inst) ((inst) + 0x00000017), 0x00000101 +#define BF_VCO_COMP_OUT_INFO(inst) ((inst) + 0x00000017), 0x00000102 +#define BF_VCO_FINE_CAL_EN_INFO(inst) ((inst) + 0x00000017), 0x00000103 +#define BF_VCO_CAL_ALC_WAIT_INFO(inst) ((inst) + 0x00000017), 0x00000304 +#define BF_VCO_COARSE_CAL_EN_INFO(inst) ((inst) + 0x00000017), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_VCO_ALC_FREQ_CAL_BYTE1_ADDR(inst) ((inst) + 0x00000018) +#define BF_VCO_CAL_ALC_CLK_DIV_INFO(inst) ((inst) + 0x00000018), 0x00000300 +#define BF_VCO_CAL_ALC_INIT_WAIT_INFO(inst) ((inst) + 0x00000018), 0x00000203 +#define BF_VCO_CAL_INIT_DEL_INFO(inst) ((inst) + 0x00000018), 0x00000305 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_VCO_ALC_FREQ_CAL_BYTE2_ADDR(inst) ((inst) + 0x00000019) +#define BF_VCO_INIT_ALC_VALUE_INFO(inst) ((inst) + 0x00000019), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_F_ALC_BYTE0_ADDR(inst) ((inst) + 0x0000001A) +#define BF_VCO_F_ALC_INFO(inst) ((inst) + 0x0000001A), 0x00000B00 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_F_ALC_BYTE1_ADDR(inst) ((inst) + 0x0000001B) +#define BF_ALC_COMP_CLK_F_VAL_INFO(inst) ((inst) + 0x0000001B), 0x00000104 +#define BF_FORCE_ALC_COMP_CLK_INFO(inst) ((inst) + 0x0000001B), 0x00000105 +#define BF_VCO_ALC_CAL_EN_INFO(inst) ((inst) + 0x0000001B), 0x00000106 +#define BF_VCO_F_ALC_EN_INFO(inst) ((inst) + 0x0000001B), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_VCO_F_COARSE_BAND_BYTE0_ADDR(inst) ((inst) + 0x0000001C) +#define BF_VCO_F_COARSE_BAND_INFO(inst) ((inst) + 0x0000001C), 0x00000900 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_VCO_F_COARSE_BAND_BYTE1_ADDR(inst) ((inst) + 0x0000001D) +#define BF_VCO_F_COARSE_BAND_EN_INFO(inst) ((inst) + 0x0000001D), 0x00000101 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_VCO_F_FINE_BAND_ADDR(inst) ((inst) + 0x0000001E) +#define BF_VCO_F_FINE_BAND_INFO(inst) ((inst) + 0x0000001E), 0x00000600 +#define BF_VCO_F_FINE_BAND_EN_INFO(inst) ((inst) + 0x0000001E), 0x00000106 +#define BF_VCO_F_FINE_BAND_INDEX_EN_INFO(inst) ((inst) + 0x0000001E), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_VCO_TC_BYTE1_ADDR(inst) ((inst) + 0x0000001F) +#define BF_VCO_VAR_TC_INFO(inst) ((inst) + 0x0000001F), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_VCO_TC_BYTE2_ADDR(inst) ((inst) + 0x00000020) +#define BF_VCO_TC_TRACKING_EN_INFO(inst) ((inst) + 0x00000020), 0x00000100 +#define BF_TC_FLAG_STEP_EN_INFO(inst) ((inst) + 0x00000020), 0x00000101 +#define BF_VCO_TC_WAIT_INFO(inst) ((inst) + 0x00000020), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_VCO_TC_BYTE3_ADDR(inst) ((inst) + 0x00000021) +#define BF_TC_OV_STEP_INFO(inst) ((inst) + 0x00000021), 0x00000400 +#define BF_TC_FLAG_STEP_INFO(inst) ((inst) + 0x00000021), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_MCS_CONTROL_ADDR(inst) ((inst) + 0x00000022) +#define BF_MCS_ENABLE_INFO(inst) ((inst) + 0x00000022), 0x00000100 +#define BF_MCS_CLKGEN_SYNC_ENABLE_INFO(inst) ((inst) + 0x00000022), 0x00000101 +#define BF_MCS_SDM_SYNC_ENABLE_INFO(inst) ((inst) + 0x00000022), 0x00000102 +#define BF_MCS_DEVICE_CLK_DIVIDER_SYNC_ENABLE_INFO(inst) ((inst) + 0x00000022), 0x00000103 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_MCS_CONTROL_2_ADDR(inst) ((inst) + 0x00000023) +#define BF_MCS_PULSE_DELAY_INFO(inst) ((inst) + 0x00000023), 0x00000300 +#define BF_MCS_WAIT_COUNT_INFO(inst) ((inst) + 0x00000023), 0x00000203 +#define BF_RETIME_SEL_PSYNCDIV_INFO(inst) ((inst) + 0x00000023), 0x00000105 +#define BF_SEL_PSYNCDIV_FE_INFO(inst) ((inst) + 0x00000023), 0x00000106 +#define BF_INV_SYSREF_INFO(inst) ((inst) + 0x00000023), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_MCS_CONTROL_3_ADDR(inst) ((inst) + 0x00000024) +#define BF_INTERNAL_SYSREF_EN_INFO(inst) ((inst) + 0x00000024), 0x00000100 +#define BF_GCNT_SYSREF_EN_INFO(inst) ((inst) + 0x00000024), 0x00000101 +#define BF_REFCLK_MCSRST_ON_RE_INFO(inst) ((inst) + 0x00000024), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_MCS_STATUS_ADDR(inst) ((inst) + 0x00000025) +#define BF_MCS_SPI_STATUS_INFO(inst) ((inst) + 0x00000025), 0x00000300 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_LOCKDET_CONFIG_ADDR(inst) ((inst) + 0x00000026) +#define BF_LOCKDET_MODE_INFO(inst) ((inst) + 0x00000026), 0x00000200 +#define BF_LOCKDET_CNT_INFO(inst) ((inst) + 0x00000026), 0x00000202 +#define BF_FORCE_LOCK_INFO(inst) ((inst) + 0x00000026), 0x00000104 +#define BF_SYN_LOCK_INFO(inst) ((inst) + 0x00000026), 0x00000105 +#define BF_LOCK_WINDOW_SIZE_INFO(inst) ((inst) + 0x00000026), 0x00000106 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_LOCKDET_CONFIG2_ADDR(inst) ((inst) + 0x00000027) +#define BF_FAST_UNLOCK_EN_INFO(inst) ((inst) + 0x00000027), 0x00000100 +#define BF_UNLOCK_TIMEOUT_EN_INFO(inst) ((inst) + 0x00000027), 0x00000101 +#define BF_FAST_UNLOCK_THR_INFO(inst) ((inst) + 0x00000027), 0x00000204 +#define BF_UNLOCK_TIMEOUT_VAL_INFO(inst) ((inst) + 0x00000027), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_PSCTL0_ADDR(inst) ((inst) + 0x00000028) +#define BF_PSEN_INFO(inst) ((inst) + 0x00000028), 0x00000100 +#define BF_CALTYP_INFO(inst) ((inst) + 0x00000028), 0x00000301 +#define BF_CALPER_INFO(inst) ((inst) + 0x00000028), 0x00000304 +#define BF_ABORT_PLL_MEM_MAP_INFO(inst) ((inst) + 0x00000028), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_PSCTL1_ADDR(inst) ((inst) + 0x00000029) +#define BF_CTSTEP_INFO(inst) ((inst) + 0x00000029), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_PSCTL2_ADDR(inst) ((inst) + 0x0000002A) +#define BF_CSTEP_INFO(inst) ((inst) + 0x0000002A), 0x00000C00 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_PSCTL3_ADDR(inst) ((inst) + 0x0000002B) +#define BF_QTHR_INFO(inst) ((inst) + 0x0000002B), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_PSCTL4_ADDR(inst) ((inst) + 0x0000002C) +#define BF_ICALWAIT_INFO(inst) ((inst) + 0x0000002C), 0x00000200 +#define BF_TSZERO_INFO(inst) ((inst) + 0x0000002C), 0x00000103 +#define BF_TSPRSC_INFO(inst) ((inst) + 0x0000002C), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_PSCTL5_ADDR(inst) ((inst) + 0x0000002D) +#define BF_LG_DIV_INFO(inst) ((inst) + 0x0000002D), 0x00000A00 +#endif /* USE_PRIVATE_BF */ + +#define REG_PSCTL6_ADDR(inst) ((inst) + 0x0000002E) + +#ifdef USE_PRIVATE_BF +#define REG_PSCTL7_ADDR(inst) ((inst) + 0x0000002F) +#define BF_READ_GCNT_INFO(inst) ((inst) + 0x0000002F), 0x00000100 +#define BF_FDOVDM_INFO(inst) ((inst) + 0x0000002F), 0x00000104 +#define BF_INV_LO_I_INFO(inst) ((inst) + 0x0000002F), 0x00000106 +#define BF_INV_LO_Q_INFO(inst) ((inst) + 0x0000002F), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_PSSTAT_ADDR(inst) ((inst) + 0x00000030) +#define BF_PSBUSY_INFO(inst) ((inst) + 0x00000030), 0x00000100 +#define BF_MPEND_INFO(inst) ((inst) + 0x00000030), 0x00000101 +#define BF_CPEND_INFO(inst) ((inst) + 0x00000030), 0x00000102 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_PHADJ0_ADDR(inst) ((inst) + 0x00000031) +#define BF_PHADJ_INFO(inst) ((inst) + 0x00000031), 0x00001700 +#endif /* USE_PRIVATE_BF */ + +#define REG_PHADJ1_ADDR(inst) ((inst) + 0x00000032) + +#define REG_PHADJ2_ADDR(inst) ((inst) + 0x00000033) + +#ifdef USE_PRIVATE_BF +#define REG_FDOVD0_ADDR(inst) ((inst) + 0x00000034) +#define BF_FDOVD_INFO(inst) ((inst) + 0x00000034), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_FDOVD1_ADDR(inst) ((inst) + 0x00000035) + +#define REG_FDOVD2_ADDR(inst) ((inst) + 0x00000036) + +#define REG_FDOVD3_ADDR(inst) ((inst) + 0x00000037) + +#ifdef USE_PRIVATE_BF +#define REG_WPA0_ADDR(inst) ((inst) + 0x00000038) +#define BF_WPA_INFO(inst) ((inst) + 0x00000038), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_WPA1_ADDR(inst) ((inst) + 0x00000039) + +#define REG_WPA2_ADDR(inst) ((inst) + 0x0000003A) + +#define REG_WPA3_ADDR(inst) ((inst) + 0x0000003B) + +#ifdef USE_PRIVATE_BF +#define REG_POAI0_ADDR(inst) ((inst) + 0x0000003C) +#define BF_POAI_INFO(inst) ((inst) + 0x0000003C), 0x00001400 +#endif /* USE_PRIVATE_BF */ + +#define REG_POAI1_ADDR(inst) ((inst) + 0x0000003D) + +#define REG_POAI2_ADDR(inst) ((inst) + 0x0000003E) + +#ifdef USE_PRIVATE_BF +#define REG_POAQ0_ADDR(inst) ((inst) + 0x0000003F) +#define BF_POAQ_INFO(inst) ((inst) + 0x0000003F), 0x00001400 +#endif /* USE_PRIVATE_BF */ + +#define REG_POAQ1_ADDR(inst) ((inst) + 0x00000040) + +#define REG_POAQ2_ADDR(inst) ((inst) + 0x00000041) + +#ifdef USE_PRIVATE_BF +#define REG_PHDIFF0_ADDR(inst) ((inst) + 0x00000042) +#define BF_PHDIFF_INFO(inst) ((inst) + 0x00000042), 0x00001700 +#endif /* USE_PRIVATE_BF */ + +#define REG_PHDIFF1_ADDR(inst) ((inst) + 0x00000043) + +#define REG_PHDIFF2_ADDR(inst) ((inst) + 0x00000044) + +#ifdef USE_PRIVATE_BF +#define REG_GCNT0_ADDR(inst) ((inst) + 0x00000045) +#define BF_GCNT_INFO(inst) ((inst) + 0x00000045), 0x00004000 +#endif /* USE_PRIVATE_BF */ + +#define REG_GCNT1_ADDR(inst) ((inst) + 0x00000046) + +#define REG_GCNT2_ADDR(inst) ((inst) + 0x00000047) + +#define REG_GCNT3_ADDR(inst) ((inst) + 0x00000048) + +#define REG_GCNT4_ADDR(inst) ((inst) + 0x00000049) + +#define REG_GCNT5_ADDR(inst) ((inst) + 0x0000004A) + +#define REG_GCNT6_ADDR(inst) ((inst) + 0x0000004B) + +#define REG_GCNT7_ADDR(inst) ((inst) + 0x0000004C) + +#ifdef USE_PRIVATE_BF +#define REG_GCNT_SYSREF0_ADDR(inst) ((inst) + 0x0000004D) +#define BF_GCNT_SYSREF_INFO(inst) ((inst) + 0x0000004D), 0x00004000 +#endif /* USE_PRIVATE_BF */ + +#define REG_GCNT_SYSREF1_ADDR(inst) ((inst) + 0x0000004E) + +#define REG_GCNT_SYSREF2_ADDR(inst) ((inst) + 0x0000004F) + +#define REG_GCNT_SYSREF3_ADDR(inst) ((inst) + 0x00000050) + +#define REG_GCNT_SYSREF4_ADDR(inst) ((inst) + 0x00000051) + +#define REG_GCNT_SYSREF5_ADDR(inst) ((inst) + 0x00000052) + +#define REG_GCNT_SYSREF6_ADDR(inst) ((inst) + 0x00000053) + +#define REG_GCNT_SYSREF7_ADDR(inst) ((inst) + 0x00000054) + +#ifdef USE_PRIVATE_BF +#define REG_MOD0_0_ADDR(inst) ((inst) + 0x00000055) +#define BF_MOD0_INFO(inst) ((inst) + 0x00000055), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_MOD0_1_ADDR(inst) ((inst) + 0x00000056) + +#define REG_MOD0_2_ADDR(inst) ((inst) + 0x00000057) + +#define REG_MOD0_3_ADDR(inst) ((inst) + 0x00000058) + +#ifdef USE_PRIVATE_BF +#define REG_MOD1_0_ADDR(inst) ((inst) + 0x00000059) +#define BF_MOD1_INFO(inst) ((inst) + 0x00000059), 0x00001700 +#endif /* USE_PRIVATE_BF */ + +#define REG_MOD1_1_ADDR(inst) ((inst) + 0x0000005A) + +#define REG_MOD1_2_ADDR(inst) ((inst) + 0x0000005B) + +#ifdef USE_PRIVATE_BF +#define REG_MOD2_0_ADDR(inst) ((inst) + 0x0000005C) +#define BF_MOD2_INFO(inst) ((inst) + 0x0000005C), 0x00001700 +#endif /* USE_PRIVATE_BF */ + +#define REG_MOD2_1_ADDR(inst) ((inst) + 0x0000005D) + +#define REG_MOD2_2_ADDR(inst) ((inst) + 0x0000005E) + +#ifdef USE_PRIVATE_BF +#define REG_DTAPS0_ADDR(inst) ((inst) + 0x0000005F) +#define BF_DTAPS_B0_INFO(inst) ((inst) + 0x0000005F), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_DTAPS1_ADDR(inst) ((inst) + 0x00000060) +#define BF_DTAPS_B1_INFO(inst) ((inst) + 0x00000060), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_DTAPS2_ADDR(inst) ((inst) + 0x00000061) +#define BF_DTAPS_B2_INFO(inst) ((inst) + 0x00000061), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_DTAPS3_ADDR(inst) ((inst) + 0x00000062) +#define BF_DTAPS_B3_INFO(inst) ((inst) + 0x00000062), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_SDA_ADDR(inst) ((inst) + 0x00000063) +#define BF_SDA_INFO(inst) ((inst) + 0x00000063), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_SDM_DITH_ADDR(inst) ((inst) + 0x00000064) +#define BF_NUM_DITHER_BITS_INFO(inst) ((inst) + 0x00000064), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TCCTL_ADDR(inst) ((inst) + 0x00000065) +#define BF_TCFORCEN_INFO(inst) ((inst) + 0x00000065), 0x00000100 +#define BF_TCUPDINIT_INFO(inst) ((inst) + 0x00000065), 0x00000101 +#define BF_TCPOL_INFO(inst) ((inst) + 0x00000065), 0x00000102 +#define BF_TCFORCE_INFO(inst) ((inst) + 0x00000065), 0x00000103 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TCIDAC_0_ADDR(inst) ((inst) + 0x00000066) +#define BF_TCIDAC_INFO(inst) ((inst) + 0x00000066), 0x00000C00 +#endif /* USE_PRIVATE_BF */ + +#define REG_TCIDAC_1_ADDR(inst) ((inst) + 0x00000067) + +#ifdef USE_PRIVATE_BF +#define REG_LOGEN_CTL0_ADDR(inst) ((inst) + 0x00000068) +#define BF_LODIV_THERMCODE_INFO(inst) ((inst) + 0x00000068), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_LOGEN_CTL1_ADDR(inst) ((inst) + 0x00000069) +#define BF_LOOUTDIV_THERMCODE_INFO(inst) ((inst) + 0x00000069), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_LOGEN_CTL2_ADDR(inst) ((inst) + 0x0000006A) +#define BF_LOOUTDIV_LEAF_THERMCODE_INFO(inst) ((inst) + 0x0000006A), 0x00000200 +#define BF_LOOUTDIV_LEAF_FUND_INFO(inst) ((inst) + 0x0000006A), 0x00000103 +#define BF_XLOIN_BAND_INFO(inst) ((inst) + 0x0000006A), 0x00000304 +#define BF_XLOIN_SPARE_INFO(inst) ((inst) + 0x0000006A), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_LOGEN_CTL3_ADDR(inst) ((inst) + 0x0000006B) +#define BF_LODIV_KILLCLK_INFO(inst) ((inst) + 0x0000006B), 0x00000100 +#define BF_LOOUTDIV_KILLCLK_INFO(inst) ((inst) + 0x0000006B), 0x00000101 +#define BF_LODIV_RB_INFO(inst) ((inst) + 0x0000006B), 0x00000104 +#define BF_LOOUTDIV_RB_INFO(inst) ((inst) + 0x0000006B), 0x00000105 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_LOGEN_CTL4_ADDR(inst) ((inst) + 0x0000006C) +#define BF_XLOIN_FUND_INV_INFO(inst) ((inst) + 0x0000006C), 0x00000100 +#define BF_LODIV_FUND_INFO(inst) ((inst) + 0x0000006C), 0x00000101 +#define BF_LOOUTDIV_FUND_INFO(inst) ((inst) + 0x0000006C), 0x00000102 +#define BF_SEL_VCO_OR_EXTLO_INFO(inst) ((inst) + 0x0000006C), 0x00000104 +#define BF_SEL_TX_LO_INFO(inst) ((inst) + 0x0000006C), 0x00000105 +#define BF_SEL_RX_LO_INFO(inst) ((inst) + 0x0000006C), 0x00000106 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_LOGEN_CTL5_ADDR(inst) ((inst) + 0x0000006D) +#define BF_LO_PHSYNC_LEAF_FUND_INFO(inst) ((inst) + 0x0000006D), 0x00000100 +#define BF_LO_PHSYNC_LEAF_THERMCODE_INFO(inst) ((inst) + 0x0000006D), 0x00000202 +#define BF_LO_PHSYNC_LEAF_KILLCLK_INFO(inst) ((inst) + 0x0000006D), 0x00000104 +#define BF_LO_PHSYNC_LEAF_RB_INFO(inst) ((inst) + 0x0000006D), 0x00000105 +#define BF_LO_PHSYNC_QUAD2_KILLCLK_INFO(inst) ((inst) + 0x0000006D), 0x00000106 +#define BF_LO_PHSYNC_QUAD2_RB_INFO(inst) ((inst) + 0x0000006D), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_LOGEN_CTL6_ADDR(inst) ((inst) + 0x0000006E) +#define BF_LOGEN_SPARES_INFO(inst) ((inst) + 0x0000006E), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CLKGEN_DIGCORE_1_ADDR(inst) ((inst) + 0x0000006F) +#define BF_DIGCORE_DIV1_EN_INFO(inst) ((inst) + 0x0000006F), 0x00000100 +#define BF_DIGCORE_DIV3_EN_INFO(inst) ((inst) + 0x0000006F), 0x00000101 +#define BF_CLKGEN_SYNCCLK_OUTPUT_EN_INFO(inst) ((inst) + 0x0000006F), 0x00000102 +#define BF_DIGCORE_DIV3_KILLCLK_INFO(inst) ((inst) + 0x0000006F), 0x00000104 +#define BF_DIGCORE_SAMPLE_KILLCLK_INFO(inst) ((inst) + 0x0000006F), 0x00000105 +#define BF_DIGCORE_INTERFACE_KILLCLK_INFO(inst) ((inst) + 0x0000006F), 0x00000106 +#define BF_DIGCORE_DIV_RSTB_INFO(inst) ((inst) + 0x0000006F), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CLKGEN_DIGCORE_2_ADDR(inst) ((inst) + 0x00000070) +#define BF_DIGCORE_INTDIV_BINCODE_INFO(inst) ((inst) + 0x00000070), 0x00000400 +#define BF_DIGCORE_CLKDIV_THERMCODE_INFO(inst) ((inst) + 0x00000070), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CLKGEN_DIGCORE_3_ADDR(inst) ((inst) + 0x00000071) +#define BF_CLKGEN_SPARES_INFO(inst) ((inst) + 0x00000071), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CLKGEN_ROOT_DIV_ADDR(inst) ((inst) + 0x00000072) +#define BF_ROOT_CLKDIV_RB_INFO(inst) ((inst) + 0x00000072), 0x00000100 +#define BF_ROOT_CLKDIV_KILLCLK_INFO(inst) ((inst) + 0x00000072), 0x00000103 +#define BF_ROOT_CLKDIV_FUND_INFO(inst) ((inst) + 0x00000072), 0x00000104 +#define BF_ROOT_CLKDIV_DIV2_INFO(inst) ((inst) + 0x00000072), 0x00000105 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TEST_CLKDIV_ADDR(inst) ((inst) + 0x00000073) +#define BF_TEST_CLKDIV_RSTB_INFO(inst) ((inst) + 0x00000073), 0x00000100 +#define BF_TEST_CLKDIV_SAMPLE_KILLCLK_INFO(inst) ((inst) + 0x00000073), 0x00000101 +#define BF_TEST_CLKDIV_DIV1_EN_INFO(inst) ((inst) + 0x00000073), 0x00000102 +#define BF_TEST_CLKDIV_THERMCODE_INFO(inst) ((inst) + 0x00000073), 0x00000204 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REF_CLK_BYTE0_ADDR(inst) ((inst) + 0x00000074) +#define BF_REF_CLK_DIVIDE_RATIO_INFO(inst) ((inst) + 0x00000074), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_MOD_VCO_CAL_CTL_ADDR(inst) ((inst) + 0x00000075) +#define BF_VCOCAL_MAXCNTBAND_EN_INFO(inst) ((inst) + 0x00000075), 0x00000100 +#define BF_ENDVCOCAL_MAXCNT_EN_INFO(inst) ((inst) + 0x00000075), 0x00000101 +#define BF_FREQ_CAL_SINGLE_INFO(inst) ((inst) + 0x00000075), 0x00000102 +#define BF_FCAL_SINGLE_UPD_BANDS_INFO(inst) ((inst) + 0x00000075), 0x00000103 +#define BF_VCOCAL_TIMEDBANDUPD_EN_INFO(inst) ((inst) + 0x00000075), 0x00000104 +#define BF_FREQ_CAL_CNT_RDSEL_INFO(inst) ((inst) + 0x00000075), 0x00000106 +#define BF_FORCE_VCO_INIT_ALC_VALUE_INFO(inst) ((inst) + 0x00000075), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_QUICK_FREQ_CAL_CTL_ADDR(inst) ((inst) + 0x00000076) +#define BF_QUICK_FREQ_CAL_THRESHOLD_INFO(inst) ((inst) + 0x00000076), 0x00000700 +#define BF_QUICK_FREQ_CAL_EN_INFO(inst) ((inst) + 0x00000076), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FREQ_CAL_MAX_CNT0_ADDR(inst) ((inst) + 0x00000077) +#define BF_FREQ_CAL_MAX_CNT_INFO(inst) ((inst) + 0x00000077), 0x00001800 +#endif /* USE_PRIVATE_BF */ + +#define REG_FREQ_CAL_MAX_CNT1_ADDR(inst) ((inst) + 0x00000078) + +#define REG_FREQ_CAL_MAX_CNT2_ADDR(inst) ((inst) + 0x00000079) + +#ifdef USE_PRIVATE_BF +#define REG_FINE_CAP_DNL_OFFSET_ADDR(inst) ((inst) + 0x0000007A) +#define BF_DNL_OFFSET_INFO(inst) ((inst) + 0x0000007A), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FREQ_CALCNT_RDBCK0_ADDR(inst) ((inst) + 0x0000007B) +#define BF_FREQ_CALCNT_RDBCK_INFO(inst) ((inst) + 0x0000007B), 0x00001800 +#endif /* USE_PRIVATE_BF */ + +#define REG_FREQ_CALCNT_RDBCK1_ADDR(inst) ((inst) + 0x0000007C) + +#define REG_FREQ_CALCNT_RDBCK2_ADDR(inst) ((inst) + 0x0000007D) + +#ifdef USE_PRIVATE_BF +#define REG_FINE_CAP_DNL_0_ADDR(inst) ((inst) + 0x0000007E) +#define BF_DNL_0_INFO(inst) ((inst) + 0x0000007E), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FINE_CAP_DNL_1_ADDR(inst) ((inst) + 0x0000007F) +#define BF_DNL_1_INFO(inst) ((inst) + 0x0000007F), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FINE_CAP_DNL_2_ADDR(inst) ((inst) + 0x00000080) +#define BF_DNL_2_INFO(inst) ((inst) + 0x00000080), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FINE_CAP_DNL_3_ADDR(inst) ((inst) + 0x00000081) +#define BF_DNL_3_INFO(inst) ((inst) + 0x00000081), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FINE_CAP_DNL_4_ADDR(inst) ((inst) + 0x00000082) +#define BF_DNL_4_INFO(inst) ((inst) + 0x00000082), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FINE_CAP_DNL_5_ADDR(inst) ((inst) + 0x00000083) +#define BF_DNL_5_INFO(inst) ((inst) + 0x00000083), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FINE_CAP_DNL_6_ADDR(inst) ((inst) + 0x00000084) +#define BF_DNL_6_INFO(inst) ((inst) + 0x00000084), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FINE_CAP_DNL_7_ADDR(inst) ((inst) + 0x00000085) +#define BF_DNL_7_INFO(inst) ((inst) + 0x00000085), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FINE_CAP_DNL_8_ADDR(inst) ((inst) + 0x00000086) +#define BF_DNL_8_INFO(inst) ((inst) + 0x00000086), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CP_CTL0_ADDR(inst) ((inst) + 0x00000087) +#define BF_CP_EN_INFO(inst) ((inst) + 0x00000087), 0x00000100 +#define BF_CP_BLEED_DN_EN_INFO(inst) ((inst) + 0x00000087), 0x00000102 +#define BF_CP_BLEED_UP_EN_INFO(inst) ((inst) + 0x00000087), 0x00000103 +#define BF_CP_BW_INFO(inst) ((inst) + 0x00000087), 0x00000204 +#define BF_CP_GAINBITS_INFO(inst) ((inst) + 0x00000087), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CP_CTL1_ADDR(inst) ((inst) + 0x00000088) +#define BF_CP_IBLEED_INFO(inst) ((inst) + 0x00000088), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CP_CTL2_ADDR(inst) ((inst) + 0x00000089) +#define BF_AUXADC_HYST_ON_FLAG_INFO(inst) ((inst) + 0x00000089), 0x00000100 +#define BF_SEL_ADC_FLAG_INFO(inst) ((inst) + 0x00000089), 0x00000102 +#define BF_CP_FORCE_VDD_OVER_2_INFO(inst) ((inst) + 0x00000089), 0x00000103 +#define BF_AUXADC_HYST_FLAG_INFO(inst) ((inst) + 0x00000089), 0x00000204 +#define BF_CP_BYPASS_FILTER_INFO(inst) ((inst) + 0x00000089), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_MISC_KILL_SIGNALS_ADDR(inst) ((inst) + 0x0000008A) +#define BF_PFD_KILL_UPDNTOLD_INFO(inst) ((inst) + 0x0000008A), 0x00000100 +#define BF_KILLRDIVTODIG_INFO(inst) ((inst) + 0x0000008A), 0x00000102 +#define BF_KILLRDIVTOLD_INFO(inst) ((inst) + 0x0000008A), 0x00000103 +#define BF_KILLNDIVTOLD_INFO(inst) ((inst) + 0x0000008A), 0x00000104 +#define BF_NDIV_PS_KILLCLK_TUNEDIV4_INFO(inst) ((inst) + 0x0000008A), 0x00000105 +#define BF_KILLRDIV_VCOCAL_INFO(inst) ((inst) + 0x0000008A), 0x00000106 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_NEW_LOCK_DETECT0_ADDR(inst) ((inst) + 0x0000008B) +#define BF_LD_RSTB_INFO(inst) ((inst) + 0x0000008B), 0x00000100 +#define BF_LD_EN_INFO(inst) ((inst) + 0x0000008B), 0x00000102 +#define BF_LD_LOL_EN_INFO(inst) ((inst) + 0x0000008B), 0x00000103 +#define BF_LD_BYPASS_DIVBY32_INFO(inst) ((inst) + 0x0000008B), 0x00000104 +#define BF_LD_LOL_LDP_INFO(inst) ((inst) + 0x0000008B), 0x00000305 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_NEW_LOCK_DETECT1_ADDR(inst) ((inst) + 0x0000008C) +#define BF_LD_LOL_HYST_EN_INFO(inst) ((inst) + 0x0000008C), 0x00000100 +#define BF_LD_PD_INFO(inst) ((inst) + 0x0000008C), 0x00000101 +#define BF_LD_LOL_DEAD_CLK_INFO(inst) ((inst) + 0x0000008C), 0x00000102 +#define BF_LD_LOL_HYST_INFO(inst) ((inst) + 0x0000008C), 0x00000103 +#define BF_LD_COUNT_INFO(inst) ((inst) + 0x0000008C), 0x00000204 +#define BF_LD_LOCKED_INFO(inst) ((inst) + 0x0000008C), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_PRESCALER_CTL_ADDR(inst) ((inst) + 0x0000008D) +#define BF_NDIV_PS_EN_TUNEDIV4_INFO(inst) ((inst) + 0x0000008D), 0x00000100 +#define BF_NDIV_PS_RB_INFO(inst) ((inst) + 0x0000008D), 0x00000101 +#define BF_KILL_VCO_TO_NDIV_PS_INFO(inst) ((inst) + 0x0000008D), 0x00000102 +#define BF_NDIV_PS_DLYSEL_INFO(inst) ((inst) + 0x0000008D), 0x00000103 +#define BF_NDIV_PS_SPARES_INFO(inst) ((inst) + 0x0000008D), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_PFD_CHARGEPUMP_SPARES_ADDR(inst) ((inst) + 0x0000008E) +#define BF_PFDCP_SPARES_INFO(inst) ((inst) + 0x0000008E), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_VCO_LDO_0_ADDR(inst) ((inst) + 0x0000008F) +#define BF_LDO_THERM_SDN_THR_INFO(inst) ((inst) + 0x0000008F), 0x00000200 +#define BF_VCO_LDO_ILIM_THR_INFO(inst) ((inst) + 0x0000008F), 0x00000202 +#define BF_LDO_OVERVOLT_THR_INFO(inst) ((inst) + 0x0000008F), 0x00000204 +#define BF_LDO_OVERRIDE_INFO(inst) ((inst) + 0x0000008F), 0x00000106 +#define BF_VCO_LDO_BYPASS_INFO(inst) ((inst) + 0x0000008F), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_VCO_LDO_1_ADDR(inst) ((inst) + 0x00000090) +#define BF_LDO_VOUT_ADJ_INFO(inst) ((inst) + 0x00000090), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_VCO_LDO_2_ADDR(inst) ((inst) + 0x00000091) +#define BF_LDO_VREF_FILT_INFO(inst) ((inst) + 0x00000091), 0x00000200 +#define BF_LDO_COMPENS_ADJ_INFO(inst) ((inst) + 0x00000091), 0x00000202 +#define BF_LDO_LOAD_RES_ADJ_INFO(inst) ((inst) + 0x00000091), 0x00000104 +#define BF_LDO_COMPAR_TEST_INFO(inst) ((inst) + 0x00000091), 0x00000305 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_VCO_LDO_3_ADDR(inst) ((inst) + 0x00000092) +#define BF_LDO_SPARE_INFO(inst) ((inst) + 0x00000092), 0x00000400 +#define BF_LDO_ENVPTAT_INFO(inst) ((inst) + 0x00000092), 0x00000104 +#define BF_LDO_VPTATCTRL_INFO(inst) ((inst) + 0x00000092), 0x00000205 +#define BF_VCO_LDO_OUTPUT_PD_INFO(inst) ((inst) + 0x00000092), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_VCO_LDO_4_ADDR(inst) ((inst) + 0x00000093) +#define BF_LDO_CORE_BIAS_ADJ_INFO(inst) ((inst) + 0x00000093), 0x00000400 +#define BF_LDO_CLEAR_STATUS_INFO(inst) ((inst) + 0x00000093), 0x00000104 +#define BF_LDO_ILOAD_ADJ_INFO(inst) ((inst) + 0x00000093), 0x00000105 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_VCO_LDO_STAT_ADDR(inst) ((inst) + 0x00000094) +#define BF_LDO_OVERVOLT_INFO(inst) ((inst) + 0x00000094), 0x00000100 +#define BF_LDO_CURLIM_INFO(inst) ((inst) + 0x00000094), 0x00000101 +#define BF_LDO_THERMSDN_INFO(inst) ((inst) + 0x00000094), 0x00000102 +#define BF_LDO_POWERGOOD_INFO(inst) ((inst) + 0x00000094), 0x00000103 +#define BF_LDO_NOREF_INFO(inst) ((inst) + 0x00000094), 0x00000104 +#define BF_LDO_UVL_INFO(inst) ((inst) + 0x00000094), 0x00000105 +#define BF_LDO_LOWOUTPUT_INFO(inst) ((inst) + 0x00000094), 0x00000106 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_VCO_CTL0_ADDR(inst) ((inst) + 0x00000095) +#define BF_VCO_SEL_INFO(inst) ((inst) + 0x00000095), 0x00000200 +#define BF_VCOLCR_PD_INFO(inst) ((inst) + 0x00000095), 0x00000102 +#define BF_VCOLCR_BYPASS_BIAS_RES_INFO(inst) ((inst) + 0x00000095), 0x00000103 +#define BF_VCO_VPULL_SEL_INFO(inst) ((inst) + 0x00000095), 0x00000305 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_VCO_CTL1_ADDR(inst) ((inst) + 0x00000096) +#define BF_VCO_VAR_INFO(inst) ((inst) + 0x00000096), 0x00000400 +#define BF_VCOPKDET_CM_SEL_INFO(inst) ((inst) + 0x00000096), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_VCO_CTL2_ADDR(inst) ((inst) + 0x00000097) +#define BF_VCOPKDET_VREF_SEL_INFO(inst) ((inst) + 0x00000097), 0x00000400 +#define BF_VCOPKDET_BYP_RES_DET_INFO(inst) ((inst) + 0x00000097), 0x00000105 +#define BF_VCO_BIAS_TEST_INFO(inst) ((inst) + 0x00000097), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_VCO_CTL3_ADDR(inst) ((inst) + 0x00000098) +#define BF_VCO_LBCORE_CONFIG_INFO(inst) ((inst) + 0x00000098), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_VCO_PD0_ADDR(inst) ((inst) + 0x00000099) +#define BF_VCO_PD_INFO(inst) ((inst) + 0x00000099), 0x00000600 +#define BF_VCO_PD_OVERRIDE_INFO(inst) ((inst) + 0x00000099), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_VCO_PD1_ADDR(inst) ((inst) + 0x0000009A) +#define BF_VCOBUF_PD_INFO(inst) ((inst) + 0x0000009A), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_VCO_PD2_ADDR(inst) ((inst) + 0x0000009B) +#define BF_VCOPKDET_PD_INFO(inst) ((inst) + 0x0000009B), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_VCO_PD3_ADDR(inst) ((inst) + 0x0000009C) +#define BF_VCOPKDET_CMP_PD_INFO(inst) ((inst) + 0x0000009C), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TCIDAC_REG0_ADDR(inst) ((inst) + 0x0000009D) +#define BF_VCOTC_DAC_RST_INFO(inst) ((inst) + 0x0000009D), 0x00000100 +#define BF_VCOTC_I2V_DEGEN_BYP_INFO(inst) ((inst) + 0x0000009D), 0x00000102 +#define BF_VCOTC_I2V_PD_INFO(inst) ((inst) + 0x0000009D), 0x00000103 +#define BF_VCOTC_DAC_SCALE_INFO(inst) ((inst) + 0x0000009D), 0x00000204 +#define BF_VCOTC_I2V_FILT1_BYP_INFO(inst) ((inst) + 0x0000009D), 0x00000106 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TCIDAC_REG1_ADDR(inst) ((inst) + 0x0000009E) +#define BF_VCOTC_I2V_FILT1_INFO(inst) ((inst) + 0x0000009E), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TCIDAC_REG2_ADDR(inst) ((inst) + 0x0000009F) +#define BF_VCOTC_I2V_FILT2_INFO(inst) ((inst) + 0x0000009F), 0x00000300 +#define BF_VCOTC_I2V_FILT2_BYP_INFO(inst) ((inst) + 0x0000009F), 0x00000104 +#define BF_VCOTC_TEST_INFO(inst) ((inst) + 0x0000009F), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TCIDAC_REG3_ADDR(inst) ((inst) + 0x000000A0) +#define BF_VCOTC_I2V_MIR_INFO(inst) ((inst) + 0x000000A0), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TCIDAC_REG4_ADDR(inst) ((inst) + 0x000000A1) +#define BF_VCOTC_I2V_DIODE_INFO(inst) ((inst) + 0x000000A1), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_VCO_CTL_SPARES_0_ADDR(inst) ((inst) + 0x000000A2) +#define BF_VCO_STAT_SPARE_INFO(inst) ((inst) + 0x000000A2), 0x00001000 +#endif /* USE_PRIVATE_BF */ + +#define REG_VCO_CTL_SPARES_1_ADDR(inst) ((inst) + 0x000000A3) + +#ifdef USE_PRIVATE_BF +#define REG_VCO_STAT_SPARES_0_ADDR(inst) ((inst) + 0x000000A4) +#define BF_VCO_CTL_SPARE_INFO(inst) ((inst) + 0x000000A4), 0x00001000 +#endif /* USE_PRIVATE_BF */ + +#define REG_VCO_STAT_SPARES_1_ADDR(inst) ((inst) + 0x000000A5) + +#ifdef USE_PRIVATE_BF +#define REG_BLEED_RAMP_CTL_ADDR(inst) ((inst) + 0x000000A6) +#define BF_BLEED_RAMP_EN_INFO(inst) ((inst) + 0x000000A6), 0x00000100 +#define BF_BLEED_RAMP_INIT_INFO(inst) ((inst) + 0x000000A6), 0x00000101 +#define BF_BLEED_RAMP_DONE_INFO(inst) ((inst) + 0x000000A6), 0x00000104 +#define BF_CP_BLEED_UP_EN_RAMPED_INFO(inst) ((inst) + 0x000000A6), 0x00000106 +#define BF_CP_BLEED_DN_EN_RAMPED_INFO(inst) ((inst) + 0x000000A6), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_BLEED_RAMP_CFG_ADDR(inst) ((inst) + 0x000000A7) +#define BF_BLEED_RAMP_STEP_INFO(inst) ((inst) + 0x000000A7), 0x00000400 +#define BF_BLEED_RAMP_TIME_STEP_INFO(inst) ((inst) + 0x000000A7), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_BLEED_RAMP_STAT_ADDR(inst) ((inst) + 0x000000A8) +#define BF_CP_IBLEED_RAMPED_INFO(inst) ((inst) + 0x000000A8), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_VCO_BAND_DEBUG_COARSE_0_ADDR(inst) ((inst) + 0x000000A9) +#define BF_VCO_BAND2_COARSE_INFO(inst) ((inst) + 0x000000A9), 0x00000900 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_VCO_BAND_DEBUG_COARSE_1_ADDR(inst) ((inst) + 0x000000AA) +#define BF_VCO_BAND_COARSE_SEL_INFO(inst) ((inst) + 0x000000AA), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_VCO_BAND_DEBUG_FINE_ADDR(inst) ((inst) + 0x000000AB) +#define BF_VCO_BAND2_FINE_INFO(inst) ((inst) + 0x000000AB), 0x00000600 +#define BF_VCO_BAND_FINE_SEL_INFO(inst) ((inst) + 0x000000AB), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TESTMUX_ADDR(inst) ((inst) + 0x000000AC) +#define BF_TESTMUX_SEL_INFO(inst) ((inst) + 0x000000AC), 0x00000500 +#define BF_TESTMUX_PD_INFO(inst) ((inst) + 0x000000AC), 0x00000106 +#define BF_TESTMUX_RB_INFO(inst) ((inst) + 0x000000AC), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_SERDES_TEMP_LOOP_CTL_ADDR(inst) ((inst) + 0x000000AD) +#define BF_TC2_CURR_GM_INFO(inst) ((inst) + 0x000000AD), 0x00000300 +#define BF_TC2_GM_PD_INFO(inst) ((inst) + 0x000000AD), 0x00000104 +#define BF_TC2_GM_NORMAL_INFO(inst) ((inst) + 0x000000AD), 0x00000105 +#define BF_TC2_CAL_INFO(inst) ((inst) + 0x000000AD), 0x00000106 +#define BF_TC2_OVERRIDE_INFO(inst) ((inst) + 0x000000AD), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_SERDES_OUTPUT_DIVIDER_CTL_ADDR(inst) ((inst) + 0x000000AE) +#define BF_SERDES_PLL_ODIV_KILLCLK_INFO(inst) ((inst) + 0x000000AE), 0x00000100 +#define BF_SERDES_PLL_ODIV_RB_INFO(inst) ((inst) + 0x000000AE), 0x00000101 +#define BF_SERDES_PLL_ODIV_INFO(inst) ((inst) + 0x000000AE), 0x00000602 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_VCO_SHUNT_LDO_CTL_0_ADDR(inst) ((inst) + 0x000000AF) +#define BF_SLDO1P0_UVP_DET_THR_INFO(inst) ((inst) + 0x000000AF), 0x00000200 +#define BF_SLDO1P0_UVP_COMP_TST_INFO(inst) ((inst) + 0x000000AF), 0x00000102 +#define BF_SLDO1P0_BYP_INFO(inst) ((inst) + 0x000000AF), 0x00000103 +#define BF_SLDO1P0_SPARE_INFO(inst) ((inst) + 0x000000AF), 0x00000304 +#define BF_SLDO1P0_OVP_COMP_TST_INFO(inst) ((inst) + 0x000000AF), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_VCO_SHUNT_LDO_CTL_1_ADDR(inst) ((inst) + 0x000000B0) +#define BF_SLDO1P0_OVP_DIS_INFO(inst) ((inst) + 0x000000B0), 0x00000100 +#define BF_SLDO1P0_COMPENS_ADJ_INFO(inst) ((inst) + 0x000000B0), 0x00000101 +#define BF_SLDO1P0_PD_INFO(inst) ((inst) + 0x000000B0), 0x00000102 +#define BF_SLDO1P0_RAMP_INFO(inst) ((inst) + 0x000000B0), 0x00000103 +#define BF_SLDO1P0_OVP_DET_THR_INFO(inst) ((inst) + 0x000000B0), 0x00000204 +#define BF_SLDO1P0_VOUT_ADJ_INFO(inst) ((inst) + 0x000000B0), 0x00000206 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_VCO_SHUNT_LDO_STAT_ADDR(inst) ((inst) + 0x000000B1) +#define BF_SLDO1P0_OVFLAG_INFO(inst) ((inst) + 0x000000B1), 0x00000100 +#define BF_SLDO1P0_UVFLAG_INFO(inst) ((inst) + 0x000000B1), 0x00000101 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_SDM_SHUNT_LDO_CTL0_ADDR(inst) ((inst) + 0x000000B2) +#define BF_SLDO0P8_PD_INFO(inst) ((inst) + 0x000000B2), 0x00000100 +#define BF_SLDO0P8_BYP_INFO(inst) ((inst) + 0x000000B2), 0x00000101 +#define BF_SLDO0P8_VOUT_ADJ_INFO(inst) ((inst) + 0x000000B2), 0x00000202 +#define BF_SLDO0P8_COMPENS_ADJ_INFO(inst) ((inst) + 0x000000B2), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_SDM_SHUNT_LDO_CTL1_ADDR(inst) ((inst) + 0x000000B3) +#define BF_SLDO0P8_SPARE_INFO(inst) ((inst) + 0x000000B3), 0x00000300 +#define BF_PORB_0P8_INFO(inst) ((inst) + 0x000000B3), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#define REG_TEMPS_MAIN_00_PLL_MEM_MAP_ADDR(inst) ((inst) + 0x000000B4) +#define BF_TEMPS_RESET_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000B4), 0x00000100 +#define BF_TEMPS_START_MEASUREMENT_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000B4), 0x00000101 +#define BF_TEMPS_MEASUREMENT_READY_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000B4), 0x00000104 +#define BF_TEMPS_AWAKE_INFO(inst) ((inst) + 0x000000B4), 0x00000107 + +#define REG_TEMPS_MAIN_01_PLL_MEM_MAP_ADDR(inst) ((inst) + 0x000000B5) + +#define REG_TEMPS_MAIN_02_PLL_MEM_MAP_ADDR(inst) ((inst) + 0x000000B6) +#define BF_TEMPS_TEMPERATURE_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000B6), 0x00000C00 + +#define REG_TEMPS_MAIN_03_PLL_MEM_MAP_ADDR(inst) ((inst) + 0x000000B7) +#define BF_TEMPS_OFFSET_ADJ_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000B7), 0x00000700 + +#define REG_TEMPS_MAIN_04_PLL_MEM_MAP_ADDR(inst) ((inst) + 0x000000B8) +#define BF_TEMPS_SLOPE_ADJ_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000B8), 0x00000800 + +#define REG_TEMPS_PD_RESET_PLL_MEM_MAP_ADDR(inst) ((inst) + 0x000000B9) +#define BF_TEMPS_CLK_PD_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000B9), 0x00000100 +#define BF_TEMPS_STARTUP_PD_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000B9), 0x00000101 +#define BF_TEMPS_PTAT_PD_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000B9), 0x00000102 +#define BF_TEMPS_REF_PD_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000B9), 0x00000103 +#define BF_TEMPS_ADC_PD_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000B9), 0x00000104 +#define BF_TEMPS_RESET_ADC_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000B9), 0x00000107 + +#define REG_TEMPS_PD_OVERRIDE_ADDR(inst) ((inst) + 0x000000BA) + +#define REG_TEMPS_PD_OVERRIDE_SELECT_ADDR(inst) ((inst) + 0x000000BB) + +#define REG_TEMPS_BIAS_PTAT_PLL_MEM_MAP_ADDR(inst) ((inst) + 0x000000BC) +#define BF_TEMPS_CURR_PTAT_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000BC), 0x00000600 + +#define REG_TEMPS_BIAS_REF_PLL_MEM_MAP_ADDR(inst) ((inst) + 0x000000BD) +#define BF_TEMPS_CURR_REF_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000BD), 0x00000600 + +#define REG_TEMPS_BIAS_IAMP_PLL_MEM_MAP_ADDR(inst) ((inst) + 0x000000BE) +#define BF_TEMPS_CURR_IAMP1_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000BE), 0x00000400 +#define BF_TEMPS_CURR_IAMP2_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000BE), 0x00000404 + +#define REG_TEMPS_BIAS_VCM_PLL_MEM_MAP_ADDR(inst) ((inst) + 0x000000BF) +#define BF_TEMPS_CURR_VCM_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000BF), 0x00000400 + +#define REG_TEMPS_BIAS_COMP_PLL_MEM_MAP_ADDR(inst) ((inst) + 0x000000C0) +#define BF_TEMPS_CURR_FLASHO_N_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000C0), 0x00000400 +#define BF_TEMPS_CURR_FLASHO_P_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000C0), 0x00000404 + +#define REG_TEMPS_MUX_IN_PLL_MEM_MAP_ADDR(inst) ((inst) + 0x000000C1) +#define BF_TEMPS_SEL_MUX_VP_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000C1), 0x00000300 +#define BF_TEMPS_SEL_MUX_VM_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000C1), 0x00000304 + +#define REG_TEMPS_MUX_BG_CLK_PLL_MEM_MAP_ADDR(inst) ((inst) + 0x000000C2) +#define BF_TEMPS_SEL_MUX_BG_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000C2), 0x00000300 +#define BF_TEMPS_CLK_MUX_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000C2), 0x00000104 + +#define REG_TEMPS_TEST_CTRL_PLL_MEM_MAP_ADDR(inst) ((inst) + 0x000000C3) +#define BF_TEMPS_TEST_MODE_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000C3), 0x00000200 +#define BF_TEMPS_WAIT_TO_MEASURE_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000C3), 0x00000302 +#define BF_TEMPS_WAKE_SETTING_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000C3), 0x00000305 + +#define REG_TEMPS_TEST_STATE_STEP_PLL_MEM_MAP_ADDR(inst) ((inst) + 0x000000C4) +#define BF_TEMPS_TEST_STATE_ADVANCE_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000C4), 0x00000100 +#define BF_TEMPS_TEST_STATE_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000C4), 0x00000101 +#define BF_TEMPS_MEASURE_CONTROL_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000C4), 0x00000204 + +#define REG_TEMPS_MUX_OBS_CTRL_PLL_MEM_MAP_ADDR(inst) ((inst) + 0x000000C5) +#define BF_TEMPS_MUX_OBS_CTRL_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000C5), 0x00000800 + +#define REG_TEMPS_MUX_OBS_PLL_MEM_MAP_ADDR(inst) ((inst) + 0x000000C6) +#define BF_TEMPS_MUX_OBS_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000C6), 0x00000800 + +#define REG_TEMPS_TEST_SPARE_00_PLL_MEM_MAP_ADDR(inst) ((inst) + 0x000000C7) + +#define REG_TEMPS_TEST_SPARE_01_PLL_MEM_MAP_ADDR(inst) ((inst) + 0x000000C8) +#define BF_TEMPS_CTRL_PLL_MEM_MAP_INFO(inst) ((inst) + 0x000000C8), 0x00001000 + +#endif /* __ADI_APOLLO_BF_PLL_MEM_MAP_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_raptor_open.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_raptor_open.h new file mode 100644 index 00000000000000..e58e1e39e6b6b5 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_raptor_open.h @@ -0,0 +1,989 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:24 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_RAPTOR_OPEN_H__ +#define __ADI_APOLLO_BF_RAPTOR_OPEN_H__ + +/*============= D E F I N E S ==============*/ +#define TX_DAC8_ANALOG0_TX_SLICE_0_TX_DIGITAL0 0x61238000 +#define TX_DAC8_ANALOG1_TX_SLICE_0_TX_DIGITAL0 0x61239000 +#define TX_DAC8_ANALOG0_TX_SLICE_1_TX_DIGITAL0 0x61438000 +#define TX_DAC8_ANALOG1_TX_SLICE_1_TX_DIGITAL0 0x61439000 +#define TX_DAC8_ANALOG0_TX_SLICE_0_TX_DIGITAL1 0x61A38000 +#define TX_DAC8_ANALOG1_TX_SLICE_0_TX_DIGITAL1 0x61A39000 +#define TX_DAC8_ANALOG0_TX_SLICE_1_TX_DIGITAL1 0x61C38000 +#define TX_DAC8_ANALOG1_TX_SLICE_1_TX_DIGITAL1 0x61C39000 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0001_ADDR(inst) ((inst) + 0x00000001) +#define BF_BF_8E4B8D89_INFO(inst) ((inst) + 0x00000001), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0002_ADDR(inst) ((inst) + 0x00000002) +#define BF_BF_6C1FE910_INFO(inst) ((inst) + 0x00000002), 0x00000100 +#define BF_BF_3009C337_INFO(inst) ((inst) + 0x00000002), 0x00000101 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0003_ADDR(inst) ((inst) + 0x00000003) +#define BF_BF_F43A30FA_INFO(inst) ((inst) + 0x00000003), 0x00000100 +#define BF_BF_E3BB5782_INFO(inst) ((inst) + 0x00000003), 0x00000101 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0004_ADDR(inst) ((inst) + 0x00000004) +#define BF_BF_54F0F733_INFO(inst) ((inst) + 0x00000004), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0005_ADDR(inst) ((inst) + 0x00000005) +#define BF_BF_37B572D1_INFO(inst) ((inst) + 0x00000005), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#define REG_RESET_ADDR(inst) ((inst) + 0x00000000) +#define BF_RESET_INFO(inst) ((inst) + 0x00000000), 0x00000100 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0006_ADDR(inst) ((inst) + 0x00000006) +#define BF_BF_E669B158_INFO(inst) ((inst) + 0x00000006), 0x00000200 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0007_ADDR(inst) ((inst) + 0x00000007) +#define BF_BF_12FBD550_INFO(inst) ((inst) + 0x00000007), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0008_ADDR(inst) ((inst) + 0x00000008) +#define BF_BF_70AC9ED8_INFO(inst) ((inst) + 0x00000008), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0009_ADDR(inst) ((inst) + 0x00000009) +#define BF_BF_DEBBC5DE_INFO(inst) ((inst) + 0x00000009), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0010_ADDR(inst) ((inst) + 0x00000010) +#define BF_BF_A9676458_INFO(inst) ((inst) + 0x00000010), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0011_ADDR(inst) ((inst) + 0x00000011) +#define BF_BF_34D62158_INFO(inst) ((inst) + 0x00000011), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0012_ADDR(inst) ((inst) + 0x00000012) +#define BF_BF_A4844B60_INFO(inst) ((inst) + 0x00000012), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0013_ADDR(inst) ((inst) + 0x00000013) +#define BF_BF_BF19D3C6_INFO(inst) ((inst) + 0x00000013), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0014_ADDR(inst) ((inst) + 0x00000014) +#define BF_BF_9764175F_INFO(inst) ((inst) + 0x00000014), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0015_ADDR(inst) ((inst) + 0x00000015) +#define BF_BF_A67FEBFA_INFO(inst) ((inst) + 0x00000015), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0020_ADDR(inst) ((inst) + 0x00000020) +#define BF_BF_FF66C215_INFO(inst) ((inst) + 0x00000020), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0021_ADDR(inst) ((inst) + 0x00000021) +#define BF_BF_FE8C79E6_INFO(inst) ((inst) + 0x00000021), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0022_ADDR(inst) ((inst) + 0x00000022) +#define BF_BF_9299CD42_INFO(inst) ((inst) + 0x00000022), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0023_ADDR(inst) ((inst) + 0x00000023) +#define BF_BF_EEA1BC08_INFO(inst) ((inst) + 0x00000023), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0024_ADDR(inst) ((inst) + 0x00000024) +#define BF_BF_E47277B0_INFO(inst) ((inst) + 0x00000024), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0025_ADDR(inst) ((inst) + 0x00000025) +#define BF_BF_004A312A_INFO(inst) ((inst) + 0x00000025), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0026_ADDR(inst) ((inst) + 0x00000026) +#define BF_BF_A49E63BD_INFO(inst) ((inst) + 0x00000026), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0027_ADDR(inst) ((inst) + 0x00000027) +#define BF_BF_3E0E832A_INFO(inst) ((inst) + 0x00000027), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0028_ADDR(inst) ((inst) + 0x00000028) +#define BF_BF_FB43FE05_INFO(inst) ((inst) + 0x00000028), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0029_ADDR(inst) ((inst) + 0x00000029) +#define BF_BF_62631345_INFO(inst) ((inst) + 0x00000029), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X002A_ADDR(inst) ((inst) + 0x0000002A) +#define BF_BF_49E3F5B7_INFO(inst) ((inst) + 0x0000002A), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0030_ADDR(inst) ((inst) + 0x00000030) +#define BF_BF_E29D72B0_INFO(inst) ((inst) + 0x00000030), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0031_ADDR(inst) ((inst) + 0x00000031) +#define BF_BF_1CD7C11D_INFO(inst) ((inst) + 0x00000031), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0032_ADDR(inst) ((inst) + 0x00000032) +#define BF_BF_F09B49FE_INFO(inst) ((inst) + 0x00000032), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0033_ADDR(inst) ((inst) + 0x00000033) +#define BF_BF_9DE01DA6_INFO(inst) ((inst) + 0x00000033), 0x00000200 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0034_ADDR(inst) ((inst) + 0x00000034) +#define BF_BF_E28CCBC8_INFO(inst) ((inst) + 0x00000034), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0035_ADDR(inst) ((inst) + 0x00000035) +#define BF_BF_13CA4698_INFO(inst) ((inst) + 0x00000035), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0036_ADDR(inst) ((inst) + 0x00000036) +#define BF_BF_8337FBA4_INFO(inst) ((inst) + 0x00000036), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0037_ADDR(inst) ((inst) + 0x00000037) +#define BF_BF_1218FF47_INFO(inst) ((inst) + 0x00000037), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0038_ADDR(inst) ((inst) + 0x00000038) +#define BF_BF_864D7A88_INFO(inst) ((inst) + 0x00000038), 0x00001800 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0X0039_ADDR(inst) ((inst) + 0x00000039) + +#define REG_REG_0X0X003A_ADDR(inst) ((inst) + 0x0000003A) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X003B_ADDR(inst) ((inst) + 0x0000003B) +#define BF_BF_A166D4E4_INFO(inst) ((inst) + 0x0000003B), 0x00000200 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X003C_ADDR(inst) ((inst) + 0x0000003C) +#define BF_BF_CFF45E5F_INFO(inst) ((inst) + 0x0000003C), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X003D_ADDR(inst) ((inst) + 0x0000003D) +#define BF_BF_14871C83_INFO(inst) ((inst) + 0x0000003D), 0x00000200 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X003E_ADDR(inst) ((inst) + 0x0000003E) +#define BF_BF_B2A308D2_INFO(inst) ((inst) + 0x0000003E), 0x00000900 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0X003F_ADDR(inst) ((inst) + 0x0000003F) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0040_ADDR(inst) ((inst) + 0x00000040) +#define BF_BF_91D580BF_INFO(inst) ((inst) + 0x00000040), 0x00000900 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0X0041_ADDR(inst) ((inst) + 0x00000041) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0042_ADDR(inst) ((inst) + 0x00000042) +#define BF_BF_BD3C6EF3_INFO(inst) ((inst) + 0x00000042), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0043_ADDR(inst) ((inst) + 0x00000043) +#define BF_BF_5041F10E_INFO(inst) ((inst) + 0x00000043), 0x00001000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0X0044_ADDR(inst) ((inst) + 0x00000044) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0045_ADDR(inst) ((inst) + 0x00000045) +#define BF_BF_2355940D_INFO(inst) ((inst) + 0x00000045), 0x00000900 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0X0046_ADDR(inst) ((inst) + 0x00000046) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0047_ADDR(inst) ((inst) + 0x00000047) +#define BF_BF_86486D14_INFO(inst) ((inst) + 0x00000047), 0x00000900 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0X0048_ADDR(inst) ((inst) + 0x00000048) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0049_ADDR(inst) ((inst) + 0x00000049) +#define BF_BF_0773BE32_INFO(inst) ((inst) + 0x00000049), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X004A_ADDR(inst) ((inst) + 0x0000004A) +#define BF_BF_C72109A6_INFO(inst) ((inst) + 0x0000004A), 0x00001000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0X004B_ADDR(inst) ((inst) + 0x0000004B) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0401_ADDR(inst) ((inst) + 0x00000401) +#define BF_BF_92273DEB_INFO(inst) ((inst) + 0x00000401), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0402_ADDR(inst) ((inst) + 0x00000402) +#define BF_BF_53912B4F_INFO(inst) ((inst) + 0x00000402), 0x00000100 +#define BF_BF_E503F98B_INFO(inst) ((inst) + 0x00000402), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0403_ADDR(inst) ((inst) + 0x00000403) +#define BF_BF_E5F48D37_INFO(inst) ((inst) + 0x00000403), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0404_ADDR(inst) ((inst) + 0x00000404) +#define BF_BF_F82D59BA_INFO(inst) ((inst) + 0x00000404), 0x00000100 +#define BF_BF_7D079DC7_INFO(inst) ((inst) + 0x00000404), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0405_ADDR(inst) ((inst) + 0x00000405) +#define BF_BF_170AF5B0_INFO(inst) ((inst) + 0x00000405), 0x00000400 +#define BF_BF_B5BCDFD7_INFO(inst) ((inst) + 0x00000405), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0406_ADDR(inst) ((inst) + 0x00000406) +#define BF_BF_F4B8FCC4_INFO(inst) ((inst) + 0x00000406), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0407_ADDR(inst) ((inst) + 0x00000407) +#define BF_BF_F61A2AB5_INFO(inst) ((inst) + 0x00000407), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0408_ADDR(inst) ((inst) + 0x00000408) +#define BF_BF_1FF30FBF_INFO(inst) ((inst) + 0x00000408), 0x00000300 +#define BF_BF_A2B5B411_INFO(inst) ((inst) + 0x00000408), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0409_ADDR(inst) ((inst) + 0x00000409) +#define BF_BF_0EC59E93_INFO(inst) ((inst) + 0x00000409), 0x00000100 +#define BF_BF_913938EC_INFO(inst) ((inst) + 0x00000409), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X040A_ADDR(inst) ((inst) + 0x0000040A) +#define BF_BF_C9C4D490_INFO(inst) ((inst) + 0x0000040A), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X040B_ADDR(inst) ((inst) + 0x0000040B) +#define BF_BF_AFA76E56_INFO(inst) ((inst) + 0x0000040B), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0410_ADDR(inst) ((inst) + 0x00000410) +#define BF_BF_ED0EEF0E_INFO(inst) ((inst) + 0x00000410), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0411_ADDR(inst) ((inst) + 0x00000411) +#define BF_BF_9731CE7A_INFO(inst) ((inst) + 0x00000411), 0x00000100 +#define BF_BF_CBE62FD3_INFO(inst) ((inst) + 0x00000411), 0x00000101 +#define BF_BF_1143176A_INFO(inst) ((inst) + 0x00000411), 0x00000102 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0412_ADDR(inst) ((inst) + 0x00000412) +#define BF_BF_6AB3151A_INFO(inst) ((inst) + 0x00000412), 0x00000100 +#define BF_BF_A766B2F4_INFO(inst) ((inst) + 0x00000412), 0x00000101 +#define BF_BF_03932366_INFO(inst) ((inst) + 0x00000412), 0x00000102 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0413_ADDR(inst) ((inst) + 0x00000413) +#define BF_BF_66D7BA0A_INFO(inst) ((inst) + 0x00000413), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0414_ADDR(inst) ((inst) + 0x00000414) +#define BF_BF_05D638E6_INFO(inst) ((inst) + 0x00000414), 0x00000200 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0415_ADDR(inst) ((inst) + 0x00000415) +#define BF_BF_27BE3895_INFO(inst) ((inst) + 0x00000415), 0x00000200 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0416_ADDR(inst) ((inst) + 0x00000416) +#define BF_BF_2D922C60_INFO(inst) ((inst) + 0x00000416), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0417_ADDR(inst) ((inst) + 0x00000417) +#define BF_BF_5D0FC6EA_INFO(inst) ((inst) + 0x00000417), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0418_ADDR(inst) ((inst) + 0x00000418) +#define BF_BF_6DAB8DBD_INFO(inst) ((inst) + 0x00000418), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0419_ADDR(inst) ((inst) + 0x00000419) +#define BF_BF_D449DC69_INFO(inst) ((inst) + 0x00000419), 0x00000100 +#define BF_BF_FE62B479_INFO(inst) ((inst) + 0x00000419), 0x00000101 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X041A_ADDR(inst) ((inst) + 0x0000041A) +#define BF_BF_36FAD932_INFO(inst) ((inst) + 0x0000041A), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X041B_ADDR(inst) ((inst) + 0x0000041B) +#define BF_BF_80FDFF24_INFO(inst) ((inst) + 0x0000041B), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X041C_ADDR(inst) ((inst) + 0x0000041C) +#define BF_BF_7DC9BE35_INFO(inst) ((inst) + 0x0000041C), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X041D_ADDR(inst) ((inst) + 0x0000041D) +#define BF_BF_E7AC27B9_INFO(inst) ((inst) + 0x0000041D), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X041E_ADDR(inst) ((inst) + 0x0000041E) +#define BF_BF_4B22B334_INFO(inst) ((inst) + 0x0000041E), 0x00000200 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X041F_ADDR(inst) ((inst) + 0x0000041F) +#define BF_BF_9AE1E07A_INFO(inst) ((inst) + 0x0000041F), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0420_ADDR(inst) ((inst) + 0x00000420) +#define BF_BF_9556CFB9_INFO(inst) ((inst) + 0x00000420), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0421_ADDR(inst) ((inst) + 0x00000421) +#define BF_BF_0B06318A_INFO(inst) ((inst) + 0x00000421), 0x00000200 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0422_ADDR(inst) ((inst) + 0x00000422) +#define BF_BF_8A3CC1CE_INFO(inst) ((inst) + 0x00000422), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0423_ADDR(inst) ((inst) + 0x00000423) +#define BF_BF_0F97527D_INFO(inst) ((inst) + 0x00000423), 0x00000200 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0424_ADDR(inst) ((inst) + 0x00000424) +#define BF_BF_A3EA2614_INFO(inst) ((inst) + 0x00000424), 0x00000200 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0425_ADDR(inst) ((inst) + 0x00000425) +#define BF_BF_8035E27C_INFO(inst) ((inst) + 0x00000425), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0426_ADDR(inst) ((inst) + 0x00000426) +#define BF_BF_8008264B_INFO(inst) ((inst) + 0x00000426), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0427_ADDR(inst) ((inst) + 0x00000427) +#define BF_BF_0DE117D5_INFO(inst) ((inst) + 0x00000427), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0428_ADDR(inst) ((inst) + 0x00000428) +#define BF_BF_618A2DC8_INFO(inst) ((inst) + 0x00000428), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0429_ADDR(inst) ((inst) + 0x00000429) +#define BF_BF_A06D9CCD_INFO(inst) ((inst) + 0x00000429), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X042A_ADDR(inst) ((inst) + 0x0000042A) +#define BF_BF_18A52BE4_INFO(inst) ((inst) + 0x0000042A), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X042B_ADDR(inst) ((inst) + 0x0000042B) +#define BF_BF_C6446F22_INFO(inst) ((inst) + 0x0000042B), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X042C_ADDR(inst) ((inst) + 0x0000042C) +#define BF_BF_6CB70161_INFO(inst) ((inst) + 0x0000042C), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0450_ADDR(inst) ((inst) + 0x00000450) +#define BF_BF_BBD5ECD0_INFO(inst) ((inst) + 0x00000450), 0x00000100 +#define BF_BF_2F404EBF_INFO(inst) ((inst) + 0x00000450), 0x00000101 +#define BF_BF_7ECCDB5B_INFO(inst) ((inst) + 0x00000450), 0x00000102 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0800_ADDR(inst) ((inst) + 0x00000800) +#define BF_BF_6ED4125A_INFO(inst) ((inst) + 0x00000800), 0x00000300 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0801_ADDR(inst) ((inst) + 0x00000801) +#define BF_BF_B1AD16A3_INFO(inst) ((inst) + 0x00000801), 0x00000300 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0802_ADDR(inst) ((inst) + 0x00000802) +#define BF_BF_E7AAA3BF_INFO(inst) ((inst) + 0x00000802), 0x00000300 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0803_ADDR(inst) ((inst) + 0x00000803) +#define BF_BF_2FEF6326_INFO(inst) ((inst) + 0x00000803), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0804_ADDR(inst) ((inst) + 0x00000804) +#define BF_BF_B98C5ECC_INFO(inst) ((inst) + 0x00000804), 0x00000300 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0805_ADDR(inst) ((inst) + 0x00000805) +#define BF_BF_90325EF2_INFO(inst) ((inst) + 0x00000805), 0x00000300 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0806_ADDR(inst) ((inst) + 0x00000806) +#define BF_BF_0FE4E00B_INFO(inst) ((inst) + 0x00000806), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0807_ADDR(inst) ((inst) + 0x00000807) +#define BF_BF_FD01EA7D_INFO(inst) ((inst) + 0x00000807), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#define REG_BIAS_MODE_ADDR(inst) ((inst) + 0x00000808) +#define BF_BIAS_MODE_INFO(inst) ((inst) + 0x00000808), 0x00000100 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0809_ADDR(inst) ((inst) + 0x00000809) +#define BF_BF_E1937169_INFO(inst) ((inst) + 0x00000809), 0x00000100 +#define BF_BF_A7F8EA12_INFO(inst) ((inst) + 0x00000809), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X080A_ADDR(inst) ((inst) + 0x0000080A) +#define BF_BF_2C819551_INFO(inst) ((inst) + 0x0000080A), 0x00000400 +#define BF_BF_CF4506AF_INFO(inst) ((inst) + 0x0000080A), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X080B_ADDR(inst) ((inst) + 0x0000080B) +#define BF_BF_36D31A61_INFO(inst) ((inst) + 0x0000080B), 0x00000100 +#define BF_BF_48C25CC5_INFO(inst) ((inst) + 0x0000080B), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X080C_ADDR(inst) ((inst) + 0x0000080C) +#define BF_BF_C6671F96_INFO(inst) ((inst) + 0x0000080C), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X080D_ADDR(inst) ((inst) + 0x0000080D) +#define BF_BF_D150F5FB_INFO(inst) ((inst) + 0x0000080D), 0x00000100 +#define BF_BF_56B53ABF_INFO(inst) ((inst) + 0x0000080D), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X080E_ADDR(inst) ((inst) + 0x0000080E) +#define BF_BF_D8A97B37_INFO(inst) ((inst) + 0x0000080E), 0x00000400 +#define BF_BF_D70E1980_INFO(inst) ((inst) + 0x0000080E), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X080F_ADDR(inst) ((inst) + 0x0000080F) +#define BF_BF_125A913C_INFO(inst) ((inst) + 0x0000080F), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0810_ADDR(inst) ((inst) + 0x00000810) +#define BF_BF_F5D19006_INFO(inst) ((inst) + 0x00000810), 0x00000100 +#define BF_BF_C95EC6D7_INFO(inst) ((inst) + 0x00000810), 0x00000101 +#define BF_BF_EA68C9A3_INFO(inst) ((inst) + 0x00000810), 0x00000102 +#define BF_BF_7928739B_INFO(inst) ((inst) + 0x00000810), 0x00000103 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0811_ADDR(inst) ((inst) + 0x00000811) +#define BF_BF_61AC19DA_INFO(inst) ((inst) + 0x00000811), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0812_ADDR(inst) ((inst) + 0x00000812) +#define BF_BF_62A4A556_INFO(inst) ((inst) + 0x00000812), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0813_ADDR(inst) ((inst) + 0x00000813) +#define BF_BF_37CE76E1_INFO(inst) ((inst) + 0x00000813), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0814_ADDR(inst) ((inst) + 0x00000814) +#define BF_BF_38404F4D_INFO(inst) ((inst) + 0x00000814), 0x00000400 +#define BF_BF_DA2DCD9F_INFO(inst) ((inst) + 0x00000814), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0815_ADDR(inst) ((inst) + 0x00000815) +#define BF_BF_0E55E9C9_INFO(inst) ((inst) + 0x00000815), 0x00000400 +#define BF_BF_6DA49B8E_INFO(inst) ((inst) + 0x00000815), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0816_ADDR(inst) ((inst) + 0x00000816) +#define BF_BF_57DC81A4_INFO(inst) ((inst) + 0x00000816), 0x00000400 +#define BF_BF_E055177F_INFO(inst) ((inst) + 0x00000816), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0817_ADDR(inst) ((inst) + 0x00000817) +#define BF_BF_870215FD_INFO(inst) ((inst) + 0x00000817), 0x00000400 +#define BF_BF_21FFC997_INFO(inst) ((inst) + 0x00000817), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0818_ADDR(inst) ((inst) + 0x00000818) +#define BF_BF_CB2E7639_INFO(inst) ((inst) + 0x00000818), 0x00000400 +#define BF_BF_425B695E_INFO(inst) ((inst) + 0x00000818), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0819_ADDR(inst) ((inst) + 0x00000819) +#define BF_BF_3807D07C_INFO(inst) ((inst) + 0x00000819), 0x00000400 +#define BF_BF_9AD0FA1E_INFO(inst) ((inst) + 0x00000819), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X081A_ADDR(inst) ((inst) + 0x0000081A) +#define BF_BF_F81B06A8_INFO(inst) ((inst) + 0x0000081A), 0x00000400 +#define BF_BF_35397572_INFO(inst) ((inst) + 0x0000081A), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X081B_ADDR(inst) ((inst) + 0x0000081B) +#define BF_BF_337F98A3_INFO(inst) ((inst) + 0x0000081B), 0x00000400 +#define BF_BF_C50D3018_INFO(inst) ((inst) + 0x0000081B), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X081C_ADDR(inst) ((inst) + 0x0000081C) +#define BF_BF_3EB8AFDA_INFO(inst) ((inst) + 0x0000081C), 0x00000400 +#define BF_BF_9108630F_INFO(inst) ((inst) + 0x0000081C), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X081D_ADDR(inst) ((inst) + 0x0000081D) +#define BF_BF_FC68137A_INFO(inst) ((inst) + 0x0000081D), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0820_ADDR(inst) ((inst) + 0x00000820) +#define BF_BF_1F7436A4_INFO(inst) ((inst) + 0x00000820), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0821_ADDR(inst) ((inst) + 0x00000821) +#define BF_BF_7066C156_INFO(inst) ((inst) + 0x00000821), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0822_ADDR(inst) ((inst) + 0x00000822) +#define BF_BF_B1262357_INFO(inst) ((inst) + 0x00000822), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0823_ADDR(inst) ((inst) + 0x00000823) +#define BF_BF_50873D5A_INFO(inst) ((inst) + 0x00000823), 0x00000300 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0824_ADDR(inst) ((inst) + 0x00000824) +#define BF_BF_11498B75_INFO(inst) ((inst) + 0x00000824), 0x00000300 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0825_ADDR(inst) ((inst) + 0x00000825) +#define BF_BF_EE5FD1DB_INFO(inst) ((inst) + 0x00000825), 0x00000200 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0826_ADDR(inst) ((inst) + 0x00000826) +#define BF_BF_8EA05E7D_INFO(inst) ((inst) + 0x00000826), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0827_ADDR(inst) ((inst) + 0x00000827) +#define BF_BF_349B9412_INFO(inst) ((inst) + 0x00000827), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0828_ADDR(inst) ((inst) + 0x00000828) +#define BF_BF_5398A0B3_INFO(inst) ((inst) + 0x00000828), 0x00000300 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0829_ADDR(inst) ((inst) + 0x00000829) +#define BF_BF_709E6C26_INFO(inst) ((inst) + 0x00000829), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X082A_ADDR(inst) ((inst) + 0x0000082A) +#define BF_BF_6E917302_INFO(inst) ((inst) + 0x0000082A), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X082B_ADDR(inst) ((inst) + 0x0000082B) +#define BF_BF_62F2FF0D_INFO(inst) ((inst) + 0x0000082B), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X082C_ADDR(inst) ((inst) + 0x0000082C) +#define BF_BF_80D632ED_INFO(inst) ((inst) + 0x0000082C), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X082D_ADDR(inst) ((inst) + 0x0000082D) +#define BF_BF_2DC98F97_INFO(inst) ((inst) + 0x0000082D), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X082E_ADDR(inst) ((inst) + 0x0000082E) +#define BF_BF_27A681CF_INFO(inst) ((inst) + 0x0000082E), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X082F_ADDR(inst) ((inst) + 0x0000082F) +#define BF_BF_431EC858_INFO(inst) ((inst) + 0x0000082F), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0830_ADDR(inst) ((inst) + 0x00000830) +#define BF_BF_36E0AE84_INFO(inst) ((inst) + 0x00000830), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0831_ADDR(inst) ((inst) + 0x00000831) +#define BF_BF_D3AF6A04_INFO(inst) ((inst) + 0x00000831), 0x00000200 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0832_ADDR(inst) ((inst) + 0x00000832) +#define BF_BF_9A27FC53_INFO(inst) ((inst) + 0x00000832), 0x00000300 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0833_ADDR(inst) ((inst) + 0x00000833) +#define BF_BF_6AC65B90_INFO(inst) ((inst) + 0x00000833), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0834_ADDR(inst) ((inst) + 0x00000834) +#define BF_BF_822DED62_INFO(inst) ((inst) + 0x00000834), 0x00000300 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0835_ADDR(inst) ((inst) + 0x00000835) +#define BF_BF_417051D7_INFO(inst) ((inst) + 0x00000835), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0836_ADDR(inst) ((inst) + 0x00000836) +#define BF_BF_6FBB6357_INFO(inst) ((inst) + 0x00000836), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0837_ADDR(inst) ((inst) + 0x00000837) +#define BF_BF_80816734_INFO(inst) ((inst) + 0x00000837), 0x00000900 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0X0838_ADDR(inst) ((inst) + 0x00000838) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0839_ADDR(inst) ((inst) + 0x00000839) +#define BF_BF_F0BFE47D_INFO(inst) ((inst) + 0x00000839), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X083A_ADDR(inst) ((inst) + 0x0000083A) +#define BF_BF_548EA9EF_INFO(inst) ((inst) + 0x0000083A), 0x00000900 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0X083B_ADDR(inst) ((inst) + 0x0000083B) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X083C_ADDR(inst) ((inst) + 0x0000083C) +#define BF_BF_F93542A0_INFO(inst) ((inst) + 0x0000083C), 0x00000900 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0X083D_ADDR(inst) ((inst) + 0x0000083D) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X083E_ADDR(inst) ((inst) + 0x0000083E) +#define BF_BF_2CF5B5ED_INFO(inst) ((inst) + 0x0000083E), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X083F_ADDR(inst) ((inst) + 0x0000083F) +#define BF_BF_9F33742D_INFO(inst) ((inst) + 0x0000083F), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0840_ADDR(inst) ((inst) + 0x00000840) +#define BF_BF_1EA21983_INFO(inst) ((inst) + 0x00000840), 0x00000900 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0X0841_ADDR(inst) ((inst) + 0x00000841) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0842_ADDR(inst) ((inst) + 0x00000842) +#define BF_BF_6F85B04C_INFO(inst) ((inst) + 0x00000842), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0843_ADDR(inst) ((inst) + 0x00000843) +#define BF_BF_0AB24C19_INFO(inst) ((inst) + 0x00000843), 0x00000300 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0844_ADDR(inst) ((inst) + 0x00000844) +#define BF_BF_498BCAC3_INFO(inst) ((inst) + 0x00000844), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0845_ADDR(inst) ((inst) + 0x00000845) +#define BF_BF_07FF1574_INFO(inst) ((inst) + 0x00000845), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0846_ADDR(inst) ((inst) + 0x00000846) +#define BF_BF_BAC34A7D_INFO(inst) ((inst) + 0x00000846), 0x00000300 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0847_ADDR(inst) ((inst) + 0x00000847) +#define BF_BF_B825EFCD_INFO(inst) ((inst) + 0x00000847), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0848_ADDR(inst) ((inst) + 0x00000848) +#define BF_BF_C0056CA4_INFO(inst) ((inst) + 0x00000848), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0849_ADDR(inst) ((inst) + 0x00000849) +#define BF_BF_6C096A02_INFO(inst) ((inst) + 0x00000849), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X084A_ADDR(inst) ((inst) + 0x0000084A) +#define BF_BF_E0CBD4FB_INFO(inst) ((inst) + 0x0000084A), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X084B_ADDR(inst) ((inst) + 0x0000084B) +#define BF_BF_57CDC2DA_INFO(inst) ((inst) + 0x0000084B), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X084C_ADDR(inst) ((inst) + 0x0000084C) +#define BF_BF_BDD6BA21_INFO(inst) ((inst) + 0x0000084C), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X084D_ADDR(inst) ((inst) + 0x0000084D) +#define BF_BF_26F117D3_INFO(inst) ((inst) + 0x0000084D), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X084E_ADDR(inst) ((inst) + 0x0000084E) +#define BF_BF_BFB99502_INFO(inst) ((inst) + 0x0000084E), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X084F_ADDR(inst) ((inst) + 0x0000084F) +#define BF_BF_B0891CF7_INFO(inst) ((inst) + 0x0000084F), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0850_ADDR(inst) ((inst) + 0x00000850) +#define BF_BF_96145DD8_INFO(inst) ((inst) + 0x00000850), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0851_ADDR(inst) ((inst) + 0x00000851) +#define BF_BF_080BD1E5_INFO(inst) ((inst) + 0x00000851), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0852_ADDR(inst) ((inst) + 0x00000852) +#define BF_BF_C4ECC4FE_INFO(inst) ((inst) + 0x00000852), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0853_ADDR(inst) ((inst) + 0x00000853) +#define BF_BF_EE9D43DE_INFO(inst) ((inst) + 0x00000853), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0860_ADDR(inst) ((inst) + 0x00000860) +#define BF_BF_4AF75CD3_INFO(inst) ((inst) + 0x00000860), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0861_ADDR(inst) ((inst) + 0x00000861) +#define BF_BF_13E1B658_INFO(inst) ((inst) + 0x00000861), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0862_ADDR(inst) ((inst) + 0x00000862) +#define BF_BF_C9A41BAF_INFO(inst) ((inst) + 0x00000862), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0863_ADDR(inst) ((inst) + 0x00000863) +#define BF_BF_4B4BE0FB_INFO(inst) ((inst) + 0x00000863), 0x00000200 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0864_ADDR(inst) ((inst) + 0x00000864) +#define BF_BF_5DFB7F34_INFO(inst) ((inst) + 0x00000864), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0865_ADDR(inst) ((inst) + 0x00000865) +#define BF_BF_BEF691C4_INFO(inst) ((inst) + 0x00000865), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0870_ADDR(inst) ((inst) + 0x00000870) +#define BF_BF_08C91334_INFO(inst) ((inst) + 0x00000870), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0871_ADDR(inst) ((inst) + 0x00000871) +#define BF_BF_286AACF2_INFO(inst) ((inst) + 0x00000871), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#define REG_DC_DAC_ENABLE_ADDR(inst) ((inst) + 0x00000880) +#define BF_DC_DAC_ENABLE_INFO(inst) ((inst) + 0x00000880), 0x00000100 + +#define REG_DC_DAC_DATA0_ADDR(inst) ((inst) + 0x00000881) +#define BF_DC_DAC_DATA_INFO(inst) ((inst) + 0x00000881), 0x00000D00 + +#define REG_DC_DAC_DATA1_ADDR(inst) ((inst) + 0x00000882) + +#define REG_DC_DAC_LATCH_P_ADDR(inst) ((inst) + 0x00000883) +#define BF_DC_DAC_LATCH_P_INFO(inst) ((inst) + 0x00000883), 0x00000100 + +#define REG_DC_DAC_LATCH_N_ADDR(inst) ((inst) + 0x00000884) +#define BF_DC_DAC_LATCH_N_INFO(inst) ((inst) + 0x00000884), 0x00000100 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0890_ADDR(inst) ((inst) + 0x00000890) +#define BF_BF_4A5DBE9A_INFO(inst) ((inst) + 0x00000890), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0891_ADDR(inst) ((inst) + 0x00000891) +#define BF_BF_2B6942FC_INFO(inst) ((inst) + 0x00000891), 0x00000100 +#define BF_BF_1DA8B768_INFO(inst) ((inst) + 0x00000891), 0x00000101 +#define BF_BF_0B37568F_INFO(inst) ((inst) + 0x00000891), 0x00000102 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0892_ADDR(inst) ((inst) + 0x00000892) +#define BF_BF_56C723B1_INFO(inst) ((inst) + 0x00000892), 0x00000100 +#define BF_BF_0A1A0871_INFO(inst) ((inst) + 0x00000892), 0x00000101 +#define BF_BF_5362CEC4_INFO(inst) ((inst) + 0x00000892), 0x00000102 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0X0893_ADDR(inst) ((inst) + 0x00000893) +#define BF_BF_AA48D3AB_INFO(inst) ((inst) + 0x00000893), 0x00000100 +#define BF_BF_FA0D1E07_INFO(inst) ((inst) + 0x00000893), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#endif /* __ADI_APOLLO_BF_RAPTOR_OPEN_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_rc_tuner_analog.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_rc_tuner_analog.h new file mode 100644 index 00000000000000..0b1636686e3252 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_rc_tuner_analog.h @@ -0,0 +1,59 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:20 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_RC_TUNER_ANALOG_H__ +#define __ADI_APOLLO_BF_RC_TUNER_ANALOG_H__ + +/*============= D E F I N E S ==============*/ +#define RC_TUNER0 0x4C001B00 +#define RC_TUNER1 0x4C001F00 + +#define REG_RC_TUNER_CTRL_ADDR(inst) ((inst) + 0x00000000) +#define BF_RXADC_PD_INFO(inst) ((inst) + 0x00000000), 0x00000100 +#define BF_RXADC_RCAL_START_INFO(inst) ((inst) + 0x00000000), 0x00000101 +#define BF_RXADC_CCAL_START_INFO(inst) ((inst) + 0x00000000), 0x00000102 +#define BF_RXADC_PD_REF_INFO(inst) ((inst) + 0x00000000), 0x00000103 + +#define REG_RC_TUNER_CAP_MSB_ADDR(inst) ((inst) + 0x00000001) + +#define REG_RC_TUNER_CAP_LSB_ADDR(inst) ((inst) + 0x00000002) +#define BF_RXADC_CAP_SCALE_CONST_INFO(inst) ((inst) + 0x00000002), 0x00000C00 + +#define REG_RC_TUNER_CAP_SCALE_MSB_ADDR(inst) ((inst) + 0x00000003) + +#define REG_RC_TUNER_CAP_SCALE_LSB_ADDR(inst) ((inst) + 0x00000004) +#define BF_RXADC_G_SCALE_CONST_INFO(inst) ((inst) + 0x00000004), 0x00000C00 + +#define REG_RC_TUNER_MEAS1_LSB_ADDR(inst) ((inst) + 0x00000005) +#define BF_RXADC_G_MEASURED_1_INFO(inst) ((inst) + 0x00000005), 0x00000C00 + +#define REG_RC_TUNER_MEAS1_MSB_ADDR(inst) ((inst) + 0x00000006) + +#define REG_RC_TUNER_MEAS2_MSB_ADDR(inst) ((inst) + 0x00000007) + +#define REG_RC_TUNER_MEAS2_LSB_ADDR(inst) ((inst) + 0x00000008) +#define BF_RXADC_G_MEASURED_2_INFO(inst) ((inst) + 0x00000008), 0x00000C00 + +#define REG_RC_TUNER_COUNT_N1_MSB_ADDR(inst) ((inst) + 0x00000009) + +#define REG_RC_TUNER_COUNT_N1_LSB_ADDR(inst) ((inst) + 0x0000000A) +#define BF_RXADC_N1_COUNT_INFO(inst) ((inst) + 0x0000000A), 0x00000B00 + +#define REG_RC_TUNER_COUNT_N2_MSB_ADDR(inst) ((inst) + 0x0000000B) + +#define REG_RC_TUNER_COUNT_N2_LSB_ADDR(inst) ((inst) + 0x0000000C) +#define BF_RXADC_N2_COUNT_INFO(inst) ((inst) + 0x0000000C), 0x00000B00 + +#endif /* __ADI_APOLLO_BF_RC_TUNER_ANALOG_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_rsa.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_rsa.h new file mode 100644 index 00000000000000..ac842990628a50 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_rsa.h @@ -0,0 +1,839 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:21 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_RSA_H__ +#define __ADI_APOLLO_BF_RSA_H__ + +/*============= D E F I N E S ==============*/ +#ifdef USE_PRIVATE_BF +#define REG_EC_DAC_SPI_0_ADDR 0x4C004400 +#define BF_NVM_EC_TOTX_SPI_INFO 0x4C004400, 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_EC_DAC_SPI_1_ADDR 0x4C004401 + +#define REG_EC_DAC_SPI_2_ADDR 0x4C004402 + +#define REG_EC_DAC_SPI_3_ADDR 0x4C004403 + +#ifdef USE_PRIVATE_BF +#define REG_EC_DAC_REAL_0_ADDR 0x4C004404 +#define BF_NVM_EC_TOTX_REAL_INFO 0x4C004404, 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_EC_DAC_REAL_1_ADDR 0x4C004405 + +#define REG_EC_DAC_REAL_2_ADDR 0x4C004406 + +#define REG_EC_DAC_REAL_3_ADDR 0x4C004407 + +#ifdef USE_PRIVATE_BF +#define REG_EC_ADC_SPI_0_ADDR 0x4C004408 +#define BF_NVM_EC_TORX_SPI_INFO 0x4C004408, 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_EC_ADC_SPI_1_ADDR 0x4C004409 + +#define REG_EC_ADC_SPI_2_ADDR 0x4C00440A + +#define REG_EC_ADC_SPI_3_ADDR 0x4C00440B + +#ifdef USE_PRIVATE_BF +#define REG_EC_ADC_REAL_0_ADDR 0x4C00440C +#define BF_NVM_EC_TORX_REAL_INFO 0x4C00440C, 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_EC_ADC_REAL_1_ADDR 0x4C00440D + +#define REG_EC_ADC_REAL_2_ADDR 0x4C00440E + +#define REG_EC_ADC_REAL_3_ADDR 0x4C00440F + +#ifdef USE_PRIVATE_BF +#define REG_EC_ANA_SPI_0_ADDR 0x4C004410 +#define BF_NVM_EC_TOANA_SPI_INFO 0x4C004410, 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_EC_ANA_SPI_1_ADDR 0x4C004411 + +#define REG_EC_ANA_SPI_2_ADDR 0x4C004412 + +#define REG_EC_ANA_SPI_3_ADDR 0x4C004413 + +#ifdef USE_PRIVATE_BF +#define REG_EC_ANA_REAL_0_ADDR 0x4C004414 +#define BF_NVM_EC_TOANA_REAL_INFO 0x4C004414, 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_EC_ANA_REAL_1_ADDR 0x4C004415 + +#define REG_EC_ANA_REAL_2_ADDR 0x4C004416 + +#define REG_EC_ANA_REAL_3_ADDR 0x4C004417 + +#ifdef USE_PRIVATE_BF +#define REG_EC_GENERAL_0_ADDR 0x4C004418 +#define BF_EC_GENERAL_REAL_INFO 0x4C004418, 0x00004000 +#endif /* USE_PRIVATE_BF */ + +#define REG_EC_GENERAL_1_ADDR 0x4C004419 + +#define REG_EC_GENERAL_2_ADDR 0x4C00441A + +#define REG_EC_GENERAL_3_ADDR 0x4C00441B + +#define REG_EC_GENERAL_4_ADDR 0x4C00441C + +#define REG_EC_GENERAL_5_ADDR 0x4C00441D + +#define REG_EC_GENERAL_6_ADDR 0x4C00441E + +#define REG_EC_GENERAL_7_ADDR 0x4C00441F + +#define REG_RSA_CTRL_ADDR 0x4C004420 +#define BF_RSA_DECRYPT_EN_INFO 0x4C004420, 0x00000100 +#define BF_RSA_CLK_EN_INFO 0x4C004420, 0x00000101 +#define BF_RSA_DECRYPT_DONE_INFO 0x4C004420, 0x00000103 +#define BF_RSA_CHIP_UNLOCK_INFO 0x4C004420, 0x00000104 +#define BF_RSA_GROUP_UNLOCK_INFO 0x4C004420, 0x00000105 +#define BF_RSA_DECRYPT_CRC_FAIL_INFO 0x4C004420, 0x00000106 +#define BF_RSA_DECRYPT_ZERO_FAIL_INFO 0x4C004420, 0x00000107 + +#define REG_RSA_IN_M_0_ADDR 0x4C004421 + +#define REG_RSA_IN_M_1_ADDR 0x4C004422 + +#define REG_RSA_IN_M_2_ADDR 0x4C004423 + +#define REG_RSA_IN_M_3_ADDR 0x4C004424 + +#define REG_RSA_IN_M_4_ADDR 0x4C004425 + +#define REG_RSA_IN_M_5_ADDR 0x4C004426 + +#define REG_RSA_IN_M_6_ADDR 0x4C004427 + +#define REG_RSA_IN_M_7_ADDR 0x4C004428 + +#define REG_RSA_IN_M_8_ADDR 0x4C004429 + +#define REG_RSA_IN_M_9_ADDR 0x4C00442A + +#define REG_RSA_IN_M_10_ADDR 0x4C00442B + +#define REG_RSA_IN_M_11_ADDR 0x4C00442C + +#define REG_RSA_IN_M_12_ADDR 0x4C00442D + +#define REG_RSA_IN_M_13_ADDR 0x4C00442E + +#define REG_RSA_IN_M_14_ADDR 0x4C00442F + +#define REG_RSA_IN_M_15_ADDR 0x4C004430 + +#define REG_RSA_IN_M_16_ADDR 0x4C004431 + +#define REG_RSA_IN_M_17_ADDR 0x4C004432 + +#define REG_RSA_IN_M_18_ADDR 0x4C004433 + +#define REG_RSA_IN_M_19_ADDR 0x4C004434 + +#define REG_RSA_IN_M_20_ADDR 0x4C004435 + +#define REG_RSA_IN_M_21_ADDR 0x4C004436 + +#define REG_RSA_IN_M_22_ADDR 0x4C004437 + +#define REG_RSA_IN_M_23_ADDR 0x4C004438 + +#define REG_RSA_IN_M_24_ADDR 0x4C004439 + +#define REG_RSA_IN_M_25_ADDR 0x4C00443A + +#define REG_RSA_IN_M_26_ADDR 0x4C00443B + +#define REG_RSA_IN_M_27_ADDR 0x4C00443C + +#define REG_RSA_IN_M_28_ADDR 0x4C00443D + +#define REG_RSA_IN_M_29_ADDR 0x4C00443E + +#define REG_RSA_IN_M_30_ADDR 0x4C00443F + +#define REG_RSA_IN_M_31_ADDR 0x4C004440 + +#define REG_RSA_IN_M_32_ADDR 0x4C004441 + +#define REG_RSA_IN_M_33_ADDR 0x4C004442 + +#define REG_RSA_IN_M_34_ADDR 0x4C004443 + +#define REG_RSA_IN_M_35_ADDR 0x4C004444 + +#define REG_RSA_IN_M_36_ADDR 0x4C004445 + +#define REG_RSA_IN_M_37_ADDR 0x4C004446 + +#define REG_RSA_IN_M_38_ADDR 0x4C004447 + +#define REG_RSA_IN_M_39_ADDR 0x4C004448 + +#define REG_RSA_IN_M_40_ADDR 0x4C004449 + +#define REG_RSA_IN_M_41_ADDR 0x4C00444A + +#define REG_RSA_IN_M_42_ADDR 0x4C00444B + +#define REG_RSA_IN_M_43_ADDR 0x4C00444C + +#define REG_RSA_IN_M_44_ADDR 0x4C00444D + +#define REG_RSA_IN_M_45_ADDR 0x4C00444E + +#define REG_RSA_IN_M_46_ADDR 0x4C00444F + +#define REG_RSA_IN_M_47_ADDR 0x4C004450 + +#define REG_RSA_IN_M_48_ADDR 0x4C004451 + +#define REG_RSA_IN_M_49_ADDR 0x4C004452 + +#define REG_RSA_IN_M_50_ADDR 0x4C004453 + +#define REG_RSA_IN_M_51_ADDR 0x4C004454 + +#define REG_RSA_IN_M_52_ADDR 0x4C004455 + +#define REG_RSA_IN_M_53_ADDR 0x4C004456 + +#define REG_RSA_IN_M_54_ADDR 0x4C004457 + +#define REG_RSA_IN_M_55_ADDR 0x4C004458 + +#define REG_RSA_IN_M_56_ADDR 0x4C004459 + +#define REG_RSA_IN_M_57_ADDR 0x4C00445A + +#define REG_RSA_IN_M_58_ADDR 0x4C00445B + +#define REG_RSA_IN_M_59_ADDR 0x4C00445C + +#define REG_RSA_IN_M_60_ADDR 0x4C00445D + +#define REG_RSA_IN_M_61_ADDR 0x4C00445E + +#define REG_RSA_IN_M_62_ADDR 0x4C00445F + +#define REG_RSA_IN_M_63_ADDR 0x4C004460 + +#define REG_RSA_IN_M_64_ADDR 0x4C004461 + +#define REG_RSA_IN_M_65_ADDR 0x4C004462 + +#define REG_RSA_IN_M_66_ADDR 0x4C004463 + +#define REG_RSA_IN_M_67_ADDR 0x4C004464 + +#define REG_RSA_IN_M_68_ADDR 0x4C004465 + +#define REG_RSA_IN_M_69_ADDR 0x4C004466 + +#define REG_RSA_IN_M_70_ADDR 0x4C004467 + +#define REG_RSA_IN_M_71_ADDR 0x4C004468 + +#define REG_RSA_IN_M_72_ADDR 0x4C004469 + +#define REG_RSA_IN_M_73_ADDR 0x4C00446A + +#define REG_RSA_IN_M_74_ADDR 0x4C00446B + +#define REG_RSA_IN_M_75_ADDR 0x4C00446C + +#define REG_RSA_IN_M_76_ADDR 0x4C00446D + +#define REG_RSA_IN_M_77_ADDR 0x4C00446E + +#define REG_RSA_IN_M_78_ADDR 0x4C00446F + +#define REG_RSA_IN_M_79_ADDR 0x4C004470 + +#define REG_RSA_IN_M_80_ADDR 0x4C004471 + +#define REG_RSA_IN_M_81_ADDR 0x4C004472 + +#define REG_RSA_IN_M_82_ADDR 0x4C004473 + +#define REG_RSA_IN_M_83_ADDR 0x4C004474 + +#define REG_RSA_IN_M_84_ADDR 0x4C004475 + +#define REG_RSA_IN_M_85_ADDR 0x4C004476 + +#define REG_RSA_IN_M_86_ADDR 0x4C004477 + +#define REG_RSA_IN_M_87_ADDR 0x4C004478 + +#define REG_RSA_IN_M_88_ADDR 0x4C004479 + +#define REG_RSA_IN_M_89_ADDR 0x4C00447A + +#define REG_RSA_IN_M_90_ADDR 0x4C00447B + +#define REG_RSA_IN_M_91_ADDR 0x4C00447C + +#define REG_RSA_IN_M_92_ADDR 0x4C00447D + +#define REG_RSA_IN_M_93_ADDR 0x4C00447E + +#define REG_RSA_IN_M_94_ADDR 0x4C00447F + +#define REG_RSA_IN_M_95_ADDR 0x4C004480 + +#define REG_RSA_IN_M_96_ADDR 0x4C004481 + +#define REG_RSA_IN_M_97_ADDR 0x4C004482 + +#define REG_RSA_IN_M_98_ADDR 0x4C004483 + +#define REG_RSA_IN_M_99_ADDR 0x4C004484 + +#define REG_RSA_IN_M_100_ADDR 0x4C004485 + +#define REG_RSA_IN_M_101_ADDR 0x4C004486 + +#define REG_RSA_IN_M_102_ADDR 0x4C004487 + +#define REG_RSA_IN_M_103_ADDR 0x4C004488 + +#define REG_RSA_IN_M_104_ADDR 0x4C004489 + +#define REG_RSA_IN_M_105_ADDR 0x4C00448A + +#define REG_RSA_IN_M_106_ADDR 0x4C00448B + +#define REG_RSA_IN_M_107_ADDR 0x4C00448C + +#define REG_RSA_IN_M_108_ADDR 0x4C00448D + +#define REG_RSA_IN_M_109_ADDR 0x4C00448E + +#define REG_RSA_IN_M_110_ADDR 0x4C00448F + +#define REG_RSA_IN_M_111_ADDR 0x4C004490 + +#define REG_RSA_IN_M_112_ADDR 0x4C004491 + +#define REG_RSA_IN_M_113_ADDR 0x4C004492 + +#define REG_RSA_IN_M_114_ADDR 0x4C004493 + +#define REG_RSA_IN_M_115_ADDR 0x4C004494 + +#define REG_RSA_IN_M_116_ADDR 0x4C004495 + +#define REG_RSA_IN_M_117_ADDR 0x4C004496 + +#define REG_RSA_IN_M_118_ADDR 0x4C004497 + +#define REG_RSA_IN_M_119_ADDR 0x4C004498 + +#define REG_RSA_IN_M_120_ADDR 0x4C004499 + +#define REG_RSA_IN_M_121_ADDR 0x4C00449A + +#define REG_RSA_IN_M_122_ADDR 0x4C00449B + +#define REG_RSA_IN_M_123_ADDR 0x4C00449C + +#define REG_RSA_IN_M_124_ADDR 0x4C00449D + +#define REG_RSA_IN_M_125_ADDR 0x4C00449E + +#define REG_RSA_IN_M_126_ADDR 0x4C00449F + +#define REG_RSA_IN_M_127_ADDR 0x4C0044A0 + +#define REG_RSA_IN_M_128_ADDR 0x4C0044A1 + +#define REG_RSA_IN_M_129_ADDR 0x4C0044A2 + +#define REG_RSA_IN_M_130_ADDR 0x4C0044A3 + +#define REG_RSA_IN_M_131_ADDR 0x4C0044A4 + +#define REG_RSA_IN_M_132_ADDR 0x4C0044A5 + +#define REG_RSA_IN_M_133_ADDR 0x4C0044A6 + +#define REG_RSA_IN_M_134_ADDR 0x4C0044A7 + +#define REG_RSA_IN_M_135_ADDR 0x4C0044A8 + +#define REG_RSA_IN_M_136_ADDR 0x4C0044A9 + +#define REG_RSA_IN_M_137_ADDR 0x4C0044AA + +#define REG_RSA_IN_M_138_ADDR 0x4C0044AB + +#define REG_RSA_IN_M_139_ADDR 0x4C0044AC + +#define REG_RSA_IN_M_140_ADDR 0x4C0044AD + +#define REG_RSA_IN_M_141_ADDR 0x4C0044AE + +#define REG_RSA_IN_M_142_ADDR 0x4C0044AF + +#define REG_RSA_IN_M_143_ADDR 0x4C0044B0 + +#define REG_RSA_IN_M_144_ADDR 0x4C0044B1 + +#define REG_RSA_IN_M_145_ADDR 0x4C0044B2 + +#define REG_RSA_IN_M_146_ADDR 0x4C0044B3 + +#define REG_RSA_IN_M_147_ADDR 0x4C0044B4 + +#define REG_RSA_IN_M_148_ADDR 0x4C0044B5 + +#define REG_RSA_IN_M_149_ADDR 0x4C0044B6 + +#define REG_RSA_IN_M_150_ADDR 0x4C0044B7 + +#define REG_RSA_IN_M_151_ADDR 0x4C0044B8 + +#define REG_RSA_IN_M_152_ADDR 0x4C0044B9 + +#define REG_RSA_IN_M_153_ADDR 0x4C0044BA + +#define REG_RSA_IN_M_154_ADDR 0x4C0044BB + +#define REG_RSA_IN_M_155_ADDR 0x4C0044BC + +#define REG_RSA_IN_M_156_ADDR 0x4C0044BD + +#define REG_RSA_IN_M_157_ADDR 0x4C0044BE + +#define REG_RSA_IN_M_158_ADDR 0x4C0044BF + +#define REG_RSA_IN_M_159_ADDR 0x4C0044C0 + +#define REG_RSA_IN_M_160_ADDR 0x4C0044C1 + +#define REG_RSA_IN_M_161_ADDR 0x4C0044C2 + +#define REG_RSA_IN_M_162_ADDR 0x4C0044C3 + +#define REG_RSA_IN_M_163_ADDR 0x4C0044C4 + +#define REG_RSA_IN_M_164_ADDR 0x4C0044C5 + +#define REG_RSA_IN_M_165_ADDR 0x4C0044C6 + +#define REG_RSA_IN_M_166_ADDR 0x4C0044C7 + +#define REG_RSA_IN_M_167_ADDR 0x4C0044C8 + +#define REG_RSA_IN_M_168_ADDR 0x4C0044C9 + +#define REG_RSA_IN_M_169_ADDR 0x4C0044CA + +#define REG_RSA_IN_M_170_ADDR 0x4C0044CB + +#define REG_RSA_IN_M_171_ADDR 0x4C0044CC + +#define REG_RSA_IN_M_172_ADDR 0x4C0044CD + +#define REG_RSA_IN_M_173_ADDR 0x4C0044CE + +#define REG_RSA_IN_M_174_ADDR 0x4C0044CF + +#define REG_RSA_IN_M_175_ADDR 0x4C0044D0 + +#define REG_RSA_IN_M_176_ADDR 0x4C0044D1 + +#define REG_RSA_IN_M_177_ADDR 0x4C0044D2 + +#define REG_RSA_IN_M_178_ADDR 0x4C0044D3 + +#define REG_RSA_IN_M_179_ADDR 0x4C0044D4 + +#define REG_RSA_IN_M_180_ADDR 0x4C0044D5 + +#define REG_RSA_IN_M_181_ADDR 0x4C0044D6 + +#define REG_RSA_IN_M_182_ADDR 0x4C0044D7 + +#define REG_RSA_IN_M_183_ADDR 0x4C0044D8 + +#define REG_RSA_IN_M_184_ADDR 0x4C0044D9 + +#define REG_RSA_IN_M_185_ADDR 0x4C0044DA + +#define REG_RSA_IN_M_186_ADDR 0x4C0044DB + +#define REG_RSA_IN_M_187_ADDR 0x4C0044DC + +#define REG_RSA_IN_M_188_ADDR 0x4C0044DD + +#define REG_RSA_IN_M_189_ADDR 0x4C0044DE + +#define REG_RSA_IN_M_190_ADDR 0x4C0044DF + +#define REG_RSA_IN_M_191_ADDR 0x4C0044E0 + +#define REG_RSA_IN_M_192_ADDR 0x4C0044E1 + +#define REG_RSA_IN_M_193_ADDR 0x4C0044E2 + +#define REG_RSA_IN_M_194_ADDR 0x4C0044E3 + +#define REG_RSA_IN_M_195_ADDR 0x4C0044E4 + +#define REG_RSA_IN_M_196_ADDR 0x4C0044E5 + +#define REG_RSA_IN_M_197_ADDR 0x4C0044E6 + +#define REG_RSA_IN_M_198_ADDR 0x4C0044E7 + +#define REG_RSA_IN_M_199_ADDR 0x4C0044E8 + +#define REG_RSA_IN_M_200_ADDR 0x4C0044E9 + +#define REG_RSA_IN_M_201_ADDR 0x4C0044EA + +#define REG_RSA_IN_M_202_ADDR 0x4C0044EB + +#define REG_RSA_IN_M_203_ADDR 0x4C0044EC + +#define REG_RSA_IN_M_204_ADDR 0x4C0044ED + +#define REG_RSA_IN_M_205_ADDR 0x4C0044EE + +#define REG_RSA_IN_M_206_ADDR 0x4C0044EF + +#define REG_RSA_IN_M_207_ADDR 0x4C0044F0 + +#define REG_RSA_IN_M_208_ADDR 0x4C0044F1 + +#define REG_RSA_IN_M_209_ADDR 0x4C0044F2 + +#define REG_RSA_IN_M_210_ADDR 0x4C0044F3 + +#define REG_RSA_IN_M_211_ADDR 0x4C0044F4 + +#define REG_RSA_IN_M_212_ADDR 0x4C0044F5 + +#define REG_RSA_IN_M_213_ADDR 0x4C0044F6 + +#define REG_RSA_IN_M_214_ADDR 0x4C0044F7 + +#define REG_RSA_IN_M_215_ADDR 0x4C0044F8 + +#define REG_RSA_IN_M_216_ADDR 0x4C0044F9 + +#define REG_RSA_IN_M_217_ADDR 0x4C0044FA + +#define REG_RSA_IN_M_218_ADDR 0x4C0044FB + +#define REG_RSA_IN_M_219_ADDR 0x4C0044FC + +#define REG_RSA_IN_M_220_ADDR 0x4C0044FD + +#define REG_RSA_IN_M_221_ADDR 0x4C0044FE + +#define REG_RSA_IN_M_222_ADDR 0x4C0044FF + +#define REG_RSA_IN_M_223_ADDR 0x4C004500 + +#define REG_RSA_IN_M_224_ADDR 0x4C004501 + +#define REG_RSA_IN_M_225_ADDR 0x4C004502 + +#define REG_RSA_IN_M_226_ADDR 0x4C004503 + +#define REG_RSA_IN_M_227_ADDR 0x4C004504 + +#define REG_RSA_IN_M_228_ADDR 0x4C004505 + +#define REG_RSA_IN_M_229_ADDR 0x4C004506 + +#define REG_RSA_IN_M_230_ADDR 0x4C004507 + +#define REG_RSA_IN_M_231_ADDR 0x4C004508 + +#define REG_RSA_IN_M_232_ADDR 0x4C004509 + +#define REG_RSA_IN_M_233_ADDR 0x4C00450A + +#define REG_RSA_IN_M_234_ADDR 0x4C00450B + +#define REG_RSA_IN_M_235_ADDR 0x4C00450C + +#define REG_RSA_IN_M_236_ADDR 0x4C00450D + +#define REG_RSA_IN_M_237_ADDR 0x4C00450E + +#define REG_RSA_IN_M_238_ADDR 0x4C00450F + +#define REG_RSA_IN_M_239_ADDR 0x4C004510 + +#define REG_RSA_IN_M_240_ADDR 0x4C004511 + +#define REG_RSA_IN_M_241_ADDR 0x4C004512 + +#define REG_RSA_IN_M_242_ADDR 0x4C004513 + +#define REG_RSA_IN_M_243_ADDR 0x4C004514 + +#define REG_RSA_IN_M_244_ADDR 0x4C004515 + +#define REG_RSA_IN_M_245_ADDR 0x4C004516 + +#define REG_RSA_IN_M_246_ADDR 0x4C004517 + +#define REG_RSA_IN_M_247_ADDR 0x4C004518 + +#define REG_RSA_IN_M_248_ADDR 0x4C004519 + +#define REG_RSA_IN_M_249_ADDR 0x4C00451A + +#define REG_RSA_IN_M_250_ADDR 0x4C00451B + +#define REG_RSA_IN_M_251_ADDR 0x4C00451C + +#define REG_RSA_IN_M_252_ADDR 0x4C00451D + +#define REG_RSA_IN_M_253_ADDR 0x4C00451E + +#define REG_RSA_IN_M_254_ADDR 0x4C00451F + +#define REG_RSA_IN_M_255_ADDR 0x4C004520 + +#define REG_CHIPID_0_RSA_ADDR 0x4C004521 + +#define REG_CHIPID_1_RSA_ADDR 0x4C004522 + +#define REG_CHIPID_2_RSA_ADDR 0x4C004523 + +#define REG_CHIPID_3_RSA_ADDR 0x4C004524 + +#define REG_CHIPID_4_RSA_ADDR 0x4C004525 + +#define REG_CHIPID_5_RSA_ADDR 0x4C004526 + +#define REG_CHIPID_6_RSA_ADDR 0x4C004527 + +#define REG_CHIPID_7_RSA_ADDR 0x4C004528 + +#define REG_CHIPID_8_RSA_ADDR 0x4C004529 + +#define REG_CHIPID_9_RSA_ADDR 0x4C00452A + +#define REG_CHIPID_10_RSA_ADDR 0x4C00452B + +#define REG_CHIPID_11_RSA_ADDR 0x4C00452C + +#define REG_CHIPID_12_RSA_ADDR 0x4C00452D + +#define REG_CHIPID_13_RSA_ADDR 0x4C00452E + +#define REG_CHIPID_14_RSA_ADDR 0x4C00452F + +#define REG_CHIPID_15_RSA_ADDR 0x4C004530 + +#define REG_GROUPID_0_RSA_ADDR 0x4C004531 +#define BF_GROUPID_INFO 0x4C004531, 0x00002000 + +#define REG_GROUPID_1_RSA_ADDR 0x4C004532 + +#define REG_GROUPID_2_RSA_ADDR 0x4C004533 + +#define REG_GROUPID_3_RSA_ADDR 0x4C004534 + +#define REG_DUT_REG_REV_ADDR 0x4C004535 +#define BF_DUT_REG_REV_INFO 0x4C004535, 0x00000800 + +#define REG_ATE_ID_ADDR 0x4C004536 +#define BF_ATE_ID_INFO 0x4C004536, 0x00000800 + +#define REG_HIB_INFO_0_ADDR 0x4C004537 +#define BF_HIB_INFO_0_INFO 0x4C004537, 0x00000800 + +#define REG_HIB_INFO_1_ADDR 0x4C004538 +#define BF_HIB_INFO_1_INFO 0x4C004538, 0x00000800 + +#define REG_FUSE_INFO_ADDR 0x4C004539 +#define BF_FUSE_INFO_INFO 0x4C004539, 0x00000800 + +#define REG_PROGRAM_REV_0_ADDR 0x4C00453A +#define BF_PROGRAM_REV_0_INFO 0x4C00453A, 0x00000800 + +#define REG_PROGRAM_REV_1_ADDR 0x4C00453B +#define BF_PROGRAM_REV_1_INFO 0x4C00453B, 0x00000800 + +#define REG_DATE_0_ADDR 0x4C00453C +#define BF_DATE_0_INFO 0x4C00453C, 0x00000800 + +#define REG_DATE_1_ADDR 0x4C00453D +#define BF_DATE_1_INFO 0x4C00453D, 0x00000800 + +#define REG_SEQUENTIAL_SN_0_RSA_ADDR 0x4C00453E +#define BF_SEQUENTIAL_SN_0_RSA_INFO 0x4C00453E, 0x00000800 + +#define REG_SEQUENTIAL_SN_1_RSA_ADDR 0x4C00453F +#define BF_SEQUENTIAL_SN_1_RSA_INFO 0x4C00453F, 0x00000800 + +#define REG_FPGA_PROGRAM_ID_ADDR 0x4C004540 +#define BF_FPGA_PROGRAM_ID_INFO 0x4C004540, 0x00000800 + +#define REG_FUSE_PASSED_ADDR 0x4C004541 +#define BF_FUSE_PASSED_INFO 0x4C004541, 0x00000800 + +#define REG_SPARE_0_RSA_ADDR 0x4C004542 +#define BF_SPARE_0_INFO 0x4C004542, 0x00000800 + +#define REG_SPARE_1_RSA_ADDR 0x4C004543 +#define BF_SPARE_1_INFO 0x4C004543, 0x00000800 + +#define REG_SPARE_2_RSA_ADDR 0x4C004544 +#define BF_SPARE_2_INFO 0x4C004544, 0x00000800 + +#define REG_SPARE_3_RSA_ADDR 0x4C004545 +#define BF_SPARE_3_INFO 0x4C004545, 0x00000800 + +#define REG_SPARE_4_ADDR 0x4C004546 +#define BF_SPARE_4_INFO 0x4C004546, 0x00000800 + +#define REG_SPARE_5_ADDR 0x4C004547 +#define BF_SPARE_5_INFO 0x4C004547, 0x00000800 + +#define REG_SPARE_6_ADDR 0x4C004548 +#define BF_SPARE_6_INFO 0x4C004548, 0x00000800 + +#define REG_SPARE_7_ADDR 0x4C004549 +#define BF_SPARE_7_INFO 0x4C004549, 0x00000800 + +#define REG_SPARE_8_ADDR 0x4C00454A +#define BF_SPARE_8_INFO 0x4C00454A, 0x00000800 + +#define REG_SPARE_9_ADDR 0x4C00454B +#define BF_SPARE_9_INFO 0x4C00454B, 0x00000800 + +#define REG_SPARE_10_ADDR 0x4C00454C +#define BF_SPARE_10_INFO 0x4C00454C, 0x00000800 + +#define REG_SPARE_11_ADDR 0x4C00454D +#define BF_SPARE_11_INFO 0x4C00454D, 0x00000800 + +#define REG_SPARE_12_ADDR 0x4C00454E +#define BF_SPARE_12_INFO 0x4C00454E, 0x00000800 + +#define REG_SPARE_13_ADDR 0x4C00454F +#define BF_SPARE_13_INFO 0x4C00454F, 0x00000800 + +#define REG_SPARE_14_ADDR 0x4C004550 +#define BF_SPARE_14_INFO 0x4C004550, 0x00000800 + +#define REG_RESERVED_0_ADDR 0x4C004551 +#define BF_RESERVED_0_INFO 0x4C004551, 0x00000800 + +#define REG_RESERVED_1_ADDR 0x4C004552 +#define BF_RESERVED_1_INFO 0x4C004552, 0x00000800 + +#define REG_RESERVED_2_ADDR 0x4C004553 +#define BF_RESERVED_2_INFO 0x4C004553, 0x00000800 + +#define REG_RESERVED_3_ADDR 0x4C004554 +#define BF_RESERVED_3_INFO 0x4C004554, 0x00000800 + +#define REG_RESERVED_4_ADDR 0x4C004555 +#define BF_RESERVED_4_INFO 0x4C004555, 0x00000800 + +#define REG_RESERVED_5_ADDR 0x4C004556 +#define BF_RESERVED_5_INFO 0x4C004556, 0x00000800 + +#define REG_FW_REV_CTRL_0_L_ADDR 0x4C004557 +#define BF_FW_REV_CTRL_0_INFO 0x4C004557, 0x00001800 + +#define REG_FW_REV_CTRL_0_M_ADDR 0x4C004558 + +#define REG_FW_REV_CTRL_0_H_ADDR 0x4C004559 + +#define REG_FW_REV_CTRL_1_L_ADDR 0x4C00455A +#define BF_FW_REV_CTRL_1_INFO 0x4C00455A, 0x00001800 + +#define REG_FW_REV_CTRL_1_M_ADDR 0x4C00455B + +#define REG_FW_REV_CTRL_1_H_ADDR 0x4C00455C + +#define REG_FW_REV_CTRL_2_L_ADDR 0x4C00455D +#define BF_FW_REV_CTRL_2_INFO 0x4C00455D, 0x00001800 + +#define REG_FW_REV_CTRL_2_M_ADDR 0x4C00455E + +#define REG_FW_REV_CTRL_2_H_ADDR 0x4C00455F + +#define REG_FW_REV_CTRL_3_L_ADDR 0x4C004560 +#define BF_FW_REV_CTRL_3_INFO 0x4C004560, 0x00001800 + +#define REG_FW_REV_CTRL_3_M_ADDR 0x4C004561 + +#define REG_FW_REV_CTRL_3_H_ADDR 0x4C004562 + +#define REG_FW_REV_CTRL_4_L_ADDR 0x4C004563 +#define BF_FW_REV_CTRL_4_INFO 0x4C004563, 0x00001800 + +#define REG_FW_REV_CTRL_4_M_ADDR 0x4C004564 + +#define REG_FW_REV_CTRL_4_H_ADDR 0x4C004565 + +#define REG_FW_REV_CTRL_5_L_ADDR 0x4C004566 +#define BF_FW_REV_CTRL_5_INFO 0x4C004566, 0x00001800 + +#define REG_FW_REV_CTRL_5_M_ADDR 0x4C004567 + +#define REG_FW_REV_CTRL_5_H_ADDR 0x4C004568 + +#define REG_FW_REV_CTRL_6_L_ADDR 0x4C004569 +#define BF_FW_REV_CTRL_6_INFO 0x4C004569, 0x00001800 + +#define REG_FW_REV_CTRL_6_M_ADDR 0x4C00456A + +#define REG_FW_REV_CTRL_6_H_ADDR 0x4C00456B + +#define REG_FW_REV_CTRL_7_L_ADDR 0x4C00456C +#define BF_FW_REV_CTRL_7_INFO 0x4C00456C, 0x00001800 + +#define REG_FW_REV_CTRL_7_M_ADDR 0x4C00456D + +#define REG_FW_REV_CTRL_7_H_ADDR 0x4C00456E + +#define REG_FW_REV_CTRL_8_L_ADDR 0x4C00456F +#define BF_FW_REV_CTRL_8_INFO 0x4C00456F, 0x00001800 + +#define REG_FW_REV_CTRL_8_M_ADDR 0x4C004570 + +#define REG_FW_REV_CTRL_8_H_ADDR 0x4C004571 + +#define REG_FW_REV_CTRL_9_L_ADDR 0x4C004572 +#define BF_FW_REV_CTRL_9_INFO 0x4C004572, 0x00001800 + +#define REG_FW_REV_CTRL_9_M_ADDR 0x4C004573 + +#define REG_FW_REV_CTRL_9_H_ADDR 0x4C004574 + +#endif /* __ADI_APOLLO_BF_RSA_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_rtclk_gen.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_rtclk_gen.h new file mode 100644 index 00000000000000..d33cbc928be817 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_rtclk_gen.h @@ -0,0 +1,120 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:19 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_RTCLK_GEN_H__ +#define __ADI_APOLLO_BF_RTCLK_GEN_H__ + +/*============= D E F I N E S ==============*/ +#define REG_DUAL_CLK_MODE_ADDR 0x4C001010 +#define BF_SINGLE_DUAL_CLK_SEL_INFO 0x4C001010, 0x00000100 + +#define REG_RTCLKGEN_RX_ADDR 0x4C001011 +#define BF_RTCLKGEN_MODE_RX_A_INFO 0x4C001011, 0x00000300 +#define BF_RTCLKGEN_MODE_RX_B_INFO 0x4C001011, 0x00000304 + +#define REG_RTCLKGEN_TX_ADDR 0x4C001012 +#define BF_RTCLKGEN_MODE_TX_A_INFO 0x4C001012, 0x00000300 +#define BF_RTCLKGEN_MODE_TX_B_INFO 0x4C001012, 0x00000304 + +#define REG_RTCLKGEN_PD_ADDR 0x4C001013 +#define BF_RTCLKGEN_PD_INFO 0x4C001013, 0x00000400 + +#define REG_DIGRTCLK_OFFINSYNC_ADDR 0x4C001014 +#define BF_GATEOFFCLK_INSYNC_INFO 0x4C001014, 0x00000400 + +#define REG_SDS_REFCLK_DIV_RATIO_ADDR 0x4C001015 +#define BF_SERDES_PLL_REFCLK_DIV_INFO 0x4C001015, 0x00000500 +#define BF_SERDES_PLL_REFCLK_DIV_UPDT_INFO 0x4C001015, 0x00000107 + +#define REG_UP_RTCLK_DIV_RATIO_ADDR 0x4C001017 +#define BF_UP_RTCLK_DIV_RTCLK_GEN_INFO 0x4C001017, 0x00000400 +#define BF_UP_RTCLK_DIV_UPDT_RTCLK_GEN_INFO 0x4C001017, 0x00000107 + +#define REG_CLK_PD_DEBUG_ADDR 0x4C001018 +#define BF_UP_RTCLK_EN_INFO 0x4C001018, 0x00000100 +#define BF_SYNCEN_UP_CLKGEN_INFO 0x4C001018, 0x00000101 +#define BF_UP_RTCLK_CFG_SEL_INFO 0x4C001018, 0x00000103 +#define BF_SERDES_PLL_REFCLK_EN_INFO 0x4C001018, 0x00000104 + +#define REG_FORCE_ATSPD_CLK_EN_ADDR 0x4C001019 +#define BF_FORCE_ATSPD_CLK_EN_INFO 0x4C001019, 0x00000100 + +#define REG_CLK_SEL_CTRL_ADDR 0x4C00101A +#define BF_FREERUN_CLK_SEL_INFO 0x4C00101A, 0x00000200 +#define BF_UP_RTCLK_SEL_INFO 0x4C00101A, 0x00000202 +#define BF_ATSPD_CLK_AB_SEL_INFO 0x4C00101A, 0x00000104 + +#define REG_ATSPD_CLK_CTRL_ADDR 0x4C00101B +#define BF_ATSPD_CLK_C_DIV_INFO 0x4C00101B, 0x00000400 +#define BF_ATSPD_CLK_AB_DIV_INFO 0x4C00101B, 0x00000404 + +#define REG_DIVP_PH_MAP_RX_ADDR 0x4C00101C +#define BF_DIVGMODE2_DIV2_PHMAP_INFO 0x4C00101C, 0x00000100 +#define BF_DIVGMODE3_DIV2_PHMAP_INFO 0x4C00101C, 0x00000101 +#define BF_DIVGMODE2_DIV4_PHMAP_INFO 0x4C00101C, 0x00000204 + +#define REG_SYNC_MASK_RTCLK_ADDR 0x4C001020 +#define BF_SYNC_MASK_RTCLK_INFO 0x4C001020, 0x00000800 + +#define REG_SYNC_MASK_ADCFIFO_ADDR 0x4C001021 +#define BF_SYNC_MASK_ADCFIFO_INFO 0x4C001021, 0x00000400 + +#define REG_SYNC_MASK_DACFIFO_ADDR 0x4C001022 +#define BF_SYNC_MASK_DACFIFO_INFO 0x4C001022, 0x00000800 + +#define REG_SYNC_MASK_RXTX_ADDR 0x4C001023 +#define BF_SYNC_MASK_RXTX_INFO 0x4C001023, 0x00000400 + +#define REG_SYNC_MASK_RXTXLINK_ADDR 0x4C001024 +#define BF_SYNC_MASK_RXTXLINK_INFO 0x4C001024, 0x00000800 + +#define REG_SYNC_MASK_LPBKFIFO_ADDR 0x4C001025 +#define BF_SYNC_MASK_LPBKFIFO_INFO 0x4C001025, 0x00000200 + +#define REG_XBTI_RESET_ADDR 0x4C00102F +#define BF_XBTI_CLK_EN_INFO 0x4C00102F, 0x00000100 +#define BF_XBTI_RESET_INFO 0x4C00102F, 0x00000104 + +#define REG_XBTI_CLK_CTRL_ADDR 0x4C001030 +#define BF_XBTI_CLK_DIV_UPDT_INFO 0x4C001030, 0x00000100 +#define BF_XBTI_CLK_DIV_INFO 0x4C001030, 0x00000204 + +#define REG_XBTI_CTRL0_ADDR 0x4C001031 +#define BF_XBTI_CTRL_INFO 0x4C001031, 0x00002000 + +#define REG_XBTI_CTRL1_ADDR 0x4C001032 + +#define REG_XBTI_CTRL2_ADDR 0x4C001033 + +#define REG_XBTI_CTRL3_ADDR 0x4C001034 + +#define REG_XBTI_STATE0_ADDR 0x4C001035 +#define BF_XBTI_STATUS_INFO 0x4C001035, 0x00004000 + +#define REG_XBTI_STATE1_ADDR 0x4C001036 + +#define REG_XBTI_STATE2_ADDR 0x4C001037 + +#define REG_XBTI_STATE3_ADDR 0x4C001038 + +#define REG_XBTI_STATE4_ADDR 0x4C001039 + +#define REG_XBTI_STATE5_ADDR 0x4C00103A + +#define REG_XBTI_STATE6_ADDR 0x4C00103B + +#define REG_XBTI_STATE7_ADDR 0x4C00103C + +#endif /* __ADI_APOLLO_BF_RTCLK_GEN_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_rx_bmem.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_rx_bmem.h new file mode 100644 index 00000000000000..d37c9c82c35687 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_rx_bmem.h @@ -0,0 +1,184 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:22 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_RX_BMEM_H__ +#define __ADI_APOLLO_BF_RX_BMEM_H__ + +/*============= D E F I N E S ==============*/ +#define RX_BMEM0_REG_RX_SLICE_0_RX_DIGITAL0 0x60204000 +#define RX_BMEM1_REG0_RX_SLICE_0_RX_DIGITAL0 0x60371000 +#define RX_BMEM1_REG1_RX_SLICE_0_RX_DIGITAL0 0x60372000 +#define RX_BMEM2_REG0_RX_SLICE_0_RX_DIGITAL0 0x603A8000 +#define RX_BMEM2_REG1_RX_SLICE_0_RX_DIGITAL0 0x603A9000 +#define RX_BMEM0_REG_RX_SLICE_1_RX_DIGITAL0 0x60404000 +#define RX_BMEM1_REG0_RX_SLICE_1_RX_DIGITAL0 0x60571000 +#define RX_BMEM1_REG1_RX_SLICE_1_RX_DIGITAL0 0x60572000 +#define RX_BMEM2_REG0_RX_SLICE_1_RX_DIGITAL0 0x605A8000 +#define RX_BMEM2_REG1_RX_SLICE_1_RX_DIGITAL0 0x605A9000 +#define RX_BMEM0_REG_RX_SLICE_0_RX_DIGITAL1 0x60A04000 +#define RX_BMEM1_REG0_RX_SLICE_0_RX_DIGITAL1 0x60B71000 +#define RX_BMEM1_REG1_RX_SLICE_0_RX_DIGITAL1 0x60B72000 +#define RX_BMEM2_REG0_RX_SLICE_0_RX_DIGITAL1 0x60BA8000 +#define RX_BMEM2_REG1_RX_SLICE_0_RX_DIGITAL1 0x60BA9000 +#define RX_BMEM0_REG_RX_SLICE_1_RX_DIGITAL1 0x60C04000 +#define RX_BMEM1_REG0_RX_SLICE_1_RX_DIGITAL1 0x60D71000 +#define RX_BMEM1_REG1_RX_SLICE_1_RX_DIGITAL1 0x60D72000 +#define RX_BMEM2_REG0_RX_SLICE_1_RX_DIGITAL1 0x60DA8000 +#define RX_BMEM2_REG1_RX_SLICE_1_RX_DIGITAL1 0x60DA9000 + +#define REG_BMEM_CONTROL_1_ADDR(inst) ((inst) + 0x00000000) +#define BF_BMEM_EN_INFO(inst) ((inst) + 0x00000000), 0x00000100 +#define BF_BMEM_START_INFO(inst) ((inst) + 0x00000000), 0x00000101 +#define BF_BMEM_MODE_INFO(inst) ((inst) + 0x00000000), 0x00000202 +#define BF_BMEM_RESET_INFO(inst) ((inst) + 0x00000000), 0x00000104 +#define BF_BMEM_SLEEP_INFO(inst) ((inst) + 0x00000000), 0x00000105 +#define BF_BMEM_SHUT_DOWN_INFO(inst) ((inst) + 0x00000000), 0x00000106 +#define BF_FAST_NSLOW_MODE_INFO(inst) ((inst) + 0x00000000), 0x00000107 + +#define REG_BMEM_CONTROL_2_ADDR(inst) ((inst) + 0x00000001) +#define BF_TRIG_MODE_INFO(inst) ((inst) + 0x00000001), 0x00000100 +#define BF_TRIG_MODE_SCLR_EN_INFO(inst) ((inst) + 0x00000001), 0x00000101 +#define BF_PARITY_CHECK_EN_INFO(inst) ((inst) + 0x00000001), 0x00000102 +#define BF_SAMPLE_SIZE_INFO(inst) ((inst) + 0x00000001), 0x00000103 +#define BF_RAMCLK_PH_DIS_INFO(inst) ((inst) + 0x00000001), 0x00000104 +#define BF_BMEM_8T8R_CAP_MASK_INFO(inst) ((inst) + 0x00000001), 0x00000205 +#define BF_HOP_DLY_SEL_MODE_INFO(inst) ((inst) + 0x00000001), 0x00000107 + +#define REG_SAMPLE_DELAY_0_ADDR(inst) ((inst) + 0x00000002) +#define BF_SAMPLE_DLY_INFO(inst) ((inst) + 0x00000002), 0x00001000 + +#define REG_SAMPLE_DELAY_1_ADDR(inst) ((inst) + 0x00000003) + +#define REG_HOP_DELAY0_0_ADDR(inst) ((inst) + 0x00000004) +#define BF_HOP_DELAY0_INFO(inst) ((inst) + 0x00000004), 0x00001000 + +#define REG_HOP_DELAY0_1_ADDR(inst) ((inst) + 0x00000005) + +#define REG_HOP_DELAY1_0_ADDR(inst) ((inst) + 0x00000006) +#define BF_HOP_DELAY1_INFO(inst) ((inst) + 0x00000006), 0x00001000 + +#define REG_HOP_DELAY1_1_ADDR(inst) ((inst) + 0x00000007) + +#define REG_HOP_DELAY2_0_ADDR(inst) ((inst) + 0x00000008) +#define BF_HOP_DELAY2_INFO(inst) ((inst) + 0x00000008), 0x00001000 + +#define REG_HOP_DELAY2_1_ADDR(inst) ((inst) + 0x00000009) + +#define REG_HOP_DELAY3_0_ADDR(inst) ((inst) + 0x0000000A) +#define BF_HOP_DELAY3_INFO(inst) ((inst) + 0x0000000A), 0x00001000 + +#define REG_HOP_DELAY3_1_ADDR(inst) ((inst) + 0x0000000B) + +#define REG_ST_ADDR_CPT_0_ADDR(inst) ((inst) + 0x0000000C) +#define BF_ST_ADDR_CPT_INFO(inst) ((inst) + 0x0000000C), 0x00000F00 + +#define REG_ST_ADDR_CPT_1_ADDR(inst) ((inst) + 0x0000000D) + +#define REG_END_ADDR_CPT_0_ADDR(inst) ((inst) + 0x0000000E) +#define BF_END_ADDR_CPT_INFO(inst) ((inst) + 0x0000000E), 0x00000F00 + +#define REG_END_ADDR_CPT_1_ADDR(inst) ((inst) + 0x0000000F) + +#define REG_ST_ADDR_AWG_0_ADDR(inst) ((inst) + 0x00000010) +#define BF_ST_ADDR_AWG_INFO(inst) ((inst) + 0x00000010), 0x00000F00 + +#define REG_ST_ADDR_AWG_1_ADDR(inst) ((inst) + 0x00000011) + +#define REG_END_ADDR_AWG_0_ADDR(inst) ((inst) + 0x00000012) +#define BF_END_ADDR_AWG_INFO(inst) ((inst) + 0x00000012), 0x00000F00 + +#define REG_END_ADDR_AWG_1_ADDR(inst) ((inst) + 0x00000013) + +#define REG_ST_CPTR_ON_SMPL_VAL_ADDR(inst) ((inst) + 0x00000014) +#define BF_ST_CPTR_ON_SMPL_VAL_INFO(inst) ((inst) + 0x00000014), 0x00000800 + +#define REG_SMPL_VAL_FOR_CPTR0_0_ADDR(inst) ((inst) + 0x00000015) +#define BF_SMPL_VAL_FOR_CPTR0_INFO(inst) ((inst) + 0x00000015), 0x00002000 + +#define REG_SMPL_VAL_FOR_CPTR0_1_ADDR(inst) ((inst) + 0x00000016) + +#define REG_SMPL_VAL_FOR_CPTR0_2_ADDR(inst) ((inst) + 0x00000017) + +#define REG_SMPL_VAL_FOR_CPTR0_3_ADDR(inst) ((inst) + 0x00000018) + +#define REG_SMPL_VAL_FOR_CPTR1_0_ADDR(inst) ((inst) + 0x00000019) +#define BF_SMPL_VAL_FOR_CPTR1_INFO(inst) ((inst) + 0x00000019), 0x00002000 + +#define REG_SMPL_VAL_FOR_CPTR1_1_ADDR(inst) ((inst) + 0x0000001A) + +#define REG_SMPL_VAL_FOR_CPTR1_2_ADDR(inst) ((inst) + 0x0000001B) + +#define REG_SMPL_VAL_FOR_CPTR1_3_ADDR(inst) ((inst) + 0x0000001C) + +#define REG_SMPL_VAL_FOR_CPTR2_0_ADDR(inst) ((inst) + 0x0000001D) +#define BF_SMPL_VAL_FOR_CPTR2_INFO(inst) ((inst) + 0x0000001D), 0x00002000 + +#define REG_SMPL_VAL_FOR_CPTR2_1_ADDR(inst) ((inst) + 0x0000001E) + +#define REG_SMPL_VAL_FOR_CPTR2_2_ADDR(inst) ((inst) + 0x0000001F) + +#define REG_SMPL_VAL_FOR_CPTR2_3_ADDR(inst) ((inst) + 0x00000020) + +#define REG_SMPL_VAL_FOR_CPTR3_0_ADDR(inst) ((inst) + 0x00000021) +#define BF_SMPL_VAL_FOR_CPTR3_INFO(inst) ((inst) + 0x00000021), 0x00002000 + +#define REG_SMPL_VAL_FOR_CPTR3_1_ADDR(inst) ((inst) + 0x00000022) + +#define REG_SMPL_VAL_FOR_CPTR3_2_ADDR(inst) ((inst) + 0x00000023) + +#define REG_SMPL_VAL_FOR_CPTR3_3_ADDR(inst) ((inst) + 0x00000024) + +#define REG_SMPL_VAL_FOR_CPTR4_0_ADDR(inst) ((inst) + 0x00000025) +#define BF_SMPL_VAL_FOR_CPTR4_INFO(inst) ((inst) + 0x00000025), 0x00002000 + +#define REG_SMPL_VAL_FOR_CPTR4_1_ADDR(inst) ((inst) + 0x00000026) + +#define REG_SMPL_VAL_FOR_CPTR4_2_ADDR(inst) ((inst) + 0x00000027) + +#define REG_SMPL_VAL_FOR_CPTR4_3_ADDR(inst) ((inst) + 0x00000028) + +#define REG_SMPL_VAL_FOR_CPTR5_0_ADDR(inst) ((inst) + 0x00000029) +#define BF_SMPL_VAL_FOR_CPTR5_INFO(inst) ((inst) + 0x00000029), 0x00002000 + +#define REG_SMPL_VAL_FOR_CPTR5_1_ADDR(inst) ((inst) + 0x0000002A) + +#define REG_SMPL_VAL_FOR_CPTR5_2_ADDR(inst) ((inst) + 0x0000002B) + +#define REG_SMPL_VAL_FOR_CPTR5_3_ADDR(inst) ((inst) + 0x0000002C) + +#define REG_SMPL_VAL_FOR_CPTR6_0_ADDR(inst) ((inst) + 0x0000002D) +#define BF_SMPL_VAL_FOR_CPTR6_INFO(inst) ((inst) + 0x0000002D), 0x00002000 + +#define REG_SMPL_VAL_FOR_CPTR6_1_ADDR(inst) ((inst) + 0x0000002E) + +#define REG_SMPL_VAL_FOR_CPTR6_2_ADDR(inst) ((inst) + 0x0000002F) + +#define REG_SMPL_VAL_FOR_CPTR6_3_ADDR(inst) ((inst) + 0x00000030) + +#define REG_SMPL_VAL_FOR_CPTR7_0_ADDR(inst) ((inst) + 0x00000031) +#define BF_SMPL_VAL_FOR_CPTR7_INFO(inst) ((inst) + 0x00000031), 0x00002000 + +#define REG_SMPL_VAL_FOR_CPTR7_1_ADDR(inst) ((inst) + 0x00000032) + +#define REG_SMPL_VAL_FOR_CPTR7_2_ADDR(inst) ((inst) + 0x00000033) + +#define REG_SMPL_VAL_FOR_CPTR7_3_ADDR(inst) ((inst) + 0x00000034) + +#define REG_BMEM_STATUS_ADDR(inst) ((inst) + 0x00000035) +#define BF_CAPTURE_TRIG_PHASE_INFO(inst) ((inst) + 0x00000035), 0x00000600 +#define BF_FULL_IRQ_INFO(inst) ((inst) + 0x00000035), 0x00000106 +#define BF_PARITY_ERR_INFO(inst) ((inst) + 0x00000035), 0x00000107 + +#endif /* __ADI_APOLLO_BF_RX_BMEM_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_rx_cddc.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_rx_cddc.h new file mode 100644 index 00000000000000..8695698ab61414 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_rx_cddc.h @@ -0,0 +1,135 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:22 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_RX_CDDC_H__ +#define __ADI_APOLLO_BF_RX_CDDC_H__ + +/*============= D E F I N E S ==============*/ +#define RX_CDDC_RX_SLICE_0_RX_DIGITAL0 0x60363000 +#define RX_CDDC_RX_SLICE_1_RX_DIGITAL0 0x60563000 +#define RX_CDDC_RX_SLICE_0_RX_DIGITAL1 0x60B63000 +#define RX_CDDC_RX_SLICE_1_RX_DIGITAL1 0x60D63000 + +#define REG_COARSE_DEC_CTRL_ADDR(inst) ((inst) + 0x00000000) +#define BF_COARSE_DDC_DEC_SEL_INFO(inst) ((inst) + 0x00000000), 0x00000400 +#define BF_FINE_BYPASS_INFO(inst) ((inst) + 0x00000000), 0x00000106 +#define BF_LINK_NUM_RX_CDDC_INFO(inst) ((inst) + 0x00000000), 0x00000107 + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_BASE_OFFSET_ADDR(inst) ((inst) + 0x00000001) +#define BF_DDC_BASE_OFFSET_RX_CDDC_INFO(inst) ((inst) + 0x00000001), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_CLK_OFFSET_WR_EN_ADDR(inst) ((inst) + 0x00000002) +#define BF_CLK_OFFSET_WR_EN_RX_CDDC_INFO(inst) ((inst) + 0x00000002), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#define REG_COARSE_FILT_DEL_CTRL_ADDR(inst) ((inst) + 0x00000003) +#define BF_HB1_DEL_RX_CDDC_INFO(inst) ((inst) + 0x00000003), 0x00000100 +#define BF_HB2_DEL_RX_CDDC_INFO(inst) ((inst) + 0x00000003), 0x00000101 +#define BF_TB1_DEL_INFO(inst) ((inst) + 0x00000003), 0x00000202 + +#define REG_COARSE_CLK_DEBUG_ADDR(inst) ((inst) + 0x00000004) +#define BF_CDDC_CLK_EN_INFO(inst) ((inst) + 0x00000004), 0x00000700 + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_I_HB1_OFFSET_PH0_ADDR(inst) ((inst) + 0x00000005) +#define BF_COARSE_I_HB1_OFFSET_PH0_INFO(inst) ((inst) + 0x00000005), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_I_HB1_OFFSET_PH1_ADDR(inst) ((inst) + 0x00000006) +#define BF_COARSE_I_HB1_OFFSET_PH1_INFO(inst) ((inst) + 0x00000006), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_Q_HB1_OFFSET_PH0_ADDR(inst) ((inst) + 0x00000007) +#define BF_COARSE_Q_HB1_OFFSET_PH0_INFO(inst) ((inst) + 0x00000007), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_Q_HB1_OFFSET_PH1_ADDR(inst) ((inst) + 0x00000008) +#define BF_COARSE_Q_HB1_OFFSET_PH1_INFO(inst) ((inst) + 0x00000008), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_I_HB2_OFFSET_PH0_ADDR(inst) ((inst) + 0x00000009) +#define BF_COARSE_I_HB2_OFFSET_PH0_INFO(inst) ((inst) + 0x00000009), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_I_HB2_OFFSET_PH1_ADDR(inst) ((inst) + 0x0000000A) +#define BF_COARSE_I_HB2_OFFSET_PH1_INFO(inst) ((inst) + 0x0000000A), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_Q_HB2_OFFSET_PH0_ADDR(inst) ((inst) + 0x0000000B) +#define BF_COARSE_Q_HB2_OFFSET_PH0_INFO(inst) ((inst) + 0x0000000B), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_Q_HB2_OFFSET_PH1_ADDR(inst) ((inst) + 0x0000000C) +#define BF_COARSE_Q_HB2_OFFSET_PH1_INFO(inst) ((inst) + 0x0000000C), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_I_TB1_OFFSET_PH0_ADDR(inst) ((inst) + 0x0000000D) +#define BF_COARSE_I_TB1_OFFSET_PH0_INFO(inst) ((inst) + 0x0000000D), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_I_TB1_OFFSET_PH1_ADDR(inst) ((inst) + 0x0000000E) +#define BF_COARSE_I_TB1_OFFSET_PH1_INFO(inst) ((inst) + 0x0000000E), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_Q_TB1_OFFSET_PH0_ADDR(inst) ((inst) + 0x0000000F) +#define BF_COARSE_Q_TB1_OFFSET_PH0_INFO(inst) ((inst) + 0x0000000F), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_Q_TB1_OFFSET_PH1_ADDR(inst) ((inst) + 0x00000010) +#define BF_COARSE_Q_TB1_OFFSET_PH1_INFO(inst) ((inst) + 0x00000010), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_I_FILT_IN_OFFSET_ADDR(inst) ((inst) + 0x00000013) +#define BF_COARSE_I_FILT_IN_OFFSET_INFO(inst) ((inst) + 0x00000013), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_Q_FILT_IN_OFFSET_ADDR(inst) ((inst) + 0x00000014) +#define BF_COARSE_Q_FILT_IN_OFFSET_INFO(inst) ((inst) + 0x00000014), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_I_FILT_OUT_OFFSET_ADDR(inst) ((inst) + 0x00000015) +#define BF_COARSE_I_FILT_OUT_OFFSET_INFO(inst) ((inst) + 0x00000015), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_Q_FILT_OUT_OFFSET_ADDR(inst) ((inst) + 0x00000016) +#define BF_COARSE_Q_FILT_OUT_OFFSET_INFO(inst) ((inst) + 0x00000016), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_FILTER_GAIN_EN_RX_CDDC_ADDR(inst) ((inst) + 0x00000017) +#define BF_HB1_GAIN_EN_RX_CDDC_INFO(inst) ((inst) + 0x00000017), 0x00000100 +#define BF_TB1_GAIN_EN_INFO(inst) ((inst) + 0x00000017), 0x00000101 + +#define REG_GPIO_EN_RX_CDDC_ADDR(inst) ((inst) + 0x00000018) +#define BF_GPIO_DEC_SEL_RX_CDDC_INFO(inst) ((inst) + 0x00000018), 0x00000100 + +#endif /* __ADI_APOLLO_BF_RX_CDDC_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_rx_datin.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_rx_datin.h new file mode 100644 index 00000000000000..6f72bf81672bb9 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_rx_datin.h @@ -0,0 +1,70 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:22 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_RX_DATIN_H__ +#define __ADI_APOLLO_BF_RX_DATIN_H__ + +/*============= D E F I N E S ==============*/ +#define RX_DATIN_RX_SLICE_0_RX_DIGITAL0 0x60209000 +#define RX_DATIN_RX_SLICE_1_RX_DIGITAL0 0x60409000 +#define RX_DATIN_RX_SLICE_0_RX_DIGITAL1 0x60A09000 +#define RX_DATIN_RX_SLICE_1_RX_DIGITAL1 0x60C09000 + +#define REG_DFIFO_CTRL_RX_DATIN_ADDR(inst) ((inst) + 0x00000000) +#define BF_DFIFO_EN_RX_DATIN_INFO(inst) ((inst) + 0x00000000), 0x00000100 +#define BF_RXFIFO_WRCLK_INVERT_INFO(inst) ((inst) + 0x00000000), 0x00000101 +#define BF_DAC_FIFO_FORCEON_CTRL_RX_DATIN_INFO(inst) ((inst) + 0x00000000), 0x00000404 + +#define REG_LAT_CTRL_RX_DATIN_ADDR(inst) ((inst) + 0x00000001) +#define BF_LAT_PGM_MODE_RX_DATIN_INFO(inst) ((inst) + 0x00000001), 0x00000200 +#define BF_WR_RD_OFFSET_RX_DATIN_INFO(inst) ((inst) + 0x00000001), 0x00000302 + +#define REG_LAT_SPI_CTRL_RX_DATIN_ADDR(inst) ((inst) + 0x00000002) +#define BF_LAT_RD_SPI_RX_DATIN_INFO(inst) ((inst) + 0x00000002), 0x00000300 +#define BF_LAT_WR_SPI_RX_DATIN_INFO(inst) ((inst) + 0x00000002), 0x00000403 + +#ifdef USE_PRIVATE_BF +#define REG_SYNCCNT_STRB_RX_DATIN_ADDR(inst) ((inst) + 0x00000003) +#define BF_RDSYNCCNT_WRSTRB_RX_DATIN_INFO(inst) ((inst) + 0x00000003), 0x00000300 +#define BF_WRSYNCCNT_RDSTRB_RX_DATIN_INFO(inst) ((inst) + 0x00000003), 0x00000403 +#endif /* USE_PRIVATE_BF */ + +#define REG_LAT_REAL_RX_DATIN_ADDR(inst) ((inst) + 0x00000004) +#define BF_LAT_RD_REAL_RX_DATIN_INFO(inst) ((inst) + 0x00000004), 0x00000300 +#define BF_LAT_WR_REAL_RX_DATIN_INFO(inst) ((inst) + 0x00000004), 0x00000403 + +#define REG_SYNC_STATE_RX_DATIN_ADDR(inst) ((inst) + 0x00000005) +#define BF_RDSYNC_STATE_RX_DATIN_INFO(inst) ((inst) + 0x00000005), 0x00000200 +#define BF_WRSYNC_STATE_RX_DATIN_INFO(inst) ((inst) + 0x00000005), 0x00000202 + +#define REG_DEBUG_CTRL_ADDR(inst) ((inst) + 0x00000006) +#define BF_DBG_EN_RX_DATIN_INFO(inst) ((inst) + 0x00000006), 0x00000100 +#define BF_DBG_OUT_INFO(inst) ((inst) + 0x00000006), 0x00000101 +#define BF_DBG_OUT_DEC2_INFO(inst) ((inst) + 0x00000006), 0x00000102 + +#define REG_ADC_MUX_SEL_ADDR(inst) ((inst) + 0x00000007) +#define BF_ADC_0_MUX_SEL_INFO(inst) ((inst) + 0x00000007), 0x00000200 +#define BF_ADC_1_MUX_SEL_INFO(inst) ((inst) + 0x00000007), 0x00000202 + +#define REG_ADC_WR_SETUP_CTRL_ADDR(inst) ((inst) + 0x00000008) +#define BF_ADC_ANA_BRIDGE_WR_SETUP_CYCLES_INFO(inst) ((inst) + 0x00000008), 0x00000600 + +#define REG_ADC_WR_HOLD_CTRL_ADDR(inst) ((inst) + 0x00000009) +#define BF_ADC_ANA_BRIDGE_WR_HOLD_CYCLES_INFO(inst) ((inst) + 0x00000009), 0x00000600 + +#define REG_ADC_RD_CTRL_ADDR(inst) ((inst) + 0x0000000A) +#define BF_ADC_ANA_BRIDGE_RD_CYCLES_INFO(inst) ((inst) + 0x0000000A), 0x00000600 + +#endif /* __ADI_APOLLO_BF_RX_DATIN_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_rx_eng.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_rx_eng.h new file mode 100644 index 00000000000000..0ce3968c01b499 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_rx_eng.h @@ -0,0 +1,65 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:22 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_RX_ENG_H__ +#define __ADI_APOLLO_BF_RX_ENG_H__ + +/*============= D E F I N E S ==============*/ +#define RX_ENG_RX_DIGITAL0 0x60010000 +#define RX_ENG_RX_DIGITAL1 0x60810000 + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_DDC_BIST_OP_ADDR(inst, n) ((inst) + 0x00000000 + 1 * (n)) +#define BF_COARSE_DDC_BIST_EN_INFO(inst, n) ((inst) + 0x00000000 + 1 * (n)), 0x00000100 +#define BF_COARSE_DDC_BIST_INIT_INFO(inst, n) ((inst) + 0x00000000 + 1 * (n)), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_DDC_BIST_CRC_LO_ADDR(inst, n) ((inst) + 0x00000004 + 1 * (n)) +#define BF_COARSE_DDC_BIST_CRC_LO_INFO(inst, n) ((inst) + 0x00000004 + 1 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_DDC_BIST_CRC_HI_ADDR(inst, n) ((inst) + 0x00000008 + 1 * (n)) +#define BF_COARSE_DDC_BIST_CRC_HI_INFO(inst, n) ((inst) + 0x00000008 + 1 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_DDC_BIST_EN_STATUS_ADDR(inst, n) ((inst) + 0x0000000C + 1 * (n)) +#define BF_COARSE_DDC_BIST_EN_STATUS_INFO(inst, n) ((inst) + 0x0000000C + 1 * (n)), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FINE_DDC_BIST_OP_ADDR(inst, n) ((inst) + 0x00000010 + 1 * (n)) +#define BF_FINE_DDC_BIST_EN_INFO(inst, n) ((inst) + 0x00000010 + 1 * (n)), 0x00000103 +#define BF_FINE_DDC_BIST_INIT_INFO(inst, n) ((inst) + 0x00000010 + 1 * (n)), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FINE_DDC_BIST_CRC_LO_ADDR(inst, n) ((inst) + 0x00000018 + 1 * (n)) +#define BF_FINE_DDC_BIST_CRC_LO_INFO(inst, n) ((inst) + 0x00000018 + 1 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FINE_DDC_BIST_CRC_HI_ADDR(inst, n) ((inst) + 0x00000020 + 1 * (n)) +#define BF_FINE_DDC_BIST_CRC_HI_INFO(inst, n) ((inst) + 0x00000020 + 1 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FINE_DDC_BIST_EN_STATUS_ADDR(inst, n) ((inst) + 0x00000028 + 1 * (n)) +#define BF_FINE_DDC_BIST_EN_STATUS_INFO(inst, n) ((inst) + 0x00000028 + 1 * (n)), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#endif /* __ADI_APOLLO_BF_RX_ENG_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_rx_fine_ddc.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_rx_fine_ddc.h new file mode 100644 index 00000000000000..17a4620e005296 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_rx_fine_ddc.h @@ -0,0 +1,140 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:22 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_RX_FINE_DDC_H__ +#define __ADI_APOLLO_BF_RX_FINE_DDC_H__ + +/*============= D E F I N E S ==============*/ +#define RX_FINE_DDC0_RX_SLICE_0_RX_DIGITAL0 0x603A0000 +#define RX_FINE_DDC1_RX_SLICE_0_RX_DIGITAL0 0x603A1000 +#define RX_FINE_DDC0_RX_SLICE_1_RX_DIGITAL0 0x605A0000 +#define RX_FINE_DDC1_RX_SLICE_1_RX_DIGITAL0 0x605A1000 +#define RX_FINE_DDC0_RX_SLICE_0_RX_DIGITAL1 0x60BA0000 +#define RX_FINE_DDC1_RX_SLICE_0_RX_DIGITAL1 0x60BA1000 +#define RX_FINE_DDC0_RX_SLICE_1_RX_DIGITAL1 0x60DA0000 +#define RX_FINE_DDC1_RX_SLICE_1_RX_DIGITAL1 0x60DA1000 + +#define REG_FINE_DEC_CTRL_ADDR(inst) ((inst) + 0x00000000) +#define BF_FINE_DDC_DEC_SEL_INFO(inst) ((inst) + 0x00000000), 0x00000400 +#define BF_LINK_NUM_RX_FINE_DDC_INFO(inst) ((inst) + 0x00000000), 0x00000106 + +#define REG_FINE_FILT_DEL_CTRL_ADDR(inst) ((inst) + 0x00000001) +#define BF_HB1_DEL_RX_FINE_DDC_INFO(inst) ((inst) + 0x00000001), 0x00000100 +#define BF_HB2_DEL_RX_FINE_DDC_INFO(inst) ((inst) + 0x00000001), 0x00000101 +#define BF_HB3_DEL_INFO(inst) ((inst) + 0x00000001), 0x00000102 +#define BF_HB4_DEL_INFO(inst) ((inst) + 0x00000001), 0x00000103 +#define BF_HB5_DEL_INFO(inst) ((inst) + 0x00000001), 0x00000104 +#define BF_HB6_DEL_INFO(inst) ((inst) + 0x00000001), 0x00000105 + +#ifdef USE_PRIVATE_BF +#define REG_FINE_BASE_OFFSET_RX_FINE_DDC_ADDR(inst) ((inst) + 0x00000002) +#define BF_DDC_BASE_OFFSET_RX_FINE_DDC_INFO(inst) ((inst) + 0x00000002), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FINE_CLK_OFFSET_WR_EN_ADDR(inst) ((inst) + 0x00000003) +#define BF_CLK_OFFSET_WR_EN_RX_FINE_DDC_INFO(inst) ((inst) + 0x00000003), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#define REG_FINE_CLK_DEBUG_ADDR(inst) ((inst) + 0x00000004) +#define BF_FDDC_CLK_EN_INFO(inst) ((inst) + 0x00000004), 0x00000800 + +#ifdef USE_PRIVATE_BF +#define REG_FINE_I_FILT_OUT_OFFSET_ADDR(inst) ((inst) + 0x00000007) +#define BF_FINE_I_FILT_OUT_OFFSET_INFO(inst) ((inst) + 0x00000007), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FINE_Q_FILT_OUT_OFFSET_ADDR(inst) ((inst) + 0x00000008) +#define BF_FINE_Q_FILT_OUT_OFFSET_INFO(inst) ((inst) + 0x00000008), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FINE_I_FILT_IN_OFFSET_ADDR(inst) ((inst) + 0x00000009) +#define BF_FINE_I_FILT_IN_OFFSET_INFO(inst) ((inst) + 0x00000009), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FINE_Q_FILT_IN_OFFSET_ADDR(inst) ((inst) + 0x0000000A) +#define BF_FINE_Q_FILT_IN_OFFSET_INFO(inst) ((inst) + 0x0000000A), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FINE_I_HB1_OFFSET_ADDR(inst) ((inst) + 0x0000000B) +#define BF_FINE_I_HB1_OFFSET_INFO(inst) ((inst) + 0x0000000B), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FINE_Q_HB1_OFFSET_ADDR(inst) ((inst) + 0x0000000C) +#define BF_FINE_Q_HB1_OFFSET_INFO(inst) ((inst) + 0x0000000C), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FINE_I_HB2_OFFSET_ADDR(inst) ((inst) + 0x0000000D) +#define BF_FINE_I_HB2_OFFSET_INFO(inst) ((inst) + 0x0000000D), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FINE_Q_HB2_OFFSET_ADDR(inst) ((inst) + 0x0000000E) +#define BF_FINE_Q_HB2_OFFSET_INFO(inst) ((inst) + 0x0000000E), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FINE_I_HB3_OFFSET_ADDR(inst) ((inst) + 0x0000000F) +#define BF_FINE_I_HB3_OFFSET_INFO(inst) ((inst) + 0x0000000F), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FINE_Q_HB3_OFFSET_ADDR(inst) ((inst) + 0x00000010) +#define BF_FINE_Q_HB3_OFFSET_INFO(inst) ((inst) + 0x00000010), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FINE_I_HB4_OFFSET_ADDR(inst) ((inst) + 0x00000011) +#define BF_FINE_I_HB4_OFFSET_INFO(inst) ((inst) + 0x00000011), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FINE_Q_HB4_OFFSET_ADDR(inst) ((inst) + 0x00000012) +#define BF_FINE_Q_HB4_OFFSET_INFO(inst) ((inst) + 0x00000012), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FINE_I_HB5_OFFSET_ADDR(inst) ((inst) + 0x00000013) +#define BF_FINE_I_HB5_OFFSET_INFO(inst) ((inst) + 0x00000013), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FINE_Q_HB5_OFFSET_ADDR(inst) ((inst) + 0x00000014) +#define BF_FINE_Q_HB5_OFFSET_INFO(inst) ((inst) + 0x00000014), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FINE_I_HB6_OFFSET_ADDR(inst) ((inst) + 0x00000015) +#define BF_FINE_I_HB6_OFFSET_INFO(inst) ((inst) + 0x00000015), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FINE_Q_HB6_OFFSET_ADDR(inst) ((inst) + 0x00000016) +#define BF_FINE_Q_HB6_OFFSET_INFO(inst) ((inst) + 0x00000016), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_FILTER_GAIN_EN_RX_FINE_DDC_ADDR(inst) ((inst) + 0x00000017) +#define BF_HB1_GAIN_EN_RX_FINE_DDC_INFO(inst) ((inst) + 0x00000017), 0x00000100 + +#define REG_GPIO_EN_RX_FINE_DDC_ADDR(inst) ((inst) + 0x00000018) +#define BF_GPIO_DEC_SEL_RX_FINE_DDC_INFO(inst) ((inst) + 0x00000018), 0x00000100 + +#endif /* __ADI_APOLLO_BF_RX_FINE_DDC_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_rx_loopback.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_rx_loopback.h new file mode 100644 index 00000000000000..44ec507a735c9f --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_rx_loopback.h @@ -0,0 +1,47 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:22 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_RX_LOOPBACK_H__ +#define __ADI_APOLLO_BF_RX_LOOPBACK_H__ + +/*============= D E F I N E S ==============*/ +#define RX_LOOPBACK_RX_SLICE_0_RX_DIGITAL0 0x60200000 +#define RX_LOOPBACK_RX_SLICE_1_RX_DIGITAL0 0x60400000 +#define RX_LOOPBACK_RX_SLICE_0_RX_DIGITAL1 0x60A00000 +#define RX_LOOPBACK_RX_SLICE_1_RX_DIGITAL1 0x60C00000 + +#define REG_WRPTR_SYNC_RSTVAL_ADDR(inst) ((inst) + 0x00000000) +#define BF_WRPTR_SYNC_RSTVAL_INFO(inst) ((inst) + 0x00000000), 0x00000200 + +#ifdef USE_PRIVATE_BF +#define REG_ADC_DATA_OVR_STATUS_ADDR(inst) ((inst) + 0x00000001) +#define BF_ADC_DATA_OVR_STATUS_INFO(inst) ((inst) + 0x00000001), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ADC_DATA_OVR_CLR_ADDR(inst) ((inst) + 0x00000002) +#define BF_ADC_DATA_OVR_CLEAR_INFO(inst) ((inst) + 0x00000002), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#define REG_LPBK_WR_EN_ADDR(inst) ((inst) + 0x00000003) +#define BF_LPBK_WR_EN_INFO(inst) ((inst) + 0x00000003), 0x00000100 + +#define REG_DBG_DATA_OFF_EN_ADDR(inst) ((inst) + 0x00000004) +#define BF_DBG_DATA_OFF_EN_INFO(inst) ((inst) + 0x00000004), 0x00000100 + +#define REG_LB0_BMEM_PATH_SEL_ADDR(inst) ((inst) + 0x00000005) +#define BF_LB0_BMEM_PATH_SEL_INFO(inst) ((inst) + 0x00000005), 0x00000100 + +#endif /* __ADI_APOLLO_BF_RX_LOOPBACK_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_rx_misc.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_rx_misc.h new file mode 100644 index 00000000000000..c211cd1009b3d2 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_rx_misc.h @@ -0,0 +1,242 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:21 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_RX_MISC_H__ +#define __ADI_APOLLO_BF_RX_MISC_H__ + +/*============= D E F I N E S ==============*/ +#define RX_MISC_RX_DIGITAL0 0x60000000 +#define RX_MISC_RX_DIGITAL1 0x60800000 + +#define REG_LOW_SAMP_RX_MISC_ADDR(inst) ((inst) + 0x0000001A) +#define BF_LOW_SAMP_RX_MISC_INFO(inst) ((inst) + 0x0000001A), 0x00000100 + +#define REG_DATAPATH_CTRL_ADDR(inst) ((inst) + 0x0000001B) +#ifdef USE_PRIVATE_BF +#define BF_RXEN_CDDC_INFO(inst) ((inst) + 0x0000001B), 0x00000200 +#endif /* USE_PRIVATE_BF */ +#ifdef USE_PRIVATE_BF +#define BF_RXEN_FDDC_INFO(inst) ((inst) + 0x0000001B), 0x00000402 +#endif /* USE_PRIVATE_BF */ +#define BF_DATAPATH_CLK_EN_INFO(inst) ((inst) + 0x0000001B), 0x00000206 + +#define REG_CB_SEL0_ADDR(inst) ((inst) + 0x0000001C) +#define BF_CB_SEL_F0_INFO(inst) ((inst) + 0x0000001C), 0x00000300 +#define BF_CB_SEL_F1_INFO(inst) ((inst) + 0x0000001C), 0x00000303 + +#define REG_CB_SEL1_ADDR(inst) ((inst) + 0x0000001D) +#define BF_CB_SEL_F2_INFO(inst) ((inst) + 0x0000001D), 0x00000300 +#define BF_CB_SEL_F3_INFO(inst) ((inst) + 0x0000001D), 0x00000303 + +#ifdef USE_PRIVATE_BF +#define REG_HSDIN_DBG_CNT_EN_ADDR(inst) ((inst) + 0x0000033D) +#define BF_HSDIN_DBG_CNT_EN_INFO(inst) ((inst) + 0x0000033D), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_LINX_DBG_CNT_EN_RX_MISC_ADDR(inst) ((inst) + 0x0000033E) +#define BF_LINX_DBG_CNT_EN_INFO(inst) ((inst) + 0x0000033E), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_PFILT_DBG_CNT_EN_ADDR(inst) ((inst) + 0x0000033F) +#define BF_PFILT_DBG_CNT_EN_INFO(inst) ((inst) + 0x0000033F), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CDDC0_DBG_CNT_EN_ADDR(inst) ((inst) + 0x00000340) +#define BF_CDDC0_DBG_CNT_EN_INFO(inst) ((inst) + 0x00000340), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CDDC1_DBG_CNT_EN_ADDR(inst) ((inst) + 0x00000341) +#define BF_CDDC1_DBG_CNT_EN_INFO(inst) ((inst) + 0x00000341), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FDDC_DBG_CNT_EN_ADDR(inst) ((inst) + 0x00000342) +#define BF_FDDC_DBG_CNT_EN_INFO(inst) ((inst) + 0x00000342), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CFIR_DBG_CNT_EN_ADDR(inst) ((inst) + 0x00000343) +#define BF_CFIR_DBG_CNT_EN_INFO(inst) ((inst) + 0x00000343), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JTX_DBG_CNT_EN_ADDR(inst) ((inst) + 0x00000344) +#define BF_JTX_DBG_CNT_EN_INFO(inst) ((inst) + 0x00000344), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_HSDIN_DBG_MUX_SEL_ADDR(inst) ((inst) + 0x00000345) +#define BF_HSDIN_DBG_MUX_SEL_INFO(inst) ((inst) + 0x00000345), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_LINX_DBG_MUX_SEL_ADDR(inst) ((inst) + 0x00000346) +#define BF_LINX_DBG_MUX_SEL_INFO(inst) ((inst) + 0x00000346), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_PFILT_DBG_MUX_SEL_ADDR(inst) ((inst) + 0x00000347) +#define BF_PFILT_DBG_MUX_SEL_INFO(inst) ((inst) + 0x00000347), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CDDC0_DBG_MUX_SEL_ADDR(inst) ((inst) + 0x00000348) +#define BF_CDDC0_DBG_MUX_SEL_INFO(inst) ((inst) + 0x00000348), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CDDC1_DBG_MUX_SEL_ADDR(inst) ((inst) + 0x00000349) +#define BF_CDDC1_DBG_MUX_SEL_INFO(inst) ((inst) + 0x00000349), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FDDC_DBG_MUX_SEL_ADDR(inst) ((inst) + 0x0000034A) +#define BF_FDDC_DBG_MUX_SEL_INFO(inst) ((inst) + 0x0000034A), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CFIR_DBG_MUX_SEL_ADDR(inst) ((inst) + 0x0000034B) +#define BF_CFIR_DBG_MUX_SEL_INFO(inst) ((inst) + 0x0000034B), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JTX_DBG_MUX_SEL_ADDR(inst) ((inst) + 0x0000034C) +#define BF_JTX_DBG_MUX_SEL_INFO(inst) ((inst) + 0x0000034C), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ADC_BIST_CTRL_STATUS_ADDR(inst, n) ((inst) + 0x00000400 + 2 * (n)) +#define BF_ADC_BIST_ENABLE_INFO(inst, n) ((inst) + 0x00000400 + 2 * (n)), 0x00000100 +#define BF_ADC_BIST_START_INFO(inst, n) ((inst) + 0x00000400 + 2 * (n)), 0x00000101 +#define BF_ADC_BIST_MODE_SEL_INFO(inst, n) ((inst) + 0x00000400 + 2 * (n)), 0x00000102 +#define BF_ADC_BIST_INVERT_INFO(inst, n) ((inst) + 0x00000400 + 2 * (n)), 0x00000103 +#define BF_ADC_BIST_PASS_INFO(inst, n) ((inst) + 0x00000400 + 2 * (n)), 0x00000104 +#define BF_ADC_BIST_FAIL_INFO(inst, n) ((inst) + 0x00000400 + 2 * (n)), 0x00000105 +#define BF_ADC_BIST_DONE_INFO(inst, n) ((inst) + 0x00000400 + 2 * (n)), 0x00000106 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ADC_BIST_ERRORS_ADDR(inst, n) ((inst) + 0x00000401 + 2 * (n)) +#define BF_ADC_BIST_ERRORS_INFO(inst, n) ((inst) + 0x00000401 + 2 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_JESD_LBK_MODE_ADDR(inst) ((inst) + 0x00000441) +#define BF_JESD_LBK_MODE_RD_PTR_INFO(inst) ((inst) + 0x00000441), 0x00000200 +#define BF_JESD_LBK_MODE_PTR_OVERRIDE_RX_MISC_INFO(inst) ((inst) + 0x00000441), 0x00000102 +#endif /* USE_PRIVATE_BF */ + +#define REG_FDUC_NS_ADDR(inst) ((inst) + 0x00000442) +#define BF_DUC_NS_INFO(inst) ((inst) + 0x00000442), 0x00000500 +#define BF_DUC_NS_OVERRIDE_INFO(inst) ((inst) + 0x00000442), 0x00000105 + +#define REG_LB1_CFG_RX_MISC_ADDR(inst) ((inst) + 0x00000443) +#define BF_LB1_WR_EN_INFO(inst) ((inst) + 0x00000443), 0x00000100 +#define BF_LB1_WRPTR_SYNC_RSTVAL_INFO(inst) ((inst) + 0x00000443), 0x00000201 + +#define REG_LB2_CFG_ADDR(inst) ((inst) + 0x00000444) +#define BF_LB2_WR_EN_INFO(inst) ((inst) + 0x00000444), 0x00000100 +#define BF_LB2_WRPTR_SYNC_RSTVAL_INFO(inst) ((inst) + 0x00000444), 0x00000201 + +#define REG_ZCD_SEL_RX_ADDR(inst) ((inst) + 0x00000445) +#define BF_ZCD_SEL_TAP1_RX_MISC_INFO(inst) ((inst) + 0x00000445), 0x00000400 +#define BF_ZCD_SEL_TAP2_RX_MISC_INFO(inst) ((inst) + 0x00000445), 0x00000404 + +#ifdef USE_PRIVATE_BF +#define REG_LB1_OVR_STATUS_ADDR(inst) ((inst) + 0x00000446) +#define BF_LB1_I_OVR_STATUS_INFO(inst) ((inst) + 0x00000446), 0x00000400 +#define BF_LB1_Q_OVR_STATUS_INFO(inst) ((inst) + 0x00000446), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_LB1_OVR_CLEAR_ADDR(inst) ((inst) + 0x00000447) +#define BF_LB1_I_OVR_CLEAR_INFO(inst) ((inst) + 0x00000447), 0x00000400 +#define BF_LB1_Q_OVR_CLEAR_INFO(inst) ((inst) + 0x00000447), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_LB2_I_OVR_STATUS_ADDR(inst) ((inst) + 0x00000448) +#define BF_LB2_I_OVR_STATUS_INFO(inst) ((inst) + 0x00000448), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_LB2_I_OVR_CLEAR_ADDR(inst) ((inst) + 0x00000449) +#define BF_LB2_I_OVR_CLEAR_INFO(inst) ((inst) + 0x00000449), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_LB2_Q_OVR_STATUS_ADDR(inst) ((inst) + 0x0000044A) +#define BF_LB2_Q_OVR_STATUS_INFO(inst) ((inst) + 0x0000044A), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_LB2_Q_OVR_CLEAR_ADDR(inst) ((inst) + 0x0000044B) +#define BF_LB2_Q_OVR_CLEAR_INFO(inst) ((inst) + 0x0000044B), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_MODE_8T8R_RX_MISC_ADDR(inst) ((inst) + 0x0000044C) +#define BF_MODE_8T8R_RX_MISC_INFO(inst) ((inst) + 0x0000044C), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_LB1_BIST_CFG_RX_MISC_ADDR(inst) ((inst) + 0x0000044D) +#define BF_LB1_BIST_EN_INFO(inst) ((inst) + 0x0000044D), 0x00000100 +#define BF_LB1_BIST_FLUSH_LEN_INFO(inst) ((inst) + 0x0000044D), 0x00000201 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_LB1_BIST_LEN_LSB_ADDR(inst) ((inst) + 0x0000044E) +#define BF_LB1_BIST_LENGTH_INFO(inst) ((inst) + 0x0000044E), 0x00001300 +#endif /* USE_PRIVATE_BF */ + +#define REG_LB1_BIST_LEN_MID_ADDR(inst) ((inst) + 0x0000044F) + +#define REG_LB1_BIST_LEN_MSB_ADDR(inst) ((inst) + 0x00000450) + +#ifdef USE_PRIVATE_BF +#define REG_LB1_BIST_STATUS_ADDR(inst) ((inst) + 0x00000451) +#define BF_LB1_BIST_SIGN_CLR_INFO(inst) ((inst) + 0x00000451), 0x00000100 +#define BF_LB1_BIST_SIGN_RUN_INFO(inst) ((inst) + 0x00000451), 0x00000101 +#define BF_LB1_BIST_DONE_INFO(inst) ((inst) + 0x00000451), 0x00000102 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_LB2_BIST_CFG_RX_MISC_ADDR(inst) ((inst) + 0x00000452) +#define BF_LB2_BIST_EN_INFO(inst) ((inst) + 0x00000452), 0x00000100 +#define BF_LB2_BIST_FLUSH_LEN_INFO(inst) ((inst) + 0x00000452), 0x00000201 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_LB2_BIST_LEN_LSB_ADDR(inst) ((inst) + 0x00000453) +#define BF_LB2_BIST_LENGTH_INFO(inst) ((inst) + 0x00000453), 0x00001300 +#endif /* USE_PRIVATE_BF */ + +#define REG_LB2_BIST_LEN_MID_ADDR(inst) ((inst) + 0x00000454) + +#define REG_LB2_BIST_LEN_MSB_ADDR(inst) ((inst) + 0x00000455) + +#ifdef USE_PRIVATE_BF +#define REG_LB2_BIST_STATUS_ADDR(inst) ((inst) + 0x00000456) +#define BF_LB2_BIST_SIGN_CLR_INFO(inst) ((inst) + 0x00000456), 0x00000100 +#define BF_LB2_BIST_SIGN_RUN_INFO(inst) ((inst) + 0x00000456), 0x00000101 +#define BF_LB2_BIST_DONE_INFO(inst) ((inst) + 0x00000456), 0x00000102 +#endif /* USE_PRIVATE_BF */ + +#endif /* __ADI_APOLLO_BF_RX_MISC_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_rx_smon.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_rx_smon.h new file mode 100644 index 00000000000000..ee443a57906d76 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_rx_smon.h @@ -0,0 +1,73 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:22 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_RX_SMON_H__ +#define __ADI_APOLLO_BF_RX_SMON_H__ + +/*============= D E F I N E S ==============*/ +#define RX_SMON0_RX_SLICE_0_RX_DIGITAL0 0x60207000 +#define RX_SMON1_RX_SLICE_0_RX_DIGITAL0 0x60208000 +#define RX_SMON0_RX_SLICE_1_RX_DIGITAL0 0x60407000 +#define RX_SMON1_RX_SLICE_1_RX_DIGITAL0 0x60408000 +#define RX_SMON0_RX_SLICE_0_RX_DIGITAL1 0x60A07000 +#define RX_SMON1_RX_SLICE_0_RX_DIGITAL1 0x60A08000 +#define RX_SMON0_RX_SLICE_1_RX_DIGITAL1 0x60C07000 +#define RX_SMON1_RX_SLICE_1_RX_DIGITAL1 0x60C08000 + +#define REG_SMON_CLK_EN_ADDR(inst) ((inst) + 0x00000000) +#define BF_SMON_SFRAMER_MODE_EN_INFO(inst) ((inst) + 0x00000000), 0x00000201 + +#define REG_SMON_STATUS_FCNT_ADDR(inst) ((inst) + 0x00000001) +#define BF_SMON_STATUS_FCNT_INFO(inst) ((inst) + 0x00000001), 0x00000800 + +#define REG_SMON_PERIOD0_ADDR(inst) ((inst) + 0x00000002) +#define BF_SMON_PERIOD_INFO(inst) ((inst) + 0x00000002), 0x00002000 + +#define REG_SMON_PERIOD1_ADDR(inst) ((inst) + 0x00000003) + +#define REG_SMON_PERIOD2_ADDR(inst) ((inst) + 0x00000004) + +#define REG_SMON_PERIOD3_ADDR(inst) ((inst) + 0x00000005) + +#define REG_SMON_STATUS_CTRL_ADDR(inst) ((inst) + 0x00000006) +#define BF_SMON_STATUS_UPDATE_INFO(inst) ((inst) + 0x00000006), 0x00000100 +#define BF_SMON_STATUS_RDSEL_INFO(inst) ((inst) + 0x00000006), 0x00000301 +#define BF_SMON_PEAK_EN_INFO(inst) ((inst) + 0x00000006), 0x00000104 +#define BF_SMON_JLINK_SEL_INFO(inst) ((inst) + 0x00000006), 0x00000105 +#define BF_SMON_GPIO_EN_INFO(inst) ((inst) + 0x00000006), 0x00000106 + +#define REG_SMON_FRAMER_ADDR(inst) ((inst) + 0x00000007) +#define BF_SMON_SFRAMER_EN_INFO(inst) ((inst) + 0x00000007), 0x00000100 +#define BF_SMON_SFRAMER_MODE_INFO(inst) ((inst) + 0x00000007), 0x00000101 +#define BF_SMON_SFRAMER_INSEL_INFO(inst) ((inst) + 0x00000007), 0x00000602 + +#define REG_SMON_SYNC_CTRL_ADDR(inst) ((inst) + 0x00000008) +#define BF_SMON_SYNC_EN_INFO(inst) ((inst) + 0x00000008), 0x00000100 +#define BF_SMON_SYNC_NEXT_INFO(inst) ((inst) + 0x00000008), 0x00000101 + +#define REG_SMON_STATUS_ADDR(inst, n) ((inst) + 0x00000009 + 1 * (n)) +#define BF_SMON_STATUS_INFO(inst, n) ((inst) + 0x00000009 + 1 * (n)), 0x00000800 + +#define REG_SMON_THRESH_LOW0_ADDR(inst) ((inst) + 0x0000000C) +#define BF_SMON_THRESH_LOW_INFO(inst) ((inst) + 0x0000000C), 0x00000B00 + +#define REG_SMON_THRESH_LOW1_ADDR(inst) ((inst) + 0x0000000D) + +#define REG_SMON_THRESH_HIGH0_ADDR(inst) ((inst) + 0x0000000E) +#define BF_SMON_THRESH_HIGH_INFO(inst) ((inst) + 0x0000000E), 0x00000B00 + +#define REG_SMON_THRESH_HIGH1_ADDR(inst) ((inst) + 0x0000000F) + +#endif /* __ADI_APOLLO_BF_RX_SMON_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_rx_spectrum_sniffer.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_rx_spectrum_sniffer.h new file mode 100644 index 00000000000000..81211879e2f8db --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_rx_spectrum_sniffer.h @@ -0,0 +1,90 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:22 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_RX_SPECTRUM_SNIFFER_H__ +#define __ADI_APOLLO_BF_RX_SPECTRUM_SNIFFER_H__ + +/*============= D E F I N E S ==============*/ +#define RX_SPECTRUM_SNIFFER_RX_SLICE_0_RX_DIGITAL0 0x60205000 +#define RX_SPECTRUM_SNIFFER_RX_SLICE_1_RX_DIGITAL0 0x60405000 +#define RX_SPECTRUM_SNIFFER_RX_SLICE_0_RX_DIGITAL1 0x60A05000 +#define RX_SPECTRUM_SNIFFER_RX_SLICE_1_RX_DIGITAL1 0x60C05000 + +#define REG_SPECTRUM_SNIFFER_CONTROL_1_ADDR(inst) ((inst) + 0x00000000) +#define BF_SPECTRUM_SNIFFER_EN_INFO(inst) ((inst) + 0x00000000), 0x00000100 +#define BF_FFT_ENABLE_INFO(inst) ((inst) + 0x00000000), 0x00000101 +#define BF_SORT_EN_INFO(inst) ((inst) + 0x00000000), 0x00000102 +#define BF_MAGNITUDE_IQ_N_INFO(inst) ((inst) + 0x00000000), 0x00000103 +#define BF_FORCE_SORT_STORE_INFO(inst) ((inst) + 0x00000000), 0x00000104 +#define BF_FFT_HOLD_INFO(inst) ((inst) + 0x00000000), 0x00000105 +#define BF_FFT_ENABLE_SEL_INFO(inst) ((inst) + 0x00000000), 0x00000106 +#define BF_FFT_HOLD_SEL_INFO(inst) ((inst) + 0x00000000), 0x00000107 + +#define REG_SPECTRUM_SNIFFER_CONTROL_2_ADDR(inst) ((inst) + 0x00000001) +#define BF_REAL_MODE_INFO(inst) ((inst) + 0x00000001), 0x00000100 +#define BF_CONTINUOUS_MODE_INFO(inst) ((inst) + 0x00000001), 0x00000101 +#define BF_BOTTOM_FFT_ENABLE_INFO(inst) ((inst) + 0x00000001), 0x00000102 +#define BF_WINDOW_ENABLE_INFO(inst) ((inst) + 0x00000001), 0x00000103 +#define BF_LOW_POWER_INFO(inst) ((inst) + 0x00000001), 0x00000104 +#define BF_DITHER_ENABLE_INFO(inst) ((inst) + 0x00000001), 0x00000105 + +#define REG_ALPHA_FACTOR_ADDR(inst) ((inst) + 0x00000002) +#define BF_ALPHA_FACTOR_INFO(inst) ((inst) + 0x00000002), 0x00000400 + +#define REG_MAX_THRESHOLD_ADDR(inst) ((inst) + 0x00000003) +#define BF_MAX_THRESHOLD_INFO(inst) ((inst) + 0x00000003), 0x00000800 + +#define REG_MIN_THRESHOLD_ADDR(inst) ((inst) + 0x00000004) +#define BF_MIN_THRESHOLD_INFO(inst) ((inst) + 0x00000004), 0x00000800 + +#define REG_SPECTRUM_SNIFFER_STATUS_ADDR(inst) ((inst) + 0x00000005) +#define BF_FFT_DONE_INFO(inst) ((inst) + 0x00000005), 0x00000100 +#define BF_DBG_MAG_OVERFLOW_INFO(inst) ((inst) + 0x00000005), 0x00000101 + +#define REG_MAGNITUDE_I_0_ADDR(inst, n) ((inst) + 0x00000006 + 4 * (n)) +#define BF_MAGNITUDE_I_INFO(inst, n) ((inst) + 0x00000006 + 4 * (n)), 0x00000900 + +#define REG_MAGNITUDE_I_1_ADDR(inst, n) ((inst) + 0x00000007 + 4 * (n)) + +#define REG_BIN_NUMBER_Q_0_ADDR(inst, n) ((inst) + 0x00000008 + 4 * (n)) +#define BF_BIN_NUMBER_Q_INFO(inst, n) ((inst) + 0x00000008 + 4 * (n)), 0x00000900 + +#define REG_BIN_NUMBER_Q_1_ADDR(inst, n) ((inst) + 0x00000009 + 4 * (n)) + +#define REG_MAX_THRESHOLD_BIN_ADDR(inst, n) ((inst) + 0x00000806 + 1 * (n)) +#define BF_MAX_THRESHOLD_BIN_INFO(inst, n) ((inst) + 0x00000806 + 1 * (n)), 0x00000800 + +#define REG_MIN_THRESHOLD_BIN_ADDR(inst, n) ((inst) + 0x00000846 + 1 * (n)) +#define BF_MIN_THRESHOLD_BIN_INFO(inst, n) ((inst) + 0x00000846 + 1 * (n)), 0x00000800 + +#ifdef USE_PRIVATE_BF +#define REG_BIST_CTRL_ADDR(inst) ((inst) + 0x00000886) +#define BF_BIST_EN_RX_SPECTRUM_SNIFFER_INFO(inst) ((inst) + 0x00000886), 0x00000100 +#define BF_BIST_INIT_INFO(inst) ((inst) + 0x00000886), 0x00000101 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_BIST_CRC_LSB_ADDR(inst) ((inst) + 0x00000887) +#define BF_BIST_CRC_INFO(inst) ((inst) + 0x00000887), 0x00001000 +#endif /* USE_PRIVATE_BF */ + +#define REG_BIST_CRC_MSB_ADDR(inst) ((inst) + 0x00000888) + +#ifdef USE_PRIVATE_BF +#define REG_BIST_STATUS_ADDR(inst) ((inst) + 0x00000889) +#define BF_BIST_EN_STATUS_INFO(inst) ((inst) + 0x00000889), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#endif /* __ADI_APOLLO_BF_RX_SPECTRUM_SNIFFER_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_semaphore.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_semaphore.h new file mode 100644 index 00000000000000..3baa591cfdd20a --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_semaphore.h @@ -0,0 +1,120 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:17 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_SEMAPHORE_H__ +#define __ADI_APOLLO_BF_SEMAPHORE_H__ + +/*============= D E F I N E S ==============*/ +#define SEMAPHORE0 0x46500000 +#define SEMAPHORE1 0x46510000 +#define SEMAPHORE2 0x46520000 +#define SEMAPHORE3 0x46530000 +#define SEMAPHORE4 0x46540000 +#define SEMAPHORE5 0x46550000 +#define SEMAPHORE6 0x46560000 +#define SEMAPHORE7 0x46570000 +#define SEMAPHORE8 0x46580000 +#define SEMAPHORE9 0x46590000 +#define SEMAPHORE10 0x465A0000 +#define SEMAPHORE11 0x465B0000 +#define SEMAPHORE12 0x465C0000 +#define SEMAPHORE13 0x465D0000 +#define SEMAPHORE14 0x465E0000 +#define SEMAPHORE15 0x465F0000 +#define SEMAPHORE16 0x46600000 +#define SEMAPHORE17 0x46610000 +#define SEMAPHORE18 0x46620000 +#define SEMAPHORE19 0x46630000 +#define SEMAPHORE20 0x46640000 +#define SEMAPHORE21 0x46650000 +#define SEMAPHORE22 0x46660000 +#define SEMAPHORE23 0x46670000 +#define SEMAPHORE24 0x46680000 +#define SEMAPHORE25 0x46690000 +#define SEMAPHORE26 0x466A0000 +#define SEMAPHORE27 0x466B0000 +#define SEMAPHORE28 0x466C0000 +#define SEMAPHORE29 0x466D0000 +#define SEMAPHORE30 0x466E0000 +#define SEMAPHORE31 0x466F0000 +#define RX_SEMAPHORE0_RX_SLICE_0_RX_DIGITAL0 0x603BD000 +#define RX_SEMAPHORE1_RX_SLICE_0_RX_DIGITAL0 0x603BD100 +#define RX_SEMAPHORE2_RX_SLICE_0_RX_DIGITAL0 0x603BD200 +#define RX_SEMAPHORE3_RX_SLICE_0_RX_DIGITAL0 0x603BD300 +#define RX_SEMAPHORE4_RX_SLICE_0_RX_DIGITAL0 0x603BD400 +#define RX_SEMAPHORE5_RX_SLICE_0_RX_DIGITAL0 0x603BD500 +#define RX_SEMAPHORE6_RX_SLICE_0_RX_DIGITAL0 0x603BD600 +#define RX_SEMAPHORE7_RX_SLICE_0_RX_DIGITAL0 0x603BD700 +#define RX_SEMAPHORE0_RX_SLICE_1_RX_DIGITAL0 0x605BD000 +#define RX_SEMAPHORE1_RX_SLICE_1_RX_DIGITAL0 0x605BD100 +#define RX_SEMAPHORE2_RX_SLICE_1_RX_DIGITAL0 0x605BD200 +#define RX_SEMAPHORE3_RX_SLICE_1_RX_DIGITAL0 0x605BD300 +#define RX_SEMAPHORE4_RX_SLICE_1_RX_DIGITAL0 0x605BD400 +#define RX_SEMAPHORE5_RX_SLICE_1_RX_DIGITAL0 0x605BD500 +#define RX_SEMAPHORE6_RX_SLICE_1_RX_DIGITAL0 0x605BD600 +#define RX_SEMAPHORE7_RX_SLICE_1_RX_DIGITAL0 0x605BD700 +#define RX_SEMAPHORE0_RX_SLICE_0_RX_DIGITAL1 0x60BBD000 +#define RX_SEMAPHORE1_RX_SLICE_0_RX_DIGITAL1 0x60BBD100 +#define RX_SEMAPHORE2_RX_SLICE_0_RX_DIGITAL1 0x60BBD200 +#define RX_SEMAPHORE3_RX_SLICE_0_RX_DIGITAL1 0x60BBD300 +#define RX_SEMAPHORE4_RX_SLICE_0_RX_DIGITAL1 0x60BBD400 +#define RX_SEMAPHORE5_RX_SLICE_0_RX_DIGITAL1 0x60BBD500 +#define RX_SEMAPHORE6_RX_SLICE_0_RX_DIGITAL1 0x60BBD600 +#define RX_SEMAPHORE7_RX_SLICE_0_RX_DIGITAL1 0x60BBD700 +#define RX_SEMAPHORE0_RX_SLICE_1_RX_DIGITAL1 0x60DBD000 +#define RX_SEMAPHORE1_RX_SLICE_1_RX_DIGITAL1 0x60DBD100 +#define RX_SEMAPHORE2_RX_SLICE_1_RX_DIGITAL1 0x60DBD200 +#define RX_SEMAPHORE3_RX_SLICE_1_RX_DIGITAL1 0x60DBD300 +#define RX_SEMAPHORE4_RX_SLICE_1_RX_DIGITAL1 0x60DBD400 +#define RX_SEMAPHORE5_RX_SLICE_1_RX_DIGITAL1 0x60DBD500 +#define RX_SEMAPHORE6_RX_SLICE_1_RX_DIGITAL1 0x60DBD600 +#define RX_SEMAPHORE7_RX_SLICE_1_RX_DIGITAL1 0x60DBD700 +#define TX_SEMAPHORE0_TX_SLICE_0_TX_DIGITAL0 0x6133E000 +#define TX_SEMAPHORE1_TX_SLICE_0_TX_DIGITAL0 0x6133E100 +#define TX_SEMAPHORE2_TX_SLICE_0_TX_DIGITAL0 0x6133E200 +#define TX_SEMAPHORE3_TX_SLICE_0_TX_DIGITAL0 0x6133E300 +#define TX_SEMAPHORE4_TX_SLICE_0_TX_DIGITAL0 0x6133E400 +#define TX_SEMAPHORE5_TX_SLICE_0_TX_DIGITAL0 0x6133E500 +#define TX_SEMAPHORE6_TX_SLICE_0_TX_DIGITAL0 0x6133E600 +#define TX_SEMAPHORE7_TX_SLICE_0_TX_DIGITAL0 0x6133E700 +#define TX_SEMAPHORE0_TX_SLICE_1_TX_DIGITAL0 0x6153E000 +#define TX_SEMAPHORE1_TX_SLICE_1_TX_DIGITAL0 0x6153E100 +#define TX_SEMAPHORE2_TX_SLICE_1_TX_DIGITAL0 0x6153E200 +#define TX_SEMAPHORE3_TX_SLICE_1_TX_DIGITAL0 0x6153E300 +#define TX_SEMAPHORE4_TX_SLICE_1_TX_DIGITAL0 0x6153E400 +#define TX_SEMAPHORE5_TX_SLICE_1_TX_DIGITAL0 0x6153E500 +#define TX_SEMAPHORE6_TX_SLICE_1_TX_DIGITAL0 0x6153E600 +#define TX_SEMAPHORE7_TX_SLICE_1_TX_DIGITAL0 0x6153E700 +#define TX_SEMAPHORE0_TX_SLICE_0_TX_DIGITAL1 0x61B3E000 +#define TX_SEMAPHORE1_TX_SLICE_0_TX_DIGITAL1 0x61B3E100 +#define TX_SEMAPHORE2_TX_SLICE_0_TX_DIGITAL1 0x61B3E200 +#define TX_SEMAPHORE3_TX_SLICE_0_TX_DIGITAL1 0x61B3E300 +#define TX_SEMAPHORE4_TX_SLICE_0_TX_DIGITAL1 0x61B3E400 +#define TX_SEMAPHORE5_TX_SLICE_0_TX_DIGITAL1 0x61B3E500 +#define TX_SEMAPHORE6_TX_SLICE_0_TX_DIGITAL1 0x61B3E600 +#define TX_SEMAPHORE7_TX_SLICE_0_TX_DIGITAL1 0x61B3E700 +#define TX_SEMAPHORE0_TX_SLICE_1_TX_DIGITAL1 0x61D3E000 +#define TX_SEMAPHORE1_TX_SLICE_1_TX_DIGITAL1 0x61D3E100 +#define TX_SEMAPHORE2_TX_SLICE_1_TX_DIGITAL1 0x61D3E200 +#define TX_SEMAPHORE3_TX_SLICE_1_TX_DIGITAL1 0x61D3E300 +#define TX_SEMAPHORE4_TX_SLICE_1_TX_DIGITAL1 0x61D3E400 +#define TX_SEMAPHORE5_TX_SLICE_1_TX_DIGITAL1 0x61D3E500 +#define TX_SEMAPHORE6_TX_SLICE_1_TX_DIGITAL1 0x61D3E600 +#define TX_SEMAPHORE7_TX_SLICE_1_TX_DIGITAL1 0x61D3E700 + +#define REG_SEMAPHORE_ADDR(inst) ((inst) + 0x00000000) +#define BF_SEMAPHORE_INFO(inst) ((inst) + 0x00000000), 0x00002000 + +#endif /* __ADI_APOLLO_BF_SEMAPHORE_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_serdes_rxdig_12pack_core1p3.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_serdes_rxdig_12pack_core1p3.h new file mode 100644 index 00000000000000..849d8a57aa455d --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_serdes_rxdig_12pack_core1p3.h @@ -0,0 +1,156 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:26 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_SERDES_RXDIG_12PACK_CORE1P3_H__ +#define __ADI_APOLLO_BF_SERDES_RXDIG_12PACK_CORE1P3_H__ + +/*============= D E F I N E S ==============*/ +#define DESER_PHY_TOP_12PACK_SERDES_RX_JRX_TX_DIGITAL0 0x61638000 +#define DESER_PHY_TOP_12PACK_SERDES_RX_JRX_TX_DIGITAL1 0x61E38000 + +#define REG_RXDES_12PACK_PD0_ADDR(inst) ((inst) + 0x00000000) +#define BF_RXDES_PD_CH_INFO(inst) ((inst) + 0x00000000), 0x00000C00 + +#define REG_RXDES_12PACK_PD1_ADDR(inst) ((inst) + 0x00000001) +#define BF_RXDES_PD_CLK_RCVR_INFO(inst) ((inst) + 0x00000001), 0x00000104 +#define BF_RXDES_PD_BIASDIST_INFO(inst) ((inst) + 0x00000001), 0x00000105 + +#define REG_RXDES_12PACK_TEST_CLK_CTL_ADDR(inst) ((inst) + 0x00000002) +#define BF_RXDES_TEST_CLK_SEL_INFO(inst) ((inst) + 0x00000002), 0x00000400 +#define BF_RXDES_TEST_CLK_EN_INFO(inst) ((inst) + 0x00000002), 0x00000104 +#define BF_RXDES_EN_DESER_TESTV_OUT_INFO(inst) ((inst) + 0x00000002), 0x00000105 +#define BF_RXDES_TEST_MUX_BANK_SEL_INFO(inst) ((inst) + 0x00000002), 0x00000106 + +#define REG_RXDES_12PACK_BIAS_CTL0_ADDR(inst) ((inst) + 0x00000003) +#define BF_CTRL_IBIAS_TFR_INFO(inst) ((inst) + 0x00000003), 0x00000300 +#define BF_CTRL_IBIAS_FIX_INFO(inst) ((inst) + 0x00000003), 0x00000304 + +#define REG_RXDES_12PACK_BIAS_CTL1_ADDR(inst) ((inst) + 0x00000004) +#define BF_CTRL_IBIAS_PTAT_INFO(inst) ((inst) + 0x00000004), 0x00000300 + +#define REG_RXDES_12PACK_RATE_CTL_ADDR(inst) ((inst) + 0x00000005) +#define BF_RXDES_QHFRATE_INFO(inst) ((inst) + 0x00000005), 0x00000200 +#define BF_RXDES_PARDATAMODE_INFO(inst) ((inst) + 0x00000005), 0x00000202 +#define BF_RXDES_DIVRATE_INFO(inst) ((inst) + 0x00000005), 0x00000304 + +#define REG_RXDES_12PACK_ERRBITS_ADDR(inst) ((inst) + 0x00000006) +#define BF_RXDES_EN_ERRBITS_INFO(inst) ((inst) + 0x00000006), 0x00000100 + +#define REG_RXDES_12PACK_SPARE_CTL_ADDR(inst) ((inst) + 0x00000007) +#define BF_SPARE_CTL_SERDES_RXDIG_12PACK__CORE1P3_INFO(inst) ((inst) + 0x00000007), 0x00000800 + +#define REG_RXDES_12PACK_SPARE_STA_ADDR(inst) ((inst) + 0x00000008) +#define BF_SPARE_STA_INFO(inst) ((inst) + 0x00000008), 0x00000800 + +#define REG_RXDES_12PACK_VARDCO_CTL_ADDR(inst) ((inst) + 0x00000010) +#define BF_RXDES_VARDCO_DIVN_INFO(inst) ((inst) + 0x00000010), 0x00000300 +#define BF_RXDES_VARDCO_EN_INFO(inst) ((inst) + 0x00000010), 0x00000103 + +#define REG_RXDES_12PACK_UC_CTL0_ADDR(inst) ((inst) + 0x00000011) +#define BF_RXDES_UC_EN_INFO(inst) ((inst) + 0x00000011), 0x00000100 +#define BF_RXDES_UC_RUN_INFO(inst) ((inst) + 0x00000011), 0x00000101 +#define BF_RXDES_UC_STEP_INFO(inst) ((inst) + 0x00000011), 0x00000102 +#define BF_RXDES_UC_BREAKPOINT_EN_INFO(inst) ((inst) + 0x00000011), 0x00000103 +#define BF_RXDES_UC_MEM_OVERRIDE_INFO(inst) ((inst) + 0x00000011), 0x00000104 +#define BF_RXDES_UC_SPI_OVERRIDE_INFO(inst) ((inst) + 0x00000011), 0x00000105 + +#define REG_RXDES_12PACK_UC_CTL1_ADDR(inst) ((inst) + 0x00000012) +#define BF_RXDES_UC_STACK_START_ADDR_INFO(inst) ((inst) + 0x00000012), 0x00000C00 + +#define REG_RXDES_12PACK_UC_CTL2_ADDR(inst) ((inst) + 0x00000013) + +#define REG_RXDES_12PACK_UC_CTL3_ADDR(inst) ((inst) + 0x00000014) +#define BF_RXDES_UC_BREAKPOINT_ADDR_INFO(inst) ((inst) + 0x00000014), 0x00000C00 + +#define REG_RXDES_12PACK_UC_CTL4_ADDR(inst) ((inst) + 0x00000015) + +#define REG_RXDES_12PACK_UC_CTL5_ADDR(inst) ((inst) + 0x00000016) +#define BF_RXDES_UC_PC_PTR_INFO(inst) ((inst) + 0x00000016), 0x00000C00 + +#define REG_RXDES_12PACK_UC_CTL6_ADDR(inst) ((inst) + 0x00000017) + +#define REG_RXDES_12PACK_PHY_UC_CTL0_ADDR(inst) ((inst) + 0x00000020) +#define BF_RXDES_LMS_EN_INFO(inst) ((inst) + 0x00000020), 0x00000C00 + +#define REG_RXDES_12PACK_PHY_UC_CTL1_ADDR(inst) ((inst) + 0x00000021) + +#define REG_RXDES_12PACK_PHY_UC_CTL2_ADDR(inst) ((inst) + 0x00000022) +#define BF_RXDES_LMS_DONE_INFO(inst) ((inst) + 0x00000022), 0x00000C00 + +#define REG_RXDES_12PACK_PHY_UC_CTL3_ADDR(inst) ((inst) + 0x00000023) + +#define REG_RXDES_12PACK_PHY_UC_CTL4_ADDR(inst) ((inst) + 0x00000024) +#define BF_RXDES_LMS_FREEZE_INFO(inst) ((inst) + 0x00000024), 0x00000C00 + +#define REG_RXDES_12PACK_PHY_UC_CTL5_ADDR(inst) ((inst) + 0x00000025) + +#define REG_RXDES_12PACK_PHY_UC_CTL6_ADDR(inst) ((inst) + 0x00000026) +#define BF_RXDES_LMS_STEP_INFO(inst) ((inst) + 0x00000026), 0x00000C00 + +#define REG_RXDES_12PACK_PHY_UC_CTL7_ADDR(inst) ((inst) + 0x00000027) + +#define REG_RXDES_12PACK_PHY_INTERRUPT_CTL0_ADDR(inst) ((inst) + 0x00000028) +#define BF_RXDES_LANE_INTERRUPT_MASK_INFO(inst) ((inst) + 0x00000028), 0x00000C00 + +#define REG_RXDES_12PACK_PHY_INTERRUPT_CTL1_ADDR(inst) ((inst) + 0x00000029) + +#define REG_RXDES_12PACK_PHY_INTERRUPT_CTL2_ADDR(inst) ((inst) + 0x0000002A) +#define BF_RXDES_LANE_INTERRUPT_INVERT_INFO(inst) ((inst) + 0x0000002A), 0x00000C00 + +#define REG_RXDES_12PACK_PHY_INTERRUPT_CTL3_ADDR(inst) ((inst) + 0x0000002B) + +#define REG_RXDES_12PACK_PHY_INTERRUPT_CTL4_ADDR(inst) ((inst) + 0x0000002C) +#define BF_RXDES_GLOBAL_INTERRUPT_AND_OR_INFO(inst) ((inst) + 0x0000002C), 0x00000100 +#define BF_RXDES_GLOBAL_INTERRUPT_INVERT_INFO(inst) ((inst) + 0x0000002C), 0x00000101 +#define BF_RXDES_LOCAL_INTERRUPT_MASK_INFO(inst) ((inst) + 0x0000002C), 0x00000104 +#define BF_RXDES_LOCAL_INTERRUPT_INVERT_INFO(inst) ((inst) + 0x0000002C), 0x00000105 + +#define REG_RXDES_12PACK_PHY_USR_CTL0_ADDR(inst) ((inst) + 0x00000030) +#define BF_RXDES_USR_CTL0_INFO(inst) ((inst) + 0x00000030), 0x00000800 + +#define REG_RXDES_12PACK_PHY_USR_CTL1_ADDR(inst) ((inst) + 0x00000031) +#define BF_RXDES_USR_CTL1_INFO(inst) ((inst) + 0x00000031), 0x00000800 + +#define REG_RXDES_12PACK_PHY_USR_CTL2_ADDR(inst) ((inst) + 0x00000032) +#define BF_RXDES_USR_CTL2_INFO(inst) ((inst) + 0x00000032), 0x00000800 + +#define REG_RXDES_12PACK_PHY_USR_CTL3_ADDR(inst) ((inst) + 0x00000033) +#define BF_RXDES_USR_CTL3_INFO(inst) ((inst) + 0x00000033), 0x00000800 + +#define REG_RXDES_12PACK_PHY_USR_CTL4_ADDR(inst) ((inst) + 0x00000034) +#define BF_RXDES_USR_CTL4_INFO(inst) ((inst) + 0x00000034), 0x00000800 + +#define REG_RXDES_12PACK_PHY_USR_CTL5_ADDR(inst) ((inst) + 0x00000035) +#define BF_RXDES_USR_CTL5_INFO(inst) ((inst) + 0x00000035), 0x00000800 + +#define REG_RXDES_12PACK_PHY_USR_CTL6_ADDR(inst) ((inst) + 0x00000036) +#define BF_RXDES_USR_CTL6_INFO(inst) ((inst) + 0x00000036), 0x00000800 + +#define REG_RXDES_12PACK_PHY_USR_CTL7_ADDR(inst) ((inst) + 0x00000037) +#define BF_RXDES_USR_CTL7_INFO(inst) ((inst) + 0x00000037), 0x00000800 + +#define REG_RXDES_12PACK_PHY_USR_CTL8_ADDR(inst) ((inst) + 0x00000038) +#define BF_RXDES_USR_CTL8_INFO(inst) ((inst) + 0x00000038), 0x00000800 + +#define REG_RXDES_12PACK_PHY_USR_CTL9_ADDR(inst) ((inst) + 0x00000039) +#define BF_RXDES_USR_STA0_INFO(inst) ((inst) + 0x00000039), 0x00000800 + +#define REG_RXDES_12PACK_PHY_USR_CTL10_ADDR(inst) ((inst) + 0x0000003A) +#define BF_RXDES_USR_STA1_INFO(inst) ((inst) + 0x0000003A), 0x00000800 + +#define REG_RXDES_12PACK_REVID_ADDR(inst) ((inst) + 0x000000FF) +#define BF_RXDES_12PACK_REVID_INFO(inst) ((inst) + 0x000000FF), 0x00000800 + +#endif /* __ADI_APOLLO_BF_SERDES_RXDIG_12PACK_CORE1P3_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_serdes_rxdig_phy_core1p3.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_serdes_rxdig_phy_core1p3.h new file mode 100644 index 00000000000000..22c2fcbf54900d --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_serdes_rxdig_phy_core1p3.h @@ -0,0 +1,811 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:25 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_SERDES_RXDIG_PHY_CORE1P3_H__ +#define __ADI_APOLLO_BF_SERDES_RXDIG_PHY_CORE1P3_H__ + +/*============= D E F I N E S ==============*/ +#define DESER_PHY0_SERDES_RX_JRX_TX_DIGITAL0 0x61630000 +#define DESER_PHY1_SERDES_RX_JRX_TX_DIGITAL0 0x61630800 +#define DESER_PHY2_SERDES_RX_JRX_TX_DIGITAL0 0x61631000 +#define DESER_PHY3_SERDES_RX_JRX_TX_DIGITAL0 0x61631800 +#define DESER_PHY4_SERDES_RX_JRX_TX_DIGITAL0 0x61632000 +#define DESER_PHY5_SERDES_RX_JRX_TX_DIGITAL0 0x61632800 +#define DESER_PHY6_SERDES_RX_JRX_TX_DIGITAL0 0x61633000 +#define DESER_PHY7_SERDES_RX_JRX_TX_DIGITAL0 0x61633800 +#define DESER_PHY8_SERDES_RX_JRX_TX_DIGITAL0 0x61634000 +#define DESER_PHY9_SERDES_RX_JRX_TX_DIGITAL0 0x61634800 +#define DESER_PHY10_SERDES_RX_JRX_TX_DIGITAL0 0x61635000 +#define DESER_PHY11_SERDES_RX_JRX_TX_DIGITAL0 0x61635800 +#define DESER_PHY_ALL_SERDES_RX_JRX_TX_DIGITAL0 0x61636000 +#define DESER_PHY0_SERDES_RX_JRX_TX_DIGITAL1 0x61E30000 +#define DESER_PHY1_SERDES_RX_JRX_TX_DIGITAL1 0x61E30800 +#define DESER_PHY2_SERDES_RX_JRX_TX_DIGITAL1 0x61E31000 +#define DESER_PHY3_SERDES_RX_JRX_TX_DIGITAL1 0x61E31800 +#define DESER_PHY4_SERDES_RX_JRX_TX_DIGITAL1 0x61E32000 +#define DESER_PHY5_SERDES_RX_JRX_TX_DIGITAL1 0x61E32800 +#define DESER_PHY6_SERDES_RX_JRX_TX_DIGITAL1 0x61E33000 +#define DESER_PHY7_SERDES_RX_JRX_TX_DIGITAL1 0x61E33800 +#define DESER_PHY8_SERDES_RX_JRX_TX_DIGITAL1 0x61E34000 +#define DESER_PHY9_SERDES_RX_JRX_TX_DIGITAL1 0x61E34800 +#define DESER_PHY10_SERDES_RX_JRX_TX_DIGITAL1 0x61E35000 +#define DESER_PHY11_SERDES_RX_JRX_TX_DIGITAL1 0x61E35800 +#define DESER_PHY_ALL_SERDES_RX_JRX_TX_DIGITAL1 0x61E36000 + +#define REG_SPI_INTFCONFA_ADDR(inst) ((inst) + 0x00000000) +#define BF_SOFTRESET_INFO(inst) ((inst) + 0x00000000), 0x00000100 + +#define REG_CAL_EN_ADDR(inst) ((inst) + 0x00000001) +#define BF_RFPLL_LOCKED_INFO(inst) ((inst) + 0x00000001), 0x00000100 +#define BF_AUTOCAL_EN_INFO(inst) ((inst) + 0x00000001), 0x00000104 + +#define REG_PD_REG_0_ADDR(inst) ((inst) + 0x00000002) +#define BF_CK_DIS_CKGATES_INFO(inst) ((inst) + 0x00000002), 0x00000100 +#define BF_RXDES_PD_MBIAS_INFO(inst) ((inst) + 0x00000002), 0x00000101 +#define BF_PD_CDR_D_DES_RC_INFO(inst) ((inst) + 0x00000002), 0x00000102 +#define BF_PD_CTLE_DES_RC_INFO(inst) ((inst) + 0x00000002), 0x00000103 +#define BF_CK_PD_PI_INFO(inst) ((inst) + 0x00000002), 0x00000104 +#define BF_CK_PD_PI_DUTYDAC_INFO(inst) ((inst) + 0x00000002), 0x00000105 + +#define REG_PD_REG_1_ADDR(inst) ((inst) + 0x00000003) +#define BF_AFE_PD_CAL_INFO(inst) ((inst) + 0x00000003), 0x00000100 +#define BF_AFE_PD_VCM_INFO(inst) ((inst) + 0x00000003), 0x00000101 +#define BF_CTLE_PD_ODAC_INFO(inst) ((inst) + 0x00000003), 0x00000102 + +#define REG_MBIAS_CTL_ADDR(inst) ((inst) + 0x00000004) +#define BF_RXDES_CTRL_MBIAS_INFO(inst) ((inst) + 0x00000004), 0x00000800 + +#define REG_CAL_ADDR(inst) ((inst) + 0x00000007) +#define BF_PHASESTATE_CAL_EN_INFO(inst) ((inst) + 0x00000007), 0x00000100 +#define BF_PHASESTATE_INFO(inst) ((inst) + 0x00000007), 0x00000104 + +#define REG_LF_DLL_ADDR(inst) ((inst) + 0x00000008) +#define BF_DLLSLEW_INFO(inst) ((inst) + 0x00000008), 0x00000200 +#define BF_DLLSLEW_PREDIV_INFO(inst) ((inst) + 0x00000008), 0x00000204 +#define BF_DLLSLEW_HALFDIV_INFO(inst) ((inst) + 0x00000008), 0x00000206 + +#define REG_LF_DESER_ADDR(inst) ((inst) + 0x00000009) +#define BF_SYNC_DESER8TO32_INFO(inst) ((inst) + 0x00000009), 0x00000100 +#define BF_CLKDIV8_INV_DESER8TO32_INFO(inst) ((inst) + 0x00000009), 0x00000101 +#define BF_CLKDIV32_INV_DESER8TO32_INFO(inst) ((inst) + 0x00000009), 0x00000102 +#define BF_PHI_TEST_EN_INFO(inst) ((inst) + 0x00000009), 0x00000103 + +#define REG_PAR_DATA_CTL_ADDR(inst) ((inst) + 0x0000000A) +#define BF_PAR_DATA_INV_INFO(inst) ((inst) + 0x0000000A), 0x00000100 +#define BF_PAR_CLK_EDGE_INFO(inst) ((inst) + 0x0000000A), 0x00000101 + +#define REG_LF_PHI_RS0_ADDR(inst) ((inst) + 0x0000000B) +#define BF_LF_PHI_DES_RS_INFO(inst) ((inst) + 0x0000000B), 0x00000E00 + +#define REG_LF_PHI_RS1_ADDR(inst) ((inst) + 0x0000000C) + +#define REG_TEST_ADDR(inst) ((inst) + 0x0000000E) +#define BF_RXDES_AMUX_SEL_INFO(inst) ((inst) + 0x0000000E), 0x00000500 + +#define REG_JTAG_ADDR(inst) ((inst) + 0x0000000F) +#define BF_JTAG_DBG_CLK_INFO(inst) ((inst) + 0x0000000F), 0x00000200 +#define BF_JTAG_DBG_INIT_D_INFO(inst) ((inst) + 0x0000000F), 0x00000202 + +#define REG_CK_CTL0_ADDR(inst) ((inst) + 0x00000010) +#define BF_CK_IBSEL_INFO(inst) ((inst) + 0x00000010), 0x00000100 +#define BF_CK_QBSEL_INFO(inst) ((inst) + 0x00000010), 0x00000101 +#define BF_CK_PI_COMSENSEEN_INFO(inst) ((inst) + 0x00000010), 0x00000102 +#define BF_CK_ENSLEWMEAS_INFO(inst) ((inst) + 0x00000010), 0x00000103 +#define BF_CK_PI_DUTYDAC_MAG_INFO(inst) ((inst) + 0x00000010), 0x00000204 +#define BF_CK_PI_DUTYDAC_SGN_INFO(inst) ((inst) + 0x00000010), 0x00000106 + +#define REG_CK_CTL1_ADDR(inst) ((inst) + 0x00000011) +#define BF_CK_PI_PHI_INFO(inst) ((inst) + 0x00000011), 0x00000700 +#define BF_CK_PI_PHI_CLK_INV_INFO(inst) ((inst) + 0x00000011), 0x00000107 + +#define REG_CK_CTL2_ADDR(inst) ((inst) + 0x00000012) +#define BF_CK_PI_SLEWFS_INFO(inst) ((inst) + 0x00000012), 0x00000500 +#define BF_CK_PI_SLEWFS_FORCE_INFO(inst) ((inst) + 0x00000012), 0x00000105 +#define BF_CK_PI_SLEWFS_CAL_FBEN_FORCE_INFO(inst) ((inst) + 0x00000012), 0x00000106 + +#define REG_CK_CTL3_ADDR(inst) ((inst) + 0x00000013) +#define BF_CK_PI_FBEN_INFO(inst) ((inst) + 0x00000013), 0x00000400 +#define BF_CK_PI_SLEW_DFLIP_INFO(inst) ((inst) + 0x00000013), 0x00000104 +#define BF_CK_SLEWRATE_CKFLIP_INFO(inst) ((inst) + 0x00000013), 0x00000105 + +#define REG_CK_CTL4_ADDR(inst) ((inst) + 0x00000014) +#define BF_CK_SPO_ISTROBE_INFO(inst) ((inst) + 0x00000014), 0x00000100 +#define BF_CK_SPO_QSTROBE_INFO(inst) ((inst) + 0x00000014), 0x00000101 +#define BF_CK_SPO_UP_DN_INFO(inst) ((inst) + 0x00000014), 0x00000102 + +#define REG_CK_CTL5_ADDR(inst) ((inst) + 0x00000015) +#define BF_CK_PI_CAL_INIT_INFO(inst) ((inst) + 0x00000015), 0x00000100 +#define BF_CK_PI_COUNT_TOTAL_INFO(inst) ((inst) + 0x00000015), 0x00000301 +#define BF_CK_PI_COUNT_THR_DIFF_INFO(inst) ((inst) + 0x00000015), 0x00000404 + +#define REG_CK_CTL6_ADDR(inst) ((inst) + 0x00000016) +#define BF_CK_PI_DUTY_SEL_INFO(inst) ((inst) + 0x00000016), 0x00000300 +#define BF_CK_PI_REG_READ_INFO(inst) ((inst) + 0x00000016), 0x00000203 +#define BF_CK_PI_ROCLK_INFO(inst) ((inst) + 0x00000016), 0x00000105 +#define BF_CK_PI_ROCLK_BYPASS_INFO(inst) ((inst) + 0x00000016), 0x00000106 +#define BF_CK_PI_MEAS_INIT_INFO(inst) ((inst) + 0x00000016), 0x00000107 + +#define REG_CK_CTL7_ADDR(inst) ((inst) + 0x00000017) +#define BF_CK_PI_SLEWFS_OUT_INFO(inst) ((inst) + 0x00000017), 0x00000500 +#define BF_CK_PI_MEASIOUT_INFO(inst) ((inst) + 0x00000017), 0x00000105 +#define BF_CK_PI_MEASQOUT_INFO(inst) ((inst) + 0x00000017), 0x00000106 + +#define REG_CK_CTL8_ADDR(inst) ((inst) + 0x00000018) +#define BF_CK_PI_CAL_STATE_INFO(inst) ((inst) + 0x00000018), 0x00000400 +#define BF_CK_PI_CAL_DONE_INFO(inst) ((inst) + 0x00000018), 0x00000104 +#define BF_CK_PI_CAL_INPROGRESS_INFO(inst) ((inst) + 0x00000018), 0x00000105 +#define BF_CK_PI_MEAS_DONE_INFO(inst) ((inst) + 0x00000018), 0x00000106 +#define BF_CK_PI_MEAS_INPROGRESS_INFO(inst) ((inst) + 0x00000018), 0x00000107 + +#define REG_CK_CTL9_ADDR(inst) ((inst) + 0x00000019) +#define BF_CK_PI_COUNT_OUT_INFO(inst) ((inst) + 0x00000019), 0x00001000 + +#define REG_CK_CTL10_ADDR(inst) ((inst) + 0x0000001A) + +#define REG_CTLE_CTL0_ADDR(inst) ((inst) + 0x00000020) +#define BF_CTLE_STROBE_INFO(inst) ((inst) + 0x00000020), 0x00000100 +#define BF_AFE_CAL_STROBE_INFO(inst) ((inst) + 0x00000020), 0x00000101 +#define BF_AFE_CAL_STEP_INFO(inst) ((inst) + 0x00000020), 0x00000102 +#define BF_AFE_CAL_INIT_INFO(inst) ((inst) + 0x00000020), 0x00000104 +#define BF_FORCE_AFE_CAL_INFO(inst) ((inst) + 0x00000020), 0x00000105 +#define BF_FORCE_CTLE_REG_INFO(inst) ((inst) + 0x00000020), 0x00000106 +#define BF_CTLE_REG_OVERRIDE_INFO(inst) ((inst) + 0x00000020), 0x00000107 + +#define REG_CTLE_CTL1_ADDR(inst) ((inst) + 0x00000021) +#define BF_AFE_STATE_INFO(inst) ((inst) + 0x00000021), 0x00000500 +#define BF_AFE_CAL_DONE_INFO(inst) ((inst) + 0x00000021), 0x00000105 +#define BF_AFE_CAL_OUT_INFO(inst) ((inst) + 0x00000021), 0x00000106 + +#define REG_CTLE_CTL2_ADDR(inst) ((inst) + 0x00000022) +#define BF_CTLE_REG_DROPOUT_INFO(inst) ((inst) + 0x00000022), 0x00000500 +#define BF_CTLE_REG_CM_ADJUST_INFO(inst) ((inst) + 0x00000022), 0x00000305 + +#define REG_CTLE_CTL3_ADDR(inst) ((inst) + 0x00000023) +#define BF_CTLE_S1_GM_INFO(inst) ((inst) + 0x00000023), 0x00000500 + +#define REG_CTLE_CTL4_ADDR(inst) ((inst) + 0x00000024) +#define BF_CTLE_S1_LD_INFO(inst) ((inst) + 0x00000024), 0x00000400 +#define BF_CTLE_SQUELCH_INFO(inst) ((inst) + 0x00000024), 0x00000104 + +#define REG_CTLE_CTL5_ADDR(inst) ((inst) + 0x00000025) +#define BF_CTLE_S2_GM_INFO(inst) ((inst) + 0x00000025), 0x00000400 +#define BF_CTLE_S2_LD_INFO(inst) ((inst) + 0x00000025), 0x00000404 + +#define REG_CTLE_CTL6_ADDR(inst) ((inst) + 0x00000026) +#define BF_CTLE_S1_RP_INFO(inst) ((inst) + 0x00000026), 0x00000300 +#define BF_CTLE_S2_RP_INFO(inst) ((inst) + 0x00000026), 0x00000304 + +#define REG_CTLE_CTL7_ADDR(inst) ((inst) + 0x00000027) +#define BF_CTLE_PGA_LD_INFO(inst) ((inst) + 0x00000027), 0x00000800 + +#define REG_CTLE_CTL8_ADDR(inst) ((inst) + 0x00000028) +#define BF_CTLE_PGA_GM_INFO(inst) ((inst) + 0x00000028), 0x00001000 + +#define REG_CTLE_CTL9_ADDR(inst) ((inst) + 0x00000029) + +#define REG_CTLE_CTL10_ADDR(inst) ((inst) + 0x0000002A) +#define BF_CTLE_RSHUNT_EN_INFO(inst) ((inst) + 0x0000002A), 0x00000200 +#define BF_CTLE_RSHUNT_5K_EN_INFO(inst) ((inst) + 0x0000002A), 0x00000102 +#define BF_CTLE_RSER_EN_INFO(inst) ((inst) + 0x0000002A), 0x00000103 +#define BF_CTLE_REG_OVERRIDE_AMP_INFO(inst) ((inst) + 0x0000002A), 0x00000104 + +#define REG_CTLE_CTL11_ADDR(inst) ((inst) + 0x0000002B) +#define BF_CTLE_CSER_INFO(inst) ((inst) + 0x0000002B), 0x00000F00 + +#define REG_CTLE_CTL12_ADDR(inst) ((inst) + 0x0000002C) + +#define REG_CTLE_CTL13_ADDR(inst) ((inst) + 0x0000002D) +#define BF_CTLE_B_CTLE_ODAC_INFO(inst) ((inst) + 0x0000002D), 0x00000500 + +#define REG_CTLE_CTL14_ADDR(inst) ((inst) + 0x0000002E) +#define BF_CTLE_B_AFE_ODAC_INFO(inst) ((inst) + 0x0000002E), 0x00000500 + +#define REG_CTLE_CTL15_ADDR(inst) ((inst) + 0x0000002F) +#define BF_AFE_PROG_DLY_INFO(inst) ((inst) + 0x0000002F), 0x00000200 +#define BF_AFE_PROG_DROPOUT_MIN_INFO(inst) ((inst) + 0x0000002F), 0x00000202 +#define BF_AFE_PROG_DROPOUT_MAX_INFO(inst) ((inst) + 0x0000002F), 0x00000204 + +#define REG_CTLE_CTL16_ADDR(inst) ((inst) + 0x00000030) +#define BF_CTLE_REG_DROPOUT_SM_INFO(inst) ((inst) + 0x00000030), 0x00000500 + +#define REG_CTLE_CTL17_ADDR(inst) ((inst) + 0x00000031) +#define BF_CTLE_B_AFE_ODAC_SM_INFO(inst) ((inst) + 0x00000031), 0x00000500 + +#define REG_RAM_CTL0_ADDR(inst) ((inst) + 0x00000032) +#define BF_RAM_CEN_INFO(inst) ((inst) + 0x00000032), 0x00000104 +#define BF_RAM_WEN_INFO(inst) ((inst) + 0x00000032), 0x00000105 +#define BF_RAM_BYPASS_INFO(inst) ((inst) + 0x00000032), 0x00000106 + +#define REG_RAM_CTL1_ADDR(inst) ((inst) + 0x00000033) +#define BF_RAM_ADDR_INFO(inst) ((inst) + 0x00000033), 0x00000C00 + +#define REG_RAM_CTL2_ADDR(inst) ((inst) + 0x00000034) +#define BF_RAM_WDATA_INFO(inst) ((inst) + 0x00000034), 0x00001000 + +#define REG_RAM_CTL3_ADDR(inst) ((inst) + 0x00000035) + +#define REG_RAM_CTL4_ADDR(inst) ((inst) + 0x00000036) +#define BF_RAM_RDATA_INFO(inst) ((inst) + 0x00000036), 0x00001000 + +#define REG_RAM_CTL5_ADDR(inst) ((inst) + 0x00000037) + +#define REG_LMS_CTL0_ADDR(inst) ((inst) + 0x00000038) +#define BF_LMS_RESET_INFO(inst) ((inst) + 0x00000038), 0x00000100 +#define BF_LMS_BREAKPT_EN_INFO(inst) ((inst) + 0x00000038), 0x00000101 +#define BF_BOOTLOAD_EN_INFO(inst) ((inst) + 0x00000038), 0x00000104 +#define BF_BOOTLOAD_START_INFO(inst) ((inst) + 0x00000038), 0x00000105 + +#define REG_LMS_CTL1_ADDR(inst) ((inst) + 0x00000039) +#define BF_BOOTLOAD_ON_INFO(inst) ((inst) + 0x00000039), 0x00000104 +#define BF_BOOTLOAD_DONE_INFO(inst) ((inst) + 0x00000039), 0x00000105 + +#define REG_LMS_CTL2_ADDR(inst) ((inst) + 0x0000003A) +#define BF_LMS_NUM_ITER_INFO(inst) ((inst) + 0x0000003A), 0x00000800 + +#define REG_LMS_CTL3_ADDR(inst) ((inst) + 0x0000003B) +#define BF_LMS_FLASH_MSK_PRE_INFO(inst) ((inst) + 0x0000003B), 0x00000800 + +#define REG_LMS_CTL4_ADDR(inst) ((inst) + 0x0000003C) +#define BF_LMS_FLASH_MSK_POST_INFO(inst) ((inst) + 0x0000003C), 0x00000800 + +#define REG_LMS_CTL5_ADDR(inst) ((inst) + 0x0000003D) +#define BF_LMS_UPP_THRESH_INFO(inst) ((inst) + 0x0000003D), 0x00001000 + +#define REG_LMS_CTL6_ADDR(inst) ((inst) + 0x0000003E) + +#define REG_LMS_CTL7_ADDR(inst) ((inst) + 0x0000003F) +#define BF_LMS_BREAKPT_INFO(inst) ((inst) + 0x0000003F), 0x00000B00 + +#define REG_LMS_CTL8_ADDR(inst) ((inst) + 0x00000040) + +#define REG_LMS_CTL9_ADDR(inst) ((inst) + 0x00000041) +#define BF_LMS_CTL_FLAG_INFO(inst) ((inst) + 0x00000041), 0x00000800 + +#define REG_LMS_CTL10_ADDR(inst) ((inst) + 0x00000042) +#define BF_LMS_INNER_UP_STA_INFO(inst) ((inst) + 0x00000042), 0x00000700 + +#define REG_LMS_CTL11_ADDR(inst) ((inst) + 0x00000043) +#define BF_LMS_OUTER_UP_STA_INFO(inst) ((inst) + 0x00000043), 0x00000700 + +#define REG_LMS_CTL12_ADDR(inst) ((inst) + 0x00000044) +#define BF_LMS_INNER_DN_STA_INFO(inst) ((inst) + 0x00000044), 0x00000700 + +#define REG_LMS_CTL13_ADDR(inst) ((inst) + 0x00000045) +#define BF_LMS_OUTER_DN_STA_INFO(inst) ((inst) + 0x00000045), 0x00000700 + +#define REG_LMS_CTL14_ADDR(inst) ((inst) + 0x00000046) +#define BF_LMS_B2_STA_INFO(inst) ((inst) + 0x00000046), 0x00000600 + +#define REG_LMS_CTL15_ADDR(inst) ((inst) + 0x00000047) +#define BF_LMS_B3_STA_INFO(inst) ((inst) + 0x00000047), 0x00000600 + +#define REG_LMS_CTL16_ADDR(inst) ((inst) + 0x00000048) +#define BF_LMS_B4_STA_INFO(inst) ((inst) + 0x00000048), 0x00000500 + +#define REG_LMS_CTL17_ADDR(inst) ((inst) + 0x00000049) +#define BF_LMS_B5_STA_INFO(inst) ((inst) + 0x00000049), 0x00000500 + +#define REG_LMS_CTL18_ADDR(inst) ((inst) + 0x0000004A) +#define BF_LMS_B6_STA_INFO(inst) ((inst) + 0x0000004A), 0x00000500 + +#define REG_LMS_CTL19_ADDR(inst) ((inst) + 0x0000004B) +#define BF_LMS_DONE_INFO(inst) ((inst) + 0x0000004B), 0x00000800 + +#define REG_CTL_SPARE0_ADDR(inst) ((inst) + 0x00000050) +#define BF_CTL_SPARE0_INFO(inst) ((inst) + 0x00000050), 0x00000800 + +#define REG_CTL_SPARE1_ADDR(inst) ((inst) + 0x00000051) +#define BF_CTL_SPARE1_INFO(inst) ((inst) + 0x00000051), 0x00000800 + +#define REG_CTL_SPARE2_ADDR(inst) ((inst) + 0x00000052) +#define BF_CTL_SPARE2_INFO(inst) ((inst) + 0x00000052), 0x00000800 + +#define REG_CTL_SPARE3_ADDR(inst) ((inst) + 0x00000053) +#define BF_CTL_SPARE3_INFO(inst) ((inst) + 0x00000053), 0x00000800 + +#define REG_STATUS_SPARE0_ADDR(inst) ((inst) + 0x00000054) +#define BF_STATUS_SPARE0_INFO(inst) ((inst) + 0x00000054), 0x00000800 + +#define REG_STATUS_SPARE1_ADDR(inst) ((inst) + 0x00000055) +#define BF_STATUS_SPARE1_INFO(inst) ((inst) + 0x00000055), 0x00000800 + +#define REG_VARDCO_CTL_0_ADDR(inst) ((inst) + 0x00000058) +#define BF_VARDCO_LFSR_VALUE_INFO(inst) ((inst) + 0x00000058), 0x00000500 +#define BF_VARDCO_LFSR_BYPASS_INFO(inst) ((inst) + 0x00000058), 0x00000105 +#define BF_VARDCO_EN_INFO(inst) ((inst) + 0x00000058), 0x00000106 + +#define REG_VARDCO_CTL_1_ADDR(inst) ((inst) + 0x00000059) +#define BF_VARDCO_DIVN_INFO(inst) ((inst) + 0x00000059), 0x00000300 +#define BF_VARDCO_DIVM_INFO(inst) ((inst) + 0x00000059), 0x00000304 + +#define REG_USR_RETIMER_CTL_ADDR(inst) ((inst) + 0x00000060) +#define BF_USR_PD_INFO(inst) ((inst) + 0x00000060), 0x00000100 +#define BF_USR_SLICE0_PD_INFO(inst) ((inst) + 0x00000060), 0x00000101 +#define BF_USR_SLICE1_PD_INFO(inst) ((inst) + 0x00000060), 0x00000102 +#define BF_USR_SEL_INFO(inst) ((inst) + 0x00000060), 0x00000103 +#define BF_USR_PI_DELAY_CAL_INIT_INFO(inst) ((inst) + 0x00000060), 0x00000104 +#define BF_USR_PI_DELAY_CAL_ITER_INFO(inst) ((inst) + 0x00000060), 0x00000205 + +#define REG_USR_CTLE_CTL0_ADDR(inst) ((inst) + 0x00000061) +#define BF_USR_GM_BOOST_EN_INFO(inst) ((inst) + 0x00000061), 0x00000100 +#define BF_USR_RESETB_TIA_COMP_ODACS_INFO(inst) ((inst) + 0x00000061), 0x00000101 +#define BF_USR_TIA_RSHORT_COMP_INFO(inst) ((inst) + 0x00000061), 0x00000102 +#define BF_USR_EN_TIA_AMUX_INFO(inst) ((inst) + 0x00000061), 0x00000103 +#define BF_USR_TIA_PD_COMP_INFO(inst) ((inst) + 0x00000061), 0x00000104 + +#define REG_USR_CTLE_CTL1_ADDR(inst) ((inst) + 0x00000062) +#define BF_USR_TIA_ODAC_INFO(inst) ((inst) + 0x00000062), 0x00000600 +#define BF_USR_TIA_ODAC_STROBE_INFO(inst) ((inst) + 0x00000062), 0x00000106 + +#define REG_USR_CTLE_CTL2_ADDR(inst) ((inst) + 0x00000063) +#define BF_USR_TIACOMP_ODAC_INFO(inst) ((inst) + 0x00000063), 0x00000600 +#define BF_USR_TIACOMP_ODAC_STROBE_INFO(inst) ((inst) + 0x00000063), 0x00000106 + +#define REG_USR_PI_CTL0_ADDR(inst) ((inst) + 0x00000064) +#define BF_USR_PI_SLEWFS_OFFSET_INFO(inst) ((inst) + 0x00000064), 0x00000500 +#define BF_USR_PI_ENMEAS_INFO(inst) ((inst) + 0x00000064), 0x00000105 +#define BF_USR_PI_SEL90_135_INFO(inst) ((inst) + 0x00000064), 0x00000106 +#define BF_USR_SLEWMEAS_JESD_SRC_INFO(inst) ((inst) + 0x00000064), 0x00000107 + +#define REG_USR_PI_CTL1_ADDR(inst) ((inst) + 0x00000065) +#define BF_USR_PI_PH45_INFO(inst) ((inst) + 0x00000065), 0x00000600 +#define BF_USR_PI_PH45_OVRD_INFO(inst) ((inst) + 0x00000065), 0x00000106 + +#define REG_USR_PI_CTL2_ADDR(inst) ((inst) + 0x00000066) +#define BF_USR_PI_PH45_OUT_INFO(inst) ((inst) + 0x00000066), 0x00000600 +#define BF_CK_USR_CAL_INPROGRESS_INFO(inst) ((inst) + 0x00000066), 0x00000106 +#define BF_CK_USR_CAL_DONE_INFO(inst) ((inst) + 0x00000066), 0x00000107 + +#define REG_USR_PI_CTL3_ADDR(inst) ((inst) + 0x00000067) +#define BF_USR_PI_PH135_INFO(inst) ((inst) + 0x00000067), 0x00000600 + +#define REG_USR_TIA_CAL_CTL0_ADDR(inst) ((inst) + 0x00000068) +#define BF_TIA_CAL_INIT_INFO(inst) ((inst) + 0x00000068), 0x00000100 +#define BF_TIA_DCMEASURE_INIT_INFO(inst) ((inst) + 0x00000068), 0x00000101 +#define BF_TIA_COMPCAL_BYP_INFO(inst) ((inst) + 0x00000068), 0x00000102 +#define BF_TIA_LA_OFFSET_BYP_INFO(inst) ((inst) + 0x00000068), 0x00000103 +#define BF_TIA_COMPCAL_POL_INFO(inst) ((inst) + 0x00000068), 0x00000104 +#define BF_TIA_LA_OFFSET_POL_INFO(inst) ((inst) + 0x00000068), 0x00000105 +#define BF_TIA_CAL_BYPASS_INFO(inst) ((inst) + 0x00000068), 0x00000106 + +#define REG_USR_TIA_CAL_STA0_ADDR(inst) ((inst) + 0x00000069) +#define BF_TIA_LIMAMP_CAL_STATE_INFO(inst) ((inst) + 0x00000069), 0x00000500 +#define BF_TIA_LIMAMP_CAL_DONE_INFO(inst) ((inst) + 0x00000069), 0x00000105 + +#define REG_USR_TIA_CAL_STA1_ADDR(inst) ((inst) + 0x0000006A) +#define BF_TIA_LIMAMP_CAL_STA_INFO(inst) ((inst) + 0x0000006A), 0x00000700 + +#define REG_USR_AMUX_CTL_ADDR(inst) ((inst) + 0x0000006B) +#define BF_RXDES_AMUX_USR_SEL_INFO(inst) ((inst) + 0x0000006B), 0x00000800 + +#define REG_USR_SPARE_CTL_ADDR(inst) ((inst) + 0x0000006C) +#define BF_USR_SPARE_INFO(inst) ((inst) + 0x0000006C), 0x00000800 + +#define REG_USR_TIA_DAC_OFF_MAG_CAL_STA_ADDR(inst) ((inst) + 0x0000006D) +#define BF_USR_TIA_DAC_OFF_MAG_CAL_INFO(inst) ((inst) + 0x0000006D), 0x00000600 + +#define REG_USR_B_ODAC_COMP_CAL_STA_ADDR(inst) ((inst) + 0x0000006E) +#define BF_USR_B_ODAC_COMP_CAL_INFO(inst) ((inst) + 0x0000006E), 0x00000600 + +#define REG_PRBS_DEBUG_CTL0_ADDR(inst) ((inst) + 0x00000070) +#define BF_PRBS_RCV_EN_INFO(inst) ((inst) + 0x00000070), 0x00000100 +#define BF_PRBS_RCV_DATAREC_EN_INFO(inst) ((inst) + 0x00000070), 0x00000101 +#define BF_PRBS_RCV_DATAREC_MODE_INFO(inst) ((inst) + 0x00000070), 0x00000202 +#define BF_PRBS_RCV_DATAREC_CLR_INFO(inst) ((inst) + 0x00000070), 0x00000104 +#define BF_PRBS_RCV_AUTO_MODE_INFO(inst) ((inst) + 0x00000070), 0x00000105 + +#define REG_PRBS_DEBUG_CTL1_ADDR(inst) ((inst) + 0x00000071) +#define BF_PRBS_RCV_AUTO_MODE_THRESH_INFO(inst) ((inst) + 0x00000071), 0x00000600 + +#define REG_PRBS_DEBUG_STA0_ADDR(inst) ((inst) + 0x00000072) +#define BF_PRBS_RCV_ERR_INFO(inst) ((inst) + 0x00000072), 0x00000100 +#define BF_PRBS_RCV_ERR_STICKY_INFO(inst) ((inst) + 0x00000072), 0x00000101 +#define BF_PRBS_RCV_AUTO_MODE_DONE_INFO(inst) ((inst) + 0x00000072), 0x00000104 + +#define REG_PRBS_DEBUG_STA1_ADDR(inst) ((inst) + 0x00000073) +#define BF_PRBS_RCV_ERR_CNT_INFO(inst) ((inst) + 0x00000073), 0x00002000 + +#define REG_PRBS_DEBUG_STA2_ADDR(inst) ((inst) + 0x00000074) + +#define REG_PRBS_DEBUG_STA3_ADDR(inst) ((inst) + 0x00000075) + +#define REG_PRBS_DEBUG_STA4_ADDR(inst) ((inst) + 0x00000076) + +#define REG_DAT_DEBUG_CTL0_ADDR(inst) ((inst) + 0x00000077) +#define BF_CAPTURE_SAMPLE_INFO(inst) ((inst) + 0x00000077), 0x00000100 +#define BF_DMX_OUT_CLK_GATE_INFO(inst) ((inst) + 0x00000077), 0x00000101 + +#define REG_DAT_DEBUG_SAMPLE0_ADDR(inst) ((inst) + 0x00000078) +#define BF_SAMPLE_LATCHED_DATA_INFO(inst) ((inst) + 0x00000078), 0x00002000 + +#define REG_DAT_DEBUG_SAMPLE1_ADDR(inst) ((inst) + 0x00000079) + +#define REG_DAT_DEBUG_SAMPLE2_ADDR(inst) ((inst) + 0x0000007A) + +#define REG_DAT_DEBUG_SAMPLE3_ADDR(inst) ((inst) + 0x0000007B) + +#define REG_DAT_DEBUG_SAMPLE4_ADDR(inst) ((inst) + 0x0000007C) +#define BF_SAMPLE_LATCHED_ERR_INFO(inst) ((inst) + 0x0000007C), 0x00002000 + +#define REG_DAT_DEBUG_SAMPLE5_ADDR(inst) ((inst) + 0x0000007D) + +#define REG_DAT_DEBUG_SAMPLE6_ADDR(inst) ((inst) + 0x0000007E) + +#define REG_DAT_DEBUG_SAMPLE7_ADDR(inst) ((inst) + 0x0000007F) + +#define REG_CAL_CTL0_ADDR(inst) ((inst) + 0x00000080) +#define BF_CAL_ACC_EN_INFO(inst) ((inst) + 0x00000080), 0x00000101 +#define BF_CAL_ACC_TIMEOUT_EN_INFO(inst) ((inst) + 0x00000080), 0x00000102 +#define BF_CAL_ACC_INTERRUPT_EN_INFO(inst) ((inst) + 0x00000080), 0x00000103 +#define BF_CAL_ACC_EIN_SRC_INFO(inst) ((inst) + 0x00000080), 0x00000204 + +#define REG_CAL_CTL1_ADDR(inst) ((inst) + 0x00000081) +#define BF_CAL_DSHIFT0_INFO(inst) ((inst) + 0x00000081), 0x00000300 +#define BF_CAL_FUNC0_INFO(inst) ((inst) + 0x00000081), 0x00000304 + +#define REG_CAL_CTL2_ADDR(inst) ((inst) + 0x00000082) +#define BF_CAL_DSHIFT1_INFO(inst) ((inst) + 0x00000082), 0x00000300 +#define BF_CAL_FUNC1_INFO(inst) ((inst) + 0x00000082), 0x00000304 + +#define REG_CAL_CTL3_ADDR(inst) ((inst) + 0x00000083) +#define BF_CAL_DSHIFT2_INFO(inst) ((inst) + 0x00000083), 0x00000300 +#define BF_CAL_FUNC2_INFO(inst) ((inst) + 0x00000083), 0x00000304 + +#define REG_CAL_CTL4_ADDR(inst) ((inst) + 0x00000084) +#define BF_CAL_DSHIFT3_INFO(inst) ((inst) + 0x00000084), 0x00000300 +#define BF_CAL_FUNC3_INFO(inst) ((inst) + 0x00000084), 0x00000304 + +#define REG_CAL_CTL5_ADDR(inst) ((inst) + 0x00000085) +#define BF_CAL_MASK0_INFO(inst) ((inst) + 0x00000085), 0x00000800 + +#define REG_CAL_CTL6_ADDR(inst) ((inst) + 0x00000086) +#define BF_CAL_MASK1_INFO(inst) ((inst) + 0x00000086), 0x00000800 + +#define REG_CAL_CTL7_ADDR(inst) ((inst) + 0x00000087) +#define BF_CAL_MASK2_INFO(inst) ((inst) + 0x00000087), 0x00000800 + +#define REG_CAL_CTL8_ADDR(inst) ((inst) + 0x00000088) +#define BF_CAL_MASK3_INFO(inst) ((inst) + 0x00000088), 0x00000800 + +#define REG_CAL_CTL9_ADDR(inst) ((inst) + 0x00000089) +#define BF_CAL_QUAD0_INFO(inst) ((inst) + 0x00000089), 0x00000400 +#define BF_CAL_QUAD1_INFO(inst) ((inst) + 0x00000089), 0x00000404 + +#define REG_CAL_CTL10_ADDR(inst) ((inst) + 0x0000008A) +#define BF_CAL_QUAD2_INFO(inst) ((inst) + 0x0000008A), 0x00000400 +#define BF_CAL_QUAD3_INFO(inst) ((inst) + 0x0000008A), 0x00000404 + +#define REG_CAL_CTL11_ADDR(inst) ((inst) + 0x0000008B) +#define BF_CAL_COUNT_LIMIT_INFO(inst) ((inst) + 0x0000008B), 0x00001000 + +#define REG_CAL_CTL12_ADDR(inst) ((inst) + 0x0000008C) + +#define REG_CAL_CTL13_ADDR(inst) ((inst) + 0x0000008D) +#define BF_CAL_TIMEOUT_CNT_INFO(inst) ((inst) + 0x0000008D), 0x00001000 + +#define REG_CAL_CTL14_ADDR(inst) ((inst) + 0x0000008E) + +#define REG_CAL_CTL15_ADDR(inst) ((inst) + 0x0000008F) +#define BF_CAL_ACC_DONE_ALL_STA_INFO(inst) ((inst) + 0x0000008F), 0x00000100 +#define BF_CAL_ACC_TIMEOUT_STA_INFO(inst) ((inst) + 0x0000008F), 0x00000101 +#define BF_CAL_ACC_INTERRUPT_INFO(inst) ((inst) + 0x0000008F), 0x00000102 + +#define REG_CAL_CTL16_ADDR(inst) ((inst) + 0x00000090) +#define BF_CAL_ACC_STA0_INFO(inst) ((inst) + 0x00000090), 0x00001000 + +#define REG_CAL_CTL17_ADDR(inst) ((inst) + 0x00000091) + +#define REG_CAL_CTL18_ADDR(inst) ((inst) + 0x00000092) +#define BF_CAL_ACC_STA1_INFO(inst) ((inst) + 0x00000092), 0x00001000 + +#define REG_CAL_CTL19_ADDR(inst) ((inst) + 0x00000093) + +#define REG_CAL_CTL20_ADDR(inst) ((inst) + 0x00000094) +#define BF_CAL_ACC_STA2_INFO(inst) ((inst) + 0x00000094), 0x00001000 + +#define REG_CAL_CTL21_ADDR(inst) ((inst) + 0x00000095) + +#define REG_CAL_CTL22_ADDR(inst) ((inst) + 0x00000096) +#define BF_CAL_ACC_STA3_INFO(inst) ((inst) + 0x00000096), 0x00001000 + +#define REG_CAL_CTL23_ADDR(inst) ((inst) + 0x00000097) + +#define REG_CAL_CTL24_ADDR(inst) ((inst) + 0x00000098) +#define BF_CAL_CNT_STA0_INFO(inst) ((inst) + 0x00000098), 0x00001000 + +#define REG_CAL_CTL25_ADDR(inst) ((inst) + 0x00000099) + +#define REG_CAL_CTL26_ADDR(inst) ((inst) + 0x0000009A) +#define BF_CAL_CNT_STA1_INFO(inst) ((inst) + 0x0000009A), 0x00001000 + +#define REG_CAL_CTL27_ADDR(inst) ((inst) + 0x0000009B) + +#define REG_CAL_CTL28_ADDR(inst) ((inst) + 0x0000009C) +#define BF_CAL_CNT_STA2_INFO(inst) ((inst) + 0x0000009C), 0x00001000 + +#define REG_CAL_CTL29_ADDR(inst) ((inst) + 0x0000009D) + +#define REG_CAL_CTL30_ADDR(inst) ((inst) + 0x0000009E) +#define BF_CAL_CNT_STA3_INFO(inst) ((inst) + 0x0000009E), 0x00001000 + +#define REG_CAL_CTL31_ADDR(inst) ((inst) + 0x0000009F) + +#define REG_CAL_CTL32_ADDR(inst) ((inst) + 0x000000A0) +#define BF_CAL_LCNT_STA_INFO(inst) ((inst) + 0x000000A0), 0x00001000 + +#define REG_CAL_CTL33_ADDR(inst) ((inst) + 0x000000A1) + +#define REG_DCMEASURE_CTL0_ADDR(inst) ((inst) + 0x000000A8) +#define BF_DCMEASURE_CAL_EN_INFO(inst) ((inst) + 0x000000A8), 0x00000100 +#define BF_DCMEASURE_LD_INFO(inst) ((inst) + 0x000000A8), 0x00000101 +#define BF_DCMEASURE_HOLD_INFO(inst) ((inst) + 0x000000A8), 0x00000102 +#define BF_DCMEASURE_POL_INFO(inst) ((inst) + 0x000000A8), 0x00000103 +#define BF_DCD_DAC_DC_CNT_RDBK_HOLD_RC_INFO(inst) ((inst) + 0x000000A8), 0x00000104 + +#define REG_DCMEASURE_CTL1_ADDR(inst) ((inst) + 0x000000A9) +#define BF_DCMEASURE_CTLE_B_CTLE_ODAC_INFO(inst) ((inst) + 0x000000A9), 0x00000500 + +#define REG_DCD_DAC_DCUP_CNT_RDBK_0_ADDR(inst) ((inst) + 0x000000AA) +#define BF_DCD_DAC_DCUP_CNT_RDBK_RS_INFO(inst) ((inst) + 0x000000AA), 0x00000B00 + +#define REG_DCD_DAC_DCUP_CNT_RDBK_1_ADDR(inst) ((inst) + 0x000000AB) + +#define REG_DCD_DAC_DCDN_CNT_RDBK_0_ADDR(inst) ((inst) + 0x000000AC) +#define BF_DCD_DAC_DCDN_CNT_RDBK_RS_INFO(inst) ((inst) + 0x000000AC), 0x00000B00 + +#define REG_DCD_DAC_DCDN_CNT_RDBK_1_ADDR(inst) ((inst) + 0x000000AD) + +#define REG_DCD_DAC_HYSTERESIS_ADDR(inst) ((inst) + 0x000000AE) +#define BF_DCD_DAC_HYSTERESIS_CODE_RC_INFO(inst) ((inst) + 0x000000AE), 0x00000800 + +#define REG_EYEMON_CTL0_ADDR(inst) ((inst) + 0x000000B0) +#define BF_EYEMON_EN_INFO(inst) ((inst) + 0x000000B0), 0x00000100 +#define BF_EYEMON_START_INFO(inst) ((inst) + 0x000000B0), 0x00000101 +#define BF_EYEMON_MEAS_EN_INFO(inst) ((inst) + 0x000000B0), 0x00000104 + +#define REG_EYEMON_CTL1_ADDR(inst) ((inst) + 0x000000B1) +#define BF_EYEMON_THRESH_INFO(inst) ((inst) + 0x000000B1), 0x00000800 + +#define REG_EYEMON_STATUS0_ADDR(inst) ((inst) + 0x000000B2) +#define BF_EYEMON_STATE_INFO(inst) ((inst) + 0x000000B2), 0x00000600 + +#define REG_EYEMON_STATUS1_ADDR(inst) ((inst) + 0x000000B3) +#define BF_EYEMON_SPOI_CNT_INFO(inst) ((inst) + 0x000000B3), 0x00000500 + +#define REG_EYEMON_STATUS2_ADDR(inst) ((inst) + 0x000000B4) +#define BF_EYEMON_SPOQ_CNT_INFO(inst) ((inst) + 0x000000B4), 0x00000500 + +#define REG_EYEMON_STATUS3_ADDR(inst) ((inst) + 0x000000B5) +#define BF_EYEMON_SPOG_MEAS_INFO(inst) ((inst) + 0x000000B5), 0x00001000 + +#define REG_EYEMON_STATUS4_ADDR(inst) ((inst) + 0x000000B6) + +#define REG_EYEMON_STATUS5_ADDR(inst) ((inst) + 0x000000B7) +#define BF_EYEMON_SPOI_MEAS_INFO(inst) ((inst) + 0x000000B7), 0x00001000 + +#define REG_EYEMON_STATUS6_ADDR(inst) ((inst) + 0x000000B8) + +#define REG_EYEMON_STATUS7_ADDR(inst) ((inst) + 0x000000B9) +#define BF_EYEMON_SPOQ_MEAS_INFO(inst) ((inst) + 0x000000B9), 0x00001000 + +#define REG_EYEMON_STATUS8_ADDR(inst) ((inst) + 0x000000BA) + +#define REG_DFE_CTL0_ADDR(inst) ((inst) + 0x000000C0) +#define BF_S0_PD_IFB2_INFO(inst) ((inst) + 0x000000C0), 0x00000100 +#define BF_S0_PD_IFB3_INFO(inst) ((inst) + 0x000000C0), 0x00000101 +#define BF_S1_PD_IFB2_INFO(inst) ((inst) + 0x000000C0), 0x00000102 +#define BF_S1_PD_IFB3_INFO(inst) ((inst) + 0x000000C0), 0x00000103 + +#define REG_DFE_CTL1_ADDR(inst) ((inst) + 0x000000C1) +#define BF_FORCE_E_S0F0_INFO(inst) ((inst) + 0x000000C1), 0x00000400 +#define BF_FORCE_E_S0F1_INFO(inst) ((inst) + 0x000000C1), 0x00000404 + +#define REG_DFE_CTL2_ADDR(inst) ((inst) + 0x000000C2) +#define BF_FORCE_E_S1F0_INFO(inst) ((inst) + 0x000000C2), 0x00000400 +#define BF_FORCE_E_S1F1_INFO(inst) ((inst) + 0x000000C2), 0x00000404 + +#define REG_DFE_CTL3_ADDR(inst) ((inst) + 0x000000C3) +#define BF_S0_B_FB2_INFO(inst) ((inst) + 0x000000C3), 0x00000600 + +#define REG_DFE_CTL4_ADDR(inst) ((inst) + 0x000000C4) +#define BF_S0_B_FB3_INFO(inst) ((inst) + 0x000000C4), 0x00000600 + +#define REG_DFE_CTL5_ADDR(inst) ((inst) + 0x000000C5) +#define BF_S1_B_FB2_INFO(inst) ((inst) + 0x000000C5), 0x00000600 + +#define REG_DFE_CTL6_ADDR(inst) ((inst) + 0x000000C6) +#define BF_S1_B_FB3_INFO(inst) ((inst) + 0x000000C6), 0x00000600 + +#define REG_DFE_CTL7_ADDR(inst) ((inst) + 0x000000C7) +#define BF_DFE_CM_GMSW_INFO(inst) ((inst) + 0x000000C7), 0x00000500 +#define BF_DFE_CM_GMSW_OVRD_INFO(inst) ((inst) + 0x000000C7), 0x00000105 +#define BF_DFE_GMSW_CAP_DEL_INFO(inst) ((inst) + 0x000000C7), 0x00000106 + +#define REG_DFE_CTL8_ADDR(inst) ((inst) + 0x000000C8) +#define BF_S0_USESKEW_INFO(inst) ((inst) + 0x000000C8), 0x00000600 + +#define REG_DFE_CTL9_ADDR(inst) ((inst) + 0x000000C9) +#define BF_S1_USESKEW_INFO(inst) ((inst) + 0x000000C9), 0x00000600 + +#define REG_DFE_CTL10_ADDR(inst) ((inst) + 0x000000CA) +#define BF_S0_B_THRB1_INFO(inst) ((inst) + 0x000000CA), 0x00000700 + +#define REG_DFE_CTL11_ADDR(inst) ((inst) + 0x000000CB) +#define BF_S0_B_THRC20_INFO(inst) ((inst) + 0x000000CB), 0x00000700 + +#define REG_DFE_CTL12_ADDR(inst) ((inst) + 0x000000CC) +#define BF_S0_B_THRC21_INFO(inst) ((inst) + 0x000000CC), 0x00000700 + +#define REG_DFE_CTL13_ADDR(inst) ((inst) + 0x000000CD) +#define BF_S1_B_THRB1_INFO(inst) ((inst) + 0x000000CD), 0x00000700 + +#define REG_DFE_CTL14_ADDR(inst) ((inst) + 0x000000CE) +#define BF_S1_B_THRC20_INFO(inst) ((inst) + 0x000000CE), 0x00000700 + +#define REG_DFE_CTL15_ADDR(inst) ((inst) + 0x000000CF) +#define BF_S1_B_THRC21_INFO(inst) ((inst) + 0x000000CF), 0x00000700 + +#define REG_DFE_CTL16_ADDR(inst) ((inst) + 0x000000D0) +#define BF_S0_GM_SWITCH_OFF_VIP_INFO(inst) ((inst) + 0x000000D0), 0x00000500 + +#define REG_DFE_CTL17_ADDR(inst) ((inst) + 0x000000D1) +#define BF_S0_GM_SWITCH_OFF_VIN_INFO(inst) ((inst) + 0x000000D1), 0x00000500 + +#define REG_DFE_CTL18_ADDR(inst) ((inst) + 0x000000D2) +#define BF_S0_PD_CLKGEN_INFO(inst) ((inst) + 0x000000D2), 0x00000100 +#define BF_S0_PD_DAC_THR_INFO(inst) ((inst) + 0x000000D2), 0x00000303 +#define BF_S0_MUX_EN_OVRD_INFO(inst) ((inst) + 0x000000D2), 0x00000206 + +#define REG_DFE_CTL19_ADDR(inst) ((inst) + 0x000000D3) +#define BF_S0_PD_DAC_OFF_INFO(inst) ((inst) + 0x000000D3), 0x00000800 + +#define REG_DFE_CTL20_ADDR(inst) ((inst) + 0x000000D4) +#define BF_S0_B_F0I0_INFO(inst) ((inst) + 0x000000D4), 0x00000500 + +#define REG_DFE_CTL21_ADDR(inst) ((inst) + 0x000000D5) +#define BF_S0_B_F0I1_INFO(inst) ((inst) + 0x000000D5), 0x00000500 + +#define REG_DFE_CTL22_ADDR(inst) ((inst) + 0x000000D6) +#define BF_S0_B_F0I2_INFO(inst) ((inst) + 0x000000D6), 0x00000500 + +#define REG_DFE_CTL23_ADDR(inst) ((inst) + 0x000000D7) +#define BF_S0_B_F0I3_INFO(inst) ((inst) + 0x000000D7), 0x00000500 + +#define REG_DFE_CTL24_ADDR(inst) ((inst) + 0x000000D8) +#define BF_S0_B_F1I0_INFO(inst) ((inst) + 0x000000D8), 0x00000500 + +#define REG_DFE_CTL25_ADDR(inst) ((inst) + 0x000000D9) +#define BF_S0_B_F1I1_INFO(inst) ((inst) + 0x000000D9), 0x00000500 + +#define REG_DFE_CTL26_ADDR(inst) ((inst) + 0x000000DA) +#define BF_S0_B_F1I2_INFO(inst) ((inst) + 0x000000DA), 0x00000500 + +#define REG_DFE_CTL27_ADDR(inst) ((inst) + 0x000000DB) +#define BF_S0_B_F1I3_INFO(inst) ((inst) + 0x000000DB), 0x00000500 + +#define REG_DFE_CTL28_ADDR(inst) ((inst) + 0x000000DC) +#define BF_S0_PD_COMP_F0_INFO(inst) ((inst) + 0x000000DC), 0x00000400 +#define BF_S0_PD_COMP_F1_INFO(inst) ((inst) + 0x000000DC), 0x00000404 + +#define REG_DFE_CTL28X_ADDR(inst) ((inst) + 0x000000DD) +#define BF_S0_USE_COMP23_DATA_INFO(inst) ((inst) + 0x000000DD), 0x00000100 + +#define REG_DFE_CTL29_ADDR(inst) ((inst) + 0x000000E0) +#define BF_S1_GM_SWITCH_OFF_VIP_INFO(inst) ((inst) + 0x000000E0), 0x00000500 + +#define REG_DFE_CTL30_ADDR(inst) ((inst) + 0x000000E1) +#define BF_S1_GM_SWITCH_OFF_VIN_INFO(inst) ((inst) + 0x000000E1), 0x00000500 + +#define REG_DFE_CTL31_ADDR(inst) ((inst) + 0x000000E2) +#define BF_S1_PD_CLKGEN_INFO(inst) ((inst) + 0x000000E2), 0x00000100 +#define BF_S1_PD_DAC_THR_INFO(inst) ((inst) + 0x000000E2), 0x00000303 +#define BF_S1_MUX_EN_OVRD_INFO(inst) ((inst) + 0x000000E2), 0x00000206 + +#define REG_DFE_CTL32_ADDR(inst) ((inst) + 0x000000E3) +#define BF_S1_PD_DAC_OFF_INFO(inst) ((inst) + 0x000000E3), 0x00000800 + +#define REG_DFE_CTL33_ADDR(inst) ((inst) + 0x000000E4) +#define BF_S1_B_F0I0_INFO(inst) ((inst) + 0x000000E4), 0x00000500 + +#define REG_DFE_CTL34_ADDR(inst) ((inst) + 0x000000E5) +#define BF_S1_B_F0I1_INFO(inst) ((inst) + 0x000000E5), 0x00000500 + +#define REG_DFE_CTL35_ADDR(inst) ((inst) + 0x000000E6) +#define BF_S1_B_F0I2_INFO(inst) ((inst) + 0x000000E6), 0x00000500 + +#define REG_DFE_CTL36_ADDR(inst) ((inst) + 0x000000E7) +#define BF_S1_B_F0I3_INFO(inst) ((inst) + 0x000000E7), 0x00000500 + +#define REG_DFE_CTL37_ADDR(inst) ((inst) + 0x000000E8) +#define BF_S1_B_F1I0_INFO(inst) ((inst) + 0x000000E8), 0x00000500 + +#define REG_DFE_CTL38_ADDR(inst) ((inst) + 0x000000E9) +#define BF_S1_B_F1I1_INFO(inst) ((inst) + 0x000000E9), 0x00000500 + +#define REG_DFE_CTL39_ADDR(inst) ((inst) + 0x000000EA) +#define BF_S1_B_F1I2_INFO(inst) ((inst) + 0x000000EA), 0x00000500 + +#define REG_DFE_CTL40_ADDR(inst) ((inst) + 0x000000EB) +#define BF_S1_B_F1I3_INFO(inst) ((inst) + 0x000000EB), 0x00000500 + +#define REG_DFE_CTL41_ADDR(inst) ((inst) + 0x000000EC) +#define BF_S1_PD_COMP_F0_INFO(inst) ((inst) + 0x000000EC), 0x00000400 +#define BF_S1_PD_COMP_F1_INFO(inst) ((inst) + 0x000000EC), 0x00000404 + +#define REG_DFE_CTL41X_ADDR(inst) ((inst) + 0x000000ED) +#define BF_S1_USE_COMP23_DATA_INFO(inst) ((inst) + 0x000000ED), 0x00000100 + +#define REG_DFE_CTL42_ADDR(inst) ((inst) + 0x000000EE) +#define BF_DFE_FB_SUM_INFO(inst) ((inst) + 0x000000EE), 0x00000500 +#define BF_DFE_FB_SUM_OVRD_INFO(inst) ((inst) + 0x000000EE), 0x00000105 + +#define REG_DFE_CTL43_ADDR(inst) ((inst) + 0x000000EF) +#define BF_S0_B_FB4_INFO(inst) ((inst) + 0x000000EF), 0x00000500 +#define BF_S0_PD_FB456_INFO(inst) ((inst) + 0x000000EF), 0x00000107 + +#define REG_DFE_CTL44_ADDR(inst) ((inst) + 0x000000F0) +#define BF_S0_B_FB5_INFO(inst) ((inst) + 0x000000F0), 0x00000500 + +#define REG_DFE_CTL44X_ADDR(inst) ((inst) + 0x000000F1) +#define BF_S0_B_FB6_INFO(inst) ((inst) + 0x000000F1), 0x00000500 + +#define REG_DFE_CTL45_ADDR(inst) ((inst) + 0x000000F2) +#define BF_S1_B_FB4_INFO(inst) ((inst) + 0x000000F2), 0x00000500 +#define BF_S1_PD_FB456_INFO(inst) ((inst) + 0x000000F2), 0x00000107 + +#define REG_DFE_CTL46_ADDR(inst) ((inst) + 0x000000F3) +#define BF_S1_B_FB5_INFO(inst) ((inst) + 0x000000F3), 0x00000500 + +#define REG_DFE_CTL46X_ADDR(inst) ((inst) + 0x000000F4) +#define BF_S1_B_FB6_INFO(inst) ((inst) + 0x000000F4), 0x00000500 + +#define REG_DFE_CTL47_ADDR(inst) ((inst) + 0x000000F5) +#define BF_DFE_STROBE_INFO(inst) ((inst) + 0x000000F5), 0x00000100 + +#define REG_DFE_CTL48_ADDR(inst) ((inst) + 0x000000F6) +#define BF_RSELU_INFO(inst) ((inst) + 0x000000F6), 0x00000300 +#define BF_RSELU_BYPASS_INFO(inst) ((inst) + 0x000000F6), 0x00000103 + +#define REG_DFE_CTL49_ADDR(inst) ((inst) + 0x000000F7) +#define BF_CLKGEN_PD_VAL_SEL_INFO(inst) ((inst) + 0x000000F7), 0x00000200 +#define BF_PD_VCM_INFO(inst) ((inst) + 0x000000F7), 0x00000102 + +#define REG_DFE_CTL50_ADDR(inst) ((inst) + 0x000000F8) +#define BF_S1_DMX_SWP_DIV2_INFO(inst) ((inst) + 0x000000F8), 0x00000100 + +#define REG_DFE_CTL51_ADDR(inst) ((inst) + 0x000000F9) +#define BF_RHO_INFO(inst) ((inst) + 0x000000F9), 0x00000800 + +#define REG_DFE_CTL52_ADDR(inst) ((inst) + 0x000000FA) +#define BF_EN_FLASH_SRC_DES_RC_INFO(inst) ((inst) + 0x000000FA), 0x00000400 +#define BF_EN_FLASH_MASK_DES_RC_INFO(inst) ((inst) + 0x000000FA), 0x00000404 + +#define REG_DFE_CTL53_ADDR(inst) ((inst) + 0x000000FB) +#define BF_PROG_NMAK_REFDAC_INFO(inst) ((inst) + 0x000000FB), 0x00000200 +#define BF_PROG_NMAK_PDAC_INFO(inst) ((inst) + 0x000000FB), 0x00000202 + +#define REG_DFE_CTL54_ADDR(inst) ((inst) + 0x000000FC) +#define BF_S0_PD_GMSW_INFO(inst) ((inst) + 0x000000FC), 0x00000100 +#define BF_S0_SHORT_GMSW_INFO(inst) ((inst) + 0x000000FC), 0x00000101 +#define BF_S1_PD_GMSW_INFO(inst) ((inst) + 0x000000FC), 0x00000102 +#define BF_S1_SHORT_GMSW_INFO(inst) ((inst) + 0x000000FC), 0x00000103 + +#define REG_DIG_REVID_ADDR(inst) ((inst) + 0x000000FE) +#define BF_RX_DIG_REVID_INFO(inst) ((inst) + 0x000000FE), 0x00000800 + +#define REG_ANA_REVID_ADDR(inst) ((inst) + 0x000000FF) +#define BF_RX_ANA_REVID_INFO(inst) ((inst) + 0x000000FF), 0x00000800 + +#endif /* __ADI_APOLLO_BF_SERDES_RXDIG_PHY_CORE1P3_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_serdes_txdig_12pack_apollo_core1p1.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_serdes_txdig_12pack_apollo_core1p1.h new file mode 100644 index 00000000000000..ca1e94fd7ab60c --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_serdes_txdig_12pack_apollo_core1p1.h @@ -0,0 +1,98 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:24 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_SERDES_TXDIG_12PACK_APOLLO_CORE1P1_H__ +#define __ADI_APOLLO_BF_SERDES_TXDIG_12PACK_APOLLO_CORE1P1_H__ + +/*============= D E F I N E S ==============*/ +#define SER_PHY_TOP_12PACK_SERDES_TX_JTX_TOP_RX_DIGITAL0 0x60628000 +#define SER_PHY_TOP_12PACK_SERDES_TX_JTX_TOP_RX_DIGITAL1 0x60E28000 + +#define REG_TXSER_12PACK_CLK_CTL0_ADDR(inst) ((inst) + 0x00000000) +#define BF_SER_CLK_DIV_INFO(inst) ((inst) + 0x00000000), 0x00000200 + +#define REG_TXSER_12PACK_PD_ADDR(inst) ((inst) + 0x00000001) +#define BF_SER_CLK_PD_INFO(inst) ((inst) + 0x00000001), 0x00000100 +#define BF_DES_CLK_PD_INFO(inst) ((inst) + 0x00000001), 0x00000101 +#define BF_SERDES_CLK_PD_INFO(inst) ((inst) + 0x00000001), 0x00000102 + +#define REG_TXSER_12PACK_CLK_PD_ADDR(inst) ((inst) + 0x00000002) +#define BF_TXSER_PD_CLK_RX_INFO(inst) ((inst) + 0x00000002), 0x00000100 + +#define REG_TXSER_12PACK_CLK_CTL1_ADDR(inst) ((inst) + 0x00000003) +#define BF_TEST_CLK_OUTPUT_PD_INFO(inst) ((inst) + 0x00000003), 0x00000104 +#define BF_TEST_CLK_RECEIVER_PD_INFO(inst) ((inst) + 0x00000003), 0x00000105 +#define BF_SEL_EXT_REF_CLK_INFO(inst) ((inst) + 0x00000003), 0x00000106 +#define BF_SER_CLK_DIV_RESETB_INFO(inst) ((inst) + 0x00000003), 0x00000107 + +#define REG_TXSER_12PACK_JTAG_CTL0_ADDR(inst) ((inst) + 0x00000004) +#define BF_TXSER_JTAG_DATA_INV_INFO(inst) ((inst) + 0x00000004), 0x00000C00 + +#define REG_TXSER_12PACK_JTAG_CTL1_ADDR(inst) ((inst) + 0x00000005) + +#define REG_TXSER_12PACK_TEST_CTL_ADDR(inst) ((inst) + 0x00000006) +#define BF_TXSER_EN_SER_TESTV_OUT_INFO(inst) ((inst) + 0x00000006), 0x00000100 + +#define REG_TXSER_12PACK_TEST_CTL2_ADDR(inst) ((inst) + 0x00000007) +#define BF_TEST_CLK_SEL_INFO(inst) ((inst) + 0x00000007), 0x00000300 + +#define REG_TXSER_12PACK_PLL_REF_CTL_ADDR(inst) ((inst) + 0x00000008) +#define BF_PLL_REF_CLK_INFO(inst) ((inst) + 0x00000008), 0x00000800 + +#define REG_TXSER_12PACK_TERM_CAL_ADDR(inst) ((inst) + 0x00000010) +#define BF_DRVRPOLYCODE_INFO(inst) ((inst) + 0x00000010), 0x00000600 +#define BF_DRVSLICEOFFSETEN_INFO(inst) ((inst) + 0x00000010), 0x00000106 +#define BF_OFFSET32_EN_INFO(inst) ((inst) + 0x00000010), 0x00000107 + +#define REG_TXSER_12PACK_USR0_ADDR(inst) ((inst) + 0x00000020) +#define BF_TXSER_USR_CTL0_INFO(inst) ((inst) + 0x00000020), 0x00000800 + +#define REG_TXSER_12PACK_USR1_ADDR(inst) ((inst) + 0x00000021) +#define BF_TXSER_USR_CTL1_INFO(inst) ((inst) + 0x00000021), 0x00000800 + +#define REG_TXSER_12PACK_USR2_ADDR(inst) ((inst) + 0x00000022) +#define BF_TXSER_USR_CTL2_INFO(inst) ((inst) + 0x00000022), 0x00000800 + +#define REG_TXSER_12PACK_USR3_ADDR(inst) ((inst) + 0x00000023) +#define BF_TXSER_USR_CTL3_INFO(inst) ((inst) + 0x00000023), 0x00000800 + +#define REG_TXSER_12PACK_USR4_ADDR(inst) ((inst) + 0x00000024) +#define BF_TXSER_USR_CTL4_INFO(inst) ((inst) + 0x00000024), 0x00000800 + +#define REG_TXSER_12PACK_USR5_ADDR(inst) ((inst) + 0x00000025) +#define BF_TXSER_USR_CTL5_INFO(inst) ((inst) + 0x00000025), 0x00000800 + +#define REG_TXSER_12PACK_USR6_ADDR(inst) ((inst) + 0x00000026) +#define BF_TXSER_USR_CTL6_INFO(inst) ((inst) + 0x00000026), 0x00000800 + +#define REG_TXSER_12PACK_USR7_ADDR(inst) ((inst) + 0x00000027) +#define BF_TXSER_USR_CTL7_INFO(inst) ((inst) + 0x00000027), 0x00000800 + +#define REG_TXSER_12PACK_USR8_ADDR(inst) ((inst) + 0x00000028) +#define BF_TXSER_USR_CTL8_INFO(inst) ((inst) + 0x00000028), 0x00000800 + +#define REG_TXSER_12PACK_USR9_ADDR(inst) ((inst) + 0x00000029) +#define BF_TXSER_USR_STA0_INFO(inst) ((inst) + 0x00000029), 0x00000800 + +#define REG_TXSER_12PACK_USR10_ADDR(inst) ((inst) + 0x0000002A) +#define BF_TXSER_USR_STA1_INFO(inst) ((inst) + 0x0000002A), 0x00000800 + +#define REG_TXSER_12PACK_SPARE_ADDR(inst) ((inst) + 0x00000030) +#define BF_SPARE_CTL_SERDES_TXDIG_12PACK_APOLLO__CORE1P1_INFO(inst) ((inst) + 0x00000030), 0x00000800 + +#define REG_TXSER_12PACK_REVID_ADDR(inst) ((inst) + 0x000000FF) +#define BF_TXSER_12PACK_REVID_INFO(inst) ((inst) + 0x000000FF), 0x00000800 + +#endif /* __ADI_APOLLO_BF_SERDES_TXDIG_12PACK_APOLLO_CORE1P1_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_serdes_txdig_dcc_core1p3.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_serdes_txdig_dcc_core1p3.h new file mode 100644 index 00000000000000..b1032566db292d --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_serdes_txdig_dcc_core1p3.h @@ -0,0 +1,85 @@ +/*! + * \brief SPI Register Definition Header File, automatically generated by + * /nobackup/jbirnie/yoda_bb_workdir/yoda2h_v1.3.6 v1.3.6 at 4/21/2021 7:18:45 PM. + * + * \copyright copyright(c) 2018 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_SERDES_TXDIG_DCC_CORE1P3_H__ +#define __ADI_APOLLO_BF_SERDES_TXDIG_DCC_CORE1P3_H__ + +/*============= D E F I N E S ==============*/ +#define SER_PHY_TOP_12PACK_SERDES_TX_JTX_TOP_RX_DIGITAL0 0x60628000 +#define SER_PHY_TOP_12PACK_SERDES_TX_JTX_TOP_RX_DIGITAL1 0x60E28000 + +#define REG_TXSER_12PACK_CLK_CTL_ADDR(inst) ((inst) + 0x00000000) +#define BF_TXSER_TX_PATH_CLK_DIV_INFO(inst) ((inst) + 0x00000000), 0x00000200 + +#define REG_TXSER_12PACK_PD_ADDR(inst) ((inst) + 0x00000001) +#define BF_TXSER_PD_SER_CLK_INFO(inst) ((inst) + 0x00000001), 0x00000100 +#define BF_TXSER_PD_DES_CLK_INFO(inst) ((inst) + 0x00000001), 0x00000101 + +#define REG_TXSER_12PACK_CLK_PD_ADDR(inst) ((inst) + 0x00000002) +#define BF_TXSER_PD_CLK_RX_INFO(inst) ((inst) + 0x00000002), 0x00000100 + +#define REG_TXSER_12PACK_OFFSET_CTL_ADDR(inst) ((inst) + 0x00000003) +#define BF_DRV_RPOLY_CODE_INFO(inst) ((inst) + 0x00000003), 0x00000600 +#define BF_DRV_SLICE_OFFSET_EN_INFO(inst) ((inst) + 0x00000003), 0x00000106 +#define BF_OFFSET32_EN_INFO(inst) ((inst) + 0x00000003), 0x00000107 + +#define REG_TXSER_12PACK_JTAG_CTL0_ADDR(inst) ((inst) + 0x00000004) +#define BF_TXSER_JTAG_DATA_INV_INFO(inst) ((inst) + 0x00000004), 0x00000C00 + +#define REG_TXSER_12PACK_JTAG_CTL1_ADDR(inst) ((inst) + 0x00000005) + +#define REG_TXSER_12PACK_TEST_CTL_ADDR(inst) ((inst) + 0x00000006) +#define BF_TXSER_EN_SER_TESTV_OUT_INFO(inst) ((inst) + 0x00000006), 0x00000100 + +#define REG_TXSER_12PACK_SPARE_ADDR(inst) ((inst) + 0x00000007) +#define BF_SPARE_CTL_SERDES_TXDIG_DCC__CORE1P3_INFO(inst) ((inst) + 0x00000007), 0x00000800 + +#define REG_TXSER_12PACK_USR0_ADDR(inst) ((inst) + 0x00000010) +#define BF_TXSER_USR_CTL0_INFO(inst) ((inst) + 0x00000010), 0x00000800 + +#define REG_TXSER_12PACK_USR1_ADDR(inst) ((inst) + 0x00000011) +#define BF_TXSER_USR_CTL1_INFO(inst) ((inst) + 0x00000011), 0x00000800 + +#define REG_TXSER_12PACK_USR2_ADDR(inst) ((inst) + 0x00000012) +#define BF_TXSER_USR_CTL2_INFO(inst) ((inst) + 0x00000012), 0x00000800 + +#define REG_TXSER_12PACK_USR3_ADDR(inst) ((inst) + 0x00000013) +#define BF_TXSER_USR_CTL3_INFO(inst) ((inst) + 0x00000013), 0x00000800 + +#define REG_TXSER_12PACK_USR4_ADDR(inst) ((inst) + 0x00000014) +#define BF_TXSER_USR_CTL4_INFO(inst) ((inst) + 0x00000014), 0x00000800 + +#define REG_TXSER_12PACK_USR5_ADDR(inst) ((inst) + 0x00000015) +#define BF_TXSER_USR_CTL5_INFO(inst) ((inst) + 0x00000015), 0x00000800 + +#define REG_TXSER_12PACK_USR6_ADDR(inst) ((inst) + 0x00000016) +#define BF_TXSER_USR_CTL6_INFO(inst) ((inst) + 0x00000016), 0x00000800 + +#define REG_TXSER_12PACK_USR7_ADDR(inst) ((inst) + 0x00000017) +#define BF_TXSER_USR_CTL7_INFO(inst) ((inst) + 0x00000017), 0x00000800 + +#define REG_TXSER_12PACK_USR8_ADDR(inst) ((inst) + 0x00000018) +#define BF_TXSER_USR_CTL8_INFO(inst) ((inst) + 0x00000018), 0x00000800 + +#define REG_TXSER_12PACK_USR9_ADDR(inst) ((inst) + 0x00000019) +#define BF_TXSER_USR_STA0_INFO(inst) ((inst) + 0x00000019), 0x00000800 + +#define REG_TXSER_12PACK_USR10_ADDR(inst) ((inst) + 0x0000001A) +#define BF_TXSER_USR_STA1_INFO(inst) ((inst) + 0x0000001A), 0x00000800 + +#define REG_TXSER_12PACK_REVID_ADDR(inst) ((inst) + 0x000000FF) +#define BF_TXSER_12PACK_REVID_INFO(inst) ((inst) + 0x000000FF), 0x00000800 + +#endif /* __ADI_APOLLO_BF_SERDES_TXDIG_DCC_CORE1P3_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_serdes_txdig_phy_core1p2.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_serdes_txdig_phy_core1p2.h new file mode 100644 index 00000000000000..634c3f999ff7c4 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_serdes_txdig_phy_core1p2.h @@ -0,0 +1,184 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:23 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_SERDES_TXDIG_PHY_CORE1P2_H__ +#define __ADI_APOLLO_BF_SERDES_TXDIG_PHY_CORE1P2_H__ + +/*============= D E F I N E S ==============*/ +#define SER_PHY0_SERDES_TX_JTX_TOP_RX_DIGITAL0 0x60620000 +#define SER_PHY1_SERDES_TX_JTX_TOP_RX_DIGITAL0 0x60620800 +#define SER_PHY2_SERDES_TX_JTX_TOP_RX_DIGITAL0 0x60621000 +#define SER_PHY3_SERDES_TX_JTX_TOP_RX_DIGITAL0 0x60621800 +#define SER_PHY4_SERDES_TX_JTX_TOP_RX_DIGITAL0 0x60622000 +#define SER_PHY5_SERDES_TX_JTX_TOP_RX_DIGITAL0 0x60622800 +#define SER_PHY6_SERDES_TX_JTX_TOP_RX_DIGITAL0 0x60623000 +#define SER_PHY7_SERDES_TX_JTX_TOP_RX_DIGITAL0 0x60623800 +#define SER_PHY8_SERDES_TX_JTX_TOP_RX_DIGITAL0 0x60624000 +#define SER_PHY9_SERDES_TX_JTX_TOP_RX_DIGITAL0 0x60624800 +#define SER_PHY10_SERDES_TX_JTX_TOP_RX_DIGITAL0 0x60625000 +#define SER_PHY11_SERDES_TX_JTX_TOP_RX_DIGITAL0 0x60625800 +#define SER_PHY_ALL_SERDES_TX_JTX_TOP_RX_DIGITAL0 0x60626000 +#define SER_PHY0_SERDES_TX_JTX_TOP_RX_DIGITAL1 0x60E20000 +#define SER_PHY1_SERDES_TX_JTX_TOP_RX_DIGITAL1 0x60E20800 +#define SER_PHY2_SERDES_TX_JTX_TOP_RX_DIGITAL1 0x60E21000 +#define SER_PHY3_SERDES_TX_JTX_TOP_RX_DIGITAL1 0x60E21800 +#define SER_PHY4_SERDES_TX_JTX_TOP_RX_DIGITAL1 0x60E22000 +#define SER_PHY5_SERDES_TX_JTX_TOP_RX_DIGITAL1 0x60E22800 +#define SER_PHY6_SERDES_TX_JTX_TOP_RX_DIGITAL1 0x60E23000 +#define SER_PHY7_SERDES_TX_JTX_TOP_RX_DIGITAL1 0x60E23800 +#define SER_PHY8_SERDES_TX_JTX_TOP_RX_DIGITAL1 0x60E24000 +#define SER_PHY9_SERDES_TX_JTX_TOP_RX_DIGITAL1 0x60E24800 +#define SER_PHY10_SERDES_TX_JTX_TOP_RX_DIGITAL1 0x60E25000 +#define SER_PHY11_SERDES_TX_JTX_TOP_RX_DIGITAL1 0x60E25800 +#define SER_PHY_ALL_SERDES_TX_JTX_TOP_RX_DIGITAL1 0x60E26000 + +#define REG_PWR_DN_ADDR(inst) ((inst) + 0x00000000) +#define BF_PD_SER_INFO(inst) ((inst) + 0x00000000), 0x00000100 + +#define REG_SER_EN_ADDR(inst) ((inst) + 0x00000001) +#define BF_SER_EN_RC_INFO(inst) ((inst) + 0x00000001), 0x00000100 + +#define REG_JTX_SWING_ADDR(inst) ((inst) + 0x00000002) +#define BF_DRVSWING_SER_RC_INFO(inst) ((inst) + 0x00000002), 0x00000300 +#define BF_DRVPOSTEM_SER_RC_INFO(inst) ((inst) + 0x00000002), 0x00000304 + +#define REG_PRE_TAP_LEVEL_ADDR(inst) ((inst) + 0x00000003) +#define BF_DRVPREEM_SER_RC_INFO(inst) ((inst) + 0x00000003), 0x00000800 + +#define REG_GEN_CTL1_ADDR(inst) ((inst) + 0x00000004) +#define BF_RSTB_SER_INFO(inst) ((inst) + 0x00000004), 0x00000100 +#define BF_EN_DRVSLICEOFFSET_SER_RC_INFO(inst) ((inst) + 0x00000004), 0x00000101 +#define BF_DATA_PN_SWAP_CORR_INFO(inst) ((inst) + 0x00000004), 0x00000102 +#define BF_OUTPUTDATAINVERT_SER_RC_INFO(inst) ((inst) + 0x00000004), 0x00000103 +#define BF_PARDATAMODE_SER_RC_INFO(inst) ((inst) + 0x00000004), 0x00000204 +#define BF_LFPATHEN_SER_RC_INFO(inst) ((inst) + 0x00000004), 0x00000106 + +#define REG_PARITY_ERROR_ADDR(inst) ((inst) + 0x00000005) +#define BF_PARITY_ERROR_SER_INFO(inst) ((inst) + 0x00000005), 0x00000100 + +#define REG_PARITY_RST_N_ADDR(inst) ((inst) + 0x00000006) +#define BF_SER_PARITY_RST_N_INFO(inst) ((inst) + 0x00000006), 0x00000100 + +#define REG_CLOCK_CTL_ADDR(inst) ((inst) + 0x00000007) +#define BF_CLKOFFSET_SER_RC_INFO(inst) ((inst) + 0x00000007), 0x00000300 +#define BF_EN_FBCK_SER_RC_INFO(inst) ((inst) + 0x00000007), 0x00000104 +#define BF_FBCKINV_SER_RC_INFO(inst) ((inst) + 0x00000007), 0x00000105 +#define BF_CK66B_INV_SER_RC_INFO(inst) ((inst) + 0x00000007), 0x00000106 + +#define REG_DATA_GEN_CTL_ADDR(inst) ((inst) + 0x00000008) +#define BF_DATA_GEN_MODE_INFO(inst) ((inst) + 0x00000008), 0x00000400 +#define BF_DATA_GEN_EN_INFO(inst) ((inst) + 0x00000008), 0x00000104 + +#define REG_POLY_CODE_ADDR(inst) ((inst) + 0x0000000C) +#define BF_DRVPOLYCODE_SER_RC_INFO(inst) ((inst) + 0x0000000C), 0x00000600 + +#define REG_SYNCA_CTRL_ADDR(inst) ((inst) + 0x0000000D) +#define BF_SYNCA_RX_MODE_RC_INFO(inst) ((inst) + 0x0000000D), 0x00000100 +#define BF_SYNCA_RX_ONCHIP_TERM_RC_INFO(inst) ((inst) + 0x0000000D), 0x00000101 +#define BF_SYNCA_RX_PN_INV_RC_INFO(inst) ((inst) + 0x0000000D), 0x00000102 +#define BF_PD_SYNCA_RX_RC_INFO(inst) ((inst) + 0x0000000D), 0x00000103 + +#define REG_SYNCB_CTRL_ADDR(inst) ((inst) + 0x0000000E) +#define BF_SYNCB_RX_MODE_RC_INFO(inst) ((inst) + 0x0000000E), 0x00000100 +#define BF_SYNCB_RX_ONCHIP_TERM_RC_INFO(inst) ((inst) + 0x0000000E), 0x00000101 +#define BF_SYNCB_RX_PN_INV_RC_INFO(inst) ((inst) + 0x0000000E), 0x00000102 +#define BF_PD_SYNCB_RX_RC_INFO(inst) ((inst) + 0x0000000E), 0x00000103 + +#define REG_JTX_CTRL_ADDR(inst) ((inst) + 0x0000000F) +#define BF_JTAG_EN_SER_TESTMODE_RC_INFO(inst) ((inst) + 0x0000000F), 0x00000100 + +#define REG_DATA_FIR_ADDR(inst) ((inst) + 0x00000010) +#define BF_DATAFIREN_INFO(inst) ((inst) + 0x00000010), 0x00000800 + +#define REG_MAIN_TAP_EN1_ADDR(inst) ((inst) + 0x00000011) +#define BF_MAINTAPEN_INFO(inst) ((inst) + 0x00000011), 0x00001000 + +#define REG_MAIN_TAP_EN2_ADDR(inst) ((inst) + 0x00000012) + +#define REG_MAIN_TAP_MUX1_ADDR(inst) ((inst) + 0x00000013) +#define BF_MAINTAPMUX_INFO(inst) ((inst) + 0x00000013), 0x00001000 + +#define REG_MAIN_TAP_MUX2_ADDR(inst) ((inst) + 0x00000014) + +#define REG_POST_TAP_EN1_ADDR(inst) ((inst) + 0x00000015) +#define BF_POSTTAPEN_INFO(inst) ((inst) + 0x00000015), 0x00000C00 + +#define REG_POST_TAP_EN2_ADDR(inst) ((inst) + 0x00000016) + +#define REG_POST_TAP_MUX1_ADDR(inst) ((inst) + 0x00000017) +#define BF_POSTTAPMUX_INFO(inst) ((inst) + 0x00000017), 0x00000C00 + +#define REG_POST_TAP_MUX2_ADDR(inst) ((inst) + 0x00000018) + +#define REG_PRE_TAP_EN_ADDR(inst) ((inst) + 0x00000019) +#define BF_PRETAPEN_INFO(inst) ((inst) + 0x00000019), 0x00000800 + +#define REG_PRE_TAP_MUX_ADDR(inst) ((inst) + 0x0000001A) +#define BF_PRETAPMUX_INFO(inst) ((inst) + 0x0000001A), 0x00000800 + +#define REG_GEN_CTL2_ADDR(inst) ((inst) + 0x00000020) +#define BF_TAPCTRL_INFO(inst) ((inst) + 0x00000020), 0x00000100 +#define BF_CLKDIV160_EN_INFO(inst) ((inst) + 0x00000020), 0x00000101 +#define BF_CLKDIV8_INV_INFO(inst) ((inst) + 0x00000020), 0x00000102 +#define BF_FIFO_START_ADDR_INFO(inst) ((inst) + 0x00000020), 0x00000304 + +#define REG_SLICE_OFFSET_STA_ADDR(inst) ((inst) + 0x00000021) +#define BF_DRVSLICEENOFFSET_INFO(inst) ((inst) + 0x00000021), 0x00000400 + +#define REG_GEN_CTL3_ADDR(inst) ((inst) + 0x00000023) +#define BF_CLKDIV8_MUX_OUT_INFO(inst) ((inst) + 0x00000023), 0x00000100 + +#define REG_TAP_ERROR_ADDR(inst) ((inst) + 0x00000024) +#define BF_TAPERROR_INFO(inst) ((inst) + 0x00000024), 0x00000100 + +#define REG_SLICE_OFFSET_CTL_ADDR(inst) ((inst) + 0x00000025) +#define BF_SLICEOFFSET_OFFSET_INFO(inst) ((inst) + 0x00000025), 0x00000400 + +#define REG_DATA_FIR_STA_ADDR(inst) ((inst) + 0x00000030) +#define BF_DATAFIREN_STA_INFO(inst) ((inst) + 0x00000030), 0x00000800 + +#define REG_MAIN_TAP_EN_STA1_ADDR(inst) ((inst) + 0x00000031) +#define BF_MAINTAPEN_STA_INFO(inst) ((inst) + 0x00000031), 0x00001000 + +#define REG_MAIN_TAP_EN_STA2_ADDR(inst) ((inst) + 0x00000032) + +#define REG_MAIN_TAP_GEN_STA1_ADDR(inst) ((inst) + 0x00000033) +#define BF_MAINTAPMUX_STA_INFO(inst) ((inst) + 0x00000033), 0x00001000 + +#define REG_MAIN_TAP_GEN_STA2_ADDR(inst) ((inst) + 0x00000034) + +#define REG_POST_TAP_EN_STA1_ADDR(inst) ((inst) + 0x00000035) +#define BF_POSTTAPEN_STA_INFO(inst) ((inst) + 0x00000035), 0x00000C00 + +#define REG_POST_TAP_EN_STA2_ADDR(inst) ((inst) + 0x00000036) + +#define REG_POST_TAP_GEN_STA1_ADDR(inst) ((inst) + 0x00000037) +#define BF_POSTTAPMUX_STA_INFO(inst) ((inst) + 0x00000037), 0x00000C00 + +#define REG_POST_TAP_GEN_STA2_ADDR(inst) ((inst) + 0x00000038) + +#define REG_PRE_TAP_EN_STA_ADDR(inst) ((inst) + 0x00000039) +#define BF_PRETAPEN_STA_INFO(inst) ((inst) + 0x00000039), 0x00000800 + +#define REG_PRE_TAP_GEN_STA2_ADDR(inst) ((inst) + 0x0000003A) +#define BF_PRETAPMUX_STA_INFO(inst) ((inst) + 0x0000003A), 0x00000800 + +#define REG_TX_DIG_REVID_ADDR(inst) ((inst) + 0x0000003E) +#define BF_TX_DIG_REVID_INFO(inst) ((inst) + 0x0000003E), 0x00000800 + +#define REG_TX_REVID_ADDR(inst) ((inst) + 0x0000003F) +#define BF_TX_REVID_INFO(inst) ((inst) + 0x0000003F), 0x00000800 + +#endif /* __ADI_APOLLO_BF_SERDES_TXDIG_PHY_CORE1P2_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_snooper.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_snooper.h new file mode 100644 index 00000000000000..83c0e643b6006d --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_snooper.h @@ -0,0 +1,61 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:17 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_SNOOPER_H__ +#define __ADI_APOLLO_BF_SNOOPER_H__ + +/*============= D E F I N E S ==============*/ +#define REG_SNOOPER_CTRL_ADDR 0x46700000 +#define BF_SNOOPER_ENABLE_SPI0_DIRECT_WR_INFO 0x46700000, 0x00000100 +#define BF_SNOOPER_ENABLE_SPI0_DIRECT_RD_INFO 0x46700000, 0x00000101 +#define BF_SNOOPER_ENABLE_SPI0_PAGED_WR_INFO 0x46700000, 0x00000102 +#define BF_SNOOPER_ENABLE_SPI0_INDIRECT_WR_INFO 0x46700000, 0x00000103 +#define BF_SNOOPER_ENABLE_SPI0_INDIRECT_RD_INFO 0x46700000, 0x00000104 +#define BF_SNOOPER_ENABLE_SPI1_DIRECT_WR_INFO 0x46700000, 0x00000105 +#define BF_SNOOPER_ENABLE_SPI1_DIRECT_RD_INFO 0x46700000, 0x00000106 +#define BF_SNOOPER_ENABLE_SPI1_PAGED_WR_INFO 0x46700000, 0x00000107 +#define BF_SNOOPER_ENABLE_SPI1_INDIRECT_WR_INFO 0x46700000, 0x00000108 +#define BF_SNOOPER_ENABLE_SPI1_INDIRECT_RD_INFO 0x46700000, 0x00000109 +#define BF_SNOOPER_ADDR_DISABLE_INFO 0x46700000, 0x00000810 +#define BF_SNOOPER_ENABLE_INFO 0x46700000, 0x00000119 + +#define REG_SNOOPER_INTERRUPT_EN_ADDR 0x46700004 +#define BF_SNOOPER_STAT_INTR_EN_INFO 0x46700004, 0x00000100 +#define BF_SNOOPER_OVR_INTR_EN_INFO 0x46700004, 0x00000101 + +#define REG_SNOOPER_REGION_START_ADDR(n) (0x46700008 + 4 * (n)) +#define BF_SNOOPER_REGION_START_INFO(n) (0x46700008 + 4 * (n)), 0x00002000 + +#define REG_SNOOPER_REGION_STOP_ADDR(n) (0x4670002C + 4 * (n)) +#define BF_SNOOPER_REGION_STOP_INFO(n) (0x4670002C + 4 * (n)), 0x00002000 + +#define REG_SNOOPED_ADDR_ADDR 0x4670004C +#define BF_ADDRESS_SNOOPED_INFO 0x4670004C, 0x00002000 + +#define REG_SNOOPED_DATA_ADDR 0x46700050 +#define BF_DATA_SNOOPED_INFO 0x46700050, 0x00002000 + +#define REG_SNOOPED_CTRL_ADDR 0x46700054 +#define BF_DIR_SNOOPED_INFO 0x46700054, 0x00000100 +#define BF_MASTER_ID_SNOOPED_INFO 0x46700054, 0x00000301 +#define BF_SIZE_SNOOPED_INFO 0x46700054, 0x00000204 +#define BF_CTRL_REG_REDUNDANT_BIT_FIELDS_INFO 0x46700054, 0x00001A06 + +#define REG_SNOOPER_STATUS_ADDR 0x4670005C +#define BF_SNOOPER_EMPTY_INFO 0x4670005C, 0x00000100 +#define BF_SNOOPER_FULL_INFO 0x4670005C, 0x00000101 +#define BF_SNOOPER_OVERFLOW_INFO 0x4670005C, 0x00000102 + +#endif /* __ADI_APOLLO_BF_SNOOPER_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_spi_master.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_spi_master.h new file mode 100644 index 00000000000000..6f38a6c2afeb99 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_spi_master.h @@ -0,0 +1,139 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:17 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_SPI_MASTER_H__ +#define __ADI_APOLLO_BF_SPI_MASTER_H__ + +/*============= D E F I N E S ==============*/ +#ifdef USE_PRIVATE_BF +#define REG_STAT_SPI_MASTER_ADDR 0x46200000 +#define BF_IRQ_INFO 0x46200000, 0x00000100 +#define BF_XFRDONE_INFO 0x46200000, 0x00000101 +#define BF_TXEMPTY_INFO 0x46200000, 0x00000102 +#define BF_TXDONE_INFO 0x46200000, 0x00000103 +#define BF_TXUNDR_INFO 0x46200000, 0x00000104 +#define BF_TXIRQ_INFO 0x46200000, 0x00000105 +#define BF_RXIRQ_INFO 0x46200000, 0x00000106 +#define BF_RXOVR_INFO 0x46200000, 0x00000107 +#define BF_CS_INFO 0x46200000, 0x0000010B +#define BF_CSERR_INFO 0x46200000, 0x0000010C +#define BF_CSFALL_INFO 0x46200000, 0x0000010D +#define BF_CSRISE_INFO 0x46200000, 0x0000010E +#define BF_RDY_INFO 0x46200000, 0x0000010F +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_RX_ADDR 0x46200004 +#define BF_RX_BYTE1_INFO 0x46200004, 0x00000800 +#define BF_RX_BYTE2_INFO 0x46200004, 0x00000808 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TX_ADDR 0x46200008 +#define BF_TX_BYTE1_INFO 0x46200008, 0x00000800 +#define BF_TX_BYTE2_INFO 0x46200008, 0x00000808 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_DIV_ADDR 0x4620000C +#define BF_DIV_VALUE_INFO 0x4620000C, 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CTL_SPI_MASTER_ADDR 0x46200010 +#define BF_SPIEN_INFO 0x46200010, 0x00000100 +#define BF_MASEN_INFO 0x46200010, 0x00000101 +#define BF_CPHA_INFO 0x46200010, 0x00000102 +#define BF_CPOL_INFO 0x46200010, 0x00000103 +#define BF_WOM_INFO 0x46200010, 0x00000104 +#define BF_LSB_INFO 0x46200010, 0x00000105 +#define BF_TIM_INFO 0x46200010, 0x00000106 +#define BF_ZEN_INFO 0x46200010, 0x00000107 +#define BF_RXOF_INFO 0x46200010, 0x00000108 +#define BF_OEN_INFO 0x46200010, 0x00000109 +#define BF_LOOPBACK_INFO 0x46200010, 0x0000010A +#define BF_CON_INFO 0x46200010, 0x0000010B +#define BF_RFLUSH_INFO 0x46200010, 0x0000010C +#define BF_TFLUSH_INFO 0x46200010, 0x0000010D +#define BF_CSRST_INFO 0x46200010, 0x0000010E +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_IEN_ADDR 0x46200014 +#define BF_IRQMODE_INFO 0x46200014, 0x00000300 +#define BF_CS_INTEN_INFO 0x46200014, 0x00000108 +#define BF_TXUNDR_INTEN_INFO 0x46200014, 0x00000109 +#define BF_RXOVR_INTEN_INFO 0x46200014, 0x0000010A +#define BF_RDY_INTEN_INFO 0x46200014, 0x0000010B +#define BF_TXDONE_INTEN_INFO 0x46200014, 0x0000010C +#define BF_XFRDONE_INTEN_INFO 0x46200014, 0x0000010D +#define BF_TXEMPTY_INTEN_INFO 0x46200014, 0x0000010E +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CNT_ADDR 0x46200018 +#define BF_CNT_VALUE_INFO 0x46200018, 0x00000E00 +#define BF_FRAMECONT_INFO 0x46200018, 0x0000010F +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_DMA_ADDR 0x4620001C +#define BF_EN_SPI_MASTER_INFO 0x4620001C, 0x00000100 +#define BF_TXEN_INFO 0x4620001C, 0x00000101 +#define BF_RXEN_INFO 0x4620001C, 0x00000102 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FIFO_STAT_ADDR 0x46200020 +#define BF_TX_INFO 0x46200020, 0x00000400 +#define BF_RX_INFO 0x46200020, 0x00000408 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_RD_CTL_ADDR 0x46200024 +#define BF_CMDEN_INFO 0x46200024, 0x00000100 +#define BF_OVERLAP_INFO 0x46200024, 0x00000101 +#define BF_TXBYTES_INFO 0x46200024, 0x00000402 +#define BF_THREEPIN_INFO 0x46200024, 0x00000108 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FLOW_CTL_ADDR 0x46200028 +#define BF_MODE_SPI_MASTER_INFO 0x46200028, 0x00000200 +#define BF_RDYPOL_INFO 0x46200028, 0x00000104 +#define BF_RDBURSTSZ_INFO 0x46200028, 0x00000A06 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_WAIT_TMR_ADDR 0x4620002C +#define BF_WAIT_VALUE_INFO 0x4620002C, 0x00001000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CS_CTL_ADDR 0x46200030 +#define BF_SEL_INFO 0x46200030, 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CS_OVERRIDE_ADDR 0x46200034 +#define BF_CTL_INFO 0x46200034, 0x00000200 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_XFR_CNT_ADDR 0x46200038 +#define BF_BYTES_INFO 0x46200038, 0x00000E00 +#endif /* USE_PRIVATE_BF */ + +#endif /* __ADI_APOLLO_BF_SPI_MASTER_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_spi_pm_key.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_spi_pm_key.h new file mode 100644 index 00000000000000..d6dd1ced96b750 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_spi_pm_key.h @@ -0,0 +1,26 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:17 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_SPI_PM_KEY_H__ +#define __ADI_APOLLO_BF_SPI_PM_KEY_H__ + +/*============= D E F I N E S ==============*/ +#define CORE_0_SPI_PM_KEY 0x41100000 +#define DEBUG_KEY_REGS 0x46810100 + +#define REG_KEY_ADDR_ADDR(inst) ((inst) + 0x00000000) +#define BF_PMEM_KEY_INFO(inst) ((inst) + 0x00000000), 0x00002000 + +#endif /* __ADI_APOLLO_BF_SPI_PM_KEY_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_streamproc.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_streamproc.h new file mode 100644 index 00000000000000..91cb83c0f42572 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_streamproc.h @@ -0,0 +1,197 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:17 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_STREAMPROC_H__ +#define __ADI_APOLLO_BF_STREAMPROC_H__ + +/*============= D E F I N E S ==============*/ +#define MAIN_STREAM_PROC 0x46B00000 +#define RX_STREAM_PROC_RX_SLICE_0_RX_DIGITAL0 0x603BB000 +#define RX_STREAM_PROC_RX_SLICE_1_RX_DIGITAL0 0x605BB000 +#define RX_STREAM_PROC_RX_SLICE_0_RX_DIGITAL1 0x60BBB000 +#define RX_STREAM_PROC_RX_SLICE_1_RX_DIGITAL1 0x60DBB000 +#define TX_STREAM_PROC_TX_SLICE_0_TX_DIGITAL0 0x6133C000 +#define TX_STREAM_PROC_TX_SLICE_1_TX_DIGITAL0 0x6153C000 +#define TX_STREAM_PROC_TX_SLICE_0_TX_DIGITAL1 0x61B3C000 +#define TX_STREAM_PROC_TX_SLICE_1_TX_DIGITAL1 0x61D3C000 + +#define REG_SP_TRIGGER_STREAM_ADDR(inst) ((inst) + 0x00000000) +#define BF_STREAM_NUMBER_INFO(inst) ((inst) + 0x00000000), 0x00000800 +#define BF_TRIGGER_STREAM_INFO(inst) ((inst) + 0x00000000), 0x0000011E +#define BF_STREAM_ERROR_STREAMPROC_INFO(inst) ((inst) + 0x00000000), 0x0000011F + +#define REG_SP_DBG_CTL_ADDR(inst) ((inst) + 0x00000004) +#define BF_DBG_EN_STREAMPROC_INFO(inst) ((inst) + 0x00000004), 0x00000100 +#define BF_DBG_MODE_INFO(inst) ((inst) + 0x00000004), 0x00000201 +#define BF_DBG_TRIG_MODE_INFO(inst) ((inst) + 0x00000004), 0x00000304 +#define BF_DBG_IRQ_MASK_INFO(inst) ((inst) + 0x00000004), 0x00000108 +#define BF_DBG_RDBK_MODE_INFO(inst) ((inst) + 0x00000004), 0x00000109 +#define BF_DBG_HALT_RESUME_MASK_INFO(inst) ((inst) + 0x00000004), 0x0000010C + +#define REG_SP_DBG_HALT_CTL_ADDR(inst) ((inst) + 0x00000008) +#define BF_STREAM_HALT_INFO(inst) ((inst) + 0x00000008), 0x00000100 +#define BF_STREAM_RESUME_INFO(inst) ((inst) + 0x00000008), 0x00000101 + +#define REG_SP_DBG_RDBK_CTL_ADDR(inst) ((inst) + 0x0000000C) +#define BF_DBG_RDBK_STICKY_INFO(inst) ((inst) + 0x0000000C), 0x00000100 + +#define REG_SP_BKPT_PC_VAL_ADDR(inst) ((inst) + 0x00000010) +#define BF_BKPT_PC_VAL_INFO(inst) ((inst) + 0x00000010), 0x00001000 + +#define REG_SP_ERRORED_STREAM_NUM_ADDR(inst) ((inst) + 0x00000014) +#define BF_ERRORED_STREAM_NUMBER_INFO(inst) ((inst) + 0x00000014), 0x00000800 + +#define REG_SP_RDBK_BKPT_PC_ADDR(inst) ((inst) + 0x00000018) +#define BF_RDBK_BKPT_PC_INFO(inst) ((inst) + 0x00000018), 0x00001000 + +#define REG_SP_RDBK_CURR_PC_ADDR(inst) ((inst) + 0x0000001C) +#define BF_RDBK_CURR_PC_INFO(inst) ((inst) + 0x0000001C), 0x00001000 + +#define REG_SP_RDBK_INSTR1_INSTR2_ADDR(inst) ((inst) + 0x00000020) +#define BF_RDBK_INSTR1_INFO(inst) ((inst) + 0x00000020), 0x00000800 +#define BF_RDBK_INSTR2_INFO(inst) ((inst) + 0x00000020), 0x00000808 +#define BF_RDBK_DUAL_ISSUE_INFO(inst) ((inst) + 0x00000020), 0x00000110 + +#define REG_SP_RDBK_ERROR_VAL_ADDR(inst) ((inst) + 0x00000024) +#define BF_RDBK_ERROR_VAL_INFO(inst) ((inst) + 0x00000024), 0x00000A00 + +#define REG_SP_RDBK_R0_ADDR(inst) ((inst) + 0x00000028) +#define BF_RDBK_R0_INFO(inst) ((inst) + 0x00000028), 0x00002000 + +#define REG_SP_RDBK_R1_ADDR(inst) ((inst) + 0x0000002C) +#define BF_RDBK_R1_INFO(inst) ((inst) + 0x0000002C), 0x00002000 + +#define REG_SP_RDBK_R2_ADDR(inst) ((inst) + 0x00000030) +#define BF_RDBK_R2_INFO(inst) ((inst) + 0x00000030), 0x00002000 + +#define REG_SP_RDBK_R3_ADDR(inst) ((inst) + 0x00000034) +#define BF_RDBK_R3_INFO(inst) ((inst) + 0x00000034), 0x00002000 + +#define REG_SP_RDBK_R4_ADDR(inst) ((inst) + 0x00000038) +#define BF_RDBK_R4_INFO(inst) ((inst) + 0x00000038), 0x00002000 + +#define REG_SP_RDBK_R5_ADDR(inst) ((inst) + 0x0000003C) +#define BF_RDBK_R5_INFO(inst) ((inst) + 0x0000003C), 0x00002000 + +#define REG_SP_RDBK_R6_ADDR(inst) ((inst) + 0x00000040) +#define BF_RDBK_R6_INFO(inst) ((inst) + 0x00000040), 0x00002000 + +#define REG_SP_RDBK_R7_ADDR(inst) ((inst) + 0x00000044) +#define BF_RDBK_R7_INFO(inst) ((inst) + 0x00000044), 0x00002000 + +#define REG_SP_RDBK_RSEG_ADDR(inst) ((inst) + 0x00000048) +#define BF_RDBK_RSEG_INFO(inst) ((inst) + 0x00000048), 0x00001000 + +#define REG_SP_RDBK_TIMEOUT_COUNT_ADDR(inst) ((inst) + 0x0000004C) +#define BF_TIMEOUT_TIMER_COUNT_INFO(inst) ((inst) + 0x0000004C), 0x00001000 + +#define REG_SP_RDBK_LAST_EXECUTED_STREAM_ADDR(inst) ((inst) + 0x00000050) +#define BF_RDBK_LAST_EXECUTED_STREAM_INFO(inst) ((inst) + 0x00000050), 0x00000800 + +#define REG_SP_AHB_CTL_ADDR(inst) ((inst) + 0x00000054) +#define BF_HRESP_MASK_INFO(inst) ((inst) + 0x00000054), 0x00000100 +#define BF_POSTED_HRESP_MASK_INFO(inst) ((inst) + 0x00000054), 0x00000101 + +#define REG_SP_DCACHE_RD_DATA1_ADDR(inst) ((inst) + 0x00000058) +#define BF_RDBK_DCACHE_RD_DATA1_INFO(inst) ((inst) + 0x00000058), 0x00002000 + +#define REG_SP_DCACHE_RD_DATA2_ADDR(inst) ((inst) + 0x0000005C) +#define BF_RDBK_DCACHE_RD_DATA2_INFO(inst) ((inst) + 0x0000005C), 0x00001000 + +#define REG_SP_PREV_CURR_PC_N_RD_DATA2_ADDR(inst, n) ((inst) + 0x00000060 + 4 * (n)) +#define BF_PREV_CURR_PC_INFO(inst, n) ((inst) + 0x00000060 + 4 * (n)), 0x00001000 +#define BF_PREV_DCACHE_RD_DATA2_INFO(inst, n) ((inst) + 0x00000060 + 4 * (n)), 0x00001010 + +#define REG_SP_PREV_DCACHE_RD_DATA1_ADDR(inst, n) ((inst) + 0x00000070 + 4 * (n)) +#define BF_PREV_DCACHE_RD_DATA1_INFO(inst, n) ((inst) + 0x00000070 + 4 * (n)), 0x00002000 + +#define REG_SP_PREV_INSTR1_INSTR2_ADDR(inst, n) ((inst) + 0x00000080 + 4 * (n)) +#define BF_PREV_INSTR1_INFO(inst, n) ((inst) + 0x00000080 + 4 * (n)), 0x00000800 +#define BF_PREV_INSTR2_INFO(inst, n) ((inst) + 0x00000080 + 4 * (n)), 0x00000808 +#define BF_PREV_DUAL_ISSUE_INFO(inst, n) ((inst) + 0x00000080 + 4 * (n)), 0x00000110 + +#define REG_SP_PREV_R0_ADDR(inst, n) ((inst) + 0x00000090 + 4 * (n)) +#define BF_PREV_R0_INFO(inst, n) ((inst) + 0x00000090 + 4 * (n)), 0x00002000 + +#define REG_SP_PREV_R1_ADDR(inst, n) ((inst) + 0x000000A0 + 4 * (n)) +#define BF_PREV_R1_INFO(inst, n) ((inst) + 0x000000A0 + 4 * (n)), 0x00002000 + +#define REG_SP_PREV_R2_ADDR(inst, n) ((inst) + 0x000000B0 + 4 * (n)) +#define BF_PREV_R2_INFO(inst, n) ((inst) + 0x000000B0 + 4 * (n)), 0x00002000 + +#define REG_SP_PREV_R3_ADDR(inst, n) ((inst) + 0x000000C0 + 4 * (n)) +#define BF_PREV_R3_INFO(inst, n) ((inst) + 0x000000C0 + 4 * (n)), 0x00002000 + +#define REG_SP_PREV_R4_ADDR(inst, n) ((inst) + 0x000000D0 + 4 * (n)) +#define BF_PREV_R4_INFO(inst, n) ((inst) + 0x000000D0 + 4 * (n)), 0x00002000 + +#define REG_SP_PREV_R5_ADDR(inst, n) ((inst) + 0x000000E0 + 4 * (n)) +#define BF_PREV_R5_INFO(inst, n) ((inst) + 0x000000E0 + 4 * (n)), 0x00002000 + +#define REG_SP_PREV_R6_ADDR(inst, n) ((inst) + 0x000000F0 + 4 * (n)) +#define BF_PREV_R6_INFO(inst, n) ((inst) + 0x000000F0 + 4 * (n)), 0x00002000 + +#define REG_SP_PREV_R7_ADDR(inst, n) ((inst) + 0x00000100 + 4 * (n)) +#define BF_PREV_R7_INFO(inst, n) ((inst) + 0x00000100 + 4 * (n)), 0x00002000 + +#define REG_SP_PREV_RSEG_N_TIMEOUT_VAL_ADDR(inst, n) ((inst) + 0x00000110 + 4 * (n)) +#define BF_PREV_RSEG_INFO(inst, n) ((inst) + 0x00000110 + 4 * (n)), 0x00001000 +#define BF_PREV_TIMEOUT_TIMER_COUNT_INFO(inst, n) ((inst) + 0x00000110 + 4 * (n)), 0x00001010 + +#define REG_SP_TIMER_EVENT_STATUS_ADDR(inst) ((inst) + 0x00000120) +#define BF_EXTERNAL_TIMER_STATUS_INFO(inst) ((inst) + 0x00000120), 0x00000800 +#define BF_FIFO_EVENTS_PENDING_INFO(inst) ((inst) + 0x00000120), 0x00000808 + +#define REG_SP_AHB_FETCH_ADDR_ADDR(inst) ((inst) + 0x00000124) +#define BF_AHB_FETCH_ADDR_INFO(inst) ((inst) + 0x00000124), 0x00002000 + +#define REG_SP_REGBUS_ADDR_ADDR(inst) ((inst) + 0x00000128) +#define BF_REGBUS_ADDR_INFO(inst) ((inst) + 0x00000128), 0x00002000 + +#define REG_SP_REGBUS_SIZE_ADDR(inst) ((inst) + 0x0000012C) +#define BF_REGBUS_SIZE_INFO(inst) ((inst) + 0x0000012C), 0x00000100 + +#define REG_SP_PREV_TIMER_EVENT_STATUS_ADDR(inst, n) ((inst) + 0x00000130 + 4 * (n)) +#define BF_PREV_EXTERNAL_TIMER_STATUS_INFO(inst, n) ((inst) + 0x00000130 + 4 * (n)), 0x00000800 +#define BF_PREV_FIFO_EVENTS_PENDING_INFO(inst, n) ((inst) + 0x00000130 + 4 * (n)), 0x00000808 + +#define REG_SP_PREV_AHB_FETCH_ADDR_ADDR(inst, n) ((inst) + 0x00000140 + 4 * (n)) +#define BF_PREV_AHB_FETCH_ADDR_INFO(inst, n) ((inst) + 0x00000140 + 4 * (n)), 0x00002000 + +#define REG_SP_PREV_REGBUS_ADDR_ADDR(inst, n) ((inst) + 0x00000150 + 4 * (n)) +#define BF_PREV_REGBUS_ADDR_INFO(inst, n) ((inst) + 0x00000150 + 4 * (n)), 0x00002000 + +#define REG_SP_PREV_REGBUS_SIZE_ADDR(inst, n) ((inst) + 0x00000160 + 4 * (n)) +#define BF_PREV_REGBUS_SIZE_INFO(inst, n) ((inst) + 0x00000160 + 4 * (n)), 0x00000100 + +#define REG_SP_EVENT_MISS_ADDR(inst) ((inst) + 0x00000170) +#define BF_EVENT_MISS_IRQ_MASK_INFO(inst) ((inst) + 0x00000170), 0x00000100 + +#define REG_SP_EVENT_MISS_STATUS0_ADDR(inst) ((inst) + 0x00000174) +#define BF_EVENT_MISS0_INFO(inst) ((inst) + 0x00000174), 0x00002000 + +#define REG_SP_EVENT_MISS_STATUS1_ADDR(inst) ((inst) + 0x00000178) +#define BF_EVENT_MISS1_INFO(inst) ((inst) + 0x00000178), 0x00002000 + +#define REG_SP_EVENT_MISS_STATUS2_ADDR(inst) ((inst) + 0x0000017C) +#define BF_EVENT_MISS2_INFO(inst) ((inst) + 0x0000017C), 0x00002000 + +#define REG_SP_EVENT_MISS_STATUS3_ADDR(inst) ((inst) + 0x00000180) +#define BF_EVENT_MISS3_INFO(inst) ((inst) + 0x00000180), 0x00002000 + +#define REG_SP_CALL_FUNC_TRACE_ADDR(inst) ((inst) + 0x00000184) +#define BF_CALL_FUNC_TRACE_INFO(inst) ((inst) + 0x00000184), 0x00000100 + +#endif /* __ADI_APOLLO_BF_STREAMPROC_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_streamproc_channel.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_streamproc_channel.h new file mode 100644 index 00000000000000..24d1d4a87825eb --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_streamproc_channel.h @@ -0,0 +1,77 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:23 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_STREAMPROC_CHANNEL_H__ +#define __ADI_APOLLO_BF_STREAMPROC_CHANNEL_H__ + +/*============= D E F I N E S ==============*/ +#define RX_STREAM_PROC_CHANNEL_RX_SLICE_0_RX_DIGITAL0 0x603BC000 +#define RX_STREAM_PROC_CHANNEL_RX_SLICE_1_RX_DIGITAL0 0x605BC000 +#define RX_STREAM_PROC_CHANNEL_RX_SLICE_0_RX_DIGITAL1 0x60BBC000 +#define RX_STREAM_PROC_CHANNEL_RX_SLICE_1_RX_DIGITAL1 0x60DBC000 +#define TX_STREAM_PROC_CHANNEL_TX_SLICE_0_TX_DIGITAL0 0x6133D000 +#define TX_STREAM_PROC_CHANNEL_TX_SLICE_1_TX_DIGITAL0 0x6153D000 +#define TX_STREAM_PROC_CHANNEL_TX_SLICE_0_TX_DIGITAL1 0x61B3D000 +#define TX_STREAM_PROC_CHANNEL_TX_SLICE_1_TX_DIGITAL1 0x61D3D000 + +#ifdef USE_PRIVATE_BF +#define REG_STREAM_CONFIG_0_ADDR(inst) ((inst) + 0x00000000) +#define BF_STREAM_ECC_ERROR_CLEAR_INFO(inst) ((inst) + 0x00000000), 0x00000100 +#define BF_CH_RISE_STREAM_ERROR_INFO(inst) ((inst) + 0x00000000), 0x00000104 +#define BF_STREAM_ECC_ERROR_SENSITIVITY_INFO(inst) ((inst) + 0x00000000), 0x00000108 +#define BF_STREAM_PROC_ADDR_STREAMPROC_CHANNEL_INFO(inst) ((inst) + 0x00000000), 0x0000040C +#define BF_STREAM_RESET_STREAMPROC_CHANNEL_INFO(inst) ((inst) + 0x00000000), 0x00000110 +#define BF_RUN_STREAM_NUM_INFO(inst) ((inst) + 0x00000000), 0x00000818 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_STREAM_CONFIG_1_ADDR(inst) ((inst) + 0x00000004) +#define BF_STREAM_BASE_STREAMPROC_CHANNEL_INFO(inst) ((inst) + 0x00000004), 0x00001000 +#define BF_LAST_STREAM_NUM_STREAMPROC_CHANNEL_INFO(inst) ((inst) + 0x00000004), 0x00000810 +#define BF_MASK_CH_RISE_STREAM_TO_CORE_INFO(inst) ((inst) + 0x00000004), 0x00000118 +#define BF_STREAM_PROC_RDEN_STREAMPROC_CHANNEL_INFO(inst) ((inst) + 0x00000004), 0x0000011C +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_STREAM_CONFIG_2_ADDR(inst) ((inst) + 0x00000008) +#define BF_COMPLETED_STREAM_NUM_STREAMPROC_CHANNEL_INFO(inst) ((inst) + 0x00000008), 0x00000800 +#define BF_CH_FALL_STREAM_ERROR_INFO(inst) ((inst) + 0x00000008), 0x00000108 +#define BF_STREAM_ECC_ENABLE_INFO(inst) ((inst) + 0x00000008), 0x0000010C +#define BF_STREAM_ECC_ERROR_INFO(inst) ((inst) + 0x00000008), 0x00000110 +#define BF_CH_ENABLE_READBACK_INFO(inst) ((inst) + 0x00000008), 0x00000114 +#define BF_MASK_CH_FALL_STREAM_TO_CORE_INFO(inst) ((inst) + 0x00000008), 0x00000118 +#define BF_STREAM_ERROR_STREAMPROC_CHANNEL_INFO(inst) ((inst) + 0x00000008), 0x0000011C +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_STREAM_CONFIG_3_ADDR(inst) ((inst) + 0x0000000C) +#define BF_STREAM_ECC_ERROR_TAG_INFO(inst) ((inst) + 0x0000000C), 0x00000C00 +#define BF_MASK_CH_ANT_RISE_STREAM_TO_CORE_INFO(inst) ((inst) + 0x0000000C), 0x0000010C +#define BF_MASK_CH_ANT_FALL_STREAM_TO_CORE_INFO(inst) ((inst) + 0x0000000C), 0x00000110 +#define BF_CH_ENABLE_PIN_INVERT_INFO(inst) ((inst) + 0x0000000C), 0x00000114 +#define BF_CH_ANT_ENABLE_PIN_INVERT_INFO(inst) ((inst) + 0x0000000C), 0x00000118 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_STREAM_PROC_READBACK_DATA_ADDR(inst) ((inst) + 0x00000010) +#define BF_STREAM_PROC_DATA_STREAMPROC_CHANNEL_INFO(inst) ((inst) + 0x00000010), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_STREAM_PROC_SCRATCH_ADDR(inst, n) ((inst) + 0x00000014 + 4 * (n)) +#define BF_STREAM_SCRATCH_INFO(inst, n) ((inst) + 0x00000014 + 4 * (n)), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#endif /* __ADI_APOLLO_BF_STREAMPROC_CHANNEL_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_telemetry.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_telemetry.h new file mode 100644 index 00000000000000..ea0a7d50b8aed1 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_telemetry.h @@ -0,0 +1,110 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:17 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_TELEMETRY_H__ +#define __ADI_APOLLO_BF_TELEMETRY_H__ + +/*============= D E F I N E S ==============*/ +#define REG_TELEMETRY_CTRL_ADDR 0x46400000 +#define BF_TELEMETRY_MODES_INFO 0x46400000, 0x00000200 +#define BF_TELEMETRY_ENABLE_INFO 0x46400000, 0x00000108 + +#define REG_TELEMETRY_SOURCE_FILTER0_ADDR 0x46400004 +#define BF_TELEMETRY_RX_FILTER_INFO 0x46400004, 0x00000800 + +#define REG_TELEMETRY_SOURCE_FILTER1_ADDR 0x46400008 +#define BF_TELEMETRY_TX_FILTER_INFO 0x46400008, 0x00000800 + +#define REG_TELEMETRY_SOURCE_FILTER2_ADDR 0x4640000C +#define BF_TELEMETRY_ORX_FILTER_INFO 0x4640000C, 0x00000200 + +#define REG_TELEMETRY_SOURCE_FILTER3_ADDR 0x46400010 +#define BF_TELEMETRY_RESTOFALL_FILTER_INFO 0x46400010, 0x00000500 +#define BF_TELEMETRY_INVALID_DATA_FILTER_INFO 0x46400010, 0x00000105 +#define BF_TELEMETRY_KFA_MPU_START_FILTER_INFO 0x46400010, 0x00000806 +#define BF_TELEMETRY_KFA_MPU_DONE_FILTER_INFO 0x46400010, 0x0000080E +#define BF_TELEMETRY_KFA_STREAM_FILTER_INFO 0x46400010, 0x00000116 + +#define REG_TELEMETRY_EVENT_FILTER0_ADDR 0x46400014 +#define BF_TELEMETRY_RX_EVENT_FILTER_INFO 0x46400014, 0x00000300 + +#define REG_TELEMETRY_EVENT_FILTER1_ADDR 0x46400018 +#define BF_TELEMETRY_TX_EVENT_FILTER_INFO 0x46400018, 0x00000300 + +#define REG_TELEMETRY_EVENT_FILTER2_ADDR 0x4640001C +#define BF_TELEMETRY_ORX_EVENT_FILTER_INFO 0x4640001C, 0x00000300 + +#define REG_TELEMETRY_EVENT_FILTER3_ADDR 0x46400020 +#define BF_TELEMETRY_CORE_EVENT_FILTER_INFO 0x46400020, 0x00000800 + +#define REG_TELEMETRY_TS_MASK_ADDR 0x46400024 +#define BF_TELEMETRY_TS_MASK_BITS_INFO 0x46400024, 0x00000300 + +#define REG_TELEMETRY_CORE0_WRDATA_ADDR 0x46400028 +#define BF_TELEMETRY_CORE0_WRDATA_INFO 0x46400028, 0x00002000 + +#define REG_TELEMETRY_CORE1_WRDATA_ADDR 0x4640002C +#define BF_TELEMETRY_CORE1_WRDATA_INFO 0x4640002C, 0x00002000 + +#define REG_TELEMETRY_STREAMPROC_WRDATA_ADDR 0x46400030 +#define BF_TELEMETRY_STREAMPROC_WRDATA_INFO 0x46400030, 0x00002000 + +#define REG_TELEMETRY_CORE0_WRDATA_WO_TS_ADDR 0x46400034 +#define BF_TELEMETRY_CORE0_WRDATA_WO_TS_INFO 0x46400034, 0x00002000 + +#define REG_TELEMETRY_CORE1_WRDATA_WO_TS_ADDR 0x46400038 +#define BF_TELEMETRY_CORE1_WRDATA_WO_TS_INFO 0x46400038, 0x00002000 + +#define REG_TELEMETRY_STREAMPROC_WRDATA_WO_TS_ADDR 0x4640003C +#define BF_TELEMETRY_STREAMPROC_WRDATA_WO_TS_INFO 0x4640003C, 0x00002000 + +#define REG_TELEMETRY_STREAM_OVERFLOW_STATUS_WO_SEQFIFO_REG_ADDR 0x46400040 +#define BF_TELEMETRY_STREAM_OVR_BITS_WITH_NO_SEQFIFO_OVR_INFO 0x46400040, 0x00001300 + +#define REG_TELEMETRY_PROC_WR_OVERFLOW_STATUS_WO_SEQFIFO_REG_ADDR 0x46400044 +#define BF_TELEMETRY_PROC_WR_OVR_BITS_WITH_NO_SEQFIFO_OVR_INFO 0x46400044, 0x00000600 + +#define REG_TELEMETRY_KFA_OVERFLOW_STATUS_WO_SEQFIFO_REG_ADDR 0x46400048 +#define BF_TELEMETRY_KFA_OVR_BITS_WITH_NO_SEQFIFO_OVR_INFO 0x46400048, 0x00000900 + +#define REG_TELEMETRY_STREAM_OVERFLOW_STATUS_WITH_SEQFIFO_REG_ADDR 0x4640004C +#define BF_TELEMETRY_STREAM_OVR_BITS_WITH_SEQFIFO_OVR_INFO 0x4640004C, 0x00001300 + +#define REG_TELEMETRY_PROC_WR_OVERFLOW_STATUS_WITH_SEQFIFO_REG_ADDR 0x46400050 +#define BF_TELEMETRY_PROC_WR_OVR_BITS_WITH_SEQFIFO_OVR_INFO 0x46400050, 0x00000600 + +#define REG_TELEMETRY_KFA_OVERFLOW_STATUS_WITH_SEQFIFO_REG_ADDR 0x46400054 +#define BF_TELEMETRY_KFA_OVR_BITS_WITH_SEQFIFO_OVR_INFO 0x46400054, 0x00000900 + +#define REG_TELEMETRY_OVERFLOW_INTERRUPT_ENABLE_ADDR 0x46400058 +#define BF_TELEMETRY_INTR_ENABLE_BITS_INFO 0x46400058, 0x00000300 +#define BF_TELEMETRY_INTR_ENABLE_FOR_SEQFIFO_BIT_INFO 0x46400058, 0x00000303 + +#define REG_TELEMETRY_MEM_FIFO_INTR_EN_ADDR 0x4640005C +#define BF_TELEMETRY_MEM_OV_INTR_EN_INFO 0x4640005C, 0x00000100 +#define BF_TELEMETRY_MEM_FIFO_WATERMARK_INTR_EN_INFO 0x4640005C, 0x00000101 + +#define REG_TELEMETRY_MEM_FIFO_WATERMARK_ADDR 0x46400060 +#define BF_TELEMETRY_MEM_FIFO_WATERMARK_INFO 0x46400060, 0x00000E00 + +#define REG_TELEMETRY_MEM_FIFO_STATUS_ADDR 0x46400064 +#define BF_TELEMETRY_MEM_FIFO_EMPTY_INFO 0x46400064, 0x00000100 +#define BF_TELEMETRY_MEM_FIFO_OVERFLOW_INFO 0x46400064, 0x00000101 +#define BF_TELEMETRY_MEM_FIFO_COUNT_INFO 0x46400064, 0x00000E02 + +#define REG_TELEMETRY_MEM_DIRECT_ACCESS_ADDR 0x46400068 +#define BF_TELEMETRY_MEM_DIRECT_ACCESS_INFO 0x46400068, 0x00000100 + +#endif /* __ADI_APOLLO_BF_TELEMETRY_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_timer.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_timer.h new file mode 100644 index 00000000000000..9fbded9a40de32 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_timer.h @@ -0,0 +1,63 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:16 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_TIMER_H__ +#define __ADI_APOLLO_BF_TIMER_H__ + +/*============= D E F I N E S ==============*/ +#define CORE_0_TIMER0 0x40000000 +#define CORE_0_TIMER1 0x40010000 +#define CORE_0_TIMER2 0x40020000 +#define CORE_0_TIMER3 0x40030000 +#define CORE_0_TIMER4 0x40040000 +#define CORE_0_TIMER5 0x40050000 +#define CORE_0_TIMER6 0x40060000 +#define CORE_0_TIMER7 0x40070000 +#define CORE_0_TIMER8 0x40080000 +#define CORE_0_TIMER9 0x40090000 +#define CORE_0_TIMER10 0x400A0000 +#define CORE_0_TIMER11 0x400B0000 +#define CORE_0_TIMER12 0x400C0000 +#define CORE_0_TIMER13 0x400D0000 +#define CORE_0_TIMER14 0x400E0000 +#define CORE_0_TIMER15 0x400F0000 + +#define REG_LOAD_ADDR(inst) ((inst) + 0x00000000) +#define BF_LOAD_VAL_INFO(inst) ((inst) + 0x00000000), 0x00002000 + +#define REG_VALS_ADDR(inst) ((inst) + 0x00000004) +#define BF_TIMER_READ_VAL_INFO(inst) ((inst) + 0x00000004), 0x00002000 + +#define REG_CON_ADDR(inst) ((inst) + 0x00000008) +#define BF_PRESCALE_INFO(inst) ((inst) + 0x00000008), 0x00000200 +#define BF_UP_INFO(inst) ((inst) + 0x00000008), 0x00000102 +#define BF_MODE_TIMER_INFO(inst) ((inst) + 0x00000008), 0x00000103 +#define BF_ENABLE_INFO(inst) ((inst) + 0x00000008), 0x00000104 +#define BF_CLKSEL_INFO(inst) ((inst) + 0x00000008), 0x00000205 +#define BF_RLD_INFO(inst) ((inst) + 0x00000008), 0x00000107 +#define BF_EVENT_SEL_INFO(inst) ((inst) + 0x00000008), 0x00000408 +#define BF_EVENT_EN_INFO(inst) ((inst) + 0x00000008), 0x0000010C + +#define REG_CLRI_ADDR(inst) ((inst) + 0x0000000C) +#define BF_CLEAR_TIMER_VAL_INFO(inst) ((inst) + 0x0000000C), 0x00000100 +#define BF_CLEAR_TIMEOUT_INTERRUPT_INFO(inst) ((inst) + 0x0000000C), 0x00000101 + +#define REG_CAPTURE_ADDR(inst) ((inst) + 0x00000010) +#define BF_TIMER_CAPTURE_VAL_INFO(inst) ((inst) + 0x00000010), 0x00002000 + +#define REG_STATUS_TIMER_ADDR(inst) ((inst) + 0x00000014) +#define BF_TIMEOUT_INFO(inst) ((inst) + 0x00000014), 0x00000100 + +#endif /* __ADI_APOLLO_BF_TIMER_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_tx_bist.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_tx_bist.h new file mode 100644 index 00000000000000..6b4bccdf5d0794 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_tx_bist.h @@ -0,0 +1,39 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:24 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_TX_BIST_H__ +#define __ADI_APOLLO_BF_TX_BIST_H__ + +/*============= D E F I N E S ==============*/ +#define TX_BIST0_TX_SLICE_0_TX_DIGITAL0 0x61206000 +#define TX_BIST1_TX_SLICE_0_TX_DIGITAL0 0x61207000 +#define TX_BIST0_TX_SLICE_1_TX_DIGITAL0 0x61406000 +#define TX_BIST1_TX_SLICE_1_TX_DIGITAL0 0x61407000 +#define TX_BIST0_TX_SLICE_0_TX_DIGITAL1 0x61A06000 +#define TX_BIST1_TX_SLICE_0_TX_DIGITAL1 0x61A07000 +#define TX_BIST0_TX_SLICE_1_TX_DIGITAL1 0x61C06000 +#define TX_BIST1_TX_SLICE_1_TX_DIGITAL1 0x61C07000 + +#ifdef USE_PRIVATE_BF +#define REG_BIST_CFG_ADDR(inst) ((inst) + 0x00000000) +#define BF_BIST_EN_TX_BIST_INFO(inst) ((inst) + 0x00000000), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_BIST_SIGNA0_ADDR(inst) ((inst) + 0x00000023) +#define BF_BIST_STATUS_INFO(inst) ((inst) + 0x00000023), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#endif /* __ADI_APOLLO_BF_TX_BIST_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_tx_bist_test.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_tx_bist_test.h new file mode 100644 index 00000000000000..d6814fc99b8103 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_tx_bist_test.h @@ -0,0 +1,125 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:24 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_TX_BIST_TEST_H__ +#define __ADI_APOLLO_BF_TX_BIST_TEST_H__ + +/*============= D E F I N E S ==============*/ +#define TX_BIST_TEST_HSDOUT0_TX_SLICE_0_TX_DIGITAL0 0x6120C000 +#define TX_BIST_TEST_HSDOUT1_TX_SLICE_0_TX_DIGITAL0 0x6120C040 +#define TX_BIST_TEST_LINEARX_TX_SLICE_0_TX_DIGITAL0 0x6123C080 +#define TX_BIST_TEST_PFILT_TX_SLICE_0_TX_DIGITAL0 0x61305040 +#define TX_BIST_TEST_FDUC_TX_SLICE_0_TX_DIGITAL0 0x6130D000 +#define TX_BIST_TEST_FSRC_CFIR_TX_SLICE_0_TX_DIGITAL0 0x61316040 +#define TX_BIST_TEST_CDUC_TX_SLICE_0_TX_DIGITAL0 0x6133B000 +#define TX_BIST_TEST_HSDOUT0_TX_SLICE_1_TX_DIGITAL0 0x6140C000 +#define TX_BIST_TEST_HSDOUT1_TX_SLICE_1_TX_DIGITAL0 0x6140C040 +#define TX_BIST_TEST_LINEARX_TX_SLICE_1_TX_DIGITAL0 0x6143C080 +#define TX_BIST_TEST_PFILT_TX_SLICE_1_TX_DIGITAL0 0x61505040 +#define TX_BIST_TEST_FDUC_TX_SLICE_1_TX_DIGITAL0 0x6150D000 +#define TX_BIST_TEST_FSRC_CFIR_TX_SLICE_1_TX_DIGITAL0 0x61516040 +#define TX_BIST_TEST_CDUC_TX_SLICE_1_TX_DIGITAL0 0x6153B000 +#define TX_BIST_TEST_HSDOUT0_TX_SLICE_0_TX_DIGITAL1 0x61A0C000 +#define TX_BIST_TEST_HSDOUT1_TX_SLICE_0_TX_DIGITAL1 0x61A0C040 +#define TX_BIST_TEST_LINEARX_TX_SLICE_0_TX_DIGITAL1 0x61A3C080 +#define TX_BIST_TEST_PFILT_TX_SLICE_0_TX_DIGITAL1 0x61B05040 +#define TX_BIST_TEST_FDUC_TX_SLICE_0_TX_DIGITAL1 0x61B0D000 +#define TX_BIST_TEST_FSRC_CFIR_TX_SLICE_0_TX_DIGITAL1 0x61B16040 +#define TX_BIST_TEST_CDUC_TX_SLICE_0_TX_DIGITAL1 0x61B3B000 +#define TX_BIST_TEST_HSDOUT0_TX_SLICE_1_TX_DIGITAL1 0x61C0C000 +#define TX_BIST_TEST_HSDOUT1_TX_SLICE_1_TX_DIGITAL1 0x61C0C040 +#define TX_BIST_TEST_LINEARX_TX_SLICE_1_TX_DIGITAL1 0x61C3C080 +#define TX_BIST_TEST_PFILT_TX_SLICE_1_TX_DIGITAL1 0x61D05040 +#define TX_BIST_TEST_FDUC_TX_SLICE_1_TX_DIGITAL1 0x61D0D000 +#define TX_BIST_TEST_FSRC_CFIR_TX_SLICE_1_TX_DIGITAL1 0x61D16040 +#define TX_BIST_TEST_CDUC_TX_SLICE_1_TX_DIGITAL1 0x61D3B000 + +#define REG_TX_BIST_CTRL_ADDR(inst) ((inst) + 0x00000000) +#ifdef USE_PRIVATE_BF +#define BF_TX_BIST_ENABLE_INFO(inst) ((inst) + 0x00000000), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#ifdef USE_PRIVATE_BF +#define BF_TX_BIST_FLUSH_LEN_INFO(inst) ((inst) + 0x00000000), 0x00000201 +#endif /* USE_PRIVATE_BF */ +#ifdef USE_PRIVATE_BF +#define BF_TX_BIST_ZERO_NOT_SENSITIVE_INFO(inst) ((inst) + 0x00000000), 0x00000103 +#endif /* USE_PRIVATE_BF */ +#ifdef USE_PRIVATE_BF +#define BF_TX_BIST_DAC_START_INFO(inst) ((inst) + 0x00000000), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_TX_BIST_HOLD_NCO_INFO(inst) ((inst) + 0x00000000), 0x00000105 + +#ifdef USE_PRIVATE_BF +#define REG_TX_BIST_STATUS_ADDR(inst) ((inst) + 0x00000001) +#define BF_TX_BIST_CLR_INFO(inst) ((inst) + 0x00000001), 0x00000100 +#define BF_TX_BIST_RUN_INFO(inst) ((inst) + 0x00000001), 0x00000101 +#define BF_TX_BIST_DONE_INFO(inst) ((inst) + 0x00000001), 0x00000102 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TX_BIST_LEN_LSB_ADDR(inst) ((inst) + 0x00000002) +#define BF_TX_BIST_LENGTH_INFO(inst) ((inst) + 0x00000002), 0x00001300 +#endif /* USE_PRIVATE_BF */ + +#define REG_TX_BIST_LEN_MID_ADDR(inst) ((inst) + 0x00000003) + +#define REG_TX_BIST_LEN_MSB_ADDR(inst) ((inst) + 0x00000004) + +#ifdef USE_PRIVATE_BF +#define REG_TX_BIST_READ_CTRL_ADDR(inst) ((inst) + 0x00000005) +#define BF_TX_BIST_SIGN_RD_MODE_INFO(inst) ((inst) + 0x00000005), 0x00000100 +#define BF_TX_BIST_SIGN_RD_SEL_INFO(inst) ((inst) + 0x00000005), 0x00000501 +#define BF_TX_BIST_SIGN_RD_CLR_INFO(inst) ((inst) + 0x00000005), 0x00000106 +#define BF_TX_BIST_SIGN_RD_EN_INFO(inst) ((inst) + 0x00000005), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TX_BIST_SIGN_LSB_ADDR(inst) ((inst) + 0x00000006) +#define BF_TX_BIST_SIGNATURE_INFO(inst) ((inst) + 0x00000006), 0x00001800 +#endif /* USE_PRIVATE_BF */ + +#define REG_TX_BIST_SIGN_MID_ADDR(inst) ((inst) + 0x00000007) + +#define REG_TX_BIST_SIGN_MSB_ADDR(inst) ((inst) + 0x00000008) + +#ifdef USE_PRIVATE_BF +#define REG_TX_BIST_GLOBAL_STATUS_ADDR(inst) ((inst) + 0x00000009) +#define BF_TX_G_BIST_ENABLE_INFO(inst) ((inst) + 0x00000009), 0x00000100 +#define BF_TX_G_BIST_MODE_INFO(inst) ((inst) + 0x00000009), 0x00000101 +#define BF_TX_G_BIST_CLR_INFO(inst) ((inst) + 0x00000009), 0x00000102 +#define BF_TX_G_BIST_RUN_INFO(inst) ((inst) + 0x00000009), 0x00000103 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TX_BIST_LB0_CTRL_ADDR(inst, n) ((inst) + 0x0000000A + 1 * (n)) +#define BF_TX_LPBK_ADC_BIST_MODE_SEL_INFO(inst, n) ((inst) + 0x0000000A + 1 * (n)), 0x00000100 +#define BF_TX_LPBK_ADC_BIST_INVERT_INFO(inst, n) ((inst) + 0x0000000A + 1 * (n)), 0x00000101 +#define BF_TX_LPBK_ADC_BIST_ENABLE_INFO(inst, n) ((inst) + 0x0000000A + 1 * (n)), 0x00000102 +#define BF_TX_LPBK_ADC_BIST_START_INFO(inst, n) ((inst) + 0x0000000A + 1 * (n)), 0x00000103 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TX_BIST_LB0_STATUS_ADDR(inst, n) ((inst) + 0x0000000E + 1 * (n)) +#define BF_TX_LPBK_ADC_BIST_DONE_INFO(inst, n) ((inst) + 0x0000000E + 1 * (n)), 0x00000100 +#define BF_TX_LPBK_ADC_BIST_PASS_INFO(inst, n) ((inst) + 0x0000000E + 1 * (n)), 0x00000101 +#define BF_TX_LPBK_ADC_BIST_FAIL_INFO(inst, n) ((inst) + 0x0000000E + 1 * (n)), 0x00000102 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TX_BIST_LB0_ERROR_ADDR(inst, n) ((inst) + 0x00000012 + 1 * (n)) +#define BF_TX_LPBK_ADC_BIST_ERRORS_INFO(inst, n) ((inst) + 0x00000012 + 1 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#endif /* __ADI_APOLLO_BF_TX_BIST_TEST_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_tx_cduc.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_tx_cduc.h new file mode 100644 index 00000000000000..a70be6878fa37d --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_tx_cduc.h @@ -0,0 +1,81 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:25 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_TX_CDUC_H__ +#define __ADI_APOLLO_BF_TX_CDUC_H__ + +/*============= D E F I N E S ==============*/ +#define TX_CDUC_TX_SLICE_0_TX_DIGITAL0 0x61330000 +#define TX_CDUC_TX_SLICE_1_TX_DIGITAL0 0x61530000 +#define TX_CDUC_TX_SLICE_0_TX_DIGITAL1 0x61B30000 +#define TX_CDUC_TX_SLICE_1_TX_DIGITAL1 0x61D30000 + +#define REG_CDUC_DP_CFG0_ADDR(inst) ((inst) + 0x000001D0) +#define BF_POST_INTERP_INFO(inst) ((inst) + 0x000001D0), 0x00000400 + +#define REG_CDUC_DP_CFG1_ADDR(inst) ((inst) + 0x000001D1) +#define BF_CHB1_INT_TIME_DLY_INFO(inst) ((inst) + 0x000001D1), 0x00000100 +#define BF_CHB2_INT_TIME_DLY_INFO(inst) ((inst) + 0x000001D1), 0x00000101 +#define BF_CHB3_INT_TIME_DLY_INFO(inst) ((inst) + 0x000001D1), 0x00000102 +#define BF_CTB1_INT_TIME_DLY_INFO(inst) ((inst) + 0x000001D1), 0x00000203 + +#define REG_CDUC_TEST_MUX_ADDR(inst) ((inst) + 0x000001D2) +#define BF_TEST_MUX_INFO(inst) ((inst) + 0x000001D2), 0x00000400 + +#define REG_CDUC_IRQ_EN0_ADDR(inst) ((inst) + 0x000001D3) +#define BF_CDUC_IRQ_EN0_INFO(inst) ((inst) + 0x000001D3), 0x00000A00 + +#define REG_CDUC_IRQ_EN1_ADDR(inst) ((inst) + 0x000001D4) + +#define REG_CDUC_IRQ_EN2_ADDR(inst) ((inst) + 0x000001D5) +#define BF_CDUC_IRQ_EN1_INFO(inst) ((inst) + 0x000001D5), 0x00000A00 + +#define REG_CDUC_IRQ_EN3_ADDR(inst) ((inst) + 0x000001D6) + +#define REG_CDUC_IRQ_STATUS0_ADDR(inst) ((inst) + 0x000001D7) +#define BF_CHB1_I_OVR_STATUS0_INFO(inst) ((inst) + 0x000001D7), 0x00000100 +#define BF_CHB1_Q_OVR_STATUS0_INFO(inst) ((inst) + 0x000001D7), 0x00000101 +#define BF_CHB2_I_OVR_STATUS0_INFO(inst) ((inst) + 0x000001D7), 0x00000102 +#define BF_CHB2_Q_OVR_STATUS0_INFO(inst) ((inst) + 0x000001D7), 0x00000103 +#define BF_CHB3_I_OVR_STATUS0_INFO(inst) ((inst) + 0x000001D7), 0x00000104 +#define BF_CHB3_Q_OVR_STATUS0_INFO(inst) ((inst) + 0x000001D7), 0x00000105 +#define BF_CTB1_I_OVR_STATUS0_INFO(inst) ((inst) + 0x000001D7), 0x00000106 +#define BF_CTB1_Q_OVR_STATUS0_INFO(inst) ((inst) + 0x000001D7), 0x00000107 + +#define REG_CDUC_IRQ_STATUS1_ADDR(inst) ((inst) + 0x000001D8) +#define BF_CNCO_I_OVR_STATUS0_INFO(inst) ((inst) + 0x000001D8), 0x00000100 +#define BF_CNCO_Q_OVR_STATUS0_INFO(inst) ((inst) + 0x000001D8), 0x00000101 + +#define REG_CDUC_IRQ_STATUS2_ADDR(inst) ((inst) + 0x000001D9) +#define BF_CHB1_I_OVR_STATUS1_INFO(inst) ((inst) + 0x000001D9), 0x00000100 +#define BF_CHB1_Q_OVR_STATUS1_INFO(inst) ((inst) + 0x000001D9), 0x00000101 +#define BF_CHB2_I_OVR_STATUS1_INFO(inst) ((inst) + 0x000001D9), 0x00000102 +#define BF_CHB2_Q_OVR_STATUS1_INFO(inst) ((inst) + 0x000001D9), 0x00000103 +#define BF_CHB3_I_OVR_STATUS1_INFO(inst) ((inst) + 0x000001D9), 0x00000104 +#define BF_CHB3_Q_OVR_STATUS1_INFO(inst) ((inst) + 0x000001D9), 0x00000105 +#define BF_CTB1_I_OVR_STATUS1_INFO(inst) ((inst) + 0x000001D9), 0x00000106 +#define BF_CTB1_Q_OVR_STATUS1_INFO(inst) ((inst) + 0x000001D9), 0x00000107 + +#define REG_CDUC_IRQ_STATUS3_ADDR(inst) ((inst) + 0x000001DA) +#define BF_CNCO_I_OVR_STATUS1_INFO(inst) ((inst) + 0x000001DA), 0x00000100 +#define BF_CNCO_Q_OVR_STATUS1_INFO(inst) ((inst) + 0x000001DA), 0x00000101 + +#define REG_CDUC_IRQ_CLR_ADDR(inst) ((inst) + 0x000001DB) +#define BF_CDUC_IRQ_CLR_INFO(inst) ((inst) + 0x000001DB), 0x00000100 + +#define REG_CDUC_INTERP_GPIO_EN_ADDR(inst) ((inst) + 0x000001DC) +#define BF_POST_INTERP_GPIO_EN_INFO(inst) ((inst) + 0x000001DC), 0x00000100 + +#endif /* __ADI_APOLLO_BF_TX_CDUC_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_tx_eng.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_tx_eng.h new file mode 100644 index 00000000000000..7e4fea796341d5 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_tx_eng.h @@ -0,0 +1,107 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:24 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_TX_ENG_H__ +#define __ADI_APOLLO_BF_TX_ENG_H__ + +/*============= D E F I N E S ==============*/ +#define TX_ENG_TX_TOP_TX_DIGITAL0 0x61010000 +#define TX_ENG_TX_TOP_TX_DIGITAL1 0x61810000 + +#ifdef USE_PRIVATE_BF +#define REG_FHB1_CLK_DEBUG0_ADDR(inst) ((inst) + 0x00000000) +#define BF_FHB1_FORCE_ON_INFO(inst) ((inst) + 0x00000000), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FHB1_CLK_DEBUG1_ADDR(inst) ((inst) + 0x00000001) +#define BF_FHB1_FORCE_OFF_INFO(inst) ((inst) + 0x00000001), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FHB2_CLK_DEBUG0_ADDR(inst) ((inst) + 0x00000002) +#define BF_FHB2_FORCE_ON_INFO(inst) ((inst) + 0x00000002), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FHB2_CLK_DEBUG1_ADDR(inst) ((inst) + 0x00000003) +#define BF_FHB2_FORCE_OFF_INFO(inst) ((inst) + 0x00000003), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FHB3_CLK_DEBUG0_ADDR(inst) ((inst) + 0x00000004) +#define BF_FHB3_FORCE_ON_INFO(inst) ((inst) + 0x00000004), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FHB3_CLK_DEBUG1_ADDR(inst) ((inst) + 0x00000005) +#define BF_FHB3_FORCE_OFF_INFO(inst) ((inst) + 0x00000005), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FHB4_CLK_DEBUG0_ADDR(inst) ((inst) + 0x00000006) +#define BF_FHB4_FORCE_ON_INFO(inst) ((inst) + 0x00000006), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FHB4_CLK_DEBUG1_ADDR(inst) ((inst) + 0x00000007) +#define BF_FHB4_FORCE_OFF_INFO(inst) ((inst) + 0x00000007), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FHB5_CLK_DEBUG0_ADDR(inst) ((inst) + 0x00000008) +#define BF_FHB5_FORCE_ON_INFO(inst) ((inst) + 0x00000008), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FHB5_CLK_DEBUG1_ADDR(inst) ((inst) + 0x00000009) +#define BF_FHB5_FORCE_OFF_INFO(inst) ((inst) + 0x00000009), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FHB6_CLK_DEBUG0_ADDR(inst) ((inst) + 0x0000000A) +#define BF_FHB6_FORCE_ON_INFO(inst) ((inst) + 0x0000000A), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FHB6_CLK_DEBUG1_ADDR(inst) ((inst) + 0x0000000B) +#define BF_FHB6_FORCE_OFF_INFO(inst) ((inst) + 0x0000000B), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CHB1_CLK_DEBUG_ADDR(inst) ((inst) + 0x0000000C) +#define BF_FORCE_CHB1_ON_INFO(inst) ((inst) + 0x0000000C), 0x00000400 +#define BF_FORCE_CHB1_OFF_INFO(inst) ((inst) + 0x0000000C), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CTB1_CLK_DEBUG_ADDR(inst) ((inst) + 0x0000000D) +#define BF_FORCE_CTB1_ON_INFO(inst) ((inst) + 0x0000000D), 0x00000400 +#define BF_FORCE_CTB1_OFF_INFO(inst) ((inst) + 0x0000000D), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CHB2_CLK_DEBUG_ADDR(inst) ((inst) + 0x0000000E) +#define BF_FORCE_CHB2_ON_INFO(inst) ((inst) + 0x0000000E), 0x00000400 +#define BF_FORCE_CHB2_OFF_INFO(inst) ((inst) + 0x0000000E), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CHB3_CLK_DEBUG_ADDR(inst) ((inst) + 0x0000000F) +#define BF_FORCE_CHB3_ON_INFO(inst) ((inst) + 0x0000000F), 0x00000400 +#define BF_FORCE_CHB3_OFF_INFO(inst) ((inst) + 0x0000000F), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#endif /* __ADI_APOLLO_BF_TX_ENG_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_tx_fduc.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_tx_fduc.h new file mode 100644 index 00000000000000..fb615ed4579e56 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_tx_fduc.h @@ -0,0 +1,49 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:25 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_TX_FDUC_H__ +#define __ADI_APOLLO_BF_TX_FDUC_H__ + +/*============= D E F I N E S ==============*/ +#define TX_FDUC0_TX_SLICE_0_TX_DIGITAL0 0x61307000 +#define TX_FDUC1_TX_SLICE_0_TX_DIGITAL0 0x61308000 +#define TX_FDUC0_TX_SLICE_1_TX_DIGITAL0 0x61507000 +#define TX_FDUC1_TX_SLICE_1_TX_DIGITAL0 0x61508000 +#define TX_FDUC0_TX_SLICE_0_TX_DIGITAL1 0x61B07000 +#define TX_FDUC1_TX_SLICE_0_TX_DIGITAL1 0x61B08000 +#define TX_FDUC0_TX_SLICE_1_TX_DIGITAL1 0x61D07000 +#define TX_FDUC1_TX_SLICE_1_TX_DIGITAL1 0x61D08000 + +#define REG_FDUC_INTERP_ADDR(inst) ((inst) + 0x00000000) +#define BF_FDUC_INTERP_INFO(inst) ((inst) + 0x00000000), 0x00000700 + +#define REG_SUB_DATAPATH_CFG_ADDR(inst) ((inst) + 0x00000002) +#define BF_SUB_DP_GAIN_EN_INFO(inst) ((inst) + 0x00000002), 0x00000100 +#define BF_FDUC_INTERP_GPIO_EN_INFO(inst) ((inst) + 0x00000002), 0x00000101 + +#define REG_SUBDP_GAIN0_ADDR(inst) ((inst) + 0x00000003) +#define BF_SUBDP_GAIN_INFO(inst) ((inst) + 0x00000003), 0x00000C00 + +#define REG_SUBDP_GAIN1_ADDR(inst) ((inst) + 0x00000004) + +#define REG_INT_TIME_DELAY_ADDR(inst) ((inst) + 0x00000006) +#define BF_INT_TIME_DELAY_HB1_INFO(inst) ((inst) + 0x00000006), 0x00000100 +#define BF_INT_TIME_DELAY_HB2_INFO(inst) ((inst) + 0x00000006), 0x00000101 +#define BF_INT_TIME_DELAY_HB3_INFO(inst) ((inst) + 0x00000006), 0x00000102 +#define BF_INT_TIME_DELAY_HB4_INFO(inst) ((inst) + 0x00000006), 0x00000103 +#define BF_INT_TIME_DELAY_HB5_INFO(inst) ((inst) + 0x00000006), 0x00000104 +#define BF_INT_TIME_DELAY_HB6_INFO(inst) ((inst) + 0x00000006), 0x00000105 + +#endif /* __ADI_APOLLO_BF_TX_FDUC_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_tx_hsdout.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_tx_hsdout.h new file mode 100644 index 00000000000000..d417f6707af11f --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_tx_hsdout.h @@ -0,0 +1,112 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:24 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_TX_HSDOUT_H__ +#define __ADI_APOLLO_BF_TX_HSDOUT_H__ + +/*============= D E F I N E S ==============*/ +#define TX_HSDOUT0_TX_SLICE_0_TX_DIGITAL0 0x61204000 +#define TX_HSDOUT1_TX_SLICE_0_TX_DIGITAL0 0x61205000 +#define TX_HSDOUT0_TX_SLICE_1_TX_DIGITAL0 0x61404000 +#define TX_HSDOUT1_TX_SLICE_1_TX_DIGITAL0 0x61405000 +#define TX_HSDOUT0_TX_SLICE_0_TX_DIGITAL1 0x61A04000 +#define TX_HSDOUT1_TX_SLICE_0_TX_DIGITAL1 0x61A05000 +#define TX_HSDOUT0_TX_SLICE_1_TX_DIGITAL1 0x61C04000 +#define TX_HSDOUT1_TX_SLICE_1_TX_DIGITAL1 0x61C05000 + +#define REG_DAC_REG_WR_SETUP_CYCLES_ADDR(inst) ((inst) + 0x00000000) +#define BF_DAC_ANA_BRIDGE_WR_SETUP_CYCLES_INFO(inst) ((inst) + 0x00000000), 0x00000600 + +#define REG_DAC_REG_WR_HOLD_CYCLES_ADDR(inst) ((inst) + 0x00000001) +#define BF_DAC_ANA_BRIDGE_WR_HOLD_CYCLES_INFO(inst) ((inst) + 0x00000001), 0x00000600 + +#define REG_DAC_REG_RD_CYCLES_ADDR(inst) ((inst) + 0x00000002) +#define BF_DAC_ANA_BRIDGE_RD_CYCLES_INFO(inst) ((inst) + 0x00000002), 0x00000600 + +#define REG_DFIFO_CTRL_TX_HSDOUT_ADDR(inst) ((inst) + 0x00000050) +#define BF_DFIFO_EN_TX_HSDOUT_INFO(inst) ((inst) + 0x00000050), 0x00000100 +#define BF_DAC_FIFO_FORCEON_CTRL_TX_HSDOUT_INFO(inst) ((inst) + 0x00000050), 0x00000404 + +#define REG_LAT_CTRL_TX_HSDOUT_ADDR(inst) ((inst) + 0x00000051) +#define BF_LAT_PGM_MODE_TX_HSDOUT_INFO(inst) ((inst) + 0x00000051), 0x00000200 +#define BF_WR_RD_OFFSET_TX_HSDOUT_INFO(inst) ((inst) + 0x00000051), 0x00000304 +#define BF_DAC_SCRAMBLER_EN_INFO(inst) ((inst) + 0x00000051), 0x00000107 + +#define REG_LAT_SPI_CTRL_TX_HSDOUT_ADDR(inst) ((inst) + 0x00000052) +#define BF_LAT_WR_SPI_TX_HSDOUT_INFO(inst) ((inst) + 0x00000052), 0x00000300 +#define BF_LAT_RD_SPI_TX_HSDOUT_INFO(inst) ((inst) + 0x00000052), 0x00000404 + +#define REG_SYNCCNT_STRB_TX_HSDOUT_ADDR(inst) ((inst) + 0x00000053) +#define BF_WRSYNCCNT_RDSTRB_TX_HSDOUT_INFO(inst) ((inst) + 0x00000053), 0x00000300 +#define BF_RDSYNCCNT_WRSTRB_TX_HSDOUT_INFO(inst) ((inst) + 0x00000053), 0x00000404 + +#define REG_LAT_REAL_TX_HSDOUT_ADDR(inst) ((inst) + 0x00000054) +#define BF_LAT_WR_REAL_TX_HSDOUT_INFO(inst) ((inst) + 0x00000054), 0x00000300 +#define BF_LAT_RD_REAL_TX_HSDOUT_INFO(inst) ((inst) + 0x00000054), 0x00000404 + +#define REG_SYNC_STATE_TX_HSDOUT_ADDR(inst) ((inst) + 0x00000055) +#define BF_WRSYNC_STATE_TX_HSDOUT_INFO(inst) ((inst) + 0x00000055), 0x00000200 +#define BF_RDSYNC_STATE_TX_HSDOUT_INFO(inst) ((inst) + 0x00000055), 0x00000204 + +#define REG_DATA_INVERSION_ADDR(inst) ((inst) + 0x00000056) +#define BF_DAC_DATA_INVERSION_EN_INFO(inst) ((inst) + 0x00000056), 0x00000100 + +#define REG_DITHER_NCO_CTRL_ADDR(inst) ((inst) + 0x00000070) +#define BF_DITHER_NCO_EN_INFO(inst) ((inst) + 0x00000070), 0x00000100 +#define BF_DITHER_NCO_GAIN_INFO(inst) ((inst) + 0x00000070), 0x00000304 +#define BF_DITHER_NCO_PRN_RESET_INFO(inst) ((inst) + 0x00000070), 0x00000107 + +#define REG_DITHER_NCO_PHASE_OFFSET0_ADDR(inst) ((inst) + 0x00000071) +#define BF_DITHER_NCO_PHASE_OFFSET_INFO(inst) ((inst) + 0x00000071), 0x00000C00 + +#define REG_DITHER_NCO_PHASE_OFFSET1_ADDR(inst) ((inst) + 0x00000072) + +#define REG_DITHER_NCO_FTW0_ADDR(inst) ((inst) + 0x00000073) +#define BF_DITHER_NCO_FTW_INFO(inst) ((inst) + 0x00000073), 0x00000C00 + +#define REG_DITHER_NCO_FTW1_ADDR(inst) ((inst) + 0x00000074) + +#define REG_DITHER_NCO_MODE_ADDR(inst) ((inst) + 0x00000075) +#define BF_DITHER_NCO_MODE_INFO(inst) ((inst) + 0x00000075), 0x00000800 + +#define REG_DITHER_NCO_SYNC_CTRL_ADDR(inst) ((inst) + 0x00000076) +#define BF_DITHER_NCO_SYNC_BYSPI_INFO(inst) ((inst) + 0x00000076), 0x00000100 +#define BF_DITHER_NCO_SYNCEN_INFO(inst) ((inst) + 0x00000076), 0x00000104 + +#define REG_DITHER_NCO_PHASE_OFFSET_ACTIVE0_ADDR(inst) ((inst) + 0x00000077) +#define BF_DITHER_NCO_PHASE_OFFSET_ACTIVE_INFO(inst) ((inst) + 0x00000077), 0x00000C00 + +#define REG_DITHER_NCO_PHASE_OFFSET_ACTIVE1_ADDR(inst) ((inst) + 0x00000078) + +#define REG_DITHER_NCO_FTW_ACTIVE0_ADDR(inst) ((inst) + 0x00000079) +#define BF_DITHER_NCO_FTW_ACTIVE_INFO(inst) ((inst) + 0x00000079), 0x00000C00 + +#define REG_DITHER_NCO_FTW_ACTIVE1_ADDR(inst) ((inst) + 0x0000007A) + +#define REG_INVSINC_CFG_ADDR(inst) ((inst) + 0x000001D0) +#define BF_INVSINC_EN_INFO(inst) ((inst) + 0x000001D0), 0x00000100 + +#define REG_INVSINC_CLK_GATING_ADDR(inst) ((inst) + 0x000001D1) +#define BF_INVSINC_CLK_EN_INFO(inst) ((inst) + 0x000001D1), 0x00000100 + +#ifdef USE_PRIVATE_BF +#define REG_TEST_MUX_LVDS_ADDR(inst) ((inst) + 0x000001D4) +#define BF_TEST_SEL_LVDS_INFO(inst) ((inst) + 0x000001D4), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#define REG_TEST_MUX_CMOS_ADDR(inst) ((inst) + 0x000001D5) +#define BF_TEST_SEL_CMOS_INFO(inst) ((inst) + 0x000001D5), 0x00000500 + +#endif /* __ADI_APOLLO_BF_TX_HSDOUT_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_tx_loopback.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_tx_loopback.h new file mode 100644 index 00000000000000..8f14aba7231ffd --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_tx_loopback.h @@ -0,0 +1,40 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:24 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_TX_LOOPBACK_H__ +#define __ADI_APOLLO_BF_TX_LOOPBACK_H__ + +/*============= D E F I N E S ==============*/ +#define TX_LOOPBACK0_TX_SLICE_0_TX_DIGITAL0 0x61200000 +#define TX_LOOPBACK1_TX_SLICE_0_TX_DIGITAL0 0x61201000 +#define TX_LOOPBACK0_TX_SLICE_1_TX_DIGITAL0 0x61400000 +#define TX_LOOPBACK1_TX_SLICE_1_TX_DIGITAL0 0x61401000 +#define TX_LOOPBACK0_TX_SLICE_0_TX_DIGITAL1 0x61A00000 +#define TX_LOOPBACK1_TX_SLICE_0_TX_DIGITAL1 0x61A01000 +#define TX_LOOPBACK0_TX_SLICE_1_TX_DIGITAL1 0x61C00000 +#define TX_LOOPBACK1_TX_SLICE_1_TX_DIGITAL1 0x61C01000 + +#define REG_LB0_CFG_ADDR(inst) ((inst) + 0x00000000) +#define BF_LB0_EN_INFO(inst) ((inst) + 0x00000000), 0x00000100 + +#define REG_LB0_RDPTR_CTRL_ADDR(inst) ((inst) + 0x00000001) +#define BF_LB0_RDPTR_SYNC_RSTVAL_INFO(inst) ((inst) + 0x00000001), 0x00000200 + +#ifdef USE_PRIVATE_BF +#define REG_LB0_STATUS_ADDR(inst) ((inst) + 0x00000023) +#define BF_LB_STATUS_INFO(inst) ((inst) + 0x00000023), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#endif /* __ADI_APOLLO_BF_TX_LOOPBACK_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_tx_misc.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_tx_misc.h new file mode 100644 index 00000000000000..8d19f5c4162b04 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_tx_misc.h @@ -0,0 +1,352 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:24 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_TX_MISC_H__ +#define __ADI_APOLLO_BF_TX_MISC_H__ + +/*============= D E F I N E S ==============*/ +#define TX_MISC_TX_TOP_TX_DIGITAL0 0x61000000 +#define TX_MISC_TX_TOP_TX_DIGITAL1 0x61800000 + +#define REG_DP_CFG_ADDR(inst) ((inst) + 0x00000000) +#define BF_MODSW0_INFO(inst) ((inst) + 0x00000000), 0x00000300 +#define BF_MODSW1_INFO(inst) ((inst) + 0x00000000), 0x00000303 +#define BF_DIS_SCALE_INFO(inst) ((inst) + 0x00000000), 0x00000206 + +#ifdef USE_PRIVATE_BF +#define REG_HS_XBAR_CTRL_ADDR(inst) ((inst) + 0x00000001) +#define BF_HS_XBAR_CTRL_INFO(inst) ((inst) + 0x00000001), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_FDUC_ENABLES00_ADDR(inst) ((inst) + 0x00000002) +#define BF_FDUC_ENABLES00_INFO(inst) ((inst) + 0x00000002), 0x00000800 + +#define REG_FDUC_ENABLES01_ADDR(inst) ((inst) + 0x00000003) +#define BF_FDUC_ENABLES01_INFO(inst) ((inst) + 0x00000003), 0x00000800 + +#define REG_FDUC_ENABLES10_ADDR(inst) ((inst) + 0x00000004) +#define BF_FDUC_ENABLES10_INFO(inst) ((inst) + 0x00000004), 0x00000800 + +#define REG_FDUC_ENABLES11_ADDR(inst) ((inst) + 0x00000005) +#define BF_FDUC_ENABLES11_INFO(inst) ((inst) + 0x00000005), 0x00000800 + +#define REG_LOW_SAMP_TX_MISC_ADDR(inst) ((inst) + 0x00000007) +#define BF_LOW_SAMP_TX_MISC_INFO(inst) ((inst) + 0x00000007), 0x00000100 + +#define REG_SL0_FDUC0_HB_IRQ_EN0_ADDR(inst) ((inst) + 0x00000008) +#define BF_EN_FDUC_A0_HB1_I_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x00000008), 0x00000100 +#define BF_EN_FDUC_A0_HB2_I_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x00000008), 0x00000101 +#define BF_EN_FDUC_A0_HB3_I_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x00000008), 0x00000102 +#define BF_EN_FDUC_A0_HB4_I_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x00000008), 0x00000103 +#define BF_EN_FDUC_A0_HB5_I_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x00000008), 0x00000104 +#define BF_EN_FDUC_A0_HB6_I_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x00000008), 0x00000105 + +#define REG_SL0_FDUC0_HB_IRQ_EN1_ADDR(inst) ((inst) + 0x00000009) +#define BF_EN_FDUC_A0_HB1_Q_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x00000009), 0x00000100 +#define BF_EN_FDUC_A0_HB2_Q_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x00000009), 0x00000101 +#define BF_EN_FDUC_A0_HB3_Q_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x00000009), 0x00000102 +#define BF_EN_FDUC_A0_HB4_Q_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x00000009), 0x00000103 +#define BF_EN_FDUC_A0_HB5_Q_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x00000009), 0x00000104 +#define BF_EN_FDUC_A0_HB6_Q_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x00000009), 0x00000105 + +#define REG_SL0_FDUC1_IRQ_ADDR(inst) ((inst) + 0x0000000A) +#define BF_EN_FDUC_A1_HB1_I_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x0000000A), 0x00000100 +#define BF_EN_FDUC_A1_HB2_I_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x0000000A), 0x00000101 +#define BF_EN_FDUC_A1_HB3_I_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x0000000A), 0x00000102 +#define BF_EN_FDUC_A1_HB4_I_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x0000000A), 0x00000103 +#define BF_EN_FDUC_A1_HB5_I_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x0000000A), 0x00000104 +#define BF_EN_FDUC_A1_HB6_I_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x0000000A), 0x00000105 + +#define REG_SL0_FDUC1_HB_IRQ_EN1_ADDR(inst) ((inst) + 0x0000000B) +#define BF_EN_FDUC_A1_HB1_Q_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x0000000B), 0x00000100 +#define BF_EN_FDUC_A1_HB2_Q_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x0000000B), 0x00000101 +#define BF_EN_FDUC_A1_HB3_Q_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x0000000B), 0x00000102 +#define BF_EN_FDUC_A1_HB4_Q_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x0000000B), 0x00000103 +#define BF_EN_FDUC_A1_HB5_Q_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x0000000B), 0x00000104 +#define BF_EN_FDUC_A1_HB6_Q_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x0000000B), 0x00000105 + +#define REG_SL0_FNCO_IRQ_EN_ADDR(inst) ((inst) + 0x0000000C) +#define BF_EN_FDUC_A0_FNCO_OVR_I_IRQ0_INFO(inst) ((inst) + 0x0000000C), 0x00000100 +#define BF_EN_FDUC_A0_FNCO_OVR_I_IRQ1_INFO(inst) ((inst) + 0x0000000C), 0x00000101 +#define BF_EN_FDUC_A0_FNCO_OVR_Q_IRQ0_INFO(inst) ((inst) + 0x0000000C), 0x00000102 +#define BF_EN_FDUC_A0_FNCO_OVR_Q_IRQ1_INFO(inst) ((inst) + 0x0000000C), 0x00000103 +#define BF_EN_FDUC_A1_FNCO_OVR_I_IRQ0_INFO(inst) ((inst) + 0x0000000C), 0x00000104 +#define BF_EN_FDUC_A1_FNCO_OVR_I_IRQ1_INFO(inst) ((inst) + 0x0000000C), 0x00000105 +#define BF_EN_FDUC_A1_FNCO_OVR_Q_IRQ0_INFO(inst) ((inst) + 0x0000000C), 0x00000106 +#define BF_EN_FDUC_A1_FNCO_OVR_Q_IRQ1_INFO(inst) ((inst) + 0x0000000C), 0x00000107 + +#define REG_SL1_FDUC0_HB_IRQ_EN0_ADDR(inst) ((inst) + 0x0000000D) +#define BF_EN_FDUC_A2_HB1_I_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x0000000D), 0x00000100 +#define BF_EN_FDUC_A2_HB2_I_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x0000000D), 0x00000101 +#define BF_EN_FDUC_A2_HB3_I_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x0000000D), 0x00000102 +#define BF_EN_FDUC_A2_HB4_I_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x0000000D), 0x00000103 +#define BF_EN_FDUC_A2_HB5_I_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x0000000D), 0x00000104 +#define BF_EN_FDUC_A2_HB6_I_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x0000000D), 0x00000105 + +#define REG_SL1_FDUC0_HB_IRQ_EN1_ADDR(inst) ((inst) + 0x0000000E) +#define BF_EN_FDUC_A2_HB1_Q_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x0000000E), 0x00000100 +#define BF_EN_FDUC_A2_HB2_Q_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x0000000E), 0x00000101 +#define BF_EN_FDUC_A2_HB3_Q_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x0000000E), 0x00000102 +#define BF_EN_FDUC_A2_HB4_Q_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x0000000E), 0x00000103 +#define BF_EN_FDUC_A2_HB5_Q_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x0000000E), 0x00000104 +#define BF_EN_FDUC_A2_HB6_Q_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x0000000E), 0x00000105 + +#define REG_SL1_FDUC1_IRQ_ADDR(inst) ((inst) + 0x0000000F) +#define BF_EN_FDUC_A3_HB1_I_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x0000000F), 0x00000100 +#define BF_EN_FDUC_A3_HB2_I_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x0000000F), 0x00000101 +#define BF_EN_FDUC_A3_HB3_I_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x0000000F), 0x00000102 +#define BF_EN_FDUC_A3_HB4_I_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x0000000F), 0x00000103 +#define BF_EN_FDUC_A3_HB5_I_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x0000000F), 0x00000104 +#define BF_EN_FDUC_A3_HB6_I_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x0000000F), 0x00000105 + +#define REG_SL1_FDUC1_HB_IRQ_EN1_ADDR(inst) ((inst) + 0x00000010) +#define BF_EN_FDUC_A3_HB1_Q_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x00000010), 0x00000100 +#define BF_EN_FDUC_A3_HB2_Q_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x00000010), 0x00000101 +#define BF_EN_FDUC_A3_HB3_Q_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x00000010), 0x00000102 +#define BF_EN_FDUC_A3_HB4_Q_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x00000010), 0x00000103 +#define BF_EN_FDUC_A3_HB5_Q_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x00000010), 0x00000104 +#define BF_EN_FDUC_A3_HB6_Q_OVERFLOW_IRQ_INFO(inst) ((inst) + 0x00000010), 0x00000105 + +#define REG_SL1_FNCO_IRQ_EN_ADDR(inst) ((inst) + 0x00000011) +#define BF_EN_FDUC_A2_FNCO_OVR_I_IRQ0_INFO(inst) ((inst) + 0x00000011), 0x00000100 +#define BF_EN_FDUC_A2_FNCO_OVR_I_IRQ1_INFO(inst) ((inst) + 0x00000011), 0x00000101 +#define BF_EN_FDUC_A2_FNCO_OVR_Q_IRQ0_INFO(inst) ((inst) + 0x00000011), 0x00000102 +#define BF_EN_FDUC_A2_FNCO_OVR_Q_IRQ1_INFO(inst) ((inst) + 0x00000011), 0x00000103 +#define BF_EN_FDUC_A3_FNCO_OVR_I_IRQ0_INFO(inst) ((inst) + 0x00000011), 0x00000104 +#define BF_EN_FDUC_A3_FNCO_OVR_I_IRQ1_INFO(inst) ((inst) + 0x00000011), 0x00000105 +#define BF_EN_FDUC_A3_FNCO_OVR_Q_IRQ0_INFO(inst) ((inst) + 0x00000011), 0x00000106 +#define BF_EN_FDUC_A3_FNCO_OVR_Q_IRQ1_INFO(inst) ((inst) + 0x00000011), 0x00000107 + +#define REG_SL0_FDUC0_HB_OVERFLOW0_ADDR(inst) ((inst) + 0x00000012) +#define BF_IRQ_FDUC_A0_HB1_I_OVER_FLOW_INFO(inst) ((inst) + 0x00000012), 0x00000100 +#define BF_IRQ_FDUC_A0_HB2_I_OVER_FLOW_INFO(inst) ((inst) + 0x00000012), 0x00000101 +#define BF_IRQ_FDUC_A0_HB3_I_OVER_FLOW_INFO(inst) ((inst) + 0x00000012), 0x00000102 +#define BF_IRQ_FDUC_A0_HB4_I_OVER_FLOW_INFO(inst) ((inst) + 0x00000012), 0x00000103 +#define BF_IRQ_FDUC_A0_HB5_I_OVER_FLOW_INFO(inst) ((inst) + 0x00000012), 0x00000104 +#define BF_IRQ_FDUC_A0_HB6_I_OVER_FLOW_INFO(inst) ((inst) + 0x00000012), 0x00000105 +#define BF_IRQ_FDUC_OVER_FLOW_ALL_INFO(inst) ((inst) + 0x00000012), 0x00000106 + +#define REG_SL0_FDUC0_HB_OVERFLOW1_ADDR(inst) ((inst) + 0x00000013) +#define BF_IRQ_FDUC_A0_HB1_Q_OVER_FLOW_INFO(inst) ((inst) + 0x00000013), 0x00000100 +#define BF_IRQ_FDUC_A0_HB2_Q_OVER_FLOW_INFO(inst) ((inst) + 0x00000013), 0x00000101 +#define BF_IRQ_FDUC_A0_HB3_Q_OVER_FLOW_INFO(inst) ((inst) + 0x00000013), 0x00000102 +#define BF_IRQ_FDUC_A0_HB4_Q_OVER_FLOW_INFO(inst) ((inst) + 0x00000013), 0x00000103 +#define BF_IRQ_FDUC_A0_HB5_Q_OVER_FLOW_INFO(inst) ((inst) + 0x00000013), 0x00000104 +#define BF_IRQ_FDUC_A0_HB6_Q_OVER_FLOW_INFO(inst) ((inst) + 0x00000013), 0x00000105 + +#define REG_SL0_FDUC1_HB_OVERFLOW0_ADDR(inst) ((inst) + 0x00000014) +#define BF_IRQ_FDUC_A1_HB1_I_OVER_FLOW_INFO(inst) ((inst) + 0x00000014), 0x00000100 +#define BF_IRQ_FDUC_A1_HB2_I_OVER_FLOW_INFO(inst) ((inst) + 0x00000014), 0x00000101 +#define BF_IRQ_FDUC_A1_HB3_I_OVER_FLOW_INFO(inst) ((inst) + 0x00000014), 0x00000102 +#define BF_IRQ_FDUC_A1_HB4_I_OVER_FLOW_INFO(inst) ((inst) + 0x00000014), 0x00000103 +#define BF_IRQ_FDUC_A1_HB5_I_OVER_FLOW_INFO(inst) ((inst) + 0x00000014), 0x00000104 +#define BF_IRQ_FDUC_A1_HB6_I_OVER_FLOW_INFO(inst) ((inst) + 0x00000014), 0x00000105 + +#define REG_SL0_FDUC1_HB_OVERFLOW1_ADDR(inst) ((inst) + 0x00000015) +#define BF_IRQ_FDUC_A1_HB1_Q_OVER_FLOW_INFO(inst) ((inst) + 0x00000015), 0x00000100 +#define BF_IRQ_FDUC_A1_HB2_Q_OVER_FLOW_INFO(inst) ((inst) + 0x00000015), 0x00000101 +#define BF_IRQ_FDUC_A1_HB3_Q_OVER_FLOW_INFO(inst) ((inst) + 0x00000015), 0x00000102 +#define BF_IRQ_FDUC_A1_HB4_Q_OVER_FLOW_INFO(inst) ((inst) + 0x00000015), 0x00000103 +#define BF_IRQ_FDUC_A1_HB5_Q_OVER_FLOW_INFO(inst) ((inst) + 0x00000015), 0x00000104 +#define BF_IRQ_FDUC_A1_HB6_Q_OVER_FLOW_INFO(inst) ((inst) + 0x00000015), 0x00000105 + +#define REG_SL0_FNCO_OVERFLOW_ADDR(inst) ((inst) + 0x00000016) +#define BF_IRQ_FDUC_A0_FNCO_I_OVER_FLOW0_INFO(inst) ((inst) + 0x00000016), 0x00000100 +#define BF_IRQ_FDUC_A0_FNCO_I_OVER_FLOW1_INFO(inst) ((inst) + 0x00000016), 0x00000101 +#define BF_IRQ_FDUC_A0_FNCO_Q_OVER_FLOW0_INFO(inst) ((inst) + 0x00000016), 0x00000102 +#define BF_IRQ_FDUC_A0_FNCO_Q_OVER_FLOW1_INFO(inst) ((inst) + 0x00000016), 0x00000103 +#define BF_IRQ_FDUC_A1_FNCO_I_OVER_FLOW0_INFO(inst) ((inst) + 0x00000016), 0x00000104 +#define BF_IRQ_FDUC_A1_FNCO_I_OVER_FLOW1_INFO(inst) ((inst) + 0x00000016), 0x00000105 +#define BF_IRQ_FDUC_A1_FNCO_Q_OVER_FLOW0_INFO(inst) ((inst) + 0x00000016), 0x00000106 +#define BF_IRQ_FDUC_A1_FNCO_Q_OVER_FLOW1_INFO(inst) ((inst) + 0x00000016), 0x00000107 + +#define REG_SL1_FDUC0_HB_OVERFLOW0_ADDR(inst) ((inst) + 0x00000017) +#define BF_IRQ_FDUC_A2_HB1_I_OVER_FLOW_INFO(inst) ((inst) + 0x00000017), 0x00000100 +#define BF_IRQ_FDUC_A2_HB2_I_OVER_FLOW_INFO(inst) ((inst) + 0x00000017), 0x00000101 +#define BF_IRQ_FDUC_A2_HB3_I_OVER_FLOW_INFO(inst) ((inst) + 0x00000017), 0x00000102 +#define BF_IRQ_FDUC_A2_HB4_I_OVER_FLOW_INFO(inst) ((inst) + 0x00000017), 0x00000103 +#define BF_IRQ_FDUC_A2_HB5_I_OVER_FLOW_INFO(inst) ((inst) + 0x00000017), 0x00000104 +#define BF_IRQ_FDUC_A2_HB6_I_OVER_FLOW_INFO(inst) ((inst) + 0x00000017), 0x00000105 + +#define REG_SL1_FDUC0_HB_OVERFLOW1_ADDR(inst) ((inst) + 0x00000018) +#define BF_IRQ_FDUC_A2_HB1_Q_OVER_FLOW_INFO(inst) ((inst) + 0x00000018), 0x00000100 +#define BF_IRQ_FDUC_A2_HB2_Q_OVER_FLOW_INFO(inst) ((inst) + 0x00000018), 0x00000101 +#define BF_IRQ_FDUC_A2_HB3_Q_OVER_FLOW_INFO(inst) ((inst) + 0x00000018), 0x00000102 +#define BF_IRQ_FDUC_A2_HB4_Q_OVER_FLOW_INFO(inst) ((inst) + 0x00000018), 0x00000103 +#define BF_IRQ_FDUC_A2_HB5_Q_OVER_FLOW_INFO(inst) ((inst) + 0x00000018), 0x00000104 +#define BF_IRQ_FDUC_A2_HB6_Q_OVER_FLOW_INFO(inst) ((inst) + 0x00000018), 0x00000105 + +#define REG_SL1_FDUC1_HB_OVERFLOW0_ADDR(inst) ((inst) + 0x00000019) +#define BF_IRQ_FDUC_A3_HB1_I_OVER_FLOW_INFO(inst) ((inst) + 0x00000019), 0x00000100 +#define BF_IRQ_FDUC_A3_HB2_I_OVER_FLOW_INFO(inst) ((inst) + 0x00000019), 0x00000101 +#define BF_IRQ_FDUC_A3_HB3_I_OVER_FLOW_INFO(inst) ((inst) + 0x00000019), 0x00000102 +#define BF_IRQ_FDUC_A3_HB4_I_OVER_FLOW_INFO(inst) ((inst) + 0x00000019), 0x00000103 +#define BF_IRQ_FDUC_A3_HB5_I_OVER_FLOW_INFO(inst) ((inst) + 0x00000019), 0x00000104 +#define BF_IRQ_FDUC_A3_HB6_I_OVER_FLOW_INFO(inst) ((inst) + 0x00000019), 0x00000105 + +#define REG_SL1_FDUC1_HB_OVERFLOW1_ADDR(inst) ((inst) + 0x0000001A) +#define BF_IRQ_FDUC_A3_HB1_Q_OVER_FLOW_INFO(inst) ((inst) + 0x0000001A), 0x00000100 +#define BF_IRQ_FDUC_A3_HB2_Q_OVER_FLOW_INFO(inst) ((inst) + 0x0000001A), 0x00000101 +#define BF_IRQ_FDUC_A3_HB3_Q_OVER_FLOW_INFO(inst) ((inst) + 0x0000001A), 0x00000102 +#define BF_IRQ_FDUC_A3_HB4_Q_OVER_FLOW_INFO(inst) ((inst) + 0x0000001A), 0x00000103 +#define BF_IRQ_FDUC_A3_HB5_Q_OVER_FLOW_INFO(inst) ((inst) + 0x0000001A), 0x00000104 +#define BF_IRQ_FDUC_A3_HB6_Q_OVER_FLOW_INFO(inst) ((inst) + 0x0000001A), 0x00000105 + +#define REG_SL1_FNCO_OVERFLOW_ADDR(inst) ((inst) + 0x0000001B) +#define BF_IRQ_FDUC_A2_FNCO_I_OVER_FLOW0_INFO(inst) ((inst) + 0x0000001B), 0x00000100 +#define BF_IRQ_FDUC_A2_FNCO_I_OVER_FLOW1_INFO(inst) ((inst) + 0x0000001B), 0x00000101 +#define BF_IRQ_FDUC_A2_FNCO_Q_OVER_FLOW0_INFO(inst) ((inst) + 0x0000001B), 0x00000102 +#define BF_IRQ_FDUC_A2_FNCO_Q_OVER_FLOW1_INFO(inst) ((inst) + 0x0000001B), 0x00000103 +#define BF_IRQ_FDUC_A3_FNCO_I_OVER_FLOW0_INFO(inst) ((inst) + 0x0000001B), 0x00000104 +#define BF_IRQ_FDUC_A3_FNCO_I_OVER_FLOW1_INFO(inst) ((inst) + 0x0000001B), 0x00000105 +#define BF_IRQ_FDUC_A3_FNCO_Q_OVER_FLOW0_INFO(inst) ((inst) + 0x0000001B), 0x00000106 +#define BF_IRQ_FDUC_A3_FNCO_Q_OVER_FLOW1_INFO(inst) ((inst) + 0x0000001B), 0x00000107 + +#define REG_CDUC_DAC_ENABLES_ADDR(inst) ((inst) + 0x0000001C) +#define BF_CDUC_DAC_ENABLES0_INFO(inst) ((inst) + 0x0000001C), 0x00000200 +#define BF_CDUC_DAC_ENABLES1_INFO(inst) ((inst) + 0x0000001C), 0x00000202 +#define BF_CDUC_DAC_ENABLES2_INFO(inst) ((inst) + 0x0000001C), 0x00000204 +#define BF_CDUC_DAC_ENABLES3_INFO(inst) ((inst) + 0x0000001C), 0x00000206 + +#define REG_DUC_EN_CFG_ADDR(inst) ((inst) + 0x0000001D) +#define BF_CDUC_EN_INFO(inst) ((inst) + 0x0000001D), 0x00000400 +#define BF_CDUC_SPI_EN_INFO(inst) ((inst) + 0x0000001D), 0x00000106 +#define BF_FDUC_SPI_EN_INFO(inst) ((inst) + 0x0000001D), 0x00000107 + +#define REG_FDUC_EN_SPI_ADDR(inst) ((inst) + 0x0000001E) +#define BF_FDUC_EN_INFO(inst) ((inst) + 0x0000001E), 0x00000800 + +#define REG_FDUC_TEST_MUX_ADDR(inst) ((inst) + 0x0000001F) +#define BF_FDUC_TEST_MUX_INFO(inst) ((inst) + 0x0000001F), 0x00000600 + +#define REG_CFIR_DATA_CTRL_ADDR(inst) ((inst) + 0x00000020) +#define BF_CFIR1_SAME_AS_CFIR0_EN_INFO(inst) ((inst) + 0x00000020), 0x00000100 + +#ifdef USE_PRIVATE_BF +#define REG_LNX_DBG_MUX_SEL_ADDR(inst) ((inst) + 0x00000021) +#define BF_LNX_DBG_MUX_SEL_INFO(inst) ((inst) + 0x00000021), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CFIR_FSRC_DBG_CNT_EN_ADDR(inst) ((inst) + 0x00000022) +#define BF_CFIR_FSRC_DBG_CNT_EN_INFO(inst) ((inst) + 0x00000022), 0x00001000 +#endif /* USE_PRIVATE_BF */ + +#define REG_CFIR_FSRC_DBG_CNT_EN1_ADDR(inst) ((inst) + 0x00000023) + +#ifdef USE_PRIVATE_BF +#define REG_CFIR_FSRC_DBG_MUX_SEL_ADDR(inst) ((inst) + 0x00000024) +#define BF_CFIR_FSRC_DBG_MUX_SEL_INFO(inst) ((inst) + 0x00000024), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#define REG_LB1_CFG_TX_MISC_ADDR(inst) ((inst) + 0x00000025) +#define BF_LB1_EN_INFO(inst) ((inst) + 0x00000025), 0x00000400 +#define BF_LB1_RDPTR_SYNC_RSTVAL_SL0_INFO(inst) ((inst) + 0x00000025), 0x00000204 +#define BF_LB1_RDPTR_SYNC_RSTVAL_SL1_INFO(inst) ((inst) + 0x00000025), 0x00000206 + +#define REG_LB1_SHIFT_CTRL_ADDR(inst) ((inst) + 0x00000026) +#define BF_SL0_LB1_SHIFT_INFO(inst) ((inst) + 0x00000026), 0x00000200 +#define BF_SL1_LB1_SHIFT_INFO(inst) ((inst) + 0x00000026), 0x00000202 +#define BF_SL0_LB1_SHIFT_8T8R_INFO(inst) ((inst) + 0x00000026), 0x00000204 +#define BF_SL1_LB1_SHIFT_8T8R_INFO(inst) ((inst) + 0x00000026), 0x00000206 + +#define REG_LB2_CFG0_ADDR(inst) ((inst) + 0x00000027) +#define BF_LB2_EN_INFO(inst) ((inst) + 0x00000027), 0x00000800 + +#define REG_LB2_CFG1_ADDR(inst) ((inst) + 0x00000028) +#define BF_LB2_RDPTR_SYNC_RSTVAL_SL00_INFO(inst) ((inst) + 0x00000028), 0x00000200 +#define BF_LB2_RDPTR_SYNC_RSTVAL_SL01_INFO(inst) ((inst) + 0x00000028), 0x00000202 +#define BF_LB2_RDPTR_SYNC_RSTVAL_SL10_INFO(inst) ((inst) + 0x00000028), 0x00000204 +#define BF_LB2_RDPTR_SYNC_RSTVAL_SL11_INFO(inst) ((inst) + 0x00000028), 0x00000206 + +#define REG_ZCD_SEL_TX_ADDR(inst) ((inst) + 0x00000029) +#define BF_ZCD_SEL_TAP1_TX_MISC_INFO(inst) ((inst) + 0x00000029), 0x00000400 +#define BF_ZCD_SEL_TAP2_TX_MISC_INFO(inst) ((inst) + 0x00000029), 0x00000404 + +#ifdef USE_PRIVATE_BF +#define REG_LINX_DBG_CNT_EN_TX_MISC_ADDR(inst) ((inst) + 0x0000033E) +#define BF_LNX_DBG_CNT_EN_INFO(inst) ((inst) + 0x0000033E), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_PROCESS_MON_SEL_ADDR(inst) ((inst) + 0x0000033F) +#define BF_PROCESS_MON_SEL_INFO(inst) ((inst) + 0x0000033F), 0x00000800 + +#define REG_JESD_LBK_REGISTER_ADDR(inst) ((inst) + 0x00000340) +#define BF_JESD_LBK_MODE_INFO(inst) ((inst) + 0x00000340), 0x00000100 +#ifdef USE_PRIVATE_BF +#define BF_JESD_LBK_MODE_PTR_INFO(inst) ((inst) + 0x00000340), 0x00000201 +#endif /* USE_PRIVATE_BF */ +#ifdef USE_PRIVATE_BF +#define BF_JESD_LBK_MODE_PTR_OVERRIDE_TX_MISC_INFO(inst) ((inst) + 0x00000340), 0x00000103 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_LB1_BIST_CFG_TX_MISC_ADDR(inst) ((inst) + 0x00000341) +#define BF_LB1_BIST_SIGN_RD_EN_INFO(inst) ((inst) + 0x00000341), 0x00000100 +#define BF_LB1_BIST_SIGN_RD_MODE_INFO(inst) ((inst) + 0x00000341), 0x00000101 +#define BF_LB1_BIST_SIGN_RD_CLR_INFO(inst) ((inst) + 0x00000341), 0x00000102 +#define BF_LB1_BIST_ZERO_NOT_SENSITIVE_INFO(inst) ((inst) + 0x00000341), 0x00000103 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_LB1_BIST_RD_SEL_ADDR(inst) ((inst) + 0x00000342) +#define BF_LB1_BIST_SIGN_RD_SEL_INFO(inst) ((inst) + 0x00000342), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_LB1_BIST_SIGN_LSB_ADDR(inst) ((inst) + 0x00000343) +#define BF_LB1_BIST_SIGNATURE_INFO(inst) ((inst) + 0x00000343), 0x00001800 +#endif /* USE_PRIVATE_BF */ + +#define REG_LB1_BIST_SIGN_MID_ADDR(inst) ((inst) + 0x00000344) + +#define REG_LB1_BIST_SIGN_MSB_ADDR(inst) ((inst) + 0x00000345) + +#ifdef USE_PRIVATE_BF +#define REG_LB2_BIST_CFG_TX_MISC_ADDR(inst) ((inst) + 0x00000346) +#define BF_LB2_BIST_SIGN_RD_EN_INFO(inst) ((inst) + 0x00000346), 0x00000100 +#define BF_LB2_BIST_SIGN_RD_MODE_INFO(inst) ((inst) + 0x00000346), 0x00000101 +#define BF_LB2_BIST_SIGN_RD_CLR_INFO(inst) ((inst) + 0x00000346), 0x00000102 +#define BF_LB2_BIST_ZERO_NOT_SENSITIVE_INFO(inst) ((inst) + 0x00000346), 0x00000103 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_LB2_BIST_RD_SEL_ADDR(inst) ((inst) + 0x00000347) +#define BF_LB2_BIST_SIGN_RD_SEL_INFO(inst) ((inst) + 0x00000347), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_LB2_BIST_SIGN_LSB_ADDR(inst) ((inst) + 0x00000348) +#define BF_LB2_BIST_SIGNATURE_INFO(inst) ((inst) + 0x00000348), 0x00001800 +#endif /* USE_PRIVATE_BF */ + +#define REG_LB2_BIST_SIGN_MID_ADDR(inst) ((inst) + 0x00000349) + +#define REG_LB2_BIST_SIGN_MSB_ADDR(inst) ((inst) + 0x0000034A) + +#ifdef USE_PRIVATE_BF +#define REG_MODE_8T8R_TX_MISC_ADDR(inst) ((inst) + 0x0000034B) +#define BF_MODE_8T8R_TX_MISC_INFO(inst) ((inst) + 0x0000034B), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#define REG_LB_RDPTR_CTRL_ADDR(inst) ((inst) + 0x0000034C) +#define BF_LB1_RDPTR_RSTVAL_OVERRIDE_SL0_INFO(inst) ((inst) + 0x0000034C), 0x00000100 +#define BF_LB1_RDPTR_RSTVAL_OVERRIDE_SL1_INFO(inst) ((inst) + 0x0000034C), 0x00000101 +#define BF_LB2_RDPTR_RSTVAL_OVERRIDE_SL00_INFO(inst) ((inst) + 0x0000034C), 0x00000102 +#define BF_LB2_RDPTR_RSTVAL_OVERRIDE_SL01_INFO(inst) ((inst) + 0x0000034C), 0x00000103 +#define BF_LB2_RDPTR_RSTVAL_OVERRIDE_SL10_INFO(inst) ((inst) + 0x0000034C), 0x00000104 +#define BF_LB2_RDPTR_RSTVAL_OVERRIDE_SL11_INFO(inst) ((inst) + 0x0000034C), 0x00000105 + +#endif /* __ADI_APOLLO_BF_TX_MISC_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_tx_pa.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_tx_pa.h new file mode 100644 index 00000000000000..93a83fd6b9699f --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_tx_pa.h @@ -0,0 +1,70 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:25 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_TX_PA_H__ +#define __ADI_APOLLO_BF_TX_PA_H__ + +/*============= D E F I N E S ==============*/ +#define TX_PA0_TX_SLICE_0_TX_DIGITAL0 0x61336000 +#define TX_PA1_TX_SLICE_0_TX_DIGITAL0 0x61337000 +#define TX_PA0_TX_SLICE_1_TX_DIGITAL0 0x61536000 +#define TX_PA1_TX_SLICE_1_TX_DIGITAL0 0x61537000 +#define TX_PA0_TX_SLICE_0_TX_DIGITAL1 0x61B36000 +#define TX_PA1_TX_SLICE_0_TX_DIGITAL1 0x61B37000 +#define TX_PA0_TX_SLICE_1_TX_DIGITAL1 0x61D36000 +#define TX_PA1_TX_SLICE_1_TX_DIGITAL1 0x61D37000 + +#define REG_LONG_PA_THRES_LSB_ADDR(inst) ((inst) + 0x00000024) +#define BF_PWR_THRESHOLD_LONG_INFO(inst) ((inst) + 0x00000024), 0x00000D00 + +#define REG_LONG_PA_THRES_MSB_ADDR(inst) ((inst) + 0x00000025) + +#define REG_LONG_PA_AVG_ADDR(inst) ((inst) + 0x00000026) +#define BF_AVG_LONG_WIN_INFO(inst) ((inst) + 0x00000026), 0x00000400 + +#define REG_SHORT_PA_AVG_ADDR(inst) ((inst) + 0x00000027) +#define BF_AVG_SHORT_WIN_INFO(inst) ((inst) + 0x00000027), 0x00000200 + +#define REG_SHORT_PA_THRES_LSB_ADDR(inst) ((inst) + 0x00000028) +#define BF_PWR_THRESHOLD_SHORT_INFO(inst) ((inst) + 0x00000028), 0x00000D00 + +#define REG_SHORT_PA_THRES_MSB_ADDR(inst) ((inst) + 0x00000029) + +#define REG_LONG_PA_POWER_LSB_ADDR(inst) ((inst) + 0x00000030) +#define BF_CALCULATED_PWR_AVG_LONG_INFO(inst) ((inst) + 0x00000030), 0x00000D00 + +#define REG_LONG_PA_POWER_MSB_ADDR(inst) ((inst) + 0x00000031) + +#define REG_SHORT_PA_POWER_LSB_ADDR(inst) ((inst) + 0x00000032) +#define BF_CALCULATED_PWR_AVG_SHORT_INFO(inst) ((inst) + 0x00000032), 0x00000D00 + +#define REG_SHORT_PA_POWER_MSB_ADDR(inst) ((inst) + 0x00000033) + +#define REG_PA_PWR_AVG_CTRL_ADDR(inst) ((inst) + 0x00000034) +#define BF_LONG_PAC_ENABLE_INFO(inst) ((inst) + 0x00000034), 0x00000101 +#define BF_SHORT_PAC_ENABLE_INFO(inst) ((inst) + 0x00000034), 0x00000102 +#define BF_PA_AVG_ERR_INFO(inst) ((inst) + 0x00000034), 0x00000103 +#define BF_PA_PWR_AVG_ERR_CLEAR_INFO(inst) ((inst) + 0x00000034), 0x00000104 +#define BF_PA_CLK_ENA_INFO(inst) ((inst) + 0x00000034), 0x00000107 + +#define REG_PA_PWR_AVG_IRQ_ADDR(inst) ((inst) + 0x00000035) +#define BF_PA_AVG_ERR_IRQ_INFO(inst) ((inst) + 0x00000035), 0x00000100 +#define BF_PA_AVG_ERR_IRQ_EN_INFO(inst) ((inst) + 0x00000035), 0x00000101 +#define BF_LONG_WIN_DONE_IRQ_INFO(inst) ((inst) + 0x00000035), 0x00000102 +#define BF_LONG_WIN_DONE_IRQ_EN_INFO(inst) ((inst) + 0x00000035), 0x00000103 +#define BF_SHORT_WIN_DONE_IRQ_INFO(inst) ((inst) + 0x00000035), 0x00000104 +#define BF_SHORT_WIN_DONE_IRQ_EN_INFO(inst) ((inst) + 0x00000035), 0x00000105 + +#endif /* __ADI_APOLLO_BF_TX_PA_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_tx_paprot.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_tx_paprot.h new file mode 100644 index 00000000000000..8469460656ba8f --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_tx_paprot.h @@ -0,0 +1,161 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:24 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_TX_PAPROT_H__ +#define __ADI_APOLLO_BF_TX_PAPROT_H__ + +/*============= D E F I N E S ==============*/ +#define TX_PAPROT0_TX_SLICE_0_TX_DIGITAL0 0x61202000 +#define TX_PAPROT1_TX_SLICE_0_TX_DIGITAL0 0x61203000 +#define TX_PAPROT0_TX_SLICE_1_TX_DIGITAL0 0x61402000 +#define TX_PAPROT1_TX_SLICE_1_TX_DIGITAL0 0x61403000 +#define TX_PAPROT0_TX_SLICE_0_TX_DIGITAL1 0x61A02000 +#define TX_PAPROT1_TX_SLICE_0_TX_DIGITAL1 0x61A03000 +#define TX_PAPROT0_TX_SLICE_1_TX_DIGITAL1 0x61C02000 +#define TX_PAPROT1_TX_SLICE_1_TX_DIGITAL1 0x61C03000 + +#define REG_ALARM_CNTRL0_ADDR(inst) ((inst) + 0x00000000) +#define BF_JESD_ERR_EN_INFO(inst) ((inst) + 0x00000000), 0x00000100 +#ifdef USE_PRIVATE_BF +#define BF_CLK_STABILITY_CHECK_BYPASS_INFO(inst) ((inst) + 0x00000000), 0x00000101 +#endif /* USE_PRIVATE_BF */ +#define BF_AUTO_DYN_RECONF_EN_INFO(inst) ((inst) + 0x00000000), 0x00000102 +#ifdef USE_PRIVATE_BF +#define BF_RESET_DYN_SYNC_SM_INFO(inst) ((inst) + 0x00000000), 0x00000103 +#endif /* USE_PRIVATE_BF */ +#define BF_AVG_PWR_ERR_EN_INFO(inst) ((inst) + 0x00000000), 0x00000104 +#define BF_SRL_ERR_EN_INFO(inst) ((inst) + 0x00000000), 0x00000105 +#define BF_RAMPDWN_TO_PAPIN_EN_INFO(inst) ((inst) + 0x00000000), 0x00000106 +#ifdef USE_PRIVATE_BF +#define BF_RESET_ALARM_INFO(inst) ((inst) + 0x00000000), 0x00000107 +#endif /* USE_PRIVATE_BF */ + +#define REG_ALARM_CNTRL1_ADDR(inst) ((inst) + 0x00000001) +#define BF_FORCE_ZERO_FLUSH_EN_INFO(inst) ((inst) + 0x00000001), 0x00000100 +#define BF_FORCE_ZERO_FLUSH_SPI_INFO(inst) ((inst) + 0x00000001), 0x00000101 +#define BF_DP_ZERO_FLUSH_SEL_0_INFO(inst) ((inst) + 0x00000001), 0x00000202 +#define BF_DP_ZERO_FLUSH_SEL_1_INFO(inst) ((inst) + 0x00000001), 0x00000204 +#define BF_DATA_READY_AUTO_CONFIG_EN_INFO(inst) ((inst) + 0x00000001), 0x00000106 +#define BF_JESD_ERR_AUTO_CONFIG_EN_INFO(inst) ((inst) + 0x00000001), 0x00000107 + +#define REG_ALARM_CNTRL2_ADDR(inst) ((inst) + 0x00000002) +#define BF_JESD_ERR_SEL_RAMP_INFO(inst) ((inst) + 0x00000002), 0x00000200 +#define BF_DATA_READY_SEL_RAMP_INFO(inst) ((inst) + 0x00000002), 0x00000202 +#define BF_ZERO_FLUSH_TXEN_RISE_EN_INFO(inst) ((inst) + 0x00000002), 0x00000104 +#define BF_ZERO_FLUSH_TXEN_FALL_EN_INFO(inst) ((inst) + 0x00000002), 0x00000105 +#define BF_ZERO_FLUSH_DYN_RECONF_RAMP_UP_EN_INFO(inst) ((inst) + 0x00000002), 0x00000106 +#define BF_ZERO_FLUSH_CLOCK_STABLE_RISE_EN_INFO(inst) ((inst) + 0x00000002), 0x00000107 + +#define REG_ALARM_CNTRL3_ADDR(inst) ((inst) + 0x00000003) +#define BF_ZERO_FLUSH_START_EN_INFO(inst) ((inst) + 0x00000003), 0x00000100 +#define BF_SM_PAUSE_EN_INFO(inst) ((inst) + 0x00000003), 0x00000101 +#define BF_SM_RESUME_SPI_INFO(inst) ((inst) + 0x00000003), 0x00000102 + +#define REG_PASM_CTRL0_ADDR(inst) ((inst) + 0x00000004) +#define BF_SKIP_RAMP_DWN_INFO(inst) ((inst) + 0x00000004), 0x00000100 +#define BF_RAMP_DWN_TIMER_EN_INFO(inst) ((inst) + 0x00000004), 0x00000101 +#define BF_RAMP_UP_TIMER_EN_INFO(inst) ((inst) + 0x00000004), 0x00000102 +#define BF_ENABLE_PAPROTSM_INFO(inst) ((inst) + 0x00000004), 0x00000103 +#define BF_SKIP_RAMP_UP_INFO(inst) ((inst) + 0x00000004), 0x00000104 +#define BF_HOLD_SAMPLE_EN_INFO(inst) ((inst) + 0x00000004), 0x00000105 +#define BF_RESET_RAMP_GAIN_INFO(inst) ((inst) + 0x00000004), 0x00000106 +#define BF_DRIVE_SM_BY_DIG_EN_INFO(inst) ((inst) + 0x00000004), 0x00000107 + +#define REG_START_TIMER_ADDR(inst) ((inst) + 0x00000005) +#define BF_START_TIMER_INFO(inst) ((inst) + 0x00000005), 0x00000800 + +#define REG_ZERO_FLUSH_TIMER_LSB_ADDR(inst) ((inst) + 0x00000006) +#define BF_ZERO_FLUSH_TIMER_INFO(inst) ((inst) + 0x00000006), 0x00000D00 + +#define REG_ZERO_FLUSH_TIMER_MSB_ADDR(inst) ((inst) + 0x00000007) + +#define REG_RAMP_DWN_TIMER_VAL_LSB_ADDR(inst) ((inst) + 0x00000008) +#define BF_RAMP_DWN_TIMER_VAL_INFO(inst) ((inst) + 0x00000008), 0x00001000 + +#define REG_RAMP_DWN_TIMER_VAL_MSB_ADDR(inst) ((inst) + 0x00000009) + +#define REG_RAMP_UP_TIMER_VAL_LSB_ADDR(inst) ((inst) + 0x0000000A) +#define BF_RAMP_UP_TIMER_VAL_INFO(inst) ((inst) + 0x0000000A), 0x00001000 + +#define REG_RAMP_UP_TIMER_VAL_MSB_ADDR(inst) ((inst) + 0x0000000B) + +#define REG_SM_STATUS_ADDR(inst) ((inst) + 0x0000000C) +#define BF_MAIN_SM_CURRENT_INFO(inst) ((inst) + 0x0000000C), 0x00000500 +#define BF_CLOCKS_SM_CURRENT_INFO(inst) ((inst) + 0x0000000C), 0x00000305 + +#define REG_RAMP_DOWN_COUNT_ADDR(inst) ((inst) + 0x0000000D) +#define BF_RAMP_DOWN_COUNT_INFO(inst) ((inst) + 0x0000000D), 0x00000800 + +#define REG_MANUAL_CTRL_ADDR(inst) ((inst) + 0x00000021) +#define BF_FORCE_RAMP_DWN_INFO(inst) ((inst) + 0x00000021), 0x00000100 +#define BF_FORCE_RAMP_DWN_EN_INFO(inst) ((inst) + 0x00000021), 0x00000101 +#define BF_FORCE_RAMP_UP_INFO(inst) ((inst) + 0x00000021), 0x00000102 +#define BF_FORCE_RAMP_UP_EN_INFO(inst) ((inst) + 0x00000021), 0x00000103 +#define BF_FORCE_RAMPS_DYN_RECFIG_EN_INFO(inst) ((inst) + 0x00000021), 0x00000104 +#define BF_ZERO_DETECT_EN_INFO(inst) ((inst) + 0x00000021), 0x00000105 + +#define REG_GAIN_INC_STEP_ADDR(inst) ((inst) + 0x00000022) +#define BF_GAIN_INC_STEP_INFO(inst) ((inst) + 0x00000022), 0x00000800 + +#define REG_GAIN_DEC_STEP_ADDR(inst) ((inst) + 0x0000002A) +#define BF_GAIN_DEC_STEP_INFO(inst) ((inst) + 0x0000002A), 0x00000800 + +#define REG_GAIN_VALUE_ADDR(inst) ((inst) + 0x00000032) +#define BF_GAIN_MAX_VAL_INFO(inst) ((inst) + 0x00000032), 0x00000800 + +#define REG_RAMP_CNTRL_ADDR(inst) ((inst) + 0x00000033) +#define BF_ENABLE_GAIN_INFO(inst) ((inst) + 0x00000033), 0x00000101 +#define BF_ENABLE_RAMP_INFO(inst) ((inst) + 0x00000033), 0x00000102 + +#define REG_ZIF_RAMP_CTRL_ADDR(inst) ((inst) + 0x00000034) +#define BF_TRIG_RAMP_TOGETHER_INFO(inst) ((inst) + 0x00000034), 0x00000100 + +#define REG_SLEW_RATE_CTRL_ADDR(inst) ((inst) + 0x00000040) +#define BF_SR_CALCULATION_EN_INFO(inst) ((inst) + 0x00000040), 0x00000100 +#define BF_SR_ERR_SELF_CLR_EN_INFO(inst) ((inst) + 0x00000040), 0x00000101 +#define BF_SR_PATH_SEL_INFO(inst) ((inst) + 0x00000040), 0x00000502 +#define BF_SR_MANUAL_CLR_INFO(inst) ((inst) + 0x00000040), 0x00000107 + +#define REG_SR_THRESHOLD0_ADDR(inst) ((inst) + 0x00000041) +#define BF_SR_THRESHOLD_INFO(inst) ((inst) + 0x00000041), 0x00001100 + +#define REG_SR_THRESHOLD1_ADDR(inst) ((inst) + 0x00000042) + +#define REG_SR_THRESHOLD2_ADDR(inst) ((inst) + 0x00000043) + +#define REG_SR_CALCULATED_DATA_LSB_ADDR(inst) ((inst) + 0x00000044) +#define BF_SR_CALCULATED_INFO(inst) ((inst) + 0x00000044), 0x00001100 + +#define REG_SR_CALCULATED_DATA_ISB_ADDR(inst) ((inst) + 0x00000045) + +#define REG_SR_CALCULATED_DATA_MSB_ADDR(inst) ((inst) + 0x00000046) +#define BF_SR_DETECTED_ERR_INFO(inst) ((inst) + 0x00000046), 0x00000107 + +#define REG_PAPROT_IRQ_ENABLE_ADDR(inst) ((inst) + 0x00000060) +#define BF_SLEW_RATE_ERR_IRQ_EN_INFO(inst) ((inst) + 0x00000060), 0x00000101 + +#define REG_PAPROT_IRQ_STATUS_ADDR(inst) ((inst) + 0x00000061) +#define BF_SLEW_RATE_ERR_IRQ_INFO(inst) ((inst) + 0x00000061), 0x00000101 + +#define REG_FORCE_CLKS_ADDR(inst) ((inst) + 0x00000080) +#ifdef USE_PRIVATE_BF +#define BF_SR_CLK_EN_INFO(inst) ((inst) + 0x00000080), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_GAIN_CLK_EN_INFO(inst) ((inst) + 0x00000080), 0x00000101 + +#define REG_CLOCK_DIV_EN_ADDR(inst) ((inst) + 0x00000081) +#define BF_PA_CLKDIV_EN_INFO(inst) ((inst) + 0x00000081), 0x00000100 + +#endif /* __ADI_APOLLO_BF_TX_PAPROT_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_txen_power_ctrl.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_txen_power_ctrl.h new file mode 100644 index 00000000000000..6c6f2ab51bed72 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_txen_power_ctrl.h @@ -0,0 +1,82 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:23 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_TXEN_POWER_CTRL_H__ +#define __ADI_APOLLO_BF_TXEN_POWER_CTRL_H__ + +/*============= D E F I N E S ==============*/ +#define RXEN_POWER_CTRL0_RX_SLICE_0_RX_DIGITAL0 0x603AF000 +#define RXEN_POWER_CTRL1_RX_SLICE_0_RX_DIGITAL0 0x603B0000 +#define RXEN_POWER_CTRL0_RX_SLICE_1_RX_DIGITAL0 0x605AF000 +#define RXEN_POWER_CTRL1_RX_SLICE_1_RX_DIGITAL0 0x605B0000 +#define RXEN_POWER_CTRL0_RX_SLICE_0_RX_DIGITAL1 0x60BAF000 +#define RXEN_POWER_CTRL1_RX_SLICE_0_RX_DIGITAL1 0x60BB0000 +#define RXEN_POWER_CTRL0_RX_SLICE_1_RX_DIGITAL1 0x60DAF000 +#define RXEN_POWER_CTRL1_RX_SLICE_1_RX_DIGITAL1 0x60DB0000 +#define TXEN_POWER_CTRL0_TX_SLICE_0_TX_DIGITAL0 0x61208000 +#define TXEN_POWER_CTRL1_TX_SLICE_0_TX_DIGITAL0 0x61209000 +#define TXEN_POWER_CTRL0_TX_SLICE_1_TX_DIGITAL0 0x61408000 +#define TXEN_POWER_CTRL1_TX_SLICE_1_TX_DIGITAL0 0x61409000 +#define TXEN_POWER_CTRL0_TX_SLICE_0_TX_DIGITAL1 0x61A08000 +#define TXEN_POWER_CTRL1_TX_SLICE_0_TX_DIGITAL1 0x61A09000 +#define TXEN_POWER_CTRL0_TX_SLICE_1_TX_DIGITAL1 0x61C08000 +#define TXEN_POWER_CTRL1_TX_SLICE_1_TX_DIGITAL1 0x61C09000 + +#define REG_TXEN_PWR_CRTL_ADDR(inst) ((inst) + 0x00000000) +#define BF_SM_EN_INFO(inst) ((inst) + 0x00000000), 0x00000100 +#define BF_SPI_TXEN_ENA_INFO(inst) ((inst) + 0x00000000), 0x00000101 +#define BF_SPI_TXEN_INFO(inst) ((inst) + 0x00000000), 0x00000102 +#define BF_SEL_CNT_RATE_INFO(inst) ((inst) + 0x00000000), 0x00000103 + +#define REG_TXEN_DAC_EDGES_ADDR(inst) ((inst) + 0x00000001) +#define BF_DAC_RISE_INFO(inst) ((inst) + 0x00000001), 0x00000200 +#define BF_DAC_FALL_INFO(inst) ((inst) + 0x00000001), 0x00000202 + +#define REG_TXEN_DIG_EDGES_ADDR(inst) ((inst) + 0x00000002) +#define BF_DIG_RISE_INFO(inst) ((inst) + 0x00000002), 0x00000200 +#define BF_DIG_FALL_INFO(inst) ((inst) + 0x00000002), 0x00000202 + +#define REG_TXEN_PA_EDGES_ADDR(inst) ((inst) + 0x00000003) +#define BF_PA_RISE_INFO(inst) ((inst) + 0x00000003), 0x00000200 +#define BF_PA_FALL_INFO(inst) ((inst) + 0x00000003), 0x00000202 + +#define REG_MAX_A_ADDR(inst) ((inst) + 0x00000004) +#define BF_COUNT_MAXA_INFO(inst) ((inst) + 0x00000004), 0x00000800 + +#define REG_MAX_B_ADDR(inst) ((inst) + 0x00000005) +#define BF_COUNT_MAXB_INFO(inst) ((inst) + 0x00000005), 0x00000800 + +#define REG_MAX_C_ADDR(inst) ((inst) + 0x00000006) +#define BF_COUNT_MAXC_INFO(inst) ((inst) + 0x00000006), 0x00000800 + +#define REG_MAX_D_ADDR(inst) ((inst) + 0x00000007) +#define BF_COUNT_MAXD_INFO(inst) ((inst) + 0x00000007), 0x00000800 + +#define REG_MAX_E_ADDR(inst) ((inst) + 0x00000008) +#define BF_COUNT_MAXE_INFO(inst) ((inst) + 0x00000008), 0x00000800 + +#define REG_MAX_F_ADDR(inst) ((inst) + 0x00000009) +#define BF_COUNT_MAXF_INFO(inst) ((inst) + 0x00000009), 0x00000800 + +#define REG_COUNTER_READ_ADDR(inst) ((inst) + 0x0000000A) +#define BF_COUNT_INFO(inst) ((inst) + 0x0000000A), 0x00000800 + +#define REG_STATES_READ_ADDR(inst) ((inst) + 0x0000000B) +#define BF_STATES_INFO(inst) ((inst) + 0x0000000B), 0x00000800 + +#define REG_TXEN_SEL_ADDR(inst) ((inst) + 0x00000010) +#define BF_TXEN_SEL_INFO(inst) ((inst) + 0x00000010), 0x00000200 + +#endif /* __ADI_APOLLO_BF_TXEN_POWER_CTRL_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_txrx_cfir_coeff.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_txrx_cfir_coeff.h new file mode 100644 index 00000000000000..470b0182137d04 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_txrx_cfir_coeff.h @@ -0,0 +1,133 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:22 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_TXRX_CFIR_COEFF_H__ +#define __ADI_APOLLO_BF_TXRX_CFIR_COEFF_H__ + +/*============= D E F I N E S ==============*/ +#define RX_CFIR_COEFF_RX_SLICE_0_RX_DIGITAL0 0x603A5000 +#define RX_CFIR_COEFF_RX_SLICE_1_RX_DIGITAL0 0x605A5000 +#define RX_CFIR_COEFF_RX_SLICE_0_RX_DIGITAL1 0x60BA5000 +#define RX_CFIR_COEFF_RX_SLICE_1_RX_DIGITAL1 0x60DA5000 +#define TX_CFIR_COEFF_TX_SLICE_0_TX_DIGITAL0 0x6130F000 +#define TX_CFIR_COEFF_TX_SLICE_1_TX_DIGITAL0 0x6150F000 +#define TX_CFIR_COEFF_TX_SLICE_0_TX_DIGITAL1 0x61B0F000 +#define TX_CFIR_COEFF_TX_SLICE_1_TX_DIGITAL1 0x61D0F000 + +#define REG_I_COEFF_0_LSB_1_ADDR(inst, n) ((inst) + 0x00000000 + 2 * (n)) +#define BF_I_COEFF_0_1_INFO(inst, n) ((inst) + 0x00000000 + 2 * (n)), 0x00001000 + +#define REG_I_COEFF_0_MSB_1_ADDR(inst, n) ((inst) + 0x00000001 + 2 * (n)) + +#define REG_Q_COEFF_0_LSB_1_ADDR(inst, n) ((inst) + 0x00000020 + 2 * (n)) +#define BF_Q_COEFF_0_1_INFO(inst, n) ((inst) + 0x00000020 + 2 * (n)), 0x00001000 + +#define REG_Q_COEFF_0_MSB_1_ADDR(inst, n) ((inst) + 0x00000021 + 2 * (n)) + +#define REG_I_COEFF_1_LSB_1_ADDR(inst, n) ((inst) + 0x00000040 + 2 * (n)) +#define BF_I_COEFF_1_1_INFO(inst, n) ((inst) + 0x00000040 + 2 * (n)), 0x00001000 + +#define REG_I_COEFF_1_MSB_1_ADDR(inst, n) ((inst) + 0x00000041 + 2 * (n)) + +#define REG_Q_COEFF_1_LSB_1_ADDR(inst, n) ((inst) + 0x00000060 + 2 * (n)) +#define BF_Q_COEFF_1_1_INFO(inst, n) ((inst) + 0x00000060 + 2 * (n)), 0x00001000 + +#define REG_Q_COEFF_1_MSB_1_ADDR(inst, n) ((inst) + 0x00000061 + 2 * (n)) + +#define REG_I_COEFF_2_LSB_1_ADDR(inst, n) ((inst) + 0x00000080 + 2 * (n)) +#define BF_I_COEFF_2_1_INFO(inst, n) ((inst) + 0x00000080 + 2 * (n)), 0x00001000 + +#define REG_I_COEFF_2_MSB_1_ADDR(inst, n) ((inst) + 0x00000081 + 2 * (n)) + +#define REG_Q_COEFF_2_LSB_1_ADDR(inst, n) ((inst) + 0x000000A0 + 2 * (n)) +#define BF_Q_COEFF_2_1_INFO(inst, n) ((inst) + 0x000000A0 + 2 * (n)), 0x00001000 + +#define REG_Q_COEFF_2_MSB_1_ADDR(inst, n) ((inst) + 0x000000A1 + 2 * (n)) + +#define REG_I_COEFF_3_LSB_1_ADDR(inst, n) ((inst) + 0x000000C0 + 2 * (n)) +#define BF_I_COEFF_3_1_INFO(inst, n) ((inst) + 0x000000C0 + 2 * (n)), 0x00001000 + +#define REG_I_COEFF_3_MSB_1_ADDR(inst, n) ((inst) + 0x000000C1 + 2 * (n)) + +#define REG_Q_COEFF_3_LSB_1_ADDR(inst, n) ((inst) + 0x000000E0 + 2 * (n)) +#define BF_Q_COEFF_3_1_INFO(inst, n) ((inst) + 0x000000E0 + 2 * (n)), 0x00001000 + +#define REG_Q_COEFF_3_MSB_1_ADDR(inst, n) ((inst) + 0x000000E1 + 2 * (n)) + +#define REG_I_COEFF_0_LSB_2_ADDR(inst, n) ((inst) + 0x00000100 + 2 * (n)) +#define BF_I_COEFF_0_2_INFO(inst, n) ((inst) + 0x00000100 + 2 * (n)), 0x00001000 + +#define REG_I_COEFF_0_MSB_2_ADDR(inst, n) ((inst) + 0x00000101 + 2 * (n)) + +#define REG_Q_COEFF_0_LSB_2_ADDR(inst, n) ((inst) + 0x00000120 + 2 * (n)) +#define BF_Q_COEFF_0_2_INFO(inst, n) ((inst) + 0x00000120 + 2 * (n)), 0x00001000 + +#define REG_Q_COEFF_0_MSB_2_ADDR(inst, n) ((inst) + 0x00000121 + 2 * (n)) + +#define REG_I_COEFF_1_LSB_2_ADDR(inst, n) ((inst) + 0x00000140 + 2 * (n)) +#define BF_I_COEFF_1_2_INFO(inst, n) ((inst) + 0x00000140 + 2 * (n)), 0x00001000 + +#define REG_I_COEFF_1_MSB_2_ADDR(inst, n) ((inst) + 0x00000141 + 2 * (n)) + +#define REG_Q_COEFF_1_LSB_2_ADDR(inst, n) ((inst) + 0x00000160 + 2 * (n)) +#define BF_Q_COEFF_1_2_INFO(inst, n) ((inst) + 0x00000160 + 2 * (n)), 0x00001000 + +#define REG_Q_COEFF_1_MSB_2_ADDR(inst, n) ((inst) + 0x00000161 + 2 * (n)) + +#define REG_I_COEFF_2_LSB_2_ADDR(inst, n) ((inst) + 0x00000180 + 2 * (n)) +#define BF_I_COEFF_2_2_INFO(inst, n) ((inst) + 0x00000180 + 2 * (n)), 0x00001000 + +#define REG_I_COEFF_2_MSB_2_ADDR(inst, n) ((inst) + 0x00000181 + 2 * (n)) + +#define REG_Q_COEFF_2_LSB_2_ADDR(inst, n) ((inst) + 0x000001A0 + 2 * (n)) +#define BF_Q_COEFF_2_2_INFO(inst, n) ((inst) + 0x000001A0 + 2 * (n)), 0x00001000 + +#define REG_Q_COEFF_2_MSB_2_ADDR(inst, n) ((inst) + 0x000001A1 + 2 * (n)) + +#define REG_I_COEFF_3_LSB_2_ADDR(inst, n) ((inst) + 0x000001C0 + 2 * (n)) +#define BF_I_COEFF_3_2_INFO(inst, n) ((inst) + 0x000001C0 + 2 * (n)), 0x00001000 + +#define REG_I_COEFF_3_MSB_2_ADDR(inst, n) ((inst) + 0x000001C1 + 2 * (n)) + +#define REG_Q_COEFF_3_LSB_2_ADDR(inst, n) ((inst) + 0x000001E0 + 2 * (n)) +#define BF_Q_COEFF_3_2_INFO(inst, n) ((inst) + 0x000001E0 + 2 * (n)), 0x00001000 + +#define REG_Q_COEFF_3_MSB_2_ADDR(inst, n) ((inst) + 0x000001E1 + 2 * (n)) + +#define REG_COEFF_SEL_0_1_ADDR(inst, n) ((inst) + 0x00000201 + 1 * (n)) +#define BF_COEFF_SEL_0_1_INFO(inst, n) ((inst) + 0x00000201 + 1 * (n)), 0x00000600 + +#define REG_COEFF_SEL_1_1_ADDR(inst, n) ((inst) + 0x00000211 + 1 * (n)) +#define BF_COEFF_SEL_1_1_INFO(inst, n) ((inst) + 0x00000211 + 1 * (n)), 0x00000600 + +#define REG_COEFF_SEL_2_1_ADDR(inst, n) ((inst) + 0x00000221 + 1 * (n)) +#define BF_COEFF_SEL_2_1_INFO(inst, n) ((inst) + 0x00000221 + 1 * (n)), 0x00000600 + +#define REG_COEFF_SEL_3_1_ADDR(inst, n) ((inst) + 0x00000231 + 1 * (n)) +#define BF_COEFF_SEL_3_1_INFO(inst, n) ((inst) + 0x00000231 + 1 * (n)), 0x00000600 + +#define REG_COEFF_SEL_0_2_ADDR(inst, n) ((inst) + 0x00000241 + 1 * (n)) +#define BF_COEFF_SEL_0_2_INFO(inst, n) ((inst) + 0x00000241 + 1 * (n)), 0x00000600 + +#define REG_COEFF_SEL_1_2_ADDR(inst, n) ((inst) + 0x00000251 + 1 * (n)) +#define BF_COEFF_SEL_1_2_INFO(inst, n) ((inst) + 0x00000251 + 1 * (n)), 0x00000600 + +#define REG_COEFF_SEL_2_2_ADDR(inst, n) ((inst) + 0x00000261 + 1 * (n)) +#define BF_COEFF_SEL_2_2_INFO(inst, n) ((inst) + 0x00000261 + 1 * (n)), 0x00000600 + +#define REG_COEFF_SEL_3_2_ADDR(inst, n) ((inst) + 0x00000271 + 1 * (n)) +#define BF_COEFF_SEL_3_2_INFO(inst, n) ((inst) + 0x00000271 + 1 * (n)), 0x00000600 + +#endif /* __ADI_APOLLO_BF_TXRX_CFIR_COEFF_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_txrx_cfir_top.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_txrx_cfir_top.h new file mode 100644 index 00000000000000..60f81f0658967f --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_txrx_cfir_top.h @@ -0,0 +1,167 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:22 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_TXRX_CFIR_TOP_H__ +#define __ADI_APOLLO_BF_TXRX_CFIR_TOP_H__ + +/*============= D E F I N E S ==============*/ +#define RX_CFIR_TOP_RX_SLICE_0_RX_DIGITAL0 0x603A4000 +#define RX_CFIR_TOP_RX_SLICE_1_RX_DIGITAL0 0x605A4000 +#define RX_CFIR_TOP_RX_SLICE_0_RX_DIGITAL1 0x60BA4000 +#define RX_CFIR_TOP_RX_SLICE_1_RX_DIGITAL1 0x60DA4000 +#define TX_CFIR_TOP_TX_SLICE_0_TX_DIGITAL0 0x6130E000 +#define TX_CFIR_TOP_TX_SLICE_1_TX_DIGITAL0 0x6150E000 +#define TX_CFIR_TOP_TX_SLICE_0_TX_DIGITAL1 0x61B0E000 +#define TX_CFIR_TOP_TX_SLICE_1_TX_DIGITAL1 0x61D0E000 + +#define REG_CFIR_MODE_ADDR(inst) ((inst) + 0x00000000) +#define BF_CFIR_BYPASS_INFO(inst) ((inst) + 0x00000000), 0x00000100 + +#define REG_CFIR_CFG_ADDR(inst) ((inst) + 0x00000001) +#define BF_CFIR_SPARSE_FILT_EN_INFO(inst) ((inst) + 0x00000001), 0x00000100 +#ifdef USE_PRIVATE_BF +#define BF_CFIR_32TAPS_EN_INFO(inst) ((inst) + 0x00000001), 0x00000101 +#endif /* USE_PRIVATE_BF */ + +#define REG_CFIR_PROFILE_ADDR(inst) ((inst) + 0x00000002) +#define BF_COEFF_PROFILE_SEL_INFO(inst) ((inst) + 0x00000002), 0x00000400 +#define BF_GPIO_PROFILE_EN_INFO(inst) ((inst) + 0x00000002), 0x00000104 + +#define REG_CFIR_TRIGGER_ADDR(inst) ((inst) + 0x00000003) +#define BF_TRIGGER_EN_TXRX_CFIR_TOP_INFO(inst) ((inst) + 0x00000003), 0x00000100 +#define BF_COEFF_TRANSFER_INFO(inst) ((inst) + 0x00000003), 0x00000101 + +#define REG_CFIR_GAIN0_1_ADDR(inst) ((inst) + 0x00000010) +#define BF_CFIR_GAIN0_1_INFO(inst) ((inst) + 0x00000010), 0x00000300 + +#define REG_CFIR_GAIN1_1_ADDR(inst) ((inst) + 0x00000011) +#define BF_CFIR_GAIN1_1_INFO(inst) ((inst) + 0x00000011), 0x00000300 + +#define REG_CFIR_GAIN2_1_ADDR(inst) ((inst) + 0x00000012) +#define BF_CFIR_GAIN2_1_INFO(inst) ((inst) + 0x00000012), 0x00000300 + +#define REG_CFIR_GAIN3_1_ADDR(inst) ((inst) + 0x00000013) +#define BF_CFIR_GAIN3_1_INFO(inst) ((inst) + 0x00000013), 0x00000300 + +#define REG_CFIR_GAIN0_2_ADDR(inst) ((inst) + 0x00000014) +#define BF_CFIR_GAIN0_2_INFO(inst) ((inst) + 0x00000014), 0x00000300 + +#define REG_CFIR_GAIN1_2_ADDR(inst) ((inst) + 0x00000015) +#define BF_CFIR_GAIN1_2_INFO(inst) ((inst) + 0x00000015), 0x00000300 + +#define REG_CFIR_GAIN2_2_ADDR(inst) ((inst) + 0x00000016) +#define BF_CFIR_GAIN2_2_INFO(inst) ((inst) + 0x00000016), 0x00000300 + +#define REG_CFIR_GAIN3_2_ADDR(inst) ((inst) + 0x00000017) +#define BF_CFIR_GAIN3_2_INFO(inst) ((inst) + 0x00000017), 0x00000300 + +#ifdef USE_PRIVATE_BF +#define REG_CFIR_BIST_CTRL_ADDR(inst) ((inst) + 0x00000018) +#define BF_CFIR_BIST_EN_INFO(inst) ((inst) + 0x00000018), 0x00000100 +#define BF_CFIR_BIST_INIT_INFO(inst) ((inst) + 0x00000018), 0x00000101 +#define BF_CFIR_BIST_EN_CLEAR_INFO(inst) ((inst) + 0x00000018), 0x00000102 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CFIR_BIST_CRC_LSB_ADDR(inst) ((inst) + 0x00000019) +#define BF_CFIR_BIST_CRC_INFO(inst) ((inst) + 0x00000019), 0x00001000 +#endif /* USE_PRIVATE_BF */ + +#define REG_CFIR_BIST_CRC_MSB_ADDR(inst) ((inst) + 0x0000001A) + +#define REG_I_COMP_SCAL_LSB_1_ADDR(inst, n) ((inst) + 0x00000020 + 2 * (n)) +#define BF_I_COMPLEX_SCALAR_1_INFO(inst, n) ((inst) + 0x00000020 + 2 * (n)), 0x00001000 + +#define REG_I_COMP_SCAL_MSB_1_ADDR(inst, n) ((inst) + 0x00000021 + 2 * (n)) + +#define REG_Q_COMP_SCAL_LSB_1_ADDR(inst, n) ((inst) + 0x00000028 + 2 * (n)) +#define BF_Q_COMPLEX_SCALAR_1_INFO(inst, n) ((inst) + 0x00000028 + 2 * (n)), 0x00001000 + +#define REG_Q_COMP_SCAL_MSB_1_ADDR(inst, n) ((inst) + 0x00000029 + 2 * (n)) + +#define REG_I_COMP_SCAL_LSB_2_ADDR(inst, n) ((inst) + 0x00000030 + 2 * (n)) +#define BF_I_COMPLEX_SCALAR_2_INFO(inst, n) ((inst) + 0x00000030 + 2 * (n)), 0x00001000 + +#define REG_I_COMP_SCAL_MSB_2_ADDR(inst, n) ((inst) + 0x00000031 + 2 * (n)) + +#define REG_Q_COMP_SCAL_LSB_2_ADDR(inst, n) ((inst) + 0x00000038 + 2 * (n)) +#define BF_Q_COMPLEX_SCALAR_2_INFO(inst, n) ((inst) + 0x00000038 + 2 * (n)), 0x00001000 + +#define REG_Q_COMP_SCAL_MSB_2_ADDR(inst, n) ((inst) + 0x00000039 + 2 * (n)) + +#define REG_DPATH0_MEM_SEL_1_ADDR(inst) ((inst) + 0x00000040) +#define BF_DPATH0_MEM_SEL0_1_INFO(inst) ((inst) + 0x00000040), 0x00000200 +#define BF_DPATH0_MEM_SEL1_1_INFO(inst) ((inst) + 0x00000040), 0x00000202 +#define BF_DPATH0_MEM_SEL2_1_INFO(inst) ((inst) + 0x00000040), 0x00000204 + +#define REG_DPATH1_MEM_SEL_1_ADDR(inst) ((inst) + 0x00000041) +#define BF_DPATH1_MEM_SEL0_1_INFO(inst) ((inst) + 0x00000041), 0x00000200 +#define BF_DPATH1_MEM_SEL1_1_INFO(inst) ((inst) + 0x00000041), 0x00000202 +#define BF_DPATH1_MEM_SEL2_1_INFO(inst) ((inst) + 0x00000041), 0x00000204 + +#define REG_DPATH2_MEM_SEL_1_ADDR(inst) ((inst) + 0x00000042) +#define BF_DPATH2_MEM_SEL0_1_INFO(inst) ((inst) + 0x00000042), 0x00000200 +#define BF_DPATH2_MEM_SEL1_1_INFO(inst) ((inst) + 0x00000042), 0x00000202 +#define BF_DPATH2_MEM_SEL2_1_INFO(inst) ((inst) + 0x00000042), 0x00000204 + +#define REG_DPATH3_MEM_SEL_1_ADDR(inst) ((inst) + 0x00000043) +#define BF_DPATH3_MEM_SEL0_1_INFO(inst) ((inst) + 0x00000043), 0x00000200 +#define BF_DPATH3_MEM_SEL1_1_INFO(inst) ((inst) + 0x00000043), 0x00000202 +#define BF_DPATH3_MEM_SEL2_1_INFO(inst) ((inst) + 0x00000043), 0x00000204 + +#define REG_DPATH0_MEM_SEL_2_ADDR(inst) ((inst) + 0x00000044) +#define BF_DPATH0_MEM_SEL0_2_INFO(inst) ((inst) + 0x00000044), 0x00000200 +#define BF_DPATH0_MEM_SEL1_2_INFO(inst) ((inst) + 0x00000044), 0x00000202 +#define BF_DPATH0_MEM_SEL2_2_INFO(inst) ((inst) + 0x00000044), 0x00000204 + +#define REG_DPATH1_MEM_SEL_2_ADDR(inst) ((inst) + 0x00000045) +#define BF_DPATH1_MEM_SEL0_2_INFO(inst) ((inst) + 0x00000045), 0x00000200 +#define BF_DPATH1_MEM_SEL1_2_INFO(inst) ((inst) + 0x00000045), 0x00000202 +#define BF_DPATH1_MEM_SEL2_2_INFO(inst) ((inst) + 0x00000045), 0x00000204 + +#define REG_DPATH2_MEM_SEL_2_ADDR(inst) ((inst) + 0x00000046) +#define BF_DPATH2_MEM_SEL0_2_INFO(inst) ((inst) + 0x00000046), 0x00000200 +#define BF_DPATH2_MEM_SEL1_2_INFO(inst) ((inst) + 0x00000046), 0x00000202 +#define BF_DPATH2_MEM_SEL2_2_INFO(inst) ((inst) + 0x00000046), 0x00000204 + +#define REG_DPATH3_MEM_SEL_2_ADDR(inst) ((inst) + 0x00000047) +#define BF_DPATH3_MEM_SEL0_2_INFO(inst) ((inst) + 0x00000047), 0x00000200 +#define BF_DPATH3_MEM_SEL1_2_INFO(inst) ((inst) + 0x00000047), 0x00000202 +#define BF_DPATH3_MEM_SEL2_2_INFO(inst) ((inst) + 0x00000047), 0x00000204 + +#ifdef USE_PRIVATE_BF +#define REG_CFIR_CLK_OFFSET_WR_EN_ADDR(inst) ((inst) + 0x00000048) +#define BF_CLK_OFFSET_WR_EN_TXRX_CFIR_TOP_INFO(inst) ((inst) + 0x00000048), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CFIR_ENGCLK_PH0_OFFSET_ADDR(inst, n) ((inst) + 0x00000049 + 1 * (n)) +#define BF_ENGCLK_PH0_OFFSET_INFO(inst, n) ((inst) + 0x00000049 + 1 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CFIR_ENGCLK_PH4_OFFSET_ADDR(inst, n) ((inst) + 0x0000004D + 1 * (n)) +#define BF_ENGCLK_PH4_OFFSET_INFO(inst, n) ((inst) + 0x0000004D + 1 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_CFIR_IRQ_ENABLE_ADDR(inst) ((inst) + 0x00000051) +#define BF_IRQ_ENABLE_I_TXRX_CFIR_TOP_INFO(inst) ((inst) + 0x00000051), 0x00000100 +#define BF_IRQ_ENABLE_Q_TXRX_CFIR_TOP_INFO(inst) ((inst) + 0x00000051), 0x00000101 + +#define REG_CFIR_IRQ_STATUS_ADDR(inst) ((inst) + 0x00000052) +#define BF_IRQ_STATUS_I_TXRX_CFIR_TOP_INFO(inst) ((inst) + 0x00000052), 0x00000100 +#define BF_IRQ_STATUS_Q_TXRX_CFIR_TOP_INFO(inst) ((inst) + 0x00000052), 0x00000101 + +#endif /* __ADI_APOLLO_BF_TXRX_CFIR_TOP_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_txrx_coarse_nco.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_txrx_coarse_nco.h new file mode 100644 index 00000000000000..1e903a311330c3 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_txrx_coarse_nco.h @@ -0,0 +1,258 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:22 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_TXRX_COARSE_NCO_H__ +#define __ADI_APOLLO_BF_TXRX_COARSE_NCO_H__ + +/*============= D E F I N E S ==============*/ +#define RX_COARSE_NCO0_RX_SLICE_0_RX_DIGITAL0 0x60366000 +#define RX_COARSE_NCO1_RX_SLICE_0_RX_DIGITAL0 0x60367000 +#define RX_COARSE_NCO0_RX_SLICE_1_RX_DIGITAL0 0x60566000 +#define RX_COARSE_NCO1_RX_SLICE_1_RX_DIGITAL0 0x60567000 +#define RX_COARSE_NCO0_RX_SLICE_0_RX_DIGITAL1 0x60B66000 +#define RX_COARSE_NCO1_RX_SLICE_0_RX_DIGITAL1 0x60B67000 +#define RX_COARSE_NCO0_RX_SLICE_1_RX_DIGITAL1 0x60D66000 +#define RX_COARSE_NCO1_RX_SLICE_1_RX_DIGITAL1 0x60D67000 +#define TX_COARSE_NCO0_TX_SLICE_0_TX_DIGITAL0 0x61334000 +#define TX_COARSE_NCO1_TX_SLICE_0_TX_DIGITAL0 0x61335000 +#define TX_COARSE_NCO0_TX_SLICE_1_TX_DIGITAL0 0x61534000 +#define TX_COARSE_NCO1_TX_SLICE_1_TX_DIGITAL0 0x61535000 +#define TX_COARSE_NCO0_TX_SLICE_0_TX_DIGITAL1 0x61B34000 +#define TX_COARSE_NCO1_TX_SLICE_0_TX_DIGITAL1 0x61B35000 +#define TX_COARSE_NCO0_TX_SLICE_1_TX_DIGITAL1 0x61D34000 +#define TX_COARSE_NCO1_TX_SLICE_1_TX_DIGITAL1 0x61D35000 + +#define REG_DRC_DITHER_TXRX_COARSE_NCO_ADDR(inst) ((inst) + 0x00000006) +#define BF_DRC_AMP_DITHER_EN_INFO(inst) ((inst) + 0x00000006), 0x00000100 +#define BF_DRC_PHASE_DITHER_EN_INFO(inst) ((inst) + 0x00000006), 0x00000101 + +#define REG_TRIG_HOP_CTRL_ADDR(inst) ((inst) + 0x0000000F) +#define BF_AUTOFLIP_INCDIR_TXRX_COARSE_NCO_INFO(inst) ((inst) + 0x0000000F), 0x00000100 +#define BF_AUTO_INC_DECB_TXRX_COARSE_NCO_INFO(inst) ((inst) + 0x0000000F), 0x00000101 +#define BF_HOP_CTRL_INIT_TXRX_COARSE_NCO_INFO(inst) ((inst) + 0x0000000F), 0x00000102 +#define BF_NEXT_HOP_NUMBER_WR_EN_INFO(inst) ((inst) + 0x0000000F), 0x00000103 + +#define REG_TRIG_HOP_STATUS_ADDR(inst) ((inst) + 0x00000010) +#define BF_CHDIR_INT_STATUS_TXRX_COARSE_NCO_INFO(inst) ((inst) + 0x00000010), 0x00000100 +#define BF_HOP_INT_STATUS_TXRX_COARSE_NCO_INFO(inst) ((inst) + 0x00000010), 0x00000101 +#define BF_PROFILE_INT_OUT_INFO(inst) ((inst) + 0x00000010), 0x00000102 +#define BF_NEXT_HOP_PNDSTAT_INFO(inst) ((inst) + 0x00000010), 0x00000103 + +#define REG_TRIG_HOP_INT_CTRL_ADDR(inst) ((inst) + 0x00000011) +#define BF_HOP_INT_CLR_TXRX_COARSE_NCO_INFO(inst) ((inst) + 0x00000011), 0x00000100 +#define BF_HOP_INT_MASK_TXRX_COARSE_NCO_INFO(inst) ((inst) + 0x00000011), 0x00000101 + +#define REG_HOP_HIGHLIM_ADDR(inst) ((inst) + 0x00000012) +#define BF_HOP_HIGHLIM_INFO(inst) ((inst) + 0x00000012), 0x00000400 + +#define REG_HOP_LOWLIM_ADDR(inst) ((inst) + 0x00000013) +#define BF_HOP_LOWLIM_INFO(inst) ((inst) + 0x00000013), 0x00000400 + +#define REG_HOP_INT_NUM_ADDR(inst) ((inst) + 0x00000014) +#define BF_HOP_INT_NUM_INFO(inst) ((inst) + 0x00000014), 0x00000400 + +#define REG_NEXT_HOP_NUMBER_ADDR(inst) ((inst) + 0x00000015) +#define BF_NEXT_HOP_NUMBER_INFO(inst) ((inst) + 0x00000015), 0x00000400 + +#define REG_PROFILE_SEL_MODE_TXRX_COARSE_NCO_ADDR(inst) ((inst) + 0x00000016) +#define BF_PROFILE_SEL_MODE_TXRX_COARSE_NCO_INFO(inst) ((inst) + 0x00000016), 0x00000200 + +#define REG_DRC_NCO_CHAN_SEL_CTRL_ADDR(inst) ((inst) + 0x00000017) +#define BF_DRC_NCO_CHAN_SEL_MODE_INFO(inst) ((inst) + 0x00000017), 0x00000400 +#define BF_DRC_NCO_REGMAP_CHAN_SEL_INFO(inst) ((inst) + 0x00000017), 0x00000404 + +#define REG_DRC_PROFILE_UPDATE_CTRL_ADDR(inst) ((inst) + 0x00000018) +#define BF_DRC_PROFILE_UPDATE_INDEX_INFO(inst) ((inst) + 0x00000018), 0x00000400 + +#define REG_MXR_TEST_MODE_VALUE0_ADDR(inst) ((inst) + 0x00000026) +#define BF_MIXER_TEST_MODE_VAL_TXRX_COARSE_NCO_INFO(inst) ((inst) + 0x00000026), 0x00000E00 + +#define REG_MXR_TEST_MODE_VALUE1_ADDR(inst) ((inst) + 0x00000027) + +#define REG_FREQ_COHRNCE_CTRL_ADDR(inst) ((inst) + 0x00000028) +#define BF_FREQ_COHRNCE_TXRX_COARSE_NCO_INFO(inst) ((inst) + 0x00000028), 0x00000200 + +#define REG_COARSE_DRC_IF_ADDR(inst) ((inst) + 0x00000029) +#define BF_DRC_IF_MODE_TXRX_COARSE_NCO_INFO(inst) ((inst) + 0x00000029), 0x00000200 + +#define REG_COARSE_DRC_MIXER_CTRL_ADDR(inst) ((inst) + 0x0000002A) +#define BF_DRC_MIXER_SEL_INFO(inst) ((inst) + 0x0000002A), 0x00000100 +#define BF_CMPLX_MXR_SCALE_EN_INFO(inst) ((inst) + 0x0000002A), 0x00000101 + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_MXR_CLK_OFFSET_I0_ADDR(inst) ((inst) + 0x0000002C) +#define BF_COARSE_MXR_CLK_OFFSET_I0_INFO(inst) ((inst) + 0x0000002C), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_MXR_CLK_OFFSET_I1_ADDR(inst) ((inst) + 0x0000002D) +#define BF_COARSE_MXR_CLK_OFFSET_I1_INFO(inst) ((inst) + 0x0000002D), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_MXR_CLK_OFFSET_I2_ADDR(inst) ((inst) + 0x0000002E) +#define BF_COARSE_MXR_CLK_OFFSET_I2_INFO(inst) ((inst) + 0x0000002E), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_MXR_CLK_OFFSET_I3_ADDR(inst) ((inst) + 0x0000002F) +#define BF_COARSE_MXR_CLK_OFFSET_I3_INFO(inst) ((inst) + 0x0000002F), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_MXR_CLK_OFFSET_Q0_ADDR(inst) ((inst) + 0x00000030) +#define BF_COARSE_MXR_CLK_OFFSET_Q0_INFO(inst) ((inst) + 0x00000030), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_MXR_CLK_OFFSET_Q1_ADDR(inst) ((inst) + 0x00000031) +#define BF_COARSE_MXR_CLK_OFFSET_Q1_INFO(inst) ((inst) + 0x00000031), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_MXR_CLK_OFFSET_Q2_ADDR(inst) ((inst) + 0x00000032) +#define BF_COARSE_MXR_CLK_OFFSET_Q2_INFO(inst) ((inst) + 0x00000032), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_MXR_CLK_OFFSET_Q3_ADDR(inst) ((inst) + 0x00000033) +#define BF_COARSE_MXR_CLK_OFFSET_Q3_INFO(inst) ((inst) + 0x00000033), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_COARSE_DRC_CLK_BASE_OFFSET_ADDR(inst) ((inst) + 0x00000034) +#define BF_COARSE_DRC_BASE_OFFSET_INFO(inst) ((inst) + 0x00000034), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#define REG_COARSE_DRC_CTRL_ADDR(inst) ((inst) + 0x00000035) +#define BF_COARSE_DRC_EN_INFO(inst) ((inst) + 0x00000035), 0x00000100 +#ifdef USE_PRIVATE_BF +#define BF_COARSE_CLK_OFFSET_WR_EN_INFO(inst) ((inst) + 0x00000035), 0x00000101 +#endif /* USE_PRIVATE_BF */ +#define BF_CDRC_CLK_EN_INFO(inst) ((inst) + 0x00000035), 0x00000102 + +#define REG_ACTIVE_PROFILE_ADDR(inst) ((inst) + 0x00000036) +#define BF_ACTIVE_PROFILE_INFO(inst) ((inst) + 0x00000036), 0x00000400 + +#define REG_PCT_RST_CTRL_TXRX_COARSE_NCO_ADDR(inst) ((inst) + 0x00000038) +#define BF_TS_RST_MODE_TXRX_COARSE_NCO_INFO(inst) ((inst) + 0x00000038), 0x00000100 +#define BF_SPI_TS_RST_TXRX_COARSE_NCO_INFO(inst) ((inst) + 0x00000038), 0x00000103 + +#define REG_PCT_RST_STATUS_TXRX_COARSE_NCO_ADDR(inst) ((inst) + 0x00000039) +#define BF_RST_DONE_TXRX_COARSE_NCO_INFO(inst) ((inst) + 0x00000039), 0x00000100 +#define BF_RST_DONE_CLR_TXRX_COARSE_NCO_INFO(inst) ((inst) + 0x00000039), 0x00000101 + +#define REG_PCT_RD_EN_TXRX_COARSE_NCO_ADDR(inst) ((inst) + 0x0000003A) +#define BF_TIMESTAMP_READ_EN_TXRX_COARSE_NCO_INFO(inst) ((inst) + 0x0000003A), 0x00000100 + +#define REG_PCT_STATUS0_TXRX_COARSE_NCO_ADDR(inst) ((inst) + 0x0000003B) +#define BF_TIMESTAMP_STATUS_TXRX_COARSE_NCO_INFO(inst) ((inst) + 0x0000003B), 0x00004000 + +#define REG_PCT_STATUS1_TXRX_COARSE_NCO_ADDR(inst) ((inst) + 0x0000003C) + +#define REG_PCT_STATUS2_TXRX_COARSE_NCO_ADDR(inst) ((inst) + 0x0000003D) + +#define REG_PCT_STATUS3_TXRX_COARSE_NCO_ADDR(inst) ((inst) + 0x0000003E) + +#define REG_PCT_STATUS4_TXRX_COARSE_NCO_ADDR(inst) ((inst) + 0x0000003F) + +#define REG_PCT_STATUS5_TXRX_COARSE_NCO_ADDR(inst) ((inst) + 0x00000040) + +#define REG_PCT_STATUS6_TXRX_COARSE_NCO_ADDR(inst) ((inst) + 0x00000041) + +#define REG_PCT_STATUS7_TXRX_COARSE_NCO_ADDR(inst) ((inst) + 0x00000042) + +#ifdef USE_PRIVATE_BF +#define REG_MOD_NCO_CTRL_TXRX_COARSE_NCO_ADDR(inst) ((inst) + 0x00000043) +#define BF_MOD_NCO_PHASE_ERROR_LOAD_ENABLE_TXRX_COARSE_NCO_INFO(inst) ((inst) + 0x00000043), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_MOD_NCO_LOAD_STATUS_ADDR(inst) ((inst) + 0x00000044) +#define BF_MOD_NCO_PHASE_ERROR_LOAD_STATUS_TXRX_COARSE_NCO_INFO(inst) ((inst) + 0x00000044), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#define REG_DRC_PHASE_INC_FRAC_A0_TXRX_COARSE_NCO_ADDR(inst) ((inst) + 0x00000045) +#define BF_DRC_PHASE_INC_FRAC_A_INFO(inst) ((inst) + 0x00000045), 0x00002000 + +#define REG_DRC_PHASE_INC_FRAC_A1_TXRX_COARSE_NCO_ADDR(inst) ((inst) + 0x00000046) + +#define REG_DRC_PHASE_INC_FRAC_A2_TXRX_COARSE_NCO_ADDR(inst) ((inst) + 0x00000047) + +#define REG_DRC_PHASE_INC_FRAC_A3_ADDR(inst) ((inst) + 0x00000048) + +#define REG_DRC_PHASE_INC_FRAC_B0_TXRX_COARSE_NCO_ADDR(inst) ((inst) + 0x00000049) +#define BF_DRC_PHASE_INC_FRAC_B_INFO(inst) ((inst) + 0x00000049), 0x00002000 + +#define REG_DRC_PHASE_INC_FRAC_B1_TXRX_COARSE_NCO_ADDR(inst) ((inst) + 0x0000004A) + +#define REG_DRC_PHASE_INC_FRAC_B2_TXRX_COARSE_NCO_ADDR(inst) ((inst) + 0x0000004B) + +#define REG_DRC_PHASE_INC_FRAC_B3_ADDR(inst) ((inst) + 0x0000004C) + +#ifdef USE_PRIVATE_BF +#define REG_MOD_NCO_LOAD_VALUE0_ADDR(inst) ((inst) + 0x0000004D) +#define BF_MOD_NCO_PHASE_ERROR_LOAD_VALUE_INFO(inst) ((inst) + 0x0000004D), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_MOD_NCO_LOAD_VALUE1_ADDR(inst) ((inst) + 0x0000004E) + +#define REG_MOD_NCO_LOAD_VALUE2_ADDR(inst) ((inst) + 0x0000004F) + +#define REG_MOD_NCO_LOAD_VALUE3_ADDR(inst) ((inst) + 0x00000050) + +#define REG_DRC_PHASE_INC0_ADDR(inst) ((inst) + 0x00000051) +#define BF_DRC_PHASE_INC_INFO(inst) ((inst) + 0x00000051), 0x00002000 + +#define REG_DRC_PHASE_INC1_ADDR(inst) ((inst) + 0x00000052) + +#define REG_DRC_PHASE_INC2_ADDR(inst) ((inst) + 0x00000053) + +#define REG_DRC_PHASE_INC3_ADDR(inst) ((inst) + 0x00000054) + +#define REG_DRC_PHASE_OFFSET0_ADDR(inst) ((inst) + 0x00000055) +#define BF_DRC_PHASE_OFFSET_INFO(inst) ((inst) + 0x00000055), 0x00002000 + +#define REG_DRC_PHASE_OFFSET1_ADDR(inst) ((inst) + 0x00000056) + +#define REG_DRC_PHASE_OFFSET2_ADDR(inst) ((inst) + 0x00000057) + +#define REG_DRC_PHASE_OFFSET3_ADDR(inst) ((inst) + 0x00000058) + +#define REG_DRC_ACTIVE_PHASE_INC0_TXRX_COARSE_NCO_ADDR(inst) ((inst) + 0x00000059) +#define BF_DRC_ACTIVE_PHASE_INC_INFO(inst) ((inst) + 0x00000059), 0x00002000 + +#define REG_DRC_ACTIVE_PHASE_INC1_TXRX_COARSE_NCO_ADDR(inst) ((inst) + 0x0000005A) + +#define REG_DRC_ACTIVE_PHASE_INC2_TXRX_COARSE_NCO_ADDR(inst) ((inst) + 0x0000005B) + +#define REG_DRC_ACTIVE_PHASE_INC3_TXRX_COARSE_NCO_ADDR(inst) ((inst) + 0x0000005C) + +#define REG_DRC_ACTIVE_PHASE_OFFSET0_TXRX_COARSE_NCO_ADDR(inst) ((inst) + 0x0000005D) +#define BF_DRC_ACTIVE_PHASE_OFFSET_INFO(inst) ((inst) + 0x0000005D), 0x00002000 + +#define REG_DRC_ACTIVE_PHASE_OFFSET1_TXRX_COARSE_NCO_ADDR(inst) ((inst) + 0x0000005E) + +#define REG_DRC_ACTIVE_PHASE_OFFSET2_TXRX_COARSE_NCO_ADDR(inst) ((inst) + 0x0000005F) + +#define REG_DRC_ACTIVE_PHASE_OFFSET3_TXRX_COARSE_NCO_ADDR(inst) ((inst) + 0x00000060) + +#define REG_DRC_MOD_NCO_PROFILE_UPDATE_ADDR(inst) ((inst) + 0x00000061) +#define BF_DRC_MOD_NCO_PROFILE_UPDATE_INFO(inst) ((inst) + 0x00000061), 0x00000100 + +#define REG_TRIG_RESET_EN_ADDR(inst) ((inst) + 0x00000062) +#define BF_TRIG_RESET_EN_INFO(inst) ((inst) + 0x00000062), 0x00000100 + +#endif /* __ADI_APOLLO_BF_TXRX_COARSE_NCO_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_txrx_enable.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_txrx_enable.h new file mode 100644 index 00000000000000..c9fa57dd392179 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_txrx_enable.h @@ -0,0 +1,73 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:22 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_TXRX_ENABLE_H__ +#define __ADI_APOLLO_BF_TXRX_ENABLE_H__ + +/*============= D E F I N E S ==============*/ +#define TXRX_ENABLE_RX_DIGITAL0 0x60020000 +#define TXRX_ENABLE_RX_DIGITAL1 0x60820000 +#define TXRX_ENABLE_TX_SLICE_0_TX_DIGITAL0 0x6120A000 +#define TXRX_ENABLE_TX_SLICE_1_TX_DIGITAL0 0x6140A000 +#define TXRX_ENABLE_TX_SLICE_0_TX_DIGITAL1 0x61A0A000 +#define TXRX_ENABLE_TX_SLICE_1_TX_DIGITAL1 0x61C0A000 + +#define REG_TXRX_ENABLE_CTRL_ADDR(inst, n) ((inst) + 0x00000000 + 15 * (n)) +#define BF_ENABLE_POL_INFO(inst, n) ((inst) + 0x00000000 + 15 * (n)), 0x00000100 +#define BF_ENABLE_SPI_INFO(inst, n) ((inst) + 0x00000000 + 15 * (n)), 0x00000101 +#define BF_ENABLE_SPIEN_INFO(inst, n) ((inst) + 0x00000000 + 15 * (n)), 0x00000102 + +#define REG_SLICE_SEL_ADDR(inst, n) ((inst) + 0x00000001 + 15 * (n)) +#define BF_SLICE_SEL_INFO(inst, n) ((inst) + 0x00000001 + 15 * (n)), 0x00000400 + +#define REG_LINX_SEL_ADDR(inst, n) ((inst) + 0x00000002 + 15 * (n)) +#define BF_LINX_SEL_INFO(inst, n) ((inst) + 0x00000002 + 15 * (n)), 0x00000400 + +#define REG_PFILT_SEL_ADDR(inst, n) ((inst) + 0x00000003 + 15 * (n)) +#define BF_PFILT_SEL_INFO(inst, n) ((inst) + 0x00000003 + 15 * (n)), 0x00000200 + +#define REG_CDUC_CDDC_SEL_ADDR(inst, n) ((inst) + 0x00000004 + 15 * (n)) +#define BF_CDUC_CDDC_SEL_INFO(inst, n) ((inst) + 0x00000004 + 15 * (n)), 0x00000400 + +#define REG_FDUC_FDDC_SEL_ADDR(inst, n) ((inst) + 0x00000005 + 15 * (n)) +#define BF_FDUC_FDDC_SEL_INFO(inst, n) ((inst) + 0x00000005 + 15 * (n)), 0x00000800 + +#define REG_CFIR_SEL_ADDR(inst, n) ((inst) + 0x00000006 + 15 * (n)) +#define BF_CFIR_SEL_INFO(inst, n) ((inst) + 0x00000006 + 15 * (n)), 0x00000200 + +#define REG_FSRC_SEL_ADDR(inst, n) ((inst) + 0x00000007 + 15 * (n)) +#define BF_FSRC_SEL_INFO(inst, n) ((inst) + 0x00000007 + 15 * (n)), 0x00000200 + +#define REG_JRX_JTX_LINK_SEL_ADDR(inst, n) ((inst) + 0x00000008 + 15 * (n)) +#define BF_JRX_JTX_LINK_SEL_INFO(inst, n) ((inst) + 0x00000008 + 15 * (n)), 0x00000200 + +#define REG_JRX_JTX_PHY_SEL0_ADDR(inst, n) ((inst) + 0x00000009 + 15 * (n)) +#define BF_JRX_JTX_PHY_SEL_INFO(inst, n) ((inst) + 0x00000009 + 15 * (n)), 0x00000C00 + +#define REG_JRX_JTX_PHY_SEL1_ADDR(inst, n) ((inst) + 0x0000000A + 15 * (n)) + +#define REG_MODSW_SEL_ADDR(inst, n) ((inst) + 0x0000000B + 15 * (n)) +#define BF_MODSW_SEL_INFO(inst, n) ((inst) + 0x0000000B + 15 * (n)), 0x00000100 + +#define REG_INVSINC_SEL_ADDR(inst, n) ((inst) + 0x0000000C + 15 * (n)) +#define BF_INVSINC_SEL_INFO(inst, n) ((inst) + 0x0000000C + 15 * (n)), 0x00000400 + +#define REG_GAIN_SEL_ADDR(inst, n) ((inst) + 0x0000000D + 15 * (n)) +#define BF_GAIN_SEL_INFO(inst, n) ((inst) + 0x0000000D + 15 * (n)), 0x00000400 + +#define REG_SRD_SEL_ADDR(inst, n) ((inst) + 0x0000000E + 15 * (n)) +#define BF_SRD_SEL_INFO(inst, n) ((inst) + 0x0000000E + 15 * (n)), 0x00000400 + +#endif /* __ADI_APOLLO_BF_TXRX_ENABLE_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_txrx_fine_nco.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_txrx_fine_nco.h new file mode 100644 index 00000000000000..adafceb38a5697 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_txrx_fine_nco.h @@ -0,0 +1,654 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:23 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_TXRX_FINE_NCO_H__ +#define __ADI_APOLLO_BF_TXRX_FINE_NCO_H__ + +/*============= D E F I N E S ==============*/ +#define RX_FINE_NCO0_RX_SLICE_0_RX_DIGITAL0 0x603AA000 +#define RX_FINE_NCO1_RX_SLICE_0_RX_DIGITAL0 0x603AB000 +#define RX_FINE_NCO2_RX_SLICE_0_RX_DIGITAL0 0x603AC000 +#define RX_FINE_NCO3_RX_SLICE_0_RX_DIGITAL0 0x603AD000 +#define RX_FINE_NCO0_RX_SLICE_1_RX_DIGITAL0 0x605AA000 +#define RX_FINE_NCO1_RX_SLICE_1_RX_DIGITAL0 0x605AB000 +#define RX_FINE_NCO2_RX_SLICE_1_RX_DIGITAL0 0x605AC000 +#define RX_FINE_NCO3_RX_SLICE_1_RX_DIGITAL0 0x605AD000 +#define RX_FINE_NCO0_RX_SLICE_0_RX_DIGITAL1 0x60BAA000 +#define RX_FINE_NCO1_RX_SLICE_0_RX_DIGITAL1 0x60BAB000 +#define RX_FINE_NCO2_RX_SLICE_0_RX_DIGITAL1 0x60BAC000 +#define RX_FINE_NCO3_RX_SLICE_0_RX_DIGITAL1 0x60BAD000 +#define RX_FINE_NCO0_RX_SLICE_1_RX_DIGITAL1 0x60DAA000 +#define RX_FINE_NCO1_RX_SLICE_1_RX_DIGITAL1 0x60DAB000 +#define RX_FINE_NCO2_RX_SLICE_1_RX_DIGITAL1 0x60DAC000 +#define RX_FINE_NCO3_RX_SLICE_1_RX_DIGITAL1 0x60DAD000 +#define TX_FINE_NCO0_TX_SLICE_0_TX_DIGITAL0 0x61309000 +#define TX_FINE_NCO1_TX_SLICE_0_TX_DIGITAL0 0x6130A000 +#define TX_FINE_NCO2_TX_SLICE_0_TX_DIGITAL0 0x6130B000 +#define TX_FINE_NCO3_TX_SLICE_0_TX_DIGITAL0 0x6130C000 +#define TX_FINE_NCO0_TX_SLICE_1_TX_DIGITAL0 0x61509000 +#define TX_FINE_NCO1_TX_SLICE_1_TX_DIGITAL0 0x6150A000 +#define TX_FINE_NCO2_TX_SLICE_1_TX_DIGITAL0 0x6150B000 +#define TX_FINE_NCO3_TX_SLICE_1_TX_DIGITAL0 0x6150C000 +#define TX_FINE_NCO0_TX_SLICE_0_TX_DIGITAL1 0x61B09000 +#define TX_FINE_NCO1_TX_SLICE_0_TX_DIGITAL1 0x61B0A000 +#define TX_FINE_NCO2_TX_SLICE_0_TX_DIGITAL1 0x61B0B000 +#define TX_FINE_NCO3_TX_SLICE_0_TX_DIGITAL1 0x61B0C000 +#define TX_FINE_NCO0_TX_SLICE_1_TX_DIGITAL1 0x61D09000 +#define TX_FINE_NCO1_TX_SLICE_1_TX_DIGITAL1 0x61D0A000 +#define TX_FINE_NCO2_TX_SLICE_1_TX_DIGITAL1 0x61D0B000 +#define TX_FINE_NCO3_TX_SLICE_1_TX_DIGITAL1 0x61D0C000 + +#define REG_FINE_NCO_CLK_CTRL_ADDR(inst) ((inst) + 0x00000000) +#define BF_FINE_DRC_EN0_INFO(inst) ((inst) + 0x00000000), 0x00000100 +#ifdef USE_PRIVATE_BF +#define BF_CLK_OFFSET_WR_EN_TXRX_FINE_NCO_INFO(inst) ((inst) + 0x00000000), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_FDRC_CLK_EN_INFO(inst) ((inst) + 0x00000000), 0x00000103 + +#ifdef USE_PRIVATE_BF +#define REG_FINE_BASE_OFFSET_TXRX_FINE_NCO_ADDR(inst) ((inst) + 0x00000001) +#define BF_DRC_BASE_OFFSET_INFO(inst) ((inst) + 0x00000001), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FINE_I_MXR_OFFSET_ADDR(inst) ((inst) + 0x00000002) +#define BF_FINE_I_MXR_OFFSET_INFO(inst) ((inst) + 0x00000002), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FINE_Q_MXR_OFFSET_ADDR(inst) ((inst) + 0x00000003) +#define BF_FINE_Q_MXR_OFFSET_INFO(inst) ((inst) + 0x00000003), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_FINE_MXR_CTRL_ADDR(inst) ((inst) + 0x00000004) +#define BF_DRC_IF_MODE_TXRX_FINE_NCO_INFO(inst) ((inst) + 0x00000004), 0x00000200 +#define BF_DRC_MXR_SEL_INFO(inst) ((inst) + 0x00000004), 0x00000102 +#define BF_CMPLX_MXR_MULT_SCALE_EN_INFO(inst) ((inst) + 0x00000004), 0x00000103 + +#ifdef USE_PRIVATE_BF +#define REG_ARAMP_INC_DEC_PROFNUM_ADDR(inst) ((inst) + 0x00000005) +#define BF_ARAMP_INC_PROFNUM_INFO(inst) ((inst) + 0x00000005), 0x00000400 +#define BF_ARAMP_DEC_PROFNUM_INFO(inst) ((inst) + 0x00000005), 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FRAMP_ARAMP_DIR_ADDR(inst) ((inst) + 0x00000006) +#define BF_FRAMP_DIR_INFO(inst) ((inst) + 0x00000006), 0x00000100 +#define BF_FRAMP_DIR_AUTOFLIP_INFO(inst) ((inst) + 0x00000006), 0x00000101 +#define BF_ARAMP_DIR_INFO(inst) ((inst) + 0x00000006), 0x00000102 +#define BF_ARAMP_DIR_AUTOFLIP_INFO(inst) ((inst) + 0x00000006), 0x00000103 +#define BF_SYMM_ARAMP_INFO(inst) ((inst) + 0x00000006), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FRAMP_INC_PROFNUM_ADDR(inst) ((inst) + 0x00000007) +#define BF_FRAMP_INC_PROFNUM_INFO(inst) ((inst) + 0x00000007), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FRAMP_DEC_PROFNUM_ADDR(inst) ((inst) + 0x00000008) +#define BF_FRAMP_DEC_PROFNUM_INFO(inst) ((inst) + 0x00000008), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARAMP_SCALE_EN_ADDR(inst) ((inst) + 0x00000015) +#define BF_ARAMP_SCALE_EN_INFO(inst) ((inst) + 0x00000015), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARAMP_UPDTRATE0_ADDR(inst) ((inst) + 0x00000016) +#define BF_ARAMP_UPDTRATE0_INFO(inst) ((inst) + 0x00000016), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_ARAMP_UPDTRATE1_ADDR(inst) ((inst) + 0x00000017) +#define BF_ARAMP_UPDTRATE1_INFO(inst) ((inst) + 0x00000017), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_AUTOFLIP_INCDIR_ADDR(inst) ((inst) + 0x00000018) +#define BF_AUTOFLIP_INCDIR_TXRX_FINE_NCO_INFO(inst) ((inst) + 0x00000018), 0x00000600 + +#define REG_AUTO_INC_DECB_ADDR(inst) ((inst) + 0x00000019) +#define BF_AUTO_INC_DECB_TXRX_FINE_NCO_INFO(inst) ((inst) + 0x00000019), 0x00000600 + +#define REG_CHDIR_INT_STATUS_ADDR(inst) ((inst) + 0x0000001A) +#define BF_CHDIR_INT_STATUS_TXRX_FINE_NCO_INFO(inst) ((inst) + 0x0000001A), 0x00000600 + +#define REG_DRC_ACTIVE_PHASE_INC0_TXRX_FINE_NCO_ADDR(inst) ((inst) + 0x0000001B) +#define BF_DRC0_ACTIVE_PHASE_INC_INFO(inst) ((inst) + 0x0000001B), 0x00003000 + +#define REG_DRC_ACTIVE_PHASE_INC1_TXRX_FINE_NCO_ADDR(inst) ((inst) + 0x0000001C) + +#define REG_DRC_ACTIVE_PHASE_INC2_TXRX_FINE_NCO_ADDR(inst) ((inst) + 0x0000001D) + +#define REG_DRC_ACTIVE_PHASE_INC3_TXRX_FINE_NCO_ADDR(inst) ((inst) + 0x0000001E) + +#define REG_DRC_ACTIVE_PHASE_INC4_ADDR(inst) ((inst) + 0x0000001F) + +#define REG_DRC_ACTIVE_PHASE_INC5_ADDR(inst) ((inst) + 0x00000020) + +#define REG_DRC_ACTIVE_PHASE_OFFSET0_TXRX_FINE_NCO_ADDR(inst) ((inst) + 0x00000021) +#define BF_DRC0_ACTIVE_PHASE_OFFSET_INFO(inst) ((inst) + 0x00000021), 0x00003000 + +#define REG_DRC_ACTIVE_PHASE_OFFSET1_TXRX_FINE_NCO_ADDR(inst) ((inst) + 0x00000022) + +#define REG_DRC_ACTIVE_PHASE_OFFSET2_TXRX_FINE_NCO_ADDR(inst) ((inst) + 0x00000023) + +#define REG_DRC_ACTIVE_PHASE_OFFSET3_TXRX_FINE_NCO_ADDR(inst) ((inst) + 0x00000024) + +#define REG_DRC_ACTIVE_PHASE_OFFSET4_ADDR(inst) ((inst) + 0x00000025) + +#define REG_DRC_ACTIVE_PHASE_OFFSET5_ADDR(inst) ((inst) + 0x00000026) + +#define REG_DRC_DITHER_TXRX_FINE_NCO_ADDR(inst) ((inst) + 0x00000027) +#define BF_DRC0_AMP_DITHER_EN_INFO(inst) ((inst) + 0x00000027), 0x00000100 +#define BF_DRC0_PHASE_DITHER_EN_INFO(inst) ((inst) + 0x00000027), 0x00000101 + +#define REG_DRC_PHASE_INC_FRAC_A0_TXRX_FINE_NCO_ADDR(inst) ((inst) + 0x00000028) +#define BF_DRC0_PHASE_INC_FRAC_A_INFO(inst) ((inst) + 0x00000028), 0x00001800 + +#define REG_DRC_PHASE_INC_FRAC_A1_TXRX_FINE_NCO_ADDR(inst) ((inst) + 0x00000029) + +#define REG_DRC_PHASE_INC_FRAC_A2_TXRX_FINE_NCO_ADDR(inst) ((inst) + 0x0000002A) + +#define REG_DRC_PHASE_INC_FRAC_B0_TXRX_FINE_NCO_ADDR(inst) ((inst) + 0x0000002E) +#define BF_DRC0_PHASE_INC_FRAC_B_INFO(inst) ((inst) + 0x0000002E), 0x00001800 + +#define REG_DRC_PHASE_INC_FRAC_B1_TXRX_FINE_NCO_ADDR(inst) ((inst) + 0x0000002F) + +#define REG_DRC_PHASE_INC_FRAC_B2_TXRX_FINE_NCO_ADDR(inst) ((inst) + 0x00000030) + +#define REG_DUTY_CYCLE0_ADDR(inst) ((inst) + 0x00000034) +#define BF_DUTY_CYCLE0_INFO(inst) ((inst) + 0x00000034), 0x00000800 + +#define REG_DUTY_CYCLE1_ADDR(inst) ((inst) + 0x00000035) +#define BF_DUTY_CYCLE1_INFO(inst) ((inst) + 0x00000035), 0x00000800 + +#define REG_NCO_COHRENCE_CTRL_ADDR(inst) ((inst) + 0x00000036) +#define BF_FREQ_COHRNCE_TXRX_FINE_NCO_INFO(inst) ((inst) + 0x00000036), 0x00000200 +#ifdef USE_PRIVATE_BF +#define BF_FJMP_COHRNCE_INFO(inst) ((inst) + 0x00000036), 0x00000202 +#endif /* USE_PRIVATE_BF */ +#ifdef USE_PRIVATE_BF +#define BF_FSTOP_COHRNCE_INFO(inst) ((inst) + 0x00000036), 0x00000204 +#endif /* USE_PRIVATE_BF */ +#define BF_NCORST_COHRNCE_INFO(inst) ((inst) + 0x00000036), 0x00000106 + +#define REG_INTERRUPT_OUT_ADDR(inst) ((inst) + 0x00000037) +#define BF_INTERRUPT_OUT_INFO(inst) ((inst) + 0x00000037), 0x00000100 +#ifdef USE_PRIVATE_BF +#define BF_FRMP_ERR_INTRPT_INFO(inst) ((inst) + 0x00000037), 0x00000101 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FRAMP_ERR_INTRP_CLR_ADDR(inst) ((inst) + 0x00000038) +#define BF_FRMP_ERR_INTRPT_CLR_INFO(inst) ((inst) + 0x00000038), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#define REG_GPIO_HOP_ADDR(inst) ((inst) + 0x00000039) +#define BF_GPIO_ALL_HOP_INFO(inst) ((inst) + 0x00000039), 0x00000100 +#define BF_TXRX_GPIOSHARE_INFO(inst) ((inst) + 0x00000039), 0x00000101 + +#ifdef USE_PRIVATE_BF +#define REG_HOP_AMP0_ADDR(inst) ((inst) + 0x0000003A) +#define BF_HOP_AMP0_INFO(inst) ((inst) + 0x0000003A), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_HOP_AMP1_ADDR(inst) ((inst) + 0x0000003B) +#define BF_HOP_AMP1_INFO(inst) ((inst) + 0x0000003B), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_HOP_AMP_INCR0_ADDR(inst) ((inst) + 0x0000003C) +#define BF_HOP_AMP_INCR0_INFO(inst) ((inst) + 0x0000003C), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_HOP_AMP_INCR1_ADDR(inst) ((inst) + 0x0000003D) +#define BF_HOP_AMP_INCR1_INFO(inst) ((inst) + 0x0000003D), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_HOP_CTRL_ADDR(inst) ((inst) + 0x0000003E) +#define BF_HOP_MODE_EN_INFO(inst) ((inst) + 0x0000003E), 0x00000100 +#define BF_HOP_MODE_INFO(inst) ((inst) + 0x0000003E), 0x00000301 +#define BF_HOP_CTRL_INIT_TXRX_FINE_NCO_INFO(inst) ((inst) + 0x0000003E), 0x00000104 + +#ifdef USE_PRIVATE_BF +#define REG_HOP_FDECR0_ADDR(inst) ((inst) + 0x0000003F) +#define BF_HOP_FDECR0_INFO(inst) ((inst) + 0x0000003F), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_HOP_FDECR1_ADDR(inst) ((inst) + 0x00000040) +#define BF_HOP_FDECR1_INFO(inst) ((inst) + 0x00000040), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_HOP_FDECR2_ADDR(inst) ((inst) + 0x00000041) +#define BF_HOP_FDECR2_INFO(inst) ((inst) + 0x00000041), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_HOP_FDECR3_ADDR(inst) ((inst) + 0x00000042) +#define BF_HOP_FDECR3_INFO(inst) ((inst) + 0x00000042), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_HOP_FINCR0_ADDR(inst) ((inst) + 0x00000043) +#define BF_HOP_FINCR0_INFO(inst) ((inst) + 0x00000043), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_HOP_FINCR1_ADDR(inst) ((inst) + 0x00000044) +#define BF_HOP_FINCR1_INFO(inst) ((inst) + 0x00000044), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_HOP_FINCR2_ADDR(inst) ((inst) + 0x00000045) +#define BF_HOP_FINCR2_INFO(inst) ((inst) + 0x00000045), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_HOP_FINCR3_ADDR(inst) ((inst) + 0x00000046) +#define BF_HOP_FINCR3_INFO(inst) ((inst) + 0x00000046), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_HOP_HIGHLIMIT_PR0_ADDR(inst) ((inst) + 0x00000047) +#define BF_HOP_HIGHLIMIT_PR0_INFO(inst) ((inst) + 0x00000047), 0x00000600 + +#ifdef USE_PRIVATE_BF +#define REG_HOP_HIGHLIMIT_PR1_ADDR(inst) ((inst) + 0x00000048) +#define BF_HOP_HIGHLIMIT_PR1_INFO(inst) ((inst) + 0x00000048), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#define REG_HOP_HIGHLIMIT_PR2_ADDR(inst) ((inst) + 0x00000049) +#define BF_HOP_HIGHLIMIT_PR2_INFO(inst) ((inst) + 0x00000049), 0x00000600 + +#ifdef USE_PRIVATE_BF +#define REG_HOP_HIGHLIMIT_PR3_ADDR(inst) ((inst) + 0x0000004A) +#define BF_HOP_HIGHLIMIT_PR3_INFO(inst) ((inst) + 0x0000004A), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_HOP_HIGHLIMIT_PR4_ADDR(inst) ((inst) + 0x0000004B) +#define BF_HOP_HIGHLIMIT_PR4_INFO(inst) ((inst) + 0x0000004B), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_HOP_HIGHLIMIT_PR5_ADDR(inst) ((inst) + 0x0000004C) +#define BF_HOP_HIGHLIMIT_PR5_INFO(inst) ((inst) + 0x0000004C), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#define REG_HOP_INTRPT_PR0_ADDR(inst) ((inst) + 0x0000004D) +#define BF_HOP_INT_NUM0_INFO(inst) ((inst) + 0x0000004D), 0x00000600 +#define BF_HOP_INT_MASK_TXRX_FINE_NCO_INFO(inst) ((inst) + 0x0000004D), 0x00000606 +#define BF_HOP_INT_CLR_TXRX_FINE_NCO_INFO(inst) ((inst) + 0x0000004D), 0x00000607 + +#ifdef USE_PRIVATE_BF +#define REG_HOP_INTRPT_PR1_ADDR(inst) ((inst) + 0x0000004E) +#define BF_HOP_INT_NUM1_INFO(inst) ((inst) + 0x0000004E), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#define REG_HOP_INTRPT_PR2_ADDR(inst) ((inst) + 0x0000004F) +#define BF_HOP_INT_NUM2_INFO(inst) ((inst) + 0x0000004F), 0x00000600 + +#ifdef USE_PRIVATE_BF +#define REG_HOP_INTRPT_PR3_ADDR(inst) ((inst) + 0x00000050) +#define BF_HOP_INT_NUM3_INFO(inst) ((inst) + 0x00000050), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_HOP_INTRPT_PR4_ADDR(inst) ((inst) + 0x00000051) +#define BF_HOP_INT_NUM4_INFO(inst) ((inst) + 0x00000051), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_HOP_INTRPT_PR5_ADDR(inst) ((inst) + 0x00000052) +#define BF_HOP_INT_NUM5_INFO(inst) ((inst) + 0x00000052), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#define REG_HOP_INT_STATUS_ADDR(inst) ((inst) + 0x00000053) +#define BF_HOP_INT_STATUS_TXRX_FINE_NCO_INFO(inst) ((inst) + 0x00000053), 0x00000600 + +#ifdef USE_PRIVATE_BF +#define REG_HOP_JMP_HIGH0_ADDR(inst) ((inst) + 0x00000054) +#define BF_HOP_JMP_HIGH0_INFO(inst) ((inst) + 0x00000054), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_HOP_JMP_HIGH1_ADDR(inst) ((inst) + 0x00000055) +#define BF_HOP_JMP_HIGH1_INFO(inst) ((inst) + 0x00000055), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_HOP_JMP_HIGH2_ADDR(inst) ((inst) + 0x00000056) +#define BF_HOP_JMP_HIGH2_INFO(inst) ((inst) + 0x00000056), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_HOP_JMP_HIGH3_ADDR(inst) ((inst) + 0x00000057) +#define BF_HOP_JMP_HIGH3_INFO(inst) ((inst) + 0x00000057), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_HOP_JMP_LOW0_ADDR(inst) ((inst) + 0x00000058) +#define BF_HOP_JMP_LOW0_INFO(inst) ((inst) + 0x00000058), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_HOP_JMP_LOW1_ADDR(inst) ((inst) + 0x00000059) +#define BF_HOP_JMP_LOW1_INFO(inst) ((inst) + 0x00000059), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_HOP_JMP_LOW2_ADDR(inst) ((inst) + 0x0000005A) +#define BF_HOP_JMP_LOW2_INFO(inst) ((inst) + 0x0000005A), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_HOP_JMP_LOW3_ADDR(inst) ((inst) + 0x0000005B) +#define BF_HOP_JMP_LOW3_INFO(inst) ((inst) + 0x0000005B), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_HOP_LOWLIMIT_PR0_ADDR(inst) ((inst) + 0x0000005C) +#define BF_HOP_LOWLIMIT_PR0_INFO(inst) ((inst) + 0x0000005C), 0x00000600 + +#ifdef USE_PRIVATE_BF +#define REG_HOP_LOWLIMIT_PR1_ADDR(inst) ((inst) + 0x0000005D) +#define BF_HOP_LOWLIMIT_PR1_INFO(inst) ((inst) + 0x0000005D), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#define REG_HOP_LOWLIMIT_PR2_ADDR(inst) ((inst) + 0x0000005E) +#define BF_HOP_LOWLIMIT_PR2_INFO(inst) ((inst) + 0x0000005E), 0x00000600 + +#ifdef USE_PRIVATE_BF +#define REG_HOP_LOWLIMIT_PR3_ADDR(inst) ((inst) + 0x0000005F) +#define BF_HOP_LOWLIMIT_PR3_INFO(inst) ((inst) + 0x0000005F), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_HOP_LOWLIMIT_PR4_ADDR(inst) ((inst) + 0x00000060) +#define BF_HOP_LOWLIMIT_PR4_INFO(inst) ((inst) + 0x00000060), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_HOP_LOWLIMIT_PR5_ADDR(inst) ((inst) + 0x00000061) +#define BF_HOP_LOWLIMIT_PR5_INFO(inst) ((inst) + 0x00000061), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#define REG_HOP_PHASE_INC0_ADDR(inst) ((inst) + 0x00000062) +#define BF_HOP_PHASE_INC0_INFO(inst) ((inst) + 0x00000062), 0x00000800 + +#define REG_HOP_PHASE_INC1_ADDR(inst) ((inst) + 0x00000063) +#define BF_HOP_PHASE_INC1_INFO(inst) ((inst) + 0x00000063), 0x00000800 + +#define REG_HOP_PHASE_INC2_ADDR(inst) ((inst) + 0x00000064) +#define BF_HOP_PHASE_INC2_INFO(inst) ((inst) + 0x00000064), 0x00000800 + +#define REG_HOP_PHASE_INC3_ADDR(inst) ((inst) + 0x00000065) +#define BF_HOP_PHASE_INC3_INFO(inst) ((inst) + 0x00000065), 0x00000800 + +#define REG_HOP_PHASE_OFFSET0_ADDR(inst) ((inst) + 0x00000066) +#define BF_HOP_PHASE_OFFSET0_INFO(inst) ((inst) + 0x00000066), 0x00000800 + +#define REG_HOP_PHASE_OFFSET1_ADDR(inst) ((inst) + 0x00000067) +#define BF_HOP_PHASE_OFFSET1_INFO(inst) ((inst) + 0x00000067), 0x00000800 + +#define REG_HOP_PROFILE_PAGE_ADDR(inst) ((inst) + 0x00000068) +#define BF_HOP_PROFILE_PAGE_INFO(inst) ((inst) + 0x00000068), 0x00000600 + +#ifdef USE_PRIVATE_BF +#define REG_HOP_STOP_FREQ0_ADDR(inst) ((inst) + 0x00000069) +#define BF_HOP_STOP_FREQ0_INFO(inst) ((inst) + 0x00000069), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_HOP_STOP_FREQ1_ADDR(inst) ((inst) + 0x0000006A) +#define BF_HOP_STOP_FREQ1_INFO(inst) ((inst) + 0x0000006A), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_HOP_STOP_FREQ2_ADDR(inst) ((inst) + 0x0000006B) +#define BF_HOP_STOP_FREQ2_INFO(inst) ((inst) + 0x0000006B), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_HOP_STOP_FREQ3_ADDR(inst) ((inst) + 0x0000006C) +#define BF_HOP_STOP_FREQ3_INFO(inst) ((inst) + 0x0000006C), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_HOP_TIME0_ADDR(inst) ((inst) + 0x0000006D) +#define BF_HOP_TIME0_INFO(inst) ((inst) + 0x0000006D), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_HOP_TIME1_ADDR(inst) ((inst) + 0x0000006E) +#define BF_HOP_TIME1_INFO(inst) ((inst) + 0x0000006E), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_MAIN_NCO_CTRL_ADDR(inst) ((inst) + 0x0000006F) +#define BF_MAIN2_NCO_SEL_INFO(inst) ((inst) + 0x0000006F), 0x00000100 +#define BF_MAIN_NCO_SYNC_UPDT_EN_INFO(inst) ((inst) + 0x0000006F), 0x00000101 +#define BF_MAIN_NCO_SYNC_UPDT_INFO(inst) ((inst) + 0x0000006F), 0x00000102 + +#define REG_MAIN2_PHASE_INC0_ADDR(inst) ((inst) + 0x00000070) +#define BF_MAIN2_PHASE_INC_INFO(inst) ((inst) + 0x00000070), 0x00003000 + +#define REG_MAIN2_PHASE_INC1_ADDR(inst) ((inst) + 0x00000071) + +#define REG_MAIN2_PHASE_INC2_ADDR(inst) ((inst) + 0x00000072) + +#define REG_MAIN2_PHASE_INC3_ADDR(inst) ((inst) + 0x00000073) + +#define REG_MAIN2_PHASE_INC4_ADDR(inst) ((inst) + 0x00000074) + +#define REG_MAIN2_PHASE_INC5_ADDR(inst) ((inst) + 0x00000075) + +#define REG_MAIN2_PHASE_OFFSET0_ADDR(inst) ((inst) + 0x00000076) +#define BF_MAIN2_PHASE_OFFSET_INFO(inst) ((inst) + 0x00000076), 0x00003000 + +#define REG_MAIN2_PHASE_OFFSET1_ADDR(inst) ((inst) + 0x00000077) + +#define REG_MAIN2_PHASE_OFFSET2_ADDR(inst) ((inst) + 0x00000078) + +#define REG_MAIN2_PHASE_OFFSET3_ADDR(inst) ((inst) + 0x00000079) + +#define REG_MAIN2_PHASE_OFFSET4_ADDR(inst) ((inst) + 0x0000007A) + +#define REG_MAIN2_PHASE_OFFSET5_ADDR(inst) ((inst) + 0x0000007B) + +#ifdef USE_PRIVATE_BF +#define REG_MAIN_AMP0_ADDR(inst) ((inst) + 0x0000007C) +#define BF_MAIN_AMP0_INFO(inst) ((inst) + 0x0000007C), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_MAIN_AMP1_ADDR(inst) ((inst) + 0x0000007D) +#define BF_MAIN_AMP1_INFO(inst) ((inst) + 0x0000007D), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_MAIN_PHASE_INC0_ADDR(inst) ((inst) + 0x0000007E) +#define BF_MAIN_PHASE_INC_INFO(inst) ((inst) + 0x0000007E), 0x00003000 + +#define REG_MAIN_PHASE_INC1_ADDR(inst) ((inst) + 0x0000007F) + +#define REG_MAIN_PHASE_INC2_ADDR(inst) ((inst) + 0x00000080) + +#define REG_MAIN_PHASE_INC3_ADDR(inst) ((inst) + 0x00000081) + +#define REG_MAIN_PHASE_INC4_ADDR(inst) ((inst) + 0x00000082) + +#define REG_MAIN_PHASE_INC5_ADDR(inst) ((inst) + 0x00000083) + +#define REG_MAIN_PHASE_OFFSET0_ADDR(inst) ((inst) + 0x00000084) +#define BF_MAIN_PHASE_OFFSET_INFO(inst) ((inst) + 0x00000084), 0x00003000 + +#define REG_MAIN_PHASE_OFFSET1_ADDR(inst) ((inst) + 0x00000085) + +#define REG_MAIN_PHASE_OFFSET2_ADDR(inst) ((inst) + 0x00000086) + +#define REG_MAIN_PHASE_OFFSET3_ADDR(inst) ((inst) + 0x00000087) + +#define REG_MAIN_PHASE_OFFSET4_ADDR(inst) ((inst) + 0x00000088) + +#define REG_MAIN_PHASE_OFFSET5_ADDR(inst) ((inst) + 0x00000089) + +#ifdef USE_PRIVATE_BF +#define REG_MOD_NCO_LOAD_CTRL_ADDR(inst) ((inst) + 0x0000008A) +#define BF_MOD_NCO_PHASE_ERROR_LOAD_ENABLE_TXRX_FINE_NCO_INFO(inst) ((inst) + 0x0000008A), 0x00000100 +#define BF_MOD_NCO_PHASE_ERROR_LOAD_STATUS_TXRX_FINE_NCO_INFO(inst) ((inst) + 0x0000008A), 0x00000101 +#endif /* USE_PRIVATE_BF */ + +#define REG_MOD_NCO_CTRL_TXRX_FINE_NCO_ADDR(inst) ((inst) + 0x0000008B) +#define BF_MOD_PARAM_SCH_INFO(inst) ((inst) + 0x0000008B), 0x00000200 +#define BF_USE_FRC_AB_INFO(inst) ((inst) + 0x0000008B), 0x00000102 + +#define REG_NEXT_HOP_NUMBER_PR0_ADDR(inst) ((inst) + 0x0000008C) +#define BF_NEXT_HOP_NUMBER_PR0_INFO(inst) ((inst) + 0x0000008C), 0x00000600 + +#ifdef USE_PRIVATE_BF +#define REG_NEXT_HOP_NUMBER_PR1_ADDR(inst) ((inst) + 0x0000008D) +#define BF_NEXT_HOP_NUMBER_PR1_INFO(inst) ((inst) + 0x0000008D), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#define REG_NEXT_HOP_NUMBER_PR2_ADDR(inst) ((inst) + 0x0000008E) +#define BF_NEXT_HOP_NUMBER_PR2_INFO(inst) ((inst) + 0x0000008E), 0x00000600 + +#ifdef USE_PRIVATE_BF +#define REG_NEXT_HOP_NUMBER_PR3_ADDR(inst) ((inst) + 0x0000008F) +#define BF_NEXT_HOP_NUMBER_PR3_INFO(inst) ((inst) + 0x0000008F), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_NEXT_HOP_NUMBER_PR4_ADDR(inst) ((inst) + 0x00000090) +#define BF_NEXT_HOP_NUMBER_PR4_INFO(inst) ((inst) + 0x00000090), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_NEXT_HOP_NUMBER_PR5_ADDR(inst) ((inst) + 0x00000091) +#define BF_NEXT_HOP_NUMBER_PR5_INFO(inst) ((inst) + 0x00000091), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#define REG_PROFILE_GRP_COUNTER_VAL_PR0_ADDR(inst) ((inst) + 0x00000092) +#define BF_PROFILE_GRP_COUNTER_VAL_INFO(inst) ((inst) + 0x00000092), 0x00002400 + +#define REG_PROFILE_GRP_COUNTER_VAL_PR1_ADDR(inst) ((inst) + 0x00000093) + +#define REG_PROFILE_GRP_COUNTER_VAL_PR2_ADDR(inst) ((inst) + 0x00000094) + +#define REG_PROFILE_GRP_COUNTER_VAL_PR3_ADDR(inst) ((inst) + 0x00000095) + +#define REG_PROFILE_GRP_COUNTER_VAL_PR4_ADDR(inst) ((inst) + 0x00000096) + +#define REG_PROFILE_GRP_COUNTER_VAL_PR5_ADDR(inst) ((inst) + 0x00000097) + +#define REG_PROFILE_SEL_MODE_TXRX_FINE_NCO_ADDR(inst) ((inst) + 0x00000098) +#define BF_PROFILE_SEL_MODE_TXRX_FINE_NCO_INFO(inst) ((inst) + 0x00000098), 0x00000400 + +#define REG_REGMAP_HOPPROF_ADDR(inst) ((inst) + 0x00000099) +#define BF_REGMAP_HOPPROF_INFO(inst) ((inst) + 0x00000099), 0x00000600 + +#define REG_SAW_POSNEG_SEL_ADDR(inst) ((inst) + 0x0000009A) +#define BF_SAW_POSNEG_SEL_INFO(inst) ((inst) + 0x0000009A), 0x00000100 + +#define REG_SQW_HIGH0_ADDR(inst) ((inst) + 0x0000009C) +#define BF_SQW_HIGH0_INFO(inst) ((inst) + 0x0000009C), 0x00000800 + +#define REG_SQW_HIGH1_ADDR(inst) ((inst) + 0x0000009D) +#define BF_SQW_HIGH1_INFO(inst) ((inst) + 0x0000009D), 0x00000800 + +#define REG_SQW_LOW0_ADDR(inst) ((inst) + 0x0000009E) +#define BF_SQW_LOW0_INFO(inst) ((inst) + 0x0000009E), 0x00000800 + +#define REG_SQW_LOW1_ADDR(inst) ((inst) + 0x0000009F) +#define BF_SQW_LOW1_INFO(inst) ((inst) + 0x0000009F), 0x00000800 + +#define REG_TRIG_HOP_SEL0_ADDR(inst) ((inst) + 0x000000A0) +#define BF_TRIG_HOP_SEL0_INFO(inst) ((inst) + 0x000000A0), 0x00000600 + +#ifdef USE_PRIVATE_BF +#define REG_TRIG_HOP_SEL1_ADDR(inst) ((inst) + 0x000000A1) +#define BF_TRIG_HOP_SEL1_INFO(inst) ((inst) + 0x000000A1), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TRIG_HOP_SEL2_ADDR(inst) ((inst) + 0x000000A2) +#define BF_TRIG_HOP_SEL2_INFO(inst) ((inst) + 0x000000A2), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TRIG_HOP_SEL3_ADDR(inst) ((inst) + 0x000000A3) +#define BF_TRIG_HOP_SEL3_INFO(inst) ((inst) + 0x000000A3), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TRIG_HOP_SEL4_ADDR(inst) ((inst) + 0x000000A4) +#define BF_TRIG_HOP_SEL4_INFO(inst) ((inst) + 0x000000A4), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TRIG_HOP_SEL5_ADDR(inst) ((inst) + 0x000000A5) +#define BF_TRIG_HOP_SEL5_INFO(inst) ((inst) + 0x000000A5), 0x00000600 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_WAVE_OFFSET0_ADDR(inst) ((inst) + 0x000000A6) +#define BF_WAVE_OFFSET0_INFO(inst) ((inst) + 0x000000A6), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_WAVE_OFFSET1_ADDR(inst) ((inst) + 0x000000A7) +#define BF_WAVE_OFFSET1_INFO(inst) ((inst) + 0x000000A7), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_WAVE_SEL_ADDR(inst) ((inst) + 0x000000A8) +#define BF_WAVE_SEL_INFO(inst) ((inst) + 0x000000A8), 0x00000200 + +#define REG_PCT_RST_CTRL_TXRX_FINE_NCO_ADDR(inst) ((inst) + 0x000000A9) +#define BF_TS_RST_MODE_TXRX_FINE_NCO_INFO(inst) ((inst) + 0x000000A9), 0x00000100 +#define BF_SPI_TS_RST_TXRX_FINE_NCO_INFO(inst) ((inst) + 0x000000A9), 0x00000101 + +#define REG_PCT_RST_STATUS_TXRX_FINE_NCO_ADDR(inst) ((inst) + 0x000000AA) +#define BF_RST_DONE_TXRX_FINE_NCO_INFO(inst) ((inst) + 0x000000AA), 0x00000100 +#define BF_RST_DONE_CLR_TXRX_FINE_NCO_INFO(inst) ((inst) + 0x000000AA), 0x00000101 + +#define REG_PCT_RD_EN_TXRX_FINE_NCO_ADDR(inst) ((inst) + 0x000000AB) +#define BF_TIMESTAMP_READ_EN_TXRX_FINE_NCO_INFO(inst) ((inst) + 0x000000AB), 0x00000100 + +#define REG_PCT_STATUS0_TXRX_FINE_NCO_ADDR(inst) ((inst) + 0x000000AC) +#define BF_TIMESTAMP_STATUS_TXRX_FINE_NCO_INFO(inst) ((inst) + 0x000000AC), 0x00004000 + +#define REG_PCT_STATUS1_TXRX_FINE_NCO_ADDR(inst) ((inst) + 0x000000AD) + +#define REG_PCT_STATUS2_TXRX_FINE_NCO_ADDR(inst) ((inst) + 0x000000AE) + +#define REG_PCT_STATUS3_TXRX_FINE_NCO_ADDR(inst) ((inst) + 0x000000AF) + +#define REG_PCT_STATUS4_TXRX_FINE_NCO_ADDR(inst) ((inst) + 0x000000B0) + +#define REG_PCT_STATUS5_TXRX_FINE_NCO_ADDR(inst) ((inst) + 0x000000B1) + +#define REG_PCT_STATUS6_TXRX_FINE_NCO_ADDR(inst) ((inst) + 0x000000B2) + +#define REG_PCT_STATUS7_TXRX_FINE_NCO_ADDR(inst) ((inst) + 0x000000B3) + +#define REG_MXR_TEST_MODE_VAL0_ADDR(inst) ((inst) + 0x000000B4) +#define BF_MIXER_TEST_MODE_VAL_TXRX_FINE_NCO_INFO(inst) ((inst) + 0x000000B4), 0x00001000 + +#define REG_MXR_TEST_MODE_VAL1_ADDR(inst) ((inst) + 0x000000B5) + +#endif /* __ADI_APOLLO_BF_TXRX_FINE_NCO_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_txrx_fsrc.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_txrx_fsrc.h new file mode 100644 index 00000000000000..81d6481b7e456c --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_txrx_fsrc.h @@ -0,0 +1,234 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:22 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_TXRX_FSRC_H__ +#define __ADI_APOLLO_BF_TXRX_FSRC_H__ + +/*============= D E F I N E S ==============*/ +#define RX_FSRC_RX_SLICE_0_RX_DIGITAL0 0x603A6000 +#define RX_FSRC_RX_SLICE_1_RX_DIGITAL0 0x605A6000 +#define RX_FSRC_RX_SLICE_0_RX_DIGITAL1 0x60BA6000 +#define RX_FSRC_RX_SLICE_1_RX_DIGITAL1 0x60DA6000 +#define TX_FSRC_TX_SLICE_0_TX_DIGITAL0 0x61310000 +#define TX_FSRC_TX_SLICE_1_TX_DIGITAL0 0x61510000 +#define TX_FSRC_TX_SLICE_0_TX_DIGITAL1 0x61B10000 +#define TX_FSRC_TX_SLICE_1_TX_DIGITAL1 0x61D10000 + +#define REG_FSRC_RATE_INT_0_ADDR(inst) ((inst) + 0x00000001) +#define BF_FSRC_RATE_INT_INFO(inst) ((inst) + 0x00000001), 0x00003000 + +#define REG_FSRC_RATE_INT_1_ADDR(inst) ((inst) + 0x00000002) + +#define REG_FSRC_RATE_INT_2_ADDR(inst) ((inst) + 0x00000003) + +#define REG_FSRC_RATE_INT_3_ADDR(inst) ((inst) + 0x00000004) + +#define REG_FSRC_RATE_INT_4_ADDR(inst) ((inst) + 0x00000005) + +#define REG_FSRC_RATE_INT_5_ADDR(inst) ((inst) + 0x00000006) + +#define REG_FSRC_RATE_FRAC_A_0_ADDR(inst) ((inst) + 0x00000007) +#define BF_FSRC_RATE_FRAC_A_INFO(inst) ((inst) + 0x00000007), 0x00003000 + +#define REG_FSRC_RATE_FRAC_A_1_ADDR(inst) ((inst) + 0x00000008) + +#define REG_FSRC_RATE_FRAC_A_2_ADDR(inst) ((inst) + 0x00000009) + +#define REG_FSRC_RATE_FRAC_A_3_ADDR(inst) ((inst) + 0x0000000A) + +#define REG_FSRC_RATE_FRAC_A_4_ADDR(inst) ((inst) + 0x0000000B) + +#define REG_FSRC_RATE_FRAC_A_5_ADDR(inst) ((inst) + 0x0000000C) + +#define REG_FSRC_RATE_FRAC_B_0_ADDR(inst) ((inst) + 0x0000000D) +#define BF_FSRC_RATE_FRAC_B_INFO(inst) ((inst) + 0x0000000D), 0x00003000 + +#define REG_FSRC_RATE_FRAC_B_1_ADDR(inst) ((inst) + 0x0000000E) + +#define REG_FSRC_RATE_FRAC_B_2_ADDR(inst) ((inst) + 0x0000000F) + +#define REG_FSRC_RATE_FRAC_B_3_ADDR(inst) ((inst) + 0x00000010) + +#define REG_FSRC_RATE_FRAC_B_4_ADDR(inst) ((inst) + 0x00000011) + +#define REG_FSRC_RATE_FRAC_B_5_ADDR(inst) ((inst) + 0x00000012) + +#define REG_SAMPLE_FRAC_DELAY_0_ADDR(inst) ((inst) + 0x00000013) +#define BF_SAMPLE_FRAC_DELAY_INFO(inst) ((inst) + 0x00000013), 0x00001000 + +#define REG_SAMPLE_FRAC_DELAY_1_ADDR(inst) ((inst) + 0x00000014) + +#ifdef USE_PRIVATE_BF +#define REG_FSRC_ROUND_WORD_0_ADDR(inst) ((inst) + 0x00000015) +#define BF_FSRC_ROUND_WORD_INFO(inst) ((inst) + 0x00000015), 0x00001800 +#endif /* USE_PRIVATE_BF */ + +#define REG_FSRC_ROUND_WORD_1_ADDR(inst) ((inst) + 0x00000016) + +#define REG_FSRC_ROUND_WORD_2_ADDR(inst) ((inst) + 0x00000017) + +#ifdef USE_PRIVATE_BF +#define REG_SAMPLE_FRAC_DELAY_CTRL_ADDR(inst) ((inst) + 0x00000018) +#define BF_FRAC_DELAY_SAMPLE_SHIFT_FIX_INFO(inst) ((inst) + 0x00000018), 0x00000100 +#define BF_SAMPLE_FRAC_DELAY_LOAD_INFO(inst) ((inst) + 0x00000018), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#define REG_GAIN_REDUCTION_0_ADDR(inst) ((inst) + 0x00000019) +#define BF_GAIN_REDUCTION_INFO(inst) ((inst) + 0x00000019), 0x00000C00 + +#define REG_GAIN_REDUCTION_1_ADDR(inst) ((inst) + 0x0000001A) + +#define REG_PTR_SYNCRSTVAL_CTRL_ADDR(inst) ((inst) + 0x0000001B) +#ifdef USE_PRIVATE_BF +#define BF_PTR_SYNCRSTVAL_INFO(inst) ((inst) + 0x0000001B), 0x00000600 +#endif /* USE_PRIVATE_BF */ +#define BF_PTR_SYNCRSTVAL_REGMAP_OVERWRITE_INFO(inst) ((inst) + 0x0000001B), 0x00000107 + +#define REG_FSRC_CTRL_ADDR(inst) ((inst) + 0x0000001C) +#define BF_FSRC_EN0_INFO(inst) ((inst) + 0x0000001C), 0x00000100 +#define BF_FSRC_EN1_INFO(inst) ((inst) + 0x0000001C), 0x00000101 +#define BF_FSRC_BYPASS_INFO(inst) ((inst) + 0x0000001C), 0x00000102 +#define BF_FSRC_4T4R_SPLIT_INFO(inst) ((inst) + 0x0000001C), 0x00000103 +#define BF_FSRC_DITHER_EN_INFO(inst) ((inst) + 0x0000001C), 0x00000105 +#define BF_FSRC_DATA_MULT_DITHER_EN_INFO(inst) ((inst) + 0x0000001C), 0x00000106 +#define BF_FSRC_1X_MODE_INFO(inst) ((inst) + 0x0000001C), 0x00000107 + +#ifdef USE_PRIVATE_BF +#define REG_CLOCK_GATE_EN_GEN_OFFSET_ADDR(inst) ((inst) + 0x0000001D) +#define BF_FIXED_CLK_GATE_EN_GEN_OFFSET_INFO(inst) ((inst) + 0x0000001D), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_CLOCK_GATE_GEN_CTRL_ADDR(inst) ((inst) + 0x0000001E) +#define BF_CLKGATE_GEN_WAIT_FOR_SYNC_INFO(inst) ((inst) + 0x0000001E), 0x00000100 +#define BF_CLKGATE_GEN_RESET_INFO(inst) ((inst) + 0x0000001E), 0x00000101 +#endif /* USE_PRIVATE_BF */ + +#define REG_FSRC_IRQ_EN_ADDR(inst) ((inst) + 0x0000001F) +#define BF_EN_FSRC_CH0_OVR_I_IRQ_INFO(inst) ((inst) + 0x0000001F), 0x00000100 +#define BF_EN_FSRC_CH0_OVR_Q_IRQ_INFO(inst) ((inst) + 0x0000001F), 0x00000101 +#define BF_EN_FSRC_CH1_OVR_I_IRQ_INFO(inst) ((inst) + 0x0000001F), 0x00000102 +#define BF_EN_FSRC_CH1_OVR_Q_IRQ_INFO(inst) ((inst) + 0x0000001F), 0x00000103 + +#define REG_FSRC_OVERFLOW_ADDR(inst) ((inst) + 0x00000020) +#define BF_IRQ_CH0_FSRC_I_OVER_FLOW_INFO(inst) ((inst) + 0x00000020), 0x00000100 +#define BF_IRQ_CH0_FSRC_Q_OVER_FLOW_INFO(inst) ((inst) + 0x00000020), 0x00000101 +#define BF_IRQ_CH1_FSRC_I_OVER_FLOW_INFO(inst) ((inst) + 0x00000020), 0x00000102 +#define BF_IRQ_CH1_FSRC_Q_OVER_FLOW_INFO(inst) ((inst) + 0x00000020), 0x00000103 +#define BF_IRQ_FSRC_OVER_FLOW_ALL_INFO(inst) ((inst) + 0x00000020), 0x00000104 + +#ifdef USE_PRIVATE_BF +#define REG_FSRC_BASE_OFFSET_ADDR(inst) ((inst) + 0x00000021) +#define BF_FSRC_BASE_OFFSET_INFO(inst) ((inst) + 0x00000021), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FSRC_CLK_OFFSET_WR_EN_ADDR(inst) ((inst) + 0x00000022) +#define BF_FSRC_CLK_GEN_PHASE_OFFSET_WR_EN_INFO(inst) ((inst) + 0x00000022), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FSRC_CLK_DEBUG_ADDR(inst) ((inst) + 0x00000023) +#define BF_DEBUG_FSRC_CLKOFF_EN_INFO(inst) ((inst) + 0x00000023), 0x00000700 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FSRC_I_IN_OFFSET_PH0_ADDR(inst) ((inst) + 0x00000024) +#define BF_FSRC_I_IN_OFFSET_PH0_INFO(inst) ((inst) + 0x00000024), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FSRC_I_IN_OFFSET_PH1_ADDR(inst) ((inst) + 0x00000025) +#define BF_FSRC_I_IN_OFFSET_PH1_INFO(inst) ((inst) + 0x00000025), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FSRC_I_OUT_OFFSET_PH0_ADDR(inst) ((inst) + 0x00000026) +#define BF_FSRC_I_OUT_OFFSET_PH0_INFO(inst) ((inst) + 0x00000026), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FSRC_I_OUT_OFFSET_PH1_ADDR(inst) ((inst) + 0x00000027) +#define BF_FSRC_I_OUT_OFFSET_PH1_INFO(inst) ((inst) + 0x00000027), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FSRC_Q_IN_OFFSET_PH0_ADDR(inst) ((inst) + 0x00000028) +#define BF_FSRC_Q_IN_OFFSET_PH0_INFO(inst) ((inst) + 0x00000028), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FSRC_Q_IN_OFFSET_PH1_ADDR(inst) ((inst) + 0x00000029) +#define BF_FSRC_Q_IN_OFFSET_PH1_INFO(inst) ((inst) + 0x00000029), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FSRC_Q_OUT_OFFSET_PH0_ADDR(inst) ((inst) + 0x0000002A) +#define BF_FSRC_Q_OUT_OFFSET_PH0_INFO(inst) ((inst) + 0x0000002A), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FSRC_Q_OUT_OFFSET_PH1_ADDR(inst) ((inst) + 0x0000002B) +#define BF_FSRC_Q_OUT_OFFSET_PH1_INFO(inst) ((inst) + 0x0000002B), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_TX_FSRC_MUX_CTRL_ADDR(inst) ((inst) + 0x0000002C) +#define BF_FSRC_IN_MUX_SEL_INFO(inst) ((inst) + 0x0000002C), 0x00000200 +#define BF_FSRC_OUT_MUX_SEL_INFO(inst) ((inst) + 0x0000002C), 0x00000202 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FSRC_Q_FILT_CTRL_ADDR(inst) ((inst) + 0x0000002D) +#define BF_FSRC_Q_FILT_FIFO_SYNC_CTRL_INFO(inst) ((inst) + 0x0000002D), 0x00000200 +#define BF_FSRC_Q_FILT_ROOT_CLK_CTRL_INFO(inst) ((inst) + 0x0000002D), 0x00000102 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FSRC_GATED_CLK_VALID_ADDR(inst) ((inst) + 0x0000002E) +#define BF_GATED_CLK_VALID_INFO(inst) ((inst) + 0x0000002E), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FSRC_BIST_CTRL_ADDR(inst) ((inst) + 0x00000030) +#define BF_FSRC_BIST_EN_INFO(inst) ((inst) + 0x00000030), 0x00000100 +#define BF_FSRC_BIST_INIT_INFO(inst) ((inst) + 0x00000030), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FSRC_BIST_EN_STATUS_ADDR(inst) ((inst) + 0x00000031) +#define BF_FSRC_BIST_EN_STATUS_INFO(inst) ((inst) + 0x00000031), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FSRC_BIST_CRC_LO_ADDR(inst) ((inst) + 0x00000032) +#define BF_FSRC_BIST_CRC_INFO(inst) ((inst) + 0x00000032), 0x00001000 +#endif /* USE_PRIVATE_BF */ + +#define REG_FSRC_BIST_CRC_HI_ADDR(inst) ((inst) + 0x00000033) + +#ifdef USE_PRIVATE_BF +#define REG_FSRC_NS_SEL_CTRL_ADDR(inst) ((inst) + 0x00000034) +#define BF_FSRC_NS_SEL_INFO(inst) ((inst) + 0x00000034), 0x00000200 +#define BF_FSRC_NS_SEL_OVERWRITE_INFO(inst) ((inst) + 0x00000034), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_FSRC_NS_READ_ADDR(inst) ((inst) + 0x00000035) +#define BF_FSRC_NS_RS_INFO(inst) ((inst) + 0x00000035), 0x00000300 +#define BF_FSRC_NS_SPLIT_INVALID_INFO(inst) ((inst) + 0x00000035), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#endif /* __ADI_APOLLO_BF_TXRX_FSRC_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_txrx_pfilt_coeff.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_txrx_pfilt_coeff.h new file mode 100644 index 00000000000000..bc956864150985 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_txrx_pfilt_coeff.h @@ -0,0 +1,47 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:22 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_TXRX_PFILT_COEFF_H__ +#define __ADI_APOLLO_BF_TXRX_PFILT_COEFF_H__ + +/*============= D E F I N E S ==============*/ +#define RX_PFILT_COEFF0_RX_SLICE_0_RX_DIGITAL0 0x60360000 +#define RX_PFILT_COEFF1_RX_SLICE_0_RX_DIGITAL0 0x60361000 +#define RX_PFILT_COEFF0_RX_SLICE_1_RX_DIGITAL0 0x60560000 +#define RX_PFILT_COEFF1_RX_SLICE_1_RX_DIGITAL0 0x60561000 +#define RX_PFILT_COEFF0_RX_SLICE_0_RX_DIGITAL1 0x60B60000 +#define RX_PFILT_COEFF1_RX_SLICE_0_RX_DIGITAL1 0x60B61000 +#define RX_PFILT_COEFF0_RX_SLICE_1_RX_DIGITAL1 0x60D60000 +#define RX_PFILT_COEFF1_RX_SLICE_1_RX_DIGITAL1 0x60D61000 +#define TX_PFILT_COEFF0_TX_SLICE_0_TX_DIGITAL0 0x61302000 +#define TX_PFILT_COEFF1_TX_SLICE_0_TX_DIGITAL0 0x61303000 +#define TX_PFILT_COEFF0_TX_SLICE_1_TX_DIGITAL0 0x61502000 +#define TX_PFILT_COEFF1_TX_SLICE_1_TX_DIGITAL0 0x61503000 +#define TX_PFILT_COEFF0_TX_SLICE_0_TX_DIGITAL1 0x61B02000 +#define TX_PFILT_COEFF1_TX_SLICE_0_TX_DIGITAL1 0x61B03000 +#define TX_PFILT_COEFF0_TX_SLICE_1_TX_DIGITAL1 0x61D02000 +#define TX_PFILT_COEFF1_TX_SLICE_1_TX_DIGITAL1 0x61D03000 + +#define REG_COEFF_0_LSB_ADDR(inst, n) ((inst) + 0x00000000 + 2 * (n)) +#define BF_COEFF_0_INFO(inst, n) ((inst) + 0x00000000 + 2 * (n)), 0x00001000 + +#define REG_COEFF_0_MSB_ADDR(inst, n) ((inst) + 0x00000001 + 2 * (n)) + +#define REG_COEFF_1_LSB_ADDR(inst, n) ((inst) + 0x00000040 + 2 * (n)) +#define BF_COEFF_1_INFO(inst, n) ((inst) + 0x00000040 + 2 * (n)), 0x00001000 + +#define REG_COEFF_1_MSB_ADDR(inst, n) ((inst) + 0x00000041 + 2 * (n)) + +#endif /* __ADI_APOLLO_BF_TXRX_PFILT_COEFF_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_txrx_pfilt_top.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_txrx_pfilt_top.h new file mode 100644 index 00000000000000..297c09d6843d81 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_txrx_pfilt_top.h @@ -0,0 +1,128 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:22 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_TXRX_PFILT_TOP_H__ +#define __ADI_APOLLO_BF_TXRX_PFILT_TOP_H__ + +/*============= D E F I N E S ==============*/ +#define RX_PFILT_TOP_RX_SLICE_0_RX_DIGITAL0 0x60362000 +#define RX_PFILT_TOP_RX_SLICE_1_RX_DIGITAL0 0x60562000 +#define RX_PFILT_TOP_RX_SLICE_0_RX_DIGITAL1 0x60B62000 +#define RX_PFILT_TOP_RX_SLICE_1_RX_DIGITAL1 0x60D62000 +#define TX_PFILT_TOP_TX_SLICE_0_TX_DIGITAL0 0x61304000 +#define TX_PFILT_TOP_TX_SLICE_1_TX_DIGITAL0 0x61504000 +#define TX_PFILT_TOP_TX_SLICE_0_TX_DIGITAL1 0x61B04000 +#define TX_PFILT_TOP_TX_SLICE_1_TX_DIGITAL1 0x61D04000 + +#define REG_PFIR_MODE_ADDR(inst, n) ((inst) + 0x0000000C + 1 * (n)) +#define BF_PFIR_I_MODE_INFO(inst, n) ((inst) + 0x0000000C + 1 * (n)), 0x00000400 +#define BF_PFIR_Q_MODE_INFO(inst, n) ((inst) + 0x0000000C + 1 * (n)), 0x00000404 + +#ifdef USE_PRIVATE_BF +#define REG_LEGACY_PFIR_I_GAIN_ADDR(inst, n) ((inst) + 0x0000000E + 1 * (n)) +#define BF_LEGACY_PFIR_IX_GAIN_INFO(inst, n) ((inst) + 0x0000000E + 1 * (n)), 0x00000300 +#define BF_LEGACY_PFIR_IY_GAIN_INFO(inst, n) ((inst) + 0x0000000E + 1 * (n)), 0x00000303 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_LEGACY_PFIR_Q_GAIN_ADDR(inst, n) ((inst) + 0x00000010 + 1 * (n)) +#define BF_LEGACY_PFIR_QX_GAIN_INFO(inst, n) ((inst) + 0x00000010 + 1 * (n)), 0x00000300 +#define BF_LEGACY_PFIR_QY_GAIN_INFO(inst, n) ((inst) + 0x00000010 + 1 * (n)), 0x00000303 +#endif /* USE_PRIVATE_BF */ + +#define REG_PFIR_BIST_CTRL_ADDR(inst, n) ((inst) + 0x00000012 + 1 * (n)) +#ifdef USE_PRIVATE_BF +#define BF_PFIR_BIST_EN_INFO(inst, n) ((inst) + 0x00000012 + 1 * (n)), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#ifdef USE_PRIVATE_BF +#define BF_PFIR_BIST_INIT_INFO(inst, n) ((inst) + 0x00000012 + 1 * (n)), 0x00000101 +#endif /* USE_PRIVATE_BF */ +#ifdef USE_PRIVATE_BF +#define BF_PFIR_BIST_EN_STATUS_INFO(inst, n) ((inst) + 0x00000012 + 1 * (n)), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#ifdef USE_PRIVATE_BF +#define BF_DITHER_DIS_INFO(inst, n) ((inst) + 0x00000012 + 1 * (n)), 0x00000103 +#endif /* USE_PRIVATE_BF */ +#define BF_OUTPUT_DITHER_EN_INFO(inst, n) ((inst) + 0x00000012 + 1 * (n)), 0x00000104 + +#ifdef USE_PRIVATE_BF +#define REG_DELAY_SETTING_ADDR(inst, n) ((inst) + 0x00000014 + 1 * (n)) +#define BF_DELAY_SETTING_INFO(inst, n) ((inst) + 0x00000014 + 1 * (n)), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_PFIR_COEFF_TRANSFER_ADDR(inst, n) ((inst) + 0x00000016 + 1 * (n)) +#define BF_PFIR_COEFF_TRANSFER_INFO(inst, n) ((inst) + 0x00000016 + 1 * (n)), 0x00000100 + +#ifdef USE_PRIVATE_BF +#define REG_PFIR_BIST_CRC_LSB_ADDR(inst, n) ((inst) + 0x00000018 + 1 * (n)) +#define BF_PFIR_BIST_CRC_INFO(inst, n) ((inst) + 0x00000018 + 1 * (n)), 0x00001000 +#endif /* USE_PRIVATE_BF */ + +#define REG_PFIR_BIST_CRC_MSB_ADDR(inst, n) ((inst) + 0x0000001A + 1 * (n)) + +#define REG_HC_PROG_DELAY_ADDR(inst, n) ((inst) + 0x0000001C + 1 * (n)) +#define BF_HC_PROG_DELAY_INFO(inst, n) ((inst) + 0x0000001C + 1 * (n)), 0x00000700 + +#define REG_MODE_AND_DATA_TYPE_SEL_ADDR(inst) ((inst) + 0x00000024) +#define BF_QUAD_MODE_INFO(inst) ((inst) + 0x00000024), 0x00000100 +#define BF_REAL_DATA_INFO(inst) ((inst) + 0x00000024), 0x00000101 +#define BF_MODE_SWITCH_INFO(inst) ((inst) + 0x00000024), 0x00000102 +#define BF_ADD_SUB_SEL_INFO(inst) ((inst) + 0x00000024), 0x00000103 + +#define REG_PFILT_TRIGGER_EN_ADDR(inst) ((inst) + 0x00000025) +#define BF_PFILT_TRIGGER_EN_INFO(inst) ((inst) + 0x00000025), 0x00000100 + +#define REG_PFILT_CONTROL_ADDR(inst) ((inst) + 0x00000026) +#define BF_EQ_GPIO_EN_INFO(inst) ((inst) + 0x00000026), 0x00000100 +#define BF_GPIO_CONFIG1_INFO(inst) ((inst) + 0x00000026), 0x00000101 +#define BF_DISABLE_ORX_INFO(inst) ((inst) + 0x00000026), 0x00000402 + +#define REG_RD_COEFF_PAGE_SEL_ADDR(inst, n) ((inst) + 0x00000027 + 1 * (n)) +#define BF_RD_COEFF_PAGE_SEL_INFO(inst, n) ((inst) + 0x00000027 + 1 * (n)), 0x00000200 + +#ifdef USE_PRIVATE_BF +#define REG_EIGER_MODE_ADDR(inst) ((inst) + 0x00000029) +#define BF_EIGER_MODE_INFO(inst) ((inst) + 0x00000029), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_PFIR_I_GAIN_ADDR(inst, n) ((inst) + 0x00000030 + 1 * (n)) +#define BF_PFIR_IX_GAIN_INFO(inst, n) ((inst) + 0x00000030 + 1 * (n)), 0x00000400 +#define BF_PFIR_IY_GAIN_INFO(inst, n) ((inst) + 0x00000030 + 1 * (n)), 0x00000404 + +#define REG_PFIR_Q_GAIN_ADDR(inst, n) ((inst) + 0x00000048 + 1 * (n)) +#define BF_PFIR_QX_GAIN_INFO(inst, n) ((inst) + 0x00000048 + 1 * (n)), 0x00000400 +#define BF_PFIR_QY_GAIN_INFO(inst, n) ((inst) + 0x00000048 + 1 * (n)), 0x00000404 + +#define REG_PFIR_IX_SCALAR_GAIN_ADDR(inst, n) ((inst) + 0x00000060 + 1 * (n)) +#define BF_PFIR_IX_SCALAR_GAIN_INFO(inst, n) ((inst) + 0x00000060 + 1 * (n)), 0x00000600 + +#define REG_PFIR_IY_SCALAR_GAIN_ADDR(inst, n) ((inst) + 0x00000078 + 1 * (n)) +#define BF_PFIR_IY_SCALAR_GAIN_INFO(inst, n) ((inst) + 0x00000078 + 1 * (n)), 0x00000600 + +#define REG_PFIR_QX_SCALAR_GAIN_ADDR(inst, n) ((inst) + 0x00000090 + 1 * (n)) +#define BF_PFIR_QX_SCALAR_GAIN_INFO(inst, n) ((inst) + 0x00000090 + 1 * (n)), 0x00000600 + +#define REG_PFIR_QY_SCALAR_GAIN_ADDR(inst, n) ((inst) + 0x00000108 + 1 * (n)) +#define BF_PFIR_QY_SCALAR_GAIN_INFO(inst, n) ((inst) + 0x00000108 + 1 * (n)), 0x00000600 + +#define REG_PFILT_IRQ_ENABLE_ADDR(inst) ((inst) + 0x00000110) +#define BF_IRQ_ENABLE_I_TXRX_PFILT_TOP_INFO(inst) ((inst) + 0x00000110), 0x00000100 +#define BF_IRQ_ENABLE_Q_TXRX_PFILT_TOP_INFO(inst) ((inst) + 0x00000110), 0x00000101 + +#define REG_PFILT_IRQ_STATUS_ADDR(inst) ((inst) + 0x00000111) +#define BF_IRQ_STATUS_I_TXRX_PFILT_TOP_INFO(inst) ((inst) + 0x00000111), 0x00000100 +#define BF_IRQ_STATUS_Q_TXRX_PFILT_TOP_INFO(inst) ((inst) + 0x00000111), 0x00000101 + +#endif /* __ADI_APOLLO_BF_TXRX_PFILT_TOP_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_txrx_postfsrc_reconf.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_txrx_postfsrc_reconf.h new file mode 100644 index 00000000000000..ee82de402c05ea --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_txrx_postfsrc_reconf.h @@ -0,0 +1,63 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:23 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_TXRX_POSTFSRC_RECONF_H__ +#define __ADI_APOLLO_BF_TXRX_POSTFSRC_RECONF_H__ + +/*============= D E F I N E S ==============*/ +#define TXRX_POSTFSRC_RECONF_RX_SLICE_0_RX_DIGITAL0 0x603AE000 +#define TXRX_POSTFSRC_RECONF_RX_SLICE_1_RX_DIGITAL0 0x605AE000 +#define TXRX_POSTFSRC_RECONF_RX_SLICE_0_RX_DIGITAL1 0x60BAE000 +#define TXRX_POSTFSRC_RECONF_RX_SLICE_1_RX_DIGITAL1 0x60DAE000 +#define TXRX_POSTFSRC_RECONF_TX_SLICE_0_TX_DIGITAL0 0x61317000 +#define TXRX_POSTFSRC_RECONF_TX_SLICE_1_TX_DIGITAL0 0x61517000 +#define TXRX_POSTFSRC_RECONF_TX_SLICE_0_TX_DIGITAL1 0x61B17000 +#define TXRX_POSTFSRC_RECONF_TX_SLICE_1_TX_DIGITAL1 0x61D17000 + +#define REG_POSTFSRC_RECONF_LCM0_ADDR(inst) ((inst) + 0x000002EB) +#define BF_POSTFSRC_LCM_INFO(inst) ((inst) + 0x000002EB), 0x00001000 + +#define REG_POSTFSRC_RECONF_LCM1_ADDR(inst) ((inst) + 0x000002EC) + +#ifdef USE_PRIVATE_BF +#define REG_POSTFSRC_SM_STATE_ADDR(inst) ((inst) + 0x000002F3) +#define BF_POSTFSRC_SM_STATE_INFO(inst) ((inst) + 0x000002F3), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#define REG_RECONFIG_RAMP_WIDTH_TXRX_POSTFSRC_RECONF_ADDR(inst) ((inst) + 0x000002F4) +#define BF_RECONFIG_RAMP_WIDTH_TXRX_POSTFSRC_RECONF_INFO(inst) ((inst) + 0x000002F4), 0x00000500 + +#ifdef USE_PRIVATE_BF +#define REG_RECONFIG_ERROR_STATUS_ADDR(inst) ((inst) + 0x000002F5) +#define BF_TIME_ERROR_STATUS_TXRX_POSTFSRC_RECONF_INFO(inst) ((inst) + 0x000002F5), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#define REG_POSTFSRC_NEWCLK_DLY_ADDR(inst) ((inst) + 0x000002F6) +#define BF_NEWCLK_DLY_TXRX_POSTFSRC_RECONF_INFO(inst) ((inst) + 0x000002F6), 0x00000500 + +#define REG_POSTFSRC_RECONFIG_DONE_ADDR(inst) ((inst) + 0x000002F7) +#define BF_RECONFIG_DONE_INFO(inst) ((inst) + 0x000002F7), 0x00000100 + +#ifdef USE_PRIVATE_BF +#define REG_POSTFSRC_FORCE_NEWCLK_ADDR(inst) ((inst) + 0x000002F8) +#define BF_FORCE_NEWCLK_TXRX_POSTFSRC_RECONF_INFO(inst) ((inst) + 0x000002F8), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_EXTRA_RECONFIG_DLY_ADDR(inst) ((inst) + 0x000002F9) +#define BF_EXTRA_RECONFIG_DLY_INFO(inst) ((inst) + 0x000002F9), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#endif /* __ADI_APOLLO_BF_TXRX_POSTFSRC_RECONF_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_txrx_prefsrc_reconf.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_txrx_prefsrc_reconf.h new file mode 100644 index 00000000000000..01f0e5a069326f --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_txrx_prefsrc_reconf.h @@ -0,0 +1,91 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:22 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_TXRX_PREFSRC_RECONF_H__ +#define __ADI_APOLLO_BF_TXRX_PREFSRC_RECONF_H__ + +/*============= D E F I N E S ==============*/ +#define TXRX_PREFSRC_RECONF_RX_SLICE_0_RX_DIGITAL0 0x6020A000 +#define TXRX_PREFSRC_RECONF_RX_SLICE_1_RX_DIGITAL0 0x6040A000 +#define TXRX_PREFSRC_RECONF_RX_SLICE_0_RX_DIGITAL1 0x60A0A000 +#define TXRX_PREFSRC_RECONF_RX_SLICE_1_RX_DIGITAL1 0x60C0A000 +#define TXRX_PREFSRC_RECONF_TX_SLICE_0_TX_DIGITAL0 0x6120B000 +#define TXRX_PREFSRC_RECONF_TX_SLICE_1_TX_DIGITAL0 0x6140B000 +#define TXRX_PREFSRC_RECONF_TX_SLICE_0_TX_DIGITAL1 0x61A0B000 +#define TXRX_PREFSRC_RECONF_TX_SLICE_1_TX_DIGITAL1 0x61C0B000 + +#define REG_PREFSRC_RECONF_SYNC_CTRL_ADDR(inst) ((inst) + 0x000002E8) +#ifdef USE_PRIVATE_BF +#define BF_FORCE_TS_SYNC_INFO(inst) ((inst) + 0x000002E8), 0x00000101 +#endif /* USE_PRIVATE_BF */ +#define BF_NONRESYNC_SYSREF_EN_INFO(inst) ((inst) + 0x000002E8), 0x00000102 +#define BF_TRIG_RECONF_MODE_INFO(inst) ((inst) + 0x000002E8), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_FORCE_SYNC_EN_INFO(inst) ((inst) + 0x000002E8), 0x00000104 +#endif /* USE_PRIVATE_BF */ + +#define REG_PREFSRC_RECONF_CTRL_ADDR(inst) ((inst) + 0x000002E9) +#define BF_CNCO_RESET_EN_INFO(inst) ((inst) + 0x000002E9), 0x00000101 +#define BF_TIMESTAMP_RESET_EN_INFO(inst) ((inst) + 0x000002E9), 0x00000102 +#define BF_RESYNC_EN_INFO(inst) ((inst) + 0x000002E9), 0x00000103 +#define BF_TZERO_COHERENCE_EN_INFO(inst) ((inst) + 0x000002E9), 0x00000104 +#define BF_FNCO_RESET_EN_INFO(inst) ((inst) + 0x000002E9), 0x00000105 + +#define REG_PREFSRC_RECONF_LCM0_ADDR(inst) ((inst) + 0x000002EA) +#define BF_PREFSRC_LCM_INFO(inst) ((inst) + 0x000002EA), 0x00000900 + +#define REG_PREFSRC_RECONF_LCM1_ADDR(inst) ((inst) + 0x000002EB) + +#ifdef USE_PRIVATE_BF +#define REG_PREFSRC_RECONF_ERROR_STATUS_ADDR(inst) ((inst) + 0x000002F1) +#define BF_RECONFIG_ERROR_STATUS_INFO(inst) ((inst) + 0x000002F1), 0x00000400 +#define BF_TIME_ERROR_STATUS_TXRX_PREFSRC_RECONF_INFO(inst) ((inst) + 0x000002F1), 0x00000105 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_PREFSRC_SM_STATE_ADDR(inst) ((inst) + 0x000002F2) +#define BF_PREFSRC_SM_STATE_INFO(inst) ((inst) + 0x000002F2), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_PREFSRC_TRIG_INP_CNT_ADDR(inst) ((inst) + 0x000002F4) +#define BF_TRIG_INPUT_COUNT_INFO(inst) ((inst) + 0x000002F4), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_PREFSRC_SYNC_INP_CNT_ADDR(inst) ((inst) + 0x000002F5) +#define BF_SYNC_INPUT_COUNT_INFO(inst) ((inst) + 0x000002F5), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#define REG_PREFSRC_RECONF_RESET_STATUS_ADDR(inst) ((inst) + 0x000002F6) +#define BF_TIMESTAMP_RESET_DONE_INFO(inst) ((inst) + 0x000002F6), 0x00000100 +#define BF_CNCO_RESET_DONE_INFO(inst) ((inst) + 0x000002F6), 0x00000101 +#define BF_FNCO_RESET_DONE_INFO(inst) ((inst) + 0x000002F6), 0x00000102 + +#define REG_RECONFIG_FLUSH_COUNT_ADDR(inst) ((inst) + 0x000002F7) +#define BF_RECONFIG_FLUSH_COUNT_INFO(inst) ((inst) + 0x000002F7), 0x00000500 + +#define REG_RECONFIG_RAMP_WIDTH_TXRX_PREFSRC_RECONF_ADDR(inst) ((inst) + 0x000002F8) +#define BF_RECONFIG_RAMP_WIDTH_TXRX_PREFSRC_RECONF_INFO(inst) ((inst) + 0x000002F8), 0x00000500 + +#define REG_PREFSRC_RECONF_NEWCLK_DLY_ADDR(inst) ((inst) + 0x000002F9) +#define BF_NEWCLK_DLY_TXRX_PREFSRC_RECONF_INFO(inst) ((inst) + 0x000002F9), 0x00000500 + +#ifdef USE_PRIVATE_BF +#define REG_PREFSRC_FORCE_NEWCLK_ADDR(inst) ((inst) + 0x000002FA) +#define BF_FORCE_NEWCLK_TXRX_PREFSRC_RECONF_INFO(inst) ((inst) + 0x000002FA), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#endif /* __ADI_APOLLO_BF_TXRX_PREFSRC_RECONF_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_txrx_streamproc_config.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_txrx_streamproc_config.h new file mode 100644 index 00000000000000..29981545f3d277 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_txrx_streamproc_config.h @@ -0,0 +1,34 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:22 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_TXRX_STREAMPROC_CONFIG_H__ +#define __ADI_APOLLO_BF_TXRX_STREAMPROC_CONFIG_H__ + +/*============= D E F I N E S ==============*/ +#define RX_STREAMPROC_CONFIG_RX_DIGITAL0 0x60022000 +#define RX_STREAMPROC_CONFIG_RX_DIGITAL1 0x60822000 +#define TX_STREAMPROC_CONFIG_TX_TOP_TX_DIGITAL0 0x61021000 +#define TX_STREAMPROC_CONFIG_TX_TOP_TX_DIGITAL1 0x61821000 + +#define REG_STREAMPROC_1US_COUNT_ADDR(inst) ((inst) + 0x00000000) +#define BF_REFERENCE_CLOCK_CYCLES_TXRX_STREAMPROC_CONFIG_INFO(inst) ((inst) + 0x00000000), 0x00000800 + +#define REG_STREAMPROC_REG_RD_DELAY_ADDR(inst) ((inst) + 0x00000001) +#define BF_STREAMPROC_REG_RD_DELAY_INFO(inst) ((inst) + 0x00000001), 0x00000400 + +#define REG_STREAMPROC_EVENT_TRIG_MASK_ADDR(inst) ((inst) + 0x00000002) +#define BF_STREAMPROC_EVENT_TRIG_MASK_INFO(inst) ((inst) + 0x00000002), 0x00000800 + +#endif /* __ADI_APOLLO_BF_TXRX_STREAMPROC_CONFIG_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_txrx_trigger_ts.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_txrx_trigger_ts.h new file mode 100644 index 00000000000000..52082eca4793f9 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_txrx_trigger_ts.h @@ -0,0 +1,155 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:22 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_TXRX_TRIGGER_TS_H__ +#define __ADI_APOLLO_BF_TXRX_TRIGGER_TS_H__ + +/*============= D E F I N E S ==============*/ +#define TXRX_TRIGGER_TS_RX_DIGITAL0 0x60021000 +#define TXRX_TRIGGER_TS_RX_DIGITAL1 0x60821000 +#define TXRX_TRIGGER_TS_TX_TOP_TX_DIGITAL0 0x61020000 +#define TXRX_TRIGGER_TS_TX_TOP_TX_DIGITAL1 0x61820000 + +#define REG_COUNT0_REG0_ADDR(inst) ((inst) + 0x00000000) +#define BF_COUNT0_REG0_INFO(inst) ((inst) + 0x00000000), 0x00000800 + +#define REG_COUNT0_REG1_ADDR(inst) ((inst) + 0x00000001) +#define BF_COUNT0_REG1_INFO(inst) ((inst) + 0x00000001), 0x00000800 + +#define REG_COUNT1_REG0_ADDR(inst) ((inst) + 0x00000002) +#define BF_COUNT1_REG0_INFO(inst) ((inst) + 0x00000002), 0x00000800 + +#define REG_COUNT1_REG1_ADDR(inst) ((inst) + 0x00000003) +#define BF_COUNT1_REG1_INFO(inst) ((inst) + 0x00000003), 0x00000800 + +#define REG_TS_RST_STATUS_ADDR(inst) ((inst) + 0x0000001E) +#define BF_RST_DONE_TXRX_TRIGGER_TS_INFO(inst) ((inst) + 0x0000001E), 0x00000100 +#define BF_RST_DONE_CLR_TXRX_TRIGGER_TS_INFO(inst) ((inst) + 0x0000001E), 0x00000101 + +#define REG_TS_RST_ADDR(inst) ((inst) + 0x0000001F) +#define BF_TS_RST_MODE_TXRX_TRIGGER_TS_INFO(inst) ((inst) + 0x0000001F), 0x00000100 +#define BF_SPI_TS_RST_TXRX_TRIGGER_TS_INFO(inst) ((inst) + 0x0000001F), 0x00000102 + +#define REG_TS_RD_EN_ADDR(inst) ((inst) + 0x00000020) +#define BF_TIMESTAMP_READ_EN_TXRX_TRIGGER_TS_INFO(inst) ((inst) + 0x00000020), 0x00000100 + +#define REG_TS_STATUS0_ADDR(inst) ((inst) + 0x00000021) +#define BF_TIMESTAMP_STATUS_TXRX_TRIGGER_TS_INFO(inst) ((inst) + 0x00000021), 0x00004000 + +#define REG_TS_STATUS1_ADDR(inst) ((inst) + 0x00000022) + +#define REG_TS_STATUS2_ADDR(inst) ((inst) + 0x00000023) + +#define REG_TS_STATUS3_ADDR(inst) ((inst) + 0x00000024) + +#define REG_TS_STATUS4_ADDR(inst) ((inst) + 0x00000025) + +#define REG_TS_STATUS5_ADDR(inst) ((inst) + 0x00000026) + +#define REG_TS_STATUS6_ADDR(inst) ((inst) + 0x00000027) + +#define REG_TS_STATUS7_ADDR(inst) ((inst) + 0x00000028) + +#define REG_TRIG_OFFSET0_ADDR(inst, n) ((inst) + 0x00000035 + 1 * (n)) +#define BF_TRIG_OFFSET0_INFO(inst, n) ((inst) + 0x00000035 + 1 * (n)), 0x00004000 + +#define REG_TRIG_OFFSET1_ADDR(inst, n) ((inst) + 0x00000055 + 1 * (n)) + +#define REG_TRIG_OFFSET2_ADDR(inst, n) ((inst) + 0x00000075 + 1 * (n)) + +#define REG_TRIG_OFFSET3_ADDR(inst, n) ((inst) + 0x00000095 + 1 * (n)) + +#define REG_TRIG_OFFSET4_ADDR(inst, n) ((inst) + 0x000000B5 + 1 * (n)) + +#define REG_TRIG_OFFSET5_ADDR(inst, n) ((inst) + 0x000000D5 + 1 * (n)) + +#define REG_TRIG_OFFSET6_ADDR(inst, n) ((inst) + 0x000000F5 + 1 * (n)) + +#define REG_TRIG_OFFSET7_ADDR(inst, n) ((inst) + 0x00000115 + 1 * (n)) + +#define REG_TRIG_PERIOD0_ADDR(inst, n) ((inst) + 0x00000135 + 1 * (n)) +#define BF_TRIG_PERIOD0_INFO(inst, n) ((inst) + 0x00000135 + 1 * (n)), 0x00004000 + +#define REG_TRIG_PERIOD1_ADDR(inst, n) ((inst) + 0x00000155 + 1 * (n)) + +#define REG_TRIG_PERIOD2_ADDR(inst, n) ((inst) + 0x00000175 + 1 * (n)) + +#define REG_TRIG_PERIOD3_ADDR(inst, n) ((inst) + 0x00000195 + 1 * (n)) + +#define REG_TRIG_PERIOD4_ADDR(inst, n) ((inst) + 0x000001B5 + 1 * (n)) + +#define REG_TRIG_PERIOD5_ADDR(inst, n) ((inst) + 0x000001D5 + 1 * (n)) + +#define REG_TRIG_PERIOD6_ADDR(inst, n) ((inst) + 0x000001F5 + 1 * (n)) + +#define REG_TRIG_PERIOD7_ADDR(inst, n) ((inst) + 0x00000215 + 1 * (n)) + +#define REG_TRIG_GPIO_PERIOD0_ADDR(inst, n) ((inst) + 0x00000235 + 1 * (n)) +#define BF_TRIG_GPIO_PERIOD0_INFO(inst, n) ((inst) + 0x00000235 + 1 * (n)), 0x00001000 + +#define REG_TRIG_GPIO_PERIOD1_ADDR(inst, n) ((inst) + 0x00000255 + 1 * (n)) + +#define REG_TRIG_SEL_MUX_BMEM_ADDR(inst, n) ((inst) + 0x00000275 + 1 * (n)) +#define BF_TRIG_SEL_MUX_BMEM_INFO(inst, n) ((inst) + 0x00000275 + 1 * (n)), 0x00000300 + +#define REG_SPI_TRIG_ADDR(inst) ((inst) + 0x00000277) +#define BF_SPI_TRIG_INFO(inst) ((inst) + 0x00000277), 0x00000100 + +#define REG_TM_SEL0_ADDR(inst) ((inst) + 0x00000278) +#define BF_TM_SEL0_INFO(inst) ((inst) + 0x00000278), 0x00000500 + +#define REG_TM_SEL1_ADDR(inst) ((inst) + 0x00000298) +#define BF_TM_SEL1_INFO(inst) ((inst) + 0x00000298), 0x00000500 + +#define REG_TRIG_SEL_MUX_CDRC0_ADDR(inst, n) ((inst) + 0x000002B8 + 1 * (n)) +#define BF_TRIG_SEL_MUX_CDRC0_INFO(inst, n) ((inst) + 0x000002B8 + 1 * (n)), 0x00000300 + +#define REG_TRIG_SEL_MUX_CDRC1_ADDR(inst, n) ((inst) + 0x000002BA + 1 * (n)) +#define BF_TRIG_SEL_MUX_CDRC1_INFO(inst, n) ((inst) + 0x000002BA + 1 * (n)), 0x00000300 + +#define REG_TRIG_SEL_MUX_FDRC0_ADDR(inst, n) ((inst) + 0x000002BC + 1 * (n)) +#define BF_TRIG_SEL_MUX_FDRC0_INFO(inst, n) ((inst) + 0x000002BC + 1 * (n)), 0x00000300 + +#define REG_TRIG_SEL_MUX_FDRC1_ADDR(inst, n) ((inst) + 0x000002C0 + 1 * (n)) +#define BF_TRIG_SEL_MUX_FDRC1_INFO(inst, n) ((inst) + 0x000002C0 + 1 * (n)), 0x00000300 + +#define REG_TRIG_SEL_MUX_LINEARX_ADDR(inst) ((inst) + 0x000002C4) +#define BF_TRIG_SEL_MUX_LINEARX_INFO(inst) ((inst) + 0x000002C4), 0x00000300 + +#define REG_TRIG_CTRL_TXRX_TRIGGER_TS_ADDR(inst, n) ((inst) + 0x000002C7 + 1 * (n)) +#define BF_MUTE_TRIG_INFO(inst, n) ((inst) + 0x000002C7 + 1 * (n)), 0x00000100 +#define BF_TRIG_EN_INFO(inst, n) ((inst) + 0x000002C7 + 1 * (n)), 0x00000101 +#define BF_TRIG_MASK_COUNT_INFO(inst, n) ((inst) + 0x000002C7 + 1 * (n)), 0x00000202 +#define BF_TRIG_SEL_INFO(inst, n) ((inst) + 0x000002C7 + 1 * (n)), 0x00000204 + +#define REG_TRIG_SEL_MUX_RECONFIG_ADDR(inst) ((inst) + 0x000002E7) +#define BF_TRIG_SEL_MUX_RECONFIG_INFO(inst) ((inst) + 0x000002E7), 0x00000300 + +#define REG_TRIG_SEL_MUX_PFILT0_ADDR(inst) ((inst) + 0x000002F7) +#define BF_TRIG_SEL_MUX_PFILT0_INFO(inst) ((inst) + 0x000002F7), 0x00000300 + +#define REG_TRIG_SEL_MUX_PFILT1_ADDR(inst) ((inst) + 0x000002F8) +#define BF_TRIG_SEL_MUX_PFILT1_INFO(inst) ((inst) + 0x000002F8), 0x00000300 + +#define REG_TRIG_SEL_MUX_CFIR_ADDR(inst, n) ((inst) + 0x000002F9 + 1 * (n)) +#define BF_TRIG_SEL_MUX_CFIR_INFO(inst, n) ((inst) + 0x000002F9 + 1 * (n)), 0x00000300 + +#define REG_TRIG_SEL_MUX_CBMEM_ADDR(inst, n) ((inst) + 0x000002FB + 1 * (n)) +#define BF_TRIG_SEL_MUX_CBMEM_INFO(inst, n) ((inst) + 0x000002FB + 1 * (n)), 0x00000303 + +#define REG_TRIG_SEL_MUX_FBMEM_ADDR(inst, n) ((inst) + 0x000002FD + 1 * (n)) +#define BF_TRIG_SEL_MUX_FBMEM_INFO(inst, n) ((inst) + 0x000002FD + 1 * (n)), 0x00000300 + +#endif /* __ADI_APOLLO_BF_TXRX_TRIGGER_TS_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_uart.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_uart.h new file mode 100644 index 00000000000000..bc377821f079c8 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_uart.h @@ -0,0 +1,156 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:17 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_UART_H__ +#define __ADI_APOLLO_BF_UART_H__ + +/*============= D E F I N E S ==============*/ +#ifdef USE_PRIVATE_BF +#define REG_REVID_ADDR 0x46100000 +#define BF_REV_INFO 0x46100000, 0x00000400 +#define BF_MAJOR_INFO 0x46100000, 0x00000404 +#endif /* USE_PRIVATE_BF */ + +#define REG_CTL_UART_ADDR 0x46100004 +#define BF_EN_UART_INFO 0x46100004, 0x00000100 +#define BF_LOOP_EN_INFO 0x46100004, 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_RESVD2_INFO 0x46100004, 0x00000102 +#endif /* USE_PRIVATE_BF */ +#ifdef USE_PRIVATE_BF +#define BF_RESVD3_INFO 0x46100004, 0x00000103 +#endif /* USE_PRIVATE_BF */ +#define BF_MOD_INFO 0x46100004, 0x00000204 +#ifdef USE_PRIVATE_BF +#define BF_RESVD6_INFO 0x46100004, 0x00000106 +#endif /* USE_PRIVATE_BF */ +#ifdef USE_PRIVATE_BF +#define BF_RESVD7_INFO 0x46100004, 0x00000107 +#endif /* USE_PRIVATE_BF */ +#define BF_WLS_INFO 0x46100004, 0x00000208 +#ifdef USE_PRIVATE_BF +#define BF_RESVD10_INFO 0x46100004, 0x0000010A +#endif /* USE_PRIVATE_BF */ +#ifdef USE_PRIVATE_BF +#define BF_RESVD11_INFO 0x46100004, 0x0000010B +#endif /* USE_PRIVATE_BF */ +#define BF_STB_INFO 0x46100004, 0x0000010C +#define BF_STBH_INFO 0x46100004, 0x0000010D +#define BF_PEN_INFO 0x46100004, 0x0000010E +#define BF_EPS_INFO 0x46100004, 0x0000010F +#define BF_STP_INFO 0x46100004, 0x00000110 +#define BF_FPE_INFO 0x46100004, 0x00000111 +#define BF_FFE_INFO 0x46100004, 0x00000112 +#define BF_SB_INFO 0x46100004, 0x00000113 +#ifdef USE_PRIVATE_BF +#define BF_RESVD20_INFO 0x46100004, 0x00000114 +#endif /* USE_PRIVATE_BF */ +#ifdef USE_PRIVATE_BF +#define BF_RESVD21_INFO 0x46100004, 0x00000115 +#endif /* USE_PRIVATE_BF */ +#define BF_FCPOL_INFO 0x46100004, 0x00000116 +#define BF_RPOLC_INFO 0x46100004, 0x00000117 +#define BF_TPOLC_INFO 0x46100004, 0x00000118 +#define BF_MRTS_INFO 0x46100004, 0x00000119 +#define BF_XOFF_INFO 0x46100004, 0x0000011A +#define BF_ARTS_INFO 0x46100004, 0x0000011B +#define BF_ACTS_INFO 0x46100004, 0x0000011C +#define BF_RFIT_INFO 0x46100004, 0x0000011D +#define BF_RFRT_INFO 0x46100004, 0x0000011E +#ifdef USE_PRIVATE_BF +#define BF_RESVD31_INFO 0x46100004, 0x0000011F +#endif /* USE_PRIVATE_BF */ + +#define REG_STAT_UART_ADDR 0x46100008 +#define BF_DR_INFO 0x46100008, 0x00000100 +#define BF_OE_INFO 0x46100008, 0x00000101 +#define BF_PE_INFO 0x46100008, 0x00000102 +#define BF_FE_INFO 0x46100008, 0x00000103 +#define BF_BI_INFO 0x46100008, 0x00000104 +#define BF_THRE_INFO 0x46100008, 0x00000105 +#define BF_TEMT_INFO 0x46100008, 0x00000107 +#define BF_TFI_INFO 0x46100008, 0x00000108 +#define BF_ASTKY_INFO 0x46100008, 0x00000109 +#define BF_ADDR_INFO 0x46100008, 0x0000010A +#define BF_RO_INFO 0x46100008, 0x0000010B +#define BF_SCTS_INFO 0x46100008, 0x0000010C +#define BF_CTS_INFO 0x46100008, 0x00000110 +#define BF_RFCS_INFO 0x46100008, 0x00000111 + +#define REG_SCR_ADDR 0x4610000C +#define BF_VALUE_SCR_INFO 0x4610000C, 0x00000800 + +#define REG_CLK_ADDR 0x46100010 +#define BF_DIV_INFO 0x46100010, 0x00001F00 +#define BF_EDBO_INFO 0x46100010, 0x0000011F + +#define REG_IMSK_ADDR 0x46100014 +#define BF_ERBFI_INFO 0x46100014, 0x00000100 +#define BF_ETBEI_INFO 0x46100014, 0x00000101 +#define BF_ELSI_INFO 0x46100014, 0x00000102 +#define BF_EDSSI_INFO 0x46100014, 0x00000103 +#define BF_EDTPTI_INFO 0x46100014, 0x00000104 +#define BF_ETFI_INFO 0x46100014, 0x00000105 +#define BF_ERFCI_INFO 0x46100014, 0x00000106 +#define BF_EAWI_INFO 0x46100014, 0x00000107 +#define BF_ERXS_INFO 0x46100014, 0x00000108 +#define BF_ETXS_INFO 0x46100014, 0x00000109 + +#define REG_IMSK_SET_ADDR 0x46100018 +#define BF_ERBFI_SET_INFO 0x46100018, 0x00000100 +#define BF_ETBEI_SET_INFO 0x46100018, 0x00000101 +#define BF_ELSI_SET_INFO 0x46100018, 0x00000102 +#define BF_EDSSI_SET_INFO 0x46100018, 0x00000103 +#define BF_EDTPTI_SET_INFO 0x46100018, 0x00000104 +#define BF_ETFI_SET_INFO 0x46100018, 0x00000105 +#define BF_ERFCI_SET_INFO 0x46100018, 0x00000106 +#define BF_EAWI_SET_INFO 0x46100018, 0x00000107 +#define BF_ERXS_SET_INFO 0x46100018, 0x00000108 +#define BF_ETXS_SET_INFO 0x46100018, 0x00000109 + +#define REG_IMSK_CLR_ADDR 0x4610001C +#define BF_ERBFI_CLR_INFO 0x4610001C, 0x00000100 +#define BF_ETBEI_CLR_INFO 0x4610001C, 0x00000101 +#define BF_ELSI_CLR_INFO 0x4610001C, 0x00000102 +#define BF_EDSSI_CLR_INFO 0x4610001C, 0x00000103 +#define BF_EDTPTI_CLR_INFO 0x4610001C, 0x00000104 +#define BF_ETFI_CLR_INFO 0x4610001C, 0x00000105 +#define BF_ERFCI_CLR_INFO 0x4610001C, 0x00000106 +#define BF_EAWI_CLR_INFO 0x4610001C, 0x00000107 +#define BF_ERXS_CLR_INFO 0x4610001C, 0x00000108 +#define BF_ETXS_CLR_INFO 0x4610001C, 0x00000109 + +#define REG_RBR_ADDR 0x46100020 +#define BF_VALUE_RBR_INFO 0x46100020, 0x00000800 + +#define REG_THR_ADDR 0x46100024 +#define BF_VALUE_THR_INFO 0x46100024, 0x00000800 + +#define REG_TAIP_ADDR 0x46100028 +#define BF_VALUE_TAIP_INFO 0x46100028, 0x00000800 + +#define REG_TSR_ADDR 0x4610002C +#define BF_VALUE_TSR_INFO 0x4610002C, 0x00000B00 + +#define REG_RSR_ADDR 0x46100030 +#define BF_VALUE_RSR_INFO 0x46100030, 0x00000A00 + +#define REG_TXCNT_ADDR 0x46100034 +#define BF_VALUE_TXCNT_INFO 0x46100034, 0x00001F00 + +#define REG_RXCNT_ADDR 0x46100038 +#define BF_VALUE_RXCNT_INFO 0x46100038, 0x00001F00 + +#endif /* __ADI_APOLLO_BF_UART_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_uartfifo.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_uartfifo.h new file mode 100644 index 00000000000000..6f1f58caab6bd5 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_uartfifo.h @@ -0,0 +1,35 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:17 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_UARTFIFO_H__ +#define __ADI_APOLLO_BF_UARTFIFO_H__ + +/*============= D E F I N E S ==============*/ +#define REG_UARTFIFO_DATA_ADDR 0x46000000 +#define BF_FIFODATA_INFO 0x46000000, 0x00000800 + +#define REG_UARTFIFO_STATUS_ADDR 0x46000004 +#define BF_FIFO_UNDERFLOW_INFO 0x46000004, 0x00000100 +#define BF_FIFO_HALF_FULL_INFO 0x46000004, 0x00000101 +#define BF_FIFO_ALMOST_FULL_INFO 0x46000004, 0x00000102 +#define BF_FIFO_FULL_INFO 0x46000004, 0x00000103 + +#define REG_UARTFIFO_INTR_EN_ADDR 0x46000008 +#define BF_FIFOINTREN_INFO 0x46000008, 0x00000400 + +#define REG_UARTFIFO_OCCUPANCY_STATUS_ADDR 0x4600000C +#define BF_FIFO_OCCUPANCY_STATUS_INFO 0x4600000C, 0x00000900 + +#endif /* __ADI_APOLLO_BF_UARTFIFO_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_venus_dcal_open.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_venus_dcal_open.h new file mode 100644 index 00000000000000..98c0e21336fc3b --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_venus_dcal_open.h @@ -0,0 +1,370 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:19 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_VENUS_DCAL_OPEN_H__ +#define __ADI_APOLLO_BF_VENUS_DCAL_OPEN_H__ + +/*============= D E F I N E S ==============*/ +#define VENUS_DCAL_REGMAP_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x60280000 +#define VENUS_DCAL_REGMAP_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x60480000 +#define VENUS_DCAL_REGMAP_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A80000 +#define VENUS_DCAL_REGMAP_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C80000 + +#define REG_DCAL_SCRATCH_BEGIN_ADDR(inst) ((inst) + 0x00000000) +#define BF_DCAL_SCRATCH_BEGIN_INFO(inst) ((inst) + 0x00000000), 0x00002000 + +#define REG_REG_0X0004_VENUS_DCAL__OPEN_ADDR(inst) ((inst) + 0x00000004) +#ifdef USE_PRIVATE_BF +#define BF_BF_65905AEB_INFO(inst) ((inst) + 0x00000004), 0x00000800 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_65905AEB_WEB_INFO(inst) ((inst) + 0x00000004), 0x00000108 +#ifdef USE_PRIVATE_BF +#define BF_BF_153627F9_INFO(inst) ((inst) + 0x00000004), 0x00000810 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_153627F9_WEB_INFO(inst) ((inst) + 0x00000004), 0x00000118 + +#define REG_REG_0X0008_VENUS_DCAL__OPEN_ADDR(inst) ((inst) + 0x00000008) +#ifdef USE_PRIVATE_BF +#define BF_BF_1D1898C8_INFO(inst) ((inst) + 0x00000008), 0x00000800 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_1D1898C8_WEB_INFO(inst) ((inst) + 0x00000008), 0x00000108 +#ifdef USE_PRIVATE_BF +#define BF_BF_D8B905EC_INFO(inst) ((inst) + 0x00000008), 0x00000810 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_D8B905EC_WEB_INFO(inst) ((inst) + 0x00000008), 0x00000118 + +#define REG_CUST_CONV_CTRL_ADDR(inst, n) ((inst) + 0x0000000C + 4 * (n)) +#define BF_TPAT_MODE_SEL_INFO(inst, n) ((inst) + 0x0000000C + 4 * (n)), 0x00000410 +#define BF_TPAT_INVERT_INFO(inst, n) ((inst) + 0x0000000C + 4 * (n)), 0x00000115 +#define BF_TPAT_RESTART_INFO(inst, n) ((inst) + 0x0000000C + 4 * (n)), 0x00000117 + +#define REG_CUST_USR_PAT_ADDR(inst, n) ((inst) + 0x0000002C + 4 * (n)) +#define BF_TPAT_USR_PAT_INFO(inst, n) ((inst) + 0x0000002C + 4 * (n)), 0x00001000 + +#define REG_REG_0X003C_VENUS_DCAL__OPEN_ADDR(inst, n) ((inst) + 0x0000003C + 4 * (n)) +#ifdef USE_PRIVATE_BF +#define BF_BF_F3500F69_INFO(inst, n) ((inst) + 0x0000003C + 4 * (n)), 0x00000210 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_F3500F69_WEB_INFO(inst, n) ((inst) + 0x0000003C + 4 * (n)), 0x00000112 +#ifdef USE_PRIVATE_BF +#define BF_BF_FE706944_INFO(inst, n) ((inst) + 0x0000003C + 4 * (n)), 0x00000116 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_FE706944_WEB_INFO(inst, n) ((inst) + 0x0000003C + 4 * (n)), 0x00000117 + +#define REG_REG_0X005C_VENUS_DCAL__OPEN_ADDR(inst) ((inst) + 0x0000005C) +#ifdef USE_PRIVATE_BF +#define BF_BF_C3ED7542_INFO(inst) ((inst) + 0x0000005C), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_C3ED7542_WEB_INFO(inst) ((inst) + 0x0000005C), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_6FF193DE_INFO(inst) ((inst) + 0x0000005C), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_6FF193DE_WEB_INFO(inst) ((inst) + 0x0000005C), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_952F97F2_INFO(inst) ((inst) + 0x0000005C), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_952F97F2_WEB_INFO(inst) ((inst) + 0x0000005C), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_A1FA7FB8_INFO(inst) ((inst) + 0x0000005C), 0x00000106 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_A1FA7FB8_WEB_INFO(inst) ((inst) + 0x0000005C), 0x00000107 +#ifdef USE_PRIVATE_BF +#define BF_BF_C8C93406_INFO(inst) ((inst) + 0x0000005C), 0x00000108 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_C8C93406_WEB_INFO(inst) ((inst) + 0x0000005C), 0x00000109 +#ifdef USE_PRIVATE_BF +#define BF_BF_2F45D307_INFO(inst) ((inst) + 0x0000005C), 0x0000010A +#endif /* USE_PRIVATE_BF */ +#define BF_BF_2F45D307_WEB_INFO(inst) ((inst) + 0x0000005C), 0x0000010B +#ifdef USE_PRIVATE_BF +#define BF_BF_066FBC7D_INFO(inst) ((inst) + 0x0000005C), 0x0000010C +#endif /* USE_PRIVATE_BF */ +#define BF_BF_066FBC7D_WEB_INFO(inst) ((inst) + 0x0000005C), 0x0000010D +#ifdef USE_PRIVATE_BF +#define BF_BF_F9C55881_INFO(inst) ((inst) + 0x0000005C), 0x0000010E +#endif /* USE_PRIVATE_BF */ +#define BF_BF_F9C55881_WEB_INFO(inst) ((inst) + 0x0000005C), 0x0000010F +#ifdef USE_PRIVATE_BF +#define BF_BF_AE88D120_INFO(inst) ((inst) + 0x0000005C), 0x0000011E +#endif /* USE_PRIVATE_BF */ +#define BF_BF_AE88D120_WEB_INFO(inst) ((inst) + 0x0000005C), 0x0000011F + +#define REG_REG_0X0060_VENUS_DCAL__OPEN_ADDR(inst) ((inst) + 0x00000060) +#ifdef USE_PRIVATE_BF +#define BF_BF_C0C064C6_INFO(inst) ((inst) + 0x00000060), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_C0C064C6_WEB_INFO(inst) ((inst) + 0x00000060), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_186A7DF7_INFO(inst) ((inst) + 0x00000060), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_186A7DF7_WEB_INFO(inst) ((inst) + 0x00000060), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_00791309_INFO(inst) ((inst) + 0x00000060), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_00791309_WEB_INFO(inst) ((inst) + 0x00000060), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_27A5E948_INFO(inst) ((inst) + 0x00000060), 0x00000106 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_27A5E948_WEB_INFO(inst) ((inst) + 0x00000060), 0x00000107 +#ifdef USE_PRIVATE_BF +#define BF_BF_D79258B3_INFO(inst) ((inst) + 0x00000060), 0x00000108 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_D79258B3_WEB_INFO(inst) ((inst) + 0x00000060), 0x00000109 +#ifdef USE_PRIVATE_BF +#define BF_BF_E8110471_INFO(inst) ((inst) + 0x00000060), 0x0000010A +#endif /* USE_PRIVATE_BF */ +#define BF_BF_E8110471_WEB_INFO(inst) ((inst) + 0x00000060), 0x0000010B +#ifdef USE_PRIVATE_BF +#define BF_BF_2C9ED7B9_INFO(inst) ((inst) + 0x00000060), 0x0000010C +#endif /* USE_PRIVATE_BF */ +#define BF_BF_2C9ED7B9_WEB_INFO(inst) ((inst) + 0x00000060), 0x0000010D +#ifdef USE_PRIVATE_BF +#define BF_BF_E61D6D80_INFO(inst) ((inst) + 0x00000060), 0x0000010E +#endif /* USE_PRIVATE_BF */ +#define BF_BF_E61D6D80_WEB_INFO(inst) ((inst) + 0x00000060), 0x0000010F +#ifdef USE_PRIVATE_BF +#define BF_BF_6D8FDD12_INFO(inst) ((inst) + 0x00000060), 0x0000011E +#endif /* USE_PRIVATE_BF */ +#define BF_BF_6D8FDD12_WEB_INFO(inst) ((inst) + 0x00000060), 0x0000011F + +#define REG_REG_0X0068_VENUS_DCAL__OPEN_ADDR(inst) ((inst) + 0x00000068) +#ifdef USE_PRIVATE_BF +#define BF_BF_799FD906_INFO(inst) ((inst) + 0x00000068), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_799FD906_WEB_INFO(inst) ((inst) + 0x00000068), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_AEC1FBD9_INFO(inst) ((inst) + 0x00000068), 0x00000804 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_AEC1FBD9_WEB_INFO(inst) ((inst) + 0x00000068), 0x0000010C +#ifdef USE_PRIVATE_BF +#define BF_BF_8AE41084_INFO(inst) ((inst) + 0x00000068), 0x0000080D +#endif /* USE_PRIVATE_BF */ +#define BF_BF_8AE41084_WEB_INFO(inst) ((inst) + 0x00000068), 0x00000115 +#ifdef USE_PRIVATE_BF +#define BF_BF_B9811EB3_INFO(inst) ((inst) + 0x00000068), 0x00000816 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_B9811EB3_WEB_INFO(inst) ((inst) + 0x00000068), 0x0000011E + +#define REG_REG_0X006C_VENUS_DCAL__OPEN_ADDR(inst) ((inst) + 0x0000006C) +#ifdef USE_PRIVATE_BF +#define BF_BF_B76A3C34_INFO(inst) ((inst) + 0x0000006C), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_B76A3C34_WEB_INFO(inst) ((inst) + 0x0000006C), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_133FECF5_INFO(inst) ((inst) + 0x0000006C), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_133FECF5_WEB_INFO(inst) ((inst) + 0x0000006C), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_4DC5BF86_INFO(inst) ((inst) + 0x0000006C), 0x00000804 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_4DC5BF86_WEB_INFO(inst) ((inst) + 0x0000006C), 0x0000010C +#ifdef USE_PRIVATE_BF +#define BF_BF_23F81451_INFO(inst) ((inst) + 0x0000006C), 0x0000080D +#endif /* USE_PRIVATE_BF */ +#define BF_BF_23F81451_WEB_INFO(inst) ((inst) + 0x0000006C), 0x00000115 +#ifdef USE_PRIVATE_BF +#define BF_BF_A403BA02_INFO(inst) ((inst) + 0x0000006C), 0x00000816 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_A403BA02_WEB_INFO(inst) ((inst) + 0x0000006C), 0x0000011E + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0070_VENUS_DCAL__OPEN_ADDR(inst) ((inst) + 0x00000070) +#define BF_BF_69891E46_INFO(inst) ((inst) + 0x00000070), 0x00000800 +#define BF_BF_CC510E0C_INFO(inst) ((inst) + 0x00000070), 0x00000808 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0074_VENUS_DCAL__OPEN_ADDR(inst) ((inst) + 0x00000074) +#define BF_BF_F5C7267F_INFO(inst) ((inst) + 0x00000074), 0x00000408 +#define BF_BF_42F4D459_INFO(inst) ((inst) + 0x00000074), 0x0000010D +#define BF_BF_0E519C6B_INFO(inst) ((inst) + 0x00000074), 0x0000010E +#define BF_BF_1D4E994A_INFO(inst) ((inst) + 0x00000074), 0x0000010F +#define BF_BF_D243CEBC_INFO(inst) ((inst) + 0x00000074), 0x00000418 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0078_VENUS_DCAL__OPEN_ADDR(inst) ((inst) + 0x00000078) +#define BF_BF_FDEC5891_INFO(inst) ((inst) + 0x00000078), 0x00000408 +#define BF_BF_9812E42B_INFO(inst) ((inst) + 0x00000078), 0x0000010D +#define BF_BF_00877BB4_INFO(inst) ((inst) + 0x00000078), 0x0000010E +#define BF_BF_D8AD3486_INFO(inst) ((inst) + 0x00000078), 0x0000010F +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X007C_VENUS_DCAL__OPEN_ADDR(inst) ((inst) + 0x0000007C) +#ifdef USE_PRIVATE_BF +#define BF_BF_B0EEA13E_INFO(inst) ((inst) + 0x0000007C), 0x00000300 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_B0EEA13E_WEB_INFO(inst) ((inst) + 0x0000007C), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_125BD416_INFO(inst) ((inst) + 0x0000007C), 0x00000304 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_125BD416_WEB_INFO(inst) ((inst) + 0x0000007C), 0x00000107 +#ifdef USE_PRIVATE_BF +#define BF_BF_FAFF7B1A_INFO(inst) ((inst) + 0x0000007C), 0x00000308 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_FAFF7B1A_WEB_INFO(inst) ((inst) + 0x0000007C), 0x0000010B +#ifdef USE_PRIVATE_BF +#define BF_BF_F3337F4F_INFO(inst) ((inst) + 0x0000007C), 0x0000030C +#endif /* USE_PRIVATE_BF */ +#define BF_BF_F3337F4F_WEB_INFO(inst) ((inst) + 0x0000007C), 0x0000010F +#ifdef USE_PRIVATE_BF +#define BF_BF_DA710C92_INFO(inst) ((inst) + 0x0000007C), 0x00000310 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_DA710C92_WEB_INFO(inst) ((inst) + 0x0000007C), 0x00000113 +#ifdef USE_PRIVATE_BF +#define BF_BF_D36F4FAA_INFO(inst) ((inst) + 0x0000007C), 0x00000314 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_D36F4FAA_WEB_INFO(inst) ((inst) + 0x0000007C), 0x00000117 +#ifdef USE_PRIVATE_BF +#define BF_BF_140A522B_INFO(inst) ((inst) + 0x0000007C), 0x00000318 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_140A522B_WEB_INFO(inst) ((inst) + 0x0000007C), 0x0000011B +#ifdef USE_PRIVATE_BF +#define BF_BF_A3EC1B9D_INFO(inst) ((inst) + 0x0000007C), 0x0000031C +#endif /* USE_PRIVATE_BF */ +#define BF_BF_A3EC1B9D_WEB_INFO(inst) ((inst) + 0x0000007C), 0x0000011F + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0080_VENUS_DCAL__OPEN_ADDR(inst) ((inst) + 0x00000080) +#define BF_BF_FBEE0B3C_INFO(inst) ((inst) + 0x00000080), 0x00000800 +#define BF_BF_E0086C88_INFO(inst) ((inst) + 0x00000080), 0x00000808 +#define BF_BF_B04EAF9B_INFO(inst) ((inst) + 0x00000080), 0x00000810 +#define BF_BF_C62F9DD2_INFO(inst) ((inst) + 0x00000080), 0x00000818 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0084_VENUS_DCAL__OPEN_ADDR(inst) ((inst) + 0x00000084) +#define BF_BF_7A860592_INFO(inst) ((inst) + 0x00000084), 0x00000800 +#define BF_BF_4EC5642D_INFO(inst) ((inst) + 0x00000084), 0x00000810 +#define BF_BF_BFAE9EFF_INFO(inst) ((inst) + 0x00000084), 0x00000818 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0088_VENUS_DCAL__OPEN_ADDR(inst) ((inst) + 0x00000088) +#ifdef USE_PRIVATE_BF +#define BF_BF_353CD723_INFO(inst) ((inst) + 0x00000088), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_353CD723_WEB_INFO(inst) ((inst) + 0x00000088), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_B214D2A2_INFO(inst) ((inst) + 0x00000088), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_B214D2A2_WEB_INFO(inst) ((inst) + 0x00000088), 0x00000103 + +#define REG_REG_0X008C_VENUS_DCAL__OPEN_ADDR(inst) ((inst) + 0x0000008C) +#ifdef USE_PRIVATE_BF +#define BF_BF_6877F9DB_INFO(inst) ((inst) + 0x0000008C), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_6877F9DB_WEB_INFO(inst) ((inst) + 0x0000008C), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_F13E8147_INFO(inst) ((inst) + 0x0000008C), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_F13E8147_WEB_INFO(inst) ((inst) + 0x0000008C), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_724868B0_INFO(inst) ((inst) + 0x0000008C), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_724868B0_WEB_INFO(inst) ((inst) + 0x0000008C), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_7005A3C2_INFO(inst) ((inst) + 0x0000008C), 0x00000106 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_7005A3C2_WEB_INFO(inst) ((inst) + 0x0000008C), 0x00000107 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0090_VENUS_DCAL__OPEN_ADDR(inst, n) ((inst) + 0x00000090 + 4 * (n)) +#define BF_BF_E4D1D250_INFO(inst, n) ((inst) + 0x00000090 + 4 * (n)), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00A0_VENUS_DCAL__OPEN_ADDR(inst, n) ((inst) + 0x000000A0 + 4 * (n)) +#define BF_BF_0ADCCC43_INFO(inst, n) ((inst) + 0x000000A0 + 4 * (n)), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00B0_VENUS_DCAL__OPEN_ADDR(inst, n) ((inst) + 0x000000B0 + 4 * (n)) +#define BF_BF_85081AEA_INFO(inst, n) ((inst) + 0x000000B0 + 4 * (n)), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00C0_VENUS_DCAL__OPEN_ADDR(inst, n) ((inst) + 0x000000C0 + 4 * (n)) +#define BF_BF_CAADE6EB_INFO(inst, n) ((inst) + 0x000000C0 + 4 * (n)), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00D0_VENUS_DCAL__OPEN_ADDR(inst, n) ((inst) + 0x000000D0 + 4 * (n)) +#define BF_BF_A9E91F37_INFO(inst, n) ((inst) + 0x000000D0 + 4 * (n)), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00E0_VENUS_DCAL__OPEN_ADDR(inst, n) ((inst) + 0x000000E0 + 4 * (n)) +#define BF_BF_902169B2_INFO(inst, n) ((inst) + 0x000000E0 + 4 * (n)), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00F0_VENUS_DCAL__OPEN_ADDR(inst, n) ((inst) + 0x000000F0 + 4 * (n)) +#define BF_BF_DC00DB1E_INFO(inst, n) ((inst) + 0x000000F0 + 4 * (n)), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0100_VENUS_DCAL__OPEN_ADDR(inst, n) ((inst) + 0x00000100 + 4 * (n)) +#define BF_BF_ECD9C66D_INFO(inst, n) ((inst) + 0x00000100 + 4 * (n)), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0110_ADDR(inst, n) ((inst) + 0x00000110 + 4 * (n)) +#define BF_BF_472B2E6F_INFO(inst, n) ((inst) + 0x00000110 + 4 * (n)), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0588_VENUS_DCAL__OPEN_ADDR(inst, n) ((inst) + 0x00000588 + 4 * (n)) +#define BF_BF_965DC444_INFO(inst, n) ((inst) + 0x00000588 + 4 * (n)), 0x00000300 +#define BF_BF_3C848DBF_INFO(inst, n) ((inst) + 0x00000588 + 4 * (n)), 0x00000103 +#define BF_BF_DDBE019C_INFO(inst, n) ((inst) + 0x00000588 + 4 * (n)), 0x00000304 +#define BF_BF_97D3C301_INFO(inst, n) ((inst) + 0x00000588 + 4 * (n)), 0x00000107 +#define BF_BF_44D750FF_INFO(inst, n) ((inst) + 0x00000588 + 4 * (n)), 0x00000308 +#define BF_BF_DF2C7815_INFO(inst, n) ((inst) + 0x00000588 + 4 * (n)), 0x0000010B +#define BF_BF_F0197C39_INFO(inst, n) ((inst) + 0x00000588 + 4 * (n)), 0x0000030C +#define BF_BF_6DDF402C_INFO(inst, n) ((inst) + 0x00000588 + 4 * (n)), 0x0000010F +#define BF_BF_A668FCF5_INFO(inst, n) ((inst) + 0x00000588 + 4 * (n)), 0x00000310 +#define BF_BF_49F2951C_INFO(inst, n) ((inst) + 0x00000588 + 4 * (n)), 0x00000113 +#define BF_BF_08731E8D_INFO(inst, n) ((inst) + 0x00000588 + 4 * (n)), 0x00000314 +#define BF_BF_002240B3_INFO(inst, n) ((inst) + 0x00000588 + 4 * (n)), 0x00000117 +#define BF_BF_30FD0FFB_INFO(inst, n) ((inst) + 0x00000588 + 4 * (n)), 0x00000318 +#define BF_BF_45F810DF_INFO(inst, n) ((inst) + 0x00000588 + 4 * (n)), 0x0000011B +#define BF_BF_340F1D9F_INFO(inst, n) ((inst) + 0x00000588 + 4 * (n)), 0x0000031C +#define BF_BF_2153268E_INFO(inst, n) ((inst) + 0x00000588 + 4 * (n)), 0x0000011F +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X07FC_ADDR(inst) ((inst) + 0x000007FC) +#define BF_BF_6155D3A1_INFO(inst) ((inst) + 0x000007FC), 0x00000300 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0800_ADDR(inst, n) ((inst) + 0x00000800 + 4 * (n)) +#define BF_BF_51CC7466_INFO(inst, n) ((inst) + 0x00000800 + 4 * (n)), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0814_ADDR(inst) ((inst) + 0x00000814) +#define BF_BF_B8021B85_INFO(inst) ((inst) + 0x00000814), 0x00000400 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0818_ADDR(inst) ((inst) + 0x00000818) +#define BF_BF_69C7D5DE_INFO(inst) ((inst) + 0x00000818), 0x00000200 +#endif /* USE_PRIVATE_BF */ + +#define REG_DCAL_SCRATCH_END_ADDR(inst) ((inst) + 0x00001FFC) +#define BF_DCAL_SCRATCH_END_INFO(inst) ((inst) + 0x00001FFC), 0x00002000 + +#endif /* __ADI_APOLLO_BF_VENUS_DCAL_OPEN_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_venus_fcal_broadcast_open.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_venus_fcal_broadcast_open.h new file mode 100644 index 00000000000000..6aa93877b0c688 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_venus_fcal_broadcast_open.h @@ -0,0 +1,469 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:20 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_VENUS_FCAL_BROADCAST_OPEN_H__ +#define __ADI_APOLLO_BF_VENUS_FCAL_BROADCAST_OPEN_H__ + +/*============= D E F I N E S ==============*/ +#define VENUS_FCAL_BROADCAST_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x60286800 +#define VENUS_FCAL_BROADCAST_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x60486800 +#define VENUS_FCAL_BROADCAST_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A86800 +#define VENUS_FCAL_BROADCAST_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C86800 + +#define REG_FCAL_SCRATCH_BEGIN_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000000) +#define BF_FCAL_SCRATCH_BEGIN_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000000), 0x00002000 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0004_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000004) +#define BF_BF_70D31378_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000004), 0x00000500 +#define BF_BF_AE9D973E_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000004), 0x00000107 +#define BF_BF_E3872070_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000004), 0x00000408 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0008_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000008) +#define BF_BF_95E42D3D_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000008), 0x00001508 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0010_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000010) +#ifdef USE_PRIVATE_BF +#define BF_BF_9811EAE1_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000010), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_9811EAE1_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000010), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_27E0F6ED_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000010), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_27E0F6ED_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000010), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_1ADEB97E_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000010), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_1ADEB97E_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000010), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_0F77D67B_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000010), 0x00000106 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_0F77D67B_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000010), 0x00000107 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0014_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000014) +#define BF_BF_FD5AEA08_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000014), 0x00000800 +#define BF_BF_226FC1E7_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000014), 0x00000808 +#define BF_BF_78F9304A_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000014), 0x00000810 +#define BF_BF_364A15DC_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000014), 0x00000818 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0018_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000018) + +#define REG_REG_0X0038_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000038) + +#define REG_REG_0X0058_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000058) + +#define REG_REG_0X0088_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000088) + +#define REG_REG_0X00B8_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000000B8) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0118_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst, n) ((inst) + 0x00000118 + 4 * (n)) +#define BF_BF_4148A6B6_VENUS_FCAL__BROADCAST_OPEN_INFO(inst, n) ((inst) + 0x00000118 + 4 * (n)), 0x00001508 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0120_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst, n) ((inst) + 0x00000120 + 4 * (n)) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0128_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst, n) ((inst) + 0x00000128 + 4 * (n)) +#define BF_BF_398889CE_VENUS_FCAL__BROADCAST_OPEN_INFO(inst, n) ((inst) + 0x00000128 + 4 * (n)), 0x00001508 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0130_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst, n) ((inst) + 0x00000130 + 4 * (n)) + +#define REG_REG_0X0144_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000144) + +#define REG_REG_0X0184_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000184) +#ifdef USE_PRIVATE_BF +#define BF_BF_C5135C52_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_C5135C52_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_39861C20_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_39861C20_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_7CB8B9B0_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_7CB8B9B0_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_B0D333EE_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000106 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_B0D333EE_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000107 +#ifdef USE_PRIVATE_BF +#define BF_BF_D4A3F5FF_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000108 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_D4A3F5FF_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000109 +#ifdef USE_PRIVATE_BF +#define BF_BF_EC817610_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000184), 0x0000010C +#endif /* USE_PRIVATE_BF */ +#define BF_BF_EC817610_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000184), 0x0000010D +#ifdef USE_PRIVATE_BF +#define BF_BF_FB5A9FD4_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000184), 0x0000010E +#endif /* USE_PRIVATE_BF */ +#define BF_BF_FB5A9FD4_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000184), 0x0000010F +#ifdef USE_PRIVATE_BF +#define BF_BF_7FA84C3E_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000110 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_7FA84C3E_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000111 +#ifdef USE_PRIVATE_BF +#define BF_BF_08328F9C_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000112 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_08328F9C_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000113 +#ifdef USE_PRIVATE_BF +#define BF_BF_938A3AC2_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000114 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_938A3AC2_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000115 + +#define REG_REG_0X0188_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000188) +#ifdef USE_PRIVATE_BF +#define BF_BF_A217FBDF_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000188), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_A217FBDF_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000188), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_CE0AFDEA_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000188), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_CE0AFDEA_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000188), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_96EB681F_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000188), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_96EB681F_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000188), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_46B6F335_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000188), 0x00000106 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_46B6F335_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000188), 0x00000107 +#ifdef USE_PRIVATE_BF +#define BF_BF_87DFCBB4_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000188), 0x00000108 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_87DFCBB4_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000188), 0x00000109 +#ifdef USE_PRIVATE_BF +#define BF_BF_8E62455B_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000188), 0x0000010A +#endif /* USE_PRIVATE_BF */ +#define BF_BF_8E62455B_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000188), 0x0000010B + +#define REG_REG_0X018C_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000018C) +#ifdef USE_PRIVATE_BF +#define BF_BF_C99662C6_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000018C), 0x00000200 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_C99662C6_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000018C), 0x00000102 +#ifdef USE_PRIVATE_BF +#define BF_BF_69F16890_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000018C), 0x00000203 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_69F16890_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000018C), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_13059625_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000018C), 0x00000106 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_13059625_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000018C), 0x00000107 + +#define REG_REG_0X0190_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000190) +#ifdef USE_PRIVATE_BF +#define BF_BF_D38298F0_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000190), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_D38298F0_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000190), 0x00000101 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0194_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000194) +#define BF_BF_419A5D0E_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000194), 0x00000800 +#define BF_BF_100E7AD9_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000194), 0x00000808 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0198_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000198) +#define BF_BF_3473A519_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000198), 0x00000300 +#define BF_BF_4643E55A_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000198), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X019C_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000019C) +#ifdef USE_PRIVATE_BF +#define BF_BF_A63FA2F8_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000019C), 0x00000300 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_A63FA2F8_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000019C), 0x00000103 + +#define REG_REG_0X01A0_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000001A0) +#ifdef USE_PRIVATE_BF +#define BF_BF_D327F78A_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001A0), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_D327F78A_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001A0), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_C07E65B3_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001A0), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_C07E65B3_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001A0), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_3F783369_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001A0), 0x00000508 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_3F783369_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001A0), 0x0000010D + +#define REG_REG_0X01A4_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000001A4) +#ifdef USE_PRIVATE_BF +#define BF_BF_9658CC5F_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001A4), 0x00000300 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_9658CC5F_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001A4), 0x00000103 + +#define REG_REG_0X01A8_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000001A8) +#ifdef USE_PRIVATE_BF +#define BF_BF_DC2E8285_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001A8), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_DC2E8285_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001A8), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_268FD896_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001A8), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_268FD896_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001A8), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_6B6E8283_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001A8), 0x00000508 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_6B6E8283_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001A8), 0x0000010D + +#define REG_REG_0X01AC_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000001AC) +#ifdef USE_PRIVATE_BF +#define BF_BF_6BCE4EAB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001AC), 0x00000300 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_6BCE4EAB_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001AC), 0x00000103 + +#define REG_REG_0X01B0_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000001B0) +#ifdef USE_PRIVATE_BF +#define BF_BF_4F961F18_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001B0), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_4F961F18_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001B0), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_6680B429_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001B0), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_6680B429_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001B0), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_8E0203E1_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001B0), 0x00000508 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_8E0203E1_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001B0), 0x0000010D + +#define REG_REG_0X01B4_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000001B4) +#ifdef USE_PRIVATE_BF +#define BF_BF_612FDDCF_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001B4), 0x00000300 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_612FDDCF_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001B4), 0x00000103 + +#define REG_REG_0X01B8_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000001B8) +#ifdef USE_PRIVATE_BF +#define BF_BF_1DA2547C_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001B8), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_1DA2547C_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001B8), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_E430F192_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001B8), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_E430F192_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001B8), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_27B8F94C_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001B8), 0x00000508 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_27B8F94C_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001B8), 0x0000010D + +#define REG_REG_0X01C4_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000001C4) +#ifdef USE_PRIVATE_BF +#define BF_BF_F32C451E_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001C4), 0x00000300 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_F32C451E_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001C4), 0x00000103 + +#define REG_REG_0X01C8_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000001C8) +#ifdef USE_PRIVATE_BF +#define BF_BF_D6AABA16_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001C8), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_D6AABA16_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001C8), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_B00F6B93_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001C8), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_B00F6B93_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001C8), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_F1137625_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001C8), 0x00000508 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_F1137625_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001C8), 0x0000010D + +#define REG_REG_0X01CC_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000001CC) + +#define REG_REG_0X01D0_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000001D0) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X01D4_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000001D4) +#define BF_BF_34BC2DC7_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001D4), 0x00000100 +#define BF_BF_23CEB507_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001D4), 0x00000101 +#define BF_BF_9018E84F_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001D4), 0x00000102 +#define BF_BF_153FC4E0_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001D4), 0x00000103 +#define BF_BF_FD479377_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001D4), 0x00000104 +#define BF_BF_819337B6_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001D4), 0x00000105 +#define BF_BF_F4A1EDA4_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001D4), 0x00000107 +#define BF_BF_8528D94D_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001D4), 0x00000108 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X01D8_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000001D8) +#define BF_BF_C0BCC740_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001D8), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X01DC_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000001DC) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X01E0_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000001E0) +#define BF_BF_BBD1A61F_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001E0), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X01E4_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000001E4) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X01E8_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000001E8) +#define BF_BF_CFA1A74A_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001E8), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X01EC_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000001EC) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X01F0_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000001F0) +#define BF_BF_9CDC1423_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001F0), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X01F4_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000001F4) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X01F8_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000001F8) +#define BF_BF_8D590883_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000001F8), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X01FC_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000001FC) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0200_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000200) +#define BF_BF_08B4682B_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000200), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0204_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000204) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0210_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000210) +#define BF_BF_3372594F_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000210), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0214_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000214) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0218_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000218) +#define BF_BF_80AA4B94_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000218), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X021C_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000021C) + +#define REG_REG_0X0220_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst, n) ((inst) + 0x00000220 + 4 * (n)) + +#define REG_REG_0X0244_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst, n) ((inst) + 0x00000244 + 4 * (n)) + +#define REG_REG_0X0268_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst, n) ((inst) + 0x00000268 + 4 * (n)) + +#define REG_REG_0X028C_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst, n) ((inst) + 0x0000028C + 4 * (n)) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X02B0_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000002B0) +#define BF_BF_83E000B8_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000002B0), 0x00001500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X02B4_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000002B4) +#define BF_BF_BA00FBEA_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000002B4), 0x00001500 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X02B8_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000002B8) + +#define REG_REG_0X02BC_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000002BC) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X02C0_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000002C0) +#define BF_BF_CEE2B5CB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000002C0), 0x00000100 +#define BF_BF_8A88506E_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000002C0), 0x00000102 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X02D0_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000002D0) +#define BF_BF_B10B6B72_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000002D0), 0x00000100 +#define BF_BF_1173FB44_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000002D0), 0x00000304 +#define BF_BF_6E44740D_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000002D0), 0x00000107 +#define BF_BF_21D0FDD2_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000002D0), 0x00000508 +#define BF_BF_0ADDB6F6_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000002D0), 0x00000510 +#define BF_BF_DB09B423_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000002D0), 0x00000818 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X02D4_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000002D4) + +#define REG_REG_0X0300_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst, n) ((inst) + 0x00000300 + 4 * (n)) + +#define REG_REG_0X0380_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000380) + +#define REG_REG_0X0384_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000384) + +#define REG_REG_0X0388_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000388) + +#define REG_REG_0X0390_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000390) + +#define REG_REG_0X0394_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst, n) ((inst) + 0x00000394 + 4 * (n)) + +#define REG_REG_0X03B8_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000003B8) +#ifdef USE_PRIVATE_BF +#define BF_BF_AB9D1A93_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000003B8), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_AB9D1A93_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000003B8), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_8B2DD03F_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000003B8), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_8B2DD03F_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000003B8), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_DF4C1F1C_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000003B8), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_DF4C1F1C_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000003B8), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_5A94F853_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000003B8), 0x00000106 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_5A94F853_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000003B8), 0x00000107 +#ifdef USE_PRIVATE_BF +#define BF_BF_DFDF6717_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000003B8), 0x00000108 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_DFDF6717_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000003B8), 0x00000109 +#ifdef USE_PRIVATE_BF +#define BF_BF_2A106DB9_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000003B8), 0x0000010C +#endif /* USE_PRIVATE_BF */ +#define BF_BF_2A106DB9_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000003B8), 0x0000010D +#ifdef USE_PRIVATE_BF +#define BF_BF_C8DCAF93_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000003B8), 0x0000090E +#endif /* USE_PRIVATE_BF */ +#define BF_BF_C8DCAF93_WEB_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000003B8), 0x00000117 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X03BC_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000003BC) +#define BF_BF_DDBBD610_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000003BC), 0x00000100 +#define BF_BF_5EC297FF_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000003BC), 0x00000101 +#define BF_BF_80C6E8BE_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000003BC), 0x00000102 +#define BF_BF_61262D7E_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000003BC), 0x00000103 +#define BF_BF_9A5D4E20_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000003BC), 0x00000104 +#define BF_BF_927D900E_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000003BC), 0x00000105 +#define BF_BF_DABE39F7_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000003BC), 0x00000106 +#define BF_BF_2B113489_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000003BC), 0x00000107 +#define BF_BF_D88809F8_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000003BC), 0x00000108 +#define BF_BF_66A4D584_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000003BC), 0x00000109 +#define BF_BF_55FD00E6_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000003BC), 0x0000010A +#define BF_BF_214F12BE_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000003BC), 0x0000010B +#define BF_BF_85CB74CC_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000003BC), 0x0000010C +#define BF_BF_BA3DEBCE_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000003BC), 0x0000010D +#define BF_BF_F541A0E2_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000003BC), 0x00000110 +#define BF_BF_AF396B85_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000003BC), 0x00000111 +#endif /* USE_PRIVATE_BF */ + +#define REG_FCAL_SCRATCH_END_VENUS_FCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000007FC) +#define BF_FCAL_SCRATCH_END_VENUS_FCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000007FC), 0x00002000 + +#endif /* __ADI_APOLLO_BF_VENUS_FCAL_BROADCAST_OPEN_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_venus_fcal_open.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_venus_fcal_open.h new file mode 100644 index 00000000000000..7e756b6ece4e7f --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_venus_fcal_open.h @@ -0,0 +1,581 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:20 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_VENUS_FCAL_OPEN_H__ +#define __ADI_APOLLO_BF_VENUS_FCAL_OPEN_H__ + +/*============= D E F I N E S ==============*/ +#define VENUS_FCAL_REGMAP0_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x60287000 +#define VENUS_FCAL_REGMAP1_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x60287800 +#define VENUS_FCAL_REGMAP2_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x60288000 +#define VENUS_FCAL_REGMAP3_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x60288800 +#define VENUS_FCAL_REGMAP4_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x60289000 +#define VENUS_FCAL_REGMAP5_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x60289800 +#define VENUS_FCAL_REGMAP6_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x6028A000 +#define VENUS_FCAL_REGMAP7_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x6028A800 +#define VENUS_FCAL_REGMAP0_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x60487000 +#define VENUS_FCAL_REGMAP1_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x60487800 +#define VENUS_FCAL_REGMAP2_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x60488000 +#define VENUS_FCAL_REGMAP3_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x60488800 +#define VENUS_FCAL_REGMAP4_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x60489000 +#define VENUS_FCAL_REGMAP5_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x60489800 +#define VENUS_FCAL_REGMAP6_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x6048A000 +#define VENUS_FCAL_REGMAP7_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x6048A800 +#define VENUS_FCAL_REGMAP0_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A87000 +#define VENUS_FCAL_REGMAP1_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A87800 +#define VENUS_FCAL_REGMAP2_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A88000 +#define VENUS_FCAL_REGMAP3_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A88800 +#define VENUS_FCAL_REGMAP4_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A89000 +#define VENUS_FCAL_REGMAP5_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A89800 +#define VENUS_FCAL_REGMAP6_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A8A000 +#define VENUS_FCAL_REGMAP7_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A8A800 +#define VENUS_FCAL_REGMAP0_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C87000 +#define VENUS_FCAL_REGMAP1_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C87800 +#define VENUS_FCAL_REGMAP2_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C88000 +#define VENUS_FCAL_REGMAP3_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C88800 +#define VENUS_FCAL_REGMAP4_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C89000 +#define VENUS_FCAL_REGMAP5_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C89800 +#define VENUS_FCAL_REGMAP6_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C8A000 +#define VENUS_FCAL_REGMAP7_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C8A800 + +#define REG_FCAL_SCRATCH_BEGIN_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x00000000) +#define BF_FCAL_SCRATCH_BEGIN_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000000), 0x00002000 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0004_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x00000004) +#define BF_BF_70D31378_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000004), 0x00000500 +#define BF_BF_AE9D973E_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000004), 0x00000107 +#define BF_BF_E3872070_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000004), 0x00000408 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0008_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x00000008) +#define BF_BF_95E42D3D_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000008), 0x00001508 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0010_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x00000010) +#ifdef USE_PRIVATE_BF +#define BF_BF_9811EAE1_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000010), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_9811EAE1_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000010), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_27E0F6ED_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000010), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_27E0F6ED_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000010), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_1ADEB97E_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000010), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_1ADEB97E_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000010), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_0F77D67B_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000010), 0x00000106 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_0F77D67B_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000010), 0x00000107 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0014_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x00000014) +#define BF_BF_FD5AEA08_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000014), 0x00000800 +#define BF_BF_226FC1E7_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000014), 0x00000808 +#define BF_BF_78F9304A_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000014), 0x00000810 +#define BF_BF_364A15DC_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000014), 0x00000818 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0018_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x00000018) +#define BF_BF_B263A595_INFO(inst) ((inst) + 0x00000018), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0038_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x00000038) +#define BF_BF_32EF326F_INFO(inst) ((inst) + 0x00000038), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0058_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x00000058) +#define BF_BF_4CA57706_INFO(inst) ((inst) + 0x00000058), 0x00004000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0088_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x00000088) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X00B8_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000000B8) +#define BF_BF_2CF16EA5_INFO(inst) ((inst) + 0x000000B8), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0118_VENUS_FCAL__OPEN_ADDR(inst, n) ((inst) + 0x00000118 + 4 * (n)) +#define BF_BF_4148A6B6_VENUS_FCAL__OPEN_INFO(inst, n) ((inst) + 0x00000118 + 4 * (n)), 0x00001508 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0120_VENUS_FCAL__OPEN_ADDR(inst, n) ((inst) + 0x00000120 + 4 * (n)) +#define BF_BF_960D50F4_INFO(inst, n) ((inst) + 0x00000120 + 4 * (n)), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0128_VENUS_FCAL__OPEN_ADDR(inst, n) ((inst) + 0x00000128 + 4 * (n)) +#define BF_BF_398889CE_VENUS_FCAL__OPEN_INFO(inst, n) ((inst) + 0x00000128 + 4 * (n)), 0x00001508 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0130_VENUS_FCAL__OPEN_ADDR(inst, n) ((inst) + 0x00000130 + 4 * (n)) +#define BF_BF_67C0DF75_INFO(inst, n) ((inst) + 0x00000130 + 4 * (n)), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0144_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x00000144) +#define BF_BF_82A6F3DA_INFO(inst) ((inst) + 0x00000144), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0184_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x00000184) +#ifdef USE_PRIVATE_BF +#define BF_BF_C5135C52_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_C5135C52_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_39861C20_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_39861C20_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_7CB8B9B0_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_7CB8B9B0_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_B0D333EE_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000106 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_B0D333EE_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000107 +#ifdef USE_PRIVATE_BF +#define BF_BF_D4A3F5FF_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000108 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_D4A3F5FF_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000109 +#ifdef USE_PRIVATE_BF +#define BF_BF_EC817610_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000184), 0x0000010C +#endif /* USE_PRIVATE_BF */ +#define BF_BF_EC817610_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000184), 0x0000010D +#ifdef USE_PRIVATE_BF +#define BF_BF_FB5A9FD4_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000184), 0x0000010E +#endif /* USE_PRIVATE_BF */ +#define BF_BF_FB5A9FD4_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000184), 0x0000010F +#ifdef USE_PRIVATE_BF +#define BF_BF_7FA84C3E_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000110 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_7FA84C3E_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000111 +#ifdef USE_PRIVATE_BF +#define BF_BF_08328F9C_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000112 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_08328F9C_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000113 +#ifdef USE_PRIVATE_BF +#define BF_BF_938A3AC2_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000114 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_938A3AC2_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000184), 0x00000115 + +#define REG_REG_0X0188_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x00000188) +#ifdef USE_PRIVATE_BF +#define BF_BF_A217FBDF_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000188), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_A217FBDF_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000188), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_CE0AFDEA_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000188), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_CE0AFDEA_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000188), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_96EB681F_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000188), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_96EB681F_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000188), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_46B6F335_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000188), 0x00000106 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_46B6F335_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000188), 0x00000107 +#ifdef USE_PRIVATE_BF +#define BF_BF_87DFCBB4_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000188), 0x00000108 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_87DFCBB4_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000188), 0x00000109 +#ifdef USE_PRIVATE_BF +#define BF_BF_8E62455B_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000188), 0x0000010A +#endif /* USE_PRIVATE_BF */ +#define BF_BF_8E62455B_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000188), 0x0000010B + +#define REG_REG_0X018C_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x0000018C) +#ifdef USE_PRIVATE_BF +#define BF_BF_C99662C6_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x0000018C), 0x00000200 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_C99662C6_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x0000018C), 0x00000102 +#ifdef USE_PRIVATE_BF +#define BF_BF_69F16890_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x0000018C), 0x00000203 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_69F16890_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x0000018C), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_13059625_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x0000018C), 0x00000106 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_13059625_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x0000018C), 0x00000107 + +#define REG_REG_0X0190_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x00000190) +#ifdef USE_PRIVATE_BF +#define BF_BF_D38298F0_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000190), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_D38298F0_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000190), 0x00000101 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0194_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x00000194) +#define BF_BF_419A5D0E_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000194), 0x00000800 +#define BF_BF_100E7AD9_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000194), 0x00000808 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0198_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x00000198) +#define BF_BF_3473A519_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000198), 0x00000300 +#define BF_BF_4643E55A_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000198), 0x00000304 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X019C_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x0000019C) +#ifdef USE_PRIVATE_BF +#define BF_BF_A63FA2F8_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x0000019C), 0x00000300 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_A63FA2F8_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x0000019C), 0x00000103 + +#define REG_REG_0X01A0_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000001A0) +#ifdef USE_PRIVATE_BF +#define BF_BF_D327F78A_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001A0), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_D327F78A_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001A0), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_C07E65B3_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001A0), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_C07E65B3_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001A0), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_3F783369_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001A0), 0x00000508 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_3F783369_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001A0), 0x0000010D + +#define REG_REG_0X01A4_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000001A4) +#ifdef USE_PRIVATE_BF +#define BF_BF_9658CC5F_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001A4), 0x00000300 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_9658CC5F_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001A4), 0x00000103 + +#define REG_REG_0X01A8_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000001A8) +#ifdef USE_PRIVATE_BF +#define BF_BF_DC2E8285_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001A8), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_DC2E8285_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001A8), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_268FD896_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001A8), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_268FD896_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001A8), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_6B6E8283_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001A8), 0x00000508 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_6B6E8283_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001A8), 0x0000010D + +#define REG_REG_0X01AC_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000001AC) +#ifdef USE_PRIVATE_BF +#define BF_BF_6BCE4EAB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001AC), 0x00000300 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_6BCE4EAB_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001AC), 0x00000103 + +#define REG_REG_0X01B0_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000001B0) +#ifdef USE_PRIVATE_BF +#define BF_BF_4F961F18_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001B0), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_4F961F18_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001B0), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_6680B429_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001B0), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_6680B429_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001B0), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_8E0203E1_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001B0), 0x00000508 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_8E0203E1_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001B0), 0x0000010D + +#define REG_REG_0X01B4_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000001B4) +#ifdef USE_PRIVATE_BF +#define BF_BF_612FDDCF_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001B4), 0x00000300 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_612FDDCF_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001B4), 0x00000103 + +#define REG_REG_0X01B8_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000001B8) +#ifdef USE_PRIVATE_BF +#define BF_BF_1DA2547C_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001B8), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_1DA2547C_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001B8), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_E430F192_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001B8), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_E430F192_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001B8), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_27B8F94C_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001B8), 0x00000508 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_27B8F94C_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001B8), 0x0000010D + +#define REG_REG_0X01C4_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000001C4) +#ifdef USE_PRIVATE_BF +#define BF_BF_F32C451E_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001C4), 0x00000300 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_F32C451E_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001C4), 0x00000103 + +#define REG_REG_0X01C8_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000001C8) +#ifdef USE_PRIVATE_BF +#define BF_BF_D6AABA16_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001C8), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_D6AABA16_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001C8), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_B00F6B93_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001C8), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_B00F6B93_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001C8), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_F1137625_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001C8), 0x00000508 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_F1137625_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001C8), 0x0000010D + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X01CC_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000001CC) +#define BF_BF_F1E4CA3F_INFO(inst) ((inst) + 0x000001CC), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X01D0_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000001D0) +#define BF_BF_565759C1_INFO(inst) ((inst) + 0x000001D0), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X01D4_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000001D4) +#define BF_BF_34BC2DC7_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001D4), 0x00000100 +#define BF_BF_23CEB507_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001D4), 0x00000101 +#define BF_BF_9018E84F_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001D4), 0x00000102 +#define BF_BF_153FC4E0_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001D4), 0x00000103 +#define BF_BF_FD479377_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001D4), 0x00000104 +#define BF_BF_819337B6_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001D4), 0x00000105 +#define BF_BF_F4A1EDA4_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001D4), 0x00000107 +#define BF_BF_8528D94D_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001D4), 0x00000108 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X01D8_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000001D8) +#define BF_BF_C0BCC740_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001D8), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X01DC_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000001DC) +#define BF_BF_91C8B049_INFO(inst) ((inst) + 0x000001DC), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X01E0_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000001E0) +#define BF_BF_BBD1A61F_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001E0), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X01E4_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000001E4) +#define BF_BF_83226F2E_INFO(inst) ((inst) + 0x000001E4), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X01E8_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000001E8) +#define BF_BF_CFA1A74A_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001E8), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X01EC_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000001EC) +#define BF_BF_D1BBB026_INFO(inst) ((inst) + 0x000001EC), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X01F0_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000001F0) +#define BF_BF_9CDC1423_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001F0), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X01F4_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000001F4) +#define BF_BF_AA42E05E_INFO(inst) ((inst) + 0x000001F4), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X01F8_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000001F8) +#define BF_BF_8D590883_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000001F8), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X01FC_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000001FC) +#define BF_BF_6451CED1_INFO(inst) ((inst) + 0x000001FC), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0200_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x00000200) +#define BF_BF_08B4682B_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000200), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0204_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x00000204) +#define BF_BF_D4420C10_INFO(inst) ((inst) + 0x00000204), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0210_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x00000210) +#define BF_BF_3372594F_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000210), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0214_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x00000214) +#define BF_BF_C3E7B4D2_INFO(inst) ((inst) + 0x00000214), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0218_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x00000218) +#define BF_BF_80AA4B94_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x00000218), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X021C_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x0000021C) +#define BF_BF_03298689_INFO(inst) ((inst) + 0x0000021C), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0220_VENUS_FCAL__OPEN_ADDR(inst, n) ((inst) + 0x00000220 + 4 * (n)) +#define BF_BF_D7A38C69_INFO(inst, n) ((inst) + 0x00000220 + 4 * (n)), 0x00004000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0244_VENUS_FCAL__OPEN_ADDR(inst, n) ((inst) + 0x00000244 + 4 * (n)) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0268_VENUS_FCAL__OPEN_ADDR(inst, n) ((inst) + 0x00000268 + 4 * (n)) +#define BF_BF_452FAE76_INFO(inst, n) ((inst) + 0x00000268 + 4 * (n)), 0x00004000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X028C_VENUS_FCAL__OPEN_ADDR(inst, n) ((inst) + 0x0000028C + 4 * (n)) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X02B0_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000002B0) +#define BF_BF_83E000B8_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000002B0), 0x00001500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X02B4_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000002B4) +#define BF_BF_BA00FBEA_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000002B4), 0x00001500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X02B8_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000002B8) +#define BF_BF_9E455DE0_INFO(inst) ((inst) + 0x000002B8), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X02BC_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000002BC) +#define BF_BF_AEF29814_INFO(inst) ((inst) + 0x000002BC), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X02C0_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000002C0) +#define BF_BF_CEE2B5CB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000002C0), 0x00000100 +#define BF_BF_8A88506E_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000002C0), 0x00000102 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X02D0_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000002D0) +#define BF_BF_B10B6B72_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000002D0), 0x00000100 +#define BF_BF_1173FB44_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000002D0), 0x00000304 +#define BF_BF_6E44740D_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000002D0), 0x00000107 +#define BF_BF_21D0FDD2_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000002D0), 0x00000508 +#define BF_BF_0ADDB6F6_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000002D0), 0x00000510 +#define BF_BF_DB09B423_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000002D0), 0x00000818 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X02D4_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000002D4) +#define BF_BF_38C26EA2_INFO(inst) ((inst) + 0x000002D4), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0300_VENUS_FCAL__OPEN_ADDR(inst, n) ((inst) + 0x00000300 + 4 * (n)) +#define BF_BF_3039D2A8_INFO(inst, n) ((inst) + 0x00000300 + 4 * (n)), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0380_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x00000380) +#define BF_BF_1055F572_INFO(inst) ((inst) + 0x00000380), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0384_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x00000384) +#define BF_BF_55714486_INFO(inst) ((inst) + 0x00000384), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0388_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x00000388) +#define BF_BF_15F3DBF8_INFO(inst) ((inst) + 0x00000388), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0390_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x00000390) +#define BF_BF_E92C8CBD_INFO(inst) ((inst) + 0x00000390), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0394_VENUS_FCAL__OPEN_ADDR(inst, n) ((inst) + 0x00000394 + 4 * (n)) +#define BF_BF_0692F660_INFO(inst, n) ((inst) + 0x00000394 + 4 * (n)), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X03B8_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000003B8) +#ifdef USE_PRIVATE_BF +#define BF_BF_AB9D1A93_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000003B8), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_AB9D1A93_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000003B8), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_8B2DD03F_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000003B8), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_8B2DD03F_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000003B8), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_DF4C1F1C_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000003B8), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_DF4C1F1C_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000003B8), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_5A94F853_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000003B8), 0x00000106 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_5A94F853_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000003B8), 0x00000107 +#ifdef USE_PRIVATE_BF +#define BF_BF_DFDF6717_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000003B8), 0x00000108 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_DFDF6717_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000003B8), 0x00000109 +#ifdef USE_PRIVATE_BF +#define BF_BF_2A106DB9_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000003B8), 0x0000010C +#endif /* USE_PRIVATE_BF */ +#define BF_BF_2A106DB9_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000003B8), 0x0000010D +#ifdef USE_PRIVATE_BF +#define BF_BF_C8DCAF93_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000003B8), 0x0000090E +#endif /* USE_PRIVATE_BF */ +#define BF_BF_C8DCAF93_WEB_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000003B8), 0x00000117 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X03BC_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000003BC) +#define BF_BF_DDBBD610_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000003BC), 0x00000100 +#define BF_BF_5EC297FF_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000003BC), 0x00000101 +#define BF_BF_80C6E8BE_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000003BC), 0x00000102 +#define BF_BF_61262D7E_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000003BC), 0x00000103 +#define BF_BF_9A5D4E20_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000003BC), 0x00000104 +#define BF_BF_927D900E_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000003BC), 0x00000105 +#define BF_BF_DABE39F7_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000003BC), 0x00000106 +#define BF_BF_2B113489_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000003BC), 0x00000107 +#define BF_BF_D88809F8_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000003BC), 0x00000108 +#define BF_BF_66A4D584_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000003BC), 0x00000109 +#define BF_BF_55FD00E6_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000003BC), 0x0000010A +#define BF_BF_214F12BE_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000003BC), 0x0000010B +#define BF_BF_85CB74CC_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000003BC), 0x0000010C +#define BF_BF_BA3DEBCE_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000003BC), 0x0000010D +#define BF_BF_F541A0E2_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000003BC), 0x00000110 +#define BF_BF_AF396B85_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000003BC), 0x00000111 +#endif /* USE_PRIVATE_BF */ + +#define REG_FCAL_SCRATCH_END_VENUS_FCAL__OPEN_ADDR(inst) ((inst) + 0x000007FC) +#define BF_FCAL_SCRATCH_END_VENUS_FCAL__OPEN_INFO(inst) ((inst) + 0x000007FC), 0x00002000 + +#endif /* __ADI_APOLLO_BF_VENUS_FCAL_OPEN_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_venus_ical_broadcast_open.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_venus_ical_broadcast_open.h new file mode 100644 index 00000000000000..6304d5fe2accb0 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_venus_ical_broadcast_open.h @@ -0,0 +1,78 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:20 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_VENUS_ICAL_BROADCAST_OPEN_H__ +#define __ADI_APOLLO_BF_VENUS_ICAL_BROADCAST_OPEN_H__ + +/*============= D E F I N E S ==============*/ +#define VENUS_ICAL_BROADCAST_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x6028B000 +#define VENUS_ICAL_BROADCAST_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x6048B000 +#define VENUS_ICAL_BROADCAST_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A8B000 +#define VENUS_ICAL_BROADCAST_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C8B000 + +#define REG_ICAL_SCRATCH_BEGIN_VENUS_ICAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000000) +#define BF_ICAL_SCRATCH_BEGIN_VENUS_ICAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000000), 0x00002000 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0004_VENUS_ICAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000004) +#define BF_BF_BD620D06_VENUS_ICAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000004), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0008_VENUS_ICAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000008) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X000C_VENUS_ICAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000000C) +#define BF_BF_7CB52A3F_VENUS_ICAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000000C), 0x00000300 +#define BF_BF_D296E6CA_VENUS_ICAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000000C), 0x00000304 +#define BF_BF_4C2C6025_VENUS_ICAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000000C), 0x00000308 +#define BF_BF_3880FAE8_VENUS_ICAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000000C), 0x0000030C +#define BF_BF_A0453F15_VENUS_ICAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000000C), 0x00000310 +#define BF_BF_69400B27_VENUS_ICAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000000C), 0x00000314 +#define BF_BF_8C1CBE2A_VENUS_ICAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000000C), 0x00000318 +#define BF_BF_24FE7242_VENUS_ICAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000000C), 0x0000031C +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0010_VENUS_ICAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000010) +#define BF_BF_B5BD3244_VENUS_ICAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000010), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0014_VENUS_ICAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000014) +#define BF_BF_7636BB0C_VENUS_ICAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000014), 0x00001200 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0018_VENUS_ICAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000018) + +#define REG_REG_0X001C_VENUS_ICAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000001C) + +#define REG_REG_0X0020_VENUS_ICAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000020) + +#define REG_REG_0X0024_VENUS_ICAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000024) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0028_VENUS_ICAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000028) +#define BF_BF_1EC9BB81_VENUS_ICAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000028), 0x00001500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X002C_VENUS_ICAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000002C) +#define BF_BF_2F42F9D5_VENUS_ICAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000002C), 0x00001500 +#endif /* USE_PRIVATE_BF */ + +#define REG_ICAL_SCRATCH_END_VENUS_ICAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000007FC) +#define BF_ICAL_SCRATCH_END_VENUS_ICAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000007FC), 0x00002000 + +#endif /* __ADI_APOLLO_BF_VENUS_ICAL_BROADCAST_OPEN_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_venus_ical_open.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_venus_ical_open.h new file mode 100644 index 00000000000000..5d4985f73b75e7 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_venus_ical_open.h @@ -0,0 +1,124 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:20 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_VENUS_ICAL_OPEN_H__ +#define __ADI_APOLLO_BF_VENUS_ICAL_OPEN_H__ + +/*============= D E F I N E S ==============*/ +#define VENUS_ICAL_REGMAP0_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x6028B800 +#define VENUS_ICAL_REGMAP1_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x6028C000 +#define VENUS_ICAL_REGMAP2_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x6028C800 +#define VENUS_ICAL_REGMAP3_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x6028D000 +#define VENUS_ICAL_REGMAP4_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x6028D800 +#define VENUS_ICAL_REGMAP5_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x6028E000 +#define VENUS_ICAL_REGMAP6_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x6028E800 +#define VENUS_ICAL_REGMAP7_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x6028F000 +#define VENUS_ICAL_REGMAP0_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x6048B800 +#define VENUS_ICAL_REGMAP1_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x6048C000 +#define VENUS_ICAL_REGMAP2_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x6048C800 +#define VENUS_ICAL_REGMAP3_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x6048D000 +#define VENUS_ICAL_REGMAP4_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x6048D800 +#define VENUS_ICAL_REGMAP5_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x6048E000 +#define VENUS_ICAL_REGMAP6_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x6048E800 +#define VENUS_ICAL_REGMAP7_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x6048F000 +#define VENUS_ICAL_REGMAP0_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A8B800 +#define VENUS_ICAL_REGMAP1_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A8C000 +#define VENUS_ICAL_REGMAP2_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A8C800 +#define VENUS_ICAL_REGMAP3_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A8D000 +#define VENUS_ICAL_REGMAP4_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A8D800 +#define VENUS_ICAL_REGMAP5_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A8E000 +#define VENUS_ICAL_REGMAP6_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A8E800 +#define VENUS_ICAL_REGMAP7_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A8F000 +#define VENUS_ICAL_REGMAP0_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C8B800 +#define VENUS_ICAL_REGMAP1_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C8C000 +#define VENUS_ICAL_REGMAP2_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C8C800 +#define VENUS_ICAL_REGMAP3_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C8D000 +#define VENUS_ICAL_REGMAP4_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C8D800 +#define VENUS_ICAL_REGMAP5_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C8E000 +#define VENUS_ICAL_REGMAP6_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C8E800 +#define VENUS_ICAL_REGMAP7_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C8F000 + +#define REG_ICAL_SCRATCH_BEGIN_VENUS_ICAL__OPEN_ADDR(inst) ((inst) + 0x00000000) +#define BF_ICAL_SCRATCH_BEGIN_VENUS_ICAL__OPEN_INFO(inst) ((inst) + 0x00000000), 0x00002000 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0004_VENUS_ICAL__OPEN_ADDR(inst) ((inst) + 0x00000004) +#define BF_BF_BD620D06_VENUS_ICAL__OPEN_INFO(inst) ((inst) + 0x00000004), 0x00000100 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0008_VENUS_ICAL__OPEN_ADDR(inst) ((inst) + 0x00000008) +#define BF_BF_A527D04B_INFO(inst) ((inst) + 0x00000008), 0x00000100 +#define BF_BF_3DAB5E7F_INFO(inst) ((inst) + 0x00000008), 0x00000101 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X000C_VENUS_ICAL__OPEN_ADDR(inst) ((inst) + 0x0000000C) +#define BF_BF_7CB52A3F_VENUS_ICAL__OPEN_INFO(inst) ((inst) + 0x0000000C), 0x00000300 +#define BF_BF_D296E6CA_VENUS_ICAL__OPEN_INFO(inst) ((inst) + 0x0000000C), 0x00000304 +#define BF_BF_4C2C6025_VENUS_ICAL__OPEN_INFO(inst) ((inst) + 0x0000000C), 0x00000308 +#define BF_BF_3880FAE8_VENUS_ICAL__OPEN_INFO(inst) ((inst) + 0x0000000C), 0x0000030C +#define BF_BF_A0453F15_VENUS_ICAL__OPEN_INFO(inst) ((inst) + 0x0000000C), 0x00000310 +#define BF_BF_69400B27_VENUS_ICAL__OPEN_INFO(inst) ((inst) + 0x0000000C), 0x00000314 +#define BF_BF_8C1CBE2A_VENUS_ICAL__OPEN_INFO(inst) ((inst) + 0x0000000C), 0x00000318 +#define BF_BF_24FE7242_VENUS_ICAL__OPEN_INFO(inst) ((inst) + 0x0000000C), 0x0000031C +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0010_VENUS_ICAL__OPEN_ADDR(inst) ((inst) + 0x00000010) +#define BF_BF_B5BD3244_VENUS_ICAL__OPEN_INFO(inst) ((inst) + 0x00000010), 0x00000500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0014_VENUS_ICAL__OPEN_ADDR(inst) ((inst) + 0x00000014) +#define BF_BF_7636BB0C_VENUS_ICAL__OPEN_INFO(inst) ((inst) + 0x00000014), 0x00001200 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0018_VENUS_ICAL__OPEN_ADDR(inst) ((inst) + 0x00000018) +#define BF_BF_07A65CC1_INFO(inst) ((inst) + 0x00000018), 0x00001200 +#define BF_BF_602BD5EC_INFO(inst) ((inst) + 0x00000018), 0x0000011F +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X001C_VENUS_ICAL__OPEN_ADDR(inst) ((inst) + 0x0000001C) +#define BF_BF_373F82E3_INFO(inst) ((inst) + 0x0000001C), 0x00001200 +#define BF_BF_BCE07784_INFO(inst) ((inst) + 0x0000001C), 0x0000011F +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0020_VENUS_ICAL__OPEN_ADDR(inst) ((inst) + 0x00000020) +#define BF_BF_0F0069B9_INFO(inst) ((inst) + 0x00000020), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0024_VENUS_ICAL__OPEN_ADDR(inst) ((inst) + 0x00000024) +#define BF_BF_ABC3056F_INFO(inst) ((inst) + 0x00000024), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0028_VENUS_ICAL__OPEN_ADDR(inst) ((inst) + 0x00000028) +#define BF_BF_1EC9BB81_VENUS_ICAL__OPEN_INFO(inst) ((inst) + 0x00000028), 0x00001500 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X002C_VENUS_ICAL__OPEN_ADDR(inst) ((inst) + 0x0000002C) +#define BF_BF_2F42F9D5_VENUS_ICAL__OPEN_INFO(inst) ((inst) + 0x0000002C), 0x00001500 +#endif /* USE_PRIVATE_BF */ + +#define REG_ICAL_SCRATCH_END_VENUS_ICAL__OPEN_ADDR(inst) ((inst) + 0x000007FC) +#define BF_ICAL_SCRATCH_END_VENUS_ICAL__OPEN_INFO(inst) ((inst) + 0x000007FC), 0x00002000 + +#endif /* __ADI_APOLLO_BF_VENUS_ICAL_OPEN_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_venus_scal_broadcast_open.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_venus_scal_broadcast_open.h new file mode 100644 index 00000000000000..3cef3bb0ae04d7 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_venus_scal_broadcast_open.h @@ -0,0 +1,899 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:20 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_VENUS_SCAL_BROADCAST_OPEN_H__ +#define __ADI_APOLLO_BF_VENUS_SCAL_BROADCAST_OPEN_H__ + +/*============= D E F I N E S ==============*/ +#define VENUS_SCAL_BROADCAST_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x60282000 +#define VENUS_SCAL_BROADCAST_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x60482000 +#define VENUS_SCAL_BROADCAST_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A82000 +#define VENUS_SCAL_BROADCAST_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C82000 + +#define REG_SCAL_SCRATCH_BEGIN_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000000) +#define BF_SCAL_SCRATCH_BEGIN_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000000), 0x00002000 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0004_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst, n) ((inst) + 0x00000004 + 4 * (n)) +#define BF_BF_507BA89F_VENUS_SCAL__BROADCAST_OPEN_INFO(inst, n) ((inst) + 0x00000004 + 4 * (n)), 0x00001108 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X001C_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst, n) ((inst) + 0x0000001C + 4 * (n)) +#define BF_BF_A4C77B32_VENUS_SCAL__BROADCAST_OPEN_INFO(inst, n) ((inst) + 0x0000001C + 4 * (n)), 0x00001308 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0034_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst, n) ((inst) + 0x00000034 + 4 * (n)) + +#define REG_REG_0X004C_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst, n) ((inst) + 0x0000004C + 4 * (n)) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0084_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst, n) ((inst) + 0x00000084 + 4 * (n)) +#define BF_BF_28B73B48_VENUS_SCAL__BROADCAST_OPEN_INFO(inst, n) ((inst) + 0x00000084 + 4 * (n)), 0x00001508 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0134_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst, n) ((inst) + 0x00000134 + 4 * (n)) + +#define REG_REG_0X0158_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst, n) ((inst) + 0x00000158 + 4 * (n)) + +#define REG_REG_0X017C_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst, n) ((inst) + 0x0000017C + 4 * (n)) + +#define REG_REG_0X01A0_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst, n) ((inst) + 0x000001A0 + 4 * (n)) + +#define REG_REG_0X01E4_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst, n) ((inst) + 0x000001E4 + 4 * (n)) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0204_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst, n) ((inst) + 0x00000204 + 4 * (n)) +#define BF_BF_92C0547B_VENUS_SCAL__BROADCAST_OPEN_INFO(inst, n) ((inst) + 0x00000204 + 4 * (n)), 0x00001508 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X020C_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000020C) + +#define REG_REG_0X022C_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000022C) + +#define REG_REG_0X024C_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000024C) + +#define REG_REG_0X0400_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000400) + +#define REG_REG_0X0404_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000404) + +#define REG_REG_0X0408_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000408) + +#define REG_REG_0X040C_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000040C) +#ifdef USE_PRIVATE_BF +#define BF_BF_4D25EF5C_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000040C), 0x00000200 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_4D25EF5C_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000040C), 0x00000102 +#ifdef USE_PRIVATE_BF +#define BF_BF_48F55CE0_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000040C), 0x00000203 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_48F55CE0_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000040C), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_38DA1C3D_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000040C), 0x00000206 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_38DA1C3D_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000040C), 0x00000108 + +#define REG_REG_0X0410_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000410) + +#define REG_REG_0X0414_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000414) + +#define REG_REG_0X0418_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000418) + +#define REG_REG_0X041C_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000041C) + +#define REG_REG_0X0420_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000420) + +#define REG_REG_0X0424_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000424) + +#define REG_REG_0X0428_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000428) +#ifdef USE_PRIVATE_BF +#define BF_BF_BAD86450_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000428), 0x00000600 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_BAD86450_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000428), 0x00000106 +#ifdef USE_PRIVATE_BF +#define BF_BF_0D9CF522_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000428), 0x00000607 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_0D9CF522_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000428), 0x0000010D + +#define REG_REG_0X042C_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000042C) + +#define REG_REG_0X0430_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000430) + +#define REG_REG_0X0434_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000434) + +#define REG_REG_0X0438_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000438) + +#define REG_REG_0X043C_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000043C) + +#define REG_REG_0X0440_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000440) + +#define REG_REG_0X0444_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000444) + +#define REG_REG_0X0448_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000448) + +#define REG_REG_0X044C_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000044C) + +#define REG_REG_0X0450_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000450) + +#define REG_REG_0X0454_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000454) + +#define REG_REG_0X0458_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000458) + +#define REG_REG_0X045C_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000045C) + +#define REG_REG_0X0460_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000460) + +#define REG_REG_0X0464_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000464) + +#define REG_REG_0X0468_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000468) + +#define REG_REG_0X046C_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000046C) +#ifdef USE_PRIVATE_BF +#define BF_BF_04FC627D_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000046C), 0x00000800 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_04FC627D_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000046C), 0x00000108 + +#define REG_REG_0X0470_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000470) +#ifdef USE_PRIVATE_BF +#define BF_BF_89FA30CF_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000470), 0x00000400 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_89FA30CF_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000470), 0x00000104 +#ifdef USE_PRIVATE_BF +#define BF_BF_83063494_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000470), 0x00000405 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_83063494_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000470), 0x00000109 +#ifdef USE_PRIVATE_BF +#define BF_BF_6073B2AA_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000470), 0x0000040A +#endif /* USE_PRIVATE_BF */ +#define BF_BF_6073B2AA_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000470), 0x0000010E +#ifdef USE_PRIVATE_BF +#define BF_BF_56C106E1_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000470), 0x0000040F +#endif /* USE_PRIVATE_BF */ +#define BF_BF_56C106E1_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000470), 0x00000113 +#ifdef USE_PRIVATE_BF +#define BF_BF_34407588_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000470), 0x00000414 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_34407588_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000470), 0x00000118 + +#define REG_REG_0X0474_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000474) +#ifdef USE_PRIVATE_BF +#define BF_BF_DAD827A3_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000474), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_DAD827A3_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000474), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_7BA7C73B_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000474), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_7BA7C73B_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000474), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_DBA82E9D_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000474), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_DBA82E9D_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000474), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_3098C59C_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000474), 0x00000106 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_3098C59C_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000474), 0x00000107 + +#define REG_REG_0X0478_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000478) +#ifdef USE_PRIVATE_BF +#define BF_BF_45F7874C_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000478), 0x00000400 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_45F7874C_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000478), 0x00000104 +#ifdef USE_PRIVATE_BF +#define BF_BF_32F08E3A_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000478), 0x00000405 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_32F08E3A_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000478), 0x00000109 +#ifdef USE_PRIVATE_BF +#define BF_BF_D797E7BF_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000478), 0x0000040A +#endif /* USE_PRIVATE_BF */ +#define BF_BF_D797E7BF_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000478), 0x0000010E + +#define REG_REG_0X047C_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000047C) +#ifdef USE_PRIVATE_BF +#define BF_BF_A432F804_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000047C), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_A432F804_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000047C), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_59DA3AA0_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000047C), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_59DA3AA0_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000047C), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_48B52FAE_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000047C), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_48B52FAE_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000047C), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_CEDBB6EE_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000047C), 0x00000106 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_CEDBB6EE_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000047C), 0x00000107 + +#define REG_REG_0X0480_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000480) +#ifdef USE_PRIVATE_BF +#define BF_BF_821BF1CA_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000480), 0x00000300 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_821BF1CA_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000480), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_27DD70A9_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000480), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_27DD70A9_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000480), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_AD4714AD_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000480), 0x00000206 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_AD4714AD_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000480), 0x00000108 + +#define REG_REG_0X0484_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000484) +#ifdef USE_PRIVATE_BF +#define BF_BF_5CA2D2B4_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000484), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_5CA2D2B4_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000484), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_CC0429E4_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000484), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_CC0429E4_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000484), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_67599BD7_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000484), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_67599BD7_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000484), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_B9D7C00F_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000484), 0x00000106 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_B9D7C00F_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000484), 0x00000107 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0488_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000488) +#define BF_BF_EC9E82E8_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000488), 0x00000800 +#define BF_BF_0818209E_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000488), 0x00000808 +#define BF_BF_B416D230_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000488), 0x00000810 +#define BF_BF_EACE3FE4_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000488), 0x00000818 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X048C_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000048C) +#ifdef USE_PRIVATE_BF +#define BF_BF_ED7193DA_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_ED7193DA_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_9F9E1975_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_9F9E1975_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_25552B6D_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_25552B6D_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_5E7E18C6_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000106 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_5E7E18C6_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000107 +#ifdef USE_PRIVATE_BF +#define BF_BF_F4D789F1_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000108 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_F4D789F1_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000109 +#ifdef USE_PRIVATE_BF +#define BF_BF_E1F9065C_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000048C), 0x0000010A +#endif /* USE_PRIVATE_BF */ +#define BF_BF_E1F9065C_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000048C), 0x0000010B +#ifdef USE_PRIVATE_BF +#define BF_BF_5B7943BD_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000048C), 0x0000010C +#endif /* USE_PRIVATE_BF */ +#define BF_BF_5B7943BD_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000048C), 0x0000010D +#ifdef USE_PRIVATE_BF +#define BF_BF_684D9C7E_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000048C), 0x0000010E +#endif /* USE_PRIVATE_BF */ +#define BF_BF_684D9C7E_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000048C), 0x0000010F +#ifdef USE_PRIVATE_BF +#define BF_BF_B483B9CE_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000112 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_B483B9CE_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000113 +#ifdef USE_PRIVATE_BF +#define BF_BF_C967ACFB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000114 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_C967ACFB_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000115 +#ifdef USE_PRIVATE_BF +#define BF_BF_9580F3CE_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000116 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_9580F3CE_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000117 +#ifdef USE_PRIVATE_BF +#define BF_BF_5B4B40B3_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000118 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_5B4B40B3_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000119 +#ifdef USE_PRIVATE_BF +#define BF_BF_6A3A083B_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000048C), 0x0000011A +#endif /* USE_PRIVATE_BF */ +#define BF_BF_6A3A083B_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000048C), 0x0000011B +#ifdef USE_PRIVATE_BF +#define BF_BF_D5CAD3F6_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000048C), 0x0000021C +#endif /* USE_PRIVATE_BF */ +#define BF_BF_D5CAD3F6_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000048C), 0x0000011E + +#define REG_REG_0X0490_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000490) +#ifdef USE_PRIVATE_BF +#define BF_BF_37ABA1A8_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000490), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_37ABA1A8_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000490), 0x00000101 + +#define REG_REG_0X0494_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000494) +#ifdef USE_PRIVATE_BF +#define BF_BF_4A6EADD0_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000494), 0x00000500 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_4A6EADD0_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000494), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_13A16383_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000494), 0x00000306 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_13A16383_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000494), 0x00000109 +#ifdef USE_PRIVATE_BF +#define BF_BF_C3BD2E36_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000494), 0x0000040A +#endif /* USE_PRIVATE_BF */ +#define BF_BF_C3BD2E36_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000494), 0x0000010E +#ifdef USE_PRIVATE_BF +#define BF_BF_49DD6537_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000494), 0x0000030F +#endif /* USE_PRIVATE_BF */ +#define BF_BF_49DD6537_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000494), 0x00000112 +#ifdef USE_PRIVATE_BF +#define BF_BF_FC7B85A0_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000494), 0x00000113 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_FC7B85A0_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000494), 0x00000114 +#ifdef USE_PRIVATE_BF +#define BF_BF_A946AEFC_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000494), 0x00000115 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_A946AEFC_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000494), 0x00000116 + +#define REG_REG_0X0498_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000498) +#ifdef USE_PRIVATE_BF +#define BF_BF_A0BA0FAB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000498), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_A0BA0FAB_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000498), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_1A41BF89_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000498), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_1A41BF89_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000498), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_73E79897_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000498), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_73E79897_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000498), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_54B73BD8_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000498), 0x00000106 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_54B73BD8_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000498), 0x00000107 +#ifdef USE_PRIVATE_BF +#define BF_BF_B0654939_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000498), 0x00000108 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_B0654939_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000498), 0x00000109 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X049C_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000049C) +#define BF_BF_0B8DA998_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000049C), 0x00000500 +#define BF_BF_40FAAB06_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000049C), 0x00000107 +#define BF_BF_9D6BE1C4_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000049C), 0x00000408 +#define BF_BF_72EE83E6_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000049C), 0x0000020D +#define BF_BF_6751217C_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000049C), 0x00000410 +#define BF_BF_0ABC4A65_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000049C), 0x00000418 +#define BF_BF_7465262C_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000049C), 0x0000031D +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X04A0_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000004A0) +#ifdef USE_PRIVATE_BF +#define BF_BF_D9F03C0D_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004A0), 0x00001000 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_D9F03C0D_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004A0), 0x00000110 + +#define REG_REG_0X04A4_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000004A4) +#ifdef USE_PRIVATE_BF +#define BF_BF_C5EB3B6B_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004A4), 0x00000C00 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_C5EB3B6B_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004A4), 0x0000010C +#ifdef USE_PRIVATE_BF +#define BF_BF_E123593E_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004A4), 0x0000080D +#endif /* USE_PRIVATE_BF */ +#define BF_BF_E123593E_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004A4), 0x00000115 +#ifdef USE_PRIVATE_BF +#define BF_BF_393452C1_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004A4), 0x00000416 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_393452C1_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004A4), 0x0000011A + +#define REG_REG_0X04A8_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000004A8) +#ifdef USE_PRIVATE_BF +#define BF_BF_762E9A1B_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004A8), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_762E9A1B_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004A8), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_EFCC4262_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004A8), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_EFCC4262_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004A8), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_5E9A28EB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004A8), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_5E9A28EB_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004A8), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_1BCD2E5C_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004A8), 0x00000106 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_1BCD2E5C_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004A8), 0x00000107 + +#define REG_REG_0X04AC_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000004AC) +#ifdef USE_PRIVATE_BF +#define BF_BF_2D4E0C9F_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004AC), 0x00000300 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_2D4E0C9F_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004AC), 0x00000103 + +#define REG_REG_0X04B0_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000004B0) +#ifdef USE_PRIVATE_BF +#define BF_BF_C0973401_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004B0), 0x00000300 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_C0973401_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004B0), 0x00000103 + +#define REG_REG_0X04B4_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000004B4) +#ifdef USE_PRIVATE_BF +#define BF_BF_D04D53CC_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004B4), 0x00000300 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_D04D53CC_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004B4), 0x00000103 + +#define REG_REG_0X04B8_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000004B8) +#ifdef USE_PRIVATE_BF +#define BF_BF_1CC10689_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004B8), 0x00000300 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_1CC10689_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004B8), 0x00000103 + +#define REG_REG_0X04BC_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000004BC) +#ifdef USE_PRIVATE_BF +#define BF_BF_28BB343D_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004BC), 0x00000300 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_28BB343D_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004BC), 0x00000103 + +#define REG_REG_0X04C0_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000004C0) +#ifdef USE_PRIVATE_BF +#define BF_BF_56104F9F_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004C0), 0x00000500 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_56104F9F_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004C0), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_15ACCE3B_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004C0), 0x00000506 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_15ACCE3B_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004C0), 0x0000010B +#ifdef USE_PRIVATE_BF +#define BF_BF_7A15F80D_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004C0), 0x0000050C +#endif /* USE_PRIVATE_BF */ +#define BF_BF_7A15F80D_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004C0), 0x00000111 +#ifdef USE_PRIVATE_BF +#define BF_BF_99D1F504_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004C0), 0x00000512 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_99D1F504_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004C0), 0x00000117 +#ifdef USE_PRIVATE_BF +#define BF_BF_71632961_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004C0), 0x00000518 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_71632961_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004C0), 0x0000011D + +#define REG_REG_0X04C4_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000004C4) +#ifdef USE_PRIVATE_BF +#define BF_BF_C515FC1B_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004C4), 0x0000010A +#endif /* USE_PRIVATE_BF */ +#define BF_BF_C515FC1B_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004C4), 0x0000010B +#ifdef USE_PRIVATE_BF +#define BF_BF_BF9D4E01_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004C4), 0x0000010C +#endif /* USE_PRIVATE_BF */ +#define BF_BF_BF9D4E01_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004C4), 0x0000010D +#ifdef USE_PRIVATE_BF +#define BF_BF_17A918A1_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004C4), 0x0000010E +#endif /* USE_PRIVATE_BF */ +#define BF_BF_17A918A1_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004C4), 0x0000010F +#ifdef USE_PRIVATE_BF +#define BF_BF_F585D73C_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004C4), 0x00000110 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_F585D73C_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004C4), 0x00000111 +#ifdef USE_PRIVATE_BF +#define BF_BF_60D96D7E_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004C4), 0x00000112 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_60D96D7E_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004C4), 0x00000113 + +#define REG_REG_0X04C8_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000004C8) +#ifdef USE_PRIVATE_BF +#define BF_BF_6E6DD6A6_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004C8), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_6E6DD6A6_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004C8), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_75358B68_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004C8), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_75358B68_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004C8), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_7260E949_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004C8), 0x00000108 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_7260E949_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004C8), 0x00000109 +#ifdef USE_PRIVATE_BF +#define BF_BF_7DDCFB88_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004C8), 0x0000050A +#endif /* USE_PRIVATE_BF */ +#define BF_BF_7DDCFB88_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004C8), 0x0000010F +#ifdef USE_PRIVATE_BF +#define BF_BF_815F65AE_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004C8), 0x00000110 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_815F65AE_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004C8), 0x00000111 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X04CC_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000004CC) +#define BF_BF_92EE659F_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000100 +#define BF_BF_9CE5B3DD_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000101 +#define BF_BF_997ED7A2_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000102 +#define BF_BF_8773591D_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000103 +#define BF_BF_2B51C820_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000104 +#define BF_BF_33785069_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000105 +#define BF_BF_43B42B61_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000106 +#define BF_BF_990DB6C3_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000107 +#define BF_BF_8AE80AAE_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000108 +#define BF_BF_ECF1FE4C_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000109 +#define BF_BF_3B9FA7CD_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004CC), 0x0000010A +#define BF_BF_F3ABEC40_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004CC), 0x0000010B +#define BF_BF_4459CB53_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004CC), 0x0000010C +#define BF_BF_9626B1AE_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004CC), 0x0000010D +#define BF_BF_F071661E_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004CC), 0x0000010E +#define BF_BF_C9385D2A_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004CC), 0x0000010F +#define BF_BF_905990E8_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000110 +#define BF_BF_ECC16671_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000111 +#define BF_BF_2D25984B_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000112 +#define BF_BF_90FE67B3_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000113 +#define BF_BF_46178217_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000114 +#define BF_BF_DA03E966_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000115 +#define BF_BF_9B05C98F_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000116 +#define BF_BF_D274852B_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000117 +#define BF_BF_54915CD0_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000118 +#define BF_BF_FE0CAE4C_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000119 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X04D4_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000004D4) +#ifdef USE_PRIVATE_BF +#define BF_BF_C53B812B_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004D4), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_C53B812B_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004D4), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_EB0FA4A2_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004D4), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_EB0FA4A2_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004D4), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_97354A59_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004D4), 0x00000404 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_97354A59_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004D4), 0x00000108 +#ifdef USE_PRIVATE_BF +#define BF_BF_CB643805_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004D4), 0x00000409 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_CB643805_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004D4), 0x0000010D +#ifdef USE_PRIVATE_BF +#define BF_BF_D2561460_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004D4), 0x0000010E +#endif /* USE_PRIVATE_BF */ +#define BF_BF_D2561460_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004D4), 0x0000010F + +#define REG_REG_0X04DC_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000004DC) + +#define REG_REG_0X04E0_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000004E0) +#ifdef USE_PRIVATE_BF +#define BF_BF_3F7D6943_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004E0), 0x00000200 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_3F7D6943_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004E0), 0x00000102 +#ifdef USE_PRIVATE_BF +#define BF_BF_1A6F84CA_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004E0), 0x00000203 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_1A6F84CA_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004E0), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_ADA50B94_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004E0), 0x00000206 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_ADA50B94_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004E0), 0x00000108 +#ifdef USE_PRIVATE_BF +#define BF_BF_77976C72_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004E0), 0x00000209 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_77976C72_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004E0), 0x0000010B +#ifdef USE_PRIVATE_BF +#define BF_BF_07F52F79_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004E0), 0x0000020C +#endif /* USE_PRIVATE_BF */ +#define BF_BF_07F52F79_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004E0), 0x0000010E + +#define REG_REG_0X04E4_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000004E4) +#ifdef USE_PRIVATE_BF +#define BF_BF_0DD44427_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004E4), 0x00000400 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_0DD44427_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004E4), 0x00000104 +#ifdef USE_PRIVATE_BF +#define BF_BF_BF879925_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004E4), 0x00000405 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_BF879925_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004E4), 0x00000109 +#ifdef USE_PRIVATE_BF +#define BF_BF_1476FFA8_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004E4), 0x0000040A +#endif /* USE_PRIVATE_BF */ +#define BF_BF_1476FFA8_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004E4), 0x0000010E +#ifdef USE_PRIVATE_BF +#define BF_BF_001C94C5_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004E4), 0x0000040F +#endif /* USE_PRIVATE_BF */ +#define BF_BF_001C94C5_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004E4), 0x00000113 +#ifdef USE_PRIVATE_BF +#define BF_BF_B3E34C3B_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004E4), 0x00000414 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_B3E34C3B_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004E4), 0x00000118 +#ifdef USE_PRIVATE_BF +#define BF_BF_92ECC13C_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004E4), 0x00000119 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_92ECC13C_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004E4), 0x0000011A + +#define REG_REG_0X04E8_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000004E8) +#ifdef USE_PRIVATE_BF +#define BF_BF_B5424714_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004E8), 0x00000300 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_B5424714_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004E8), 0x00000103 + +#define REG_REG_0X04EC_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000004EC) +#ifdef USE_PRIVATE_BF +#define BF_BF_3EBE01A9_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004EC), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_3EBE01A9_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004EC), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_B2862FC4_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004EC), 0x00000D04 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_B2862FC4_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004EC), 0x00000111 +#ifdef USE_PRIVATE_BF +#define BF_BF_3DB03CBF_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004EC), 0x00000D12 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_3DB03CBF_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004EC), 0x0000011F + +#define REG_REG_0X04F0_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000004F0) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X04F4_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000004F4) +#define BF_BF_4188D5E1_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004F4), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X04F8_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000004F8) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X04FC_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000004FC) +#define BF_BF_2F9A8F1A_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000004FC), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0500_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000500) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0504_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000504) +#define BF_BF_4FA1F584_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000504), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0508_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000508) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X050C_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000050C) +#define BF_BF_0B81DFC5_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000050C), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0510_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000510) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0514_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000514) +#define BF_BF_A4A947A9_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000514), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0518_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000518) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X051C_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000051C) +#define BF_BF_D1D80148_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000051C), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0520_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000520) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0524_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000524) +#define BF_BF_708AD7DF_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000524), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0528_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000528) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X052C_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000052C) +#define BF_BF_75851DAC_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000052C), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0530_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000530) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0534_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000534) +#define BF_BF_C3ED8B31_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000534), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0538_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000538) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X053C_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000053C) +#define BF_BF_7855ACBB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000053C), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0540_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000540) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0544_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000544) +#define BF_BF_4B3AFE05_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000544), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0548_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000548) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X054C_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000054C) +#define BF_BF_CF9F3639_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000054C), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0550_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000550) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0554_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000554) +#define BF_BF_D392D19B_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000554), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0558_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000558) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X055C_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000055C) +#define BF_BF_AB82BE1F_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000055C), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0560_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000560) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0564_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000564) +#define BF_BF_4EE09902_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000564), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0568_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000568) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X056C_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000056C) +#define BF_BF_ACDFF011_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000056C), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0570_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000570) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0574_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000574) +#define BF_BF_1E874AC1_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000574), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0578_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000578) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X057C_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000057C) +#define BF_BF_A5CB372A_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000057C), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0580_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000580) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0584_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000584) +#define BF_BF_3EE65425_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000584), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0588_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000588) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X058C_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000058C) +#define BF_BF_6434B1F4_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000058C), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0590_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000590) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0594_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000594) +#define BF_BF_962412FE_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000594), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0598_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000598) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X059C_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000059C) +#define BF_BF_23FA173C_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000059C), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X05A0_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000005A0) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X05A4_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000005A4) +#define BF_BF_2CF7CF41_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000005A4), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X05A8_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000005A8) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X05AC_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000005AC) +#define BF_BF_249EE9F7_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000005AC), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X05B0_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000005B0) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X05B4_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000005B4) +#define BF_BF_503461ED_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000005B4), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X05B8_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000005B8) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X05BC_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000005BC) +#define BF_BF_29476181_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000005BC), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X05C0_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000005C0) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X05C4_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000005C4) +#define BF_BF_B9E86EFE_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000005C4), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X05C8_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000005C8) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X05CC_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000005CC) +#define BF_BF_3925C0DE_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000005CC), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X05D0_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000005D0) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X05D4_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000005D4) +#define BF_BF_94B7FB06_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000005D4), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X05D8_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000005D8) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X05DC_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000005DC) +#define BF_BF_BC512F04_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000005DC), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X05E0_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000005E0) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X05E4_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000005E4) +#define BF_BF_D0EFDFC6_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000005E4), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X05E8_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000005E8) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X05EC_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000005EC) +#define BF_BF_42723B74_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000005EC), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X05F0_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000005F0) + +#define REG_REG_0X0600_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000600) +#ifdef USE_PRIVATE_BF +#define BF_BF_466C700F_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000600), 0x00000300 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_466C700F_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000600), 0x00000103 + +#define REG_REG_0X0604_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000604) +#ifdef USE_PRIVATE_BF +#define BF_BF_ED93AE22_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000604), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_ED93AE22_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000604), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_242F3948_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000604), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_242F3948_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000604), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_151077EC_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000604), 0x00000504 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_151077EC_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000604), 0x00000109 + +#define REG_REG_0X0608_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x00000608) +#ifdef USE_PRIVATE_BF +#define BF_BF_45ACACF6_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000608), 0x00000300 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_45ACACF6_WEB_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x00000608), 0x00000103 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X060C_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x0000060C) +#define BF_BF_A226534A_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x0000060C), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_SCAL_SCRATCH_END_VENUS_SCAL__BROADCAST_OPEN_ADDR(inst) ((inst) + 0x000007FC) +#define BF_SCAL_SCRATCH_END_VENUS_SCAL__BROADCAST_OPEN_INFO(inst) ((inst) + 0x000007FC), 0x00002000 + +#endif /* __ADI_APOLLO_BF_VENUS_SCAL_BROADCAST_OPEN_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_venus_scal_open.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_venus_scal_open.h new file mode 100644 index 00000000000000..402b3839a3ea81 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_venus_scal_open.h @@ -0,0 +1,1113 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 7/19/2021 9:28:20 PM. + * + * @copyright copyright(c) 2021 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_VENUS_SCAL_OPEN_H__ +#define __ADI_APOLLO_BF_VENUS_SCAL_OPEN_H__ + +/*============= D E F I N E S ==============*/ +#define VENUS_SCAL_REGMAP0_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x60282800 +#define VENUS_SCAL_REGMAP1_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x60283000 +#define VENUS_SCAL_REGMAP2_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x60283800 +#define VENUS_SCAL_REGMAP3_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x60284000 +#define VENUS_SCAL_REGMAP4_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x60284800 +#define VENUS_SCAL_REGMAP5_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x60285000 +#define VENUS_SCAL_REGMAP6_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x60285800 +#define VENUS_SCAL_REGMAP7_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL0 0x60286000 +#define VENUS_SCAL_REGMAP0_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x60482800 +#define VENUS_SCAL_REGMAP1_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x60483000 +#define VENUS_SCAL_REGMAP2_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x60483800 +#define VENUS_SCAL_REGMAP3_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x60484000 +#define VENUS_SCAL_REGMAP4_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x60484800 +#define VENUS_SCAL_REGMAP5_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x60485000 +#define VENUS_SCAL_REGMAP6_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x60485800 +#define VENUS_SCAL_REGMAP7_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL0 0x60486000 +#define VENUS_SCAL_REGMAP0_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A82800 +#define VENUS_SCAL_REGMAP1_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A83000 +#define VENUS_SCAL_REGMAP2_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A83800 +#define VENUS_SCAL_REGMAP3_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A84000 +#define VENUS_SCAL_REGMAP4_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A84800 +#define VENUS_SCAL_REGMAP5_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A85000 +#define VENUS_SCAL_REGMAP6_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A85800 +#define VENUS_SCAL_REGMAP7_ADC32_ANALOG_REGS_RX_SLICE_0_RX_DIGITAL1 0x60A86000 +#define VENUS_SCAL_REGMAP0_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C82800 +#define VENUS_SCAL_REGMAP1_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C83000 +#define VENUS_SCAL_REGMAP2_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C83800 +#define VENUS_SCAL_REGMAP3_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C84000 +#define VENUS_SCAL_REGMAP4_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C84800 +#define VENUS_SCAL_REGMAP5_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C85000 +#define VENUS_SCAL_REGMAP6_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C85800 +#define VENUS_SCAL_REGMAP7_ADC32_ANALOG_REGS_RX_SLICE_1_RX_DIGITAL1 0x60C86000 + +#define REG_SCAL_SCRATCH_BEGIN_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000000) +#define BF_SCAL_SCRATCH_BEGIN_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000000), 0x00002000 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0004_VENUS_SCAL__OPEN_ADDR(inst, n) ((inst) + 0x00000004 + 4 * (n)) +#define BF_BF_507BA89F_VENUS_SCAL__OPEN_INFO(inst, n) ((inst) + 0x00000004 + 4 * (n)), 0x00001108 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X001C_VENUS_SCAL__OPEN_ADDR(inst, n) ((inst) + 0x0000001C + 4 * (n)) +#define BF_BF_A4C77B32_VENUS_SCAL__OPEN_INFO(inst, n) ((inst) + 0x0000001C + 4 * (n)), 0x00001308 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0034_VENUS_SCAL__OPEN_ADDR(inst, n) ((inst) + 0x00000034 + 4 * (n)) +#define BF_BF_4C11EC69_INFO(inst, n) ((inst) + 0x00000034 + 4 * (n)), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X004C_VENUS_SCAL__OPEN_ADDR(inst, n) ((inst) + 0x0000004C + 4 * (n)) +#define BF_BF_4520F3B2_INFO(inst, n) ((inst) + 0x0000004C + 4 * (n)), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0084_VENUS_SCAL__OPEN_ADDR(inst, n) ((inst) + 0x00000084 + 4 * (n)) +#define BF_BF_28B73B48_VENUS_SCAL__OPEN_INFO(inst, n) ((inst) + 0x00000084 + 4 * (n)), 0x00001508 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0134_VENUS_SCAL__OPEN_ADDR(inst, n) ((inst) + 0x00000134 + 4 * (n)) +#define BF_BF_9165E1BF_INFO(inst, n) ((inst) + 0x00000134 + 4 * (n)), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0158_VENUS_SCAL__OPEN_ADDR(inst, n) ((inst) + 0x00000158 + 4 * (n)) +#define BF_BF_60B7FE5A_INFO(inst, n) ((inst) + 0x00000158 + 4 * (n)), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X017C_VENUS_SCAL__OPEN_ADDR(inst, n) ((inst) + 0x0000017C + 4 * (n)) +#define BF_BF_E957A710_INFO(inst, n) ((inst) + 0x0000017C + 4 * (n)), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X01A0_VENUS_SCAL__OPEN_ADDR(inst, n) ((inst) + 0x000001A0 + 4 * (n)) +#define BF_BF_E2EF3B98_INFO(inst, n) ((inst) + 0x000001A0 + 4 * (n)), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X01E4_VENUS_SCAL__OPEN_ADDR(inst, n) ((inst) + 0x000001E4 + 4 * (n)) +#define BF_BF_BA0DA821_INFO(inst, n) ((inst) + 0x000001E4 + 4 * (n)), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0204_VENUS_SCAL__OPEN_ADDR(inst, n) ((inst) + 0x00000204 + 4 * (n)) +#define BF_BF_92C0547B_VENUS_SCAL__OPEN_INFO(inst, n) ((inst) + 0x00000204 + 4 * (n)), 0x00001508 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X020C_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x0000020C) +#define BF_BF_D3211CFA_INFO(inst) ((inst) + 0x0000020C), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X022C_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x0000022C) +#define BF_BF_C96B1B9D_INFO(inst) ((inst) + 0x0000022C), 0x00004000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X024C_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x0000024C) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0400_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000400) +#define BF_BF_21E3283D_INFO(inst) ((inst) + 0x00000400), 0x00004000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0404_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000404) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0408_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000408) +#define BF_BF_4BD87248_INFO(inst) ((inst) + 0x00000408), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X040C_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x0000040C) +#ifdef USE_PRIVATE_BF +#define BF_BF_4D25EF5C_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000040C), 0x00000200 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_4D25EF5C_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000040C), 0x00000102 +#ifdef USE_PRIVATE_BF +#define BF_BF_48F55CE0_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000040C), 0x00000203 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_48F55CE0_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000040C), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_38DA1C3D_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000040C), 0x00000206 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_38DA1C3D_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000040C), 0x00000108 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0410_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000410) +#define BF_BF_96BCC18D_INFO(inst) ((inst) + 0x00000410), 0x00004000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0414_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000414) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0418_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000418) +#define BF_BF_CC931EEA_INFO(inst) ((inst) + 0x00000418), 0x00004000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X041C_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x0000041C) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0420_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000420) +#define BF_BF_66BBAEBB_INFO(inst) ((inst) + 0x00000420), 0x00004000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0424_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000424) + +#define REG_REG_0X0428_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000428) +#ifdef USE_PRIVATE_BF +#define BF_BF_BAD86450_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000428), 0x00000600 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_BAD86450_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000428), 0x00000106 +#ifdef USE_PRIVATE_BF +#define BF_BF_0D9CF522_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000428), 0x00000607 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_0D9CF522_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000428), 0x0000010D + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X042C_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x0000042C) +#define BF_BF_B62785DB_INFO(inst) ((inst) + 0x0000042C), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0430_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000430) +#define BF_BF_733BBA6A_INFO(inst) ((inst) + 0x00000430), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0434_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000434) +#define BF_BF_47486732_INFO(inst) ((inst) + 0x00000434), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0438_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000438) +#define BF_BF_454B21FC_INFO(inst) ((inst) + 0x00000438), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X043C_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x0000043C) +#define BF_BF_3BB2B179_INFO(inst) ((inst) + 0x0000043C), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0440_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000440) +#define BF_BF_0D3C03A5_INFO(inst) ((inst) + 0x00000440), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0444_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000444) +#define BF_BF_53142F7C_INFO(inst) ((inst) + 0x00000444), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0448_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000448) +#define BF_BF_FF13351A_INFO(inst) ((inst) + 0x00000448), 0x00004000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X044C_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x0000044C) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0450_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000450) +#define BF_BF_246FD1C9_INFO(inst) ((inst) + 0x00000450), 0x00004000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0454_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000454) + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0458_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000458) +#define BF_BF_AC57581C_INFO(inst) ((inst) + 0x00000458), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X045C_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x0000045C) +#define BF_BF_F6B2636C_INFO(inst) ((inst) + 0x0000045C), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0460_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000460) +#define BF_BF_5D22C096_INFO(inst) ((inst) + 0x00000460), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0464_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000464) +#define BF_BF_83558BC6_INFO(inst) ((inst) + 0x00000464), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0468_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000468) +#define BF_BF_D4C5F783_INFO(inst) ((inst) + 0x00000468), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X046C_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x0000046C) +#ifdef USE_PRIVATE_BF +#define BF_BF_04FC627D_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000046C), 0x00000800 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_04FC627D_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000046C), 0x00000108 + +#define REG_REG_0X0470_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000470) +#ifdef USE_PRIVATE_BF +#define BF_BF_89FA30CF_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000470), 0x00000400 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_89FA30CF_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000470), 0x00000104 +#ifdef USE_PRIVATE_BF +#define BF_BF_83063494_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000470), 0x00000405 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_83063494_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000470), 0x00000109 +#ifdef USE_PRIVATE_BF +#define BF_BF_6073B2AA_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000470), 0x0000040A +#endif /* USE_PRIVATE_BF */ +#define BF_BF_6073B2AA_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000470), 0x0000010E +#ifdef USE_PRIVATE_BF +#define BF_BF_56C106E1_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000470), 0x0000040F +#endif /* USE_PRIVATE_BF */ +#define BF_BF_56C106E1_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000470), 0x00000113 +#ifdef USE_PRIVATE_BF +#define BF_BF_34407588_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000470), 0x00000414 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_34407588_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000470), 0x00000118 + +#define REG_REG_0X0474_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000474) +#ifdef USE_PRIVATE_BF +#define BF_BF_DAD827A3_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000474), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_DAD827A3_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000474), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_7BA7C73B_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000474), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_7BA7C73B_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000474), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_DBA82E9D_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000474), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_DBA82E9D_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000474), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_3098C59C_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000474), 0x00000106 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_3098C59C_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000474), 0x00000107 + +#define REG_REG_0X0478_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000478) +#ifdef USE_PRIVATE_BF +#define BF_BF_45F7874C_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000478), 0x00000400 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_45F7874C_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000478), 0x00000104 +#ifdef USE_PRIVATE_BF +#define BF_BF_32F08E3A_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000478), 0x00000405 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_32F08E3A_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000478), 0x00000109 +#ifdef USE_PRIVATE_BF +#define BF_BF_D797E7BF_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000478), 0x0000040A +#endif /* USE_PRIVATE_BF */ +#define BF_BF_D797E7BF_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000478), 0x0000010E + +#define REG_REG_0X047C_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x0000047C) +#ifdef USE_PRIVATE_BF +#define BF_BF_A432F804_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000047C), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_A432F804_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000047C), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_59DA3AA0_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000047C), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_59DA3AA0_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000047C), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_48B52FAE_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000047C), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_48B52FAE_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000047C), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_CEDBB6EE_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000047C), 0x00000106 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_CEDBB6EE_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000047C), 0x00000107 + +#define REG_REG_0X0480_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000480) +#ifdef USE_PRIVATE_BF +#define BF_BF_821BF1CA_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000480), 0x00000300 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_821BF1CA_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000480), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_27DD70A9_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000480), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_27DD70A9_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000480), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_AD4714AD_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000480), 0x00000206 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_AD4714AD_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000480), 0x00000108 + +#define REG_REG_0X0484_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000484) +#ifdef USE_PRIVATE_BF +#define BF_BF_5CA2D2B4_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000484), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_5CA2D2B4_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000484), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_CC0429E4_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000484), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_CC0429E4_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000484), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_67599BD7_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000484), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_67599BD7_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000484), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_B9D7C00F_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000484), 0x00000106 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_B9D7C00F_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000484), 0x00000107 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0488_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000488) +#define BF_BF_EC9E82E8_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000488), 0x00000800 +#define BF_BF_0818209E_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000488), 0x00000808 +#define BF_BF_B416D230_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000488), 0x00000810 +#define BF_BF_EACE3FE4_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000488), 0x00000818 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X048C_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x0000048C) +#ifdef USE_PRIVATE_BF +#define BF_BF_ED7193DA_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_ED7193DA_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_9F9E1975_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_9F9E1975_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_25552B6D_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_25552B6D_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_5E7E18C6_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000106 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_5E7E18C6_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000107 +#ifdef USE_PRIVATE_BF +#define BF_BF_F4D789F1_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000108 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_F4D789F1_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000109 +#ifdef USE_PRIVATE_BF +#define BF_BF_E1F9065C_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000048C), 0x0000010A +#endif /* USE_PRIVATE_BF */ +#define BF_BF_E1F9065C_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000048C), 0x0000010B +#ifdef USE_PRIVATE_BF +#define BF_BF_5B7943BD_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000048C), 0x0000010C +#endif /* USE_PRIVATE_BF */ +#define BF_BF_5B7943BD_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000048C), 0x0000010D +#ifdef USE_PRIVATE_BF +#define BF_BF_684D9C7E_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000048C), 0x0000010E +#endif /* USE_PRIVATE_BF */ +#define BF_BF_684D9C7E_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000048C), 0x0000010F +#ifdef USE_PRIVATE_BF +#define BF_BF_B483B9CE_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000112 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_B483B9CE_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000113 +#ifdef USE_PRIVATE_BF +#define BF_BF_C967ACFB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000114 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_C967ACFB_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000115 +#ifdef USE_PRIVATE_BF +#define BF_BF_9580F3CE_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000116 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_9580F3CE_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000117 +#ifdef USE_PRIVATE_BF +#define BF_BF_5B4B40B3_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000118 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_5B4B40B3_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000048C), 0x00000119 +#ifdef USE_PRIVATE_BF +#define BF_BF_6A3A083B_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000048C), 0x0000011A +#endif /* USE_PRIVATE_BF */ +#define BF_BF_6A3A083B_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000048C), 0x0000011B +#ifdef USE_PRIVATE_BF +#define BF_BF_D5CAD3F6_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000048C), 0x0000021C +#endif /* USE_PRIVATE_BF */ +#define BF_BF_D5CAD3F6_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000048C), 0x0000011E + +#define REG_REG_0X0490_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000490) +#ifdef USE_PRIVATE_BF +#define BF_BF_37ABA1A8_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000490), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_37ABA1A8_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000490), 0x00000101 + +#define REG_REG_0X0494_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000494) +#ifdef USE_PRIVATE_BF +#define BF_BF_4A6EADD0_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000494), 0x00000500 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_4A6EADD0_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000494), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_13A16383_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000494), 0x00000306 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_13A16383_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000494), 0x00000109 +#ifdef USE_PRIVATE_BF +#define BF_BF_C3BD2E36_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000494), 0x0000040A +#endif /* USE_PRIVATE_BF */ +#define BF_BF_C3BD2E36_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000494), 0x0000010E +#ifdef USE_PRIVATE_BF +#define BF_BF_49DD6537_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000494), 0x0000030F +#endif /* USE_PRIVATE_BF */ +#define BF_BF_49DD6537_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000494), 0x00000112 +#ifdef USE_PRIVATE_BF +#define BF_BF_FC7B85A0_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000494), 0x00000113 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_FC7B85A0_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000494), 0x00000114 +#ifdef USE_PRIVATE_BF +#define BF_BF_A946AEFC_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000494), 0x00000115 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_A946AEFC_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000494), 0x00000116 + +#define REG_REG_0X0498_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000498) +#ifdef USE_PRIVATE_BF +#define BF_BF_A0BA0FAB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000498), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_A0BA0FAB_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000498), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_1A41BF89_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000498), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_1A41BF89_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000498), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_73E79897_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000498), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_73E79897_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000498), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_54B73BD8_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000498), 0x00000106 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_54B73BD8_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000498), 0x00000107 +#ifdef USE_PRIVATE_BF +#define BF_BF_B0654939_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000498), 0x00000108 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_B0654939_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000498), 0x00000109 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X049C_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x0000049C) +#define BF_BF_0B8DA998_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000049C), 0x00000500 +#define BF_BF_40FAAB06_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000049C), 0x00000107 +#define BF_BF_9D6BE1C4_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000049C), 0x00000408 +#define BF_BF_72EE83E6_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000049C), 0x0000020D +#define BF_BF_6751217C_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000049C), 0x00000410 +#define BF_BF_0ABC4A65_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000049C), 0x00000418 +#define BF_BF_7465262C_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000049C), 0x0000031D +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X04A0_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000004A0) +#ifdef USE_PRIVATE_BF +#define BF_BF_D9F03C0D_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004A0), 0x00001000 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_D9F03C0D_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004A0), 0x00000110 + +#define REG_REG_0X04A4_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000004A4) +#ifdef USE_PRIVATE_BF +#define BF_BF_C5EB3B6B_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004A4), 0x00000C00 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_C5EB3B6B_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004A4), 0x0000010C +#ifdef USE_PRIVATE_BF +#define BF_BF_E123593E_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004A4), 0x0000080D +#endif /* USE_PRIVATE_BF */ +#define BF_BF_E123593E_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004A4), 0x00000115 +#ifdef USE_PRIVATE_BF +#define BF_BF_393452C1_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004A4), 0x00000416 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_393452C1_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004A4), 0x0000011A + +#define REG_REG_0X04A8_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000004A8) +#ifdef USE_PRIVATE_BF +#define BF_BF_762E9A1B_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004A8), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_762E9A1B_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004A8), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_EFCC4262_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004A8), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_EFCC4262_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004A8), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_5E9A28EB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004A8), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_5E9A28EB_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004A8), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_1BCD2E5C_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004A8), 0x00000106 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_1BCD2E5C_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004A8), 0x00000107 + +#define REG_REG_0X04AC_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000004AC) +#ifdef USE_PRIVATE_BF +#define BF_BF_2D4E0C9F_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004AC), 0x00000300 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_2D4E0C9F_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004AC), 0x00000103 + +#define REG_REG_0X04B0_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000004B0) +#ifdef USE_PRIVATE_BF +#define BF_BF_C0973401_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004B0), 0x00000300 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_C0973401_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004B0), 0x00000103 + +#define REG_REG_0X04B4_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000004B4) +#ifdef USE_PRIVATE_BF +#define BF_BF_D04D53CC_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004B4), 0x00000300 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_D04D53CC_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004B4), 0x00000103 + +#define REG_REG_0X04B8_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000004B8) +#ifdef USE_PRIVATE_BF +#define BF_BF_1CC10689_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004B8), 0x00000300 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_1CC10689_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004B8), 0x00000103 + +#define REG_REG_0X04BC_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000004BC) +#ifdef USE_PRIVATE_BF +#define BF_BF_28BB343D_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004BC), 0x00000300 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_28BB343D_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004BC), 0x00000103 + +#define REG_REG_0X04C0_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000004C0) +#ifdef USE_PRIVATE_BF +#define BF_BF_56104F9F_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004C0), 0x00000500 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_56104F9F_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004C0), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_15ACCE3B_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004C0), 0x00000506 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_15ACCE3B_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004C0), 0x0000010B +#ifdef USE_PRIVATE_BF +#define BF_BF_7A15F80D_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004C0), 0x0000050C +#endif /* USE_PRIVATE_BF */ +#define BF_BF_7A15F80D_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004C0), 0x00000111 +#ifdef USE_PRIVATE_BF +#define BF_BF_99D1F504_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004C0), 0x00000512 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_99D1F504_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004C0), 0x00000117 +#ifdef USE_PRIVATE_BF +#define BF_BF_71632961_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004C0), 0x00000518 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_71632961_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004C0), 0x0000011D + +#define REG_REG_0X04C4_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000004C4) +#ifdef USE_PRIVATE_BF +#define BF_BF_C515FC1B_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004C4), 0x0000010A +#endif /* USE_PRIVATE_BF */ +#define BF_BF_C515FC1B_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004C4), 0x0000010B +#ifdef USE_PRIVATE_BF +#define BF_BF_BF9D4E01_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004C4), 0x0000010C +#endif /* USE_PRIVATE_BF */ +#define BF_BF_BF9D4E01_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004C4), 0x0000010D +#ifdef USE_PRIVATE_BF +#define BF_BF_17A918A1_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004C4), 0x0000010E +#endif /* USE_PRIVATE_BF */ +#define BF_BF_17A918A1_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004C4), 0x0000010F +#ifdef USE_PRIVATE_BF +#define BF_BF_F585D73C_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004C4), 0x00000110 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_F585D73C_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004C4), 0x00000111 +#ifdef USE_PRIVATE_BF +#define BF_BF_60D96D7E_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004C4), 0x00000112 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_60D96D7E_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004C4), 0x00000113 + +#define REG_REG_0X04C8_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000004C8) +#ifdef USE_PRIVATE_BF +#define BF_BF_6E6DD6A6_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004C8), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_6E6DD6A6_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004C8), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_75358B68_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004C8), 0x00000104 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_75358B68_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004C8), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_7260E949_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004C8), 0x00000108 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_7260E949_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004C8), 0x00000109 +#ifdef USE_PRIVATE_BF +#define BF_BF_7DDCFB88_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004C8), 0x0000050A +#endif /* USE_PRIVATE_BF */ +#define BF_BF_7DDCFB88_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004C8), 0x0000010F +#ifdef USE_PRIVATE_BF +#define BF_BF_815F65AE_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004C8), 0x00000110 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_815F65AE_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004C8), 0x00000111 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X04CC_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000004CC) +#define BF_BF_92EE659F_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000100 +#define BF_BF_9CE5B3DD_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000101 +#define BF_BF_997ED7A2_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000102 +#define BF_BF_8773591D_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000103 +#define BF_BF_2B51C820_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000104 +#define BF_BF_33785069_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000105 +#define BF_BF_43B42B61_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000106 +#define BF_BF_990DB6C3_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000107 +#define BF_BF_8AE80AAE_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000108 +#define BF_BF_ECF1FE4C_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000109 +#define BF_BF_3B9FA7CD_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004CC), 0x0000010A +#define BF_BF_F3ABEC40_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004CC), 0x0000010B +#define BF_BF_4459CB53_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004CC), 0x0000010C +#define BF_BF_9626B1AE_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004CC), 0x0000010D +#define BF_BF_F071661E_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004CC), 0x0000010E +#define BF_BF_C9385D2A_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004CC), 0x0000010F +#define BF_BF_905990E8_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000110 +#define BF_BF_ECC16671_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000111 +#define BF_BF_2D25984B_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000112 +#define BF_BF_90FE67B3_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000113 +#define BF_BF_46178217_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000114 +#define BF_BF_DA03E966_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000115 +#define BF_BF_9B05C98F_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000116 +#define BF_BF_D274852B_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000117 +#define BF_BF_54915CD0_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000118 +#define BF_BF_FE0CAE4C_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004CC), 0x00000119 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X04D4_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000004D4) +#ifdef USE_PRIVATE_BF +#define BF_BF_C53B812B_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004D4), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_C53B812B_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004D4), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_EB0FA4A2_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004D4), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_EB0FA4A2_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004D4), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_97354A59_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004D4), 0x00000404 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_97354A59_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004D4), 0x00000108 +#ifdef USE_PRIVATE_BF +#define BF_BF_CB643805_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004D4), 0x00000409 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_CB643805_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004D4), 0x0000010D +#ifdef USE_PRIVATE_BF +#define BF_BF_D2561460_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004D4), 0x0000010E +#endif /* USE_PRIVATE_BF */ +#define BF_BF_D2561460_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004D4), 0x0000010F + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X04DC_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000004DC) +#define BF_BF_0F880F25_INFO(inst) ((inst) + 0x000004DC), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X04E0_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000004E0) +#ifdef USE_PRIVATE_BF +#define BF_BF_3F7D6943_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004E0), 0x00000200 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_3F7D6943_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004E0), 0x00000102 +#ifdef USE_PRIVATE_BF +#define BF_BF_1A6F84CA_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004E0), 0x00000203 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_1A6F84CA_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004E0), 0x00000105 +#ifdef USE_PRIVATE_BF +#define BF_BF_ADA50B94_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004E0), 0x00000206 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_ADA50B94_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004E0), 0x00000108 +#ifdef USE_PRIVATE_BF +#define BF_BF_77976C72_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004E0), 0x00000209 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_77976C72_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004E0), 0x0000010B +#ifdef USE_PRIVATE_BF +#define BF_BF_07F52F79_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004E0), 0x0000020C +#endif /* USE_PRIVATE_BF */ +#define BF_BF_07F52F79_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004E0), 0x0000010E + +#define REG_REG_0X04E4_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000004E4) +#ifdef USE_PRIVATE_BF +#define BF_BF_0DD44427_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004E4), 0x00000400 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_0DD44427_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004E4), 0x00000104 +#ifdef USE_PRIVATE_BF +#define BF_BF_BF879925_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004E4), 0x00000405 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_BF879925_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004E4), 0x00000109 +#ifdef USE_PRIVATE_BF +#define BF_BF_1476FFA8_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004E4), 0x0000040A +#endif /* USE_PRIVATE_BF */ +#define BF_BF_1476FFA8_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004E4), 0x0000010E +#ifdef USE_PRIVATE_BF +#define BF_BF_001C94C5_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004E4), 0x0000040F +#endif /* USE_PRIVATE_BF */ +#define BF_BF_001C94C5_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004E4), 0x00000113 +#ifdef USE_PRIVATE_BF +#define BF_BF_B3E34C3B_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004E4), 0x00000414 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_B3E34C3B_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004E4), 0x00000118 +#ifdef USE_PRIVATE_BF +#define BF_BF_92ECC13C_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004E4), 0x00000119 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_92ECC13C_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004E4), 0x0000011A + +#define REG_REG_0X04E8_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000004E8) +#ifdef USE_PRIVATE_BF +#define BF_BF_B5424714_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004E8), 0x00000300 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_B5424714_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004E8), 0x00000103 + +#define REG_REG_0X04EC_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000004EC) +#ifdef USE_PRIVATE_BF +#define BF_BF_3EBE01A9_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004EC), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_3EBE01A9_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004EC), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_B2862FC4_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004EC), 0x00000D04 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_B2862FC4_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004EC), 0x00000111 +#ifdef USE_PRIVATE_BF +#define BF_BF_3DB03CBF_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004EC), 0x00000D12 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_3DB03CBF_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004EC), 0x0000011F + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X04F0_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000004F0) +#define BF_BF_00A846A3_INFO(inst) ((inst) + 0x000004F0), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X04F4_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000004F4) +#define BF_BF_4188D5E1_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004F4), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X04F8_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000004F8) +#define BF_BF_2FC68603_INFO(inst) ((inst) + 0x000004F8), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X04FC_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000004FC) +#define BF_BF_2F9A8F1A_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000004FC), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0500_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000500) +#define BF_BF_6E25F661_INFO(inst) ((inst) + 0x00000500), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0504_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000504) +#define BF_BF_4FA1F584_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000504), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0508_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000508) +#define BF_BF_82793082_INFO(inst) ((inst) + 0x00000508), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X050C_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x0000050C) +#define BF_BF_0B81DFC5_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000050C), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0510_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000510) +#define BF_BF_784B0F75_INFO(inst) ((inst) + 0x00000510), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0514_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000514) +#define BF_BF_A4A947A9_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000514), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0518_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000518) +#define BF_BF_58ECDFC2_INFO(inst) ((inst) + 0x00000518), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X051C_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x0000051C) +#define BF_BF_D1D80148_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000051C), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0520_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000520) +#define BF_BF_D1607095_INFO(inst) ((inst) + 0x00000520), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0524_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000524) +#define BF_BF_708AD7DF_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000524), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0528_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000528) +#define BF_BF_DFE4D7DD_INFO(inst) ((inst) + 0x00000528), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X052C_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x0000052C) +#define BF_BF_75851DAC_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000052C), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0530_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000530) +#define BF_BF_AA64DED9_INFO(inst) ((inst) + 0x00000530), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0534_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000534) +#define BF_BF_C3ED8B31_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000534), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0538_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000538) +#define BF_BF_B4B5A6C1_INFO(inst) ((inst) + 0x00000538), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X053C_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x0000053C) +#define BF_BF_7855ACBB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000053C), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0540_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000540) +#define BF_BF_29A47F0D_INFO(inst) ((inst) + 0x00000540), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0544_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000544) +#define BF_BF_4B3AFE05_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000544), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0548_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000548) +#define BF_BF_C47668E5_INFO(inst) ((inst) + 0x00000548), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X054C_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x0000054C) +#define BF_BF_CF9F3639_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000054C), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0550_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000550) +#define BF_BF_82E004D1_INFO(inst) ((inst) + 0x00000550), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0554_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000554) +#define BF_BF_D392D19B_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000554), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0558_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000558) +#define BF_BF_3AD01442_INFO(inst) ((inst) + 0x00000558), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X055C_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x0000055C) +#define BF_BF_AB82BE1F_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000055C), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0560_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000560) +#define BF_BF_1AFAA34A_INFO(inst) ((inst) + 0x00000560), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0564_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000564) +#define BF_BF_4EE09902_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000564), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0568_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000568) +#define BF_BF_5D9EC428_INFO(inst) ((inst) + 0x00000568), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X056C_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x0000056C) +#define BF_BF_ACDFF011_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000056C), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0570_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000570) +#define BF_BF_37EBFAB1_INFO(inst) ((inst) + 0x00000570), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0574_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000574) +#define BF_BF_1E874AC1_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000574), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0578_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000578) +#define BF_BF_AB02A333_INFO(inst) ((inst) + 0x00000578), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X057C_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x0000057C) +#define BF_BF_A5CB372A_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000057C), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0580_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000580) +#define BF_BF_A0DDEC2F_INFO(inst) ((inst) + 0x00000580), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0584_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000584) +#define BF_BF_3EE65425_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000584), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0588_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000588) +#define BF_BF_21335A8D_INFO(inst) ((inst) + 0x00000588), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X058C_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x0000058C) +#define BF_BF_6434B1F4_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000058C), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0590_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000590) +#define BF_BF_4D12CF33_INFO(inst) ((inst) + 0x00000590), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0594_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000594) +#define BF_BF_962412FE_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000594), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X0598_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000598) +#define BF_BF_5BB1C70F_INFO(inst) ((inst) + 0x00000598), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X059C_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x0000059C) +#define BF_BF_23FA173C_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000059C), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X05A0_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000005A0) +#define BF_BF_9512FD04_INFO(inst) ((inst) + 0x000005A0), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X05A4_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000005A4) +#define BF_BF_2CF7CF41_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000005A4), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X05A8_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000005A8) +#define BF_BF_4963956F_INFO(inst) ((inst) + 0x000005A8), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X05AC_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000005AC) +#define BF_BF_249EE9F7_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000005AC), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X05B0_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000005B0) +#define BF_BF_AD599480_INFO(inst) ((inst) + 0x000005B0), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X05B4_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000005B4) +#define BF_BF_503461ED_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000005B4), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X05B8_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000005B8) +#define BF_BF_D89B2244_INFO(inst) ((inst) + 0x000005B8), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X05BC_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000005BC) +#define BF_BF_29476181_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000005BC), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X05C0_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000005C0) +#define BF_BF_744E1013_INFO(inst) ((inst) + 0x000005C0), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X05C4_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000005C4) +#define BF_BF_B9E86EFE_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000005C4), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X05C8_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000005C8) +#define BF_BF_8FAABBBA_INFO(inst) ((inst) + 0x000005C8), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X05CC_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000005CC) +#define BF_BF_3925C0DE_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000005CC), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X05D0_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000005D0) +#define BF_BF_15410123_INFO(inst) ((inst) + 0x000005D0), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X05D4_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000005D4) +#define BF_BF_94B7FB06_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000005D4), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X05D8_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000005D8) +#define BF_BF_DEAED8DB_INFO(inst) ((inst) + 0x000005D8), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X05DC_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000005DC) +#define BF_BF_BC512F04_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000005DC), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X05E0_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000005E0) +#define BF_BF_ADC1F655_INFO(inst) ((inst) + 0x000005E0), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X05E4_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000005E4) +#define BF_BF_D0EFDFC6_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000005E4), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X05E8_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000005E8) +#define BF_BF_D14D7EB7_INFO(inst) ((inst) + 0x000005E8), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X05EC_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000005EC) +#define BF_BF_42723B74_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000005EC), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X05F0_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000005F0) +#define BF_BF_BAC0A92F_INFO(inst) ((inst) + 0x000005F0), 0x00002000 +#endif /* USE_PRIVATE_BF */ + +#define REG_REG_0X0600_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000600) +#ifdef USE_PRIVATE_BF +#define BF_BF_466C700F_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000600), 0x00000300 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_466C700F_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000600), 0x00000103 + +#define REG_REG_0X0604_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000604) +#ifdef USE_PRIVATE_BF +#define BF_BF_ED93AE22_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000604), 0x00000100 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_ED93AE22_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000604), 0x00000101 +#ifdef USE_PRIVATE_BF +#define BF_BF_242F3948_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000604), 0x00000102 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_242F3948_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000604), 0x00000103 +#ifdef USE_PRIVATE_BF +#define BF_BF_151077EC_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000604), 0x00000504 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_151077EC_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000604), 0x00000109 + +#define REG_REG_0X0608_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x00000608) +#ifdef USE_PRIVATE_BF +#define BF_BF_45ACACF6_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000608), 0x00000300 +#endif /* USE_PRIVATE_BF */ +#define BF_BF_45ACACF6_WEB_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x00000608), 0x00000103 + +#ifdef USE_PRIVATE_BF +#define REG_REG_0X060C_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x0000060C) +#define BF_BF_A226534A_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x0000060C), 0x00000800 +#endif /* USE_PRIVATE_BF */ + +#define REG_SCAL_SCRATCH_END_VENUS_SCAL__OPEN_ADDR(inst) ((inst) + 0x000007FC) +#define BF_SCAL_SCRATCH_END_VENUS_SCAL__OPEN_INFO(inst) ((inst) + 0x000007FC), 0x00002000 + +#endif /* __ADI_APOLLO_BF_VENUS_SCAL_OPEN_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_watchdog_timer.h b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_watchdog_timer.h new file mode 100644 index 00000000000000..7e366ef238e36a --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/inc/bitfields/b0/adi_apollo_bf_watchdog_timer.h @@ -0,0 +1,30 @@ +/*! + * @brief SPI Register Definition Header File, automatically generated by + * yoda2h v1.3.8 at 2/15/2023 10:39:17 AM. + * + * @copyright copyright(c) 2023 - Analog Devices Inc.All Rights Reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * @addtogroup APOLLO_BF + * @{ + */ +#ifndef __ADI_APOLLO_BF_WATCHDOG_TIMER_H__ +#define __ADI_APOLLO_BF_WATCHDOG_TIMER_H__ + +/*============= D E F I N E S ==============*/ +#define REG_WD_LOAD_ADDR 0x41000000 +#define BF_WD_LOAD_VAL_INFO 0x41000000, 0x00002000 + +#define REG_WD_CON_ADDR 0x41000004 +#define BF_WD_ENABLE_INFO 0x41000004, 0x00000100 +#define BF_WD_RESTART_INFO 0x41000004, 0x00000101 + +#define REG_WD_VAL_ADDR 0x41000008 +#define BF_WD_VAL_INFO 0x41000008, 0x00002000 + +#endif /* __ADI_APOLLO_BF_WATCHDOG_TIMER_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/src/adi_apollo_private_blk_sel.c b/drivers/iio/trx-rf/ad9088/private/src/adi_apollo_private_blk_sel.c new file mode 100644 index 00000000000000..5ac76cf25e3463 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/src/adi_apollo_private_blk_sel.c @@ -0,0 +1,61 @@ +/*! + * \brief Private block select API implementations + * + * \copyright copyright(c) 2024 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_PRIVATE_DEVICE + * @{ + */ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_config.h" +#include "adi_apollo_hal.h" +#include "adi_apollo_bmem_types.h" +#include "adi_apollo_cddc_types.h" +#include "adi_apollo_cduc_types.h" +#include "adi_apollo_cfir_types.h" +#include "adi_apollo_cnco_types.h" +#include "adi_apollo_fnco_types.h" +#include "adi_apollo_fddc_types.h" +#include "adi_apollo_fduc_types.h" +#include "adi_apollo_fsrc_types.h" +#include "adi_apollo_invsinc_types.h" +#include "adi_apollo_pfilt_types.h" +#include "adi_apollo_sniffer_types.h" +#include "adi_apollo_smon_types.h" +#include "adi_apollo_txmux_types.h" +#include "adi_apollo_private_device.h" + +int32_t adi_apollo_private_blk_sel_mask_set(adi_apollo_device_t *device) +{ + ADI_APOLLO_NULL_POINTER_RETURN(device); + + /* Set the valid blk select masks based on 4T4R/8T8R device type. */ + device->dev_info.blk_sel_mask.adc = 0xff; + device->dev_info.blk_sel_mask.bmem = (device->dev_info.is_8t8r ? ADI_APOLLO_BMEM_ALL : ADI_APOLLO_BMEM_ALL_4T4R); + device->dev_info.blk_sel_mask.cddc = (device->dev_info.is_8t8r ? ADI_APOLLO_CDDC_ALL : ADI_APOLLO_CDDC_ALL_4T4R); + device->dev_info.blk_sel_mask.cduc = (device->dev_info.is_8t8r ? ADI_APOLLO_CDUC_ALL : ADI_APOLLO_CDUC_ALL_4T4R); + device->dev_info.blk_sel_mask.cfir = (device->dev_info.is_8t8r ? ADI_APOLLO_CFIR_ALL : ADI_APOLLO_CFIR_ALL_4T4R); + device->dev_info.blk_sel_mask.cnco = (device->dev_info.is_8t8r ? ADI_APOLLO_CNCO_ALL : ADI_APOLLO_CNCO_ALL_4T4R); + device->dev_info.blk_sel_mask.dac = 0xff; + device->dev_info.blk_sel_mask.fddc = (device->dev_info.is_8t8r ? ADI_APOLLO_FDDC_ALL : ADI_APOLLO_FDDC_ALL_4T4R); + device->dev_info.blk_sel_mask.fduc = (device->dev_info.is_8t8r ? ADI_APOLLO_FDUC_ALL : ADI_APOLLO_FDUC_ALL_4T4R); + device->dev_info.blk_sel_mask.fnco = (device->dev_info.is_8t8r ? ADI_APOLLO_FNCO_ALL : ADI_APOLLO_FNCO_ALL_4T4R); + device->dev_info.blk_sel_mask.fsrc = (device->dev_info.is_8t8r ? ADI_APOLLO_FSRC_ALL : ADI_APOLLO_FSRC_ALL_4T4R); + device->dev_info.blk_sel_mask.invsinc = (device->dev_info.is_8t8r ? ADI_APOLLO_INVSINC_ALL : ADI_APOLLO_INVSINC_ALL_4T4R); + device->dev_info.blk_sel_mask.pfilt = (device->dev_info.is_8t8r ? ADI_APOLLO_PFILT_ALL : ADI_APOLLO_PFILT_ALL_4T4R); + device->dev_info.blk_sel_mask.rxen = 0xff; + device->dev_info.blk_sel_mask.smon = (device->dev_info.is_8t8r ? ADI_APOLLO_SMON_ALL : ADI_APOLLO_SMON_ALL_4T4R); + device->dev_info.blk_sel_mask.sniffer = ADI_APOLLO_SNIFFER_ALL; + device->dev_info.blk_sel_mask.txen = 0xff; + device->dev_info.blk_sel_mask.txmux = (device->dev_info.is_8t8r ? ADI_APOLLO_TX_SUMMER_ALL : ADI_APOLLO_TX_SUMMER_ALL_4T4R); + + return API_CMS_ERROR_OK; +} + +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/src/adi_apollo_private_bmem.c b/drivers/iio/trx-rf/ad9088/private/src/adi_apollo_private_bmem.c new file mode 100644 index 00000000000000..1cfede7a80fe6b --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/src/adi_apollo_private_bmem.c @@ -0,0 +1,705 @@ +/*! + * \brief Private BMEM API implementations + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_BMEM + * @{ + */ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_private_bmem.h" +#include "adi_apollo_private_blk_sel_types.h" +#include "adi_apollo_bf_rx_bmem.h" +#include "adi_apollo_config.h" +#include "adi_apollo_hal.h" + +#define TIMEOUT_US 100000 +#define POLL_DELAY_US 10 + +/*==================== L O C A L F U N C T I O N S ====================*/ +typedef uint32_t(*calc_bmem_base_f)(int32_t bmem_index); + +static uint32_t calc_bmem_hsdin_base(int32_t bmem_index); +static uint32_t calc_bmem_fddc_base(int32_t bmem_index); +static uint32_t calc_bmem_cddc_base(int32_t bmem_index); +static uint32_t calc_hsdin_bmem_sram_base(int32_t bmem_index); +static uint32_t calc_fine_bmem_sram_base(int32_t bmem_index); +static uint32_t calc_coarse_bmem_sram_base(int32_t bmem_index); +static uint32_t calc_hsdin_bmem_sram_base(int32_t bmem_index); + +static calc_bmem_base_f calc_bmem_base_func(adi_apollo_bmem_loc_e bmem_loc); +static calc_bmem_base_f calc_sram_base_func(adi_apollo_bmem_loc_e bmem_loc); + +/*==================== P U B L I C A P I C O D E ====================*/ + +int32_t adi_apollo_private_bmem_delay_sample_set(adi_apollo_device_t *device, adi_apollo_bmem_loc_e bmem_loc, adi_apollo_blk_sel_t bmems, uint16_t sample_delay) +{ + int32_t err = API_CMS_ERROR_OK; + int32_t i; + uint32_t regmap_base_addr; + calc_bmem_base_f calc_bmem_base; + calc_bmem_base = calc_bmem_base_func(bmem_loc); + + ADI_CMS_NULL_PTR_CHECK(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_BMEM_BLK_SEL_MASK(bmems); + + for (i = 0; i < ADI_APOLLO_BMEM_NUM; i++) { + if ((bmems & (ADI_APOLLO_BMEM_A0 << i)) > 0) { + regmap_base_addr = calc_bmem_base(i); + + // Set sample delay + err = adi_apollo_hal_bf_set(device, BF_SAMPLE_DLY_INFO(regmap_base_addr), sample_delay); + ADI_CMS_ERROR_RETURN(err); + } + } + + return err; +} + +int32_t adi_apollo_private_bmem_delay_hop_set(adi_apollo_device_t *device, adi_apollo_bmem_loc_e bmem_loc, adi_apollo_blk_sel_t bmems, uint16_t sample_delay[], uint32_t sample_delay_length) +{ + int32_t err = API_CMS_ERROR_OK; + int32_t i; + uint32_t regmap_base_addr; + calc_bmem_base_f calc_bmem_base; + calc_bmem_base = calc_bmem_base_func(bmem_loc); + + ADI_CMS_NULL_PTR_CHECK(device); + ADI_APOLLO_LOG_FUNC(); + ADI_CMS_NULL_PTR_CHECK(sample_delay); + ADI_CMS_INVALID_PARAM_CHECK(sample_delay_length != ADI_APOLLO_BMEM_HOP_PROFILES); + ADI_APOLLO_BMEM_BLK_SEL_MASK(bmems); + + for (i = 0; i < ADI_APOLLO_BMEM_NUM; i++) { + if ((bmems & (ADI_APOLLO_BMEM_A0 << i)) > 0) { + regmap_base_addr = calc_bmem_base(i); + + // Set hop delays + err = adi_apollo_hal_bf_set(device, BF_HOP_DELAY0_INFO(regmap_base_addr), sample_delay[0]); + ADI_CMS_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_HOP_DELAY1_INFO(regmap_base_addr), sample_delay[1]); + ADI_CMS_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_HOP_DELAY2_INFO(regmap_base_addr), sample_delay[2]); + ADI_CMS_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_HOP_DELAY3_INFO(regmap_base_addr), sample_delay[3]); + ADI_CMS_ERROR_RETURN(err); + } + } + + return err; +} + +int32_t adi_apollo_private_bmem_delay_sample_config(adi_apollo_device_t *device, adi_apollo_bmem_loc_e bmem_loc, adi_apollo_blk_sel_t bmems, adi_apollo_bmem_delay_sample_t *config) +{ + int32_t err; + int32_t i; + uint32_t regmap_base_addr; + calc_bmem_base_f calc_bmem_base; + calc_bmem_base = calc_bmem_base_func(bmem_loc); + + ADI_CMS_NULL_PTR_CHECK(device); + ADI_APOLLO_LOG_FUNC(); + ADI_CMS_NULL_PTR_CHECK(config); + ADI_APOLLO_BMEM_BLK_SEL_MASK(bmems); + + for (i = 0; i < ADI_APOLLO_BMEM_NUM; i++) { + if ((bmems & (ADI_APOLLO_BMEM_A0 << i)) > 0) { + regmap_base_addr = calc_bmem_base(i); + + // Enable BMEM + err = adi_apollo_hal_bf_set(device, BF_BMEM_EN_INFO(regmap_base_addr), 1); + ADI_CMS_ERROR_RETURN(err); + + // Set delay mode + err = adi_apollo_hal_bf_set(device, BF_BMEM_MODE_INFO(regmap_base_addr), 1); + ADI_CMS_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_SAMPLE_SIZE_INFO(regmap_base_addr), config->sample_size); + ADI_CMS_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_RAMCLK_PH_DIS_INFO(regmap_base_addr), config->ramclk_ph_dis); + ADI_CMS_ERROR_RETURN(err); + + // Disable triggers + err = adi_apollo_hal_bf_set(device, BF_TRIG_MODE_INFO(regmap_base_addr), 0); + ADI_CMS_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_HOP_DLY_SEL_MODE_INFO(regmap_base_addr), 0); + ADI_CMS_ERROR_RETURN(err); + + + // Set parity check + err = adi_apollo_hal_bf_set(device, BF_PARITY_CHECK_EN_INFO(regmap_base_addr), config->parity_check_en); + ADI_CMS_ERROR_RETURN(err); + } + } + + err = adi_apollo_private_bmem_delay_sample_set(device, bmem_loc, bmems, config->sample_delay); + ADI_CMS_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_private_bmem_delay_hop_config(adi_apollo_device_t *device, adi_apollo_bmem_loc_e bmem_loc, adi_apollo_blk_sel_t bmems, adi_apollo_bmem_delay_hop_t *config) +{ + int32_t err; + int32_t i; + uint32_t regmap_base_addr; + calc_bmem_base_f calc_bmem_base; + calc_bmem_base = calc_bmem_base_func(bmem_loc); + + ADI_CMS_NULL_PTR_CHECK(device); + ADI_APOLLO_LOG_FUNC(); + ADI_CMS_NULL_PTR_CHECK(config); + ADI_APOLLO_BMEM_BLK_SEL_MASK(bmems); + + for (i = 0; i < ADI_APOLLO_BMEM_NUM; i++) { + if ((bmems & (ADI_APOLLO_BMEM_A0 << i)) > 0) { + regmap_base_addr = calc_bmem_base(i); + + // Enable BMEM + err = adi_apollo_hal_bf_set(device, BF_BMEM_EN_INFO(regmap_base_addr), 1); + ADI_CMS_ERROR_RETURN(err); + + // Set delay mode + err = adi_apollo_hal_bf_set(device, BF_BMEM_MODE_INFO(regmap_base_addr), 1); + ADI_CMS_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_SAMPLE_SIZE_INFO(regmap_base_addr), config->sample_size); + ADI_CMS_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_RAMCLK_PH_DIS_INFO(regmap_base_addr), config->ramclk_ph_dis); + ADI_CMS_ERROR_RETURN(err); + + // Enable triggers + err = adi_apollo_hal_bf_set(device, BF_TRIG_MODE_INFO(regmap_base_addr), 1); + ADI_CMS_ERROR_RETURN(err); + + // Set hop delay select mode + err = adi_apollo_hal_bf_set(device, BF_HOP_DLY_SEL_MODE_INFO(regmap_base_addr), config->hop_delay_sel_mode); + ADI_CMS_ERROR_RETURN(err); + + // Set trigger mode self clear + err = adi_apollo_hal_bf_set(device, BF_TRIG_MODE_SCLR_EN_INFO(regmap_base_addr), config->trig_mode_sclr_en); + ADI_CMS_ERROR_RETURN(err); + + // Set parity check + err = adi_apollo_hal_bf_set(device, BF_PARITY_CHECK_EN_INFO(regmap_base_addr), config->parity_check_en); + ADI_CMS_ERROR_RETURN(err); + } + } + + err = adi_apollo_private_bmem_delay_hop_set(device, bmem_loc, bmems, config->hop_delay, ADI_APOLLO_BMEM_HOP_PROFILES); + ADI_CMS_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_private_bmem_delay_start(adi_apollo_device_t *device, adi_apollo_bmem_loc_e bmem_loc, adi_apollo_blk_sel_t bmems) +{ + int32_t err; + uint8_t i; + uint32_t regmap_base_addr = 0; + calc_bmem_base_f calc_bmem_base; + calc_bmem_base = calc_bmem_base_func(bmem_loc); + + ADI_CMS_NULL_PTR_CHECK(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_BMEM_BLK_SEL_MASK(bmems); + + for (i = 0; i < ADI_APOLLO_BMEM_NUM; i++) { + if ((bmems & (ADI_APOLLO_BMEM_A0 << i)) > 0) { + regmap_base_addr = calc_bmem_base(i); + + // Issue start signal for pushing data in loop + err = adi_apollo_hal_bf_set(device, BF_BMEM_START_INFO(regmap_base_addr), 1); + ADI_CMS_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_wait_to_clear(device, BF_BMEM_START_INFO(regmap_base_addr) , TIMEOUT_US, POLL_DELAY_US); + ADI_CMS_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_private_bmem_capture_config(adi_apollo_device_t *device, adi_apollo_bmem_loc_e bmem_loc, adi_apollo_blk_sel_t bmems, adi_apollo_bmem_capture_t *config) +{ + int32_t err; + uint8_t i; + uint32_t regmap_base_addr = 0; + calc_bmem_base_f calc_bmem_base; + calc_bmem_base = calc_bmem_base_func(bmem_loc); + + ADI_CMS_NULL_PTR_CHECK(device); + ADI_APOLLO_LOG_FUNC(); + ADI_CMS_NULL_PTR_CHECK(config); + ADI_APOLLO_BMEM_BLK_SEL_MASK(bmems); + + for (i = 0; i < ADI_APOLLO_BMEM_NUM; i++) { + if ((bmems & (ADI_APOLLO_BMEM_A0 << i)) > 0) { + regmap_base_addr = calc_bmem_base(i); + + // Enable BMEM + err = adi_apollo_hal_bf_set(device, BF_BMEM_EN_INFO(regmap_base_addr), 1); + ADI_CMS_ERROR_RETURN(err); + + // Set capture mode + err = adi_apollo_hal_bf_set(device, BF_BMEM_MODE_INFO(regmap_base_addr), 0); + ADI_CMS_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_SAMPLE_SIZE_INFO(regmap_base_addr), config->sample_size); + ADI_CMS_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_RAMCLK_PH_DIS_INFO(regmap_base_addr), config->ramclk_ph_dis); + ADI_CMS_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_ST_ADDR_CPT_INFO(regmap_base_addr), config->st_addr_cpt); + ADI_CMS_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_END_ADDR_CPT_INFO(regmap_base_addr), config->end_addr_cpt); + ADI_CMS_ERROR_RETURN(err); + + // Set mask value + err = adi_apollo_hal_bf_set(device, BF_BMEM_8T8R_CAP_MASK_INFO(regmap_base_addr), 0); + ADI_CMS_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_PARITY_CHECK_EN_INFO(regmap_base_addr), config->parity_check_en); + ADI_CMS_ERROR_RETURN(err); + + // Disable trigger mode + err = adi_apollo_hal_bf_set(device, BF_TRIG_MODE_INFO(regmap_base_addr), 0); + ADI_CMS_ERROR_RETURN(err); + + // Disable sample threshold capture mode + err = adi_apollo_hal_bf_set(device, BF_ST_CPTR_ON_SMPL_VAL_INFO(regmap_base_addr), 0); + ADI_CMS_ERROR_RETURN(err); + + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_private_bmem_capture_run(adi_apollo_device_t *device, adi_apollo_bmem_loc_e bmem_loc, adi_apollo_blk_sel_t bmems) +{ + int32_t err; + uint8_t i; + uint32_t regmap_base_addr = 0; + calc_bmem_base_f calc_bmem_base; + calc_bmem_base = calc_bmem_base_func(bmem_loc); + + ADI_CMS_NULL_PTR_CHECK(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_BMEM_BLK_SEL_MASK(bmems); + + for (i = 0; i < ADI_APOLLO_BMEM_NUM; i++) { + if ((bmems & (ADI_APOLLO_BMEM_A0 << i)) > 0) { + regmap_base_addr = calc_bmem_base(i); + + // Issue BMEM Reset before every capture + err = adi_apollo_hal_bf_set(device, BF_BMEM_RESET_INFO(regmap_base_addr), 1); + ADI_CMS_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_wait_to_clear(device, BF_BMEM_RESET_INFO(regmap_base_addr) , TIMEOUT_US, POLL_DELAY_US); + ADI_CMS_ERROR_RETURN(err); + + // Set SRAM access to converter - Fast + err = adi_apollo_hal_bf_set(device, BF_FAST_NSLOW_MODE_INFO(regmap_base_addr), 1); + ADI_CMS_ERROR_RETURN(err); + + // Wait at least 4 i_HCLK and 4 (i_refclk/i_clk_div) when fast_nslow_mode switched + err = adi_apollo_hal_delay_us(device, 10000); + ADI_CMS_ERROR_RETURN(err); + + // Issue start signal for normal capture + err = adi_apollo_hal_bf_set(device, BF_BMEM_START_INFO(regmap_base_addr), 1); + ADI_CMS_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_wait_to_clear(device, BF_BMEM_START_INFO(regmap_base_addr) , TIMEOUT_US, POLL_DELAY_US); + ADI_CMS_ERROR_RETURN(err); + + // Wait for Capture to complete and RAM to fill + err = adi_apollo_hal_bf_wait_to_set(device, BF_FULL_IRQ_INFO(regmap_base_addr) , TIMEOUT_US, POLL_DELAY_US); + ADI_CMS_ERROR_RETURN(err); + + // Set SRAM access to uP/SPI/HSCI - Slow + err = adi_apollo_hal_bf_set(device, BF_FAST_NSLOW_MODE_INFO(regmap_base_addr), 0); + ADI_CMS_ERROR_RETURN(err); + + // Delay after switching fast_nslow_mode. Before reading the memory + err = adi_apollo_hal_delay_us(device, 10000); + ADI_CMS_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_private_bmem_capture_get(adi_apollo_device_t *device, adi_apollo_bmem_loc_e bmem_loc, adi_apollo_blk_sel_t bmems, uint32_t data[], uint32_t length) +{ + int32_t err; + uint8_t i; + uint32_t regmap_base_addr = 0; + calc_bmem_base_f calc_sram_base; + + ADI_CMS_NULL_PTR_CHECK(device); + ADI_APOLLO_LOG_FUNC(); + ADI_CMS_NULL_PTR_CHECK(data); + ADI_CMS_SINGLE_SELECT_CHECK(bmems); + ADI_APOLLO_BMEM_BLK_SEL_MASK(bmems); + + calc_sram_base = calc_sram_base_func(bmem_loc); + + for (i = 0; i < ADI_APOLLO_BMEM_NUM; i++) { + // verify we're only requesting one bmem + if ((bmems & (ADI_APOLLO_BMEM_A0 << i)) > 0) { + regmap_base_addr = calc_sram_base(i); + + // Read data from SRAM + err = adi_apollo_hal_stream_reg32_get(device, regmap_base_addr, data, length, 0); + ADI_CMS_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; + } + } + + return API_CMS_ERROR_INVALID_PARAM; +} + +int32_t adi_apollo_private_bmem_awg_config(adi_apollo_device_t *device, adi_apollo_bmem_loc_e bmem_loc, adi_apollo_blk_sel_t bmems, adi_apollo_bmem_awg_t *config) +{ + int32_t err; + uint8_t i; + uint32_t regmap_base_addr = 0; + calc_bmem_base_f calc_bmem_base; + calc_bmem_base = calc_bmem_base_func(bmem_loc); + + ADI_CMS_NULL_PTR_CHECK(device); + ADI_APOLLO_LOG_FUNC(); + ADI_CMS_NULL_PTR_CHECK(config); + ADI_APOLLO_BMEM_BLK_SEL_MASK(bmems); + + for (i = 0; i < ADI_APOLLO_BMEM_NUM; i++) { + if ((bmems & (ADI_APOLLO_BMEM_A0 << i)) > 0) { + regmap_base_addr = calc_bmem_base(i); + + // Enable BMEM + err = adi_apollo_hal_bf_set(device, BF_BMEM_EN_INFO(regmap_base_addr), 1); + ADI_CMS_ERROR_RETURN(err); + + // Set AWG mode + err = adi_apollo_hal_bf_set(device, BF_BMEM_MODE_INFO(regmap_base_addr), 2); + ADI_CMS_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_SAMPLE_SIZE_INFO(regmap_base_addr), config->sample_size); + ADI_CMS_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_RAMCLK_PH_DIS_INFO(regmap_base_addr), config->ramclk_ph_dis); + ADI_CMS_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_PARITY_CHECK_EN_INFO(regmap_base_addr), config->parity_check_en); + ADI_CMS_ERROR_RETURN(err); + + // Disable trigger mode + err = adi_apollo_hal_bf_set(device, BF_TRIG_MODE_INFO(regmap_base_addr), 0); + ADI_CMS_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_private_bmem_awg_start(adi_apollo_device_t *device, adi_apollo_bmem_loc_e bmem_loc, adi_apollo_blk_sel_t bmems) +{ + int32_t err; + uint8_t i; + uint32_t regmap_base_addr = 0; + calc_bmem_base_f calc_bmem_base; + calc_bmem_base = calc_bmem_base_func(bmem_loc); + + ADI_CMS_NULL_PTR_CHECK(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_BMEM_BLK_SEL_MASK(bmems); + + for (i = 0; i < ADI_APOLLO_BMEM_NUM; i++) { + if ((bmems & (ADI_APOLLO_BMEM_A0 << i)) > 0) { + regmap_base_addr = calc_bmem_base(i); + + // Set SRAM access to converter - Fast + err = adi_apollo_hal_bf_set(device, BF_FAST_NSLOW_MODE_INFO(regmap_base_addr), 1); + ADI_CMS_ERROR_RETURN(err); + } + } + + // Wait at least 4 i_HCLK and 4 (i_refclk/i_clk_div) when fast_nslow_mode switched + err = adi_apollo_hal_delay_us(device, 10000); + ADI_CMS_ERROR_RETURN(err); + + for (i = 0; i < ADI_APOLLO_BMEM_NUM; i++) { + if ((bmems & (ADI_APOLLO_BMEM_A0 << i)) > 0) { + regmap_base_addr = calc_bmem_base(i); + + // Issue start signal for pushing data in loop + err = adi_apollo_hal_bf_set(device, BF_BMEM_START_INFO(regmap_base_addr), 1); + ADI_CMS_ERROR_RETURN(err); + } + } + + for (i = 0; i < ADI_APOLLO_BMEM_NUM; i++) { + if ((bmems & (ADI_APOLLO_BMEM_A0 << i)) > 0) { + regmap_base_addr = calc_bmem_base(i); + + err = adi_apollo_hal_bf_wait_to_clear(device, BF_BMEM_START_INFO(regmap_base_addr) , TIMEOUT_US, POLL_DELAY_US); + ADI_CMS_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_private_bmem_awg_stop(adi_apollo_device_t *device, adi_apollo_bmem_loc_e bmem_loc, adi_apollo_blk_sel_t bmems) +{ + int32_t err; + uint8_t i; + uint32_t regmap_base_addr = 0; + calc_bmem_base_f calc_bmem_base; + calc_bmem_base = calc_bmem_base_func(bmem_loc); + + ADI_CMS_NULL_PTR_CHECK(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_BMEM_BLK_SEL_MASK(bmems); + + for (i = 0; i < ADI_APOLLO_BMEM_NUM; i++) { + if ((bmems & (ADI_APOLLO_BMEM_A0 << i)) > 0) { + regmap_base_addr = calc_bmem_base(i); + + // Issue BMEM Reset for Multiple AWGs + err = adi_apollo_hal_bf_set(device, BF_BMEM_RESET_INFO(regmap_base_addr), 1); + ADI_CMS_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_wait_to_clear(device, BF_BMEM_RESET_INFO(regmap_base_addr) , TIMEOUT_US, POLL_DELAY_US); + ADI_CMS_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_private_bmem_awg_sram_set(adi_apollo_device_t *device, adi_apollo_bmem_loc_e bmem_loc, adi_apollo_blk_sel_t bmems, uint32_t data[], uint32_t length) +{ + int32_t err; + uint8_t i; + uint32_t regmap_base_addr = 0; + adi_apollo_hal_protocol_e ap; + calc_bmem_base_f calc_sram_base, calc_bmem_base; + + ADI_CMS_NULL_PTR_CHECK(device); + ADI_APOLLO_LOG_FUNC(); + ADI_CMS_NULL_PTR_CHECK(data); + ADI_APOLLO_BMEM_BLK_SEL_MASK(bmems); + + /* Only SPI transactions can be used for writing BMEM AWG */ + err = adi_apollo_hal_active_protocol_get(device, &ap); + ADI_CMS_ERROR_RETURN(err); + + if (ap != ADI_APOLLO_HAL_PROTOCOL_SPI0) { + ADI_CMS_ERROR_RETURN(API_CMS_ERROR_PROTOCOL_OP_NOT_SUPPORTED); + } + + calc_sram_base = calc_sram_base_func(bmem_loc); + calc_bmem_base = calc_bmem_base_func(bmem_loc); + + for (i = 0; i < ADI_APOLLO_BMEM_NUM; i++) { + if ((bmems & (ADI_APOLLO_BMEM_A0 << i)) > 0) { + regmap_base_addr = calc_bmem_base(i); + // Set SRAM access to uP - slow + err = adi_apollo_hal_bf_set(device, BF_FAST_NSLOW_MODE_INFO(regmap_base_addr), 0); + ADI_CMS_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_ST_ADDR_AWG_INFO(regmap_base_addr), 0); + ADI_CMS_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_END_ADDR_AWG_INFO(regmap_base_addr), length - 1); + ADI_CMS_ERROR_RETURN(err); + + } + } + + // Wait at least 4 i_HCLK and 4 (i_refclk/i_clk_div) when fast_nslow_mode switched + err = adi_apollo_hal_delay_us(device, 10000); + ADI_CMS_ERROR_RETURN(err); + + for (i = 0; i < ADI_APOLLO_BMEM_NUM; i++) { + if ((bmems & (ADI_APOLLO_BMEM_A0 << i)) > 0) { + regmap_base_addr = calc_sram_base(i); + + // Write data to sram + err = adi_apollo_hal_stream_reg32_set(device, regmap_base_addr, data, length, 0); + ADI_CMS_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_private_bmem_awg_sample_write(adi_apollo_device_t *device, adi_apollo_bmem_loc_e bmem_loc, adi_apollo_blk_sel_t bmems, int16_t data16[], uint32_t data16_len) +{ + int32_t err; + uint32_t vec32_len = data16_len/2; + uint32_t vec32[vec32_len]; + uint32_t s0, s1; + int32_t i; + + ADI_CMS_NULL_PTR_CHECK(device); + ADI_APOLLO_LOG_FUNC(); + ADI_CMS_NULL_PTR_CHECK(data16); + ADI_APOLLO_BMEM_BLK_SEL_MASK(bmems); + + /* Pack 2 16-bit samples into 32-bit word for BMEM write */ + for (i = 0; i < data16_len; i += 2) + { + s0 = ((uint32_t)data16[i + 0] <<4 ) & 0xffff; // Left justify 12-bit to data. Lower 4 bits must be 0 per design. + s1 = ((uint32_t)data16[i + 1] <<4 ) & 0xffff; + vec32[i / 2] = s0 | s1 << 16; + } + + err = adi_apollo_private_bmem_awg_sram_set(device, bmem_loc, bmems, vec32, vec32_len); + ADI_CMS_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_private_bmem_awg_sample_shared_write(adi_apollo_device_t *device, adi_apollo_bmem_loc_e bmem_loc, adi_apollo_blk_sel_t bmems, + int16_t data16_0[], int16_t data16_1[], uint32_t data16_len, + uint32_t scratch32[], uint32_t scratch32_len) +{ + int32_t err; + uint32_t vec32_len = data16_len; + uint32_t *vec32 = scratch32; + uint32_t s0, s1; + int32_t i; + + ADI_CMS_NULL_PTR_CHECK(device); + ADI_APOLLO_LOG_FUNC(); + ADI_CMS_NULL_PTR_CHECK(data16_0); + ADI_CMS_NULL_PTR_CHECK(data16_1); + ADI_CMS_NULL_PTR_CHECK(scratch32); + ADI_CMS_INVALID_PARAM_CHECK(data16_len > (ADI_APOLLO_BMEM_HSDIN_MEM_SIZE_BYTES / (2 * sizeof(uint16_t)))); + ADI_CMS_INVALID_PARAM_CHECK(scratch32_len < data16_len); + ADI_APOLLO_BMEM_BLK_SEL_MASK(bmems); + + /* Pack 2 16-bit samples into 32-bit word for BMEM write */ + for (i = 0; i < data16_len; i += 2) { + s0 = ((uint32_t)data16_0[i + 0] << 4) & 0xffff; // Left justify 12-bit to data. Lower 4 bits must be 0 per design. + s1 = ((uint32_t)data16_0[i + 1] << 4) & 0xffff; + vec32[i] = s0 | s1 << 16; + + s0 = ((uint32_t)data16_1[i + 0] << 4) & 0xffff; // Left justify 12-bit to data. Lower 4 bits must be 0 per design. + s1 = ((uint32_t)data16_1[i + 1] << 4) & 0xffff; + vec32[i + 1] = s0 | s1 << 16; + } + + err = adi_apollo_private_bmem_awg_sram_set(device, bmem_loc, bmems, vec32, vec32_len); + ADI_CMS_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +static uint32_t calc_bmem_hsdin_base(int32_t bmem_index) +{ + static uint32_t bmem_regmap[ADI_APOLLO_BMEM_NUM] = { + RX_BMEM0_REG_RX_SLICE_0_RX_DIGITAL0, RX_BMEM0_REG_RX_SLICE_1_RX_DIGITAL0, + RX_BMEM0_REG_RX_SLICE_0_RX_DIGITAL0, RX_BMEM0_REG_RX_SLICE_1_RX_DIGITAL0, + RX_BMEM0_REG_RX_SLICE_0_RX_DIGITAL1, RX_BMEM0_REG_RX_SLICE_1_RX_DIGITAL1, + RX_BMEM0_REG_RX_SLICE_0_RX_DIGITAL1, RX_BMEM0_REG_RX_SLICE_1_RX_DIGITAL1 + }; + + return bmem_regmap[bmem_index]; +} + +static uint32_t calc_bmem_fddc_base(int32_t bmem_index) +{ + static uint32_t bmem_regmap[ADI_APOLLO_BMEM_NUM] = { + RX_BMEM2_REG0_RX_SLICE_0_RX_DIGITAL0, RX_BMEM2_REG0_RX_SLICE_1_RX_DIGITAL0, + RX_BMEM2_REG0_RX_SLICE_0_RX_DIGITAL0, RX_BMEM2_REG0_RX_SLICE_1_RX_DIGITAL0, + RX_BMEM2_REG0_RX_SLICE_0_RX_DIGITAL1, RX_BMEM2_REG0_RX_SLICE_1_RX_DIGITAL1, + RX_BMEM2_REG0_RX_SLICE_0_RX_DIGITAL1, RX_BMEM2_REG0_RX_SLICE_1_RX_DIGITAL1 + }; + + return bmem_regmap[bmem_index]; +} + +static uint32_t calc_bmem_cddc_base(int32_t bmem_index) +{ + static uint32_t bmem_regmap[ADI_APOLLO_BMEM_NUM] = { + RX_BMEM1_REG0_RX_SLICE_0_RX_DIGITAL0, RX_BMEM1_REG0_RX_SLICE_1_RX_DIGITAL0, + RX_BMEM1_REG0_RX_SLICE_0_RX_DIGITAL0, RX_BMEM1_REG0_RX_SLICE_1_RX_DIGITAL0, + RX_BMEM1_REG0_RX_SLICE_0_RX_DIGITAL1, RX_BMEM1_REG0_RX_SLICE_1_RX_DIGITAL1, + RX_BMEM1_REG0_RX_SLICE_0_RX_DIGITAL1, RX_BMEM1_REG0_RX_SLICE_1_RX_DIGITAL1 + }; + + return bmem_regmap[bmem_index]; +} + +static uint32_t calc_hsdin_bmem_sram_base(int32_t bmem_index) +{ + static uint32_t bmem_regmap[ADI_APOLLO_BMEM_NUM] = { + 0x60240000, 0x60440000, + 0x60240000, 0x60440000, + 0x60A40000, 0x60C40000, + 0x60A40000, 0x60C40000 + }; + + return bmem_regmap[bmem_index]; +} + +static uint32_t calc_fine_bmem_sram_base(int32_t bmem_index) +{ + static uint32_t bmem_regmap[ADI_APOLLO_BMEM_NUM] = { + 0x603C0000, 0x605C0000, + 0x603C0000, 0x605C0000, + 0x60BC0000, 0x60DC0000, + 0x60BC0000, 0x60DC0000 + }; + + return bmem_regmap[bmem_index]; +} + +static uint32_t calc_coarse_bmem_sram_base(int32_t bmem_index) +{ + static uint32_t bmem_regmap[ADI_APOLLO_BMEM_NUM] = { + 0x60380000, 0x60580000, + 0x60380000, 0x60580000, + 0x60B80000, 0x60D80000, + 0x60B80000, 0x60D80000 + }; + + return bmem_regmap[bmem_index]; +} + +static calc_bmem_base_f calc_bmem_base_func(adi_apollo_bmem_loc_e bmem_loc) +{ + static calc_bmem_base_f bmem_base_func[3] = { + &calc_bmem_hsdin_base, &calc_bmem_cddc_base, &calc_bmem_fddc_base + }; + return bmem_base_func[bmem_loc]; +} + +static calc_bmem_base_f calc_sram_base_func(adi_apollo_bmem_loc_e bmem_loc) +{ + static calc_bmem_base_f bmem_base_func[3] = { + &calc_hsdin_bmem_sram_base, &calc_coarse_bmem_sram_base, &calc_fine_bmem_sram_base + }; + return bmem_base_func[bmem_loc]; +} diff --git a/drivers/iio/trx-rf/ad9088/private/src/adi_apollo_private_device.c b/drivers/iio/trx-rf/ad9088/private/src/adi_apollo_private_device.c new file mode 100644 index 00000000000000..709cbf0f535e1f --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/src/adi_apollo_private_device.c @@ -0,0 +1,531 @@ +/*! + * \brief Private device API implementations + * + * \copyright copyright(c) 2024 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_PRIVATE_DEVICE + * @{ + */ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_config.h" +#include "adi_apollo_hal.h" +#include "adi_apollo_bmem_types.h" +#include "adi_apollo_cddc_types.h" +#include "adi_apollo_cduc_types.h" +#include "adi_apollo_cnco_types.h" +#include "adi_apollo_fnco_types.h" +#include "adi_apollo_fddc_types.h" +#include "adi_apollo_fduc_types.h" +#include "adi_apollo_invsinc_types.h" +#include "adi_apollo_pfilt_types.h" +#include "adi_apollo_sniffer_types.h" +#include "adi_apollo_smon_types.h" +#include "adi_apollo_txmux_types.h" +#include "adi_apollo_private_device.h" +#include "adi_apollo_bf_hsci.h" +#include "adi_utils.h" + +#define SEVEN_CONSECUTIVE_1S_VAL (0x7FU) // 0b01111111 +#define FIVE_CONSECUTIVE_1S_VAL (0x1FU) // 0b00011111 +#define THREE_CONSECUTIVE_1S_VAL (0x07U) // 0b00000111 +#define SEVEN_CONSECUTIVE_1S_INDEX_BOUNDS 3, 8 // Lower index = 3, Upper Index = 8 +#define FIVE_CONSECUTIVE_1S_INDEX_BOUNDS 2, 9 // Lower index = 2, Upper Index = 9 +#define THREE_CONSECUTIVE_1S_INDEX_BOUNDS 1, 10 // Lower index = 1, Upper Index = 10 + +/*============= C O D E ====================*/ + +static int32_t hsci_manual_linkup_enable_set(adi_apollo_device_t *device, uint8_t enable, uint16_t link_up_signal_bits); +static int32_t calc_rxclk_adj_from_eyediagram(adi_apollo_device_t *device, uint16_t eye_diagram, uint8_t *calc_rx_clk_adj); +static int32_t hsci_auto_linkup_enable_set(adi_apollo_device_t *device, uint8_t enable, uint8_t hscim_mosi_clk_inv, uint8_t hscim_miso_clk_inv); +static int32_t calc_rxclk_adj_from_link_table(adi_apollo_device_t *device, uint16_t apollo_alink_table, uint8_t *calc_rx_clk_adj); +static int32_t calc_txclk_adj_from_link_table(adi_apollo_device_t *device, uint16_t hscim_alink_table, uint8_t *calc_tx_clk_adj); +static int32_t apollo_hsci_clk_values_set(adi_apollo_device_t *device, uint8_t rx_inv, uint8_t rx_adj, uint8_t tx_inv, uint8_t tx_adj); +static int32_t apollo_hsci_clk_values_get(adi_apollo_device_t *device, uint8_t *rx_inv, uint8_t *rx_adj, uint8_t *tx_inv, uint8_t *tx_adj); +static int32_t apollo_hsci_auto_link_clk_values_get(adi_apollo_device_t *device, uint8_t *auto_rx_inv, uint8_t *auto_rx_adj, uint8_t *auto_tx_inv, uint8_t *auto_tx_adj); +static int32_t apollo_hsci_reset(adi_apollo_device_t *device, uint8_t do_hard_rst); +static __maybe_unused int32_t apollo_hsci_debug_clk_values_get(adi_apollo_device_t *device); +static __maybe_unused int32_t apollo_hsci_debug_error_reg_get(adi_apollo_device_t *device); + + +int32_t adi_apollo_private_device_hsci_manual_linkup_configure(adi_apollo_device_t *device) +{ + int32_t err; + uint16_t link_up_signal_bits = 0x155; + uint16_t eye_diagram = 0x00; + uint8_t rxclk_inv = 0; + uint8_t rxclk_adj = 0; + + ADI_CMS_NULL_PTR_CHECK(device); + ADI_APOLLO_LOG_FUNC(); + ADI_CMS_NULL_PTR_CHECK(device->hal_info.hsci_desc.manual_linkup); + + // Hard Reset HSCI On DUT + err = apollo_hsci_reset(device, 1); + ADI_CMS_ERROR_RETURN(err); + + // Enable HSCI Manual Linkup on Apollo and FPGA + err = hsci_manual_linkup_enable_set(device, 1, link_up_signal_bits); + ADI_CMS_ERROR_RETURN(err); + + // Clear Rx CLK Invert. + err = adi_apollo_hal_bf_set(device, BF_HSCI_RXCLK_INV_INFO, rxclk_inv); + ADI_APOLLO_ERROR_RETURN(err); + + // Read Positive Eye-diagram + err = adi_apollo_hal_bf_get(device, BF_HSCI_DIG_EYE_POS_INFO, (uint8_t *)&eye_diagram, 2); + ADI_CMS_ERROR_RETURN(err); + + // Calculate rxclk_adj value based on Positive Eye Diagram + err = calc_rxclk_adj_from_eyediagram(device, eye_diagram, &rxclk_adj); + ADI_CMS_ERROR_RETURN(err); + + // Set Rx CLK ADJ + err = adi_apollo_hal_bf_set(device, BF_HSCI_RXCLK_ADJ_INFO, rxclk_adj); + ADI_CMS_ERROR_RETURN(err); + + // Disable HSCI Manual linkup on Apollo and FPGA + err = hsci_manual_linkup_enable_set(device, 0, 0x00); + ADI_CMS_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_private_device_hsci_auto_linkup_configure(adi_apollo_device_t *device) +{ + int32_t err; + uint8_t retry_count = 0; + uint8_t hscim_mosi_clk_inv = 0; + uint8_t hscim_miso_clk_inv = 0; + uint16_t apollo_alink_table = 0; + uint16_t hscim_alink_table = 0; + uint8_t auto_rxclk_inv = 0; + uint8_t auto_txclk_inv = 0; + uint8_t auto_rxclk_adj = 0; // Useful for debug only + uint8_t auto_txclk_adj = 0; // Useful for debug only + uint8_t calc_rx_clk_adj = 0; + uint8_t calc_tx_clk_adj = 0; + uint8_t rx_calc_err_status = 0; + uint8_t tx_calc_err_status = 0; + uint8_t auto_linkup_achieved = 0; + + ADI_CMS_NULL_PTR_CHECK(device); + ADI_APOLLO_LOG_FUNC(); + ADI_CMS_NULL_PTR_CHECK(device->hal_info.hsci_desc.auto_linkup); + ADI_CMS_NULL_PTR_CHECK(device->hal_info.hsci_desc.alink_tbl_get); + + // Hard Reset HSCI On DUT + err = apollo_hsci_reset(device, 1); + ADI_CMS_ERROR_RETURN(err); + + do { + apollo_alink_table = 0x00; + hscim_alink_table = 0x00; + + // Enable HSCI Auto Linkup on Apollo and FPGA + err = hsci_auto_linkup_enable_set(device, 1, hscim_mosi_clk_inv, hscim_miso_clk_inv); + ADI_CMS_ERROR_RETURN(err); + + // Get Apollo auto linkup table + err = adi_apollo_hal_bf_get(device, BF_AUTO_LINK_TABLE_INFO, (uint8_t *) &apollo_alink_table, 2); + ADI_CMS_ERROR_RETURN(err); + + // Get FPGA auto linkup table + err = adi_apollo_hal_alink_tbl_get(device, &hscim_alink_table); + ADI_CMS_ERROR_RETURN(err); + + // Calculate rxclk_adj value based on AUTO_LINK_TABLE + // If valid rxclk_adj value isn't found, flip the MOSI_CLK_INV Bit and set error flag + err = calc_rxclk_adj_from_link_table(device, apollo_alink_table, &calc_rx_clk_adj); + if (err == API_CMS_ERROR_HSCI_LINK_UP) { + hscim_mosi_clk_inv ^= 0x01; + hscim_mosi_clk_inv &= 0x01; + rx_calc_err_status = 1; + } else { + rx_calc_err_status = 0; + } + + // Calculate txclk_adj value based on HSCIM_LINK_TABLE + // If valid txclk_adj value isn't found, flip the MISO_CLK_INV Bit and set error flag + err = calc_txclk_adj_from_link_table(device, hscim_alink_table, &calc_tx_clk_adj); + if (err == API_CMS_ERROR_HSCI_LINK_UP) { + hscim_miso_clk_inv ^= 0x01; + hscim_miso_clk_inv &= 0x01; + tx_calc_err_status = 1; + } else { + tx_calc_err_status = 0; + } + + // If any tx/rxclk_adj value is invalid, disable HSCI auto linkup on Apollo and FPGA + if ((rx_calc_err_status != 0) || (tx_calc_err_status != 0)) { + err = hsci_auto_linkup_enable_set(device, 0, hscim_mosi_clk_inv, hscim_miso_clk_inv); + ADI_CMS_ERROR_RETURN(err); + + auto_linkup_achieved = 0; + retry_count++; + } else { + auto_linkup_achieved = 1; + } + } while ((auto_linkup_achieved != 1) && (retry_count < 5)); + + if (auto_linkup_achieved == 0x01) { + ADI_APOLLO_LOG_MSG("Apollo HSCI Auto Link: Established."); + } else { + ADI_APOLLO_LOG_MSG("Apollo HSCI Auto Link: *** FAILED ***."); + ADI_CMS_ERROR_RETURN(API_CMS_ERROR_HSCI_LINK_UP); + } + + // Readback CLK setting updated during Auto linkup procedure + apollo_hsci_auto_link_clk_values_get(device, &auto_rxclk_inv, &auto_rxclk_adj, &auto_txclk_inv, &auto_txclk_adj); + ADI_CMS_ERROR_RETURN(err); + + // Disable HSCI Auto linkup on Apollo and FPGA + err = hsci_auto_linkup_enable_set(device, 0, hscim_mosi_clk_inv, hscim_miso_clk_inv); + ADI_CMS_ERROR_RETURN(err); + + // Overwrite HSCI port's clk setting with AUTO Tx/Rx CLK Invert and Calculated Tx/Rx CLK Adjust values. + err = apollo_hsci_clk_values_set(device, auto_rxclk_inv, calc_rx_clk_adj, auto_txclk_inv, calc_tx_clk_adj); + ADI_CMS_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +static int32_t hsci_manual_linkup_enable_set(adi_apollo_device_t *device, uint8_t enable, uint16_t link_up_signal_bits) +{ + int32_t err = 0; + + ADI_CMS_NULL_PTR_CHECK(device); + ADI_APOLLO_INVALID_PARAM_RETURN(enable > 1); + + // Enable HSCI port On Apollo + err = adi_apollo_hal_bf_set(device, BF_HSCI_EN_INFO, 1); + ADI_CMS_ERROR_RETURN(err); + + // Enables (or disables) manual linkup procedure in Apollo + err = adi_apollo_hal_bf_set(device, BF_HSCI_RX_LINKUP_MODE_INFO, enable); + ADI_CMS_ERROR_RETURN(err); + + // Enables (or disables) eye diagram + err = adi_apollo_hal_bf_set(device, BF_HSCI_CTRL_RX_EYE_EN_INFO, enable); + ADI_CMS_ERROR_RETURN(err); + + // Enable link-up on Master and Write Link-up signal on Master + err = adi_apollo_hal_manual_linkup(device, enable, link_up_signal_bits); + ADI_CMS_ERROR_RETURN(err); + + err = adi_apollo_hal_delay_us(device, 1000); + ADI_CMS_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +static int32_t calc_rxclk_adj_from_eyediagram(adi_apollo_device_t *device, uint16_t eye_diagram, uint8_t *calc_rx_clk_adj) +{ + ADI_APOLLO_LOG_VAR(ADI_CMS_LOG_API, "Apollo EYE_DIAGRAM: 0x%04X.", eye_diagram); + + if (!adi_api_utils_check_consecutive_ones_bounded(eye_diagram, FIVE_CONSECUTIVE_1S_VAL, FIVE_CONSECUTIVE_1S_INDEX_BOUNDS, calc_rx_clk_adj)) { + ADI_APOLLO_LOG_VAR(ADI_CMS_LOG_API, "There are 5 consecutive 1's in the Apollo's Eye-Diagram. Rx_clk_adj centered at index %d.", *calc_rx_clk_adj); + } else if (!adi_api_utils_check_consecutive_ones_bounded(eye_diagram, THREE_CONSECUTIVE_1S_VAL, THREE_CONSECUTIVE_1S_INDEX_BOUNDS, calc_rx_clk_adj)) { + ADI_APOLLO_LOG_VAR(ADI_CMS_LOG_API, "There are 3 consecutive 1's in the Apollo's Eye-Diagram. Rx_clk_adj centered at index %d.", *calc_rx_clk_adj); + } else { + *calc_rx_clk_adj = 0; // 0 is an invalid clk_adj value + ADI_APOLLO_LOG_ERR("There are no consecutive 1's of length 3 or 5, in Apollo's Eye-Diagram."); + ADI_CMS_ERROR_RETURN(API_CMS_ERROR_HSCI_LINK_UP); + } + + return API_CMS_ERROR_OK; +} + +static int32_t hsci_auto_linkup_enable_set(adi_apollo_device_t *device, uint8_t enable, uint8_t hscim_mosi_clk_inv, uint8_t hscim_miso_clk_inv) +{ + int32_t err = 0; + uint8_t i = 0; + uint8_t retry_count = 20; + uint8_t link_active = 0; + + ADI_CMS_NULL_PTR_CHECK(device); + ADI_APOLLO_INVALID_PARAM_RETURN(enable > 1); + ADI_APOLLO_INVALID_PARAM_RETURN(hscim_mosi_clk_inv > 1); + ADI_APOLLO_INVALID_PARAM_RETURN(hscim_miso_clk_inv > 1); + + // Enables (or disables) txclk_adj value to be overridden during auto linkup + err = adi_apollo_hal_bf_set(device, BF_TXCLK_ADJ_OVERRIDE_INFO, enable); + ADI_CMS_ERROR_RETURN(err); + + // Enables (or disables) auto linkup procedure in Apollo + err = adi_apollo_hal_bf_set(device, BF_HSCI_AUTO_LINKUP_INFO, enable); + ADI_CMS_ERROR_RETURN(err); + + // Enables HSCI port on Apollo + err = adi_apollo_hal_bf_set(device, BF_HSCI_EN_INFO, 1); + ADI_CMS_ERROR_RETURN(err); + + // Enables HSCI on FPGA using HAL func ptr and reset HSCIM if disabled + err = adi_apollo_hal_auto_linkup(device, enable, hscim_mosi_clk_inv, hscim_miso_clk_inv); + ADI_CMS_ERROR_RETURN(err); + + // When enabled, check if HSCI Link is established on Apollo + // And when disabled, soft resets the HSCI port on Apollo + if (enable) { + for (i = 0; i < retry_count; ++i) { + err = adi_apollo_hal_bf_get(device, BF_LINK_ACTIVE_INFO, &link_active, 1); + ADI_CMS_ERROR_RETURN(err); + + if (link_active == 0x01) { + ADI_APOLLO_LOG_MSG("Apollo HSCI Auto Link: Active."); + break; + } else if ((link_active == 0x00) && (i < (retry_count - 1))) { + ADI_APOLLO_LOG_MSG("Waiting for link to establish..."); + err = adi_apollo_hal_delay_us(device, 1000); + ADI_CMS_ERROR_RETURN(err); + } else { + ADI_APOLLO_LOG_MSG("Apollo HSCI Auto Link: *** FAILED ***."); + ADI_CMS_ERROR_RETURN(API_CMS_ERROR_OPERATION_TIMEOUT); + } + } + } else { + err = apollo_hsci_reset(device, 0); + ADI_CMS_ERROR_RETURN(err); + } + + return API_CMS_ERROR_OK; +} + + +static int32_t calc_rxclk_adj_from_link_table(adi_apollo_device_t *device, uint16_t apollo_alink_table, uint8_t *calc_rx_clk_adj) +{ + ADI_APOLLO_LOG_VAR(ADI_CMS_LOG_API, "Apollo AUTO_LINK_TABLE: 0x%04X.", apollo_alink_table); + + if (!adi_api_utils_check_consecutive_ones_bounded(apollo_alink_table, SEVEN_CONSECUTIVE_1S_VAL, SEVEN_CONSECUTIVE_1S_INDEX_BOUNDS, calc_rx_clk_adj)) { + ADI_APOLLO_LOG_VAR(ADI_CMS_LOG_API, "There are 7 consecutive 1's in the Apollo's AUTO_LINK_TABLE. Rx_clk_adj centered at index %d.", *calc_rx_clk_adj); + } else if (!adi_api_utils_check_consecutive_ones_bounded(apollo_alink_table, FIVE_CONSECUTIVE_1S_VAL, FIVE_CONSECUTIVE_1S_INDEX_BOUNDS, calc_rx_clk_adj)) { + ADI_APOLLO_LOG_VAR(ADI_CMS_LOG_API, "There are 5 consecutive 1's in the Apollo's AUTO_LINK_TABLE. Rx_clk_adj centered at index %d.", *calc_rx_clk_adj); + } else if (!adi_api_utils_check_consecutive_ones_bounded(apollo_alink_table, THREE_CONSECUTIVE_1S_VAL, THREE_CONSECUTIVE_1S_INDEX_BOUNDS, calc_rx_clk_adj)) { + ADI_APOLLO_LOG_VAR(ADI_CMS_LOG_API, "There are 3 consecutive 1's in the Apollo's AUTO_LINK_TABLE. Rx_clk_adj centered at index %d.", *calc_rx_clk_adj); + } else { + *calc_rx_clk_adj = 0; // 0 is an invalid clk_adj value + ADI_APOLLO_LOG_ERR("There are no consecutive 1's of length 3, 5 or 7, in Apollo's AUTO_LINK_TABLE."); + ADI_CMS_ERROR_RETURN(API_CMS_ERROR_HSCI_LINK_UP); + } + + return API_CMS_ERROR_OK; +} + +static int32_t calc_txclk_adj_from_link_table(adi_apollo_device_t *device, uint16_t hscim_alink_table, uint8_t *calc_tx_clk_adj) +{ + ADI_APOLLO_LOG_VAR(ADI_CMS_LOG_API, "FPGA HSCI_M ALINK_TABLE: 0x%04X.", hscim_alink_table); + + if (!adi_api_utils_check_consecutive_ones_bounded(hscim_alink_table, SEVEN_CONSECUTIVE_1S_VAL, SEVEN_CONSECUTIVE_1S_INDEX_BOUNDS, calc_tx_clk_adj)) { + ADI_APOLLO_LOG_VAR(ADI_CMS_LOG_API, "There are 7 consecutive 1's in the FPGA's ALINK_TABLE. Tx_clk_adj centered at index %d.", *calc_tx_clk_adj); + } else if (!adi_api_utils_check_consecutive_ones_bounded(hscim_alink_table, FIVE_CONSECUTIVE_1S_VAL, FIVE_CONSECUTIVE_1S_INDEX_BOUNDS, calc_tx_clk_adj)) { + ADI_APOLLO_LOG_VAR(ADI_CMS_LOG_API, "There are 5 consecutive 1's in the FPGA's ALINK_TABLE. Tx_clk_adj centered at index %d.", *calc_tx_clk_adj); + } else if (!adi_api_utils_check_consecutive_ones_bounded(hscim_alink_table, THREE_CONSECUTIVE_1S_VAL, THREE_CONSECUTIVE_1S_INDEX_BOUNDS, calc_tx_clk_adj)) { + ADI_APOLLO_LOG_VAR(ADI_CMS_LOG_API, "There are 3 consecutive 1's in the FPGA's ALINK_TABLE. Tx_clk_adj centered at index %d.", *calc_tx_clk_adj); + } else { + *calc_tx_clk_adj = 0; // 0 is an invalid clk_adj value + ADI_APOLLO_LOG_ERR("There are no consecutive 1's of length 3, 5 or 7, in FPGA's ALINK_TABLE."); + ADI_CMS_ERROR_RETURN(API_CMS_ERROR_HSCI_LINK_UP); + } + + return API_CMS_ERROR_OK; +} + + +static int32_t apollo_hsci_clk_values_set(adi_apollo_device_t *device, uint8_t rx_inv, uint8_t rx_adj, uint8_t tx_inv, uint8_t tx_adj) +{ + int32_t err = 0; + + ADI_CMS_NULL_PTR_CHECK(device); + ADI_APOLLO_INVALID_PARAM_RETURN(rx_inv > 1); + ADI_APOLLO_INVALID_PARAM_RETURN(rx_adj > 15); + ADI_APOLLO_INVALID_PARAM_RETURN(tx_inv > 1); + ADI_APOLLO_INVALID_PARAM_RETURN(tx_adj > 15); + + // Set Rx CLK Invert. + err = adi_apollo_hal_bf_set(device, BF_HSCI_RXCLK_INV_INFO, rx_inv); + ADI_CMS_ERROR_RETURN(err); + + // Set Rx CLK ADJ + err = adi_apollo_hal_bf_set(device, BF_HSCI_RXCLK_ADJ_INFO, rx_adj); + ADI_CMS_ERROR_RETURN(err); + + // Set Tx CLK Invert. + err = adi_apollo_hal_bf_set(device, BF_HSCI_TXCLK_INV_INFO, tx_inv); + ADI_CMS_ERROR_RETURN(err); + + // Set CLK ADJ + err = adi_apollo_hal_bf_set(device, BF_HSCI_TXCLK_ADJ_INFO, tx_adj); + ADI_CMS_ERROR_RETURN(err); + + ADI_APOLLO_LOG_VAR(ADI_CMS_LOG_API, "Set HSCI_ RXCLK_INV: %02d RXCLK_ADJ: %02d TXCLK_INV: %02d TXCLK_ADJ: %02d.", rx_inv, rx_adj, tx_inv, tx_adj); + + return API_CMS_ERROR_OK; +} + +static int32_t apollo_hsci_clk_values_get(adi_apollo_device_t *device, uint8_t *rx_inv, uint8_t *rx_adj, uint8_t *tx_inv, uint8_t *tx_adj) +{ + int32_t err = 0; + + ADI_CMS_NULL_PTR_CHECK(device); + ADI_CMS_NULL_PTR_CHECK(rx_inv); + ADI_CMS_NULL_PTR_CHECK(rx_adj); + ADI_CMS_NULL_PTR_CHECK(tx_inv); + ADI_CMS_NULL_PTR_CHECK(tx_adj); + + // Get HSCI RxCLK Invert + err = adi_apollo_hal_bf_get(device, BF_HSCI_RXCLK_INV_INFO, rx_inv, 1); + ADI_CMS_ERROR_RETURN(err); + + // Get HSCI RxCLK ADJ + err = adi_apollo_hal_bf_get(device, BF_HSCI_RXCLK_ADJ_INFO, rx_adj, 1); + ADI_CMS_ERROR_RETURN(err); + + // Get HSCI TxCLK Invert + err = adi_apollo_hal_bf_get(device, BF_HSCI_TXCLK_INV_INFO, tx_inv, 1); + ADI_CMS_ERROR_RETURN(err); + + // Get HSCI TxCLK ADJ + err = adi_apollo_hal_bf_get(device, BF_HSCI_TXCLK_ADJ_INFO, tx_adj, 1); + ADI_CMS_ERROR_RETURN(err); + + ADI_APOLLO_LOG_VAR(ADI_CMS_LOG_API, "Get HSCI_ RXCLK_INV: %02d RXCLK_ADJ: %02d TXCLK_INV: %02d TXCLK_ADJ: %02d.", + *rx_inv, *rx_adj, *tx_inv, *tx_adj); + + return API_CMS_ERROR_OK; +} + + +static int32_t apollo_hsci_auto_link_clk_values_get(adi_apollo_device_t *device, uint8_t *auto_rx_inv, uint8_t *auto_rx_adj, uint8_t *auto_tx_inv, uint8_t *auto_tx_adj) +{ + int32_t err = 0; + + ADI_CMS_NULL_PTR_CHECK(device); + ADI_CMS_NULL_PTR_CHECK(auto_rx_inv); + ADI_CMS_NULL_PTR_CHECK(auto_rx_adj); + ADI_CMS_NULL_PTR_CHECK(auto_tx_inv); + ADI_CMS_NULL_PTR_CHECK(auto_tx_adj); + + // Get AUTO RxCLK Invert + err = adi_apollo_hal_bf_get(device, BF_AUTO_RXCLK_INV_INFO, auto_rx_inv, 1); + ADI_CMS_ERROR_RETURN(err); + + // Get AUTO RxCLK ADJ + err = adi_apollo_hal_bf_get(device, BF_AUTO_RXCLK_ADJ_INFO, auto_rx_adj, 1); + ADI_CMS_ERROR_RETURN(err); + + // Get AUTO TxCLK Invert + err = adi_apollo_hal_bf_get(device, BF_AUTO_TXCLK_INV_INFO, auto_tx_inv, 1); + ADI_CMS_ERROR_RETURN(err); + + // Get AUTO TxCLK ADJ + err = adi_apollo_hal_bf_get(device, BF_AUTO_TXCLK_ADJ_INFO, auto_tx_adj, 1); + ADI_CMS_ERROR_RETURN(err); + + ADI_APOLLO_LOG_VAR(ADI_CMS_LOG_API, "Get AUTO_ RXCLK_INV: %02d RXCLK_ADJ: %02d TXCLK_INV: %02d TXCLK_ADJ: %02d.", + *auto_rx_inv, *auto_rx_adj, *auto_tx_inv, *auto_tx_adj); + + return API_CMS_ERROR_OK; +} + + +static int32_t apollo_hsci_reset(adi_apollo_device_t *device, uint8_t do_hard_rst) +{ + int32_t err = 0; + uint32_t reg = REG_MAIN_CTRL_ADDR; + uint32_t info = 0; + + ADI_CMS_NULL_PTR_CHECK(device); + ADI_APOLLO_INVALID_PARAM_RETURN(do_hard_rst > 1); + + info = (do_hard_rst == 1) ? BF_INFO_EXTRACT(BF_HSCI_HARD_RESET_INFO) : BF_INFO_EXTRACT(BF_HSCI_SOFT_RESET_INFO); + + err = adi_apollo_hal_bf_set(device, reg, info, 1); + ADI_CMS_ERROR_RETURN(err); + + err = adi_apollo_hal_delay_us(device, 1000); + ADI_CMS_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, reg, info, 0); + ADI_CMS_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +static int32_t apollo_hsci_debug_clk_values_get(adi_apollo_device_t *device) +{ + int32_t err = 0; + uint8_t rx_inv, rx_adj = 0; + uint8_t tx_inv, tx_adj = 0; + + ADI_CMS_NULL_PTR_CHECK(device); + + // Readback CLK setting used by HSCI Port + err = apollo_hsci_clk_values_get(device, &rx_inv, &rx_adj, &tx_inv, &tx_adj); + ADI_CMS_ERROR_RETURN(err); + + // Readback CLK setting updated during Auto linkup procedure + err = apollo_hsci_auto_link_clk_values_get(device, &rx_inv, &rx_adj, &tx_inv, &tx_adj); + ADI_CMS_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +static int32_t apollo_hsci_debug_error_reg_get(adi_apollo_device_t *device) +{ + int32_t err = 0; + uint8_t reg_read = 0; + + ADI_CMS_NULL_PTR_CHECK(device); + + // ERROR_STATUS + err = adi_apollo_hal_reg_get(device, REG_ERROR_STATUS_ADDR, ®_read); + ADI_CMS_ERROR_RETURN(err); + ADI_APOLLO_LOG_VAR(ADI_CMS_LOG_API, "ERROR_STATUS (0x%08X): 0x%02X.", REG_ERROR_STATUS_ADDR, reg_read); + + // ERROR_FLAG_DIS + err = adi_apollo_hal_reg_get(device, REG_ERROR_FLAG_DIS_ADDR, ®_read); + ADI_CMS_ERROR_RETURN(err); + ADI_APOLLO_LOG_VAR(ADI_CMS_LOG_API, "ERROR_FLAG_DIS (0x%08X): 0x%02X.", REG_ERROR_FLAG_DIS_ADDR, reg_read); + + // FSM_STATUS + err = adi_apollo_hal_reg_get(device, REG_FSM_STATUS_ADDR, ®_read); + ADI_CMS_ERROR_RETURN(err); + ADI_APOLLO_LOG_VAR(ADI_CMS_LOG_API, "FSM_STATUS (0x%08X): 0x%02X.", REG_FSM_STATUS_ADDR, reg_read); + + // AHB_FSM_STATUS + err = adi_apollo_hal_reg_get(device, REG_AHB_FSM_STATUS_ADDR, ®_read); + ADI_CMS_ERROR_RETURN(err); + ADI_APOLLO_LOG_VAR(ADI_CMS_LOG_API, "AHB_FSM_STATUS (0x%08X): 0x%02X.", REG_AHB_FSM_STATUS_ADDR, reg_read); + + // AUTO_LINK_TABLE_LO + err = adi_apollo_hal_reg_get(device, REG_AUTO_LINK_TABLE_LO_ADDR, ®_read); + ADI_CMS_ERROR_RETURN(err); + ADI_APOLLO_LOG_VAR(ADI_CMS_LOG_API, "AUTO_LINK_TABLE_LO (0x%08X): 0x%02X.", REG_AUTO_LINK_TABLE_LO_ADDR, reg_read); + + // AUTO_LINK_TABLE_HI + err = adi_apollo_hal_reg_get(device, REG_AUTO_LINK_TABLE_HI_ADDR, ®_read); + ADI_CMS_ERROR_RETURN(err); + ADI_APOLLO_LOG_VAR(ADI_CMS_LOG_API, "AUTO_LINK_TABLE_HI (0x%08X): 0x%02X.", REG_AUTO_LINK_TABLE_HI_ADDR, reg_read); + + // HSCI_ERR_INFO + err = adi_apollo_hal_reg_get(device, REG_HSCI_ERR_INFO_ADDR, ®_read); + ADI_CMS_ERROR_RETURN(err); + ADI_APOLLO_LOG_VAR(ADI_CMS_LOG_API, "HSCI_ERR_INFO (0x%08X): 0x%02X.", REG_HSCI_ERR_INFO_ADDR, reg_read); + + return API_CMS_ERROR_OK; +} + + +uint8_t adi_apollo_private_device_lockout_get(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_private_device_feat_lockout_e feat) +{ + return (terminal == ADI_APOLLO_RX ? + (device->dev_info.lockout_mask.rx_lockout_mask & (1ul << feat)) : + (device->dev_info.lockout_mask.tx_lockout_mask & (1ul << feat))) != 0; +} + +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/private/src/adi_apollo_private_sysclk_cond.c b/drivers/iio/trx-rf/ad9088/private/src/adi_apollo_private_sysclk_cond.c new file mode 100644 index 00000000000000..137a6ceb613c3f --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/private/src/adi_apollo_private_sysclk_cond.c @@ -0,0 +1,95 @@ +/*! + * \brief: Apollo private system clock calibration functions + * + * \copyright copyright(c) 2023 Analog Devices, Inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated Analog Devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_SYSCLK_COND + * @{ + */ + +#include "adi_apollo_private_sysclk_cond.h" +#include "adi_apollo_cfg_types.h" +#include "adi_apollo_config.h" +#include "adi_apollo_hal.h" + +int32_t adi_apollo_private_sysclk_cond_defaults_set(adi_apollo_device_t *device, adi_apollo_clk_cfg_t *clk_cfg) +{ + int32_t err; + /* Initial clock conditioning constants. ***Do not modify*** */ + uint32_t cc_config_address, cc_cal_data_address_a, cc_cal_data_address_b; + uint32_t cal_data[88] = { 0 }; + uint8_t low_speed = clk_cfg->dev_clk_freq_Hz < 15000000000ULL; + adi_apollo_sysclk_cond_calconfig_t calconfig = { + .adc_centering_capture_length_Kb = low_speed ? 1 : 8, + .adc_centering_capture_avg = low_speed ? 1 : 8, + .adc_centering_capture_runs = 1, + .adc_centering_done = 0, + .adc_centering_use_debubbler = 1, + .adc_centering_use_noise_not_spread = 1, + .adc_use_caldata = 0, + .adc_centering_min_valid_offset = -26, + .adc_centering_max_valid_offset = 14, + .adc_centering_low_threshold = 3395, // floor(10^(-155dB/10dB) * 10e9 * 2^30 + 0.5) = 3395 + .adc_centering_high_threshold = low_speed ? 10737418 : 2142397, + .adc_centering_precapture_delayus = 10000, + .adc_post_correction_delayus = 0, + }; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_hal_reg32_get(device, APOLLO_CPU_1_FW_CLK_COND_CONFIG_PTR, &cc_config_address); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_reg32_get(device, APOLLO_CPU_1_FW_CLK_COND_0_CALDATA_PTR, &cc_cal_data_address_a); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_reg32_get(device, APOLLO_CPU_1_FW_CLK_COND_1_CALDATA_PTR, &cc_cal_data_address_b); + ADI_APOLLO_ERROR_RETURN(err); + + cal_data[0] = (-5 << 16) & 0x00ff0000; // Side A default + err = adi_apollo_hal_stream_reg32_set(device, cc_cal_data_address_a, cal_data, sizeof(cal_data) / sizeof(cal_data[0]), false); + ADI_APOLLO_ERROR_RETURN(err); + + cal_data[0] = (-8 << 16) & 0x00ff0000; // Side B default + err = adi_apollo_hal_stream_reg32_set(device, cc_cal_data_address_b, cal_data, sizeof(cal_data) / sizeof(cal_data[0]), false); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_reg32_set(device, + cc_config_address + 0, + calconfig.adc_centering_capture_runs << 16 | + calconfig.adc_centering_capture_avg << 8 | + calconfig.adc_centering_capture_length_Kb); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_reg32_set(device, + cc_config_address + 4, + calconfig.adc_centering_min_valid_offset << 24 | + calconfig.adc_use_caldata << 16 | + calconfig.adc_centering_use_noise_not_spread << 8 | + calconfig.adc_centering_use_debubbler << 0); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_reg32_set(device, cc_config_address + 8, calconfig.adc_centering_max_valid_offset); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_reg32_set(device, cc_config_address + 12, calconfig.adc_centering_low_threshold); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_reg32_set(device, cc_config_address + 16, calconfig.adc_centering_high_threshold); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_reg32_set(device, + cc_config_address + 20, + calconfig.adc_post_correction_delayus << 16 | + calconfig.adc_centering_precapture_delayus << 0); + + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +/*! @} */ \ No newline at end of file diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo.h new file mode 100644 index 00000000000000..8d2347c2b85b79 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo.h @@ -0,0 +1,23 @@ +/*! + * \brief API header file + * This file contains all the publicly exposed methods and data + * structures to interface with API. + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO + * @{ + */ +#ifndef __ADI_APOLLO_H__ +#define __ADI_APOLLO_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_types.h" + +#endif /* __ADI_APOLLO_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_adc.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_adc.h new file mode 100644 index 00000000000000..63a8f4f496cd52 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_adc.h @@ -0,0 +1,416 @@ +/*! + * \brief ADC definition headers + * + * \copyright copyright(c) 2024 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_ADC + * @{ + */ +#ifndef __ADI_APOLLO_ADC_H__ +#define __ADI_APOLLO_ADC_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_adc_types.h" +#include "adi_apollo_cfg_types.h" + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Execute an ADC init (foreground) calibration + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] adcs Target ADC selector \ref adi_apollo_adc_select_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_adc_cal(adi_apollo_device_t *device, adi_apollo_blk_sel_t adcs); + +/** + * \brief Execute an ADC init (foreground) calibration with config option + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] adcs Target ADC selector \ref adi_apollo_adc_select_e + * \param[in] init_cal_cfg Initial cal configuration. Specify init defaults, NVM or user defined. \ref adi_apollo_init_cal_cfg_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_adc_init_cal(adi_apollo_device_t *device, adi_apollo_blk_sel_t adcs, adi_apollo_init_cal_cfg_e init_cal_cfg); + +/** + * @brief Start the ADC initialization calibration process without waiting for completion. + * + * This function initializes and starts the ADC foreground calibration for the specified ADC blocks. + * It sets up the calibration configuration and issues the necessary mailbox commands to begin calibration. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] adcs Target ADC selector \ref adi_apollo_adc_select_e + * \param[in] init_cal_cfg Initial cal configuration. Specify init defaults, NVM or user defined. \ref adi_apollo_init_cal_cfg_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_adc_init_cal_start(adi_apollo_device_t *device, adi_apollo_blk_sel_t adcs, adi_apollo_init_cal_cfg_e init_cal_cfg); + +/** + * @brief Wait for ADC initialization calibration to complete. + * + * It logs progress and detailed error information if the calibration fails or times out. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] adcs Target ADC selector \ref adi_apollo_adc_select_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_adc_init_cal_complete(adi_apollo_device_t *device, adi_apollo_blk_sel_t adcs); + +/** + * \brief Set ADC Sync Path Delay + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] delay_type Type of delay \ref adi_apollo_sync_path_delay_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_adc_sync_path_delay_set(adi_apollo_device_t *device, adi_apollo_sync_path_delay_e delay_type); + +/** + * \brief Set ADC Nyquist Zone + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] adcs Target ADC selector \ref adi_apollo_adc_select_e + * \param[in] nyquist_zone Nyquist zone: 1 = first Nyquist, 2 = second Nyquist + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_adc_nyquist_zone_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t adcs, uint32_t nyquist_zone); + + +/** + * \brief Get ADC Nyquist Zone + * \note Only one ADC select per call. Select one within ADI_APOLLO_ADC_A0 - ADI_APOLLO_ADC_B3. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] adc Target ADC selector \ref adi_apollo_adc_select_e + * \param[out] nyquist_zone Pointer to Nyquist zone return val. 1 = first Nyquist, 2 = second Nyquist + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_adc_nyquist_zone_get(adi_apollo_device_t *device, adi_apollo_blk_sel_t adc, uint32_t *nyquist_zone); + +/** + * \brief Get ADC background calibration state + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] adcs Target ADC selector \ref adi_apollo_adc_select_e + * \param[out] state Array of \ref adi_apollo_adc_bgcal_state_t structs containing per ADC bgcal error and state info + * Array/ADC indexes for 4T4R: 0: ADC A0, 1: ADC A1, 4: ADC B0, 5: ADC B1 + * \param[in] len Length of state array (should be 8) + * + * Common ADC bgcal states: + * 0x1A = > APOLLO_CALFRMWRK_STATE_RESUMED | APOLLO_CALFRMWRK_STATE_RUNNING | APOLLO_CALFRMWRK_STATE_ENABLED + * 0x25 = > APOLLO_CALFRMWRK_STATE_SUSPENDED | APOLLO_CALFRMWRK_STATE_INACTIVE | APOLLO_CALFRMWRK_STATE_DISABLED + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. +*/ +int32_t adi_apollo_adc_bgcal_state_get(adi_apollo_device_t *device, adi_apollo_blk_sel_t adcs, adi_apollo_adc_bgcal_state_t state[], uint32_t len); + +/** + * \brief Freeze the ADC background calibration + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] adcs Target ADC selector \ref adi_apollo_adc_select_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + * + * \note Use \ref adi_apollo_adc_bgcal_state_get to get background cal state info +*/ +int32_t adi_apollo_adc_bgcal_freeze(adi_apollo_device_t* device, adi_apollo_blk_sel_t adcs); + +/** + * \brief Unfreeze the ADC background calibration + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] adcs Target ADC selector \ref adi_apollo_adc_select_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + * + * \note Use \ref adi_apollo_adc_bgcal_state_get to get background cal state info +*/ +int32_t adi_apollo_adc_bgcal_unfreeze(adi_apollo_device_t *device, adi_apollo_blk_sel_t adcs); + +/** + * \brief Enable or Disable the ADC mode switching feature + * + * \note To enable ADC mode switching, this API needs to be called BEFORE loading the device profile into DUTs memory + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] enable 1 enables the mode switching feature, 0 disables it + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. +*/ +int32_t adi_apollo_adc_mode_switch_enable_set(adi_apollo_device_t *device, uint8_t enable); + +/** + * \brief Perform setup sequence for the ADC Mode Switch for select ADCs. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] adcs Target ADC selector \ref adi_apollo_adc_select_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. +*/ +int32_t adi_apollo_adc_mode_switch_prepare(adi_apollo_device_t *device, adi_apollo_blk_sel_t adcs); + +/** + * \brief Execute ADC Slice Mode Switch for select ADCs. For fast switch, this API is replaced by GPIO toggle with func mode ADI_APOLLO_FUNC_ADC_MODE_SWITCH + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] adcs Target ADC selector \ref adi_apollo_adc_select_e + * \param[in] method Execute switch via fw or regmap. Parameter ADI_APOLLO_ADC_MODE_SWITCH_BY_GPIO is invalid \ref adi_apollo_adc_mode_switch_method_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. +*/ +int32_t adi_apollo_adc_mode_switch_execute(adi_apollo_device_t *device, adi_apollo_blk_sel_t adcs, adi_apollo_adc_mode_switch_method_e method); + +/** + * \brief Perform restore/cleanup sequence for the ADC Mode Switch for select ADCs. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] adcs Target ADC selector \ref adi_apollo_adc_select_e + * \param[in] enable_bgcal 1: Re-enable background cals 0: leave bgcal disabled + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. +*/ +int32_t adi_apollo_adc_mode_switch_restore(adi_apollo_device_t *device, adi_apollo_blk_sel_t adcs, uint8_t enable_bgcal); + +/** + * \brief Program fast detect settings + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] adcs Target ADC selector \ref adi_apollo_adc_select_e + * \param[in] config Fast detect settings \ref adi_apollo_adc_fast_detect_pgm_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. +*/ +int32_t adi_apollo_adc_fast_detect_pgm(adi_apollo_device_t *device, adi_apollo_blk_sel_t adcs, const adi_apollo_adc_fast_detect_pgm_t *config); + +/** + * \brief Read fast detect status from fw + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] adc Target ADC selector \ref adi_apollo_adc_select_e + * \param[out] fast_detect 1 if signal is detected, 0 otherwise + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. +*/ +int32_t adi_apollo_adc_fast_detect_status_get(adi_apollo_device_t *device, adi_apollo_blk_sel_t adc, uint8_t *fast_detect); + +/** + * \brief Get ADC status data + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[out] status ADC status \ref adi_apollo_adc_status_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. +*/ +int32_t adi_apollo_adc_status_get(adi_apollo_device_t *device, adi_apollo_adc_status_t *status); + +/** + * \brief Sets ADC cal gating on groups of calibrations preventing them from operating during background calibration. + * \note ADC BG Cal should be freezed (i.e paused) before calling this API. + * Changes made to the Calibration Gating configuration will take effect upon re-enabling bg calibration. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] adcs Target ADC selector \ref adi_apollo_adc_select_e + * \param[in] cal_gates ADC Background Calibration Gating Groups. \ref adi_apollo_adc_cal_group_gate_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_adc_bg_cal_grp_gate_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t adcs, uint32_t cal_gates); + + +/** + * \brief Gets ADC cal gating applied on groups of background calibration. + * \note ADC BG Cal should be freezed (i.e paused) before calling this API. + * Changes made to the Calibration Gating configuration will take effect upon re-enabling bg calibration. + * Only one ADC select per call. Select one within ADI_APOLLO_ADC_A0 - ADI_APOLLO_ADC_B3. + * + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] adc Target ADC selector \ref adi_apollo_adc_select_e + * \param[out] cal_gates ADC Background Calibration Gating Groups. \ref adi_apollo_adc_cal_group_gate_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_adc_bg_cal_grp_gate_get(adi_apollo_device_t *device, adi_apollo_blk_sel_t adc, uint32_t *cal_gates); + +/** + * \brief ADC DEBUG ONLY (deliberately vague) + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] adcs Target ADC selector \ref adi_apollo_adc_select_e + * \param[in] debug_val ADC Debug Value + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_adc_debug0_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t adcs, uint32_t debug_val); + + +/** + * \brief ADC DEBUG ONLY (deliberately vague) + * \note Only one ADC select per call. Select one within ADI_APOLLO_ADC_A0 - ADI_APOLLO_ADC_B3. + * + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] adc Target ADC selector \ref adi_apollo_adc_select_e + * \param[out] debug_val ADC Debug Value + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_adc_debug0_get(adi_apollo_device_t *device, adi_apollo_blk_sel_t adc, uint32_t *debug_val); + +/** + * \brief Gets ADC input protection status for monitored events like power, over-range detection and amplitude diversion. + * When a given status toggles high, it will remain high until this API is called to read it. + * Upon reading, the status will be cleared to 0. + * \note Only one ADC select per call. Select one within ADI_APOLLO_ADC_A0 - ADI_APOLLO_ADC_B3. + * + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] adc Target ADC selector \ref adi_apollo_adc_select_e + * \param[out] input_status Pointer to Struct with ADC input status. \ref adi_apollo_adc_input_status_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_adc_input_status_get(adi_apollo_device_t *device, adi_apollo_blk_sel_t adc, adi_apollo_adc_input_status_t *input_status); + +/** + * \brief Configures the ADC input level which will engage Over Range Protection. + * The threshold can be adjusted in 0.5 dB steps from -0.5 dBFS to -4 dBFS, + * relative to nominal (500 mVpp) full-scale. Default threshold is -1 dBFS. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] adcs Target ADC selector \ref adi_apollo_adc_select_e + * \param[in] ovr_threshold Over-Range protection threshold level. \ref adi_apollo_adc_ovr_threshold_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_adc_ovr_threshold_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t adcs, uint32_t ovr_threshold); + +/** + * \brief Gets ADC's input level threshold which would engage Over-Range Protection. + * \note Only one ADC select per call. Select one within ADI_APOLLO_ADC_A0 - ADI_APOLLO_ADC_B3. + * + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] adc Target ADC selector \ref adi_apollo_adc_select_e + * \param[out] ovr_threshold Over-Range protection threshold level. \ref adi_apollo_adc_ovr_threshold_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_adc_ovr_threshold_get(adi_apollo_device_t *device, adi_apollo_blk_sel_t adc, uint32_t *ovr_threshold); + +/** + * \brief Configures the number of samples at or above the Over-Range Threshold required to + * engage Over-Range Protection. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] adcs Target ADC selector \ref adi_apollo_adc_select_e + * \param[in] num_samples Num of samples at or above threshold. Range 1 - 10000 Samples. + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_adc_ovr_samples_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t adcs, uint32_t num_samples); + +/** + * \brief Gets number of samples at or above over-range threshold which would engage Over-Range Protection. + * \note Only one ADC select per call. Select one within ADI_APOLLO_ADC_A0 - ADI_APOLLO_ADC_B3. + * + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] adc Target ADC selector \ref adi_apollo_adc_select_e + * \param[out] num_samples Num of samples at or above threshold. Range 1 - 10000 Samples. + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_adc_ovr_samples_get(adi_apollo_device_t *device, adi_apollo_blk_sel_t adc, uint32_t *num_samples); + +/** + * \brief Get the Calibration Co-efficient Status. + * \note Only one ADC select per call. Select one within ADI_APOLLO_ADC_A0 - ADI_APOLLO_ADC_B3. + * + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] adc Target ADC selector \ref adi_apollo_adc_select_e + * \param[out] coeff_status Calibration Co-efficient Status. + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_adc_fact_cal_status_get(adi_apollo_device_t *device, adi_apollo_blk_sel_t adc, uint64_t *coeff_status); + +/** + * \brief Set the Calibration Co-efficient Mode + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] adcs Target ADC selector \ref adi_apollo_adc_select_e + * \param[in] coeff_mode Calibration Co-efficient Mode. + * + + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_adc_fact_cal_mode_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t adcs, uint32_t coeff_mode); + +/** + * \brief Get the Calibration Co-efficient Mode. + * \note Only one ADC select per call. Select one within ADI_APOLLO_ADC_A0 - ADI_APOLLO_ADC_B3. + * + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] adc Target ADC selector \ref adi_apollo_adc_select_e + * \param[out] coeff_mode Calibration Co-efficient Mode. + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_adc_fact_cal_mode_get(adi_apollo_device_t *device, adi_apollo_blk_sel_t adc, uint32_t *coeff_mode); + +#ifdef __cplusplus +} +#endif + +#endif /*__ADI_APOLLO_ADC_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_adc_types.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_adc_types.h new file mode 100644 index 00000000000000..4ebb905184719e --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_adc_types.h @@ -0,0 +1,154 @@ +/*! + * \brief Apollo ADC types headers + * + * \copyright copyright(c) 2024 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_ADC + * @{ + */ +#ifndef __ADI_APOLLO_ADC_TYPES_H__ +#define __ADI_APOLLO_ADC_TYPES_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_cms_api_common.h" +#include "adi_apollo_common.h" +#include "adi_apollo_mailbox_types.h" + +/*============= D E F I N E S ==============*/ +#define ADI_APOLLO_4T4R_ADC_TIMEOUT 120 +#define ADI_APOLLO_8T8R_ADC_TIMEOUT 240 + +/*! + * \brief Enumerates ADC sync path delay types + */ +typedef enum { + ADI_APOLLO_SYNC_PATH_DELAY_ALL_HIGH = 0, + ADI_APOLLO_SYNC_PATH_DELAY_SAME_AS_CLK = 1, + ADI_APOLLO_SYNC_PATH_DELAY_MID_SCALE = 2, + ADI_APOLLO_SYNC_PATH_DELAY_ALL_LOW = 3 +} adi_apollo_sync_path_delay_e; + +/*! + * \brief Enumerates ADC Slice Modes + */ +typedef enum { + ADI_APOLLO_ADC_MODE_RANDOM = 0, + ADI_APOLLO_ADC_MODE_SEQUENTIAL = 1, + ADI_APOLLO_ADC_MODE_DISABLED = 255 +} adi_apollo_adc_mode_e; + +/*! + * \brief Enumerates methods available for ADC Slice mode switching + */ +typedef enum { + ADI_APOLLO_ADC_MODE_SWITCH_BY_COMMAND = 0, + ADI_APOLLO_ADC_MODE_SWITCH_BY_REGMAP = 1, + ADI_APOLLO_ADC_MODE_SWITCH_BY_GPIO = 2 +} adi_apollo_adc_mode_switch_method_e; + +/*! + * \brief Enumerates current state of ADC Tracking / BG Calibration + */ +typedef enum { + ADI_APOLLO_ADC_BGCAL_STATE_SUSPENDED = APOLLO_CALFRMWRK_STATE_SUSPENDED, /*!< code: 0x01 Cal's timer is not running */ + ADI_APOLLO_ADC_BGCAL_STATE_RESUMED = APOLLO_CALFRMWRK_STATE_RESUMED, /*!< code: 0x02 Cal's timer is running */ + ADI_APOLLO_ADC_BGCAL_STATE_INACTIVE = APOLLO_CALFRMWRK_STATE_INACTIVE, /*!< code: 0x04 Cal's Main function is not executing */ + ADI_APOLLO_ADC_BGCAL_STATE_RUNNING = APOLLO_CALFRMWRK_STATE_RUNNING, /*!< code: 0x08 Cal's Main function is executing */ + ADI_APOLLO_ADC_BGCAL_STATE_ENABLED = APOLLO_CALFRMWRK_STATE_ENABLED, /*!< code: 0x10 Cal is enabled back from the host */ + ADI_APOLLO_ADC_BGCAL_STATE_DISABLED = APOLLO_CALFRMWRK_STATE_DISABLED, /*!< code: 0x20 Cal is disabled from the host */ + ADI_APOLLO_ADC_BGCAL_STATE_ERROR = APOLLO_CALFRMWRK_STATE_ERROR, /*!< code: 0x40 Cal is errored out */ + ADI_APOLLO_ADC_BGCAL_STATE_UNKNOWN = 0xFFFF +} adi_apollo_adc_bgcal_state_e; + +/*! + * \brief ADC Background Calibration Gating Groups + */ +typedef enum { + ADI_APOLLO_ADC_CAL_GROUP_ALL_INP_DEP = 0x01U, /*!< All Input Dependent Calibrations */ + ADI_APOLLO_ADC_CAL_GROUP_IL_GAIN_0 = 0x02U, /*!< Interleaving Gain Option 0 */ + ADI_APOLLO_ADC_CAL_GROUP_IL_GAIN_1 = 0x04U, /*!< Interleaving Gain Option 1 */ + ADI_APOLLO_ADC_CAL_GROUP_IL_OFFSET = 0x08U, /*!< Interleaving Offset */ + ADI_APOLLO_ADC_CAL_GROUP_IL_TIMING = 0x10U, /*!< Interleaving Timing */ + ADI_APOLLO_ADC_CAL_GROUP_FE_NLE = 0x20U, /*!< Frontend Non-linearity */ +} adi_apollo_adc_cal_group_gate_e; + +/*! + * \brief ADC Over-Range Protection Threshold + */ +typedef enum { + ADI_APOLLO_ADC_OVR_THRESH_M0P5_DB = 0x00U, /*!< Engage Over-Range at -0.5 dBFS */ + ADI_APOLLO_ADC_OVR_THRESH_M1P0_DB = 0x01U, /*!< Engage Over-Range at -1.0 dBFS */ + ADI_APOLLO_ADC_OVR_THRESH_M1P5_DB = 0x02U, /*!< Engage Over-Range at -1.5 dBFS */ + ADI_APOLLO_ADC_OVR_THRESH_M2P0_DB = 0x03U, /*!< Engage Over-Range at -2.0 dBFS */ + ADI_APOLLO_ADC_OVR_THRESH_M2P5_DB = 0x04U, /*!< Engage Over-Range at -2.5 dBFS */ + ADI_APOLLO_ADC_OVR_THRESH_M3P0_DB = 0x05U, /*!< Engage Over-Range at -3.0 dBFS */ + ADI_APOLLO_ADC_OVR_THRESH_M3P5_DB = 0x06U, /*!< Engage Over-Range at -3.5 dBFS */ + ADI_APOLLO_ADC_OVR_THRESH_M4P0_DB = 0x07U, /*!< Engage Over-Range at -4.0 dBFS */ +} adi_apollo_adc_ovr_threshold_e; + +/*! + * \brief ADC Tracking / BG Cal error and status struct + */ +typedef struct { + uint32_t state_valid; /* 1 = bgcal_error and bgcal_state fields have valid values, 0 = state unknown */ + uint32_t bgcal_error; /* 0 = no error */ + uint32_t bgcal_state; /* cal state bits \ref adi_apollo_adc_bgcal_state_e */ +} adi_apollo_adc_bgcal_state_t; + +/*! + * \brief ADC Fast Detect Configuration struct + */ +typedef struct { + uint8_t enable; /*!< Enable (1) or disable (0) fast detect */ + uint32_t upper_threshold; /*!< Upper threshold value [threshold = ( 10^(dbfs/20) * 2^11 )] */ + uint32_t lower_threshold; /*!< Lower threshold value [threshold = ( 10^(dbfs/20) * 2^11 )] */ + uint32_t dwell_cycles; /*!< Dwell cycles number */ +} adi_apollo_adc_fast_detect_pgm_t; + +/*! + * \brief ADC Init (FG) Calibration Status struct + */ +typedef struct { + uint8_t err_status[ADI_APOLLO_ADC_NUM]; /*!< True if calibrations reporting an error [indices A0 -> A3 B0 -> B3] */ + uint32_t duration_ms; /*!< Duration in msec of the last initial calibration run */ + uint8_t since_power_up[ADI_APOLLO_ADC_NUM]; /*!< True if calibrations run since power up for each channel [indices A0 -> A3 B0 -> B3] */ + uint8_t last_run[ADI_APOLLO_ADC_NUM]; /*!< True if calibrations run in during the previous runInitCals() call for each channel [indices A0 -> A3 B0 -> B3] */ +} adi_apollo_adc_fg_cal_status_t; + +/*! + * \brief ADC Tracking (BG) Calibration Status struct + */ +typedef struct { + uint8_t enabled[ADI_APOLLO_ADC_NUM]; /*!< which ADC Rx tracking calibrations are enabled per channel. [indices A0 -> A3 B0 -> B3] \ref adi_apollo_adc_select_e */ + uint32_t error[ADI_APOLLO_ADC_NUM]; /*!< ADC Rx tracking calibration error per channel [indices A0 -> A3 B0 -> B3] */ + uint32_t state[ADI_APOLLO_ADC_NUM]; /*!< ADC Rx tracking calibration state per channel [indices A0 -> A3 B0 -> B3] \ref adi_apollo_adc_bgcal_state_e */ +} adi_apollo_adc_bg_cal_status_t; + +/*! + * \brief ADC Calibration Status struct + */ +typedef struct { + adi_apollo_adc_fg_cal_status_t fg_cal; /*!< Foreground cal information \ref adi_apollo_adc_fg_cal_status_t */ + adi_apollo_adc_bg_cal_status_t bg_cal; /*!< Background cal information \ref adi_apollo_adc_bg_cal_status_t */ + uint8_t mode[ADI_APOLLO_ADC_NUM]; /*!< ADC slice modes \ref adi_apollo_adc_mode_e [indices A0 -> A3 B0 -> B3] */ +} adi_apollo_adc_status_t; + +/*! + * \brief ADC input signal status monitored during calibration. + When the status goes high, it will remain high until it's read back. + * + */ +typedef struct { + uint8_t power; /*!< 1: ADC input signal does not have enough power */ + uint8_t amp_diversity; /*!< 1: Diversity of the amplitudes of the input samples fell below a predetermined threshold */ + uint8_t over_range; /*!< 1: Over-range detected */ +} adi_apollo_adc_input_status_t; + + +#endif /* __ADI_APOLLO_ADC_TYPES_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_arm.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_arm.h new file mode 100644 index 00000000000000..8924dc830e84f7 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_arm.h @@ -0,0 +1,232 @@ +/*! + * \brief Apollo ARM headers + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_ARM + * @{ + */ +#ifndef __ADI_APOLLO_ARM_H__ +#define __ADI_APOLLO_ARM_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_arm_types.h" + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Clear firmware boot status. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[out] status Boot status - Pointer to boot status variable + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_arm_boot_status(adi_apollo_device_t *device, uint8_t *status); + +/** + * \brief CPU ram boot error check. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_arm_ram_boot_error_check(adi_apollo_device_t *device); + +/** + * \brief Get firmware profile CRC status + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return API_CMS_ERROR_PROFILE_CRC Invalid profile CRC + */ +int32_t adi_apollo_arm_profile_crc_valid_get(adi_apollo_device_t *device); + +/** + * \brief CPU rom ec transfer validation. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_arm_rom_ec_transfer_check(adi_apollo_device_t *device); + +/** + * \brief Prapare cpu for firmware loading. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_arm_fwload_pre_config(adi_apollo_device_t *device); + +/** + * \brief Post firmware loading setup to boot cpu using uploaded fw binary. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_arm_fwload_post_config(adi_apollo_device_t *device); + +/** + * \brief Load memory to CPU ram + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] binary_info Pointer to the cpu binary loading config structure + * \param[in] chunk_sz_bytes Number of bytes to transfer to CPU at a time + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_arm_memload(adi_apollo_device_t *device, adi_apollo_arm_binary_info_t *binary_info, uint16_t chunk_sz_bytes); + +/** + * \brief Load device profile to CPU + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] profile adi_apollo_top_t structure pointer + * \param[in] chunk_sz_bytes Number of bytes to transfer to CPU at a time + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_arm_profile_write(adi_apollo_device_t *device, adi_apollo_top_t *profile, uint16_t chunk_sz_bytes); + +/** + * \brief Send device profile memory transfer complete indication to firmware + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] profile adi_apollo_top_t structure pointer + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_arm_profile_write_post_config(adi_apollo_device_t *device, adi_apollo_top_t *profile); + +/** + * \brief Load device firmware to CPU + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] core Target core. \ref adi_apollo_cpu_id_e + * \param[in] fw_image_buf Firmware binary byte array + * \param[in] fw_image_size_bytes Firmware image size + * \param[in] chunk_sz_bytes Number of bytes to transfer to CPU at a time + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_arm_firmware_buf_write(adi_apollo_device_t *device, uint8_t core, uint8_t fw_image_buf[], uint32_t fw_image_size_bytes, uint16_t chunk_sz_bytes); + +/** + * \brief Load device firmware to CPU + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] mem_addr_to_load Memory address where the firware buffer needs to be written. + * \param[in] fw_image_buf Firmware binary byte array + * \param[in] fw_image_size_bytes Firmware image size + * \param[in] chunk_sz_bytes Number of bytes to transfer to CPU at a time + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_arm_tye_firmware_buf_write(adi_apollo_device_t *device, uint32_t mem_addr_to_load, uint8_t fw_image_buf[], uint32_t fw_image_size_bytes, uint16_t chunk_sz_bytes); + +/** + * \brief Load device profile byte array to CPU + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] profile_buf Device profile byte array + * \param[in] profile_size_bytes Device profile buffer size + * \param[in] chunk_sz_bytes Number of bytes to transfer to CPU at a time + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_arm_profile_buf_write(adi_apollo_device_t *device, uint8_t profile_buf[], uint32_t profile_size_bytes, uint16_t chunk_sz_bytes); + +/** + * \brief Check if Tiny Enclave is bypassed or not + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[out] is_bypassed 1 = Tiny Enclave is bypassed, load standard binary. 0 = not bypassed, load TyE App pack binaries. + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_arm_tye_bypassed_get(adi_apollo_device_t *device, uint8_t *is_bypassed); + +/** + * \brief Triggers the arm cores to boot TyE FW + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_arm_tye_boot_ready_set(adi_apollo_device_t *device); + +/** + * \brief Validate if secure boot passes + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] is_encrypted FW in App pack is encrypted(1) or not(0) + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_arm_tye_validate_boot_completion(adi_apollo_device_t *device, uint8_t is_encrypted); + +/** + * \brief Get Firmware error codes + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[out] cpu_errs Struct containing firmware error codes + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_arm_err_codes_get(adi_apollo_device_t *device, adi_apollo_cpu_errors_t *cpu_errs); + +/** + * \brief Get FW IRQ OUT status + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[out] fw_irq_out Status of FW interrupt triggering - 1 triggered, 0 not triggered + * \param[out] irq_source Source of IRQ trigger \ref adi_apollo_fw_irq_out_source_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_arm_fw_irq_out_get(adi_apollo_device_t *device, uint8_t *fw_irq_out, uint32_t *irq_source); + +/** + * \brief Clear FW IRQ sticky bits + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_arm_fw_irq_out_clear(adi_apollo_device_t *device); + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_ARM_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_arm_types.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_arm_types.h new file mode 100644 index 00000000000000..7358d07457202b --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_arm_types.h @@ -0,0 +1,92 @@ +/*! + * \brief Apollo ARM types headers + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_ARM + * @{ + */ +#ifndef __ADI_APOLLO_ARM_TYPES_H__ +#define __ADI_APOLLO_ARM_TYPES_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_cms_api_common.h" +#include "adi_apollo_common.h" + +/*============= D E F I N E S ==============*/ + +#define ADI_APOLLO_ARM_BOOT_STATUS_READ_RETRY_COUNT (50U) +#define ADI_APOLLO_ROM_BOOT_STEP_EC_TRANSFER (4U) +#define ADI_APOLLO_RAM_BOOT_STEP_WAIT_FOR_CONFIG (0x1DU) +#define ADI_APOLLO_RAM_BOOT_STEP_DEVICE_CONFIG_CRC_CHECK (0x1EU) +#define ADI_APOLLO_CPU_BOOT_DONE (0x2EU) +#define ADI_APOLLO_CPU_BOOT_MAILBOX_READY (0x34U) + +#define ADI_SECURE_BOOT_STAGE_CHECK (0x7FU) +#define ADI_ENCR_SECURE_BOOT_STAGE_CHECK (0xFFU) + +#define ADI_APOLLO_ARM_EC_TRANSFER_STATUS_READ_RETRY_COUNT (50U) + +#define ADI_APOLLO_CPU1_PM_START MEM_CODE_MEMORY_B_0 +#define ADI_APOLLO_CPU0_PM_START MEM_CODE_MEMORY_A_6 + +#define ADI_APOLLO_FW_DEVICE_PROFILE_PTR (0x21000414U) + + +/*! + * \brief Enumerates shared memory banks between program memory and data memory for arm core. + Setting for the l1mem0_shared_bank_div_ctrl and l1mem1_shared_bank_div_ctrl registers. + */ +typedef enum { + ADI_APOLLO_DIV_IRAM_352K_DRAM_352K = 0x00U, /*!< Set program memory(IRAM) to 352KB and data memory(DRAM) to 352KB. */ + ADI_APOLLO_DIV_IRAM_288K_DRAM_416K = 0x01U, /*!< Set program memory(IRAM) to 288KB and data memory(DRAM) to 416KB. */ + ADI_APOLLO_DIV_IRAM_320K_DRAM_384K = 0x02U, /*!< Set program memory(IRAM) to 320KB and data memory(DRAM) to 384KB. */ + ADI_APOLLO_DIV_IRAM_384K_DRAM_320K = 0x03U, /*!< Set program memory(IRAM) to 384KB and data memory(DRAM) to 320KB. */ + ADI_APOLLO_DIV_IRAM_416K_DRAM_288K = 0x04U /*!< Set program memory(IRAM) to 416KB and data memory(DRAM) to 288KB. */ +} adi_apollo_cpu_memory_bank_div_sel_e; + +/*! +* \brief CPU firmware memory location select +*/ +typedef enum { + ADI_APOLLO_FW_CPU_0 = 0, /*!< Select Apollo CPU 0 firmware memory location */ + ADI_APOLLO_FW_CPU_1 = 1, /*!< Select Apollo CPU 1 firmware memory location */ + ADI_APOLLO_DEVICE_PROFILE = 2, /*!< Select Apollo device profile memory location */ + ADI_APOLLO_WARM_BOOT = 3, /*!< Select Apollo warm boot memory location */ +} adi_apollo_cpu_memory_sel_e; + + +typedef enum +{ + ADI_APOLLO_FW_IRQ_OUT_SOURCE_FDUC_A = 0x01u, /*< code: 0x01 interrupt source: FDUC_A */ + ADI_APOLLO_FW_IRQ_OUT_SOURCE_CDUC_A0 = 0x02u, /*< code: 0x02 interrupt source: CDUC_A0 */ + ADI_APOLLO_FW_IRQ_OUT_SOURCE_CDUC_A1 = 0x04u, /*< code: 0x04 interrupt source: CDUC_A1 */ + ADI_APOLLO_FW_IRQ_OUT_SOURCE_FDUC_B = 0x08u, /*< code: 0x08 interrupt source: FDUC_B */ + ADI_APOLLO_FW_IRQ_OUT_SOURCE_CDUC_B0 = 0x10u, /*< code: 0x10 interrupt source: CDUC_B0 */ + ADI_APOLLO_FW_IRQ_OUT_SOURCE_CDUC_B1 = 0x20u, /*< code: 0x20 interrupt source: CDUC_B1 */ +} adi_apollo_fw_irq_out_source_e; + +/*! + * \brief FW load config Structure + */ +typedef struct adi_apollo_arm_binary_info +{ + uint8_t *binary_ptr; /*!< Binary pointer */ + int32_t binary_sz_bytes; /*!< Binary size in bytes */ + uint32_t cpu_start_addr; /*!< CPU memory location */ + uint8_t is_cont; /*!< Indication of first vs cont txn */ +} adi_apollo_arm_binary_info_t; + +typedef struct { + int32_t last_cmd; /* FW error generated by last command execution */ + int32_t system; /* FW error generated by system code */ + int32_t track_cal; /* FW error generated by the tracking cals */ +} adi_apollo_cpu_errors_t; + +#endif /* __ADI_APOLLO_ARM_TYPES_H__ */ +/*! @} */ \ No newline at end of file diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_bmem.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_bmem.h new file mode 100644 index 00000000000000..dba164959c8869 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_bmem.h @@ -0,0 +1,326 @@ +/*! + * \brief BMEM Block definition headers + * + * \copyright copyright(c) 2024 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_BMEM + * @{ + */ +#ifndef __ADI_APOLLO_BMEM_H__ +#define __ADI_APOLLO_BMEM_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_bmem_types.h" + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Configures BMEM to AWG + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] bmems Target BMEM \ref adi_apollo_bmem_sel_e + * \param[in] config \ref adi_apollo_bmem_awg_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_bmem_hsdin_awg_config(adi_apollo_device_t *device, adi_apollo_blk_sel_t bmems, adi_apollo_bmem_awg_t *config); + +/** + * \brief Starts normal BMEM AWG in loop + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] bmems Target BMEM \ref adi_apollo_bmem_sel_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_bmem_hsdin_awg_start(adi_apollo_device_t *device, adi_apollo_blk_sel_t bmems); + +/** + * \brief Stops normal BMEM AWG + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] bmems Target BMEM \ref adi_apollo_bmem_sel_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_bmem_hsdin_awg_stop(adi_apollo_device_t *device, adi_apollo_blk_sel_t bmems); + +/** + * \brief Writes Rx BMEM SRAM. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] bmems Target BMEM \ref adi_apollo_bmem_sel_e + * \param[in] data Array of data to write. Each 32-bit word contains two 16-bit samples + * \param[in] length Number of 32-bit words to write. 64K max. + */ +int32_t adi_apollo_bmem_hsdin_awg_sram_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t bmems, uint32_t data[], uint32_t length); + +/** + * \brief Configures BMEM to AWG with 16-bit sample data. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] bmems Target BMEM \ref adi_apollo_bmem_sel_e + * \param[in] data16 Array of 16-bit data samples to play out of bmem awg. + * \param[in] data16_len Length of data array + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_bmem_hsdin_awg_sample_write(adi_apollo_device_t *device, adi_apollo_blk_sel_t bmems, int16_t data16[], uint32_t data16_len); + +/** + * \brief Configures BMEM to AWG with 16-bit sample data for 8T8R devices + * + * \note + * For 8T8R devices, BMEM instances split the sram memory between ADC pairs (e.g. A0/A2). + * This results in half the number of samples per converter channel. + * + * This function requires a user provided scratch memory. Prevents exceeding local stack limits. + * Apollo APIs don't use dynamic memory allocation. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] bmems Target BMEM \ref adi_apollo_bmem_sel_e + * \param[in] data16_0 Array of 16-bit data samples to play out of bmem awg for first ADC in pair + * \param[in] data16_1 Array of 16-bit data samples to play out of bmem awg for second ADC in pair + * \param[in] data16_len Length of data16_0 and data16_1 arrays + * \param[in] scratch32 User provided 32-bit scratch array. Used by function to assemble data and write mem. + * \param[in] scratch32_len Length of scratch32 array + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_bmem_hsdin_awg_sample_shared_write(adi_apollo_device_t *device, adi_apollo_blk_sel_t bmems, + int16_t data16_0[], int16_t data16_1[], uint32_t data16_len, + uint32_t scratch32[], uint32_t scratch32_len); + +/** + * \brief Configures BMEM to Capture + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] bmems Target BMEM \ref adi_apollo_bmem_sel_e + * \param[in] config \ref adi_apollo_bmem_capture_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_bmem_hsdin_capture_config(adi_apollo_device_t *device, adi_apollo_blk_sel_t bmems, adi_apollo_bmem_capture_t *config); + +/** + * \brief Runs normal BMEM capture + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] bmems Target BMEM \ref adi_apollo_bmem_sel_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_bmem_hsdin_capture_run(adi_apollo_device_t *device, adi_apollo_blk_sel_t bmems); + +/** + * \brief Reads Rx BMEM SRAM. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] bmems Target BMEM \ref adi_apollo_bmem_sel_e + * \param[out] data Data that is read out of each \ref adi_apollo_bmem_sel_e. Each 32-bit word contains two 16-bit samples + * \param[in] length Number of 32-bit words to read. 64K max. + */ +int32_t adi_apollo_bmem_hsdin_capture_get(adi_apollo_device_t *device, adi_apollo_blk_sel_t bmems, uint32_t data[], uint32_t length); + +/** + * \brief Sets BMEM sample delay + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] bmems Target BMEM \ref adi_apollo_bmem_sel_e + * \param[in] sample_delay Sample delay + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_bmem_hsdin_delay_sample_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t bmems, uint16_t sample_delay); + +/** + * \brief Sets BMEM delay for the 4 hopping profiles + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] bmems Target BMEM \ref adi_apollo_bmem_sel_e + * \param[in] sample_delay Sample delay array - 4 elements + * \param[in] sample_delay_length Sample delay array length (must be 4) + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_bmem_hsdin_delay_hop_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t bmems, uint16_t sample_delay[], uint32_t sample_delay_length); + +/** + * \brief Configures BMEM to delay + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] bmems Target BMEM \ref adi_apollo_bmem_sel_e + * \param[in] config BMEM delay config \ref adi_apollo_bmem_delay_sample_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_bmem_hsdin_delay_sample_config(adi_apollo_device_t *device, adi_apollo_blk_sel_t bmems, adi_apollo_bmem_delay_sample_t *config); + +/** + * \brief Configures BMEM to delay with hopping mode + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] bmems Target BMEM \ref adi_apollo_bmem_sel_e + * \param[in] config BMEM delay config \ref adi_apollo_bmem_delay_hop_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_bmem_hsdin_delay_hop_config(adi_apollo_device_t *device, adi_apollo_blk_sel_t bmems, adi_apollo_bmem_delay_hop_t *config); + +/** + * \brief Starts BMEM sample delay + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] bmems Target BMEM \ref adi_apollo_bmem_sel_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_bmem_hsdin_delay_start(adi_apollo_device_t *device, adi_apollo_blk_sel_t bmems); + +/** + * \brief Sets BMEM sample delay + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] bmems Target BMEM \ref adi_apollo_bmem_sel_e + * \param[in] sample_delay Sample delay + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_bmem_cddc_delay_sample_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t bmems, uint16_t sample_delay); + +/** + * \brief Sets BMEM delay for the 4 hopping profiles + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] bmems Target BMEM \ref adi_apollo_bmem_sel_e + * \param[in] sample_delay Sample delay array - 4 elements + * \param[in] sample_delay_length Sample delay array length (must be 4) + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_bmem_cddc_delay_hop_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t bmems, uint16_t sample_delay[], uint32_t sample_delay_length); + +/** + * \brief Configures BMEM to delay + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] bmems Target BMEM \ref adi_apollo_bmem_sel_e + * \param[in] config BMEM delay config \ref adi_apollo_bmem_delay_sample_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_bmem_cddc_delay_sample_config(adi_apollo_device_t *device, adi_apollo_blk_sel_t bmems, adi_apollo_bmem_delay_sample_t *config); + +/** + * \brief Configures BMEM to delay with hopping mode + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] bmems Target BMEM \ref adi_apollo_bmem_sel_e + * \param[in] config BMEM delay config \ref adi_apollo_bmem_delay_hop_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_bmem_cddc_delay_hop_config(adi_apollo_device_t *device, adi_apollo_blk_sel_t bmems, adi_apollo_bmem_delay_hop_t *config); + +/** + * \brief Starts BMEM sample delay + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] bmems Target BMEM \ref adi_apollo_bmem_sel_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_bmem_cddc_delay_start(adi_apollo_device_t *device, adi_apollo_blk_sel_t bmems); + +/** + * \brief Sets BMEM sample delay + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] bmems Target BMEM \ref adi_apollo_bmem_sel_e + * \param[in] sample_delay Sample delay + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_bmem_fddc_delay_sample_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t bmems, uint16_t sample_delay); + +/** + * \brief Sets BMEM delay for the 4 hopping profiles + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] bmems Target BMEM \ref adi_apollo_bmem_sel_e + * \param[in] sample_delay Sample delay array - 4 elements + * \param[in] sample_delay_length Sample delay array length (must be 4) + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_bmem_fddc_delay_hop_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t bmems, uint16_t sample_delay[], uint32_t sample_delay_length); + +/** + * \brief Configures BMEM to delay + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] bmems Target BMEM \ref adi_apollo_bmem_sel_e + * \param[in] config BMEM delay config \ref adi_apollo_bmem_delay_sample_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_bmem_fddc_delay_sample_config(adi_apollo_device_t *device, adi_apollo_blk_sel_t bmems, adi_apollo_bmem_delay_sample_t *config); + +/** + * \brief Configures BMEM to delay with hopping mode + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] bmems Target BMEM \ref adi_apollo_bmem_sel_e + * \param[in] config BMEM delay config \ref adi_apollo_bmem_delay_hop_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_bmem_fddc_delay_hop_config(adi_apollo_device_t *device, adi_apollo_blk_sel_t bmems, adi_apollo_bmem_delay_hop_t *config); + +/** + * \brief Starts BMEM sample delay + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] bmems Target BMEM \ref adi_apollo_bmem_sel_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_bmem_fddc_delay_start(adi_apollo_device_t *device, adi_apollo_blk_sel_t bmems); + + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_BMEM_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_bmem_types.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_bmem_types.h new file mode 100644 index 00000000000000..c0e4046a596f78 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_bmem_types.h @@ -0,0 +1,104 @@ +/*! + * \brief BMEM Block definition headers + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_BMEM + * @{ + */ +#ifndef __ADI_APOLLO_BMEM_TYPES_H__ +#define __ADI_APOLLO_BMEM_TYPES_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_cms_api_common.h" +#include "adi_apollo_common.h" + +/*============= D E F I N E S ==============*/ +#define ADI_APOLLO_BMEM_NUM 8 +#define ADI_APOLLO_BMEM_PER_SIDE 4 +#define ADI_APOLLO_BMEM_HOP_PROFILES 4 +#define ADI_APOLLO_BMEM_HSDIN_MEM_SIZE_BYTES (128*1024) +#define ADI_APOLLO_BMEM_HSDIN_MEM_SIZE_WORDS (ADI_APOLLO_BMEM_HSDIN_MEM_SIZE_BYTES/4) +#define ADI_APOLLO_BMEM_CDDC_MEM_SIZE_BYTES (16*1024) +#define ADI_APOLLO_BMEM_CDDC_MEM_SIZE_WORDS (ADI_APOLLO_BMEM_CDDC_MEM_SIZE_BYTES/4) +#define ADI_APOLLO_BMEM_FDDC_MEM_SIZE_BYTES (2*1024) +#define ADI_APOLLO_BMEM_FDDC_MEM_SIZE_WORDS (ADI_APOLLO_BMEM_FDDC_MEM_SIZE_BYTES/4) + +/*! +* \brief Enumerates BMEM selection +*/ + +typedef enum { + ADI_APOLLO_BMEM_NONE = 0x00, /*!< No BMEM */ + ADI_APOLLO_BMEM_A0 = 0x01, /*!< BMEM 0 of SIDE A */ + ADI_APOLLO_BMEM_A1 = 0x02, /*!< BMEM 1 of SIDE A */ + ADI_APOLLO_BMEM_A2 = 0x04, /*!< BMEM 2 of SIDE A */ + ADI_APOLLO_BMEM_A3 = 0x08, /*!< BMEM 3 of SIDE A */ + ADI_APOLLO_BMEM_B0 = 0x10, /*!< BMEM 0 of SIDE B */ + ADI_APOLLO_BMEM_B1 = 0x20, /*!< BMEM 1 of SIDE B */ + ADI_APOLLO_BMEM_B2 = 0x40, /*!< BMEM 2 of SIDE B */ + ADI_APOLLO_BMEM_B3 = 0x80, /*!< BMEM 3 of SIDE B */ + ADI_APOLLO_BMEM_ALL = 0xFF, /*!< All BMEM */ + ADI_APOLLO_BMEM_ALL_4T4R = 0xFF, /*!< All BMEM (4T4R) */ +} adi_apollo_bmem_sel_e; + +/*! +* \brief Enumerates BMEM locations +*/ + +typedef enum { + ADI_APOLLO_BMEM_HSDIN = 0, /*!< HSDIN/ADC BMEM */ + ADI_APOLLO_BMEM_CDDC = 1, /*!< Coarse BMEM */ + ADI_APOLLO_BMEM_FDDC = 2, /*!< Fine BMEM */ +} adi_apollo_bmem_loc_e; + +/*! +* \brief BMEM Capture mode configuration data +*/ +typedef struct { + uint8_t sample_size; /*!< 0: NORMAL 16b, 1: DEBUG 32b */ + uint8_t ramclk_ph_dis; /*!< Set 1 to Disable SRAM Clock Phasing. */ + uint16_t st_addr_cpt; /*!< Start Address of SRAM in Capture Mode */ + uint16_t end_addr_cpt; /*!< End Address of SRAM in Capture Mode */ + uint8_t parity_check_en; /*!< Set 1 to Enable Parity Check on Data Read from SRAM. */ +} adi_apollo_bmem_capture_t; + +/*! +* \brief BMEM AWG mode configuration data +*/ +typedef struct { + uint8_t sample_size; /*!< 0: NORMAL 16b, 1: DEBUG 32b */ + uint8_t ramclk_ph_dis; /*!< Set 1 to Disable SRAM Clock Phasing. */ + uint8_t parity_check_en; /*!< Set 1 to Enable Parity Check on Data Read from SRAM. */ +} adi_apollo_bmem_awg_t; + +/*! +* \brief BMEM delay mode configuration data +*/ +typedef struct { + uint8_t sample_size; /*!< 0: NORMAL 16b, 1: DEBUG 32b */ + uint8_t ramclk_ph_dis; /*!< Set 1 to Disable SRAM Clock Phasing. */ + uint16_t sample_delay; /*!< Only used if trig_mode == 0 */ + uint8_t parity_check_en; /*!< Set 1 to Enable Parity Check on Data Read from SRAM. */ +} adi_apollo_bmem_delay_sample_t; + +/*! +* \brief BMEM delay mode with hopping configuration data +*/ +typedef struct { + uint8_t sample_size; /*!< 0: NORMAL 16b, 1: DEBUG 32b */ + uint8_t ramclk_ph_dis; /*!< Set 1 to Disable SRAM Clock Phasing. */ + uint16_t hop_delay[ADI_APOLLO_BMEM_HOP_PROFILES]; /*!< Sample delay profiles */ + uint8_t hop_delay_sel_mode; /*!< 0 to cycle 0-1-2-3-0 1 for gpio select next profile */ + uint8_t trig_mode_sclr_en; /*!< Set to 1 to self clear after a trigger */ + uint8_t parity_check_en; /*!< Set 1 to Enable Parity Check on Data Read from SRAM. */ +} adi_apollo_bmem_delay_hop_t; + + +#endif /* __ADI_APOLLO_BMEM_TYPES_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_cddc.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_cddc.h new file mode 100644 index 00000000000000..18d95d08ac8a4d --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_cddc.h @@ -0,0 +1,149 @@ +/*! + * \brief Coarse DDC functional block API prototypes + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_CDDC + * @{ + */ +#ifndef __ADI_APOLLO_CDDC_H__ +#define __ADI_APOLLO_CDDC_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_cddc_types.h" + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Set the coarse DDC decimation + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] cddcs Target CDDC. ADI_APOLLO_CDDC_A0, _A0 to A3, B0 to B3, _ALL \ref adi_apollo_cddc_select_e + * \param[in] dcm Coarse decimation. ADI_APOLLO_CDDC_RATIO_1, _2, _3, _4, _6, _12 \ref adi_apollo_cddc_ratio_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cddc_dcm_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t cddcs, adi_apollo_cddc_ratio_e dcm); + +/** + * \brief Set the coarse DDC link num + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] cddcs Target CDDC \ref adi_apollo_cddc_select_e + * \param[in] link_num Jesd link num cddc is sent to (req's if fddc bypassed) 0 = link0, 1 = link1 + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cddc_link_num_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t cddcs, uint8_t link_num); + +/** + * \brief Set state of coarse DDC debug clocks + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] cddcs Target CDDC \ref adi_apollo_cddc_select_e + * \param[in] clkoff_n Set to 0xff for normal operation. See bitfield COARSE_CLK_DEBUG. + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cddc_debug_clkoff_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t cddcs, uint8_t clkoff_n); + +/** + * \brief Configure CDDC parameters + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] cddcs Target CDDC \ref adi_apollo_cddc_select_e + * \param[in] config CDDC configuration \ref adi_apollo_cddc_pgm_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cddc_pgm(adi_apollo_device_t *device, adi_apollo_blk_sel_t cddcs, adi_apollo_cddc_pgm_t *config); + +/** + * \brief Inspect CDDC parameters + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] cddc Single Target CDDC \ref adi_apollo_cddc_select_e + * \param[out] cddc_inspect Pointer to cddc inspect structure. \ref adi_apollo_cddc_inspect_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cddc_inspect(adi_apollo_device_t *device, adi_apollo_blk_sel_t cddc, adi_apollo_cddc_inspect_t *cddc_inspect); + +/** + * \brief Sets the fine ddc bypass + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] cddcs Target CDDC \ref adi_apollo_cddc_select_e + * \param[in] bypass_enable 0 = don't bypass fddc, 1 = bypass fddc. CDDC output is sent directly to dformat + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cddc_fine_bypass_enable(adi_apollo_device_t *device, adi_apollo_blk_sel_t cddcs, uint8_t bypass_enable); + +/** + * \brief Determine the numeric CDDC decimation value from the associated enum. Enum vals are HW specific + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] bf_enum Enum that contains register bitfield value for decimation. + * \param[out] val Numeric value of decimation bf enum. + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cddc_dcm_bf_to_val(adi_apollo_device_t *device, adi_apollo_cddc_ratio_e bf_enum, uint32_t *val); + +/** + * \brief Enable or disable CDDC +6dB filter gains + * + * The CDDC block contains +6dB gain options for the HB1 and TB1 filters. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] cddcs Target CDDC \ref adi_apollo_cddc_select_e + * \param[in] filt_sel Filter selections. Selections include HB1 or TB1. \ref adi_apollo_cddc_gain_select_e + * \param[in] enable Enable flag. 0: disable, 1: enable + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cddc_gain_enable_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t cddcs, uint16_t filt_sel, uint8_t enable); + +/** + * \brief Get state of the CDDC HB1 or TB1 +6dB gain + * + * The CDDC block contains +6dB gain options for the HB1 and TB1 filters. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] cddcs Target CDDC. Single selection only. \ref adi_apollo_cddc_select_e + * \param[in] filt_sel Filter selection. Single selection only. \ref adi_apollo_cddc_gain_select_e + * \param[out] enable Enable flag. 0: disable, 1: enable + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cddc_gain_enable_get(adi_apollo_device_t *device, adi_apollo_blk_sel_t cddcs, uint16_t filt_sel, uint8_t *enable); + + +#ifndef CLIENT_IGNORE + +#endif /* CLIENT_IGNORE*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_CDDC_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_cddc_types.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_cddc_types.h new file mode 100644 index 00000000000000..906c69ae9f2d71 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_cddc_types.h @@ -0,0 +1,87 @@ +/*! + * \brief Coarse DDC functional block definitions + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_CDDC + * @{ + */ +#ifndef __ADI_APOLLO_CDDC_TYPES_H__ +#define __ADI_APOLLO_CDDC_TYPES_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_cms_api_common.h" +#include "adi_apollo_common.h" + +/*============= D E F I N E S ==============*/ +#define ADI_APOLLO_CDDC_NUM 8 +#define ADI_APOLLO_CDDC_PER_SIDE_NUM 4 + +/*! + * \brief Enumerates RX coarse DDC select + */ +typedef enum { + ADI_APOLLO_CDDC_NONE = 0x00, /*!< No COARSE DDC */ + ADI_APOLLO_CDDC_A0 = 0x01, /*!< COARSE DDC 0 of SIDE A */ + ADI_APOLLO_CDDC_A1 = 0x02, /*!< COARSE DDC 1 of SIDE A */ + ADI_APOLLO_CDDC_A2 = 0x04, /*!< COARSE DDC 2 of SIDE A */ + ADI_APOLLO_CDDC_A3 = 0x08, /*!< COARSE DDC 3 of SIDE A */ + ADI_APOLLO_CDDC_B0 = 0x10, /*!< COARSE DDC 0 of SIDE B */ + ADI_APOLLO_CDDC_B1 = 0x20, /*!< COARSE DDC 1 of SIDE B */ + ADI_APOLLO_CDDC_B2 = 0x40, /*!< COARSE DDC 2 of SIDE B */ + ADI_APOLLO_CDDC_B3 = 0x80, /*!< COARSE DDC 3 of SIDE B */ + ADI_APOLLO_CDDC_ALL = 0xFF, /*!< ALL COARSE DDCs */ + ADI_APOLLO_CDDC_ALL_4T4R = 0x33 /*!< ALL COARSE DDCs (4T4R) */ +} adi_apollo_cddc_select_e; + + +/*! + * \brief Enumerates the CDDC filter +6db gain block selection + */ +typedef enum { + ADI_APOLLO_CDDC_GAIN_NONE = 0x00, + ADI_APOLLO_CDDC_GAIN_HB1 = 0x01, /*!< CDDC HB1 filter gain block select */ + ADI_APOLLO_CDDC_GAIN_TB1 = 0x02, /*!< CDDC TB1 filter gain block select */ + ADI_APOLLO_CDDC_GAIN_ALL = 0x03 /*!< ALL CDDC gain blocks */ + +} adi_apollo_cddc_gain_select_e; + + +/*! + * \brief Rx coarse DDC configuration + */ +typedef struct { + adi_apollo_cddc_ratio_e dcm; /*!< \ref adi_apollo_cddc_ratio_e */ + uint8_t link_num; /*!< 0: Link0, 1: Link1 */ + uint8_t debug_clkoff_n; /*!< bit 0: filter input clock + bit 1: filter output clock + bit 2: hb1 clock + bit 3: hb2 clock + bit 4: reserved + bit 5: reserved + bit 6: tb1 clock */ + uint8_t fine_bypass; /*!< 0: Disable, 1: Enable */ + uint8_t hb1_filt_dly_en; /*!< HB1 filter delay enable */ + uint8_t hb2_filt_dly_en; /*!< HB2 filter delay enable */ + adi_apollo_tb1_filt_dly_cycles_e tb1_filt_dly; /*!< TB1 filter delay */ + uint8_t hb1_gain_6db_en; /*!< 6dB gain enabled for HB1 filter */ + uint8_t tb1_gain_6db_en; /*!< 6dB gain enabled for TB1 filter */ +} adi_apollo_cddc_pgm_t; + +/*! + * \brief CDDC inspect params + */ +typedef struct { + adi_apollo_cddc_cfg_t dp_cfg; /*!< Parameters defined from device profile \ref apollo_cpu_device_profile_types.h */ + + adi_apollo_cddc_select_e cddc; /*!< The CDDC single instance select enum (e.g. A0, B0, etc.) */ + +} adi_apollo_cddc_inspect_t; + +#endif /* __ADI_APOLLO_CDDC_TYPES_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_cduc.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_cduc.h new file mode 100644 index 00000000000000..2388eb34ceb694 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_cduc.h @@ -0,0 +1,108 @@ +/*! + * \brief Coarse DUC functional block API prototypes + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_CDUC + * @{ + */ +#ifndef __ADI_APOLLO_CDUC_H__ +#define __ADI_APOLLO_CDUC_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_cduc_types.h" + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * \brief Sets coarse DUC interpolation value + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] cducs Coarse DUC selection. ADI_APOLLO_CDUC_A0, _A0 to _A3, _B0 to _B3, _ALL \ref adi_apollo_cduc_select_e + * \param[in] interp Interpolation enum. ADI_APOLLO_CDUC_RATIO_1, _2, _3, _4, _6, _8, _12 \ref adi_apollo_cduc_ratio_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cduc_interp_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t cducs, uint8_t interp); + +/** + * \brief Sets coarse DUC interpolator block parameters + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] cducs Coarse DUC selection. \ref adi_apollo_cduc_select_e + * \param[in] config Pointer to coarse interpolation parameter struct. \ref adi_apollo_cduc_pgm_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cduc_pgm(adi_apollo_device_t *device, adi_apollo_blk_sel_t cducs, const adi_apollo_cduc_pgm_t *config); + +/** + * \brief Enable or disable regsiter control for setting a CDUC's active state + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] cducs Coarse DUC selection. \ref adi_apollo_cduc_select_e + * \param[in] cduc_spien_en Enables(1) or disables(0) register control of CDUC active state. Bypasses auto decode. (Typically disabled) + * \param[in] cduc_spi_en If cduc_spien_en is true, then a 1 will activate and 0 deactivate the selected DUCs + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cduc_enable_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t cducs, uint8_t cduc_spien_en, uint8_t cduc_spi_en); + +/** + * \brief Inspect CDUC parameters + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] cduc Single Target CDUC \ref adi_apollo_cduc_select_e + * \param[out] cduc_inspect Pointer to cduc inspect structure. \ref adi_apollo_cduc_inspect_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cduc_inspect(adi_apollo_device_t *device, adi_apollo_blk_sel_t cduc, adi_apollo_cduc_inspect_t *cduc_inspect); + +/** + * \brief Determine the numeric CDUC interpolation value from the associated enum. Enum vals are HW specific + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] bf_enum Enum that contains register bitfield value for decimation. + * \param[out] val Numeric value of decimation bf enum. + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cduc_interp_bf_to_val(adi_apollo_device_t* device, adi_apollo_cduc_ratio_e bf_enum, uint32_t* val); + +/** + * \brief Enables/disables coarse DUC IRQ generation + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] cducs Coarse DUC selection. ADI_APOLLO_CDUC_A0, _A0 to _A3, _B0 to _B3, _ALL \ref adi_apollo_cduc_select_e + * \param[in] enable Interpolation enum. 1 to enable, 0 to disable + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cduc_irq_enable_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t cducs, uint8_t enable); + +#ifndef CLIENT_IGNORE + +#endif /* CLIENT_IGNORE*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_CDUC_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_cduc_types.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_cduc_types.h new file mode 100644 index 00000000000000..96c85b0e77454e --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_cduc_types.h @@ -0,0 +1,77 @@ +/*! + * \brief Coarse DUC functional block definitions + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_CDUC + * @{ + */ +#ifndef __ADI_APOLLO_CDUC_TYPES_H__ +#define __ADI_APOLLO_CDUC_TYPES_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_cms_api_common.h" +#include "adi_apollo_common.h" + +/*============= D E F I N E S ==============*/ +#define ADI_APOLLO_CDUC_NUM 8 +#define ADI_APOLLO_CDUC_PER_SIDE_NUM 4 + +/*! + * \brief Enumerates TX coarse DUC select + */ +typedef enum { + ADI_APOLLO_CDUC_NONE = 0x00, /*!< No COARSE DUC */ + ADI_APOLLO_CDUC_A0 = 0x01, /*!< COARSE DUC 0 of SIDE A */ + ADI_APOLLO_CDUC_A1 = 0x02, /*!< COARSE DUC 1 of SIDE A */ + ADI_APOLLO_CDUC_A2 = 0x04, /*!< COARSE DUC 2 of SIDE A */ + ADI_APOLLO_CDUC_A3 = 0x08, /*!< COARSE DUC 3 of SIDE A */ + ADI_APOLLO_CDUC_B0 = 0x10, /*!< COARSE DUC 0 of SIDE B */ + ADI_APOLLO_CDUC_B1 = 0x20, /*!< COARSE DUC 1 of SIDE B */ + ADI_APOLLO_CDUC_B2 = 0x40, /*!< COARSE DUC 2 of SIDE B */ + ADI_APOLLO_CDUC_B3 = 0x80, /*!< COARSE DUC 3 of SIDE B */ + ADI_APOLLO_CDUC_ALL = 0xFF, /*!< All COARSE DUCs */ + ADI_APOLLO_CDUC_ALL_4T4R = 0x33 /*!< All COARSE DUCs (4T4R) */ +} adi_apollo_cduc_select_e; + +/*! + * \brief Tx coarse DUC configuration + */ +typedef struct { + uint8_t interp; /*!< Interpolation value */ + uint8_t chb1_int_time_dly; /*!< Coarse HB1 int time delay control */ + uint8_t chb2_int_time_dly; /*!< Coarse HB2 int time delay control */ + uint8_t chb3_int_time_dly; /*!< Coarse HB3 int time delay control */ + uint8_t ctb1_int_time_dly; /*!< Coarse TB1 int time delay control */ + uint8_t test_mux; /*!< Test signal mux */ + uint16_t cduc_irq_en; /*!< Coarse DUC irq enable */ + uint16_t cduc_irq_status; /*!< Coarse DUC irq status (write to clear status) */ + + uint8_t cduc_spien_en; /*!< Enables(1) or disables(0) SPI control of CDUC. Bypasses auto decode. (Typically disabled) */ + uint8_t cduc_spi_en; /*!< Enable(1) or disable(0) the duc if cduc_spien_en is enabled */ +} adi_apollo_cduc_pgm_t; + +/*! + * \brief CDUC inspect params + */ +typedef struct { + adi_apollo_cduc_cfg_t dp_cfg; /*!< Parameters defined from device profile \ref apollo_cpu_device_profile_types.h */ + uint8_t chb1_int_time_dly; /*!< Coarse HB1 int time delay control */ + uint8_t chb2_int_time_dly; /*!< Coarse HB2 int time delay control */ + uint8_t chb3_int_time_dly; /*!< Coarse HB3 int time delay control */ + uint8_t ctb1_int_time_dly; /*!< Coarse TB1 int time delay control */ + uint8_t test_mux; /*!< Test signal mux */ + uint16_t cduc_irq_en; /*!< Coarse DUC irq enable */ + uint16_t cduc_irq_status; /*!< Coarse DUC irq status (write to clear status) */ + + uint8_t cduc_spien_en; /*!< Enables(1) or disables(0) SPI control of CDUC. Bypasses auto decode. (Typically disabled) */ + uint8_t cduc_spi_en; /*!< Enable(1) or disable(0) the duc if cduc_spien_en is enabled */ +} adi_apollo_cduc_inspect_t; + +#endif /* __ADI_APOLLO_CDUC_TYPES_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_cfg.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_cfg.h new file mode 100644 index 00000000000000..fd4d5c3e5cdba0 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_cfg.h @@ -0,0 +1,327 @@ +/*! + * \brief Top level configuration definition headers + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_CFG + * @{ + */ +#ifndef __ADI_APOLLO_CFG_H__ +#define __ADI_APOLLO_CFG_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_cfg_types.h" + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Configures digital data paths from device profile + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] config Configuration parameters. \ref adi_apollo_top_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cfg_data_path(adi_apollo_device_t *device, adi_apollo_top_t *config); + +/** + * \brief Configures the initial cal configuration for ADCs + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] adcs ADC selection mask \ref adi_apollo_adc_select_e + * \param[in] init_cal_cfg Initial cal configuration \ref adi_apollo_init_cal_cfg_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cfg_adc_init_cal_cfg_set(adi_apollo_device_t *device, const uint16_t adcs, adi_apollo_init_cal_cfg_e init_cal_cfg); + +/** + * \brief Configures the initial cal configuration for DACs + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] dacs DAC selection mask \ref adi_apollo_dac_select_e + * \param[in] init_cal_cfg Initial cal configuration \ref adi_apollo_init_cal_cfg_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cfg_dac_init_cal_cfg_set(adi_apollo_device_t *device, const uint16_t dacs, adi_apollo_init_cal_cfg_e init_cal_cfg); + +/** + * \brief Configures the initial cal configuration for Rx SERDES (JRx) + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] serdes Serdes selection mask \ref adi_apollo_serdes_12pack_select_e + * \param[in] init_cal_cfg Initial cal configuration \ref adi_apollo_init_cal_cfg_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cfg_serdes_rx_init_cal_cfg_set(adi_apollo_device_t *device, const uint16_t serdes, adi_apollo_init_cal_cfg_e init_cal_cfg); + +/** + * \brief Configures the initial cal configuration for Tx SERDESs (JTx) + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] serdes Serdes selection mask \ref adi_apollo_serdes_12pack_select_e + * \param[in] init_cal_cfg Initial cal configuration \ref adi_apollo_init_cal_cfg_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cfg_serdes_tx_init_cal_cfg_set(adi_apollo_device_t *device, const uint16_t serdes, adi_apollo_init_cal_cfg_e init_cal_cfg); + +/** + * \brief Loads ADC calibration data + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] adcs ADC selection mask. Selected units will get same cal_data \ref adi_apollo_adc_select_e + * \param[in] mode ADC mode selection. Random(0) or Sequential(1). + * \param[in] cal_data Array of calibration raw data for one ADC + * \param[in] len Number of bytes in cal_data (may include crc) + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cfg_adc_cal_data_set(adi_apollo_device_t *device, const uint16_t adcs, uint8_t mode, uint8_t cal_data[], uint32_t len); + +/** + * \brief Loads DAC calibration data + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] dacs DAC selection mask. Selected units will get same cal_data \ref adi_apollo_dac_select_e + * \param[in] cal_data Array of calibration raw data for one DAC + * \param[in] len Number of bytes in cal_data (may include crc) + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cfg_dac_cal_data_set(adi_apollo_device_t *device, const uint16_t dacs, uint8_t cal_data[], uint32_t len); + +/** + * \brief Loads SERDES RX calibration data + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] serdes Serdes selection mask \ref adi_apollo_serdes_12pack_select_e + * \param[in] cal_data Array of calibration raw data for one SERDES pack + * \param[in] len Number of bytes in cal_data (may include crc) + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cfg_serdes_rx_cal_data_set(adi_apollo_device_t *device, const uint16_t serdes, uint8_t cal_data[], uint32_t len); + +/** + * \brief Loads SERDES TX calibration data + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] serdes Serdes selection mask \ref adi_apollo_serdes_12pack_select_e + * \param[in] cal_data Array of calibration raw data for one SERDES pack + * \param[in] len Number of bytes in cal_data (may include crc) + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cfg_serdes_tx_cal_data_set(adi_apollo_device_t *device, const uint16_t serdes, uint8_t cal_data[], uint32_t len); + +/** + * \brief Read the current ADC calibration data from device. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] adcs ADC selection mask. Only a single ADC may be selected. \ref adi_apollo_adc_select_e + * \param[in] mode ADC mode selection. Random(0) or Sequential(1). + * \param[out] cal_data Array to store calibration data. Memory is allocated by the caller. + * \param[in] len Number of bytes in cal_data (includes room for ending checksum.) + * The cal_data array length can be retrieved from \ref adi_apollo_cfg_adc_cal_data_len_get() + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cfg_adc_cal_data_get(adi_apollo_device_t* device, const uint16_t adcs, uint8_t mode, uint8_t cal_data[], uint32_t len); + +/** + * \brief Read the current DAC calibration data from device. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] dacs DAC selection mask. Only a single DAC may be selected. \ref adi_apollo_dac_select_e + * \param[out] cal_data Array to store calibration data. Memory is allocated by the caller. + * \param[in] len Number of bytes in cal_data (includes room for ending checksum.) + * The cal_data array length can be retrieved from \ref adi_apollo_cfg_dac_cal_data_len_get() + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cfg_dac_cal_data_get(adi_apollo_device_t* device, const uint16_t dacs, uint8_t cal_data[], uint32_t len); + +/** + * \brief Read the current SERDES Rx calibration data from device. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] serdes SERDES selection mask. Only a single SERDES may be selected. \ref adi_apollo_serdes_12pack_select_e + * \param[out] cal_data Array to store calibration data. Memory is allocated by the caller. + * \param[in] len Number of bytes in cal_data (includes room for ending checksum.) + * The cal_data array length can be retrieved from \ref adi_apollo_cfg_serdes_rx_cal_data_len_get() + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cfg_serdes_rx_cal_data_get(adi_apollo_device_t* device, const uint16_t serdes, uint8_t cal_data[], uint32_t len); + +/** + * \brief Read the current SERDES Tx calibration data from device. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] serdes SERDES selection mask. Only a single SERDES may be selected. \ref adi_apollo_serdes_12pack_select_e + * \param[out] cal_data Array to store calibration data. Memory is allocated by the caller. + * \param[in] len Number of bytes in cal_data (includes room for ending checksum.) + * The cal_data array length can be retrieved from \ref adi_apollo_cfg_serdes_tx_cal_data_len_get() + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cfg_serdes_tx_cal_data_get(adi_apollo_device_t* device, const uint16_t serdes, uint8_t cal_data[], uint32_t len); + +/** + * \brief Get size (in bytes) of ADC calibration data. Includes ending 32-bit checksum. + * All ADC instances have the same cal data length. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] mode ADC mode selection. Random(0) or Sequential(1). + * \param[out] len Number of bytes in cal_data (includes ending 32-bit checksum) + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cfg_adc_cal_data_len_get(adi_apollo_device_t* device, uint8_t mode, uint32_t* len); + +/** + * \brief Get size (in bytes) of DAC calibration data. Includes ending 32-bit checksum. + * All DAC instances have the same cal data length. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[out] len Number of bytes in cal_data (includes ending 32-bit checksum) + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cfg_dac_cal_data_len_get(adi_apollo_device_t* device, uint32_t* len); + +/** + * \brief Get size (in bytes) of SERDES Rx calibration data. Includes ending 32-bit checksum. + * All SERDES RX instances have the same cal data length. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[out] len Number of bytes in cal_data (includes ending 32-bit checksum) + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cfg_serdes_rx_cal_data_len_get(adi_apollo_device_t* device, uint32_t* len); + +/** + * \brief Get size (in bytes) of SERDES Tx calibration data. Includes ending 32-bit checksum. + * All SERDES Tx instances have the same cal data length. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[out] len Number of bytes in cal_data (includes ending 32-bit checksum) + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cfg_serdes_tx_cal_data_len_get(adi_apollo_device_t* device, uint32_t* len); + +/** + * \brief Get API profile type version + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[out] ver Pointer to struct to store the version info(major, minor and patch) \ref adi_apollo_profile_version_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cfg_profile_type_version_get(adi_apollo_device_t *device, adi_apollo_profile_version_t *ver); + +/** + * \brief Configures the number of time bridging cal run for Rx SERDES (JRx) after init cal + * \note Call this API after loading FW bins and before loading device profile onto Apollo. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] bridging_cal_runs Num times bridging cal runs after init cal. Default 3. Range 0 - 3. + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cfg_serdes_rx_bridging_cal_cfg_set(adi_apollo_device_t *device, uint8_t bridging_cal_runs); + +/** + * \brief Set the Clock Conditioning data to device. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] sides Apollo side selection mask. \ref adi_apollo_side_select_e + * \param[in] cal_data Array to load calibration data. Memory is allocated by the caller. + * \param[in] len Number of bytes in cal_data (includes room for ending checksum.) + * The cal_data array length can be retrieved from \ref adi_apollo_cfg_clk_cond_cal_data_len_get + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cfg_clk_cond_cal_data_set(adi_apollo_device_t *device, const uint16_t sides, uint8_t cal_data[], uint32_t len); + +/** + * \brief Read the current Clock Conditioning data from device. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] sides Apollo side selection mask. \ref adi_apollo_side_select_e + * \param[out] cal_data Array to store calibration data. Memory is allocated by the caller. + * \param[in] len Number of bytes in cal_data (includes room for ending checksum.) + * The cal_data array length can be retrieved from \ref adi_apollo_cfg_clk_cond_cal_data_len_get + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cfg_clk_cond_cal_data_get(adi_apollo_device_t* device, const uint16_t sides, uint8_t cal_data[], uint32_t len); + +/** + * \brief Get size (in bytes) of Clock Conditioning data. Includes ending 32-bit checksum. + * Both CC Side instances have the same cal data length. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[out] len Number of bytes in cal_data (includes ending 32-bit checksum) + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cfg_clk_cond_cal_data_len_get(adi_apollo_device_t* device, uint32_t* len); + +/** + * \brief Sets clock conditioning cal cfg. Must be done after firmware loading but before profile loading. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] cc_cal_cfg cal config. \ref adi_apollo_sysclock_cond_cfg_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cfg_clk_cond_cal_cfg_set(adi_apollo_device_t *device, adi_apollo_sysclock_cond_cfg_e cc_cal_cfg); + + +#ifndef CLIENT_IGNORE +#endif /* CLIENT_IGNORE*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_CFG_H__ */ +/*! @} */ + diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_cfg_types.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_cfg_types.h new file mode 100644 index 00000000000000..a3f196dc9ecffe --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_cfg_types.h @@ -0,0 +1,118 @@ +/*! + * \brief Top level configuration definition headers + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_CFG + * @{ + */ +#ifndef __ADI_APOLLO_CFG_TYPES_H__ +#define __ADI_APOLLO_CFG_TYPES_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_cms_api_common.h" +#include "adi_apollo_common.h" +#include "apollo_cpu_device_profile_types.h" + +/*============= D E F I N E S ==============*/ +/* Scratch registers for warmboot INT_CAL_CFG flags. Each module uses 4 bits. */ +#define ADI_APOLLO_WARMBOOT_CFG_BASE_ADDR 0x47000200 + +#define ADI_APOLLO_WARMBOOT_CFG_SERDES_RX_1_0 163 +#define ADI_APOLLO_WARMBOOT_CFG_SERDES_TX_1_0 164 + +#define ADI_APOLLO_WARMBOOT_CFG_ADC_A1_A0 165 +#define ADI_APOLLO_WARMBOOT_CFG_ADC_A3_A2 166 +#define ADI_APOLLO_WARMBOOT_CFG_ADC_B1_B0 167 +#define ADI_APOLLO_WARMBOOT_CFG_ADC_B3_B2 168 + +#define ADI_APOLLO_WARMBOOT_CFG_DAC_A1_A0 169 +#define ADI_APOLLO_WARMBOOT_CFG_DAC_A3_A2 170 +#define ADI_APOLLO_WARMBOOT_CFG_DAC_B1_B0 171 +#define ADI_APOLLO_WARMBOOT_CFG_DAC_B3_B2 172 + +#define ADI_APOLLO_WARMBOOT_CFG_LINEARX_RX_A1_A0 173 +#define ADI_APOLLO_WARMBOOT_CFG_LINEARX_RX_A3_A2 174 +#define ADI_APOLLO_WARMBOOT_CFG_LINEARX_RX_B1_B0 175 +#define ADI_APOLLO_WARMBOOT_CFG_LINEARX_RX_B3_B2 176 + +#define ADI_APOLLO_WARMBOOT_CFG_LINEARX_TX_A1_A0 177 +#define ADI_APOLLO_WARMBOOT_CFG_LINEARX_TX_A3_A2 178 +#define ADI_APOLLO_WARMBOOT_CFG_LINEARX_TX_B1_B0 179 +#define ADI_APOLLO_WARMBOOT_CFG_LINEARX_TX_B3_B2 180 + +#define ADI_APOLLO_WARMBOOT_CFG_SYSCLK_CONDITIONING 182 + +#define ADI_APOLLO_SERDES_RX_NUM_BRIDGING_CALS 196 + +#define ADI_APOLLO_DAC_CAL_OBJ_SIZE 24 +#define ADI_APOLLO_DAC_CAL_OBJ_OFFSET 20 +#define ADI_APOLLO_SERDES_RX_CAL_OBJ_SIZE 24 +#define ADI_APOLLO_SERDES_RX_CAL_OBJ_OFFSET 20 +#define ADI_APOLLO_SERDES_TX_CAL_OBJ_SIZE 24 +#define ADI_APOLLO_SERDES_TX_CAL_OBJ_OFFSET 20 + +#define ADI_APOLLO_ADC_CAL_STRUCT_SIZE 28 +#define ADI_APOLLO_ADC_CAL_STRUCT_RAND_DATA_OFFSET 20 +#define ADI_APOLLO_ADC_CAL_STRUCT_SEQ_DATA_OFFSET 24 + +#define ADI_APOLLO_ADC_CAL_RANDOM_MODE 00 +#define ADI_APOLLO_ADC_CAL_SEQUENTIAL_MODE 01 + +/* This register states if the TDC/firmware MCS is in progress and if the synch is achieved */ +#define ADI_APOLLO_MCS_OPERATION_AND_SYNCH_STATUS 181 + +/* Warm boot fw calibration object locations */ +#define ADI_APOLLO_CPU_1_FW_ADC_RX_OBJ_PTR (0x21000534U) /*!< ADC Rx object pointer */ +#define ADI_APOLLO_CPU_1_FW_ADC_RX_SIZE_PTR (0x21000538U) /*!< ADC Rx size pointer */ +#define ADI_APOLLO_CPU_1_FW_ADC_RX_VERSION_PTR (0x2100053CU) /*!< ADC Rx version pointer */ +#define ADI_APOLLO_CPU_1_FW_DAC_TX_OBJ_PTR (0x21000540U) /*!< DAC Tx object pointer */ +#define ADI_APOLLO_CPU_1_FW_DAC_TX_SIZE_PTR (0x21000544U) /*!< DAC Tx size pointer */ +#define ADI_APOLLO_CPU_1_FW_DAC_TX_VERSION_PTR (0x21000548U) /*!< DAC Tx version pointer */ +#define ADI_APOLLO_CPU_0_FW_SERDES_RX_OBJ_PTR (0x20000224U) /*!< Serdes Rx object pointer */ +#define ADI_APOLLO_CPU_0_FW_SERDES_RX_SIZE_PTR (0x20000228U) /*!< Serdes Rx size pointer */ +#define ADI_APOLLO_CPU_0_FW_SERDES_RX_VERSION_PTR (0x2000022CU) /*!< Serdes Rx version pointer */ +#define ADI_APOLLO_CPU_1_FW_SERDES_TX_OBJ_PTR (0x21000558U) /*!< Serdes Tx object pointer */ +#define ADI_APOLLO_CPU_1_FW_SERDES_TX_SIZE_PTR (0x2100055CU) /*!< Serdes Tx size pointer */ +#define ADI_APOLLO_CPU_1_FW_SERDES_TX_VERSION_PTR (0x21000560U) /*!< Serdes Tx version pointer */ + +/* Clock conditioning structure pointer locations */ +#define APOLLO_CPU_1_FW_CLK_COND_CONFIG_PTR (0x21000660U) /*!< ADC clock conditioning config ref pointer */ +#define APOLLO_CPU_1_FW_CLK_COND_0_CALDATA_PTR (0x21000664U) /*!< ADC clock conditioning side A cal ref pointer */ +#define APOLLO_CPU_1_FW_CLK_COND_1_CALDATA_PTR (0x21000668U) /*!< ADC clock conditioning side B cal ref pointer */ +#define APOLLO_CPU_1_FW_CLK_COND_BGCAL_CLIP_PTR (0x21000688U) /*!< Clock conditioning Bg calibration clip status pointer */ + +/* The cal data size is in bytes, included 32-bit checksum. Same length for all Clock Conditioning instances This value is fixed. 116 + 4 */ +#define ADI_APOLLO_CLK_COND_CAL_DATA_LEN_BYTES (120U) +/*! + * \brief Enumeration of initial calibration configurations + */ +typedef enum +{ + ADI_APOLLO_INIT_CAL_DISABLED = 0, /*!< No Init Calibration - start with default calibration data */ + ADI_APOLLO_INIT_CAL_DISABLED_WARMBOOT_FROM_NVM, /*!< No Init Calibration - start with calibration data from NVM */ + ADI_APOLLO_INIT_CAL_DISABLED_WARMBOOT_FROM_USER, /*!< No Init Calibration - start with calibration data from USER */ + ADI_APOLLO_INIT_CAL_ENABLED, /*!< Run Init Calibration - start with default calibration data */ + ADI_APOLLO_INIT_CAL_ENABLED_WARMBOOT_FROM_NVM, /*!< Run Init Calibration - start with calibration data from NVM */ + ADI_APOLLO_INIT_CAL_ENABLED_WARMBOOT_FROM_USER, /*!< Run Init Calibration - start with calibration data from USER */ +} adi_apollo_init_cal_cfg_e; + +/*! + * \brief Enumeration of Clock Conditioning Configurations + */ +typedef enum +{ + ADI_APOLLO_SYSCLKCONDITIONING_ENABLED = 0, /*!< Run clock conditioning calibration */ + ADI_APOLLO_SYSCLKCONDITIONING_DISABLED = 1, /*!< No clock conditioning calibration */ + ADI_APOLLO_SYSCLKCONDITIONING_ENABLED_WARMBOOT_FROM_USER = 2, /*!< Run clock conditioning calibration - start with cal data from user */ + ADI_APOLLO_SYSCLKCONDITIONING_DISABLED_WARMBOOT_FROM_USER = 3, /*!< No clock conditioning calibration - start with cal data from user */ +} adi_apollo_sysclock_cond_cfg_e; + +#endif /* __ADI_APOLLO_CFG_TYPES_H__ */ + +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_cfir.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_cfir.h new file mode 100644 index 00000000000000..c861be533955eb --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_cfir.h @@ -0,0 +1,199 @@ +/*! + * \brief CFIR Block definition headers + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_CFIR + * @{ + */ +#ifndef __ADI_APOLLO_CFIR_H__ +#define __ADI_APOLLO_CFIR_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_cfir_types.h" + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Configure CFIR parameters + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] cfirs Target CFIR \ref adi_apollo_cfir_sel_e + * \param[in] config \ref adi_apollo_cfir_pgm_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cfir_pgm(adi_apollo_device_t* device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t cfirs, adi_apollo_cfir_pgm_t *config); + + +/** + * \brief Load CFIR coefficients for one or more profiles + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] cfirs Target CFIR \ref adi_apollo_cfir_sel_e + * \param[in] cfir_profiles CFIR profiles bit-or selector \ref adi_apollo_cfir_profile_sel_e + * \param[in] cfir_dps CFIR data path bit-or selector \ref adi_apollo_cfir_dp_sel + * \param[in] cfir_coeff_i Array of 16-bit coefficients I channel + * \param[in] cfir_coeff_q Array of 16-bit coefficients Q channel + * \param[in] len Length of cfir_coeff_i and cfir_coeff_q arrays. Must be 16. + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cfir_coeff_pgm(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t cfirs, uint8_t cfir_profiles, uint8_t cfir_dps, int16_t cfir_coeff_i[], int16_t cfir_coeff_q[], uint32_t len); + +/** + * \brief Load CFIR complex scalar values for one or more profiles + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] cfirs Target CFIR \ref adi_apollo_cfir_sel_e + * \param[in] cfir_profiles CFIR profiles bit-or selector \ref adi_apollo_cfir_profile_sel_e + * \param[in] cfir_dps CFIR data path bit-or selector \ref adi_apollo_cfir_dp_sel + * \param[in] scalar_i Complex scalar for I stream (0x7fff default) + * \param[in] scalar_q Complex scalar for Q stream (0x0000 default) + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cfir_scalar_pgm(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t cfirs, uint8_t cfir_profiles, uint8_t cfir_dps, uint16_t scalar_i, uint16_t scalar_q); + +/** + * \brief Load CFIR gain adjustment values for one or more profiles + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] cfirs Target CFIR \ref adi_apollo_cfir_sel_e + * \param[in] cfir_profiles CFIR profiles bit-or selector \ref adi_apollo_cfir_profile_sel_e + * \param[in] cfir_dps CFIR data path bit-or selector \ref adi_apollo_cfir_dp_sel + * \param[in] gain Gain db adjustment \ref adi_apollo_cfir_gain_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cfir_gain_pgm(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t cfirs, uint8_t cfir_profiles, uint8_t cfir_dps, uint8_t gain); + +/** + * \brief Load CFIR sparse mode coefficient sel (hsel) for one or more profiles + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] cfirs Target CFIR \ref adi_apollo_cfir_sel_e + * \param[in] cfir_profiles CFIR profiles bit-or selector \ref adi_apollo_cfir_profile_sel_e + * \param[in] cfir_dps CFIR data path bit-or selector \ref adi_apollo_cfir_dp_sel + * \param[in] cfir_coeff_sel Array sparse mode coeff sel. Values range from 0..63 and depends on mem_sel setting + * \param[in] len Length of cfir_coeff_sel. Must be 16. + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cfir_sparse_coeff_sel_pgm(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t cfirs, uint8_t cfir_profiles, uint8_t cfir_dps, uint16_t cfir_coeff_sel[], uint32_t len); + +/** + * \brief Load CFIR sparse mode mem_sel values (mem_sel) for one or more profiles + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] cfirs Target CFIR \ref adi_apollo_cfir_sel_e + * \param[in] cfir_profiles CFIR profiles bit-or selector \ref adi_apollo_cfir_profile_sel_e + * \param[in] cfir_dps CFIR data path bit-or selector \ref adi_apollo_cfir_dp_sel + * \param[in] cfir_mem_sel Select which data store slices go into the data path mux. configurable per data path. (valid values 0..3) + * \param[in] len Length of cfir_coeff_sel. Must be 3. + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cfir_sparse_mem_sel_pgm(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t cfirs, uint8_t cfir_profiles, uint8_t cfir_dps, uint8_t cfir_mem_sel[], uint32_t len); + + +/** + * \brief Configure the CFIR for a specific profile + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] cfirs Target CFIR \ref adi_apollo_cfir_sel_e + * \param[in] cfir_dps CFIR data path bit-or selector \ref adi_apollo_cfir_dp_sel + * \param[in] coeff_profile_sel Profile to configure the CFIR \ref adi_apollo_cfir_profile_sel_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cfir_profile_sel(adi_apollo_device_t* device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t cfirs, uint8_t cfir_dps, uint8_t coeff_profile_sel); + +/** + * \brief Enable or bypass the CFIR + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] cfirs Target CFIR \ref adi_apollo_cfir_sel_e + * \param[in] mode Enable or bypass the CFIR. \ref adi_apollo_cfir_enable_sel_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cfir_mode_enable_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t cfirs, adi_apollo_cfir_enable_sel_e mode); + +/** + * \brief Inspect CFIR parameters + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] cfirs Target CFIR \ref adi_apollo_cfir_sel_e + * \param[out] cfir_inspect Pointer to cfilt inspect struct \ref adi_apollo_cfir_inspect_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cfir_inspect(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t cfirs, adi_apollo_cfir_inspect_t *cfir_inspect); + +/** + * \brief Set the CFIR profile selection and hopping mode + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] cfirs Target CFIR (ADI_APOLLO_CFIR_A0, A1, B0, B1) \ref adi_apollo_cfir_sel_e + * \param[in] prof_sel_mode Profile select mode. Can be direct spi, regmap and trig based. \ref adi_apollo_cfir_profile_sel_mode_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cfir_profile_sel_mode_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t cfirs, const adi_apollo_cfir_profile_sel_mode_e prof_sel_mode); + +/** + * \brief Set the next CFIR profile selection or hop + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] cfirs Target CFIR (ADI_APOLLO_CFIR_A0, A1, B0, B1) \ref adi_apollo_cfir_sel_e + * \param[in] cfir_dps CFIR data path bit-or selector (ADI_APOLLO_CFIR_DP_0, 1, 2, 3) \ref adi_apollo_cfir_dp_sel + * \param[in] hop_num Profile (e.g. coeff set) to hop to. Will be immediate if in direct regmap mode, or scheduled for next trigger. + * + * The behavior of the function is influenced by adi_apollo_cfir_profile_sel_mode_set(). + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cfir_next_hop_num_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t cfirs, uint8_t cfir_dps, int16_t hop_num); + +#ifndef CLIENT_IGNORE + +#endif /* CLIENT_IGNORE*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_CFIR_H__ */ +/*! @} */ + diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_cfir_types.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_cfir_types.h new file mode 100644 index 00000000000000..60091a6c93c0b5 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_cfir_types.h @@ -0,0 +1,109 @@ +/*! + * \brief CFIR Block definition headers + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_CFIR + * @{ + */ +#ifndef __ADI_APOLLO_CFIR_TYPES_H__ +#define __ADI_APOLLO_CFIR_TYPES_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_cms_api_common.h" +#include "adi_apollo_common.h" + +/*============= D E F I N E S ==============*/ +#define ADI_APOLLO_CFIR_NUM 4 +#define ADI_APOLLO_CFIR_PER_SIDE_NUM 2 +#define ADI_APOLLO_CFIR_DP_PER_INST_NUM 4 +#define ADI_APOLLO_CFIR_PROFILE_NUM 2 +#define ADI_APOLLO_CFIR_COEFF_NUM 16 +#define ADI_APOLLO_CFIR_MEM_SEL_NUM 3 +#define ADI_APOLLO_CFIR_NUM_PROFILES 2 +#define ADI_APOLLO_CFIR_COEFF_SETS 4 +#define ADI_APOLLO_CFIR_NUM_TAPS 16 + +/*! + * \brief Enumerates CFIR select + */ +typedef enum { + ADI_APOLLO_CFIR_NONE = 0x0000, /*!< No CFIR */ + ADI_APOLLO_CFIR_A0 = 0x0001, /*!< CFIR 0 of SIDE A */ + ADI_APOLLO_CFIR_A1 = 0x0002, /*!< CFIR 1 of SIDE A */ + ADI_APOLLO_CFIR_B0 = 0x0004, /*!< CFIR 0 of SIDE B */ + ADI_APOLLO_CFIR_B1 = 0x0008, /*!< CFIR 1 of SIDE B */ + ADI_APOLLO_CFIR_ALL = 0x000F, /*!< ALL CFIRs */ + ADI_APOLLO_CFIR_ALL_4T4R = 0x000F /*!< ALL CFIRs 4T4R (same as 8T8R)*/ +} adi_apollo_cfir_sel_e; + +/*! + * \brief Enumerates CFIR data path select for a CFIR instance + */ +typedef enum { + ADI_APOLLO_CFIR_DP_NONE = 0x0000, /*!< No CFIR data path select */ + ADI_APOLLO_CFIR_DP_0 = 0x0001, /*!< CFIR data path 0 */ + ADI_APOLLO_CFIR_DP_1 = 0x0002, /*!< CFIR data path 1 */ + ADI_APOLLO_CFIR_DP_2 = 0x0004, /*!< CFIR data path 2 (8t8r only) */ + ADI_APOLLO_CFIR_DP_3 = 0x0008, /*!< CFIR data path 3 (8t8r only) */ + ADI_APOLLO_CFIR_DP_ALL = 0x000F, /*!< ALL CFIR data paths */ + ADI_APOLLO_CFIR_DP_ALL_4T4R = 0x0003 /*!< ALL CFIR data paths */ +} adi_apollo_cfir_dp_sel; + +/*! +* \brief Enumerates CFIR PROFILE selection +*/ +typedef enum { + ADI_APOLLO_CFIR_PROFILE_NONE = 0x00, /*!< No filter profile */ + ADI_APOLLO_CFIR_PROFILE_0 = 0x01, /*!< 1st filter profile */ + ADI_APOLLO_CFIR_PROFILE_1 = 0x02, /*!< 2nd filter profile */ + ADI_APOLLO_CFIR_PROFILE_ALL = 0x03, /*!< All filter profile */ +} adi_apollo_cfir_profile_sel_e; + +/*! +* \brief Enumerates CFIR enable/bypass option +*/ +typedef enum { + ADI_APOLLO_CFIR_BYPASS = 0x00, /*!< Bypass the CFIR */ + ADI_APOLLO_CFIR_ENABLE = 0x01 /*!< Enable the CFIR */ +} adi_apollo_cfir_enable_sel_e; + +/*! +* \brief Enumerates CFIR profile selection mode +*/ +typedef enum +{ + ADI_APOLLO_CFIR_CHAN_SEL_DIRECT_REGMAP = 0, /*!< Direct spi/hsci CFIR hop select */ + ADI_APOLLO_CFIR_CHAN_SEL_DIRECT_GPIO = 1, /*!< Direct GPIO hop select switch between 2 coeff sets */ + ADI_APOLLO_CFIR_CHAN_SEL_TRIG_REGMAP = 2, /*!< Trigger based hopping. Scheduled regmap */ + ADI_APOLLO_CFIR_CHAN_SEL_TRIG_GPIO = 3, /*!< Trigger based hopping. Scheduled GPIO */ + ADI_APOLLO_CFIR_CHAN_SEL_NUM +} adi_apollo_cfir_profile_sel_mode_e; + +/*! +* \brief CFIR programming data +*/ +typedef struct { + uint8_t cfir_bypass; /*!< Bypass CFIR. 0: Disable, 1: Enable */ + uint8_t cfir_sparse_filt_en; /*!< Enable Sparse Filter. 0: Disable, 1: Enable */ + uint8_t cfir_32taps_en; /*!< Enable 32-taps filter 0: Disable, 1: Enable */ + uint8_t cfir_coeff_transfer; /*!< Coefficient Transfer Signal. Transfers all coefficient data from master registers to slave registers. 0: Disable, 1: Enable */ +} adi_apollo_cfir_pgm_t; + +/*! +* \brief CFIR inspect param +*/ +typedef struct { + adi_apollo_cfir_cfg_t dp_cfg; /*!< Parameters defined from device profile \ref apollo_cpu_device_profile_types.h */ + + uint8_t cfir_coeff_transfer; /*!< Coefficient Transfer Signal. Transfers all coefficient data from master registers to slave registers. 0: Disable, 1: Enable */ + uint16_t sparse_coeff[ADI_APOLLO_CFIR_NUM_PROFILES][ADI_APOLLO_CFIR_COEFF_SETS][ADI_APOLLO_CFIR_NUM_TAPS]; + uint8_t sparse_mem[ADI_APOLLO_CFIR_NUM_PROFILES][ADI_APOLLO_CFIR_COEFF_SETS][ADI_APOLLO_CFIR_MEM_SEL_NUM]; +} adi_apollo_cfir_inspect_t; +#endif /* __ADI_APOLLO_CFIR_TYPES_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_clk_mcs.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_clk_mcs.h new file mode 100644 index 00000000000000..e3eda4a485e715 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_clk_mcs.h @@ -0,0 +1,494 @@ +/*! + * \brief Clock and multi chip sync related API prototypes + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_CLK + * @{ + */ +#ifndef __ADI_APOLLO_CLK_MCS_H__ +#define __ADI_APOLLO_CLK_MCS_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_clk_mcs_types.h" + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Configures the ADC/RX data fifo + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] adcs ADC selection mask \ref adi_apollo_adc_select_e + * \param[in] fifo_config Fifo configuration \ref adi_apollo_data_fifo_config_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_clk_mcs_rx_data_fifo_configure(adi_apollo_device_t *device, const uint16_t adcs, adi_apollo_data_fifo_config_t *fifo_config); + +/** + * \brief Enables the ADC/RX data fifo + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] adcs ADC selection mask \ref adi_apollo_adc_select_e + * \param[in] enable Fifo enable 1 = enable, 0 = disable + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_clk_mcs_rx_data_fifo_enable(adi_apollo_device_t *device, const uint16_t adcs, uint8_t enable); + +/** + * \brief Writes the ADC/RX data fifo wr/rd fifo offsets + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] adcs ADC selection mask \ref adi_apollo_adc_select_e + * \param[in] wr_offset Write fifo offset + * \param[in] rd_offset Read fifo offset + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_clk_mcs_rx_data_fifo_offset_set(adi_apollo_device_t *device, const uint16_t adcs, uint8_t wr_offset, uint8_t rd_offset); + +/** + * \brief Configures ADC/RX data fifo mode + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] adcs ADC selection mask \ref adi_apollo_adc_select_e + * \param[in] mode Fifo mode Deterministic Latency mode typical. \ref adi_apollo_data_fifo_mode_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_clk_mcs_rx_data_fifo_mode_set(adi_apollo_device_t *device, const uint16_t adcs, adi_apollo_data_fifo_mode_e mode); + +/** + * \brief Configures the DAC/TX data fifo + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] dacs DAC selection mask \ref adi_apollo_dac_select_e + * \param[in] fifo_config Fifo configuration \ref adi_apollo_data_fifo_config_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_clk_mcs_tx_data_fifo_configure(adi_apollo_device_t *device, const uint16_t dacs, adi_apollo_data_fifo_config_t *fifo_config); + +/** + * \brief Enables the DAC/TX data fifo + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] dacs DAC selection mask \ref adi_apollo_dac_select_e + * \param[in] enable Fifo enable 1 = enable, 0 = disable + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_clk_mcs_tx_data_fifo_enable(adi_apollo_device_t *device, const uint16_t dacs, uint8_t enable); + +/** + * \brief Writes the DAC/TX data fifo wr/rd fifo offsets + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] dacs DAC selection mask \ref adi_apollo_dac_select_e + * \param[in] wr_offset Write fifo offset + * \param[in] rd_offset Read fifo offset + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_clk_mcs_tx_data_fifo_offset_set(adi_apollo_device_t *device, const uint16_t dacs, uint8_t wr_offset, uint8_t rd_offset); + +/** + * \brief Configures DAC/TX data fifo mode + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] dacs DAC selection mask \ref adi_apollo_dac_select_e + * \param[in] mode Fifo mode Deterministic Latency mode typical. \ref adi_apollo_data_fifo_mode_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_clk_mcs_tx_data_fifo_mode_set(adi_apollo_device_t *device, const uint16_t dacs, adi_apollo_data_fifo_mode_e mode); + +/** + * \brief Align internal to external sysref and issue system sync + * + * Performs internal to external SYSREF alignment using the HW based method. + * This is followed by a system sync of all digital blocks except for JTx and JRx. Omiting + * JRx and JTx sync here prevents the JESD links from dropping. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_clk_mcs_sync_hw_align_set(adi_apollo_device_t *device); + +/** + * \brief Check if oneshot sync is complete. + * + * \note Called in response to \ref adi_apollo_clk_mcs_sync_hw_align_set + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[out] status Sync complete if bit = 1. For single clock, b0 = center status. For dual clock, b0 = A side, b1 = B side. + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_clk_mcs_sync_hw_align_get(adi_apollo_device_t *device, uint8_t *status); + +/** + * \brief Issue system sync w/o internal sysref alignment + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_clk_mcs_sync_only_set(adi_apollo_device_t *device); + +/** + * \brief Check if sync only is complete. + * + * \note Called in response to \ref adi_apollo_clk_mcs_sync_only_set + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[out] status Sync complete if bit = 1. For single clock, b0 = center status. For dual clock, b0 = A side, b1 = B side. + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_clk_mcs_sync_only_get(adi_apollo_device_t *device, uint8_t *status); + +/** + * \brief Enable or disable the use of triggers for internal clock resets or digital configurations + * + * \note When using trigger to reset datapath clocks or issue dynamic reconfiguration + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] enable 1 to enable, 0 to disable + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_clk_mcs_trig_sync_enable(adi_apollo_device_t *device, uint8_t enable); + +/** + * \brief Get trigger active state for internal clock resets / dynamic reconfig + * + * \note When using trigger to reset datapath clocks or issue dynamic reconfiguration + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[out] enable 1 to enable, 0 to disable + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_clk_mcs_trig_sync_enable_get(adi_apollo_device_t *device, uint8_t *enable); + +/** + * \brief Enable the resets for Rx/Tx datapath clocks when trigger occurs + * + * \note After using any trigger based reset, run this function to clear any enables set for trigger. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_clk_mcs_trig_reset_dsp_enable(adi_apollo_device_t *device); + +/** + * \brief Disable the resets for all clocks by trigger + * + * \note After using any trigger based reset, run this function to clear any enables set for trigger. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_clk_mcs_trig_reset_disable(adi_apollo_device_t *device); + +/** + * \brief Read back the phase value of input trigger wrt the internal SYSREF. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] trig Index of trigger (ADI_APOLLO_TRIG_PIN_A0, _A1, _B0, _B1) \ref adi_apollo_trig_pin_e + * \param[out] phase_0 A side phase val for dual clock mode, else center phase val + * \param[out] phase_1 B side phase val for dual clock, else 0 for single + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_clk_mcs_trig_phase_get(adi_apollo_device_t *device, adi_apollo_trig_pin_e trig, uint16_t *phase_0, uint16_t *phase_1); + +/** + * \brief Datapath trigger reset masks. + * + * \note For example, to reset only RxA and TxB from a trigger, set rxtx_mask = ADI_APOLLO_SYNC_MASK_RX_DIG_A | ADI_APOLLO_SYNC_MASK_TX_DIG_B + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] rxtx_mask Reset disable mask for datapaths. A selected path will ignore reset trigger. \ref adi_apollo_sync_mask_rxtx_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_clk_mcs_dig_path_reset_mask_set(adi_apollo_device_t *device, adi_apollo_sync_mask_rxtx_e rxtx_mask); + +/** + * \brief Disable all data path resets based on a trigger + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_clk_mcs_dig_path_reset_disable(adi_apollo_device_t *device); + +/** + * \brief Disable all JTx/JRx link resets based on a trigger + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_clk_mcs_rxtx_link_reset_disable(adi_apollo_device_t *device); + +/** + * \brief Disable all data path link resets based on a trigger + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_clk_mcs_lpbk_fifo_reset_disable(adi_apollo_device_t *device); + +/** + * \brief Oneshot sync. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_clk_mcs_oneshot_sync(adi_apollo_device_t *device); + +/** + * \brief Dynamic sync. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_clk_mcs_dynamic_sync(adi_apollo_device_t *device); + +/** + * \brief Manual reconfiguration sync. + * + * Sync modes Key behaviors + * ---------- ------------- + * oneshot_sync HW state machine controlled sync flow, with HW based sysref alignment operation. + * dyn_cfg_sync Programmable HW state machine controlled sync flow only (no sysref alignment). + * manual_sync SPI controlled single step sync. + * trigger_sync Trigger controlled/selected single step or continuous sync. + + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_clk_mcs_man_reconfig_sync(adi_apollo_device_t *device); + +/** + * \brief Run default Dynamic Sync Sequence + * + * This sync sequence will minimize supply transients during device synchronization + * - Sync: digital root clocks + * + * - Call: adi_apollo_clk_mcs_dyn_sync_rxtxlinks_sequence_run() to sync + * ADC & DAC fifos, Rx & Tx digital, Loopback fifos and JTx & JRx + * + * On Enter: all sync masks are expected to be cleared + * On Exit: all sync masks are clear + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_clk_mcs_dyn_sync_sequence_run(adi_apollo_device_t *device); + +/** + * \brief Run JTx and JRx SerDes Link Dynamic Sync Sequence with digital root clks masked + * + * This sync sequence will minimize supply transients during JESD link synchronization. + * - Sync: ADC & DAC fifos, Rx & Tx digital, Loopback fifos, JTx-A0, JTx-A1 (not dig root clks) + * - Sync: JTx-B0, JTx-B1 + * - Sync: JRx-A0, JRx-A1 + * - SYnc: JRx-B0, JRx-B1 + * + * On Enter: all sync masks are expected to be cleared + * On Exit: all sync masks are clear + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_clk_mcs_dyn_sync_rxtxlinks_sequence_run(adi_apollo_device_t *device); + +/** + * \brief Set the SYSREF receiver enable + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] enable MCS SYSREF receiver enable. ADI_APOLLO_ENABLE or ADI_APOLLO_DISABLE + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_clk_mcs_sysref_en_set(adi_apollo_device_t *device, uint8_t enable); + +/** + * \brief Get the MCS SYSREF receiver enable state + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[out] enable Pointer to sysref receiver enable result + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_clk_mcs_sysref_en_get(adi_apollo_device_t* device, uint8_t* enable); + +/** + * \brief Get the MCS internal sysref period + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[out] sysref_per Pointer to sysref period result + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_clk_mcs_internal_sysref_per_get(adi_apollo_device_t *device, uint16_t *sysref_per); + +/** + * \brief Set the MCS subclass + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] subclass The JESD subclass. 0 = subclass 0, 1 = subclass 1. + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_clk_mcs_subclass_set(adi_apollo_device_t *device, uint32_t subclass); + +/** + * \brief Get the MCS subclass + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[out] subclass Pointer to subclass result + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_clk_mcs_subclass_get(adi_apollo_device_t *device, uint32_t *subclass); + +/** + * \brief Get the external to internal SYSREF phase difference + * + * This API returns a measurement of the external to internal phase difference. After + * a synchronization (e.g. adi_apollo_clk_mcs_oneshot_sync()) the result should be 0. + * Result is units of Fclk. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[out] sysref_phase Pointer to ext-to-int SYSREF phase delta in units or FClk. + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_clk_mcs_sysref_phase_get(adi_apollo_device_t *device, uint32_t *sysref_phase); + +/** + * \brief Number of SYSREFs to ignore before using one as a proper phase sampling instant + * + * Assuming that the first several sysrefs arriving at the device will be noisy or invalid in time. + * Ask the device to wait a predetermined number of pulses before using one to use as a + * proper phase sample of the internal counter. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] sysref_count Number of sysrefs to ignore (range 0-255) + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_clk_mcs_sysref_count_set(adi_apollo_device_t* device, uint32_t sysref_count); + +/** + * \brief Set the SYSREF internal termination resistor enable. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure. + * \param[in] enable MCS SYSREF internal termination resistor enable. + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_clk_mcs_sysref_internal_term_en_set(adi_apollo_device_t *device, uint8_t enable); + +/** + * \brief Maps a trigger pin to Rx and Tx digital + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure. + * \param[in] rx_tx_select Rx and Tx digital selection mask to map. \ref adi_apollo_rx_tx_dig_select_e + * \param[in] trig_pin The trigger pin to map to the selected digital blocks + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_clk_mcs_sync_trig_map(adi_apollo_device_t *device, uint16_t rx_tx_select, adi_apollo_trig_pin_e trig_pin); + +/** + * \brief Get the status of the clock input power detector + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure. + * \param[out] status_a Clock input power detector status for center clock (single mode) or side A (dual mode) + * \param[out] status_b Clock input power detector status unused (single mode) or side B (dual mode) + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_clk_mcs_input_power_status_get(adi_apollo_device_t *device, adi_apollo_clk_input_power_status_e *status_a, adi_apollo_clk_input_power_status_e *status_b); + +/** + * \brief Set the digital clock reset mask + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure. + * \param[in] enable 1 to mask digital clocks from trigger based resets, 0 to unmask + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_clk_mcs_dig_clk_mask_set(adi_apollo_device_t *device, uint8_t enable); + +#ifndef CLIENT_IGNORE +#endif /* CLIENT_IGNORE*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_CLK_MCS_H__ */ +/*! @} */ + diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_clk_mcs_types.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_clk_mcs_types.h new file mode 100644 index 00000000000000..a89d85dbc20999 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_clk_mcs_types.h @@ -0,0 +1,175 @@ +/*! + * \brief Clock and multi chip sync definitions header + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_CLK_MCS + * @{ + */ +#ifndef __ADI_APOLLO_CLK_MCS_TYPES_H__ +#define __ADI_APOLLO_CLK_MCS_TYPES_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_cms_api_common.h" +#include "adi_apollo_common.h" +#include "apollo_cpu_device_profile_types.h" + +/*============= D E F I N E S ==============*/ +#define ADI_APOLLO_PLL_REF_CLK_FREQ_KHZ_MAX 1000000 + +/*! + * \brief Data converter fifo Rx:Tx clock ratio + */ +typedef enum { + ADI_APOLLO_DATA_FIFO_CLK_RATIO_1_TO_1 = 0, /*!< CLock ration RX:TX = 1:1 */ + ADI_APOLLO_DATA_FIFO_CLK_RATIO_1_TO_2 = 1, /*!< CLock ration RX:TX = 1:2 */ + ADI_APOLLO_DATA_FIFO_CLK_RATIO_1_TO_4 = 2, /*!< CLock ration RX:TX = 1:4 */ +} adi_apollo_data_fifo_conv_clk_ratio_e; + +/*! + * \brief Data converter fifo mode + */ +typedef enum { + ADI_APOLLO_DATA_FIFO_MODE_NON_DL = 0x00, /*!< Debug mode - w/o deterministic latency */ + ADI_APOLLO_DATA_FIFO_MODE_DL = 0x01, /*!< Normal mode w/ deterministic latency */ + ADI_APOLLO_DATA_FIFO_MODE_FORCE_ON = 0x02, /*!< Debug mode - force on */ +} adi_apollo_data_fifo_mode_e; + +/*! + * \brief Rx and Tx dig sync mask select + */ +typedef enum { + ADI_APOLLO_SYNC_MASK_RX_TX_NONE = 0x00, /*!< Select none */ + ADI_APOLLO_SYNC_MASK_RX_DIG_A = 0x01, /*!< Rx dig A */ + ADI_APOLLO_SYNC_MASK_RX_DIG_B = 0x02, /*!< Rx dig B */ + ADI_APOLLO_SYNC_MASK_TX_DIG_A = 0x04, /*!< Tx dig A */ + ADI_APOLLO_SYNC_MASK_TX_DIG_B = 0x08, /*!< Tx dig B */ + ADI_APOLLO_SYNC_MASK_RX_TX_ALL = 0x0F, /*!< Select all */ +} adi_apollo_sync_mask_rxtx_e; + +/*! + * \brief JRx and JTx link sync mask select + */ +typedef enum { + ADI_APOLLO_SYNC_MASK_RXTX_LINK_NONE = 0x00, /*!< Select none */ + ADI_APOLLO_SYNC_MASK_JTX_A_LINK0 = 0x01, /*!< JTx A Link 0 */ + ADI_APOLLO_SYNC_MASK_JTX_A_LINK1 = 0x02, /*!< JTx A Link 1 */ + ADI_APOLLO_SYNC_MASK_JTX_B_LINK0 = 0x04, /*!< JTx B Link 0 */ + ADI_APOLLO_SYNC_MASK_JTX_B_LINK1 = 0x08, /*!< JTx B Link 1 */ + ADI_APOLLO_SYNC_MASK_JRX_A_LINK0 = 0x10, /*!< JRx A Link 0 */ + ADI_APOLLO_SYNC_MASK_JRX_A_LINK1 = 0x20, /*!< JRx A Link 1 */ + ADI_APOLLO_SYNC_MASK_JRX_B_LINK0 = 0x40, /*!< JRx B Link 0 */ + ADI_APOLLO_SYNC_MASK_JRX_B_LINK1 = 0x80, /*!< JRx B Link 1 */ + ADI_APOLLO_SYNC_MASK_RXTX_LINK_ALL = 0xFF, /*!< Select all */ +} adi_apollo_sync_mask_rxtx_link_e; + +/*! + * \brief Loopback FIFO sync mask select + */ +typedef enum { + ADI_APOLLO_SYNC_MASK_LPBKFIFO_NONE = 0x0, /*!< Select none */ + ADI_APOLLO_SYNC_MASK_LPBKFIFO_A = 0x1, /*!< Loopback FIFO A */ + ADI_APOLLO_SYNC_MASK_LPBKFIFO_B = 0x2, /*!< Loopback FIFO B */ + ADI_APOLLO_SYNC_MASK_LPBKFIFO_ALL = 0x3, /*!< Select all */ +} adi_apollo_sync_mask_lpbkfifo_e; + +/*! + * \brief Root clock sync mask select + */ +typedef enum { + ADI_APOLLO_SYNC_MASK_RTCLK_NONE = 0x00, /*!< Select none */ + ADI_APOLLO_SYNC_MASK_RTCLK_RX_DIG_A = 0x01, /*!< Rx A dig root clk */ + ADI_APOLLO_SYNC_MASK_RTCLK_RX_CONV_A = 0x02, /*!< Rx A conv root clk */ + ADI_APOLLO_SYNC_MASK_RTCLK_RX_DIG_B = 0x04, /*!< Rx B dig root clk */ + ADI_APOLLO_SYNC_MASK_RTCLK_RX_CONV_B = 0x08, /*!< Rx B conv root clk */ + ADI_APOLLO_SYNC_MASK_RTCLK_TX_DIG_A = 0x10, /*!< Tx A dig root clk */ + ADI_APOLLO_SYNC_MASK_RTCLK_TX_CONV_A = 0x20, /*!< Tx A conv root clk */ + ADI_APOLLO_SYNC_MASK_RTCLK_TX_DIG_B = 0x40, /*!< Tx B dig root clk */ + ADI_APOLLO_SYNC_MASK_RTCLK_TX_CONV_B = 0x80, /*!< Tx B conv root clk */ + ADI_APOLLO_SYNC_MASK_RTCLK_DIG_ALL = 0x55, /*!< Select all Rx/Tx dig */ + ADI_APOLLO_SYNC_MASK_RTCLK_CONV_ALL = 0xAA, /*!< Select all Rx/Tx conv */ + ADI_APOLLO_SYNC_MASK_RTCLK_ALL = 0xFF /*!< Select all */ +} adi_apollo_sync_mask_rtclk_e; + +/*! + * \brief ADC FIFO sync mask select + */ +typedef enum { + ADI_APOLLO_SYNC_MASK_ADCFIFO_NONE = 0x00, /*!< Select none */ + ADI_APOLLO_SYNC_MASK_ADCFIFO_A0 = 0x01, /*!< ADC FIFO A0 */ + ADI_APOLLO_SYNC_MASK_ADCFIFO_A1 = 0x02, /*!< ADC FIFO A1 */ + ADI_APOLLO_SYNC_MASK_ADCFIFO_B0 = 0x04, /*!< ADC FIFO B0 */ + ADI_APOLLO_SYNC_MASK_ADCFIFO_B1 = 0x08, /*!< ADC FIFO B1 */ + ADI_APOLLO_SYNC_MASK_ADCFIFO_ALL = 0x0F, /*!< Select all */ +} adi_apollo_sync_mask_adcfifo_e; + +/*! + * \brief DAC FIFO sync mask select + */ +typedef enum { + ADI_APOLLO_SYNC_MASK_DACFIFO_NONE = 0x00, /*!< Select none */ + ADI_APOLLO_SYNC_MASK_DACFIFO_A0 = 0x01, /*!< DAC FIFO A0 */ + ADI_APOLLO_SYNC_MASK_DACFIFO_A1 = 0x02, /*!< DAC FIFO A1 */ + ADI_APOLLO_SYNC_MASK_DACFIFO_A2 = 0x04, /*!< DAC FIFO A2 */ + ADI_APOLLO_SYNC_MASK_DACFIFO_A3 = 0x08, /*!< DAC FIFO A3 */ + ADI_APOLLO_SYNC_MASK_DACFIFO_B0 = 0x10, /*!< DAC FIFO B0 */ + ADI_APOLLO_SYNC_MASK_DACFIFO_B1 = 0x20, /*!< DAC FIFO B1 */ + ADI_APOLLO_SYNC_MASK_DACFIFO_B2 = 0x40, /*!< DAC FIFO B2 */ + ADI_APOLLO_SYNC_MASK_DACFIFO_B3 = 0x80, /*!< DAC FIFO B3 */ + ADI_APOLLO_SYNC_MASK_DACFIFO_ALL = 0xFF, /*!< Select all */ +} adi_apollo_sync_mask_dacfifo_e; + + +/*! + * \brief Rx and Tx dig select + */ +typedef enum { + ADI_APOLLO_RX_TX_NONE = 0x00, /*!< Select none */ + ADI_APOLLO_RX_DIG_A = 0x01, /*!< Rx dig A */ + ADI_APOLLO_RX_DIG_B = 0x02, /*!< Rx dig B */ + ADI_APOLLO_TX_DIG_A = 0x04, /*!< Tx dig A */ + ADI_APOLLO_TX_DIG_B = 0x08, /*!< Tx dig B */ + ADI_APOLLO_RX_TX_ALL = 0x0F, /*!< Select all Rx and Tx */ +} adi_apollo_rx_tx_dig_select_e; + +/*! + * \brief MCS trigger pin selection + */ +typedef enum { + ADI_APOLLO_TRIG_PIN_A0 = 0, /*!< MCS trigger Pin A0 */ + ADI_APOLLO_TRIG_PIN_A1 = 1, /*!< MCS trigger Pin A1 */ + ADI_APOLLO_TRIG_PIN_B0 = 2, /*!< MCS trigger Pin B0 */ + ADI_APOLLO_TRIG_PIN_B1 = 3, /*!< MCS trigger Pin B1 */ + ADI_APOLLO_TRIG_PIN_NUM = 4 /*!< Number of trigger pins */ +} adi_apollo_trig_pin_e; + +/*! + * \brief Clock input power detection status + */ +typedef enum { + ADI_APOLLO_CLK_PWR_GOOD = 0, /*!< Clock input power is good */ + ADI_APOLLO_CLK_PWR_UNDERDRIVEN, /*!< Clock input power is underdriven */ + ADI_APOLLO_CLK_PWR_OVERDRIVEN, /*!< Clock input power is overdriven */ + ADI_APOLLO_CLK_PWR_UNUSED, /*!< No reading for clock input power */ +} adi_apollo_clk_input_power_status_e; + +/*! + * \brief Converter data fifo configuration. + */ +typedef struct adi_apollo_data_fifo_config { + uint8_t enable; /*!< Data fifo enable enable */ + adi_apollo_data_fifo_mode_e mode; /*!< Fifo mode. \ref adi_apollo_data_fifo_mode_e */ + adi_apollo_data_fifo_conv_clk_ratio_e conv_clk_ratio; /*!< Rx:Tx converter clock ratio */ + uint8_t lat_override; /*!< If 1, programs lat_rd_offset and lat_wr_offset vals, else use defaults */ + uint8_t lat_rd_offset; /*!< Latency read offset value, if lat_override is 1 */ + uint8_t lat_wr_offset; /*!< Latency write offset, if lat_override is 1 */ +} adi_apollo_data_fifo_config_t; + +#endif /* __ADI_APOLLO_CLK_MCS_TYPES_H__ */ + +/*! @} */ \ No newline at end of file diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_cnco.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_cnco.h new file mode 100644 index 00000000000000..a87bc6069f7213 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_cnco.h @@ -0,0 +1,239 @@ +/*! + * \brief Coarse NCO functional block API prototypes + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_CNCO + * @{ + */ +#ifndef __ADI_APOLLO_CNCO_H__ +#define __ADI_APOLLO_CNCO_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_cnco_types.h" + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Load coarse nco phase increment profiles + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] cncos Target CNCOs \ref adi_apollo_coarse_nco_select_e + * \param[in] word_sel Select the phase incr or offset \ref adi_apollo_nco_profile_word_sel_e + * \param[in] first Profile number to load (0 - 15) + * \param[in] words Array of phase increment or offset words (32-bit) + * \param[in] length Number of profiles to load. (first + length must be < 16) + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cnco_profile_load(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t cncos, + adi_apollo_nco_profile_word_sel_e word_sel, uint8_t first, uint32_t words[], uint32_t length); + +/** + * \brief COARSE NCO HOP Enable + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] cncos Target CNCOs \ref adi_apollo_coarse_nco_select_e + * \param[in] config \ref adi_apollo_coarse_nco_hop_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cnco_hop_enable(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t cncos, adi_apollo_coarse_nco_hop_t *config); + +/** + * \brief Configure Coarse NCO channel parameters + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] cncos Target CNCOs \ref adi_apollo_coarse_nco_select_e + * \param[in] profile_num Profile to update + * \param[in] config NCO channel config \ref adi_apollo_coarse_nco_chan_pgm_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cnco_chan_pgm(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t cncos, uint8_t profile_num, adi_apollo_coarse_nco_chan_pgm_t *config); + +/** + * \brief Configure Coarse NCO parameters + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] cncos Target CNCOs \ref adi_apollo_coarse_nco_select_e + * \param[in] config \ref adi_apollo_cnco_pgm_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cnco_pgm(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t cncos, adi_apollo_cnco_pgm_t *config); + +/** + * \brief Inspect Coarse NCO parameters + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] cnco Single Target CNCOs \ref adi_apollo_coarse_nco_select_e + * \param[out] cnco_inspect Pointer to cnco inspect structure. \ref adi_apollo_cnco_inspect_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cnco_inspect(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t cnco, adi_apollo_cnco_inspect_t *cnco_inspect); + +/** + * \brief Enables coarse NCO instances + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] cncos Target CNCOs \ref adi_apollo_coarse_nco_select_e + * \param[in] enable 1 to enable the NCO + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cnco_enable_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t cncos, uint8_t enable); + +/** + * \brief Sets the coarse NCO mode for variable IF, ZIF, Fs/4 or test mode + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] cncos Target CNCOs \ref adi_apollo_coarse_nco_select_e + * \param[in] mode Select variable IF, zero IF, Fs/4 or test NCO mode. \ref adi_apollo_nco_mixer_mode_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cnco_mode_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t cncos, adi_apollo_nco_mixer_mode_e mode); + +/** + * \brief Sets the coarse NCO test mode input value + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] cncos Target CNCOs \ref adi_apollo_coarse_nco_select_e + * \param[in] val Mixer DC Test mode input value \ref adi_apollo_cnco_mxr_test_sel_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cnco_test_mode_val_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t cncos, uint16_t val); + +/** + * \brief Sets coarse NCO hop freq tuning word (phase increment) + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] cncos Target CNCOs \ref adi_apollo_coarse_nco_select_e + * \param[in] profile_num The index in profile table to update + * \param[in] active_en If true, will also set profile_num as the active profile. If in direct spi/hsci mode, output will be immdediate. + * \param[in] ftw Frequency tuning word value + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cnco_ftw_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t cncos, uint8_t profile_num, uint8_t active_en, uint32_t ftw); + +/** + * \brief Sets coarse phase hop offset word (phase offset) + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] cncos Target CNCOs \ref adi_apollo_coarse_nco_select_e + * \param[in] profile_num The index in profile table to update + * \param[in] active_en If true, will also set profile_num as the active profile. If in direct spi/hsci mode, output will be immdediate. + * \param[in] pow Phase offset word + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cnco_pow_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t cncos, uint8_t profile_num, uint8_t active_en, uint32_t pow); + +/** + * \brief Sets coarse NCO hop modulus params + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] cncos Target CNCOs \ref adi_apollo_coarse_nco_select_e + * \param[in] frac_a Numerator of modulus ratio + * \param[in] frac_b Denominator of modulus ratio + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cnco_mod_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t cncos, uint32_t frac_a, uint32_t frac_b); + +/** + * \brief Sets the coarse NCO mixer for real or complex + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] cncos Target CNCOs \ref adi_apollo_coarse_nco_select_e + * \param[in] mixer Select real or complex mixer mode. \ref adi_apollo_drc_mixer_sel_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cnco_mixer_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t cncos, adi_apollo_drc_mixer_sel_e mixer); + +/** + * \brief Sets the profile selection mode + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] cncos Target CNCOs \ref adi_apollo_coarse_nco_select_e + * \param[in] profile_sel_mode Profile selection mode (e.g. direct reg) \ref adi_apollo_nco_profile_sel_mode_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cnco_profile_sel_mode_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t cncos, adi_apollo_nco_profile_sel_mode_e profile_sel_mode); + +/** + * \brief Sets the active profile when profile select mode is direct register + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] cncos Target CNCOs \ref adi_apollo_coarse_nco_select_e + * \param[in] profile_num Profile for NCO + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cnco_active_profile_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t cncos, uint8_t profile_num); + +/** + * \brief Sets the coarse NCO next hop number for trigger based hopping + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] cncos Target CNCOs \ref adi_apollo_coarse_nco_select_e + * \param[in] hop_num The profile number to hop to on next trigger + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_cnco_next_hop_num_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t cncos, int16_t hop_num); + +#ifndef CLIENT_IGNORE + +#endif /* CLIENT_IGNORE*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_CNCO_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_cnco_types.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_cnco_types.h new file mode 100644 index 00000000000000..3c082a03a22160 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_cnco_types.h @@ -0,0 +1,148 @@ +/*! + * \brief Coarse NCO functional block definitions + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_CNCO + * @{ + */ +#ifndef __ADI_APOLLO_CNCO_TYPES_H__ +#define __ADI_APOLLO_CNCO_TYPES_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_cms_api_common.h" +#include "adi_apollo_common.h" + +/*============= D E F I N E S ==============*/ +#define ADI_APOLLO_CNCO_NUM 8 /* Sized for 8T8R */ +#define ADI_APOLLO_CNCO_PER_SIDE_NUM 4 + +/*! + * \brief Enumerates RX coarse NCO select + */ +typedef enum +{ + ADI_APOLLO_CNCO_NONE = 0x00, /*!< No COARSE NCO */ + ADI_APOLLO_CNCO_A0 = 0x01, /*!< COARSE NCO 0 of SIDE A */ + ADI_APOLLO_CNCO_A1 = 0x02, /*!< COARSE NCO 1 of SIDE A */ + ADI_APOLLO_CNCO_A2 = 0x04, /*!< COARSE NCO 2 of SIDE A */ + ADI_APOLLO_CNCO_A3 = 0x08, /*!< COARSE NCO 3 of SIDE A */ + ADI_APOLLO_CNCO_B0 = 0x10, /*!< COARSE NCO 0 of SIDE B */ + ADI_APOLLO_CNCO_B1 = 0x20, /*!< COARSE NCO 1 of SIDE B */ + ADI_APOLLO_CNCO_B2 = 0x40, /*!< COARSE NCO 2 of SIDE B */ + ADI_APOLLO_CNCO_B3 = 0x80, /*!< COARSE NCO 3 of SIDE B */ + ADI_APOLLO_CNCO_ALL = 0xFF, /*!< ALL COARSE NCOs (8T8R) */ + ADI_APOLLO_CNCO_ALL_4T4R = 0x33 /*!< ALL COARSE NCOs (4T4R) */ +} adi_apollo_coarse_nco_select_e; + +/*! +* \brief Enumerates cnco profile chan selection mode +*/ +typedef enum { + ADI_APOLLO_CNCO_CHAN_SEL_DIRECT_REGMAP = 0x00, /*!< Direct spi/hsci nco profile select. Apply profile immediately */ + ADI_APOLLO_CNCO_CHAN_SEL_DIRECT_GPIO = 0x04, /*!< Direct GPIO profile select. Apply profile immediately */ + ADI_APOLLO_CNCO_CHAN_SEL_TRIGGER_BASED = 0x0d /*!< Trigger based hopping. Trig options: external, internal (timer based) and spi/hsci. */ +} adi_apollo_cnco_profile_sel_mode_e; + +/*! +* \brief Enumerates cnco phase handling after FTW hop +*/ +typedef enum { + ADI_APOLLO_CNCO_HOP_PHASE_COHERENT = 0x00, /*!< Hopped phase coherent with initial phase */ + ADI_APOLLO_CNCO_HOP_PHASE_CONTINUOUS = 0x01, /*!< Maintain phase between hops */ + ADI_APOLLO_CNCO_HOP_PHASE_RESET = 0x02 /*!< Reset phase after hop */ +} adi_apollo_cnco_hop_phase_handling_e; + +/*! +* \brief Enumerates cnco profile select mode for trigger based hopping +*/ +typedef enum { + ADI_APOLLO_CNCO_TRIG_PROF_SEL_AUTO = 0x0, /*!< Auto Hopping Mode selection in Trigger based hopping */ + ADI_APOLLO_CNCO_TRIG_PROF_SEL_REGMAP = 0x1, /*!< Scheduled Regmap Hopping Mode selection in Trigger based Hopping */ + ADI_APOLLO_CNCO_TRIG_PROF_SEL_GPIO = 0x2 /*!< Scheduled GPIO hopping mode selection in Trigger based hopping */ +} adi_apollo_cnco_trig_profile_sel_mode_e; + +/*! +* \brief Enumerates cnco mixer dc test mode values selection +*/ +typedef enum { + ADI_APOLLO_CNCO_MXR_TEST_RX_FS = 0x7FF, /*!< Rx path Full scale value */ + ADI_APOLLO_CNCO_MXR_TEST_RX_FS_BY2 = 0x3FF, /*!< Rx path Full scale by 2 value */ + ADI_APOLLO_CNCO_MXR_TEST_RX_FS_BY4 = 0x1FF, /*!< Rx path Full scale by 4 value */ + ADI_APOLLO_CNCO_MXR_TEST_TX_FS = 0x1FFF, /*!< Tx path Full scale value */ + ADI_APOLLO_CNCO_MXR_TEST_TX_FS_BY2 = 0xFFF, /*!< Tx path Full scale by 2 value */ + ADI_APOLLO_CNCO_MXR_TEST_TX_FS_BY4 = 0x7FF, /*!< Tx path Full scale by 4 value */ +} adi_apollo_cnco_mxr_test_sel_e; + +/*! + * \brief Tx coarse nco parameters + */ +typedef struct { + uint32_t ftw; /*!< Freq tuning work (phase increment) */ + adi_apollo_nco_mixer_mode_e mode; /*!< NCO mode. (ADI_APOLLO_MXR_VAR_IF_MODE, _ZERO_IF_MODE, _FS_BY_4_MODE, _TEST_MODE) \ref adi_apollo_nco_mixer_mode_e */ + adi_apollo_drc_mixer_sel_e mixer; /*!< NCO mixer real or complex mode. (ADI_APOLLO_DRC_MIXER_REAL, _COMPLEX)\ref adi_apollo_drc_mixer_sel_e */ +} adi_apollo_tx_cnco_t; + +/*! +* \brief COARSE NCO programming data +*/ +typedef struct { + adi_apollo_nco_mixer_mode_e if_mode; /*!< \ref adi_apollo_nco_mixer_mode_e */ + adi_apollo_drc_mixer_sel_e mixer_sel; /*!< \ref adi_apollo_drc_mixer_sel_e */ + adi_apollo_nco_cmplx_mult_scale_e cmplx_mxr_scale_en; /*!< Enables the complex mixer scaling (0.7x or 1x scaling) */ + adi_apollo_nco_profile_sel_mode_e profile_sel_mode; /*!< Profile selection mode (direct reg, gpio or trigger) */ + uint8_t profile_num; /*!< Profile index to program and set active (for direct spi/hsci mode)*/ + uint32_t drc_phase_inc; /*!< NCO phase increment. Complex mixing freq = (drc_phase_inc * Fs) / 2^32 */ + uint32_t drc_phase_offset; /*!< NCO phase offset. Fs/32 clocks in 4T4R and Fs/16 clocks in 8T8R */ + uint32_t drc_phase_inc_frac_a; /*!< Numerator correction term for modulus phase accumulator */ + uint32_t drc_phase_inc_frac_b; /*!< Denominator correction term for modulus phase accumulator */ + uint16_t dc_testmode_value; /*!< dc multiplier for nco test mode */ + uint8_t drc_en; /*!< Enabling Coarse DDC/DUC */ + uint8_t debug_drc_clkoff_n; /*!< If this bit is zero, NCO mixer Clock is shut off */ +} adi_apollo_cnco_pgm_t; + +/*! +* \brief COARSE NCO inspect params +*/ +typedef struct { + adi_apollo_cnco_cfg_t dp_cfg; /*!< Parameters defined from device profile \ref apollo_cpu_device_profile_types.h */ + + uint8_t profile_num; /*!< Shadow Register index for rd/wr */ + uint8_t active_profile_num; /*!< Profile index to program and set active (for direct spi/hsci mode)*/ + + uint32_t active_phase_inc; /*!< Active phase inc */ + uint32_t active_phase_offset; /*!< Active phase offset */ + uint8_t drc_phase_dither_en; /*!< Enabling Phase Dither Correction in NCO output */ + uint8_t drc_amp_dither_en; /*!< Enabling Amplitude Dither Correction in NCO output */ +} adi_apollo_cnco_inspect_t; + +/*! +* \brief Coarse NCO hop programming data +*/ +typedef struct { + adi_apollo_nco_profile_sel_mode_e profile_sel_mode; /*!< Profile selection mode (e.g. direct or trigger based) */ + adi_apollo_nco_auto_flip_incdir_e auto_mode; /*!< Selects auto flip, increment or decrement when auto hop enabled. \ref adi_apollo_nco_auto_flip_incdir_e */ + uint8_t high_limit; /*!< Upper hop limit profile num when auto hop flip is enabled */ + uint8_t low_limit; /*!< Lower hop limit profile num when auto hop flip is enabled */ + uint8_t next_hop_number_wr_en; /*!< 1 = Enable writing next hop number. 0 = disable */ + uint8_t hop_ctrl_init; /*!< 1 = Enable loading the initial profile to start hopping from. 0 = disable */ + uint8_t phase_handling; /*!< Phase handling after frequency hop \ref adi_apollo_cnco_hop_phase_handling_e */ +} adi_apollo_coarse_nco_hop_t; + +/*! +* \brief COARSE NCO channel programming data +*/ +typedef struct { + uint32_t drc_phase_inc; /*!< NCO Phase Increment Value. Phase Increment Value for the NCO. Complex mixing frequency = (drc_phase_inc * Fs) / 2^10.*/ + uint32_t drc_phase_offset; /*!< DDC/DUC phase offset input. Registered in Fs/32 clock in 4T4R and Fs/16 clock in 8T8R */ + uint32_t drc_phase_inc_frac_a; /*!< Numerator correction term for modulus phase accumulator */ + uint32_t drc_phase_inc_frac_b; /*!< Denominator correction term for modulus phase accumulator */ +} adi_apollo_coarse_nco_chan_pgm_t; + +#endif /* __ADI_APOLLO_CNCO_TYPES_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_common.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_common.h new file mode 100644 index 00000000000000..30e22f4ea0b1e4 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_common.h @@ -0,0 +1,37 @@ +/*! + * \brief API header file + * This file contains all the publicly exposed methods and data + * structures to interface with API. + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_COMMON + * @{ + */ +#ifndef __ADI_APOLLO_COMMON_H__ +#define __ADI_APOLLO_COMMON_H__ + + + /*============= I N C L U D E S ============*/ +#include "adi_apollo_common_types.h" + +#ifndef __maybe_unused +#define __maybe_unused __attribute__((__unused__)) +#endif + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_COMMON_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_common_types.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_common_types.h new file mode 100644 index 00000000000000..b1372fbda36df2 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_common_types.h @@ -0,0 +1,486 @@ +/*! + * \brief API header file + * This file contains all the publicly exposed methods and data + * structures to interface with API. + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_COMMON + * @{ + */ + +#ifndef __ADI_APOLLO_COMMON_TYPES_H__ +#define __ADI_APOLLO_COMMON_TYPES_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_cms_api_common.h" +#include "apollo_cpu_device_profile_types.h" +#include "adi_apollo_hal_regio_spi_types.h" +#include "adi_apollo_hal_regio_hsci_types.h" +#include "adi_apollo_startup_types.h" + +/*============= D E F I N E S ==============*/ +#define USE_PRIVATE_BF + +#define adi_apollo_blk_sel_t uint16_t + +#define ADI_APOLLO_ADC_NUM 8 +#define ADI_APOLLO_ADC_PER_SIDE_NUM 4 +#define ADI_APOLLO_DAC_NUM 8 +#define ADI_APOLLO_DAC_PER_SIDE_NUM 4 + +#define ADI_APOLLO_NUM_JTX_SERDES_12PACKS 2 +#define ADI_APOLLO_NUM_JRX_SERDES_12PACKS 2 +#define ADI_APOLLO_NUM_JTX_LINKS 4 +#define ADI_APOLLO_NUM_JRX_LINKS 4 +#define ADI_APOLLO_NUM_JTX_LINKS_PER_SIDE 2 +#define ADI_APOLLO_NUM_JRX_LINKS_PER_SIDE 2 + +#define ADI_APOLLO_NUM_LINX_PER_SIDE 4 +#define ADI_APOLLO_NUM_CFIR_PER_SIDE 2 +#define ADI_APOLLO_NUM_FSRC_PER_SIDE 2 + +#define ADI_APOLLO_JESD_SER_COUNT 12 +#define ADI_APOLLO_JESD_DESER_COUNT 12 + +#define ADI_APOLLO_USE_FLOATING_TYPE 0 +#define ADI_APOLLO_USE_SPI_BURST_MODE 0 + +#define ADI_APOLLO_LOW 0 +#define ADI_APOLLO_HIGH 1 + +#define ADI_APOLLO_DISABLE 0 +#define ADI_APOLLO_ENABLE 1 + +#define ADI_APOLLO_NUM_TRIG_MASTER_PER_SIDE 32 + +#define BF_INFO_EXTRACT(...) BF_INFO_EXTRACT_2(__VA_ARGS__) +#define BF_INFO_EXTRACT_2(addr, bf_info) (bf_info) + +#define REG_ADDR_EXTRACT(...) REG_ADDR_EXTRACT_2(__VA_ARGS__) +#define REG_ADDR_EXTRACT_2(addr, bf_info) (addr) + +#define ADI_APOLLO_MAX_SLICES_PER_SIDE_NUM 4 /* Max number of slices per side. For 8T8R, 2 slices are split into 4 */ + +/** + * The following ADI_APOLLO_xxx_IDX2B macros convert functional block indexes to a bit-wise selector. + * Top level APIs use indexes (e.g. 0, 1, ...) plus a side select to address functional blocks. + * Block level APIs use bitwise selectors and are scaled for 8T8R devices. + */ +#define ADI_APOLLO_SIDE_IDX2B(side) (1<<(side)) +#define ADI_APOLLO_CDDC_IDX2B(side, idx) (1<<((side)*(ADI_APOLLO_CDDC_PER_SIDE_NUM) + (idx))) +#define ADI_APOLLO_FDDC_IDX2B(side, idx) (1<<((side)*(ADI_APOLLO_FDDC_PER_SIDE_NUM) + (idx))) +#define ADI_APOLLO_CDUC_IDX2B(side, idx) (1<<((side)*(ADI_APOLLO_CDUC_PER_SIDE_NUM) + (idx))) +#define ADI_APOLLO_FDUC_IDX2B(side, idx) (1<<((side)*(ADI_APOLLO_FDUC_PER_SIDE_NUM) + (idx))) +#define ADI_APOLLO_PFILT_IDX2B(side, idx) (1<<((side)*(ADI_APOLLO_PFILT_PER_SIDE) + (idx))) +#define ADI_APOLLO_PFILT_COEFF_IDX2B(idx) (1<< (idx)) +#define ADI_APOLLO_CFIR_IDX2B(side, idx) (1<<((side)*(ADI_APOLLO_CFIR_PER_SIDE_NUM) + (idx))) +#define ADI_APOLLO_CFIR_COEFF_SET_IDX2B(idx) (1<< (idx)) +#define ADI_APOLLO_CFIR_PROFILE_IDX2B(idx) (1<< (idx)) +#define ADI_APOLLO_FSRC_IDX2B(side, idx) (1<<((side)*(ADI_APOLLO_FSRC_PER_SIDE_NUM) + (idx))) +#define ADI_APOLLO_DFMT_IDX2B(side, idx) (1<<((side)*(ADI_APOLLO_JESD_LINKS) + (idx))) +#define ADI_APOLLO_SMON_IDX2B(side, idx) (1 << ((side) * (ADI_APOLLO_SMON_PER_SIDE_NUM) + (idx))) + +/*! + * \brief Enumerates ADC Select + */ +typedef enum { + ADI_APOLLO_ADC_NONE = 0x0, /*!< No ADC */ + ADI_APOLLO_ADC_A0 = 0x1, /*!< ADC0 of SIDE A */ + ADI_APOLLO_ADC_A1 = 0x2, /*!< ADC1 of SIDE A */ + ADI_APOLLO_ADC_A2 = 0x4, /*!< ADC2 of SIDE A */ + ADI_APOLLO_ADC_A3 = 0x8, /*!< ADC3 of SIDE A */ + ADI_APOLLO_ADC_B0 = 0x10, /*!< ADC0 of SIDE B */ + ADI_APOLLO_ADC_B1 = 0x20, /*!< ADC1 of SIDE B */ + ADI_APOLLO_ADC_B2 = 0x40, /*!< ADC2 of SIDE B */ + ADI_APOLLO_ADC_B3 = 0x80, /*!< ADC3 of SIDE B */ + ADI_APOLLO_ADC_ALL = 0xFF, /*!< ALL ADCs (8T8R) */ + ADI_APOLLO_ADC_A_ALL = 0x0F, /*!< ALL ADCs of SIDE A (8T8R) */ + ADI_APOLLO_ADC_B_ALL = 0xF0, /*!< ALL ADCs of SIDE B (8T8R) */ + ADI_APOLLO_ADC_ALL_4T4R = 0x33, /*!< ALL ADCs (4T4R) */ + ADI_APOLLO_ADC_A_ALL_4T4R = 0x03, /*!< ALL ADCs of SIDE A (4T4R) */ + ADI_APOLLO_ADC_B_ALL_4T4R = 0x30, /*!< ALL ADCs of SIDE B (4T4R) */ +} adi_apollo_adc_select_e; + +/*! + * \brief Enumerates ADC Select - Side independent + */ +typedef enum { + ADI_APOLLO_ADC_IDX_NONE = 0x0, /*!< No ADC */ + ADI_APOLLO_ADC_0 = 0x1, /*!< ADC0 */ + ADI_APOLLO_ADC_1 = 0x2, /*!< ADC1 */ + ADI_APOLLO_ADC_2 = 0x4, /*!< ADC2 */ + ADI_APOLLO_ADC_3 = 0x8, /*!< ADC3 */ + ADI_APOLLO_ADC_IDX_ALL = 0xF, /*!< All ADCs */ +} adi_apollo_adc_idx_e; + +/*! + * \brief Enumerates DAC Select - Side independent + */ +typedef enum { + ADI_APOLLO_DAC_IDX_NONE = 0x0, /*!< No DAC */ + ADI_APOLLO_DAC_0 = 0x1, /*!< DAC0 */ + ADI_APOLLO_DAC_1 = 0x2, /*!< DAC1 */ + ADI_APOLLO_DAC_2 = 0x4, /*!< DAC2 */ + ADI_APOLLO_DAC_3 = 0x8, /*!< DAC3 */ + ADI_APOLLO_DAC_IDX_ALL = 0xF, /*!< All DACs */ +} adi_apollo_dac_idx_e; + +/*! + * \brief Enumerates DAC Select + */ +typedef enum { + ADI_APOLLO_DAC_NONE = 0x0, /*!< No DAC */ + ADI_APOLLO_DAC_A0 = 0x1, /*!< DAC0 of SIDE A */ + ADI_APOLLO_DAC_A1 = 0x2, /*!< DAC1 of SIDE A */ + ADI_APOLLO_DAC_A2 = 0x4, /*!< DAC2 of SIDE A */ + ADI_APOLLO_DAC_A3 = 0x8, /*!< DAC3 of SIDE A */ + ADI_APOLLO_DAC_B0 = 0x10, /*!< DAC0 of SIDE B */ + ADI_APOLLO_DAC_B1 = 0x20, /*!< DAC1 of SIDE B */ + ADI_APOLLO_DAC_B2 = 0x40, /*!< DAC2 of SIDE B */ + ADI_APOLLO_DAC_B3 = 0x80, /*!< DAC3 of SIDE B */ + ADI_APOLLO_DAC_ALL = 0xFF, /*!< ALL DACs (8T8R) */ + ADI_APOLLO_DAC_A_ALL = 0x0F, /*!< ALL DACs of SIDE A (8T8R) */ + ADI_APOLLO_DAC_B_ALL = 0xF0, /*!< ALL DACs of SIDE B (8T8R) */ + ADI_APOLLO_DAC_ALL_4T4R = 0x33, /*!< ALL DACs (4T4R) */ + ADI_APOLLO_DAC_A_ALL_4T4R = 0x03, /*!< ALL DACs of SIDE A (4T4R) */ + ADI_APOLLO_DAC_B_ALL_4T4R = 0x30, /*!< ALL DACs of SIDE B (4T4R) */ +} adi_apollo_dac_select_e; + +/*! + * \brief Enumerates East/West side + */ +typedef enum { + ADI_APOLLO_SIDE_NONE = 0x0, /*!< No side */ + ADI_APOLLO_SIDE_A = 0x1, /*!< A side select */ + ADI_APOLLO_SIDE_B = 0x2, /*!< B side select */ + ADI_APOLLO_SIDE_ALL = 0x3 /*!< All sides */ +} adi_apollo_side_select_e; + +/*! + * \brief Enumerates the serdes 12-packs + */ +typedef enum { + ADI_APOLLO_TXRX_SERDES_12PACK_NONE = 0x00, /*!< No select */ + ADI_APOLLO_TXRX_SERDES_12PACK_A = 0x01, /*!< Tx or Rx 12pack side A */ + ADI_APOLLO_TXRX_SERDES_12PACK_B = 0x02, /*!< Tx or Rx 12pack side B */ + ADI_APOLLO_TXRX_SERDES_12PACK_ALL = 0x03 /*!< Tx or Rx 12packs all sides */ +} adi_apollo_serdes_12pack_select_e; + +/*! + * \brief Enumerates Link Select + */ +typedef enum { + ADI_APOLLO_LINK_NONE = 0x0, /*!< No Link */ + ADI_APOLLO_LINK_A0 = 0x1, /*!< A side Link 0 */ + ADI_APOLLO_LINK_A1 = 0x2, /*!< A side Link 1 */ + ADI_APOLLO_LINK_B0 = 0x4, /*!< B side Link 0 */ + ADI_APOLLO_LINK_B1 = 0x8, /*!< B side Link 1 */ + ADI_APOLLO_LINK_ALL = 0xf /*!< All Links */ +} adi_apollo_jesd_link_select_e; + +/*! + * \brief Enumerates Link side Select + */ +typedef enum { + ADI_APOLLO_LINK_SIDE_NONE = 0x0, /*!< No Link */ + ADI_APOLLO_LINK_SIDE_A = 0x1, /*!< A side. Corresponds to both link 0 and link 1 of side A */ + ADI_APOLLO_LINK_SIDE_B = 0x4, /*!< B side. Corresponds to both link 0 and link 1 of side B */ + ADI_APOLLO_LINK_SIDE_ALL = 0x5 /*!< All sides. Corresponds to all Links */ +} adi_apollo_jesd_link_side_select_e; + +/*! +* \brief Enumerates Terminal type selection +*/ +typedef enum { + ADI_APOLLO_RX = 0x0, /*!< RX TERMINAL SIGNAL PATH*/ + ADI_APOLLO_TX = 0x1, /*!< TX TERMINAL SIGNAL PATH */ +} adi_apollo_terminal_e; + +/*! + * \brief Enumerates Reset Operation + */ +typedef enum { + ADI_APOLLO_NO_RESET = 0, /*!< No Reset */ + ADI_APOLLO_SOFT_RESET = 1, /*!< Soft Reset */ + ADI_APOLLO_HARD_RESET = 2, /*!< Hard Reset */ + ADI_APOLLO_SOFT_RESET_AND_INIT = 3, /*!< Soft Reset Then Init */ + ADI_APOLLO_HARD_RESET_AND_INIT = 4 /*!< Hard Reset Then Init */ +} adi_apollo_reset_e; + +/*! + * \brief Enumerates JESD Serializer Swing Settings + */ +typedef enum { + ADI_APOLLO_SER_SWING_1000 = 0, /*!< 1000 mV Swing */ + ADI_APOLLO_SER_SWING_850 = 1, /*!< 850 mV Swing */ + ADI_APOLLO_SER_SWING_750 = 2, /*!< 750 mV Swing */ + ADI_APOLLO_SER_SWING_500 = 3 /*!< 500 mV Swing */ +} adi_apollo_ser_swing_e; + +/*! + * \brief Enumerates JESD Serializer Pre-Emphasis Settings + */ +typedef enum { + ADI_APOLLO_SER_PRE_EMP_0DB = 0, /*!< 0 db Pre-Emphasis */ + ADI_APOLLO_SER_PRE_EMP_3DB = 1, /*!< 3 db Pre-Emphasis */ + ADI_APOLLO_SER_PRE_EMP_6DB = 2 /*!< 6 db Pre-Emphasis */ +} adi_apollo_ser_pre_emp_e; + +/*! + * \brief Enumerates JESD Serializer Post-Emphasis Settings + */ +typedef enum { + ADI_APOLLO_SER_POST_EMP_0DB = 0, /*!< 0 db Post-Emphasis */ + ADI_APOLLO_SER_POST_EMP_3DB = 1, /*!< 3 db Post-Emphasis */ + ADI_APOLLO_SER_POST_EMP_6DB = 2, /*!< 6 db Post-Emphasis */ + ADI_APOLLO_SER_POST_EMP_9DB = 3, /*!< 9 db Post-Emphasis */ + ADI_APOLLO_SER_POST_EMP_12DB = 4 /*!< 12 db Post-Emphasis */ +} adi_apollo_ser_post_emp_e; + +/*! +* \brief Powerup control enable pin select +*/ +typedef enum { + ADI_APOLLO_PUC_EN_PIN_0 = 0, /*!< Enable pin 0 select for a pwr control input */ + ADI_APOLLO_PUC_EN_PIN_1 = 1, /*!< Enable pin 1 select for a pwr control input */ + ADI_APOLLO_PUC_EN_PIN_2 = 2, /*!< Enable pin 2 select for a pwr control input */ + ADI_APOLLO_PUC_EN_PIN_3 = 3, /*!< Enable pin 3 select for a pwr control input */ +} adi_apollo_puc_en_pin_sel_e; + +/*! +* \brief Powerup control clock rate +*/ +typedef enum { + ADI_APOLLO_PUC_CLK_RATE_FS_DIV_32 = 0, /*!< Clock rate of Fs/32 (default) */ + ADI_APOLLO_PUC_CLK_RATE_FS_DIV_256 = 1, /*!< Clock rate of Fs/32 (default) */ +} adi_apollo_puc_clk_rate_sel_e; + + +/*! +* \brief Powerup control rising edge select +*/ +typedef enum { + ADI_APOLLO_PUC_EDGE_RISE_E0 = 0, /*!< Converter enable rise on E0: after few retiming clock cycles from RxEn rising edge */ + ADI_APOLLO_PUC_EDGE_RISE_E1 = 1, /*!< Converter enable rise on E1: after counter A reaches max programmed value. */ + ADI_APOLLO_PUC_EDGE_RISE_E2 = 2, /*!< Converter enable rise on E2: after counters A+B reach max programmed value. */ + ADI_APOLLO_PUC_EDGE_RISE_E3 = 3, /*!< Converter enable rise on E3: after counters A+B+C reach max programmed value. */ +} adi_apollo_puc_edge_rise_sel_e; + +/*! +* \brief Powerup control falling edge select +*/ +typedef enum { + ADI_APOLLO_PUC_EDGE_FALL_E4 = 0, /*!< Converter enable fall on E4: after few retiming clock cycles from RxEn falling edge */ + ADI_APOLLO_PUC_EDGE_FALL_E5 = 1, /*!< Converter enable fall on E5: after counter D reaches max programmed value. */ + ADI_APOLLO_PUC_EDGE_FALL_E6 = 2, /*!< Converter enable fall on E6: after counters D+E reach max programmed value. */ + ADI_APOLLO_PUC_EDGE_FALL_E7 = 3, /*!< Converter enable fall on E7: after counters D+E+F reach max programmed value. */ +} adi_apollo_puc_edge_fall_sel_e; + +/*! + * \brief Enumerates slice select per side + */ +typedef enum { + ADI_APOLLO_RX_SLICE_NONE = 0x00, /*!< No slices */ + ADI_APOLLO_RX_SIDE_A_SLICE_0 = 0x01, /*!< Side A slice 0 select */ + ADI_APOLLO_RX_SIDE_A_SLICE_1 = 0x02, /*!< Side A slice 1 select */ + ADI_APOLLO_RX_SIDE_A_SLICE_2 = 0x04, /*!< Side A slice 2 select (8t8r only) */ + ADI_APOLLO_RX_SIDE_A_SLICE_3 = 0x08, /*!< Side A slice 3 select (8t8r only) */ + ADI_APOLLO_RX_SIDE_B_SLICE_0 = 0x10, /*!< Side B slice 0 select */ + ADI_APOLLO_RX_SIDE_B_SLICE_1 = 0x20, /*!< Side B slice 1 select */ + ADI_APOLLO_RX_SIDE_B_SLICE_2 = 0x40, /*!< Side B slice 2 select (8t8r only) */ + ADI_APOLLO_RX_SIDE_B_SLICE_3 = 0x80, /*!< Side B slice 3 select (8t8r only) */ + ADI_APOLLO_RX_SLICE_ALL = 0xFF, /*!< All slices */ +} adi_apollo_rx_slice_select_e; + +/*! + * \brief Enumerates slice select per side + */ +typedef enum { + ADI_APOLLO_TX_SLICE_NONE = 0x00, /*!< No slices */ + ADI_APOLLO_TX_SIDE_A_SLICE_0 = 0x01, /*!< Side A slice 0 select */ + ADI_APOLLO_TX_SIDE_A_SLICE_1 = 0x02, /*!< Side A slice 1 select */ + ADI_APOLLO_TX_SIDE_A_SLICE_2 = 0x04, /*!< Side A slice 2 select (8t8r only) */ + ADI_APOLLO_TX_SIDE_A_SLICE_3 = 0x08, /*!< Side A slice 3 select (8t8r only) */ + ADI_APOLLO_TX_SIDE_B_SLICE_0 = 0x10, /*!< Side B slice 0 select */ + ADI_APOLLO_TX_SIDE_B_SLICE_1 = 0x20, /*!< Side B slice 1 select */ + ADI_APOLLO_TX_SIDE_B_SLICE_2 = 0x40, /*!< Side B slice 2 select (8t8r only) */ + ADI_APOLLO_TX_SIDE_B_SLICE_3 = 0x80, /*!< Side B slice 3 select (8t8r only) */ + ADI_APOLLO_TX_SLICE_ALL = 0xFF, /*!< All slices */ +} adi_apollo_tx_slice_select_e; + +/*! + * \brief Enumerates LINX select + */ +typedef enum { + ADI_APOLLO_LINX_NONE = 0x00, /*!< No LINX */ + ADI_APOLLO_LINX_A0 = 0x01, /*!< LINX 0 of SIDE A */ + ADI_APOLLO_LINX_A1 = 0x02, /*!< LINX 1 of SIDE A */ + ADI_APOLLO_LINX_A2 = 0x04, /*!< LINX 2 of SIDE A (8t8r only) */ + ADI_APOLLO_LINX_A3 = 0x08, /*!< LINX 3 of SIDE A (8t8r only) */ + ADI_APOLLO_LINX_B0 = 0x10, /*!< LINX 0 of SIDE B */ + ADI_APOLLO_LINX_B1 = 0x20, /*!< LINX 1 of SIDE B*/ + ADI_APOLLO_LINX_B2 = 0x40, /*!< LINX 2 of SIDE B (8t8r only) */ + ADI_APOLLO_LINX_B3 = 0x80, /*!< LINX 3 of SIDE B (8t8r only) */ + ADI_APOLLO_LINX_ALL = 0xFF /*!< ALL LINXs */ +} adi_apollo_linx_sel_e; + +/*! + * \brief Enumerates INVSINC select + */ +typedef enum { + ADI_APOLLO_TX_INVSINC_NONE = 0x00, /*!< No TX_INVSINC */ + ADI_APOLLO_TX_INVSINC_A0 = 0x01, /*!< TX_INVSINC 0 of SIDE A */ + ADI_APOLLO_TX_INVSINC_A1 = 0x02, /*!< TX_INVSINC 1 of SIDE A */ + ADI_APOLLO_TX_INVSINC_A2 = 0x04, /*!< TX_INVSINC 2 of SIDE A (8t8r only) */ + ADI_APOLLO_TX_INVSINC_A3 = 0x08, /*!< TX_INVSINC 3 of SIDE A (8t8r only) */ + ADI_APOLLO_TX_INVSINC_B0 = 0x10, /*!< TX_INVSINC 0 of SIDE B */ + ADI_APOLLO_TX_INVSINC_B1 = 0x20, /*!< TX_INVSINC 1 of SIDE B*/ + ADI_APOLLO_TX_INVSINC_B2 = 0x40, /*!< TX_INVSINC 2 of SIDE B (8t8r only) */ + ADI_APOLLO_TX_INVSINC_B3 = 0x80, /*!< TX_INVSINC 3 of SIDE B (8t8r only) */ + ADI_APOLLO_TX_INVSINC_ALL = 0xFF /*!< ALL TX_INVSINCs */ +} adi_apollo_tx_invsinc_sel_e; + +/*! + * \brief Enumerates GAIN CTRL select + */ +typedef enum { + ADI_APOLLO_TX_GAIN_NONE = 0x00, /*!< No TX_GAIN */ + ADI_APOLLO_TX_GAIN_A0 = 0x01, /*!< TX_GAIN 0 of SIDE A */ + ADI_APOLLO_TX_GAIN_A1 = 0x02, /*!< TX_GAIN 1 of SIDE A */ + ADI_APOLLO_TX_GAIN_A2 = 0x04, /*!< TX_GAIN 2 of SIDE A (8t8r only) */ + ADI_APOLLO_TX_GAIN_A3 = 0x08, /*!< TX_GAIN 3 of SIDE A (8t8r only) */ + ADI_APOLLO_TX_GAIN_B0 = 0x10, /*!< TX_GAIN 0 of SIDE B */ + ADI_APOLLO_TX_GAIN_B1 = 0x20, /*!< TX_GAIN 1 of SIDE B*/ + ADI_APOLLO_TX_GAIN_B2 = 0x40, /*!< TX_GAIN 2 of SIDE B (8t8r only) */ + ADI_APOLLO_TX_GAIN_B3 = 0x80, /*!< TX_GAIN 3 of SIDE B (8t8r only) */ + ADI_APOLLO_TX_GAIN_ALL = 0xFF /*!< ALL TX_GAINs */ +} adi_apollo_tx_gain_ctrl_sel_e; + +typedef enum { + ADI_APOLLO_TX_SRD_NONE = 0x00, /*!< No TX_SRD */ + ADI_APOLLO_TX_SRD_A0 = 0x01, /*!< TX_SRD 0 of SIDE A */ + ADI_APOLLO_TX_SRD_A1 = 0x02, /*!< TX_SRD 1 of SIDE A */ + ADI_APOLLO_TX_SRD_A2 = 0x04, /*!< TX_SRD 2 of SIDE A (8t8r only) */ + ADI_APOLLO_TX_SRD_A3 = 0x08, /*!< TX_SRD 3 of SIDE A (8t8r only) */ + ADI_APOLLO_TX_SRD_B0 = 0x10, /*!< TX_SRD 0 of SIDE B */ + ADI_APOLLO_TX_SRD_B1 = 0x20, /*!< TX_SRD 1 of SIDE B*/ + ADI_APOLLO_TX_SRD_B2 = 0x40, /*!< TX_SRD 2 of SIDE B (8t8r only) */ + ADI_APOLLO_TX_SRD_B3 = 0x80, /*!< TX_SRD 3 of SIDE B (8t8r only) */ + ADI_APOLLO_TX_SRD_ALL = 0xFF /*!< ALL TX_SRDs */ +} adi_apollo_tx_srd_sel_e; + +/*! +* \brief NCO auto hop profile selection mode +*/ +typedef enum { + ADI_APOLLO_NCO_AUTO_HOP_DECR = 0, /*!< Auto hop decrement mode*/ + ADI_APOLLO_NCO_AUTO_HOP_INCR = 1, /*!< Auto hop increment mode */ + ADI_APOLLO_NCO_AUTO_HOP_FLIP = 2 /*!< Auto hop flip mode. Uses hi/lo limits. */ +} adi_apollo_nco_auto_flip_incdir_e; + +#ifndef CLIENT_IGNORE + +typedef struct { + adi_apollo_blk_sel_t adc; + adi_apollo_blk_sel_t bmem; + adi_apollo_blk_sel_t cddc; + adi_apollo_blk_sel_t cduc; + adi_apollo_blk_sel_t cfir; + adi_apollo_blk_sel_t cnco; + adi_apollo_blk_sel_t dac; + adi_apollo_blk_sel_t fddc; + adi_apollo_blk_sel_t fduc; + adi_apollo_blk_sel_t fnco; + adi_apollo_blk_sel_t fsrc; + adi_apollo_blk_sel_t invsinc; + adi_apollo_blk_sel_t pfilt; + adi_apollo_blk_sel_t rxen; + adi_apollo_blk_sel_t smon; + adi_apollo_blk_sel_t sniffer; + adi_apollo_blk_sel_t txen; + adi_apollo_blk_sel_t txmux; +} adi_apollo_device_blk_sel_mask_t; + +/*! + * \brief Per lane JESD Serializer Settings + */ +typedef struct { + adi_apollo_ser_swing_e swing_setting; + adi_apollo_ser_pre_emp_e pre_emp_setting; + adi_apollo_ser_post_emp_e post_emp_setting; +} adi_apollo_ser_lane_settings_t; + + + +/*! + * \brief Device Hardware Abstract Layer Structure + */ +typedef struct { + void * user_data; /*!< Pointer to generic user data. */ + void * dev_hal_info; /*!< Pointer to user platform hal object */ + + adi_apollo_hal_regio_spi_desc_t spi0_desc; /*!< SPI0 HAL descriptor */ + adi_apollo_hal_regio_spi_desc_t spi1_desc; /*!< SPI1 HAL descriptor */ + adi_apollo_hal_regio_hsci_desc_t hsci_desc; /*!< HSCI HAL descriptor */ + + void *active_regio; /*!< Active device protocol (e.g. sp0, sp1, hsci) */ + + adi_apollo_hal_open_t hw_open; /*!< Platform hal open (optional) */ + adi_apollo_hal_close_t hw_close; /*!< Platform hal close (optional) */ + adi_apollo_hal_delay_us_t delay_us; /*!< Platform hal delay us (required) */ + adi_apollo_hal_reset_pin_ctrl_t reset_pin_ctrl; /*!< Platform hal reset pin control (required) */ + adi_apollo_hal_log_write_t log_write; /*!< Platform hal log write function (optional) */ +} adi_apollo_hal_t; + +/*! + * \brief Device Internal Information Structure + */ +typedef struct { + uint64_t dev_freq_hz; /*!< Device clock frequency in Hz */ + uint64_t dac_freq_hz; /*!< DAC clock frequency in Hz */ + uint64_t adc_freq_hz; /*!< ADC clock frequency in Hz */ + uint8_t dev_rev; /*!< Device revision, 0:a0, 1:b0 */ + uint8_t is_8t8r; /*!< 0 if 4t4r device, 1 if 8t8r device */ + uint8_t is_dual_clk; /*!< Whether the device is in dual clk mode */ + + adi_apollo_device_lockout_t lockout_mask; /*!< device variant feature lockout */ + adi_apollo_device_blk_sel_mask_t blk_sel_mask; /*!< device block instance select masks */ +} adi_apollo_info_t; + +/*! + * \brief Device startup sequence information structure + * + * The adi_apollo_hal_fw_provider_t data struct, along with open, close and get methods, create an interface for providing + * FW binaries during adi_apollo_startup_execute() execution. This provides a platform agnostic interface for loading + * the Apollo firmware. + * + * All memory management, file I/O, etc. is handled in user app space. + */ +typedef struct { + adi_apollo_fw_provider_t *fw_provider; /*!< Platform FW image provider. Used in startup sequence */ + + adi_apollo_fw_provider_open_t open; /*!< Called from adi_apollo_startup_execute() before 'get' when writing a FW binary to ARM (may be NULL) */ + adi_apollo_fw_provider_close_t close; /*!< Called from adi_apollo_startup_execute() after 'get' when writing a FW binary ARM (may be NULL) */ + adi_apollo_fw_provider_get_t get; /*!< Called from adi_apollo_startup_execute() to obtain binary data to be loaded to ARM. Required. */ +} adi_apollo_startup_t; + +/*! +* \brief Device Structure +*/ +typedef struct adi_apollo_device_t { + adi_apollo_hal_t hal_info; + adi_apollo_info_t dev_info; + adi_apollo_startup_t startup_info; +} adi_apollo_device_t; + + +#endif /* CLIENT_IGNORE*/ + +#endif /* __ADI_APOLLO_COMMON_TYPES_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_config.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_config.h new file mode 100644 index 00000000000000..0cca172a1c7e84 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_config.h @@ -0,0 +1,161 @@ +/*! + * \brief Device configuration header + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_CONFIG + * @{ + */ +#ifndef __ADI_APOLLO_CONFIG_H__ +#define __ADI_APOLLO_CONFIG_H__ + +/*============= D E F I N E S ==============*/ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_common.h" + +/*============= D E F I N E S ==============*/ +#if (defined(__STDC_VERSION__) && __STDC_VERSION__ == 199901L) + #define __FUNCTION_NAME__ __func__ +#else + #define __FUNCTION_NAME__ __FUNCTION__ +#endif + +#define ADI_APOLLO_API_REV 0x00000001 + +/* var error report */ +#define ADI_APOLLO_MSG_REPORT(var, comment) \ + adi_apollo_hal_error_report(device, ADI_CMS_LOG_MSG, API_CMS_ERROR_OK, __FILE__, __FUNCTION_NAME__, __LINE__, #var, comment) +#define ADI_APOLLO_WARN_REPORT(var, comment) \ + adi_apollo_hal_error_report(device, ADI_CMS_LOG_WARN, API_CMS_ERROR_OK, __FILE__, __FUNCTION_NAME__, __LINE__, #var, comment) +#define ADI_APOLLO_ERROR_REPORT(error, var, comment) \ + adi_apollo_hal_error_report(device, ADI_CMS_LOG_ERR, error, __FILE__, __FUNCTION_NAME__, __LINE__, #var, comment) + +/* log report */ +#define ADI_APOLLO_LOG_FUNC() \ + adi_apollo_hal_log_write(device, ADI_CMS_LOG_API, "%s(...)", __FUNCTION_NAME__) +#define ADI_APOLLO_LOG_SPIR(addr, data) \ + adi_apollo_hal_log_write(device, ADI_CMS_LOG_SPI, "apollo: r@%.4x = %.2x", addr, data) +#define ADI_APOLLO_LOG_SPIW(addr, data) \ + adi_apollo_hal_log_write(device, ADI_CMS_LOG_SPI, "apollo: w@%.4x = %.2x", addr, data) +#define ADI_APOLLO_LOG_SPIR32(addr, data) \ + adi_apollo_hal_log_write(device, ADI_CMS_LOG_SPI, "apollo: r32@%.4x = %.8x", addr, data) +#define ADI_APOLLO_LOG_SPIW32(addr, data) \ + adi_apollo_hal_log_write(device, ADI_CMS_LOG_SPI, "apollo: w32@%.4x = %.8x", addr, data) + +#define ADI_APOLLO_LOG_VAR(type, msg, ...) \ + adi_apollo_hal_log_write(device, type, msg, ##__VA_ARGS__) + +#define ADI_APOLLO_LOG_MSG(msg) \ + adi_apollo_hal_log_write(device, ADI_CMS_LOG_MSG, msg) +#define ADI_APOLLO_LOG_MSG_VAR(msg, ...) \ + ADI_APOLLO_LOG_VAR(ADI_CMS_LOG_MSG, msg, ##__VA_ARGS__) + +#define ADI_APOLLO_LOG_WARN(msg) \ + adi_apollo_hal_log_write(device, ADI_CMS_LOG_WARN, msg) +#define ADI_APOLLO_LOG_WARN_VAR(msg, ...) \ + ADI_APOLLO_LOG_VAR(ADI_CMS_LOG_WARN, msg, ##__VA_ARGS__) + +#define ADI_APOLLO_LOG_ERR(msg) \ + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, msg) +#define ADI_APOLLO_LOG_ERR_VAR(msg, ...) \ + ADI_APOLLO_LOG_VAR(ADI_CMS_LOG_ERR, msg, ##__VA_ARGS__) + +/* var error check */ +#define ADI_APOLLO_LOG_ERROR_RETURN_CODE(err, msg, code) \ +{ \ + if ((err) != API_CMS_ERROR_OK) { \ + ADI_APOLLO_LOG_ERR(msg); \ + return (code); \ + } \ +} + +#define ADI_APOLLO_LOG_ERROR_RETURN(err, msg) \ + ADI_APOLLO_LOG_ERROR_RETURN_CODE(err, msg, err); + +#define ADI_APOLLO_ERROR_RETURN(r) \ +{ \ + if (r != API_CMS_ERROR_OK) { \ + return r; \ + } \ +} + +#define ADI_APOLLO_LOG_ERROR_RETURN_VAR(r, msg, ...) \ +{ \ + if (r != API_CMS_ERROR_OK) { \ + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, msg, ##__VA_ARGS__); \ + return r; \ + } \ +} + +#define ADI_APOLLO_ERROR_GOTO(r, label) \ +{ \ + if (r != API_CMS_ERROR_OK) { \ + goto label; \ + } \ +} + +#define ADI_APOLLO_LOG_ERROR_GOTO_VAR(r, label, msg, ...) \ +{ \ + if (r != API_CMS_ERROR_OK) { \ + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, msg, ##__VA_ARGS__); \ + goto label; \ + } \ +} + +#define ADI_APOLLO_NULL_POINTER_RETURN(p) \ +{ \ + if(p == NULL) { \ + ADI_APOLLO_ERROR_REPORT(API_CMS_ERROR_NULL_PARAM, p, "Null pointer passed."); \ + return API_CMS_ERROR_NULL_PARAM; \ + } \ +} + +#define ADI_APOLLO_INVALID_PARAM_RETURN(r) \ +{ \ + if(r) { \ + ADI_APOLLO_ERROR_REPORT(API_CMS_ERROR_INVALID_PARAM, r, "Invalid param passed."); \ + return API_CMS_ERROR_INVALID_PARAM; \ + } \ +} + +#define ADI_APOLLO_NOT_IMPLEMENTED_RETURN(r) \ +{ \ + if(r) { \ + ADI_APOLLO_ERROR_REPORT(API_CMS_ERROR_NOT_IMPLEMENTED, r, "Not implemented feature or param."); \ + return API_CMS_ERROR_NOT_IMPLEMENTED; \ + } \ +} + +#define ADI_APOLLO_INVALID_PARAM_WARN(r) \ +{ \ + if(r) { \ + ADI_APOLLO_WARN_REPORT(r, "Invalid param passed."); \ + } \ +} + +#define ADI_APOLLO_DEV_FEAT_LOCKOUT_RETURN(term, feat) \ +{ \ + if (adi_apollo_private_device_lockout_get(device, term, feat)) { \ + ADI_APOLLO_ERROR_REPORT(API_CMS_ERROR_FEAT_LOCKOUT, feat, "Device feature is locked out."); \ + return API_CMS_ERROR_FEAT_LOCKOUT; \ + } \ +} + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_CONFIG_H__ */ + +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_dac.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_dac.h new file mode 100644 index 00000000000000..d184a25fe414fc --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_dac.h @@ -0,0 +1,121 @@ +/*! + * \brief DAC definition headers + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_DAC + * @{ + */ +#ifndef __ADI_APOLLO_DAC_H__ +#define __ADI_APOLLO_DAC_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_dac_types.h" + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Set internal dac core trim attributes (deliberately vague) + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] dacs Target DAC selector \ref adi_apollo_dac_select_e + * \param[in] trim_attr Clock trim attribute. \ref adi_apollo_dac_clk_trim_e + * \param[in] trim_val Trim value + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details + */ +int32_t adi_apollo_dac_clk_trim_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t dacs, adi_apollo_dac_clk_trim_e trim_attr, uint8_t trim_val); + +/** + * \brief Get an internal dac core trim attribute (deliberately vague) + * \note Only 1 DAC selection per call + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] dacs Target DAC selector. Only one dac selected at a time. \ref adi_apollo_dac_select_e + * \param[in] trim_attr Clock trim attribute. \ref adi_apollo_dac_clk_trim_e + * \param[out] trim_val Trim value return + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details + */ +int32_t adi_apollo_dac_clk_trim_get(adi_apollo_device_t *device, adi_apollo_blk_sel_t dacs, adi_apollo_dac_clk_trim_e trim_attr, uint8_t *trim_val); + +/** + * \brief Enable or disable tx datapath scrambler to avoid substrate noise coupling + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] scrambler_sel DAC Scrambler selection. \ref adi_apollo_dac_select_e + * \param[in] enable 1: to enable scrambler, 0: to disable + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_dac_scrambler_enable_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t scrambler_sel, uint8_t enable); + +/** + * \brief Get state of tx datapath scrambler + * \note Only one scrambler channel per call. Select one within ADI_APOLLO_DAC_A0 - ADI_APOLLO_DAC_B3. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] scrambler_sel DAC Scrambler selection. \ref adi_apollo_dac_select_e + * \param[out] enable Enable flag. 0: disable, 1: enable + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_dac_scrambler_enable_get(adi_apollo_device_t *device, adi_apollo_blk_sel_t scrambler_sel, uint8_t *enable); + +/** + * \brief Enable or disable internal dac data (deliberately vague) + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] dacs Target DAC selector \ref adi_apollo_dac_select_e + * \param[in] enable 1. Enable DAC data. 0. Disable DAC data. + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details + */ +int32_t adi_apollo_dac_data_enable(adi_apollo_device_t *device, adi_apollo_blk_sel_t dacs, uint8_t enable); + +/** + * \brief Locks out or unlock DAC's Standby control + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] dacs Target DAC selector \ref adi_apollo_dac_select_e + * \param[in] lock_state 1: Locks out DAC's Standby control ensuring DACs are always ON, (Default) + * 0: Unlocks DAC's Standby control so DACs can be toggled in or out of STANDBY using either SPI or GPIO control + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details + */ +int32_t adi_apollo_dac_standby_lock_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t dacs, uint8_t lock_state); + +/** + * \brief Get DAC's Standby Control lock state + * \note Only 1 DAC selection per call + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] dacs Target DAC selector \ref adi_apollo_dac_select_e + * \param[out] lock_state 1: DAC's Standby control is locked and DAC can't be configured into STANDBY + * 0: DAC's Standby control is unlocked and DACs can be toggled in or out of STANDBY using either SPI or GPIO control + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details + */ +int32_t adi_apollo_dac_standby_lock_get(adi_apollo_device_t *device, adi_apollo_blk_sel_t dacs, uint8_t *lock_state); + +#ifdef __cplusplus +} +#endif + +#endif /*__ADI_APOLLO_DAC_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_dac_types.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_dac_types.h new file mode 100644 index 00000000000000..d4a9d75b0ed50e --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_dac_types.h @@ -0,0 +1,31 @@ +/*! + * \brief Apollo DAC types header + * + * \copyright copyright(c) 2022 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_DAC + * @{ + */ +#ifndef __ADI_APOLLO_DAC_TYPES_H__ +#define __ADI_APOLLO_DAC_TYPES_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_cms_api_common.h" +#include "adi_apollo_common.h" + +/*! +* \brief DAC clock trim attributes +*/ +typedef enum { + ADI_APOLLO_DAC_CLK_TRIM_1 = 1, + ADI_APOLLO_DAC_CLK_TRIM_2 = 2, + ADI_APOLLO_DAC_CLK_TRIM_3 = 3 +} adi_apollo_dac_clk_trim_e; + +#endif /* __ADI_APOLLO_DAC_TYPES_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_device.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_device.h new file mode 100644 index 00000000000000..772e10372233c4 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_device.h @@ -0,0 +1,307 @@ +/*! + * \brief API header file + * This file contains all the publicly exposed methods and data + * structures to interface with API. + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_DEVICE + * @{ + */ +#ifndef __ADI_APOLLO_DEVICE_H__ +#define __ADI_APOLLO_DEVICE_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_common.h" +#include "adi_apollo_device_types.h" + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Perform SPI register write access to device + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] addr SPI address to which the value of data parameter shall be written + * \param[in] data 8-bit value to be written to SPI register defined by the address parameter. + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_device_spi_register_set(adi_apollo_device_t *device, uint32_t addr, uint8_t data); + +/** + * \brief Perform SPI register read access from device + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] addr SPI address from which the value of data parameter shall be read, + * \param[out] data Pointer to an 8-bit variable to which the value of the + * SPI register at the address defined by address parameter shall be stored. + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_device_spi_register_get(adi_apollo_device_t *device, uint32_t addr, uint8_t *data); + +/** + * \brief Open hardware platform + * Just call user callback for function pointer 'hw_open'. Please note this is optional if user + * configure hardware platform by themselves. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] reset_opt A parameter to indicate reset operation. \ref adi_apollo_reset_e + * ADI_APOLLO_NO_RESET indicates no reset is required + * ADI_APOLLO_SOFT_RESET indicates a software reset is required. + * ADI_APOLLO_HARD_RESET indicates a hardware reset is required. + * ADI_APOLLO_SOFT_RESET_AND_INIT indicates a software reset + initialization is required. + * ADI_APOLLO_HARD_RESET_AND_INIT indicates a hardware reset + initialization is required. + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_device_hw_open(adi_apollo_device_t *device, adi_apollo_reset_e reset_opt); + +/** + * \brief Close hardware platform + * Just call user callback for function pointer 'hw_close'. Please note this is optional if user + * close hardware platform by themselves. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_device_hw_close(adi_apollo_device_t *device); + +/** + * \brief Initialize apollo device + * This API will configure device SPI working mode, and check power supplies status. Must be called + * after platform SPI master is already initialized and adi_apollo_device_reset() is called. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_device_init(adi_apollo_device_t *device); + +/** + * \brief De-initialize device + * This API will do hard then soft reset. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_device_deinit(adi_apollo_device_t *device); + +/** + * \brief Reset device + * Issues a hard reset or soft reset of the device. + * Performs a full reset of device via the hardware pin (hard) or + * via the SPI register (soft). + * Resetting all SPI registers to default and triggering the required + * initialization sequence. + * adi_apollo_device_init() will be called if operation is ADI_APOLLO_SOFT_RESET_AND_INIT or + * ADI_APOLLO_HARD_RESET_AND_INIT. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] reset_opt A parameter to indicate reset operation. \ref adi_apollo_reset_e + * ADI_APOLLO_NO_RESET indicates no reset is required + * ADI_APOLLO_SOFT_RESET indicates a software reset is required. + * ADI_APOLLO_HARD_RESET indicates a hardware reset is required. + * ADI_APOLLO_SOFT_RESET_AND_INIT indicates a software reset + initialization is required. + * ADI_APOLLO_HARD_RESET_AND_INIT indicates a hardware reset + initialization is required. + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_device_reset(adi_apollo_device_t *device, adi_apollo_reset_e reset_opt); + +/** + * \brief Get chip identification data + * Read-back product type, identification and revision data. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[out] chip_id \ref adi_cms_chip_id_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_device_chip_id_get(adi_apollo_device_t *device, adi_cms_chip_id_t *chip_id); + +/** + * \brief Get API revision + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[out] rev_major Pointer to variable to store the major revision + * \param[out] rev_minor Pointer to variable to store the minor revision + * \param[out] rev_rc Pointer to variable to store the rc revision + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_device_api_revision_get(adi_apollo_device_t *device, uint16_t *rev_major, + uint16_t *rev_minor, uint16_t *rev_rc); + +/** + * \brief Get Laminate ID + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[out] id Pointer to silicon laminate id. + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_device_laminate_id_get(adi_apollo_device_t *device, uint8_t *id); + +/** + * \brief Get DIE ID + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[out] id Pointer to silicon DIE id. + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_device_die_id_get(adi_apollo_device_t *device, uint8_t *id); + +/** + * \brief Get Silicon Grade ID + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[out] si_grade Pointer to Silicon Grade ID. + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_device_si_grade_get(adi_apollo_device_t *device, uint8_t *si_grade); + +/** + * \brief Get sw variant Tx/Rx/Mxfe info + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[out] mxfe Pointer to sw variant tx/rx/mxfe info. \ref adi_apollo_device_sw_variant_mxfe_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_device_sw_mxfe_get(adi_apollo_device_t *device, adi_apollo_device_sw_variant_mxfe_e *mxfe); + +/** + * \brief Get sw trim info + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[out] sw_trim Pointer to sw trim info. \ref adi_apollo_device_sw_variant_trim_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_device_sw_trim_get(adi_apollo_device_t *device, adi_apollo_device_sw_variant_trim_e *sw_trim); + +/** + * \brief Get trx config info + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[out] trx_cfg Pointer to trx config. \ref adi_apollo_device_rev_trx_config_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_device_trx_config_get(adi_apollo_device_t *device, adi_apollo_device_rev_trx_config_e *trx_cfg); + +/** + * \brief Get rx type info + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[out] rx_type Pointer to rx type. \ref adi_apollo_device_rev_rx_type_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_device_rx_type_get(adi_apollo_device_t *device, adi_apollo_device_rev_rx_type_e *rx_type); + +/** + * \brief Get board variant and rev info + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[out] board_var_rev Pointer to board variant and rev info. \ref adi_apollo_device_board_var_and_rev_info_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_device_board_variant_and_rev_get(adi_apollo_device_t *device, adi_apollo_device_board_var_and_rev_info_t *board_var_rev); + +/** + * \brief Configure SPI settings + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] spi_config Ptr to spi configuration \ref adi_apollo_device_spi_settings_t + * \param[in] spi_num Spi num (0 = SPI0, 1 = SPI1) + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_device_spi_configure(adi_apollo_device_t *device, adi_apollo_device_spi_settings_t *spi_config, uint8_t spi_num); + +/** + * \brief Configure HSCI settings + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] hsci_config Ptr to hsci configuration \ref adi_apollo_device_hsci_settings_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_device_hsci_configure(adi_apollo_device_t *device, adi_apollo_device_hsci_settings_t *hsci_config); + +/** + * \brief Get UUID + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[out] uuid Array of uuid + * \param[in] uuid_len Length of uuid array param. Must be set to ADI_APOLLO_UUID_NUM_BYTES + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_device_uuid_get(adi_apollo_device_t *device, uint8_t uuid[], uint32_t uuid_len); + +/** + * \brief Get TMU Data + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[out] tmu_data Temperature data returned by CPU + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_device_tmu_get(adi_apollo_device_t *device, adi_apollo_device_tmu_data_t *tmu_data); + +/** + * \brief Enable TMU + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_device_tmu_enable(adi_apollo_device_t *device); + +#ifndef CLIENT_IGNORE +#endif /* CLIENT_IGNORE*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_DEVICE_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_device_types.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_device_types.h new file mode 100644 index 00000000000000..9251abc1e427b8 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_device_types.h @@ -0,0 +1,162 @@ +/*! + * \brief API SPI and HSCI device header file + * This file contains all the publicly exposed methods and data + * structures to interface with API. + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_DEVICE + * @{ + */ + +#ifndef __ADI_APOLLO_DEVICE_TYPES_H__ +#define __ADI_APOLLO_DEVICE_TYPES_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_cms_api_common.h" + +#define ADI_APOLLO_UUID_NUM_BYTES 16 + +/*! + * @brief Enumerates SW variant Tx/Rx/Mxfe + */ +typedef enum { + ADI_APOLLO_DEVICE_SW_VARIANT_TX_ONLY = 0x0, /*!< TX only part */ + ADI_APOLLO_DEVICE_SW_VARIANT_RX_ONLY = 0x1, /*!< RX only part */ + ADI_APOLLO_DEVICE_SW_VARIANT_MXFE = 0x2, /*!< MXFE part */ + ADI_APOLLO_DEVICE_SW_VARIANT_INVALID = 0xFF /*!< Invalid SW variant */ +} adi_apollo_device_sw_variant_mxfe_e; + +/*! + * @brief Enumerates SW variant Trim + */ +typedef enum { + ADI_APOLLO_DEVICE_SW_VARIANT_TRIM_NOT_SET = 0x0, /*!< SW Trim is not set yet */ + ADI_APOLLO_DEVICE_SW_VARIANT_TRIM_SW1 = 0x1, /*!< This part is suitable for SW1, SW3, SW5 trim levels. */ + ADI_APOLLO_DEVICE_SW_VARIANT_TRIM_SW3 = 0x3, /*!< This part is suitable for SW3, SW5 trim levels. */ + ADI_APOLLO_DEVICE_SW_VARIANT_TRIM_SW5 = 0x5, /*!< This part is suitable only for SW5 trim levels. */ + ADI_APOLLO_DEVICE_SW_VARIANT_TRIM_INVALID = 0xFF /*!< Invalid SW Trim */ +} adi_apollo_device_sw_variant_trim_e; + +/*! + * @brief Enumerates Rev Trx Config + */ +typedef enum { + ADI_APOLLO_DEVICE_REV_TRX_CONFIG_4T4R = 0x0, /*!< 4T4R */ + ADI_APOLLO_DEVICE_REV_TRX_CONFIG_8T8R = 0x1, /*!< 8T8R */ +} adi_apollo_device_rev_trx_config_e; + +/*! + * @brief Enumerates Rev RX Type + */ +typedef enum { + ADI_APOLLO_DEVICE_REV_RX_DIFF = 0x0, /*!< differential rx */ + ADI_APOLLO_DEVICE_REV_RX_SE = 0x1, /*!< single ended rx */ +} adi_apollo_device_rev_rx_type_e; + +/*! + * @brief board variant and rev info structure + */ +typedef struct { + adi_apollo_device_sw_variant_mxfe_e mxfe; + adi_apollo_device_sw_variant_trim_e sw_trim; + adi_apollo_device_rev_trx_config_e trx_cfg; + adi_apollo_device_rev_rx_type_e rx_type; + uint8_t si_grade; + uint8_t die_id; +} adi_apollo_device_board_var_and_rev_info_t; + +/*! + * @brief SPI mode settings + */ +typedef enum { + ADI_APOLLO_DEVICE_SPI_NONE = 0, /*!< Keep this for test */ + ADI_APOLLO_DEVICE_SPI_SDO = 1, /*!< SDO active, 4-wire only */ + ADI_APOLLO_DEVICE_SPI_SDIO = 2, /*!< SDIO active, 3-wire only */ + ADI_APOLLO_DEVICE_SPI_CONFIG_MAX = 3 /*!< Keep it last */ +} adi_apollo_device_spi_sdo_config_e; + +/*! + * @brief SPI bit order settings + */ +typedef enum { + ADI_APOLLO_DEVICE_SPI_MSB_LAST = 0, /*!< LSB first */ + ADI_APOLLO_DEVICE_SPI_MSB_FIRST = 1 /*!< MSB first */ +} adi_apollo_device_spi_msb_config_e; + +/*! + * @brief SPI address increment settings + */ +typedef enum { + ADI_APOLLO_DEVICE_SPI_ADDR_DEC_AUTO = 0, /*!< auto decremented */ + ADI_APOLLO_DEVICE_SPI_ADDR_INC_AUTO = 1 /*!< auto incremented */ +} adi_apollo_device_spi_addr_inc_e; + +/*! + * @brief SPI config + */ +typedef struct +{ + adi_apollo_device_spi_sdo_config_e sdo; /*!< SPI interface 3/4 wire mode configuration */ + adi_apollo_device_spi_msb_config_e msb; /*!< SPI interface MSB/LSB bit order configuration */ + adi_apollo_device_spi_addr_inc_e addr_inc; /*!< SPI interface address increment configuration */ +} adi_apollo_device_spi_settings_t; + + +/*! + * @brief HSCI address increment settings + */ +typedef enum { + ADI_APOLLO_DEVICE_HSCI_ADDR_DEC_AUTO = 0, /*!< auto decremented */ + ADI_APOLLO_DEVICE_HSCI_ADDR_INC_AUTO = 1 /*!< auto incremented */ +} adi_apollo_device_hsci_addr_inc_e; + +/*! +*\brief HSCI config +*/ +typedef struct { + adi_apollo_device_hsci_addr_inc_e addr_inc; /*!< HSCI interface address increment configuration */ + uint8_t loopback_en; /*!< Enable/Disable HSCI Loopback mode */ + uint8_t auto_linkup_en; /*!< Enable/Disable HSCI auto linkup mode */ +} adi_apollo_device_hsci_settings_t; + +/*! +* \brief Temperature readings from all temperature sensors +*/ +typedef enum { + ADI_APOLLO_DEVICE_TMU_SERDES_PLL = 1, + ADI_APOLLO_DEVICE_TMU_MPU_A = 2, + ADI_APOLLO_DEVICE_TMU_MPU_B = 3, + ADI_APOLLO_DEVICE_TMU_ADC_A = 4, + ADI_APOLLO_DEVICE_TMU_CLK_A = 5, + ADI_APOLLO_DEVICE_TMU_ADC_B = 6, + ADI_APOLLO_DEVICE_TMU_CLK_B = 7, + ADI_APOLLO_DEVICE_TMU_CLK_C = 8 +} adi_apollo_device_tmu_index_e; + +/** + * \brief API function wrap for temperature data returned by CPU + */ +typedef struct { + int16_t temp_degrees_celsius[9]; /*!< Temperature readings from all temperature sensors \ref adi_apollo_device_tmu_index_e for details.*/ + int16_t temp_degrees_celsius_avg; /*!< Average temperature reading of temperature sensors specified in avgMask */ + uint16_t avg_mask; /*!< Bitmask indicating which temperature sensors are averaged in tempDegreesCelciusAvg - see \ref adi_apollo_mailbox_temp_sensor_mask_e */ + int16_t max_temp_degrees_celsius; /*!< Max temperature reading of temperature sensors specified in avgMask */ + int16_t min_temp_degrees_celsius; /*!< Min temperature reading of temperature sensors specified in avgMask */ +} adi_apollo_device_tmu_data_t; + +typedef struct { + uint32_t rx_lockout_mask; /*!< rx device hw feature mask (1 means locked out) */ + uint32_t tx_lockout_mask; /*!< tx device hw feature mask (1 means locked out) */ +} adi_apollo_device_lockout_t; + +#ifndef CLIENT_IGNORE +#endif /* CLIENT_IGNORE*/ + +#endif /* __ADI_APOLLO_DEVICE_TYPES_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_dformat.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_dformat.h new file mode 100644 index 00000000000000..9aa711389d5d5a --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_dformat.h @@ -0,0 +1,134 @@ +/*! + * \brief DDC Block definition headers + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_DFORMAT + * @{ + */ +#ifndef __ADI_APOLLO_DFORMAT_H__ +#define __ADI_APOLLO_DFORMAT_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_dformat_types.h" + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif +/** + * \brief Configure DFORMAT parameters + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] links Target link select \ref adi_apollo_jesd_link_select_e + * \param[in] config \ref adi_apollo_dformat_pgm_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_dformat_pgm(adi_apollo_device_t *device, const uint16_t links, adi_apollo_dformat_pgm_t *config); + +/** + * \brief Configure chip output resolution + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] links Target link select \ref adi_apollo_jesd_link_select_e + * \param[in] resolution Chip output resolution, \ref adi_apollo_chip_output_res_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_dformat_res_sel_set(adi_apollo_device_t *device, + const uint16_t links, + adi_apollo_chip_output_res_e resolution); + +/** + * \brief Select output data format + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] links Target link select \ref adi_apollo_jesd_link_select_e + * \param[in] format 0: 2's complement, 1: offset binary, 2: gray code + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_dformat_format_sel_set(adi_apollo_device_t *device, const uint16_t links, + uint8_t format); + +/** + * \brief Select converter control bit function + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] links Target link select \ref adi_apollo_jesd_link_select_e + * \param[in] bit0_sel Control bit selection 0 (LSB) \ref adi_apollo_dformat_ctrl_bit_e + * \param[in] bit1_sel Control bit selection 1 \ref adi_apollo_dformat_ctrl_bit_e + * \param[in] bit2_sel Control bit selection 2 (MSB) \ref adi_apollo_dformat_ctrl_bit_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_dformat_ctrl_bit_sel_set(adi_apollo_device_t *device, const uint16_t links, + uint8_t bit0_sel, uint8_t bit1_sel, uint8_t bit2_sel); + +/** + * \brief Inspect DFORMAT parameters for a link + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] link Target link select (ADI_APOLLO_LINK_A0, A1, B0, B1) \ref adi_apollo_jesd_link_select_e + * \param[out] inspect Pointer to DFormat inspect structure. + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_dformat_inspect(adi_apollo_device_t *device, const uint16_t link, adi_apollo_dformat_inspect_t *inspect); + +/** + * \brief Get DFORMAT overflow status + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] link Target link select (ADI_APOLLO_LINK_A0, A1, B0, B1) \ref adi_apollo_jesd_link_select_e + * \param[in] clear Clear sticky overflow status bits + * \param[out] status Overflow status + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_dformat_overflow_status_get(adi_apollo_device_t *device, const uint16_t link, uint8_t clear, uint8_t *status); + +/** + * \brief Clear DFORMAT overflow status + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] link Target link select (ADI_APOLLO_LINK_A0, A1, B0, B1) \ref adi_apollo_jesd_link_select_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_dformat_overflow_status_clear(adi_apollo_device_t *device, const uint16_t link); + +/** + * \brief Connect SMON and Fast Detect JESD control bits FDDC I/Q path + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] map Map specifying control bit to FDDC I/Q path connectons \ref adi_apollo_dformat_smon_fd_map_t + * \param[in] map_len NUmber of entries in 'map' array + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_dformat_smon_fd_fddc_set(adi_apollo_device_t *device, adi_apollo_dformat_smon_fd_map_t map[], uint32_t map_len); + +#ifndef CLIENT_IGNORE +#endif /* CLIENT_IGNORE*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_DFORMAT_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_dformat_types.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_dformat_types.h new file mode 100644 index 00000000000000..9c927ea9b52b4a --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_dformat_types.h @@ -0,0 +1,110 @@ +/*! + * \brief DDC Block definition headers + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_DFORMAT + * @{ + */ +#ifndef __ADI_APOLLO_DFORMAT_TYPES_H__ +#define __ADI_APOLLO_DFORMAT_TYPES_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_cms_api_common.h" +#include "adi_apollo_common.h" +#include "adi_apollo_rxmux_types.h" + +/*============= D E F I N E S ==============*/ +#define ADI_APOLLO_DFORMAT_FDDC_SMON_I_PATH 0 +#define ADI_APOLLO_DFORMAT_FDDC_SMON_Q_PATH 1 + +/*! +* \brief Enumerates Digital ADC Data Format selection +*/ +typedef enum { + ADI_APOLLO_DFOR_COMPLEMENT_2 = 0x0, /*!< 2's complement */ + ADI_APOLLO_DFOR_OFFSET_BINARY = 0x1, /*!< Offset Binary */ + ADI_APOLLO_DFOR_GRAY_CODE = 0x2, /*!< Gray Code */ +} adi_apollo_dformat_sel_e; + +/*! + * \brief Enumerates Chip Output Resolution + */ +typedef enum { + ADI_APOLLO_CHIP_OUT_RES_16BIT = 0x0, /*!< 16Bit */ + ADI_APOLLO_CHIP_OUT_RES_15BIT = 0x1, /*!< 15Bit */ + ADI_APOLLO_CHIP_OUT_RES_14BIT = 0x2, /*!< 14Bit */ + ADI_APOLLO_CHIP_OUT_RES_13BIT = 0x3, /*!< 13Bit */ + ADI_APOLLO_CHIP_OUT_RES_12BIT = 0x4, /*!< 12Bit */ + ADI_APOLLO_CHIP_OUT_RES_11BIT = 0x5, /*!< 11Bit */ + ADI_APOLLO_CHIP_OUT_RES_10BIT = 0x6, /*!< 10Bit */ + ADI_APOLLO_CHIP_OUT_RES_09BIT = 0x7, /*!< 9Bit */ + ADI_APOLLO_CHIP_OUT_RES_08BIT = 0x8 /*!< 8Bit */ +} adi_apollo_chip_output_res_e; + +/*! + * \brief Enumerates JESD control bit selection + */ +typedef enum { + ADI_APOLLO_DFOR_CTRL_OVR = 0x0, /*!< Ctrl bit assigned to overflow */ + ADI_APOLLO_DFOR_CTRL_LOW = 0x1, /*!< Ctrl bit always low */ + ADI_APOLLO_DFOR_CTRL_SMON = 0x2, /*!< Ctrl bit assigned to SMON */ + ADI_APOLLO_DFOR_CTRL_FD = 0x3, /*!< Ctrl bit assigned to Fast Detect */ + ADI_APOLLO_DFOR_CTRL_SYSREF = 0x5, /*!< Ctrl bit assigned to SYSREF (fullbandwidth mode only) */ + ADI_APOLLO_DFOR_CTRL_INVALID = 0x6, /*!< Ctrl bit assigned to invalid data status */ + ADI_APOLLO_DFOR_CTRL_NEGFS = 0x7, /*!< Ctrl bit assigned to negative fullscale */ +} adi_apollo_dformat_ctrl_bit_e; + +/*! + * \brief Enumerates FDDC I/Q to ADC select for FD and SMON + */ +typedef enum { + ADI_APOLLO_DFOR_FDDC_ADC_A0 = 0, /*!< FDDC I/Q to ADC-A0 sel */ + ADI_APOLLO_DFOR_FDDC_ADC_A1 = 2, /*!< FDDC I/Q to ADC-A1 sel */ + ADI_APOLLO_DFOR_FDDC_ADC_A2 = 1, /*!< FDDC I/Q to ADC-A2 sel */ + ADI_APOLLO_DFOR_FDDC_ADC_A3 = 3 /*!< FDDC I/Q to ADC-A3 sel */ +} adi_apollo_dformat_fddc_adc_e; + +/*! +* \brief DFORMAT programming data +*/ +typedef struct { + adi_apollo_dformat_sel_e dfor_sel; /*!< \ref adi_apollo_dformat_sel_e */ + uint8_t dfor_inv; /*!< Digital ADC Sample Invert on link. 0: ADC sample data is NOT inverted, 1: ADC sample data is inverted */ + uint8_t dfor_ddc_dither_en; /*!< Dformat dither enable for DDC mode for link. 0: dformat dither disable, 1: dformat dither enable */ + adi_apollo_chip_output_res_e dfor_res; /*!< \ref adi_apollo_chip_output_res_e */ + uint8_t link_en; /*!< Link 1:Enable, 0:Disable */ + uint16_t dcm_ratio; /*!< Chip Decimation Ratio corresponding to link. The least overall decimation among DDCs present in link */ + uint16_t total_dcm; /*!< Link Total Decimation */ + uint8_t invalid_en; /*!< Invalid sample enable */ + uint8_t sample_repeat_en; /*!< Sample repeat enable */ +} adi_apollo_dformat_pgm_t; + +/*! +* \brief DFORMAT SMON and Fast Detect map to FDDC I/Q path sel +*/ +typedef struct { + adi_apollo_rxmux_cbout_sel_e cbout; /*!< SMON to ADC connect via Rx Mux1. CBout_x */ + adi_apollo_blk_sel_t fddc_select; /*!< FDDC select \ref adi_apollo_fine_ddc_select_e */ + uint8_t i_q_select; /*!< FDDC I or Q path */ +} adi_apollo_dformat_smon_fd_map_t; + +/*! + * \brief DFORMAT inspect params + */ +typedef struct +{ + adi_apollo_dformat_cfg_t dp_cfg; /*!< \ref adi_apollo_dformat_cfg_t */ + uint8_t link_en; /*!< Link 1:Enable, 0:Disable */ + uint16_t dcm_ratio; /*!< Chip Decimation Ratio corresponding to link. The least overall decimation among DDCs present in link */ + uint16_t total_dcm; /*!< Link Total Decimation */ + +} adi_apollo_dformat_inspect_t; + +#endif /* __ADI_APOLLO_DFORMAT_TYPES_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_fddc.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_fddc.h new file mode 100644 index 00000000000000..c82877efa1daa8 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_fddc.h @@ -0,0 +1,135 @@ +/*! + * \brief Fine DDC functional block API prototypes + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_FDDC + * @{ + */ +#ifndef __ADI_APOLLO_FDDC_H__ +#define __ADI_APOLLO_FDDC_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_fddc_types.h" + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Set the fine DDC decimation + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] fddcs Target FDDC. ADI_APOLLO_FDDC_A0, _A0-_A7, _B0-_B7, _ALL \ref adi_apollo_fine_ddc_select_e + * \param[in] dcm Fine decimation enum. ADI_APOLLO_FDDC_RATIO_1, _2, _4, _8, _16, _32 \ref adi_apollo_fddc_ratio_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_fddc_dcm_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t fddcs, adi_apollo_fddc_ratio_e dcm); + +/** + * \brief Set the fine DDC link num + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] fddcs Target FDDC \ref adi_apollo_fine_ddc_select_e + * \param[in] link_num Jesd link num fddc is sent to. 0 = link0, 1 = link1 + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_fddc_link_num_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t fddcs, uint8_t link_num); + +/** + * \brief Set state of fine DDC debug clocks + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] fddcs Target FDDC \ref adi_apollo_fine_ddc_select_e + * \param[in] clkoff_n Set to 0xff for normal operation. See bitfield FINE_CLK_DEBUG. + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_fddc_debug_clkoff_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t fddcs, uint8_t clkoff_n); + +/** + * \brief Configure FDDC parameters + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] fddcs Target FDDC \ref adi_apollo_fine_ddc_select_e + * \param[in] config \ref adi_apollo_fddc_pgm_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_fddc_pgm(adi_apollo_device_t *device, adi_apollo_blk_sel_t fddcs, adi_apollo_fddc_pgm_t *config); + +/** + * \brief Inspect FDDC parameters + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] fddc Single Target FDDC \ref adi_apollo_fine_ddc_select_e + * \param[out] fddc_inspect Pointer to fddc inspect structure. \ref adi_apollo_fddc_inspect_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_fddc_inspect(adi_apollo_device_t *device, adi_apollo_blk_sel_t fddc, adi_apollo_fddc_inspect_t *fddc_inspect); + +/** + * \brief Determine the numeric FDDC decimation value from the associated enum. Enum vals are HW specific + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] bf_enum Enum that contains register bitfield value for decimation. + * \param[out] val Numeric value of decimation bf enum. + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_fddc_dcm_bf_to_val(adi_apollo_device_t *device, adi_apollo_fddc_ratio_e bf_enum, uint32_t *val); + +/** + * \brief Enable the FDDC datapath HB1 +6dB gain + * + * The HB1 filter contains an optional +6dB gain block. + * This write needs to be performed before sync. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] fddcs Fine FDDC selection. \ref adi_apollo_fine_ddc_select_e + * \param[in] enable Enable flag. 0: disable, 1: enable + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_fddc_gain_enable_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t fddcs, uint8_t enable); + +/** + * \brief Get state of the FDDC datapath +6dB gain + * + * The HB1 filter contains an optional +6dB gain block. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] fddcs Fine FDDC selection. Single selection only. \ref adi_apollo_fine_ddc_select_e + * \param[out] enable Enable flag. 0: disable, 1: enable + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_fddc_gain_enable_get(adi_apollo_device_t *device, adi_apollo_blk_sel_t fddcs, uint8_t *enable); + +#ifndef CLIENT_IGNORE + +#endif /* CLIENT_IGNORE*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_FDDC_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_fddc_types.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_fddc_types.h new file mode 100644 index 00000000000000..8b2d5906087ec5 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_fddc_types.h @@ -0,0 +1,77 @@ +/*! + * \brief Fine DDC functional block definitions + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_FDDC + * @{ + */ +#ifndef __ADI_APOLLO_FDDC_TYPES_H__ +#define __ADI_APOLLO_FDDC_TYPES_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_cms_api_common.h" +#include "adi_apollo_common.h" + +/*============= D E F I N E S ==============*/ +#define ADI_APOLLO_FDDC_NUM 16 +#define ADI_APOLLO_FDDC_PER_SIDE_NUM 8 + +/*! + * \brief Enumerates RX fine DDC select + */ +typedef enum { + ADI_APOLLO_FDDC_NONE = 0x0000, /*!< No FINE DDC */ + ADI_APOLLO_FDDC_A0 = 0x0001, /*!< FINE DDC 0 of SIDE A */ + ADI_APOLLO_FDDC_A1 = 0x0002, /*!< FINE DDC 1 of SIDE A */ + ADI_APOLLO_FDDC_A2 = 0x0004, /*!< FINE DDC 2 of SIDE A */ + ADI_APOLLO_FDDC_A3 = 0x0008, /*!< FINE DDC 3 of SIDE A */ + ADI_APOLLO_FDDC_A4 = 0x0010, /*!< FINE DDC 4 of SIDE A */ + ADI_APOLLO_FDDC_A5 = 0x0020, /*!< FINE DDC 5 of SIDE A */ + ADI_APOLLO_FDDC_A6 = 0x0040, /*!< FINE DDC 6 of SIDE A */ + ADI_APOLLO_FDDC_A7 = 0x0080, /*!< FINE DDC 7 of SIDE A */ + ADI_APOLLO_FDDC_B0 = 0x0100, /*!< FINE DDC 0 of SIDE B */ + ADI_APOLLO_FDDC_B1 = 0x0200, /*!< FINE DDC 1 of SIDE B */ + ADI_APOLLO_FDDC_B2 = 0x0400, /*!< FINE DDC 2 of SIDE B */ + ADI_APOLLO_FDDC_B3 = 0x0800, /*!< FINE DDC 3 of SIDE B */ + ADI_APOLLO_FDDC_B4 = 0x1000, /*!< FINE DDC 4 of SIDE B */ + ADI_APOLLO_FDDC_B5 = 0x2000, /*!< FINE DDC 5 of SIDE B */ + ADI_APOLLO_FDDC_B6 = 0x4000, /*!< FINE DDC 6 of SIDE B */ + ADI_APOLLO_FDDC_B7 = 0x8000, /*!< FINE DDC 7 of SIDE B */ + ADI_APOLLO_FDDC_ALL = 0xFFFF, /*!< ALL FINE DDCs */ + ADI_APOLLO_FDDC_ALL_4T4R = 0x0F0F /*!< ALL FINE DDCs (4T4R) */ +} adi_apollo_fine_ddc_select_e; + +/*! +* \brief FDDC programming data +*/ +typedef struct { + adi_apollo_fddc_ratio_e dcm; /*!< \ref adi_apollo_fddc_ratio_e */ + uint8_t link_num; /*!< 0: Link0, 1: Link1 */ + uint8_t debug_clkoff_n; /*!< bit 0: filter input clock + bit 1: hb1 clock + bit 2: hb2 clock + bit 3: hb3 clock + bit 4: hb4 clock + bit 5: hb5 clock + bit 6: hb6 clock + bit 7: filter output clock */ + uint8_t hb1_gain_6db_en; /*!< +6dB gain enable on HB1. 0: disable, 1: enable */ + +} adi_apollo_fddc_pgm_t; + +/*! +* \brief FDDC inspect params +*/ +typedef struct { + adi_apollo_fddc_cfg_t dp_cfg; /*!< Parameters defined from device profile \ref apollo_cpu_device_profile_types.h */ + +} adi_apollo_fddc_inspect_t; + +#endif /* __ADI_APOLLO_FDDC_TYPES_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_fduc.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_fduc.h new file mode 100644 index 00000000000000..174a3a2ab84851 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_fduc.h @@ -0,0 +1,150 @@ +/*! + * \brief Fine DUC functional block API prototypes + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_FDUC + * @{ + */ +#ifndef __ADI_APOLLO_FDUC_H__ +#define __ADI_APOLLO_FDUC_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_fduc_types.h" + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Sets fine DUC interpolation value + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] fducs Fine DUC selection. ADI_APOLLO_FDUC_A0, _A0 to _A7, _B0 to _B7, _ALL \ref adi_apollo_fduc_select_e + * \param[in] interp Interpolation enum. ADI_APOLLO_FDUC_RATIO_1, _2, _4, _8, _16, _32, _64 \ref adi_apollo_fduc_ratio_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_fduc_interp_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t fducs, uint8_t interp); + +/** + * \brief Enable fine DUC sub datapath gain + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] fducs Fine DUC selection. \ref adi_apollo_fduc_select_e + * \param[in] enable Enable flag. 0: disable, 1: enable + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_fduc_subdp_gain_enable(adi_apollo_device_t *device, adi_apollo_blk_sel_t fducs, uint8_t enable); + +/** + * \brief Sets the fine DUC sub datapath gain + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] fducs Fine DUC selection. \ref adi_apollo_fduc_select_e + * \param[in] gain 12-bit gain value + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_fduc_subdp_gain_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t fducs, uint16_t gain); + +/** + * \brief Sets the fine DUC integer time delay + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] fducs Fine DUC selection. \ref adi_apollo_fduc_select_e + * \param[in] dly Delay value + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_fduc_int_tdly_hb_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t fducs, uint8_t dly); + +/** + * \brief Sets fine DUC interpolator block parameters + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] fducs Fine DUC selection. \ref adi_apollo_fduc_select_e + * \param[in] config Pointer to fine interpolation parameter struct. \ref adi_apollo_fduc_pgm_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_fduc_pgm(adi_apollo_device_t *device, adi_apollo_blk_sel_t fducs, const adi_apollo_fduc_pgm_t *config); + +/** + * \brief Inspect FDUC parameters + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] fduc Single Target FDUC \ref adi_apollo_fduc_select_e + * \param[out] fduc_inspect Pointer to FDUC inspect structure. \ref adi_apollo_fduc_inspect_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_fduc_inspect(adi_apollo_device_t *device, adi_apollo_blk_sel_t fduc, adi_apollo_fduc_inspect_t *fduc_inspect); + +/** + * \brief Enable or disable register control for setting a FDUC's active state + * + * This method allows FDUC enabling using SPI, which overrides FDUC enables auto decoded + * by summer configuration. + * + * fduc_spien_en must be set for fduc_spi_en to have an effect. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] fducs Coarse FUC selection. \ref adi_apollo_fduc_select_e + * \param[in] fduc_spien_en Enables(1) or disables(0) register control of FDUC active state. Bypasses auto decode. (Typically disabled) + * \param[in] fduc_spi_en If fduc_spien_en is true, then a 1 will activate and 0 deactivate the selected FDUCs + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_fduc_enable_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t fducs, uint8_t fduc_spien_en, uint8_t fduc_spi_en); + + +/** + * \brief Determine the numeric FDUC interpolation value from the associated enum. Enum vals are HW specific + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] bf_enum Enum that contains register bitfield value for decimation. + * \param[out] val Numeric value of decimation bf enum. + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_fduc_interp_bf_to_val(adi_apollo_device_t* device, adi_apollo_fduc_ratio_e bf_enum, uint32_t* val); + +/** + * \brief Enable FDUC overflows to trigger an interrupt + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] fducs Target FDUC \ref adi_apollo_fduc_select_e + * \param[in] enable 1 to enable, 0 to disable + * + * \return API_CMS_ERROR_OK Completed successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_fduc_irq_enable_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t fducs, uint8_t enable); + + +#ifndef CLIENT_IGNORE + +#endif /* CLIENT_IGNORE */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_FDUC_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_fduc_types.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_fduc_types.h new file mode 100644 index 00000000000000..9c5c47ff247a84 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_fduc_types.h @@ -0,0 +1,94 @@ +/*! + * \brief Fine DUC functional block definitions + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_FDUC + * @{ + */ +#ifndef __ADI_APOLLO_FDUC_TYPES_H__ +#define __ADI_APOLLO_FDUC_TYPES_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_cms_api_common.h" +#include "adi_apollo_common.h" + +/*============= D E F I N E S ==============*/ +#define ADI_APOLLO_FDUC_NUM 16 +#define ADI_APOLLO_FDUC_PER_SIDE_NUM 8 +#define ADI_APOLLO_FDUC_INT_DLY_NUM 6 + +/*! + * \brief Enumerates Tx fine DUC select + */ +typedef enum { + ADI_APOLLO_FDUC_NONE = 0x0000, /*!< No FINE DUC */ + ADI_APOLLO_FDUC_A0 = 0x0001, /*!< FINE DUC 0 of SIDE A */ + ADI_APOLLO_FDUC_A1 = 0x0002, /*!< FINE DUC 1 of SIDE A */ + ADI_APOLLO_FDUC_A2 = 0x0004, /*!< FINE DUC 2 of SIDE A */ + ADI_APOLLO_FDUC_A3 = 0x0008, /*!< FINE DUC 3 of SIDE A */ + ADI_APOLLO_FDUC_A4 = 0x0010, /*!< FINE DUC 4 of SIDE A */ + ADI_APOLLO_FDUC_A5 = 0x0020, /*!< FINE DUC 5 of SIDE A */ + ADI_APOLLO_FDUC_A6 = 0x0040, /*!< FINE DUC 6 of SIDE A */ + ADI_APOLLO_FDUC_A7 = 0x0080, /*!< FINE DUC 7 of SIDE A */ + ADI_APOLLO_FDUC_B0 = 0x0100, /*!< FINE DUC 0 of SIDE B */ + ADI_APOLLO_FDUC_B1 = 0x0200, /*!< FINE DUC 1 of SIDE B */ + ADI_APOLLO_FDUC_B2 = 0x0400, /*!< FINE DUC 2 of SIDE B */ + ADI_APOLLO_FDUC_B3 = 0x0800, /*!< FINE DUC 3 of SIDE B */ + ADI_APOLLO_FDUC_B4 = 0x1000, /*!< FINE DUC 4 of SIDE B */ + ADI_APOLLO_FDUC_B5 = 0x2000, /*!< FINE DUC 5 of SIDE B */ + ADI_APOLLO_FDUC_B6 = 0x4000, /*!< FINE DUC 6 of SIDE B */ + ADI_APOLLO_FDUC_B7 = 0x8000, /*!< FINE DUC 7 of SIDE B */ + ADI_APOLLO_FDUC_ALL = 0xFFFF, /*!< All FINE DUCs */ + ADI_APOLLO_FDUC_A_ALL = 0x00FF, /*!< All A side FINE DUCs */ + ADI_APOLLO_FDUC_B_ALL = 0xFF00, /*!< All B side FINE DUCs */ + ADI_APOLLO_FDUC_ALL_4T4R = 0x0F0F, /*!< All FINE DUCs (4T4R) */ + ADI_APOLLO_FDUC_A_ALL_4T4R = 0x000F, /*!< All A side FINE DUCs (4T4R) */ + ADI_APOLLO_FDUC_B_ALL_4T4R = 0x0F00, /*!< All B side FINE DUCs (4T4R) */ +} adi_apollo_fduc_select_e; + +/*! + * \brief Enumerates fine DUC integer delay select + */ +typedef enum { + ADI_APOLLO_FDUC_INT_DLY_NONE = 0x0000, /*!< No int delay */ + ADI_APOLLO_FDUC_INT_DLY_HB1 = 0x0001, /*!< HB1 int delay select */ + ADI_APOLLO_FDUC_INT_DLY_HB2 = 0x0002, /*!< HB2 int delay select */ + ADI_APOLLO_FDUC_INT_DLY_HB3 = 0x0004, /*!< HB3 int delay select */ + ADI_APOLLO_FDUC_INT_DLY_HB4 = 0x0008, /*!< HB4 int delay select */ + ADI_APOLLO_FDUC_INT_DLY_HB5 = 0x0010, /*!< HB5 int delay select */ + ADI_APOLLO_FDUC_INT_DLY_HB6 = 0x0020, /*!< HB6 int delay select */ + ADI_APOLLO_FDUC_INT_DLY_ALL = 0x003F, /*!< All int delays selected*/ +} adi_apollo_fduc_int_tdly_select_e; + +/*! + * \brief Tx fine DUC configuration + */ +typedef struct { + uint8_t interp; /*!< Interpolation value */ + uint8_t sub_dp_gain_en; /*!< Enable sub data path gain. Set value subdp_gain param */ + uint16_t subdp_gain; /*!< Sub data path 12-bit gain */ + uint8_t int_tdly_hb; /*!< Integer time delay control mask for HB1-HB6. b0=HB1, B1=HB2, etc. */ + + uint8_t fduc_spien_en; /*!< Enables(1) or disables(0) SPI control of FDUC. Bypasses auto decode. (Typically disabled) */ + uint8_t fduc_spi_en; /*!< Enable(1) or disable(0) the duc if fduc_spien_en is enabled */ +} adi_apollo_fduc_pgm_t; + +/*! + * \brief Tx fine DUC inspect parameters + */ +typedef struct { + adi_apollo_fduc_cfg_t dp_cfg; /*!< Parameters defined from device profile \ref apollo_cpu_device_profile_types.h */ + + uint8_t int_tdly_hb; /*!< Integer time delay control mask for HB1-HB6. b0=HB1, B1=HB2, etc. */ + uint8_t fduc_spien_en; /*!< Enables(1) or disables(0) SPI control of FDUC. Bypasses auto decode. (Typically disabled) */ + uint8_t fduc_spi_en; /*!< Enable(1) or disable(0) the duc if fduc_spien_en is enabled */ +} adi_apollo_fduc_inspect_t; + +#endif /* __ADI_APOLLO_FDUC_TYPES_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_fnco.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_fnco.h new file mode 100644 index 00000000000000..652f8db2827bf3 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_fnco.h @@ -0,0 +1,292 @@ +/*! + * \brief Fine NCO functional block API prototypes + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_FNCO + * @{ + */ +#ifndef __ADI_APOLLO_FNCO_H__ +#define __ADI_APOLLO_FNCO_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_fnco_types.h" + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Load a FINE NCO profile + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] fncos Target FNCOs \ref adi_apollo_fine_nco_select_e + * \param[in] word_sel Select the phase incr or offset \ref adi_apollo_nco_profile_word_sel_e + * \param[in] first Profile number to load (0 - 15) + * \param[in] words Array of phase increment or offset words (32-bit) + * \param[in] length Number of profiles to load. (first + length must be < 16) + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_fnco_profile_load(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t fncos, + adi_apollo_nco_profile_word_sel_e word_sel, uint8_t first, uint32_t words[], uint32_t length); + +/** + * \brief FINE NCO HOP Enable + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] fncos Target FNCOs \ref adi_apollo_fine_nco_select_e + * \param[in] config \ref adi_apollo_fine_nco_hop_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_fnco_hop_pgm(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t fncos, adi_apollo_fine_nco_hop_t *config); + +/** + * \brief Configure Fine NCO channel parameters + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] fncos Target FNCOs \ref adi_apollo_fine_nco_select_e + * \param[in] profile_num Profile to update + * \param[in] config \ref adi_apollo_fine_nco_chan_pgm_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_fnco_chan_pgm(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t fncos, uint8_t profile_num, adi_apollo_fine_nco_chan_pgm_t *config); + +/** + * \brief Configure Fine NCO main parameters + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] fncos Target FNCOs \ref adi_apollo_fine_nco_select_e + * \param[in] config \ref adi_apollo_fine_nco_main_pgm_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_fnco_main_pgm(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t fncos, adi_apollo_fine_nco_main_pgm_t *config); + +/** + * \brief Configure Fine NCO Rx parameters + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] fncos Target FNCOs \ref adi_apollo_fine_nco_select_e + * \param[in] config \ref adi_apollo_fnco_pgm_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_fnco_pgm(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t fncos, adi_apollo_fnco_pgm_t *config); + +/** + * \brief Configure Fine NCO Rx parameters + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] fnco Single Target FNCOs \ref adi_apollo_fine_nco_select_e + * \param[out] fnco_inspect Pointer to fnco inspect structure. \ref adi_apollo_fnco_inspect_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_fnco_inspect(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t fnco, adi_apollo_fnco_inspect_t *fnco_inspect); + +/** + * \brief Sets the fine NCO mixer for real or complex + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] fncos Target FNCOs \ref adi_apollo_fine_nco_select_e + * \param[in] mixer Select real or complex mixer mode. \ref adi_apollo_drc_mixer_sel_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_fnco_mixer_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t fncos, adi_apollo_drc_mixer_sel_e mixer); + +/** + * \brief Sets the fine NCO mode for variable IF, ZIF, Fs/4 or test mode + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] fncos Target FNCOs \ref adi_apollo_fine_nco_select_e + * \param[in] mode Select variable IF, zero IF, Fs/4 or test NCO mode. \ref adi_apollo_nco_mixer_mode_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_fnco_mode_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t fncos, adi_apollo_nco_mixer_mode_e mode); + +/** + * \brief Sets the fine main NCO phase increment value. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] fncos Target FNCOs \ref adi_apollo_fine_nco_select_e + * \param[in] ftw Frequency tuning word value + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_fnco_main_phase_inc_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t fncos, uint64_t ftw); + +/** + * \brief Sets the fine main NCO phase offset value. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] fncos Target FNCOs \ref adi_apollo_fine_nco_select_e + * \param[in] pow Phase offset tuning word value + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + * + * \note Hopping must be disabled to use this function. See \ref adi_apollo_fnco_hop_enable + */ +int32_t adi_apollo_fnco_main_phase_offset_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t fncos, uint64_t pow); + + +/** + * \brief Enables fine NCO instances + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] fncos Target FNCOs \ref adi_apollo_fine_nco_select_e + * \param[in] enable 1 to enable + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + * + * \note Hopping must be disabled to use this function. See \ref adi_apollo_fnco_hop_enable + */ +int32_t adi_apollo_fnco_enable_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t fncos, uint8_t enable); + + +/** + * \brief Sets the fine NCO test mode input value + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] fncos Target FNCOs \ref adi_apollo_fine_nco_select_e + * \param[in] val Mixer DC Test mode input value \ref adi_apollo_fnco_mxr_test_sel_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_fnco_test_mode_val_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t fncos, uint16_t val); + + +/** + * \brief Sets fine NCO hop freq tuning word (phase increment) + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] fncos Target FNCOs \ref adi_apollo_fine_nco_select_e + * \param[in] profile_num The index in profile table to update + * \param[in] active_en If true, will also set profile_num as the active profile. If in direct spi/hsci mode, output will be immediate. + * \param[in] ftw Frequency tuning word value + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + * + * \note Hopping must be enabled to use this function. See \ref adi_apollo_fnco_hop_enable. + */ +int32_t adi_apollo_fnco_ftw_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t fncos, uint8_t profile_num, uint8_t active_en, uint32_t ftw); + +/** + * \brief Sets fine NCO phase hop offset word (phase offset) + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] fncos Target FNCOs \ref adi_apollo_fine_nco_select_e + * \param[in] profile_num The index in profile table to update + * \param[in] active_en If true, will also set profile_num as the active profile. If in direct spi/hsci mode, output will be immediate. + * \param[in] pow Phase offset word value + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + * + * \note Hopping must be enabled to use this function. See \ref adi_apollo_fnco_hop_enable. + */ +int32_t adi_apollo_fnco_pow_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t fncos, uint8_t profile_num, uint8_t active_en, uint32_t pow); + +/** + * \brief Sets the profile selection mode + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] fncos Target FNCOs \ref adi_apollo_fine_nco_select_e + * \param[in] profile_sel_mode Profile selection mode (e.g. direct reg) \ref adi_apollo_nco_profile_sel_mode_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_fnco_profile_sel_mode_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t fncos, adi_apollo_nco_profile_sel_mode_e profile_sel_mode); + +/** + * \brief Sets the active profile when profile select mode is direct register + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] fncos Target FNCOs \ref adi_apollo_fine_nco_select_e + * \param[in] profile_num Profile table index for NCO + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_fnco_active_profile_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t fncos, uint8_t profile_num); + +/** + * \brief Enable or disable fine NCO hopping + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] fncos Target FNCOs \ref adi_apollo_fine_nco_select_e + * \param[in] hop_en NCO hop enable. 1: enable hopping, 0: disable hopping + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_fnco_hop_enable(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t fncos, uint8_t hop_en); + +/** + * \brief Sets the fine NCO next hop number for trigger based hopping + * + * \note Freq and phase can hop together or individually. See \ref adi_apollo_fnco_trig_hop_sel_e + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] fncos Target FNCOs \ref adi_apollo_coarse_nco_select_e + * \param[in] hop_num_freq The freq profile number to hop to on next trigger. + * \param[in] hop_num_phase The phase profile number to hop to on next trigger. + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_fnco_next_hop_num_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t fncos, int16_t hop_num_freq, int16_t hop_num_phase); + + +#ifndef CLIENT_IGNORE + +#endif /* CLIENT_IGNORE*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_FNCO_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_fnco_types.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_fnco_types.h new file mode 100644 index 00000000000000..a3f796ac61b4d7 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_fnco_types.h @@ -0,0 +1,144 @@ +/*! + * \brief Fine NCO functional block definitions + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_FNCO + * @{ + */ +#ifndef __ADI_APOLLO_FNCO_TYPES_H__ +#define __ADI_APOLLO_FNCO_TYPES_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_cms_api_common.h" +#include "adi_apollo_common.h" + +/*============= D E F I N E S ==============*/ +#define ADI_APOLLO_FNCO_NUM 16 /* Sized for 8T8R */ +#define ADI_APOLLO_FNCO_PER_SIDE_NUM 8 + +/*! + * \brief Enumerates RX fine NCO select + */ +typedef enum +{ + ADI_APOLLO_FNCO_NONE = 0x0000, /*!< No FINE NCO */ + ADI_APOLLO_FNCO_A0 = 0x0001, /*!< FINE NCO 0 of SIDE A */ + ADI_APOLLO_FNCO_A1 = 0x0002, /*!< FINE NCO 1 of SIDE A */ + ADI_APOLLO_FNCO_A2 = 0x0004, /*!< FINE NCO 2 of SIDE A */ + ADI_APOLLO_FNCO_A3 = 0x0008, /*!< FINE NCO 3 of SIDE A */ + ADI_APOLLO_FNCO_A4 = 0x0010, /*!< FINE NCO 4 of SIDE A */ + ADI_APOLLO_FNCO_A5 = 0x0020, /*!< FINE NCO 5 of SIDE A */ + ADI_APOLLO_FNCO_A6 = 0x0040, /*!< FINE NCO 6 of SIDE A */ + ADI_APOLLO_FNCO_A7 = 0x0080, /*!< FINE NCO 7 of SIDE A */ + ADI_APOLLO_FNCO_B0 = 0x0100, /*!< FINE NCO 0 of SIDE B */ + ADI_APOLLO_FNCO_B1 = 0x0200, /*!< FINE NCO 1 of SIDE B */ + ADI_APOLLO_FNCO_B2 = 0x0400, /*!< FINE NCO 2 of SIDE B */ + ADI_APOLLO_FNCO_B3 = 0x0800, /*!< FINE NCO 3 of SIDE B */ + ADI_APOLLO_FNCO_B4 = 0x1000, /*!< FINE NCO 4 of SIDE B */ + ADI_APOLLO_FNCO_B5 = 0x2000, /*!< FINE NCO 5 of SIDE B */ + ADI_APOLLO_FNCO_B6 = 0x4000, /*!< FINE NCO 6 of SIDE B */ + ADI_APOLLO_FNCO_B7 = 0x8000, /*!< FINE NCO 7 of SIDE B */ + ADI_APOLLO_FNCO_ALL = 0xFFFF, /*!< ALL FINE NCOs (8T8R) */ + ADI_APOLLO_FNCO_A_ALL = 0x00FF, /*!< ALL FINE NCOs SIDE A */ + ADI_APOLLO_FNCO_B_ALL = 0xFF00, /*!< ALL FINE NCOs SIDE B */ + ADI_APOLLO_FNCO_ALL_4T4R = 0x0F0F, /*!< ALL FINE NCOs (4T4R) */ + ADI_APOLLO_FNCO_A_ALL_4T4R = 0x000F, /*!< ALL FINE NCOs SIDE A (4T4R) */ + ADI_APOLLO_FNCO_B_ALL_4T4R = 0x0F00 /*!< ALL FINE NCOs SIDE B (4T4R) */ +} adi_apollo_fine_nco_select_e; + +/*! +* \brief Enumerates fnco mixer dc test mode values selection +*/ +typedef enum { + ADI_APOLLO_FNCO_MXR_TEST_RX_FS = 0x1FFF, /*!< Rx path Full scale value */ + ADI_APOLLO_FNCO_MXR_TEST_RX_FS_BY2 = 0xFFF, /*!< Rx path Full scale by 2 value */ + ADI_APOLLO_FNCO_MXR_TEST_RX_FS_BY4 = 0x7FF, /*!< Rx path Full scale by 4 value */ + ADI_APOLLO_FNCO_MXR_TEST_TX_FS = 0x7FFF, /*!< Tx path Full scale value */ + ADI_APOLLO_FNCO_MXR_TEST_TX_FS_BY2 = 0x3FFF, /*!< Tx path Full scale by 2 value */ + ADI_APOLLO_FNCO_MXR_TEST_TX_FS_BY4 = 0x1FFF, /*!< Tx path Full scale by 4 value */ +} adi_apollo_fnco_mxr_test_sel_e; + +/*! +* \brief Enumerates fnco phase handling after FTW hop +*/ +typedef enum { + ADI_APOLLO_FNCO_HOP_PHASE_COHERENT = 0x00, /*!< Hopped phase coherent with initial phase */ + ADI_APOLLO_FNCO_HOP_PHASE_CONTINUOUS = 0x01, /*!< Maintain phase between hops */ + ADI_APOLLO_FNCO_HOP_PHASE_RESET = 0x02 /*!< Reset phase after hop */ +} adi_apollo_fnco_hop_phase_handling_e; + +/*! +* \brief FINE NCO programming data +*/ +typedef struct { + uint8_t drc_en; /*!< Fine nco enable. 1: enable, 0: disable */ + uint8_t debug_drc_clkoff_n; /*!< If this bit is zero, NCO mixer clock is shut off */ + uint8_t hop_mode_en; /*!< 1: Fine NCO hopping enabled, 0: Fine NCO hopping disabled */ + adi_apollo_nco_mixer_mode_e if_mode; /*!< Select IF modes. For example, var if, zero if, fs/4 and DC test. \ref adi_apollo_nco_mixer_mode_e */ + uint16_t dc_testmode_value; /*!< dc multiplier for nco test mode */ + adi_apollo_drc_mixer_sel_e mixer_sel; /*!< Selects real or complex mixing. \ref adi_apollo_drc_mixer_sel_e */ + adi_apollo_nco_cmplx_mult_scale_e cmplx_mxr_scale_en; /*!< Enables the complex mixer scaling. 0.7x or 1x scaling. \ref adi_apollo_nco_cmplx_mult_scale_e */ + adi_apollo_nco_profile_sel_mode_e profile_sel_mode; /*!< Profile selection mode (direct reg, gpio or trigger) */ + uint8_t profile_num; /*!< Profile index to program and set active (for direct spi/hsci mode)*/ + uint64_t main_phase_inc; /*!< Main NCO Phase Increment Value. Two's Complement Phase Increment Value for the NCO. Complex mixing frequency = (ddc_phase_inc * Fs) / 2^48. */ + uint64_t main_phase_offset; /*!< Main NCO Phase Offset. */ + uint64_t drc_phase_inc_frac_a; /*!< Two's Complement Numerator correction term for modulus phase accumulator */ + uint64_t drc_phase_inc_frac_b; /*!< Two's Complement Denominator correction term for modulus phase accumulator */ +} adi_apollo_fnco_pgm_t; + +/*! +* \brief FINE NCO inspect params +*/ +typedef struct { + adi_apollo_fnco_cfg_t dp_cfg; /*!< Parameters defined from device profile \ref apollo_cpu_device_profile_types.h */ + + uint8_t hop_mode_en; /*!< 1: Fine NCO hopping enabled, 0: Fine NCO hopping disabled */ + uint8_t profile_num; /*!< Profile index to program (for direct spi/hsci mode) */ + uint8_t regmap_hopprof; /*!< Regmap based hopping profile number (0-31) */ + uint64_t active_phase_inc; /*!< Active phase inc */ + uint64_t active_phase_offset; /*!< Active phase offset */ + uint8_t drc_phase_dither_en; /*!< Enabling Phase Dither Correction in NCO output */ + uint8_t drc_amp_dither_en; /*!< Enabling Amplitude Dither Correction in NCO output */ +} adi_apollo_fnco_inspect_t; + +/*! +* \brief Fine NCO hop programming data +*/ +typedef struct { + adi_apollo_fnco_trig_hop_sel_e nco_trig_hop_sel; /*!< Enables hoping for freq, phase offset or both */ + adi_apollo_nco_profile_sel_mode_e profile_sel_mode; /*!< Profile selection mode (e.g. direct or trigger based) */ + adi_apollo_nco_auto_flip_incdir_e phase_inc_auto_mode; /*!< Selects freq auto flip, increment or decrement when auto hop enabled. \ref adi_apollo_nco_auto_flip_incdir_e */ + adi_apollo_nco_auto_flip_incdir_e phase_offset_auto_mode; /*!< Selects phase offset auto flip, increment or decrement when auto hop enabled. \ref adi_apollo_nco_auto_flip_incdir_e */ + uint8_t phase_inc_high_limit; /*!< Upper freq hop limit profile num when auto hop flip is enabled */ + uint8_t phase_inc_low_limit; /*!< Lower freq hop limit profile num when auto hop flip is enabled */ + uint8_t phase_offset_high_limit; /*!< Upper phase offset hop limit profile num when auto hop flip is enabled */ + uint8_t phase_offset_low_limit; /*!< Lower phase offset hop limit profile num when auto hop flip is enabled */ + uint8_t phase_handling; /*!< Phase handling after frequency hop \ref adi_apollo_fnco_hop_phase_handling_e */ +} adi_apollo_fine_nco_hop_t; + +/*! +* \brief FINE NCO main programming data +*/ +typedef struct { + uint64_t main_phase_inc; /*!< Main NCO Phase Increment Value. Two's Complement Phase Increment Value for the NCO. Complex mixing frequency = (ddc_phase_inc * Fs) / 2^48. */ + uint64_t main_phase_offset; /*!< Main NCO Phase Offset. */ + uint64_t drc_phase_inc_frac_a; /*!< Two's Complement Numerator correction term for modulus phase accumulator */ + uint64_t drc_phase_inc_frac_b; /*!< Two's Complement Denominator correction term for modulus phase accumulator */ +} adi_apollo_fine_nco_main_pgm_t; + +/*! +* \brief FINE NCO channel programming data +*/ +typedef struct { + uint32_t drc_phase_inc; /*!< Channel NCO Phase Increment Value. Two's Complement Phase Increment Value for the NCO. Complex mixing frequency = (ddc_phase_inc * Fs) / 2^32. */ + uint32_t drc_phase_offset; /*!< Channel NCO Phase Offset. */ +} adi_apollo_fine_nco_chan_pgm_t; + +#endif /* __ADI_APOLLO_FNCO_TYPES_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_fsrc.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_fsrc.h new file mode 100644 index 00000000000000..445bbd5f6b1ff7 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_fsrc.h @@ -0,0 +1,153 @@ +/*! + * \brief FSRC Block definition headers + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_FSRC + * @{ + */ +#ifndef __ADI_APOLLO_FSRC_H__ +#define __ADI_APOLLO_FSRC_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_fsrc_types.h" + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Configure FSRC parameters + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] fsrcs Target FSRC \ref adi_apollo_fsrc_sel_e + * \param[in] config \ref adi_apollo_fsrc_pgm_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_fsrc_pgm(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t fsrcs, adi_apollo_fsrc_pgm_t *config); + +/** + * \brief Inspect FSRC parameters of one FSC block + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] fsrc Target FSRC \ref adi_apollo_fsrc_sel_e + * \param[in] fsrc_inspect \ref adi_apollo_fsrc_inspect_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_fsrc_inspect(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t fsrc, adi_apollo_fsrc_inspect_t *fsrc_inspect); + + +/** + * \brief Configure RX Rate Match FIFO parameters + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] links Target link select + * \param[in] config \ref adi_apollo_rx_rm_fifo_pgm_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_fsrc_rx_rm_fifo_pgm(adi_apollo_device_t *device, const uint16_t links, adi_apollo_rx_rm_fifo_pgm_t *config); + + +/** + * \brief Set the FSRC rate parameters + * + * FSRC rate = (rate_int + rate_frac_a/rate_frac_b)/2^48 + * + * Gain Reduction = round(2^12*M/N) + * + * The FSRC ratio m/n must be between 1 and 2, not inclusive (n > m) + * + * Python code example for generating FSRC parameters + * + * from math import gcd as mathgcd + * from math import floor as mathfloor + * + * def calculate_fsrc_parameters(fsrc_n, fsrc_m): + * """ + * Calculates FSRC Ratio and Gain Settings as per the FSRC User Guide + * :param fsrc_n: int - FSRC Ratio Numerator + * :param fsrc_m: int - FSRC Ratio Denominator + * :return: tuple of int - int, frac_a, frac_b and gain reduction setting + * """ + * p_bits = 48 + * gain_reduction = pow(2, 12) * fsrc_m / fsrc_n + * if fsrc_n == 1 and fsrc_m == 1: + * gain_reduction = pow(2, 12) - 1 + * else: + * gain_reduction = mathfloor(gain_reduction) + * fsrc_rate_int = int(mathfloor((fsrc_m / fsrc_n) * pow(2, p_bits))) + * a = (pow(2, p_bits) * fsrc_m) % fsrc_n + * b = fsrc_n + * gcd_a_b = mathgcd(a, b) + * fsrc_rate_frac_a = a / gcd_a_b + * fsrc_rate_frac_b = b / gcd_a_b + * return fsrc_rate_int, int(fsrc_rate_frac_a), int(fsrc_rate_frac_b), gain_reduction + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] fsrcs Target FSRC \ref adi_apollo_fsrc_sel_e + * \param[in] rate_int rate_int: FSRC rate = (FSRC rate_int + rate_frac_a/rate_frac_b)/2^48 + * \param[in] rate_frac_a rate_frac_a FSRC rate = (FSRC rate_int + rate_frac_a/rate_frac_b)/2^48 + * \param[in] rate_frac_b rate_frac_b FSRC rate = (FSRC rate_int + rate_frac_a/rate_frac_b)/2^48 + * \param[in] gain_red gain_red Gain Reduction = round(2^12*M/N) + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_fsrc_rate_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t fsrcs, + uint64_t rate_int, uint64_t rate_frac_a, uint64_t rate_frac_b, uint16_t gain_red); + +/** + * \brief Configures an FSRC block given n/m parameters. + * + * FSRC ratio is n/m. The ratio must between 1 and 2, inclusive. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] fsrcs Target FSRC \ref adi_apollo_fsrc_sel_e + * \param[in] n Numerator (n > m) + * \param[in] m Denominator (m < n) + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_fsrc_ratio_set(adi_apollo_device_t* device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t fsrcs, uint32_t n, uint32_t m); + + +/** + * \brief Enable or disable FSRC 1x mode + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] fsrcs Target FSRC \ref adi_apollo_fsrc_sel_e + * \param[in] enable 1 to enable 1x mode, 0 disable + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_fsrc_mode_1x_enable_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t fsrcs, uint8_t enable); + +#ifndef CLIENT_IGNORE + +#endif /* CLIENT_IGNORE*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_FSRC_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_fsrc_types.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_fsrc_types.h new file mode 100644 index 00000000000000..2e20571b889dcd --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_fsrc_types.h @@ -0,0 +1,82 @@ +/*! + * \brief FSRC Block definition headers + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_FSRC + * @{ + */ +#ifndef __ADI_APOLLO_FSRC_TYPES_H__ +#define __ADI_APOLLO_FSRC_TYPES_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_cms_api_common.h" +#include "adi_apollo_common.h" + +/*============= D E F I N E S ==============*/ +#define ADI_APOLLO_FSRC_NUM 4 +#define ADI_APOLLO_FSRC_PER_SIDE_NUM 2 + +/*! +* \brief Enumerates FSRC selection +*/ +typedef enum { + ADI_APOLLO_FSRC_NONE = 0x0, /*!< No FSRC */ + ADI_APOLLO_FSRC_A0 = 0x1, /*!< FSRC 0 of SIDE A */ + ADI_APOLLO_FSRC_A1 = 0x2, /*!< FSRC 1 of SIDE A */ + ADI_APOLLO_FSRC_B0 = 0x4, /*!< FSRC 0 of SIDE B */ + ADI_APOLLO_FSRC_B1 = 0x8, /*!< FSRC 1 of SIDE B */ + ADI_APOLLO_FSRC_ALL = 0xF, /*!< All FSRC */ + ADI_APOLLO_FSRC_ALL_4T4R = 0xF /*!< All FSRC 4T4R (same as 8T8R)*/ +} adi_apollo_fsrc_sel_e; + +/*! +* \brief FSRC programming data +*/ +typedef struct { + uint64_t fsrc_rate_int; /*!< A variable of FSRC rate = (FSRC rate_int + rate_frac_a/rate_frac_b)/2^48 */ + uint64_t fsrc_rate_frac_a; /*!< A variable of FSRC rate = (FSRC rate_int + rate_frac_a/rate_frac_b)/2^48 */ + uint64_t fsrc_rate_frac_b; /*!< A variable of FSRC rate = (FSRC rate_int + rate_frac_a/rate_frac_b)/2^48 */ + uint16_t gain_reduction; /*!< Gain Reduction for Decimation */ + uint16_t sample_frac_delay; /*!< This is used to delay the output sample by this fractional delay */ + uint8_t ptr_syncrstval; /*!< This is used for the FIFO pointer value when the internal fifo-sync is generated */ + uint8_t ptr_overwrite; /*!< 1: FIFO reset pointer value is used from regmap; 0: FIFO reset pointer value computed in design */ + uint8_t fsrc_data_mult_dither_en; /*!< If this bit is 1, dither is added into FSRC in the data and delta multiplication calculation */ + uint8_t fsrc_dither_en; /*!< If this bit is 1, dither is added into FSRC in the delta delay calculation */ + uint8_t fsrc_4t4r_split; /*!< If this bit is set FSRC0_1 is enabled. This bit is only to be used for 4T4R two stream use case */ + uint8_t fsrc_bypass; /*!< If this bit is 1, the FSRC is bypassed */ + uint8_t fsrc_en0; /*!< If this bit is 1, FSRC0 is enabled */ + uint8_t fsrc_en1; /*!< If this bit is 1, FSRC1 is enabled */ + uint8_t fsrc_1x_mode; /*!< If this bit is 1, FSRC will be in 1x mode */ +} adi_apollo_fsrc_pgm_t; + +/*! +* \brief FSRC inspect param +*/ +typedef struct { + adi_apollo_fsrc_cfg_t dp_cfg; /*!< Parameters defined from device profile \ref apollo_cpu_device_profile_types.h */ + uint8_t fsrc_bypass; /*!< If this bit is 1, the FSRC is bypassed */ +} adi_apollo_fsrc_inspect_t; + + +/*! +* \brief RX Rate Match FIFO programming data +*/ +typedef struct { + uint16_t dcm_ratio; /*!< Chip Decimation Ratio corresponding to link. The least overall decimation among DDCs present in link */ + uint16_t total_dcm; /*!< Link Total Decimation */ + uint8_t invalid_en; /*!< When Link_TOTAL_DEC is not equal to Chip Decimation , Invalid_en should be 1 to indicate that invalid data can be inserted by the rate match fifo. */ + uint8_t dfor_ddc_dither_en; /*!< Dformat dither enable for DDC mode for link. 0: dformat dither disable, 1: dformat dither enable */ + uint8_t sample_repeat_en; /*!< Sample Repeat Enable. 1:Enable, 0:Disable */ + uint8_t startup_force_inv_en; /*!< If this bit is high and invalid_en bit is also high for that link, + then after the sync (clkgen_sync) till the reconfig_done signal (inside reconfig control), we will transmit invalid samples */ +} adi_apollo_rx_rm_fifo_pgm_t; + + +#endif /* __ADI_APOLLO_FSRC_TYPES_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_gpio.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_gpio.h new file mode 100644 index 00000000000000..d4e0cc7f21959e --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_gpio.h @@ -0,0 +1,210 @@ +/*! + * \brief GPIO definition headers + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_GPIO + * @{ + */ +#ifndef __ADI_APOLLO_GPIO_H__ +#define __ADI_APOLLO_GPIO_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_gpio_types.h" + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief GPIO Quick Config Mode + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] profile Quick Config Profile \ref adi_apollo_gpio_quick_cfg_profile_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_gpio_quick_config_mode_set(adi_apollo_device_t *device, adi_apollo_gpio_quick_cfg_profile_e profile); + +/** + * \brief Configure CMOS GPIO & SYNC pads in CMOS Debug mode + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] gpio_index GPIO num : 0-46 + * 0-30 CMOS GPIO's, 31-46 for SYNC PADS in CMOS Mode + * \param[in] debug_stage Debug Stage sel \ref adi_apollo_gpio_cmos_debug_stage_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_gpio_cmos_debug_mode_set(adi_apollo_device_t *device, uint8_t gpio_index, + adi_apollo_gpio_cmos_debug_stage_e debug_stage); + +/** + * \brief Configure CMOS GPIO & SYNC pads in CMOS Functional mode + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] gpio_index GPIO num : 0-46 + * 0-30 CMOS GPIO's, 31-46 for SYNC PADS in CMOS Mode + * \param[in] func_num Function number to be attached with GPIO + * \ref adi_apollo_gpio_func_e for details. + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_gpio_cmos_func_mode_set(adi_apollo_device_t *device, uint8_t gpio_index, + adi_apollo_gpio_func_e func_num); + +/** + * \brief Configure SYNC pads in CMOS or LVDS mode + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] pad_index Sync pad index \ref adi_apollo_gpio_sync_pad_e for details + * \param[in] mode CMOS or LVDS mode \ref adi_apollo_gpio_sync_pad_mode_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_gpio_sync_pad_cmos_lvds_mode_set(adi_apollo_device_t *device, uint8_t pad_index, + adi_apollo_gpio_sync_pad_mode_e mode); + +/** + * \brief Configure CMOS GPIO & SYNC pads in CMOS GPIO mode + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] gpio_index GPIO num : 0-46 + * 0-30 CMOS GPIO's, 31-46 for SYNC PADS in CMOS Mode + * \param[in] gpio_dir GPIO Direction. \ref adi_apollo_gpio_dir_e for details. + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_gpio_cmos_gpio_mode_set(adi_apollo_device_t *device, uint8_t gpio_index, adi_apollo_gpio_dir_e gpio_dir); + +/** + * \brief Configure SYNC pads in LVDS Debug mode + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] sync_pad SYNC_PAD \ref adi_apollo_gpio_sync_pad_e for details. + * \param[in] debug_func_num Debug Function number to be attached with SYNC PAD + * \ref adi_apollo_gpio_debug_func_e for details + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_gpio_sync_pad_lvds_debug_mode_set(adi_apollo_device_t *device, adi_apollo_gpio_sync_pad_e sync_pad, + adi_apollo_gpio_debug_func_e debug_func_num); + +/** + * \brief Configure SYNC pads in LVDS Functional mode + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] sync_pad SYNC_PAD \ref adi_apollo_gpio_sync_pad_e for details. + * \param[in] func_num Function number to be attached with SYNC PAD.\ref adi_apollo_gpio_func_e for details. + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_gpio_sync_pad_lvds_func_mode_set(adi_apollo_device_t *device, adi_apollo_gpio_sync_pad_e sync_pad, + adi_apollo_gpio_func_e func_num); + +/** + * \brief Sets data to be driven on GPIO pin + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] gpio_index GPIO num : 0-46 + * 0-30 CMOS GPIO's, 31-46 for SYNC PADS in CMOS Mode + * \param[in] gpio_data Data to be written to GPIO + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_gpio_cmos_output_set(adi_apollo_device_t *device, uint8_t gpio_index, uint8_t gpio_data); + +/** + * \brief Reads the data from input GPIO pin + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] gpio_index GPIO num : 0-46 + * 0-30 CMOS GPIO's, 31-46 for SYNC PADS in CMOS Mode + * \param[out] gpio_data Data from GPIO pin + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_gpio_cmos_input_get(adi_apollo_device_t *device, uint8_t gpio_index, uint8_t *gpio_data); + +/** + * \brief Read back the data driven on SYNCIN Pads + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] sync_pad SYNC_PAD \ref adi_apollo_gpio_sync_pad_e for details. + * \param[out] pad_data Data from SYNCIN Pad + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_gpio_sync_pad_lvds_input_get(adi_apollo_device_t *device, adi_apollo_gpio_sync_pad_e sync_pad, + uint8_t *pad_data); + +/** + * \brief Enable(1) / Disable(0) Schmitt trigger in input buffer of GPIOs in CMOS mode. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure. + * \param[in] gpio_index GPIO num : 0-46. + * 0-30 CMOS GPIO's, 31-46 for SYNC PADS in CMOS Mode. + * \param[in] st_enable Enable (1) the schmitt trigger on input buffer or Disable (0). + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_gpio_cmos_st_enable(adi_apollo_device_t *device, uint8_t gpio_index, uint8_t st_enable); + + +/** + * \brief Enable(1) or Disable(0) On-chip 100 Ohm Termination on SYNCIN Pad's receive buffer. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] syncin_pad SYNCIN_PAD index. \ref adi_apollo_gpio_sync_pad_e for details. + * \param[in] termination_enable Enable (1) the termination on receive buffer or Disable (0). + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_gpio_syncin_pad_termination_enable(adi_apollo_device_t *device, adi_apollo_gpio_sync_pad_e syncin_pad, uint8_t termination_enable); + +/** + * \brief Enable(1) or Disable(0) Apollo LVDS pads sync mode + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] sync_pad SYNC_PAD index. \ref adi_apollo_gpio_sync_pad_e for details. + * \param[in] enable Enable (1) the LVDS sync mode or Disable (0). + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_gpio_sync_pad_lvds_enable(adi_apollo_device_t *device, adi_apollo_gpio_sync_pad_e sync_pad, uint8_t enable); + +/** + * \brief Configure GPIO pins for JESD 204B + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_gpio_jesd_204b_configure(adi_apollo_device_t *device); + + +#ifdef __cplusplus +} +#endif + +#endif /*__ADI_APOLLO_GPIO_H__ */ +/*! @} */ \ No newline at end of file diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_gpio_hop.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_gpio_hop.h new file mode 100644 index 00000000000000..e07def7fba367a --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_gpio_hop.h @@ -0,0 +1,340 @@ +/*! + * \brief GPIO select definition headers + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_GPIO + * @{ + */ +#ifndef __ADI_APOLLO_GPIO_HOP_H__ +#define __ADI_APOLLO_GPIO_HOP_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_gpio.h" +#include "adi_apollo_gpio_hop_types.h" +#include "adi_apollo_types.h" + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Set up GPIO profile selection for user-defined gpio configuration (no quick config) + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] profile Profile select struct \ref adi_apollo_gpio_hop_profile_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_gpio_hop_profile_configure(adi_apollo_device_t *device, const adi_apollo_gpio_hop_profile_t *profile); + +/** + * \brief GPIO profile select bit calculation + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] config Profile select struct \ref adi_apollo_gpio_hop_profile_t + * \param[in] profile Profile number to select + * \param[out] mask GPIO mask to set + * \param[out] value GPIO values if corresponding bit in mask is set + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_gpio_hop_profile_calc(adi_apollo_device_t *device, const adi_apollo_gpio_hop_profile_t *config, uint8_t profile, uint64_t *mask, uint64_t *value); + +/** + * \brief GPIO profile select bit calculation for given quick config + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] config Quick config profile (valid 1234568) \ref adi_apollo_gpio_quick_cfg_profile_e + * \param[in] profile Profile number to select + * \param[out] mask GPIO mask to set + * \param[out] value GPIO values if corresponding bit in mask is set + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_gpio_hop_profile_qc_calc(adi_apollo_device_t *device, adi_apollo_gpio_quick_cfg_profile_e config, uint8_t profile, uint64_t *mask, uint64_t *value); + + +/** + * \brief Set up GPIO block selection for user-defined gpio configuration (no quick config) + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] config Block select struct \ref adi_apollo_gpio_hop_block_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_gpio_hop_block_configure(adi_apollo_device_t *device, const adi_apollo_gpio_hop_block_t *config); + +/** + * \brief GPIO block select bit calculation + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] config Block select struct \ref adi_apollo_gpio_hop_block_t + * \param[in] block Blocks to select \ref adi_apollo_gpio_hop_block_e + * \param[out] mask GPIO mask to set + * \param[out] value GPIO values if corresponding bit in mask is set + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_gpio_hop_block_calc(adi_apollo_device_t *device, const adi_apollo_gpio_hop_block_t *config, adi_apollo_gpio_hop_block_e block, uint64_t *mask, uint64_t *value); + +/** + * \brief GPIO block select bit calculation for given quick config + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] config Quick config profile (valid 123458) \ref adi_apollo_gpio_quick_cfg_profile_e + * \param[in] block Blocks to select \ref adi_apollo_gpio_hop_block_e + * \param[out] mask GPIO mask to set + * \param[out] value GPIO values if corresponding bit in mask is set + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_gpio_hop_block_qc_calc(adi_apollo_device_t *device, adi_apollo_gpio_quick_cfg_profile_e config, adi_apollo_gpio_hop_block_e block, uint64_t *mask, uint64_t *value); + +/** + * \brief Set up GPIO side selection for user-defined gpio configuration (no quick config) + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] config Side select struct \ref adi_apollo_gpio_hop_side_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_gpio_hop_side_configure(adi_apollo_device_t *device, const adi_apollo_gpio_hop_side_t *config); + +/** + * \brief GPIO side select bit calculation + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] config Side select struct \ref adi_apollo_gpio_hop_side_t + * \param[in] side Sides to select \ref adi_apollo_side_select_e + * \param[out] mask GPIO mask to set + * \param[out] value GPIO values if corresponding bit in mask is set + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_gpio_hop_side_calc(adi_apollo_device_t *device, const adi_apollo_gpio_hop_side_t *config, adi_apollo_side_select_e side, uint64_t *mask, uint64_t *value); + +/** + * \brief GPIO side select bit calculation for given quick config + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] config Quick config profile (valid 12458) \ref adi_apollo_gpio_quick_cfg_profile_e + * \param[in] side Sides to select \ref adi_apollo_side_select_e + * \param[out] mask GPIO mask to set + * \param[out] value GPIO values if corresponding bit in mask is set + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_gpio_hop_side_qc_calc(adi_apollo_device_t *device, adi_apollo_gpio_quick_cfg_profile_e config, adi_apollo_side_select_e side, uint64_t *mask, uint64_t *value); + +/** + * \brief Set up GPIO slice selection for user-defined gpio configuration (no quick config) + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] config Slice select struct \ref adi_apollo_gpio_hop_slice_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_gpio_hop_slice_configure(adi_apollo_device_t *device, const adi_apollo_gpio_hop_slice_t *config); + +/** + * \brief GPIO slice select bit calculation + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] config Slice select struct \ref adi_apollo_gpio_hop_slice_t + * \param[in] slice Slice number + * \param[out] mask GPIO mask to set + * \param[out] value GPIO values if corresponding bit in mask is set + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_gpio_hop_slice_calc(adi_apollo_device_t *device, const adi_apollo_gpio_hop_slice_t *config, uint8_t slice, uint64_t *mask, uint64_t *value); + +/** + * \brief GPIO slice select bit calculation for given quick config + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] config Quick config profile (valid 12458) \ref adi_apollo_gpio_quick_cfg_profile_e + * \param[in] slice Slice number + * \param[out] mask GPIO mask to set + * \param[out] value GPIO values if corresponding bit in mask is set + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_gpio_hop_slice_qc_calc(adi_apollo_device_t *device, adi_apollo_gpio_quick_cfg_profile_e config, uint8_t slice, uint64_t *mask, uint64_t *value); + +/** + * \brief Set up GPIO terminal selection for user-defined gpio configuration (no quick config) + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] config Slice select struct \ref adi_apollo_gpio_hop_terminal_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_gpio_hop_terminal_configure(adi_apollo_device_t *device, const adi_apollo_gpio_hop_terminal_t *config); + +/** + * \brief GPIO terminal select bit calculation + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] config Terminal select struct \ref adi_apollo_gpio_hop_terminal_t + * \param[in] terminal Terminal \ref adi_apollo_gpio_hop_terminal_e + * \param[out] mask GPIO mask to set + * \param[out] value GPIO values if corresponding bit in mask is set + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_gpio_hop_terminal_calc(adi_apollo_device_t *device, const adi_apollo_gpio_hop_terminal_t *config, adi_apollo_gpio_hop_terminal_e terminal, uint64_t *mask, uint64_t *value); + +/** + * \brief GPIO terminal select bit calculation for given quick config + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] config Quick config profile (valid 1234568) \ref adi_apollo_gpio_quick_cfg_profile_e + * \param[in] terminal Terminal \ref adi_apollo_gpio_hop_terminal_e + * \param[out] mask GPIO mask to set + * \param[out] value GPIO values if corresponding bit in mask is set + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_gpio_hop_terminal_qc_calc(adi_apollo_device_t *device, adi_apollo_gpio_quick_cfg_profile_e config, adi_apollo_gpio_hop_terminal_e terminal, uint64_t *mask, uint64_t *value); + +/** + * \brief GPIO/SPI select for block profile hopping + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] select Hopping select \ref adi_apollo_gpio_hop_select_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_gpio_hop_block_select_set(adi_apollo_device_t *device, adi_apollo_gpio_hop_select_e select); + +/** + * \brief Block set for profile hopping (block_select must be set to SPI) + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] block Blocks to select \ref adi_apollo_gpio_hop_block_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_gpio_hop_block_set(adi_apollo_device_t *device, adi_apollo_gpio_hop_block_e block); + +/** + * \brief GPIO/SPI select for slice profile hopping. If SPI, overrides GPIO select for slice, side, and terminal. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] block Target block \ref adi_apollo_gpio_hop_block_e + * \param[in] select Hopping select \ref adi_apollo_gpio_hop_select_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_gpio_hop_slice_select_set(adi_apollo_device_t *device, adi_apollo_gpio_hop_block_e block, adi_apollo_gpio_hop_select_e select); + +/** + * \brief Enable hopping for selected FNCOs (slice_select must be set to SPI) + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] fncos FNCOs to select \ref adi_apollo_fnco_select_e + * \param[in] enable Hopping enable + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_gpio_hop_fnco_enable_set(adi_apollo_device_t *device, uint32_t terminal, uint32_t fncos, uint8_t enable); + +/** + * \brief Enable hopping for selected CNCOs (slice_select must be set to SPI) + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] cncos CNCOs to select \ref adi_apollo_cnco_select_e + * \param[in] enable Hopping enable + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_gpio_hop_cnco_enable_set(adi_apollo_device_t *device, uint32_t terminal, uint32_t cncos, uint8_t enable); + +/** + * \brief Enable hopping for selected CFIR datapaths (slice_select must be set to SPI) + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] cfirs CFIRs to select \ref adi_apollo_cfir_select_e + * \param[in] paths CFIR datapaths to select \ref adi_apollo_cfir_dp_sel + * \param[in] enable Hopping enable + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_gpio_hop_cfir_enable_set(adi_apollo_device_t *device, uint32_t terminal, uint32_t cfirs, uint32_t paths, uint8_t enable); + +/** + * \brief Enable hopping for selected PFILTs (slice_select must be set to SPI) + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] sides Sides to select \ref adi_apollo_side_select_e + * \param[in] enable Hopping enable + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_gpio_hop_pfilt_enable_set(adi_apollo_device_t *device, uint32_t terminal, uint32_t sides, uint8_t enable); + +/** + * \brief Enable hopping for selected reconfig blocks (slice_select must be set to SPI) + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] fdrcs FDRCs to select \ref adi_apollo_reconfig_select_e + * \param[in] enable Hopping enable + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_gpio_hop_dynamic_config_enable_set(adi_apollo_device_t *device, uint32_t terminal, uint32_t fdrcs, uint8_t enable); + +/** + * \brief Enable hopping for selected BMEMs (delay mode only) (slice_select must be set to SPI) + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] bmems Target BMEMs \ref adi_apollo_bmem_sel_e + * \param[in] enable Hopping enable + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_gpio_hop_bmem_delay_enable_set(adi_apollo_device_t *device, uint32_t bmems, uint8_t enable); + +#ifdef __cplusplus +} +#endif + +#endif /*__ADI_APOLLO_GPIO_HOP_H__ */ +/*! @} */ \ No newline at end of file diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_gpio_hop_types.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_gpio_hop_types.h new file mode 100644 index 00000000000000..14e4a9e0ee69ae --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_gpio_hop_types.h @@ -0,0 +1,106 @@ +/*! + * \brief API header file + * This file contains all the publicly exposed methods and data + * structures to interface with API. + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_GPIO + * @{ + */ + +#ifndef __ADI_APOLLO_GPIO_HOP_TYPES_H__ +#define __ADI_APOLLO_GPIO_HOP_TYPES_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_cms_api_common.h" +#include "adi_apollo_common.h" + +/*============= D E F I N E S ==============*/ + +#define ADI_APOLLO_GPIO_HOP_PROFILE_BIT_NUMBER 5 +#define ADI_APOLLO_GPIO_HOP_BLOCK_BIT_NUMBER 4 +#define ADI_APOLLO_GPIO_HOP_SIDE_BIT_NUMBER 1 +#define ADI_APOLLO_GPIO_HOP_SLICE_BIT_NUMBER 3 +#define ADI_APOLLO_GPIO_HOP_TERMINAL_BIT_NUMBER 2 + +#define ADI_APOLLO_GPIO_HOP_IDX_NONE -1 /*!< Use to indicate that a gpio bit is not to be used. I.e. pfilt profile needs only 2 bits, [26, 27, -1, -1, -1] */ + +/*! +* \brief Enumerates Tx/Rx hop parameter selection +*/ +typedef enum { + ADI_APOLLO_GPIO_HOP_TX = 0x0, /*!< TX TERMINAL SIGNAL PATH*/ + ADI_APOLLO_GPIO_HOP_RX = 0x1, /*!< RX TERMINAL SIGNAL PATH */ + ADI_APOLLO_GPIO_HOP_TXRX = 0x2, /*!< RX AND TX TERMINAL SIGNAL PATH */ +} adi_apollo_gpio_hop_terminal_e; + +/*! +* \brief Enumerates GPIO select blocks +*/ +typedef enum { + ADI_APOLLO_GPIO_BLOCK_FNCO = 0, + ADI_APOLLO_GPIO_BLOCK_CNCO = 1, + ADI_APOLLO_GPIO_BLOCK_FNCO_CNCO = 2, + ADI_APOLLO_GPIO_BLOCK_PFILT = 3, + ADI_APOLLO_GPIO_BLOCK_CNCO_PFILT = 4, + ADI_APOLLO_GPIO_BLOCK_FNCO_CFIR = 5, + ADI_APOLLO_GPIO_BLOCK_FDDC = 6, + ADI_APOLLO_GPIO_BLOCK_BMEM_DELAY = 7, + ADI_APOLLO_GPIO_BLOCK_CFIR = 8, + ADI_APOLLO_GPIO_BLOCK_FNCO_PFILT = 9, + ADI_APOLLO_GPIO_BLOCK_PFILT_CFIR = 10, + ADI_APOLLO_GPIO_BLOCK_CDDC = 11, + ADI_APOLLO_GPIO_BLOCK_LINX = 12 +} adi_apollo_gpio_hop_block_e; + +/*! +* \brief Enumerates SPI/GPIO hop parameter selection +*/ +typedef enum { + ADI_APOLLO_GPIO_HOP_SELECT_GPIO = 0, + ADI_APOLLO_GPIO_HOP_SELECT_SPI = 1 +} adi_apollo_gpio_hop_select_e; + +/*! +* \brief GPIO profile select +*/ +typedef struct { + uint8_t index[ADI_APOLLO_GPIO_HOP_PROFILE_BIT_NUMBER]; /*!< GPIO indexes for profile select bits */ +} adi_apollo_gpio_hop_profile_t; + +/*! +* \brief GPIO block select +*/ +typedef struct { + uint8_t index[ADI_APOLLO_GPIO_HOP_BLOCK_BIT_NUMBER]; /*!< GPIO indexes for block select bits */ +} adi_apollo_gpio_hop_block_t; + +/*! +* \brief GPIO side select +*/ +typedef struct { + uint8_t index[ADI_APOLLO_GPIO_HOP_SIDE_BIT_NUMBER]; /*!< GPIO indexes for side select bits */ +} adi_apollo_gpio_hop_side_t; + +/*! +* \brief GPIO slice select +*/ +typedef struct { + uint8_t index[ADI_APOLLO_GPIO_HOP_SLICE_BIT_NUMBER]; /*!< GPIO indexes for slice select bits */ +} adi_apollo_gpio_hop_slice_t; + +/*! +* \brief GPIO terminal select +*/ +typedef struct { + uint8_t index[ADI_APOLLO_GPIO_HOP_TERMINAL_BIT_NUMBER]; /*!< GPIO indexes for terminal select bits */ +} adi_apollo_gpio_hop_terminal_t; + +#endif /* __ADI_APOLLO_GPIO_HOP_TYPES_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_gpio_types.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_gpio_types.h new file mode 100644 index 00000000000000..ece99d14afd6e1 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_gpio_types.h @@ -0,0 +1,283 @@ +/*! + * \brief API header file + * This file contains all the publicly exposed methods and data + * structures to interface with API. + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_GPIO + * @{ + */ + +#ifndef __ADI_APOLLO_GPIO_TYPES_H__ +#define __ADI_APOLLO_GPIO_TYPES_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_cms_api_common.h" +#include "adi_apollo_common.h" + +/*============= D E F I N E S ==============*/ +#define ADI_APOLLO_NUM_CMOS_GPIO 35 /*! [34:00] */ +#define ADI_APOLLO_NUM_GPIO 51 /*! [50:35] */ + +/*! +* \brief Enumerates Sync Pads +*/ +typedef enum { + ADI_APOLLO_SYNCINB0_B = 35, /*! +#include +#endif + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Get bit field value. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] reg register to read from + * \param[in] info information about bitfield + * \param[out] value value of bitfield + * \param[in] value_size_bytes no of bytes + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_hal_bf_get(adi_apollo_device_t *device, uint32_t reg, uint32_t info, uint8_t value[], uint8_t value_size_bytes); + +/** + * \brief Set bit field value. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] reg register to read from + * \param[in] info information about bitfield + * \param[in] value value of bitfield + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_hal_bf_set(adi_apollo_device_t *device, uint32_t reg, uint32_t info, uint64_t value); + +/** + * \brief Set register value based on a mask + * + * \param[in] device Context variable - Pointer to the device structure + * \param[in] reg Register write + * \param[in] data Value to write to register + * \param[in] mask Bitfield mask. Only bits set in the mask will be written to register + * + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_hal_masked_reg_set(adi_apollo_device_t *device, uint32_t reg, uint8_t data, uint8_t mask); + +/** + * \brief Set paged register value based on a mask + * + * \param[in] device Context variable - Pointer to the device structure + * \param[in] reg Register write + * \param[in] data Value to write to register + * \param[in] mask Bitfield mask. Only bits set in the mask will be written to register + * + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_hal_paged_masked_reg_set(adi_apollo_device_t *device, uint32_t reg, uint8_t data, uint8_t mask); + +/** + * \brief Get 8-bit register value. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] reg Register to read from + * \param[out] data Value of register (8-bit) + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_hal_reg_get(adi_apollo_device_t *device, uint32_t reg, uint8_t *data); + +/** + * \brief Get 32-bit register value. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] reg Register to read from + * \param[out] data Value of register (32-bit) + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_hal_reg32_get(adi_apollo_device_t *device, uint32_t reg, uint32_t *data); + +/** + * \brief Set the 8-bit register value. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] reg Register to write to + * \param[in] data Value to write to register + * + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_hal_reg_set(adi_apollo_device_t *device, uint32_t reg, uint8_t data); + +/** + * \brief Set the 32-bit register value. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] reg Register to write to + * \param[in] data Value to write to register + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_hal_reg32_set(adi_apollo_device_t *device, uint32_t reg, uint32_t data); + +/** + * \brief Get the register value for a polling operation. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] reg Register to read from + * \param[out] data Value of register (8-bits) + * \param[in] timeout_us Suggested timeout value from API (usecs) + * \param[in] reg_expect Typical register exp (not masked) + * \param[in] reg_mask Bitfield register mask + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_hal_reg_poll_get(adi_apollo_device_t *device, uint32_t reg, uint8_t *data, uint32_t timeout_us, uint8_t reg_expect, uint8_t reg_mask); + + + +/** + * \brief Sets the page base address for subsequent paged register accesses. + * + * This function sets up the base address used for paged register access. + * + * The following APIs are affected: + * \ref adi_apollo_hal_paged_reg_set + * \ref adi_apollo_hal_paged_reg32_set + * \ref adi_apollo_hal_paged_bf_set + * + * \note Paging is only valid for writes. Device doesn't support paging reads. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] base_addr Page base address + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_hal_paged_base_addr_set(adi_apollo_device_t *device, uint32_t base_addr); + +/** + * \brief Set the 8-bit register value offset from the page base address. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] reg Register to write. \ref adi_apollo_hal_paged_base_addr_set + * \param[in] data Value to write to register + * + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_hal_paged_reg_set(adi_apollo_device_t *device, uint32_t reg, uint8_t data); + + +/** + * \brief Set the 32-bit register value offset from the page base address. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] reg Register to write, offset from the paged base address. \ref adi_apollo_hal_paged_base_addr_set + * \param[in] data Value to write to register + * + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_hal_paged_reg32_set(adi_apollo_device_t *device, uint32_t reg, uint32_t data); + +/** + * \brief 8-bit register stream writes. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] reg Start address register to write + * \param[in] data Data array to write to the register + * \param[in] data_len_bytes Total number of bytes to stream + * \param[in] is_cont Flag to decide if stream is continuous to previous txn + * + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_hal_stream_reg_set(adi_apollo_device_t *device, uint32_t reg, uint8_t data[], uint32_t data_len_bytes, uint8_t is_cont); + +/** + * \brief 32-bit register stream writes. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] reg Start address register to write + * \param[in] data Data array to write to the register + * \param[in] data_len_words Total number of words to stream + * \param[in] is_cont Flag to decide if stream is continuous to previous txn + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_hal_stream_reg32_set(adi_apollo_device_t *device, uint32_t reg, uint32_t data[], uint32_t data_len_words, uint8_t is_cont); + +/** + * \brief 8-bit register stream read. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] reg Start address register to read + * \param[out] data Data array read from start address reg + * \param[in] data_len_bytes Total number of bytes to stream + * \param[in] is_cont Flag to decide if stream is continuous to previous txn + * + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_hal_stream_reg_get(adi_apollo_device_t *device, uint32_t reg, uint8_t data[], uint32_t data_len_bytes, uint8_t is_cont); + +/** + * \brief 32-bit register stream read. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] reg Start address register to read + * \param[out] data Data array read from start address reg + * \param[in] data_len_words Total number of bytes to stream + * \param[in] is_cont Flag to decide if stream is continuous to previous txn + * + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_hal_stream_reg32_get(adi_apollo_device_t *device, uint32_t reg, uint32_t data[], uint32_t data_len_words, uint8_t is_cont); + +/** + * \brief Set bit field value using paged register addressing. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] reg Register to write. \ref adi_apollo_hal_paged_base_addr_set + * \param[in] info Information about bitfield + * \param[in] value Value of bitfield + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_hal_paged_bf_set(adi_apollo_device_t *device, uint32_t reg, uint32_t info, uint64_t value); + +/** + * \brief Sets the active protocol for API + * + * This function changes the active protocol used for register access. If the platform + * supports multiple protocols, then realtime switching is possible. For example, one + * can switch between SPI0 and HSCI by calling this function. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] protocol Selects to active protocol for API register access. \ref adi_apollo_hal_protocol_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_hal_active_protocol_set(adi_apollo_device_t *device, adi_apollo_hal_protocol_e protocol); + +/** + * \brief Gets the active protocol for API + * + * This function returns the active protocol used for register access. If the platform + * supports multiple protocols, then realtime switching is possible. For example, one + * can switch between SPI0 and HSCI by calling the \ref adi_apollo_hal_active_protocol_set function. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[out] protocol Active protocol for API register access. \ref adi_apollo_hal_protocol_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_hal_active_protocol_get(adi_apollo_device_t *device, adi_apollo_hal_protocol_e *protocol); + +/** + * \brief Enable the read-modify-write feature for bit field writes. + * + * Apollo supports a hardware read-modify-write feature that eliminates + * the need to first read a register (e.g from spi) when modifying a bitfield within a register. + * + * \note It is recommended that r-m-w is enabled for optimal register transacton performance. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] protocol Selects to active protocol for API register access. \ref adi_apollo_hal_protocol_e + * \param[in] rmw_en 0 = disable rmw, 1 = enable rmw + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_hal_rmw_enable_set(adi_apollo_device_t *device, adi_apollo_hal_protocol_e protocol, uint8_t rmw_en); + +/** + * \brief Returns the read-modify-write feature enable state. + * + * Apollo supports a hardware read-modify-write feature that eliminates + * the need to first read a register (e.g from spi) when modifying a bitfield within a register. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] protocol Selects to active protocol for API register access. \ref adi_apollo_hal_protocol_e + * \param[out] rmw_en 0 = disable rmw, 1 = enable rmw + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_hal_rmw_enable_get(adi_apollo_device_t *device, adi_apollo_hal_protocol_e protocol, uint8_t *rmw_en); + +/** + * \brief Configuring the manual link-up operation + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] enable Set 1 to enable manual link-up + * \param[in] link_up_signal_bits Clock signal used to achieve linkup + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_hal_manual_linkup(adi_apollo_device_t *device, uint8_t enable, uint16_t link_up_signal_bits); + +/** + * \brief Configuring the auto link-up operation + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] enable Set 1 to enable auto link-up + * \param[in] hscim_mosi_clk_inv Set 1, inverts HSCIM's mosi_clk output clk to Apollo + * \param[in] hscim_miso_clk_inv Set 1, inverts HSCIM's miso_clk input clk from Apollo + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_hal_auto_linkup(adi_apollo_device_t *device, uint8_t enable, uint8_t hscim_mosi_clk_inv, uint8_t hscim_miso_clk_inv); + +/** + * \brief Get the HSCIM auto link_table + * \note Retrive HSCIM ALINK_TABLE after Apollo's link_active is set + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] enable Set 1 to enable auto link-up + * \param[out] hscim_alink_table Pointer to a variable that stores link table value from HSCI_M + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_hal_alink_tbl_get(adi_apollo_device_t *device, uint16_t *hscim_alink_table); + +#ifndef CLIENT_IGNORE + +/** + * \brief Calls the platform hw_open function + * + * \note hw_open is optional. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_hal_hw_open(adi_apollo_device_t *device); + +/** + * \brief Calls the platform hw_close function + * + * \note hw_open is optional. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_hal_hw_close(adi_apollo_device_t *device); + +/** + * \brief Calls the platform delay_us function + * + * \note delay_us is required. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] us Delay in micro seconds + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_hal_delay_us(adi_apollo_device_t *device, uint32_t us); + + +/** + * \brief Calls the platform reset_pin_ctrl function + * + * \note reset_pin_ctrl is required. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] enable 0 = disable, 1 = enable + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_hal_reset_pin_ctrl(adi_apollo_device_t *device, uint8_t enable); + + +/** + * \brief Calls the platform log_write function + * + * \note log_write is optional. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] type Type of log message. \ref adi_cms_log_type_e + * \param[in] comment Comment string + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_hal_log_write(adi_apollo_device_t *device, adi_cms_log_type_e type, const char* comment, ...); + +/** + * \brief Wait for a bitfield to clear + * + * \note Supports single bit bit-field only. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] reg Register to read from + * \param[in] info Information about bitfield + * \param[in] timeout Timeout in us + * \param[in] poll_dly Polling delay in us + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_hal_bf_wait_to_clear(adi_apollo_device_t *device, uint32_t reg, uint32_t info, uint32_t timeout, uint32_t poll_dly); + +/** + * \brief Wait for a bitfield to set + * + * \note Supports single bit bit-field only. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] reg Register to read from + * \param[in] info Information about bitfield +* \param[in] timeout Timeout in us + * \param[in] poll_dly Polling delay in us + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_hal_bf_wait_to_set(adi_apollo_device_t *device, uint32_t reg, uint32_t info, uint32_t timeout, uint32_t poll_dly); + +/** + * \brief Creates formatted log error message. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] log_type Log type. See \ref adi_cms_log_type_e + * \param[in] error Error code + * \param[in] file_name Name for file where error occurred + * \param[in] func_name Name of function where error occurred + * \param[in] line_num Line number in files where error occurred + * \param[in] var_name Variable name + * \param[in] comment Comment string + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_hal_error_report(adi_apollo_device_t* device, adi_cms_log_type_e log_type, + int32_t error, const char* file_name, const char* func_name, uint32_t line_num, + const char* var_name, const char* comment); + +/** + * \brief Assigns user allocated memory for use by HAL APIs + * + * \note Currently only applicable for HSCI protocol + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] protocol Protocol to assign buffer to. See \ref adi_apollo_hal_protocol_e + * \param[in] buff Pointer to user allocated memory + * \param[in] buff_len Nummber of bytes in 'buff'. Max 32K, Min 128 + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_hal_buffer_set(adi_apollo_device_t* device, adi_apollo_hal_protocol_e protocol, uint8_t *buff, uint32_t buff_len); + +/** + * \brief Gets pointer to user allocated memory that is used by API for various transactions + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] protocol Protocol to get buffer from. See \ref adi_apollo_hal_protocol_e + * \param[out] buff Pointer to user allocated memory + * \param[out] buff_len Nummber of bytes in 'buff'. + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_hal_buffer_get(adi_apollo_device_t* device, adi_apollo_hal_protocol_e protocol, uint8_t **buff, uint32_t *buff_len); + +#endif /* CLIENT_IGNORE*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __APOLLO_REG_H__ */ + +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_hal_regio.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_hal_regio.h new file mode 100644 index 00000000000000..a8f95f5d796282 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_hal_regio.h @@ -0,0 +1,41 @@ +/*! + * \brief Contains abstract hal register io definitions + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_HAL + * @{ + */ + +#ifndef __ADI_APOLLO_HAL_REGIO_H__ +#define __ADI_APOLLO_HAL_REGIO_H__ + +#include "adi_cms_api_common.h" +#include "adi_apollo_hal_types.h" + +#define ADI_APOLLO_HAL_SWAP32(w) (((w)>>24)&0xff) | (((w)<<8)&0xff0000) | (((w)>>8)&0xff00) | (((w)<<24)&0xff000000) + +#ifndef CLIENT_IGNORE +/*! + * \brief Abstract register I/O struct def. + */ +typedef struct { + adi_apollo_hal_protocol_e protocol_id; /*!< Indicates protocol type \ref adi_apollo_hal_protocol_e */ + uint8_t supports_paging; /*!< Indicates of paging is supported */ + uint8_t rmw_enabled; /*!< Indicates if read-modify-write feature should be used */ + uint8_t poll_read_en; /*!< Indicates if poll reads are enabled */ + uint8_t poll_read_returns_val; /*!< Indicates if a polling read returns an actual value. */ + + void *child_desc; /*!< Pointer to specific protocol type descriptor (e.g. spi0, spi1, hsci) */ + void *ops; /*!< Container for protocol specific regio implementations */ +} adi_apollo_hal_regio_t; +#endif /* CLIENT_IGNORE*/ + +#endif /* __ADI_APOLLO_HAL_REGIO_H__ */ + +/*! @} */ \ No newline at end of file diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_hal_regio_hsci_types.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_hal_regio_hsci_types.h new file mode 100644 index 00000000000000..77403ac264525d --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_hal_regio_hsci_types.h @@ -0,0 +1,69 @@ +/*! + * \brief Contains hsci hal register io types + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_HAL + * @{ + */ + +#ifndef __ADI_APOLLO_HAL_REGIO_HSCI_TYPES_H__ +#define __ADI_APOLLO_HAL_REGIO_HSCI_TYPES_H__ + +#include "adi_cms_api_common.h" +#include "adi_apollo_hal_regio.h" + +#define ADI_APOLLO_HAL_REGIO_HSCI_NO_MASK 0 + +/* Default payload buffer size in case no optional buffer is provided for stream_read and stream_write and multiple of 4 */ +#define ADI_APOLLO_HAL_REGIO_HSCI_STREAM_DEFAULT_PAYLOAD_SIZE (32760U) +/* 4 Bytes header overhead to stream bytes*/ +#define ADI_APOLLO_HAL_REGIO_HSCI_STREAM_HEADER_OVERHEAD (4U) +/* Default total buffer size in case no optional buffer is provided for stream_read and stream_write and multiple of 4 */ +#define ADI_APOLLO_HAL_REGIO_HSCI_STREAM_DEFAULT_SIZE (ADI_APOLLO_HAL_REGIO_HSCI_STREAM_DEFAULT_PAYLOAD_SIZE + ADI_APOLLO_HAL_REGIO_HSCI_STREAM_HEADER_OVERHEAD) + +/*! + * \brief HSCI transaction data size + */ +typedef enum { + ADI_APOLLO_HAL_REGIO_HSCI_BUS_SIZE_D8 = 0, + ADI_APOLLO_HAL_REGIO_HSCI_BUS_SIZE_D16 = 1, + ADI_APOLLO_HAL_REGIO_HSCI_BUS_SIZE_D32 = 2, +} adi_apollo_hal_regio_hsci_bus_size_e; + +#ifndef CLIENT_IGNORE +/*! + * \brief HSCI register I/O descriptor + */ +typedef struct { + uint8_t is_used; /*!< 0 = protocol block not used (default), 1 = is used */ + + /* These functions are supplied by the customer platform driver */ + adi_apollo_hal_init_t init; /*!< Platform init function ptr. \ref adi_apollo_hal_init_t */ + adi_apollo_hal_xfer_t xfer; /*!< Platform rd/wr transaction function ptr. \ref adi_apollo_hal_xfer_t */ + adi_apollo_hal_write_t write; /*!< Platform write transaction function ptr. \ref adi_apollo_hal_write_t */ + adi_apollo_hal_read_t read; /*!< Platform read transaction function ptr. \ref adi_apollo_hal_read_t */ + adi_apollo_hal_poll_read_t poll_read; /*!< Platform poll read transaction function ptr. \ref adi_apollo_hal_poll_read_t */ + adi_apollo_hal_manual_linkup_t manual_linkup; /*!< Platform manual linkup transaction function ptr. \ref adi_apollo_hal_manual_linkup_t */ + adi_apollo_hal_auto_linkup_t auto_linkup; /*!< Platform auto linkup transaction function ptr. \ref adi_apollo_hal_auto_linkup_t */ + adi_apollo_hal_alink_tbl_get_t alink_tbl_get; /*!< Platform auto link_table get function ptr. \ref adi_apollo_hal_alink_tbl_get_t */ + + adi_apollo_device_hsci_settings_t hsci_config; /*!< Device hsci settings. \ref adi_apollo_device_hsci_settings_t */ + void *dev_obj; /*!< Platform defined object */ + + /* Internal API fields */ + adi_apollo_hal_regio_t base_regio; /*!< Pointer to base register I/O */ + + uint8_t *buff; /*!< User allocated memory for stream transaction usage. */ + uint32_t buff_len; /*!< Length of allocated memory for stream transaction usage. */ +} adi_apollo_hal_regio_hsci_desc_t; +#endif /* CLIENT_IGNORE*/ + +#endif /* __ADI_APOLLO_HAL_REGIO_HSCI_TYPES_H__ */ + +/*! @} */ \ No newline at end of file diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_hal_regio_spi_types.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_hal_regio_spi_types.h new file mode 100644 index 00000000000000..a4a77cb0b274cb --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_hal_regio_spi_types.h @@ -0,0 +1,81 @@ +/*! + * \brief Contains spi hal register io types + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_HAL + * @{ + */ + +#ifndef __ADI_APOLLO_HAL_REGIO_SPI_TYPES_H__ +#define __ADI_APOLLO_HAL_REGIO_SPI_TYPES_H__ + +#include "adi_cms_api_common.h" +#include "adi_apollo_hal_types.h" +#include "adi_apollo_device_types.h" +#include "adi_apollo_hal_regio.h" + +#define ADI_APOLLO_DIRECT_SPI_REGION_LEN 0x4000ul + +/*! + * \brief SPI transaction data size + */ +typedef enum { + ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D8 = 0, + ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D16 = 1, + ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D32 = 2 +} adi_apollo_hal_regio_spi_bus_size_e; + +#ifndef CLIENT_IGNORE +typedef struct { + uint8_t enabled; + uint8_t valid; +} adi_apollo_hal_regio_spi_base_addr_cache_t; + +typedef struct { + uint8_t dma_ctrl; + uint8_t addr3; + uint8_t addr2; + uint8_t addr1; + /* There is no point caching addr0 byte as this is always required + * to be written in order to latch in the new DMA addr. */ + uint8_t valid; + uint8_t enabled; +} adi_apollo_hal_regio_spi_indir_cache_t; + +/*! + * \brief SPI register I/O descriptor + */ +typedef struct { + uint8_t is_used; /*!< 0 = protocol block not used (default), 1 = is used */ + uint8_t is_spi1; /*!< Indicates spi instance: 0 = spi0, 1 = spi1 */ + uint8_t rd_stream_en; /*!< Enable rd streaming transactions by API. 0 = disable, 1 = enable */ + uint8_t wr_stream_en; /*!< Enable wr streaming transactions by API. 0 = disable, 1 = enable */ + + /* These functions are supplied by the customer platform driver */ + adi_apollo_hal_init_t init; /*!< Platform init function ptr. \ref adi_apollo_hal_init_t */ + adi_apollo_hal_xfer_t xfer; /*!< Platform rd/wr transaction function ptr. \ref adi_apollo_hal_xfer_t */ + adi_apollo_hal_write_t write; /*!< Platform write transaction function ptr. \ref adi_apollo_hal_write_t */ + adi_apollo_hal_read_t read; /*!< Platform read transaction function ptr. \ref adi_apollo_hal_read_t */ + adi_apollo_hal_poll_read_t poll_read; /*!< Platform poll read transaction function ptr. \ref adi_apollo_hal_poll_read_t */ + + adi_apollo_device_spi_settings_t spi_config; /*!< Device spi settings. \ref adi_apollo_device_spi_settings_t */ + void *dev_obj; /*!< Platform defined object for SPI instance */ + + /* Internal API fields */ + adi_apollo_hal_regio_t base_regio; /*!< Base HAL register I/O */ + uint32_t page_base_addr; /*!< Current SPI page base address */ + adi_apollo_hal_regio_spi_base_addr_cache_t base_addr_cache; /*!< Byte-level cache of SPI paged access addr */ + adi_apollo_hal_regio_spi_indir_cache_t indir_cache; /*!< Byte-level cache of SPI indirect (aka DMA) addr */ + adi_apollo_hal_txn_config_t txn_config; /*!< Transaction info passed to HAL read/write functions */ +} adi_apollo_hal_regio_spi_desc_t; +#endif /* CLIENT_IGNORE*/ + +#endif /* __ADI_APOLLO_HAL_REGIO_SPI_TYPES_H__ */ + +/*! @} */ \ No newline at end of file diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_hal_types.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_hal_types.h new file mode 100644 index 00000000000000..8ebc286e853ed2 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_hal_types.h @@ -0,0 +1,232 @@ +/*! + * \brief HAL API type definition headers + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_HAL + * @{ + */ +#ifndef __ADI_APOLLO_HAL_TYPES_H__ +#define __ADI_APOLLO_HAL_TYPES_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_cms_api_common.h" + +/*============= D E F I N E S ==============*/ + +/* Max len for addresss supported for either SPI or HSCI transactions */ +#define ADI_APOLLO_HAL_BUFFER_LEN_HSCI_ADDR (4U) +/* Max len allocatable for user space by HAL API: 32KB + ADI_APOLLO_HAL_BUFFER_LEN_HSCI_ADDR */ +#define ADI_APOLLO_HAL_BUFFER_LEN_MAX (32768U + ADI_APOLLO_HAL_BUFFER_LEN_HSCI_ADDR) +/* Min len allocatable for user space by HAL API: 128B */ +#define ADI_APOLLO_HAL_BUFFER_LEN_MIN (128U) + +/*! + * \brief Enumerates HAL protocol selection + */ +typedef enum { + ADI_APOLLO_HAL_PROTOCOL_SPI0 = 0, /*!< SPI0 protocol */ + ADI_APOLLO_HAL_PROTOCOL_SPI1 = 1, /*!< SPI1 protocol */ + ADI_APOLLO_HAL_PROTOCOL_HSCI = 2, /*!< HSCI protocol */ +} adi_apollo_hal_protocol_e; + +/*! + * \brief Enumerates HAL protocol Settings + */ +typedef enum { + ADI_APOLLO_HAL_TXN_MODE_SINGLE = 0, /*!< Single Transaction */ + ADI_APOLLO_HAL_TXN_MODE_STREAM = 1, /*!< Contiguous */ + ADI_APOLLO_HAL_TXN_MODE_DISCONTIG = 2, /*!< Discontiguous */ +} adi_apollo_hal_txn_mode_e; + +typedef enum { + ADI_APOLLO_HAL_TXN_SIZE_D8 = 0, + ADI_APOLLO_HAL_TXN_SIZE_D16 = 1, + ADI_APOLLO_HAL_TXN_SIZE_D32 = 2, +} adi_apollo_hal_txn_size_e; + +/*! + * \brief Device transaction config structure + */ +typedef struct { + uint8_t addr_len; /*!< Interface reg address size, in bytes */ + uint8_t data_len; /*!< Interface reg data size, in bytes */ + uint32_t stream_len; /*!< Interface transaction stream length. Number of data words to transfer. */ + uint64_t mask; /*!< Interface reg mask */ + uint8_t is_bf_txn; /*!< 0 = reg txn, mask for reg. 1 = bf txn, mask for bf mask */ +} adi_apollo_hal_txn_config_t; + +/** + * \brief Platform dependent hal init function + * + * \param[in] dev_obj Pointer to platform specific data + * \param[in] config Pointer to platform specific configuration struct + * + * \return 0 for success + * \return Any non-zero value indicates an error + * + * \note Not required by API + */ +typedef int32_t(*adi_apollo_hal_init_t)(void *dev_obj, void *config); + +/** + * \brief Platform dependent spi or hsci hal transfer function + * + * \param[in] dev_obj Pointer to platform specific data + * \param[in] in_data Pointer to array of data to send + * \param[out] out_data Pointer to array of data to receive + * \param[in] size_bytes The size in bytes allocated for each of the in_data and out_data arrays. + * + * \return 0 for success + * \return Any non-zero value indicates an error + */ +typedef int32_t(*adi_apollo_hal_xfer_t)(void *dev_obj, uint8_t *in_data, uint8_t *out_data, uint32_t size_bytes); + +/** + * \brief Platform dependent spi or hsci hal write function + * + * \param[in] dev_obj Pointer to platform specific data + * \param[in] tx_data Pointer to array of data to send + * \param[in] num_tx_bytes Number of bytes in tx_data array + * \param[in] txn_config Pointer to structure describing transaction \ref adi_apollo_hal_txn_config_t + * + * \return 0 for success + * \return Any non-zero value indicates an error + */ +typedef int32_t(*adi_apollo_hal_write_t)(void *dev_obj, const uint8_t tx_data[], uint32_t num_tx_bytes, adi_apollo_hal_txn_config_t *txn_config); + +/** + * \brief Platform dependent spi or hsci hal read function + * + * \param[in] dev_obj Pointer to platform specific data + * \param[in] tx_data Pointer to array of data to send + * \param[out] rx_data Pointer to array of data to receive + * \param[in] num_tx_rx_bytes Number of bytes for both tx_data and rx_data arrays + * \param[in] txn_config Pointer to structure describing transaction \ref adi_apollo_hal_txn_config_t + * + * \return 0 for success + * \return Any non-zero value indicates an error + */ +typedef int32_t(*adi_apollo_hal_read_t)(void *dev_obj, const uint8_t tx_data[], uint8_t rx_data[], uint32_t num_tx_rx_bytes, adi_apollo_hal_txn_config_t *txn_config); + +/** + * \brief Platform dependent spi or hsci hal polling read function + * + * \param[in] dev_obj Pointer to platform specific data + * \param[in] tx_data Pointer to array of data to send + * \param[out] rx_data Pointer to array of data to receive + * \param[in] num_tx_rx_bytes Number of bytes for both tx_data and rx_data arrays + * \param[in] timeout_us Timeout in us + * \param[in] reg_expect Pointer to expected register value + * \param[in] reg_mask Pointer to mask of relevant bits in register + * \param[in] txn_config Pointer to structure describing transaction \ref adi_apollo_hal_txn_config_t + * + * \return 0 for success + * \return Any non-zero value indicates an error + */ +typedef int32_t(*adi_apollo_hal_poll_read_t)(void *dev_obj, const uint8_t tx_data[], uint8_t rx_data[], uint32_t num_tx_rx_bytes, + uint32_t timeout_us, void *reg_expect, void *reg_mask, adi_apollo_hal_txn_config_t *txn_config); + + +/** + * \brief Platform dependent hsci hal manual linkup function + * + * \param[in] dev_obj Pointer to platform specific data + * \param[in] enable Enable manual linkup + * \param[in] link_up_signal_bits Link up signal + * + * \return 0 for success + * \return Any non-zero value indicates an error + */ +typedef int32_t(*adi_apollo_hal_manual_linkup_t)(void *dev_obj, uint8_t enable, uint16_t link_up_signal_bits); + +/** + * \brief Platform dependent hsci hal auto linkup function + * + * \param[in] dev_obj Pointer to platform specific data + * \param[in] enable Enable auto linkup + * \param[in] hscim_mosi_clk_inv Set 1, inverts HSCIM's mosi_clk output clk to Apollo + * \param[in] hscim_miso_clk_inv Set 1, inverts HSCIM's miso_clk input clk from Apollo + * + * \return 0 for success + * \return Any non-zero value indicates an error + */ +typedef int32_t(*adi_apollo_hal_auto_linkup_t)(void *dev_obj, uint8_t enable, uint8_t hscim_mosi_clk_inv, uint8_t hscim_miso_clk_inv); + +/** + * \brief Platform dependent hsci hal auto link_table get function + * \note Retrive HSCIM ALINK_TABLE after Apollo's link_active is set + * + * \param[in] dev_obj Pointer to platform specific data + * \param[out] hscim_alink_table Pointer to a variable that stores link table value from HSCI_M + * + * \return 0 for success + * \return Any non-zero value indicates an error + */ +typedef int32_t(*adi_apollo_hal_alink_tbl_get_t)(void *dev_obj, uint16_t *hscim_alink_table); + +/** + * \brief Platform dependent hal open + * + * \param[in] dev_obj Pointer to platform specific data + * + * \return 0 for success + * \return Any non-zero value indicates an error + */ +typedef int32_t(*adi_apollo_hal_open_t)(void *dev_obj); + +/** + * \brief Platform dependent hal close + * + * \param[in] dev_obj Pointer to platform specific data + * + * \return 0 for success + * \return Any non-zero value indicates an error + */ +typedef int32_t(*adi_apollo_hal_close_t)(void *dev_obj); + +/** + * \brief Platform dependent delay for specified number of microseconds. + * + * \param[in] dev_obj Pointer to platform specific data + * \param[in] us Time to delay/sleep in microseconds + * + * \return 0 for success + * \return Any non-zero value indicates an error + */ +typedef int32_t(*adi_apollo_hal_delay_us_t)(void *dev_obj, uint32_t us); + +/** + * \brief Platform dependent reset pin control function + * + * \param[in] dev_obj Pointer to platform specific data + * \param[in] enable Indicates the desired enable/disable reset via the ADI device RESETB pin + * 0: indicates RESETB pin is set HIGH + * 1: indicates RESETB pin is set LOW + * + * \return 0 for success + * \return Any non-zero value indicates an error + */ +typedef int32_t(*adi_apollo_hal_reset_pin_ctrl_t)(void *dev_obj, uint8_t enable); + +/** + * \brief Platform dependent write log message function + * + * \param[in] dev_obj Pointer to platform specific data + * \param[in] log_type \ref adi_cms_log_type_e + * \param[in] message Format string + * \param[in] argp Variable message + * + * \return 0 for success + * \return Any non-zero value indicates an error + */ +typedef int32_t(*adi_apollo_hal_log_write_t)(void *dev_obj, int32_t log_type, const char *message, va_list argp); + +#endif /* __ADI_APOLLO_HAL_TYPES_H__ */ + +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_invsinc.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_invsinc.h new file mode 100644 index 00000000000000..6d5ae86ca604ae --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_invsinc.h @@ -0,0 +1,58 @@ +/*! + * \brief Inverse Sinc Block definition headers + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_INVSINC + * @{ + */ +#ifndef __ADI_APOLLO_INVSINC_H__ +#define __ADI_APOLLO_INVSINC_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_invsinc_types.h" + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Enable tx invsinc to compensate the DAC sinc roll off gain lost + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] invsincs INVSINC channel selection. \ref adi_apollo_invsinc_select_e + * \param[in] enable 1: to enable invinc, 0: to disable + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_invsinc_enable(adi_apollo_device_t *device, adi_apollo_blk_sel_t invsincs, const uint8_t enable); + +/** + * \brief Inspect Inverse Sinc param data from device + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] invsincs A single INVSINC channel. \ref adi_apollo_invsinc_select_e + * \param[out] invsinc_inspect Pointer to invsinc inspect structure. \ref adi_apollo_invsinc_inspect_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_invsinc_inspect(adi_apollo_device_t *device, adi_apollo_blk_sel_t invsincs, adi_apollo_invsinc_inspect_t *invsinc_inspect); + +#ifndef CLIENT_IGNORE + +#endif /* CLIENT_IGNORE*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_INVSINC_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_invsinc_types.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_invsinc_types.h new file mode 100644 index 00000000000000..b6e3b977f4943b --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_invsinc_types.h @@ -0,0 +1,53 @@ +/*! + * \brief Inverse Sinc Block definition headers + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_INVSINC + * @{ + */ +#ifndef __ADI_APOLLO_INVSINC_TYPES_H__ +#define __ADI_APOLLO_INVSINC_TYPES_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_cms_api_common.h" +#include "adi_apollo_common.h" + +/*============= D E F I N E S ==============*/ +#define ADI_APOLLO_NUM_INVSINC 8 + +/*! + * \brief Enumerates TX INVSINC Select + */ +typedef enum { + ADI_APOLLO_INVSINC_NONE = 0x0, /*!< No INVSINC */ + ADI_APOLLO_INVSINC_A0 = 0x1, /*!< INVSINC0 of SIDE A */ + ADI_APOLLO_INVSINC_A1 = 0x2, /*!< INVSINC1 of SIDE A */ + ADI_APOLLO_INVSINC_A2 = 0x4, /*!< INVSINC2 of SIDE A */ + ADI_APOLLO_INVSINC_A3 = 0x8, /*!< INVSINC3 of SIDE A */ + ADI_APOLLO_INVSINC_B0 = 0x10, /*!< INVSINC0 of SIDE B */ + ADI_APOLLO_INVSINC_B1 = 0x20, /*!< INVSINC1 of SIDE B */ + ADI_APOLLO_INVSINC_B2 = 0x40, /*!< INVSINC2 of SIDE B */ + ADI_APOLLO_INVSINC_B3 = 0x80, /*!< INVSINC3 of SIDE B */ + ADI_APOLLO_INVSINC_ALL = 0xFF, /*!< ALL INVSINCs */ + ADI_APOLLO_INVSINC_ALL_4T4R = 0x33 /*!< ALL INVSINCs (4T4R) */ + +} adi_apollo_invsinc_select_e; + +/** + * \brief Inverse Sinc inspect params + */ +typedef struct +{ + uint8_t invsinc_en; /*!< Inverse sinc enable status. 1 = enabled, 0 = disabled */ + uint8_t invsinc_clk_en; /*!< Inverse sinc clock enable status. 1 = enabled, 0 = disabled */ +} adi_apollo_invsinc_inspect_t; + + +#endif /* __ADI_APOLLO_INVSINC_TYPES_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_jrx.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_jrx.h new file mode 100644 index 00000000000000..88a9f718623b04 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_jrx.h @@ -0,0 +1,425 @@ +/*! + * \brief JRX BLOCK definition headers + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_JRX + * @{ + */ +#ifndef __ADI_APOLLO_JRX_H__ +#define __ADI_APOLLO_JRX_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_jrx_types.h" + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Enable or disable the JESD link for Rx + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] links Target link from adi_apollo_jesd_link_select_e + * \param[in] link_en 1b'0 - LINK_POWER_DOWN, + * 1b'1 - LINK_ENABLE + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_jrx_link_enable_set(adi_apollo_device_t *device, + const uint16_t links, + uint8_t link_en); + +/** + * \brief Get current jrx 204C lane status + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] link Target link from adi_apollo_jesd_link_select_e + * \param[in] lane Target serdes lane. Valid values from 0 to ADI_APOLLO_JESD_DESER_COUNT-1 \ref adi_apollo_common_types.h + * \param[out] status Pointer to jrx 204c lane status + * bit[2:0] - Current Link State. + * 3'b0 : ENUM000 : RESET. + * 3'b1 : ENUM001 : UNLOCKED. Complete Sync Header (SH) detection and alignment. + * 3'b10 : ENUM002 : BLOCK. Complete the lane de-skew and lane alignment. + * 3'b11 : ENUM003 : DESKEW. Complete Multi-Block detection and alignment. + * 3'b100 : ENUM004 : M_BLOCK. Complete Extended Multi-block detection. + * 3'b101 : ENUM005 : E_M_BLOCK. Complete Extended Multi-block alignment. + * 3'b110 : ENUM006 : Link Ready. Link is up and running. + * 3'b111 : ENUM007 : FORCED. A lock state by asserting bit-field jrx_dl_204C_link_lock=1 + * bit3 - Reserved + * bit4 - Link PCLK slower copmare to conv_clk error. 0=NORMAL, 1=PCLK_SLOWER + * bit5 - Link PCLK faster copmare to conv_clk error. 0=NORMAL, 1=PCLK_FASTER + * bit6 - reserved + * bit7 - reserved + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_jrx_j204c_lane_status_get(adi_apollo_device_t *device, + const uint16_t link, + const uint16_t lane, + uint16_t *status); + +/** + * \brief Get current jrx link status + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] link Target link side from adi_apollo_jesd_link_select_e + * \param[out] status Pointer to jrx link status + * bit0 - link JESD mode. 0=CORRECT, 1=ERROR + * bit1 - link NS Down_Scale_Ratio. 0=NO_OVERFLOW, 1=OVERFLOW + * bit2 - reserved + * bit3 - reserved + * bit4 - reserved + * bit5 - user data ready. 1=ready, 0=not ready. + * bit6 - sysref phase established. 1=established, 0=not established + * bit7 - core config invalid. 1=invald, 0=valid + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_jrx_link_status_get(adi_apollo_device_t *device, + const uint16_t link, + uint16_t *status); + +/** + * \brief Get current jrx 204B link status + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] link Target link adi_apollo_jesd_link_select_e + * \param[in] lane Target serdes lane. Valid values from 0 to ADI_APOLLO_JESD_DESER_COUNT-1 \ref adi_apollo_common_types.h + * \param[out] status Pointer to jrx link status + * bit0 - the End of Frame + * bit1 - the End of Multi-Frame + * bit2 - frame sync lost + * bit3 - sync~ output from link layer + * bit4 - data payload available. 0=data not ready, 1=data ready + * bit5 - checksum status. 0=bad checksum, 1=good checksum + * bit6 - reserved + * bit7 - reserved + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_jrx_j204b_lane_status_get(adi_apollo_device_t *device, + const uint16_t link, + const uint16_t lane, + uint16_t *status); + + +/** + * \brief Get jrx lane rate adapt values. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] link_sides Target link side \ref adi_apollo_jesd_link_side_select_e + * \param[in] physical_lane Physical lane index (0~11) + * \param[out] lr_adapt Jrx lane rate adapt \ref adi_apollo_serdes_lr_adapt_ratio_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_jrx_lr_adapt_get(adi_apollo_device_t *device, + uint8_t link_sides, + uint8_t physical_lane, + uint8_t *lr_adapt); + +/** + * \brief Get current jrx 204B link error status + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] link Target link adi_apollo_jesd_link_select_e + * \param[in] lane Target serdes lane. Valid values from 0 to ADI_APOLLO_JESD_DESER_COUNT-1 \ref adi_apollo_common_types.h + * \param[out] status Pointer to jrx link status + * bit0 - bad disparity error. 0=NORMAL, 1=ERROR + * bit1 - code group sync (CGS) error. 0=FAIL, 1=PASS + * bit2 - checksum error. 0=FAIL, 1=PASS + * bit3 - frame sync error. 0=FAIL, 1=PASS + * bit4 - interlane de-scew error. 0=NORMAL, 1=ERROR + * bit5 - interlane synchronization status. 0=NORMAL, 1=ERROR + * bit6 - not in table error status. 0=NORMAL, 1=ERROR + * bit7 - unexpected K-character error status. 0=NORMAL, 1=ERROR + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_jrx_j204b_lane_error_get(adi_apollo_device_t *device, + const uint16_t link, + const uint16_t lane, + uint16_t *status); + +/** + * \brief Get current jrx rm fifo status + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] link Target link from adi_apollo_jesd_link_select_e + * \param[out] status Pointer to jrx rm_fifo status + * bit[1:0] - RM_FIFO empty status + * 2'b00 : Not_Empty : Both Slice RM Not Empty. + * 2'b01 : Slice0_RM_Empty : Only Slice0 RM Empty. + * 2'b10 : SLICE1_RM_EMPTY : Only Slice1 RM Empty. + * 2'b11 : Both_RM_EMPTY : Both Slice RM Empty. + * bit[3:2] - RM_FIFO full status + * 2'b00 : Not_Full : No RM Full. + * 2'b01 : Slice0_RM_Full : Only Slice0 RM Full. + * 2'b10 : Slice1_RM_Full : Only Slice1 RM Full. + * 2'b11 : Both_RM_Full : Both Slice RM Full. + * bit4 - Invalid sample error flag + * bit[7:5] - reserved + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_jrx_rm_fifo_status(adi_apollo_device_t *device, + const uint16_t link, + uint16_t *status); + +/** + * \brief Reset the JRx rate match fifo + * + * This can be called to clean up DAC output when FSRC is enabled. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] link_sides Target link side \ref adi_apollo_jesd_link_side_select_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_jrx_rm_fifo_reset(adi_apollo_device_t *device, + const uint16_t link_sides); + +/** + * \brief Get current jrx lane fifo status + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] link Target link from adi_apollo_jesd_link_select_e + * \param[out] status Pointer to jrx lane fifo status + * bit[11:0] - lane fifo empty flag for data from SERDINx. + * bit[27:16] - lane fifo full flag for data from SERDINx. + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_jrx_lane_fifo_status(adi_apollo_device_t *device, + const uint16_t link, + uint32_t *status); + +/** + * \brief clear all pclk error counters + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] links Target link side from adi_apollo_jesd_link_select_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_jrx_clear_pclk_errors(adi_apollo_device_t *device, + const uint16_t links); + +/** + * \brief Inspect Jrx link param data from device + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] links Target link. Only 1 link selection per call \ref adi_apollo_jesd_link_select_e + * \param[out] jrx_inspect Pointer to jrx inspect structure. \ref adi_apollo_jesd_rx_inspect_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_jrx_link_inspect(adi_apollo_device_t *device, + const uint16_t links, + adi_apollo_jesd_rx_inspect_t *jrx_inspect); + +/** + * \brief Set LMFC phase adjustment in conv_clk cycles. + * + * There is a phase counter in each link. It is reset by each new SYSREF signal. + * Thereafter, it increments on each conv_clk cycle. + * + * There are K*S/NS conv_clk cycles in an LEMC/LMFC. Therefore, the counter counts + * from 0 to K*S/NS-1 and wraps around. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] links Target link. \ref adi_apollo_jesd_link_select_e + * \param[in] phase_adjust Maximum value is k*s/ns-1. Set to 0 for normal operation. + *s + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_jrx_phase_adjust_set(adi_apollo_device_t* device, + const uint16_t links, + const uint16_t phase_adjust); + +/** + * \brief Get LMFC phase adjustment in conv_clk cycles. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] links Target link + * \param[out] phase_adjust Pointer to phase_adjust result. + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_jrx_phase_adjust_get(adi_apollo_device_t *device, + const uint16_t links, + uint16_t *phase_adjust); + +/** + * \brief Calculates the jrx phase adjustment. + * + * The arrival time of local LMFC/LEMC can be different across links. This function + * determines the phase differences across links and calculates an adjustment value that + * can be applied with \ref adi_apollo_jrx_phase_adjust_set(). + * + * Given that delay or skew can vary some between power on and across temperature/environment, + * a margin can be added. Default is ADI_APOLLO_JRX_PHASE_ADJ_MARGIN_DEFAULT. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] links Target links. + * \param[in] margin Margin for particular system. Default is ADI_APOLLO_JRX_PHASE_ADJ_MARGIN_DEFAULT + * \param[out] phase_adjust Maximum value is k*s/ns-1. + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_jrx_phase_adjust_calc(adi_apollo_device_t *device, const uint16_t links, uint16_t margin, uint16_t *phase_adjust); + +/** + * \brief Configure the JESD Rx lane cross bar between physical lane and logic lane + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] links Target link + * \param[in] physical_lane Physical lane index (0~11) + * \param[in] logical_lane Logical lane index + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_jrx_lane_xbar_set(adi_apollo_device_t *device, + const uint16_t links, + uint8_t physical_lane, + uint8_t logical_lane); + +/** + * \brief Configure the JESD Rx lanes cross bar between physical lane and logic lane + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] links Target link + * \param[in] logical_lanes Logical lane index + * \param[in] length Logical lane index array size + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_jrx_lanes_xbar_set(adi_apollo_device_t *device, + const uint16_t links, + uint8_t logical_lanes[], + uint32_t length); + +/** + * \brief Set jrx lane rate adapt values. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] link_sides Target link side \ref adi_apollo_jesd_link_side_select_e + * \param[in] physical_lane Physical lane index (0~11) + * \param[in] lr_adapt Jrx lane rate adapt \ref adi_apollo_serdes_lr_adapt_ratio_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_jrx_lr_adapt_set(adi_apollo_device_t *device, + uint8_t link_sides, + uint8_t physical_lane, + uint8_t lr_adapt); + +/** + * \brief Gets the number of conv clock cycles since last SYSREF, phase_diff + * + * The largest phase difference of all links is for the latest arrival local LMFC/LEMC. + * Reset by each SYSREF. + * The counter counts from 0 to K*S/NS-1 and wraps around. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] links Target link + * \param[out] phase_diff Pointer to phase_diff result + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_jrx_phase_diff_get(adi_apollo_device_t* device, + const uint16_t links, + uint16_t *phase_diff); + +/** + * \brief Enable JRx 204C IRQs + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] links Target link + * \param[in] irqs IRQ bitmask \ref adi_apollo_jrx_j204c_irq_e + * \param[in] enable 1 = Enable. 0 = Disable + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_jrx_j204c_irq_enable_set(adi_apollo_device_t *device, + const uint16_t links, + const uint32_t irqs, uint8_t enable); + +/** + * \brief Get enable status for JRx 204C IRQs + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] links Target link + * \param[out] irqs_enabled IRQ enable status bitmask. Bits defined by \ref adi_apollo_jrx_j204c_irq_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_jrx_j204c_irq_enable_get(adi_apollo_device_t *device, + const uint16_t links, + uint32_t *irqs_enabled); + +/** + * \brief Get status of JRx 204C IRQs + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] links Target links. if links > 1, 'status' is combination of all links or'd together + * \param[in] irqs IRQ bitmask \ref adi_apollo_jrx_j204c_irq_e + * \param[in] clear If true, then the interrupts will be cleared after reading + * \param[out] status IRQ status bitmask. Bits defined by \ref adi_apollo_jrx_j204c_irq_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_jrx_j204c_irq_get(adi_apollo_device_t *device, + const uint16_t links, const uint32_t irqs, + uint8_t clear, uint32_t *status); + +/** + * \brief Clear JRx 204C IRQ sticky bits + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] links Target link + * \param[in] irqs IRQ bitmask \ref adi_apollo_jrx_j204c_irq_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_jrx_j204c_irq_clear(adi_apollo_device_t *device, + const uint16_t links, + const uint32_t irqs); + +#ifndef CLIENT_IGNORE + +int32_t adi_apollo_jesd_rx_sample_repeat_en(adi_apollo_device_t *device, + const uint16_t link_sides, + uint8_t enable); + +#endif /* CLIENT_IGNORE*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_JRX_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_jrx_types.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_jrx_types.h new file mode 100644 index 00000000000000..60b43f90865e07 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_jrx_types.h @@ -0,0 +1,76 @@ +/*! + * \brief JRX BLOCK definition headers + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_JRX + * @{ + */ +#ifndef __ADI_APOLLO_JRX_TYPES_H__ +#define __ADI_APOLLO_JRX_TYPES_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_cms_api_common.h" +#include "adi_apollo_common.h" + +/*============= D E F I N E S ==============*/ + +#define ADI_APOLLO_JRX_LANES_MAX 12 +#define ADI_APOLLO_JRX_J204C_IRQ_NUM 10 +#define ADI_APOLLO_JRX_PHASE_ADJ_MARGIN_DEFAULT 2 + +/** + * \brief Jrx link status mask from + */ +typedef enum { + ADI_APOLLO_JRX_LINK_STAT_NOT_IN_TABLE = 0x01, + ADI_APOLLO_JRX_LINK_STAT_SCALE_OVERFLOW = 0x02, + ADI_APOLLO_JRX_LINK_STAT_USR_DAT_RDY = 0x20, + ADI_APOLLO_JRX_LINK_STAT_SYSREF_RECV = 0x40, + ADI_APOLLO_JRX_LINK_STAT_CFG_INVALID = 0x80 +} adi_apollo_jrx_link_stat_e; + +/** + * \brief JRx 204C IRQs + */ +typedef enum { + ADI_APOLLO_JRX_J204C_IRQ_CRC = 0x01, + ADI_APOLLO_JRX_J204C_IRQ_SH = 0x02, + ADI_APOLLO_JRX_J204C_IRQ_MB = 0x04, + ADI_APOLLO_JRX_J204C_IRQ_EMB = 0x08, + ADI_APOLLO_JRX_J204C_IRQ_DATA_RDY_LOST = 0x10, + ADI_APOLLO_JRX_J204C_IRQ_RM_FIFO_EMPTY = 0x20, + ADI_APOLLO_JRX_J204C_IRQ_RM_FIFO_FULL = 0x40, + ADI_APOLLO_JRX_J204C_IRQ_LANE_FIFO_EMPTY = 0x80, + ADI_APOLLO_JRX_J204C_IRQ_LANE_FIFO_FULL = 0x100, + ADI_APOLLO_JRX_J204C_IRQ_INVALID_SAMPLE = 0x200, + ADI_APOLLO_JRX_J204C_IRQ_ALL = 0x3FF, + } adi_apollo_jrx_j204c_irq_e; + +/** + * \brief JESD Rx inspect params + */ +typedef struct adi_apollo_jesd_rx_inspect +{ + uint8_t link_en; /*!< Link enable status. 1 = enabled, 0 = disabled */ + adi_apollo_jesd_lanes_per_link_e l_minus1; /*!< Number of lanes minus 1 */ + adi_apollo_jesd_octs_per_frm_e f_minus1; /*!< Number of bytes (octets) per frame minus 1 */ + adi_apollo_jesd_convs_per_link_e m_minus1; /*!< Number of converters minus 1 */ + adi_apollo_jesd_samp_conv_frm_e s_minus1; /*!< Number of samples per converter per frame minus 1 */ + adi_apollo_jesd_conv_resol_e n_minus1; /*!< Link converter resolution minus 1 */ + adi_apollo_jesd_bits_per_samp_e np_minus1; /*!< Converter sample resolution in bits minus 1 */ + adi_apollo_jesd_samp_per_conv_e ns_minus1; /*!< Number of samples per converter in Conv_sample */ + uint8_t k_minus1; /*!< Number of frames in a multiframe - 1 (0 - 255) */ + adi_apollo_jesd_cont_bits_per_samp_e cs; /*!< Number of control bits per sample */ + uint8_t jesd_mode; /*!< Jesd mode s*/ + adi_apollo_jesd_version_e ver; /*!< 0 = 204B, 1 = 204C */ + adi_apollo_jesd_subclass_e subclass; /*!< Subclass setting */ +} adi_apollo_jesd_rx_inspect_t; + +#endif /* __ADI_APOLLO_JRX_TYPES_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_jtx.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_jtx.h new file mode 100644 index 00000000000000..286c236f041a95 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_jtx.h @@ -0,0 +1,339 @@ +/*! + * \brief JESD TX Block definition headers + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_JTX + * @{ + */ +#ifndef __ADI_APOLLO_JTX_H__ +#define __ADI_APOLLO_JTX_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_jtx_types.h" + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Enable or Disable jtx link + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] links Target link select \ref adi_apollo_jesd_link_select_e + * \param[in] link_en 1:Enable, 0:Disable + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_jtx_link_enable_set(adi_apollo_device_t *device, const uint16_t links, + uint8_t link_en); + +/** + * \brief Get jtx link status + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] link Target link select \ref adi_apollo_jesd_link_select_e + * \param[out] status Pointer to jtx status + * bit[3:0] - QBF status + * bit4 - frame sync status + * bit5 - jtx pll locked + * bit6 - phase established + * bit7 - jtx invalid mode + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_jtx_link_status_get(adi_apollo_device_t *device, + const uint16_t link, + uint16_t *status); + +/** + * \brief Inspect Jtx link param data from device + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] links Target link. \ref adi_apollo_jesd_link_select_e + * \param[out] jtx_inspect Pointer to jtx inspect structure. \ref adi_apollo_jesd_tx_inspect_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_jtx_link_inspect(adi_apollo_device_t *device, + const uint16_t links, + adi_apollo_jesd_tx_inspect_t *jtx_inspect); + +/** + * \brief Output LMFC phase adjustment in conv_clk cycles. + * + * There is a phase counter in each link. It is reset by each new SYSREF signal. + * Thereafter, it increments on each conv_clk cycle. + * + * There are K*S/NS conv_clk cycles in an LEMC/LMFC. Therefore, the counter counts + * from 0 to K*S/NS-1 and wraps around. + * + * \remarks This API typically for debug purposes. Set to 0 for normal operation. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] links Target link. \ref adi_apollo_jesd_link_select_e + * \param[in] phase_adjust Maximum value is k*s/ns-1. Set to 0 for normal operation. + *s + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_jtx_phase_adjust_set(adi_apollo_device_t *device, + const uint16_t links, + const uint16_t phase_adjust); + +/** + * \brief Configure the JESD Tx lane cross bar between physical lane and logical lane + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] links Target link select \ref adi_apollo_jesd_link_select_e + * \param[in] physical_lane Physical lane index (0~11) + * \param[in] logical_lane Logical lane index (0~11) + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_jtx_lane_xbar_set(adi_apollo_device_t *device, const uint16_t links, + uint8_t physical_lane, uint8_t logical_lane); + +/** + * \brief Configure the JESD Tx lanes cross bar between physical lane and logical lane + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] links Target link select \ref adi_apollo_jesd_link_select_e + * \param[in] logical_lanes Logical lanes index (0~11 for each value) + * \param[in] length Logical lanes index array size + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_jtx_lanes_xbar_set(adi_apollo_device_t *device, const uint16_t links, + uint8_t logical_lanes[], uint32_t length); + +/** + * \brief Configure the JESD Tx (JTx) subclass mode + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] links Target link + * \param[in] subclass Link subclass operation mode. 0 = subclass 0, 1 = subclass 1 + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_jtx_subclass_set(adi_apollo_device_t* device, + const uint16_t links, + const uint16_t subclass); + + +/** + * \brief Set Output Drive Swing level for jtx serdes lanes. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] link_sides Target link side \ref adi_apollo_jesd_link_side_select_e + * \param[in] physical_lane Physical lane index (0~11) + * \param[in] drive_swing Output drive swing level of serdes lane \ref adi_apollo_ser_swing_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_jtx_lane_drive_swing_set(adi_apollo_device_t *device, + uint8_t link_sides, + uint8_t physical_lane, + uint8_t drive_swing); + +/** + * \brief Set Pre-Emphasis level for jtx serdes lanes. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] link_sides Target link side \ref adi_apollo_jesd_link_side_select_e + * \param[in] physical_lane Physical lane index (0~11) + * \param[in] pre_emp Pre-Emphasis level of serdes lane \ref adi_apollo_ser_pre_emp_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_jtx_lane_pre_emphasis_set(adi_apollo_device_t *device, + uint8_t link_sides, + uint8_t physical_lane, + uint8_t pre_emp); + +/** + * \brief Set Post-Emphasis level for jtx serdes lanes. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] link_sides Target link side \ref adi_apollo_jesd_link_side_select_e + * \param[in] physical_lane Physical lane index (0~11) + * \param[in] post_emp Post-Emphasis level of serdes lane \ref adi_apollo_ser_post_emp_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_jtx_lane_post_emphasis_set(adi_apollo_device_t *device, + uint8_t link_sides, + uint8_t physical_lane, + uint8_t post_emp); + +/** + * \brief Set swing/pre emphasis/post emphasis levels for multiple serdes lane. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] link_sides Target link side \ref adi_apollo_jesd_link_side_select_e + * \param[in] physical_lane Array of physical lane indexes (0~11) + * \param[in] drive_swing Array of output drive swing levels of serdes lanes \ref adi_apollo_ser_swing_e + * \param[in] pre_emp Array of pre-Emphasis levels of serdes lanes \ref adi_apollo_ser_pre_emp_e + * \param[in] post_emp Array of Post-Emphasis levels of serdes lanes \ref adi_apollo_ser_post_emp_e + * \param[in] num_lanes Number of serdes lane to set levels of + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_jtx_multi_lane_swing_emphasis_set(adi_apollo_device_t *device, + uint8_t link_sides, + uint8_t physical_lane[], + uint8_t drive_swing[], + uint8_t pre_emp[], + uint8_t post_emp[], + uint32_t num_lanes); +/** + * \brief Get Output Drive Swing level for jtx serdes lanes. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] link_sides Target link side \ref adi_apollo_jesd_link_side_select_e + * \param[in] physical_lane Physical lane index (0~11) + * \param[out] drive_swing Pointer to an 8-bit variable to which the value of + * output drive swing level of serdes lane be returned \ref adi_apollo_ser_swing_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_jtx_lane_drive_swing_get(adi_apollo_device_t *device, + uint8_t link_sides, + uint8_t physical_lane, + uint8_t *drive_swing); + +/** + * \brief Get jtx lane rate adapt values. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] link_sides Target link side \ref adi_apollo_jesd_link_side_select_e + * \param[in] physical_lane Physical lane index (0~11) + * \param[out] lr_adapt Jtx lane rate adapt \ref adi_apollo_serdes_lr_adapt_ratio_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_jtx_lr_adapt_get(adi_apollo_device_t *device, + uint8_t link_sides, + uint8_t physical_lane, + uint8_t *lr_adapt); +/** + * \brief Get Pre-Emphasis level for jtx serdes lanes. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] link_sides Target link side \ref adi_apollo_jesd_link_side_select_e + * \param[in] physical_lane Physical lane index (0~11) + * \param[out] pre_emp Pointer to an 8-bit variable to which the value of + * pre-emphasis level of serdes lane be returned \ref adi_apollo_ser_pre_emp_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_jtx_lane_pre_emphasis_get(adi_apollo_device_t *device, + uint8_t link_sides, + uint8_t physical_lane, + uint8_t *pre_emp); + +/** + * \brief Get Post-Emphasis level for jtx serdes lanes. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] link_sides Target link side \ref adi_apollo_jesd_link_side_select_e + * \param[in] physical_lane Physical lane index (0~11) + * \param[out] post_emp Pointer to an 8-bit variable to which the value of + * post-emphasis level of serdes lane be returned \ref adi_apollo_ser_post_emp_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_jtx_lane_post_emphasis_get(adi_apollo_device_t *device, + uint8_t link_sides, + uint8_t physical_lane, + uint8_t *post_emp); + +/** + * \brief Get swing/pre emphasis/post emphasis levels for multiple serdes lane. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] link_sides Target link side \ref adi_apollo_jesd_link_side_select_e + * \param[in] physical_lane Array of physical lane index (0~11) + * \param[out] drive_swing Array of 8-bit variable to which the value of drive swing + * output drive swing level of serdes lane be returned \ref adi_apollo_ser_swing_e + * \param[out] pre_emp Array of 8-bit variable to which the value of + * pre-emphasis level of serdes lane be returned \ref adi_apollo_ser_pre_emp_e + * \param[out] post_emp Array of 8-bit variable to which the value of post emp + * post-emphasis level of serdes lane be returned \ref adi_apollo_ser_post_emp_e + * \param[in] num_lanes Number of serdes lane to get levels of + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_jtx_multi_lane_swing_emphasis_get(adi_apollo_device_t *device, + uint8_t link_sides, + uint8_t physical_lane[], + uint8_t drive_swing[], + uint8_t pre_emp[], + uint8_t post_emp[], + uint32_t num_lanes); + +/** + * \brief Force sending invalid samples as part of FSRC reconfig flow. + * + * Invalid forcing is auto cleared by device after reconfig completes. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] links Target link + * \param[in] enable 0 = don't force invalid samples, 1 = force invalids + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_jtx_force_invalids_set(adi_apollo_device_t* device, + const uint16_t links, + const uint8_t enable); + +/** + * \brief Set jtx lane rate adapt values. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] link_sides Target link side \ref adi_apollo_jesd_link_side_select_e + * \param[in] physical_lane Physical lane index (0~11) + * \param[in] lr_adapt Jtx lane rate adapt \ref adi_apollo_serdes_lr_adapt_ratio_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_jtx_lr_adapt_set(adi_apollo_device_t *device, + uint8_t link_sides, + uint8_t physical_lane, + uint8_t lr_adapt); + +#ifndef CLIENT_IGNORE +uint32_t calc_jtx_dual_link_base(int32_t link); +uint32_t calc_jtx_qbf_txfe_base(int32_t link); +uint32_t calc_jtx_jesd_param_base(int32_t link); +#endif /* CLIENT_IGNORE*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_JTX_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_jtx_types.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_jtx_types.h new file mode 100755 index 00000000000000..98f7073947fcc5 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_jtx_types.h @@ -0,0 +1,43 @@ +/*! + * \brief JTX BLOCK definition headers + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_JTX + * @{ + */ +#ifndef __ADI_APOLLO_JTX_TYPES_H__ +#define __ADI_APOLLO_JTX_TYPES_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_cms_api_common.h" +#include "adi_apollo_common.h" + +/*============= D E F I N E S ==============*/ +/** + * \brief JESD Rx inspect params + */ +typedef struct adi_apollo_jesd_tx_inspect +{ + uint8_t link_en; /*!< Link enable status. 1 = enabled, 0 = disabled */ + adi_apollo_jesd_lanes_per_link_e l_minus1; /*!< Number of lanes minus 1 */ + adi_apollo_jesd_octs_per_frm_e f_minus1; /*!< Number of bytes (octets) per frame minus 1 */ + adi_apollo_jesd_convs_per_link_e m_minus1; /*!< Number of converters minus 1 */ + adi_apollo_jesd_samp_conv_frm_e s_minus1; /*!< Number of samples per converter per frame minus 1 */ + adi_apollo_jesd_conv_resol_e n_minus1; /*!< Link converter resolution minus 1 */ + adi_apollo_jesd_bits_per_samp_e np_minus1; /*!< Converter sample resolution in bits minus 1 */ + adi_apollo_jesd_samp_per_conv_e ns_minus1; /*!< Number of samples per converter in Conv_sample */ + uint8_t k_minus1; /*!< Number of frames in a multiframe - 1 (0 - 255) */ + adi_apollo_jesd_cont_bits_per_samp_e cs; /*!< Number of control bits per sample */ + uint8_t jesd_mode; /*!< Jesd mode s*/ + adi_apollo_jesd_version_e ver; /*!< 0 = 204B, 1 = 204C */ + adi_apollo_jesd_subclass_e subclass; /*!< Subclass setting */ +} adi_apollo_jesd_tx_inspect_t; + +#endif /* __ADI_APOLLO_JTX_TYPES_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_lb0.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_lb0.h new file mode 100644 index 00000000000000..ef9dc17f8aeaa4 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_lb0.h @@ -0,0 +1,133 @@ +/*! + * \brief Loopback 0 control functions + * + * \copyright copyright(c) 2023 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_LB0 + * @{ + */ +#ifndef __ADI_APOLLO_LB0_H__ +#define __ADI_APOLLO_LB0_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_cms_api_common.h" +#include "adi_apollo_common.h" + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Enable/disable loopback write FIFO clock in RX. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] sides Side select \ref adi_apollo_side_select_e for designators. + * \param[in] enable 1 to enable side(s), 0 to disable + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_lb0_rx_enable_set(adi_apollo_device_t *device, uint16_t sides, uint8_t enable); + +/** + * \brief Enable/disable loopback for TX + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] adcs ADC select \ref adi_apollo_adc_select_e for designators. + * \param[in] enable 1 to enable adc(s), 0 to disable + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_lb0_tx_enable_set(adi_apollo_device_t *device, uint16_t adcs, uint8_t enable); + +/** + * \brief Set XBAR mapping + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] sides Side select (single side) \ref adi_apollo_side_select_e for designators. + * \param[in] adcs Array of adcs to map to dacs: {DAC_0,...,DAC_N} \ref adi_apollo_adc_idx_e for designators. + * \param[in] adc_map_length Length of adc map (2 for 4t4r, 4 for 8t8r) + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_lb0_tx_xbar_set(adi_apollo_device_t *device, uint16_t sides, uint16_t adcs[], uint32_t adc_map_length); + +/** + * \brief Set read pointer reset value + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] adcs ADC select \ref adi_apollo_adc_select_e for designators. + * \param[in] value FIFO for read pointer reset (0, 1, or 2) + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_lb0_read_ptr_rst_set(adi_apollo_device_t *device, uint16_t adcs, uint8_t value); + +/** + * \brief Set write pointer reset value + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] sides Side select \ref adi_apollo_side_select_e for designators. + * \param[in] value FIFO for write pointer reset (0, 1, or 2) + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_lb0_write_ptr_rst_set(adi_apollo_device_t *device, uint16_t sides, uint8_t value); + +/** + * \brief Get overflow status and clear + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] adcs ADC select \ref adi_apollo_adc_select_e for designators. + * \param[out] status Status of overflow + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_lb0_overflow_status_get(adi_apollo_device_t *device, uint16_t adcs, uint8_t *status); + +/** + * \brief Enable/disable loopback debug data mode + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] sides Side select \ref adi_apollo_side_select_e for designators. + * \param[in] enable 1 to enable side(s), 0 to disable + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_lb0_debug_data_enable_set(adi_apollo_device_t *device, uint16_t sides, uint8_t enable); + +/** + * \brief Enable/disable loopback from BMEM. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] sides Side select \ref adi_apollo_side_select_e for designators. + * \param[in] enable 1 to enable side(s), 0 to disable + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_lb0_bmem_enable_set(adi_apollo_device_t *device, uint16_t sides, uint8_t enable); + + +#ifndef CLIENT_IGNORE + +#endif /* CLIENT_IGNORE*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_LB0_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_loopback.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_loopback.h new file mode 100644 index 00000000000000..c9de3a8abe897f --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_loopback.h @@ -0,0 +1,222 @@ +/*! + * \brief Loopback control functions + * + * \copyright copyright(c) 2023 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_LOOPBACK + * @{ + */ +#ifndef __ADI_APOLLO_LOOPBACK_H__ +#define __ADI_APOLLO_LOOPBACK_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_cms_api_common.h" +#include "adi_apollo_common.h" +#include "adi_apollo_loopback_types.h" + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Enable/disable loopback write FIFO clock in RX. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] sides Side select \ref adi_apollo_side_select_e for designators. + * \param[in] enable 1 to enable side(s), 0 to disable + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_loopback_lb0_rx_enable_set(adi_apollo_device_t *device, uint16_t sides, uint8_t enable); + +/** + * \brief Enable/disable loopback for TX + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] adcs ADC select \ref adi_apollo_adc_select_e for designators. + * \param[in] enable 1 to enable adc(s), 0 to disable + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_loopback_lb0_tx_enable_set(adi_apollo_device_t *device, uint16_t adcs, uint8_t enable); + +/** + * \brief Set Loopback0 ADC to DAC mux0 (hsdout) using fixed 1-to-1 mapping + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] sides Side select (single side) \ref adi_apollo_side_select_e for designators. + * \param[in] adcs Array of adcs to map to dacs: {DAC_0,...,DAC_N} \ref adi_apollo_adc_idx_e for designators. + * \param[in] adc_map_length Length of adc map (2 for 4t4r, 4 for 8t8r) + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_loopback_lb0_tx_xbar_set(adi_apollo_device_t *device, uint16_t sides, uint16_t adcs[], uint32_t adc_map_length); + +/** + * \brief Set Loopback0 ADC to DAC mux0 (hsdout) using custom mapping + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] sides Side select (single side) \ref adi_apollo_side_select_e for designators. + * \param[in] adcs Array of adcs to map. \ref adi_apollo_adc_idx_e for designators. + * \param[in] dacs Array of dacs to map to adcs: {adcs[0]->dacs[0], adcs[1]->dacs[1], ...} \ref adi_apollo_dac_idx_e for designators. + * \param[in] adc_map_length Length of adc map (2 for 4t4r, 4 for 8t8r) + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_loopback_lb0_tx_xbar_custom_set(adi_apollo_device_t *device, uint16_t sides, uint16_t adcs[], uint16_t dacs[], uint32_t adc_map_length); + + +/** + * \brief Set read pointer reset value + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] adcs ADC select \ref adi_apollo_adc_select_e for designators. + * \param[in] value FIFO for read pointer reset (0, 1, or 2) + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_loopback_lb0_read_ptr_rst_set(adi_apollo_device_t *device, uint16_t adcs, uint8_t value); + +/** + * \brief Set write pointer reset value + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] sides Side select \ref adi_apollo_side_select_e for designators. + * \param[in] value FIFO for write pointer reset (0, 1, or 2) + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_loopback_lb0_write_ptr_rst_set(adi_apollo_device_t *device, uint16_t sides, uint8_t value); + +/** + * \brief Get overflow status and clear + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] adcs ADC select \ref adi_apollo_adc_select_e for designators. + * \param[out] status Status of overflow + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_loopback_lb0_overflow_status_get(adi_apollo_device_t *device, uint16_t adcs, uint8_t *status); + +/** + * \brief Enable/disable loopback debug data mode + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] sides Side select \ref adi_apollo_side_select_e for designators. + * \param[in] enable 1 to enable side(s), 0 to disable + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_loopback_lb0_debug_data_enable_set(adi_apollo_device_t *device, uint16_t sides, uint8_t enable); + +/** + * \brief Enable/disable loopback from BMEM. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] sides Side select \ref adi_apollo_side_select_e for designators. + * \param[in] enable 1 to enable side(s), 0 to disable + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_loopback_lb0_bmem_enable_set(adi_apollo_device_t *device, uint16_t sides, uint8_t enable); + +/** + * \brief Enable/disable JESD loopback + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] sides Side select \ref adi_apollo_side_select_e for designators. + * \param[in] enable 1 to enable side(s), 0 to disable + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_loopback_jesd_enable_set(adi_apollo_device_t *device, uint16_t sides, uint8_t enable); + +/** + * \brief Enable/disable LB1 + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] sides Side select \ref adi_apollo_side_select_e for designators. + * \param[in] enable 1 to enable, 0 to disable + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_loopback_lb1_enable_set(adi_apollo_device_t *device, uint16_t sides, uint8_t enable); + +/** + * \brief Enable/disable LB1 per CDUC (can be done dynamically) + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] cducs CDUC select \ref adi_apollo_cduc_select_e for designators. + * \param[in] enable 1 to enable, 0 to disable + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_loopback_lb1_cduc_enable_set(adi_apollo_device_t *device, uint16_t cducs, uint8_t enable); + +/** + * \brief Set LB1 blending mode. + * \note Use FDUC gain enable blocks to scale Tx DP data to prevent overflow + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] cducs Bit selector for CDUCs \ref adi_apollo_cduc_select_e for designators. + * \param[in] mode Blend mode to apply to loopback1 data \ref adi_apollo_loopback_lb1_blend_mode_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_loopback_lb1_blend_set(adi_apollo_device_t *device, uint16_t cducs, adi_apollo_loopback_lb1_blend_mode_e mode); + +/** + * \brief Enable/disable LB2 + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] sides Side select \ref adi_apollo_side_select_e for designators. + * \param[in] enable 1 to enable, 0 to disable + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_loopback_lb2_enable_set(adi_apollo_device_t *device, uint16_t sides, uint8_t enable); + +/** + * \brief Enable/disable LB2 per FDUC (can be done dynamically) + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] fducs FDUC select \ref adi_apollo_fduc_select_e for designators. + * \param[in] enable 1 to enable, 0 to disable + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_loopback_lb2_fduc_enable_set(adi_apollo_device_t *device, uint16_t fducs, uint8_t enable); + + +#ifndef CLIENT_IGNORE + +#endif /* CLIENT_IGNORE*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_LOOPBACK_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_loopback_types.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_loopback_types.h new file mode 100644 index 00000000000000..637acd14e44b4d --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_loopback_types.h @@ -0,0 +1,32 @@ +/*! + * \brief LB BLOCK definition headers + * + * \copyright copyright(c) 2024 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_LOOPBACK + * @{ + */ +#ifndef __ADI_APOLLO_LOOPBACK_TYPES_H__ +#define __ADI_APOLLO_LOOPBACK_TYPES_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_cms_api_common.h" +#include "adi_apollo_common.h" + +/*============= D E F I N E S ==============*/ +/*! +* \brief EnumeratesLB1 +*/ +typedef enum { + ADI_APOLLO_LB1_BLEND_DISABLE = 0x0, /*!< Disable blending*/ + ADI_APOLLO_LB1_BLEND_DIV_2 = 0x1, /*!< Enable blend with loopback1 data scaled by 2 */ + ADI_APOLLO_LB1_BLEND_DIV_4 = 0x3, /*!< Enable blend with loopback1 data scaled by 4 */ +} adi_apollo_loopback_lb1_blend_mode_e; + +#endif /* __ADI_APOLLO_LOOPBACK_TYPES_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_mailbox.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_mailbox.h new file mode 100644 index 00000000000000..755f4b0ae8da50 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_mailbox.h @@ -0,0 +1,539 @@ +/** + * \file adi_apollo_mailbox.h + * + * \brief Mailbox Block definition headers + */ + +/* + * \copyright copyright(c) 2021 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + + +/*! + * \addtogroup ADI_APOLLO_MAILBOX + * @{ + */ + +#ifndef __ADI_APOLLO_MAILBOX_H__ +#define __ADI_APOLLO_MAILBOX_H__ + +/* WARNING!! This file is autogenerated by build_mailbox.py. Do not edit here */ + +/*============= I N C L U D E S ============*/ +#include "adi_cms_api_common.h" +#include "adi_apollo_mailbox_types.h" + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Ping the CPU + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] cmd Parameters for target. See \ref adi_apollo_mailbox_cmd_ping_t + * \param[out] resp Parameters from target. See \ref adi_apollo_mailbox_resp_ping_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_mailbox_ping(adi_apollo_device_t *device, adi_apollo_mailbox_cmd_ping_t *cmd, adi_apollo_mailbox_resp_ping_t *resp); + +/** + * \brief Run initial calibrations + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] cmd Parameters for target. See \ref adi_apollo_mailbox_cmd_run_init_t + * \param[out] resp Parameters from target. See \ref adi_apollo_mailbox_resp_run_init_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_mailbox_run_init(adi_apollo_device_t *device, adi_apollo_mailbox_cmd_run_init_t *cmd, adi_apollo_mailbox_resp_run_init_t *resp); + +/** + * \brief Get the completion status of initial calibrations + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[out] resp Parameters from target. See \ref adi_apollo_mailbox_resp_run_init_get_completion_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_mailbox_run_init_get_completion(adi_apollo_device_t *device, adi_apollo_mailbox_resp_run_init_get_completion_t *resp); + +/** + * \brief Get detailed status information on initial calibrations + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[out] resp Parameters from target. See \ref adi_apollo_mailbox_resp_run_init_get_detailed_status_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_mailbox_run_init_get_detailed_status(adi_apollo_device_t *device, adi_apollo_mailbox_resp_run_init_get_detailed_status_t *resp); + +/** + * \brief Abort any in progress initial calibrations + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[out] resp Parameters from target. See \ref adi_apollo_mailbox_resp_run_init_abort_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_mailbox_run_init_abort(adi_apollo_device_t *device, adi_apollo_mailbox_resp_run_init_abort_t *resp); + +/** + * \brief Set the set of enabled tracking cals + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] cmd Parameters for target. See \ref adi_apollo_mailbox_cmd_set_enabled_tracking_cals_t + * \param[out] resp Parameters from target. See \ref adi_apollo_mailbox_resp_set_enabled_tracking_cals_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_mailbox_set_enabled_tracking_cals(adi_apollo_device_t *device, adi_apollo_mailbox_cmd_set_enabled_tracking_cals_t *cmd, adi_apollo_mailbox_resp_set_enabled_tracking_cals_t *resp); + +/** + * \brief Get the set of enabled tracking cals + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[out] resp Parameters from target. See \ref adi_apollo_mailbox_resp_get_enabled_tracking_cals_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_mailbox_get_enabled_tracking_cals(adi_apollo_device_t *device, adi_apollo_mailbox_resp_get_enabled_tracking_cals_t *resp); + +/** + * \brief Get detailed state information for all tracking cals + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[out] resp Parameters from target. See \ref adi_apollo_mailbox_resp_get_tracking_cal_state_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_mailbox_get_tracking_cal_state(adi_apollo_device_t *device, adi_apollo_mailbox_resp_get_tracking_cal_state_t *resp); + +/** + * \brief Get calibration status information + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] cmd Parameters for target. See \ref adi_apollo_mailbox_cmd_get_cal_status_t + * \param[out] resp Parameters from target. See \ref adi_apollo_mailbox_resp_get_cal_status_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_mailbox_get_cal_status(adi_apollo_device_t *device, adi_apollo_mailbox_cmd_get_cal_status_t *cmd, adi_apollo_mailbox_resp_get_cal_status_t *resp); + +/** + * \brief Get system status information + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] cmd Parameters for target. See \ref adi_apollo_mailbox_cmd_get_sys_status_t + * \param[out] resp Parameters from target. See \ref adi_apollo_mailbox_resp_get_sys_status_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_mailbox_get_sys_status(adi_apollo_device_t *device, adi_apollo_mailbox_cmd_get_sys_status_t *cmd, adi_apollo_mailbox_resp_get_sys_status_t *resp); + +/** + * \brief Get device temperature information + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] cmd Parameters for target. See \ref adi_apollo_mailbox_cmd_get_device_temperature_t + * \param[out] resp Parameters from target. See \ref adi_apollo_mailbox_resp_get_device_temperature_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_mailbox_get_device_temperature(adi_apollo_device_t *device, adi_apollo_mailbox_cmd_get_device_temperature_t *cmd, adi_apollo_mailbox_resp_get_device_temperature_t *resp); + +/** + * \brief Get enabled temp sensors + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[out] resp Parameters from target. See \ref adi_apollo_mailbox_resp_get_enabled_temp_sensors_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_mailbox_get_enabled_temp_sensors(adi_apollo_device_t *device, adi_apollo_mailbox_resp_get_enabled_temp_sensors_t *resp); + +/** + * \brief Set enabled temp sensors + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] cmd Parameters for target. See \ref adi_apollo_mailbox_cmd_set_enabled_temp_sensors_t + * \param[out] resp Parameters from target. See \ref adi_apollo_mailbox_resp_set_enabled_temp_sensors_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_mailbox_set_enabled_temp_sensors(adi_apollo_device_t *device, adi_apollo_mailbox_cmd_set_enabled_temp_sensors_t *cmd, adi_apollo_mailbox_resp_set_enabled_temp_sensors_t *resp); + +/** + * \brief Unlock the configuration for changing + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] cmd Parameters for target. See \ref adi_apollo_mailbox_cmd_unlock_config_t + * \param[out] resp Parameters from target. See \ref adi_apollo_mailbox_resp_unlock_config_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_mailbox_unlock_config(adi_apollo_device_t *device, adi_apollo_mailbox_cmd_unlock_config_t *cmd, adi_apollo_mailbox_resp_unlock_config_t *resp); + +/** + * \brief Set system or calibration configuration + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] cmd Parameters for target. See \ref adi_apollo_mailbox_cmd_set_config_t + * \param[out] resp Parameters from target. See \ref adi_apollo_mailbox_resp_set_config_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_mailbox_set_config(adi_apollo_device_t *device, adi_apollo_mailbox_cmd_set_config_t *cmd, adi_apollo_mailbox_resp_set_config_t *resp); + +/** + * \brief Get system or calibration configuration + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] cmd Parameters for target. See \ref adi_apollo_mailbox_cmd_get_config_t + * \param[out] resp Parameters from target. See \ref adi_apollo_mailbox_resp_get_config_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_mailbox_get_config(adi_apollo_device_t *device, adi_apollo_mailbox_cmd_get_config_t *cmd, adi_apollo_mailbox_resp_get_config_t *resp); + +/** + * \brief Set system or calibration ctrl + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] cmd Parameters for target. See \ref adi_apollo_mailbox_cmd_set_ctrl_t + * \param[out] resp Parameters from target. See \ref adi_apollo_mailbox_resp_set_ctrl_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_mailbox_set_ctrl(adi_apollo_device_t *device, adi_apollo_mailbox_cmd_set_ctrl_t *cmd, adi_apollo_mailbox_resp_set_ctrl_t *resp); + +/** + * \brief Enter debug mode + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] cmd Parameters for target. See \ref adi_apollo_mailbox_cmd_enter_debug_mode_t + * \param[out] resp Parameters from target. See \ref adi_apollo_mailbox_resp_enter_debug_mode_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_mailbox_enter_debug_mode(adi_apollo_device_t *device, adi_apollo_mailbox_cmd_enter_debug_mode_t *cmd, adi_apollo_mailbox_resp_enter_debug_mode_t *resp); + +/** + * \brief Generic debug command + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] cmd Parameters for target. See \ref adi_apollo_mailbox_cmd_debug_t + * \param[out] resp Parameters from target. See \ref adi_apollo_mailbox_resp_debug_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_mailbox_debug(adi_apollo_device_t *device, adi_apollo_mailbox_cmd_debug_t *cmd, adi_apollo_mailbox_resp_debug_t *resp); + +/** + * \brief Set CPU log filters + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] cmd Parameters for target. See \ref adi_apollo_mailbox_cmd_set_log_filters_t + * \param[out] resp Parameters from target. See \ref adi_apollo_mailbox_resp_set_log_filters_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_mailbox_set_log_filters(adi_apollo_device_t *device, adi_apollo_mailbox_cmd_set_log_filters_t *cmd, adi_apollo_mailbox_resp_set_log_filters_t *resp); + +/** + * \brief Resume task(s) suspended due to breakpoint + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] cmd Parameters for target. See \ref adi_apollo_mailbox_cmd_resume_bkpt_t + * \param[out] resp Parameters from target. See \ref adi_apollo_mailbox_resp_resume_bkpt_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_mailbox_resume_bkpt(adi_apollo_device_t *device, adi_apollo_mailbox_cmd_resume_bkpt_t *cmd, adi_apollo_mailbox_resp_resume_bkpt_t *resp); + +/** + * \brief Run SERDES eye sweep + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] cmd Parameters for target. See \ref adi_apollo_mailbox_cmd_run_serdes_eye_sweep_t + * \param[out] resp Parameters from target. See \ref adi_apollo_mailbox_resp_run_serdes_eye_sweep_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_mailbox_run_serdes_eye_sweep(adi_apollo_device_t *device, adi_apollo_mailbox_cmd_run_serdes_eye_sweep_t *cmd, adi_apollo_mailbox_resp_run_serdes_eye_sweep_t *resp); + +/** + * \brief Run SERDES vertical eye sweep + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] cmd Parameters for target. See \ref adi_apollo_mailbox_cmd_run_serdes_vert_eye_sweep_t + * \param[out] resp Parameters from target. See \ref adi_apollo_mailbox_resp_run_serdes_vert_eye_sweep_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_mailbox_run_serdes_vert_eye_sweep(adi_apollo_device_t *device, adi_apollo_mailbox_cmd_run_serdes_vert_eye_sweep_t *cmd, adi_apollo_mailbox_resp_run_serdes_vert_eye_sweep_t *resp); + +/** + * \brief Set GPIO pin configuration + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] cmd Parameters for target. See \ref adi_apollo_mailbox_cmd_set_gpio_t + * \param[out] resp Parameters from target. See \ref adi_apollo_mailbox_resp_set_gpio_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_mailbox_set_gpio(adi_apollo_device_t *device, adi_apollo_mailbox_cmd_set_gpio_t *cmd, adi_apollo_mailbox_resp_set_gpio_t *resp); + +/** + * \brief Get GPIO pin configuration + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] cmd Parameters for target. See \ref adi_apollo_mailbox_cmd_get_gpio_t + * \param[out] resp Parameters from target. See \ref adi_apollo_mailbox_resp_get_gpio_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_mailbox_get_gpio(adi_apollo_device_t *device, adi_apollo_mailbox_cmd_get_gpio_t *cmd, adi_apollo_mailbox_resp_get_gpio_t *resp); + +/** + * \brief MBIAS pre clock init + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[out] resp Parameters from target. See \ref adi_apollo_mailbox_resp_mbias_pre_clock_init_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_mailbox_mbias_pre_clock_init(adi_apollo_device_t *device, adi_apollo_mailbox_resp_mbias_pre_clock_init_t *resp); + +/** + * \brief MBIAS post clock init + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[out] resp Parameters from target. See \ref adi_apollo_mailbox_resp_mbias_post_clock_init_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_mailbox_mbias_post_clock_init(adi_apollo_device_t *device, adi_apollo_mailbox_resp_mbias_post_clock_init_t *resp); + +/** + * \brief sysclk configuration + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[out] resp Parameters from target. See \ref adi_apollo_mailbox_resp_sysclk_configuration_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_mailbox_sysclk_configuration(adi_apollo_device_t *device, adi_apollo_mailbox_resp_sysclk_configuration_t *resp); + +/** + * \brief sysclk conditioning + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] cmd Parameters for target. See \ref adi_apollo_mailbox_cmd_sysclk_conditioning_t + * \param[out] resp Parameters from target. See \ref adi_apollo_mailbox_resp_sysclk_conditioning_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_mailbox_sysclk_conditioning(adi_apollo_device_t *device, adi_apollo_mailbox_cmd_sysclk_conditioning_t *cmd, adi_apollo_mailbox_resp_sysclk_conditioning_t *resp); + +/** + * \brief sysclk switch from ring oscillator + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[out] resp Parameters from target. See \ref adi_apollo_mailbox_resp_sysclk_switch_to_hsdig_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_mailbox_sysclk_switch_to_hsdig(adi_apollo_device_t *device, adi_apollo_mailbox_resp_sysclk_switch_to_hsdig_t *resp); + +/** + * \brief Set DAC Bias + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] cmd Parameters for target. See \ref adi_apollo_mailbox_cmd_master_bias_set_dac_bias_mode_t + * \param[out] resp Parameters from target. See \ref adi_apollo_mailbox_resp_master_bias_set_dac_bias_mode_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_mailbox_master_bias_set_dac_bias_mode(adi_apollo_device_t *device, adi_apollo_mailbox_cmd_master_bias_set_dac_bias_mode_t *cmd, adi_apollo_mailbox_resp_master_bias_set_dac_bias_mode_t *resp); + +/** + * \brief sysclk switch to ring oscillator + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[out] resp Parameters from target. See \ref adi_apollo_mailbox_resp_sysclk_switch_to_ringosc_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_mailbox_sysclk_switch_to_ringosc(adi_apollo_device_t *device, adi_apollo_mailbox_resp_sysclk_switch_to_ringosc_t *resp); + +/** + * \brief program pll + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] cmd Parameters for target. See \ref adi_apollo_mailbox_cmd_pgm_pll_t + * \param[out] resp Parameters from target. See \ref adi_apollo_mailbox_resp_pgm_pll_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_mailbox_pgm_pll(adi_apollo_device_t *device, adi_apollo_mailbox_cmd_pgm_pll_t *cmd, adi_apollo_mailbox_resp_pgm_pll_t *resp); + +/** + * \brief Update CRC for all calibration data + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[out] resp Parameters from target. See \ref adi_apollo_mailbox_resp_update_cal_data_crc_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_mailbox_update_cal_data_crc(adi_apollo_device_t *device, adi_apollo_mailbox_resp_update_cal_data_crc_t *resp); + +/** + * \brief Gets the firmware version information + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[out] resp Parameters from target. See \ref adi_apollo_mailbox_resp_get_fw_version_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_mailbox_get_fw_version(adi_apollo_device_t *device, adi_apollo_mailbox_resp_get_fw_version_t *resp); + +/** + * \brief Request challenge + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] cmd Parameters for target. See \ref adi_apollo_mailbox_cmd_request_challenge_t + * \param[out] resp Parameters from target. See \ref adi_apollo_mailbox_resp_request_challenge_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_mailbox_request_challenge(adi_apollo_device_t *device, adi_apollo_mailbox_cmd_request_challenge_t *cmd, adi_apollo_mailbox_resp_request_challenge_t *resp); + +/** + * \brief Set challenge + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] cmd Parameters for target. See \ref adi_apollo_mailbox_cmd_set_challenge_t + * \param[out] resp Parameters from target. See \ref adi_apollo_mailbox_resp_set_challenge_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_mailbox_set_challenge(adi_apollo_device_t *device, adi_apollo_mailbox_cmd_set_challenge_t *cmd, adi_apollo_mailbox_resp_set_challenge_t *resp); + +/** + * \brief Power up JTx + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[out] resp Parameters from target. See \ref adi_apollo_mailbox_resp_power_up_jtx_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_mailbox_power_up_jtx(adi_apollo_device_t *device, adi_apollo_mailbox_resp_power_up_jtx_t *resp); + +/** + * \brief Set configuration by user + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] cmd Parameters for target. See \ref adi_apollo_mailbox_cmd_mcs_bsync_set_config_t + * \param[out] resp Parameters from target. See \ref adi_apollo_mailbox_resp_mcs_bsync_set_config_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_mailbox_mcs_bsync_set_config(adi_apollo_device_t *device, adi_apollo_mailbox_cmd_mcs_bsync_set_config_t *cmd, adi_apollo_mailbox_resp_mcs_bsync_set_config_t *resp); + +/** + * \brief Get configuration by user + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[out] resp Parameters from target. See \ref adi_apollo_mailbox_resp_mcs_bsync_get_config_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_mailbox_mcs_bsync_get_config(adi_apollo_device_t *device, adi_apollo_mailbox_resp_mcs_bsync_get_config_t *resp); + +/** + * \brief Start the BSYNC synchornization process + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[out] resp Parameters from target. See \ref adi_apollo_mailbox_resp_mcs_bsync_go_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_mailbox_mcs_bsync_go(adi_apollo_device_t *device, adi_apollo_mailbox_resp_mcs_bsync_go_t *resp); + +/** + * \brief Gets the ADC slice modes + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[out] resp Parameters from target. See \ref adi_apollo_mailbox_resp_get_adc_slice_modes_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_mailbox_get_adc_slice_modes(adi_apollo_device_t *device, adi_apollo_mailbox_resp_get_adc_slice_modes_t *resp); + +/** + * \brief Set the action of ADC slice mode fast switch + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] cmd Parameters for target. See \ref adi_apollo_mailbox_cmd_set_adc_slice_mode_fast_switch_action_t + * \param[out] resp Parameters from target. See \ref adi_apollo_mailbox_resp_set_adc_slice_mode_fast_switch_action_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_mailbox_set_adc_slice_mode_fast_switch_action(adi_apollo_device_t *device, adi_apollo_mailbox_cmd_set_adc_slice_mode_fast_switch_action_t *cmd, adi_apollo_mailbox_resp_set_adc_slice_mode_fast_switch_action_t *resp); + + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_MAILBOX_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_mailbox_handler.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_mailbox_handler.h new file mode 100644 index 00000000000000..ebaf709362976a --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_mailbox_handler.h @@ -0,0 +1,43 @@ +/** + * \file adi_apollo_mailbox_handler.h + * + * \brief Mailbox Block definition headers + */ + +/* + * \copyright copyright(c) 2021 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + + +#ifndef __ADI_APOLLO_MAILBOX_HANDLER_H__ +#define __ADI_APOLLO_MAILBOX_HANDLER_H__ + +/* WARNING!! This file is autogenerated by build_mailbox.py. Do not edit here */ + +/*============= I N C L U D E S ============*/ +#include "adi_cms_api_common.h" +#include "adi_apollo_mailbox_types.h" + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Check Mailbox ready status + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_mailbox_ready_check(adi_apollo_device_t *device); + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_MAILBOX_HANDLER_H__ */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_mailbox_types.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_mailbox_types.h new file mode 100644 index 00000000000000..029f062450d447 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_mailbox_types.h @@ -0,0 +1,1810 @@ +/** + * \file adi_apollo_mailbox_types.h + * + * \brief Mailbox Block definition types + * + * \copyright copyright(c) 2021 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_MAILBOX + * @{ + */ + +#ifndef __ADI_APOLLO_MAILBOX_TYPES_H__ +#define __ADI_APOLLO_MAILBOX_TYPES_H__ + +/* WARNING!! This file is autogenerated by build_mailbox.py. Do not edit here */ + +#include "adi_cms_api_common.h" +#include "adi_apollo_common.h" + +#ifdef DOXYGEN_RUN +#define ADI_APOLLO_PACKED(s) s +#else +#include "adi_apollo_platform_pack.h" +#endif + +/** + * \brief mailbox command ID enumeration + */ +typedef enum adi_apollo_mailbox_cmd_id +{ + ADI_APOLLO_MAILBOX_PING = 0u, /*!< Opcode 0: Ping the CPU. See \ref adi_apollo_mailbox_resp_ping, \ref adi_apollo_mailbox_ping */ + ADI_APOLLO_MAILBOX_RUN_INIT = 1u, /*!< Opcode 1: Run initial calibrations. See \ref adi_apollo_mailbox_resp_run_init, \ref adi_apollo_mailbox_run_init */ + ADI_APOLLO_MAILBOX_RUN_INIT_GET_COMPLETION = 2u, /*!< Opcode 2: Get the completion status of initial calibrations. See \ref adi_apollo_mailbox_resp_run_init_get_completion, \ref adi_apollo_mailbox_run_init_get_completion */ + ADI_APOLLO_MAILBOX_RUN_INIT_GET_DETAILED_STATUS = 3u, /*!< Opcode 3: Get detailed status information on initial calibrations. See \ref adi_apollo_mailbox_resp_run_init_get_detailed_status, \ref adi_apollo_mailbox_run_init_get_detailed_status */ + ADI_APOLLO_MAILBOX_RUN_INIT_ABORT = 4u, /*!< Opcode 4: Abort any in progress initial calibrations. See \ref adi_apollo_mailbox_resp_run_init_abort, \ref adi_apollo_mailbox_run_init_abort */ + ADI_APOLLO_MAILBOX_SET_ENABLED_TRACKING_CALS = 5u, /*!< Opcode 5: Set the set of enabled tracking cals. See \ref adi_apollo_mailbox_resp_set_enabled_tracking_cals, \ref adi_apollo_mailbox_set_enabled_tracking_cals */ + ADI_APOLLO_MAILBOX_GET_ENABLED_TRACKING_CALS = 6u, /*!< Opcode 6: Get the set of enabled tracking cals. See \ref adi_apollo_mailbox_resp_get_enabled_tracking_cals, \ref adi_apollo_mailbox_get_enabled_tracking_cals */ + ADI_APOLLO_MAILBOX_GET_TRACKING_CAL_STATE = 7u, /*!< Opcode 7: Get detailed state information for all tracking cals. See \ref adi_apollo_mailbox_resp_get_tracking_cal_state, \ref adi_apollo_mailbox_get_tracking_cal_state */ + ADI_APOLLO_MAILBOX_GET_CAL_STATUS = 8u, /*!< Opcode 8: Get calibration status information. See \ref adi_apollo_mailbox_resp_get_cal_status, \ref adi_apollo_mailbox_get_cal_status */ + ADI_APOLLO_MAILBOX_GET_SYS_STATUS = 9u, /*!< Opcode 9: Get system status information. See \ref adi_apollo_mailbox_resp_get_sys_status, \ref adi_apollo_mailbox_get_sys_status */ + ADI_APOLLO_MAILBOX_GET_DEVICE_TEMPERATURE = 12u, /*!< Opcode 12: Get device temperature information. See \ref adi_apollo_mailbox_resp_get_device_temperature, \ref adi_apollo_mailbox_get_device_temperature */ + ADI_APOLLO_MAILBOX_GET_ENABLED_TEMP_SENSORS = 13u, /*!< Opcode 13: Get enabled temp sensors. See \ref adi_apollo_mailbox_resp_get_enabled_temp_sensors, \ref adi_apollo_mailbox_get_enabled_temp_sensors */ + ADI_APOLLO_MAILBOX_SET_ENABLED_TEMP_SENSORS = 14u, /*!< Opcode 14: Set enabled temp sensors. See \ref adi_apollo_mailbox_resp_set_enabled_temp_sensors, \ref adi_apollo_mailbox_set_enabled_temp_sensors */ + ADI_APOLLO_MAILBOX_UNLOCK_CONFIG = 17u, /*!< Opcode 17: Unlock the configuration for changing. See \ref adi_apollo_mailbox_resp_unlock_config, \ref adi_apollo_mailbox_unlock_config */ + ADI_APOLLO_MAILBOX_SET_CONFIG = 18u, /*!< Opcode 18: Set system or calibration configuration. See \ref adi_apollo_mailbox_resp_set_config, \ref adi_apollo_mailbox_set_config */ + ADI_APOLLO_MAILBOX_GET_CONFIG = 19u, /*!< Opcode 19: Get system or calibration configuration. See \ref adi_apollo_mailbox_resp_get_config, \ref adi_apollo_mailbox_get_config */ + ADI_APOLLO_MAILBOX_SET_CTRL = 20u, /*!< Opcode 20: Set system or calibration ctrl. See \ref adi_apollo_mailbox_resp_set_ctrl, \ref adi_apollo_mailbox_set_ctrl */ + ADI_APOLLO_MAILBOX_ENTER_DEBUG_MODE = 21u, /*!< Opcode 21: Enter debug mode. See \ref adi_apollo_mailbox_resp_enter_debug_mode, \ref adi_apollo_mailbox_enter_debug_mode */ + ADI_APOLLO_MAILBOX_DEBUG = 22u, /*!< Opcode 22: Generic debug command. See \ref adi_apollo_mailbox_resp_debug, \ref adi_apollo_mailbox_debug */ + ADI_APOLLO_MAILBOX_SET_LOG_FILTERS = 23u, /*!< Opcode 23: Set CPU log filters. See \ref adi_apollo_mailbox_resp_set_log_filters, \ref adi_apollo_mailbox_set_log_filters */ + ADI_APOLLO_MAILBOX_RESUME_BKPT = 24u, /*!< Opcode 24: Resume task(s) suspended due to breakpoint. See \ref adi_apollo_mailbox_resp_resume_bkpt, \ref adi_apollo_mailbox_resume_bkpt */ + ADI_APOLLO_MAILBOX_RUN_SERDES_EYE_SWEEP = 26u, /*!< Opcode 26: Run SERDES eye sweep. See \ref adi_apollo_mailbox_resp_run_serdes_eye_sweep, \ref adi_apollo_mailbox_run_serdes_eye_sweep */ + ADI_APOLLO_MAILBOX_RUN_SERDES_VERT_EYE_SWEEP = 29u, /*!< Opcode 29: Run SERDES vertical eye sweep. See \ref adi_apollo_mailbox_resp_run_serdes_vert_eye_sweep, \ref adi_apollo_mailbox_run_serdes_vert_eye_sweep */ + ADI_APOLLO_MAILBOX_SET_GPIO = 30u, /*!< Opcode 30: Set GPIO pin configuration. See \ref adi_apollo_mailbox_resp_set_gpio, \ref adi_apollo_mailbox_set_gpio */ + ADI_APOLLO_MAILBOX_GET_GPIO = 31u, /*!< Opcode 31: Get GPIO pin configuration. See \ref adi_apollo_mailbox_resp_get_gpio, \ref adi_apollo_mailbox_get_gpio */ + ADI_APOLLO_MAILBOX_MBIAS_PRE_CLOCK_INIT = 32u, /*!< Opcode 32: MBIAS pre clock init. See \ref adi_apollo_mailbox_resp_mbias_pre_clock_init, \ref adi_apollo_mailbox_mbias_pre_clock_init */ + ADI_APOLLO_MAILBOX_MBIAS_POST_CLOCK_INIT = 33u, /*!< Opcode 33: MBIAS post clock init. See \ref adi_apollo_mailbox_resp_mbias_post_clock_init, \ref adi_apollo_mailbox_mbias_post_clock_init */ + ADI_APOLLO_MAILBOX_SYSCLK_CONFIGURATION = 34u, /*!< Opcode 34: sysclk configuration. See \ref adi_apollo_mailbox_resp_sysclk_configuration, \ref adi_apollo_mailbox_sysclk_configuration */ + ADI_APOLLO_MAILBOX_SYSCLK_CONDITIONING = 35u, /*!< Opcode 35: sysclk conditioning. See \ref adi_apollo_mailbox_resp_sysclk_conditioning, \ref adi_apollo_mailbox_sysclk_conditioning */ + ADI_APOLLO_MAILBOX_SYSCLK_SWITCH_TO_HSDIG = 36u, /*!< Opcode 36: sysclk switch from ring oscillator. See \ref adi_apollo_mailbox_resp_sysclk_switch_to_hsdig, \ref adi_apollo_mailbox_sysclk_switch_to_hsdig */ + ADI_APOLLO_MAILBOX_MASTER_BIAS_SET_DAC_BIAS_MODE = 37u, /*!< Opcode 37: Set DAC Bias. See \ref adi_apollo_mailbox_resp_master_bias_set_dac_bias_mode, \ref adi_apollo_mailbox_master_bias_set_dac_bias_mode */ + ADI_APOLLO_MAILBOX_SYSCLK_SWITCH_TO_RINGOSC = 38u, /*!< Opcode 38: sysclk switch to ring oscillator. See \ref adi_apollo_mailbox_resp_sysclk_switch_to_ringosc, \ref adi_apollo_mailbox_sysclk_switch_to_ringosc */ + ADI_APOLLO_MAILBOX_PGM_PLL = 39u, /*!< Opcode 39: program pll. See \ref adi_apollo_mailbox_resp_pgm_pll, \ref adi_apollo_mailbox_pgm_pll */ + ADI_APOLLO_MAILBOX_UPDATE_CAL_DATA_CRC = 40u, /*!< Opcode 40: Update CRC for all calibration data. See \ref adi_apollo_mailbox_resp_update_cal_data_crc, \ref adi_apollo_mailbox_update_cal_data_crc */ + ADI_APOLLO_MAILBOX_GET_FW_VERSION = 41u, /*!< Opcode 41: Gets the firmware version information. See \ref adi_apollo_mailbox_resp_get_fw_version, \ref adi_apollo_mailbox_get_fw_version */ + ADI_APOLLO_MAILBOX_REQUEST_CHALLENGE = 42u, /*!< Opcode 42: Request challenge. See \ref adi_apollo_mailbox_resp_request_challenge, \ref adi_apollo_mailbox_request_challenge */ + ADI_APOLLO_MAILBOX_SET_CHALLENGE = 43u, /*!< Opcode 43: Set challenge. See \ref adi_apollo_mailbox_resp_set_challenge, \ref adi_apollo_mailbox_set_challenge */ + ADI_APOLLO_MAILBOX_POWER_UP_JTX = 44u, /*!< Opcode 44: Power up JTx. See \ref adi_apollo_mailbox_resp_power_up_jtx, \ref adi_apollo_mailbox_power_up_jtx */ + ADI_APOLLO_MAILBOX_MCS_BSYNC_SET_CONFIG = 45u, /*!< Opcode 45: Set configuration by user. See \ref adi_apollo_mailbox_resp_mcs_bsync_set_config, \ref adi_apollo_mailbox_mcs_bsync_set_config */ + ADI_APOLLO_MAILBOX_MCS_BSYNC_GET_CONFIG = 46u, /*!< Opcode 46: Get configuration by user. See \ref adi_apollo_mailbox_resp_mcs_bsync_get_config, \ref adi_apollo_mailbox_mcs_bsync_get_config */ + ADI_APOLLO_MAILBOX_MCS_BSYNC_GO = 47u, /*!< Opcode 47: Start the BSYNC synchornization process. See \ref adi_apollo_mailbox_resp_mcs_bsync_go, \ref adi_apollo_mailbox_mcs_bsync_go */ + ADI_APOLLO_MAILBOX_GET_ADC_SLICE_MODES = 48u, /*!< Opcode 48: Gets the ADC slice modes. See \ref adi_apollo_mailbox_resp_get_adc_slice_modes, \ref adi_apollo_mailbox_get_adc_slice_modes */ + ADI_APOLLO_MAILBOX_SET_ADC_SLICE_MODE_FAST_SWITCH_ACTION = 49u /*!< Opcode 49: Set the action of ADC slice mode fast switch. See \ref adi_apollo_mailbox_resp_set_adc_slice_mode_fast_switch_action, \ref adi_apollo_mailbox_set_adc_slice_mode_fast_switch_action */ +} adi_apollo_mailbox_cmd_id_e; + +/***************************************************************************** + * Enumerations + *****************************************************************************/ +typedef enum +{ + APOLLO_CPU_NO_ERROR = 0x00, /*< code: 0x00 no error */ + APOLLO_CPU_ADC_RX_SCAL_OBJ_ERROR = 0x01, /*< code: 0x01 err: Slice cal-object, cause: calibration may have saturated, recovery: no recovery */ + APOLLO_CPU_ADC_RX_SCAL_INTERRUPT_STATUS_ERROR = 0x02, /*< code: 0x02 err: Slice cal-IRQ status, cause: Unexpected HW behavior; interrupt status error; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_ADC_RX_SCAL_INTERRUPT_FG_ERROR = 0x03, /*< code: 0x03 err: Slice cal-interrupt foreground error, cause: Unexpected HW behavior; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_ADC_RX_SCAL_INTERRUPT_BG_ERROR = 0x04, /*< code: 0x04 err: Slice cal-interrupt background error, cause: Unexpected HW behavior; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_ADC_RX_FCAL_OBJ_ERROR = 0x05, /*< code: 0x05 err: Front-End cal-object, cause: calibration may have saturated, recovery: no recovery */ + APOLLO_CPU_ADC_RX_FCAL_INTERRUPT_STATUS_ERROR = 0x06, /*< code: 0x06 err: Front-End cal-IRQ status, cause: Unexpected HW behavior; interrupt status; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_ADC_RX_FCAL_INTERRUPT_FG_ERROR = 0x07, /*< code: 0x07 err: Front-End cal - interrupt foreground error, cause: Unexpected HW behavior; Front-end interrupt foreground; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_ADC_RX_FCAL_INTERRUPT_BG_ERROR = 0x08, /*< code: 0x08 err: Front-End cal - interrupt background error, cause: Unexpected HW behavior; Front-end interrupt background; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_ADC_RX_ICAL_OBJ_ERROR = 0x09, /*< code: 0x09 err: Interleaving cal-object, cause: calibration may have saturated; report to ADI, recovery: no recovery */ + APOLLO_CPU_ADC_RX_ICAL_INTERRUPT_STATUS_ERROR = 0x0a, /*< code: 0x0a err: Interleaving cal-IRQ status, cause: Unexpected HW behavior; interrupt status; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_ADC_RX_ICAL_INTERRUPT_FG_ERROR = 0x0b, /*< code: 0x0b err: Interleaving cal-interrupt foreground, cause: Unexpected HW behavior; interleaving interrupt foreground; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_ADC_RX_ICAL_INTERRUPT_BG_ERROR = 0x0c, /*< code: 0x0c err: Interleaving cal-interrupt background, cause: Unexpected HW behavior; interleaving interrupt background; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_ADC_RX_FTEST_OBJ_ERROR = 0x0d, /*< code: 0x0d err: Factory test cal-object, cause: Factory test cal object; report to ADI, recovery: no recovery */ + APOLLO_CPU_ADC_RX_FTEST_INTERRUPT_STATUS_ERROR = 0x0e, /*< code: 0x0e err: Factory test cal-IRQ status, cause: Unexpected HW behavior; interrupt status; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_ADC_RX_FTEST_INTERRUPT_FC_ERROR = 0x0f, /*< code: 0x0f err: Factory test cal-interrupt factory calibration, cause: Unexpected HW behavior; Factory test cal interrupt calibration; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_ADC_RX_SIGA_OBJ_ERROR = 0x10, /*< code: 0x10 err: Signal analysis-object, cause: Signal cnalysis object; report to ADI, recovery: no recovery */ + APOLLO_CPU_ADC_RX_SIGA_INTERRUPT_ERROR = 0x11, /*< code: 0x11 err: Signal Analysis-interrupt, cause: Unexpected HW behavior; Interrupt; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_ADC_RX_INTERRUPT_TIMEOUT_ERROR = 0x12, /*< code: 0x12 err: Interrupt timeout, cause: Unexpected HW behavior; Interrupt timeout; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_ADC_RX_SW_REVISION_SUM_ERROR = 0x13, /*< code: 0x13 err: Software revision summation, cause: Unexpected HW behavior; Software revision summation error; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_ADC_RX_FAST_DETECT_ERROR = 0x14, /*< code: 0x14 err: Fast detect configuration, cause: Unexpected HW behavior; Fast detect configuration error; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_ADC_RX_CMD_INVALID_ERROR = 0x15, /*< code: 0x15 err: Control command was invalid, cause: Unexpected HW behavior; bad command; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_ADC_RX_CMD_QUEUE_ERROR = 0x16, /*< code: 0x16 err: Control command queue, cause: Unexpected HW behavior; command queue error; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_ADC_RX_HW_SLICE_INIT_ERROR = 0x17, /*< code: 0x17 err: HW Slice cal Initialization, cause: Unexpected HW behavior; slice csl init; report to ADI; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_ADC_RX_HW_TRACK_INIT_ERROR = 0x18, /*< code: 0x18 err: HW Track & Hold Initialization, cause: Unexpected HW behavior; tracking cal; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_ADC_RX_UNKNOWN_ERROR = 0x19, /*< code: 0x19 err: Unknown or unhandled error, cause: Unexpected HW behavior; unhandled error; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_ADC_RX_FSM_CMD_ERROR = 0x1f, /*< code: 0x1f err: FSM command returns error, cause: Unexpected HW behavior; FSM command error; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_ADC_RX_HW_STARTUP_ERROR = 0x20, /*< code: 0x20 err: HW start-up error, cause: Unexpected HW behavior; start-up error; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_ADC_RX_CAL_TIMEOUT_ERROR = 0x21, /*< code: 0x21 err: Cal timed-out, cause: Unexpected HW behavior; Cal did not finish in expected time; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_ADC_RX_CONFIG_INVALID_PARAM_ERROR = 0x22, /*< code: 0x22 err: Bad config parameter, cause: bad config parameter, recovery: invalid parameter passed */ + APOLLO_CPU_ADC_RX_CTRL_FUNC_NOT_SUPPORTED_ERROR = 0x23, /*< code: 0x23 err: Unknown control command (see module), cause: unhandled control command, recovery: invalid parameter passed */ + APOLLO_CPU_ADC_RX_ALREADY_RUNNING_CAL_ERROR = 0x24, /*< code: 0x24 err: Requested to run a cal when in the middle of a cal, cause: Must wait until currently running cal completes, recovery: Check interface */ + APOLLO_CPU_ADC_RX_CMD_NEEDS_DEBUG_MODE_ERROR = 0x25, /*< code: 0x25 err: The ctrl or config cmd only works in debug mode, cause: cmd only works in debug mode, recovery: Check interface */ + APOLLO_CPU_ADC_RX_TRACKING_NEEDS_INIT_ERROR = 0x26, /*< code: 0x26 err: Must run initial cal before tracking, cause: Did not successfully complete initial ADC Rx cal, recovery: Check interface */ + APOLLO_CPU_ADC_RX_INIT_DAC_NOT_RUNNING_ERROR = 0x27, /*< code: 0x27 err: DAC stream not running, cause: Unexpected HW behavior; init cal; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_ADC_RX_HW_REG_VERIFY_ERROR = 0x28, /*< code: 0x28 err: Some of the HW registers failed to verify, cause: Unexpected HW behavior; Used for ADI HW diagnostics; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_ADC_RX_NVM_READING_DATA_ERROR = 0x29, /*< code: 0x29 err: Reading calibration data from NVM, cause: Unexpected HW behavior; NVM data reading error; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_ADC_RX_NVM_DATA_LENGTH_MISMATCH_ERROR = 0x2a, /*< code: 0x2a err: NVM data length mismatch, cause: Unexpected HW behavior; NVM data error; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_ADC_RX_ALL_ADC_DISABLED_ERROR = 0x2b, /*< code: 0x2b err: The ctrl or config cmd only works when ADCs are enabled, cause: cmd only works when ADCs are enabled, recovery: Check interface */ + APOLLO_CPU_ADC_RX_NVM_DATA_VERSION_MISMATCH_ERROR = 0x2c, /*< code: 0x2c err: NVM data version mismatch, cause: Unexpected HW behavior; NVM data version error; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_ADC_RX_ADC_SLICE_MODE_SWITCH_FAILED_ERROR = 0x2d, /*< code: 0x2d err: ADC slice mode switch failed, cause: Unexpected HW behavior; Failed on switching ADC slice mode; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_ADC_RX_NVM_DATA_NOT_FUSED_ERROR = 0x2e, /*< code: 0x2e err: NVM data not fused, cause: Unexpected HW behavior; NVM data error; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_ADC_RX_ADC_NOT_IN_ABORT_STATE_ERROR = 0x2f, /*< code: 0x2f err: ADC not in abort state, cause: Unexpected HW behavior; ADC abort error; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_ADC_RX_ADC_PARAM_GET_ERROR = 0x30, /*< code: 0x30 err: ADC wrong parameter or internal error, cause: Unexpected HW behavior; ADC parameter get error; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_ADC_RX_ADC_PARAM_SET_ERROR = 0x31, /*< code: 0x31 err: ADC wrong parameter or internal error, cause: Unexpected HW behavior; ADC parameter set error; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_ADC_RX_ADC_PREP_SLICE_MODE_SWITCH_FAILED_ERROR = 0x32, /*< code: 0x32 err: Preparing ADC slice mode fast switch failed, cause: Unexpected HW behavior; Failed on preparing ADC slice mode fast switch; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_ADC_RX_ADC_RESUM_SLICE_MODE_SWITCH_FAILED_ERROR = 0x33, /*< code: 0x33 err: Resuming ADC slice mode fast switch failed, cause: Unexpected HW behavior; Failed on resuming ADC slice mode fast switch; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_ADC_RX_ADC_MODE_SWITCH_ENABLED_IN_8T8R_ERROR = 0x34, /*< code: 0x34 err: ADC slice mode switch not supported in 8T8R, cause: Unexpected HW behavior; ADC slice mode switch not supported in 8T8R; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_ADC_RX_GUARD_OBJ_ERROR = 0x35, /*< code: 0x35 err: Factory test guard-object, cause: Factory test cal object; report to ADI, recovery: no recovery */ + APOLLO_CPU_ADC_RX_ADC_CAL_DAC_CFG_ERROR = 0x36, /*< code: 0x36 err: ADC wrong parameter or internal error, cause: Unexpected HW behavior; ADC calibration DAC configuration error; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_DAC_TX_CMD_ERROR = 0x101, /*< code: 0x101 err: Bad Control command, cause: Unexpected HW behavior; bad command; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_DAC_TX_QUEUE_ERROR = 0x102, /*< code: 0x102 err: Control command queue, cause: Unexpected HW behavior; command queue error; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_DAC_TX_HW_STARTUP_ERROR = 0x103, /*< code: 0x103 err: HW start-up error, cause: Unexpected HW behavior; start-up error; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_DAC_TX_CAL_TIMEOUT_ERROR = 0x104, /*< code: 0x104 err: Cal timed-out, cause: Unexpected HW behavior; Cal did not finish in expected time; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_DAC_TX_CONFIG_INVALID_PARAM_ERROR = 0x105, /*< code: 0x105 err: Bad config parameter, cause: bad config parameter, recovery: invalid parameter passed */ + APOLLO_CPU_DAC_TX_UNKNOWN_ERROR = 0x106, /*< code: 0x106 err: Unknown or unhandled error, cause: Unexpected HW behavior; unhandled error; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_DAC_TX_CTRL_FUNC_NOT_SUPPORTED_ERROR = 0x107, /*< code: 0x107 err: Unknown control command (see module), cause: unhandled control command, recovery: invalid parameter passed */ + APOLLO_CPU_DAC_TX_ALREADY_RUNNING_CAL_ERROR = 0x108, /*< code: 0x108 err: Requested to run a cal when in the middle of a cal, cause: Must wait until currently running cal completes, recovery: Check interface */ + APOLLO_CPU_DAC_TX_CMD_NEEDS_DEBUG_MODE_ERROR = 0x109, /*< code: 0x109 err: The ctrl or config cmd only works in debug mode, cause: cmd only works in debug mode, recovery: Check interface */ + APOLLO_CPU_DAC_TX_TRACKING_NEEDS_INIT_ERROR = 0x10a, /*< code: 0x10a err: Must run initial cal before tracking, cause: Did not successfully complete initial DAC Tx cal, recovery: Check interface */ + APOLLO_CPU_DAC_TX_INIT_DAC_NOT_RUNNING_ERROR = 0x10b, /*< code: 0x10b err: DAC stream not running, cause: Unexpected HW behavior; init cal; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_DAC_TX_HW_REG_VERIFY_ERROR = 0x10c, /*< code: 0x10c err: Some of the HW registers failed to verify, cause: Unexpected HW behavior; Used for ADI HW diagnostics; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_DAC_TX_INTERRUPT_STATUS_ERROR = 0x10d, /*< code: 0x10d err: Invalid interrupt status, cause: Unexpected HW behavior; Invalid value of interrupt status; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_DAC_TX_INTERRUPT_TIMEOUT_ERROR = 0x10e, /*< code: 0x10e err: Timeout due to not receiving an interrupt, cause: Unexpected HW behavior; Timeout; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_DAC_TX_BIAS_POWER_MODE_ERROR = 0x10f, /*< code: 0x10f err: Bias failed to power up or down, cause: Unexpected HW behavior; Bias power error; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_DAC_TX_DLL_FAILED_TO_LOCK_ERROR = 0x110, /*< code: 0x110 err: Clock DLL has failed to lock, cause: Unexpected HW behavior; Clock DLL unlock; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_DAC_TX_NVM_READING_DATA_ERROR = 0x111, /*< code: 0x111 err: Reading calibration data from NVM, cause: Unexpected HW behavior; NVM data reading error; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_DAC_TX_NVM_DATA_LENGTH_MISMATCH_ERROR = 0x112, /*< code: 0x112 err: NVM data length mismatch, cause: Unexpected HW behavior; NVM data error; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_DAC_TX_ALL_DAC_DISABLED_ERROR = 0x113, /*< code: 0x113 err: The ctrl or config cmd only works when DACs are enabled, cause: cmd only works when DACs are enabled, recovery: Check interface */ + APOLLO_CPU_DAC_TX_NVM_DATA_NOT_FUSED_ERROR = 0x114, /*< code: 0x114 err: NVM data not fused, cause: Unexpected HW behavior; NVM data error; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_DAC_TX_SW_REVISION_SUM_ERROR = 0x115, /*< code: 0x115 err: Software revision summation, cause: Unexpected HW behavior; Software revision summation error; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_DAC_TX_INVALID_MODE_ERROR = 0x116, /*< code: 0x116 err: Mode (4T,8T,etc.) invalid, cause: Unexpected HW behavior; Invalid mode error; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_SERDES_RX_ALREADY_RUNNING_CAL_ERROR = 0x201, /*< code: 0x201 err: Requested to run a cal when in the middle of a cal, cause: Must wait until currently running cal completes, recovery: Check interface */ + APOLLO_CPU_SERDES_RX_CAL_INVALID_PARAM_ERROR = 0x202, /*< code: 0x202 err: Set Cal args Error, cause: Invalid argument passed to SERDES command, recovery: Check command arguments against supported set */ + APOLLO_CPU_SERDES_RX_TRACK_NO_INIT_ERROR = 0x203, /*< code: 0x203 err: Attempting to run tracking cals before init cals, cause: Serdes tracking calibration was initiated before serdes initial calibration, recovery: Run serdes initial calibration before starting serdes tracking cal */ + APOLLO_CPU_SERDES_RX_NVM_READING_DATA_ERROR = 0x204, /*< code: 0x204 err: Reading Rx calibration data from NVM, cause: Unexpected HW behavior; NVM data reading error; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_SERDES_RX_NVM_DATA_LENGTH_MISMATCH_ERROR = 0x205, /*< code: 0x205 err: NVM data length mismatch, cause: Unexpected HW behavior; NVM data error; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_SERDES_RX_HW_STARTUP_ERROR = 0x206, /*< code: 0x206 err: HW start-up error, cause: Unexpected HW behavior; start-up error; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_SERDES_RX_LANE00_ERROR = 0x207, /*< code: 0x207 err: Lane 0 Error, cause: Unexpected HW behavior; ; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_SERDES_RX_LANE01_ERROR = 0x208, /*< code: 0x208 err: Lane 1 Error, cause: Unexpected HW behavior; ; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_SERDES_RX_LANE02_ERROR = 0x209, /*< code: 0x209 err: Lane 2 Error, cause: Unexpected HW behavior; ; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_SERDES_RX_LANE03_ERROR = 0x20a, /*< code: 0x20a err: Lane 3 Error, cause: Unexpected HW behavior; ; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_SERDES_RX_LANE04_ERROR = 0x20b, /*< code: 0x20b err: Lane 4 Error, cause: Unexpected HW behavior; ; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_SERDES_RX_LANE05_ERROR = 0x20c, /*< code: 0x20c err: Lane 5 Error, cause: Unexpected HW behavior; ; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_SERDES_RX_LANE06_ERROR = 0x20d, /*< code: 0x20d err: Lane 6 Error, cause: Unexpected HW behavior; ; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_SERDES_RX_LANE07_ERROR = 0x20e, /*< code: 0x20e err: Lane 7 Error, cause: Unexpected HW behavior; ; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_SERDES_RX_LANE08_ERROR = 0x20f, /*< code: 0x20f err: Lane 8 Error, cause: Unexpected HW behavior; ; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_SERDES_RX_LANE09_ERROR = 0x210, /*< code: 0x210 err: Lane 9 Error, cause: Unexpected HW behavior; ; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_SERDES_RX_LANE10_ERROR = 0x211, /*< code: 0x211 err: Lane 10 Error, cause: Unexpected HW behavior; ; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_SERDES_RX_LANE11_ERROR = 0x212, /*< code: 0x212 err: Lane 11 Error, cause: Unexpected HW behavior; ; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_SERDES_RX_LANE12_ERROR = 0x213, /*< code: 0x213 err: Lane 12 Error, cause: Unexpected HW behavior; ; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_SERDES_RX_CMD_ERROR = 0x214, /*< code: 0x214 err: Bad Control command, cause: Unexpected HW behavior; bad command; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_SERDES_RX_QUEUE_ERROR = 0x215, /*< code: 0x215 err: Control command queue, cause: Unexpected HW behavior; command queue error; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_SERDES_RX_UNMAPPED_ERROR = 0x216, /*< code: 0x216 err: Unmapped serdes error, cause: Undefined Internal serdes error, recovery: Unknown internal serdes error - Reset device If the problem persists contact ADI. */ + APOLLO_CPU_SERDES_RX_NVM_DATA_NOT_FUSED_ERROR = 0x217, /*< code: 0x217 err: NVM data not fused, cause: Unexpected HW behavior; NVM data error; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_SERDES_RX_INTERRUPT_TIMEOUT_ERROR = 0x218, /*< code: 0x218 err: Interrupt Timeout, cause: Unexpected HW behavior; Interrupt timeout error; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_SERDES_RX_INVALID_LANE_NUMBER_ERROR = 0x219, /*< code: 0x219 err: Invalid lane number, cause: Unexpected HW behavior; Invalid lane error; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_SERDES_TX_CAL_LANE_POWERED_DOWN_ERROR = 0x301, /*< code: 0x301 err: Lane is powered down or not configured, cause: Requesting to calibrate a lane that is powered-down or not configure, recovery: Check provided lane number/mask against serdes device profile */ + APOLLO_CPU_SERDES_TX_CAL_LANE_TAP_ERROR = 0x302, /*< code: 0x302 err: Wrong value of emphasis, cause: Requested SERDES emphasis is wrong, recovery: Check provided emphasis value */ + APOLLO_CPU_SERDES_TX_CAL_LANE_PARITY_ERROR = 0x303, /*< code: 0x303 err: Calculating parity, cause: Unexpected HW behavior; Parity error; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_SERDES_TX_CAL_CTRL_CMD_NOT_SUPPORTED_ERROR = 0x304, /*< code: 0x304 err: Control command not supported, cause: Requested SERDES command doesn't exist, recovery: Check provided command against supported command set */ + APOLLO_CPU_SERDES_TX_CAL_LANE_UNMAPPED_ERROR = 0x305, /*< code: 0x305 err: Unmapped serdes error, cause: Undefined Internal serdes error, recovery: Unknown internal serdes error - Reset device If the problem persists contact ADI. */ + APOLLO_CPU_SERDES_TX_CAL_UNKNOWN_ERROR = 0x306, /*< code: 0x306 err: Unknown or unhandled error, cause: Unexpected HW behavior; unhandled error; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_SERDES_TX_CAL_INVALID_PARAM_ERROR = 0x307, /*< code: 0x307 err: Set Cal args Error, cause: Invalid argument passed to SERDES command, recovery: Check command arguments against supported set */ + APOLLO_CPU_SERDES_TX_CMD_ERROR = 0x308, /*< code: 0x308 err: Bad Control command, cause: Unexpected HW behavior; bad command; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_SERDES_TX_INIT_CAL_TIMEOUT_ERROR = 0x309, /*< code: 0x309 err: Init Cal didn't complete in the prescribed amount of time, cause: No serial traffic present - Check serial link integrity, recovery: Reset JESD link or device, re-run calibration If the problem persists contact ADI. */ + APOLLO_CPU_SERDES_TX_NVM_READING_DATA_ERROR = 0x30a, /*< code: 0x30a err: Reading Tx calibration data from NVM, cause: Unexpected HW behavior; NVM data reading error; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_SERDES_TX_NVM_DATA_LENGTH_MISMATCH_ERROR = 0x30b, /*< code: 0x30b err: NVM data length mismatch, cause: Unexpected HW behavior; NVM data error; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_SERDES_TX_HW_STARTUP_ERROR = 0x30c, /*< code: 0x30c err: HW start-up error, cause: Unexpected HW behavior; start-up error; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_SERDES_TX_NVM_DATA_NOT_FUSED_ERROR = 0x30d, /*< code: 0x30d err: NVM data not fused, cause: Unexpected HW behavior; NVM data error; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_MCS_INVALID_MODE_ERROR = 0x401, /*< code: 0x401 err: The mode requested by the user is invalid, cause: MCS mode is invalid, recovery: Check provided configuration (MCS FW mode) */ + APOLLO_CPU_MCS_WRONG_REFERENCE_PERIOD_ERROR = 0x402, /*< code: 0x402 err: The reference period configuration given by the user is wrong, cause: one of the reference sysref period is zero, recovery: Check provided reference period configuration */ + APOLLO_CPU_MCS_WRONG_OFFSET_ERROR = 0x403, /*< code: 0x403 err: The offset configuration given by the user is wrong, cause: one of the offsets is larger than one-fourth internal sysref period, recovery: Check provided offset configuration */ + APOLLO_CPU_MCS_WRONG_STATE_BEFORE_RUN_ERROR = 0x404, /*< code: 0x404 err: MCS FW set in an unexpected state before running, cause: MCS FW state machine is not in start or end, recovery: Try running MCS FW again. Wait for MCS state to become start or end */ + APOLLO_CPU_MCS_REACHED_INVALID_STATE_ERROR = 0x405, /*< code: 0x405 err: Multi-chip Sync (MCS) FW reached an invalid state during execution., cause: Possible actions: Configure SysRefs with Faster Periods, Reduce decRate, handle as warning and poll done bit, recovery: invalid parameter passed */ + APOLLO_CPU_MCS_SYNC_TIMEOUT_ERROR = 0x406, /*< code: 0x406 err: Synchronization timeout, cause: Check clock, sysref, and subclass configuration, recovery: Turn on clock and/or sysref signals and try again */ + APOLLO_CPU_MCS_FW_FAILED_ERROR = 0x407, /*< code: 0x407 err: Multi-chip Sync (MCS) FW failed to complete synchronization in the allotted time., cause: Possible actions: Configure SysRefs with Faster Periods, Reduce decRate, handle as warning and poll done bit, recovery: invalid parameter passed */ + APOLLO_CPU_MCS_CONFIG_DATA_LENGTH_AND_OFFSET_ERROR = 0x408, /*< code: 0x408 err: Wrong configuration size, cause: No config change has been made, recovery: Check provided configuration */ + APOLLO_CPU_MCS_CTRL_CMD_INVALID_PARAMETER_ERROR = 0x409, /*< code: 0x409 err: Wrong configuration ID, cause: No config change has been made, recovery: Check provided configuration */ + APOLLO_CPU_MCS_INVALID_BSYNC_MODE_ERROR = 0x40a, /*< code: 0x40a err: The mode requested by the user is invalid, cause: MCS BSYNC mode is invalid, recovery: Check provided configuration (MCS BSYNC mode) */ + APOLLO_CPU_MCS_ALREADY_RUNNING_CAL_ERROR = 0x40b, /*< code: 0x40b err: Requested to run a cal when in the middle of a cal, cause: Must wait until currently running cal completes, recovery: Check interface */ + APOLLO_CPU_MCS_CTRL_INVALID_CMD_ERROR = 0x40c, /*< code: 0x40c err: Wrong command ID, cause: No config change has been made, recovery: Check provided command */ + APOLLO_CPU_MCS_SYSREF_WITHIN_KEEPOUT_WINDOW_ERROR = 0x40d, /*< code: 0x40d err: External SysRef is within the Keep-Out Window, cause: SysRef Alignment did not complete, recovery: Provide an updated time-difference offset, Increase decRate, or adjust the timing of External SysRef and clock to ensure External SysRef is well-sampled */ + APOLLO_CPU_MCS_GPIO_MISCONFIGURATION_ERROR = 0x40e, /*< code: 0x40e err: DELADJ or DELSTR GPIO numbers are not valid, cause: The provided GPIO configuration is not supported., recovery: Check GPIO configuration */ + APOLLO_CPU_MCS_MEASUREMENT_ERROR = 0x40f, /*< code: 0x40f err: MCS measurement error, cause: MCS module was not able to complete a measurement., recovery: Check MCS configuration */ + APOLLO_CPU_MCS_TRACKING_NEEDS_INIT_ERROR = 0x410, /*< code: 0x410 err: Must run initial cal before tracking, cause: Did not successfully complete initial MCS cal, recovery: Check interface */ + APOLLO_CPU_LINEARX_RX_ALREADY_RUNNING_CAL_ERROR = 0x580, /*< code: 0x580 err: Requested to run a cal when in the middle of a cal, cause: Must wait until currently running cal completes, recovery: Check interface */ + APOLLO_CPU_LINEARX_RX_CAL_TIMEOUT_ERROR = 0x581, /*< code: 0x581 err: Cal timed-out, cause: Unexpected HW behavior; Cal did not finish in expected time; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_LINEARX_RX_CTRL_FSM_CMD_NOT_SUPPORTED_ERROR = 0x582, /*< code: 0x582 err: Command not supported, cause: The used parameter is not supported, recovery: Correct the parameter and rerun */ + APOLLO_CPU_LINEARX_RX_CTRL_SET_FSM_CMD_ERROR = 0x583, /*< code: 0x583 err: Wrong command sequence, cause: Unexpected command sequence or wrong pre-conditions, recovery: Check interface */ + APOLLO_CPU_LINEARX_RX_CTRL_RUN_ERROR = 0x584, /*< code: 0x584 err: Control wrapper error, cause: Wrong configuration or signal conditioning., recovery: Review error and status registers. */ + APOLLO_CPU_LINEARX_RX_DISABLED_ERROR = 0x585, /*< code: 0x585 err: The ctrl or config cmd only works when Linearx is enabled, cause: cmd only works when Linearx is enabled, recovery: Check feature */ + APOLLO_CPU_CFG_DEVICE_PROFILE_CRC_ERROR = 0x8001, /*< code: 0x8001 err: Failed CRC verification, cause: Programmed image is corrupted. Original image may be invalid or may have been corrupted during SPI transfer., recovery: Reprogram the device profile image. */ + APOLLO_CPU_CFG_DEVICE_PROFILE_MISSING_DATA_ERROR = 0x8002, /*< code: 0x8002 err: Missing data for enabled channel, cause: Invalid device profile, recovery: invalid parameter passed */ + APOLLO_CPU_CFG_DEVICE_PROFILE_VERSION_MISMATCH_ERROR = 0x8003, /*< code: 0x8003 err: Version mismatch, cause: Invalid device profile, recovery: invalid parameter passed */ + APOLLO_CPU_STRM_DRV_INVALID_PARAM_ERROR = 0xb101, /*< code: 0xb101 err: Invalid input parameters, cause: One or more input parameters are not valid, recovery: Firmware programmatic error. Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_STRM_DRV_TIMEOUT_ERROR = 0xb102, /*< code: 0xb102 err: Timer expired waiting for stream completion, cause: The stream timeout can occur due to stream processor waiting for other streams to complete., recovery: The stream execution is timed out. Rerun the feature to recover from this error. */ + APOLLO_CPU_STRM_DRV_GENERAL_ERROR = 0xb103, /*< code: 0xb103 err: Triggered stream reported an error, cause: The stream that is triggered either through firmware or API has generated an error., recovery: Rerun feature to recover from this error */ + APOLLO_CPU_STRM_DRV_CRC_ERROR = 0xb104, /*< code: 0xb104 err: Failed CRC verification, cause: Programmed image is corrupted. Original image may be invalid or may have been corrupted during SPI transfer., recovery: Reprogram the stream image. - Alternate explanation - err: Failed CRC verification, cause: The failure could be due to bit errors in SPI interface., recovery: Rerun feature to recover from this error */ + APOLLO_CPU_STRM_DRV_STM_REP_FIFO_ERROR = 0xb105, /*< code: 0xb105 err: Stream Processor reported a FIFO error, cause: The stream FIFO is full. This could happen due to back to back streams being triggered., recovery: Rerunning the feature could solve the issue. */ + APOLLO_CPU_STRM_DRV_STM_REP_EXT_TIMER_ERROR = 0xb106, /*< code: 0xb106 err: Stream Processor reported an external timer error, cause: External timer started by stream failed. This could fail if no external timers available., recovery: Rerunning the feature could solve the issue. */ + APOLLO_CPU_STRM_DRV_STM_REP_INV_INSTR_ERROR = 0xb107, /*< code: 0xb107 err: Stream Processor reported an invalid instruction., cause: This could happen if the stream is corrupted or stream is generated wrongly, recovery: Recreate the stream and reprogram the device. If the problem persists contact ADI. */ + APOLLO_CPU_STRM_DRV_STM_REP_INV_AHB_ADDR_ERROR = 0xb108, /*< code: 0xb108 err: Stream Processor reported an invalid AHB address, cause: Wrong AHB address is accessed in the stream., recovery: Recreate the stream and reprogram the device. If the problem persists contact ADI. */ + APOLLO_CPU_STRM_DRV_STM_REP_INV_STREAM_NUM_ERROR = 0xb109, /*< code: 0xb109 err: Stream Processor reported an invalid stream number, cause: Invalid stream number called from stream or firmware, recovery: Recreate the stream and reprogram the device. If the problem persists contact ADI. */ + APOLLO_CPU_STRM_DRV_STM_REP_STACK_OVERFLOW_ERROR = 0xb10a, /*< code: 0xb10a err: Stream Processor reported a stack overflow, cause: Too many nested calls in the stream can cause this, recovery: Recreate the stream and reprogram the device. If the problem persists contact ADI. */ + APOLLO_CPU_STRM_DRV_STM_REP_TIMEOUT_ERROR = 0xb10b, /*< code: 0xb10b err: Stream Processor reported a timeout error, cause: The stream did not complete within the set timeout period, recovery: Recreate the stream and reprogram the device. If the problem persists contact ADI. */ + APOLLO_CPU_STRM_DRV_STM_REP_CHECK_INSTR_ERROR = 0xb10c, /*< code: 0xb10c err: Stream Processor reported a check instruction error, cause: This could happen if a wrong instruction is used in the stream., recovery: Recreate the stream and reprogram the device. If the problem persists contact ADI. */ + APOLLO_CPU_STRM_DRV_STM_REP_INV_SPI_ADDR_ERROR = 0xb10d, /*< code: 0xb10d err: Stream Processor reported an invalid SPI address, cause: Invalid SPI addess accessed in the stream., recovery: Recreate the stream and reprogram the device. If the problem persists contact ADI. */ + APOLLO_CPU_STRM_DRV_PREV_STM_TIMEOUT_ERROR = 0xb10e, /*< code: 0xb10e err: Previous Stream didn't finish, cause: The previous stream started by the stream processor or firmware did not finish, recovery: Rerun the feature. If the problem persists contact ADI. */ + APOLLO_CPU_STRM_DRV_FUNC_NOT_SUPPORTED_ERROR = 0xb10f, /*< code: 0xb10f err: Function not supported, cause: The functionality is not yet supported., recovery: Recreate the stream and reprogram the device. If the problem persists contact ADI. */ + APOLLO_CPU_MASTER_BIAS_PTAT_CAL_FAILED_ERROR = 0xb301, /*< code: 0xb301 err: RB0 Ptat calibration failed, cause: Unexpected failure in resistor trim logic, or no clock provided to trim logic., recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_MASTER_BIAS_PTAT_R_TXBBF_INVALID_ERROR = 0xb302, /*< code: 0xb302 err: Invalid Ptat resistor value for TxBBF, cause: Ptat trim calibration generated an out-of-range result, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_MASTER_BIAS_PTAT_R_UPC_INVALID_ERROR = 0xb303, /*< code: 0xb303 err: Invalid Ptat resistor value for UPC, cause: Ptat trim calibration generated an out-of-range result, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_MASTER_BIAS_PTAT_R_UPC_BIAS_INVALID_ERROR = 0xb304, /*< code: 0xb304 err: Invalid Ptat resistor value for UPC BIAS, cause: Ptat trim calibration generated an out-of-range result, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_MASTER_BIAS_PTAT_R_VGA_INVALID_ERROR = 0xb305, /*< code: 0xb305 err: Invalid Ptat resistor value for VGA, cause: Ptat trim calibration generated an out-of-range result, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_MASTER_BIAS_TRIM_PROGRAMMING_FAILED_ERROR = 0xb306, /*< code: 0xb306 err: Invalid Ptat resistor value for VGA, cause: Ptat trim calibration generated an out-of-range result, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_MASTER_BIAS_REQUESTED_DAC_BIAS_INVALID_ERROR = 0xb307, /*< code: 0xb307 err: Invalid DAC bias requested., cause: Invalid DAC bias requested., recovery: Provide valid DAC Bias 0 - 1.25mA, 1 - 5mA. */ + APOLLO_CPU_MASTER_BIAS_RC_TUNER_PROGRAMMING_FAILED_ERROR = 0xb308, /*< code: 0xb308 err: Invalid cap or resistor value for RC tuner, cause: RC tuner calibration generated an out-of-range result, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_MASTER_BIAS_RC_TUNER_CAL_FAILED_ERROR = 0xb309, /*< code: 0xb309 err: Calibration not completed., cause: A0 does not supports RC Tuner cal in single clock mode., recovery: invalid parameter passed */ + APOLLO_CPU_VCO_LDO_LOWOUTPUT_ERROR = 0xb401, /*< code: 0xb401 err: LDO output voltage is below low side of target range, cause: VCO LDO bypass capacitor is shorted to GND, recovery: Check board layout. If the problem persists contact ADI. - Alternate explanation - err: Unexpected LDO hardware behavior, cause: Unknown cause, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_VCO_LDO_UVL_ERROR = 0xb402, /*< code: 0xb402 err: Input supply voltage is below low side of target range, cause: Input supply voltage is below undervoltage-lockout threshold, recovery: Check the input supply voltage and try again. If the problem persists contact ADI. */ + APOLLO_CPU_VCO_LDO_NOREF_ERROR = 0xb403, /*< code: 0xb403 err: Reference input voltage below low side of target range, cause: Unexpected HW behavior; Unexpected hardware behavior, reference input voltage below low side of target range; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_VCO_LDO_THERMSDN_ERROR = 0xb404, /*< code: 0xb404 err: Temperature is above high side of target range, cause: Temperature is above high side of target range, recovery: Check board layout. If the problem persists contact ADI. - Alternate explanation - err: Unexpected LDO hardware behavior, cause: Unknown cause, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_VCO_LDO_CURLIM_ERROR = 0xb405, /*< code: 0xb405 err: Load current is above high side of target range dictated by VCO, cause: VCO LDO bypass capacitor is shorted to GND, recovery: Check board layout. If the problem persists contact ADI. - Alternate explanation - err: Unexpected LDO hardware behavior, cause: Unknown cause, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_VCO_LDO_OVERVOLT_ERROR = 0xb406, /*< code: 0xb406 err: LDO output voltage is above high side of target range, cause: VCO LDO bypass capacitor is shorted to VDD, recovery: Check board layout. If the problem persists contact ADI. - Alternate explanation - err: Unexpected LDO hardware behavior, cause: Unknown cause, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_SHUNT_LDO_SLDO1P0_UV_ERROR = 0xb407, /*< code: 0xb407 err: LDO output voltage is below low threshold, cause: PD bit =1 or Rampup Bit =0 or Master Bias/LCR is not up, recovery: Reset device If the problem persists contact ADI. - Alternate explanation - err: Unexpected LDO hardware behavior, cause: Unknown cause, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_SHUNT_LDO_SLDO1P0_OV_ERROR = 0xb408, /*< code: 0xb408 err: LDO output voltage is above high threshold, cause: Unexpected HW behavior; PD bit =1 or Unexpected hardware behavior; report to ADI, recovery: Reset device. If the problem persists contact ADI. */ + APOLLO_CPU_SHUNT_LDO_SLDO1P0_POWER_NOT_OK_ERROR = 0xb409, /*< code: 0xb409 err: LDO output voltage is not good., cause: Unexpected hardware behavior, under and over voltage status bits are set, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_SHUNT_LDO_SLDO0P8_POWER_NOT_OK_ERROR = 0xb40a, /*< code: 0xb40a err: LDO output voltage below the targeted threshold, cause: LDO output does not power up at all or it may need longer wait time to power up to the targeted threshold., recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_VCO_LDO_BAD_STATE_ERROR = 0xb40b, /*< code: 0xb40b err: LDO logic controller failure, cause: LDO logic controller is in a bad state, recovery: Check board layout. If the problem persists contact ADI. - Alternate explanation - err: Unexpected LDO hardware behavior, cause: Unknown cause, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_DWT_DRV_NOT_INITIALIZED_ERROR = 0xb501, /*< code: 0xb501 err: Data Watchpoint and Trace (DWT)) driver not initialized, cause: HW doesn't support the DWT the driver is expecting, recovery: Reprogram the device using a valid package and try again. If the problem persists contact ADI. */ + APOLLO_CPU_DEV_TEMP_SENSOR_INVALID_AVGMASK_ERROR = 0xb601, /*< code: 0xb601 err: HAL Invalid Average Mask, cause: parameter out of range, recovery: parameter should be > 0 and < 256, see adi_apollo_DevTempSensor_e in the API */ + APOLLO_CPU_DEV_TEMP_SENSOR_TIMEOUT_CLKGEN_ERROR = 0xb602, /*< code: 0xb602 err: HAL Temp sensor for Clk Gen PLL conversion timeout, cause: Hardware was unable to acquire temperature sample within time limit, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_DEV_TEMP_SENSOR_TIMEOUT_SERDES_ERROR = 0xb603, /*< code: 0xb603 err: HAL Temp sensor for SERDES PLL conversion timeout, cause: Hardware was unable to acquire temperature sample within time limit, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_DEV_TEMP_SENSOR_TIMEOUT_ANA_MPU_A_ERROR = 0xb604, /*< code: 0xb604 err: HAL Temp sensor for ana_mpu_top_A conversion timeout, cause: Hardware was unable to acquire temperature sample within time limit, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_DEV_TEMP_SENSOR_TIMEOUT_ANA_MPU_B_ERROR = 0xb605, /*< code: 0xb605 err: HAL Temp sensor for ana_mpu_top_B conversion timeout, cause: Hardware was unable to acquire temperature sample within time limit, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_DEV_TEMP_SENSOR_TIMEOUT_LPU_VENUS_A_ERROR = 0xb606, /*< code: 0xb606 err: HAL Temp sensor for lpu_venusdual_r0_A conversion timeout, cause: Hardware was unable to acquire temperature sample within time limit, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_DEV_TEMP_SENSOR_TIMEOUT_CK_DIST_CORNER_A_ERROR = 0xb607, /*< code: 0xb607 err: HAL Temp sensor for ck_dist_corner_A conversion timeout, cause: Hardware was unable to acquire temperature sample within time limit, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_DEV_TEMP_SENSOR_TIMEOUT_LPU_VENUS_B_ERROR = 0xb608, /*< code: 0xb608 err: HAL Temp sensor for lpu_venusdual_r0_B conversion timeout, cause: Hardware was unable to acquire temperature sample within time limit, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_DEV_TEMP_SENSOR_TIMEOUT_CK_DIST_CORNER_B_ERROR = 0xb609, /*< code: 0xb609 err: HAL Temp sensor for ck_dist_corner_B conversion timeout, cause: Hardware was unable to acquire temperature sample within time limit, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_DEV_TEMP_SENSOR_TIMEOUT_CK_DIST_CENTER_ERROR = 0xb60a, /*< code: 0xb60a err: HAL Temp sensor for ck_dist_center conversion timeout, cause: Hardware was unable to acquire temperature sample within time limit, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_DEV_TEMP_SENSOR_INVALID_EN_ERROR = 0xb60b, /*< code: 0xb60b err: HAL Invalid Temp sensor Enable bit, cause: parameter out of range, recovery: Temp Sensor is not on the accessed core, see adi_apollo_DevTempSensor_e in the API */ + APOLLO_CPU_PLL_CLKGEN_SYNTH_LOCK_FAILED_ERROR = 0xb701, /*< code: 0xb701 err: Clk PLL Synth Lock Failed, cause: Unexpected hardware behavior, hardware lock detection timeout, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_PLL_RANGE_ERROR = 0xb702, /*< code: 0xb702 err: User Input freq out of range, cause: Specified frequency by the user was out of range, recovery: invalid parameter passed */ + APOLLO_CPU_PLL_INVALID_PLL_ERROR = 0xb703, /*< code: 0xb703 err: User specified invalid PLL type, cause: Specified PLL name by the user was incorrect, recovery: invalid parameter passed */ + APOLLO_CPU_PLL_NOT_ENABLED_ERROR = 0xb704, /*< code: 0xb704 err: Selected PLL was Not Enabled, cause: Selected PLL not enabled, recovery: invalid parameter passed */ + APOLLO_CPU_PLL_VCO_CAL_FAILED_ERROR = 0xb705, /*< code: 0xb705 err: VCO calibration failed, cause: Unexpected hardware behavior, hardware VCO calibration timeout, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_PLL_INVALID_LOOPFILTER_PARAM_ERROR = 0xb706, /*< code: 0xb706 err: Invalid Loopfilter parameters, phase of BW out of range., cause: Specified Loopfilter parameters out of range, recovery: invalid parameter passed */ + APOLLO_CPU_PLL_CP_CAL_FAILED_ERROR = 0xb707, /*< code: 0xb707 err: CP calibration failed, cause: Unexpected hardware behavior, hardware CP calibration timeout, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_PLL_BLEED_CAL_FAILED_ERROR = 0xb708, /*< code: 0xb708 err: Bleed ramp calibration failed, cause: Unexpected hardware behavior, hardware Bleed calibration timeout, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_PLL_INVALID_RX_LEAF_ERROR = 0xb709, /*< code: 0xb709 err: Invalid Rx Leaf hardware setting, the selected freq could not be realized., cause: Specified RX frequency could not be realized, recovery: invalid parameter passed */ + APOLLO_CPU_PLL_INVALID_TX_LEAF_ERROR = 0xb70a, /*< code: 0xb70a err: Invalid Tx Leaf hardware setting, the selected freq could not be realized., cause: Specified TX frequency could not be realized, recovery: invalid parameter passed */ + APOLLO_CPU_PLL_PHASE_SYNC_INVALID_SETTING_ERROR = 0xb70b, /*< code: 0xb70b err: Phase Sync Invalid mode setting, cause: Specified Phase sync mode invalid, recovery: invalid parameter passed */ + APOLLO_CPU_PLL_PHASE_SYNC_TIMEOUT_ERROR = 0xb70c, /*< code: 0xb70c err: Phase Sync timeout, cause: Unexpected hardware behavior, phase sync calibration timeout, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_PLL_PHASE_MISMATCH_ERROR = 0xb70d, /*< code: 0xb70d err: Phase Sync phase mismatch, cause: Unexpected hardware behavior, thase sync Golden counter mismatch, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_PLL_EXT_LO_IN_RANGE_ERROR = 0xb70e, /*< code: 0xb70e err: External LO Input freq out of range, cause: Specified external LO frequncy out of range, recovery: invalid parameter passed */ + APOLLO_CPU_PLL_SWEEPFAIL_ARM_TOO_FAST_ERROR = 0xb70f, /*< code: 0xb70f err: Clk Sweep test fail, Arm clock speed too fast and could not be realized., cause: Unexpected hardware behavior, clk Sweep test fail, ARM speed cannot be realized, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_PLL_TEMPSENSOR_TIMEOUT_ERROR = 0xb710, /*< code: 0xb710 err: PLL temp sensor timeout, cause: Unexpected hardware behavior, PLL temp sensor reading did not finish, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_PLL_MUST_BE_IN_TEST_MODE_ERROR = 0xb711, /*< code: 0xb711 err: PLL Invalid debug mode setting, cause: PLL Attempting to enter a debug mode but not in debug mode, recovery: invalid parameter passed */ + APOLLO_CPU_PLL_PHASE_GCNT_SDM_MCS_TIMEOUT_ERROR = 0xb712, /*< code: 0xb712 err: GCNT SDM Mcs timeout, cause: Unexpected hardware behavior, GCNT SDM Mcs h/w Timeout, recovery: Rerun feature to recover from this error */ + APOLLO_CPU_PLL_PHASE_GCNT_CLKGEN_MCS_TIMEOUT_ERROR = 0xb713, /*< code: 0xb713 err: GCNT ClkGen Mcs timeout, cause: Unexpected hardware behavior, GCNT Clkgen Mcs h/w Timeout, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_PLL_FORCED_ALC_TIMEOUT_ERROR = 0xb714, /*< code: 0xb714 err: Forced ALC Enable-Disable timeout, cause: Unexpected hardware behavior, Forced ALC Enable-Disabled h/w Timeout, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_PLL_SERDES_SYNTH_LOCK_FAILED_ERROR = 0xb715, /*< code: 0xb715 err: Serdes PLL Synth Lock Failed, cause: Unexpected hardware behavior, hardware lock detection timeout, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_JESD_DRV_FRM_LANE_OVERLAP_ERROR = 0xb801, /*< code: 0xb801 err: Serializer lane overlap, cause: Incorrect serializer lane assignment, recovery: invalid parameter passed */ + APOLLO_JESD_DRV_DFRM_LANE_OVERLAP_ERROR = 0xb802, /*< code: 0xb802 err: Deserializer lane overlap, cause: Incorrect deserializer lane assignment, recovery: invalid parameter passed */ + APOLLO_JESD_DRV_FRM_INVALID_SAMPRATE_ERROR = 0xb803, /*< code: 0xb803 err: Framer invalid sample rate, cause: Incorrect framer sample rate in the profile, recovery: invalid parameter passed */ + APOLLO_JESD_DRV_LKSH_INVALID_SAMPRATE_ERROR = 0xb804, /*< code: 0xb804 err: Link sharing invalid sample rate, cause: Incorrect link sharing sample rate in the profile, recovery: invalid parameter passed */ + APOLLO_JESD_DRV_DFRM_INVALID_SAMPRATE_ERROR = 0xb805, /*< code: 0xb805 err: Deframer invalid sample rate, cause: Incorrect deframer sample rate in the profile, recovery: invalid parameter passed */ + APOLLO_JESD_DRV_FRM_SYNC_PAD_CFG_INVALID_ERROR = 0xb806, /*< code: 0xb806 err: Invalid framer Sync Pad configuration, cause: Incorrect framer sync pad configuration provided, recovery: invalid parameter passed */ + APOLLO_JESD_DRV_DFRM_SYNC_PAD_CFG_INVALID_ERROR = 0xb807, /*< code: 0xb807 err: Invalid deframer Sync Pad configuration, cause: Incorrect deframer sync pad configuration provided, recovery: invalid parameter passed */ + APOLLO_JESD_DRV_FRM0_NOT_ENABLED_ERROR = 0xb808, /*< code: 0xb808 err: Framer 0 must be enabled, cause: Framer 0 is not used in the profile, recovery: invalid parameter passed */ + APOLLO_JESD_DRV_FRM_INVALID_SPLXBAR_ENTRY_ERROR = 0xb809, /*< code: 0xb809 err: Invalid framer sample crossbar entry, cause: Invalid framer sample crossbar entry in the profile, recovery: invalid parameter passed */ + APOLLO_JESD_DRV_FRM_INVALID_LINK_LAYER_MODE_ERROR = 0xb80a, /*< code: 0xb80a err: Invalid framer link layer mode of operation, cause: Invalid framer mode parameter in the profile, recovery: invalid parameter passed */ + APOLLO_JESD_DRV_DFRM_INVALID_SPLXBAR_ENTRY_ERROR = 0xb80b, /*< code: 0xb80b err: Invalid deframer sample crossbar entry, cause: Invalid deframer sample crossbar entry in the profile, recovery: invalid parameter passed */ + APOLLO_JESD_DRV_DFRM_INVALID_LINK_LAYER_MODE_ERROR = 0xb80c, /*< code: 0xb80c err: Invalid deframer link layer mode of operation, cause: Invalid deframer mode parameter in the profile, recovery: invalid parameter passed */ + APOLLO_JESD_DRV_FRM_S_NOT_POW2_ERROR = 0xb80d, /*< code: 0xb80d err: Framer S parameter is not a power of 2, cause: Invalid framer S parameter in the profile, recovery: invalid parameter passed */ + APOLLO_JESD_DRV_DFRM_S_NOT_POW2_ERROR = 0xb80e, /*< code: 0xb80e err: Deframer S parameter is not a power of 2, cause: Invalid deframer S parameter in the profile, recovery: invalid parameter passed */ + APOLLO_JESD_DRV_FRM_INVALID_CONFIG_DET_ERROR = 0xb80f, /*< code: 0xb80f err: Invalid framer config detected by JESD hardware block, cause: Invalid framer configuration detected by the JESD hardware block, recovery: invalid parameter passed */ + APOLLO_JESD_DRV_DRFM_INVALID_CONFIG_DET_ERROR = 0xb810, /*< code: 0xb810 err: Invalid deframer config detected by Jesd h/w block, cause: Invalid deframer configuration detected by the JESD hardware block, recovery: invalid parameter passed */ + APOLLO_JESD_DRV_LKSH_INVALID_SPLXBAR_ENTRY_ERROR = 0xb811, /*< code: 0xb811 err: Invalid sample crossbar entry in link sharing profile, cause: Invalid link sharing sample crossbar entry in the profile, recovery: invalid parameter passed */ + APOLLO_JESD_DRV_UNSUPPORTED_FREQ_DIV_RATIO_ERROR = 0xb812, /*< code: 0xb812 err: Unsupported frequency divide ratio, cause: Invalid frequency parameter in the profile, recovery: invalid parameter passed */ + APOLLO_JESD_DRV_INVALID_FREQ_INPUT_ERROR = 0xb813, /*< code: 0xb813 err: Invalid frequency, cause: Invalid frequency parameter provided in the profile, recovery: invalid parameter passed */ + APOLLO_JESD_DRV_FRM_NUM_OF_CONV_INVALID_ERROR = 0xb814, /*< code: 0xb814 err: Invalid number of converters, cause: Invalid number of converters specified in the profile, recovery: invalid parameter passed */ + APOLLO_JESD_DRV_SER_INVALID_LANE_SELECTED_ERROR = 0xb815, /*< code: 0xb815 err: Invalid serializer lane selected, cause: Invalid serializer lane selected, recovery: invalid parameter passed */ + APOLLO_JESD_DRV_SER_INVALID_LANE_PARAMETER_ERROR = 0xb816, /*< code: 0xb816 err: Invalid serializer lane parameter, cause: Invalid serializer lane parameter, recovery: invalid parameter passed */ + APOLLO_UART_DRV_INVALID_SCLK_FREQ_ERROR = 0xb901, /*< code: 0xb901 err: Invalid SCLK freq, cause: SCLK is too low for configured UART bit rate, check device clock setting., recovery: invalid parameter passed */ + APOLLO_GPIO_DRV_INVALID_SIGNAL_ID_ERROR = 0xbc01, /*< code: 0xbc01 err: Invalid signal ID provided, cause: Invalid signal ID provided, recovery: invalid parameter passed */ + APOLLO_GPIO_DRV_INVALID_PIN_ID_ERROR = 0xbc02, /*< code: 0xbc02 err: Invalid GPIO pin number provided, cause: Invalid GPIO pin number provided, recovery: invalid parameter passed */ + APOLLO_HSCI_DRV_UNKNOWN_COMMAND_ERROR = 0xbd00, /*< code: 0xbd00 err: Unknown HSCI command received, cause: Unexpected HSCI error encountered, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_HSCI_DRV_BAD_PARITY_DETECTED_ERROR = 0xbd01, /*< code: 0xbd01 err: Bad parity detected, cause: Unexpected HSCI error encountered, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_HSCI_DRV_ADDRESS_SIZE_ERROR = 0xbd02, /*< code: 0xbd02 err: More Than 4 address bytes are received, cause: Unexpected HSCI error encountered, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_HSCI_DRV_BYTE_NUM_SIZE_ERROR = 0xbd03, /*< code: 0xbd03 err: More Than 3 byte_num bytes are received, cause: Unexpected HSCI error encountered, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_HSCI_DRV_WRITE_FIFO_FULL_ERROR = 0xbd04, /*< code: 0xbd04 err: Write FIFO becomes full, cause: Unexpected HSCI error encountered, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_HSCI_DRV_READ_FIFO_FULL_ERROR = 0xbd05, /*< code: 0xbd05 err: Read FIFO becomes full, cause: Unexpected HSCI error encountered, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_HSCI_DRV_HREADY_TIMEOUT_ERROR = 0xbd06, /*< code: 0xbd06 err: HREADY time out, cause: Unexpected HSCI error encountered, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_HSCI_DRV_AHB_BUS_TRANSACTION_ERROR = 0xbd07, /*< code: 0xbd07 err: AHB bus transaction error, cause: Unexpected HSCI error encountered, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_SYSCLK_DRV_SKEW_NOT_CORRECTED_AT_CLOCK_RECEIVER_ERROR = 0xbe01, /*< code: 0xbe01 err: skew not corrected at clock receiver, cause: user supplied clock has bad skew, recovery: invalid parameter passed */ + APOLLO_SYSCLK_DRV_MAX_CORRECTION_VALUE_REACHED_AT_TL_ERROR = 0xbe02, /*< code: 0xbe02 err: very bad skew or dc in the clock supplied, cause: user supplied clock has bad skew or dc., recovery: invalid parameter passed */ + APOLLO_SYSCLK_DRV_CONDITIONING_FAILED_ERROR = 0xbe03, /*< code: 0xbe03 err: clock is not corrected/conditioned, cause: user supplied clock can't be corrected., recovery: Reset device If the problem persists contact ADI. */ + APOLLO_SYSCLK_DRV_INCORRECT_ARM_CLOCK_FREQ_ERROR = 0xbe04, /*< code: 0xbe04 err: Clock is not switched from Ring osc, cause: user requested arm clk freq is > 500 MHZ, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_SYSCLK_DRV_INVALID_CLK_PATH_SEGMENT_ERROR = 0xbe05, /*< code: 0xbe05 err: invalid clock path segment, cause: user requested to calibrate invalid clock path segment, recovery: invalid parameter passed */ + APOLLO_SYSCLK_DRV_CONDITIONING_MAX_REACHED_ERROR = 0xbe06, /*< code: 0xbe06 err: clock is not corrected/conditioned, cause: cause: max correction code is reached,, recovery: recovery: Handle error as warning, Reset device If the problem persists contact ADI. */ + APOLLO_TE_DRV_GET_VERSION_FAILED_ERROR = 0xbf01, /*< code: 0xbf01 err: failed on getting TE version, cause: Unexpected or unhandled TE mailbox error encountered, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_TE_DRV_ENABLE_FEATURES_FAILED_ERROR = 0xbf02, /*< code: 0xbf02 err: failed on enabling features, cause: Unexpected or unhandled TE mailbox error encountered, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_TE_DRV_GET_ENABLED_FEATURES_FAILED_ERROR = 0xbf03, /*< code: 0xbf03 err: failed on getting enabled features, cause: Unexpected or unhandled TE mailbox error encountered, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_TE_DRV_INVALID_CHALLENGE_TYPE_ERROR = 0xbf04, /*< code: 0xbf04 err: Invalid challenge type, cause: User inputs invalid challenge type, recovery: invalid parameter passed */ + APOLLO_TE_DRV_REQUEST_CHALLENGE_FAILED_ERROR = 0xbf05, /*< code: 0xbf05 err: failed on requesting challenge, cause: Unexpected or unhandled TE mailbox error encountered, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_TE_DRV_SECURE_DEBUG_ACCESS_FAILED_ERROR = 0xbf06, /*< code: 0xbf06 err: failed on securing debug access, cause: Unexpected or unhandled TE mailbox error encountered, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_TE_DRV_SET_RMA_FAILED_ERROR = 0xbf07, /*< code: 0xbf07 err: failed on setting RMA, cause: Unexpected or unhandled TE mailbox error encountered, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_SYSTEM_GP_TIMER_ERROR = 0xff01, /*< code: 0xff01 err: General-purpose timer error, cause: Software Timer allocation failure., recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_SYSTEM_MAILBOX_ERROR = 0xff02, /*< code: 0xff02 err: Mailbox generic error, cause: Unexpected or unhandled mailbox error encountered, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_SYSTEM_MAILBOX_BUSY_ERROR = 0xff03, /*< code: 0xff03 err: Mailbox busy error, cause: The requested mailbox hardware is in use and cannot receive commands, recovery: Rerun feature to recover from this error */ + APOLLO_CPU_SYSTEM_MAILBOX_INVALID_HANDLE_ERROR = 0xff04, /*< code: 0xff04 err: Mailbox handle invalid, cause: Mailbox operation requested on an invalid mailbox, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_SYSTEM_MAILBOX_INVALID_CMD_ID_ERROR = 0xff05, /*< code: 0xff05 err: Mailbox invalid command id, cause: An unhandled command ID was provided, recovery: Check feature */ + APOLLO_CPU_SYSTEM_MAILBOX_LINK_BUSY_ERROR = 0xff06, /*< code: 0xff06 err: Mailbox link busy, cause: The requested mailbox link is in use and cannot receive commands, recovery: Rerun feature to recover from this error */ + APOLLO_CPU_SYSTEM_MAILBOX_CMD_TOO_LARGE_ERROR = 0xff07, /*< code: 0xff07 err: Mailbox command too large for link buffer, cause: Command payload is unexpectedly too large for mailbox buffer, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_SYSTEM_MAILBOX_INVALID_CMD_PARAM_ERROR = 0xff08, /*< code: 0xff08 err: Mailbox invalid command parameter(s) supplied, cause: Mailbox received a command with invalid or out of range parameters(s), recovery: Rerun feature to recover from this error */ + APOLLO_CPU_SYSTEM_INVALID_CPU_ID_ERROR = 0xff09, /*< code: 0xff09 err: Invalid CPU ID specified, cause: Given CPU ID parameter is invalid., recovery: Reprogram the CPU firmware image. If the problem persists contact ADI. */ + APOLLO_CPU_SYSTEM_NULL_PTR_ERROR = 0xff0a, /*< code: 0xff0a err: Null pointer provided, cause: Programmed image is corrupted. Original image may be invalid or may have been corrupted during SPI transfer., recovery: Reprogram the CPU firmware image. If the problem persists contact ADI. */ + APOLLO_CPU_SYSTEM_TASK_CREATE_ERROR = 0xff0b, /*< code: 0xff0b err: O/S Task create error, cause: This can happen if wrong parameters are passed to the Task Create API, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_SYSTEM_CAPTURE_RAM_LOCK_ERROR = 0xff0c, /*< code: 0xff0c err: Failed to lock specified capture RAM, cause: API failed to lock ram access, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_SYSTEM_CAPTURE_RAM_UNLOCK_ERROR = 0xff0d, /*< code: 0xff0d err: Failed to unlock specified capture RAM, cause: API failed to unlock ram for access, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_SYSTEM_CTRL_CMD_ARG_INVALID_ERROR = 0xff0e, /*< code: 0xff0e err: The Ctrl Cmd argument is not valid, cause: A wrong value is input by the user as the argument, recovery: Verify command argument is correct and try again. */ + APOLLO_CPU_SYSTEM_INIT_CAL_INIT_ERROR = 0xff0f, /*< code: 0xff0f err: Init cal framework initialization error, cause: Unexpected error encountered during init cal framework initialization., recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_SYSTEM_MAILBOX_TIMEOUT_CORE0_ERROR = 0xff10, /*< code: 0xff10 err: Inter-processor mailbox timeout, cause: Core-1 didn't received an answer from a command it sent to Core-0, recovery: Rerun feature to recover from this error */ + APOLLO_CPU_SYSTEM_INIT_CAL_ABORTED_ERROR = 0xff14, /*< code: 0xff14 err: Init cal interrupted by ABORT command, cause: Init cal is aborted due to a ABORT command, recovery: Rerun the init cals. */ + APOLLO_CPU_SYSTEM_INIT_CAL_WARM_BOOT_CHKSUM_ERROR = 0xff15, /*< code: 0xff15 err: Init cal warm boot checksum error, cause: Init cal data image is corrupted., recovery: Rerun init cal */ + APOLLO_CPU_SYSTEM_INIT_CAL_INV_CHAN_MASK_ERROR = 0xff16, /*< code: 0xff16 err: Init cal invalid channel mask error, cause: Channel numbers that are not enabled in the profile are selected in the channel mask., recovery: Rerun the init cal with correct channel mask. */ + APOLLO_CPU_SYSTEM_INIT_CAL_INV_CAL_MASK_ERROR = 0xff17, /*< code: 0xff17 err: Init cal invalid cal mask error, cause: The Init cal mask might have unsupported cals., recovery: Rerun the init cal with correct cal mask. */ + APOLLO_CPU_SYSTEM_INIT_CAL_ALREADY_IN_PROGRESS_ERROR = 0xff18, /*< code: 0xff18 err: Init cal already in progress, cause: The Init cal command is sent again while one is in progress, recovery: Make sure not to send the init cal command while one is in progress. */ + APOLLO_CPU_SYSTEM_EFUSE_PROFILE_ERROR = 0xff19, /*< code: 0xff19 err: Profile checksum failed or bad profile wrt to EFUSE, cause: The Device Profile image is corrupted. Original image may be invalid or may have been corrupted during SPI transfer., recovery: Reprogram the Device Profile image. If the problem persists contact ADI. */ + APOLLO_CPU_SYSTEM_EVENT_CREATE_ERROR = 0xff1c, /*< code: 0xff1c err: Could not create the event, cause: This can happen if wrong parameters are passed to the OS call., recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_SYSTEM_QUEUE_CREATE_ERROR = 0xff1d, /*< code: 0xff1d err: Could not create the Queue, cause: This can happen if wrong parameters are passed to the OS call., recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_SYSTEM_TIMER_CREATE_ERROR = 0xff1e, /*< code: 0xff1e err: Could not create the timer, cause: This can happen if wrong parameters are passed to the OS call., recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_SYSTEM_QUEUE_POST_ERROR = 0xff1f, /*< code: 0xff1f err: Failed to post the message, cause: This can happen if the queue is full., recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_SYSTEM_QUEUE_RECV_ERROR = 0xff20, /*< code: 0xff20 err: Failed to receive the message, cause: This can happen if wrong parameters are passed to the OS call., recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_SYSTEM_RPC_MGR_RECV_ERROR = 0xff21, /*< code: 0xff21 err: RPC manager failed to receive the message from the other core, cause: Check if the other core is running., recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_SYSTEM_RPC_MGR_TRANSMIT_ERROR = 0xff22, /*< code: 0xff22 err: RPC manager failed to transmit the message to the other core, cause: This can happen if wrong parameters are passed to the OS call., recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_SYSTEM_STACK_OVERFLOW_ERROR = 0xff23, /*< code: 0xff23 err: Task stack overflow, cause: This can happen if the OS configuration is corrupted., recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_SYSTEM_TASK_DOES_NOT_EXIST_ERROR = 0xff24, /*< code: 0xff24 err: Commands sent to task that does not exist, cause: This can happen if a command is sent to a channel that is not enabled in the profile or disabled., recovery: Rerun the feature with the correct channel mask. */ + APOLLO_CPU_SYSTEM_CTRL_TASK_INVALID_MSG_ERROR = 0xff25, /*< code: 0xff25 err: Invalid message passed to ctrl task, cause: This can happen if an unsupported command is sent., recovery: Rerun the feature with the correct command. */ + APOLLO_CPU_SYSTEM_INSUFFICIENT_MEMORY_ERROR = 0xff26, /*< code: 0xff26 err: Insufficient memory available for the requested operation, cause: This can happen if an insufficient buffer size is sent for a command. For example get config or get cal status., recovery: Rerun the command with the correct buffer size allocated. */ + APOLLO_CPU_SYSTEM_CTRL_FUNC_NOT_SUPPORTED_ERROR = 0xff27, /*< code: 0xff27 err: The given cal does not support the control function, cause: The control command that is not supported is sent to the cal., recovery: Rerun the command with the correct control command. */ + APOLLO_CPU_SYSTEM_SET_CONFIG_FUNC_NOT_SUPPORTED_ERROR = 0xff28, /*< code: 0xff28 err: The given cal does not support the set config function, cause: The set configuration command is sent to the cal which does not support it., recovery: invalid parameter passed */ + APOLLO_CPU_SYSTEM_GET_CONFIG_FUNC_NOT_SUPPORTED_ERROR = 0xff29, /*< code: 0xff29 err: The given cal does not support the get config function, cause: The get configuration command is sent to the cal which does not support it., recovery: invalid parameter passed */ + APOLLO_CPU_SYSTEM_STATUS_FUNC_NOT_SUPPORTED_ERROR = 0xff2a, /*< code: 0xff2a err: The given cal does not support the get status function, cause: The get status command is sent to the cal which does not support it., recovery: invalid parameter passed */ + APOLLO_CPU_SYSTEM_INVALID_CHANNEL_MASK_ERROR = 0xff2b, /*< code: 0xff2b err: The given channel is not enabled in the profile, cause: This can happen if a channel is not enabled in the profile is getting enabled or disabled., recovery: invalid parameter passed */ + APOLLO_CPU_SYSTEM_INVALID_CONFIG_OBJECT_ERROR = 0xff2c, /*< code: 0xff2c err: The given target configuration object is invalid, cause: This can happen if the set configuration command is sent with a wrong configuration object ID., recovery: invalid parameter passed */ + APOLLO_CPU_SYSTEM_INVALID_CONFIG_SIZE_ERROR = 0xff2d, /*< code: 0xff2d err: The given configuration size is invalid, cause: This can happen if the set configuration command is sent with wrong configuration size., recovery: invalid parameter passed */ + APOLLO_CPU_SYSTEM_INVALID_CONFIG_OFFSET_ERROR = 0xff2e, /*< code: 0xff2e err: The given configuration offset is invalid, cause: This can happen if the set or get configuration command is sent with wrong offset into the configuration structure., recovery: invalid parameter passed */ + APOLLO_CPU_SYSTEM_INVALID_CONFIG_STATE_ERROR = 0xff2f, /*< code: 0xff2f err: The config cannot be updated in current state of module., cause: The framework configuration cannot be changed when the init cals are running., recovery: Rerun the configuration command after the init cals are complete. */ + APOLLO_CPU_SYSTEM_INVALID_PACK_MASK_ERROR = 0xff30, /*< code: 0xff30 err: The given pack is invalid or not enabled in the profile, cause: This can happen if a pack is invalid or not enabled in the profile is getting enabled or disabled., recovery: invalid parameter passed */ + APOLLO_CPU_SYSTEM_HAL_FUNC_NOT_IMPLEMENTED_ERROR = 0xff51, /*< code: 0xff51 err: HAL Functionality not implemented, cause: HAL functionality encountered has not been implemented in ARM FW, recovery: Firmware update may be required. If the problem persists contact ADI. */ + APOLLO_CPU_SYSTEM_HAL_INVALID_CHANNEL_ERROR = 0xff52, /*< code: 0xff52 err: HAL Invalid channel, cause: Invalid channel configuration in profile or an invalid channel requested., recovery: Verify channel configuration and reprogram the Device Profile image. */ + APOLLO_CPU_SYSTEM_HAL_INVALID_LO_ERROR = 0xff53, /*< code: 0xff53 err: HAL Invalid LO, cause: Invalid PLL chosen for LO. This could be due to corrupted program memory., recovery: Reprogram the CPU firmware image. If the problem persists contact ADI. */ + APOLLO_CPU_SYSTEM_AHB_COMMON_INVALID_ERROR = 0xff54, /*< code: 0xff54 err: AHB (Common)) error detected, cause: Invalid SPI address access either an invalid address or span of registers, recovery: Verify address and range are correct for the SPI region being accessed */ + APOLLO_CPU_SYSTEM_AHB_CPU0_INVALID_ERROR = 0xff55, /*< code: 0xff55 err: AHB (CPU0)) error detected, cause: Core0 FW accessing invalid memory address or range, recovery: If the problem persists acquire a memdump and contact ADI */ + APOLLO_CPU_SYSTEM_AHB_CPU1_INVALID_ERROR = 0xff56, /*< code: 0xff56 err: AHB (CPU1)) error detected, cause: Core1 FW accessing invalid memory address or range, recovery: If the problem persists acquire a memdump and contact ADI */ + APOLLO_CPU_SYSTEM_SECONDARY_CPU_BOOT_FAILED_ERROR = 0xff58, /*< code: 0xff58 err: Primary CPU detected secondary CPU(s) boot failure, cause: Secondary core not completing boot, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_SYSTEM_UTIL_TIMER_ERROR = 0xff59, /*< code: 0xff59 err: Utilities timer internal error, cause: RTOS taskscheduler not running for timer request, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_SYSTEM_LOGEN_INVALID_LO_CONFIG_ERROR = 0xff5a, /*< code: 0xff5a err: LOGEN Invalid LO Input/Output Configuration, cause: User selected an invalid logen config, verify Device Proifle/Configurator settings., recovery: invalid parameter passed */ + APOLLO_CPU_SYSTEM_FORCE_EXCEPTION_COMMAND_ERROR = 0xff5c, /*< code: 0xff5c err: Intentional crash, from force exception command, cause: API command sent to force an exception in the ARM, recovery: no recovery */ + APOLLO_CPU_SYSTEM_CONFIG_LOCKED_ERROR = 0xff5d, /*< code: 0xff5d err: Configuration locked, for updating, cause: The configuration is not unlocked before sending the config command., recovery: invalid parameter passed */ + APOLLO_CPU_SYSTEM_CONFIG_KEY_MISMATCH_ERROR = 0xff5e, /*< code: 0xff5e err: The given key to unlock configuration did not match with the key in current package, cause: The configuration key did not match required key to unlock., recovery: Use the correct key given by ADI and try to unlock the configuration again. */ + APOLLO_CPU_SYSTEM_CONFIG_LIMIT_REACHED_ERROR = 0xff5f, /*< code: 0xff5f err: Number of configuration update limit reached, cause: Reached the limit of the number configuration commmands allowed., recovery: Reset the device to send new set of configuration parameters. */ + APOLLO_CPU_SYSTEM_DBG_KEY_MISMATCH_ERROR = 0xff60, /*< code: 0xff60 err: The given key to enter debug mode did not match with the key to enter debug mode, cause: The debug key did not match required key to unlock., recovery: Try to send the command again with the right Debug key. Contact ADI to get the correct key if the problem persists. */ + APOLLO_CPU_SYSTEM_CTRL_CMD_LENGTH_INVALID_ERROR = 0xff61, /*< code: 0xff61 err: The Set Ctrl Cmd length is less than expected or greater than max data size allowed, cause: The control command buffer is greater than the supported size., recovery: Change the size of the control command payload or increase the control command buffer size. */ + APOLLO_CPU_SYSTEM_WATCHDOG_EXPIRED_ERROR = 0xff62, /*< code: 0xff62 err: Watchdog timer expired, system is unresponsive, cause: Not all firmware tasks completed in the expected time frame., recovery: Collect memory dump to provide debug information and reset device. - Alternate explanation - err: Not all firmware tasks completed in the expected time frame, possibly due to bad parameters, cause: Collect memory dump to provide debug information, verify that all calibrations and commands have valid parameters, and reset device., recovery: invalid parameter passed */ + APOLLO_CPU_SYSTEM_SHARED_MEM_MUTEX_TIMEOUT_ERROR = 0xff63, /*< code: 0xff63 err: Shared memory mutex timeout, cause: This could happen if the shared mutex cannot be obtained within the timeout period, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_SYSTEM_SWBKPT_INVALID_TABLE_INDEX_ERROR = 0xff64, /*< code: 0xff64 err: The given index to the SW Breakpoint Table is out of range, cause: This is a programmatic error and is not expected to happen, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_SYSTEM_SHARED_MEM_MUTEX_TAKEN_ERROR = 0xff65, /*< code: 0xff65 err: Shared memory mutex already taken, cause: This could happen if trying to take the mutex which is already taken., recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_SYSTEM_SHARED_MEM_MUTEX_RELEASE_ERROR = 0xff66, /*< code: 0xff66 err: Shared memory mutex released without owning it, cause: This could happen if trying to release the mutex which is not owned., recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_SYSTEM_UNSUPPORTED_CHANS_PER_CPU_ERROR = 0xff67, /*< code: 0xff67 err: This system is being configured to support too many channels per CPU., cause: This is a Configurator channel enable issue., recovery: Check the profile and the Configurator logic. */ + APOLLO_CPU_SYSTEM_INVALID_STATUS_SIZE_ERROR = 0xff68, /*< code: 0xff68 err: The given status size is invalid, cause: The user requested the status size larger than supported size., recovery: Change the size of the status command buffer size. */ + APOLLO_CPU_SYSTEM_STARTUP_TIMEOUT_ERROR = 0xff69, /*< code: 0xff69 err: Init and tracking start-up functions still running, cause: The ctrl task waits a predefined amount of time which is not long enough, recovery: Increase the timeout in the FW ctrl task. */ + APOLLO_CPU_SYSTEM_DBG_CMD_NOT_SUPPORTED_ERROR = 0xff6a, /*< code: 0xff6a err: The debug command is not supported after entering debug mode, cause: Wrong or not supported debug command, recovery: Try to send the command again with the right debug command. If the problem persists contact ADI. */ + APOLLO_CPU_SYSTEM_DBG_CMD_PARAMS_INVALID_ERROR = 0xff6b, /*< code: 0xff6b err: The debug command parameters is not supported after entering debug mode, cause: Wrong or not supported debug command parameters, recovery: Try to send the command again with the right debug command parameters. If the problem persists contact ADI. */ + APOLLO_CPU_SYSTEM_HAL_TX_ATTEN_RESTORE_ERROR = 0xff6c, /*< code: 0xff6c err: HAL Tx attenuation restore failed, cause: Cannot restore Tx attenuation because the settings were not saved, recovery: Unexpected error - If the problem persists acquire a memdump and contact ADI */ + APOLLO_CPU_SYSTEM_DEBUG_FUNC_NOT_SUPPORTED_ERROR = 0xff6d, /*< code: 0xff6d err: The given cal does not support the debug function, cause: The debug command that is not supported is sent to the cal., recovery: Rerun the command with the correct control command. */ + APOLLO_CPU_SYSTEM_HEALTHMON_TOO_MANY_TASKS_ERROR = 0xff6e, /*< code: 0xff6e err: The health monitor memory allocation is not large enough for the current number of tasks, cause: The number of RTOS tasks is greater than expected., recovery: no recovery */ + APOLLO_CPU_SYSTEM_SEM_CREATE_FAILED_ERROR = 0xff6f, /*< code: 0xff6f err: Failed to create system semaphore, cause: This could happen because the system applies the semphore failure., recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_SYSTEM_SEM_TAKE_FAILED_ERROR = 0xff70, /*< code: 0xff70 err: Semaphore take operation failure, cause: This could happen because the system failedin taking the semphore., recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_SYSTEM_SIMULATED_ERROR = 0xff71, /*< code: 0xff71 err: Error code used for ADI system testing, cause: This error is not possible during customer use, recovery: no recovery */ + APOLLO_CPU_SYSTEM_PRODUCT_ID_ERROR = 0xff72, /*< code: 0xff72 err: Product ID is invalid, cause: Product ID/Silicon version is unknown., recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_SYSTEM_RADIO_LOOPBACK_ERROR = 0xff73, /*< code: 0xff73 err: Radio loopback requested but being used, cause: A cal is already using a radio loopback, recovery: Verify cal logic to find multiple request */ + APOLLO_CPU_SYSTEM_TIMER_STOP_ERROR = 0xff74, /*< code: 0xff74 err: System timer stop error, cause: System timer didn't stop within timeout, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_SYSTEM_OUT_OF_RESET_ERROR = 0xff75, /*< code: 0xff75 err: Indicates system is out of reset. Used to indicate if system has reset before mailbox could respond to a command, cause: System initializes mailbox response with this error code, recovery: Restart mailbox interaction sequence as system has reset */ + APOLLO_CPU_SYSTEM_BOOT_NVM_POWERUP_ERROR = 0xff76, /*< code: 0xff76 err: NVM power up error in boot, cause: NVM power up error in boot, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_SYSTEM_BOOT_NVM_READ_SETUP_ERROR = 0xff77, /*< code: 0xff77 err: NVM read set up error in boot, cause: NVM read set up error in boot, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_SYSTEM_BOOT_PORB_RX_ERROR = 0xff78, /*< code: 0xff78 err: PORB Rx Status, cause: PORB RX not ready, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_SYSTEM_BOOT_PORB_TX_ERROR = 0xff79, /*< code: 0xff79 err: PORB Tx Status, cause: PORB TX not ready, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_SYSTEM_BOOT_PORB_SERDES_ERROR = 0xff7a, /*< code: 0xff7a err: PORB serdes Status, cause: PORB serdes not ready, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_SYSTEM_BOOT_PORB_MCS_MB_CK_ERROR = 0xff7b, /*< code: 0xff7b err: PORB mcs_mb_ck Status, cause: PORB mcs_mb_ck not ready, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_SYSTEM_BOOT_CHIP_MODE_MISMATCH_ERROR = 0xff7c, /*< code: 0xff7c err: chip mode (8T8R/4T4R) mismatch error, cause: chip mode (8T8R/4T4R) mismatch between hardware and profile, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_SYSTEM_BOOT_2ND_REG_INIT_ERROR = 0xff7d, /*< code: 0xff7d err: secondary register initialization error, cause: 2nd secondary register initialization, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_SYSTEM_BOOT_EC_TRANSFER_ERROR = 0xff7e, /*< code: 0xff7e err: boot EC transfer error, cause: boot EC transfer, recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_SYSTEM_BOOT_NVM_READ_ERROR = 0xff7f, /*< code: 0xff7f err: boot NVM read error, cause: boot EC transfer , recovery: Reset device If the problem persists contact ADI. */ + APOLLO_CPU_SYSTEM_INVALID_SW_TRIM_ERROR = 0xff80, /*< code: 0xff80 err: Invalid SW trim in profile., cause: invalid sw_trim in profile error, recovery: no recovery */ + APOLLO_CPU_SYSTEM_SW3_TRIM_MISMATCH_SW1_PART_ERROR = 0xff81, /*< code: 0xff81 err: SW3 trim in profile mismatches SW1 part., cause: sw3_trim in profile mismatches SW1 part error, recovery: no recovery */ + APOLLO_CPU_SYSTEM_SW5_TRIM_MISMATCH_SW1_PART_ERROR = 0xff82, /*< code: 0xff82 err: SW5 trim in profile mismatches SW1 part., cause: sw5_trim in profile mismatches SW1 part error, recovery: no recovery */ + APOLLO_CPU_SYSTEM_SW5_TRIM_MISMATCH_SW3_PART_ERROR = 0xff83, /*< code: 0xff83 err: SW5 trim in profile mismatches SW3 part., cause: sw5_trim in profile mismatches SW3 part error, recovery: no recovery */ + + //APOLLO_CPU_CAL_EXIT_OCCURRED_ERROR = 0xffff, /*< code: 0xffff calibration exit occurred */ + //APOLLO_CPU_FORCE_UINT32 = (int32_t)0xffffffff /*< code: (int32_t)0xffffffff used to force enumeration to be 32bits in width */ +} adi_apollo_mailbox_cpu_error_code_e; + +/** + * \see also \ref: adi_apollo_mailbox_apollo_init_calibrations_msk_e + */ +typedef enum +{ + APOLLO_INIT_CAL_IC_ADC_RX = 0x00, /*< code: 0x00 ADC Rx */ + APOLLO_INIT_CAL_IC_DAC_TX = 0x01, /*< code: 0x01 DAC Tx */ + APOLLO_INIT_CAL_IC_SERDES_RX = 0x02, /*< code: 0x02 SERDES Rx Initial Cal */ + APOLLO_INIT_CAL_IC_SERDES_TX = 0x03, /*< code: 0x03 SERDES Tx Initial Cal */ + APOLLO_INIT_CAL_IC_MCS = 0x04, /*< code: 0x04 MCS Calibration */ + APOLLO_INIT_CAL_IC_LINEARX_RX = 0x05, /*< code: 0x05 LINEARX Rx Initial Cal */ + APOLLO_INIT_CAL_IC_TEST_1 = 0x06 /*< code: 0x06 Test cal 1, Initial Cal Framework test */ +} adi_apollo_mailbox_apollo_init_calibrations_e; + +/** + * \see also \ref: adi_apollo_mailbox_apollo_rx_channel_number_msk_e + */ +typedef enum +{ + APOLLO_RX_CHANNEL_CH_A0 = 0x00, /*< code: 0x00 Channel A0 */ + APOLLO_RX_CHANNEL_CH_A1 = 0x01, /*< code: 0x01 Channel A1 */ + APOLLO_RX_CHANNEL_CH_A2 = 0x02, /*< code: 0x02 Channel A2 - 8T/8R Only */ + APOLLO_RX_CHANNEL_CH_A3 = 0x03, /*< code: 0x03 Channel A3 - 8T/8R Only */ + APOLLO_RX_CHANNEL_CH_B0 = 0x04, /*< code: 0x04 Channel B0 */ + APOLLO_RX_CHANNEL_CH_B1 = 0x05, /*< code: 0x05 Channel B1 */ + APOLLO_RX_CHANNEL_CH_B2 = 0x06, /*< code: 0x06 Channel B2 - 8T/8R Only */ + APOLLO_RX_CHANNEL_CH_B3 = 0x07 /*< code: 0x07 Channel B3 - 8T/8R Only */ +} adi_apollo_mailbox_apollo_rx_channel_numbers_e; + +/** + * \see also \ref: adi_apollo_mailbox_apollo_tx_channel_number_msk_e + */ +typedef enum +{ + APOLLO_TX_CHANNEL_CH_A0 = 0x00, /*< code: 0x00 Channel A0 */ + APOLLO_TX_CHANNEL_CH_A1 = 0x01, /*< code: 0x01 Channel A1 */ + APOLLO_TX_CHANNEL_CH_A2 = 0x02, /*< code: 0x02 Channel A2 - 8T/8R Only */ + APOLLO_TX_CHANNEL_CH_A3 = 0x03, /*< code: 0x03 Channel A3 - 8T/8R Only */ + APOLLO_TX_CHANNEL_CH_B0 = 0x04, /*< code: 0x04 Channel B0 */ + APOLLO_TX_CHANNEL_CH_B1 = 0x05, /*< code: 0x05 Channel B1 */ + APOLLO_TX_CHANNEL_CH_B2 = 0x06, /*< code: 0x06 Channel B2 - 8T/8R Only */ + APOLLO_TX_CHANNEL_CH_B3 = 0x07 /*< code: 0x07 Channel B3 - 8T/8R Only */ +} adi_apollo_mailbox_apollo_tx_channel_numbers_e; + +/** + * \see also \ref: adi_apollo_mailbox_apollo_serdes_pack_msk_e + */ +typedef enum +{ + APOLLO_SERDES_PACK_NUM_PACK_0_EAST = 0x00, /*< code: 0x00 SERDES pack 0 east */ + APOLLO_SERDES_PACK_NUM_PACK_1_WEST = 0x01 /*< code: 0x01 SERDES pack 1 west */ +} adi_apollo_mailbox_apollo_serdes_pack_e; + +/** + * \see also \ref: adi_apollo_mailbox_apollo_linearx_chan_msk_e + */ +typedef enum +{ + APOLLO_LINEARX_CHAN_NUM_CH_A0 = 0x00, /*< code: 0x00 Channel A0 */ + APOLLO_LINEARX_CHAN_NUM_CH_A1 = 0x01, /*< code: 0x01 Channel A1 */ + APOLLO_LINEARX_CHAN_NUM_CH_A2 = 0x02, /*< code: 0x02 Channel A2 - 8T/8R Only */ + APOLLO_LINEARX_CHAN_NUM_CH_A3 = 0x03, /*< code: 0x03 Channel A3 - 8T/8R Only */ + APOLLO_LINEARX_CHAN_NUM_CH_B0 = 0x04, /*< code: 0x04 Channel B0 */ + APOLLO_LINEARX_CHAN_NUM_CH_B1 = 0x05, /*< code: 0x05 Channel B1 */ + APOLLO_LINEARX_CHAN_NUM_CH_B2 = 0x06, /*< code: 0x06 Channel B2 - 8T/8R Only */ + APOLLO_LINEARX_CHAN_NUM_CH_B3 = 0x07 /*< code: 0x07 Channel B3 - 8T/8R Only */ +} adi_apollo_mailbox_apollo_linearx_chan_e; + +/** + * \see also \ref: adi_apollo_mailbox_apollo_mcs_channel_number_msk_e + */ +typedef enum +{ + APOLLO_MCS_CHANNEL_CH_A0 = 0x00, /*< code: 0x00 Channel A0 */ + APOLLO_MCS_CHANNEL_CH_A1 = 0x01, /*< code: 0x01 Channel A1 */ + APOLLO_MCS_CHANNEL_CH_A2 = 0x02, /*< code: 0x02 Channel A2 - 8T/8R Only */ + APOLLO_MCS_CHANNEL_CH_A3 = 0x03, /*< code: 0x03 Channel A3 - 8T/8R Only */ + APOLLO_MCS_CHANNEL_CH_B0 = 0x04, /*< code: 0x04 Channel B0 */ + APOLLO_MCS_CHANNEL_CH_B1 = 0x05, /*< code: 0x05 Channel B1 */ + APOLLO_MCS_CHANNEL_CH_B2 = 0x06, /*< code: 0x06 Channel B2 - 8T/8R Only */ + APOLLO_MCS_CHANNEL_CH_B3 = 0x07 /*< code: 0x07 Channel B3 - 8T/8R Only */ +} adi_apollo_mailbox_apollo_mcs_channel_numbers_e; + +typedef enum +{ + CAL_STATUS_COMMON = 0x00, /*< code: 0x00 Common calibration status */ + CAL_STATUS_SPECIFIC = 0x01, /*< code: 0x01 Calibration-specific status */ + CAL_STATUS_PRIVATE = 0x02, /*< code: 0x02 Private calibration-specific status */ + CAL_STATUS_NUM_STATUS = 0x03 /*< code: 0x03 Number of status types */ +} adi_apollo_mailbox_cal_status_type_e; + +typedef enum +{ + APOLLO_CPU_OBJID_IC_START = 0x00, /*< code: 0x00 Start of Initial Calibration OBJID */ + APOLLO_CPU_OBJID_IC_ADC_RX = 0x00, /*< code: 0x00 ADC Rx */ + APOLLO_CPU_OBJID_IC_DAC_TX = 0x01, /*< code: 0x01 DAC Tx */ + APOLLO_CPU_OBJID_IC_SERDES_RX = 0x02, /*< code: 0x02 SERDES Rx Initial Cal */ + APOLLO_CPU_OBJID_IC_SERDES_TX = 0x03, /*< code: 0x03 SERDES Tx Initial Cal */ + APOLLO_CPU_OBJID_TC_NUM_CALS = 0x03, /*< code: 0x03 number of tracking cals */ + APOLLO_CPU_OBJID_IC_MCS = 0x04, /*< code: 0x04 MCS Calibration */ + APOLLO_CPU_OBJID_IC_LINEARX_RX = 0x05, /*< code: 0x05 LINEARX Rx Initial Cal */ + APOLLO_CPU_OBJID_IC_TEST_1 = 0x06, /*< code: 0x06 Test cal 1, Initial Cal Framework test */ + APOLLO_CPU_OBJID_IC_END = 0x06, /*< code: 0x06 End of Initial Calibration OBJID */ + APOLLO_CPU_OBJID_IC_NUM_CALS = 0x07, /*< code: 0x07 number of initial cals */ + APOLLO_CPU_OBJID_TC_START = 0x30, /*< code: 0x30 Start of Tracking Calibration OBJID */ + APOLLO_CPU_OBJID_TC_SERDES_RX = 0x30, /*< code: 0x30 SERDES Rx Tracking Cal */ + APOLLO_CPU_OBJID_TC_INTERNAL_START = 0x31, /*< code: 0x31 Start of Internal Tracking Calibration OBJID */ + APOLLO_CPU_OBJID_TC_ADC_RX = 0x31, /*< code: 0x31 ADC Rx */ + APOLLO_CPU_OBJID_TC_MCS = 0x32, /*< code: 0x32 MCS Tracking Cal */ + APOLLO_CPU_OBJID_TC_END = 0x32, /*< code: 0x32 End of Tracking Calibration OBJID */ + APOLLO_CPU_OBJID_CFG_DEVICE_PROFILE = 0x80, /*< code: 0x80 Configuration profile */ + APOLLO_CPU_OBJID_CFG_RADIO_EVENT = 0x81, /*< code: 0x81 Radio events module */ + APOLLO_CPU_OBJID_CFG_INITIAL_CALS = 0x82, /*< code: 0x82 Initial Calibration framework configuration */ + APOLLO_CPU_OBJID_CFG_CAL_SCHEDULER = 0x83, /*< code: 0x83 Calibration scheduler */ + APOLLO_CPU_OBJID_CFG_HM = 0x84, /*< code: 0x84 HM Timer Control */ + APOLLO_CPU_OBJID_CFG_PARITY_ERROR_CHECK = 0x85, /*< code: 0x85 Configurable objects for memory refresh */ + APOLLO_CPU_OBJID_CFG_SYSTEM_CONFIG = 0x86, /*< code: 0x86 System configuration */ + APOLLO_CPU_OBJID_CFG_TRACKING_CALS = 0x87, /*< code: 0x87 Set tracking cal framework configuration */ + APOLLO_CPU_OBJID_CFG_TELEM = 0x8c, /*< code: 0x8c Configure the telemetry logging */ + APOLLO_CPU_OBJID_CFG_RESERVED3 = 0x8d, /*< code: 0x8d reserved */ + APOLLO_CPU_OBJID_CFG_RESERVED4 = 0x8e, /*< code: 0x8e reserved */ + APOLLO_CPU_OBJID_CFG_RESERVED5 = 0x8f, /*< code: 0x8f reserved */ + APOLLO_CPU_OBJID_DRV_NCO = 0xb0, /*< code: 0xb0 NCO */ + APOLLO_CPU_OBJID_DRV_STREAM = 0xb1, /*< code: 0xb1 Stream */ + APOLLO_CPU_OBJID_DRV_FSC = 0xb2, /*< code: 0xb2 FSC */ + APOLLO_CPU_OBJID_DRV_MASTER_BIAS = 0xb3, /*< code: 0xb3 Master Bias */ + APOLLO_CPU_OBJID_DRV_LDO = 0xb4, /*< code: 0xb4 LDO */ + APOLLO_CPU_OBJID_DRV_DWT = 0xb5, /*< code: 0xb5 DWT */ + APOLLO_CPU_OBJID_DRV_TEMP = 0xb6, /*< code: 0xb6 TEMP */ + APOLLO_CPU_OBJID_DRV_PLL = 0xb7, /*< code: 0xb7 PLL */ + APOLLO_CPU_OBJID_DRV_JESD = 0xb8, /*< code: 0xb8 JESD */ + APOLLO_CPU_OBJID_DRV_UART = 0xb9, /*< code: 0xb9 UART */ + APOLLO_CPU_OBJID_DRV_TXATTEN = 0xba, /*< code: 0xba TXATTEN */ + APOLLO_CPU_OBJID_DRV_RX_CFG = 0xbb, /*< code: 0xbb Rx Config */ + APOLLO_CPU_OBJID_DRV_GPIO = 0xbc, /*< code: 0xbc GPIO */ + APOLLO_CPU_OBJID_DRV_HSCI = 0xbd, /*< code: 0xbd HSCI */ + APOLLO_CPU_OBJID_DRV_SYSCLK = 0xbe, /*< code: 0xbe SYSCLK */ + APOLLO_CPU_OBJID_DRV_TE = 0xbf, /*< code: 0xbf Tiny Enclave */ + APOLLO_CPU_OBJID_HAL_RADIO = 0xc0, /*< code: 0xc0 HAL_RADIO */ + APOLLO_CPU_OBJID_DRV_DUMMY = 0xf0, /*< code: 0xf0 Dummy driver object */ + APOLLO_CPU_OBJID_SYSTEM_START = 0xff, /*< code: 0xff Start of System OBJID */ + APOLLO_CPU_OBJID_SYSTEM_ERROR = 0xff, /*< code: 0xff System error */ + APOLLO_CPU_OBJID_SYSTEM_END = 0xff /*< code: 0xff End of System OBJID */ +} adi_apollo_mailbox_sys_cal_object_id_e; + +/** + * \see also \ref: adi_apollo_mailbox_apollo_channel_num_msk_e + */ +typedef enum +{ + APOLLO_CHANNEL_NUM_CH_A0 = 0x00, /*< code: 0x00 Channel A0 */ + APOLLO_CHANNEL_NUM_CH_A1 = 0x01, /*< code: 0x01 Channel A1 */ + APOLLO_CHANNEL_NUM_CH_A2 = 0x02, /*< code: 0x02 Channel A2 - 8T/8R Only */ + APOLLO_CHANNEL_NUM_CH_A3 = 0x03, /*< code: 0x03 Channel A3 - 8T/8R Only */ + APOLLO_CHANNEL_NUM_CH_B0 = 0x04, /*< code: 0x04 Channel B0 */ + APOLLO_CHANNEL_NUM_CH_B1 = 0x05, /*< code: 0x05 Channel B1 */ + APOLLO_CHANNEL_NUM_CH_B2 = 0x06, /*< code: 0x06 Channel B2 - 8T/8R Only */ + APOLLO_CHANNEL_NUM_CH_B3 = 0x07 /*< code: 0x07 Channel B3 - 8T/8R Only */ +} adi_apollo_mailbox_apollo_channel_num_e; + +typedef enum +{ + SYS_STATUS_PUBLIC = 0x00, /*< code: 0x00 Public System status */ + SYS_STATUS_PRIVATE = 0x01 /*< code: 0x01 Private System status */ +} adi_apollo_mailbox_sys_status_type_e; + +/** + * \see also \ref: adi_apollo_mailbox_temp_sensor_mask_e + */ +typedef enum +{ + ADI_APOLLO_DEVTEMP_CLKPLL = 0x00, /*< code: 0x00 Clk PLL temperature sensor with ADC */ + ADI_APOLLO_DEVTEMP_SERDESPLL = 0x01, /*< code: 0x01 SERDES PLL temperature sensor with ADC */ + ADI_APOLLO_DEVTEMP_MPU_A = 0x02, /*< code: 0x02 ana_mpu_top_A temperature sensor with shared ADC */ + ADI_APOLLO_DEVTEMP_MPU_B = 0x03, /*< code: 0x03 ana_mpu_top_B temperature sensor with shared ADC */ + ADI_APOLLO_DEVTEMP_LPU_VENUS_A = 0x04, /*< code: 0x04 lpu_venusdual_r0_A temperature sensor stub without ADC */ + ADI_APOLLO_DEVTEMP_LPU_CK_CORNER_A = 0x05, /*< code: 0x05 ck_dist_corner_A temperature sensor stub without ADC */ + ADI_APOLLO_DEVTEMP_LPU_VENUS_B = 0x06, /*< code: 0x06 lpu_venusdual_r0_B temperature sensor stub without ADC */ + ADI_APOLLO_DEVTEMP_LPU_CK_CORNER_B = 0x07, /*< code: 0x07 ck_dist_corner_B temperature sensor stub without ADC */ + ADI_APOLLO_DEVTEMP_LPU_CK_CENTER = 0x08, /*< code: 0x08 ck_dist_center temperature sensor stub without ADC */ + ADI_APOLLO_DEVTEMP_MAX_SENSORS = 0x09 /*< code: 0x09 Max number of temperature sensors */ +} adi_apollo_mailbox_temp_sensor_e; + +typedef enum +{ + CTRL_CMD_GET_SW_VERSION = 0x00, /*< code: 0x00 Get software version */ + CTRL_CMD_INIT = 0x01, /*< code: 0x01 Initialization */ + CTRL_CMD_SET_FSM_CMD = 0x02, /*< code: 0x02 Set FSM command */ + CTRL_CMD_GET_FSM_STATE = 0x03, /*< code: 0x03 Get FSM state */ + CTRL_CMD_GET_DATA_SIZES = 0x04, /*< code: 0x04 Get data sizes */ + CTRL_CMD_GET_DATA_ADDRS = 0x05, /*< code: 0x05 Get data addresses */ + CTRL_CMD_RUN = 0x06, /*< code: 0x06 Run command */ + CTRL_CMD_PARAM_SET = 0x07, /*< code: 0x07 Set parameters command */ + CTRL_CMD_PARAM_GET = 0x08 /*< code: 0x08 Get parameters command */ +} adi_apollo_mailbox_ctrl_cmd_e; + +typedef enum +{ + APOLLO_HAL_CLI_LOGLVL_ERROR = 0x01, /*< code: 0x01 Error message */ + APOLLO_HAL_CLI_LOGLVL_WARNING = 0x02, /*< code: 0x02 Warning message */ + APOLLO_HAL_CLI_LOGLVL_INFO = 0x03, /*< code: 0x03 Informational message, least verbose */ + APOLLO_HAL_CLI_LOGLVL_INFO_2 = 0x04, /*< code: 0x04 Informational message, most verbose */ + APOLLO_HAL_CLI_LOGLVL_NUM_LEVELS = 0x05 /*< code: 0x05 Number of log levels */ +} adi_apollo_mailbox_hal_cli_log_level_e; + +typedef enum +{ + APOLLO_MCS_HAL_CLI_CPU_ID_NONE = 0x00, /*< code: 0x00 No CPUs */ + APOLLO_MCS_HAL_CLI_CPU_ID_0 = 0x01, /*< code: 0x01 CPU 0 (Primary CPU) */ + APOLLO_MCS_HAL_CLI_CPU_ID_1 = 0x02, /*< code: 0x02 CPU 1 */ + APOLLO_MCS_HAL_CLI_CPU_ID_ALL = 0x03 /*< code: 0x03 All CPUs */ +} adi_apollo_mailbox_hal_cli_cpu_id_e; + +typedef enum +{ + APOLLO_SERDES_LANE_NUM_1 = 0x00, /*< code: 0x00 serdes lane number 1 */ + APOLLO_SERDES_LANE_NUM_2 = 0x01, /*< code: 0x01 serdes lane number 2 */ + APOLLO_SERDES_LANE_NUM_3 = 0x02, /*< code: 0x02 serdes lane number 3 */ + APOLLO_SERDES_LANE_NUM_4 = 0x03, /*< code: 0x03 serdes lane number 4 */ + APOLLO_SERDES_LANE_NUM_5 = 0x04, /*< code: 0x04 serdes lane number 5 */ + APOLLO_SERDES_LANE_NUM_6 = 0x05, /*< code: 0x05 serdes lane number 6 */ + APOLLO_SERDES_LANE_NUM_7 = 0x06, /*< code: 0x06 serdes lane number 7 */ + APOLLO_SERDES_LANE_NUM_8 = 0x07, /*< code: 0x07 serdes lane number 8 */ + APOLLO_SERDES_LANE_NUM_9 = 0x08, /*< code: 0x08 serdes lane number 9 */ + APOLLO_SERDES_LANE_NUM_10 = 0x09, /*< code: 0x09 serdes lane number 10 */ + APOLLO_SERDES_LANE_NUM_11 = 0x0a, /*< code: 0x0a serdes lane number 11 */ + APOLLO_SERDES_LANE_NUM_12 = 0x0b, /*< code: 0x0b serdes lane number 12 */ + APOLLO_SERDES_LANE_NUM_13 = 0x0c, /*< code: 0x0c serdes lane number 13 */ + APOLLO_SERDES_LANE_NUM_14 = 0x0d, /*< code: 0x0d serdes lane number 14 */ + APOLLO_SERDES_LANE_NUM_15 = 0x0e, /*< code: 0x0e serdes lane number 15 */ + APOLLO_SERDES_LANE_NUM_16 = 0x0f, /*< code: 0x0f serdes lane number 16 */ + APOLLO_SERDES_LANE_NUM_17 = 0x10, /*< code: 0x10 serdes lane number 17 */ + APOLLO_SERDES_LANE_NUM_18 = 0x11, /*< code: 0x11 serdes lane number 18 */ + APOLLO_SERDES_LANE_NUM_19 = 0x12, /*< code: 0x12 serdes lane number 19 */ + APOLLO_SERDES_LANE_NUM_20 = 0x13, /*< code: 0x13 serdes lane number 20 */ + APOLLO_SERDES_LANE_NUM_21 = 0x14, /*< code: 0x14 serdes lane number 21 */ + APOLLO_SERDES_LANE_NUM_22 = 0x15, /*< code: 0x15 serdes lane number 22 */ + APOLLO_SERDES_LANE_NUM_23 = 0x16, /*< code: 0x16 serdes lane number 23 */ + APOLLO_SERDES_LANE_NUM_24 = 0x17 /*< code: 0x17 serdes lane number 24 */ +} adi_apollo_mailbox_serdes_lane_num_e; + +typedef enum +{ + GPIO_SIGNAL_SWBKPT_BKPT_HIT = 0x00, /*< code: 0x00 SW breakpoint was hit signal */ + GPIO_SIGNAL_SWBKPT_RESUME_FROM_BKPT = 0x01 /*< code: 0x01 Resume from SW breakpoint signal */ +} adi_apollo_mailbox_gpio_signal_e; + +typedef enum +{ + APOLLO_GPIO_PIN_00 = 0x00, /*< code: 0x00 GPIO Pin 0 */ + APOLLO_GPIO_PIN_01 = 0x01, /*< code: 0x01 GPIO Pin 1 */ + APOLLO_GPIO_PIN_02 = 0x02, /*< code: 0x02 GPIO Pin 2 */ + APOLLO_GPIO_PIN_03 = 0x03, /*< code: 0x03 GPIO Pin 3 */ + APOLLO_GPIO_PIN_04 = 0x04, /*< code: 0x04 GPIO Pin 4 */ + APOLLO_GPIO_PIN_05 = 0x05, /*< code: 0x05 GPIO Pin 5 */ + APOLLO_GPIO_PIN_06 = 0x06, /*< code: 0x06 GPIO Pin 6 */ + APOLLO_GPIO_PIN_07 = 0x07, /*< code: 0x07 GPIO Pin 7 */ + APOLLO_GPIO_PIN_08 = 0x08, /*< code: 0x08 GPIO Pin 8 */ + APOLLO_GPIO_PIN_09 = 0x09, /*< code: 0x09 GPIO Pin 9 */ + APOLLO_GPIO_PIN_10 = 0x0a, /*< code: 0x0a GPIO Pin 10 */ + APOLLO_GPIO_PIN_11 = 0x0b, /*< code: 0x0b GPIO Pin 11 */ + APOLLO_GPIO_PIN_12 = 0x0c, /*< code: 0x0c GPIO Pin 12 */ + APOLLO_GPIO_PIN_13 = 0x0d, /*< code: 0x0d GPIO Pin 13 */ + APOLLO_GPIO_PIN_14 = 0x0e, /*< code: 0x0e GPIO Pin 14 */ + APOLLO_GPIO_PIN_15 = 0x0f, /*< code: 0x0f GPIO Pin 15 */ + APOLLO_GPIO_PIN_16 = 0x10, /*< code: 0x10 GPIO Pin 16 */ + APOLLO_GPIO_PIN_17 = 0x11, /*< code: 0x11 GPIO Pin 17 */ + APOLLO_GPIO_PIN_18 = 0x12, /*< code: 0x12 GPIO Pin 18 */ + APOLLO_GPIO_PIN_19 = 0x13, /*< code: 0x13 GPIO Pin 19 */ + APOLLO_GPIO_PIN_20 = 0x14, /*< code: 0x14 GPIO Pin 20 */ + APOLLO_GPIO_PIN_21 = 0x15, /*< code: 0x15 GPIO Pin 21 */ + APOLLO_GPIO_PIN_22 = 0x16, /*< code: 0x16 GPIO Pin 22 */ + APOLLO_GPIO_PIN_23 = 0x17 /*< code: 0x17 GPIO Pin 23 */ +} adi_apollo_mailbox_gpio_pin_selection_e; + +typedef enum +{ + GPIO_PIN_POLARITY_NORMAL = 0x00, /*< code: 0x00 Normal pin polarity */ + GPIO_PIN_POLARITY_INVERTED = 0x01 /*< code: 0x01 Inverted pin polarity */ +} adi_apollo_mailbox_gpio_polarity_e; + +typedef enum +{ + GPIO_PIN_DISABLE = 0x00, /*< code: 0x00 Disable pin for a given signal */ + GPIO_PIN_ENABLE = 0x01 /*< code: 0x01 Enable pin for a given signal */ +} adi_apollo_mailbox_gpio_pin_ctrl_e; + +typedef enum +{ + APOLLO_SYSCLK_ALL_WITH_RINGOSC_SWITCH = 0x00, /*< code: 0x00 All Transmission line segments including Clock Receivers */ + APOLLO_SYSCLK_USE_DAC_SPECIAL_SENSOR = 0x01, /*< code: 0x01 DAC special sensor based fine tune */ + APOLLO_SYSCLK_START_BG_CAL = 0x02, /*< code: 0x02 Start background calibration */ + APOLLO_SYSCLK_STOP_BG_CAL = 0x03, /*< code: 0x03 Stop background calibration */ + APOLLO_SYSCLK_RESUME_BG_CAL = 0x04 /*< code: 0x04 Resume background calibration */ +} adi_apollo_mailbox_clk_path_segment_e; + +typedef enum +{ + APOLLO_PLL_CLKGEN_PLL = 0x00, /*< code: 0x00 Clock Gen PLL */ + APOLLO_PLL_SERDES_PLL = 0x01 /*< code: 0x01 Serdes PLL */ +} adi_apollo_mailbox_pll_sel_name_e; + +typedef enum +{ + CHALLENGE_TYPE_CHALLENGE_GET_VALUE = 0x00, /*< code: 0x00 Get challenge value */ + CHALLENGE_TYPE_CHALLENGE_SECURE_DEBUG_ACCESS = 0x01, /*< code: 0x01 Secure debug access */ + CHALLENGE_TYPE_ADI_ENCLAVE_CHAL_SET_CUST_RMA = 0x02, /*< code: 0x02 Set customer RMA */ + CHALLENGE_TYPE_ADI_ENCLAVE_CHAL_SET_ADI_RMA = 0x03 /*< code: 0x03 Set ADI RMA */ +} adi_apollo_mailbox_challenge_type_e; + +typedef enum +{ + APOLLO_MCS_BSYNC_ALIGN = 0x00, /*< code: 0x00 Align */ + APOLLO_MCS_BSYNC_OUTPUT_EN = 0x01, /*< code: 0x01 Output enable and loopback measurement */ + APOLLO_MCS_BSYNC_OUTPUT_DIS = 0x02, /*< code: 0x02 Output disable */ + APOLLO_MCS_BSYNC_MODE_ERROR = 0x03 /*< code: 0x03 Error mode */ +} adi_apollo_mailbox_mcs_bsync_mode_e; + +typedef enum +{ + APOLLO_ADC_PREP_FAST_MODE_SWITCH = 0x00, /*< code: 0x00 Prepare ADC slice mode fast switch */ + APOLLO_ADC_EXEC_FAST_MODE_SWITCH = 0x01, /*< code: 0x01 Execute ADC slice mode fast switch */ + APOLLO_ADC_RESUME_FAST_MODE_SWITCH = 0x02 /*< code: 0x02 Resume ADC slice mode fast switch */ +} adi_apollo_mailbox_adc_slice_mode_fast_switch_action_e; + +/** + * \see also \ref: adi_apollo_mailbox_apollo_init_calibrations_e + */ +typedef enum +{ + APOLLO_INIT_CAL_MSK_IC_ADC_RX = 0x01, /*< code: 0x01 ADC Rx */ + APOLLO_INIT_CAL_MSK_IC_DAC_TX = 0x02, /*< code: 0x02 DAC Tx */ + APOLLO_INIT_CAL_MSK_IC_SERDES_RX = 0x04, /*< code: 0x04 SERDES Rx Initial Cal */ + APOLLO_INIT_CAL_MSK_IC_SERDES_TX = 0x08, /*< code: 0x08 SERDES Tx Initial Cal */ + APOLLO_INIT_CAL_MSK_IC_MCS = 0x10, /*< code: 0x10 MCS Calibration */ + APOLLO_INIT_CAL_MSK_IC_LINEARX_RX = 0x20, /*< code: 0x20 LINEARX Rx Initial Cal */ + APOLLO_INIT_CAL_MSK_IC_TEST_1 = 0x40 /*< code: 0x40 Test cal 1, Initial Cal Framework test */ +} adi_apollo_mailbox_apollo_init_calibrations_msk_e; + +/** + * \see also \ref: adi_apollo_mailbox_apollo_rx_channel_numbers_e + */ +typedef enum +{ + APOLLO_RX_CHANNEL_MSK_CH_A0 = 0x01, /*< code: 0x01 Channel A0 */ + APOLLO_RX_CHANNEL_MSK_CH_A1 = 0x02, /*< code: 0x02 Channel A1 */ + APOLLO_RX_CHANNEL_MSK_CH_A2 = 0x04, /*< code: 0x04 Channel A2 - 8T/8R Only */ + APOLLO_RX_CHANNEL_MSK_CH_A3 = 0x08, /*< code: 0x08 Channel A3 - 8T/8R Only */ + APOLLO_RX_CHANNEL_MSK_CH_B0 = 0x10, /*< code: 0x10 Channel B0 */ + APOLLO_RX_CHANNEL_MSK_CH_B1 = 0x20, /*< code: 0x20 Channel B1 */ + APOLLO_RX_CHANNEL_MSK_CH_B2 = 0x40, /*< code: 0x40 Channel B2 - 8T/8R Only */ + APOLLO_RX_CHANNEL_MSK_CH_B3 = 0x80 /*< code: 0x80 Channel B3 - 8T/8R Only */ +} adi_apollo_mailbox_apollo_rx_channel_number_msk_e; + +/** + * \see also \ref: adi_apollo_mailbox_apollo_tx_channel_numbers_e + */ +typedef enum +{ + APOLLO_TX_CHANNEL_MSK_CH_A0 = 0x01, /*< code: 0x01 Channel A0 */ + APOLLO_TX_CHANNEL_MSK_CH_A1 = 0x02, /*< code: 0x02 Channel A1 */ + APOLLO_TX_CHANNEL_MSK_CH_A2 = 0x04, /*< code: 0x04 Channel A2 - 8T/8R Only */ + APOLLO_TX_CHANNEL_MSK_CH_A3 = 0x08, /*< code: 0x08 Channel A3 - 8T/8R Only */ + APOLLO_TX_CHANNEL_MSK_CH_B0 = 0x10, /*< code: 0x10 Channel B0 */ + APOLLO_TX_CHANNEL_MSK_CH_B1 = 0x20, /*< code: 0x20 Channel B1 */ + APOLLO_TX_CHANNEL_MSK_CH_B2 = 0x40, /*< code: 0x40 Channel B2 - 8T/8R Only */ + APOLLO_TX_CHANNEL_MSK_CH_B3 = 0x80 /*< code: 0x80 Channel B3 - 8T/8R Only */ +} adi_apollo_mailbox_apollo_tx_channel_number_msk_e; + +/** + * \see also \ref: adi_apollo_mailbox_apollo_serdes_pack_e + */ +typedef enum +{ + APOLLO_SERDES_PACK_NUM_MSK_PACK_0_EAST = 0x01, /*< code: 0x01 SERDES pack 0 east */ + APOLLO_SERDES_PACK_NUM_MSK_PACK_1_WEST = 0x02 /*< code: 0x02 SERDES pack 1 west */ +} adi_apollo_mailbox_apollo_serdes_pack_msk_e; + +/** + * \see also \ref: adi_apollo_mailbox_apollo_linearx_chan_e + */ +typedef enum +{ + APOLLO_LINEARX_CHAN_NUM_MSK_CH_A0 = 0x01, /*< code: 0x01 Channel A0 */ + APOLLO_LINEARX_CHAN_NUM_MSK_CH_A1 = 0x02, /*< code: 0x02 Channel A1 */ + APOLLO_LINEARX_CHAN_NUM_MSK_CH_A2 = 0x04, /*< code: 0x04 Channel A2 - 8T/8R Only */ + APOLLO_LINEARX_CHAN_NUM_MSK_CH_A3 = 0x08, /*< code: 0x08 Channel A3 - 8T/8R Only */ + APOLLO_LINEARX_CHAN_NUM_MSK_CH_B0 = 0x10, /*< code: 0x10 Channel B0 */ + APOLLO_LINEARX_CHAN_NUM_MSK_CH_B1 = 0x20, /*< code: 0x20 Channel B1 */ + APOLLO_LINEARX_CHAN_NUM_MSK_CH_B2 = 0x40, /*< code: 0x40 Channel B2 - 8T/8R Only */ + APOLLO_LINEARX_CHAN_NUM_MSK_CH_B3 = 0x80 /*< code: 0x80 Channel B3 - 8T/8R Only */ +} adi_apollo_mailbox_apollo_linearx_chan_msk_e; + +/** + * \see also \ref: adi_apollo_mailbox_apollo_mcs_channel_numbers_e + */ +typedef enum +{ + APOLLO_MCS_CHANNEL_MSK_CH_A0 = 0x01, /*< code: 0x01 Channel A0 */ + APOLLO_MCS_CHANNEL_MSK_CH_A1 = 0x02, /*< code: 0x02 Channel A1 */ + APOLLO_MCS_CHANNEL_MSK_CH_A2 = 0x04, /*< code: 0x04 Channel A2 - 8T/8R Only */ + APOLLO_MCS_CHANNEL_MSK_CH_A3 = 0x08, /*< code: 0x08 Channel A3 - 8T/8R Only */ + APOLLO_MCS_CHANNEL_MSK_CH_B0 = 0x10, /*< code: 0x10 Channel B0 */ + APOLLO_MCS_CHANNEL_MSK_CH_B1 = 0x20, /*< code: 0x20 Channel B1 */ + APOLLO_MCS_CHANNEL_MSK_CH_B2 = 0x40, /*< code: 0x40 Channel B2 - 8T/8R Only */ + APOLLO_MCS_CHANNEL_MSK_CH_B3 = 0x80 /*< code: 0x80 Channel B3 - 8T/8R Only */ +} adi_apollo_mailbox_apollo_mcs_channel_number_msk_e; + +/** + * Calibration state +*/ +typedef enum +{ + APOLLO_CALFRMWRK_STATE_SUSPENDED = 0x01, /*< code: 0x01 Cal's timer is not running */ + APOLLO_CALFRMWRK_STATE_RESUMED = 0x02, /*< code: 0x02 Cal's timer is running */ + APOLLO_CALFRMWRK_STATE_INACTIVE = 0x04, /*< code: 0x04 Cal's Main function is not executing */ + APOLLO_CALFRMWRK_STATE_RUNNING = 0x08, /*< code: 0x08 Cal's Main function is executing */ + APOLLO_CALFRMWRK_STATE_ENABLED = 0x10, /*< code: 0x10 Cal is enabled back from the host */ + APOLLO_CALFRMWRK_STATE_DISABLED = 0x20, /*< code: 0x20 Cal is disabled from the host */ + APOLLO_CALFRMWRK_STATE_ERROR = 0x40 /*< code: 0x40 Cal is errored out */ +} adi_apollo_mailbox_calfrmwrk_state_e; + +/** + * \see also \ref: adi_apollo_mailbox_temp_sensor_e + */ +typedef enum +{ + ADI_APOLLO_DEVTEMP_MASK_CLKPLL = 0x01, /*< code: 0x01 Clk PLL temperature sensor with ADC */ + ADI_APOLLO_DEVTEMP_MASK_SERDESPLL = 0x02, /*< code: 0x02 SERDES PLL temperature sensor with ADC */ + ADI_APOLLO_DEVTEMP_MASK_MPU_A = 0x04, /*< code: 0x04 ana_mpu_top_A temperature sensor with shared ADC */ + ADI_APOLLO_DEVTEMP_MASK_MPU_B = 0x08, /*< code: 0x08 ana_mpu_top_B temperature sensor with shared ADC */ + ADI_APOLLO_DEVTEMP_MASK_LPU_VENUS_A = 0x10, /*< code: 0x10 lpu_venusdual_r0_A temperature sensor stub without ADC */ + ADI_APOLLO_DEVTEMP_MASK_LPU_CK_CORNER_A = 0x20, /*< code: 0x20 ck_dist_corner_A temperature sensor stub without ADC */ + ADI_APOLLO_DEVTEMP_MASK_LPU_VENUS_B = 0x40, /*< code: 0x40 lpu_venusdual_r0_B temperature sensor stub without ADC */ + ADI_APOLLO_DEVTEMP_MASK_LPU_CK_CORNER_B = 0x80, /*< code: 0x80 ck_dist_corner_B temperature sensor stub without ADC */ + ADI_APOLLO_DEVTEMP_MASK_LPU_CK_CENTER = 0x100 /*< code: 0x100 ck_dist_center temperature sensor stub without ADC */ +} adi_apollo_mailbox_temp_sensor_mask_e; + +/** + * \see also \ref: adi_apollo_mailbox_apollo_channel_num_e + */ +typedef enum +{ + APOLLO_CHANNEL_NUM_MSK_CH_A0 = 0x01, /*< code: 0x01 Channel A0 */ + APOLLO_CHANNEL_NUM_MSK_CH_A1 = 0x02, /*< code: 0x02 Channel A1 */ + APOLLO_CHANNEL_NUM_MSK_CH_A2 = 0x04, /*< code: 0x04 Channel A2 - 8T/8R Only */ + APOLLO_CHANNEL_NUM_MSK_CH_A3 = 0x08, /*< code: 0x08 Channel A3 - 8T/8R Only */ + APOLLO_CHANNEL_NUM_MSK_CH_B0 = 0x10, /*< code: 0x10 Channel B0 */ + APOLLO_CHANNEL_NUM_MSK_CH_B1 = 0x20, /*< code: 0x20 Channel B1 */ + APOLLO_CHANNEL_NUM_MSK_CH_B2 = 0x40, /*< code: 0x40 Channel B2 - 8T/8R Only */ + APOLLO_CHANNEL_NUM_MSK_CH_B3 = 0x80 /*< code: 0x80 Channel B3 - 8T/8R Only */ +} adi_apollo_mailbox_apollo_channel_num_msk_e; + +/***************************************************************************** + * Sub structure forward declarations + *****************************************************************************/ +struct adi_apollo_mailbox_tracking_cal_enable_masks; +struct adi_apollo_mailbox_tracking_cal_state; +struct adi_apollo_mailbox_temp_data; +struct adi_apollo_mailbox_object_id_filter; + +/***************************************************************************** + * Sub structures + *****************************************************************************/ +/** + * \brief data structure to hold tracking calibration enable masks + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_tracking_cal_enable_masks +{ + uint32_t serdes_rx_enable_masks; /*!< which SerDes Rx tracking calibrations are enabled per pack. - see \ref adi_apollo_mailbox_apollo_serdes_pack_msk_e */ + uint32_t adc_rx_enable_masks; /*!< which ADC Rx tracking calibrations are enabled per channel. - see \ref adi_apollo_mailbox_apollo_rx_channel_number_msk_e */ + uint32_t mcs_tc_enable_mask; /*!< If the MCS tracking cal is enabled or not - see \ref adi_apollo_mailbox_apollo_mcs_channel_number_msk_e */ +} adi_apollo_mailbox_tracking_cal_enable_masks_t; +) + +/** + * \brief hold tracking calibration state information + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_tracking_cal_state +{ + uint32_t serdes_rx_cal_error[2]; /*!< SerDes Rx tracking calibration error per pack */ + uint32_t serdes_rx_cal_state[2]; /*!< SerDes Rx tracking calibration state per pack - see \ref adi_apollo_mailbox_calfrmwrk_state_e for each element */ + uint32_t adc_rx_cal_error[8]; /*!< ADC Rx tracking calibration error per channel */ + uint32_t adc_rx_cal_state[8]; /*!< ADC Rx tracking calibration state per channel - see \ref adi_apollo_mailbox_calfrmwrk_state_e for each element */ + uint32_t mcs_cal_error[1]; /*!< MCS tracking calibration error per channel */ + uint32_t mcs_cal_state[1]; /*!< MCS tracking calibration state per channel - see \ref adi_apollo_mailbox_calfrmwrk_state_e for each element */ +} adi_apollo_mailbox_tracking_cal_state_t; +) + +/** + * \brief Temperature data returned by CPU + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_temp_data +{ + int16_t temp_degrees_celsius[9]; /*!< Temperature readings from all temperature sensors */ + int16_t temp_degrees_celsius_avg; /*!< Average temperature reading of temperature sensors specified in avgMask */ + uint16_t avg_mask; /*!< Bitmask indicating which temperature sensors are averaged in tempDegreesCelciusAvg - see \ref adi_apollo_mailbox_temp_sensor_mask_e */ + int16_t max_temp_degrees_celsius; /*!< Max temperature reading of temperature sensors specified in avgMask */ + int16_t min_temp_degrees_celsius; /*!< Min temperature reading of temperature sensors specified in avgMask */ +} adi_apollo_mailbox_temp_data_t; +) + +/** + * \brief log object ID filter settings + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_object_id_filter +{ + uint32_t sys_cal_object_id; /*!< Object ID of calibration or system component - see \ref adi_apollo_mailbox_sys_cal_object_id_e */ + uint8_t object_id_filter_enable; /*!< Filter enable/disable */ +} adi_apollo_mailbox_object_id_filter_t; +) + +/***************************************************************************** + * Command structures + *****************************************************************************/ + +/** + * \brief \ref ADI_APOLLO_MAILBOX_PING Cmd structure. + * \details Ping the CPU. See also \ref adi_apollo_mailbox_resp_ping + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_cmd_ping +{ + uint32_t echo_data; /*!< Data to be echoed back by CPU */ +} adi_apollo_mailbox_cmd_ping_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_RUN_INIT Cmd structure. + * \details Run initial calibrations. See also \ref adi_apollo_mailbox_resp_run_init + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_cmd_run_init +{ + uint32_t cal_mask; /*!< Mask of adi_apollo_InitCalibrations to run on init - see \ref adi_apollo_mailbox_apollo_init_calibrations_msk_e */ + uint32_t rx_channel_mask; /*!< Mask to hold Rx channels to run on init - see \ref adi_apollo_mailbox_apollo_rx_channel_number_msk_e */ + uint32_t tx_channel_mask; /*!< Mask to hold Tx channels to run on init - see \ref adi_apollo_mailbox_apollo_tx_channel_number_msk_e */ + uint32_t serdes_rx_pack_mask; /*!< Mask to hold SerDes Rx packs to run on init - see \ref adi_apollo_mailbox_apollo_serdes_pack_msk_e */ + uint32_t serdes_tx_pack_mask; /*!< Mask to hold SerDes Tx packs to run on init - see \ref adi_apollo_mailbox_apollo_serdes_pack_msk_e */ + uint32_t linearx_chan_mask; /*!< Mask to hold linearx chan to run on init - see \ref adi_apollo_mailbox_apollo_linearx_chan_msk_e */ +} adi_apollo_mailbox_cmd_run_init_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_SET_ENABLED_TRACKING_CALS Cmd structure. + * \details Set the set of enabled tracking cals. See also \ref adi_apollo_mailbox_resp_set_enabled_tracking_cals + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_cmd_set_enabled_tracking_cals +{ + uint32_t serdes_rx_pack_mask; /*!< which Rx packs to apply the SerDes Rx calibration to - see \ref adi_apollo_mailbox_apollo_serdes_pack_msk_e */ + uint32_t adc_rx_channel_mask; /*!< which Rx channels to apply the ADC Rx calibration to - see \ref adi_apollo_mailbox_apollo_rx_channel_number_msk_e */ + uint32_t mcs_tc_mask; /*!< To enable or not the MCS tracking cal - see \ref adi_apollo_mailbox_apollo_mcs_channel_number_msk_e */ + uint8_t enable_disable; /*!< tracking cal enable/disable */ +} adi_apollo_mailbox_cmd_set_enabled_tracking_cals_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_GET_CAL_STATUS Cmd structure. + * \details Get calibration status information. See also \ref adi_apollo_mailbox_resp_get_cal_status + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_cmd_get_cal_status +{ + uint8_t cal_status_type; /*!< Calibration status type to be retrieved - see \ref adi_apollo_mailbox_cal_status_type_e */ + uint32_t sys_cal_object_id; /*!< Object ID of calibration or system component - see \ref adi_apollo_mailbox_sys_cal_object_id_e */ + uint32_t channel_num; /*!< Channel number (0 for channel 1, 1 for channel 2, etc.) - see \ref adi_apollo_mailbox_apollo_channel_num_e */ +} adi_apollo_mailbox_cmd_get_cal_status_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_GET_SYS_STATUS Cmd structure. + * \details Get system status information. See also \ref adi_apollo_mailbox_resp_get_sys_status + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_cmd_get_sys_status +{ + uint8_t sys_status_type; /*!< system status type to be retrieved - see \ref adi_apollo_mailbox_sys_status_type_e */ + uint32_t sys_cal_object_id; /*!< Object ID of calibration or system component - see \ref adi_apollo_mailbox_sys_cal_object_id_e */ + uint32_t channel_num; /*!< Channel number (0 for channel 1, 1 for channel 2, etc.) - see \ref adi_apollo_mailbox_apollo_channel_num_e */ +} adi_apollo_mailbox_cmd_get_sys_status_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_GET_DEVICE_TEMPERATURE Cmd structure. + * \details Get device temperature information. See also \ref adi_apollo_mailbox_resp_get_device_temperature + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_cmd_get_device_temperature +{ + uint16_t avg_mask; /*!< Bitmask values indicating which temperature sensor readings should be averaged - see \ref adi_apollo_mailbox_temp_sensor_mask_e */ +} adi_apollo_mailbox_cmd_get_device_temperature_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_SET_ENABLED_TEMP_SENSORS Cmd structure. + * \details Set enabled temp sensors. See also \ref adi_apollo_mailbox_resp_set_enabled_temp_sensors + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_cmd_set_enabled_temp_sensors +{ + uint16_t temp_sensor_mask; /*!< Bitmask indicating enabled temperature sensor(s) - see \ref adi_apollo_mailbox_temp_sensor_mask_e */ +} adi_apollo_mailbox_cmd_set_enabled_temp_sensors_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_UNLOCK_CONFIG Cmd structure. + * \details Unlock the configuration for changing. See also \ref adi_apollo_mailbox_resp_unlock_config + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_cmd_unlock_config +{ + uint32_t config_key; /*!< configuration key */ +} adi_apollo_mailbox_cmd_unlock_config_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_SET_CONFIG Cmd structure. + * \details Set system or calibration configuration. See also \ref adi_apollo_mailbox_resp_set_config + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_cmd_set_config +{ + uint32_t sys_cal_object_id; /*!< Object ID of calibration or system component - see \ref adi_apollo_mailbox_sys_cal_object_id_e */ + uint16_t offset; /*!< Offset into the configuration structure */ + uint8_t data_buffer[1014]; /*!< Data buffer. Length used indicated by length field */ + uint32_t length; /*!< used length of the buffer */ +} adi_apollo_mailbox_cmd_set_config_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_GET_CONFIG Cmd structure. + * \details Get system or calibration configuration. See also \ref adi_apollo_mailbox_resp_get_config + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_cmd_get_config +{ + uint32_t sys_cal_object_id; /*!< Object ID of calibration or system component - see \ref adi_apollo_mailbox_sys_cal_object_id_e */ + uint16_t offset; /*!< Offset into the configuration structure */ + uint16_t length; /*!< Length of the configuration in bytes */ +} adi_apollo_mailbox_cmd_get_config_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_SET_CTRL Cmd structure. + * \details Set system or calibration ctrl. See also \ref adi_apollo_mailbox_resp_set_ctrl + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_cmd_set_ctrl +{ + uint32_t sys_cal_object_id; /*!< Object ID of calibration or system component - see \ref adi_apollo_mailbox_sys_cal_object_id_e */ + uint32_t ctrl_cmd; /*!< Command to be executed - see \ref adi_apollo_mailbox_ctrl_cmd_e */ + uint32_t channel_num; /*!< Channel number (0 for channel 1, 1 for channel 2, etc.) - see \ref adi_apollo_mailbox_apollo_channel_num_e */ + uint8_t data_buffer[1008]; /*!< Data buffer. Length used indicated by length field */ + uint32_t length; /*!< used length of the buffer */ +} adi_apollo_mailbox_cmd_set_ctrl_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_ENTER_DEBUG_MODE Cmd structure. + * \details Enter debug mode. See also \ref adi_apollo_mailbox_resp_enter_debug_mode + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_cmd_enter_debug_mode +{ + uint32_t debug_mode_key; /*!< debug mode key */ +} adi_apollo_mailbox_cmd_enter_debug_mode_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_DEBUG Cmd structure. + * \details Generic debug command. See also \ref adi_apollo_mailbox_resp_debug + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_cmd_debug +{ + uint32_t sys_cal_object_id; /*!< Object ID of calibration or system component - see \ref adi_apollo_mailbox_sys_cal_object_id_e */ + uint32_t debug_cmd; /*!< Command to be executed */ + uint32_t channel_num; /*!< Channel number (0 for channel 1, 1 for channel 2, etc.) - see \ref adi_apollo_mailbox_apollo_channel_num_e */ + uint8_t data_buffer[1008]; /*!< Data buffer. Length used indicated by length field */ + uint32_t length; /*!< used length of the buffer */ +} adi_apollo_mailbox_cmd_debug_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_SET_LOG_FILTERS Cmd structure. + * \details Set CPU log filters. See also \ref adi_apollo_mailbox_resp_set_log_filters + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_cmd_set_log_filters +{ + uint8_t log_event_filter; /*!< CPU log events - see \ref adi_apollo_mailbox_hal_cli_log_level_e */ + uint8_t cpu_id_filter; /*!< CPU log CPU ID - see \ref adi_apollo_mailbox_hal_cli_cpu_id_e */ + adi_apollo_mailbox_object_id_filter_t object_id_filter; /*!< log object ID filter settings */ +} adi_apollo_mailbox_cmd_set_log_filters_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_RESUME_BKPT Cmd structure. + * \details Resume task(s) suspended due to breakpoint. See also \ref adi_apollo_mailbox_resp_resume_bkpt + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_cmd_resume_bkpt +{ + uint32_t sys_cal_object_id; /*!< Object ID of calibration or system component - see \ref adi_apollo_mailbox_sys_cal_object_id_e */ + uint32_t channel_num_mask; /*!< Channel number mask - see \ref adi_apollo_mailbox_apollo_channel_num_msk_e */ + uint8_t resume_all; /*!< resume all */ +} adi_apollo_mailbox_cmd_resume_bkpt_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_RUN_SERDES_EYE_SWEEP Cmd structure. + * \details Run SERDES eye sweep. See also \ref adi_apollo_mailbox_resp_run_serdes_eye_sweep + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_cmd_run_serdes_eye_sweep +{ + uint8_t lane; /*!< Serializer lane number - see \ref adi_apollo_mailbox_serdes_lane_num_e */ + uint8_t prbs_pattern; /*!< PRBS pattern */ + uint8_t force_using_outer; /*!< Flag indicating 'outer' should be used for phase detection 0 (default) - do not use outer for phase detection, 1 - use outer for phase detection */ + uint32_t prbs_check_duration_ms; /*!< Duration of PRBS check in [ms] */ +} adi_apollo_mailbox_cmd_run_serdes_eye_sweep_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_RUN_SERDES_VERT_EYE_SWEEP Cmd structure. + * \details Run SERDES vertical eye sweep. See also \ref adi_apollo_mailbox_resp_run_serdes_vert_eye_sweep + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_cmd_run_serdes_vert_eye_sweep +{ + uint8_t lane; /*!< Serializer lane number - see \ref adi_apollo_mailbox_serdes_lane_num_e */ +} adi_apollo_mailbox_cmd_run_serdes_vert_eye_sweep_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_SET_GPIO Cmd structure. + * \details Set GPIO pin configuration. See also \ref adi_apollo_mailbox_resp_set_gpio + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_cmd_set_gpio +{ + uint8_t signal; /*!< ARM controlled GPIO signal enumeration - see \ref adi_apollo_mailbox_gpio_signal_e */ + uint8_t pin; /*!< GPIO pin - see \ref adi_apollo_mailbox_gpio_pin_selection_e */ + uint8_t polarity; /*!< ARM controlled GPIO pin polarity enumeration - see \ref adi_apollo_mailbox_gpio_polarity_e */ + uint8_t enable; /*!< enable 0 - disable, 1 - enable - see \ref adi_apollo_mailbox_gpio_pin_ctrl_e */ +} adi_apollo_mailbox_cmd_set_gpio_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_GET_GPIO Cmd structure. + * \details Get GPIO pin configuration. See also \ref adi_apollo_mailbox_resp_get_gpio + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_cmd_get_gpio +{ + uint8_t signal; /*!< ARM controlled GPIO signal enumeration - see \ref adi_apollo_mailbox_gpio_signal_e */ +} adi_apollo_mailbox_cmd_get_gpio_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_SYSCLK_CONDITIONING Cmd structure. + * \details sysclk conditioning. See also \ref adi_apollo_mailbox_resp_sysclk_conditioning + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_cmd_sysclk_conditioning +{ + uint8_t clk_path_segment; /*!< clock path segment enumeration - see \ref adi_apollo_mailbox_clk_path_segment_e */ +} adi_apollo_mailbox_cmd_sysclk_conditioning_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_MASTER_BIAS_SET_DAC_BIAS_MODE Cmd structure. + * \details Set DAC Bias. See also \ref adi_apollo_mailbox_resp_master_bias_set_dac_bias_mode + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_cmd_master_bias_set_dac_bias_mode +{ + uint8_t bias_mode; /*!< DAC Bias enumeration */ +} adi_apollo_mailbox_cmd_master_bias_set_dac_bias_mode_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_PGM_PLL Cmd structure. + * \details program pll. See also \ref adi_apollo_mailbox_resp_pgm_pll + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_cmd_pgm_pll +{ + uint8_t pll; /*!< PLL Type Enumeration - see \ref adi_apollo_mailbox_pll_sel_name_e */ + uint32_t loop_bandwidth_hz; /*!< PLL Loop bandwidth. (valid range: 1kHz - 10 MHz) */ + uint8_t phase_margin_degrees; /*!< PLL Phase Margin in degrees. (valid range 0 - 80) */ + uint8_t div_range_mode; /*!< when high, enables vco divby1 from root divider */ + uint8_t div2_mode; /*!< when high, enables vco divby2 from root divider - div_range_mode must be zero */ + uint8_t power; /*!< PLL Power setting */ + uint8_t ref_clk_div; /*!< PLL ref clock divider. (valid range: 0 - 31) */ + uint8_t i_bleed_en; /*!< PLL bleed ramp enable */ + uint8_t serdes_pll_odiv; /*!< Divider value (Yoda reg. name: register serdes_output_divider_ctl) */ + uint32_t feedback_int; /*!< Integer portion of feedback factor */ + uint32_t feedback_frac; /*!< Fractional portion of feedback factor */ +} adi_apollo_mailbox_cmd_pgm_pll_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_REQUEST_CHALLENGE Cmd structure. + * \details Request challenge. See also \ref adi_apollo_mailbox_resp_request_challenge + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_cmd_request_challenge +{ + uint8_t challenge_type; /*!< Challenge_type to be requested - see \ref adi_apollo_mailbox_challenge_type_e */ +} adi_apollo_mailbox_cmd_request_challenge_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_SET_CHALLENGE Cmd structure. + * \details Set challenge. See also \ref adi_apollo_mailbox_resp_set_challenge + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_cmd_set_challenge +{ + uint32_t challenge_type; /*!< Challenge_type to be set - see \ref adi_apollo_mailbox_challenge_type_e */ + uint8_t data_buffer[1016]; /*!< Data buffer. Length used indicated by length field */ + uint32_t length; /*!< used length of the buffer */ +} adi_apollo_mailbox_cmd_set_challenge_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_MCS_BSYNC_SET_CONFIG Cmd structure. + * \details Set configuration by user. See also \ref adi_apollo_mailbox_resp_mcs_bsync_set_config + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_cmd_mcs_bsync_set_config +{ + uint8_t func_mode; /*!< Function mode for controlling BSYNC operations - see \ref adi_apollo_mailbox_mcs_bsync_mode_e */ + uint32_t bsync_div; /*!< BSYNC division ratio relative to Apollo device clock */ +} adi_apollo_mailbox_cmd_mcs_bsync_set_config_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_SET_ADC_SLICE_MODE_FAST_SWITCH_ACTION Cmd structure. + * \details Set the action of ADC slice mode fast switch. See also \ref adi_apollo_mailbox_resp_set_adc_slice_mode_fast_switch_action + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_cmd_set_adc_slice_mode_fast_switch_action +{ + uint32_t adc_rx_channel_mask; /*!< which Rx channels to set the action of the ADC Rx fast mode switch to - see \ref adi_apollo_mailbox_apollo_rx_channel_number_msk_e */ + uint8_t adc_slice_mode_fast_switch_action; /*!< ADC slice mode fast switch action - see \ref adi_apollo_mailbox_adc_slice_mode_fast_switch_action_e */ +} adi_apollo_mailbox_cmd_set_adc_slice_mode_fast_switch_action_t; +) + +/***************************************************************************** + * Response structures + *****************************************************************************/ + +/** + * \brief \ref ADI_APOLLO_MAILBOX_PING Resp structure. + * \details Ping the CPU. See also \ref adi_apollo_mailbox_cmd_ping + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_resp_ping +{ + uint32_t status; /*!< cpu error response code - see \ref adi_apollo_mailbox_cpu_error_code_e */ + uint32_t echo_data; /*!< Data to be echoed back by CPU */ +} adi_apollo_mailbox_resp_ping_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_RUN_INIT Resp structure. + * \details Run initial calibrations. See also \ref adi_apollo_mailbox_cmd_run_init + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_resp_run_init +{ + uint32_t status; /*!< cpu error response code - see \ref adi_apollo_mailbox_cpu_error_code_e */ +} adi_apollo_mailbox_resp_run_init_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_RUN_INIT_GET_COMPLETION Resp structure. + * \details Get the completion status of initial calibrations + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_resp_run_init_get_completion +{ + uint32_t status; /*!< cpu error response code - see \ref adi_apollo_mailbox_cpu_error_code_e */ + uint8_t in_progress; /*!< Init cal progress flag. Will be set to 1 if an initial calibration run is currently in progress. Set to 0 otherwise. */ + uint8_t success; /*!< Init cal success/failure status. Set to 1 if all cals completed successfully. Set to 0 otherwise. Only valid when inProgress equals 0. Issue APOLLO_CPU_CMD_ID_RUN_INIT_GET_DETAILED_STATUS for detailed error info. */ +} adi_apollo_mailbox_resp_run_init_get_completion_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_RUN_INIT_GET_DETAILED_STATUS Resp structure. + * \details Get detailed status information on initial calibrations + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_resp_run_init_get_detailed_status +{ + uint32_t status; /*!< cpu error response code - see \ref adi_apollo_mailbox_cpu_error_code_e */ + uint32_t init_err_codes[8]; /*!< Set of initial calibration error codes for each channel */ + uint32_t init_err_cals[8]; /*!< Bitmask indicating calibrations reporting an error for each channel - see \ref adi_apollo_mailbox_apollo_init_calibrations_msk_e for each element */ + uint32_t cals_duration_msec; /*!< Duration in msec of the last initial calibration run */ + uint32_t cals_since_power_up[8]; /*!< Bitmask indicating calibrations run since power up for each channel - see \ref adi_apollo_mailbox_apollo_init_calibrations_msk_e for each element */ + uint32_t cals_last_run[8]; /*!< Bitmask indicating calibrations run in during the previous runInitCals() call for each channel - see \ref adi_apollo_mailbox_apollo_init_calibrations_msk_e for each element */ +} adi_apollo_mailbox_resp_run_init_get_detailed_status_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_RUN_INIT_ABORT Resp structure. + * \details Abort any in progress initial calibrations + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_resp_run_init_abort +{ + uint32_t status; /*!< cpu error response code - see \ref adi_apollo_mailbox_cpu_error_code_e */ +} adi_apollo_mailbox_resp_run_init_abort_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_SET_ENABLED_TRACKING_CALS Resp structure. + * \details Set the set of enabled tracking cals. See also \ref adi_apollo_mailbox_cmd_set_enabled_tracking_cals + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_resp_set_enabled_tracking_cals +{ + uint32_t status; /*!< cpu error response code - see \ref adi_apollo_mailbox_cpu_error_code_e */ +} adi_apollo_mailbox_resp_set_enabled_tracking_cals_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_GET_ENABLED_TRACKING_CALS Resp structure. + * \details Get the set of enabled tracking cals + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_resp_get_enabled_tracking_cals +{ + uint32_t status; /*!< cpu error response code - see \ref adi_apollo_mailbox_cpu_error_code_e */ + adi_apollo_mailbox_tracking_cal_enable_masks_t tracking_cal_enable_masks; /*!< data structure to hold tracking calibration enable masks */ +} adi_apollo_mailbox_resp_get_enabled_tracking_cals_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_GET_TRACKING_CAL_STATE Resp structure. + * \details Get detailed state information for all tracking cals + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_resp_get_tracking_cal_state +{ + uint32_t status; /*!< cpu error response code - see \ref adi_apollo_mailbox_cpu_error_code_e */ + adi_apollo_mailbox_tracking_cal_state_t tracking_cal_state; /*!< hold tracking calibration state information */ +} adi_apollo_mailbox_resp_get_tracking_cal_state_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_GET_CAL_STATUS Resp structure. + * \details Get calibration status information. See also \ref adi_apollo_mailbox_cmd_get_cal_status + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_resp_get_cal_status +{ + uint32_t status; /*!< cpu error response code - see \ref adi_apollo_mailbox_cpu_error_code_e */ + uint8_t data_buffer[1016]; /*!< Data buffer. Length used indicated by length field */ + uint32_t length; /*!< used length of the buffer */ +} adi_apollo_mailbox_resp_get_cal_status_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_GET_SYS_STATUS Resp structure. + * \details Get system status information. See also \ref adi_apollo_mailbox_cmd_get_sys_status + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_resp_get_sys_status +{ + uint32_t status; /*!< cpu error response code - see \ref adi_apollo_mailbox_cpu_error_code_e */ + uint8_t data_buffer[1016]; /*!< Data buffer. Length used indicated by length field */ + uint32_t length; /*!< used length of the buffer */ +} adi_apollo_mailbox_resp_get_sys_status_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_GET_DEVICE_TEMPERATURE Resp structure. + * \details Get device temperature information. See also \ref adi_apollo_mailbox_cmd_get_device_temperature + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_resp_get_device_temperature +{ + uint32_t status; /*!< cpu error response code - see \ref adi_apollo_mailbox_cpu_error_code_e */ + adi_apollo_mailbox_temp_data_t temp_data; /*!< Temperature data returned by CPU */ +} adi_apollo_mailbox_resp_get_device_temperature_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_GET_ENABLED_TEMP_SENSORS Resp structure. + * \details Get enabled temp sensors + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_resp_get_enabled_temp_sensors +{ + uint32_t status; /*!< cpu error response code - see \ref adi_apollo_mailbox_cpu_error_code_e */ + uint16_t temp_sensor_mask; /*!< Bitmask indicating enabled temperature sensor(s) - see \ref adi_apollo_mailbox_temp_sensor_mask_e */ +} adi_apollo_mailbox_resp_get_enabled_temp_sensors_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_SET_ENABLED_TEMP_SENSORS Resp structure. + * \details Set enabled temp sensors. See also \ref adi_apollo_mailbox_cmd_set_enabled_temp_sensors + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_resp_set_enabled_temp_sensors +{ + uint32_t status; /*!< cpu error response code - see \ref adi_apollo_mailbox_cpu_error_code_e */ + uint16_t temp_sensor_mask; /*!< Bitmask indicating enabled temperature sensor(s) - see \ref adi_apollo_mailbox_temp_sensor_mask_e */ +} adi_apollo_mailbox_resp_set_enabled_temp_sensors_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_UNLOCK_CONFIG Resp structure. + * \details Unlock the configuration for changing. See also \ref adi_apollo_mailbox_cmd_unlock_config + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_resp_unlock_config +{ + uint32_t status; /*!< cpu error response code - see \ref adi_apollo_mailbox_cpu_error_code_e */ +} adi_apollo_mailbox_resp_unlock_config_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_SET_CONFIG Resp structure. + * \details Set system or calibration configuration. See also \ref adi_apollo_mailbox_cmd_set_config + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_resp_set_config +{ + uint32_t status; /*!< cpu error response code - see \ref adi_apollo_mailbox_cpu_error_code_e */ +} adi_apollo_mailbox_resp_set_config_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_GET_CONFIG Resp structure. + * \details Get system or calibration configuration. See also \ref adi_apollo_mailbox_cmd_get_config + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_resp_get_config +{ + uint32_t status; /*!< cpu error response code - see \ref adi_apollo_mailbox_cpu_error_code_e */ + uint8_t data_buffer[1016]; /*!< Data buffer. Length used indicated by length field */ + uint32_t length; /*!< used length of the buffer */ +} adi_apollo_mailbox_resp_get_config_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_SET_CTRL Resp structure. + * \details Set system or calibration ctrl. See also \ref adi_apollo_mailbox_cmd_set_ctrl + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_resp_set_ctrl +{ + uint32_t status; /*!< cpu error response code - see \ref adi_apollo_mailbox_cpu_error_code_e */ + uint8_t data_buffer[1016]; /*!< Data buffer. Length used indicated by length field */ + uint32_t length; /*!< used length of the buffer */ +} adi_apollo_mailbox_resp_set_ctrl_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_ENTER_DEBUG_MODE Resp structure. + * \details Enter debug mode. See also \ref adi_apollo_mailbox_cmd_enter_debug_mode + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_resp_enter_debug_mode +{ + uint32_t status; /*!< cpu error response code - see \ref adi_apollo_mailbox_cpu_error_code_e */ +} adi_apollo_mailbox_resp_enter_debug_mode_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_DEBUG Resp structure. + * \details Generic debug command. See also \ref adi_apollo_mailbox_cmd_debug + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_resp_debug +{ + uint32_t status; /*!< cpu error response code - see \ref adi_apollo_mailbox_cpu_error_code_e */ +} adi_apollo_mailbox_resp_debug_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_SET_LOG_FILTERS Resp structure. + * \details Set CPU log filters. See also \ref adi_apollo_mailbox_cmd_set_log_filters + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_resp_set_log_filters +{ + uint32_t status; /*!< cpu error response code - see \ref adi_apollo_mailbox_cpu_error_code_e */ +} adi_apollo_mailbox_resp_set_log_filters_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_RESUME_BKPT Resp structure. + * \details Resume task(s) suspended due to breakpoint. See also \ref adi_apollo_mailbox_cmd_resume_bkpt + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_resp_resume_bkpt +{ + uint32_t status; /*!< cpu error response code - see \ref adi_apollo_mailbox_cpu_error_code_e */ +} adi_apollo_mailbox_resp_resume_bkpt_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_RUN_SERDES_EYE_SWEEP Resp structure. + * \details Run SERDES eye sweep. See also \ref adi_apollo_mailbox_cmd_run_serdes_eye_sweep + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_resp_run_serdes_eye_sweep +{ + uint32_t status; /*!< cpu error response code - see \ref adi_apollo_mailbox_cpu_error_code_e */ +} adi_apollo_mailbox_resp_run_serdes_eye_sweep_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_RUN_SERDES_VERT_EYE_SWEEP Resp structure. + * \details Run SERDES vertical eye sweep. See also \ref adi_apollo_mailbox_cmd_run_serdes_vert_eye_sweep + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_resp_run_serdes_vert_eye_sweep +{ + uint32_t status; /*!< cpu error response code - see \ref adi_apollo_mailbox_cpu_error_code_e */ +} adi_apollo_mailbox_resp_run_serdes_vert_eye_sweep_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_SET_GPIO Resp structure. + * \details Set GPIO pin configuration. See also \ref adi_apollo_mailbox_cmd_set_gpio + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_resp_set_gpio +{ + uint32_t status; /*!< cpu error response code - see \ref adi_apollo_mailbox_cpu_error_code_e */ +} adi_apollo_mailbox_resp_set_gpio_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_GET_GPIO Resp structure. + * \details Get GPIO pin configuration. See also \ref adi_apollo_mailbox_cmd_get_gpio + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_resp_get_gpio +{ + uint32_t status; /*!< cpu error response code - see \ref adi_apollo_mailbox_cpu_error_code_e */ + uint8_t pin; /*!< GPIO pin - see \ref adi_apollo_mailbox_gpio_pin_selection_e */ + uint8_t polarity; /*!< ARM controlled GPIO pin polarity enumeration - see \ref adi_apollo_mailbox_gpio_polarity_e */ +} adi_apollo_mailbox_resp_get_gpio_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_MBIAS_PRE_CLOCK_INIT Resp structure. + * \details MBIAS pre clock init + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_resp_mbias_pre_clock_init +{ + uint32_t status; /*!< cpu error response code - see \ref adi_apollo_mailbox_cpu_error_code_e */ +} adi_apollo_mailbox_resp_mbias_pre_clock_init_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_MBIAS_POST_CLOCK_INIT Resp structure. + * \details MBIAS post clock init + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_resp_mbias_post_clock_init +{ + uint32_t status; /*!< cpu error response code - see \ref adi_apollo_mailbox_cpu_error_code_e */ +} adi_apollo_mailbox_resp_mbias_post_clock_init_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_SYSCLK_CONFIGURATION Resp structure. + * \details sysclk configuration + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_resp_sysclk_configuration +{ + uint32_t status; /*!< cpu error response code - see \ref adi_apollo_mailbox_cpu_error_code_e */ +} adi_apollo_mailbox_resp_sysclk_configuration_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_SYSCLK_CONDITIONING Resp structure. + * \details sysclk conditioning. See also \ref adi_apollo_mailbox_cmd_sysclk_conditioning + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_resp_sysclk_conditioning +{ + uint32_t status; /*!< cpu error response code - see \ref adi_apollo_mailbox_cpu_error_code_e */ +} adi_apollo_mailbox_resp_sysclk_conditioning_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_SYSCLK_SWITCH_TO_HSDIG Resp structure. + * \details sysclk switch from ring oscillator + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_resp_sysclk_switch_to_hsdig +{ + uint32_t status; /*!< cpu error response code - see \ref adi_apollo_mailbox_cpu_error_code_e */ +} adi_apollo_mailbox_resp_sysclk_switch_to_hsdig_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_MASTER_BIAS_SET_DAC_BIAS_MODE Resp structure. + * \details Set DAC Bias. See also \ref adi_apollo_mailbox_cmd_master_bias_set_dac_bias_mode + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_resp_master_bias_set_dac_bias_mode +{ + uint32_t status; /*!< cpu error response code - see \ref adi_apollo_mailbox_cpu_error_code_e */ +} adi_apollo_mailbox_resp_master_bias_set_dac_bias_mode_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_SYSCLK_SWITCH_TO_RINGOSC Resp structure. + * \details sysclk switch to ring oscillator + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_resp_sysclk_switch_to_ringosc +{ + uint32_t status; /*!< cpu error response code - see \ref adi_apollo_mailbox_cpu_error_code_e */ +} adi_apollo_mailbox_resp_sysclk_switch_to_ringosc_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_PGM_PLL Resp structure. + * \details program pll. See also \ref adi_apollo_mailbox_cmd_pgm_pll + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_resp_pgm_pll +{ + uint32_t status; /*!< cpu error response code - see \ref adi_apollo_mailbox_cpu_error_code_e */ +} adi_apollo_mailbox_resp_pgm_pll_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_UPDATE_CAL_DATA_CRC Resp structure. + * \details Update CRC for all calibration data + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_resp_update_cal_data_crc +{ + uint32_t status; /*!< cpu error response code - see \ref adi_apollo_mailbox_cpu_error_code_e */ +} adi_apollo_mailbox_resp_update_cal_data_crc_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_GET_FW_VERSION Resp structure. + * \details Gets the firmware version information + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_resp_get_fw_version +{ + uint32_t status; /*!< cpu error response code - see \ref adi_apollo_mailbox_cpu_error_code_e */ + uint16_t major; /*!< Software major version */ + uint16_t minor; /*!< Software minor version */ + uint16_t patch; /*!< Software patch version */ + uint8_t quality_level[3]; /*!< Software quality level string */ + uint16_t state_version; /*!< Internal release version at give quality level */ + uint16_t build_year; /*!< The year the firmware was built */ + uint8_t build_month; /*!< The month the firmware was built */ + uint8_t build_day; /*!< The day the firmware was built */ + uint8_t build_hour; /*!< The hour the firware was built (UTC) */ + uint8_t build_min; /*!< The minute the firware was built (UTC) */ +} adi_apollo_mailbox_resp_get_fw_version_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_REQUEST_CHALLENGE Resp structure. + * \details Request challenge. See also \ref adi_apollo_mailbox_cmd_request_challenge + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_resp_request_challenge +{ + uint32_t status; /*!< cpu error response code - see \ref adi_apollo_mailbox_cpu_error_code_e */ + uint8_t data_buffer[1016]; /*!< Data buffer. Length used indicated by length field */ + uint32_t length; /*!< used length of the buffer */ +} adi_apollo_mailbox_resp_request_challenge_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_SET_CHALLENGE Resp structure. + * \details Set challenge. See also \ref adi_apollo_mailbox_cmd_set_challenge + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_resp_set_challenge +{ + uint32_t status; /*!< cpu error response code - see \ref adi_apollo_mailbox_cpu_error_code_e */ +} adi_apollo_mailbox_resp_set_challenge_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_POWER_UP_JTX Resp structure. + * \details Power up JTx + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_resp_power_up_jtx +{ + uint32_t status; /*!< cpu error response code - see \ref adi_apollo_mailbox_cpu_error_code_e */ +} adi_apollo_mailbox_resp_power_up_jtx_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_MCS_BSYNC_SET_CONFIG Resp structure. + * \details Set configuration by user. See also \ref adi_apollo_mailbox_cmd_mcs_bsync_set_config + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_resp_mcs_bsync_set_config +{ + uint32_t status; /*!< cpu error response code - see \ref adi_apollo_mailbox_cpu_error_code_e */ +} adi_apollo_mailbox_resp_mcs_bsync_set_config_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_MCS_BSYNC_GET_CONFIG Resp structure. + * \details Get configuration by user + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_resp_mcs_bsync_get_config +{ + uint32_t status; /*!< cpu error response code - see \ref adi_apollo_mailbox_cpu_error_code_e */ + uint8_t func_mode; /*!< Function mode for controlling BSYNC operations - see \ref adi_apollo_mailbox_mcs_bsync_mode_e */ + uint32_t bsync_div; /*!< BSYNC division ratio relative to Apollo device clock */ + uint8_t done_flag; /*!< */ + int64_t delta_t0; /*!< Time difference after alignment in femtoseconds for the CENTER sysref */ + int64_t delta_t1; /*!< Measure delay needed to be compensated by delay line in femtoseconds for the CENTER sysref */ + int64_t delta_t0_a; /*!< Time difference after alignment in femtoseconds for the side A sysref */ + int64_t delta_t1_a; /*!< Measure delay needed to be compensated by delay line in femtoseconds for the side A sysref */ + int64_t delta_t0_b; /*!< Time difference after alignment in femtoseconds for the side B sysref */ + int64_t delta_t1_b; /*!< Measure delay needed to be compensated by delay line in femtoseconds for the side B sysref */ +} adi_apollo_mailbox_resp_mcs_bsync_get_config_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_MCS_BSYNC_GO Resp structure. + * \details Start the BSYNC synchornization process + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_resp_mcs_bsync_go +{ + uint32_t status; /*!< cpu error response code - see \ref adi_apollo_mailbox_cpu_error_code_e */ +} adi_apollo_mailbox_resp_mcs_bsync_go_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_GET_ADC_SLICE_MODES Resp structure. + * \details Gets the ADC slice modes + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_resp_get_adc_slice_modes +{ + uint32_t status; /*!< cpu error response code - see \ref adi_apollo_mailbox_cpu_error_code_e */ + uint8_t adc_slice_mode[8]; /*!< ADC slice modes ([0]:A0,[1]:A1,[2]:A2,[3]:A3,[4]:B0,[5]:B1,[6]:B2,[7]:B3). 0: Random, 1: Sequential, 255: Channel disabled */ +} adi_apollo_mailbox_resp_get_adc_slice_modes_t; +) + +/** + * \brief \ref ADI_APOLLO_MAILBOX_SET_ADC_SLICE_MODE_FAST_SWITCH_ACTION Resp structure. + * \details Set the action of ADC slice mode fast switch. See also \ref adi_apollo_mailbox_cmd_set_adc_slice_mode_fast_switch_action + */ +ADI_APOLLO_PACKED( +typedef struct adi_apollo_mailbox_resp_set_adc_slice_mode_fast_switch_action +{ + uint32_t status; /*!< cpu error response code - see \ref adi_apollo_mailbox_cpu_error_code_e */ +} adi_apollo_mailbox_resp_set_adc_slice_mode_fast_switch_action_t; +) + +#endif /* __ADI_APOLLO_MAILBOX_TYPES_H__ */ +/*! @} */ \ No newline at end of file diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_mcs_cal.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_mcs_cal.h new file mode 100644 index 00000000000000..9151db807f3fcb --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_mcs_cal.h @@ -0,0 +1,216 @@ +/*! + * \brief Multi Chip Sync Calibration API definition header + * + * \copyright copyright(c) 2024 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_MCS_CAL + * @{ + */ +#ifndef __ADI_APOLLO_MCS_CAL_H__ +#define __ADI_APOLLO_MCS_CAL_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_mcs_cal_types.h" + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" +{ +#endif + +/** + * \brief Load configuration data required for MCS Calibration. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure. + * \param[in] cal_config Pointer to MCS Cal Configuration Struct. \ref adi_apollo_mcs_cal_config_t. + * + * \return API_CMS_ERROR_OK API Completed Successfully. + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_mcs_cal_config_set(adi_apollo_device_t *device, adi_apollo_mcs_cal_config_t *cal_config); + +/** + * \brief Execute an Initial MCS Calibration. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure. + * + * \return API_CMS_ERROR_OK API Completed Successfully. + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_mcs_cal_init_run(adi_apollo_device_t *device); + +/** + * \brief Get status of a MCS Initial Calibration run. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure. + * \param[out] cal_status Pointer to struct containing MCS init cal error and state info. \ref adi_apollo_mcs_cal_init_status_t. + * + * \return API_CMS_ERROR_OK API Completed Successfully. + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_mcs_cal_init_status_get(adi_apollo_device_t *device, adi_apollo_mcs_cal_init_status_t *cal_status); + +/** + * \brief Set select parameters related to MCS Calibration. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure. + * \param[in] mcs_parameter Select MCS configuration parameter. \ref adi_apollo_mcs_parameter_e. + * \param[in] data MCS Configuration Data corresponding to selected parameter. + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_mcs_cal_parameter_set(adi_apollo_device_t *device, adi_apollo_mcs_parameter_e mcs_parameter, uint64_t data); + +/** + * \brief Set decimation for MCS Tracking Calibration to do TDC measurement. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure. + * \param[in] decimation TDC decimation value. + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_mcs_cal_tracking_decimation_set(adi_apollo_device_t *device, uint16_t decimation); + +/** + * \brief Enable/Disable MCS Tracking Calibration. + * \note Tracking decimation needs to be set before calling this API. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure. + * \param[in] enable Enable(1) / Disable(0) MCS Tracking Calibration. + * + * \return API_CMS_ERROR_OK API Completed Successfully. + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_mcs_cal_tracking_enable(adi_apollo_device_t *device, uint8_t enable); + +/** + * \brief Initialize MCS Tracking Calibration. This initializes mcs tracking fw with user-defined values in \ref adi_apollo_drv_adf4382_config_t. + * \note User needs to call this API if 'track_initialize' was not already set in \ref adi_apollo_drv_adf4382_config_t. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure. + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_mcs_cal_tracking_initialize_set(adi_apollo_device_t *device); + +/** + * \brief Execute MCS Foreground Tracking Calibration for fast SysRef alignment. + * \note MCS Foreground Tracking routine can send multiple phase adjust GPIO strobes, if needed, to ADF4382. + * This allows for faster SysRef clock calibration. It is recommended to run this AFTER \ref adi_apollo_mcs_cal_init_run(). + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure. + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_mcs_cal_fg_tracking_run(adi_apollo_device_t *device); + +/** + * \brief Execute MCS Background Tracking Calibration for maintaining SysRef alignment. + * \note MCS Background Tracking routine runs periodically, in background, + * measuring SysRef time difference using Apollo TDC and if required sends phase correction strobe to ADF4382. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure. + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_mcs_cal_bg_tracking_run(adi_apollo_device_t *device); + +/** + * \brief Halts(freezes) MCS Background Tracking Calibration. TDC measurement and phase correction routine will be halted. + * \note To be used before getting tracking cal status or if phase correction is not needed. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure. + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_mcs_cal_bg_tracking_freeze(adi_apollo_device_t *device); + +/** + * \brief Restarts(unfreezes) MCS Background Tracking Calibration. TDC measurement and phase correction routine will start again. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure. + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_mcs_cal_bg_tracking_unfreeze(adi_apollo_device_t *device); + +/** + * \brief Stops(aborts) MCS Background Tracking Calibration. TDC measurement and phase correction routine will stop. + * \note This will set all MCS configuration settings to 0 and disable TDC measurements. + * To restart, user would have to re-configure MCS cal config and re-initialize it. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure. + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_mcs_cal_bg_tracking_abort(adi_apollo_device_t *device); + +/** + * \brief Force a MCS Foreground Tracking Calibration for fast SysRef alignment. + * \note This is only used if user doesn't want conventional MCS FG Tracking cal and want to send phase correction only when needed. + * It is recommended to run this AFTER \ref adi_apollo_mcs_cal_init_run(). + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure. + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_mcs_cal_force_fg_tracking_run(adi_apollo_device_t *device); + +/** + * \brief Force a ONE TIME MCS Background Tracking Calibration for maintaining SysRef alignment. + * \note This is only used if user doesn't want conventional PERIODIC MCS BG Tracking cal and want to send phase correction only when needed. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure. + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_mcs_cal_force_bg_tracking_run(adi_apollo_device_t *device); + +/** + * \brief Performs a coarse bleed current adjustment on ADF4382. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure. + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_mcs_cal_coarse_jump_set(adi_apollo_device_t *device); + +/** + * \brief Get status of MCS Tracking Calibration. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure. + * \param[out] cal_status Pointer to struct containing MCS tracking cal error and state info. \ref adi_apollo_mcs_cal_status_t. + * + * \return API_CMS_ERROR_OK API Completed Successfully. + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_mcs_cal_tracking_status_get(adi_apollo_device_t *device, adi_apollo_mcs_cal_status_t *cal_status); + + +#ifndef CLIENT_IGNORE + + +#endif /* CLIENT_IGNORE*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_MCS_CAL_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_mcs_cal_types.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_mcs_cal_types.h new file mode 100644 index 00000000000000..e306f7ece71833 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_mcs_cal_types.h @@ -0,0 +1,330 @@ +/*! + * \brief Multi Chip Sync Calibration user defined types definition header + * + * \copyright copyright(c) 2024 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_MCS_CAL + * @{ + */ +#ifndef __ADI_APOLLO_MCS_CAL_TYPES_H__ +#define __ADI_APOLLO_MCS_CAL_TYPES_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_cms_api_common.h" +#include "adi_apollo_common.h" + +#ifdef DOXYGEN_RUN +#define ADI_APOLLO_PACKED(s) s +#else +#include "adi_apollo_platform_pack.h" +#endif + +#ifdef __GNUC__ +#define ADI_APOLLO_PACK_ENUM __attribute__((packed)) +#else +#define ADI_APOLLO_PACK_ENUM +#endif + +/*============================================================================* + * D E F I N E S * + *============================================================================*/ +#define ADF4382_MAX_COARSE_CODE (15U) +#define ADF4382_MAX_FINE_CODE (511U) +#define ADF4382_NUM_STROBES_TO_COVER_FINE_RANGE (128U) +#define MCS_MAX_NUM_INST (3U) +#define MCS_MAX_NUM_EVENTS (3U) + +/*============================================================================* + * E N U M S * + *============================================================================*/ +/** + * MCS Parameter Enumerations + */ +typedef enum { + MCS_PARAMS_ALL = 0, /*!< Set the entire MCS FW config structure. */ + MCS_USE_SIDE_A_AS_REFERENCE_UINT8 = 1, /*!< Set to 1, Side A is used as reference when aligning or comparing against Side B while using Center TDC. */ + MCS_USE_GAPPED_SYSREF_UINT8 = 2, /*!< Set to 1, External SysRef is 'Gapped-Periodic'. Meaning, the signal randomly misses cycles. The nominal period of External SysRef must be Exactly the same as internal SysRef period.*/ + MCS_LEAVE_SYSREF_RECEIVER_ON_POST_SYNC_UINT8 = 3, /*!< If set to 1, Apollo's External SysRef receiver is left turned on post MCS init Calibration.Set to 1 if running MCS Tracking calibration. */ + MCS_TRACK_ABORT_UINT8 = 4, /*!< Set to 1, MCS Tracking calibration will clear configuration variables, including ADF4382 Current DAC correction values, and will enter idle, waiting for users to configure the next action. */ + MCS_TRACK_HALT_UINT8 = 5, /*!< Set to 1, MCS Tracking calibration will bypass MCS tracking calibration. It will not use TDC or send commands to ADF4382.*/ + MCS_TRACK_INITIALIZE_UINT8 = 6, /*!< Set to 1, MCS Tracking calibration will take the user-defined track_start_coarse, track_start_fine, track_start_bleed_pol, maxFineCode, maxCoarseCode track_win, and adi_apollo_track_target as initial values for MCS Tracking calibration. */ + MCS_TRACK_FOREGROUND_UINT8 = 7, /*!< It can only be used after track_initialize has finished. Set to 1, track_foreground will run TDC measurements and send ADF4382 correction signals at a faster rate than track_background. */ + MCS_TRACK_FORCE_FOREGROUND_UINT8 = 8, /*!< It can only be used after track_initialize has finished. Set to 1, track_force_foreground will execute track_foreground. It is self-clearing. It can be written to 1 to re-run foreground. */ + MCS_TRACK_BACKGROUND_0_UINT8 = 9, /*!< Set to 1, MCS tracking calibration will measure time differences with TDC, and send correction signals to the single or side A's ADF4382. Up to 1 correction signal will be sent per second.*/ + MCS_TRACK_BACKGROUND_1_UINT8 = 10, /*!< Set to 1, MCS tracking calibration will measure time differences with TDC, and send correction signals to Side B's ADF4382. Up to 1 correction signal will be sent per second.*/ + MCS_TRACK_COARSE_JUMP_0_UINT8 = 11, /*!< Set to 1 to allow the single or side A's ADF4382 to do one Coarse DAC adjustment. */ + MCS_TRACK_COARSE_JUMP_1_UINT8 = 12, /*!< Set to 1 to allow side B's ADF4382 to do one Coarse DAC adjustment. */ + MCS_TRACK_FORCE_BACKGROUND_STEP_0_UINT8 = 13, /*!< Allows for one track_background calibration cycle to be performed with the single or side A's ADF4382 while tracking calibration is halted. It may or may not send a strobe signal to the single or side A's ADF4382 */ + MCS_TRACK_FORCE_BACKGROUND_STEP_1_UINT8 = 14, /*!< Allows for one track_background calibration cycle to be performed with side B's ADF4382 while tracking calibration is halted. It may or may not send a strobe signal to the single or side A's ADF4382 */ + MCS_MEASUREMENT_DECIMATION_RATE_UINT16 = 15, /*!< Controls the number of External sysref measurements that MCS digital performs using TDC. If set to 65535, the total number of measurements are: 16*(65535 + 1) = 1048576. */ + MCS_REFERENCE_PERIOD_C_UINT64 = 16, /*!< External sysref period driven to the center sysref receiver in femtoseconds. Must be non-zero in any MCS init or tracking mode. */ + MCS_REFERENCE_PERIOD_A_UINT64 = 17, /*!< Usually, External sysref period driven to the Side A's sysref receiver in femtoseconds. Must be non-zero in any MCS init or tracking mode. If MCS Init Cal mode = 3, 4, or 5, and use_side_A_as_reference == 0; then, the Internal SysRef period in femtoseconds of the B-side's Internal Sysref should be provided. */ + MCS_REFERENCE_PERIOD_B_UINT64 = 18, /*!< Usually, External sysref period driven to the Side B's sysref receiver in femtoseconds. Must be non-zero in any MCS init or tracking mode. If MCS Init Cal mode = 3, 4, or 5, and use_side_A_as_reference == 1; then, the Internal SysRef period in femtoseconds of the B-side's Internal Sysref should be provided. */ + MCS_OFFSET_C_FEMTOSECONDS_INT64 = 19, /*!< Desired time difference between the rising edge of Center MCS's Internal sysref and the rising edge of Center External SysRef. Notice, we can only adjust in steps of 1 high-speed clock period during MCS init Cal. */ + MCS_OFFSET_A_FEMTOSECONDS_INT64 = 20, /*!< Desired time difference between the rising edge of Side A MCS's Internal sysref and the rising edge of its reference sysref. Notice, we can only adjust in steps of 1 high-speed clock period during MCS init Cal. */ + MCS_OFFSET_B_FEMTOSECONDS_INT64 = 21, /*!< Desired time difference between the rising edge of Side B MCS's Internal sysref and the rising edge of it reference sysref. Notice, we can only adjust in steps of 1 high-speed clock period during MCS init Cal. */ + MCS_ADF4382_DEL_MODE_UINT8 = 22, /*!< Equivalent to DEL_MODE in ADF4382 datasheet. */ + MCS_ADF4382_TRACK_START_COARSE_UINT8 = 23, /*!< User-Defined starting value for Coarse DAC Correction. */ + MCS_ADF4382_TRACK_START_BLEED_POL_UINT8 = 24, /*!< User-Defined starting value for DAC Bleed Polarity. */ + MCS_ADF4382_TRACK_POLARITY_SELECT_UINT8 = 25, /*!< Set to 1 to invert the polarity of correction. */ + MCS_ADF4382_PHASE_ADJUSTMENT_UINT8 = 26, /*!< Increments on the ADF4382's Bleed Current Correction DAC per strobe. Must be programmed to match register phase_adjustment on ADF4382. */ + MCS_ADF4382_TRACK_START_FINE_UINT16 = 27, /*!< User-Defined starting value for Fine DAC Correction. */ + MCS_ADF4382_DELSTR_GPIO_0_UINT8 = 28, /*!< AD9084's GPIO to be used as DELSTR for the single or Side A's ADF4382. */ + MCS_ADF4382_DELSTR_GPIO_1_UINT8 = 29, /*!< AD9084's GPIO to be used as DELSTR for Side B's ADF4382. */ + MCS_ADF4382_DELADJ_GPIO_0_UINT8 = 30, /*!< AD9084's GPIO to be used as DELADJ for the single or Side A's ADF4382. */ + MCS_ADF4382_DELADJ_GPIO_1_UINT8 = 31, /*!< AD9084's GPIO to be used as DELADJ for Side B's ADF4382. */ + MCS_ADF4382_TRACK_WIN_UINT32 = 32, /*!< Time in in absolute-value femtoseconds allowed for internal sysref to drift with respect to external sysref before MCS Tracking Calibration sends adjustments to ADF4382. */ + MCS_ADF4382_TRACK_TARGET_0_INT32 = 33, /*!< Time offset in picoseconds between the rising edge of internal and External sysref for the single or Side A's ADF4382. */ + MCS_ADF4382_TRACK_TARGET_1_INT32 = 34, /*!< Time offset in picoseconds between the rising edge of internal and External sysref for Side B's ADF4382. */ + MCS_PARAMETER_LAST = 0xFF +} ADI_APOLLO_PACK_ENUM adi_apollo_mcs_parameter_e; + +/** + * @brief MCS init cal state + * + */ +typedef enum { + MCS_START = 0U, /*!< Start state */ + MCS_SETUP_MEAS = 1U, /*!< State to setup and start measurement */ + MCS_EVENT_WAIT = 2U, /*!< Event wait state, interrupt or polling */ + MCS_PROCESS_MEAS = 3U, /*!< State to process measurement results */ + MCS_ALIGN_CLOCKS = 4U, /*!< State to align clocks */ + MCS_CLEANUP = 5U, /*!< State to cleanup */ + MCS_FINAL = 6U, /*!< Dummy Final state to indicate completion */ +} ADI_APOLLO_PACK_ENUM adi_apollo_mcs_fsmstate_e; + +/** + * @brief Tracking cal state definition. + * + */ +typedef enum { + track_state_reset = 0, + track_state_init_done = 1, + track_state_foreground_done = 2, /*!< Foreground is complete */ + track_state_background_running = 3, /*!< Tracking is good */ + track_state_background_running_active_fault = 4, /*!< There is an error that needs adjusting */ + track_state_last_state = 5, /*!< Marks last state */ +} ADI_APOLLO_PACK_ENUM adi_apollo_mcs_cal_track_state_e; + +/** + * @brief Representation of the mode types that ADF4382 can operate. + * Mirror of bit 5 (DEL_MODE) at address 0x32 in ADF4382 IC. + */ +typedef enum { + CpBld_Mode = 0, /*!< Charge Pump Bleed current mode (Integer mode) */ + Frac0_Mode = 1 /*!< Fractional-N operation with the fraction=0 mode */ +} ADI_APOLLO_PACK_ENUM adi_apollo_drv_adf4382_delay_mode_e; + +/*============================================================================* + * S T R U C T S * + *============================================================================*/ +/** + * @brief Structure to hold the ADF4382' GPIO control pins. + * + */ +typedef struct { + uint8_t clock_deladj[2]; + uint8_t clock_delstr[2]; +} adi_apollo_drv_adf4382_gpio_map_t; + +/** + * @brief ADF4382 specific configuration object. + * + */ +ADI_APOLLO_PACKED( +typedef struct { + adi_apollo_drv_adf4382_delay_mode_e del_mode; /*!< 0: Integer = 0, frac-N = 1 */ + uint8_t track_start_coarse; /*!< 1: what is the initial coarse code applied to adf4382 */ + uint8_t track_start_bleed_pol; /*!< 2: Direction the fine and coarse DACs are setup for 0 = positive DAC, 1 = negative DAC */ + uint8_t track_polarity_select; /*!< 3: Variable used just in case feedback to adf4382 is wrong direction. */ + uint8_t phase_adjustment; /*!< 4: Number of fine steps taken on each DELSTR */ + uint8_t pad8; /*!< 5: 1-byte padding */ + uint16_t track_start_fine; /*!< 6: what is the initial fine code applied to adf4382 */ + uint8_t DELSTR_gpio[2]; /*!< 7: Which GPIO to use for DELSTR */ + uint8_t pad[2]; + uint8_t DELADJ_gpio[2]; /*!< 8: Which GPIO to use for DELADJ */ + uint8_t pad2[2]; + uint32_t track_win; /*!< 9: Tracking window size in femtoseconds */ + int32_t track_target[2]; /*!< 10: Track target (offset) in femtoseconds for mode with one TDC per ADF4382 */ +} adi_apollo_drv_adf4382_config_t;) + +/** + * @brief ADF4382 specific status object. + * + */ +ADI_APOLLO_PACKED( +typedef struct { + uint8_t bleed_pol; /*!< 0: 1 = Negative, 0 = positive */ + int8_t current_coarse_value; /*!< 1: Should be less than +/- coarse range */ + int16_t current_fine_value; /*!< 2: INT mode: Within Fine range; FRAC mode: Any integer */ + uint8_t EOR_POS; /*!< 4: Positive edge of fine range */ + uint8_t EOR_NEG; /*!< 5: Negative edge of fine range */ + uint8_t EOR_Coarse; /*!< 6: Coarse out of range */ + uint8_t padding_byte; /*!< 7: Padding bytes */ +} adi_apollo_drv_adf4382_status_t;) + +/** + * \brief Data structure to hold common init and tracking calibration status information + */ +ADI_APOLLO_PACKED( +typedef struct { + uint32_t errorCode; + uint32_t percentComplete; + uint32_t performanceMetric; + uint32_t iterCount; + uint32_t updateCount; +} adi_apollo_CalStatus_t;) + +/** + * @brief MCS Calibration Configuration + * + */ +ADI_APOLLO_PACKED( +typedef struct { + uint8_t use_side_A_as_reference; /*!< For ADI_APOLLO_MCS_INIT_MODE3/3/4, 0 = Use Side B Ref, 1 = Use Side A Ref */ + uint8_t use_gapped_sysref; /*!< If 1, detecting true period of gapped sysref signal is enabled */ + uint8_t pad8; + uint8_t leave_sysref_receiver_ON_post_sync; /*!< 0 = switch off sysref receiver, 1 = leave sysref receiver on */ + uint8_t track_abort; /*!< Set to 1 to abort MCS Tracking calibration and Disable AD9084's TDC Hardware. */ + uint8_t track_halt; /*!< Set to 1 to bypass MCS Tracking Calibration cycle. */ + uint8_t track_initialize; /*!< Set to 1 to capture the user-defined initial settings and enable AD9084's TDC and GPIO Hardware. */ + uint8_t pad8_2; + uint8_t track_foreground; /*!< Set to 1 to run fast tunning of internal and external sysref. Requires halt = 0. Suggested usage: post MCS Init Calibration. */ + uint8_t track_force_foreground; /*!< Set to 1 to run fast tunning of internal and external sysref. Bypasses halt = 1. */ + uint8_t track_background[2]; /*!< Set to 1 to enable MCS tracking calibration cycle: TDC run, if needed, Send Strobe. Requires halt = 0. One calibration cycle per second. */ + uint8_t track_coarse_jump[2]; /*!< Set to 1 to allow crossing of coarse bleed current DAC values on ADF4382. */ + uint8_t track_force_background_step[2]; /*!< Set to 1 to enable MCS tracking calibration cycle: TDC run, if needed, Send Strobe. Bypasses halt = 1. One calibration cycle per second. */ + uint16_t measurement_decimation_rate; /*!< Decimation Rate used by AD9084's TDC digital. Total SysRef measurements = 16*(decimation + 1) */ + uint16_t pad16; + uint64_t reference_period_C_femtoseconds; /*!< Reference Period in femtoseconds of side center MCS */ + uint64_t reference_period_A_femtoseconds; /*!< Reference Period in femtoseconds of side A MCS */ + uint64_t reference_period_B_femtoseconds; /*!< Reference Period in femtoseconds of side B MCS */ + int64_t offset_C_femtoseconds; /*!< 64 Bits of Offset in femtoseconds of center MCS */ + int64_t offset_A_femtoseconds; /*!< 64 Bits of Offset in femtoseconds of side A MCS */ + int64_t offset_B_femtoseconds; /*!< 64 Bits of Offset in femtoseconds of side B MCS */ + adi_apollo_drv_adf4382_config_t adf4382_specific_config; +} adi_apollo_mcs_cal_config_t;) + +/** + * @brief MCS Private Calibration Status + * + */ +ADI_APOLLO_PACKED( +typedef struct { + uint8_t foreground_done; /*!< 0: Indicate if Foreground cal completed. 1 byte */ + adi_apollo_mcs_cal_track_state_e track_state[2]; /*!< 1: 0 = init, 1 = track good, 2 = track error; 2 bytes */ + uint8_t track_lock[2]; /*!< 2: Signals are within tracking window distance of one another; 2 bytes */ + uint8_t halt_active; /*!< 3: Indicate if the calibration executed the halt command; 1 byte */ + uint8_t force_background_done[2]; /*!< 4: Indicates if a Force Background Step Complete; 2 bytes */ + uint8_t abort_done; /*!< 5: Indicates if abort has completed. 1 bytes */ + uint8_t pad_to_64bits[7]; /*!< 6: Padding to bring to long long size. 7 bytes */ + adi_apollo_drv_adf4382_status_t adf4382_specific_status[2]; /*!< 7: ADF4382 specific status; 16 bytes */ + int64_t current_measure[2]; /*!< 8: Current measurement before last adjustment [femtoseconds] */ +} adi_apollo_mcs_private_cal_status_t;) + +/** + * @brief MCS Calibration Status + * + */ +ADI_APOLLO_PACKED( +typedef struct { + adi_apollo_CalStatus_t hdr; /*!< Header. */ + uint32_t pad32; + adi_apollo_mcs_private_cal_status_t mcs_tracking_cal_status; /*!< MCS Tracking Calibration Status and Data. */ +} adi_apollo_mcs_cal_status_t;) + +/** + * @brief MCS Calibration Data + * + * Interpretation of adi_apollo_mcs_cal_data_t: + * Center, Side A and Side B here do not refer to the MCS which is being used, but the internal sysref which is being aligned, and they + * may or not be the same. + * ADI_APOLLO_MCS_MODE0: diff_C_Before_femtoseconds/Aft, internal_period_C_femtoseconds, is_C_Locked. + * ADI_APOLLO_MCS_MODE1: diff_B_Before_femtoseconds/Aft, internal_period_B_femtoseconds, is_B_Locked, diff_A_Before_femtoseconds/Aft, internal_period_A_femtoseconds, is_A_Locked. + * ADI_APOLLO_MCS_MODE2: if use_side_A_as_reference == 0, diff_A_Before_femtoseconds/Aft, internal_period_A_femtoseconds, is_A_Locked (Side B internal sysref taken as reference). + * if use_side_A_as_reference == 1, diff_B_Before_femtoseconds/Aft, internal_period_B_femtoseconds, is_B_Locked (Side A internal sysref taken as reference). + * ADI_APOLLO_MCS_MODE3: if use_side_A_as_reference == 0, diff_A_Before_femtoseconds, internal_period_A_femtoseconds (Side B internal sysref is taken as reference). + * if use_side_A_as_reference == 1, diff_B_Before_femtoseconds, internal_period_B_femtoseconds (Side A internal sysref is taken as reference). + * ADI_APOLLO_MCS_MODE4: diff_B_Before_femtoseconds/Aft, internal_period_B_femtoseconds, is_B_Locked, diff_A_Before_femtoseconds/Aft, internal_period_A_femtoseconds, is_A_Locked. use_side_A_as_reference == 0 + * means that Side B TDC is used for Step 1 and Side B internal sysref is aligned, and in Step 2, Side A internal + * sysref is aligned. If use_side_A_as_reference == 1, Side A TDC is used for Step 1 and Side A internal sysref is aligned, + * and in Step 2, Side B internal sysref is aligned + */ +ADI_APOLLO_PACKED( +typedef struct { + uint8_t is_C_Locked; /*!< Is Center Int Sysref Locked? */ + uint8_t is_A_Locked; /*!< Is Side A Int Sysref Locked? */ + uint8_t is_B_Locked; /*!< Is Side A Int Sysref Locked? */ + uint8_t pad8[5]; + int64_t diff_C_Before_femtoseconds; /*!< Time Difference Bef Alignment of Ctr Int Sysref in femtosecond */ + int64_t diff_A_Before_femtoseconds; /*!< Time Difference Bef Alignment of Side A Int Sysref in femtosecond */ + int64_t diff_B_Before_femtoseconds; /*!< Time Difference Bef Alignment of Side B Int Sysref in femtosecond */ + int64_t internal_period_C_femtoseconds; /*!< Period of (usually internal) sysref for Center MCS in femtosecond */ + int64_t internal_period_A_femtoseconds; /*!< Period of (usually internal) sysref for Side A MCS in femtosecond */ + int64_t internal_period_B_femtoseconds; /*!< Period of (usually internal) sysref for Side B MCS in femtosecond */ + int64_t diff_C_After_femtoseconds; /*!< Time Difference Aft Alignment of Ctr Int Sysref in femtosecond */ + int64_t diff_A_After_femtoseconds; /*!< Time Difference Aft Alignment of Side A Int Sysref in femtosecond */ + int64_t diff_B_After_femtoseconds; /*!< Time Difference Aft Alignment of Side B Int Sysref in femtosecond */ + int64_t recommended_offset_C_femtoseconds; /*!< Recommended offset Aft Alignment of Ctr Int Sysref in femtosecond */ + int64_t recommended_offset_A_femtoseconds; /*!< Recommended offset Aft Alignment of Side A Int Sysref in femtosecond */ + int64_t recommended_offset_B_femtoseconds; /*!< Recommended offset Aft Alignment of Side B Int Sysref in femtosecond */ +} adi_apollo_mcs_cal_data_t;) + +/** + * @brief MCS calInit Status structure + * + */ +ADI_APOLLO_PACKED( +typedef struct { + adi_apollo_CalStatus_t hdr; /*!< Header. */ + uint32_t mcsErr; /*!< MCS Init Calibration error code. */ + adi_apollo_mcs_cal_data_t data; /*!< MCS Init Calibration Status and Data. */ +} adi_apollo_mcs_cal_init_status_t;) + +/** + * @brief MCS Calibration State + * + * firstPassDone is only relevant to ADI_APOLLO_MCS_MODE4 and identifies step 1 or step 2 + * alignDone identifies measurement or remeasurement phase + * event_waiting is the event being waited for in MCS_EVENT_WAIT state + */ +ADI_APOLLO_PACKED( +typedef struct { + adi_apollo_mcs_fsmstate_e fsmState; /*!< FSM State */ + adi_apollo_mcs_fsmstate_e prevFsmState; /*!< Previous FSM State */ + uint8_t event_waiting; /*!< Event being waited for*/ + uint8_t alignDone; /*!< Is Alignment Done */ + uint8_t is_Side_A_Done; /*!< Is Side A Done Flag */ + uint8_t is_Side_B_Done; /*!< Is Side B Done Flag */ + uint8_t firstPassDone; /*!< First Pass Done */ + uint8_t isDone; /*!< Is MCS Operation Done */ + uint8_t extraSyncStep; /*!< Extra sync phase for modes 2 and 4 */ + uint8_t partial_alignment_done; /*!< Counter Measure for Extra rotations from divG */ + uint8_t tdc_precondition_is_completed; /*!< Flag that will indicate if we already completed the TDC precondition */ + uint8_t pad8_cal_state[3]; /*!< Padding */ +} adi_apollo_mcs_cal_state_t;) + +#ifndef CLIENT_IGNORE +/** + * @brief Top level MCS object + * + */ +ADI_APOLLO_PACKED( +typedef struct { + uint8_t *p_base_mcs_tdc_regmap[MCS_MAX_NUM_INST]; /*!< Pointers to base address of MCS TDC regmaps */ + adi_apollo_mcs_cal_config_t *config; /*!< Pointer to config object */ + adi_apollo_mcs_cal_init_status_t cal_init_status; /*!< Status data for the init cal */ + adi_apollo_mcs_cal_status_t tracking_status; /*!< Status data for the tracking cal */ + adi_apollo_mcs_cal_state_t state; /*!< State object */ + uint8_t event_flags[MCS_MAX_NUM_EVENTS]; /*!< Event flag array */ + uint8_t pad; +} adi_apollo_mcs_t;) +#endif // !CLIENT_IGNORE + +#endif /* __ADI_APOLLO_MCS_CAL_TYPES_H__ */ +/*! @} */ \ No newline at end of file diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_pfilt.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_pfilt.h new file mode 100644 index 00000000000000..2168e045c2c29b --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_pfilt.h @@ -0,0 +1,241 @@ +/*! + * \brief PFILT Block definition headers + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_PFILT + * @{ + */ +#ifndef __ADI_APOLLO_PFILT_H__ +#define __ADI_APOLLO_PFILT_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_pfilt_types.h" + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Configure PFILT MODE parameters + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] pfilts Target PFILT \ref adi_apollo_pfilt_sel_e + * \param[in] config \ref adi_apollo_pfilt_mode_pgm_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_pfilt_mode_pgm(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t pfilts, adi_apollo_pfilt_mode_pgm_t *config); + +/** + * \brief Configure PFILT gain and delay parameters + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] pfilts Target PFILT \ref adi_apollo_pfilt_sel_e + * \param[in] pfilt_banks Target PFILT coeff banks \ref adi_apollo_pfilt_bank_sel_e + * \param[in] config \ref adi_apollo_pfilt_gain_dly_pgm_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_pfilt_gain_dly_pgm(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t pfilts, uint8_t pfilt_banks, adi_apollo_pfilt_gain_dly_pgm_t *config); + +/** + * \brief Configure PFILT coeff parameters + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] pfilts Target PFILT a mask of which pfilt + * \param[in] pfilt_banks Target PFILT coeff banks \ref adi_apollo_pfilt_bank_sel_e + * \param[in] pfilt_coeff Coefficient values for the PFILT bank + * \param[in] length Coefficient values for the PFILT bank array size + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_pfilt_coeff_pgm(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t pfilts, uint8_t pfilt_banks, int16_t pfilt_coeff[], uint32_t length); + +/** + * \brief Set PFILT coeffs for Real-N, Real-N/2 or Real-N/4 modes + * + * \note Real-N = 32 taps, Real-N/2 = 16 taps, Real-N/4 = 8 taps + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] pfilts Target PFILT (ADI_APOLLO_PFILT_A0, A1, B0, A1) \ref adi_apollo_pfilt_sel_e + * \param[in] pfilt_banks Target PFILT coeff banks (ADI_APOLLO_PFILT_BANK0, 1, 2, 3) \ref adi_apollo_pfilt_bank_sel_e + * \param[in] streams Streams to set coeffs for (ADI_APOLLO_PFILT_STREAM_0, _1) \ref adi_apollo_pfilt_stream_sel_e + * \param[in] ntap_mode Num real taps (ADI_APOLLO_PFILT_MODE_N_REAL, _N_DIV_BY_2_REAL, _N_DIV_BY_4_REAL) \ref adi_apollo_pfilt_mode_e + * \param[in] coeffs Coefficient values for the PFILT bank + * \param[in] coeffs_len Length of coeffs array + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_pfilt_coeff_ntap_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t pfilts, uint8_t pfilt_banks, + uint16_t streams, adi_apollo_pfilt_mode_e ntap_mode, int16_t coeffs[], uint32_t coeffs_len); + +/** + * \brief Set PFILT coeffs for half-complex mode + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] pfilts Target PFILT (ADI_APOLLO_PFILT_A0, A1, B0, A1) \ref adi_apollo_pfilt_sel_e + * \param[in] pfilt_banks Target PFILT coeff banks (ADI_APOLLO_PFILT_BANK0, 1, 2, 3) \ref adi_apollo_pfilt_bank_sel_e + * \param[in] coeffs0 Coefficient values for first stream + * \param[in] coeffs1 Coefficient values for second stream + * \param[in] coeffs_len Length of each coeff array + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_pfilt_coeff_half_complex_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t pfilts, uint8_t pfilt_banks, + int16_t coeffs0[], int16_t coeffs1[], uint32_t coeffs_len); + +/** + * \brief Set PFILT coeffs for full-matrix mode + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] pfilts Target PFILT (ADI_APOLLO_PFILT_A0, A1, B0, A1) \ref adi_apollo_pfilt_sel_e + * \param[in] pfilt_banks Target PFILT coeff banks (ADI_APOLLO_PFILT_BANK0, 1, 2, 3) \ref adi_apollo_pfilt_bank_sel_e + * \param[in] coeffs0 Coefficient values + * \param[in] coeffs1 Coefficient values + * \param[in] coeffs2 Coefficient values + * \param[in] coeffs3 Coefficient values + * \param[in] coeffs_len Length of each coefficient array (N/4, 8 taps) + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_pfilt_coeff_full_matrix_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t pfilts, uint8_t pfilt_banks, + int16_t coeffs0[], int16_t coeffs1[], int16_t coeffs2[], int16_t coeffs3[], uint32_t coeffs_len); + +/** + * \brief Set PFILT delay fir half-complex mode + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] pfilts Target PFILT (ADI_APOLLO_PFILT_A0, A1, B0, A1) \ref adi_apollo_pfilt_sel_e + * \param[in] pfilt_banks Target PFILT coeff banks (ADI_APOLLO_PFILT_BANK0, 1, 2, 3) \ref adi_apollo_pfilt_bank_sel_e + * \param[in] delay Delay stream value (in terms of samples) + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_pfilt_half_complex_delay_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t pfilts, uint8_t pfilt_banks, uint8_t delay); + +/** + * \brief Select filter bank to transfer to active + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] pfilts Target PFILT select mask \ref adi_apollo_pfilt_sel_e + * \param[in] bank_sel Coeff bank to transfer to active (single selection) \ref adi_apollo_pfilt_bank_sel_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_pfilt_coeff_transfer(adi_apollo_device_t* device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t pfilts, uint8_t bank_sel); + +/** + * \brief Inspect RX PFILT parameters + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] pfilt Target PFILT \ref adi_apollo_pfilt_sel_e + * \param[out] pfilt_inspect Pointer to pfilt inspect struct \ref adi_apollo_pfilt_inspect_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_pfilt_inspect(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t pfilt, adi_apollo_pfilt_inspect_t *pfilt_inspect); + +/** + * \brief Set the PFILT mode only, can be used to enable or bypass the filter + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] pfilts Target PFILT \ref adi_apollo_pfilt_sel_e + * \param[in] iq_sel Bit-or select of I(stream 0) and Q(stream 1) \ref adi_apollo_pfilt_stream_sel_e + * \param[in] mode PFILT mode or disable \ref adi_apollo_pfilt_mode_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_pfilt_mode_enable_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t pfilts, uint8_t iq_sel, adi_apollo_pfilt_mode_e mode); + +/** + * \brief Set the PFILT profile selection and hopping mode + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] pfilts Target PFILT (ADI_APOLLO_FILT_A0, A1, B0, B1) \ref adi_apollo_pfilt_sel_e + * \param[in] prof_sel_mode Profile select mode. Can be direct spi, regmap and trig based. \ref adi_apollo_pfilt_profile_sel_mode_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_pfilt_profile_sel_mode_set(adi_apollo_device_t* device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t pfilts, const adi_apollo_pfilt_profile_sel_mode_e prof_sel_mode); + +/** + * \brief Set the next PFILT profile selection or hop + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] pfilts Target PFILT (ADI_APOLLO_PFILT_A0, A1, B0, B1) \ref adi_apollo_pfilt_sel_e + * \param[in] hop_num Profile (e.g. coeff set) to hop to. Will be immediate if in direct regmap mode, or scheduled for next trigger. + * + * The behavior of the function is influenced by adi_apollo_pfilt_profile_sel_mode_set(). + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_pfilt_next_hop_num_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t pfilts, int16_t hop_num); + +/** + * \brief Set the Rx PFILT ADC averaging mode + * + * \note PFILT averaging only applicable to Rx PFILT + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] pfilts Target PFILT (ADI_APOLLO_PFILT_A0, A1, B0, B1) \ref adi_apollo_pfilt_sel_e + * \param[in] ave_mode Average mode (ADI_APOLLO_PFILT_AVE_DISABLE, ENABLE_AVE, ENABLE_SUB) \ref adi_apollo_pfilt_ave_mode_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_pfilt_ave_mode_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t pfilts, adi_apollo_pfilt_ave_mode_e ave_mode); + +/** + * \brief Set the PFILT data type for real or complex processing + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] pfilts Target PFILT (ADI_APOLLO_PFILT_A0, A1, B0, B1) \ref adi_apollo_pfilt_sel_e + * \param[in] data_type PFILT input data type (ADI_APOLLO_PFILT_COMPLEX_DATA, _REAL_DATA) \ref adi_apollo_pfilt_data_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_pfilt_data_type_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t pfilts, adi_apollo_pfilt_data_e data_type); + +#ifndef CLIENT_IGNORE + +#endif /* CLIENT_IGNORE*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_PFILT_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_pfilt_types.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_pfilt_types.h new file mode 100644 index 00000000000000..f33c47b57a616a --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_pfilt_types.h @@ -0,0 +1,136 @@ +/*! + * \brief PFILT Block definition headers + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_PFILT + * @{ + */ +#ifndef __ADI_APOLLO_PFILT_TYPES_H__ +#define __ADI_APOLLO_PFILT_TYPES_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_cms_api_common.h" +#include "adi_apollo_common.h" + +/*============= D E F I N E S ==============*/ +#define ADI_APOLLO_PFILT_NUM 4 +#define ADI_APOLLO_PFILT_BANK_NUM 4 +#define ADI_APOLLO_PFILT_PER_SIDE 2 +#define ADI_APOLLO_PFILT_BANKS_PER_REGMAP 2 +#define ADI_APOLLO_PFILT_COEFF_NUM 32 +#define ADI_APOLLO_PFILT_STREAMS_NUM 2 + +/*! +* \brief Enumerates PFLIT selection +*/ + +/*! +* \brief Enumerates A PFILT selection +*/ +typedef enum +{ + ADI_APOLLO_PFILT_NONE = 0x0, /*!< No PFILT */ + ADI_APOLLO_PFILT_A0 = 0x1, /*!< PFILT 0 of SIDE A */ + ADI_APOLLO_PFILT_A1 = 0x2, /*!< PFILT 1 of SIDE A (8t8r only) */ + ADI_APOLLO_PFILT_B0 = 0x4, /*!< PFILT 0 of SIDE B */ + ADI_APOLLO_PFILT_B1 = 0x8, /*!< PFILT 1 of SIDE B (8t8r only) */ + ADI_APOLLO_PFILT_ALL = 0xF, /*!< All PFILT (8T8R) */ + ADI_APOLLO_PFILT_ALL_4T4R = 0x5 /*!< All PFILT (4T4R) */ +} adi_apollo_pfilt_sel_e; + +/*! +* \brief Enumerates A PFILT stream selection +*/ +typedef enum { + ADI_APOLLO_PFILT_STREAM_NONE = 0x0, /*!< No PFILT streams */ + ADI_APOLLO_PFILT_STREAM_0 = 0x1, /*!< Stream 0 (I) */ + ADI_APOLLO_PFILT_STREAM_1 = 0x2, /*!< Stream 1 (Q) */ + ADI_APOLLO_PFILT_STREAM_ALL = 0x3, /*!< All PFILT streams */ +} adi_apollo_pfilt_stream_sel_e; + +/*! +* \brief Enumerates PFLIT COEFF BANK selection +*/ +typedef enum { + ADI_APOLLO_PFILT_BANK_NONE = 0x00, /*!< No PFILT BANK */ + ADI_APOLLO_PFILT_BANK0 = 0x01, /*!< 1st coeff bank */ + ADI_APOLLO_PFILT_BANK1 = 0x02, /*!< 2nd coeff bank */ + ADI_APOLLO_PFILT_BANK2 = 0x04, /*!< 3rd coeff bank */ + ADI_APOLLO_PFILT_BANK3 = 0x08, /*!< 4th coeff bank */ + ADI_APOLLO_PFILT_BANK_ALL = 0x0F, /*!< All PFILT BANK */ +} adi_apollo_pfilt_bank_sel_e; + +/*! +* \brief Enumerates PFILT profile selection mode +*/ +typedef enum +{ + ADI_APOLLO_PFILT_CHAN_SEL_DIRECT_REGMAP = 0, /*!< Direct spi/hsci PFILT hop select */ + ADI_APOLLO_PFILT_CHAN_SEL_DIRECT_GPIO = 1, /*!< Direct GPIO hop select cfg 0, GPIO[1:0] switch between all 4 coeff sets */ + ADI_APOLLO_PFILT_CHAN_SEL_DIRECT_GPIO_1 = 2, /*!< Direct GPIO hop select cfg 1, GPIO[0] stream 0, GPIO[1] stream 1 */ + ADI_APOLLO_PFILT_CHAN_SEL_TRIG_REGMAP = 3, /*!< Trigger based hopping. Scheduled Regmap */ + ADI_APOLLO_PFILT_CHAN_SEL_TRIG_GPIO = 4, /*!< Trigger based hopping. Use GPIO[1:0] to select between all 4 coeff sets */ + ADI_APOLLO_PFILT_CHAN_SEL_TRIG_GPIO_1 = 5, /*!< Trigger based hopping alternate select. Use GPIO[0] to select for stream 0, GPIO[1] for stream 1 */ + ADI_APOLLO_PFILT_CHAN_SEL_NUM +} adi_apollo_pfilt_profile_sel_mode_e; + +/*! +* \brief Enumerates PFILT averaging selection mode +*/ +typedef enum +{ + ADI_APOLLO_PFILT_AVE_DISABLE = 0, /*!< Disable the averaging block ahead of PFILT */ + ADI_APOLLO_PFILT_AVE_ENABLE_ADD = 1, /*!< Enable the averaging block, add the two streams */ + ADI_APOLLO_PFILT_AVE_ENABLE_SUB = 2, /*!< Enable the averaging block, subtract the two streams */ + ADI_APOLLO_PFILT_AVE_NUM +} adi_apollo_pfilt_ave_mode_e; + +/*! +* \brief PFILT MODE programming data +*/ +typedef struct +{ + adi_apollo_pfilt_dq_mode_e dq_mode; /*!< Dual or quad mode \ref adi_apollo_pfilt_dq_mode_e */ + adi_apollo_pfilt_data_e data; /*!< Real or Complex data \ref adi_apollo_pfilt_data_e */ + uint8_t mode_switch; /*!< 0: Disable Modsw (averaging), 1: Enable */ + uint8_t add_sub_sel; /*!< 0: subtraction, 1: addition for Modsw (averaging) */ + adi_apollo_pfilt_mode_e pfir_i_mode[2]; /*!< Filter mode (e.g. bypass, real n/2, etc.) [1] valid for 8T8R devices only \ref adi_apollo_pfilt_mode_e */ + adi_apollo_pfilt_mode_e pfir_q_mode[2]; /*!< Filter mode (e.g. bypass, real n/2, etc.) [1] valid for 8T8R devices only \ref adi_apollo_pfilt_mode_e */ +} adi_apollo_pfilt_mode_pgm_t; + +/*! +* \brief PFILT gain and delay programming data +*/ +typedef struct { + adi_apollo_pfilt_gain_e pfir_ix_gain; /*!< \ref adi_apollo_pfilt_gain_e PFIR IX GAIN */ + adi_apollo_pfilt_gain_e pfir_iy_gain; /*!< \ref adi_apollo_pfilt_gain_e PFIR IY GAIN */ + adi_apollo_pfilt_gain_e pfir_qx_gain; /*!< \ref adi_apollo_pfilt_gain_e PFIR QX GAIN */ + adi_apollo_pfilt_gain_e pfir_qy_gain; /*!< \ref adi_apollo_pfilt_gain_e PFIR QY GAIN */ + uint8_t pfir_ix_scalar_gain; /*!< PFIR_IX_SCALAR_GAIN (6 bit Gain Multiplier)*/ + uint8_t pfir_iy_scalar_gain; /*!< PFIR_IY_SCALAR_GAIN (6 bit Gain Multiplier)*/ + uint8_t pfir_qx_scalar_gain; /*!< PFIR_QX_SCALAR_GAIN (6 bit Gain Multiplier)*/ + uint8_t pfir_qy_scalar_gain; /*!< PFIR_QY_SCALAR_GAIN (6 bit Gain Multiplier)*/ + uint8_t hc_delay; /*!< Programmable Delay for Half Complex Mode. Units are adc samples */ +} adi_apollo_pfilt_gain_dly_pgm_t; + +/*! +* \brief RX PFILT inspect param +*/ +typedef struct { + adi_apollo_pfilt_cfg_t dp_cfg; /*!< Parameters defined from device profile \ref apollo_cpu_device_profile_types.h */ + + uint8_t bank_sel; /*! Active filter bank (0-3) */ + uint8_t pfir_coeff_transfer; /*!< Coefficient Transfer Signal. Transfers all coefficient data from master to slave registers. */ + uint8_t eq_gpio_sel; /*!< 0: REGMAP_SELECT: use rd_coeffIpage_sel to select the coeff bank, 1: GPIO_SELECT: use i_eq_gpio to select coeff bank */ + uint8_t gpio_config1; /*!< 0: Disable: use i_eq_gpio[1:0] to select the coeff bank, 1: Enable: use part select of i_eq_gpio[1:0] to select coeff bank */ +} adi_apollo_pfilt_inspect_t; + +#endif /* __ADI_APOLLO_PFILT_TYPES_H__ */ + +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_platform_pack.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_platform_pack.h new file mode 100644 index 00000000000000..4114bd626be42f --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_platform_pack.h @@ -0,0 +1,59 @@ +/** + * \file adi_apollo_platform_pack.h + * + * \brief Contains platform pack define + * + * \details Contains platform pack define + * + * APOLLO API Version: $ADI_APOLLO_API_VERSION$ + */ + +/** + * Disclaimer Legal Disclaimer + * Copyright 2019 - 2019 Analog Devices Inc. + * Released under the APOLLO API license, for more information + * see the "LICENSE.PDF" file in this zip file. + */ + +#ifndef __ADI_APOLLO_PLATFORM_PACK_H__ +#define __ADI_APOLLO_PLATFORM_PACK_H__ + +#ifndef ADI_APOLLO_FW +#include "adi_apollo_user.h" +#endif + + +#if (!defined(ADI_APOLLO_PACK_START) || !defined(ADI_APOLLO_PACK_FINISH)) +#ifdef __GNUC__ +#define ADI_APOLLO_PACK_START _Pragma("pack(1)") +#define ADI_APOLLO_PACK_FINISH _Pragma("pack()") +#elif defined __ICCARM__ +#define ADI_APOLLO_PACK_START _Pragma("pack(1)") +#define ADI_APOLLO_PACK_FINISH _Pragma("pack()") +#elif defined _MSC_VER +#define ADI_APOLLO_PACK_START __pragma(pack(1)) +#define ADI_APOLLO_PACK_FINISH __pragma(pack()) +#else +#error ( "Define the ADI_APOLLO_PACK_START and ADI_APOLLO_PACK_FINISH macros for your compiler." ) +#endif +#endif + +#ifndef ADI_APOLLO_PACKED +#if defined __ICCARM__ +/* + * Error[Pm154]: in the definition of a function-like macro, each instance of a + * parameter shall be enclosed in parenthesis (MISRA C 2004 rule 19.10) + * + * ADI_APOLLO_PACKED() is a macro used for structure packing. The parameter + * for this macro must be a structure definition, which cannot be enclosed in + * parenthesis (syntatically invalid). + */ +#pragma diag_suppress=Pm154 +#define ADI_APOLLO_PACKED(d) _Pragma("pack(1)") d _Pragma("pack()") +#pragma diag_default=Pm154 +#else +#define ADI_APOLLO_PACKED(d) ADI_APOLLO_PACK_START d ADI_APOLLO_PACK_FINISH +#endif +#endif + +#endif /* __ADI_APOLLO_PLATFORM_PACK_H__ */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_reconfig.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_reconfig.h new file mode 100644 index 00000000000000..981146866241c0 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_reconfig.h @@ -0,0 +1,61 @@ +/*! + * \brief RECONFIG Block definition headers + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_RECONFIG + * @{ + */ +#ifndef __ADI_APOLLO_RECONFIG_H__ +#define __ADI_APOLLO_RECONFIG_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_reconfig_types.h" + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Configure reconfig controller modes of trigger, coherence, reconfiguration interval etc. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] sides Target side \ref adi_apollo_side_select_e + * \param[in] config \ref adi_apollo_reconfig_ctrl_pgm_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_reconfig_ctrl_pgm(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, uint8_t sides, adi_apollo_reconfig_ctrl_pgm_t *config); + +/** + * \brief Gets a reconfig controller's internal or trigger sync event counter. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal (ADI_APOLLO_RX, _TX) \ref adi_apollo_terminal_e + * \param[in] sides Target side select (ADI_APOLLO_SIDE_A, _B). One side per call. \ref adi_apollo_side_select_e + * \param[in] rec_type Reconfig controller trigger type (ADI_APOLLO_RECONFIG_EXTERNAL, _INTERNAL) \ref adi_apollo_reconfig_type_e + * \param[out] count Pointer to reconfig event count return val. This is a 4-bit value that rolls over. + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_reconfig_trig_evt_cnt_get(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, uint8_t sides, adi_apollo_reconfig_type_e rec_type, uint16_t *count); + +#ifndef CLIENT_IGNORE + +#endif /* CLIENT_IGNORE*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_RECONFIG_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_reconfig_types.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_reconfig_types.h new file mode 100644 index 00000000000000..80447316fa32b3 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_reconfig_types.h @@ -0,0 +1,74 @@ +/*! + * \brief RECONFIG Block definition headers + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_RECONFIG + * @{ + */ +#ifndef __ADI_APOLLO_RECONFIG_TYPES_H__ +#define __ADI_APOLLO_RECONFIG_TYPES_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_cms_api_common.h" +#include "adi_apollo_common.h" + +/*============= D E F I N E S ==============*/ + +/*! +* \brief Enumerates dynamic config selection +*/ +typedef enum { + ADI_APOLLO_RECONFIG_A0 = 0x1, /*!< 4t4r FDRC A0*/ + ADI_APOLLO_RECONFIG_A1 = 0x2, /*!< 4t4r FDRC A1*/ + ADI_APOLLO_RECONFIG_A2 = 0x4, /*!< 4t4r FDRC A2*/ + ADI_APOLLO_RECONFIG_A3 = 0x8, /*!< 4t4r FDRC A3*/ + ADI_APOLLO_RECONFIG_B0 = 0x10, /*!< 4t4r FDRC B0*/ + ADI_APOLLO_RECONFIG_B1 = 0x20, /*!< 4t4r FDRC B1*/ + ADI_APOLLO_RECONFIG_B2 = 0x40, /*!< 4t4r FDRC B2*/ + ADI_APOLLO_RECONFIG_B3 = 0x80, /*!< 4t4r FDRC B3*/ + ADI_APOLLO_RECONFIG_A0_A4 = 0x1, /*!< 8t8r FDRC A0 + A4*/ + ADI_APOLLO_RECONFIG_A1_A5 = 0x2, /*!< 8t8r FDRC A1 + A5*/ + ADI_APOLLO_RECONFIG_A2_A6 = 0x4, /*!< 8t8r FDRC A2 + A6*/ + ADI_APOLLO_RECONFIG_A3_A7 = 0x8, /*!< 8t8r FDRC A3 + A7*/ + ADI_APOLLO_RECONFIG_B0_B4 = 0x10, /*!< 8t8r FDRC B0 + B4*/ + ADI_APOLLO_RECONFIG_B1_B5 = 0x20, /*!< 8t8r FDRC B1 + B5*/ + ADI_APOLLO_RECONFIG_B2_B6 = 0x40, /*!< 8t8r FDRC B2 + B6*/ + ADI_APOLLO_RECONFIG_B3_B7 = 0x80, /*!< 8t8r FDRC B3 + B7*/ +} adi_apollo_reconfig_select_e; + +/*! + * \brief Enumerates the reconfig controller input counter types + */ +typedef enum { + ADI_APOLLO_RECONFIG_EXTERNAL = 0, /*!< External generated reconfig count (e.g. ext trig sync)*/ + ADI_APOLLO_RECONFIG_INTERNAL = 1, /*!< Internal generated reconfig count (e.g. time stamp) */ + ADI_APOLLO_RECONFIG_TYPE_NUM = 2 /*!< No. of types */ +} adi_apollo_reconfig_type_e; + + +/*! +* \brief RECONFIG CONTROL programming data +*/ +typedef struct { + uint8_t trig_reconfig_mode; /*!< Trigger based Reconfiguration Mode + 1=> choose internal triggers for reconfiguration after one sync event + 0=> Use external trigger (retimed to internal-sysref boundary) for resynchronization. >*/ + uint8_t cnco_reset; /*!< 1=>Reset CNCO with next sync/trigger. Design Needs a risedge on this bit to enable the CNCO reset if in Tzero coherence mode. 0 =>Do not reset CNCO >*/ + uint8_t timestamp_reset_en; /*!< 1=>Reset timestamp with next sync/trigger. Design Needs a risedge on this bit to enable the timestamp reset. 0 =>Do not reset timestamp >*/ + uint8_t resync_en; /*!< 1=> Forcefully enable resynchronization of all clocks at next sync/trigger(debug feature). 0 =>Resynchronization based on inputs >*/ + uint8_t tzero_coherence_en; /*!< 1=> Coherence w.r.t Time0 enabled. 0 => Coherence w.r.t immediately preceding trigger/sync >*/ + uint8_t fnco_reset_en; /*!< 1=>Reset FNCO with next sync/trigger if tzero_coherence_en is disabled. 0 =>Do not reset FNCO >*/ + uint16_t prefsrc_lcm; /*!< Decides the LCM value used in counter for PreFSRC Reconfiguration controller. This decides the time taken for reconfiguration, + but needs to be programmed according to the decimation/interpolation modes. >*/ + uint16_t postfsrc_lcm; /*!< Decides the LCM value used in counter for PostFSRC Reconfiguration controller. This decides the time taken for reconfiguration, + but needs to be programmed according to the decimation/interpolation modes. >*/ +} adi_apollo_reconfig_ctrl_pgm_t; + +#endif /* __ADI_APOLLO_RECONFIG_TYPES_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_rx.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_rx.h new file mode 100644 index 00000000000000..24c552da3f52d9 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_rx.h @@ -0,0 +1,152 @@ +/*! + * \brief RX top level API definition headers + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_RX + * @{ + */ +#ifndef __ADI_APOLLO_RX_H__ +#define __ADI_APOLLO_RX_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_rx_types.h" + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Configures RX data path blocks for device side + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] side Device side, A or B \ref adi_apollo_sides_e + * \param[in] config Configuration parameters. \ref adi_apollo_rxpath_t + * \param[in] jtx_config JESD JTx parameters for Rx data path. \ref adi_apollo_jesd_tx_cfg_t + * + * \return API_CMS_ERROR_OK Completed successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_rx_configure(adi_apollo_device_t *device, adi_apollo_sides_e side, adi_apollo_rxpath_t *config, adi_apollo_jesd_tx_cfg_t *jtx_config); + +/** + * \brief Configures RX coarse DDC + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] side Device side, A or B \ref adi_apollo_sides_e + * \param[in] idx Index of block to configure. \ref adi_apollo_cddc_idx_e + * \param[in] config Configuration parameters. \ref adi_apollo_cddc_cfg_t + * + * \return API_CMS_ERROR_OK Completed successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_rx_cddc_configure(adi_apollo_device_t *device, adi_apollo_sides_e side, adi_apollo_cddc_idx_e idx, adi_apollo_cddc_cfg_t *config); + +/** + * \brief Configures RX fine DDC + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] side Device side, A or B \ref adi_apollo_sides_e + * \param[in] idx Index of block to configure. \ref adi_apollo_fddc_idx_e + * \param[in] config Configuration parameters. \ref adi_apollo_fddc_cfg_t + * + * \return API_CMS_ERROR_OK Completed successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_rx_fddc_configure(adi_apollo_device_t *device, adi_apollo_sides_e side, adi_apollo_fddc_idx_e idx, adi_apollo_fddc_cfg_t *config); + +/** + * \brief Configures RX pfilt + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] side Device side, A or B \ref adi_apollo_sides_e + * \param[in] idx Index of block to configure. \ref adi_apollo_pfilt_idx_e + * \param[in] config Configuration parameters. \ref adi_apollo_pfilt_cfg_t + * + * \return API_CMS_ERROR_OK Completed successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_rx_pfilt_configure(adi_apollo_device_t *device, adi_apollo_sides_e side, adi_apollo_pfilt_idx_e idx, adi_apollo_pfilt_cfg_t *config); + +/** + * \brief Configures RX crossbars and low sample enable + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] side Device side, A or B \ref adi_apollo_sides_e + * \param[in] config Configuration parameters. \ref adi_apollo_rxpath_misc_t + * + * \return API_CMS_ERROR_OK Completed successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_rx_rxpath_misc_configure(adi_apollo_device_t *device, adi_apollo_sides_e side, adi_apollo_rxpath_misc_t *config); + +/** + * \brief configures rx cfir + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] side Device side, A or B \ref adi_apollo_sides_e + * \param[in] idx Index of block to configure. \ref adi_apollo_cfir_idx_e + * \param[in] config Configuration parameters. \ref adi_apollo_cfir_cfg_t + * + * \return API_CMS_ERROR_OK Completed successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_rx_cfir_configure(adi_apollo_device_t *device, adi_apollo_sides_e side, adi_apollo_cfir_idx_e idx, adi_apollo_cfir_cfg_t *config); + +/** + * \brief Configures RX fsrc + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] side Device side, A or B \ref adi_apollo_sides_e + * \param[in] idx Index of block to configure (0 or 1) + * \param[in] config Configuration parameters. \ref adi_apollo_fsrc_cfg_t + * + * \return API_CMS_ERROR_OK Completed successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_rx_fsrc_configure(adi_apollo_device_t *device, adi_apollo_sides_e side, uint8_t idx, adi_apollo_fsrc_cfg_t *config); + +/** + * \brief Configure DFORMAT parameters + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] side Target side \ref adi_apollo_sides_e + * \param[in] link_idx Link index. There 2 per side. + * \param[in] config Ptr to Dformat configuration. (1 per link) \ref adi_apollo_dformat_cfg_t + * \param[in] jtx_link_config Ptr to JTx link configuration (1 per link) \ref adi_apollo_jesd_tx_link_cfg_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_rx_dformat_configure(adi_apollo_device_t* device, adi_apollo_sides_e side, adi_apollo_jesd_links_e link_idx, + adi_apollo_dformat_cfg_t *config, adi_apollo_jesd_tx_link_cfg_t* jtx_link_config); + +/** + * \brief Configure SMON parameters + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] side Target side \ref adi_apollo_sides_e + * \param[in] idx Index of SMON block to configure. There 4 per side. \ref adi_apollo_smon_idx_e + * \param[in] config Configuration parameters. \ref adi_apollo_smon_cfg_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_rx_smon_configure(adi_apollo_device_t *device, adi_apollo_sides_e side, adi_apollo_smon_idx_e idx, + adi_apollo_smon_cfg_t *config); + +#ifndef CLIENT_IGNORE +#endif /* CLIENT_IGNORE*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_RX_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_rx_types.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_rx_types.h new file mode 100644 index 00000000000000..fb452b0eab77e7 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_rx_types.h @@ -0,0 +1,29 @@ +/*! + * \brief RX top level API type definition headers + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_RX + * @{ + */ +#ifndef __ADI_APOLLO_RX_TYPES_H__ +#define __ADI_APOLLO_RX_TYPES_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_cms_api_common.h" +#include "adi_apollo_common.h" +#include "apollo_cpu_device_profile_types.h" + +/*============= D E F I N E S ==============*/ + +/* Force idl-gen to pick up file */ +typedef uint8_t adi_apollo_rx_types_dummy; + +#endif /* __ADI_APOLLO_RX_TYPES_H__ */ + +/*! @} */ \ No newline at end of file diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_rxen.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_rxen.h new file mode 100644 index 00000000000000..f61ca3d7cac5de --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_rxen.h @@ -0,0 +1,152 @@ +/*! + * \brief RXEN Block definition headers + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_RXEN + * @{ + */ +#ifndef __ADI_APOLLO_RXEN_H__ +#define __ADI_APOLLO_RXEN_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_rxen_types.h" +#include "adi_apollo_private_blk_sel_types.h" + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Configure the entire rxen powerup control block. + * Generates enable signals for converters and digital blocks. + * + * \note Configures pwrup ctrl, edges, counters and pin sel. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] adcs ADC selections. \ref adi_apollo_rxen_adc_select_e + * \param[in] config Configuration parameters. \ref adi_apollo_rxen_pwrup_blk_config_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_rxen_pwrup_ctrl_config_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t adcs, const adi_apollo_rxen_pwrup_blk_config_t *config); + +/** + * \brief Configure rxen powerup control input selects. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] adcs ADC selections. \ref adi_apollo_rxen_adc_select_e + * \param[in] config Configuration parameters. \ref adi_apollo_rxen_pwrup_ctrl_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_rxen_pwrup_ctrl_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t adcs, const adi_apollo_rxen_pwrup_ctrl_t *config); + +/** + * \brief Configure rxen rise/fall control for adc, digital and pa. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] adcs ADC selections. \ref adi_apollo_rxen_adc_select_e + * \param[in] config Configuration parameters. \ref adi_apollo_rxen_pwrup_ctrl_edge_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_rxen_pwrup_ctrl_edge_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t adcs, const adi_apollo_rxen_pwrup_ctrl_edge_t *config); + +/** + * \brief Configure rxen powerup control counters for sequencing + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] adcs ADC selections. \ref adi_apollo_rxen_adc_select_e + * \param[in] config Configuration parameters. \ref adi_apollo_rxen_pwrup_ctrl_count_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_rxen_pwrup_ctrl_count_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t adcs, const adi_apollo_rxen_pwrup_ctrl_count_t *config); + +/** + * \brief Configure rxen powerup ctrl enable pin selects + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] adcs ADC selections. \ref adi_apollo_rxen_adc_select_e + * \param[in] pin Enable pin select. \ref adi_apollo_puc_en_pin_sel_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_rxen_pwrup_ctrl_pin_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t adcs, adi_apollo_puc_en_pin_sel_e pin); + +/** + * \brief Set rxen powerup control spi enable + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] adcs ADC selections. \ref adi_apollo_rxen_adc_select_e + * \param[in] spi_en 0 = disable, 1 = enable + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_rxen_pwrup_ctrl_spien_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t adcs, uint8_t spi_en); + +/** + * \brief Configures digital blocks to enable/disable from powerup controller + * + * Uses dig_en outputs from the power control block to + * enable selected digital blocks. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] dig_enables Dig enable selections from pwrup ctrl + * \param[in] config Configuration parameters. \ref adi_apollo_rxen_blk_config_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_rxen_config_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t dig_enables, const adi_apollo_rxen_blk_config_t *config); + +/** + * \brief Selects spi or digital input to control which blocks are controlled by rxen + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] dig_enables Dig enable selections from pwrup ctrl + * \param[in] config Configuration parameters. \ref adi_apollo_rxen_ctrl_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_rxen_ctrl_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t dig_enables, const adi_apollo_rxen_ctrl_t *config); + +/** + * \brief Sets respective rxen enable via spi control + * + * \note This function is only applicable when spien_en is set. \ref adi_apollo_rxen_ctrl_t + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] dig_enables dig enable selections from pwrup ctrl + * \param[in] spi_en Sets hi/lo the respective enable via spi. + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_rxen_spien_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t dig_enables, uint8_t spi_en); + + +#ifndef CLIENT_IGNORE + +#endif /* CLIENT_IGNORE*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_RXEN_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_rxen_types.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_rxen_types.h new file mode 100644 index 00000000000000..b8cf7d199a20df --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_rxen_types.h @@ -0,0 +1,140 @@ +/*! + * \brief RXEN Block definition type headers + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_RXEN + * @{ + */ +#ifndef __ADI_APOLLO_RXEN_TYPES_H__ +#define __ADI_APOLLO_RXEN_TYPES_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_cms_api_common.h" +#include "adi_apollo_common.h" + +/*============= D E F I N E S ==============*/ +#define ADI_APOLLO_DIG_EN_NUM 8 /* Num of dig enables from TX/RX enable pwr control */ +#define ADI_APOLLO_DIG_EN_PER_SIDE_NUM 4 /* Num of dig enables from TX/RX enable pwr control per side */ + +/*! + * \brief Enumerates ADC Select + */ +typedef enum { + ADI_APOLLO_RXEN_ADC_NONE = 0x0, /*!< No ADC */ + ADI_APOLLO_RXEN_ADC_A0 = 0x1, /*!< ADC0 of side A */ + ADI_APOLLO_RXEN_ADC_A1 = 0x2, /*!< ADC1 of side A */ + ADI_APOLLO_RXEN_ADC_A2 = 0x4, /*!< ADC2 of side A */ + ADI_APOLLO_RXEN_ADC_A3 = 0x8, /*!< ADC3 of side A */ + ADI_APOLLO_RXEN_ADC_B0 = 0x10, /*!< ADC0 of side B */ + ADI_APOLLO_RXEN_ADC_B1 = 0x20, /*!< ADC1 of side B */ + ADI_APOLLO_RXEN_ADC_B2 = 0x40, /*!< ADC2 of side B */ + ADI_APOLLO_RXEN_ADC_B3 = 0x80, /*!< ADC3 of side B */ + ADI_APOLLO_RXEN_ADC_ALL = 0xFF /*!< ALL ADCs */ +} adi_apollo_rxen_adc_select_e; + +/*! +* \brief Dig enable select from powerup control block +*/ +typedef enum { + ADI_APOLLO_RXEN_EN_NONE = 0, /*!< No dig enable pins */ + ADI_APOLLO_RXEN_EN_A0 = 0x01, /*!< Digital enable A0 from pwr control input */ + ADI_APOLLO_RXEN_EN_A1 = 0x02, /*!< Digital enable A1 from pwr control input */ + ADI_APOLLO_RXEN_EN_A2 = 0x04, /*!< Digital enable A2 from pwr control input */ + ADI_APOLLO_RXEN_EN_A3 = 0x08, /*!< Digital enable A3 from pwr control input */ + ADI_APOLLO_RXEN_EN_B0 = 0x10, /*!< Digital enable B0 from pwr control input */ + ADI_APOLLO_RXEN_EN_B1 = 0x20, /*!< Digital enable B1 from pwr control input */ + ADI_APOLLO_RXEN_EN_B2 = 0x40, /*!< Digital enable B2 from pwr control input */ + ADI_APOLLO_RXEN_EN_B3 = 0x80, /*!< Digital enable B3 from pwr control input */ + ADI_APOLLO_RXEN_EN_ALL = 0xFF, /*!< All dig enable pins */ +} adi_apollo_rxen_en_select_e; + +/*! +* \brief Dig enable from powerup is active polarity select +*/ +typedef enum { + ADI_APOLLO_DIG_EN_ACTIVE_HIGH = 0, /*!< Polarity of respective dig en is active high */ + ADI_APOLLO_DIG_EN_ACTIVE_LOW = 1, /*!< Polarity of respective dig en is active low */ +} adi_apollo_rxen_en_polarity_e; + + +/*! +* \brief RxEN powerup control SPI +*/ +typedef struct { + uint8_t sm_en; /*!< 0: State machine bypassed. (dac_stdby, dig_en and pa_en follow RxEN), 1: Edge control state machine enabled. */ + uint8_t spi_rxen_en; /*!< 0: Use the RxEN input signal, 1: Ignore RxEN input signal and use input from SPI control */ + uint8_t spi_rxen; /*!< 0: Rx blocks gated off/standby, 1: RX blocks are enabled (spi_rxen_en must be enabled to use this control) */ + adi_apollo_puc_clk_rate_sel_e sm_clk_rate; /*!< Select clock rate of state machine counters. */ +} adi_apollo_rxen_pwrup_ctrl_t; + +/*! +* \brief RxEN powerup control edges +*/ +typedef struct { + adi_apollo_puc_edge_rise_sel_e adc_rise; /*!< adc enable to rise after RxEN rise. (\ref adi_apollo_puc_edge_rise_sel_e) */ + adi_apollo_puc_edge_fall_sel_e adc_fall; /*!< adc enable to fall after RxEN fall. (\ref adi_apollo_puc_edge_fall_sel_e) */ + adi_apollo_puc_edge_rise_sel_e dig_rise; /*!< dig block enable to rise after RxEN rise. (\ref adi_apollo_puc_edge_rise_sel_e) */ + adi_apollo_puc_edge_fall_sel_e dig_fall; /*!< dig block enable to fall after RxEN fall. (\ref adi_apollo_puc_edge_fall_sel_e) */ + adi_apollo_puc_edge_rise_sel_e pa_rise; /*!< PA enable to rise after RxEN rise. (\ref adi_apollo_puc_edge_rise_sel_e) */ + adi_apollo_puc_edge_fall_sel_e pa_fall; /*!< PA enable to fall after RxEN fall. (\ref adi_apollo_puc_edge_fall_sel_e) */ +} adi_apollo_rxen_pwrup_ctrl_edge_t; + +/*! +* \brief RxEN powerup control counters +*/ +typedef struct { + uint8_t count_maxa; /*!< Maximum programmed counter value from E0 to E1 (Fs/32 per count) */ + uint8_t count_maxb; /*!< Maximum programmed counter value from E1 to E2 (Fs/32 per count) */ + uint8_t count_maxc; /*!< Maximum programmed counter value from E2 to E3 (Fs/32 per count) */ + uint8_t count_maxd; /*!< Maximum programmed counter value from E4 to E5 (Fs/32 per count) */ + uint8_t count_maxe; /*!< Maximum programmed counter value from E5 to E6 (Fs/32 per count) */ + uint8_t count_maxf; /*!< Maximum programmed counter value from E6 to E7 (Fs/32 per count) */ +} adi_apollo_rxen_pwrup_ctrl_count_t; + +/*! +* \brief RxEN powerup control block configuration +*/ +typedef struct { + adi_apollo_rxen_pwrup_ctrl_t ctrl; + adi_apollo_rxen_pwrup_ctrl_edge_t edge; + adi_apollo_rxen_pwrup_ctrl_count_t count; + adi_apollo_puc_en_pin_sel_e pin_en; /*!< Select which enable pin is mapped to the pwrup control. */ +} adi_apollo_rxen_pwrup_blk_config_t; + +/*! +* \brief RxEN control SPI +*/ +typedef struct { + adi_apollo_rxen_en_polarity_e enable_polarity; /*!< Enable input polarity */ + uint8_t spien_en; /*!< 0: Use the dig input signal, 1: Ignore input signal and use SPI control */ + uint8_t spi_en; /*!< SPI Enable/Disable. Applicable when spien_en set true */ +} adi_apollo_rxen_ctrl_t; + +typedef struct { + adi_apollo_rxen_en_polarity_e enable_polarity; + uint8_t spi_en; + uint8_t spien_en; + uint16_t slice_sel; + uint8_t linx_sel; + uint16_t pfilt_sel; + uint16_t cddc_sel; + uint16_t fddc_sel; + uint8_t cfir_sel; + uint8_t fsrc_sel; + uint16_t jtx_link_sel; + uint16_t jtx_phy_sel_side_a; /*!< JTX phy lane bit-wise select side a */ + uint16_t jtx_phy_sel_side_b; /*!< JTX phy lane bit-wise select side b */ + uint8_t modsw_sel; + uint8_t invsinc_sel; + uint8_t gain_sel; + uint8_t srd_sel; +} adi_apollo_rxen_blk_config_t; + +#endif /* __ADI_APOLLO_RXEN_TYPES_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_rxmisc.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_rxmisc.h new file mode 100644 index 00000000000000..42c98a1935d72d --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_rxmisc.h @@ -0,0 +1,70 @@ +/*! + * \brief Rx Misc functional block API prototypes + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_RXMISC + * @{ + */ +#ifndef __ADI_APOLLO_RXMISC_H__ +#define __ADI_APOLLO_RXMISC_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_rxmisc_types.h" + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Sets low sampling rx mode + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] side_sel Target side \ref adi_apollo_side_select_e + * \param[in] low_samp_en 1: low sampling enabled 0: low sampling disabled + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_rxmisc_low_samp_set(adi_apollo_device_t *device, adi_apollo_side_select_e side_sel, uint8_t low_samp_en); + +/** + * \brief Configure RX MISC parameters + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] side_sel Target side \ref adi_apollo_side_select_e + * \param[in] config \ref adi_apollo_rx_misc_pgm_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_rxmisc_pgm(adi_apollo_device_t *device, adi_apollo_side_select_e side_sel, adi_apollo_rx_misc_pgm_t *config); + +/** + * \brief Rx datapath (DP) reset. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] side_sel Target side \ref adi_apollo_side_select_e + * \param[in] reset_en 0: clears the datapath reset. 1: set DP reset + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_rxmisc_dp_reset(adi_apollo_device_t *device, adi_apollo_side_select_e side_sel, uint8_t reset_en); + +#ifndef CLIENT_IGNORE + +#endif /* CLIENT_IGNORE*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_RXMISC_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_rxmisc_types.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_rxmisc_types.h new file mode 100644 index 00000000000000..6282f13a89c515 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_rxmisc_types.h @@ -0,0 +1,41 @@ +/*! + * \brief Rx Misc functional block definitions + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_RXMISC + * @{ + */ +#ifndef __ADI_APOLLO_RXMISC_TYPES_H__ +#define __ADI_APOLLO_RXMISC_TYPES_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_cms_api_common.h" +#include "adi_apollo_common.h" + +/*============= D E F I N E S ==============*/ + +/*! +* \brief Enumerates RX DATAPATH CLK selection +*/ +typedef enum { + ADI_APOLLO_DATAPATH_CLK_DISABLE = 0x0, /*!< Disable the datapath clocks */ + ADI_APOLLO_DATAPATH_CLK_ENABLE_INPHASE = 0x1, /*!< Enables the I datapath clocks */ + ADI_APOLLO_DATAPATH_CLK_ENABLE_QPHASE = 0x2, /*!< Enables the Q datapath clocks */ +} adi_apollo_datapath_clk_e; + +/*! +* \brief RX MISC programming data +*/ +typedef struct { + uint8_t datapath_clk; /*!< \ref adi_apollo_datapath_clk_e */ + uint8_t low_samp_en; /*!< 1: the lower sample case is enabled, 0: Disabled */ +} adi_apollo_rx_misc_pgm_t; + +#endif /* __ADI_APOLLO_RXMISC_TYPES_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_rxmux.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_rxmux.h new file mode 100644 index 00000000000000..de24ed110ee1bc --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_rxmux.h @@ -0,0 +1,75 @@ +/*! + * \brief Rx Crossbar Mux functional block API prototypes + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_RXMUX + * @{ + */ +#ifndef __ADI_APOLLO_RXMUX_H__ +#define __ADI_APOLLO_RXMUX_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_rxmux_types.h" + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Configure the ADC crossbar mux1 + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] side_sel Target bit-wise side select \ref adi_apollo_side_select_e + * \param[in] cbout_from_adc_sel Array of cross bar outputs from ADC selects. \ref adi_apollo_rx_mux0_sel_e + * \param[in] length Length of cbout_from_adc_sel array param. (2 for 4T4R, 4 for 8T8R devices) + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_rxmux_xbar1_set(adi_apollo_device_t *device, adi_apollo_side_select_e side_sel, + adi_apollo_rx_mux0_sel_e cbout_from_adc_sel[], uint32_t length); + +/** + * \brief Configure the Rx CDDC-to-FDDC crossbar + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] side_sel Target bit-wise side select \ref adi_apollo_side_select_e + * \param[in] coarse_to_fine_xbar_sel Array of CDDC to FDDC configurations \ref adi_apollo_rx_mux2_sel_e + * \param[in] length Length of coarse_to_fine_xbar_sel array param. Must be set to ADI_APOLLO_RX_MUX2_NUM + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_rxmux_xbar2_set(adi_apollo_device_t *device, adi_apollo_side_select_e side_sel, adi_apollo_rx_mux2_sel_e coarse_to_fine_xbar_sel[], uint32_t length); + +/** + * \brief Configure the Rx sample crossbar + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] link_sel Target bit-wise link select \ref adi_apollo_jesd_link_select_e + * \param[in] sample_offset Value at which to start programming the xbar + * \param[in] sample_sel Sample select xbar values \ref adi_apollo_rxmux_sample_sel_e + * \param[in] length Number of sbar values to program + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_rxmux_sample_xbar_set(adi_apollo_device_t *device, uint16_t link_sel, uint8_t sample_offset, adi_apollo_rxmux_sample_sel_e sample_sel[], uint32_t length); + +#ifndef CLIENT_IGNORE + +#endif /* CLIENT_IGNORE*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_RXMUX_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_rxmux_types.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_rxmux_types.h new file mode 100644 index 00000000000000..87e419389e3121 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_rxmux_types.h @@ -0,0 +1,60 @@ +/*! + * \brief Rx Crossbar Mux functional block definitions + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_RXMUX + * @{ + */ +#ifndef __ADI_APOLLO_RXMUX_TYPES_H__ +#define __ADI_APOLLO_RXMUX_TYPES_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_cms_api_common.h" +#include "adi_apollo_common.h" + +/*============= D E F I N E S ==============*/ +#define ADI_APOLLO_ADC_MUX_NUM 8 +#define ADI_APOLLO_ADC_MUX_PER_SIDE 4 +#define ADI_APOLLO_ADC_PER_MUX 4 + + +/*! +* \brief Enumerates Rx Sample Xbar select +*/ +typedef enum { + ADI_APOLLO_RXMUX_SAMPLE_FINE0_I = 0u, + ADI_APOLLO_RXMUX_SAMPLE_FINE0_Q = 1u, + ADI_APOLLO_RXMUX_SAMPLE_FINE1_I = 2u, + ADI_APOLLO_RXMUX_SAMPLE_FINE1_Q = 3u, + ADI_APOLLO_RXMUX_SAMPLE_FINE2_I = 4u, + ADI_APOLLO_RXMUX_SAMPLE_FINE2_Q = 5u, + ADI_APOLLO_RXMUX_SAMPLE_FINE3_I = 6u, + ADI_APOLLO_RXMUX_SAMPLE_FINE3_Q = 7u, + ADI_APOLLO_RXMUX_SAMPLE_FINE4_I = 8u, + ADI_APOLLO_RXMUX_SAMPLE_FINE4_Q = 9u, + ADI_APOLLO_RXMUX_SAMPLE_FINE5_I = 10u, + ADI_APOLLO_RXMUX_SAMPLE_FINE5_Q = 11u, + ADI_APOLLO_RXMUX_SAMPLE_FINE6_I = 12u, + ADI_APOLLO_RXMUX_SAMPLE_FINE6_Q = 13u, + ADI_APOLLO_RXMUX_SAMPLE_FINE7_I = 14u, + ADI_APOLLO_RXMUX_SAMPLE_FINE7_Q = 15u, +} adi_apollo_rxmux_sample_sel_e; + +/*! +* \brief Enumerates Rx Mux1 crossbar outputs (CBOUT). ADC inputs are routed to CBOUTx +*/ +typedef enum { + ADI_APOLLO_RXMUX_CBOUT_0 = 0u, /*!< Rx Mux1 CBOUT-0 output */ + ADI_APOLLO_RXMUX_CBOUT_1 = 1u, /*!< Rx Mux1 CBOUT-1 output */ + ADI_APOLLO_RXMUX_CBOUT_2 = 2u, /*!< Rx Mux1 CBOUT-2 output */ + ADI_APOLLO_RXMUX_CBOUT_3 = 3u /*!< Rx Mux1 CBOUT-3 output */ +} adi_apollo_rxmux_cbout_sel_e; + +#endif /* __ADI_APOLLO_RXMUX_TYPES_H__ */ +/*! @} */ \ No newline at end of file diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_serdes.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_serdes.h new file mode 100644 index 00000000000000..47813d4a420e08 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_serdes.h @@ -0,0 +1,320 @@ +/*! + * \brief SerDes related definition headers + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_SERDES + * @{ + */ +#ifndef __ADI_APOLLO_SERDES_H__ +#define __ADI_APOLLO_SERDES_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_serdes_types.h" +#include "adi_apollo_cfg_types.h" + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Execute an Apollo JRx serdes init (foreground) calibration + * \note FPGA must be transmitting data for SERDES cal to function successfully. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_serdes_jrx_cal(adi_apollo_device_t* device); + +/** + * \brief Execute an Apollo JRx serdes init (foreground) calibration with config option. + * \note FPGA must be transmitting data for SERDES cal to function successfully. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] serdes Serdes selection mask \ref adi_apollo_serdes_12pack_select_e + * \param[in] init_cal_cfg Initial cal configuration. Specify init defaults, NVM or user defined. \ref adi_apollo_init_cal_cfg_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_serdes_jrx_init_cal(adi_apollo_device_t* device, uint16_t serdes, adi_apollo_init_cal_cfg_e init_cal_cfg); + +/** + * \brief Freeze (Halt) the Apollo JRx serdes background calibration + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] serdes Serdes selection mask \ref adi_apollo_serdes_12pack_select_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_serdes_jrx_bgcal_freeze(adi_apollo_device_t* device, uint16_t serdes); + +/** + * \brief Unfreeze (Start/Restarts) the Apollo JRx serdes background calibration + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] serdes Serdes selection mask \ref adi_apollo_serdes_12pack_select_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_serdes_jrx_bgcal_unfreeze(adi_apollo_device_t* device, uint16_t serdes); + +/** + * \brief Get SERDES JRx background calibration state + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] serdes Serdes selection mask \ref adi_apollo_serdes_12pack_select_e + * \param[out] state Array of \ref adi_apollo_serdes_bgcal_state_t structs containing per SERDES PACK bgcal error and state info + * Array/Serdes_Pack indexes : 0: SERDES_12PACK_A, 1: SERDES_12PACK_B + * \param[in] len Length of state array (should be 2) + * + * Common Serdes bgcal states: + * 0x1A = > APOLLO_SERDES_BGCAL_STATE_RESUMED | APOLLO_SERDES_BGCAL_STATE_RUNNING | APOLLO_SERDES_BGCAL_STATE_ENABLED + * 0x25 = > APOLLO_SERDES_BGCAL_STATE_SUSPENDED | APOLLO_SERDES_BGCAL_STATE_INACTIVE | APOLLO_SERDES_BGCAL_STATE_DISABLED + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. +*/ +int32_t adi_apollo_serdes_jrx_bgcal_state_get(adi_apollo_device_t *device, uint16_t serdes, adi_apollo_serdes_bgcal_state_t state[], uint32_t len); + +/** + * \brief Configures the tx serdes pll + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] config Serdes pll configuration parameters. \ref adi_apollo_serdes_pll_pgm_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_serdes_pll_config(adi_apollo_device_t *device, adi_apollo_serdes_pll_pgm_t *config); + +/** + * \brief Power up/down the serdes pll + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] pwr_up Power up or down \ref adi_apollo_serdes_pll_power_up_down_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_serdes_pll_power(adi_apollo_device_t *device, adi_apollo_serdes_pll_power_up_down_e pwr_up); + +/** + * \brief Serdes PLL reset + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] reset_type Type of serdes reset. \ref adi_apollo_serdes_pll_reset_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_serdes_pll_reset(adi_apollo_device_t *device, adi_apollo_serdes_pll_reset_e reset_type); + +/** + * \brief Configures the tx serializer + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] sides Serializer select. There is on per side. + * \param[in] config Serializer configuration parameters. \ref adi_apollo_serializer_pgm_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_serdes_serializer_config(adi_apollo_device_t *device, const uint16_t sides, adi_apollo_serializer_pgm_t *config); + +/** + * \brief Configures the PRBS Generator + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] lanes Array containing lanes for PRBS testing + * \param[in] lanes_len Length of lanes array + * \param[in] config \ref adi_apollo_serdes_prbs_generator_enable_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_serdes_prbs_generator_enable(adi_apollo_device_t *device, + uint8_t lanes[], uint32_t lanes_len, + adi_apollo_serdes_prbs_generator_enable_t *config); + +/** + * \brief Configures the JRx PRBS Checker + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] lanes Array containing lanes for PRBS testing + * \param[in] lanes_len Length of lanes array + * \param[in] config The PRBS configuration to apply to lanes requested \ref adi_apollo_serdes_prbs_checker_enable_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_serdes_jrx_prbs_checker_enable(adi_apollo_device_t *device, + uint8_t lanes[], uint32_t lanes_len, + adi_apollo_serdes_prbs_checker_enable_t *config); + +/** + * \brief Reads the PRBS Checker status + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] lanes Array containing lanes for PRBS testing + * \param[in] status Array of lane status result structs, one for lane \ref adi_apollo_serdes_prbs_checker_status_t + * \param[in] lanes_len Length of lanes and status arrays + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_serdes_jrx_prbs_checker_status(adi_apollo_device_t *device, + uint8_t lanes[], + adi_apollo_serdes_prbs_checker_status_t status[], + uint32_t lanes_len); + +/** + * \brief Apply the JRx SPO clock strobe + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] lanes Array containing lanes for PRBS testing + * \param[in] lanes_len Length of lanes array + * \param[in] spo_strobe Apply strobe to lanes requested \ref adi_apollo_serdes_ck_spo_strobe_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_serdes_jrx_clock_strobe(adi_apollo_device_t *device, + uint8_t lanes[], uint32_t lanes_len, + adi_apollo_serdes_ck_spo_strobe_e spo_strobe); + +/** + * \brief Set the JRx DFE flash mask + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] lanes Array containing lanes for PRBS testing + * \param[in] lanes_len Length of lanes array + * \param[in] flash_mask Digital counting of flash outputs toward DLL phase accumulator. 4-bit value. + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_serdes_jrx_set_flash_mask(adi_apollo_device_t *device, + uint8_t lanes[], uint32_t lanes_len, uint8_t flash_mask); + +/** + * \brief Set the JRx SPO direction + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] lanes Array containing lanes for PRBS testing + * \param[in] lanes_len Length of lanes array + * \param[in] dir SPO direction. 1=UP, 0=DOWN + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_serdes_jrx_spo_dir_set(adi_apollo_device_t *device, + uint8_t lanes[], uint32_t lanes_len, uint8_t dir); + +/** + * \brief Clear the PRBS error count + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] lanes Array containing lanes for PRBS testing + * \param[in] lanes_len Length of lanes array + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_serdes_jrx_prbs_clear_error(adi_apollo_device_t *device, + uint8_t lanes[], uint32_t lanes_len); + +/** + * \brief Perform a Horizontal Eye Sweep for select JRx Serdes lane. + * \note Only 1 lane selection per call. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] lane Target Serdes Lane. \ref adi_apollo_mailbox_serdes_lane_num_e + * \param[in] prbs_pattern PRBS Pattern being used. \ref adi_apollo_serdes_jrx_prbs_mode_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_serdes_jrx_horiz_eye_sweep(adi_apollo_device_t *device, + const uint16_t lane, + const uint8_t prbs_pattern); + +/** + * \brief Get Response of a Horizontal Eye Monitor Test for select JRx serdes lane. + * \note Only 1 lane selection per call. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] lane Target Serdes Lane. \ref adi_apollo_mailbox_serdes_lane_num_e + * \param[out] resp Response of a Horizontal Eye Monitor Test. See \ref adi_apollo_serdes_jrx_horiz_eye_resp_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_serdes_jrx_horiz_eye_sweep_resp_get(adi_apollo_device_t *device, + const uint16_t lane, + adi_apollo_serdes_jrx_horiz_eye_resp_t *resp); + +/** + * \brief Perform a Vertical Eye Sweep for select JRx Serdes lane. + * \note Only 1 lane selection per call. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] lane Target Serdes Lane. \ref adi_apollo_mailbox_serdes_lane_num_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_serdes_jrx_vert_eye_sweep(adi_apollo_device_t *device, + const uint16_t lane); + +/** + * \brief Get Response of a Vertical Eye Monitor Test for select JRx serdes lane. + * \note Only 1 lane selection per call. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] lane Target Serdes Lane. \ref adi_apollo_mailbox_serdes_lane_num_e + * \param[out] resp Response of a Vertical Eye Monitor Test. See \ref adi_apollo_serdes_jrx_vert_eye_resp_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_serdes_jrx_vert_eye_sweep_resp_get(adi_apollo_device_t *device, + const uint16_t lane, + adi_apollo_serdes_jrx_vert_eye_resp_t *resp); + +/** + * \brief Reads serdes PLL lock status + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] side_index Apollo side index \ref adi_apollo_sides_e + * \param[in] lane_mask Lane mask to read the status + * \param[out] status PLL lock status + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_serdes_pll_locked_status(adi_apollo_device_t *device, + adi_apollo_sides_e side_index, + uint16_t lane_mask, + uint16_t *status); + +#ifndef CLIENT_IGNORE + +#endif /* CLIENT_IGNORE*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_SERDES_H__ */ +/*! @} */ \ No newline at end of file diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_serdes_types.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_serdes_types.h new file mode 100644 index 00000000000000..6d5f3c645b2460 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_serdes_types.h @@ -0,0 +1,195 @@ +/*! + * \brief SerDes Block definition headers + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_SERDES + * @{ + */ +#ifndef __ADI_APOLLO_SERDES_TYPES_H__ +#define __ADI_APOLLO_SERDES_TYPES_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_cms_api_common.h" +#include "adi_apollo_common.h" +#include "adi_apollo_mailbox_types.h" + +/*============= D E F I N E S ==============*/ + +#define ADI_APOLLO_SERDES_JRX_VERT_EYE_TEST_RESP_BUF_SIZE (66U) + +/*! +* \brief Enumerates the serdes pll powerup selection +*/ +typedef enum { + ADI_APOLLO_SERDES_PLL_POWER_DOWN = 0, /*!< Power down the PLL */ + ADI_APOLLO_SERDES_PLL_POWER_UP = 1, /*!< Power up the PLL */ +} adi_apollo_serdes_pll_power_up_down_e; + +/*! +* \brief Enumerates the serdes pll reset selection +*/ +typedef enum { + ADI_APOLLO_SERDES_PLL_RESET_SYNTH = 0, /*!< Synth reset */ + ADI_APOLLO_SERDES_PLL_RESET_ODIV = 1, /*!< Output divider reset */ + ADI_APOLLO_SERDES_PLL_RESET_NUM = 2 /*!< Number of serdes reset types */ +} adi_apollo_serdes_pll_reset_e; + +/*! +* \brief Enumerates the serdes tx clock divider +*/ +typedef enum { + ADI_APOLLO_SERDES_JTX_CLOCK_DIV_1 = 0, /*!< tx serial clk div 1 */ + ADI_APOLLO_SERDES_JTX_CLOCK_DIV_2 = 1, /*!< tx serial clk div 2 */ + ADI_APOLLO_SERDES_JTX_CLOCK_DIV_4 = 2, /*!< tx serial clk div 3 */ + ADI_APOLLO_SERDES_JTX_CLOCK_DIV_PD = 3, /*!< tx serial clk div powerdown */ +} adi_apollo_serdes_tx_clock_div_e; + +/*! +* \brief Enumerates the serdes tx parallel data width +*/ +typedef enum { + ADI_APOLLO_SERDES_JTX_DATA_WIDTH_66 = 1, /*!< Parallel data width 66 (JESD204C) */ + ADI_APOLLO_SERDES_JTX_DATA_WIDTH_40 = 2, /*!< Parallel data width 40 (JESD204B) */ +} adi_apollo_serdes_tx_data_width_e; + + +/*! +* \brief Enumerates the JRx serdes PRBS pattern mode +*/ +typedef enum { + ADI_APOLLO_SERDES_JRX_PRBS7 = 0, /*!< PRBS7 serdes test pattern */ + ADI_APOLLO_SERDES_JRX_PRBS9 = 1, /*!< PRBS9 serdes test pattern */ + ADI_APOLLO_SERDES_JRX_PRBS15 = 2, /*!< PRBS15 serdes test pattern */ + ADI_APOLLO_SERDES_JRX_PRBS31 = 3 /*!< PRBS31 serdes test pattern */ +} adi_apollo_serdes_jrx_prbs_mode_e; + +/*! +* \brief Enumerates JTx serdes data and prbs test patterns +*/ +typedef enum { + ADI_APOLLO_SERDES_JTX_DATA_00 = 0, /*!< 0x00 serdes test pattern */ + ADI_APOLLO_SERDES_JTX_DATA_FF = 1, /*!< 0xFF serdes test pattern */ + ADI_APOLLO_SERDES_JTX_DATA_AA = 2, /*!< 0xAA serdes test pattern */ + ADI_APOLLO_SERDES_JTX_DATA_55 = 3, /*!< 0x55 serdes test pattern */ + ADI_APOLLO_SERDES_JTX_DATA_CC = 4, /*!< 0xCC serdes test pattern */ + ADI_APOLLO_SERDES_JTX_DATA_33 = 5, /*!< 0x33 serdes test pattern */ + ADI_APOLLO_SERDES_JTX_DATA_F0 = 6, /*!< 0xF0 serdes test pattern */ + ADI_APOLLO_SERDES_JTX_DATA_0F = 7, /*!< 0x0F serdes test pattern */ + ADI_APOLLO_SERDES_JTX_PRBS7 = 8, /*!< PRBS7 serdes test pattern */ + ADI_APOLLO_SERDES_JTX_PRBS9 = 9, /*!< PRBS9 serdes test pattern */ + ADI_APOLLO_SERDES_JTX_PRBS15 = 10, /*!< PRBS15 serdes test pattern */ + ADI_APOLLO_SERDES_JTX_PRBS31 = 11, /*!< PRBS31 serdes test pattern */ + ADI_APOLLO_SERDES_JTX_DATA_FF00 = 12, /*!< 0xFF00 serdes test pattern */ + ADI_APOLLO_SERDES_JTX_DATA_00FF = 13, /*!< 0x00FF serdes test pattern */ +} adi_apollo_serdes_jtx_prbs_mode_e; + +/*! +* \brief Enumerates CK SPO strobe +*/ +typedef enum { + ADI_APOLLO_SERDES_CK_SPO_STROBE_NONE = 0, + ADI_APOLLO_SERDES_CK_SPO_ISTROBE = 1, + ADI_APOLLO_SERDES_CK_SPO_QSTROBE = 2, +} adi_apollo_serdes_ck_spo_strobe_e; + +/*! +* \brief Enumerates current state of SERDES Tracking / BG Calibration +*/ +typedef enum { + ADI_APOLLO_SERDES_BGCAL_STATE_SUSPENDED = APOLLO_CALFRMWRK_STATE_SUSPENDED, /*!< code: 0x01 Cal's timer is not running */ + ADI_APOLLO_SERDES_BGCAL_STATE_RESUMED = APOLLO_CALFRMWRK_STATE_RESUMED, /*!< code: 0x02 Cal's timer is running */ + ADI_APOLLO_SERDES_BGCAL_STATE_INACTIVE = APOLLO_CALFRMWRK_STATE_INACTIVE, /*!< code: 0x04 Cal's Main function is not executing */ + ADI_APOLLO_SERDES_BGCAL_STATE_RUNNING = APOLLO_CALFRMWRK_STATE_RUNNING, /*!< code: 0x08 Cal's Main function is executing */ + ADI_APOLLO_SERDES_BGCAL_STATE_ENABLED = APOLLO_CALFRMWRK_STATE_ENABLED, /*!< code: 0x10 Cal is enabled back from the host */ + ADI_APOLLO_SERDES_BGCAL_STATE_DISABLED = APOLLO_CALFRMWRK_STATE_DISABLED, /*!< code: 0x20 Cal is disabled from the host */ + ADI_APOLLO_SERDES_BGCAL_STATE_ERROR = APOLLO_CALFRMWRK_STATE_ERROR, /*!< code: 0x40 Cal is errored out */ + ADI_APOLLO_SERDES_BGCAL_STATE_UNKNOWN = 0xFFFF +} adi_apollo_serdes_bgcal_state_e; + +/*! +* \brief SERDES Tracking / BG Cal error and status struct +*/ +typedef struct { + uint32_t state_valid; /* 1 = bgcal_error and bgcal_state fields have valid values, 0 = state unknown */ + uint32_t bgcal_error; /* 0 = no error */ + uint32_t bgcal_state; /* cal state bits \ref adi_apollo_serdes_bgcal_state_e */ +} adi_apollo_serdes_bgcal_state_t; + +/*! +* \brief SerDes Pll configuration struct +*/ +typedef struct { + uint16_t sdm_int; /*!< Feedback divider (N) */ + uint8_t ref_clk_byte0; /*!< Ref clock divider (1..63) (R) */ + uint8_t serdes_pll_odiv; /*!< /33 feedback clock divider (for async mode) */ + uint8_t root_clkdiv_fund; /*!< /33 low or high range divider (for async mode) */ + uint8_t root_clkdiv_div2; /*!< /33 post /1 or /2 */ + uint8_t vco_sel; /*!< Vco sel */ +} adi_apollo_serdes_pll_pgm_t; + +/*! +* \brief Serializer configuration struct +*/ +typedef struct { + uint8_t tx_clock_div; /*!< Serdes tx data width. \ref adi_apollo_serdes_tx_clock_div_e */ + uint8_t tx_data_width; /*!< Serdes tx data width. \ref adi_apollo_serdes_tx_data_width_e */ + uint8_t pd_ser; /*!< 1 = powerdown serialize. 0 = normal */ + uint8_t jesd_ver; /*!< JESD204 version. 0 = 204B, 1 = 204C */ +} adi_apollo_serializer_pgm_t; + +/*! +* \brief PRBS Generator (JTx) configuration struct +*/ +typedef struct { + uint8_t enable; /*!< 1 = Enable. 0 = Disable */ + uint8_t mode; /*!< PRBS and data test pattern. \ref adi_apollo_serdes_jtx_prbs_mode_e */ +} adi_apollo_serdes_prbs_generator_enable_t; + +/*! +* \brief JRx PRBS checker configuration struct +*/ +typedef struct { + uint8_t enable; /*!< In regular mode 1 = Enable. 0 = Disable */ + uint8_t auto_mode; /*!< 1 = auto mode. 0 = regular mode */ + uint8_t auto_mode_thres; /*!< How many words of data to check threshold - in 2^. 6-bits */ + uint8_t prbs_mode; /*!< PRBS pattern \ref adi_apollo_serdes_jrx_prbs_mode_e */ +} adi_apollo_serdes_prbs_checker_enable_t; + +/*! +* \brief PRBS Checker status +*/ +typedef struct { + uint8_t err; /*!< Non-sticky bit, active output of error checker */ + uint8_t err_sticky; /*!< Sticky bit of 'have any errors occurred since last error count clear' */ + uint8_t auto_mode_done; /*!< error checker has finished checking the correct number of words in auto mode */ + uint32_t err_count; /*!< count of errors */ +} adi_apollo_serdes_prbs_checker_status_t; + +/*! + * \brief JRx Horizontal Eye Monitor Test Response + */ +typedef struct +{ + uint8_t ver; /*!< Results version */ + int8_t spo_left; /*!< Left Static Phase Offset Value */ + int8_t spo_right; /*!< Right Static Phase Offset Value */ +} adi_apollo_serdes_jrx_horiz_eye_resp_t; + +/*! + * \brief JRx Vertical Eye Monitor Test Response + */ +typedef struct +{ + uint8_t ver; /*!< Results version */ + int8_t eye_heights_at_spo[ADI_APOLLO_SERDES_JRX_VERT_EYE_TEST_RESP_BUF_SIZE]; /*!< Test results buffer */ +} adi_apollo_serdes_jrx_vert_eye_resp_t; + +#endif /* __ADI_APOLLO_SERDES_TYPES_H__ */ + +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_smon.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_smon.h new file mode 100644 index 00000000000000..9ef61e6e1da100 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_smon.h @@ -0,0 +1,157 @@ +/*! + * \brief SMON Block definition headers + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_SMON + * @{ + */ +#ifndef __ADI_APOLLO_SMON_H__ +#define __ADI_APOLLO_SMON_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_smon_types.h" + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Configure SMON parameters + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] smons Target SMON \ref adi_apollo_smon_sel_e + * \param[in] config \ref adi_apollo_smon_pgm_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_smon_pgm(adi_apollo_device_t *device, adi_apollo_blk_sel_t smons, adi_apollo_smon_pgm_t *config); + +/** + * \brief Configure SMON DFOR parameters + * + * \deprecated Use \ref adi_apollo_dformat_ctrl_bit_sel_set() and \ref adi_apollo_dformat_smon_fd_fddc_set() instead. + * This function will be removed in the future. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] links Target links + * \param[in] fddcs Target FDDC \ref adi_apollo_fine_ddc_select_e + * \param[in] config \ref adi_apollo_smon_dfor_pgm_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_smon_dfor_pgm(adi_apollo_device_t *device, adi_apollo_blk_sel_t links, adi_apollo_blk_sel_t fddcs, adi_apollo_smon_dfor_pgm_t *config); + +/** + * \brief Update SMON STATUS + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] smons Target SMON \ref adi_apollo_smon_sel_e + * \param[in] update A pulse on this signal will cause the status value to change in the regmap. 0: Status not updated, 1: Status updated. + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_smon_status_update(adi_apollo_device_t *device, adi_apollo_blk_sel_t smons, uint8_t update); + +/** + * \brief Read SMON STATUS + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] smons Target SMON \ref adi_apollo_smon_sel_e + * \param[out] data \ref adi_apollo_smon_read_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_smon_read(adi_apollo_device_t *device, adi_apollo_blk_sel_t smons, adi_apollo_smon_read_t *data); + +/** + * \brief Inspect SMON parameters + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] smons Target SMON (only one per call) \ref adi_apollo_smon_sel_e + * \param[out] smon_inspect Pointer to SMON inspect structure. \ref adi_apollo_smon_inspect_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_smon_inspect(adi_apollo_device_t *device, adi_apollo_blk_sel_t smons, adi_apollo_smon_inspect_t *smon_inspect); + +/** + * \brief Get the SMON peak value from register. Updates automatically. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] smons Target SMON (only one per call) \ref adi_apollo_smon_sel_e + * \param[out] pk_val Pointer to SMON peadk value result + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_smon_peak_val_get(adi_apollo_device_t *device, adi_apollo_blk_sel_t smons, uint16_t *pk_val); + +/** + * \brief Set the SMON high/low thresholds for GPIO output + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] smons Target SMON \ref adi_apollo_smon_sel_e + * \param[in] thresh_low Lower threshold value (11-bit val) + * \param[in] thresh_high Upper threshold value (11-bit val) + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_smon_thresh_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t smons, uint16_t thresh_low, uint16_t thresh_high); + +/** + * \brief Get the SMON high/low thresholds for GPIO output + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] smons Target SMON (only one select per call) \ref adi_apollo_smon_sel_e + * \param[out] thresh_low Pointer to lower threshold value (11-bit val) + * \param[out] thresh_high Pointer to upper threshold value (11-bit val) + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_smon_thresh_get(adi_apollo_device_t *device, adi_apollo_blk_sel_t smons, uint16_t *thresh_low, uint16_t *thresh_high); + +/** + * \brief Get the SMON peak value from an array of samples + * This function automatically determines the framer type. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] smons Target SMON (only one select per call) \ref adi_apollo_smon_sel_e + * \param[in] cap_array Pointer array of samples + * \param[in] cap_len Number of samples in 'cap_array' + * \param[in] offset First sample in 'cap_arrray' to gebin deserialization + * \param[in] smon_ctrl_bit_mask Mask applied to each sample to extract the bit value + * \param[out] sof_idx Pointer to the start of frame offset found. Can be used to get the next frame via 'offset' + * \param[out] pk_val Pointer to the deserialized peak value found + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_smon_peak_val_from_cap_get(adi_apollo_device_t *device, adi_apollo_blk_sel_t smons, + int16_t cap_array[], uint32_t cap_len, uint32_t offset, + uint16_t smon_ctrl_bit_mask, + uint32_t *sof_idx, uint16_t *pk_val); + +#ifndef CLIENT_IGNORE + +#endif /* CLIENT_IGNORE*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_SMON_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_smon_types.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_smon_types.h new file mode 100644 index 00000000000000..a0dd36513aec93 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_smon_types.h @@ -0,0 +1,129 @@ +/*! + * \brief SMON Block definition headers + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_SMON + * @{ + */ +#ifndef __ADI_APOLLO_SMON_TYPES_H__ +#define __ADI_APOLLO_SMON_TYPES_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_cms_api_common.h" +#include "adi_apollo_common.h" +#include "adi_apollo_fddc_types.h" + +/*============= D E F I N E S ==============*/ +#define ADI_APOLLO_SMON_NUM 8 +#define ADI_APOLLO_SMON_PER_SIDE_NUM 4 +#define ADI_APOLLO_SMON_STATUS_SIZE 3 +#define ADI_APOLLO_SMON_MAX_THRESH_VAL (2047) + +/*! +* \brief Enumerates SMON selection +*/ +typedef enum { + ADI_APOLLO_SMON_NONE = 0x00, /*!< No SMON */ + ADI_APOLLO_SMON_A0 = 0x01, /*!< SMON 0 of SIDE A */ + ADI_APOLLO_SMON_A1 = 0x02, /*!< SMON 1 of SIDE A */ + ADI_APOLLO_SMON_A2 = 0x04, /*!< SMON 2 of SIDE A */ + ADI_APOLLO_SMON_A3 = 0x08, /*!< SMON 3 of SIDE A */ + ADI_APOLLO_SMON_B0 = 0x10, /*!< SMON 0 of SIDE B */ + ADI_APOLLO_SMON_B1 = 0x20, /*!< SMON 1 of SIDE B */ + ADI_APOLLO_SMON_B2 = 0x40, /*!< SMON 2 of SIDE B */ + ADI_APOLLO_SMON_B3 = 0x80, /*!< SMON 3 of SIDE B */ + ADI_APOLLO_SMON_ALL = 0xFF, /*!< All SMON */ + ADI_APOLLO_SMON_ALL_4T4R = 0x33, /*!< All SMON (4t4r) */ +} adi_apollo_smon_sel_e; + +/*! +* \brief Enumerates SMON SFRAMER MODE selection +*/ +typedef enum { + ADI_APOLLO_SFRAMER_TEN_BIT_DISABLE = 0x0, /*!< 10 Bit Framer Disabled */ + ADI_APOLLO_SFRAMER_TEN_BIT_ENABLE = 0x1, /*!< 10 Bit Framer Enabled */ + ADI_APOLLO_SFRAMER_FIVE_BIT_DISABLE = 0x2, /*!< 5 Bit Framer Disabled */ + ADI_APOLLO_SFRAMER_FIVE_BIT_ENABLE = 0x3, /*!< 5 Bit Framer Enabled */ +} adi_apollo_smon_sframer_sel_e; + +/*! + * \brief Enumerates SMON framer types + */ +typedef enum { + ADI_APOLLO_SMON_SFRAMER_TEN_BIT = 0x0, /*!< 10 Bit Framer type */ + ADI_APOLLO_SMON_SFRAMER_FIVE_BIT = 0x1 /*!< 5 Bit Framer type */ +} adi_apollo_smon_sframer_type_e; + +/*! +* \brief SMON programming data +*/ +typedef struct { + adi_apollo_smon_sframer_sel_e sframer_mode_en; /*!< \ref adi_apollo_smon_sframer_sel_e */ + uint32_t smon_period; /*!< Signal Monitor Period */ + uint16_t thresh_low; /*!< 11 bit lower threshold for the absolute value of peak detected */ + uint16_t thresh_high; /*!< 11 bit upper threshold for the absolute value of peak detected */ + uint8_t sync_en; /*!< SMON Synchronization Enable. + 0: Synchronization Disabled; + 1: Synchronization Enabled. + If smon_sync_next == 1, only the next valide edge of the SYSREF pin will be used to synchronize the SMON block. + Subsequent edges of the SYSREF pin will be ignored. Once the next SYSREF has been received, this bit will be cleared */ + uint8_t sync_next; /*!< 0: Continuous mode, 1: Next Synchronization Mode */ + uint8_t sframer_en; /*!< Signal Monitor Serial Framer Enable. 0: Serial Framer is disabled; 1: Serial Framer is enabled. */ + uint8_t sframer_mode; /*!< Signal Monitor Serial Framer Mode Selection. 0: 10-bit Framer Selected; 1: 5-bit Framer Selected. */ + uint8_t sframer_insel; /*!< Signal Monitor Serial Framer Input Selection + When each individual bit is a 1, the corresponding signal statistics information is sent within the frame. + [0]: Reserved for thermometer detect + [1]: Peak Detector Data Inserted in Serial Frame. + [2]: Reserved RMS Magnitude + [3]: Reserved MS Power + [4]: Reserved for threshold crossing + [5]: Reserved */ + uint8_t peak_en; /*!< Signal Monitor Peak Detector Enable. 0: Peak Detector Disabled, 1: Peak Detector Enabled */ + uint8_t status_rdsel; /*!< Signal Monitor Status Read-back Selection + 0x0: Reserved for thermometer detect + 0x1: Peak Detector placed on Status read-back signals + 0x2: Reserved for RMS Magnitude + 0x3: Reserved for MS Power + 0x4: Reserved for threshold crossing + 0x5: Reserved + 0x6-0x7: Reserved */ + uint8_t jlink_sel; /*!< 0: JESD Link0, 1: JESD LInk1 */ + uint8_t gpio_en; /*!< If set, allows GPIO output of peak indication. Peak_en also has to be enabled for this feature. */ +} adi_apollo_smon_pgm_t; + +/*! +* \brief SMON DFOR programming data +*/ +typedef struct { + uint8_t ctrl_bit_0; /*!< Control Bit 0 Mux Selection \ref adi_apollo_dformat_ctrl_bit_e */ + uint8_t ctrl_bit_1; /*!< Control Bit 1 Mux Selection \ref adi_apollo_dformat_ctrl_bit_e */ + uint8_t ctrl_bit_2; /*!< Control Bit 2 Mux Selection \ref adi_apollo_dformat_ctrl_bit_e */ + uint8_t fine_adc_i_sel[ADI_APOLLO_FDDC_NUM]; /*!< FDDC ADC I Path Selection. \ref adi_apollo_dformat_fddc_adc_e */ + uint8_t fine_adc_q_sel[ADI_APOLLO_FDDC_NUM]; /*!< FDDC ADC Q Path Selection. \ref adi_apollo_dformat_fddc_adc_e */ +} adi_apollo_smon_dfor_pgm_t; + +/*! +* \brief SMON Status read data +*/ +typedef struct { + uint8_t status_fcnt; /*!< Increments whenever period counter expires */ + uint32_t status; /*!< 20 bits Signal Monitor Serial Data Output bits */ +} adi_apollo_smon_read_t; + +/*! + * \brief SMON inspect params + */ +typedef struct +{ + adi_apollo_smon_cfg_t dp_cfg; /*!< Parameters defined from device profile \ref apollo_cpu_device_profile_types.h */ + +} adi_apollo_smon_inspect_t; + +#endif /* __ADI_APOLLO_SMON_TYPES_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_sniffer.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_sniffer.h new file mode 100644 index 00000000000000..067946a7bc5af0 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_sniffer.h @@ -0,0 +1,141 @@ +/*! + * \brief Spectrum Sniffer definition headers + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_SNIFFER + * @{ + */ +#ifndef __ADI_APOLLO_SNIFFER_H__ +#define __ADI_APOLLO_SNIFFER_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_sniffer_types.h" + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Enable/disable sniffer + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] sniffers Target sniffer selector \ref adi_apollo_sniffer_select_e + * \param[in] enable 1 to enable, 0 to disable + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_sniffer_enable_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t sniffers, uint8_t enable); + +/** + * \brief Set ADC mux for sniffer + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] sniffers Target sniffer selector \ref adi_apollo_sniffer_select_e + * \param[in] adc Single ADC to input to sniffer \ref adi_apollo_adc_idx_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_sniffer_adc_mux_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t sniffers, uint16_t adc); + +/** + * \brief Setup FFT Sniffer (before oneshot sync) or disable + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] sniffers Target sniffer selector \ref adi_apollo_sniffer_select_e + * \param[in] config Sniffer init parameters \ref adi_apollo_sniffer_init_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_sniffer_init(adi_apollo_device_t *device, adi_apollo_blk_sel_t sniffers, adi_apollo_sniffer_init_t *config); + +/** + * \brief Program FFT Sniffer + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] sniffers Target sniffer selector \ref adi_apollo_sniffer_select_e + * \param[in] config Sniffer programming parameters \ref adi_apollo_sniffer_pgm_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_sniffer_pgm(adi_apollo_device_t *device, adi_apollo_blk_sel_t sniffers, adi_apollo_sniffer_pgm_t *config); + +/** + * \brief Get Sniffer FFT data using regmap data request sequence + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] sniffers Single target sniffer selector \ref adi_apollo_sniffer_select_e + * \param[in] config Sniffer programming parameters \ref adi_apollo_sniffer_pgm_t + * \param[out] fft_data_params FFT data output \ref adi_apollo_sniffer_fft_data_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_sniffer_data_get(adi_apollo_device_t *device, adi_apollo_blk_sel_t sniffers, adi_apollo_sniffer_param_t *config, adi_apollo_sniffer_fft_data_t *fft_data_params); + +/** + * \brief Set sniffer fft enable value in data request sequence. Can be mapped to GPIO + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] sniffers Sniffer selector mask \ref adi_apollo_sniffer_select_e + * \param[in] enable 1 to enable fft calculations, 0 to disable + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_sniffer_fft_enable_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t sniffers, uint8_t enable); + +/** + * \brief Set sniffer fft hold value in data request sequence. Can be mapped to GPIO + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] sniffers Sniffer selector mask \ref adi_apollo_sniffer_select_e + * \param[in] hold Falling edge (1->0) requests new data to read. When fft_done goes high, set hold to 1 and read data. + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_sniffer_fft_hold_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t sniffers, uint8_t hold); + +/** + * \brief Get status of sniffer fft calculation in data request sequence. Can be mapped to GPIO + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] sniffers Single target sniffer selector \ref adi_apollo_sniffer_select_e + * \param[out] done 1: FFT calculation/load done 0: FFT calculation/load not done + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_sniffer_fft_done_get(adi_apollo_device_t *device, adi_apollo_blk_sel_t sniffers, uint8_t *done); + +/** + * \brief Read back sniffer FFT data + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] sniffers Single target sniffer selector \ref adi_apollo_sniffer_select_e + * \param[in] config Sniffer programming parameters \ref adi_apollo_sniffer_pgm_t + * \param[out] fft_data_params FFT data output \ref adi_apollo_sniffer_fft_data_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_sniffer_fft_data_get(adi_apollo_device_t *device, adi_apollo_blk_sel_t sniffers, adi_apollo_sniffer_param_t *config, adi_apollo_sniffer_fft_data_t *fft_data_params); + + +#ifdef __cplusplus +} +#endif + +#endif /*__ADI_APOLLO_SNIFFER_H__ */ +/*! @} */ \ No newline at end of file diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_sniffer_types.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_sniffer_types.h new file mode 100644 index 00000000000000..e7474b843d881a --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_sniffer_types.h @@ -0,0 +1,124 @@ +/*! + * \brief API header file + * This file contains all the publicly exposed methods and data + * structures to interface with API. + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_SNIFFER + * @{ + */ + +#ifndef __ADI_APOLLO_SNIFFER_TYPES_H__ +#define __ADI_APOLLO_SNIFFER_TYPES_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_cms_api_common.h" +#include "adi_apollo_common.h" + +/*============= D E F I N E S ==============*/ +#define ADI_APOLLO_SNIFFER_FFT_LENGTH 512 +#define ADI_APOLLO_SNIFFER_NUM 2 + +/*! +* \brief Enumerates selection between gpio and regmap input +*/ +typedef enum { + ADI_APOLLO_SNIFFER_GPIO_INPUT = 0x0, /*!< Select GPIO Input */ + ADI_APOLLO_SNIFFER_REGMAP_INPUT = 0x1 /*!< Select Regmap Input */ +} adi_apollo_sniffer_gpio_regmap_select_e; + +/*! +* \brief Enumerates sniffer for side A and B +*/ +typedef enum { + ADI_APOLLO_SNIFFER_A = 0x1, /*!< Select Sniffer Side A */ + ADI_APOLLO_SNIFFER_B = 0x2, /*!< Select Sniffer Side B */ + ADI_APOLLO_SNIFFER_ALL = 0x3 /*!< Select Sniffer Side A&B (same for both 4T4R and 8T8R)*/ +} adi_apollo_sniffer_select_e; + +/*! +* \brief Enumerates Spectrum Sniffer Modes +*/ +typedef enum { + ADI_APOLLO_SNIFFER_NORMAL_MAGNITUDE = 0x0, /*!< Normal Magnitude mode */ + ADI_APOLLO_SNIFFER_INSTANT_MAGNITUDE = 0x1, /*!< Instantaneous/Debug Magnitude mode */ + ADI_APOLLO_SNIFFER_NORMAL_IQ = 0x2, /*!< Normal IQ mode */ + ADI_APOLLO_SNIFFER_INSTANT_IQ = 0x3 /*!< Instantaneous/Debug IQ mode */ +} adi_apollo_sniffer_mode_e; + +/*! +* \brief Spectrum Sniffer Init Parameters +*/ +typedef struct { + uint8_t sniffer_enable; /*!< 0: Disable spec Sniffer 1:Enable spec sniffer */ + uint8_t fft_hold_sel; /*!< 0: Select via GPIO 1:Select via Regmap + \ref adi_apollo_sniffer_gpio_regmap_select_e */ + uint8_t fft_enable_sel; /*!< 0: Select via GPIO 1:Select via Regmap + \ref adi_apollo_sniffer_gpio_regmap_select_e */ + uint8_t real_mode; /*!< 0: Complex FFT, 1 : Real FFT + \ref adi_apollo_sniffer_fft_type_e*/ + uint8_t max_threshold; /*!< Maximum Threshold for Magnitude */ + uint8_t min_threshold; /*!< Minimum Threshold for Magnitude */ +} adi_apollo_sniffer_init_t; + +/*! +* \brief Spectrum Sniffer Programming Parameters +*/ +typedef struct { + uint8_t bottom_fft_enable; /*!< 1: Bottom FFT Enable, 0: Bottom FFT Disable */ + uint8_t window_enable; /*!< 1: Windowing Enable, 0: Windowing Disable */ + uint8_t sort_enable; /*!< 1: Sorting Enable, 0: Sorting Disable */ + uint8_t low_power_enable; /*!< 1: low power Enable, 0: Normal mode */ + uint8_t dither_enable; /*!< 1: dither Enable, 0: dither Disable */ + uint8_t continuous_mode; /*!< 1: continuous mode, 0: single mode + \ref adi_apollo_sniffer_continuous_mode_e */ + uint8_t alpha_factor; /*!< Alpha Factor. 0 - 9 valid values + 0 : Exponential Averaging is Disabled + 1-9 : Exponential Averaging is Enabled */ + uint16_t adc; /*!< Single ADC select \ref adi_apollo_adc_idx_e */ + adi_apollo_sniffer_mode_e sniffer_mode; /*!< \ref adi_apollo_sniffer_mode_e */ + +} adi_apollo_sniffer_pgm_t; + +/*! +* \brief Spectrum Sniffer Reading Parameters +*/ +typedef struct { + uint8_t run_fft_engine_background; /*!< If 0, stop FFT engine when reading data to save power */ + uint64_t timeout_us; /*!< Timeout: if set to 0, no timeout */ +} adi_apollo_sniffer_read_t; + + +/*! +* \brief Spectrum Sniffer Parameters +*/ +typedef struct { + adi_apollo_sniffer_init_t init; + adi_apollo_sniffer_pgm_t pgm; + adi_apollo_sniffer_read_t read; +} adi_apollo_sniffer_param_t; + +/*! +* \brief Spectrum Sniffer data +*/ +typedef struct { + uint16_t mag_i_data[ADI_APOLLO_SNIFFER_FFT_LENGTH]; /*!< Contents of Magnitude / I data registers */ + uint16_t bin_q_data[ADI_APOLLO_SNIFFER_FFT_LENGTH]; /*!< Contents of Bin # / Q data registers */ + uint8_t bin_above_threshold[ADI_APOLLO_SNIFFER_FFT_LENGTH]; /*!< Contents of bin above threshold data registers (Magnitude mode only) */ + uint8_t bin_below_threshold[ADI_APOLLO_SNIFFER_FFT_LENGTH]; /*!< Contents of bin below threshold data registers (Magnitude mode only) */ + + uint16_t max_threshold; /*!< Max threshold value */ + uint16_t min_threshold; /*!< Min threshold value */ + uint16_t valid_data_length; /*!< Length of valid data in arrays (512 complex, 256 real) */ + uint8_t fft_is_complex; /*!< Whether or not the FFT is complex or real */ + adi_apollo_sniffer_mode_e data_mode; /*!< Sniffer mode during data capture \ref adi_apollo_sniffer_mode_e */ +} adi_apollo_sniffer_fft_data_t; + +#endif /* __ADI_APOLLO_SNIFFER_TYPES_H__ */ +/*! @} */ \ No newline at end of file diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_startup.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_startup.h new file mode 100644 index 00000000000000..e441cd73f7538d --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_startup.h @@ -0,0 +1,49 @@ +/*! + * \brief Apollo API startup sequence API header + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_STARTUP + * @{ + */ +#ifndef __ADI_APOLLO_STARTUP_H__ +#define __ADI_APOLLO_STARTUP_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_common.h" +#include "adi_apollo_device_types.h" + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Perform Apollo startup sequence + * + * \note All clocks must be configured for the device profile configuration prior to + * calling this function. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] dev_profile Device profile + * \param[in] startup_type Startup sequence run mask. May run sections \ref adi_apollo_startup_seq_type_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_startup_execute(adi_apollo_device_t *device, adi_apollo_top_t *dev_profile, uint32_t startup_type); + +#ifndef CLIENT_IGNORE +#endif /* CLIENT_IGNORE*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_STARTUP_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_startup_types.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_startup_types.h new file mode 100644 index 00000000000000..93f7bd1f5e75f7 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_startup_types.h @@ -0,0 +1,95 @@ +/*! + * \brief Apollo API startup sequence types + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_STARTUP + * @{ + */ +#ifndef __ADI_APOLLO_STARTUP_TYPES_H__ +#define __ADI_APOLLO_STARTUP_TYPES_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_device_types.h" + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +/*! + * \brief Enumerates startup sequence types + */ +typedef enum { + ADI_APOLLO_STARTUP_SEQ_FW_LOAD = 0x00000001, + ADI_APOLLO_STARTUP_SEQ_PROFILE_LOAD = 0x00000002, + ADI_APOLLO_STARTUP_SEQ_TMU_EN = 0x00000004, + ADI_APOLLO_STARTUP_SEQ_DP_CONFIG = 0x00000008, + ADI_APOLLO_STARTUP_SEQ_LINK_EN = 0x00000010, + ADI_APOLLO_STARTUP_SEQ_TXRX_ACTIVATE = 0x00000020, + ADI_APOLLO_STARTUP_SEQ_SYNC = 0x00000040, + + ADI_APOLLO_STARTUP_SEQ_DEFAULT = 0x0000007F, +} adi_apollo_startup_seq_type_e; + +/*! +* \brief Enumerates FW image types +*/ +typedef enum { + ADI_APOLLO_FW_ID_CORE_0_STD_FW_BIN = 0, + ADI_APOLLO_FW_ID_CORE_1_STD_FW_BIN = 1, + + ADI_APOLLO_FW_ID_SECR_BOOT_HDR_BIN = 2, + ADI_APOLLO_FW_ID_CORE_0_TYE_FW_BIN = 3, + ADI_APOLLO_FW_ID_CORE_1_TYE_FW_BIN = 4, + ADI_APOLLO_FW_ID_TYE_OPER_FW_BIN = 5, + + ADI_APOLLO_FW_ID_PROD_SECR_BOOT_HDR_BIN = 6, + ADI_APOLLO_FW_ID_PROD_CORE_0_TYE_FW_BIN = 7, + ADI_APOLLO_FW_ID_PROD_CORE_1_TYE_FW_BIN = 8, + ADI_APOLLO_FW_ID_PROD_TYE_OPER_FW_BIN = 9, + + ADI_APOLLO_FW_ID_MAX + +} adi_apollo_startup_fw_id_e; + + +#ifndef CLIENT_IGNORE + +/*! + * \brief Apollo FW image provider structure + */ +typedef struct adi_apollo_fw_provider_t { + char *desc; /*!< User specific text description */ + + void *tag; /*!< Implementation specific struct/obj */ +} adi_apollo_fw_provider_t; + +/*! + * \brief Apollo startup sequence - open. Called before a FW image load. + */ +typedef int32_t (*adi_apollo_fw_provider_open_t) (adi_apollo_fw_provider_t *obj, adi_apollo_startup_fw_id_e fw_id); + +/*! + * \brief Apollo startup sequence - close. Called after a FW image load. + */ +typedef int32_t (*adi_apollo_fw_provider_close_t) (adi_apollo_fw_provider_t *obj, adi_apollo_startup_fw_id_e fw_id); + +/*! + * \brief Apollo startup sequence - get. Called during FW image load to get raw FW bytes + */ +typedef int32_t (*adi_apollo_fw_provider_get_t) (adi_apollo_fw_provider_t *obj, adi_apollo_startup_fw_id_e fw_id, uint8_t **byte_arr, uint32_t* bytes_read); + +#endif /* CLIENT_IGNORE*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_STARTUP_TYPES_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_sysclk_cond.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_sysclk_cond.h new file mode 100644 index 00000000000000..05f7071d19a508 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_sysclk_cond.h @@ -0,0 +1,75 @@ +/*! + * \brief: Apollo system clock calibration functions + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + * + */ + +/*! + * \addtogroup ADI_APOLLO_SYSCLK_COND + * @{ + */ +#ifndef __ADI_APOLLO_SYSCLK_COND_H__ +#define __ADI_APOLLO_SYSCLK_COND_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_cfg_types.h" +#include "adi_apollo_mailbox.h" + +/*============= E X P O R T S ==============*/ + +#define ADI_APOLLO_SYSCLK_COND_CENTER_MAX_TO 10 + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Execute a foreground ADC clock conditioning calibration + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_sysclk_cond_cal(adi_apollo_device_t *device); + +/** + * \brief Execute a background clock conditioning calibration + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_sysclk_cond_bg_cal_start(adi_apollo_device_t* device); + +/** + * \brief Stop background clock conditioning calibration + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_sysclk_cond_bg_cal_stop(adi_apollo_device_t* device); + +/** + * \brief Resume background clock conditioning calibration + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_sysclk_cond_bg_cal_resume(adi_apollo_device_t* device); + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_SYSCLK_COND_H__ */ +/*! @} */ \ No newline at end of file diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_sysclk_cond_types.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_sysclk_cond_types.h new file mode 100644 index 00000000000000..353bf6a9f8de07 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_sysclk_cond_types.h @@ -0,0 +1,88 @@ +/*! **************************************************************************** + * + * @file: adi_apollo_sysclk_cond_types.h + * + * @brief: Apollo system clock calibration structure + * + * @details: This file contains all the System Clock calibrations + * prototypes referenced. + * + ******************************************************************************* + Copyright(c) 2019-2020 Analog Devices, Inc. All Rights Reserved. This software + is proprietary & confidential to Analog Devices, Inc. and its licensors. By + using this software you agree to the terms of the associated Analog Devices + License Agreement. + ******************************************************************************* + */ + +#ifndef __ADI_APOLLO_SYSCLK_COND_TYPES_H__ +#define __ADI_APOLLO_SYSCLK_COND_TYPES_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_cms_api_common.h" +#include "adi_apollo_common.h" + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +/*============= D E F I N E S ==============*/ +#define ADI_APOLLO_SYSCLK_COND_CENTER_MAX_TO 15 /*!< Max timeout for clock conditioning centering to complete */ + +/*! +* \brief Enumerates sysclk cond errors +*/ +typedef enum { + ADI_APOLLO_SYSCLK_COND_ERR_OK = 0, /*!< No error */ + ADI_APOLLO_SYSCLK_COND_ERR_TOTAL_VALID_OFST = -1, /*!< Total valid offset error */ + ADI_APOLLO_SYSCLK_COND_ERR_REC_VALID_OFST = -2 /*!< Recommended offset error */ +} adi_apollo_sysclk_cond_err_e; + + +/*! +* \brief System clock conditioning calibration config structure +*/ +typedef struct adi_apollo_sysclk_cond_calconfig +{ + uint8_t adc_centering_capture_length_Kb; /*!< Number ADC samples stored per BMEM capture, in KiloSamples. 8=8192 ADC samples */ + uint8_t adc_centering_capture_avg; /*!< Number of averaged sweep runs used for offset estimation.*/ + uint8_t adc_centering_capture_runs; /*!< Number of BMEM captures done per each individual offset setting, during a particular sweep.*/ + uint8_t adc_centering_done; /*!< Output flag. Read-Only. This flag is 0=in progress, and 1=completed */ + uint8_t adc_centering_use_debubbler; /*!< Enable for measurement debubbling. If set to 1, this will enable removal of false-positive measurements. */ + uint8_t adc_centering_use_noise_not_spread; /*!< Enable for measurements using noise variance instead of ADC code spread. + If set to 1, an ADC sample variance estimate over each BMEM capture is used as measurement. + If set to 0, ADC code spread (Max - Min) is used as measurement. */ + uint8_t adc_use_caldata; /*!< Enable for direct coefficient usage. If set to 1, coefficients stored in calData's adc01CalCoeffs are used for clock trimming. Recommended value is 0 */ + int8_t adc_centering_min_valid_offset; /*!< Sets the lowest offset used during sweeps. The lowest value this variable can take is -26. Recommended value is -26 (0xE6 in uint8) */ + int8_t adc_centering_max_valid_offset; /*!< Sets the highest offset used during sweeps. The highest value this variable can take is 14. Recommended value is 14 */ + uint8_t padding[3]; /*!< Unused */ + uint32_t adc_centering_low_threshold; /*!< Sets the lower-bound on measurements that are considered as good. Recommended value is 3395 */ + uint32_t adc_centering_high_threshold; /*!< Sets the upper-bound on measurements that are considered as good. Recommneded value is 2142397 */ + uint16_t adc_centering_precapture_delayus; /*!< Delay added before each BMEM capture. Its units are microseconds. Recommended value is 10000 */ + uint16_t adc_post_correction_delayus; /*!< Delay added after each analog-domain correction. Recommended value is 0 */ +} adi_apollo_sysclk_cond_calconfig_t; + +typedef struct adi_apollo_sysclk_cond_caldata +{ + int8_t adc01_recommended_offset; /*!< These is the recommended offset to be used for optimal ADC performance. */ + uint8_t total_valid_offsets; /*!< The total number of offset found to be within the criteria set by calconfig_t */ + int8_t current_offset; /*!< The offset currently used. It is automatically set to adc01_recommended_offset whenever re-centering is run. + However, the user can set any desired current_offset, and run trimming without re-centering and the desired offset will be applied */ + int8_t adc0_min_offset; /*!< Minimum offset found for ADC Channel 0 (Per side), that meets the criteria set in calconfig_t */ + int8_t adc1_min_offset; /*!< Minimum offset found for ADC Channel 1 (Per side), that meets the criteria set in calconfig_t */ + int8_t adc0_max_offset; /*!< Maximum offset found for ADC Channel 0 (Per side), that meets the criteria set in calconfig_t */ + int8_t adc1_max_offset; /*!< Maximum offset found for ADC Channel 4 (Per side), that meets the criteria set in calconfig_t */ + int8_t adc01_calcoeffs[6]; /*!< Coefficients used for direct trimming of the ADC path */ + uint8_t padding64[3]; + /* the compiler wants to place adc_std_combined_measurements at multiples of 8 bytes */ + uint64_t adc_std_combined_measurements[41]; /*!< Resulting measurements after the re-centering routine completes. */ + uint32_t crc; +} adi_apollo_sysclk_cond_caldata_t; + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_SYSCLK_COND_TYPES_H__ */ +/*! @} */ \ No newline at end of file diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_tmode.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_tmode.h new file mode 100644 index 00000000000000..9327e76bb60d5b --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_tmode.h @@ -0,0 +1,92 @@ +/*! + * \brief Test Mode Block definition headers + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_TMODE + * @{ + */ +#ifndef __ADI_APOLLO_TMODE_H__ +#define __ADI_APOLLO_TMODE_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_tmode_types.h" + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Set ADC Test Mode + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] links Target links \ref adi_apollo_jesd_link_select_e + * \param[in] converter_mask Target converters selection mask \ref adi_apollo_rx_tmode_sel_e + * \param[in] mode Test mode, \ref adi_apollo_rx_tmode_type_sel_e + * \param[in] res Test mode output resolution, \ref adi_apollo_rx_tmode_res_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_tmode_config_set(adi_apollo_device_t *device, + const uint16_t links, + const uint8_t converter_mask, + adi_apollo_rx_tmode_type_sel_e mode, + adi_apollo_rx_tmode_res_e res); + +/** + * \brief Set ADC User Pattern of Test Mode + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] links Target links \ref adi_apollo_jesd_link_select_e + * \param[in] usr_pattern User pattern + * \param[in] length User pattern array length + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_tmode_usr_pattern_set(adi_apollo_device_t *device, + const uint16_t links, + uint16_t usr_pattern[], + uint32_t length); + +/** + * \brief Set ADC Test Mode + * + * \param[in] device Context variable -Pointer to the device structure + * \param[in] links Target links + * \param[in] mode Test mode, \ref adi_apollo_rx_tmode_type_sel_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_tmode_type_sel_set(adi_apollo_device_t *device, + const uint16_t links, + adi_apollo_rx_tmode_type_sel_e mode); + +/** + * \brief Set the adc test mode resolution. + * + * \param[in] device Context variable -Pointer to the device structure + * \param[in] links Target link select + * \param[in] res Test mode output resolution, \ref adi_apollo_rx_tmode_res_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 + */ +int32_t adi_apollo_tmode_resolution_set(adi_apollo_device_t *device, + const uint16_t links, + adi_apollo_rx_tmode_res_e res); + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_TMODE_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_tmode_types.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_tmode_types.h new file mode 100644 index 00000000000000..db0b3fd557d937 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_tmode_types.h @@ -0,0 +1,28 @@ +/*! + * \brief Test Mode Block definition headers + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_TMODE + * @{ + */ +#ifndef __ADI_APOLLO_RX_TMODE_TYPES_H__ +#define __ADI_APOLLO_RX_TMODE_TYPES_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_cms_api_common.h" +#include "adi_apollo_common.h" + +/*============= D E F I N E S ==============*/ +#define ADI_APOLLO_TMODE_USR_PAT_NUM 8 + +/* Force idl-gen to pick up file */ +typedef uint8_t adi_apollo_tmode_types_dummy; + +#endif /* __ADI_APOLLO_RX_TMODE_TYPES_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_trigts.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_trigts.h new file mode 100644 index 00000000000000..55fdaf4b47475e --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_trigts.h @@ -0,0 +1,348 @@ +/*! + * \brief Trigger and Timestamp functional block definition header + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_TRIGGER_TS + * @{ + */ +#ifndef __ADI_APOLLO_TRIGGER_TS_H__ +#define __ADI_APOLLO_TRIGGER_TS_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_trigts_types.h" + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Configures trigger masters offset and period + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] side_sel Target side \ref adi_apollo_side_select_e + * \param[in] trig_masters trigger masters selection \ref adi_apollo_trig_mst_sel_e + * \param[in] config Configuration parameters. \ref adi_apollo_trig_mst_config_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_trigts_mst_config(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_side_select_e side_sel, + uint32_t trig_masters, adi_apollo_trig_mst_config_t *config); + +/** + * \brief Gets the trigger master configuration + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] side_sel Target side \ref adi_apollo_side_select_e + * \param[in] trig_masters trigger masters selection \ref adi_apollo_trig_mst_sel_e + * \param[out] config Current trig mst configuration. \ref adi_apollo_trig_mst_config_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_trigts_mst_inspect(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_side_select_e side_sel, + uint32_t trig_masters, adi_apollo_trig_mst_config_t *config); + +/** + * \brief Enables Mute trigger feature + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] side_sel Target side \ref adi_apollo_side_select_e + * \param[in] trig_masters trigger masters selection \ref adi_apollo_trig_mst_sel_e + * \param[in] trigger_mute Enable trigger mute. \ref adi_apollo_trig_mute_sel_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_trigts_mst_mute(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_side_select_e side_sel, + uint32_t trig_masters, adi_apollo_trig_mute_sel_e trigger_mute); + +/** + * \brief Selects which mute mask to use for muting after specified count number + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] side_sel Target side \ref adi_apollo_side_select_e + * \param[in] trig_masters trigger masters selection \ref adi_apollo_trig_mst_sel_e + * \param[in] trigger_mute Which trigger counter register to use for trigger mute. \ref adi_apollo_trig_mute_mask_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_trigts_mst_mute_mask_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_side_select_e side_sel, + uint32_t trig_masters, adi_apollo_trig_mute_mask_e trigger_mute); + +/** + * \brief Sets the number of pulses to enable trigger master before muting + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] side_sel Target side \ref adi_apollo_side_select_e + * \param[in] trigger_mute Which trigger counter register to use for trigger mute. \ref adi_apollo_trig_mute_mask_e + * \param[in] trig_mst Trigger master to count pulses \ref adi_apollo_trig_mst_sel_e + * \param[in] pulse_count Number of pulses after which trigger master is muted + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_trigts_mst_mute_mask_count_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_side_select_e side_sel, + adi_apollo_trig_mute_mask_e trigger_mute, adi_apollo_trig_mst_sel_e trig_mst, uint16_t pulse_count); + +/** + * \brief Select trigger selection mux output for dynamic reconfig + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] side_sel Target side \ref adi_apollo_side_select_e + * \param[in] trig_sel Trigger Selection Mux Select Line \ref adi_apollo_trigger_sel_mux_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_trigts_reconfig_trig_sel_mux_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_side_select_e side_sel, + adi_apollo_trigger_sel_mux_e trig_sel); + +/** + * \brief Select trigger selection mux output for CDDC/CDUC + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] cdrcs Target CDRCs \ref adi_apollo_cddc_select_e or \ref adi_apollo_cduc_select_e + * \param[in] trig_sel Trigger Selection Mux Select Line \ref adi_apollo_trigger_sel_mux_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_trigts_cdrc_trig_sel_mux_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t cdrcs, + adi_apollo_trigger_sel_mux_e trig_sel); + +/** + * \brief Select trigger selection mux output for FDDC/FDUC + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] fdrcs Target FDRCs \ref adi_apollo_fine_ddc_select_e or \ref adi_apollo_fine_duc_select_e + * \param[in] trig_sel Trigger Selection Mux Select Line \ref adi_apollo_trigger_sel_mux_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_trigts_fdrc_trig_sel_mux_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t fdrcs, adi_apollo_trigger_sel_mux_e trig_sel); + +/** + * \brief Select trigger selection mux output for BMEM + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] bmems Target BMEM \ref adi_apollo_bmem_sel_e + * \param[in] trig_sel Trigger Selection Mux Select Line \ref adi_apollo_trigger_sel_mux_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_trigts_bmem_trig_sel_mux_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t bmems, adi_apollo_trigger_sel_mux_e trig_sel); + +/** + * \brief Select trigger selection mux output for PFILT + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] pfilts Target PFILT \ref adi_apollo_pfilt_sel_e + * \param[in] trig_sel Trigger Selection Mux Select Line \ref adi_apollo_trigger_sel_mux_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_trigts_pfilt_trig_sel_mux_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t pfilts, adi_apollo_trigger_sel_mux_e trig_sel); + +/** + * \brief Select trigger selection mux output for CFIR + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] cfirs Target CFIR \ref adi_apollo_cfir_sel_e + * \param[in] trig_sel Trigger Selection Mux Select Line \ref adi_apollo_trigger_sel_mux_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_trigts_cfir_trig_sel_mux_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t cfirs, adi_apollo_trigger_sel_mux_e trig_sel); + +/** + * \brief Configures CNCO trigger master's offset and period + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] cncos Target CDDC \ref adi_apollo_cddc_select_e + * \param[in] config Configuration parameters. \ref adi_apollo_trig_mst_config_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_trigts_cnco_trig_mst_config(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t cncos, + adi_apollo_trig_mst_config_t *config); + +/** + * \brief Configures FNCO trigger master's offset and period + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] fncos Target FDDC \ref adi_apollo_fine_ddc_select_e + * \param[in] config Configuration parameters. \ref adi_apollo_trig_mst_config_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_trigts_fnco_trig_mst_config(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t fncos, + adi_apollo_trig_mst_config_t *config); + +/** + * \brief Configures PFILT trigger master's offset and period + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] pfilts Target PFILT \ref adi_apollo_pfilt_select_e + * \param[in] config Configuration parameters. \ref adi_apollo_trig_mst_config_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_trigts_pfilt_trig_mst_config(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t pfilts, + adi_apollo_trig_mst_config_t *config); +/** + * \brief Configures CFIR trigger master's offset and period + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] cfirs Target CFIR \ref adi_apollo_cfir_select_e + * \param[in] config Configuration parameters. \ref adi_apollo_trig_mst_config_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_trigts_cfir_trig_mst_config(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t cfirs, + adi_apollo_trig_mst_config_t *config); + +/** + * \brief Configures reconfig ctrl trigger masters offset and period + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] side_sel Target side \ref adi_apollo_side_select_e + * \param[in] config Configuration parameters. \ref adi_apollo_trig_mst_config_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_trigts_reconfig_trig_mst_config(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, + adi_apollo_side_select_e side_sel, adi_apollo_trig_mst_config_t *config); + +/** + * \brief Creates a trigger pulse via spi/hsci + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] side_sel Target side \ref adi_apollo_side_select_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_trigts_trig_now(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_side_select_e side_sel); + +/** + * \brief Return the timestamp counter value + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] side_sel Target side \ref adi_apollo_side_select_e + * \param[out] val Pointer to 64-bit current timestamp counter value + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_trigts_counter_get(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_side_select_e side_sel, uint64_t *val); + +/** + * \brief Set the timestamp counter reset mode (via SPI or SYSREF) + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] side_sel Target side \ref adi_apollo_side_select_e + * \param[in] mode Reset mode. ADI_APOLLO_TRIG_TS_RESET_MODE_SYSREF, _SPI based. \ref adi_apollo_trig_ts_reset_mode_e + * + * Use adi_apollo_trigts_ts_reset() to reset the timestamp counter during program execution. + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_trigts_ts_reset_mode_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, uint16_t side_sel, adi_apollo_trig_ts_reset_mode_e mode); + +/** + * \brief Reset the timestamp counter + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] side_sel Target side \ref adi_apollo_side_select_e + * \param[in] sync 1 to enable reset on sync event AND perform sync event. 0 to just enable. (n/a for SPI reset mode) + * + * Calling this API with sync=0 enables the sync event, but doesn't execute it. This allows arming + * multiple timestamp counters and syncing them together on final call with sync=1. + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_trigts_ts_reset(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, uint16_t side_sel, uint8_t sync); + +/** + * \brief Clears the timestamp reset done status sticky bit + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] side_sel Target side \ref adi_apollo_side_select_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_trigts_reset_done_clear(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, uint16_t side_sel); + +/** + * \brief Returns the reset-done status following a timestamp reset request + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] side_sel Target side \ref adi_apollo_side_select_e + * \param[out] reset_done_status Pointer to reset-done status. 1 if reset completed, 0 otherwise. + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_trigts_reset_done_get(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, uint16_t side_sel, uint8_t *reset_done_status); + +/** + * \brief Setup external trigger without dynamic reconfiguration + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure. + * \param[in] terminal Target terminal \ref adi_apollo_terminal_e + * \param[in] side_sel Target side \ref adi_apollo_side_select_e + */ +int32_t adi_apollo_trigts_ext_trig_no_dr_setup(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, uint16_t side_sel); + +#ifndef CLIENT_IGNORE +#endif /* CLIENT_IGNORE */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_TRIGGER_TS_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_trigts_types.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_trigts_types.h new file mode 100644 index 00000000000000..10d881048c67f0 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_trigts_types.h @@ -0,0 +1,101 @@ +/*! + * \brief Trigger and Timestamp functional block type definitions header + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_TRIGGER_TS + * @{ + */ +#ifndef __ADI_APOLLO_TRIGGER_TS_TYPES_H__ +#define __ADI_APOLLO_TRIGGER_TS_TYPES_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_cms_api_common.h" +#include "adi_apollo_common.h" + +/*============= D E F I N E S ==============*/ +/*! +* \brief Enumerates TRIGGER MASTER selection for both Side A and B +*/ +typedef enum { + ADI_APOLLO_TRIG_MST_CNCO_0 = 0x00000001, + ADI_APOLLO_TRIG_MST_CNCO_2 = 0x00000002, /*! 8T8R mode */ + ADI_APOLLO_TRIG_MST_CNCO_1 = 0x00000004, + ADI_APOLLO_TRIG_MST_CNCO_3 = 0x00000008, /*! 8T8R mode */ + ADI_APOLLO_TRIG_MST_FNCO_0 = 0x00000010, + ADI_APOLLO_TRIG_MST_FNCO_4 = 0x00000020, /*! 8T8R mode */ + ADI_APOLLO_TRIG_MST_FNCO_1 = 0x00000040, + ADI_APOLLO_TRIG_MST_FNCO_5 = 0x00000080, /*! 8T8R mode */ + ADI_APOLLO_TRIG_MST_FNCO_2 = 0x00000100, + ADI_APOLLO_TRIG_MST_FNCO_6 = 0x00000200, /*! 8T8R mode */ + ADI_APOLLO_TRIG_MST_FNCO_3 = 0x00000400, + ADI_APOLLO_TRIG_MST_FNCO_7 = 0x00000800, /*! 8T8R mode */ + ADI_APOLLO_TRIG_MST_BMEM0 = 0x00001000, /*! Rx only */ + ADI_APOLLO_TRIG_MST_BMEM1 = 0x00004000, /*! Rx only */ + ADI_APOLLO_TRIG_MST_LINEARX = 0x00010000, + ADI_APOLLO_TRIG_MST_RECONFIG = 0x00040000, + ADI_APOLLO_TRIG_MST_PFILT0 = 0x00080000, + ADI_APOLLO_TRIG_MST_PFILT1 = 0x00100000, + ADI_APOLLO_TRIG_MST_CFIR0 = 0x00200000, + ADI_APOLLO_TRIG_MST_CFIR1 = 0x00400000 +} adi_apollo_trig_mst_sel_e; + +/*! +* \brief Enumerates the output of trigger selection mux +*/ +typedef enum { + ADI_APOLLO_TRIG_INPUT = 0, + ADI_APOLLO_TRIG_SPI = 1, + ADI_APOLLO_TRIG_MASTER = 2 +} adi_apollo_trigger_sel_mux_e; + +/*! +* \brief Enumerates trigger mute selection +*/ +typedef enum { + ADI_APOLLO_TRIG_MUTE_ENABLE = 1, /*! Mute out the Trigger Master output */ + ADI_APOLLO_TRIG_MUTE_DISABLE = 0 +} adi_apollo_trig_mute_sel_e; + +/*! +* \brief Enumerates trigger mute selection +*/ +typedef enum { + ADI_APOLLO_TRIG_MUTE_MASK_DISABLE = 0, /*! Disable mute counter mask */ + ADI_APOLLO_TRIG_MUTE_MASK_0 = 1, /*! Mute trigger after count in mask 0 */ + ADI_APOLLO_TRIG_MUTE_MASK_1 = 2 /*! Mute trigger after count in mask 1 */ +} adi_apollo_trig_mute_mask_e; + +/*! +* \brief Enumerates trigger Enable / Disable selection +*/ +typedef enum { + ADI_APOLLO_TRIG_ENABLE = 1, /*! Enable trigger */ + ADI_APOLLO_TRIG_DISABLE = 0 /*! Disable trigger */ +} adi_apollo_trig_enable_sel_e; + +/*! +* \brief Enumerates timestamp reset mode +*/ +typedef enum +{ + ADI_APOLLO_TRIG_TS_RESET_MODE_SYSREF = 0, /*! SYSREF based reset */ + ADI_APOLLO_TRIG_TS_RESET_MODE_SPI = 1 /*! SPI based reset */ +} adi_apollo_trig_ts_reset_mode_e; + +/*! + * \brief Trigger Master Config Structure + */ +typedef struct { + uint64_t trig_period; /*! Cycles at sampling frequency between triggers */ + uint64_t trig_offset; /*! Min. of 31 for sysref reset, 32 for SPI reset */ + adi_apollo_trig_enable_sel_e trig_enable; +} adi_apollo_trig_mst_config_t; + +#endif /* __ADI_APOLLO_TRIGGER_TS_TYPES_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_tx.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_tx.h new file mode 100644 index 00000000000000..9be6d724fe2931 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_tx.h @@ -0,0 +1,154 @@ +/*! + * \brief TX top level API definition headers + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_TX + * @{ + */ +#ifndef __ADI_APOLLO_TX_H__ +#define __ADI_APOLLO_TX_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_tx_types.h" + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Configures TX data path blocks for device side + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] side Device side, A or B \ref adi_apollo_sides_e + * \param[in] config Configuration parameters. \ref adi_apollo_txpath_t + * \param[in] jrx_config JESD JRx parameters for Tx data path. \ref adi_apollo_jesd_rx_cfg_t + * + * \return API_CMS_ERROR_OK Completed successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_tx_configure(adi_apollo_device_t* device, adi_apollo_sides_e side, adi_apollo_txpath_t *config, adi_apollo_jesd_rx_cfg_t *jrx_config); + +/** + * \brief Configures TX coarse DUC + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] side Device side, A or B \ref adi_apollo_sides_e + * \param[in] idx Index of block to configure. \ref adi_apollo_cduc_idx_e + * \param[in] config Configuration parameters. \ref adi_apollo_cduc_cfg_t + * + * \return API_CMS_ERROR_OK Completed successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_tx_cduc_configure(adi_apollo_device_t *device, adi_apollo_sides_e side, adi_apollo_cduc_idx_e idx, adi_apollo_cduc_cfg_t *config); + +/** + * \brief Configures TX fine DUC + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] side Device side, A or B \ref adi_apollo_sides_e + * \param[in] idx Index of block to configure. \ref adi_apollo_fduc_idx_e + * \param[in] config Configuration parameters. \ref adi_apollo_fduc_cfg_t + * + * \return API_CMS_ERROR_OK Completed successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_tx_fduc_configure(adi_apollo_device_t *device, adi_apollo_sides_e side, adi_apollo_fduc_idx_e idx, adi_apollo_fduc_cfg_t *config); + +/** + * \brief Configures TX pfilt + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] side Device side, A or B \ref adi_apollo_sides_e + * \param[in] idx Index of block to configure. \ref adi_apollo_pfilt_idx_e + * \param[in] config Configuration parameters. \ref adi_apollo_pfilt_cfg_t + * + * \return API_CMS_ERROR_OK Completed successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_tx_pfilt_configure(adi_apollo_device_t *device, adi_apollo_sides_e side, adi_apollo_pfilt_idx_e idx, adi_apollo_pfilt_cfg_t *config); + +/** + * \brief Configures TX cfir + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] side Device side, A or B \ref adi_apollo_sides_e + * \param[in] idx Index of block to configure. \ref adi_apollo_cfir_idx_e + * \param[in] config Configuration parameters. \ref adi_apollo_cfir_cfg_t + * + * \return API_CMS_ERROR_OK Completed successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_tx_cfir_configure(adi_apollo_device_t *device, adi_apollo_sides_e side, adi_apollo_cfir_idx_e idx, adi_apollo_cfir_cfg_t *config); + +/** + * \brief Configures TX fsrc + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] side Device side, A or B \ref adi_apollo_sides_e + * \param[in] idx Index of block to configure (0 or 1) + * \param[in] config FSRC config parameters. \ref adi_apollo_fsrc_cfg_t + * \param[in] jrx_link_config JRX link config parameters. \ref adi_apollo_jesd_rx_link_cfg_t + * + * \return API_CMS_ERROR_OK Completed successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_tx_fsrc_configure(adi_apollo_device_t *device, adi_apollo_sides_e side, uint8_t idx, + adi_apollo_fsrc_cfg_t *config, adi_apollo_jesd_rx_link_cfg_t *jrx_link_config); + +/** + * \brief Configures TX misc (xbars, summer, low samp) + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] side Device side, A or B \ref adi_apollo_sides_e + * \param[in] config TX misc config parameters (xbars, summer, low samp) \ref adi_apollo_txpath_misc_t + * + * \return API_CMS_ERROR_OK Completed successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_tx_txpath_misc_configure(adi_apollo_device_t *device, adi_apollo_sides_e side, adi_apollo_txpath_misc_t *config); + +/** + * \brief Configures TX inv sinc + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] side Device side, A or B \ref adi_apollo_sides_e + * \param[in] idx Index of block to configure. \ref adi_apollo_cduc_path_idx_e + * \param[in] enable inverse since enable. 1 to enable, 0 to disable + * + * \return API_CMS_ERROR_OK Completed successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_tx_inv_sinc_configure(adi_apollo_device_t *device, adi_apollo_sides_e side, adi_apollo_cduc_path_idx_e idx, uint8_t enable); + + + +#ifndef CLIENT_IGNORE +/** + * \brief Configures TX/JRX rate matching with sample repeat if FSRC is not in use + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] side Device side, A or B \ref adi_apollo_sides_e + * \param[in] link_idx Link index. \ref adi_apollo_jesd_links_e + * \param[in] tx_path_config Tx path for side from device profile. \ref adi_apollo_txpath_t + * \param[in] jrx_config JRX link config parameters. \ref adi_apollo_jesd_rx_cfg_t + * + * \return API_CMS_ERROR_OK Completed successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_tx_sample_repeat_configure(adi_apollo_device_t *device, adi_apollo_sides_e side, + adi_apollo_jesd_links_e link_idx, adi_apollo_txpath_t *tx_path_config, adi_apollo_jesd_rx_cfg_t *jrx_config); +#endif /* CLIENT_IGNORE*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_TX_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_tx_types.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_tx_types.h new file mode 100644 index 00000000000000..cff3e33dce4678 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_tx_types.h @@ -0,0 +1,29 @@ +/*! + * \brief TX top level API type definition headers + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_TX + * @{ + */ +#ifndef __ADI_APOLLO_TX_TYPES_H__ +#define __ADI_APOLLO_TX_TYPES_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_cms_api_common.h" +#include "adi_apollo_common.h" +#include "apollo_cpu_device_profile_types.h" + +/*============= D E F I N E S ==============*/ + +/* Force idl-gen to pick up file */ +typedef uint8_t adi_apollo_tx_types_dummy; + +#endif /* __ADI_APOLLO_TX_TYPES_H__ */ + +/*! @} */ \ No newline at end of file diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_txen.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_txen.h new file mode 100644 index 00000000000000..9abb03396aced7 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_txen.h @@ -0,0 +1,130 @@ +/*! + * \brief TXEN Block definition headers + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_TXEN + * @{ + */ +#ifndef __ADI_APOLLO_TXEN_H__ +#define __ADI_APOLLO_TXEN_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_txen_types.h" + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Configure the txen block + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] tx_enables tx enable selections. \ref adi_apollo_txen_en_select_e + * \param[in] config Pointer to txen block config. \ref adi_apollo_txen_blk_config_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_txen_config_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t tx_enables, const adi_apollo_txen_blk_config_t *config); + +/** + * \brief Configures tx_pwrup_ctrl block + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] dacs DAC Selection. \ref adi_apollo_txen_dac_select_e + * \param[in] config Pointer to tx_pwrup_ctrl block paramaters. \ref adi_apollo_txen_pwrup_blk_config_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_txen_pwrup_ctrl_config_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t dacs, const adi_apollo_txen_pwrup_blk_config_t *config); + +/** + * \brief Configures tx_pwrup_ctrl reg + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] dacs DAC Selection. \ref adi_apollo_txen_dac_select_e + * \param[in] config Pointer to tx_pwrup_ctrl reg paramaters. \ref adi_apollo_txen_pwrup_ctrl_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_txen_pwrup_ctrl_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t dacs, const adi_apollo_txen_pwrup_ctrl_t *config); + +/** + * \brief Configures edges of dac_en, dig_en, pa_en signals + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] dacs DAC Selection. \ref adi_apollo_txen_dac_select_e + * \param[in] config Pointer to tx_pwrup_ctrl block paramaters. \ref adi_apollo_txen_pwrup_ctrl_edge_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_txen_pwrup_ctrl_edge_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t dacs, const adi_apollo_txen_pwrup_ctrl_edge_t *config); + +/** + * \brief Sets maximum programmed counter values + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] dacs DAC Selection. \ref adi_apollo_txen_dac_select_e + * \param[in] config Pointer to tx_pwrup_ctrl_count_set paramaters. \ref adi_apollo_txen_pwrup_ctrl_count_t + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_txen_pwrup_ctrl_count_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t dacs, const adi_apollo_txen_pwrup_ctrl_count_t *config); + +/** + * \brief Configures txen pin sel mapping + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] dacs DAC Selection. \ref adi_apollo_txen_dac_select_e + * \param[in] pin Powerup control enable pin select. \ref adi_apollo_puc_en_pin_sel_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_txen_pwrup_ctrl_pin_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t dacs, adi_apollo_puc_en_pin_sel_e pin); + +/** + * \brief Selects the txen clock rate + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] dacs DAC Selection. \ref adi_apollo_txen_dac_select_e + * \param[in] sel_cnt_rate clock rate. \ref adi_apollo_puc_clk_rate_sel_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_txen_pwrup_ctrl_sel_cnt_rate_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t dacs, uint8_t sel_cnt_rate); + +/** + * \brief Enable txen powerup control state machine + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] dacs DAC Selection. \ref adi_apollo_txen_dac_select_e + * \param[in] sm_en Enable or Disable State Machine. + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_txen_pwrup_ctrl_sm_en_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t dacs, uint8_t sm_en); + +#ifndef CLIENT_IGNORE + +#endif /* CLIENT_IGNORE*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_TXEN_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_txen_types.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_txen_types.h new file mode 100644 index 00000000000000..88a20f66fb0701 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_txen_types.h @@ -0,0 +1,138 @@ +/*! + * \brief TXEN Block definition headers + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_TXEN + * @{ + */ +#ifndef __ADI_APOLLO_TXEN_TYPES_H__ +#define __ADI_APOLLO_TXEN_TYPES_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_cms_api_common.h" +#include "adi_apollo_common.h" + +/*============= D E F I N E S ==============*/ + +#define ADI_APOLLO_NUM_TX_EN 8 /* Num of TX_EN pins */ +#define ADI_APOLLO_NUM_TX_EN_PER_SIDE 4 /* Num of TX_EN pins per side */ +#define ADI_APOLLO_NUM_TX_GAIN_PER_SIDE 4 +#define ADI_APOLLO_NUM_TX_SRD_PER_SIDE 4 +#define ADI_APOLLO_NUM_TX_INVSINC_PER_SIDE 4 + +/*! + * \brief Enumerates DAC Select + */ +typedef enum { + ADI_APOLLO_TXEN_DAC_NONE = 0x0, /*!< No DAC */ + ADI_APOLLO_TXEN_DAC_A0 = 0x1, /*!< DAC0 of SIDE A */ + ADI_APOLLO_TXEN_DAC_A1 = 0x2, /*!< DAC1 of SIDE A */ + ADI_APOLLO_TXEN_DAC_A2 = 0x4, /*!< DAC2 of SIDE A */ + ADI_APOLLO_TXEN_DAC_A3 = 0x8, /*!< DAC3 of SIDE A */ + ADI_APOLLO_TXEN_DAC_B0 = 0x10, /*!< DAC0 of SIDE B */ + ADI_APOLLO_TXEN_DAC_B1 = 0x20, /*!< DAC1 of SIDE B */ + ADI_APOLLO_TXEN_DAC_B2 = 0x40, /*!< DAC2 of SIDE B */ + ADI_APOLLO_TXEN_DAC_B3 = 0x80, /*!< DAC3 of SIDE B */ + ADI_APOLLO_TXEN_DAC_ALL = 0xFF /*!< ALL DACs */ +} adi_apollo_txen_dac_select_e; + +/*! +* \brief Tx enable pin polarity select +*/ +typedef enum { + ADI_APOLLO_TXEN_EN_ACTIVE_HIGH = 0, /*!< Polarity of respective Tx en is active high */ + ADI_APOLLO_TXEN_EN_ACTIVE_LOW = 1, /*!< Polarity of respective Tx en is active low */ +} adi_apollo_txen_en_polarity_e; + +/*! +* \brief Enumerates TX_EN pin select +*/ +typedef enum { + ADI_APOLLO_TX_EN_NONE = 0x00, /*!< No TX_EN pins */ + ADI_APOLLO_TX_EN_A0 = 0x01, /*!< TX_EN pin 0 of SIDE A */ + ADI_APOLLO_TX_EN_A1 = 0x02, /*!< TX_EN pin 1 of SIDE A */ + ADI_APOLLO_TX_EN_A2 = 0x04, /*!< TX_EN pin 2 of SIDE A */ + ADI_APOLLO_TX_EN_A3 = 0x08, /*!< TX_EN pin 3 of SIDE A */ + ADI_APOLLO_TX_EN_B0 = 0x10, /*!< TX_EN pin 0 of SIDE B */ + ADI_APOLLO_TX_EN_B1 = 0x20, /*!< TX_EN pin 1 of SIDE B */ + ADI_APOLLO_TX_EN_B2 = 0x40, /*!< TX_EN pin 2 of SIDE B */ + ADI_APOLLO_TX_EN_B3 = 0x80, /*!< TX_EN pin 3 of SIDE B */ + ADI_APOLLO_TX_EN_ALL = 0xFF, /*!< All TX_EN pins */ +} adi_apollo_txen_en_select_e; + +/*! + * \brief TxEN Block Config + */ +typedef struct { + adi_apollo_txen_en_polarity_e enable_polarity; + uint8_t spi_en; + uint8_t spien_en; + uint16_t slice_sel; + uint8_t linx_sel; + uint16_t pfilt_sel; + uint16_t cduc_sel; + uint16_t fduc_sel; + uint8_t cfir_sel; + uint8_t fsrc_sel; + uint16_t jrx_link_sel; + uint16_t jrx_phy_sel_side_a; /*!< JRX phy lane bit-wise select side a */ + uint16_t jrx_phy_sel_side_b; /*!< JRX phy lane bit-wise select side b */ + uint8_t modsw_sel; + uint8_t invsinc_sel; + uint8_t gain_sel; + uint8_t srd_sel; + +} adi_apollo_txen_blk_config_t; + +/*! +* \brief TxEN powerup control SPI +*/ +typedef struct { + uint8_t sm_en; /*!< 0: State machine bypassed. (dac_stdby, dig_en and pa_en follow TxEN), 1: Edge control state machine enabled. */ + uint8_t spi_txen_en; /*!< 0: Use the TxEN input signal, 1: Ignore TxEN input signal and use input from SPI control */ + uint8_t spi_txen; /*!< 0: Tx blocks gated off/standby, 1:TRX blocks are enabled (spi_txen_en must be enabled to use this control) */ + adi_apollo_puc_clk_rate_sel_e sm_clk_rate; /*!< Select clock rate of state machine counters. */ +} adi_apollo_txen_pwrup_ctrl_t; + +/*! +* \brief TxEN powerup control edges +*/ +typedef struct { + adi_apollo_puc_edge_rise_sel_e dac_rise; /*!< dac enable to rise after TxEN rise. (\ref adi_apollo_puc_edge_rise_sel_e) */ + adi_apollo_puc_edge_fall_sel_e dac_fall; /*!< dac enable to fall after TxEN fall. (\ref adi_apollo_puc_edge_fall_sel_e) */ + adi_apollo_puc_edge_rise_sel_e dig_rise; /*!< dig block enable to rise after TxEN rise. (\ref adi_apollo_puc_edge_rise_sel_e) */ + adi_apollo_puc_edge_fall_sel_e dig_fall; /*!< dig block enable to fall after TxEN fall. (\ref adi_apollo_puc_edge_fall_sel_e) */ + adi_apollo_puc_edge_rise_sel_e pa_rise; /*!< PA enable to rise after TxEN rise. (\ref adi_apollo_puc_edge_rise_sel_e) */ + adi_apollo_puc_edge_fall_sel_e pa_fall; /*!< PA enable to fall after TxEN fall. (\ref adi_apollo_puc_edge_fall_sel_e) */ +} adi_apollo_txen_pwrup_ctrl_edge_t; + +/*! +* \brief TxEN powerup control counters +*/ +typedef struct { + uint8_t count_maxa; /*!< Maximum programmed counter value from E0 to E1 (Fs/32 per count) */ + uint8_t count_maxb; /*!< Maximum programmed counter value from E1 to E2 (Fs/32 per count) */ + uint8_t count_maxc; /*!< Maximum programmed counter value from E2 to E3 (Fs/32 per count) */ + uint8_t count_maxd; /*!< Maximum programmed counter value from E4 to E5 (Fs/32 per count) */ + uint8_t count_maxe; /*!< Maximum programmed counter value from E5 to E6 (Fs/32 per count) */ + uint8_t count_maxf; /*!< Maximum programmed counter value from E6 to E7 (Fs/32 per count) */ +} adi_apollo_txen_pwrup_ctrl_count_t; + +/*! +* \brief TxEN powerup control block configuration +*/ +typedef struct { + adi_apollo_txen_pwrup_ctrl_t ctrl; + adi_apollo_txen_pwrup_ctrl_edge_t edge; + adi_apollo_txen_pwrup_ctrl_count_t count; + adi_apollo_puc_en_pin_sel_e pin_en; /*!< Select which enable pin from CONV_POW_ONOFF is used as TXEN_POWER_CTRL input. */ +} adi_apollo_txen_pwrup_blk_config_t; + +#endif /* __ADI_APOLLO_TXEN_TYPES_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_txmisc.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_txmisc.h new file mode 100644 index 00000000000000..5f2cbbb0ed50eb --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_txmisc.h @@ -0,0 +1,82 @@ +/*! + * \brief Tx Misc functional block API prototypes + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_TXMISC + * @{ + */ +#ifndef __ADI_APOLLO_TXMISC_H__ +#define __ADI_APOLLO_TXMISC_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_txmisc_types.h" + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Sets low sampling tx mode + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] side_sel Target side \ref adi_apollo_side_select_e + * \param[in] low_samp_en 1: low sampling enabled 0: low sampling disabled + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_txmisc_low_samp_set(adi_apollo_device_t *device, adi_apollo_side_select_e side_sel, uint8_t low_samp_en); + +/** + * \brief Tx datapath (DP) reset. + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] side_sel Target side \ref adi_apollo_side_select_e + * \param[in] reset_en 0: clears the dayapath reset. 1: set DP reset + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_txmisc_dp_reset(adi_apollo_device_t *device, adi_apollo_side_select_e side_sel, uint8_t reset_en); + +/** + * \brief Enables/disables CDUC dac + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] cducs Coarse DUC selection. ADI_APOLLO_CDUC_A0, _A0 to _A3, _B0 to _B3, _ALL \ref adi_apollo_cduc_select_e + * \param[in] enable Enable CDUC dac. 1 to enable, 0 to disable + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_txmisc_cduc_dac_enable_set(adi_apollo_device_t *device, const uint16_t cducs, const uint8_t enable); + +/** + * \brief Inspect TX crossbars and low sample enable + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] side Target side \ref adi_apollo_side_select_e + * \param[out] txmisc_inspect Pointer to tx path inspect struct \ref adi_apollo_txpath_inspect_t + * + * \return API_CMS_ERROR_OK Completed successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_txmisc_inspect(adi_apollo_device_t *device, uint16_t side, adi_apollo_txmisc_inspect_t *txmisc_inspect); + +#ifndef CLIENT_IGNORE + +#endif /* CLIENT_IGNORE */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_TXMISC_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_txmisc_types.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_txmisc_types.h new file mode 100644 index 00000000000000..15eb92709a0643 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_txmisc_types.h @@ -0,0 +1,33 @@ +/*! + * \brief Tx Misc functional block definitions + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_TXMISC + * @{ + */ +#ifndef __ADI_APOLLO_TXMISC_TYPES_H__ +#define __ADI_APOLLO_TXMISC_TYPES_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_cms_api_common.h" +#include "adi_apollo_common.h" + +/*============= D E F I N E S ==============*/ +#define ADI_APOLLO_TX_MISC_REGMAP_NUM 2 + +/*! +* \brief tx path inspect param +*/ +typedef struct { + adi_apollo_txpath_misc_t dp; /*!< Parameters defined from device profile \ref apollo_cpu_device_profile_types.h */ +} adi_apollo_txmisc_inspect_t; + + +#endif /* __ADI_APOLLO_TXMISC_TYPES_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_txmux.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_txmux.h new file mode 100644 index 00000000000000..ce39ebbaa9b41c --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_txmux.h @@ -0,0 +1,107 @@ +/*! + * \brief TX MUX Block definition headers + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_TXMUX + * @{ + */ +#ifndef __ADI_APOLLO_TXMUX_H__ +#define __ADI_APOLLO_TXMUX_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_txmux_types.h" + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * \brief Sets the fine DUC to summer/coarse DUC connection path + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] summers Tx path summer selection, bitwise-or. ADI_APOLLO_TX_SUMMER_A0, A1, ... A4, ADI_APOLLO_TX_SUMMER_B0, B1, ... B4 (A3-A4, B3-B4 for 8T8R) \ref adi_apollo_summer_select_e + * \param[in] fducs_connected FDUCs connected to the summers, bitwise-or. ADI_APOLLO_FDUC_A0, A1, ... A7, ADI_APOLLO_FDUC_B0, B1, ... B7 (A4-A7, B4-B7 for 8T8R) + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_txmux_summer_block_set(adi_apollo_device_t *device, const uint16_t summers, const uint16_t fducs_connected); + +/** + * \brief Sets HSDOUT MUX path + * + * Array index selects DAC (both 4T4R and 8T8R) + * dac[0] DAC-A0 + * dac[1] DAC-A1 + * dac[2] DAC-A2 + * dac[3] DAC-A3 + * + * Values (4T4R) + * 0 Slice 0-x (e.g. CDUC-A0) + * 1 Slice 1-x (e.g. CDUC-A1) + * 2 0s + * 2 0s + * + * Values (8T8R) + * 0 Slice 0-0 (e.g. CDUC-A0) + * 1 Slice 0-1 (e.g. CDUC-A2) + * 2 Slice 1-0 (e.g. CDUC-A1) + * 2 Slice 1-1 (e.g. CDUC-A3) + * + * Same applies to side B + * + * + * Example Usage (8T8R) + * + * // Mux CDUC outputs to DAC - A0 + * uint8_t dac_to_cduc0[] = {0, 1, 2, 3}; // DAC-A0 => CDUC-A0 + * adi_apollo_txmux_hsdout_set(device, ADI_APOLLO_SIDE_A, dac_to_cduc0, 4); + * + * uint8_t dac_to_cduc1[] = {1, 1, 2, 3}; // DAC-A0 => CDUC-A2 + * adi_apollo_txmux_hsdout_set(device, ADI_APOLLO_SIDE_A, dac_to_cduc1, 4); + * + * uint8_t dac_to_cduc2[] = {2, 1, 2, 3}; // DAC-A0 => CDUC-A1 + * adi_apollo_txmux_hsdout_set(device, ADI_APOLLO_SIDE_A, dac_to_cduc2, 4); + * + * uint8_t dac_to_cduc3[] = {3, 1, 2, 3}; // DAC-A0 => CDUC-A3 + * adi_apollo_txmux_hsdout_set(device, ADI_APOLLO_SIDE_A, dac_to_cduc3, 4); + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] side_sel Device side(s) to set HSDOUT \ref adi_apollo_side_select_e. + * \param[in] dac Array indices are DAC index for a side (0-3) and values are corresponding HSDOUT xbar input channels(0-3) to be connected + * \param[in] length Length of the dac array, max value ADI_APOLLO_NUM_DAC + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_txmux_hsdout_set(adi_apollo_device_t *device, adi_apollo_side_select_e side_sel, const uint8_t dac[], const uint32_t length); + +/** + * \brief Sets the modulator switch (MODSW) + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] side_sel Device side(s) to set MODSW \ref adi_apollo_side_select_e + * \param[in] modsw0 Modulator switch configuration \ref adi_apollo_modsw_select_e + * \param[in] modsw1 Modulator switch configuration (for 8T8R only) \ref adi_apollo_modsw_select_e + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_txmux_modsw_set(adi_apollo_device_t *device, adi_apollo_side_select_e side_sel, adi_apollo_modsw_select_e modsw0, adi_apollo_modsw_select_e modsw1); + +#ifndef CLIENT_IGNORE + +#endif /* CLIENT_IGNORE*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_TXMUX_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_txmux_types.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_txmux_types.h new file mode 100644 index 00000000000000..3fe3611ee29b3d --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_txmux_types.h @@ -0,0 +1,56 @@ +/*! + * \brief TX MUX Block definition headers + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_TXMUX + * @{ + */ +#ifndef __ADI_APOLLO_TXMUX_TYPES_H__ +#define __ADI_APOLLO_TXMUX_TYPES_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_cms_api_common.h" +#include "adi_apollo_common.h" + +/*============= D E F I N E S ==============*/ +#define ADI_APOLLO_TX_SUMMER_NUM 8 +#define ADI_APOLLO_TX_SUMMER_PER_SIDE_NUM 4 +#define ADI_APOLLO_NUM_DAC 8 /* Num of DACs */ +#define ADI_APOLLO_NUM_DAC_PER_SIDE 4 /* Num of DACs per side */ +#define ADI_APOLLO_NUM_INVSINC 8 + +/** + * \brief Enumerates Tx summer select + */ +typedef enum { + ADI_APOLLO_TX_SUMMER_NONE = 0x00, /*!< No Tx summer */ + ADI_APOLLO_TX_SUMMER_A0 = 0x01, /*!< Summer 0 of SIDE A */ + ADI_APOLLO_TX_SUMMER_A1 = 0x02, /*!< Summer 1 of SIDE A */ + ADI_APOLLO_TX_SUMMER_A2 = 0x04, /*!< Summer 2 of SIDE A */ + ADI_APOLLO_TX_SUMMER_A3 = 0x08, /*!< Summer 3 of SIDE A */ + ADI_APOLLO_TX_SUMMER_B0 = 0x10, /*!< Summer 0 of SIDE B */ + ADI_APOLLO_TX_SUMMER_B1 = 0x20, /*!< Summer 1 of SIDE B */ + ADI_APOLLO_TX_SUMMER_B2 = 0x40, /*!< Summer 2 of SIDE B */ + ADI_APOLLO_TX_SUMMER_B3 = 0x80, /*!< Summer 3 of SIDE B */ + ADI_APOLLO_TX_SUMMER_ALL = 0xFF, /*!< All Tx Summers */ + ADI_APOLLO_TX_SUMMER_ALL_4T4R = 0x33 /*!< All Tx Summers (4T4R) */ +} adi_apollo_summer_select_e; + +/** + * \brief Enumerates the MODSW configuration options + */ +typedef enum { + ADI_APOLLO_MODSW_0 = 0x00, /*!< DAC0 = CDUC_A0 I, DAC1 = CDUC_A1 I */ + ADI_APOLLO_MODSW_1 = 0x01, /*!< DAC0 = CDUC_A0 I + CDUC_A1 I, DAC1 = CDUC_A0 Q + CDUC_A1 Q */ + ADI_APOLLO_MODSW_2 = 0x02, /*!< DAC0 = CDUC_A0 I, DAC1 = CDUC_A0 Q */ + ADI_APOLLO_MODSW_3 = 0x03 /*!< DAC0 = CDUC_A1 I, DAC1 = CDUC_A1 Q */ +} adi_apollo_modsw_select_e; + +#endif /* __ADI_APOLLO_TXMUX_TYPES_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_types.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_types.h new file mode 100644 index 00000000000000..f29db02f7ad00f --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_types.h @@ -0,0 +1,69 @@ +/*! + * \brief API header file + * This file contains all the publicly exposed methods and data + * structures to interface with API. + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_TYPES + * @{ + */ +#ifndef __ADI_APOLLO_TYPES_H__ +#define __ADI_APOLLO_TYPES_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_cms_api_common.h" +#include "adi_apollo_config.h" +#include "adi_apollo_common.h" +#include "adi_apollo_adc.h" +#include "adi_apollo_dac.h" +#include "adi_apollo_arm.h" +#include "adi_apollo_device.h" +#include "adi_apollo_clk_mcs.h" +#include "adi_apollo_jrx.h" +#include "adi_apollo_jtx.h" +#include "adi_apollo_serdes.h" +#include "adi_apollo_hal.h" +#include "adi_apollo_tmode.h" +#include "adi_apollo_gpio.h" +#include "adi_apollo_bmem.h" +#include "adi_apollo_pfilt.h" +#include "adi_apollo_cfir.h" +#include "adi_apollo_fsrc.h" +#include "adi_apollo_cddc.h" +#include "adi_apollo_fddc.h" +#include "adi_apollo_fduc.h" +#include "adi_apollo_cduc.h" +#include "adi_apollo_dformat.h" +#include "adi_apollo_rxmux.h" +#include "adi_apollo_rxmisc.h" +#include "adi_apollo_cnco.h" +#include "adi_apollo_fnco.h" +#include "adi_apollo_smon.h" +#include "adi_apollo_rxen.h" +#include "adi_apollo_startup.h" +#include "adi_apollo_trigts.h" +#include "adi_apollo_txen.h" +#include "adi_apollo_txmisc.h" +#include "adi_apollo_reconfig.h" +#include "adi_apollo_txmux.h" +#include "adi_apollo_mailbox.h" +#include "adi_apollo_mailbox_handler.h" +#include "adi_apollo_cfg.h" +#include "adi_apollo_rx.h" +#include "adi_apollo_tx.h" +#include "adi_apollo_invsinc.h" +#include "adi_apollo_sniffer.h" +#include "adi_apollo_sysclk_cond.h" +#include "apollo_cpu_device_profile_types.h" +#include "adi_apollo_mcs_cal.h" +#include "adi_apollo_gpio_hop_types.h" +#include "adi_apollo_loopback.h" + +#endif /* __ADI_APOLLO_TYPES_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_user.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_user.h new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_utils.h b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_utils.h new file mode 100644 index 00000000000000..43c70f694e42b2 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/adi_apollo_utils.h @@ -0,0 +1,59 @@ +/*! + * \brief Apollo API utilities + * + * \copyright copyright(c) 2023 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_UTILS + * @{ + */ +#ifndef __ADI_APOLLO_UTILS_H__ +#define __ADI_APOLLO_UTILS_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_types.h" + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Get the side select for selected adcs + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] adc_select Target adcs \ref adi_apollo_adc_select_e + * \param[out] side_select Target sides \ref adi_apollo_side_select_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_utils_side_from_adc_select_get(adi_apollo_device_t *device, uint16_t adc_select, uint16_t *side_select); + +/** + * \brief Get the side select for selected dacs + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] dac_select Target dacs \ref adi_apollo_dac_select_e + * \param[out] side_select Target sides \ref adi_apollo_side_select_e + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_utils_side_from_dac_select_get(adi_apollo_device_t *device, uint16_t dac_select, uint16_t *side_select); + + +#ifndef CLIENT_IGNORE + +#endif /* CLIENT_IGNORE */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_UTILS_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/inc/apollo_cpu_device_profile_types.h b/drivers/iio/trx-rf/ad9088/public/inc/apollo_cpu_device_profile_types.h new file mode 100644 index 00000000000000..f8f8ff2c5731d9 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/inc/apollo_cpu_device_profile_types.h @@ -0,0 +1,2439 @@ +/** + * \file apollo_cpu_device_profile_types.h + * \brief Device profile for Apollo API + * \copyright Analog Devices Inc. 2021. All rights reserved. + * Released under the APOLLO API license, for more information see "LICENSE.txt" in the SDK + */ + +#ifndef __APOLLO_CPU_DEVICE_PROFILE_TYPES_H__ +#define __APOLLO_CPU_DEVICE_PROFILE_TYPES_H__ + +#ifdef __KERNEL__ +#include +#else +#include +#include +#endif +#include "adi_apollo_platform_pack.h" + +#define ADI_APOLLO_PROFILE_VERSION_MAJOR 10 /*!< Major */ +#define ADI_APOLLO_PROFILE_VERSION_MINOR 1 /*!< Minor */ +#define ADI_APOLLO_PROFILE_VERSION_PATCH 2 /*!< Patch */ + +#define ADI_APOLLO_DACS_PER_SIDE 4 /*!< #DACs per side. */ +#define ADI_APOLLO_ADCS_PER_SIDE 4 /*!< #Max ADCs per side. (8T8R) */ +#define ADI_APOLLO_4T4R_ADCS_PER_SIDE 2 /*!< #ADCs per side. (4T4R) */ +#define ADI_APOLLO_4T4R_ADCS_TOTAL 4 /*!< #ADCs total. (4T4R) */ +#define ADI_APOLLO_NUM_NCOS_PER_DRC 2 /*!< #NCOs per DRC. */ +#define ADI_APOLLO_PFILT_COEFFS 32 /*!< #coefficients for a programmable filter. */ +#define ADI_APOLLO_CFIR_NUM_TAPS 16 +#define ADI_APOLLO_CNCO_PROFILE_NUM 16 /*!< # of tuning profiles per CNCO */ +#define ADI_APOLLO_FNCO_PROFILE_NUM 32 /*!< # of tuning profiles per FNCO */ +#define ADI_APOLLO_DAC_DIG_SLICE_PER_SIDE 2 +#define ADI_APOLLO_NUM_ADF4382_GPIOS 2 /*!< # of gpios to control ext ADF4382s */ +#define ADI_APOLLO_MAX_NUM_ADF4382 2 /*!< Max # of ADF4382 that can be connected */ +#define ADI_APOLLO_NUM_GPIOS 51 /*!< # of GPIOs for Apollo */ + +#define ADI_APOLLO_PROFILE_TX_CHAN_MASK (0x000000FFU) +#define ADI_APOLLO_PROFILE_TX_CHAN_POS (0U) + +#define ADI_APOLLO_PROFILE_RX_CHAN_MASK (0x000000FFU) +#define ADI_APOLLO_PROFILE_RX_CHAN_POS (0U) +#define ADI_APOLLO_NUM_TXRX_CHAN 8 + +#ifndef ADI_APOLLO_PACK_ENUM +#ifdef __GNUC__ +#define ADI_APOLLO_PACK_ENUM __attribute__((packed)) +#else +#define ADI_APOLLO_PACK_ENUM +#endif +#endif + + +/** + * \brief Apollo Side Enumeration + */ +typedef enum adi_apollo_sides { + ADI_APOLLO_SIDE_IDX_A = 0u, /*!< Apollo A Side */ + ADI_APOLLO_SIDE_IDX_B = 1u, /*!< Apollo B Side */ + ADI_APOLLO_NUM_SIDES = 2u /*!< Number of Apollo Sides */ +} ADI_APOLLO_PACK_ENUM adi_apollo_sides_e; + + +/** + * \brief Apollo Per Side Link Enumeration + */ +typedef enum adi_apollo_jesd_links { + ADI_APOLLO_JESD_LINK_0 = 0u, /*!< Apollo Link 0 */ + ADI_APOLLO_JESD_LINK_1 = 1u, /*!< Apollo Link 1 */ + ADI_APOLLO_JESD_LINKS = 2u /*!< Number of Apollo Links Per Side */ +} ADI_APOLLO_PACK_ENUM adi_apollo_jesd_links_e; + + +/** + * \brief RX Channel Enumeration + */ +typedef enum adi_apollo_rx_channel_num { + ADI_APOLLO_RX_CH_A0 = 0u, /*!< RX Channel A0 */ + ADI_APOLLO_RX_CH_A1 = 1u, /*!< RX Channel A1 */ + ADI_APOLLO_RX_CH_A2 = 2u, /*!< RX Channel A2 */ + ADI_APOLLO_RX_CH_A3 = 3u, /*!< RX Channel A3 */ + ADI_APOLLO_RX_CH_B0 = 4u, /*!< RX Channel B0 */ + ADI_APOLLO_RX_CH_B1 = 5u, /*!< RX Channel B1 */ + ADI_APOLLO_RX_CH_B2 = 6u, /*!< RX Channel B2 */ + ADI_APOLLO_RX_CH_B3 = 7u, /*!< RX Channel B3 */ + ADI_APOLLO_RX_CH_MAX = 7u, /*!< RX Channel Max Count */ + ADI_APOLLO_RX_CH_LEN = 8u /*!< RX Channel Length for Arrays */ +} ADI_APOLLO_PACK_ENUM adi_apollo_rx_channel_num_e; + + +/** + * \brief TX Channel Enumeration + */ +typedef enum adi_apollo_tx_channel_num { + ADI_APOLLO_TX_CH_A0 = 0u, /*!< TX Channel A0 */ + ADI_APOLLO_TX_CH_A1 = 1u, /*!< TX Channel A1 */ + ADI_APOLLO_TX_CH_A2 = 2u, /*!< TX Channel A2 */ + ADI_APOLLO_TX_CH_A3 = 3u, /*!< TX Channel A3 */ + ADI_APOLLO_TX_CH_B0 = 4u, /*!< TX Channel B0 */ + ADI_APOLLO_TX_CH_B1 = 5u, /*!< TX Channel B1 */ + ADI_APOLLO_TX_CH_B2 = 6u, /*!< TX Channel B2 */ + ADI_APOLLO_TX_CH_B3 = 7u, /*!< TX Channel B3 */ + ADI_APOLLO_TX_CH_MAX = 7u, /*!< TX Channel Max Count */ + ADI_APOLLO_TX_CH_LEN = 8u /*!< TX Channel Length for Arrays */ +} ADI_APOLLO_PACK_ENUM adi_apollo_tx_channel_num_e; + + +/** + * \brief Coarse Digital Down Converter Index Enumeration + */ +typedef enum adi_apollo_cddc_idx { + ADI_APOLLO_CDDC_IDX_0 = 0u, /*!< CDDC Index 0 */ + ADI_APOLLO_CDDC_IDX_1 = 1u, /*!< CDDC Index 1 */ + ADI_APOLLO_CDDCS_PER_SIDE = 2u /*!< CDDC Indices Per Side */ +} ADI_APOLLO_PACK_ENUM adi_apollo_cddc_idx_e; + + +/** + * \brief Coarse Digital Down Converter Path Index Enumeration + */ +typedef enum adi_apollo_cddc_path_idx { + ADI_APOLLO_CDDC_PATH_IDX_0 = 0u, /*!< CDDC Path Index 0 */ + ADI_APOLLO_CDDC_PATH_IDX_1 = 1u, /*!< CDDC Path Index 1 */ + ADI_APOLLO_CDDC_PATH_IDX_2 = 2u, /*!< CDDC Path Index 2 */ + ADI_APOLLO_CDDC_PATH_IDX_3 = 3u, /*!< CDDC Path Index 3 */ + ADI_APOLLO_CDDC_PATHS_PER_SIDE = 4u /*!< CDDC Path Indices Per Side */ +} ADI_APOLLO_PACK_ENUM adi_apollo_cddc_path_idx_e; + + +/** + * \brief Fine Digital Down Converter Index Enumeration + */ +typedef enum adi_apollo_fddc_idx { + ADI_APOLLO_FDDC_IDX_0 = 0u, /*!< FDDC Index 0 */ + ADI_APOLLO_FDDC_IDX_1 = 1u, /*!< FDDC Index 1 */ + ADI_APOLLO_FDDC_IDX_2 = 2u, /*!< FDDC Index 2 */ + ADI_APOLLO_FDDC_IDX_3 = 3u, /*!< FDDC Index 3 */ + ADI_APOLLO_FDDCS_PER_SIDE = 4u /*!< FDDC Indices Per Side */ +} ADI_APOLLO_PACK_ENUM adi_apollo_fddc_idx_e; + + +/** + * \brief Fine Digital Down Converter Path Index Enumeration + */ +typedef enum adi_apollo_fddc_path_idx { + ADI_APOLLO_FDDC_PATH_IDX_0 = 0u, /*!< FDDC Path Index 0 */ + ADI_APOLLO_FDDC_PATH_IDX_1 = 1u, /*!< FDDC Path Index 1 */ + ADI_APOLLO_FDDC_PATH_IDX_2 = 2u, /*!< FDDC Path Index 2 */ + ADI_APOLLO_FDDC_PATH_IDX_3 = 3u, /*!< FDDC Path Index 3 */ + ADI_APOLLO_FDDC_PATH_IDX_4 = 4u, /*!< FDDC Path Index 4 */ + ADI_APOLLO_FDDC_PATH_IDX_5 = 5u, /*!< FDDC Path Index 5 */ + ADI_APOLLO_FDDC_PATH_IDX_6 = 6u, /*!< FDDC Path Index 6 */ + ADI_APOLLO_FDDC_PATH_IDX_7 = 7u, /*!< FDDC Path Index 7 */ + ADI_APOLLO_FDDC_PATHS_PER_SIDE = 8u /*!< FDDC Path Indices Per Side */ +} ADI_APOLLO_PACK_ENUM adi_apollo_fddc_path_idx_e; + + +/** + * \brief Buffer Memory Index Enumeration + */ +typedef enum adi_apollo_bmem_idx { + ADI_APOLLO_BMEM_IDX_0 = 0u, /*!< BMEM Index 0 */ + ADI_APOLLO_BMEM_IDX_1 = 1u, /*!< BMEM Index 1 */ + ADI_APOLLO_BMEM_IDX_2 = 2u, /*!< BMEM Index 2 */ + ADI_APOLLO_BMEM_IDX_3 = 3u, /*!< BMEM Index 3 */ + ADI_APOLLO_BMEM_IDX_4 = 4u, /*!< BMEM Index 4 */ + ADI_APOLLO_BMEM_IDX_5 = 5u, /*!< BMEM Index 5 */ + ADI_APOLLO_BMEMS_PER_SIDE = 6u /*!< BMEM Indices Per Side */ +} ADI_APOLLO_PACK_ENUM adi_apollo_bmem_idx_e; + + +/** + * \brief Coarse Digital Up Converter Index Enumeration + */ +typedef enum adi_apollo_cduc_idx { + ADI_APOLLO_CDUC_IDX_0 = 0u, /*!< CDUC Index 0 */ + ADI_APOLLO_CDUC_IDX_1 = 1u, /*!< CDUC Index 1 */ + ADI_APOLLO_CDUCS_PER_SIDE = 2u /*!< CDUC Indices Per Side */ +} ADI_APOLLO_PACK_ENUM adi_apollo_cduc_idx_e; + + +/** + * \brief Coarse Digital Up Converter Path Index Enumeration + */ +typedef enum adi_apollo_cduc_path_idx { + ADI_APOLLO_CDUC_PATH_IDX_0 = 0u, /*!< CDUC Path Index 0 */ + ADI_APOLLO_CDUC_PATH_IDX_1 = 1u, /*!< CDUC Path Index 1 */ + ADI_APOLLO_CDUC_PATH_IDX_2 = 2u, /*!< CDUC Path Index 2 */ + ADI_APOLLO_CDUC_PATH_IDX_3 = 3u, /*!< CDUC Path Index 3 */ + ADI_APOLLO_CDUC_PATHS_PER_SIDE = 4u /*!< CDUC Path Indices Per Side */ +} ADI_APOLLO_PACK_ENUM adi_apollo_cduc_path_idx_e; + + +/** + * \brief Fine Digital Up Converter Index Enumeration + */ +typedef enum adi_apollo_fduc_idx { + ADI_APOLLO_FDUC_IDX_0 = 0u, /*!< FDUC Index 0 */ + ADI_APOLLO_FDUC_IDX_1 = 1u, /*!< FDUC Index 1 */ + ADI_APOLLO_FDUC_IDX_2 = 2u, /*!< FDUC Index 2 */ + ADI_APOLLO_FDUC_IDX_3 = 3u, /*!< FDUC Index 3 */ + ADI_APOLLO_FDUCS_PER_SIDE = 4u /*!< FDUC Indices Per Side */ +} ADI_APOLLO_PACK_ENUM adi_apollo_fduc_idx_e; + + +/** + * \brief Fine Digital Up Converter Path Index Enumeration + */ +typedef enum adi_apollo_fduc_path_idx { + ADI_APOLLO_FDUC_PATH_IDX_0 = 0u, /*!< FDUC Path Index 0 */ + ADI_APOLLO_FDUC_PATH_IDX_1 = 1u, /*!< FDUC Path Index 1 */ + ADI_APOLLO_FDUC_PATH_IDX_2 = 2u, /*!< FDUC Path Index 2 */ + ADI_APOLLO_FDUC_PATH_IDX_3 = 3u, /*!< FDUC Path Index 3 */ + ADI_APOLLO_FDUC_PATH_IDX_4 = 4u, /*!< FDUC Path Index 4 */ + ADI_APOLLO_FDUC_PATH_IDX_5 = 5u, /*!< FDUC Path Index 5 */ + ADI_APOLLO_FDUC_PATH_IDX_6 = 6u, /*!< FDUC Path Index 6 */ + ADI_APOLLO_FDUC_PATH_IDX_7 = 7u, /*!< FDUC Path Index 7 */ + ADI_APOLLO_FDUC_PATHS_PER_SIDE = 8u /*!< FDUC Path Indices Per Side */ +} ADI_APOLLO_PACK_ENUM adi_apollo_fduc_path_idx_e; + + +/** + * \brief Programmable Filter Index Enumeration + */ +typedef enum adi_apollo_pfilt_idx { + ADI_APOLLO_PFILT_IDX_0 = 0u, /*!< PFILT Index 0 */ + ADI_APOLLO_PFILTS_PER_SIDE = 1u /*!< PFILT Indices Per Side */ +} ADI_APOLLO_PACK_ENUM adi_apollo_pfilt_idx_e; + + +/** + * \brief Complex Filter Index Enumeration + */ +typedef enum adi_apollo_cfir_idx { + ADI_APOLLO_CFIR_IDX_0 = 0u, /*!< CFIR Index 0 */ + ADI_APOLLO_CFIR_IDX_1 = 1u, /*!< CFIR Index 1 */ + ADI_APOLLO_CFIRS_PER_SIDE = 2u /*!< CFIR Indices Per Side */ +} ADI_APOLLO_PACK_ENUM adi_apollo_cfir_idx_e; + + +/** + * \brief Signal Monitor Index Enumeration + */ +typedef enum adi_apollo_smon_idx { + ADI_APOLLO_SMON_IDX_0 = 0u, /*!< SMON Index 0 */ + ADI_APOLLO_SMON_IDX_1 = 1u, /*!< SMON Index 1 */ + ADI_APOLLO_SMON_IDX_2 = 2u, /*!< SMON Index 2 */ + ADI_APOLLO_SMON_IDX_3 = 3u, /*!< SMON Index 3 */ + ADI_APOLLO_SMONS_PER_SIDE = 4u /*!< SMON Indices Per Side */ +} ADI_APOLLO_PACK_ENUM adi_apollo_smon_idx_e; + + +/** + * \brief RX/TX Enable Index Enumeration + */ +typedef enum adi_apollo_rxtx_enable_idx { + ADI_APOLLO_RXTX_ENABLE_IDX_0 = 0u, /*!< RXTX En Index 0 */ + ADI_APOLLO_RXTX_ENABLE_IDX_1 = 1u, /*!< RXTX En Index 1 */ + ADI_APOLLO_RXTX_ENABLE_IDX_2 = 2u, /*!< RXTX En Index 2 */ + ADI_APOLLO_RXTX_ENABLE_IDX_3 = 3u, /*!< RXTX En Index 3 */ + ADI_APOLLO_RXTX_ENABLES_PER_SIDE = 4u /*!< RXTX En Indices Per Side */ +} ADI_APOLLO_PACK_ENUM adi_apollo_rxtx_enable_idx_e; + + +/** + * \brief RX/TX Power Enable Index Enumeration + */ +typedef enum adi_apollo_rxtx_enable_pwr_idx { + ADI_APOLLO_RXTX_POWER_CTRL_IDX_0 = 0u, /*!< RXTX Power En Index 0 */ + ADI_APOLLO_RXTX_POWER_CTRL_IDX_1 = 1u, /*!< RXTX Power En Index 1 */ + ADI_APOLLO_RXTX_POWER_CTRL_IDX_2 = 2u, /*!< RXTX Power En Index 2 */ + ADI_APOLLO_RXTX_POWER_CTRL_IDX_3 = 3u, /*!< RXTX Power En Index 3 */ + ADI_APOLLO_RXTX_POWER_CTRL_IDX_4 = 4u, /*!< RXTX Power En Index 4 */ + ADI_APOLLO_RXTX_POWER_CTRL_IDX_5 = 5u, /*!< RXTX Power En Index 5 */ + ADI_APOLLO_RXTX_POWER_CTRL_IDX_6 = 6u, /*!< RXTX Power En Index 6 */ + ADI_APOLLO_RXTX_POWER_CTRL_IDX_7 = 7u, /*!< RXTX Power En Index 7 */ + ADI_APOLLO_RXTX_POWER_CTRL_PER_SIDE = 8u /*!< RXTX Power En Indices Per Side */ +} ADI_APOLLO_PACK_ENUM adi_apollo_rxtx_enable_pwr_idx_e; + + +#define ADI_APOLLO_JESD_MAX_LANES_PER_SIDE (12u) +#define ADI_APOLLO_JESD_MAX_SAMPLE_XBAR_IDXS (96u) +#define ADI_APOLLO_JESD_MAX_CONV_XBAR_IDXS (16u) + + +/** + * \brief SerDes Lane Enumeration. Used for both JRx and JTx PHY Lanes. + */ +typedef enum adi_apollo_serdes_lane_num { + ADI_APOLLO_SERDES_LANE_0 = 0u, /*!< SerDes Lane #0 Index */ + ADI_APOLLO_SERDES_LANE_1 = 1u, /*!< SerDes Lane #1 Index */ + ADI_APOLLO_SERDES_LANE_2 = 2u, /*!< SerDes Lane #2 Index */ + ADI_APOLLO_SERDES_LANE_3 = 3u, /*!< SerDes Lane #3 Index */ + ADI_APOLLO_SERDES_LANE_4 = 4u, /*!< SerDes Lane #4 Index */ + ADI_APOLLO_SERDES_LANE_5 = 5u, /*!< SerDes Lane #5 Index */ + ADI_APOLLO_SERDES_LANE_6 = 6u, /*!< SerDes Lane #6 Index */ + ADI_APOLLO_SERDES_LANE_7 = 7u, /*!< SerDes Lane #7 Index */ + ADI_APOLLO_SERDES_LANE_8 = 8u, /*!< SerDes Lane #8 Index */ + ADI_APOLLO_SERDES_LANE_9 = 9u, /*!< SerDes Lane #9 Index */ + ADI_APOLLO_SERDES_LANE_10 = 10u, /*!< SerDes Lane #10 Index */ + ADI_APOLLO_SERDES_LANE_11 = 11u, /*!< SerDes Lane #11 Index */ + ADI_APOLLO_SERDES_LANE_12 = 12u, /*!< SerDes Lane #12 Index */ + ADI_APOLLO_SERDES_LANE_13 = 13u, /*!< SerDes Lane #13 Index */ + ADI_APOLLO_SERDES_LANE_14 = 14u, /*!< SerDes Lane #14 Index */ + ADI_APOLLO_SERDES_LANE_15 = 15u, /*!< SerDes Lane #15 Index */ + ADI_APOLLO_SERDES_LANE_16 = 16u, /*!< SerDes Lane #16 Index */ + ADI_APOLLO_SERDES_LANE_17 = 17u, /*!< SerDes Lane #17 Index */ + ADI_APOLLO_SERDES_LANE_18 = 18u, /*!< SerDes Lane #18 Index */ + ADI_APOLLO_SERDES_LANE_19 = 19u, /*!< SerDes Lane #19 Index */ + ADI_APOLLO_SERDES_LANE_20 = 20u, /*!< SerDes Lane #20 Index */ + ADI_APOLLO_SERDES_LANE_21 = 21u, /*!< SerDes Lane #21 Index */ + ADI_APOLLO_SERDES_LANE_22 = 22u, /*!< SerDes Lane #22 Index */ + ADI_APOLLO_SERDES_LANE_23 = 23u, /*!< SerDes Lane #23 Index */ + ADI_APOLLO_SERDES_LANE_LEN = 24u /*!< Total Number of SerDes Lanes supported */ +} ADI_APOLLO_PACK_ENUM adi_apollo_serdes_lane_num_e; + + +/** + * \brief Serializer Framer Enumeration + */ +typedef enum adi_apollo_jesd_framer { + ADI_APOLLO_JESD_FRAMER_0 = 0u, /*!< Framer 0 */ + ADI_APOLLO_JESD_FRAMER_1 = 1u, /*!< Framer 1 */ + ADI_APOLLO_JESD_FRAMER_NUM = 2u /*!< Total Number of Framers */ +} ADI_APOLLO_PACK_ENUM adi_apollo_jesd_framer_e; + +/** + * \brief Deserializer Deframer Enumeration + */ +typedef enum adi_apollo_jesd_deframer { + ADI_APOLLO_JESD_DEFRAMER_0 = 0u, /*!< Deframer 0 */ + ADI_APOLLO_JESD_DEFRAMER_1 = 1u, /*!< Deframer 1 */ + ADI_APOLLO_JESD_DEFRAMER_NUM = 2u /*!< Total Number of Deframers */ +} ADI_APOLLO_PACK_ENUM adi_apollo_jesd_deframer_e; + + +/** + * \brief SerDes Pack Index Enumeration. Used for both JRx and JTx. + */ +typedef enum adi_apollo_ser_des_pack { + ADI_APOLLO_SERDES_PACK_IDX_0 = 0u, /*!< Pack 0 */ + ADI_APOLLO_SERDES_PACK_IDX_1 = 1u, /*!< Pack 1 */ + ADI_APOLLO_SERDES_NUM_PACKS = 2u /*!< Total Number of SerDes Packs */ +} ADI_APOLLO_PACK_ENUM adi_apollo_ser_des_pack_e; + + +/** + * \brief Serializer Quad-Byte Framer Enumeration + */ +typedef enum adi_apollo_jesd_qbf_txfe { + ADI_APOLLO_JESD_QBF_TXFE_0 = 0u, /*!< QBF 0 */ + ADI_APOLLO_JESD_QBF_TXFE_1 = 1u, /*!< QBF 1 */ + ADI_APOLLO_JESD_QBF_TXFE_NUM = 2u /*!< Total Number of QBFs */ +} ADI_APOLLO_PACK_ENUM adi_apollo_jesd_qbf_txfe_e; + + +/** + * \brief Serializer Framer Virtual Converter Enumeration + */ +typedef enum adi_apollo_jesd_frm_conv_xbar_select { + ADI_APOLLO_JESD_FRM_CONVXBAR_VCONV_0 = 0u, /*!< Virtual Converter 0 */ + ADI_APOLLO_JESD_FRM_CONVXBAR_VCONV_1 = 1u, /*!< Virtual Converter 1 */ + ADI_APOLLO_JESD_FRM_CONVXBAR_VCONV_2 = 2u, /*!< Virtual Converter 2 */ + ADI_APOLLO_JESD_FRM_CONVXBAR_VCONV_3 = 3u, /*!< Virtual Converter 3 */ + ADI_APOLLO_JESD_FRM_CONVXBAR_VCONV_4 = 4u, /*!< Virtual Converter 4 */ + ADI_APOLLO_JESD_FRM_CONVXBAR_VCONV_5 = 5u, /*!< Virtual Converter 5 */ + ADI_APOLLO_JESD_FRM_CONVXBAR_VCONV_6 = 6u, /*!< Virtual Converter 6 */ + ADI_APOLLO_JESD_FRM_CONVXBAR_VCONV_7 = 7u, /*!< Virtual Converter 7 */ + ADI_APOLLO_JESD_FRM_CONVXBAR_VCONV_8 = 8u, /*!< Virtual Converter 8 */ + ADI_APOLLO_JESD_FRM_CONVXBAR_VCONV_9 = 9u, /*!< Virtual Converter 9 */ + ADI_APOLLO_JESD_FRM_CONVXBAR_VCONV_10 = 10u, /*!< Virtual Converter 10 */ + ADI_APOLLO_JESD_FRM_CONVXBAR_VCONV_11 = 11u, /*!< Virtual Converter 11 */ + ADI_APOLLO_JESD_FRM_CONVXBAR_VCONV_12 = 12u, /*!< Virtual Converter 12 */ + ADI_APOLLO_JESD_FRM_CONVXBAR_VCONV_13 = 13u, /*!< Virtual Converter 13 */ + ADI_APOLLO_JESD_FRM_CONVXBAR_VCONV_14 = 14u, /*!< Virtual Converter 14 */ + ADI_APOLLO_JESD_FRM_CONVXBAR_VCONV_15 = 15u, /*!< Virtual Converter 15 */ + ADI_APOLLO_JESD_FRM_CONVXBAR_VCONV_NUM = 16u /*!< Total Number of Virtual Converters */ +} ADI_APOLLO_PACK_ENUM adi_apollo_jesd_frm_conv_xbar_select_e; + + +/** + * \brief Deserializer Deframer SYNC Pad Power Enumeration + */ +typedef enum adi_apollo_jesd_dfrm_sync_pad_req { + ADI_APOLLO_JESD_DFRM_PWR_ON_SYNC_PAD1 = 0u, /*!< Power On Sync Pad 1 */ + ADI_APOLLO_JESD_DFRM_PWR_ON_SYNC_PAD2 = 1u, /*!< Power On Sync Pad 2 */ + ADI_APOLLO_JESD_DFRM_PWR_ON_ALL_SYNC_PADS = 2u, /*!< Power On All Sync Pads */ + ADI_APOLLO_JESD_DFRM_PWR_OFF_ALL_SYNC_PADS = 3u /*!< Power Off All Sync Pads */ +} ADI_APOLLO_PACK_ENUM adi_apollo_jesd_dfrm_sync_pad_req_e; + + +/** + * \brief JESD Converter Clock Mode Enumeration + */ +typedef enum adi_apollo_jesd_conv_clock_mode { + ADI_APOLLO_JESD_NO_RESAMPLE_FIR = 0u, /*!< No Resampling */ + ADI_APOLLO_JESD_2_3_RESAMPLE_FIR = 1u, /*!< 2/3 Resampling */ + ADI_APOLLO_JESD_3_4_RESAMPLE_FIR = 2u /*!< 3/4 Resampling */ +} ADI_APOLLO_PACK_ENUM adi_apollo_jesd_conv_clock_mode_e; + + +/** + * \brief CPU ID Enumeration + */ +typedef enum adi_apollo_cpu_id { + ADI_APOLLO_CPU_ID_0 = 0u, /*!< CPU 0 */ + ADI_APOLLO_CPU_ID_1 = 1u /*!< CPU 1 */ +} ADI_APOLLO_PACK_ENUM adi_apollo_cpu_id_e; + +#define ADI_APOLLO_RX_CHAN_LEN_CPU (ADI_APOLLO_RX_CH_LEN / 1u) +#define ADI_APOLLO_TX_CHAN_LEN_CPU (ADI_APOLLO_TX_CH_LEN / 1u) +#define ADI_APOLLO_SERDES_LANE_LEN_CPU (ADI_APOLLO_SERDES_LANE_LEN / 1u) +#define ADI_APOLLO_SERDES_PACK_LEN_CPU (ADI_APOLLO_SERDES_NUM_PACKS / 1u) + + +/** + * \brief Profile Version Structure + */ +ADI_APOLLO_PACK_START +typedef struct adi_apollo_profile_version { + uint8_t major; /*!< Major component in profile version */ + uint16_t minor; /*!< Minor component in profile version */ + uint8_t patch; /*!< Patch component in profile version */ +} adi_apollo_profile_version_t; +ADI_APOLLO_PACK_FINISH + + +/** + * \brief DAC Configuration Structure + */ +ADI_APOLLO_PACK_START +typedef struct adi_apollo_dac_cfg { + uint64_t dac_sampling_rate_Hz; /*!< DAC sampling rate in Hz. */ + bool shuffle_en[ADI_APOLLO_DACS_PER_SIDE]; /*!< True to enable shuffle. */ + bool scrambler_en[ADI_APOLLO_DACS_PER_SIDE]; /*!< True to enable scrambler */ + bool data_invert_en[ADI_APOLLO_DACS_PER_SIDE]; /*!< True to enable data inversion */ +} adi_apollo_dac_cfg_t; +ADI_APOLLO_PACK_FINISH + + +/** + * \brief ADC FG Calibration Type Enumerations + */ +typedef enum adi_apollo_adc_init_cal_type { + ADI_APOLLO_ADC_INIT_CAL_TYPE_EXT_INPUT = 0U, /*!< ADC FG cal with external signal */ + ADI_APOLLO_ADC_INIT_CAL_TYPE_NO_INPUT = 1U, /*!< ADC FG cal without external signal */ +} ADI_APOLLO_PACK_ENUM adi_apollo_adc_init_cal_type_e; + + +/** + * \brief ADC Slice Clocking Mode Enumerations + */ +typedef enum adi_apollo_adc_slc_mode { + ADI_APOLLO_ADC_SLICE_PPRAND3P1 = 6u, /*!< Ping-Pong Random 3+1 Mode */ + ADI_APOLLO_ADC_SLICE_PPSEQ4 = 7u, /*!< Ping-Pong Sequential 4 Mode */ + ADI_APOLLO_ADC_SLICE_RAND3P1 = 10u, /*!< Random 3+1 Mode */ + ADI_APOLLO_ADC_SLICE_SEQ4 = 11u /*!< Sequential 4 Mode */ +} ADI_APOLLO_PACK_ENUM adi_apollo_adc_slc_mode_e; + + +/** + * \brief ADC Track & Hold Mode Enumerations + */ +typedef enum adi_apollo_adc_trk_mode { + ADI_APOLLO_ADC_TRACK_SEQ1 = 0u, /*!< Single Track & Hold Mode */ + ADI_APOLLO_ADC_TRACK_SEQ2 = 1u /*!< Sequential 2 Mode */ +} ADI_APOLLO_PACK_ENUM adi_apollo_adc_trk_mode_e; + + +/** + * \brief ADC Full Scale Adjust Enumerations + */ +typedef enum adi_apollo_adc_full_scale_adj { + ADI_APOLLO_ADC_FULL_SCALE_ADJ_M6P0DB = 160U, /*!< -6.0 dB (0xA0) */ + ADI_APOLLO_ADC_FULL_SCALE_ADJ_M5P0DB = 176U, /*!< -5.0 dB (0xB0) */ + ADI_APOLLO_ADC_FULL_SCALE_ADJ_M4P0DB = 192U, /*!< -4.0 dB (0xC0) */ + ADI_APOLLO_ADC_FULL_SCALE_ADJ_M3P0DB = 208U, /*!< -3.0 dB (0xD0) */ + ADI_APOLLO_ADC_FULL_SCALE_ADJ_M2P0DB = 224U, /*!< -2.0 dB (0xE0) */ + ADI_APOLLO_ADC_FULL_SCALE_ADJ_M1P0DB = 240U, /*!< -1.0 dB (0xF0) */ + ADI_APOLLO_ADC_FULL_SCALE_ADJ_DEFAULT = 0U, /*!< 0.0 dB (0x00) */ + ADI_APOLLO_ADC_FULL_SCALE_ADJ_P1P0DB = 16U, /*!< +1.0 dB (0x10) */ + ADI_APOLLO_ADC_FULL_SCALE_ADJ_P2P0DB = 32U, /*!< +2.0 dB (0x20) */ +} ADI_APOLLO_PACK_ENUM adi_apollo_adc_full_scale_adj_e; + + +/** + * \brief ADC Input Coupling Enumerations + */ +typedef enum adi_apollo_adc_input_coupling { + ADI_APOLLO_ADC_INPUT_COUPLING_AC = 0u, /*!< AC Coupled Input */ + ADI_APOLLO_ADC_INPUT_COUPLING_DC = 1u /*!< DC Coupled Input */ +} ADI_APOLLO_PACK_ENUM adi_apollo_adc_input_coupling_e; + + +/** + * \brief ADC Input Signal Type Enumerations + */ +typedef enum adi_apollo_adc_input_signal { + ADI_APOLLO_ADC_INPUT_SIGNAL_DIFFERENTIAL = 0u, /*!< Differential Signal */ + ADI_APOLLO_ADC_INPUT_SIGNAL_SINGLE_ENDED = 1u /*!< Single-Ended Signal */ +} ADI_APOLLO_PACK_ENUM adi_apollo_adc_input_signal_e; + + +/** + * \brief ADC Input Polarity Enumerations + */ +typedef enum adi_apollo_adc_input_polarity { + ADI_APOLLO_ADC_INPUT_POLARITY_NORMAL = 0u, /*!< Normal */ + ADI_APOLLO_ADC_INPUT_POLARITY_INVERT = 1u /*!< Inverted */ +} ADI_APOLLO_PACK_ENUM adi_apollo_adc_input_polarity_e; + + +/** + * \brief ADC Slice Mode Switch Configuration Structure + */ +ADI_APOLLO_PACK_START +typedef struct adi_apollo_adc_slice_mode_switch_cfg { + uint8_t switch_type; /*!< ADC Slice Mode Switch Type */ + uint8_t trig_gpio_num; /*!< GPIO number used for triggering ADC slice mode switch */ +} adi_apollo_adc_slice_mode_switch_cfg_t; +ADI_APOLLO_PACK_FINISH + + +/** + * \brief ADC Configuration Structure + */ +ADI_APOLLO_PACK_START +typedef struct adi_apollo_adc_cfg { + uint64_t adc_sampling_rate_Hz; /*!< ADC sampling rate in Hz. */ + adi_apollo_adc_init_cal_type_e adc_init_cal_type; /*!< ADC initial calibration type. */ + uint8_t adc_init_cal_index; /*!< ADC initial calibration index. */ + adi_apollo_adc_slc_mode_e adc_slice_mode[ADI_APOLLO_ADCS_PER_SIDE]; /*!< Slice mode */ + adi_apollo_adc_trk_mode_e adc_track_mode[ADI_APOLLO_ADCS_PER_SIDE]; /*!< Track mode */ + adi_apollo_adc_full_scale_adj_e full_scale_adj[ADI_APOLLO_ADCS_PER_SIDE]; /*!< Full Scale Adjust */ + adi_apollo_adc_input_coupling_e inp_coupling_type[ADI_APOLLO_ADCS_PER_SIDE]; /*!< Input Coupling Type */ + adi_apollo_adc_input_signal_e inp_signal_type[ADI_APOLLO_ADCS_PER_SIDE]; /*!< Input Signal Type */ + adi_apollo_adc_input_polarity_e inp_polarity[ADI_APOLLO_ADCS_PER_SIDE]; /*!< Input Polarity */ + adi_apollo_adc_slice_mode_switch_cfg_t slice_mode_switch_cfg; /*!< Slice mode switch configuration */ + uint32_t adc_options[8]; /*!< ADC Options */ +} adi_apollo_adc_cfg_t; +ADI_APOLLO_PACK_FINISH + + +/** + * \brief Coarse DDC (Digital Down Converter) Ratio/Decimation Enumeration + */ +typedef enum adi_apollo_cddc_ratio { + ADI_APOLLO_CDDC_RATIO_1 = 0u, /*!< Decimate by 1 */ + ADI_APOLLO_CDDC_RATIO_2 = 1u, /*!< Decimate by 2 */ + ADI_APOLLO_CDDC_RATIO_3 = 2u, /*!< Decimate by 3 */ + ADI_APOLLO_CDDC_RATIO_4 = 3u, /*!< Decimate by 4 */ + ADI_APOLLO_CDDC_RATIO_6 = 4u, /*!< Decimate by 6 */ + ADI_APOLLO_CDDC_RATIO_12 = 6u, /*!< Decimate by 12 */ +} ADI_APOLLO_PACK_ENUM adi_apollo_cddc_ratio_e; + + +/** + * \brief Coarse DUC (Digital Up Converter) Ratio/Interpolation Enumeration + */ +typedef enum adi_apollo_cduc_ratio { + ADI_APOLLO_CDUC_RATIO_1 = 1u, /*!< Interpolate by 1 */ + ADI_APOLLO_CDUC_RATIO_2 = 2u, /*!< Interpolate by 2 */ + ADI_APOLLO_CDUC_RATIO_3 = 3u, /*!< Interpolate by 3 */ + ADI_APOLLO_CDUC_RATIO_4 = 4u, /*!< Interpolate by 4 */ + ADI_APOLLO_CDUC_RATIO_6 = 6u, /*!< Interpolate by 6 */ + ADI_APOLLO_CDUC_RATIO_8 = 8u, /*!< Interpolate by 8 */ + ADI_APOLLO_CDUC_RATIO_12 = 12u, /*!< Interpolate by 12 */ +} ADI_APOLLO_PACK_ENUM adi_apollo_cduc_ratio_e; + + +/** + * \brief Fine DDC (Digital Down Converter) Ratio/Decimation Enumeration + */ +typedef enum adi_apollo_fddc_ratio { + ADI_APOLLO_FDDC_RATIO_1 = 0u, /*!< Decimate by 1 */ + ADI_APOLLO_FDDC_RATIO_2 = 1u, /*!< Decimate by 2 */ + ADI_APOLLO_FDDC_RATIO_4 = 2u, /*!< Decimate by 4 */ + ADI_APOLLO_FDDC_RATIO_8 = 3u, /*!< Decimate by 8 */ + ADI_APOLLO_FDDC_RATIO_16 = 4u, /*!< Decimate by 16 */ + ADI_APOLLO_FDDC_RATIO_32 = 5u, /*!< Decimate by 32 */ + ADI_APOLLO_FDDC_RATIO_64 = 6u /*!< Decimate by 64 */ +} ADI_APOLLO_PACK_ENUM adi_apollo_fddc_ratio_e; + + +/** + * \brief Fine DUC (Digital Up Converter) Ratio/Interpolation Enumeration + */ +typedef enum adi_apollo_fduc_ratio { + ADI_APOLLO_FDUC_RATIO_1 = 1u, /*!< Interpolate by 1 */ + ADI_APOLLO_FDUC_RATIO_2 = 2u, /*!< Interpolate by 2 */ + ADI_APOLLO_FDUC_RATIO_4 = 4u, /*!< Interpolate by 4 */ + ADI_APOLLO_FDUC_RATIO_8 = 8u, /*!< Interpolate by 8 */ + ADI_APOLLO_FDUC_RATIO_16 = 16u, /*!< Interpolate by 16 */ + ADI_APOLLO_FDUC_RATIO_32 = 32u, /*!< Interpolate by 32 */ + ADI_APOLLO_FDUC_RATIO_64 = 64u /*!< Interpolate by 64 */ +} ADI_APOLLO_PACK_ENUM adi_apollo_fduc_ratio_e; + + +/** + * \brief NCO Mixer Modes Enumeration + */ +typedef enum adi_apollo_nco_mixer_mode { + ADI_APOLLO_MXR_VAR_IF_MODE = 0u, /*!< Variable IF Mode */ + ADI_APOLLO_MXR_ZERO_IF_MODE = 1u, /*!< Zero IF Mode */ + ADI_APOLLO_MXR_FS_BY_4_MODE = 2u, /*!< Fs/4 Hz IF Mode */ + ADI_APOLLO_MXR_TEST_MODE = 3u /*!< Test Mode */ +} ADI_APOLLO_PACK_ENUM adi_apollo_nco_mixer_mode_e; + + +/** + * \brief NCO Modes Enumeration + */ +typedef enum adi_apollo_nco_mode { + ADI_APOLLO_NCO_MOD_INTEGER = 0u, /*!< Integer Mode */ + ADI_APOLLO_NCO_MOD_INT_PLUS_MODULUS = 1u /*!< Modulus Mode */ +} ADI_APOLLO_PACK_ENUM adi_apollo_nco_mode_e; + + +/** + * \brief NCO Profile Word Select Enumeration + */ +typedef enum adi_apollo_nco_profile_word_sel { + ADI_APOLLO_NCO_PROFILE_PHASE_INCREMENT = 0u, /*!< Phase Increment Word */ + ADI_APOLLO_NCO_PROFILE_PHASE_OFFSET = 1u, /*!< Phase Offset Word */ +} ADI_APOLLO_PACK_ENUM adi_apollo_nco_profile_word_sel_e; + + +/** + * \brief FNCO Profile Chan Selection Mode Enumeration + */ +typedef enum adi_apollo_nco_profile_sel_mode { + ADI_APOLLO_NCO_CHAN_SEL_TRIG_AUTO = 0u, /*!< Trigger based hopping. Auto Hopping Mode */ + ADI_APOLLO_NCO_CHAN_SEL_TRIG_REGMAP = 1u, /*!< Trigger based hopping. Scheduled Regmap */ + ADI_APOLLO_NCO_CHAN_SEL_TRIG_GPIO = 2u, /*!< Trigger based hopping. Scheduled GPIO */ + ADI_APOLLO_NCO_CHAN_SEL_DIRECT_GPIO = 3u, /*!< Direct GPIO profile select. All params hop together */ + ADI_APOLLO_NCO_CHAN_SEL_DIRECT_REGMAP = 4u /*!< Direct spi/hsci nco profile select. All params hop together */ +} ADI_APOLLO_PACK_ENUM adi_apollo_nco_profile_sel_mode_e; + + +/** + * \brief FNCO Trigger Hop Select Enumeration + */ +typedef enum adi_apollo_fnco_trig_hop_sel { + ADI_APOLLO_FNCO_TRIG_HOP_FREQ = 1u, /*!< Hop freq in trigger based hopping */ + ADI_APOLLO_FNCO_TRIG_HOP_PHASE = 4u, /*!< Hop phase in trigger based hopping */ + ADI_APOLLO_FNCO_TRIG_HOP_FREQ_PHASE = 5u /*!< Hop freq and phase in trigger based hopping */ +} ADI_APOLLO_PACK_ENUM adi_apollo_fnco_trig_hop_sel_e; + + +/** + * \brief NCO Next Hop Select Mode Enumeration. Applicable for trigger based auto hop. + */ +typedef enum adi_apollo_nco_auto_hop_dir_sel { + ADI_APOLLO_NCO_AUTO_HOP_DIR_DECR = 0u, /*!< Decrement profile num on trigger */ + ADI_APOLLO_NCO_AUTO_HOP_DIR_INCR = 1u, /*!< Increment profile num on trigger */ +} ADI_APOLLO_PACK_ENUM adi_apollo_nco_auto_hop_dir_sel_e; + + +/** + * \brief DRC Mixer Selection Enumeration + */ +typedef enum adi_apollo_drc_mixer_sel { + ADI_APOLLO_DRC_MIXER_REAL = 0u, /*!< Real Mixing */ + ADI_APOLLO_DRC_MIXER_COMPLEX = 1u /*!< Complex Mixing */ +} ADI_APOLLO_PACK_ENUM adi_apollo_drc_mixer_sel_e; + + +/** + * \brief CDRC TB1 Filter Delay Enumeration + */ +typedef enum adi_apollo_cdrc_tb1_filt_dly { + ADI_APOLLO_CDRC_TB1_FILT_DLY_NONE = 0u, /*!< No filter delay */ + ADI_APOLLO_CDRC_TB1_FILT_DLY_STAGE_1 = 1u, /*!< Delay 1 filter stage */ + ADI_APOLLO_CDRC_TB1_FILT_DLY_STAGE_2 = 2u, /*!< Delay 2 filter stages */ + ADI_APOLLO_CDRC_TB1_FILT_DLY_STAGE_3 = 3u /*!< Delay 3 filter stages */ +} ADI_APOLLO_PACK_ENUM adi_apollo_cdrc_tb1_filt_dly_e; + + +/** + * \brief Complex Mixer Multiplication Scaling Enumeration + */ +typedef enum adi_apollo_nco_cmplx_mult_scale { + ADI_APOLLO_CMPLX_MULT_SCALE_0p7 = 0u, /*!< Scale by .7 */ + ADI_APOLLO_CMPLX_MULT_SCALE_1 = 1u /*!< Scale by 1 */ +} ADI_APOLLO_PACK_ENUM adi_apollo_nco_cmplx_mult_scale_e; + + +/** + * \brief CNCO Config Structure + */ +ADI_APOLLO_PACK_START +typedef struct adi_apollo_cnco_cfg { + bool drc_en; /*!< CDRC enable */ + adi_apollo_nco_mode_e nco_mode; /*!< NCO integer or integer plus modulus */ + + /* Register name in Yoda: coarse_drc_mixer_ctrl */ + adi_apollo_nco_mixer_mode_e nco_if_mode; /*!< NCO mixer mode. var-if, zero-if, fs-by-4, dc-test */ + adi_apollo_drc_mixer_sel_e drc_mxr_sel; /*!< Real or complex mixing select */ + adi_apollo_nco_cmplx_mult_scale_e cmplx_mxr_mult_scale_en; /*!< NCO complex multiplication scale */ + uint16_t dc_testmode_value; /*!< Mixer test mode value */ + + uint32_t nco_phase_inc; /*!< NCO phase increment word */ + uint32_t nco_phase_offset; /*!< NCO phase offset word */ + uint32_t nco_phase_inc_frac_a; /*!< Modulus phase increment numerator. */ + uint32_t nco_phase_inc_frac_b; /*!< Modulus phase increment denominator. */ + uint32_t nco_phase_inc_words[ADI_APOLLO_CNCO_PROFILE_NUM]; /*!< NCO phase increment words */ + uint32_t nco_phase_offset_words[ADI_APOLLO_CNCO_PROFILE_NUM]; /*!< NCO phase offset words */ + + bool amp_dither_en; /*!< Amplitude Dither Enable, False: Disable, True: Enabled. */ + bool phase_dither_en; /*!< Phase Dither Enable, False: Disable, True: Enabled. */ + + /* Hopping and Trigger */ + adi_apollo_nco_profile_sel_mode_e nco_profile_sel_mode; /*!< Profile selection mode (e.g. direct or trigger based) */ + adi_apollo_nco_auto_hop_dir_sel_e nco_auto_inc_dec; /*!< Increment or decrement profile selection for auto hop. */ + bool debug_cdrc_clkoff_n; /*!< if TRUE (typical), enable nco clocks */ + +} adi_apollo_cnco_cfg_t; +ADI_APOLLO_PACK_FINISH + + +/** + * \brief Fine NCO Hop Mode Enumeration + */ +typedef enum adi_apollo_fnco_hop_mode { + ADI_APOLLO_FNCO_HOP_MODE_STANDARD = 0u, /*!< Standard Hopping Mode */ + ADI_APOLLO_FNCO_HOP_MODE_FRAMP = 1u, /*!< Frequency Ramp Hopping Mode */ + ADI_APOLLO_FNCO_HOP_MODE_FRAMP_JMP = 2u, /*!< Frequency Ramp with Jump Hop Mode */ + ADI_APOLLO_FNCO_HOP_MODE_FRAMP_JMP_ARAMP = 3u /*!< Frequency Ramp with Jump and Amplitude Ramping Hop Mode */ +} ADI_APOLLO_PACK_ENUM adi_apollo_fnco_hop_mode_e; + + +/** + * \brief FNCO Config Structure + */ +ADI_APOLLO_PACK_START +typedef struct adi_apollo_fnco_cfg { + bool drc_en; /*!< FDRC enable */ + adi_apollo_nco_mode_e nco_mode; /*!< NCO integer or integer plus modulus */ + + /* Register name in Yoda: fine_mixer_ctrl */ + adi_apollo_nco_mixer_mode_e nco_if_mode; /*!< NCO mixer mode. var-if, zero-if, fs-by-4, dc-test */ + adi_apollo_drc_mixer_sel_e drc_mxr_sel; /*!< Real or complex mixing select */ + adi_apollo_nco_cmplx_mult_scale_e cmplx_mxr_mult_scale_en; /*!< NCO complex multiplication scale */ + uint16_t dc_testmode_value; /*!< Mixer test mode value */ + + uint64_t nco_phase_inc; /*!< NCO phase increment word */ + uint64_t nco_phase_offset; /*!< NCO phase offset word */ + uint64_t nco_phase_inc_frac_a; /*!< Modulus phase increment numerator. */ + uint64_t nco_phase_inc_frac_b; /*!< Modulus phase increment denominator. */ + + bool amp_dither_en; /*!< Amplitude Dither Enable, False: Disable, True: Enabled. */ + bool phase_dither_en; /*!< Phase Dither Enable, False: Disable, True: Enabled. */ + + bool hop_mode_en; /*!< If TRUE, enable freq hopping. */ + uint8_t hop_mode; /*!< Fine NCO hop mode. */ + + uint32_t nco_phase_inc_words[ADI_APOLLO_FNCO_PROFILE_NUM]; /*!< NCO phase increment words */ + uint32_t nco_phase_offset_words[ADI_APOLLO_FNCO_PROFILE_NUM]; /*!< NCO phase offset words */ + + /* Hopping and Trigger */ + adi_apollo_nco_profile_sel_mode_e nco_profile_sel_mode; /*!< Profile selection mode (e.g. direct or trigger based) */ + adi_apollo_nco_auto_hop_dir_sel_e nco_auto_inc_dec_freq; /*!< Increment or decrement freq profile selection for auto hop. */ + adi_apollo_nco_auto_hop_dir_sel_e nco_auto_inc_dec_phase; /*!< Increment or decrement phase profile selection for auto hop. */ + adi_apollo_fnco_trig_hop_sel_e nco_trig_hop_sel; /*!< Select params to change on hop. Freq, phase or both */ + bool debug_fdrc_clkoff_n; /*!< if TRUE (typical), enable nco clocks */ +} adi_apollo_fnco_cfg_t; +ADI_APOLLO_PACK_FINISH + + +/** + * \brief TB1 Filter Delay Setting Enumeration + */ +typedef enum adi_apollo_tb1_filt_dly_cycles { + ADI_APOLLO_TB1_FILT_DLY_DISABLED = 0u, /*!< TB1 Filter Delay Disabled */ + ADI_APOLLO_TB1_FILT_DLY_1CYCLE = 1u, /*!< TB1 Filter 1 Cycle Delay */ + ADI_APOLLO_TB1_FILT_DLY_2CYCLES = 2u /*!< TB1 Filter 2 Cycles Disabled */ +} ADI_APOLLO_PACK_ENUM adi_apollo_tb1_filt_dly_cycles_e; + + +/** + * \brief Coarse Digital Down Converter Config Structure + */ +ADI_APOLLO_PACK_START +typedef struct adi_apollo_cddc_cfg { + adi_apollo_cnco_cfg_t nco[ADI_APOLLO_NUM_NCOS_PER_DRC]; /*!< NCO corresponding to CDDC */ + adi_apollo_cddc_ratio_e drc_ratio; /*!< Data Rate Conversion Ratio (Decimation) */ + bool fine_bypass; /*!< true = bypass the fine DDC. */ + uint8_t link_num; /*!< Jesd link num CDDC is connected to (when fddc is bypassed) */ + bool hb1_filt_dly_en; /*!< if TRUE, HB1 filter uses a delayed input */ + bool hb2_filt_dly_en; /*!< if TRUE, HB2 filter uses a delayed input */ + adi_apollo_tb1_filt_dly_cycles_e tb1_filt_dly_cycles; /*!< 0 = No Delay, 1 = 1 Cycle, 2 = 2 Cycles */ + bool hb1_gain_6db_en; /*!< if TRUE, the 6dB gain for HB1 filter is enabled */ + bool tb1_gain_6db_en; /*!< if TRUE, the 6dB gain for TB1 filter is enabled */ + + bool trig_mst_en; /*!< true to enable the trigger master, false to disable */ + uint64_t trig_mst_period; /*!< Trigger master period, in units of Fs. Used w/ profile sel timer */ + uint64_t trig_mst_offset; /*!< Trigger master offset, in units of Fs. Used w/ profile sel timer */ + uint8_t debug_cddc_clkoff_n; /*!< If this bit is zero the clocks are shutoff.bit 0 : filter input clock bit 1 : filter output clockbit 2: hb1 clockbit 3: hb2 clockbit 4: reservedbit 5: reservedbit 6: tb1 clock */ + /* Trigger sel mux: external, internal or spi (see txrx_trigger_ts, reg: TRIG_SEL_MUX_CDRC0n amd TRIG_SEL_MUX_CDRC1n) */ +} adi_apollo_cddc_cfg_t; +ADI_APOLLO_PACK_FINISH + + +/** + * \brief Coarse Digital Up Converter Config Structure + */ +ADI_APOLLO_PACK_START +typedef struct adi_apollo_cduc_cfg { + adi_apollo_cnco_cfg_t nco[ADI_APOLLO_NUM_NCOS_PER_DRC]; /*!< NCO corresponding to CDUC */ + adi_apollo_cduc_ratio_e drc_ratio; /*!< Data Rate Conversion Ratio (Interpolation) */ +} adi_apollo_cduc_cfg_t; +ADI_APOLLO_PACK_FINISH + +/** + * \brief Fine Digital Down Converter Config Structure + */ +ADI_APOLLO_PACK_START +typedef struct adi_apollo_fddc_cfg { + adi_apollo_fnco_cfg_t nco[ADI_APOLLO_NUM_NCOS_PER_DRC]; /*!< NCO corresponding to FDDC */ + adi_apollo_fddc_ratio_e drc_ratio; /*!< Data Rate Conversion Ratio (Decimation) */ + + uint8_t link_num; /*!< Jesd link num FDDC is connected */ + uint8_t debug_fddc_clkoff_n; /*!< 0xff (typical) to enable ddc clks */ + bool hb1_filt_dly_en; /*!< if TRUE, HB1 filter uses a delayed input */ + bool hb2_filt_dly_en; /*!< if TRUE, HB2 filter uses a delayed input */ + bool hb3_filt_dly_en; /*!< if TRUE, HB3 filter uses a delayed input */ + bool hb4_filt_dly_en; /*!< if TRUE, HB4 filter uses a delayed input */ + bool hb5_filt_dly_en; /*!< if TRUE, HB5 filter uses a delayed input */ + bool hb6_filt_dly_en; /*!< if TRUE, HB6 filter uses a delayed input */ + bool hb1_gain_6db_en; /*!< if TRUE, the 6dB gain for HB1 filter is enabled */ +} adi_apollo_fddc_cfg_t; +ADI_APOLLO_PACK_FINISH + +/** + * \brief Fine Digital Up Converter Config Structure + */ +ADI_APOLLO_PACK_START +typedef struct adi_apollo_fduc_cfg { + adi_apollo_fnco_cfg_t nco[ADI_APOLLO_NUM_NCOS_PER_DRC]; /*!< NCO corresponding to FDUC */ + adi_apollo_fduc_ratio_e drc_ratio; /*!< Data Rate Conversion Ratio (Interpolation) */ + + bool sub_dp_gain_en; /*!< FDUC input gain control enable */ + uint16_t subdp_gain; /*!< FDUC sub data path gain */ +} adi_apollo_fduc_cfg_t; +ADI_APOLLO_PACK_FINISH + + +/** + * \brief Programmable Filter (PFILT) Mode Enumeration + */ +typedef enum adi_apollo_pfilt_mode { + ADI_APOLLO_PFILT_MODE_DISABLED = 0u, /*!< Disabled (filters bypassed) */ + ADI_APOLLO_PFILT_MODE_N_DIV_BY_4_REAL = 1u, /*!< Real N/4 Tap Filter for the I/Q channel */ + ADI_APOLLO_PFILT_MODE_N_DIV_BY_2_REAL = 2u, /*!< Real N/2 Tap Filter for the I/Q channel */ + ADI_APOLLO_PFILT_MODE_MATRIX = 4u, /*!< Real N/4 tap Matrix mode of operation (pfilt_q_mode/pfilt_i_mode must also be set to 100) */ + ADI_APOLLO_PFILT_MODE_HALF_COMPLEX = 6u, /*!< Half Complex Filter using N/2-Tap Filters for the Q/I channel + N/2 Tap Programmable Delay Line for the I/Q Channel */ + ADI_APOLLO_PFILT_MODE_N_REAL = 7u /*!< Real N Tap Filter for the I/Q (pfilt_q_mode/pfilt_i_mode must be set to 000 */ +} ADI_APOLLO_PACK_ENUM adi_apollo_pfilt_mode_e; + + +/** + * \brief Programmable Filter Gain Enumeration + */ +typedef enum adi_apollo_pfilt_gain { + ADI_APOLLO_PFILT_GAIN_ZERO_DB = 0u, /*!< No Gain (0 dB) */ + ADI_APOLLO_PFILT_GAIN_POS_6_DB = 1u, /*!< +6 dB Gain */ + ADI_APOLLO_PFILT_GAIN_POS_12_DB = 2u, /*!< +12 dB Gain */ + ADI_APOLLO_PFILT_GAIN_POS_18_DB = 3u, /*!< +18 dB Gain */ + ADI_APOLLO_PFILT_GAIN_POS_24_DB = 4u, /*!< +24 dB Gain */ +} ADI_APOLLO_PACK_ENUM adi_apollo_pfilt_gain_e; + + +/** + * \brief Programmable Filter Coefficient Set Enumeration + */ +typedef enum adi_apollo_pfilt_coeffs_sets_per_prfl { + ADI_APOLLO_PFILT_COEFF_SET_0 = 0u, /*!< Coefficient Set 0 */ + ADI_APOLLO_PFILT_COEFF_SET_1 = 1u, /*!< Coefficient Set 1 */ + ADI_APOLLO_PFILT_COEFF_SET_2 = 2u, /*!< Coefficient Set 2 */ + ADI_APOLLO_PFILT_COEFF_SET_3 = 3u, /*!< Coefficient Set 3 */ + ADI_APOLLO_PFILT_COEFF_SET_4 = 4u, /*!< Coefficient Set 4 */ + ADI_APOLLO_PFILT_COEFF_SET_5 = 5u, /*!< Coefficient Set 5 */ + ADI_APOLLO_PFILT_COEFF_SET_6 = 6u, /*!< Coefficient Set 6 */ + ADI_APOLLO_PFILT_COEFF_SET_7 = 7u, /*!< Coefficient Set 7 */ + ADI_APOLLO_PFILT_COEFF_SETS = 8u /*!< Total Number of Coefficient Sets */ +} ADI_APOLLO_PACK_ENUM adi_apollo_pfilt_coeffs_sets_per_prfl_e; + +/** + * \brief Programmable Filter Control Set Enumeration + */ +typedef enum adi_apollo_pfilt_ctrl_sets { + ADI_APOLLO_PFILT_CTRL_SET_0 = 0u, /*!< Control Set 0 */ + ADI_APOLLO_PFILT_CTRL_SET_1 = 1u, /*!< Control Set 1 */ + ADI_APOLLO_PFILT_CTRL_SETS = 2u /*!< Total Number of Control Sets */ +} ADI_APOLLO_PACK_ENUM adi_apollo_pfilt_ctrl_sets_e; + + +/** + * \brief Programmable Filter Mode Selection Enumeration + */ +typedef enum adi_apollo_pfilt_dq_mode { + ADI_APOLLO_PFILT_DUAL_MODE = 0u, /*!< PFILT Dual Mode */ + ADI_APOLLO_PFILT_QUAD_MODE = 1u, /*!< PFILT Quad Mode */ +} ADI_APOLLO_PACK_ENUM adi_apollo_pfilt_dq_mode_e; + + +/** + * \brief Programmable Filter Data Mode Selection Enumeration + */ +typedef enum adi_apollo_pfilt_data { + ADI_APOLLO_PFILT_COMPLEX_DATA = 0u, /*!< PFILT Complex Data */ + ADI_APOLLO_PFILT_REAL_DATA = 1u /*!< PFILT Real Data */ +} ADI_APOLLO_PACK_ENUM adi_apollo_pfilt_data_e; + + +/** + * \brief Programmable Filter Switch Selection Enumeration + */ +typedef enum adi_apollo_pfilt_mode_sw_add_sub { + ADI_APOLLO_PFILT_SUB_FOR_MOD_SW = 0u, /*!< Select subtraction operation */ + ADI_APOLLO_PFILT_ADD_FOR_MOD_SW = 1u /*!< Select addition operation */ +} ADI_APOLLO_PACK_ENUM adi_apollo_pfilt_mode_sw_add_sub_e; + + +/** + * \brief Programmable Filter Switch 3dB Averaging Enable Enumeration + */ +typedef enum adi_apollo_pfilt_mode_sw_ave_en { + ADI_APOLLO_PFILT_DISABLE_3DB_AVG_MOD_SW = 0u, /*!< Disable Mode Switch (3dB Average). Only for Rx PFILT */ + ADI_APOLLO_PFILT_ENABLE_3DB_AVG_MOD_SW = 1u /*!< Enable Mode Switch (3dB Average). Only for Rx PFILT */ +} ADI_APOLLO_PACK_ENUM adi_apollo_pfilt_mode_sw_ave_en_e; + + +/** + * \brief Programmable Filter Config Structure + */ +ADI_APOLLO_PACK_START +typedef struct adi_apollo_pfilt_cfg { + bool enable; /*!< Filter enable */ + + int16_t coeffs[ADI_APOLLO_PFILT_COEFF_SETS][ADI_APOLLO_PFILT_COEFFS]; /*!< List of filter coefficients */ + + adi_apollo_pfilt_mode_e i_mode[ADI_APOLLO_PFILT_CTRL_SETS]; /*!< Filter mode for i stream */ + adi_apollo_pfilt_mode_e q_mode[ADI_APOLLO_PFILT_CTRL_SETS]; /*!< Filter mode for q stream */ + + bool output_dither_en[ADI_APOLLO_PFILT_CTRL_SETS]; /*!< Enable Dither at Final Output Truncation (Rx Only) */ + + adi_apollo_pfilt_data_e real_data; /*!< Selects real or complex data streams */ + adi_apollo_pfilt_dq_mode_e dq_mode; /*!< Dual(4t4r) or Quad(8t8r) filter mode */ + adi_apollo_pfilt_mode_sw_add_sub_e add_sub_sel; /*!< Add/Sub for Mode Switch (3dB Average) */ + adi_apollo_pfilt_mode_sw_ave_en_e mode_switch; /*!< Enable for 3dB Averaging (Mode Switch) for Rx PFILT */ + bool pfilt_trigger_en; /*!< Enable for Trigger-based Profile Hopping */ + + adi_apollo_pfilt_gain_e pfir_ix_gain_db[ADI_APOLLO_PFILT_COEFF_SETS]; /*!< Shift gain */ + adi_apollo_pfilt_gain_e pfir_iy_gain_db[ADI_APOLLO_PFILT_COEFF_SETS]; /*!< Shift gain. Only used in matrix mode */ + adi_apollo_pfilt_gain_e pfir_qx_gain_db[ADI_APOLLO_PFILT_COEFF_SETS]; /*!< Shift gain. */ + adi_apollo_pfilt_gain_e pfir_qy_gain_db[ADI_APOLLO_PFILT_COEFF_SETS]; /*!< Shift gain. Only used in matrix mode */ + + uint8_t pfir_ix_scalar_gain_db[ADI_APOLLO_PFILT_COEFF_SETS]; /*!< Scalar gain */ + uint8_t pfir_iy_scalar_gain_db[ADI_APOLLO_PFILT_COEFF_SETS]; /*!< Scalar gain. Only used in matrix mode */ + uint8_t pfir_qx_scalar_gain_db[ADI_APOLLO_PFILT_COEFF_SETS]; /*!< Scalar gain */ + uint8_t pfir_qy_scalar_gain_db[ADI_APOLLO_PFILT_COEFF_SETS]; /*!< Scalar gain. Only used in matrix mode */ + + uint8_t hc_prog_delay[ADI_APOLLO_PFILT_COEFF_SETS]; /*!< Programmable delay line */ +} adi_apollo_pfilt_cfg_t; +ADI_APOLLO_PACK_FINISH + + +/** + * \brief Complex Filter Profile Index Enumeration + */ +typedef enum adi_apollo_cfir_profiles { + ADI_APOLLO_CFIR_PROFILE_IDX_0 = 0u, /*!< CFIR Profile Index 0 */ + ADI_APOLLO_CFIR_PROFILE_IDX_1 = 1u, /*!< CFIR Profile Index 1 */ + ADI_APOLLO_CFIR_NUM_PROFILES = 2u /*!< Number of CFIR Profile Indices */ +} ADI_APOLLO_PACK_ENUM adi_apollo_cfir_profiles_e; + + +/** + * \brief Complex Filter Coefficient Set Enumeration + */ +typedef enum adi_apollo_cfir_coeffs_sets_per_prfl { + ADI_APOLLO_CFIR_COEFF_SET_0 = 0, /*!< CFIR Coefficient Set 0 */ + ADI_APOLLO_CFIR_COEFF_SET_1 = 1, /*!< CFIR Coefficient Set 1 */ + ADI_APOLLO_CFIR_COEFF_SET_2 = 2, /*!< CFIR Coefficient Set 2 */ + ADI_APOLLO_CFIR_COEFF_SET_3 = 3, /*!< CFIR Coefficient Set 3 */ + ADI_APOLLO_CFIR_COEFF_SETS = 4 /*!< Number of CFIR Coefficient Sets */ +} ADI_APOLLO_PACK_ENUM adi_apollo_cfir_coeffs_sets_per_prfl_e; + + +/** + * \brief Complex Filter Gain Enumeration + */ +typedef enum adi_apollo_cfir_gain { + ADI_APOLLO_CFIR_GAIN_MINUS18_DB = 0, /*!< -18 dB */ + ADI_APOLLO_CFIR_GAIN_MINUS12_DB = 1, /*!< -12 dB */ + ADI_APOLLO_CFIR_GAIN_MINUS6_DB = 2, /*!< -6 dB */ + ADI_APOLLO_CFIR_GAIN_ZERO_DB = 3, /*!< No Gain (0 dB) */ + ADI_APOLLO_CFIR_GAIN_PLUS6_DB = 4, /*!< +6 dB */ + ADI_APOLLO_CFIR_GAIN_PLUS12_DB = 5 /*!< +12 dB */ +} ADI_APOLLO_PACK_ENUM adi_apollo_cfir_gain_e; + + +/** + * \brief Complex Filter Band Mode Enumeration + */ +typedef enum adi_apollo_cfir_sing_dual_mode { + ADI_APOLLO_CFIR_SINGLE_BAND = 0, /*!< CFIR Single Band Mode */ + ADI_APOLLO_CFIR_DUAL_BAND = 1 /*!< CFIR Dual Band Mode */ +} ADI_APOLLO_PACK_ENUM adi_apollo_cfir_sing_dual_mode_e; + + +/** + * \brief Complex Filter Config Structure + */ +ADI_APOLLO_PACK_START +typedef struct adi_apollo_cfir_cfg { + int16_t coeffs_i[ADI_APOLLO_CFIR_NUM_PROFILES][ADI_APOLLO_CFIR_COEFF_SETS][ADI_APOLLO_CFIR_NUM_TAPS]; /*!< CFIR I-data Filter Coefficients */ + int16_t coeffs_q[ADI_APOLLO_CFIR_NUM_PROFILES][ADI_APOLLO_CFIR_COEFF_SETS][ADI_APOLLO_CFIR_NUM_TAPS]; /*!< CFIR Q-data Filter Coefficients */ + adi_apollo_cfir_gain_e cfir_gain_dB[ADI_APOLLO_CFIR_NUM_PROFILES][ADI_APOLLO_CFIR_COEFF_SETS]; /*!< CFIR Gain in dB Coefficients */ + uint16_t scalar_i[ADI_APOLLO_CFIR_NUM_PROFILES][ADI_APOLLO_CFIR_COEFF_SETS]; /*!< CFIR Scalar I Coefficients */ + uint16_t scalar_q[ADI_APOLLO_CFIR_NUM_PROFILES][ADI_APOLLO_CFIR_COEFF_SETS]; /*!< CFIR Scalar Q Coefficients */ + bool enable; /*!< High-level enable for complex filter */ + bool sparse_mode; /*!< CFIR Sparse Filter Mode */ + adi_apollo_cfir_sing_dual_mode_e cfir_mode; /*!< CFIR Single/Dual Mode */ +} adi_apollo_cfir_cfg_t; +ADI_APOLLO_PACK_FINISH + + +/** + * \brief Fractional Sampling Rate Converter Config Structure + */ +ADI_APOLLO_PACK_START +typedef struct adi_apollo_fsrc_cfg { + uint64_t fsrc_rate_int; /*!< Rate, integer part (48 bits). */ + uint64_t fsrc_rate_frac_a; /*!< Rate, numerator of fractional part (48 bits). */ + uint64_t fsrc_rate_frac_b; /*!< Rate, denominator of fractional part (48 bits). */ + uint16_t fsrc_delay; /*!< Sample fractional delay. */ + uint16_t gain_reduction; /*!< 12 bit value */ + uint8_t ptr_syncrstval; /*!< 6 bit value this is used for the FIFO pointer value when the internal fifo-sync is generated when ptr_overwrite is 1 */ + bool ptr_overwrite; /*!< 0 == FIFO reset ptr computed by design, 1 == Use pointer value from ptr_syncrstval */ + bool data_mult_dither_en; /*!< 0 == Disable, 1 == Enable to use added dither in the fsrc data and delta multiplication calculation */ + bool dither_en; /*!< 0 == Disable, 1 == Enable to use added dither in the fsrc delta delay calculation */ + bool split_4t4r; /*!< 0 == Normal mode, 1 == Use the 4t4r split (4t4r two-stream cases) */ + bool mode_1x; /*!< 0 == Normal mode, 1 == 1x mode */ + bool enable0; /*!< 0 == Disable, 1 == Enable for fsrc0 */ + bool enable1; /*!< 0 == Disable, 1 == Enable for fsrc1 */ + bool bypass; /*!< 0 == Not Bypassed, 1 == Bypass */ +} adi_apollo_fsrc_cfg_t; +ADI_APOLLO_PACK_FINISH + + +/** + * \brief Dynamic Reconfig Configuration Structure + */ +ADI_APOLLO_PACK_START +typedef struct adi_apollo_dyn_recfg_cfg { + uint16_t prefsrc_lcm; /*!< 9 bit value */ + uint16_t postfsrc_lcm; /*!< 16 bit value */ + bool trig_recfg_mode; /*!< 0 == Sync Mode, 1 == Trig Mode */ + bool cnco_rst_en; /*!< 0 == Disable, 1 == Enable */ + bool fnco_rst_en; /*!< 0 == Disable, 1 == Enable */ + bool resync_en; /*!< 0 == Disable, 1 == Enable */ + bool ts_rst_en; /*!< 0 == Disable, 1 == Enable */ + bool tzero_coher_en; /*!< 0 == Disable, 1 == Enable */ +} adi_apollo_dyn_recfg_cfg_t; +ADI_APOLLO_PACK_FINISH + + +#define ADI_APOLLO_FDUC0_REPRESENTATION_IN_CDUC_SUMMER 0x01 /*!< Both 4T4R and 8T8R */ +#define ADI_APOLLO_FDUC1_REPRESENTATION_IN_CDUC_SUMMER 0x02 /*!< Both 4T4R and 8T8R */ +#define ADI_APOLLO_FDUC2_REPRESENTATION_IN_CDUC_SUMMER 0x04 /*!< Both 4T4R and 8T8R */ +#define ADI_APOLLO_FDUC3_REPRESENTATION_IN_CDUC_SUMMER 0x08 /*!< Both 4T4R and 8T8R */ +#define ADI_APOLLO_FDUC4_REPRESENTATION_IN_CDUC_SUMMER 0x10 /*!< Only 8T8R */ +#define ADI_APOLLO_FDUC5_REPRESENTATION_IN_CDUC_SUMMER 0x20 /*!< Only 8T8R */ +#define ADI_APOLLO_FDUC6_REPRESENTATION_IN_CDUC_SUMMER 0x40 /*!< Only 8T8R */ +#define ADI_APOLLO_FDUC7_REPRESENTATION_IN_CDUC_SUMMER 0x80 /*!< Only 8T8R */ + + +/** + * \brief Tx Mux1 (Mod Switch) Control Enumeration + */ +typedef enum adi_apollo_tx_mux1_sel { + ADI_APOLLO_4T4R_MODSW0_OUT0_FROM_I0_OUT1_FROM_I1 = 0u, /*!< DAC0 = CNCO_[Side]0_I, DAC1 = CNCO_[Side]1_I */ + ADI_APOLLO_4T4R_MODSW0_OUT0_FROM_I0I1_OUT1_FROM_Q0Q1 = 1u, /*!< DAC0 = CNCO_[Side]0_I + CNCO_[Side]1_I, DAC1 = CNCO_[Side]0_Q + CNCO_[Side]1_Q */ + ADI_APOLLO_4T4R_MODSW0_OUT0_FROM_I0_OUT1_FROM_Q0 = 2u, /*!< DAC0 = CNCO_[Side]0_I, DAC1 = CNCO_[Side]0_Q */ + ADI_APOLLO_4T4R_MODSW0_OUT0_FROM_I1_OUT1_FROM_Q1 = 3u, /*!< DAC0 = CNCO_[Side]1_I, DAC1 = CNCO_[Side]1_Q */ + + ADI_APOLLO_8T8R_MODSW0_OUT0_FROM_I0_OUT1_FROM_I2 = 0u, /*!< DAC0 = CNCO_[Side]0_I, DAC1 = CNCO_[Side]2_I */ + ADI_APOLLO_8T8R_MODSW0_OUT0_FROM_I0I2_OUT1_FROM_Q0Q2 = 1u, /*!< DAC0 = CNCO_[Side]0_I + CNCO_[Side]2_I, DAC1 = CNCO_[Side]0_Q + CNCO_[Side]2_Q */ + ADI_APOLLO_8T8R_MODSW0_OUT0_FROM_I0_OUT1_FROM_Q0 = 2u, /*!< DAC0 = CNCO_[Side]0_I, DAC1 = CNCO_[Side]0_Q */ + ADI_APOLLO_8T8R_MODSW0_OUT0_FROM_I2_OUT1_FROM_Q2 = 3u, /*!< DAC0 = CNCO_[Side]2_I, DAC1 = CNCO_[Side]2_Q */ + + ADI_APOLLO_8T8R_MODSW1_OUT2_FROM_I1_OUT3_FROM_I3 = 0u, /*!< DAC2 = CNCO_[Side]1_I, DAC3 = CNCO_[Side]3_I */ + ADI_APOLLO_8T8R_MODSW1_OUT2_FROM_I1I3_OUT3_FROM_Q1Q3 = 1u, /*!< DAC2 = CNCO_[Side]1_I + CNCO_[Side]3_I, DAC3 = CNCO_[Side]1_Q + CNCO_[Side]3_Q */ + ADI_APOLLO_8T8R_MODSW1_OUT2_FROM_I1_OUT3_FROM_Q1 = 2u, /*!< DAC2 = CNCO_[Side]1_I, DAC3 = CNCO_[Side]1_Q */ + ADI_APOLLO_8T8R_MODSW1_OUT2_FROM_I3_OUT3_FROM_Q3 = 3u /*!< DAC2 = CNCO_[Side]3_I, DAC3 = CNCO_[Side]3_Q */ +} ADI_APOLLO_PACK_ENUM adi_apollo_tx_mux1_sel_e; + +/** + * \brief Tx Mux1 (Mod Switch) Index Enumeration + */ +typedef enum adi_apollo_tx_mux1_idx { + ADI_APOLLO_4T4R_MODSW0 = 0u, /*!< 4t4r Mod Switch 0 Index */ + ADI_APOLLO_8T8R_MODSW0 = 0u, /*!< 8t8r Mod Switch 0 Index */ + ADI_APOLLO_8T8R_MODSW1 = 1u, /*!< 8t8r Mod Switch 1 Index */ + ADI_APOLLO_TX_MUX1_NUM_4T4R = 1u, /*!< 4t4r has only 1 index */ + ADI_APOLLO_TX_MUX1_NUM_8T8R = 2u /*!< Both modsw0 and modsw1 bit fields are in register dp_cfg */ +} ADI_APOLLO_PACK_ENUM adi_apollo_tx_mux1_idx_e; + +/** + * \brief High-speed cross bar control Mod Switch or ADC to DAC + */ +typedef enum adi_apollo_tx_mux0_sel { + ADI_APOLLO_4T4R_DAC_FROM_MODSW0_OUT0 = 0u, + ADI_APOLLO_4T4R_DAC_FROM_MODSW0_OUT1 = 1u, + ADI_APOLLO_8T8R_DAC_FROM_MODSW0_OUT0 = 0u, + ADI_APOLLO_8T8R_DAC_FROM_MODSW0_OUT1 = 1u, + ADI_APOLLO_8T8R_DAC_FROM_MODSW1_OUT0 = 2u, + ADI_APOLLO_8T8R_DAC_FROM_MODSW1_OUT1 = 3u, + ADI_APOLLO_4T4R_LOOPBACK_DAC_FROM_ADC0 = 0u, + ADI_APOLLO_4T4R_LOOPBACK_DAC_FROM_ADC1 = 1u, + ADI_APOLLO_8T8R_LOOPBACK_DAC_FROM_ADC0 = 0u, + ADI_APOLLO_8T8R_LOOPBACK_DAC_FROM_ADC1 = 1u, + ADI_APOLLO_8T8R_LOOPBACK_DAC_FROM_ADC2 = 2u, + ADI_APOLLO_8T8R_LOOPBACK_DAC_FROM_ADC3 = 3u +} ADI_APOLLO_PACK_ENUM adi_apollo_tx_mux0_sel_e; + + +/** + * \brief Tx Path Misc Config Structure + */ +ADI_APOLLO_PACK_START +typedef struct adi_apollo_txpath_misc { + uint8_t cduc_dac_enables[ADI_APOLLO_CDUC_PATHS_PER_SIDE]; /*!< 1xNx XBar Control, onlt used when FDUCs are bypassed. */ + uint8_t fduc_cduc_summer[ADI_APOLLO_CDUC_PATHS_PER_SIDE]; /*!< FDUC to CDUC summer blocks. */ + /*!< If fduc_cduc_summer[0] = FDUC0_REPRESENTATION_IN_CDUC_SUMMER + FDUC1_REPRESENTATION_IN_CDUC_SUMMER, + Then the CDUC 0 input will be the sum of FDUC 0 and FDUC 1. In Yoda, the registers are enables00, enables01, enables10, enables11 */ + + adi_apollo_tx_mux1_sel_e mux1_sel[ADI_APOLLO_TX_MUX1_NUM_8T8R]; /*!< Mod Switch controls */ + adi_apollo_tx_mux0_sel_e mux0_sel[ADI_APOLLO_CDUC_PATHS_PER_SIDE]; /*!< Each of these occupy two bits in register hs_xbar_ctrl */ + bool low_samp_en; /*!< Tx_Top.Tx_Misc.low_samp, TRUE: enable low sampling */ +} adi_apollo_txpath_misc_t; +ADI_APOLLO_PACK_FINISH + + +/** + * \brief PA Protect Power Detector Config Structure + */ +ADI_APOLLO_PACK_START +typedef struct adi_apollo_paprot_pwr_cfg { + bool pa_clk_en; /*!< True to enable when TxEN is low */ + bool short_pac_en; /*!< True to enable */ + bool long_pac_en; /*!< True to enable */ + uint16_t pwr_threshold_long; /*!< 13Bits for the long window average power threshold */ + uint16_t pwr_threshold_short; /*!< 13Bits for the short window average power threshold */ + uint8_t avg_long_win; /*!< 4Bits for 2 ** (9+avg_long_win) sample count */ + uint8_t avg_short_win; /*!< 2Bits for 2 ** (3+avg_short_win) sample count */ +} adi_apollo_paprot_pwr_cfg_t; +ADI_APOLLO_PACK_FINISH + + +/** + * \brief PA Protect Zero Flush from PA to FDUC Select + */ +typedef enum adi_apollo_paprot_zf_sel { + ADI_APOLLO_PAPROT_ZF_SEL_F0_P0 = 0u, + ADI_APOLLO_PAPROT_ZF_SEL_F2_P0 = 1u, + ADI_APOLLO_PAPROT_ZF_SEL_F1_P0 = 2u, + ADI_APOLLO_PAPROT_ZF_SEL_F3_P0 = 3u +} ADI_APOLLO_PACK_ENUM adi_apollo_paprot_zf_sel_e; + + +/** + * \brief PA Protect JESD and Data Ready Select + */ +typedef enum adi_apollo_paprot_jesd_dr_sel { + ADI_APOLLO_PAPROT_JESD_DF_SEL_L0 = 0u, + ADI_APOLLO_PAPROT_JESD_DF_SEL_L1 = 1u, + ADI_APOLLO_PAPROT_JESD_DF_SEL_BOTH = 2u +} ADI_APOLLO_PACK_ENUM adi_apollo_paprot_jesd_dr_sel_e; + + +/** + * \brief PA Protect State Machine Control Config Structure + */ +ADI_APOLLO_PACK_START +typedef struct adi_apollo_paprot_sm_cfg { + bool enable_paprotsm; /*!< 1: Enable the PA protection state machine. The PA protection fsm is the main control of the PA protection algorithm. It monitors alarms and initiate ramp up/down when necessary. */ + bool rampdwn_to_papin_en; /*!< 1: Will bring the RAMP down signal out on PA_EN pins. 0: The PA_EN signal will come out of txen power ctrl machine */ + bool srl_err_en; /*!< 1: Enable the slew rate errors to trigger an alarm when the measured slew rate is higher than a threshold. 0: will not trigger a ramp down. */ + bool avg_pwr_err_en; /*!< 1: Enable the average power to trigger an alarm when measured power is higher than a threshold. 0: will not trigger a ramp down. */ + bool auto_dyn_recfg_en; /*!< 1: dyn reconfig triggers ramps. 0: dyn reconfig would not trigger the ramps. */ + bool jesd_err_en; /*!< 1: Enable the JESD errors to trigger an alarm. */ + bool jesd_err_auto_cfg_en; /*!< Allow the JESD errors to be automatically routed to different RAMPS based on JESD parameters. */ + bool data_ready_auto_cfg_en; /*!< Allow the data_ready to be automatically routed to different RAMPS based on JESD parameters. */ + bool zero_flush_clock_stable_rise_en; /*!< Enable Zero Flushing On Rising Edge of Clock Stable. Zero Flushing Will Stop After ZERO_FLUSH_TIMER Clock Cycles. */ + bool zero_flush_dyn_recfg_ramp_up_en; /*!< Enable Zero Flushing Before Ramp Up Via Dynamic Reconfiguration. PAPROT SM Must be Enabled. Zero Flushing Will Stop After ZERO_FLUSH_TIMER Clock Cycles. */ + bool zero_flush_txen_fall_en; /*!< Enable Zero Flushing on Falling Edge of TXEN. Zero Flushing Will Stop After ZERO_FLUSH_TIMER Clock Cycles. */ + bool zero_flush_txen_rise_en; /*!< Enable Zero Flushing on Rising Edge of TXEN. Zero Flushing Will Stop After ZERO_FLUSH_TIMER Clock Cycles. */ + bool zero_flush_start_en; /*!< Enable Zero Flushing After Initial Power Up and Clock Synchronization Sequence. Zero Flushing Will Stop After ZERO_FLUSH_TIMER Clock Cycles. */ + bool drive_sm_by_dig_en; /*!< 1: dig_en from txen power control is driving the PA protect SM. 0: TXEN from pins will be driving the SM. */ + bool hold_sample_en; /*!< 1: Enable the function that will allow user to hold the last good sample. */ + bool skip_ramp_up; /*!< 1: The ramp up event in the SM will be disabled i.e. skip the ramp up state and jump to operation state. */ + bool skip_ramp_down; /*!< 1: The ramp down event in the SM will be disabled i.e. skip the ramp down state and jump to operation state. */ + bool ramp_up_timer_en; /*!< Enable the ramp up timer. */ + bool ramp_dwn_timer_en; /*!< Enable the ramp down timer. */ + uint16_t zero_flush_timer; /*!< 13Bits Zero Flush timer */ + uint16_t ramp_down_timer_val; /*!< 16Bits Ramp Down timer */ + uint16_t ramp_up_timer_val; /*!< 16Bits Ramp Up timer */ + adi_apollo_paprot_zf_sel_e dp_zero_flush_sel_0; /*!< Select Zero Flush from PA to FDUC Mapping. */ + adi_apollo_paprot_zf_sel_e dp_zero_flush_sel_1; /*!< Select Zero Flush from PA to FDUC Mapping. */ + adi_apollo_paprot_jesd_dr_sel_e data_ready_sel_ramp; /*!< The select bit for mapping data_ready[1:0] to the different RAMP paths. */ + adi_apollo_paprot_jesd_dr_sel_e jesd_err_sel_ramp; /*!< The select bit for mapping jesd_err[1:0] to the different RAMP paths. */ +} adi_apollo_paprot_sm_cfg_t; +ADI_APOLLO_PACK_FINISH + + +/** + * \brief PAProt Ramp Control Config Structure + */ +ADI_APOLLO_PACK_START +typedef struct adi_apollo_paprot_ramp_cfg { + bool gain_clk_en; /*!< True to enable when TxEN is low */ + bool zero_detect_en; /*!< Enable the ramp up only when non-zero data is detected and this bit is enabled. */ + bool force_ramps_dyn_recfg_en; /*!< Enable the ramps from dynamic reconfig controller bypassing PA protect SM. */ + bool force_ramp_up_en; /*!< Enable the manual forcing of a ramp up. */ + bool force_ramp_dwn_en; /*!< Enable the manual forcing of a ramp down. */ + bool enable_gain; /*!< True to enable the gain */ + bool enable_ramp; /*!< Enable the ramping up and down of the gain steps. When this bit is set to 0 the multiplier gain value is fixed to the programmed GAIN_VALUE. When the ramp_en is asserted the gain block is automatically enabled. */ + bool trig_ramp_together; /*!< Enable simultaneous ramp up and ramp down of IQ pairs. */ + uint8_t gain_inc_step; /*!< 8Bits for the gain increase step for PA protection RAMP up process. */ + uint8_t gain_dec_step; /*!< 8Bits for the gain decrease step for PA protection RAMP down process. */ + uint8_t gain_max_val; /*!< 8Bits for the maximum gain value that data will be multiplied w/ after ramp up is completed ie: DAC = data*max_gain. */ +} adi_apollo_paprot_ramp_cfg_t; +ADI_APOLLO_PACK_FINISH + + +/** + * \brief PAProt Slew Rate Config Structure + */ +ADI_APOLLO_PACK_START +typedef struct adi_apollo_paprot_sr_cfg { + bool sr_clk_en; /*!< True to enable when TxEN is low */ + bool sr_err_self_clr_en; /*!< True to enable the slew rate detector error self clear */ + bool sr_calculation_en; /*!< True to enable slew rate calculations */ + bool slew_rate_err_irq_en; /*!< True to enable slew rate error IRQ */ + uint8_t sr_path_sel; /*!< 5Bits for the which of the 32 calculated values are read back */ + uint32_t sr_threshold; /*!< 17Bits for the slew rate threshold */ +} adi_apollo_paprot_sr_cfg_t; +ADI_APOLLO_PACK_FINISH + + +/** + * \brief PA Protect Config Structure + */ +ADI_APOLLO_PACK_START +typedef struct adi_apollo_paprot_cfg { + bool pa_clkdiv_en; /*!< True to enable */ + adi_apollo_paprot_pwr_cfg_t paprot_pwr_cfg; /*!< PAProt Power Detector Configuration */ + adi_apollo_paprot_sm_cfg_t paprot_sm_cfg; /*!< PAProt State Machine Configuration */ + adi_apollo_paprot_ramp_cfg_t paprot_ramp_cfg; /*!< PAProt Ramp Up/Down Configuration */ + adi_apollo_paprot_sr_cfg_t paprot_sr_cfg; /*!< PAProt Slew Rate Configuration */ +} adi_apollo_paprot_cfg_t; +ADI_APOLLO_PACK_FINISH + + +/** + * \brief Rx/Tx Enable Sel Config Structure + */ +ADI_APOLLO_PACK_START +typedef struct adi_apollo_rxtxen_cfg { + bool enable_spien; /*!< Enable SPI Control Bit for Respective Enable. 0 == Disable, 1 == Enable */ + bool enable_spi; /*!< SPI Control Bit Instead of GPIO for Respective Enable. This Value is Used Only If Respective ENABLE_SPIEN Bit is Set to 1. */ + bool enable_pol; /*!< Polarity Selection for Respective Enable. 0 == Active High, 1 == Active Low */ + uint8_t slice_sel; /*!< 4bits - Select for Slice by Respective Enable. Each Bit Corresponds to Separate Slice. */ + uint8_t pfilt_sel; /*!< 2bits - Select for PFILT Clock Gating by Respective Enable. Each Bit Corresponds to Separate PFILT. */ + uint8_t cdrc_sel; /*!< 4bits - Select for CDRC Clock Gating by Respective Enable. Each Bit Corresponds to Separate CDRC. */ + uint8_t fdrc_sel; /*!< 8bits - Select for FDRC Clock Gating by Respective Enable. Each Bit Corresponds to Separate FDRC. */ + uint8_t cfir_sel; /*!< 2bits - Select for CFIR Clock Gating by Respective Enable. Each Bit Corresponds to Separate CFIR. */ + uint8_t fsrc_sel; /*!< 2bits - Select for FSRC Clock Gating by Respective Enable. Each Bit Corresponds to Separate FSRC. */ + uint8_t jesd_link_sel; /*!< 2bits - Select for JESD Link Clock Gating by Respective Enable. Each Bit Corresponds to Separate JESD Link. */ + uint16_t jesd_phy_sel; /*!< 12bits - Select for JRX/JTX PHY Power Down by Respective Enable. Each Bit Corresponds to Separate JRX/JTX PHY. */ + bool modsw_sel; /*!< 0 == Not Selected, 1 == Selected */ + uint8_t invsinc_sel; /*!< 4bits - Select for INVSINC Clock Gating by Respective Enable. Each Bit Corresponds to Separate INVSINC. */ + uint8_t gain_sel; /*!< 4bits - Select for GAIN Control by Respective Enable. Each Bit Corresponds to Separate GAIN. */ + uint8_t srd_sel; /*!< 4bits - Select for Slew Rate Det by Respective Enable. Each Bit Corresponds to Separate SRD. */ +} adi_apollo_rxtxen_cfg_t; +ADI_APOLLO_PACK_FINISH + + +/** + * \brief Rx/Tx Enable Power Sel Options + */ +typedef enum adi_apollo_rxtxen_pwr_sel { + ADI_APOLLO_RXTXEN_PWR_SEL_0 = 0u, /*!< rxtxen[0] to pin_rxtxen */ + ADI_APOLLO_RXTXEN_PWR_SEL_1 = 1u, /*!< rxtxen[1] to pin_rxtxen */ + ADI_APOLLO_RXTXEN_PWR_SEL_2 = 2u, /*!< rxtxen[2] to pin_rxtxen */ + ADI_APOLLO_RXTXEN_PWR_SEL_3 = 3u /*!< rxtxen[3] to pin_rxtxen */ +} ADI_APOLLO_PACK_ENUM adi_apollo_rxtxen_pwr_sel_e; + + +/** + * \brief Rx/Tx Enable Power Rise Options + */ +typedef enum adi_apollo_rxtxen_pwr_rise { + ADI_APOLLO_RXTXEN_PWR_RISE_E0 = 0u, /*!< Signal to rise on E0 */ + ADI_APOLLO_RXTXEN_PWR_RISE_E1 = 1u, /*!< Signal to rise on E1 */ + ADI_APOLLO_RXTXEN_PWR_RISE_E2 = 2u, /*!< Signal to rise on E2 */ + ADI_APOLLO_RXTXEN_PWR_RISE_E3 = 3u /*!< Signal to rise on E3 */ +} ADI_APOLLO_PACK_ENUM adi_apollo_rxtxen_pwr_rise_e; + + +/** + * \brief Rx/Tx Enable Power Fall Options + */ +typedef enum adi_apollo_rxtxen_pwr_fall { + ADI_APOLLO_RXTXEN_PWR_FALL_E4 = 0u, /*!< Signal to fall on E4 */ + ADI_APOLLO_RXTXEN_PWR_FALL_E5 = 1u, /*!< Signal to fall on E5 */ + ADI_APOLLO_RXTXEN_PWR_FALL_E6 = 2u, /*!< Signal to fall on E6 */ + ADI_APOLLO_RXTXEN_PWR_FALL_E7 = 3u /*!< Signal to fall on E7 */ +} ADI_APOLLO_PACK_ENUM adi_apollo_rxtxen_pwr_fall_e; + + +/** + * \brief Rx/Tx Enable Power Control Config Structure + */ +ADI_APOLLO_PACK_START +typedef struct adi_apollo_rxtxen_pwr_cfg { + adi_apollo_rxtxen_pwr_sel_e rxtxen_sel; /*!< These two bits will select which GPIO txen[3:0] bits is selected for the power control input signal. */ + bool spi_rxtxen; /*!< Setting for Rx/Tx Enable. Only in use if spi_rxtxen_ena == 1. 0 == Disable, 1 == Enable. */ + bool spi_rxtxen_ena; /*!< 0 == Use GPIO for Rx/Tx Enable. 1 == Use spi_rxtxen for Rx/Tx Enable. */ + bool sm_en; /*!< 0 == State machine will be bypassed and dac_stanby=~Rx/TxEN, dig_en=Rx/TxEN and pa_en=Rx/TxEN. 1 == Rx/Tx en powerup control state machine is enabled. */ + bool sel_cnt_rate; /*!< Select the txen clock rate to be used. This bit will add the option to run the TXEN power control at a slower rate. Slowing down the clock rate of the state machine counters will allow for a longer wait time between events from E0 to E7. This may be needed in case the datapath becomes longer. A setting of 1 will use the slower clock which is Fs/256 for 4T4R and Fs/128 for 8T8R, while the default of zero will select Fs/32 for 4T4R and Fs/16 for 8T8R. */ + adi_apollo_rxtxen_pwr_fall_e conv_fall; /*!< These bits define the falling edges of conv_en signal with respect to Rx/TxEN falling edges. Note conv_standby is inverted from conv_en. */ + adi_apollo_rxtxen_pwr_rise_e conv_rise; /*!< These bits define the rising edges of conv_en signal with respect to Rx/TxEN rising edges. Note conv_standby is inverted from conv_en. */ + adi_apollo_rxtxen_pwr_fall_e dig_fall; /*!< These bits define the falling edges of dig_en signal with respect to TxEN falling edges. */ + adi_apollo_rxtxen_pwr_rise_e dig_rise; /*!< These bits define the rising edges of dig_en signal with respect to TxEN rising edges. */ + adi_apollo_rxtxen_pwr_fall_e pa_fall; /*!< These bits define the falling edges of pa_en signal with respect to TxEN falling edges. */ + adi_apollo_rxtxen_pwr_rise_e pa_rise; /*!< These bits define the rising edges of pa_en signal with respect to TxEN rising edges. */ + uint8_t count_maxa; /*!< 8bits - Maximum programmed counter value from E0 to E1. */ + uint8_t count_maxb; /*!< 8bits - Maximum programmed counter value from E1 to E2. */ + uint8_t count_maxc; /*!< 8bits - Maximum programmed counter value from E2 to E3. */ + uint8_t count_maxd; /*!< 8bits - Maximum programmed counter value from E4 to E5. */ + uint8_t count_maxe; /*!< 8bits - Maximum programmed counter value from E5 to E6. */ + uint8_t count_maxf; /*!< 8bits - Maximum programmed counter value from E6 to E7. */ +} adi_apollo_rxtxen_pwr_cfg_t; +ADI_APOLLO_PACK_FINISH + + +/** + * \brief TX path configuration + */ +ADI_APOLLO_PACK_START +typedef struct adi_apollo_txpath { + adi_apollo_cduc_cfg_t tx_cduc[ADI_APOLLO_CDUCS_PER_SIDE]; /*!< Coarse digital up converter config */ + adi_apollo_fduc_cfg_t tx_fduc[ADI_APOLLO_FDUCS_PER_SIDE]; /*!< Fine digital up converter config */ + adi_apollo_pfilt_cfg_t tx_pfilt[ADI_APOLLO_PFILTS_PER_SIDE]; /*!< Programmable filters */ + adi_apollo_cfir_cfg_t tx_cfir[ADI_APOLLO_CFIRS_PER_SIDE]; /*!< Complex FIRs */ + adi_apollo_fsrc_cfg_t tx_fsrc; /*!< Fractional sampling rate converters */ + adi_apollo_txpath_misc_t tx_mux_summer_xbar; /*!< Summers. multiplexers, crossbar config */ + adi_apollo_dyn_recfg_cfg_t tx_dyn_recfg; /*!< Dynamic Reconfig Static settings */ + adi_apollo_paprot_cfg_t tx_pa_prot[ADI_APOLLO_CDUC_PATHS_PER_SIDE]; /*!< PA Protect configuration */ + bool inv_sinc_en[ADI_APOLLO_CDUC_PATHS_PER_SIDE]; /*!< Inverse sinc enable */ + adi_apollo_rxtxen_cfg_t tx_enable[ADI_APOLLO_RXTX_ENABLES_PER_SIDE]; /*!< Tx Enable Clock Gating config */ + adi_apollo_rxtxen_pwr_cfg_t tx_power[ADI_APOLLO_RXTX_POWER_CTRL_PER_SIDE]; /*!< Tx Enable Power config */ +} adi_apollo_txpath_t; +ADI_APOLLO_PACK_FINISH + +/*! +* Enumerates the values that two bit fields adc_0_mux_sel, bits 0 and 1 in +* register adc_mux_sel and adc_1_mux_sel, bits 2 and 3 in register adc_mux_sel +* can assume. +* For the case of 4T4R, adc_1_mux_sel does not have any impact, since there are +* only two ADCs on each side. For 8T8R, both of these fields are used and each +* of these fields controls one crossbar. +*/ +typedef enum adi_apollo_rx_mux0_sel { + ADI_APOLLO_4T4R_CB_OUT_0_FROM_ADC0 = 0u, /*!< 4T4R's first (side A or B) adc_mux_sel=00000000 */ + ADI_APOLLO_4T4R_CB_OUT_0_FROM_ADC1 = 1u, /*!< 4T4R's first (side A or B) adc_mux_sel=00000001 */ + ADI_APOLLO_4T4R_CB_OUT_1_FROM_ADC1 = 0u, /*!< 4T4R's second (side A or B) adc_mux_sel=00000000 */ + ADI_APOLLO_4T4R_CB_OUT_1_FROM_ADC0 = 1u, /*!< 4T4R's second (side A or B) adc_mux_sel=00000001 */ + ADI_APOLLO_8T8R_CB_OUT_FROM_ADC0 = 0u, + ADI_APOLLO_8T8R_CB_OUT_FROM_ADC1 = 2u, + ADI_APOLLO_8T8R_CB_OUT_FROM_ADC2 = 1u, + ADI_APOLLO_8T8R_CB_OUT_FROM_ADC3 = 3u +} ADI_APOLLO_PACK_ENUM adi_apollo_rx_mux0_sel_e; + +typedef enum adi_apollo_rx_mux0_idx { + ADI_APOLLO_4T4R_CB_OUT0 = 0u, + ADI_APOLLO_4T4R_CB_OUT1 = 1u, + ADI_APOLLO_8T8R_CB_OUT0 = 0u, + ADI_APOLLO_8T8R_CB_OUT2 = 1u, + ADI_APOLLO_8T8R_CB_OUT1 = 2u, + ADI_APOLLO_8T8R_CB_OUT3 = 3u, + ADI_APOLLO_RX_MUX0_NUM_4T4R = 2u, + ADI_APOLLO_RX_MUX0_NUM_8T8R = 4u +} ADI_APOLLO_PACK_ENUM adi_apollo_rx_mux0_idx_e; + + +/** + * \brief Rx Coarse fine crossbar (MUX2) configuration + */ +typedef enum adi_apollo_rx_mux2_sel { + /* values for FDDC0 (and FDDC4 in 8T8R) */ + ADI_APOLLO_CB_4T4R_C0_TO_F0 = 0u, /*!< 4T4R: CDDC 0 goes to FDDC 0 */ + ADI_APOLLO_CB_4T4R_C1_TO_F0 = 4u, /*!< 4T4R: CDDC 1 goes to FDDC 0 */ + ADI_APOLLO_CB_8T8R_C0_C2_TO_F0_F4 = 0u, /*!< 8T8R: CDDC 0 goes to FDDC 0 and CDDC 2 goes to FDDC 4 */ + ADI_APOLLO_CB_8T8R_C2_C0_TO_F0_F4 = 1u, /*!< 8T8R: CDDC 2 goes to FDDC 0 and CDDC 0 goes to FDDC 4 */ + ADI_APOLLO_CB_8T8R_C0_TO_F0_F4 = 2u, /*!< 8T8R: CDDC 0 goes to both FDDC 0 and FDDC 4 */ + ADI_APOLLO_CB_8T8R_C2_TO_F0_F4 = 3u, /*!< 8T8R: CDDC 2 goes to both FDDC 0 and FDDC 4 */ + ADI_APOLLO_CB_8T8R_C1_C3_TO_F0_F4 = 4u, /*!< 8T8R: CDDC 1 goes to FDDC 0 and CDDC 3 goes to FDDC 4 */ + ADI_APOLLO_CB_8T8R_C3_C1_TO_F0_F4 = 5u, /*!< 8T8R: CDDC 3 goes to FDDC 0 and CDDC 1 goes to FDDC 4 */ + ADI_APOLLO_CB_8T8R_C1_TO_F0_F4 = 6u, /*!< 8T8R: CDDC 1 goes to both FDDC 0 and FDDC 4 */ + ADI_APOLLO_CB_8T8R_C3_TO_F0_F4 = 7u, /*!< 8T8R: CDDC 3 goes to both FDDC 0 and FDDC 4 */ + + /* values for FDDC1 (and FDDC5 in 8T8R) */ + ADI_APOLLO_CB_4T4R_C0_TO_F1 = 0u, /*!< 4T4R: CDDC 0 goes to FDDC 1 */ + ADI_APOLLO_CB_4T4R_C1_TO_F1 = 4u, /*!< 4T4R: CDDC 1 goes to FDDC 1 */ + ADI_APOLLO_CB_8T8R_C0_C2_TO_F1_F5 = 0u, /*!< 8T8R: CDDC 0 goes to FDDC 1 and CDDC 2 goes to FDDC 5 */ + ADI_APOLLO_CB_8T8R_C2_C0_TO_F1_F5 = 1u, /*!< 8T8R: CDDC 2 goes to FDDC 1 and CDDC 0 goes to FDDC 5 */ + ADI_APOLLO_CB_8T8R_C0_TO_F1_F5 = 2u, /*!< 8T8R: CDDC 0 goes to both FDDC 1 and FDDC 5 */ + ADI_APOLLO_CB_8T8R_C2_TO_F1_F5 = 3u, /*!< 8T8R: CDDC 2 goes to both FDDC 1 and FDDC 5 */ + ADI_APOLLO_CB_8T8R_C1_C3_TO_F1_F5 = 4u, /*!< 8T8R: CDDC 1 goes to FDDC 1 and CDDC 3 goes to FDDC 5 */ + ADI_APOLLO_CB_8T8R_C3_C1_TO_F1_F5 = 5u, /*!< 8T8R: CDDC 3 goes to FDDC 1 and CDDC 1 goes to FDDC 5 */ + ADI_APOLLO_CB_8T8R_C1_TO_F1_F5 = 6u, /*!< 8T8R: CDDC 1 goes to both FDDC 1 and FDDC 5 */ + ADI_APOLLO_CB_8T8R_C3_TO_F1_F5 = 7u, /*!< 8T8R: CDDC 3 goes to both FDDC 1 and FDDC 5 */ + + /* values for FDDC2 (and FDDC6 in 8T8R) */ + ADI_APOLLO_CB_4T4R_C0_TO_F2 = 0u, /*!< 4T4R: CDDC 0 goes to FDDC 2 */ + ADI_APOLLO_CB_4T4R_C1_TO_F2 = 4u, /*!< 4T4R: CDDC 1 goes to FDDC 2 */ + ADI_APOLLO_CB_8T8R_C0_C2_TO_F2_F6 = 0u, /*!< 8T8R: CDDC 0 goes to FDDC 2 and CDDC 2 goes to FDDC 6 */ + ADI_APOLLO_CB_8T8R_C2_C0_TO_F2_F6 = 1u, /*!< 8T8R: CDDC 2 goes to FDDC 2 and CDDC 0 goes to FDDC 6 */ + ADI_APOLLO_CB_8T8R_C0_TO_F2_F6 = 2u, /*!< 8T8R: CDDC 0 goes to both FDDC 2 and FDDC 6 */ + ADI_APOLLO_CB_8T8R_C2_TO_F2_F6 = 3u, /*!< 8T8R: CDDC 2 goes to both FDDC 2 and FDDC 6 */ + ADI_APOLLO_CB_8T8R_C1_C3_TO_F2_F6 = 4u, /*!< 8T8R: CDDC 1 goes to FDDC 2 and CDDC 3 goes to FDDC 6 */ + ADI_APOLLO_CB_8T8R_C3_C1_TO_F2_F6 = 5u, /*!< 8T8R: CDDC 3 goes to FDDC 2 and CDDC 1 goes to FDDC 6 */ + ADI_APOLLO_CB_8T8R_C1_TO_F2_F6 = 6u, /*!< 8T8R: CDDC 1 goes to both FDDC 2 and FDDC 6 */ + ADI_APOLLO_CB_8T8R_C3_TO_F2_F6 = 7u, /*!< 8T8R: CDDC 3 goes to both FDDC 2 and FDDC 6 */ + + /* values for FDDC3 (and FDDC7 in 8T8R) */ + ADI_APOLLO_CB_4T4R_C0_TO_F3 = 0u, /*!< 4T4R: CDDC 0 goes to FDDC 3 */ + ADI_APOLLO_CB_4T4R_C1_TO_F3 = 4u, /*!< 4T4R: CDDC 1 goes to FDDC 3 */ + ADI_APOLLO_CB_8T8R_C0_C2_TO_F3_F7 = 0u, /*!< 8T8R: CDDC 0 goes to FDDC 3 and CDDC 2 goes to FDDC 7 */ + ADI_APOLLO_CB_8T8R_C2_C0_TO_F3_F7 = 1u, /*!< 8T8R: CDDC 2 goes to FDDC 3 and CDDC 0 goes to FDDC 7 */ + ADI_APOLLO_CB_8T8R_C0_TO_F3_F7 = 2u, /*!< 8T8R: CDDC 0 goes to both FDDC 3 and FDDC 7 */ + ADI_APOLLO_CB_8T8R_C2_TO_F3_F7 = 3u, /*!< 8T8R: CDDC 2 goes to both FDDC 3 and FDDC 7 */ + ADI_APOLLO_CB_8T8R_C1_C3_TO_F3_F7 = 4u, /*!< 8T8R: CDDC 1 goes to FDDC 3 and CDDC 3 goes to FDDC 7 */ + ADI_APOLLO_CB_8T8R_C3_C1_TO_F3_F7 = 5u, /*!< 8T8R: CDDC 3 goes to FDDC 3 and CDDC 1 goes to FDDC 7 */ + ADI_APOLLO_CB_8T8R_C1_TO_F3_F7 = 6u, /*!< 8T8R: CDDC 1 goes to both FDDC 3 and FDDC 7 */ + ADI_APOLLO_CB_8T8R_C3_TO_F3_F7 = 7u /*!< 8T8R: CDDC 3 goes to both FDDC 3 and FDDC 7 */ +} ADI_APOLLO_PACK_ENUM adi_apollo_rx_mux2_sel_e; + +typedef enum adi_apollo_rx_mux2_idx { + ADI_APOLLO_4T4R_FDDC0 = 0u, + ADI_APOLLO_4T4R_FDDC1 = 1u, + ADI_APOLLO_4T4R_FDDC2 = 2u, + ADI_APOLLO_4T4R_FDDC3 = 3u, + ADI_APOLLO_8T8R_FDDC0_4 = 0u, + ADI_APOLLO_8T8R_FDDC1_5 = 1u, + ADI_APOLLO_8T8R_FDDC2_6 = 2u, + ADI_APOLLO_8T8R_FDDC3_7 = 3u, + ADI_APOLLO_RX_MUX2_NUM = 4u +} ADI_APOLLO_PACK_ENUM adi_apollo_rx_mux2_idx_e; + + +/** + * \brief Rx Path Misc Config Structure + */ +ADI_APOLLO_PACK_START +typedef struct adi_apollo_rxpath_misc { + adi_apollo_rx_mux0_sel_e mux0_out_adc_sel[ADI_APOLLO_RX_MUX0_NUM_8T8R]; /*!< ADC to CB_out multiplexer (RX MUX0) select. Register name for programming is adc_mux_sel */ + adi_apollo_rx_mux2_sel_e mux2_fddc_input_sel[ADI_APOLLO_RX_MUX2_NUM]; /*!< Coarse to fine crossbar (RX MUX2) config */ + bool low_samp_en; /*!< Rx_Misc.low_samp, TRUE: enable low sampling */ +} adi_apollo_rxpath_misc_t; +ADI_APOLLO_PACK_FINISH + +typedef enum adi_apollo_rx_tmode_sel { + /* + dformat_tmode_sel_0[0] = 4T4R Converter 0 enable/8T8T Converter 0/1 enable: + 1'b0: disable + 1'b1 enable + dformat_tmode_sel_0[1] = 4T4R Converter 1 enable/8T8T Converter 2/3 enable: + 1'b0: disable + 1'b1 enable + dformat_tmode_sel_0[2] = 4T4R Converter 2 enable/8T8T Converter 4/5 enable: + 1'b0: disable + 1'b1 enable + dformat_tmode_sel_0[3] = 4T4R Converter 3 enable/8T8T Converter 6/7 enable: + 1'b0: disable + 1'b1 enable + dformat_tmode_sel_0[4] = 4T4R Converter 4 enable/8T8T Converter 8/9 enable: + 1'b0: disable + 1'b1 enable + dformat_tmode_sel_0[5] = 4T4R Converter 5 enable/8T8T Converter 10/11 enable: + 1'b0: disable + 1'b1 enable + dformat_tmode_sel_0[6] = 4T4R Converter 6 enable/8T8T Converter 12/13 enable: + 1'b0: disable + 1'b1 enable + dformat_tmode_sel_0[7] = 4T4R Converter 7 enable/8T8T Converter 14/15 enable: + 1'b0: disable + 1'b1 enable + */ + ADI_APOLLO_RX_4T4R_TMODE_SEL_CONV_DISABLE = 0u, + ADI_APOLLO_RX_4T4R_TMODE_SEL_CONV_0_ENABLE = 1u, + ADI_APOLLO_RX_4T4R_TMODE_SEL_CONV_1_ENABLE = 2u, + ADI_APOLLO_RX_4T4R_TMODE_SEL_CONV_2_ENABLE = 4u, + ADI_APOLLO_RX_4T4R_TMODE_SEL_CONV_3_ENABLE = 8u, + ADI_APOLLO_RX_4T4R_TMODE_SEL_CONV_4_ENABLE = 16u, + ADI_APOLLO_RX_4T4R_TMODE_SEL_CONV_5_ENABLE = 32u, + ADI_APOLLO_RX_4T4R_TMODE_SEL_CONV_6_ENABLE = 64u, + ADI_APOLLO_RX_4T4R_TMODE_SEL_CONV_7_ENABLE = 128u, + + ADI_APOLLO_RX_8T8R_TMODE_SEL_CONV_DISABLE = 0u, + ADI_APOLLO_RX_8T8R_TMODE_SEL_CONV_01_ENABLE = 1u, + ADI_APOLLO_RX_8T8R_TMODE_SEL_CONV_23_ENABLE = 2u, + ADI_APOLLO_RX_8T8R_TMODE_SEL_CONV_45_ENABLE = 4u, + ADI_APOLLO_RX_8T8R_TMODE_SEL_CONV_67_ENABLE = 8u, + ADI_APOLLO_RX_8T8R_TMODE_SEL_CONV_89_ENABLE = 16u, + ADI_APOLLO_RX_8T8R_TMODE_SEL_CONV_AB_ENABLE = 32u, + ADI_APOLLO_RX_8T8R_TMODE_SEL_CONV_CD_ENABLE = 64u, + ADI_APOLLO_RX_8T8R_TMODE_SEL_CONV_EF_ENABLE = 128u, +} ADI_APOLLO_PACK_ENUM adi_apollo_rx_tmode_sel_e; + +/** + * \brief Test Mode Type Selection Enumeration + */ +typedef enum adi_apollo_rx_tmode_type_sel { + ADI_APOLLO_TMODE_TYPE_SEL_NORM = 0u, /*!< Normal Mode: TMode off */ + ADI_APOLLO_TMODE_TYPE_SEL_MIDSCALE = 1u, /*!< Midscale */ + ADI_APOLLO_TMODE_TYPE_SEL_POS_FS = 2u, /*!< Positive Fullscale */ + ADI_APOLLO_TMODE_TYPE_SEL_NEG_FS = 3u, /*!< Negative Fullscale */ + ADI_APOLLO_TMODE_TYPE_SEL_ACB = 4u, /*!< Alternating Checkerboard */ + ADI_APOLLO_TMODE_TYPE_SEL_PN23 = 5u, /*!< Pseudo Random Number 23 */ + ADI_APOLLO_TMODE_TYPE_SEL_PN9 = 6u, /*!< Pseudo Random Number 9 */ + ADI_APOLLO_TMODE_TYPE_SEL_WT = 7u, /*!< Word Toggle */ + ADI_APOLLO_TMODE_TYPE_SEL_USR = 8u, /*!< User Data Pattern */ + ADI_APOLLO_TMODE_TYPE_SEL_PN7 = 9u, /*!< Pseudo Random Number 7 */ + ADI_APOLLO_TMODE_TYPE_SEL_PN15 = 10u, /*!< Pseudo Random Number 15 */ + ADI_APOLLO_TMODE_TYPE_SEL_PN31 = 11u, /*!< Pseudo Random Number 31 */ + ADI_APOLLO_TMODE_TYPE_SEL_RAMP = 15u /*!< Sample Ramp */ +} ADI_APOLLO_PACK_ENUM adi_apollo_rx_tmode_type_sel_e; + +/** + * \brief Rx Test Mode Resolution Enumeration + */ +typedef enum adi_apollo_rx_tmode_res { + ADI_APOLLO_RX_TMODE_RES_16B = 0u, /*!< 16 Bit */ + ADI_APOLLO_RX_TMODE_RES_15B = 1u, /*!< 15 Bit */ + ADI_APOLLO_RX_TMODE_RES_14B = 2u, /*!< 14 Bit */ + ADI_APOLLO_RX_TMODE_RES_13B = 3u, /*!< 13 Bit */ + ADI_APOLLO_RX_TMODE_RES_12B = 4u /*!< 12 Bit */ +} ADI_APOLLO_PACK_ENUM adi_apollo_rx_tmode_res_e; + + +/** + * \brief Dformat Test Mode Config Structure + */ +ADI_APOLLO_PACK_START +typedef struct adi_apollo_tmode_cfg { + adi_apollo_rx_tmode_sel_e sel; /*!< Tmode Data Routing Selection */ + adi_apollo_rx_tmode_type_sel_e type_sel; /*!< Tmode Data Type Selection */ + bool pn_force_rst; /*!< True to reset pn gen */ + bool flush; /*!< True to enable sync reset of I path */ + bool usr_pat_sel; /*!< Tmode Single or Continuous Pattern Selection */ + adi_apollo_rx_tmode_res_e res; /*!< Tmode Resolution */ +} adi_apollo_tmode_cfg_t; +ADI_APOLLO_PACK_FINISH + + +/** + * \brief Rate Match Fifo Config Structure + */ +ADI_APOLLO_PACK_START +typedef struct adi_apollo_rm_fifo_cfg { + bool invalid_en; /*!< True to enable invalid sample insertion */ + bool sample_repeat_en; /*!< True to enable sample repeat */ +} adi_apollo_rm_fifo_cfg_t; +ADI_APOLLO_PACK_FINISH + +/** + * \brief RX Data Format Selection Enumeration + */ +typedef enum adi_apollo_rx_dformat_sel { + ADI_APOLLO_RX_DFORMAT_SEL_2COMP = 0u, /*!< 2's Complement */ + ADI_APOLLO_RX_DFORMAT_SEL_OFF_BIN = 1u, /*!< Offset Binary */ + ADI_APOLLO_RX_DFORMAT_SEL_GRAY = 2u /*!< Gray Code */ +} ADI_APOLLO_PACK_ENUM adi_apollo_rx_dformat_sel_e; + +/** + * \brief Rx Data Format Resolution Enumeration + */ +typedef enum adi_apollo_rx_dformat_res { + ADI_APOLLO_RX_DFORMAT_RES_16B = 0u, /*!< 16 Bit */ + ADI_APOLLO_RX_DFORMAT_RES_15B = 1u, /*!< 15 Bit */ + ADI_APOLLO_RX_DFORMAT_RES_14B = 2u, /*!< 14 Bit */ + ADI_APOLLO_RX_DFORMAT_RES_13B = 3u, /*!< 13 Bit */ + ADI_APOLLO_RX_DFORMAT_RES_12B = 4u, /*!< 12 Bit */ + ADI_APOLLO_RX_DFORMAT_RES_11B = 5u, /*!< 11 Bit */ + ADI_APOLLO_RX_DFORMAT_RES_10B = 6u, /*!< 10 Bit */ + ADI_APOLLO_RX_DFORMAT_RES_9B = 7u, /*!< 9 Bit */ + ADI_APOLLO_RX_DFORMAT_RES_8B = 8u, /*!< 8 Bit */ + ADI_APOLLO_RX_DFORMAT_RES_7B = 9u /*!< 7 Bit */ +} ADI_APOLLO_PACK_ENUM adi_apollo_rx_dformat_res_e; + + +/** + * \brief Dformat Config Structure + */ +ADI_APOLLO_PACK_START +typedef struct adi_apollo_dformat_cfg { + bool inv; /*!< True to invert ADC sample data */ + adi_apollo_rx_dformat_sel_e sel; /*!< Dformat Output Data Selection */ + bool ddc_dither_en; /*!< True to enable ddc dither */ + adi_apollo_rx_dformat_res_e res; /*!< Dformat Resolution */ + adi_apollo_tmode_cfg_t tmode; /*!< Tmode config */ + adi_apollo_rm_fifo_cfg_t rm_fifo; /*!< Rate Match Fifo config */ +} adi_apollo_dformat_cfg_t; +ADI_APOLLO_PACK_FINISH + + +/** + * \brief Valid SMON JESD Link Selections + */ +typedef enum adi_apollo_rx_smon_jlink_sel { + ADI_APOLLO_RX_SMON_JLINK_SEL0 = 0, + ADI_APOLLO_RX_SMON_JLINK_SEL1 = 1u +} ADI_APOLLO_PACK_ENUM adi_apollo_rx_smon_jlink_sel_e; + + +/** + * \brief Valid SMON Framer Modes + */ +typedef enum adi_apollo_rx_smon_framer_mode { + ADI_APOLLO_RX_SMON_FRAMER_MODE_10B = 0u, + ADI_APOLLO_RX_SMON_FRAMER_MODE_5B = 1u, +} ADI_APOLLO_PACK_ENUM adi_apollo_rx_smon_framer_mode_e; + + +/** + * \brief Valid SMON Sync Next Modes + */ +typedef enum adi_apollo_rx_smon_sync { + ADI_APOLLO_RX_SMON_SYNC_CONT = 0u, /*!< Continuous Mode. */ + ADI_APOLLO_RX_SMON_SYNC_NEXT = 1u /*!< Next Synchroniztion Mode. */ +} ADI_APOLLO_PACK_ENUM adi_apollo_rx_smon_sync_e; + + +/** + * \brief SMON Config Structure + */ +ADI_APOLLO_PACK_START +typedef struct adi_apollo_smon_cfg { + uint32_t period; /*!< 32Bits Signal Monitor Period. */ + bool gpio_en; /*!< Signal Monitor GPIO Enable. If set, allows GPIO output of peak indication. Peak_en also has to be enabled for this feature. */ + bool peak_en; /*!< Signal Monitor Peak Detector Enable. False: Peak Detector Disabled True: Peak Detector Enabled */ + adi_apollo_rx_smon_jlink_sel_e jlink_sel; /*!< SMON JESD Link Selection. */ + bool sframer_en; /*!< Signal Monitor Serial Framer Enable. */ + adi_apollo_rx_smon_framer_mode_e sframer_mode; /*!< Signal Monitor Serial Framer Mode Selection. */ + bool sync_en; /*!< SMON Synchronization Enable. */ + adi_apollo_rx_smon_sync_e sync_next; /*!< SMON Next Synchronization Mode. */ + uint16_t thresh_high; /*!< 11Bits Signal Monitor GPIO Higher Threshold. */ + uint16_t thresh_low; /*!< 11Bits Signal Monitor GPIO Lower Threshold. */ +} adi_apollo_smon_cfg_t; +ADI_APOLLO_PACK_FINISH + + +/** + * \brief Buffer Memory Sample RAM Access Speed Mode Enumeration + */ +typedef enum adi_apollo_bmem_sram_speed_mode { + ADI_APOLLO_BMEM_SRAM_SPEED_MODE_SLOW = 0u, /*!< Slow Mode for reading out. */ + ADI_APOLLO_BMEM_SRAM_SPEED_MODE_FAST = 1u /*!< Fast Mode for capturing and playing from/to datapath. */ +} ADI_APOLLO_PACK_ENUM adi_apollo_bmem_sram_speed_mode_e; + + + +/** + * \brief Buffer Memory Mode of Operation Enumeration + */ +typedef enum adi_apollo_bmem_mode { + ADI_APOLLO_BMEM_MODE_CAPTURE = 0u, /*!< Capture Mode. BMEM will capture data from the datapath. */ + ADI_APOLLO_BMEM_MODE_DELAY = 1u, /*!< Delay Mode. BMEM will act as a delay buffer for the datapath. */ + ADI_APOLLO_BMEM_MODE_AWG = 2u /*!< Arbitrary Waveform Generation Mode. BMEM will play the loaded vector to the datapath. */ +} ADI_APOLLO_PACK_ENUM adi_apollo_bmem_mode_e; + + + +/** + * \brief Buffer Memory Hop Delay Selection Mode Enumeration + */ +typedef enum adi_apollo_bmem_hop_dly_sel_mode { + ADI_APOLLO_BMEM_HOP_DLY_SEL_MODE_TRIG = 0u, /*!< Hop Delay via Trigger. */ + ADI_APOLLO_BMEM_HOP_DLY_SEL_MODE_GPIO = 1u /*!< Hop Delay via GPIO. */ +} ADI_APOLLO_PACK_ENUM adi_apollo_bmem_hop_dly_sel_mode_e; + + + +/** + * \brief Buffer Memory 8t8r Capture Mask Mode Enumeration + */ +typedef enum adi_apollo_bmem_8t8r_cap_mask { + ADI_APOLLO_BMEM_8T8R_CAP_MASK_ALL_UNMASKED = 0u, /*!< All Converters are Unmasked. */ + ADI_APOLLO_BMEM_8T8R_CAP_MASK_LOWER_MASKED = 1u, /*!< Lower Converters are Masked. */ + ADI_APOLLO_BMEM_8T8R_CAP_MASK_UPPER_MASKED = 2u, /*!< Upper Converters are Masked. */ + ADI_APOLLO_BMEM_8T8R_CAP_MASK_ALL_MASKED = 3u /*!< All Converters are Masked. */ +} ADI_APOLLO_PACK_ENUM adi_apollo_bmem_8t8r_cap_mask_e; + + +/** + * \brief BMEM Config Structure + */ +ADI_APOLLO_PACK_START +typedef struct adi_apollo_bmem_cfg { + adi_apollo_bmem_sram_speed_mode_e fast_nslow_mode; /*!< SRAM Access Mode. */ + bool bmem_shut_down; /*!< True to set SRAM in Shut Down Mode. False to disable Shut Down Mode. */ + bool bmem_sleep; /*!< True to set SRAM in Sleep Mode. False to disable Sleep Mode. */ + adi_apollo_bmem_mode_e bmem_mode; /*!< BMEM Mode of Operation. Capture, Delay, or AWG. */ + bool bmem_en; /*!< True to enable BMEM. */ + adi_apollo_bmem_hop_dly_sel_mode_e hop_dly_sel_mode; /*!< Hop Delay Selection Mode. */ + adi_apollo_bmem_8t8r_cap_mask_e bmem_8t8r_cap_mask; /*!< Disable Capture for none, some, or all converters in 8T8R Mode. */ + bool ramclk_ph_dis; /*!< True to Disable SRAM Clock Phasing */ + bool parity_check_en; /*!< True to Enable Parity Check on Data Read from SRAM. */ + bool trig_mode_en; /*!< True to Enable Hopping via Trigger, False to use start signal. */ + bool trig_mode_sclr_en; /*!< True to Self Clear TRIG_MODE Bit After a Trigger Event. */ + uint16_t sample_dly; /*!< Sample Delay Value in Delay Mode. This Value is Used Only If TRIG_MODE Bit is Set to 0. */ + uint16_t hop_delay0; /*!< Hop Delay Value 0 in Delay Mode. + This Value is Used Only If TRIG_MODE Bit or HOP_DLY_SEL_MODE Bit is Set to 1. If HOP_DLY_SEL_MODE Bit is 1, Hop Delay Value is Selected Based on I_HOP_DLY_SEL Inputs. + If TRIG_MODE Bit is 1, When Trigger Comes from Trigger Master, Hop Delay Value Switches from 0->1->2->3->0 */ + uint16_t hop_delay1; /*!< Hop Delay Value 1 in Delay Mode. */ + uint16_t hop_delay2; /*!< Hop Delay Value 2 in Delay Mode. */ + uint16_t hop_delay3; /*!< Hop Delay Value 3 in Delay Mode. */ +} adi_apollo_bmem_cfg_t; +ADI_APOLLO_PACK_FINISH + + + +/** + * \brief RX path configuration + */ +ADI_APOLLO_PACK_START +typedef struct adi_apollo_rxpath { + adi_apollo_cddc_cfg_t rx_cddc[ADI_APOLLO_CDDCS_PER_SIDE]; /*!< Coarse digital down converter config */ + adi_apollo_fddc_cfg_t rx_fddc[ADI_APOLLO_FDDCS_PER_SIDE]; /*!< Fine digital down converter config */ + adi_apollo_pfilt_cfg_t rx_pfilt[ADI_APOLLO_PFILTS_PER_SIDE]; /*!< Programmable filters */ + adi_apollo_cfir_cfg_t rx_cfir[ADI_APOLLO_CFIRS_PER_SIDE]; /*!< Complex FIRs */ + adi_apollo_fsrc_cfg_t rx_fsrc; /*!< Fractional sampling rate converters */ + adi_apollo_rxpath_misc_t rx_mux_splitter_xbar; /*!< Summers, multiplexers, crossbar config */ + adi_apollo_dyn_recfg_cfg_t rx_dyn_recfg; /*!< Dynamic Reconfig Static settings */ + adi_apollo_dformat_cfg_t rx_dformat[ADI_APOLLO_JESD_LINKS]; /*!< Dformat, Tmode, and RMFifo config */ + adi_apollo_smon_cfg_t rx_smon[ADI_APOLLO_SMONS_PER_SIDE]; /*!< SMON config */ + adi_apollo_rxtxen_cfg_t rx_enable[ADI_APOLLO_RXTX_ENABLES_PER_SIDE]; /*!< Rx Enable Clock Gating config */ + adi_apollo_rxtxen_pwr_cfg_t rx_power[ADI_APOLLO_RXTX_POWER_CTRL_PER_SIDE]; /*!< Rx Enable Power config */ + adi_apollo_bmem_cfg_t rx_bmem[ADI_APOLLO_BMEMS_PER_SIDE]; /*!< BMEM Config*/ +} adi_apollo_rxpath_t; +ADI_APOLLO_PACK_FINISH + + + +/** + * \brief Clock PLL Config + */ +ADI_APOLLO_PACK_START +typedef struct adi_apollo_clk_pll_cfg { + uint32_t loop_bandwidth; /*!< PLL Loop bandwidth */ + uint8_t phase_margin; /*!< PLL Phase Margin */ + uint8_t div_range; /*!< Serdes only Div Range */ + uint8_t div2; /*!< Serdes only Div 2 */ + uint8_t power; /*!< PLL Power setting */ + uint8_t ref_clk_div; /*!< PLL ref clock divider */ + uint8_t i_bleed_en; /*!< PLL bleed ramp enable */ + uint32_t feedback_int; /*!< Integer portion of feedback factor */ + uint32_t feedback_frac; /*!< Fractional portion of feedback factor */ +} adi_apollo_clk_pll_cfg_t; +ADI_APOLLO_PACK_FINISH + + + +/** + * \brief SERDES PLL Config + */ +ADI_APOLLO_PACK_START +typedef struct adi_apollo_serdes_pll_cfg { + uint32_t loop_bandwidth; /*!< PLL Loop bandwidth */ + uint8_t phase_margin; /*!< PLL Phase Margin */ + uint8_t div_range; /*!< Serdes only Div Range */ + uint8_t div2; /*!< Serdes only Div 2 */ + uint8_t power; /*!< PLL Power setting */ + uint8_t ref_clk_div; /*!< PLL ref clock divider */ + uint8_t i_bleed_en; /*!< PLL bleed ramp enable */ + uint8_t serdes_pll_odiv; /*!< Divider value (Yoda reg. name: register serdes_output_divider_ctl) */ + uint32_t feedback_int; /*!< Integer portion of feedback factor */ + uint32_t feedback_frac; /*!< Fractional portion of feedback factor */ +} adi_apollo_serdes_pll_cfg_t; +ADI_APOLLO_PACK_FINISH + + +/** + * \brief Valid Apollo Clocking Modes + */ +typedef enum adi_apollo_divg_mode { + ADI_APOLLO_CLOCKING_MODE_SDR_DIV_8 = 0u, /*!< Single data rate, divide by 8 */ + ADI_APOLLO_CLOCKING_MODE_SDR_DIV_4 = 1u, /*!< Single data rate, divide by 4 */ + ADI_APOLLO_CLOCKING_MODE_DDR_DIV_4 = 2u, /*!< Double data rate, divide by 4 */ + ADI_APOLLO_CLOCKING_MODE_SDR_DIV_4_DDR_DIV_2 = 3u /*!< Single data rate divide by 4 and double data rate divide by 2 */ +} ADI_APOLLO_PACK_ENUM adi_apollo_divg_mode_e; + + +/** + * \brief Valid ARM Clock Side Selection + */ +typedef enum adi_apollo_arm_clock_sel { + ADI_APOLLO_ARM_CLOCK_SEL_A = 0u, /*!< A side */ + ADI_APOLLO_ARM_CLOCK_SEL_B = 1u /*!< B side */ +} ADI_APOLLO_PACK_ENUM adi_apollo_arm_clock_sel_e; + + +/** + * \brief Clock configuration + */ +ADI_APOLLO_PACK_START +typedef struct adi_apollo_clk_cfg { + bool is_dual_clk; /*!< FALSE: Single (Center) clocking, TRUE: Dual clocking */ + bool clk_path_sel; /*!< FALSE: On-chip PLL, TRUE: External clock */ + uint32_t ref_clk_freq_kHz; /*!< Reference clock frequency. */ + adi_apollo_divg_mode_e clocking_mode; /*!< DivG block in clock generator. */ + bool adc_divby2[ADI_APOLLO_NUM_SIDES]; /*!< Divider control for ADC clock path. TRUE: Divide by 2 */ + bool dac_divby2[ADI_APOLLO_NUM_SIDES]; /*!< Divider control for DAC clock path. TRUE: Divide by 2 */ + bool adc_inclk_invert0[ADI_APOLLO_NUM_SIDES]; /*!< Enable ADC 0 clock inversion. TRUE: invert clock */ + bool adc_inclk_invert1[ADI_APOLLO_NUM_SIDES]; /*!< Enable ADC 1 clock inversion. TRUE: invert clock */ + uint64_t dev_clk_freq_Hz; /*!< Device clock frequency in Hertz */ + adi_apollo_arm_clock_sel_e arm_clock_sel; /*!< Selection of where the ARM/JESD clock originates when single_dual_clk_sel == True */ + uint8_t arm_clk_div; /*!< Arm clock divider. */ + uint8_t serdes_clk_div; /*!< SerDes Ref Clock Divider */ +} adi_apollo_clk_cfg_t; +ADI_APOLLO_PACK_FINISH + + +/** + * \brief Sysref input configuration + */ +ADI_APOLLO_PACK_START +typedef struct adi_apollo_sysref_inp_cfg { + uint64_t ref_to_int_period_ratio; /*!< Ratio of Reference Sysref to Internal Sysref */ + bool sysref_present; /*!< True if external sysref is provided to this instance of inp */ + bool rx_term_en; /*!< True to enable on-chip termination, False to disable*/ + bool cm_above_900mv; /*!< True if wanted sysref common mode above 900mV */ +} adi_apollo_sysref_inp_cfg_t; +ADI_APOLLO_PACK_FINISH + + +/** + * \brief ADF4382 Delay Correction Mode. Bit 5 of ADF4382 register 0x032: DEL_MODE + */ +typedef enum adi_apollo_adf4382_corr { + ADI_APOLLO_ADF4382_CORR_INT = 0u, /*!< Charge-Pump Bleed Mode */ + ADI_APOLLO_ADF4382_CORR_FRAC = 1u, /*!< Fractional Mode, using the ADF4382's sigma-delta modulator */ +} ADI_APOLLO_PACK_ENUM adi_apollo_adf4382_corr_e; + + +/** + * \brief ADF4382 Physical Instantiation Mapping for Dual-Clock + */ +typedef enum adi_apollo_adf4382_instance_side_cfg { + ADI_APOLLO_ADF4382_INSTANCE_SIDE_CFG_NONE = 0u, /*!< No ADF4382 device is connected to this clocking side */ + ADI_APOLLO_ADF4382_INSTANCE_SIDE_CFG_1 = 1u, /*!< Physical Instance 1 ADF4382 device is connected to this clocking side */ + ADI_APOLLO_ADF4382_INSTANCE_SIDE_CFG_2 = 2u, /*!< Physical Instance 2 ADF4382 device is connected to this clocking side */ +} ADI_APOLLO_PACK_ENUM adi_apollo_adf4382_instance_side_cfg_e; + +/** + * \brief ADF4382 configuration + */ +ADI_APOLLO_PACK_START +typedef struct adi_apollo_adf4382_cfg { + adi_apollo_adf4382_instance_side_cfg_e side_a_adf4382_instance_cfg; /*!< Defines which ADF4382 Instance is driving side A. Only relevant in Dual-Clock mode. */ + adi_apollo_adf4382_instance_side_cfg_e side_b_adf4382_instance_cfg; /*!< Defines which ADF4382 Instance is driving side B. Only relevant in Dual-Clock mode. */ + + adi_apollo_adf4382_corr_e del_mode; /*!< Selects the clock phase correction approach for clock align for all adf4382 */ + + /*!< ADF4382 Clock GPIO selection + GPIOs that will be used to tell one or two ADF4382 to actuate one step of adjustment (either advance or delay clock based on the delay adjust variables) + The first index corresponds to the ADF4382 instance '1' from ADF4382_clock_align_config + */ + uint8_t clock_align_delay_adjust_gpio[ADI_APOLLO_NUM_ADF4382_GPIOS]; /*!< Clock Align Delay Adjust */ + uint8_t clock_align_delay_strobe_gpio[ADI_APOLLO_NUM_ADF4382_GPIOS]; /*!< Clock Align Delay Strobe */ + + /*!< Settings per ADF4382 */ + bool track_polarity_select[ADI_APOLLO_MAX_NUM_ADF4382]; /*!< Variable used in case clock correction feedback(delay_adjust) to a particular ADF4382 is inverted. */ + uint8_t phase_adj[ADI_APOLLO_MAX_NUM_ADF4382]; /*!< Phase adjustment steps of the ADF4382. Must match the PHASE_ADJUSTMENT of ADF4382. */ + uint32_t track_win[ADI_APOLLO_MAX_NUM_ADF4382]; /*!< The amount of deviation the ADF4382's output clock can drift, in femtosecond [ fs ], relative to AD9084's External SysRef (BSYNC) before MCS Tracking attempts to correct it. This is the clock tracking window. */ +} adi_apollo_adf4382_cfg_t; +ADI_APOLLO_PACK_FINISH + + +/** + * \brief MCS Trigger configuration + */ +ADI_APOLLO_PACK_START +typedef struct adi_apollo_mcs_trigger_cfg { + uint8_t trigger_pin_to_rx_datapath_a_mapping; /*!< MCS Trigger for A Side Rx */ + uint8_t trigger_pin_to_rx_datapath_b_mapping; /*!< MCS Trigger for B Side Rx */ + uint8_t trigger_pin_to_tx_datapath_a_mapping; /*!< MCS Trigger for A Side Tx */ + uint8_t trigger_pin_to_tx_datapath_b_mapping; /*!< MCS Trigger for B Side Tx */ +} adi_apollo_mcs_trigger_cfg_t; +ADI_APOLLO_PACK_FINISH + + +/** + * \brief Multi-Chip Sync configuration + */ +ADI_APOLLO_PACK_START +typedef struct adi_apollo_mcs_cfg { + adi_apollo_sysref_inp_cfg_t center_sysref; /*!< Center clocking region, sysref input pin configuration */ + adi_apollo_sysref_inp_cfg_t side_a_sysref; /*!< Side A clocking region, sysref input pin configuration */ + adi_apollo_sysref_inp_cfg_t side_b_sysref; /*!< Side B clocking region, sysref input pin configuration */ + + bool use_gapped_sysref; /*!< if True, external sysref period (minimum) must match internal sysref period. If False, External Sysref period must be integer multiple of internal sysref */ + + bool leave_sysref_rx_on; /*!< True to leave sysref rx on after sync, False to turn it off */ + + uint16_t num_sysref_avg_mcs_fw; /*!< Number of sysref averages to use for mcs firmware */ + uint8_t sysref_lock_window_mcs_fw; /*!< Lock window for the sysref with mcs firmware */ + + uint16_t internal_sysref_prd_digclk_cycles_center; /*!< Sys Ref Period of Center MCS in number of master digital clock cycles */ + uint16_t internal_sysref_prd_digclk_cycles_side_a; /*!< Sys Ref Period of side A MCS in number of master digital clock cycles */ + uint16_t internal_sysref_prd_digclk_cycles_side_b; /*!< Sys Ref Period of side B MCS in number of master digital clock cycles */ + + adi_apollo_adf4382_cfg_t adf4382_cfg; + adi_apollo_mcs_trigger_cfg_t mcs_trigger_cfg; /*!< MCS Trigger Config */ +} adi_apollo_mcs_cfg_t; +ADI_APOLLO_PACK_FINISH + + +/** + * \brief Valid JESD Sync Subclasses + */ +typedef enum adi_apollo_jesd_subclass { + ADI_APOLLO_SUBCLASS_0 = 0u, + ADI_APOLLO_SUBCLASS_1 = 1u, + ADI_APOLLO_SUBCLASS_2 = 2u +} ADI_APOLLO_PACK_ENUM adi_apollo_jesd_subclass_e; + + +/** + * \brief Valid JESD Logical Lanes + */ +typedef enum adi_apollo_jtx_lane_xbar_sel { + ADI_APOLLO_XBAR_LOGIC_LANE_0 = 0u, + ADI_APOLLO_XBAR_LOGIC_LANE_1 = 1u, + ADI_APOLLO_XBAR_LOGIC_LANE_2 = 2u, + ADI_APOLLO_XBAR_LOGIC_LANE_3 = 3u, + ADI_APOLLO_XBAR_LOGIC_LANE_4 = 4u, + ADI_APOLLO_XBAR_LOGIC_LANE_5 = 5u, + ADI_APOLLO_XBAR_LOGIC_LANE_6 = 6u, + ADI_APOLLO_XBAR_LOGIC_LANE_7 = 7u, + ADI_APOLLO_XBAR_LOGIC_LANE_8 = 8u, + ADI_APOLLO_XBAR_LOGIC_LANE_9 = 9u, + ADI_APOLLO_XBAR_LOGIC_LANE_10 = 10u, + ADI_APOLLO_XBAR_LOGIC_LANE_11 = 11u +} ADI_APOLLO_PACK_ENUM adi_apollo_jtx_lane_xbar_sel_e; + + +/** + * \brief Valid JESD PHY Lanes + */ +typedef enum adi_apollo_jrx_lane_xbar_sel { + ADI_APOLLO_XBAR_PHY_LANE_0 = 0u, + ADI_APOLLO_XBAR_PHY_LANE_1 = 1u, + ADI_APOLLO_XBAR_PHY_LANE_2 = 2u, + ADI_APOLLO_XBAR_PHY_LANE_3 = 3u, + ADI_APOLLO_XBAR_PHY_LANE_4 = 4u, + ADI_APOLLO_XBAR_PHY_LANE_5 = 5u, + ADI_APOLLO_XBAR_PHY_LANE_6 = 6u, + ADI_APOLLO_XBAR_PHY_LANE_7 = 7u, + ADI_APOLLO_XBAR_PHY_LANE_8 = 8u, + ADI_APOLLO_XBAR_PHY_LANE_9 = 9u, + ADI_APOLLO_XBAR_PHY_LANE_10 = 10u, + ADI_APOLLO_XBAR_PHY_LANE_11 = 11u +} ADI_APOLLO_PACK_ENUM adi_apollo_jrx_lane_xbar_sel_e; + + +/** + * \brief Valid JESD Versions + */ +typedef enum adi_apollo_jesd_version { + ADI_APOLLO_JESD_204B = 0u, + ADI_APOLLO_JESD_204C = 1u +} ADI_APOLLO_PACK_ENUM adi_apollo_jesd_version_e; + + +/** + * \brief Link independent configuration (applies to both links if dual_link is true) + */ +ADI_APOLLO_PACK_START +typedef struct adi_apollo_jesd_common_cfg { + adi_apollo_jesd_version_e ver; /*!< 0 = 204B, 1 = 204C */ + adi_apollo_jesd_subclass_e subclass; /*!< Subclass setting */ + bool dual_link; /*!< TRUE: Dual link */ + uint16_t lane_enables; /*!< Each bit for one lane (12 lanes) */ + uint32_t lane_rate_kHz; /*!< Lane rate */ +} adi_apollo_jesd_common_cfg_t; +ADI_APOLLO_PACK_FINISH + + +/** + * \brief Valid JESD Lanes Per Link Settings + */ +typedef enum adi_apollo_jesd_lanes_per_link { + ADI_APOLLO_LANES_PER_LINK_1 = 0u, + ADI_APOLLO_LANES_PER_LINK_2 = 1u, + ADI_APOLLO_LANES_PER_LINK_3 = 2u, + ADI_APOLLO_LANES_PER_LINK_4 = 3u, + ADI_APOLLO_LANES_PER_LINK_6 = 5u, + ADI_APOLLO_LANES_PER_LINK_8 = 7u, + ADI_APOLLO_LANES_PER_LINK_12 = 11u +} ADI_APOLLO_PACK_ENUM adi_apollo_jesd_lanes_per_link_e; + + +/** + * \brief Valid JESD Octet Per Frame Settings + */ +typedef enum adi_apollo_jesd_octs_per_frm { + ADI_APOLLO_OCT_PER_FRM_1 = 0u, + ADI_APOLLO_OCT_PER_FRM_2 = 1u, + ADI_APOLLO_OCT_PER_FRM_3 = 2u, + ADI_APOLLO_OCT_PER_FRM_4 = 3u, + ADI_APOLLO_OCT_PER_FRM_6 = 5u, + ADI_APOLLO_OCT_PER_FRM_8 = 7u, + ADI_APOLLO_OCT_PER_FRM_12 = 11u, + ADI_APOLLO_OCT_PER_FRM_16 = 15u, + ADI_APOLLO_OCT_PER_FRM_24 = 23u, + ADI_APOLLO_OCT_PER_FRM_32 = 31u +} ADI_APOLLO_PACK_ENUM adi_apollo_jesd_octs_per_frm_e; + + +/** + * \brief Valid JESD Converter Per Link Settings + */ +typedef enum adi_apollo_jesd_convs_per_link { + ADI_APOLLO_CONV_PER_LINK_1 = 0u, + ADI_APOLLO_CONV_PER_LINK_2 = 1u, + ADI_APOLLO_CONV_PER_LINK_3 = 2u, + ADI_APOLLO_CONV_PER_LINK_4 = 3u, + ADI_APOLLO_CONV_PER_LINK_6 = 5u, + ADI_APOLLO_CONV_PER_LINK_8 = 7u, + ADI_APOLLO_CONV_PER_LINK_12 = 11u, + ADI_APOLLO_CONV_PER_LINK_16 = 15u +} ADI_APOLLO_PACK_ENUM adi_apollo_jesd_convs_per_link_e; + + +/** + * \brief Valid JESD Control Bits Per Sample Settings + */ +typedef enum adi_apollo_jesd_cont_bits_per_samp { + ADI_APOLLO_CONT_BITS_PER_SAMP_0 = 0u, + ADI_APOLLO_CONT_BITS_PER_SAMP_1 = 1u, + ADI_APOLLO_CONT_BITS_PER_SAMP_2 = 2u, + ADI_APOLLO_CONT_BITS_PER_SAMP_3 = 3u +} ADI_APOLLO_PACK_ENUM adi_apollo_jesd_cont_bits_per_samp_e; + + +/** + * \brief Valid JESD Converter Resolution Settings + */ +typedef enum adi_apollo_jesd_conv_resol { + ADI_APOLLO_CONV_RESOL_7 = 6u, + ADI_APOLLO_CONV_RESOL_8 = 7u, + ADI_APOLLO_CONV_RESOL_9 = 8u, + ADI_APOLLO_CONV_RESOL_10 = 9u, + ADI_APOLLO_CONV_RESOL_11 = 10u, + ADI_APOLLO_CONV_RESOL_12 = 11u, + ADI_APOLLO_CONV_RESOL_13 = 12u, + ADI_APOLLO_CONV_RESOL_14 = 13u, + ADI_APOLLO_CONV_RESOL_15 = 14u, + ADI_APOLLO_CONV_RESOL_16 = 15u +} ADI_APOLLO_PACK_ENUM adi_apollo_jesd_conv_resol_e; + + +/** + * \brief Valid JESD Sample Per Conv Per Frame Settings + */ +typedef enum adi_apollo_jesd_samp_conv_frm { + ADI_APOLLO_SAMP_CONV_FRM_1 = 0u, + ADI_APOLLO_SAMP_CONV_FRM_2 = 1u, + ADI_APOLLO_SAMP_CONV_FRM_3 = 2u, + ADI_APOLLO_SAMP_CONV_FRM_4 = 3u, + ADI_APOLLO_SAMP_CONV_FRM_6 = 5u, + ADI_APOLLO_SAMP_CONV_FRM_8 = 7u, + ADI_APOLLO_SAMP_CONV_FRM_12 = 11u, + ADI_APOLLO_SAMP_CONV_FRM_16 = 15u +} ADI_APOLLO_PACK_ENUM adi_apollo_jesd_samp_conv_frm_e; + + +/** + * \brief Valid JESD Bits Per Sample Settings + */ +typedef enum adi_apollo_jesd_bits_per_samp { + ADI_APOLLO_BITS_PER_SAMP_8 = 7u, + ADI_APOLLO_BITS_PER_SAMP_12 = 11u, + ADI_APOLLO_BITS_PER_SAMP_16 = 15u +} ADI_APOLLO_PACK_ENUM adi_apollo_jesd_bits_per_samp_e; + + +/** + * \brief Valid JESD Sample Per Conv Settings + */ +typedef enum adi_apollo_jesd_samp_per_conv { + ADI_APOLLO_SAMP_PER_CONV_1 = 0u, + ADI_APOLLO_SAMP_PER_CONV_2 = 1u, + ADI_APOLLO_SAMP_PER_CONV_4 = 3u, + ADI_APOLLO_SAMP_PER_CONV_8 = 7u, + ADI_APOLLO_SAMP_PER_CONV_12 = 11u, + ADI_APOLLO_SAMP_PER_CONV_16 = 15u, + ADI_APOLLO_SAMP_PER_CONV_24 = 23u, + ADI_APOLLO_SAMP_PER_CONV_32 = 31u +} ADI_APOLLO_PACK_ENUM adi_apollo_jesd_samp_per_conv_e; + + +/** + * \brief Valid JESD SYNCb Settings + */ +typedef enum adi_apollo_jesd_syncb_sel { + ADI_APOLLO_JESD_FRM_SYNCB_CMOS = 0u, + ADI_APOLLO_JESD_FRM_SYNCB_LVDS_WITH_INTL_TERM = 1u, + ADI_APOLLO_JESD_FRM_SYNCB_LVDS_NO_INTL_TERM = 2u +} ADI_APOLLO_PACK_ENUM adi_apollo_jesd_syncb_sel_e; + + +/** + * \brief Per Link JTx Config Structure + */ +ADI_APOLLO_PACK_START +typedef struct adi_apollo_jesd_tx_link_cfg { + bool link_in_use; /*!< if TRUE, the link is in use */ + uint8_t e_minus1; /*!< Blocks in Multi-block minus 1 for 204C */ + uint8_t bank_id; /*!< Bank ID extension to Device ID (0-15)*/ + uint8_t dev_id; /*!< Device ID link identification number (0-255) */ + uint8_t base_lane_id; /*!< Starting Lane ID */ + adi_apollo_jesd_lanes_per_link_e l_minus1; /*!< Number of lanes minus 1 */ + adi_apollo_jesd_octs_per_frm_e f_minus1; /*!< Number of bytes (octets) per frame minus 1 */ + adi_apollo_jesd_convs_per_link_e m_minus1; /*!< Number of converters minus 1 */ + adi_apollo_jesd_samp_conv_frm_e s_minus1; /*!< Number of samples per converter per frame minus 1 */ + bool high_dens; /*!< TRUE: High-density */ + uint8_t k_minus1; /*!< Number of frames in a multiframe - 1 (0 - 255) */ + adi_apollo_jesd_conv_resol_e n_minus1; /*!< Link converter resolution minus 1 */ + adi_apollo_jesd_bits_per_samp_e np_minus1; /*!< Converter sample resolution in bits minus 1 */ + adi_apollo_jesd_samp_per_conv_e ns_minus1; /*!< Number of samples per converter in Conv_sample */ + adi_apollo_jesd_cont_bits_per_samp_e cs; /*!< Number of control bits per sample*/ + bool scr; /*!< Scrambling enable */ + bool quick_cfg_en; /*!< Enable Quick configuration mode */ + uint8_t quick_mode_id; /*!< Quick configuration mode ID */ + uint8_t syncb_in_sel; /*!< Selects SYNCb input source. */ + adi_apollo_jesd_syncb_sel_e syncb_lvds_mode; /*!< SyncB LVDS Mode select */ + bool fec_enable; /*!< If TRUE, forward error correction is enabled */ + bool async_mode; /*!< IF TRUE, asynchronous mode is enabled */ + bool metword_rev; /*!< IF TRUE, bit ordering of CRC/FEC is reversed */ + uint16_t link_dp_ratio; /*!< Link datapath ratio */ + uint16_t link_total_ratio; /*!< Link total ratio */ + uint16_t phase_adjust; /*!< LMFC offset for deterministic delay, Yoda register: sync_sysref_delay */ + adi_apollo_jesd_frm_conv_xbar_select_e conv_xbar_sel[ADI_APOLLO_JESD_MAX_CONV_XBAR_IDXS]; /*!< Converter crossbar selection */ + adi_apollo_jtx_lane_xbar_sel_e lane_xbar[ADI_APOLLO_JESD_MAX_LANES_PER_SIDE]; /*!< Lane crossbar selection */ +} adi_apollo_jesd_tx_link_cfg_t; +ADI_APOLLO_PACK_FINISH + + +/** + * \brief List of Serializer Output Swings + */ +typedef enum adi_apollo_jesd_jtx_output_drive_swing { + ADI_APOLLO_JESD_DRIVE_SWING_VTT_100 = 0u, /*!< Output Swing at 100% Vtt */ + ADI_APOLLO_JESD_DRIVE_SWING_VTT_85 = 1u, /*!< Output Swing at 85% Vtt */ + ADI_APOLLO_JESD_DRIVE_SWING_VTT_75 = 2u, /*!< Output Swing at 75% Vtt */ + ADI_APOLLO_JESD_DRIVE_SWING_VTT_50 = 3u, /*!< Output Swing at 50% Vtt */ + ADI_APOLLO_JESD_DRIVE_SWING_LAST_VALID = 3u /*!< Last Valid Output Swing */ +} ADI_APOLLO_PACK_ENUM adi_apollo_jesd_jtx_output_drive_swing_e; + + +/** + * \brief List of Serializer Pre Tap Values + */ +typedef enum adi_apollo_jesd_jtx_pre_emphasis { + ADI_APOLLO_JESD_PRE_TAP_LEVEL_0_DB = 0u, + ADI_APOLLO_JESD_PRE_TAP_LEVEL_3_DB = 1u, + ADI_APOLLO_JESD_PRE_TAP_LEVEL_6_DB = 2u, + ADI_APOLLO_JESD_PRE_TAP_LEVEL_LAST_VALID = 2u +} ADI_APOLLO_PACK_ENUM adi_apollo_jesd_jtx_pre_emphasis_e; + + +/** + * \brief List of Serializer Post Tap Values + */ +typedef enum adi_apollo_jesd_jtx_post_emphasis { + ADI_APOLLO_JESD_POST_TAP_LEVEL_0_DB = 0u, + ADI_APOLLO_JESD_POST_TAP_LEVEL_3_DB = 1u, + ADI_APOLLO_JESD_POST_TAP_LEVEL_6_DB = 2u, + ADI_APOLLO_JESD_POST_TAP_LEVEL_9_DB = 3u, + ADI_APOLLO_JESD_POST_TAP_LEVEL_12_DB = 4u, + ADI_APOLLO_JESD_POST_TAP_LEVEL_LAST_VALID = 4u +} ADI_APOLLO_PACK_ENUM adi_apollo_jesd_jtx_post_emphasis_e; + + +/** + * \brief Valid SerDes Lanerate Adapt Ratios + */ +typedef enum adi_apollo_serdes_lr_adapt_ratio { + ADI_APOLLO_SERDES_LR_ADAPT_RATIO_1 = 0u, + ADI_APOLLO_SERDES_LR_ADAPT_RATIO_2 = 1u, + ADI_APOLLO_SERDES_LR_ADAPT_RATIO_4 = 2u, + ADI_APOLLO_SERDES_LR_ADAPT_RATIO_8 = 3u, + ADI_APOLLO_SERDES_LR_ADAPT_RATIO_16 = 4u, + ADI_APOLLO_SERDES_LR_ADAPT_RATIO_32 = 5u +} ADI_APOLLO_PACK_ENUM adi_apollo_serdes_lr_adapt_ratio_e; + + + +/** + * \brief Per Lane Serializer Config Structure + */ +ADI_APOLLO_PACK_START +typedef struct adi_apollo_jesd_ser_lane { + adi_apollo_jesd_jtx_output_drive_swing_e ser_amplitude; /*!< Serializer lane amplitude */ + adi_apollo_jesd_jtx_pre_emphasis_e ser_pre_emphasis; /*!< Serializer lane pre-emphasis */ + adi_apollo_jesd_jtx_post_emphasis_e ser_post_emphasis; /*!< Serializer lane post-emphasis */ + bool ser_invert_lane_polarity; /*!< Serializer lane PN inversion select: TRUE = invert */ + adi_apollo_serdes_lr_adapt_ratio_e lanerate_adapt; /*!< Lanerate Adapt ratio */ +} adi_apollo_jesd_ser_lane_t; +ADI_APOLLO_PACK_FINISH + + +/** + * \brief List of Rate Modes for Deserializer + */ +typedef enum adi_apollo_deser_mode { + ADI_APOLLO_DESER_MODE_FULL_RATE = 0u, /*!< Full Rate Mode */ + ADI_APOLLO_DESER_MODE_HALF_RATE = 1u, /*!< Half Rate Mode */ + ADI_APOLLO_DESER_MODE_QUARTER_RATE = 2u, /*!< Quarter Rate Mode */ + ADI_APOLLO_DESER_MODE_VSR = 3u, /*!< Very Short Reach Mode */ + ADI_APOLLO_DESER_NUM_OF_MODES = 4u, /*!< Number of modes */ +} ADI_APOLLO_PACK_ENUM adi_apollo_deser_mode_e; + + +/** + * \brief List of config options for deserializer + */ +typedef enum adi_apollo_deser_cfg_option_idx { + ADI_APOLLO_DESER_CFG_OPTION_1 = 0u, + ADI_APOLLO_DESER_CFG_OPTION_2 = 1u, + ADI_APOLLO_DESER_CFG_OPTION_3 = 2u, + ADI_APOLLO_DESER_CFG_OPTION_4 = 3u, + ADI_APOLLO_DESER_CFG_OPTION_5 = 4u, + ADI_APOLLO_DESER_CFG_OPTION_6 = 5u, + ADI_APOLLO_DESER_CFG_OPTION_7 = 6u, + ADI_APOLLO_DESER_CFG_OPTION_8 = 7u, + ADI_APOLLO_DESER_CFG_OPTION_9 = 8u, + ADI_APOLLO_DESER_CFG_OPTION_10 = 9u, + ADI_APOLLO_DESER_NUM_CFGS = 10u +} ADI_APOLLO_PACK_ENUM adi_apollo_deser_cfg_option_idx_e; + + +/** + * \brief List of Override options for deserializer + */ +typedef enum adi_apollo_deser_override_name { + ADI_APOLLO_DESER_INVALID = 0, /*!< No further settings applied */ + ADI_APOLLO_DESER_JRX_CTLE_S1_GM = 1u, /*!< AEQ stage 1 transconductance weight; 17 units with irregular coding - 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,31 are valid. */ + ADI_APOLLO_DESER_JRX_CTLE_S1_LD = 2u, /*!< AEQ stage 1 load impedance weight; 15 units with irregular coding - 0,1,2,3,4,5,6,7,9,10,11,12,13,14,15 are valid.*/ + ADI_APOLLO_DESER_JRX_CTLE_S2_GM = 3u, /*!< AEQ stage 2 load impedance weight; 12 units with irregular coding - 0,1,2,3,4,5,6,7,12,13,14,15 are valid.*/ + ADI_APOLLO_DESER_JRX_CTLE_S2_LD = 4u, /*!< AEQ stage 2 transconductance weight; 13 units with irregular coding - 0,1,2,3,4,6,7,11,12,13,14,15 are valid.*/ + ADI_APOLLO_DESER_LAST_VALID = 4u +} ADI_APOLLO_PACK_ENUM adi_apollo_deser_override_name_e; + + + +/** + * \brief Per Lane Deserializer Config Structure + */ +ADI_APOLLO_PACK_START +typedef struct adi_apollo_jesd_deser_lane { + uint8_t high_boost_options; /*!< Mask containing how the config options should be applied */ + bool des_inv_lane_pol; /*!< Deserializer Lane PN inversion select: TRUE = invert */ + adi_apollo_serdes_lr_adapt_ratio_e lanerate_adapt; /*!< Lanerate Adapt ratio */ + uint32_t cfg_options[ADI_APOLLO_DESER_NUM_CFGS]; /*!< Used for modifying the SerDes configuration at startup based off customers use case */ + uint16_t ctle_filter_mask; /*!< Used to modify Des PHY ctle filter before running cals.Multiple bits can be set for this field - Bit 0: low bandwidth, Bit 1: medium bandwidth, Bit 2: high bandwidth, Bits 3-8: For debugging purposes. */ +} adi_apollo_jesd_deser_lane_t; +ADI_APOLLO_PACK_FINISH + + + +/** + * \brief Configuration for individual links within JRX + */ +ADI_APOLLO_PACK_START +typedef struct adi_apollo_jesd_rx_link_cfg { + bool link_in_use; /*!< if TRUE, the link is in use */ + uint8_t e_minus1; /*!< Blocks in Multi-block minus 1 for 204C */ + uint8_t bank_id; /*!< Bank ID extension to Device ID (0-15)*/ + uint8_t dev_id; /*!< Device ID link identification number (0-255) */ + uint8_t base_lane_id; /*!< Starting Lane ID */ + adi_apollo_jesd_lanes_per_link_e l_minus1; /*!< Number of lanes minus 1 */ + adi_apollo_jesd_octs_per_frm_e f_minus1; /*!< Number of bytes (octets) per frame minus 1 */ + adi_apollo_jesd_convs_per_link_e m_minus1; /*!< Number of converters minus 1 */ + adi_apollo_jesd_samp_conv_frm_e s_minus1; /*!< Number of samples per converter per frame minus 1 */ + bool high_dens; /*!< High-density */ + uint8_t k_minus1; /*!< Number of frames in a multiframe minus 1 (0 - 255) */ + adi_apollo_jesd_conv_resol_e n_minus1; /*!< Link converter resolution minus 1 */ + adi_apollo_jesd_bits_per_samp_e np_minus1; /*!< Converter sample resolution in bits minus 1 */ + adi_apollo_jesd_samp_per_conv_e ns_minus1; /*!< Number of samples per converter in Conv_sample minus 1 */ + adi_apollo_jesd_cont_bits_per_samp_e cs; /*!< Number of control bits per sample*/ + bool scr; /*!< Scrambling enable */ + bool quick_cfg_en; /*!< Enable Quick configuration mode */ + uint8_t quick_mode_id; /*!< Quick configuration mode ID */ + adi_apollo_jesd_dfrm_sync_pad_req_e syncb_out_sel; /*!< Selects deframer SYNCBOUT pin. */ + adi_apollo_jesd_syncb_sel_e syncb_lvds_mode; /*!< SyncB LVDS Mode select */ + uint16_t link_dp_ratio; /*!< Link datapath ratio */ + uint16_t link_total_ratio; /*!< Link total ratio */ + bool invalid_data_en; /*!< True to enable invalid sample removal */ + uint8_t invalid_sample_num; /*!< The number of invalid samples each conv_clk. The value should be (JTX_NS - 1). */ + bool sample_repeat_en; /*!< True to enable sample repeat removal */ + uint16_t phase_adjust; /*!< LMFC offset for deterministic delay, Yoda register: sync_sysref_delay */ + uint8_t sample_xbar_sel[ADI_APOLLO_JESD_MAX_SAMPLE_XBAR_IDXS]; /*!< Converter sample crossbar selection */ + adi_apollo_jrx_lane_xbar_sel_e lane_xbar[ADI_APOLLO_JESD_MAX_LANES_PER_SIDE]; /*!< Lane crossbar selection */ +} adi_apollo_jesd_rx_link_cfg_t; +ADI_APOLLO_PACK_FINISH + + +/** + * \brief Per Side JTx Config Structure + */ +ADI_APOLLO_PACK_START +typedef struct adi_apollo_jesd_tx_cfg { + adi_apollo_jesd_common_cfg_t common_link_cfg; /*!< Config for both links or one link if only one link */ + adi_apollo_jesd_tx_link_cfg_t tx_link_cfg[ADI_APOLLO_JESD_LINKS]; /*!< Config for each of the link(s) */ + adi_apollo_jesd_ser_lane_t serializer_lane[ADI_APOLLO_JESD_MAX_LANES_PER_SIDE]; /*!< Per Serializer Lane Config */ +} adi_apollo_jesd_tx_cfg_t; +ADI_APOLLO_PACK_FINISH + +/** + * \brief Possible number of bridging calibrations for SERDES Rx initial calibration + */ +typedef enum adi_apollo_deser_num_bridging_cals { + ADI_APOLLO_NUM_BRIDGING_CALS_0 = 0u, + ADI_APOLLO_NUM_BRIDGING_CALS_1 = 1u, + ADI_APOLLO_NUM_BRIDGING_CALS_2 = 2u, + ADI_APOLLO_NUM_BRIDGING_CALS_3 = 3u +} ADI_APOLLO_PACK_ENUM adi_apollo_deser_num_bridging_cals_e; + +ADI_APOLLO_PACK_START +/** + * \brief JESD Deserializer Common Config Structure + */ +typedef struct adi_apollo_jesd_deser_common { + adi_apollo_deser_mode_e rx_des_mode; /*!< Deserializer mode settings */ + adi_apollo_deser_num_bridging_cals_e num_bridging_cals; /*!< Number of bridging calibrations */ + bool sample_xbar_override; /*!< 0 == Use design sample xbar ramp settings, 1 == Use values in sample_xbar_sel for both links. */ +} adi_apollo_jesd_deser_common_t; +ADI_APOLLO_PACK_FINISH + + +ADI_APOLLO_PACK_START +/** + * \brief Per Side JRx Config Structure + */ +typedef struct adi_apollo_jesd_rx_cfg { + adi_apollo_jesd_common_cfg_t common_link_cfg; /*!< Common config for JRx link */ + adi_apollo_jesd_rx_link_cfg_t rx_link_cfg[ADI_APOLLO_JESD_LINKS]; /*!< Config for JRx link */ + adi_apollo_jesd_deser_common_t deserializer_common; /*!< Properties common to all Rx lanes in a pack */ + adi_apollo_jesd_deser_lane_t deserializer_lane[ADI_APOLLO_JESD_MAX_LANES_PER_SIDE]; /*!< Per Deserializer Lane Config */ +} adi_apollo_jesd_rx_cfg_t; +ADI_APOLLO_PACK_FINISH + + +/** + * \brief GPIO Config Structure + */ +ADI_APOLLO_PACK_START +typedef struct adi_apollo_gpio_cfg { + uint8_t gpio_quick_config; /*!< GPIO quick configuration. See user guide for information on quick config use cases. */ + uint64_t gpio_mode_en; /*!< Nth bit corresponds to Nth GPIO pin for enabling gpio_mode_dir for that pin. */ + uint64_t gpio_mode_dir; /*!< This field has meaning only if corresponding gpio_mode_en is set to 1. if gpio_mode_dir = 1 than gpio will be configured as an input and if gpio_mode_dir=0 than gpio will be configured as output. */ + uint64_t gpio_from_master; /*!< This field is used by masters (core0/core1/stream_proc) to write data to Digital GPIO pins. */ + uint64_t gpio_from_set; /*!< Writing a '1' to a bit in this field sets the corresponding bit in the gpio_from_master register. Writing '0' has no effect. */ + uint64_t gpio_from_clear; /*!< Writing a '1' to a bit in this field clears the corresponding bit in the gpio_from_master register. Writing '0' has no effect. */ + uint8_t gpio_source_control[ADI_APOLLO_NUM_GPIOS]; /*!< Select pin of GPIO functional pinmux. */ + uint64_t gpio_stage_sel_lsb; /*!< 64Bits select the mux stage of GPIO pinmuxing. */ + uint64_t gpio_stage_sel_msb; /*!< 38Bits select the mux stage of GPIO pinmuxing. */ +} adi_apollo_gpio_cfg_t; +ADI_APOLLO_PACK_FINISH + + +/** + * \brief SW Trim Level Enumeration + */ +typedef enum adi_apollo_cfg_sw_trim { + ADI_APOLLO_SW_TRIM_NOT_SET = 0, /*!< SW Trim is not set for this profile may not work with SW1/3 trim levels */ + ADI_APOLLO_SW_TRIM_1 = 1u, /*!< This profile is suitable for SW1, SW3, SW5 trim levels. */ + ADI_APOLLO_SW_TRIM_3 = 3u, /*!< This profile is suitable for SW3, SW5 trim levels. */ + ADI_APOLLO_SW_TRIM_5 = 5u /*!< This profile is suitable only for SW5 trim levels. */ +} ADI_APOLLO_PACK_ENUM adi_apollo_cfg_sw_trim_e; + + +/** + * \brief Profile Configuration Structure - Contains the profile version and compatibilty information + */ +ADI_APOLLO_PACK_START +typedef struct adi_apollo_profile_cfg { + adi_apollo_profile_version_t profile_version; /*!< Profile version */ + uint16_t cfg_version; /*!< A specific profile can be valued several times, each with a new config_version */ + bool is_8t8r; /*!< True for 8t8r, False for 4t4r */ + adi_apollo_cfg_sw_trim_e sw_trim; /*!< The minimum SW Trim level this profile supports */ +} adi_apollo_profile_cfg_t; +ADI_APOLLO_PACK_FINISH + + +/** + * \brief Apollo Top Profile Structure + */ +ADI_APOLLO_PACK_START +typedef struct adi_apollo_top { + adi_apollo_profile_cfg_t profile_cfg; /*!< Profile version and misc high level info */ + adi_apollo_clk_cfg_t clk_cfg; /*!< Clock configuration */ + adi_apollo_clk_pll_cfg_t clk_pll; /*!< Main PLL configuration */ + adi_apollo_mcs_cfg_t mcs_cfg; /*!< MCS configuration */ + adi_apollo_gpio_cfg_t gpio_cfg; /*!< GPIO configuration */ + adi_apollo_txpath_t tx_path[ADI_APOLLO_NUM_SIDES]; /*!< Tx Path configuration */ + adi_apollo_rxpath_t rx_path[ADI_APOLLO_NUM_SIDES]; /*!< Rx Path configuration */ + adi_apollo_jesd_tx_cfg_t jtx[ADI_APOLLO_NUM_SIDES]; /*!< JTX configuration */ + adi_apollo_jesd_rx_cfg_t jrx[ADI_APOLLO_NUM_SIDES]; /*!< JRX configuration */ + adi_apollo_dac_cfg_t dac_cfg[ADI_APOLLO_NUM_SIDES]; /*!< DAC configuration */ + adi_apollo_adc_cfg_t adc_cfg[ADI_APOLLO_NUM_SIDES]; /*!< ADC configuration */ + bool lb0_en[ADI_APOLLO_NUM_SIDES][ADI_APOLLO_DAC_DIG_SLICE_PER_SIDE]; /*!< Loopback for feeding the DAC from ADC */ + adi_apollo_serdes_pll_cfg_t serdes_pll; /*!< SERDES PLL structure */ + uint16_t adc_enable; /*!< ADC Enable. B0=ADC_A0, B1=ADC_A1, B2=ADC_A2, B3=ADC_A3, B4=ADC_B0, B5=ADC_B1, B6=ADC_B2, B7=ADC_B3 */ + uint16_t dac_enable; /*!< DAC Enable. B0=DAC_A0, B1=DAC_A1, B2=DAC_A2, B3=DAC_A3, B4=DAC_B0, B5=DAC_B1, B6=DAC_B2, B7=DAC_B3 */ + uint8_t reserved_cfg[64]; /*!< Extra space for temporary feature implementation */ + uint32_t profile_checksum; /*!< Checksum of the entire profile using CRC32 */ +} adi_apollo_top_t; +ADI_APOLLO_PACK_FINISH + +#endif /* __APOLLO_CPU_DEVICE_PROFILE_TYPES_H__ */ diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_adc.c b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_adc.c new file mode 100644 index 00000000000000..b58f895d278f9a --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_adc.c @@ -0,0 +1,1316 @@ +/*! + * \brief APIs for ADC + * + * \copyright copyright(c) 2024 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_ADC + * @{ + */ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_bf_master_bias_ctrl.h" +#include "adi_apollo_bf_mcs_c_only.h" +#include "adi_apollo_clk_mcs.h" +#include "adi_apollo_private_blk_sel_types.h" +#include "adi_apollo_bf_custom.h" +#include "adi_apollo_bf_venus_fcal_open.h" + +#include "adi_apollo_adc.h" +#include "adi_apollo_config.h" +#include "adi_apollo_common.h" +#include "adi_apollo_hal.h" +#include "adi_apollo_mailbox.h" +#include "adi_apollo_cfg.h" +#include "adi_utils.h" + +/*============= D E F I N E S ==============*/ +#define ADC_OVR_SAMPLES_MIN 1 +#define ADC_OVR_SAMPLES_MAX 10000 +#define ADC_OVR_CYCLES_MIN 1 +#define ADC_OVR_CYCLES_MAX 1000 + +#define ADI_APOLLO_ADC_FAST_DETECT_SETTINGS_STRUCT 2 /*!< [in ] Set the Fast Detect Settings (defined by adi_apollo_adc_fast_detect_pgm_t) */ +#define ADI_APOLLO_ADC_INPUT_NYQUIST_ZONE_UINT32 6 /*!< [in,out] Set/Get the Input Nyquist Zone (0=disabled, 1=1st, 2=2nd, etc.) */ +#define ADI_APOLLO_ADC_FAST_DETECT_STATUS_UINT32 16 /*!< [ out] Get the Fast Detect Status. */ +#define ADI_APOLLO_ADC_DEBUG0_UINT32 19 /*!< [in,out] Set/Get Debug_0 Capability (deliberately vague) */ +#define ADI_APOLLO_ADC_CAL_GATING_GROUP_UINT32 20 /*!< [in,out] Set/Get Calibration Group Gating */ +#define ADI_APOLLO_ADC_INPUT_STATUS_UINT32 21 /*!< [ out] Get the Input Condition Status. */ +#define ADI_APOLLO_ADC_OVER_RANGE_THRESHOLD_UINT32 22 /*!< [in,out] Set/Get Over Range Protection Threshold */ +#define ADI_APOLLO_ADC_OVER_RANGE_SAMPLES_UINT32 23 /*!< [in,out] Set/Get Over Range Protection Number of Samples */ +#define ADI_APOLLO_ADC_FACTORY_CAL_COEFF_STATUS_UINT64 31 /*!< [ out] Get the Calibration Co-efficient Status. */ +#define ADI_APOLLO_ADC_FACTORY_CAL_COEFF_MODE_UINT32 32 /*!< [in,out] Set/Get the Calibration Co-efficient Mode. */ + + +static uint32_t calc_master_bias_base(int32_t index); + +/*==================== P U B L I C A P I C O D E ====================*/ +int32_t adi_apollo_adc_cal(adi_apollo_device_t *device, adi_apollo_blk_sel_t adcs) +{ + int32_t err; + uint8_t is_adc_nvm_fused = 0; + adi_apollo_init_cal_cfg_e init_cal_cfg = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_ADC_BLK_SEL_MASK(adcs); + + // Check if Apollo has NVM data for ADC CAL + err = adi_apollo_hal_bf_get(device, BF_ADC_NVM_CALDATA_FUSED_INFO, &is_adc_nvm_fused, 1); + ADI_CMS_ERROR_RETURN(err); + adi_apollo_hal_log_write(device, ADI_CMS_LOG_MSG, "is_adc_nvm_fused: 0x%02X", is_adc_nvm_fused); + + // If there is NVM data, start ADC cal with that else start a full ADC cal + init_cal_cfg = (is_adc_nvm_fused == 1) ? ADI_APOLLO_INIT_CAL_ENABLED_WARMBOOT_FROM_NVM + : ADI_APOLLO_INIT_CAL_ENABLED; + err = adi_apollo_adc_init_cal(device, adcs, init_cal_cfg); + ADI_CMS_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_adc_init_cal_start(adi_apollo_device_t *device, adi_apollo_blk_sel_t adcs, adi_apollo_init_cal_cfg_e init_cal_cfg) +{ + int32_t err; + adi_apollo_mailbox_cmd_run_init_t run_init_cmd = {0}; + adi_apollo_mailbox_resp_run_init_t run_init_resp = {0}; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_ADC_BLK_SEL_MASK(adcs); + + /* Init the mailbox command struct */ + run_init_cmd.cal_mask = APOLLO_INIT_CAL_MSK_IC_ADC_RX; + run_init_cmd.rx_channel_mask = adcs; + run_init_cmd.tx_channel_mask = 0; + run_init_cmd.serdes_rx_pack_mask = 0; + run_init_cmd.serdes_tx_pack_mask = 0; + run_init_cmd.linearx_chan_mask = 0; + + + /* Set ADC Init calibration config. Once enabled they can be started with mailbox commands */ + adi_apollo_hal_log_write(device, ADI_CMS_LOG_API, "ADC Init cal config: %d. ref: adi_apollo_init_cal_cfg_e\n", init_cal_cfg); + if (err = adi_apollo_cfg_adc_init_cal_cfg_set(device, adcs, init_cal_cfg), err != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Error from adi_apollo_cfg_adc_init_cal_cfg_set() %d", err); + goto end; + } + + /* Run the ADC foreground cal */ + adi_apollo_hal_log_write(device, ADI_CMS_LOG_API, "Starting ADC foreground cal\n"); + if (err = adi_apollo_mailbox_run_init(device, &run_init_cmd, &run_init_resp), err != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Error from adi_apollo_mailbox_run_init() %d", err); + goto end; + } + + if (run_init_resp.status != APOLLO_CPU_NO_ERROR) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "ADC Init cal error code = 0x%x\n", run_init_resp.status); + err = API_CMS_ERROR_MAILBOX_RESP_STATUS; + goto end; + } + +end: + return err; +} + +int32_t adi_apollo_adc_init_cal_complete(adi_apollo_device_t *device, adi_apollo_blk_sel_t adcs) +{ + int32_t err; + uint8_t i; + uint8_t cal_complete = 0; + uint32_t max_delay_us = 0; + uint32_t poll_delay_us = 1000000; + uint32_t delay_us; + adi_apollo_mailbox_resp_run_init_get_completion_t run_init_complete_resp = {0}; + adi_apollo_mailbox_resp_run_init_get_detailed_status_t run_init_cal_detailed_status_resp = {0}; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_ADC_BLK_SEL_MASK(adcs); + + + max_delay_us = (device->dev_info.is_8t8r ? ADI_APOLLO_8T8R_ADC_TIMEOUT : ADI_APOLLO_4T4R_ADC_TIMEOUT) * 1000000; + + /* Wait for ADC Init cal to complete */ + for (delay_us = 0; delay_us < max_delay_us; delay_us += poll_delay_us) { + if (err = adi_apollo_mailbox_run_init_get_completion(device, &run_init_complete_resp), err != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "adi_apollo_mailbox_run_init_get_completion() err %d\n"); + goto end; + } + + if ((delay_us % (5 * poll_delay_us)) == 0) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_API, "ADC Init Cal: status=%d in_progress=%d success=%d %ds\n", + run_init_complete_resp.status, run_init_complete_resp.in_progress, run_init_complete_resp.success, (delay_us / poll_delay_us)); + } + + if (run_init_complete_resp.in_progress == 0) { + cal_complete = 1; + break; + } + + adi_apollo_hal_delay_us(device, poll_delay_us); + } + + if (run_init_complete_resp.success != 1) { + if (err = adi_apollo_mailbox_run_init_get_detailed_status(device, &run_init_cal_detailed_status_resp), err != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Error from adi_apollo_mailbox_run_init_get_detailed_status() %d\n", err); + goto end; + } + + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "cpu_status = 0x%02X", run_init_cal_detailed_status_resp.status); + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "cals_duration_msec = %d", run_init_cal_detailed_status_resp.cals_duration_msec); + + // ADC init cal populates 4 index/channel data for 4T4R and 8 for 8T8R devices + for (i = 0; i < (device->dev_info.is_8t8r ? 8 : 4); ++i) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "init_err_codes[%d] = 0x%02X \t init_err_cals[%d] = 0x%02X", + i, run_init_cal_detailed_status_resp.init_err_codes[i], i, run_init_cal_detailed_status_resp.init_err_cals[i]); + // adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "cals_since_power_ups[%d] = %d \t cals_last_runs[%d] = %d", + // i, run_init_cal_detailed_status_resp.cals_since_power_up[i], i, run_init_cal_detailed_status_resp.cals_last_run[i]); + } + } + if (cal_complete) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_API, "ADC Init cal completed %s in %ds\n", + run_init_complete_resp.success ? "successfully" : "w/ ERROR", delay_us / 1000000); + err = run_init_complete_resp.success ? API_CMS_ERROR_OK : API_CMS_ERROR_ADC_INIT_CAL_ERROR; + goto end; + } else { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "ADC Init cal timeout after %ds\n", max_delay_us / 1000000); + err = API_CMS_ERROR_ADC_CAL_TIMEOUT; + goto end; + } + +end: + return err; +} + +int32_t adi_apollo_adc_init_cal(adi_apollo_device_t *device, adi_apollo_blk_sel_t adcs, adi_apollo_init_cal_cfg_e init_cal_cfg) +{ + int32_t err; + + err = adi_apollo_adc_init_cal_start(device, adcs, init_cal_cfg); + ADI_APOLLO_ERROR_RETURN(err); + + return adi_apollo_adc_init_cal_complete(device, adcs); +} + +int32_t adi_apollo_adc_nyquist_zone_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t adcs, + uint32_t nyquist_zone) +{ + int32_t err; + uint16_t i; + adi_apollo_blk_sel_t adc; + adi_apollo_mailbox_cmd_set_ctrl_t set_ctrl_cmd = { + .sys_cal_object_id = APOLLO_CPU_OBJID_IC_ADC_RX, + .ctrl_cmd = CTRL_CMD_PARAM_SET, + .data_buffer[0] = ADI_APOLLO_ADC_INPUT_NYQUIST_ZONE_UINT32, + .data_buffer[1] = 0, + .data_buffer[2] = 0, + .data_buffer[3] = 0, + .data_buffer[4] = (nyquist_zone & 0xFFU), + .data_buffer[5] = (nyquist_zone & 0xFF00U) >> 8, + .data_buffer[6] = (nyquist_zone & 0xFF0000U) >> 16, + .data_buffer[7] = (nyquist_zone & 0xFF000000U) >> 24, + .length = 8 + }; + adi_apollo_mailbox_resp_set_ctrl_t set_ctrl_resp = {0}; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(nyquist_zone > 2); + ADI_APOLLO_ADC_BLK_SEL_MASK(adcs); + + for (i = 0; i < ADI_APOLLO_ADC_NUM; i++) { + adc = adcs & (ADI_APOLLO_ADC_A0 << i); + + if (adc > 0) { + set_ctrl_cmd.channel_num = i; + + err = adi_apollo_mailbox_set_ctrl(device, &set_ctrl_cmd, &set_ctrl_resp); + if (err != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Error from adi_apollo_mailbox_set_ctrl() %d", err); + return err; + } + + if (set_ctrl_resp.status != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Mailbox Response Status Error from adi_apollo_mailbox_set_ctrl() 0x%X", set_ctrl_resp.status); + return API_CMS_ERROR_MAILBOX_RESP_STATUS; + } + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_adc_nyquist_zone_get(adi_apollo_device_t *device, adi_apollo_blk_sel_t adc, + uint32_t *nyquist_zone) +{ + int32_t err; + uint16_t i, adc_index; + adi_apollo_mailbox_cmd_set_ctrl_t set_ctrl_cmd = { + .sys_cal_object_id = APOLLO_CPU_OBJID_IC_ADC_RX, + .ctrl_cmd = CTRL_CMD_PARAM_GET, + .data_buffer[0] = ADI_APOLLO_ADC_INPUT_NYQUIST_ZONE_UINT32, + .data_buffer[1] = 0, + .data_buffer[2] = 0, + .data_buffer[3] = 0, + .length = 4 + }; + adi_apollo_mailbox_resp_set_ctrl_t set_ctrl_resp = {0}; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(nyquist_zone); + ADI_APOLLO_INVALID_PARAM_RETURN(adi_api_utils_num_selected(adc) != 1); + ADI_APOLLO_ADC_BLK_SEL_MASK(adc); + + for (i = 0; i < ADI_APOLLO_ADC_NUM; i++) { + if ( (adc & (ADI_APOLLO_ADC_A0 << i)) > 0 ) { + adc_index = i; + break; + } + } + + set_ctrl_cmd.channel_num = adc_index; + + err = adi_apollo_mailbox_set_ctrl(device, &set_ctrl_cmd, &set_ctrl_resp); + if (err != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Error from adi_apollo_mailbox_set_ctrl() %d", err); + return err; + } + + if (set_ctrl_resp.status != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Mailbox Response Status Error from adi_apollo_mailbox_set_ctrl() 0x%X", set_ctrl_resp.status); + return API_CMS_ERROR_MAILBOX_RESP_STATUS; + } + + /* Extract Nyquist Zone info from response structure */ + *nyquist_zone = (set_ctrl_resp.data_buffer[4+0]) | (set_ctrl_resp.data_buffer[4+1] << 8) | + (set_ctrl_resp.data_buffer[4+2] << 16) | (set_ctrl_resp.data_buffer[4+3] << 24); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_adc_sync_path_delay_set(adi_apollo_device_t *device, adi_apollo_sync_path_delay_e delay_type) +{ + int32_t err; + uint8_t i; + uint32_t mbias; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_hal_bf_set(device, BF_C2A_TL1_SYNC_R_INFO, delay_type); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_C2A_TL1_SYNC_C_INFO, delay_type); + ADI_APOLLO_ERROR_RETURN(err); + + for (i = 0; i < ADI_APOLLO_NUM_SIDES; i++) { + mbias = calc_master_bias_base(i); + + err = adi_apollo_hal_bf_set(device, BF_C2S_SYNC_C_INFO(mbias), delay_type); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_ADC_TL1_SYNC_C_INFO(mbias), delay_type); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_ADC_TL2_SYNC_C_INFO(mbias), delay_type); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_C2B_TL2_SYNC_C_INFO(mbias), delay_type); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_S01_SYNC_C_INFO(mbias), delay_type); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_S23_SYNC_C_INFO(mbias), delay_type); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_C2S_SYNC_R_INFO(mbias), delay_type); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_ADC_TL1_SYNC_R_INFO(mbias), delay_type); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_ADC_TL2_SYNC_R_INFO(mbias), delay_type); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_C2B_TL2_SYNC_R_INFO(mbias), delay_type); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_S01_SYNC_R_INFO(mbias), delay_type); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_S23_SYNC_R_INFO(mbias), delay_type); + ADI_APOLLO_ERROR_RETURN(err); + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_adc_bgcal_state_get(adi_apollo_device_t *device, adi_apollo_blk_sel_t adcs, adi_apollo_adc_bgcal_state_t state[], uint32_t len) +{ + int32_t err = API_CMS_ERROR_OK; + uint8_t i; + adi_apollo_blk_sel_t adc; + adi_apollo_mailbox_resp_get_tracking_cal_state_t track_cal_state_resp = {0}; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(state); + ADI_APOLLO_INVALID_PARAM_RETURN(len < ADI_APOLLO_ADC_NUM); + ADI_APOLLO_ADC_BLK_SEL_MASK(adcs); + + if (err = adi_apollo_mailbox_get_tracking_cal_state(device, &track_cal_state_resp), err != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Error from adi_apollo_mailbox_get_tracking_cal_state() %d", err); + goto end; + } + + if (track_cal_state_resp.status != APOLLO_CPU_NO_ERROR) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "ADC BG cal state error code = 0x%x\n", track_cal_state_resp.status); + err = API_CMS_ERROR_MAILBOX_RESP_STATUS; + goto end; + } + + for (i = 0; i < ADI_APOLLO_ADC_NUM; i++) { + adc = adcs & (ADI_APOLLO_ADC_A0 << i); + if (adc > 0) { + state[i].state_valid = 1; + state[i].bgcal_error = track_cal_state_resp.tracking_cal_state.adc_rx_cal_error[i]; + state[i].bgcal_state = track_cal_state_resp.tracking_cal_state.adc_rx_cal_state[i]; + } else { + state[i].state_valid = 0; + state[i].bgcal_error = track_cal_state_resp.tracking_cal_state.adc_rx_cal_error[i]; + state[i].bgcal_state = track_cal_state_resp.tracking_cal_state.adc_rx_cal_state[i]; + } + } + +end: + return err; +} + +int32_t adi_apollo_adc_bgcal_freeze(adi_apollo_device_t* device, adi_apollo_blk_sel_t adcs) +{ + int32_t err = API_CMS_ERROR_OK; + adi_apollo_mailbox_cmd_set_enabled_tracking_cals_t track_cal_cmd = {0}; + adi_apollo_mailbox_resp_set_enabled_tracking_cals_t track_cal_resp = {0}; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_ADC_BLK_SEL_MASK(adcs); + + /* Init the mailbox command struct */ + track_cal_cmd.adc_rx_channel_mask = adcs; + track_cal_cmd.enable_disable = 0; + track_cal_cmd.serdes_rx_pack_mask = 0; + track_cal_cmd.mcs_tc_mask = 0; + + /* + * Freeze the background cals + */ + adi_apollo_hal_log_write(device, ADI_CMS_LOG_API, "Freezing ADC background tracking cals\n"); + + + if (err = adi_apollo_mailbox_set_enabled_tracking_cals(device, &track_cal_cmd, &track_cal_resp), err != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Error from adi_apollo_mailbox_set_enabled_tracking_cals() (freeze) %d\n", err); + goto end; + } + + if (track_cal_resp.status != APOLLO_CPU_NO_ERROR) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "ADC BG cal error code = 0x%x\n", track_cal_resp.status); + err = API_CMS_ERROR_ADC_TRACK_CAL_ERROR; + goto end; + } + +end: + return err; +} + +int32_t adi_apollo_adc_bgcal_unfreeze(adi_apollo_device_t* device, adi_apollo_blk_sel_t adcs) +{ + int32_t err = API_CMS_ERROR_OK; + adi_apollo_mailbox_cmd_set_enabled_tracking_cals_t track_cal_cmd = {0}; + adi_apollo_mailbox_resp_set_enabled_tracking_cals_t track_cal_resp = {0}; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_ADC_BLK_SEL_MASK(adcs); + + /* Init the mailbox command struct */ + track_cal_cmd.adc_rx_channel_mask = adcs; + track_cal_cmd.enable_disable = 1; + track_cal_cmd.serdes_rx_pack_mask = 0; + track_cal_cmd.mcs_tc_mask = 0; + /* + * Unfreeze the background cals + */ + adi_apollo_hal_log_write(device, ADI_CMS_LOG_API, "Unfreeze ADC background tracking cals\n"); + if (err = adi_apollo_mailbox_set_enabled_tracking_cals(device, &track_cal_cmd, &track_cal_resp), err != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Error from adi_apollo_mailbox_set_enabled_tracking_cals() (unfreeze) %d\n", err); + goto end; + } + + if (track_cal_resp.status != APOLLO_CPU_NO_ERROR) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "ADC BG cal error code = 0x%x\n", track_cal_resp.status); + err = API_CMS_ERROR_ADC_TRACK_CAL_ERROR; + goto end; + } + +end: + return err; +} + +int32_t adi_apollo_adc_mode_switch_enable_set(adi_apollo_device_t *device, uint8_t enable) +{ + int32_t err = API_CMS_ERROR_OK; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_hal_reg_set(device, REG_ADC_SLICE_MODE_SWITCH_ENABLE_ADDR, enable); + ADI_APOLLO_ERROR_RETURN(err); + + return err; +} + +int32_t adi_apollo_adc_mode_switch_prepare(adi_apollo_device_t *device, adi_apollo_blk_sel_t adcs) +{ + int32_t err = API_CMS_ERROR_OK; + uint8_t trig_status; + + adi_apollo_mailbox_resp_set_adc_slice_mode_fast_switch_action_t resp; + adi_apollo_mailbox_cmd_set_adc_slice_mode_fast_switch_action_t cmd; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_ADC_BLK_SEL_MASK(adcs); + + /* Init the mailbox command */ + cmd.adc_rx_channel_mask = adcs; + cmd.adc_slice_mode_fast_switch_action = APOLLO_ADC_PREP_FAST_MODE_SWITCH; + + err = adi_apollo_clk_mcs_trig_sync_enable_get(device, &trig_status); + ADI_APOLLO_ERROR_RETURN(err); + ADI_CMS_CHECK(trig_status != 0, API_CMS_ERROR_BAD_STATE); + + // Abort all background calibrations. + err = adi_apollo_adc_bgcal_freeze(device, adcs); + ADI_APOLLO_ERROR_RETURN(err); + + // Delay 50ms for ADC BG cals to disable and go inactive + err = adi_apollo_hal_delay_us(device, 50000); + ADI_APOLLO_ERROR_RETURN(err); + + // Set the ADC Channel Mask, where, Reg bits[7:0] corresponds to [B3 B2 B1 B0 A3 A2 A1 A0]. + err = adi_apollo_hal_reg_set(device, REG_ADC_SLICE_MODE_SWITCH_CHANNEL_MASK_ADDR, adcs); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_mailbox_set_adc_slice_mode_fast_switch_action(device, &cmd, &resp); + ADI_APOLLO_ERROR_RETURN(err); + if (resp.status != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Mailbox Response Status Error from adi_apollo_mailbox_set_adc_slice_mode_fast_switch_action() 0x%X", resp.status); + return API_CMS_ERROR_MAILBOX_RESP_STATUS; + } + + return err; +} + +int32_t adi_apollo_adc_mode_switch_execute(adi_apollo_device_t *device, adi_apollo_blk_sel_t adcs, adi_apollo_adc_mode_switch_method_e method) +{ + int32_t err = API_CMS_ERROR_OK; + + adi_apollo_mailbox_resp_set_adc_slice_mode_fast_switch_action_t resp; + adi_apollo_mailbox_cmd_set_adc_slice_mode_fast_switch_action_t cmd; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(method > ADI_APOLLO_ADC_MODE_SWITCH_BY_REGMAP); + ADI_APOLLO_ADC_BLK_SEL_MASK(adcs); + + /* Init the mailbox command */ + cmd.adc_rx_channel_mask = adcs; + cmd.adc_slice_mode_fast_switch_action = APOLLO_ADC_EXEC_FAST_MODE_SWITCH; + + if (method == ADI_APOLLO_ADC_MODE_SWITCH_BY_COMMAND) { + err = adi_apollo_mailbox_set_adc_slice_mode_fast_switch_action(device, &cmd, &resp); + ADI_APOLLO_ERROR_RETURN(err); + if (resp.status != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Mailbox Response Status Error from adi_apollo_mailbox_set_adc_slice_mode_fast_switch_action() 0x%X", resp.status); + return API_CMS_ERROR_MAILBOX_RESP_STATUS; + } + } else { + // Trigger the slice mode switch for above selected ADC channels. + err = adi_apollo_hal_reg_set(device, REG_ADC_SLICE_MODE_SWITCH_TRIGGER_ADDR, 1); + ADI_APOLLO_ERROR_RETURN(err); + } + + return err; +} + +int32_t adi_apollo_adc_mode_switch_restore(adi_apollo_device_t *device, adi_apollo_blk_sel_t adcs, uint8_t enable_bgcal) +{ + int32_t err = API_CMS_ERROR_OK; + + adi_apollo_mailbox_resp_set_adc_slice_mode_fast_switch_action_t resp; + adi_apollo_mailbox_cmd_set_adc_slice_mode_fast_switch_action_t cmd; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_ADC_BLK_SEL_MASK(adcs); + + /* Init the mailbox command */ + cmd.adc_rx_channel_mask = adcs; + cmd.adc_slice_mode_fast_switch_action = APOLLO_ADC_RESUME_FAST_MODE_SWITCH; + + err = adi_apollo_mailbox_set_adc_slice_mode_fast_switch_action(device, &cmd, &resp); + ADI_APOLLO_ERROR_RETURN(err); + if (resp.status != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Mailbox Response Status Error from adi_apollo_mailbox_set_adc_slice_mode_fast_switch_action() 0x%X", resp.status); + return API_CMS_ERROR_MAILBOX_RESP_STATUS; + } + + if (enable_bgcal) { + // Restart all background calibrations. + err = adi_apollo_adc_bgcal_unfreeze(device, adcs); + ADI_APOLLO_ERROR_RETURN(err); + } + + return err; +} + +int32_t adi_apollo_adc_fast_detect_pgm(adi_apollo_device_t *device, adi_apollo_blk_sel_t adcs, const adi_apollo_adc_fast_detect_pgm_t *config) +{ + adi_apollo_mailbox_cmd_set_ctrl_t set_ctrl_cmd = {0}; + adi_apollo_mailbox_resp_set_ctrl_t set_ctrl_resp = {0}; + int32_t err; + uint16_t i; + adi_apollo_blk_sel_t adc; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(config); + ADI_APOLLO_INVALID_PARAM_RETURN(config->lower_threshold > config->upper_threshold) + ADI_APOLLO_ADC_BLK_SEL_MASK(adcs); + + set_ctrl_cmd.sys_cal_object_id = APOLLO_CPU_OBJID_IC_ADC_RX; + set_ctrl_cmd.ctrl_cmd = CTRL_CMD_PARAM_SET; + set_ctrl_cmd.data_buffer[0] = ADI_APOLLO_ADC_FAST_DETECT_SETTINGS_STRUCT; + set_ctrl_cmd.data_buffer[4] = config->enable; + set_ctrl_cmd.data_buffer[8] = (config->upper_threshold) & 0xFFU; + set_ctrl_cmd.data_buffer[9] = (config->upper_threshold >> 8) & 0xFFU; + set_ctrl_cmd.data_buffer[10] = (config->lower_threshold) & 0xFFU; + set_ctrl_cmd.data_buffer[11] = (config->lower_threshold >> 8) & 0xFFU; + set_ctrl_cmd.data_buffer[12] = (config->dwell_cycles) & 0xFFU; + set_ctrl_cmd.data_buffer[13] = (config->dwell_cycles >> 8) & 0xFFU; + set_ctrl_cmd.data_buffer[14] = (config->dwell_cycles >> 16) & 0xFFU; + set_ctrl_cmd.data_buffer[15] = (config->dwell_cycles >> 24) & 0xFFU; + set_ctrl_cmd.length = 16; + + for (i = 0; i < ADI_APOLLO_ADC_NUM; i++) { + adc = adcs & (ADI_APOLLO_ADC_A0 << i); + + if (adc > 0) { + + set_ctrl_cmd.channel_num = i; + + err = adi_apollo_mailbox_set_ctrl(device, &set_ctrl_cmd, &set_ctrl_resp); + if (err != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Error from adi_apollo_mailbox_set_ctrl() %d", err); + return err; + } + + if (set_ctrl_resp.status != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Mailbox Response Status Error from adi_apollo_mailbox_set_ctrl() 0x%X", set_ctrl_resp.status); + return API_CMS_ERROR_MAILBOX_RESP_STATUS; + } + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_adc_fast_detect_status_get(adi_apollo_device_t *device, adi_apollo_blk_sel_t adc, uint8_t *fast_detect) +{ + adi_apollo_mailbox_cmd_set_ctrl_t set_ctrl_cmd = {0}; + adi_apollo_mailbox_resp_set_ctrl_t set_ctrl_resp = {0}; + int32_t err; + uint32_t fast_detect_status; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(fast_detect); + ADI_APOLLO_INVALID_PARAM_RETURN(adi_api_utils_num_selected(adc) != 1); + ADI_APOLLO_ADC_BLK_SEL_MASK(adc); + + set_ctrl_cmd.sys_cal_object_id = APOLLO_CPU_OBJID_IC_ADC_RX; + set_ctrl_cmd.ctrl_cmd = CTRL_CMD_PARAM_GET; + set_ctrl_cmd.data_buffer[0] = ADI_APOLLO_ADC_FAST_DETECT_STATUS_UINT32; + set_ctrl_cmd.length = 4; + set_ctrl_cmd.channel_num = adi_api_utils_select_lsb_get(adc); + + err = adi_apollo_mailbox_set_ctrl(device, &set_ctrl_cmd, &set_ctrl_resp); + if (err != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Error from adi_apollo_mailbox_set_ctrl() %d", err); + return err; + } + + if (set_ctrl_resp.status != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Mailbox Response Status Error from adi_apollo_mailbox_set_ctrl() 0x%X", set_ctrl_resp.status); + return API_CMS_ERROR_MAILBOX_RESP_STATUS; + } + + /* Extract fast detect info from response structure */ + fast_detect_status = (set_ctrl_resp.data_buffer[4+0]) | (set_ctrl_resp.data_buffer[4+1] << 8) | + (set_ctrl_resp.data_buffer[4+2] << 16) | (set_ctrl_resp.data_buffer[4+3] << 24); + + *fast_detect = (fast_detect_status == 0) ? 0 : 1; + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_adc_status_get(adi_apollo_device_t *device, adi_apollo_adc_status_t *status) +{ + int32_t err = API_CMS_ERROR_OK; + adi_apollo_mailbox_resp_run_init_get_detailed_status_t init_response = {0}; + adi_apollo_mailbox_resp_get_enabled_tracking_cals_t enabled_cals = {0}; + adi_apollo_mailbox_resp_get_tracking_cal_state_t cal_state = {0}; + adi_apollo_mailbox_resp_get_adc_slice_modes_t slice_modes = {0}; + uint8_t i; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(status); + + err = adi_apollo_mailbox_run_init_get_detailed_status(device, &init_response); + ADI_APOLLO_ERROR_RETURN(err); + if (init_response.status != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Mailbox Response Status Error from adi_apollo_mailbox_run_init_get_detailed_status() 0x%X", init_response.status); + return API_CMS_ERROR_MAILBOX_RESP_STATUS; + } + + err = adi_apollo_mailbox_get_enabled_tracking_cals(device, &enabled_cals); + ADI_APOLLO_ERROR_RETURN(err); + if (enabled_cals.status != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Mailbox Response Status Error from adi_apollo_mailbox_get_enabled_tracking_cals() 0x%X", enabled_cals.status); + return API_CMS_ERROR_MAILBOX_RESP_STATUS; + } + + err = adi_apollo_mailbox_get_tracking_cal_state(device, &cal_state); + ADI_APOLLO_ERROR_RETURN(err); + if (cal_state.status != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Mailbox Response Status Error from adi_apollo_mailbox_get_tracking_cal_state() 0x%X", cal_state.status); + return API_CMS_ERROR_MAILBOX_RESP_STATUS; + } + + err = adi_apollo_mailbox_get_adc_slice_modes(device, &slice_modes); + ADI_APOLLO_ERROR_RETURN(err); + if (slice_modes.status != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Mailbox Response Status Error from adi_apollo_mailbox_get_adc_slice_modes() 0x%X", slice_modes.status); + return API_CMS_ERROR_MAILBOX_RESP_STATUS; + } + + status->fg_cal.duration_ms = init_response.cals_duration_msec; + for (i = 0; i < ADI_APOLLO_ADC_NUM; i++) { + status->fg_cal.last_run[i] = ((init_response.cals_last_run[i] & APOLLO_INIT_CAL_MSK_IC_ADC_RX) > 0) ? 1 : 0; + status->fg_cal.since_power_up[i] = ((init_response.cals_since_power_up[i] & APOLLO_INIT_CAL_MSK_IC_ADC_RX) > 0) ? 1 : 0; + status->fg_cal.err_status[i] = ((init_response.init_err_cals[i] & APOLLO_INIT_CAL_MSK_IC_ADC_RX) > 0) ? 1 : 0; + + status->bg_cal.enabled[i] = (enabled_cals.tracking_cal_enable_masks.adc_rx_enable_masks & (1 << i)) ? 1 : 0; + status->bg_cal.error[i] = cal_state.tracking_cal_state.adc_rx_cal_error[i]; + status->bg_cal.state[i] = cal_state.tracking_cal_state.adc_rx_cal_state[i]; + + status->mode[i] = slice_modes.adc_slice_mode[i]; + } + + return err; +} + +int32_t adi_apollo_adc_bg_cal_grp_gate_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t adcs, uint32_t cal_gates) +{ + int32_t err; + uint16_t i; + adi_apollo_blk_sel_t adc; + adi_apollo_mailbox_cmd_set_ctrl_t set_ctrl_cmd = { + .sys_cal_object_id = APOLLO_CPU_OBJID_IC_ADC_RX, + .ctrl_cmd = CTRL_CMD_PARAM_SET, + .data_buffer[0] = ADI_APOLLO_ADC_CAL_GATING_GROUP_UINT32, + .data_buffer[1] = 0, + .data_buffer[2] = 0, + .data_buffer[3] = 0, + .data_buffer[4] = (cal_gates & 0xFFU), + .data_buffer[5] = (cal_gates & 0xFF00U) >> 8, + .data_buffer[6] = (cal_gates & 0xFF0000U) >> 16, + .data_buffer[7] = (cal_gates & 0xFF000000U) >> 24, + .length = 8 + }; + adi_apollo_mailbox_resp_set_ctrl_t set_ctrl_resp = {0}; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_ADC_BLK_SEL_MASK(adcs); + + for (i = 0; i < ADI_APOLLO_ADC_NUM; i++) { + adc = adcs & (ADI_APOLLO_ADC_A0 << i); + + if (adc > 0) { + set_ctrl_cmd.channel_num = i; + + err = adi_apollo_mailbox_set_ctrl(device, &set_ctrl_cmd, &set_ctrl_resp); + if (err != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Error from adi_apollo_mailbox_set_ctrl() %d", err); + return err; + } + + if (set_ctrl_resp.status != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Mailbox Response Status Error from adi_apollo_mailbox_set_ctrl() 0x%X", set_ctrl_resp.status); + return API_CMS_ERROR_MAILBOX_RESP_STATUS; + } + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_adc_bg_cal_grp_gate_get(adi_apollo_device_t *device, adi_apollo_blk_sel_t adc, uint32_t *cal_gates) +{ + int32_t err; + uint16_t i, adc_index; + adi_apollo_mailbox_cmd_set_ctrl_t set_ctrl_cmd = { + .sys_cal_object_id = APOLLO_CPU_OBJID_IC_ADC_RX, + .ctrl_cmd = CTRL_CMD_PARAM_GET, + .data_buffer[0] = ADI_APOLLO_ADC_CAL_GATING_GROUP_UINT32, + .data_buffer[1] = 0, + .data_buffer[2] = 0, + .data_buffer[3] = 0, + .length = 4 + }; + adi_apollo_mailbox_resp_set_ctrl_t set_ctrl_resp = {0}; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(cal_gates); + ADI_APOLLO_INVALID_PARAM_RETURN(adi_api_utils_num_selected(adc) != 1); + ADI_APOLLO_ADC_BLK_SEL_MASK(adc); + + for (i = 0; i < ADI_APOLLO_ADC_NUM; i++) { + if ( (adc & (ADI_APOLLO_ADC_A0 << i)) > 0 ) { + adc_index = i; + break; + } + } + + set_ctrl_cmd.channel_num = adc_index; + + err = adi_apollo_mailbox_set_ctrl(device, &set_ctrl_cmd, &set_ctrl_resp); + if (err != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Error from adi_apollo_mailbox_set_ctrl() %d", err); + return err; + } + + if (set_ctrl_resp.status != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Mailbox Response Status Error from adi_apollo_mailbox_set_ctrl() 0x%X", set_ctrl_resp.status); + return API_CMS_ERROR_MAILBOX_RESP_STATUS; + } + + /* Extract ADC BG Calibration gating info from response structure */ + *cal_gates = (set_ctrl_resp.data_buffer[4+0]) | (set_ctrl_resp.data_buffer[4+1] << 8) | + (set_ctrl_resp.data_buffer[4+2] << 16) | (set_ctrl_resp.data_buffer[4+3] << 24); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_adc_debug0_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t adcs, uint32_t debug_val) +{ + int32_t err; + uint16_t i; + adi_apollo_blk_sel_t adc; + adi_apollo_mailbox_cmd_set_ctrl_t set_ctrl_cmd = { + .sys_cal_object_id = APOLLO_CPU_OBJID_IC_ADC_RX, + .ctrl_cmd = CTRL_CMD_PARAM_SET, + .data_buffer[0] = ADI_APOLLO_ADC_DEBUG0_UINT32, + .data_buffer[1] = 0, + .data_buffer[2] = 0, + .data_buffer[3] = 0, + .data_buffer[4] = (debug_val & 0xFFU), + .data_buffer[5] = (debug_val & 0xFF00U) >> 8, + .data_buffer[6] = (debug_val & 0xFF0000U) >> 16, + .data_buffer[7] = (debug_val & 0xFF000000U) >> 24, + .length = 8 + }; + adi_apollo_mailbox_resp_set_ctrl_t set_ctrl_resp = {0}; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_ADC_BLK_SEL_MASK(adcs); + + for (i = 0; i < ADI_APOLLO_ADC_NUM; i++) { + adc = adcs & (ADI_APOLLO_ADC_A0 << i); + + if (adc > 0) { + set_ctrl_cmd.channel_num = i; + + err = adi_apollo_mailbox_set_ctrl(device, &set_ctrl_cmd, &set_ctrl_resp); + if (err != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Error from adi_apollo_mailbox_set_ctrl() %d", err); + return err; + } + + if (set_ctrl_resp.status != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Mailbox Response Status Error from adi_apollo_mailbox_set_ctrl() 0x%X", set_ctrl_resp.status); + return API_CMS_ERROR_MAILBOX_RESP_STATUS; + } + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_adc_debug0_get(adi_apollo_device_t *device, adi_apollo_blk_sel_t adc, uint32_t *debug_val) +{ + int32_t err; + uint16_t i, adc_index; + adi_apollo_mailbox_cmd_set_ctrl_t set_ctrl_cmd = { + .sys_cal_object_id = APOLLO_CPU_OBJID_IC_ADC_RX, + .ctrl_cmd = CTRL_CMD_PARAM_GET, + .data_buffer[0] = ADI_APOLLO_ADC_DEBUG0_UINT32, + .data_buffer[1] = 0, + .data_buffer[2] = 0, + .data_buffer[3] = 0, + .length = 4 + }; + adi_apollo_mailbox_resp_set_ctrl_t set_ctrl_resp = {0}; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(debug_val); + ADI_APOLLO_INVALID_PARAM_RETURN(adi_api_utils_num_selected(adc) != 1); + ADI_APOLLO_ADC_BLK_SEL_MASK(adc); + + for (i = 0; i < ADI_APOLLO_ADC_NUM; i++) { + if ( (adc & (ADI_APOLLO_ADC_A0 << i)) > 0 ) { + adc_index = i; + break; + } + } + + set_ctrl_cmd.channel_num = adc_index; + + err = adi_apollo_mailbox_set_ctrl(device, &set_ctrl_cmd, &set_ctrl_resp); + if (err != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Error from adi_apollo_mailbox_set_ctrl() %d", err); + return err; + } + + if (set_ctrl_resp.status != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Mailbox Response Status Error from adi_apollo_mailbox_set_ctrl() 0x%X", set_ctrl_resp.status); + return API_CMS_ERROR_MAILBOX_RESP_STATUS; + } + + /* Extract ADC BG Calibration gating info from response structure */ + *debug_val = (set_ctrl_resp.data_buffer[4+0]) | (set_ctrl_resp.data_buffer[4+1] << 8) | + (set_ctrl_resp.data_buffer[4+2] << 16) | (set_ctrl_resp.data_buffer[4+3] << 24); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_adc_input_status_get(adi_apollo_device_t *device, adi_apollo_blk_sel_t adc, adi_apollo_adc_input_status_t *input_status) +{ + int32_t err; + uint16_t i, adc_index; + uint32_t status_readback = 0; + adi_apollo_mailbox_cmd_set_ctrl_t set_ctrl_cmd = { + .sys_cal_object_id = APOLLO_CPU_OBJID_IC_ADC_RX, + .ctrl_cmd = CTRL_CMD_PARAM_GET, + .data_buffer[0] = ADI_APOLLO_ADC_INPUT_STATUS_UINT32, + .data_buffer[1] = 0, + .data_buffer[2] = 0, + .data_buffer[3] = 0, + .length = 4 + }; + adi_apollo_mailbox_resp_set_ctrl_t set_ctrl_resp = {0}; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(input_status); + ADI_APOLLO_INVALID_PARAM_RETURN(adi_api_utils_num_selected(adc) != 1); + ADI_APOLLO_ADC_BLK_SEL_MASK(adc); + + for (i = 0; i < ADI_APOLLO_ADC_NUM; i++) { + if ( (adc & (ADI_APOLLO_ADC_A0 << i)) > 0 ) { + adc_index = i; + break; + } + } + + set_ctrl_cmd.channel_num = adc_index; + + err = adi_apollo_mailbox_set_ctrl(device, &set_ctrl_cmd, &set_ctrl_resp); + if (err != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Error from adi_apollo_mailbox_set_ctrl() %d", err); + return err; + } + + if (set_ctrl_resp.status != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Mailbox Response Status Error from adi_apollo_mailbox_set_ctrl() 0x%X", set_ctrl_resp.status); + return API_CMS_ERROR_MAILBOX_RESP_STATUS; + } + + /* Extract ADC input status from response structure */ + status_readback = (set_ctrl_resp.data_buffer[4+0]) | (set_ctrl_resp.data_buffer[4+1] << 8) | + (set_ctrl_resp.data_buffer[4+2] << 16) | (set_ctrl_resp.data_buffer[4+3] << 24); + + input_status->power = (status_readback >> 0) & 0x01; + input_status->amp_diversity = (status_readback >> 1) & 0x01; + input_status->over_range = (status_readback >> 2) & 0x01; + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_adc_ovr_threshold_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t adcs, uint32_t ovr_threshold) +{ + int32_t err; + uint16_t i; + adi_apollo_blk_sel_t adc; + adi_apollo_mailbox_cmd_set_ctrl_t set_ctrl_cmd = { + .sys_cal_object_id = APOLLO_CPU_OBJID_IC_ADC_RX, + .ctrl_cmd = CTRL_CMD_PARAM_SET, + .data_buffer[0] = ADI_APOLLO_ADC_OVER_RANGE_THRESHOLD_UINT32, + .data_buffer[1] = 0, + .data_buffer[2] = 0, + .data_buffer[3] = 0, + .data_buffer[4] = (ovr_threshold & 0xFFU), + .data_buffer[5] = (ovr_threshold & 0xFF00U) >> 8, + .data_buffer[6] = (ovr_threshold & 0xFF0000U) >> 16, + .data_buffer[7] = (ovr_threshold & 0xFF000000U) >> 24, + .length = 8 + }; + adi_apollo_mailbox_resp_set_ctrl_t set_ctrl_resp = {0}; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_CMS_RANGE_CHECK(ovr_threshold, ADI_APOLLO_ADC_OVR_THRESH_M0P5_DB, ADI_APOLLO_ADC_OVR_THRESH_M4P0_DB); + ADI_APOLLO_ADC_BLK_SEL_MASK(adcs); + + for (i = 0; i < ADI_APOLLO_ADC_NUM; i++) { + adc = adcs & (ADI_APOLLO_ADC_A0 << i); + + if (adc > 0) { + set_ctrl_cmd.channel_num = i; + + err = adi_apollo_mailbox_set_ctrl(device, &set_ctrl_cmd, &set_ctrl_resp); + if (err != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Error from adi_apollo_mailbox_set_ctrl() %d", err); + return err; + } + + if (set_ctrl_resp.status != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Mailbox Response Status Error from adi_apollo_mailbox_set_ctrl() 0x%X", set_ctrl_resp.status); + return API_CMS_ERROR_MAILBOX_RESP_STATUS; + } + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_adc_ovr_threshold_get(adi_apollo_device_t *device, adi_apollo_blk_sel_t adc, uint32_t *ovr_threshold) +{ + int32_t err; + uint16_t i, adc_index; + adi_apollo_mailbox_cmd_set_ctrl_t set_ctrl_cmd = { + .sys_cal_object_id = APOLLO_CPU_OBJID_IC_ADC_RX, + .ctrl_cmd = CTRL_CMD_PARAM_GET, + .data_buffer[0] = ADI_APOLLO_ADC_OVER_RANGE_THRESHOLD_UINT32, + .data_buffer[1] = 0, + .data_buffer[2] = 0, + .data_buffer[3] = 0, + .length = 4 + }; + adi_apollo_mailbox_resp_set_ctrl_t set_ctrl_resp = {0}; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(ovr_threshold); + ADI_APOLLO_INVALID_PARAM_RETURN(adi_api_utils_num_selected(adc) != 1); + ADI_APOLLO_ADC_BLK_SEL_MASK(adc); + + for (i = 0; i < ADI_APOLLO_ADC_NUM; i++) { + if ( (adc & (ADI_APOLLO_ADC_A0 << i)) > 0 ) { + adc_index = i; + break; + } + } + + set_ctrl_cmd.channel_num = adc_index; + + err = adi_apollo_mailbox_set_ctrl(device, &set_ctrl_cmd, &set_ctrl_resp); + if (err != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Error from adi_apollo_mailbox_set_ctrl() %d", err); + return err; + } + + if (set_ctrl_resp.status != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Mailbox Response Status Error from adi_apollo_mailbox_set_ctrl() 0x%X", set_ctrl_resp.status); + return API_CMS_ERROR_MAILBOX_RESP_STATUS; + } + + /* Extract Over-Range Threshold info from response structure */ + *ovr_threshold = (set_ctrl_resp.data_buffer[4+0]) | (set_ctrl_resp.data_buffer[4+1] << 8) | + (set_ctrl_resp.data_buffer[4+2] << 16) | (set_ctrl_resp.data_buffer[4+3] << 24); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_adc_ovr_samples_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t adcs, uint32_t num_samples) +{ + int32_t err; + uint16_t i; + adi_apollo_blk_sel_t adc; + adi_apollo_mailbox_cmd_set_ctrl_t set_ctrl_cmd = { + .sys_cal_object_id = APOLLO_CPU_OBJID_IC_ADC_RX, + .ctrl_cmd = CTRL_CMD_PARAM_SET, + .data_buffer[0] = ADI_APOLLO_ADC_OVER_RANGE_SAMPLES_UINT32, + .data_buffer[1] = 0, + .data_buffer[2] = 0, + .data_buffer[3] = 0, + .data_buffer[4] = (num_samples & 0xFFU), + .data_buffer[5] = (num_samples & 0xFF00U) >> 8, + .data_buffer[6] = (num_samples & 0xFF0000U) >> 16, + .data_buffer[7] = (num_samples & 0xFF000000U) >> 24, + .length = 8 + }; + adi_apollo_mailbox_resp_set_ctrl_t set_ctrl_resp = {0}; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_CMS_RANGE_CHECK(num_samples, ADC_OVR_SAMPLES_MIN, ADC_OVR_SAMPLES_MAX); + ADI_APOLLO_ADC_BLK_SEL_MASK(adcs); + + for (i = 0; i < ADI_APOLLO_ADC_NUM; i++) { + adc = adcs & (ADI_APOLLO_ADC_A0 << i); + + if (adc > 0) { + set_ctrl_cmd.channel_num = i; + + err = adi_apollo_mailbox_set_ctrl(device, &set_ctrl_cmd, &set_ctrl_resp); + if (err != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Error from adi_apollo_mailbox_set_ctrl() %d", err); + return err; + } + + if (set_ctrl_resp.status != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Mailbox Response Status Error from adi_apollo_mailbox_set_ctrl() 0x%X", set_ctrl_resp.status); + return API_CMS_ERROR_MAILBOX_RESP_STATUS; + } + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_adc_ovr_samples_get(adi_apollo_device_t *device, adi_apollo_blk_sel_t adc, uint32_t *num_samples) +{ + int32_t err; + uint16_t i, adc_index; + adi_apollo_mailbox_cmd_set_ctrl_t set_ctrl_cmd = { + .sys_cal_object_id = APOLLO_CPU_OBJID_IC_ADC_RX, + .ctrl_cmd = CTRL_CMD_PARAM_GET, + .data_buffer[0] = ADI_APOLLO_ADC_OVER_RANGE_SAMPLES_UINT32, + .data_buffer[1] = 0, + .data_buffer[2] = 0, + .data_buffer[3] = 0, + .length = 4 + }; + adi_apollo_mailbox_resp_set_ctrl_t set_ctrl_resp = {0}; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(num_samples); + ADI_APOLLO_INVALID_PARAM_RETURN(adi_api_utils_num_selected(adc) != 1); + ADI_APOLLO_ADC_BLK_SEL_MASK(adc); + + for (i = 0; i < ADI_APOLLO_ADC_NUM; i++) { + if ( (adc & (ADI_APOLLO_ADC_A0 << i)) > 0 ) { + adc_index = i; + break; + } + } + + set_ctrl_cmd.channel_num = adc_index; + + err = adi_apollo_mailbox_set_ctrl(device, &set_ctrl_cmd, &set_ctrl_resp); + if (err != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Error from adi_apollo_mailbox_set_ctrl() %d", err); + return err; + } + + if (set_ctrl_resp.status != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Mailbox Response Status Error from adi_apollo_mailbox_set_ctrl() 0x%X", set_ctrl_resp.status); + return API_CMS_ERROR_MAILBOX_RESP_STATUS; + } + + /* Extract Num of samples at or above over-range threshold from response structure */ + *num_samples = (set_ctrl_resp.data_buffer[4+0]) | (set_ctrl_resp.data_buffer[4+1] << 8) | + (set_ctrl_resp.data_buffer[4+2] << 16) | (set_ctrl_resp.data_buffer[4+3] << 24); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_adc_fact_cal_status_get(adi_apollo_device_t *device, adi_apollo_blk_sel_t adc, uint64_t *coeff_status) +{ + int32_t err; + uint16_t i, adc_index; + adi_apollo_mailbox_cmd_set_ctrl_t set_ctrl_cmd = { + .sys_cal_object_id = APOLLO_CPU_OBJID_IC_ADC_RX, + .ctrl_cmd = CTRL_CMD_PARAM_GET, + .data_buffer[0] = ADI_APOLLO_ADC_FACTORY_CAL_COEFF_STATUS_UINT64, + .data_buffer[1] = 0, + .data_buffer[2] = 0, + .data_buffer[3] = 0, + .length = 8 + }; + adi_apollo_mailbox_resp_set_ctrl_t set_ctrl_resp = {0}; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(coeff_status); + ADI_APOLLO_INVALID_PARAM_RETURN(adi_api_utils_num_selected(adc) != 1); + ADI_APOLLO_ADC_BLK_SEL_MASK(adc); + + for (i = 0; i < ADI_APOLLO_ADC_NUM; i++) { + if ( (adc & (ADI_APOLLO_ADC_A0 << i)) > 0 ) { + adc_index = i; + break; + } + } + + set_ctrl_cmd.channel_num = adc_index; + + err = adi_apollo_mailbox_set_ctrl(device, &set_ctrl_cmd, &set_ctrl_resp); + if (err != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Error from adi_apollo_mailbox_set_ctrl() %d", err); + return err; + } + + if (set_ctrl_resp.status != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Mailbox Response Status Error from adi_apollo_mailbox_set_ctrl() 0x%X", set_ctrl_resp.status); + return API_CMS_ERROR_MAILBOX_RESP_STATUS; + } + + /* Extract Num of samples at or above over-range threshold from response structure */ + *coeff_status = (uint64_t)(set_ctrl_resp.data_buffer[4+0]) | ((uint64_t)(set_ctrl_resp.data_buffer[4+1]) << 8) | + ((uint64_t)(set_ctrl_resp.data_buffer[4+2]) << 16) | ((uint64_t)(set_ctrl_resp.data_buffer[4+3]) << 24) | + ((uint64_t)(set_ctrl_resp.data_buffer[4+4]) << 32) | ((uint64_t)(set_ctrl_resp.data_buffer[4+5]) << 40) | + ((uint64_t)(set_ctrl_resp.data_buffer[4+6]) << 48) | ((uint64_t)(set_ctrl_resp.data_buffer[4+7]) << 56); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_adc_fact_cal_mode_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t adcs, uint32_t coeff_mode) +{ + int32_t err; + uint16_t i; + adi_apollo_blk_sel_t adc; + adi_apollo_mailbox_cmd_set_ctrl_t set_ctrl_cmd = { + .sys_cal_object_id = APOLLO_CPU_OBJID_IC_ADC_RX, + .ctrl_cmd = CTRL_CMD_PARAM_SET, + .data_buffer[0] = ADI_APOLLO_ADC_FACTORY_CAL_COEFF_MODE_UINT32, + .data_buffer[1] = 0, + .data_buffer[2] = 0, + .data_buffer[3] = 0, + .data_buffer[4] = (coeff_mode & 0xFFU), + .data_buffer[5] = (coeff_mode & 0xFF00U) >> 8, + .data_buffer[6] = (coeff_mode & 0xFF0000U) >> 16, + .data_buffer[7] = (coeff_mode & 0xFF000000U) >> 24, + .length = 8 + }; + adi_apollo_mailbox_resp_set_ctrl_t set_ctrl_resp = {0}; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + /* TOBE DEFINED by ADC ADI_CMS_RANGE_CHECK(coeff_mode, ADC_COEFF_MODE_MIN, ADC_COEFF_MODE_MAX); */ + ADI_APOLLO_ADC_BLK_SEL_MASK(adcs); + + for (i = 0; i < ADI_APOLLO_ADC_NUM; i++) { + adc = adcs & (ADI_APOLLO_ADC_A0 << i); + + if (adc > 0) { + set_ctrl_cmd.channel_num = i; + + err = adi_apollo_mailbox_set_ctrl(device, &set_ctrl_cmd, &set_ctrl_resp); + if (err != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Error from adi_apollo_mailbox_set_ctrl() %d", err); + return err; + } + + if (set_ctrl_resp.status != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Mailbox Response Status Error from adi_apollo_mailbox_set_ctrl() 0x%X", set_ctrl_resp.status); + return API_CMS_ERROR_MAILBOX_RESP_STATUS; + } + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_adc_fact_cal_mode_get(adi_apollo_device_t *device, adi_apollo_blk_sel_t adc, uint32_t *coeff_mode) +{ + int32_t err; + uint16_t i, adc_index; + adi_apollo_mailbox_cmd_set_ctrl_t set_ctrl_cmd = { + .sys_cal_object_id = APOLLO_CPU_OBJID_IC_ADC_RX, + .ctrl_cmd = CTRL_CMD_PARAM_GET, + .data_buffer[0] = ADI_APOLLO_ADC_FACTORY_CAL_COEFF_MODE_UINT32, + .data_buffer[1] = 0, + .data_buffer[2] = 0, + .data_buffer[3] = 0, + .length = 4 + }; + adi_apollo_mailbox_resp_set_ctrl_t set_ctrl_resp = {0}; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(coeff_mode); + ADI_APOLLO_INVALID_PARAM_RETURN(adi_api_utils_num_selected(adc) != 1); + ADI_APOLLO_ADC_BLK_SEL_MASK(adc); + + for (i = 0; i < ADI_APOLLO_ADC_NUM; i++) { + if ( (adc & (ADI_APOLLO_ADC_A0 << i)) > 0 ) { + adc_index = i; + break; + } + } + + set_ctrl_cmd.channel_num = adc_index; + + err = adi_apollo_mailbox_set_ctrl(device, &set_ctrl_cmd, &set_ctrl_resp); + if (err != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Error from adi_apollo_mailbox_set_ctrl() %d", err); + return err; + } + + if (set_ctrl_resp.status != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Mailbox Response Status Error from adi_apollo_mailbox_set_ctrl() 0x%X", set_ctrl_resp.status); + return API_CMS_ERROR_MAILBOX_RESP_STATUS; + } + + /* Extract Num of samples at or above over-range threshold from response structure */ + *coeff_mode = (set_ctrl_resp.data_buffer[4+0]) | (set_ctrl_resp.data_buffer[4+1] << 8) | + (set_ctrl_resp.data_buffer[4+2] << 16) | (set_ctrl_resp.data_buffer[4+3] << 24); + + return API_CMS_ERROR_OK; +} + +static uint32_t calc_master_bias_base(int32_t index) +{ + static uint32_t master_bias_base_addr[] = { + MBIAS0, MBIAS1 + }; + + return master_bias_base_addr[index]; +} + +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_arm.c b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_arm.c new file mode 100644 index 00000000000000..4dba1379244313 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_arm.c @@ -0,0 +1,744 @@ + /*! + * \brief API implementation ARM CPU + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_ARM + * @{ + */ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_arm.h" +#include "adi_apollo_config.h" + +#include "adi_apollo_bf_custom.h" +#include "adi_apollo_bf_core.h" +#include "adi_apollo_bf_mb_regs.h" + +#include "adi_apollo_hal.h" + +#define SIM_BF_ALT18_FW_STATUS REG_ALT_BOOT_ADDR(18), 0x00000800 +#define SIM_BF_RAM_BOOT_STATUS REG_ALT_BOOT_ADDR(21), 0x00000800 +#define SIM_BF_RAM_BOOT_ERROR REG_ALT_BOOT_ADDR(22), 0x00000800 + +static int32_t adi_apollo_arm_fw_load_check(adi_apollo_device_t *device, uint8_t *status); +static int32_t adi_apollo_arm_profile_load_check(adi_apollo_device_t *device, uint8_t *status); +static int32_t adi_apollo_arm_boot_status_clear(adi_apollo_device_t *device); +static int32_t adi_apollo_arm_core_reset(adi_apollo_device_t *device, uint8_t core); +static int32_t adi_apollo_arm_ram_lock_check(adi_apollo_device_t *device); +static int32_t adi_apollo_arm_stack_ptr_boot_addr_set(adi_apollo_device_t *device, uint8_t core, adi_apollo_arm_binary_info_t *binary_info); +static int32_t get_cpu_device_profile_start_address(adi_apollo_device_t *device, uint32_t *cpu_device_profile_addr); +static int32_t adi_apollo_arm_tye_bootstage_check(adi_apollo_device_t *device, uint8_t stage, uint8_t is_encrypted); +static int32_t device_feat_lockout_set(adi_apollo_device_t *device); + +/*==================== P U B L I C A P I C O D E ====================*/ + +int32_t adi_apollo_arm_boot_status(adi_apollo_device_t *device, uint8_t *status) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + //ADI_APOLLO_LOG_FUNC(); + + // Core1 Boot Status + err = adi_apollo_hal_bf_get(device, BF_RAM_BOOT_CORE1_STATUS, status, 1); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_arm_ram_boot_error_check(adi_apollo_device_t *device) +{ + int32_t err; + uint32_t status = 0x00; + adi_apollo_cpu_errors_t cpu_errors; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_arm_err_codes_get(device, &cpu_errors); + ADI_APOLLO_ERROR_RETURN(err); + /* boot errors are stored under the system category */ + status = cpu_errors.system; + ADI_APOLLO_LOG_MSG_VAR("REG_RAM_BOOT_ERROR 0x%X", status); + + /* use only 16-bits of status */ + status = status & 0xFFFF; + ADI_APOLLO_ERROR_RETURN(status); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_arm_rom_ec_transfer_check(adi_apollo_device_t *device) +{ + int32_t err; + uint8_t status; + uint32_t retry_count = 50; + uint32_t poll_delay_us = 100000; // 100ms + uint32_t i; + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + adi_apollo_hal_regio_t *desc = (adi_apollo_hal_regio_t *) device->hal_info.active_regio; + + for (i = 0; i < retry_count; i++) { + + err = adi_apollo_hal_reg_poll_get(device, REG_ADDR_EXTRACT(BF_BOOT_STATUS), &status, retry_count * poll_delay_us, ADI_APOLLO_ROM_BOOT_STEP_EC_TRANSFER, 0xff); + ADI_APOLLO_ERROR_RETURN(err); + + if (status >= ADI_APOLLO_ROM_BOOT_STEP_EC_TRANSFER || !desc->poll_read_returns_val) { + err = API_CMS_ERROR_OK; + break; + } + + // Delay before next poll read + err = adi_apollo_hal_delay_us(device, poll_delay_us); + ADI_APOLLO_ERROR_RETURN(err); + } + + if (status < ADI_APOLLO_ROM_BOOT_STEP_EC_TRANSFER) { + err = API_CMS_ERROR_ERROR; + } + + ADI_APOLLO_LOG_MSG_VAR("EC Transfer Flag : %d.", status); + ADI_APOLLO_LOG_MSG_VAR("EC Transfer Check : %s.", (status >= ADI_APOLLO_ROM_BOOT_STEP_EC_TRANSFER) ? "Passed" : "*** FAILED ***"); + + return err; +} + +int32_t adi_apollo_arm_profile_crc_valid_get(adi_apollo_device_t *device) +{ + int32_t err; + uint8_t val; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_hal_bf_get(device, BF_DEVICE_PROFILE_CRC_CHECK_STATUS, (uint8_t *)&val, sizeof(val)); + ADI_APOLLO_ERROR_RETURN(err); + + return val ? API_CMS_ERROR_PROFILE_CRC : API_CMS_ERROR_OK; + +} + +int32_t adi_apollo_arm_fwload_pre_config(adi_apollo_device_t *device) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + /* Check for RAM Lock */ + err = adi_apollo_arm_ram_lock_check(device); + ADI_APOLLO_ERROR_RETURN(err); + + /* Stop ARM core 0 */ + err = adi_apollo_hal_bf_set(device, BF_ARM0_M3_RUN_INFO, 0); + ADI_APOLLO_ERROR_RETURN(err); + + /* Stop ARM core 1 */ + err = adi_apollo_hal_bf_set(device, BF_ARM1_M3_RUN_INFO, 0); + ADI_APOLLO_ERROR_RETURN(err); + + /* Clear boot status */ + err = adi_apollo_arm_boot_status_clear(device); + ADI_APOLLO_ERROR_RETURN(err); + + /* Memory Bank division control set (Core 0)*/ + err = adi_apollo_hal_bf_set(device, BF_L1MEM0_SHARED_BANK_DIV_INFO, ADI_APOLLO_DIV_IRAM_384K_DRAM_320K); + ADI_APOLLO_ERROR_RETURN(err); + + /* Memory Bank division control set (Core 1)*/ + err = adi_apollo_hal_bf_set(device, BF_L1MEM1_SHARED_BANK_DIV_INFO, ADI_APOLLO_DIV_IRAM_352K_DRAM_352K); + ADI_APOLLO_ERROR_RETURN(err); + + /* Make core 1 Primary */ + err = adi_apollo_hal_bf_set(device, BF_CPU_0_PRIMARY, 0); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_CPU_1_PRIMARY, 1); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_arm_fwload_post_config(adi_apollo_device_t *device) +{ + int32_t err; + uint8_t status; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + /* Reset core 0 */ + err = adi_apollo_arm_core_reset(device, ADI_APOLLO_CPU_ID_0); + ADI_APOLLO_ERROR_RETURN(err); + + /* Start core 1 */ + err = adi_apollo_hal_bf_set(device, BF_ARM1_M3_RUN_INFO, 1); + ADI_APOLLO_ERROR_RETURN(err); + + /* Start core 0 */ + err = adi_apollo_hal_bf_set(device, BF_ARM0_M3_RUN_INFO, 1); + ADI_APOLLO_ERROR_RETURN(err); + + // Delay 100ms to start the core + err = adi_apollo_hal_delay_us(device, 100000); + + /* Check the FW boot status is waiting for device profile config */ + err = adi_apollo_arm_fw_load_check(device, &status); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_arm_profile_write(adi_apollo_device_t *device, adi_apollo_top_t *profile, uint16_t chunk_sz_bytes) +{ + int32_t err; + adi_apollo_arm_binary_info_t binary_info; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(profile); + + binary_info.binary_ptr = (uint8_t *)profile; + binary_info.binary_sz_bytes = sizeof(struct adi_apollo_top); + binary_info.is_cont = 0; + get_cpu_device_profile_start_address(device, &(binary_info.cpu_start_addr)); + + err = adi_apollo_arm_memload(device, &binary_info, chunk_sz_bytes); + ADI_APOLLO_ERROR_RETURN(err); + + /* V10 Profile update: Clock config field 'single_dual_clk_sel' renamed to 'is_dual_clk' (type unchanged) - COMPLETED */ + device->dev_info.is_dual_clk = profile->clk_cfg.is_dual_clk; + /* V10 Profile update: Field 'dev_clk_freq_kHz' renamed to 'dev_clk_freq_Hz' (uint32_t->uint64_t, kHz->Hz, remove *1000 multiplication) */ + device->dev_info.dev_freq_hz = (uint64_t)profile->clk_cfg.dev_clk_freq_Hz; + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_arm_profile_write_post_config(adi_apollo_device_t *device, adi_apollo_top_t *profile) +{ + int32_t err; + uint8_t status; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(profile); + + /* set transfer done flag */ + err = adi_apollo_hal_bf_set(device, BF_CONFIG_TRANSFER_DONE, 1); + ADI_APOLLO_ERROR_RETURN(err); + + /* read boot status */ + err = adi_apollo_arm_profile_load_check(device, &status); + ADI_APOLLO_ERROR_RETURN(err); + + /* check CRC */ + if (err = adi_apollo_arm_profile_crc_valid_get(device), err == API_CMS_ERROR_PROFILE_CRC) { + ADI_APOLLO_LOG_WARN("profile crc is invalid."); + } + + /* Store device feature enable configurations */ + device_feat_lockout_set(device); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_arm_profile_buf_write(adi_apollo_device_t *device, uint8_t profile_buf[], uint32_t profile_size_bytes, uint16_t chunk_sz_bytes) +{ + int32_t err; + adi_apollo_arm_binary_info_t binary_info; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(profile_buf); + ADI_APOLLO_INVALID_PARAM_RETURN(profile_size_bytes != sizeof(adi_apollo_top_t)); + + binary_info.binary_ptr = (uint8_t *)profile_buf; + binary_info.binary_sz_bytes = profile_size_bytes; + binary_info.is_cont = 0; + get_cpu_device_profile_start_address(device, &(binary_info.cpu_start_addr)); + + err = adi_apollo_arm_memload(device, &binary_info, chunk_sz_bytes); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_arm_firmware_buf_write(adi_apollo_device_t *device, uint8_t core, uint8_t fw_image_buf[], uint32_t fw_image_size_bytes, uint16_t chunk_sz_bytes) +{ + adi_apollo_arm_binary_info_t binary_info; + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(fw_image_buf); + ADI_APOLLO_INVALID_PARAM_RETURN(core > ADI_APOLLO_CPU_ID_1); + + binary_info.binary_ptr = &fw_image_buf[0]; + binary_info.binary_sz_bytes = fw_image_size_bytes; + binary_info.cpu_start_addr = (core == ADI_APOLLO_CPU_ID_0) ? ADI_APOLLO_CPU0_PM_START : ADI_APOLLO_CPU1_PM_START; + binary_info.is_cont = 0; + + /* Set Core's Stack ptr and Boot Addr */ + err = adi_apollo_arm_stack_ptr_boot_addr_set(device, core, &binary_info); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_arm_memload(device, &binary_info, chunk_sz_bytes); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_arm_tye_firmware_buf_write(adi_apollo_device_t *device, uint32_t mem_addr_to_load, uint8_t fw_image_buf[], uint32_t fw_image_size_bytes, uint16_t chunk_sz_bytes) +{ + adi_apollo_arm_binary_info_t binary_info; + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(fw_image_buf); + + binary_info.binary_ptr = &fw_image_buf[0]; + binary_info.binary_sz_bytes = fw_image_size_bytes; + binary_info.cpu_start_addr = mem_addr_to_load; + binary_info.is_cont = 0; + + err = adi_apollo_arm_memload(device, &binary_info, chunk_sz_bytes); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_arm_memload(adi_apollo_device_t *device, adi_apollo_arm_binary_info_t *binary_info, uint16_t chunk_sz_bytes) +{ + int32_t err; + uint32_t cpu_address_to_load; + int32_t pending_bytes; + uint8_t *data_ptr; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(binary_info); + ADI_APOLLO_NULL_POINTER_RETURN(binary_info->binary_ptr); + ADI_APOLLO_INVALID_PARAM_RETURN(binary_info->binary_sz_bytes < 1); + ADI_APOLLO_INVALID_PARAM_RETURN(chunk_sz_bytes < 1 || chunk_sz_bytes > (16 * 1024)); // A0 has max stream limit of 16k + ADI_APOLLO_INVALID_PARAM_RETURN(chunk_sz_bytes % 4); + + pending_bytes = binary_info->binary_sz_bytes; + + /* chunk size should not be bigger then total size and should always be % 4 */ + if (chunk_sz_bytes > binary_info->binary_sz_bytes) { + chunk_sz_bytes = binary_info->binary_sz_bytes - (binary_info->binary_sz_bytes % 4); + } + + cpu_address_to_load = binary_info->cpu_start_addr; + + data_ptr = binary_info->binary_ptr; + + ADI_APOLLO_LOG_MSG_VAR("Loading %d bytes", pending_bytes); + + /* Send data in chunk_sz_bytes */ + while (pending_bytes > 0 && pending_bytes / chunk_sz_bytes > 0) { + err = adi_apollo_hal_stream_reg32_set(device, cpu_address_to_load, (uint32_t *)data_ptr, chunk_sz_bytes / 4, binary_info->is_cont); + ADI_APOLLO_ERROR_RETURN(err); + + pending_bytes -= chunk_sz_bytes; + binary_info->is_cont = 1; + data_ptr += chunk_sz_bytes; + cpu_address_to_load += chunk_sz_bytes; + } + + /* send remaining bytes */ + if (pending_bytes > 0) { + /* have to reset the FIFO and reconfigure the SPI bus to 8-bit txn */ + binary_info->is_cont = 0; + err = adi_apollo_hal_stream_reg_set(device, cpu_address_to_load, data_ptr, pending_bytes, binary_info->is_cont); + ADI_APOLLO_ERROR_RETURN(err); + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_arm_tye_bypassed_get(adi_apollo_device_t *device, uint8_t *is_bypassed) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(is_bypassed); + + err = adi_apollo_hal_bf_get(device, BF_NVMB_TE_BYPASS_INFO, is_bypassed, 1); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_arm_tye_boot_ready_set(adi_apollo_device_t *device) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_hal_bf_set(device, BF_TE_BOOT_READY_SET, 1); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_arm_tye_validate_boot_completion(adi_apollo_device_t *device, uint8_t is_encrypted) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(is_encrypted > 1); + + err = adi_apollo_arm_tye_bootstage_check(device, 0, is_encrypted); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_arm_tye_bootstage_check(device, 1, is_encrypted); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_arm_err_codes_get(adi_apollo_device_t *device, adi_apollo_cpu_errors_t *cpu_errs) +{ + int32_t err = API_CMS_ERROR_OK; + uint32_t err_ptr = 0x00; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(cpu_errs); + + /* Get location of error struct */ + err = adi_apollo_hal_reg32_get(device, REG_RAM_BOOT_ERROR_PTR, &err_ptr); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_reg32_get(device, err_ptr + 0, (uint32_t *) &(cpu_errs->last_cmd)); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_reg32_get(device, err_ptr + 4, (uint32_t*) &(cpu_errs->system)); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_reg32_get(device, err_ptr + 8, (uint32_t*) &(cpu_errs->track_cal)); + ADI_APOLLO_ERROR_RETURN(err); + + return err; +} + +int32_t adi_apollo_arm_fw_irq_out_get(adi_apollo_device_t *device, uint8_t *fw_irq_out, uint32_t *irq_source) +{ + int32_t err = API_CMS_ERROR_OK; + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(fw_irq_out); + ADI_APOLLO_NULL_POINTER_RETURN(irq_source); + + err = adi_apollo_hal_bf_get(device, BF_FW_IRQ_OUT_INFO, fw_irq_out, sizeof(*fw_irq_out)); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_get(device, BF_FW_IRQ_OUT_SOURCE_INFO, (uint8_t*)irq_source, sizeof(*irq_source)); + ADI_APOLLO_ERROR_RETURN(err); + + return err; +} + +int32_t adi_apollo_arm_fw_irq_out_clear(adi_apollo_device_t *device) +{ + int32_t err = API_CMS_ERROR_OK; + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_hal_bf_set(device, BF_FW_IRQ_OUT_INFO, 0); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_FW_IRQ_OUT_SOURCE_INFO, 0); + ADI_APOLLO_ERROR_RETURN(err); + + return err; +} + +/* Wait for firmware boot status to be wait_for_config */ +static int32_t adi_apollo_arm_fw_load_check(adi_apollo_device_t *device, uint8_t *status) +{ + int32_t err; + uint8_t retry_count = ADI_APOLLO_ARM_BOOT_STATUS_READ_RETRY_COUNT; + uint32_t poll_delay_us = 100000; // 100ms + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + adi_apollo_hal_regio_t *desc = (adi_apollo_hal_regio_t *) device->hal_info.active_regio; + + /* Read boot status - wait for state ADI_APOLLO_RAM_BOOT_STEP_WAIT_FOR_CONFIG */ + do { + + err = adi_apollo_hal_reg_poll_get(device, REG_ADDR_EXTRACT(BF_RAM_BOOT_CORE1_STATUS), status, + ADI_APOLLO_ARM_BOOT_STATUS_READ_RETRY_COUNT* poll_delay_us, + ADI_APOLLO_RAM_BOOT_STEP_WAIT_FOR_CONFIG, 0xff); + ADI_APOLLO_ERROR_RETURN(err); + + ADI_APOLLO_LOG_MSG_VAR("BF_RAM_BOOT_CORE1_STATUS: %d.", *status); + + if (*status >= ADI_APOLLO_RAM_BOOT_STEP_WAIT_FOR_CONFIG || !desc->poll_read_returns_val) { + return API_CMS_ERROR_OK; + } + + // Delay 'poll_delay_us' to wait before reading status again + err = adi_apollo_hal_delay_us(device, poll_delay_us); + ADI_APOLLO_ERROR_RETURN(err); + + retry_count--; + } while (retry_count); + + return API_CMS_ERROR_ERROR; +} + +/* Wait for firmware boot status to be >= profile crc check passed */ +static int32_t adi_apollo_arm_profile_load_check(adi_apollo_device_t *device, uint8_t *status) +{ + int32_t err; + uint8_t retry_count = ADI_APOLLO_ARM_BOOT_STATUS_READ_RETRY_COUNT; + uint32_t poll_delay_us = 100000; // 100ms + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + adi_apollo_hal_regio_t *desc = (adi_apollo_hal_regio_t *) device->hal_info.active_regio; + + /* Read boot status - wait for state ADI_APOLLO_RAM_BOOT_STEP_DEVICE_CONFIG_CRC_CHECK */ + do { + err = adi_apollo_hal_reg_poll_get(device, REG_ADDR_EXTRACT(BF_RAM_BOOT_CORE1_STATUS), status, + ADI_APOLLO_ARM_BOOT_STATUS_READ_RETRY_COUNT * poll_delay_us, + ADI_APOLLO_RAM_BOOT_STEP_DEVICE_CONFIG_CRC_CHECK, 0xff); + ADI_APOLLO_ERROR_RETURN(err); + + if (*status >= ADI_APOLLO_RAM_BOOT_STEP_DEVICE_CONFIG_CRC_CHECK || !desc->poll_read_returns_val) { + return API_CMS_ERROR_OK; + } + + // Delay 'poll_delay_us' to wait before reading status again + err = adi_apollo_hal_delay_us(device, poll_delay_us); + ADI_APOLLO_ERROR_RETURN(err); + + retry_count--; + } while (retry_count); + + return API_CMS_ERROR_ERROR; +} + +static int32_t adi_apollo_arm_tye_bootstage_check(adi_apollo_device_t *device, uint8_t stage, uint8_t is_encrypted) +{ + int32_t err; + uint8_t status; + uint8_t error; + uint8_t expected_value; + uint32_t bootstage_reg_addr; + uint32_t error_reg_addr; + uint32_t error_bf_info; + uint8_t retry_count = ADI_APOLLO_ARM_BOOT_STATUS_READ_RETRY_COUNT; + uint32_t poll_delay_us = 100000; // 100ms + uint8_t i; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(is_encrypted > 1); + ADI_APOLLO_INVALID_PARAM_RETURN(stage > 1); + + expected_value = (is_encrypted == 0) ? ADI_SECURE_BOOT_STAGE_CHECK : ADI_ENCR_SECURE_BOOT_STAGE_CHECK; + bootstage_reg_addr = (stage == 0) ? REG_SECURE_BOOT_STAGE0 : REG_SECURE_BOOT_STAGE1; + error_reg_addr = (stage == 0) ? REG_ADDR_EXTRACT(BF_ERROR_CODE_0_INFO) : REG_ADDR_EXTRACT(BF_ERROR_CODE_1_INFO); + error_bf_info = (stage == 0) ? BF_INFO_EXTRACT(BF_ERROR_CODE_0_INFO) : BF_INFO_EXTRACT(BF_ERROR_CODE_1_INFO); + + adi_apollo_hal_regio_t *desc = (adi_apollo_hal_regio_t *) device->hal_info.active_regio; + + /* Read secure_boot_stage_x status - wait for state 'expected_value' */ + for (i = 0; i < retry_count; i++) { + + err = adi_apollo_hal_reg_poll_get(device, bootstage_reg_addr, &status, + retry_count * poll_delay_us, expected_value, 0xff); + ADI_APOLLO_ERROR_RETURN(err); + + if (status == expected_value || !desc->poll_read_returns_val) { + err = API_CMS_ERROR_OK; + break; + } + + // Wait 'poll_delay_us' before next poll read + err = adi_apollo_hal_delay_us(device, poll_delay_us); + ADI_APOLLO_ERROR_RETURN(err); + } + + err = adi_apollo_hal_bf_get(device, error_reg_addr, error_bf_info, &error, 1); + ADI_APOLLO_ERROR_RETURN(err); + + ADI_APOLLO_LOG_MSG_VAR( "SECURE_BOOT_STAGE_%d CHECK: %s.", stage, (status == expected_value) ? "Passed" : "*** FAILED ***"); + + if (status != expected_value) { + err = API_CMS_ERROR_ERROR; + } + + return err; +} + +static int32_t adi_apollo_arm_boot_status_clear(adi_apollo_device_t *device) +{ + int32_t err; + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_hal_bf_set(device, BF_RAM_BOOT_CORE1_STATUS, 0); + ADI_APOLLO_ERROR_RETURN(err) + + err = adi_apollo_hal_bf_set(device, BF_RAM_BOOT_CORE0_STATUS, 0); + ADI_APOLLO_ERROR_RETURN(err) + + return API_CMS_ERROR_OK; +} + +static int32_t adi_apollo_arm_core_reset(adi_apollo_device_t* device, uint8_t core) +{ + int32_t err; + uint32_t reg_addr = 0; + adi_apollo_hal_protocol_e protocol; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(core > ADI_APOLLO_CPU_ID_1); + + reg_addr = (core == ADI_APOLLO_CPU_ID_0) ? REG_ARM0_RESET_ADDR : REG_ARM1_RESET_ADDR; + + /* + Resetting ARM core w/ HSCI resets the uP_subsystem, which resets the HSCI configuration itself + resulting in further HSCI transactions to not go through hence switching to SPI during the reset + */ + adi_apollo_hal_active_protocol_get(device, &protocol); + adi_apollo_hal_active_protocol_set(device, ADI_APOLLO_HAL_PROTOCOL_SPI0); + + err = adi_apollo_hal_reg_set(device, reg_addr, 1); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_delay_us(device, 100000); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_reg_set(device, reg_addr, 0); + ADI_APOLLO_ERROR_RETURN(err); + + /* Restore active protocol */ + adi_apollo_hal_active_protocol_set(device, protocol); + + return API_CMS_ERROR_OK; +} + +static int32_t adi_apollo_arm_ram_lock_check(adi_apollo_device_t *device) +{ + int32_t err; + uint8_t ram_lock; + uint8_t retry_count = ADI_APOLLO_ARM_EC_TRANSFER_STATUS_READ_RETRY_COUNT; + uint32_t poll_delay_us = 10000; // 10ms + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + adi_apollo_hal_regio_t *desc = (adi_apollo_hal_regio_t *) device->hal_info.active_regio; + + /* EC RAM lock status - wait for FW to release the EC ram lock */ + do { + err = adi_apollo_hal_reg_poll_get(device, REG_ADDR_EXTRACT(BF_EC_RAM_LOCK_INFO), &ram_lock, + ADI_APOLLO_ARM_EC_TRANSFER_STATUS_READ_RETRY_COUNT * poll_delay_us, + 0x00, BF_EC_RAM_LOCK_MASK); + ADI_APOLLO_ERROR_RETURN(err); + + if (!(ram_lock & BF_EC_RAM_LOCK_MASK) || !desc->poll_read_returns_val) { + return API_CMS_ERROR_OK; + } + + // Delay 'poll_delay_us' to wait before reading status again + err = adi_apollo_hal_delay_us(device, poll_delay_us); + ADI_APOLLO_ERROR_RETURN(err); + + retry_count--; + } while (retry_count); + + return API_CMS_ERROR_EC_RAM_LOCK_ERROR; +} + + +static int32_t adi_apollo_arm_stack_ptr_boot_addr_set(adi_apollo_device_t *device, uint8_t core, adi_apollo_arm_binary_info_t *binary_info) +{ + int32_t err; + + uint8_t *fw_image_buf = binary_info->binary_ptr; + uint32_t reg_addr = 0; + uint32_t bf_info = 0; + uint32_t reg_val = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(binary_info); + ADI_APOLLO_NULL_POINTER_RETURN(binary_info->binary_ptr); + ADI_APOLLO_INVALID_PARAM_RETURN(binary_info->binary_sz_bytes < 1); + ADI_APOLLO_INVALID_PARAM_RETURN(core > ADI_APOLLO_CPU_ID_1); + + /* Extract Stack pointer and update */ + reg_val = ( (fw_image_buf[3] << 24) | (fw_image_buf[2] << 16) | (fw_image_buf[1] << 8) | fw_image_buf[0] ); + + reg_addr = (core == ADI_APOLLO_CPU_ID_0) ? REG_ADDR_EXTRACT(BF_ARM0_STACK_PTR_INFO) : REG_ADDR_EXTRACT(BF_ARM1_STACK_PTR_INFO); + bf_info = (core == ADI_APOLLO_CPU_ID_0) ? BF_INFO_EXTRACT(BF_ARM0_STACK_PTR_INFO) : BF_INFO_EXTRACT(BF_ARM1_STACK_PTR_INFO); + + err = adi_apollo_hal_bf_set(device, reg_addr, bf_info, reg_val); + ADI_APOLLO_ERROR_RETURN(err); + + ADI_APOLLO_LOG_MSG_VAR("Core%d Stack Pointer: \treg_addr: 0x%08X.\treg_val: 0x%08X.", core, reg_addr, reg_val); + + + /* Extract Boot address and update */ + reg_val = ( (fw_image_buf[7] << 24) | (fw_image_buf[6] << 16) | (fw_image_buf[5] << 8) | fw_image_buf[4] ); + + reg_addr = (core == ADI_APOLLO_CPU_ID_0) ? REG_ADDR_EXTRACT(BF_ARM0_BOOT_ADDR_INFO) : REG_ADDR_EXTRACT(BF_ARM1_BOOT_ADDR_INFO); + bf_info = (core == ADI_APOLLO_CPU_ID_0) ? BF_INFO_EXTRACT(BF_ARM0_BOOT_ADDR_INFO) : BF_INFO_EXTRACT(BF_ARM1_BOOT_ADDR_INFO); + + err = adi_apollo_hal_bf_set(device, reg_addr, bf_info, reg_val); + ADI_APOLLO_ERROR_RETURN(err); + + ADI_APOLLO_LOG_MSG_VAR("Core%d Boot Addr: \treg_addr: 0x%08X.\treg_val: 0x%08X.", core, reg_addr, reg_val); + + return API_CMS_ERROR_OK; +} + +static int32_t get_cpu_device_profile_start_address(adi_apollo_device_t *device, uint32_t *cpu_device_profile_addr) +{ + uint32_t address = ADI_APOLLO_FW_DEVICE_PROFILE_PTR; + int32_t err; + + err = adi_apollo_hal_reg32_get(device, address, cpu_device_profile_addr); + ADI_APOLLO_ERROR_RETURN(err); + ADI_APOLLO_LOG_MSG_VAR("Device Profile address: 0x%x\n", *cpu_device_profile_addr); + + return API_CMS_ERROR_OK; +} + +static int32_t device_feat_lockout_set(adi_apollo_device_t *device) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + + err = adi_apollo_hal_bf_get(device, BF_EC_RX_INFO, (uint8_t *)&device->dev_info.lockout_mask.rx_lockout_mask, sizeof(device->dev_info.lockout_mask.rx_lockout_mask)); + ADI_APOLLO_ERROR_RETURN(err); + ADI_APOLLO_LOG_VAR(ADI_CMS_LOG_API, "Device feat lockout mask (rx): 0x%08x", device->dev_info.lockout_mask.rx_lockout_mask); + + err = adi_apollo_hal_bf_get(device, BF_EC_TX_INFO, (uint8_t *)&device->dev_info.lockout_mask.tx_lockout_mask, sizeof(device->dev_info.lockout_mask.tx_lockout_mask)); + ADI_APOLLO_ERROR_RETURN(err); + ADI_APOLLO_LOG_VAR(ADI_CMS_LOG_API, "Device feat lockout mask (tx): 0x%08x", device->dev_info.lockout_mask.tx_lockout_mask); + + return API_CMS_ERROR_OK; +} + +/*! @} */ \ No newline at end of file diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_bmem.c b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_bmem.c new file mode 100644 index 00000000000000..9e6b07bf3b6084 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_bmem.c @@ -0,0 +1,394 @@ +/*! + * \brief APIs for BMEM + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_BMEM + * @{ + */ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_bmem.h" +#include "adi_apollo_private_bmem.h" +#include "adi_apollo_private_blk_sel_types.h" + +#include "adi_apollo_bf_rx_bmem.h" + +#include "adi_apollo_config.h" +#include "adi_apollo_hal.h" + +/*==================== L O C A L F U N C T I O N S ====================*/ + + +/*==================== P U B L I C A P I C O D E ====================*/ + +int32_t adi_apollo_bmem_hsdin_awg_config(adi_apollo_device_t *device, adi_apollo_blk_sel_t bmems, adi_apollo_bmem_awg_t *config) +{ + int32_t err; + + ADI_CMS_NULL_PTR_CHECK(device); + ADI_APOLLO_LOG_FUNC(); + ADI_CMS_NULL_PTR_CHECK(config); + ADI_APOLLO_BMEM_BLK_SEL_MASK(bmems); + + + err = adi_apollo_private_bmem_awg_config(device, ADI_APOLLO_BMEM_HSDIN, bmems, config); + ADI_CMS_ERROR_RETURN(err); + + return err; +} + +int32_t adi_apollo_bmem_hsdin_awg_start(adi_apollo_device_t *device, adi_apollo_blk_sel_t bmems) +{ + int32_t err; + + ADI_CMS_NULL_PTR_CHECK(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_BMEM_BLK_SEL_MASK(bmems); + + err = adi_apollo_private_bmem_awg_start(device, ADI_APOLLO_BMEM_HSDIN, bmems); + ADI_CMS_ERROR_RETURN(err); + + return err; +} + +int32_t adi_apollo_bmem_hsdin_awg_stop(adi_apollo_device_t *device, adi_apollo_blk_sel_t bmems) +{ + int32_t err; + + ADI_CMS_NULL_PTR_CHECK(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_BMEM_BLK_SEL_MASK(bmems); + + err = adi_apollo_private_bmem_awg_stop(device, ADI_APOLLO_BMEM_HSDIN, bmems); + ADI_CMS_ERROR_RETURN(err); + + return err; +} + +int32_t adi_apollo_bmem_hsdin_awg_sram_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t bmems, uint32_t data[], uint32_t length) +{ + int32_t err; + + ADI_CMS_NULL_PTR_CHECK(device); + ADI_APOLLO_LOG_FUNC(); + ADI_CMS_NULL_PTR_CHECK(data); + ADI_CMS_INVALID_PARAM_CHECK(length > ADI_APOLLO_BMEM_HSDIN_MEM_SIZE_WORDS); + ADI_APOLLO_BMEM_BLK_SEL_MASK(bmems); + + err = adi_apollo_private_bmem_awg_sram_set(device, ADI_APOLLO_BMEM_HSDIN, bmems, data, length); + ADI_CMS_ERROR_RETURN(err); + + return err; +} + +int32_t adi_apollo_bmem_hsdin_awg_sample_write(adi_apollo_device_t *device, adi_apollo_blk_sel_t bmems, int16_t data16[], uint32_t data16_len) +{ + int32_t err; + + ADI_CMS_NULL_PTR_CHECK(device); + ADI_APOLLO_LOG_FUNC(); + ADI_CMS_NULL_PTR_CHECK(data16); + ADI_CMS_INVALID_PARAM_CHECK(data16_len/2 > ADI_APOLLO_BMEM_HSDIN_MEM_SIZE_WORDS); + ADI_APOLLO_BMEM_BLK_SEL_MASK(bmems); + + err = adi_apollo_private_bmem_awg_sample_write(device, ADI_APOLLO_BMEM_HSDIN, bmems, data16, data16_len); + ADI_CMS_ERROR_RETURN(err); + + return err; +} + +int32_t adi_apollo_bmem_hsdin_awg_sample_shared_write(adi_apollo_device_t *device, adi_apollo_blk_sel_t bmems, + int16_t data16_0[], int16_t data16_1[], uint32_t data16_len, + uint32_t scratch32[], uint32_t scratch32_len) +{ + int32_t err; + + ADI_CMS_NULL_PTR_CHECK(device); + ADI_APOLLO_LOG_FUNC(); + ADI_CMS_NULL_PTR_CHECK(data16_0); + ADI_CMS_NULL_PTR_CHECK(data16_1); + ADI_CMS_NULL_PTR_CHECK(scratch32); + ADI_CMS_INVALID_PARAM_CHECK(data16_len > (ADI_APOLLO_BMEM_HSDIN_MEM_SIZE_BYTES / (2 * sizeof(uint16_t)))); + ADI_CMS_INVALID_PARAM_CHECK(scratch32_len < data16_len); + ADI_APOLLO_BMEM_BLK_SEL_MASK(bmems); + + err = adi_apollo_private_bmem_awg_sample_shared_write(device, ADI_APOLLO_BMEM_HSDIN, bmems, data16_0, data16_1, data16_len, scratch32, scratch32_len); + ADI_CMS_ERROR_RETURN(err); + + return err; +} + +int32_t adi_apollo_bmem_hsdin_capture_get(adi_apollo_device_t *device, adi_apollo_blk_sel_t bmems, uint32_t data[], uint32_t length) +{ + int32_t err; + + ADI_CMS_NULL_PTR_CHECK(device); + ADI_APOLLO_LOG_FUNC(); + ADI_CMS_NULL_PTR_CHECK(data); + ADI_CMS_SINGLE_SELECT_CHECK(bmems); + ADI_APOLLO_BMEM_BLK_SEL_MASK(bmems); + + err = adi_apollo_private_bmem_capture_get(device, ADI_APOLLO_BMEM_HSDIN, bmems, data, length); + ADI_CMS_ERROR_RETURN(err); + + return err; +} + +int32_t adi_apollo_bmem_hsdin_capture_run(adi_apollo_device_t *device, adi_apollo_blk_sel_t bmems) +{ + int32_t err; + + ADI_CMS_NULL_PTR_CHECK(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_BMEM_BLK_SEL_MASK(bmems); + + err = adi_apollo_private_bmem_capture_run(device, ADI_APOLLO_BMEM_HSDIN, bmems); + ADI_CMS_ERROR_RETURN(err); + + return err; +} + +int32_t adi_apollo_bmem_hsdin_capture_config(adi_apollo_device_t *device, adi_apollo_blk_sel_t bmems, adi_apollo_bmem_capture_t *config) +{ + int32_t err; + + ADI_CMS_NULL_PTR_CHECK(device); + ADI_APOLLO_LOG_FUNC(); + ADI_CMS_NULL_PTR_CHECK(config); + ADI_CMS_INVALID_PARAM_CHECK(config->end_addr_cpt - config->st_addr_cpt >= ADI_APOLLO_BMEM_HSDIN_MEM_SIZE_WORDS); + ADI_APOLLO_BMEM_BLK_SEL_MASK(bmems); + + err = adi_apollo_private_bmem_capture_config(device, ADI_APOLLO_BMEM_HSDIN, bmems, config); + ADI_CMS_ERROR_RETURN(err); + + return err; +} + +int32_t adi_apollo_bmem_hsdin_delay_sample_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t bmems, uint16_t sample_delay) +{ + int32_t err; + + ADI_CMS_NULL_PTR_CHECK(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_BMEM_BLK_SEL_MASK(bmems); + + err = adi_apollo_private_bmem_delay_sample_set(device, ADI_APOLLO_BMEM_HSDIN, bmems, sample_delay); + ADI_CMS_ERROR_RETURN(err); + + return err; +} + +int32_t adi_apollo_bmem_hsdin_delay_hop_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t bmems, uint16_t sample_delay[], uint32_t sample_delay_length) +{ + int32_t err; + + ADI_CMS_NULL_PTR_CHECK(device); + ADI_APOLLO_LOG_FUNC(); + ADI_CMS_NULL_PTR_CHECK(sample_delay); + ADI_CMS_INVALID_PARAM_CHECK(sample_delay_length != ADI_APOLLO_BMEM_HOP_PROFILES); + ADI_APOLLO_BMEM_BLK_SEL_MASK(bmems); + + err = adi_apollo_private_bmem_delay_hop_set(device, ADI_APOLLO_BMEM_HSDIN, bmems, sample_delay, sample_delay_length); + ADI_CMS_ERROR_RETURN(err); + + return err; +} + +int32_t adi_apollo_bmem_hsdin_delay_sample_config(adi_apollo_device_t *device, adi_apollo_blk_sel_t bmems, adi_apollo_bmem_delay_sample_t *config) +{ + int32_t err; + + ADI_CMS_NULL_PTR_CHECK(device); + ADI_APOLLO_LOG_FUNC(); + ADI_CMS_NULL_PTR_CHECK(config); + ADI_APOLLO_BMEM_BLK_SEL_MASK(bmems); + + err = adi_apollo_private_bmem_delay_sample_config(device, ADI_APOLLO_BMEM_HSDIN, bmems, config); + ADI_CMS_ERROR_RETURN(err); + + return err; +} + +int32_t adi_apollo_bmem_hsdin_delay_hop_config(adi_apollo_device_t *device, adi_apollo_blk_sel_t bmems, adi_apollo_bmem_delay_hop_t *config) +{ + int32_t err; + + ADI_CMS_NULL_PTR_CHECK(device); + ADI_APOLLO_LOG_FUNC(); + ADI_CMS_NULL_PTR_CHECK(config); + ADI_APOLLO_BMEM_BLK_SEL_MASK(bmems); + + err = adi_apollo_private_bmem_delay_hop_config(device, ADI_APOLLO_BMEM_HSDIN, bmems, config); + ADI_CMS_ERROR_RETURN(err); + + return err; +} + +int32_t adi_apollo_bmem_hsdin_delay_start(adi_apollo_device_t *device, adi_apollo_blk_sel_t bmems) +{ + int32_t err; + + ADI_CMS_NULL_PTR_CHECK(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_BMEM_BLK_SEL_MASK(bmems); + + err = adi_apollo_private_bmem_delay_start(device, ADI_APOLLO_BMEM_HSDIN, bmems); + ADI_CMS_ERROR_RETURN(err); + + return err; +} + +int32_t adi_apollo_bmem_cddc_delay_sample_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t bmems, uint16_t sample_delay) +{ + int32_t err; + + ADI_CMS_NULL_PTR_CHECK(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_BMEM_BLK_SEL_MASK(bmems); + + err = adi_apollo_private_bmem_delay_sample_set(device, ADI_APOLLO_BMEM_CDDC, bmems, sample_delay); + ADI_CMS_ERROR_RETURN(err); + + return err; +} + +int32_t adi_apollo_bmem_cddc_delay_hop_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t bmems, uint16_t sample_delay[], uint32_t sample_delay_length) +{ + int32_t err; + + ADI_CMS_NULL_PTR_CHECK(device); + ADI_APOLLO_LOG_FUNC(); + ADI_CMS_NULL_PTR_CHECK(sample_delay); + ADI_CMS_INVALID_PARAM_CHECK(sample_delay_length != ADI_APOLLO_BMEM_HOP_PROFILES); + ADI_APOLLO_BMEM_BLK_SEL_MASK(bmems); + + err = adi_apollo_private_bmem_delay_hop_set(device, ADI_APOLLO_BMEM_CDDC, bmems, sample_delay, sample_delay_length); + ADI_CMS_ERROR_RETURN(err); + + return err; +} + +int32_t adi_apollo_bmem_cddc_delay_sample_config(adi_apollo_device_t *device, adi_apollo_blk_sel_t bmems, adi_apollo_bmem_delay_sample_t *config) +{ + int32_t err; + + ADI_CMS_NULL_PTR_CHECK(device); + ADI_APOLLO_LOG_FUNC(); + ADI_CMS_NULL_PTR_CHECK(config); + ADI_APOLLO_BMEM_BLK_SEL_MASK(bmems); + + err = adi_apollo_private_bmem_delay_sample_config(device, ADI_APOLLO_BMEM_CDDC, bmems, config); + ADI_CMS_ERROR_RETURN(err); + + return err; +} + +int32_t adi_apollo_bmem_cddc_delay_hop_config(adi_apollo_device_t *device, adi_apollo_blk_sel_t bmems, adi_apollo_bmem_delay_hop_t *config) +{ + int32_t err; + + ADI_CMS_NULL_PTR_CHECK(device); + ADI_APOLLO_LOG_FUNC(); + ADI_CMS_NULL_PTR_CHECK(config); + ADI_APOLLO_BMEM_BLK_SEL_MASK(bmems); + + err = adi_apollo_private_bmem_delay_hop_config(device, ADI_APOLLO_BMEM_CDDC, bmems, config); + ADI_CMS_ERROR_RETURN(err); + + return err; +} + +int32_t adi_apollo_bmem_cddc_delay_start(adi_apollo_device_t *device, adi_apollo_blk_sel_t bmems) +{ + int32_t err; + + ADI_CMS_NULL_PTR_CHECK(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_BMEM_BLK_SEL_MASK(bmems); + + err = adi_apollo_private_bmem_delay_start(device, ADI_APOLLO_BMEM_CDDC, bmems); + ADI_CMS_ERROR_RETURN(err); + + return err; +} + +int32_t adi_apollo_bmem_fddc_delay_sample_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t bmems, uint16_t sample_delay) +{ + int32_t err; + + ADI_CMS_NULL_PTR_CHECK(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_BMEM_BLK_SEL_MASK(bmems); + + err = adi_apollo_private_bmem_delay_sample_set(device, ADI_APOLLO_BMEM_FDDC, bmems, sample_delay); + ADI_CMS_ERROR_RETURN(err); + + return err; +} + +int32_t adi_apollo_bmem_fddc_delay_hop_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t bmems, uint16_t sample_delay[], uint32_t sample_delay_length) +{ + int32_t err; + + ADI_CMS_NULL_PTR_CHECK(device); + ADI_APOLLO_LOG_FUNC(); + ADI_CMS_NULL_PTR_CHECK(sample_delay); + ADI_CMS_INVALID_PARAM_CHECK(sample_delay_length != ADI_APOLLO_BMEM_HOP_PROFILES); + ADI_APOLLO_BMEM_BLK_SEL_MASK(bmems); + + err = adi_apollo_private_bmem_delay_hop_set(device, ADI_APOLLO_BMEM_FDDC, bmems, sample_delay, sample_delay_length); + ADI_CMS_ERROR_RETURN(err); + + return err; +} + +int32_t adi_apollo_bmem_fddc_delay_sample_config(adi_apollo_device_t *device, adi_apollo_blk_sel_t bmems, adi_apollo_bmem_delay_sample_t *config) +{ + int32_t err; + + ADI_CMS_NULL_PTR_CHECK(device); + ADI_APOLLO_LOG_FUNC(); + ADI_CMS_NULL_PTR_CHECK(config); + ADI_APOLLO_BMEM_BLK_SEL_MASK(bmems); + + err = adi_apollo_private_bmem_delay_sample_config(device, ADI_APOLLO_BMEM_FDDC, bmems, config); + ADI_CMS_ERROR_RETURN(err); + + return err; +} + +int32_t adi_apollo_bmem_fddc_delay_hop_config(adi_apollo_device_t *device, adi_apollo_blk_sel_t bmems, adi_apollo_bmem_delay_hop_t *config) +{ + int32_t err; + + ADI_CMS_NULL_PTR_CHECK(device); + ADI_APOLLO_LOG_FUNC(); + ADI_CMS_NULL_PTR_CHECK(config); + ADI_APOLLO_BMEM_BLK_SEL_MASK(bmems); + + err = adi_apollo_private_bmem_delay_hop_config(device, ADI_APOLLO_BMEM_FDDC, bmems, config); + ADI_CMS_ERROR_RETURN(err); + + return err; +} + +int32_t adi_apollo_bmem_fddc_delay_start(adi_apollo_device_t *device, adi_apollo_blk_sel_t bmems) +{ + int32_t err; + + ADI_CMS_NULL_PTR_CHECK(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_BMEM_BLK_SEL_MASK(bmems); + + err = adi_apollo_private_bmem_delay_start(device, ADI_APOLLO_BMEM_FDDC, bmems); + ADI_CMS_ERROR_RETURN(err); + + return err; +} +/*! @} */ \ No newline at end of file diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_cddc.c b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_cddc.c new file mode 100644 index 00000000000000..40dfad3ba0e0c4 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_cddc.c @@ -0,0 +1,340 @@ +/*! + * \brief Coarse DDC functional block API implementation + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_CDDC + * @{ + */ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_cddc.h" +#include "adi_apollo_cnco.h" +#include "adi_apollo_ddc_local.h" +#include "adi_apollo_nco_local.h" +#include "adi_apollo_duc_local.h" +#include "adi_apollo_pfilt_local.h" +#include "adi_apollo_private_blk_sel_types.h" +#include "adi_apollo_bf_rx_cddc.h" +#include "adi_apollo_bf_rx_fine_ddc.h" +#include "adi_apollo_bf_txrx_coarse_nco.h" +#include "adi_apollo_bf_txrx_fine_nco.h" +#include "adi_apollo_bf_txrx_pfilt_top.h" +#include "adi_apollo_bf_jtx_dformat.h" +#include "adi_apollo_bf_rx_misc.h" +#include "adi_apollo_bf_custom.h" +#include "adi_apollo_bf_rx_datin.h" + +#include "adi_apollo_config.h" +#include "adi_apollo_hal.h" +#include "adi_utils.h" + +/*==================== P U B L I C A P I C O D E ====================*/ + +int32_t adi_apollo_cddc_dcm_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t cddcs, adi_apollo_cddc_ratio_e dcm) +{ + int32_t err; + uint8_t i; + adi_apollo_blk_sel_t cddc; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_CDDC_BLK_SEL_MASK(cddcs); + + for(i = 0; i < ADI_APOLLO_CDDC_NUM; i ++) { + cddc = cddcs & (ADI_APOLLO_CDDC_A0 << i); + if (cddc > 0) { + regmap_base_addr = calc_rx_cddc_base(i); + + err = adi_apollo_hal_bf_set(device, BF_COARSE_DDC_DEC_SEL_INFO(regmap_base_addr), dcm); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_cddc_link_num_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t cddcs, uint8_t link_num) +{ + int32_t err; + uint8_t i; + adi_apollo_blk_sel_t cddc; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_CDDC_BLK_SEL_MASK(cddcs); + + for(i = 0; i < ADI_APOLLO_CDDC_NUM; i ++) { + cddc = cddcs & (ADI_APOLLO_CDDC_A0 << i); + if (cddc > 0) { + regmap_base_addr = calc_rx_cddc_base(i); + + err = adi_apollo_hal_bf_set(device, BF_LINK_NUM_RX_CDDC_INFO(regmap_base_addr), link_num); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_cddc_debug_clkoff_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t cddcs, uint8_t clkoff_n) +{ + int32_t err; + uint8_t i; + adi_apollo_blk_sel_t cddc; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_CDDC_BLK_SEL_MASK(cddcs); + + for(i = 0; i < ADI_APOLLO_CDDC_NUM; i ++) { + cddc = cddcs & (ADI_APOLLO_CDDC_A0 << i); + if (cddc > 0) { + regmap_base_addr = calc_rx_cddc_base(i); + + err = adi_apollo_hal_bf_set(device, BF_CDDC_CLK_EN_INFO(regmap_base_addr), clkoff_n); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_cddc_pgm(adi_apollo_device_t *device, adi_apollo_blk_sel_t cddcs, adi_apollo_cddc_pgm_t *config) +{ + int32_t err; + uint8_t i; + adi_apollo_blk_sel_t cddc; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(config); + ADI_APOLLO_CDDC_BLK_SEL_MASK(cddcs); + + for(i = 0; i < ADI_APOLLO_CDDC_NUM; i ++) { + cddc = cddcs & (ADI_APOLLO_CDDC_A0 << i); + if (cddc > 0) { + regmap_base_addr = calc_rx_cddc_base(i); + + err = adi_apollo_hal_bf_set(device, BF_COARSE_DDC_DEC_SEL_INFO(regmap_base_addr), config->dcm); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_LINK_NUM_RX_CDDC_INFO(regmap_base_addr), config->link_num); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_CDDC_CLK_EN_INFO(regmap_base_addr), config->debug_clkoff_n); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_FINE_BYPASS_INFO(regmap_base_addr), config->fine_bypass); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_HB1_DEL_RX_CDDC_INFO(regmap_base_addr), config->hb1_filt_dly_en); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_HB2_DEL_RX_CDDC_INFO(regmap_base_addr), config->hb2_filt_dly_en); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_TB1_DEL_INFO(regmap_base_addr), config->tb1_filt_dly); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_HB1_GAIN_EN_RX_CDDC_INFO(regmap_base_addr), config->hb1_gain_6db_en); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_TB1_GAIN_EN_INFO(regmap_base_addr), config->tb1_gain_6db_en); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_cddc_inspect(adi_apollo_device_t *device, adi_apollo_blk_sel_t cddc, adi_apollo_cddc_inspect_t *cddc_inspect) +{ + int32_t err; + uint8_t i; + uint32_t regmap_base_addr = 0; + adi_apollo_blk_sel_t cddc_x; + adi_apollo_cnco_inspect_t cnco_inspect = {{0}}; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(cddc_inspect); + ADI_APOLLO_INVALID_PARAM_RETURN(adi_api_utils_num_selected(cddc) != 1); + ADI_APOLLO_CDDC_BLK_SEL_MASK(cddc); + + // For 8t8r, regmap is shared for each split CDUC (A0/A2, A1/A3, ...) + cddc_x = ((cddc & 0xCC) >> 2) | (cddc & 0x33); + + for(i = 0; i < ADI_APOLLO_CDDC_NUM; i ++) { + if ((cddc & (ADI_APOLLO_CDDC_A0 << i)) > 0) { + regmap_base_addr = calc_rx_cddc_base(i); + + // CNCO A0-A1, B0-B1 + err = adi_apollo_cnco_inspect(device, ADI_APOLLO_RX, cddc_x, &cnco_inspect); + ADI_APOLLO_ERROR_RETURN(err); + cddc_inspect->dp_cfg.nco[0] = cnco_inspect.dp_cfg; + + // CNCO A2-A3, B2-B3 + if (device->dev_info.is_8t8r) { + err = adi_apollo_cnco_inspect(device, ADI_APOLLO_RX, (cddc_x << 2), &cnco_inspect); + ADI_APOLLO_ERROR_RETURN(err); + cddc_inspect->dp_cfg.nco[1] = cnco_inspect.dp_cfg; + } + + err = adi_apollo_hal_bf_get(device, BF_COARSE_DDC_DEC_SEL_INFO(regmap_base_addr), (uint8_t*) &(cddc_inspect->dp_cfg.drc_ratio), sizeof(cddc_inspect->dp_cfg.drc_ratio)); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_LINK_NUM_RX_CDDC_INFO(regmap_base_addr), &(cddc_inspect->dp_cfg.link_num), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_FINE_BYPASS_INFO(regmap_base_addr), (uint8_t*) &(cddc_inspect->dp_cfg.fine_bypass), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_HB1_DEL_RX_CDDC_INFO(regmap_base_addr), (uint8_t*) &(cddc_inspect->dp_cfg.hb1_filt_dly_en), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_HB2_DEL_RX_CDDC_INFO(regmap_base_addr), (uint8_t*) &(cddc_inspect->dp_cfg.hb2_filt_dly_en), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_TB1_DEL_INFO(regmap_base_addr), (uint8_t *)&(cddc_inspect->dp_cfg.tb1_filt_dly_cycles), sizeof(cddc_inspect->dp_cfg.tb1_filt_dly_cycles)); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_HB1_GAIN_EN_RX_CDDC_INFO(regmap_base_addr), (uint8_t*) &(cddc_inspect->dp_cfg.hb1_gain_6db_en), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_TB1_GAIN_EN_INFO(regmap_base_addr), (uint8_t*) &(cddc_inspect->dp_cfg.tb1_gain_6db_en), 1); + ADI_APOLLO_ERROR_RETURN(err); + + /* Only one inspect per call */ + break; + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_cddc_fine_bypass_enable(adi_apollo_device_t *device, adi_apollo_blk_sel_t cddcs, uint8_t bypass_enable) +{ + int32_t err; + uint8_t i; + adi_apollo_blk_sel_t cddc; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_CDDC_BLK_SEL_MASK(cddcs); + + for(i = 0; i < ADI_APOLLO_CDDC_NUM; i ++) { + cddc = cddcs & (ADI_APOLLO_CDDC_A0 << i); + if (cddc > 0) { + regmap_base_addr = calc_rx_cddc_base(i); + + err = adi_apollo_hal_bf_set(device, BF_FINE_BYPASS_INFO(regmap_base_addr), bypass_enable); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_cddc_dcm_bf_to_val(adi_apollo_device_t *device, adi_apollo_cddc_ratio_e bf_enum, uint32_t *val) +{ + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(val); + + switch (bf_enum) { + case ADI_APOLLO_CDDC_RATIO_1: + case ADI_APOLLO_CDDC_RATIO_2: + case ADI_APOLLO_CDDC_RATIO_3: + case ADI_APOLLO_CDDC_RATIO_4: + *val = bf_enum + 1; + break; + + case ADI_APOLLO_CDDC_RATIO_6: + *val = 6; + break; + + case ADI_APOLLO_CDDC_RATIO_12: + *val = 12; + break; + + default: + ADI_APOLLO_LOG_ERR("Invalid adi_apollo_cddc_ratio_e enum"); + return API_CMS_ERROR_INVALID_PARAM; + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_cddc_gain_enable_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t cddcs, uint16_t filt_sel, uint8_t enable) +{ + int32_t err; + uint16_t i; + adi_apollo_blk_sel_t cddc; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_CDDC_BLK_SEL_MASK(cddcs); + + for (i = 0; i < ADI_APOLLO_CDDC_NUM; i++) { + cddc = cddcs & (ADI_APOLLO_CDDC_A0 << i); + if (cddc > 0) { + regmap_base_addr = calc_rx_cddc_base(i); + + if ((filt_sel & ADI_APOLLO_CDDC_GAIN_HB1) != 0) { + err = adi_apollo_hal_bf_set(device, BF_HB1_GAIN_EN_RX_CDDC_INFO(regmap_base_addr), (enable != 0) ? 1 : 0); + } + if ((filt_sel & ADI_APOLLO_CDDC_GAIN_TB1) != 0) { + err = adi_apollo_hal_bf_set(device, BF_TB1_GAIN_EN_INFO(regmap_base_addr), (enable != 0) ? 1 : 0); + } + + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_cddc_gain_enable_get(adi_apollo_device_t *device, adi_apollo_blk_sel_t cddcs, uint16_t filt_sel, uint8_t *enable) +{ + int32_t err; + uint16_t i; + adi_apollo_blk_sel_t cddc; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(enable); + ADI_APOLLO_INVALID_PARAM_RETURN(adi_api_utils_num_selected(cddcs) != 1); + ADI_APOLLO_INVALID_PARAM_RETURN(adi_api_utils_num_selected(filt_sel) != 1); + ADI_APOLLO_CDDC_BLK_SEL_MASK(cddcs); + + for (i = 0; i < ADI_APOLLO_CDDC_NUM; i++) { + cddc = cddcs & (ADI_APOLLO_CDDC_A0 << i); + if (cddc > 0) { + regmap_base_addr = calc_rx_cddc_base(i); + + if ((filt_sel & ADI_APOLLO_CDDC_GAIN_HB1) != 0) { + err = adi_apollo_hal_bf_get(device, BF_HB1_GAIN_EN_RX_CDDC_INFO(regmap_base_addr), enable, sizeof(*enable)); + } + if ((filt_sel & ADI_APOLLO_CDDC_GAIN_TB1) != 0) { + err = adi_apollo_hal_bf_get(device, BF_TB1_GAIN_EN_INFO(regmap_base_addr), enable, sizeof(*enable)); + } + ADI_APOLLO_ERROR_RETURN(err); + + break; + } + } + + return API_CMS_ERROR_OK; +} + + + +uint32_t calc_rx_cddc_base(int32_t cddc_index) +{ + static uint32_t rx_cddc_regmap[ADI_APOLLO_CDDC_NUM] = { + RX_CDDC_RX_SLICE_0_RX_DIGITAL0, RX_CDDC_RX_SLICE_1_RX_DIGITAL0, + RX_CDDC_RX_SLICE_0_RX_DIGITAL0, RX_CDDC_RX_SLICE_1_RX_DIGITAL0, + RX_CDDC_RX_SLICE_0_RX_DIGITAL1, RX_CDDC_RX_SLICE_1_RX_DIGITAL1, + RX_CDDC_RX_SLICE_0_RX_DIGITAL1, RX_CDDC_RX_SLICE_1_RX_DIGITAL1, + }; + return rx_cddc_regmap[cddc_index]; +} +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_cduc.c b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_cduc.c new file mode 100644 index 00000000000000..1c7f84e9cf13a6 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_cduc.c @@ -0,0 +1,265 @@ +/*! + * \brief Coarse DUC functional block API implementation + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_CDUC + * @{ + */ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_cduc.h" +#include "adi_apollo_cnco.h" +#include "adi_apollo_duc_local.h" +#include "adi_apollo_txmisc_local.h" +#include "adi_apollo_private_blk_sel_types.h" + +#include "adi_apollo_bf_tx_cduc.h" +#include "adi_apollo_bf_tx_misc.h" + +#include "adi_apollo_config.h" +#include "adi_apollo_hal.h" +#include "adi_utils.h" + +static const uint8_t cduc_sel_to_reg_bit[4] = { 0x01, 0x04, 0x10, 0x40 }; + +/*==================== P U B L I C A P I C O D E ====================*/ + +int32_t adi_apollo_cduc_interp_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t cducs, uint8_t interp) +{ + int32_t err; + uint16_t i; + adi_apollo_blk_sel_t cduc; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_CDUC_BLK_SEL_MASK(cducs); + + for (i = 0; i < ADI_APOLLO_CDUC_NUM; i ++) { + cduc = cducs & (ADI_APOLLO_CDUC_A0 << i); + + if (cduc > 0) { + regmap_base_addr = calc_tx_cduc_base(i); + + err = adi_apollo_hal_bf_set(device, BF_POST_INTERP_INFO(regmap_base_addr), interp); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_cduc_pgm(adi_apollo_device_t *device, adi_apollo_blk_sel_t cducs, const adi_apollo_cduc_pgm_t *config) +{ + int32_t err; + uint16_t i; + adi_apollo_blk_sel_t cduc; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(config); + ADI_APOLLO_CDUC_BLK_SEL_MASK(cducs); + + for (i = 0; i < ADI_APOLLO_CDUC_NUM; i ++) { + cduc = cducs & (ADI_APOLLO_CDUC_A0 << i); + + if (cduc > 0) { + regmap_base_addr = calc_tx_cduc_base(i); + + err = adi_apollo_hal_bf_set(device, BF_POST_INTERP_INFO(regmap_base_addr), config->interp); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_TEST_MUX_INFO(regmap_base_addr), config->test_mux); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_CHB1_INT_TIME_DLY_INFO(regmap_base_addr), config->chb1_int_time_dly); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_CHB2_INT_TIME_DLY_INFO(regmap_base_addr), config->chb2_int_time_dly); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_CHB3_INT_TIME_DLY_INFO(regmap_base_addr), config->chb3_int_time_dly); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_CTB1_INT_TIME_DLY_INFO(regmap_base_addr), config->ctb1_int_time_dly); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + /* CDUC SPI enable configuration */ + err = adi_apollo_cduc_enable_set(device, cducs, config->cduc_spien_en, config->cduc_spi_en); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_cduc_enable_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t cducs, uint8_t cduc_spien_en, uint8_t cduc_spi_en) +{ + int32_t err; + uint32_t regmap_base_addr = 0; + uint8_t side_index; + uint8_t bf_cduc_en = 0; + uint8_t bits2change[2] = { + (cducs >> 0) & ((1 << ADI_APOLLO_CDUC_PER_SIDE_NUM) - 1), + (cducs >> ADI_APOLLO_CDUC_PER_SIDE_NUM) & ((1 << ADI_APOLLO_CDUC_PER_SIDE_NUM) - 1) + }; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_CDUC_BLK_SEL_MASK(cducs); + + for (side_index = 0; side_index < ADI_APOLLO_NUM_SIDES; side_index++) { + if (bits2change[side_index]) { + regmap_base_addr = calc_tx_misc_base(side_index); // One tx_misc regmap per side + + err = adi_apollo_hal_bf_set(device, BF_CDUC_SPI_EN_INFO(regmap_base_addr), cduc_spien_en ? 1 : 0); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_get(device, BF_CDUC_EN_INFO(regmap_base_addr), &bf_cduc_en, sizeof(bf_cduc_en)); + ADI_APOLLO_ERROR_RETURN(err); + + bf_cduc_en &= ~bits2change[side_index]; + bf_cduc_en |= (cduc_spi_en ? bits2change[side_index] : 0); + err = adi_apollo_hal_bf_set(device, BF_CDUC_EN_INFO(regmap_base_addr), bf_cduc_en); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_cduc_inspect(adi_apollo_device_t *device, adi_apollo_blk_sel_t cduc, adi_apollo_cduc_inspect_t *cduc_inspect) +{ + int32_t err; + uint8_t i; + uint8_t duc_en_cfg_reg; + uint32_t regmap_base_addr = 0; + adi_apollo_blk_sel_t cduc_x; + adi_apollo_cnco_inspect_t cnco_inspect = {{0}}; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(cduc_inspect); + ADI_APOLLO_INVALID_PARAM_RETURN(adi_api_utils_num_selected(cduc)!= 1); + ADI_APOLLO_CDUC_BLK_SEL_MASK(cduc); + + // For 8t8r, regmap is shared for each split CDUC (A0/A2, A1/A3, ...) + cduc_x = ((cduc & 0xCC) >> 2) | (cduc & 0x33); + + for(i = 0; i < ADI_APOLLO_CDUC_NUM; i ++) { + if ((cduc & (ADI_APOLLO_CDUC_A0 << i)) > 0) { + regmap_base_addr = calc_tx_cduc_base(i); + + // CNCO A0-A1, B0-B1 + err = adi_apollo_cnco_inspect(device, ADI_APOLLO_TX, cduc_x, &cnco_inspect); + ADI_APOLLO_ERROR_RETURN(err); + cduc_inspect->dp_cfg.nco[0] = cnco_inspect.dp_cfg; + + // CNCO A2-A3, B2-B3 + if (device->dev_info.is_8t8r) { + err = adi_apollo_cnco_inspect(device, ADI_APOLLO_TX, (cduc_x << 2), &cnco_inspect); + ADI_APOLLO_ERROR_RETURN(err); + cduc_inspect->dp_cfg.nco[1] = cnco_inspect.dp_cfg; + } + + err = adi_apollo_hal_bf_get(device, BF_POST_INTERP_INFO(regmap_base_addr), (uint8_t *) &(cduc_inspect->dp_cfg.drc_ratio), sizeof(cduc_inspect->dp_cfg.drc_ratio)); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_get(device, BF_TEST_MUX_INFO(regmap_base_addr), &(cduc_inspect->test_mux), 1); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_get(device, BF_CHB1_INT_TIME_DLY_INFO(regmap_base_addr), &(cduc_inspect->chb1_int_time_dly), 1); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_get(device, BF_CHB2_INT_TIME_DLY_INFO(regmap_base_addr), &(cduc_inspect->chb2_int_time_dly), 1); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_get(device, BF_CHB3_INT_TIME_DLY_INFO(regmap_base_addr), &(cduc_inspect->chb3_int_time_dly), 1); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_get(device, BF_CTB1_INT_TIME_DLY_INFO(regmap_base_addr), &(cduc_inspect->ctb1_int_time_dly), 1); + ADI_APOLLO_ERROR_RETURN(err); + + /* CDUC SPI enable */ + regmap_base_addr = calc_tx_misc_base(i / ADI_APOLLO_CDUC_PER_SIDE_NUM); // Regmap base address for side + + err = adi_apollo_hal_bf_get(device, BF_CDUC_SPI_EN_INFO(regmap_base_addr), &(cduc_inspect->cduc_spien_en), sizeof(cduc_inspect->cduc_spien_en)); // spi control enable for side + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_reg_get(device, REG_DUC_EN_CFG_ADDR(regmap_base_addr), &duc_en_cfg_reg); + ADI_APOLLO_ERROR_RETURN(err); + cduc_inspect->cduc_spi_en = duc_en_cfg_reg & cduc_sel_to_reg_bit[i % ADI_APOLLO_CDUC_PER_SIDE_NUM]; + + break; // Only one block inspect per call + } + + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_cduc_interp_bf_to_val(adi_apollo_device_t* device, adi_apollo_cduc_ratio_e bf_enum, uint32_t* val) +{ + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(val); + + switch (bf_enum) { + case ADI_APOLLO_CDUC_RATIO_1: + case ADI_APOLLO_CDUC_RATIO_2: + case ADI_APOLLO_CDUC_RATIO_3: + case ADI_APOLLO_CDUC_RATIO_4: + case ADI_APOLLO_CDUC_RATIO_6: + case ADI_APOLLO_CDUC_RATIO_8: + case ADI_APOLLO_CDUC_RATIO_12: + *val = bf_enum; + break; + + default: + ADI_APOLLO_LOG_ERR("Invalid adi_apollo_cduc_ratio_e enum"); + return API_CMS_ERROR_INVALID_PARAM; + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_cduc_irq_enable_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t cducs, uint8_t enable) +{ + int32_t err; + uint32_t regmap_base_addr = 0; + uint8_t i; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_CDUC_BLK_SEL_MASK(cducs); + + for(i = 0; i < ADI_APOLLO_CDUC_NUM; i ++) { + if ((cducs & (ADI_APOLLO_CDUC_A0 << i)) > 0) { + regmap_base_addr = calc_tx_cduc_base(i); + + err = adi_apollo_hal_bf_set(device, BF_CDUC_IRQ_EN0_INFO(regmap_base_addr), enable ? 0x3FF : 0); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +uint32_t calc_tx_cduc_base(int32_t idx) +{ + static const uint32_t tx_cduc_regmap[ADI_APOLLO_CDUC_NUM] = { + TX_CDUC_TX_SLICE_0_TX_DIGITAL0, TX_CDUC_TX_SLICE_1_TX_DIGITAL0, TX_CDUC_TX_SLICE_0_TX_DIGITAL0, TX_CDUC_TX_SLICE_1_TX_DIGITAL0, + TX_CDUC_TX_SLICE_0_TX_DIGITAL1, TX_CDUC_TX_SLICE_1_TX_DIGITAL1, TX_CDUC_TX_SLICE_0_TX_DIGITAL1, TX_CDUC_TX_SLICE_1_TX_DIGITAL1, + }; + + return tx_cduc_regmap[idx]; +} + +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_cfg.c b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_cfg.c new file mode 100644 index 00000000000000..1f3ebee681edcb --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_cfg.c @@ -0,0 +1,780 @@ +/*! + * \brief APIs for SYS TOP + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_CFG + * @{ + */ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_config.h" +#include "adi_apollo_hal.h" +#include "adi_apollo_ddc_local.h" +#include "adi_apollo_cfg.h" +#include "adi_apollo_rx.h" +#include "adi_apollo_tx.h" +#include "adi_apollo_gpio.h" +#include "adi_apollo_clk_mcs.h" +#include "adi_apollo_dac.h" +#include "adi_apollo_sysclk_cond.h" +#include "adi_utils.h" + +#define ADI_APOLLO_CONV_IDX_CONV(is_8t8r, idx, per_side) (is_8t8r) ? (idx) : (((idx) / (per_side/2)) + ((idx) % (per_side))) + +static uint32_t calc_adc_cal_cfg_reg(int32_t idx); +static uint32_t calc_dac_cal_cfg_reg(int32_t idx); +static int32_t cal_data_size_addr_get(adi_apollo_device_t *device, uint8_t idx, + uint32_t cal_obj_siz, uint32_t cal_obj_ofst, uint32_t obj_ptr, uint32_t siz_ptr, + uint32_t *size, uint32_t *address); +static int32_t cal_data_len_get(adi_apollo_device_t* device, + uint32_t cal_obj_ofst, uint32_t siz_ptr, + uint32_t *size); +static uint8_t is_init_cal_cfg_valid(adi_apollo_init_cal_cfg_e init_cal_cfg); +static uint8_t is_clk_cond_cal_cfg_valid(adi_apollo_sysclock_cond_cfg_e cc_cal_cfg); + +/*==================== P U B L I C A P I C O D E ====================*/ + +int32_t adi_apollo_cfg_data_path(adi_apollo_device_t *device, adi_apollo_top_t *config) +{ + int32_t err; + uint8_t i; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(config); + ADI_APOLLO_LOG_FUNC(); + + /* RX path config */ + for(i = 0; i < ADI_APOLLO_NUM_SIDES; i++) { + err = adi_apollo_rx_configure(device, i, &(config->rx_path[i]), &(config->jtx[i])); + ADI_APOLLO_ERROR_RETURN(err); + } + + /* Enable Rx data FIFOs */ + err = adi_apollo_clk_mcs_rx_data_fifo_enable(device, config->adc_enable, 1); + ADI_APOLLO_ERROR_RETURN(err); + + /* TX path config*/ + for(i = 0; i < ADI_APOLLO_NUM_SIDES; i++) { + err = adi_apollo_tx_configure(device, i, &(config->tx_path[i]), &(config->jrx[i])); + ADI_APOLLO_ERROR_RETURN(err); + } + + /* Enable DAC Scramblers */ + err = adi_apollo_dac_scrambler_enable_set(device, config->dac_enable, 1); + ADI_APOLLO_ERROR_RETURN(err); + + /* Enable DACs */ + err = adi_apollo_dac_data_enable(device, config->dac_enable, 1); + ADI_APOLLO_ERROR_RETURN(err); + + /* Enable Tx data FIFOs */ + err = adi_apollo_clk_mcs_tx_data_fifo_enable(device, config->dac_enable, 1); + ADI_APOLLO_ERROR_RETURN(err); + + if (config->jtx[0].common_link_cfg.ver == ADI_APOLLO_JESD_204B) { + err = adi_apollo_gpio_jesd_204b_configure(device); + ADI_APOLLO_ERROR_RETURN(err); + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_cfg_adc_init_cal_cfg_set(adi_apollo_device_t *device, const uint16_t adcs, adi_apollo_init_cal_cfg_e init_cal_cfg) +{ + int32_t err; + uint8_t i; + uint16_t adc; + uint32_t init_cal_cfg_reg; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(!is_init_cal_cfg_valid(init_cal_cfg)); + + for(i = 0; i < ADI_APOLLO_ADC_NUM; i ++) { + adc = adcs & (ADI_APOLLO_ADC_A0 << i); + if (adc > 0) { + init_cal_cfg_reg = calc_adc_cal_cfg_reg(i); + + err = adi_apollo_hal_bf_set(device, ADI_APOLLO_WARMBOOT_CFG_BASE_ADDR + init_cal_cfg_reg, (i % 2 == 0) ? 0x00000400 : 0x00000404, init_cal_cfg); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_cfg_clk_cond_cal_cfg_set(adi_apollo_device_t *device, adi_apollo_sysclock_cond_cfg_e cc_cal_cfg) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(!is_clk_cond_cal_cfg_valid(cc_cal_cfg)); + err = adi_apollo_hal_bf_set(device, ADI_APOLLO_WARMBOOT_CFG_BASE_ADDR + ADI_APOLLO_WARMBOOT_CFG_SYSCLK_CONDITIONING, 0x00000400, cc_cal_cfg); + ADI_APOLLO_ERROR_RETURN(err); + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_cfg_dac_init_cal_cfg_set(adi_apollo_device_t *device, const uint16_t dacs, adi_apollo_init_cal_cfg_e init_cal_cfg) +{ + int32_t err; + uint8_t i; + uint16_t dac; + uint32_t init_cal_cfg_reg; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + for(i = 0; i < ADI_APOLLO_DAC_NUM; i ++) { + dac = dacs & (ADI_APOLLO_DAC_A0 << i); + if (dac > 0) { + init_cal_cfg_reg = calc_dac_cal_cfg_reg(i); + + err = adi_apollo_hal_bf_set(device, ADI_APOLLO_WARMBOOT_CFG_BASE_ADDR + init_cal_cfg_reg, (i % 2 == 0) ? 0x00000400 : 0x00000404, init_cal_cfg); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_cfg_serdes_rx_init_cal_cfg_set(adi_apollo_device_t *device, const uint16_t serdes, adi_apollo_init_cal_cfg_e init_cal_cfg) +{ + int32_t err; + uint8_t i; + uint16_t s; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + for(i = 0; i < ADI_APOLLO_NUM_JRX_SERDES_12PACKS; i ++) { + s = serdes & (ADI_APOLLO_TXRX_SERDES_12PACK_A << i); + if (s > 0) { + err = adi_apollo_hal_bf_set(device, ADI_APOLLO_WARMBOOT_CFG_BASE_ADDR + ADI_APOLLO_WARMBOOT_CFG_SERDES_RX_1_0, (i % 2 == 0) ? 0x00000400 : 0x00000404, init_cal_cfg); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_cfg_serdes_tx_init_cal_cfg_set(adi_apollo_device_t *device, const uint16_t serdes, adi_apollo_init_cal_cfg_e init_cal_cfg) +{ + int32_t err; + uint8_t i; + uint16_t s; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + for(i = 0; i < ADI_APOLLO_NUM_JTX_SERDES_12PACKS; i ++) { + s = serdes & (ADI_APOLLO_TXRX_SERDES_12PACK_A << i); + if (s > 0) { + err = adi_apollo_hal_bf_set(device, ADI_APOLLO_WARMBOOT_CFG_BASE_ADDR + ADI_APOLLO_WARMBOOT_CFG_SERDES_TX_1_0, (i % 2 == 0) ? 0x00000400 : 0x00000404, init_cal_cfg); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_cfg_adc_cal_data_set(adi_apollo_device_t *device, const uint16_t adcs, uint8_t mode, uint8_t cal_data[], uint32_t len) +{ + int32_t err; + uint8_t i; + uint16_t adc; + uint32_t size_bytes; + uint32_t address; + uint8_t cal_data_offset; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(cal_data); + ADI_APOLLO_INVALID_PARAM_RETURN(mode > 1); + + cal_data_offset = (mode == ADI_APOLLO_ADC_CAL_SEQUENTIAL_MODE) ? ADI_APOLLO_ADC_CAL_STRUCT_SEQ_DATA_OFFSET : ADI_APOLLO_ADC_CAL_STRUCT_RAND_DATA_OFFSET; + + for(i = 0; i < ADI_APOLLO_ADC_NUM; i++) { + adc = adcs & (ADI_APOLLO_ADC_A0 << i); + if (adc > 0) { + /* Get the cal data size and address location */ + err = cal_data_size_addr_get(device, + ADI_APOLLO_CONV_IDX_CONV(device->dev_info.is_8t8r, i, ADI_APOLLO_ADC_PER_SIDE_NUM), + ADI_APOLLO_ADC_CAL_STRUCT_SIZE, cal_data_offset, + ADI_APOLLO_CPU_1_FW_ADC_RX_OBJ_PTR, ADI_APOLLO_CPU_1_FW_ADC_RX_SIZE_PTR, + &size_bytes, &address); + ADI_APOLLO_ERROR_RETURN(err); + + if (size_bytes != len - 4) { /* Assumes incoming data has 4-byte crc */ + return API_CMS_ERROR_ERROR; /* cal_data size fw mismatch */ + } + + /* Stream cal data to core */ + err = adi_apollo_hal_stream_reg_set(device, address, cal_data, len, 0); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_cfg_dac_cal_data_set(adi_apollo_device_t *device, const uint16_t dacs, uint8_t cal_data[], uint32_t len) +{ + int32_t err; + uint8_t i; + uint16_t dac; + uint32_t size_bytes; + uint32_t address; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(cal_data); + + for(i = 0; i < ADI_APOLLO_DAC_NUM; i ++) { + dac = dacs & (ADI_APOLLO_DAC_A0 << i); + if (dac > 0) { + /* Get the cal data size and address location */ + err = cal_data_size_addr_get(device, i, + ADI_APOLLO_DAC_CAL_OBJ_SIZE, ADI_APOLLO_DAC_CAL_OBJ_OFFSET, + ADI_APOLLO_CPU_1_FW_DAC_TX_OBJ_PTR, ADI_APOLLO_CPU_1_FW_DAC_TX_SIZE_PTR, + &size_bytes, &address); + ADI_APOLLO_ERROR_RETURN(err); + + if (size_bytes != len - 4) { /* Assumes incoming data has 4-byte crc */ + return API_CMS_ERROR_ERROR; /* cal_data size fw mismatch */ + } + + /* Stream cal data to core */ + err = adi_apollo_hal_stream_reg_set(device, address, cal_data, len, 0); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_cfg_serdes_rx_cal_data_set(adi_apollo_device_t *device, const uint16_t serdes, uint8_t cal_data[], uint32_t len) +{ + int32_t err; + uint8_t i; + uint16_t s; + uint32_t size_bytes; + uint32_t address; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(cal_data); + + for(i = 0; i < ADI_APOLLO_NUM_JTX_SERDES_12PACKS; i ++) { + s = serdes & (ADI_APOLLO_TXRX_SERDES_12PACK_A << i); + if (s > 0) { + /* Get the cal data size and address location */ + err = cal_data_size_addr_get(device, i, + ADI_APOLLO_SERDES_RX_CAL_OBJ_SIZE, ADI_APOLLO_SERDES_RX_CAL_OBJ_OFFSET, + ADI_APOLLO_CPU_0_FW_SERDES_RX_OBJ_PTR, ADI_APOLLO_CPU_0_FW_SERDES_RX_SIZE_PTR, + &size_bytes, &address); + + ADI_APOLLO_ERROR_RETURN(err); + + if (size_bytes != len - 4) { /* Assumes incoming data has 4-byte crc */ + return API_CMS_ERROR_ERROR; /* cal_data size fw mismatch */ + } + + /* Stream cal data to core */ + err = adi_apollo_hal_stream_reg_set(device, address, cal_data, len, 0); + ADI_APOLLO_ERROR_RETURN(err); + + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_cfg_serdes_tx_cal_data_set(adi_apollo_device_t *device, const uint16_t serdes, uint8_t cal_data[], uint32_t len) +{ + int32_t err; + uint8_t i; + uint16_t s; + uint32_t size_bytes; + uint32_t address; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(cal_data); + + for(i = 0; i < ADI_APOLLO_NUM_JTX_SERDES_12PACKS; i ++) { + s = serdes & (ADI_APOLLO_TXRX_SERDES_12PACK_A << i); + if (s > 0) { + /* Get the cal data size and address location */ + err = cal_data_size_addr_get(device, i, + ADI_APOLLO_SERDES_TX_CAL_OBJ_SIZE, ADI_APOLLO_SERDES_TX_CAL_OBJ_OFFSET, + ADI_APOLLO_CPU_1_FW_SERDES_TX_OBJ_PTR, ADI_APOLLO_CPU_1_FW_SERDES_TX_SIZE_PTR, + &size_bytes, &address); + ADI_APOLLO_ERROR_RETURN(err); + + if (size_bytes != len - 4) { /* Assumes incoming data has 4-byte crc */ + return API_CMS_ERROR_ERROR; /* cal_data size fw mismatch */ + } + + /* Stream cal data to core */ + err = adi_apollo_hal_stream_reg_set(device, address, cal_data, len, 0); + ADI_APOLLO_ERROR_RETURN(err); + + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_cfg_clk_cond_cal_data_set(adi_apollo_device_t *device, const uint16_t sides, uint8_t cal_data[], uint32_t len) +{ + int32_t err; + uint8_t i; + uint16_t side; + uint32_t size_bytes; + uint32_t address_ptr; + uint32_t address; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(cal_data); + ADI_APOLLO_INVALID_PARAM_RETURN(adi_api_utils_num_selected(sides) != 1); + + for (i = 0; i < ADI_APOLLO_NUM_SIDES; i++) { + side = sides & (ADI_APOLLO_SIDE_A << i); + if (side > 0) { + /* Get the cal data size and address location */ + err = adi_apollo_cfg_clk_cond_cal_data_len_get(device, &size_bytes); + ADI_APOLLO_ERROR_RETURN(err); + + if (size_bytes != len) { + return API_CMS_ERROR_INVALID_PARAM; + } + + address_ptr = (side == ADI_APOLLO_SIDE_A) ? APOLLO_CPU_1_FW_CLK_COND_0_CALDATA_PTR : APOLLO_CPU_1_FW_CLK_COND_1_CALDATA_PTR; + err = adi_apollo_hal_reg32_get(device, address_ptr, &address); + ADI_APOLLO_ERROR_RETURN(err); + + /* Stream cal data to core */ + err = adi_apollo_hal_stream_reg_set(device, address, cal_data, len, 0); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_cfg_clk_cond_cal_data_get(adi_apollo_device_t* device, const uint16_t sides, uint8_t cal_data[], uint32_t len) +{ + int32_t err; + uint8_t i; + uint16_t side; + uint32_t size_bytes; + uint32_t address_ptr; + uint32_t address; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(cal_data); + ADI_APOLLO_INVALID_PARAM_RETURN(adi_api_utils_num_selected(sides) != 1); + + for (i = 0; i < ADI_APOLLO_NUM_SIDES; i++) { + side = sides & (ADI_APOLLO_SIDE_A << i); + if (side > 0) { + /* Get the cal data size and address location */ + err = adi_apollo_cfg_clk_cond_cal_data_len_get(device, &size_bytes); + ADI_APOLLO_ERROR_RETURN(err); + + if (size_bytes != len) { + return API_CMS_ERROR_INVALID_PARAM; + } + address_ptr = (side == ADI_APOLLO_SIDE_A) ? APOLLO_CPU_1_FW_CLK_COND_0_CALDATA_PTR : APOLLO_CPU_1_FW_CLK_COND_1_CALDATA_PTR; + err = adi_apollo_hal_reg32_get(device, address_ptr, &address); + ADI_APOLLO_ERROR_RETURN(err); + + /* Stream cal data from core */ + err = adi_apollo_hal_stream_reg_get(device, address, cal_data, len, 0); + ADI_APOLLO_ERROR_RETURN(err); + + break; + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_cfg_adc_cal_data_get(adi_apollo_device_t *device, const uint16_t adcs, uint8_t mode, uint8_t cal_data[], uint32_t len) +{ + int32_t err; + uint8_t i; + uint16_t adc; + uint32_t size_bytes; + uint32_t address; + uint8_t cal_data_offset; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(cal_data); + ADI_APOLLO_INVALID_PARAM_RETURN(adi_api_utils_num_selected(adcs) != 1); + ADI_APOLLO_INVALID_PARAM_RETURN(mode > 1); + + cal_data_offset = (mode == ADI_APOLLO_ADC_CAL_SEQUENTIAL_MODE) ? ADI_APOLLO_ADC_CAL_STRUCT_SEQ_DATA_OFFSET : ADI_APOLLO_ADC_CAL_STRUCT_RAND_DATA_OFFSET; + + for(i = 0; i < ADI_APOLLO_ADC_NUM; i++) { + adc = adcs & (ADI_APOLLO_ADC_A0 << i); + if (adc > 0) { + /* Get the cal data size and address location */ + err = cal_data_size_addr_get(device, + ADI_APOLLO_CONV_IDX_CONV(device->dev_info.is_8t8r, i, ADI_APOLLO_ADC_PER_SIDE_NUM), + ADI_APOLLO_ADC_CAL_STRUCT_SIZE, cal_data_offset, + ADI_APOLLO_CPU_1_FW_ADC_RX_OBJ_PTR, ADI_APOLLO_CPU_1_FW_ADC_RX_SIZE_PTR, + &size_bytes, &address); + ADI_APOLLO_ERROR_RETURN(err); + + if (size_bytes != len - 4) { /* size_bytes is size of cal data, not including 32-bit CRC */ + return API_CMS_ERROR_ERROR; /* cal_data size FW mismatch */ + } + + /* Stream cal data from core */ + err = adi_apollo_hal_stream_reg_get(device, address, cal_data, len, 0); + ADI_APOLLO_ERROR_RETURN(err); + + break; + } + } + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_cfg_dac_cal_data_get(adi_apollo_device_t *device, const uint16_t dacs, uint8_t cal_data[], uint32_t len) +{ + int32_t err; + uint8_t i; + uint16_t dac; + uint32_t size_bytes; + uint32_t address; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(cal_data); + ADI_APOLLO_INVALID_PARAM_RETURN(adi_api_utils_num_selected(dacs) != 1); + + for(i = 0; i < ADI_APOLLO_DAC_NUM; i++) { + dac = dacs & (ADI_APOLLO_DAC_A0 << i); + if (dac > 0) { + /* Get the cal data size and address location */ + err = cal_data_size_addr_get(device, + ADI_APOLLO_CONV_IDX_CONV(device->dev_info.is_8t8r, i, ADI_APOLLO_DAC_PER_SIDE_NUM), + ADI_APOLLO_DAC_CAL_OBJ_SIZE, ADI_APOLLO_DAC_CAL_OBJ_OFFSET, + ADI_APOLLO_CPU_1_FW_DAC_TX_OBJ_PTR, ADI_APOLLO_CPU_1_FW_DAC_TX_SIZE_PTR, + &size_bytes, &address); + ADI_APOLLO_ERROR_RETURN(err); + + if (size_bytes != len - 4) { /* size_bytes is size of cal data, not including 32-bit CRC */ + return API_CMS_ERROR_ERROR; /* cal_data size FW mismatch */ + } + + /* Stream cal data from core */ + err = adi_apollo_hal_stream_reg_get(device, address, cal_data, len, 0); + ADI_APOLLO_ERROR_RETURN(err); + + break; + } + } + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_cfg_serdes_rx_cal_data_get(adi_apollo_device_t* device, const uint16_t serdes, uint8_t cal_data[], uint32_t len) +{ + int32_t err; + uint8_t i; + uint16_t s; + uint32_t size_bytes; + uint32_t address; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(cal_data); + ADI_APOLLO_INVALID_PARAM_RETURN(adi_api_utils_num_selected(serdes) != 1); + + for (i = 0; i < ADI_APOLLO_NUM_JTX_SERDES_12PACKS; i++) { + s = serdes & (ADI_APOLLO_TXRX_SERDES_12PACK_A << i); + if (s > 0) { + /* Get the cal data size and address location */ + err = cal_data_size_addr_get(device, i, + ADI_APOLLO_SERDES_RX_CAL_OBJ_SIZE, ADI_APOLLO_SERDES_RX_CAL_OBJ_OFFSET, + ADI_APOLLO_CPU_0_FW_SERDES_RX_OBJ_PTR, ADI_APOLLO_CPU_0_FW_SERDES_RX_SIZE_PTR, + &size_bytes, &address); + ADI_APOLLO_ERROR_RETURN(err); + + if (size_bytes != len - 4) { /* size_bytes is size of cal data, not including 32-bit CRC */ + return API_CMS_ERROR_ERROR; /* cal_data size FW mismatch */ + } + + /* Stream cal data from core */ + err = adi_apollo_hal_stream_reg_get(device, address, cal_data, len, 0); + ADI_APOLLO_ERROR_RETURN(err); + + break; + } + } + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_cfg_serdes_tx_cal_data_get(adi_apollo_device_t* device, const uint16_t serdes, uint8_t cal_data[], uint32_t len) +{ + int32_t err; + uint8_t i; + uint16_t s; + uint32_t size_bytes; + uint32_t address; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(cal_data); + ADI_APOLLO_INVALID_PARAM_RETURN(adi_api_utils_num_selected(serdes) != 1); + + for (i = 0; i < ADI_APOLLO_NUM_JTX_SERDES_12PACKS; i++) { + s = serdes & (ADI_APOLLO_TXRX_SERDES_12PACK_A << i); + if (s > 0) { + /* Get the cal data size and address location */ + err = cal_data_size_addr_get(device, i, + ADI_APOLLO_SERDES_TX_CAL_OBJ_SIZE, ADI_APOLLO_SERDES_TX_CAL_OBJ_OFFSET, + ADI_APOLLO_CPU_1_FW_SERDES_TX_OBJ_PTR, ADI_APOLLO_CPU_1_FW_SERDES_TX_SIZE_PTR, + &size_bytes, &address); + ADI_APOLLO_ERROR_RETURN(err); + + if (size_bytes != len - 4) { /* size_bytes is size of cal data, not including 32-bit CRC */ + return API_CMS_ERROR_ERROR; /* cal_data size FW mismatch */ + } + + /* Stream cal data from core */ + err = adi_apollo_hal_stream_reg_get(device, address, cal_data, len, 0); + ADI_APOLLO_ERROR_RETURN(err); + + break; + } + } + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_cfg_adc_cal_data_len_get(adi_apollo_device_t* device, uint8_t mode, uint32_t* len) +{ + int32_t err = API_CMS_ERROR_OK; + uint8_t cal_data_offset; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(len); + ADI_APOLLO_INVALID_PARAM_RETURN(mode > 1); + + cal_data_offset = (mode == ADI_APOLLO_ADC_CAL_SEQUENTIAL_MODE) ? ADI_APOLLO_ADC_CAL_STRUCT_SEQ_DATA_OFFSET : ADI_APOLLO_ADC_CAL_STRUCT_RAND_DATA_OFFSET; + + /* Get the cal data size in byes. Same length for all ADC instances */ + err = cal_data_len_get(device, + cal_data_offset, + ADI_APOLLO_CPU_1_FW_ADC_RX_SIZE_PTR, + len); + + /* Add 32-bit checksum */ + *len += 4; + + return err; +} + +int32_t adi_apollo_cfg_dac_cal_data_len_get(adi_apollo_device_t* device, uint32_t* len) +{ + int32_t err = API_CMS_ERROR_OK; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(len); + + /* Get the cal data size in byes. Same length for all ADC instances */ + err = cal_data_len_get(device, + ADI_APOLLO_DAC_CAL_OBJ_OFFSET, + ADI_APOLLO_CPU_1_FW_DAC_TX_SIZE_PTR, + len); + + /* Add 32-bit checksum */ + *len += 4; + + return err; +} + +int32_t adi_apollo_cfg_serdes_rx_cal_data_len_get(adi_apollo_device_t* device, uint32_t* len) +{ + int32_t err = API_CMS_ERROR_OK; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(len); + + /* Get the cal data size in byes. Same length for all ADC instances */ + err = cal_data_len_get(device, + ADI_APOLLO_SERDES_RX_CAL_OBJ_OFFSET, + ADI_APOLLO_CPU_0_FW_SERDES_RX_SIZE_PTR, + len); + + /* Add 32-bit checksum */ + *len += 4; + + return err; +} + +int32_t adi_apollo_cfg_serdes_tx_cal_data_len_get(adi_apollo_device_t* device, uint32_t* len) +{ + int32_t err = API_CMS_ERROR_OK; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(len); + + /* Get the cal data size in byes. Same length for all ADC instances */ + err = cal_data_len_get(device, + ADI_APOLLO_SERDES_TX_CAL_OBJ_OFFSET, + ADI_APOLLO_CPU_1_FW_SERDES_TX_SIZE_PTR, + len); + + /* Add 32-bit checksum */ + *len += 4; + + return err; +} + +int32_t adi_apollo_cfg_profile_type_version_get(adi_apollo_device_t *device, adi_apollo_profile_version_t *ver) +{ + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(ver); + + ver->major = ADI_APOLLO_PROFILE_VERSION_MAJOR; + ver->minor = ADI_APOLLO_PROFILE_VERSION_MINOR; + ver->patch = ADI_APOLLO_PROFILE_VERSION_PATCH; + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_cfg_serdes_rx_bridging_cal_cfg_set(adi_apollo_device_t *device, uint8_t bridging_cal_runs) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_CMS_RANGE_CHECK(bridging_cal_runs, 0, 3); + + err = adi_apollo_hal_reg_set(device, (ADI_APOLLO_WARMBOOT_CFG_BASE_ADDR + ADI_APOLLO_SERDES_RX_NUM_BRIDGING_CALS), (0x80 | bridging_cal_runs)); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_cfg_clk_cond_cal_data_len_get(adi_apollo_device_t* device, uint32_t* len) +{ + int32_t err = API_CMS_ERROR_OK; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(len); + + /* The cal data size is in bytes, included 32-bit checksum. Same length for all Clock Conditioning instances + This value is fixed. + */ + *len = ADI_APOLLO_CLK_COND_CAL_DATA_LEN_BYTES; + + return err; +} + +static int32_t cal_data_len_get(adi_apollo_device_t* device, + uint32_t cal_obj_ofst, uint32_t siz_ptr, + uint32_t* size) +{ + int32_t err; + uint32_t cal_size_p; + + err = adi_apollo_hal_reg32_get(device, siz_ptr, &cal_size_p); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_reg32_get(device, cal_size_p + cal_obj_ofst, size); /* Size in bytes, doesn't include 4-byte crc */ + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +static int32_t cal_data_size_addr_get(adi_apollo_device_t *device, uint8_t idx, + uint32_t cal_obj_siz, uint32_t cal_obj_ofst, uint32_t obj_ptr, uint32_t siz_ptr, + uint32_t *size, uint32_t *address) +{ + int32_t err; + uint32_t cal_size_p; + uint32_t cal_data_addr_p; + uint32_t cal_offset = cal_obj_siz * idx; /* FW dependent byte offset into struct */ + + err = adi_apollo_hal_reg32_get(device, obj_ptr, &cal_data_addr_p); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_reg32_get(device, siz_ptr, &cal_size_p); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_reg32_get(device, cal_size_p + cal_obj_ofst, size); /* Size doesn't include 4-byte crc */ + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_reg32_get(device, cal_data_addr_p + cal_offset + cal_obj_ofst, address); /* Mem address of core's cal data */ + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +static uint8_t is_init_cal_cfg_valid(adi_apollo_init_cal_cfg_e init_cal_cfg) { + switch (init_cal_cfg) { + case ADI_APOLLO_INIT_CAL_DISABLED: + case ADI_APOLLO_INIT_CAL_DISABLED_WARMBOOT_FROM_NVM: + case ADI_APOLLO_INIT_CAL_DISABLED_WARMBOOT_FROM_USER: + case ADI_APOLLO_INIT_CAL_ENABLED: + case ADI_APOLLO_INIT_CAL_ENABLED_WARMBOOT_FROM_NVM: + case ADI_APOLLO_INIT_CAL_ENABLED_WARMBOOT_FROM_USER: + return 1; + } + + return 0; +} + +static uint8_t is_clk_cond_cal_cfg_valid(adi_apollo_sysclock_cond_cfg_e cc_cal_cfg) { + switch (cc_cal_cfg) { + case ADI_APOLLO_SYSCLKCONDITIONING_ENABLED: + case ADI_APOLLO_SYSCLKCONDITIONING_DISABLED: + case ADI_APOLLO_SYSCLKCONDITIONING_ENABLED_WARMBOOT_FROM_USER: + case ADI_APOLLO_SYSCLKCONDITIONING_DISABLED_WARMBOOT_FROM_USER: + return 1; + } + + return 0; +} + +static uint32_t calc_adc_cal_cfg_reg(int32_t idx) +{ + static uint32_t cal_cfg_reg_addr[] = { + ADI_APOLLO_WARMBOOT_CFG_ADC_A1_A0, /* A1:A0 */ + ADI_APOLLO_WARMBOOT_CFG_ADC_A3_A2, /* A3:A2 */ + ADI_APOLLO_WARMBOOT_CFG_ADC_B1_B0, /* B1:B0 */ + ADI_APOLLO_WARMBOOT_CFG_ADC_B3_B2, /* B3:B2 */ + }; + return cal_cfg_reg_addr[idx/2]; +} + +static uint32_t calc_dac_cal_cfg_reg(int32_t idx) +{ + static uint32_t cal_cfg_reg_addr[] = { + ADI_APOLLO_WARMBOOT_CFG_DAC_A1_A0, /* A1:A0 */ + ADI_APOLLO_WARMBOOT_CFG_DAC_A3_A2, /* A3:A2 */ + ADI_APOLLO_WARMBOOT_CFG_DAC_B1_B0, /* B1:B0 */ + ADI_APOLLO_WARMBOOT_CFG_DAC_B3_B2, /* B3:B2 */ + }; + return cal_cfg_reg_addr[idx/2]; +} +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_cfir.c b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_cfir.c new file mode 100644 index 00000000000000..a244542a09b16c --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_cfir.c @@ -0,0 +1,1070 @@ +/*! + * \brief APIs for CFIR + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_CFIR + * @{ + */ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_cfir.h" +#include "adi_apollo_cfir_local.h" +#include "adi_apollo_trigts_types.h" +#include "adi_apollo_trigts_local.h" +#include "adi_apollo_private_device.h" +#include "adi_apollo_private_blk_sel_types.h" + +#include "adi_apollo_bf_txrx_cfir_top.h" +#include "adi_apollo_bf_txrx_cfir_coeff.h" +#include "adi_apollo_bf_txrx_trigger_ts.h" +#include "adi_apollo_bf_custom.h" + +#include "adi_apollo_config.h" +#include "adi_apollo_hal.h" +#include "adi_utils.h" + +/*==================== P U B L I C A P I C O D E ====================*/ + +int32_t adi_apollo_cfir_pgm(adi_apollo_device_t* device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t cfirs, adi_apollo_cfir_pgm_t* config) +{ + int32_t err; + uint16_t cfir; + uint8_t i; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_DEV_FEAT_LOCKOUT_RETURN(terminal, ADI_APOLLO_EC_CFIR_LOCK); + ADI_APOLLO_NULL_POINTER_RETURN(config); + ADI_APOLLO_CFIR_BLK_SEL_MASK(cfirs); + + for (i = 0; i < ADI_APOLLO_CFIR_NUM; i++) { + cfir = cfirs & (ADI_APOLLO_CFIR_A0 << i); + if (cfir > 0) { + regmap_base_addr = calc_cfir_base(terminal, i); + + err = adi_apollo_hal_bf_set(device, BF_CFIR_BYPASS_INFO(regmap_base_addr), config->cfir_bypass); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_CFIR_SPARSE_FILT_EN_INFO(regmap_base_addr), config->cfir_sparse_filt_en); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_CFIR_32TAPS_EN_INFO(regmap_base_addr), config->cfir_32taps_en); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_COEFF_TRANSFER_INFO(regmap_base_addr), config->cfir_coeff_transfer); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_cfir_coeff_pgm(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t cfirs, uint8_t cfir_profiles, uint8_t cfir_dps, int16_t cfir_coeff_i[], int16_t cfir_coeff_q[], uint32_t len) +{ + int32_t err; + uint16_t cfir; + uint16_t cfir_profile; + uint16_t cfir_dp; + uint8_t i, j, k, dp; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_DEV_FEAT_LOCKOUT_RETURN(terminal, ADI_APOLLO_EC_CFIR_LOCK); + ADI_APOLLO_NULL_POINTER_RETURN(cfir_coeff_i); + ADI_APOLLO_NULL_POINTER_RETURN(cfir_coeff_q); + ADI_APOLLO_CFIR_BLK_SEL_MASK(cfirs); + + for (i = 0; i < ADI_APOLLO_CFIR_NUM; i++) { + cfir = cfirs & (ADI_APOLLO_CFIR_A0 << i); + if (cfir > 0) { + regmap_base_addr = calc_cfir_coeff_base(terminal, i); + + /* Set reg_map base address for subsequent paged writes */ + adi_apollo_hal_paged_base_addr_set(device, regmap_base_addr); + + for (dp = 0; dp < ADI_APOLLO_CFIR_PROFILE_NUM; dp++) { + cfir_profile = cfir_profiles & (ADI_APOLLO_CFIR_DP_0 << dp); + if (cfir_profile > 0) { + + for (j = 0; j < ADI_APOLLO_CFIR_DP_PER_INST_NUM; j++) { + cfir_dp = cfir_dps & (ADI_APOLLO_CFIR_DP_0 << j); + if (cfir_dp > 0) { + + if (dp == 0) { /* profile 1 */ + switch (j) { + case 0: + for (k = 0; k < ADI_APOLLO_CFIR_COEFF_NUM; k++) { + err = adi_apollo_hal_paged_bf_set(device, BF_I_COEFF_0_1_INFO(regmap_base_addr, k), cfir_coeff_i[k]); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_paged_bf_set(device, BF_Q_COEFF_0_1_INFO(regmap_base_addr, k), cfir_coeff_q[k]); + ADI_APOLLO_ERROR_RETURN(err); + } + break; + + case 1: + for (k = 0; k < ADI_APOLLO_CFIR_COEFF_NUM; k++) { + err = adi_apollo_hal_paged_bf_set(device, BF_I_COEFF_1_1_INFO(regmap_base_addr, k), cfir_coeff_i[k]); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_paged_bf_set(device, BF_Q_COEFF_1_1_INFO(regmap_base_addr, k), cfir_coeff_q[k]); + ADI_APOLLO_ERROR_RETURN(err); + } + break; + + case 2: + for (k = 0; k < ADI_APOLLO_CFIR_COEFF_NUM; k++) { + err = adi_apollo_hal_paged_bf_set(device, BF_I_COEFF_2_1_INFO(regmap_base_addr, k), cfir_coeff_i[k]); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_paged_bf_set(device, BF_Q_COEFF_2_1_INFO(regmap_base_addr, k), cfir_coeff_q[k]); + ADI_APOLLO_ERROR_RETURN(err); + } + break; + case 3: + for (k = 0; k < ADI_APOLLO_CFIR_COEFF_NUM; k++) { + err = adi_apollo_hal_paged_bf_set(device, BF_I_COEFF_3_1_INFO(regmap_base_addr, k), cfir_coeff_i[k]); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_paged_bf_set(device, BF_Q_COEFF_3_1_INFO(regmap_base_addr, k), cfir_coeff_q[k]); + ADI_APOLLO_ERROR_RETURN(err); + } + break; + } + } else { /* profile #2 */ + switch (j) { + case 0: + for (k = 0; k < ADI_APOLLO_CFIR_COEFF_NUM; k++) { + err = adi_apollo_hal_paged_bf_set(device, BF_I_COEFF_0_2_INFO(regmap_base_addr, k), cfir_coeff_i[k]); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_paged_bf_set(device, BF_Q_COEFF_0_2_INFO(regmap_base_addr, k), cfir_coeff_q[k]); + ADI_APOLLO_ERROR_RETURN(err); + } + break; + + case 1: + for (k = 0; k < ADI_APOLLO_CFIR_COEFF_NUM; k++) { + err = adi_apollo_hal_paged_bf_set(device, BF_I_COEFF_1_2_INFO(regmap_base_addr, k), cfir_coeff_i[k]); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_paged_bf_set(device, BF_Q_COEFF_1_2_INFO(regmap_base_addr, k), cfir_coeff_q[k]); + ADI_APOLLO_ERROR_RETURN(err); + } + break; + + case 2: + for (k = 0; k < ADI_APOLLO_CFIR_COEFF_NUM; k++) { + err = adi_apollo_hal_paged_bf_set(device, BF_I_COEFF_2_2_INFO(regmap_base_addr, k), cfir_coeff_i[k]); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_paged_bf_set(device, BF_Q_COEFF_2_2_INFO(regmap_base_addr, k), cfir_coeff_q[k]); + ADI_APOLLO_ERROR_RETURN(err); + } + break; + + case 3: + for (k = 0; k < ADI_APOLLO_CFIR_COEFF_NUM; k++) { + err = adi_apollo_hal_paged_bf_set(device, BF_I_COEFF_3_2_INFO(regmap_base_addr, k), cfir_coeff_i[k]); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_paged_bf_set(device, BF_Q_COEFF_3_2_INFO(regmap_base_addr, k), cfir_coeff_q[k]); + ADI_APOLLO_ERROR_RETURN(err); + } + break; + } + } + } + } + } + } + + + } + + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_cfir_scalar_pgm(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t cfirs, uint8_t cfir_profiles, uint8_t cfir_dps, uint16_t scalar_i, uint16_t scalar_q) +{ + int32_t err; + uint16_t cfir; + uint16_t cfir_profile; + uint16_t cfir_dp; + uint8_t i, j, dp; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_DEV_FEAT_LOCKOUT_RETURN(terminal, ADI_APOLLO_EC_CFIR_LOCK); + ADI_APOLLO_CFIR_BLK_SEL_MASK(cfirs); + + for (i = 0; i < ADI_APOLLO_CFIR_NUM; i++) { + cfir = cfirs & (ADI_APOLLO_CFIR_A0 << i); + if (cfir > 0) { + regmap_base_addr = calc_cfir_base(terminal, i); + + /* Set reg_map base address for subsequent paged writes */ + err = adi_apollo_hal_paged_base_addr_set(device, regmap_base_addr); + ADI_APOLLO_ERROR_RETURN(err); + + for (dp = 0; dp < ADI_APOLLO_CFIR_PROFILE_NUM; dp++) { + cfir_profile = cfir_profiles & (ADI_APOLLO_CFIR_DP_0 << dp); + if (cfir_profile > 0) { + + for (j = 0; j < ADI_APOLLO_CFIR_DP_PER_INST_NUM; j++) { + cfir_dp = cfir_dps & (ADI_APOLLO_CFIR_DP_0 << j); + if (cfir_dp > 0) { + + if (dp == 0) { /* profile 1 */ + switch (j) { + case 0: + err = adi_apollo_hal_paged_bf_set(device, BF_I_COMPLEX_SCALAR_1_INFO(regmap_base_addr, 0), scalar_i); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_paged_bf_set(device, BF_Q_COMPLEX_SCALAR_1_INFO(regmap_base_addr, 0), scalar_q); + ADI_APOLLO_ERROR_RETURN(err); + break; + case 1: + err = adi_apollo_hal_paged_bf_set(device, BF_I_COMPLEX_SCALAR_1_INFO(regmap_base_addr, 1), scalar_i); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_paged_bf_set(device, BF_Q_COMPLEX_SCALAR_1_INFO(regmap_base_addr, 1), scalar_q); + ADI_APOLLO_ERROR_RETURN(err); + break; + case 2: + err = adi_apollo_hal_paged_bf_set(device, BF_I_COMPLEX_SCALAR_1_INFO(regmap_base_addr, 2), scalar_i); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_paged_bf_set(device, BF_Q_COMPLEX_SCALAR_1_INFO(regmap_base_addr, 2), scalar_q); + ADI_APOLLO_ERROR_RETURN(err); + break; + case 3: + err = adi_apollo_hal_paged_bf_set(device, BF_I_COMPLEX_SCALAR_1_INFO(regmap_base_addr, 3), scalar_i); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_paged_bf_set(device, BF_Q_COMPLEX_SCALAR_1_INFO(regmap_base_addr, 3), scalar_q); + ADI_APOLLO_ERROR_RETURN(err); + break; + } + } else { /* profile #2 */ + switch (j) { + case 0: + err = adi_apollo_hal_paged_bf_set(device, BF_I_COMPLEX_SCALAR_2_INFO(regmap_base_addr, 0), scalar_i); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_paged_bf_set(device, BF_Q_COMPLEX_SCALAR_2_INFO(regmap_base_addr, 0), scalar_q); + ADI_APOLLO_ERROR_RETURN(err); + break; + case 1: + err = adi_apollo_hal_paged_bf_set(device, BF_I_COMPLEX_SCALAR_2_INFO(regmap_base_addr, 1), scalar_i); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_paged_bf_set(device, BF_Q_COMPLEX_SCALAR_2_INFO(regmap_base_addr, 1), scalar_q); + ADI_APOLLO_ERROR_RETURN(err); + break; + case 2: + err = adi_apollo_hal_paged_bf_set(device, BF_I_COMPLEX_SCALAR_2_INFO(regmap_base_addr, 2), scalar_i); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_paged_bf_set(device, BF_Q_COMPLEX_SCALAR_2_INFO(regmap_base_addr, 2), scalar_q); + ADI_APOLLO_ERROR_RETURN(err); + break; + case 3: + err = adi_apollo_hal_paged_bf_set(device, BF_I_COMPLEX_SCALAR_2_INFO(regmap_base_addr, 3), scalar_i); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_paged_bf_set(device, BF_Q_COMPLEX_SCALAR_2_INFO(regmap_base_addr, 3), scalar_q); + ADI_APOLLO_ERROR_RETURN(err); + break; + } + } + } + } + } + } + + + } + + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_cfir_gain_pgm(adi_apollo_device_t* device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t cfirs, uint8_t cfir_profiles, uint8_t cfir_dps, uint8_t gain) +{ + int32_t err; + adi_apollo_blk_sel_t cfir; + uint16_t cfir_profile; + uint16_t cfir_dp; + uint8_t i, j, dp; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_DEV_FEAT_LOCKOUT_RETURN(terminal, ADI_APOLLO_EC_CFIR_LOCK); + ADI_APOLLO_CFIR_BLK_SEL_MASK(cfirs); + + for (i = 0; i < ADI_APOLLO_CFIR_NUM; i++) { + cfir = cfirs & (ADI_APOLLO_CFIR_A0 << i); + if (cfir > 0) { + regmap_base_addr = calc_cfir_base(terminal, i); + + /* Set reg_map base address for subsequent paged writes */ + err = adi_apollo_hal_paged_base_addr_set(device, regmap_base_addr); + ADI_APOLLO_ERROR_RETURN(err); + + for (dp = 0; dp < ADI_APOLLO_CFIR_PROFILE_NUM; dp++) { + cfir_profile = cfir_profiles & (ADI_APOLLO_CFIR_DP_0 << dp); + if (cfir_profile > 0) { + + for (j = 0; j < ADI_APOLLO_CFIR_DP_PER_INST_NUM; j++) { + cfir_dp = cfir_dps & (ADI_APOLLO_CFIR_DP_0 << j); + if (cfir_dp > 0) { + + if (dp == 0) { /* profile 1 */ + switch (j) { + case 0: + err = adi_apollo_hal_paged_bf_set(device, BF_CFIR_GAIN0_1_INFO(regmap_base_addr), gain); + ADI_APOLLO_ERROR_RETURN(err); + break; + case 1: + err = adi_apollo_hal_paged_bf_set(device, BF_CFIR_GAIN1_1_INFO(regmap_base_addr), gain); + ADI_APOLLO_ERROR_RETURN(err); + break; + case 2: + err = adi_apollo_hal_paged_bf_set(device, BF_CFIR_GAIN2_1_INFO(regmap_base_addr), gain); + ADI_APOLLO_ERROR_RETURN(err); + break; + case 3: + err = adi_apollo_hal_paged_bf_set(device, BF_CFIR_GAIN3_1_INFO(regmap_base_addr), gain); + ADI_APOLLO_ERROR_RETURN(err); + break; + } + } else { /* profile #2 */ + switch (j) { + case 0: + err = adi_apollo_hal_paged_bf_set(device, BF_CFIR_GAIN0_2_INFO(regmap_base_addr), gain); + ADI_APOLLO_ERROR_RETURN(err); + break; + case 1: + err = adi_apollo_hal_paged_bf_set(device, BF_CFIR_GAIN1_2_INFO(regmap_base_addr), gain); + ADI_APOLLO_ERROR_RETURN(err); + break; + case 2: + err = adi_apollo_hal_paged_bf_set(device, BF_CFIR_GAIN2_2_INFO(regmap_base_addr), gain); + ADI_APOLLO_ERROR_RETURN(err); + break; + case 3: + err = adi_apollo_hal_paged_bf_set(device, BF_CFIR_GAIN3_2_INFO(regmap_base_addr), gain); + ADI_APOLLO_ERROR_RETURN(err); + break; + } + } + } + } + } + } + + + } + + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_cfir_sparse_coeff_sel_pgm(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t cfirs, uint8_t cfir_profiles, uint8_t cfir_dps, uint16_t cfir_coeff_sel[], uint32_t len) +{ + int32_t err; + adi_apollo_blk_sel_t cfir; + uint16_t cfir_profile; + uint16_t cfir_dp; + uint8_t i, j, k, dp; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_DEV_FEAT_LOCKOUT_RETURN(terminal, ADI_APOLLO_EC_CFIR_LOCK); + ADI_APOLLO_NULL_POINTER_RETURN(cfir_coeff_sel); + ADI_APOLLO_CFIR_BLK_SEL_MASK(cfirs); + + for (i = 0; i < ADI_APOLLO_CFIR_NUM; i++) { + cfir = cfirs & (ADI_APOLLO_CFIR_A0 << i); + if (cfir > 0) { + + regmap_base_addr = calc_cfir_coeff_base(terminal, i); + + for (dp = 0; dp < ADI_APOLLO_CFIR_PROFILE_NUM; dp++) { + cfir_profile = cfir_profiles & (ADI_APOLLO_CFIR_DP_0 << dp); + if (cfir_profile > 0) { + + for (j = 0; j < ADI_APOLLO_CFIR_DP_PER_INST_NUM; j++) { + cfir_dp = cfir_dps & (ADI_APOLLO_CFIR_DP_0 << j); + if (cfir_dp > 0) { + + if (dp == 0) { /* profile 1 */ + switch (j) { + case 0: + for(k = 0; k < ADI_APOLLO_CFIR_COEFF_NUM; k++) { + err = adi_apollo_hal_bf_set(device, BF_COEFF_SEL_0_1_INFO(regmap_base_addr, k), cfir_coeff_sel[k]); + ADI_APOLLO_ERROR_RETURN(err); + } + break; + case 1: + for(k = 0; k < ADI_APOLLO_CFIR_COEFF_NUM; k++) { + err = adi_apollo_hal_bf_set(device, BF_COEFF_SEL_1_1_INFO(regmap_base_addr, k), cfir_coeff_sel[k]); + ADI_APOLLO_ERROR_RETURN(err); + } + break; + case 2: + for(k = 0; k < ADI_APOLLO_CFIR_COEFF_NUM; k++) { + err = adi_apollo_hal_bf_set(device, BF_COEFF_SEL_2_1_INFO(regmap_base_addr, k), cfir_coeff_sel[k]); + ADI_APOLLO_ERROR_RETURN(err); + } + break; + case 3: + for(k = 0; k < ADI_APOLLO_CFIR_COEFF_NUM; k++) { + err = adi_apollo_hal_bf_set(device, BF_COEFF_SEL_3_1_INFO(regmap_base_addr, k), cfir_coeff_sel[k]); + ADI_APOLLO_ERROR_RETURN(err); + } + break; + } + } else { /* profile #2 */ + switch (j) { + case 0: + for(k = 0; k < ADI_APOLLO_CFIR_COEFF_NUM; k++) { + err = adi_apollo_hal_bf_set(device, BF_COEFF_SEL_0_2_INFO(regmap_base_addr, k), cfir_coeff_sel[k]); + ADI_APOLLO_ERROR_RETURN(err); + } + break; + case 1: + for(k = 0; k < ADI_APOLLO_CFIR_COEFF_NUM; k++) { + err = adi_apollo_hal_bf_set(device, BF_COEFF_SEL_1_2_INFO(regmap_base_addr, k), cfir_coeff_sel[k]); + ADI_APOLLO_ERROR_RETURN(err); + } + break; + case 2: + for(k = 0; k < ADI_APOLLO_CFIR_COEFF_NUM; k++) { + err = adi_apollo_hal_bf_set(device, BF_COEFF_SEL_2_2_INFO(regmap_base_addr, k), cfir_coeff_sel[k]); + ADI_APOLLO_ERROR_RETURN(err); + } + break; + case 3: + for(k = 0; k < ADI_APOLLO_CFIR_COEFF_NUM; k++) { + err = adi_apollo_hal_bf_set(device, BF_COEFF_SEL_3_2_INFO(regmap_base_addr, k), cfir_coeff_sel[k]); + ADI_APOLLO_ERROR_RETURN(err); + } + break; + } + } + } + } + } + } + } + + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_cfir_sparse_mem_sel_pgm(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t cfirs, uint8_t cfir_profiles, uint8_t cfir_dps, uint8_t cfir_mem_sel[], uint32_t len) +{ + int32_t err; + adi_apollo_blk_sel_t cfir; + uint16_t cfir_profile; + uint16_t cfir_dp; + uint8_t i, j, dp; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_DEV_FEAT_LOCKOUT_RETURN(terminal, ADI_APOLLO_EC_CFIR_LOCK); + ADI_APOLLO_NULL_POINTER_RETURN(cfir_mem_sel); + ADI_APOLLO_INVALID_PARAM_RETURN(len != ADI_APOLLO_CFIR_MEM_SEL_NUM) + ADI_APOLLO_CFIR_BLK_SEL_MASK(cfirs); + + for (i = 0; i < ADI_APOLLO_CFIR_NUM; i++) { + cfir = cfirs & (ADI_APOLLO_CFIR_A0 << i); + if (cfir > 0) { + regmap_base_addr = calc_cfir_base(terminal, i); + + for (dp = 0; dp < ADI_APOLLO_CFIR_PROFILE_NUM; dp++) { + cfir_profile = cfir_profiles & (ADI_APOLLO_CFIR_DP_0 << dp); + if (cfir_profile > 0) { + + for (j = 0; j < ADI_APOLLO_CFIR_DP_PER_INST_NUM; j++) { + cfir_dp = cfir_dps & (ADI_APOLLO_CFIR_DP_0 << j); + if (cfir_dp > 0) { + + if (dp == 0) { /* profile 1 */ + switch (j) { + case 0: + err = adi_apollo_hal_bf_set(device, BF_DPATH0_MEM_SEL0_1_INFO(regmap_base_addr), cfir_mem_sel[0]); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_DPATH0_MEM_SEL1_1_INFO(regmap_base_addr), cfir_mem_sel[1]); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_DPATH0_MEM_SEL2_1_INFO(regmap_base_addr), cfir_mem_sel[2]); + ADI_APOLLO_ERROR_RETURN(err); + break; + case 1: + err = adi_apollo_hal_bf_set(device, BF_DPATH1_MEM_SEL0_1_INFO(regmap_base_addr), cfir_mem_sel[0]); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_DPATH1_MEM_SEL1_1_INFO(regmap_base_addr), cfir_mem_sel[1]); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_DPATH1_MEM_SEL2_1_INFO(regmap_base_addr), cfir_mem_sel[2]); + ADI_APOLLO_ERROR_RETURN(err); + break; + case 2: + err = adi_apollo_hal_bf_set(device, BF_DPATH2_MEM_SEL0_1_INFO(regmap_base_addr), cfir_mem_sel[0]); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_DPATH2_MEM_SEL1_1_INFO(regmap_base_addr), cfir_mem_sel[1]); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_DPATH2_MEM_SEL2_1_INFO(regmap_base_addr), cfir_mem_sel[2]); + ADI_APOLLO_ERROR_RETURN(err); + break; + case 3: + err = adi_apollo_hal_bf_set(device, BF_DPATH3_MEM_SEL0_1_INFO(regmap_base_addr), cfir_mem_sel[0]); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_DPATH3_MEM_SEL1_1_INFO(regmap_base_addr), cfir_mem_sel[1]); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_DPATH3_MEM_SEL2_1_INFO(regmap_base_addr), cfir_mem_sel[2]); + ADI_APOLLO_ERROR_RETURN(err); + break; + } + } else { /* profile #2 */ + switch (j) { + case 0: + err = adi_apollo_hal_bf_set(device, BF_DPATH0_MEM_SEL0_2_INFO(regmap_base_addr), cfir_mem_sel[0]); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_DPATH0_MEM_SEL1_2_INFO(regmap_base_addr), cfir_mem_sel[1]); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_DPATH0_MEM_SEL2_2_INFO(regmap_base_addr), cfir_mem_sel[2]); + ADI_APOLLO_ERROR_RETURN(err); + break; + case 1: + err = adi_apollo_hal_bf_set(device, BF_DPATH1_MEM_SEL0_2_INFO(regmap_base_addr), cfir_mem_sel[0]); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_DPATH1_MEM_SEL1_2_INFO(regmap_base_addr), cfir_mem_sel[1]); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_DPATH1_MEM_SEL2_2_INFO(regmap_base_addr), cfir_mem_sel[2]); + ADI_APOLLO_ERROR_RETURN(err); + break; + case 2: + err = adi_apollo_hal_bf_set(device, BF_DPATH2_MEM_SEL0_2_INFO(regmap_base_addr), cfir_mem_sel[0]); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_DPATH2_MEM_SEL1_2_INFO(regmap_base_addr), cfir_mem_sel[1]); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_DPATH2_MEM_SEL2_2_INFO(regmap_base_addr), cfir_mem_sel[2]); + ADI_APOLLO_ERROR_RETURN(err); + break; + case 3: + err = adi_apollo_hal_bf_set(device, BF_DPATH3_MEM_SEL0_2_INFO(regmap_base_addr), cfir_mem_sel[0]); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_DPATH3_MEM_SEL1_2_INFO(regmap_base_addr), cfir_mem_sel[1]); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_DPATH3_MEM_SEL2_2_INFO(regmap_base_addr), cfir_mem_sel[2]); + ADI_APOLLO_ERROR_RETURN(err); + break; + } + } + } + } + } + } + + + } + + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_cfir_profile_sel(adi_apollo_device_t* device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t cfirs, uint8_t cfir_dps, uint8_t coeff_profile_sel) +{ + int32_t err; + adi_apollo_blk_sel_t cfir; + uint16_t cfir_dp; + uint8_t i, j; + uint32_t regmap_base_addr = 0; + uint8_t profile_sel_bf; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_DEV_FEAT_LOCKOUT_RETURN(terminal, ADI_APOLLO_EC_CFIR_LOCK); + ADI_APOLLO_INVALID_PARAM_RETURN(adi_api_utils_num_selected(coeff_profile_sel) != 1); + ADI_APOLLO_CFIR_BLK_SEL_MASK(cfirs); + + /* single bit is used to select between profile 0 or 1 */ + profile_sel_bf = coeff_profile_sel == ADI_APOLLO_CFIR_PROFILE_0 ? 0 : 1; + + for (i = 0; i < ADI_APOLLO_CFIR_NUM; i++) { + cfir = cfirs & (ADI_APOLLO_CFIR_A0 << i); + if (cfir > 0) { + regmap_base_addr = calc_cfir_base(terminal, i); + + for (j = 0; j < ADI_APOLLO_CFIR_DP_PER_INST_NUM; j++) { + cfir_dp = cfir_dps & (ADI_APOLLO_CFIR_DP_0 << j); + if (cfir_dp > 0) { + + switch (j) { + case 0: + err = adi_apollo_hal_bf_set(device, BF_COEFF_PROFILE_SEL0_INFO(regmap_base_addr), profile_sel_bf); + ADI_APOLLO_ERROR_RETURN(err); + break; + case 1: + err = adi_apollo_hal_bf_set(device, BF_COEFF_PROFILE_SEL1_INFO(regmap_base_addr), profile_sel_bf); + ADI_APOLLO_ERROR_RETURN(err); + break; + case 2: + err = adi_apollo_hal_bf_set(device, BF_COEFF_PROFILE_SEL2_INFO(regmap_base_addr), profile_sel_bf); + ADI_APOLLO_ERROR_RETURN(err); + break; + case 3: + err = adi_apollo_hal_bf_set(device, BF_COEFF_PROFILE_SEL3_INFO(regmap_base_addr), profile_sel_bf); + ADI_APOLLO_ERROR_RETURN(err); + break; + } + } + } + + /* Generate 0->1 pulse to transfer selected back to active */ + err = adi_apollo_hal_bf_set(device, BF_COEFF_TRANSFER_INFO(regmap_base_addr), 0); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_COEFF_TRANSFER_INFO(regmap_base_addr), 1); + ADI_APOLLO_ERROR_RETURN(err); + } + + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_cfir_mode_enable_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t cfirs, adi_apollo_cfir_enable_sel_e mode) +{ + int32_t err; + adi_apollo_blk_sel_t cfir; + uint8_t i; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_DEV_FEAT_LOCKOUT_RETURN(terminal, ADI_APOLLO_EC_CFIR_LOCK); + ADI_APOLLO_CFIR_BLK_SEL_MASK(cfirs); + + for (i = 0; i < ADI_APOLLO_CFIR_NUM; i++) { + cfir = cfirs & (ADI_APOLLO_CFIR_A0 << i); + if (cfir > 0) { + regmap_base_addr = calc_cfir_base(terminal, i); + + err = adi_apollo_hal_bf_set(device, BF_CFIR_BYPASS_INFO(regmap_base_addr), (mode == ADI_APOLLO_CFIR_BYPASS) ? 1 : 0); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_cfir_profile_sel_mode_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t cfirs, const adi_apollo_cfir_profile_sel_mode_e prof_sel_mode) +{ + int32_t err; + uint8_t i; + adi_apollo_blk_sel_t cfir; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_DEV_FEAT_LOCKOUT_RETURN(terminal, ADI_APOLLO_EC_CFIR_LOCK); + ADI_APOLLO_INVALID_PARAM_RETURN(prof_sel_mode > (ADI_APOLLO_CFIR_CHAN_SEL_NUM - 1)); + ADI_APOLLO_CFIR_BLK_SEL_MASK(cfirs); + + const uint8_t bank_regs[ADI_APOLLO_CFIR_CHAN_SEL_NUM][3] = { + {0, 0}, // trigger_en, gpio_profile_en + {0, 1}, + {1, 0}, + {1, 1}}; + + for (i = 0; i < ADI_APOLLO_CFIR_NUM; i++) { + cfir = cfirs & (ADI_APOLLO_CFIR_A0 << i); + if (cfir > 0) { + regmap_base_addr = calc_cfir_base(terminal, i); + + err = adi_apollo_hal_bf_set(device, BF_TRIGGER_EN_TXRX_CFIR_TOP_INFO(regmap_base_addr), bank_regs[prof_sel_mode][0]); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_GPIO_PROFILE_EN_INFO(regmap_base_addr), bank_regs[prof_sel_mode][1]); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_cfir_next_hop_num_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t cfirs, uint8_t cfir_dps, int16_t hop_num) +{ + int32_t err; + uint8_t i, j; + adi_apollo_blk_sel_t cfir; + uint16_t cfir_dp; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_DEV_FEAT_LOCKOUT_RETURN(terminal, ADI_APOLLO_EC_CFIR_LOCK); + ADI_APOLLO_INVALID_PARAM_RETURN(hop_num > (ADI_APOLLO_CFIR_PROFILE_NUM - 1)); + ADI_APOLLO_CFIR_BLK_SEL_MASK(cfirs); + + for (i = 0; i < ADI_APOLLO_CFIR_NUM; i++) { + cfir = cfirs & (ADI_APOLLO_CFIR_A0 << i); + + if (cfir > 0) { + regmap_base_addr = calc_cfir_base(terminal, i); + + for (j = 0; j < ADI_APOLLO_CFIR_DP_PER_INST_NUM; j++) { + cfir_dp = cfir_dps & (ADI_APOLLO_CFIR_DP_0 << j); + + if (cfir_dp > 0) { + + switch (j) { + case 0: + err = adi_apollo_hal_bf_set(device, BF_COEFF_PROFILE_SEL0_INFO(regmap_base_addr), hop_num); + ADI_APOLLO_ERROR_RETURN(err); + break; + case 1: + err = adi_apollo_hal_bf_set(device, BF_COEFF_PROFILE_SEL1_INFO(regmap_base_addr), hop_num); + ADI_APOLLO_ERROR_RETURN(err); + break; + case 2: + err = adi_apollo_hal_bf_set(device, BF_COEFF_PROFILE_SEL2_INFO(regmap_base_addr), hop_num); + ADI_APOLLO_ERROR_RETURN(err); + break; + case 3: + err = adi_apollo_hal_bf_set(device, BF_COEFF_PROFILE_SEL3_INFO(regmap_base_addr), hop_num); + ADI_APOLLO_ERROR_RETURN(err); + break; + } + } + } + } + } + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_cfir_inspect(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t cfirs, adi_apollo_cfir_inspect_t *cfir_inspect) +{ + int32_t err; + adi_apollo_blk_sel_t cfir; + uint8_t i, j, k, dp, is_bypassed; + uint32_t regmap_base_addr = 0, regmap_coeff_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_DEV_FEAT_LOCKOUT_RETURN(terminal, ADI_APOLLO_EC_CFIR_LOCK); + ADI_APOLLO_INVALID_PARAM_RETURN(adi_api_utils_num_selected(cfirs)!= 1); + ADI_APOLLO_NULL_POINTER_RETURN(cfir_inspect); + ADI_APOLLO_CFIR_BLK_SEL_MASK(cfirs); + + for (i = 0; i < ADI_APOLLO_CFIR_NUM; i++) { + cfir = cfirs & (ADI_APOLLO_CFIR_A0 << i); + if (cfir > 0) { + regmap_base_addr = calc_cfir_base(terminal, i); + + /* cfir_pgm */ + err = adi_apollo_hal_bf_get(device, BF_CFIR_BYPASS_INFO(regmap_base_addr), &is_bypassed, 1); + ADI_APOLLO_ERROR_RETURN(err); + + cfir_inspect->dp_cfg.enable = !is_bypassed; // not-bypassed means cfir is enabled + + err = adi_apollo_hal_bf_get(device, BF_CFIR_SPARSE_FILT_EN_INFO(regmap_base_addr), (uint8_t*)&(cfir_inspect->dp_cfg.sparse_mode), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_CFIR_32TAPS_EN_INFO(regmap_base_addr), (uint8_t*)&(cfir_inspect->dp_cfg.cfir_mode), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_COEFF_TRANSFER_INFO(regmap_base_addr), (uint8_t*)&(cfir_inspect->cfir_coeff_transfer), 1); + ADI_APOLLO_ERROR_RETURN(err); + + regmap_coeff_base_addr = calc_cfir_coeff_base(terminal, i); + for (dp = 0; dp < ADI_APOLLO_CFIR_PROFILE_NUM; dp++) { + for (j = 0; j < ADI_APOLLO_CFIR_DP_PER_INST_NUM; j++) { + if (dp == 0) { /* profile 1 */ + switch (j) { + case 0: + + for (k = 0; k < ADI_APOLLO_CFIR_COEFF_NUM; k++) { + /* coeff_pgm */ + err = adi_apollo_hal_bf_get(device, BF_I_COEFF_0_1_INFO(regmap_coeff_base_addr, k), (uint8_t*)&(cfir_inspect->dp_cfg.coeffs_i[dp][j][k]), 2); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_Q_COEFF_0_1_INFO(regmap_coeff_base_addr, k), (uint8_t*)&(cfir_inspect->dp_cfg.coeffs_q[dp][j][k]), 2); + ADI_APOLLO_ERROR_RETURN(err); + + /* sparse_coeff_sel_pgm */ + err = adi_apollo_hal_bf_get(device, BF_COEFF_SEL_0_1_INFO(regmap_coeff_base_addr, k), (uint8_t*)&(cfir_inspect->sparse_coeff[dp][j][k]), 2); + ADI_APOLLO_ERROR_RETURN(err); + } + + /* scalar_pgm */ + err = adi_apollo_hal_bf_get(device, BF_I_COMPLEX_SCALAR_1_INFO(regmap_base_addr, 0), (uint8_t*)&(cfir_inspect->dp_cfg.scalar_i[dp][j]), 2); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_Q_COMPLEX_SCALAR_1_INFO(regmap_base_addr, 0), (uint8_t*)&(cfir_inspect->dp_cfg.scalar_q[dp][j]), 2); + ADI_APOLLO_ERROR_RETURN(err); + + /* gain_pgm */ + err = adi_apollo_hal_bf_get(device, BF_CFIR_GAIN0_1_INFO(regmap_base_addr), (uint8_t*)&(cfir_inspect->dp_cfg.cfir_gain_dB[dp][j]), 1); + ADI_APOLLO_ERROR_RETURN(err); + + /* sparse_mem_sel_pgm */ + err = adi_apollo_hal_bf_get(device, BF_DPATH0_MEM_SEL0_1_INFO(regmap_base_addr), (uint8_t*)&(cfir_inspect->sparse_mem[dp][j][0]), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_DPATH0_MEM_SEL1_1_INFO(regmap_base_addr), (uint8_t*)&(cfir_inspect->sparse_mem[dp][j][1]), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_DPATH0_MEM_SEL2_1_INFO(regmap_base_addr), (uint8_t*)&(cfir_inspect->sparse_mem[dp][j][2]), 1); + ADI_APOLLO_ERROR_RETURN(err); + break; + + case 1: + for (k = 0; k < ADI_APOLLO_CFIR_COEFF_NUM; k++) { + err = adi_apollo_hal_bf_get(device, BF_I_COEFF_1_1_INFO(regmap_coeff_base_addr, k), (uint8_t*)&(cfir_inspect->dp_cfg.coeffs_i[dp][j][k]), 2); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_Q_COEFF_1_1_INFO(regmap_coeff_base_addr, k), (uint8_t*)&(cfir_inspect->dp_cfg.coeffs_q[dp][j][k]), 2); + ADI_APOLLO_ERROR_RETURN(err); + + /* sparse_coeff_sel_pgm */ + err = adi_apollo_hal_bf_get(device, BF_COEFF_SEL_1_1_INFO(regmap_coeff_base_addr, k), (uint8_t*)&(cfir_inspect->sparse_coeff[dp][j][k]), 2); + ADI_APOLLO_ERROR_RETURN(err); + } + err = adi_apollo_hal_bf_get(device, BF_I_COMPLEX_SCALAR_1_INFO(regmap_base_addr, 1), (uint8_t*)&(cfir_inspect->dp_cfg.scalar_i[dp][j]), 2); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_Q_COMPLEX_SCALAR_1_INFO(regmap_base_addr, 1), (uint8_t*)&(cfir_inspect->dp_cfg.scalar_q[dp][j]), 2); + ADI_APOLLO_ERROR_RETURN(err); + + /* gain_pgm */ + err = adi_apollo_hal_bf_get(device, BF_CFIR_GAIN1_1_INFO(regmap_base_addr), (uint8_t*)&(cfir_inspect->dp_cfg.cfir_gain_dB[dp][j]), 1); + ADI_APOLLO_ERROR_RETURN(err); + + /* sparse_mem_sel_pgm */ + err = adi_apollo_hal_bf_get(device, BF_DPATH1_MEM_SEL0_1_INFO(regmap_base_addr), (uint8_t*)&(cfir_inspect->sparse_mem[dp][j][0]), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_DPATH1_MEM_SEL1_1_INFO(regmap_base_addr), (uint8_t*)&(cfir_inspect->sparse_mem[dp][j][1]), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_DPATH1_MEM_SEL2_1_INFO(regmap_base_addr), (uint8_t*)&(cfir_inspect->sparse_mem[dp][j][2]), 1); + ADI_APOLLO_ERROR_RETURN(err); + break; + + case 2: + for (k = 0; k < ADI_APOLLO_CFIR_COEFF_NUM; k++) { + err = adi_apollo_hal_bf_get(device, BF_I_COEFF_2_1_INFO(regmap_coeff_base_addr, k), (uint8_t*)&(cfir_inspect->dp_cfg.coeffs_i[dp][j][k]), 2); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_Q_COEFF_2_1_INFO(regmap_coeff_base_addr, k), (uint8_t*)&(cfir_inspect->dp_cfg.coeffs_q[dp][j][k]), 2); + ADI_APOLLO_ERROR_RETURN(err); + + /* sparse_coeff_sel_pgm */ + err = adi_apollo_hal_bf_get(device, BF_COEFF_SEL_2_1_INFO(regmap_coeff_base_addr, k), (uint8_t*)&(cfir_inspect->sparse_coeff[dp][j][k]), 2); + ADI_APOLLO_ERROR_RETURN(err); + } + err = adi_apollo_hal_bf_get(device, BF_I_COMPLEX_SCALAR_1_INFO(regmap_base_addr, 2), (uint8_t*)&(cfir_inspect->dp_cfg.scalar_i[dp][j]), 2); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_Q_COMPLEX_SCALAR_1_INFO(regmap_base_addr, 2), (uint8_t*)&(cfir_inspect->dp_cfg.scalar_q[dp][j]), 2); + ADI_APOLLO_ERROR_RETURN(err); + + /* gain_pgm */ + err = adi_apollo_hal_bf_get(device, BF_CFIR_GAIN2_1_INFO(regmap_base_addr), (uint8_t*)&(cfir_inspect->dp_cfg.cfir_gain_dB[dp][j]), 1); + ADI_APOLLO_ERROR_RETURN(err); + + /* sparse_mem_sel_pgm */ + err = adi_apollo_hal_bf_get(device, BF_DPATH2_MEM_SEL0_1_INFO(regmap_base_addr), (uint8_t*)&(cfir_inspect->sparse_mem[dp][j][0]), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_DPATH2_MEM_SEL1_1_INFO(regmap_base_addr), (uint8_t*)&(cfir_inspect->sparse_mem[dp][j][1]), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_DPATH2_MEM_SEL2_1_INFO(regmap_base_addr), (uint8_t*)&(cfir_inspect->sparse_mem[dp][j][2]), 1); + ADI_APOLLO_ERROR_RETURN(err); + break; + case 3: + for (k = 0; k < ADI_APOLLO_CFIR_COEFF_NUM; k++) { + err = adi_apollo_hal_bf_get(device, BF_I_COEFF_3_1_INFO(regmap_coeff_base_addr, k), (uint8_t*)&(cfir_inspect->dp_cfg.coeffs_i[dp][j][k]), 2); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_Q_COEFF_3_1_INFO(regmap_coeff_base_addr, k), (uint8_t*)&(cfir_inspect->dp_cfg.coeffs_q[dp][j][k]), 2); + ADI_APOLLO_ERROR_RETURN(err); + + /* sparse_coeff_sel_pgm */ + err = adi_apollo_hal_bf_get(device, BF_COEFF_SEL_3_1_INFO(regmap_coeff_base_addr, k), (uint8_t*)&(cfir_inspect->sparse_coeff[dp][j][k]), 2); + ADI_APOLLO_ERROR_RETURN(err); + } + err = adi_apollo_hal_bf_get(device, BF_I_COMPLEX_SCALAR_1_INFO(regmap_base_addr, 3), (uint8_t*)&(cfir_inspect->dp_cfg.scalar_i[dp][j]), 2); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_Q_COMPLEX_SCALAR_1_INFO(regmap_base_addr, 3), (uint8_t*)&(cfir_inspect->dp_cfg.scalar_q[dp][j]), 2); + ADI_APOLLO_ERROR_RETURN(err); + + /* gain_pgm */ + err = adi_apollo_hal_bf_get(device, BF_CFIR_GAIN3_1_INFO(regmap_base_addr), (uint8_t*)&(cfir_inspect->dp_cfg.cfir_gain_dB[dp][j]), 1); + ADI_APOLLO_ERROR_RETURN(err); + + /* sparse_mem_sel_pgm */ + err = adi_apollo_hal_bf_get(device, BF_DPATH3_MEM_SEL0_1_INFO(regmap_base_addr), (uint8_t*)&(cfir_inspect->sparse_mem[dp][j][0]), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_DPATH3_MEM_SEL1_1_INFO(regmap_base_addr), (uint8_t*)&(cfir_inspect->sparse_mem[dp][j][1]), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_DPATH3_MEM_SEL2_1_INFO(regmap_base_addr), (uint8_t*)&(cfir_inspect->sparse_mem[dp][j][2]), 1); + ADI_APOLLO_ERROR_RETURN(err); + break; + } + } else { /* profile #2 */ + switch (j) { + case 0: + for (k = 0; k < ADI_APOLLO_CFIR_COEFF_NUM; k++) { + err = adi_apollo_hal_bf_get(device, BF_I_COEFF_0_2_INFO(regmap_coeff_base_addr, k), (uint8_t*)&(cfir_inspect->dp_cfg.coeffs_i[dp][j][k]), 2); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_Q_COEFF_0_2_INFO(regmap_coeff_base_addr, k), (uint8_t*)&(cfir_inspect->dp_cfg.coeffs_q[dp][j][k]), 2); + ADI_APOLLO_ERROR_RETURN(err); + + /* sparse_coeff_sel_pgm */ + err = adi_apollo_hal_bf_get(device, BF_COEFF_SEL_0_2_INFO(regmap_coeff_base_addr, k), (uint8_t*)&(cfir_inspect->sparse_coeff[dp][j][k]), 2); + ADI_APOLLO_ERROR_RETURN(err); + } + err = adi_apollo_hal_bf_get(device, BF_I_COMPLEX_SCALAR_2_INFO(regmap_base_addr, 0), (uint8_t*)&(cfir_inspect->dp_cfg.scalar_i[dp][j]), 2); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_Q_COMPLEX_SCALAR_2_INFO(regmap_base_addr, 0), (uint8_t*)&(cfir_inspect->dp_cfg.scalar_q[dp][j]), 2); + ADI_APOLLO_ERROR_RETURN(err); + + /* gain_pgm */ + err = adi_apollo_hal_bf_get(device, BF_CFIR_GAIN0_2_INFO(regmap_base_addr), (uint8_t*)&(cfir_inspect->dp_cfg.cfir_gain_dB[dp][j]), 1); + ADI_APOLLO_ERROR_RETURN(err); + + /* sparse_mem_sel_pgm */ + err = adi_apollo_hal_bf_get(device, BF_DPATH0_MEM_SEL0_2_INFO(regmap_base_addr), (uint8_t*)&(cfir_inspect->sparse_mem[dp][j][0]), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_DPATH0_MEM_SEL1_2_INFO(regmap_base_addr), (uint8_t*)&(cfir_inspect->sparse_mem[dp][j][1]), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_DPATH0_MEM_SEL2_2_INFO(regmap_base_addr), (uint8_t*)&(cfir_inspect->sparse_mem[dp][j][2]), 1); + ADI_APOLLO_ERROR_RETURN(err); + break; + + case 1: + for (k = 0; k < ADI_APOLLO_CFIR_COEFF_NUM; k++) { + err = adi_apollo_hal_bf_get(device, BF_I_COEFF_1_2_INFO(regmap_coeff_base_addr, k), (uint8_t*)&(cfir_inspect->dp_cfg.coeffs_i[dp][j][k]), 2); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_Q_COEFF_1_2_INFO(regmap_coeff_base_addr, k), (uint8_t*)&(cfir_inspect->dp_cfg.coeffs_q[dp][j][k]), 2); + ADI_APOLLO_ERROR_RETURN(err); + + /* sparse_coeff_sel_pgm */ + err = adi_apollo_hal_bf_get(device, BF_COEFF_SEL_1_2_INFO(regmap_coeff_base_addr, k), (uint8_t*)&(cfir_inspect->sparse_coeff[dp][j][k]), 2); + ADI_APOLLO_ERROR_RETURN(err); + } + err = adi_apollo_hal_bf_get(device, BF_I_COMPLEX_SCALAR_2_INFO(regmap_base_addr, 1), (uint8_t*)&(cfir_inspect->dp_cfg.scalar_i[dp][j]), 2); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_Q_COMPLEX_SCALAR_2_INFO(regmap_base_addr, 1), (uint8_t*)&(cfir_inspect->dp_cfg.scalar_q[dp][j]), 2); + ADI_APOLLO_ERROR_RETURN(err); + + /* gain_pgm */ + err = adi_apollo_hal_bf_get(device, BF_CFIR_GAIN1_2_INFO(regmap_base_addr), (uint8_t*)&(cfir_inspect->dp_cfg.cfir_gain_dB[dp][j]), 1); + ADI_APOLLO_ERROR_RETURN(err); + + /* sparse_mem_sel_pgm */ + err = adi_apollo_hal_bf_get(device, BF_DPATH1_MEM_SEL0_2_INFO(regmap_base_addr), (uint8_t*)&(cfir_inspect->sparse_mem[dp][j][0]), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_DPATH1_MEM_SEL1_2_INFO(regmap_base_addr), (uint8_t*)&(cfir_inspect->sparse_mem[dp][j][1]), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_DPATH1_MEM_SEL2_2_INFO(regmap_base_addr), (uint8_t*)&(cfir_inspect->sparse_mem[dp][j][2]), 1); + ADI_APOLLO_ERROR_RETURN(err); + break; + + case 2: + for (k = 0; k < ADI_APOLLO_CFIR_COEFF_NUM; k++) { + err = adi_apollo_hal_bf_get(device, BF_I_COEFF_2_2_INFO(regmap_coeff_base_addr, k), (uint8_t*)&(cfir_inspect->dp_cfg.coeffs_i[dp][j][k]), 2); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_Q_COEFF_2_2_INFO(regmap_coeff_base_addr, k), (uint8_t*)&(cfir_inspect->dp_cfg.coeffs_q[dp][j][k]), 2); + ADI_APOLLO_ERROR_RETURN(err); + + /* sparse_coeff_sel_pgm */ + err = adi_apollo_hal_bf_get(device, BF_COEFF_SEL_2_2_INFO(regmap_coeff_base_addr, k), (uint8_t*)&(cfir_inspect->sparse_coeff[dp][j][k]), 2); + ADI_APOLLO_ERROR_RETURN(err); + } + err = adi_apollo_hal_bf_get(device, BF_I_COMPLEX_SCALAR_2_INFO(regmap_base_addr, 2), (uint8_t*)&(cfir_inspect->dp_cfg.scalar_i[dp][j]), 2); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_Q_COMPLEX_SCALAR_2_INFO(regmap_base_addr, 2), (uint8_t*)&(cfir_inspect->dp_cfg.scalar_q[dp][j]), 2); + ADI_APOLLO_ERROR_RETURN(err); + + /* gain_pgm */ + err = adi_apollo_hal_bf_get(device, BF_CFIR_GAIN2_2_INFO(regmap_base_addr), (uint8_t*)&(cfir_inspect->dp_cfg.cfir_gain_dB[dp][j]), 1); + ADI_APOLLO_ERROR_RETURN(err); + + /* sparse_mem_sel_pgm */ + err = adi_apollo_hal_bf_get(device, BF_DPATH2_MEM_SEL0_2_INFO(regmap_base_addr), (uint8_t*)&(cfir_inspect->sparse_mem[dp][j][0]), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_DPATH2_MEM_SEL1_2_INFO(regmap_base_addr), (uint8_t*)&(cfir_inspect->sparse_mem[dp][j][1]), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_DPATH2_MEM_SEL2_2_INFO(regmap_base_addr), (uint8_t*)&(cfir_inspect->sparse_mem[dp][j][2]), 1); + ADI_APOLLO_ERROR_RETURN(err); + break; + + case 3: + for (k = 0; k < ADI_APOLLO_CFIR_COEFF_NUM; k++) { + err = adi_apollo_hal_bf_get(device, BF_I_COEFF_3_2_INFO(regmap_coeff_base_addr, k), (uint8_t*)&(cfir_inspect->dp_cfg.coeffs_i[dp][j][k]), 2); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_Q_COEFF_3_2_INFO(regmap_coeff_base_addr, k), (uint8_t*)&(cfir_inspect->dp_cfg.coeffs_q[dp][j][k]), 2); + ADI_APOLLO_ERROR_RETURN(err); + + /* sparse_coeff_sel_pgm */ + err = adi_apollo_hal_bf_get(device, BF_COEFF_SEL_3_2_INFO(regmap_coeff_base_addr, k), (uint8_t*)&(cfir_inspect->sparse_coeff[dp][j][k]), 2); + ADI_APOLLO_ERROR_RETURN(err); + } + err = adi_apollo_hal_bf_get(device, BF_I_COMPLEX_SCALAR_2_INFO(regmap_base_addr, 3), (uint8_t*)&(cfir_inspect->dp_cfg.scalar_i[dp][j]), 2); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_Q_COMPLEX_SCALAR_2_INFO(regmap_base_addr, 3), (uint8_t*)&(cfir_inspect->dp_cfg.scalar_q[dp][j]), 2); + ADI_APOLLO_ERROR_RETURN(err); + + /* gain_pgm */ + err = adi_apollo_hal_bf_get(device, BF_CFIR_GAIN3_2_INFO(regmap_base_addr), (uint8_t*)&(cfir_inspect->dp_cfg.cfir_gain_dB[dp][j]), 1); + ADI_APOLLO_ERROR_RETURN(err); + + /* sparse_mem_sel_pgm */ + err = adi_apollo_hal_bf_get(device, BF_DPATH3_MEM_SEL0_2_INFO(regmap_base_addr), (uint8_t*)&(cfir_inspect->sparse_mem[dp][j][0]), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_DPATH3_MEM_SEL1_2_INFO(regmap_base_addr), (uint8_t*)&(cfir_inspect->sparse_mem[dp][j][1]), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_DPATH3_MEM_SEL2_2_INFO(regmap_base_addr), (uint8_t*)&(cfir_inspect->sparse_mem[dp][j][2]), 1); + ADI_APOLLO_ERROR_RETURN(err); + break; + } + } + } + } + } + } + + + + return API_CMS_ERROR_OK; +} + +uint32_t calc_cfir_base(adi_apollo_terminal_e terminal, int32_t cfir_index) +{ + static uint32_t rx_cfir_regmap[ADI_APOLLO_CFIR_NUM] = { + RX_CFIR_TOP_RX_SLICE_0_RX_DIGITAL0, + RX_CFIR_TOP_RX_SLICE_1_RX_DIGITAL0, + RX_CFIR_TOP_RX_SLICE_0_RX_DIGITAL1, + RX_CFIR_TOP_RX_SLICE_1_RX_DIGITAL1 + }; + static uint32_t tx_cfir_regmap[ADI_APOLLO_CFIR_NUM] = { + TX_CFIR_TOP_TX_SLICE_0_TX_DIGITAL0, + TX_CFIR_TOP_TX_SLICE_1_TX_DIGITAL0, + TX_CFIR_TOP_TX_SLICE_0_TX_DIGITAL1, + TX_CFIR_TOP_TX_SLICE_1_TX_DIGITAL1, + }; + if (terminal == ADI_APOLLO_RX) + return rx_cfir_regmap[cfir_index]; + else + return tx_cfir_regmap[cfir_index]; +} + +uint32_t calc_cfir_coeff_base(adi_apollo_terminal_e terminal, int32_t cfir_index) +{ + static uint32_t rx_cfir_coeff_regmap[ADI_APOLLO_CFIR_NUM] = { + RX_CFIR_COEFF_RX_SLICE_0_RX_DIGITAL0, + RX_CFIR_COEFF_RX_SLICE_1_RX_DIGITAL0, + RX_CFIR_COEFF_RX_SLICE_0_RX_DIGITAL1, + RX_CFIR_COEFF_RX_SLICE_1_RX_DIGITAL1, + }; + static uint32_t tx_cfir_coeff_regmap[ADI_APOLLO_CFIR_NUM] = { + TX_CFIR_COEFF_TX_SLICE_0_TX_DIGITAL0, + TX_CFIR_COEFF_TX_SLICE_1_TX_DIGITAL0, + TX_CFIR_COEFF_TX_SLICE_0_TX_DIGITAL1, + TX_CFIR_COEFF_TX_SLICE_1_TX_DIGITAL1, + }; + if (terminal == ADI_APOLLO_RX) + return rx_cfir_coeff_regmap[cfir_index]; + else + return tx_cfir_coeff_regmap[cfir_index]; +} +/*! @} */ \ No newline at end of file diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_cfir_local.h b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_cfir_local.h new file mode 100644 index 00000000000000..8f130631849af6 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_cfir_local.h @@ -0,0 +1,37 @@ +/*! + * \brief CFIR local defines and prototypes + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_CFIR + * @{ + */ +#ifndef __ADI_APOLLO_CFIR_LOCAL_H__ +#define __ADI_APOLLO_CFIR_LOCAL_H__ + +/*============= I N C L U D E S ============*/ + +/*============= D E F I N E S ==============*/ + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +uint32_t calc_cfir_base(adi_apollo_terminal_e terminal, int32_t cfir_index); +uint32_t calc_cfir_coeff_base(adi_apollo_terminal_e terminal, int32_t cfir_index); + +#ifndef CLIENT_IGNORE +#endif /* CLIENT_IGNORE*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_CFIR_LOCAL_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_clk_mcs.c b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_clk_mcs.c new file mode 100644 index 00000000000000..07d31eb87423cb --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_clk_mcs.c @@ -0,0 +1,1181 @@ +/*! + * \brief Clock and multi chip sync API implementation + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_CLK_MCS + * @{ + */ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_config.h" +#include "adi_apollo_hal.h" + +#include "adi_apollo_clk_mcs.h" +#include "adi_apollo_bf_rx_datin.h" +#include "adi_apollo_bf_tx_hsdout.h" +#include "adi_apollo_bf_mcs_sync.h" +#include "adi_apollo_bf_mcs_tdc.h" +#include "adi_apollo_bf_rtclk_gen.h" +#include "adi_apollo_bf_custom.h" + +static uint32_t calc_rx_datin_base(int32_t idx); +static uint32_t calc_tx_hsdout_base(int32_t idx); +static uint32_t calc_mcs_tdc_top_dual_clk_base(int32_t idx); +static void get_adc_fifo_offsets(adi_apollo_data_fifo_conv_clk_ratio_e clk_ratio, uint8_t *wr_offset, uint8_t *rd_offset); +static void get_dac_fifo_offsets(adi_apollo_data_fifo_conv_clk_ratio_e clk_ratio, uint8_t *wr_offset, uint8_t *rd_offset); +static int32_t mask_sync(adi_apollo_device_t *device, uint32_t reg, uint32_t info, int32_t filter, uint64_t value); +static int32_t rxtxlink_sync(adi_apollo_device_t *device, adi_apollo_sync_mask_rxtx_link_e rxtx_link_mask); +static int32_t clk_pd_status_get(adi_apollo_device_t *device, int32_t top_base, adi_apollo_clk_input_power_status_e *status); + + +#define IS_DUAL_CLK(device) (device->dev_info.is_dual_clk) + +/*==================== P U B L I C A P I C O D E ====================*/ + +int32_t adi_apollo_clk_mcs_rx_data_fifo_configure(adi_apollo_device_t *device, const uint16_t adcs, adi_apollo_data_fifo_config_t *fifo_config) +{ + int32_t err; + uint8_t i; + uint16_t adc; + uint32_t regmap_base_addr; + uint8_t lat_wr; + uint8_t lat_rd; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(fifo_config); + ADI_APOLLO_INVALID_PARAM_RETURN(fifo_config->enable > 1); + ADI_APOLLO_INVALID_PARAM_RETURN(fifo_config->mode > ADI_APOLLO_DATA_FIFO_MODE_FORCE_ON); + if (fifo_config->lat_override) { + ADI_APOLLO_INVALID_PARAM_RETURN(fifo_config->lat_wr_offset > 0xF); + ADI_APOLLO_INVALID_PARAM_RETURN(fifo_config->lat_rd_offset > 0x7); + } + + for(i = 0; i < ADI_APOLLO_ADC_NUM; i ++) { + adc = adcs & (ADI_APOLLO_ADC_A0 << i); + if (adc > 0) { + regmap_base_addr = calc_rx_datin_base(i); + + /* Enable */ + err = adi_apollo_hal_bf_set(device, BF_DFIFO_EN_RX_DATIN_INFO(regmap_base_addr), fifo_config->enable); + ADI_APOLLO_ERROR_RETURN(err); + + /* Mode */ + err = adi_apollo_hal_bf_set(device, BF_LAT_PGM_MODE_RX_DATIN_INFO(regmap_base_addr), fifo_config->mode); + ADI_APOLLO_ERROR_RETURN(err); + + /* Offsets - Use defaults unless override specified */ + if (fifo_config->lat_override) { + lat_wr = fifo_config->lat_wr_offset; + lat_rd = fifo_config->lat_rd_offset; + } else { + get_adc_fifo_offsets(fifo_config->conv_clk_ratio, &lat_wr, &lat_rd); + } + + err = adi_apollo_hal_bf_set(device, BF_LAT_WR_SPI_RX_DATIN_INFO(regmap_base_addr), lat_wr); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_LAT_RD_SPI_RX_DATIN_INFO(regmap_base_addr), lat_rd); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_clk_mcs_rx_data_fifo_enable(adi_apollo_device_t *device, const uint16_t adcs, uint8_t enable) +{ + int32_t err; + uint8_t i; + uint16_t adc; + uint32_t regmap_base_addr; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(enable > 1); + + for(i = 0; i < ADI_APOLLO_ADC_NUM; i ++) { + adc = adcs & (ADI_APOLLO_ADC_A0 << i); + if (adc > 0) { + regmap_base_addr = calc_rx_datin_base(i); + + err = adi_apollo_hal_bf_set(device, BF_DFIFO_EN_RX_DATIN_INFO(regmap_base_addr), enable); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_clk_mcs_rx_data_fifo_offset_set(adi_apollo_device_t *device, const uint16_t adcs, uint8_t wr_offset, uint8_t rd_offset) +{ + int32_t err; + uint8_t i; + uint16_t adc; + uint32_t regmap_base_addr; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(wr_offset > 0xF); + ADI_APOLLO_INVALID_PARAM_RETURN(rd_offset > 0x7); + + for(i = 0; i < ADI_APOLLO_ADC_NUM; i ++) { + adc = adcs & (ADI_APOLLO_ADC_A0 << i); + if (adc > 0) { + regmap_base_addr = calc_rx_datin_base(i); + + err = adi_apollo_hal_bf_set(device, BF_LAT_WR_SPI_RX_DATIN_INFO(regmap_base_addr), wr_offset); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_LAT_RD_SPI_RX_DATIN_INFO(regmap_base_addr), rd_offset); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_clk_mcs_rx_data_fifo_mode_set(adi_apollo_device_t *device, const uint16_t adcs, adi_apollo_data_fifo_mode_e mode) +{ + int32_t err; + uint8_t i; + uint16_t adc; + uint32_t regmap_base_addr; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(mode > ADI_APOLLO_DATA_FIFO_MODE_FORCE_ON); + + for(i = 0; i < ADI_APOLLO_ADC_NUM; i ++) { + adc = adcs & (ADI_APOLLO_ADC_A0 << i); + if (adc > 0) { + regmap_base_addr = calc_rx_datin_base(i); + + err = adi_apollo_hal_bf_set(device, BF_LAT_PGM_MODE_RX_DATIN_INFO(regmap_base_addr), mode); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_clk_mcs_tx_data_fifo_configure(adi_apollo_device_t *device, const uint16_t dacs, adi_apollo_data_fifo_config_t *fifo_config) +{ + int32_t err; + uint8_t i; + uint16_t dac; + uint32_t regmap_base_addr; + uint8_t lat_wr; + uint8_t lat_rd; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(fifo_config); + + for(i = 0; i < ADI_APOLLO_DAC_NUM; i ++) { + dac = dacs & (ADI_APOLLO_DAC_A0 << i); + if (dac > 0) { + regmap_base_addr = calc_tx_hsdout_base(i); + + /* Enable */ + err = adi_apollo_hal_bf_set(device, BF_DFIFO_EN_TX_HSDOUT_INFO(regmap_base_addr), fifo_config->enable); + ADI_APOLLO_ERROR_RETURN(err); + + /* Mode */ + err = adi_apollo_hal_bf_set(device, BF_LAT_PGM_MODE_TX_HSDOUT_INFO(regmap_base_addr), fifo_config->mode); + ADI_APOLLO_ERROR_RETURN(err); + + /* Offsets - Use defaults unless override specified */ + if (fifo_config->lat_override) { + lat_wr = fifo_config->lat_wr_offset; + lat_rd = fifo_config->lat_rd_offset; + } else { + get_dac_fifo_offsets(fifo_config->conv_clk_ratio, &lat_wr, &lat_rd); + } + + err = adi_apollo_hal_bf_set(device, BF_LAT_WR_SPI_TX_HSDOUT_INFO(regmap_base_addr), lat_wr); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_LAT_RD_SPI_TX_HSDOUT_INFO(regmap_base_addr), lat_rd); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_clk_mcs_tx_data_fifo_enable(adi_apollo_device_t *device, const uint16_t dacs, uint8_t enable) +{ + int32_t err; + uint8_t i; + uint16_t dac; + uint32_t regmap_base_addr; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + for(i = 0; i < ADI_APOLLO_DAC_NUM; i ++) { + dac = dacs & (ADI_APOLLO_DAC_A0 << i); + if (dac > 0) { + regmap_base_addr = calc_tx_hsdout_base(i); + + err = adi_apollo_hal_bf_set(device, BF_DFIFO_EN_TX_HSDOUT_INFO(regmap_base_addr), enable); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_clk_mcs_tx_data_fifo_offset_set(adi_apollo_device_t *device, const uint16_t dacs, uint8_t wr_offset, uint8_t rd_offset) +{ + int32_t err; + uint8_t i; + uint16_t dac; + uint32_t regmap_base_addr; + + for(i = 0; i < ADI_APOLLO_DAC_NUM; i ++) { + dac = dacs & (ADI_APOLLO_DAC_A0 << i); + if (dac > 0) { + regmap_base_addr = calc_tx_hsdout_base(i); + + err = adi_apollo_hal_bf_set(device, BF_LAT_WR_SPI_TX_HSDOUT_INFO(regmap_base_addr), wr_offset); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_LAT_RD_SPI_TX_HSDOUT_INFO(regmap_base_addr), rd_offset); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_clk_mcs_tx_data_fifo_mode_set(adi_apollo_device_t *device, const uint16_t dacs, adi_apollo_data_fifo_mode_e mode) +{ + int32_t err; + uint8_t i; + uint16_t dac; + uint32_t regmap_base_addr; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + for(i = 0; i < ADI_APOLLO_DAC_NUM; i ++) { + dac = dacs & (ADI_APOLLO_DAC_A0 << i); + if (dac > 0) { + regmap_base_addr = calc_tx_hsdout_base(i); + + err = adi_apollo_hal_bf_set(device, BF_LAT_PGM_MODE_TX_HSDOUT_INFO(regmap_base_addr), 1); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_clk_mcs_sync_hw_align_set(adi_apollo_device_t *device) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + // Clear Rx-Tx digital mask to be synced + err = adi_apollo_hal_reg_set(device, REG_SYNC_MASK_RXTX_ADDR, ADI_APOLLO_SYNC_MASK_RX_TX_NONE); + ADI_APOLLO_ERROR_RETURN(err); + + // Set Rx-Tx serdes link mask to avoid getting synced + err = adi_apollo_hal_reg_set(device, REG_SYNC_MASK_RXTXLINK_ADDR, ADI_APOLLO_SYNC_MASK_RXTX_LINK_ALL); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_clk_mcs_oneshot_sync(device); + ADI_APOLLO_ERROR_RETURN(err); + + // Clear JTx/JRx link masks + err = adi_apollo_hal_reg_set(device, REG_SYNC_MASK_RXTXLINK_ADDR, ADI_APOLLO_SYNC_MASK_RXTX_LINK_NONE); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_clk_mcs_sync_hw_align_get(adi_apollo_device_t *device, uint8_t *status) +{ + int32_t err; + uint8_t data[2]; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(status); + + *status = 0; + + if (IS_DUAL_CLK(device)) { + err = adi_apollo_hal_bf_get(device, BF_ONESHOT_SYNC_DONE_INFO(MCS_SYNC_MCSTOP1), &data[0], 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_ONESHOT_SYNC_DONE_INFO(MCS_SYNC_MCSTOP2), &data[1], 1); + ADI_APOLLO_ERROR_RETURN(err); + *status = data[0] | (data[1] << 1); + } else { + err = adi_apollo_hal_bf_get(device, BF_ONESHOT_SYNC_DONE_INFO(MCS_SYNC_MCSTOP0), &data[0], 1); + ADI_APOLLO_ERROR_RETURN(err); + *status = data[0]; + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_clk_mcs_sync_only_set(adi_apollo_device_t *device) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + if (IS_DUAL_CLK(device)) { + err = adi_apollo_hal_bf_set(device, BF_DYN_CFG_SYNC_INFO(MCS_SYNC_MCSTOP1), 0x01); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_DYN_CFG_SYNC_INFO(MCS_SYNC_MCSTOP2), 0x01); + ADI_APOLLO_ERROR_RETURN(err); + } else { + err = adi_apollo_hal_bf_set(device, BF_DYN_CFG_SYNC_INFO(MCS_SYNC_MCSTOP0), 0x01); + ADI_APOLLO_ERROR_RETURN(err); + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_clk_mcs_sync_only_get(adi_apollo_device_t *device, uint8_t *status) +{ + int32_t err; + uint8_t data[2]; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(status); + + *status = 0; + + if (IS_DUAL_CLK(device)) { + err = adi_apollo_hal_bf_get(device, BF_DYN_CFG_SYNC_DONE_INFO(MCS_SYNC_MCSTOP1), &data[0], 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_DYN_CFG_SYNC_DONE_INFO(MCS_SYNC_MCSTOP2), &data[1], 1); + ADI_APOLLO_ERROR_RETURN(err); + *status = data[0] | (data[1] << 1); + } else { + err = adi_apollo_hal_bf_get(device, BF_DYN_CFG_SYNC_DONE_INFO(MCS_SYNC_MCSTOP0), &data[0], 1); + ADI_APOLLO_ERROR_RETURN(err); + *status = data[0]; + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_clk_mcs_trig_sync_enable(adi_apollo_device_t *device, uint8_t enable) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + if (IS_DUAL_CLK(device)) { + err = adi_apollo_hal_bf_set(device, BF_TRIGGER_SYNC_INFO(MCS_SYNC_MCSTOP1), enable); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_TRIGGER_SYNC_INFO(MCS_SYNC_MCSTOP2), enable); + ADI_APOLLO_ERROR_RETURN(err); + } else { + err = adi_apollo_hal_bf_set(device, BF_TRIGGER_SYNC_INFO(MCS_SYNC_MCSTOP0), enable); + ADI_APOLLO_ERROR_RETURN(err); + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_clk_mcs_trig_sync_enable_get(adi_apollo_device_t *device, uint8_t *enable) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(enable) + + if (IS_DUAL_CLK(device)) { + err = adi_apollo_hal_bf_get(device, BF_TRIGGER_SYNC_INFO(MCS_SYNC_MCSTOP1), enable, 1); + ADI_APOLLO_ERROR_RETURN(err); + } else { + err = adi_apollo_hal_bf_get(device, BF_TRIGGER_SYNC_INFO(MCS_SYNC_MCSTOP0), enable, 1); + ADI_APOLLO_ERROR_RETURN(err); + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_clk_mcs_trig_reset_dsp_enable(adi_apollo_device_t *device) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + if (IS_DUAL_CLK(device)) { + err = adi_apollo_hal_bf_set(device, BF_SYNCTRL_MAN_INFO(MCS_SYNC_MCSTOP1), 0x00c0); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_SYNCTRL_MAN_INFO(MCS_SYNC_MCSTOP2), 0x00c0); + ADI_APOLLO_ERROR_RETURN(err); + } else { + err = adi_apollo_hal_bf_set(device, BF_SYNCTRL_MAN_INFO(MCS_SYNC_MCSTOP0), 0x00c0); + ADI_APOLLO_ERROR_RETURN(err); + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_clk_mcs_trig_reset_disable(adi_apollo_device_t *device) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + if (IS_DUAL_CLK(device)) { + err = adi_apollo_hal_bf_set(device, BF_SYNCTRL_MAN_INFO(MCS_SYNC_MCSTOP1), 0x0000); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_SYNCTRL_MAN_INFO(MCS_SYNC_MCSTOP2), 0x0000); + ADI_APOLLO_ERROR_RETURN(err); + } else { + err = adi_apollo_hal_bf_set(device, BF_SYNCTRL_MAN_INFO(MCS_SYNC_MCSTOP0), 0x0000); + ADI_APOLLO_ERROR_RETURN(err); + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_clk_mcs_trig_phase_get(adi_apollo_device_t *device, adi_apollo_trig_pin_e trig, uint16_t *phase_0, uint16_t *phase_1) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(phase_0); + ADI_APOLLO_NULL_POINTER_RETURN(phase_1); + ADI_APOLLO_INVALID_PARAM_RETURN(trig >= ADI_APOLLO_TRIG_PIN_NUM); + + *phase_0 = 0; + *phase_1 = 0; + + switch (trig) { + case ADI_APOLLO_TRIG_PIN_A0: + if (IS_DUAL_CLK(device)) { + err = adi_apollo_hal_bf_get(device, BF_TRIG_PHASE_A0_INFO(MCS_SYNC_MCSTOP1), (uint8_t*)phase_0, sizeof(*phase_0)); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_TRIG_PHASE_A0_INFO(MCS_SYNC_MCSTOP2), (uint8_t*)phase_1, sizeof(*phase_1)); + ADI_APOLLO_ERROR_RETURN(err); + } + else { + err = adi_apollo_hal_bf_get(device, BF_TRIG_PHASE_A0_INFO(MCS_SYNC_MCSTOP0), (uint8_t*)phase_0, sizeof(*phase_0)); + ADI_APOLLO_ERROR_RETURN(err); + } + break; + + case ADI_APOLLO_TRIG_PIN_A1: + if (IS_DUAL_CLK(device)) { + err = adi_apollo_hal_bf_get(device, BF_TRIG_PHASE_A1_INFO(MCS_SYNC_MCSTOP1), (uint8_t*)phase_0, sizeof(*phase_0)); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_TRIG_PHASE_A1_INFO(MCS_SYNC_MCSTOP2), (uint8_t*)phase_1, sizeof(*phase_1)); + ADI_APOLLO_ERROR_RETURN(err); + } + else { + err = adi_apollo_hal_bf_get(device, BF_TRIG_PHASE_A1_INFO(MCS_SYNC_MCSTOP0), (uint8_t*)phase_0, sizeof(*phase_0)); + ADI_APOLLO_ERROR_RETURN(err); + } + break; + + case ADI_APOLLO_TRIG_PIN_B0: + if (IS_DUAL_CLK(device)) { + err = adi_apollo_hal_bf_get(device, BF_TRIG_PHASE_B0_INFO(MCS_SYNC_MCSTOP1), (uint8_t*)phase_0, sizeof(*phase_0)); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_TRIG_PHASE_B0_INFO(MCS_SYNC_MCSTOP2), (uint8_t*)phase_1, sizeof(*phase_1)); + ADI_APOLLO_ERROR_RETURN(err); + } + else { + err = adi_apollo_hal_bf_get(device, BF_TRIG_PHASE_B0_INFO(MCS_SYNC_MCSTOP0), (uint8_t*)phase_0, sizeof(*phase_0)); + ADI_APOLLO_ERROR_RETURN(err); + } + break; + + case ADI_APOLLO_TRIG_PIN_B1: + if (IS_DUAL_CLK(device)) { + err = adi_apollo_hal_bf_get(device, BF_TRIG_PHASE_B1_INFO(MCS_SYNC_MCSTOP1), (uint8_t*)phase_0, sizeof(*phase_0)); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_TRIG_PHASE_B1_INFO(MCS_SYNC_MCSTOP2), (uint8_t*)phase_1, sizeof(*phase_1)); + ADI_APOLLO_ERROR_RETURN(err); + } + else { + err = adi_apollo_hal_bf_get(device, BF_TRIG_PHASE_B1_INFO(MCS_SYNC_MCSTOP0), (uint8_t*)phase_0, sizeof(*phase_0)); + ADI_APOLLO_ERROR_RETURN(err); + } + break; + + default: + return API_CMS_ERROR_INVALID_PARAM; + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_clk_mcs_dig_path_reset_mask_set(adi_apollo_device_t *device, adi_apollo_sync_mask_rxtx_e rxtx_mask) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_hal_bf_set(device, BF_SYNC_MASK_RXTX_INFO, ~rxtx_mask); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_clk_mcs_dig_path_reset_disable(adi_apollo_device_t *device) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_hal_bf_set(device, BF_SYNC_MASK_RXTX_INFO, ADI_APOLLO_SYNC_MASK_RX_TX_ALL); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_clk_mcs_rxtx_link_reset_disable(adi_apollo_device_t *device) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_hal_bf_set(device, BF_SYNC_MASK_RXTXLINK_INFO, ADI_APOLLO_SYNC_MASK_RXTX_LINK_ALL); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_clk_mcs_lpbk_fifo_reset_disable(adi_apollo_device_t *device) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_hal_bf_set(device, BF_SYNC_MASK_LPBKFIFO_INFO, ADI_APOLLO_SYNC_MASK_LPBKFIFO_ALL); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + + +int32_t adi_apollo_clk_mcs_oneshot_sync(adi_apollo_device_t *device) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + if (IS_DUAL_CLK(device)) { + err = adi_apollo_hal_bf_set(device, BF_ONESHOT_SYNC_INFO(MCS_SYNC_MCSTOP1), 0x01); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_wait_to_set(device, BF_ONESHOT_SYNC_DONE_INFO(MCS_SYNC_MCSTOP1), 100000, 10); + ADI_APOLLO_LOG_ERROR_RETURN_CODE(err, "EAST oneshot sync bit never set", API_CMS_ERROR_OPERATION_TIMEOUT); + + err = adi_apollo_hal_bf_set(device, BF_ONESHOT_SYNC_INFO(MCS_SYNC_MCSTOP2), 0x01); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_wait_to_set(device, BF_ONESHOT_SYNC_DONE_INFO(MCS_SYNC_MCSTOP2), 100000, 10); + ADI_APOLLO_LOG_ERROR_RETURN_CODE(err, "WEST oneshot sync bit never set", API_CMS_ERROR_OPERATION_TIMEOUT); + } else { + err = adi_apollo_hal_bf_set(device, BF_ONESHOT_SYNC_INFO(MCS_SYNC_MCSTOP0), 0x01); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_wait_to_set(device, BF_ONESHOT_SYNC_DONE_INFO(MCS_SYNC_MCSTOP0), 100000, 10); + ADI_APOLLO_LOG_ERROR_RETURN_CODE(err, "CENTER oneshot sync bit never set", API_CMS_ERROR_OPERATION_TIMEOUT); + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_clk_mcs_dynamic_sync(adi_apollo_device_t *device) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + if (IS_DUAL_CLK(device)) { + err = adi_apollo_hal_bf_set(device, BF_DYN_CFG_SYNC_INFO(MCS_SYNC_MCSTOP1), 0x01); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_wait_to_set(device, BF_DYN_CFG_SYNC_DONE_INFO(MCS_SYNC_MCSTOP1), 100000, 10); + ADI_APOLLO_LOG_ERROR_RETURN_CODE(err, "EAST dynamic sync bit never set", API_CMS_ERROR_OPERATION_TIMEOUT); + + err = adi_apollo_hal_bf_set(device, BF_DYN_CFG_SYNC_INFO(MCS_SYNC_MCSTOP2), 0x01); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_wait_to_set(device, BF_DYN_CFG_SYNC_DONE_INFO(MCS_SYNC_MCSTOP2), 100000, 10); + ADI_APOLLO_LOG_ERROR_RETURN_CODE(err, "WEST dynamic sync bit never set", API_CMS_ERROR_OPERATION_TIMEOUT); + } else { + err = adi_apollo_hal_bf_set(device, BF_DYN_CFG_SYNC_INFO(MCS_SYNC_MCSTOP0), 0x01); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_wait_to_set(device, BF_DYN_CFG_SYNC_DONE_INFO(MCS_SYNC_MCSTOP0), 100000, 10); + ADI_APOLLO_LOG_ERROR_RETURN_CODE(err, "CENTER dynamic sync bit never set", API_CMS_ERROR_OPERATION_TIMEOUT); + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_clk_mcs_man_reconfig_sync(adi_apollo_device_t *device) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + if (IS_DUAL_CLK(device)) { + err = adi_apollo_hal_bf_set(device, BF_MANUAL_SYNC_INFO(MCS_SYNC_MCSTOP1), 0x01); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_wait_to_set(device, BF_MANUAL_SYNC_DONE_INFO(MCS_SYNC_MCSTOP1), 100000, 10); + ADI_APOLLO_LOG_ERROR_RETURN_CODE(err, "EAST manual sync bit never set", API_CMS_ERROR_OPERATION_TIMEOUT); + + err = adi_apollo_hal_bf_set(device, BF_MANUAL_SYNC_INFO(MCS_SYNC_MCSTOP2), 0x01); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_wait_to_set(device, BF_MANUAL_SYNC_DONE_INFO(MCS_SYNC_MCSTOP2), 100000, 10); + ADI_APOLLO_LOG_ERROR_RETURN_CODE(err, "WEST manual sync bit never set", API_CMS_ERROR_OPERATION_TIMEOUT); + } else { + err = adi_apollo_hal_bf_set(device, BF_MANUAL_SYNC_INFO(MCS_SYNC_MCSTOP0), 0x01); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_wait_to_set(device, BF_MANUAL_SYNC_DONE_INFO(MCS_SYNC_MCSTOP0), 100000, 10); + ADI_APOLLO_LOG_ERROR_RETURN_CODE(err, "CENTER manual sync bit never set", API_CMS_ERROR_OPERATION_TIMEOUT); + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_clk_mcs_dyn_sync_rxtxlinks_sequence_run(adi_apollo_device_t *device) +{ + uint32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + // Set Rx-Tx digital root clk mask to avoid them getting re-synced + err = adi_apollo_hal_reg_set(device, REG_SYNC_MASK_RTCLK_ADDR, ADI_APOLLO_SYNC_MASK_RTCLK_DIG_ALL); + ADI_APOLLO_ERROR_RETURN(err); + + // Mask JTx A link 0 & link 1 and perform dynamic sync + err = rxtxlink_sync(device, ADI_APOLLO_SYNC_MASK_JTX_A_LINK0 | ADI_APOLLO_SYNC_MASK_JTX_A_LINK1); + ADI_APOLLO_ERROR_RETURN(err); + + // Mask JTx B link 0 & link 1 and perform dynamic sync + err = rxtxlink_sync(device, ADI_APOLLO_SYNC_MASK_JTX_B_LINK0 | ADI_APOLLO_SYNC_MASK_JTX_B_LINK1); + ADI_APOLLO_ERROR_RETURN(err); + + // Mask JRx A link 0 & link 1 and perform dynamic sync + err = rxtxlink_sync(device, ADI_APOLLO_SYNC_MASK_JRX_A_LINK0 | ADI_APOLLO_SYNC_MASK_JRX_A_LINK1); + ADI_APOLLO_ERROR_RETURN(err); + + // Mask JRx B link 0 & link 1 and perform dynamic sync + err = rxtxlink_sync(device, ADI_APOLLO_SYNC_MASK_JRX_B_LINK0 | ADI_APOLLO_SYNC_MASK_JRX_B_LINK1); + ADI_APOLLO_ERROR_RETURN(err); + + // Clear Rx-Tx digital root clk mask + err = adi_apollo_hal_reg_set(device, REG_SYNC_MASK_RTCLK_ADDR, ADI_APOLLO_SYNC_MASK_RTCLK_NONE); + ADI_APOLLO_ERROR_RETURN(err); + + // Clear JTx/JRx link masks + err = adi_apollo_hal_reg_set(device, REG_SYNC_MASK_RXTXLINK_ADDR, ADI_APOLLO_SYNC_MASK_RXTX_LINK_NONE); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + + + +int32_t adi_apollo_clk_mcs_dyn_sync_sequence_run(adi_apollo_device_t *device) +{ + uint32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + /* Mask Synchronization of ADC and DAC fifos, Rx and Tx digital, JRx and JTx link, and LPBK fifo */ + err = adi_apollo_hal_bf_set(device, BF_SYNC_MASK_ADCFIFO_INFO, ADI_APOLLO_SYNC_MASK_ADCFIFO_ALL); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_SYNC_MASK_DACFIFO_INFO, ADI_APOLLO_SYNC_MASK_DACFIFO_ALL); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_clk_mcs_dig_path_reset_disable(device); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_clk_mcs_rxtx_link_reset_disable(device); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_clk_mcs_lpbk_fifo_reset_disable(device); + ADI_APOLLO_ERROR_RETURN(err); + + /* Synchronize Root Clocks */ + err = adi_apollo_clk_mcs_dynamic_sync(device); + ADI_APOLLO_ERROR_RETURN(err); + + /* + * Allow synchronization of other blocks + * RTCLK and RXTXLINK masks handled inside adi_apollo_clk_mcs_dyn_sync_rxtxlinks_sequence_run() + */ + err = adi_apollo_hal_bf_set(device, BF_SYNC_MASK_ADCFIFO_INFO, ADI_APOLLO_SYNC_MASK_ADCFIFO_NONE); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_SYNC_MASK_DACFIFO_INFO, ADI_APOLLO_SYNC_MASK_DACFIFO_NONE); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_SYNC_MASK_RXTX_INFO, ADI_APOLLO_SYNC_MASK_RX_TX_NONE); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_SYNC_MASK_LPBKFIFO_INFO, ADI_APOLLO_SYNC_MASK_LPBKFIFO_NONE); + ADI_APOLLO_ERROR_RETURN(err); + + /* Staggered Synchronization of JTx and JRx links. */ + err = adi_apollo_clk_mcs_dyn_sync_rxtxlinks_sequence_run(device); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_clk_mcs_subclass_set(adi_apollo_device_t *device, uint32_t subclass) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + if (IS_DUAL_CLK(device)) { + err = adi_apollo_hal_bf_set(device, BF_SUBCLASS_SEL_INFO(MCS_SYNC_MCSTOP1), subclass == 0 ? 0 : 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_SUBCLASS_SEL_INFO(MCS_SYNC_MCSTOP2), subclass == 0 ? 0 : 1); + ADI_APOLLO_ERROR_RETURN(err); + } else { + err = adi_apollo_hal_bf_set(device, BF_SUBCLASS_SEL_INFO(MCS_SYNC_MCSTOP0), subclass == 0 ? 0 : 1); + ADI_APOLLO_ERROR_RETURN(err); + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_clk_mcs_subclass_get(adi_apollo_device_t *device, uint32_t *subclass) +{ + int32_t err; + uint8_t val_e, val_w; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(subclass); + + if (IS_DUAL_CLK(device)) { + err = adi_apollo_hal_bf_get(device, BF_SUBCLASS_SEL_INFO(MCS_SYNC_MCSTOP1), &val_e, sizeof(val_e)); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_SUBCLASS_SEL_INFO(MCS_SYNC_MCSTOP2), &val_w, sizeof(val_w)); + ADI_APOLLO_ERROR_RETURN(err); + + if (val_e != val_w) { + return API_CMS_ERROR_ERROR; + } + + *subclass = val_e; + } else { + err = adi_apollo_hal_bf_get(device, BF_SUBCLASS_SEL_INFO(MCS_SYNC_MCSTOP0), (uint8_t *)subclass, sizeof(*subclass)); + ADI_APOLLO_ERROR_RETURN(err); + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_clk_mcs_internal_sysref_per_get(adi_apollo_device_t *device, uint16_t *sysref_per) +{ + int32_t err; + uint16_t val_e, val_w; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(sysref_per); + + if (IS_DUAL_CLK(device)) { + err = adi_apollo_hal_bf_get(device, BF_INT_SYSREF_PERIOD_INFO(MCS_SYNC_MCSTOP1), (uint8_t *)&val_e, sizeof(val_e)); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_INT_SYSREF_PERIOD_INFO(MCS_SYNC_MCSTOP2), (uint8_t *)&val_w, sizeof(val_w)); + ADI_APOLLO_ERROR_RETURN(err); + + if (val_e != val_w) { + return API_CMS_ERROR_ERROR; + } + + *sysref_per = val_e; + } else { + err = adi_apollo_hal_bf_get(device, BF_INT_SYSREF_PERIOD_INFO(MCS_SYNC_MCSTOP0), (uint8_t *)sysref_per, sizeof(*sysref_per)); + ADI_APOLLO_ERROR_RETURN(err); + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_clk_mcs_sysref_phase_get(adi_apollo_device_t *device, uint32_t *sysref_phase) +{ + int32_t err; + uint32_t val_e, val_w; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(sysref_phase); + + /* generate strobe for sysref phase read */ + if (IS_DUAL_CLK(device)) { + err = adi_apollo_hal_bf_set(device, BF_SYSREF_PHASE_INFO(MCS_SYNC_MCSTOP1), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_SYSREF_PHASE_INFO(MCS_SYNC_MCSTOP1), (uint8_t *)&val_e, sizeof(val_e)); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_SYSREF_PHASE_INFO(MCS_SYNC_MCSTOP2), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_SYSREF_PHASE_INFO(MCS_SYNC_MCSTOP2), (uint8_t *)&val_w, sizeof(val_w)); + ADI_APOLLO_ERROR_RETURN(err); + + if (val_e != val_w) { + return API_CMS_ERROR_ERROR; + } + + *sysref_phase = val_e; + } else { + err = adi_apollo_hal_bf_set(device, BF_SYSREF_PHASE_INFO(MCS_SYNC_MCSTOP0), 1); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_get(device, BF_SYSREF_PHASE_INFO(MCS_SYNC_MCSTOP0), (uint8_t *)sysref_phase, sizeof(*sysref_phase)); + ADI_APOLLO_ERROR_RETURN(err); + } + + return API_CMS_ERROR_OK; +} + + +int32_t adi_apollo_clk_mcs_sysref_count_set(adi_apollo_device_t* device, uint32_t sysref_count) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + if (IS_DUAL_CLK(device)) { + err = adi_apollo_hal_bf_set(device, BF_SYSREF_COUNT_INFO(MCS_SYNC_MCSTOP1), sysref_count); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_SYSREF_COUNT_INFO(MCS_SYNC_MCSTOP2), sysref_count); + ADI_APOLLO_ERROR_RETURN(err); + } else { + err = adi_apollo_hal_bf_set(device, BF_SYSREF_COUNT_INFO(MCS_SYNC_MCSTOP0), sysref_count); + ADI_APOLLO_ERROR_RETURN(err); + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_clk_mcs_sysref_en_set(adi_apollo_device_t* device, uint8_t enable) +{ + + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_hal_bf_set(device, BF_SYSREF_EN_INFO(MCS_TDC_MCSTOP0), enable != 0 ? 1 : 0); + ADI_APOLLO_ERROR_RETURN(err); + + /* Add 50us delay when enabling SYSREF to ensure receiver stability before oneshot sync */ + if (enable != 0) { + err = adi_apollo_hal_delay_us(device, 50); + ADI_APOLLO_ERROR_RETURN(err); + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_clk_mcs_sysref_en_get(adi_apollo_device_t* device, uint8_t* enable) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(enable); + + err = adi_apollo_hal_bf_get(device, BF_SYSREF_EN_INFO(MCS_TDC_MCSTOP0), (uint8_t*)enable, sizeof(*enable)); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_clk_mcs_sysref_internal_term_en_set(adi_apollo_device_t *device, uint8_t enable) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + if (IS_DUAL_CLK(device)) { + err = adi_apollo_hal_bf_set(device, BF_SYSREF_RX_RTERM_PD_INFO(MCS_TDC_MCSTOP1), !enable ? 1 : 0); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_SYSREF_RX_RTERM_PD_INFO(MCS_TDC_MCSTOP2), !enable ? 1 : 0); + ADI_APOLLO_ERROR_RETURN(err); + } else { + err = adi_apollo_hal_bf_set(device, BF_SYSREF_RX_RTERM_PD_INFO(MCS_TDC_MCSTOP0), !enable ? 1 : 0); + ADI_APOLLO_ERROR_RETURN(err); + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_clk_mcs_sync_trig_map(adi_apollo_device_t *device, uint16_t rx_tx_select, adi_apollo_trig_pin_e trig_pin) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(trig_pin > ADI_APOLLO_TRIG_PIN_B1); + + if (rx_tx_select & ADI_APOLLO_RX_DIG_A) { + if (IS_DUAL_CLK(device)) { + err = adi_apollo_hal_bf_set(device, BF_MCS_AB_TRIG_SEL_RX_INFO(MCS_SYNC_MCSTOP1), trig_pin); + ADI_APOLLO_ERROR_RETURN(err); + } else { + err = adi_apollo_hal_bf_set(device, BF_MCS_C_TRIG_SEL_RX_A_INFO(MCS_SYNC_MCSTOP0), trig_pin); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + if (rx_tx_select & ADI_APOLLO_RX_DIG_B) { + if (IS_DUAL_CLK(device)) { + err = adi_apollo_hal_bf_set(device, BF_MCS_AB_TRIG_SEL_RX_INFO(MCS_SYNC_MCSTOP2), trig_pin); + ADI_APOLLO_ERROR_RETURN(err); + } else { + err = adi_apollo_hal_bf_set(device, BF_MCS_C_TRIG_SEL_RX_B_INFO(MCS_SYNC_MCSTOP0), trig_pin); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + if (rx_tx_select & ADI_APOLLO_TX_DIG_A) { + if (IS_DUAL_CLK(device)) { + err = adi_apollo_hal_bf_set(device, BF_MCS_AB_TRIG_SEL_TX_INFO(MCS_SYNC_MCSTOP1), trig_pin); + ADI_APOLLO_ERROR_RETURN(err); + } else { + err = adi_apollo_hal_bf_set(device, BF_MCS_C_TRIG_SEL_TX_A_INFO(MCS_SYNC_MCSTOP0), trig_pin); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + if (rx_tx_select & ADI_APOLLO_TX_DIG_B) { + if (IS_DUAL_CLK(device)) { + err = adi_apollo_hal_bf_set(device, BF_MCS_AB_TRIG_SEL_TX_INFO(MCS_SYNC_MCSTOP2), trig_pin); + ADI_APOLLO_ERROR_RETURN(err); + } else { + err = adi_apollo_hal_bf_set(device, BF_MCS_C_TRIG_SEL_TX_B_INFO(MCS_SYNC_MCSTOP0), trig_pin); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + + + +int32_t adi_apollo_clk_mcs_input_power_status_get(adi_apollo_device_t *device, adi_apollo_clk_input_power_status_e *status_a, adi_apollo_clk_input_power_status_e *status_b) +{ + int32_t err; + + adi_apollo_clk_input_power_status_e *status_arr[2] = {status_a, status_b}; + int32_t top; + uint8_t i; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(status_a); + ADI_APOLLO_NULL_POINTER_RETURN(status_b); + + if (IS_DUAL_CLK(device)) { + for (i = 0; i < ADI_APOLLO_NUM_SIDES; i++) { + top = calc_mcs_tdc_top_dual_clk_base(i); + err = clk_pd_status_get(device, top, status_arr[i]); + ADI_APOLLO_ERROR_RETURN(err); + } + } else { + + *status_b = ADI_APOLLO_CLK_PWR_UNUSED; + + err = clk_pd_status_get(device, MCS_TDC_MCSTOP0, status_a); + ADI_APOLLO_ERROR_RETURN(err); + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_clk_mcs_dig_clk_mask_set(adi_apollo_device_t *device, uint8_t enable) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + // mask off digital clocks from ext trigger reset + err = adi_apollo_hal_reg_set(device, REG_SYNC_MASK_ADCFIFO_ADDR, enable ? 0xF : 0); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_reg_set(device, REG_SYNC_MASK_DACFIFO_ADDR, enable ? 0xF : 0); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_reg_set(device, REG_SYNC_MASK_LPBKFIFO_ADDR, enable ? 0x3 : 0); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_reg_set(device, REG_SYNC_MASK_RTCLK_ADDR, enable ? 0xFF : 0); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_reg_set(device, REG_SYNC_MASK_RXTX_ADDR, enable ? 0xF : 0); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_reg_set(device, REG_SYNC_MASK_RXTXLINK_ADDR, enable ? 0xF : 0); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; + +} + +/*==================== S T A T I C F U N C T I O N S ====================*/ + +static __maybe_unused int32_t clk_pd_status_get(adi_apollo_device_t *device, int32_t top_base, adi_apollo_clk_input_power_status_e *status) +{ + int32_t err; + uint8_t scr, rx; + + /* Toggle clock comparator to get measurement */ + err = adi_apollo_hal_bf_set(device, BF_CK_CKR_PD_COMP_CK_INFO(top_base), 0); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_CK_CKR_PD_COMP_CK_INFO(top_base), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_CK_CKR_PD_COMP_CK_INFO(top_base), 0); + ADI_APOLLO_ERROR_RETURN(err); + + /* Read status bits */ + err = adi_apollo_hal_bf_get(device, BF_CK_CKR_PD_STATUS_RX_INFO(top_base), (uint8_t*)&rx, sizeof(rx)); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_get(device, BF_CK_CKR_PD_STATUS_SCR_INFO(top_base), (uint8_t*)&scr, sizeof(scr)); + ADI_APOLLO_ERROR_RETURN(err); + + if (scr && rx) { + *status = ADI_APOLLO_CLK_PWR_OVERDRIVEN; + } else if (!scr && rx) { + *status = ADI_APOLLO_CLK_PWR_GOOD; + } else if (!scr && !rx) { + *status = ADI_APOLLO_CLK_PWR_UNDERDRIVEN; + } else { + return API_CMS_ERROR_CLK_CKT; + } + return API_CMS_ERROR_OK; +} + +static int32_t rxtxlink_sync(adi_apollo_device_t *device, adi_apollo_sync_mask_rxtx_link_e rxtx_link_mask) +{ + return mask_sync(device, BF_SYNC_MASK_RXTXLINK_INFO, ADI_APOLLO_SYNC_MASK_RXTX_LINK_ALL, (uint64_t)rxtx_link_mask); +} + +static int32_t mask_sync(adi_apollo_device_t *device, uint32_t reg, uint32_t info, int32_t filter, uint64_t value) +{ + uint32_t err; + + err = adi_apollo_hal_bf_set(device, reg, info, filter & ~value); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_clk_mcs_dynamic_sync(device); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_delay_us(device, 50); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +static void get_adc_fifo_offsets(adi_apollo_data_fifo_conv_clk_ratio_e clk_ratio, uint8_t *wr_offset, uint8_t *rd_offset) +{ + uint8_t is_4t4r = 1; + + /* wr_ofst rd_ofst */ + static uint8_t adc_fifo_offsets_4t4r[2][3] = {{0, 0, 0}, {3, 4, 4}}; /* 4t4r ratio offsets: 1:1, 1:2, 1:4 */ + static uint8_t adc_fifo_offsets_8t8r[2][3] = {{0, 0, 0}, {5, 5, 5}}; /* 8t8r ratio offsets: 1:1, 1:2, 1:4 */ + + if (is_4t4r) { + *wr_offset = adc_fifo_offsets_4t4r[0][clk_ratio]; + *rd_offset = adc_fifo_offsets_4t4r[1][clk_ratio]; + } else { + *wr_offset = adc_fifo_offsets_8t8r[0][clk_ratio]; + *rd_offset = adc_fifo_offsets_8t8r[1][clk_ratio]; + } +} + +static void get_dac_fifo_offsets(adi_apollo_data_fifo_conv_clk_ratio_e clk_ratio, uint8_t *wr_offset, uint8_t *rd_offset) +{ + uint8_t is_4t4r = 1; + /* wr_ofst rd_ofst */ + static uint8_t dac_fifo_offsets_4t4r[2][3] = {{0, 0, 0}, {2, 2, 2}}; /* 4t4r ratio offsets: 1:1, 1:2, 1:4 */ + static uint8_t dac_fifo_offsets_8t8r[2][3] = {{3, 2, 2}, {0, 0, 0}}; /* 8t8r ratio offsets: 1:1, 1:2, 1:4 */ + + if (is_4t4r) { + *wr_offset = dac_fifo_offsets_4t4r[0][clk_ratio]; + *rd_offset = dac_fifo_offsets_4t4r[1][clk_ratio]; + } else { + *wr_offset = dac_fifo_offsets_8t8r[0][clk_ratio]; + *rd_offset = dac_fifo_offsets_8t8r[1][clk_ratio]; + } +} + +static uint32_t calc_rx_datin_base(int32_t idx) +{ + static uint32_t rx_datin_regmap[ADI_APOLLO_ADC_NUM] = { + RX_DATIN_RX_SLICE_0_RX_DIGITAL0, /* A0: 4T4R/8T8R */ + RX_DATIN_RX_SLICE_1_RX_DIGITAL0, /* A1: 4T4R/8T8R */ + RX_DATIN_RX_SLICE_0_RX_DIGITAL0, /* A2: 8T8R */ + RX_DATIN_RX_SLICE_1_RX_DIGITAL0, /* A3: 8T8R */ + + RX_DATIN_RX_SLICE_0_RX_DIGITAL1, /* B0: 4T4R/8T8R */ + RX_DATIN_RX_SLICE_1_RX_DIGITAL1, /* B1: 4T4R/8T8R */ + RX_DATIN_RX_SLICE_0_RX_DIGITAL1, /* B2: 8T8R */ + RX_DATIN_RX_SLICE_1_RX_DIGITAL1 /* B3: 8T8R */ + }; + return rx_datin_regmap[idx]; +} + +static __maybe_unused uint32_t calc_mcs_tdc_top_dual_clk_base(int32_t idx) +{ + static uint32_t mcs_tdc_top_regmap[] = { + MCS_TDC_MCSTOP1, /* A */ + MCS_TDC_MCSTOP2 /* B */ + }; + return mcs_tdc_top_regmap[idx]; +} + +uint32_t calc_tx_hsdout_base(int32_t index) +{ + /* + * This table is organized for DAC context usage (fifo, scrambler) of hsdout, + * different from datapath (e.g. inv sinc) + */ + static uint32_t tx_hsdout_regmap[ADI_APOLLO_DAC_NUM] = { + TX_HSDOUT0_TX_SLICE_0_TX_DIGITAL0, /* A0 */ + TX_HSDOUT1_TX_SLICE_0_TX_DIGITAL0, /* A1* */ + TX_HSDOUT0_TX_SLICE_1_TX_DIGITAL0, /* A2* */ + TX_HSDOUT1_TX_SLICE_1_TX_DIGITAL0, /* A3 */ + + TX_HSDOUT0_TX_SLICE_0_TX_DIGITAL1, /* B0 */ + TX_HSDOUT1_TX_SLICE_0_TX_DIGITAL1, /* B1* */ + TX_HSDOUT0_TX_SLICE_1_TX_DIGITAL1, /* B2* */ + TX_HSDOUT1_TX_SLICE_1_TX_DIGITAL1 /* B3 */ + }; + return tx_hsdout_regmap[index]; +} + +/*! @} */ \ No newline at end of file diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_cnco.c b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_cnco.c new file mode 100644 index 00000000000000..432960c95ad8d4 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_cnco.c @@ -0,0 +1,665 @@ +/*! + * \brief CNCO functional block API implementation + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_CNCO + * @{ + */ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_cnco.h" +#include "adi_apollo_nco_local.h" +#include "adi_apollo_private_blk_sel_types.h" + +#include "adi_apollo_bf_txrx_coarse_nco.h" + +#include "adi_apollo_config.h" +#include "adi_apollo_hal.h" + +#include "adi_utils.h" + +static uint8_t profile_sel_to_bf(adi_apollo_nco_profile_sel_mode_e ps); +static int32_t bf_to_nco_profile_sel(adi_apollo_device_t *device, uint32_t regmap_base_addr, adi_apollo_nco_profile_sel_mode_e *ps); +static uint8_t nco_profile_sel_to_profile_sel_mode_bf(adi_apollo_nco_profile_sel_mode_e ps); + +/*==================== P U B L I C A P I C O D E ====================*/ +int32_t adi_apollo_cnco_profile_load(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t cncos, + adi_apollo_nco_profile_word_sel_e word_sel, uint8_t first, uint32_t words[], uint32_t length) +{ + int32_t err; + uint8_t i, j; + adi_apollo_blk_sel_t cnco; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(words); + ADI_APOLLO_INVALID_PARAM_RETURN((first+length) > ADI_APOLLO_CNCO_PROFILE_NUM) + ADI_APOLLO_CNCO_BLK_SEL_MASK(cncos); + + for (i = 0; i < ADI_APOLLO_CNCO_NUM; i++) { + cnco = cncos & (ADI_APOLLO_CNCO_A0 << i); + if (cnco > 0) { + + regmap_base_addr = (terminal == ADI_APOLLO_RX) ? calc_rx_cnco_base(i) : calc_tx_cnco_base(i); + + for(j = first; j < first+length; j++) { + err = adi_apollo_hal_paged_reg_set(device, REG_DRC_PROFILE_UPDATE_CTRL_ADDR(regmap_base_addr), j); // only bf in reg, use wr reg + ADI_APOLLO_ERROR_RETURN(err); + + if (word_sel == ADI_APOLLO_NCO_PROFILE_PHASE_INCREMENT) { + err = adi_apollo_hal_paged_bf_set(device, BF_DRC_PHASE_INC_INFO(regmap_base_addr), words[j-first]); + ADI_APOLLO_ERROR_RETURN(err); + } else { + err = adi_apollo_hal_paged_bf_set(device, BF_DRC_PHASE_OFFSET_INFO(regmap_base_addr), words[j-first]); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + err = adi_apollo_hal_paged_reg_set(device, REG_DRC_PROFILE_UPDATE_CTRL_ADDR(regmap_base_addr), 0); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_cnco_hop_enable(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t cncos, adi_apollo_coarse_nco_hop_t *config) +{ + int32_t err; + uint8_t i; + adi_apollo_blk_sel_t cnco; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(config); + ADI_APOLLO_CNCO_BLK_SEL_MASK(cncos); + + for(i = 0; i < ADI_APOLLO_CNCO_NUM; i ++) { + cnco = cncos & (ADI_APOLLO_CNCO_A0 << i); + if (cnco > 0) { + regmap_base_addr = (terminal == ADI_APOLLO_RX) ? calc_rx_cnco_base(i) : calc_tx_cnco_base(i); + + err = adi_apollo_hal_bf_set(device, BF_DRC_NCO_CHAN_SEL_MODE_INFO(regmap_base_addr), profile_sel_to_bf(config->profile_sel_mode)); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_FREQ_COHRNCE_TXRX_COARSE_NCO_INFO(regmap_base_addr), config->phase_handling); + ADI_APOLLO_ERROR_RETURN(err); + + if ((config->profile_sel_mode >= ADI_APOLLO_NCO_CHAN_SEL_TRIG_AUTO) && + (config->profile_sel_mode <= ADI_APOLLO_NCO_CHAN_SEL_TRIG_GPIO)) { + err = adi_apollo_hal_bf_set(device, BF_PROFILE_SEL_MODE_TXRX_COARSE_NCO_INFO(regmap_base_addr), nco_profile_sel_to_profile_sel_mode_bf(config->profile_sel_mode)); + ADI_APOLLO_ERROR_RETURN(err); + } + + if (config->auto_mode == ADI_APOLLO_NCO_AUTO_HOP_FLIP) { + if(config->low_limit >= config->high_limit){ + return API_CMS_ERROR_INVALID_PARAM; + } + + err = adi_apollo_hal_bf_set(device, BF_AUTO_INC_DECB_TXRX_COARSE_NCO_INFO(regmap_base_addr), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_AUTOFLIP_INCDIR_TXRX_COARSE_NCO_INFO(regmap_base_addr), 1); + ADI_APOLLO_ERROR_RETURN(err); + } else { + err = adi_apollo_hal_bf_set(device, BF_AUTO_INC_DECB_TXRX_COARSE_NCO_INFO(regmap_base_addr), config->auto_mode); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_AUTOFLIP_INCDIR_TXRX_COARSE_NCO_INFO(regmap_base_addr), 0); + ADI_APOLLO_ERROR_RETURN(err); + } + + err = adi_apollo_hal_bf_set(device, BF_HOP_HIGHLIM_INFO(regmap_base_addr), config->high_limit); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_HOP_LOWLIM_INFO(regmap_base_addr), config->low_limit); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_HOP_CTRL_INIT_TXRX_COARSE_NCO_INFO(regmap_base_addr), config->hop_ctrl_init); + ADI_APOLLO_ERROR_RETURN(err); + + if (config->profile_sel_mode == ADI_APOLLO_NCO_CHAN_SEL_TRIG_REGMAP) { + err = adi_apollo_hal_bf_set(device, BF_NEXT_HOP_NUMBER_WR_EN_INFO(regmap_base_addr), config->next_hop_number_wr_en); + ADI_APOLLO_ERROR_RETURN(err); + } + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_cnco_chan_pgm(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t cncos, uint8_t profile_num, adi_apollo_coarse_nco_chan_pgm_t *config) +{ + int32_t err; + uint8_t i; + adi_apollo_blk_sel_t cnco; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(config); + ADI_APOLLO_INVALID_PARAM_RETURN(profile_num > ADI_APOLLO_CNCO_PROFILE_NUM-1); + ADI_APOLLO_CNCO_BLK_SEL_MASK(cncos); + + for(i = 0; i < ADI_APOLLO_CNCO_NUM; i ++) { + cnco = cncos & (ADI_APOLLO_CNCO_A0 << i); + if (cnco > 0) { + regmap_base_addr = (terminal == ADI_APOLLO_RX) ? calc_rx_cnco_base(i) : calc_tx_cnco_base(i); + + /* Select profile to update */ + err = adi_apollo_hal_paged_reg_set(device, REG_DRC_PROFILE_UPDATE_CTRL_ADDR(regmap_base_addr), profile_num); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_DRC_PHASE_INC_INFO(regmap_base_addr), config->drc_phase_inc); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_DRC_PHASE_OFFSET_INFO(regmap_base_addr), config->drc_phase_offset); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_DRC_PHASE_INC_FRAC_A_INFO(regmap_base_addr), config->drc_phase_inc_frac_a); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_DRC_PHASE_INC_FRAC_B_INFO(regmap_base_addr), config->drc_phase_inc_frac_b); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_cnco_pgm(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t cncos, adi_apollo_cnco_pgm_t *config) +{ + int32_t err; + uint8_t i; + adi_apollo_blk_sel_t cnco; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(config); + ADI_APOLLO_CNCO_BLK_SEL_MASK(cncos); + + for(i = 0; i < ADI_APOLLO_CNCO_NUM; i ++) { + cnco = cncos & (ADI_APOLLO_CNCO_A0 << i); + if (cnco > 0) { + regmap_base_addr = (terminal == ADI_APOLLO_RX) ? calc_rx_cnco_base(i) : calc_tx_cnco_base(i); + + err = adi_apollo_hal_bf_set(device, BF_DRC_IF_MODE_TXRX_COARSE_NCO_INFO(regmap_base_addr), config->if_mode); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_DRC_MIXER_SEL_INFO(regmap_base_addr), config->mixer_sel); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_CMPLX_MXR_SCALE_EN_INFO(regmap_base_addr), config->cmplx_mxr_scale_en); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_paged_reg_set(device, REG_DRC_PROFILE_UPDATE_CTRL_ADDR(regmap_base_addr), config->profile_num); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_DRC_NCO_CHAN_SEL_MODE_INFO(regmap_base_addr), profile_sel_to_bf(config->profile_sel_mode)); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_DRC_NCO_REGMAP_CHAN_SEL_INFO(regmap_base_addr), config->profile_num); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_DRC_PHASE_INC_INFO(regmap_base_addr),config->drc_phase_inc); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_DRC_PHASE_OFFSET_INFO(regmap_base_addr),config->drc_phase_offset); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_DRC_PHASE_INC_FRAC_A_INFO(regmap_base_addr), config->drc_phase_inc_frac_a); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_DRC_PHASE_INC_FRAC_B_INFO(regmap_base_addr), config->drc_phase_inc_frac_b); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_MIXER_TEST_MODE_VAL_TXRX_COARSE_NCO_INFO(regmap_base_addr), config->dc_testmode_value); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_COARSE_DRC_EN_INFO(regmap_base_addr), config->drc_en); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_CDRC_CLK_EN_INFO(regmap_base_addr),config->debug_drc_clkoff_n); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_cnco_inspect(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t cnco, adi_apollo_cnco_inspect_t *cnco_inspect) +{ + int32_t err; + uint8_t i, j; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(cnco_inspect); + ADI_APOLLO_INVALID_PARAM_RETURN(adi_api_utils_num_selected(cnco) != 1); + ADI_APOLLO_CNCO_BLK_SEL_MASK(cnco); + + for(i = 0; i < ADI_APOLLO_CNCO_NUM; i ++) { + if ((cnco & (ADI_APOLLO_CNCO_A0 << i)) > 0) { + regmap_base_addr = (terminal == ADI_APOLLO_RX) ? calc_rx_cnco_base(i) : calc_tx_cnco_base(i); + + err = adi_apollo_hal_bf_get(device, BF_AUTO_INC_DECB_TXRX_COARSE_NCO_INFO(regmap_base_addr), (uint8_t *) &(cnco_inspect->dp_cfg.nco_auto_inc_dec), sizeof(cnco_inspect->dp_cfg.nco_auto_inc_dec)); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_get(device, BF_DRC_IF_MODE_TXRX_COARSE_NCO_INFO(regmap_base_addr), (uint8_t *) &(cnco_inspect->dp_cfg.nco_if_mode), sizeof(cnco_inspect->dp_cfg.nco_if_mode)); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_DRC_MIXER_SEL_INFO(regmap_base_addr), (uint8_t *) &(cnco_inspect->dp_cfg.drc_mxr_sel), sizeof(cnco_inspect->dp_cfg.drc_mxr_sel)); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_CMPLX_MXR_SCALE_EN_INFO(regmap_base_addr), (uint8_t *) &(cnco_inspect->dp_cfg.cmplx_mxr_mult_scale_en), sizeof(cnco_inspect->dp_cfg.cmplx_mxr_mult_scale_en)); + ADI_APOLLO_ERROR_RETURN(err); + + err = bf_to_nco_profile_sel(device, regmap_base_addr, &(cnco_inspect->dp_cfg).nco_profile_sel_mode); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_get(device, BF_DRC_PROFILE_UPDATE_INDEX_INFO(regmap_base_addr), &(cnco_inspect->profile_num), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_DRC_NCO_REGMAP_CHAN_SEL_INFO(regmap_base_addr), &(cnco_inspect->active_profile_num), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_DRC_PHASE_INC_INFO(regmap_base_addr), (uint8_t *) (&(cnco_inspect->dp_cfg.nco_phase_inc)), 4); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_DRC_PHASE_OFFSET_INFO(regmap_base_addr), (uint8_t *) (&(cnco_inspect->dp_cfg.nco_phase_offset)), 4); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_DRC_PHASE_INC_FRAC_A_INFO(regmap_base_addr), (uint8_t *) (&(cnco_inspect->dp_cfg.nco_phase_inc_frac_a)), 4); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_DRC_PHASE_INC_FRAC_B_INFO(regmap_base_addr), (uint8_t *) (&(cnco_inspect->dp_cfg.nco_phase_inc_frac_b)), 4); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_get(device, BF_MIXER_TEST_MODE_VAL_TXRX_COARSE_NCO_INFO(regmap_base_addr), (uint8_t *) (&(cnco_inspect->dp_cfg.dc_testmode_value)), 2); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_get(device, BF_COARSE_DRC_EN_INFO(regmap_base_addr), (uint8_t*) &(cnco_inspect->dp_cfg.drc_en), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_CDRC_CLK_EN_INFO(regmap_base_addr), + (uint8_t *) &(cnco_inspect->dp_cfg.debug_cdrc_clkoff_n), sizeof(cnco_inspect->dp_cfg.debug_cdrc_clkoff_n)); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_get(device, BF_DRC_ACTIVE_PHASE_INC_INFO(regmap_base_addr), (uint8_t *) (&(cnco_inspect->active_phase_inc)), 4); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_DRC_ACTIVE_PHASE_OFFSET_INFO(regmap_base_addr), (uint8_t *) (&(cnco_inspect->active_phase_offset)), 4); + ADI_APOLLO_ERROR_RETURN(err) + + err = adi_apollo_hal_bf_get(device, BF_DRC_PHASE_DITHER_EN_INFO(regmap_base_addr), &(cnco_inspect->drc_phase_dither_en), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_DRC_AMP_DITHER_EN_INFO(regmap_base_addr), &(cnco_inspect->drc_amp_dither_en), 1); + ADI_APOLLO_ERROR_RETURN(err); + + for (j = 0; j < ADI_APOLLO_CNCO_PROFILE_NUM; j++) { + err = adi_apollo_hal_paged_reg_set(device, REG_DRC_PROFILE_UPDATE_CTRL_ADDR(regmap_base_addr), j); // only bf in reg, use wr reg + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_get(device, BF_DRC_PHASE_INC_INFO(regmap_base_addr), (uint8_t *) &cnco_inspect->dp_cfg.nco_phase_inc_words[j], 4); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_get(device, BF_DRC_PHASE_OFFSET_INFO(regmap_base_addr), (uint8_t*) &cnco_inspect->dp_cfg.nco_phase_offset_words[j], 4); + ADI_APOLLO_ERROR_RETURN(err); + } + + /* Return REG_DRC_PROFILE_UPDATE_CTRL_ADDR back to original state */ + err = adi_apollo_hal_paged_reg_set(device, REG_DRC_PROFILE_UPDATE_CTRL_ADDR(regmap_base_addr), cnco_inspect->profile_num); + ADI_APOLLO_ERROR_RETURN(err); + + /* Only one inspect per call */ + break; + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_cnco_enable_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t cncos, uint8_t enable) +{ + int32_t err; + uint16_t i; + adi_apollo_blk_sel_t cnco; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_CNCO_BLK_SEL_MASK(cncos); + + for (i = 0; i < ADI_APOLLO_CNCO_NUM; i ++) { + cnco = cncos & (ADI_APOLLO_CNCO_A0 << i); + if (cnco > 0) { + regmap_base_addr = (terminal == ADI_APOLLO_RX) ? calc_rx_cnco_base(i) : calc_tx_cnco_base(i); + + err = adi_apollo_hal_bf_set(device, BF_COARSE_DRC_EN_INFO(regmap_base_addr), enable); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_cnco_mode_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t cncos, adi_apollo_nco_mixer_mode_e mode) +{ + int32_t err; + uint16_t i; + adi_apollo_blk_sel_t cnco; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_CNCO_BLK_SEL_MASK(cncos); + + for (i = 0; i < ADI_APOLLO_CNCO_NUM; i++) { + cnco = cncos & (ADI_APOLLO_CNCO_A0 << i); + if (cnco > 0) { + regmap_base_addr = (terminal == ADI_APOLLO_RX) ? calc_rx_cnco_base(i) : calc_tx_cnco_base(i); + + /* Set reg_map base address for subsequent paged writes */ + err = adi_apollo_hal_paged_base_addr_set(device, regmap_base_addr); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_paged_bf_set(device, BF_DRC_IF_MODE_TXRX_COARSE_NCO_INFO(regmap_base_addr), mode); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_cnco_test_mode_val_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t cncos, uint16_t val) +{ + int32_t err; + uint16_t i; + adi_apollo_blk_sel_t cnco; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_CNCO_BLK_SEL_MASK(cncos); + + for (i = 0; i < ADI_APOLLO_CNCO_NUM; i++) { + cnco = cncos & (ADI_APOLLO_CNCO_A0 << i); + if (cnco > 0) { + regmap_base_addr = (terminal == ADI_APOLLO_RX) ? calc_rx_cnco_base(i) : calc_tx_cnco_base(i); + + err = adi_apollo_hal_bf_set(device, BF_MIXER_TEST_MODE_VAL_TXRX_COARSE_NCO_INFO(regmap_base_addr), val); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_cnco_ftw_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t cncos, uint8_t profile_num, uint8_t active_en, uint32_t ftw) +{ + int32_t err; + uint16_t i; + adi_apollo_blk_sel_t cnco; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_CNCO_BLK_SEL_MASK(cncos); + + for (i = 0; i < ADI_APOLLO_CNCO_NUM; i++) { + cnco = cncos & (ADI_APOLLO_CNCO_A0 << i); + if (cnco > 0) { + regmap_base_addr = (terminal == ADI_APOLLO_RX) ? calc_rx_cnco_base(i) : calc_tx_cnco_base(i); + + /* Set reg_map base address for subsequent paged writes */ + err = adi_apollo_hal_paged_base_addr_set(device, regmap_base_addr); + ADI_APOLLO_ERROR_RETURN(err); + + /* Select profile to update */ + err = adi_apollo_hal_paged_reg_set(device, REG_DRC_PROFILE_UPDATE_CTRL_ADDR(regmap_base_addr), profile_num); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_paged_bf_set(device, BF_DRC_PHASE_INC_INFO(regmap_base_addr), ftw); + ADI_APOLLO_ERROR_RETURN(err); + + if (active_en) { + err = adi_apollo_hal_paged_bf_set(device, BF_DRC_NCO_REGMAP_CHAN_SEL_INFO(regmap_base_addr), profile_num); + ADI_APOLLO_ERROR_RETURN(err); + } + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_cnco_pow_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t cncos, uint8_t profile_num, uint8_t active_en, uint32_t pow) +{ + int32_t err; + uint16_t i; + adi_apollo_blk_sel_t cnco; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_CNCO_BLK_SEL_MASK(cncos); + + for (i = 0; i < ADI_APOLLO_CNCO_NUM; i++) { + cnco = cncos & (ADI_APOLLO_CNCO_A0 << i); + if (cnco > 0) { + regmap_base_addr = (terminal == ADI_APOLLO_RX) ? calc_rx_cnco_base(i) : calc_tx_cnco_base(i); + + /* Select profile to update */ + err = adi_apollo_hal_paged_reg_set(device, REG_DRC_PROFILE_UPDATE_CTRL_ADDR(regmap_base_addr), profile_num); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_DRC_PHASE_OFFSET_INFO(regmap_base_addr), pow); + ADI_APOLLO_ERROR_RETURN(err); + + if (active_en) { + err = adi_apollo_hal_bf_set(device, BF_DRC_NCO_REGMAP_CHAN_SEL_INFO(regmap_base_addr), profile_num); + ADI_APOLLO_ERROR_RETURN(err); + } + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_cnco_mod_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t cncos, uint32_t frac_a, uint32_t frac_b) +{ + int32_t err; + uint16_t i; + adi_apollo_blk_sel_t cnco; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(frac_a >= frac_b && frac_a != 0); + ADI_APOLLO_CNCO_BLK_SEL_MASK(cncos); + + for (i = 0; i < ADI_APOLLO_CNCO_NUM; i++) { + cnco = cncos & (ADI_APOLLO_CNCO_A0 << i); + if (cnco > 0) { + regmap_base_addr = (terminal == ADI_APOLLO_RX) ? calc_rx_cnco_base(i) : calc_tx_cnco_base(i); + + /* Set reg_map base address for subsequent paged writes */ + err = adi_apollo_hal_paged_base_addr_set(device, regmap_base_addr); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_paged_bf_set(device, BF_DRC_PHASE_INC_FRAC_A_INFO(regmap_base_addr), frac_a); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_paged_bf_set(device, BF_DRC_PHASE_INC_FRAC_B_INFO(regmap_base_addr), frac_b); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_paged_bf_set(device, BF_DRC_MOD_NCO_PROFILE_UPDATE_INFO(regmap_base_addr), 0); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_paged_bf_set(device, BF_DRC_MOD_NCO_PROFILE_UPDATE_INFO(regmap_base_addr), 1); + ADI_APOLLO_ERROR_RETURN(err); + + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_cnco_mixer_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t cncos, adi_apollo_drc_mixer_sel_e mixer) +{ + int32_t err; + uint16_t i; + adi_apollo_blk_sel_t cnco; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_CNCO_BLK_SEL_MASK(cncos); + + for (i = 0; i < ADI_APOLLO_CNCO_NUM; i++) { + cnco = cncos & (ADI_APOLLO_CNCO_A0 << i); + if (cnco > 0) { + regmap_base_addr = (terminal == ADI_APOLLO_RX) ? calc_rx_cnco_base(i) : calc_tx_cnco_base(i); + + err = adi_apollo_hal_bf_set(device, BF_DRC_MIXER_SEL_INFO(regmap_base_addr), mixer); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_cnco_next_hop_num_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t cncos, int16_t hop_num) +{ + int32_t err; + uint16_t i; + adi_apollo_blk_sel_t cnco; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(hop_num > ADI_APOLLO_CNCO_PROFILE_NUM-1); + ADI_APOLLO_CNCO_BLK_SEL_MASK(cncos); + + for (i = 0; i < ADI_APOLLO_CNCO_NUM; i++) { + cnco = cncos & (ADI_APOLLO_CNCO_A0 << i); + if (cnco > 0) { + regmap_base_addr = (terminal == ADI_APOLLO_RX) ? calc_rx_cnco_base(i) : calc_tx_cnco_base(i); + + err = adi_apollo_hal_reg_set(device, REG_NEXT_HOP_NUMBER_ADDR(regmap_base_addr), hop_num); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + + +int32_t adi_apollo_cnco_profile_sel_mode_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t cncos, adi_apollo_nco_profile_sel_mode_e profile_sel_mode) +{ + int32_t err; + uint16_t i; + adi_apollo_blk_sel_t cnco; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_CNCO_BLK_SEL_MASK(cncos); + + for (i = 0; i < ADI_APOLLO_CNCO_NUM; i++) { + cnco = cncos & (ADI_APOLLO_CNCO_A0 << i); + if (cnco > 0) { + regmap_base_addr = (terminal == ADI_APOLLO_RX) ? calc_rx_cnco_base(i) : calc_tx_cnco_base(i); + + err = adi_apollo_hal_bf_set(device, BF_DRC_NCO_CHAN_SEL_MODE_INFO(regmap_base_addr), profile_sel_to_bf(profile_sel_mode)); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_cnco_active_profile_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t cncos, uint8_t profile_num) +{ + int32_t err; + uint16_t i; + adi_apollo_blk_sel_t cnco; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(profile_num > ADI_APOLLO_CNCO_PROFILE_NUM-1); + ADI_APOLLO_CNCO_BLK_SEL_MASK(cncos); + + for (i = 0; i < ADI_APOLLO_CNCO_NUM; i++) { + cnco = cncos & (ADI_APOLLO_CNCO_A0 << i); + if (cnco > 0) { + regmap_base_addr = (terminal == ADI_APOLLO_RX) ? calc_rx_cnco_base(i) : calc_tx_cnco_base(i); + + err = adi_apollo_hal_bf_set(device, BF_DRC_NCO_REGMAP_CHAN_SEL_INFO(regmap_base_addr), profile_num); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +uint32_t calc_tx_cnco_base(int32_t idx) +{ + static const uint32_t tx_cnco_regmap[ADI_APOLLO_CNCO_NUM] = { + TX_COARSE_NCO0_TX_SLICE_0_TX_DIGITAL0, + TX_COARSE_NCO0_TX_SLICE_1_TX_DIGITAL0, + TX_COARSE_NCO1_TX_SLICE_0_TX_DIGITAL0, + TX_COARSE_NCO1_TX_SLICE_1_TX_DIGITAL0, + + TX_COARSE_NCO0_TX_SLICE_0_TX_DIGITAL1, + TX_COARSE_NCO0_TX_SLICE_1_TX_DIGITAL1, + TX_COARSE_NCO1_TX_SLICE_0_TX_DIGITAL1, + TX_COARSE_NCO1_TX_SLICE_1_TX_DIGITAL1 + }; + + return tx_cnco_regmap[idx]; +} + +uint32_t calc_rx_cnco_base(int32_t idx) +{ + static uint32_t rx_coarse_nco_regmap[ADI_APOLLO_CNCO_NUM] = { + RX_COARSE_NCO0_RX_SLICE_0_RX_DIGITAL0, RX_COARSE_NCO0_RX_SLICE_1_RX_DIGITAL0, + RX_COARSE_NCO1_RX_SLICE_0_RX_DIGITAL0, RX_COARSE_NCO1_RX_SLICE_1_RX_DIGITAL0, + RX_COARSE_NCO0_RX_SLICE_0_RX_DIGITAL1, RX_COARSE_NCO0_RX_SLICE_1_RX_DIGITAL1, + RX_COARSE_NCO1_RX_SLICE_0_RX_DIGITAL1, RX_COARSE_NCO1_RX_SLICE_1_RX_DIGITAL1 + }; + return rx_coarse_nco_regmap[idx]; +} + +/* Convert generic profile select mode (i.e. used by both cnco and fnco) to cnco specific 'BF_DRC_NCO_CHAN_SEL_MODE_INFO' bf value */ +static uint8_t profile_sel_to_bf(adi_apollo_nco_profile_sel_mode_e ps) +{ + static const uint8_t conv_table[] = { + ADI_APOLLO_CNCO_CHAN_SEL_TRIGGER_BASED, + ADI_APOLLO_CNCO_CHAN_SEL_TRIGGER_BASED, + ADI_APOLLO_CNCO_CHAN_SEL_TRIGGER_BASED, + ADI_APOLLO_CNCO_CHAN_SEL_DIRECT_GPIO, + ADI_APOLLO_CNCO_CHAN_SEL_DIRECT_REGMAP}; + return (conv_table[ps]); +} + +static int32_t bf_to_nco_profile_sel(adi_apollo_device_t *device, uint32_t regmap_base_addr, adi_apollo_nco_profile_sel_mode_e *ps) +{ + int32_t err; + + uint8_t drc_nco_chan_sel_mode; + uint8_t profile_sel_mode; + + err = adi_apollo_hal_bf_get(device, BF_DRC_NCO_CHAN_SEL_MODE_INFO(regmap_base_addr), (uint8_t *)&drc_nco_chan_sel_mode, sizeof(drc_nco_chan_sel_mode)); + ADI_APOLLO_ERROR_RETURN(err); + + if (drc_nco_chan_sel_mode == ADI_APOLLO_CNCO_CHAN_SEL_DIRECT_REGMAP) { + *ps = ADI_APOLLO_NCO_CHAN_SEL_DIRECT_REGMAP; + } else if (drc_nco_chan_sel_mode == ADI_APOLLO_CNCO_CHAN_SEL_DIRECT_GPIO) { + *ps = ADI_APOLLO_NCO_CHAN_SEL_DIRECT_GPIO; + } else if (drc_nco_chan_sel_mode == ADI_APOLLO_CNCO_CHAN_SEL_TRIGGER_BASED) { + err = adi_apollo_hal_bf_get(device, BF_PROFILE_SEL_MODE_TXRX_COARSE_NCO_INFO(regmap_base_addr), (uint8_t *)&profile_sel_mode, sizeof(profile_sel_mode)); + ADI_APOLLO_ERROR_RETURN(err); + + *ps = (adi_apollo_nco_profile_sel_mode_e)profile_sel_mode; + } + + return err; +} + +/* Convert generic profile select mode (i.e. used by both cnco and fnco) to cnco specific 'BF_PROFILE_SEL_MODE_TXRX_COARSE_NCO_INFO' bf value */ +static uint8_t nco_profile_sel_to_profile_sel_mode_bf(adi_apollo_nco_profile_sel_mode_e ps) +{ + static const uint8_t conv_table[] = { + ADI_APOLLO_CNCO_TRIG_PROF_SEL_AUTO, + ADI_APOLLO_CNCO_TRIG_PROF_SEL_REGMAP, + ADI_APOLLO_CNCO_TRIG_PROF_SEL_GPIO}; + return (conv_table[ps]); +} +/*! @} */ \ No newline at end of file diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_dac.c b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_dac.c new file mode 100644 index 00000000000000..20115b7daed78c --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_dac.c @@ -0,0 +1,345 @@ +/*! + * \brief APIs for DAC + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_DAC + * @{ + */ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_dac.h" +#include "adi_apollo_config.h" +#include "adi_apollo_hal.h" +#include "adi_utils.h" +#include "adi_apollo_private_blk_sel_types.h" +#include "adi_apollo_bf_tx_hsdout.h" +#include "adi_apollo_mailbox.h" + + +#define ADI_APOLLO_DAC_DECODER_ENABLE_UINT8 0 /*!< Enable decoder */ +#define ADI_APOLLO_DAC_BIAS_FORCE_STANDBY_EN_UINT8 4 /*!< Bias force standby enable */ +#define ADI_APOLLO_DAC_CLK_DUTYCTRL_OFFSET_PRG_UINT8 5 /*!< ADI_APOLLO_DAC_CLK_TRIM_2 */ +#define ADI_APOLLO_DAC_CLK_PHASECTRL_OFFSET_PRG_UINT8 6 /*!< ADI_APOLLO_DAC_CLK_TRIM_3 */ +#define ADI_APOLLO_DAC_CLK_PHASECTRL_SKEW_PRG_UINT8 7 /*!< ADI_APOLLO_DAC_CLK_TRIM_1 */ + + +static uint32_t calc_tx_hsdout_base(int32_t idx); +static uint8_t calc_dac_trim_param(adi_apollo_dac_clk_trim_e trim_attr); + +int32_t adi_apollo_dac_clk_trim_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t dacs, adi_apollo_dac_clk_trim_e trim_attr, uint8_t trim_val) +{ + int32_t err; + uint8_t i; + adi_apollo_mailbox_cmd_set_ctrl_t set_ctrl_cmd = { + .sys_cal_object_id = APOLLO_CPU_OBJID_IC_DAC_TX, + .ctrl_cmd = CTRL_CMD_PARAM_SET, + .data_buffer[0] = calc_dac_trim_param(trim_attr), + .data_buffer[1] = 0, + .data_buffer[2] = 0, + .data_buffer[3] = 0, + .data_buffer[4] = trim_val, + .data_buffer[5] = 0, + .data_buffer[6] = 0, + .data_buffer[7] = 0, + .length = 8 + }; + adi_apollo_mailbox_resp_set_ctrl_t set_ctrl_resp = {0}; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_CMS_RANGE_CHECK(trim_attr, ADI_APOLLO_DAC_CLK_TRIM_1, ADI_APOLLO_DAC_CLK_TRIM_3); + ADI_APOLLO_DAC_BLK_SEL_MASK(dacs); + + for (i = 0; i < ADI_APOLLO_DAC_NUM; i++) { + if ( (dacs & (ADI_APOLLO_DAC_A0 << i)) > 0 ) { + set_ctrl_cmd.channel_num = i; + + err = adi_apollo_mailbox_set_ctrl(device, &set_ctrl_cmd, &set_ctrl_resp); + if (err != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Error from adi_apollo_mailbox_set_ctrl() %d", err); + return err; + } + if (set_ctrl_resp.status != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Mailbox Response Status Error from adi_apollo_mailbox_set_ctrl() 0x%X", set_ctrl_resp.status); + return API_CMS_ERROR_MAILBOX_RESP_STATUS; + } + adi_apollo_hal_delay_us(device, 100 * 1000); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_dac_clk_trim_get(adi_apollo_device_t *device, adi_apollo_blk_sel_t dacs, adi_apollo_dac_clk_trim_e trim_attr, uint8_t *trim_val) +{ + int32_t err; + uint8_t i; + adi_apollo_mailbox_cmd_set_ctrl_t set_ctrl_cmd = { + .sys_cal_object_id = APOLLO_CPU_OBJID_IC_DAC_TX, + .ctrl_cmd = CTRL_CMD_PARAM_GET, + .data_buffer[0] = calc_dac_trim_param(trim_attr), + .data_buffer[1] = 0, + .data_buffer[2] = 0, + .data_buffer[3] = 0, + .length = 4 + }; + adi_apollo_mailbox_resp_set_ctrl_t set_ctrl_resp = {0}; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(trim_val); + ADI_CMS_RANGE_CHECK(trim_attr, ADI_APOLLO_DAC_CLK_TRIM_1, ADI_APOLLO_DAC_CLK_TRIM_3); + ADI_APOLLO_INVALID_PARAM_RETURN(adi_api_utils_num_selected(dacs) != 1); + ADI_APOLLO_DAC_BLK_SEL_MASK(dacs); + + for (i = 0; i < ADI_APOLLO_DAC_NUM; i++) { + if ( (dacs & (ADI_APOLLO_DAC_A0 << i)) > 0 ) { + set_ctrl_cmd.channel_num = i; + break; + } + } + + err = adi_apollo_mailbox_set_ctrl(device, &set_ctrl_cmd, &set_ctrl_resp); + if (err != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Error from adi_apollo_mailbox_set_ctrl() %d", err); + return err; + } + + if (set_ctrl_resp.status != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Mailbox Response Status Error from adi_apollo_mailbox_set_ctrl() 0x%X", set_ctrl_resp.status); + return API_CMS_ERROR_MAILBOX_RESP_STATUS; + } + + /* Extract DAC Trim info from response structure */ + *trim_val = set_ctrl_resp.data_buffer[4]; + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_dac_scrambler_enable_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t scrambler_sel, uint8_t enable) +{ + int32_t err; + uint8_t i; + adi_apollo_blk_sel_t scrambler_chan; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_DAC_BLK_SEL_MASK(scrambler_sel); + + for (i = 0; i < ADI_APOLLO_DAC_NUM; i++) { + scrambler_chan = scrambler_sel & (ADI_APOLLO_DAC_A0 << i); + if (scrambler_chan > 0) { + regmap_base_addr = calc_tx_hsdout_base(i); + + /* Enable DAC Scrambler */ + err = adi_apollo_hal_bf_set(device, BF_DAC_SCRAMBLER_EN_INFO(regmap_base_addr), enable); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + + +int32_t adi_apollo_dac_scrambler_enable_get(adi_apollo_device_t *device, adi_apollo_blk_sel_t scrambler_sel, uint8_t *enable) +{ + int32_t err; + uint8_t i; + adi_apollo_blk_sel_t scrambler_chan; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(adi_api_utils_num_selected(scrambler_sel) != 1); + ADI_APOLLO_DAC_BLK_SEL_MASK(scrambler_sel); + + for (i = 0; i < ADI_APOLLO_DAC_NUM; i++) { + scrambler_chan = scrambler_sel & (ADI_APOLLO_DAC_A0 << i); + if (scrambler_chan > 0) { + regmap_base_addr = calc_tx_hsdout_base(i); + + /* Get Scrambler enable status */ + err = adi_apollo_hal_bf_get(device, BF_DAC_SCRAMBLER_EN_INFO(regmap_base_addr), enable, sizeof(*enable)); + ADI_APOLLO_ERROR_RETURN(err); + + break; /* only one chan per call */ + } + } + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_dac_data_enable(adi_apollo_device_t *device, adi_apollo_blk_sel_t dacs, uint8_t enable) +{ + int32_t err; + uint8_t i; + adi_apollo_mailbox_cmd_set_ctrl_t set_ctrl_cmd = { + .sys_cal_object_id = APOLLO_CPU_OBJID_IC_DAC_TX, + .ctrl_cmd = CTRL_CMD_PARAM_SET, + .data_buffer[0] = ADI_APOLLO_DAC_DECODER_ENABLE_UINT8, + .data_buffer[1] = 0, + .data_buffer[2] = 0, + .data_buffer[3] = 0, + .data_buffer[4] = enable, + .data_buffer[5] = 0, + .data_buffer[6] = 0, + .data_buffer[7] = 0, + .length = 8 + }; + adi_apollo_mailbox_resp_set_ctrl_t set_ctrl_resp = {0}; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_CMS_RANGE_CHECK(enable, 0, 1); + ADI_APOLLO_DAC_BLK_SEL_MASK(dacs); + + for (i = 0; i < ADI_APOLLO_DAC_NUM; i++) { + if ( (dacs & (ADI_APOLLO_DAC_A0 << i)) > 0 ) { + set_ctrl_cmd.channel_num = i; + + err = adi_apollo_mailbox_set_ctrl(device, &set_ctrl_cmd, &set_ctrl_resp); + if (err != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Error from adi_apollo_mailbox_set_ctrl() %d", err); + return err; + } + if (set_ctrl_resp.status != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Mailbox Response Status Error from adi_apollo_mailbox_set_ctrl() 0x%X", set_ctrl_resp.status); + return API_CMS_ERROR_MAILBOX_RESP_STATUS; + } + adi_apollo_hal_delay_us(device, 100 * 1000); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_dac_standby_lock_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t dacs, uint8_t lock_state) +{ + int32_t err; + uint8_t i; + adi_apollo_mailbox_cmd_set_ctrl_t set_ctrl_cmd = { + .sys_cal_object_id = APOLLO_CPU_OBJID_IC_DAC_TX, + .ctrl_cmd = CTRL_CMD_PARAM_SET, + .data_buffer[0] = ADI_APOLLO_DAC_BIAS_FORCE_STANDBY_EN_UINT8, + .data_buffer[1] = 0, + .data_buffer[2] = 0, + .data_buffer[3] = 0, + .data_buffer[4] = lock_state, + .data_buffer[5] = 0, + .data_buffer[6] = 0, + .data_buffer[7] = 0, + .length = 8 + }; + adi_apollo_mailbox_resp_set_ctrl_t set_ctrl_resp = {0}; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(lock_state > 1); + ADI_APOLLO_DAC_BLK_SEL_MASK(dacs); + + for (i = 0; i < ADI_APOLLO_DAC_NUM; i++) { + if ( (dacs & (ADI_APOLLO_DAC_A0 << i)) > 0 ) { + set_ctrl_cmd.channel_num = i; + + err = adi_apollo_mailbox_set_ctrl(device, &set_ctrl_cmd, &set_ctrl_resp); + if (err != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Error from adi_apollo_mailbox_set_ctrl() %d", err); + return err; + } + if (set_ctrl_resp.status != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Mailbox Response Status Error from adi_apollo_mailbox_set_ctrl() 0x%X", set_ctrl_resp.status); + return API_CMS_ERROR_MAILBOX_RESP_STATUS; + } + adi_apollo_hal_delay_us(device, 100 * 1000); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_dac_standby_lock_get(adi_apollo_device_t *device, adi_apollo_blk_sel_t dacs, uint8_t *lock_state) +{ + int32_t err; + uint8_t i; + adi_apollo_mailbox_cmd_set_ctrl_t set_ctrl_cmd = { + .sys_cal_object_id = APOLLO_CPU_OBJID_IC_DAC_TX, + .ctrl_cmd = CTRL_CMD_PARAM_GET, + .data_buffer[0] = ADI_APOLLO_DAC_BIAS_FORCE_STANDBY_EN_UINT8, + .data_buffer[1] = 0, + .data_buffer[2] = 0, + .data_buffer[3] = 0, + .length = 4 + }; + adi_apollo_mailbox_resp_set_ctrl_t set_ctrl_resp = {0}; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(lock_state); + ADI_APOLLO_INVALID_PARAM_RETURN(adi_api_utils_num_selected(dacs) != 1); + ADI_APOLLO_DAC_BLK_SEL_MASK(dacs); + + for (i = 0; i < ADI_APOLLO_DAC_NUM; i++) { + if ( (dacs & (ADI_APOLLO_DAC_A0 << i)) > 0 ) { + set_ctrl_cmd.channel_num = i; + break; + } + } + + err = adi_apollo_mailbox_set_ctrl(device, &set_ctrl_cmd, &set_ctrl_resp); + if (err != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Error from adi_apollo_mailbox_set_ctrl() %d", err); + return err; + } + + if (set_ctrl_resp.status != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Mailbox Response Status Error from adi_apollo_mailbox_set_ctrl() 0x%X", set_ctrl_resp.status); + return API_CMS_ERROR_MAILBOX_RESP_STATUS; + } + + /* Extract DAC STANDBY Control lock state info from response structure */ + *lock_state = set_ctrl_resp.data_buffer[4]; + + return API_CMS_ERROR_OK; +} + + +__maybe_unused uint32_t calc_tx_hsdout_base(int32_t index) +{ + /* + * This table is organized for DAC context usage (fifo, scrambler) of hsdout, + * different from datapath (e.g. inv sinc) + */ + static uint32_t tx_hsdout_regmap[ADI_APOLLO_DAC_NUM] = { + TX_HSDOUT0_TX_SLICE_0_TX_DIGITAL0, /* A0 */ + TX_HSDOUT1_TX_SLICE_0_TX_DIGITAL0, /* A1* */ + TX_HSDOUT0_TX_SLICE_1_TX_DIGITAL0, /* A2* */ + TX_HSDOUT1_TX_SLICE_1_TX_DIGITAL0, /* A3 */ + + TX_HSDOUT0_TX_SLICE_0_TX_DIGITAL1, /* B0 */ + TX_HSDOUT1_TX_SLICE_0_TX_DIGITAL1, /* B1* */ + TX_HSDOUT0_TX_SLICE_1_TX_DIGITAL1, /* B2* */ + TX_HSDOUT1_TX_SLICE_1_TX_DIGITAL1 /* B3 */ + }; + return tx_hsdout_regmap[index]; +} + +static uint8_t calc_dac_trim_param(adi_apollo_dac_clk_trim_e trim_attr) +{ + ADI_CMS_RANGE_CHECK(trim_attr, ADI_APOLLO_DAC_CLK_TRIM_1, ADI_APOLLO_DAC_CLK_TRIM_3); + + if (trim_attr == ADI_APOLLO_DAC_CLK_TRIM_1) { + return ADI_APOLLO_DAC_CLK_PHASECTRL_SKEW_PRG_UINT8; + } else if (trim_attr == ADI_APOLLO_DAC_CLK_TRIM_2) { + return ADI_APOLLO_DAC_CLK_DUTYCTRL_OFFSET_PRG_UINT8; + } else { + return ADI_APOLLO_DAC_CLK_PHASECTRL_OFFSET_PRG_UINT8; + } +} + +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_ddc_local.h b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_ddc_local.h new file mode 100644 index 00000000000000..2b3a85f7400688 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_ddc_local.h @@ -0,0 +1,37 @@ +/*! + * \brief DDC functional block local API implementation + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_CDDC + * @{ + */ +#ifndef __ADI_APOLLO_DDC_LOCAL_H__ +#define __ADI_APOLLO_DDC_LOCAL_H__ + +/*============= I N C L U D E S ============*/ + +/*============= D E F I N E S ==============*/ + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +uint32_t calc_rx_cddc_base(int32_t cddc_index); +uint32_t calc_rx_fddc_base(int32_t fddc_index); + +#ifndef CLIENT_IGNORE +#endif /* CLIENT_IGNORE*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_DDC_LOCAL_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_device.c b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_device.c new file mode 100644 index 00000000000000..2aa7df331f41a1 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_device.c @@ -0,0 +1,575 @@ +/*! + * \brief General device API implementations + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_DEVICE + * @{ + */ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_config.h" +#include "adi_apollo_hal.h" +#include "adi_apollo_bf_core.h" +#include "adi_apollo_bf_hsci.h" +#include "adi_apollo_hal_regio_local.h" +#include "adi_apollo_device.h" +#include "adi_apollo_bf_mcs_sync.h" +#include "adi_apollo_bf_rsa.h" +#include "adi_apollo_mailbox.h" +#include "adi_apollo_private_device.h" +#include "adi_apollo_private_blk_sel.h" +#include "adi_apollo_bf_ec.h" +#include "adi_apollo_rxmisc.h" +#include "adi_apollo_txmisc.h" +#include "adi_apollo_bf_custom.h" + +/*============= D A T A ====================*/ +static uint16_t apollo_api_revision[3] = { 2, 0, 10 }; + +static adi_apollo_mailbox_cmd_set_enabled_temp_sensors_t temp_senors_cmd = { + .temp_sensor_mask = ADI_APOLLO_DEVTEMP_MASK_SERDESPLL | + ADI_APOLLO_DEVTEMP_MASK_MPU_A | ADI_APOLLO_DEVTEMP_MASK_MPU_B | + ADI_APOLLO_DEVTEMP_MASK_LPU_VENUS_A | ADI_APOLLO_DEVTEMP_MASK_LPU_VENUS_B | + ADI_APOLLO_DEVTEMP_MASK_LPU_CK_CORNER_A | ADI_APOLLO_DEVTEMP_MASK_LPU_CK_CORNER_B | ADI_APOLLO_DEVTEMP_MASK_LPU_CK_CENTER +}; + +/*============= C O D E ====================*/ +static int32_t configure_spi(adi_apollo_device_t *device); +static int32_t device_context_init(adi_apollo_device_t* device); + +int32_t adi_apollo_device_spi_register_set(adi_apollo_device_t *device, uint32_t addr, uint8_t data) +{ + int32_t err; + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_hal_reg_set(device, addr, data); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_device_spi_register_get(adi_apollo_device_t *device, uint32_t addr, uint8_t *data) +{ + int32_t err; + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(data); + + err = adi_apollo_hal_reg_get(device, addr, data); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_device_api_revision_get(adi_apollo_device_t *device, uint16_t *rev_major, uint16_t *rev_minor, uint16_t *rev_rc) +{ + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(rev_major); + ADI_APOLLO_NULL_POINTER_RETURN(rev_minor); + ADI_APOLLO_NULL_POINTER_RETURN(rev_rc); + + *rev_major = apollo_api_revision[0]; + *rev_minor = apollo_api_revision[1]; + *rev_rc = apollo_api_revision[2]; + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_device_reset(adi_apollo_device_t *device, adi_apollo_reset_e reset_opt) +{ + int32_t err; + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(reset_opt > ADI_APOLLO_HARD_RESET_AND_INIT); + + /* Datapath reset - mitigates power supply current change */ + err = adi_apollo_rxmisc_dp_reset(device, ADI_APOLLO_SIDE_ALL, 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_txmisc_dp_reset(device, ADI_APOLLO_SIDE_ALL, 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_rxmisc_dp_reset(device, ADI_APOLLO_SIDE_ALL, 0); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_txmisc_dp_reset(device, ADI_APOLLO_SIDE_ALL, 0); + ADI_APOLLO_ERROR_RETURN(err); + + /* Device reset */ + if ((reset_opt == ADI_APOLLO_SOFT_RESET) || (reset_opt == ADI_APOLLO_SOFT_RESET_AND_INIT)) { + err = adi_apollo_hal_reg_set(device, REG_SPI_IFACE_CONFIG_A_ADDR, 0x81); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_reg_set(device, REG_SPI_IFACE_CONFIG_A_ADDR, 0x00); + ADI_APOLLO_ERROR_RETURN(err); + } else if ((reset_opt == ADI_APOLLO_HARD_RESET) || (reset_opt == ADI_APOLLO_HARD_RESET_AND_INIT)) { + err = adi_apollo_hal_reset_pin_ctrl(device, 0); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_delay_us(device, 1000); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_reset_pin_ctrl(device, 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_delay_us(device, 1000); + ADI_APOLLO_ERROR_RETURN(err); + } + + /* do init */ + if ((reset_opt == ADI_APOLLO_SOFT_RESET_AND_INIT) || (reset_opt == ADI_APOLLO_HARD_RESET_AND_INIT)) { + err = adi_apollo_device_init(device); + ADI_APOLLO_ERROR_RETURN(err); + } + + /* Align the SPI page base addresses after reset */ + device->hal_info.spi0_desc.page_base_addr = 0; + device->hal_info.spi1_desc.page_base_addr = 0; + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_device_init(adi_apollo_device_t *device) +{ + int32_t err; + uint32_t endian_test_val = 0x11223344; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + /* log API information */ + err = adi_apollo_hal_log_write(device, ADI_CMS_LOG_MSG, "api v%d.%d.%d ", + apollo_api_revision[0], apollo_api_revision[1], apollo_api_revision[2]); + ADI_APOLLO_ERROR_RETURN(err); + + /* get host cpu endian mode */ + if (*(uint8_t *)&endian_test_val == 0x44) + ADI_APOLLO_LOG_MSG("host is using little endian mode."); + else + ADI_APOLLO_LOG_MSG("host is using big endian mode."); + + /* program device spi config */ + err = configure_spi(device); + ADI_APOLLO_ERROR_RETURN(err); + + /* Configure device hsci */ + if (device->hal_info.hsci_desc.is_used) { + err = adi_apollo_device_hsci_configure(device, &device->hal_info.hsci_desc.hsci_config); + ADI_APOLLO_ERROR_RETURN(err); + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_device_deinit(adi_apollo_device_t *device) +{ + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_device_chip_id_get(adi_apollo_device_t *device, adi_cms_chip_id_t *chip_id) +{ + int32_t err; + uint8_t reg_val = 0x0; + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(chip_id); + + err = adi_apollo_hal_reg_get(device, REG_CHIP_TYPE_ADDR, ®_val); + ADI_APOLLO_ERROR_RETURN(err); + chip_id->chip_type = reg_val; + + err = adi_apollo_hal_reg_get(device, REG_PRODUCT_ID_0_ADDR, ®_val); + ADI_APOLLO_ERROR_RETURN(err); + chip_id->prod_id = reg_val; + + err = adi_apollo_hal_reg_get(device, REG_PRODUCT_ID_1_ADDR, ®_val); + ADI_APOLLO_ERROR_RETURN(err); + chip_id->prod_id |= (reg_val << 8); + + err = adi_apollo_hal_reg_get(device, REG_CHIP_GRADE_ADDR, ®_val); + ADI_APOLLO_ERROR_RETURN(err); + chip_id->prod_grade = (reg_val >> 4); + chip_id->dev_revision = (reg_val & 0x0F); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_device_laminate_id_get(adi_apollo_device_t *device, uint8_t *id) +{ + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(id); + + return adi_apollo_hal_reg_get(device, REG_LAMINATE_ID_ADDR, (uint8_t *)id); +} + +int32_t adi_apollo_device_die_id_get(adi_apollo_device_t *device, uint8_t *id) +{ + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(id); + + return adi_apollo_hal_reg_get(device, REG_DIE_ID_ADDR, (uint8_t *)id); +} + +int32_t adi_apollo_device_si_grade_get(adi_apollo_device_t *device, uint8_t *si_grade) +{ + int32_t err; + uint8_t reg_val; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(si_grade); + + err = adi_apollo_hal_reg_get(device, REG_EC_ANA_BYTE2_ADDR, ®_val); + ADI_APOLLO_ERROR_RETURN(err); + + *si_grade = (reg_val & 0x01); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_device_sw_mxfe_get(adi_apollo_device_t *device, adi_apollo_device_sw_variant_mxfe_e *mxfe) +{ + int32_t err; + uint8_t reg_val; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(mxfe); + + err = adi_apollo_hal_reg_get(device, REG_PART_VARIANT_SW_MXFE_ADDR, ®_val); + ADI_APOLLO_ERROR_RETURN(err); + + *mxfe = (reg_val <= 2) ? + (adi_apollo_device_sw_variant_mxfe_e)reg_val : + ADI_APOLLO_DEVICE_SW_VARIANT_INVALID; + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_device_sw_trim_get(adi_apollo_device_t *device, adi_apollo_device_sw_variant_trim_e *sw_trim) +{ + int32_t err; + uint8_t reg_val; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(sw_trim); + + err = adi_apollo_hal_reg_get(device, REG_PART_VARIANT_SW_TRIM_ADDR, ®_val); + ADI_APOLLO_ERROR_RETURN(err); + switch (reg_val) { + case 0: + case 1: + case 3: + case 5: + *sw_trim = (adi_apollo_device_sw_variant_trim_e)reg_val; + break; + default: + *sw_trim = ADI_APOLLO_DEVICE_SW_VARIANT_TRIM_INVALID; + break; + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_device_trx_config_get(adi_apollo_device_t *device, adi_apollo_device_rev_trx_config_e *trx_cfg) +{ + int32_t err; + uint8_t reg_val; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(trx_cfg); + + err = adi_apollo_device_die_id_get(device, ®_val); + ADI_APOLLO_ERROR_RETURN(err); + + /* Bit 7 indicates 4T4R (0) or 8T8R (1) */ + *trx_cfg = (adi_apollo_device_rev_trx_config_e)((reg_val & 0x80) >> 7); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_device_rx_type_get(adi_apollo_device_t *device, adi_apollo_device_rev_rx_type_e *rx_type) +{ + int32_t err; + uint8_t reg_val; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(rx_type); + + err = adi_apollo_device_die_id_get(device, ®_val); + ADI_APOLLO_ERROR_RETURN(err); + + /* Bit 5 indicates Differential (0) or single-ended (1) */ + *rx_type = (adi_apollo_device_rev_rx_type_e)((reg_val & 0x40) >> 6); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_device_board_variant_and_rev_get(adi_apollo_device_t *device, adi_apollo_device_board_var_and_rev_info_t *board_var_rev) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(board_var_rev); + + /* read back die id */ + err = adi_apollo_device_die_id_get(device, &board_var_rev->die_id); + ADI_APOLLO_ERROR_RETURN(err); + + /* read back si_grade */ + err = adi_apollo_device_si_grade_get(device, &board_var_rev->si_grade); + ADI_APOLLO_ERROR_RETURN(err); + + /* read back mxfe */ + err = adi_apollo_device_sw_mxfe_get(device, &board_var_rev->mxfe); + ADI_APOLLO_ERROR_RETURN(err); + + /* read back sw trim */ + err = adi_apollo_device_sw_trim_get(device, &board_var_rev->sw_trim); + ADI_APOLLO_ERROR_RETURN(err); + + /* read back trx config */ + err = adi_apollo_device_trx_config_get(device, &board_var_rev->trx_cfg); + ADI_APOLLO_ERROR_RETURN(err); + + /* read back rx type */ + err = adi_apollo_device_rx_type_get(device, &board_var_rev->rx_type); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_device_hw_open(adi_apollo_device_t *device, adi_apollo_reset_e reset_opt) +{ + + int32_t err; + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(reset_opt < ADI_APOLLO_NO_RESET) + ADI_APOLLO_INVALID_PARAM_RETURN(reset_opt > ADI_APOLLO_HARD_RESET_AND_INIT) + ADI_APOLLO_NULL_POINTER_RETURN(device->hal_info.delay_us); // Check delay driver function assignment + + err = adi_apollo_hal_hw_open(device); + ADI_APOLLO_ERROR_RETURN(err); + + /* Internal regio configuration */ + err = adi_apollo_l_hal_regio_spi_init(&device->hal_info.spi0_desc, 0); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_l_hal_regio_spi_init(&device->hal_info.spi1_desc, 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_l_hal_regio_hsci_init(&device->hal_info.hsci_desc); + ADI_APOLLO_ERROR_RETURN(err); + + /* Configure device spi */ + err = configure_spi(device); + ADI_APOLLO_ERROR_RETURN(err); + + /* Do any device context one-time initialization */ + err = device_context_init(device); + ADI_APOLLO_ERROR_RETURN(err); + + /* Do optional reset */ + if (reset_opt != ADI_APOLLO_NO_RESET) { + err = adi_apollo_device_reset(device, reset_opt); + ADI_APOLLO_ERROR_RETURN(err); + } + + /* Store the block selection mask for device type (is_8t8r mask be established) */ + adi_apollo_private_blk_sel_mask_set(device); + + /* Configure device hsci */ + if (device->hal_info.hsci_desc.is_used) { + err = adi_apollo_device_hsci_configure(device, &device->hal_info.hsci_desc.hsci_config); + ADI_APOLLO_ERROR_RETURN(err); + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_device_hw_close(adi_apollo_device_t *device) +{ + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_device_spi_configure(adi_apollo_device_t *device, adi_apollo_device_spi_settings_t *spi_config, uint8_t spi_num) +{ + int32_t err = API_CMS_ERROR_OK; + uint8_t reg_val = 0x00; + void *active_regio_save; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(spi_config); + + /* To init spi0 or spi1, spi0 must be active */ + if (!device->hal_info.spi0_desc.is_used) { + return API_CMS_ERROR_ERROR; + } + + /* Assemble spi init register val */ + reg_val |= (spi_config->sdo == ADI_APOLLO_DEVICE_SPI_SDIO) ? 0x00 : 0x18; /* 3-wire : 4-wire */ + reg_val |= (spi_config->addr_inc == ADI_APOLLO_DEVICE_SPI_ADDR_DEC_AUTO) ? 0x00 : 0x24; /* dec : incr */ + reg_val |= (spi_config->msb == ADI_APOLLO_DEVICE_SPI_MSB_FIRST) ? 0x00 : 0x42; /* MSB first : LSB first */ + + /* Set active regio to spi0, save current active one (e.g. hsci) */ + active_regio_save = device->hal_info.active_regio; + device->hal_info.active_regio = &device->hal_info.spi0_desc.base_regio; + + if (spi_num == 1) { + if (device->hal_info.spi1_desc.is_used) { + err = adi_apollo_hal_reg_set(device, REG_SPI1_ENABLE_ADDR, 0x01); /* Enable spi1 (using spi0) */ + device->hal_info.active_regio = &device->hal_info.spi1_desc.base_regio; + } + else { + err = API_CMS_ERROR_ERROR; + } + } + + if (err == API_CMS_ERROR_OK) { + err = adi_apollo_hal_reg_set(device, REG_SPI_FIFO_MODE_REG_ADDR, 0); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_reg_set(device, REG_SPI_IFACE_CONFIG_A_ADDR, reg_val); /* Set config reg for spi0 or spi1 */ + ADI_APOLLO_ERROR_RETURN(err); + } + + /* Restore the original active regio */ + if (active_regio_save != NULL) { + device->hal_info.active_regio = active_regio_save; + } + + return err; +} + +int32_t adi_apollo_device_hsci_configure(adi_apollo_device_t *device, adi_apollo_device_hsci_settings_t *hsci_config) +{ + int32_t err = API_CMS_ERROR_OK; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(hsci_config); + + if (hsci_config->auto_linkup_en == 1) { + err = adi_apollo_private_device_hsci_auto_linkup_configure(device); + ADI_APOLLO_ERROR_RETURN(err); + } else { + err = adi_apollo_private_device_hsci_manual_linkup_configure(device); + ADI_APOLLO_ERROR_RETURN(err); + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_device_uuid_get(adi_apollo_device_t *device, uint8_t uuid[], uint32_t uuid_len) +{ + int32_t err, i; + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(uuid_len != ADI_APOLLO_UUID_NUM_BYTES); + + for (i = 0; i < uuid_len; i++) { + err = adi_apollo_hal_reg_get(device, REG_CHIPID_0_RSA_ADDR + i, (uint8_t *)uuid + i); + ADI_APOLLO_ERROR_RETURN(err); + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_device_tmu_enable(adi_apollo_device_t *device) +{ + int32_t err = API_CMS_ERROR_OK; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + adi_apollo_mailbox_resp_set_enabled_temp_sensors_t temp_sensors_resp; + err = adi_apollo_mailbox_set_enabled_temp_sensors(device, &temp_senors_cmd, &temp_sensors_resp); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_device_tmu_get(adi_apollo_device_t *device, adi_apollo_device_tmu_data_t *tmu_data) +{ + int32_t err = API_CMS_ERROR_OK; + adi_apollo_device_tmu_index_e temp_degrees_celsius_index; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(tmu_data); + + /* + * Read device temperature sensors. + */ + adi_apollo_mailbox_cmd_get_device_temperature_t get_temp_cmd = { + .avg_mask = temp_senors_cmd.temp_sensor_mask + }; + adi_apollo_mailbox_resp_get_device_temperature_t get_temp_resp; + err = adi_apollo_mailbox_get_device_temperature(device, &get_temp_cmd, &get_temp_resp); + ADI_APOLLO_ERROR_RETURN(err); + + // Extract values to the tmu_data struct + tmu_data->avg_mask = get_temp_resp.temp_data.avg_mask; + tmu_data->max_temp_degrees_celsius = get_temp_resp.temp_data.max_temp_degrees_celsius; + tmu_data->min_temp_degrees_celsius = get_temp_resp.temp_data.min_temp_degrees_celsius; + for (temp_degrees_celsius_index = ADI_APOLLO_DEVICE_TMU_SERDES_PLL; temp_degrees_celsius_index <= ADI_APOLLO_DEVICE_TMU_CLK_C; temp_degrees_celsius_index++) { + tmu_data->temp_degrees_celsius[temp_degrees_celsius_index] = get_temp_resp.temp_data.temp_degrees_celsius[temp_degrees_celsius_index]; + } + + tmu_data->temp_degrees_celsius_avg = get_temp_resp.temp_data.temp_degrees_celsius_avg; + + return API_CMS_ERROR_OK; +} + +/* Configure device spi */ +static int32_t configure_spi(adi_apollo_device_t *device) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + + if (device->hal_info.spi0_desc.is_used) { + err = adi_apollo_hal_active_protocol_set(device, ADI_APOLLO_HAL_PROTOCOL_SPI0); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_device_spi_configure(device, &device->hal_info.spi0_desc.spi_config, 0); + ADI_APOLLO_ERROR_RETURN(err); + } + + if (device->hal_info.spi1_desc.is_used) { + err = adi_apollo_device_spi_configure(device, &device->hal_info.spi1_desc.spi_config, 1); + ADI_APOLLO_ERROR_RETURN(err); + } + + return API_CMS_ERROR_OK; +} + +/* Initialize device context info */ +static int32_t device_context_init(adi_apollo_device_t* device) +{ + int32_t err; + uint8_t rev_major; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + + /* Set 4t4r/8t8r flag */ + err = adi_apollo_hal_bf_get(device, BF_MASK_REVISION_MAJOR_INFO, &rev_major, sizeof(rev_major)); + ADI_APOLLO_ERROR_RETURN(err); + + device->dev_info.is_8t8r = (rev_major >> 3) & 1; + ADI_APOLLO_LOG_VAR(ADI_CMS_LOG_API, "Device config: %s", device->dev_info.is_8t8r ? "8T8R" : "4T4R"); + + return API_CMS_ERROR_OK; +} + +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_dformat.c b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_dformat.c new file mode 100644 index 00000000000000..6305d5067b5a75 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_dformat.c @@ -0,0 +1,411 @@ +/*! + * \brief APIs for DFORMAT functional block + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_DFORMAT + * @{ + */ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_dformat.h" + +#include "adi_apollo_dformat_local.h" +#include "adi_apollo_tmode_local.h" +#include "adi_apollo_fddc_types.h" +#include "adi_apollo_bf_jtx_dformat.h" + +#include "adi_apollo_config.h" +#include "adi_apollo_hal.h" +#include "adi_utils.h" + +/*==================== P U B L I C A P I C O D E ====================*/ + +#define BF_INVALID_EN_INFO_LINK0 0x00000100 // Link0 invalid bitfield +#define BF_INVALID_EN_INFO_LINK1 0x00000101 // Link1 invalid bitfield + +/* Struct for acessing bit fields */ +typedef struct { + uint32_t reg_offset; + uint32_t bf_info; +} reg_bf_info_map_t; + +static uint8_t cbout_to_bf(uint8_t cbout, uint8_t is_8t8r); + +int32_t adi_apollo_dformat_pgm(adi_apollo_device_t *device, const uint16_t links, adi_apollo_dformat_pgm_t *config) +{ + int32_t err, i; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(config); + + for (i = 0; i < ADI_APOLLO_NUM_JTX_LINKS; i++) { + if ((1 << i) & links) { + regmap_base_addr = calc_jtx_dformat_base(i); + + if ((i % ADI_APOLLO_NUM_JTX_LINKS_PER_SIDE) == 0) { /* Link 0 */ + err = adi_apollo_hal_bf_set(device, BF_DFORMAT_SEL_0_INFO(regmap_base_addr), config->dfor_sel); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_DFORMAT_INV_0_INFO(regmap_base_addr), config->dfor_inv); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_DFORMAT_DDC_DITHER_EN_0_INFO(regmap_base_addr), config->dfor_ddc_dither_en); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_DFORMAT_RES_0_INFO(regmap_base_addr), config->dfor_res); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_LINK_EN_0_INFO(regmap_base_addr), config->link_en); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_LINK_DDC_DEC_0_INFO(regmap_base_addr), config->dcm_ratio); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_LINK_TOTAL_DEC_0_INFO(regmap_base_addr), config->total_dcm); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, REG_INVALID_EN_ADDR(regmap_base_addr), BF_INVALID_EN_INFO_LINK0, config->invalid_en); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_SAMPLE_REPEAT_EN_0_INFO(regmap_base_addr), config->sample_repeat_en); + ADI_APOLLO_ERROR_RETURN(err); + } else { /* Link 1 */ + err = adi_apollo_hal_bf_set(device, BF_DFORMAT_SEL_1_INFO(regmap_base_addr), config->dfor_sel); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_DFORMAT_INV_1_INFO(regmap_base_addr), config->dfor_inv); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_DFORMAT_DDC_DITHER_EN_1_INFO(regmap_base_addr), config->dfor_ddc_dither_en); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_DFORMAT_RES_1_INFO(regmap_base_addr), config->dfor_res); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_LINK_EN_1_INFO(regmap_base_addr), config->link_en); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_LINK_DDC_DEC_1_INFO(regmap_base_addr), config->dcm_ratio); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_LINK_TOTAL_DEC_1_INFO(regmap_base_addr), config->total_dcm); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, REG_INVALID_EN_ADDR(regmap_base_addr), BF_INVALID_EN_INFO_LINK1, config->invalid_en); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_SAMPLE_REPEAT_EN_1_INFO(regmap_base_addr), config->sample_repeat_en); + ADI_APOLLO_ERROR_RETURN(err); + } + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_dformat_res_sel_set(adi_apollo_device_t *device, + const uint16_t links, + adi_apollo_chip_output_res_e resolution) +{ + int32_t err, i; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + for (i = 0; i < ADI_APOLLO_NUM_JTX_LINKS; i++) { + if ((1 << i) & links) { + regmap_base_addr = calc_jtx_dformat_base(i); + + if ((i % ADI_APOLLO_NUM_JTX_LINKS_PER_SIDE) == 0) { + err = adi_apollo_hal_bf_set(device, BF_DFORMAT_RES_0_INFO(regmap_base_addr), resolution); /* Link 0 */ + } else { + err = adi_apollo_hal_bf_set(device, BF_DFORMAT_RES_1_INFO(regmap_base_addr), resolution); /* Link 1*/ + } + + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_dformat_format_sel_set(adi_apollo_device_t *device, const uint16_t links, + uint8_t format) +{ + int32_t err, i; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(format > 2); + + for (i = 0; i < ADI_APOLLO_NUM_JTX_LINKS; i++) { + if ((1 << i) & links) { + regmap_base_addr = calc_jtx_dformat_base(i); + + if ((i % ADI_APOLLO_NUM_JTX_LINKS_PER_SIDE) == 0) { + err = adi_apollo_hal_bf_set(device, BF_DFORMAT_SEL_0_INFO(regmap_base_addr), format); /* Link 0 */ + ADI_APOLLO_ERROR_RETURN(err); + } else { + err = adi_apollo_hal_bf_set(device, BF_DFORMAT_SEL_1_INFO(regmap_base_addr), format); /* Link 1 */ + ADI_APOLLO_ERROR_RETURN(err); + } + + ADI_APOLLO_ERROR_RETURN(err); + } + } + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_dformat_ctrl_bit_sel_set(adi_apollo_device_t *device, const uint16_t links, + uint8_t bit0_sel, uint8_t bit1_sel, uint8_t bit2_sel) +{ + int32_t err, i; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + for (i = 0; i < ADI_APOLLO_NUM_JTX_LINKS; i++) { + if ((1 << i) & links) { + regmap_base_addr = calc_jtx_dformat_base(i); + + if ((i % ADI_APOLLO_NUM_JTX_LINKS_PER_SIDE) == 0) { + err = adi_apollo_hal_bf_set(device, BF_DFORMAT_CTRL_BIT_0_SEL_0_INFO(regmap_base_addr), bit0_sel); /* Link 0 */ + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_DFORMAT_CTRL_BIT_1_SEL_0_INFO(regmap_base_addr), bit1_sel); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_DFORMAT_CTRL_BIT_2_SEL_0_INFO(regmap_base_addr), bit2_sel); + ADI_APOLLO_ERROR_RETURN(err); + } else { + err = adi_apollo_hal_bf_set(device, BF_DFORMAT_CTRL_BIT_0_SEL_1_INFO(regmap_base_addr), bit0_sel); /* Link 1 */ + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_DFORMAT_CTRL_BIT_1_SEL_1_INFO(regmap_base_addr), bit1_sel); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_DFORMAT_CTRL_BIT_2_SEL_1_INFO(regmap_base_addr), bit2_sel); + ADI_APOLLO_ERROR_RETURN(err); + } + + ADI_APOLLO_ERROR_RETURN(err); + } + } + return API_CMS_ERROR_OK; +} + + +int32_t adi_apollo_dformat_conv_test_mode_enable_set(adi_apollo_device_t *device, + const uint16_t links, + uint8_t enable) +{ + int32_t err, i; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + for (i = 0; i < ADI_APOLLO_NUM_JTX_LINKS; i ++) { + if ((1 << i) & links) { + + regmap_base_addr = calc_jtx_dformat_base(i); + + if ((i % ADI_APOLLO_TMODE_N) == 0) { + err = adi_apollo_hal_bf_set(device, BF_DFORMAT_TMODE_SEL_0_INFO(regmap_base_addr), enable); /* Link 0 */ + } else { + err = adi_apollo_hal_bf_set(device, BF_DFORMAT_TMODE_SEL_1_INFO(regmap_base_addr), enable); /* Link 1 */ + } + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_dformat_inspect(adi_apollo_device_t *device, const uint16_t link, adi_apollo_dformat_inspect_t *inspect){ + int32_t err, i; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(inspect); + ADI_APOLLO_INVALID_PARAM_RETURN(adi_api_utils_num_selected(link) != 1); + + for (i = 0; i < ADI_APOLLO_NUM_JTX_LINKS; i++) { + if ((1 << i) & link) { + regmap_base_addr = calc_jtx_dformat_base(i); + + if ((i % ADI_APOLLO_NUM_JTX_LINKS_PER_SIDE) == 0) { /* Link 0 */ + err = adi_apollo_hal_bf_get(device, BF_DFORMAT_SEL_0_INFO(regmap_base_addr), &(inspect->dp_cfg.sel), sizeof(inspect->dp_cfg.sel)); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_DFORMAT_INV_0_INFO(regmap_base_addr), (uint8_t*) &(inspect->dp_cfg.inv), sizeof(inspect->dp_cfg.inv)); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_DFORMAT_DDC_DITHER_EN_0_INFO(regmap_base_addr), (uint8_t*) &(inspect->dp_cfg.ddc_dither_en), sizeof(inspect->dp_cfg.ddc_dither_en)); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_DFORMAT_RES_0_INFO(regmap_base_addr), &(inspect->dp_cfg.res), sizeof(inspect->dp_cfg.res)); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_LINK_EN_0_INFO(regmap_base_addr), &(inspect->link_en), sizeof(inspect->link_en)); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_LINK_DDC_DEC_0_INFO(regmap_base_addr), (uint8_t*) &(inspect->dcm_ratio), sizeof(inspect->dcm_ratio)); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_LINK_TOTAL_DEC_0_INFO(regmap_base_addr), (uint8_t*) &(inspect->total_dcm), sizeof(inspect->total_dcm)); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_SAMPLE_REPEAT_EN_0_INFO(regmap_base_addr), + (uint8_t*) &(inspect->dp_cfg.rm_fifo.sample_repeat_en), sizeof(inspect->dp_cfg.rm_fifo.sample_repeat_en)); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, REG_INVALID_EN_ADDR(regmap_base_addr), BF_INVALID_EN_INFO_LINK0, + (uint8_t*) &(inspect->dp_cfg.rm_fifo.invalid_en), sizeof(inspect->dp_cfg.rm_fifo.invalid_en)); + ADI_APOLLO_ERROR_RETURN(err); + } else { /* Link 1 */ + err = adi_apollo_hal_bf_get(device, BF_DFORMAT_SEL_1_INFO(regmap_base_addr), &(inspect->dp_cfg.sel), sizeof(inspect->dp_cfg.sel)); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_DFORMAT_INV_1_INFO(regmap_base_addr), (uint8_t*) &(inspect->dp_cfg.inv), sizeof(inspect->dp_cfg.inv)); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_DFORMAT_DDC_DITHER_EN_1_INFO(regmap_base_addr), (uint8_t*) &(inspect->dp_cfg.ddc_dither_en), sizeof(inspect->dp_cfg.ddc_dither_en)); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_DFORMAT_RES_1_INFO(regmap_base_addr), &(inspect->dp_cfg.res), sizeof(inspect->dp_cfg.res)); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_LINK_EN_1_INFO(regmap_base_addr), &(inspect->link_en), sizeof(inspect->link_en)); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_LINK_DDC_DEC_1_INFO(regmap_base_addr), (uint8_t*) &(inspect->dcm_ratio), sizeof(inspect->dcm_ratio)); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_LINK_TOTAL_DEC_1_INFO(regmap_base_addr), (uint8_t*) &(inspect->total_dcm), sizeof(inspect->total_dcm)); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_SAMPLE_REPEAT_EN_1_INFO(regmap_base_addr), + (uint8_t*) &(inspect->dp_cfg.rm_fifo.sample_repeat_en), sizeof(inspect->dp_cfg.rm_fifo.sample_repeat_en)); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, REG_INVALID_EN_ADDR(regmap_base_addr), BF_INVALID_EN_INFO_LINK1, + (uint8_t*) &(inspect->dp_cfg.rm_fifo.invalid_en), sizeof(inspect->dp_cfg.rm_fifo.invalid_en)); + ADI_APOLLO_ERROR_RETURN(err); + } + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_dformat_overflow_status_get(adi_apollo_device_t *device, const uint16_t link, uint8_t clear, uint8_t *status) { + int32_t err; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(status); + ADI_APOLLO_INVALID_PARAM_RETURN(adi_api_utils_num_selected(link) != 1); + + regmap_base_addr = calc_jtx_dformat_base(link); + + if (link == ADI_APOLLO_LINK_A0 || link == ADI_APOLLO_LINK_B0) { // Link 0 + err = adi_apollo_hal_bf_get(device, BF_DFORMAT_OVR_STATUS_0_INFO(regmap_base_addr), status, sizeof(*status)); + ADI_APOLLO_ERROR_RETURN(err); + } else { // Link 1 + err = adi_apollo_hal_bf_get(device, BF_DFORMAT_OVR_STATUS_1_INFO(regmap_base_addr), status, sizeof(*status)); + ADI_APOLLO_ERROR_RETURN(err); + } + + if (clear) { + err = adi_apollo_dformat_overflow_status_clear(device, link); + ADI_APOLLO_ERROR_RETURN(err); + } + + return API_CMS_ERROR_OK; +} + + +int32_t adi_apollo_dformat_overflow_status_clear(adi_apollo_device_t *device, const uint16_t link) { + int32_t err, i; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + for (i = 0; i < ADI_APOLLO_NUM_JTX_LINKS; i++) { + if ((1 << i) & link) { + regmap_base_addr = calc_jtx_dformat_base(i); + if ((i % ADI_APOLLO_NUM_JTX_LINKS_PER_SIDE) == 0) { // Link 0 + err = adi_apollo_hal_bf_set(device, BF_DFORMAT_OVR_CLR_0_INFO(regmap_base_addr), 0); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_DFORMAT_OVR_CLR_0_INFO(regmap_base_addr), 0xFF); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_DFORMAT_OVR_CLR_0_INFO(regmap_base_addr), 0); + ADI_APOLLO_ERROR_RETURN(err); + } else { // Link 1 + err = adi_apollo_hal_bf_set(device, BF_DFORMAT_OVR_CLR_1_INFO(regmap_base_addr), 0); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_DFORMAT_OVR_CLR_1_INFO(regmap_base_addr), 0xFF); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_DFORMAT_OVR_CLR_1_INFO(regmap_base_addr), 0); + ADI_APOLLO_ERROR_RETURN(err); + } + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_dformat_smon_fd_fddc_set(adi_apollo_device_t *device, adi_apollo_dformat_smon_fd_map_t map[], uint32_t map_len) +{ + int32_t err; + int32_t i; + int32_t idx; + uint8_t i_q_sel; + uint8_t cbout_bf; + adi_apollo_blk_sel_t fddc; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(map); + ADI_APOLLO_INVALID_PARAM_RETURN(map_len > ADI_APOLLO_FDDC_NUM) + + static reg_bf_info_map_t fddc_iq_map[2][ADI_APOLLO_FDDC_PER_SIDE_NUM] = { + { /* FDDC-I path*/ + {BF_FINE0_ADC_I_SEL_INFO(0)}, /* A0/B0 */ + {BF_FINE1_ADC_I_SEL_INFO(0)}, /* A1/B1 */ + {BF_FINE2_ADC_I_SEL_INFO(0)}, /* A2/B2 */ + {BF_FINE3_ADC_I_SEL_INFO(0)}, /* A3/B3 */ + {BF_FINE4_ADC_I_SEL_INFO(0)}, /* A4/B4 */ + {BF_FINE5_ADC_I_SEL_INFO(0)}, /* A5/B5 */ + {BF_FINE6_ADC_I_SEL_INFO(0)}, /* A6/B6 */ + {BF_FINE7_ADC_I_SEL_INFO(0)}, /* A7/B7 */ + }, + { /* FDDC-Q path */ + {BF_FINE0_ADC_Q_SEL_INFO(0)}, /* A0/B0 */ + {BF_FINE1_ADC_Q_SEL_INFO(0)}, /* A1/B1 */ + {BF_FINE2_ADC_Q_SEL_INFO(0)}, /* A2/B2 */ + {BF_FINE3_ADC_Q_SEL_INFO(0)}, /* A3/B3 */ + {BF_FINE4_ADC_Q_SEL_INFO(0)}, /* A4/B4 */ + {BF_FINE5_ADC_Q_SEL_INFO(0)}, /* A5/B5 */ + {BF_FINE6_ADC_Q_SEL_INFO(0)}, /* A6/B6 */ + {BF_FINE7_ADC_Q_SEL_INFO(0)}, /* A7/B7 */ + } + }; + + for (idx = 0; idx < map_len; idx++) { + for (i = 0; i < ADI_APOLLO_FDDC_NUM; i++) { + fddc = map[idx].fddc_select & (ADI_APOLLO_FDDC_A0 << i); + if (fddc > 0) { + regmap_base_addr = calc_jtx_dformat_base((i / ADI_APOLLO_FDDC_PER_SIDE_NUM) * ADI_APOLLO_NUM_JTX_LINKS_PER_SIDE); + + err = map[idx].i_q_select > 1 ? API_CMS_ERROR_INVALID_PARAM : API_CMS_ERROR_OK; + ADI_APOLLO_LOG_ERROR_RETURN_VAR(err, "i_q_select out of range %d", map[idx].i_q_select); + + err = (device->dev_info.is_8t8r ? (map[idx].cbout > ADI_APOLLO_RXMUX_CBOUT_3 ? API_CMS_ERROR_INVALID_PARAM : API_CMS_ERROR_OK) : + (map[idx].cbout > ADI_APOLLO_RXMUX_CBOUT_1 ? API_CMS_ERROR_INVALID_PARAM : API_CMS_ERROR_OK)); + ADI_APOLLO_LOG_ERROR_RETURN_VAR(err, "cbout out of range %d", map[idx].cbout); + + i_q_sel = map[idx].i_q_select; + cbout_bf = cbout_to_bf((uint8_t) map[idx].cbout, device->dev_info.is_8t8r); + + err = adi_apollo_hal_bf_set(device, + fddc_iq_map[i_q_sel][i % ADI_APOLLO_FDDC_PER_SIDE_NUM].reg_offset + regmap_base_addr, + fddc_iq_map[i_q_sel][i % ADI_APOLLO_FDDC_PER_SIDE_NUM].bf_info, cbout_bf); + ADI_APOLLO_ERROR_RETURN(err); + } + } + } + + return API_CMS_ERROR_OK; +} + +static uint8_t cbout_to_bf(uint8_t cbout, uint8_t is_8t8r) +{ + return is_8t8r ? cbout : (cbout == 0) ? cbout : 2; /* for 4t4r 0=cbout0, 2=cbout1 */ +} + +uint32_t calc_jtx_dformat_base(int32_t link) +{ + return ((link / ADI_APOLLO_NUM_JTX_LINKS_PER_SIDE) == 0) ? JTX_DFORMAT_JTX_TOP_RX_DIGITAL0 : JTX_DFORMAT_JTX_TOP_RX_DIGITAL1; +} +/*! @} */ \ No newline at end of file diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_dformat_local.h b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_dformat_local.h new file mode 100644 index 00000000000000..84c423376410a4 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_dformat_local.h @@ -0,0 +1,51 @@ +/*! + * \brief Apollo DFFORMAT functional block local defines and prototypes + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_DFORMAT + * @{ + */ +#ifndef __ADI_APOLLO_DFORMAT_LOCAL_H__ +#define __ADI_APOLLO_DFORMAT_LOCAL_H__ + + +/*============= I N C L U D E S ============*/ + +/*============= D E F I N E S ==============*/ + +/*============= E X P O R T S ==============*/ + +/** + * \brief Enable virtual converter test mode + * + * \param[in] device Context variable - Pointer to the APOLLO device data structure + * \param[in] links Target link select + * \param[in] enable Enable test mode, bit0 - virtual converter0, bit1 - virtual converter1, ... + * + * \return API_CMS_ERROR_OK API Completed Successfully + * \return <0 Failed. \ref adi_cms_error_e for details. + */ +int32_t adi_apollo_dformat_conv_test_mode_enable_set(adi_apollo_device_t *device, + const uint16_t links, + uint8_t enable); + + +#ifdef __cplusplus +extern "C" { +#endif + +uint32_t calc_jtx_dformat_base(int32_t link); + + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_DFORMAT_LOCAL_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_duc_local.h b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_duc_local.h new file mode 100644 index 00000000000000..8cd0bfe60d20b6 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_duc_local.h @@ -0,0 +1,37 @@ +/*! + * \brief DUC local defines and prototypes + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_CDUC + * @{ + */ +#ifndef __ADI_APOLLO_DUC_LOCAL_H__ +#define __ADI_APOLLO_DUC_LOCAL_H__ + +/*============= I N C L U D E S ============*/ + +/*============= D E F I N E S ==============*/ + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +uint32_t calc_tx_cduc_base(int32_t idx); +uint32_t calc_tx_fduc_base(int32_t idx); + +#ifndef CLIENT_IGNORE +#endif /* CLIENT_IGNORE */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_DUC_LOCAL_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_fddc.c b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_fddc.c new file mode 100644 index 00000000000000..f94103129423ca --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_fddc.c @@ -0,0 +1,269 @@ +/*! + * \brief Fine DDC functional block API implementation + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_FDDC + * @{ + */ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_fddc.h" +#include "adi_apollo_fnco.h" +#include "adi_apollo_ddc_local.h" +#include "adi_apollo_nco_local.h" +#include "adi_apollo_duc_local.h" +#include "adi_apollo_pfilt_local.h" +#include "adi_apollo_private_blk_sel_types.h" + +#include "adi_apollo_bf_rx_cddc.h" +#include "adi_apollo_bf_rx_fine_ddc.h" +#include "adi_apollo_bf_txrx_coarse_nco.h" +#include "adi_apollo_bf_txrx_fine_nco.h" +#include "adi_apollo_bf_txrx_pfilt_top.h" +#include "adi_apollo_bf_jtx_dformat.h" +#include "adi_apollo_bf_rx_misc.h" +#include "adi_apollo_bf_custom.h" +#include "adi_apollo_bf_rx_datin.h" + +#include "adi_apollo_config.h" +#include "adi_apollo_hal.h" +#include "adi_utils.h" + +/*==================== P U B L I C A P I C O D E ====================*/ + +int32_t adi_apollo_fddc_dcm_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t fddcs, adi_apollo_fddc_ratio_e dcm) +{ + int32_t err; + adi_apollo_blk_sel_t fddc; + uint8_t i; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_FDDC_BLK_SEL_MASK(fddcs); + + for(i = 0; i < ADI_APOLLO_FDDC_NUM; i ++) { + fddc = fddcs & (ADI_APOLLO_FDDC_A0 << i); + if (fddc > 0) { + regmap_base_addr = calc_rx_fddc_base(i); + + err = adi_apollo_hal_bf_set(device, BF_FINE_DDC_DEC_SEL_INFO(regmap_base_addr), dcm); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_fddc_link_num_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t fddcs, uint8_t link_num) +{ + int32_t err; + adi_apollo_blk_sel_t fddc; + uint8_t i; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_FDDC_BLK_SEL_MASK(fddcs); + + for(i = 0; i < ADI_APOLLO_FDDC_NUM; i ++) { + fddc = fddcs & (ADI_APOLLO_FDDC_A0 << i); + if (fddc > 0) { + regmap_base_addr = calc_rx_fddc_base(i); + + err = adi_apollo_hal_bf_set(device, BF_LINK_NUM_RX_FINE_DDC_INFO(regmap_base_addr), link_num); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_fddc_debug_clkoff_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t fddcs, uint8_t clkoff_n) +{ + int32_t err; + adi_apollo_blk_sel_t fddc; + uint8_t i; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_FDDC_BLK_SEL_MASK(fddcs); + + for(i = 0; i < ADI_APOLLO_FDDC_NUM; i ++) { + fddc = fddcs & (ADI_APOLLO_FDDC_A0 << i); + if (fddc > 0) { + regmap_base_addr = calc_rx_fddc_base(i); + + err = adi_apollo_hal_bf_set(device, BF_FDDC_CLK_EN_INFO(regmap_base_addr), clkoff_n); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_fddc_pgm(adi_apollo_device_t *device, adi_apollo_blk_sel_t fddcs, adi_apollo_fddc_pgm_t *config) +{ + int32_t err; + adi_apollo_blk_sel_t fddc; + uint8_t i; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(config); + ADI_APOLLO_FDDC_BLK_SEL_MASK(fddcs); + + for(i = 0; i < ADI_APOLLO_FDDC_NUM; i ++) { + fddc = fddcs & (ADI_APOLLO_FDDC_A0 << i); + if (fddc > 0) { + regmap_base_addr = calc_rx_fddc_base(i); + + err = adi_apollo_hal_bf_set(device, BF_FINE_DDC_DEC_SEL_INFO(regmap_base_addr), config->dcm); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_LINK_NUM_RX_FINE_DDC_INFO(regmap_base_addr), config->link_num); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_FDDC_CLK_EN_INFO(regmap_base_addr), config->debug_clkoff_n); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_HB1_GAIN_EN_RX_FINE_DDC_INFO(regmap_base_addr), config->hb1_gain_6db_en); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_fddc_inspect(adi_apollo_device_t *device, adi_apollo_blk_sel_t fddc, adi_apollo_fddc_inspect_t *fddc_inspect) +{ + int32_t err; + uint8_t i; + uint32_t regmap_base_addr = 0; + adi_apollo_blk_sel_t fddc_x; + adi_apollo_fnco_inspect_t fnco_inspect = {{0}}; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(fddc_inspect); + ADI_APOLLO_INVALID_PARAM_RETURN(adi_api_utils_num_selected(fddc) != 1); + ADI_APOLLO_FDDC_BLK_SEL_MASK(fddc); + + // For 8t8r, regmap is shared for each split FDUC (A0/A4, A1/A5, ...) + fddc_x = ((fddc & 0xF0F0) >> 4) | (fddc & 0x0F0F); + + for (i = 0; i < ADI_APOLLO_FDDC_NUM; i ++) { + if ((fddc & (ADI_APOLLO_FDDC_A0 << i)) > 0) { + regmap_base_addr = calc_rx_fddc_base(i); + + // FNCO A0-A3, B0-B3 + err = adi_apollo_fnco_inspect(device, ADI_APOLLO_RX, fddc_x, &fnco_inspect); + ADI_APOLLO_ERROR_RETURN(err); + fddc_inspect->dp_cfg.nco[0] = fnco_inspect.dp_cfg; + + // FNCO A4-A7, B4-B7 + if (device->dev_info.is_8t8r) { + err = adi_apollo_fnco_inspect(device, ADI_APOLLO_RX, (fddc_x << 4), &fnco_inspect); + ADI_APOLLO_ERROR_RETURN(err); + fddc_inspect->dp_cfg.nco[1] = fnco_inspect.dp_cfg; + } + + err = adi_apollo_hal_bf_get(device, BF_FINE_DDC_DEC_SEL_INFO(regmap_base_addr),(uint8_t*) &(fddc_inspect->dp_cfg.drc_ratio), sizeof(fddc_inspect->dp_cfg.drc_ratio)); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_LINK_NUM_RX_FINE_DDC_INFO(regmap_base_addr), &(fddc_inspect->dp_cfg.link_num), 1); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_get(device, BF_FDDC_CLK_EN_INFO(regmap_base_addr), &(fddc_inspect->dp_cfg.debug_fddc_clkoff_n), 1); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_get(device, BF_HB1_GAIN_EN_RX_FINE_DDC_INFO(regmap_base_addr), (uint8_t*) &(fddc_inspect->dp_cfg.hb1_gain_6db_en), sizeof(fddc_inspect->dp_cfg.hb1_gain_6db_en)); + ADI_APOLLO_ERROR_RETURN(err); + + /* Only one inspect per call */ + break; + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_fddc_dcm_bf_to_val(adi_apollo_device_t *device, adi_apollo_fddc_ratio_e bf_enum, uint32_t *val) +{ + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(val); + ADI_APOLLO_INVALID_PARAM_RETURN((bf_enum < ADI_APOLLO_FDDC_RATIO_1) || (bf_enum > ADI_APOLLO_FDDC_RATIO_64)); + + *val = 1u << bf_enum; + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_fddc_gain_enable_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t fddcs, uint8_t enable) +{ + int32_t err; + uint16_t i; + adi_apollo_blk_sel_t fddc; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_FDDC_BLK_SEL_MASK(fddcs); + + for (i = 0; i < ADI_APOLLO_FDDC_NUM; i++) { + fddc = fddcs & (ADI_APOLLO_FDDC_A0 << i); + if (fddc > 0) { + regmap_base_addr = calc_rx_fddc_base(i); + + err = adi_apollo_hal_bf_set(device, BF_HB1_GAIN_EN_RX_FINE_DDC_INFO(regmap_base_addr), enable); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_fddc_gain_enable_get(adi_apollo_device_t *device, adi_apollo_blk_sel_t fddcs, uint8_t *enable) +{ + int32_t err; + uint16_t i; + adi_apollo_blk_sel_t fddc; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(enable); + ADI_APOLLO_INVALID_PARAM_RETURN(adi_api_utils_num_selected(fddcs) != 1); + ADI_APOLLO_FDDC_BLK_SEL_MASK(fddcs); + + for (i = 0; i < ADI_APOLLO_FDDC_NUM; i++) { + fddc = fddcs & (ADI_APOLLO_FDDC_A0 << i); + if (fddc > 0) { + regmap_base_addr = calc_rx_fddc_base(i); + + err = adi_apollo_hal_bf_get(device, BF_HB1_GAIN_EN_RX_FINE_DDC_INFO(regmap_base_addr), enable, sizeof(*enable)); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + + +uint32_t calc_rx_fddc_base(int32_t fddc_index) +{ + static uint32_t rx_fddc_regmap[ADI_APOLLO_FDDC_NUM] = { + RX_FINE_DDC0_RX_SLICE_0_RX_DIGITAL0, RX_FINE_DDC1_RX_SLICE_0_RX_DIGITAL0, RX_FINE_DDC0_RX_SLICE_1_RX_DIGITAL0, RX_FINE_DDC1_RX_SLICE_1_RX_DIGITAL0, + RX_FINE_DDC0_RX_SLICE_0_RX_DIGITAL0, RX_FINE_DDC1_RX_SLICE_0_RX_DIGITAL0, RX_FINE_DDC0_RX_SLICE_1_RX_DIGITAL0, RX_FINE_DDC1_RX_SLICE_1_RX_DIGITAL0, + RX_FINE_DDC0_RX_SLICE_0_RX_DIGITAL1, RX_FINE_DDC1_RX_SLICE_0_RX_DIGITAL1, RX_FINE_DDC0_RX_SLICE_1_RX_DIGITAL1, RX_FINE_DDC1_RX_SLICE_1_RX_DIGITAL1, + RX_FINE_DDC0_RX_SLICE_0_RX_DIGITAL1, RX_FINE_DDC1_RX_SLICE_0_RX_DIGITAL1, RX_FINE_DDC0_RX_SLICE_1_RX_DIGITAL1, RX_FINE_DDC1_RX_SLICE_1_RX_DIGITAL1, + }; + return rx_fddc_regmap[fddc_index]; +} +/*! @} */ \ No newline at end of file diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_fduc.c b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_fduc.c new file mode 100644 index 00000000000000..2c95443d6b0627 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_fduc.c @@ -0,0 +1,364 @@ +/*! + * \brief Fine DUC functional block API implementation + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_FDUC + * @{ + */ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_fduc.h" +#include "adi_apollo_fnco.h" +#include "adi_apollo_duc_local.h" +#include "adi_apollo_txmisc_local.h" +#include "adi_apollo_txmisc_types.h" +#include "adi_apollo_private_blk_sel_types.h" + +#include "adi_apollo_bf_tx_fduc.h" +#include "adi_apollo_bf_tx_misc.h" +#include "adi_apollo_bf_custom.h" + +#include "adi_apollo_config.h" +#include "adi_apollo_hal.h" +#include "adi_utils.h" + +static const uint8_t fduc_sel_to_reg_bit[8] = { 0x01, 0x04, 0x10, 0x40, 0x02, 0x08, 0x20, 0x80 }; + +uint32_t calc_fduc_irq_offset(int32_t idx); + +/*==================== P U B L I C A P I C O D E ====================*/ + +int32_t adi_apollo_fduc_interp_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t fducs, uint8_t interp) +{ + int32_t err; + uint16_t i; + adi_apollo_blk_sel_t fduc; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_FDUC_BLK_SEL_MASK(fducs); + + for (i = 0; i < ADI_APOLLO_FDUC_NUM; i++) { + fduc = fducs & (ADI_APOLLO_FDUC_A0 << i); + if (fduc > 0) { + regmap_base_addr = calc_tx_fduc_base(i); + + err = adi_apollo_hal_bf_set(device, BF_FDUC_INTERP_INFO(regmap_base_addr), interp); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_fduc_subdp_gain_enable(adi_apollo_device_t *device, adi_apollo_blk_sel_t fducs, uint8_t enable) +{ + int32_t err; + uint16_t i; + adi_apollo_blk_sel_t fduc; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_FDUC_BLK_SEL_MASK(fducs); + + for (i = 0; i < ADI_APOLLO_FDUC_NUM; i++) { + fduc = fducs & (ADI_APOLLO_FDUC_A0 << i); + if (fduc > 0) { + regmap_base_addr = calc_tx_fduc_base(i); + + err = adi_apollo_hal_bf_set(device, BF_SUB_DP_GAIN_EN_INFO(regmap_base_addr), enable); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_fduc_subdp_gain_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t fducs, uint16_t gain) +{ + int32_t err; + uint16_t i; + adi_apollo_blk_sel_t fduc; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_FDUC_BLK_SEL_MASK(fducs); + + for (i = 0; i < ADI_APOLLO_FDUC_NUM; i++) { + fduc = fducs & (ADI_APOLLO_FDUC_A0 << i); + if (fduc > 0) { + regmap_base_addr = calc_tx_fduc_base(i); + + err = adi_apollo_hal_bf_set(device, BF_SUBDP_GAIN_INFO(regmap_base_addr), gain); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_fduc_int_tdly_hb_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t fducs, uint8_t dly) +{ + int32_t err; + uint16_t i; + adi_apollo_blk_sel_t fduc; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_FDUC_BLK_SEL_MASK(fducs); + + for (i = 0; i < ADI_APOLLO_FDUC_NUM; i++) { + fduc = fducs & (ADI_APOLLO_FDUC_A0 << i); + if (fduc > 0) { + regmap_base_addr = calc_tx_fduc_base(i); + + err = adi_apollo_hal_reg_set(device, REG_INT_TIME_DELAY_ADDR(regmap_base_addr), dly); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_fduc_pgm(adi_apollo_device_t *device, adi_apollo_blk_sel_t fducs, const adi_apollo_fduc_pgm_t *config) +{ + int32_t err; + uint16_t i; + adi_apollo_blk_sel_t fduc; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(config); + ADI_APOLLO_FDUC_BLK_SEL_MASK(fducs); + + for (i = 0; i < ADI_APOLLO_FDUC_NUM; i++) { + fduc = fducs & (ADI_APOLLO_FDUC_A0 << i); + + if (fduc > 0) { + regmap_base_addr = calc_tx_fduc_base(i); + + err = adi_apollo_hal_bf_set(device, BF_FDUC_INTERP_INFO(regmap_base_addr), config->interp); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_SUB_DP_GAIN_EN_INFO(regmap_base_addr), config->sub_dp_gain_en); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_SUBDP_GAIN_INFO(regmap_base_addr), config->subdp_gain); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_reg_set(device, REG_INT_TIME_DELAY_ADDR(regmap_base_addr), config->int_tdly_hb); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + /* FDUC SPI enable configuration */ + err = adi_apollo_fduc_enable_set(device, fducs, config->fduc_spien_en, config->fduc_spi_en); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_fduc_inspect(adi_apollo_device_t *device, adi_apollo_blk_sel_t fduc, adi_apollo_fduc_inspect_t *fduc_inspect) +{ + int32_t err; + uint8_t i; + uint8_t fduc_en_reg; + uint32_t regmap_base_addr = 0; + adi_apollo_blk_sel_t fduc_x; + adi_apollo_fnco_inspect_t fnco_inspect = {{0}}; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(fduc_inspect); + ADI_APOLLO_INVALID_PARAM_RETURN(adi_api_utils_num_selected(fduc) != 1); + ADI_APOLLO_FDUC_BLK_SEL_MASK(fduc); + + // For 8t8r, regmap is shared for each split FDUC (A0/A4, A1/A5, ...) + fduc_x = ((fduc & 0xF0F0) >> 4) | (fduc & 0x0F0F); + + for (i = 0; i < ADI_APOLLO_FDUC_NUM; i++) { + if ((fduc_x & (ADI_APOLLO_FDUC_A0 << i)) > 0) { + regmap_base_addr = calc_tx_fduc_base(i); + + // FNCO A0-A3, B0-B3 + err = adi_apollo_fnco_inspect(device, ADI_APOLLO_TX, fduc_x, &fnco_inspect); + ADI_APOLLO_ERROR_RETURN(err); + fduc_inspect->dp_cfg.nco[0] = fnco_inspect.dp_cfg; + + // FNCO A4-A7, B4-B7 + if (device->dev_info.is_8t8r) { + err = adi_apollo_fnco_inspect(device, ADI_APOLLO_TX, (fduc_x << 4), &fnco_inspect); + ADI_APOLLO_ERROR_RETURN(err); + fduc_inspect->dp_cfg.nco[1] = fnco_inspect.dp_cfg; + } + + err = adi_apollo_hal_bf_get(device, BF_FDUC_INTERP_INFO(regmap_base_addr), &(fduc_inspect->dp_cfg.drc_ratio), sizeof(fduc_inspect->dp_cfg.drc_ratio)); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_get(device, BF_SUB_DP_GAIN_EN_INFO(regmap_base_addr), (uint8_t *) &(fduc_inspect->dp_cfg.sub_dp_gain_en), 1); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_get(device, BF_SUBDP_GAIN_INFO(regmap_base_addr), (uint8_t *) &(fduc_inspect->dp_cfg.subdp_gain), 2); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_reg_get(device, REG_INT_TIME_DELAY_ADDR(regmap_base_addr), &(fduc_inspect->int_tdly_hb)); + ADI_APOLLO_ERROR_RETURN(err); + + /* FDUC SPI enable (these are usually disabled in favor of auto select) */ + regmap_base_addr = calc_tx_misc_base(i / ADI_APOLLO_FDUC_PER_SIDE_NUM); // Regmap base address for side + + err = adi_apollo_hal_bf_get(device, BF_FDUC_SPI_EN_INFO(regmap_base_addr), &(fduc_inspect->fduc_spien_en), sizeof(fduc_inspect->fduc_spien_en)); // spi control enable for side + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_reg_get(device, REG_FDUC_EN_SPI_ADDR(regmap_base_addr), &fduc_en_reg); + ADI_APOLLO_ERROR_RETURN(err); + fduc_inspect->fduc_spi_en = fduc_en_reg & fduc_sel_to_reg_bit[i % ADI_APOLLO_FDUC_PER_SIDE_NUM]; + + /* Only one inspect per call */ + break; + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_fduc_enable_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t fducs, uint8_t fduc_spien_en, uint8_t fduc_spi_en) +{ + int32_t err; + uint16_t i, j; + adi_apollo_blk_sel_t fduc; + uint32_t regmap_base_addr; + adi_apollo_blk_sel_t fducs_side; + uint8_t fduc_en_reg; + uint8_t fduc_en_reg_mask, fduc_en_reg_val; + uint8_t sel_mask = (1 << ADI_APOLLO_FDUC_PER_SIDE_NUM) - 1; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_FDUC_BLK_SEL_MASK(fducs); + + for (i = 0; i < ADI_APOLLO_NUM_SIDES; i++) { + + fducs_side = (fducs >> ((i == 0) ? 0 : ADI_APOLLO_FDUC_PER_SIDE_NUM)) & sel_mask; + + if (!fducs_side) { + continue; + } + + regmap_base_addr = calc_tx_misc_base(i); // Regmap base address for side + + err = adi_apollo_hal_bf_set(device, BF_FDUC_SPI_EN_INFO(regmap_base_addr), fduc_spien_en != 0 ? 1 : 0); // enable spi control for side + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_reg_get(device, REG_FDUC_EN_SPI_ADDR(regmap_base_addr), &fduc_en_reg); + ADI_APOLLO_ERROR_RETURN(err); + + fduc_en_reg_mask = 0; + fduc_en_reg_val = 0; + for (j = 0; j < ADI_APOLLO_FDUC_PER_SIDE_NUM; j++) { + fduc = fducs_side & (ADI_APOLLO_FDUC_A0 << j); + + /* Only modify selected FDUCs */ + if (fduc) { + fduc_en_reg_mask |= fduc_sel_to_reg_bit[j]; + fduc_en_reg_val |= (fduc_sel_to_reg_bit[j] & (fduc_spi_en ? 0xFF : 00)); + } + } + + fduc_en_reg &= ~(fduc_en_reg_mask); + fduc_en_reg |= fduc_en_reg_val; + + err = adi_apollo_hal_reg_set(device, REG_FDUC_EN_SPI_ADDR(regmap_base_addr), fduc_en_reg); // set the FDUC enable mask + ADI_APOLLO_ERROR_RETURN(err); + } + + return API_CMS_ERROR_OK; +} + + +int32_t adi_apollo_fduc_interp_bf_to_val(adi_apollo_device_t* device, adi_apollo_fduc_ratio_e bf_enum, uint32_t* val) +{ + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(val); + + switch (bf_enum) { + case ADI_APOLLO_FDUC_RATIO_1: + case ADI_APOLLO_FDUC_RATIO_2: + case ADI_APOLLO_FDUC_RATIO_4: + case ADI_APOLLO_FDUC_RATIO_8: + case ADI_APOLLO_FDUC_RATIO_16: + case ADI_APOLLO_FDUC_RATIO_32: + case ADI_APOLLO_FDUC_RATIO_64: + *val = bf_enum; + break; + + default: + ADI_APOLLO_LOG_ERR("Invalid adi_apollo_fduc_ratio_e enum"); + return API_CMS_ERROR_INVALID_PARAM; + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_fduc_irq_enable_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t fducs, uint8_t enable) +{ + int32_t err; + uint16_t fduc_index; + adi_apollo_blk_sel_t fduc; + uint32_t regmap_base_addr = 0, regmap_info = 0x600, regmap_offset = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_FDUC_BLK_SEL_MASK(fducs); + + for (fduc_index = 0; fduc_index < ADI_APOLLO_FDUC_NUM; fduc_index++) { + fduc = fducs & (ADI_APOLLO_FDUC_A0 << fduc_index); + if (fduc > 0) { + regmap_base_addr = calc_tx_misc_base(fduc_index / ADI_APOLLO_FDUC_PER_SIDE_NUM); + regmap_offset = calc_fduc_irq_offset(fduc % ADI_APOLLO_FDUC_PER_SIDE_NUM); + + err = adi_apollo_hal_bf_set(device, regmap_base_addr + regmap_offset, regmap_info, enable ? 0x3F : 0); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +uint32_t calc_tx_fduc_base(int32_t idx) +{ + static const uint32_t tx_fduc_regmap[ADI_APOLLO_FDUC_NUM] = { + TX_FDUC0_TX_SLICE_0_TX_DIGITAL0, TX_FDUC1_TX_SLICE_0_TX_DIGITAL0, TX_FDUC0_TX_SLICE_1_TX_DIGITAL0, TX_FDUC1_TX_SLICE_1_TX_DIGITAL0, + TX_FDUC0_TX_SLICE_0_TX_DIGITAL0, TX_FDUC1_TX_SLICE_0_TX_DIGITAL0, TX_FDUC0_TX_SLICE_1_TX_DIGITAL0, TX_FDUC1_TX_SLICE_1_TX_DIGITAL0, + TX_FDUC0_TX_SLICE_0_TX_DIGITAL1, TX_FDUC1_TX_SLICE_0_TX_DIGITAL1, TX_FDUC0_TX_SLICE_1_TX_DIGITAL1, TX_FDUC1_TX_SLICE_1_TX_DIGITAL1, + TX_FDUC0_TX_SLICE_0_TX_DIGITAL1, TX_FDUC1_TX_SLICE_0_TX_DIGITAL1, TX_FDUC0_TX_SLICE_1_TX_DIGITAL1, TX_FDUC1_TX_SLICE_1_TX_DIGITAL1, + }; + + return tx_fduc_regmap[idx]; +} + +uint32_t calc_fduc_irq_offset(int32_t idx) +{ + static const uint32_t tx_misc_regmap[ADI_APOLLO_FDUC_PER_SIDE_NUM] = { + REG_SL0_FDUC0_HB_IRQ_EN0_ADDR(0), + REG_SL0_FDUC1_IRQ_ADDR(0), + REG_SL1_FDUC0_HB_IRQ_EN0_ADDR(0), + REG_SL1_FDUC1_IRQ_ADDR(0) + }; + + return tx_misc_regmap[idx]; +} + +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_fnco.c b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_fnco.c new file mode 100644 index 00000000000000..41088c90526ab4 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_fnco.c @@ -0,0 +1,699 @@ +/*! + * \brief FNCO functional block API implementation + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_FNCO + * @{ + */ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_fnco.h" +#include "adi_apollo_nco_local.h" +#include "adi_apollo_private_blk_sel_types.h" + +#include "adi_apollo_bf_txrx_fine_nco.h" +#include "adi_apollo_bf_custom.h" + +#include "adi_apollo_config.h" +#include "adi_apollo_hal.h" + +#include "adi_utils.h" + +/*==================== P U B L I C A P I C O D E ====================*/ +int32_t adi_apollo_fnco_profile_load(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t fncos, + adi_apollo_nco_profile_word_sel_e word_sel, uint8_t first, uint32_t words[], uint32_t length) +{ + int32_t err; + uint16_t i, j; + adi_apollo_blk_sel_t fnco; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(words); + ADI_APOLLO_INVALID_PARAM_RETURN((first+length) > ADI_APOLLO_FNCO_PROFILE_NUM) + ADI_APOLLO_FNCO_BLK_SEL_MASK(fncos); + + for (i = 0; i < ADI_APOLLO_FNCO_NUM; i++) { + + fnco = fncos & (ADI_APOLLO_FNCO_A0 << i); + + if (fnco > 0) { + regmap_base_addr = (terminal == ADI_APOLLO_RX) ? calc_rx_fnco_base(i) : calc_tx_fnco_base(i); + + for(j = first; j < first+length; j++) { + err = adi_apollo_hal_paged_bf_set(device, BF_HOP_PROFILE_PAGE_INFO(regmap_base_addr), j); + ADI_APOLLO_ERROR_RETURN(err); + + if (word_sel == ADI_APOLLO_NCO_PROFILE_PHASE_INCREMENT) { + err = adi_apollo_hal_paged_bf_set(device, BF_HOP_PHASE_INC_INFO(regmap_base_addr), words[j-first]); + ADI_APOLLO_ERROR_RETURN(err); + } else { + err = adi_apollo_hal_paged_bf_set(device, BF_HOP_PHASE_OFFSET_INFO(regmap_base_addr), words[j-first]); + ADI_APOLLO_ERROR_RETURN(err); + } + } + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_fnco_hop_pgm(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t fncos, adi_apollo_fine_nco_hop_t *config) +{ + int32_t err; + adi_apollo_blk_sel_t fnco; + uint16_t i; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(config); + ADI_APOLLO_FNCO_BLK_SEL_MASK(fncos); + + for(i = 0; i < ADI_APOLLO_FNCO_NUM; i ++) { + fnco = fncos & (ADI_APOLLO_FNCO_A0 << i); + if (fnco > 0) { + regmap_base_addr = (terminal == ADI_APOLLO_RX) ? calc_rx_fnco_base(i) : calc_tx_fnco_base(i); + + err = adi_apollo_hal_bf_set(device, BF_TRIG_HOP_SEL0_INFO(regmap_base_addr), config->nco_trig_hop_sel); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_FREQ_COHRNCE_TXRX_FINE_NCO_INFO(regmap_base_addr), config->phase_handling); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_AUTOFLIP_INCDIR_FTW_TXRX_FINE_NCO_INFO(regmap_base_addr), + (config->phase_inc_auto_mode == ADI_APOLLO_NCO_AUTO_HOP_FLIP) ? 1 : 0); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_AUTOFLIP_INCDIR_PHOFST_TXRX_FINE_NCO_INFO(regmap_base_addr), + (config->phase_offset_auto_mode == ADI_APOLLO_NCO_AUTO_HOP_FLIP) ? 1 : 0); + ADI_APOLLO_ERROR_RETURN(err); + + + err = adi_apollo_hal_bf_set(device, BF_HOP_HIGHLIMIT_PR0_INFO(regmap_base_addr), config->phase_inc_high_limit); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_HOP_LOWLIMIT_PR0_INFO(regmap_base_addr), config->phase_inc_low_limit); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_HOP_HIGHLIMIT_PR2_INFO(regmap_base_addr), config->phase_offset_high_limit); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_HOP_LOWLIMIT_PR2_INFO(regmap_base_addr), config->phase_offset_low_limit); + ADI_APOLLO_ERROR_RETURN(err); + + /* if phase_inc and phase_offset are both in auto_flip mode then auto inc/dec register is not programmed */ + if (config->phase_inc_auto_mode != ADI_APOLLO_NCO_AUTO_HOP_FLIP && config->phase_offset_auto_mode != ADI_APOLLO_NCO_AUTO_HOP_FLIP) { + err = adi_apollo_hal_bf_set(device, BF_AUTO_INC_DECB_FTW_TXRX_FINE_NCO_INFO(regmap_base_addr), config->phase_inc_auto_mode); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_AUTO_INC_DECB_PHOFST_TXRX_FINE_NCO_INFO(regmap_base_addr), config->phase_offset_auto_mode); + ADI_APOLLO_ERROR_RETURN(err); + } else if (config->phase_inc_auto_mode != ADI_APOLLO_NCO_AUTO_HOP_FLIP) { + err = adi_apollo_hal_bf_set(device, BF_AUTO_INC_DECB_FTW_TXRX_FINE_NCO_INFO(regmap_base_addr), config->phase_inc_auto_mode); + ADI_APOLLO_ERROR_RETURN(err); + } else if (config->phase_offset_auto_mode != ADI_APOLLO_NCO_AUTO_HOP_FLIP) { + err = adi_apollo_hal_bf_set(device, BF_AUTO_INC_DECB_PHOFST_TXRX_FINE_NCO_INFO(regmap_base_addr), config->phase_offset_auto_mode); + ADI_APOLLO_ERROR_RETURN(err); + } + + err = adi_apollo_hal_bf_set(device, BF_PROFILE_SEL_MODE_TXRX_FINE_NCO_INFO(regmap_base_addr), config->profile_sel_mode); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_TXRX_GPIOSHARE_INFO(regmap_base_addr), + (config->profile_sel_mode == ADI_APOLLO_NCO_CHAN_SEL_TRIG_GPIO || config->profile_sel_mode == ADI_APOLLO_NCO_CHAN_SEL_DIRECT_GPIO) ? 1 : 0); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_HOP_CTRL_INIT_TXRX_FINE_NCO_INFO(regmap_base_addr), 0); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_HOP_CTRL_INIT_TXRX_FINE_NCO_INFO(regmap_base_addr), 1); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_fnco_chan_pgm(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t fncos, uint8_t profile_num, adi_apollo_fine_nco_chan_pgm_t *config) +{ + int32_t err; + adi_apollo_blk_sel_t fnco; + uint16_t i; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(config); + ADI_APOLLO_FNCO_BLK_SEL_MASK(fncos); + + for(i = 0; i < ADI_APOLLO_FNCO_NUM; i ++) { + fnco = fncos & (ADI_APOLLO_FNCO_A0 << i); + if (fnco > 0) { + regmap_base_addr = (terminal == ADI_APOLLO_RX) ? calc_rx_fnco_base(i) : calc_tx_fnco_base(i); + + err = adi_apollo_hal_paged_bf_set(device, BF_HOP_PROFILE_PAGE_INFO(regmap_base_addr), profile_num); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_HOP_PHASE_INC_INFO(regmap_base_addr), config->drc_phase_inc); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_HOP_PHASE_OFFSET_INFO(regmap_base_addr), config->drc_phase_offset); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_fnco_main_pgm(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t fncos, adi_apollo_fine_nco_main_pgm_t *config) +{ + int32_t err; + adi_apollo_blk_sel_t fnco; + uint16_t i; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(config); + ADI_APOLLO_FNCO_BLK_SEL_MASK(fncos); + + for(i = 0; i < ADI_APOLLO_FNCO_NUM; i ++) { + fnco = fncos & (ADI_APOLLO_FNCO_A0 << i); + if (fnco > 0) { + regmap_base_addr = (terminal == ADI_APOLLO_RX) ? calc_rx_fnco_base(i) : calc_tx_fnco_base(i); + + err = adi_apollo_hal_bf_set(device, BF_MAIN_PHASE_INC_INFO(regmap_base_addr), config->main_phase_inc); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_MAIN_PHASE_OFFSET_INFO(regmap_base_addr), config->main_phase_offset); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_DRC0_PHASE_INC_FRAC_A_INFO(regmap_base_addr), config->drc_phase_inc_frac_a); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_DRC0_PHASE_INC_FRAC_B_INFO(regmap_base_addr), config->drc_phase_inc_frac_b); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_fnco_pgm(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t fncos, adi_apollo_fnco_pgm_t *config) +{ + int32_t err; + adi_apollo_blk_sel_t fnco; + uint16_t i; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(config); + ADI_APOLLO_FNCO_BLK_SEL_MASK(fncos); + + for(i = 0; i < ADI_APOLLO_FNCO_NUM; i ++) { + fnco = fncos & (ADI_APOLLO_FNCO_A0 << i); + if (fnco > 0) { + regmap_base_addr = (terminal == ADI_APOLLO_RX) ? calc_rx_fnco_base(i) : calc_tx_fnco_base(i); + + err = adi_apollo_hal_bf_set(device, BF_DRC_IF_MODE_TXRX_FINE_NCO_INFO(regmap_base_addr), config->if_mode); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_DRC_MXR_SEL_INFO(regmap_base_addr), config->mixer_sel); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_CMPLX_MXR_MULT_SCALE_EN_INFO(regmap_base_addr), config->cmplx_mxr_scale_en); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_HOP_MODE_EN_INFO(regmap_base_addr), config->hop_mode_en); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_FINE_DRC_EN0_INFO(regmap_base_addr), config->drc_en); + + err = adi_apollo_hal_bf_set(device, BF_FDRC_CLK_EN_INFO(regmap_base_addr),config->debug_drc_clkoff_n); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_PROFILE_SEL_MODE_TXRX_FINE_NCO_INFO(regmap_base_addr), config->profile_sel_mode); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_TXRX_GPIOSHARE_INFO(regmap_base_addr), + (config->profile_sel_mode == ADI_APOLLO_NCO_CHAN_SEL_TRIG_GPIO || config->profile_sel_mode == ADI_APOLLO_NCO_CHAN_SEL_DIRECT_GPIO) ? 1 : 0); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_paged_bf_set(device, BF_HOP_PROFILE_PAGE_INFO(regmap_base_addr), config->profile_num); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_REGMAP_HOPPROF_INFO(regmap_base_addr), config->profile_num); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_MAIN_PHASE_INC_INFO(regmap_base_addr), config->main_phase_inc); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_MAIN_PHASE_OFFSET_INFO(regmap_base_addr), config->main_phase_offset); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_DRC0_PHASE_INC_FRAC_A_INFO(regmap_base_addr), config->drc_phase_inc_frac_a); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_DRC0_PHASE_INC_FRAC_B_INFO(regmap_base_addr), config->drc_phase_inc_frac_b); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_MIXER_TEST_MODE_VAL_TXRX_FINE_NCO_INFO(regmap_base_addr), config->dc_testmode_value); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_fnco_main_phase_inc_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t fncos, uint64_t ftw) +{ + int32_t err; + uint16_t i; + adi_apollo_blk_sel_t fnco; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_FNCO_BLK_SEL_MASK(fncos); + + for (i = 0; i < ADI_APOLLO_FNCO_NUM; i++) { + fnco = fncos & (ADI_APOLLO_FNCO_A0 << i); + if (fnco > 0) { + regmap_base_addr = (terminal == ADI_APOLLO_RX) ? calc_rx_fnco_base(i) : calc_tx_fnco_base(i); + + err = adi_apollo_hal_bf_set(device, BF_MAIN_PHASE_INC_INFO(regmap_base_addr), ftw); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_fnco_main_phase_offset_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t fncos, uint64_t pow) +{ + int32_t err; + uint16_t i; + adi_apollo_blk_sel_t fnco; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_FNCO_BLK_SEL_MASK(fncos); + + for (i = 0; i < ADI_APOLLO_FNCO_NUM; i++) { + fnco = fncos & (ADI_APOLLO_FNCO_A0 << i); + if (fnco > 0) { + regmap_base_addr = (terminal == ADI_APOLLO_RX) ? calc_rx_fnco_base(i) : calc_tx_fnco_base(i); + + err = adi_apollo_hal_bf_set(device, BF_MAIN_PHASE_OFFSET_INFO(regmap_base_addr), pow); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_fnco_inspect(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t fnco, adi_apollo_fnco_inspect_t *fnco_inspect) +{ + int32_t err; + uint16_t i, j; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(fnco_inspect); + ADI_APOLLO_INVALID_PARAM_RETURN(adi_api_utils_num_selected(fnco) != 1); + ADI_APOLLO_FNCO_BLK_SEL_MASK(fnco); + + for(i = 0; i < ADI_APOLLO_FNCO_NUM; i ++) { + if ((fnco & (ADI_APOLLO_FNCO_A0 << i)) > 0) { + regmap_base_addr = (terminal == ADI_APOLLO_RX) ? calc_rx_fnco_base(i) : calc_tx_fnco_base(i); + + err = adi_apollo_hal_bf_get(device, BF_DRC_IF_MODE_TXRX_FINE_NCO_INFO(regmap_base_addr), &(fnco_inspect->dp_cfg.nco_if_mode), sizeof(fnco_inspect->dp_cfg.nco_if_mode)); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_DRC_MXR_SEL_INFO(regmap_base_addr), &(fnco_inspect->dp_cfg.drc_mxr_sel), sizeof(fnco_inspect->dp_cfg.drc_mxr_sel)); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_CMPLX_MXR_MULT_SCALE_EN_INFO(regmap_base_addr), &(fnco_inspect->dp_cfg.cmplx_mxr_mult_scale_en), sizeof(fnco_inspect->dp_cfg.cmplx_mxr_mult_scale_en)); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_HOP_MODE_EN_INFO(regmap_base_addr), &(fnco_inspect->hop_mode_en), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_FINE_DRC_EN0_INFO(regmap_base_addr), (uint8_t *) &(fnco_inspect->dp_cfg.drc_en), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_FDRC_CLK_EN_INFO(regmap_base_addr), + (uint8_t *) &(fnco_inspect->dp_cfg.debug_fdrc_clkoff_n), sizeof(fnco_inspect->dp_cfg.debug_fdrc_clkoff_n)); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_get(device, BF_TRIG_HOP_SEL0_INFO(regmap_base_addr), + (uint8_t *) &(fnco_inspect->dp_cfg.nco_trig_hop_sel), sizeof(fnco_inspect->dp_cfg.nco_trig_hop_sel)); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_get(device, BF_AUTO_INC_DECB_FTW_TXRX_FINE_NCO_INFO(regmap_base_addr), + (uint8_t *) &(fnco_inspect->dp_cfg.nco_auto_inc_dec_freq), sizeof(fnco_inspect->dp_cfg.nco_auto_inc_dec_freq)); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_get(device, BF_AUTO_INC_DECB_PHOFST_TXRX_FINE_NCO_INFO(regmap_base_addr), + (uint8_t *) &(fnco_inspect->dp_cfg.nco_auto_inc_dec_phase), sizeof(fnco_inspect->dp_cfg.nco_auto_inc_dec_phase)); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_get(device, BF_PROFILE_SEL_MODE_TXRX_FINE_NCO_INFO(regmap_base_addr), + (uint8_t *) &(fnco_inspect->dp_cfg.nco_profile_sel_mode), sizeof(fnco_inspect->dp_cfg.nco_profile_sel_mode)); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_get(device, BF_HOP_PROFILE_PAGE_INFO(regmap_base_addr), &(fnco_inspect->profile_num), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_REGMAP_HOPPROF_INFO(regmap_base_addr), &(fnco_inspect->regmap_hopprof), 1); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_get(device, BF_MAIN_PHASE_INC_INFO(regmap_base_addr), (uint8_t *) (&(fnco_inspect->dp_cfg.nco_phase_inc)), 8); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_MAIN_PHASE_OFFSET_INFO(regmap_base_addr), (uint8_t *) (&(fnco_inspect->dp_cfg.nco_phase_offset)), 8); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_DRC0_PHASE_INC_FRAC_A_INFO(regmap_base_addr), (uint8_t *) (&(fnco_inspect->dp_cfg.nco_phase_inc_frac_a)), 8); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_DRC0_PHASE_INC_FRAC_B_INFO(regmap_base_addr), (uint8_t *) (&(fnco_inspect->dp_cfg.nco_phase_inc_frac_b)), 8); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_get(device, BF_MIXER_TEST_MODE_VAL_TXRX_FINE_NCO_INFO(regmap_base_addr), + (uint8_t *) (&(fnco_inspect->dp_cfg.dc_testmode_value)), sizeof(fnco_inspect->dp_cfg.dc_testmode_value)); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_get(device, BF_DRC0_ACTIVE_PHASE_INC_INFO(regmap_base_addr), (uint8_t *) (&(fnco_inspect->active_phase_inc)), 8); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_DRC0_ACTIVE_PHASE_OFFSET_INFO(regmap_base_addr), (uint8_t *) (&(fnco_inspect->active_phase_offset)), 8); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_get(device, BF_DRC0_PHASE_DITHER_EN_INFO(regmap_base_addr), &(fnco_inspect->drc_phase_dither_en), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_DRC0_AMP_DITHER_EN_INFO(regmap_base_addr), &(fnco_inspect->drc_amp_dither_en), 1); + ADI_APOLLO_ERROR_RETURN(err); + + for (j = 0; j < ADI_APOLLO_FNCO_PROFILE_NUM; j++) { + err = adi_apollo_hal_paged_reg_set(device, REG_HOP_PROFILE_PAGE_ADDR(regmap_base_addr), j); // only bf in reg, use wr reg + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_get(device, BF_HOP_PHASE_INC_INFO(regmap_base_addr), (uint8_t *) &(fnco_inspect->dp_cfg.nco_phase_inc_words[j]), 4); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_get(device, BF_HOP_PHASE_OFFSET_INFO(regmap_base_addr), (uint8_t *) &(fnco_inspect->dp_cfg.nco_phase_offset_words[j]), 4); + ADI_APOLLO_ERROR_RETURN(err); + } + + /* Return REG_HOP_PROFILE_PAGE_ADDR back to original state */ + err = adi_apollo_hal_paged_reg_set(device, REG_HOP_PROFILE_PAGE_ADDR(regmap_base_addr), fnco_inspect->profile_num); + ADI_APOLLO_ERROR_RETURN(err); + + /* Only one inspect per call */ + break; + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_fnco_mode_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t fncos, adi_apollo_nco_mixer_mode_e mode) +{ + int32_t err; + uint16_t i; + adi_apollo_blk_sel_t fnco; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_FNCO_BLK_SEL_MASK(fncos); + + for (i = 0; i < ADI_APOLLO_FNCO_NUM; i++) { + fnco = fncos & (ADI_APOLLO_FNCO_A0 << i); + if (fnco > 0) { + regmap_base_addr = (terminal == ADI_APOLLO_RX) ? calc_rx_fnco_base(i) : calc_tx_fnco_base(i); + + err = adi_apollo_hal_bf_set(device, BF_DRC_IF_MODE_TXRX_FINE_NCO_INFO(regmap_base_addr), mode); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_fnco_mixer_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t fncos, adi_apollo_drc_mixer_sel_e mixer) +{ + int32_t err; + uint16_t i; + adi_apollo_blk_sel_t fnco; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_FNCO_BLK_SEL_MASK(fncos); + + for (i = 0; i < ADI_APOLLO_FNCO_NUM; i++) { + fnco = fncos & (ADI_APOLLO_FNCO_A0 << i); + if (fnco > 0) { + regmap_base_addr = (terminal == ADI_APOLLO_RX) ? calc_rx_fnco_base(i) : calc_tx_fnco_base(i); + + err = adi_apollo_hal_bf_set(device, BF_DRC_MXR_SEL_INFO(regmap_base_addr), mixer); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_fnco_enable_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t fncos, uint8_t enable) +{ + int32_t err; + uint16_t i; + adi_apollo_blk_sel_t fnco; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_FNCO_BLK_SEL_MASK(fncos); + + for (i = 0; i < ADI_APOLLO_FNCO_NUM; i++) { + fnco = fncos & (ADI_APOLLO_FNCO_A0 << i); + if (fnco > 0) { + regmap_base_addr = (terminal == ADI_APOLLO_RX) ? calc_rx_fnco_base(i) : calc_tx_fnco_base(i); + + err = adi_apollo_hal_bf_set(device, BF_FINE_DRC_EN0_INFO(regmap_base_addr), enable); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_fnco_test_mode_val_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t fncos, uint16_t val) +{ + int32_t err; + uint16_t i; + adi_apollo_blk_sel_t fnco; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_FNCO_BLK_SEL_MASK(fncos); + + for (i = 0; i < ADI_APOLLO_FNCO_NUM; i++) { + fnco = fncos & (ADI_APOLLO_FNCO_A0 << i); + if (fnco > 0) { + regmap_base_addr = (terminal == ADI_APOLLO_RX) ? calc_rx_fnco_base(i) : calc_tx_fnco_base(i); + + err = adi_apollo_hal_bf_set(device, BF_MIXER_TEST_MODE_VAL_TXRX_FINE_NCO_INFO(regmap_base_addr), val); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_fnco_ftw_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t fncos, uint8_t profile_num, uint8_t active_en, uint32_t ftw) +{ + int32_t err; + uint16_t i; + adi_apollo_blk_sel_t fnco; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(profile_num > ADI_APOLLO_FNCO_PROFILE_NUM-1); + ADI_APOLLO_FNCO_BLK_SEL_MASK(fncos); + + for (i = 0; i < ADI_APOLLO_FNCO_NUM; i++) { + fnco = fncos & (ADI_APOLLO_FNCO_A0 << i); + if (fnco > 0) { + regmap_base_addr = (terminal == ADI_APOLLO_RX) ? calc_rx_fnco_base(i) : calc_tx_fnco_base(i); + + /* Select profile to update */ + err = adi_apollo_hal_paged_bf_set(device, BF_HOP_PROFILE_PAGE_INFO(regmap_base_addr), profile_num); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_HOP_PHASE_INC_INFO(regmap_base_addr), ftw); + ADI_APOLLO_ERROR_RETURN(err); + + if (active_en) { + err = adi_apollo_hal_bf_set(device, BF_REGMAP_HOPPROF_INFO(regmap_base_addr), profile_num); + ADI_APOLLO_ERROR_RETURN(err); + } + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_fnco_pow_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t fncos, uint8_t profile_num, uint8_t active_en, uint32_t pow) +{ + int32_t err; + uint16_t i; + adi_apollo_blk_sel_t fnco; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(profile_num > ADI_APOLLO_FNCO_PROFILE_NUM-1); + ADI_APOLLO_FNCO_BLK_SEL_MASK(fncos); + + for (i = 0; i < ADI_APOLLO_FNCO_NUM; i++) { + fnco = fncos & (ADI_APOLLO_FNCO_A0 << i); + if (fnco > 0) { + regmap_base_addr = (terminal == ADI_APOLLO_RX) ? calc_rx_fnco_base(i) : calc_tx_fnco_base(i); + + /* Select profile to update */ + err = adi_apollo_hal_paged_bf_set(device, BF_HOP_PROFILE_PAGE_INFO(regmap_base_addr), profile_num); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_HOP_PHASE_OFFSET_INFO(regmap_base_addr), pow); + ADI_APOLLO_ERROR_RETURN(err); + + if (active_en) { + err = adi_apollo_hal_bf_set(device, BF_REGMAP_HOPPROF_INFO(regmap_base_addr), profile_num); + ADI_APOLLO_ERROR_RETURN(err); + } + } + } + + return API_CMS_ERROR_OK; +} + + +int32_t adi_apollo_fnco_profile_sel_mode_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t fncos, adi_apollo_nco_profile_sel_mode_e profile_sel_mode) +{ + int32_t err; + uint16_t i; + adi_apollo_blk_sel_t fnco; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_FNCO_BLK_SEL_MASK(fncos); + + for (i = 0; i < ADI_APOLLO_FNCO_NUM; i++) { + fnco = fncos & (ADI_APOLLO_FNCO_A0 << i); + if (fnco > 0) { + regmap_base_addr = (terminal == ADI_APOLLO_RX) ? calc_rx_fnco_base(i) : calc_tx_fnco_base(i); + + err = adi_apollo_hal_bf_set(device, BF_PROFILE_SEL_MODE_TXRX_FINE_NCO_INFO(regmap_base_addr), profile_sel_mode); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_TXRX_GPIOSHARE_INFO(regmap_base_addr), + (profile_sel_mode == ADI_APOLLO_NCO_CHAN_SEL_TRIG_GPIO || profile_sel_mode == ADI_APOLLO_NCO_CHAN_SEL_DIRECT_GPIO) ? 1 : 0); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + + +int32_t adi_apollo_fnco_active_profile_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t fncos, uint8_t profile_num) +{ + int32_t err; + uint16_t i; + adi_apollo_blk_sel_t fnco; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(profile_num > ADI_APOLLO_FNCO_PROFILE_NUM-1); + ADI_APOLLO_FNCO_BLK_SEL_MASK(fncos); + + for (i = 0; i < ADI_APOLLO_FNCO_NUM; i++) { + fnco = fncos & (ADI_APOLLO_FNCO_A0 << i); + if (fnco > 0) { + regmap_base_addr = (terminal == ADI_APOLLO_RX) ? calc_rx_fnco_base(i) : calc_tx_fnco_base(i); + + err = adi_apollo_hal_bf_set(device, BF_REGMAP_HOPPROF_INFO(regmap_base_addr), profile_num); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_fnco_hop_enable(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t fncos, uint8_t hop_en) +{ + int32_t err; + uint16_t i; + adi_apollo_blk_sel_t fnco; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_FNCO_BLK_SEL_MASK(fncos); + + for (i = 0; i < ADI_APOLLO_FNCO_NUM; i++) { + fnco = fncos & (ADI_APOLLO_FNCO_A0 << i); + if (fnco > 0) { + regmap_base_addr = (terminal == ADI_APOLLO_RX) ? calc_rx_fnco_base(i) : calc_tx_fnco_base(i); + + err = adi_apollo_hal_bf_set(device, BF_HOP_MODE_EN_INFO(regmap_base_addr), hop_en); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_fnco_next_hop_num_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t fncos, int16_t hop_num_freq, int16_t hop_num_phase) +{ + int32_t err; + uint16_t i; + adi_apollo_blk_sel_t fnco; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(hop_num_freq > ADI_APOLLO_FNCO_PROFILE_NUM); + ADI_APOLLO_INVALID_PARAM_RETURN(hop_num_phase > ADI_APOLLO_FNCO_PROFILE_NUM); + ADI_APOLLO_FNCO_BLK_SEL_MASK(fncos); + + for (i = 0; i < ADI_APOLLO_FNCO_NUM; i++) { + fnco = fncos & (ADI_APOLLO_FNCO_A0 << i); + if (fnco > 0) { + regmap_base_addr = (terminal == ADI_APOLLO_RX) ? calc_rx_fnco_base(i) : calc_tx_fnco_base(i); + + err = adi_apollo_hal_reg_set(device, REG_NEXT_HOP_NUMBER_PR0_ADDR(regmap_base_addr), hop_num_freq); /* Freq hop num */ + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_reg_set(device, REG_NEXT_HOP_NUMBER_PR2_ADDR(regmap_base_addr), hop_num_phase); /* Phase hop num */ + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + + +uint32_t calc_tx_fnco_base(int32_t idx) +{ + static const uint32_t tx_fnco_regmap[ADI_APOLLO_FNCO_NUM] = { + TX_FINE_NCO0_TX_SLICE_0_TX_DIGITAL0, TX_FINE_NCO2_TX_SLICE_0_TX_DIGITAL0, + TX_FINE_NCO0_TX_SLICE_1_TX_DIGITAL0, TX_FINE_NCO2_TX_SLICE_1_TX_DIGITAL0, + TX_FINE_NCO1_TX_SLICE_0_TX_DIGITAL0, TX_FINE_NCO3_TX_SLICE_0_TX_DIGITAL0, + TX_FINE_NCO1_TX_SLICE_1_TX_DIGITAL0, TX_FINE_NCO3_TX_SLICE_1_TX_DIGITAL0, + + TX_FINE_NCO0_TX_SLICE_0_TX_DIGITAL1, TX_FINE_NCO2_TX_SLICE_0_TX_DIGITAL1, + TX_FINE_NCO0_TX_SLICE_1_TX_DIGITAL1, TX_FINE_NCO2_TX_SLICE_1_TX_DIGITAL1, + TX_FINE_NCO1_TX_SLICE_0_TX_DIGITAL1, TX_FINE_NCO3_TX_SLICE_0_TX_DIGITAL1, + TX_FINE_NCO1_TX_SLICE_1_TX_DIGITAL1, TX_FINE_NCO3_TX_SLICE_1_TX_DIGITAL1 + }; + + return tx_fnco_regmap[idx]; +} + +uint32_t calc_rx_fnco_base(int32_t idx) +{ + static uint32_t rx_fine_nco_regmap[ADI_APOLLO_FNCO_NUM] = { + RX_FINE_NCO0_RX_SLICE_0_RX_DIGITAL0, RX_FINE_NCO2_RX_SLICE_0_RX_DIGITAL0, RX_FINE_NCO0_RX_SLICE_1_RX_DIGITAL0, RX_FINE_NCO2_RX_SLICE_1_RX_DIGITAL0, + RX_FINE_NCO1_RX_SLICE_0_RX_DIGITAL0, RX_FINE_NCO3_RX_SLICE_0_RX_DIGITAL0, RX_FINE_NCO1_RX_SLICE_1_RX_DIGITAL0, RX_FINE_NCO3_RX_SLICE_1_RX_DIGITAL0, + RX_FINE_NCO0_RX_SLICE_0_RX_DIGITAL1, RX_FINE_NCO2_RX_SLICE_0_RX_DIGITAL1, RX_FINE_NCO0_RX_SLICE_1_RX_DIGITAL1, RX_FINE_NCO2_RX_SLICE_1_RX_DIGITAL1, + RX_FINE_NCO1_RX_SLICE_0_RX_DIGITAL1, RX_FINE_NCO3_RX_SLICE_0_RX_DIGITAL1, RX_FINE_NCO1_RX_SLICE_1_RX_DIGITAL1, RX_FINE_NCO3_RX_SLICE_1_RX_DIGITAL1 + }; + return rx_fine_nco_regmap[idx]; +} +/*! @} */ \ No newline at end of file diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_fsrc.c b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_fsrc.c new file mode 100644 index 00000000000000..a8d5a37bfcc6ef --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_fsrc.c @@ -0,0 +1,308 @@ +/*! + * \brief APIs for FSRC + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_FSRC + * @{ + */ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_fsrc.h" +#include "adi_apollo_fsrc_local.h" +#include "adi_apollo_dformat_local.h" +#include "adi_apollo_private_device.h" +#include "adi_apollo_private_blk_sel_types.h" + +#include "adi_apollo_bf_txrx_fsrc.h" +#include "adi_apollo_bf_jtx_dformat.h" +#include "adi_apollo_bf_custom.h" + +#include "adi_apollo_config.h" +#include "adi_apollo_hal.h" + +#include "adi_utils.h" + +/*==================== P U B L I C A P I C O D E ====================*/ + +int32_t adi_apollo_fsrc_pgm(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t fsrcs, adi_apollo_fsrc_pgm_t *config) +{ + int32_t err; + uint8_t i; + adi_apollo_blk_sel_t fsrc; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_DEV_FEAT_LOCKOUT_RETURN(terminal, ADI_APOLLO_EC_FSRC_LOCK); + ADI_APOLLO_NULL_POINTER_RETURN(config); + ADI_APOLLO_FSRC_BLK_SEL_MASK(fsrcs); + + /* Set the rate parameters */ + err = adi_apollo_fsrc_rate_set(device, terminal, fsrcs, + config->fsrc_rate_int, config->fsrc_rate_frac_a, config->fsrc_rate_frac_b, config->gain_reduction); + ADI_APOLLO_ERROR_RETURN(err); + + /* Set the mode 1x */ + err = adi_apollo_fsrc_mode_1x_enable_set(device, terminal, fsrcs, config->fsrc_1x_mode); + ADI_APOLLO_ERROR_RETURN(err); + + for(i = 0; i < ADI_APOLLO_FSRC_NUM; i += 2) { //Common bitfield for 0 & 1 fsrcs + fsrc = fsrcs & ((ADI_APOLLO_FSRC_A0 << i) | (ADI_APOLLO_FSRC_A0 << (i+1))); + if (fsrc > 0) { + regmap_base_addr = calc_fsrc_base(terminal, i); + + err = adi_apollo_hal_bf_set(device, BF_SAMPLE_FRAC_DELAY_INFO(regmap_base_addr), config->sample_frac_delay); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_PTR_SYNCRSTVAL_REGMAP_OVERWRITE_INFO(regmap_base_addr), config->ptr_overwrite); + ADI_APOLLO_ERROR_RETURN(err); + if (config->ptr_overwrite == 1) { + err = adi_apollo_hal_bf_set(device, BF_PTR_SYNCRSTVAL_INFO(regmap_base_addr), config->ptr_syncrstval); + ADI_APOLLO_ERROR_RETURN(err); + } + err = adi_apollo_hal_bf_set(device, BF_FSRC_DATA_MULT_DITHER_EN_INFO(regmap_base_addr), config->fsrc_data_mult_dither_en); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_FSRC_DITHER_EN_INFO(regmap_base_addr), config->fsrc_dither_en); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_FSRC_4T4R_SPLIT_INFO(regmap_base_addr), config->fsrc_4t4r_split); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_FSRC_BYPASS_INFO(regmap_base_addr), config->fsrc_bypass); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + /* Set the stream enables */ + for(i = 0; i < ADI_APOLLO_FSRC_NUM; i ++) { + fsrc = fsrcs & (ADI_APOLLO_FSRC_A0 << i); + if (fsrc > 0) { + regmap_base_addr = calc_fsrc_base(terminal, i); + + if (i % 2 == 0) { + err = adi_apollo_hal_bf_set(device, BF_FSRC_EN0_INFO(regmap_base_addr), config->fsrc_en0); + ADI_APOLLO_ERROR_RETURN(err); + } else { + err = adi_apollo_hal_bf_set(device, BF_FSRC_EN1_INFO(regmap_base_addr), config->fsrc_en1); + ADI_APOLLO_ERROR_RETURN(err); + } + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_fsrc_inspect(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t fsrc, adi_apollo_fsrc_inspect_t *fsrc_inspect) +{ + int32_t err; + uint8_t i; + adi_apollo_blk_sel_t fsrc_temp; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_DEV_FEAT_LOCKOUT_RETURN(terminal, ADI_APOLLO_EC_FSRC_LOCK); + ADI_APOLLO_NULL_POINTER_RETURN(fsrc_inspect); + ADI_APOLLO_INVALID_PARAM_RETURN(adi_api_utils_num_selected(fsrc)!= 1); + ADI_APOLLO_FSRC_BLK_SEL_MASK(fsrc); + + for(i = 0; i < ADI_APOLLO_FSRC_NUM; i += 2) { //Common bitfield for 0 & 1 fsrcs + fsrc_temp = fsrc & ((ADI_APOLLO_FSRC_A0 << i) | (ADI_APOLLO_FSRC_A0 << (i+1))); + if (fsrc_temp > 0) { + regmap_base_addr = calc_fsrc_base(terminal, i); + + err = adi_apollo_hal_bf_get(device, BF_FSRC_RATE_INT_INFO(regmap_base_addr), (uint8_t*) &(fsrc_inspect->dp_cfg.fsrc_rate_int), 8); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_FSRC_RATE_FRAC_A_INFO(regmap_base_addr), (uint8_t*) &(fsrc_inspect->dp_cfg.fsrc_rate_frac_a), 8); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_FSRC_RATE_FRAC_B_INFO(regmap_base_addr), (uint8_t*) &(fsrc_inspect->dp_cfg.fsrc_rate_frac_b), 8); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_SAMPLE_FRAC_DELAY_INFO(regmap_base_addr), (uint8_t*) &(fsrc_inspect->dp_cfg.fsrc_delay), 2); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_GAIN_REDUCTION_INFO(regmap_base_addr), (uint8_t*) &(fsrc_inspect->dp_cfg.gain_reduction), 2); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_PTR_SYNCRSTVAL_REGMAP_OVERWRITE_INFO(regmap_base_addr), (uint8_t*) &(fsrc_inspect->dp_cfg.ptr_overwrite), 1); + ADI_APOLLO_ERROR_RETURN(err); + if (fsrc_inspect->dp_cfg.ptr_overwrite == 1){ + err = adi_apollo_hal_bf_get(device, BF_PTR_SYNCRSTVAL_INFO(regmap_base_addr), (uint8_t*) &(fsrc_inspect->dp_cfg.ptr_syncrstval), 1); + ADI_APOLLO_ERROR_RETURN(err); + } + err = adi_apollo_hal_bf_get(device, BF_FSRC_DATA_MULT_DITHER_EN_INFO(regmap_base_addr), (uint8_t*) &(fsrc_inspect->dp_cfg.data_mult_dither_en), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_FSRC_DITHER_EN_INFO(regmap_base_addr), (uint8_t*) &(fsrc_inspect->dp_cfg.dither_en), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_FSRC_4T4R_SPLIT_INFO(regmap_base_addr), (uint8_t*) &(fsrc_inspect->dp_cfg.split_4t4r), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_FSRC_BYPASS_INFO(regmap_base_addr), (uint8_t*) &(fsrc_inspect->fsrc_bypass), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_FSRC_1X_MODE_INFO(regmap_base_addr), (uint8_t*) &(fsrc_inspect->dp_cfg.mode_1x), 1); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + /* first clear the enables since only one will be updated in the function call */ + fsrc_inspect->dp_cfg.enable0 = 0; + fsrc_inspect->dp_cfg.enable1 = 0; + + /* Now retrieve the enable for the specific FSC block */ + for(i = 0; i < ADI_APOLLO_FSRC_NUM; i ++) { + fsrc_temp = fsrc & (ADI_APOLLO_FSRC_A0 << i); + if (fsrc_temp > 0) { + regmap_base_addr = calc_fsrc_base(terminal, i); + + if (i % 2 == 0) { + err = adi_apollo_hal_bf_get(device, BF_FSRC_EN0_INFO(regmap_base_addr), (uint8_t*) &(fsrc_inspect->dp_cfg.enable0), 1); + ADI_APOLLO_ERROR_RETURN(err); + } else { + err = adi_apollo_hal_bf_get(device, BF_FSRC_EN1_INFO(regmap_base_addr), (uint8_t*) &(fsrc_inspect->dp_cfg.enable1), 1); + ADI_APOLLO_ERROR_RETURN(err); + } + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_fsrc_rx_rm_fifo_pgm(adi_apollo_device_t *device, const uint16_t links, adi_apollo_rx_rm_fifo_pgm_t *config) +{ + int32_t err, i; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_DEV_FEAT_LOCKOUT_RETURN(ADI_APOLLO_RX, ADI_APOLLO_EC_FSRC_LOCK); + + for (i = 0; i < ADI_APOLLO_NUM_JTX_LINKS; i++) { + if ((1 << i) & links) { + regmap_base_addr = calc_jtx_dformat_base(i); + + if ((i % ADI_APOLLO_NUM_JTX_LINKS_PER_SIDE) == 0) { /* Link 0 */ + err = adi_apollo_hal_bf_set(device, BF_LINK_DDC_DEC_0_INFO(regmap_base_addr), config->dcm_ratio); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_LINK_TOTAL_DEC_0_INFO(regmap_base_addr), config->total_dcm); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_INVALID_EN_0_INFO(regmap_base_addr), config->invalid_en); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_DFORMAT_DDC_DITHER_EN_0_INFO(regmap_base_addr), config->dfor_ddc_dither_en); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_SAMPLE_REPEAT_EN_0_INFO(regmap_base_addr), config->sample_repeat_en); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_STARTUP_FRCE_INVALID_EN_INFO(regmap_base_addr, 0), config->startup_force_inv_en); + ADI_APOLLO_ERROR_RETURN(err); + + } else { /* Link 1 */ + err = adi_apollo_hal_bf_set(device, BF_LINK_DDC_DEC_1_INFO(regmap_base_addr), config->dcm_ratio); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_LINK_TOTAL_DEC_1_INFO(regmap_base_addr), config->total_dcm); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_INVALID_EN_1_INFO(regmap_base_addr), config->invalid_en); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_DFORMAT_DDC_DITHER_EN_1_INFO(regmap_base_addr), config->dfor_ddc_dither_en); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_SAMPLE_REPEAT_EN_1_INFO(regmap_base_addr), config->sample_repeat_en); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_STARTUP_FRCE_INVALID_EN_INFO(regmap_base_addr, 1), config->startup_force_inv_en); + ADI_APOLLO_ERROR_RETURN(err); + + } + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_fsrc_rate_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t fsrcs, + uint64_t rate_int, uint64_t rate_frac_a, uint64_t rate_frac_b, uint16_t gain_red) +{ + int32_t err; + uint8_t i; + adi_apollo_blk_sel_t fsrc; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_DEV_FEAT_LOCKOUT_RETURN(terminal, ADI_APOLLO_EC_FSRC_LOCK); + ADI_APOLLO_FSRC_BLK_SEL_MASK(fsrcs); + + for (i = 0; i < ADI_APOLLO_FSRC_NUM; i += 2) { + fsrc = fsrcs & ((ADI_APOLLO_FSRC_A0 << i) | (ADI_APOLLO_FSRC_A0 << (i+1))); + if (fsrc > 0) { + regmap_base_addr = calc_fsrc_base(terminal, i); + + err = adi_apollo_hal_bf_set(device, BF_FSRC_RATE_INT_INFO(regmap_base_addr), rate_int); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_FSRC_RATE_FRAC_A_INFO(regmap_base_addr), rate_frac_a); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_FSRC_RATE_FRAC_B_INFO(regmap_base_addr), rate_frac_b); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_GAIN_REDUCTION_INFO(regmap_base_addr), gain_red); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_fsrc_ratio_set(adi_apollo_device_t* device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t fsrcs, uint32_t n, uint32_t m) +{ + int32_t err; + uint64_t rate_int, rate_frac_a, rate_frac_b, gain_red; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_DEV_FEAT_LOCKOUT_RETURN(terminal, ADI_APOLLO_EC_FSRC_LOCK); + ADI_APOLLO_INVALID_PARAM_RETURN( (!(m > 0)) || (n == m) || (n / m >= 2) ); + ADI_APOLLO_FSRC_BLK_SEL_MASK(fsrcs); + + err = adi_api_utils_ratio_decomposition(m, n, 48, &rate_int, &rate_frac_a, &rate_frac_b); + ADI_APOLLO_ERROR_RETURN(err); + + gain_red = adi_api_utils_div_floor_u64(4096ull * (uint64_t)m, (uint64_t)n); + + return adi_apollo_fsrc_rate_set(device, terminal, fsrcs, rate_int, rate_frac_a, rate_frac_b, gain_red); +} + + +int32_t adi_apollo_fsrc_mode_1x_enable_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t fsrcs, uint8_t enable) +{ + int32_t err; + uint8_t i; + adi_apollo_blk_sel_t fsrc; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_DEV_FEAT_LOCKOUT_RETURN(terminal, ADI_APOLLO_EC_FSRC_LOCK); + ADI_APOLLO_FSRC_BLK_SEL_MASK(fsrcs); + + for (i = 0; i < ADI_APOLLO_FSRC_NUM; i += 2) { + fsrc = fsrcs & ((ADI_APOLLO_FSRC_A0 << i) | (ADI_APOLLO_FSRC_A0 << (i+1))); + if (fsrc > 0) { + regmap_base_addr = calc_fsrc_base(terminal, i); + err = adi_apollo_hal_bf_set(device, BF_FSRC_1X_MODE_INFO(regmap_base_addr), enable); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +uint32_t calc_fsrc_base(adi_apollo_terminal_e terminal, int32_t fsrc_index) +{ + static uint32_t rx_fsrc_regmap[ADI_APOLLO_FSRC_NUM] = { + RX_FSRC_RX_SLICE_0_RX_DIGITAL0, RX_FSRC_RX_SLICE_0_RX_DIGITAL0, + RX_FSRC_RX_SLICE_0_RX_DIGITAL1, RX_FSRC_RX_SLICE_0_RX_DIGITAL1 + }; + static uint32_t tx_fsrc_regmap[ADI_APOLLO_FSRC_NUM] = { + TX_FSRC_TX_SLICE_0_TX_DIGITAL0, TX_FSRC_TX_SLICE_0_TX_DIGITAL0, + TX_FSRC_TX_SLICE_0_TX_DIGITAL1, TX_FSRC_TX_SLICE_0_TX_DIGITAL1 + }; + if (terminal == ADI_APOLLO_RX) + return rx_fsrc_regmap[fsrc_index]; + else + return tx_fsrc_regmap[fsrc_index]; +} +/*! @} */ \ No newline at end of file diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_fsrc_local.h b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_fsrc_local.h new file mode 100644 index 00000000000000..546cf7920a2d81 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_fsrc_local.h @@ -0,0 +1,36 @@ +/*! + * \brief FSRC local defines and prototypes + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_FSRC + * @{ + */ +#ifndef __ADI_APOLLO_FSRC_LOCAL_H__ +#define __ADI_APOLLO_FSRC_LOCAL_H__ + +/*============= I N C L U D E S ============*/ + +/*============= D E F I N E S ==============*/ + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +uint32_t calc_fsrc_base(adi_apollo_terminal_e terminal, int32_t fsrc_index); + +#ifndef CLIENT_IGNORE +#endif /* CLIENT_IGNORE*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_FSRC_LOCAL_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_gpio.c b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_gpio.c new file mode 100644 index 00000000000000..1abdabb9502a85 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_gpio.c @@ -0,0 +1,413 @@ +/*! + * \brief APIs for GPIO + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_GPIO + * @{ + */ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_config.h" +#include "adi_apollo_bf_core.h" +#include "adi_apollo_hal.h" +#include "adi_apollo_gpio.h" + +static uint32_t calc_sync_pad_ctl_addr(int32_t index); +static uint32_t calc_gpio_stage_sel_byte_address(uint8_t gpio_index); +static uint32_t calc_bf_info_gpio_stage_sel(uint8_t gpio_index); + +/*==================== P U B L I C A P I C O D E ====================*/ +int32_t adi_apollo_gpio_cmos_debug_mode_set(adi_apollo_device_t *device, uint8_t gpio_index, + adi_apollo_gpio_cmos_debug_stage_e debug_stage) +{ + int32_t err; + uint32_t gpio_stage_sel_addr = 0; + uint8_t lvds_pad; + uint32_t bf_info; + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(gpio_index > ADI_APOLLO_NUM_GPIO - 1); + + if (gpio_index > ADI_APOLLO_NUM_CMOS_GPIO - 1) { + // Config SYNC PAD to CMOS mode + lvds_pad = (gpio_index % 2 == 1) ? gpio_index : gpio_index - 1; + err = adi_apollo_gpio_sync_pad_cmos_lvds_mode_set(device, lvds_pad, ADI_APOLLO_CMOS_MODE); + ADI_APOLLO_ERROR_RETURN(err); + } + + gpio_stage_sel_addr = calc_gpio_stage_sel_byte_address(gpio_index); + bf_info = calc_bf_info_gpio_stage_sel(gpio_index); + + err = adi_apollo_hal_bf_set(device, gpio_stage_sel_addr, bf_info, debug_stage); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_gpio_cmos_func_mode_set(adi_apollo_device_t *device, uint8_t gpio_index, + adi_apollo_gpio_func_e func_num) +{ + int32_t err; + uint32_t gpio_stage_sel_addr = 0; + uint8_t lvds_pad; + uint32_t bf_info; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(gpio_index > ADI_APOLLO_NUM_GPIO - 1); + + if (gpio_index > ADI_APOLLO_NUM_CMOS_GPIO - 1) { + // Config SYNC PAD to CMOS mode + lvds_pad = (gpio_index % 2 == 1) ? gpio_index : gpio_index - 1; + err = adi_apollo_gpio_sync_pad_cmos_lvds_mode_set(device, lvds_pad, ADI_APOLLO_CMOS_MODE); + ADI_APOLLO_ERROR_RETURN(err); + } + + gpio_stage_sel_addr = calc_gpio_stage_sel_byte_address(gpio_index); + bf_info = calc_bf_info_gpio_stage_sel(gpio_index); + + err = adi_apollo_hal_bf_set(device, gpio_stage_sel_addr, bf_info, 0); // GPIO_STAGE_SEL = 2’b00 : Functional Stage + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_GPIO_SOURCE_CONTROL_INFO(gpio_index), func_num); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_gpio_cmos_gpio_mode_set(adi_apollo_device_t *device, uint8_t gpio_index, adi_apollo_gpio_dir_e gpio_dir) +{ + int32_t err; + uint32_t gpio_mode_ctrl_byte_addr = 0; + uint32_t gpio_dir_addr = 0; + uint8_t bf_start, lvds_pad, gpio_ctrl_byte; + uint32_t bf_info; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(gpio_index > ADI_APOLLO_NUM_GPIO - 1); + + // calc mode_ctrl_byte and mode_dir byte addr + gpio_ctrl_byte = gpio_index / 8; + bf_start = gpio_index % 8; + gpio_mode_ctrl_byte_addr = REG_GPIO_MODE_CONTROL_BYTE0_ADDR + gpio_ctrl_byte; + gpio_dir_addr = REG_GPIO_MODE_DIR_BYTE0_ADDR + gpio_ctrl_byte; + bf_info = bf_start | (1<< 8); //1 bit wide BF + + if (gpio_index > ADI_APOLLO_NUM_CMOS_GPIO - 1) { + // Config SYNC PAD to CMOS mode + lvds_pad = (gpio_index % 2 == 1) ? gpio_index : gpio_index - 1; + err = adi_apollo_gpio_sync_pad_cmos_lvds_mode_set(device, lvds_pad, ADI_APOLLO_CMOS_MODE); + ADI_APOLLO_ERROR_RETURN(err); + } + + err = adi_apollo_hal_bf_set(device, gpio_mode_ctrl_byte_addr, bf_info, 1); // GPIO MODE EN + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, gpio_dir_addr, bf_info, gpio_dir); // GPIO Dir + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_gpio_cmos_output_set(adi_apollo_device_t *device, uint8_t gpio_index, uint8_t gpio_data) +{ + int32_t err; + uint32_t gpio_from_master_byte_addr = 0; + uint8_t bf_start, gpio_from_master_byte; + uint32_t bf_info; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(gpio_index > ADI_APOLLO_NUM_GPIO - 1); + ADI_APOLLO_INVALID_PARAM_RETURN(gpio_data > 1); + + gpio_from_master_byte = gpio_index / 8; + bf_start = gpio_index % 8; + bf_info = bf_start | (1<< 8); //1 bit wide BF + + gpio_from_master_byte_addr = REG_GPIO_FROM_MASTER_BYTE0_ADDR + gpio_from_master_byte; + + err = adi_apollo_hal_bf_set(device, gpio_from_master_byte_addr, bf_info, gpio_data); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_gpio_cmos_input_get(adi_apollo_device_t *device, uint8_t gpio_index, uint8_t *gpio_data) +{ + int32_t err; + uint32_t spi_read_byte_addr = 0; + uint8_t bf_start, spi_read_byte; + uint32_t bf_info; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(gpio_data); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(gpio_index > ADI_APOLLO_NUM_GPIO - 1); + + // Enable Schmitt trigger. + err = adi_apollo_gpio_cmos_st_enable(device, gpio_index, 1); + ADI_APOLLO_ERROR_RETURN(err); + + spi_read_byte = gpio_index / 8; + bf_start = gpio_index % 8; + bf_info = bf_start | (1<< 8); //1 bit wide BF + + spi_read_byte_addr = REG_GPIO_SPI_READ_BYTE0_ADDR + spi_read_byte; + + err = adi_apollo_hal_bf_get(device, spi_read_byte_addr, bf_info, gpio_data, 1); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_gpio_quick_config_mode_set(adi_apollo_device_t *device, adi_apollo_gpio_quick_cfg_profile_e profile) +{ + int32_t err; + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + /* set stage_sel of GPIO's to functional mode */ + err = adi_apollo_hal_reg_set(device, REG_GPIO_STAGE_SEL_BYTE0_ADDR, 0x00); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_reg_set(device, REG_GPIO_STAGE_SEL_BYTE1_ADDR, 0x00); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_reg_set(device, REG_GPIO_STAGE_SEL_BYTE2_ADDR, 0x00); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_reg_set(device, REG_GPIO_STAGE_SEL_BYTE3_ADDR, 0x00); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_reg_set(device, REG_GPIO_STAGE_SEL_BYTE4_ADDR, 0x00); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_reg_set(device, REG_GPIO_STAGE_SEL_BYTE5_ADDR, 0x00); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_reg_set(device, REG_GPIO_STAGE_SEL_BYTE6_ADDR, 0x00); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_reg_set(device, REG_GPIO_STAGE_SEL_BYTE7_ADDR, 0x00); + ADI_APOLLO_ERROR_RETURN(err); + + /*Quick Config Profile*/ + err = adi_apollo_hal_bf_set(device, BF_GPIO_QUICK_CONFIG_INFO, profile); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_gpio_sync_pad_lvds_debug_mode_set(adi_apollo_device_t *device, adi_apollo_gpio_sync_pad_e sync_pad, + adi_apollo_gpio_debug_func_e debug_func_num) +{ + int32_t err; + uint32_t sync_pad_ctl_addr = 0; + uint32_t gpio_stage_sel_info = BF_INFO_EXTRACT(BF_SYNCOUTB0_A_GPIO_STAGE_SEL_INFO); + uint32_t debug_source_sel_info = BF_INFO_EXTRACT(BF_SYNCOUTB0_A_GPIO_DEBUG_SOURCE_SEL_INFO); + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + // Debug mode-Only valid for SYNC_OUT Pads + ADI_APOLLO_INVALID_PARAM_RETURN(sync_pad < ADI_APOLLO_SYNCOUTB0_B); + + // Configure pad in LVDS mode + err = adi_apollo_gpio_sync_pad_cmos_lvds_mode_set(device, sync_pad, ADI_APOLLO_LVDS_MODE); + ADI_APOLLO_ERROR_RETURN(err); + + sync_pad_ctl_addr = calc_sync_pad_ctl_addr(sync_pad); + + // gpio_stage_sel + err = adi_apollo_hal_bf_set(device, sync_pad_ctl_addr + 1, gpio_stage_sel_info, 1); + ADI_APOLLO_ERROR_RETURN(err); + + // Assign debug function to SYNC PAD + err = adi_apollo_hal_bf_set(device, sync_pad_ctl_addr + 1, debug_source_sel_info, debug_func_num); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_gpio_sync_pad_lvds_func_mode_set(adi_apollo_device_t *device, adi_apollo_gpio_sync_pad_e sync_pad, + adi_apollo_gpio_func_e func_num) +{ + int32_t err; + uint32_t sync_pad_ctl_addr = 0; + uint32_t gpio_stage_sel_info = BF_INFO_EXTRACT(BF_SYNCOUTB0_A_GPIO_STAGE_SEL_INFO); + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + // Configure pad in LVDS mode + err = adi_apollo_gpio_sync_pad_cmos_lvds_mode_set(device, sync_pad, ADI_APOLLO_LVDS_MODE); + ADI_APOLLO_ERROR_RETURN(err); + + sync_pad_ctl_addr = calc_sync_pad_ctl_addr(sync_pad); + + if (sync_pad >= ADI_APOLLO_SYNCOUTB0_B) { + // gpio_stage_sel to func mode + err = adi_apollo_hal_bf_set(device, sync_pad_ctl_addr + 1, gpio_stage_sel_info, 0); + ADI_APOLLO_ERROR_RETURN(err); + } + // Assign function number to SYNC PAD + err = adi_apollo_hal_bf_set(device, BF_GPIO_SOURCE_CONTROL_INFO(sync_pad), func_num); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_gpio_sync_pad_cmos_lvds_mode_set(adi_apollo_device_t *device, uint8_t pad_index, + adi_apollo_gpio_sync_pad_mode_e mode) +{ + int32_t err; + uint32_t sync_pad_ctrl_addr = 0; + uint32_t lvds_sel_info = BF_INFO_EXTRACT(BF_SYNCINB0_A_LVDS_SEL_INFO); + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(pad_index < ADI_APOLLO_SYNCINB0_B); + + sync_pad_ctrl_addr = calc_sync_pad_ctl_addr(pad_index); + err = adi_apollo_hal_bf_set(device, sync_pad_ctrl_addr, lvds_sel_info, mode); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_gpio_sync_pad_lvds_input_get(adi_apollo_device_t *device, adi_apollo_gpio_sync_pad_e sync_pad, + uint8_t *pad_data) +{ + int32_t err; + uint32_t sync_pad_ctrl_addr = 0; + uint32_t spi_read_info = BF_INFO_EXTRACT(BF_SYNCINB0_A_SPI_READ_INFO); + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(pad_data); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(sync_pad > ADI_APOLLO_SYNCINB1_A); //Valid only for Sync in Pads + + sync_pad_ctrl_addr = calc_sync_pad_ctl_addr(sync_pad); + err = adi_apollo_hal_bf_get(device, sync_pad_ctrl_addr, spi_read_info, pad_data, 1); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_gpio_cmos_st_enable(adi_apollo_device_t *device, uint8_t gpio_index, uint8_t st_enable) +{ + int32_t err = API_CMS_ERROR_ERROR; + uint32_t cmos_pad_st_addr = ( REG_CMOS_PAD_ST_BYTE0_ADDR + (gpio_index / 8) ); + uint32_t st_byte_info = ( (1 << 8) | (gpio_index % 8) ); + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(gpio_index > ADI_APOLLO_NUM_GPIO - 1); + ADI_APOLLO_INVALID_PARAM_RETURN(st_enable > 1); + + err = adi_apollo_hal_bf_set(device, cmos_pad_st_addr, st_byte_info, st_enable); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_gpio_syncin_pad_termination_enable(adi_apollo_device_t *device, adi_apollo_gpio_sync_pad_e syncin_pad, uint8_t termination_enable) +{ + int32_t err = API_CMS_ERROR_ERROR; + uint32_t sync_pad_ctrl_addr = 0; + uint32_t term_en_info = BF_INFO_EXTRACT(BF_SYNCINB0_A_TERM_EN_INFO); + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(termination_enable > 1); + + if ( (syncin_pad < ADI_APOLLO_SYNCINB0_B) || (syncin_pad > ADI_APOLLO_SYNCINB1_A) ) + return API_CMS_ERROR_INVALID_PARAM; + + sync_pad_ctrl_addr = calc_sync_pad_ctl_addr(syncin_pad); + + err = adi_apollo_hal_bf_set(device, sync_pad_ctrl_addr, term_en_info, termination_enable); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_gpio_sync_pad_lvds_enable(adi_apollo_device_t *device, adi_apollo_gpio_sync_pad_e sync_pad, uint8_t enable) +{ + int32_t err = API_CMS_ERROR_ERROR; + uint32_t sync_pad_ctrl_addr = 0; + uint32_t en_info = BF_INFO_EXTRACT(BF_SYNCINB0_A_PAD_EN_INFO); + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(sync_pad > ADI_APOLLO_SYNCOUTB1_A); + ADI_APOLLO_INVALID_PARAM_RETURN(enable > 1); + + sync_pad_ctrl_addr = calc_sync_pad_ctl_addr(sync_pad); + + err = adi_apollo_hal_bf_set(device, sync_pad_ctrl_addr, en_info, enable); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_gpio_jesd_204b_configure(adi_apollo_device_t *device) +{ + int32_t err = API_CMS_ERROR_ERROR; + uint32_t i; + uint8_t pads[8] = {ADI_APOLLO_SYNCINB0_B,ADI_APOLLO_SYNCINB0_A,ADI_APOLLO_SYNCOUTB0_B,ADI_APOLLO_SYNCOUTB0_A,ADI_APOLLO_SYNCINB1_B,ADI_APOLLO_SYNCINB1_A,ADI_APOLLO_SYNCOUTB1_B,ADI_APOLLO_SYNCOUTB1_A}; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + for (i = 0; i < 8; i++) { + err = adi_apollo_gpio_sync_pad_cmos_lvds_mode_set(device, pads[i], ADI_APOLLO_LVDS_MODE); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_gpio_sync_pad_lvds_enable(device, pads[i], 1); + ADI_APOLLO_ERROR_RETURN(err); + } + + return API_CMS_ERROR_OK; +} + +static uint32_t calc_sync_pad_ctl_addr(int32_t index) +{ + static uint32_t lvds_pad_ctrl_addr[] = { + REG_SYNCINB0_B_CNTRL_ADDR, REG_SYNCINB1_B_CNTRL_ADDR, REG_SYNCINB0_A_CNTRL_ADDR, + REG_SYNCINB1_A_CNTRL_ADDR, REG_SYNCOUTB0_B_CNTRL_BYTE0_ADDR, REG_SYNCOUTB1_B_CNTRL_BYTE0_ADDR, + REG_SYNCOUTB0_A_CNTRL_BYTE0_ADDR, REG_SYNCOUTB1_A_CNTRL_BYTE0_ADDR + }; + + return (lvds_pad_ctrl_addr[(index % ADI_APOLLO_SYNCINB0_B) / 2]); +} + +static uint32_t calc_gpio_stage_sel_byte_address(uint8_t gpio_index) +{ + uint8_t bf_start_bit, stage_sel_byte; + // 102 bit wide bitfield split into 13 reg. + bf_start_bit = 2 *gpio_index; // 2*i : 2*i +1 + stage_sel_byte = bf_start_bit / 8; + + return REG_GPIO_STAGE_SEL_BYTE0_ADDR + stage_sel_byte; +} + +static uint32_t calc_bf_info_gpio_stage_sel(uint8_t gpio_index) +{ + uint8_t bf_start_bit, bf_start_byte; + uint32_t bf_info; + // 102 bit wide bitfield split into 13 reg. + bf_start_bit = 2 *gpio_index; // 2*i : 2*i +1 + bf_start_byte = bf_start_bit % 8; + bf_info = bf_start_byte | (2 << 8); //2 bit wide BF + + return bf_info; +} +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_gpio_hop.c b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_gpio_hop.c new file mode 100644 index 00000000000000..d120444d82f1bb --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_gpio_hop.c @@ -0,0 +1,598 @@ +/*! + * \brief APIs for GPIO select + * + * \copyright copyright(c) 2024 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_GPIO_HOP + * @{ + */ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_gpio_hop.h" +#include "adi_apollo_config.h" +#include "adi_apollo_hal.h" +#include "adi_apollo_bf_apollo_profile_config.h" +#include "adi_apollo_bf_custom.h" + +static uint32_t calc_profile_func_mode(int32_t index); +static uint32_t calc_block_func_mode(int32_t index); +static uint32_t calc_slice_func_mode(int32_t index); +static uint32_t calc_term_func_mode(int32_t index); + +const adi_apollo_gpio_hop_profile_t * calc_profile_qc(int32_t index); +const adi_apollo_gpio_hop_block_t * calc_block_qc(int32_t index); +const adi_apollo_gpio_hop_side_t * calc_side_qc(int32_t index); +const adi_apollo_gpio_hop_slice_t * calc_slice_qc(int32_t index); +const adi_apollo_gpio_hop_terminal_t * calc_term_qc(int32_t index); + +// Quick config mapping - several quick configs have overlaps indicated by the variable names +const adi_apollo_gpio_hop_profile_t ADI_APOLLO_GPIO_HOP_PROFILE_1238 = {{26, 27, 28, 29, 30}}; +const adi_apollo_gpio_hop_profile_t ADI_APOLLO_GPIO_HOP_PROFILE_45 = {{24, 25, 26, 27, 28}}; +const adi_apollo_gpio_hop_profile_t ADI_APOLLO_GPIO_HOP_PROFILE_6 = {{16, 17, 18, 19, 20}}; + +const adi_apollo_gpio_hop_block_t ADI_APOLLO_GPIO_HOP_BLOCK_123 = {{23, 24, 25, 31}}; +const adi_apollo_gpio_hop_block_t ADI_APOLLO_GPIO_HOP_BLOCK_45 = {{21, 22, 23, 31}}; +const adi_apollo_gpio_hop_block_t ADI_APOLLO_GPIO_HOP_BLOCK_8 = {{23, 24, 25, -1}}; + +const adi_apollo_gpio_hop_side_t ADI_APOLLO_GPIO_HOP_SIDE_128 = {{22}}; +const adi_apollo_gpio_hop_side_t ADI_APOLLO_GPIO_HOP_SIDE_45 = {{20}}; + +const adi_apollo_gpio_hop_slice_t ADI_APOLLO_GPIO_HOP_SLICE_128 = {{19, 20, 21}}; +const adi_apollo_gpio_hop_slice_t ADI_APOLLO_GPIO_HOP_SLICE_45 = {{17, 18, 19}}; + +const adi_apollo_gpio_hop_terminal_t ADI_APOLLO_GPIO_HOP_TERMINAL_128 = {{17, 18}}; +const adi_apollo_gpio_hop_terminal_t ADI_APOLLO_GPIO_HOP_TERMINAL_3 = {{21, 22}}; +const adi_apollo_gpio_hop_terminal_t ADI_APOLLO_GPIO_HOP_TERMINAL_45 = {{15, 16}}; +const adi_apollo_gpio_hop_terminal_t ADI_APOLLO_GPIO_HOP_TERMINAL_6 = {{16, 17}}; + +/*==================== P U B L I C A P I C O D E ====================*/ +int32_t adi_apollo_gpio_hop_profile_configure(adi_apollo_device_t *device, const adi_apollo_gpio_hop_profile_t *config) +{ + int32_t err; + uint8_t i; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(config); + + for (i = 0; i < ADI_APOLLO_GPIO_HOP_PROFILE_BIT_NUMBER; i++) { + if (config->index[i] != ADI_APOLLO_GPIO_HOP_IDX_NONE) { + err = adi_apollo_gpio_cmos_func_mode_set(device, config->index[i], calc_profile_func_mode(i)); + ADI_APOLLO_ERROR_RETURN(err); + } + } + return err; +} + +int32_t adi_apollo_gpio_hop_profile_calc(adi_apollo_device_t *device, const adi_apollo_gpio_hop_profile_t *config, uint8_t profile, uint64_t *mask, uint64_t *value) +{ + uint8_t i; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(config); + ADI_APOLLO_NULL_POINTER_RETURN(value); + ADI_APOLLO_NULL_POINTER_RETURN(mask); + + *mask = (uint64_t)0; + *value = (uint64_t)0; + + for (i = 0; i < ADI_APOLLO_GPIO_HOP_PROFILE_BIT_NUMBER; i++) { + if (config->index[i] != ADI_APOLLO_GPIO_HOP_IDX_NONE) { + *mask |= ((uint64_t)1 << config->index[i]); + if ((profile & (1 << i)) > 0) { + *value |= ((uint64_t)1 << config->index[i]); + } + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_gpio_hop_profile_qc_calc(adi_apollo_device_t *device, adi_apollo_gpio_quick_cfg_profile_e config, uint8_t number, uint64_t *mask, uint64_t *value) +{ + const adi_apollo_gpio_hop_profile_t *idx; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + idx = calc_profile_qc(config); + ADI_APOLLO_INVALID_PARAM_RETURN(idx == NULL); + + return adi_apollo_gpio_hop_profile_calc(device, idx, number, mask, value); +} + + +int32_t adi_apollo_gpio_hop_block_configure(adi_apollo_device_t *device, const adi_apollo_gpio_hop_block_t *config) +{ + int32_t err; + uint8_t i; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(config); + + for (i = 0; i < ADI_APOLLO_GPIO_HOP_BLOCK_BIT_NUMBER; i++) { + if (config->index[i] != ADI_APOLLO_GPIO_HOP_IDX_NONE) { + err = adi_apollo_gpio_cmos_func_mode_set(device, config->index[i], calc_block_func_mode(i)); + ADI_APOLLO_ERROR_RETURN(err); + } + } + return err; +} + +int32_t adi_apollo_gpio_hop_block_calc(adi_apollo_device_t *device, const adi_apollo_gpio_hop_block_t *config, adi_apollo_gpio_hop_block_e block, uint64_t *mask, uint64_t *value) +{ + uint8_t i; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(config); + ADI_APOLLO_NULL_POINTER_RETURN(value); + ADI_APOLLO_NULL_POINTER_RETURN(mask); + + *mask = (uint64_t)0; + *value = (uint64_t)0; + + for (i = 0; i < ADI_APOLLO_GPIO_HOP_BLOCK_BIT_NUMBER; i++) { + if (config->index[i] != ADI_APOLLO_GPIO_HOP_IDX_NONE) { + *mask |= ((uint64_t)1 << config->index[i]); + if ((block & (1 << i)) > 0) { + *value |= ((uint64_t)1 << config->index[i]); + } + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_gpio_hop_block_qc_calc(adi_apollo_device_t *device, adi_apollo_gpio_quick_cfg_profile_e config, adi_apollo_gpio_hop_block_e block, uint64_t *mask, uint64_t *value) +{ + const adi_apollo_gpio_hop_block_t *idx; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + idx = calc_block_qc(config); + ADI_APOLLO_INVALID_PARAM_RETURN(idx == NULL); + + return adi_apollo_gpio_hop_block_calc(device, idx, block, mask, value); +} + +int32_t adi_apollo_gpio_hop_side_configure(adi_apollo_device_t *device, const adi_apollo_gpio_hop_side_t *config) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(config); + + err = adi_apollo_gpio_cmos_func_mode_set(device, config->index[0], ADI_APOLLO_FUNC_PROFILE_TXRX_BA); + + return err; +} + +int32_t adi_apollo_gpio_hop_side_calc(adi_apollo_device_t *device, const adi_apollo_gpio_hop_side_t *config, adi_apollo_side_select_e side, uint64_t *mask, uint64_t *value) +{ + uint8_t i; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(config); + ADI_APOLLO_NULL_POINTER_RETURN(value); + ADI_APOLLO_NULL_POINTER_RETURN(mask); + ADI_APOLLO_INVALID_PARAM_RETURN(side != ADI_APOLLO_SIDE_A && side != ADI_APOLLO_SIDE_B) + + *mask = (uint64_t)0; + *value = (uint64_t)0; + + for (i = 0; i < ADI_APOLLO_GPIO_HOP_SIDE_BIT_NUMBER; i++) { + if (config->index[i] != ADI_APOLLO_GPIO_HOP_IDX_NONE) { + *mask |= ((uint64_t)1 << config->index[i]); + if (side == ADI_APOLLO_SIDE_B) { + *value |= ((uint64_t)1 << config->index[i]); + } + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_gpio_hop_side_qc_calc(adi_apollo_device_t *device, adi_apollo_gpio_quick_cfg_profile_e config, adi_apollo_side_select_e side, uint64_t *mask, uint64_t *value) +{ + const adi_apollo_gpio_hop_side_t *idx; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + idx = calc_side_qc(config); + ADI_APOLLO_INVALID_PARAM_RETURN(idx == NULL); + + return adi_apollo_gpio_hop_side_calc(device, idx, side, mask, value); +} + + +int32_t adi_apollo_gpio_hop_slice_configure(adi_apollo_device_t *device, const adi_apollo_gpio_hop_slice_t *config) +{ + int32_t err; + uint8_t i; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(config); + + for (i = 0; i < ADI_APOLLO_GPIO_HOP_SLICE_BIT_NUMBER; i++) { + if (config->index[i] != ADI_APOLLO_GPIO_HOP_IDX_NONE) { + err = adi_apollo_gpio_cmos_func_mode_set(device, config->index[i], calc_slice_func_mode(i)); + ADI_APOLLO_ERROR_RETURN(err); + } + } + return err; +} + +int32_t adi_apollo_gpio_hop_slice_calc(adi_apollo_device_t *device, const adi_apollo_gpio_hop_slice_t *config, uint8_t slice, uint64_t *mask, uint64_t *value) +{ + uint8_t i; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(config); + ADI_APOLLO_NULL_POINTER_RETURN(value); + ADI_APOLLO_NULL_POINTER_RETURN(mask); + + *mask = (uint64_t)0; + *value = (uint64_t)0; + + for (i = 0; i < ADI_APOLLO_GPIO_HOP_SLICE_BIT_NUMBER; i++) { + if (config->index[i] != ADI_APOLLO_GPIO_HOP_IDX_NONE) { + *mask |= ((uint64_t)1 << config->index[i]); + if ((slice & (1 << i)) > 0) { + *value |= ((uint64_t)1 << config->index[i]); + } + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_gpio_hop_slice_qc_calc(adi_apollo_device_t *device, adi_apollo_gpio_quick_cfg_profile_e config, uint8_t slice, uint64_t *mask, uint64_t *value) +{ + const adi_apollo_gpio_hop_slice_t *idx; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + idx = calc_slice_qc(config); + ADI_APOLLO_INVALID_PARAM_RETURN(idx == NULL); + + return adi_apollo_gpio_hop_slice_calc(device, idx, slice, mask, value); +} + +int32_t adi_apollo_gpio_hop_terminal_configure(adi_apollo_device_t *device, const adi_apollo_gpio_hop_terminal_t *config) +{ + int32_t err; + uint8_t i; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(config); + + for (i = 0; i < ADI_APOLLO_GPIO_HOP_TERMINAL_BIT_NUMBER; i++) { + if (config->index[i] != ADI_APOLLO_GPIO_HOP_IDX_NONE) { + err = adi_apollo_gpio_cmos_func_mode_set(device, config->index[i], calc_term_func_mode(i)); + ADI_APOLLO_ERROR_RETURN(err); + } + } + return err; +} + +int32_t adi_apollo_gpio_hop_terminal_calc(adi_apollo_device_t *device, const adi_apollo_gpio_hop_terminal_t *config, adi_apollo_gpio_hop_terminal_e terminal, uint64_t *mask, uint64_t *value) +{ + uint8_t i; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(config); + ADI_APOLLO_NULL_POINTER_RETURN(value); + ADI_APOLLO_NULL_POINTER_RETURN(mask); + + *mask = (uint64_t)0; + *value = (uint64_t)0; + + for (i = 0; i < ADI_APOLLO_GPIO_HOP_TERMINAL_BIT_NUMBER; i++) { + if (config->index[i] != ADI_APOLLO_GPIO_HOP_IDX_NONE) { + *mask |= ((uint64_t)1 << config->index[i]); + if ((terminal & (1 << i)) > 0) { + *value |= ((uint64_t)1 << config->index[i]); + } + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_gpio_hop_terminal_qc_calc(adi_apollo_device_t *device, adi_apollo_gpio_quick_cfg_profile_e config, adi_apollo_gpio_hop_terminal_e terminal, uint64_t *mask, uint64_t *value) +{ + const adi_apollo_gpio_hop_terminal_t *idx; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + idx = calc_term_qc(config); + ADI_APOLLO_INVALID_PARAM_RETURN(idx == NULL); + + return adi_apollo_gpio_hop_terminal_calc(device, idx, terminal, mask, value); +} + +int32_t adi_apollo_gpio_hop_block_select_set(adi_apollo_device_t *device, adi_apollo_gpio_hop_select_e select) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_hal_bf_set(device, BF_FCN_SEL_SPI_GPIO_INFO, select); + ADI_APOLLO_ERROR_RETURN(err); + + return err; +} + +int32_t adi_apollo_gpio_hop_block_set(adi_apollo_device_t *device, adi_apollo_gpio_hop_block_e block) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_hal_bf_set(device, BF_PROFILE_FCN_SEL_INFO, block); + ADI_APOLLO_ERROR_RETURN(err); + + return err; +} + +int32_t adi_apollo_gpio_hop_slice_select_set(adi_apollo_device_t *device, adi_apollo_gpio_hop_block_e block, adi_apollo_gpio_hop_select_e select) +{ + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + switch (block) { + case ADI_APOLLO_GPIO_BLOCK_FNCO: + return adi_apollo_hal_bf_set(device, BF_FNCO_SLICE_SELECT_SPI_GPIO_INFO, select); + + case ADI_APOLLO_GPIO_BLOCK_CNCO: + return adi_apollo_hal_bf_set(device, BF_CNCO_SLICE_SELECT_SPI_GPIO_INFO, select); + + case ADI_APOLLO_GPIO_BLOCK_FNCO_CNCO: + return adi_apollo_hal_bf_set(device, BF_FNCO_CNCO_SLICE_SELECT_SPI_GPIO_INFO, select); + + case ADI_APOLLO_GPIO_BLOCK_PFILT: + return adi_apollo_hal_bf_set(device, BF_PFILT_SLICE_SELECT_SPI_GPIO_INFO, select); + + case ADI_APOLLO_GPIO_BLOCK_CNCO_PFILT: + return adi_apollo_hal_bf_set(device, BF_CNCO_PFILT_SLICE_SELECT_SPI_GPIO_INFO, select); + + case ADI_APOLLO_GPIO_BLOCK_FNCO_CFIR: + return adi_apollo_hal_bf_set(device, BF_FNCO_CFIR_SLICE_SELECT_SPI_GPIO_INFO, select); + + case ADI_APOLLO_GPIO_BLOCK_FDDC: + case ADI_APOLLO_GPIO_BLOCK_CDDC: + return adi_apollo_hal_bf_set(device, BF_DYN_CONFIG_SLICE_SELECT_SPI_GPIO_INFO, select); + + case ADI_APOLLO_GPIO_BLOCK_BMEM_DELAY: + return adi_apollo_hal_bf_set(device, BF_BMEM_HOP_SLICE_SELECT_SPI_GPIO_INFO, select); + + case ADI_APOLLO_GPIO_BLOCK_CFIR: + return adi_apollo_hal_bf_set(device, BF_CFIR_SLICE_SELECT_SPI_GPIO_INFO, select); + + case ADI_APOLLO_GPIO_BLOCK_FNCO_PFILT: + return adi_apollo_hal_bf_set(device, BF_FNCO_PFILT_SLICE_SELECT_SPI_GPIO_INFO, select); + + case ADI_APOLLO_GPIO_BLOCK_PFILT_CFIR: + return adi_apollo_hal_bf_set(device, BF_PFILT_CFIR_SLICE_SELECT_SPI_GPIO_INFO, select); + + case ADI_APOLLO_GPIO_BLOCK_LINX: + return API_CMS_ERROR_INVALID_PARAM; + } + + return API_CMS_ERROR_INVALID_PARAM; +} + +int32_t adi_apollo_gpio_hop_fnco_enable_set(adi_apollo_device_t *device, uint32_t terminal, uint32_t fncos, uint8_t enable) +{ + int32_t err; + int32_t regmap_base = REG_FNCO_SLICE_SELECT_REG_ADDR; + uint32_t fnco, index; + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + for (index = 0; index < ADI_APOLLO_FNCO_NUM; index++) { + fnco = fncos & (ADI_APOLLO_FNCO_A0 << index); + if (fnco > 0) { + err = adi_apollo_hal_bf_set(device, regmap_base, terminal == ADI_APOLLO_RX ? BF_PC_RX_FNCO_SLICE_SELECT_INFO(index) : BF_PC_TX_FNCO_SLICE_SELECT_INFO(index), enable); + ADI_APOLLO_ERROR_RETURN(err); + } + } + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_gpio_hop_cnco_enable_set(adi_apollo_device_t *device, uint32_t terminal, uint32_t cncos, uint8_t enable) +{ + int32_t err; + int32_t regmap_base = REG_CNCO_SLICE_SELECT_REG_ADDR; + uint32_t cnco, index; + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + for (index = 0; index < ADI_APOLLO_CNCO_NUM; index++) { + cnco = cncos & (ADI_APOLLO_CNCO_A0 << index); + if (cnco > 0) { + err = adi_apollo_hal_bf_set(device, regmap_base, terminal == ADI_APOLLO_RX ? BF_PC_RX_CNCO_SLICE_SELECT_INFO(index) : BF_PC_TX_CNCO_SLICE_SELECT_INFO(index), enable); + ADI_APOLLO_ERROR_RETURN(err); + } + } + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_gpio_hop_cfir_enable_set(adi_apollo_device_t *device, uint32_t terminal, uint32_t cfirs, uint32_t paths, uint8_t enable) +{ + int32_t err; + int32_t regmap_base = REG_CFIR_SLICE_SELECT_REG_ADDR; + uint32_t cfir, path, i, j, index; + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + for (i = 0; i < ADI_APOLLO_CFIR_NUM; i++) { + cfir = cfirs & (ADI_APOLLO_CFIR_A0 << i); + if (cfir > 0) { + for (j = 0; j < ADI_APOLLO_CFIR_DP_PER_INST_NUM; j++) { + path = paths & (ADI_APOLLO_CFIR_DP_0 << i); + if (path > 0) { + index = i * ADI_APOLLO_CFIR_DP_PER_INST_NUM + j; + err = adi_apollo_hal_bf_set(device, regmap_base, terminal == ADI_APOLLO_RX ? BF_PC_RX_CFIR_SLICE_SELECT_INFO(index) : BF_PC_TX_CFIR_SLICE_SELECT_INFO(index), enable); + ADI_APOLLO_ERROR_RETURN(err); + } + } + } + } + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_gpio_hop_pfilt_enable_set(adi_apollo_device_t *device, uint32_t terminal, uint32_t sides, uint8_t enable) +{ + int32_t err; + int32_t regmap_base = REG_PFILT_SLICE_SELECT_REG_ADDR; + uint32_t side, side_index; + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + for (side_index = 0; side_index < ADI_APOLLO_NUM_SIDES; side_index++) { + side = sides & (ADI_APOLLO_SIDE_A << side_index); + if (side > 0) { + err = adi_apollo_hal_bf_set(device, regmap_base, terminal == ADI_APOLLO_RX ? BF_PC_RX_PFILT_SLICE_SELECT_INFO(side_index) : BF_PC_TX_PFILT_SLICE_SELECT_INFO(side_index), enable); + ADI_APOLLO_ERROR_RETURN(err); + } + } + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_gpio_hop_dynamic_config_enable_set(adi_apollo_device_t *device, uint32_t terminal, uint32_t fdrcs, uint8_t enable) +{ + int32_t err; + int32_t regmap_base = REG_DYN_CONFIG_SLICE_SELECT_REG_ADDR; + uint32_t fdrc, index; + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + for (index = 0; index < ADI_APOLLO_CDUC_NUM; index++) { + fdrc = fdrcs & (ADI_APOLLO_CDUC_A0 << index); + if (fdrc > 0) { + err = adi_apollo_hal_bf_set(device, regmap_base, terminal == ADI_APOLLO_RX ? BF_PC_RX_DR_SLICE_SELECT_INFO(index) : BF_PC_TX_DR_SLICE_SELECT_INFO(index), enable); + ADI_APOLLO_ERROR_RETURN(err); + } + } + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_gpio_hop_bmem_delay_enable_set(adi_apollo_device_t *device, uint32_t bmems, uint8_t enable) +{ + int32_t err; + int32_t regmap_base = REG_BMEM_HOP_SLICE_SELECT_REG_ADDR; + uint32_t bmem, index; + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + for (index = 0; index < ADI_APOLLO_BMEM_NUM; index++) { + bmem = bmems & (ADI_APOLLO_BMEM_A0 << index); + if (bmem > 0) { + err = adi_apollo_hal_bf_set(device, regmap_base, BF_PC_BMEM_HOP_SLICE_SELECT_INFO(index), enable); + ADI_APOLLO_ERROR_RETURN(err); + } + } + return API_CMS_ERROR_OK; +} + + +static uint32_t calc_profile_func_mode(int32_t index) +{ + static uint32_t func_mode[] = { + ADI_APOLLO_FUNC_PROFILE_0, ADI_APOLLO_FUNC_PROFILE_1, ADI_APOLLO_FUNC_PROFILE_2, + ADI_APOLLO_FUNC_PROFILE_3, ADI_APOLLO_FUNC_PROFILE_4 + }; + return (func_mode[index]); +} + +static uint32_t calc_block_func_mode(int32_t index) +{ + static uint32_t func_mode[] = { + ADI_APOLLO_FUNC_PROFILE_FCN_SEL_0, ADI_APOLLO_FUNC_PROFILE_FCN_SEL_1, ADI_APOLLO_FUNC_PROFILE_FCN_SEL_2, ADI_APOLLO_FUNC_PROFILE_FCN_SEL_3 + }; + return (func_mode[index]); +} + +static uint32_t calc_slice_func_mode(int32_t index) +{ + static uint32_t func_mode[] = { + ADI_APOLLO_FUNC_PROFILE_TXRX_SLICE_0, ADI_APOLLO_FUNC_PROFILE_TXRX_SLICE_1, ADI_APOLLO_FUNC_PROFILE_TXRX_SLICE_2 + }; + return (func_mode[index]); +} + +static uint32_t calc_term_func_mode(int32_t index) +{ + static uint32_t func_mode[] = { + ADI_APOLLO_FUNC_PROFILE_TX_RXN_0, ADI_APOLLO_FUNC_PROFILE_TX_RXN_1 + }; + return (func_mode[index]); +} + +const adi_apollo_gpio_hop_profile_t * calc_profile_qc(int32_t index) +{ + static const adi_apollo_gpio_hop_profile_t *map[] = { + NULL, &ADI_APOLLO_GPIO_HOP_PROFILE_1238, &ADI_APOLLO_GPIO_HOP_PROFILE_1238, &ADI_APOLLO_GPIO_HOP_PROFILE_1238, &ADI_APOLLO_GPIO_HOP_PROFILE_45, + &ADI_APOLLO_GPIO_HOP_PROFILE_45, &ADI_APOLLO_GPIO_HOP_PROFILE_6, NULL, &ADI_APOLLO_GPIO_HOP_PROFILE_1238 + }; + return (map[index]); +} + +const adi_apollo_gpio_hop_block_t * calc_block_qc(int32_t index) +{ + static const adi_apollo_gpio_hop_block_t *map[] = { + NULL, &ADI_APOLLO_GPIO_HOP_BLOCK_123, &ADI_APOLLO_GPIO_HOP_BLOCK_123, &ADI_APOLLO_GPIO_HOP_BLOCK_123, &ADI_APOLLO_GPIO_HOP_BLOCK_45, + &ADI_APOLLO_GPIO_HOP_BLOCK_45, NULL, NULL, &ADI_APOLLO_GPIO_HOP_BLOCK_8 + }; + return (map[index]); +} + +const adi_apollo_gpio_hop_side_t * calc_side_qc(int32_t index) +{ + static const adi_apollo_gpio_hop_side_t *map[] = { + NULL, &ADI_APOLLO_GPIO_HOP_SIDE_128, &ADI_APOLLO_GPIO_HOP_SIDE_128, NULL, &ADI_APOLLO_GPIO_HOP_SIDE_45, + &ADI_APOLLO_GPIO_HOP_SIDE_45, NULL, NULL, &ADI_APOLLO_GPIO_HOP_SIDE_128 + }; + return (map[index]); +} + +const adi_apollo_gpio_hop_slice_t * calc_slice_qc(int32_t index) +{ + static const adi_apollo_gpio_hop_slice_t *map[] = { + NULL, &ADI_APOLLO_GPIO_HOP_SLICE_128, &ADI_APOLLO_GPIO_HOP_SLICE_128, NULL, &ADI_APOLLO_GPIO_HOP_SLICE_45, + &ADI_APOLLO_GPIO_HOP_SLICE_45, NULL, NULL, &ADI_APOLLO_GPIO_HOP_SLICE_128 + }; + return (map[index]); +} + +const adi_apollo_gpio_hop_terminal_t * calc_term_qc(int32_t index) +{ + static const adi_apollo_gpio_hop_terminal_t *map[] = { + NULL, &ADI_APOLLO_GPIO_HOP_TERMINAL_128, &ADI_APOLLO_GPIO_HOP_TERMINAL_128, &ADI_APOLLO_GPIO_HOP_TERMINAL_3, &ADI_APOLLO_GPIO_HOP_TERMINAL_45, + &ADI_APOLLO_GPIO_HOP_TERMINAL_45, &ADI_APOLLO_GPIO_HOP_TERMINAL_6, NULL, &ADI_APOLLO_GPIO_HOP_TERMINAL_128 + }; + return (map[index]); +} + +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_hal.c b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_hal.c new file mode 100644 index 00000000000000..0159a566bfa573 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_hal.c @@ -0,0 +1,752 @@ +/*! + * \brief HAL function implementations + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_HAL + * @{ + */ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_config.h" +#include "adi_apollo_hal.h" +#include "adi_apollo_hal_regio_local.h" + +/*============= C O D E ====================*/ +static int32_t bf_set(adi_apollo_hal_regio_t *desc, uint32_t reg, uint8_t offset, uint8_t width, uint8_t reg_bytes, uint64_t value, uint8_t is_paged); +static int32_t bf_set_rmw(adi_apollo_hal_regio_t *desc, uint32_t reg, uint8_t offset, uint8_t width, uint8_t reg_bytes, uint64_t value, uint8_t is_paged); +static int32_t bf_get(adi_apollo_hal_regio_t *desc, uint32_t reg, uint8_t offset, uint8_t width, uint8_t reg_bytes, uint8_t *value, uint8_t value_size_bytes); +static int32_t bf_wait(adi_apollo_device_t *device, uint32_t reg, uint32_t info, uint32_t timeout, uint32_t poll_dly, uint8_t match); + + +int32_t adi_apollo_hal_hw_open(adi_apollo_device_t *device) +{ + ADI_APOLLO_NULL_POINTER_RETURN(device); + if (device->hal_info.hw_open != NULL) { + if (API_CMS_ERROR_OK != device->hal_info.hw_open(device->hal_info.dev_hal_info)) + return API_CMS_ERROR_HW_OPEN; + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_hal_hw_close(adi_apollo_device_t *device) +{ + ADI_APOLLO_NULL_POINTER_RETURN(device); + if (device->hal_info.hw_close != NULL) { + if (API_CMS_ERROR_OK != device->hal_info.hw_close(device->hal_info.dev_hal_info)) + return API_CMS_ERROR_HW_CLOSE; + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_hal_reset_pin_ctrl(adi_apollo_device_t *device, uint8_t enable) +{ + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(device->hal_info.reset_pin_ctrl); + if (API_CMS_ERROR_OK != device->hal_info.reset_pin_ctrl(device->hal_info.user_data, enable)){ + return API_CMS_ERROR_RESET_PIN_CTRL; + } + + return API_CMS_ERROR_OK; +} + + +int32_t adi_apollo_hal_delay_us(adi_apollo_device_t *device, uint32_t us) +{ + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(device->hal_info.delay_us); + if (API_CMS_ERROR_OK != device->hal_info.delay_us(device->hal_info.user_data, us)) { + return API_CMS_ERROR_DELAY_US; + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_hal_log_write(adi_apollo_device_t *device, adi_cms_log_type_e log_type, const char* comment, ...) +{ + va_list argp; + ADI_APOLLO_NULL_POINTER_RETURN(device); + + if (device->hal_info.log_write != NULL) { + va_start(argp, comment); + if (API_CMS_ERROR_OK != device->hal_info.log_write(device->hal_info.user_data, log_type, comment, argp)) + return API_CMS_ERROR_LOG_WRITE; + va_end(argp); + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_hal_error_report(adi_apollo_device_t* device, adi_cms_log_type_e log_type, + int32_t error, const char* file_name, const char* func_name, uint32_t line_num, + const char* var_name, const char* comment) +{ + (void)error; // Prevent compile errors til used. + if (device == NULL) + return API_CMS_ERROR_NULL_PARAM; + + if (API_CMS_ERROR_OK != adi_apollo_hal_log_write(device, log_type, + "%s, \"%s\" in %s(...), line%d in %s", + comment, var_name, func_name, line_num, file_name)) { + return API_CMS_ERROR_LOG_WRITE; + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_hal_bf_wait_to_clear(adi_apollo_device_t *device, uint32_t reg, uint32_t info, uint32_t timeout, uint32_t poll_dly) +{ + return bf_wait(device, reg, info, timeout, poll_dly, 0x00); +} + +int32_t adi_apollo_hal_bf_wait_to_set(adi_apollo_device_t *device, uint32_t reg, uint32_t info, uint32_t timeout, uint32_t poll_dly) +{ + return bf_wait(device, reg, info, timeout, poll_dly, 0x01); +} + +int32_t adi_apollo_hal_bf_get(adi_apollo_device_t *device, uint32_t reg, uint32_t info, uint8_t value[], uint8_t value_size_bytes) +{ + int32_t err; + uint8_t offset = (uint8_t)(info >> 0), width = (uint8_t)(info >> 8); + uint8_t reg_bytes = ((width + offset) >> 3) + (((width + offset) & 7) == 0 ? 0 : 1); + adi_apollo_hal_regio_t *desc; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(device->hal_info.active_regio); + ADI_APOLLO_INVALID_PARAM_RETURN(width > 64); + ADI_APOLLO_INVALID_PARAM_RETURN(width < 1); + ADI_APOLLO_INVALID_PARAM_RETURN(reg_bytes > sizeof(uint64_t) + 1); + ADI_APOLLO_INVALID_PARAM_RETURN(reg_bytes < 1); + + desc = device->hal_info.active_regio; + + err = bf_get(desc, reg, offset, width, reg_bytes, value, value_size_bytes); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_hal_reg_set(adi_apollo_device_t *device, uint32_t reg, uint8_t data) +{ + int32_t err; + adi_apollo_hal_regio_t *desc; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(device->hal_info.active_regio); + + desc = device->hal_info.active_regio; + + err = ((adi_apollo_hal_regio_ops_t*)desc->ops)->wr_reg(desc->child_desc, reg, data); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_hal_reg32_set(adi_apollo_device_t *device, uint32_t reg, uint32_t data) +{ + int32_t err; + adi_apollo_hal_regio_t *desc; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(device->hal_info.active_regio); + + desc = device->hal_info.active_regio; + + err = ((adi_apollo_hal_regio_ops_t*)desc->ops)->wr_reg32(desc->child_desc, reg, data); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_hal_stream_reg_set(adi_apollo_device_t *device, uint32_t reg, uint8_t data[], uint32_t data_len_bytes, uint8_t is_cont) +{ + int32_t err; + adi_apollo_hal_regio_t *desc; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(device->hal_info.active_regio); + + desc = device->hal_info.active_regio; + + err = ((adi_apollo_hal_regio_ops_t*)desc->ops)->stream_wr_reg(desc->child_desc, reg, data, data_len_bytes, is_cont); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_hal_stream_reg32_set(adi_apollo_device_t *device, uint32_t reg, uint32_t data[], uint32_t data_len_words, uint8_t is_cont) +{ + int32_t err; + adi_apollo_hal_regio_t *desc; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(device->hal_info.active_regio); + + desc = device->hal_info.active_regio; + + err = ((adi_apollo_hal_regio_ops_t*)desc->ops)->stream_wr_reg32(desc->child_desc, reg, data, data_len_words, is_cont); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_hal_stream_reg_get(adi_apollo_device_t *device, uint32_t reg, uint8_t data[], uint32_t data_len_bytes, uint8_t is_cont) +{ + int32_t err; + adi_apollo_hal_regio_t *desc; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(device->hal_info.active_regio); + + desc = device->hal_info.active_regio; + + err = ((adi_apollo_hal_regio_ops_t*)desc->ops)->stream_rd_reg(desc->child_desc, reg, data, data_len_bytes, is_cont); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_hal_stream_reg32_get(adi_apollo_device_t *device, uint32_t reg, uint32_t data[], uint32_t data_len_words, uint8_t is_cont) +{ + int32_t err; + adi_apollo_hal_regio_t *desc; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(device->hal_info.active_regio); + + desc = device->hal_info.active_regio; + + err = ((adi_apollo_hal_regio_ops_t*)desc->ops)->stream_rd_reg32(desc->child_desc, reg, data, data_len_words, is_cont); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_hal_masked_reg_set(adi_apollo_device_t *device, uint32_t reg, uint8_t data, uint8_t mask) +{ + int32_t err; + adi_apollo_hal_regio_t *desc; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(device->hal_info.active_regio); + + desc = device->hal_info.active_regio; + + err = ((adi_apollo_hal_regio_ops_t*)desc->ops)->wr_reg_rmw(desc->child_desc, reg, data, mask, ADI_APOLLO_HAL_REGIO_NOT_PAGED); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_hal_paged_masked_reg_set(adi_apollo_device_t *device, uint32_t reg, uint8_t data, uint8_t mask) +{ + int32_t err; + adi_apollo_hal_regio_t *desc; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(device->hal_info.active_regio); + + desc = device->hal_info.active_regio; + + err = ((adi_apollo_hal_regio_ops_t*)desc->ops)->wr_reg_rmw(desc->child_desc, reg, data, mask, ADI_APOLLO_HAL_REGIO_PAGED); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_hal_paged_base_addr_set(adi_apollo_device_t *device, uint32_t base_addr) +{ + int32_t err; + adi_apollo_hal_regio_t *desc; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(device->hal_info.active_regio); + + desc = device->hal_info.active_regio; + + err = ((adi_apollo_hal_regio_ops_t*)desc->ops)->set_page_base_addr(desc->child_desc, base_addr); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_hal_paged_reg_set(adi_apollo_device_t *device, uint32_t reg, uint8_t data) +{ + int32_t err; + adi_apollo_hal_regio_t *desc; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(device->hal_info.active_regio); + + desc = device->hal_info.active_regio; + + err = ((adi_apollo_hal_regio_ops_t*)desc->ops)->wr_reg_paged(desc->child_desc, reg, data); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_hal_paged_reg32_set(adi_apollo_device_t *device, uint32_t reg, uint32_t data) +{ + int32_t err; + adi_apollo_hal_regio_t *desc; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(device->hal_info.active_regio); + + desc = device->hal_info.active_regio; + + err = ((adi_apollo_hal_regio_ops_t*)desc->ops)->wr_reg32_paged(desc->child_desc, reg, data); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_hal_reg_get(adi_apollo_device_t *device, uint32_t reg, uint8_t *data) +{ + int32_t err; + adi_apollo_hal_regio_t *desc; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(device->hal_info.active_regio); + + desc = device->hal_info.active_regio; + + err = ((adi_apollo_hal_regio_ops_t*)desc->ops)->rd_reg(desc->child_desc, reg, data); + + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_hal_reg32_get(adi_apollo_device_t *device, uint32_t reg, uint32_t *data) +{ + int32_t err; + adi_apollo_hal_regio_t *desc; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(device->hal_info.active_regio); + + desc = device->hal_info.active_regio; + + err = ((adi_apollo_hal_regio_ops_t*)desc->ops)->rd_reg32(desc->child_desc, reg, data); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_hal_bf_set(adi_apollo_device_t *device, uint32_t reg, uint32_t info, uint64_t value) +{ + int32_t err; + uint8_t offset = (uint8_t)(info >> 0), width = (uint8_t)(info >> 8); + uint8_t reg_bytes = ((width + offset) >> 3) + (((width + offset) & 7) == 0 ? 0 : 1); + adi_apollo_hal_regio_t *desc; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(device->hal_info.active_regio); + ADI_APOLLO_INVALID_PARAM_RETURN(width > 64); + ADI_APOLLO_INVALID_PARAM_RETURN(width < 1); + + desc = device->hal_info.active_regio; + + if (desc->rmw_enabled) { + err = bf_set_rmw(desc, reg, offset, width, reg_bytes, value, ADI_APOLLO_HAL_REGIO_PAGED); + ADI_APOLLO_ERROR_RETURN(err); + } else { + err = bf_set(desc, reg, offset, width, reg_bytes, value, ADI_APOLLO_HAL_REGIO_NOT_PAGED); + ADI_APOLLO_ERROR_RETURN(err); + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_hal_paged_bf_set(adi_apollo_device_t *device, uint32_t reg, uint32_t info, uint64_t value) +{ + int32_t err; + uint8_t offset = (uint8_t)(info >> 0), width = (uint8_t)(info >> 8); + uint8_t reg_bytes = ((width + offset) >> 3) + (((width + offset) & 7) == 0 ? 0 : 1); + adi_apollo_hal_regio_t *desc; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(device->hal_info.active_regio); + ADI_APOLLO_INVALID_PARAM_RETURN(width > 64); + ADI_APOLLO_INVALID_PARAM_RETURN(width < 1); + + desc = device->hal_info.active_regio; + + if (desc->rmw_enabled) { + err = bf_set_rmw(desc, reg, offset, width, reg_bytes, value, ADI_APOLLO_HAL_REGIO_PAGED); + ADI_APOLLO_ERROR_RETURN(err); + } else { + err = bf_set(desc, reg, offset, width, reg_bytes, value, ADI_APOLLO_HAL_REGIO_PAGED); + ADI_APOLLO_ERROR_RETURN(err); + } + + return API_CMS_ERROR_OK; +} + + +int32_t adi_apollo_hal_reg_poll_get(adi_apollo_device_t *device, uint32_t reg, uint8_t *data, uint32_t timeout_us, uint8_t reg_expect, uint8_t reg_mask) +{ + int32_t err; + adi_apollo_hal_regio_t *desc; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(device->hal_info.active_regio); + + desc = device->hal_info.active_regio; + + err = ((adi_apollo_hal_regio_ops_t*)desc->ops)->rd_reg_poll(desc->child_desc, reg, data, timeout_us, reg_expect, reg_mask); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_hal_active_protocol_set(adi_apollo_device_t *device, adi_apollo_hal_protocol_e protocol) +{ + ADI_APOLLO_NULL_POINTER_RETURN(device); + + if (protocol == ADI_APOLLO_HAL_PROTOCOL_SPI0) { + device->hal_info.active_regio = &device->hal_info.spi0_desc.base_regio; + } else if (protocol == ADI_APOLLO_HAL_PROTOCOL_SPI1) { + device->hal_info.active_regio = &device->hal_info.spi1_desc.base_regio; + } else if (protocol == ADI_APOLLO_HAL_PROTOCOL_HSCI) { + device->hal_info.active_regio = &device->hal_info.hsci_desc.base_regio; + } else { + return API_CMS_ERROR_INVALID_PARAM; + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_hal_active_protocol_get(adi_apollo_device_t *device, adi_apollo_hal_protocol_e *protocol) +{ + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(protocol); + + *protocol = ((adi_apollo_hal_regio_t *)device->hal_info.active_regio)->protocol_id; + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_hal_rmw_enable_set(adi_apollo_device_t *device, adi_apollo_hal_protocol_e protocol, uint8_t rmw_en) +{ + ADI_APOLLO_NULL_POINTER_RETURN(device); + + if (protocol == ADI_APOLLO_HAL_PROTOCOL_SPI0) { + device->hal_info.spi0_desc.base_regio.rmw_enabled = rmw_en; + } else if (protocol == ADI_APOLLO_HAL_PROTOCOL_SPI1) { + device->hal_info.spi1_desc.base_regio.rmw_enabled = rmw_en; + } else if (protocol == ADI_APOLLO_HAL_PROTOCOL_HSCI) { + device->hal_info.hsci_desc.base_regio.rmw_enabled = rmw_en; + } else { + return API_CMS_ERROR_INVALID_PARAM; + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_hal_rmw_enable_get(adi_apollo_device_t *device, adi_apollo_hal_protocol_e protocol, uint8_t *rmw_en) +{ + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(rmw_en); + + if (protocol == ADI_APOLLO_HAL_PROTOCOL_SPI0) { + *rmw_en = device->hal_info.spi0_desc.base_regio.rmw_enabled; + } else if (protocol == ADI_APOLLO_HAL_PROTOCOL_SPI1) { + *rmw_en = device->hal_info.spi1_desc.base_regio.rmw_enabled; + } else if (protocol == ADI_APOLLO_HAL_PROTOCOL_HSCI) { + *rmw_en = device->hal_info.hsci_desc.base_regio.rmw_enabled; + } else { + return API_CMS_ERROR_INVALID_PARAM; + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_hal_manual_linkup(adi_apollo_device_t *device, uint8_t enable, uint16_t link_up_signal_bits) +{ + int32_t err; + adi_apollo_hal_protocol_e protocol; + adi_apollo_hal_regio_t *desc; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(device->hal_info.active_regio); + + // Save the current protocol + err = adi_apollo_hal_active_protocol_get(device, &protocol); + ADI_APOLLO_ERROR_RETURN(err); + + // Change the protocol to HSCI to access hooks for manual linkup HAL function + err = adi_apollo_hal_active_protocol_set(device, ADI_APOLLO_HAL_PROTOCOL_HSCI); + ADI_APOLLO_ERROR_RETURN(err); + + // Invoke manual link-up method + desc = device->hal_info.active_regio; + + err = ((adi_apollo_hal_regio_ops_t*)desc->ops)->manual_linkup(desc->child_desc, enable, link_up_signal_bits); + ADI_APOLLO_ERROR_RETURN(err); + + // Revert protocol + err = adi_apollo_hal_active_protocol_set(device, protocol); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_hal_auto_linkup(adi_apollo_device_t *device, uint8_t enable, uint8_t hscim_mosi_clk_inv, uint8_t hscim_miso_clk_inv) +{ + int32_t err; + adi_apollo_hal_protocol_e protocol; + adi_apollo_hal_regio_t *desc; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(device->hal_info.active_regio); + + // Save the current protocol + err = adi_apollo_hal_active_protocol_get(device, &protocol); + ADI_APOLLO_ERROR_RETURN(err); + + // Change the protocol to HSCI to access hooks for auto linkup HAL function + err = adi_apollo_hal_active_protocol_set(device, ADI_APOLLO_HAL_PROTOCOL_HSCI); + ADI_APOLLO_ERROR_RETURN(err); + + // Invoke auto link-up method + desc = device->hal_info.active_regio; + + err = ((adi_apollo_hal_regio_ops_t*)desc->ops)->auto_linkup(desc->child_desc, enable, hscim_mosi_clk_inv, hscim_miso_clk_inv); + ADI_APOLLO_ERROR_RETURN(err); + + // Revert protocol + err = adi_apollo_hal_active_protocol_set(device, protocol); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_hal_alink_tbl_get(adi_apollo_device_t *device, uint16_t *hscim_alink_table) +{ + int32_t err; + adi_apollo_hal_protocol_e protocol; + adi_apollo_hal_regio_t *desc; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(device->hal_info.active_regio); + + // Save the current protocol + err = adi_apollo_hal_active_protocol_get(device, &protocol); + ADI_APOLLO_ERROR_RETURN(err); + + // Change the protocol to HSCI to access hooks for auto linkup HAL function + err = adi_apollo_hal_active_protocol_set(device, ADI_APOLLO_HAL_PROTOCOL_HSCI); + ADI_APOLLO_ERROR_RETURN(err); + + // Invoke auto link-up method + desc = device->hal_info.active_regio; + + err = ((adi_apollo_hal_regio_ops_t*)desc->ops)->alink_tbl_get(desc->child_desc, hscim_alink_table); + ADI_APOLLO_ERROR_RETURN(err); + + // Revert protocol + err = adi_apollo_hal_active_protocol_set(device, protocol); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +static int32_t bf_set(adi_apollo_hal_regio_t *desc, uint32_t reg, uint8_t offset, uint8_t width, uint8_t reg_bytes, uint64_t value, uint8_t is_paged) +{ + int32_t err; + uint32_t mask = 0; + uint8_t reg_offset = (offset/8), data8 = 0; + offset = offset % 8; + + for (;reg_offset < reg_bytes; reg_offset++) { + if ((offset + width) <= 8) { /* last 8bits */ + if ((offset > 0) || ((offset + width) < 8)) { + err = ((adi_apollo_hal_regio_ops_t*)desc->ops)->rd_reg(desc->child_desc, reg + reg_offset, &data8); + ADI_APOLLO_ERROR_RETURN(err); + } + mask = (1 << width) - 1; + data8 = data8 & (~(mask << offset)); + data8 = data8 | ((value & mask) << offset); + } + else { + if (offset > 0) { + err = ((adi_apollo_hal_regio_ops_t*)desc->ops)->rd_reg(desc->child_desc, reg + reg_offset, &data8); + ADI_APOLLO_ERROR_RETURN(err); + } + mask = (1 << (8 - offset)) - 1; + data8 = data8 & (~(mask << offset)); + data8 = data8 | ((value & mask) << offset); + value = value >> (8 - offset); + width = width - (8 - offset); + offset = 0; + } + if (is_paged) { + err = ((adi_apollo_hal_regio_ops_t*)desc->ops)->wr_reg_paged(desc->child_desc, reg + reg_offset, data8); + } else { + err = ((adi_apollo_hal_regio_ops_t*)desc->ops)->wr_reg(desc->child_desc, reg + reg_offset, data8); + } + ADI_APOLLO_ERROR_RETURN(err); + } + + return API_CMS_ERROR_OK; +} + +static int32_t bf_set_rmw(adi_apollo_hal_regio_t *desc, uint32_t reg, uint8_t offset, uint8_t width, uint8_t reg_bytes, uint64_t value, uint8_t is_paged) +{ + int32_t err; + uint8_t mask = 0; + uint8_t reg_offset = (offset / 8), data8 = 0; + offset = offset % 8; + + for (; reg_offset < reg_bytes; reg_offset++) { + if ((offset + width) <= 8) { + /* last 8bits */ + mask = ((1 << width) - 1) << offset; + data8 = (uint8_t)(value << offset); + } + else { + mask = ~((1 << offset) - 1); // rmw mask - 1's represent bits to set + data8 = (uint8_t)(value << offset); + value = value >> (8 - offset); + width = width - (8 - offset); + offset = 0; + } + + err = ((adi_apollo_hal_regio_ops_t*)desc->ops)->wr_reg_rmw(desc->child_desc, reg + reg_offset, data8, mask, is_paged); + ADI_APOLLO_ERROR_RETURN(err); + } + + return API_CMS_ERROR_OK; +} + +static int32_t bf_get(adi_apollo_hal_regio_t *desc, uint32_t reg, uint8_t offset, uint8_t width, uint8_t reg_bytes, uint8_t value[], uint8_t value_size_bytes) +{ + int32_t err; + uint8_t reg_offset = 0, data8 = 0; + uint32_t mask = 0, endian_test_val = 0x11223344; + uint64_t bf_val = 0; + uint8_t i = 0, j = 0, filled_bits = 0; + + uint64_t bf_mask64 = (reg_bytes >= sizeof(uint64_t)) ? UINT64_MAX : ((1ull<ops)->rd_bf(desc->child_desc, reg, bf_reg_buff, reg_bytes, bf_mask64); + ADI_APOLLO_ERROR_RETURN(err); + + reg_offset = (offset / 8); + offset = offset % 8; + + for (; reg_offset < reg_bytes; reg_offset++) { + if ((offset + width) <= 8) { /* last 8bits */ + mask = (1 << width) - 1; + data8 = bf_reg_buff[reg_offset]; + data8 = (data8 >> offset) & mask; + bf_val = bf_val + ((uint64_t)data8 << filled_bits); + filled_bits = filled_bits + width; + } + else { + mask = (1 << (8 - offset)) - 1; + data8 = bf_reg_buff[reg_offset]; + data8 = (data8 >> offset) & mask; + bf_val = bf_val + ((uint64_t)data8 << filled_bits); + width = width - (8 - offset); + filled_bits = filled_bits + (8 - offset); + offset = 0; + } + } + + /* Save bitfield value to buffer with proper endianness */ + for(i = 0; i < value_size_bytes; i++) { + j = (*(uint8_t *)&endian_test_val == 0x44) ? (i) : (value_size_bytes - 1 - i); + value[j] = (uint8_t)(bf_val >> (i << 3)); + } + + return API_CMS_ERROR_OK; +} + +static int32_t bf_wait(adi_apollo_device_t *device, uint32_t reg, uint32_t info, uint32_t timeout, uint32_t poll_dly, uint8_t match) +{ + int32_t err; + uint8_t reg_or_bf_value = 0; + uint8_t offset = (uint8_t)info; + uint8_t width = (uint8_t)(info >> 8); + uint8_t reg_mask = (1 << offset); + uint8_t reg_exp = (match << offset); + uint8_t reg_offset = offset / 8; + uint32_t poll_dly_cnt = 0; + adi_apollo_hal_regio_t *desc; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_INVALID_PARAM_RETURN(poll_dly < 1); + ADI_APOLLO_INVALID_PARAM_RETURN(width > 1); + ADI_APOLLO_INVALID_PARAM_RETURN(match > 1); + + desc = device->hal_info.active_regio; + + if (desc->poll_read_en) { + /* Poll read function handles timeout condition */ + return ((adi_apollo_hal_regio_ops_t*)desc->ops)->rd_reg_poll(desc->child_desc, reg + reg_offset, ®_or_bf_value, timeout, reg_exp, reg_mask); + } else { + for (poll_dly_cnt = 0; poll_dly_cnt < timeout; poll_dly_cnt += poll_dly) { + err = adi_apollo_hal_delay_us(device, poll_dly); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, reg, info, ®_or_bf_value, 1); + ADI_APOLLO_ERROR_RETURN(err); + + if (reg_or_bf_value == match) { + return API_CMS_ERROR_OK; + } + } + } + + return API_CMS_ERROR_OPERATION_TIMEOUT; +} + +int32_t adi_apollo_hal_buffer_set(adi_apollo_device_t* device, adi_apollo_hal_protocol_e protocol, uint8_t *buff, uint32_t buff_len) +{ + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(buff); + ADI_APOLLO_INVALID_PARAM_RETURN(buff_len > ADI_APOLLO_HAL_BUFFER_LEN_MAX); + ADI_APOLLO_INVALID_PARAM_RETURN(buff_len < ADI_APOLLO_HAL_BUFFER_LEN_MIN); + + if (protocol == ADI_APOLLO_HAL_PROTOCOL_HSCI) { + device->hal_info.hsci_desc.buff = buff; + device->hal_info.hsci_desc.buff_len = buff_len; + } else { + return API_CMS_ERROR_NOT_SUPPORTED; + } + + return API_CMS_ERROR_OK; +} + + +int32_t adi_apollo_hal_buffer_get(adi_apollo_device_t* device, adi_apollo_hal_protocol_e protocol, uint8_t **buff, uint32_t *buff_len) +{ + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(buff); + ADI_APOLLO_NULL_POINTER_RETURN(buff_len); + + if (protocol == ADI_APOLLO_HAL_PROTOCOL_HSCI) { + *buff = device->hal_info.hsci_desc.buff; + *buff_len = device->hal_info.hsci_desc.buff_len; + } else { + *buff = NULL; + *buff_len = 0; + return API_CMS_ERROR_NOT_SUPPORTED; + } + + return API_CMS_ERROR_OK; +} + +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_hal_regio_hsci.c b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_hal_regio_hsci.c new file mode 100644 index 00000000000000..6ea370d6399e55 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_hal_regio_hsci.c @@ -0,0 +1,591 @@ +/*! + * \brief HAL HSCI function implementations + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +#include "adi_apollo_config.h" +#include "adi_apollo_hal_regio_local.h" +#include "adi_apollo_hal_regio_hsci_types.h" + +static int32_t hsci_regio_write(adi_apollo_hal_regio_hsci_desc_t *desc, uint32_t reg, uint8_t data); +static int32_t hsci_regio_write32(adi_apollo_hal_regio_hsci_desc_t *desc, uint32_t reg, uint32_t data); +static int32_t hsci_regio_rmw_write(adi_apollo_hal_regio_hsci_desc_t *desc, uint32_t reg, uint8_t data, uint8_t mask, uint8_t is_paged); +static int32_t hsci_regio_paged_base_addr_set(adi_apollo_hal_regio_hsci_desc_t *desc, uint32_t address); +static int32_t hsci_regio_paged_write(adi_apollo_hal_regio_hsci_desc_t *desc, uint32_t address, uint8_t data); +static int32_t hsci_regio_paged_write32(adi_apollo_hal_regio_hsci_desc_t *desc, uint32_t address, uint32_t data); +static int32_t hsci_regio_read(adi_apollo_hal_regio_hsci_desc_t *desc, uint32_t reg, uint8_t *data); +static int32_t hsci_regio_read32(adi_apollo_hal_regio_hsci_desc_t *desc, uint32_t reg, uint32_t *data); +static int32_t hsci_regio_stream_write(adi_apollo_hal_regio_hsci_desc_t *desc, uint32_t reg, uint8_t *data, uint32_t data_len_bytes, uint8_t is_cont); +static int32_t hsci_regio_stream_write32(adi_apollo_hal_regio_hsci_desc_t *desc, uint32_t reg, uint32_t *data, uint32_t data_len_words, uint8_t is_cont); +static int32_t hsci_regio_stream_read(adi_apollo_hal_regio_hsci_desc_t *desc, uint32_t reg, uint8_t *data, uint32_t data_len_bytes, uint8_t is_cont); +static int32_t hsci_regio_stream_read32(adi_apollo_hal_regio_hsci_desc_t *desc, uint32_t reg, uint32_t *data, uint32_t data_len_words, uint8_t is_cont); +static int32_t hsci_regio_poll_read(adi_apollo_hal_regio_hsci_desc_t *desc, uint32_t reg, uint8_t *data, uint32_t timeout_us, uint8_t reg_expect, uint8_t reg_mask); +static int32_t alt_hsci_regio_poll_read(adi_apollo_hal_regio_hsci_desc_t *desc, uint32_t reg, uint8_t *data, uint32_t timeout_us, uint8_t reg_expect, uint8_t reg_mask); +static int32_t hsci_regio_read_bf(adi_apollo_hal_regio_hsci_desc_t *desc, uint32_t reg, uint8_t *data, uint32_t data_len_bytes, uint64_t mask); +static int32_t hsci_regio_manual_linkup(adi_apollo_hal_regio_hsci_desc_t *desc, uint8_t enable, uint16_t link_up_signal_bits); +static int32_t hsci_regio_auto_linkup(adi_apollo_hal_regio_hsci_desc_t *desc, uint8_t enable, uint8_t hscim_mosi_clk_inv, uint8_t hscim_miso_clk_inv); +static int32_t hsci_regio_alink_tbl_get(adi_apollo_hal_regio_hsci_desc_t *desc, uint16_t *hscim_alink_table); + +/* HSCI implementations of regio operations */ +static adi_apollo_hal_regio_ops_t hsci_regio_ops = { + .wr_reg = (adi_apollo_hal_regio_wr_reg_t) &hsci_regio_write, + .wr_reg32 = (adi_apollo_hal_regio_wr_reg32_t) &hsci_regio_write32, + .wr_reg_rmw = (adi_apollo_hal_regio_wr_reg_rmw_t) &hsci_regio_rmw_write, + .wr_reg_paged = (adi_apollo_hal_regio_wr_reg_paged_t) &hsci_regio_paged_write, + .wr_reg32_paged = (adi_apollo_hal_regio_wr_reg32_paged_t) &hsci_regio_paged_write32, + .rd_reg = (adi_apollo_hal_regio_rd_reg_t) &hsci_regio_read, + .rd_reg32 = (adi_apollo_hal_regio_rd_reg32_t) &hsci_regio_read32, + .rd_reg_poll = (adi_apollo_hal_regio_rd_reg_poll_t) &hsci_regio_poll_read, + .set_page_base_addr = (adi_apollo_hal_regio_set_page_base_addr_t) &hsci_regio_paged_base_addr_set, + .stream_wr_reg = (adi_apollo_hal_regio_stream_wr_reg_t) &hsci_regio_stream_write, + .stream_wr_reg32 = (adi_apollo_hal_regio_stream_wr_reg32_t) &hsci_regio_stream_write32, + .stream_rd_reg = (adi_apollo_hal_regio_stream_rd_reg_t) &hsci_regio_stream_read, + .stream_rd_reg32 = (adi_apollo_hal_regio_stream_rd_reg32_t) &hsci_regio_stream_read32, + .rd_bf = (adi_apollo_hal_regio_rd_bf_t) &hsci_regio_read_bf, + .manual_linkup = (adi_apollo_hal_regio_manual_linkup_t) &hsci_regio_manual_linkup, + .auto_linkup = (adi_apollo_hal_regio_auto_linkup_t) &hsci_regio_auto_linkup, + .alink_tbl_get = (adi_apollo_hal_regio_alink_tbl_get_t) &hsci_regio_alink_tbl_get, +}; + +/* Predefined transaction configs */ +static adi_apollo_hal_txn_config_t txn_cfgs[] = { + {.addr_len = 4, .data_len = 1, .stream_len = 1}, /* Single 8-bit transaction */ + {.addr_len = 4, .data_len = 2, .stream_len = 1}, /* Single 16-bit transaction */ + {.addr_len = 4, .data_len = 4, .stream_len = 1}, /* Single 32-bit transaction */ +}; + +/* Default poll read if not define */ +static int32_t alt_hsci_regio_poll_read(adi_apollo_hal_regio_hsci_desc_t *desc, uint32_t reg, uint8_t *data, uint32_t timeout_us, uint8_t reg_expect, uint8_t reg_mask) +{ + return hsci_regio_read(desc, reg, data); +} + +int32_t adi_apollo_l_hal_regio_hsci_init(adi_apollo_hal_regio_hsci_desc_t *desc) +{ + if (desc == NULL) { + return API_CMS_ERROR_NULL_PARAM; + } + + desc->base_regio.ops = &hsci_regio_ops; // interface + desc->base_regio.child_desc = desc; // instance + desc->base_regio.protocol_id = ADI_APOLLO_HAL_PROTOCOL_HSCI; + + /* If the user didn't specify an optional poll read hal, use the built in alternate */ + if (desc->poll_read == NULL) { + hsci_regio_ops.rd_reg_poll = (adi_apollo_hal_regio_rd_reg_poll_t) &alt_hsci_regio_poll_read; + desc->base_regio.poll_read_returns_val = 1; + } + desc->base_regio.poll_read_en = (desc->poll_read != NULL); + + return API_CMS_ERROR_OK; +} + +static int32_t hsci_write(adi_apollo_hal_regio_hsci_desc_t *desc, uint32_t addr, uint32_t data, adi_apollo_hal_regio_hsci_bus_size_e buf_size) +{ + int32_t err; + uint8_t xfer_sz_bytes = 0; + uint8_t in_data[8] = {0}; + uint8_t out_data[8] = {0}; + + if (!desc) + { + return API_CMS_ERROR_NULL_PARAM; + } + + /* Assign 32-bit reg address */ + in_data[0] = (addr >> 0) & 0xFF; + in_data[1] = (addr >> 8) & 0xFF; + in_data[2] = (addr >> 16) & 0xFF; + in_data[3] = (addr >> 24) & 0xFF; + xfer_sz_bytes += 4; + + /* Assign data */ + if (buf_size == ADI_APOLLO_HAL_REGIO_HSCI_BUS_SIZE_D8) + { + in_data[4] = data & 0xFF; + xfer_sz_bytes += 1; + } + else if (buf_size == ADI_APOLLO_HAL_REGIO_HSCI_BUS_SIZE_D16) + { + in_data[4] = data & 0xFF; + in_data[5] = (data >> 8) & 0xFF; + xfer_sz_bytes += 2; + } + else if (buf_size == ADI_APOLLO_HAL_REGIO_HSCI_BUS_SIZE_D32) + { + in_data[4] = data & 0xFF; + in_data[5] = (data >> 8) & 0xFF; + in_data[6] = (data >> 16) & 0xFF; + in_data[7] = (data >> 24) & 0xFF; + xfer_sz_bytes += 4; + } + /* write method takes precedence over xfer if both defined */ + if (desc->write != NULL) { + err = desc->write(desc->dev_obj, in_data, xfer_sz_bytes, &txn_cfgs[buf_size]); + ADI_APOLLO_ERROR_RETURN(err); + } + else if (desc->xfer != NULL) { + err = desc->xfer(desc->dev_obj, in_data, out_data, xfer_sz_bytes); + ADI_APOLLO_ERROR_RETURN(err); + } + else + { + return API_CMS_ERROR_NULL_PARAM; + } + + return err; +} + + +static int32_t hsci_rmw(adi_apollo_hal_regio_hsci_desc_t *desc, uint32_t addr, uint32_t data, uint32_t mask, adi_apollo_hal_regio_hsci_bus_size_e buf_size) +{ + int32_t err; + uint8_t xfer_sz_bytes = 0; + uint8_t in_data[12] = {0}; + uint8_t out_data[12] = {0}; + adi_apollo_hal_txn_config_t txn_config; + + if (!desc) + { + return API_CMS_ERROR_NULL_PARAM; + } + + /* Assign 32-bit reg address */ + in_data[0] = (addr >> 0) & 0xFF; + in_data[1] = (addr >> 8) & 0xFF; + in_data[2] = (addr >> 16) & 0xFF; + in_data[3] = (addr >> 24) & 0xFF; + xfer_sz_bytes += 4; + + /* Assign data */ + if (buf_size == ADI_APOLLO_HAL_REGIO_HSCI_BUS_SIZE_D8) + { + in_data[4] = mask & 0xFF; + in_data[5] = data & 0xFF; + xfer_sz_bytes += 2; + } + else if (buf_size == ADI_APOLLO_HAL_REGIO_HSCI_BUS_SIZE_D16) + { + in_data[4] = mask & 0xFF; + in_data[5] = (mask >> 8) & 0xFF; + in_data[6] = data & 0xFF; + in_data[7] = (data >> 8) & 0xFF; + xfer_sz_bytes += 4; + } + else if (buf_size == ADI_APOLLO_HAL_REGIO_HSCI_BUS_SIZE_D32) + { + in_data[4] = mask & 0xFF; + in_data[5] = (mask >> 8) & 0xFF; + in_data[6] = (mask >> 16) & 0xFF; + in_data[7] = (mask >> 24) & 0xFF; + + in_data[8] = data & 0xFF; + in_data[9] = (data >> 8) & 0xFF; + in_data[10] = (data >> 16) & 0xFF; + in_data[11] = (data >> 24) & 0xFF; + xfer_sz_bytes += 8; + } + /* write method takes precedence over xfer if both defined */ + if (desc->write != NULL) { + txn_config = txn_cfgs[buf_size]; + txn_config.mask = mask; + txn_config.is_bf_txn = 0x81; // is_bf_txn[7] = rmw, is_bf_txn[0] = is bf transaction + err = desc->write(desc->dev_obj, in_data, xfer_sz_bytes, &txn_config); + ADI_APOLLO_ERROR_RETURN(err); + } + else if (desc->xfer != NULL) { + err = desc->xfer(desc->dev_obj, in_data, out_data, xfer_sz_bytes); + ADI_APOLLO_ERROR_RETURN(err); + } + else + { + return API_CMS_ERROR_NULL_PARAM; + } + + return err; +} + +static int32_t hsci_read(adi_apollo_hal_regio_hsci_desc_t *desc, uint32_t addr, uint32_t *data, adi_apollo_hal_regio_hsci_bus_size_e buf_size) +{ + int32_t err; + uint8_t xfer_sz_bytes = 0; + uint8_t in_data[8] = {0}; + uint8_t out_data[8] = {0}; + + /* Assign 32-bit reg address */ + in_data[0] = (addr >> 0) & 0xFF; + in_data[1] = (addr >> 8) & 0xFF; + in_data[2] = (addr >> 16) & 0xFF; + in_data[3] = (addr >> 24) & 0xFF; + xfer_sz_bytes += 4; + if (buf_size == ADI_APOLLO_HAL_REGIO_HSCI_BUS_SIZE_D8) { + xfer_sz_bytes += 1; + } else if (buf_size == ADI_APOLLO_HAL_REGIO_HSCI_BUS_SIZE_D32) { + xfer_sz_bytes += 4; + } else if (buf_size == ADI_APOLLO_HAL_REGIO_HSCI_BUS_SIZE_D16) { + xfer_sz_bytes += 2; + } else { + return API_CMS_ERROR_HSCI_REGIO_XFER; + } + + /* read method takes precedence over xfer if both defined */ + if (desc->read != NULL) { + err = desc->read(desc->dev_obj, in_data, out_data, xfer_sz_bytes, &txn_cfgs[buf_size]); + ADI_APOLLO_ERROR_RETURN(err); + } + else if (desc->xfer != NULL) { + err = desc->xfer(desc->dev_obj, in_data, out_data, xfer_sz_bytes); + ADI_APOLLO_ERROR_RETURN(err); + } + else + { + return API_CMS_ERROR_NULL_PARAM; + } + + *data = 0; + if (buf_size == ADI_APOLLO_HAL_REGIO_HSCI_BUS_SIZE_D8) { + *data |= out_data[4]; + } else if (buf_size == ADI_APOLLO_HAL_REGIO_HSCI_BUS_SIZE_D32) { + *data |= out_data[4] << 24; + *data |= out_data[5] << 16; + *data |= out_data[6] << 8; + *data |= out_data[7] << 0; + } else if (buf_size == ADI_APOLLO_HAL_REGIO_HSCI_BUS_SIZE_D16) { + *data |= out_data[4] << 8; + *data |= out_data[5] << 0; + } else { + return API_CMS_ERROR_HSCI_REGIO_XFER; + } + return err; +} + +static int32_t hsci_poll_read(adi_apollo_hal_regio_hsci_desc_t *desc, uint32_t addr, uint32_t *data, adi_apollo_hal_regio_hsci_bus_size_e buf_size, uint32_t timeout_us, uint8_t reg_expect, uint8_t reg_mask) +{ + int32_t err; + uint8_t xfer_sz_bytes = 0; + uint8_t in_data[8] = {0}; + uint8_t out_data[8] = {0}; + + /* Assign 32-bit reg address */ + in_data[0] = (addr >> 0) & 0xFF; + in_data[1] = (addr >> 8) & 0xFF; + in_data[2] = (addr >> 16) & 0xFF; + in_data[3] = (addr >> 24) & 0xFF; + xfer_sz_bytes += 4; + if (buf_size == ADI_APOLLO_HAL_REGIO_HSCI_BUS_SIZE_D8) { + xfer_sz_bytes += 1; + } else if (buf_size == ADI_APOLLO_HAL_REGIO_HSCI_BUS_SIZE_D32) { + xfer_sz_bytes += 4; + } else if (buf_size == ADI_APOLLO_HAL_REGIO_HSCI_BUS_SIZE_D16) { + xfer_sz_bytes += 2; + } else { + return API_CMS_ERROR_HSCI_REGIO_XFER; + } + + /* read method takes precedence over xfer if both defined */ + if (desc->poll_read != NULL) { + err = desc->poll_read(desc->dev_obj, in_data, out_data, xfer_sz_bytes, timeout_us, ®_expect, ®_mask, &txn_cfgs[buf_size]); + ADI_APOLLO_ERROR_RETURN(err); + } + else + { + return API_CMS_ERROR_NULL_PARAM; + } + + *data = 0; + if (buf_size == ADI_APOLLO_HAL_REGIO_HSCI_BUS_SIZE_D8) { + *data |= out_data[4]; + } else if (buf_size == ADI_APOLLO_HAL_REGIO_HSCI_BUS_SIZE_D32) { + *data |= out_data[4] << 24; + *data |= out_data[5] << 16; + *data |= out_data[6] << 8; + *data |= out_data[7] << 0; + } else if (buf_size == ADI_APOLLO_HAL_REGIO_HSCI_BUS_SIZE_D16) { + *data |= out_data[4] << 8; + *data |= out_data[5] << 0; + } else { + return API_CMS_ERROR_HSCI_REGIO_XFER; + } + return err; +} + +static int32_t stream_write(adi_apollo_hal_regio_hsci_desc_t *desc, uint32_t reg, uint8_t *data, adi_apollo_hal_regio_hsci_bus_size_e bus_size, uint32_t stream_bytes, uint8_t is_cont) +{ + int32_t err; + uint32_t i; + uint32_t xfer_sz_bytes = 0; + + uint32_t in_data_len; + adi_apollo_hal_txn_config_t stream_txn_cfgs = {.addr_len = 4, .data_len = 1, .stream_len = stream_bytes}; /* Continuous 8-bit transaction */ + +#if defined(__KERNEL__) || defined(ADI_MIN_STACK_ALLOC) + uint8_t *in_data; + /* Take optional buffer in case it exists and size can, at least, transmit HSCI header */ + if (desc->buff != NULL) { + if (desc->buff_len > ADI_APOLLO_HAL_REGIO_HSCI_STREAM_HEADER_OVERHEAD) { + in_data_len = desc->buff_len - ADI_APOLLO_HAL_REGIO_HSCI_STREAM_HEADER_OVERHEAD; + in_data = desc->buff; + } else { + return API_CMS_ERROR_ERROR; // Chuck size not supported + } + } else { + return API_CMS_ERROR_NULL_PARAM; + } +#else + uint8_t in_data[ADI_APOLLO_HAL_REGIO_HSCI_STREAM_DEFAULT_SIZE]; + in_data_len = ADI_APOLLO_HAL_REGIO_HSCI_STREAM_DEFAULT_PAYLOAD_SIZE; +#endif + + if (stream_bytes > in_data_len) { + return API_CMS_ERROR_ERROR; // Chuck size not supported + } + + /* Assign 32-bit reg address */ + in_data[0] = (reg >> 0) & 0xFF; + in_data[1] = (reg >> 8) & 0xFF; + in_data[2] = (reg >> 16) & 0xFF; + in_data[3] = (reg >> 24) & 0xFF; + xfer_sz_bytes += ADI_APOLLO_HAL_REGIO_HSCI_STREAM_HEADER_OVERHEAD; + xfer_sz_bytes += stream_bytes; + + for (i=0; iwrite != NULL) { + err = desc->write(desc->dev_obj, in_data, xfer_sz_bytes, &stream_txn_cfgs); + ADI_APOLLO_ERROR_RETURN(err); + } + else if (desc->xfer != NULL) { + return API_CMS_ERROR_NOT_SUPPORTED; + } + else + { + return API_CMS_ERROR_NULL_PARAM; + } + + return err; +} + +static int32_t stream_read(adi_apollo_hal_regio_hsci_desc_t *desc, uint32_t reg, uint8_t *data, adi_apollo_hal_regio_hsci_bus_size_e bus_size, uint32_t stream_bytes, uint8_t is_cont) +{ + int32_t err; + uint32_t i; + uint32_t xfer_sz_bytes = 0; + uint8_t in_data[8] = {0}; + uint32_t out_data_len; + + adi_apollo_hal_txn_config_t stream_txn_cfgs = {.addr_len = 4, .data_len = 1, .stream_len = stream_bytes}; /* Continuous 8-bit transaction */ + +#if defined(__KERNEL__) || defined(ADI_MIN_STACK_ALLOC) + uint8_t *out_data; + /* Take optional buffer in case it exists and size can, at least, transmit HSCI header */ + if (desc->buff != NULL) { + if (desc->buff_len > ADI_APOLLO_HAL_REGIO_HSCI_STREAM_HEADER_OVERHEAD) { + out_data_len = desc->buff_len - ADI_APOLLO_HAL_REGIO_HSCI_STREAM_HEADER_OVERHEAD; + out_data = desc->buff; + } else { + return API_CMS_ERROR_ERROR; // Chuck size not supported + } + } else { + return API_CMS_ERROR_NULL_PARAM; + } +#else + uint8_t out_data[ADI_APOLLO_HAL_REGIO_HSCI_STREAM_DEFAULT_SIZE]; + out_data_len = ADI_APOLLO_HAL_REGIO_HSCI_STREAM_DEFAULT_PAYLOAD_SIZE; +#endif + + if (stream_bytes > out_data_len) { + return API_CMS_ERROR_ERROR; // Chuck size not supported + } + + /* Assign 32-bit reg address */ + in_data[0] = (reg >> 0) & 0xFF; + in_data[1] = (reg >> 8) & 0xFF; + in_data[2] = (reg >> 16) & 0xFF; + in_data[3] = (reg >> 24) & 0xFF; + xfer_sz_bytes += ADI_APOLLO_HAL_REGIO_HSCI_STREAM_HEADER_OVERHEAD; + xfer_sz_bytes += stream_bytes; + + /* read method takes precedence over xfer if both defined */ + if (desc->read != NULL) { + err = desc->read(desc->dev_obj, in_data, out_data, xfer_sz_bytes, &stream_txn_cfgs); + ADI_APOLLO_ERROR_RETURN(err); + } + else if (desc->xfer != NULL) { + return API_CMS_ERROR_NOT_SUPPORTED; + } + else + { + return API_CMS_ERROR_NULL_PARAM; + } + + for (i=0; imanual_linkup(desc->dev_obj, enable, link_up_signal_bits); + ADI_APOLLO_ERROR_RETURN(err); + + return err; +} + +static int32_t hsci_regio_auto_linkup(adi_apollo_hal_regio_hsci_desc_t *desc, uint8_t enable, uint8_t hscim_mosi_clk_inv, uint8_t hscim_miso_clk_inv) +{ + int32_t err; + + err = desc->auto_linkup(desc->dev_obj, enable, hscim_mosi_clk_inv, hscim_miso_clk_inv); + ADI_APOLLO_ERROR_RETURN(err); + + return err; +} + +static int32_t hsci_regio_alink_tbl_get(adi_apollo_hal_regio_hsci_desc_t *desc, uint16_t *hscim_alink_table) +{ + int32_t err; + + err = desc->alink_tbl_get(desc->dev_obj, hscim_alink_table); + ADI_APOLLO_ERROR_RETURN(err); + + return err; +} \ No newline at end of file diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_hal_regio_local.h b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_hal_regio_local.h new file mode 100644 index 00000000000000..8c03ad2046b590 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_hal_regio_local.h @@ -0,0 +1,88 @@ +/*! + * \brief Register IO local defines and prototypes + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +#ifndef __ADI_APOLLO_HAL_REGIO_LOCAL_H__ +#define __ADI_APOLLO_HAL_REGIO_LOCAL_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_hal_regio_spi_types.h" +#include "adi_apollo_hal_regio_hsci_types.h" + +/*============= D E F I N E S ==============*/ + +#define ADI_APOLLO_HAL_REGIO_NOMASK 0 +#define ADI_APOLLO_HAL_REGIO_NOT_PAGED 0 +#define ADI_APOLLO_HAL_REGIO_PAGED 1 + +typedef int32_t (*adi_apollo_hal_regio_wr_reg_t) (void *desc, uint32_t address, uint8_t data); +typedef int32_t (*adi_apollo_hal_regio_wr_reg32_t) (void *desc, uint32_t address, uint32_t data); +typedef int32_t (*adi_apollo_hal_regio_rd_reg_t) (void *desc, uint32_t address, uint8_t *data); +typedef int32_t (*adi_apollo_hal_regio_rd_reg32_t) (void *desc, uint32_t address, uint32_t *data); +typedef int32_t (*adi_apollo_hal_regio_wr_reg_rmw_t) (void *desc, uint32_t address, uint8_t data, uint8_t mask, uint8_t is_paged); +typedef int32_t (*adi_apollo_hal_regio_rd_reg_poll_t) (void *desc, uint32_t address, uint8_t *data, uint32_t timeout_us, uint8_t reg_expect, uint8_t reg_mask); +typedef int32_t (*adi_apollo_hal_regio_set_page_base_addr_t) (void *desc, uint32_t address); +typedef int32_t (*adi_apollo_hal_regio_wr_reg_paged_t) (void *desc, uint32_t address, uint8_t data); +typedef int32_t (*adi_apollo_hal_regio_wr_reg32_paged_t) (void *desc, uint32_t address, uint32_t data); +typedef int32_t (*adi_apollo_hal_regio_stream_wr_reg_t) (void *desc, uint32_t address, uint8_t *data, uint32_t data_len_bytes, uint8_t is_cont); +typedef int32_t (*adi_apollo_hal_regio_stream_wr_reg32_t) (void *desc, uint32_t address, uint32_t *data, uint32_t data_len_words, uint8_t is_cont); +typedef int32_t (*adi_apollo_hal_regio_stream_rd_reg_t) (void *desc, uint32_t address, uint8_t *data, uint32_t data_len_bytes, uint8_t is_cont); +typedef int32_t (*adi_apollo_hal_regio_stream_rd_reg32_t) (void *desc, uint32_t address, uint32_t *data, uint32_t data_len_words, uint8_t is_cont); +typedef int32_t (*adi_apollo_hal_regio_manual_linkup_t) (void *desc, uint8_t enable, uint16_t link_up_signal_bits); +typedef int32_t (*adi_apollo_hal_regio_auto_linkup_t) (void *desc, uint8_t enable, uint8_t hscim_mosi_clk_inv, uint8_t hscim_miso_clk_inv); +typedef int32_t (*adi_apollo_hal_regio_alink_tbl_get_t) (void *desc, uint16_t *hscim_alink_table); +typedef int32_t (*adi_apollo_hal_regio_rd_bf_t) (void *desc, uint32_t address, uint8_t *data, uint32_t data_len_bytes, uint64_t bf_mask); + +/*! + * \brief Functions that are implemented by all regio protocol types (e.g. spi, hsci) + */ +typedef struct { + adi_apollo_hal_regio_wr_reg_t wr_reg; + adi_apollo_hal_regio_wr_reg32_t wr_reg32; + adi_apollo_hal_regio_rd_reg_t rd_reg; + adi_apollo_hal_regio_rd_reg32_t rd_reg32; + adi_apollo_hal_regio_wr_reg_rmw_t wr_reg_rmw; + + adi_apollo_hal_regio_rd_reg_poll_t rd_reg_poll; + adi_apollo_hal_regio_rd_bf_t rd_bf; + + /* Paging ops (Apollo supports paging for writes only) */ + adi_apollo_hal_regio_set_page_base_addr_t set_page_base_addr; + adi_apollo_hal_regio_wr_reg_paged_t wr_reg_paged; + adi_apollo_hal_regio_wr_reg32_paged_t wr_reg32_paged; + + /* Streaming ops */ + adi_apollo_hal_regio_stream_wr_reg_t stream_wr_reg; + adi_apollo_hal_regio_stream_wr_reg32_t stream_wr_reg32; + adi_apollo_hal_regio_stream_rd_reg_t stream_rd_reg; + adi_apollo_hal_regio_stream_rd_reg32_t stream_rd_reg32; + + /* Manual linkup */ + adi_apollo_hal_regio_manual_linkup_t manual_linkup; + + /* Auto linkup */ + adi_apollo_hal_regio_auto_linkup_t auto_linkup; + adi_apollo_hal_regio_alink_tbl_get_t alink_tbl_get; +} adi_apollo_hal_regio_ops_t; + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +int32_t adi_apollo_l_hal_regio_spi_init(adi_apollo_hal_regio_spi_desc_t *desc, uint8_t is_spi1); +int32_t adi_apollo_l_hal_regio_hsci_init(adi_apollo_hal_regio_hsci_desc_t *desc); + +#ifndef CLIENT_IGNORE +#endif /* CLIENT_IGNORE*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_HAL_REGIO_LOCAL_H__ */ \ No newline at end of file diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_hal_regio_spi.c b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_hal_regio_spi.c new file mode 100644 index 00000000000000..a0112584de91af --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_hal_regio_spi.c @@ -0,0 +1,1194 @@ +/*! + * \brief HAL SPI function implementations + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +#include "adi_apollo_config.h" +#include "adi_apollo_bf_core.h" +#include "adi_apollo_hal_regio_local.h" +#include "adi_apollo_hal_regio_spi_types.h" + +#define FIFO_MODE_BYTE_CNT_EN_THRESH 1 /* Number of bytes where spi fifo mode enabled */ + +static int32_t spi_regio_write(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t reg, uint8_t data); +static int32_t spi_regio_write32(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t reg, uint32_t data); +static int32_t spi_regio_rmw_write(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t reg, uint8_t data, uint8_t mask, uint8_t is_paged); +static int32_t spi_regio_paged_base_addr_set(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t address); +static int32_t spi_regio_paged_write(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t address, uint8_t data); +static int32_t spi_regio_paged_write32(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t address, uint32_t data); +static int32_t spi_regio_read(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t reg, uint8_t *data); +static int32_t spi_regio_read32(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t reg, uint32_t *data); +static int32_t spi_regio_poll_read(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t reg, uint8_t *data, uint32_t timeout_us, uint8_t reg_expect, uint8_t reg_mask); +static int32_t spi_regio_stream_write(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t reg, uint8_t *data, uint32_t data_len_bytes, uint8_t is_cont); +static int32_t spi_regio_stream_write32(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t reg, uint32_t *data, uint32_t data_len_words, uint8_t is_cont); +static int32_t spi_regio_stream_read(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t reg, uint8_t *data, uint32_t data_len_bytes, uint8_t is_cont); +static int32_t spi_regio_stream_read32(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t reg, uint32_t *data, uint32_t data_len_words, uint8_t is_cont); +static int32_t indirect_poll_read(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t reg, uint32_t *data, adi_apollo_hal_regio_spi_bus_size_e bus_size, uint32_t timeout_us, uint8_t reg_expect, uint8_t reg_mask); +static int32_t alt_spi_regio_poll_read(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t reg, uint8_t *data, uint32_t timeout_us, uint8_t reg_expect, uint8_t reg_mask); +static int32_t spi_regio_read_bf(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t reg, uint8_t *data, uint32_t data_len_bytes, uint64_t bf_mask); +static int32_t spi_regio_read_bf_direct(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t reg, uint8_t *data, uint32_t data_len_bytes, uint64_t mask); +static int32_t spi_regio_read_bf_indirect(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t reg, uint8_t *data, uint32_t data_len_bytes, uint64_t mask); +static int32_t indirect_readx(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t reg, uint32_t *data, adi_apollo_hal_regio_spi_bus_size_e bus_size); +static int32_t indirect_writex(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t reg, uint32_t data, adi_apollo_hal_regio_spi_bus_size_e bus_size); +static int32_t stream_readx(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t reg, uint8_t *data, adi_apollo_hal_regio_spi_bus_size_e bus_size, uint32_t stream_bytes, uint8_t is_cont); +static int32_t stream_writex(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t reg, uint8_t *data, adi_apollo_hal_regio_spi_bus_size_e bus_size, uint32_t stream_bytes, uint8_t is_cont); + +/* SPI implementations of regio operations */ +static adi_apollo_hal_regio_ops_t spi_regio_ops = { + .wr_reg = (adi_apollo_hal_regio_wr_reg_t) &spi_regio_write, + .wr_reg32 = (adi_apollo_hal_regio_wr_reg32_t) &spi_regio_write32, + .wr_reg_rmw = (adi_apollo_hal_regio_wr_reg_rmw_t) &spi_regio_rmw_write, + .wr_reg_paged = (adi_apollo_hal_regio_wr_reg_paged_t) &spi_regio_paged_write, + .wr_reg32_paged = (adi_apollo_hal_regio_wr_reg32_paged_t) &spi_regio_paged_write32, + .rd_reg = (adi_apollo_hal_regio_rd_reg_t) &spi_regio_read, + .rd_reg32 = (adi_apollo_hal_regio_rd_reg32_t) &spi_regio_read32, + .rd_reg_poll = (adi_apollo_hal_regio_rd_reg_poll_t) &spi_regio_poll_read, + .set_page_base_addr = (adi_apollo_hal_regio_set_page_base_addr_t) &spi_regio_paged_base_addr_set, + .stream_wr_reg = (adi_apollo_hal_regio_stream_wr_reg_t) &spi_regio_stream_write, + .stream_wr_reg32 = (adi_apollo_hal_regio_stream_wr_reg32_t) &spi_regio_stream_write32, + .stream_rd_reg = (adi_apollo_hal_regio_stream_rd_reg_t) &spi_regio_stream_read, + .stream_rd_reg32 = (adi_apollo_hal_regio_stream_rd_reg32_t) &spi_regio_stream_read32, + .rd_bf = (adi_apollo_hal_regio_rd_bf_t) &spi_regio_read_bf +}; + +/* Predefined default transaction configs. */ +static adi_apollo_hal_txn_config_t default_txn_cfgs[] = { + {.addr_len = 2, .data_len = 1, .stream_len = 1, .mask = 0x000000ffull, .is_bf_txn = 0}, /* Single 8-bit transaction */ + {.addr_len = 2, .data_len = 2, .stream_len = 1, .mask = 0x0000ffffull, .is_bf_txn = 0}, /* Single 16-bit transaction */ + {.addr_len = 2, .data_len = 4, .stream_len = 1, .mask = 0xffffffffull, .is_bf_txn = 0}, /* Single 32-bit transaction */ +}; + +static int32_t direct_or_paged_write(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t reg, uint32_t data, adi_apollo_hal_regio_spi_bus_size_e bus_size, uint32_t mask, uint8_t is_paged); +static int32_t indirect_write(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t reg, uint32_t data, adi_apollo_hal_regio_spi_bus_size_e bus_size); +static int32_t direct_read(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t reg, uint32_t *data, adi_apollo_hal_regio_spi_bus_size_e bus_size); +static int32_t indirect_read(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t reg, uint32_t *data, adi_apollo_hal_regio_spi_bus_size_e bus_size); +static int32_t mask_reg_set(adi_apollo_hal_regio_spi_desc_t *desc, adi_apollo_hal_regio_spi_bus_size_e bus_size, uint32_t mask); +static int32_t indirect_addr_set(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t reg, uint8_t dma_ctrl); +static int32_t direct_poll_read(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t reg, uint32_t *data, adi_apollo_hal_regio_spi_bus_size_e bus_size, uint32_t timeout_us, uint8_t reg_expect, uint8_t reg_mask); +static int32_t stream_write(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t reg, uint8_t *data, adi_apollo_hal_regio_spi_bus_size_e bus_size, uint32_t stream_bytes, uint8_t is_cont); +static int32_t stream_read(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t reg, uint8_t *data, adi_apollo_hal_regio_spi_bus_size_e bus_size, uint32_t stream_bytes, uint8_t is_cont); +static int32_t set_spi_fifo_mode(adi_apollo_hal_regio_spi_desc_t *desc, uint8_t is_fifo_enabled, adi_apollo_hal_regio_spi_bus_size_e bus_size); +static int32_t align_page_base_address(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t reg, adi_apollo_hal_regio_spi_bus_size_e size, uint32_t *reg_offset_p); +static int32_t txn_config_set(adi_apollo_hal_regio_spi_desc_t *desc, uint8_t addr_siz_bytes, uint8_t data_siz_bytes, uint8_t stream_len, uint64_t mask, uint8_t is_bf_txn); +static int32_t txn_config_default_set(adi_apollo_hal_regio_spi_desc_t *desc, adi_apollo_hal_regio_spi_bus_size_e spi_bus_size); +static int32_t spi_write_stream_fifo_mode(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t reg, uint8_t *data, uint32_t data_len_bytes, uint64_t mask, uint8_t is_bf); + +/* Default poll read if not defined */ +static int32_t alt_spi_regio_poll_read(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t reg, uint8_t *data, uint32_t timeout_us, uint8_t reg_expect, uint8_t reg_mask) +{ + return spi_regio_read(desc, reg, data); +} + +int32_t adi_apollo_l_hal_regio_spi_init(adi_apollo_hal_regio_spi_desc_t *desc, uint8_t is_spi1) +{ + if (desc == NULL) { + return API_CMS_ERROR_NULL_PARAM; + } + + desc->base_regio.ops = &spi_regio_ops; // interface + desc->base_regio.child_desc = desc; // instance (child) + desc->base_regio.protocol_id = is_spi1 ? ADI_APOLLO_HAL_PROTOCOL_SPI1 : ADI_APOLLO_HAL_PROTOCOL_SPI0; + desc->is_spi1 = is_spi1; + desc->base_addr_cache.enabled = 0; + desc->base_addr_cache.valid = 0; + desc->indir_cache.enabled = 0; + desc->indir_cache.valid = 0; + + /* If the user didn't specify an optional poll read hal for SPI0, use the built in alternate */ + if (!is_spi1 && desc->poll_read == NULL) { + spi_regio_ops.rd_reg_poll = (adi_apollo_hal_regio_rd_reg_poll_t) &alt_spi_regio_poll_read; + desc->base_regio.poll_read_returns_val = 1; + } + desc->base_regio.poll_read_en = (desc->poll_read != NULL); + + return API_CMS_ERROR_OK; +} + +/* 8-bit register write */ +static int32_t spi_regio_write(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t reg, uint8_t data) +{ + int32_t err; + + if ((reg >> 24) == 0x47) { + /* spi direct */ + err = direct_or_paged_write(desc, reg, data, ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D8, ADI_APOLLO_HAL_REGIO_NOMASK, ADI_APOLLO_HAL_REGIO_NOT_PAGED); + } else { + /* spi indirect */ + err = indirect_write(desc, reg, data, ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D8); + } + + return (err == API_CMS_ERROR_OK) ? API_CMS_ERROR_OK : API_CMS_ERROR_SPI_REGIO_XFER; +} + +/* 32-bit register write */ +static int32_t spi_regio_write32(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t reg, uint32_t data) +{ + int32_t err; + + if ((reg >> 24) == 0x47) { + /* spi direct */ + err = direct_or_paged_write(desc, reg, data, ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D32, ADI_APOLLO_HAL_REGIO_NOMASK, ADI_APOLLO_HAL_REGIO_NOT_PAGED); + } else { + /* spi indirect */ + err = indirect_write(desc, reg, data, ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D32); + } + + return (err == API_CMS_ERROR_OK) ? API_CMS_ERROR_OK : API_CMS_ERROR_SPI_REGIO_XFER; +} + +/* 8-bit read-modify-write */ +static int32_t spi_regio_rmw_write(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t reg, uint8_t data, uint8_t mask, uint8_t is_paged) +{ + int32_t err = API_CMS_ERROR_OK; + uint32_t reg_offset = reg; + + if ((reg >> 24) == 0x47 && !is_paged) { + reg_offset = reg; + } else if (is_paged) { + err = align_page_base_address(desc, reg, ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D8, ®_offset); + } else { + /* spi indirect doesn't support masked writes */ + return API_CMS_ERROR_SPI_REGIO_XFER; + } + + if (err == API_CMS_ERROR_OK) { + err = direct_or_paged_write(desc, reg_offset, data, ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D8, mask, is_paged); + } + + return (err == API_CMS_ERROR_OK) ? API_CMS_ERROR_OK : API_CMS_ERROR_SPI_REGIO_XFER; +} + +static int32_t spi_regio_paged_base_addr_set(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t reg) +{ + int32_t err; + uint32_t reg_word_aligned = reg & ~0x03ul; /* Page address must be on 32-bit boundary */ + + // Program the spi paged base address + uint32_t spi_page_base_reg = desc->is_spi1 ? REG_SPI1_PAGE_ADDRESS_31TO24_ADDR : REG_SPI0_BASE_PAGE_ADDRESS_31TO24_ADDR; + + // Cache of the base addr bytes for further optimisation. + // If this is the first time we're communicating with the device, we don't know the + // value of the page_base_addr register. It seems to be 0s but we cannot trust that. Thus, + // we make the cache valid the first time we write a known value. + + if (!desc->base_addr_cache.enabled || !desc->base_addr_cache.valid) + { + // Byte-level caching is either disabled or invalid; update the entire register in h/w + err = spi_regio_write(desc, spi_page_base_reg + 0, (uint8_t)(reg_word_aligned >> 24)); + ADI_APOLLO_ERROR_RETURN(err); + + err = spi_regio_write(desc, spi_page_base_reg + 1, (uint8_t)(reg_word_aligned >> 16)); + ADI_APOLLO_ERROR_RETURN(err); + + err = spi_regio_write(desc, spi_page_base_reg + 2, (uint8_t)(reg_word_aligned >> 8)); + ADI_APOLLO_ERROR_RETURN(err); + + err = spi_regio_write(desc, spi_page_base_reg + 3, (uint8_t)(reg_word_aligned >> 0)); + ADI_APOLLO_ERROR_RETURN(err); + + // Update ADI's own word-level cache variable + desc->page_base_addr = reg_word_aligned; + + // Now we can mark our cache as valid + desc->base_addr_cache.valid = 1; + return API_CMS_ERROR_OK; + } else { + // Byte-level caching is enabled; contents are valid. + // Only update the bytes that have changed. + + if ((desc->page_base_addr & 0xFF000000) != (reg_word_aligned & 0xFF000000)) { + err = spi_regio_write(desc, spi_page_base_reg + 0, (uint8_t)(reg_word_aligned >> 24)); + ADI_APOLLO_ERROR_RETURN(err); + } + + if ((desc->page_base_addr & 0x00FF0000) != (reg_word_aligned & 0x00FF0000)) { + err = spi_regio_write(desc, spi_page_base_reg + 1, (uint8_t)(reg_word_aligned >> 16)); + ADI_APOLLO_ERROR_RETURN(err); + } + + if ((desc->page_base_addr & 0x0000FF00) != (reg_word_aligned & 0x0000FF00)) { + err = spi_regio_write(desc, spi_page_base_reg + 2, (uint8_t)(reg_word_aligned >> 8)); + ADI_APOLLO_ERROR_RETURN(err); + } + + if ((desc->page_base_addr & 0x000000FF) != (reg_word_aligned & 0x000000FF)) { + err = spi_regio_write(desc, spi_page_base_reg + 3, (uint8_t)(reg_word_aligned >> 0)); + ADI_APOLLO_ERROR_RETURN(err); + } + + // Also update word-level cache variable + desc->page_base_addr = reg_word_aligned; + } + + return API_CMS_ERROR_OK; +} + +/* 8-bit paged write */ +static int32_t spi_regio_paged_write(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t reg, uint8_t data) +{ + int32_t err; + uint32_t reg_offset; + + /* spi paged write - base addr is on 32-bit boundary. Offsets can be 0 to 0x3fff */ + err = align_page_base_address(desc, reg, ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D8, ®_offset); + if (err != API_CMS_ERROR_OK) { + return err; + } + + err = direct_or_paged_write(desc, reg_offset, data, ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D8, ADI_APOLLO_HAL_REGIO_NOMASK, ADI_APOLLO_HAL_REGIO_PAGED); + + return (err == API_CMS_ERROR_OK) ? API_CMS_ERROR_OK : API_CMS_ERROR_SPI_REGIO_XFER; +} + +/* 32-bit paged write */ +static int32_t spi_regio_paged_write32(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t reg, uint32_t data) +{ + int32_t err; + uint32_t reg_offset; + + /* spi paged write - base addr is on 32-bit boundary. Offsets can be 0 to 0x3fff */ + err = align_page_base_address(desc, reg, ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D32, ®_offset); + if (err != API_CMS_ERROR_OK) { + return err; + } + + /* spi paged write 32 */ + err = direct_or_paged_write(desc, reg_offset, data, ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D32, ADI_APOLLO_HAL_REGIO_NOMASK, ADI_APOLLO_HAL_REGIO_PAGED); + + return (err == API_CMS_ERROR_OK) ? API_CMS_ERROR_OK : API_CMS_ERROR_SPI_REGIO_XFER; +} + +/* 8-bit register read */ +static int32_t spi_regio_read(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t reg, uint8_t *data) +{ + int32_t err; + uint32_t rd_val; + + if ((reg >> 24) == 0x47) { + /* spi direct */ + err = direct_read(desc, reg, &rd_val, ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D8); + } else { + /* spi indirect */ + err = indirect_read(desc, reg, &rd_val, ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D8); + } + + *data = (uint8_t) rd_val; + + return (err == API_CMS_ERROR_OK) ? API_CMS_ERROR_OK : API_CMS_ERROR_SPI_REGIO_XFER; +} + +/* 32-bit register read */ +static int32_t spi_regio_read32(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t reg, uint32_t *data) +{ + int32_t err; + + if ((reg >> 24) == 0x47) { + /* spi direct */ + err = direct_read(desc, reg, data, ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D32); + } else { + /* spi indirect */ + err = indirect_read(desc, reg, data, ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D32); + } + + return (err == API_CMS_ERROR_OK) ? API_CMS_ERROR_OK : API_CMS_ERROR_SPI_REGIO_XFER; +} + +static int32_t spi_regio_read_bf(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t reg, uint8_t *data, uint32_t data_len_bytes, uint64_t mask) +{ + int32_t err = API_CMS_ERROR_OK; + + if ((reg >> 24) == 0x47) { + /* spi direct */ + err = spi_regio_read_bf_direct(desc, reg, data, data_len_bytes, mask); + } else { + /* spi indirect */ + err = spi_regio_read_bf_indirect(desc, reg, data, data_len_bytes, mask); + } + + return err; +} + +static int32_t spi_regio_read_bf_direct(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t reg, uint8_t *data, uint32_t data_len_bytes, uint64_t mask) +{ + int32_t i, err; + + uint8_t in_data[16] = { 0 }; + uint8_t out_data[16] = { 0 }; + uint8_t xfer_sz_bytes; + + /* Set txn config info for bitfield */ + txn_config_set(desc, 2, 1, data_len_bytes, mask, 1); /* 2 addr, 1 data, data_len_bytes */ + + /* Direct address (from 0x470000000) */ + in_data[0] = ((reg >> 8) & 0x3F) | 0x80; + in_data[1] = (reg >> 0) & 0xFF; + + for (i = 0; i < data_len_bytes; i++) { + in_data[2 + i] = data[i]; + } + xfer_sz_bytes = 2 + data_len_bytes; + + err = desc->read(desc->dev_obj, in_data, out_data, xfer_sz_bytes, &desc->txn_config); + + for (i = 0; i < data_len_bytes; i++) { + data[i] = out_data[i + 2]; + } + + return (err == API_CMS_ERROR_OK) ? API_CMS_ERROR_OK : API_CMS_ERROR_SPI_REGIO_XFER; +} + + +static int32_t spi_regio_read_bf_indirect(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t reg, uint8_t *data, uint32_t data_len_bytes, uint64_t mask) +{ + int32_t dma_dat0, i, err; + + uint8_t spidma_ahb_bus_select = 0; + uint8_t spidma_auto_incr = 1; + uint8_t spidma_bus_size = ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D8; // Size of read/write. 0 = byte, 1 = half-word, 2 = full-word, 3 = invalid. + uint8_t spidma_sys_codeb = 0; + uint8_t spidma_rd_wrb = 1; + uint8_t spidma_ctl_data = (spidma_rd_wrb << 7) | (spidma_sys_codeb << 6) | (spidma_bus_size << 2) | (spidma_auto_incr << 1) | (spidma_ahb_bus_select << 0); + uint8_t in_data[16] = { 0 }; + uint8_t out_data[16] = { 0 }; + uint8_t xfer_sz_bytes; + + indirect_addr_set(desc, reg, spidma_ctl_data); + + /* FIFO mode is efficient if #bytes > 4 */ + if (data_len_bytes > FIFO_MODE_BYTE_CNT_EN_THRESH) { + set_spi_fifo_mode(desc, 1, ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D8); + } + + /* Set txn config info for bitfield */ + txn_config_set(desc, 2, 1, data_len_bytes, mask, 1); /* 2 addr, 1 data, data_len_bytes */ + + /* Set SPI address to spi dma lsb. Using auto increment mode */ + dma_dat0 = desc->is_spi1 ? REG_SPIDMA1_DATA0_ADDR : REG_SPIDMA0_DATA0_ADDR; + in_data[0] = ((dma_dat0 >> 8) & 0x3F) | 0x80; + in_data[1] = (dma_dat0 >> 0) & 0xFF; + + for (i = 0; i < data_len_bytes; i++) { + in_data[2 + i] = data[i]; + } + xfer_sz_bytes = 2 + data_len_bytes; + err = desc->read(desc->dev_obj, in_data, out_data, xfer_sz_bytes, &desc->txn_config); + + for (i = 0; i < data_len_bytes; i++) { + data[i] = out_data[i + 2]; + } + + /* Reset txn spi fifo mode */ + if (data_len_bytes > FIFO_MODE_BYTE_CNT_EN_THRESH) { + set_spi_fifo_mode(desc, 0, ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D8); + } + + return (err == API_CMS_ERROR_OK) ? API_CMS_ERROR_OK : API_CMS_ERROR_SPI_REGIO_XFER; +} + +/* 8 bit stream write */ +static int32_t spi_regio_stream_write(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t reg, uint8_t *data, uint32_t data_len_bytes, uint8_t is_cont) +{ + int32_t err; + if (desc->wr_stream_en) { + err = stream_write(desc, reg, data, ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D8, data_len_bytes, is_cont); + } else { + err = stream_writex(desc, reg, data, ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D8, data_len_bytes, is_cont); + } + + return (err == API_CMS_ERROR_OK) ? API_CMS_ERROR_OK : API_CMS_ERROR_SPI_REGIO_XFER; +} + +/* 32 bit stream write */ +static int32_t spi_regio_stream_write32(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t reg, uint32_t *data, uint32_t data_len_words, uint8_t is_cont) +{ + int32_t err; + + if (desc->wr_stream_en) { + err = stream_write(desc, reg, (uint8_t *)data, ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D32, data_len_words * 4, is_cont); + } else { + err = stream_writex(desc, reg, (uint8_t *)data, ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D32, data_len_words * 4, is_cont); + } + + return (err == API_CMS_ERROR_OK) ? API_CMS_ERROR_OK : API_CMS_ERROR_SPI_REGIO_XFER; +} + +/* 8 bit stream read */ +static int32_t spi_regio_stream_read(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t reg, uint8_t *data, uint32_t data_len_bytes, uint8_t is_cont) +{ + int32_t err; + if (desc->rd_stream_en) { + err = stream_read(desc, reg, data, ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D8, data_len_bytes, is_cont); + } else { + err = stream_readx(desc, reg, data, ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D8, data_len_bytes, is_cont); + } + return (err == API_CMS_ERROR_OK) ? API_CMS_ERROR_OK : API_CMS_ERROR_SPI_REGIO_XFER; +} + +/* 32 bit stream read */ +static int32_t spi_regio_stream_read32(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t reg, uint32_t *data, uint32_t data_len_words, uint8_t is_cont) +{ + int32_t err; + if (desc->rd_stream_en) { + err = stream_read(desc, reg, (uint8_t *)data, ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D32, data_len_words * 4, is_cont); + } else { + err = stream_readx(desc, reg, (uint8_t *)data, ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D32, data_len_words * 4, is_cont); + } + + return (err == API_CMS_ERROR_OK) ? API_CMS_ERROR_OK : API_CMS_ERROR_SPI_REGIO_XFER; +} + +static int32_t indirect_poll_read(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t reg, uint32_t *data, adi_apollo_hal_regio_spi_bus_size_e bus_size, uint32_t timeout_us, uint8_t reg_expect, uint8_t reg_mask) +{ + int32_t err; + uint8_t spidma_ahb_bus_select = 0; + uint8_t spidma_auto_incr = 0; + uint8_t spidma_bus_size = bus_size; // Size of read/write. 0 = byte, 1 = half-word, 2 = full-word, 3 = invalid. + uint8_t spidma_sys_codeb = 0; + uint8_t spidma_rd_wrb = 1; + uint8_t spidma_ctl_data = (spidma_rd_wrb << 7) | (spidma_sys_codeb << 6) | (spidma_bus_size << 2) | (spidma_auto_incr << 1) | (spidma_ahb_bus_select << 0); + uint8_t in_data[10] = {0}; + uint8_t out_data[10] = {0}; + uint8_t xfer_sz_bytes; + + /* Set the dma ctl and address */ + err = indirect_addr_set(desc, reg, spidma_ctl_data); + ADI_APOLLO_ERROR_RETURN(err); + + /* in_data: [DMA address last 8 bits] [reg address] */ + in_data[0] = REG_SPIDMA0_ADDR3_ADDR & 0xFFU; + in_data[1] = REG_SPIDMA0_ADDR2_ADDR & 0xFFU; + in_data[2] = REG_SPIDMA0_ADDR1_ADDR & 0xFFU; + in_data[3] = REG_SPIDMA0_ADDR0_ADDR & 0xFFU; + + in_data[4] = (reg >> 24) & 0xFFU; + in_data[5] = (reg >> 16) & 0xFFU; + in_data[6] = (reg >> 8) & 0xFFU; + in_data[7] = (reg >> 0) & 0xFFU; + + xfer_sz_bytes = 8; + + if (bus_size == ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D8) { + xfer_sz_bytes += 1; + } else if (bus_size == ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D32) { + xfer_sz_bytes += 4; + } else if (bus_size == ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D16) { + xfer_sz_bytes += 2; + } else { + return API_CMS_ERROR_SPI_REGIO_XFER; + } + + // platform driver with ATE mods - needs work + err = desc->poll_read(desc->dev_obj, in_data, out_data, xfer_sz_bytes, timeout_us, ®_expect, ®_mask, &default_txn_cfgs[bus_size]); + ADI_APOLLO_ERROR_RETURN(err); + + *data = 0; + if (bus_size == ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D8) { + *data |= out_data[2]; + } else if (bus_size == ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D32) { + *data |= out_data[2] << 0; + *data |= out_data[3] << 8; + *data |= out_data[4] << 16; + *data |= out_data[5] << 24; + } else if (bus_size == ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D16) { + *data |= out_data[2] << 0; + *data |= out_data[3] << 8; + } else { + return API_CMS_ERROR_SPI_REGIO_XFER; + } + + return API_CMS_ERROR_OK; +} + +/* 8-bit register polled read */ +static int32_t spi_regio_poll_read(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t reg, uint8_t *data, uint32_t timeout_us, uint8_t reg_expect, uint8_t reg_mask) +{ + int32_t err; + uint32_t rd_val; + + if ((reg >> 24) == 0x47) { + /* spi direct */ + err = direct_poll_read(desc, reg, &rd_val, ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D8, timeout_us, reg_expect, reg_mask); + } else { + /* spi indirect */ + err = indirect_poll_read(desc, reg, &rd_val, ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D8, timeout_us, reg_expect, reg_mask); + } + + *data = (uint8_t) rd_val; + + return (err == API_CMS_ERROR_OK) ? API_CMS_ERROR_OK : API_CMS_ERROR_SPI_REGIO_XFER; +} + +static int32_t direct_or_paged_write(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t reg, uint32_t data, adi_apollo_hal_regio_spi_bus_size_e bus_size, uint32_t mask, uint8_t is_paged) +{ + int32_t err; + uint8_t in_data[6] = {0}; + uint8_t out_data[6] = {0}; + uint8_t xfer_sz_bytes; + + if (desc->base_regio.rmw_enabled && (mask != ADI_APOLLO_HAL_REGIO_NOMASK)) + { + err = mask_reg_set(desc, bus_size, mask); /* sets mask reg if necessary */ + } + + /* Direct address (from 0x470000000) */ + in_data[0] = ((reg >> 8) & 0x3F) | (is_paged ? 0x40 : 0); + in_data[1] = (reg >> 0) & 0xFF; + if (bus_size == ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D8) { + in_data[2] = (uint8_t)(data >> 0); + xfer_sz_bytes = 3; + } else if (bus_size == ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D32) { + in_data[2] = (uint8_t)(data >> 0); + in_data[3] = (uint8_t)(data >> 8); + in_data[4] = (uint8_t)(data >> 16); + in_data[5] = (uint8_t)(data >> 24); + xfer_sz_bytes = 6; + } else if (bus_size == ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D16) { + in_data[2] = (uint8_t)(data >> 0); + in_data[3] = (uint8_t)(data >> 8); + xfer_sz_bytes = 4; + } else { + return -1; + } + + /* write method takes precedence over xfer if both defined */ + if (desc->write != NULL) { + err = desc->write(desc->dev_obj, in_data, xfer_sz_bytes, &default_txn_cfgs[bus_size]); + ADI_APOLLO_ERROR_RETURN(err); + } else { + err = desc->xfer(desc->dev_obj, in_data, out_data, xfer_sz_bytes); + ADI_APOLLO_ERROR_RETURN(err); + } + + return err; +} + +static int32_t indirect_write(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t reg, uint32_t data, adi_apollo_hal_regio_spi_bus_size_e bus_size) +{ + if (desc->wr_stream_en) + { + return stream_write(desc, reg, (uint8_t *) &data, bus_size, (1 << bus_size), 0); + } else { + return indirect_writex(desc, reg, data, bus_size); + } +} + +static int32_t mask_reg_set(adi_apollo_hal_regio_spi_desc_t *desc, adi_apollo_hal_regio_spi_bus_size_e bus_size, uint32_t mask) +{ + int32_t err; + + if (bus_size == ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D32) { + if (mask == 0xffffffff) { + return API_CMS_ERROR_OK; + } + err = spi_regio_write(desc, desc->is_spi1 ? REG_SPI1_MASK_31TO24_ADDR : REG_SPI0_MASK_31TO24_ADDR, (mask >> 24) & 0xFF); + ADI_APOLLO_ERROR_RETURN(err); + err = spi_regio_write(desc, desc->is_spi1 ? REG_SPI1_MASK_23TO16_ADDR : REG_SPI0_MASK_23TO16_ADDR, (mask >> 16) & 0xFF); + ADI_APOLLO_ERROR_RETURN(err); + } + + if ((bus_size == ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D32) || (bus_size == ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D16)) { + if ((mask & 0xffff) == 0xffff) { + return API_CMS_ERROR_OK; + } + err = spi_regio_write(desc, desc->is_spi1 ? REG_SPI1_MASK_15TO8_ADDR : REG_SPI0_MASK_15TO8_ADDR, (mask >> 8) & 0xFF); + ADI_APOLLO_ERROR_RETURN(err); + } + + if ((mask & 0xff) != 0xff) { + err = spi_regio_write(desc, desc->is_spi1 ? REG_SPI1_MASK_7TO0_ADDR : REG_SPI0_MASK_7TO0_ADDR, (mask >> 0) & 0xFF); + ADI_APOLLO_ERROR_RETURN(err); + } + + + return API_CMS_ERROR_OK; +} + +static int32_t direct_read(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t reg, uint32_t *data, adi_apollo_hal_regio_spi_bus_size_e bus_size) +{ + int32_t err; + uint8_t in_data[6] = {0}; + uint8_t out_data[6] = {0}; + uint8_t xfer_sz_bytes; + + // ADI_APOLLO_NULL_POINTER_RETURN(desc); + + /* Direct address (from 0x470000000) */ + in_data[0] = ((reg >> 8) & 0x3F) | 0x80; + in_data[1] = (reg >> 0) & 0xFF; + + if (bus_size == ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D8) { + xfer_sz_bytes = 3; + } else if (bus_size == ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D32) { + xfer_sz_bytes = 6; + } else if (bus_size == ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D16) { + xfer_sz_bytes = 4; + } else { + return -1; + } + + /* read method takes precedence over xfer if both defined */ + if (desc->read != NULL) { + err = desc->read(desc->dev_obj, in_data, out_data, xfer_sz_bytes, &default_txn_cfgs[bus_size]); + ADI_APOLLO_ERROR_RETURN(err); + } else { + err = desc->xfer(desc->dev_obj, in_data, out_data, xfer_sz_bytes); + ADI_APOLLO_ERROR_RETURN(err); + } + + *data = 0; + if (bus_size == ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D8) { + *data |= out_data[2]; + } else if (bus_size == ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D32) { + *data |= out_data[2] << 0; + *data |= out_data[3] << 8; + *data |= out_data[4] << 16; + *data |= out_data[5] << 24; + } else if (bus_size == ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D16) { + *data |= out_data[2] << 0; + *data |= out_data[3] << 8; + } else { + return API_CMS_ERROR_SPI_REGIO_XFER; + } + + return API_CMS_ERROR_OK; +} + +static int32_t indirect_read(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t reg, uint32_t *data, adi_apollo_hal_regio_spi_bus_size_e bus_size) +{ + if (desc->rd_stream_en) { + return stream_read(desc, reg, (uint8_t *)data, bus_size, (1 << bus_size), 0); + } else { + return indirect_readx(desc, reg, data, bus_size); + } +} + +static int32_t direct_poll_read(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t reg, uint32_t *data, adi_apollo_hal_regio_spi_bus_size_e bus_size, uint32_t timeout_us, uint8_t reg_expect, uint8_t reg_mask) +{ + int32_t err; + uint8_t in_data[6] = {0}; + uint8_t out_data[6] = {0}; + uint8_t xfer_sz_bytes; + + /* Direct address (from 0x470000000) */ + in_data[0] = ((reg >> 8) & 0x3F) | 0x80; + in_data[1] = (reg >> 0) & 0xFF; + + if (bus_size == ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D8) { + xfer_sz_bytes = 3; + } else if (bus_size == ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D32) { + xfer_sz_bytes = 6; + } else if (bus_size == ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D16) { + xfer_sz_bytes = 4; + } else { + return API_CMS_ERROR_SPI_REGIO_XFER; + } + + err = desc->poll_read(desc->dev_obj, in_data, out_data, xfer_sz_bytes, timeout_us, ®_expect, ®_mask, &default_txn_cfgs[bus_size]); + ADI_APOLLO_ERROR_RETURN(err); + + *data = 0; + if (bus_size == ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D8) { + *data |= out_data[2]; + } else if (bus_size == ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D32) { + *data |= out_data[2] << 0; + *data |= out_data[3] << 8; + *data |= out_data[4] << 16; + *data |= out_data[5] << 24; + } else if (bus_size == ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D16) { + *data |= out_data[2] << 0; + *data |= out_data[3] << 8; + } else { + return API_CMS_ERROR_SPI_REGIO_XFER; + } + + return API_CMS_ERROR_OK; +} + +static int32_t indirect_addr_set(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t reg, uint8_t dma_ctrl) +{ + int32_t err; + + if (!desc->indir_cache.enabled || !desc->indir_cache.valid) + { + // The cache is invalid or is not enabled; Write all addr + // bytes to the device. + err = spi_regio_write(desc, + desc->is_spi1 ? REG_SPIDMA1_CTL_ADDR + : REG_SPIDMA0_CTL_ADDR, + dma_ctrl); + ADI_APOLLO_ERROR_RETURN(err); + desc->indir_cache.dma_ctrl = dma_ctrl; + + err = spi_regio_write(desc, + desc->is_spi1 ? REG_SPIDMA1_ADDR3_ADDR + : REG_SPIDMA0_ADDR3_ADDR, + (reg >> 24) & 0xFF); + ADI_APOLLO_ERROR_RETURN(err); + desc->indir_cache.addr3 = (reg >> 24) & 0xFF; + + err = spi_regio_write(desc, + desc->is_spi1 ? REG_SPIDMA1_ADDR2_ADDR + : REG_SPIDMA0_ADDR2_ADDR, + (reg >> 16) & 0xFF); + ADI_APOLLO_ERROR_RETURN(err); + desc->indir_cache.addr2 = (reg >> 16) & 0xFF; + + err = spi_regio_write(desc, + desc->is_spi1 ? REG_SPIDMA1_ADDR1_ADDR + : REG_SPIDMA0_ADDR1_ADDR, + (reg >> 8) & 0xFF); + ADI_APOLLO_ERROR_RETURN(err); + desc->indir_cache.addr1 = (reg >> 8) & 0xFF; + + err = spi_regio_write(desc, + desc->is_spi1 ? REG_SPIDMA1_ADDR0_ADDR + : REG_SPIDMA0_ADDR0_ADDR, + (reg >> 0) & 0xFF); + ADI_APOLLO_ERROR_RETURN(err); + + // Mark cache as valid + desc->indir_cache.valid = 1; + } else { + // Cache is valid and enabled. Only write the addr bytes + // which are different to the cached addr to the device. + if (desc->indir_cache.dma_ctrl != dma_ctrl) { + err = spi_regio_write(desc, + desc->is_spi1 ? REG_SPIDMA1_CTL_ADDR + : REG_SPIDMA0_CTL_ADDR, + dma_ctrl); + ADI_APOLLO_ERROR_RETURN(err); + desc->indir_cache.dma_ctrl = dma_ctrl; + } + + if (desc->indir_cache.addr3 != ((reg >> 24) & 0xFF)) { + err = spi_regio_write(desc, + desc->is_spi1 ? REG_SPIDMA1_ADDR3_ADDR + : REG_SPIDMA0_ADDR3_ADDR, + (reg >> 24) & 0xFF); + ADI_APOLLO_ERROR_RETURN(err); + desc->indir_cache.addr3 = (reg >> 24) & 0xFF; + } + + if (desc->indir_cache.addr2 != ((reg >> 16) & 0xFF)) { + err = spi_regio_write(desc, + desc->is_spi1 ? REG_SPIDMA1_ADDR2_ADDR + : REG_SPIDMA0_ADDR2_ADDR, + (reg >> 16) & 0xFF); + ADI_APOLLO_ERROR_RETURN(err); + desc->indir_cache.addr2 = (reg >> 16) & 0xFF; + } + + if (desc->indir_cache.addr1 != ((reg >> 8) & 0xFF)) { + err = spi_regio_write(desc, + desc->is_spi1 ? REG_SPIDMA1_ADDR1_ADDR + : REG_SPIDMA0_ADDR1_ADDR, + (reg >> 8) & 0xFF); + ADI_APOLLO_ERROR_RETURN(err); + desc->indir_cache.addr1 = (reg >> 8) & 0xFF; + } + + // The DMA (indirect) register is not latched in until + // the least-significant byte is written. So always write this last byte. + err = spi_regio_write(desc, + desc->is_spi1 ? REG_SPIDMA1_ADDR0_ADDR + : REG_SPIDMA0_ADDR0_ADDR, + (reg >> 0) & 0xFF); + ADI_APOLLO_ERROR_RETURN(err); + } + + return API_CMS_ERROR_OK; +} + +/* + This mode is introduced in SPI Slave to improve SPI Indirect DMA efficiency when it is in auto-increment/decrement mode. + + spi_fifo_mode[2:0] Description + 000 SPI usual behavior (no change) + 001 8-bit access + 010 16-bit access + 011 32-bit access + +*/ +static __maybe_unused int32_t set_spi_fifo_mode(adi_apollo_hal_regio_spi_desc_t *desc, uint8_t is_fifo_enabled, adi_apollo_hal_regio_spi_bus_size_e bus_size) +{ + int32_t err; + + if (is_fifo_enabled) { + if (bus_size == ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D32) { + err = spi_regio_write(desc, REG_SPI_FIFO_MODE_REG_ADDR, 0x03u); + } else if(bus_size == ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D16) { + err = spi_regio_write(desc, REG_SPI_FIFO_MODE_REG_ADDR, 0x02u); + } else if (bus_size == ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D8) { + err = spi_regio_write(desc, REG_SPI_FIFO_MODE_REG_ADDR, 0x01u); + } + } else { + err = spi_regio_write(desc, REG_SPI_FIFO_MODE_REG_ADDR, 0x00u); + } + + return err; +} + +static int32_t stream_write(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t reg, uint8_t *data, adi_apollo_hal_regio_spi_bus_size_e bus_size, uint32_t stream_bytes, uint8_t is_cont) +{ + int32_t err; + + uint32_t pending_sz_bytes = stream_bytes; + uint32_t data_index = 0; + uint32_t data32; + + if(!is_cont) { + uint8_t spidma_ahb_bus_select = 0; + uint8_t spidma_auto_incr = 1; + uint8_t spidma_bus_size = bus_size; // Size of read/write. 0 = byte, 1 = half-word, 2 = full-word, 3 = invalid. + uint8_t spidma_sys_codeb = 0; + uint8_t spidma_rd_wrb = 0; + uint8_t spidma_ctl_data = (spidma_rd_wrb << 7) | (spidma_sys_codeb << 6) | (spidma_bus_size << 2) | (spidma_auto_incr << 1) | (spidma_ahb_bus_select << 0); + + //set_spi_fifo_mode(desc, 4); // 4 = no fifo mode + indirect_addr_set(desc, reg, spidma_ctl_data); + } + + while (pending_sz_bytes > 0) { + if (bus_size == ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D32 && pending_sz_bytes > 3) { + data32 = (data[data_index + 3] << 0) | (data[data_index + 2] << 8) | (data[data_index + 1] << 16) | (data[data_index + 0] << 24); + err = direct_or_paged_write(desc, desc->is_spi1 ? REG_SPIDMA1_DATA3_ADDR : REG_SPIDMA0_DATA3_ADDR, + data32, ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D32, + ADI_APOLLO_HAL_REGIO_NOMASK, ADI_APOLLO_HAL_REGIO_NOT_PAGED); + ADI_APOLLO_ERROR_RETURN(err); + pending_sz_bytes -= 4; + data_index += 4; + } else if (((bus_size == ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D32) || (bus_size == ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D16)) && pending_sz_bytes > 1) { + data32 = (data[data_index + 1] << 0) | (data[data_index + 0] << 8); + err = direct_or_paged_write(desc, desc->is_spi1 ? REG_SPIDMA1_DATA1_ADDR : REG_SPIDMA0_DATA1_ADDR, + data32 & 0x0000ffff, ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D16, + ADI_APOLLO_HAL_REGIO_NOMASK, ADI_APOLLO_HAL_REGIO_NOT_PAGED); + ADI_APOLLO_ERROR_RETURN(err); + pending_sz_bytes -= 2; + data_index += 2; + } else { + data32 = data[data_index + 0]; + err = direct_or_paged_write(desc, desc->is_spi1 ? REG_SPIDMA1_DATA0_ADDR : REG_SPIDMA0_DATA0_ADDR, + data32 & 0x000000ff, ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D8, + ADI_APOLLO_HAL_REGIO_NOMASK, ADI_APOLLO_HAL_REGIO_NOT_PAGED); + ADI_APOLLO_ERROR_RETURN(err); + pending_sz_bytes -= 1; + data_index += 1; + } + } + + return err; +} + +static int32_t stream_read(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t reg, uint8_t *data, adi_apollo_hal_regio_spi_bus_size_e bus_size, uint32_t stream_bytes, uint8_t is_cont) +{ + int32_t err; + + uint32_t pending_sz_bytes = stream_bytes; + uint32_t data32; + uint8_t *data_ptr; + + if(!is_cont) { + uint8_t spidma_ahb_bus_select = 0; + uint8_t spidma_auto_incr = 1; + uint8_t spidma_bus_size = bus_size; // Size of read/write. 0 = byte, 1 = half-word, 2 = full-word, 3 = invalid. + uint8_t spidma_sys_codeb = 0; + uint8_t spidma_rd_wrb = 1; + uint8_t spidma_ctl_data = (spidma_rd_wrb << 7) | (spidma_sys_codeb << 6) | (spidma_bus_size << 2) | (spidma_auto_incr << 1) | (spidma_ahb_bus_select << 0); + + indirect_addr_set(desc, reg, spidma_ctl_data); + } + + *data = 0; + + data_ptr = (uint8_t *) data; + + while (pending_sz_bytes > 0) { + if (bus_size == ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D32 && pending_sz_bytes > 3) { + err = direct_read(desc, desc->is_spi1 ? REG_SPIDMA1_DATA3_ADDR : REG_SPIDMA0_DATA3_ADDR, + &data32, ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D32); + ADI_APOLLO_ERROR_RETURN(err); + *(data_ptr + 0) = (data32 >> 24) & 0xff; + *(data_ptr + 1) = (data32 >> 16) & 0xff; + *(data_ptr + 2) = (data32 >> 8) & 0xff; + *(data_ptr + 3) = (data32 >> 0) & 0xff; + pending_sz_bytes -= 4; + data_ptr += 4; + } else if (((bus_size == ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D32) || (bus_size == ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D16)) && pending_sz_bytes > 1) { + err = direct_read(desc, desc->is_spi1 ? REG_SPIDMA1_DATA1_ADDR : REG_SPIDMA0_DATA1_ADDR, + &data32, ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D16); + ADI_APOLLO_ERROR_RETURN(err); + *(data_ptr + 0) = (data32 >> 8) & 0xff; + *(data_ptr + 1) = (data32 >> 0) & 0xff; + pending_sz_bytes -= 2; + data_ptr += 2; + } else { + err = direct_read(desc, desc->is_spi1 ? REG_SPIDMA1_DATA0_ADDR : REG_SPIDMA0_DATA0_ADDR, + &data32, ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D8); + ADI_APOLLO_ERROR_RETURN(err); + *(data_ptr + 0) = (data32 >> 0) & 0xff; + pending_sz_bytes -= 1; + data_ptr += 1; + } + } + + return err; +} + +/* Checks paged address alignment and updates address if out of active page range */ +static int32_t align_page_base_address(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t reg, adi_apollo_hal_regio_spi_bus_size_e size, uint32_t *reg_offset_p) +{ + int32_t err; + uint32_t range = (size == ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D8) ? 0 : 3; /* 8 bit, 32 bit */ + int32_t reg_offset = reg - desc->page_base_addr; + + if ( (reg_offset < 0) || ((reg_offset + range) > (ADI_APOLLO_DIRECT_SPI_REGION_LEN - 1)) ) + { + err = spi_regio_paged_base_addr_set(desc, reg & 0xffffc000); // Page offset out of range for this transaction. Updates desc->page_base_addr. + if (err != API_CMS_ERROR_OK) { + return err; + } + reg_offset = reg - desc->page_base_addr; + } + + /* reg offset from page base */ + *reg_offset_p = (uint32_t)reg_offset; + + return API_CMS_ERROR_OK; +} + +static __maybe_unused int32_t spi_write_stream_fifo_mode(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t reg, uint8_t *data, uint32_t data_len_bytes, uint64_t mask, uint8_t is_bf) +{ + int32_t dma_dat0, err, i; + uint8_t in_data[16] = { 0 }; + uint8_t xfer_sz_bytes; + + set_spi_fifo_mode(desc, 1, ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D8); + + /* Set txn config info for bitfield */ + txn_config_set(desc, 2, 1, data_len_bytes, mask, is_bf); /* 2 addr, 1 data, data_len_bytes */ + + /* Write the SPI DMA control reg data with first byte */ + dma_dat0 = desc->is_spi1 ? REG_SPIDMA1_DATA0_ADDR : REG_SPIDMA0_DATA0_ADDR; + in_data[0] = ((dma_dat0 >> 8) & 0x3F) | 0x80; + in_data[1] = (dma_dat0 >> 0) & 0xFF; + + for (i = 0; i < data_len_bytes; i++) { + in_data[2 + i] = data[i]; + } + xfer_sz_bytes = 2 + data_len_bytes; + err = desc->write(desc->dev_obj, in_data, xfer_sz_bytes, &desc->txn_config); + + /* Reset txn spi fifo mode */ + set_spi_fifo_mode(desc, 0, ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D8); + + return (err == API_CMS_ERROR_OK) ? API_CMS_ERROR_OK : API_CMS_ERROR_SPI_REGIO_XFER; +} + +static __maybe_unused int32_t txn_config_default_set(adi_apollo_hal_regio_spi_desc_t *desc, adi_apollo_hal_regio_spi_bus_size_e spi_bus_size) +{ + adi_apollo_hal_txn_config_t *txn_config_p = &desc->txn_config; + adi_apollo_hal_txn_config_t *default_txn_config_p = &default_txn_cfgs[spi_bus_size]; + + txn_config_p->addr_len = default_txn_config_p->addr_len; + txn_config_p->data_len = default_txn_config_p->data_len; + txn_config_p->stream_len = default_txn_config_p->stream_len; + txn_config_p->mask = default_txn_config_p->mask; + txn_config_p->is_bf_txn = default_txn_config_p->is_bf_txn; + + return API_CMS_ERROR_OK; +} + + +static int32_t txn_config_set(adi_apollo_hal_regio_spi_desc_t *desc, uint8_t addr_siz_bytes, uint8_t data_siz_bytes, uint8_t stream_len, uint64_t mask, uint8_t is_bf_txn) +{ + adi_apollo_hal_txn_config_t *txn_config_p = &desc->txn_config; + + txn_config_p->addr_len = addr_siz_bytes; + txn_config_p->data_len = data_siz_bytes; + txn_config_p->stream_len = stream_len; + txn_config_p->mask = mask; + txn_config_p->is_bf_txn = is_bf_txn; + + return API_CMS_ERROR_OK; +} + +/* + * indirect_readx - Indirect register read that doesn't generate any streaming transactions. Use when rd_stream_en = 0. + */ +static int32_t indirect_readx(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t reg, uint32_t *data, adi_apollo_hal_regio_spi_bus_size_e bus_size) { + int32_t err; + uint8_t spidma_ahb_bus_select = 0; + uint8_t spidma_auto_incr = 0; + uint8_t spidma_bus_size = bus_size; // Size of read/write. 0 = byte, 1 = half-word, 2 = full-word, 3 = invalid. + uint8_t spidma_sys_codeb = 0; + uint8_t spidma_rd_wrb = 1; + uint8_t spidma_ctl_data = (spidma_rd_wrb << 7) | (spidma_sys_codeb << 6) | (spidma_bus_size << 2) | (spidma_auto_incr << 1) | (spidma_ahb_bus_select << 0); + uint8_t *data_ptr; + + /* Set the dma ctl and address */ + err = indirect_addr_set(desc, reg, spidma_ctl_data); + ADI_APOLLO_ERROR_RETURN(err); + + *data = 0; + + data_ptr = (uint8_t *) data; + + if (bus_size == ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D32) { + err = spi_regio_read(desc, desc->is_spi1 ? REG_SPIDMA1_DATA3_ADDR : REG_SPIDMA0_DATA3_ADDR, data_ptr + 3); /* msb */ + ADI_APOLLO_ERROR_RETURN(err); + err = spi_regio_read(desc, desc->is_spi1 ? REG_SPIDMA1_DATA2_ADDR : REG_SPIDMA0_DATA2_ADDR, data_ptr + 2); + ADI_APOLLO_ERROR_RETURN(err); + } + + if ((bus_size == ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D32) || (bus_size == ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D16)) { + err = spi_regio_read(desc, desc->is_spi1 ? REG_SPIDMA1_DATA1_ADDR : REG_SPIDMA0_DATA1_ADDR, data_ptr + 1); + ADI_APOLLO_ERROR_RETURN(err); + } + + err = spi_regio_read(desc, desc->is_spi1 ? REG_SPIDMA1_DATA0_ADDR : REG_SPIDMA0_DATA0_ADDR, data_ptr + 0); /* lsb */ + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +/* + * indirect_writex - Indirect register write that doesn't generate any streaming transactions. Use when wr_stream_en = 0. + */ +static int32_t indirect_writex(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t reg, uint32_t data, adi_apollo_hal_regio_spi_bus_size_e bus_size) { + int32_t err; + uint8_t spidma_ahb_bus_select = 0; + uint8_t spidma_auto_incr = 0; + uint8_t spidma_bus_size = bus_size; // Size of read/write. 0 = byte, 1 = half-word, 2 = full-word, 3 = invalid. + uint8_t spidma_sys_codeb = 0; + uint8_t spidma_rd_wrb = 0; + uint8_t spidma_ctl_data = (spidma_rd_wrb << 7) | (spidma_sys_codeb << 6) | (spidma_bus_size << 2) | (spidma_auto_incr << 1) | (spidma_ahb_bus_select << 0); + + /* Set the dma ctl and address */ + indirect_addr_set(desc, reg, spidma_ctl_data); + + if (bus_size == ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D32) { + err = spi_regio_write(desc, desc->is_spi1 ? REG_SPIDMA1_DATA3_ADDR : REG_SPIDMA0_DATA3_ADDR, (data >> 24) & 0xFF); // MSB + ADI_APOLLO_ERROR_RETURN(err); + err = spi_regio_write(desc, desc->is_spi1 ? REG_SPIDMA1_DATA2_ADDR : REG_SPIDMA0_DATA2_ADDR, (data >> 16) & 0xFF); + ADI_APOLLO_ERROR_RETURN(err); + } + + if ((bus_size == ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D32) || (bus_size == ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D16)) { + err = spi_regio_write(desc, desc->is_spi1 ? REG_SPIDMA1_DATA1_ADDR : REG_SPIDMA0_DATA1_ADDR, (data >> 8) & 0xFF); + ADI_APOLLO_ERROR_RETURN(err); + } + + err = spi_regio_write(desc, desc->is_spi1 ? REG_SPIDMA1_DATA0_ADDR : REG_SPIDMA0_DATA0_ADDR, (data >> 0) & 0xFF); // LSB + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +/* + * stream_readx - pseudo read stream function that doesn't generate any streaming transactions. Use when rd_stream_en = 0. + */ +static int32_t stream_readx(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t reg, uint8_t *data, adi_apollo_hal_regio_spi_bus_size_e bus_size, uint32_t stream_bytes, uint8_t is_cont) { + int32_t err; + + uint32_t pending_sz_bytes = stream_bytes; + uint8_t *data_ptr; + + if (!is_cont) { + uint8_t spidma_ahb_bus_select = 0; + uint8_t spidma_auto_incr = 1; + uint8_t spidma_bus_size = bus_size; // Size of read/write. 0 = byte, 1 = half-word, 2 = full-word, 3 = invalid. + uint8_t spidma_sys_codeb = 0; + uint8_t spidma_rd_wrb = 1; + uint8_t spidma_ctl_data = (spidma_rd_wrb << 7) | (spidma_sys_codeb << 6) | (spidma_bus_size << 2) | (spidma_auto_incr << 1) | (spidma_ahb_bus_select << 0); + + indirect_addr_set(desc, reg, spidma_ctl_data); + } + + *data = 0; + + data_ptr = (uint8_t *) data; + + while (pending_sz_bytes > 0) { + if (bus_size == ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D32 && pending_sz_bytes > 3) { + err = spi_regio_read(desc, desc->is_spi1 ? REG_SPIDMA1_DATA3_ADDR : REG_SPIDMA0_DATA3_ADDR, (data_ptr + 3)); + ADI_APOLLO_ERROR_RETURN(err); + err = spi_regio_read(desc, desc->is_spi1 ? REG_SPIDMA1_DATA2_ADDR : REG_SPIDMA0_DATA2_ADDR, (data_ptr + 2)); + ADI_APOLLO_ERROR_RETURN(err); + pending_sz_bytes -= 2; + } + + if (((bus_size == ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D32) || (bus_size == ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D16)) && pending_sz_bytes > 1) { + err = spi_regio_read(desc, desc->is_spi1 ? REG_SPIDMA1_DATA1_ADDR : REG_SPIDMA0_DATA1_ADDR, (data_ptr + 1)); + ADI_APOLLO_ERROR_RETURN(err); + pending_sz_bytes -= 1; + } + + err = spi_regio_read(desc, desc->is_spi1 ? REG_SPIDMA1_DATA0_ADDR : REG_SPIDMA0_DATA0_ADDR, (data_ptr + 0)); + ADI_APOLLO_ERROR_RETURN(err); + pending_sz_bytes -= 1; + + if (bus_size == ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D32) { + data_ptr += 4; + } else if (bus_size == ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D16) { + data_ptr += 2; + } else { + data_ptr += 1; + } + } + return err; +} + +/* + * stream_writex - pseudo write stream function that doesn't generate any streaming transactions. Use when wr_stream_en = 0. + */ +static int32_t stream_writex(adi_apollo_hal_regio_spi_desc_t *desc, uint32_t reg, uint8_t *data, adi_apollo_hal_regio_spi_bus_size_e bus_size, uint32_t stream_bytes, uint8_t is_cont) { + int32_t err; + + uint32_t pending_sz_bytes = stream_bytes; + uint32_t data_index = 0; + + if (!is_cont) { + uint8_t spidma_ahb_bus_select = 0; + uint8_t spidma_auto_incr = 1; + uint8_t spidma_bus_size = bus_size; // Size of read/write. 0 = byte, 1 = half-word, 2 = full-word, 3 = invalid. + uint8_t spidma_sys_codeb = 0; + uint8_t spidma_rd_wrb = 0; + uint8_t spidma_ctl_data = (spidma_rd_wrb << 7) | (spidma_sys_codeb << 6) | (spidma_bus_size << 2) | (spidma_auto_incr << 1) | (spidma_ahb_bus_select << 0); + + indirect_addr_set(desc, reg, spidma_ctl_data); + } + + while (pending_sz_bytes > 0) { + if (bus_size == ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D32 && pending_sz_bytes > 3) { + err = spi_regio_write(desc, desc->is_spi1 ? REG_SPIDMA1_DATA3_ADDR : REG_SPIDMA0_DATA3_ADDR, (data[data_index + 3]) & 0xFF); + ADI_APOLLO_ERROR_RETURN(err); + err = spi_regio_write(desc, desc->is_spi1 ? REG_SPIDMA1_DATA2_ADDR : REG_SPIDMA0_DATA2_ADDR, (data[data_index + 2]) & 0xFF); + ADI_APOLLO_ERROR_RETURN(err); + pending_sz_bytes -= 2; + } + + if (((bus_size == ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D32) || (bus_size == ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D16)) && pending_sz_bytes > 1) { + err = spi_regio_write(desc, desc->is_spi1 ? REG_SPIDMA1_DATA1_ADDR : REG_SPIDMA0_DATA1_ADDR, (data[data_index + 1]) & 0xFF); + ADI_APOLLO_ERROR_RETURN(err); + pending_sz_bytes -= 1; + } + + err = spi_regio_write(desc, desc->is_spi1 ? REG_SPIDMA1_DATA0_ADDR : REG_SPIDMA0_DATA0_ADDR, (data[data_index]) & 0xFF); + ADI_APOLLO_ERROR_RETURN(err); + pending_sz_bytes -= 1; + + if (bus_size == ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D32) { + data_index += 4; + } else if (bus_size == ADI_APOLLO_HAL_REGIO_SPI_BUS_SIZE_D16) { + data_index += 2; + } else { + data_index += 1; + } + } + + return err; +} diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_invsinc.c b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_invsinc.c new file mode 100644 index 00000000000000..3725a503cf0ba1 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_invsinc.c @@ -0,0 +1,113 @@ +/*! + * \brief APIs for Tx Inverse Sinc + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_INVSINC + * @{ + */ + +/*============= I N C L U D E S ============*/ +#include "adi_utils.h" +#include "adi_apollo_invsinc.h" +#include "adi_apollo_private_blk_sel_types.h" + +#include "adi_apollo_bf_tx_hsdout.h" +#include "adi_apollo_config.h" +#include "adi_apollo_hal.h" + +/*==================== P U B L I C A P I C O D E ====================*/ +static uint32_t calc_tx_hsdout_base(int32_t index); + +int32_t adi_apollo_invsinc_enable(adi_apollo_device_t *device, adi_apollo_blk_sel_t invsincs, const uint8_t enable) +{ + int32_t err; + uint8_t i; + adi_apollo_blk_sel_t invsinc; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVSINC_BLK_SEL_MASK(invsincs); + + for (i = 0; i < ADI_APOLLO_NUM_INVSINC; i++) { + invsinc = invsincs & (ADI_APOLLO_INVSINC_A0 << i) & (device->dev_info.is_8t8r ? 0xff : 0x33); + if (invsinc > 0) { + regmap_base_addr = calc_tx_hsdout_base(i); + + /* Enable INVSINC CLK */ + err = adi_apollo_hal_bf_set(device, BF_INVSINC_CLK_EN_INFO(regmap_base_addr), enable); + ADI_APOLLO_ERROR_RETURN(err); + + /* Enable INVSINC */ + err = adi_apollo_hal_bf_set(device, BF_INVSINC_EN_INFO(regmap_base_addr), enable); + ADI_APOLLO_ERROR_RETURN(err); + + if (device->dev_info.is_8t8r == 0) { // In 4T4R, in the current design, Invsinc enable control uses 2 bits to control each slice. + regmap_base_addr = calc_tx_hsdout_base(i + 2); + + err = adi_apollo_hal_bf_set(device, BF_INVSINC_EN_INFO(regmap_base_addr), enable); + ADI_APOLLO_ERROR_RETURN(err); + } + } + } + + return API_CMS_ERROR_OK; +} + + +int32_t adi_apollo_invsinc_inspect(adi_apollo_device_t *device, adi_apollo_blk_sel_t invsincs, adi_apollo_invsinc_inspect_t *invsinc_inspect) +{ + int32_t err; + uint8_t i; + adi_apollo_blk_sel_t invsinc; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(invsinc_inspect); + ADI_APOLLO_INVALID_PARAM_RETURN(adi_api_utils_num_selected(invsincs) != 1); + ADI_APOLLO_INVSINC_BLK_SEL_MASK(invsincs); + + for (i = 0; i < ADI_APOLLO_NUM_INVSINC; i++) { + invsinc = invsincs & (ADI_APOLLO_INVSINC_A0 << i); + if (invsinc > 0) { + regmap_base_addr = calc_tx_hsdout_base(i); + + /* Get INVSINC CLK enable state */ + err = adi_apollo_hal_bf_get(device, BF_INVSINC_CLK_EN_INFO(regmap_base_addr), &(invsinc_inspect->invsinc_clk_en), 1); + ADI_APOLLO_ERROR_RETURN(err); + + /* Get INVSINC enable state */ + err = adi_apollo_hal_bf_get(device, BF_INVSINC_EN_INFO(regmap_base_addr), &(invsinc_inspect->invsinc_en), 1); + ADI_APOLLO_ERROR_RETURN(err); + + break; /* only one chan per call */ + } + } + + return API_CMS_ERROR_OK; +} + +static uint32_t calc_tx_hsdout_base(int32_t index) +{ + static uint32_t tx_hsdout_regmap[ADI_APOLLO_DAC_NUM] = { + TX_HSDOUT0_TX_SLICE_0_TX_DIGITAL0, /* A0 */ + TX_HSDOUT0_TX_SLICE_1_TX_DIGITAL0, /* A1 */ + TX_HSDOUT1_TX_SLICE_0_TX_DIGITAL0, /* A2 */ + TX_HSDOUT1_TX_SLICE_1_TX_DIGITAL0, /* A3 */ + + TX_HSDOUT0_TX_SLICE_0_TX_DIGITAL1, /* B0 */ + TX_HSDOUT0_TX_SLICE_1_TX_DIGITAL1, /* B1 */ + TX_HSDOUT1_TX_SLICE_0_TX_DIGITAL1, /* B2 */ + TX_HSDOUT1_TX_SLICE_1_TX_DIGITAL1 /* B3 */ + }; + return tx_hsdout_regmap[index]; +} + +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_jrx.c b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_jrx.c new file mode 100644 index 00000000000000..9b83f1f3ba1b5f --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_jrx.c @@ -0,0 +1,884 @@ +/*! + * \brief APIs for JESD Rx (JRx) + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_JRX + * @{ + */ + +/*============= I N C L U D E S ============*/ +#include "adi_utils.h" +#include "adi_apollo_jrx.h" + +#include "adi_apollo_bf_jrx_jesd_l0.h" +#include "adi_apollo_bf_jrx_phy_ifx.h" +#include "adi_apollo_bf_jrx_core.h" +#include "adi_apollo_bf_jrx_wrapper.h" +#include "adi_apollo_bf_jrx_dac_sample_prbs.h" +#include "adi_apollo_bf_jrx_dl_204c.h" +#include "adi_apollo_bf_jrx_dl_204b.h" +#include "adi_apollo_bf_custom.h" +#include "adi_apollo_bf_jrx_jesd_l0.h" +#include "adi_apollo_bf_custom.h" + +#include "adi_apollo_serdes.h" + +#include "adi_apollo_config.h" +#include "adi_apollo_hal.h" + +static uint32_t calc_jrx_core_base(int32_t link); +static uint32_t calc_jrx_wrapper_base(int32_t link); +static uint32_t calc_jrx_dl_204c_base(int32_t link); +static uint32_t calc_jrx_dl_204b_base(int32_t link); +static uint32_t calc_jrx_jesd_l0_base(int32_t link); +static void calc_j204c_irq_en(uint32_t base, int32_t link, uint32_t idx, uint32_t *address, uint32_t *info); +static void calc_j204c_irq(uint32_t base, int32_t link, uint32_t idx, uint32_t *address, uint32_t *info); +static uint32_t calc_jrx_phy_ifx_base(int32_t link); + +/*==================== P U B L I C A P I C O D E ====================*/ + +int32_t adi_apollo_jrx_link_enable_set(adi_apollo_device_t *device, + const uint16_t links, + uint8_t link_en) +{ + int32_t err; + uint32_t regmap_base_addr = 0; + uint8_t i, link_enable = 0; + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + for (i = 0; i < ADI_APOLLO_NUM_JRX_LINKS; i++) { + if ((1 << i) & links) { + + regmap_base_addr = calc_jrx_wrapper_base(i); + err = adi_apollo_hal_bf_get(device, BF_LINK_EN_INFO(regmap_base_addr), &link_enable, 1); + ADI_APOLLO_ERROR_RETURN(err); + + if(i%ADI_APOLLO_NUM_JRX_LINKS_PER_SIDE == 0) { + link_enable &= ~(0x01); + link_enable |= link_en; + } else { + link_enable &= ~(0x02); + link_enable |= (link_en << 1); + } + err = adi_apollo_hal_bf_set(device, BF_LINK_EN_INFO(regmap_base_addr), link_enable); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_jrx_lane_fifo_status(adi_apollo_device_t *device, + const uint16_t link, + uint32_t *status) +{ + int32_t err; + uint32_t regmap_base_addr = 0; + uint32_t res = 0x00; + uint16_t lane_fifo_empty; + uint16_t lane_fifo_full; + uint8_t link_index = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(status); + ADI_APOLLO_INVALID_PARAM_RETURN(adi_api_utils_num_selected(link) != 1); // Check if only one link is selected + + link_index = adi_api_utils_select_lsb_get(link); + + regmap_base_addr = calc_jrx_wrapper_base(link_index); + + err = adi_apollo_hal_bf_get(device, BF_LANE_FIFO_EMPTY_INFO(regmap_base_addr), (uint8_t *)&lane_fifo_empty, 2); + ADI_APOLLO_ERROR_RETURN(err); + res |= lane_fifo_empty & 0x0FFF; + + err = adi_apollo_hal_bf_get(device, BF_LANE_FIFO_FULL_INFO(regmap_base_addr), (uint8_t *)&lane_fifo_full, 2); + ADI_APOLLO_ERROR_RETURN(err); + res |= (lane_fifo_full << 16) & 0x0FFF0000; + + *status = res; + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_jrx_rm_fifo_status(adi_apollo_device_t *device, + const uint16_t link, + uint16_t *status) +{ + int32_t err; + uint32_t regmap_base_addr = 0; + uint16_t res = 0x00; + uint8_t reg8; + uint8_t link_index = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(status); + //ADI_APOLLO_INVALID_PARAM_RETURN(link_side > ADI_APOLLO_NUM_JRX_LINKS_PER_SIDE); + ADI_APOLLO_INVALID_PARAM_RETURN(adi_api_utils_num_selected(link) != 1); // Check if only one link is selected + + link_index = adi_api_utils_select_lsb_get(link); + + + regmap_base_addr = calc_jrx_wrapper_base(link_index); + + err = adi_apollo_hal_reg_get(device, REG_RM_FIFO_STATUS_ADDR(regmap_base_addr), ®8); /* RM FIFO status */ + ADI_APOLLO_ERROR_RETURN(err); + if(link_index % ADI_APOLLO_NUM_JRX_LINKS_PER_SIDE == 0) { + res |= reg8 & 0x01; + res |= (reg8 >> 1) & 0x02; + res |= (reg8 >> 2) & 0x04; + } else { + res |= (reg8 >> 1) & 0x01; + res |= (reg8 >> 2) & 0x02; + res |= (reg8 >> 2) & 0x04; + } + + *status = res; + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_jrx_rm_fifo_reset(adi_apollo_device_t *device, + const uint16_t link_sides) +{ + int32_t err, i; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + for (i = 0; i < ADI_APOLLO_NUM_JRX_LINKS; i += ADI_APOLLO_NUM_JRX_LINKS_PER_SIDE) { + if ((1 << i) & link_sides) { + regmap_base_addr = calc_jrx_wrapper_base(i); + err = adi_apollo_hal_bf_set(device, BF_RM_FIFO_RESET_INFO(regmap_base_addr), 0); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_RM_FIFO_RESET_INFO(regmap_base_addr), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_RM_FIFO_RESET_INFO(regmap_base_addr), 0); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_jrx_j204c_lane_status_get(adi_apollo_device_t *device, + const uint16_t link, + const uint16_t lane, + uint16_t *status) +{ + int32_t err; + uint32_t regmap_base_addr = 0; + uint16_t res = 0x00; + uint8_t reg8; + uint8_t link_index = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(status); + ADI_APOLLO_INVALID_PARAM_RETURN(lane >= ADI_APOLLO_JESD_DESER_COUNT); // Check if lane is in range + ADI_APOLLO_INVALID_PARAM_RETURN(adi_api_utils_num_selected(link) != 1); // Check if only one link is selected + + link_index = adi_api_utils_select_lsb_get(link); + + regmap_base_addr = calc_jrx_dl_204c_base(link_index); + + err = adi_apollo_hal_bf_get(device, BF_JRX_DL_204C_STATE_INFO(regmap_base_addr, lane), ®8, 1); /* 204C Lane status register */ + ADI_APOLLO_ERROR_RETURN(err); + res |= (reg8 & 0x07); + + regmap_base_addr = calc_jrx_core_base(link_index); + + if (link_index % ADI_APOLLO_NUM_JRX_LINKS_PER_SIDE == 0) { + err = adi_apollo_hal_bf_get(device, BF_JRX_CORE_PCLK_SLOW_ERROR_LINK0_INFO(regmap_base_addr, lane), ®8, 1); + res |= (reg8 << 4) & 0x10; + + err = adi_apollo_hal_bf_get(device, BF_JRX_CORE_PCLK_FAST_ERROR_LINK0_INFO(regmap_base_addr, lane), ®8, 1); + res |= (reg8 << 5) & 0x20; + } else { + + err = adi_apollo_hal_bf_get(device, BF_JRX_CORE_PCLK_SLOW_ERROR_LINK1_INFO(regmap_base_addr, lane), ®8, 1); + res |= (reg8 << 4) & 0x10; + + err = adi_apollo_hal_bf_get(device, BF_JRX_CORE_PCLK_FAST_ERROR_LINK1_INFO(regmap_base_addr, lane), ®8, 1); + res |= (reg8 << 5) & 0x20; + } + + *status = res; + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_jrx_link_status_get(adi_apollo_device_t *device, + const uint16_t link, + uint16_t *status) +{ + int32_t err; + uint32_t regmap_base_addr = 0; + uint8_t reg8; + uint16_t res = 0x00; + uint8_t link_index = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(status); + ADI_APOLLO_INVALID_PARAM_RETURN(adi_api_utils_num_selected(link) != 1); // Check if only one link is selected + + link_index = adi_api_utils_select_lsb_get(link); + + regmap_base_addr = calc_jrx_wrapper_base(link_index); + + err = adi_apollo_hal_bf_get(device, BF_JESD_MODES_NOT_IN_TABLE_INFO(regmap_base_addr, link_index % ADI_APOLLO_NUM_JRX_LINKS_PER_SIDE), ®8, 1); + ADI_APOLLO_ERROR_RETURN(err); + res |= (reg8 & 0x01); // & ADI_APOLLO_JRX_LINK_STAT_NOT_IN_TABLE + + err = adi_apollo_hal_bf_get(device, BF_DOWN_SCALE_OVERFLOW_INFO(regmap_base_addr, link_index % ADI_APOLLO_NUM_JRX_LINKS_PER_SIDE), ®8, 1); + ADI_APOLLO_ERROR_RETURN(err); + res |= (reg8 << 1) & ADI_APOLLO_JRX_LINK_STAT_SCALE_OVERFLOW; + + regmap_base_addr = calc_jrx_core_base(link); + + err = adi_apollo_hal_bf_get(device, BF_JRX_CORE_USR_DATA_RDY_INFO(regmap_base_addr, link_index % ADI_APOLLO_NUM_JRX_LINKS_PER_SIDE), ®8, 1); + ADI_APOLLO_ERROR_RETURN(err); + res |= (reg8 << 5) & ADI_APOLLO_JRX_LINK_STAT_USR_DAT_RDY; + + err = adi_apollo_hal_bf_get(device, BF_JRX_CORE_SYSREF_RCVD_INFO(regmap_base_addr, link_index % ADI_APOLLO_NUM_JRX_LINKS_PER_SIDE), ®8, 1); + ADI_APOLLO_ERROR_RETURN(err); + res |= (reg8 << 6) & ADI_APOLLO_JRX_LINK_STAT_SYSREF_RECV; + + err = adi_apollo_hal_bf_get(device, BF_JRX_CORE_CFG_INVALID_INFO(regmap_base_addr, link_index % ADI_APOLLO_NUM_JRX_LINKS_PER_SIDE), ®8, 1); + ADI_APOLLO_ERROR_RETURN(err); + res |= (reg8 << 7) & ADI_APOLLO_JRX_LINK_STAT_CFG_INVALID; + + *status = res; + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_jrx_j204b_lane_status_get(adi_apollo_device_t *device, + const uint16_t link, + const uint16_t lane, + uint16_t *status) +{ + int32_t err; + uint32_t regmap_base_addr = 0; + uint16_t res = 0x00; + uint8_t reg8; + uint8_t link_index = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(status); + ADI_APOLLO_INVALID_PARAM_RETURN(lane >= ADI_APOLLO_JESD_DESER_COUNT); // Check if lane is in range + ADI_APOLLO_INVALID_PARAM_RETURN(adi_api_utils_num_selected(link) != 1); // Check if only one link is selected + + link_index = adi_api_utils_select_lsb_get(link); + + regmap_base_addr = calc_jrx_dl_204b_base(link_index); + + err = adi_apollo_hal_reg_get(device, REG_JRX_DL_204B_LANE_STATUS_ADDR(regmap_base_addr, lane), ®8); + + ADI_APOLLO_ERROR_RETURN(err); + res |= reg8 & 0x3F; + + *status = res; + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_jrx_j204b_lane_error_get(adi_apollo_device_t *device, + const uint16_t link, + const uint16_t lane, + uint16_t *status) +{ + int32_t err; + uint32_t regmap_base_addr = 0; + uint8_t reg8; + uint16_t res = 0x00; + uint8_t link_index = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(status); + ADI_APOLLO_INVALID_PARAM_RETURN(lane >= ADI_APOLLO_JESD_DESER_COUNT); // Check if lane is in range + ADI_APOLLO_INVALID_PARAM_RETURN(adi_api_utils_num_selected(link) != 1); // Check if only one link is selected + + link_index = adi_api_utils_select_lsb_get(link); + + regmap_base_addr = calc_jrx_dl_204b_base(link_index); + + err = adi_apollo_hal_reg_get(device, REG_JRX_DL_204B_LANE_ERR_STATUS_ADDR(regmap_base_addr, lane), ®8); + + ADI_APOLLO_ERROR_RETURN(err); + res |= reg8; + + *status = res; + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_jrx_lr_adapt_get(adi_apollo_device_t *device, + uint8_t link_sides, + uint8_t physical_lane, + uint8_t *lr_adapt) +{ + int32_t err, i; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(lr_adapt); + ADI_APOLLO_INVALID_PARAM_RETURN(link_sides > ADI_APOLLO_LINK_SIDE_ALL); + ADI_APOLLO_INVALID_PARAM_RETURN(physical_lane > ADI_APOLLO_JRX_LANES_MAX - 1); + + + for (i = 0; i < ADI_APOLLO_NUM_JRX_LINKS; i += ADI_APOLLO_NUM_JRX_LINKS_PER_SIDE) { + if ((1 << i) & link_sides) { + regmap_base_addr = calc_jrx_phy_ifx_base(i); + err = adi_apollo_hal_bf_get(device, BF_JRX_IFX_LOG2_SPLIT_INFO(regmap_base_addr, physical_lane), lr_adapt, 1); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_jrx_clear_pclk_errors(adi_apollo_device_t *device, + const uint16_t links) +{ + int32_t err; + uint32_t regmap_base_addr = 0; + uint8_t link; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + for (link = 0; link < ADI_APOLLO_NUM_JRX_LINKS; link++) { + if ((1 << link) & links) { + regmap_base_addr = calc_jrx_core_base(link); + err = adi_apollo_hal_bf_set(device, BF_JRX_CORE_PCLK_ERROR_CLEAR_INFO(regmap_base_addr, link % ADI_APOLLO_NUM_JRX_LINKS_PER_SIDE), 1); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_jrx_link_inspect(adi_apollo_device_t *device, + const uint16_t links, + adi_apollo_jesd_rx_inspect_t *jrx_inspect) +{ + int32_t err; + uint32_t regmap_base_addr = 0; + uint8_t link = 0; + uint8_t link_enable; + uint8_t i; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(jrx_inspect); + ADI_APOLLO_INVALID_PARAM_RETURN(adi_api_utils_num_selected(links) != 1); + + for (i = 0; i < ADI_APOLLO_NUM_JRX_LINKS; i++) { + if ((1 << i) & links) { + link = i%ADI_APOLLO_NUM_JRX_LINKS_PER_SIDE; + regmap_base_addr = calc_jrx_jesd_l0_base(i); + + /* inspect from device registers */ + err = adi_apollo_hal_bf_get(device, BF_JRX_CORE_L_CFG_INFO(regmap_base_addr, link), (uint8_t*) &(jrx_inspect->l_minus1), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_JRX_CORE_F_CFG_INFO(regmap_base_addr, link), (uint8_t*) &(jrx_inspect->f_minus1), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_JRX_CORE_M_CFG_INFO(regmap_base_addr, link), (uint8_t*) &(jrx_inspect->m_minus1), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_JRX_CORE_S_CFG_INFO(regmap_base_addr, link), (uint8_t*) &(jrx_inspect->s_minus1), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_JRX_CORE_N_CFG_INFO(regmap_base_addr, link), (uint8_t*) &(jrx_inspect->n_minus1), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_JRX_CORE_NP_CFG_INFO(regmap_base_addr, link), (uint8_t*) &(jrx_inspect->np_minus1), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_JRX_CORE_K_CFG_INFO(regmap_base_addr, link), &(jrx_inspect->k_minus1), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_JRX_CORE_CS_CFG_INFO(regmap_base_addr, link), (uint8_t*) &(jrx_inspect->cs), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_JRX_CORE_SUBCLASSV_CFG_INFO(regmap_base_addr, link), &(jrx_inspect->subclass), 1); + ADI_APOLLO_ERROR_RETURN(err); + + /* get link enable state */ + regmap_base_addr = calc_jrx_wrapper_base(i); + err = adi_apollo_hal_bf_get(device, BF_LINK_EN_INFO(regmap_base_addr), &link_enable, 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_JESD_MODE_INFO(regmap_base_addr, link), (uint8_t *) &(jrx_inspect->jesd_mode), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_READBACK_JRX_NS_PARAM_INFO(regmap_base_addr, link), (uint8_t *)&(jrx_inspect->ns_minus1), 1); + ADI_APOLLO_ERROR_RETURN(err); + + if (i % ADI_APOLLO_NUM_JRX_LINKS_PER_SIDE == 0) { + jrx_inspect->link_en = (link_enable & 0x01) != 0 ? 1 : 0; + } else { + jrx_inspect->link_en = (link_enable & 0x02) != 0 ? 1 : 0; + } + + regmap_base_addr = calc_jrx_core_base(i); + err = adi_apollo_hal_bf_get(device, BF_JRX_LINK_TYPE_INFO(regmap_base_addr), (uint8_t *) &(jrx_inspect->ver), 1); + ADI_APOLLO_ERROR_RETURN(err); + + /* Only one inspect per call */ + break; + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_jrx_phase_adjust_set(adi_apollo_device_t* device, + const uint16_t links, + const uint16_t phase_adjust) +{ + int32_t err; + uint32_t regmap_base_addr = 0; + uint8_t i; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + for (i = 0; i < ADI_APOLLO_NUM_JRX_LINKS; i++) { + if ((1 << i) & links) { + regmap_base_addr = calc_jrx_core_base(i); + + err = adi_apollo_hal_bf_set(device, BF_JRX_CORE_PHASE_ADJUST_INFO_LSB(regmap_base_addr, (i % ADI_APOLLO_NUM_JRX_LINKS_PER_SIDE)), (uint8_t)phase_adjust); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_JRX_CORE_PHASE_ADJUST_INFO_MSB(regmap_base_addr, (i % ADI_APOLLO_NUM_JRX_LINKS_PER_SIDE)), (uint8_t)(phase_adjust >> 8)); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_jrx_phase_adjust_get(adi_apollo_device_t *device, + const uint16_t links, + uint16_t *phase_adjust) +{ + int32_t err; + uint32_t regmap_base_addr = 0; + uint8_t i; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(phase_adjust); + ADI_APOLLO_INVALID_PARAM_RETURN(adi_api_utils_num_selected(links) != 1); + + for (i = 0; i < ADI_APOLLO_NUM_JRX_LINKS; i++) { + if ((1 << i) & links) { + regmap_base_addr = calc_jrx_core_base(i); + + err = adi_apollo_hal_reg_get(device, REG_JRX_CORE_PHASE_ADJUST0_ADDR(regmap_base_addr, i % ADI_APOLLO_NUM_JRX_LINKS_PER_SIDE), ((uint8_t *)phase_adjust + 0)); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_reg_get(device, REG_JRX_CORE_PHASE_ADJUST1_ADDR(regmap_base_addr, i % ADI_APOLLO_NUM_JRX_LINKS_PER_SIDE), ((uint8_t *)phase_adjust + 1)); + ADI_APOLLO_ERROR_RETURN(err); + + break; // single value per call + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_jrx_phase_adjust_calc(adi_apollo_device_t *device, const uint16_t links, uint16_t margin, uint16_t *phase_adjust) +{ + int32_t err = API_CMS_ERROR_OK; + uint16_t jrx_phase_diff0, jrx_phase_diff1; + uint16_t max_jrx_core_phase_diff; + uint16_t lmfc_period; + adi_apollo_jesd_rx_inspect_t jrx_status; + int16_t phase_diff; + uint16_t abs_phase_diff; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(phase_adjust); + + /* Function currently only supporting single link per side */ + if (links != (ADI_APOLLO_LINK_A0 | ADI_APOLLO_LINK_B0)) { + ADI_APOLLO_LOG_ERR("Phase adjust calc support for LINKs A0 & B0 only"); + return API_CMS_ERROR_NOT_SUPPORTED; + } + + err = adi_apollo_jrx_link_inspect(device, ADI_APOLLO_LINK_A0, &jrx_status); + ADI_APOLLO_ERROR_RETURN(err); + + if ((jrx_status.ns_minus1 + 1) == 0) { + ADI_APOLLO_ERROR_RETURN(API_CMS_ERROR_DIV_BY_ZERO); + } + + lmfc_period = ((jrx_status.k_minus1 + 1) * (jrx_status.s_minus1 + 1)) / (jrx_status.ns_minus1 + 1); + + err = adi_apollo_jrx_phase_diff_get(device, ADI_APOLLO_LINK_A0, &jrx_phase_diff0); + ADI_APOLLO_ERROR_RETURN(err); + + err =adi_apollo_jrx_phase_diff_get(device, ADI_APOLLO_LINK_B0, &jrx_phase_diff1); + ADI_APOLLO_ERROR_RETURN(err); + + phase_diff = (jrx_phase_diff0 - jrx_phase_diff1); + abs_phase_diff = (phase_diff < 0) ? -phase_diff : phase_diff; + if (abs_phase_diff < (lmfc_period / 2)) { + max_jrx_core_phase_diff = ADI_UTILS_MAX(jrx_phase_diff0, jrx_phase_diff1); + } else { + max_jrx_core_phase_diff = ADI_UTILS_MIN(jrx_phase_diff0, jrx_phase_diff1); + } + + *phase_adjust = (max_jrx_core_phase_diff + margin) % lmfc_period; + + return err; +} + +int32_t adi_apollo_jrx_phase_diff_get(adi_apollo_device_t* device, + const uint16_t links, + uint16_t *phase_diff) +{ + int32_t err; + uint32_t regmap_base_addr = 0; + uint8_t i; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(phase_diff); + ADI_APOLLO_INVALID_PARAM_RETURN(adi_api_utils_num_selected(links) != 1); + + for (i = 0; i < ADI_APOLLO_NUM_JRX_LINKS; i++) { + if ((1 << i) & links) { + regmap_base_addr = calc_jrx_core_base(i); + + err = adi_apollo_hal_reg_get(device, REG_JRX_CORE_LANE_PHASE_DIFF_0_ADDR(regmap_base_addr, i % ADI_APOLLO_NUM_JRX_LINKS_PER_SIDE), ((uint8_t *)phase_diff+0)); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_reg_get(device, REG_JRX_CORE_LANE_PHASE_DIFF_1_ADDR(regmap_base_addr, i % ADI_APOLLO_NUM_JRX_LINKS_PER_SIDE), ((uint8_t*)phase_diff+1)); + ADI_APOLLO_ERROR_RETURN(err); + + break; // single value per call + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_jrx_lane_xbar_set(adi_apollo_device_t *device, + const uint16_t links, + uint8_t physical_lane, + uint8_t logical_lane) +{ + int32_t err, i; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(physical_lane > ADI_APOLLO_JRX_LANES_MAX-1); + + for (i = 0; i < ADI_APOLLO_NUM_JRX_LINKS; i++) { + if ((1 << i) & links) { + + regmap_base_addr = calc_jrx_core_base(i); + + if ((i % ADI_APOLLO_NUM_JRX_LINKS_PER_SIDE) == 0) { + err = adi_apollo_hal_bf_set(device, BF_JRX_CORE_LANE_SEL_LINK0_INFO(regmap_base_addr, physical_lane), logical_lane); /* Link 0 */ + } else { + err = adi_apollo_hal_bf_set(device, BF_JRX_CORE_LANE_SEL_LINK1_INFO(regmap_base_addr, physical_lane), logical_lane); /* Link 1*/ + } + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_jrx_lanes_xbar_set(adi_apollo_device_t *device, + const uint16_t links, + uint8_t logical_lanes[], + uint32_t length) +{ + int32_t err, i; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(length > ADI_APOLLO_JRX_LANES_MAX); + + for (i = 0; i < length; i++) { + err = adi_apollo_jrx_lane_xbar_set(device, links, i, logical_lanes[i]); + ADI_APOLLO_ERROR_RETURN(err); + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_jrx_j204c_irq_enable_set(adi_apollo_device_t *device, + const uint16_t links, + const uint32_t irqs, uint8_t enable) +{ + int32_t err, link_idx, irq_idx; + uint32_t regmap_base_addr = 0, address, info; + uint16_t link; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(enable > 1); + + for (link_idx = 0; link_idx < ADI_APOLLO_NUM_JRX_LINKS; link_idx++) { + link = (1 << link_idx) & links; + if (link > 0) { + regmap_base_addr = calc_jrx_wrapper_base(link_idx); + for (irq_idx = 0; irq_idx < ADI_APOLLO_JRX_J204C_IRQ_NUM; irq_idx++) { + if (irqs & (1 << irq_idx)) { + calc_j204c_irq_en(regmap_base_addr, link_idx, irq_idx, &address, &info); + err = adi_apollo_hal_bf_set(device, address, info, enable); + ADI_APOLLO_ERROR_RETURN(err); + + calc_j204c_irq(regmap_base_addr, link_idx, irq_idx, &address, &info); + err = adi_apollo_hal_bf_set(device, address, info, 0); + ADI_APOLLO_ERROR_RETURN(err); + } + } + } + } + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_jrx_j204c_irq_enable_get(adi_apollo_device_t *device, + const uint16_t links, + uint32_t *irqs_enabled) +{ + int32_t err, link_idx, irq_idx; + uint32_t regmap_base_addr = 0, address, info; + uint16_t link; + uint8_t single_status; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(irqs_enabled); + ADI_APOLLO_INVALID_PARAM_RETURN(adi_api_utils_num_selected(links) != 1); + + *irqs_enabled = 0; + + for (link_idx = 0; link_idx < ADI_APOLLO_NUM_JRX_LINKS; link_idx++) { + link = (1 << link_idx) & links; + if (link > 0) { + regmap_base_addr = calc_jrx_wrapper_base(link_idx); + for (irq_idx = 0; irq_idx < ADI_APOLLO_JRX_J204C_IRQ_NUM; irq_idx++) { + calc_j204c_irq_en(regmap_base_addr, link_idx, irq_idx, &address, &info); + err = adi_apollo_hal_bf_get(device, address, info, &single_status, 1); + ADI_APOLLO_ERROR_RETURN(err); + if (single_status) { + *irqs_enabled = *irqs_enabled | (1 << irq_idx); + } + } + } + } + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_jrx_j204c_irq_get(adi_apollo_device_t *device, + const uint16_t links, + const uint32_t irqs, uint8_t clear, uint32_t *status) +{ + int32_t err, link_idx, irq_idx; + uint32_t regmap_base_addr = 0, address, info; + uint16_t link; + uint8_t single_status; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(status); + + *status = 0; + + for (link_idx = 0; link_idx < ADI_APOLLO_NUM_JRX_LINKS; link_idx++) { + link = (1 << link_idx) & links; + if (link > 0) { + regmap_base_addr = calc_jrx_wrapper_base(link_idx); + for (irq_idx = 0; irq_idx < ADI_APOLLO_JRX_J204C_IRQ_NUM; irq_idx++) { + if (irqs & (1 << irq_idx)) { + calc_j204c_irq(regmap_base_addr, link_idx, irq_idx, &address, &info); + err = adi_apollo_hal_bf_get(device, address, info, &single_status, 1); + ADI_APOLLO_ERROR_RETURN(err); + if (single_status) { + *status = *status | (1 << irq_idx); + } + } + } + } + } + + if (clear) { + err = adi_apollo_jrx_j204c_irq_clear(device, links, irqs); + ADI_APOLLO_ERROR_RETURN(err); + } + + return err; +} + +int32_t adi_apollo_jrx_j204c_irq_clear(adi_apollo_device_t *device, + const uint16_t links, + const uint32_t irqs) +{ + int32_t err, link_idx, irq_idx; + uint32_t regmap_base_addr = 0, address, info; + uint16_t link; + uint32_t jrx_dl_204c_instance; + uint8_t single_status; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + for (link_idx = 0; link_idx < ADI_APOLLO_NUM_JRX_LINKS; link_idx++) { + link = (1 << link_idx) & links; + if (link > 0) { + regmap_base_addr = calc_jrx_wrapper_base(link_idx); + for (irq_idx = 0; irq_idx < ADI_APOLLO_JRX_J204C_IRQ_NUM; irq_idx++) { + if (irqs & (1 << irq_idx)) { + calc_j204c_irq(regmap_base_addr, link_idx, irq_idx, &address, &info); + err = adi_apollo_hal_bf_get(device, address, info, &single_status, 1); + ADI_APOLLO_ERROR_RETURN(err); + if (single_status) { + if (irq_idx == 0) { // For CRC, must clear the error count BEFORE clearing IRQ status + jrx_dl_204c_instance = calc_jrx_dl_204c_base(link_idx); + err = adi_apollo_hal_bf_set(device, BF_JRX_DL_204C_CLR_ERR_CNT_INFO(jrx_dl_204c_instance), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_JRX_DL_204C_CLR_ERR_CNT_INFO(jrx_dl_204c_instance), 0); + ADI_APOLLO_ERROR_RETURN(err); + } + err = adi_apollo_hal_bf_set(device, address, info, 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, address, info, 0); + ADI_APOLLO_ERROR_RETURN(err); + } + } + } + } + } + + return API_CMS_ERROR_OK; +} +int32_t adi_apollo_jrx_lr_adapt_set(adi_apollo_device_t *device, + uint8_t link_sides, + uint8_t physical_lane, + uint8_t lr_adapt) +{ + int32_t err, i; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(link_sides > ADI_APOLLO_LINK_SIDE_ALL); + ADI_APOLLO_INVALID_PARAM_RETURN(physical_lane > ADI_APOLLO_JRX_LANES_MAX - 1); + ADI_APOLLO_INVALID_PARAM_RETURN(lr_adapt > ADI_APOLLO_SERDES_LR_ADAPT_RATIO_4); + + for (i = 0; i < ADI_APOLLO_NUM_JRX_LINKS; i += ADI_APOLLO_NUM_JRX_LINKS_PER_SIDE) { + if ((1 << i) & link_sides) { + regmap_base_addr = calc_jrx_phy_ifx_base(i); + err = adi_apollo_hal_bf_set(device, BF_JRX_IFX_LOG2_SPLIT_INFO(regmap_base_addr, physical_lane), lr_adapt); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +/*==================== L O C A L A P I C O D E ====================*/ + +int32_t adi_apollo_jesd_rx_sample_repeat_en(adi_apollo_device_t *device, + const uint16_t link_sides, + uint8_t enable) +{ + int32_t err, i; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(enable > 0x1); + + for (i = 0; i < ADI_APOLLO_NUM_JTX_LINKS; i++) { + if ((1 << i) & link_sides) { + regmap_base_addr = calc_jrx_wrapper_base(i); + err = adi_apollo_hal_bf_set(device, BF_SAMPLE_REPEAT_EN_INFO(regmap_base_addr, (i % ADI_APOLLO_NUM_JRX_LINKS_PER_SIDE)), enable); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +static uint32_t calc_jrx_core_base(int32_t link) +{ + return ((link / ADI_APOLLO_NUM_JRX_LINKS_PER_SIDE) == 0) ? JRX_CORE_JRX_TX_DIGITAL0 : JRX_CORE_JRX_TX_DIGITAL1; +} + +static uint32_t calc_jrx_wrapper_base(int32_t link) +{ + return ((link / ADI_APOLLO_NUM_JRX_LINKS_PER_SIDE) == 0) ? JRX_WRAPPER_JRX_TX_DIGITAL0 : JRX_WRAPPER_JRX_TX_DIGITAL1; +} + +static uint32_t calc_jrx_dl_204c_base(int32_t link) +{ + return ((link/ADI_APOLLO_NUM_JRX_LINKS_PER_SIDE) == 0) ? JRX_DL_204C_JRX_TX_DIGITAL0 : JRX_DL_204C_JRX_TX_DIGITAL1; +} + +static uint32_t calc_jrx_dl_204b_base(int32_t link) +{ + return ((link/ADI_APOLLO_NUM_JRX_LINKS_PER_SIDE) == 0) ? JRX_DL_204B_JRX_TX_DIGITAL0 : JRX_DL_204B_JRX_TX_DIGITAL1; +} + +static uint32_t calc_jrx_jesd_l0_base(int32_t link) +{ + return ((link/ADI_APOLLO_NUM_JRX_LINKS_PER_SIDE) == 0) ? JRX_JESD_L0_JRX_TX_DIGITAL0 : JRX_JESD_L0_JRX_TX_DIGITAL1; +} + +static void calc_j204c_irq_en(uint32_t base, int32_t link, uint32_t idx, uint32_t *address, uint32_t *info) +{ + uint32_t j204c_irq_map[ADI_APOLLO_JRX_J204C_IRQ_NUM * 2] = { + BF_JRX_204C_CRC_IRQ_ENABLE_INFO(base, (link % ADI_APOLLO_NUM_JRX_LINKS_PER_SIDE)), + BF_JRX_204C_SH_IRQ_ENABLE_INFO(base, (link % ADI_APOLLO_NUM_JRX_LINKS_PER_SIDE)), + BF_JRX_204C_MB_IRQ_ENABLE_INFO(base, (link % ADI_APOLLO_NUM_JRX_LINKS_PER_SIDE)), + BF_JRX_204C_EMB_IRQ_ENABLE_INFO(base, (link % ADI_APOLLO_NUM_JRX_LINKS_PER_SIDE)), + BF_DATA_RDY_LOST_IRQ_ENABLE_INFO(base, (link % ADI_APOLLO_NUM_JRX_LINKS_PER_SIDE)), + BF_RM_FIFO_EMPTY_IRQ_ENABLE_INFO(base, (link % ADI_APOLLO_NUM_JRX_LINKS_PER_SIDE)), + BF_RM_FIFO_FULL_IRQ_ENABLE_INFO(base, (link % ADI_APOLLO_NUM_JRX_LINKS_PER_SIDE)), + BF_JRX_LANE_FIFO_EMPTY_IRQ_ENABLE_INFO(base, (link % ADI_APOLLO_NUM_JRX_LINKS_PER_SIDE)), + BF_JRX_LANE_FIFO_FULL_IRQ_ENABLE_INFO(base, (link % ADI_APOLLO_NUM_JRX_LINKS_PER_SIDE)), + BF_INVALID_SAMPLE_ERR_IRQ_ENABLE_INFO(base, (link % ADI_APOLLO_NUM_JRX_LINKS_PER_SIDE)) + }; + + *address = j204c_irq_map[idx * 2]; + *info = j204c_irq_map[idx * 2 + 1]; +} + +static void calc_j204c_irq(uint32_t base, int32_t link, uint32_t idx, uint32_t *address, uint32_t *info) +{ + uint32_t j204c_irq_map[ADI_APOLLO_JRX_J204C_IRQ_NUM * 2] = { + BF_JRX_204C_CRC_IRQ_INFO(base, (link % ADI_APOLLO_NUM_JRX_LINKS_PER_SIDE)), + BF_JRX_204C_SH_IRQ_INFO(base, (link % ADI_APOLLO_NUM_JRX_LINKS_PER_SIDE)), + BF_JRX_204C_MB_IRQ_INFO(base, (link % ADI_APOLLO_NUM_JRX_LINKS_PER_SIDE)), + BF_JRX_204C_EMB_IRQ_INFO(base, (link % ADI_APOLLO_NUM_JRX_LINKS_PER_SIDE)), + BF_DATA_RDY_LOST_IRQ_INFO(base, (link % ADI_APOLLO_NUM_JRX_LINKS_PER_SIDE)), + BF_RM_FIFO_EMPTY_IRQ_INFO(base, (link % ADI_APOLLO_NUM_JRX_LINKS_PER_SIDE)), + BF_RM_FIFO_FULL_IRQ_INFO(base, (link % ADI_APOLLO_NUM_JRX_LINKS_PER_SIDE)), + BF_JRX_LANE_FIFO_EMPTY_IRQ_INFO(base, (link % ADI_APOLLO_NUM_JRX_LINKS_PER_SIDE)), + BF_JRX_LANE_FIFO_FULL_IRQ_INFO(base, (link % ADI_APOLLO_NUM_JRX_LINKS_PER_SIDE)), + BF_INVALID_SAMPLE_ERR_IRQ_INFO(base, (link % ADI_APOLLO_NUM_JRX_LINKS_PER_SIDE)) + }; + + *address = j204c_irq_map[idx * 2]; + *info = j204c_irq_map[idx * 2 + 1]; +} + +static uint32_t calc_jrx_phy_ifx_base(int32_t link) +{ + return ((link / ADI_APOLLO_NUM_JRX_LINKS_PER_SIDE) == 0) ? JRX_PHY_IFX_JRX_TX_DIGITAL0 : JRX_PHY_IFX_JRX_TX_DIGITAL1; +} +/*! @} */ \ No newline at end of file diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_jtx.c b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_jtx.c new file mode 100644 index 00000000000000..31eb96e57a46fc --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_jtx.c @@ -0,0 +1,786 @@ +/*! + * \brief APIs for JTx + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_JTX + * @{ + */ + +/*============= I N C L U D E S ============*/ +#include "adi_utils.h" +#include "adi_apollo_jtx.h" +#include "adi_apollo_dformat_local.h" + +#include "adi_apollo_bf_jtx_dformat.h" +#include "adi_apollo_bf_jtx_dual_link.h" +#include "adi_apollo_bf_jtx_qbf_txfe.h" +#include "adi_apollo_bf_serdes_txdig_phy_core1p2.h" + +#include "adi_apollo_mailbox.h" +#include "adi_apollo_config.h" +#include "adi_apollo_hal.h" + +/*============= D E F I N E S ==============*/ +#define ADI_APOLLO_JTX_LANES_MAX 12 +#define ADI_APOLLO_SERDES_TX_DRIVE_SWING_STRUCT 0 +#define ADI_APOLLO_SERDES_TX_PRE_EMPHASIS_STRUCT 1 +#define ADI_APOLLO_SERDES_TX_POST_EMPHASIS_STRUCT 2 +#define ADI_APOLLO_SERDES_TX_SWING_EMPHASIS_STRUCT 3 +#define ADI_APOLLO_SERDES_TX_LANES_SWING_EMPHASIS_STRUCT 4 + +/*==================== P U B L I C A P I C O D E ====================*/ + +int32_t adi_apollo_jtx_link_enable_set(adi_apollo_device_t *device, const uint16_t links, + uint8_t link_en) +{ + int32_t err, i; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(link_en > 1); + + for (i = 0; i < ADI_APOLLO_NUM_JTX_LINKS; i++) { + if ((1 << i) & links) { + regmap_base_addr = calc_jtx_dual_link_base(i); + err = adi_apollo_hal_bf_set(device, BF_JTX_LINK_EN_INFO(regmap_base_addr), link_en); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_jtx_link_status_get(adi_apollo_device_t *device, + const uint16_t link, + uint16_t *status) +{ + int32_t err, i, link_count, link_index; + uint32_t regmap_base_addr = 0; + uint16_t res; + uint8_t reg8; + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(status); + + link_count = 0; + link_index = 0; + for (i = 0; i < ADI_APOLLO_NUM_JTX_LINKS; i++) { + if ((1 << i) & link) { + /*Reading status for only one link*/ + link_count++; + ADI_APOLLO_INVALID_PARAM_RETURN(link_count > 1); + link_index = i; + } + } + + if (((1 << link_index) & link)) { + + regmap_base_addr = calc_jtx_dual_link_base(link_index); + + err = adi_apollo_hal_bf_get(device, BF_JTX_SYNC_N_SEL_INFO(regmap_base_addr), ®8, 1); /* QBF status */ + ADI_APOLLO_ERROR_RETURN(err); + res = reg8 & 0x0F; + + err = adi_apollo_hal_bf_get(device, BF_JTX_DL_204B_SYNC_N_INFO(regmap_base_addr), ®8, 1); /* frame sync */ + ADI_APOLLO_ERROR_RETURN(err); + res += (reg8 & 0x1) << 4; + + /* PLL status applicable for only link0 registers*/ + regmap_base_addr = calc_jtx_qbf_txfe_base(link_index == 1 ? 0 : link_index == 3 ? 2 : link_index); + + err = adi_apollo_hal_bf_get(device, BF_JTX_PLL_LOCKED_INFO(regmap_base_addr), ®8, 1); /* PLL status */ + ADI_APOLLO_ERROR_RETURN(err); + res += (reg8 & 0x1) << 5; + + regmap_base_addr = calc_jtx_qbf_txfe_base(link_index); + + err = adi_apollo_hal_bf_get(device, BF_JTX_PHASE_ESTABLISHED_INFO(regmap_base_addr), ®8, 1); /* Phase Established Readback */ + ADI_APOLLO_ERROR_RETURN(err); + res += (reg8 & 0x1) << 6; + + err = adi_apollo_hal_bf_get(device, BF_JTX_INVALID_MODE_INFO(regmap_base_addr), ®8, 1); /* Invalid Mode */ + ADI_APOLLO_ERROR_RETURN(err); + res += (reg8 & 0x1) << 7; + } + *status = res; + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_jtx_link_inspect(adi_apollo_device_t *device, + const uint16_t links, + adi_apollo_jesd_tx_inspect_t *jtx_inspect) +{ + int32_t err; + uint32_t regmap_base_addr = 0; + uint8_t i; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(jtx_inspect); + ADI_APOLLO_INVALID_PARAM_RETURN(adi_api_utils_num_selected(links) != 1); + + for (i = 0; i < ADI_APOLLO_NUM_JTX_LINKS; i++) { + if ((1 << i) & links) { + regmap_base_addr = calc_jtx_jesd_param_base(i); + + err = adi_apollo_hal_bf_get(device, BF_JTX_L_CFG_INFO(regmap_base_addr), (uint8_t* )&(jtx_inspect->l_minus1), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_JTX_F_CFG_INFO(regmap_base_addr), (uint8_t*) &(jtx_inspect->f_minus1), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_JTX_M_CFG_INFO(regmap_base_addr), (uint8_t*) &(jtx_inspect->m_minus1), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_JTX_S_CFG_INFO(regmap_base_addr), (uint8_t*) &(jtx_inspect->s_minus1), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_JTX_N_CFG_INFO(regmap_base_addr), (uint8_t*) &(jtx_inspect->n_minus1), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_JTX_NP_CFG_INFO(regmap_base_addr), (uint8_t*) &(jtx_inspect->np_minus1), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_JTX_K_CFG_INFO(regmap_base_addr), &(jtx_inspect->k_minus1), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_JTX_CS_CFG_INFO(regmap_base_addr), (uint8_t*) &(jtx_inspect->cs), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_JTX_SUBCLASSV_CFG_INFO(regmap_base_addr), &(jtx_inspect->subclass), 1); + ADI_APOLLO_ERROR_RETURN(err); + + regmap_base_addr = calc_jtx_dual_link_base(i); + err = adi_apollo_hal_bf_get(device, BF_JTX_LINK_EN_INFO(regmap_base_addr), &(jtx_inspect->link_en), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_JTX_NS_CFG_INFO(regmap_base_addr), (uint8_t*) &(jtx_inspect->ns_minus1), 1); + ADI_APOLLO_ERROR_RETURN(err); + + regmap_base_addr = calc_jtx_dual_link_base((i/2)*2); // bf only valid on link A0/B0 + err = adi_apollo_hal_bf_get(device, BF_JTX_LINK_204C_SEL_INFO(regmap_base_addr), (uint8_t*)&(jtx_inspect->ver), 1); + ADI_APOLLO_ERROR_RETURN(err); + + regmap_base_addr = calc_jtx_qbf_txfe_base(i); + err = adi_apollo_hal_bf_get(device, BF_JTX_MODE_INFO(regmap_base_addr), (uint8_t*) &(jtx_inspect->jesd_mode), 1); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_jtx_phase_adjust_set(adi_apollo_device_t* device, + const uint16_t links, + const uint16_t phase_adjust) +{ + int32_t err; + uint32_t regmap_base_addr = 0; + uint8_t i; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + for (i = 0; i < ADI_APOLLO_NUM_JTX_LINKS; i++) { + if ((1 << i) & links) { + + if ((1 << i) & links) { + regmap_base_addr = calc_jtx_dual_link_base(i); + + err = adi_apollo_hal_bf_set(device, BF_JTX_TPL_PHASE_ADJUST_INFO(regmap_base_addr), (uint8_t)phase_adjust); + ADI_APOLLO_ERROR_RETURN(err); + } + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_jtx_subclass_set(adi_apollo_device_t *device, + const uint16_t links, + const uint16_t subclass) +{ + int32_t err; + uint32_t regmap_base_addr = 0; + uint8_t i; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + for (i = 0; i < ADI_APOLLO_NUM_JTX_LINKS; i++) { + if ((1 << i) & links) { + + if ((1 << i) & links) { + regmap_base_addr = calc_jtx_dual_link_base(i); + + err = adi_apollo_hal_bf_set(device, BF_JTX_SUBCLASSV_CFG_INFO(regmap_base_addr), subclass); + ADI_APOLLO_ERROR_RETURN(err); + } + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_jtx_lane_xbar_set(adi_apollo_device_t *device, + const uint16_t links, + uint8_t physical_lane, uint8_t logical_lane) +{ + int32_t err, i; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(logical_lane > ADI_APOLLO_JTX_LANES_MAX-1); + ADI_APOLLO_INVALID_PARAM_RETURN(physical_lane > ADI_APOLLO_JTX_LANES_MAX-1); + + for (i = 0; i < ADI_APOLLO_NUM_JTX_LINKS; i++) { + if ((1 << i) & links) { + regmap_base_addr = calc_jtx_dual_link_base(i); + err = adi_apollo_hal_bf_set(device, BF_JTX_LANE_ASSIGN_INFO(regmap_base_addr, physical_lane), logical_lane); + ADI_APOLLO_ERROR_RETURN(err); + } + } + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_jtx_lanes_xbar_set(adi_apollo_device_t *device, const uint16_t links, + uint8_t logical_lanes[], uint32_t length) +{ + int32_t err, i; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(length > ADI_APOLLO_JTX_LANES_MAX); + + for (i = 0; i < length; i++) { + err = adi_apollo_jtx_lane_xbar_set(device, links, i, logical_lanes[i]); + ADI_APOLLO_ERROR_RETURN(err); + } + + return API_CMS_ERROR_OK; +} + + +int32_t adi_apollo_jtx_lane_drive_swing_set(adi_apollo_device_t *device, + uint8_t link_sides, + uint8_t physical_lane, + uint8_t drive_swing) +{ + adi_apollo_mailbox_cmd_set_ctrl_t set_ctrl_cmd = { + .sys_cal_object_id = APOLLO_CPU_OBJID_IC_SERDES_TX, + .ctrl_cmd = CTRL_CMD_PARAM_SET, + .data_buffer[0] = ADI_APOLLO_SERDES_TX_DRIVE_SWING_STRUCT, + .data_buffer[1] = 0, + .data_buffer[2] = 0, + .data_buffer[3] = 0, + .data_buffer[4] = physical_lane, + .data_buffer[5] = drive_swing, + .data_buffer[6] = 0, + .data_buffer[7] = 0, + .length = 8 + }; + + adi_apollo_mailbox_resp_set_ctrl_t set_ctrl_resp; + int32_t err, i; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(link_sides > ADI_APOLLO_LINK_SIDE_ALL); + ADI_APOLLO_INVALID_PARAM_RETURN(physical_lane > ADI_APOLLO_JTX_LANES_MAX-1); + ADI_APOLLO_INVALID_PARAM_RETURN(drive_swing > ADI_APOLLO_SER_SWING_500); + + for (i = 0; i < ADI_APOLLO_NUM_JTX_LINKS; i += ADI_APOLLO_NUM_JTX_LINKS_PER_SIDE) { + if ((1 << i) & link_sides) { + set_ctrl_cmd.channel_num = (i >> 1); // 0 for side A and 1 for side B + + err = adi_apollo_mailbox_set_ctrl(device, &set_ctrl_cmd, &set_ctrl_resp); + if (err != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Error from adi_apollo_mailbox_set_ctrl() %d", err); + return err; + } + + if (set_ctrl_resp.status != API_CMS_ERROR_OK){ + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Mailbox Response Status Error from adi_apollo_mailbox_set_ctrl() 0x%X", set_ctrl_resp.status); + return API_CMS_ERROR_ERROR; + } + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_jtx_lane_pre_emphasis_set(adi_apollo_device_t *device, + uint8_t link_sides, + uint8_t physical_lane, + uint8_t pre_emp) +{ + adi_apollo_mailbox_cmd_set_ctrl_t set_ctrl_cmd = { + .sys_cal_object_id = APOLLO_CPU_OBJID_IC_SERDES_TX, + .ctrl_cmd = CTRL_CMD_PARAM_SET, + .data_buffer[0] = ADI_APOLLO_SERDES_TX_PRE_EMPHASIS_STRUCT, + .data_buffer[1] = 0, + .data_buffer[2] = 0, + .data_buffer[3] = 0, + .data_buffer[4] = physical_lane, + .data_buffer[5] = pre_emp, + .data_buffer[6] = 0, + .data_buffer[7] = 0, + .length = 8 + }; + + adi_apollo_mailbox_resp_set_ctrl_t set_ctrl_resp; + int32_t err, i; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(link_sides > ADI_APOLLO_LINK_SIDE_ALL); + ADI_APOLLO_INVALID_PARAM_RETURN(physical_lane > ADI_APOLLO_JTX_LANES_MAX-1); + ADI_APOLLO_INVALID_PARAM_RETURN(pre_emp > ADI_APOLLO_SER_PRE_EMP_6DB); + + for (i = 0; i < ADI_APOLLO_NUM_JTX_LINKS; i += ADI_APOLLO_NUM_JTX_LINKS_PER_SIDE) { + if ((1 << i) & link_sides) { + set_ctrl_cmd.channel_num = (i >> 1); // 0 for side A and 1 for side B + + err = adi_apollo_mailbox_set_ctrl(device, &set_ctrl_cmd, &set_ctrl_resp); + if (err != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Error from adi_apollo_mailbox_set_ctrl() %d", err); + return err; + } + + if (set_ctrl_resp.status != API_CMS_ERROR_OK){ + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Mailbox Response Status Error from adi_apollo_mailbox_set_ctrl() 0x%X", set_ctrl_resp.status); + return API_CMS_ERROR_ERROR; + } + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_jtx_lane_post_emphasis_set(adi_apollo_device_t *device, + uint8_t link_sides, + uint8_t physical_lane, + uint8_t post_emp) +{ + adi_apollo_mailbox_cmd_set_ctrl_t set_ctrl_cmd = { + .sys_cal_object_id = APOLLO_CPU_OBJID_IC_SERDES_TX, + .ctrl_cmd = CTRL_CMD_PARAM_SET, + .data_buffer[0] = ADI_APOLLO_SERDES_TX_POST_EMPHASIS_STRUCT, + .data_buffer[1] = 0, + .data_buffer[2] = 0, + .data_buffer[3] = 0, + .data_buffer[4] = physical_lane, + .data_buffer[5] = post_emp, + .data_buffer[6] = 0, + .data_buffer[7] = 0, + .length = 8 + }; + + adi_apollo_mailbox_resp_set_ctrl_t set_ctrl_resp; + int32_t err, i; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(link_sides > ADI_APOLLO_LINK_SIDE_ALL); + ADI_APOLLO_INVALID_PARAM_RETURN(physical_lane > ADI_APOLLO_JTX_LANES_MAX-1); + ADI_APOLLO_INVALID_PARAM_RETURN(post_emp > ADI_APOLLO_SER_POST_EMP_12DB); + + for (i = 0; i < ADI_APOLLO_NUM_JTX_LINKS; i += ADI_APOLLO_NUM_JTX_LINKS_PER_SIDE) { + if ((1 << i) & link_sides) { + set_ctrl_cmd.channel_num = (i >> 1); // 0 for side A and 1 for side B + + err = adi_apollo_mailbox_set_ctrl(device, &set_ctrl_cmd, &set_ctrl_resp); + if (err != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Error from adi_apollo_mailbox_set_ctrl() %d", err); + return err; + } + + if (set_ctrl_resp.status != API_CMS_ERROR_OK){ + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Mailbox Response Status Error from adi_apollo_mailbox_set_ctrl() 0x%X", set_ctrl_resp.status); + return API_CMS_ERROR_ERROR; + } + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_jtx_multi_lane_swing_emphasis_set(adi_apollo_device_t *device, + uint8_t link_sides, + uint8_t* physical_lane, + uint8_t* drive_swing, + uint8_t* pre_emp, + uint8_t* post_emp, + uint32_t num_lanes) +{ + adi_apollo_mailbox_cmd_set_ctrl_t set_ctrl_cmd = { + .sys_cal_object_id = APOLLO_CPU_OBJID_IC_SERDES_TX, + .ctrl_cmd = CTRL_CMD_PARAM_SET, + .data_buffer[0] = ADI_APOLLO_SERDES_TX_LANES_SWING_EMPHASIS_STRUCT, + .data_buffer[1] = 0, + .data_buffer[2] = 0, + .data_buffer[3] = 0, + .length = 4 + (num_lanes * 4) + }; + + + adi_apollo_mailbox_resp_set_ctrl_t set_ctrl_resp; + int32_t err, i; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(link_sides > ADI_APOLLO_LINK_SIDE_ALL); + ADI_APOLLO_INVALID_PARAM_RETURN(num_lanes > ADI_APOLLO_JTX_LANES_MAX); + + for (int i = 0; i < num_lanes; i++) { + ADI_APOLLO_INVALID_PARAM_RETURN(physical_lane[i] > ADI_APOLLO_JTX_LANES_MAX-1); + ADI_APOLLO_INVALID_PARAM_RETURN(drive_swing[i] > ADI_APOLLO_SER_SWING_500); + ADI_APOLLO_INVALID_PARAM_RETURN(pre_emp[i] > ADI_APOLLO_SER_PRE_EMP_6DB); + ADI_APOLLO_INVALID_PARAM_RETURN(post_emp[i] > ADI_APOLLO_SER_POST_EMP_12DB); + set_ctrl_cmd.data_buffer[4 + (i*4)] = physical_lane[i]; + set_ctrl_cmd.data_buffer[5 + (i*4)] = drive_swing[i]; + set_ctrl_cmd.data_buffer[6 + (i*4)] = pre_emp[i]; + set_ctrl_cmd.data_buffer[7 + (i*4)] = post_emp[i]; + } + + for (i = 0; i < ADI_APOLLO_NUM_JTX_LINKS; i += ADI_APOLLO_NUM_JTX_LINKS_PER_SIDE) { + if ((1 << i) & link_sides) { + set_ctrl_cmd.channel_num = (i >> 1); // 0 for side A and 1 for side B + + err = adi_apollo_mailbox_set_ctrl(device, &set_ctrl_cmd, &set_ctrl_resp); + if (err != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Error from adi_apollo_mailbox_set_ctrl() %d", err); + return err; + } + + if (set_ctrl_resp.status != API_CMS_ERROR_OK){ + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Mailbox Response Status Error from adi_apollo_mailbox_set_ctrl() 0x%X", set_ctrl_resp.status); + return API_CMS_ERROR_ERROR; + } + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_jtx_lr_adapt_set(adi_apollo_device_t *device, + uint8_t link_sides, + uint8_t physical_lane, + uint8_t lr_adapt) +{ + int32_t err, i; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(link_sides > ADI_APOLLO_LINK_SIDE_ALL); + ADI_APOLLO_INVALID_PARAM_RETURN(physical_lane > ADI_APOLLO_JTX_LANES_MAX - 1); + ADI_APOLLO_INVALID_PARAM_RETURN(lr_adapt > ADI_APOLLO_SERDES_LR_ADAPT_RATIO_32); + + for (i = 0; i < ADI_APOLLO_NUM_JTX_LINKS; i += ADI_APOLLO_NUM_JTX_LINKS_PER_SIDE) { + if ((1 << i) & link_sides) { + regmap_base_addr = calc_jtx_dual_link_base(i); + err = adi_apollo_hal_bf_set(device, BF_JTX_BR_LOG2_RATIO_INFO(regmap_base_addr, physical_lane), lr_adapt); + ADI_APOLLO_ERROR_RETURN(err); + } + } + return API_CMS_ERROR_OK; +} + + +int32_t adi_apollo_jtx_lane_drive_swing_get(adi_apollo_device_t *device, + uint8_t link_sides, + uint8_t physical_lane, + uint8_t *drive_swing) +{ + adi_apollo_mailbox_cmd_set_ctrl_t set_ctrl_cmd = { + .sys_cal_object_id = APOLLO_CPU_OBJID_IC_SERDES_TX, + .ctrl_cmd = CTRL_CMD_PARAM_GET, + .data_buffer[0] = ADI_APOLLO_SERDES_TX_DRIVE_SWING_STRUCT, + .data_buffer[1] = 0, + .data_buffer[2] = 0, + .data_buffer[3] = 0, + .data_buffer[4] = physical_lane, + .data_buffer[5] = 0, + .data_buffer[6] = 0, + .data_buffer[7] = 0, + .length = 8 + }; + + adi_apollo_mailbox_resp_set_ctrl_t set_ctrl_resp; + int32_t err, i; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(link_sides > ADI_APOLLO_LINK_SIDE_ALL); + ADI_APOLLO_INVALID_PARAM_RETURN(physical_lane > ADI_APOLLO_JTX_LANES_MAX-1); + + for (i = 0; i < ADI_APOLLO_NUM_JTX_LINKS; i += ADI_APOLLO_NUM_JTX_LINKS_PER_SIDE) { + if ((1 << i) & link_sides) { + set_ctrl_cmd.channel_num = (i >> 1); // 0 for side A and 1 for side B + + err = adi_apollo_mailbox_set_ctrl(device, &set_ctrl_cmd, &set_ctrl_resp); + if (err != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Error from adi_apollo_mailbox_set_ctrl() %d", err); + return err; + } + + if (set_ctrl_resp.status != API_CMS_ERROR_OK){ + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Mailbox Response Status Error from adi_apollo_mailbox_set_ctrl() 0x%X", set_ctrl_resp.status); + return API_CMS_ERROR_ERROR; + } + + /* Extract Drive Swing info from response structure + set_ctrl_resp.data_buffer[4] --> physical_lane + set_ctrl_resp.data_buffer[5] --> drive_swing */ + *drive_swing = set_ctrl_resp.data_buffer[5]; + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_jtx_lane_pre_emphasis_get(adi_apollo_device_t *device, + uint8_t link_sides, + uint8_t physical_lane, + uint8_t *pre_emp) +{ + adi_apollo_mailbox_cmd_set_ctrl_t set_ctrl_cmd = { + .sys_cal_object_id = APOLLO_CPU_OBJID_IC_SERDES_TX, + .ctrl_cmd = CTRL_CMD_PARAM_GET, + .data_buffer[0] = ADI_APOLLO_SERDES_TX_PRE_EMPHASIS_STRUCT, + .data_buffer[1] = 0, + .data_buffer[2] = 0, + .data_buffer[3] = 0, + .data_buffer[4] = physical_lane, + .data_buffer[5] = 0, + .data_buffer[6] = 0, + .data_buffer[7] = 0, + .length = 8 + }; + + adi_apollo_mailbox_resp_set_ctrl_t set_ctrl_resp; + int32_t err, i; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(link_sides > ADI_APOLLO_LINK_SIDE_ALL); + ADI_APOLLO_INVALID_PARAM_RETURN(physical_lane > ADI_APOLLO_JTX_LANES_MAX-1); + + for (i = 0; i < ADI_APOLLO_NUM_JTX_LINKS; i += ADI_APOLLO_NUM_JTX_LINKS_PER_SIDE) { + if ((1 << i) & link_sides) { + set_ctrl_cmd.channel_num = (i >> 1); // 0 for side A and 1 for side B + + err = adi_apollo_mailbox_set_ctrl(device, &set_ctrl_cmd, &set_ctrl_resp); + if (err != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Error from adi_apollo_mailbox_set_ctrl() %d", err); + return err; + } + + if (set_ctrl_resp.status != API_CMS_ERROR_OK){ + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Mailbox Response Status Error from adi_apollo_mailbox_set_ctrl() 0x%X", set_ctrl_resp.status); + return API_CMS_ERROR_ERROR; + } + + /* Extract Drive Swing info from response structure + set_ctrl_resp.data_buffer[4] --> physical_lane + set_ctrl_resp.data_buffer[5] --> drive_swing */ + *pre_emp = set_ctrl_resp.data_buffer[5]; + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_jtx_lane_post_emphasis_get(adi_apollo_device_t *device, + uint8_t link_sides, + uint8_t physical_lane, + uint8_t *post_emp) +{ + adi_apollo_mailbox_cmd_set_ctrl_t set_ctrl_cmd = { + .sys_cal_object_id = APOLLO_CPU_OBJID_IC_SERDES_TX, + .ctrl_cmd = CTRL_CMD_PARAM_GET, + .data_buffer[0] = ADI_APOLLO_SERDES_TX_POST_EMPHASIS_STRUCT, + .data_buffer[1] = 0, + .data_buffer[2] = 0, + .data_buffer[3] = 0, + .data_buffer[4] = physical_lane, + .data_buffer[5] = 0, + .data_buffer[6] = 0, + .data_buffer[7] = 0, + .length = 8 + }; + + adi_apollo_mailbox_resp_set_ctrl_t set_ctrl_resp; + int32_t err, i; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(link_sides > ADI_APOLLO_LINK_SIDE_ALL); + ADI_APOLLO_INVALID_PARAM_RETURN(physical_lane > ADI_APOLLO_JTX_LANES_MAX-1); + + for (i = 0; i < ADI_APOLLO_NUM_JTX_LINKS; i += ADI_APOLLO_NUM_JTX_LINKS_PER_SIDE) { + if ((1 << i) & link_sides) { + set_ctrl_cmd.channel_num = (i >> 1); // 0 for side A and 1 for side B + + err = adi_apollo_mailbox_set_ctrl(device, &set_ctrl_cmd, &set_ctrl_resp); + if (err != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Error from adi_apollo_mailbox_set_ctrl() %d", err); + return err; + } + + if (set_ctrl_resp.status != API_CMS_ERROR_OK){ + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Mailbox Response Status Error from adi_apollo_mailbox_set_ctrl() 0x%X", set_ctrl_resp.status); + return API_CMS_ERROR_ERROR; + } + + /* Extract Drive Swing info from response structure + set_ctrl_resp.data_buffer[4] --> physical_lane + set_ctrl_resp.data_buffer[5] --> post_emp */ + *post_emp = set_ctrl_resp.data_buffer[5]; + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_jtx_multi_lane_swing_emphasis_get(adi_apollo_device_t *device, + uint8_t link_sides, + uint8_t* physical_lane, + uint8_t* drive_swing, + uint8_t* pre_emp, + uint8_t* post_emp, + uint32_t num_lanes) +{ + adi_apollo_mailbox_cmd_set_ctrl_t set_ctrl_cmd = { + .sys_cal_object_id = APOLLO_CPU_OBJID_IC_SERDES_TX, + .ctrl_cmd = CTRL_CMD_PARAM_GET, + .data_buffer[0] = ADI_APOLLO_SERDES_TX_LANES_SWING_EMPHASIS_STRUCT, + .data_buffer[1] = 0, + .data_buffer[2] = 0, + .data_buffer[3] = 0, + .length = 4 + (num_lanes * 4) + }; + + adi_apollo_mailbox_resp_set_ctrl_t set_ctrl_resp; + int32_t err, i; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(physical_lane); + ADI_APOLLO_NULL_POINTER_RETURN(drive_swing); + ADI_APOLLO_NULL_POINTER_RETURN(pre_emp); + ADI_APOLLO_NULL_POINTER_RETURN(post_emp); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(link_sides > ADI_APOLLO_LINK_SIDE_ALL); + ADI_APOLLO_INVALID_PARAM_RETURN(num_lanes > ADI_APOLLO_JTX_LANES_MAX); + + for (int i = 0; i < num_lanes; i++) { + ADI_APOLLO_INVALID_PARAM_RETURN(physical_lane[i] > ADI_APOLLO_JTX_LANES_MAX-1); + set_ctrl_cmd.data_buffer[4 + (i*4)] = physical_lane[i]; + } + + for (i = 0; i < ADI_APOLLO_NUM_JTX_LINKS; i += ADI_APOLLO_NUM_JTX_LINKS_PER_SIDE) { + if ((1 << i) & link_sides) { + set_ctrl_cmd.channel_num = (i >> 1); // 0 for side A and 1 for side B + + err = adi_apollo_mailbox_set_ctrl(device, &set_ctrl_cmd, &set_ctrl_resp); + if (err != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Error from adi_apollo_mailbox_set_ctrl() %d", err); + return err; + } + + if (set_ctrl_resp.status != API_CMS_ERROR_OK){ + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Mailbox Response Status Error from adi_apollo_mailbox_set_ctrl() 0x%X", set_ctrl_resp.status); + return API_CMS_ERROR_ERROR; + } + + /* Extract Drive Swing info from response structure + set_ctrl_resp.data_buffer[4] --> physical_lane + set_ctrl_resp.data_buffer[5] --> drive_swing + set_ctrl_resp.data_buffer[6] --> pre_emp + set_ctrl_resp.data_buffer[7] --> post_emp */ + for (int i = 0; i < num_lanes; i++) { + drive_swing[i] = set_ctrl_resp.data_buffer[(i*4)+5]; + pre_emp[i] = set_ctrl_resp.data_buffer[(i*4)+6]; + post_emp[i] = set_ctrl_resp.data_buffer[(i*4)+7]; + } + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_jtx_lr_adapt_get(adi_apollo_device_t *device, + uint8_t link_sides, + uint8_t physical_lane, + uint8_t *lr_adapt) +{ + int32_t err, i; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(link_sides > ADI_APOLLO_LINK_SIDE_ALL); + ADI_APOLLO_INVALID_PARAM_RETURN(physical_lane > ADI_APOLLO_JTX_LANES_MAX - 1); + ADI_APOLLO_NULL_POINTER_RETURN(lr_adapt); + + for (i = 0; i < ADI_APOLLO_NUM_JTX_LINKS; i += ADI_APOLLO_NUM_JTX_LINKS_PER_SIDE) { + if ((1 << i) & link_sides) { + regmap_base_addr = calc_jtx_dual_link_base(i); + err = adi_apollo_hal_bf_get(device, BF_JTX_BR_LOG2_RATIO_INFO(regmap_base_addr, physical_lane), lr_adapt, 1); + ADI_APOLLO_ERROR_RETURN(err); + } + } + return API_CMS_ERROR_OK; +} + + +int32_t adi_apollo_jtx_force_invalids_set(adi_apollo_device_t* device, + const uint16_t links, + const uint8_t enable) +{ + int32_t err, i; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + for (i = 0; i < ADI_APOLLO_NUM_JTX_LINKS; i++) { + if ((1 << i) & links) { + regmap_base_addr = calc_jtx_dformat_base(i); + + err = adi_apollo_hal_bf_set(device, BF_FORCE_INVALID_EN_INFO(regmap_base_addr, i % 2), enable); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +uint32_t calc_jtx_dual_link_base(int32_t link) +{ + static uint32_t jtx_dual_link_regmap[4] = { + JTX_DUAL_LINK_0_JTX_TOP_RX_DIGITAL0, JTX_DUAL_LINK_1_JTX_TOP_RX_DIGITAL0, + JTX_DUAL_LINK_0_JTX_TOP_RX_DIGITAL1, JTX_DUAL_LINK_1_JTX_TOP_RX_DIGITAL1 + }; + return jtx_dual_link_regmap[link]; +} + +uint32_t calc_jtx_qbf_txfe_base(int32_t link) +{ + static uint32_t jtx_qbf_regmap[4] = { + JTX_QBF_TXFE_0_JTX_TOP_RX_DIGITAL0, JTX_QBF_TXFE_1_JTX_TOP_RX_DIGITAL0, + JTX_QBF_TXFE_0_JTX_TOP_RX_DIGITAL1, JTX_QBF_TXFE_1_JTX_TOP_RX_DIGITAL1 + }; + return jtx_qbf_regmap[link]; +} + +uint32_t calc_jtx_jesd_param_base(int32_t link) +{ + static uint32_t jtx_jesd_param_regmap[4] = { + JTX_DUAL_LINK_0_JTX_TOP_RX_DIGITAL0, JTX_DUAL_LINK_1_JTX_TOP_RX_DIGITAL0, + JTX_DUAL_LINK_0_JTX_TOP_RX_DIGITAL1, JTX_DUAL_LINK_1_JTX_TOP_RX_DIGITAL1 + }; + return jtx_jesd_param_regmap[link]; +} +/*! @} */ \ No newline at end of file diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_lb0.c b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_lb0.c new file mode 100644 index 00000000000000..ed132e70ed3e66 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_lb0.c @@ -0,0 +1,375 @@ +/*! + * \brief Loopback 0 control functions + * + * \copyright copyright(c) 2023 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_LB0 + * @{ + */ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_lb0.h" + +#include "adi_apollo_bf_rx_loopback.h" +#include "adi_apollo_bf_tx_loopback.h" +#include "adi_apollo_bf_tx_misc.h" + +#include "adi_apollo_config.h" +#include "adi_apollo_hal.h" +#include "adi_apollo_utils.h" + +#include "adi_utils.h" + + +/*==================== D E F I N E S ====================*/ + +static uint32_t calc_rx_lb_base(int32_t side); +static uint32_t calc_tx_misc_base(int32_t side); +static uint32_t calc_tx_lb_base(int32_t adc); + +static int32_t adi_apollo_lb0_tx_xbar_map(adi_apollo_device_t *device, adi_apollo_adc_idx_e adc, adi_apollo_dac_idx_e dac, uint8_t *xbar); + +/*==================== P U B L I C A P I C O D E ====================*/ + +int32_t adi_apollo_lb0_debug_data_enable_set(adi_apollo_device_t *device, uint16_t sides, uint8_t enable) +{ + int32_t err, i, select; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + for(i = 0; i < ADI_APOLLO_NUM_SIDES; i ++) { + select = sides & (ADI_APOLLO_SIDE_A << i); + if (select > 0) { + regmap_base_addr = calc_rx_lb_base(i); + + // Enable/disable debug data gating + err = adi_apollo_hal_bf_set(device, BF_DBG_DATA_OFF_EN_INFO(regmap_base_addr), enable); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_lb0_rx_enable_set(adi_apollo_device_t *device, uint16_t sides, uint8_t enable) +{ + int32_t err, i, select; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + for(i = 0; i < ADI_APOLLO_NUM_SIDES; i ++) { + select = sides & (ADI_APOLLO_SIDE_A << i); + if (select > 0) { + regmap_base_addr = calc_rx_lb_base(i); + + // Enable/disable Rx loopback + err = adi_apollo_hal_bf_set(device, BF_LPBK_WR_EN_INFO(regmap_base_addr), enable); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_lb0_tx_enable_set(adi_apollo_device_t *device, uint16_t adcs, uint8_t enable) +{ + int32_t err, i, j, select; + uint32_t regmap_base_addr = 0; + + // For 4t4r device need to set two consecutive bitfields to enable, so we can't just loop through like normal. Need to calculate which indeces we need + uint8_t tr4_offset = 4; // skip A2/A3 (normally indeces 2 and 3) and go straight to 4 + uint8_t tr4_adc_per_side = 2; // number of adcs per side for a 4t4r device + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + // Enable/disable regs for 8t8r + if (device->dev_info.is_8t8r) { + for(i = 0; i < ADI_APOLLO_ADC_NUM; i ++) { + select = adcs & (ADI_APOLLO_ADC_A0 << i); + if (select > 0) { + regmap_base_addr = calc_tx_lb_base(i); + + // Enable/disable Tx loopback + err = adi_apollo_hal_bf_set(device, BF_LB0_EN_INFO(regmap_base_addr), enable); + ADI_APOLLO_ERROR_RETURN(err); + } + } + } else { // Enable/disable registers for 4t4r device + for (i = 0; i < ADI_APOLLO_NUM_SIDES; i++) { + for (j = 0; j < tr4_adc_per_side; j++) { + select = adcs & (ADI_APOLLO_ADC_A0 << (tr4_offset * i + j)); + if (select > 0) { + + regmap_base_addr = calc_tx_lb_base(tr4_offset * i + 2 * j); + err = adi_apollo_hal_bf_set(device, BF_LB0_EN_INFO(regmap_base_addr), enable); + ADI_APOLLO_ERROR_RETURN(err); + + regmap_base_addr = calc_tx_lb_base(tr4_offset * i + 2 * j + 1); + err = adi_apollo_hal_bf_set(device, BF_LB0_EN_INFO(regmap_base_addr), enable); + ADI_APOLLO_ERROR_RETURN(err); + + } + } + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_lb0_tx_xbar_set(adi_apollo_device_t *device, uint16_t sides, uint16_t adcs[], uint32_t adc_map_length) +{ + int32_t err; + uint32_t regmap_base_addr = 0; + uint8_t i, select,xbar_value = 0xb0; + adi_apollo_dac_idx_e dacs[ADI_APOLLO_DAC_PER_SIDE_NUM] = {ADI_APOLLO_DAC_0, ADI_APOLLO_DAC_1, ADI_APOLLO_DAC_2, ADI_APOLLO_DAC_3}; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(adcs); + + // Check parameters are valid + if ((device->dev_info.is_8t8r && adc_map_length != 4) || (!device->dev_info.is_8t8r && adc_map_length != 2)) { + return API_CMS_ERROR_INVALID_PARAM; + } + + // Calculate xbar value + for (i = 0; i < adc_map_length; i++) { + err = adi_apollo_lb0_tx_xbar_map(device, adcs[i], dacs[i], &xbar_value); + ADI_APOLLO_ERROR_RETURN(err); + } + + for(i = 0; i < ADI_APOLLO_NUM_SIDES; i ++) { + select = sides & (ADI_APOLLO_SIDE_A << i); + if (select > 0) { + + // set tx xbar + regmap_base_addr = calc_tx_misc_base(i); + err = adi_apollo_hal_bf_set(device, BF_HS_XBAR_CTRL_INFO(regmap_base_addr), xbar_value); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_lb0_read_ptr_rst_set(adi_apollo_device_t *device, uint16_t adcs, uint8_t value) +{ + int32_t err, i, select; + uint32_t regmap_base_addr = 0; + + if (value >= 3){ + return API_CMS_ERROR_INVALID_PARAM; + } + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + for(i = 0; i < ADI_APOLLO_ADC_NUM; i ++) { + select = adcs & (ADI_APOLLO_ADC_A0 << i); + if (select > 0) { + regmap_base_addr = calc_tx_lb_base(i); + + // Set read pointer + err = adi_apollo_hal_bf_set(device, BF_LB0_RDPTR_SYNC_RSTVAL_INFO(regmap_base_addr), value); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_lb0_write_ptr_rst_set(adi_apollo_device_t *device, uint16_t sides, uint8_t value) +{ + int32_t err, i, select; + uint32_t regmap_base_addr = 0; + + if (value >= 3){ + return API_CMS_ERROR_INVALID_PARAM; + } + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + for(i = 0; i < ADI_APOLLO_NUM_SIDES; i ++) { + select = sides & (ADI_APOLLO_SIDE_A << i); + if (select > 0) { + regmap_base_addr = calc_rx_lb_base(i); + + // Set write ptr + err = adi_apollo_hal_bf_set(device, BF_LPBK_WR_EN_INFO(regmap_base_addr), value); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_lb0_overflow_status_get(adi_apollo_device_t *device, uint16_t adcs, uint8_t *status) +{ + int32_t err; + uint16_t sides; + uint8_t bitmask; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(status); + + err = adi_apollo_utils_side_from_adc_select_get(device, adcs, &sides); + ADI_APOLLO_ERROR_RETURN(err); + + // Get the bitmask + switch (adcs) + { + case ADI_APOLLO_ADC_A0: + case ADI_APOLLO_ADC_B0: + bitmask = 0x1; + break; + + case ADI_APOLLO_ADC_A1: + case ADI_APOLLO_ADC_B1: + bitmask = 0x4; + break; + + case ADI_APOLLO_ADC_A2: + case ADI_APOLLO_ADC_B2: + bitmask = 0x2; + break; + + case ADI_APOLLO_ADC_A3: + case ADI_APOLLO_ADC_B3: + bitmask = 0x8; + break; + + default: + return API_CMS_ERROR_INVALID_PARAM; + } + + // Side A + if (sides == ADI_APOLLO_SIDE_A) { + err = adi_apollo_hal_bf_get(device, BF_ADC_DATA_OVR_STATUS_INFO(RX_LOOPBACK_RX_SLICE_0_RX_DIGITAL0), status, 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_ADC_DATA_OVR_CLEAR_INFO(RX_LOOPBACK_RX_SLICE_0_RX_DIGITAL0), bitmask); + ADI_APOLLO_ERROR_RETURN(err); + } + // Side B + if (sides == ADI_APOLLO_SIDE_B) { + err = adi_apollo_hal_bf_get(device, BF_ADC_DATA_OVR_STATUS_INFO(RX_LOOPBACK_RX_SLICE_0_RX_DIGITAL1), status, 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_ADC_DATA_OVR_CLEAR_INFO(RX_LOOPBACK_RX_SLICE_0_RX_DIGITAL1), bitmask); + ADI_APOLLO_ERROR_RETURN(err); + } + + // Set status + *status = *status & bitmask ? 1 : 0; + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_lb0_bmem_enable_set(adi_apollo_device_t *device, uint16_t sides, uint8_t enable) +{ +#ifdef B0 + int32_t err, i, select; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + for(i = 0; i < ADI_APOLLO_NUM_SIDES; i ++) { + select = sides & (ADI_APOLLO_SIDE_A << i); + if (select > 0) { + regmap_base_addr = calc_rx_lb_base(i); + + // Enable/disable debug data gating + err = adi_apollo_hal_bf_set(device, BF_LB0_BMEM_PATH_SEL_INFO(regmap_base_addr), enable); + ADI_APOLLO_ERROR_RETURN(err); + } + } +#endif +#ifdef A0 + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); +#endif + return API_CMS_ERROR_OK; +} + + +static uint32_t calc_rx_lb_base(int32_t side) { + static const uint32_t rx_lb_reg[ADI_APOLLO_NUM_SIDES] = {RX_LOOPBACK_RX_SLICE_0_RX_DIGITAL0, RX_LOOPBACK_RX_SLICE_0_RX_DIGITAL1}; + return rx_lb_reg[side]; +} + +static uint32_t calc_tx_misc_base(int32_t side) { + static const uint32_t tx_misc_reg[ADI_APOLLO_NUM_SIDES] = {TX_MISC_TX_TOP_TX_DIGITAL0, TX_MISC_TX_TOP_TX_DIGITAL1}; + return tx_misc_reg[side]; +} + +static uint32_t calc_tx_lb_base(int32_t adc){ + static const uint32_t tx_lb_reg[ADI_APOLLO_ADC_NUM] = {TX_LOOPBACK0_TX_SLICE_0_TX_DIGITAL0, TX_LOOPBACK1_TX_SLICE_0_TX_DIGITAL0, TX_LOOPBACK0_TX_SLICE_1_TX_DIGITAL0, TX_LOOPBACK1_TX_SLICE_1_TX_DIGITAL0, + TX_LOOPBACK0_TX_SLICE_0_TX_DIGITAL1, TX_LOOPBACK1_TX_SLICE_0_TX_DIGITAL1, TX_LOOPBACK0_TX_SLICE_1_TX_DIGITAL1, TX_LOOPBACK1_TX_SLICE_1_TX_DIGITAL1}; + + return tx_lb_reg[adc]; +} + +static int32_t adi_apollo_lb0_tx_xbar_map(adi_apollo_device_t *device, adi_apollo_adc_idx_e adc, adi_apollo_dac_idx_e dac, uint8_t *xbar) { + uint8_t bit_shift; + uint8_t map_val; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + // Get bit value for adcs + switch (adc) + { + case ADI_APOLLO_ADC_0: + map_val = 0; + break; + case ADI_APOLLO_ADC_1: + map_val = 1; + break; + case ADI_APOLLO_ADC_2: + map_val = 2; + break; + case ADI_APOLLO_ADC_3: + map_val = 3; + break; + + default: + return API_CMS_ERROR_INVALID_PARAM; + } + + // Get bit positions + switch (dac) + { + case ADI_APOLLO_DAC_0: + bit_shift = 0; + break; + case ADI_APOLLO_DAC_1: + bit_shift = 2; + break; + case ADI_APOLLO_DAC_2: + bit_shift = 4; + break; + case ADI_APOLLO_DAC_3: + bit_shift = 6; + break; + + default: + return API_CMS_ERROR_INVALID_PARAM; + } + + // Update xbar value + *xbar = *xbar & ~((uint8_t)3 << bit_shift); + *xbar = *xbar | (map_val << bit_shift); + + return API_CMS_ERROR_OK; +} \ No newline at end of file diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_loopback.c b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_loopback.c new file mode 100644 index 00000000000000..17a101d1b7d3bb --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_loopback.c @@ -0,0 +1,518 @@ +/*! + * \brief Loopback 0 control functions + * + * \copyright copyright(c) 2023 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_LB0 + * @{ + */ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_loopback.h" +#include "adi_apollo_private_device.h" + +#include "adi_apollo_bf_rx_loopback.h" +#include "adi_apollo_bf_tx_loopback.h" +#include "adi_apollo_bf_tx_misc.h" +#include "adi_apollo_txmisc_local.h" +#include "adi_apollo_bf_rx_misc.h" +#include "adi_apollo_rxmisc_local.h" +#include "adi_apollo_bf_custom.h" + +#include "adi_apollo_config.h" +#include "adi_apollo_hal.h" +#include "adi_apollo_utils.h" + +#include "adi_utils.h" + + +/*==================== D E F I N E S ====================*/ + +static uint32_t calc_rx_lb_base(int32_t side); +static uint32_t calc_tx_lb_base(int32_t adc); +static uint32_t calc_lb1_blend_base(int32_t cduc); + +static int32_t loopback_lb0_tx_xbar_map(adi_apollo_device_t *device, adi_apollo_adc_idx_e adc, adi_apollo_dac_idx_e dac, uint8_t *xbar); + +/*==================== P U B L I C A P I C O D E ====================*/ + +int32_t adi_apollo_loopback_lb0_debug_data_enable_set(adi_apollo_device_t *device, uint16_t sides, uint8_t enable) +{ + int32_t err, i, select; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_DEV_FEAT_LOCKOUT_RETURN(ADI_APOLLO_TX, ADI_APOLLO_EC_LPBK0_LOCK); + + for (i = 0; i < ADI_APOLLO_NUM_SIDES; i++) { + select = sides & (ADI_APOLLO_SIDE_A << i); + if (select > 0) { + regmap_base_addr = calc_rx_lb_base(i); + + // Enable/disable debug data gating + err = adi_apollo_hal_bf_set(device, BF_DBG_DATA_OFF_EN_INFO(regmap_base_addr), enable); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_loopback_lb0_rx_enable_set(adi_apollo_device_t *device, uint16_t sides, uint8_t enable) +{ + int32_t err, i, select; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_DEV_FEAT_LOCKOUT_RETURN(ADI_APOLLO_TX, ADI_APOLLO_EC_LPBK0_LOCK); + + for (i = 0; i < ADI_APOLLO_NUM_SIDES; i++) { + select = sides & (ADI_APOLLO_SIDE_A << i); + if (select > 0) { + regmap_base_addr = calc_rx_lb_base(i); + + // Enable/disable Rx loopback + err = adi_apollo_hal_bf_set(device, BF_LPBK_WR_EN_INFO(regmap_base_addr), enable); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_loopback_lb0_tx_enable_set(adi_apollo_device_t *device, uint16_t adcs, uint8_t enable) +{ + int32_t err, i, select; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_DEV_FEAT_LOCKOUT_RETURN(ADI_APOLLO_TX, ADI_APOLLO_EC_LPBK0_LOCK); + + // 4T4R devices require setting bf pairs + if (!device->dev_info.is_8t8r) { + adcs |= (adcs & ADI_APOLLO_ADC_A0) ? ADI_APOLLO_ADC_A2 : 0; + adcs |= (adcs & ADI_APOLLO_ADC_A1) ? ADI_APOLLO_ADC_A3 : 0; + } + + for (i = 0; i < ADI_APOLLO_ADC_NUM; i++) { + select = adcs & (ADI_APOLLO_ADC_A0 << i); + if (select > 0) { + regmap_base_addr = calc_tx_lb_base(i); + + // Enable/disable Tx loopback + err = adi_apollo_hal_bf_set(device, BF_LB0_EN_INFO(regmap_base_addr), enable); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_loopback_lb0_tx_xbar_set(adi_apollo_device_t *device, uint16_t sides, uint16_t adcs[], uint32_t adc_map_length) +{ + uint16_t dacs[ADI_APOLLO_DAC_PER_SIDE_NUM] = {ADI_APOLLO_DAC_0, ADI_APOLLO_DAC_1, ADI_APOLLO_DAC_2, ADI_APOLLO_DAC_3}; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + return (adi_apollo_loopback_lb0_tx_xbar_custom_set(device, sides, adcs, dacs, adc_map_length)); +} + +int32_t adi_apollo_loopback_lb0_tx_xbar_custom_set(adi_apollo_device_t *device, uint16_t sides, uint16_t adcs[], uint16_t dacs[], uint32_t adc_map_length) +{ + int32_t err; + uint32_t regmap_base_addr = 0; + uint8_t i, j, select, xbar_value; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_DEV_FEAT_LOCKOUT_RETURN(ADI_APOLLO_TX, ADI_APOLLO_EC_LPBK0_LOCK); + ADI_APOLLO_NULL_POINTER_RETURN(adcs); + ADI_APOLLO_NULL_POINTER_RETURN(dacs); + + // Check parameters are valid + if ((device->dev_info.is_8t8r && adc_map_length != 4) || (!device->dev_info.is_8t8r && adc_map_length != 2)) { + return API_CMS_ERROR_INVALID_PARAM; + } + + for (i = 0; i < ADI_APOLLO_NUM_SIDES; i++) { + select = sides & (ADI_APOLLO_SIDE_A << i); + if (select > 0) { + + // set tx xbar + regmap_base_addr = calc_tx_misc_base(i); + + // Get current xbar value + err = adi_apollo_hal_bf_get(device, BF_HS_XBAR_CTRL_INFO(regmap_base_addr), &xbar_value, sizeof(xbar_value)); + ADI_APOLLO_ERROR_RETURN(err); + + // Calculate xbar value + for (j = 0; j < adc_map_length; j++) { + err = loopback_lb0_tx_xbar_map(device, adcs[j], dacs[j], &xbar_value); + ADI_APOLLO_ERROR_RETURN(err); + } + + err = adi_apollo_hal_bf_set(device, BF_HS_XBAR_CTRL_INFO(regmap_base_addr), xbar_value); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_loopback_lb0_read_ptr_rst_set(adi_apollo_device_t *device, uint16_t adcs, uint8_t value) +{ + int32_t err, i, select; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_DEV_FEAT_LOCKOUT_RETURN(ADI_APOLLO_TX, ADI_APOLLO_EC_LPBK0_LOCK); + ADI_APOLLO_INVALID_PARAM_RETURN(value >= 3); + + for (i = 0; i < ADI_APOLLO_ADC_NUM; i++) { + select = adcs & (ADI_APOLLO_ADC_A0 << i); + if (select > 0) { + regmap_base_addr = calc_tx_lb_base(i); + + // Set read pointer + err = adi_apollo_hal_bf_set(device, BF_LB0_RDPTR_SYNC_RSTVAL_INFO(regmap_base_addr), value); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_loopback_lb0_write_ptr_rst_set(adi_apollo_device_t *device, uint16_t sides, uint8_t value) +{ + int32_t err, i, select; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_DEV_FEAT_LOCKOUT_RETURN(ADI_APOLLO_TX, ADI_APOLLO_EC_LPBK0_LOCK); + ADI_APOLLO_INVALID_PARAM_RETURN(value >= 3); + + for (i = 0; i < ADI_APOLLO_NUM_SIDES; i++) { + select = sides & (ADI_APOLLO_SIDE_A << i); + if (select > 0) { + regmap_base_addr = calc_rx_lb_base(i); + + // Set write ptr + err = adi_apollo_hal_bf_set(device, BF_LPBK_WR_EN_INFO(regmap_base_addr), value); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_loopback_lb0_overflow_status_get(adi_apollo_device_t *device, uint16_t adcs, uint8_t *status) +{ + int32_t err; + uint16_t sides; + uint8_t bitmask; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_DEV_FEAT_LOCKOUT_RETURN(ADI_APOLLO_TX, ADI_APOLLO_EC_LPBK0_LOCK); + ADI_APOLLO_NULL_POINTER_RETURN(status); + + err = adi_apollo_utils_side_from_adc_select_get(device, adcs, &sides); + ADI_APOLLO_ERROR_RETURN(err); + + // Get the bitmask + switch (adcs) + { + case ADI_APOLLO_ADC_A0: + case ADI_APOLLO_ADC_B0: + bitmask = 0x1; + break; + + case ADI_APOLLO_ADC_A1: + case ADI_APOLLO_ADC_B1: + bitmask = 0x4; + break; + + case ADI_APOLLO_ADC_A2: + case ADI_APOLLO_ADC_B2: + bitmask = 0x2; + break; + + case ADI_APOLLO_ADC_A3: + case ADI_APOLLO_ADC_B3: + bitmask = 0x8; + break; + + default: + return API_CMS_ERROR_INVALID_PARAM; + } + + // Side A + if (sides == ADI_APOLLO_SIDE_A) { + err = adi_apollo_hal_bf_get(device, BF_ADC_DATA_OVR_STATUS_INFO(RX_LOOPBACK_RX_SLICE_0_RX_DIGITAL0), status, 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_ADC_DATA_OVR_CLEAR_INFO(RX_LOOPBACK_RX_SLICE_0_RX_DIGITAL0), bitmask); + ADI_APOLLO_ERROR_RETURN(err); + } + // Side B + if (sides == ADI_APOLLO_SIDE_B) { + err = adi_apollo_hal_bf_get(device, BF_ADC_DATA_OVR_STATUS_INFO(RX_LOOPBACK_RX_SLICE_0_RX_DIGITAL1), status, 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_ADC_DATA_OVR_CLEAR_INFO(RX_LOOPBACK_RX_SLICE_0_RX_DIGITAL1), bitmask); + ADI_APOLLO_ERROR_RETURN(err); + } + + // Set status + *status = *status & bitmask ? 1 : 0; + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_loopback_lb0_bmem_enable_set(adi_apollo_device_t *device, uint16_t sides, uint8_t enable) +{ + int32_t err, i, select; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_DEV_FEAT_LOCKOUT_RETURN(ADI_APOLLO_TX, ADI_APOLLO_EC_LPBK0_LOCK); + + for (i = 0; i < ADI_APOLLO_NUM_SIDES; i++) { + select = sides & (ADI_APOLLO_SIDE_A << i); + if (select > 0) { + regmap_base_addr = calc_rx_lb_base(i); + + // Enable/disable debug data gating + err = adi_apollo_hal_bf_set(device, BF_LB0_BMEM_PATH_SEL_INFO(regmap_base_addr), enable); + ADI_APOLLO_ERROR_RETURN(err); + } + } + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_loopback_jesd_enable_set(adi_apollo_device_t *device, uint16_t sides, uint8_t enable) +{ + + int32_t err; + uint8_t i; + uint32_t regmap_base_addr = 0; + uint16_t side; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(enable > 1); + ADI_APOLLO_DEV_FEAT_LOCKOUT_RETURN(ADI_APOLLO_TX, ADI_APOLLO_EC_LPBK123_LOCK); + + for (i = 0; i < ADI_APOLLO_NUM_SIDES; i++) { + side = sides & (ADI_APOLLO_SIDE_A << i); + if (side > 0) { + regmap_base_addr = calc_tx_misc_base(i); + + // Ensure data reaches loopback point + if (enable) { + err = adi_apollo_hal_bf_set(device, BF_CDUC_DAC_ENABLES0_INFO(regmap_base_addr), 3); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_FDUC_ENABLES00_INFO(regmap_base_addr), 0xFF); + ADI_APOLLO_ERROR_RETURN(err); + } + + err = adi_apollo_hal_bf_set(device, BF_JESD_LBK_MODE_INFO(regmap_base_addr), enable); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_loopback_lb1_enable_set(adi_apollo_device_t *device, uint16_t sides, uint8_t enable) +{ + int32_t err, i; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_DEV_FEAT_LOCKOUT_RETURN(ADI_APOLLO_TX, ADI_APOLLO_EC_LPBK123_LOCK); + + for (i = 0; i < ADI_APOLLO_NUM_SIDES; i++) { + if ((sides & (1 << i)) > 0) { + // Enable/disable LB1 write + regmap_base_addr = calc_rx_misc_base(i); + err = adi_apollo_hal_bf_set(device, BF_LB1_WR_EN_INFO(regmap_base_addr), enable); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_loopback_lb1_cduc_enable_set(adi_apollo_device_t *device, uint16_t cducs, uint8_t enable) +{ + int32_t err, i; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_DEV_FEAT_LOCKOUT_RETURN(ADI_APOLLO_TX, ADI_APOLLO_EC_LPBK123_LOCK); + + for (i = 0; i < ADI_APOLLO_CDUC_NUM; i++) { + if ((cducs & (1 << i)) > 0) { + regmap_base_addr = calc_tx_misc_base(i/ADI_APOLLO_CDUC_PER_SIDE_NUM); + err = adi_apollo_hal_bf_set(device, BF_LB1_EN0_INFO(regmap_base_addr) + (i%ADI_APOLLO_CDUC_PER_SIDE_NUM), enable); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_loopback_lb1_blend_set(adi_apollo_device_t *device, uint16_t cducs, adi_apollo_loopback_lb1_blend_mode_e mode) +{ + int32_t err, i; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_DEV_FEAT_LOCKOUT_RETURN(ADI_APOLLO_TX, ADI_APOLLO_EC_LPBK123_LOCK); + + for (i = 0; i < ADI_APOLLO_CDUC_NUM; i++) { + if ((cducs & (1 << i)) > 0) { + err = adi_apollo_hal_bf_set(device, calc_lb1_blend_base(2*i), calc_lb1_blend_base(2*i + 1), mode); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_loopback_lb2_enable_set(adi_apollo_device_t *device, uint16_t sides, uint8_t enable) +{ + int32_t err, i; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_DEV_FEAT_LOCKOUT_RETURN(ADI_APOLLO_TX, ADI_APOLLO_EC_LPBK123_LOCK); + + for (i = 0; i < ADI_APOLLO_NUM_SIDES; i++) { + if ((sides & (1 << i)) > 0) { + // Enable/disable LB2 write + regmap_base_addr = calc_rx_misc_base(i); + err = adi_apollo_hal_bf_set(device, BF_LB2_WR_EN_INFO(regmap_base_addr), enable); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_loopback_lb2_fduc_enable_set(adi_apollo_device_t *device, uint16_t fducs, uint8_t enable) +{ + int32_t err, i; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_DEV_FEAT_LOCKOUT_RETURN(ADI_APOLLO_TX, ADI_APOLLO_EC_LPBK123_LOCK); + + for (i = 0; i < ADI_APOLLO_FDUC_NUM; i++) { + if ((fducs & (1 << i)) > 0) { + regmap_base_addr = calc_tx_misc_base(i/ADI_APOLLO_FDUC_PER_SIDE_NUM); + err = adi_apollo_hal_bf_set(device, BF_LB2_EN0_INFO(regmap_base_addr) + (i%ADI_APOLLO_FDUC_PER_SIDE_NUM), enable); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + + +static uint32_t calc_rx_lb_base(int32_t side) { + static const uint32_t rx_lb_reg[ADI_APOLLO_NUM_SIDES] = {RX_LOOPBACK_RX_SLICE_0_RX_DIGITAL0, RX_LOOPBACK_RX_SLICE_0_RX_DIGITAL1}; + return rx_lb_reg[side]; +} + +static uint32_t calc_tx_lb_base(int32_t adc) +{ + static const uint32_t tx_lb_reg[ADI_APOLLO_ADC_NUM] = { + TX_LOOPBACK0_TX_SLICE_0_TX_DIGITAL0, TX_LOOPBACK0_TX_SLICE_1_TX_DIGITAL0, // A0, A1 + TX_LOOPBACK1_TX_SLICE_0_TX_DIGITAL0, TX_LOOPBACK1_TX_SLICE_1_TX_DIGITAL0, // A2, A3 + TX_LOOPBACK0_TX_SLICE_0_TX_DIGITAL1, TX_LOOPBACK0_TX_SLICE_1_TX_DIGITAL1, // B0, B1 + TX_LOOPBACK1_TX_SLICE_0_TX_DIGITAL1, TX_LOOPBACK1_TX_SLICE_1_TX_DIGITAL1 // B2, B3 + }; + return tx_lb_reg[adc]; +} + +static int32_t loopback_lb0_tx_xbar_map(adi_apollo_device_t *device, adi_apollo_adc_idx_e adc, adi_apollo_dac_idx_e dac, uint8_t *xbar) { + uint8_t bit_shift; + uint8_t map_val; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + // Get bit value for adcs + switch (adc) + { + case ADI_APOLLO_ADC_0: + map_val = 0; + break; + case ADI_APOLLO_ADC_1: + map_val = device->dev_info.is_8t8r ? 2 : 1; + break; + case ADI_APOLLO_ADC_2: + map_val = device->dev_info.is_8t8r ? 1 : 2; + break; + case ADI_APOLLO_ADC_3: + map_val = 3; + break; + + default: + ADI_APOLLO_ERROR_RETURN(API_CMS_ERROR_INVALID_PARAM); + } + + // Get bit positions + switch (dac) + { + case ADI_APOLLO_DAC_0: + bit_shift = 0; + break; + case ADI_APOLLO_DAC_1: + bit_shift = 2; + break; + case ADI_APOLLO_DAC_2: + bit_shift = 4; + break; + case ADI_APOLLO_DAC_3: + bit_shift = 6; + break; + + default: + ADI_APOLLO_ERROR_RETURN(API_CMS_ERROR_INVALID_PARAM); + } + + // Update xbar value + *xbar = *xbar & ~((uint8_t)3 << bit_shift); + *xbar = *xbar | (map_val << bit_shift); + + return API_CMS_ERROR_OK; +} + +static uint32_t calc_lb1_blend_base(int32_t cduc){ + static const uint32_t lb_reg[ADI_APOLLO_CDUC_NUM * 2] = { + BF_SL0_LB1_SHIFT_INFO(TX_MISC_TX_TOP_TX_DIGITAL0), BF_SL1_LB1_SHIFT_INFO(TX_MISC_TX_TOP_TX_DIGITAL0), + BF_SL0_LB1_SHIFT_8T8R_INFO(TX_MISC_TX_TOP_TX_DIGITAL0), BF_SL1_LB1_SHIFT_8T8R_INFO(TX_MISC_TX_TOP_TX_DIGITAL0), + BF_SL0_LB1_SHIFT_INFO(TX_MISC_TX_TOP_TX_DIGITAL1), BF_SL1_LB1_SHIFT_INFO(TX_MISC_TX_TOP_TX_DIGITAL1), + BF_SL0_LB1_SHIFT_8T8R_INFO(TX_MISC_TX_TOP_TX_DIGITAL1), BF_SL1_LB1_SHIFT_8T8R_INFO(TX_MISC_TX_TOP_TX_DIGITAL1) + }; + return lb_reg[cduc]; +} +/*! @} */ \ No newline at end of file diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_mailbox.c b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_mailbox.c new file mode 100644 index 00000000000000..be1942fa2038d1 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_mailbox.c @@ -0,0 +1,651 @@ +/*! + * \brief APIs for MAILBOX + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_MAILBOX + * @{ + */ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_mailbox.h" +#include "adi_apollo_mailbox_handler_local.h" + +#include "adi_apollo_config.h" +#include "adi_apollo_hal.h" + +/*==================== P U B L I C A P I C O D E ====================*/ + +int32_t adi_apollo_mailbox_ping(adi_apollo_device_t *device, adi_apollo_mailbox_cmd_ping_t *cmd, adi_apollo_mailbox_resp_ping_t *resp) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(cmd); + ADI_APOLLO_NULL_POINTER_RETURN(resp); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_mailbox_xfer(device, ADI_APOLLO_MAILBOX_PING, (uint8_t *)cmd, sizeof(adi_apollo_mailbox_cmd_ping_t), (uint8_t *)resp, sizeof(adi_apollo_mailbox_resp_ping_t)); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_mailbox_run_init(adi_apollo_device_t *device, adi_apollo_mailbox_cmd_run_init_t *cmd, adi_apollo_mailbox_resp_run_init_t *resp) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(cmd); + ADI_APOLLO_NULL_POINTER_RETURN(resp); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_mailbox_xfer(device, ADI_APOLLO_MAILBOX_RUN_INIT, (uint8_t *)cmd, sizeof(adi_apollo_mailbox_cmd_run_init_t), (uint8_t *)resp, sizeof(adi_apollo_mailbox_resp_run_init_t)); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_mailbox_run_init_get_completion(adi_apollo_device_t *device, adi_apollo_mailbox_resp_run_init_get_completion_t *resp) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(resp); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_mailbox_xfer(device, ADI_APOLLO_MAILBOX_RUN_INIT_GET_COMPLETION, NULL, 0, (uint8_t *)resp, sizeof(adi_apollo_mailbox_resp_run_init_get_completion_t)); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_mailbox_run_init_get_detailed_status(adi_apollo_device_t *device, adi_apollo_mailbox_resp_run_init_get_detailed_status_t *resp) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(resp); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_mailbox_xfer(device, ADI_APOLLO_MAILBOX_RUN_INIT_GET_DETAILED_STATUS, NULL, 0, (uint8_t *)resp, sizeof(adi_apollo_mailbox_resp_run_init_get_detailed_status_t)); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_mailbox_run_init_abort(adi_apollo_device_t *device, adi_apollo_mailbox_resp_run_init_abort_t *resp) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(resp); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_mailbox_xfer(device, ADI_APOLLO_MAILBOX_RUN_INIT_ABORT, NULL, 0, (uint8_t *)resp, sizeof(adi_apollo_mailbox_resp_run_init_abort_t)); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_mailbox_set_enabled_tracking_cals(adi_apollo_device_t *device, adi_apollo_mailbox_cmd_set_enabled_tracking_cals_t *cmd, adi_apollo_mailbox_resp_set_enabled_tracking_cals_t *resp) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(cmd); + ADI_APOLLO_NULL_POINTER_RETURN(resp); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_mailbox_xfer(device, ADI_APOLLO_MAILBOX_SET_ENABLED_TRACKING_CALS, (uint8_t *)cmd, sizeof(adi_apollo_mailbox_cmd_set_enabled_tracking_cals_t), (uint8_t *)resp, sizeof(adi_apollo_mailbox_resp_set_enabled_tracking_cals_t)); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_mailbox_get_enabled_tracking_cals(adi_apollo_device_t *device, adi_apollo_mailbox_resp_get_enabled_tracking_cals_t *resp) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(resp); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_mailbox_xfer(device, ADI_APOLLO_MAILBOX_GET_ENABLED_TRACKING_CALS, NULL, 0, (uint8_t *)resp, sizeof(adi_apollo_mailbox_resp_get_enabled_tracking_cals_t)); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_mailbox_get_tracking_cal_state(adi_apollo_device_t *device, adi_apollo_mailbox_resp_get_tracking_cal_state_t *resp) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(resp); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_mailbox_xfer(device, ADI_APOLLO_MAILBOX_GET_TRACKING_CAL_STATE, NULL, 0, (uint8_t *)resp, sizeof(adi_apollo_mailbox_resp_get_tracking_cal_state_t)); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_mailbox_get_cal_status(adi_apollo_device_t *device, adi_apollo_mailbox_cmd_get_cal_status_t *cmd, adi_apollo_mailbox_resp_get_cal_status_t *resp) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(cmd); + ADI_APOLLO_NULL_POINTER_RETURN(resp); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_mailbox_xfer(device, ADI_APOLLO_MAILBOX_GET_CAL_STATUS, (uint8_t *)cmd, sizeof(adi_apollo_mailbox_cmd_get_cal_status_t), (uint8_t *)resp, sizeof(adi_apollo_mailbox_resp_get_cal_status_t)); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_mailbox_get_sys_status(adi_apollo_device_t *device, adi_apollo_mailbox_cmd_get_sys_status_t *cmd, adi_apollo_mailbox_resp_get_sys_status_t *resp) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(cmd); + ADI_APOLLO_NULL_POINTER_RETURN(resp); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_mailbox_xfer(device, ADI_APOLLO_MAILBOX_GET_SYS_STATUS, (uint8_t *)cmd, sizeof(adi_apollo_mailbox_cmd_get_sys_status_t), (uint8_t *)resp, sizeof(adi_apollo_mailbox_resp_get_sys_status_t)); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_mailbox_get_device_temperature(adi_apollo_device_t *device, adi_apollo_mailbox_cmd_get_device_temperature_t *cmd, adi_apollo_mailbox_resp_get_device_temperature_t *resp) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(cmd); + ADI_APOLLO_NULL_POINTER_RETURN(resp); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_mailbox_xfer(device, ADI_APOLLO_MAILBOX_GET_DEVICE_TEMPERATURE, (uint8_t *)cmd, sizeof(adi_apollo_mailbox_cmd_get_device_temperature_t), (uint8_t *)resp, sizeof(adi_apollo_mailbox_resp_get_device_temperature_t)); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_mailbox_get_enabled_temp_sensors(adi_apollo_device_t *device, adi_apollo_mailbox_resp_get_enabled_temp_sensors_t *resp) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(resp); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_mailbox_xfer(device, ADI_APOLLO_MAILBOX_GET_ENABLED_TEMP_SENSORS, NULL, 0, (uint8_t *)resp, sizeof(adi_apollo_mailbox_resp_get_enabled_temp_sensors_t)); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_mailbox_set_enabled_temp_sensors(adi_apollo_device_t *device, adi_apollo_mailbox_cmd_set_enabled_temp_sensors_t *cmd, adi_apollo_mailbox_resp_set_enabled_temp_sensors_t *resp) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(cmd); + ADI_APOLLO_NULL_POINTER_RETURN(resp); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_mailbox_xfer(device, ADI_APOLLO_MAILBOX_SET_ENABLED_TEMP_SENSORS, (uint8_t *)cmd, sizeof(adi_apollo_mailbox_cmd_set_enabled_temp_sensors_t), (uint8_t *)resp, sizeof(adi_apollo_mailbox_resp_set_enabled_temp_sensors_t)); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_mailbox_unlock_config(adi_apollo_device_t *device, adi_apollo_mailbox_cmd_unlock_config_t *cmd, adi_apollo_mailbox_resp_unlock_config_t *resp) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(cmd); + ADI_APOLLO_NULL_POINTER_RETURN(resp); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_mailbox_xfer(device, ADI_APOLLO_MAILBOX_UNLOCK_CONFIG, (uint8_t *)cmd, sizeof(adi_apollo_mailbox_cmd_unlock_config_t), (uint8_t *)resp, sizeof(adi_apollo_mailbox_resp_unlock_config_t)); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_mailbox_set_config(adi_apollo_device_t *device, adi_apollo_mailbox_cmd_set_config_t *cmd, adi_apollo_mailbox_resp_set_config_t *resp) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(cmd); + ADI_APOLLO_NULL_POINTER_RETURN(resp); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_mailbox_xfer(device, ADI_APOLLO_MAILBOX_SET_CONFIG, (uint8_t *)cmd, sizeof(adi_apollo_mailbox_cmd_set_config_t), (uint8_t *)resp, sizeof(adi_apollo_mailbox_resp_set_config_t)); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_mailbox_get_config(adi_apollo_device_t *device, adi_apollo_mailbox_cmd_get_config_t *cmd, adi_apollo_mailbox_resp_get_config_t *resp) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(cmd); + ADI_APOLLO_NULL_POINTER_RETURN(resp); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_mailbox_xfer(device, ADI_APOLLO_MAILBOX_GET_CONFIG, (uint8_t *)cmd, sizeof(adi_apollo_mailbox_cmd_get_config_t), (uint8_t *)resp, sizeof(adi_apollo_mailbox_resp_get_config_t)); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_mailbox_set_ctrl(adi_apollo_device_t *device, adi_apollo_mailbox_cmd_set_ctrl_t *cmd, adi_apollo_mailbox_resp_set_ctrl_t *resp) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(cmd); + ADI_APOLLO_NULL_POINTER_RETURN(resp); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_mailbox_xfer(device, ADI_APOLLO_MAILBOX_SET_CTRL, (uint8_t *)cmd, sizeof(adi_apollo_mailbox_cmd_set_ctrl_t), (uint8_t *)resp, sizeof(adi_apollo_mailbox_resp_set_ctrl_t)); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_mailbox_enter_debug_mode(adi_apollo_device_t *device, adi_apollo_mailbox_cmd_enter_debug_mode_t *cmd, adi_apollo_mailbox_resp_enter_debug_mode_t *resp) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(cmd); + ADI_APOLLO_NULL_POINTER_RETURN(resp); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_mailbox_xfer(device, ADI_APOLLO_MAILBOX_ENTER_DEBUG_MODE, (uint8_t *)cmd, sizeof(adi_apollo_mailbox_cmd_enter_debug_mode_t), (uint8_t *)resp, sizeof(adi_apollo_mailbox_resp_enter_debug_mode_t)); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_mailbox_debug(adi_apollo_device_t *device, adi_apollo_mailbox_cmd_debug_t *cmd, adi_apollo_mailbox_resp_debug_t *resp) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(cmd); + ADI_APOLLO_NULL_POINTER_RETURN(resp); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_mailbox_xfer(device, ADI_APOLLO_MAILBOX_DEBUG, (uint8_t *)cmd, sizeof(adi_apollo_mailbox_cmd_debug_t), (uint8_t *)resp, sizeof(adi_apollo_mailbox_resp_debug_t)); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_mailbox_set_log_filters(adi_apollo_device_t *device, adi_apollo_mailbox_cmd_set_log_filters_t *cmd, adi_apollo_mailbox_resp_set_log_filters_t *resp) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(cmd); + ADI_APOLLO_NULL_POINTER_RETURN(resp); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_mailbox_xfer(device, ADI_APOLLO_MAILBOX_SET_LOG_FILTERS, (uint8_t *)cmd, sizeof(adi_apollo_mailbox_cmd_set_log_filters_t), (uint8_t *)resp, sizeof(adi_apollo_mailbox_resp_set_log_filters_t)); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_mailbox_resume_bkpt(adi_apollo_device_t *device, adi_apollo_mailbox_cmd_resume_bkpt_t *cmd, adi_apollo_mailbox_resp_resume_bkpt_t *resp) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(cmd); + ADI_APOLLO_NULL_POINTER_RETURN(resp); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_mailbox_xfer(device, ADI_APOLLO_MAILBOX_RESUME_BKPT, (uint8_t *)cmd, sizeof(adi_apollo_mailbox_cmd_resume_bkpt_t), (uint8_t *)resp, sizeof(adi_apollo_mailbox_resp_resume_bkpt_t)); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_mailbox_run_serdes_eye_sweep(adi_apollo_device_t *device, adi_apollo_mailbox_cmd_run_serdes_eye_sweep_t *cmd, adi_apollo_mailbox_resp_run_serdes_eye_sweep_t *resp) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(cmd); + ADI_APOLLO_NULL_POINTER_RETURN(resp); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_mailbox_xfer(device, ADI_APOLLO_MAILBOX_RUN_SERDES_EYE_SWEEP, (uint8_t *)cmd, sizeof(adi_apollo_mailbox_cmd_run_serdes_eye_sweep_t), (uint8_t *)resp, sizeof(adi_apollo_mailbox_resp_run_serdes_eye_sweep_t)); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_mailbox_run_serdes_vert_eye_sweep(adi_apollo_device_t *device, adi_apollo_mailbox_cmd_run_serdes_vert_eye_sweep_t *cmd, adi_apollo_mailbox_resp_run_serdes_vert_eye_sweep_t *resp) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(cmd); + ADI_APOLLO_NULL_POINTER_RETURN(resp); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_mailbox_xfer(device, ADI_APOLLO_MAILBOX_RUN_SERDES_VERT_EYE_SWEEP, (uint8_t *)cmd, sizeof(adi_apollo_mailbox_cmd_run_serdes_vert_eye_sweep_t), (uint8_t *)resp, sizeof(adi_apollo_mailbox_resp_run_serdes_vert_eye_sweep_t)); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_mailbox_set_gpio(adi_apollo_device_t *device, adi_apollo_mailbox_cmd_set_gpio_t *cmd, adi_apollo_mailbox_resp_set_gpio_t *resp) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(cmd); + ADI_APOLLO_NULL_POINTER_RETURN(resp); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_mailbox_xfer(device, ADI_APOLLO_MAILBOX_SET_GPIO, (uint8_t *)cmd, sizeof(adi_apollo_mailbox_cmd_set_gpio_t), (uint8_t *)resp, sizeof(adi_apollo_mailbox_resp_set_gpio_t)); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_mailbox_get_gpio(adi_apollo_device_t *device, adi_apollo_mailbox_cmd_get_gpio_t *cmd, adi_apollo_mailbox_resp_get_gpio_t *resp) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(cmd); + ADI_APOLLO_NULL_POINTER_RETURN(resp); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_mailbox_xfer(device, ADI_APOLLO_MAILBOX_GET_GPIO, (uint8_t *)cmd, sizeof(adi_apollo_mailbox_cmd_get_gpio_t), (uint8_t *)resp, sizeof(adi_apollo_mailbox_resp_get_gpio_t)); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_mailbox_mbias_pre_clock_init(adi_apollo_device_t *device, adi_apollo_mailbox_resp_mbias_pre_clock_init_t *resp) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(resp); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_mailbox_xfer(device, ADI_APOLLO_MAILBOX_MBIAS_PRE_CLOCK_INIT, NULL, 0, (uint8_t *)resp, sizeof(adi_apollo_mailbox_resp_mbias_pre_clock_init_t)); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_mailbox_mbias_post_clock_init(adi_apollo_device_t *device, adi_apollo_mailbox_resp_mbias_post_clock_init_t *resp) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(resp); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_mailbox_xfer(device, ADI_APOLLO_MAILBOX_MBIAS_POST_CLOCK_INIT, NULL, 0, (uint8_t *)resp, sizeof(adi_apollo_mailbox_resp_mbias_post_clock_init_t)); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_mailbox_sysclk_configuration(adi_apollo_device_t *device, adi_apollo_mailbox_resp_sysclk_configuration_t *resp) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(resp); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_mailbox_xfer(device, ADI_APOLLO_MAILBOX_SYSCLK_CONFIGURATION, NULL, 0, (uint8_t *)resp, sizeof(adi_apollo_mailbox_resp_sysclk_configuration_t)); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_mailbox_sysclk_conditioning(adi_apollo_device_t *device, adi_apollo_mailbox_cmd_sysclk_conditioning_t *cmd, adi_apollo_mailbox_resp_sysclk_conditioning_t *resp) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(cmd); + ADI_APOLLO_NULL_POINTER_RETURN(resp); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_mailbox_xfer(device, ADI_APOLLO_MAILBOX_SYSCLK_CONDITIONING, (uint8_t *)cmd, sizeof(adi_apollo_mailbox_cmd_sysclk_conditioning_t), (uint8_t *)resp, sizeof(adi_apollo_mailbox_resp_sysclk_conditioning_t)); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_mailbox_sysclk_switch_to_hsdig(adi_apollo_device_t *device, adi_apollo_mailbox_resp_sysclk_switch_to_hsdig_t *resp) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(resp); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_mailbox_xfer(device, ADI_APOLLO_MAILBOX_SYSCLK_SWITCH_TO_HSDIG, NULL, 0, (uint8_t *)resp, sizeof(adi_apollo_mailbox_resp_sysclk_switch_to_hsdig_t)); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_mailbox_master_bias_set_dac_bias_mode(adi_apollo_device_t *device, adi_apollo_mailbox_cmd_master_bias_set_dac_bias_mode_t *cmd, adi_apollo_mailbox_resp_master_bias_set_dac_bias_mode_t *resp) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(cmd); + ADI_APOLLO_NULL_POINTER_RETURN(resp); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_mailbox_xfer(device, ADI_APOLLO_MAILBOX_MASTER_BIAS_SET_DAC_BIAS_MODE, (uint8_t *)cmd, sizeof(adi_apollo_mailbox_cmd_master_bias_set_dac_bias_mode_t), (uint8_t *)resp, sizeof(adi_apollo_mailbox_resp_master_bias_set_dac_bias_mode_t)); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_mailbox_sysclk_switch_to_ringosc(adi_apollo_device_t *device, adi_apollo_mailbox_resp_sysclk_switch_to_ringosc_t *resp) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(resp); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_mailbox_xfer(device, ADI_APOLLO_MAILBOX_SYSCLK_SWITCH_TO_RINGOSC, NULL, 0, (uint8_t *)resp, sizeof(adi_apollo_mailbox_resp_sysclk_switch_to_ringosc_t)); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_mailbox_pgm_pll(adi_apollo_device_t *device, adi_apollo_mailbox_cmd_pgm_pll_t *cmd, adi_apollo_mailbox_resp_pgm_pll_t *resp) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(cmd); + ADI_APOLLO_NULL_POINTER_RETURN(resp); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_mailbox_xfer(device, ADI_APOLLO_MAILBOX_PGM_PLL, (uint8_t *)cmd, sizeof(adi_apollo_mailbox_cmd_pgm_pll_t), (uint8_t *)resp, sizeof(adi_apollo_mailbox_resp_pgm_pll_t)); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_mailbox_update_cal_data_crc(adi_apollo_device_t *device, adi_apollo_mailbox_resp_update_cal_data_crc_t *resp) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(resp); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_mailbox_xfer(device, ADI_APOLLO_MAILBOX_UPDATE_CAL_DATA_CRC, NULL, 0, (uint8_t *)resp, sizeof(adi_apollo_mailbox_resp_update_cal_data_crc_t)); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_mailbox_get_fw_version(adi_apollo_device_t *device, adi_apollo_mailbox_resp_get_fw_version_t *resp) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(resp); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_mailbox_xfer(device, ADI_APOLLO_MAILBOX_GET_FW_VERSION, NULL, 0, (uint8_t *)resp, sizeof(adi_apollo_mailbox_resp_get_fw_version_t)); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_mailbox_request_challenge(adi_apollo_device_t *device, adi_apollo_mailbox_cmd_request_challenge_t *cmd, adi_apollo_mailbox_resp_request_challenge_t *resp) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(cmd); + ADI_APOLLO_NULL_POINTER_RETURN(resp); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_mailbox_xfer(device, ADI_APOLLO_MAILBOX_REQUEST_CHALLENGE, (uint8_t *)cmd, sizeof(adi_apollo_mailbox_cmd_request_challenge_t), (uint8_t *)resp, sizeof(adi_apollo_mailbox_resp_request_challenge_t)); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_mailbox_set_challenge(adi_apollo_device_t *device, adi_apollo_mailbox_cmd_set_challenge_t *cmd, adi_apollo_mailbox_resp_set_challenge_t *resp) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(cmd); + ADI_APOLLO_NULL_POINTER_RETURN(resp); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_mailbox_xfer(device, ADI_APOLLO_MAILBOX_SET_CHALLENGE, (uint8_t *)cmd, sizeof(adi_apollo_mailbox_cmd_set_challenge_t), (uint8_t *)resp, sizeof(adi_apollo_mailbox_resp_set_challenge_t)); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_mailbox_power_up_jtx(adi_apollo_device_t *device, adi_apollo_mailbox_resp_power_up_jtx_t *resp) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(resp); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_mailbox_xfer(device, ADI_APOLLO_MAILBOX_POWER_UP_JTX, NULL, 0, (uint8_t *)resp, sizeof(adi_apollo_mailbox_resp_power_up_jtx_t)); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_mailbox_mcs_bsync_set_config(adi_apollo_device_t *device, adi_apollo_mailbox_cmd_mcs_bsync_set_config_t *cmd, adi_apollo_mailbox_resp_mcs_bsync_set_config_t *resp) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(cmd); + ADI_APOLLO_NULL_POINTER_RETURN(resp); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_mailbox_xfer(device, ADI_APOLLO_MAILBOX_MCS_BSYNC_SET_CONFIG, (uint8_t *)cmd, sizeof(adi_apollo_mailbox_cmd_mcs_bsync_set_config_t), (uint8_t *)resp, sizeof(adi_apollo_mailbox_resp_mcs_bsync_set_config_t)); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_mailbox_mcs_bsync_get_config(adi_apollo_device_t *device, adi_apollo_mailbox_resp_mcs_bsync_get_config_t *resp) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(resp); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_mailbox_xfer(device, ADI_APOLLO_MAILBOX_MCS_BSYNC_GET_CONFIG, NULL, 0, (uint8_t *)resp, sizeof(adi_apollo_mailbox_resp_mcs_bsync_get_config_t)); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_mailbox_mcs_bsync_go(adi_apollo_device_t *device, adi_apollo_mailbox_resp_mcs_bsync_go_t *resp) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(resp); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_mailbox_xfer(device, ADI_APOLLO_MAILBOX_MCS_BSYNC_GO, NULL, 0, (uint8_t *)resp, sizeof(adi_apollo_mailbox_resp_mcs_bsync_go_t)); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_mailbox_get_adc_slice_modes(adi_apollo_device_t *device, adi_apollo_mailbox_resp_get_adc_slice_modes_t *resp) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(resp); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_mailbox_xfer(device, ADI_APOLLO_MAILBOX_GET_ADC_SLICE_MODES, NULL, 0, (uint8_t *)resp, sizeof(adi_apollo_mailbox_resp_get_adc_slice_modes_t)); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_mailbox_set_adc_slice_mode_fast_switch_action(adi_apollo_device_t *device, adi_apollo_mailbox_cmd_set_adc_slice_mode_fast_switch_action_t *cmd, adi_apollo_mailbox_resp_set_adc_slice_mode_fast_switch_action_t *resp) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(cmd); + ADI_APOLLO_NULL_POINTER_RETURN(resp); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_mailbox_xfer(device, ADI_APOLLO_MAILBOX_SET_ADC_SLICE_MODE_FAST_SWITCH_ACTION, (uint8_t *)cmd, sizeof(adi_apollo_mailbox_cmd_set_adc_slice_mode_fast_switch_action_t), (uint8_t *)resp, sizeof(adi_apollo_mailbox_resp_set_adc_slice_mode_fast_switch_action_t)); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} +/*! @} */ \ No newline at end of file diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_mailbox_handler.c b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_mailbox_handler.c new file mode 100644 index 00000000000000..2fab7c6a5ae22d --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_mailbox_handler.c @@ -0,0 +1,156 @@ +/*! + * \brief APIs for MAILBOX + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_MAILBOX + * @{ + */ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_arm.h" +#include "adi_apollo_mailbox_handler.h" +#include "adi_apollo_mailbox_handler_local.h" + +#define USE_PRIVATE_BF +#include "adi_apollo_bf_core.h" +#include "adi_apollo_bf_custom.h" + +#include "adi_apollo_config.h" +#include "adi_apollo_hal.h" + +#define ADI_ADI_APOLLO_CPU1_MAILBOX_START 0x21000000 +#define ADI_ADI_APOLLO_RAM_BOOT_STEP_MAILBOX_INIT 48U +#define ADI_ADI_APOLLO_RAM_BOOT_STEP_MAILBOX_READY 52U + +/*==================== P U B L I C A P I C O D E ====================*/ + +int32_t adi_apollo_mailbox_ready_check(adi_apollo_device_t *device) +{ + int32_t err; + uint8_t boot_status = 0x00; + uint8_t prev_boot_status = 0x00; + int32_t i; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + for (i = 0; i < 100; i++) + { + err = adi_apollo_arm_ram_boot_error_check(device); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_arm_boot_status(device, &boot_status); + ADI_APOLLO_ERROR_RETURN(err); + + if (boot_status != prev_boot_status) { + ADI_APOLLO_LOG_MSG_VAR("Core 1 Ram Boot Status: 0x%02X", boot_status); + prev_boot_status = boot_status; + } + + if (boot_status >= ADI_ADI_APOLLO_RAM_BOOT_STEP_MAILBOX_READY) + { + err = API_CMS_ERROR_OK; + break; + } + + // delay 50ms + err = adi_apollo_hal_delay_us(device, 50000); + ADI_APOLLO_ERROR_RETURN(err); + + err = API_CMS_ERROR_ERROR; + } + + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_mailbox_busy_wait(adi_apollo_device_t *device) +{ + uint32_t delay_us = 1000; // 1ms polling delay + uint32_t max_delay_us = 15000000; // 15s timeout + return adi_apollo_hal_bf_wait_to_clear(device, BF_ARM1_SPI0_COMMAND_BUSY_INFO, max_delay_us, delay_us); +} + +int32_t adi_apollo_mailbox_read(adi_apollo_device_t *device, adi_apollo_mailbox_cmd_id_e cmd_id, uint8_t* ptr_resp, const size_t size_resp) +{ + + int32_t err; + uint32_t i; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_NULL_POINTER_RETURN(ptr_resp); + // ADI_APOLLO_LOG_FUNC(); + + /* Wait for non-busy state */ + err = adi_apollo_mailbox_busy_wait(device); + ADI_APOLLO_ERROR_RETURN(err); + + /* Read buffer */ + for (i = 0; i < size_resp; i++) + { + err = adi_apollo_hal_reg_get(device, (ADI_ADI_APOLLO_CPU1_MAILBOX_START + i), (ptr_resp + i)); + ADI_APOLLO_ERROR_RETURN(err); + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_mailbox_write(adi_apollo_device_t *device, adi_apollo_mailbox_cmd_id_e cmd_id, uint8_t* ptr_cmd, const size_t size_cmd) +{ + + int32_t err; + uint32_t i; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + if (size_cmd != 0) + ADI_APOLLO_NULL_POINTER_RETURN(ptr_cmd); + // ADI_APOLLO_LOG_FUNC(); + + /* Wait for non-busy state */ + err = adi_apollo_mailbox_busy_wait(device); + ADI_APOLLO_ERROR_RETURN(err); + + /* Write buffer */ + if (size_cmd != 0) + { + for (i = 0; i < size_cmd; i++) + { + err = adi_apollo_hal_reg_set(device, (ADI_ADI_APOLLO_CPU1_MAILBOX_START + i), *(ptr_cmd + i)); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + /* Write OPCODE */ + err = adi_apollo_hal_bf_set(device, BF_ARM1_SPI0_COMMAND_INFO, cmd_id); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; + +} + +int32_t adi_apollo_mailbox_xfer(adi_apollo_device_t *device, adi_apollo_mailbox_cmd_id_e cmd_id, uint8_t* ptr_cmd, const size_t size_cmd, uint8_t* ptr_resp, const size_t size_resp) +{ + + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + if (size_cmd != 0) + ADI_APOLLO_NULL_POINTER_RETURN(ptr_cmd); + ADI_APOLLO_NULL_POINTER_RETURN(ptr_resp); + // ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_mailbox_write(device, cmd_id, ptr_cmd, size_cmd); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_mailbox_read(device, cmd_id, ptr_resp, size_resp); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; + +} +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_mailbox_handler_local.h b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_mailbox_handler_local.h new file mode 100644 index 00000000000000..f4163bab4ef63d --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_mailbox_handler_local.h @@ -0,0 +1,39 @@ +/*! + * \brief MAILBOX Handler local defines and prototypes + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_MAILBOX_HANDLER_LOCAL + * @{ + */ +#ifndef __ADI_APOLLO_MAILBOX_HANDLER_LOCAL_H__ +#define __ADI_APOLLO_MAILBOX_HANDLER_LOCAL_H__ + +/*============= I N C L U D E S ============*/ + +/*============= D E F I N E S ==============*/ + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +int32_t adi_apollo_mailbox_busy_wait(adi_apollo_device_t *device); +int32_t adi_apollo_mailbox_read(adi_apollo_device_t *device, adi_apollo_mailbox_cmd_id_e cmd_id, uint8_t* ptr_resp, const size_t size_resp); +int32_t adi_apollo_mailbox_write(adi_apollo_device_t *device, adi_apollo_mailbox_cmd_id_e cmd_id, uint8_t* ptr_cmd, const size_t size_cmd); +int32_t adi_apollo_mailbox_xfer(adi_apollo_device_t *device, adi_apollo_mailbox_cmd_id_e cmd_id, uint8_t* ptr_cmd, const size_t size_cmd, uint8_t* ptr_resp, const size_t size_resp); + +#ifndef CLIENT_IGNORE +#endif /* CLIENT_IGNORE*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_MAILBOX_HANDLER_LOCAL_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_mcs_cal.c b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_mcs_cal.c new file mode 100644 index 00000000000000..ed2c27614fdc38 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_mcs_cal.c @@ -0,0 +1,551 @@ +/*! + * \brief APIs for Multi Chip Sync Calibration + * + * \copyright copyright(c) 2024 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_MCS_CAL + * @{ + */ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_mcs_cal.h" +#include "adi_apollo_mailbox.h" +#include "adi_apollo_config.h" +#include "adi_apollo_hal.h" + +/*==================== P U B L I C A P I C O D E ====================*/ +int32_t adi_apollo_mcs_cal_config_set(adi_apollo_device_t *device, adi_apollo_mcs_cal_config_t *cal_config) +{ + int32_t err = API_CMS_ERROR_ERROR; + uint8_t config_size = sizeof(adi_apollo_mcs_cal_config_t); + uint8_t expected_config_size = 96; // Expected byte size for adi_apollo_mcs_cal_config_t + uint8_t mcs_parameter_len = 4; // sub command like mcs_parameter has its length set to 4 bytes in set_ctrl_cmd.data_buffer[0:3]. + + adi_apollo_mailbox_cmd_set_ctrl_t set_ctrl_cmd = {0}; + adi_apollo_mailbox_resp_set_ctrl_t set_ctrl_resp = {0}; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(cal_config); + + if (config_size != expected_config_size) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_API, "MCS Cal Config struct size does not match! Expected: %d Got: %d.\n", expected_config_size, config_size); + return API_CMS_ERROR_INVALID_PARAM; + } + + set_ctrl_cmd.sys_cal_object_id = APOLLO_CPU_OBJID_TC_MCS; + set_ctrl_cmd.ctrl_cmd = CTRL_CMD_PARAM_SET; + set_ctrl_cmd.channel_num = 0; // For MCS config channel num isn't used, so set to 0. + set_ctrl_cmd.length = expected_config_size + mcs_parameter_len; + + memset(set_ctrl_cmd.data_buffer, 0, set_ctrl_cmd.length); // Clear data buffer + set_ctrl_cmd.data_buffer[0] = MCS_PARAMS_ALL; // \ref adi_apollo_mcs_parameter_e. 4 bytes for mcs_parameter. + set_ctrl_cmd.data_buffer[1] = 0; + set_ctrl_cmd.data_buffer[2] = 0; + set_ctrl_cmd.data_buffer[3] = 0; + + // Copy the cal_config struct data into the data_buffer + memcpy(&set_ctrl_cmd.data_buffer[4], cal_config, config_size); + + err = adi_apollo_mailbox_set_ctrl(device, &set_ctrl_cmd, &set_ctrl_resp); + ADI_APOLLO_ERROR_RETURN(err); + + if (set_ctrl_resp.status != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Mailbox Response Status Error from adi_apollo_mailbox_set_ctrl() 0x%X", set_ctrl_resp.status); + return API_CMS_ERROR_MAILBOX_RESP_STATUS; + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_mcs_cal_init_run(adi_apollo_device_t *device) +{ + int32_t err = API_CMS_ERROR_ERROR; + uint8_t i = 0; + adi_apollo_mailbox_cmd_run_init_t run_init_cmd = {0}; + adi_apollo_mailbox_resp_run_init_t run_init_resp = {0}; + adi_apollo_mailbox_resp_run_init_get_completion_t run_init_complete_resp = {0}; + adi_apollo_mailbox_resp_run_init_get_detailed_status_t run_init_cal_detailed_status_resp = {0}; + uint32_t max_delay_us = 60 * 1000000; + uint32_t poll_delay_us = 1000000; + uint32_t delay_us; + uint8_t cal_complete = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + run_init_cmd.cal_mask = APOLLO_INIT_CAL_MSK_IC_MCS; + run_init_cmd.rx_channel_mask = 0; + run_init_cmd.tx_channel_mask = 0; + run_init_cmd.serdes_rx_pack_mask = 0; + run_init_cmd.serdes_tx_pack_mask = 0; + run_init_cmd.linearx_chan_mask = 0; + + // Run the MCS init cal + adi_apollo_hal_log_write(device, ADI_CMS_LOG_API, "Starting MCS init cal\n"); + if (err = adi_apollo_mailbox_run_init(device, &run_init_cmd, &run_init_resp), err != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Error from adi_apollo_mailbox_run_init() %d.\n", err); + goto end; + } + + if (run_init_resp.status != APOLLO_CPU_NO_ERROR) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "MCS Init cal error code = %d.\n", run_init_resp.status); + err = API_CMS_ERROR_MAILBOX_RESP_STATUS; + goto end; + } + + // Wait for init cal to complete + for (delay_us = 0; delay_us < max_delay_us; delay_us += poll_delay_us) { + if (err = adi_apollo_mailbox_run_init_get_completion(device, &run_init_complete_resp), err != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Error from adi_apollo_mailbox_run_init_get_completion() %d.\n", err); + goto end; + } + + if ((delay_us % (5 * poll_delay_us)) == 0) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_API, "MCS Init Cal: status=%d in_progress=%d success=%d %ds.\n", + run_init_complete_resp.status, run_init_complete_resp.in_progress, run_init_complete_resp.success, (delay_us / poll_delay_us)); + } + + if (run_init_complete_resp.in_progress == 0) { + cal_complete = 1; + break; + } + + adi_apollo_hal_delay_us(device, poll_delay_us); + } + + if (run_init_complete_resp.success != 1) { + if (err = adi_apollo_mailbox_run_init_get_detailed_status(device, &run_init_cal_detailed_status_resp), err != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Error from adi_apollo_mailbox_run_init_get_detailed_status() %d.\n", err); + goto end; + } + + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "cpu_status = 0x%02X", run_init_cal_detailed_status_resp.status); + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "cals_duration_msec = %d", run_init_cal_detailed_status_resp.cals_duration_msec); + + // MCS init cal populates 1 index/channel data + for (i = 0; i < 1; ++i) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "init_err_codes[%d] = 0x%02X \t init_err_cals[%d] = 0x%02X", + i, run_init_cal_detailed_status_resp.init_err_codes[i], i, run_init_cal_detailed_status_resp.init_err_cals[i]); + // adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "cals_since_power_ups[%d] = %d \t cals_last_runs[%d] = %d", + // i, run_init_cal_detailed_status_resp.cals_since_power_up[i], i, run_init_cal_detailed_status_resp.cals_last_run[i]); + } + } + + if (cal_complete) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_API, "MCS Init cal completed %s in %ds\n", + run_init_complete_resp.success ? "successfully" : "w/ ERROR", delay_us / 1000000); + err = run_init_complete_resp.success ? API_CMS_ERROR_OK : API_CMS_ERROR_MCS_INIT_CAL_ERROR; + goto end; + } else { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "MCS Init cal timeout after %ds\n", max_delay_us / 1000000); + err = API_CMS_ERROR_MCS_CAL_TIMEOUT; + goto end; + } + +end: + return err; +} + +int32_t adi_apollo_mcs_cal_init_status_get(adi_apollo_device_t *device, adi_apollo_mcs_cal_init_status_t *cal_status) +{ + int32_t err = API_CMS_ERROR_ERROR; + adi_apollo_mailbox_cmd_get_cal_status_t cal_status_cmd = {0}; + adi_apollo_mailbox_resp_get_cal_status_t cal_status_resp = {0}; + uint8_t cal_status_size = sizeof(adi_apollo_mcs_cal_init_status_t); + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(cal_status); + + // CAL_STATUS_SPECIFIC will let apollo_fw know that we want all of MCC FW CalData. Not just error codes. + cal_status_cmd.cal_status_type = CAL_STATUS_SPECIFIC; + + // MCS Cal type: init cal. + cal_status_cmd.sys_cal_object_id = APOLLO_CPU_OBJID_IC_MCS; + + // For MCS config channel num isn't used, so set to 0. + cal_status_cmd.channel_num = 0; + + if (err = adi_apollo_mailbox_get_cal_status(device, &cal_status_cmd, &cal_status_resp), err != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Error from adi_apollo_mailbox_get_cal_status() %d.\n", err); + goto end; + } + + // Check if the cal status response matches the size of adi_apollo_mcs_cal_init_status_t struct. + if (cal_status_size != cal_status_resp.length) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_API, "MCS Init Cal Status Data buffer size does not match! Expected: %d Got: %d.\n", cal_status_size, cal_status_resp.length); + err = API_CMS_ERROR_MAILBOX_RESP_STATUS; + goto end; + } + + memcpy(cal_status, cal_status_resp.data_buffer, cal_status_resp.length); + +end: + return err; +} + +int32_t adi_apollo_mcs_cal_parameter_set(adi_apollo_device_t *device, adi_apollo_mcs_parameter_e mcs_parameter, uint64_t data) +{ + int32_t err = API_CMS_ERROR_ERROR; + uint8_t i = 0; + adi_apollo_mailbox_cmd_set_ctrl_t set_ctrl_cmd = {0}; + adi_apollo_mailbox_resp_set_ctrl_t set_ctrl_resp = {0}; + uint8_t mcs_parameter_len = 4; // sub command like mcs_parameter has its length set to 4 bytes in set_ctrl_cmd.data_buffer[0:3]. + uint8_t parameter_data_len = 8; // 8 bytes for mcs_parameter data in set_ctrl_cmd.data_buffer[4:11]. + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + set_ctrl_cmd.sys_cal_object_id = APOLLO_CPU_OBJID_TC_MCS; + set_ctrl_cmd.ctrl_cmd = CTRL_CMD_PARAM_SET; + set_ctrl_cmd.channel_num = 0; // For MCS config channel num isn't used, so set to 0. + set_ctrl_cmd.length = mcs_parameter_len + parameter_data_len; + + memset(set_ctrl_cmd.data_buffer, 0, set_ctrl_cmd.length); // Clear data buffer + set_ctrl_cmd.data_buffer[0] = mcs_parameter; // \ref adi_apollo_mcs_parameter_e + set_ctrl_cmd.data_buffer[1] = 0; + set_ctrl_cmd.data_buffer[2] = 0; + set_ctrl_cmd.data_buffer[3] = 0; + + for (i = 0; i < parameter_data_len; ++i) { + set_ctrl_cmd.data_buffer[4 + i] = (data >> (8 * i)) & 0xFF; + } + + err = adi_apollo_mailbox_set_ctrl(device, &set_ctrl_cmd, &set_ctrl_resp); + ADI_APOLLO_ERROR_RETURN(err); + + if (set_ctrl_resp.status != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Mailbox Response Status Error from adi_apollo_mailbox_set_ctrl() 0x%X", set_ctrl_resp.status); + return API_CMS_ERROR_MAILBOX_RESP_STATUS; + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_mcs_cal_tracking_decimation_set(adi_apollo_device_t *device, uint16_t decimation) +{ + int32_t err = API_CMS_ERROR_ERROR; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_mcs_cal_parameter_set(device, MCS_MEASUREMENT_DECIMATION_RATE_UINT16, decimation); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_mcs_cal_tracking_enable(adi_apollo_device_t *device, uint8_t enable) +{ + int32_t err = API_CMS_ERROR_ERROR; + adi_apollo_mailbox_cmd_set_enabled_tracking_cals_t cmd = {0}; + adi_apollo_mailbox_resp_set_enabled_tracking_cals_t resp = {0}; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(enable > 1); + + cmd.serdes_rx_pack_mask = 0; // For MCS tracking, serdes mask isn't used, so set to 0. + cmd.adc_rx_channel_mask = 0; // For MCS tracking, channel mask isn't used, so set to 0. + cmd.mcs_tc_mask = 1; + cmd.enable_disable = enable; + + err = adi_apollo_mailbox_set_enabled_tracking_cals(device, &cmd, &resp); + ADI_APOLLO_ERROR_RETURN(err); + + if (resp.status != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Mailbox Response Status Error from adi_apollo_mailbox_set_enabled_tracking_cals() 0x%X", resp.status); + return API_CMS_ERROR_MAILBOX_RESP_STATUS; + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_mcs_cal_tracking_initialize_set(adi_apollo_device_t *device) +{ + int32_t err = API_CMS_ERROR_ERROR; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_mcs_cal_parameter_set(device, MCS_TRACK_INITIALIZE_UINT8, 1); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_mcs_cal_fg_tracking_run(adi_apollo_device_t *device) +{ + int32_t err = API_CMS_ERROR_ERROR; + uint8_t i = 0; + adi_apollo_mcs_cal_status_t tracking_cal_status = {{0}}; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_mcs_cal_parameter_set(device, MCS_TRACK_FOREGROUND_UINT8, 1); + ADI_APOLLO_ERROR_RETURN(err); + + // Wait for fg tracking cal to complete + for (i = 0; i < 60; ++i) { + err = adi_apollo_mcs_cal_tracking_status_get(device, &tracking_cal_status); + ADI_APOLLO_ERROR_RETURN(err); + + if ((i > 0) && ((i % 5) == 0)) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_API, "MCS FG Tracking Cal: foreground_done = %d. %dsec.\n", + tracking_cal_status.mcs_tracking_cal_status.foreground_done, i); + } + + if ((tracking_cal_status.mcs_tracking_cal_status.foreground_done == 1) && (tracking_cal_status.hdr.errorCode == 0)) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_API, "MCS FG Tracking Cal: foreground_done = %d. %dsec.\n", + tracking_cal_status.mcs_tracking_cal_status.foreground_done, i); + break; + } + + adi_apollo_hal_delay_us(device, 1 * 1000000); + } + + if (tracking_cal_status.mcs_tracking_cal_status.foreground_done != 1) { + return API_CMS_ERROR_MCS_CAL_TIMEOUT; + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_mcs_cal_bg_tracking_run(adi_apollo_device_t *device) +{ + int32_t err = API_CMS_ERROR_ERROR; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_mcs_cal_parameter_set(device, MCS_TRACK_BACKGROUND_0_UINT8, 1); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_mcs_cal_bg_tracking_freeze(adi_apollo_device_t *device) +{ + int32_t err = API_CMS_ERROR_ERROR; + uint8_t i = 0; + adi_apollo_mcs_cal_status_t tracking_cal_status = {{0}}; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_mcs_cal_parameter_set(device, MCS_TRACK_HALT_UINT8, 1); + ADI_APOLLO_ERROR_RETURN(err); + + // Wait for bg tracking cal to halt + for (i = 0; i < 60; ++i) { + err = adi_apollo_mcs_cal_tracking_status_get(device, &tracking_cal_status); + ADI_APOLLO_ERROR_RETURN(err); + + if ((i > 0) && ((i % 5) == 0)) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_API, "MCS BG Tracking Cal: halt_active = %d. %dsec.\n", + tracking_cal_status.mcs_tracking_cal_status.halt_active, i); + } + + if ((tracking_cal_status.mcs_tracking_cal_status.halt_active == 1) && (tracking_cal_status.hdr.errorCode == 0)) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_API, "MCS BG Tracking Cal: halt_active = %d. %dsec.\n", + tracking_cal_status.mcs_tracking_cal_status.halt_active, i); + break; + } + + adi_apollo_hal_delay_us(device, 1 * 1000000); + } + + if (tracking_cal_status.mcs_tracking_cal_status.halt_active != 1) { + return API_CMS_ERROR_MCS_CAL_TIMEOUT; + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_mcs_cal_bg_tracking_unfreeze(adi_apollo_device_t *device) +{ + int32_t err = API_CMS_ERROR_ERROR; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_mcs_cal_parameter_set(device, MCS_TRACK_HALT_UINT8, 0); + ADI_APOLLO_ERROR_RETURN(err); + + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_mcs_cal_bg_tracking_abort(adi_apollo_device_t *device) +{ + int32_t err = API_CMS_ERROR_ERROR; + uint8_t i = 0; + adi_apollo_mcs_cal_status_t tracking_cal_status = {{0}}; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_mcs_cal_parameter_set(device, MCS_TRACK_ABORT_UINT8, 1); + ADI_APOLLO_ERROR_RETURN(err); + + // Wait for bg tracking cal to halt + for (i = 0; i < 60; ++i) { + err = adi_apollo_mcs_cal_tracking_status_get(device, &tracking_cal_status); + ADI_APOLLO_ERROR_RETURN(err); + + if ((i > 0) && ((i % 5) == 0)) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_API, "MCS BG Tracking Cal: abort_done = %d. %dsec.\n", + tracking_cal_status.mcs_tracking_cal_status.abort_done, i); + } + + if ((tracking_cal_status.mcs_tracking_cal_status.abort_done == 1) && (tracking_cal_status.hdr.errorCode == 0)) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_API, "MCS BG Tracking Cal: abort_done = %d. %dsec.\n", + tracking_cal_status.mcs_tracking_cal_status.abort_done, i); + break; + } + + adi_apollo_hal_delay_us(device, 1 * 1000000); + } + + if (tracking_cal_status.mcs_tracking_cal_status.abort_done != 1) { + return API_CMS_ERROR_MCS_CAL_TIMEOUT; + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_mcs_cal_force_fg_tracking_run(adi_apollo_device_t *device) +{ + int32_t err = API_CMS_ERROR_ERROR; + uint8_t i = 0; + adi_apollo_mcs_cal_status_t tracking_cal_status = {{0}}; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_mcs_cal_parameter_set(device, MCS_TRACK_FORCE_FOREGROUND_UINT8, 1); + ADI_APOLLO_ERROR_RETURN(err); + + // Wait for fg tracking cal to complete + for (i = 0; i < 60; ++i) { + err = adi_apollo_mcs_cal_tracking_status_get(device, &tracking_cal_status); + ADI_APOLLO_ERROR_RETURN(err); + + if ((i > 0) && ((i % 5) == 0)) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_API, "MCS Forced FG Tracking Cal: foreground_done = %d. %dsec.\n", + tracking_cal_status.mcs_tracking_cal_status.foreground_done, i); + } + + if ((tracking_cal_status.mcs_tracking_cal_status.foreground_done == 1) && (tracking_cal_status.hdr.errorCode == 0)) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_API, "MCS Forced FG Tracking Cal: foreground_done = %d. %dsec.\n", + tracking_cal_status.mcs_tracking_cal_status.foreground_done, i); + break; + } + + adi_apollo_hal_delay_us(device, 1 * 1000000); + } + + if (tracking_cal_status.mcs_tracking_cal_status.foreground_done != 1) { + return API_CMS_ERROR_MCS_CAL_TIMEOUT; + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_mcs_cal_force_bg_tracking_run(adi_apollo_device_t *device) +{ + int32_t err = API_CMS_ERROR_ERROR; + uint8_t i = 0; + adi_apollo_mcs_cal_status_t tracking_cal_status = {{0}}; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_mcs_cal_parameter_set(device, MCS_TRACK_FORCE_BACKGROUND_STEP_0_UINT8, 1); + ADI_APOLLO_ERROR_RETURN(err); + + // Wait for fg tracking cal to complete + for (i = 0; i < 60; ++i) { + err = adi_apollo_mcs_cal_tracking_status_get(device, &tracking_cal_status); + ADI_APOLLO_ERROR_RETURN(err); + + if ((i > 0) && ((i % 5) == 0)) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_API, "MCS Forced BG Tracking Cal: force_background_done[0] = %d. %dsec.\n", + tracking_cal_status.mcs_tracking_cal_status.force_background_done[0], i); + } + + if ((tracking_cal_status.mcs_tracking_cal_status.force_background_done[0] == 1) && (tracking_cal_status.hdr.errorCode == 0)) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_API, "MCS Forced BG Tracking Cal: force_background_done[0] = %d. %dsec.\n", + tracking_cal_status.mcs_tracking_cal_status.force_background_done[0], i); + break; + } + + adi_apollo_hal_delay_us(device, 1 * 1000000); + } + + if (tracking_cal_status.mcs_tracking_cal_status.force_background_done[0] != 1) { + return API_CMS_ERROR_MCS_CAL_TIMEOUT; + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_mcs_cal_coarse_jump_set(adi_apollo_device_t *device) +{ + int32_t err = API_CMS_ERROR_ERROR; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_mcs_cal_parameter_set(device, MCS_TRACK_COARSE_JUMP_0_UINT8, 1); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_mcs_cal_tracking_status_get(adi_apollo_device_t *device, adi_apollo_mcs_cal_status_t *cal_status) +{ + int32_t err = API_CMS_ERROR_ERROR; + adi_apollo_mailbox_cmd_get_cal_status_t cal_status_cmd = {0}; + adi_apollo_mailbox_resp_get_cal_status_t cal_status_resp = {0}; + uint8_t cal_status_size = sizeof(adi_apollo_mcs_cal_status_t); + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(cal_status); + + // CAL_STATUS_SPECIFIC will let apollo_fw know that we want all of MCC FW CalData. Not just error codes. + cal_status_cmd.cal_status_type = CAL_STATUS_SPECIFIC; + + // MCS Cal type: tracking cal. + cal_status_cmd.sys_cal_object_id = APOLLO_CPU_OBJID_TC_MCS; + + // For MCS config channel num isn't used, so set to 0. + cal_status_cmd.channel_num = 0; + + if (err = adi_apollo_mailbox_get_cal_status(device, &cal_status_cmd, &cal_status_resp), err != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Error from adi_apollo_mailbox_get_cal_status() %d.\n", err); + goto end; + } + + // Check if the cal status response matches the size of adi_apollo_mcs_cal_status_t struct. + if (cal_status_size != cal_status_resp.length) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_API, "MCS Tracking Cal Status Data buffer size does not match! Expected: %d Got: %d.\n", cal_status_size, cal_status_resp.length); + err = API_CMS_ERROR_MCS_TRACK_CAL_ERROR; + goto end; + } + + memcpy(cal_status, cal_status_resp.data_buffer, cal_status_resp.length); + +end: + return err; +} + +/*! @} */ \ No newline at end of file diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_nco_local.h b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_nco_local.h new file mode 100644 index 00000000000000..1e83b542cd9ec5 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_nco_local.h @@ -0,0 +1,40 @@ +/*! + * \brief NCO local defines and prototypes + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_CNCO + * @{ + */ +#ifndef __ADI_APOLLO_NCO_LOCAL_H__ +#define __ADI_APOLLO_NCO_LOCAL_H__ + +/*============= I N C L U D E S ============*/ + +/*============= D E F I N E S ==============*/ + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +uint32_t calc_rx_cnco_base(int32_t idx); +uint32_t calc_rx_fnco_base(int32_t idx); +uint32_t calc_tx_cnco_base(int32_t idx); +uint32_t calc_tx_fnco_base(int32_t idx); + + +#ifndef CLIENT_IGNORE +#endif /* CLIENT_IGNORE*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_NCO_LOCAL_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_pfilt.c b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_pfilt.c new file mode 100644 index 00000000000000..03d5a5586696a5 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_pfilt.c @@ -0,0 +1,785 @@ +/*! + * \brief APIs for PFILT + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_PFILT + * @{ + */ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_pfilt.h" +#include "adi_apollo_pfilt_local.h" +#include "adi_apollo_private_device.h" +#include "adi_apollo_private_blk_sel_types.h" + +#include "adi_apollo_bf_txrx_pfilt_top.h" +#include "adi_apollo_bf_txrx_pfilt_coeff.h" +#include "adi_apollo_bf_custom.h" + +#include "adi_apollo_config.h" +#include "adi_apollo_hal.h" +#include "adi_utils.h" + +static int32_t write_bank(adi_apollo_device_t *device, uint32_t bank_num, uint32_t regmap_base_addr, int first_idx, int16_t ceoffs[], uint32_t n_taps); + +typedef struct +{ + uint16_t n_taps; + uint16_t idx[ADI_APOLLO_PFILT_STREAMS_NUM]; + uint16_t idx_fmtx[ADI_APOLLO_PFILT_STREAMS_NUM]; +} stream_mode_loc_map_t; + +static const stream_mode_loc_map_t stream_mode_loc_map[] = { + {32, {0, 16}, {0, 0}}, // N tap + {16, {0, 16}, {0, 0}}, // N/2 tap + { 8, {0, 16}, {0, 0}}, // N/4 tap + {16, {0, 16}, {0, 0}}, // Half-Matrix + { 8, {0, 16}, {8, 24}} // Full-Matrix +}; + +/* Map pfilt mode enum to coeff layout for that mode */ +static const int pfilt_mode_to_idx[8] = { + 0, // bypass, n/a + 2, // n/4 tap + 1, // n/2 tap + 0, // n/a + 4, // full matrix + 0, // n/a + 3, // half-cmplx + 0 // n tap +}; + +/*==================== P U B L I C A P I C O D E ====================*/ + +int32_t adi_apollo_pfilt_mode_pgm(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t pfilts, adi_apollo_pfilt_mode_pgm_t *config) +{ + int32_t err; + uint8_t i; + adi_apollo_blk_sel_t pfilt; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_DEV_FEAT_LOCKOUT_RETURN(terminal, ADI_APOLLO_EC_PFILT_LOCK); + ADI_APOLLO_PFILT_BLK_SEL_MASK(pfilts); + + /* Common bitfield for 0 & 1 pfilts */ + for(i = 0; i < ADI_APOLLO_PFILT_NUM; i += 2) { + pfilt = pfilts & ((ADI_APOLLO_PFILT_A0 << i) | (ADI_APOLLO_PFILT_A0 << (i+1))); + if (pfilt > 0) { + regmap_base_addr = calc_pfilt_base(terminal, i); + + err = adi_apollo_hal_bf_set(device, BF_QUAD_MODE_INFO(regmap_base_addr), config->dq_mode); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_REAL_DATA_INFO(regmap_base_addr), config->data); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_MODE_SWITCH_INFO(regmap_base_addr), config->mode_switch); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_ADD_SUB_SEL_INFO(regmap_base_addr), config->add_sub_sel); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + /* + * 4t4r: Program for n=0; + * 8t8r ADC pair 0: Program for n=0; + * 8t8r ADC pair 1: Program for n=1 + */ + for(i = 0; i < ADI_APOLLO_PFILT_NUM; i ++) { + pfilt = pfilts & (ADI_APOLLO_PFILT_A0 << i); + if (pfilt > 0) { + regmap_base_addr = calc_pfilt_base(terminal, i); + + /* v10 + * A0 and B0 get i/q_mode[0] + * A1 and B1 get i/q_mode[1] + */ + err = adi_apollo_hal_bf_set(device, BF_PFIR_I_MODE_INFO(regmap_base_addr, i%2), config->pfir_i_mode[i%2]); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_PFIR_Q_MODE_INFO(regmap_base_addr, i%2), config->pfir_q_mode[i%2]); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_pfilt_gain_dly_pgm(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t pfilts, uint8_t pfilt_banks, adi_apollo_pfilt_gain_dly_pgm_t *config) +{ + int32_t err; + uint8_t i, j, pfilt_bank, pfilt_local; + adi_apollo_blk_sel_t pfilt; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_DEV_FEAT_LOCKOUT_RETURN(terminal, ADI_APOLLO_EC_PFILT_LOCK); + ADI_APOLLO_PFILT_BLK_SEL_MASK(pfilts); + + /* + * for each of the pfilts (4 for 8T8R: A0/A1/B0/B1, 2 for 4T4R: A0/B0) + * for each of the 4 banks supported in each pfilt + * set the parameters gain/scalar-gain/delay + * + * 4t4r: Program n=0 for 1st coeff bank; + * 4t4r: Program n=1 for 2nd coeff bank; + * 4t4r: Program n=2 for 3rd coeff bank; + * 4t4r: Program n=3 for 4th coeff bank; + * + * 8t8r: Program n=0 for 1st coeff bank of ADC pair 0; + * 8t8r: Program n=1 for 2nd coeff bank of ADC pair 0; + * 8t8r: Program n=2 for 3rd coeff bank of ADC pair 0; + * 8t8r: Program n=3 for 4th coeff bank of ADC pair 0; + * 8t8r: Program n=4 for 1st coeff bank of ADC pair 1; + * 8t8r: Program n=5 for 2nd coeff bank of ADC pair 1; + * 8t8r: Program n=6 for 3rd coeff bank of ADC pair 1; + * 8t8r: Program n=7 for 4th coeff bank of ADC pair 1; + */ + for(i = 0; i < ADI_APOLLO_PFILT_NUM; i ++) { + pfilt = pfilts & (ADI_APOLLO_PFILT_A0 << i); + if (pfilt > 0) { + /* base of pfilt */ + regmap_base_addr = calc_pfilt_base(terminal, i); + + /* For each of the banks supported in a pfilt */ + for(j = 0; j < ADI_APOLLO_PFILT_BANK_NUM; j ++) { + pfilt_bank = pfilt_banks & (ADI_APOLLO_PFILT_BANK0 < 0) { + /* i: 0 to 3 + * (i % ADI_APOLLO_PFILT_PER_SIDE): 0, 1, 0, 1 + * (i % ADI_APOLLO_PFILT_PER_SIDE) * ADI_APOLLO_PFILT_BANK_NUM: 0, 4, 0, 4 + * pfilt_local: 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 (the bank index) + * */ + pfilt_local = (((i%ADI_APOLLO_PFILT_PER_SIDE)*ADI_APOLLO_PFILT_BANK_NUM) + j); + + err = adi_apollo_hal_bf_set(device, BF_PFIR_IX_GAIN_INFO(regmap_base_addr, pfilt_local), config->pfir_ix_gain); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_PFIR_IY_GAIN_INFO(regmap_base_addr, pfilt_local), config->pfir_iy_gain); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_PFIR_QX_GAIN_INFO(regmap_base_addr, pfilt_local), config->pfir_qx_gain); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_PFIR_QY_GAIN_INFO(regmap_base_addr, pfilt_local), config->pfir_qy_gain); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_PFIR_IX_SCALAR_GAIN_INFO(regmap_base_addr, pfilt_local), config->pfir_ix_scalar_gain); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_PFIR_IY_SCALAR_GAIN_INFO(regmap_base_addr, pfilt_local), config->pfir_iy_scalar_gain); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_PFIR_QX_SCALAR_GAIN_INFO(regmap_base_addr, pfilt_local), config->pfir_qx_scalar_gain); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_PFIR_QY_SCALAR_GAIN_INFO(regmap_base_addr, pfilt_local), config->pfir_qy_scalar_gain); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_HC_PROG_DELAY_INFO(regmap_base_addr, pfilt_local), config->hc_delay); + ADI_APOLLO_ERROR_RETURN(err); + } + } + } + } + return API_CMS_ERROR_OK; +} + +/* + * This function programs a set of length coefficients into a BANK + * + * For each side of the chip (A and B) + * For each of Tx and Rx * + * For 4T4R + * There is one PFIR called A0 on side A and one PFIR called B0 on side B + * The PFIR has 4 coefficients sets associated with it + * (on Side A, these are at 0x60360000, 0x60360040, 0x60560000, 0x60560040) + * (on Side B, these are at 0x60B60000, 0x60B60040, 0x60D60000, 0x60D60040) + * For 8T8R + * There is one additional PFIR called A1 on side A and one additional PFIR called B1 on side B + * This additional PFIR has 4 coefficients sets associated with it + * (e.g. on Side A, these are at 0x60361000, 0x60361040, 0x60561000, 0x60561040) + * (e.g. on Side B, these are at 0x60B61000, 0x60B61040, 0x60D61000, 0x60D61040) + * + * So, in summary: + * There are 4 sets of coefficients (4 x 32 x int16) on each side of the chip, for Tx and Rx separately for a 4T4R chip + * There are 8 sets of coefficients (8 x 32 x int16) on each side of the chip, for Tx and Rx separately for a 8T8R chip + * + * This function gets these parameters: + * RX/Tx + * A 4 bit mask that indicates which of the A0/A1/B0/B1 coefficient sets are to be written to with the coefficients - pfilts is a 4 bit value: B1:B0:A1:A0 + * pfilt_banks: This is a 4 bit field indicating which banks to write to within the PFIR (3:2:1:0) with the coefficients + * */ +int32_t adi_apollo_pfilt_coeff_pgm(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t pfilts, uint8_t pfilt_banks, int16_t pfilt_coeff[], uint32_t length) +{ + int32_t err; + uint8_t i, j, k, pfilt_bank; + adi_apollo_blk_sel_t pfilt; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_DEV_FEAT_LOCKOUT_RETURN(terminal, ADI_APOLLO_EC_PFILT_LOCK); + ADI_APOLLO_INVALID_PARAM_RETURN(length > ADI_APOLLO_PFILT_COEFF_NUM); + ADI_APOLLO_PFILT_BLK_SEL_MASK(pfilts); + + for(i = 0; i < ADI_APOLLO_PFILT_NUM; i ++) { + pfilt = pfilts & (ADI_APOLLO_PFILT_A0 << i); + if (pfilt > 0) { + for(j = 0; j < ADI_APOLLO_PFILT_BANK_NUM; j ++) { + pfilt_bank = pfilt_banks & (ADI_APOLLO_PFILT_BANK0 < 0) { + regmap_base_addr = calc_pfilt_coeff_base(terminal, (i*ADI_APOLLO_PFILT_BANK_NUM)+j); + if (j % ADI_APOLLO_PFILT_BANKS_PER_REGMAP == 0) { //BANK0 and BANK2 + for(k = 0; k < length; k++) { + err = adi_apollo_hal_bf_set(device, BF_COEFF_0_INFO(regmap_base_addr, k), pfilt_coeff[k]); + ADI_APOLLO_ERROR_RETURN(err); + } + } + else { //BANK1 and BANK3 + for(k = 0; k < length; k++) { + err = adi_apollo_hal_bf_set(device, BF_COEFF_1_INFO(regmap_base_addr, k), pfilt_coeff[k]); + ADI_APOLLO_ERROR_RETURN(err); + } + } + } + } + } + } + return API_CMS_ERROR_OK; + +} + +int32_t adi_apollo_pfilt_coeff_ntap_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t pfilts, uint8_t pfilt_banks, + uint16_t streams, adi_apollo_pfilt_mode_e mode, int16_t coeffs[], uint32_t coeffs_len) +{ + int32_t err; + uint8_t i, j, s, pfilt_bank; + adi_apollo_blk_sel_t pfilt; + uint32_t regmap_base_addr = 0; + stream_mode_loc_map_t stream_ceoff_loc; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_DEV_FEAT_LOCKOUT_RETURN(terminal, ADI_APOLLO_EC_PFILT_LOCK); + ADI_APOLLO_NULL_POINTER_RETURN(coeffs); + ADI_APOLLO_INVALID_PARAM_RETURN(terminal > ADI_APOLLO_TX); + ADI_APOLLO_INVALID_PARAM_RETURN(pfilts & ~ADI_APOLLO_PFILT_ALL); + ADI_APOLLO_INVALID_PARAM_RETURN(pfilt_banks & ~ADI_APOLLO_PFILT_BANK_ALL); + ADI_APOLLO_INVALID_PARAM_RETURN(streams & ~ADI_APOLLO_PFILT_STREAM_ALL); + ADI_APOLLO_INVALID_PARAM_RETURN(!((mode == ADI_APOLLO_PFILT_MODE_N_REAL) || (mode == ADI_APOLLO_PFILT_MODE_N_DIV_BY_2_REAL) || (mode == ADI_APOLLO_PFILT_MODE_N_DIV_BY_4_REAL))); + ADI_APOLLO_INVALID_PARAM_RETURN((mode == ADI_APOLLO_PFILT_MODE_N_REAL) && ((coeffs_len != 32) || (adi_api_utils_num_selected(streams) != 1)) ); + ADI_APOLLO_INVALID_PARAM_RETURN((mode == ADI_APOLLO_PFILT_MODE_N_DIV_BY_2_REAL) && (coeffs_len != 16)); + ADI_APOLLO_INVALID_PARAM_RETURN((mode == ADI_APOLLO_PFILT_MODE_N_DIV_BY_4_REAL) && (coeffs_len != 8)); + ADI_APOLLO_PFILT_BLK_SEL_MASK(pfilts); + + /* Get coeff bank location info for given mode */ + stream_ceoff_loc = stream_mode_loc_map[pfilt_mode_to_idx[mode]]; + + for (i = 0; i < ADI_APOLLO_PFILT_NUM; i++) { + pfilt = pfilts & (ADI_APOLLO_PFILT_A0 << i); + if (pfilt > 0) { + for (j = 0; j < ADI_APOLLO_PFILT_BANK_NUM; j++) { + pfilt_bank = pfilt_banks & (ADI_APOLLO_PFILT_BANK0 << j); + if (pfilt_bank > 0) { + regmap_base_addr = calc_pfilt_coeff_base(terminal, (i * ADI_APOLLO_PFILT_BANK_NUM) + j); + for (s = 0; s < ADI_APOLLO_PFILT_STREAMS_NUM; s++) { + if (streams & (ADI_APOLLO_PFILT_STREAM_0 << s)) { + err = write_bank(device, j, regmap_base_addr, stream_ceoff_loc.idx[s], coeffs, stream_ceoff_loc.n_taps); + ADI_APOLLO_ERROR_RETURN(err); + } + } + } + } + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_pfilt_coeff_half_complex_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t pfilts, uint8_t pfilt_banks, + int16_t coeffs0[], int16_t coeffs1[], uint32_t coeffs_len) +{ + int32_t err; + uint8_t i, j, pfilt_bank; + adi_apollo_blk_sel_t pfilt; + uint32_t regmap_base_addr = 0; + stream_mode_loc_map_t stream_ceoff_loc; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_DEV_FEAT_LOCKOUT_RETURN(terminal, ADI_APOLLO_EC_PFILT_LOCK); + ADI_APOLLO_NULL_POINTER_RETURN(coeffs0); + ADI_APOLLO_NULL_POINTER_RETURN(coeffs1); + ADI_APOLLO_INVALID_PARAM_RETURN(terminal > ADI_APOLLO_TX); + ADI_APOLLO_INVALID_PARAM_RETURN(pfilts & ~ADI_APOLLO_PFILT_ALL); + ADI_APOLLO_INVALID_PARAM_RETURN(pfilt_banks & ~ADI_APOLLO_PFILT_BANK_ALL); + ADI_APOLLO_INVALID_PARAM_RETURN(coeffs_len != 16); + ADI_APOLLO_PFILT_BLK_SEL_MASK(pfilts); + + /* Get coeff bank location info for half-complex */ + stream_ceoff_loc = stream_mode_loc_map[pfilt_mode_to_idx[ADI_APOLLO_PFILT_MODE_HALF_COMPLEX]]; + + for (i = 0; i < ADI_APOLLO_PFILT_NUM; i++) { + pfilt = pfilts & (ADI_APOLLO_PFILT_A0 << i); + if (pfilt > 0) { + for (j = 0; j < ADI_APOLLO_PFILT_BANK_NUM; j++) { + pfilt_bank = pfilt_banks & (ADI_APOLLO_PFILT_BANK0 << j); + if (pfilt_bank > 0) { + regmap_base_addr = calc_pfilt_coeff_base(terminal, (i * ADI_APOLLO_PFILT_BANK_NUM) + j); + err = write_bank(device, j, regmap_base_addr, stream_ceoff_loc.idx[0], coeffs0, stream_ceoff_loc.n_taps); + ADI_APOLLO_ERROR_RETURN(err); + err = write_bank(device, j, regmap_base_addr, stream_ceoff_loc.idx[1], coeffs1, stream_ceoff_loc.n_taps); + ADI_APOLLO_ERROR_RETURN(err); + } + } + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_pfilt_coeff_full_matrix_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t pfilts, uint8_t pfilt_banks, + int16_t coeffs0[], int16_t coeffs1[], int16_t coeffs2[], int16_t coeffs3[], uint32_t coeffs_len) +{ + int32_t err; + uint8_t i, j, pfilt_bank; + adi_apollo_blk_sel_t pfilt; + uint32_t regmap_base_addr = 0; + stream_mode_loc_map_t stream_ceoff_loc; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_DEV_FEAT_LOCKOUT_RETURN(terminal, ADI_APOLLO_EC_PFILT_LOCK); + ADI_APOLLO_NULL_POINTER_RETURN(coeffs0); + ADI_APOLLO_NULL_POINTER_RETURN(coeffs1); + ADI_APOLLO_NULL_POINTER_RETURN(coeffs2); + ADI_APOLLO_NULL_POINTER_RETURN(coeffs3); + ADI_APOLLO_INVALID_PARAM_RETURN(terminal > ADI_APOLLO_TX); + ADI_APOLLO_INVALID_PARAM_RETURN(pfilts & ~ADI_APOLLO_PFILT_ALL); + ADI_APOLLO_INVALID_PARAM_RETURN(pfilt_banks & ~ADI_APOLLO_PFILT_BANK_ALL); + ADI_APOLLO_INVALID_PARAM_RETURN(coeffs_len != 8); + ADI_APOLLO_PFILT_BLK_SEL_MASK(pfilts); + + /* Get coeff bank locations info for full matrix */ + stream_ceoff_loc = stream_mode_loc_map[pfilt_mode_to_idx[ADI_APOLLO_PFILT_MODE_MATRIX]]; + + for (i = 0; i < ADI_APOLLO_PFILT_NUM; i++) { + pfilt = pfilts & (ADI_APOLLO_PFILT_A0 << i); + if (pfilt > 0) { + for (j = 0; j < ADI_APOLLO_PFILT_BANK_NUM; j++) { + pfilt_bank = pfilt_banks & (ADI_APOLLO_PFILT_BANK0 << j); + if (pfilt_bank > 0) { + regmap_base_addr = calc_pfilt_coeff_base(terminal, (i * ADI_APOLLO_PFILT_BANK_NUM) + j); + err = write_bank(device, j, regmap_base_addr, stream_ceoff_loc.idx[0], coeffs0, stream_ceoff_loc.n_taps); + ADI_APOLLO_ERROR_RETURN(err); + err = write_bank(device, j, regmap_base_addr, stream_ceoff_loc.idx[1], coeffs1, stream_ceoff_loc.n_taps); + ADI_APOLLO_ERROR_RETURN(err); + err = write_bank(device, j, regmap_base_addr, stream_ceoff_loc.idx_fmtx[0], coeffs2, stream_ceoff_loc.n_taps); + ADI_APOLLO_ERROR_RETURN(err); + err = write_bank(device, j, regmap_base_addr, stream_ceoff_loc.idx_fmtx[1], coeffs3, stream_ceoff_loc.n_taps); + ADI_APOLLO_ERROR_RETURN(err); + } + } + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_pfilt_half_complex_delay_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t pfilts, uint8_t pfilt_banks, uint8_t delay) +{ + int32_t err; + uint8_t i, j, pfilt_bank, pfilt_local; + adi_apollo_blk_sel_t pfilt; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_DEV_FEAT_LOCKOUT_RETURN(terminal, ADI_APOLLO_EC_PFILT_LOCK); + ADI_APOLLO_INVALID_PARAM_RETURN(terminal > ADI_APOLLO_TX); + ADI_APOLLO_INVALID_PARAM_RETURN(pfilts & ~ADI_APOLLO_PFILT_ALL); + ADI_APOLLO_INVALID_PARAM_RETURN(pfilt_banks & ~ADI_APOLLO_PFILT_BANK_ALL); + ADI_APOLLO_INVALID_PARAM_RETURN(delay > 127); + ADI_APOLLO_PFILT_BLK_SEL_MASK(pfilts); + + for(i = 0; i < ADI_APOLLO_PFILT_NUM; i ++) { + pfilt = pfilts & (ADI_APOLLO_PFILT_A0 << i); + if (pfilt > 0) { + regmap_base_addr = calc_pfilt_base(terminal, i); + + for(j = 0; j < ADI_APOLLO_PFILT_BANK_NUM; j ++) { + pfilt_bank = pfilt_banks & (ADI_APOLLO_PFILT_BANK0 < 0) { + pfilt_local = (((i%ADI_APOLLO_PFILT_PER_SIDE)*ADI_APOLLO_PFILT_BANK_NUM) + j); + + err = adi_apollo_hal_bf_set(device, BF_HC_PROG_DELAY_INFO(regmap_base_addr, pfilt_local), delay); + ADI_APOLLO_ERROR_RETURN(err); + } + } + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_pfilt_coeff_transfer(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t pfilts, uint8_t bank_sel) +{ + int32_t err; + uint8_t i, pfilt_bank; + adi_apollo_blk_sel_t pfilt; + uint8_t bank_number = 0; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_DEV_FEAT_LOCKOUT_RETURN(terminal, ADI_APOLLO_EC_PFILT_LOCK); + ADI_APOLLO_INVALID_PARAM_RETURN(adi_api_utils_num_selected(bank_sel)!= 1); + ADI_APOLLO_PFILT_BLK_SEL_MASK(pfilts); + + for(i = 0; i < ADI_APOLLO_PFILT_BANK_NUM; i ++) { + pfilt_bank = bank_sel & (ADI_APOLLO_PFILT_BANK0 < 0) { + bank_number = i; + break; + } + } + + for(i = 0; i < ADI_APOLLO_PFILT_NUM; i ++) { + pfilt = pfilts & (ADI_APOLLO_PFILT_A0 << i); + if (pfilt > 0) { + regmap_base_addr = calc_pfilt_base(terminal, i); + + err = adi_apollo_hal_bf_set(device, BF_RD_COEFF_PAGE_SEL_INFO(regmap_base_addr, i%2), bank_number); + ADI_APOLLO_ERROR_RETURN(err); + + /* Generate 0->1 pulse to transfer selected back to active */ + err = adi_apollo_hal_bf_set(device, BF_PFIR_COEFF_TRANSFER_INFO(regmap_base_addr, i%2), 0); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_PFIR_COEFF_TRANSFER_INFO(regmap_base_addr, i%2), 1); + ADI_APOLLO_ERROR_RETURN(err); + } + } + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_pfilt_inspect(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t pfilt, adi_apollo_pfilt_inspect_t *pfilt_inspect) +{ + int32_t err; + uint8_t i, j, k, pfilt_local; + adi_apollo_blk_sel_t pfilt_temp; + uint32_t regmap_base_addr = 0; + uint32_t regmap_coeff_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_DEV_FEAT_LOCKOUT_RETURN(terminal, ADI_APOLLO_EC_PFILT_LOCK); + ADI_APOLLO_NULL_POINTER_RETURN(pfilt_inspect); + ADI_APOLLO_INVALID_PARAM_RETURN(adi_api_utils_num_selected(pfilt)!= 1); + ADI_APOLLO_PFILT_BLK_SEL_MASK(pfilt); + + /* pfilt_transfer_coeff_regmode: read the bank number*/ + for (i = 0; i < ADI_APOLLO_PFILT_NUM; i++) { + pfilt_temp = pfilt & (ADI_APOLLO_PFILT_A0 << i); + if (pfilt_temp > 0) { + regmap_base_addr = calc_pfilt_base(terminal, i); + + err = adi_apollo_hal_bf_get(device, BF_PFIR_COEFF_TRANSFER_INFO(regmap_base_addr, i%2), (uint8_t*)&(pfilt_inspect->pfir_coeff_transfer), 1); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_get(device, BF_RD_COEFF_PAGE_SEL_INFO(regmap_base_addr, i%2), (uint8_t*)&(pfilt_inspect->bank_sel), 1); + ADI_APOLLO_ERROR_RETURN(err); + break; + } + } + + + for (i = 0; i < ADI_APOLLO_PFILT_NUM; i+= 2) { //Common bitfield for 0 & 1 pfilts + pfilt_temp = pfilt & ((ADI_APOLLO_PFILT_A0 << i) | (ADI_APOLLO_PFILT_A0 << (i+1))); + if (pfilt_temp > 0) { + regmap_base_addr = calc_pfilt_base(terminal, i); + + /* pfilt_mode_pgm and pfilt_pgm*/ + err = adi_apollo_hal_bf_get(device, BF_QUAD_MODE_INFO(regmap_base_addr), (uint8_t*) &(pfilt_inspect->dp_cfg.dq_mode), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_REAL_DATA_INFO(regmap_base_addr), (uint8_t*) &(pfilt_inspect->dp_cfg.real_data), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_MODE_SWITCH_INFO(regmap_base_addr), (uint8_t*) &(pfilt_inspect->dp_cfg.mode_switch), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_ADD_SUB_SEL_INFO(regmap_base_addr), (uint8_t*) &(pfilt_inspect->dp_cfg.add_sub_sel), 1); + ADI_APOLLO_ERROR_RETURN(err); + + /* pfilt_setup_gpio_transfer */ + err = adi_apollo_hal_bf_get(device, BF_EQ_GPIO_EN_INFO(regmap_base_addr), (uint8_t*) &(pfilt_inspect->eq_gpio_sel), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_GPIO_CONFIG1_INFO(regmap_base_addr), (uint8_t*) &(pfilt_inspect->gpio_config1), 1); + ADI_APOLLO_ERROR_RETURN(err); + + break; + } + } + + for (i = 0; i < ADI_APOLLO_PFILT_NUM; i++) { + pfilt_temp = pfilt & (ADI_APOLLO_PFILT_A0 << i); + if (pfilt_temp > 0) { + regmap_base_addr = calc_pfilt_base(terminal, i); + + err = adi_apollo_hal_bf_get(device, BF_PFIR_I_MODE_INFO(regmap_base_addr, i%2), (uint8_t*) &(pfilt_inspect->dp_cfg.i_mode[i%2]), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_PFIR_Q_MODE_INFO(regmap_base_addr, i%2), (uint8_t*) &(pfilt_inspect->dp_cfg.q_mode[i%2]), 1); + ADI_APOLLO_ERROR_RETURN(err); + + for (j = 0; j < ADI_APOLLO_PFILT_BANK_NUM; j++) { + /* pfilt_gain_dly_pgm */ + pfilt_local = (((i % ADI_APOLLO_PFILT_PER_SIDE) * ADI_APOLLO_PFILT_BANK_NUM) + j); + + err = adi_apollo_hal_bf_get(device, BF_PFIR_IX_GAIN_INFO(regmap_base_addr, pfilt_local), (uint8_t*) &(pfilt_inspect->dp_cfg.pfir_ix_gain_db[j]), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_PFIR_IY_GAIN_INFO(regmap_base_addr, pfilt_local), (uint8_t*) &(pfilt_inspect->dp_cfg.pfir_iy_gain_db[j]), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_PFIR_QX_GAIN_INFO(regmap_base_addr, pfilt_local), (uint8_t*) &(pfilt_inspect->dp_cfg.pfir_qx_gain_db[j]), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_PFIR_QY_GAIN_INFO(regmap_base_addr, pfilt_local), (uint8_t*) &(pfilt_inspect->dp_cfg.pfir_qy_gain_db[j]), 1); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_get(device, BF_PFIR_IX_SCALAR_GAIN_INFO(regmap_base_addr, pfilt_local), (uint8_t*) &(pfilt_inspect->dp_cfg.pfir_ix_scalar_gain_db[j]), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_PFIR_IY_SCALAR_GAIN_INFO(regmap_base_addr, pfilt_local), (uint8_t*) &(pfilt_inspect->dp_cfg.pfir_iy_scalar_gain_db[j]), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_PFIR_QX_SCALAR_GAIN_INFO(regmap_base_addr, pfilt_local), (uint8_t*) &(pfilt_inspect->dp_cfg.pfir_qx_scalar_gain_db[j]), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_PFIR_QY_SCALAR_GAIN_INFO(regmap_base_addr, pfilt_local), (uint8_t*) &(pfilt_inspect->dp_cfg.pfir_qy_scalar_gain_db[j]), 1); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_get(device, BF_HC_PROG_DELAY_INFO(regmap_base_addr, pfilt_local), (uint8_t*) &(pfilt_inspect->dp_cfg.hc_prog_delay[j]), 1); + ADI_APOLLO_ERROR_RETURN(err); + + /* pfilt_coeff_pgm */ + regmap_coeff_base_addr = calc_pfilt_coeff_base(terminal, (i * ADI_APOLLO_PFILT_BANK_NUM) + j); + if (j % ADI_APOLLO_PFILT_BANKS_PER_REGMAP == 0) { //BANK0 and BANK2 + for (k = 0; k < ADI_APOLLO_PFILT_COEFF_NUM; k++) { + err = adi_apollo_hal_bf_get(device, BF_COEFF_0_INFO(regmap_coeff_base_addr, k), (uint8_t*) &(pfilt_inspect->dp_cfg.coeffs[j][k]), 2); + ADI_APOLLO_ERROR_RETURN(err); + } + } + else { //BANK1 and BANK3 + for (k = 0; k < ADI_APOLLO_PFILT_COEFF_NUM; k++) { + err = adi_apollo_hal_bf_get(device, BF_COEFF_1_INFO(regmap_coeff_base_addr, k), (uint8_t*) &(pfilt_inspect->dp_cfg.coeffs[j][k]), 2); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + } + + break; + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_pfilt_mode_enable_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t pfilts, uint8_t iq_sel, adi_apollo_pfilt_mode_e mode) +{ + int32_t err; + uint8_t i; + adi_apollo_blk_sel_t pfilt; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_DEV_FEAT_LOCKOUT_RETURN(terminal, ADI_APOLLO_EC_PFILT_LOCK); + ADI_APOLLO_PFILT_BLK_SEL_MASK(pfilts); + + for(i = 0; i < ADI_APOLLO_PFILT_NUM; i ++) { + pfilt = pfilts & (ADI_APOLLO_PFILT_A0 << i); + if (pfilt > 0) { + regmap_base_addr = calc_pfilt_base(terminal, i); + + if (iq_sel & ADI_APOLLO_PFILT_STREAM_0) { + err = adi_apollo_hal_bf_set(device, BF_PFIR_I_MODE_INFO(regmap_base_addr, i%2), mode); + ADI_APOLLO_ERROR_RETURN(err); + } + if (iq_sel & ADI_APOLLO_PFILT_STREAM_1) { + err = adi_apollo_hal_bf_set(device, BF_PFIR_Q_MODE_INFO(regmap_base_addr, i%2), mode); + ADI_APOLLO_ERROR_RETURN(err); + } + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_pfilt_profile_sel_mode_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t pfilts, const adi_apollo_pfilt_profile_sel_mode_e prof_sel_mode) +{ + int32_t err; + uint8_t i; + adi_apollo_blk_sel_t pfilt; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_DEV_FEAT_LOCKOUT_RETURN(terminal, ADI_APOLLO_EC_PFILT_LOCK); + ADI_APOLLO_INVALID_PARAM_RETURN(prof_sel_mode > (ADI_APOLLO_PFILT_CHAN_SEL_NUM-1)); + ADI_APOLLO_PFILT_BLK_SEL_MASK(pfilts); + + const uint8_t bank_regs[ADI_APOLLO_PFILT_CHAN_SEL_NUM][3] = { + {0, 0, 0}, // BF_PFILT_TRIGGER_EN_INFO, BF_EQ_GPIO_EN_INFO, BF_GPIO_CONFIG1_INFO + {0, 1, 0}, + {0, 1, 1}, + {1, 0, 0}, + {1, 1, 0}, + {1, 1, 1} + }; + + for(i = 0; i < ADI_APOLLO_PFILT_NUM; i ++) { + pfilt = pfilts & (ADI_APOLLO_PFILT_A0 << i); + if (pfilt > 0) { + regmap_base_addr = calc_pfilt_base(terminal, i); + + err = adi_apollo_hal_bf_set(device, BF_PFILT_TRIGGER_EN_INFO(regmap_base_addr), bank_regs[prof_sel_mode][0]); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_EQ_GPIO_EN_INFO(regmap_base_addr), bank_regs[prof_sel_mode][1]); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_GPIO_CONFIG1_INFO(regmap_base_addr), bank_regs[prof_sel_mode][2]); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_pfilt_next_hop_num_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t pfilts, int16_t hop_num) +{ + int32_t err; + uint8_t i; + adi_apollo_blk_sel_t pfilt; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_DEV_FEAT_LOCKOUT_RETURN(terminal, ADI_APOLLO_EC_PFILT_LOCK); + ADI_APOLLO_INVALID_PARAM_RETURN(hop_num > ADI_APOLLO_PFILT_BANK_NUM-1); + ADI_APOLLO_PFILT_BLK_SEL_MASK(pfilts); + + for (i = 0; i < ADI_APOLLO_PFILT_NUM; i++) { + pfilt = pfilts & (ADI_APOLLO_PFILT_A0 << i); + if (pfilt > 0) { + regmap_base_addr = calc_pfilt_base(terminal, i); + + err = adi_apollo_hal_bf_set(device, BF_RD_COEFF_PAGE_SEL_INFO(regmap_base_addr, i%2), hop_num); // Next active coeff bank on trig event + ADI_APOLLO_ERROR_RETURN(err); + } + } + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_pfilt_ave_mode_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t pfilts, adi_apollo_pfilt_ave_mode_e ave_mode) +{ + int32_t err; + uint8_t i; + adi_apollo_blk_sel_t pfilt; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_DEV_FEAT_LOCKOUT_RETURN(ADI_APOLLO_RX, ADI_APOLLO_EC_PFILT_LOCK); + ADI_APOLLO_INVALID_PARAM_RETURN(ave_mode > ADI_APOLLO_PFILT_AVE_NUM - 1); + ADI_APOLLO_PFILT_BLK_SEL_MASK(pfilts); + + for (i = 0; i < ADI_APOLLO_PFILT_NUM; i++) { + pfilt = pfilts & (ADI_APOLLO_PFILT_A0 << i); + if (pfilt > 0) { + regmap_base_addr = calc_pfilt_base(ADI_APOLLO_RX, i); + + err = adi_apollo_hal_bf_set(device, BF_MODE_SWITCH_INFO(regmap_base_addr), ave_mode != ADI_APOLLO_PFILT_AVE_DISABLE); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_ADD_SUB_SEL_INFO(regmap_base_addr), ave_mode == ADI_APOLLO_PFILT_AVE_ENABLE_ADD); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_QUAD_MODE_INFO(regmap_base_addr), device->dev_info.is_8t8r ? 1 : 0); + ADI_APOLLO_ERROR_RETURN(err); + } + } + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_pfilt_data_type_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t pfilts, adi_apollo_pfilt_data_e data_type) +{ + int32_t err; + uint8_t i; + adi_apollo_blk_sel_t pfilt; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_DEV_FEAT_LOCKOUT_RETURN(terminal, ADI_APOLLO_EC_PFILT_LOCK); + ADI_APOLLO_INVALID_PARAM_RETURN(data_type > ADI_APOLLO_PFILT_REAL_DATA); + ADI_APOLLO_PFILT_BLK_SEL_MASK(pfilts); + + for (i = 0; i < ADI_APOLLO_PFILT_NUM; i++) { + pfilt = pfilts & (ADI_APOLLO_PFILT_A0 << i); + if (pfilt > 0) { + regmap_base_addr = calc_pfilt_base(terminal, i); + + err = adi_apollo_hal_bf_set(device, BF_REAL_DATA_INFO(regmap_base_addr), data_type); + ADI_APOLLO_ERROR_RETURN(err); + } + } + return API_CMS_ERROR_OK; +} + +uint32_t calc_pfilt_coeff_base(adi_apollo_terminal_e terminal, int32_t global_bank_base) +{ + static uint32_t rx_pfilt_coeff_regmap[ADI_APOLLO_PFILT_NUM * ADI_APOLLO_PFILT_BANK_NUM] = { + RX_PFILT_COEFF0_RX_SLICE_0_RX_DIGITAL0, RX_PFILT_COEFF0_RX_SLICE_0_RX_DIGITAL0, RX_PFILT_COEFF0_RX_SLICE_1_RX_DIGITAL0, RX_PFILT_COEFF0_RX_SLICE_1_RX_DIGITAL0, + RX_PFILT_COEFF1_RX_SLICE_0_RX_DIGITAL0, RX_PFILT_COEFF1_RX_SLICE_0_RX_DIGITAL0, RX_PFILT_COEFF1_RX_SLICE_1_RX_DIGITAL0, RX_PFILT_COEFF1_RX_SLICE_1_RX_DIGITAL0, + RX_PFILT_COEFF0_RX_SLICE_0_RX_DIGITAL1, RX_PFILT_COEFF0_RX_SLICE_0_RX_DIGITAL1, RX_PFILT_COEFF0_RX_SLICE_1_RX_DIGITAL1, RX_PFILT_COEFF0_RX_SLICE_1_RX_DIGITAL1, + RX_PFILT_COEFF1_RX_SLICE_0_RX_DIGITAL1, RX_PFILT_COEFF1_RX_SLICE_0_RX_DIGITAL1, RX_PFILT_COEFF1_RX_SLICE_1_RX_DIGITAL1, RX_PFILT_COEFF1_RX_SLICE_1_RX_DIGITAL1, + }; + static uint32_t tx_pfilt_coeff_regmap[ADI_APOLLO_PFILT_NUM * ADI_APOLLO_PFILT_BANK_NUM] = { + TX_PFILT_COEFF0_TX_SLICE_0_TX_DIGITAL0, TX_PFILT_COEFF0_TX_SLICE_0_TX_DIGITAL0, TX_PFILT_COEFF0_TX_SLICE_1_TX_DIGITAL0, TX_PFILT_COEFF0_TX_SLICE_1_TX_DIGITAL0, + TX_PFILT_COEFF1_TX_SLICE_0_TX_DIGITAL0, TX_PFILT_COEFF1_TX_SLICE_0_TX_DIGITAL0, TX_PFILT_COEFF1_TX_SLICE_1_TX_DIGITAL0, TX_PFILT_COEFF1_TX_SLICE_1_TX_DIGITAL0, + TX_PFILT_COEFF0_TX_SLICE_0_TX_DIGITAL1, TX_PFILT_COEFF0_TX_SLICE_0_TX_DIGITAL1, TX_PFILT_COEFF0_TX_SLICE_1_TX_DIGITAL1, TX_PFILT_COEFF0_TX_SLICE_1_TX_DIGITAL1, + TX_PFILT_COEFF1_TX_SLICE_0_TX_DIGITAL1, TX_PFILT_COEFF1_TX_SLICE_0_TX_DIGITAL1, TX_PFILT_COEFF1_TX_SLICE_1_TX_DIGITAL1, TX_PFILT_COEFF1_TX_SLICE_1_TX_DIGITAL1, + }; + if (terminal == ADI_APOLLO_RX) + return rx_pfilt_coeff_regmap[global_bank_base]; + else + return tx_pfilt_coeff_regmap[global_bank_base]; +} + +uint32_t calc_pfilt_base(adi_apollo_terminal_e terminal, int32_t pfilt_index) +{ + static uint32_t rx_pfilt_regmap[ADI_APOLLO_PFILT_NUM] = { + RX_PFILT_TOP_RX_SLICE_0_RX_DIGITAL0, RX_PFILT_TOP_RX_SLICE_0_RX_DIGITAL0, + RX_PFILT_TOP_RX_SLICE_0_RX_DIGITAL1, RX_PFILT_TOP_RX_SLICE_0_RX_DIGITAL1 + }; + static uint32_t tx_pfilt_regmap[ADI_APOLLO_PFILT_NUM] = { + TX_PFILT_TOP_TX_SLICE_0_TX_DIGITAL0, TX_PFILT_TOP_TX_SLICE_0_TX_DIGITAL0, + TX_PFILT_TOP_TX_SLICE_0_TX_DIGITAL1, TX_PFILT_TOP_TX_SLICE_0_TX_DIGITAL1 + }; + if (terminal == ADI_APOLLO_RX) + return rx_pfilt_regmap[pfilt_index]; + else + return tx_pfilt_regmap[pfilt_index]; +} + +static int32_t write_bank(adi_apollo_device_t *device, uint32_t bank_num, uint32_t regmap_base_addr, int first_idx, int16_t ceoffs[], uint32_t n_taps) +{ + int32_t err; + uint32_t i; + + if ((bank_num % ADI_APOLLO_PFILT_BANKS_PER_REGMAP == 0)) { //BANK0 and BANK2 + for (i = 0; i < n_taps; i++) { + err = adi_apollo_hal_bf_set(device, BF_COEFF_0_INFO(regmap_base_addr, (i + first_idx) % ADI_APOLLO_PFILT_COEFF_NUM), ceoffs[i]); + ADI_APOLLO_ERROR_RETURN(err); + } + } else { //BANK1 and BANK3 + for (i = 0; i < n_taps; i++) { + err = adi_apollo_hal_bf_set(device, BF_COEFF_1_INFO(regmap_base_addr, (i + first_idx) % ADI_APOLLO_PFILT_COEFF_NUM), ceoffs[i]); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return err; +} +/*! @} */ \ No newline at end of file diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_pfilt_local.h b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_pfilt_local.h new file mode 100644 index 00000000000000..8e0e6c3faaea37 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_pfilt_local.h @@ -0,0 +1,38 @@ +/*! + * \brief PFILT local defines and prototypes + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_PFILT + * @{ + */ +#ifndef __ADI_APOLLO_PFILT_LOCAL_H__ +#define __ADI_APOLLO_PFILT_LOCAL_H__ + +/*============= I N C L U D E S ============*/ + +/*============= D E F I N E S ==============*/ + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +uint32_t calc_pfilt_base(adi_apollo_terminal_e terminal, int32_t pfilt_index); +uint32_t calc_pfilt_coeff_base(adi_apollo_terminal_e terminal, int32_t global_bank_base); + + +#ifndef CLIENT_IGNORE +#endif /* CLIENT_IGNORE*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_PFILT_LOCAL_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_reconfig.c b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_reconfig.c new file mode 100644 index 00000000000000..8bc362aaa3b052 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_reconfig.c @@ -0,0 +1,132 @@ +/*! + * \brief APIs for RECONFIG + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_RECONFIG + * \{ + */ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_reconfig.h" +#include "adi_apollo_reconfig_local.h" +#include "adi_apollo_private_device.h" + +#include "adi_apollo_bf_txrx_prefsrc_reconf.h" +#include "adi_apollo_bf_txrx_postfsrc_reconf.h" + +#include "adi_apollo_config.h" +#include "adi_apollo_hal.h" +#include "adi_utils.h" + +/*==================== P U B L I C A P I C O D E ====================*/ + +int32_t adi_apollo_reconfig_ctrl_pgm(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, uint8_t sides, adi_apollo_reconfig_ctrl_pgm_t *config) +{ + int32_t err; + uint8_t i, side; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_DEV_FEAT_LOCKOUT_RETURN(terminal, ADI_APOLLO_EC_DYN_CFG_LOCK); + + for(i = 0; i < ADI_APOLLO_NUM_SIDES; i ++) { + side = sides & (ADI_APOLLO_SIDE_A << i); + if (side > 0) { + regmap_base_addr = calc_prefsrc_reconfig_base(terminal, i); + + err = adi_apollo_hal_bf_set(device, BF_TRIG_RECONF_MODE_INFO(regmap_base_addr), config->trig_reconfig_mode); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_CNCO_RESET_EN_INFO(regmap_base_addr), config->cnco_reset); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_TIMESTAMP_RESET_EN_INFO(regmap_base_addr), config->timestamp_reset_en); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_RESYNC_EN_INFO(regmap_base_addr), config->resync_en); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_TZERO_COHERENCE_EN_INFO(regmap_base_addr), config->tzero_coherence_en); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_FNCO_RESET_EN_INFO(regmap_base_addr), config->fnco_reset_en); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_PREFSRC_LCM_INFO(regmap_base_addr), config->prefsrc_lcm); + ADI_APOLLO_ERROR_RETURN(err); + + regmap_base_addr = calc_postfsrc_reconfig_base(terminal, i); + + err = adi_apollo_hal_bf_set(device, BF_POSTFSRC_LCM_INFO(regmap_base_addr), config->postfsrc_lcm); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + + +int32_t adi_apollo_reconfig_trig_evt_cnt_get(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, uint8_t sides, adi_apollo_reconfig_type_e rec_type, uint16_t *count) +{ + int32_t err; + uint8_t i, side; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_DEV_FEAT_LOCKOUT_RETURN(terminal, ADI_APOLLO_EC_DYN_CFG_LOCK); + ADI_APOLLO_INVALID_PARAM_RETURN(adi_api_utils_num_selected(sides) != 1); + ADI_APOLLO_INVALID_PARAM_RETURN(rec_type >= ADI_APOLLO_RECONFIG_TYPE_NUM); + + for (i = 0; i < ADI_APOLLO_NUM_SIDES; i++) { + side = sides & (ADI_APOLLO_SIDE_A << i); + if (side > 0) { + regmap_base_addr = calc_prefsrc_reconfig_base(terminal, i); + + if (rec_type == ADI_APOLLO_RECONFIG_EXTERNAL) { + err = adi_apollo_hal_bf_get(device, BF_SYNC_INPUT_COUNT_INFO(regmap_base_addr), (uint8_t *)count, sizeof(*count)); + ADI_APOLLO_ERROR_RETURN(err); + } else { + err = adi_apollo_hal_bf_get(device, BF_TRIG_INPUT_COUNT_INFO(regmap_base_addr), (uint8_t*)count, sizeof(*count)); + ADI_APOLLO_ERROR_RETURN(err); + } + + break; // single return val + } + } + + return API_CMS_ERROR_OK; +} + + + + +uint32_t calc_prefsrc_reconfig_base(adi_apollo_terminal_e terminal, int32_t reconfig_index) +{ + static uint32_t rx_prefsrc_reconfig_regmap[ADI_APOLLO_NUM_SIDES] = { + TXRX_PREFSRC_RECONF_RX_SLICE_0_RX_DIGITAL0, TXRX_PREFSRC_RECONF_RX_SLICE_0_RX_DIGITAL1 + }; + static uint32_t tx_prefsrc_reconfig_regmap[ADI_APOLLO_NUM_SIDES] = { + TXRX_PREFSRC_RECONF_TX_SLICE_0_TX_DIGITAL0, TXRX_PREFSRC_RECONF_TX_SLICE_0_TX_DIGITAL1 + }; + if (terminal == ADI_APOLLO_RX) + return rx_prefsrc_reconfig_regmap[reconfig_index]; + else + return tx_prefsrc_reconfig_regmap[reconfig_index]; +} + +uint32_t calc_postfsrc_reconfig_base(adi_apollo_terminal_e terminal, int32_t reconfig_index) +{ + static uint32_t rx_postfsrc_reconfig_regmap[ADI_APOLLO_NUM_SIDES] = { + TXRX_POSTFSRC_RECONF_RX_SLICE_0_RX_DIGITAL0, TXRX_POSTFSRC_RECONF_RX_SLICE_0_RX_DIGITAL1 + }; + static uint32_t tx_postfsrc_reconfig_regmap[ADI_APOLLO_NUM_SIDES] = { + TXRX_POSTFSRC_RECONF_TX_SLICE_0_TX_DIGITAL0, TXRX_POSTFSRC_RECONF_TX_SLICE_0_TX_DIGITAL1 + }; + if (terminal == ADI_APOLLO_RX) + return rx_postfsrc_reconfig_regmap[reconfig_index]; + else + return tx_postfsrc_reconfig_regmap[reconfig_index]; +} +/*! @} */ \ No newline at end of file diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_reconfig_local.h b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_reconfig_local.h new file mode 100644 index 00000000000000..d03b24cd509ab1 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_reconfig_local.h @@ -0,0 +1,37 @@ +/*! + * \brief RECONFIG local defines and prototypes + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_RECONFIG + * @{ + */ +#ifndef __ADI_APOLLO_RECONFIG_LOCAL_H__ +#define __ADI_APOLLO_RECONFIG_LOCAL_H__ + +/*============= I N C L U D E S ============*/ + +/*============= D E F I N E S ==============*/ + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +uint32_t calc_prefsrc_reconfig_base(adi_apollo_terminal_e terminal, int32_t reconfig_index); +uint32_t calc_postfsrc_reconfig_base(adi_apollo_terminal_e terminal, int32_t reconfig_index); + +#ifndef CLIENT_IGNORE +#endif /* CLIENT_IGNORE*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_RECONFIG_LOCAL_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_rx.c b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_rx.c new file mode 100644 index 00000000000000..84ad824b2bf565 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_rx.c @@ -0,0 +1,569 @@ +/*! + * \brief RX data path top level APIs + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_RX + * @{ + */ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo.h" +#include "adi_apollo_rx.h" +#include "adi_apollo_config.h" +#include "adi_apollo_cfg.h" +#include "adi_apollo_hal.h" +#include "adi_apollo_private_device.h" +#include "adi_apollo_ddc_local.h" + +/*==================== P U B L I C A P I C O D E ====================*/ +int32_t adi_apollo_rx_configure(adi_apollo_device_t *device, adi_apollo_sides_e side, adi_apollo_rxpath_t *config, adi_apollo_jesd_tx_cfg_t *jtx_config) +{ + int32_t err; + uint8_t i; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(config); + ADI_APOLLO_NULL_POINTER_RETURN(jtx_config); + ADI_APOLLO_INVALID_PARAM_RETURN((side > ADI_APOLLO_NUM_SIDES - 1)); + + /* Release RX datapath DP reset */ + adi_apollo_rxmisc_dp_reset(device, (adi_apollo_side_select_e)(1 << side), 0); + + /* CDDC/CNCO config */ + for(i = 0; i < ADI_APOLLO_CDDCS_PER_SIDE; i ++) { + err = adi_apollo_rx_cddc_configure(device, side, (adi_apollo_cddc_idx_e)i, &(config->rx_cddc[i])); + ADI_APOLLO_ERROR_RETURN(err); + } + + /* FDDC/FNCO config */ + for(i = 0; i < ADI_APOLLO_FDDCS_PER_SIDE; i ++) { + err = adi_apollo_rx_fddc_configure(device, side, (adi_apollo_fddc_idx_e)i, &(config->rx_fddc[i])); + ADI_APOLLO_ERROR_RETURN(err); + } + + /* XBARs config */ + err = adi_apollo_rx_rxpath_misc_configure(device, side, &(config->rx_mux_splitter_xbar)); + ADI_APOLLO_ERROR_RETURN(err); + + /* PFILT CONFIG */ + if (!adi_apollo_private_device_lockout_get(device, ADI_APOLLO_RX, ADI_APOLLO_EC_PFILT_LOCK)) { + for(i = 0; i < ADI_APOLLO_PFILTS_PER_SIDE; i ++) { + err = adi_apollo_rx_pfilt_configure(device, side, (adi_apollo_pfilt_idx_e)i, &(config->rx_pfilt[i])); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + /* CFIR config */ + if (!adi_apollo_private_device_lockout_get(device, ADI_APOLLO_RX, ADI_APOLLO_EC_CFIR_LOCK)) { + for(i = 0; i < ADI_APOLLO_CFIRS_PER_SIDE; i ++) { + err = adi_apollo_rx_cfir_configure(device, side, (adi_apollo_cfir_idx_e)i, &(config->rx_cfir[i])); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + /* FSRC config */ + if (!adi_apollo_private_device_lockout_get(device, ADI_APOLLO_RX, ADI_APOLLO_EC_FSRC_LOCK)) { + for (i = 0; i < ADI_APOLLO_FSRC_PER_SIDE_NUM; i++) { + err = adi_apollo_rx_fsrc_configure(device, side, (uint8_t)i, &(config->rx_fsrc)); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + /* DFORMAT config */ + for (i = 0; i < ADI_APOLLO_JESD_LINKS; i++) { // # of JESD links per side + err = adi_apollo_rx_dformat_configure(device, side, (adi_apollo_jesd_links_e)i, &(config->rx_dformat[i]), &(jtx_config->tx_link_cfg[i])); + ADI_APOLLO_ERROR_RETURN(err); + } + + /* SMON config */ + for (i = 0; i < ADI_APOLLO_SMONS_PER_SIDE; i++) { + err = adi_apollo_rx_smon_configure(device, side, (adi_apollo_smon_idx_e)i, &(config->rx_smon[i])); + ADI_APOLLO_ERROR_RETURN(err); + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_rx_cddc_configure(adi_apollo_device_t *device, adi_apollo_sides_e side, adi_apollo_cddc_idx_e idx, adi_apollo_cddc_cfg_t *config) +{ + int32_t err; + uint8_t cddc_sel; + uint8_t cnco_sel; + int cnco_idx; + adi_apollo_cddc_pgm_t ddc_pgm_config; + adi_apollo_cnco_pgm_t nco_pgm_config; + adi_apollo_coarse_nco_hop_t nco_hop_profile_config; + adi_apollo_trig_mst_config_t nco_trig_mst_config; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(config); + + /* Determine block api select from index */ + cddc_sel = ADI_APOLLO_CDDC_IDX2B(side, idx); + + /* Program the coarse ddc */ + ddc_pgm_config.dcm = config->drc_ratio; + ddc_pgm_config.fine_bypass = config->fine_bypass; + ddc_pgm_config.link_num = config->link_num; + ddc_pgm_config.debug_clkoff_n = config->debug_cddc_clkoff_n; + ddc_pgm_config.hb1_filt_dly_en = config->hb1_filt_dly_en; + ddc_pgm_config.hb2_filt_dly_en = config->hb2_filt_dly_en; + ddc_pgm_config.tb1_filt_dly = config->tb1_filt_dly_cycles; + ddc_pgm_config.hb1_gain_6db_en = config->hb1_gain_6db_en; + ddc_pgm_config.tb1_gain_6db_en = config->tb1_gain_6db_en; + err = adi_apollo_cddc_pgm(device, cddc_sel, &ddc_pgm_config); + ADI_APOLLO_ERROR_RETURN(err); + + /* Program the CNCOs (there are two CNCOs per CDDC) */ + for (cnco_idx = 0; cnco_idx < ADI_APOLLO_NUM_NCOS_PER_DRC; cnco_idx++) { + + cnco_sel = cddc_sel << (2 * cnco_idx); // Selects A0/A2, A1/A3, ... B1/B3 (pairs for 8t8r) + + /* Program the coarse nco */ + nco_pgm_config.drc_en = config->nco[cnco_idx].drc_en; + nco_pgm_config.debug_drc_clkoff_n = config->nco[cnco_idx].debug_cdrc_clkoff_n; + nco_pgm_config.profile_num = 0; + nco_pgm_config.profile_sel_mode = config->nco[cnco_idx].nco_profile_sel_mode; + nco_pgm_config.cmplx_mxr_scale_en = config->nco[cnco_idx].cmplx_mxr_mult_scale_en; + nco_pgm_config.drc_phase_inc = config->nco[cnco_idx].nco_phase_inc; + nco_pgm_config.drc_phase_offset = config->nco[cnco_idx].nco_phase_offset; + nco_pgm_config.drc_phase_inc_frac_a = config->nco[cnco_idx].nco_phase_inc_frac_a; + nco_pgm_config.drc_phase_inc_frac_b = config->nco[cnco_idx].nco_phase_inc_frac_b; + nco_pgm_config.if_mode = config->nco[cnco_idx].nco_if_mode; + nco_pgm_config.mixer_sel = config->nco[cnco_idx].drc_mxr_sel; + nco_pgm_config.dc_testmode_value = config->nco[cnco_idx].dc_testmode_value; + err = adi_apollo_cnco_pgm(device, ADI_APOLLO_RX, cnco_sel, &nco_pgm_config); + ADI_APOLLO_ERROR_RETURN(err); + + /* Load the coarse nco profiles */ + err = adi_apollo_cnco_profile_load(device, ADI_APOLLO_RX, cnco_sel, + ADI_APOLLO_NCO_PROFILE_PHASE_INCREMENT, 0, config->nco[cnco_idx].nco_phase_inc_words, ADI_APOLLO_CNCO_PROFILE_NUM); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_cnco_profile_load(device, ADI_APOLLO_RX, cnco_sel, + ADI_APOLLO_NCO_PROFILE_PHASE_OFFSET, 0, config->nco[cnco_idx].nco_phase_offset_words, ADI_APOLLO_CNCO_PROFILE_NUM); + ADI_APOLLO_ERROR_RETURN(err); + + /* Profile trigger or direct based profile sel */ + nco_hop_profile_config.profile_sel_mode = config->nco[cnco_idx].nco_profile_sel_mode; + + /* Auto hop flip, incr or decr */ + nco_hop_profile_config.auto_mode = config->nco[cnco_idx].nco_auto_inc_dec; + nco_hop_profile_config.low_limit = 0; + nco_hop_profile_config.high_limit = 15; + nco_hop_profile_config.next_hop_number_wr_en = 0; + nco_hop_profile_config.hop_ctrl_init = 0; + nco_hop_profile_config.phase_handling = 0; + + err = adi_apollo_cnco_hop_enable(device, ADI_APOLLO_RX, cnco_sel, &nco_hop_profile_config); + ADI_APOLLO_ERROR_RETURN(err); + + nco_trig_mst_config.trig_enable = ADI_APOLLO_TRIG_DISABLE; + nco_trig_mst_config.trig_period = config->trig_mst_period; + nco_trig_mst_config.trig_offset = config->trig_mst_offset; + err = adi_apollo_trigts_cnco_trig_mst_config(device, ADI_APOLLO_RX, cnco_sel, &nco_trig_mst_config); + ADI_APOLLO_ERROR_RETURN(err); + + /* Set initial phase inc and offset. Select profile 0 as default. */ + err = adi_apollo_cnco_ftw_set(device, ADI_APOLLO_RX, cnco_sel, 0, 1, config->nco[cnco_idx].nco_phase_inc); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_cnco_pow_set(device, ADI_APOLLO_RX, cnco_sel, 0, 1, config->nco[cnco_idx].nco_phase_offset); + ADI_APOLLO_ERROR_RETURN(err); + } + + // Trigger selection mux here + err = adi_apollo_trigts_cdrc_trig_sel_mux_set(device, ADI_APOLLO_RX, cddc_sel, ADI_APOLLO_TRIG_SPI); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + + +int32_t adi_apollo_rx_fddc_configure(adi_apollo_device_t *device, adi_apollo_sides_e side, adi_apollo_fddc_idx_e idx, adi_apollo_fddc_cfg_t *config) +{ + int32_t err; + uint16_t fddc_sel; + uint16_t fnco_sel; + int fnco_idx; + adi_apollo_fddc_pgm_t ddc_pgm_config; + adi_apollo_fnco_pgm_t nco_pgm_config; + adi_apollo_fine_nco_hop_t nco_hop_profile_config; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(config); + ADI_APOLLO_INVALID_PARAM_RETURN((idx > ADI_APOLLO_FDDCS_PER_SIDE-1)) + + /* Determine block api select from index */ + fddc_sel = ADI_APOLLO_FDDC_IDX2B(side, idx); + + /* Program the fddc functional block */ + ddc_pgm_config.dcm = config->drc_ratio; + ddc_pgm_config.debug_clkoff_n = config->debug_fddc_clkoff_n; + ddc_pgm_config.link_num = config->link_num; + ddc_pgm_config.hb1_gain_6db_en = config->hb1_gain_6db_en; + err = adi_apollo_fddc_pgm(device, fddc_sel, &ddc_pgm_config); + ADI_APOLLO_ERROR_RETURN(err); + + /* Program the FNCOs (there are two FNCOs per FDDC) */ + for (fnco_idx = 0; fnco_idx < ADI_APOLLO_NUM_NCOS_PER_DRC; fnco_idx++) { + + fnco_sel = fddc_sel << (4 * fnco_idx); // Selects A0/A4, A1/A5, ... B3/B7 (pairs for 8t8r) + + /* Program fine nco */ + nco_pgm_config.drc_en = config->nco[fnco_idx].drc_en; + nco_pgm_config.debug_drc_clkoff_n = config->nco[fnco_idx].debug_fdrc_clkoff_n; + nco_pgm_config.if_mode = config->nco[fnco_idx].nco_if_mode; + nco_pgm_config.mixer_sel = config->nco[fnco_idx].drc_mxr_sel; + nco_pgm_config.cmplx_mxr_scale_en = config->nco[fnco_idx].cmplx_mxr_mult_scale_en; + nco_pgm_config.profile_num = 0; + nco_pgm_config.profile_sel_mode = config->nco[fnco_idx].nco_profile_sel_mode; + nco_pgm_config.hop_mode_en = config->nco[fnco_idx].hop_mode_en; + nco_pgm_config.main_phase_inc = config->nco[fnco_idx].nco_phase_inc; + nco_pgm_config.main_phase_offset = config->nco[fnco_idx].nco_phase_offset; + nco_pgm_config.drc_phase_inc_frac_a = config->nco[fnco_idx].nco_phase_inc_frac_a; + nco_pgm_config.drc_phase_inc_frac_b = config->nco[fnco_idx].nco_phase_inc_frac_b; + nco_pgm_config.dc_testmode_value = config->nco[fnco_idx].dc_testmode_value; + err = adi_apollo_fnco_pgm(device, ADI_APOLLO_RX, fnco_sel, &nco_pgm_config); + ADI_APOLLO_ERROR_RETURN(err); + + /* Load fine nco profiles */ + err = adi_apollo_fnco_profile_load(device, ADI_APOLLO_RX, fnco_sel, + ADI_APOLLO_NCO_PROFILE_PHASE_INCREMENT, 0, config->nco[fnco_idx].nco_phase_inc_words, ADI_APOLLO_FNCO_PROFILE_NUM); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_fnco_profile_load(device, ADI_APOLLO_RX, fnco_sel, + ADI_APOLLO_NCO_PROFILE_PHASE_OFFSET, 0, config->nco[fnco_idx].nco_phase_offset_words, ADI_APOLLO_FNCO_PROFILE_NUM); + ADI_APOLLO_ERROR_RETURN(err); + + /* Configure hopping */ + nco_hop_profile_config.profile_sel_mode = config->nco[fnco_idx].nco_profile_sel_mode; + + nco_hop_profile_config.nco_trig_hop_sel = config->nco[fnco_idx].nco_trig_hop_sel; + nco_hop_profile_config.phase_inc_auto_mode = (adi_apollo_nco_auto_flip_incdir_e) config->nco[fnco_idx].nco_auto_inc_dec_freq; + nco_hop_profile_config.phase_offset_auto_mode = (adi_apollo_nco_auto_flip_incdir_e )config->nco[fnco_idx].nco_auto_inc_dec_phase; + nco_hop_profile_config.phase_inc_low_limit = 0; + nco_hop_profile_config.phase_inc_high_limit = 31; + nco_hop_profile_config.phase_offset_low_limit = 0; + nco_hop_profile_config.phase_offset_high_limit = 31; + nco_hop_profile_config.phase_handling = 0; + err = adi_apollo_fnco_hop_pgm(device, ADI_APOLLO_RX, fnco_sel, &nco_hop_profile_config); + + /* Set initial hop index to 0. This is relevant when hop_mode_en is true */ + err = adi_apollo_fnco_ftw_set(device, ADI_APOLLO_RX, fnco_sel, 0, 1, config->nco[fnco_idx].nco_phase_inc_words[0]); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_fnco_pow_set(device, ADI_APOLLO_RX, fnco_sel, 0, 1, config->nco[fnco_idx].nco_phase_offset_words[0]); + ADI_APOLLO_ERROR_RETURN(err); + + } + + // Trigger selection mux here + err = adi_apollo_trigts_fdrc_trig_sel_mux_set(device, ADI_APOLLO_RX, fddc_sel, ADI_APOLLO_TRIG_SPI); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_rx_pfilt_configure(adi_apollo_device_t *device, adi_apollo_sides_e side, adi_apollo_pfilt_idx_e idx_pfilt, adi_apollo_pfilt_cfg_t *config) +{ + int32_t err; + uint8_t coeff_set_idx; + uint8_t ctrl_sets_idx; + adi_apollo_pfilt_mode_pgm_t blk_mode_config; + adi_apollo_pfilt_gain_dly_pgm_t blk_gain_dly_config; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(config); + ADI_APOLLO_INVALID_PARAM_RETURN((idx_pfilt > ADI_APOLLO_PFILTS_PER_SIDE-1)) + + /* In a 4T4R part, there is one pfilt on each side (side A and Side B), "pfilt 0" => pfilt A0 on side A and pfilt B0 on side B + * In an 8T8R part, there are two pfilts on each side => pfilt A0 and A1 on side A, and pfilt B0 and B1 on side B + * Each pfilt has 4 banks that can be switched between + * This mean there are 8 pfilt banks in an 8T8R on each side => 16 banks in total + * This function's job is to program the 8 banks on the side passed into the function + * This function should not try to program the upper 4 banks into A1/B1 if this is not an 8T8R part + */ + adi_apollo_blk_sel_t pfiltsMsk = (device->dev_info.is_8t8r) ? ADI_APOLLO_PFILT_ALL : ADI_APOLLO_PFILT_ALL_4T4R; + + for (coeff_set_idx = 0; coeff_set_idx 0) { + + /* Program pfilt coefficient sets */ + err = adi_apollo_pfilt_coeff_pgm(device, + ADI_APOLLO_RX, + pfilts, + ADI_APOLLO_PFILT_COEFF_IDX2B(coeff_set_idx), + config->coeffs[coeff_set_idx], + ADI_APOLLO_PFILT_COEFFS); + ADI_APOLLO_ERROR_RETURN(err); + + /* Configure pfilt gain and delay sets */ + blk_gain_dly_config.pfir_ix_gain = config->pfir_ix_gain_db[coeff_set_idx]; + blk_gain_dly_config.pfir_iy_gain = config->pfir_iy_gain_db[coeff_set_idx]; + blk_gain_dly_config.pfir_qx_gain = config->pfir_qx_gain_db[coeff_set_idx]; + blk_gain_dly_config.pfir_qy_gain = config->pfir_qy_gain_db[coeff_set_idx]; + blk_gain_dly_config.pfir_ix_scalar_gain = config->pfir_ix_scalar_gain_db[coeff_set_idx]; + blk_gain_dly_config.pfir_iy_scalar_gain = config->pfir_iy_scalar_gain_db[coeff_set_idx]; + blk_gain_dly_config.pfir_qx_scalar_gain = config->pfir_qx_scalar_gain_db[coeff_set_idx]; + blk_gain_dly_config.pfir_qy_scalar_gain = config->pfir_qy_scalar_gain_db[coeff_set_idx]; + blk_gain_dly_config.hc_delay = config->hc_prog_delay[coeff_set_idx]; + + err = adi_apollo_pfilt_gain_dly_pgm(device, + ADI_APOLLO_RX, + pfilts, + ADI_APOLLO_PFILT_COEFF_IDX2B(coeff_set_idx), + &blk_gain_dly_config); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + /* Program pfilt mode + * The mode of a filter is split into the i mode and the q mode (a mode pair) + * There are two mode pairs on each side, a mode pair for pfilt 0 and a mode pair for pfilt 1 + * i_mode[0] and q_mode[0] for pfilt 0 + * i_mode[1] and q_mode[1] for pfilt 1 + */ + blk_mode_config.data = config->real_data; + blk_mode_config.add_sub_sel = config->add_sub_sel; + blk_mode_config.dq_mode = device->dev_info.is_8t8r ? ADI_APOLLO_PFILT_QUAD_MODE : ADI_APOLLO_PFILT_DUAL_MODE; + blk_mode_config.mode_switch = config->mode_switch; + + /* Program the PFIR sets for 4T4R or 8T8R */ + for (ctrl_sets_idx = 0; ctrl_sets_idx < ADI_APOLLO_PFILT_CTRL_SETS; ctrl_sets_idx++) + { + blk_mode_config.pfir_i_mode[ctrl_sets_idx] = config->enable ? config->i_mode[ctrl_sets_idx] : ADI_APOLLO_PFILT_MODE_DISABLED; + blk_mode_config.pfir_q_mode[ctrl_sets_idx] = config->enable ? config->q_mode[ctrl_sets_idx] : ADI_APOLLO_PFILT_MODE_DISABLED; + + adi_apollo_blk_sel_t pfilts = pfiltsMsk & (ADI_APOLLO_PFILT_IDX2B(side, ctrl_sets_idx)); + + /* Only program the mode if the filter exists */ + if (pfilts > 0) { + + err = adi_apollo_pfilt_mode_pgm(device, + ADI_APOLLO_RX, + pfilts, + &blk_mode_config); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_rx_rxpath_misc_configure(adi_apollo_device_t *device, adi_apollo_sides_e side, adi_apollo_rxpath_misc_t *config) +{ + int32_t err; + adi_apollo_rx_misc_pgm_t rx_misc_pgm_params; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(config); + + /* RX crossbar1, ADC */ + err = adi_apollo_rxmux_xbar1_set(device, ADI_APOLLO_SIDE_IDX2B(side), config->mux0_out_adc_sel, + device->dev_info.is_8t8r ? ADI_APOLLO_RX_MUX0_NUM_8T8R : ADI_APOLLO_RX_MUX0_NUM_4T4R); + ADI_APOLLO_ERROR_RETURN(err); + + /* RX crossbar2, CDDC-to-FDDC */ + err = adi_apollo_rxmux_xbar2_set(device, ADI_APOLLO_SIDE_IDX2B(side), config->mux2_fddc_input_sel, ADI_APOLLO_RX_MUX2_NUM); + ADI_APOLLO_ERROR_RETURN(err); + + /* RX datapath clock config and low sample rate */ + rx_misc_pgm_params.datapath_clk = ADI_APOLLO_DATAPATH_CLK_ENABLE_INPHASE | ADI_APOLLO_DATAPATH_CLK_ENABLE_QPHASE; + rx_misc_pgm_params.low_samp_en = config->low_samp_en; + err = adi_apollo_rxmisc_pgm(device, ADI_APOLLO_SIDE_IDX2B(side), &rx_misc_pgm_params); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_rx_cfir_configure(adi_apollo_device_t *device, adi_apollo_sides_e side, adi_apollo_cfir_idx_e idx_cfir, adi_apollo_cfir_cfg_t *config) +{ + int32_t err; + uint8_t idx_profile, idx_set; + adi_apollo_cfir_pgm_t blk_mode_config; + uint16_t sparse_coeff_sel_sel[ADI_APOLLO_CFIR_NUM_TAPS] = {0}; + uint8_t sparse_mem_sel[ADI_APOLLO_CFIR_MEM_SEL_NUM] = {0}; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(config); + ADI_APOLLO_INVALID_PARAM_RETURN((idx_cfir > ADI_APOLLO_CFIRS_PER_SIDE-1)) + + /* CFIR top parameters */ + blk_mode_config.cfir_bypass = config->enable ? 0 : 1; //Bypass config + blk_mode_config.cfir_sparse_filt_en = config->sparse_mode; + blk_mode_config.cfir_32taps_en = config->cfir_mode; //cfir_32taps_en config + blk_mode_config.cfir_coeff_transfer = 0; //coeff_transfer should go from 0 to 1 + + err = adi_apollo_cfir_pgm(device, ADI_APOLLO_RX, ADI_APOLLO_CFIR_IDX2B(side, idx_cfir), &blk_mode_config); + ADI_APOLLO_ERROR_RETURN(err); + + /* Program CFIR coefficients, gain, scalar gain and sparse values for all profiles */ + for (idx_profile = 0; idx_profile < ADI_APOLLO_CFIR_NUM_PROFILES; idx_profile++) { + for (idx_set = 0; idx_set < ADI_APOLLO_CFIR_COEFF_SETS; idx_set++) { + err = adi_apollo_cfir_coeff_pgm(device, ADI_APOLLO_RX, ADI_APOLLO_CFIR_IDX2B(side, idx_cfir), + ADI_APOLLO_CFIR_PROFILE_IDX2B(idx_profile), + ADI_APOLLO_CFIR_COEFF_SET_IDX2B(idx_set), + config->coeffs_i[idx_profile][idx_set], config->coeffs_q[idx_profile][idx_set], ADI_APOLLO_CFIR_NUM_TAPS); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_cfir_scalar_pgm(device, ADI_APOLLO_RX, ADI_APOLLO_CFIR_IDX2B(side, idx_cfir), + ADI_APOLLO_CFIR_PROFILE_IDX2B(idx_profile), + ADI_APOLLO_CFIR_COEFF_SET_IDX2B(idx_set), + config->scalar_i[idx_profile][idx_set], config->scalar_q[idx_profile][idx_set]); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_cfir_gain_pgm(device, ADI_APOLLO_RX, ADI_APOLLO_CFIR_IDX2B(side, idx_cfir), + ADI_APOLLO_CFIR_PROFILE_IDX2B(idx_profile), + ADI_APOLLO_CFIR_COEFF_SET_IDX2B(idx_set), + config->cfir_gain_dB[idx_profile][idx_set]); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_cfir_sparse_coeff_sel_pgm(device, ADI_APOLLO_RX, ADI_APOLLO_CFIR_IDX2B(side, idx_cfir), + ADI_APOLLO_CFIR_PROFILE_IDX2B(idx_profile), + ADI_APOLLO_CFIR_COEFF_SET_IDX2B(idx_set), + sparse_coeff_sel_sel, ADI_APOLLO_CFIR_NUM_TAPS); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_cfir_sparse_mem_sel_pgm(device, ADI_APOLLO_RX, ADI_APOLLO_CFIR_IDX2B(side, idx_cfir), + ADI_APOLLO_CFIR_PROFILE_IDX2B(idx_profile), + ADI_APOLLO_CFIR_COEFF_SET_IDX2B(idx_set), + sparse_mem_sel, ADI_APOLLO_CFIR_MEM_SEL_NUM); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + /* Make profile #0 active for all data paths. Transfers profile 0 coeffs and gains to CFIR block */ + err = adi_apollo_cfir_profile_sel(device, ADI_APOLLO_RX, ADI_APOLLO_CFIR_IDX2B(side, idx_cfir), + ADI_APOLLO_CFIR_DP_ALL, ADI_APOLLO_CFIR_PROFILE_0); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_rx_fsrc_configure(adi_apollo_device_t *device, adi_apollo_sides_e side, uint8_t idx_fsrc, adi_apollo_fsrc_cfg_t *config) +{ + int32_t err; + adi_apollo_fsrc_pgm_t blk_mode_config; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(config); + ADI_APOLLO_INVALID_PARAM_RETURN((idx_fsrc > ADI_APOLLO_FSRC_PER_SIDE_NUM-1)) + + /* Program fsrc */ + blk_mode_config.fsrc_rate_int = config->fsrc_rate_int; + blk_mode_config.fsrc_rate_frac_a = config->fsrc_rate_frac_a; + blk_mode_config.fsrc_rate_frac_b = config->fsrc_rate_frac_b; + blk_mode_config.sample_frac_delay = config->fsrc_delay; + blk_mode_config.fsrc_en0 = config->enable0; + blk_mode_config.fsrc_en1 = config->enable1; + blk_mode_config.gain_reduction = config->gain_reduction; + blk_mode_config.ptr_overwrite = config->ptr_overwrite; + blk_mode_config.ptr_syncrstval = config->ptr_syncrstval; + blk_mode_config.fsrc_data_mult_dither_en = config->data_mult_dither_en; + blk_mode_config.fsrc_dither_en = config->dither_en; + blk_mode_config.fsrc_4t4r_split = config->split_4t4r; + blk_mode_config.fsrc_bypass = (config->enable0 || config->enable1) ? 0 : 1; + blk_mode_config.fsrc_1x_mode = config->mode_1x; + + err = adi_apollo_fsrc_pgm(device, ADI_APOLLO_RX, + ADI_APOLLO_FSRC_IDX2B(side, idx_fsrc), + &blk_mode_config); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_rx_dformat_configure(adi_apollo_device_t *device, adi_apollo_sides_e side, + adi_apollo_jesd_links_e link_idx, adi_apollo_dformat_cfg_t *config, adi_apollo_jesd_tx_link_cfg_t *jtx_link_config) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(jtx_link_config); + ADI_APOLLO_NULL_POINTER_RETURN(config); + ADI_APOLLO_INVALID_PARAM_RETURN((side > ADI_APOLLO_NUM_SIDES - 1)); + ADI_APOLLO_INVALID_PARAM_RETURN((link_idx > ADI_APOLLO_JESD_LINKS - 1)) + + adi_apollo_dformat_pgm_t dformat_config = { + .dcm_ratio = jtx_link_config->link_dp_ratio, + .total_dcm = jtx_link_config->link_total_ratio, + .link_en = jtx_link_config->link_in_use, + .dfor_ddc_dither_en = config->ddc_dither_en, + .dfor_inv = config->inv, + .dfor_res = config->res, + .dfor_sel = config->sel, + .invalid_en = config->rm_fifo.invalid_en, + .sample_repeat_en = config->rm_fifo.sample_repeat_en + }; + + err = adi_apollo_dformat_pgm(device, ADI_APOLLO_DFMT_IDX2B(side, link_idx), &dformat_config); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_rx_smon_configure(adi_apollo_device_t *device, adi_apollo_sides_e side, adi_apollo_smon_idx_e idx, + adi_apollo_smon_cfg_t *config) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(config); + ADI_APOLLO_INVALID_PARAM_RETURN((side > ADI_APOLLO_NUM_SIDES - 1)); + ADI_APOLLO_INVALID_PARAM_RETURN((idx > ADI_APOLLO_SMONS_PER_SIDE - 1)) + + adi_apollo_smon_pgm_t smon_pgm = { + .sframer_mode_en = (config->sframer_mode == ADI_APOLLO_RX_SMON_FRAMER_MODE_5B) ? ADI_APOLLO_SFRAMER_FIVE_BIT_ENABLE : ADI_APOLLO_SFRAMER_TEN_BIT_ENABLE, + .smon_period = config->period, + .thresh_low = config->thresh_low, + .thresh_high = config->thresh_high, + .sync_en = config->sync_en, + .sync_next = config->sync_next, + .sframer_en = config->sframer_en, + .sframer_mode = config->sframer_mode, + .sframer_insel = 2, // only peak mag in framer supported + .peak_en = config->peak_en, + .status_rdsel = 1, // only peak mag in reg readback supported + .jlink_sel = config->jlink_sel, + .gpio_en = config->gpio_en + }; + err = adi_apollo_smon_pgm(device, ADI_APOLLO_SMON_IDX2B(side, idx), &smon_pgm); + ADI_CMS_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_rxen.c b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_rxen.c new file mode 100644 index 00000000000000..86c3bfaa371c0f --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_rxen.c @@ -0,0 +1,399 @@ +/*! + * \brief APIs for Rx power control + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_RXEN + * @{ + */ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_rxen.h" +#include "adi_apollo_rxen_local.h" +#include "adi_apollo_pfilt.h" +#include "adi_apollo_cddc.h" +#include "adi_apollo_fddc.h" +#include "adi_apollo_private_blk_sel_types.h" + +#include "adi_apollo_bf_conv_pow_onoff.h" +#include "adi_apollo_bf_txen_power_ctrl.h" +#include "adi_apollo_bf_txrx_enable.h" + +#include "adi_apollo_config.h" +#include "adi_apollo_hal.h" + +/*==================== P U B L I C A P I C O D E ====================*/ + +int32_t adi_apollo_rxen_pwrup_ctrl_config_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t adcs, const adi_apollo_rxen_pwrup_blk_config_t *config) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(config); + ADI_APOLLO_RXEN_BLK_SEL_MASK(adcs); + + err = adi_apollo_rxen_pwrup_ctrl_set(device, adcs, &config->ctrl); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_rxen_pwrup_ctrl_edge_set(device, adcs, &config->edge); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_rxen_pwrup_ctrl_count_set(device, adcs, &config->count); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_rxen_pwrup_ctrl_pin_set(device, adcs, config->pin_en); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_rxen_pwrup_ctrl_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t adcs, const adi_apollo_rxen_pwrup_ctrl_t *config) +{ + int32_t err; + uint8_t i; + adi_apollo_blk_sel_t adc; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(config); + ADI_APOLLO_RXEN_BLK_SEL_MASK(adcs); + + for(i = 0; i < ADI_APOLLO_ADC_NUM; i ++) { + adc = adcs & (ADI_APOLLO_RXEN_ADC_A0 << i); + if (adc > 0) { + regmap_base_addr = calc_txen_power_ctrl_base(i); + + err = adi_apollo_hal_bf_set(device, BF_SM_EN_INFO(regmap_base_addr), config->sm_en); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_SPI_TXEN_ENA_INFO(regmap_base_addr), config->spi_rxen_en); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_SPI_TXEN_INFO(regmap_base_addr), config->spi_rxen); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_SEL_CNT_RATE_INFO(regmap_base_addr), (config->sm_clk_rate == ADI_APOLLO_PUC_CLK_RATE_FS_DIV_256) ? 1 : 0); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_rxen_pwrup_ctrl_edge_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t adcs, const adi_apollo_rxen_pwrup_ctrl_edge_t *config) +{ + int32_t err; + uint8_t i; + adi_apollo_blk_sel_t adc; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(config); + ADI_APOLLO_RXEN_BLK_SEL_MASK(adcs); + + for(i = 0; i < ADI_APOLLO_ADC_NUM; i ++) { + adc = adcs & (ADI_APOLLO_RXEN_ADC_A0 << i); + if (adc > 0) { + regmap_base_addr = calc_txen_power_ctrl_base(i); + + err = adi_apollo_hal_bf_set(device, BF_DAC_RISE_INFO(regmap_base_addr), config->adc_rise); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_DAC_FALL_INFO(regmap_base_addr), config->adc_fall); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_DIG_RISE_INFO(regmap_base_addr), config->dig_rise); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_DIG_FALL_INFO(regmap_base_addr), config->dig_fall); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_PA_RISE_INFO(regmap_base_addr), config->pa_rise); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_PA_FALL_INFO(regmap_base_addr), config->pa_fall); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_rxen_pwrup_ctrl_count_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t adcs, const adi_apollo_rxen_pwrup_ctrl_count_t *config) +{ + int32_t err; + uint8_t i; + adi_apollo_blk_sel_t adc; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(config); + ADI_APOLLO_RXEN_BLK_SEL_MASK(adcs); + + for(i = 0; i < ADI_APOLLO_ADC_NUM; i ++) { + adc = adcs & (ADI_APOLLO_RXEN_ADC_A0 << i); + if (adc > 0) { + regmap_base_addr = calc_txen_power_ctrl_base(i); + + err = adi_apollo_hal_bf_set(device, BF_COUNT_MAXA_INFO(regmap_base_addr), config->count_maxa); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_COUNT_MAXB_INFO(regmap_base_addr), config->count_maxb); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_COUNT_MAXC_INFO(regmap_base_addr), config->count_maxc); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_COUNT_MAXD_INFO(regmap_base_addr), config->count_maxd); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_COUNT_MAXE_INFO(regmap_base_addr), config->count_maxe); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_COUNT_MAXF_INFO(regmap_base_addr), config->count_maxf); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_rxen_pwrup_ctrl_pin_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t adcs, adi_apollo_puc_en_pin_sel_e pin) +{ + int32_t err; + uint8_t i; + adi_apollo_blk_sel_t adc; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_RXEN_BLK_SEL_MASK(adcs); + + for(i = 0; i < ADI_APOLLO_ADC_NUM; i ++) { + adc = adcs & (ADI_APOLLO_RXEN_ADC_A0 << i); + if (adc > 0) { + regmap_base_addr = calc_txen_power_ctrl_base(i); + + err = adi_apollo_hal_bf_set(device, BF_TXEN_SEL_INFO(regmap_base_addr), pin); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_rxen_pwrup_ctrl_spien_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t adcs, uint8_t spi_en) +{ + int32_t err; + uint8_t i; + adi_apollo_blk_sel_t adc; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_RXEN_BLK_SEL_MASK(adcs); + + for(i = 0; i < ADI_APOLLO_ADC_NUM; i ++) { + adc = adcs & (ADI_APOLLO_RXEN_ADC_A0 << i); + if (adc > 0) { + regmap_base_addr = calc_txen_power_ctrl_base(i); + + err = adi_apollo_hal_bf_set(device, BF_SPI_TXEN_INFO(regmap_base_addr), spi_en); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + + + +int32_t adi_apollo_rxen_config_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t dig_enables, const adi_apollo_rxen_blk_config_t *config) +{ + int32_t err; + uint8_t i, side; + adi_apollo_blk_sel_t dig_en; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(config); + ADI_APOLLO_INVALID_PARAM_RETURN(config->pfilt_sel > ADI_APOLLO_PFILT_ALL); + ADI_APOLLO_RXEN_BLK_SEL_MASK(dig_enables); + + for(i = 0; i < ADI_APOLLO_DIG_EN_NUM; i ++) { + dig_en = dig_enables & (ADI_APOLLO_RXEN_EN_A0 << i); + if (dig_en > 0) { + side = i / ADI_APOLLO_DIG_EN_PER_SIDE_NUM; + regmap_base_addr = calc_rx_enable_base(side); + + /* Enable polarity */ + err = adi_apollo_hal_bf_set(device, + BF_ENABLE_POL_INFO(regmap_base_addr, (i % ADI_APOLLO_DIG_EN_PER_SIDE_NUM)), + (config->enable_polarity == ADI_APOLLO_DIG_EN_ACTIVE_HIGH) ? 0 : 1); + ADI_APOLLO_ERROR_RETURN(err); + + /* SPI enable */ + err = adi_apollo_hal_bf_set(device, + BF_ENABLE_SPI_INFO(regmap_base_addr, (i % ADI_APOLLO_DIG_EN_PER_SIDE_NUM)), + (config->spi_en == ADI_APOLLO_DISABLE) ? 0 : 1); + ADI_APOLLO_ERROR_RETURN(err); + + /* SPIEN enable */ + err = adi_apollo_hal_bf_set(device, + BF_ENABLE_SPIEN_INFO(regmap_base_addr, (i % ADI_APOLLO_DIG_EN_PER_SIDE_NUM)), + (config->spien_en == ADI_APOLLO_DISABLE) ? 0 : 1); + ADI_APOLLO_ERROR_RETURN(err); + + /* Slice select - other selects are OR'd with slice */ + err = adi_apollo_hal_bf_set(device, + BF_SLICE_SEL_INFO(regmap_base_addr, (i % ADI_APOLLO_DIG_EN_PER_SIDE_NUM)), + (side == 0) ? config->slice_sel : config->slice_sel >> ADI_APOLLO_MAX_SLICES_PER_SIDE_NUM); + ADI_APOLLO_ERROR_RETURN(err); + + /* Linx select */ + err = adi_apollo_hal_bf_set(device, + BF_LINX_SEL_INFO(regmap_base_addr, (i % ADI_APOLLO_DIG_EN_PER_SIDE_NUM)), + (side == 0) ? config->linx_sel : config->linx_sel >> ADI_APOLLO_NUM_LINX_PER_SIDE); + ADI_APOLLO_ERROR_RETURN(err); + + /* PFILT select */ + err = adi_apollo_hal_bf_set(device, + BF_PFILT_SEL_INFO(regmap_base_addr, (i % ADI_APOLLO_DIG_EN_PER_SIDE_NUM)), + (side == 0) ? config->pfilt_sel : config->pfilt_sel >> ADI_APOLLO_PFILT_PER_SIDE); + ADI_APOLLO_ERROR_RETURN(err); + + /* CDDC select */ + err = adi_apollo_hal_bf_set(device, + BF_CDUC_CDDC_SEL_INFO(regmap_base_addr, (i % ADI_APOLLO_DIG_EN_PER_SIDE_NUM)), + (side == 0) ? config->cddc_sel : config->cddc_sel >> ADI_APOLLO_CDDC_PER_SIDE_NUM); + ADI_APOLLO_ERROR_RETURN(err); + + /* FDDC select */ + err = adi_apollo_hal_bf_set(device, + BF_FDUC_FDDC_SEL_INFO(regmap_base_addr, (i % ADI_APOLLO_DIG_EN_PER_SIDE_NUM)), + (side == 0) ? config->fddc_sel : config->fddc_sel >> ADI_APOLLO_FDDC_PER_SIDE_NUM); + ADI_APOLLO_ERROR_RETURN(err); + + /* CFIR select */ + err = adi_apollo_hal_bf_set(device, + BF_CFIR_SEL_INFO(regmap_base_addr, (i % ADI_APOLLO_DIG_EN_PER_SIDE_NUM)), + (side == 0) ? config->cfir_sel : config->cfir_sel >> ADI_APOLLO_NUM_CFIR_PER_SIDE); + + /* FSRC select */ + err = adi_apollo_hal_bf_set(device, + BF_FSRC_SEL_INFO(regmap_base_addr, (i % ADI_APOLLO_DIG_EN_PER_SIDE_NUM)), + (side == 0) ? config->fsrc_sel : config->fsrc_sel >> ADI_APOLLO_NUM_FSRC_PER_SIDE); + ADI_APOLLO_ERROR_RETURN(err); + + /* JTX link select */ + err = adi_apollo_hal_bf_set(device, + BF_JRX_JTX_LINK_SEL_INFO(regmap_base_addr, (i % ADI_APOLLO_DIG_EN_PER_SIDE_NUM)), + (side == 0) ? config->jtx_link_sel : config->jtx_link_sel >> ADI_APOLLO_NUM_JTX_LINKS_PER_SIDE); + ADI_APOLLO_ERROR_RETURN(err); + + /* JTX phy select */ + err = adi_apollo_hal_bf_set(device, + BF_JRX_JTX_PHY_SEL_INFO(regmap_base_addr, (i % ADI_APOLLO_DIG_EN_PER_SIDE_NUM)), + (side == 0) ? config->jtx_phy_sel_side_a : config->jtx_phy_sel_side_b); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_rxen_ctrl_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t dig_enables, const adi_apollo_rxen_ctrl_t *config) +{ + int32_t err; + uint8_t i, side; + adi_apollo_blk_sel_t dig_en; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(config); + ADI_APOLLO_RXEN_BLK_SEL_MASK(dig_enables); + + for(i = 0; i < ADI_APOLLO_DIG_EN_NUM; i ++) { + dig_en = dig_enables & (ADI_APOLLO_RXEN_EN_A0 << i); + if (dig_en > 0) { + side = i / ADI_APOLLO_DIG_EN_PER_SIDE_NUM; + regmap_base_addr = calc_rx_enable_base(side); + + /* Enable polarity */ + err = adi_apollo_hal_bf_set(device, + BF_ENABLE_POL_INFO(regmap_base_addr, (i % ADI_APOLLO_DIG_EN_PER_SIDE_NUM)), + (config->enable_polarity == ADI_APOLLO_DIG_EN_ACTIVE_HIGH) ? 0 : 1); + ADI_APOLLO_ERROR_RETURN(err); + + /* SPI enable */ + err = adi_apollo_hal_bf_set(device, + BF_ENABLE_SPI_INFO(regmap_base_addr, (i % ADI_APOLLO_DIG_EN_PER_SIDE_NUM)), + (config->spi_en == ADI_APOLLO_DISABLE) ? 0 : 1); + ADI_APOLLO_ERROR_RETURN(err); + + /* SPIEN enable */ + err = adi_apollo_hal_bf_set(device, + BF_ENABLE_SPIEN_INFO(regmap_base_addr, (i % ADI_APOLLO_DIG_EN_PER_SIDE_NUM)), + (config->spien_en == ADI_APOLLO_DISABLE) ? 0 : 1); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_rxen_spien_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t dig_enables, uint8_t spi_en) +{ + int32_t err; + uint8_t i, side; + adi_apollo_blk_sel_t dig_en; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_RXEN_BLK_SEL_MASK(dig_enables); + + for(i = 0; i < ADI_APOLLO_DIG_EN_NUM; i ++) { + dig_en = dig_enables & (ADI_APOLLO_RXEN_EN_A0 << i); + if (dig_en > 0) { + side = i / ADI_APOLLO_DIG_EN_PER_SIDE_NUM; + regmap_base_addr = calc_rx_enable_base(side); + + /* SPI enable */ + err = adi_apollo_hal_bf_set(device, + BF_ENABLE_SPI_INFO(regmap_base_addr, (i % ADI_APOLLO_DIG_EN_PER_SIDE_NUM)), + (spi_en == ADI_APOLLO_DISABLE) ? 0 : 1); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + + + +uint32_t calc_txen_power_ctrl_base(int32_t adc_index) +{ + static uint32_t txen_power_ctrl_regmap[] = { + RXEN_POWER_CTRL0_RX_SLICE_0_RX_DIGITAL0, RXEN_POWER_CTRL1_RX_SLICE_0_RX_DIGITAL0, + RXEN_POWER_CTRL0_RX_SLICE_1_RX_DIGITAL0, RXEN_POWER_CTRL1_RX_SLICE_1_RX_DIGITAL0, + RXEN_POWER_CTRL0_RX_SLICE_0_RX_DIGITAL1, RXEN_POWER_CTRL1_RX_SLICE_0_RX_DIGITAL1, + RXEN_POWER_CTRL0_RX_SLICE_1_RX_DIGITAL1, RXEN_POWER_CTRL1_RX_SLICE_1_RX_DIGITAL1 + }; + + return (txen_power_ctrl_regmap[adc_index]); +} + +uint32_t calc_rx_enable_base(int32_t index) +{ + static uint32_t rx_enable_regmap[] = { + TXRX_ENABLE_RX_DIGITAL0, TXRX_ENABLE_RX_DIGITAL1 + }; + + return (rx_enable_regmap[index]); +} +/*! @} */ \ No newline at end of file diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_rxen_local.h b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_rxen_local.h new file mode 100644 index 00000000000000..033c3f04771d39 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_rxen_local.h @@ -0,0 +1,37 @@ +/*! + * \brief RXEN local defines and prototypes + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_RXEN + * @{ + */ +#ifndef __ADI_APOLLO_RXEN_LOCAL_H__ +#define __ADI_APOLLO_RXEN_LOCAL_H__ + +/*============= I N C L U D E S ============*/ + +/*============= D E F I N E S ==============*/ + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +uint32_t calc_txen_power_ctrl_base(int32_t adc_index); +uint32_t calc_rx_enable_base(int32_t index); + +#ifndef CLIENT_IGNORE +#endif /* CLIENT_IGNORE*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_RXEN_LOCAL_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_rxmisc.c b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_rxmisc.c new file mode 100644 index 00000000000000..6949e2f27b533e --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_rxmisc.c @@ -0,0 +1,103 @@ +/*! + * \brief Rx Misc functional block API implementation + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_RXMISC + * @{ + */ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_rxmisc.h" +#include "adi_apollo_rxmisc_local.h" + +#include "adi_apollo_bf_core.h" +#include "adi_apollo_bf_rx_misc.h" + +#include "adi_apollo_config.h" +#include "adi_apollo_hal.h" + +/*==================== P U B L I C A P I C O D E ====================*/ + +int32_t adi_apollo_rxmisc_low_samp_set(adi_apollo_device_t *device, adi_apollo_side_select_e side_sel, uint8_t low_samp_en) +{ + int32_t err; + uint8_t side, side_index; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + for (side_index = 0; side_index < ADI_APOLLO_NUM_SIDES; side_index++) { + side = side_sel & (ADI_APOLLO_SIDE_A << side_index); + if (side > 0) { + regmap_base_addr = calc_rx_misc_base(side_index); + + err = adi_apollo_hal_bf_set(device, BF_LOW_SAMP_RX_MISC_INFO(regmap_base_addr), low_samp_en); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_rxmisc_pgm(adi_apollo_device_t *device, adi_apollo_side_select_e side_sel, adi_apollo_rx_misc_pgm_t *config) +{ + int32_t err; + uint8_t side, side_index; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + for (side_index = 0; side_index < ADI_APOLLO_NUM_SIDES; side_index++) { + side = side_sel & (ADI_APOLLO_SIDE_A << side_index); + if (side > 0) { + regmap_base_addr = calc_rx_misc_base(side_index); + + err = adi_apollo_hal_bf_set(device, BF_DATAPATH_CLK_EN_INFO(regmap_base_addr), config->datapath_clk); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_LOW_SAMP_RX_MISC_INFO(regmap_base_addr), config->low_samp_en); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_rxmisc_dp_reset(adi_apollo_device_t *device, adi_apollo_side_select_e side_sel, uint8_t reset_en) +{ + int32_t err; + uint8_t side, side_index; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + for (side_index = 0; side_index < ADI_APOLLO_NUM_SIDES; side_index++) { + side = side_sel & (ADI_APOLLO_SIDE_A << side_index); + if (side > 0) { + if (side_index == 0) + err = adi_apollo_hal_bf_set(device, BF_RX_DP_RESET_A_INFO, reset_en); + else + err = adi_apollo_hal_bf_set(device, BF_RX_DP_RESET_B_INFO, reset_en); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +uint32_t calc_rx_misc_base(int32_t side_idx) +{ + static uint32_t rx_misc_regmap[ADI_APOLLO_NUM_SIDES] = { + RX_MISC_RX_DIGITAL0, + RX_MISC_RX_DIGITAL1 + }; + return rx_misc_regmap[side_idx]; +} +/*! @} */ \ No newline at end of file diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_rxmisc_local.h b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_rxmisc_local.h new file mode 100644 index 00000000000000..dff49280d70907 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_rxmisc_local.h @@ -0,0 +1,36 @@ +/*! + * \brief Rx misc functional block local API implementation + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_RXMISC + * @{ + */ +#ifndef __ADI_APOLLO_RXMISC_LOCAL_H__ +#define __ADI_APOLLO_RXMISC_LOCAL_H__ + +/*============= I N C L U D E S ============*/ + +/*============= D E F I N E S ==============*/ + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +uint32_t calc_rx_misc_base(int32_t side_sel); + +#ifndef CLIENT_IGNORE +#endif /* CLIENT_IGNORE*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_RXMISC_LOCAL_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_rxmux.c b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_rxmux.c new file mode 100644 index 00000000000000..db670dbef23a5d --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_rxmux.c @@ -0,0 +1,134 @@ +/*! + * \brief Rx Crossbar Mux functional block API implementation + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_RXMUX + * @{ + */ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_rxmux.h" +#include "adi_apollo_rxmux_local.h" +#include "adi_apollo_rxmisc_local.h" + +#include "adi_apollo_jtx.h" + +#include "adi_apollo_bf_rx_misc.h" +#include "adi_apollo_bf_rx_datin.h" +#include "adi_apollo_bf_jtx_dual_link.h" + +#include "adi_apollo_config.h" +#include "adi_apollo_hal.h" + +/*==================== P U B L I C A P I C O D E ====================*/ + +int32_t adi_apollo_rxmux_xbar1_set(adi_apollo_device_t *device, adi_apollo_side_select_e side_sel, adi_apollo_rx_mux0_sel_e cbout_from_adc_sel[], uint32_t length) +{ + int32_t err; + uint8_t cb_out, side, side_index, bf_val; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(cbout_from_adc_sel); + + if (device->dev_info.is_8t8r) { + ADI_APOLLO_INVALID_PARAM_RETURN(length != ADI_APOLLO_RX_MUX0_NUM_8T8R); + } else { + ADI_APOLLO_INVALID_PARAM_RETURN(length != ADI_APOLLO_RX_MUX0_NUM_4T4R); + } + + for (side_index = 0; side_index < ADI_APOLLO_NUM_SIDES; side_index++) { + side = side_sel & (ADI_APOLLO_SIDE_A << side_index); + if (side > 0) { + + for (cb_out = 0; cb_out < length; cb_out++) { + regmap_base_addr = calc_rx_datin_base((cb_out % 2) + 2*side_index); + + bf_val = cbout_from_adc_sel[cb_out]; + + if (cb_out < 2) { + err = adi_apollo_hal_bf_set(device, BF_ADC_0_MUX_SEL_INFO(regmap_base_addr), bf_val); + ADI_APOLLO_ERROR_RETURN(err); + } else { + err = adi_apollo_hal_bf_set(device, BF_ADC_1_MUX_SEL_INFO(regmap_base_addr), bf_val); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_rxmux_xbar2_set(adi_apollo_device_t *device, adi_apollo_side_select_e side_sel, adi_apollo_rx_mux2_sel_e coarse_to_fine_xbar_sel[], uint32_t length) +{ + int32_t err; + uint8_t side, side_index; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(coarse_to_fine_xbar_sel); + ADI_APOLLO_INVALID_PARAM_RETURN(length != ADI_APOLLO_RX_MUX2_NUM); + + for (side_index = 0; side_index < ADI_APOLLO_NUM_SIDES; side_index++) { + side = side_sel & (ADI_APOLLO_SIDE_A << side_index); + if (side > 0) { + + regmap_base_addr = calc_rx_misc_base(side_index); + + err = adi_apollo_hal_bf_set(device, BF_CB_SEL_F0_INFO(regmap_base_addr), coarse_to_fine_xbar_sel[0]); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_CB_SEL_F1_INFO(regmap_base_addr), coarse_to_fine_xbar_sel[1]); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_CB_SEL_F2_INFO(regmap_base_addr), coarse_to_fine_xbar_sel[2]); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_CB_SEL_F3_INFO(regmap_base_addr), coarse_to_fine_xbar_sel[3]); + ADI_APOLLO_ERROR_RETURN(err); + + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_rxmux_sample_xbar_set(adi_apollo_device_t *device, uint16_t link_sel, uint8_t sample_offset, adi_apollo_rxmux_sample_sel_e sample_sel[], uint32_t length) +{ + int32_t err; + uint32_t regmap_base_addr = 0; + uint8_t i, j; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(sample_sel); + ADI_APOLLO_INVALID_PARAM_RETURN((sample_offset + length) > ADI_APOLLO_JESD_MAX_SAMPLE_XBAR_IDXS); + + for (i = 0; i < ADI_APOLLO_NUM_JTX_LINKS; i++) { + if ((1 << i) & link_sel) { + regmap_base_addr = calc_jtx_dual_link_base(i); + for (j = 0; j < length; j++) + err = adi_apollo_hal_bf_set(device, BF_JTX_CONV_SEL_INFO(regmap_base_addr, sample_offset + j), sample_sel[j]); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +uint32_t calc_rx_datin_base(int32_t adc_mux_index) +{ + static uint32_t rx_datin_regmap[] = { + RX_DATIN_RX_SLICE_0_RX_DIGITAL0, RX_DATIN_RX_SLICE_1_RX_DIGITAL0, + RX_DATIN_RX_SLICE_0_RX_DIGITAL1, RX_DATIN_RX_SLICE_1_RX_DIGITAL1 + }; + return rx_datin_regmap[adc_mux_index]; +} +/*! @} */ \ No newline at end of file diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_rxmux_local.h b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_rxmux_local.h new file mode 100644 index 00000000000000..cf08361dcc85bb --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_rxmux_local.h @@ -0,0 +1,36 @@ +/*! + * \brief Rx Crossbar Mux functional block local API implementation + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_RXMUX + * @{ + */ +#ifndef __ADI_APOLLO_RXMUX_LOCAL_H__ +#define __ADI_APOLLO_RXMUX_LOCAL_H__ + +/*============= I N C L U D E S ============*/ + +/*============= D E F I N E S ==============*/ + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +uint32_t calc_rx_datin_base(int32_t adc_mux_index); + +#ifndef CLIENT_IGNORE +#endif /* CLIENT_IGNORE*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_RXMUX_LOCAL_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_serdes.c b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_serdes.c new file mode 100644 index 00000000000000..f77940f793fc20 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_serdes.c @@ -0,0 +1,840 @@ +/*! + * \brief APIs for SerDes related blocks + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_SERDES + * @{ + */ + +#define ADI_APOLLO_SERDES_JRX_TIMEOUT 60 + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_serdes.h" +#include "adi_apollo_config.h" + +#include "adi_apollo_bf_pll_mem_map.h" +#include "adi_apollo_bf_rtclk_gen.h" +#include "adi_apollo_bf_serdes_txdig_12pack_apollo_core1p1.h" +#include "adi_apollo_bf_serdes_txdig_phy_core1p2.h" +#include "adi_apollo_bf_serdes_rxdig_phy_core1p3.h" + +#include "adi_apollo_hal.h" +#include "adi_apollo_cfg.h" +#include "adi_apollo_mailbox.h" + +/*============= D E F I N E S ==============*/ +#define ADI_APOLLO_SERDES_RX_LANES_MAX_PER_SIDE (12U) +#define ADI_APOLLO_SERDES_RX_TEST_HORIZ_EYE_RESULTS (1U) +#define ADI_APOLLO_SERDES_RX_TEST_VERT_EYE_RESULTS (3U) + + +static uint32_t calc_serdes_tx_12pack_base(int32_t index); +static uint32_t calc_serdes_tx_dig_base(int32_t index); +static uint32_t calc_serdes_rx_dig_lane_base(int32_t index); +static uint32_t calc_serdes_tx_dig_lane_base(int32_t index); + +static int32_t reset_synth(adi_apollo_device_t *device); +static int32_t reset_odiv(adi_apollo_device_t *device); + +/* Table of reset functions */ +static int32_t (*reset_tbl[])(adi_apollo_device_t *device) = {reset_synth, reset_odiv}; + +int32_t adi_apollo_serdes_jrx_cal(adi_apollo_device_t* device) +{ + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + return adi_apollo_serdes_jrx_init_cal(device, ADI_APOLLO_TXRX_SERDES_12PACK_ALL, ADI_APOLLO_INIT_CAL_ENABLED); +} + +int32_t adi_apollo_serdes_jrx_init_cal(adi_apollo_device_t* device, uint16_t serdes, adi_apollo_init_cal_cfg_e init_cal_cfg) +{ + int32_t err = API_CMS_ERROR_OK; + uint8_t i = 0; + adi_apollo_mailbox_resp_run_init_get_completion_t run_init_get_completion = {0}; + adi_apollo_mailbox_resp_run_init_t run_init_resp = {0}; + uint32_t max_delay_us = ADI_APOLLO_SERDES_JRX_TIMEOUT * 1000000; + uint32_t poll_delay_us = 1000000; + uint32_t delay_us; + uint8_t cal_complete = 0; + + adi_apollo_mailbox_cmd_run_init_t run_init_cmd = {0}; + adi_apollo_mailbox_resp_run_init_get_detailed_status_t run_init_cal_detailed_status_resp = {0}; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(serdes > ADI_APOLLO_TXRX_SERDES_12PACK_ALL); + + /* Init the mailbox command struct */ + run_init_cmd.cal_mask = APOLLO_INIT_CAL_MSK_IC_SERDES_RX; + run_init_cmd.serdes_rx_pack_mask = serdes; + run_init_cmd.rx_channel_mask = 0; + run_init_cmd.tx_channel_mask = 0; + run_init_cmd.serdes_tx_pack_mask = 0; + run_init_cmd.linearx_chan_mask = 0; + + /* Set SerDes Init Cal Configuration */ + adi_apollo_hal_log_write(device, ADI_CMS_LOG_API, "SerDes JRx Init cal config: %d. ref: adi_apollo_init_cal_cfg_e\n", init_cal_cfg); + if (err = adi_apollo_cfg_serdes_rx_init_cal_cfg_set(device, serdes, init_cal_cfg), err != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Error from adi_apollo_cfg_serdes_rx_init_cal_cfg_set() %d", err); + goto end; + } + + /* Send mailbox command to start cal */ + adi_apollo_hal_log_write(device, ADI_CMS_LOG_API, "Starting SerDes JRx foreground cal\n"); + if (err = adi_apollo_mailbox_run_init(device, &run_init_cmd, &run_init_resp), err != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Error from adi_apollo_mailbox_run_init() %d", err); + goto end; + } + + if (run_init_resp.status != APOLLO_CPU_NO_ERROR) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "SerDes JRx Init cal error code = 0x%x\n", run_init_resp.status); + err = API_CMS_ERROR_MAILBOX_RESP_STATUS; + goto end; + } + + /* Wait for SERDES cal to finish. */ + for (delay_us = 0; delay_us < max_delay_us; delay_us += poll_delay_us) { + if (err = adi_apollo_mailbox_run_init_get_completion(device, &run_init_get_completion), err != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "adi_apollo_mailbox_run_init_get_completion() err %d\n"); + goto end; + } + + if ((delay_us % (5 * poll_delay_us)) == 0) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_API, "SerDes JRx Init Cal: status=%d in_progress=%d success=%d %ds\n", + run_init_get_completion.status, run_init_get_completion.in_progress, run_init_get_completion.success, (delay_us / poll_delay_us)); + } + + if (run_init_get_completion.in_progress == 0) { + cal_complete = 1; + break; + } + + adi_apollo_hal_delay_us(device, poll_delay_us); + } + + if (run_init_get_completion.success != 1) { + if (err = adi_apollo_mailbox_run_init_get_detailed_status(device, &run_init_cal_detailed_status_resp), err != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Error from adi_apollo_mailbox_run_init_get_detailed_status() %d.\n", err); + goto end; + } + + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "cpu_status = 0x%02X", run_init_cal_detailed_status_resp.status); + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "cals_duration_msec = %d", run_init_cal_detailed_status_resp.cals_duration_msec); + + // SerDes init cal populates 2 index/channel data + for (i = 0; i < 2; ++i) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "init_err_codes[%d] = 0x%02X \t init_err_cals[%d] = 0x%02X", + i, run_init_cal_detailed_status_resp.init_err_codes[i], i, run_init_cal_detailed_status_resp.init_err_cals[i]); + // adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "cals_since_power_ups[%d] = %d \t cals_last_runs[%d] = %d", + // i, run_init_cal_detailed_status_resp.cals_since_power_up[i], i, run_init_cal_detailed_status_resp.cals_last_run[i]); + } + } + + if (cal_complete) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_API, "SerDes JRx Init cal completed %s in %ds\n", + run_init_get_completion.success ? "successfully" : "w/ ERROR", delay_us / 1000000); + err = run_init_get_completion.success ? API_CMS_ERROR_OK : API_CMS_ERROR_SERDES_CAL_ERROR; + goto end; + } else { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "SerDes JRx Init cal timeout after %ds\n", max_delay_us / 1000000); + err = API_CMS_ERROR_SERDES_CAL_TIMEOUT; + goto end; + } + +end: + return err; +} + +int32_t adi_apollo_serdes_jrx_bgcal_freeze(adi_apollo_device_t* device, uint16_t serdes) +{ + int32_t err = API_CMS_ERROR_OK; + adi_apollo_mailbox_cmd_set_enabled_tracking_cals_t track_cal_cmd = {0}; + adi_apollo_mailbox_resp_set_enabled_tracking_cals_t track_cal_resp = {0}; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(serdes > ADI_APOLLO_TXRX_SERDES_12PACK_ALL); + + /* Init the mailbox command struct */ + track_cal_cmd.serdes_rx_pack_mask = serdes; + track_cal_cmd.enable_disable = 0; + track_cal_cmd.adc_rx_channel_mask = 0; + track_cal_cmd.mcs_tc_mask = 0; + + /* + * Freeze the background cals + */ + adi_apollo_hal_log_write(device, ADI_CMS_LOG_API, "Freezing SERDES JRx background tracking cals\n"); + + + if (err = adi_apollo_mailbox_set_enabled_tracking_cals(device, &track_cal_cmd, &track_cal_resp), err != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Error from adi_apollo_mailbox_set_enabled_tracking_cals() (freeze) %d\n", err); + goto end; + } + + if (track_cal_resp.status != APOLLO_CPU_NO_ERROR) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "SerDes JRx BG cal error code = 0x%x\n", track_cal_resp.status); + err = API_CMS_ERROR_SERDES_CAL_ERROR; + goto end; + } + +end: + return err; +} + +int32_t adi_apollo_serdes_jrx_bgcal_unfreeze(adi_apollo_device_t* device, uint16_t serdes) +{ + int32_t err = API_CMS_ERROR_OK; + adi_apollo_mailbox_cmd_set_enabled_tracking_cals_t track_cal_cmd = {0}; + adi_apollo_mailbox_resp_set_enabled_tracking_cals_t track_cal_resp = {0}; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(serdes > ADI_APOLLO_TXRX_SERDES_12PACK_ALL); + + /* Init the mailbox command struct */ + track_cal_cmd.serdes_rx_pack_mask = serdes; + track_cal_cmd.enable_disable = 1; + track_cal_cmd.adc_rx_channel_mask = 0; + track_cal_cmd.mcs_tc_mask = 0; + + /* + * Unfreeze the background cals + */ + adi_apollo_hal_log_write(device, ADI_CMS_LOG_API, "Unfreeze SERDES JRx background tracking cals\n"); + if (err = adi_apollo_mailbox_set_enabled_tracking_cals(device, &track_cal_cmd, &track_cal_resp), err != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Error from adi_apollo_mailbox_set_enabled_tracking_cals() (unfreeze) %d\n", err); + goto end; + } + + if (track_cal_resp.status != APOLLO_CPU_NO_ERROR) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "SerDes JRx BG cal error code = 0x%x\n", track_cal_resp.status); + err = API_CMS_ERROR_SERDES_CAL_ERROR; + goto end; + } + +end: + return err; +} + +int32_t adi_apollo_serdes_jrx_bgcal_state_get(adi_apollo_device_t *device, uint16_t serdes, adi_apollo_serdes_bgcal_state_t state[], uint32_t len) +{ + int32_t err = API_CMS_ERROR_OK; + uint8_t i; + uint16_t s = 0; + adi_apollo_mailbox_resp_get_tracking_cal_state_t track_cal_state_resp = {0}; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(serdes > ADI_APOLLO_TXRX_SERDES_12PACK_ALL); + ADI_APOLLO_NULL_POINTER_RETURN(state); + ADI_APOLLO_INVALID_PARAM_RETURN(len != ADI_APOLLO_NUM_SIDES); + + if (err = adi_apollo_mailbox_get_tracking_cal_state(device, &track_cal_state_resp), err != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Error from adi_apollo_mailbox_get_tracking_cal_state() %d", err); + goto end; + } + + if (track_cal_state_resp.status != APOLLO_CPU_NO_ERROR) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "SerDes JRx BG cal state error code = 0x%x\n", track_cal_state_resp.status); + err = API_CMS_ERROR_MAILBOX_RESP_STATUS; + goto end; + } + + for (i = 0; i < ADI_APOLLO_NUM_JRX_SERDES_12PACKS; i++) { + s = serdes & (ADI_APOLLO_TXRX_SERDES_12PACK_A << i); + if (s > 0) { + state[i].state_valid = 1; + state[i].bgcal_error = track_cal_state_resp.tracking_cal_state.serdes_rx_cal_error[i]; + state[i].bgcal_state = track_cal_state_resp.tracking_cal_state.serdes_rx_cal_state[i]; + } else { + state[i].state_valid = 0; + state[i].bgcal_error = track_cal_state_resp.tracking_cal_state.serdes_rx_cal_error[i]; + state[i].bgcal_state = track_cal_state_resp.tracking_cal_state.serdes_rx_cal_state[i]; + } + } + +end: + return err; +} + +int32_t adi_apollo_serdes_pll_config(adi_apollo_device_t *device, adi_apollo_serdes_pll_pgm_t *config) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(config); + + err = adi_apollo_hal_bf_set(device, BF_SDM_INT_INFO(SERDES_PLL), config->sdm_int); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_REF_CLK_DIVIDE_RATIO_INFO(SERDES_PLL), config->ref_clk_byte0); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_SERDES_PLL_ODIV_INFO(SERDES_PLL), config->serdes_pll_odiv); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_ROOT_CLKDIV_FUND_INFO(SERDES_PLL), config->root_clkdiv_fund); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_ROOT_CLKDIV_DIV2_INFO(SERDES_PLL), config->root_clkdiv_div2); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_VCO_SEL_INFO(SERDES_PLL), config->vco_sel); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_serdes_serializer_config(adi_apollo_device_t *device, const uint16_t sides, adi_apollo_serializer_pgm_t *config) +{ + int32_t err, i; + uint32_t serdes_tx_12pack_base_addr = 0; + uint32_t serdes_tx_dig_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(config); + + for (i = 0; i < ADI_APOLLO_NUM_SIDES; i++) { + if ((1 << i) & sides) { + serdes_tx_12pack_base_addr = calc_serdes_tx_12pack_base(i); + serdes_tx_dig_base_addr = calc_serdes_tx_dig_base(i); + + err = adi_apollo_hal_bf_set(device, BF_SER_CLK_DIV_INFO(serdes_tx_12pack_base_addr), config->tx_clock_div); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_PARDATAMODE_SER_RC_INFO(serdes_tx_dig_base_addr), config->tx_data_width); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_PD_SER_INFO(serdes_tx_dig_base_addr), config->pd_ser); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + + +int32_t adi_apollo_serdes_pll_power(adi_apollo_device_t *device, adi_apollo_serdes_pll_power_up_down_e pwr_up) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_hal_reg_set(device, REG_MISC_PD_ADDR(SERDES_PLL), pwr_up ? 0x00 : 0xff); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_reg_set(device, REG_LOGEN_CLKGEN_LOSYNC_PD_ADDR(SERDES_PLL), pwr_up ? 0x00 : 0xff); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + + +int32_t adi_apollo_serdes_pll_reset(adi_apollo_device_t *device, adi_apollo_serdes_pll_reset_e reset_type) +{ + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(reset_type > ADI_APOLLO_SERDES_PLL_RESET_NUM-1); + + // Call the specific reset in index in table + return reset_tbl[reset_type](device); +} + +int32_t adi_apollo_serdes_prbs_generator_enable(adi_apollo_device_t *device, + uint8_t lanes[], uint32_t lanes_len, + adi_apollo_serdes_prbs_generator_enable_t *config) +{ + int32_t err, i; + uint8_t lane; + uint32_t serdes_tx_dig_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(lanes); + ADI_APOLLO_NULL_POINTER_RETURN(config); + ADI_APOLLO_INVALID_PARAM_RETURN(lanes_len > ADI_APOLLO_JESD_MAX_LANES_PER_SIDE*2); + + for (i=0; i (ADI_APOLLO_JESD_MAX_LANES_PER_SIDE*2 - 1)); + + serdes_tx_dig_base_addr = calc_serdes_tx_dig_lane_base(lane); + + err = adi_apollo_hal_bf_set(device, BF_DATA_GEN_MODE_INFO(serdes_tx_dig_base_addr), config->mode); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_DATA_GEN_EN_INFO(serdes_tx_dig_base_addr), config->enable); + ADI_APOLLO_ERROR_RETURN(err); + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_serdes_jrx_spo_dir_set(adi_apollo_device_t *device, + uint8_t lanes[], uint32_t lanes_len, uint8_t dir) +{ + int32_t err, i; + uint8_t lane; + uint32_t serdes_rx_dig_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(lanes); + ADI_APOLLO_INVALID_PARAM_RETURN(lanes_len > ADI_APOLLO_JESD_MAX_LANES_PER_SIDE*2); + + for (i=0; i (ADI_APOLLO_JESD_MAX_LANES_PER_SIDE*2 - 1)); + + serdes_rx_dig_base_addr = calc_serdes_rx_dig_lane_base(lane); + + err = adi_apollo_hal_bf_set(device, BF_CK_SPO_UP_DN_INFO(serdes_rx_dig_base_addr), dir); + ADI_APOLLO_ERROR_RETURN(err); + } + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_serdes_jrx_set_flash_mask(adi_apollo_device_t *device, + uint8_t lanes[], uint32_t lanes_len, uint8_t flash_mask) +{ + int32_t err, i; + uint8_t lane; + uint32_t serdes_rx_dig_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(lanes); + ADI_APOLLO_INVALID_PARAM_RETURN(lanes_len > ADI_APOLLO_JESD_MAX_LANES_PER_SIDE*2); + + for (i=0; i (ADI_APOLLO_JESD_MAX_LANES_PER_SIDE*2 - 1)); + + serdes_rx_dig_base_addr = calc_serdes_rx_dig_lane_base(lane); + + err = adi_apollo_hal_bf_set(device, BF_EN_FLASH_MASK_DES_RC_INFO(serdes_rx_dig_base_addr), flash_mask); + ADI_APOLLO_ERROR_RETURN(err); + } + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_serdes_jrx_clock_strobe(adi_apollo_device_t *device, + uint8_t lanes[], uint32_t lanes_len, + adi_apollo_serdes_ck_spo_strobe_e spo_strobe) +{ + int32_t err, i; + uint8_t lane; + uint32_t serdes_rx_dig_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(lanes); + ADI_APOLLO_INVALID_PARAM_RETURN(lanes_len > ADI_APOLLO_JESD_MAX_LANES_PER_SIDE*2); + + for (i=0; i (ADI_APOLLO_JESD_MAX_LANES_PER_SIDE*2 - 1)); + + serdes_rx_dig_base_addr = calc_serdes_rx_dig_lane_base(lane); + + if(spo_strobe == ADI_APOLLO_SERDES_CK_SPO_ISTROBE) { + err = adi_apollo_hal_bf_set(device, BF_CK_SPO_ISTROBE_INFO(serdes_rx_dig_base_addr), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_CK_SPO_ISTROBE_INFO(serdes_rx_dig_base_addr), 0); + ADI_APOLLO_ERROR_RETURN(err); + } + else if(spo_strobe == ADI_APOLLO_SERDES_CK_SPO_QSTROBE) { + err = adi_apollo_hal_bf_set(device, BF_CK_SPO_QSTROBE_INFO(serdes_rx_dig_base_addr), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_CK_SPO_QSTROBE_INFO(serdes_rx_dig_base_addr), 0); + ADI_APOLLO_ERROR_RETURN(err); + } + else { + err = adi_apollo_hal_bf_set(device, BF_CK_SPO_ISTROBE_INFO(serdes_rx_dig_base_addr), 0); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_CK_SPO_QSTROBE_INFO(serdes_rx_dig_base_addr), 0); + ADI_APOLLO_ERROR_RETURN(err); + } + + } + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_serdes_jrx_prbs_clear_error(adi_apollo_device_t *device, + uint8_t lanes[], uint32_t lanes_len) +{ + int32_t err, i; + uint8_t lane; + uint32_t serdes_rx_dig_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(lanes); + ADI_APOLLO_INVALID_PARAM_RETURN(lanes_len > ADI_APOLLO_JESD_MAX_LANES_PER_SIDE*2); + + for (i=0; i (ADI_APOLLO_JESD_MAX_LANES_PER_SIDE*2 - 1)); + + serdes_rx_dig_base_addr = calc_serdes_rx_dig_lane_base(lane); + + /* clear the error count */ + err = adi_apollo_hal_bf_set(device, BF_PRBS_RCV_DATAREC_CLR_INFO(serdes_rx_dig_base_addr), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_PRBS_RCV_DATAREC_CLR_INFO(serdes_rx_dig_base_addr), 0); + ADI_APOLLO_ERROR_RETURN(err); + } + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_serdes_jrx_prbs_checker_enable(adi_apollo_device_t *device, + uint8_t lanes[], uint32_t lanes_len, + adi_apollo_serdes_prbs_checker_enable_t *config) +{ + int32_t err, i; + uint8_t lane; + uint32_t serdes_rx_dig_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(lanes); + ADI_APOLLO_NULL_POINTER_RETURN(config); + ADI_APOLLO_INVALID_PARAM_RETURN(lanes_len > ADI_APOLLO_JESD_MAX_LANES_PER_SIDE*2); + + for (i=0; i (ADI_APOLLO_JESD_MAX_LANES_PER_SIDE*2 - 1)); + + serdes_rx_dig_base_addr = calc_serdes_rx_dig_lane_base(lane); + + err = adi_apollo_hal_bf_set(device, BF_PRBS_RCV_DATAREC_MODE_INFO(serdes_rx_dig_base_addr), config->prbs_mode); + ADI_APOLLO_ERROR_RETURN(err); + + if (config->auto_mode == 0) { //Regular mode + err = adi_apollo_hal_bf_set(device, BF_PRBS_RCV_EN_INFO(serdes_rx_dig_base_addr), config->enable); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_PRBS_RCV_DATAREC_EN_INFO(serdes_rx_dig_base_addr), config->enable); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_PRBS_RCV_DATAREC_CLR_INFO(serdes_rx_dig_base_addr), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_PRBS_RCV_DATAREC_CLR_INFO(serdes_rx_dig_base_addr), 0); + ADI_APOLLO_ERROR_RETURN(err); + } + else { + err = adi_apollo_hal_bf_set(device, BF_PRBS_RCV_DATAREC_CLR_INFO(serdes_rx_dig_base_addr), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_PRBS_RCV_AUTO_MODE_THRESH_INFO(serdes_rx_dig_base_addr), config->auto_mode_thres); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_PRBS_RCV_AUTO_MODE_INFO(serdes_rx_dig_base_addr), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_PRBS_RCV_AUTO_MODE_INFO(serdes_rx_dig_base_addr), 0); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_serdes_jrx_prbs_checker_status(adi_apollo_device_t *device, + uint8_t lanes[], + adi_apollo_serdes_prbs_checker_status_t status[], + uint32_t lanes_len) +{ + int32_t err, i; + uint8_t lane; + uint32_t serdes_rx_dig_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(lanes); + ADI_APOLLO_NULL_POINTER_RETURN(status); + ADI_APOLLO_INVALID_PARAM_RETURN(lanes_len > ADI_APOLLO_JESD_MAX_LANES_PER_SIDE*2); + + for (i=0; i (ADI_APOLLO_JESD_MAX_LANES_PER_SIDE*2 - 1)); + + serdes_rx_dig_base_addr = calc_serdes_rx_dig_lane_base(lane); + + err = adi_apollo_hal_bf_get(device, BF_PRBS_RCV_ERR_INFO(serdes_rx_dig_base_addr), &(status[lane].err), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_PRBS_RCV_ERR_STICKY_INFO(serdes_rx_dig_base_addr), &(status[lane].err_sticky), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_PRBS_RCV_AUTO_MODE_DONE_INFO(serdes_rx_dig_base_addr), &(status[lane].auto_mode_done), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_PRBS_RCV_ERR_CNT_INFO(serdes_rx_dig_base_addr), (uint8_t *) &(status[lane].err_count), 4); + ADI_APOLLO_ERROR_RETURN(err); + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_serdes_jrx_horiz_eye_sweep(adi_apollo_device_t *device, + const uint16_t lane, + const uint8_t prbs_pattern) +{ + int32_t err = API_CMS_ERROR_ERROR; + adi_apollo_mailbox_cmd_run_serdes_eye_sweep_t horz_eye_cmd = {0}; + adi_apollo_mailbox_resp_run_serdes_eye_sweep_t resp = {0}; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(lane >= ADI_APOLLO_SERDES_LANE_LEN); + + horz_eye_cmd.lane = lane; + horz_eye_cmd.prbs_pattern = prbs_pattern; + horz_eye_cmd.force_using_outer = 0; + horz_eye_cmd.prbs_check_duration_ms = 10; + + err = adi_apollo_mailbox_run_serdes_eye_sweep(device, &horz_eye_cmd, &resp); + ADI_APOLLO_ERROR_RETURN(err); + + if (resp.status != APOLLO_CPU_NO_ERROR) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Horizontal Eye Sweep Mailbox Response Status Error code = %d\n", resp.status); + return API_CMS_ERROR_MAILBOX_RESP_STATUS; + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_serdes_jrx_horiz_eye_sweep_resp_get(adi_apollo_device_t *device, + const uint16_t lane, + adi_apollo_serdes_jrx_horiz_eye_resp_t *resp) +{ + int32_t err = API_CMS_ERROR_ERROR; + adi_apollo_mailbox_cmd_set_ctrl_t set_ctrl_cmd = { + .sys_cal_object_id = APOLLO_CPU_OBJID_IC_SERDES_RX, + .ctrl_cmd = CTRL_CMD_PARAM_GET, + .data_buffer[0] = ADI_APOLLO_SERDES_RX_TEST_HORIZ_EYE_RESULTS, + .data_buffer[1] = 0, + .data_buffer[2] = 0, + .data_buffer[3] = 0, + .length = 4 + }; + adi_apollo_mailbox_resp_set_ctrl_t set_ctrl_resp; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(lane >= ADI_APOLLO_SERDES_LANE_LEN); + + /* + set_ctrl_cmd is generic cmd and for SERDES Rx/Tx related cmds, + requires the channel_num to be set to 0 for side A and 1 for side B + */ + set_ctrl_cmd.channel_num = ((lane / ADI_APOLLO_SERDES_RX_LANES_MAX_PER_SIDE) == 0) ? APOLLO_SERDES_PACK_NUM_PACK_0_EAST : APOLLO_SERDES_PACK_NUM_PACK_1_WEST; + + err = adi_apollo_mailbox_set_ctrl(device, &set_ctrl_cmd, &set_ctrl_resp); + ADI_APOLLO_ERROR_RETURN(err); + + if (set_ctrl_resp.status != API_CMS_ERROR_OK){ + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Mailbox Response Status Error from adi_apollo_mailbox_set_ctrl() 0x%X", set_ctrl_resp.status); + return API_CMS_ERROR_MAILBOX_RESP_STATUS; + } + + resp->ver = set_ctrl_resp.data_buffer[4]; + resp->spo_left = set_ctrl_resp.data_buffer[5]; + resp->spo_right = set_ctrl_resp.data_buffer[6]; + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_serdes_jrx_vert_eye_sweep(adi_apollo_device_t *device, + const uint16_t lane) +{ + int32_t err = API_CMS_ERROR_ERROR; + adi_apollo_mailbox_cmd_run_serdes_vert_eye_sweep_t vert_eye_cmd = {0}; + adi_apollo_mailbox_resp_run_serdes_vert_eye_sweep_t resp = {0}; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(lane >= ADI_APOLLO_SERDES_LANE_LEN); + + vert_eye_cmd.lane = lane; + + err = adi_apollo_mailbox_run_serdes_vert_eye_sweep(device, &vert_eye_cmd, &resp); + ADI_APOLLO_ERROR_RETURN(err); + + if (resp.status != APOLLO_CPU_NO_ERROR) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Vertical Eye Sweep Mailbox Response Status Error code = %d\n", resp.status); + return API_CMS_ERROR_MAILBOX_RESP_STATUS; + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_serdes_jrx_vert_eye_sweep_resp_get(adi_apollo_device_t *device, + const uint16_t lane, + adi_apollo_serdes_jrx_vert_eye_resp_t *resp) +{ + int32_t err = API_CMS_ERROR_ERROR; + adi_apollo_mailbox_cmd_set_ctrl_t set_ctrl_cmd = { + .sys_cal_object_id = APOLLO_CPU_OBJID_IC_SERDES_RX, + .ctrl_cmd = CTRL_CMD_PARAM_GET, + .data_buffer[0] = ADI_APOLLO_SERDES_RX_TEST_VERT_EYE_RESULTS, + .data_buffer[1] = 0, + .data_buffer[2] = 0, + .data_buffer[3] = 0, + .length = 4 + }; + adi_apollo_mailbox_resp_set_ctrl_t set_ctrl_resp; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(lane >= ADI_APOLLO_SERDES_LANE_LEN); + + /* + set_ctrl_cmd is generic cmd and for SERDES Rx/Tx related cmds, + requires the channel_num to be set to 0 for side A and 1 for side B + */ + set_ctrl_cmd.channel_num = ((lane / ADI_APOLLO_SERDES_RX_LANES_MAX_PER_SIDE) == 0) ? APOLLO_SERDES_PACK_NUM_PACK_0_EAST : APOLLO_SERDES_PACK_NUM_PACK_1_WEST; + + err = adi_apollo_mailbox_set_ctrl(device, &set_ctrl_cmd, &set_ctrl_resp); + ADI_APOLLO_ERROR_RETURN(err); + + if (set_ctrl_resp.status != API_CMS_ERROR_OK){ + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "Mailbox Response Status Error from adi_apollo_mailbox_set_ctrl() 0x%X", set_ctrl_resp.status); + return API_CMS_ERROR_MAILBOX_RESP_STATUS; + } + + resp->ver = set_ctrl_resp.data_buffer[4]; + memcpy(resp->eye_heights_at_spo, set_ctrl_resp.data_buffer + 5, ADI_APOLLO_SERDES_JRX_VERT_EYE_TEST_RESP_BUF_SIZE * sizeof(int8_t)); + + return API_CMS_ERROR_OK; +} + +static int32_t reset_synth(adi_apollo_device_t *device) +{ + int err; + + // Assert reset + err = adi_apollo_hal_reg_set(device, REG_SYNTH_RESETB_ADDR(SERDES_PLL), 0x00); + ADI_APOLLO_ERROR_RETURN(err); + + // Lift reset + err = adi_apollo_hal_reg_set(device, REG_SYNTH_RESETB_ADDR(SERDES_PLL), 0xff); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +static int32_t reset_odiv(adi_apollo_device_t *device) +{ + int err; + + // Assert reset + err = adi_apollo_hal_bf_set(device, BF_SERDES_PLL_ODIV_RB_INFO(SERDES_PLL), 0x00); + ADI_APOLLO_ERROR_RETURN(err); + + // Lift reset + err = adi_apollo_hal_bf_set(device, BF_SERDES_PLL_ODIV_RB_INFO(SERDES_PLL), 0x01); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_serdes_pll_locked_status(adi_apollo_device_t *device, + adi_apollo_sides_e side, + uint16_t lane_mask, + uint16_t *status) +{ + int32_t err, i; + uint32_t serdes_rx_dig_base_addr = 0; + uint8_t lane; + uint8_t pll_locked = 0; + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(status); + ADI_APOLLO_INVALID_PARAM_RETURN(side >= ADI_APOLLO_NUM_SIDES); + ADI_APOLLO_INVALID_PARAM_RETURN(lane_mask > 0xFFF); + + /* clear the status */ + *status = 0; + + for(i = 0; i < ADI_APOLLO_JESD_MAX_LANES_PER_SIDE; i++) { + if ((1 << i) & lane_mask) { + lane = i + (side * ADI_APOLLO_JESD_MAX_LANES_PER_SIDE); + serdes_rx_dig_base_addr = calc_serdes_rx_dig_lane_base(lane); + + err = adi_apollo_hal_bf_get(device, BF_RFPLL_LOCKED_INFO(serdes_rx_dig_base_addr), (uint8_t *) &pll_locked, 1); + ADI_APOLLO_ERROR_RETURN(err); + + if(pll_locked) { + *status |= (1 << i); + } + } + } + return API_CMS_ERROR_OK; +} + +static uint32_t calc_serdes_tx_12pack_base(int32_t index) +{ + static uint32_t tx_12pack_regmap[] = { + SER_PHY_TOP_12PACK_SERDES_TX_JTX_TOP_RX_DIGITAL0, SER_PHY_TOP_12PACK_SERDES_TX_JTX_TOP_RX_DIGITAL1 + }; + + return (tx_12pack_regmap[index]); +} + +static uint32_t calc_serdes_tx_dig_base(int32_t index) +{ + static uint32_t serdes_tx_dig_regmap[] = { + SER_PHY_ALL_SERDES_TX_JTX_TOP_RX_DIGITAL0, SER_PHY_ALL_SERDES_TX_JTX_TOP_RX_DIGITAL1 + }; + + return (serdes_tx_dig_regmap[index]); +} + +static uint32_t calc_serdes_rx_dig_lane_base(int32_t index) +{ + static uint32_t serdes_rx_dig_lane_regmap[] = { + DESER_PHY0_SERDES_RX_JRX_TX_DIGITAL0, DESER_PHY1_SERDES_RX_JRX_TX_DIGITAL0, + DESER_PHY2_SERDES_RX_JRX_TX_DIGITAL0, DESER_PHY3_SERDES_RX_JRX_TX_DIGITAL0, + DESER_PHY4_SERDES_RX_JRX_TX_DIGITAL0, DESER_PHY5_SERDES_RX_JRX_TX_DIGITAL0, + DESER_PHY6_SERDES_RX_JRX_TX_DIGITAL0, DESER_PHY7_SERDES_RX_JRX_TX_DIGITAL0, + DESER_PHY8_SERDES_RX_JRX_TX_DIGITAL0, DESER_PHY9_SERDES_RX_JRX_TX_DIGITAL0, + DESER_PHY10_SERDES_RX_JRX_TX_DIGITAL0, DESER_PHY11_SERDES_RX_JRX_TX_DIGITAL0, + DESER_PHY0_SERDES_RX_JRX_TX_DIGITAL1, DESER_PHY1_SERDES_RX_JRX_TX_DIGITAL1, + DESER_PHY2_SERDES_RX_JRX_TX_DIGITAL1, DESER_PHY3_SERDES_RX_JRX_TX_DIGITAL1, + DESER_PHY4_SERDES_RX_JRX_TX_DIGITAL1, DESER_PHY5_SERDES_RX_JRX_TX_DIGITAL1, + DESER_PHY6_SERDES_RX_JRX_TX_DIGITAL1, DESER_PHY7_SERDES_RX_JRX_TX_DIGITAL1, + DESER_PHY8_SERDES_RX_JRX_TX_DIGITAL1, DESER_PHY9_SERDES_RX_JRX_TX_DIGITAL1, + DESER_PHY10_SERDES_RX_JRX_TX_DIGITAL1, DESER_PHY11_SERDES_RX_JRX_TX_DIGITAL1 + }; + + return (serdes_rx_dig_lane_regmap[index]); +} + +static uint32_t calc_serdes_tx_dig_lane_base(int32_t index) +{ + static uint32_t serdes_tx_dig_lane_regmap[] = { + SER_PHY0_SERDES_TX_JTX_TOP_RX_DIGITAL0, SER_PHY1_SERDES_TX_JTX_TOP_RX_DIGITAL0, + SER_PHY2_SERDES_TX_JTX_TOP_RX_DIGITAL0, SER_PHY3_SERDES_TX_JTX_TOP_RX_DIGITAL0, + SER_PHY4_SERDES_TX_JTX_TOP_RX_DIGITAL0, SER_PHY5_SERDES_TX_JTX_TOP_RX_DIGITAL0, + SER_PHY6_SERDES_TX_JTX_TOP_RX_DIGITAL0, SER_PHY7_SERDES_TX_JTX_TOP_RX_DIGITAL0, + SER_PHY8_SERDES_TX_JTX_TOP_RX_DIGITAL0, SER_PHY9_SERDES_TX_JTX_TOP_RX_DIGITAL0, + SER_PHY10_SERDES_TX_JTX_TOP_RX_DIGITAL0, SER_PHY11_SERDES_TX_JTX_TOP_RX_DIGITAL0, + SER_PHY0_SERDES_TX_JTX_TOP_RX_DIGITAL1, SER_PHY1_SERDES_TX_JTX_TOP_RX_DIGITAL1, + SER_PHY2_SERDES_TX_JTX_TOP_RX_DIGITAL1, SER_PHY3_SERDES_TX_JTX_TOP_RX_DIGITAL1, + SER_PHY4_SERDES_TX_JTX_TOP_RX_DIGITAL1, SER_PHY5_SERDES_TX_JTX_TOP_RX_DIGITAL1, + SER_PHY6_SERDES_TX_JTX_TOP_RX_DIGITAL1, SER_PHY7_SERDES_TX_JTX_TOP_RX_DIGITAL1, + SER_PHY8_SERDES_TX_JTX_TOP_RX_DIGITAL1, SER_PHY9_SERDES_TX_JTX_TOP_RX_DIGITAL1, + SER_PHY10_SERDES_TX_JTX_TOP_RX_DIGITAL1, SER_PHY11_SERDES_TX_JTX_TOP_RX_DIGITAL1 + }; + + return (serdes_tx_dig_lane_regmap[index]); +} +/*! @} */ \ No newline at end of file diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_smon.c b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_smon.c new file mode 100644 index 00000000000000..48e67c3547ebb1 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_smon.c @@ -0,0 +1,589 @@ + +/*! + * \brief APIs for SMON + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_SMON + * @{ + */ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_smon.h" +#include "adi_apollo_smon_local.h" +#include "adi_apollo_dformat_local.h" +#include "adi_apollo_trigts_local.h" +#include "adi_apollo_private_blk_sel_types.h" + +#include "adi_apollo_bf_rx_smon.h" +#include "adi_apollo_bf_jtx_dformat.h" + +#include "adi_apollo_config.h" +#include "adi_apollo_hal.h" + +#include "adi_utils.h" + +#define FRAMER_5_SUB_FRAME_NUM_BITS 5 +#define FRAMER_5_SUB_FRAME_ID_NUM_BITS (1 * FRAMER_5_SUB_FRAME_NUM_BITS) +#define FRAMER_5_SUB_FRAME_DATA_NUM_BITS (4 * FRAMER_5_SUB_FRAME_NUM_BITS) +#define FRAMER_5_SUB_FRAME_IDLE_NUM_BITS (1 * FRAMER_5_SUB_FRAME_NUM_BITS) +#define FRAMER_5_MIN_SAMPLES (FRAMER_5_SUB_FRAME_ID_NUM_BITS + FRAMER_5_SUB_FRAME_DATA_NUM_BITS + FRAMER_5_SUB_FRAME_IDLE_NUM_BITS) + +#define FRAMER_10_SUB_FRAME_NUM_BITS 10 +#define FRAMER_10_SUB_FRAME_ID_NUM_BITS (1 * FRAMER_10_SUB_FRAME_NUM_BITS) +#define FRAMER_10_SUB_FRAME_DATA_NUM_BITS (2 * FRAMER_10_SUB_FRAME_NUM_BITS) +#define FRAMER_10_SUB_FRAME_IDLE_NUM_BITS (1 * FRAMER_10_SUB_FRAME_NUM_BITS) +#define FRAMER_10_MIN_SAMPLES (FRAMER_10_SUB_FRAME_ID_NUM_BITS + FRAMER_10_SUB_FRAME_DATA_NUM_BITS + FRAMER_10_SUB_FRAME_IDLE_NUM_BITS) + +typedef int32_t (*framer_sof_get_t)(int16_t *samples, uint32_t num_samples, uint32_t ofst, uint16_t smon_ctrl_bit_mask, uint32_t *sof_idx); +typedef int32_t (*framer_peak_val_get_t)(int16_t *samples, uint32_t num_samples, uint32_t sof_idx, uint16_t smon_ctrl_bit_mask, uint16_t *peak_val); + +static int32_t sof_framer5_get(int16_t *samples, uint32_t num_samples, uint32_t ofst, uint16_t smon_ctrl_bit_mask, uint32_t *sof_idx); +static int32_t peak_val_framer5_get(int16_t *samples, uint32_t num_samples, uint32_t sof_idx, uint16_t smon_ctrl_bit_mask, uint16_t *peak_val); + +static int32_t sof_framer10_get(int16_t *samples, uint32_t num_samples, uint32_t ofst, uint16_t smon_ctrl_bit_mask, uint32_t *sof_idx); +static int32_t peak_val_framer10_get(int16_t *samples, uint32_t num_samples, uint32_t sof_idx, uint16_t smon_ctrl_bit_mask, uint16_t *peak_val); + +/*==================== P U B L I C A P I C O D E ====================*/ + +int32_t adi_apollo_smon_pgm(adi_apollo_device_t *device, adi_apollo_blk_sel_t smons, adi_apollo_smon_pgm_t *config) +{ + int32_t err; + uint8_t i; + adi_apollo_blk_sel_t smon; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(config); + ADI_APOLLO_SMON_BLK_SEL_MASK(smons); + + for (i = 0; i < ADI_APOLLO_SMON_NUM; i++) { + smon = smons & (ADI_APOLLO_SMON_A0 << i); + if (smon > 0) { + regmap_base_addr = calc_smon_base(i); + + err = adi_apollo_hal_bf_set(device, BF_SMON_SFRAMER_MODE_EN_INFO(regmap_base_addr), config->sframer_mode_en); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_SMON_PERIOD_INFO(regmap_base_addr), config->smon_period); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_SMON_THRESH_LOW_INFO(regmap_base_addr), config->thresh_low); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_SMON_THRESH_HIGH_INFO(regmap_base_addr), config->thresh_high); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_SMON_SYNC_EN_INFO(regmap_base_addr), config->sync_en); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_SMON_SYNC_NEXT_INFO(regmap_base_addr), config->sync_next); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_SMON_SFRAMER_EN_INFO(regmap_base_addr), config->sframer_en); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_SMON_SFRAMER_MODE_INFO(regmap_base_addr), config->sframer_mode); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_SMON_SFRAMER_INSEL_INFO(regmap_base_addr), config->sframer_insel); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_SMON_PEAK_EN_INFO(regmap_base_addr), config->peak_en); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_SMON_STATUS_RDSEL_INFO(regmap_base_addr), config->status_rdsel); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_SMON_JLINK_SEL_INFO(regmap_base_addr), config->jlink_sel); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_SMON_GPIO_EN_INFO(regmap_base_addr), config->gpio_en); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_smon_dfor_pgm(adi_apollo_device_t *device, adi_apollo_blk_sel_t links, adi_apollo_blk_sel_t fddcs, adi_apollo_smon_dfor_pgm_t *config) +{ + int32_t err, i; + adi_apollo_blk_sel_t fddc; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(config); + ADI_APOLLO_FDDC_BLK_SEL_MASK(fddcs); + + for (i = 0; i < ADI_APOLLO_NUM_JTX_LINKS; i++) { + if ((1 << i) & links) { + regmap_base_addr = calc_jtx_dformat_base(i); + + if ((i % ADI_APOLLO_NUM_JTX_LINKS_PER_SIDE) == 0) { /* LINK 0 (A0/B0) */ + err = adi_apollo_hal_bf_set(device, BF_DFORMAT_CTRL_BIT_0_SEL_0_INFO(regmap_base_addr), config->ctrl_bit_0); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_DFORMAT_CTRL_BIT_1_SEL_0_INFO(regmap_base_addr), config->ctrl_bit_1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_DFORMAT_CTRL_BIT_2_SEL_0_INFO(regmap_base_addr), config->ctrl_bit_2); + ADI_APOLLO_ERROR_RETURN(err); + } else { /* LINK 1 (A1/B1) */ + err = adi_apollo_hal_bf_set(device, BF_DFORMAT_CTRL_BIT_0_SEL_1_INFO(regmap_base_addr), config->ctrl_bit_0); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_DFORMAT_CTRL_BIT_1_SEL_1_INFO(regmap_base_addr), config->ctrl_bit_1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_DFORMAT_CTRL_BIT_2_SEL_1_INFO(regmap_base_addr), config->ctrl_bit_2); + ADI_APOLLO_ERROR_RETURN(err); + } + } + } + + /* Select SMON status bits for the fine DDCs */ + for (i = 0; i < ADI_APOLLO_FDDC_NUM; i++) { + fddc = fddcs & (ADI_APOLLO_FDDC_A0 << i); + if (fddc > 0) { + regmap_base_addr = calc_jtx_dformat_base((i / ADI_APOLLO_FDDC_PER_SIDE_NUM) * ADI_APOLLO_NUM_JTX_LINKS_PER_SIDE); + + switch (i % ADI_APOLLO_FDDC_PER_SIDE_NUM) { + case 0: + err = adi_apollo_hal_bf_set(device, BF_FINE0_ADC_I_SEL_INFO(regmap_base_addr), config->fine_adc_i_sel[i]); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_FINE0_ADC_Q_SEL_INFO(regmap_base_addr), config->fine_adc_q_sel[i]); + ADI_APOLLO_ERROR_RETURN(err); + break; + case 1: + err = adi_apollo_hal_bf_set(device, BF_FINE1_ADC_I_SEL_INFO(regmap_base_addr), config->fine_adc_i_sel[i]); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_FINE1_ADC_Q_SEL_INFO(regmap_base_addr), config->fine_adc_q_sel[i]); + ADI_APOLLO_ERROR_RETURN(err); + break; + case 2: + err = adi_apollo_hal_bf_set(device, BF_FINE2_ADC_I_SEL_INFO(regmap_base_addr), config->fine_adc_i_sel[i]); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_FINE2_ADC_Q_SEL_INFO(regmap_base_addr), config->fine_adc_q_sel[i]); + ADI_APOLLO_ERROR_RETURN(err); + break; + case 3: + err = adi_apollo_hal_bf_set(device, BF_FINE3_ADC_I_SEL_INFO(regmap_base_addr), config->fine_adc_i_sel[i]); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_FINE3_ADC_Q_SEL_INFO(regmap_base_addr), config->fine_adc_q_sel[i]); + ADI_APOLLO_ERROR_RETURN(err); + break; + + /* FINE4-FINE7 is 8T8R only */ + case 4: + err = adi_apollo_hal_bf_set(device, BF_FINE4_ADC_I_SEL_INFO(regmap_base_addr), config->fine_adc_i_sel[i]); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_FINE4_ADC_Q_SEL_INFO(regmap_base_addr), config->fine_adc_q_sel[i]); + ADI_APOLLO_ERROR_RETURN(err); + break; + case 5: + err = adi_apollo_hal_bf_set(device, BF_FINE5_ADC_I_SEL_INFO(regmap_base_addr), config->fine_adc_i_sel[i]); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_FINE5_ADC_Q_SEL_INFO(regmap_base_addr), config->fine_adc_q_sel[i]); + ADI_APOLLO_ERROR_RETURN(err); + break; + case 6: + err = adi_apollo_hal_bf_set(device, BF_FINE6_ADC_I_SEL_INFO(regmap_base_addr), config->fine_adc_i_sel[i]); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_FINE6_ADC_Q_SEL_INFO(regmap_base_addr), config->fine_adc_q_sel[i]); + ADI_APOLLO_ERROR_RETURN(err); + break; + case 7: + err = adi_apollo_hal_bf_set(device, BF_FINE7_ADC_I_SEL_INFO(regmap_base_addr), config->fine_adc_i_sel[i]); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_FINE7_ADC_Q_SEL_INFO(regmap_base_addr), config->fine_adc_q_sel[i]); + ADI_APOLLO_ERROR_RETURN(err); + break; + } + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_smon_status_update(adi_apollo_device_t *device, adi_apollo_blk_sel_t smons, uint8_t update) +{ + int32_t err; + uint8_t i; + adi_apollo_blk_sel_t smon; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_SMON_BLK_SEL_MASK(smons); + + for (i = 0; i < ADI_APOLLO_SMON_NUM; i++) { + smon = smons & (ADI_APOLLO_SMON_A0 << i); + if (smon > 0) { + regmap_base_addr = calc_smon_base(i); + + err = adi_apollo_hal_bf_set(device, BF_SMON_STATUS_UPDATE_INFO(regmap_base_addr), update); //Toggle bit + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_smon_read(adi_apollo_device_t *device, adi_apollo_blk_sel_t smons, adi_apollo_smon_read_t *data) +{ + int32_t err; + uint8_t i, j, reg8; + adi_apollo_blk_sel_t smon; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(data); + ADI_CMS_SINGLE_SELECT_CHECK(smons); + ADI_APOLLO_SMON_BLK_SEL_MASK(smons); + + for (i = 0; i < ADI_APOLLO_SMON_NUM; i++) { + smon = smons & (ADI_APOLLO_SMON_A0 << i); + if (smon > 0) { + regmap_base_addr = calc_smon_base(i); + + err = adi_apollo_hal_bf_get(device, BF_SMON_STATUS_FCNT_INFO(regmap_base_addr), &data->status_fcnt, 1); + ADI_APOLLO_ERROR_RETURN(err); + + data->status = 0; + for (j = 0; j < ADI_APOLLO_SMON_STATUS_SIZE; j++) { + err = adi_apollo_hal_bf_get(device, BF_SMON_STATUS_INFO(regmap_base_addr, j), ®8, 1); + ADI_APOLLO_ERROR_RETURN(err); + data->status |= reg8 << (j*8); + } + } + } + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_smon_peak_val_get(adi_apollo_device_t *device, adi_apollo_blk_sel_t smons, uint16_t *pk_val) +{ + int32_t err; + uint8_t i; + uint8_t j; + uint8_t reg8; + adi_apollo_blk_sel_t smon; + uint32_t status; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(pk_val); + ADI_CMS_SINGLE_SELECT_CHECK(smons); + ADI_APOLLO_SMON_BLK_SEL_MASK(smons); + + for (i = 0; i < ADI_APOLLO_SMON_NUM; i++) { + smon = smons & (ADI_APOLLO_SMON_A0 << i); + if (smon > 0) { + regmap_base_addr = calc_smon_base(i); + + // Toggle for pk val update + err = adi_apollo_hal_bf_set(device, BF_SMON_STATUS_UPDATE_INFO(regmap_base_addr), 0); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_SMON_STATUS_UPDATE_INFO(regmap_base_addr), 1); + ADI_APOLLO_ERROR_RETURN(err); + + status = 0; + for (j = 0; j < ADI_APOLLO_SMON_STATUS_SIZE; j++) { + err = adi_apollo_hal_bf_get(device, BF_SMON_STATUS_INFO(regmap_base_addr, j), ®8, 1); + ADI_APOLLO_ERROR_RETURN(err); + status |= reg8 << (j * 8); + } + + *pk_val = (uint16_t)((status & 0x000ffe00) >> 9); + + /* Only one get result per call */ + break; + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_smon_thresh_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t smons, uint16_t thresh_low, uint16_t thresh_high) +{ + int32_t err; + uint8_t i; + adi_apollo_blk_sel_t smon; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(thresh_low > ADI_APOLLO_SMON_MAX_THRESH_VAL); + ADI_APOLLO_INVALID_PARAM_RETURN(thresh_high > ADI_APOLLO_SMON_MAX_THRESH_VAL); + ADI_APOLLO_INVALID_PARAM_RETURN(thresh_low > thresh_high); + ADI_APOLLO_SMON_BLK_SEL_MASK(smons); + + for (i = 0; i < ADI_APOLLO_SMON_NUM; i++) { + smon = smons & (ADI_APOLLO_SMON_A0 << i); + if (smon > 0) { + regmap_base_addr = calc_smon_base(i); + + err = adi_apollo_hal_bf_set(device, BF_SMON_THRESH_LOW_INFO(regmap_base_addr), thresh_low); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_SMON_THRESH_HIGH_INFO(regmap_base_addr), thresh_high); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_smon_thresh_get(adi_apollo_device_t *device, adi_apollo_blk_sel_t smons, uint16_t *thresh_low, uint16_t *thresh_high) +{ + int32_t err; + uint8_t i; + adi_apollo_blk_sel_t smon; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(thresh_low); + ADI_APOLLO_NULL_POINTER_RETURN(thresh_high); + ADI_CMS_SINGLE_SELECT_CHECK(smons); + ADI_APOLLO_SMON_BLK_SEL_MASK(smons); + + for (i = 0; i < ADI_APOLLO_SMON_NUM; i++) { + smon = smons & (ADI_APOLLO_SMON_A0 << i); + if (smon > 0) { + regmap_base_addr = calc_smon_base(i); + + err = adi_apollo_hal_bf_get(device, BF_SMON_THRESH_LOW_INFO(regmap_base_addr), (uint8_t *) thresh_low, sizeof(*thresh_low)); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_SMON_THRESH_HIGH_INFO(regmap_base_addr), (uint8_t *) thresh_high, sizeof(*thresh_high)); + ADI_APOLLO_ERROR_RETURN(err); + + /* Only one get result per call */ + break; + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_smon_inspect(adi_apollo_device_t *device, adi_apollo_blk_sel_t smons, adi_apollo_smon_inspect_t *smon_inspect) +{ + int32_t err; + uint16_t i; + adi_apollo_blk_sel_t smon; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(smon_inspect); + ADI_CMS_SINGLE_SELECT_CHECK(smons); + ADI_APOLLO_SMON_BLK_SEL_MASK(smons); + + for (i = 0; i < ADI_APOLLO_SMON_NUM; i++) { + smon = smons & (ADI_APOLLO_SMON_A0 << i); + if (smon > 0) { + regmap_base_addr = calc_smon_base(i); + + err = adi_apollo_hal_bf_get(device, BF_SMON_PERIOD_INFO(regmap_base_addr), (uint8_t *) &(smon_inspect->dp_cfg.period), sizeof(smon_inspect->dp_cfg.period)); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_SMON_GPIO_EN_INFO(regmap_base_addr), (uint8_t *) &(smon_inspect->dp_cfg.gpio_en), sizeof(smon_inspect->dp_cfg.gpio_en)); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_SMON_PEAK_EN_INFO(regmap_base_addr), (uint8_t *)&(smon_inspect->dp_cfg.peak_en), sizeof(smon_inspect->dp_cfg.peak_en)); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_SMON_JLINK_SEL_INFO(regmap_base_addr), (uint8_t *)&(smon_inspect->dp_cfg.jlink_sel), sizeof(smon_inspect->dp_cfg.jlink_sel)); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_SMON_SFRAMER_EN_INFO(regmap_base_addr), (uint8_t *)&(smon_inspect->dp_cfg.sframer_en), sizeof(smon_inspect->dp_cfg.sframer_en)); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_SMON_SFRAMER_MODE_INFO(regmap_base_addr), (uint8_t *)&(smon_inspect->dp_cfg.sframer_mode), sizeof(smon_inspect->dp_cfg.sframer_mode)); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_SMON_SYNC_EN_INFO(regmap_base_addr), (uint8_t *)&(smon_inspect->dp_cfg.sync_en), sizeof(smon_inspect->dp_cfg.sync_en)); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_SMON_SYNC_NEXT_INFO(regmap_base_addr), (uint8_t *)&(smon_inspect->dp_cfg.sync_next), sizeof(smon_inspect->dp_cfg.sync_next)); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_SMON_THRESH_HIGH_INFO(regmap_base_addr), (uint8_t *)&(smon_inspect->dp_cfg.thresh_high), sizeof(smon_inspect->dp_cfg.thresh_high)); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_SMON_THRESH_LOW_INFO(regmap_base_addr), (uint8_t *)&(smon_inspect->dp_cfg.thresh_low), sizeof(smon_inspect->dp_cfg.thresh_low)); + ADI_APOLLO_ERROR_RETURN(err); + + /* Only one inspect per call */ + break; + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_smon_peak_val_from_cap_get(adi_apollo_device_t *device, adi_apollo_blk_sel_t smons, + int16_t cap_array[], uint32_t cap_len, uint32_t offset, + uint16_t smon_ctrl_bit_mask, + uint32_t *sof_idx, uint16_t *pk_val) +{ + int32_t err; + uint16_t i; + adi_apollo_blk_sel_t smon; + framer_sof_get_t sof_get; + framer_peak_val_get_t pk_val_get; + uint32_t regmap_base_addr = 0; + uint8_t framer_mode; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(cap_array); + ADI_APOLLO_NULL_POINTER_RETURN(sof_idx); + ADI_APOLLO_NULL_POINTER_RETURN(pk_val); + ADI_CMS_SINGLE_SELECT_CHECK(smons); + ADI_APOLLO_SMON_BLK_SEL_MASK(smons); + + for (i = 0; i < ADI_APOLLO_SMON_NUM; i++) { + smon = smons & (ADI_APOLLO_SMON_A0 << i); + + if (smon > 0) { + regmap_base_addr = calc_smon_base(i); + + err = adi_apollo_hal_bf_get(device, BF_SMON_SFRAMER_MODE_INFO(regmap_base_addr), &framer_mode, sizeof(framer_mode)); + ADI_APOLLO_ERROR_RETURN(err); + + // Assign the 5-bit or 10-bit framer de-serialization methods + sof_get = (framer_mode == ADI_APOLLO_SMON_SFRAMER_TEN_BIT) ? sof_framer10_get : sof_framer5_get; + pk_val_get = (framer_mode == ADI_APOLLO_SMON_SFRAMER_TEN_BIT) ? peak_val_framer10_get : peak_val_framer5_get; + + /* Find the start of frame */ + err = sof_get(cap_array, cap_len, offset, smon_ctrl_bit_mask, sof_idx); + ADI_APOLLO_ERROR_RETURN(err); + + /* Extract the pk mag */ + err = pk_val_get(cap_array, cap_len, *sof_idx, smon_ctrl_bit_mask, pk_val); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +static int32_t sof_framer5_get(int16_t *samples, uint32_t num_samples, uint32_t ofst, uint16_t smon_ctrl_bit_mask, uint32_t *sof_idx) +{ + int32_t s_idx; + int32_t k_idx; + uint8_t sof_found = 0; + int16_t key_seq[11] = {1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 0}; + int32_t key_seq_len = sizeof(key_seq) / sizeof(key_seq[0]); + + *sof_idx = 0; + + if ((num_samples - ofst) < FRAMER_5_MIN_SAMPLES) { + return API_CMS_ERROR_SMON_FRAMER_MIN_SAMPLES_ERROR; + } + + for (s_idx = ofst; s_idx < num_samples - key_seq_len; s_idx++) { + sof_found = 0; + for (k_idx = 0; k_idx < key_seq_len; k_idx++) { + if (((samples[s_idx + k_idx] & smon_ctrl_bit_mask) ? 1 : 0) != key_seq[k_idx]) { + break; + } + } + if (k_idx == key_seq_len) { + sof_found = 1; + break; + } + } + + if (sof_found) { + *sof_idx = s_idx + FRAMER_5_SUB_FRAME_IDLE_NUM_BITS; // Skip over last idle sub-frame, advance to start of identifier sub-frame + } else { + return API_CMS_ERROR_SMON_FRAMER_SOF_NOT_FOUND; + } + + return API_CMS_ERROR_OK; + } + +static int32_t peak_val_framer5_get(int16_t *samples, uint32_t num_samples, uint32_t sof_idx, uint16_t smon_ctrl_bit_mask, uint16_t *peak_val) +{ + + *peak_val = 0; + int16_t shft = 15; + + if ((num_samples - sof_idx - FRAMER_5_SUB_FRAME_ID_NUM_BITS) < (FRAMER_5_SUB_FRAME_DATA_NUM_BITS)) { + return API_CMS_ERROR_SMON_FRAMER_MIN_SAMPLES_ERROR; + } + + // Skip over identifier sub-frame + for (int i = FRAMER_5_SUB_FRAME_ID_NUM_BITS; i < (FRAMER_5_SUB_FRAME_ID_NUM_BITS + FRAMER_5_SUB_FRAME_DATA_NUM_BITS); i++) { + if (!(i % FRAMER_5_SUB_FRAME_NUM_BITS)) { + continue; // skip sub-frame leading 0 start bit + } + + *peak_val |= ((samples[sof_idx + i] & smon_ctrl_bit_mask) ? 1 : 0) << shft; + shft--; + } + + *peak_val = ((uint16_t)(*peak_val)) >> 5; // shift down to 11 bits (resolution of peak hold detector) + + return API_CMS_ERROR_OK; +} + +static int32_t sof_framer10_get(int16_t *samples, uint32_t num_samples, uint32_t ofst, uint16_t smon_ctrl_bit_mask, uint32_t *sof_idx) +{ + int32_t s_idx; + int32_t k_idx; + uint8_t sof_found = 0; + int16_t key_seq[20] = {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1}; + int32_t key_seq_len = sizeof(key_seq) / sizeof(key_seq[0]); + + *sof_idx = 0; + + if ((num_samples - ofst) < FRAMER_10_MIN_SAMPLES) { + return API_CMS_ERROR_SMON_FRAMER_MIN_SAMPLES_ERROR; + } + + for (s_idx = ofst; s_idx < num_samples - key_seq_len; s_idx++) { + sof_found = 0; + for (k_idx = 0; k_idx < key_seq_len; k_idx++) { + + //printf("%6d %d\n", s_idx + k_idx, ((samples[s_idx + k_idx] & ctrl_bit_mask) ? 1 : 0)); + + if (((samples[s_idx + k_idx] & smon_ctrl_bit_mask) ? 1 : 0) != key_seq[k_idx]) { + break; + } + } + if (k_idx == key_seq_len) { + sof_found = 1; + break; + } + } + + if (sof_found) { + *sof_idx = s_idx + FRAMER_10_SUB_FRAME_IDLE_NUM_BITS; // Skip over last idle sub-frame, advance to start of identifier sub-frame + } else { + return API_CMS_ERROR_SMON_FRAMER_SOF_NOT_FOUND; + } + + return API_CMS_ERROR_OK;} + +static int32_t peak_val_framer10_get(int16_t *samples, uint32_t num_samples, uint32_t sof_idx, uint16_t smon_ctrl_bit_mask, uint16_t *peak_val) +{ + *peak_val = 0; + int16_t shft = 15; + + if ((num_samples - sof_idx - FRAMER_10_SUB_FRAME_ID_NUM_BITS) < (FRAMER_10_SUB_FRAME_DATA_NUM_BITS)) { + return API_CMS_ERROR_SMON_FRAMER_MIN_SAMPLES_ERROR; + } + + // Skip over identifier sub-frame + for (int i = FRAMER_10_SUB_FRAME_ID_NUM_BITS; i < (FRAMER_10_SUB_FRAME_ID_NUM_BITS + FRAMER_10_SUB_FRAME_DATA_NUM_BITS); i++) { + if ( (i % FRAMER_10_SUB_FRAME_NUM_BITS == 0) || (i %FRAMER_10_SUB_FRAME_NUM_BITS == 9) ) { + continue; // skip sub-frame start and stop sub-frame bits + } + + *peak_val |= ((samples[sof_idx + i] & smon_ctrl_bit_mask) ? 1 : 0) << shft; + shft--; + } + + *peak_val = ((uint16_t)(*peak_val)) >> 5; // shift down to 11 bits (resolution of peak hold detector) + + return API_CMS_ERROR_OK; +} + +uint32_t calc_smon_base(int32_t smon_index) +{ + static uint32_t rx_smon_regmap[ADI_APOLLO_SMON_NUM] = { + RX_SMON0_RX_SLICE_0_RX_DIGITAL0, RX_SMON0_RX_SLICE_1_RX_DIGITAL0, + RX_SMON1_RX_SLICE_0_RX_DIGITAL0, RX_SMON1_RX_SLICE_1_RX_DIGITAL0, + RX_SMON0_RX_SLICE_0_RX_DIGITAL1, RX_SMON0_RX_SLICE_1_RX_DIGITAL1, + RX_SMON1_RX_SLICE_0_RX_DIGITAL1, RX_SMON1_RX_SLICE_1_RX_DIGITAL1, + }; + + return rx_smon_regmap[smon_index]; +} +/*! @} */ \ No newline at end of file diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_smon_local.h b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_smon_local.h new file mode 100644 index 00000000000000..f9d11b84bcf4af --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_smon_local.h @@ -0,0 +1,36 @@ +/*! + * \brief SMON local defines and prototypes + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_SMON + * @{ + */ +#ifndef __ADI_APOLLO_SMON_LOCAL_H__ +#define __ADI_APOLLO_SMON_LOCAL_H__ + +/*============= I N C L U D E S ============*/ + +/*============= D E F I N E S ==============*/ + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +uint32_t calc_smon_base(int32_t smon_index); + +#ifndef CLIENT_IGNORE +#endif /* CLIENT_IGNORE*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_SMON_LOCAL_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_sniffer.c b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_sniffer.c new file mode 100644 index 00000000000000..0c6932af77dcc1 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_sniffer.c @@ -0,0 +1,456 @@ +/*! + * \brief APIs for Spectrum Sniffer + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_SNIFFER + * @{ + */ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_config.h" +#include "adi_apollo_hal.h" +#include "adi_apollo_private_device.h" +#include "adi_apollo_private_blk_sel_types.h" + +#include "adi_apollo_bf_rx_spectrum_sniffer.h" +#include "adi_apollo_bf_rx_datin.h" +#include "adi_apollo_sniffer.h" +#include "adi_utils.h" + +#define DEFAULT_FFT_TIMEOUT_US 1000 + +static uint32_t calc_rx_sniffer_base(int32_t sniffer_index); +static uint32_t calc_rx_datin_base(int32_t sniffer_index); +static uint32_t calc_adc_mux(adi_apollo_adc_idx_e adc); + +/*==================== P U B L I C A P I C O D E ====================*/ + +int32_t adi_apollo_sniffer_enable_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t sniffers, uint8_t enable) { + int32_t err; + uint32_t regmap_base_addr = 0; + uint16_t side_index; + adi_apollo_blk_sel_t side; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_DEV_FEAT_LOCKOUT_RETURN(ADI_APOLLO_RX, ADI_APOLLO_EC_FFT_SPECTURMSNIFFER_LOCK); + ADI_APOLLO_SNIFFER_BLK_SEL_MASK(sniffers); + + for (side_index = 0; side_index < ADI_APOLLO_SNIFFER_NUM; side_index++) { + side = sniffers & (ADI_APOLLO_SNIFFER_A << side_index); + if (side > 0) { + + regmap_base_addr = calc_rx_sniffer_base(side_index); + // Spectrum sniffer enable + err = adi_apollo_hal_bf_set(device, BF_SPECTRUM_SNIFFER_EN_INFO(regmap_base_addr), enable); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return err; +} + +int32_t adi_apollo_sniffer_adc_mux_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t sniffers, uint16_t adc) { + int32_t err; + uint32_t regmap_base_addr = 0; + uint16_t side_index; + adi_apollo_blk_sel_t side; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_DEV_FEAT_LOCKOUT_RETURN(ADI_APOLLO_RX, ADI_APOLLO_EC_FFT_SPECTURMSNIFFER_LOCK); + ADI_APOLLO_INVALID_PARAM_RETURN( ! (adc == ADI_APOLLO_ADC_0 || adc == ADI_APOLLO_ADC_1 || adc == ADI_APOLLO_ADC_2 || adc == ADI_APOLLO_ADC_3)); + ADI_APOLLO_SNIFFER_BLK_SEL_MASK(sniffers); + + for (side_index = 0; side_index < ADI_APOLLO_SNIFFER_NUM; side_index++) { + side = sniffers & (ADI_APOLLO_SNIFFER_A << side_index); + if (side > 0) { + + regmap_base_addr = calc_rx_datin_base(side_index); + + // ADC mux + err = adi_apollo_hal_bf_set(device, BF_ADC_0_MUX_SEL_INFO(regmap_base_addr), calc_adc_mux(adc)); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return err; +} + +int32_t adi_apollo_sniffer_init(adi_apollo_device_t *device, adi_apollo_blk_sel_t sniffers, adi_apollo_sniffer_init_t *config) { + // Must be called prior to oneshot sync + int32_t err; + uint32_t regmap_base_addr = 0; + uint16_t side_index; + adi_apollo_blk_sel_t side; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_DEV_FEAT_LOCKOUT_RETURN(ADI_APOLLO_RX, ADI_APOLLO_EC_FFT_SPECTURMSNIFFER_LOCK); + ADI_APOLLO_NULL_POINTER_RETURN(config); + ADI_APOLLO_SNIFFER_BLK_SEL_MASK(sniffers); + + for (side_index = 0; side_index < ADI_APOLLO_SNIFFER_NUM; side_index++) { + side = sniffers & (ADI_APOLLO_SNIFFER_A << side_index); + if (side > 0) { + + regmap_base_addr = calc_rx_sniffer_base(side_index); + // Spectrum sniffer enable + err = adi_apollo_hal_bf_set(device, BF_SPECTRUM_SNIFFER_EN_INFO(regmap_base_addr), config->sniffer_enable); + ADI_APOLLO_ERROR_RETURN(err); + + // fft_hold_sel : To select between GPIO and regmap + err = adi_apollo_hal_bf_set(device, BF_FFT_HOLD_SEL_INFO(regmap_base_addr), config->fft_hold_sel); + ADI_APOLLO_ERROR_RETURN(err); + + // fft_enable_sel : To select between GPIO and regmap + err = adi_apollo_hal_bf_set(device, BF_FFT_ENABLE_SEL_INFO(regmap_base_addr), config->fft_enable_sel); + ADI_APOLLO_ERROR_RETURN(err); + + // real_mode : To select between real fft and complex fft + err = adi_apollo_hal_bf_set(device, BF_REAL_MODE_INFO(regmap_base_addr), config->real_mode); + ADI_APOLLO_ERROR_RETURN(err); + + // max_threshold: To set max threshold. + err = adi_apollo_hal_bf_set(device, BF_MAX_THRESHOLD_INFO(regmap_base_addr), config->max_threshold); + ADI_APOLLO_ERROR_RETURN(err); + + // min_threshold: To set min threshold + err = adi_apollo_hal_bf_set(device, BF_MIN_THRESHOLD_INFO(regmap_base_addr), config->min_threshold); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return err; +} + +int32_t adi_apollo_sniffer_pgm(adi_apollo_device_t *device, adi_apollo_blk_sel_t sniffers, adi_apollo_sniffer_pgm_t *config) { + int32_t err; + uint32_t regmap_base_addr = 0; + uint8_t mag_iq, force_sort_store; + uint16_t side_index; + adi_apollo_blk_sel_t side; + + // Check parameters: some configurations are invalid per user guide + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_DEV_FEAT_LOCKOUT_RETURN(ADI_APOLLO_RX, ADI_APOLLO_EC_FFT_SPECTURMSNIFFER_LOCK); + ADI_APOLLO_NULL_POINTER_RETURN(config); + ADI_APOLLO_SNIFFER_BLK_SEL_MASK(sniffers); + + // Get parameters for different modes + + if (config->sniffer_mode > ADI_APOLLO_SNIFFER_INSTANT_MAGNITUDE) { // IQ mode + mag_iq = 0; + } else { // Magnitude mode + mag_iq = 1; + } + + if (config->sniffer_mode % 2 == 1) { // Instantaneous/debug mode + force_sort_store = 1; + } else { // Normal mode + force_sort_store = 0; + } + + if (config->sniffer_mode > ADI_APOLLO_SNIFFER_INSTANT_MAGNITUDE) { + ADI_APOLLO_INVALID_PARAM_RETURN(config->sort_enable != 0); + ADI_APOLLO_INVALID_PARAM_RETURN(config->bottom_fft_enable != 0); + ADI_APOLLO_INVALID_PARAM_RETURN(config->continuous_mode == 1); + } + + if (config->continuous_mode == 1) { + ADI_APOLLO_INVALID_PARAM_RETURN(config->alpha_factor != 0); + } + + ADI_APOLLO_INVALID_PARAM_RETURN(config->alpha_factor > 9); // alpha factor can be 0 - 9 + + // Set values per side + + err = adi_apollo_sniffer_adc_mux_set(device, sniffers, config->adc); + ADI_APOLLO_ERROR_RETURN(err); + + for (side_index = 0; side_index < ADI_APOLLO_SNIFFER_NUM; side_index++) { + side = sniffers & (ADI_APOLLO_SNIFFER_A << side_index); + if (side > 0) { + + regmap_base_addr = calc_rx_sniffer_base(side_index); + + // bottom_fft_enable + err = adi_apollo_hal_bf_set(device, BF_BOTTOM_FFT_ENABLE_INFO(regmap_base_addr), config->bottom_fft_enable); + ADI_APOLLO_ERROR_RETURN(err); + + // window_enable + err = adi_apollo_hal_bf_set(device, BF_WINDOW_ENABLE_INFO(regmap_base_addr), config->window_enable); + ADI_APOLLO_ERROR_RETURN(err); + + // sort_enable + err = adi_apollo_hal_bf_set(device, BF_SORT_EN_INFO(regmap_base_addr), config->sort_enable); + ADI_APOLLO_ERROR_RETURN(err); + + // magnitude_iq_n : To select between magnitude or IQ mode + err = adi_apollo_hal_bf_set(device, BF_MAGNITUDE_IQ_N_INFO(regmap_base_addr), mag_iq); + ADI_APOLLO_ERROR_RETURN(err); + + // force_sort_store_enable : to force instantaneous sorting/storing of data + err = adi_apollo_hal_bf_set(device, BF_FORCE_SORT_STORE_INFO(regmap_base_addr), force_sort_store); + ADI_APOLLO_ERROR_RETURN(err); + + // low_power_enable + err = adi_apollo_hal_bf_set(device, BF_LOW_POWER_INFO(regmap_base_addr), config->low_power_enable); + ADI_APOLLO_ERROR_RETURN(err); + + // dither_enable + err = adi_apollo_hal_bf_set(device, BF_DITHER_ENABLE_INFO(regmap_base_addr), config->dither_enable); + ADI_APOLLO_ERROR_RETURN(err); + + // continuous_mode + err = adi_apollo_hal_bf_set(device, BF_CONTINUOUS_MODE_INFO(regmap_base_addr), config->continuous_mode); + ADI_APOLLO_ERROR_RETURN(err); + + // alpha_factor + err = adi_apollo_hal_bf_set(device, BF_ALPHA_FACTOR_INFO(regmap_base_addr), config->alpha_factor); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return err; +} + +int32_t adi_apollo_sniffer_fft_enable_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t sniffers, uint8_t enable) { + int32_t err = API_CMS_ERROR_OK; + uint32_t regmap_base_addr = 0; + uint16_t s; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_DEV_FEAT_LOCKOUT_RETURN(ADI_APOLLO_RX, ADI_APOLLO_EC_FFT_SPECTURMSNIFFER_LOCK); + ADI_APOLLO_SNIFFER_BLK_SEL_MASK(sniffers); + + for (s = 0; s < ADI_APOLLO_SNIFFER_NUM; s++) { + if (sniffers & (1 << s)) { + regmap_base_addr = calc_rx_sniffer_base(s); + err = adi_apollo_hal_bf_set(device, BF_FFT_ENABLE_INFO(regmap_base_addr), enable); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return err; +} + +int32_t adi_apollo_sniffer_fft_hold_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t sniffers, uint8_t hold) { + int32_t err = API_CMS_ERROR_OK; + uint32_t regmap_base_addr = 0; + uint16_t s; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_DEV_FEAT_LOCKOUT_RETURN(ADI_APOLLO_RX, ADI_APOLLO_EC_FFT_SPECTURMSNIFFER_LOCK); + ADI_APOLLO_SNIFFER_BLK_SEL_MASK(sniffers); + + for (s = 0; s < ADI_APOLLO_SNIFFER_NUM; s++) { + if (sniffers & (1 << s)) { + regmap_base_addr = calc_rx_sniffer_base(s); + err = adi_apollo_hal_bf_set(device, BF_FFT_HOLD_INFO(regmap_base_addr), hold); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return err; +} + +int32_t adi_apollo_sniffer_fft_done_get(adi_apollo_device_t *device, adi_apollo_blk_sel_t sniffers, uint8_t *done) { + int32_t err = API_CMS_ERROR_OK; + uint32_t regmap_base_addr = 0; + uint16_t s; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_DEV_FEAT_LOCKOUT_RETURN(ADI_APOLLO_RX, ADI_APOLLO_EC_FFT_SPECTURMSNIFFER_LOCK); + ADI_APOLLO_INVALID_PARAM_RETURN(adi_api_utils_num_selected(sniffers) != 1); + ADI_APOLLO_NULL_POINTER_RETURN(done); + ADI_APOLLO_SNIFFER_BLK_SEL_MASK(sniffers); + + for (s = 0; s < ADI_APOLLO_SNIFFER_NUM; s++) { + if (sniffers & (1 << s)) { + regmap_base_addr = calc_rx_sniffer_base(s); + err = adi_apollo_hal_bf_get(device, BF_FFT_DONE_INFO(regmap_base_addr), done, 1); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return err; +} + +int32_t adi_apollo_sniffer_fft_data_get(adi_apollo_device_t *device, adi_apollo_blk_sel_t sniffers, adi_apollo_sniffer_param_t *config, adi_apollo_sniffer_fft_data_t *fft_data_params) { + int32_t err; + uint32_t regmap_base_addr = 0; + uint16_t side; + + uint8_t max_threshold_tmp; + uint8_t min_threshold_tmp; + + uint16_t k, j; + + // Check parameters + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_DEV_FEAT_LOCKOUT_RETURN(ADI_APOLLO_RX, ADI_APOLLO_EC_FFT_SPECTURMSNIFFER_LOCK); + ADI_APOLLO_NULL_POINTER_RETURN(fft_data_params); + ADI_APOLLO_NULL_POINTER_RETURN(config); + ADI_APOLLO_INVALID_PARAM_RETURN(sniffers > ADI_APOLLO_SNIFFER_B); + ADI_APOLLO_INVALID_PARAM_RETURN(config->init.real_mode && config->pgm.sniffer_mode > ADI_APOLLO_SNIFFER_INSTANT_MAGNITUDE); // Real mode has no meaning in IQ mode + ADI_APOLLO_SNIFFER_BLK_SEL_MASK(sniffers); + + side = (sniffers == ADI_APOLLO_SNIFFER_A) ? 0 : 1; + regmap_base_addr = calc_rx_sniffer_base(side); + + // Update fft data with meta info + + fft_data_params->data_mode = config->pgm.sniffer_mode; + fft_data_params->valid_data_length = (config->init.real_mode) ? (ADI_APOLLO_SNIFFER_FFT_LENGTH / 2) : ADI_APOLLO_SNIFFER_FFT_LENGTH; + fft_data_params->max_threshold = config->init.max_threshold; + fft_data_params->min_threshold = config->init.min_threshold; + fft_data_params->fft_is_complex = config->init.real_mode ? 0 : 1; + + // Read data + for (k = 0; k < fft_data_params->valid_data_length; k++) { + + // Read Magnitude / I data + err = adi_apollo_hal_bf_get(device, BF_MAGNITUDE_I_INFO(regmap_base_addr, k), + (uint8_t *) &fft_data_params->mag_i_data[k], 2); + ADI_APOLLO_ERROR_RETURN(err); + + // Read Bin number / Q data + if (config->pgm.sniffer_mode > ADI_APOLLO_SNIFFER_INSTANT_MAGNITUDE || config->pgm.sort_enable) { // IQ mode or sorting enabled + err = adi_apollo_hal_bf_get(device, BF_BIN_NUMBER_Q_INFO(regmap_base_addr, k), + (uint8_t *) &fft_data_params->bin_q_data[k], 2); + ADI_APOLLO_ERROR_RETURN(err); + } else { + fft_data_params->bin_q_data[k] = k; // When sorting is disabled, every bin_number returns as 0 so we manually set it in software + } + } + + // Read bin threshold values (magnitude mode only) + if (config->pgm.sniffer_mode <= ADI_APOLLO_SNIFFER_INSTANT_MAGNITUDE) { // Mag mode + for (k = 0; k < fft_data_params->valid_data_length/8; k++) { + //for reading bins above threshold and below threshold + + err = adi_apollo_hal_bf_get(device, BF_MAX_THRESHOLD_BIN_INFO(regmap_base_addr, k), &max_threshold_tmp, 1); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_get(device, BF_MIN_THRESHOLD_BIN_INFO(regmap_base_addr, k), &min_threshold_tmp, 1); + ADI_APOLLO_ERROR_RETURN(err); + + for (j = 0 ; j < 8; j++) { + + fft_data_params->bin_above_threshold[k*8 + j] = ((max_threshold_tmp & (1 << j)) > 0) ? 1 : 0; + fft_data_params->bin_below_threshold[k*8 + j] = ((min_threshold_tmp & (1 << j)) > 0) ? 1 : 0; + } + } + + } + + return err; +} + +int32_t adi_apollo_sniffer_data_get(adi_apollo_device_t *device, adi_apollo_blk_sel_t sniffers, adi_apollo_sniffer_param_t *config, adi_apollo_sniffer_fft_data_t *fft_data_params) { + int32_t err; + uint8_t fft_done = 0; + uint64_t fft_timeout; + uint8_t do_fft_timeout; + + // Check parameters + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_DEV_FEAT_LOCKOUT_RETURN(ADI_APOLLO_RX, ADI_APOLLO_EC_FFT_SPECTURMSNIFFER_LOCK); + ADI_APOLLO_NULL_POINTER_RETURN(fft_data_params); + ADI_APOLLO_NULL_POINTER_RETURN(config); + ADI_APOLLO_INVALID_PARAM_RETURN(sniffers > ADI_APOLLO_SNIFFER_B); + ADI_APOLLO_INVALID_PARAM_RETURN(config->init.real_mode && config->pgm.sniffer_mode > ADI_APOLLO_SNIFFER_INSTANT_MAGNITUDE); // Real mode has no meaning in IQ mode + ADI_APOLLO_INVALID_PARAM_RETURN(config->init.fft_enable_sel == ADI_APOLLO_SNIFFER_GPIO_INPUT); + ADI_APOLLO_INVALID_PARAM_RETURN(config->init.fft_hold_sel == ADI_APOLLO_SNIFFER_GPIO_INPUT); + ADI_APOLLO_SNIFFER_BLK_SEL_MASK(sniffers); + + + fft_timeout = config->read.timeout_us ? config->read.timeout_us : DEFAULT_FFT_TIMEOUT_US; + do_fft_timeout = (config->pgm.sniffer_mode % 2 == 1 || config->read.timeout_us) ? 1 : 0; // Do timeout for instantaneous mode or if timeout is set + + // Data request sequence + + // Set FFT enable high + err = adi_apollo_sniffer_fft_enable_set(device, sniffers, 1); + ADI_APOLLO_ERROR_RETURN(err); + + // Set FFT hold low + err = adi_apollo_sniffer_fft_hold_set(device, sniffers, 0); + ADI_APOLLO_ERROR_RETURN(err); + + // Wait for fft_done to go high + while(fft_done == 0) { + err = adi_apollo_sniffer_fft_done_get(device, sniffers, &fft_done); + ADI_APOLLO_ERROR_RETURN(err); + + if (do_fft_timeout) { + device->hal_info.delay_us(device, 1); + fft_timeout--; + if (! fft_timeout ) { + return API_CMS_ERROR_OPERATION_TIMEOUT; + } + } + } + + // Disable fft engine + if (! config->read.run_fft_engine_background) { + err = adi_apollo_sniffer_fft_enable_set(device, sniffers, 0); + ADI_APOLLO_ERROR_RETURN(err); + } + // Hold fft + err = adi_apollo_sniffer_fft_hold_set(device, sniffers, 1); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_sniffer_fft_data_get(device, sniffers, config, fft_data_params); + ADI_APOLLO_ERROR_RETURN(err); + + return err; +} + +static uint32_t calc_rx_sniffer_base(int32_t sniffer_index) +{ + static uint32_t sniffer_addr[] = { + RX_SPECTRUM_SNIFFER_RX_SLICE_0_RX_DIGITAL0, RX_SPECTRUM_SNIFFER_RX_SLICE_0_RX_DIGITAL1 + }; + + return sniffer_addr[sniffer_index]; +} + +static uint32_t calc_rx_datin_base(int32_t sniffer_index) +{ + static uint32_t datin_addr[] = { + RX_DATIN_RX_SLICE_0_RX_DIGITAL0, RX_DATIN_RX_SLICE_0_RX_DIGITAL1 + }; + + return datin_addr[sniffer_index]; +} + +static uint32_t calc_adc_mux(adi_apollo_adc_idx_e adc) +{ + uint8_t i; + + for (i = 0; i < ADI_APOLLO_ADC_PER_SIDE_NUM; i++) { + if ((1 << i) & adc) { + return i; + } + } + + return 0; +} + +/*! @} */ \ No newline at end of file diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_startup.c b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_startup.c new file mode 100644 index 00000000000000..1da5c22815c6a9 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_startup.c @@ -0,0 +1,522 @@ +/*! + * \brief Startup sequence APIs + * + * \copyright copyright(c) 2024 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_STARTUP + * @{ + */ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo.h" +#include "adi_utils.h" +#include "adi_apollo_startup_types.h" +#include "adi_apollo_bf_custom.h" + +#define SECR_BOOT_HDR_MEM_ADDR (0x01030000U) // CODE_MEMORY_A_6 APOLLO_CPU0_IRAM_START +#define CORE_0_TYE_FW_MEM_ADDR (0x20000000U) // SYS_MEMORY_A_0 APOLLO_CPU0_DRAM_START +#define CORE_1_TYE_FW_MEM_ADDR (0x02000000U) // CODE_MEMORY_B_0 APOLLO_CPU1_IRAM_START +#define TYE_OPER_FW_MEM_ADDR (0x21000000U) // SYS_MEMORY_B_0 APOLLO_CPU1_DRAM_START +#define TYE_USER_SCENARIO (4) + +#define FW_TRANSFER_CHUNK_SIZE (16 * 1024) // FW write chunk block size +#define PREFIX "adi_apollo_startup_execute: " + +/*============= C O D E ====================*/ +static int32_t startup_seq_execute(adi_apollo_device_t *device, adi_apollo_top_t *dev_profile, + adi_apollo_fw_provider_t *fw_provider, adi_apollo_startup_seq_type_e startup_type); +static int32_t fw_load(adi_apollo_device_t *device); +static int32_t tye_fw_load(adi_apollo_device_t *device, uint8_t scenario); +static int32_t profile_load(adi_apollo_device_t *device, adi_apollo_top_t *profile); +static int32_t activate_rx_tx_blocks(adi_apollo_device_t *device); + +static int32_t seq_fw_load(adi_apollo_device_t *device, adi_apollo_fw_provider_t *fw_provider); +static int32_t seq_profile_load(adi_apollo_device_t *device, adi_apollo_top_t *dev_profile); +static int32_t seq_tmu_enable(adi_apollo_device_t *device); +static int32_t seq_dp_config(adi_apollo_device_t *device, adi_apollo_top_t *dev_profile); +static int32_t seq_link_en(adi_apollo_device_t *device, adi_apollo_top_t *dev_profile); +static int32_t seq_txrx_activate(adi_apollo_device_t *device); +static int32_t seq_sync(adi_apollo_device_t *device); + +int32_t adi_apollo_startup_execute(adi_apollo_device_t *device, adi_apollo_top_t *dev_profile, uint32_t startup_type) +{ + int32_t err = API_CMS_ERROR_OK; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(dev_profile); + ADI_APOLLO_NULL_POINTER_RETURN(device->startup_info.fw_provider); + ADI_APOLLO_NULL_POINTER_RETURN(device->startup_info.fw_provider->desc); + ADI_APOLLO_NULL_POINTER_RETURN(device->startup_info.get); + ADI_APOLLO_INVALID_PARAM_RETURN((startup_type & ADI_APOLLO_STARTUP_SEQ_DEFAULT) == 0); + + ADI_APOLLO_LOG_MSG_VAR(PREFIX"startup_type 0x%08x", startup_type); + ADI_APOLLO_LOG_MSG_VAR(PREFIX"profile checksum %lu", dev_profile->profile_checksum); + ADI_APOLLO_LOG_MSG_VAR(PREFIX"fw_provider desc '%s'", device->startup_info.fw_provider->desc); + + /* Execute the startup sequence */ + err = startup_seq_execute(device, dev_profile, device->startup_info.fw_provider, startup_type); + ADI_APOLLO_ERROR_RETURN(err); + + return err; +} + +static int32_t startup_seq_execute(adi_apollo_device_t *device, adi_apollo_top_t *dev_profile, + adi_apollo_fw_provider_t *fw_provider, adi_apollo_startup_seq_type_e startup_type) +{ + + int32_t err = API_CMS_ERROR_OK; + + if (startup_type & ADI_APOLLO_STARTUP_SEQ_FW_LOAD) { + err = seq_fw_load(device, fw_provider); + ADI_APOLLO_LOG_MSG_VAR(PREFIX"seq_fw_load: %s", (err == API_CMS_ERROR_OK) ? "OK" : "Error"); + ADI_APOLLO_ERROR_RETURN(err); + } + + if (startup_type & ADI_APOLLO_STARTUP_SEQ_PROFILE_LOAD) { + err = seq_profile_load(device, dev_profile); + ADI_APOLLO_LOG_MSG_VAR(PREFIX"seq_profile_load: %s", (err == API_CMS_ERROR_OK) ? "OK" : "Error"); + ADI_APOLLO_ERROR_RETURN(err); + } + + if (startup_type & ADI_APOLLO_STARTUP_SEQ_TMU_EN) { + err = seq_tmu_enable(device); + ADI_APOLLO_LOG_MSG_VAR(PREFIX"seq_tmu_enable: %s", (err == API_CMS_ERROR_OK) ? "OK" : "Error"); + ADI_APOLLO_ERROR_RETURN(err); + } + + if (startup_type & ADI_APOLLO_STARTUP_SEQ_DP_CONFIG) { + err = seq_dp_config(device, dev_profile); + ADI_APOLLO_LOG_MSG_VAR(PREFIX"seq_dp_config: %s", (err == API_CMS_ERROR_OK) ? "OK" : "Error"); + ADI_APOLLO_ERROR_RETURN(err); + } + + if (startup_type & ADI_APOLLO_STARTUP_SEQ_LINK_EN) { + err = seq_link_en(device, dev_profile); + ADI_APOLLO_LOG_MSG_VAR(PREFIX"seq_link_en: %s", (err == API_CMS_ERROR_OK) ? "OK" : "Error"); + ADI_APOLLO_ERROR_RETURN(err); + } + + if (startup_type & ADI_APOLLO_STARTUP_SEQ_TXRX_ACTIVATE) { + err = seq_txrx_activate(device); + ADI_APOLLO_LOG_MSG_VAR(PREFIX"seq_txrx_activate: %s", (err == API_CMS_ERROR_OK) ? "OK" : "Error"); + ADI_APOLLO_ERROR_RETURN(err); + } + + if (startup_type & ADI_APOLLO_STARTUP_SEQ_SYNC) { + err = seq_sync(device); + ADI_APOLLO_LOG_MSG_VAR(PREFIX"seq_sync: %s", (err == API_CMS_ERROR_OK) ? "OK" : "Error"); + ADI_APOLLO_ERROR_RETURN(err); + } + + return err; +} + +static int32_t seq_fw_load(adi_apollo_device_t *device, adi_apollo_fw_provider_t *fw_provider) +{ + + int32_t err = API_CMS_ERROR_OK; + uint8_t tye_bypassed = 0; + + ADI_APOLLO_LOG_MSG(PREFIX"ADI_APOLLO_STARTUP_SEQ_FW_LOAD"); + + err = adi_apollo_arm_tye_bypassed_get(device, &tye_bypassed); + ADI_APOLLO_ERROR_RETURN(err); + ADI_APOLLO_LOG_MSG_VAR(PREFIX"TyE bypassed: %d", tye_bypassed); + + /* Load FW files */ + if (tye_bypassed) { + /* Load the standard device firmware for core0 and core1.*/ + err = fw_load(device); + ADI_APOLLO_LOG_ERROR_RETURN_VAR(err, PREFIX"fw_load", ""); + } else { + /* Load the TyE app pack firmware.*/ + err = tye_fw_load(device, TYE_USER_SCENARIO); + ADI_APOLLO_LOG_ERROR_RETURN_VAR(err, PREFIX"tye_fw_load %d", err); + } + + return err; +} + +static int32_t seq_profile_load(adi_apollo_device_t *device, adi_apollo_top_t *dev_profile) +{ + int32_t err = API_CMS_ERROR_OK; + uint32_t num_tries = 10; + uint8_t boot_status = 0; + uint8_t prev_boot_status = 0; + int32_t fw_err_code = 0; + + ADI_APOLLO_LOG_MSG("ADI_APOLLO_STARTUP_SEQ_PROFILE_LOAD"); + + /* Wait for FW ready to accept profile */ + num_tries = 100; + do { + err = adi_apollo_hal_delay_us(device, 50000); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_arm_boot_status(device, &boot_status); + ADI_APOLLO_ERROR_RETURN(err); + + if (boot_status != prev_boot_status) { + ADI_APOLLO_LOG_MSG_VAR("Core 1 Ram Boot Status: 0x%02X", boot_status); + prev_boot_status = boot_status; + } + + } while (boot_status != ADI_APOLLO_RAM_BOOT_STEP_WAIT_FOR_CONFIG && num_tries-- > 0); + + if (boot_status != ADI_APOLLO_RAM_BOOT_STEP_WAIT_FOR_CONFIG) { + err = API_CMS_ERROR_STARTUP_FW_RDY_FOR_PROFILE_ERROR; + ADI_APOLLO_LOG_ERROR_RETURN_VAR(err, PREFIX"FW didn't reach wait for device profile state. boot_status: 0x%x.", boot_status); + } + + /* + * Load the device profile use case into the firmware (arm) + * + * Firmware configures: + * - Clocks and PLLs + * - JESD JRx and JTx + * + * The API will configure other functional blocks using the same device profile + */ + ADI_APOLLO_LOG_MSG_VAR(PREFIX"Loading device profile (ver=%d.%d.%d, %s)...", + dev_profile->profile_cfg.profile_version.major, + dev_profile->profile_cfg.profile_version.minor, + dev_profile->profile_cfg.profile_version.patch, + dev_profile->profile_cfg.is_8t8r ? "8T8R" : "4T4R"); + ADI_APOLLO_LOG_MSG_VAR(PREFIX"Profile checksum: %u", dev_profile->profile_checksum); + err = profile_load(device, dev_profile); + ADI_APOLLO_LOG_ERROR_RETURN_VAR(err, PREFIX"Profile write to device failed. err: %d", err); + + /* Verify FW mailbox is ready */ + num_tries = 600; + do { + err = adi_apollo_hal_delay_us(device, 1 * 50000); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_arm_boot_status(device, &boot_status); + ADI_APOLLO_ERROR_RETURN(err); + + if (boot_status != prev_boot_status) { + ADI_APOLLO_LOG_MSG_VAR("Core 1 Ram Boot Status: 0x%02X", boot_status); + prev_boot_status = boot_status; + } + + } while (boot_status != ADI_APOLLO_CPU_BOOT_MAILBOX_READY && num_tries-- > 0); + + if (boot_status != ADI_APOLLO_CPU_BOOT_MAILBOX_READY) { + // Log the FW error code + fw_err_code = adi_apollo_arm_ram_boot_error_check(device); + ADI_APOLLO_LOG_ERR_VAR(PREFIX "FW didn't reach mailbox ready state. fw_err_code: 0x%x", fw_err_code); + + err = API_CMS_ERROR_STARTUP_FW_MAILBOX_RDY_ERROR; + ADI_APOLLO_LOG_ERROR_RETURN_VAR(err, PREFIX"FW didn't reach mailbox ready state. boot_status: 0x%x", boot_status); + } + + + return err; +} + +static int32_t seq_tmu_enable(adi_apollo_device_t *device) +{ + int32_t err = API_CMS_ERROR_OK; + + ADI_APOLLO_LOG_MSG(PREFIX"ADI_APOLLO_STARTUP_SEQ_TMU_EN"); + + /* Enable TMU */ + err = adi_apollo_device_tmu_enable(device); + ADI_APOLLO_LOG_ERROR_RETURN_VAR(err, PREFIX"adi_apollo_device_tmu_enable. err: %d", err); + + return err; +} + +static int32_t seq_dp_config(adi_apollo_device_t *device, adi_apollo_top_t *dev_profile) +{ + int32_t err = API_CMS_ERROR_OK; + + ADI_APOLLO_LOG_MSG(PREFIX"ADI_APOLLO_STARTUP_SEQ_DP_CONFIG"); + + /* Configure the Rx and Tx data paths as specified in the device profile */ + err = adi_apollo_cfg_data_path(device, dev_profile); + ADI_APOLLO_LOG_ERROR_RETURN_VAR(err, PREFIX"adi_apollo_cfg_data_path failed. err: %d", err); + + return err; +} + +static int32_t seq_link_en(adi_apollo_device_t *device, adi_apollo_top_t *dev_profile) +{ + int32_t err; + + ADI_APOLLO_LOG_MSG(PREFIX"ADI_APOLLO_STARTUP_SEQ_LINK_EN"); + + /* Enable Apollo JTx and JRx links based on device profile */ + err = adi_apollo_jtx_link_enable_set(device, ADI_APOLLO_LINK_A0, dev_profile->jtx[0].tx_link_cfg[0].link_in_use); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_jtx_link_enable_set(device, ADI_APOLLO_LINK_A1, dev_profile->jtx[0].tx_link_cfg[1].link_in_use); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_jtx_link_enable_set(device, ADI_APOLLO_LINK_B0, dev_profile->jtx[1].tx_link_cfg[0].link_in_use); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_jtx_link_enable_set(device, ADI_APOLLO_LINK_B1, dev_profile->jtx[1].tx_link_cfg[1].link_in_use); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_jrx_link_enable_set(device, ADI_APOLLO_LINK_A0, dev_profile->jrx[0].rx_link_cfg[0].link_in_use); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_jrx_link_enable_set(device, ADI_APOLLO_LINK_A1, dev_profile->jrx[0].rx_link_cfg[1].link_in_use); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_jrx_link_enable_set(device, ADI_APOLLO_LINK_B0, dev_profile->jrx[1].rx_link_cfg[0].link_in_use); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_jrx_link_enable_set(device, ADI_APOLLO_LINK_B1, dev_profile->jrx[1].rx_link_cfg[1].link_in_use); + ADI_APOLLO_ERROR_RETURN(err); + + return err; +} + +static int32_t seq_txrx_activate(adi_apollo_device_t *device) +{ + int32_t err; + + ADI_APOLLO_LOG_MSG(PREFIX"ADI_APOLLO_STARTUP_SEQ_TXRX_ACTIVATE"); + + /* Activate the Rx and Tx blocks */ + err = activate_rx_tx_blocks(device); + ADI_APOLLO_LOG_ERROR_RETURN_VAR(err, PREFIX"activate_rx_tx_blocks failed. err: %d", err); + + return err; +} + +static int32_t seq_sync(adi_apollo_device_t *device) +{ + int32_t err; + + ADI_APOLLO_LOG_MSG(PREFIX"ADI_APOLLO_STARTUP_SEQ_SYNC"); + + /* Datapath reset */ + err = adi_apollo_rxmisc_dp_reset(device, ADI_APOLLO_SIDE_ALL, 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_txmisc_dp_reset(device, ADI_APOLLO_SIDE_ALL, 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_rxmisc_dp_reset(device, ADI_APOLLO_SIDE_ALL, 0); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_txmisc_dp_reset(device, ADI_APOLLO_SIDE_ALL, 0); + ADI_APOLLO_ERROR_RETURN(err); + + /* Dynamic sync sequence - gradual enabling of blocks to mitigate dynamic power */ + err = adi_apollo_clk_mcs_dyn_sync_sequence_run(device); + ADI_APOLLO_LOG_ERROR_RETURN_VAR(err, PREFIX"adi_apollo_clk_mcs_dyn_sync_sequence_run failed. err: %d\n", err); + + return err; +} + +static int32_t fw_load(adi_apollo_device_t *device) +{ + int32_t err; + uint8_t *core1_fw_buf = NULL; + uint8_t *core0_fw_buf = NULL; + uint32_t core1_size_bytes = 0; + uint32_t core0_size_bytes = 0; + adi_apollo_fw_provider_t *fw_provider; + + fw_provider = device->startup_info.fw_provider; + + err = adi_apollo_arm_fwload_pre_config(device); + ADI_CMS_ERROR_RETURN(err); + + ADI_APOLLO_LOG_MSG(PREFIX"Loading firmware for Core1..."); + err = device->startup_info.open ? device->startup_info.open(fw_provider, ADI_APOLLO_FW_ID_CORE_1_STD_FW_BIN) : API_CMS_ERROR_OK; + ADI_CMS_ERROR_RETURN(err); + + err = device->startup_info.get(fw_provider, ADI_APOLLO_FW_ID_CORE_1_STD_FW_BIN, &core1_fw_buf, &core1_size_bytes); + ADI_CMS_ERROR_RETURN(err); + + err = adi_apollo_arm_firmware_buf_write(device, ADI_APOLLO_CPU_ID_1, core1_fw_buf, core1_size_bytes, FW_TRANSFER_CHUNK_SIZE); + ADI_CMS_ERROR_RETURN(err); + + err = device->startup_info.close ? device->startup_info.close(fw_provider, ADI_APOLLO_FW_ID_CORE_1_STD_FW_BIN) : API_CMS_ERROR_OK; + ADI_CMS_ERROR_RETURN(err); + + ADI_APOLLO_LOG_MSG(PREFIX"Loading firmware for Core0..."); + err = device->startup_info.open ? device->startup_info.open(fw_provider, ADI_APOLLO_FW_ID_CORE_0_STD_FW_BIN) : API_CMS_ERROR_OK; + ADI_CMS_ERROR_RETURN(err); + + err = device->startup_info.get(fw_provider, ADI_APOLLO_FW_ID_CORE_0_STD_FW_BIN, &core0_fw_buf, &core0_size_bytes); + ADI_CMS_ERROR_RETURN(err); + + err = adi_apollo_arm_firmware_buf_write(device, ADI_APOLLO_CPU_ID_0, core0_fw_buf, core0_size_bytes, FW_TRANSFER_CHUNK_SIZE); + ADI_CMS_ERROR_RETURN(err); + + err = device->startup_info.close ? device->startup_info.close(fw_provider, ADI_APOLLO_FW_ID_CORE_0_STD_FW_BIN) : API_CMS_ERROR_OK; + ADI_CMS_ERROR_RETURN(err); + + err = adi_apollo_arm_fwload_post_config(device); + ADI_CMS_ERROR_RETURN(err); + + return err; +} + +static int32_t tye_fw_load(adi_apollo_device_t *device, uint8_t scenario) +{ + int32_t err = API_CMS_ERROR_OK; + uint8_t si_grade; + + adi_apollo_startup_fw_id_e secr_hdr_filename; + adi_apollo_startup_fw_id_e core0_fw_filename; + adi_apollo_startup_fw_id_e core1_fw_filename; + adi_apollo_startup_fw_id_e oper_fw_filename; + + uint8_t *secr_hdr_buf = NULL; + uint8_t *core0_fw_buf = NULL; + uint8_t *core1_fw_buf = NULL; + uint8_t *oper_fw_buf = NULL; + + uint32_t secr_hdr_size_bytes = 0; + uint32_t core0_fw_size_bytes = 0; + uint32_t core1_fw_size_bytes = 0; + uint32_t oper_fw_size_bytes = 0; + + adi_apollo_fw_provider_t *fw_provider = device->startup_info.fw_provider; + + ADI_APOLLO_LOG_MSG_VAR(PREFIX"Running scenario = %d", scenario); + + err = adi_apollo_device_si_grade_get(device, &si_grade); + ADI_CMS_ERROR_RETURN(err); + ADI_APOLLO_LOG_MSG_VAR(PREFIX"Apollo Silicon Grade = %02d", si_grade); + + secr_hdr_filename = (si_grade == 0) ? ADI_APOLLO_FW_ID_SECR_BOOT_HDR_BIN : ADI_APOLLO_FW_ID_PROD_SECR_BOOT_HDR_BIN; + core0_fw_filename = (si_grade == 0) ? ADI_APOLLO_FW_ID_CORE_0_TYE_FW_BIN : ADI_APOLLO_FW_ID_PROD_CORE_0_TYE_FW_BIN; + core1_fw_filename = (si_grade == 0) ? ADI_APOLLO_FW_ID_CORE_1_TYE_FW_BIN : ADI_APOLLO_FW_ID_PROD_CORE_1_TYE_FW_BIN; + oper_fw_filename = (si_grade == 0) ? ADI_APOLLO_FW_ID_TYE_OPER_FW_BIN : ADI_APOLLO_FW_ID_PROD_TYE_OPER_FW_BIN; + + err = adi_apollo_arm_fwload_pre_config(device); + ADI_CMS_ERROR_RETURN(err); + + /* Load the firmware header to memory. */ + ADI_APOLLO_LOG_MSG(PREFIX"Loading TyE SecureBoot Header image..."); + err = device->startup_info.open ? device->startup_info.open(fw_provider, secr_hdr_filename) : API_CMS_ERROR_OK; + ADI_CMS_ERROR_RETURN(err); + + err = device->startup_info.get(fw_provider, secr_hdr_filename, &secr_hdr_buf, &secr_hdr_size_bytes); + ADI_CMS_ERROR_RETURN(err); + + err = adi_apollo_arm_tye_firmware_buf_write(device, SECR_BOOT_HDR_MEM_ADDR, secr_hdr_buf, secr_hdr_size_bytes, FW_TRANSFER_CHUNK_SIZE); + ADI_CMS_ERROR_RETURN(err); + + err = device->startup_info.close ? device->startup_info.close(fw_provider, secr_hdr_filename) : API_CMS_ERROR_OK; + ADI_CMS_ERROR_RETURN(err); + + // Scenarios 2 and 4 app_pack contains the core 0 firmware image. + if (scenario == 2 || scenario == 4) { + ADI_APOLLO_LOG_MSG(PREFIX"Loading Core0 firmware image..."); + err = device->startup_info.open ? device->startup_info.open(fw_provider, core0_fw_filename) : API_CMS_ERROR_OK; + ADI_CMS_ERROR_RETURN(err); + + err = device->startup_info.get(fw_provider, core0_fw_filename, &core0_fw_buf, &core0_fw_size_bytes); + ADI_CMS_ERROR_RETURN(err); + + err = adi_apollo_arm_tye_firmware_buf_write(device, CORE_0_TYE_FW_MEM_ADDR, core0_fw_buf, core0_fw_size_bytes, FW_TRANSFER_CHUNK_SIZE); + ADI_CMS_ERROR_RETURN(err); + + err = device->startup_info.close ? device->startup_info.close(fw_provider, core0_fw_filename) : API_CMS_ERROR_OK; + ADI_CMS_ERROR_RETURN(err); + } + + // Scenarios 3 and 4 app_pack contains the core 1 firmware image. + if (scenario == 3 || scenario == 4) { + ADI_APOLLO_LOG_MSG(PREFIX"Loading Core1 firmware image..."); + err = device->startup_info.open ? device->startup_info.open(fw_provider, core1_fw_filename) : API_CMS_ERROR_OK; + ADI_CMS_ERROR_RETURN(err); + + err = device->startup_info.get(fw_provider, core1_fw_filename, &core1_fw_buf, &core1_fw_size_bytes); + ADI_CMS_ERROR_RETURN(err); + + err = adi_apollo_arm_tye_firmware_buf_write(device, CORE_1_TYE_FW_MEM_ADDR, core1_fw_buf, core1_fw_size_bytes, FW_TRANSFER_CHUNK_SIZE); + ADI_CMS_ERROR_RETURN(err); + + err = device->startup_info.close ? device->startup_info.close(fw_provider, core1_fw_filename) : API_CMS_ERROR_OK; + ADI_CMS_ERROR_RETURN(err); + } + + /* Load the operation firmware image to memory */ + ADI_APOLLO_LOG_MSG(PREFIX"Loading TinyE Operation firmware image..."); + err = device->startup_info.open ? device->startup_info.open(fw_provider, oper_fw_filename) : API_CMS_ERROR_OK; + ADI_CMS_ERROR_RETURN(err); + + device->startup_info.get(fw_provider, oper_fw_filename, &oper_fw_buf, &oper_fw_size_bytes); + ADI_CMS_ERROR_RETURN(err); + + err = adi_apollo_arm_tye_firmware_buf_write(device, TYE_OPER_FW_MEM_ADDR, oper_fw_buf, oper_fw_size_bytes, FW_TRANSFER_CHUNK_SIZE); + ADI_CMS_ERROR_RETURN(err); + + err = device->startup_info.close ? device->startup_info.close(fw_provider, oper_fw_filename) : API_CMS_ERROR_OK; + ADI_CMS_ERROR_RETURN(err); + + /* Set boot ready bit */ + err = adi_apollo_arm_tye_boot_ready_set(device); + ADI_APOLLO_LOG_ERROR_RETURN_VAR(err, PREFIX"Error setting boot ready bit. Err: %d.", err); + ADI_APOLLO_LOG_MSG(PREFIX"Boot Ready bit has been set"); + + /* Delay 0.1s */ + adi_apollo_hal_delay_us(device, 1 * 10000); + + err = adi_apollo_arm_fwload_post_config(device); + ADI_APOLLO_LOG_ERROR_RETURN_VAR(err, PREFIX"adi_apollo_arm_fwload_post_config error. Err: %d.", err); + + err = adi_apollo_arm_tye_validate_boot_completion(device, 1); + ADI_APOLLO_LOG_ERROR_RETURN_VAR(err, PREFIX"Error: adi_apollo_arm_tye_validate_boot_completion. Err: %d.", err); + + return err; +} + +static int32_t profile_load(adi_apollo_device_t *device, adi_apollo_top_t *profile) +{ + int32_t err; + uint8_t boot_status; + uint32_t device_profile_start_addr; + + err = adi_apollo_hal_bf_set(device, BF_CONFIG_TRANSFER_DONE, 0); + + /* Write the profile configuration to ARM memory for firmware processing */ + if (err = adi_apollo_arm_profile_write(device, profile, 16 * 1024), err != API_CMS_ERROR_OK) { + ADI_APOLLO_LOG_ERR_VAR(PREFIX"adi_apollo_arm_profile_write error: 0x%x", err); + return err; + } + + adi_apollo_hal_reg32_get(device, ADI_APOLLO_FW_DEVICE_PROFILE_PTR, &device_profile_start_addr); + + /* Notify firmware that profile load has completed */ + if (err = adi_apollo_arm_profile_write_post_config(device, profile), err != API_CMS_ERROR_OK) { + adi_apollo_arm_boot_status(device, &boot_status); + ADI_APOLLO_LOG_ERR_VAR(PREFIX"Profile write completed with error code: %d. boot_status: 0x%x", err, boot_status); + return err; + } + + return API_CMS_ERROR_OK; +} + +static int32_t activate_rx_tx_blocks(adi_apollo_device_t *device) +{ + int32_t err; + + /* Enable Rx blocks - enable/disable via spi */ + adi_apollo_rxen_pwrup_ctrl_t rxen_config = { + .sm_clk_rate = ADI_APOLLO_PUC_CLK_RATE_FS_DIV_32, + .sm_en = 0, .spi_rxen = 1, .spi_rxen_en = 1 + }; + + err = adi_apollo_rxen_pwrup_ctrl_set(device, ADI_APOLLO_RXEN_ADC_ALL, &rxen_config); + ADI_CMS_ERROR_RETURN(err); + + /* Enable Tx blocks - enable/disable via spi */ + adi_apollo_txen_pwrup_ctrl_t txen_config = { + .sm_clk_rate = ADI_APOLLO_PUC_CLK_RATE_FS_DIV_32, + .sm_en = 0, .spi_txen = 1, .spi_txen_en = 1 + }; + + err = adi_apollo_txen_pwrup_ctrl_set(device, ADI_APOLLO_TXEN_DAC_ALL, &txen_config); + ADI_CMS_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +/*! @} */ \ No newline at end of file diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_sysclk_cond.c b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_sysclk_cond.c new file mode 100644 index 00000000000000..b063357d917358 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_sysclk_cond.c @@ -0,0 +1,117 @@ +/*! + * \brief APIs for Apollo system clock calibration + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_SYSCLK_COND + * @{ + */ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_config.h" +#include "adi_apollo_hal.h" +#include "adi_apollo_sysclk_cond.h" + +/*==================== P U B L I C A P I C O D E ====================*/ +int32_t adi_apollo_sysclk_cond_cal(adi_apollo_device_t* device) +{ + int32_t err; + adi_apollo_mailbox_resp_sysclk_conditioning_t sysclk_cond_resp; + adi_apollo_mailbox_cmd_sysclk_conditioning_t cc_cmd; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + adi_apollo_hal_log_write(device, ADI_CMS_LOG_API, "Starting clock conditioning cal (can take up to %d secs)...\n", ADI_APOLLO_SYSCLK_COND_CENTER_MAX_TO); + + /*** ADC and SERDES tracking cals must be disabled ***/ + + /* + * Run clock conditioning calibration + */ + cc_cmd.clk_path_segment = APOLLO_SYSCLK_ALL_WITH_RINGOSC_SWITCH; + if (err = adi_apollo_mailbox_sysclk_conditioning(device, &cc_cmd, &sysclk_cond_resp), err != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "adi_apollo_sysclk_cond_cal returned err = %d", err); + goto end; + } + if (sysclk_cond_resp.status != APOLLO_CPU_NO_ERROR) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "adi_apollo_sysclk_cond_cal response = %d", sysclk_cond_resp.status); + err = API_CMS_ERROR_ERROR; + goto end; + } + else { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_API, "End clock conditioning: OK"); + } + +end: + return err; +} + +int32_t adi_apollo_sysclk_cond_bg_cal_start(adi_apollo_device_t* device) +{ + int32_t err; + adi_apollo_mailbox_resp_sysclk_conditioning_t sysclk_cond_resp; + adi_apollo_mailbox_cmd_sysclk_conditioning_t cc_cmd; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + cc_cmd.clk_path_segment = APOLLO_SYSCLK_START_BG_CAL; + if (err = adi_apollo_mailbox_sysclk_conditioning(device, &cc_cmd, &sysclk_cond_resp), err != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "adi_apollo_mailbox_sysclk_conditioning returned err = %d", err); + } + if (sysclk_cond_resp.status != APOLLO_CPU_NO_ERROR) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "adi_apollo_sysclk_bg_cond_caldata_start_validate response = %d", sysclk_cond_resp.status); + err = API_CMS_ERROR_ERROR; + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_sysclk_cond_bg_cal_stop(adi_apollo_device_t* device) +{ + int32_t err; + adi_apollo_mailbox_resp_sysclk_conditioning_t sysclk_cond_resp; + adi_apollo_mailbox_cmd_sysclk_conditioning_t cc_cmd; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + cc_cmd.clk_path_segment = APOLLO_SYSCLK_STOP_BG_CAL; + if (err = adi_apollo_mailbox_sysclk_conditioning(device, &cc_cmd, &sysclk_cond_resp), err != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "adi_apollo_mailbox_sysclk_conditioning returned err = %d", err); + } + if (sysclk_cond_resp.status != APOLLO_CPU_NO_ERROR) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "adi_apollo_sysclk_bg_cond_caldata_stop_validate response = %d", sysclk_cond_resp.status); + err = API_CMS_ERROR_ERROR; + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_sysclk_cond_bg_cal_resume(adi_apollo_device_t* device) +{ + int32_t err; + adi_apollo_mailbox_resp_sysclk_conditioning_t sysclk_cond_resp; + adi_apollo_mailbox_cmd_sysclk_conditioning_t cc_cmd; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + cc_cmd.clk_path_segment = APOLLO_SYSCLK_RESUME_BG_CAL; + if (err = adi_apollo_mailbox_sysclk_conditioning(device, &cc_cmd, &sysclk_cond_resp), err != API_CMS_ERROR_OK) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "adi_apollo_mailbox_sysclk_conditioning returned err = %d", err); + } + if (sysclk_cond_resp.status != APOLLO_CPU_NO_ERROR) { + adi_apollo_hal_log_write(device, ADI_CMS_LOG_ERR, "adi_apollo_sysclk_bg_cond_caldata_resume_validate response = %d", sysclk_cond_resp.status); + err = API_CMS_ERROR_ERROR; + } + + return API_CMS_ERROR_OK; +} +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_tmode.c b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_tmode.c new file mode 100644 index 00000000000000..9eee51291e3c9d --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_tmode.c @@ -0,0 +1,185 @@ +/*! + * \brief APIs for JESD Tx (JTx) + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_TMODE + * @{ + */ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_tmode.h" +#include "adi_apollo_jtx.h" +#include "adi_apollo_dformat.h" +#include "adi_apollo_dformat_local.h" +#include "adi_apollo_tmode_local.h" + +#include "adi_apollo_bf_jtx_dformat.h" +#include "adi_apollo_bf_jtx_dual_link.h" +#include "adi_apollo_bf_jtx_qbf_txfe.h" +#include "adi_apollo_bf_serdes_txdig_phy_core1p2.h" + +#include "adi_apollo_config.h" +#include "adi_apollo_hal.h" + +/*==================== P U B L I C A P I C O D E ====================*/ + +int32_t adi_apollo_tmode_config_set(adi_apollo_device_t *device, + const uint16_t links, + const uint8_t converter_mask, + adi_apollo_rx_tmode_type_sel_e mode, + adi_apollo_rx_tmode_res_e res) + +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + ADI_CMS_RANGE_CHECK(res, ADI_APOLLO_RX_TMODE_RES_16B, ADI_APOLLO_RX_TMODE_RES_12B); + ADI_CMS_RANGE_CHECK(mode, ADI_APOLLO_TMODE_TYPE_SEL_NORM, ADI_APOLLO_TMODE_TYPE_SEL_RAMP); + + /* set test mode converters */ + err = adi_apollo_dformat_conv_test_mode_enable_set(device, links, converter_mask); + ADI_APOLLO_ERROR_RETURN(err); + + /* set JTx output resolution */ + err = adi_apollo_dformat_res_sel_set(device, links, res); + ADI_APOLLO_ERROR_RETURN(err); + + /* Set ADC TMODE block res */ + adi_apollo_tmode_resolution_set(device, links, res); + + /* set test mode type */ + err = adi_apollo_tmode_type_sel_set(device, links, mode); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_tmode_usr_pattern_set(adi_apollo_device_t *device, + const uint16_t links, + uint16_t usr_pattern[], + uint32_t length) +{ + int32_t err, i, j, k; + int32_t pat_addr_offset_lsb[ADI_APOLLO_TMODE_USR_PAT_NUM], + pat_addr_offset_msb[ADI_APOLLO_TMODE_USR_PAT_NUM]; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(length > ADI_APOLLO_TMODE_USR_PAT_NUM); + + /* Generating address offsets for User Pattern indices */ + + pat_addr_offset_lsb[0] = REG_TMODE_USR_LSB_P0_JTX_DFORMAT_ADDR(0, 0) - REG_TMODE_USR_LSB_P0_JTX_DFORMAT_ADDR(0, 0); + pat_addr_offset_lsb[1] = REG_TMODE_USR_LSB_P1_JTX_DFORMAT_ADDR(0, 0) - REG_TMODE_USR_LSB_P0_JTX_DFORMAT_ADDR(0, 0); + pat_addr_offset_lsb[2] = REG_TMODE_USR_LSB_P2_JTX_DFORMAT_ADDR(0, 0) - REG_TMODE_USR_LSB_P1_JTX_DFORMAT_ADDR(0, 0); + pat_addr_offset_lsb[3] = REG_TMODE_USR_LSB_P3_JTX_DFORMAT_ADDR(0, 0) - REG_TMODE_USR_LSB_P2_JTX_DFORMAT_ADDR(0, 0); + pat_addr_offset_lsb[4] = REG_TMODE_USR_LSB_P4_JTX_DFORMAT_ADDR(0, 0) - REG_TMODE_USR_LSB_P3_JTX_DFORMAT_ADDR(0, 0); + pat_addr_offset_lsb[5] = REG_TMODE_USR_LSB_P5_JTX_DFORMAT_ADDR(0, 0) - REG_TMODE_USR_LSB_P4_JTX_DFORMAT_ADDR(0, 0); + pat_addr_offset_lsb[6] = REG_TMODE_USR_LSB_P6_JTX_DFORMAT_ADDR(0, 0) - REG_TMODE_USR_LSB_P5_JTX_DFORMAT_ADDR(0, 0); + pat_addr_offset_lsb[7] = REG_TMODE_USR_LSB_P7_JTX_DFORMAT_ADDR(0, 0) - REG_TMODE_USR_LSB_P6_JTX_DFORMAT_ADDR(0, 0); + + pat_addr_offset_msb[0] = REG_TMODE_USR_MSB_P0_JTX_DFORMAT_ADDR(0, 0) - REG_TMODE_USR_MSB_P0_JTX_DFORMAT_ADDR(0, 0); + pat_addr_offset_msb[1] = REG_TMODE_USR_MSB_P1_JTX_DFORMAT_ADDR(0, 0) - REG_TMODE_USR_MSB_P0_JTX_DFORMAT_ADDR(0, 0); + pat_addr_offset_msb[2] = REG_TMODE_USR_MSB_P2_JTX_DFORMAT_ADDR(0, 0) - REG_TMODE_USR_MSB_P1_JTX_DFORMAT_ADDR(0, 0); + pat_addr_offset_msb[3] = REG_TMODE_USR_MSB_P3_JTX_DFORMAT_ADDR(0, 0) - REG_TMODE_USR_MSB_P2_JTX_DFORMAT_ADDR(0, 0); + pat_addr_offset_msb[4] = REG_TMODE_USR_MSB_P4_JTX_DFORMAT_ADDR(0, 0) - REG_TMODE_USR_MSB_P3_JTX_DFORMAT_ADDR(0, 0); + pat_addr_offset_msb[5] = REG_TMODE_USR_MSB_P5_JTX_DFORMAT_ADDR(0, 0) - REG_TMODE_USR_MSB_P4_JTX_DFORMAT_ADDR(0, 0); + pat_addr_offset_msb[6] = REG_TMODE_USR_MSB_P6_JTX_DFORMAT_ADDR(0, 0) - REG_TMODE_USR_MSB_P5_JTX_DFORMAT_ADDR(0, 0); + pat_addr_offset_msb[7] = REG_TMODE_USR_MSB_P7_JTX_DFORMAT_ADDR(0, 0) - REG_TMODE_USR_MSB_P6_JTX_DFORMAT_ADDR(0, 0); + + for (k = 1; k < length; k ++) { + pat_addr_offset_lsb[k] = pat_addr_offset_lsb[k] + pat_addr_offset_lsb[k-1]; + pat_addr_offset_msb[k] = pat_addr_offset_msb[k] + pat_addr_offset_msb[k-1]; + } + + /* Writing user pattern data to registers */ + for (i = 0; i < ADI_APOLLO_NUM_JTX_LINKS; i++) { + if ((1 << i) & links) { + + regmap_base_addr = calc_jtx_dformat_base(i); + + for (j = 0; j < length; j ++) { + + err = adi_apollo_hal_reg_set(device, REG_TMODE_USR_LSB_P0_JTX_DFORMAT_ADDR(regmap_base_addr, (i % ADI_APOLLO_TMODE_N)) + pat_addr_offset_lsb[j], + (uint8_t)usr_pattern[j]); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_reg_set(device, REG_TMODE_USR_MSB_P0_JTX_DFORMAT_ADDR(regmap_base_addr, (i % ADI_APOLLO_TMODE_N)) + pat_addr_offset_msb[j], + (uint8_t)(usr_pattern[j] >> 8)); + ADI_APOLLO_ERROR_RETURN(err); + } + } + } + + return API_CMS_ERROR_OK; +} + +/*==================== L O C A L A P I C O D E ====================*/ + + +int32_t adi_apollo_tmode_type_sel_set(adi_apollo_device_t *device, + const uint16_t links, + adi_apollo_rx_tmode_type_sel_e mode) +{ + int32_t err, i; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + for (i = 0; i < ADI_APOLLO_NUM_JTX_LINKS; i ++) { + if ((1 << i) & links) { + + regmap_base_addr = calc_jtx_dformat_base(i); + + if ((i % ADI_APOLLO_TMODE_N) == 0) { + err = adi_apollo_hal_bf_set(device, BF_TMODE_TYPE_SEL_INFO(regmap_base_addr), mode); /* Link 0 */ + ADI_APOLLO_ERROR_RETURN(err); + } else { + err = adi_apollo_hal_bf_set(device, BF_TMODE_TYPE_SEL_LINK1_INFO(regmap_base_addr), mode); /* Link 1 */ + ADI_APOLLO_ERROR_RETURN(err); + } + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_tmode_resolution_set(adi_apollo_device_t *device, + const uint16_t links, + adi_apollo_rx_tmode_res_e res) +{ + int32_t err, i; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + for (i = 0; i < ADI_APOLLO_NUM_JTX_LINKS; i ++) { + if ((1 << i) & links) { + regmap_base_addr = calc_jtx_dformat_base(i); + + if ((i % ADI_APOLLO_TMODE_N) == 0) { + err = adi_apollo_hal_bf_set(device, BF_TMODE_RES_INFO(regmap_base_addr), res); /* Link 0 */ + ADI_APOLLO_ERROR_RETURN(err); + } else { + err = adi_apollo_hal_bf_set(device, BF_TMODE_RES_LINK1_INFO(regmap_base_addr), res); /* Link 1 */ + ADI_APOLLO_ERROR_RETURN(err); + } + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} +/*! @} */ \ No newline at end of file diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_tmode_local.h b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_tmode_local.h new file mode 100644 index 00000000000000..123d7717978f6b --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_tmode_local.h @@ -0,0 +1,35 @@ +/*! + * \brief Apollo TMODE functional block local defines and prototypes + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_DFORMAT + * @{ + */ +#ifndef __ADI_APOLLO_TMODE_LOCAL_H__ +#define __ADI_APOLLO_TMODE_LOCAL_H__ + + +/*============= I N C L U D E S ============*/ + +/*============= D E F I N E S ==============*/ +#define ADI_APOLLO_TMODE_N 2 /*!< 2 TMODE instances. One per link. */ + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + + + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_TMODE_LOCAL_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_trigts.c b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_trigts.c new file mode 100644 index 00000000000000..7e40744d777d0a --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_trigts.c @@ -0,0 +1,973 @@ +/*! + * \brief APIs for TRIGGER & TIMESTAMP + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_TRIGGER + * @{ + */ + +/*============= I N C L U D E S ============*/ +#include "adi_utils.h" +#include "adi_apollo_trigts.h" +#include "adi_apollo_trigts_local.h" +#include "adi_apollo_reconfig_local.h" +#include "adi_apollo_cnco_types.h" +#include "adi_apollo_fnco_types.h" +#include "adi_apollo_cddc_types.h" +#include "adi_apollo_fddc_types.h" +#include "adi_apollo_pfilt_types.h" +#include "adi_apollo_cfir_types.h" +#include "adi_apollo_bmem_types.h" +#include "adi_apollo_clk_mcs.h" +#include "adi_apollo_private_blk_sel_types.h" + +#include "adi_apollo_bf_txrx_trigger_ts.h" +#include "adi_apollo_bf_txrx_prefsrc_reconf.h" + +#include "adi_apollo_config.h" +#include "adi_apollo_hal.h" + +/* Struct used for addressing functional block trig sel muxes */ +typedef struct { + uint32_t reg_base_addr; + uint32_t bf_info; +} reg_bf_info_map_t; + +/* Maps CNCO functional blocks to associated trig master select */ +static uint32_t calc_cnco_trig_mst_num(uint8_t cnco_index); + +/* Maps FNCO functional blocks to associated trig master select */ +static uint32_t calc_fnco_trig_mst_num(uint8_t fnco_index); + +/* Maps PFILT functional blocks to associated trig master select */ +static uint32_t calc_pfilt_trig_mst_num(uint8_t pfilt_index); + +/* Maps CFIR functional blocks to associated trig master select */ +static uint32_t calc_cfir_trig_mst_num(uint8_t cfir_index); + +/* Trigger sel mux register and bf info */ +static reg_bf_info_map_t *calc_cdrc_trig_sel_mux(adi_apollo_terminal_e terminal, uint8_t cnco_idx); +static reg_bf_info_map_t *calc_fdrc_trig_sel_mux(adi_apollo_terminal_e terminal, uint8_t fnco_idx); +static reg_bf_info_map_t *calc_bmem_trig_sel_mux(adi_apollo_terminal_e terminal, uint8_t bmem_idx); +static reg_bf_info_map_t *calc_pfilt_trig_sel_mux(adi_apollo_terminal_e terminal, uint8_t pfilt_idx); +static reg_bf_info_map_t *calc_cfir_trig_sel_mux(adi_apollo_terminal_e terminal, uint8_t cfir_idx); + +/* Utility for converting a functional block select index to its associated trig mst sel*/ +static uint32_t fb_sel_to_tm_sel(uint32_t(*fb2tm_fp)(uint8_t), uint32_t fb_sel, uint8_t fb_sel_per_side, uint16_t fb_sel_side_offset); + +/*==================== P U B L I C A P I C O D E ====================*/ +int32_t adi_apollo_trigts_mst_config(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_side_select_e side_sel, + uint32_t trig_msts, adi_apollo_trig_mst_config_t *config) +{ + int32_t err; + uint8_t i, side, side_index, trig_index; + uint32_t trig_mst; + uint8_t byte_array[8]; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(config); + + for (side_index = 0; side_index < ADI_APOLLO_NUM_SIDES; side_index++) { + side = side_sel & (ADI_APOLLO_SIDE_A << side_index); + if (side > 0) { + regmap_base_addr = calc_trigts_base(terminal, side_index); + + /* Set reg_map base address for subsequent paged writes */ + adi_apollo_hal_paged_base_addr_set(device, regmap_base_addr); + + for (trig_index = 0; trig_index < ADI_APOLLO_NUM_TRIG_MASTER_PER_SIDE; trig_index++) { + trig_mst = trig_msts & (ADI_APOLLO_TRIG_MST_CNCO_0 << trig_index); + + if (trig_mst > 0) { + + /* Trigger enable */ + // err = adi_apollo_hal_bf_set(device, BF_TRIG_EN_INFO(regmap_base_addr, trig_index), config->trig_enable); + err = adi_apollo_hal_paged_bf_set(device, BF_TRIG_EN_INFO(regmap_base_addr, trig_index), config->trig_enable); + ADI_APOLLO_ERROR_RETURN(err); + + /* Trigger offset (registers have a stride of 32) */ + adi_uint64_to_byte_array(byte_array, config->trig_offset); + for (i=0; i<8; i++) { + // adi_apollo_hal_reg_set(device, REG_TRIG_OFFSET0_ADDR(regmap_base_addr, trig_index) + i*32, byte_array[i]); /* not paged */ + adi_apollo_hal_paged_reg_set(device, REG_TRIG_OFFSET0_ADDR(regmap_base_addr, trig_index) + i*32, byte_array[i]); + ADI_APOLLO_ERROR_RETURN(err); + } + + /* Trigger period (registers have a stride of 32) */ + adi_uint64_to_byte_array(byte_array, config->trig_period); + for (i=0; i<8; i++) { + // adi_apollo_hal_reg_set(device, REG_TRIG_PERIOD0_ADDR(regmap_base_addr, trig_index) + i*32, byte_array[i]); /* not paged */ + adi_apollo_hal_paged_reg_set(device, REG_TRIG_PERIOD0_ADDR(regmap_base_addr, trig_index) + i*32, byte_array[i]); + ADI_APOLLO_ERROR_RETURN(err); + } + + } + } + } + } + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_trigts_mst_inspect(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_side_select_e side_sel, + uint32_t trig_msts, adi_apollo_trig_mst_config_t *config) +{ + int32_t err; + uint8_t i, side, side_index, trig_index; + uint32_t trig_mst; + uint8_t val_u64[8]; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(config); + ADI_APOLLO_INVALID_PARAM_RETURN(adi_api_utils_num_selected(side_sel) != 1); + + for (side_index = 0; side_index < ADI_APOLLO_NUM_SIDES; side_index++) { + side = side_sel & (ADI_APOLLO_SIDE_A << side_index); + if (side > 0) { + regmap_base_addr = calc_trigts_base(terminal, side_index); + + for (trig_index = 0; trig_index < ADI_APOLLO_NUM_TRIG_MASTER_PER_SIDE; trig_index++) { + trig_mst = trig_msts & (ADI_APOLLO_TRIG_MST_CNCO_0 << trig_index); + + if (trig_mst > 0) { + + /* Trigger enable */ + err = adi_apollo_hal_bf_get(device, BF_TRIG_EN_INFO(regmap_base_addr, trig_index), (uint8_t *) &config->trig_enable, sizeof(config->trig_enable)); + ADI_APOLLO_ERROR_RETURN(err); + + /* Trigger offset (registers have a stride of 32) */ + for (i=0; i<8; i++) { + adi_apollo_hal_reg_get(device, REG_TRIG_PERIOD0_ADDR(regmap_base_addr, trig_index) + i*32, &val_u64[i]); + } + adi_byte_array_to_uint64(val_u64, &config->trig_period); + + /* Trigger period (registers have a stride of 32) */ + for (i=0; i<8; i++) { + adi_apollo_hal_reg_get(device, REG_TRIG_OFFSET0_ADDR(regmap_base_addr, trig_index) + i*32, &val_u64[i]); + } + adi_byte_array_to_uint64(val_u64, &config->trig_offset); + + // Can only return one trig mst config at time + return API_CMS_ERROR_OK; + } + } + } + } + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_trigts_mst_mute(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_side_select_e side_sel, + uint32_t trig_msts, adi_apollo_trig_mute_sel_e trigger_mute) +{ + int32_t err; + uint8_t side, side_index, trig_index; + uint32_t trig_mst; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + for (side_index = 0; side_index < ADI_APOLLO_NUM_SIDES; side_index++) { + side = side_sel & (ADI_APOLLO_SIDE_A << side_index); + if (side > 0) { + regmap_base_addr = calc_trigts_base(terminal, side_index); + + for (trig_index = 0; trig_index < ADI_APOLLO_NUM_TRIG_MASTER_PER_SIDE; trig_index++) { + trig_mst = trig_msts & (ADI_APOLLO_TRIG_MST_CNCO_0 << trig_index); + if (trig_mst > 0) { + err = adi_apollo_hal_bf_set(device, BF_MUTE_TRIG_INFO(regmap_base_addr, trig_index), trigger_mute); + ADI_APOLLO_ERROR_RETURN(err); + } + } + } + } + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_trigts_mst_mute_mask_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_side_select_e side_sel, + uint32_t trig_msts, adi_apollo_trig_mute_mask_e trigger_mute) +{ + int32_t err; + uint8_t side, side_index, trig_index; + uint32_t trig_mst; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(trigger_mute > ADI_APOLLO_TRIG_MUTE_MASK_1); + + for (side_index = 0; side_index < ADI_APOLLO_NUM_SIDES; side_index++) { + side = side_sel & (ADI_APOLLO_SIDE_A << side_index); + if (side > 0) { + regmap_base_addr = calc_trigts_base(terminal, side_index); + + for (trig_index = 0; trig_index < ADI_APOLLO_NUM_TRIG_MASTER_PER_SIDE; trig_index++) { + trig_mst = trig_msts & (ADI_APOLLO_TRIG_MST_CNCO_0 << trig_index); + if (trig_mst > 0) { + err = adi_apollo_hal_bf_set(device, BF_TRIG_MASK_COUNT_INFO(regmap_base_addr, trig_index), trigger_mute); + ADI_APOLLO_ERROR_RETURN(err); + } + } + } + } + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_trigts_mst_mute_mask_count_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_side_select_e side_sel, + adi_apollo_trig_mute_mask_e trigger_mute, adi_apollo_trig_mst_sel_e trig_mst, uint16_t pulse_count) +{ + int32_t err; + uint8_t side, side_index; + uint32_t regmap_base_addr = 0; + uint32_t trig = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(trigger_mute == ADI_APOLLO_TRIG_MUTE_MASK_DISABLE); + ADI_APOLLO_INVALID_PARAM_RETURN(adi_api_utils_num_selected(trig_mst) != 1); + + trig = adi_api_utils_select_lsb_get(trig_mst); + + for (side_index = 0; side_index < ADI_APOLLO_NUM_SIDES; side_index++) { + side = side_sel & (ADI_APOLLO_SIDE_A << side_index); + if (side > 0) { + regmap_base_addr = calc_trigts_base(terminal, side_index); + if (trigger_mute == ADI_APOLLO_TRIG_MUTE_MASK_0) { + err = adi_apollo_hal_bf_set(device, BF_COUNT0_REG0_INFO(regmap_base_addr), pulse_count); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_COUNT0_REG1_INFO(regmap_base_addr), pulse_count >> 8); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_TM_SEL0_INFO(regmap_base_addr), trig); + ADI_APOLLO_ERROR_RETURN(err); + } else { + err = adi_apollo_hal_bf_set(device, BF_COUNT1_REG0_INFO(regmap_base_addr), pulse_count); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_COUNT1_REG1_INFO(regmap_base_addr), pulse_count >> 8); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_TM_SEL1_INFO(regmap_base_addr), trig); + ADI_APOLLO_ERROR_RETURN(err); + } + } + } + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_trigts_reconfig_trig_sel_mux_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_side_select_e side_sel, + adi_apollo_trigger_sel_mux_e trig_sel) +{ + int32_t err; + uint8_t side, side_index; + uint32_t regmap_base_addr = 0; + + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + for (side_index = 0; side_index < ADI_APOLLO_NUM_SIDES; side_index++) { + side = side_sel & (ADI_APOLLO_SIDE_A << side_index); + if (side > 0) { + regmap_base_addr = calc_trigts_base(terminal, side_index); + + err = adi_apollo_hal_bf_set(device, BF_TRIG_SEL_MUX_RECONFIG_INFO(regmap_base_addr), trig_sel); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_trigts_cdrc_trig_sel_mux_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t cdrcs, adi_apollo_trigger_sel_mux_e trig_sel) +{ + int32_t err; + uint8_t i; + adi_apollo_blk_sel_t cdrc; + reg_bf_info_map_t *reg_bfinfo; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_CNCO_BLK_SEL_MASK(cdrcs); + + for(i = 0; i < ADI_APOLLO_CNCO_NUM; i ++) { + cdrc = cdrcs & (ADI_APOLLO_CNCO_A0 << i); + if (cdrc > 0) { + reg_bfinfo = calc_cdrc_trig_sel_mux(terminal, i); + + err = adi_apollo_hal_bf_set(device, reg_bfinfo->reg_base_addr, reg_bfinfo->bf_info, trig_sel); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_trigts_fdrc_trig_sel_mux_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t fdrcs, adi_apollo_trigger_sel_mux_e trig_sel) +{ + int32_t err; + uint8_t i; + adi_apollo_blk_sel_t fdrc; + reg_bf_info_map_t *reg_bfinfo; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_FNCO_BLK_SEL_MASK(fdrcs); + + for(i = 0; i < ADI_APOLLO_FNCO_NUM; i ++) { + fdrc = fdrcs & (ADI_APOLLO_FNCO_A0 << i); + if (fdrc > 0) { + reg_bfinfo = calc_fdrc_trig_sel_mux(terminal, i); + + err = adi_apollo_hal_bf_set(device, reg_bfinfo->reg_base_addr, reg_bfinfo->bf_info, trig_sel); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_trigts_bmem_trig_sel_mux_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t bmems, adi_apollo_trigger_sel_mux_e trig_sel) +{ + int32_t err; + uint8_t i; + adi_apollo_blk_sel_t bmem; + reg_bf_info_map_t *reg_bfinfo; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_BMEM_BLK_SEL_MASK(bmems); + + for(i = 0; i < ADI_APOLLO_BMEM_NUM; i ++) { + bmem = bmems & (ADI_APOLLO_BMEM_A0 << i); + if (bmem > 0) { + reg_bfinfo = calc_bmem_trig_sel_mux(terminal, i); + + err = adi_apollo_hal_bf_set(device, reg_bfinfo->reg_base_addr, reg_bfinfo->bf_info, trig_sel); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_trigts_pfilt_trig_sel_mux_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t pfilts, adi_apollo_trigger_sel_mux_e trig_sel) +{ + int32_t err; + uint8_t i; + adi_apollo_blk_sel_t pfilt; + reg_bf_info_map_t *reg_bfinfo; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_PFILT_BLK_SEL_MASK(pfilts); + + for(i = 0; i < ADI_APOLLO_PFILT_NUM; i ++) { + pfilt = pfilts & (ADI_APOLLO_PFILT_A0 << i); + if (pfilt > 0) { + reg_bfinfo = calc_pfilt_trig_sel_mux(terminal, i); + + err = adi_apollo_hal_bf_set(device, reg_bfinfo->reg_base_addr, reg_bfinfo->bf_info, trig_sel); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_trigts_cfir_trig_sel_mux_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t cfirs, adi_apollo_trigger_sel_mux_e trig_sel) +{ + int32_t err; + uint8_t i; + adi_apollo_blk_sel_t cfir; + reg_bf_info_map_t *reg_bfinfo; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_CFIR_BLK_SEL_MASK(cfirs); + + for(i = 0; i < ADI_APOLLO_PFILT_NUM; i ++) { + cfir = cfirs & (ADI_APOLLO_PFILT_A0 << i); + if (cfir > 0) { + reg_bfinfo = calc_cfir_trig_sel_mux(terminal, i); + + err = adi_apollo_hal_bf_set(device, reg_bfinfo->reg_base_addr, reg_bfinfo->bf_info, trig_sel); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_trigts_trig_now(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_side_select_e side_sel) +{ + int32_t err; + uint8_t side, side_index; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + for (side_index = 0; side_index < ADI_APOLLO_NUM_SIDES; side_index++) { + side = side_sel & (ADI_APOLLO_SIDE_A << side_index); + if (side > 0) { + regmap_base_addr = calc_trigts_base(terminal, side_index); + + // A low-to-high transition spi_trig + err = adi_apollo_hal_reg_set(device, REG_SPI_TRIG_ADDR(regmap_base_addr), 0); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_reg_set(device, REG_SPI_TRIG_ADDR(regmap_base_addr), 1); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_trigts_counter_get(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_side_select_e side_sel, uint64_t *val) +{ + int32_t err; + uint8_t side, side_index; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(val); + ADI_APOLLO_INVALID_PARAM_RETURN(adi_api_utils_num_selected(side_sel) != 1); + + for (side_index = 0; side_index < ADI_APOLLO_NUM_SIDES; side_index++) { + side = side_sel & (ADI_APOLLO_SIDE_A << side_index); + if (side > 0) { + regmap_base_addr = calc_trigts_base(terminal, side_index); + + /* Latch 64-bit timestamp counter*/ + err = adi_apollo_hal_bf_set(device, BF_TIMESTAMP_READ_EN_TXRX_TRIGGER_TS_INFO(regmap_base_addr), 0); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_TIMESTAMP_READ_EN_TXRX_TRIGGER_TS_INFO(regmap_base_addr), 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_TIMESTAMP_READ_EN_TXRX_TRIGGER_TS_INFO(regmap_base_addr), 0); + ADI_APOLLO_ERROR_RETURN(err); + + /* Read the 64-bit counter value */ + err = adi_apollo_hal_bf_get(device, BF_TIMESTAMP_STATUS_TXRX_TRIGGER_TS_INFO(regmap_base_addr), (uint8_t *)val, sizeof(*val)); + ADI_APOLLO_ERROR_RETURN(err); + + /* Only single value returned */ + break; + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_trigts_cnco_trig_mst_config(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t cncos, adi_apollo_trig_mst_config_t *config) +{ + int32_t err; + uint32_t trig_msts; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(config); + + /* Configure cnco trigger masters for Side A */ + trig_msts = fb_sel_to_tm_sel(calc_cnco_trig_mst_num, cncos, ADI_APOLLO_CDDC_PER_SIDE_NUM, ADI_APOLLO_CDDC_A0); + if (trig_msts > 0){ + err = adi_apollo_trigts_mst_config(device, terminal, ADI_APOLLO_SIDE_A, trig_msts, config); + ADI_APOLLO_ERROR_RETURN(err); + } + + /* Configure cnco trigger masters for Side B */ + trig_msts = fb_sel_to_tm_sel(calc_cnco_trig_mst_num, cncos, ADI_APOLLO_CDDC_PER_SIDE_NUM, ADI_APOLLO_CDDC_B0); + if (trig_msts > 0){ + err = adi_apollo_trigts_mst_config(device, terminal, ADI_APOLLO_SIDE_B, trig_msts, config); + ADI_APOLLO_ERROR_RETURN(err); + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_trigts_fnco_trig_mst_config(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t fncos, adi_apollo_trig_mst_config_t *config) +{ + int32_t err; + uint32_t trig_msts = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(config); + + /* Configure fnco trigger masters for Side A */ + trig_msts = fb_sel_to_tm_sel(calc_fnco_trig_mst_num, fncos, ADI_APOLLO_FDDC_PER_SIDE_NUM, ADI_APOLLO_FDDC_A0); + if (trig_msts > 0){ + err = adi_apollo_trigts_mst_config(device, terminal, ADI_APOLLO_SIDE_A, trig_msts, config); + ADI_APOLLO_ERROR_RETURN(err); + } + + /* Configure fnco trigger masters for Side B */ + trig_msts = fb_sel_to_tm_sel(calc_fnco_trig_mst_num, fncos, ADI_APOLLO_FDDC_PER_SIDE_NUM, ADI_APOLLO_FDDC_B0); + if (trig_msts > 0){ + err = adi_apollo_trigts_mst_config(device, terminal, ADI_APOLLO_SIDE_B, trig_msts, config); + ADI_APOLLO_ERROR_RETURN(err); + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_trigts_pfilt_trig_mst_config(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t pfilts, adi_apollo_trig_mst_config_t *config) +{ + int32_t err; + uint32_t trig_msts; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(config); + + /* Configure pfilt trigger masters for Side A */ + trig_msts = fb_sel_to_tm_sel(calc_pfilt_trig_mst_num, pfilts, ADI_APOLLO_PFILT_PER_SIDE, ADI_APOLLO_PFILT_A0); + if (trig_msts > 0) { + err = adi_apollo_trigts_mst_config(device, terminal, ADI_APOLLO_SIDE_A, trig_msts, config); + ADI_APOLLO_ERROR_RETURN(err); + } + + /* Configure PFILT trigger masters for Side B */ + trig_msts = fb_sel_to_tm_sel(calc_pfilt_trig_mst_num, pfilts, ADI_APOLLO_PFILT_PER_SIDE, ADI_APOLLO_PFILT_B0); + if (trig_msts > 0) { + err = adi_apollo_trigts_mst_config(device, terminal, ADI_APOLLO_SIDE_B, trig_msts, config); + ADI_APOLLO_ERROR_RETURN(err); + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_trigts_cfir_trig_mst_config(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_blk_sel_t cfirs, adi_apollo_trig_mst_config_t *config) +{ + int32_t err; + uint32_t trig_msts; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(config); + + /* Configure cfir trigger masters for Side A */ + trig_msts = fb_sel_to_tm_sel(calc_cfir_trig_mst_num, cfirs, ADI_APOLLO_CFIRS_PER_SIDE, ADI_APOLLO_CFIR_A0); + if (trig_msts > 0) { + err = adi_apollo_trigts_mst_config(device, terminal, ADI_APOLLO_SIDE_A, trig_msts, config); + ADI_APOLLO_ERROR_RETURN(err); + } + + /* Configure CFIR trigger masters for Side B */ + trig_msts = fb_sel_to_tm_sel(calc_cfir_trig_mst_num, cfirs, ADI_APOLLO_CFIRS_PER_SIDE, ADI_APOLLO_CFIR_B0); + if (trig_msts > 0) { + err = adi_apollo_trigts_mst_config(device, terminal, ADI_APOLLO_SIDE_B, trig_msts, config); + ADI_APOLLO_ERROR_RETURN(err); + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_trigts_reconfig_trig_mst_config(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, adi_apollo_side_select_e side_sel, + adi_apollo_trig_mst_config_t *config) +{ + return adi_apollo_trigts_mst_config(device, terminal, side_sel, ADI_APOLLO_TRIG_MST_RECONFIG, config); +} + +int32_t adi_apollo_trigts_ts_reset_mode_set(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, uint16_t side_sel, adi_apollo_trig_ts_reset_mode_e mode) +{ + int32_t err; + uint8_t side_index; + uint16_t side; + uint32_t regmap_base_addr = 0; + uint32_t prefsrc_regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + for (side_index = 0; side_index < ADI_APOLLO_NUM_SIDES; side_index++) { + side = side_sel & (ADI_APOLLO_SIDE_A << side_index); + if (side > 0) { + regmap_base_addr = calc_trigts_base(terminal, side_index); + + // Set the timestamp reset mode: SYSREF or SPI based + err = adi_apollo_hal_bf_set(device, BF_TS_RST_MODE_TXRX_TRIGGER_TS_INFO(regmap_base_addr), mode); + ADI_APOLLO_ERROR_RETURN(err); + + // Clear reset done status for selected timestamp instance + err = adi_apollo_hal_bf_set(device, BF_RST_DONE_CLR_TXRX_TRIGGER_TS_INFO(regmap_base_addr), 0); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_RST_DONE_CLR_TXRX_TRIGGER_TS_INFO(regmap_base_addr), 1); + ADI_APOLLO_ERROR_RETURN(err); + + if (mode == ADI_APOLLO_TRIG_TS_RESET_MODE_SYSREF) { + prefsrc_regmap_base_addr = calc_prefsrc_reconfig_base(terminal, side_index); + + // Enable timestamp reset on sync event (timestamp_reset_en requires 0->1 transition to set) + err = adi_apollo_hal_bf_set(device, BF_TIMESTAMP_RESET_EN_INFO(prefsrc_regmap_base_addr), 0); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_TIMESTAMP_RESET_EN_INFO(prefsrc_regmap_base_addr), 1); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_NONRESYNC_SYSREF_EN_INFO(prefsrc_regmap_base_addr), 1); + ADI_APOLLO_ERROR_RETURN(err); + } + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_trigts_ts_reset(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, uint16_t side_sel, uint8_t sync) +{ + int32_t err; + uint8_t side_index; + uint16_t side; + uint8_t mode, sync_pending = 0; + uint32_t regmap_base_addr = 0; + uint32_t prefsrc_regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + for (side_index = 0; side_index < ADI_APOLLO_NUM_SIDES; side_index++) { + side = side_sel & (ADI_APOLLO_SIDE_A << side_index); + if (side > 0) { + regmap_base_addr = calc_trigts_base(terminal, side_index); + + // Clear reset done status + err = adi_apollo_hal_bf_set(device, BF_RST_DONE_CLR_TXRX_TRIGGER_TS_INFO(regmap_base_addr), 0); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_RST_DONE_CLR_TXRX_TRIGGER_TS_INFO(regmap_base_addr), 1); + ADI_APOLLO_ERROR_RETURN(err); + + // Determine current timestamp reset mode + err = adi_apollo_hal_bf_get(device, BF_TS_RST_MODE_TXRX_TRIGGER_TS_INFO(regmap_base_addr), &mode, sizeof(mode)); + ADI_APOLLO_ERROR_RETURN(err); + + if (mode == ADI_APOLLO_TRIG_TS_RESET_MODE_SYSREF) { + // Reset timestamp counter via SYSREF/SYNC + prefsrc_regmap_base_addr = calc_prefsrc_reconfig_base(terminal, side_index); + + // Enable timestamp reset on sync event (timestamp_reset_en requires 0->1 transition to set) + err = adi_apollo_hal_bf_set(device, BF_TIMESTAMP_RESET_EN_INFO(prefsrc_regmap_base_addr), 0); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_TIMESTAMP_RESET_EN_INFO(prefsrc_regmap_base_addr), 1); + ADI_APOLLO_ERROR_RETURN(err); + + // Defer sync request until all timestamp block instances are configure (i.e. one trig does all) + sync_pending = sync; + } else { + // Reset timestamp counter via SPI + err = adi_apollo_hal_bf_set(device, BF_SPI_TS_RST_TXRX_TRIGGER_TS_INFO(regmap_base_addr), 0); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_SPI_TS_RST_TXRX_TRIGGER_TS_INFO(regmap_base_addr), 1); + ADI_APOLLO_ERROR_RETURN(err); + } + } + } + + if (sync_pending) { + err = adi_apollo_clk_mcs_sync_only_set(device); // dynamic sync (no SYSREF realignment) + ADI_APOLLO_ERROR_RETURN(err); + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_trigts_reset_done_clear(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, uint16_t side_sel) { + int32_t err; + uint8_t side_index; + uint16_t side; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + for (side_index = 0; side_index < ADI_APOLLO_NUM_SIDES; side_index++) { + side = side_sel & (ADI_APOLLO_SIDE_A << side_index); + if (side > 0) { + regmap_base_addr = calc_trigts_base(terminal, side_index); + + // Clear reset done + err = adi_apollo_hal_bf_set(device, BF_RST_DONE_CLR_TXRX_TRIGGER_TS_INFO(regmap_base_addr), 0); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_RST_DONE_CLR_TXRX_TRIGGER_TS_INFO(regmap_base_addr), 1); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_trigts_reset_done_get(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, uint16_t side_sel, uint8_t *reset_done_status) +{ + int32_t err; + uint8_t side_index; + uint16_t side; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_INVALID_PARAM_RETURN(adi_api_utils_num_selected(side_sel) != 1); + + for (side_index = 0; side_index < ADI_APOLLO_NUM_SIDES; side_index++) { + side = side_sel & (ADI_APOLLO_SIDE_A << side_index); + if (side > 0) { + regmap_base_addr = calc_trigts_base(terminal, side_index); + + err = adi_apollo_hal_bf_get(device, BF_RST_DONE_TXRX_TRIGGER_TS_INFO(regmap_base_addr), reset_done_status, sizeof(*reset_done_status)); + ADI_APOLLO_ERROR_RETURN(err); + + /* Only single value returned */ + break; + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_trigts_ext_trig_no_dr_setup(adi_apollo_device_t *device, adi_apollo_terminal_e terminal, uint16_t side_sel) +{ + int32_t err; + uint8_t side_index; + uint16_t side; + uint32_t prefsrc_regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_clk_mcs_trig_sync_enable(device, 1); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_clk_mcs_dig_clk_mask_set(device, 1); + ADI_APOLLO_ERROR_RETURN(err); + + for (side_index = 0; side_index < ADI_APOLLO_NUM_SIDES; side_index++) { + side = side_sel & (ADI_APOLLO_SIDE_A << side_index); + if (side > 0) { + prefsrc_regmap_base_addr = calc_prefsrc_reconfig_base(terminal, side_index); + + err = adi_apollo_hal_bf_set(device, BF_NONRESYNC_SYSREF_EN_INFO(prefsrc_regmap_base_addr), 1); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; + +} + +static uint32_t calc_cnco_trig_mst_num(uint8_t cnco_index) +{ + static uint32_t cnco_trig_mst_map[ADI_APOLLO_CDDC_PER_SIDE_NUM] = { + ADI_APOLLO_TRIG_MST_CNCO_0, ADI_APOLLO_TRIG_MST_CNCO_1, + ADI_APOLLO_TRIG_MST_CNCO_2, ADI_APOLLO_TRIG_MST_CNCO_3 + }; + return cnco_trig_mst_map[cnco_index]; +} + +static uint32_t calc_fnco_trig_mst_num(uint8_t fnco_index) +{ + static uint32_t fnco_trig_mst_map[ADI_APOLLO_FDDC_PER_SIDE_NUM] = { + ADI_APOLLO_TRIG_MST_FNCO_0, ADI_APOLLO_TRIG_MST_FNCO_1, + ADI_APOLLO_TRIG_MST_FNCO_2, ADI_APOLLO_TRIG_MST_FNCO_3, + ADI_APOLLO_TRIG_MST_FNCO_4, ADI_APOLLO_TRIG_MST_FNCO_5, + ADI_APOLLO_TRIG_MST_FNCO_6, ADI_APOLLO_TRIG_MST_FNCO_7 + }; + return fnco_trig_mst_map[fnco_index]; +} + +static uint32_t calc_pfilt_trig_mst_num(uint8_t pfilt_index) +{ + static uint32_t pfilt_trig_mst_map[ADI_APOLLO_PFILT_PER_SIDE] = { + ADI_APOLLO_TRIG_MST_PFILT0, ADI_APOLLO_TRIG_MST_PFILT1}; + return pfilt_trig_mst_map[pfilt_index]; +} + +static uint32_t calc_cfir_trig_mst_num(uint8_t cfir_index) +{ + static uint32_t cfir_trig_mst_map[ADI_APOLLO_CFIR_PER_SIDE_NUM] = { + ADI_APOLLO_TRIG_MST_CFIR0, ADI_APOLLO_TRIG_MST_CFIR1}; + return cfir_trig_mst_map[cfir_index]; +} + +static uint32_t fb_sel_to_tm_sel(uint32_t(*fb2tm_fp)(uint8_t), uint32_t fb_sel, uint8_t fb_sel_per_side, uint16_t fb_sel_side_offset) +{ + uint8_t i; + uint32_t fb, trig_msts = 0; + + // Determine the corresponding trigger master(tm) selects from a functional block(fb) select + for (i = 0; i < fb_sel_per_side; i ++) { + fb = fb_sel & (fb_sel_side_offset << i); + if (fb > 0) { + trig_msts |= fb2tm_fp(i); /* func block idx to trig mst bit sel */ + } + } + return trig_msts; +} + +static reg_bf_info_map_t *calc_cdrc_trig_sel_mux(adi_apollo_terminal_e terminal, uint8_t cnco_idx) +{ + static reg_bf_info_map_t cdrc_rx_trig_sel_mux[] = { + {BF_TRIG_SEL_MUX_CDRC0_INFO(TXRX_TRIGGER_TS_RX_DIGITAL0, 0)}, /* A0 */ + {BF_TRIG_SEL_MUX_CDRC0_INFO(TXRX_TRIGGER_TS_RX_DIGITAL0, 1)}, /* A1 */ + {BF_TRIG_SEL_MUX_CDRC1_INFO(TXRX_TRIGGER_TS_RX_DIGITAL0, 0)}, /* A2 */ + {BF_TRIG_SEL_MUX_CDRC1_INFO(TXRX_TRIGGER_TS_RX_DIGITAL0, 1)}, /* A3 */ + + {BF_TRIG_SEL_MUX_CDRC0_INFO(TXRX_TRIGGER_TS_RX_DIGITAL1, 0)}, /* B0 */ + {BF_TRIG_SEL_MUX_CDRC0_INFO(TXRX_TRIGGER_TS_RX_DIGITAL1, 1)}, /* B1 */ + {BF_TRIG_SEL_MUX_CDRC1_INFO(TXRX_TRIGGER_TS_RX_DIGITAL1, 0)}, /* B2 */ + {BF_TRIG_SEL_MUX_CDRC1_INFO(TXRX_TRIGGER_TS_RX_DIGITAL1, 1)} /* B3 */ + }; + + static reg_bf_info_map_t cdrc_tx_trig_sel_mux[] = { + {BF_TRIG_SEL_MUX_CDRC0_INFO(TXRX_TRIGGER_TS_TX_TOP_TX_DIGITAL0, 0)}, /* A0 */ + {BF_TRIG_SEL_MUX_CDRC0_INFO(TXRX_TRIGGER_TS_TX_TOP_TX_DIGITAL0, 1)}, /* A1 */ + {BF_TRIG_SEL_MUX_CDRC1_INFO(TXRX_TRIGGER_TS_TX_TOP_TX_DIGITAL0, 0)}, /* A2 */ + {BF_TRIG_SEL_MUX_CDRC1_INFO(TXRX_TRIGGER_TS_TX_TOP_TX_DIGITAL0, 1)}, /* A3 */ + + {BF_TRIG_SEL_MUX_CDRC0_INFO(TXRX_TRIGGER_TS_TX_TOP_TX_DIGITAL1, 0)}, /* B0 */ + {BF_TRIG_SEL_MUX_CDRC0_INFO(TXRX_TRIGGER_TS_TX_TOP_TX_DIGITAL1, 1)}, /* B1 */ + {BF_TRIG_SEL_MUX_CDRC1_INFO(TXRX_TRIGGER_TS_TX_TOP_TX_DIGITAL1, 0)}, /* B2 */ + {BF_TRIG_SEL_MUX_CDRC1_INFO(TXRX_TRIGGER_TS_TX_TOP_TX_DIGITAL1, 1)} /* B3 */ + }; + + return (terminal == ADI_APOLLO_RX) ? &cdrc_rx_trig_sel_mux[cnco_idx] : &cdrc_tx_trig_sel_mux[cnco_idx]; +} + +static reg_bf_info_map_t *calc_fdrc_trig_sel_mux(adi_apollo_terminal_e terminal, uint8_t fnco_idx) +{ + static reg_bf_info_map_t fdrc_rx_trig_sel_mux[] = { + {BF_TRIG_SEL_MUX_FDRC0_INFO(TXRX_TRIGGER_TS_RX_DIGITAL0, 0)}, /* A0 */ + {BF_TRIG_SEL_MUX_FDRC0_INFO(TXRX_TRIGGER_TS_RX_DIGITAL0, 1)}, /* A1 */ + {BF_TRIG_SEL_MUX_FDRC0_INFO(TXRX_TRIGGER_TS_RX_DIGITAL0, 2)}, /* A2 */ + {BF_TRIG_SEL_MUX_FDRC0_INFO(TXRX_TRIGGER_TS_RX_DIGITAL0, 3)}, /* A3 */ + {BF_TRIG_SEL_MUX_FDRC1_INFO(TXRX_TRIGGER_TS_RX_DIGITAL0, 0)}, /* A4 */ + {BF_TRIG_SEL_MUX_FDRC1_INFO(TXRX_TRIGGER_TS_RX_DIGITAL0, 1)}, /* A5 */ + {BF_TRIG_SEL_MUX_FDRC1_INFO(TXRX_TRIGGER_TS_RX_DIGITAL0, 2)}, /* A6 */ + {BF_TRIG_SEL_MUX_FDRC1_INFO(TXRX_TRIGGER_TS_RX_DIGITAL0, 3)}, /* A7 */ + + {BF_TRIG_SEL_MUX_FDRC0_INFO(TXRX_TRIGGER_TS_RX_DIGITAL1, 0)}, /* B0 */ + {BF_TRIG_SEL_MUX_FDRC0_INFO(TXRX_TRIGGER_TS_RX_DIGITAL1, 1)}, /* B1 */ + {BF_TRIG_SEL_MUX_FDRC0_INFO(TXRX_TRIGGER_TS_RX_DIGITAL1, 2)}, /* B2 */ + {BF_TRIG_SEL_MUX_FDRC0_INFO(TXRX_TRIGGER_TS_RX_DIGITAL1, 3)}, /* B3 */ + {BF_TRIG_SEL_MUX_FDRC1_INFO(TXRX_TRIGGER_TS_RX_DIGITAL1, 0)}, /* B4 */ + {BF_TRIG_SEL_MUX_FDRC1_INFO(TXRX_TRIGGER_TS_RX_DIGITAL1, 1)}, /* B5 */ + {BF_TRIG_SEL_MUX_FDRC1_INFO(TXRX_TRIGGER_TS_RX_DIGITAL1, 2)}, /* B6 */ + {BF_TRIG_SEL_MUX_FDRC1_INFO(TXRX_TRIGGER_TS_RX_DIGITAL1, 3)}, /* B7 */ + }; + + static reg_bf_info_map_t fdrc_tx_trig_sel_mux[] = { + {BF_TRIG_SEL_MUX_FDRC0_INFO(TXRX_TRIGGER_TS_TX_TOP_TX_DIGITAL0, 0)}, /* A0 */ + {BF_TRIG_SEL_MUX_FDRC0_INFO(TXRX_TRIGGER_TS_TX_TOP_TX_DIGITAL0, 1)}, /* A1 */ + {BF_TRIG_SEL_MUX_FDRC0_INFO(TXRX_TRIGGER_TS_TX_TOP_TX_DIGITAL0, 2)}, /* A2 */ + {BF_TRIG_SEL_MUX_FDRC0_INFO(TXRX_TRIGGER_TS_TX_TOP_TX_DIGITAL0, 3)}, /* A3 */ + {BF_TRIG_SEL_MUX_FDRC1_INFO(TXRX_TRIGGER_TS_TX_TOP_TX_DIGITAL0, 0)}, /* A4 */ + {BF_TRIG_SEL_MUX_FDRC1_INFO(TXRX_TRIGGER_TS_TX_TOP_TX_DIGITAL0, 1)}, /* A5 */ + {BF_TRIG_SEL_MUX_FDRC1_INFO(TXRX_TRIGGER_TS_TX_TOP_TX_DIGITAL0, 2)}, /* A6 */ + {BF_TRIG_SEL_MUX_FDRC1_INFO(TXRX_TRIGGER_TS_TX_TOP_TX_DIGITAL0, 3)}, /* A7 */ + + {BF_TRIG_SEL_MUX_FDRC0_INFO(TXRX_TRIGGER_TS_TX_TOP_TX_DIGITAL1, 0)}, /* B0 */ + {BF_TRIG_SEL_MUX_FDRC0_INFO(TXRX_TRIGGER_TS_TX_TOP_TX_DIGITAL1, 1)}, /* B1 */ + {BF_TRIG_SEL_MUX_FDRC0_INFO(TXRX_TRIGGER_TS_TX_TOP_TX_DIGITAL1, 2)}, /* B2 */ + {BF_TRIG_SEL_MUX_FDRC0_INFO(TXRX_TRIGGER_TS_TX_TOP_TX_DIGITAL1, 3)}, /* B3 */ + {BF_TRIG_SEL_MUX_FDRC1_INFO(TXRX_TRIGGER_TS_TX_TOP_TX_DIGITAL1, 0)}, /* B4 */ + {BF_TRIG_SEL_MUX_FDRC1_INFO(TXRX_TRIGGER_TS_TX_TOP_TX_DIGITAL1, 1)}, /* B5 */ + {BF_TRIG_SEL_MUX_FDRC1_INFO(TXRX_TRIGGER_TS_TX_TOP_TX_DIGITAL1, 2)}, /* B6 */ + {BF_TRIG_SEL_MUX_FDRC1_INFO(TXRX_TRIGGER_TS_TX_TOP_TX_DIGITAL1, 3)}, /* B7 */ + }; + + return (terminal == ADI_APOLLO_RX) ? &fdrc_rx_trig_sel_mux[fnco_idx] : &fdrc_tx_trig_sel_mux[fnco_idx]; +} + +static reg_bf_info_map_t *calc_bmem_trig_sel_mux(adi_apollo_terminal_e terminal, uint8_t bmem_idx) +{ + static reg_bf_info_map_t bmem_rx_trig_sel_mux[] = { + {BF_TRIG_SEL_MUX_BMEM_INFO(TXRX_TRIGGER_TS_RX_DIGITAL0, 0)}, /* A0 */ + {BF_TRIG_SEL_MUX_BMEM_INFO(TXRX_TRIGGER_TS_RX_DIGITAL0, 1)}, /* A1 */ + {BF_TRIG_SEL_MUX_BMEM_INFO(TXRX_TRIGGER_TS_RX_DIGITAL0, 0)}, /* A2 */ + {BF_TRIG_SEL_MUX_BMEM_INFO(TXRX_TRIGGER_TS_RX_DIGITAL0, 1)}, /* A3 */ + + {BF_TRIG_SEL_MUX_BMEM_INFO(TXRX_TRIGGER_TS_RX_DIGITAL1, 0)}, /* B0 */ + {BF_TRIG_SEL_MUX_BMEM_INFO(TXRX_TRIGGER_TS_RX_DIGITAL1, 1)}, /* B1 */ + {BF_TRIG_SEL_MUX_BMEM_INFO(TXRX_TRIGGER_TS_RX_DIGITAL1, 0)}, /* B2 */ + {BF_TRIG_SEL_MUX_BMEM_INFO(TXRX_TRIGGER_TS_RX_DIGITAL1, 1)}, /* B3 */ + }; + + static reg_bf_info_map_t bmem_tx_trig_sel_mux[] = { + {BF_TRIG_SEL_MUX_BMEM_INFO(TXRX_TRIGGER_TS_TX_TOP_TX_DIGITAL0, 0)}, /* A0 */ + {BF_TRIG_SEL_MUX_BMEM_INFO(TXRX_TRIGGER_TS_TX_TOP_TX_DIGITAL0, 1)}, /* A1 */ + {BF_TRIG_SEL_MUX_BMEM_INFO(TXRX_TRIGGER_TS_TX_TOP_TX_DIGITAL0, 0)}, /* A2 */ + {BF_TRIG_SEL_MUX_BMEM_INFO(TXRX_TRIGGER_TS_TX_TOP_TX_DIGITAL0, 1)}, /* A3 */ + + {BF_TRIG_SEL_MUX_BMEM_INFO(TXRX_TRIGGER_TS_TX_TOP_TX_DIGITAL1, 0)}, /* B0 */ + {BF_TRIG_SEL_MUX_BMEM_INFO(TXRX_TRIGGER_TS_TX_TOP_TX_DIGITAL1, 1)}, /* B1 */ + {BF_TRIG_SEL_MUX_BMEM_INFO(TXRX_TRIGGER_TS_TX_TOP_TX_DIGITAL1, 0)}, /* B2 */ + {BF_TRIG_SEL_MUX_BMEM_INFO(TXRX_TRIGGER_TS_TX_TOP_TX_DIGITAL1, 1)}, /* B3 */ + }; + + return (terminal == ADI_APOLLO_RX) ? &bmem_rx_trig_sel_mux[bmem_idx] : &bmem_tx_trig_sel_mux[bmem_idx]; +} + +static reg_bf_info_map_t *calc_pfilt_trig_sel_mux(adi_apollo_terminal_e terminal, uint8_t pfilt_idx) +{ + static reg_bf_info_map_t pfilt_rx_trig_sel_mux[] = { + {BF_TRIG_SEL_MUX_PFILT0_INFO(TXRX_TRIGGER_TS_RX_DIGITAL0)}, /* A0 */ + {BF_TRIG_SEL_MUX_PFILT1_INFO(TXRX_TRIGGER_TS_RX_DIGITAL0)}, /* A1 */ + + {BF_TRIG_SEL_MUX_PFILT0_INFO(TXRX_TRIGGER_TS_RX_DIGITAL1)}, /* B0 */ + {BF_TRIG_SEL_MUX_PFILT1_INFO(TXRX_TRIGGER_TS_RX_DIGITAL1)}, /* B1 */ + }; + + static reg_bf_info_map_t pfilt_tx_trig_sel_mux[] = { + {BF_TRIG_SEL_MUX_PFILT0_INFO(TXRX_TRIGGER_TS_TX_TOP_TX_DIGITAL0)}, /* A0 */ + {BF_TRIG_SEL_MUX_PFILT1_INFO(TXRX_TRIGGER_TS_TX_TOP_TX_DIGITAL0)}, /* A1 */ + + {BF_TRIG_SEL_MUX_PFILT0_INFO(TXRX_TRIGGER_TS_TX_TOP_TX_DIGITAL1)}, /* B0 */ + {BF_TRIG_SEL_MUX_PFILT1_INFO(TXRX_TRIGGER_TS_TX_TOP_TX_DIGITAL1)}, /* B1 */ + }; + + return (terminal == ADI_APOLLO_RX) ? &pfilt_rx_trig_sel_mux[pfilt_idx] : &pfilt_tx_trig_sel_mux[pfilt_idx]; +} + +static reg_bf_info_map_t *calc_cfir_trig_sel_mux(adi_apollo_terminal_e terminal, uint8_t cfir_idx) +{ + static reg_bf_info_map_t cfir_rx_trig_sel_mux[] = { + {BF_TRIG_SEL_MUX_CFIR_INFO(TXRX_TRIGGER_TS_RX_DIGITAL0, 0)}, /* A0 */ + {BF_TRIG_SEL_MUX_CFIR_INFO(TXRX_TRIGGER_TS_RX_DIGITAL0, 1)}, /* A1 */ + + {BF_TRIG_SEL_MUX_CFIR_INFO(TXRX_TRIGGER_TS_RX_DIGITAL1, 0)}, /* B0 */ + {BF_TRIG_SEL_MUX_CFIR_INFO(TXRX_TRIGGER_TS_RX_DIGITAL1, 1)}, /* B1 */ + }; + + static reg_bf_info_map_t cfir_tx_trig_sel_mux[] = { + {BF_TRIG_SEL_MUX_CFIR_INFO(TXRX_TRIGGER_TS_TX_TOP_TX_DIGITAL0, 0)}, /* A0 */ + {BF_TRIG_SEL_MUX_CFIR_INFO(TXRX_TRIGGER_TS_TX_TOP_TX_DIGITAL0, 1)}, /* A1 */ + + {BF_TRIG_SEL_MUX_CFIR_INFO(TXRX_TRIGGER_TS_TX_TOP_TX_DIGITAL1, 0)}, /* B0 */ + {BF_TRIG_SEL_MUX_CFIR_INFO(TXRX_TRIGGER_TS_TX_TOP_TX_DIGITAL1, 1)}, /* B1 */ + }; + + return (terminal == ADI_APOLLO_RX) ? &cfir_rx_trig_sel_mux[cfir_idx] : &cfir_tx_trig_sel_mux[cfir_idx]; +} + + uint32_t calc_trigts_base(adi_apollo_terminal_e terminal, int32_t side_index) + { + static uint32_t rx_trigts_regmap[ADI_APOLLO_NUM_SIDES] = { + TXRX_TRIGGER_TS_RX_DIGITAL0, TXRX_TRIGGER_TS_RX_DIGITAL1 + }; + static uint32_t tx_trigts_regmap[ADI_APOLLO_NUM_SIDES] = { + TXRX_TRIGGER_TS_TX_TOP_TX_DIGITAL0, TXRX_TRIGGER_TS_TX_TOP_TX_DIGITAL1 + }; + if (terminal == ADI_APOLLO_RX) + return rx_trigts_regmap[side_index]; + else + return tx_trigts_regmap[side_index]; + } + + + +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_trigts_local.h b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_trigts_local.h new file mode 100644 index 00000000000000..ba6ada305064b4 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_trigts_local.h @@ -0,0 +1,37 @@ +/*! + * \brief Apollo TRIG_TS local defines and prototypes + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_TRIG + * @{ + */ +#ifndef __ADI_APOLLO_TRIG_TS_LOCAL_H__ +#define __ADI_APOLLO_TRIG_TS_LOCAL_H__ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_common.h" + +/*============= D E F I N E S ==============*/ + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +uint32_t calc_trigts_base(adi_apollo_terminal_e terminal, int32_t side_index); + +#ifndef CLIENT_IGNORE +#endif /* CLIENT_IGNORE*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_TRIG_TS_LOCAL_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_tx.c b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_tx.c new file mode 100644 index 00000000000000..73ed78029e2a5b --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_tx.c @@ -0,0 +1,583 @@ +/*! + * \brief TX data path top level APIs + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_TX + * @{ + */ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo.h" +#include "adi_apollo_tx.h" +#include "adi_apollo_config.h" +#include "adi_apollo_cfg.h" +#include "adi_apollo_hal.h" +#include "adi_apollo_duc_local.h" +#include "adi_apollo_dac.h" +#include "adi_apollo_jrx.h" +#include "adi_apollo_private_device.h" +#include "adi_apollo_bf_tx_misc.h" +#include "adi_apollo_txmisc_local.h" + +/*==================== P U B L I C A P I C O D E ====================*/ +int32_t adi_apollo_tx_configure(adi_apollo_device_t *device, adi_apollo_sides_e side, adi_apollo_txpath_t *config, adi_apollo_jesd_rx_cfg_t* jrx_config) +{ + int32_t err; + uint8_t i; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(config); + ADI_APOLLO_NULL_POINTER_RETURN(jrx_config); + ADI_APOLLO_INVALID_PARAM_RETURN((side > ADI_APOLLO_NUM_SIDES - 1)); + + + /* Release TX datapath DP reset */ + adi_apollo_txmisc_dp_reset(device, (adi_apollo_side_select_e)(1 << side), 0); + + /* CDUC/CNCO config */ + for (i = 0; i < ADI_APOLLO_CDUCS_PER_SIDE; i ++) { + err = adi_apollo_tx_cduc_configure(device, side, (adi_apollo_cduc_idx_e)i, &(config->tx_cduc[i])); + ADI_APOLLO_ERROR_RETURN(err); + } + + /* FDUC/FNCO config */ + for (i = 0; i < ADI_APOLLO_FDUCS_PER_SIDE; i ++) { + err = adi_apollo_tx_fduc_configure(device, side, (adi_apollo_fduc_idx_e)i, &(config->tx_fduc[i])); + ADI_APOLLO_ERROR_RETURN(err); + } + + /* Summer, XBAR and misc config */ + err = adi_apollo_tx_txpath_misc_configure(device, side, &(config->tx_mux_summer_xbar)); + ADI_APOLLO_ERROR_RETURN(err); + + /* PFILT config */ + if (!adi_apollo_private_device_lockout_get(device, ADI_APOLLO_TX, ADI_APOLLO_EC_PFILT_LOCK)) { + for (i = 0; i < ADI_APOLLO_PFILTS_PER_SIDE; i ++) { + err = adi_apollo_tx_pfilt_configure(device, side, (adi_apollo_pfilt_idx_e)i, &(config->tx_pfilt[i])); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + /* CFIR config */ + if (!adi_apollo_private_device_lockout_get(device, ADI_APOLLO_TX, ADI_APOLLO_EC_CFIR_LOCK)) { + for(i = 0; i < ADI_APOLLO_CFIRS_PER_SIDE; i ++) { + err = adi_apollo_tx_cfir_configure(device, side, (adi_apollo_cfir_idx_e)i, &(config->tx_cfir[i])); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + /* FSRC config */ + if (!adi_apollo_private_device_lockout_get(device, ADI_APOLLO_TX, ADI_APOLLO_EC_FSRC_LOCK)) { + for(i = 0; i < ADI_APOLLO_FSRC_PER_SIDE_NUM; i ++) { + err = adi_apollo_tx_fsrc_configure(device, side, (uint8_t)i, &(config->tx_fsrc), &(jrx_config->rx_link_cfg[i])); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + /* Inverse SINC config */ + for (i = 0; i < ADI_APOLLO_CDUC_PATHS_PER_SIDE; i ++) { + err = adi_apollo_tx_inv_sinc_configure(device, side, (adi_apollo_cduc_path_idx_e)i, config->inv_sinc_en[i] ? 1 : 0); + ADI_APOLLO_ERROR_RETURN(err); + } + + /* Tx Sample Repeat config */ + for (i = 0; i < ADI_APOLLO_JESD_LINKS; i++) { + err = adi_apollo_tx_sample_repeat_configure(device, side, (adi_apollo_jesd_links_e)i, config, jrx_config); + ADI_APOLLO_ERROR_RETURN(err); + } + + return API_CMS_ERROR_OK; +} + + +int32_t adi_apollo_tx_cduc_configure(adi_apollo_device_t *device, adi_apollo_sides_e side, adi_apollo_cduc_idx_e idx, adi_apollo_cduc_cfg_t *config) +{ + int32_t err; + uint8_t cduc_sel; + uint8_t cnco_sel; + int cnco_idx; + adi_apollo_cduc_pgm_t duc_pgm_config; + adi_apollo_cnco_pgm_t nco_pgm_config; + adi_apollo_coarse_nco_hop_t nco_hop_profile_config; + adi_apollo_trig_mst_config_t nco_trig_mst_config; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(config); + + /* Determine block api select from index */ + cduc_sel = ADI_APOLLO_CDUC_IDX2B(side, idx); + + /* Program the coarse DUC */ + duc_pgm_config.interp = config->drc_ratio; + duc_pgm_config.chb1_int_time_dly = 0; + duc_pgm_config.chb2_int_time_dly = 0; + duc_pgm_config.chb3_int_time_dly = 0; + duc_pgm_config.ctb1_int_time_dly = 0; + duc_pgm_config.test_mux = 0; + duc_pgm_config.cduc_spien_en = 0; + duc_pgm_config.cduc_spi_en = 0x00; + duc_pgm_config.cduc_irq_en = 0; + duc_pgm_config.cduc_irq_status = 0xff; + err = adi_apollo_cduc_pgm(device, cduc_sel, &duc_pgm_config); + ADI_APOLLO_ERROR_RETURN(err); + + /* Program the CNCOs (there are two CNCOs per CDUC) */ + for (cnco_idx = 0; cnco_idx < ADI_APOLLO_NUM_NCOS_PER_DRC; cnco_idx++) { + + cnco_sel = cduc_sel << (2 * cnco_idx); // Selects A0/A2, A1/A3, ... B1/B3 (pairs for 8t8r) + + /* Program the coarse NCO */ + nco_pgm_config.drc_en = config->nco[cnco_idx].drc_en; + nco_pgm_config.debug_drc_clkoff_n = 0xff; + nco_pgm_config.profile_num = 0; + nco_pgm_config.profile_sel_mode = config->nco[cnco_idx].nco_profile_sel_mode; + nco_pgm_config.cmplx_mxr_scale_en = config->nco[cnco_idx].cmplx_mxr_mult_scale_en; + nco_pgm_config.drc_phase_inc = config->nco[cnco_idx].nco_phase_inc; + nco_pgm_config.drc_phase_offset = config->nco[cnco_idx].nco_phase_offset; + nco_pgm_config.drc_phase_inc_frac_a = config->nco[cnco_idx].nco_phase_inc_frac_a; + nco_pgm_config.drc_phase_inc_frac_b = config->nco[cnco_idx].nco_phase_inc_frac_b; + nco_pgm_config.if_mode = config->nco[cnco_idx].nco_if_mode; + nco_pgm_config.mixer_sel = config->nco[cnco_idx].drc_mxr_sel; + nco_pgm_config.dc_testmode_value = config->nco[cnco_idx].dc_testmode_value; + err = adi_apollo_cnco_pgm(device, ADI_APOLLO_TX, cnco_sel, &nco_pgm_config); + ADI_APOLLO_ERROR_RETURN(err); + + /* Load the coarse nco profiles */ + err = adi_apollo_cnco_profile_load(device, ADI_APOLLO_TX, cnco_sel, + ADI_APOLLO_NCO_PROFILE_PHASE_INCREMENT, 0, config->nco[cnco_idx].nco_phase_inc_words, ADI_APOLLO_CNCO_PROFILE_NUM); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_cnco_profile_load(device, ADI_APOLLO_TX, cnco_sel, + ADI_APOLLO_NCO_PROFILE_PHASE_OFFSET, 0, config->nco[cnco_idx].nco_phase_offset_words, ADI_APOLLO_CNCO_PROFILE_NUM); + ADI_APOLLO_ERROR_RETURN(err); + + /* Auto hop flip, incr or decr */ + nco_hop_profile_config.profile_sel_mode = config->nco[cnco_idx].nco_profile_sel_mode; + nco_hop_profile_config.auto_mode = config->nco[cnco_idx].nco_auto_inc_dec; + nco_hop_profile_config.low_limit = 0; + nco_hop_profile_config.high_limit = 15; + nco_hop_profile_config.next_hop_number_wr_en = 0; + nco_hop_profile_config.hop_ctrl_init = 0; + nco_hop_profile_config.phase_handling = 0; + err = adi_apollo_cnco_hop_enable(device, ADI_APOLLO_TX, cnco_sel, &nco_hop_profile_config); + ADI_APOLLO_ERROR_RETURN(err); + + nco_trig_mst_config.trig_enable = ADI_APOLLO_TRIG_DISABLE; + nco_trig_mst_config.trig_period = 0; + nco_trig_mst_config.trig_offset = 0; + err = adi_apollo_trigts_cnco_trig_mst_config(device, ADI_APOLLO_TX, cnco_sel, &nco_trig_mst_config); + ADI_APOLLO_ERROR_RETURN(err); + + /* Set initial phase inc and offset. Select profile 0 as default. */ + err = adi_apollo_cnco_ftw_set(device, ADI_APOLLO_TX, cnco_sel, 0, 1, config->nco[cnco_idx].nco_phase_inc); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_cnco_pow_set(device, ADI_APOLLO_TX, cnco_sel, 0, 1, config->nco[cnco_idx].nco_phase_offset); + ADI_APOLLO_ERROR_RETURN(err); + } + + // Trigger selection mux here + err = adi_apollo_trigts_cdrc_trig_sel_mux_set(device, ADI_APOLLO_TX, cduc_sel, ADI_APOLLO_TRIG_SPI); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_tx_fduc_configure(adi_apollo_device_t *device, adi_apollo_sides_e side, adi_apollo_fduc_idx_e idx, adi_apollo_fduc_cfg_t *config) +{ + int32_t err; + uint16_t fduc_sel; + uint16_t fnco_sel; + int fnco_idx; + adi_apollo_fduc_pgm_t duc_pgm_config; + adi_apollo_fnco_pgm_t nco_pgm_config; + adi_apollo_fine_nco_hop_t nco_hop_profile_config; + adi_apollo_trig_mst_config_t nco_trig_mst_config; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(config); + ADI_APOLLO_INVALID_PARAM_RETURN((idx > ADI_APOLLO_FDUCS_PER_SIDE-1)) + + /* Determine block api select from index */ + fduc_sel = ADI_APOLLO_FDUC_IDX2B(side, idx); + + /* Program the FDUC functional block */ + duc_pgm_config.interp = config->drc_ratio; + duc_pgm_config.int_tdly_hb = 0, /* post v1.1.0 dev profile */ + duc_pgm_config.sub_dp_gain_en = config->sub_dp_gain_en; + duc_pgm_config.subdp_gain = config->subdp_gain; + duc_pgm_config.fduc_spien_en = 0x00; // disable FDUC enable by SPI, use auto FDUC enable summer mux + err = adi_apollo_fduc_pgm(device, fduc_sel, &duc_pgm_config); + ADI_APOLLO_ERROR_RETURN(err); + + /* Program the FNCOs (there are two FNCOs per FDUC) */ + for (fnco_idx = 0; fnco_idx < ADI_APOLLO_NUM_NCOS_PER_DRC; fnco_idx++) { + + fnco_sel = fduc_sel << (4 * fnco_idx); // Selects A0/A4, A1/A5, ... B3/B7 (pairs for 8t8r) + + nco_pgm_config.drc_en = config->nco[fnco_idx].drc_en; + nco_pgm_config.debug_drc_clkoff_n = config->nco[fnco_idx].debug_fdrc_clkoff_n; + nco_pgm_config.if_mode = config->nco[fnco_idx].nco_if_mode; + nco_pgm_config.mixer_sel = config->nco[fnco_idx].drc_mxr_sel; + nco_pgm_config.cmplx_mxr_scale_en = config->nco[fnco_idx].cmplx_mxr_mult_scale_en; + nco_pgm_config.hop_mode_en = config->nco[fnco_idx].hop_mode_en; + nco_pgm_config.profile_num = 0; + nco_pgm_config.profile_sel_mode = config->nco[fnco_idx].nco_profile_sel_mode; + nco_pgm_config.main_phase_inc = config->nco[fnco_idx].nco_phase_inc; + nco_pgm_config.main_phase_offset = config->nco[fnco_idx].nco_phase_offset; + nco_pgm_config.drc_phase_inc_frac_a = config->nco[fnco_idx].nco_phase_inc_frac_a; + nco_pgm_config.drc_phase_inc_frac_b = config->nco[fnco_idx].nco_phase_inc_frac_b; + nco_pgm_config.dc_testmode_value = config->nco[fnco_idx].dc_testmode_value; + err = adi_apollo_fnco_pgm(device, ADI_APOLLO_TX, fnco_sel, &nco_pgm_config); + ADI_APOLLO_ERROR_RETURN(err); + + /* Load fine nco profiles */ + err = adi_apollo_fnco_profile_load(device, ADI_APOLLO_TX, fnco_sel, + ADI_APOLLO_NCO_PROFILE_PHASE_INCREMENT, 0, config->nco[fnco_idx].nco_phase_inc_words, ADI_APOLLO_FNCO_PROFILE_NUM); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_fnco_profile_load(device, ADI_APOLLO_TX, fnco_sel, + ADI_APOLLO_NCO_PROFILE_PHASE_OFFSET, 0, config->nco[fnco_idx].nco_phase_offset_words, ADI_APOLLO_FNCO_PROFILE_NUM); + ADI_APOLLO_ERROR_RETURN(err); + + /* Configure hopping */ + nco_hop_profile_config.profile_sel_mode = config->nco[fnco_idx].nco_profile_sel_mode; + nco_hop_profile_config.nco_trig_hop_sel = config->nco[fnco_idx].nco_trig_hop_sel; + nco_hop_profile_config.phase_inc_auto_mode = (adi_apollo_nco_auto_flip_incdir_e)config->nco[fnco_idx].nco_auto_inc_dec_freq; + nco_hop_profile_config.phase_offset_auto_mode = (adi_apollo_nco_auto_flip_incdir_e)config->nco[fnco_idx].nco_auto_inc_dec_phase; + nco_hop_profile_config.phase_inc_low_limit = 0; + nco_hop_profile_config.phase_inc_high_limit = 31; + nco_hop_profile_config.phase_offset_low_limit = 0; + nco_hop_profile_config.phase_offset_high_limit = 31; + nco_hop_profile_config.phase_handling = 0; + err = adi_apollo_fnco_hop_pgm(device, ADI_APOLLO_TX, fnco_sel, &nco_hop_profile_config); + + nco_trig_mst_config.trig_enable = ADI_APOLLO_TRIG_DISABLE; + nco_trig_mst_config.trig_period = 0; + nco_trig_mst_config.trig_offset = 0; + err = adi_apollo_trigts_fnco_trig_mst_config(device, ADI_APOLLO_TX, fnco_sel, &nco_trig_mst_config); + ADI_APOLLO_ERROR_RETURN(err); + + // Trigger selection mux here + err = adi_apollo_trigts_fdrc_trig_sel_mux_set(device, ADI_APOLLO_TX, fduc_sel, ADI_APOLLO_TRIG_SPI); + ADI_APOLLO_ERROR_RETURN(err); + + /* Set initial hop index to 0. This is relevant when hop_mode_en is true */ + err = adi_apollo_fnco_ftw_set(device, ADI_APOLLO_TX, fnco_sel, 0, 1, config->nco[fnco_idx].nco_phase_inc_words[0]); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_fnco_pow_set(device, ADI_APOLLO_TX, fnco_sel, 0, 1, config->nco[fnco_idx].nco_phase_offset_words[0]); + ADI_APOLLO_ERROR_RETURN(err); + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_tx_pfilt_configure(adi_apollo_device_t *device, adi_apollo_sides_e side, adi_apollo_pfilt_idx_e idx_pfilt, adi_apollo_pfilt_cfg_t *config) +{ + int32_t err; + uint8_t coeff_set_idx; + uint8_t ctrl_sets_idx; + adi_apollo_pfilt_mode_pgm_t blk_mode_config; + adi_apollo_pfilt_gain_dly_pgm_t blk_gain_dly_config; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(config); + ADI_APOLLO_INVALID_PARAM_RETURN((idx_pfilt > ADI_APOLLO_PFILTS_PER_SIDE-1)) + + /* In a 4T4R part, there is one pfilt on each side (side A and Side B), "pfilt 0" => pfilt A0 on side A and pfilt B0 on side B + * In an 8T8R part, there are two pfilts on each side => pfilt A0 and A1 on side A, and pfilt B0 and B1 on side B + * Each pfilt has 4 banks that can be switched between + * This mean there are 8 pfilt banks in an 8T8R on each side => 16 banks in total + * This function's job is to program the 8 banks on the side passed into the function + * This function should not try to program the upper 4 banks into A1/B1 if this is not an 8T8R part + */ + adi_apollo_blk_sel_t pfiltsMsk = (device->dev_info.is_8t8r) ? ADI_APOLLO_PFILT_ALL : ADI_APOLLO_PFILT_ALL_4T4R; + + for (coeff_set_idx = 0; coeff_set_idx 0) { + /* Program pfilt coefficient sets */ + err = adi_apollo_pfilt_coeff_pgm(device, + ADI_APOLLO_TX, + pfilts, + ADI_APOLLO_PFILT_COEFF_IDX2B(coeff_set_idx), + config->coeffs[coeff_set_idx], + ADI_APOLLO_PFILT_COEFFS); + ADI_APOLLO_ERROR_RETURN(err); + + /* Configure pfilt gain and delay sets */ + blk_gain_dly_config.pfir_ix_gain = config->pfir_ix_gain_db[coeff_set_idx]; + blk_gain_dly_config.pfir_iy_gain = config->pfir_iy_gain_db[coeff_set_idx]; + blk_gain_dly_config.pfir_qx_gain = config->pfir_qx_gain_db[coeff_set_idx]; + blk_gain_dly_config.pfir_qy_gain = config->pfir_qy_gain_db[coeff_set_idx]; + blk_gain_dly_config.pfir_ix_scalar_gain = config->pfir_ix_scalar_gain_db[coeff_set_idx]; + blk_gain_dly_config.pfir_iy_scalar_gain = config->pfir_iy_scalar_gain_db[coeff_set_idx]; + blk_gain_dly_config.pfir_qx_scalar_gain = config->pfir_qx_scalar_gain_db[coeff_set_idx]; + blk_gain_dly_config.pfir_qy_scalar_gain = config->pfir_qy_scalar_gain_db[coeff_set_idx]; + blk_gain_dly_config.hc_delay = config->hc_prog_delay[coeff_set_idx]; + + err = adi_apollo_pfilt_gain_dly_pgm(device, + ADI_APOLLO_TX, + pfilts, + ADI_APOLLO_PFILT_COEFF_IDX2B(coeff_set_idx), + &blk_gain_dly_config); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + /* Program pfilt mode */ + blk_mode_config.data = config->real_data; + blk_mode_config.add_sub_sel = config->add_sub_sel; + blk_mode_config.dq_mode = device->dev_info.is_8t8r ? ADI_APOLLO_PFILT_QUAD_MODE : ADI_APOLLO_PFILT_DUAL_MODE; + blk_mode_config.mode_switch = config->mode_switch; + + /* v10 - loop through both sets */ + /* Program the PFIR sets for 4T4R or 8T8R */ + for (ctrl_sets_idx = 0; ctrl_sets_idx < ADI_APOLLO_PFILT_CTRL_SETS; ctrl_sets_idx++) + { + blk_mode_config.pfir_i_mode[ctrl_sets_idx] = config->enable ? config->i_mode[ctrl_sets_idx] : ADI_APOLLO_PFILT_MODE_DISABLED; + blk_mode_config.pfir_q_mode[ctrl_sets_idx] = config->enable ? config->q_mode[ctrl_sets_idx] : ADI_APOLLO_PFILT_MODE_DISABLED; + + adi_apollo_blk_sel_t pfilts = pfiltsMsk & (ADI_APOLLO_PFILT_IDX2B(side, ctrl_sets_idx)); + + /* Only program the mode if the filter exists */ + if (pfilts > 0) { + err = adi_apollo_pfilt_mode_pgm(device, + ADI_APOLLO_TX, + pfilts, + &blk_mode_config); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_tx_cfir_configure(adi_apollo_device_t* device, adi_apollo_sides_e side, adi_apollo_cfir_idx_e idx_cfir, adi_apollo_cfir_cfg_t* config) +{ + int32_t err; + uint8_t idx_profile, idx_set; + adi_apollo_cfir_pgm_t blk_mode_config; + uint16_t sparse_coeff_sel_sel[ADI_APOLLO_CFIR_NUM_TAPS] = { 0 }; + uint8_t sparse_mem_sel[ADI_APOLLO_CFIR_MEM_SEL_NUM] = { 0 }; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(config); + ADI_APOLLO_INVALID_PARAM_RETURN((idx_cfir > ADI_APOLLO_CFIRS_PER_SIDE - 1)) + + /* CFIR top parameters */ + blk_mode_config.cfir_bypass = config->enable ? 0 : 1; //Bypass config + blk_mode_config.cfir_sparse_filt_en = config->sparse_mode; + blk_mode_config.cfir_32taps_en = config->cfir_mode; //cfir_32taps_en config + blk_mode_config.cfir_coeff_transfer = 0; //coeff_transfer should go from 0 to 1 + + err = adi_apollo_cfir_pgm(device, ADI_APOLLO_TX, ADI_APOLLO_CFIR_IDX2B(side, idx_cfir), &blk_mode_config); + ADI_APOLLO_ERROR_RETURN(err); + + /* Program CFIR coefficients, gain, scalar gain and sparse values for all profiles */ + for (idx_profile = 0; idx_profile < ADI_APOLLO_CFIR_NUM_PROFILES; idx_profile++) { + for (idx_set = 0; idx_set < ADI_APOLLO_CFIR_COEFF_SETS; idx_set++) { + err = adi_apollo_cfir_coeff_pgm(device, ADI_APOLLO_TX, ADI_APOLLO_CFIR_IDX2B(side, idx_cfir), + ADI_APOLLO_CFIR_PROFILE_IDX2B(idx_profile), + ADI_APOLLO_CFIR_COEFF_SET_IDX2B(idx_set), + config->coeffs_i[idx_profile][idx_set], config->coeffs_q[idx_profile][idx_set], ADI_APOLLO_CFIR_NUM_TAPS); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_cfir_scalar_pgm(device, ADI_APOLLO_TX, ADI_APOLLO_CFIR_IDX2B(side, idx_cfir), + ADI_APOLLO_CFIR_PROFILE_IDX2B(idx_profile), + ADI_APOLLO_CFIR_COEFF_SET_IDX2B(idx_set), + config->scalar_i[idx_profile][idx_set], config->scalar_q[idx_profile][idx_set]); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_cfir_gain_pgm(device, ADI_APOLLO_TX, ADI_APOLLO_CFIR_IDX2B(side, idx_cfir), + ADI_APOLLO_CFIR_PROFILE_IDX2B(idx_profile), + ADI_APOLLO_CFIR_COEFF_SET_IDX2B(idx_set), + config->cfir_gain_dB[idx_profile][idx_set]); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_cfir_sparse_coeff_sel_pgm(device, ADI_APOLLO_TX, ADI_APOLLO_CFIR_IDX2B(side, idx_cfir), + ADI_APOLLO_CFIR_PROFILE_IDX2B(idx_profile), + ADI_APOLLO_CFIR_COEFF_SET_IDX2B(idx_set), + sparse_coeff_sel_sel, ADI_APOLLO_CFIR_NUM_TAPS); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_cfir_sparse_mem_sel_pgm(device, ADI_APOLLO_TX, ADI_APOLLO_CFIR_IDX2B(side, idx_cfir), + ADI_APOLLO_CFIR_PROFILE_IDX2B(idx_profile), + ADI_APOLLO_CFIR_COEFF_SET_IDX2B(idx_set), + sparse_mem_sel, ADI_APOLLO_CFIR_MEM_SEL_NUM); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + /* Make profile #0 active for all data paths. Transfers profile 0 coeffs and gains to CFIR block */ + err = adi_apollo_cfir_profile_sel(device, ADI_APOLLO_TX, ADI_APOLLO_CFIR_IDX2B(side, idx_cfir), + ADI_APOLLO_CFIR_DP_ALL, ADI_APOLLO_CFIR_PROFILE_0); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_tx_fsrc_configure(adi_apollo_device_t *device, adi_apollo_sides_e side, uint8_t idx_fsrc, + adi_apollo_fsrc_cfg_t *config, adi_apollo_jesd_rx_link_cfg_t *jrx_link_config) +{ + int32_t err; + adi_apollo_fsrc_pgm_t blk_mode_config; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(config); + ADI_APOLLO_NULL_POINTER_RETURN(jrx_link_config); + ADI_APOLLO_INVALID_PARAM_RETURN((idx_fsrc > ADI_APOLLO_FSRC_PER_SIDE_NUM-1)) + + /* Program fsrc */ + blk_mode_config.fsrc_rate_int = config->fsrc_rate_int; + blk_mode_config.fsrc_rate_frac_a = config->fsrc_rate_frac_a; + blk_mode_config.fsrc_rate_frac_b = config->fsrc_rate_frac_b; + blk_mode_config.sample_frac_delay = config->fsrc_delay; + blk_mode_config.fsrc_en0 = config->enable0; + blk_mode_config.fsrc_en1 = config->enable1; + blk_mode_config.gain_reduction = config->gain_reduction; + blk_mode_config.ptr_overwrite = config->ptr_overwrite; + blk_mode_config.ptr_syncrstval = config->ptr_syncrstval; + blk_mode_config.fsrc_data_mult_dither_en = config->data_mult_dither_en; + blk_mode_config.fsrc_dither_en = config->dither_en; + blk_mode_config.fsrc_4t4r_split = config->split_4t4r; + blk_mode_config.fsrc_bypass = (config->enable0 || config->enable1) ? 0 : 1 ; + blk_mode_config.fsrc_1x_mode = config->mode_1x; + + err = adi_apollo_fsrc_pgm(device, ADI_APOLLO_TX, + ADI_APOLLO_FSRC_IDX2B(side, idx_fsrc), + &blk_mode_config); + ADI_APOLLO_ERROR_RETURN(err); + + #include "adi_apollo_bf_jrx_wrapper.h" + uint32_t jrx_wrapper; + jrx_wrapper = side ? JRX_WRAPPER_JRX_TX_DIGITAL1 : JRX_WRAPPER_JRX_TX_DIGITAL0; + if (jrx_link_config->link_in_use) { + /* Enable Invalid Samples */ + err = adi_apollo_hal_bf_set(device, BF_INVALID_DATA_EN_INFO(jrx_wrapper, idx_fsrc), (config->enable0 || config->enable1)); + ADI_APOLLO_ERROR_RETURN(err); + /* Number of Invalid Samples */ + err = adi_apollo_hal_bf_set(device, BF_NUM_OF_INVALID_SAMPLE_INFO(jrx_wrapper, idx_fsrc), jrx_link_config->ns_minus1); + ADI_APOLLO_ERROR_RETURN(err); + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_tx_txpath_misc_configure(adi_apollo_device_t *device, adi_apollo_sides_e side, adi_apollo_txpath_misc_t *config) +{ + int32_t err; + uint8_t i, summer_sel; + uint16_t fduc_sel; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(config); + + /* Summer crossbar (Tx mux2) */ + for (i = 0; i < ADI_APOLLO_CDUC_PATHS_PER_SIDE; i++) { + /* Determine block api select from index. (summer/cduc are 1-to-1) */ + summer_sel = ADI_APOLLO_CDUC_IDX2B(side, i); + + /* Convert FDUC side selection to api bit mask */ + fduc_sel = config->fduc_cduc_summer[i] << ((side == ADI_APOLLO_SIDE_IDX_A) ? 0 : ADI_APOLLO_TX_SUMMER_NUM); + + /* Program the FDUC-to-CDUC summer crossbar */ + err = adi_apollo_txmux_summer_block_set(device, summer_sel, fduc_sel); + ADI_APOLLO_ERROR_RETURN(err); + } + + /* For each CDUC on the side selected, pass in the enable from the device profile */ + for (i = 0; i < ADI_APOLLO_CDUC_PATHS_PER_SIDE; i++) { + uint8_t cducs = ADI_APOLLO_CDUC_IDX2B(side, i); + + err = adi_apollo_txmisc_cduc_dac_enable_set(device, cducs, config->cduc_dac_enables[i]); + } + + /* HSDOUT (Tx mux0) */ + err = adi_apollo_txmux_hsdout_set(device, ADI_APOLLO_SIDE_IDX2B(side), config->mux0_sel, ADI_APOLLO_NUM_DAC_PER_SIDE); + ADI_APOLLO_ERROR_RETURN(err); + + /* Modulator Switch (MODSW, Tx mux1) */ + err = adi_apollo_txmux_modsw_set(device, ADI_APOLLO_SIDE_IDX2B(side), (adi_apollo_modsw_select_e)config->mux1_sel[0], (adi_apollo_modsw_select_e)config->mux1_sel[1]); + ADI_APOLLO_ERROR_RETURN(err); + + /* Low sample mode */ + err = adi_apollo_txmisc_low_samp_set(device, ADI_APOLLO_SIDE_IDX2B(side), config->low_samp_en? 1 : 0); + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_tx_inv_sinc_configure(adi_apollo_device_t *device, adi_apollo_sides_e side, adi_apollo_cduc_path_idx_e idx, uint8_t enable) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + err = adi_apollo_invsinc_enable(device, ADI_APOLLO_CDUC_IDX2B(side, idx), enable); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_tx_sample_repeat_configure(adi_apollo_device_t *device, adi_apollo_sides_e side, + adi_apollo_jesd_links_e link_idx, adi_apollo_txpath_t *tx_path_config, adi_apollo_jesd_rx_cfg_t *jrx_config) +{ + int32_t err; + uint16_t links = side ? ADI_APOLLO_LINK_SIDE_B : ADI_APOLLO_LINK_SIDE_A; + adi_apollo_fsrc_cfg_t *fsrc_config; + adi_apollo_jesd_rx_link_cfg_t *jrx_link_config; + uint8_t is_1x1x_mode = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_INVALID_PARAM_RETURN(link_idx > ADI_APOLLO_JESD_LINK_1); + ADI_APOLLO_NULL_POINTER_RETURN(tx_path_config); + ADI_APOLLO_NULL_POINTER_RETURN(jrx_config); + + /* V10 fix*/ + fsrc_config = &(tx_path_config->tx_fsrc); + jrx_link_config = &(jrx_config->rx_link_cfg[link_idx]); + + /* V10 fix*/ + if (!(fsrc_config->enable0 || fsrc_config->enable1) && jrx_link_config->link_in_use) { + + // If link dp ratio does not match the greatest duc ratio, then sample repeat should be enabled. + is_1x1x_mode = (tx_path_config->tx_cduc[0].drc_ratio == ADI_APOLLO_CDUC_RATIO_1) && (tx_path_config->tx_fduc[0].drc_ratio == ADI_APOLLO_FDUC_RATIO_1); + err = adi_apollo_jesd_rx_sample_repeat_en(device, links << (int32_t)link_idx, !is_1x1x_mode); + + ADI_APOLLO_ERROR_RETURN(err); + } + return API_CMS_ERROR_OK; +} +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_txen.c b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_txen.c new file mode 100644 index 00000000000000..648f52f2c05a95 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_txen.c @@ -0,0 +1,399 @@ +/*! + * \brief APIs for TxEn + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_TXEN + * @{ + */ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_txen.h" +#include "adi_apollo_txen_local.h" +#include "adi_apollo_pfilt.h" +#include "adi_apollo_cduc.h" +#include "adi_apollo_fduc.h" +#include "adi_apollo_private_blk_sel_types.h" + +#include "adi_apollo_bf_txen_power_ctrl.h" +#include "adi_apollo_bf_txrx_enable.h" +#include "adi_apollo_bf_tx_hsdout.h" + +#include "adi_apollo_config.h" +#include "adi_apollo_hal.h" + +/*==================== P U B L I C A P I C O D E ====================*/ + +int32_t adi_apollo_txen_pwrup_ctrl_config_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t dacs, const adi_apollo_txen_pwrup_blk_config_t *config) +{ + int32_t err; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(config); + ADI_APOLLO_TXEN_BLK_SEL_MASK(dacs); + + err = adi_apollo_txen_pwrup_ctrl_set(device, dacs, &config->ctrl); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_txen_pwrup_ctrl_edge_set(device, dacs, &config->edge); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_txen_pwrup_ctrl_count_set(device, dacs, &config->count); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_txen_pwrup_ctrl_pin_set(device, dacs, config->pin_en); + ADI_APOLLO_ERROR_RETURN(err); + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_txen_pwrup_ctrl_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t dacs, const adi_apollo_txen_pwrup_ctrl_t *config) +{ + int32_t err; + uint8_t i; + adi_apollo_blk_sel_t dac; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(config); + ADI_APOLLO_TXEN_BLK_SEL_MASK(dacs); + + for (i = 0; i < ADI_APOLLO_DAC_NUM; i ++) { + dac = dacs & (ADI_APOLLO_TXEN_DAC_A0 << i); + if (dac > 0) { + regmap_base_addr = calc_tx_txen_power_ctrl_base(i); + + err = adi_apollo_hal_bf_set(device, BF_SM_EN_INFO(regmap_base_addr), config->sm_en); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_SPI_TXEN_ENA_INFO(regmap_base_addr), config->spi_txen_en); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_SPI_TXEN_INFO(regmap_base_addr), config->spi_txen); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_SEL_CNT_RATE_INFO(regmap_base_addr), + (config->sm_clk_rate == ADI_APOLLO_PUC_CLK_RATE_FS_DIV_256) ? 1 : 0); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_txen_pwrup_ctrl_edge_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t dacs, const adi_apollo_txen_pwrup_ctrl_edge_t *config) +{ + int32_t err; + uint8_t i; + adi_apollo_blk_sel_t dac; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(config); + ADI_APOLLO_TXEN_BLK_SEL_MASK(dacs); + + for (i = 0; i < ADI_APOLLO_DAC_NUM; i ++) { + dac = dacs & (ADI_APOLLO_TXEN_DAC_A0 << i); + if (dac > 0) { + regmap_base_addr = calc_tx_txen_power_ctrl_base(i); + + err = adi_apollo_hal_bf_set(device, BF_DAC_RISE_INFO(regmap_base_addr), config->dac_rise); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_DAC_FALL_INFO(regmap_base_addr), config->dac_fall); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_DIG_RISE_INFO(regmap_base_addr), config->dig_rise); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_DIG_FALL_INFO(regmap_base_addr), config->dig_fall); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_PA_RISE_INFO(regmap_base_addr), config->pa_rise); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_set(device, BF_PA_FALL_INFO(regmap_base_addr), config->pa_fall); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_txen_pwrup_ctrl_count_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t dacs, const adi_apollo_txen_pwrup_ctrl_count_t *config) +{ + int32_t err; + uint8_t i; + adi_apollo_blk_sel_t dac; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(config); + ADI_APOLLO_TXEN_BLK_SEL_MASK(dacs); + + for (i = 0; i < ADI_APOLLO_DAC_NUM; i ++) { + dac = dacs & (ADI_APOLLO_TXEN_DAC_A0 << i); + if (dac > 0) { + regmap_base_addr = calc_tx_txen_power_ctrl_base(i); + + err = adi_apollo_hal_bf_set(device, BF_COUNT_MAXA_INFO(regmap_base_addr), config->count_maxa); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_COUNT_MAXB_INFO(regmap_base_addr), config->count_maxb); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_COUNT_MAXC_INFO(regmap_base_addr), config->count_maxc); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_COUNT_MAXD_INFO(regmap_base_addr), config->count_maxd); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_COUNT_MAXE_INFO(regmap_base_addr), config->count_maxe); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_bf_set(device, BF_COUNT_MAXF_INFO(regmap_base_addr), config->count_maxf); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_txen_pwrup_ctrl_pin_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t dacs, adi_apollo_puc_en_pin_sel_e pin) +{ + int32_t err; + uint8_t i; + adi_apollo_blk_sel_t dac; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_TXEN_BLK_SEL_MASK(dacs); + + for (i = 0; i < ADI_APOLLO_DAC_NUM; i ++) { + dac = dacs & (ADI_APOLLO_TXEN_DAC_A0 << i); + if (dac > 0) { + regmap_base_addr = calc_tx_txen_power_ctrl_base(i); + + err = adi_apollo_hal_bf_set(device, BF_TXEN_SEL_INFO(regmap_base_addr), pin); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_txen_pwrup_ctrl_sm_en_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t dacs, uint8_t sm_en) +{ + int32_t err; + uint8_t i; + adi_apollo_blk_sel_t dac; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_TXEN_BLK_SEL_MASK(dacs); + + for (i = 0; i < ADI_APOLLO_DAC_NUM; i ++) { + dac = dacs & (ADI_APOLLO_TXEN_DAC_A0 << i); + if (dac > 0) { + regmap_base_addr = calc_tx_txen_power_ctrl_base(i); + + err = adi_apollo_hal_bf_set(device, BF_SM_EN_INFO(regmap_base_addr), sm_en); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; + +} + +int32_t adi_apollo_txen_pwrup_ctrl_sel_cnt_rate_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t dacs, uint8_t sel_cnt_rate) +{ + int32_t err; + uint8_t i; + adi_apollo_blk_sel_t dac; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_TXEN_BLK_SEL_MASK(dacs); + + for (i = 0; i < ADI_APOLLO_DAC_NUM; i ++) { + dac = dacs & (ADI_APOLLO_TXEN_DAC_A0 << i); + if (dac > 0) { + regmap_base_addr = calc_tx_txen_power_ctrl_base(i); + err = adi_apollo_hal_bf_set(device, BF_SEL_CNT_RATE_INFO(regmap_base_addr), + (sel_cnt_rate == ADI_APOLLO_PUC_CLK_RATE_FS_DIV_256) ? 1 : 0); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; + +} + +/* Map Tx chanId to address for bias_force_standby_en bitfield */ +static uint32_t tx_chan_id_to_bias_force_standby_en_addr [] = { + 0x6123880b, + 0x6123880b, + 0x6123880b, + 0x6123980b, + 0x6143880b, + 0x6143980b, + 0x61a3880b, + 0x61a3980b, + 0x61c3880b, + 0x61c3980b +}; + +int32_t adi_apollo_txen_config_set(adi_apollo_device_t *device, adi_apollo_blk_sel_t tx_enables, const adi_apollo_txen_blk_config_t *config) +{ + int32_t err; + uint8_t chan_id, side; + adi_apollo_blk_sel_t tx_en; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(config); + ADI_APOLLO_TXEN_BLK_SEL_MASK(tx_enables); + + for (chan_id = 0; chan_id < ADI_APOLLO_NUM_TX_EN; chan_id ++) { + tx_en = tx_enables & (ADI_APOLLO_TX_EN_A0 << chan_id); + if (tx_en > 0) { + + side = chan_id / ADI_APOLLO_NUM_TX_EN_PER_SIDE; + + /* TXRX_ENABLE block on TX_SLICE0 controls both slices. There is no TXRX_ENABLE block on TX_SLICE1. */ + regmap_base_addr = calc_tx_enable_base(side); + + /* Enable polarity */ + err = adi_apollo_hal_bf_set(device, + BF_ENABLE_POL_INFO(regmap_base_addr, (chan_id % ADI_APOLLO_NUM_TX_EN_PER_SIDE)), + (config->enable_polarity == ADI_APOLLO_TXEN_EN_ACTIVE_HIGH) ? 0 : 1); + ADI_APOLLO_ERROR_RETURN(err); + + /* SPI enable */ + err = adi_apollo_hal_bf_set(device, + BF_ENABLE_SPI_INFO(regmap_base_addr, (chan_id % ADI_APOLLO_NUM_TX_EN_PER_SIDE)), + (config->spi_en == ADI_APOLLO_DISABLE) ? 0 : 1); + ADI_APOLLO_ERROR_RETURN(err); + + /* SPIEN enable */ + err = adi_apollo_hal_bf_set(device, + BF_ENABLE_SPIEN_INFO(regmap_base_addr, (chan_id % ADI_APOLLO_NUM_TX_EN_PER_SIDE)), + (config->spien_en == ADI_APOLLO_DISABLE) ? 0 : 1); + ADI_APOLLO_ERROR_RETURN(err); + + /* Slice select */ + /* Regardless of 8T8R or 4T4R, the lower four bits in config->slice_sel are for SideA; the upper four for SideB */ + err = adi_apollo_hal_bf_set(device, + BF_SLICE_SEL_INFO(regmap_base_addr, (chan_id % ADI_APOLLO_NUM_TX_EN_PER_SIDE)), + (side == 0) ? config->slice_sel : config->slice_sel >> ADI_APOLLO_MAX_SLICES_PER_SIDE_NUM); + ADI_APOLLO_ERROR_RETURN(err); + + /* Linx select */ + err = adi_apollo_hal_bf_set(device, + BF_LINX_SEL_INFO(regmap_base_addr, (chan_id % ADI_APOLLO_NUM_TX_EN_PER_SIDE)), + (side == 0) ? config->linx_sel : config->linx_sel >> ADI_APOLLO_NUM_LINX_PER_SIDE); + ADI_APOLLO_ERROR_RETURN(err); + + /* PFILT select */ + err = adi_apollo_hal_bf_set(device, + BF_PFILT_SEL_INFO(regmap_base_addr, (chan_id % ADI_APOLLO_NUM_TX_EN_PER_SIDE)), + (side == 0) ? config->pfilt_sel : config->pfilt_sel >> ADI_APOLLO_PFILT_PER_SIDE); + ADI_APOLLO_ERROR_RETURN(err); + + /* CDUC select */ + err = adi_apollo_hal_bf_set(device, + BF_CDUC_CDDC_SEL_INFO(regmap_base_addr, (chan_id % ADI_APOLLO_NUM_TX_EN_PER_SIDE)), + (side == 0) ? config->cduc_sel : config->cduc_sel >> ADI_APOLLO_CDUC_PER_SIDE_NUM); + ADI_APOLLO_ERROR_RETURN(err); + + /* FDUC select */ + err = adi_apollo_hal_bf_set(device, + BF_FDUC_FDDC_SEL_INFO(regmap_base_addr, (chan_id % ADI_APOLLO_NUM_TX_EN_PER_SIDE)), + (side == 0) ? config->fduc_sel : config->fduc_sel >> ADI_APOLLO_FDUC_PER_SIDE_NUM); + ADI_APOLLO_ERROR_RETURN(err); + + /* CFIR select */ + err = adi_apollo_hal_bf_set(device, + BF_CFIR_SEL_INFO(regmap_base_addr, (chan_id % ADI_APOLLO_NUM_TX_EN_PER_SIDE)), + (side == 0) ? config->cfir_sel : config->cfir_sel >> ADI_APOLLO_NUM_CFIR_PER_SIDE); + ADI_APOLLO_ERROR_RETURN(err); + + /* FSRC select */ + err = adi_apollo_hal_bf_set(device, + BF_FSRC_SEL_INFO(regmap_base_addr, (chan_id % ADI_APOLLO_NUM_TX_EN_PER_SIDE)), + (side == 0) ? config->fsrc_sel : config->fsrc_sel >> ADI_APOLLO_NUM_FSRC_PER_SIDE); + ADI_APOLLO_ERROR_RETURN(err); + + /* JRX link select */ + err = adi_apollo_hal_bf_set(device, + BF_JRX_JTX_LINK_SEL_INFO(regmap_base_addr, (chan_id % ADI_APOLLO_NUM_TX_EN_PER_SIDE)), + (side == 0) ? config->jrx_link_sel : config->jrx_link_sel >> ADI_APOLLO_NUM_JRX_LINKS_PER_SIDE); + ADI_APOLLO_ERROR_RETURN(err); + + /* JRX phy0 & phy1 select */ + err = adi_apollo_hal_bf_set(device, + BF_JRX_JTX_PHY_SEL_INFO(regmap_base_addr, (chan_id % ADI_APOLLO_NUM_TX_EN_PER_SIDE)), + (side == 0) ? config->jrx_phy_sel_side_a : config->jrx_phy_sel_side_b); + ADI_APOLLO_ERROR_RETURN(err); + + /* MODSW select */ + err = adi_apollo_hal_bf_set(device, + BF_MODSW_SEL_INFO(regmap_base_addr, (chan_id % ADI_APOLLO_NUM_TX_EN_PER_SIDE)), + (config->modsw_sel == ADI_APOLLO_DISABLE) ? 0 : 1); + ADI_APOLLO_ERROR_RETURN(err); + + /* INVSINC select */ + err = adi_apollo_hal_bf_set(device, + BF_INVSINC_SEL_INFO(regmap_base_addr, (chan_id % ADI_APOLLO_NUM_TX_EN_PER_SIDE)), + (side == 0) ? config->invsinc_sel : config->invsinc_sel >> ADI_APOLLO_NUM_TX_INVSINC_PER_SIDE); + ADI_APOLLO_ERROR_RETURN(err); + + /* GAIN select */ + err = adi_apollo_hal_bf_set(device, + BF_GAIN_SEL_INFO(regmap_base_addr, (chan_id % ADI_APOLLO_NUM_TX_EN_PER_SIDE)), + (side == 0) ? config->gain_sel : config->gain_sel >> ADI_APOLLO_NUM_TX_GAIN_PER_SIDE); + ADI_APOLLO_ERROR_RETURN(err); + + /* SRD select */ + err = adi_apollo_hal_bf_set(device, + BF_SRD_SEL_INFO(regmap_base_addr, (chan_id % ADI_APOLLO_NUM_TX_EN_PER_SIDE)), + (side == 0) ? config->srd_sel : config->srd_sel >> ADI_APOLLO_NUM_TX_SRD_PER_SIDE); + ADI_APOLLO_ERROR_RETURN(err); + + /* Set DAC to disable output on standby signal */ + err = adi_apollo_hal_bf_set(device, tx_chan_id_to_bias_force_standby_en_addr[chan_id], 0x0104, 0); + ADI_CMS_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +uint32_t calc_tx_txen_power_ctrl_base(int32_t dac_index) +{ + static uint32_t tx_txen_power_ctrl_regmap[] = { + TXEN_POWER_CTRL0_TX_SLICE_0_TX_DIGITAL0, TXEN_POWER_CTRL1_TX_SLICE_0_TX_DIGITAL0, + TXEN_POWER_CTRL0_TX_SLICE_1_TX_DIGITAL0, TXEN_POWER_CTRL1_TX_SLICE_1_TX_DIGITAL0, + TXEN_POWER_CTRL0_TX_SLICE_0_TX_DIGITAL1, TXEN_POWER_CTRL1_TX_SLICE_0_TX_DIGITAL1, + TXEN_POWER_CTRL0_TX_SLICE_1_TX_DIGITAL1, TXEN_POWER_CTRL1_TX_SLICE_1_TX_DIGITAL1 + }; + + return (tx_txen_power_ctrl_regmap[dac_index]); +} + +uint32_t calc_tx_enable_base(int32_t index) +{ + static uint32_t tx_enable_regmap[] = { + TXRX_ENABLE_TX_SLICE_0_TX_DIGITAL0, TXRX_ENABLE_TX_SLICE_0_TX_DIGITAL1 + }; + + return (tx_enable_regmap[index]); +} + +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_txen_local.h b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_txen_local.h new file mode 100644 index 00000000000000..e6a0d5074ed92f --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_txen_local.h @@ -0,0 +1,35 @@ +/*! + * \brief Apollo Tx En local defines and prototypes + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_TXEN + * @{ + */ +#ifndef __ADI_APOLLO_TXEN_LOCAL_H__ +#define __ADI_APOLLO_TXEN_LOCAL_H__ + + +/*============= I N C L U D E S ============*/ + +/*============= D E F I N E S ==============*/ + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +uint32_t calc_tx_txen_power_ctrl_base(int32_t dac_index); +uint32_t calc_tx_enable_base(int32_t index); + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_TXEN_LOCAL_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_txmisc.c b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_txmisc.c new file mode 100644 index 00000000000000..9fee043caa7f79 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_txmisc.c @@ -0,0 +1,203 @@ +/*! + * \brief Tx Misc functional block API implementation + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_TXMISC + * @{ + */ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_txmisc.h" +#include "adi_apollo_txmisc_local.h" + +#include "adi_apollo_bf_core.h" +#include "adi_apollo_bf_tx_misc.h" + +#include "adi_apollo_cduc.h" +#include "adi_apollo_config.h" +#include "adi_apollo_hal.h" +#include "adi_utils.h" + +static int32_t tx_summer_inspect(adi_apollo_device_t* device, uint16_t side_idx, adi_apollo_txpath_misc_t* dp); +static int32_t tx_cduc_dac_inspect(adi_apollo_device_t* device, uint16_t side_idx, adi_apollo_txpath_misc_t* dp); + +/*==================== P U B L I C A P I C O D E ====================*/ + +int32_t adi_apollo_txmisc_low_samp_set(adi_apollo_device_t *device, adi_apollo_side_select_e side_sel, uint8_t low_samp_en) +{ + int32_t err; + uint8_t side, side_index; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + for (side_index = 0; side_index < ADI_APOLLO_NUM_SIDES; side_index++) { + side = side_sel & (ADI_APOLLO_SIDE_A << side_index); + if (side > 0) { + regmap_base_addr = calc_tx_misc_base(side_index); + + err = adi_apollo_hal_bf_set(device, BF_LOW_SAMP_TX_MISC_INFO(regmap_base_addr), low_samp_en); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_txmisc_dp_reset(adi_apollo_device_t *device, adi_apollo_side_select_e side_sel, uint8_t reset_en) +{ + int32_t err; + uint8_t side, side_index; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + for (side_index = 0; side_index < ADI_APOLLO_NUM_SIDES; side_index++) { + side = side_sel & (ADI_APOLLO_SIDE_A << side_index); + if (side > 0) { + if (side_index == 0) + err = adi_apollo_hal_bf_set(device, BF_TX_DP_RESET_A_INFO, reset_en); + else + err = adi_apollo_hal_bf_set(device, BF_TX_DP_RESET_B_INFO, reset_en); + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_txmisc_cduc_dac_enable_set(adi_apollo_device_t *device, const uint16_t cducs, const uint8_t enable) +{ + int32_t err; + uint16_t i, cducs_sel; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + for (i = 0; i < ADI_APOLLO_CDUC_NUM; i++) { + /* Select one CDUC at a time */ + cducs_sel = cducs & (ADI_APOLLO_CDUC_A0 << i); + if (cducs_sel > 0) { + /* Base address is side-dependent */ + regmap_base_addr = calc_tx_misc_base(i / ADI_APOLLO_CDUC_PATHS_PER_SIDE); + + /* Program the CDUC_DAC_ENABLESx fields */ + switch (i % ADI_APOLLO_CDUC_PATHS_PER_SIDE) + { + case 0: + err = adi_apollo_hal_bf_set(device, BF_CDUC_DAC_ENABLES0_INFO(regmap_base_addr), enable); + break; + case 1: + err = adi_apollo_hal_bf_set(device, BF_CDUC_DAC_ENABLES1_INFO(regmap_base_addr), enable); + break; + case 2: + err = adi_apollo_hal_bf_set(device, BF_CDUC_DAC_ENABLES2_INFO(regmap_base_addr), enable); + break; + case 3: + err = adi_apollo_hal_bf_set(device, BF_CDUC_DAC_ENABLES3_INFO(regmap_base_addr), enable); + break; + } + ADI_APOLLO_ERROR_RETURN(err); + } + } + + return API_CMS_ERROR_OK; +} + + +int32_t adi_apollo_txmisc_inspect(adi_apollo_device_t *device, uint16_t side_sel, adi_apollo_txmisc_inspect_t *txmisc_inspect) +{ + int32_t err; + uint8_t side, side_index; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + ADI_APOLLO_NULL_POINTER_RETURN(txmisc_inspect); + ADI_APOLLO_INVALID_PARAM_RETURN(adi_api_utils_num_selected(side_sel) != 1); + + for (side_index = 0; side_index < ADI_APOLLO_NUM_SIDES; side_index++) { + side = side_sel & (ADI_APOLLO_SIDE_A << side_index); + if (side > 0) { + err = tx_summer_inspect(device, side_index, &txmisc_inspect->dp); + ADI_APOLLO_ERROR_RETURN(err); + + err = tx_cduc_dac_inspect(device, side_index, &txmisc_inspect->dp); + ADI_APOLLO_ERROR_RETURN(err); + + /* Inspect only one side per call */ + break; + } + } + + return API_CMS_ERROR_OK; +} + +static int32_t tx_summer_inspect(adi_apollo_device_t* device, uint16_t side_idx, adi_apollo_txpath_misc_t *dp) +{ + int32_t err; + uint8_t fduc_enables[4]; + + uint32_t regmap_base_addr = calc_tx_misc_base(side_idx); + + err = adi_apollo_hal_reg_get(device, REG_FDUC_ENABLES00_ADDR(regmap_base_addr), &fduc_enables[0]); + ADI_APOLLO_ERROR_RETURN(err); + + err = adi_apollo_hal_reg_get(device, REG_FDUC_ENABLES10_ADDR(regmap_base_addr), &fduc_enables[2]); + ADI_APOLLO_ERROR_RETURN(err); + + + if (device->dev_info.is_8t8r) { + /* Summer A0 */ + dp->fduc_cduc_summer[0] = + ((fduc_enables[0] & 0x01) >> 0) | ((fduc_enables[0] & 0x04) >> 1) | ((fduc_enables[0] & 0x10) >> 2) | ((fduc_enables[0] & 0x40) >> 3) | + ((fduc_enables[0] & 0x02) << 3) | ((fduc_enables[0] & 0x08) >> 2) | ((fduc_enables[0] & 0x20) >> 1) | ((fduc_enables[0] & 0x80) >> 0); + /* Summer A1 */ + dp->fduc_cduc_summer[1] = + ((fduc_enables[2] & 0x01) >> 0) | ((fduc_enables[2] & 0x04) >> 1) | ((fduc_enables[2] & 0x10) >> 2) | ((fduc_enables[2] & 0x40) >> 3) | + ((fduc_enables[2] & 0x02) << 3) | ((fduc_enables[2] & 0x08) >> 2) | ((fduc_enables[2] & 0x20) >> 1) | ((fduc_enables[2] & 0x80) >> 0); + } else { + /* Summer A0 */ + dp->fduc_cduc_summer[0] = fduc_enables[0] & 0x0f; + + /* Summer A1 */ + dp->fduc_cduc_summer[1] = fduc_enables[2] & 0x0f; + } + + return API_CMS_ERROR_OK; +} + +static int32_t tx_cduc_dac_inspect(adi_apollo_device_t* device, uint16_t side_idx, adi_apollo_txpath_misc_t *dp) +{ + int32_t err; + uint32_t regmap_base_addr = calc_tx_misc_base(side_idx); + + err = adi_apollo_hal_bf_get(device, BF_CDUC_DAC_ENABLES0_INFO(regmap_base_addr), &dp->cduc_dac_enables[0], 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_CDUC_DAC_ENABLES1_INFO(regmap_base_addr), &dp->cduc_dac_enables[1], 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_CDUC_DAC_ENABLES2_INFO(regmap_base_addr), &dp->cduc_dac_enables[2], 1); + ADI_APOLLO_ERROR_RETURN(err); + err = adi_apollo_hal_bf_get(device, BF_CDUC_DAC_ENABLES3_INFO(regmap_base_addr), &dp->cduc_dac_enables[3], 1); + + return API_CMS_ERROR_OK; +} + +uint32_t calc_tx_misc_base(int32_t idx) +{ + static const uint32_t tx_misc_regmap[ADI_APOLLO_TX_MISC_REGMAP_NUM] = { + TX_MISC_TX_TOP_TX_DIGITAL0, + + TX_MISC_TX_TOP_TX_DIGITAL1 + }; + + return tx_misc_regmap[idx]; +} +/*! @} */ \ No newline at end of file diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_txmisc_local.h b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_txmisc_local.h new file mode 100644 index 00000000000000..edffb72e5b5627 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_txmisc_local.h @@ -0,0 +1,36 @@ +/*! + * \brief Tx misc functional block local API implementation + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_TXMISC + * @{ + */ +#ifndef __ADI_APOLLO_TXMISC_LOCAL_H__ +#define __ADI_APOLLO_TXMISC_LOCAL_H__ + +/*============= I N C L U D E S ============*/ + +/*============= D E F I N E S ==============*/ + +/*============= E X P O R T S ==============*/ +#ifdef __cplusplus +extern "C" { +#endif + +uint32_t calc_tx_misc_base(int32_t side); + +#ifndef CLIENT_IGNORE +#endif /* CLIENT_IGNORE*/ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADI_APOLLO_TXMISC_LOCAL_H__ */ +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_txmux.c b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_txmux.c new file mode 100644 index 00000000000000..21f294d38f661e --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_txmux.c @@ -0,0 +1,131 @@ +/*! + * \brief APIs for Tx MUXs + * + * \copyright copyright(c) 2018 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_TXMUX + * @{ + */ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_txmux.h" +#include "adi_apollo_txen_local.h" +#include "adi_apollo_duc_local.h" +#include "adi_apollo_fduc_types.h" +#include "adi_apollo_txmisc_local.h" + +#include "adi_apollo_bf_tx_misc.h" +#include "adi_apollo_bf_tx_hsdout.h" + +#include "adi_apollo_config.h" +#include "adi_apollo_hal.h" + +/*==================== P U B L I C A P I C O D E ====================*/ + +int32_t adi_apollo_txmux_summer_block_set(adi_apollo_device_t *device, const uint16_t summers, const uint16_t fducs_connected) +{ + int32_t err; + uint8_t fduc, fducs, fduc_sel_mask; + uint16_t i, j, reg_ofst, summer; + uint32_t regmap_base_addr = 0; + + /* align summer reg A A0 A1 A2 A3 */ + /* B0 B1 B2 B3 */ + const static uint8_t reg_ofst_tab[4] = {0x00, 0x02, 0x01, 0x03}; + + /* fduc selects for 8T devices A0 A1 A2 A3 A4 A5 A6 A7 */ + /* B0 B1 B2 B3 B4 B5 B6 B7 */ + const static uint8_t fduc_sel_map_8t8r[] = {0x01, 0x04, 0x10, 0x40, 0x02, 0x08, 0x20, 0x80}; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + for (i = 0; i < ADI_APOLLO_TX_SUMMER_NUM; i ++) { + summer = summers & (ADI_APOLLO_TX_SUMMER_A0 << i); + + if (summer > 0) { + regmap_base_addr = calc_tx_misc_base(i / ADI_APOLLO_TX_SUMMER_PER_SIDE_NUM); + + // Determine proper fduc enable register + reg_ofst = reg_ofst_tab[i % ADI_APOLLO_TX_SUMMER_PER_SIDE_NUM]; + + fducs = (i < ADI_APOLLO_TX_SUMMER_PER_SIDE_NUM) ? fducs_connected : fducs_connected >> ADI_APOLLO_FDUC_PER_SIDE_NUM; + + fduc_sel_mask = 0; + for (j = 0; j < ADI_APOLLO_FDUC_PER_SIDE_NUM; j++) { + fduc = fducs & (ADI_APOLLO_FDUC_A0 << j); + if (fduc > 0) { + fduc_sel_mask |= (device->dev_info.is_8t8r == 1) ? fduc_sel_map_8t8r[j] : (1< ADI_APOLLO_NUM_DAC_PER_SIDE); + + for (i = 0; i < length; i ++) { + xbar |= (0x03 & dac[i]) << (2*i); + } + + if ((side_sel & ADI_APOLLO_SIDE_A) > 0) { + regmap_base_addr = calc_tx_misc_base(0); + err = adi_apollo_hal_bf_set(device, BF_HS_XBAR_CTRL_INFO(regmap_base_addr), (uint8_t)xbar); + ADI_APOLLO_ERROR_RETURN(err); + } + + if ((side_sel & ADI_APOLLO_SIDE_B) > 0) { + regmap_base_addr = calc_tx_misc_base(1); + err = adi_apollo_hal_bf_set(device, BF_HS_XBAR_CTRL_INFO(regmap_base_addr), (uint8_t)xbar); + ADI_APOLLO_ERROR_RETURN(err); + } + + return API_CMS_ERROR_OK; +} + +int32_t adi_apollo_txmux_modsw_set(adi_apollo_device_t *device, adi_apollo_side_select_e side_sel, adi_apollo_modsw_select_e modsw0, adi_apollo_modsw_select_e modsw1) +{ + int32_t err; + uint8_t side, side_index; + uint32_t regmap_base_addr = 0; + + ADI_APOLLO_NULL_POINTER_RETURN(device); + ADI_APOLLO_LOG_FUNC(); + + for (side_index = 0; side_index < ADI_APOLLO_NUM_SIDES; side_index++) { + side = side_sel & (ADI_APOLLO_SIDE_A << side_index); + if (side > 0) { + regmap_base_addr = calc_tx_misc_base(side_index); + + err = adi_apollo_hal_bf_set(device, BF_MODSW0_INFO(regmap_base_addr), modsw0); + ADI_APOLLO_ERROR_RETURN(err); + + if (device->dev_info.is_8t8r) { + err = adi_apollo_hal_bf_set(device, BF_MODSW1_INFO(regmap_base_addr), modsw1); + ADI_APOLLO_ERROR_RETURN(err); + } + } + } + + return API_CMS_ERROR_OK; +} + +/*! @} */ diff --git a/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_utils.c b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_utils.c new file mode 100644 index 00000000000000..10be86227a1f39 --- /dev/null +++ b/drivers/iio/trx-rf/ad9088/public/src/adi_apollo_utils.c @@ -0,0 +1,45 @@ +/*! + * \brief Apollo API utilities + * + * \copyright copyright(c) 2023 analog devices, inc. all rights reserved. + * This software is proprietary to Analog Devices, Inc. and its + * licensor. By using this software you agree to the terms of the + * associated analog devices software license agreement. + */ + +/*! + * \addtogroup ADI_APOLLO_UTILS + * @{ + */ + +/*============= I N C L U D E S ============*/ +#include "adi_apollo_utils.h" + +static int32_t converter_to_sides(adi_apollo_device_t* device, uint16_t converter, uint16_t *side_select); + +/*==================== P U B L I C A P I C O D E ====================*/ + +int32_t adi_apollo_utils_side_from_adc_select_get(adi_apollo_device_t *device, uint16_t adc_select, uint16_t *side_select) { + return converter_to_sides(device, adc_select, side_select); +} + +int32_t adi_apollo_utils_side_from_dac_select_get(adi_apollo_device_t *device, uint16_t dac_select, uint16_t *side_select) { + return converter_to_sides(device, dac_select, side_select); +} + +/*==================== L O C A L A P I C O D E ====================*/ + +static int32_t converter_to_sides(adi_apollo_device_t* device, uint16_t converter, uint16_t *side_select) { + adi_apollo_side_select_e sel = 0; + + if (converter & ADI_APOLLO_ADC_A_ALL) { + sel = sel | ADI_APOLLO_SIDE_A; + } + if (converter & ADI_APOLLO_ADC_B_ALL) { + sel = sel | ADI_APOLLO_SIDE_B; + } + *side_select = sel; + + return API_CMS_ERROR_OK; +} +/*! @} */ \ No newline at end of file diff --git a/drivers/jesd204/jesd204-fsm.c b/drivers/jesd204/jesd204-fsm.c index 32cc5bc819dcf0..1779a10bc05ad0 100644 --- a/drivers/jesd204/jesd204-fsm.c +++ b/drivers/jesd204/jesd204-fsm.c @@ -157,6 +157,9 @@ static const struct jesd204_fsm_table_entry jesd204_start_links_states[] = { JESD204_STATE_OP(CLOCKS_ENABLE), JESD204_STATE_OP(LINK_ENABLE), JESD204_STATE_OP(LINK_RUNNING), + JESD204_STATE_OP(OPT_POST_SETUP_STAGE1), + JESD204_STATE_OP(OPT_POST_SETUP_STAGE2), + JESD204_STATE_OP(OPT_POST_SETUP_STAGE3), JESD204_STATE_OP_LAST(OPT_POST_RUNNING_STAGE), }; @@ -203,6 +206,12 @@ const char *jesd204_state_str(enum jesd204_dev_state state) return "opt_setup_stage4"; case JESD204_STATE_OPT_SETUP_STAGE5: return "opt_setup_stage5"; + case JESD204_STATE_OPT_POST_SETUP_STAGE1: + return "opt_post_setup_stage1"; + case JESD204_STATE_OPT_POST_SETUP_STAGE2: + return "opt_post_setup_stage2"; + case JESD204_STATE_OPT_POST_SETUP_STAGE3: + return "opt_post_setup_stage3"; case JESD204_STATE_OPT_POST_RUNNING_STAGE: return "opt_post_running_stage"; case JESD204_STATE_DONT_CARE: diff --git a/drivers/jesd204/jesd204-priv.h b/drivers/jesd204/jesd204-priv.h index fa142662cbb2f2..e9e83c4d19cc84 100644 --- a/drivers/jesd204/jesd204-priv.h +++ b/drivers/jesd204/jesd204-priv.h @@ -44,6 +44,9 @@ enum jesd204_dev_state { JESD204_STATE_ENUM(CLOCKS_ENABLE), JESD204_STATE_ENUM(LINK_ENABLE), JESD204_STATE_ENUM(LINK_RUNNING), + JESD204_STATE_ENUM(OPT_POST_SETUP_STAGE1), + JESD204_STATE_ENUM(OPT_POST_SETUP_STAGE2), + JESD204_STATE_ENUM(OPT_POST_SETUP_STAGE3), JESD204_STATE_ENUM(OPT_POST_RUNNING_STAGE), JESD204_STATE_DONT_CARE = 999, }; diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index 22c16d096571f5..3dee47a68b3e47 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -71,6 +71,18 @@ config ADI_AXI_TDD the previous TDD engine, this core can only be used standalone mode, and is not embedded into other devices. +config ADI_AXI_HSCI + tristate "Analog Devices HSCI Interface Support" + depends on HAS_IOMEM + depends on OF + help + The data hsci interface is found on some digitizer products. + This option is usually not enabled manually but rather by other + drivers that use the data hsci engine to manage interface transfers. + + To compile this driver as a module, choose M here: the + module will be called adi-axi-hsci. + config DUMMY_IRQ tristate "Dummy IRQ handler" help diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 08d1b95d3a9f97..74409f617f1dff 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_AD525X_DPOT_I2C) += ad525x_dpot-i2c.o obj-$(CONFIG_AD525X_DPOT_SPI) += ad525x_dpot-spi.o obj-$(CONFIG_ADI_AXI_DATA_OFFLOAD) += adi-axi-data-offload.o obj-$(CONFIG_ADI_AXI_TDD) += adi-axi-tdd.o +obj-$(CONFIG_ADI_AXI_HSCI) += adi-axi-hsci.o obj-$(CONFIG_ATMEL_SSC) += atmel-ssc.o obj-$(CONFIG_DUMMY_IRQ) += dummy-irq.o obj-$(CONFIG_ICS932S401) += ics932s401.o diff --git a/drivers/misc/adi-axi-hsci.c b/drivers/misc/adi-axi-hsci.c new file mode 100644 index 00000000000000..79801d78419ed1 --- /dev/null +++ b/drivers/misc/adi-axi-hsci.c @@ -0,0 +1,1267 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Analog Devices AXI HSCI interface + * + * Copyright 2023-2025 Analog Devices Inc. + * + * Wiki: https://wiki.analog.com/resources/fpga/docs/hsci + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "adi-axi-hsci.h" + +/* + * +----------+----------------------------+---------+-----------------------------------------------------------------------+ + * | ADDRESS | REG NAME | BITS | BITFIELD | + * +----------+----------------------------+---------+-----------------------------------------------------------------------+ + * | 00000000 | REVISION_ID | | | + * | | | [15:0] | revision_id_hsci_revision_id (r) | + * | 00008001 | HSCI_MASTER_MODE | | | + * | | | [1:0] | hsci_master_mode_hsci_xfer_mode (r/w) | + * | | | [4] | ver_b__na (r/w) | + * | 00008002 | HSCI_MASTER_XFER_NUM | | | + * | | | [15:0] | hsci_master_xfer_num_hsci_xfer_num (r/w) | + * | 00008003 | HSCI_MASTER_ADDR_SIZE | | | + * | | | [2:0] | hsci_master_addr_size_hsci_addr_size (r/w) | + * | 00008004 | HSCI_MASTER_BYTE_NUM | | | + * | | | [16:0] | hsci_master_byte_num_hsci_byte_num (r/w) | + * | 00008005 | HSCI_MASTER_TARGET | | | + * | | | [31:0] | hsci_master_target_spi_target (r/w) | + * | 00008006 | HSCI_MASTER_CTRL | | | + * | | | [1:0] | hsci_master_ctrl_hsci_cmd_sel (r/w) | + * | | | [5:4] | hsci_master_ctrl_hsci_slave_ahb_tsize (r/w) | + * | 00008007 | HSCI_MASTER_BRAM_ADDRESS | | | + * | | | [15:0] | hsci_master_bram_address_hsci_bram_start_address (r/w) | + * | 00008008 | HSCI_MASTER_RUN | | | + * | | | [0] | hsci_master_run_hsci_run (r/w) | + * | 00008009 | HSCI_MASTER_STATUS | | | + * | | | [0] | hsci_master_status_master_done (r) Volatile | + * | | | [1] | hsci_master_status_master_running (r) Volatile | + * | | | [2] | hsci_master_status_master_wr_in_prog (r) Volatile | + * | | | [3] | hsci_master_status_master_rd_in_prog (r) Volatile | + * | | | [4] | hsci_master_status_miso_test_lfsr_acq (r) Volatile | + * | 0000800a | HSCI_MASTER_LINKUP_CTRL | | | + * | | | [9:0] | hsci_master_linkup_ctrl_hsci_man_linkup_word (r/w) | + * | | | [10] | hsci_master_linkup_ctrl_hsci_man_linkup (r/w) | + * | | | [11] | hsci_master_linkup_ctrl_hsci_auto_linkup (r/w) | + * | | | [12] | mosi_clk_inv (r/w) | + * | | | [13] | miso_clk_inv (r/w) | + * | 0000800b | HSCI_MASTER_TEST_CTRL | | | + * | | | [0] | hsci_master_test_ctrl_hsci_mosi_test_mode (r/w) | + * | | | [1] | hsci_master_test_ctrl_hsci_miso_test_mode (r/w) | + * | | | [2] | hsci_master_test_ctrl_hsci_capture_mode (r/w) | + * | 0000800c | HSCI_MASTER_LINKUP_STATUS | | | + * | | | [0] | hsci_master_linkup_status_link_active (r) Volatile | + * | | | [7:4] | hsci_master_linkup_status_alink_txclk_adj (r) Volatile | + * | | | [8] | hsci_master_linkup_status_alink_txclk_inv (r) Volatile | + * | | | [10] | txclk_adj_mismatch (r) Volatile | + * | | | [11] | txclk_inv_mismatch (r) Volatile | + * | 0000800d | HSCI_MASTER_LINKUP_STATUS2 | | | + * | | | [15:0] | hsci_master_linkup_status2_alink_table (r) Volatile | + * | | | [19:16] | hsci_master_linkup_status2_alink_fsm (r) Volatile | + * | 0000800e | HSCI_DEBUG_STATUS | | | + * | | | [3:0] | hsci_debug_status_enc_fsm (r) Volatile | + * | | | [6:4] | hsci_debug_status_dec_fsm (r) Volatile | + * | | | [17:8] | hsci_debug_status_capture_word (r) Volatile | + * | | | [18] | hsci_debug_status_parity_error (r) Volatile | + * | | | [19] | hsci_debug_status_unkown_instruction_error (r) Volatile | + * | | | [27:20] | hsci_debug_status_slave_error_code (r) Volatile | + * | 0000800f | MISO_TEST_BER | | | + * | | | [31:0] | miso_test_ber_miso_test_ber (r) Volatile | + * | 00008010 | HSCI_MASTER_LINK_ERR_INFO | | | + * | | | [30:0] | hsci_link_err_info (r) Volatile | + * | 00008011 | HSCI_RATE_CTRL | | | + * | | | [0] | hsci_mmcm_drp_trig (r/w) | + * | | | [2:1] | hsci_rate_sel (r/w) | + * | | | [8] | hsci_pll_reset (r/w) | + * | 00008012 | HSCI_MASTER_RST | | | + * | | | [4] | hsci_master_clear_errors (r/w) | + * | | | [8] | hsci_master_rstn (r/w) | + * | 00008013 | HSCI_PHY_STATUS | | | + * | | | [0] | hsci_reset_seq_done (r) Volatile | + * | | | [1] | hsci_phy_pll_locked (r) Volatile | + * | | | [2] | hsci_vtc_rdy_tx (r) Volatile | + * | | | [3] | hsci_vtc_rdy_rx (r) Volatile | + * | | | [4] | hsci_dly_rdy_tx (r) Volatile | + * | | | [5] | hsci_dly_rdy_rx (r) Volatile | + * | 0000801f | HSCI_MASTER_SCRATCH | | | + * | | | [31:0] | scratch_reg (r/w) | + * +----------+----------------------------+---------+-----------------------------------------------------------------------+ + */ + +/* Register map */ +/* definition of register offset for hsci controller */ +#define AXI_HSCI_REVID 0x0000 +#define AXI_HSCI_BUF_RDDATA 0x0001 +#define AXI_HSCI_MODE 0x8001 +#define AXI_HSCI_XFER_NUM 0x8002 +#define AXI_HSCI_ADDR_SIZE 0x8003 +#define AXI_HSCI_BYTE_NUM 0x8004 +#define AXI_HSCI_TARGET 0x8005 +#define AXI_HSCI_CTRL 0x8006 +#define AXI_HSCI_BRAM_ADDR 0x8007 +#define AXI_HSCI_RUN 0x8008 +#define AXI_HSCI_STATUS 0x8009 +#define AXI_HSCI_LINKUP_CTRL 0x800A +#define AXI_HSCI_TEST_CTRL 0x800B +#define AXI_HSCI_LINKUP_STAT 0x800C +#define AXI_HSCI_LINKUP_STAT2 0x800D +#define AXI_HSCI_DEBUG_STAT 0x800E +#define AXI_MISO_TEST_BER 0x800F +#define AXI_HSCI_MASTER_LINK_ERR_INFO 0x8010 +#define AXI_HSCI_RATE_CTRL_ADDR 0x8011 +#define AXI_HSCI_MASTER_RST_ADDR 0x8012 +#define AXI_HSCI_PHY_STATUS_ADDR 0x8013 +#define AXI_HSCI_SCRATCH 0x801F +#define AXI_HSCI_BUF_RDDATA_SIZE 0x7FFF +#define AXI_HSCI_BUF_WRDATA_SIZE (AXI_HSCI_BUF_RDDATA_SIZE - 4) + +#define AXI_HSCI_RATE_CTRL_MSK GENMASK(2, 1) +#define AXI_HSCI_LINKUP_CTRL_MOSI_CLK_INV BIT(12) +#define AXI_HSCI_LINKUP_CTRL_MISO_CLK_INV BIT(13) + +#define HSCI_READ_LEN 0xBEEF0001 +#define HSCI_READ_CNT 0xBEEF0002 +#define HSCI_WRITE_LEN 0xBEEF0003 +#define HSCI_WRITE_CNT 0xBEEF0004 + +/* Private driver data */ + +struct axi_hsci_state { + struct device *dev; + struct list_head entry; + struct clk *pclk; + void __iomem *regs; + struct dentry *debugdir; + + /* + * The update lock is used to prevent races when updating + * partial registers, see axi_hsci_write_mask. + * Additionally, lifecycle changes are managed by this + * mutex. + */ + struct mutex update_lock; + u32 version; + struct kref kref; + bool initialized; + bool silent; + struct device_node *of_node; + u32 linkup_ctrl; + u64 stat_read_len; + u64 stat_read_cnt; + u64 stat_write_len; + u64 stat_write_cnt; +}; + +static LIST_HEAD(probed_devices); +static DEFINE_MUTEX(probed_devices_lock); +static int32_t axi_hsci_wait_done(struct axi_hsci_state *st); + +/** + * axi_hsci_write - Write a value to a register in the AXI HSCI device + * @st: Pointer to the axi_hsci_state structure representing the device state + * @reg: Register address to write to + * @val: Value to write to the register + * + * This function writes a value to a register in the AXI HSCI device. It first prints a + * debug message indicating the register address, physical address, and value being written. + * Then, it uses the iowrite32() function to write the value to the register. !TODO: If the debug + * flag is enabled, it reads the value from the register and compares it with the value that was + * written. If the values do not match, it prints an error message indicating the register address, + * physical address, and the expected and actual values. + */ +static void axi_hsci_write(struct axi_hsci_state *st, u32 reg, u32 val) +{ + iowrite32(val, st->regs + (reg * 4)); +} + +/** + * axi_hsci_read - Read a value from a register in the AXI HSCI device + * @st: Pointer to the AXI HSCI device state structure + * @reg: Register offset to read from + * + * This function reads a value from a register in the AXI HSCI device. + * It uses the ioread32() function to read the value from the device's + * memory-mapped registers. The register offset is multiplied by 4 to + * convert it to the byte offset. + * + * Returns the value read from the register. + */ +static u32 axi_hsci_read(struct axi_hsci_state *st, u32 reg) +{ + return ioread32(st->regs + (reg * 4)); +} + +/** + * axi_hsci_write_mask - Write a value to a register with a mask + * @st: Pointer to the axi_hsci_state structure + * @reg: Register address + * @val: Value to be written + * @mask: Mask to apply to the value before writing + * + * This function writes a value to a register with a mask. It first reads the + * current value of the register, clears the bits specified by the mask, and + * then sets the bits specified by the value and mask. Finally, it writes the + * modified value back to the register. + */ +static void axi_hsci_write_mask(struct axi_hsci_state *st, u32 reg, u32 val, + u32 mask) +{ + u32 data; + + data = axi_hsci_read(st, reg) & ~mask; + data |= val & mask; + + axi_hsci_write(st, reg, data); +} + +/** + * axi_hsci_wait_link_active - Waits for the HSCI link to become active. + * @st: Pointer to the HSCI state structure. + * + * This function polls the HSCI link status register to check if the link + * is active. It reads the status register up to 1000 times or until the + * link becomes active, whichever comes first. + * + * Return: 0 if the link becomes active, -EIO otherwise. + */ +static int axi_hsci_wait_link_active(struct axi_hsci_state *st) +{ + u32 cnt = 0, status = 0; + int ret = -EIO; + + do { + status = axi_hsci_read(st, AXI_HSCI_LINKUP_STAT); + + if ((status & 0x1) == 1) + ret = 0; + + } while ((cnt++ < 1000) && (ret != 0)); + + return ret; +} + +/** + * axi_hsci_silent - Enable or disable silent mode for AXI HSCI + * @st: Pointer to the AXI HSCI state structure + * @enable: Boolean value indicating whether to enable or disable silent mode + * + * This function is used to enable or disable silent mode for the AXI HSCI + * driver. When silent mode is enabled, the driver will suppress debug and + * informational messages. The @st parameter is a pointer to the AXI HSCI + * state structure. The @enable parameter is a boolean value indicating + * whether to enable or disable silent mode. + * + * Returns 0 in success, -ENODEV otherwise + */ +int axi_hsci_silent(struct axi_hsci_state *st, bool enable) +{ + guard(mutex)(&st->update_lock); + if (!st->initialized) + return -ENODEV; + + st->silent = enable; + return 0; +} +EXPORT_SYMBOL_GPL(axi_hsci_silent); + +/** + * axi_hsci_manual_linkup - Manually control the link-up status of AXI HSCI + * @st: Pointer to the AXI HSCI state structure + * @enable: Flag to enable or disable link-up control (0 - disable, 1 - enable) + * @link_up_signal_bits: Bitmask representing the link-up signal bits + * + * This function allows manual control of the link-up status of the AXI HSCI. + * It sets the link-up control register with the specified enable flag and + * link-up signal bits. The enable flag determines whether link-up control is + * enabled or disabled, while the link-up signal bits represent the specific + * bits to be set in the link-up control register. + * + * Return: Always returns 0 unless the device is not present (-ENODEV). + */ +int axi_hsci_manual_linkup(struct axi_hsci_state *st, u8 enable, + uint16_t link_up_signal_bits) +{ + dev_dbg(st->dev, "%s:%d\n", __func__, __LINE__); + + guard(mutex)(&st->update_lock); + if (!st->initialized) + return -ENODEV; + + axi_hsci_write(st, AXI_HSCI_LINKUP_CTRL, st->linkup_ctrl | + ((enable & 0x01) << 10) | ((link_up_signal_bits & 0x3FF))); + + return 0; +} +EXPORT_SYMBOL_GPL(axi_hsci_manual_linkup); + +/** + * axi_hsci_auto_linkup - Configures the automatic linkup for the HSCI interface. + * @st: Pointer to the axi_hsci_state structure. + * @enable: Enable or disable the automatic linkup (1 to enable, 0 to disable). + * @hscim_mosi_clk_inv: Invert the MOSI clock (1 to invert, 0 to keep as is). + * @hscim_miso_clk_inv: Invert the MISO clock (1 to invert, 0 to keep as is). + * + * This function configures the automatic linkup control register of the HSCI + * interface based on the provided parameters. If the linkup is disabled, it + * also performs a reset sequence on the HSCI master. + * + * Return: Always returns 0. + */ +int axi_hsci_auto_linkup(struct axi_hsci_state *st, u8 enable, + u8 hscim_mosi_clk_inv, u8 hscim_miso_clk_inv) +{ + dev_dbg(st->dev, "%s:%d\n", __func__, __LINE__); + + guard(mutex)(&st->update_lock); + if (!st->initialized) + return -ENODEV; + + axi_hsci_write(st, AXI_HSCI_LINKUP_CTRL, ((enable & 0x01) << 11) | + ((hscim_mosi_clk_inv & 0x01) << 12) | + ((hscim_miso_clk_inv & 0x01) << 13)); + + if (!enable) { + axi_hsci_write(st, AXI_HSCI_MASTER_RST_ADDR, 0x00); + axi_hsci_write(st, AXI_HSCI_MASTER_RST_ADDR, 0x100); + } + + return 0; +} +EXPORT_SYMBOL_GPL(axi_hsci_auto_linkup); + +/** + * axi_hsci_alink_tbl_get - Retrieve the ALINK table value. + * @st: Pointer to the axi_hsci_state structure. + * @hscim_alink_table: Pointer to a u16 variable where the ALINK table value will be stored. + * + * This function reads the ALINK table value from the hardware and stores it in the provided + * variable. It first waits for the link to become active. If the link is active, it reads the + * ALINK table value from the AXI_HSCI_LINKUP_STAT2 register and stores the lower 16 bits of the + * read value in the provided variable. If the link is not active, it returns an error. + * + * Return: 0 on success, -EIO if the link is not active. + */ +int axi_hsci_alink_tbl_get(struct axi_hsci_state *st, u16 *hscim_alink_table) +{ + u32 reg_read; + + guard(mutex)(&st->update_lock); + if (!st->initialized) + return -ENODEV; + + if (axi_hsci_wait_link_active(st) == 0) { + reg_read = axi_hsci_read(st, AXI_HSCI_LINKUP_STAT2); + *hscim_alink_table = reg_read & 0xFFFF; + return 0; + } + + return -EIO; +} +EXPORT_SYMBOL_GPL(axi_hsci_alink_tbl_get); + +/** + * axi_hsci_readm - Read data from AXI HSCI device + * @st: Pointer to the axi_hsci_state structure representing the device state + * @tx_data: Pointer to the transmit data buffer + * @rx_data: Pointer to the receive data buffer + * @num_tx_rx_bytes: Number of bytes to transmit and receive + * @addr_len: Address length in bytes + * @data_len: Data length in bytes + * @stream_len: Number of streams to read + * + * This function reads data from the AXI HSCI device. It takes the transmit data buffer, + * receive data buffer, number of bytes to transmit and receive, address length, data length, + * and number of streams as input parameters. It returns 0 on success and a negative error + * code on failure. + * + * The function first checks if the address length is supported. If not, it returns an error. + * It then calculates the total length of data to be read and updates the statistics. + * If the data length is not supported, the function returns an error. + * + * The function then writes the transmit data to the BRAM (Block RAM) of the device and starts + * the transaction. It waits for the transaction to complete and then reads the data from the BRAM. + * If the number of streams is greater than or equal to 2, the function reads the data in chunks + * of 4 bytes and stores it in the receive data buffer. If the data length is 1, 2, or 4 bytes, + * the function reads the data accordingly and stores it in the receive data buffer. + * + * If the transaction is successful, the function updates the statistics and returns 0. + * If the transaction fails or the device is busy, the function returns an error. + * + * Returns: 0 on success, negative error code on failure + */ +int axi_hsci_readm(struct axi_hsci_state *st, const u8 *tx_data, u8 *rx_data, u32 num_tx_rx_bytes, + u8 addr_len, u8 data_len, u32 stream_len) +{ + int ret = -EFAULT; + u32 addr = 0; + u32 bram_addr = 0x1000; + u32 rdData = 0; + u32 i, word_size, byte_size, len; + + if (addr_len != 4) { + dev_err(st->dev, "HSCI addr size not supported\n"); + return -EINVAL; + } + + guard(mutex)(&st->update_lock); + if (!st->initialized) + return -ENODEV; + + len = data_len * stream_len; + + st->stat_read_len += len; + + if (len >= AXI_HSCI_BUF_RDDATA_SIZE) { + dev_err(st->dev, "HSCI data size not supported\n"); + return -EINVAL; + } + + addr = get_unaligned_le32(tx_data); + + dev_dbg(st->dev, "%s: addr 0x%x len %d\n", __func__, addr, len); + + if (!axi_hsci_wait_done(st)) { + axi_hsci_write(st, AXI_HSCI_BRAM_ADDR, bram_addr); + axi_hsci_write(st, bram_addr, addr); + axi_hsci_write(st, AXI_HSCI_XFER_NUM, 1); + axi_hsci_write(st, AXI_HSCI_ADDR_SIZE, 3); + axi_hsci_write(st, AXI_HSCI_BYTE_NUM, len); + axi_hsci_write(st, AXI_HSCI_CTRL, ((0 & 0x3) << 4) | (1 & 0x3)); + axi_hsci_write(st, AXI_HSCI_RUN, 1); + + if (!axi_hsci_wait_done(st)) { + if (stream_len >= 2) { + word_size = len / 4; + byte_size = len % 4; + + for (i = 0; i < word_size; i++) { + rdData = axi_hsci_read(st, AXI_HSCI_BUF_RDDATA + i); + put_unaligned_le32(rdData, &rx_data[4 + (i * 4)]); + } + + if (byte_size != 0) + rdData = axi_hsci_read(st, AXI_HSCI_BUF_RDDATA + word_size); + + for (i = 0; i < byte_size; i++) + rx_data[4 + (word_size * 4) + i] = rdData >> (8 * i); + + ret = 0; + } else { + if (data_len == 1) { + rdData = axi_hsci_read(st, AXI_HSCI_BUF_RDDATA) & 0xFF; + rx_data[4] = rdData; + ret = 0; + } else if (data_len == 2) { + rdData = axi_hsci_read(st, AXI_HSCI_BUF_RDDATA) & 0xFFFF; + put_unaligned_be16(rdData, &rx_data[4]); + ret = 0; + } else if (data_len == 4) { + rdData = axi_hsci_read(st, AXI_HSCI_BUF_RDDATA); + put_unaligned_be32(rdData, &rx_data[4]); + ret = 0; + } else { + return -EFAULT; + } + } + } + } else { + dev_err(st->dev, "HSCI Master busy. Transaction Failed!"); + return -EBUSY; + } + + st->stat_read_cnt++; + + return ret; +} +EXPORT_SYMBOL_GPL(axi_hsci_readm); + +/** + * axi_hsci_writem - Write data to the AXI HSCI device + * @st: Pointer to the axi_hsci_state structure representing the device state + * @tx_data: Array of bytes containing the data to be written + * @num_tx_rx_bytes: Number of bytes to be transmitted and received + * @addr_len: Length of the address in bytes + * @data_len: Length of the data in bytes + * @stream_len: Length of the stream in bytes + * + * This function writes data to the AXI HSCI device. It takes the device state, + * the data to be written, the number of bytes to be transmitted and received, + * the length of the address, the length of the data, and the length of the stream + * as parameters. It returns 0 on success or a negative error code on failure. + */ +int axi_hsci_writem(struct axi_hsci_state *st, const u8 *tx_data, + u32 num_tx_rx_bytes, u8 addr_len, u8 data_len, u32 stream_len) +{ + int ret = -EFAULT; + u32 addr = 0; + u32 bram_addr = 0x0001; + u32 wrData = 0; + u32 i, word_size, byte_size, len; + + if (addr_len != 4) { + dev_err(st->dev, "HSCI addr size not supported\n"); + return -EINVAL; + } + + guard(mutex)(&st->update_lock); + if (!st->initialized) + return -ENODEV; + + len = data_len * stream_len; + st->stat_write_len += len; + + if (len >= AXI_HSCI_BUF_WRDATA_SIZE) { + dev_err(st->dev, "HSCI data size not supported\n"); + return -EINVAL; + } + + addr = get_unaligned_le32(tx_data); + + dev_dbg(st->dev, "%s: addr 0x%x len %d\n", __func__, addr, len); + + if (axi_hsci_wait_done(st) == 0) { + //Write BRAM + axi_hsci_write(st, AXI_HSCI_BRAM_ADDR, bram_addr); + axi_hsci_write(st, bram_addr, addr); + bram_addr = bram_addr + 1; + + if (stream_len >= 2) { + word_size = len / 4; + byte_size = len % 4; + + for (i = 0; i < word_size; i++) { + wrData = get_unaligned_le32(&tx_data[4 + (i * 4)]); + axi_hsci_write(st, bram_addr + i, wrData); + } + + if (word_size != 0) { + axi_hsci_write(st, AXI_HSCI_XFER_NUM, 1); + axi_hsci_write(st, AXI_HSCI_ADDR_SIZE, 3); + axi_hsci_write(st, AXI_HSCI_BYTE_NUM, (word_size * 4)); + axi_hsci_write(st, AXI_HSCI_CTRL, ((1 & 0x3) << 4) | (0 & 0x3)); + axi_hsci_write(st, AXI_HSCI_RUN, 1); + if (axi_hsci_wait_done(st) == 0) + ret = 0; + } + + wrData = 0; + for (i = 0; i < byte_size; i++) + wrData |= (tx_data[4 + (word_size * 4) + i] << (8 * i)); + + if (byte_size != 0) { + axi_hsci_write(st, AXI_HSCI_BRAM_ADDR, bram_addr); + axi_hsci_write(st, bram_addr, + addr + (word_size * 4)); + axi_hsci_write(st, bram_addr + 1, wrData); + axi_hsci_write(st, AXI_HSCI_XFER_NUM, 1); + axi_hsci_write(st, AXI_HSCI_ADDR_SIZE, 3); + axi_hsci_write(st, AXI_HSCI_BYTE_NUM, byte_size); + axi_hsci_write(st, AXI_HSCI_CTRL, ((0 & 0x3) << 4) | (0 & 0x3)); + axi_hsci_write(st, AXI_HSCI_RUN, 1); + if (axi_hsci_wait_done(st) == 0) + ret = 0; + } + } else { + if (data_len == 1) { + wrData = tx_data[4]; + axi_hsci_write(st, bram_addr, wrData); + } else if (data_len == 2) { + wrData = get_unaligned_le16(&tx_data[4]); + axi_hsci_write(st, bram_addr, wrData); + } else if (data_len == 4) { + wrData = get_unaligned_le32(&tx_data[4]); + axi_hsci_write(st, bram_addr, wrData); + } else { + return -EINVAL; + } + axi_hsci_write(st, AXI_HSCI_XFER_NUM, 1); + axi_hsci_write(st, AXI_HSCI_ADDR_SIZE, 3); + /* bytes can be transferred for single transaction */ + axi_hsci_write(st, AXI_HSCI_BYTE_NUM, data_len); + /* HSCI SLAVE AHB TSIZE and CMD SEL */ + axi_hsci_write(st, AXI_HSCI_CTRL, ((0 & 0x3) << 4) | (0 & 0x3)); + axi_hsci_write(st, AXI_HSCI_RUN, 1); + if (axi_hsci_wait_done(st) == 0) + ret = 0; + } + } else { + dev_err(st->dev, "HSCI Master busy. Transaction Failed!"); + return -EBUSY; + } + + st->stat_write_cnt++; + + return ret; +} +EXPORT_SYMBOL_GPL(axi_hsci_writem); + +/** + * axi_hsci_dbg_get - Get debug information from AXI HSCI device + * @data: Pointer to the AXI HSCI device state structure + * @val: Pointer to store the retrieved value + * @offset: Offset of the debug information to retrieve + * @mask: Mask to apply to the retrieved value + * @shift: Number of bits to shift the retrieved value + * + * This function is used to retrieve debug information from the AXI HSCI device. + * The debug information is specified by the @offset parameter, which determines + * which debug information to retrieve. The retrieved value is stored in the + * memory pointed to by @val. + * + * Return: 0 on success, negative error code on failure + */ +static int axi_hsci_dbg_get(void *data, u64 *val, size_t offset, u32 mask, + int shift) +{ + struct axi_hsci_state *st = data; + u64 rdata; + + guard(mutex)(&st->update_lock); + + switch (offset) { + case HSCI_READ_LEN: + rdata = st->stat_read_len; + break; + case HSCI_READ_CNT: + rdata = st->stat_read_cnt; + break; + case HSCI_WRITE_LEN: + rdata = st->stat_write_len; + break; + case HSCI_WRITE_CNT: + rdata = st->stat_write_cnt; + break; + default: + rdata = (axi_hsci_read(st, offset) & mask) >> shift; + } + + *val = rdata; + + return 0; +} + +/** + * axi_hsci_dbg_set - Set a debug value in the AXI HSCI device + * @data: Pointer to the AXI HSCI device state structure + * @val: Value to be set + * @offset: Offset of the register to be modified + * @mask: Bit mask to apply to the register value + * @shift: Number of bits to shift the value before applying the mask + * + * This function sets a debug value in the AXI HSCI device. It takes a pointer to + * the AXI HSCI device state structure, the value to be set, the offset of the + * register to be modified, the bit mask to apply to the register value, and the + * number of bits to shift the value before applying the mask. + * + * If the input value is greater than UINT_MAX, indicating that it doesn't fit + * into 32 bits, the function returns -EINVAL. + * + * The function acquires the update lock to ensure exclusive access to the device + * state. It then writes the modified value to the specified register using the + * provided offset, mask, and shift. Finally, it releases the update lock. + * + * Return: 0 on success, -EINVAL if the input value is too large + */ +static int axi_hsci_dbg_set(void *data, u64 val, size_t offset, u32 mask, + int shift) +{ + struct axi_hsci_state *st = data; + u32 n = val; + + /* Input value didn't fit into 32 bit */ + if (val > UINT_MAX) + return -EINVAL; + + scoped_guard(mutex, &st->update_lock) + axi_hsci_write_mask(st, offset, n << shift, mask); + + return 0; +} + +struct axi_do_dbg_attr { + char *name; + umode_t mode; + const struct file_operations *fops; + int (*get)(void *t, u64 *v); +}; + +static struct dentry *axi_hsci_dbg_parent; + +#define ADI_REG_DEVICE_ATTR(_name, _mode, _off, _mask, _shift, _fmt) \ +static int axi_hsci_dbg_ ## _name ## _get(void *data, u64 *val) \ +{ \ + return axi_hsci_dbg_get(data, val, _off, _mask, _shift); \ +} \ +static int axi_hsci_dbg_ ## _name ## _set(void *data, u64 val) \ +{ \ + return axi_hsci_dbg_set(data, val, _off, _mask, _shift); \ +} \ +DEFINE_DEBUGFS_ATTRIBUTE(axi_hsci_dbg_ ## _name, \ + axi_hsci_dbg_ ## _name ## _get, \ + axi_hsci_dbg_ ## _name ## _set, \ + _fmt); \ +static struct axi_do_dbg_attr axi_hsci_dbg_ ## _name ## _attr = { \ + .name = __stringify(_name), \ + .mode = _mode, \ + .fops = &axi_hsci_dbg_ ## _name, \ + .get = &axi_hsci_dbg_ ## _name ## _get \ +} + +ADI_REG_DEVICE_ATTR(revision_id_hsci_revision_id, 0444, AXI_HSCI_REVID, + GENMASK(15, 0), 0, "%llu\n"); +ADI_REG_DEVICE_ATTR(_hsci_xfer_mode, 0644, AXI_HSCI_MODE, GENMASK(1, 0), 0, + "%llu\n"); +ADI_REG_DEVICE_ATTR(_ver_b_na, 0644, AXI_HSCI_MODE, BIT(4), 4, "%llu\n"); +ADI_REG_DEVICE_ATTR(hsci_master_xfer_num_hsci_xfer_num, 0644, AXI_HSCI_XFER_NUM, + GENMASK(15, 0), 0, "%llu\n"); +ADI_REG_DEVICE_ATTR(hsci_master_addr_size_hsci_addr_size, 0644, + AXI_HSCI_ADDR_SIZE, GENMASK(2, 0), 0, "%llu\n"); +ADI_REG_DEVICE_ATTR(hsci_master_byte_num_hsci_byte_num, 0644, AXI_HSCI_BYTE_NUM, + GENMASK(16, 0), 0, "%llu\n"); +ADI_REG_DEVICE_ATTR(hsci_master_target_spi_target, 0644, AXI_HSCI_TARGET, + GENMASK(31, 0), 0, "%llu\n"); +ADI_REG_DEVICE_ATTR(hsci_master_ctrl_hsci_cmd_sel, 0644, AXI_HSCI_CTRL, + GENMASK(1, 0), 0, "%llu\n"); +ADI_REG_DEVICE_ATTR(hsci_master_ctrl_hsci_slave_ahb_tsize, 0644, AXI_HSCI_CTRL, + GENMASK(5, 4), 4, "%llu\n"); +ADI_REG_DEVICE_ATTR(hsci_master_bram_address_hsci_bram_start_address, 0644, + AXI_HSCI_BRAM_ADDR, GENMASK(15, 0), 0, "0x%llX\n"); +ADI_REG_DEVICE_ATTR(hsci_master_run_hsci_run, 0644, AXI_HSCI_RUN, BIT(0), 0, + "%llu\n"); +ADI_REG_DEVICE_ATTR(hsci_master_status_master_done, 0444, AXI_HSCI_STATUS, + BIT(0), 0, "%llu\n"); +ADI_REG_DEVICE_ATTR(hsci_master_status_master_running, 0444, AXI_HSCI_STATUS, + BIT(1), 1, "%llu\n"); +ADI_REG_DEVICE_ATTR(hsci_master_status_master_wr_in_prog, 0444, AXI_HSCI_STATUS, + BIT(2), 2, "%llu\n"); +ADI_REG_DEVICE_ATTR(hsci_master_status_master_rd_in_prog, 0444, AXI_HSCI_STATUS, + BIT(3), 3, "%llu\n"); +ADI_REG_DEVICE_ATTR(hsci_master_status_miso_test_lfsr_acq, 0444, + AXI_HSCI_STATUS, BIT(4), 4, "%llu\n"); +ADI_REG_DEVICE_ATTR(hsci_master_linkup_ctrl_hsci_man_linkup_word, 0644, + AXI_HSCI_LINKUP_CTRL, GENMASK(9, 0), 0, "%llu\n"); +ADI_REG_DEVICE_ATTR(hsci_master_linkup_ctrl_hsci_man_linkup, 0644, + AXI_HSCI_LINKUP_CTRL, BIT(10), 10, "%llu\n"); +ADI_REG_DEVICE_ATTR(hsci_master_linkup_ctrl_hsci_auto_linkup, 0644, + AXI_HSCI_LINKUP_CTRL, BIT(11), 11, "%llu\n"); +ADI_REG_DEVICE_ATTR(hsci_master_linkup_ctrl_mosi_clk_inv, 0644, + AXI_HSCI_LINKUP_CTRL, BIT(12), 12, "%llu\n"); +ADI_REG_DEVICE_ATTR(hsci_master_linkup_ctrl_miso_clk_inv, 0644, + AXI_HSCI_LINKUP_CTRL, BIT(13), 13, "%llu\n"); +ADI_REG_DEVICE_ATTR(hsci_master_test_ctrl_hsci_mosi_test_mode, 0644, + AXI_HSCI_TEST_CTRL, BIT(0), 0, "%llu\n"); +ADI_REG_DEVICE_ATTR(hsci_master_test_ctrl_hsci_miso_test_mode, 0644, + AXI_HSCI_TEST_CTRL, BIT(1), 1, "%llu\n"); +ADI_REG_DEVICE_ATTR(hsci_master_test_ctrl_hsci_capture_mode, 0644, + AXI_HSCI_TEST_CTRL, BIT(2), 2, "%llu\n"); +ADI_REG_DEVICE_ATTR(hsci_master_linkup_status_link_active, 0444, + AXI_HSCI_LINKUP_STAT, BIT(0), 0, "%llu\n"); +ADI_REG_DEVICE_ATTR(hsci_master_linkup_status_alink_txclk_adj, 0444, + AXI_HSCI_LINKUP_STAT, GENMASK(7, 4), 4, "%llu\n"); +ADI_REG_DEVICE_ATTR(hsci_master_linkup_status_alink_txclk_inv, 0444, + AXI_HSCI_LINKUP_STAT, BIT(8), 8, "%llu\n"); +ADI_REG_DEVICE_ATTR(hsci_master_linkup_status_txclk_adj_mismatch, 0444, + AXI_HSCI_LINKUP_STAT, BIT(10), 10, "%llu\n"); +ADI_REG_DEVICE_ATTR(hsci_master_linkup_status_txclk_inv_mismatch, 0444, + AXI_HSCI_LINKUP_STAT, BIT(11), 11, "%llu\n"); +ADI_REG_DEVICE_ATTR(hsci_master_linkup_status2_alink_table, 0444, + AXI_HSCI_LINKUP_STAT2, GENMASK(15, 0), 0, "%llu\n"); +ADI_REG_DEVICE_ATTR(hsci_master_linkup_status2_alink_fsm, 0444, + AXI_HSCI_LINKUP_STAT2, GENMASK(19, 16), 16, "%llu\n"); +ADI_REG_DEVICE_ATTR(hsci_debug_status_enc_fsm, 0444, AXI_HSCI_DEBUG_STAT, + GENMASK(3, 0), 0, "%llu\n"); +ADI_REG_DEVICE_ATTR(hsci_debug_status_dec_fsm, 0444, AXI_HSCI_DEBUG_STAT, + GENMASK(6, 4), 4, "%llu\n"); +ADI_REG_DEVICE_ATTR(hsci_debug_status_capture_word, 0444, AXI_HSCI_DEBUG_STAT, + GENMASK(17, 8), 8, "%llu\n"); +ADI_REG_DEVICE_ATTR(hsci_debug_status_parity_error, 0444, AXI_HSCI_DEBUG_STAT, + BIT(18), 18, "%llu\n"); +ADI_REG_DEVICE_ATTR(hsci_debug_status_unkown_instruction_error, 0444, + AXI_HSCI_DEBUG_STAT, BIT(19), 19, "%llu\n"); +ADI_REG_DEVICE_ATTR(hsci_debug_status_slave_error_code, 0444, + AXI_HSCI_DEBUG_STAT, GENMASK(27, 20), 20, "%llu\n"); +ADI_REG_DEVICE_ATTR(miso_test_ber_miso_test_ber, 0444, AXI_MISO_TEST_BER, + GENMASK(31, 0), 0, "%llu\n"); +ADI_REG_DEVICE_ATTR(hsci_master_link_err_info, 0444, + AXI_HSCI_MASTER_LINK_ERR_INFO, GENMASK(30, 0), 0, "%llu\n"); +ADI_REG_DEVICE_ATTR(hsci_mmcm_drp_trig, 0644, AXI_HSCI_RATE_CTRL_ADDR, BIT(0), + 0, "%llu\n"); +ADI_REG_DEVICE_ATTR(hsci_rate_sel, 0644, AXI_HSCI_RATE_CTRL_ADDR, + BIT(1) | BIT(2), 1, "%llu\n"); +ADI_REG_DEVICE_ATTR(hsci_pll_reset, 0644, AXI_HSCI_RATE_CTRL_ADDR, BIT(8), 8, + "%llu\n"); +ADI_REG_DEVICE_ATTR(hsci_master_clear_errors, 0644, AXI_HSCI_MASTER_RST_ADDR, + BIT(4), 4, "%llu\n"); +ADI_REG_DEVICE_ATTR(hsci_master_rstn, 0644, AXI_HSCI_MASTER_RST_ADDR, BIT(8), 8, + "%llu\n"); +ADI_REG_DEVICE_ATTR(hsci_reset_seq_done, 0444, AXI_HSCI_PHY_STATUS_ADDR, BIT(0), + 0, "%llu\n"); +ADI_REG_DEVICE_ATTR(hsci_phy_pll_locked, 0444, AXI_HSCI_PHY_STATUS_ADDR, BIT(1), + 1, "%llu\n"); +ADI_REG_DEVICE_ATTR(hsci_vtc_rdy_tx, 0444, AXI_HSCI_PHY_STATUS_ADDR, BIT(2), 2, + "%llu\n"); +ADI_REG_DEVICE_ATTR(hsci_vtc_rdy_rx, 0444, AXI_HSCI_PHY_STATUS_ADDR, BIT(3), 3, + "%llu\n"); +ADI_REG_DEVICE_ATTR(hsci_dly_rdy_tx, 0444, AXI_HSCI_PHY_STATUS_ADDR, BIT(4), 4, + "%llu\n"); +ADI_REG_DEVICE_ATTR(hsci_dly_rdy_rx, 0444, AXI_HSCI_PHY_STATUS_ADDR, BIT(5), 5, + "%llu\n"); +ADI_REG_DEVICE_ATTR(hsci_master_scratch_scratch_reg, 0444, AXI_HSCI_SCRATCH, + GENMASK(31, 0), 0, "%llu\n"); +ADI_REG_DEVICE_ATTR(stat_read_len, 0444, HSCI_READ_LEN, 0, 0, "%llu\n"); +ADI_REG_DEVICE_ATTR(stat_read_count, 0444, HSCI_READ_CNT, 0, 0, "%llu\n"); +ADI_REG_DEVICE_ATTR(stat_write_len, 0444, HSCI_WRITE_LEN, 0, 0, "%llu\n"); +ADI_REG_DEVICE_ATTR(stat_write_count, 0444, HSCI_WRITE_CNT, 0, 0, "%llu\n"); + +static struct axi_do_dbg_attr *axi_hsci_dbg_attrs[] = { + &axi_hsci_dbg_revision_id_hsci_revision_id_attr, + &axi_hsci_dbg__hsci_xfer_mode_attr, + &axi_hsci_dbg__ver_b_na_attr, + &axi_hsci_dbg_hsci_master_xfer_num_hsci_xfer_num_attr, + &axi_hsci_dbg_hsci_master_addr_size_hsci_addr_size_attr, + &axi_hsci_dbg_hsci_master_byte_num_hsci_byte_num_attr, + &axi_hsci_dbg_hsci_master_target_spi_target_attr, + &axi_hsci_dbg_hsci_master_ctrl_hsci_cmd_sel_attr, + &axi_hsci_dbg_hsci_master_ctrl_hsci_slave_ahb_tsize_attr, + &axi_hsci_dbg_hsci_master_bram_address_hsci_bram_start_address_attr, + &axi_hsci_dbg_hsci_master_run_hsci_run_attr, + &axi_hsci_dbg_hsci_master_status_master_done_attr, + &axi_hsci_dbg_hsci_master_status_master_running_attr, + &axi_hsci_dbg_hsci_master_status_master_wr_in_prog_attr, + &axi_hsci_dbg_hsci_master_status_master_rd_in_prog_attr, + &axi_hsci_dbg_hsci_master_status_miso_test_lfsr_acq_attr, + &axi_hsci_dbg_hsci_master_linkup_ctrl_hsci_man_linkup_word_attr, + &axi_hsci_dbg_hsci_master_linkup_ctrl_hsci_man_linkup_attr, + &axi_hsci_dbg_hsci_master_linkup_ctrl_hsci_auto_linkup_attr, + &axi_hsci_dbg_hsci_master_linkup_ctrl_mosi_clk_inv_attr, + &axi_hsci_dbg_hsci_master_linkup_ctrl_miso_clk_inv_attr, + &axi_hsci_dbg_hsci_master_test_ctrl_hsci_mosi_test_mode_attr, + &axi_hsci_dbg_hsci_master_test_ctrl_hsci_miso_test_mode_attr, + &axi_hsci_dbg_hsci_master_test_ctrl_hsci_capture_mode_attr, + &axi_hsci_dbg_hsci_master_linkup_status_link_active_attr, + &axi_hsci_dbg_hsci_master_linkup_status_alink_txclk_adj_attr, + &axi_hsci_dbg_hsci_master_linkup_status_alink_txclk_inv_attr, + &axi_hsci_dbg_hsci_master_linkup_status_txclk_adj_mismatch_attr, + &axi_hsci_dbg_hsci_master_linkup_status_txclk_inv_mismatch_attr, + &axi_hsci_dbg_hsci_master_linkup_status2_alink_table_attr, + &axi_hsci_dbg_hsci_master_linkup_status2_alink_fsm_attr, + &axi_hsci_dbg_hsci_debug_status_enc_fsm_attr, + &axi_hsci_dbg_hsci_debug_status_dec_fsm_attr, + &axi_hsci_dbg_hsci_debug_status_capture_word_attr, + &axi_hsci_dbg_hsci_debug_status_parity_error_attr, + &axi_hsci_dbg_hsci_debug_status_unkown_instruction_error_attr, + &axi_hsci_dbg_hsci_debug_status_slave_error_code_attr, + &axi_hsci_dbg_miso_test_ber_miso_test_ber_attr, + &axi_hsci_dbg_hsci_master_link_err_info_attr, + &axi_hsci_dbg_hsci_mmcm_drp_trig_attr, + &axi_hsci_dbg_hsci_rate_sel_attr, + &axi_hsci_dbg_hsci_pll_reset_attr, + &axi_hsci_dbg_hsci_master_clear_errors_attr, + &axi_hsci_dbg_hsci_master_rstn_attr, + &axi_hsci_dbg_hsci_reset_seq_done_attr, + &axi_hsci_dbg_hsci_phy_pll_locked_attr, + &axi_hsci_dbg_hsci_vtc_rdy_tx_attr, + &axi_hsci_dbg_hsci_vtc_rdy_rx_attr, + &axi_hsci_dbg_hsci_dly_rdy_tx_attr, + &axi_hsci_dbg_hsci_dly_rdy_rx_attr, + &axi_hsci_dbg_hsci_master_scratch_scratch_reg_attr, + &axi_hsci_dbg_stat_read_len_attr, + &axi_hsci_dbg_stat_read_count_attr, + &axi_hsci_dbg_stat_write_len_attr, + &axi_hsci_dbg_stat_write_count_attr, + NULL /* END OF LIST MARKER */ +}; + +/** + * axi_hsci_wait_done - Wait for the AXI HSCI operation to complete + * @st: Pointer to the axi_hsci_state structure + * + * This function waits for the AXI HSCI operation to complete by continuously + * checking the status register. It returns 0 if the operation completes + * successfully, or -ETIMEDOUT if the operation times out. + * + * The function also handles the case when the operation times out. If the + * operation times out, it unlocks the update lock, prints debug information, + * resets the device, and returns the error code. + * + * Return: 0 if the operation completes successfully, or -ETIMEDOUT if the + * operation times out. + */ + +static int32_t axi_hsci_wait_done(struct axi_hsci_state *st) +{ + int ret = -ETIMEDOUT, i = 0; + u32 cnt = 0; + u32 status = 0; + unsigned long long val; + + do { + status = axi_hsci_read(st, AXI_HSCI_STATUS); + if ((status & 0x1) == 1) + ret = 0; + } while ((cnt++ < 60000) && (ret != 0)); + + if (ret) { + if (!st->silent) { + mutex_unlock(&st->update_lock); + while (axi_hsci_dbg_attrs[i]) { + axi_hsci_dbg_attrs[i]->get(st, &val); + dev_err(st->dev, "%s: %llu\n", axi_hsci_dbg_attrs[i]->name, val); + i++; + } + mutex_lock(&st->update_lock); + + dev_err(st->dev, "%s:%d RESET !!!!! status %x\n", + __func__, __LINE__, status); + } + + axi_hsci_write(st, AXI_HSCI_MASTER_RST_ADDR, 0x00); + axi_hsci_write(st, AXI_HSCI_MASTER_RST_ADDR, 0x100); + } + + return ret; +} + +/** + * axi_hsci_dbg_cleanup - Clean up debugfs entries for AXI HSCI driver + * @data: Pointer to the axi_hsci_state structure + * + * This function is responsible for cleaning up the debugfs entries created + * for the AXI HSCI driver. It removes the debug directory and all its + * subdirectories and files recursively. + */ +static void axi_hsci_dbg_cleanup(void *data) +{ + struct axi_hsci_state *st = data; + + debugfs_remove_recursive(st->debugdir); +} + +#define kref_to_data_offload(x) container_of(x, struct axi_hsci_state, kref) + +/** + * axi_hsci_release - Release function for AXI HSCI driver + * @kref: Pointer to the reference counter structure + * + * This function is called when the reference count of the AXI HSCI driver + * reaches zero. It releases the resources associated with the driver. + * + * @kref: Pointer to the reference counter structure + */ +static void axi_hsci_release(struct kref *kref) +{ + struct axi_hsci_state *st = kref_to_data_offload(kref); + + of_node_put(st->of_node); + kfree(st); +} + +/** + * axi_hsci_put - Release the reference to the AXI HSCI state + * @data: Pointer to the AXI HSCI state structure + * + * This function releases the reference to the AXI HSCI state structure. + * It is called when the reference count reaches zero, indicating that + * the structure is no longer in use. + */ +static void axi_hsci_put(void *data) +{ + struct axi_hsci_state *st = data; + + kref_put(&st->kref, axi_hsci_release); +} + +/** + * axi_hsci_unregister - Unregister an AXI HSCI device + * @data: Pointer to the AXI HSCI device state + * + * This function is used to unregister an AXI HSCI device. It removes the device + * state from the list of probed devices and sets the device's initialized flag + * to false. + */ +static void axi_hsci_unregister(void *data) +{ + struct axi_hsci_state *st = data; + + mutex_lock(&probed_devices_lock); + list_del(&st->entry); + mutex_unlock(&probed_devices_lock); + + mutex_lock(&st->update_lock); + st->initialized = false; + mutex_unlock(&st->update_lock); +} + +/** + * axi_hsci_register - Register an AXI HSCI device + * @dev: Pointer to the device structure + * @st: Pointer to the AXI HSCI state structure + * + * This function is used to register an AXI HSCI device with the Linux kernel. + * It adds the device to the list of probed devices and associates an action + * to unregister the device in case of failure. + * + * Return: 0 on success, negative error code on failure + */ +static int axi_hsci_register(struct device *dev, struct axi_hsci_state *st) +{ + mutex_lock(&probed_devices_lock); + list_add(&st->entry, &probed_devices); + mutex_unlock(&probed_devices_lock); + + return devm_add_action_or_reset(dev, axi_hsci_unregister, st); +} + +/** + * devm_axi_hsci_get_optional - Get an optional AXI HSCI device state + * @dev: Pointer to the device structure + * + * This function is used to get the optional AXI HSCI (High Speed Communication Interface) + * device state associated with the given device. It searches for a device node in the device's + * device tree that is connected to the AXI HSCI and returns the corresponding device state. + * + * Return: Pointer to the AXI HSCI device state on success, NULL if no device node is found, + * or an error pointer if an error occurs. + */ +struct axi_hsci_state *devm_axi_hsci_get_optional(struct device *dev) +{ + struct axi_hsci_state *st; + int ret; + + struct device_node *of_node __free(device_node) = of_parse_phandle(dev->of_node, + "adi,axi-hsci-connected", + 0); + if (!of_node) + return NULL; + + guard(mutex)(&probed_devices_lock); + + list_for_each_entry(st, &probed_devices, entry) { + if (st->of_node != of_node) + continue; + + kref_get(&st->kref); + ret = devm_add_action_or_reset(dev, axi_hsci_put, st); + if (ret) + return ERR_PTR(ret); + + return st; + } + + dev_dbg(dev, "Failed to find requested hsci \"%s\", try again later!\n", + of_node->name); + + return ERR_PTR(-EPROBE_DEFER); +} +EXPORT_SYMBOL_GPL(devm_axi_hsci_get_optional); + +struct axi_hsci_info { + u32 version; +}; + +/** + * axi_hsci_probe - Probe function for the AXI HSCI driver + * @pdev: Pointer to the platform device structure + * + * This function is called when a platform device is being probed. + * It initializes the AXI HSCI driver by performing the following steps: + * - Retrieves the device tree node associated with the platform device + * - Retrieves the AXI HSCI device information from the device tree + * - Allocates memory for the AXI HSCI state structure + * - Initializes the AXI HSCI state structure + * - Retrieves the reference input clock for the AXI HSCI + * - Reads the interface speed from the device tree and sets the corresponding rate selection + * - Sets the clock rate for the AXI HSCI + * - Enables the reference input clock + * - Registers a cleanup action to release resources on device removal + * - Maps the AXI HSCI registers to virtual memory + * - Reads the IP core version and checks if it is compatible with the driver + * - Creates a debugfs directory for the AXI HSCI device and registers debugfs files + * - Writes the rate selection to the AXI HSCI rate control register + * - Checks the status of the HSCI Master PHY + * - Enables the HSCI Master + * - Registers the AXI HSCI device with other drivers + * + * Return: 0 on success, negative error code on failure + */ +static int axi_hsci_probe(struct platform_device *pdev) +{ + int ret; + struct axi_hsci_state *st; + const struct axi_hsci_info *info; + struct device_node *np = pdev->dev.of_node; + struct axi_do_dbg_attr **i; + u32 reg_val, interface_rate, hsci_rate_sel; + + dev_dbg(&pdev->dev, "Device Tree Probing \'%s\'\n", np->name); + + info = of_device_get_match_data(&pdev->dev); + if (!info) + return -ENODEV; + + st = kzalloc(sizeof(*st), GFP_KERNEL); + if (!st) + return -ENOMEM; + + st->dev = &pdev->dev; + st->of_node = of_node_get(np); + + ret = devm_mutex_init(&pdev->dev, &st->update_lock); + if (ret) + return ret; + + kref_init(&st->kref); + + st->pclk = devm_clk_get(&pdev->dev, "pclk"); + if (IS_ERR(st->pclk)) + return dev_err_probe(&pdev->dev, PTR_ERR(st->pclk), + "failed to get the reference input clock\n"); + + interface_rate = 800; + ret = of_property_read_u32(np, "adi,hsci-interface-speed-mhz", &interface_rate); + + switch (interface_rate) { + case 800: + hsci_rate_sel = 0; + break; + case 400: + hsci_rate_sel = 1; + break; + case 200: + hsci_rate_sel = 2; + break; + default: + return dev_err_probe(&pdev->dev, -EINVAL, + "Invalid adi,hsci-interface-speed-mhz\n"); + } + + if (of_property_read_bool(np, "adi,hsci-miso-clk-inv-en")) + st->linkup_ctrl |= AXI_HSCI_LINKUP_CTRL_MISO_CLK_INV; + + if (of_property_read_bool(np, "adi,hsci-mosi-clk-inv-en")) + st->linkup_ctrl |= AXI_HSCI_LINKUP_CTRL_MOSI_CLK_INV; + + ret = clk_set_rate(st->pclk, interface_rate * 1000000 / 4); + if (ret) + return dev_err_probe(&pdev->dev, ret, "clk_set_rate\n"); + + ret = clk_prepare_enable(st->pclk); + if (ret) + return dev_err_probe(&pdev->dev, ret, "clk_prepare_enable\n"); + + ret = devm_add_action_or_reset(&pdev->dev, axi_hsci_put, st); + if (ret) + return dev_err_probe(&pdev->dev, ret, "devm_add_action_or_reset\n"); + + st->regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(st->regs)) + return dev_err_probe(&pdev->dev, PTR_ERR(st->regs), + "devm_platform_ioremap_resource\n"); + + st->version = axi_hsci_read(st, AXI_HSCI_REVID); + if (info->version > st->version) { + return dev_err_probe(&pdev->dev, -ENODEV, + "IP core version is too old. Expected %d.0.0, Reported %d.0.0\n", + info->version, st->version); + } + + if (!IS_ERR(axi_hsci_dbg_parent)) { + st->debugdir = debugfs_create_dir(np->name, axi_hsci_dbg_parent); + if (!IS_ERR(st->debugdir)) { + for (i = axi_hsci_dbg_attrs; *i; i++) + debugfs_create_file_unsafe((*i)->name, (*i)->mode, + st->debugdir, st, (*i)->fops); + + ret = devm_add_action_or_reset(&pdev->dev, axi_hsci_dbg_cleanup, st); + if (ret) + return ret; + } + } + + axi_hsci_write_mask(st, AXI_HSCI_RATE_CTRL_ADDR, + FIELD_PREP(AXI_HSCI_RATE_CTRL_MSK, hsci_rate_sel), + AXI_HSCI_RATE_CTRL_MSK); + + /* Check HSCI Master PHY status */ + reg_val = axi_hsci_read(st, AXI_HSCI_PHY_STATUS_ADDR); + if (reg_val != 0x3F) + dev_warn(&pdev->dev, "HSCI PHY is 0x%X, expected 0x3F\n", reg_val); + + /* Enable the HSCI Master */ + axi_hsci_write(st, AXI_HSCI_MASTER_RST_ADDR, 0x100); + + /* Check HSCI Master PHY status */ + reg_val = axi_hsci_read(st, AXI_HSCI_PHY_STATUS_ADDR); + if (reg_val != 0x3F) + dev_warn(&pdev->dev, "HSCI PHY is 0x%X, expected 0x3F\n", reg_val); + + st->initialized = true; + + /* Register device for other drivers to access */ + ret = axi_hsci_register(&pdev->dev, st); + if (ret) + return ret; + + /* Done */ + dev_dbg(&pdev->dev, "AXI HSCI IP core (%d.0.0) probed @ %u MHz\n", + st->version, interface_rate); + + return 0; +} + +static const struct axi_hsci_info axi_hsci_1_0_a_info = { + .version = 1, +}; + +/* Match table for of_platform binding */ +static const struct of_device_id axi_hsci_of_match[] = { + { .compatible = "adi,axi-hsci-1.0.a", .data = &axi_hsci_1_0_a_info }, + { /* end of list */ } +}; +MODULE_DEVICE_TABLE(of, axi_hsci_of_match); + +static struct platform_driver axi_hsci_driver = { + .driver = { + .name = KBUILD_MODNAME, + .of_match_table = axi_hsci_of_match, + }, + .probe = axi_hsci_probe +}; + +static int axi_hsci_driver_register(struct platform_driver *driver) +{ + axi_hsci_dbg_parent = debugfs_create_dir(KBUILD_MODNAME, NULL); + return platform_driver_register(driver); +} + +static void axi_hsci_driver_unregister(struct platform_driver *driver) +{ + debugfs_remove_recursive(axi_hsci_dbg_parent); + platform_driver_unregister(driver); +} + +module_driver(axi_hsci_driver, + axi_hsci_driver_register, + axi_hsci_driver_unregister); + +MODULE_AUTHOR("Michael Hennerich "); +MODULE_DESCRIPTION("Analog Devices hsci interface driver"); +MODULE_LICENSE("Dual BSD/GPL"); diff --git a/drivers/misc/adi-axi-hsci.h b/drivers/misc/adi-axi-hsci.h new file mode 100644 index 00000000000000..0002585ac97a26 --- /dev/null +++ b/drivers/misc/adi-axi-hsci.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Analog Devices AXI HSCI interface + * + * Copyright 2023 Analog Devices Inc. + * + * Wiki: https://wiki.analog.com/resources/fpga/docs/hsci + */ + +#ifndef ADI_AXI_HSCI_H_ +#define ADI_AXI_HSCI_H_ + +#include +#include + +struct axi_hsci_state; + +int axi_hsci_silent(struct axi_hsci_state *st, bool enable); + +int axi_hsci_alink_tbl_get(struct axi_hsci_state *st, + u16 *hscim_alink_table); + +int axi_hsci_manual_linkup(struct axi_hsci_state *st, u8 enable, + u16 link_up_signal_bits); + +int axi_hsci_auto_linkup(struct axi_hsci_state *st, u8 enable, + u8 hscim_mosi_clk_inv, u8 hscim_miso_clk_inv); + +int axi_hsci_readm(struct axi_hsci_state *st, const u8 tx_data[], u8 rx_data[], + u32 num_tx_rx_bytes, u8 addr_len, u8 data_len, + u32 stream_len); + +int axi_hsci_writem(struct axi_hsci_state *st, const u8 tx_data[], + u32 num_tx_rx_bytes, u8 addr_len, u8 data_len, + u32 stream_len); + +struct axi_hsci_state *devm_axi_hsci_get_optional(struct device *source); + +#endif /* ADI_AXI_HSCI_H_ */ diff --git a/firmware/204C_M4_L1_NP16_20p0_16x4.bin b/firmware/204C_M4_L1_NP16_20p0_16x4.bin new file mode 100644 index 00000000000000..12de8525409bc9 Binary files /dev/null and b/firmware/204C_M4_L1_NP16_20p0_16x4.bin differ diff --git a/firmware/204C_M4_L4_NP16_20p0_4x4.bin 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00000000000000..56b85282fd3148 Binary files /dev/null and b/firmware/id01_uc42.bin differ diff --git a/firmware/id01_uc43.bin b/firmware/id01_uc43.bin new file mode 100644 index 00000000000000..8fae77e1324171 Binary files /dev/null and b/firmware/id01_uc43.bin differ diff --git a/include/dt-bindings/iio/adc/adi,ad9088.h b/include/dt-bindings/iio/adc/adi,ad9088.h new file mode 100644 index 00000000000000..02a74af6be54fc --- /dev/null +++ b/include/dt-bindings/iio/adc/adi,ad9088.h @@ -0,0 +1,24 @@ +/* + * Driver for AD9088 and similar high-speed MxFEs + * + * Copyright 2022 Analog Devices Inc. + * + * Licensed under the GPL-2. + */ +#ifndef _DT_BINDINGS_IIO_ADC_AD9088_H +#define _DT_BINDINGS_IIO_ADC_AD9088_H + + + /* + * JESD204-FSM defines + */ +#define DEFRAMER_LINK_A0_TX 0 +#define DEFRAMER_LINK_A1_TX 1 +#define DEFRAMER_LINK_B0_TX 2 +#define DEFRAMER_LINK_B1_TX 3 +#define FRAMER_LINK_A0_RX 4 +#define FRAMER_LINK_A1_RX 5 +#define FRAMER_LINK_B0_RX 6 +#define FRAMER_LINK_B1_RX 7 + +#endif diff --git a/include/dt-bindings/jesd204/device-states.h b/include/dt-bindings/jesd204/device-states.h index aa197b20ebaa74..aec163b290ac34 100644 --- a/include/dt-bindings/jesd204/device-states.h +++ b/include/dt-bindings/jesd204/device-states.h @@ -23,7 +23,10 @@ #define JESD204_FSM_STATE_CLOCKS_ENABLE 13 #define JESD204_FSM_STATE_LINK_ENABLE 14 #define JESD204_FSM_STATE_LINK_RUNNING 15 -#define JESD204_FSM_STATE_OPT_POST_RUNNING_STAGE 16 +#define JESD204_FSM_STATE_OPT_POST_SETUP_STAGE1 16 +#define JESD204_FSM_STATE_OPT_POST_SETUP_STAGE2 17 +#define JESD204_FSM_STATE_OPT_POST_SETUP_STAGE3 18 +#define JESD204_FSM_STATE_OPT_POST_RUNNING_STAGE 19 /* Update this when adding states */ #define JESD204_FSM_STATE_LAST (JESD204_FSM_STATE_OPT_POST_RUNNING_STAGE) diff --git a/include/linux/iio/logic/axi_aion_trig.h b/include/linux/iio/logic/axi_aion_trig.h new file mode 100644 index 00000000000000..15548a5b698946 --- /dev/null +++ b/include/linux/iio/logic/axi_aion_trig.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * AXI-AION-TRIG driver interface + * + * Copyright 2026 Analog Devices Inc. + */ + +#ifndef _AXI_AION_TRIG_H_ +#define _AXI_AION_TRIG_H_ + +void axi_aion_trig_manual_trigger(void); + +#endif /* _AXI_AION_TRIG_H_ */ diff --git a/include/linux/jesd204/jesd204.h b/include/linux/jesd204/jesd204.h index 19250ff2ad3f2f..618ad01080bcd3 100644 --- a/include/linux/jesd204/jesd204.h +++ b/include/linux/jesd204/jesd204.h @@ -225,6 +225,9 @@ enum jesd204_dev_op { JESD204_OP_CLOCKS_ENABLE, JESD204_OP_LINK_ENABLE, JESD204_OP_LINK_RUNNING, + JESD204_OP_OPT_POST_SETUP_STAGE1, + JESD204_OP_OPT_POST_SETUP_STAGE2, + JESD204_OP_OPT_POST_SETUP_STAGE3, JESD204_OP_OPT_POST_RUNNING_STAGE, __JESD204_MAX_OPS, diff --git a/tools/iio/Build b/tools/iio/Build index 8d0f3af3723fc2..afbb89d22365ff 100644 --- a/tools/iio/Build +++ b/tools/iio/Build @@ -2,3 +2,5 @@ iio_utils-y += iio_utils.o lsiio-y += lsiio.o iio_utils.o iio_event_monitor-y += iio_event_monitor.o iio_utils.o iio_generic_buffer-y += iio_generic_buffer.o iio_utils.o +ad9088_cal_dump-y += ad9088_cal_dump.o + diff --git a/tools/iio/Makefile b/tools/iio/Makefile index 3bcce0b7d10f42..afe03e3405f9e3 100644 --- a/tools/iio/Makefile +++ b/tools/iio/Makefile @@ -14,7 +14,7 @@ MAKEFLAGS += -r override CFLAGS += -O2 -Wall -g -D_GNU_SOURCE -I$(OUTPUT)include -ALL_TARGETS := iio_event_monitor lsiio iio_generic_buffer +ALL_TARGETS := iio_event_monitor lsiio iio_generic_buffer ad9088_cal_dump ALL_PROGRAMS := $(patsubst %,$(OUTPUT)%,$(ALL_TARGETS)) all: $(ALL_PROGRAMS) @@ -55,6 +55,12 @@ $(IIO_GENERIC_BUFFER_IN): prepare FORCE $(OUTPUT)iio_utils-in.o $(OUTPUT)iio_generic_buffer: $(IIO_GENERIC_BUFFER_IN) $(QUIET_LINK)$(CC) $(CFLAGS) $(LDFLAGS) $< -o $@ +AD9088_CAL_DUMP_IN := $(OUTPUT)ad9088_cal_dump-in.o +$(AD9088_CAL_DUMP_IN): prepare FORCE + $(Q)$(MAKE) $(build)=ad9088_cal_dump +$(OUTPUT)ad9088_cal_dump: $(AD9088_CAL_DUMP_IN) + $(QUIET_LINK)$(CC) $(CFLAGS) $(LDFLAGS) -lz $< -o $@ + clean: rm -f $(ALL_PROGRAMS) rm -rf $(OUTPUT)include/linux/iio diff --git a/tools/iio/ad9088_cal_dump.c b/tools/iio/ad9088_cal_dump.c new file mode 100644 index 00000000000000..df07cc6c3fa779 --- /dev/null +++ b/tools/iio/ad9088_cal_dump.c @@ -0,0 +1,329 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * AD9088 Calibration Data Dump Tool + * + * Copyright 2025 Analog Devices Inc. + * + * Usage: ad9088_cal_dump + * + * This tool reads an AD9088 calibration data file and displays: + * - Header information (magic, version, chip ID, configuration) + * - Section offsets and sizes + * - CRC validation + * - Calibration data summary + */ + +#include +#include +#include +#include +#include +#include +#include /* For CRC32 calculation */ + +/* Magic number for AD9088 calibration files */ +#define AD9088_CAL_MAGIC 0x41443930 /* "AD90" */ +#define AD9088_CAL_VERSION 2 + +/* Chip IDs */ +#define CHIPID_AD9084 0x9084 +#define CHIPID_AD9088 0x9088 + +/* Number of devices */ +#define ADI_APOLLO_NUM_ADC_CAL_MODES 2 +#define ADI_APOLLO_NUM_JTX_SERDES_12PACKS 4 +#define ADI_APOLLO_NUM_SIDES 2 + +/* Calibration file header structure (must match kernel driver) */ +struct ad9088_cal_header { + uint32_t magic; /* Magic number "AD90" */ + uint32_t version; /* File format version */ + uint32_t chip_id; /* Chip ID (0x9084 or 0x9088) */ + uint8_t is_8t8r; /* 1 = 8T8R, 0 = 4T4R */ + uint8_t num_adcs; /* Number of ADCs */ + uint8_t num_serdes_rx; /* Number of SERDES RX 12-packs */ + uint8_t num_clk_cond; /* Number of clock conditioning sides */ + uint8_t reserved1[4]; /* Reserved for future use */ + + /* Section offsets from start of file */ + uint32_t adc_cal_offset; /* Offset to ADC cal data */ + uint32_t serdes_rx_cal_offset; /* Offset to SERDES RX cal data */ + uint32_t clk_cond_cal_offset; /* Offset to clock conditioning cal data */ + + /* Section sizes */ + uint32_t adc_cal_size; /* Total size of all ADC cal data */ + uint32_t serdes_rx_cal_size; /* Total size of all SERDES RX cal data */ + uint32_t clk_cond_cal_size; /* Total size of all clock conditioning cal data */ + + uint32_t total_size; /* Total file size including CRC */ + uint32_t reserved2[4]; /* Reserved for future use */ +} __attribute__((packed)); + +static const char *chip_id_to_string(uint32_t chip_id) +{ + switch (chip_id) { + case CHIPID_AD9084: + return "AD9084"; + case CHIPID_AD9088: + return "AD9088"; + default: + return "Unknown"; + } +} + +static void print_header(const struct ad9088_cal_header *hdr) +{ + printf("=== AD9088 Calibration Data Header ===\n\n"); + + printf("Magic Number: 0x%08X ('%c%c%c%c') %s\n", + hdr->magic, + (hdr->magic >> 0) & 0xFF, + (hdr->magic >> 8) & 0xFF, + (hdr->magic >> 16) & 0xFF, + (hdr->magic >> 24) & 0xFF, + hdr->magic == AD9088_CAL_MAGIC ? "[OK]" : "[INVALID]"); + + printf("Version: %u %s\n", + hdr->version, + hdr->version == AD9088_CAL_VERSION ? "[OK]" : "[UNSUPPORTED]"); + + printf("Chip ID: 0x%04X (%s)\n", + hdr->chip_id, + chip_id_to_string(hdr->chip_id)); + + printf("Configuration: %s\n", + hdr->is_8t8r ? "8T8R (8 TX, 8 RX)" : "4T4R (4 TX, 4 RX)"); + + printf("Number of ADCs: %u\n", hdr->num_adcs); + printf("Number of SERDES RX: %u\n", hdr->num_serdes_rx); + printf("Number of Clk Cond: %u\n", hdr->num_clk_cond); + + printf("\n=== Calibration Sections ===\n\n"); + + printf("ADC Calibration:\n"); + printf(" Offset: 0x%08X (%u bytes)\n", hdr->adc_cal_offset, hdr->adc_cal_offset); + printf(" Size: 0x%08X (%u bytes)\n", hdr->adc_cal_size, hdr->adc_cal_size); + if (hdr->num_adcs > 0 && hdr->adc_cal_size > 0) { + uint32_t per_mode = hdr->adc_cal_size / ADI_APOLLO_NUM_ADC_CAL_MODES; + uint32_t per_adc = per_mode / hdr->num_adcs; + printf(" Per Mode: %u bytes\n", per_mode); + printf(" Per ADC: %u bytes\n", per_adc); + } + + printf("\nSERDES RX Calibration:\n"); + printf(" Offset: 0x%08X (%u bytes)\n", hdr->serdes_rx_cal_offset, hdr->serdes_rx_cal_offset); + printf(" Size: 0x%08X (%u bytes)\n", hdr->serdes_rx_cal_size, hdr->serdes_rx_cal_size); + if (hdr->num_serdes_rx > 0 && hdr->serdes_rx_cal_size > 0) { + uint32_t per_serdes = hdr->serdes_rx_cal_size / hdr->num_serdes_rx; + printf(" Per Pack: %u bytes\n", per_serdes); + } + + printf("\nClock Conditioning Calibration:\n"); + printf(" Offset: 0x%08X (%u bytes)\n", hdr->clk_cond_cal_offset, hdr->clk_cond_cal_offset); + printf(" Size: 0x%08X (%u bytes)\n", hdr->clk_cond_cal_size, hdr->clk_cond_cal_size); + if (hdr->num_clk_cond > 0 && hdr->clk_cond_cal_size > 0) { + uint32_t per_side = hdr->clk_cond_cal_size / hdr->num_clk_cond; + printf(" Per Side: %u bytes\n", per_side); + } + + printf("\nTotal Size: 0x%08X (%u bytes)\n", + hdr->total_size, hdr->total_size); +} + +static void print_section_summary(const char *section_name, const uint8_t *data, + uint32_t offset, uint32_t size, + uint32_t num_items, const char *item_name) +{ + uint32_t i, per_item; + bool all_zero = true; + bool all_ff = true; + + if (size == 0 || num_items == 0) { + printf("\n=== %s: Empty ===\n", section_name); + return; + } + + per_item = size / num_items; + + printf("\n=== %s ===\n", section_name); + printf("Total size: %u bytes (%u items × %u bytes)\n\n", + size, num_items, per_item); + + /* Check for all zeros or all 0xFF (likely uninitialized) */ + for (i = 0; i < size && (all_zero || all_ff); i++) { + if (data[i] != 0x00) + all_zero = false; + if (data[i] != 0xFF) + all_ff = false; + } + + if (all_zero) { + printf("WARNING: All data is zero (possibly uninitialized)\n"); + } else if (all_ff) { + printf("WARNING: All data is 0xFF (possibly uninitialized)\n"); + } + + /* Print first 16 bytes of each item */ + for (i = 0; i < num_items; i++) { + uint32_t item_offset = i * per_item; + uint32_t j, bytes_to_show; + + printf("%s %u (offset 0x%08X):\n", item_name, i, + offset + item_offset); + + bytes_to_show = per_item < 16 ? per_item : 16; + printf(" "); + for (j = 0; j < bytes_to_show; j++) { + printf("%02X ", data[item_offset + j]); + if ((j + 1) % 16 == 0) + printf("\n "); + } + if (bytes_to_show < per_item) + printf("... (%u more bytes)", per_item - bytes_to_show); + printf("\n"); + } +} + +static int validate_and_dump(const char *filename) +{ + FILE *fp; + uint8_t *data; + size_t file_size, read_size; + struct ad9088_cal_header *hdr; + uint32_t crc_stored = 0, crc_calc = 0; + int ret = 0; + + /* Open file */ + fp = fopen(filename, "rb"); + if (!fp) { + fprintf(stderr, "Error: Cannot open file '%s': %s\n", + filename, strerror(errno)); + return 1; + } + + /* Get file size */ + fseek(fp, 0, SEEK_END); + file_size = ftell(fp); + fseek(fp, 0, SEEK_SET); + + printf("File: %s\n", filename); + printf("Size: %zu bytes\n\n", file_size); + + /* Check minimum size */ + if (file_size < sizeof(struct ad9088_cal_header) + 4) { + fprintf(stderr, "Error: File too small (%zu bytes)\n", file_size); + fclose(fp); + return 1; + } + + /* Read entire file */ + data = malloc(file_size); + if (!data) { + fprintf(stderr, "Error: Cannot allocate memory\n"); + fclose(fp); + return 1; + } + + read_size = fread(data, 1, file_size, fp); + fclose(fp); + + if (read_size != file_size) { + fprintf(stderr, "Error: Read only %zu of %zu bytes\n", + read_size, file_size); + free(data); + return 1; + } + + /* Parse header */ + hdr = (struct ad9088_cal_header *)data; + + /* Validate magic number */ + if (hdr->magic != AD9088_CAL_MAGIC) { + fprintf(stderr, "Error: Invalid magic number 0x%08X (expected 0x%08X)\n", + hdr->magic, AD9088_CAL_MAGIC); + ret = 1; + goto out_print_header; + } + + /* Validate version */ + if (hdr->version != AD9088_CAL_VERSION) { + fprintf(stderr, "Warning: Unsupported version %u (expected %u)\n", + hdr->version, AD9088_CAL_VERSION); + } + + /* Validate total size */ + if (hdr->total_size != file_size) { + fprintf(stderr, "Warning: Size mismatch - header says %u, file is %zu\n", + hdr->total_size, file_size); + } + + /* Extract and verify CRC */ + memcpy(&crc_stored, data + file_size - 4, 4); + crc_calc = crc32(0L, data, file_size - 4); + + printf("=== CRC Validation ===\n\n"); + printf("Stored CRC: 0x%08X\n", crc_stored); + printf("Calculated CRC: 0x%08X\n", crc_calc); + printf("Status: %s\n\n", crc_stored == crc_calc ? "[OK]" : "[FAILED]"); + + if (crc_stored != crc_calc) { + fprintf(stderr, "Error: CRC mismatch!\n"); + ret = 1; + } + +out_print_header: + /* Print header information */ + print_header(hdr); + + /* Print section summaries if CRC is valid */ + if (crc_stored == crc_calc && ret == 0) { + /* ADC calibration */ + if (hdr->adc_cal_size > 0 && hdr->adc_cal_offset < file_size) { + uint32_t num_items = hdr->num_adcs * ADI_APOLLO_NUM_ADC_CAL_MODES; + print_section_summary("ADC Calibration Data", + data + hdr->adc_cal_offset, + hdr->adc_cal_offset, + hdr->adc_cal_size, + num_items, + "ADC Chan/Mode"); + } + + /* SERDES RX calibration */ + if (hdr->serdes_rx_cal_size > 0 && hdr->serdes_rx_cal_offset < file_size) { + print_section_summary("SERDES RX Calibration Data", + data + hdr->serdes_rx_cal_offset, + hdr->serdes_rx_cal_offset, + hdr->serdes_rx_cal_size, + hdr->num_serdes_rx, + "SERDES RX Pack"); + } + + /* Clock conditioning calibration */ + if (hdr->clk_cond_cal_size > 0 && hdr->clk_cond_cal_offset < file_size) { + print_section_summary("Clock Conditioning Calibration Data", + data + hdr->clk_cond_cal_offset, + hdr->clk_cond_cal_offset, + hdr->clk_cond_cal_size, + hdr->num_clk_cond, + "Clk Cond Side"); + } + } + + printf("\n"); + free(data); + return ret; +} + +int main(int argc, char *argv[]) +{ + if (argc != 2) { + fprintf(stderr, "Usage: %s \n", argv[0]); + fprintf(stderr, "\n"); + fprintf(stderr, "Example:\n"); + fprintf(stderr, " %s /lib/firmware/ad9088_cal.bin\n", argv[0]); + fprintf(stderr, "\n"); + return 1; + } + + return validate_and_dump(argv[1]); +}