4343#define ADI_AXI_ADC_REG_CONFIG_CMOS_OR_LVDS_N BIT(7)
4444
4545#define ADI_AXI_ADC_REG_CTRL 0x0044
46+ #define ADI_AXI_ADC_REG_CTRL_CRC_EN_MASK BIT(8)
4647#define ADI_AXI_ADC_CTRL_NUM_LANES_MSK GENMASK(12, 8)
4748#define ADI_AXI_ADC_CTRL_SYNC_MSK BIT(3)
4849#define ADI_AXI_ADC_CTRL_DDR_EDGESEL_MASK BIT(1)
@@ -568,6 +569,22 @@ static int axi_adc_reg_access(struct iio_backend *back, unsigned int reg,
568569 return regmap_write (st -> regmap , reg , writeval );
569570}
570571
572+ static int axi_adc_crc_enable (struct iio_backend * back )
573+ {
574+ struct adi_axi_adc_state * st = iio_backend_get_priv (back );
575+
576+ return regmap_set_bits (st -> regmap , ADI_AXI_ADC_REG_CNTRL_3 ,
577+ ADI_AXI_ADC_REG_CTRL_CRC_EN_MASK );
578+ }
579+
580+ static int axi_adc_crc_disable (struct iio_backend * back )
581+ {
582+ struct adi_axi_adc_state * st = iio_backend_get_priv (back );
583+
584+ return regmap_clear_bits (st -> regmap , ADI_AXI_ADC_REG_CNTRL_3 ,
585+ ADI_AXI_ADC_REG_CTRL_CRC_EN_MASK );
586+ }
587+
571588static const struct regmap_config axi_adc_regmap_config = {
572589 .val_bits = 32 ,
573590 .reg_bits = 32 ,
@@ -621,6 +638,8 @@ static const struct iio_backend_ops adi_axi_adc_ops = {
621638 .num_lanes_set = axi_adc_num_lanes_set ,
622639 .debugfs_reg_access = iio_backend_debugfs_ptr (axi_adc_reg_access ),
623640 .debugfs_print_chan_status = iio_backend_debugfs_ptr (axi_adc_debugfs_print_chan_status ),
641+ .crc_enable = axi_adc_crc_enable ,
642+ .crc_disable = axi_adc_crc_disable ,
624643};
625644
626645static const struct iio_backend_info adi_axi_adc_generic = {
@@ -645,6 +664,8 @@ static const struct iio_backend_ops adi_ad485x_ops = {
645664 .debugfs_reg_access = iio_backend_debugfs_ptr (axi_adc_reg_access ),
646665 .debugfs_print_chan_status =
647666 iio_backend_debugfs_ptr (axi_adc_debugfs_print_chan_status ),
667+ .crc_enable = axi_adc_crc_enable ,
668+ .crc_disable = axi_adc_crc_disable ,
648669};
649670
650671static const struct iio_backend_info axi_ad485x = {
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