Add "no-reset" DT property to optionally avoid resetting the SEC

In cases where the SHARC cores absolutely must be booted before
ARM Linux, applications utilizing ADI's SHARC FreeRTOS image
will crash if the SEC is reset due to using the SEC for the
rescheduler interrupt. This is due to a silicon anomaly that
prevents utilizing SHARC core-level interrupts instead of the SEC.

Therefore, an optional DT property is added to the SEC driver which
allows NOT resetting the SEC in the event that an RTOS-based
application is running prior to ARM Linux booting.

- Add boolean "no-reset" property to DT bindings for ADI SEC driver
- Add condition check to NOT reset the SEC if "no-reset" is set in DT

Signed-off-by: Brandon Hurst <brandon.hurst97@gmail.com>

Author: Brandon-Hurst

Documentation/devicetree/bindings/soc/adi/adi,system-event-controller.yaml

@@ -29,6 +29,10 @@ properties:
     $ref: /schemas/types.yaml#/definitions/uint32
     description: Number of SHARC cores available
 
+  "no-reset":
+    description: "Prevents resetting the SEC to preserve interrupts"
+    type: boolean
+
 required:
   - compatible
   - reg

drivers/soc/adi/mach-sc5xx/sec.c

@@ -209,22 +209,24 @@ static int adi_sec_probe(struct platform_device *pdev)
 
 	adi_sec->ioaddr = base;
 
-	/* Disable SYSCD_RESETb and clear RCU reset status */
-	adi_rcu_writel(0x00, adi_rcu, ADI_RCU_REG_CTL);
-	adi_rcu_writel(0x0f, adi_rcu, ADI_RCU_REG_STAT);
-
-	/* Reset SEC */
-	adi_sec_writel(0x02, adi_sec, ADI_SEC_REG_GCTL);
-	adi_sec_writel(0x02, adi_sec, ADI_SEC_REG_FCTL);
-
-	/* Initialize each core */
-	for (cores = 0; cores < adi_sec->cores; ++cores) {
-		adi_sec_writel(0x02, adi_sec,
-			       ADI_SEC_REG_CCTL_BASE + (cores +
-							1) *
-			       ADI_SEC_CCTL_SIZE);
+	if ( !(of_property_read_bool(np, "no-reset")) ) {
+		/* Disable SYSCD_RESETb and clear RCU reset status */
+		adi_rcu_writel(0x00, adi_rcu, ADI_RCU_REG_CTL);
+		adi_rcu_writel(0x0f, adi_rcu, ADI_RCU_REG_STAT);
+
+		/* Reset SEC */
+		adi_sec_writel(0x02, adi_sec, ADI_SEC_REG_GCTL);
+		adi_sec_writel(0x02, adi_sec, ADI_SEC_REG_FCTL);
+
+		/* Initialize each core */
+		for (cores = 0; cores < adi_sec->cores; ++cores) {
+			adi_sec_writel(0x02, adi_sec,
+					ADI_SEC_REG_CCTL_BASE + (cores +
+								1) *
+					ADI_SEC_CCTL_SIZE);
+		}
+		udelay(100);
 	}
-	udelay(100);
 
 	/* Enable SEC fault event */
 	adi_sec_writel(0x01, adi_sec, ADI_SEC_REG_GCTL);