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| 1 | +// SPDX-License-Identifier: GPL-2.0 |
| 2 | +/dts-v1/; |
| 3 | +/plugin/; |
| 4 | + |
| 5 | +#include "dt-bindings/iio/adc/adi,ad7768.h" |
| 6 | + |
| 7 | +/ { |
| 8 | + fragment@0 { |
| 9 | + target-path = "/"; |
| 10 | + __overlay__ { |
| 11 | + vref_regulator: vref-regulator { |
| 12 | + compatible = "regulator-fixed"; |
| 13 | + regulator-name = "fixed-supply"; |
| 14 | + regulator-min-microvolt = <4096000>; |
| 15 | + regulator-max-microvolt = <4096000>; |
| 16 | + regulator-always-on; |
| 17 | + }; |
| 18 | + |
| 19 | + axi_clk: axi_clk { |
| 20 | + compatible = "fixed-clock"; |
| 21 | + clock-frequency = <100000000>; |
| 22 | + clock-output-names = "axi-clk"; |
| 23 | + #clock-cells = <0>; |
| 24 | + }; |
| 25 | + |
| 26 | + ad7768_mclk: ad7768_mclk { |
| 27 | + compatible = "fixed-clock"; |
| 28 | + clock-frequency = <32768000>; |
| 29 | + clock-output-names = "ad7768-mclk"; |
| 30 | + #clock-cells = <0>; |
| 31 | + }; |
| 32 | + }; |
| 33 | + }; |
| 34 | + |
| 35 | + fragment@1 { |
| 36 | + target-path = "/fpga-axi"; |
| 37 | + __overlay__ { |
| 38 | + #address-cells = <1>; |
| 39 | + #size-cells = <1>; |
| 40 | + rx_dma: dmac@7c480000 { |
| 41 | + compatible = "adi,axi-dmac-1.00.a"; |
| 42 | + reg = <0x7c480000 0x1000>; |
| 43 | + #dma-cells = <1>; |
| 44 | + interrupt-parent = <&intc>; |
| 45 | + interrupts = <0 54 4>; |
| 46 | + clocks = <&clkc 16>; |
| 47 | + |
| 48 | + adi,channels { |
| 49 | + #size-cells = <0>; |
| 50 | + #address-cells = <1>; |
| 51 | + |
| 52 | + dma_channel: dma-channel@0 { |
| 53 | + reg = <0>; |
| 54 | + adi,source-bus-width = <128>; |
| 55 | + adi,source-bus-type = <2>; |
| 56 | + adi,destination-bus-width = <64>; |
| 57 | + adi,destination-bus-type = <0>; |
| 58 | + }; |
| 59 | + }; |
| 60 | + }; |
| 61 | + |
| 62 | + iio_backend: axi_adc@43c00000 { |
| 63 | + compatible = "adi,axi-adc-10.0.a"; |
| 64 | + reg = <0x43c00000 0x10000>; |
| 65 | + dmas = <&rx_dma 0>; |
| 66 | + dma-names = "rx"; |
| 67 | + clocks = <&axi_clk>; |
| 68 | + spibus-connected = <&ad7768>; |
| 69 | + }; |
| 70 | + }; |
| 71 | + }; |
| 72 | + |
| 73 | + fragment@2 { |
| 74 | + target = <&spi0>; |
| 75 | + __overlay__ { |
| 76 | + status = "okay"; |
| 77 | + #address-cells = <1>; |
| 78 | + #size-cells = <0>; |
| 79 | + ad7768: adc@0 { |
| 80 | + compatible = "adi,ad7768-4"; |
| 81 | + reg = <0>; |
| 82 | + spi-max-frequency = <1000000>; |
| 83 | + |
| 84 | + vref-supply = <&vref_regulator>; |
| 85 | + reset-gpios = <&gpio0 86 1>; |
| 86 | + clocks = <&ad7768_mclk>; |
| 87 | + clock-names = "mclk"; |
| 88 | + adi,data-lines-number = <4>; |
| 89 | + adi,common-mode-output-v = <AD7768_1P5_V>; |
| 90 | + adi,vcm-power-down; |
| 91 | + adi,power-mode = <AD7768_POWER_MODE_FAST>; |
| 92 | + |
| 93 | + io-backends = <&iio_backend>; |
| 94 | + |
| 95 | + #address-cells = <1>; |
| 96 | + #size-cells = <0>; |
| 97 | + |
| 98 | + channel@0 { |
| 99 | + reg = <0>; |
| 100 | + adi,ch-mode = <0>; |
| 101 | + adi,prebuf-pos-en; |
| 102 | + adi,refbuf-pos-en; |
| 103 | + }; |
| 104 | + |
| 105 | + channel@1 { |
| 106 | + reg = <1>; |
| 107 | + adi,ch-mode = <0>; |
| 108 | + adi,prebuf-pos-en; |
| 109 | + adi,prebuf-neg-en; |
| 110 | + adi,refbuf-pos-en; |
| 111 | + adi,refbuf-neg-en; |
| 112 | + }; |
| 113 | + |
| 114 | + channel@2 { |
| 115 | + reg = <2>; |
| 116 | + adi,ch-mode = <1>; |
| 117 | + adi,prebuf-neg-en; |
| 118 | + adi,refbuf-neg-en; |
| 119 | + }; |
| 120 | + |
| 121 | + channel@3 { |
| 122 | + reg = <3>; |
| 123 | + adi,ch-mode = <1>; |
| 124 | + adi,prebuf-pos-en; |
| 125 | + adi,refbuf-pos-en; |
| 126 | + }; |
| 127 | + }; |
| 128 | + }; |
| 129 | + }; |
| 130 | +}; |
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