diff --git a/docs/projects/adrv9009zu11eg/adrv9009_zu11eg_hdl_corundum.svg b/docs/projects/adrv9009zu11eg/adrv9009_zu11eg_hdl_corundum.svg new file mode 100644 index 00000000000..535977ac9bf --- /dev/null +++ b/docs/projects/adrv9009zu11eg/adrv9009_zu11eg_hdl_corundum.svg @@ -0,0 +1,1793 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + + + + + + + + + + Processing System + Programmable Logic + PS Memory Controller + + + JESD204B + + + + + + + 2xPL_DDR4 + + RX/TXDMAs + + + 4xRX + + 2xADRV9009 Data Path + User Logic + + + + PCIe bridge + 10GbE + QSFP+ + + 8xTX + + + + + + + USB 3.0 + + + MIG + + PS_DDR4 + + QSFP+ + + 40GbE  + + + QSPI + + + + GPIO + + + 4xOBS_RX + + + DATA OFFLOAD + + OBS_RXDMA + + CORUNDUMN.I.C. + + + + + 32 bit + + 64 bit + + PCIe + + X8 + + X1 + + X4 + + + + 2xI2C + + + + + UART + + + + 2x1GbE + + + + SDIO  + + + + 2xSPI + + + + Optional modules + + PS Ultrascale+ + + + DisplayPort + + + I2S  + + FanControl  + + diff --git a/docs/projects/adrv9009zu11eg/adrv9009_zu11eg_jesd204b.svg b/docs/projects/adrv9009zu11eg/adrv9009_zu11eg_jesd204b.svg index 29e91c3eb85..c934a642d40 100644 --- a/docs/projects/adrv9009zu11eg/adrv9009_zu11eg_jesd204b.svg +++ b/docs/projects/adrv9009zu11eg/adrv9009_zu11eg_jesd204b.svg @@ -7,356 +7,285 @@ viewBox="0 0 800 945" id="svg2" version="1.1" - inkscape:version="1.3.2 (091e20e, 2023-11-25, custom)" + inkscape:version="1.4.2 (f4327f4, 2025-05-13)" sodipodi:docname="adrv9009_zu11eg_jesd204b.svg" style="shape-rendering:crispEdges;enable-background:new" + xml:space="preserve" xmlns:inkscape="http://www.inkscape.org/namespaces/inkscape" xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd" xmlns="http://www.w3.org/2000/svg" xmlns:svg="http://www.w3.org/2000/svg" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:cc="http://creativecommons.org/ns#" - xmlns:dc="http://purl.org/dc/elements/1.1/"> - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - image/svg+xml - - - - - image/svg+xml - - MEMORY INTERCONNECT - - MEMORY INTERCONNECT - - - - - - - - - - - - - - - - - -  ADRV2CRR_FMC - ADRV2CRR_FMC - FMC CONNECTOR - FMC CONNECTOR - - Shared GT*/XCVR - - Shared GT*/XCVR  -   - - RX JESD LINK - - RX JESD LINK - EyeScan - - - EyeScan  -    -   - - RX JESD IP - - RX JESD IP - - - - - - - - - - - -   -   - - - -  ADRV9009ZU11EG - ADRV9009ZU11EG - - - - - TX JESD IP - TX JESD IP - - - - - - - - - TX JESD LINK - TX JESD LINK - - - - DAC core frame - - DAC core frame - - - - - - - - IQ Correction - - - - Correction - - - - PATTERN - PATTERNDDS - DDSDMA - DMA - - - - - DAC CHANNEL - - DAC CHANNELDAC CORE - DAC CORE - - - - - - - DAC core frame - - DAC core frame - ADRV9009 INTERFACE - - ADRV9009 INTERFACE - - - - - - ADC CHANNEL - ADC CHANNELADC CORE - ADC CORE - - - - - - - - - - - - - - - - - IQ Corr - - - Corr - - - - - - Filter - Filter - - - - - - - - - - - - - - - - - - - - - - ADC PACK - - ADC PACK - - ADC DMA - - ADC DMA - DAC DMA - DAC DMA - - - - DAC UNPACK - DAC UNPACKCORUNDUMNetwork Interface Card(only if build with CORUNDUM=1) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Receive path - Receive path - Transmit path - Transmit path - - RX OS JESD LINK - - RX OS JESD LINK - EyeScan - - - EyeScan - - RX OS JESD IP - - RX OS JESD IP - - - - - - - - - - - - - DAC core frame - - DAC core frame - - ADC CHANNEL - ADC CHANNELADC OS CORE - ADC OS CORE - - - - - - - - - - - - - - - - - IQ Corr - - - Corr - - - - Filter - Filter - - - - - - - - - - - - - - - - ADC OS PACK - - ADC OS PACK - ADC OS DMA - ADC OS DMA - Observation path - Observation path - ADRV9009 IP - - ADRV9009 IP - - - - - - - - - - - - - - Ethernet - EthernetUART - UARTQSFP+ cage (10G) DDRx - DDRxSPI - SPII2C - 2CInterrupts - Interrupts  -  Zynq MPSoC - Zynq MPSoCTimer - - Timer - - - - + style="fill:none;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:2;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /> diff --git a/docs/projects/adrv9009zu11eg/index.rst b/docs/projects/adrv9009zu11eg/index.rst index e5ab6602dea..9184f34c7c6 100644 --- a/docs/projects/adrv9009zu11eg/index.rst +++ b/docs/projects/adrv9009zu11eg/index.rst @@ -49,6 +49,17 @@ Block design :align: center :alt: ADRV9009ZU11EG block diagram +Block design - Corundum Network Interface Card integrated +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +This is available only if the project was build using the command +``make CORUNDUM=1``. + +.. image:: adrv9009_zu11eg_hdl_corundum.svg + :width: 800 + :align: center + :alt: ADRV9009ZU11EG block diagram Corundum N.I.C + Block diagram ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -168,9 +179,19 @@ axi_adrv9009_obs_jesd 0x84A7_0000 axi_adrv9009_rx_dma 0x9C42_0000 axi_adrv9009_tx_dma 0x9C40_0000 axi_adrv9009_obs_dma 0x9C44_0000 -axi_sysid_0 0x8500_0000 +axi_sysid_0 0x8500_0000 ===================== =========== +In case of :adi:`ADRV2CRR-FMC`, additional interconnects may be present in +the system. + +=========== =========== +Instance Address +=========== =========== +s_axil_ctrl 0xA000_0000 +axi_iic 0x4300_0000 +=========== =========== + SPI connections ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -331,6 +352,15 @@ axi_adrv9009_fmc_tx_jesd 12 108 140 axi_adrv9009_fmc_rx_jesd 13 109 141 ========================== === ============ ============= +In case of :adi:`ADRV2CRR-FMC`, additional interrupts may be present in the system. + +======================= === ============ ============= +Instance name HDL Linux ZynqMP Actual ZynqMP +======================= === ============ ============= +corundum_hierarcy/irq 4 93 125 +axi_iic 14 110 142 +======================= === ============ ============= + Building the HDL project ------------------------------------------------------------------------------- @@ -385,8 +415,44 @@ configure this project, depending on the carrier used. | RX_OS_JESD_S | 1 | 1 | +-------------------+----------------------------------+-------------------+ +Build the project with Corundum Network Stack support for ADRV9009-ZU11EG/ADRV2CRR-FMC +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +For this configuration of the project only, the Corundum Network Stack can be +added. This configuration supports **10 Gbps** on the **QSFP+** connector. + +`Corundum NIC `_ repository needs to +be cloned alongside HDL repository. Do a git checkout to the latest tested +version (commit - 37f2607). When the 10G-based implementation (e.g., in +this project) is used, apply the indicated patch. Then navigate back to the +location of the project, and build the project using the environmental variable +**CORUNDUM**, by setting it to 1 (default it's 0). + +**Linux/Cygwin/WSL** + +.. shell:: + + $git clone https://github.com/ucsdsysnet/corundum.git + $cd corundum + $git checkout 37f2607 + $git apply ../hdl/library/corundum/patch_axis_xgmii_rx_64.patch + $cd ../hdl/projects/adrv9009_zu11eg/adrv2crr_fmc + $make CORUNDUM=1 + A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. +.. admonition:: Publications + + The following papers pertain to the Corundum source code: + + - J- A. Forencich, A. C. Snoeren, G. Porter, G. Papen, Corundum: An Open-Source 100-Gbps NIC, in FCCM'20. + (`FCCM Paper`_, `FCCM Presentation`_) + - J- A. Forencich, System-Level Considerations for Optical Switching in Data Center Networks. (`Thesis`_) + +.. _FCCM Paper: https://www.cse.ucsd.edu/~snoeren/papers/corundum-fccm20.pdf +.. _FCCM Presentation: https://www.fccm.org/past/2020/forums/topic/corundum-an-open-source-100-gbps-nic/ +.. _Thesis: https://escholarship.org/uc/item/3mc9070t + Other considerations ------------------------------------------------------------------------------- @@ -514,6 +580,12 @@ HDL related * - JESD204_TPL_DAC - :git-hdl:`library/jesd204/ad_ip_jesd204_tpl_dac` - :ref:`ad_ip_jesd204_tpl_dac` + * - CORUNDUM_CORE + - :git-hdl:`library/corundum/corundum_core` + - :ref:`corundum_core` + * - ETHERNET_CORE + - :git-hdl:`library/corundum/ethernet` + - :ref:`corundum_ethernet_core` - :dokuwiki:`[Wiki] Generic JESD204B block designs ` - :ref:`jesd204` @@ -526,6 +598,7 @@ Software related - :git-linux:`ADRV9009ZU11EG device tree ` - :git-linux:`ADRV9009ZU11EG + FMCOMMS8 device tree ` - :git-linux:`ADRV9009ZU11EG + FMCXMWBR1 device tree ` +- :git-linux:`ADRV9009ZU11EG + ADRV2CRR-FMC CORUNDUM device tree ` - :git-no-os:`ADRV9009ZU11EG NO-OS PROJECT ` .. include:: ../common/more_information.rst diff --git a/library/corundum/ethernet/adrv9009zu11eg/Makefile b/library/corundum/ethernet/adrv9009zu11eg/Makefile new file mode 100644 index 00000000000..23bbf96936e --- /dev/null +++ b/library/corundum/ethernet/adrv9009zu11eg/Makefile @@ -0,0 +1,55 @@ +LIBRARY_NAME := ethernet_adrv9009zu11eg + +GENERIC_DEPS += ethernet_adrv9009zu11eg.v + +XILINX_DEPS += ethernet_adrv9009zu11eg_ip.tcl + +EXTERNAL_DEPS += ../../../../../corundum/fpga/mqnic/KR260/fpga/rtl/sync_signal.v +EXTERNAL_DEPS += ../../../../../corundum/fpga/common/rtl/eth_xcvr_phy_10g_gty_quad_wrapper.v +EXTERNAL_DEPS += ../../../../../corundum/fpga/common/rtl/eth_xcvr_phy_10g_gty_wrapper.v +EXTERNAL_DEPS += ../../../../../corundum/fpga/lib/eth/rtl/eth_phy_10g.v +EXTERNAL_DEPS += ../../../../../corundum/fpga/lib/eth/rtl/eth_phy_10g_tx_if.v +EXTERNAL_DEPS += ../../../../../corundum/fpga/lib/eth/rtl/eth_phy_10g_tx.v +EXTERNAL_DEPS += ../../../../../corundum/fpga/lib/eth/rtl/eth_phy_10g_rx.v +EXTERNAL_DEPS += ../../../../../corundum/fpga/lib/eth/rtl/eth_phy_10g_rx_frame_sync.v +EXTERNAL_DEPS += ../../../../../corundum/fpga/lib/eth/rtl/eth_phy_10g_rx_if.v +EXTERNAL_DEPS += ../../../../../corundum/fpga/lib/eth/rtl/eth_phy_10g_rx_ber_mon.v +EXTERNAL_DEPS += ../../../../../corundum/fpga/lib/eth/rtl/eth_phy_10g_rx_watchdog.v +EXTERNAL_DEPS += ../../../../../corundum/fpga/lib/eth/rtl/xgmii_baser_dec_64.v +EXTERNAL_DEPS += ../../../../../corundum/fpga/lib/eth/rtl/xgmii_baser_enc_64.v +EXTERNAL_DEPS += ../../../../../corundum/fpga/lib/eth/rtl/axis_xgmii_rx_32.v +EXTERNAL_DEPS += ../../../../../corundum/fpga/lib/eth/rtl/axis_xgmii_tx_32.v +EXTERNAL_DEPS += ../../../../../corundum/fpga/common/rtl/mqnic_port_map_phy_xgmii.v +EXTERNAL_DEPS += ../../../../../corundum/fpga/lib/eth/lib/axis/rtl/sync_reset.v +EXTERNAL_DEPS += ../../../../../corundum/fpga/common/rtl/rb_drp.v +EXTERNAL_DEPS += ../../../../../corundum/fpga/lib/eth/rtl/eth_mac_10g.v +EXTERNAL_DEPS += ../../../../../corundum/fpga/lib/eth/rtl/axis_xgmii_rx_64.v +EXTERNAL_DEPS += ../../../../../corundum/fpga/lib/eth/rtl/axis_xgmii_tx_64.v +EXTERNAL_DEPS += ../../../../../corundum/fpga/lib/eth/rtl/lfsr.v +EXTERNAL_DEPS += ../../../../../corundum/fpga/lib/eth/rtl/mac_ctrl_rx.v +EXTERNAL_DEPS += ../../../../../corundum/fpga/lib/eth/rtl/mac_ctrl_tx.v +EXTERNAL_DEPS += ../../../../../corundum/fpga/lib/eth/rtl/mac_pause_ctrl_rx.v +EXTERNAL_DEPS += ../../../../../corundum/fpga/lib/eth/rtl/mac_pause_ctrl_tx.v + +EXTERNAL_DEPS += ../../../../../corundum/fpga/mqnic/ZCU102/fpga/ip/eth_xcvr_gth.tcl + +XILINX_DEPS += ../../interfaces/if_ctrl_reg.xml +XILINX_DEPS += ../../interfaces/if_ctrl_reg_rtl.xml +XILINX_DEPS += ../../interfaces/if_ptp.xml +XILINX_DEPS += ../../interfaces/if_ptp_rtl.xml +XILINX_DEPS += ../../interfaces/if_flow_control_tx.xml +XILINX_DEPS += ../../interfaces/if_flow_control_tx_rtl.xml +XILINX_DEPS += ../../interfaces/if_flow_control_rx.xml +XILINX_DEPS += ../../interfaces/if_flow_control_rx_rtl.xml +XILINX_DEPS += ../../interfaces/if_ethernet_ptp.xml +XILINX_DEPS += ../../interfaces/if_ethernet_ptp_rtl.xml +XILINX_DEPS += ../../interfaces/if_axis_tx_ptp.xml +XILINX_DEPS += ../../interfaces/if_axis_tx_ptp_rtl.xml +XILINX_DEPS += ../../interfaces/if_qsfp.xml +XILINX_DEPS += ../../interfaces/if_qsfp_rtl.xml +XILINX_DEPS += ../../interfaces/if_i2c.xml +XILINX_DEPS += ../../interfaces/if_i2c_rtl.xml + +XILINX_INTERFACE_DEPS += corundum/interfaces + +include ../../../scripts/library.mk diff --git a/library/corundum/ethernet/adrv9009zu11eg/ethernet_adrv9009zu11eg.v b/library/corundum/ethernet/adrv9009zu11eg/ethernet_adrv9009zu11eg.v new file mode 100644 index 00000000000..0d8a0dacdef --- /dev/null +++ b/library/corundum/ethernet/adrv9009zu11eg/ethernet_adrv9009zu11eg.v @@ -0,0 +1,876 @@ +// SPDX-License-Identifier: BSD-2-Clause-Views +/* + * Copyright (c) 2023 The Regents of the University of California + * Copyright (c) 2025 Analog Devices, Inc. All rights reserved + */ + +`timescale 1ns/100ps + +module ethernet_adrv9009zu11eg #( + + // Structural configuration + parameter IF_COUNT = 1, + parameter PORTS_PER_IF = 1, + parameter SCHED_PER_IF = PORTS_PER_IF, + parameter PORT_MASK = 0, + parameter PORT_COUNT = IF_COUNT*PORTS_PER_IF, + + parameter TDMA_BER_ENABLE = 0, + + parameter PTP_PEROUT_COUNT = 1, + + // Interface configuration + parameter PTP_TS_ENABLE = 1, + parameter PTP_TS_FMT_TOD = 1, + parameter PTP_TS_WIDTH = PTP_TS_FMT_TOD ? 96 : 64, + parameter TX_TAG_WIDTH = 16, + parameter PFC_ENABLE = 1, + parameter LFC_ENABLE = PFC_ENABLE, + parameter ENABLE_PADDING = 1, + parameter ENABLE_DIC = 1, + parameter MIN_FRAME_LENGTH = 64, + + parameter XGMII_DATA_WIDTH = 64, + parameter XGMII_CTRL_WIDTH = XGMII_DATA_WIDTH/8, + parameter AXIS_DATA_WIDTH = XGMII_DATA_WIDTH, + parameter AXIS_KEEP_WIDTH = AXIS_DATA_WIDTH/8, + parameter AXIS_TX_USER_WIDTH = TX_TAG_WIDTH + 1, + parameter AXIS_RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1, + + // AXI lite interface configuration (control) + parameter AXIL_CTRL_DATA_WIDTH = 32, + parameter AXIL_CTRL_ADDR_WIDTH = 24, + parameter AXIL_CTRL_STRB_WIDTH = (AXIL_CTRL_DATA_WIDTH/8), + parameter AXIL_IF_CTRL_ADDR_WIDTH = AXIL_CTRL_ADDR_WIDTH-$clog2(IF_COUNT), + parameter AXIL_CSR_ENABLE = 0, + parameter AXIL_CSR_ADDR_WIDTH = AXIL_IF_CTRL_ADDR_WIDTH-5-$clog2((SCHED_PER_IF+4+7)/8), + + // Statistics counter subsystem + parameter STAT_ENABLE = 0, + parameter STAT_DMA_ENABLE = 0, + parameter STAT_AXI_ENABLE = 0, + parameter STAT_INC_WIDTH = 24, + parameter STAT_ID_WIDTH = 12 +) ( + /* + * Clock and reset + */ + input wire clk, + input wire rst, + + /* + * GPIO + */ + output wire [3:0] qsfp_led, + + /* + * Ethernet: SFP+ + */ + input wire qsfp_mgt_refclk_p, + input wire qsfp_mgt_refclk_n, + output wire [3:0] qsfp_tx_p, + output wire [3:0] qsfp_tx_n, + input wire [3:0] qsfp_rx_p, + input wire [3:0] qsfp_rx_n, + + output wire qsfp_modsell, + output wire qsfp_resetl, + input wire qsfp_modprsl, + input wire qsfp_intl, + output wire qsfp_lpmode, + output wire qsfp_gtpowergood, + + output wire qsfp_rst, + + input wire [AXIL_CSR_ADDR_WIDTH-1:0] ctrl_reg_wr_addr, + input wire [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_wr_data, + input wire [AXIL_CTRL_STRB_WIDTH-1:0] ctrl_reg_wr_strb, + input wire ctrl_reg_wr_en, + output wire ctrl_reg_wr_wait, + output wire ctrl_reg_wr_ack, + input wire [AXIL_CSR_ADDR_WIDTH-1:0] ctrl_reg_rd_addr, + input wire ctrl_reg_rd_en, + output wire [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_rd_data, + output wire ctrl_reg_rd_wait, + output wire ctrl_reg_rd_ack, + + input wire [AXIL_CSR_ADDR_WIDTH-1:0] s_axil_csr_awaddr, + input wire [2:0] s_axil_csr_awprot, + input wire s_axil_csr_awvalid, + output wire s_axil_csr_awready, + input wire [AXIL_CTRL_DATA_WIDTH-1:0] s_axil_csr_wdata, + input wire [AXIL_CTRL_STRB_WIDTH-1:0] s_axil_csr_wstrb, + input wire s_axil_csr_wvalid, + output wire s_axil_csr_wready, + output wire [1:0] s_axil_csr_bresp, + output wire s_axil_csr_bvalid, + input wire s_axil_csr_bready, + input wire [AXIL_CSR_ADDR_WIDTH-1:0] s_axil_csr_araddr, + input wire [2:0] s_axil_csr_arprot, + input wire s_axil_csr_arvalid, + output wire s_axil_csr_arready, + output wire [AXIL_CTRL_DATA_WIDTH-1:0] s_axil_csr_rdata, + output wire [1:0] s_axil_csr_rresp, + output wire s_axil_csr_rvalid, + input wire s_axil_csr_rready, + + /* + * PTP setup + */ + output wire ptp_clk, + output wire ptp_rst, + output wire ptp_sample_clk, + input wire ptp_td_sd, + input wire ptp_pps, + input wire ptp_pps_str, + input wire ptp_sync_locked, + input wire [63:0] ptp_sync_ts_rel, + input wire ptp_sync_ts_rel_step, + input wire [96:0] ptp_sync_ts_tod, + input wire ptp_sync_ts_tod_step, + input wire ptp_sync_pps, + input wire ptp_sync_pps_str, + input wire [PTP_PEROUT_COUNT-1:0] ptp_perout_locked, + input wire [PTP_PEROUT_COUNT-1:0] ptp_perout_error, + input wire [PTP_PEROUT_COUNT-1:0] ptp_perout_pulse, + + output wire [PORT_COUNT-1:0] eth_tx_clk, + output wire [PORT_COUNT-1:0] eth_tx_rst, + + output wire [PORT_COUNT-1:0] eth_tx_ptp_clk, + output wire [PORT_COUNT-1:0] eth_tx_ptp_rst, + input wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_tx_ptp_ts, + input wire [PORT_COUNT-1:0] eth_tx_ptp_ts_step, + + output wire [PORT_COUNT-1:0] eth_rx_clk, + output wire [PORT_COUNT-1:0] eth_rx_rst, + + output wire [PORT_COUNT-1:0] eth_rx_ptp_clk, + output wire [PORT_COUNT-1:0] eth_rx_ptp_rst, + input wire [PORT_COUNT*PTP_TS_WIDTH-1:0] eth_rx_ptp_ts, + input wire [PORT_COUNT-1:0] eth_rx_ptp_ts_step, + + input wire [PORT_COUNT*AXIS_DATA_WIDTH-1:0] axis_eth_tx_tdata, + input wire [PORT_COUNT*AXIS_KEEP_WIDTH-1:0] axis_eth_tx_tkeep, + input wire [PORT_COUNT-1:0] axis_eth_tx_tvalid, + output wire [PORT_COUNT-1:0] axis_eth_tx_tready, + input wire [PORT_COUNT-1:0] axis_eth_tx_tlast, + input wire [PORT_COUNT*AXIS_TX_USER_WIDTH-1:0] axis_eth_tx_tuser, + + output wire [PORT_COUNT*PTP_TS_WIDTH-1:0] axis_eth_tx_ptp_ts, + output wire [PORT_COUNT*TX_TAG_WIDTH-1:0] axis_eth_tx_ptp_ts_tag, + output wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_valid, + input wire [PORT_COUNT-1:0] axis_eth_tx_ptp_ts_ready, + + input wire [PORT_COUNT-1:0] eth_tx_enable, + output wire [PORT_COUNT-1:0] eth_tx_status, + input wire [PORT_COUNT-1:0] eth_tx_lfc_en, + input wire [PORT_COUNT-1:0] eth_tx_lfc_req, + input wire [PORT_COUNT*8-1:0] eth_tx_pfc_en, + input wire [PORT_COUNT*8-1:0] eth_tx_pfc_req, + output wire [PORT_COUNT*8-1:0] eth_tx_fc_quanta_clk_en, + + output wire [PORT_COUNT*AXIS_DATA_WIDTH-1:0] axis_eth_rx_tdata, + output wire [PORT_COUNT*AXIS_KEEP_WIDTH-1:0] axis_eth_rx_tkeep, + output wire [PORT_COUNT-1:0] axis_eth_rx_tvalid, + input wire [PORT_COUNT-1:0] axis_eth_rx_tready, + output wire [PORT_COUNT-1:0] axis_eth_rx_tlast, + output wire [PORT_COUNT*AXIS_RX_USER_WIDTH-1:0] axis_eth_rx_tuser, + + input wire [PORT_COUNT-1:0] eth_rx_enable, + output wire [PORT_COUNT-1:0] eth_rx_status, + input wire [PORT_COUNT-1:0] eth_rx_lfc_en, + output wire [PORT_COUNT-1:0] eth_rx_lfc_req, + input wire [PORT_COUNT-1:0] eth_rx_lfc_ack, + input wire [PORT_COUNT*8-1:0] eth_rx_pfc_en, + output wire [PORT_COUNT*8-1:0] eth_rx_pfc_req, + input wire [PORT_COUNT*8-1:0] eth_rx_pfc_ack, + output wire [PORT_COUNT-1:0] eth_rx_fc_quanta_clk_en, + + /* + * I2C + */ + input wire i2c_scl_i, + output reg i2c_scl_o, + output reg i2c_scl_t, + input wire i2c_sda_i, + output reg i2c_sda_o, + output reg i2c_sda_t +); + + wire qsfp_iic_scl_i_w; + wire qsfp_iic_scl_o_w; + wire qsfp_iic_scl_t_w; + wire qsfp_iic_sda_i_w; + wire qsfp_iic_sda_o_w; + wire qsfp_iic_sda_t_w; + + wire qsfp_drp_clk; + wire qsfp_drp_rst; + wire [23:0] qsfp_drp_addr; + wire [15:0] qsfp_drp_di; + wire qsfp_drp_en; + wire qsfp_drp_we; + wire [15:0] qsfp_drp_do; + wire qsfp_drp_rdy; + + localparam RB_BASE_ADDR = 16'h1000; + localparam RBB = RB_BASE_ADDR & {AXIL_CTRL_ADDR_WIDTH{1'b1}}; + + localparam RB_DRP_QSFP_BASE = RB_BASE_ADDR + 16'h20; + + reg qsfp_iic_scl_o_reg = 1'b1; + reg qsfp_iic_sda_o_reg = 1'b1; + + always @(posedge clk) begin + i2c_scl_o <= qsfp_iic_scl_o_w; + i2c_scl_t <= qsfp_iic_scl_t_w; + i2c_sda_o <= qsfp_iic_sda_o_w; + i2c_sda_t <= qsfp_iic_sda_t_w; + end + + assign qsfp_iic_scl_o_w = qsfp_iic_scl_o_reg; + assign qsfp_iic_scl_t_w = qsfp_iic_scl_o_reg; + assign qsfp_iic_sda_o_w = qsfp_iic_sda_o_reg; + assign qsfp_iic_sda_t_w = qsfp_iic_sda_o_reg; + + wire clk_156mhz_int; + + wire clk_125mhz_mmcm_out; + + // Internal 125 MHz clock + wire clk_125mhz_int; + wire rst_125mhz_int; + + wire mmcm_rst = rst; + wire mmcm_locked; + wire mmcm_clkfb; + + assign qsfp_drp_clk = clk_125mhz_int; + assign qsfp_drp_rst = rst_125mhz_int; + + wire qsfp_rx_block_lock; + wire qsfp_gtpowergood; + + wire qsfp_mgt_refclk; + wire qsfp_mgt_refclk_int; + wire qsfp_mgt_refclk_bufg; + + wire qsfp_tx_clk_int; + wire qsfp_tx_rst_int; + wire [63:0] qsfp_txd_int; + wire [7:0] qsfp_txc_int; + wire qsfp_tx_prbs31_enable_int; + wire qsfp_rx_clk_int; + wire qsfp_rx_rst_int; + wire [63:0] qsfp_rxd_int; + wire [7:0] qsfp_rxc_int; + wire qsfp_rx_prbs31_enable_int; + wire [6:0] qsfp_rx_error_count_int; + + wire qsfp_rx_status; + + wire qsfp_tx_fault_int; + wire qsfp_rx_los_int; + wire qsfp_mod_abs_int; + + sync_signal #( + .WIDTH(5), + .N(2) + ) sync_signal_inst ( + .clk(clk), + .in({qsfp_tx_fault, qsfp_rx_los, qsfp_mod_abs, scl_i, sda_i}), + .out({qsfp_tx_fault_int, qsfp_rx_los_int, qsfp_mod_abs_int, qsfp_iic_scl_i_w, qsfp_iic_sda_i_w})); + + sync_signal #( + .WIDTH(2), + .N(2) + ) sync_signal_inst_qsfp ( + .clk(clk), + .in({qsfp_modprsl, qsfp_intl}), + .out({qsfp_modprsl_int, qsfp_intl_int}) + ); + + // MMCM instance + // 156.25 MHz in, 125 MHz out + // PFD range: 10 MHz to 500 MHz + // VCO range: 800 MHz to 1600 MHz + // M = 8, D = 1 sets Fvco = 1250 MHz + // Divide by 10 to get output frequency of 125 MHz + MMCME4_BASE #( + .BANDWIDTH("OPTIMIZED"), + .CLKOUT0_DIVIDE_F(10), + .CLKOUT0_DUTY_CYCLE(0.5), + .CLKOUT0_PHASE(0), + .CLKOUT1_DIVIDE(1), + .CLKOUT1_DUTY_CYCLE(0.5), + .CLKOUT1_PHASE(0), + .CLKOUT2_DIVIDE(1), + .CLKOUT2_DUTY_CYCLE(0.5), + .CLKOUT2_PHASE(0), + .CLKOUT3_DIVIDE(1), + .CLKOUT3_DUTY_CYCLE(0.5), + .CLKOUT3_PHASE(0), + .CLKOUT4_DIVIDE(1), + .CLKOUT4_DUTY_CYCLE(0.5), + .CLKOUT4_PHASE(0), + .CLKOUT5_DIVIDE(1), + .CLKOUT5_DUTY_CYCLE(0.5), + .CLKOUT5_PHASE(0), + .CLKOUT6_DIVIDE(1), + .CLKOUT6_DUTY_CYCLE(0.5), + .CLKOUT6_PHASE(0), + .CLKFBOUT_MULT_F(8), + .CLKFBOUT_PHASE(0), + .DIVCLK_DIVIDE(1), + .REF_JITTER1(0.010), + .CLKIN1_PERIOD(6.4), + .STARTUP_WAIT("FALSE"), + .CLKOUT4_CASCADE("FALSE") + ) clk_mmcm_inst ( + .CLKIN1(clk_156mhz_int), + .CLKFBIN(mmcm_clkfb), + .RST(mmcm_rst), + .PWRDWN(1'b0), + .CLKOUT0(clk_125mhz_mmcm_out), + .CLKOUT0B(), + .CLKOUT1(), + .CLKOUT1B(), + .CLKOUT2(), + .CLKOUT2B(), + .CLKOUT3(), + .CLKOUT3B(), + .CLKOUT4(), + .CLKOUT5(), + .CLKOUT6(), + .CLKFBOUT(mmcm_clkfb), + .CLKFBOUTB(), + .LOCKED(mmcm_locked)); + + BUFG #( + ) clk_125mhz_bufg_inst ( + .I(clk_125mhz_mmcm_out), + .O(clk_125mhz_int)); + + sync_reset #( + .N(4) + ) sync_reset_125mhz_inst ( + .clk(clk_125mhz_int), + .rst(~mmcm_locked), + .out(rst_125mhz_int)); + + IBUFDS_GTE4 #( + ) ibufds_gte4_qsfp_mgt_refclk_inst ( + .I (qsfp_mgt_refclk_p), + .IB (qsfp_mgt_refclk_n), + .CEB (1'b0), + .O (qsfp_mgt_refclk), + .ODIV2 (qsfp_mgt_refclk_int)); + + BUFG_GT #( + ) bufg_gt_qsfp_mgt_refclk_inst ( + .CE (qsfp_gtpowergood), + .CEMASK (1'b1), + .CLR (1'b0), + .CLRMASK (1'b1), + .DIV (3'd0), + .I (qsfp_mgt_refclk_int), + .O (qsfp_mgt_refclk_bufg)); + + sync_reset #( + .N(4) + ) qsfp_sync_reset_inst ( + .clk(qsfp_mgt_refclk_bufg), + .rst(rst_125mhz_int), + .out(qsfp_rst)); + + // TODO move out of the IP + eth_xcvr_phy_10g_gty_quad_wrapper #( + .PRBS31_ENABLE(1), + .GT_GTH(1), + .TX_SERDES_PIPELINE(1), + .RX_SERDES_PIPELINE(1), + .COUNT_125US(125000/2.56) + ) qsfp_phy_quad_inst ( + .xcvr_ctrl_clk(clk_125mhz_int), + .xcvr_ctrl_rst(qsfp_rst), + + /* + * Common + */ + .xcvr_gtpowergood_out(qsfp_gtpowergood), + .xcvr_gtrefclk00_in(qsfp_mgt_refclk), + .xcvr_qpll0pd_in(0), + .xcvr_qpll0reset_in(0), + .xcvr_qpll0pcierate_in(0), + .xcvr_gtrefclk01_in(0), + .xcvr_qpll1pd_in(0), + .xcvr_qpll1reset_in(0), + .xcvr_qpll1pcierate_in(0), + + /* + * DRP + */ + .drp_clk(qsfp_drp_clk), + .drp_rst(qsfp_drp_rst), + .drp_addr(qsfp_drp_addr), + .drp_di(qsfp_drp_di), + .drp_en(qsfp_drp_en), + .drp_we(qsfp_drp_we), + .drp_do(qsfp_drp_do), + .drp_rdy(qsfp_drp_rdy), + + /* + * Serial data + */ + .xcvr_txp(qsfp_tx_p), + .xcvr_txn(qsfp_tx_n), + .xcvr_rxp(qsfp_rx_p), + .xcvr_rxn(qsfp_rx_n), + + /* + * PHY connections + */ + .phy_1_tx_clk(qsfp_tx_clk_int), + .phy_1_tx_rst(qsfp_tx_rst_int), + .phy_1_xgmii_txd(qsfp_txd_int), + .phy_1_xgmii_txc(qsfp_txc_int), + .phy_1_rx_clk(qsfp_rx_clk_int), + .phy_1_rx_rst(qsfp_rx_rst_int), + .phy_1_xgmii_rxd(qsfp_rxd_int), + .phy_1_xgmii_rxc(qsfp_rxc_int), + .phy_1_tx_bad_block(), + .phy_1_rx_error_count(qsfp_rx_error_count_int), + .phy_1_rx_bad_block(), + .phy_1_rx_sequence_error(), + .phy_1_rx_block_lock(qsfp_rx_block_lock), + .phy_1_rx_high_ber(), + .phy_1_rx_status(qsfp_rx_status), + .phy_1_cfg_tx_prbs31_enable(qsfp_tx_prbs31_enable_int), + .phy_1_cfg_rx_prbs31_enable(qsfp_rx_prbs31_enable_int)); + + assign clk_156mhz_int = qsfp_mgt_refclk_bufg; + + assign ptp_clk = qsfp_mgt_refclk_bufg; + assign ptp_rst = qsfp_rst; + assign ptp_sample_clk = clk_125mhz_int; + + assign qsfp_led[0] = qsfp_rx_status; + assign qsfp_led[1] = 1'b0; + + assign qsfp_modsell = 1'b0; + assign qsfp_resetl = ~qsfp_reset_reg; + assign qsfp_lpmode = qsfp_lpmode_reg; + + wire [PORT_COUNT-1:0] port_xgmii_tx_clk; + wire [PORT_COUNT-1:0] port_xgmii_tx_rst; + wire [PORT_COUNT*XGMII_DATA_WIDTH-1:0] port_xgmii_txd; + wire [PORT_COUNT*XGMII_CTRL_WIDTH-1:0] port_xgmii_txc; + + wire [PORT_COUNT-1:0] port_xgmii_rx_clk; + wire [PORT_COUNT-1:0] port_xgmii_rx_rst; + wire [PORT_COUNT*XGMII_DATA_WIDTH-1:0] port_xgmii_rxd; + wire [PORT_COUNT*XGMII_CTRL_WIDTH-1:0] port_xgmii_rxc; + + mqnic_port_map_phy_xgmii #( + .PHY_COUNT(1), + .PORT_MASK(PORT_MASK), + .PORT_GROUP_SIZE(1), + + .IF_COUNT(IF_COUNT), + .PORTS_PER_IF(PORTS_PER_IF), + + .PORT_COUNT(PORT_COUNT), + + .XGMII_DATA_WIDTH(XGMII_DATA_WIDTH), + .XGMII_CTRL_WIDTH(XGMII_CTRL_WIDTH) + ) + mqnic_port_map_phy_xgmii_inst ( + // towards PHY + .phy_xgmii_tx_clk({qsfp_tx_clk_int}), + .phy_xgmii_tx_rst({qsfp_tx_rst_int}), + .phy_xgmii_txd({qsfp_txd_int}), + .phy_xgmii_txc({qsfp_txc_int}), + .phy_tx_status(1'b1), + + .phy_xgmii_rx_clk({qsfp_rx_clk_int}), + .phy_xgmii_rx_rst({qsfp_rx_rst_int}), + .phy_xgmii_rxd({qsfp_rxd_int}), + .phy_xgmii_rxc({qsfp_rxc_int}), + .phy_rx_status({qsfp_rx_status}), + + // towards MAC + .port_xgmii_tx_clk(port_xgmii_tx_clk), + .port_xgmii_tx_rst(port_xgmii_tx_rst), + .port_xgmii_txd(port_xgmii_txd), + .port_xgmii_txc(port_xgmii_txc), + .port_tx_status(eth_tx_status), + + .port_xgmii_rx_clk(port_xgmii_rx_clk), + .port_xgmii_rx_rst(port_xgmii_rx_rst), + .port_xgmii_rxd(port_xgmii_rxd), + .port_xgmii_rxc(port_xgmii_rxc), + .port_rx_status(eth_rx_status)); + + generate + genvar n; + + for (n = 0; n < PORT_COUNT; n = n + 1) begin : mac + + assign eth_tx_clk[n] = port_xgmii_tx_clk[n]; + assign eth_tx_rst[n] = port_xgmii_tx_rst[n]; + assign eth_tx_ptp_clk[n] = port_xgmii_tx_clk[n]; + assign eth_tx_ptp_rst[n] = port_xgmii_tx_rst[n]; + assign eth_rx_clk[n] = port_xgmii_rx_clk[n]; + assign eth_rx_rst[n] = port_xgmii_rx_rst[n]; + assign eth_rx_ptp_clk[n] = port_xgmii_rx_clk[n]; + assign eth_rx_ptp_rst[n] = port_xgmii_rx_rst[n]; + + eth_mac_10g #( + .DATA_WIDTH(AXIS_DATA_WIDTH), + .KEEP_WIDTH(AXIS_KEEP_WIDTH), + .ENABLE_PADDING(ENABLE_PADDING), + .ENABLE_DIC(ENABLE_DIC), + .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH), + .PTP_TS_ENABLE(PTP_TS_ENABLE), + .PTP_TS_FMT_TOD(PTP_TS_FMT_TOD), + .PTP_TS_WIDTH(PTP_TS_WIDTH), + .TX_PTP_TS_CTRL_IN_TUSER(0), + .TX_PTP_TAG_ENABLE(PTP_TS_ENABLE), + .TX_PTP_TAG_WIDTH(TX_TAG_WIDTH), + .TX_USER_WIDTH(AXIS_TX_USER_WIDTH), + .RX_USER_WIDTH(AXIS_RX_USER_WIDTH), + .PFC_ENABLE(PFC_ENABLE), + .PAUSE_ENABLE(LFC_ENABLE) + ) eth_mac_inst ( + .tx_clk(port_xgmii_tx_clk[n]), + .tx_rst(port_xgmii_tx_rst[n]), + .rx_clk(port_xgmii_rx_clk[n]), + .rx_rst(port_xgmii_rx_rst[n]), + + /* + * AXI input + */ + .tx_axis_tdata(axis_eth_tx_tdata[n*AXIS_DATA_WIDTH +: AXIS_DATA_WIDTH]), + .tx_axis_tkeep(axis_eth_tx_tkeep[n*AXIS_KEEP_WIDTH +: AXIS_KEEP_WIDTH]), + .tx_axis_tvalid(axis_eth_tx_tvalid[n +: 1]), + .tx_axis_tready(axis_eth_tx_tready[n +: 1]), + .tx_axis_tlast(axis_eth_tx_tlast[n +: 1]), + .tx_axis_tuser(axis_eth_tx_tuser[n*AXIS_TX_USER_WIDTH +: AXIS_TX_USER_WIDTH]), + + /* + * AXI output + */ + .rx_axis_tdata(axis_eth_rx_tdata[n*AXIS_DATA_WIDTH +: AXIS_DATA_WIDTH]), + .rx_axis_tkeep(axis_eth_rx_tkeep[n*AXIS_KEEP_WIDTH +: AXIS_KEEP_WIDTH]), + .rx_axis_tvalid(axis_eth_rx_tvalid[n +: 1]), + .rx_axis_tlast(axis_eth_rx_tlast[n +: 1]), + .rx_axis_tuser(axis_eth_rx_tuser[n*AXIS_RX_USER_WIDTH +: AXIS_RX_USER_WIDTH]), + + /* + * XGMII interface + */ + .xgmii_rxd(port_xgmii_rxd[n*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]), + .xgmii_rxc(port_xgmii_rxc[n*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]), + .xgmii_txd(port_xgmii_txd[n*XGMII_DATA_WIDTH +: XGMII_DATA_WIDTH]), + .xgmii_txc(port_xgmii_txc[n*XGMII_CTRL_WIDTH +: XGMII_CTRL_WIDTH]), + + /* + * PTP + */ + .tx_ptp_ts(eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .rx_ptp_ts(eth_rx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .tx_axis_ptp_ts(axis_eth_tx_ptp_ts[n*PTP_TS_WIDTH +: PTP_TS_WIDTH]), + .tx_axis_ptp_ts_tag(axis_eth_tx_ptp_ts_tag[n*TX_TAG_WIDTH +: TX_TAG_WIDTH]), + .tx_axis_ptp_ts_valid(axis_eth_tx_ptp_ts_valid[n +: 1]), + + /* + * Link-level Flow Control (LFC) (IEEE 802.3 annex 31B PAUSE) + */ + .tx_lfc_req(eth_tx_lfc_req[n +: 1]), + .tx_lfc_resend(1'b0), + .rx_lfc_en(eth_rx_lfc_en[n +: 1]), + .rx_lfc_req(eth_rx_lfc_req[n +: 1]), + .rx_lfc_ack(eth_rx_lfc_ack[n +: 1]), + + /* + * Priority Flow Control (PFC) (IEEE 802.3 annex 31D PFC) + */ + .tx_pfc_req(eth_tx_pfc_req[n*8 +: 8]), + .tx_pfc_resend(1'b0), + .rx_pfc_en(eth_rx_pfc_en[n*8 +: 8]), + .rx_pfc_req(eth_rx_pfc_req[n*8 +: 8]), + .rx_pfc_ack(eth_rx_pfc_ack[n*8 +: 8]), + + /* + * Pause interface + */ + .tx_lfc_pause_en(1'b1), + .tx_pause_req(1'b0), + .tx_pause_ack(), + + /* + * Status + */ + .tx_start_packet(), + .tx_error_underflow(), + .rx_start_packet(), + .rx_error_bad_frame(), + .rx_error_bad_fcs(), + .stat_tx_mcf(), + .stat_rx_mcf(), + .stat_tx_lfc_pkt(), + .stat_tx_lfc_xon(), + .stat_tx_lfc_xoff(), + .stat_tx_lfc_paused(), + .stat_tx_pfc_pkt(), + .stat_tx_pfc_xon(), + .stat_tx_pfc_xoff(), + .stat_tx_pfc_paused(), + .stat_rx_lfc_pkt(), + .stat_rx_lfc_xon(), + .stat_rx_lfc_xoff(), + .stat_rx_lfc_paused(), + .stat_rx_pfc_pkt(), + .stat_rx_pfc_xon(), + .stat_rx_pfc_xoff(), + .stat_rx_pfc_paused(), + + /* + * Configuration + */ + .cfg_ifg(8'd12), + .cfg_tx_enable(eth_tx_enable[n +: 1]), + .cfg_rx_enable(eth_rx_enable[n +: 1]), + .cfg_mcf_rx_eth_dst_mcast(48'h01_80_C2_00_00_01), + .cfg_mcf_rx_check_eth_dst_mcast(1'b1), + .cfg_mcf_rx_eth_dst_ucast(48'd0), + .cfg_mcf_rx_check_eth_dst_ucast(1'b0), + .cfg_mcf_rx_eth_src(48'd0), + .cfg_mcf_rx_check_eth_src(1'b0), + .cfg_mcf_rx_eth_type(16'h8808), + .cfg_mcf_rx_opcode_lfc(16'h0001), + .cfg_mcf_rx_check_opcode_lfc(eth_rx_lfc_en[n +: 1]), + .cfg_mcf_rx_opcode_pfc(16'h0101), + .cfg_mcf_rx_check_opcode_pfc(eth_rx_pfc_en[n*8 +: 8] != 0), + .cfg_mcf_rx_forward(1'b0), + .cfg_mcf_rx_enable(eth_rx_lfc_en[n +: 1] || eth_rx_pfc_en[n*8 +: 8]), + .cfg_tx_lfc_eth_dst(48'h01_80_C2_00_00_01), + .cfg_tx_lfc_eth_src(48'h80_23_31_43_54_4C), + .cfg_tx_lfc_eth_type(16'h8808), + .cfg_tx_lfc_opcode(16'h0001), + .cfg_tx_lfc_en(eth_tx_lfc_en[n +: 1]), + .cfg_tx_lfc_quanta(16'hffff), + .cfg_tx_lfc_refresh(16'h7fff), + .cfg_tx_pfc_eth_dst(48'h01_80_C2_00_00_01), + .cfg_tx_pfc_eth_src(48'h80_23_31_43_54_4C), + .cfg_tx_pfc_eth_type(16'h8808), + .cfg_tx_pfc_opcode(16'h0101), + .cfg_tx_pfc_en(eth_tx_pfc_en[n*8 +: 8] != 0), + .cfg_tx_pfc_quanta({8{16'hffff}}), + .cfg_tx_pfc_refresh({8{16'h7fff}}), + .cfg_rx_lfc_opcode(16'h0001), + .cfg_rx_lfc_en(eth_rx_lfc_en[n +: 1]), + .cfg_rx_pfc_opcode(16'h0101), + .cfg_rx_pfc_en(eth_rx_pfc_en[n*8 +: 8] != 0)); + end + + endgenerate + + generate + + if (TDMA_BER_ENABLE) begin + + // BER tester + tdma_ber #( + .COUNT(1), + .INDEX_WIDTH(6), + .SLICE_WIDTH(5), + .AXIL_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), + .AXIL_ADDR_WIDTH(8+6+$clog2(1)), + .AXIL_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), + .SCHEDULE_START_S(0), + .SCHEDULE_START_NS(0), + .SCHEDULE_PERIOD_S(0), + .SCHEDULE_PERIOD_NS(1000000), + .TIMESLOT_PERIOD_S(0), + .TIMESLOT_PERIOD_NS(100000), + .ACTIVE_PERIOD_S(0), + .ACTIVE_PERIOD_NS(90000) + ) tdma_ber_inst ( + .clk(clk), + .rst(rst), + .phy_tx_clk({qsfp_tx_clk_int}), + .phy_rx_clk({qsfp_rx_clk_int}), + .phy_rx_error_count({qsfp_rx_error_count_int}), + .phy_cfg_tx_prbs31_enable({qsfp_cfg_tx_prbs31_enable_int}), + .phy_cfg_rx_prbs31_enable({qsfp_cfg_rx_prbs31_enable_int}), + .s_axil_awaddr(s_axil_csr_awaddr), + .s_axil_awprot(s_axil_csr_awprot), + .s_axil_awvalid(s_axil_csr_awvalid), + .s_axil_awready(s_axil_csr_awready), + .s_axil_wdata(s_axil_csr_wdata), + .s_axil_wstrb(s_axil_csr_wstrb), + .s_axil_wvalid(s_axil_csr_wvalid), + .s_axil_wready(s_axil_csr_wready), + .s_axil_bresp(s_axil_csr_bresp), + .s_axil_bvalid(s_axil_csr_bvalid), + .s_axil_bready(s_axil_csr_bready), + .s_axil_araddr(s_axil_csr_araddr), + .s_axil_arprot(s_axil_csr_arprot), + .s_axil_arvalid(s_axil_csr_arvalid), + .s_axil_arready(s_axil_csr_arready), + .s_axil_rdata(s_axil_csr_rdata), + .s_axil_rresp(s_axil_csr_rresp), + .s_axil_rvalid(s_axil_csr_rvalid), + .s_axil_rready(s_axil_csr_rready), + .ptp_ts_96(ptp_sync_ts_tod), + .ptp_ts_step(ptp_sync_ts_tod_step)); + + end else begin + + assign qsfp_cfg_tx_prbs31_enable = 1'b0; + assign qsfp_cfg_rx_prbs31_enable = 1'b0; + + end + endgenerate + + wire qsfp_drp_reg_wr_wait; + wire qsfp_drp_reg_wr_ack; + wire [AXIL_CTRL_DATA_WIDTH-1:0] qsfp_drp_reg_rd_data; + wire qsfp_drp_reg_rd_wait; + wire qsfp_drp_reg_rd_ack; + + wire qsfp_modprsl_int; + wire qsfp_intl_int; + + reg ctrl_reg_wr_ack_reg = 1'b0; + reg [AXIL_CTRL_DATA_WIDTH-1:0] ctrl_reg_rd_data_reg = {AXIL_CTRL_DATA_WIDTH{1'b0}}; + reg ctrl_reg_rd_ack_reg = 1'b0; + + reg qsfp_reset_reg = 1'b0; + reg qsfp_lpmode_reg = 1'b0; + + reg i2c_scl_o_reg = 1'b1; + reg i2c_sda_o_reg = 1'b1; + + assign ctrl_reg_wr_wait = qsfp_drp_reg_wr_wait; + assign ctrl_reg_wr_ack = ctrl_reg_wr_ack_reg | qsfp_drp_reg_wr_ack; + assign ctrl_reg_rd_data = ctrl_reg_rd_data_reg | qsfp_drp_reg_rd_data; + assign ctrl_reg_rd_wait = qsfp_drp_reg_rd_wait; + assign ctrl_reg_rd_ack = ctrl_reg_rd_ack_reg | qsfp_drp_reg_rd_ack; + + always @(posedge clk) begin + ctrl_reg_wr_ack_reg <= 1'b0; + ctrl_reg_rd_data_reg <= {AXIL_CTRL_DATA_WIDTH{1'b0}}; + ctrl_reg_rd_ack_reg <= 1'b0; + + if (ctrl_reg_wr_en && !ctrl_reg_wr_ack_reg) begin + // write operation + ctrl_reg_wr_ack_reg <= 1'b0; + case ({ctrl_reg_wr_addr >> 2, 2'b00}) + // I2C 0 + RBB+8'h0C: begin + // I2C ctrl: control + if (ctrl_reg_wr_strb[0]) begin + i2c_scl_o_reg <= ctrl_reg_wr_data[1]; + end + if (ctrl_reg_wr_strb[1]) begin + i2c_sda_o_reg <= ctrl_reg_wr_data[9]; + end + end + // XCVR GPIO + RBB+8'h1C: begin + // XCVR GPIO: control 0123 + if (ctrl_reg_wr_strb[0]) begin + qsfp_reset_reg <= ctrl_reg_wr_data[4]; + qsfp_lpmode_reg <= ctrl_reg_wr_data[5]; + end + end + default: ctrl_reg_wr_ack_reg <= 1'b0; + endcase + end + + if (ctrl_reg_rd_en && !ctrl_reg_rd_ack_reg) begin + // read operation + ctrl_reg_rd_ack_reg <= 1'b1; + case ({ctrl_reg_rd_addr >> 2, 2'b00}) + // I2C 0 + RBB+8'h00: ctrl_reg_rd_data_reg <= 32'h0000C110; // I2C ctrl: Type + RBB+8'h04: ctrl_reg_rd_data_reg <= 32'h00000100; // I2C ctrl: Version + RBB+8'h08: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h10; // I2C ctrl: Next header + RBB+8'h0C: begin + // I2C ctrl: control + ctrl_reg_rd_data_reg[0] <= i2c_scl_i; + ctrl_reg_rd_data_reg[1] <= i2c_scl_o_reg; + ctrl_reg_rd_data_reg[8] <= i2c_sda_i; + ctrl_reg_rd_data_reg[9] <= i2c_sda_o_reg; + end + // XCVR GPIO + RBB+8'h10: ctrl_reg_rd_data_reg <= 32'h0000C101; // XCVR GPIO: Type + RBB+8'h14: ctrl_reg_rd_data_reg <= 32'h00000100; // XCVR GPIO: Version + RBB+8'h18: ctrl_reg_rd_data_reg <= RB_BASE_ADDR+8'h20; // XCVR GPIO: Next header + RBB+8'h1C: begin + // XCVR GPIO: control 0123 + ctrl_reg_rd_data_reg[0] <= !qsfp_modprsl_int; + ctrl_reg_rd_data_reg[1] <= !qsfp_intl_int; + ctrl_reg_rd_data_reg[4] <= qsfp_reset_reg; + ctrl_reg_rd_data_reg[5] <= qsfp_lpmode_reg; + end + default: ctrl_reg_rd_ack_reg <= 1'b0; + endcase + end + + if (rst) begin + ctrl_reg_wr_ack_reg <= 1'b0; + ctrl_reg_rd_ack_reg <= 1'b0; + + qsfp_reset_reg <= 1'b0; + qsfp_lpmode_reg <= 1'b0; + + i2c_scl_o_reg <= 1'b1; + i2c_sda_o_reg <= 1'b1; + end + end + + rb_drp #( + .DRP_ADDR_WIDTH(24), + .DRP_DATA_WIDTH(16), + .DRP_INFO({8'h09, 8'h02, 8'd0, 8'd1}), + .REG_ADDR_WIDTH(AXIL_CSR_ADDR_WIDTH), + .REG_DATA_WIDTH(AXIL_CTRL_DATA_WIDTH), + .REG_STRB_WIDTH(AXIL_CTRL_STRB_WIDTH), + .RB_BASE_ADDR(RB_DRP_QSFP_BASE), + .RB_NEXT_PTR(0) + ) qsfp_rb_drp_inst ( + .clk(clk), + .rst(rst), + + /* + * Register interface + */ + .reg_wr_addr(ctrl_reg_wr_addr), + .reg_wr_data(ctrl_reg_wr_data), + .reg_wr_strb(ctrl_reg_wr_strb), + .reg_wr_en(ctrl_reg_wr_en), + .reg_wr_wait(qsfp_drp_reg_wr_wait), + .reg_wr_ack(qsfp_drp_reg_wr_ack), + .reg_rd_addr(ctrl_reg_rd_addr), + .reg_rd_en(ctrl_reg_rd_en), + .reg_rd_data(qsfp_drp_reg_rd_data), + .reg_rd_wait(qsfp_drp_reg_rd_wait), + .reg_rd_ack(qsfp_drp_reg_rd_ack), + + /* + * DRP + */ + .drp_clk(qsfp_drp_clk), + .drp_rst(qsfp_drp_rst), + .drp_addr(qsfp_drp_addr), + .drp_di(qsfp_drp_di), + .drp_en(qsfp_drp_en), + .drp_we(qsfp_drp_we), + .drp_do(qsfp_drp_do), + .drp_rdy(qsfp_drp_rdy)); + +endmodule diff --git a/library/corundum/ethernet/adrv9009zu11eg/ethernet_adrv9009zu11eg_ip.tcl b/library/corundum/ethernet/adrv9009zu11eg/ethernet_adrv9009zu11eg_ip.tcl new file mode 100644 index 00000000000..1692d78c5f1 --- /dev/null +++ b/library/corundum/ethernet/adrv9009zu11eg/ethernet_adrv9009zu11eg_ip.tcl @@ -0,0 +1,337 @@ +############################################################################### +## Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source ../../../../scripts/adi_env.tcl +source $ad_hdl_dir/library/scripts/adi_ip_xilinx.tcl + +global VIVADO_IP_LIBRARY + +adi_ip_create ethernet_adrv9009zu11eg + +set_property part xczu11eg-ffvf1517-2-i [current_project] + +source $ad_hdl_dir/../corundum/fpga/mqnic/ZCU102/fpga/ip/eth_xcvr_gth.tcl + +# Corundum sources +adi_ip_files ethernet_adrv9009zu11eg [list \ + "ethernet_adrv9009zu11eg.v" \ + "$ad_hdl_dir/../corundum/fpga/mqnic/KR260/fpga/rtl/sync_signal.v" \ + "$ad_hdl_dir/../corundum/fpga/common/rtl/eth_xcvr_phy_10g_gty_quad_wrapper.v" \ + "$ad_hdl_dir/../corundum/fpga/common/rtl/eth_xcvr_phy_10g_gty_wrapper.v" \ + "$ad_hdl_dir/../corundum/fpga/lib/eth/rtl/eth_phy_10g.v" \ + "$ad_hdl_dir/../corundum/fpga/lib/eth/rtl/eth_phy_10g_tx_if.v" \ + "$ad_hdl_dir/../corundum/fpga/lib/eth/rtl/eth_phy_10g_tx.v" \ + "$ad_hdl_dir/../corundum/fpga/lib/eth/rtl/eth_phy_10g_rx.v" \ + "$ad_hdl_dir/../corundum/fpga/lib/eth/rtl/eth_phy_10g_rx_frame_sync.v" \ + "$ad_hdl_dir/../corundum/fpga/lib/eth/rtl/eth_phy_10g_rx_if.v" \ + "$ad_hdl_dir/../corundum/fpga/lib/eth/rtl/eth_phy_10g_rx_ber_mon.v" \ + "$ad_hdl_dir/../corundum/fpga/lib/eth/rtl/eth_phy_10g_rx_watchdog.v" \ + "$ad_hdl_dir/../corundum/fpga/lib/eth/rtl/xgmii_baser_dec_64.v" \ + "$ad_hdl_dir/../corundum/fpga/lib/eth/rtl/xgmii_baser_enc_64.v" \ + "$ad_hdl_dir/../corundum/fpga/lib/eth/rtl/axis_xgmii_rx_32.v" \ + "$ad_hdl_dir/../corundum/fpga/lib/eth/rtl/axis_xgmii_tx_32.v" \ + "$ad_hdl_dir/../corundum/fpga/common/rtl/mqnic_port_map_phy_xgmii.v" \ + "$ad_hdl_dir/../corundum/fpga/lib/eth/lib/axis/rtl/sync_reset.v" \ + "$ad_hdl_dir/../corundum/fpga/common/rtl/rb_drp.v" \ + "$ad_hdl_dir/../corundum/fpga/lib/eth/rtl/eth_mac_10g.v" \ + "$ad_hdl_dir/../corundum/fpga/lib/eth/rtl/axis_xgmii_rx_64.v" \ + "$ad_hdl_dir/../corundum/fpga/lib/eth/rtl/axis_xgmii_tx_64.v" \ + "$ad_hdl_dir/../corundum/fpga/lib/eth/rtl/lfsr.v" \ + "$ad_hdl_dir/../corundum/fpga/lib/eth/rtl/mac_ctrl_rx.v" \ + "$ad_hdl_dir/../corundum/fpga/lib/eth/rtl/mac_ctrl_tx.v" \ + "$ad_hdl_dir/../corundum/fpga/lib/eth/rtl/mac_pause_ctrl_rx.v" \ + "$ad_hdl_dir/../corundum/fpga/lib/eth/rtl/mac_pause_ctrl_tx.v" \ +] + +adi_ip_properties_lite ethernet_adrv9009zu11eg + +set cc [ipx::current_core] + +set_property display_name "Corundum Ethernet ADRV9009ZU11EG" $cc +set_property description "Corundum Ethernet Core IP" $cc +set_property company_url {https://analogdevicesinc.github.io/hdl/library/corundum/ethernet/ethernet_adrv9009zu11eg} [ipx::current_core] + +# Remove all inferred interfaces and address spaces +ipx::remove_all_bus_interface [ipx::current_core] +ipx::remove_all_address_space [ipx::current_core] + +# Interface definitions + +adi_add_bus "axis_eth_tx" "slave" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + [ list \ + {"axis_eth_tx_tdata" "TDATA"} \ + {"axis_eth_tx_tkeep" "TKEEP"} \ + {"axis_eth_tx_tvalid" "TVALID"} \ + {"axis_eth_tx_tready" "TREADY"} \ + {"axis_eth_tx_tlast" "TLAST"} \ + {"axis_eth_tx_tuser" "TUSER"} \ + ] + +adi_add_bus_clock "eth_tx_clk" "axis_eth_tx:axis_tx_ptp" "eth_tx_rst" "master" "master" + +adi_add_bus "axis_eth_rx" "master" \ + "xilinx.com:interface:axis_rtl:1.0" \ + "xilinx.com:interface:axis:1.0" \ + [ list \ + {"axis_eth_rx_tdata" "TDATA"} \ + {"axis_eth_rx_tkeep" "TKEEP"} \ + {"axis_eth_rx_tvalid" "TVALID"} \ + {"axis_eth_rx_tready" "TREADY"} \ + {"axis_eth_rx_tlast" "TLAST"} \ + {"axis_eth_rx_tuser" "TUSER"} \ + ] + +adi_add_bus_clock "eth_rx_clk" "axis_eth_rx" "eth_rx_rst" "master" "master" + +adi_if_infer_bus analog.com:interface:if_ctrl_reg slave ctrl_reg [list \ + "ctrl_reg_wr_addr ctrl_reg_wr_addr" \ + "ctrl_reg_wr_data ctrl_reg_wr_data" \ + "ctrl_reg_wr_strb ctrl_reg_wr_strb" \ + "ctrl_reg_wr_en ctrl_reg_wr_en" \ + "ctrl_reg_wr_wait ctrl_reg_wr_wait" \ + "ctrl_reg_wr_ack ctrl_reg_wr_ack" \ + "ctrl_reg_rd_addr ctrl_reg_rd_addr" \ + "ctrl_reg_rd_data ctrl_reg_rd_data" \ + "ctrl_reg_rd_en ctrl_reg_rd_en" \ + "ctrl_reg_rd_wait ctrl_reg_rd_wait" \ + "ctrl_reg_rd_ack ctrl_reg_rd_ack" \ +] + +adi_if_infer_bus analog.com:interface:if_flow_control_tx slave flow_control_tx [list \ + "tx_enable eth_tx_enable" \ + "tx_status eth_tx_status" \ + "tx_lfc_en eth_tx_lfc_en" \ + "tx_lfc_req eth_tx_lfc_req" \ + "tx_pfc_en eth_tx_pfc_en" \ + "tx_pfc_req eth_tx_pfc_req" \ +] + +adi_if_infer_bus analog.com:interface:if_flow_control_rx slave flow_control_rx [list \ + "rx_enable eth_rx_enable" \ + "rx_status eth_rx_status" \ + "rx_lfc_en eth_rx_lfc_en" \ + "rx_lfc_req eth_rx_lfc_req" \ + "rx_lfc_ack eth_rx_lfc_ack" \ + "rx_pfc_en eth_rx_pfc_en" \ + "rx_pfc_req eth_rx_pfc_req" \ + "rx_pfc_ack eth_rx_pfc_ack" \ +] + +adi_if_infer_bus analog.com:interface:if_axis_tx_ptp slave axis_tx_ptp [list \ + "ts axis_eth_tx_ptp_ts" \ + "tag axis_eth_tx_ptp_ts_tag" \ + "valid axis_eth_tx_ptp_ts_valid" \ + "ready axis_eth_tx_ptp_ts_ready" \ +] + +adi_if_infer_bus analog.com:interface:if_ethernet_ptp slave ethernet_ptp_tx [list \ + "ptp_clk eth_tx_clk" \ + "ptp_rst eth_tx_rst" \ + "ptp_ts eth_tx_ptp_ts" \ + "ptp_ts_step eth_tx_ptp_ts_step" \ +] + +adi_if_infer_bus analog.com:interface:if_ethernet_ptp slave ethernet_ptp_rx [list \ + "ptp_clk eth_tx_clk" \ + "ptp_rst eth_tx_rst" \ + "ptp_ts eth_rx_ptp_ts" \ + "ptp_ts_step eth_rx_ptp_ts_step" \ +] + +adi_add_bus_clock "eth_tx_clk" "ethernet_ptp_tx" "eth_tx_rst" "master" "master" +adi_add_bus_clock "eth_rx_clk" "ethernet_ptp_rx" "eth_rx_rst" "master" "master" + +adi_if_infer_bus analog.com:interface:if_flow_control_tx slave flow_control_tx [list \ + "tx_enable eth_tx_enable" \ + "tx_status eth_tx_status" \ + "tx_lfc_en eth_tx_lfc_en" \ + "tx_lfc_req eth_tx_lfc_req" \ + "tx_pfc_en eth_tx_pfc_en" \ + "tx_pfc_req eth_tx_pfc_req" \ + "tx_fc_quanta_clk_en eth_tx_fc_quanta_clk_en" \ +] + +adi_if_infer_bus analog.com:interface:if_flow_control_rx slave flow_control_rx [list \ + "rx_enable eth_rx_enable" \ + "rx_status eth_rx_status" \ + "rx_lfc_en eth_rx_lfc_en" \ + "rx_lfc_req eth_rx_lfc_req" \ + "rx_lfc_ack eth_rx_lfc_ack" \ + "rx_pfc_en eth_rx_pfc_en" \ + "rx_pfc_req eth_rx_pfc_req" \ + "rx_pfc_ack eth_rx_pfc_ack" \ + "rx_fc_quanta_clk_en eth_rx_fc_quanta_clk_en" \ +] + +adi_if_infer_bus analog.com:interface:if_qsfp master qsfp [list \ + "tx_p qsfp_tx_p" \ + "tx_n qsfp_tx_n" \ + "rx_p qsfp_rx_p" \ + "rx_n qsfp_rx_n" \ + "modsell qsfp_modsell" \ + "resetl qsfp_resetl" \ + "modprsl qsfp_modprsl" \ + "intl qsfp_intl" \ + "lpmode qsfp_lpmode" \ + "gtpowergood qsfp_gtpowergood" \ +] + + +adi_if_infer_bus analog.com:interface:if_i2c master iic [list \ + "scl_i i2c_scl_i" \ + "scl_o i2c_scl_o" \ + "scl_t i2c_scl_t" \ + "sda_i i2c_sda_i" \ + "sda_o i2c_sda_o" \ + "sda_t i2c_sda_t" \ +] + +adi_if_infer_bus analog.com:interface:if_ptp slave ptp_clock [list \ + "ptp_td_sd ptp_td_sd" \ + "ptp_pps ptp_pps" \ + "ptp_pps_str ptp_pps_str" \ + "ptp_sync_locked ptp_sync_locked" \ + "ptp_sync_ts_rel ptp_sync_ts_rel" \ + "ptp_sync_ts_rel_step ptp_sync_ts_rel_step" \ + "ptp_sync_ts_tod ptp_sync_ts_tod" \ + "ptp_sync_ts_tod_step ptp_sync_ts_tod_step" \ + "ptp_sync_pps ptp_sync_pps" \ + "ptp_sync_pps_str ptp_sync_pps_str" \ + "ptp_perout_locked ptp_perout_locked" \ + "ptp_perout_error ptp_perout_error" \ + "ptp_perout_pulse ptp_perout_pulse" \ +] + +adi_add_bus "s_axil_csr" "slave" \ + "xilinx.com:interface:aximm_rtl:1.0" \ + "xilinx.com:interface:aximm:1.0" \ + { + {"s_axil_csr_awaddr" "AWADDR"} \ + {"s_axil_csr_awprot" "AWPROT"} \ + {"s_axil_csr_awvalid" "AWVALID"} \ + {"s_axil_csr_awready" "AWREADY"} \ + {"s_axil_csr_wdata" "WDATA"} \ + {"s_axil_csr_wstrb" "WSTRB"} \ + {"s_axil_csr_wvalid" "WVALID"} \ + {"s_axil_csr_wready" "WREADY"} \ + {"s_axil_csr_bresp" "BRESP"} \ + {"s_axil_csr_bvalid" "BVALID"} \ + {"s_axil_csr_bready" "BREADY"} \ + {"s_axil_csr_araddr" "ARADDR"} \ + {"s_axil_csr_arprot" "ARPROT"} \ + {"s_axil_csr_arvalid" "ARVALID"} \ + {"s_axil_csr_arready" "ARREADY"} \ + {"s_axil_csr_rdata" "RDATA"} \ + {"s_axil_csr_rresp" "RRESP"} \ + {"s_axil_csr_rvalid" "RVALID"} \ + {"s_axil_csr_rready" "RREADY"} \ + } + +## Customize GUI page + +# Remove the automatically generated GUI page +ipgui::remove_page -component $cc [ipgui::get_pagespec -name "Page 0" -component $cc] +ipx::save_core $cc + +# Physical +ipgui::add_page -name {Physical} -component $cc -display_name {Physical} +set page0 [ipgui::get_pagespec -name "Physical" -component $cc] + +set group [ipgui::add_group -name "Structural configuration" -component $cc \ + -parent $page0 -display_name "Structural configuration"] + +ipgui::add_param -name "IF_COUNT" -component $cc -parent $page0 +set p [ipgui::get_guiparamspec -name "IF_COUNT" -component $cc] +ipgui::move_param -component $cc -order 0 $p -parent $group +set_property -dict [list \ + "display_name" "Interface count" \ +] $p + +ipgui::add_param -name "PORTS_PER_IF" -component $cc -parent $page0 +set p [ipgui::get_guiparamspec -name "PORTS_PER_IF" -component $cc] +ipgui::move_param -component $cc -order 1 $p -parent $group +set_property -dict [list \ + "display_name" "Ports per interface" \ +] $p + +ipgui::add_param -name "PORT_MASK" -component $cc -parent $page0 +set p [ipgui::get_guiparamspec -name "PORT_MASK" -component $cc] +ipgui::move_param -component $cc -order 2 $p -parent $group +set_property -dict [list \ + "display_name" "Port mask" \ +] $p + +ipgui::add_page -name {PTP} -component $cc -display_name {PTP Setup} +set page1 [ipgui::get_pagespec -name "PTP" -component $cc] + +set group [ipgui::add_group -name "PTP-related configuration" -component $cc \ +-parent $page1 -display_name "PTP-related configuration"] + +ipgui::add_param -name "PTP_TS_ENABLE" -component $cc -parent $page1 +set p [ipgui::get_guiparamspec -name "PTP_TS_ENABLE" -component $cc] +ipgui::move_param -component $cc -order 0 $p -parent $group +set_property -dict [list \ + "display_name" "PTP Timestamp Enable" \ +] $p + +ipgui::add_param -name "PTP_TS_FMT_TOD" -component $cc -parent $page1 +set p [ipgui::get_guiparamspec -name "PTP_TS_FMT_TOD" -component $cc] +ipgui::move_param -component $cc -order 1 $p -parent $group +set_property -dict [list \ + "display_name" "PTP_TS_FMT_TOD" \ +] $p + +ipgui::add_page -name {Ethernet} -component $cc -display_name {Ethernet Interface Configuration} +set page2 [ipgui::get_pagespec -name "Ethernet" -component $cc] + +set group [ipgui::add_group -name "ETH Interface configuration" -component $cc \ + -parent $page2 -display_name "ETH Interface configuration"] + +ipgui::add_param -name "ENABLE_PADDING" -component $cc -parent $page2 +set p [ipgui::get_guiparamspec -name "ENABLE_PADDING" -component $cc] +ipgui::move_param -component $cc -order 0 $p -parent $group +set_property -dict [list \ + "display_name" "ENABLE_PADDING" \ +] $p + +ipgui::add_param -name "ENABLE_DIC" -component $cc -parent $page2 +set p [ipgui::get_guiparamspec -name "ENABLE_DIC" -component $cc] +ipgui::move_param -component $cc -order 1 $p -parent $group +set_property -dict [list \ + "display_name" "ENABLE_DIC" \ +] $p + +ipgui::add_param -name "MIN_FRAME_LENGTH" -component $cc -parent $page2 +set p [ipgui::get_guiparamspec -name "MIN_FRAME_LENGTH" -component $cc] +ipgui::move_param -component $cc -order 2 $p -parent $group +set_property -dict [list \ + "display_name" "MIN_FRAME_LENGTH" \ +] $p + +ipgui::add_param -name "PFC_ENABLE" -component $cc -parent $page2 +set p [ipgui::get_guiparamspec -name "PFC_ENABLE" -component $cc] +ipgui::move_param -component $cc -order 3 $p -parent $group +set_property -dict [list \ + "display_name" "PFC_ENABLE" \ +] $p + +ipgui::add_param -name "AXIL_CSR_ENABLE" -component $cc -parent $page2 +set p [ipgui::get_guiparamspec -name "AXIL_CSR_ENABLE" -component $cc] +ipgui::move_param -component $cc -order 3 $p -parent $group +set_property -dict [list \ + "widget" "checkBox" \ + "display_name" "AXI4 Lite CSR enable" \ +] $p + +## Dependencies + +adi_set_bus_dependency "s_axil_csr" "s_axil_csr" \ + "(spirit:decode(id('PARAM_VALUE.AXIL_CSR_ENABLE')) = 1)" + +## Create and save the XGUI file +ipx::create_xgui_files $cc +ipx::save_core $cc diff --git a/library/corundum/scripts/corundum.tcl b/library/corundum/scripts/corundum.tcl index 9d0b190471c..2461b11abbd 100644 --- a/library/corundum/scripts/corundum.tcl +++ b/library/corundum/scripts/corundum.tcl @@ -52,6 +52,15 @@ if [info exists ::env(BOARD)] { create_bd_pin -dir I -type clk clk_125mhz create_bd_pin -dir I -type rst rst_125mhz + } elseif [string equal $board ADRV9009ZU11EG] { + + create_bd_pin -dir O -type rst qsfp_rst + create_bd_pin -dir I qsfp_mgt_refclk_p + create_bd_pin -dir I qsfp_mgt_refclk_n + + create_bd_intf_pin -mode Master -vlnv analog.com:interface:if_qsfp_rtl:1.0 qsfp + create_bd_intf_pin -mode Master -vlnv analog.com:interface:if_i2c_rtl:1.0 qsfp_iic + } else { create_bd_pin -dir I sfp_rx_p create_bd_pin -dir I sfp_rx_n @@ -162,6 +171,98 @@ if [string equal $board K26] { MIN_FRAME_LENGTH $MIN_FRAME_LENGTH \ PFC_ENABLE $PFC_ENABLE \ ] +} elseif [string equal $board ADRV9009ZU11EG] { + ad_ip_instance corundum_core corundum_core [list \ + FPGA_ID $FPGA_ID \ + FW_ID $FW_ID \ + FW_VER $FW_VER \ + BOARD_ID $BOARD_ID \ + BOARD_VER $BOARD_VER \ + BUILD_DATE $BUILD_DATE \ + GIT_HASH $GIT_HASH \ + RELEASE_INFO $RELEASE_INFO \ + IF_COUNT $IF_COUNT \ + PORTS_PER_IF $PORTS_PER_IF \ + SCHED_PER_IF $SCHED_PER_IF \ + PORT_COUNT $PORT_COUNT \ + CLK_PERIOD_NS_NUM $CLK_PERIOD_NS_NUM \ + CLK_PERIOD_NS_DENOM $CLK_PERIOD_NS_DENOM \ + PTP_CLOCK_PIPELINE $PTP_CLOCK_PIPELINE \ + PTP_CLOCK_CDC_PIPELINE $PTP_CLOCK_CDC_PIPELINE \ + PTP_PORT_CDC_PIPELINE $PTP_PORT_CDC_PIPELINE \ + PTP_PEROUT_ENABLE $PTP_PEROUT_ENABLE \ + PTP_PEROUT_COUNT $PTP_PEROUT_COUNT \ + EVENT_QUEUE_OP_TABLE_SIZE $EVENT_QUEUE_OP_TABLE_SIZE \ + TX_QUEUE_OP_TABLE_SIZE $TX_QUEUE_OP_TABLE_SIZE \ + RX_QUEUE_OP_TABLE_SIZE $RX_QUEUE_OP_TABLE_SIZE \ + CQ_OP_TABLE_SIZE $CQ_OP_TABLE_SIZE \ + EQN_WIDTH $EQN_WIDTH \ + TX_QUEUE_INDEX_WIDTH $TX_QUEUE_INDEX_WIDTH \ + RX_QUEUE_INDEX_WIDTH $RX_QUEUE_INDEX_WIDTH \ + CQN_WIDTH $CQN_WIDTH \ + EQ_PIPELINE $EQ_PIPELINE \ + TX_QUEUE_PIPELINE $TX_QUEUE_PIPELINE \ + RX_QUEUE_PIPELINE $RX_QUEUE_PIPELINE \ + CQ_PIPELINE $CQ_PIPELINE \ + TX_DESC_TABLE_SIZE $TX_DESC_TABLE_SIZE \ + RX_DESC_TABLE_SIZE $RX_DESC_TABLE_SIZE \ + RX_INDIR_TBL_ADDR_WIDTH $RX_INDIR_TBL_ADDR_WIDTH \ + TX_SCHEDULER_OP_TABLE_SIZE $TX_SCHEDULER_OP_TABLE_SIZE \ + TX_SCHEDULER_PIPELINE $TX_SCHEDULER_PIPELINE \ + TDMA_INDEX_WIDTH $TDMA_INDEX_WIDTH \ + PTP_TS_ENABLE $PTP_TS_ENABLE \ + PTP_TS_FMT_TOD $PTP_TS_FMT_TOD \ + TX_CPL_FIFO_DEPTH $TX_CPL_FIFO_DEPTH \ + TX_CHECKSUM_ENABLE $TX_CHECKSUM_ENABLE \ + RX_HASH_ENABLE $RX_HASH_ENABLE \ + RX_CHECKSUM_ENABLE $RX_CHECKSUM_ENABLE \ + TX_FIFO_DEPTH $TX_FIFO_DEPTH \ + RX_FIFO_DEPTH $RX_FIFO_DEPTH \ + MAX_TX_SIZE $MAX_TX_SIZE \ + MAX_RX_SIZE $MAX_RX_SIZE \ + TX_RAM_SIZE $TX_RAM_SIZE \ + RX_RAM_SIZE $RX_RAM_SIZE \ + APP_ENABLE $APP_ENABLE \ + APP_ID $APP_ID \ + APP_CTRL_ENABLE $APP_CTRL_ENABLE \ + APP_DMA_ENABLE $APP_DMA_ENABLE \ + APP_AXIS_DIRECT_ENABLE $APP_AXIS_DIRECT_ENABLE \ + APP_AXIS_SYNC_ENABLE $APP_AXIS_SYNC_ENABLE \ + APP_AXIS_IF_ENABLE $APP_AXIS_IF_ENABLE \ + APP_STAT_ENABLE $APP_STAT_ENABLE \ + AXI_DATA_WIDTH $AXI_DATA_WIDTH \ + AXI_ADDR_WIDTH $AXI_ADDR_WIDTH \ + AXI_ID_WIDTH $AXI_ID_WIDTH \ + DMA_IMM_ENABLE $DMA_IMM_ENABLE \ + DMA_IMM_WIDTH $DMA_IMM_WIDTH \ + DMA_LEN_WIDTH $DMA_LEN_WIDTH \ + DMA_TAG_WIDTH $DMA_TAG_WIDTH \ + RAM_ADDR_WIDTH $RAM_ADDR_WIDTH \ + RAM_PIPELINE $RAM_PIPELINE \ + AXI_DMA_MAX_BURST_LEN $AXI_DMA_MAX_BURST_LEN \ + IRQ_COUNT $IRQ_COUNT \ + AXIL_CTRL_DATA_WIDTH $AXIL_CTRL_DATA_WIDTH \ + AXIL_CTRL_ADDR_WIDTH $AXIL_CTRL_ADDR_WIDTH \ + AXIL_APP_CTRL_DATA_WIDTH $AXIL_APP_CTRL_DATA_WIDTH \ + AXIL_APP_CTRL_ADDR_WIDTH $AXIL_APP_CTRL_ADDR_WIDTH \ + STAT_ENABLE $STAT_ENABLE \ + STAT_DMA_ENABLE $STAT_DMA_ENABLE \ + STAT_AXI_ENABLE $STAT_AXI_ENABLE \ + STAT_INC_WIDTH $STAT_INC_WIDTH \ + STAT_ID_WIDTH $STAT_ID_WIDTH + ] + + ad_ip_instance ethernet_adrv9009zu11eg ethernet_core [list \ + IF_COUNT $IF_COUNT \ + PORTS_PER_IF $PORTS_PER_IF \ + PORT_MASK $PORT_MASK \ + PTP_TS_ENABLE $PTP_TS_ENABLE \ + PTP_TS_FMT_TOD $PTP_TS_FMT_TOD \ + ENABLE_PADDING $ENABLE_PADDING \ + ENABLE_DIC $ENABLE_DIC \ + MIN_FRAME_LENGTH $MIN_FRAME_LENGTH \ + PFC_ENABLE $PFC_ENABLE + ] } else { ad_ip_instance corundum_core corundum_core [list \ FPGA_ID $FPGA_ID \ @@ -398,6 +499,20 @@ if [string equal $board K26] { ad_connect ethernet_core/iic sfp_iic + ad_connect ethernet_core/ptp_clock corundum_core/ptp_clock + ad_connect corundum_core/ptp_clk ethernet_core/ptp_clk + ad_connect corundum_core/ptp_rst ethernet_core/ptp_rst + ad_connect corundum_core/ptp_sample_clk ethernet_core/ptp_sample_clk + +} elseif [string equal $board ADRV9009ZU11EG] { + + ad_connect ethernet_core/qsfp_mgt_refclk_p qsfp_mgt_refclk_p + ad_connect ethernet_core/qsfp_mgt_refclk_n qsfp_mgt_refclk_n + ad_connect ethernet_core/qsfp_rst qsfp_rst + ad_connect ethernet_core/qsfp qsfp + + ad_connect ethernet_core/iic qsfp_iic + ad_connect ethernet_core/ptp_clock corundum_core/ptp_clock ad_connect corundum_core/ptp_clk ethernet_core/ptp_clk ad_connect corundum_core/ptp_rst ethernet_core/ptp_rst @@ -665,7 +780,9 @@ ad_ip_instance proc_sys_reset corundum_rstgen [list \ ad_connect corundum_hierarchy/rst_corundum corundum_rstgen/peripheral_reset -if {![string equal $CPU Zynq]} { +# only for MicroBlaze variant of the project, add AXI GPIO to control +# the Corundum Reset Generator +if {[string equal $CPU MB]} { ad_ip_instance axi_gpio corundum_gpio_reset [list \ C_ALL_OUTPUTS 1 \ C_DOUT_DEFAULT 0x00000000 \ @@ -673,4 +790,5 @@ if {![string equal $CPU Zynq]} { ] ad_connect corundum_gpio_reset/gpio_io_o corundum_rstgen/aux_reset_in -} + +} \ No newline at end of file diff --git a/library/corundum/scripts/corundum_adrv9009zu11eg_cfg.tcl b/library/corundum/scripts/corundum_adrv9009zu11eg_cfg.tcl new file mode 100644 index 00000000000..40060a9d8a1 --- /dev/null +++ b/library/corundum/scripts/corundum_adrv9009zu11eg_cfg.tcl @@ -0,0 +1,167 @@ +############################################################################### +## Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set build_date [clock seconds] +set git_hash 00000000 +set git_tag "" +set tag_ver 0.0.1 + +puts "Build date: ${build_date}" +puts "Git hash: ${git_hash}" +puts "Git tag: ${git_tag}" + +# FW and board IDs +set fpga_id [expr 0x4A49093] +set fw_id [expr 0x00000000] +set fw_ver $tag_ver +set board_vendor_id [expr 0x10ee] +set board_device_id [expr 0x9104] +set board_ver 1.0 +set release_info [expr 0x00000000] + +# FW ID block +set FPGA_ID [format "32'h%08x" $fpga_id] +set FW_ID [format "32'h%08x" $fw_id] +set FW_VER [format "32'h%02x%02x%02x%02x" {*}[split $fw_ver .-] 0 0 0 0] +set BOARD_ID [format "32'h%04x%04x" $board_vendor_id $board_device_id] +set BOARD_VER [format "32'h%02x%02x%02x%02x" {*}[split $board_ver .-] 0 0 0 0] +set BUILD_DATE "32'd${build_date}" +set GIT_HASH "32'h${git_hash}" +set RELEASE_INFO [format "32'h%08x" $release_info] + +# Board configuration +set TDMA_BER_ENABLE "0" + +# Structural configuration +set IF_COUNT "1" +set PORTS_PER_IF "1" +set PORT_COUNT "1" +set SCHED_PER_IF $PORTS_PER_IF +set PORT_MASK "0" + +# Clock configuration +set CLK_PERIOD_NS_NUM "4" +set CLK_PERIOD_NS_DENOM "1" + +# PTP configuration +set PTP_CLOCK_PIPELINE "0" +set PTP_CLOCK_CDC_PIPELINE "0" +set PTP_PORT_CDC_PIPELINE "0" +set PTP_PEROUT_ENABLE "1" +set PTP_PEROUT_COUNT "1" + +# Queue manager configuration +set EVENT_QUEUE_OP_TABLE_SIZE "32" +set TX_QUEUE_OP_TABLE_SIZE "32" +set RX_QUEUE_OP_TABLE_SIZE "32" +set CQ_OP_TABLE_SIZE "32" +set EQN_WIDTH "2" +set TX_QUEUE_INDEX_WIDTH "5" +set RX_QUEUE_INDEX_WIDTH "5" +set CQN_WIDTH [expr max($TX_QUEUE_INDEX_WIDTH, $RX_QUEUE_INDEX_WIDTH) + 1] +set TX_QUEUE_PIPELINE [expr 3 + max($TX_QUEUE_INDEX_WIDTH - 12, 0)] +set RX_QUEUE_PIPELINE [expr 3 + max($RX_QUEUE_INDEX_WIDTH - 12, 0)] +set EQ_PIPELINE "3" +set CQ_PIPELINE [expr 3 + max($CQN_WIDTH - 12, 0)] + +# TX and RX engine configuration +set TX_DESC_TABLE_SIZE "32" +set RX_DESC_TABLE_SIZE "32" +set RX_INDIR_TBL_ADDR_WIDTH [expr min($RX_QUEUE_INDEX_WIDTH, 8)] + +# Scheduler configuration +set TX_SCHEDULER_OP_TABLE_SIZE $TX_DESC_TABLE_SIZE +set TX_SCHEDULER_PIPELINE $TX_QUEUE_PIPELINE +set TDMA_INDEX_WIDTH "6" + +# Interface configuration +set PTP_TS_ENABLE "1" +set PTP_TS_FMT_TOD "0" +set TX_CPL_FIFO_DEPTH "32" +set TX_CHECKSUM_ENABLE "1" +set RX_HASH_ENABLE "1" +set RX_CHECKSUM_ENABLE "1" +set PFC_ENABLE "1" +set LFC_ENABLE $PFC_ENABLE +set ENABLE_PADDING "1" +set ENABLE_DIC "1" +set MIN_FRAME_LENGTH "64" +set TX_FIFO_DEPTH "32768" +set RX_FIFO_DEPTH "65536" +set MAX_TX_SIZE "9214" +set MAX_RX_SIZE "9214" +set TX_RAM_SIZE "32768" +set RX_RAM_SIZE "32768" + +# Application block configuration +set APP_ID "32'h00000000" +set APP_ENABLE "0" +set APP_CTRL_ENABLE "0" +set APP_DMA_ENABLE "0" +set APP_AXIS_DIRECT_ENABLE "0" +set APP_AXIS_SYNC_ENABLE "0" +set APP_AXIS_IF_ENABLE "0" +set APP_STAT_ENABLE "0" + +# AXI DMA interface configuration +# dict set params AXI_ADDR_WIDTH [get_property CONFIG.ADDR_WIDTH $s_axi_dma] +set AXI_ADDR_WIDTH 64 +set AXI_ID_WIDTH 8 + +# DMA interface configuration +set DMA_IMM_ENABLE "0" +set DMA_IMM_WIDTH "32" +set DMA_LEN_WIDTH "16" +set DMA_TAG_WIDTH "16" +set RAM_ADDR_WIDTH [expr int(ceil(log(max($TX_RAM_SIZE, $RX_RAM_SIZE))/log(2)))] +set RAM_PIPELINE "2" +# NOTE: Querying the BD top-level interface port (or even the ZynqMP's interface +# pin) yields 256 for the maximum burst length, instead of 16, which is +# the actually supported length (due to ZynqMP using AXI3 internally). +#dict set params AXI_DMA_MAX_BURST_LEN [get_property CONFIG.MAX_BURST_LENGTH $s_axi_dma] +set AXI_DMA_MAX_BURST_LEN "16" + +# AXI lite interface configuration (control) +set AXIL_CTRL_DATA_WIDTH 32 +set AXIL_CTRL_ADDR_WIDTH 24 + +# AXI lite interface configuration (application control) +set AXIL_APP_CTRL_DATA_WIDTH 32 +set AXIL_APP_CTRL_ADDR_WIDTH 24 + +set AXI_DATA_WIDTH 128 +set AXI_ADDR_WIDTH 64 +set AXI_ID_WIDTH 8 + +# Interrupt configuration +set IRQ_COUNT "8" +set IRQ_STRETCH "10" + +# Ethernet interface configuration +set AXIS_ETH_TX_PIPELINE "0" +set AXIS_ETH_TX_FIFO_PIPELINE "2" +set AXIS_ETH_TX_TS_PIPELINE "0" +set AXIS_ETH_RX_PIPELINE "0" +set AXIS_ETH_RX_FIFO_PIPELINE "2" + +# Statistics counter subsystem +set STAT_ENABLE "0" +set STAT_DMA_ENABLE "0" +set STAT_AXI_ENABLE "0" +set STAT_INC_WIDTH "24" +set STAT_ID_WIDTH "12" + +# EXTRA PARAMS +set AXIL_CTRL_DATA_WIDTH 32 +set AXIL_CTRL_ADDR_WIDTH 24 +set AXIL_CTRL_STRB_WIDTH 4 +set AXIL_IF_CTRL_ADDR_WIDTH 24 +set AXIL_CSR_ADDR_WIDTH 19 +set AXIL_CSR_PASSTHROUGH_ENABLE 0 +set AXIL_APP_CTRL_DATA_WIDTH 32 +set AXIL_APP_CTRL_ADDR_WIDTH 24 +set AXIL_APP_CTRL_STRB_WIDTH 4 +set DDR_ENABLE 0 +set HBM_ENABLE 0 diff --git a/projects/adrv9009zu11eg/adrv2crr_fmc/Makefile b/projects/adrv9009zu11eg/adrv2crr_fmc/Makefile index fc4790574d8..679dc150624 100644 --- a/projects/adrv9009zu11eg/adrv2crr_fmc/Makefile +++ b/projects/adrv9009zu11eg/adrv2crr_fmc/Makefile @@ -32,4 +32,33 @@ LIB_DEPS += xilinx/axi_adxcvr LIB_DEPS += xilinx/axi_dacfifo LIB_DEPS += xilinx/util_adxcvr +CORUNDUM ?= 0 + +ifeq ($(CORUNDUM), 1) + export BOARD := ADRV9009ZU11EG + export CPU := ZynqMP + + M_DEPS += system_constr_corundum.xdc + M_DEPS += system_bd_corundum.tcl + + M_DEPS += ../../../library/corundum/scripts/corundum_adrv9009zu11eg_cfg.tcl + M_DEPS += ../../../library/corundum/scripts/corundum.tcl + M_DEPS += ../../../library/corundum/scripts/sync_reset.tcl + + EXTERNAL_DEPS += ../../../../corundum/fpga/common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl + EXTERNAL_DEPS += ../../../../corundum/fpga/common/syn/vivado/rb_drp.tcl + EXTERNAL_DEPS += ../../../../corundum/fpga/common/syn/vivado/mqnic_rb_clk_info.tcl + EXTERNAL_DEPS += ../../../../corundum/fpga/common/syn/vivado/mqnic_ptp_clock.tcl + EXTERNAL_DEPS += ../../../../corundum/fpga/common/syn/vivado/mqnic_port.tcl + EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/syn/vivado/ptp_clock_cdc.tcl + EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/syn/vivado/ptp_td_leaf.tcl + EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/syn/vivado/ptp_td_rel2tod.tcl + EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/lib/axis/syn/vivado/sync_reset.tcl + EXTERNAL_DEPS += ../../../../corundum/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl + EXTERNAL_DEPS += ../../../../corundum/fpga/common/syn/vivado/tdma_ber_ch.tcl + + LIB_DEPS += corundum/corundum_core + LIB_DEPS += corundum/ethernet/adrv9009zu11eg +endif + include ../../scripts/project-xilinx.mk diff --git a/projects/adrv9009zu11eg/adrv2crr_fmc/README.md b/projects/adrv9009zu11eg/adrv2crr_fmc/README.md index 137a46652aa..42eb4aade8e 100644 --- a/projects/adrv9009zu11eg/adrv2crr_fmc/README.md +++ b/projects/adrv9009zu11eg/adrv2crr_fmc/README.md @@ -42,3 +42,14 @@ RX_OS_JESD_S=1 ``` Corresponding device tree: [zynqmp-adrv9009-zu11eg-revb-adrv2crr-fmc-revb-jesd204-fsm.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm64/boot/dts/xilinx/zynqmp-adrv9009-zu11eg-revb-adrv2crr-fmc-revb-jesd204-fsm.dts) + +#### Corundum Network Stack support with QSFP+ 10 Gbps + +This configuration ONLY, ADRV9009ZU11EG/ADRV2CRR-FMC, supports Corundum Network Stack with a QSFP+ ethernet connection, at a rate of 10 Gbps. All of the other parameters and configuration remain the same. To use this variant of the project and use the Corundum features, build the project using the following command: + +``` +make CORUNDUM=1 +``` +All of the binaries resulted from the build will be present in a folder called **CORUNDUM1**. + +Corresponding device tree: [zynqmp-adrv9009-zu11eg-revb-adrv2crr-fmc-revb-jesd204-fsm-100-qsfp.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm64/boot/dts/xilinx/zynqmp-adrv9009-zu11eg-revb-adrv2crr-fmc-revb-jesd204-fsm-100-qsfp.dts) \ No newline at end of file diff --git a/projects/adrv9009zu11eg/adrv2crr_fmc/system_bd.tcl b/projects/adrv9009zu11eg/adrv2crr_fmc/system_bd.tcl index 823586f7bfc..0d6510bfcff 100644 --- a/projects/adrv9009zu11eg/adrv2crr_fmc/system_bd.tcl +++ b/projects/adrv9009zu11eg/adrv2crr_fmc/system_bd.tcl @@ -7,6 +7,12 @@ source ../common/adrv9009zu11eg_bd.tcl source ../common/adrv2crr_fmc_bd.tcl source $ad_hdl_dir/projects/scripts/adi_pd.tcl +if {$ad_project_params(CORUNDUM) == "1"} { + source $ad_hdl_dir/library/corundum/scripts/corundum_adrv9009zu11eg_cfg.tcl + source $ad_hdl_dir/library/corundum/scripts/corundum.tcl + source system_bd_corundum.tcl +} + ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9 ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "$mem_init_sys_file_path/mem_init_sys.txt" ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 @@ -19,7 +25,8 @@ L=$ad_project_params(TX_JESD_L)\ S=$ad_project_params(TX_JESD_S)\ RX_OS:M=$ad_project_params(RX_OS_JESD_M)\ L=$ad_project_params(RX_OS_JESD_L)\ -S=$ad_project_params(RX_OS_JESD_S)" +S=$ad_project_params(RX_OS_JESD_S)\ +CORUNDUM=$ad_project_params(CORUNDUM)" sysid_gen_sys_init_file $sys_cstring diff --git a/projects/adrv9009zu11eg/adrv2crr_fmc/system_bd_corundum.tcl b/projects/adrv9009zu11eg/adrv2crr_fmc/system_bd_corundum.tcl new file mode 100644 index 00000000000..a073bfe9314 --- /dev/null +++ b/projects/adrv9009zu11eg/adrv2crr_fmc/system_bd_corundum.tcl @@ -0,0 +1,117 @@ +############################################################################### +## Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# Corundum NIC +create_bd_intf_port -mode Master -vlnv analog.com:interface:if_qsfp_rtl:1.0 qsfp + +create_bd_port -dir O -from 0 -to 0 -type rst qsfp_rst +create_bd_port -dir I qsfp_mgt_refclk_p +create_bd_port -dir I qsfp_mgt_refclk_n + +create_bd_port -dir O -from 3 -to 0 qsfp_led + +# collect build information +set build_date [clock seconds] +set git_hash 00000000 +catch { + set git_hash [exec git rev-parse --short=8 HEAD] +} +set tag_ver 0.0.0 + +# FW and board IDs +set fpga_id [expr 0x4738093] +set fw_id [expr 0x00000000] +set fw_ver $tag_ver +set board_vendor_id [expr 0x10ee] +set board_device_id [expr 0x9066] +set board_ver 1.0 +set release_info [expr 0x00000000] + +# General variables +set IRQ_SIZE 8 + +# Extra configurations for Corundum functionality +ad_ip_parameter sys_ps8 CONFIG.PSU__NUM_FABRIC_RESETS {2} + +# Corundum connections +connect_bd_net [get_bd_ports qsfp_led] [get_bd_pins corundum_hierarchy/ethernet_core/qsfp_led] + +ad_connect corundum_hierarchy/clk_corundum sys_ps8/pl_clk1 + +# Use Utility Logic Vector IP which takes sys_ps8/pl_resetn1 and negates it and connects +# it to corundum_hierarchy/rst_corundum, but first it's must be disconnected +# from the Corundum Reset Generator + +delete_bd_objs [get_bd_nets rst_corundum_1] + +ad_ip_instance util_vector_logic util_vector_logic_0 +ad_ip_parameter util_vector_logic_0 CONFIG.C_OPERATION {not} +ad_ip_parameter util_vector_logic_0 CONFIG.C_SIZE 1 + +ad_connect sys_ps8/pl_resetn1 util_vector_logic_0/Op1 +ad_connect corundum_hierarchy/rst_corundum util_vector_logic_0/Res + +ad_connect corundum_hierarchy/qsfp qsfp +ad_connect corundum_hierarchy/qsfp_rst qsfp_rst +ad_connect corundum_hierarchy/qsfp_mgt_refclk_p qsfp_mgt_refclk_p +ad_connect corundum_hierarchy/qsfp_mgt_refclk_n qsfp_mgt_refclk_n + +ad_ip_instance axi_interconnect smartconnect_corundum +ad_ip_parameter smartconnect_corundum CONFIG.NUM_MI 2 +ad_ip_parameter smartconnect_corundum CONFIG.NUM_SI 1 + +ad_connect smartconnect_corundum/ARESETN sys_ps8/pl_resetn1 +ad_connect smartconnect_corundum/S00_ARESETN sys_ps8/pl_resetn1 +ad_connect smartconnect_corundum/M00_ARESETN sys_ps8/pl_resetn1 +ad_connect smartconnect_corundum/M01_ARESETN sys_ps8/pl_resetn1 + +ad_connect smartconnect_corundum/ACLK sys_ps8/pl_clk1 +ad_connect smartconnect_corundum/S00_ACLK sys_ps8/pl_clk1 +ad_connect smartconnect_corundum/M00_ACLK sys_ps8/pl_clk1 +ad_connect smartconnect_corundum/M01_ACLK sys_ps8/pl_clk1 + +ad_connect smartconnect_corundum/M00_AXI corundum_hierarchy/s_axil_corundum + +ad_ip_parameter sys_ps8 CONFIG.PSU__USE__M_AXI_GP0 1 +ad_ip_parameter sys_ps8 CONFIG.PSU__MAXIGP0__DATA_WIDTH 32 +ad_connect smartconnect_corundum/S00_AXI sys_ps8/M_AXI_HPM0_FPD +ad_connect sys_ps8/maxihpm0_fpd_aclk sys_200m_clk + +ad_connect corundum_rstgen/slowest_sync_clk sys_200m_clk +ad_connect corundum_rstgen/ext_reset_in sys_ps8/pl_resetn0 +ad_connect corundum_rstgen/peripheral_aresetn corundum_rstn + +ad_ip_parameter sys_ps8 CONFIG.PSU__USE__S_AXI_GP5 1 +ad_connect sys_200m_clk sys_ps8/saxihp3_fpd_aclk + +assign_bd_address -offset 0xA000_0000 [get_bd_addr_segs \ + corundum_hierarchy/corundum_core/s_axil_ctrl/Reg +] -target_address_space sys_ps8/Data + +ad_ip_instance util_reduced_logic util_reduced_logic_0 +ad_ip_parameter util_reduced_logic_0 CONFIG.C_OPERATION {or} +ad_ip_parameter util_reduced_logic_0 CONFIG.C_SIZE $IRQ_SIZE + +ad_connect util_reduced_logic_0/Op1 corundum_hierarchy/irq + +ad_cpu_interrupt ps-4 mb-4 util_reduced_logic_0/Res + +ad_mem_hpc0_interconnect sys_200m_clk corundum_hierarchy/m_axi + +assign_bd_address [get_bd_addr_segs { \ + sys_ps8/SAXIGP0/HPC0_LPS_OCM \ + sys_ps8/SAXIGP0/HPC0_QSPI \ + sys_ps8/SAXIGP0/HPC0_DDR_LOW \ + sys_ps8/SAXIGP0/HPC0_DDR_HIGH \ +}] + +create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_port + +ad_ip_instance axi_iic axi_iic +ad_connect iic_port axi_iic/iic + +ad_cpu_interconnect 0x43000000 axi_iic + +ad_cpu_interrupt ps-5 mb-14 axi_iic/iic2intc_irpt diff --git a/projects/adrv9009zu11eg/adrv2crr_fmc/system_constr_corundum.xdc b/projects/adrv9009zu11eg/adrv2crr_fmc/system_constr_corundum.xdc new file mode 100644 index 00000000000..bba25a6a465 --- /dev/null +++ b/projects/adrv9009zu11eg/adrv2crr_fmc/system_constr_corundum.xdc @@ -0,0 +1,41 @@ +############################################################################### +## Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set_property -dict {PACKAGE_PIN AU11 IOSTANDARD LVCMOS18 } [get_ports qsfp_resetl ] ; +set_property -dict {PACKAGE_PIN AL12 IOSTANDARD LVCMOS18 PULLUP true } [get_ports qsfp_modprsl ] ; +set_property -dict {PACKAGE_PIN AW14 IOSTANDARD LVCMOS18 PULLUP true } [get_ports qsfp_intl ] ; +set_property -dict {PACKAGE_PIN AV11 IOSTANDARD LVCMOS18 } [get_ports qsfp_lpmode ] ; + + +set_property PACKAGE_PIN AD2 [get_ports qsfp_rx_p[0] ] ; +set_property PACKAGE_PIN AD1 [get_ports qsfp_rx_n[0] ] ; + +set_property PACKAGE_PIN AC4 [get_ports qsfp_rx_p[1] ] ; +set_property PACKAGE_PIN AC3 [get_ports qsfp_rx_n[1] ] ; + +set_property PACKAGE_PIN AB2 [get_ports qsfp_rx_p[2] ] ; +set_property PACKAGE_PIN AB1 [get_ports qsfp_rx_n[2] ] ; + +set_property PACKAGE_PIN AA4 [get_ports qsfp_rx_p[3] ] ; +set_property PACKAGE_PIN AA3 [get_ports qsfp_rx_n[3] ] ; + +set_property PACKAGE_PIN AD6 [get_ports qsfp_tx_p[0] ] ; +set_property PACKAGE_PIN AD5 [get_ports qsfp_tx_n[0] ] ; + +set_property PACKAGE_PIN AC8 [get_ports qsfp_tx_p[1] ] ; +set_property PACKAGE_PIN AC7 [get_ports qsfp_tx_n[1] ] ; + +set_property PACKAGE_PIN AB6 [get_ports qsfp_tx_p[2] ] ; +set_property PACKAGE_PIN AB5 [get_ports qsfp_tx_n[2] ] ; + +set_property PACKAGE_PIN AA8 [get_ports qsfp_tx_p[3] ] ; +set_property PACKAGE_PIN AA7 [get_ports qsfp_tx_n[3] ] ; + +set_property PACKAGE_PIN AD10 [get_ports qsfp_mgt_refclk_p ] ; +set_property PACKAGE_PIN AD9 [get_ports qsfp_mgt_refclk_n ] ; + + +# 156.25 MHz MGT reference clock +create_clock -period 6.400 -name gt_ref_clk [get_ports qsfp_mgt_refclk_p] diff --git a/projects/adrv9009zu11eg/adrv2crr_fmc/system_project.tcl b/projects/adrv9009zu11eg/adrv2crr_fmc/system_project.tcl index 41ee61720d3..d8bf6ce4a17 100644 --- a/projects/adrv9009zu11eg/adrv2crr_fmc/system_project.tcl +++ b/projects/adrv9009zu11eg/adrv2crr_fmc/system_project.tcl @@ -34,13 +34,35 @@ adi_project_create adrv9009zu11eg 0 [list \ RX_OS_JESD_M [get_env_param RX_OS_JESD_M 4] \ RX_OS_JESD_L [get_env_param RX_OS_JESD_L 4] \ RX_OS_JESD_S [get_env_param RX_OS_JESD_S 1] \ + CORUNDUM [get_env_param CORUNDUM 1] \ ] "xczu11eg-ffvf1517-2-i" adi_project_files adrv9009zu11eg [list \ - "system_top.v" \ "../common/adrv9009zu11eg_spi.v" \ "../common/adrv9009zu11eg_constr.xdc" \ "../common/adrv2crr_fmc_constr.xdc" \ "$ad_hdl_dir/library/common/ad_iobuf.v" ] +if {[get_env_param CORUNDUM 0] == 1} { + adi_project_files adrv9009zu11eg [list \ + "system_constr_corundum.xdc" \ + "system_top_corundum.v" \ + "$ad_hdl_dir/../corundum/fpga/common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl" \ + "$ad_hdl_dir/../corundum/fpga/common/syn/vivado/rb_drp.tcl" \ + "$ad_hdl_dir/../corundum/fpga/common/syn/vivado/mqnic_rb_clk_info.tcl" \ + "$ad_hdl_dir/../corundum/fpga/common/syn/vivado/mqnic_ptp_clock.tcl" \ + "$ad_hdl_dir/../corundum/fpga/common/syn/vivado/mqnic_port.tcl" \ + "$ad_hdl_dir/../corundum/fpga/lib/eth/syn/vivado/ptp_clock_cdc.tcl" \ + "$ad_hdl_dir/../corundum/fpga/lib/eth/syn/vivado/ptp_td_leaf.tcl" \ + "$ad_hdl_dir/../corundum/fpga/lib/eth/syn/vivado/ptp_td_rel2tod.tcl" \ + "$ad_hdl_dir/../corundum/fpga/lib/eth/lib/axis/syn/vivado/sync_reset.tcl" \ + "$ad_hdl_dir/../corundum/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl" \ + "$ad_hdl_dir/../corundum/fpga/common/syn/vivado/tdma_ber_ch.tcl" + ] +} else { + adi_project_files adrv9009zu11eg [list \ + "system_top.v" \ + ] +} + adi_project_run adrv9009zu11eg diff --git a/projects/adrv9009zu11eg/adrv2crr_fmc/system_top_corundum.v b/projects/adrv9009zu11eg/adrv2crr_fmc/system_top_corundum.v new file mode 100644 index 00000000000..534b7a037a8 --- /dev/null +++ b/projects/adrv9009zu11eg/adrv2crr_fmc/system_top_corundum.v @@ -0,0 +1,595 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + input fan_tach, + output fan_pwm, + input i2s_sdata_in, + output i2s_sdata_out, + output i2s_mclk, + output i2s_bclk, + output i2s_lrclk, + inout pmod0_d0, + inout pmod0_d1, + inout pmod0_d2, + inout pmod0_d3, + inout pmod0_d4, + inout pmod0_d5, + inout pmod0_d6, + inout pmod0_d7, + output gpio_0_exp_n, //CS_HMC7044 + output gpio_0_exp_p, //MOSI + input gpio_1_exp_n, //MISO + output gpio_1_exp_p, //SCK + output gpio_2_exp_n, //CS_AD9545 + inout gpio_3_exp_n, //RESET_HMC7044 + inout gpio_3_exp_p, //RESET_AD9545 + inout gpio_4_exp_n, //VCXO_SELECT + inout dip_gpio_0, + inout dip_gpio_1, + inout dip_gpio_2, + inout dip_gpio_3, + inout pb_gpio_0, + inout pb_gpio_1, + inout pb_gpio_2, + inout pb_gpio_3, + output resetb_ad9545, + output hmc7044_car_reset, + inout hmc7044_car_gpio_1, + inout hmc7044_car_gpio_2, + inout hmc7044_car_gpio_3, + inout hmc7044_car_gpio_4, + output spi_csn_hmc7044_car, + + inout i2c0_scl, + inout i2c0_sda, + + inout i2c1_scl, + inout i2c1_sda, + + input oscout_p, + input oscout_n, + + input ref_clk_a_p, + input ref_clk_a_n, + input core_clk_a_p, + input core_clk_a_n, + input [ 3:0] rx_data_a_p, + input [ 3:0] rx_data_a_n, + output [ 3:0] tx_data_a_p, + output [ 3:0] tx_data_a_n, + + output rx_sync_a_p, + output rx_sync_a_n, + output rx_os_sync_a_p, + output rx_os_sync_a_n, + input tx_sync_a_p, + input tx_sync_a_n, + input tx_sync_a_1_p, + input tx_sync_a_1_n, + input sysref_a_p, + input sysref_a_n, + + inout adrv9009_tx1_enable_a, + inout adrv9009_tx2_enable_a, + inout adrv9009_rx1_enable_a, + inout adrv9009_rx2_enable_a, + inout adrv9009_test_a, + inout adrv9009_reset_b_a, + inout adrv9009_gpint_a, + + inout adrv9009_gpio_00_a, + inout adrv9009_gpio_01_a, + inout adrv9009_gpio_02_a, + inout adrv9009_gpio_03_a, + inout adrv9009_gpio_04_a, + inout adrv9009_gpio_05_a, + inout adrv9009_gpio_06_a, + inout adrv9009_gpio_07_a, + inout adrv9009_gpio_15_a, + inout adrv9009_gpio_08_a, + inout adrv9009_gpio_09_a, + inout adrv9009_gpio_10_a, + inout adrv9009_gpio_11_a, + inout adrv9009_gpio_12_a, + inout adrv9009_gpio_14_a, + inout adrv9009_gpio_13_a, + inout adrv9009_gpio_17_a, + inout adrv9009_gpio_16_a, + inout adrv9009_gpio_18_a, + + input ref_clk_b_p, + input ref_clk_b_n, + input core_clk_b_p, + input core_clk_b_n, + input [ 3:0] rx_data_b_p, + input [ 3:0] rx_data_b_n, + output [ 3:0] tx_data_b_p, + output [ 3:0] tx_data_b_n, + + output rx_sync_b_p, + output rx_sync_b_n, + output rx_os_sync_b_p, + output rx_os_sync_b_n, + input tx_sync_b_p, + input tx_sync_b_n, + input tx_sync_b_1_p, + input tx_sync_b_1_n, + input sysref_b_p, + input sysref_b_n, + + inout adrv9009_tx1_enable_b, + inout adrv9009_tx2_enable_b, + inout adrv9009_rx1_enable_b, + inout adrv9009_rx2_enable_b, + inout adrv9009_test_b, + inout adrv9009_reset_b_b, + inout adrv9009_gpint_b, + + inout adrv9009_gpio_00_b, + inout adrv9009_gpio_01_b, + inout adrv9009_gpio_02_b, + inout adrv9009_gpio_03_b, + inout adrv9009_gpio_04_b, + inout adrv9009_gpio_05_b, + inout adrv9009_gpio_06_b, + inout adrv9009_gpio_07_b, + inout adrv9009_gpio_15_b, + inout adrv9009_gpio_08_b, + inout adrv9009_gpio_09_b, + inout adrv9009_gpio_10_b, + inout adrv9009_gpio_11_b, + inout adrv9009_gpio_12_b, + inout adrv9009_gpio_14_b, + inout adrv9009_gpio_13_b, + inout adrv9009_gpio_17_b, + inout adrv9009_gpio_16_b, + inout adrv9009_gpio_18_b, + + output hmc7044_reset, + output hmc7044_sync, + inout hmc7044_gpio_1, + inout hmc7044_gpio_2, + inout hmc7044_gpio_3, + inout hmc7044_gpio_4, + + output spi_csn_adrv9009_a, + output spi_csn_adrv9009_b, + output spi_csn_hmc7044, + + input ddr4_ref_1_clk_n, + input ddr4_ref_1_clk_p, + + output ddr4_rtl_1_act_n, + output [16:0] ddr4_rtl_1_adr, + output [1:0] ddr4_rtl_1_ba, + output [0:0] ddr4_rtl_1_bg, + output [0:0] ddr4_rtl_1_ck_c, + output [0:0] ddr4_rtl_1_ck_t, + output [0:0] ddr4_rtl_1_cke, + output [0:0] ddr4_rtl_1_cs_n, + inout [3:0] ddr4_rtl_1_dm_n, + inout [31:0] ddr4_rtl_1_dq, + inout [3:0] ddr4_rtl_1_dqs_c, + inout [3:0] ddr4_rtl_1_dqs_t, + output [0:0] ddr4_rtl_1_odt, + output ddr4_rtl_1_reset_n, + output ddr4_rtl_1_par, + input ddr4_rtl_1_alert_n, + output spi_clk, + inout spi_sdio, + input spi_miso, + + // QSPF+ signals, needed for Corundum + + output [3:0] qsfp_tx_p, + output [3:0] qsfp_tx_n, + input [3:0] qsfp_rx_p, + input [3:0] qsfp_rx_n, + + // GT REF CLK + input qsfp_mgt_refclk_p, + input qsfp_mgt_refclk_n, + + /* + * Ethernet: QSFP28 + */ + output wire qsfp_resetl, + input wire qsfp_modprsl, + input wire qsfp_intl, + output wire qsfp_lpmode, + + // previously named qsfp_led + output led_gpio_0, + output led_gpio_1, + output led_gpio_2, + output led_gpio_3 +); + + // internal signals + + wire [94:0] gpio_i; + wire [94:0] gpio_o; + wire [94:0] gpio_t; + + wire [2:0] spi_csn; + + wire ref_clk_a; + wire core_clk_a; + wire core_clk_a_ds; + wire rx_sync_rx; + wire tx_sync_a; + wire sysref_a; + wire ref_clk_b; + wire core_clk_b; + wire core_clk_b_ds; + wire rx_sync_obs; + wire rx_os_sync_b; + wire tx_sync_b; + wire sysref_b; + wire tx_sync; + wire spi_mosi; + wire spi0_miso; + wire spi_miso_s; + + reg [7:0] spi_3_to_8_csn; + + always @(*) begin + case (spi_csn) + 3'h0: spi_3_to_8_csn = 8'b11111110; + 3'h1: spi_3_to_8_csn = 8'b11111101; + 3'h2: spi_3_to_8_csn = 8'b11111011; + 3'h3: spi_3_to_8_csn = 8'b11110111; + 3'h4: spi_3_to_8_csn = 8'b11101111; + 3'h5: spi_3_to_8_csn = 8'b11011111; + 3'h6: spi_3_to_8_csn = 8'b10111111; + default: spi_3_to_8_csn = 8'b11111111; + endcase + end + + assign spi_csn_adrv9009_a = spi_3_to_8_csn[0]; + assign spi_csn_adrv9009_b = spi_3_to_8_csn[1]; + assign spi_csn_hmc7044 = spi_3_to_8_csn[2]; + assign spi_csn_hmc7044_car = spi_3_to_8_csn[3]; + assign gpio_0_exp_n = spi_3_to_8_csn[4]; + assign gpio_1_exp_p = spi_clk; + assign gpio_0_exp_p = spi_mosi; + assign spi_miso_s = ((spi_3_to_8_csn[4] == 1'b0) | (spi_3_to_8_csn[5] == 1'b0))? gpio_1_exp_n : spi_miso; + assign gpio_2_exp_n = spi_3_to_8_csn[5]; + + adrv9009zu11eg_spi i_spi ( + .spi_csn(spi_3_to_8_csn), + .spi_clk(spi_clk), + .spi_mosi(spi_mosi), + .spi_miso_i(spi_miso_s), + .spi_miso_o(spi0_miso), + .spi_sdio(spi_sdio)); + + assign tx_sync = tx_sync_a & tx_sync_b; + + assign gpio_i[94:93] = gpio_o[94:93]; + assign gpio_i[31:28] = gpio_o[31:28]; + assign gpio_i[21:20] = gpio_o[21:20]; + + ad_iobuf #( + .DATA_WIDTH(61) + ) i_iobuf ( + .dio_t ({gpio_t[92:32]}), + .dio_i ({gpio_o[92:32]}), + .dio_o ({gpio_i[92:32]}), + .dio_p ({ + gpio_4_exp_n, // 92 + gpio_3_exp_n, // 91 + gpio_3_exp_p, // 90 + hmc7044_gpio_4, // 89 + hmc7044_gpio_3, // 88 + hmc7044_gpio_1, // 87 + hmc7044_gpio_2, // 86 + hmc7044_sync, // 85 + hmc7044_reset, // 84 + adrv9009_tx2_enable_b, // 83 + adrv9009_tx1_enable_b, // 82 + adrv9009_rx2_enable_b, // 81 + adrv9009_rx1_enable_b, // 80 + adrv9009_test_b, // 79 + adrv9009_reset_b_b, // 78 + adrv9009_gpint_b, // 77 + adrv9009_gpio_18_b, // 77 + adrv9009_gpio_17_b, // 75 + adrv9009_gpio_16_b, // 74 + adrv9009_gpio_15_b, // 73 + adrv9009_gpio_14_b, // 72 + adrv9009_gpio_13_b, // 71 + adrv9009_gpio_12_b, // 70 + adrv9009_gpio_11_b, // 69 + adrv9009_gpio_10_b, // 68 + adrv9009_gpio_09_b, // 67 + adrv9009_gpio_08_b, // 66 + adrv9009_gpio_07_b, // 65 + adrv9009_gpio_06_b, // 64 + adrv9009_gpio_05_b, // 63 + adrv9009_gpio_04_b, // 62 + adrv9009_gpio_03_b, // 61 + adrv9009_gpio_02_b, // 60 + adrv9009_gpio_01_b, // 58 + adrv9009_gpio_00_b, // 58 + adrv9009_tx2_enable_a, // 57 + adrv9009_tx1_enable_a, // 56 + adrv9009_rx2_enable_a, // 55 + adrv9009_rx1_enable_a, // 54 + adrv9009_test_a, // 53 + adrv9009_reset_b_a, // 52 + adrv9009_gpint_a, // 51 + adrv9009_gpio_18_a, // 50 + adrv9009_gpio_17_a, // 49 + adrv9009_gpio_16_a, // 48 + adrv9009_gpio_15_a, // 47 + adrv9009_gpio_14_a, // 46 + adrv9009_gpio_13_a, // 45 + adrv9009_gpio_12_a, // 44 + adrv9009_gpio_11_a, // 43 + adrv9009_gpio_10_a, // 42 + adrv9009_gpio_09_a, // 41 + adrv9009_gpio_08_a, // 40 + adrv9009_gpio_07_a, // 39 + adrv9009_gpio_06_a, // 38 + adrv9009_gpio_05_a, // 37 + adrv9009_gpio_04_a, // 36 + adrv9009_gpio_03_a, // 35 + adrv9009_gpio_02_a, // 34 + adrv9009_gpio_01_a, // 33 + adrv9009_gpio_00_a})); // 32 + + ad_iobuf #( + .DATA_WIDTH(6) + ) i_carrier_iobuf_0 ( + .dio_t ({gpio_t[27:22]}), + .dio_i ({gpio_o[27:22]}), + .dio_o ({gpio_i[27:22]}), + .dio_p ({ + hmc7044_car_gpio_4, // 27 + hmc7044_car_gpio_3, // 26 + hmc7044_car_gpio_2, // 25 + hmc7044_car_gpio_1, // 24 + hmc7044_car_reset, // 23 + resetb_ad9545})); // 22 + + ad_iobuf #( + .DATA_WIDTH(20) + ) i_carrier_iobuf_1 ( + .dio_t ({gpio_t[19:0]}), + .dio_i ({gpio_o[19:0]}), + .dio_o ({gpio_i[19:0]}), + .dio_p ({ + pmod0_d7, // 19 + pmod0_d6, // 18 + pmod0_d5, // 17 + pmod0_d4, // 16 + pmod0_d3, // 15 + pmod0_d2, // 14 + pmod0_d1, // 13 + pmod0_d0, // 12 + 0'b0, // 11 + 0'b0, // 10 + 0'b0, // 9 + 0'b0, // 8 + dip_gpio_3, // 7 + dip_gpio_2, // 6 + dip_gpio_1, // 5 + dip_gpio_0, // 4 + pb_gpio_3, // 3 + pb_gpio_2, // 2 + pb_gpio_1, // 1 + pb_gpio_0})); // 0 + + //QSFP + + wire qsfp_gtpowergood; + wire qsfp_rst; + wire ptp_rst; + wire [3:0] qsfp_led; + + assign ptp_rst = qsfp_rst; + assign {led_gpio_0, led_gpio_1, led_gpio_2, led_gpio_3} = qsfp_led[3:0]; + + IBUFDS_GTE4 i_ibufds_ref_clk_1 ( + .CEB (1'd0), + .I (ref_clk_a_p), + .IB (ref_clk_a_n), + .O (ref_clk_a), + .ODIV2 ()); + + IBUFDS_GTE4 i_ibufds_ref_clk_2 ( + .CEB (1'd0), + .I (ref_clk_b_p), + .IB (ref_clk_b_n), + .O (ref_clk_b), + .ODIV2 ()); + + IBUFDS i_ibufds_sysref_1 ( + .I (sysref_a_p), + .IB (sysref_a_n), + .O (sysref_a)); + + IBUFDS i_ibufds_sysref_2 ( + .I (sysref_b_p), + .IB (sysref_b_n), + .O (sysref_b)); + + IBUFDS i_rx_clk_ibuf_1 ( + .I (core_clk_a_p), + .IB (core_clk_a_n), + .O (core_clk_a_ds)); + + BUFG i_clk_bufg_1 ( + .I (core_clk_a_ds), + .O (core_clk_a)); + + IBUFDS i_rx_clk_ibuf_2 ( + .I (core_clk_b_p), + .IB (core_clk_b_n), + .O (core_clk_b_ds)); + + BUFG i_clk_bufg_2 ( + .I (core_clk_b_ds), + .O (core_clk_b)); + + IBUFDS i_ibufds_tx_sync_1 ( + .I (tx_sync_a_p), + .IB (tx_sync_a_n), + .O (tx_sync_a)); + + IBUFDS i_ibufds_tx_sync_2 ( + .I (tx_sync_b_p), + .IB (tx_sync_b_n), + .O (tx_sync_b)); + + OBUFDS i_obufds_rx_sync_1 ( + .I (rx_sync_rx), + .O (rx_sync_a_p), + .OB (rx_sync_a_n)); + + OBUFDS i_obufds_rx_os_sync_1 ( + .I (rx_sync_obs), + .O (rx_os_sync_a_p), + .OB (rx_os_sync_a_n)); + + OBUFDS i_obufds_rx_sync_2 ( + .I (rx_sync_rx), + .O (rx_sync_b_p), + .OB (rx_sync_b_n)); + + OBUFDS i_obufds_rx_os_sync_2 ( + .I (rx_sync_obs), + .O (rx_os_sync_b_p), + .OB (rx_os_sync_b_n)); + + system_wrapper i_system_wrapper ( + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .ddr4_rtl_1_act_n(ddr4_rtl_1_act_n), + .ddr4_rtl_1_adr(ddr4_rtl_1_adr), + .ddr4_rtl_1_ba(ddr4_rtl_1_ba), + .ddr4_rtl_1_bg(ddr4_rtl_1_bg), + .ddr4_rtl_1_ck_c(ddr4_rtl_1_ck_c), + .ddr4_rtl_1_ck_t(ddr4_rtl_1_ck_t), + .ddr4_rtl_1_cke(ddr4_rtl_1_cke), + .ddr4_rtl_1_cs_n(ddr4_rtl_1_cs_n), + .ddr4_rtl_1_dm_n(ddr4_rtl_1_dm_n), + .ddr4_rtl_1_dq(ddr4_rtl_1_dq), + .ddr4_rtl_1_dqs_c(ddr4_rtl_1_dqs_c), + .ddr4_rtl_1_dqs_t(ddr4_rtl_1_dqs_t), + .ddr4_rtl_1_odt(ddr4_rtl_1_odt), + .ddr4_rtl_1_reset_n(ddr4_rtl_1_reset_n), + .sys_reset(1'b0), + .ddr4_ref_1_clk_n(ddr4_ref_1_clk_n), + .ddr4_ref_1_clk_p(ddr4_ref_1_clk_p), + .core_clk_a(core_clk_a), + .core_clk_b(core_clk_b), + .ref_clk_a(ref_clk_a), + .ref_clk_b(ref_clk_b), + // QSFP + .qsfp_rst (qsfp_rst), + .qsfp_gtpowergood (qsfp_gtpowergood), + .qsfp_intl (qsfp_intl), + .qsfp_lpmode (qsfp_lpmode), + .qsfp_mgt_refclk_p (qsfp_mgt_refclk_p), + .qsfp_mgt_refclk_n (qsfp_mgt_refclk_n), + .qsfp_modprsl (qsfp_modprsl), + .qsfp_resetl (qsfp_resetl), + .qsfp_rx_n (qsfp_rx_n), + .qsfp_rx_p (qsfp_rx_p), + .qsfp_tx_n (qsfp_tx_n), + .qsfp_tx_p (qsfp_tx_p), + .qsfp_led (qsfp_led), + // + .rx_data_0_n (rx_data_a_n[0]), + .rx_data_0_p (rx_data_a_p[0]), + .rx_data_1_n (rx_data_a_n[1]), + .rx_data_1_p (rx_data_a_p[1]), + .rx_data_2_n (rx_data_a_n[2]), + .rx_data_2_p (rx_data_a_p[2]), + .rx_data_3_n (rx_data_a_n[3]), + .rx_data_3_p (rx_data_a_p[3]), + .rx_data_4_n (rx_data_b_n[0]), + .rx_data_4_p (rx_data_b_p[0]), + .rx_data_5_n (rx_data_b_n[1]), + .rx_data_5_p (rx_data_b_p[1]), + .rx_data_6_n (rx_data_b_n[2]), + .rx_data_6_p (rx_data_b_p[2]), + .rx_data_7_n (rx_data_b_n[3]), + .rx_data_7_p (rx_data_b_p[3]), + .rx_sync_0 (rx_sync_rx), + .rx_sync_4 (rx_sync_obs), + .rx_sysref_0 (sysref_b), + .rx_sysref_4 (sysref_a), + .tx_data_0_n (tx_data_a_n[0]), + .tx_data_0_p (tx_data_a_p[0]), + .tx_data_1_n (tx_data_a_n[1]), + .tx_data_1_p (tx_data_a_p[1]), + .tx_data_2_n (tx_data_a_n[2]), + .tx_data_2_p (tx_data_a_p[2]), + .tx_data_3_n (tx_data_a_n[3]), + .tx_data_3_p (tx_data_a_p[3]), + .tx_data_4_n (tx_data_b_n[0]), + .tx_data_4_p (tx_data_b_p[0]), + .tx_data_5_n (tx_data_b_n[1]), + .tx_data_5_p (tx_data_b_p[1]), + .tx_data_6_n (tx_data_b_n[2]), + .tx_data_6_p (tx_data_b_p[2]), + .tx_data_7_n (tx_data_b_n[3]), + .tx_data_7_p (tx_data_b_p[3]), + .tx_sync_0 (tx_sync), + .tx_sysref_0 (sysref_a), + .dac_fifo_bypass(gpio_o[90]), + .iic_port_scl_io(i2c1_scl), + .iic_port_sda_io(i2c1_sda), + .i2s_bclk(i2s_bclk), + .i2s_lrclk(i2s_lrclk), + .i2s_mclk(i2s_mclk), + .i2s_sdata_in(i2s_sdata_in), + .i2s_sdata_out(i2s_sdata_out), + .axi_fan_pwm_o(fan_pwm), + .axi_fan_tacho_i(fan_tach), + .spi0_csn(spi_csn), + .spi0_miso(spi0_miso), + .spi0_mosi(spi_mosi), + .spi0_sclk(spi_clk)); + +endmodule diff --git a/projects/adrv9009zu11eg/common/adrv9009zu11eg_bd.tcl b/projects/adrv9009zu11eg/common/adrv9009zu11eg_bd.tcl index b15abf2a51c..56a0081c24b 100644 --- a/projects/adrv9009zu11eg/common/adrv9009zu11eg_bd.tcl +++ b/projects/adrv9009zu11eg/common/adrv9009zu11eg_bd.tcl @@ -319,7 +319,7 @@ ad_ip_parameter axi_adrv9009_som_rx_dma CONFIG.AXI_SLICE_SRC 1 ad_ip_parameter axi_adrv9009_som_rx_dma CONFIG.AXI_SLICE_DEST 1 ad_ip_parameter axi_adrv9009_som_rx_dma CONFIG.DMA_2D_TRANSFER 0 ad_ip_parameter axi_adrv9009_som_rx_dma CONFIG.FIFO_SIZE 32 -ad_ip_parameter axi_adrv9009_som_rx_dma MAX_BYTES_PER_BURST 256 +ad_ip_parameter axi_adrv9009_som_rx_dma CONFIG.MAX_BYTES_PER_BURST 256 ad_ip_parameter axi_adrv9009_som_rx_dma CONFIG.DMA_DATA_WIDTH_SRC $adc_dma_data_width ad_ip_parameter axi_adrv9009_som_rx_dma CONFIG.DMA_DATA_WIDTH_DEST 128 ad_ip_parameter axi_adrv9009_som_rx_dma CONFIG.CACHE_COHERENT 1 @@ -355,7 +355,7 @@ ad_ip_parameter axi_adrv9009_som_obs_dma CONFIG.AXI_SLICE_SRC 1 ad_ip_parameter axi_adrv9009_som_obs_dma CONFIG.AXI_SLICE_DEST 1 ad_ip_parameter axi_adrv9009_som_obs_dma CONFIG.DMA_2D_TRANSFER 0 ad_ip_parameter axi_adrv9009_som_obs_dma CONFIG.FIFO_SIZE 32 -ad_ip_parameter axi_adrv9009_som_obs_dma MAX_BYTES_PER_BURST 256 +ad_ip_parameter axi_adrv9009_som_obs_dma CONFIG.MAX_BYTES_PER_BURST 256 ad_ip_parameter axi_adrv9009_som_obs_dma CONFIG.DMA_DATA_WIDTH_SRC [expr 32*$RX_OS_NUM_OF_LANES] ad_ip_parameter axi_adrv9009_som_obs_dma CONFIG.DMA_DATA_WIDTH_DEST 128 ad_ip_parameter axi_adrv9009_som_obs_dma CONFIG.CACHE_COHERENT 1