From 2ad53ec966aef65e7d2ff28c772db49fd6b084e2 Mon Sep 17 00:00:00 2001 From: eminc Date: Mon, 1 Dec 2025 22:04:06 +0300 Subject: [PATCH] library/axi_ad9361/xilinx: Fix frame delineation error check The rx_error_r1 and rx_error_r2 checks were only using rx_frame_s (2 bits) instead of the concatenated {rx_frame_s, rx_frame} (4 bits) to properly validate frame alignment across consecutive clock cycles. Signed-off-by: Emin Cetin eeminceetin@gmail.com Signed-off-by: eminc --- library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v b/library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v index 89b8854d308..ec8598229e5 100644 --- a/library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v +++ b/library/axi_ad9361/xilinx/axi_ad9361_lvds_if.v @@ -220,9 +220,9 @@ module axi_ad9361_lvds_if #( reg rx_error_r2 = 'd0; always @(posedge l_clk) begin - rx_error_r1 <= ~((rx_frame_s == 4'b1100) || (rx_frame_s == 4'b0011)); - rx_error_r2 <= ~((rx_frame_s == 4'b1111) || (rx_frame_s == 4'b1100) || - (rx_frame_s == 4'b0000) || (rx_frame_s == 4'b0011)); + rx_error_r1 <= ~(({rx_frame_s, rx_frame} == 4'b1100) || ({rx_frame_s, rx_frame} == 4'b0011)); + rx_error_r2 <= ~(({rx_frame_s, rx_frame} == 4'b1111) || ({rx_frame_s, rx_frame} == 4'b1100) || + ({rx_frame_s, rx_frame} == 4'b0000) || ({rx_frame_s, rx_frame} == 4'b0011)); end always @(posedge l_clk) begin