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projects/adrv9009zu11eg: Corundum Integration
- Corundum support is ONLY available for the ADRV9009ZU11EG/ADRV2CRR_FMC variant of the project - Created a new constraints file, alongside with a new top file, for routing the QSFP signals - Added a separate bd.tcl script, to handle the necessary exports, configurations and connections for Corundum features - Added a new build mode for Corundum, by using the new parameter called CORUNDUM (make CORUNDUM=1) - All the Corundum dependecies are contraint by this variable; if the variable it's not specied when using make, the default variant of the project will be built - IMPORTANT: this implementaion of the Corundum IP, bypasses the Corundum Reset Generator (as seen in the other implementations), connects the Corundum Hierarchy reset and clock directly to the PS Signed-off-by: Cristian Mihai Popa <cristianmihai.popa@analog.com>
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‎projects/adrv9009zu11eg/adrv2crr_fmc/Makefile‎

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Original file line numberDiff line numberDiff line change
@@ -32,4 +32,33 @@ LIB_DEPS += xilinx/axi_adxcvr
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LIB_DEPS += xilinx/axi_dacfifo
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LIB_DEPS += xilinx/util_adxcvr
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CORUNDUM ?= 0
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ifeq ($(CORUNDUM), 1)
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export BOARD := ADRV9009ZU11EG
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export CPU := ZynqMP
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M_DEPS += system_constr_corundum.xdc
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M_DEPS += system_bd_corundum.tcl
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M_DEPS += $(ADI_HDL_DIR)/library/corundum/scripts/corundum_adrv9009zu11eg_cfg.tcl
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M_DEPS += $(ADI_HDL_DIR)/library/corundum/scripts/corundum.tcl
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M_DEPS += $(ADI_HDL_DIR)/library/corundum/scripts/sync_reset.tcl
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EXTERNAL_DEPS += $(ADI_HDL_DIR)/../corundum/fpga/common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl
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EXTERNAL_DEPS += $(ADI_HDL_DIR)/../corundum/fpga/common/syn/vivado/rb_drp.tcl
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EXTERNAL_DEPS += $(ADI_HDL_DIR)/../corundum/fpga/common/syn/vivado/mqnic_rb_clk_info.tcl
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EXTERNAL_DEPS += $(ADI_HDL_DIR)/../corundum/fpga/common/syn/vivado/mqnic_ptp_clock.tcl
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EXTERNAL_DEPS += $(ADI_HDL_DIR)/../corundum/fpga/common/syn/vivado/mqnic_port.tcl
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EXTERNAL_DEPS += $(ADI_HDL_DIR)/../corundum/fpga/lib/eth/syn/vivado/ptp_clock_cdc.tcl
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EXTERNAL_DEPS += $(ADI_HDL_DIR)/../corundum/fpga/lib/eth/syn/vivado/ptp_td_leaf.tcl
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EXTERNAL_DEPS += $(ADI_HDL_DIR)/../corundum/fpga/lib/eth/syn/vivado/ptp_td_rel2tod.tcl
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EXTERNAL_DEPS += $(ADI_HDL_DIR)/../corundum/fpga/lib/eth/lib/axis/syn/vivado/sync_reset.tcl
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EXTERNAL_DEPS += $(ADI_HDL_DIR)/../corundum/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl
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EXTERNAL_DEPS += $(ADI_HDL_DIR)/../corundum/fpga/common/syn/vivado/tdma_ber_ch.tcl
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LIB_DEPS += corundum/corundum_core
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LIB_DEPS += corundum/ethernet/adrv9009zu11eg
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endif
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include ../../scripts/project-xilinx.mk

‎projects/adrv9009zu11eg/adrv2crr_fmc/system_bd.tcl‎

Lines changed: 9 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,13 @@ source ../common/adrv9009zu11eg_bd.tcl
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source ../common/adrv2crr_fmc_bd.tcl
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source $ad_hdl_dir/projects/scripts/adi_pd.tcl
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if {[get_env_param CORUNDUM 0] == 1} {
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source $ad_hdl_dir/library/corundum/scripts/corundum_adrv9009zu11eg_cfg.tcl
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source $ad_hdl_dir/library/corundum/scripts/corundum.tcl
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source system_bd_corundum.tcl
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}
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ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9
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ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "$mem_init_sys_file_path/mem_init_sys.txt"
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ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9
@@ -19,7 +26,8 @@ L=$ad_project_params(TX_JESD_L)\
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S=$ad_project_params(TX_JESD_S)\
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RX_OS:M=$ad_project_params(RX_OS_JESD_M)\
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L=$ad_project_params(RX_OS_JESD_L)\
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S=$ad_project_params(RX_OS_JESD_S)"
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S=$ad_project_params(RX_OS_JESD_S)\
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CORUNDUM=$ad_project_params(CORUNDUM)"
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sysid_gen_sys_init_file $sys_cstring
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‎projects/adrv9009zu11eg/adrv2crr_fmc/system_bd_corundum.tcl‎

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###############################################################################
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## Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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# Corundum NIC
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create_bd_intf_port -mode Master -vlnv analog.com:interface:if_qsfp_rtl:1.0 qsfp
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create_bd_port -dir O -from 0 -to 0 -type rst qsfp_rst
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create_bd_port -dir I qsfp_mgt_refclk_p
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create_bd_port -dir I qsfp_mgt_refclk_n
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create_bd_port -dir O -from 3 -to 0 qsfp_led
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# collect build information
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set build_date [clock seconds]
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set git_hash 00000000
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catch {
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set git_hash [exec git rev-parse --short=8 HEAD]
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}
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set tag_ver 0.0.0
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# FW and board IDs
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set fpga_id [expr 0x4738093]
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set fw_id [expr 0x00000000]
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set fw_ver $tag_ver
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set board_vendor_id [expr 0x10ee]
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set board_device_id [expr 0x9066]
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set board_ver 1.0
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set release_info [expr 0x00000000]
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# General variables
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set IRQ_SIZE 8
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set PORTS_PER_IF "1"
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set TX_QUEUE_INDEX_WIDTH "11"
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set RX_QUEUE_INDEX_WIDTH "8"
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set CQN_WIDTH [expr max($TX_QUEUE_INDEX_WIDTH, $RX_QUEUE_INDEX_WIDTH) + 1]
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set TX_QUEUE_PIPELINE [expr 3 + max($TX_QUEUE_INDEX_WIDTH - 12, 0)]
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set RX_QUEUE_PIPELINE [expr 3 + max($RX_QUEUE_INDEX_WIDTH - 12, 0)]
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set TX_DESC_TABLE_SIZE "32"
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set RX_DESC_TABLE_SIZE "32"
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set TX_RAM_SIZE "32768"
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set RX_RAM_SIZE "32768"
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# Extra configurations for Corundum functionality
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ad_ip_parameter sys_ps8 CONFIG.PSU__NUM_FABRIC_RESETS {2}
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# Corundum connections
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connect_bd_net [get_bd_ports qsfp_led] [get_bd_pins corundum_hierarchy/ethernet_core/qsfp_led]
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ad_connect corundum_hierarchy/clk_corundum sys_ps8/pl_clk1
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# Use Utility Logic Vector IP which takes sys_ps8/pl_resetn1 and negates it and connects
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# it to corundum_hierarchy/rst_corundum, but first it's must be disconnected
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# from the Corundum Reset Generator
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delete_bd_objs [get_bd_nets rst_corundum_1]
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ad_ip_instance util_vector_logic util_vector_logic_0
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ad_ip_parameter util_vector_logic_0 CONFIG.C_OPERATION {not}
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ad_ip_parameter util_vector_logic_0 CONFIG.C_SIZE 1
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ad_connect sys_ps8/pl_resetn1 util_vector_logic_0/Op1
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ad_connect corundum_hierarchy/rst_corundum util_vector_logic_0/Res
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ad_connect corundum_hierarchy/qsfp qsfp
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ad_connect corundum_hierarchy/qsfp_rst qsfp_rst
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ad_connect corundum_hierarchy/qsfp_mgt_refclk_p qsfp_mgt_refclk_p
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ad_connect corundum_hierarchy/qsfp_mgt_refclk_n qsfp_mgt_refclk_n
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ad_ip_instance axi_interconnect smartconnect_corundum
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ad_ip_parameter smartconnect_corundum CONFIG.NUM_MI 2
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ad_ip_parameter smartconnect_corundum CONFIG.NUM_SI 1
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ad_connect smartconnect_corundum/ARESETN sys_ps8/pl_resetn1
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ad_connect smartconnect_corundum/S00_ARESETN sys_ps8/pl_resetn1
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ad_connect smartconnect_corundum/M00_ARESETN sys_ps8/pl_resetn1
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ad_connect smartconnect_corundum/M01_ARESETN sys_ps8/pl_resetn1
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ad_connect smartconnect_corundum/ACLK sys_ps8/pl_clk1
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ad_connect smartconnect_corundum/S00_ACLK sys_ps8/pl_clk1
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ad_connect smartconnect_corundum/M00_ACLK sys_ps8/pl_clk1
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ad_connect smartconnect_corundum/M01_ACLK sys_ps8/pl_clk1
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ad_connect smartconnect_corundum/M00_AXI corundum_hierarchy/s_axil_corundum
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ad_ip_parameter sys_ps8 CONFIG.PSU__USE__M_AXI_GP0 1
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ad_ip_parameter sys_ps8 CONFIG.PSU__MAXIGP0__DATA_WIDTH 32
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ad_connect smartconnect_corundum/S00_AXI sys_ps8/M_AXI_HPM0_FPD
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ad_connect sys_ps8/maxihpm0_fpd_aclk sys_200m_clk
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ad_connect corundum_rstgen/slowest_sync_clk sys_200m_clk
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ad_connect corundum_rstgen/ext_reset_in sys_ps8/pl_resetn0
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ad_connect corundum_rstgen/peripheral_aresetn corundum_rstn
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ad_ip_parameter sys_ps8 CONFIG.PSU__USE__S_AXI_GP5 1
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ad_connect sys_200m_clk sys_ps8/saxihp3_fpd_aclk
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assign_bd_address -offset 0xA000_0000 [get_bd_addr_segs \
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corundum_hierarchy/corundum_core/s_axil_ctrl/Reg
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] -target_address_space sys_ps8/Data
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ad_ip_instance util_reduced_logic util_reduced_logic_0
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ad_ip_parameter util_reduced_logic_0 CONFIG.C_OPERATION {or}
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ad_ip_parameter util_reduced_logic_0 CONFIG.C_SIZE $IRQ_SIZE
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ad_connect util_reduced_logic_0/Op1 corundum_hierarchy/irq
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ad_cpu_interrupt ps-4 mb-4 util_reduced_logic_0/Res
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ad_mem_hpc0_interconnect sys_200m_clk corundum_hierarchy/m_axi
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assign_bd_address [get_bd_addr_segs { \
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sys_ps8/SAXIGP0/HPC0_LPS_OCM \
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sys_ps8/SAXIGP0/HPC0_QSPI \
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sys_ps8/SAXIGP0/HPC0_DDR_LOW \
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sys_ps8/SAXIGP0/HPC0_DDR_HIGH \
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}]
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create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_port
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ad_ip_instance axi_iic axi_iic
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ad_connect iic_port axi_iic/iic
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ad_cpu_interconnect 0x43000000 axi_iic
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ad_cpu_interrupt ps-5 mb-14 axi_iic/iic2intc_irpt

‎projects/adrv9009zu11eg/adrv2crr_fmc/system_constr_corundum.xdc‎

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,41 @@
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###############################################################################
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## Copyright (C) 2025 Analog Devices, Inc. All rights reserved.
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### SPDX short identifier: ADIBSD
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###############################################################################
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set_property -dict {PACKAGE_PIN AU11 IOSTANDARD LVCMOS18 } [get_ports qsfp_resetl ] ;
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set_property -dict {PACKAGE_PIN AL12 IOSTANDARD LVCMOS18 PULLUP true } [get_ports qsfp_modprsl ] ;
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set_property -dict {PACKAGE_PIN AW14 IOSTANDARD LVCMOS18 PULLUP true } [get_ports qsfp_intl ] ;
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set_property -dict {PACKAGE_PIN AV11 IOSTANDARD LVCMOS18 } [get_ports qsfp_lpmode ] ;
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set_property PACKAGE_PIN AD2 [get_ports qsfp_rx_p[0] ] ;
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set_property PACKAGE_PIN AD1 [get_ports qsfp_rx_n[0] ] ;
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set_property PACKAGE_PIN AC4 [get_ports qsfp_rx_p[1] ] ;
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set_property PACKAGE_PIN AC3 [get_ports qsfp_rx_n[1] ] ;
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set_property PACKAGE_PIN AB2 [get_ports qsfp_rx_p[2] ] ;
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set_property PACKAGE_PIN AB1 [get_ports qsfp_rx_n[2] ] ;
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set_property PACKAGE_PIN AA4 [get_ports qsfp_rx_p[3] ] ;
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set_property PACKAGE_PIN AA3 [get_ports qsfp_rx_n[3] ] ;
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set_property PACKAGE_PIN AD6 [get_ports qsfp_tx_p[0] ] ;
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set_property PACKAGE_PIN AD5 [get_ports qsfp_tx_n[0] ] ;
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set_property PACKAGE_PIN AC8 [get_ports qsfp_tx_p[1] ] ;
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set_property PACKAGE_PIN AC7 [get_ports qsfp_tx_n[1] ] ;
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set_property PACKAGE_PIN AB6 [get_ports qsfp_tx_p[2] ] ;
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set_property PACKAGE_PIN AB5 [get_ports qsfp_tx_n[2] ] ;
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set_property PACKAGE_PIN AA8 [get_ports qsfp_tx_p[3] ] ;
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set_property PACKAGE_PIN AA7 [get_ports qsfp_tx_n[3] ] ;
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set_property PACKAGE_PIN AD10 [get_ports qsfp_mgt_refclk_p ] ;
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set_property PACKAGE_PIN AD9 [get_ports qsfp_mgt_refclk_n ] ;
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# 156.25 MHz MGT reference clock
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create_clock -period 6.400 -name gt_ref_clk [get_ports qsfp_mgt_refclk_p]

‎projects/adrv9009zu11eg/adrv2crr_fmc/system_project.tcl‎

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Original file line numberDiff line numberDiff line change
@@ -34,13 +34,35 @@ adi_project_create adrv9009zu11eg 0 [list \
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RX_OS_JESD_M [get_env_param RX_OS_JESD_M 4] \
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RX_OS_JESD_L [get_env_param RX_OS_JESD_L 4] \
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RX_OS_JESD_S [get_env_param RX_OS_JESD_S 1] \
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CORUNDUM [get_env_param CORUNDUM 1] \
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] "xczu11eg-ffvf1517-2-i"
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adi_project_files adrv9009zu11eg [list \
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"system_top.v" \
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"../common/adrv9009zu11eg_spi.v" \
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"../common/adrv9009zu11eg_constr.xdc" \
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"../common/adrv2crr_fmc_constr.xdc" \
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"$ad_hdl_dir/library/common/ad_iobuf.v" ]
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if {[get_env_param CORUNDUM 0] == 1} {
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adi_project_files adrv9009zu11eg [list \
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"system_constr_corundum.xdc" \
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"system_top_corundum.v" \
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"$ad_hdl_dir/../corundum/fpga/common/syn/vivado/eth_xcvr_phy_10g_gty_wrapper.tcl" \
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"$ad_hdl_dir/../corundum/fpga/common/syn/vivado/rb_drp.tcl" \
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"$ad_hdl_dir/../corundum/fpga/common/syn/vivado/mqnic_rb_clk_info.tcl" \
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"$ad_hdl_dir/../corundum/fpga/common/syn/vivado/mqnic_ptp_clock.tcl" \
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"$ad_hdl_dir/../corundum/fpga/common/syn/vivado/mqnic_port.tcl" \
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"$ad_hdl_dir/../corundum/fpga/lib/eth/syn/vivado/ptp_clock_cdc.tcl" \
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"$ad_hdl_dir/../corundum/fpga/lib/eth/syn/vivado/ptp_td_leaf.tcl" \
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"$ad_hdl_dir/../corundum/fpga/lib/eth/syn/vivado/ptp_td_rel2tod.tcl" \
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"$ad_hdl_dir/../corundum/fpga/lib/eth/lib/axis/syn/vivado/sync_reset.tcl" \
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"$ad_hdl_dir/../corundum/fpga/lib/eth/lib/axis/syn/vivado/axis_async_fifo.tcl" \
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"$ad_hdl_dir/../corundum/fpga/common/syn/vivado/tdma_ber_ch.tcl"
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]
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} else {
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adi_project_files adrv9009zu11eg [list \
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"system_top.v" \
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]
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}
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adi_project_run adrv9009zu11eg

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