Get ccd power on MI300A

[slabasan]

We just installed the latest esmi on our MI300A system and are trying to read CCD power using the following API:

ret = esmi_read_ccd_power(i, &ccd_power);

But it is giving us the following errors implying it is not supported on our syste.

Failed to get core[0] _COREENERGY, Err[20]:HSMP message/command not supported
Failed to get core[1] _COREENERGY, Err[20]:HSMP message/command not supported
Failed to get core[2] _COREENERGY, Err[20]:HSMP message/command not supported
Failed to get core[3] _COREENERGY, Err[20]:HSMP message/command not supported
Failed to get core[4] _COREENERGY, Err[20]:HSMP message/command not supported

Previously, we have been reading the socket power successfully, but we saw that the latest esmi has a new CCD power domain, so we are hoping to get this info. We see in the README that our model 90F is supported as of Family 0x19 model 90-9fh are supported from v6.6-rc1 onwards. Can you please point us to v6.6-rc1?

Tagging @patki1 as well.

[muthusAMD]

@slabasan The MI300A has the capability to fetch Socket Power.
But CCD Power monitoring is supported only from Family 1Ah Models 50h-57h onwards(not supported in MI300A)

To view the list of supported commands for a specific processor, please execute the following command on the host:

./e_smi_tool -h

Thanks.

[MuthusamyRamalingam]

@slabasan

• Please use the API esmi_metrics_table_get() to collect CCD Energy from user space on MI300A

• Please refer the below files for esmi_metrics_table_get() implementation,

  • https://github.com/amd/esmi_ib_library/blob/master/include/e_smi/e_smi.h
  • https://github.com/amd/esmi_ib_library/blob/master/src/e_smi.c

• Please refer "struct hsmp_metric_table" from the below file,

  • https://github.com/amd/esmi_ib_library/blob/master/include/asm/amd_hsmp.h
    (or)
  • https://github.com/amd/amd_hsmp/blob/master/amd_hsmp.h

  struct hsmp_metric_table {
  __u32 accumulation_counter;

  /* TEMPERATURE */
  __u32 max_socket_temperature;
  __u32 max_vr_temperature;
  __u32 max_hbm_temperature;
  __u64 max_socket_temperature_acc;
  __u64 max_vr_temperature_acc;
  __u64 max_hbm_temperature_acc;

  /* POWER */
  __u32 socket_power_limit;
  __u32 max_socket_power_limit;
  __u32 socket_power;

  /* ENERGY */
  __u64 timestamp;
  __u64 socket_energy_acc;
  __u64 ccd_energy_acc;
  __u64 xcd_energy_acc;
  __u64 aid_energy_acc;
  __u64 hbm_energy_acc;

  /* FREQUENCY */
  __u32 cclk_frequency_limit;
  __u32 gfxclk_frequency_limit;
  __u32 fclk_frequency;
  __u32 uclk_frequency;
  __u32 socclk_frequency[4];
  __u32 vclk_frequency[4];
  __u32 dclk_frequency[4];
  __u32 lclk_frequency[4];
  __u64 gfxclk_frequency_acc[8];
  __u64 cclk_frequency_acc[96];

  /* FREQUENCY RANGE */
  __u32 max_cclk_frequency;
  __u32 min_cclk_frequency;
  __u32 max_gfxclk_frequency;
  __u32 min_gfxclk_frequency;
  __u32 fclk_frequency_table[4];
  __u32 uclk_frequency_table[4];
  __u32 socclk_frequency_table[4];
  __u32 vclk_frequency_table[4];
  __u32 dclk_frequency_table[4];
  __u32 lclk_frequency_table[4];
  __u32 max_lclk_dpm_range;
  __u32 min_lclk_dpm_range;

  /* XGMI */
  __u32 xgmi_width;
  __u32 xgmi_bitrate;
  __u64 xgmi_read_bandwidth_acc[8];
  __u64 xgmi_write_bandwidth_acc[8];

  /* ACTIVITY */
  __u32 socket_c0_residency;
  __u32 socket_gfx_busy;
  __u32 dram_bandwidth_utilization;
  __u64 socket_c0_residency_acc;
  __u64 socket_gfx_busy_acc;
  __u64 dram_bandwidth_acc;
  __u32 max_dram_bandwidth;
  __u64 dram_bandwidth_utilization_acc;
  __u64 pcie_bandwidth_acc[4];

  /* THROTTLERS */
  __u32 prochot_residency_acc;
  __u32 ppt_residency_acc;
  __u32 socket_thm_residency_acc;
  __u32 vr_thm_residency_acc;
  __u32 hbm_thm_residency_acc;
  __u32 spare;

  /* New items at the end to maintain driver compatibility */
  __u32 gfxclk_frequency[8];
  };