clk: add ast2600 support

Most of the commands like writing to the FMC require the clock driver.

Signed-off-by: Tan Siewert <tan@siewert.io>

Author: sinuscosinustan

src/devicetree/g6.dts

@@ -67,6 +67,10 @@
 				compatible = "aspeed,ast2600-scu", "syscon", "simple-mfd";
 				reg = <0x1e6e2000 0x1000>;
 
+				clock {
+					compatible = "aspeed,ast2600-clock";
+				};
+
 				strapping {
 					compatible = "aspeed,ast2600-strapping";
 				};

src/soc/clk.c

@@ -28,11 +28,29 @@
 #define	SCU_SILICON_REVISION		0x7c
 
 #define	AST2500_SCU_H_PLL			0x24
-#define		AST2500_SCU_H_PLL_P_MASK			GENMASK(18, 13)
-#define		AST2500_SCU_H_PLL_P_SHIFT			13
-#define		AST2500_SCU_H_PLL_M_MASK			GENMASK(12, 5)
-#define		AST2500_SCU_H_PLL_M_SHIFT			5
-#define		AST2500_SCU_H_PLL_N_MASK			GENMASK(4, 0)
+#define		AST2500_SCU_H_PLL_P_MASK	GENMASK(18, 13)
+#define		AST2500_SCU_H_PLL_P_SHIFT	13
+#define		AST2500_SCU_H_PLL_M_MASK	GENMASK(12, 5)
+#define		AST2500_SCU_H_PLL_M_SHIFT	5
+#define		AST2500_SCU_H_PLL_N_MASK	GENMASK(4, 0)
+
+/* We only care about SCU004 for now, revision is not required here */
+#define	AST2600_SCU_SILICON_REVISION	0x04
+
+#define	AST2600_SCU_H_PLL			0x200
+#define		AST2600_SCU_H_PLL_P_MASK	GENMASK(22, 19)
+#define		AST2600_SCU_H_PLL_P_SHIFT	19
+#define		AST2600_SCU_H_PLL_N_MASK	GENMASK(18, 13)
+#define		AST2600_SCU_H_PLL_N_SHIFT	13
+#define		AST2600_SCU_H_PLL_M_MASK	GENMASK(12, 0)
+
+#define	AST2600_SCU_HW_STRAP1	0x500
+#define		AST2600_SCU_HW_STRAP1_ARM_CLK			BIT(0)
+#define		AST2600_SCU_HW_STRAP1_CPU_AXI_RATIO		BIT(16)
+#define		AST2600_SCU_HW_STRAP1_AHB_FREQ_RATIO_MASK	GENMASK(12, 11)
+#define		AST2600_SCU_HW_STRAP1_AHB_FREQ_RATIO_SHIFT	11
+
+#define	AST2600_SCU_HW_STRAP1_CLEAR	0x504
 
 struct clk_ops {
 	int64_t (*rate_ahb)(struct clk *ctx);
@@ -256,9 +274,84 @@ static const struct clk_ops ast2500_clk_ops = {
 	.enable = ast2500_clk_enable,
 };
 
+static int64_t ast2600_clk_rate_ahb(struct clk *ctx)
+{
+	uint32_t h_pll_reg, h_pll, h_pll_m, h_pll_n, h_pll_p;
+	uint32_t strap, ahb_ratio, cpu_axi_ratio, hclk;
+	int rc;
+
+	if ((rc = scu_readl(ctx->scu, AST2600_SCU_HW_STRAP1, &strap)) < 0)
+		return rc;
+
+	/* The H-PLL register allows us to calculate the CPU freq */
+	if ((rc = scu_readl(ctx->scu, AST2600_SCU_H_PLL, &h_pll_reg)) < 0)
+		return rc;
+
+	h_pll_p = ((h_pll_reg & AST2600_SCU_H_PLL_P_MASK) >> AST2600_SCU_H_PLL_P_SHIFT) + 1;
+	h_pll_n = ((h_pll_reg & AST2600_SCU_H_PLL_N_MASK) >> AST2600_SCU_H_PLL_N_SHIFT) + 1;
+	h_pll_m = (h_pll_reg & AST2600_SCU_H_PLL_M_MASK) + 1;
+
+	/* H-PLL = CLKIN (always 25 MHz) * (M+1/N+1) / P+1 */
+	h_pll = 25 * (h_pll_m / h_pll_n) / h_pll_p;
+	logt("clk: ast2600: calculated h-pll is %d MHz\n", h_pll);
+
+	cpu_axi_ratio = (strap & AST2600_SCU_HW_STRAP1_CPU_AXI_RATIO);
+
+	/* AXI/AHB clock frequency ratio selection */
+	ahb_ratio = (strap & AST2600_SCU_HW_STRAP1_AHB_FREQ_RATIO_MASK) >> AST2600_SCU_HW_STRAP1_AHB_FREQ_RATIO_SHIFT;
+	if (!ahb_ratio)
+		return -EINVAL;
+
+	/*
+	 * If cpu_axi_ratio is set, then the ratios are default, 4, 6, 8.
+	 * Otherwise, the ratios are default, 2, 3, 4.
+	 * The default is "that makes HCLK = 200MHz", but there's no explanation
+	 * how HCLK is being calculated so I'll just return 200 MHz as AHB Rate if no
+	 * ratio is set lol
+	 */
+	if (!ahb_ratio)
+		return 200;
+
+	/* Ratio calc from the binary value */
+	ahb_ratio++;
+	if (cpu_axi_ratio)
+		ahb_ratio *= 2;
+
+	logt("clk: ast2600: ahb ratio: %d:1\n", ahb_ratio);
+
+	/* I'm just gonna assume that HCLK = H-PLL / 2 / ahb_ratio */
+	hclk = h_pll / 2 / ahb_ratio;
+	logt("clk: ast2600: ahb freq: %d MHz\n", hclk);
+
+	return hclk;
+}
+
+int ast2600_clk_disable(struct clk *ctx, enum clksrc src)
+{
+	if (src != clk_arm)
+		return -ENOTSUP;
+
+	return scu_writel(ctx->scu, AST2600_SCU_HW_STRAP1, AST2600_SCU_HW_STRAP1_ARM_CLK);
+}
+
+int ast2600_clk_enable(struct clk *ctx, enum clksrc src)
+{
+	if (src != clk_arm)
+		return -ENOTSUP;
+
+	return scu_writel(ctx->scu, AST2600_SCU_HW_STRAP1_CLEAR, AST2600_SCU_HW_STRAP1_ARM_CLK);
+}
+
+static const struct clk_ops ast2600_clk_ops = {
+	.rate_ahb = ast2600_clk_rate_ahb,
+	.disable = ast2600_clk_disable,
+	.enable = ast2600_clk_enable,
+};
+
 static const struct soc_device_id clk_match[] = {
     { .compatible = "aspeed,ast2400-clock", .data = &ast2400_clk_ops },
     { .compatible = "aspeed,ast2500-clock", .data = &ast2500_clk_ops },
+    { .compatible = "aspeed,ast2600-clock", .data = &ast2600_clk_ops },
     { },
 };