wishbone.bus: fix Decoder case pattern.

Fixes #4.

Author: Jean-François Nguyen

nmigen_soc/test/test_wishbone_bus.py

@@ -351,6 +351,27 @@ def sim_test():
             sim.add_process(sim_test())
             sim.run()
 
+    def test_coarse_granularity(self):
+        dut = Decoder(addr_width=3, data_width=32)
+        sub = Interface(addr_width=2, data_width=32)
+        sub.memory_map = MemoryMap(addr_width=2, data_width=32)
+        dut.add(sub)
+
+        def sim_test():
+            yield dut.bus.cyc.eq(1)
+
+            yield dut.bus.adr.eq(0x0)
+            yield Delay(1e-6)
+            self.assertEqual((yield sub.cyc), 1)
+
+            yield dut.bus.adr.eq(0x4)
+            yield Delay(1e-6)
+            self.assertEqual((yield sub.cyc), 0)
+
+        with Simulator(dut, vcd_file=open("test.vcd", "w")) as sim:
+            sim.add_process(sim_test())
+            sim.run()
+
 
 class ArbiterTestCase(unittest.TestCase):
     def setUp(self):

nmigen_soc/wishbone/bus.py

@@ -289,7 +289,8 @@ def elaborate(self, platform):
                 if hasattr(sub_bus, "bte"):
                     m.d.comb += sub_bus.bte.eq(getattr(self.bus, "bte", BurstTypeExt.LINEAR))
 
-                with m.Case(sub_pat[:-log2_int(self.bus.data_width // self.bus.granularity)]):
+                granularity_bits = log2_int(self.bus.data_width // self.bus.granularity)
+                with m.Case(sub_pat[:-granularity_bits if granularity_bits > 0 else None]):
                     m.d.comb += [
                         sub_bus.cyc.eq(self.bus.cyc),
                         self.bus.dat_r.eq(sub_bus.dat_r),