csr.wishbone: fix WishboneCSRBridge cycle counter.

Author: Jean-François Nguyen

nmigen_soc/csr/wishbone.py

@@ -84,10 +84,11 @@ def segment(index):
                 with m.Default():
                     m.d.sync += wb_bus.dat_r[segment(index)].eq(csr_bus.r_data)
                     m.d.sync += wb_bus.ack.eq(1)
-                    m.d.sync += cycle.eq(0)
 
         with m.Else():
             m.d.sync += wb_bus.ack.eq(0)
+
+        with m.If(wb_bus.ack):
             m.d.sync += cycle.eq(0)
 
         return m

nmigen_soc/test/test_csr_wishbone.py

@@ -59,9 +59,10 @@ def sim_test():
             yield dut.wb_bus.dat_w.eq(0x55)
             yield
             yield
-            yield dut.wb_bus.stb.eq(0)
             yield
             self.assertEqual((yield dut.wb_bus.ack), 1)
+            yield dut.wb_bus.stb.eq(0)
+            yield
             self.assertEqual((yield reg_1.r_count), 0)
             self.assertEqual((yield reg_1.w_count), 1)
             self.assertEqual((yield reg_1.data), 0x55)
@@ -71,9 +72,10 @@ def sim_test():
             yield dut.wb_bus.dat_w.eq(0xaa)
             yield
             yield
-            yield dut.wb_bus.stb.eq(0)
             yield
+            yield dut.wb_bus.stb.eq(0)
             self.assertEqual((yield dut.wb_bus.ack), 1)
+            yield
             self.assertEqual((yield reg_2.r_count), 0)
             self.assertEqual((yield reg_2.w_count), 0)
             self.assertEqual((yield reg_2.data), 0)
@@ -83,9 +85,10 @@ def sim_test():
             yield dut.wb_bus.dat_w.eq(0xbb)
             yield
             yield
-            yield dut.wb_bus.stb.eq(0)
             yield
             self.assertEqual((yield dut.wb_bus.ack), 1)
+            yield dut.wb_bus.stb.eq(0)
+            yield
             self.assertEqual((yield reg_2.r_count), 0)
             self.assertEqual((yield reg_2.w_count), 1)
             self.assertEqual((yield reg_2.data), 0xbbaa)
@@ -96,21 +99,23 @@ def sim_test():
             yield dut.wb_bus.stb.eq(1)
             yield
             yield
-            yield dut.wb_bus.stb.eq(0)
             yield
             self.assertEqual((yield dut.wb_bus.ack), 1)
             self.assertEqual((yield dut.wb_bus.dat_r), 0x55)
+            yield dut.wb_bus.stb.eq(0)
+            yield
             self.assertEqual((yield reg_1.r_count), 1)
             self.assertEqual((yield reg_1.w_count), 1)
 
             yield dut.wb_bus.adr.eq(1)
             yield dut.wb_bus.stb.eq(1)
             yield
             yield
-            yield dut.wb_bus.stb.eq(0)
             yield
             self.assertEqual((yield dut.wb_bus.ack), 1)
             self.assertEqual((yield dut.wb_bus.dat_r), 0xaa)
+            yield dut.wb_bus.stb.eq(0)
+            yield
             self.assertEqual((yield reg_2.r_count), 1)
             self.assertEqual((yield reg_2.w_count), 1)
 
@@ -120,10 +125,11 @@ def sim_test():
             yield dut.wb_bus.stb.eq(1)
             yield
             yield
-            yield dut.wb_bus.stb.eq(0)
             yield
             self.assertEqual((yield dut.wb_bus.ack), 1)
             self.assertEqual((yield dut.wb_bus.dat_r), 0xbb)
+            yield dut.wb_bus.stb.eq(0)
+            yield
             self.assertEqual((yield reg_2.r_count), 1)
             self.assertEqual((yield reg_2.w_count), 1)
 
@@ -154,9 +160,10 @@ def sim_test():
             yield
             yield
             yield
-            yield dut.wb_bus.stb.eq(0)
             yield
             self.assertEqual((yield dut.wb_bus.ack), 1)
+            yield dut.wb_bus.stb.eq(0)
+            yield
             self.assertEqual((yield reg.r_count), 0)
             self.assertEqual((yield reg.w_count), 1)
             self.assertEqual((yield reg.data), 0x44332211)
@@ -170,9 +177,10 @@ def sim_test():
             yield
             yield
             yield
-            yield dut.wb_bus.stb.eq(0)
             yield
             self.assertEqual((yield dut.wb_bus.ack), 1)
+            yield dut.wb_bus.stb.eq(0)
+            yield
             self.assertEqual((yield reg.r_count), 0)
             self.assertEqual((yield reg.w_count), 1)
             self.assertEqual((yield reg.data), 0x44332211)
@@ -186,10 +194,11 @@ def sim_test():
             yield
             yield
             yield
-            yield dut.wb_bus.stb.eq(0)
             yield
             self.assertEqual((yield dut.wb_bus.ack), 1)
             self.assertEqual((yield dut.wb_bus.dat_r), 0x44332211)
+            yield dut.wb_bus.stb.eq(0)
+            yield
             self.assertEqual((yield reg.r_count), 1)
             self.assertEqual((yield reg.w_count), 1)
 
@@ -203,10 +212,11 @@ def sim_test():
             yield
             yield
             yield
-            yield dut.wb_bus.stb.eq(0)
             yield
             self.assertEqual((yield dut.wb_bus.ack), 1)
             self.assertEqual((yield dut.wb_bus.dat_r), 0x00332200)
+            yield dut.wb_bus.stb.eq(0)
+            yield
             self.assertEqual((yield reg.r_count), 1)
             self.assertEqual((yield reg.w_count), 1)