HSD #15017947641-4: arm64: dts: socfpga: agilex5: Add 4-bit SPI bus width

Add spi-tx-bus-width and spi-rx-bus-width properties with
value 4 to the agilex5 device tree.
This update configures the SPI controller to use a 4-bit
bus width for both transmission and reception,
potentially improving SPI throughput and
matching the hardware capabilities more closely.

Signed-off-by: Fong, Yan Kei <yan.kei.fong@altera.com>

Author: fongyankei

arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts

@@ -212,6 +212,8 @@
 		cdns,tsd2d-ns = <50>;
 		cdns,tchsh-ns = <4>;
 		cdns,tslch-ns = <4>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
 
 		partitions {
 			compatible = "fixed-partitions";