Commit ae1f102
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HSD #15017947641-2: arm64: dts: socfpga: stratix10: Add 4-bit SPI bus width
Add spi-tx-bus-width and spi-rx-bus-width properties with
value 4 to the stratix10 device tree.
This update configures the SPI controller to use a 4-bit
bus width for both transmission and reception,
potentially improving SPI throughput and
matching the hardware capabilities more closely.
Signed-off-by: Fong, Yan Kei <yan.kei.fong@altera.com>1 parent 3b36700 commit ae1f102
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