Commit 48b6571
Commiting the latest checkin from the socfpga-6.12.19-lts.
* HSD #16027204168-10: misc: socfpga_fcs: remove dma mapping
Remove dma mapping/unmapping as this is taken care in svc driver.
Signed-off-by: Mahesh Rao <mahesh.rao@altera.com>
* HSD #16027204168-11: misc: socfpga_fcs_hal: remove
unnecessary calls to svc_task_done()
Remove unnecessary calls to svc_task_done() which
are only required for stratix10_svc_send() calls.
Signed-off-by: Mahesh Rao <mahesh.rao@altera.com>
* dt-bindings: edac: altera: socfpga: Convert to YAML
Convert the device tree bindings for the Altera SoCFPGA ECC
Manager from text to yaml.
Signed-off-by: Matthew Gerlach <matthew.gerlach@altera.com>
Link: https://lore.kernel.org/r/20250325173139.27634-1-matthew.gerlach@altera.com
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
* HSD #16026969365: dt-bindings: edac: altera: socfpga: Add peripherals
Document sdm-qspi-ecc, cram-seu, io06b-ecc and update usb-ecc bindings
Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
* HSD #16026969365: arm64: dts: agilex5: Aligned eccmgr node to dt bindings
Updated Agilex5 eccmgr nodes to align with ecc manager yaml bindings.
Change usb0-ecc and io96b1-ecc node default status to disabled based
on Agilex5 devkit.
Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
* HSD #16026969365: EDAC/altera: Add support for IO96B memory controller
IO96B memory controller has dedicated mailbox interface for ECC error
info and error injection.
Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
* HSD# 16026424936-1: firmware: stratix10-svc: Add
support for Generic mailbox in async framework.
Add support for Generic mailbox in async framework.
Remove WARN_ONCE() when buffer is NULL
Signed-off-by: Mahesh Rao <mahesh.rao@altera.com>
* HSD# 16027094639-1: firmware: stratix10-svc: add support for RSU commands in async framework.
Add support to support RSU mailbox commands to async
framework.
Remove COMMAND_RSU_GET_DEVICE_INFO from the asynchronous
framework since it requires the same client ID as
the QSPI_OPEN command executed in FSBL, which is
only available in the svc_send() function.
Signed-off-by: Mahesh Rao <mahesh.rao@altera.com>
* HSD #16026027311: dts: agilex5: Add DBE interrupt property
Add DBE interrupt property for Agilex5 ECC devices.
Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
* HSD #16026027311: EDAC/altera: Add DBE interrupt handling for Agilex5
SoCFPGA Agilex5 has separate IRQ for DBE, include Agilex5 awareness to
differentiate between Agilex5 and other 64-bit platforms (Agilex7/S10)
since these platform triggers Asynchronous SError interrupt for DBE.
On SoCFPGA platform INTTEST register only supports 16-bit write based on
the HW design, writing 32-bit to INTTEST register triggers SError to CPU.
Use 16-bit write for INITTEST register.
Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
* HSD #15017596792: dt-bindings: edac: altera: socfpga: add compatible for USB3
Document USB3 compatible string.
Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
* Initial commit for linux socfpga CI processes
This is the initial commit for the linux socfpga CI processes.
This commit adds a CODEOWNERS file that add the reviewers automatically
when a PR is submitted.
This commit also adds the pipeline yml file that runs the github action
checks.
This commit also adds a template for the Pull request.
Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
Add coverity scan actions
Add coverity scan and coverity result parse actions.
Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
Update CODEOWNERS list
Update codeowners list for socfpga linux repository.
Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
Update ci-pipeline for coverity scan
Update coverity scan and parser to upload and download pre and post scan
snapshotas artifacts.
Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
update runners to use pg embedded runners
update github actions to use newly added pg embedded runners to
reduce runner wait time.
Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
Implement release tag checking into CI
Implement CI process to check for release tag in target branch to
prevent unauthorized check into branches that has already been
released.
Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
ci-pipeline.yml: Update verification runner type.
Update verification action runner to hpc runner and added workspace
cleanup prior to action execution.
Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
ci-pipeline.yml: add on-board verification job
Add on-board regression verification job which runs basic sanity test on
board.
Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
ci-pipeline: update container url and verification runner lable
Update container url to use containers with built in toolchains and
tools and verification runner lable to linux-arc-runner.
Removed check-review as it is redundant.
Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
* HSD# 16027100077-2: spi: spi-cadence-quadspi: Fix pm runtime unbalance
Having PM put sync in remove function is causing PM underflow during
remove operation. This is cause by runtime_pm_get_sync not being
exercise anywhere during the op. This fix will ensure that call are
match; pm_runtime_enable()/pm_runtime_disable(), pm_runtime_get_sync()/
pm_runtime_put_sync()
echo 108d2000.spi > /sys/bus/platform/drivers/cadence-qspi/unbind
[ 49.644256] Deleting MTD partitions on "108d2000.spi.0":
[ 49.649575] Deleting u-boot MTD partition
[ 49.684087] Deleting root MTD partition
[ 49.724188] cadence-qspi 108d2000.spi: Runtime PM usage count underflow!
Also change the clk_disable_unprepare() to clk_disable() as continuous
bind and unbind will cause warning being thrown with inidication that
the clock is already unprepared.
Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@intel.com>
* HSD#14024915012: spi: cadence-qspi: fix max chip-select
querying logic
Fix the querying logic for getting the max chip-select
from chip-select information in each qspi device node.
Fixes: 0f3841a ("spi: cadence-qspi: report correct number of chip-select")
Signed-off-by: Mahesh Rao <mahesh.rao@altera.com>
* HSD#15017227419-1: misc: fcs_hal: Added AES streaming APIs
Implemented streaming APIs for AES encryption/decryption
Exported functions to be used by the fcs config driver
Signed-off-by: Balsundar Ponnusamy <balsundar.ponnusamy@intel.com>
* HSD#15017227419-2: misc: fcs_config: Added AES streaming APIs
Implemented streaming APIs for the AES encryption/decryption
Added the attributes for init, update and final stage
Signed-off-by: Balsundar Ponnusamy <balsundar.ponnusamy@intel.com>
* HSD#15017227419-3: misc: fcs_hal: Streaming API for ECDSA data sign
Added streaming APIs for ECDSA SHA2 data sign operations
Exported functions that can be used by the config driver
Signed-off-by: Balsundar Ponnusamy <balsundar.ponnusamy@intel.com>
* HSD#15017227419-4: misc: fcs_config: Streaming API for ECDSA data sign
Implemented streaming APIs for the ECDSA sha2 data sign
Added the attributes for init, update and final stage
Signed-off-by: Balsundar Ponnusamy <balsundar.ponnusamy@intel.com>
* HSD#15017227419-5: misc: fcs_hal: Streaming API for ECDSA data verify
Added streaming APIs for ECDSA SHA2 data verification operations
Exported functions that can be used by the config driver
Signed-off-by: Balsundar Ponnusamy <balsundar.ponnusamy@intel.com>
* HSD#15017227419-6: misc: fcs_config: ECDSA data verify streaming APIs
Implemented streaming APIs for the ECDSA sha2 data verification
Added the attributes for init, update and final stage
Signed-off-by: Balsundar Ponnusamy <balsundar.ponnusamy@intel.com>
* HSD#15017227419-7: crypto: socfpga-crypto: Remove message digest
Removing message digest from the crypto framework
Signed-off-by: Khadgi Sagar <sagar.khadgi@intel.com>
Signed-off-by: Balsundar Ponnusamy <balsundar.ponnusamy@intel.com>
* HSD#15017227419-8: misc: fcs_hal: message digest generation updates
Removing digest generation function invokde through crypto framework
Adding digest generation to support from sysfs interface
Both one shot and streaming apis are added
Signed-off-by: Khadgi Sagar <sagar.khadgi@intel.com>
Signed-off-by: Balsundar Ponnusamy <balsundar.ponnusamy@intel.com>
* HSD#15017227419-9: misc: fcs_config: message digest generation update
Adding sysfs attributes for supporting message digest generation
with streaming and one shot mode
Signed-off-by: Khadgi Sagar <sagar.khadgi@intel.com>
Signed-off-by: Balsundar Ponnusamy <balsundar.ponnusamy@intel.com>
* HSD#15017227419-10: misc: fcs_hal: Streaming APIs for hmac verify
Added streaming APIs for hmac verification
Exported functions that can be used by the config driver
Signed-off-by: Khadgi Sagar <sagar.khadgi@intel.com>
Signed-off-by: Balsundar Ponnusamy <balsundar.ponnusamy@intel.com>
* HSD#15017227419-11: misc: fcs_config: Added streaming APIs for mac verify
Implemented streaming APIs for the hmac verification
Added the attributes for init, update and final stage
Signed-off-by: Khadgi Sagar <sagar.khadgi@intel.com>
Signed-off-by: Balsundar Ponnusamy <balsundar.ponnusamy@intel.com>
* HSD#15017619771: mtd: rawnand: cadence: Add NVDDR mode support
Add NVDDR/synchronous timing mode support to cadence nand driver.
Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
* HSD#15017844483: arm: dts: socfpga: Increase JFFS2 rootfs partition size
Increase the JFFS2 partition size to support larger JFFS2 root filesystem.
Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
* HSD #15017547288: fpga: altera-cvp: Add sleep for CVP recovery
Add 50us sleep in write_init after set CVP_CONFIG bit and
in teardown after reset CVP_CONFIG bit in order for FW to
capture correct CVP_CONFIG flag for CVP recovery.
Signed-off-by: Murugasen Krishnan, Kuhanh <kuhanh.murugasen.krishnan@intel.com>
* HSD#16027578610-1: arch: arm: configs: defconfig: Disable FCS drivers
Disable FCS drivers. This will be enabled in the series of patch set
Signed-off-by: Balsundar Ponnusamy <balsundar.ponnusamy@intel.com>
Reviewed-by: Tanmay Kathpalia <tanmay.kathpalia@intel.com>
Reviewed-by: Khadgi Sagar <sagar.khadgi@intel.com>
Reviewed-by: Mahesh Rao <mahesh.rao@altera.com>
* HSD#16027578610-2: arm64: dts: agilex5: remove fcs hal and crypto node
Removing FCS HAL driver and crypto driver node from the dtsi.
Moving the config driver inside the firmware node
Signed-off-by: Balsundar Ponnusamy <balsundar.ponnusamy@intel.com>
Reviewed-by: Tanmay Kathpalia <tanmay.kathpalia@intel.com>
Reviewed-by: Khadgi Sagar <sagar.khadgi@intel.com>
Reviewed-by: Mahesh Rao <mahesh.rao@altera.com>
* HSD#16027578610-3: dt-bindings: crypto: agilex5: Remove documentation
Remove yaml file for the crypto driver
Signed-off-by: Balsundar Ponnusamy <balsundar.ponnusamy@intel.com>
Reviewed-by: Tanmay Kathpalia <tanmay.kathpalia@intel.com>
Reviewed-by: Khadgi Sagar <sagar.khadgi@intel.com>
Reviewed-by: Mahesh Rao <mahesh.rao@altera.com>
* HSD#16027578610-4: arm64: dts: agilex: remove fcs hal and crypto node
Removing FCS HAL driver and crypto driver node from the dtsi.
Moving the config driver inside the firmware node
Signed-off-by: Balsundar Ponnusamy <balsundar.ponnusamy@intel.com>
Reviewed-by: Tanmay Kathpalia <tanmay.kathpalia@intel.com>
Reviewed-by: Khadgi Sagar <sagar.khadgi@intel.com>
Reviewed-by: Mahesh Rao <mahesh.rao@altera.com>
* HSD#16027578610-5: arm64: dts: n5x: update node name to fcs config
Updating the node name to the fcs_config
Signed-off-by: Balsundar Ponnusamy <balsundar.ponnusamy@intel.com>
Reviewed-by: Tanmay Kathpalia <tanmay.kathpalia@intel.com>
Reviewed-by: Khadgi Sagar <sagar.khadgi@intel.com>
Reviewed-by: Mahesh Rao <mahesh.rao@altera.com>
* HSD#16027578610-6: dt-bindings: misc: fcs_hal: Remove documentation
Remove yaml file for the fcs hal driver
Signed-off-by: Balsundar Ponnusamy <balsundar.ponnusamy@intel.com>
Reviewed-by: Tanmay Kathpalia <tanmay.kathpalia@intel.com>
Reviewed-by: Khadgi Sagar <sagar.khadgi@intel.com>
Reviewed-by: Mahesh Rao <mahesh.rao@altera.com>
* HSD#16027578610-7: crypto: socfpga-crypto: Remove crypto driver
Removing crypto driver and this functionality will be moved to
fcs config driver
Signed-off-by: Balsundar Ponnusamy <balsundar.ponnusamy@intel.com>
Reviewed-by: Tanmay Kathpalia <tanmay.kathpalia@intel.com>
Reviewed-by: Khadgi Sagar <sagar.khadgi@intel.com>
Reviewed-by: Mahesh Rao <mahesh.rao@altera.com>
* HSD#16027578610-8: misc: fcs_config: Combine HAL driver into config driver
Implement random number generation using config driver
Combine FCS HAL driver into config driver
Signed-off-by: Balsundar Ponnusamy <balsundar.ponnusamy@intel.com>
Reviewed-by: Tanmay Kathpalia <tanmay.kathpalia@intel.com>
Reviewed-by: Khadgi Sagar <sagar.khadgi@intel.com>
Reviewed-by: Mahesh Rao <mahesh.rao@altera.com>
* HSD#16027578610-9: arch: arm: configs: defconfig: Enable FCS config driver
Enable FCS config driver for compilation
Signed-off-by: Balsundar Ponnusamy <balsundar.ponnusamy@intel.com>
Reviewed-by: Tanmay Kathpalia <tanmay.kathpalia@intel.com>
Reviewed-by: Khadgi Sagar <sagar.khadgi@intel.com>
Reviewed-by: Mahesh Rao <mahesh.rao@altera.com>
* net: ethernet: altera: fix compilation warning
Fix day one compilation warning for enum vs. int mismatch.
Signed-off-by: Matthew Gerlach <matthew.gerlach@altera.com>
* ci-pipeline: implement false positive coverity warning bypass
Implement coverity false positive bypass mechanism until proper
disposition mechanism is implemented.
Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
* HSD#14021922100: firmware: stratix10-svc: add reboot notifier to put cores to WFI
Add reboot notifier to put all secondary cores to WFI prior to reboot to
support warm reset on Agilex and Stratix10.
Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
* HSD#14021922100 : spi: cadence-qspi: add quirk to disable runtime PM
Add quirk to disable runtime PM for socfpga.
When runtime PM is enabled it will cause the SPL to stall after reboot
as SPI is not put into a warm reset state by the kernel.
Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
* HSD #14024927011: fpga: altera-cvp: Fixed read config type for credit register
This fix is required to use the correct altera_read_config type
for CVP credit register for Agilex5 and for non-Agilex5.
altera_read_config_dword is used for Agilex5 credits as it is
12bits and altera_read_config_byte is used for non-Agilex5
credits as it is 8bits.
Signed-off-by: Murugasen Krishnan, Kuhanh <kuhanh.murugasen.krishnan@intel.com>
* HSD#15017850030: arch: arm: agilex3: update phy skew value.
Update the phy skew value based on the theoretically calculated
value, based on the board skew clock (ps)
Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>
* HSD #14025277517-1: arm64: dts: stratix10: Add Async
interrupt support
Add Async interrupt support to Stratix10 SoC FPGA
Signed-off-by: Mahesh Rao <mahesh.rao@altera.com>
* HSD #14025277517-2: hwmon: soc64: Change log print level
Change print log level from warn to debug.
Signed-off-by: Mahesh Rao <mahesh.rao@altera.com>
* HSD #15017937880: EDAC/altera: Fix OCRAM ECC init for the warm reset
OCRAM is initialize by Secure Device Manager(SDM). For the warm reset,
SDM do not perform the OCRAM wipe. So OCRAM ECC INITCOMPLETEA bit is not
set and ECC_EN bit of CTRL register is required to enable after the warm
reset.
Signed-off-by: Niravkumar L Rabara <nirav.rabara@altera.com>
* HSD#16027607811: misc: fcs: handle SDOS warning
This patch addresses the SDOS warning that occurs
for weak keys.
Signed-off-by: Sagar Khadgi <sagar.khadgi@intel.com>
Reviewed-by: Tanmay Kathpalia <tanmay.kathpalia@intel.com>
Reviewed-by: Khadgi Sagar <sagar.khadgi@intel.com>
Reviewed-by: Mahesh Rao <mahesh.rao@altera.com>
Reviewed-by: Ang Tien Sung <tien.sung.ang@intel.com>
* HSD #15017977433: fpga: altera-cvp: Add FPGA Configuration Framework dependency
Altera CvP FPGA Manager driver depends on FPGA
Configuration Framework drivers to be loaded in
the kernel. Updating FPGA_MGR_ALTERA_CVP in Kconfig
depends on to include FPGA.
Signed-off-by: Murugasen Krishnan, Kuhanh <kuhanh.murugasen.krishnan@altera.com>
* HSD#15017850030: arch: arm: agilex3: Add device tree for Agilex3 socdk
Add the base device tree for the Agilex3 SoCDK, which is an
instantiation of the Agilex5 Hard Processor System (HPS).
Signed-off-by: Niravkumar L Rabara <nirav.rabara@altera.com>
* HSD #15017947641-1: arm64: dts: socfpga: n5x: Add 4-bit SPI bus width
Add spi-tx-bus-width and spi-rx-bus-width properties with
value 4 to the n5x device tree.
This update configures the SPI controller to use a 4-bit
bus width for both transmission and reception,
potentially improving SPI throughput and
matching the hardware capabilities more closely.
Signed-off-by: Fong, Yan Kei <yan.kei.fong@altera.com>
* HSD #15017947641-2: arm64: dts: socfpga: stratix10: Add 4-bit SPI bus width
Add spi-tx-bus-width and spi-rx-bus-width properties with
value 4 to the stratix10 device tree.
This update configures the SPI controller to use a 4-bit
bus width for both transmission and reception,
potentially improving SPI throughput and
matching the hardware capabilities more closely.
Signed-off-by: Fong, Yan Kei <yan.kei.fong@altera.com>
* HSD #15017947641-3: arm64: dts: socfpga: agilex: Add 4-bit SPI bus width
Add spi-tx-bus-width and spi-rx-bus-width properties with
value 4 to the agilex device tree.
This update configures the SPI controller to use a 4-bit
bus width for both transmission and reception,
potentially improving SPI throughput and
matching the hardware capabilities more closely.
Signed-off-by: Fong, Yan Kei <yan.kei.fong@altera.com>
* HSD #15017947641-4: arm64: dts: socfpga: agilex5: Add 4-bit SPI bus width
Add spi-tx-bus-width and spi-rx-bus-width properties with
value 4 to the agilex5 device tree.
This update configures the SPI controller to use a 4-bit
bus width for both transmission and reception,
potentially improving SPI throughput and
matching the hardware capabilities more closely.
Signed-off-by: Fong, Yan Kei <yan.kei.fong@altera.com>
* ci-pipeline: Remove redundant review check
Remove redundant review check as its enabled in the git inventory
settings.
Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
* HSD# 16027100077-3: mtd: spi-nor: core: Check for null pointer to avoid soft error
Ensure that the pointer passed to module_put() in spi_nor_put_device()
is not NULL before use. In certain configurations, the pointer may be
uninitialized or NULL, which can lead to a null pointer dereference
and a soft kernel error.
This change adds a guard clause to return early, preventing the error
and maintaining system stability without requiring a reboot.
Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
* HSD#18042683105: arm64: dts: agilex7: remove undefined clock in SMMU node
Removed undefined clock in SMMU node which causes smmu probe to fail.
Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
* HSD#15017037436 arm64: dts: agilex5: add DTS support to enable ATF NAND boot
Add new DTS file to update the boot args and flash partition
details to accommodate the new FIP partition for ATF direct
NAND boot method.
Signed-off-by: Girisha Dengi <girisha.dengi@altera.com>
* HSD #14025217015: arm64: dts: agilex5: Enable SDIO support
The 'no-sdio' property indicates that the controller is
limited in sending SDIO commands during initialization.
This patch removes the property to enable full SDIO
functionality, allowing SDIO peripherals to be properly
initialized and used.
Signed-off-by: Rohan G Thomas <rohan.g.thomas@altera.com>
* HSD #16027944589: net: stmmac: Reset residual action set in L3L4 filters
When deleting an L3/L4 flower filter entry, the action field
is not being reset. So if a filter was previously configured
with a drop action, that action may persist and affect
subsequent configurations unintentionally. This commit
ensures action field is cleared when the filter is deleted.
Fixes: 425eabd ("net: stmmac: Implement L3/L4 Filters using TC Flower")
Signed-off-by: Rohan G Thomas <rohan.g.thomas@altera.com>
* correction on ci-pipeline.yml
---------
Signed-off-by: Mahesh Rao <mahesh.rao@altera.com>
Signed-off-by: Matthew Gerlach <matthew.gerlach@altera.com>
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@intel.com>
Signed-off-by: Balsundar Ponnusamy <balsundar.ponnusamy@intel.com>
Signed-off-by: Khadgi Sagar <sagar.khadgi@intel.com>
Signed-off-by: Murugasen Krishnan, Kuhanh <kuhanh.murugasen.krishnan@intel.com>
Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>
Signed-off-by: Niravkumar L Rabara <nirav.rabara@altera.com>
Signed-off-by: Sagar Khadgi <sagar.khadgi@intel.com>
Signed-off-by: Murugasen Krishnan, Kuhanh <kuhanh.murugasen.krishnan@altera.com>
Signed-off-by: Fong, Yan Kei <yan.kei.fong@altera.com>
Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
Signed-off-by: Girisha Dengi <girisha.dengi@altera.com>
Signed-off-by: Rohan G Thomas <rohan.g.thomas@altera.com>
Co-authored-by: Mahesh Rao <mahesh.rao@altera.com>
Co-authored-by: Matthew Gerlach <matthew.gerlach@altera.com>
Co-authored-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
Co-authored-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
Co-authored-by: Khairul Anuar Romli <khairul.anuar.romli@intel.com>
Co-authored-by: Balsundar Ponnusamy <balsundar.ponnusamy@intel.com>
Co-authored-by: Murugasen Krishnan, Kuhanh <kuhanh.murugasen.krishnan@intel.com>
Co-authored-by: Boon Khai Ng <boon.khai.ng@altera.com>
Co-authored-by: Niravkumar L Rabara <nirav.rabara@altera.com>
Co-authored-by: Sagar Khadgi <sagar.khadgi@intel.com>
Co-authored-by: Murugasen Krishnan, Kuhanh <kuhanh.murugasen.krishnan@altera.com>
Co-authored-by: Fong, Yan Kei <yan.kei.fong@altera.com>
Co-authored-by: Girisha Dengi <girisha.dengi@altera.com>
Co-authored-by: Rohan G Thomas <rohan.g.thomas@altera.com>
Co-authored-by: Narayan, Preetam <preetam.narayan@altera.com>1 parent 1e72f56 commit 48b6571
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36 files changed
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-948
lines changed- .github/workflows
- Documentation/devicetree/bindings
- crypto
- misc
- arch
- arm64
- boot/dts
- altera
- intel
- configs
- arm/boot/dts/intel/socfpga
- drivers
- crypto
- edac
- firmware
- fpga
- hwmon
- misc
- mtd
- nand/raw
- spi-nor
- net/ethernet
- altera
- stmicro/stmmac
- spi
- include/misc
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