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Andrew Savonichevasavonic
Andrew Savonichev
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[dxsa][mlir] Port LIT tests from dxilconv
dxilconv tool has a LIT test suite that covers most instructions. These original tests are DXBC container binaries, but the current mlir-translate tool cannot translate from them directly - it needs only the content of SHEX section. The tests are generated by extracting shader binaries from DXBC containers. LIT checks are auto-generated by MLIR utils/generate-test-checks.py script. The checks reflect the current state of the compiler, and it is expected they will change once we enable more instructions. Tests in hlsl directory are from: https://github.com/microsoft/DirectXShaderCompiler/tree/main/projects/dxilconv/test/dxbc2dxil Tests in asm directory are from: https://github.com/microsoft/DirectXShaderCompiler/tree/main/projects/dxilconv/test/dxbc2dxil-asm
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‎mlir/test/Target/DXSA/asm/call2.test‎

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// RUN: mlir-translate --import-dxsa-bin %S/inputs/call2.shex | FileCheck %s
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// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py
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// CHECK-LABEL: dxsa.dcl_global_flags <refactoringAllowed>
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// CHECK: dxsa.dcl_input_ps linear v<0, <x>>
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// CHECK: dxsa.dcl_input_ps constant v<1, <x, y, z>>
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// CHECK: dxsa.dcl_output o<0, <x>>
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// CHECK: dxsa.dcl_temps 1
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// CHECK: dxsa.mov r<0, <x, y, z>>, v<1, <x, y, z, z>>
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// CHECK: dxsa.call label<0>
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// CHECK: dxsa.callc_nz r<0, <x>>, label<0>
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// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 1 : i32}
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// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {num_components = 4 : i32, one = 0 : i32, type = 1 : i32}
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// CHECK: dxsa.instruction "switch" %[[OPERAND_0]]
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// CHECK: dxsa.case l(0x1)
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// CHECK: dxsa.call label<2>
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// CHECK: dxsa.callc_nz r<0, <y>>, label<1>
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// CHECK: dxsa.break
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// CHECK: dxsa.default
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// CHECK: dxsa.callc_nz r<0, <z>>, label<2>
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// CHECK: dxsa.break
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// CHECK: dxsa.case l(0x2)
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// CHECK: dxsa.break
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// CHECK: dxsa.endswitch
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// CHECK: dxsa.add o<0, <x>>, r<0, <x>>, l(0x3F800000)
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// CHECK: dxsa.ret
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// CHECK: dxsa.label label<0>
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// CHECK: dxsa.mov r<0, <x>>, l(0x40A00000)
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// CHECK: dxsa.ret
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// CHECK: dxsa.label label<1>
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// CHECK: dxsa.mov r<0, <x>>, v<0, <x>>
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// CHECK: dxsa.ret
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// CHECK: dxsa.label label<2>
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// CHECK: dxsa.mov r<0, <x>>, l(0x40400000)
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// CHECK: dxsa.ret
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‎mlir/test/Target/DXSA/asm/cs3.test‎

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// RUN: mlir-translate --import-dxsa-bin %S/inputs/cs3.shex | FileCheck %s
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// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py
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// CHECK-LABEL: dxsa.dcl_global_flags <refactoringAllowed>
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// CHECK: dxsa.dcl_constant_buffer <id = 0, size = 1>, <immediateIndexed>
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// CHECK: dxsa.dcl_input vThreadIDInGroup<<x, y, z>>
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// CHECK: dxsa.dcl_temps 3
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// CHECK: dxsa.dcl_tgsm_raw g<0>, 1024
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// CHECK: dxsa.dcl_thread_group <x = 4, y = 2, z = 3>
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// CHECK: dxsa.ishl r<0, <x>>, vThreadIDInGroup<<z>>, l(0x2)
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// CHECK: %[[INDEX_0:.*]] = dxsa.index.imm {imm = 0 : i32}
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// CHECK: %[[OPERAND_0:.*]] = dxsa.operand %[[INDEX_0]] {mask = 48 : i32, num_components = 4 : i32, type = 31 : i32}
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// CHECK: %[[INDEX_1:.*]] = dxsa.index.imm {imm = 0 : i32}
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// CHECK: %[[OPERAND_1:.*]] = dxsa.operand %[[INDEX_1]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32}
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// CHECK: %[[INDEX_2:.*]] = dxsa.index.imm {imm = 0 : i32}
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// CHECK: %[[INDEX_3:.*]] = dxsa.index.imm {imm = 0 : i32}
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// CHECK: %[[OPERAND_2:.*]] = dxsa.operand %[[INDEX_2]], %[[INDEX_3]] {num_components = 4 : i32, swizzle = dense<[3, 2, 1, 0]> : vector<4xi32>, type = 8 : i32}
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// CHECK: dxsa.instruction "store_raw" %[[OPERAND_0]], %[[OPERAND_1]], %[[OPERAND_2]]
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// CHECK: dxsa.sync <tgsm>
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// CHECK: dxsa.sync <uav_group>
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// CHECK: dxsa.sync <uav_global>
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// CHECK: dxsa.sync <tgsm|threads>
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// CHECK: dxsa.sync <uav_group|threads>
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// CHECK: dxsa.sync <uav_global|threads>
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// CHECK: dxsa.sync <uav_group|tgsm>
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// CHECK: dxsa.sync <uav_global|tgsm>
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// CHECK: dxsa.sync <uav_group|tgsm|threads>
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// CHECK: dxsa.sync <uav_global|tgsm|threads>
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// CHECK: %[[INDEX_4:.*]] = dxsa.index.imm {imm = 0 : i32}
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// CHECK: %[[OPERAND_3:.*]] = dxsa.operand %[[INDEX_4]] {mask = 80 : i32, num_components = 4 : i32, type = 0 : i32}
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// CHECK: %[[INDEX_5:.*]] = dxsa.index.imm {imm = 0 : i32}
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// CHECK: %[[OPERAND_4:.*]] = dxsa.operand %[[INDEX_5]] {num_components = 4 : i32, one = 0 : i32, type = 0 : i32}
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// CHECK: %[[INDEX_6:.*]] = dxsa.index.imm {imm = 0 : i32}
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// CHECK: %[[OPERAND_5:.*]] = dxsa.operand %[[INDEX_6]] {num_components = 4 : i32, swizzle = dense<[2, 0, 3, 1]> : vector<4xi32>, type = 31 : i32}
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// CHECK: dxsa.instruction "ld_raw" %[[OPERAND_3]], %[[OPERAND_4]], %[[OPERAND_5]]
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// CHECK: dxsa.imm_atomic_iadd r<2, <x>>, g<0>, r<1, <x, y, x, x>>, vThreadIDInGroup<<x>>
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// CHECK: dxsa.atomic_or g<0>, r<1, <x, y, x, x>>, vThreadIDInGroup<<x>>
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// CHECK: dxsa.atomic_cmp_store g<0>, r<1, <x, y, x, x>>, vThreadIDInGroup<<y>>, vThreadIDInGroup<<x>>
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// CHECK: dxsa.imm_atomic_cmp_exch r<1, <x>>, g<0>, r<1, <x, y, x, x>>, vThreadIDInGroup<<y>>, vThreadIDInGroup<<x>>
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// CHECK: dxsa.ret
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‎mlir/test/Target/DXSA/asm/cyclecounter.test‎

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// RUN: mlir-translate --import-dxsa-bin %S/inputs/cyclecounter.shex | FileCheck %s
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// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py
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// CHECK-LABEL: dxsa.dcl_temps 1
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// CHECK: dxsa.dcl_output o<0>
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// CHECK: dxsa.dcl_input cycleCounter<<x>>
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// CHECK: dxsa.mov r<0>, l(0x0)
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// CHECK: dxsa.mov r<0, <z>>, cycleCounter<<x>>
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// CHECK: dxsa.mov o<0>, r<0>
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‎mlir/test/Target/DXSA/asm/hs3.test‎

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// RUN: mlir-translate --import-dxsa-bin %S/inputs/hs3.shex | FileCheck %s
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// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py
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// CHECK-LABEL: dxsa.hs_decls
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// CHECK: dxsa.dcl_input_control_point_count 4
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// CHECK: dxsa.dcl_output_control_point_count 32
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// CHECK: dxsa.dcl_tessellator_domain domain_quad
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// CHECK: dxsa.dcl_tessellator_partitioning partitioning_fractional_odd
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// CHECK: dxsa.dcl_tessellator_output_primitive output_triangle_cw
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// CHECK: dxsa.dcl_hs_max_tessfactor 6.400000e+01
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// CHECK: dxsa.hs_control_point_phase
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// CHECK: dxsa.dcl_input v<[4, 0]>
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// CHECK: dxsa.dcl_input v<[4, 1], <x, y>>
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// CHECK: dxsa.dcl_input v<[4, 2], <x, y, z>>
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// CHECK: dxsa.dcl_input vOutputControlPointID<none>
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// CHECK: dxsa.dcl_input vPrim<none>
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// CHECK: dxsa.dcl_output o<0>
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// CHECK: dxsa.dcl_output o<1, <x, y>>
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// CHECK: dxsa.dcl_output o<2, <x, y, z>>
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// CHECK: dxsa.dcl_temps 1
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// CHECK: dxsa.udiv null, r<0, <x>>, vOutputControlPointID, l(0x4)
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// CHECK: dxsa.mov o<0>, v<[r<0, <x>>, 0]>
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// CHECK: dxsa.mov o<1, <x, y>>, v<[r<0, <x>>, 1], <x, y, x, x>>
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// CHECK: dxsa.mov o<2, <x, y, z>>, v<[r<0, <x>>, 2], <x, y, z, x>>
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// CHECK: dxsa.hs_fork_phase
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// CHECK: dxsa.dcl_input vicp<[4, 0]>
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// CHECK: dxsa.dcl_input vicp<[4, 1], <x, y>>
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// CHECK: dxsa.dcl_input vicp<[4, 2], <x, y, z>>
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// CHECK: dxsa.dcl_input vocp<[32, 0]>
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// CHECK: dxsa.dcl_input vocp<[32, 1], <x, y>>
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// CHECK: dxsa.dcl_input vocp<[32, 2], <x, y, z>>
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// CHECK: dxsa.dcl_hs_fork_phase_instance_count 4
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// CHECK: dxsa.dcl_input vForkInstanceID<none>
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// CHECK: dxsa.dcl_input vPrim<none>
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// CHECK: dxsa.dcl_index_range o<0>, 4
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// CHECK: dxsa.dcl_temps 1
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// CHECK: dxsa.dcl_indexable_temp x<0>[4], 1
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// CHECK: dxsa.dcl_output_siv o<0, <x>>, <finalQuadUeq0EdgeTessFactor>
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// CHECK: dxsa.dcl_output_siv o<1, <x>>, <finalQuadVeq0EdgeTessFactor>
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// CHECK: dxsa.dcl_output_siv o<2, <x>>, <finalQuadUeq1EdgeTessFactor>
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// CHECK: dxsa.dcl_output_siv o<3, <x>>, <finalQuadVeq1EdgeTessFactor>
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// CHECK: dxsa.mov x<[0, 0], <x>>, l(0x40000000)
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// CHECK: dxsa.mov x<[0, 1], <x>>, l(0x40800000)
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// CHECK: dxsa.mov x<[0, 2], <x>>, l(0x41700000)
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// CHECK: dxsa.mov x<[0, 3], <x>>, l(0x40C00000)
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// CHECK: dxsa.mov r<0, <x>>, vForkInstanceID<none>
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// CHECK: dxsa.mov o<r<0, <x>>, <x>>, x<[0, r<0, <x>>], <x>>
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// CHECK: dxsa.hs_fork_phase
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// CHECK: dxsa.dcl_input vicp<[4, 0]>
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// CHECK: dxsa.dcl_input vicp<[4, 1], <x, y>>
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// CHECK: dxsa.dcl_input vicp<[4, 2], <x, y, z>>
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// CHECK: dxsa.dcl_input vocp<[32, 0]>
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// CHECK: dxsa.dcl_input vocp<[32, 1], <x, y>>
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// CHECK: dxsa.dcl_input vocp<[32, 2], <x, y, z>>
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// CHECK: dxsa.dcl_hs_fork_phase_instance_count 4
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// CHECK: dxsa.dcl_input vForkInstanceID<none>
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// CHECK: dxsa.dcl_input vPrim<none>
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// CHECK: dxsa.dcl_index_range o<0>, 4
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// CHECK: dxsa.dcl_temps 1
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// CHECK: dxsa.dcl_indexable_temp x<0>[4], 1
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// CHECK: dxsa.dcl_output o<0, <y>>
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// CHECK: dxsa.dcl_output o<1, <y>>
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// CHECK: dxsa.dcl_output o<2, <y>>
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// CHECK: dxsa.dcl_output o<3, <y>>
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// CHECK: dxsa.mov x<[0, 0], <x>>, l(0x41400000)
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// CHECK: dxsa.mov x<[0, 1], <x>>, l(0x42000000)
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// CHECK: dxsa.mov x<[0, 2], <x>>, l(0x41700000)
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// CHECK: dxsa.mov x<[0, 3], <x>>, l(0x40A00000)
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// CHECK: dxsa.mov r<0, <x>>, vForkInstanceID<none>
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// CHECK: dxsa.mov o<r<0, <x>>, <y>>, x<[0, r<0, <x>>], <x>>
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// CHECK: dxsa.hs_join_phase
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// CHECK: dxsa.dcl_input vicp<[4, 0]>
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// CHECK: dxsa.dcl_input vicp<[4, 1], <x, y>>
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// CHECK: dxsa.dcl_input vicp<[4, 2], <x, y, z>>
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// CHECK: dxsa.dcl_input vocp<[32, 0]>
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// CHECK: dxsa.dcl_input vocp<[32, 1], <x, y>>
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// CHECK: dxsa.dcl_input vocp<[32, 2], <x, y, z>>
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// CHECK: dxsa.dcl_input vpc<0, <x, y>>
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// CHECK: dxsa.dcl_input vpc<1, <x, y>>
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// CHECK: dxsa.dcl_input vpc<2, <x, y>>
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// CHECK: dxsa.dcl_input vpc<3, <x, y>>
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// CHECK: dxsa.dcl_index_range vpc<0>, 4
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// CHECK: dxsa.dcl_output_siv o<4, <x>>, <finalQuadUInsideTessFactor>
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// CHECK: dxsa.dcl_output_siv o<5, <x>>, <finalQuadVInsideTessFactor>
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// CHECK: dxsa.dcl_output o<4, <y>>
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// CHECK: dxsa.dcl_output o<5, <y>>
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// CHECK: dxsa.dcl_input vPrim<none>
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// CHECK: dxsa.mov o<4, <x>>, l(0x41400000)
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// CHECK: dxsa.mov o<5, <x>>, l(0x40C00000)
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// CHECK: dxsa.mov o<4, <y>>, l(0x0)
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// CHECK: dxsa.mov o<5, <y>>, l(0x0)
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‎mlir/test/Target/DXSA/asm/indexabletemp4.test‎

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// RUN: mlir-translate --import-dxsa-bin %S/inputs/indexabletemp4.shex | FileCheck %s
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// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py
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// CHECK-LABEL: dxsa.dcl_global_flags <refactoringAllowed>
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// CHECK: dxsa.dcl_constant_buffer <id = 0, size = 12>, <dynamicIndexed>
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// CHECK: dxsa.dcl_input_ps constant v<1, <x>>
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// CHECK: dxsa.dcl_input_ps constant v<1, <y>>
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// CHECK: dxsa.dcl_output o<0, <x>>
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// CHECK: dxsa.dcl_temps 1
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// CHECK: dxsa.dcl_indexable_temp x<0>[4], 2
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// CHECK: dxsa.mov r<0, <x>>, v<1, <x>>
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// CHECK: dxsa.mov x<[0, 0], <x>>, cb<[0, r<0, <x>>], vector, <x>>
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// CHECK: dxsa.mov x<[0, 1], <x>>, cb<[0, 4 + r<0, <x>>], vector, <x>>
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// CHECK: dxsa.mov r<0, <x>>, v<1, <y>>
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// CHECK: dxsa.mov x<[0, 1], <y>>, r<0, <x>>
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// CHECK: dxsa.mov o<0, <x>>, x<[0, 77 + x<[0, 1], <y>>], <x>>
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// CHECK: dxsa.ret
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‎mlir/test/Target/DXSA/asm/indexabletemp6.test‎

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// RUN: mlir-translate --import-dxsa-bin %S/inputs/indexabletemp6.shex | FileCheck %s
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// NOTE: Assertions have been autogenerated by utils/generate-test-checks.py
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// CHECK-LABEL: dxsa.dcl_global_flags <refactoringAllowed|enableMinimumPrecision>
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// CHECK: dxsa.dcl_constant_buffer <id = 0, size = 12>, <dynamicIndexed>
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// CHECK: dxsa.dcl_input_ps constant v<1, <x>>
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// CHECK: dxsa.dcl_input_ps constant v<1, <y>>
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// CHECK: dxsa.dcl_output o<0, min16f, <x>>
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// CHECK: dxsa.dcl_temps 1
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// CHECK: dxsa.dcl_indexable_temp x<0>[4]
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// CHECK: dxsa.mov r<0, <x>>, v<1, <x>>
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// CHECK: dxsa.mov x<[0, 0], <x>>, cb<[0, 4 + r<0, <x>>], vector, <x>>
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// CHECK: dxsa.mov r<0, <y>>, x<[0, 0], <x>>
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// CHECK: dxsa.mov x<[0, 0], min16f, <x>>, cb<[0, r<0, <x>>], vector, min16f, <x>>
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// CHECK: dxsa.mov x<[0, 1], min16f, <x>>, cb<[0, 4 + r<0, <x>>], vector, min16f, <x>>
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// CHECK: dxsa.mov r<0, <x>>, v<1, <y>>
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// CHECK: dxsa.add x<[0, r<0, <x>>], min16f, <x>>, x<[0, r<0, <x>>], min16f, <x>>, r<0, min16f, <y>>
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// CHECK: dxsa.mov o<0, min16f, <x>>, x<[0, r<0, <x>>], min16f, <x>>
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// CHECK: dxsa.ret
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‎mlir/test/Target/DXSA/asm/inputs/call2.shex‎

356 Bytes
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‎mlir/test/Target/DXSA/asm/inputs/cs3.shex‎

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‎mlir/test/Target/DXSA/asm/inputs/cyclecounter.shex‎

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‎mlir/test/Target/DXSA/asm/inputs/hs3.shex‎

1.27 KB
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